; -------------------------------------------------------------------------------- ; @Title: J721S2 On-Chip Peripherals ; @Props: Released ; @Author: CMO ; @Changelog: 2023-08-07 ; @Manufacturer: TI - Texas Instruments ; @Doc: Generated (Trace32 Version S.2023.08.000161593), based on : ; CCS 12.4.0 J721S2_TDA4VL.xml ; @Core: Cortex-A72, Cortex-R5F, C71X ; @Chip: TDA4AL88, TDA4AL88-CR5-MCU, TDA4AL88-CR5-MAIN, TDA4AL88-CM4-0, ; TDA4AL88-CM4-1, TDA4AL88-C71X, TDA4VE88, TDA4VE88-CR5-MCU, ; TDA4VE88-CR5-MAIN0, TDA4VE88-CR5-MAIN1, TDA4VE88-CM4-0, TDA4VE88-CM4-1, ; TDA4VE88-C71X, J721S2, J721S2-CR5-MCU, J721S2-CR5-MAIN0, ; J721S2-CR5-MAIN1, J721S2-CM4-0, J721S2-CM4-1, J721S2-C71X ; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perj721s2.per 17823 2024-04-26 11:44:52Z dorthofer $ sif (CPUFAMILY()=="ARM") sif (CORENAME()=="CORTEXA72") tree "Core Registers (Cortex-A72)" AUTOINDENT.ON center tree tree.open "AArch64" tree "ID Registers" rgroup.quad spr:0x30000++0x0 line.quad 0x00 "MIDR_EL1,Main ID Register" hexmask.quad.byte 0x00 24.--31. 1. "IMPL,Implementer code" bitfld.quad 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 16.--19. "ARCH, Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8" newline hexmask.quad.word 0x00 4.--15. 1. "PART,Primary Part Number" bitfld.quad 0x00 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.quad spr:0x33001++0x0 line.quad 0x00 "CTR_EL0,Cache Type Register" bitfld.quad 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.quad 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.quad 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.quad 0x00 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.quad 0x00 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." rgroup.quad spr:0x30005++0x00 line.quad 0x00 "MPIDR_EL1,Multiprocessor Affinity Register" bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor" newline bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,Implemented" hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" newline bitfld.quad 0x00 0.--1. "CPUID,CPU ID" "1,2,3,4" rgroup.quad spr:0x30006++0x0 line.quad 0x00 "REVIDR_EL1,Revision ID Register" rgroup.quad spr:0x30014++0x00 line.quad 0x00 "ID_MMFR0_EL1,Memory Model Feature Register 0" bitfld.quad 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.quad 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.quad 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Reserved,ACTLR/AIFSR/ADFSR,?..." newline bitfld.quad 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..." bitfld.quad 0x00 12.--15. "SL,Shareability levels" "Reserved,2 levels,?..." bitfld.quad 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..." newline bitfld.quad 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.quad 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.quad spr:0x30015++0x00 line.quad 0x00 "ID_MMFR1_EL1,Memory Model Feature Register 1" bitfld.quad 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,Not required,?..." bitfld.quad 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.quad 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." newline bitfld.quad 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.quad 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.quad 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.quad spr:0x30016++0x00 line.quad 0x00 "ID_MMFR2_EL1,Memory Model Feature Register 2" bitfld.quad 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..." bitfld.quad 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.quad 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.quad spr:0x30017++0x00 line.quad 0x00 "ID_MMFR3_EL1,Memory Model Feature Register 3" bitfld.quad 0x00 28.--31. "SS,Supersection support" "Supported,?..." bitfld.quad 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..." bitfld.quad 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,?..." newline bitfld.quad 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup.quad spr:0x30026++0x00 line.quad 0x00 "ID_MMFR4_EL1,ID_MMFR4_EL1" bitfld.quad 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented,Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" rgroup.quad spr:0x30070++0x00 line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0" bitfld.quad 0x00 28.--31. "4KB,4KB granule supported" "Supported,?..." bitfld.quad 0x00 24.--27. "64KB,64KB granule supported" "Supported,?..." bitfld.quad 0x00 20.--23. "16KB,16KB granule supported" "Not supported,?..." newline bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..." newline bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,Reserved,Reserved,44 bits/16 TB,?..." rgroup.quad spr:0x30020++0x00 line.quad 0x00 "ID_ISAR0_EL1,Instruction Set Attribute Register 0" bitfld.quad 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..." newline bitfld.quad 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..." rgroup.quad spr:0x30021++0x00 line.quad 0x00 "ID_ISAR1_EL1,Instruction Set Attribute Register 1" bitfld.quad 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..." rgroup.quad spr:0x30022++0x00 line.quad 0x00 "ID_ISAR2_EL1,Instruction Set Attribute Register 2" bitfld.quad 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.quad spr:0x30023++0x00 line.quad 0x00 "ID_ISAR3_EL1,Instruction Set Attribute Register 3" bitfld.quad 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..." bitfld.quad 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.quad spr:0x30024++0x00 line.quad 0x00 "ID_ISAR4_EL1,Instruction Set Attribute Register 4" bitfld.quad 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..." bitfld.quad 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..." bitfld.quad 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..." newline bitfld.quad 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.quad spr:0x30025++0x00 line.quad 0x00 "ID_ISAR5_EL1,Instruction Set Attribute Register 5" bitfld.quad 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..." bitfld.quad 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..." newline bitfld.quad 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..." rgroup.quad spr:0x30060++0x00 line.quad 0x00 "ID_AA64ISAR0_EL1,AArch64 Instruction Set Attribute Register 0" bitfld.quad 0x00 16.--19. "CRC32,CRC32" "Reserved,Implemented,?..." bitfld.quad 0x00 12.--15. "SHA2, SHA2 instructions are implemented" "Not implemented,Implemented,?..." bitfld.quad 0x00 8.--11. "SHA1, SHA1 instructions are implemented" "Not implemented,Implemented,?..." newline bitfld.quad 0x00 4.--7. "AES,AES instructions are implemented" "Not implemented,Reserved,Implemented,?..." rgroup.quad spr:0x30010++0x00 line.quad 0x00 "ID_PFR0_EL1,Processor Feature Register 0" bitfld.quad 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.quad spr:0x30011++0x00 line.quad 0x00 "ID_PFR1_EL1,Processor Feature Register 1" bitfld.quad 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..." newline bitfld.quad 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup.quad spr:0x30040++0x00 line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0" bitfld.quad 0x00 24.--27. "GIC,Support for the GIC System register interface" "Not supported,GICv3 supported,?..." bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" newline bitfld.quad 0x00 12.--15. "EL3H,EL3 exception handling" "Reserved,Reserved,Implemented,?..." bitfld.quad 0x00 8.--11. "EL2H,EL2 exception handling" "Reserved,Reserved,Implemented,?..." bitfld.quad 0x00 4.--7. "EL1H,EL1 exception handling" "Reserved,Reserved,Implemented,?..." newline bitfld.quad 0x00 0.--3. "EL0H,EL0 exception handling" "Reserved,Reserved,Implemented,?..." rgroup.quad spr:0x30012++0x00 line.quad 0x00 "ID_DFR0_EL1,Debug Feature Register 0" bitfld.quad 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,PMUv3,?..." bitfld.quad 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.quad 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.quad spr:0x30050++0x00 line.quad 0x00 "ID_AA64DFR0_EL1,AArch64 Debug Feature Register 0" bitfld.quad 0x00 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware minus 1" "Reserved,2,?..." bitfld.quad 0x00 20.--23. "WRPS,The number of watchpoints minus 1" "Reserved,Reserved,Reserved,4,?..." bitfld.quad 0x00 12.--15. "BRPS,The number of breakpoints minus 1" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." newline bitfld.quad 0x00 8.--11. "PMUVER,Performance Monitors extension version" "Reserved,PMUv3,?..." bitfld.quad 0x00 4.--7. "TRACEVER,Trace extension" "Not implemented,?..." bitfld.quad 0x00 0.--3. "DEBUGGER,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug v8-A,?..." rgroup.quad spr:0x339C6++0x0 line.quad 0x00 "PMCEID0_EL0,Common Event Identification Register 0" bitfld.quad 0x00 30. "CH,Chain" "Not implemented,Implemented" bitfld.quad 0x00 29. "BC,Bus cycle" "Not implemented,Implemented" bitfld.quad 0x00 28. "TW,Instruction architecturally executed condition check pass" "Not implemented,Implemented" newline bitfld.quad 0x00 27. "IS,Instruction speculatively executed" "Not implemented,Implemented" bitfld.quad 0x00 26. "ME,Local memory error" "Not implemented,Implemented" bitfld.quad 0x00 25. "DA,Bus access" "Not implemented,Implemented" newline bitfld.quad 0x00 24. "DC2W,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.quad 0x00 23. "DC2R,Level 2 data cache refill" "Not implemented,Implemented" bitfld.quad 0x00 22. "DC2A,Level 2 data cache access" "Not implemented,Implemented" newline bitfld.quad 0x00 21. "DC1W,Level 1 data cache write-back" "Not implemented,Implemented" bitfld.quad 0x00 20. "IC1A,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.quad 0x00 19. "MA,Data memory access" "Not implemented,Implemented" newline bitfld.quad 0x00 18. "BP,Predictable branch speculatively executed" "Not implemented,Implemented" bitfld.quad 0x00 17. "CC,Cycle" "Not implemented,Implemented" bitfld.quad 0x00 16. "BM,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" newline bitfld.quad 0x00 15. "UL,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" bitfld.quad 0x00 14. "BR,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.quad 0x00 13. "BI,Instruction architecturally executed immediate branch" "Not implemented,Implemented" newline bitfld.quad 0x00 12. "PW,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" bitfld.quad 0x00 11. "CW,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.quad 0x00 10. "ER,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" newline bitfld.quad 0x00 9. "ET,Exception taken" "Not implemented,Implemented" bitfld.quad 0x00 8. "IA,Instruction architecturally executed" "Not implemented,Implemented" bitfld.quad 0x00 7. "ST,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" newline bitfld.quad 0x00 6. "LD,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" bitfld.quad 0x00 5. "DT1R,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.quad 0x00 4. "DC1A,Level 1 data cache access" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "DC1R,Level 1 data cache refill" "Not implemented,Implemented" bitfld.quad 0x00 2. "IT1R,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.quad 0x00 1. "IC1R,Level 1 instruction cache refill" "Not implemented,Implemented" newline bitfld.quad 0x00 0. "SI,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" rgroup.quad spr:0x33007++0x00 line.quad 0x00 "DCZID_EL0,Data Cache Zero ID" bitfld.quad 0x00 4. "DZP,Prohibit the DC ZVA instruction" "Not prohibited,Prohibited" bitfld.quad 0x00 0.--3. "BS,Block Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." group.quad spr:0x33D02++0x00 line.quad 0x00 "TPIDR_EL0,Thread Pointer/ID Register" group.quad spr:0x30D04++0x00 line.quad 0x00 "TPIDR_EL1,Thread Pointer/ID Register" group.quad spr:0x34D02++0x00 line.quad 0x00 "TPIDR_EL2,Thread Pointer/ID Register" group.quad spr:0x36D02++0x00 line.quad 0x00 "TPIDR_EL3,Thread Pointer/ID Register" group.quad spr:0x33D03++0x00 line.quad 0x00 "TPIDRRO_EL0,Thread Pointer/ID Register" tree.end tree "System Control and Configuration" group.quad spr:0x36111++0x00 line.quad 0x00 "SDER32_EL3,Secure Debug Enable Register" bitfld.quad 0x00 1. "SUNIDEN,Enable non-invasive debug features in Secure User mode" "Disabled,Enabled" bitfld.quad 0x00 0. "SUIDEN,Enable debug exceptions in Secure User mode" "Disabled,Enabled" group.quad spr:0x30100++0x0 line.quad 0x00 "SCTLR_EL1,Control Register (EL1)" bitfld.quad 0x00 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.quad 0x00 24. "E0E,Endianness of explicit data access at EL0" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 18. "NTWE,Not trap WFE" "No,Yes" bitfld.quad 0x00 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.quad 0x00 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled" bitfld.quad 0x00 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 9. "UMA,User Mask Access" "Disabled,Enabled" newline bitfld.quad 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.quad 0x00 7. "ITD,IT instruction disable" "No,Yes" newline bitfld.quad 0x00 6. "THEE,Thumb EE enable" "Disabled,Enabled" bitfld.quad 0x00 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.quad 0x00 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34100++0x0 line.quad 0x00 "SCTLR_EL2,Control Register (EL2)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x36100++0x0 line.quad 0x00 "SCTLR_EL3,Control Register (EL3)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x31F20++0x00 line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register" bitfld.quad 0x00 63. "FPMRCGEA,Force processor RCG enables active" "Not forced,Forced" bitfld.quad 0x00 62. "FPNMRCGEA,Force processor non-memory-system RCG enables active" "Not forced,Forced" newline bitfld.quad 0x00 61. "FPDIERCGEA,Force processor Decode and Integer Execute idle RCG enables active" "Not forced,Forced" bitfld.quad 0x00 60. "FPDRCGEA,Force processor Dispatch idle RCG enables active" "Not forced,Forced" newline bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes" bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes" newline bitfld.quad 0x00 57. "TA,Treat DMB st/st and DMB ld/allas DMB all/all" "Disabled,Enabled" bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes" newline bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes" bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled" newline bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled" bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes" newline bitfld.quad 0x00 51. "ECDAFEMP,Enable contention detection and fast exclusive monitor path" "Disabled,Enabled" bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes" newline bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes" bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes" newline bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes" bitfld.quad 0x00 46. "DML1DTLBM,Disable multiple outstanding L1 Data TLB misses and L2 TLB hit under miss" "No,Yes" newline bitfld.quad 0x00 45. "Dl1DCWT,Disable L1-DCache way tracker" "No,Yes" bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled" newline bitfld.quad 0x00 43. "DVABHWPREF,Disable the Load/Store hardware prefetcher from using VA to cross page boundaries" "No,Yes" bitfld.quad 0x00 42. "DPREFREQRUT,Disable prefetch requests from ReadUnique transactions" "No,Yes" newline bitfld.quad 0x00 41. "ESHWSHAEP,Enables snoop hazard while waiting for second half of atomic exclusive pair" "Disabled,Enabled" bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes" newline bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced" bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes" newline bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced" bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes" newline bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes" bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes" newline bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled" bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced" newline bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled" bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled" newline bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled" newline bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced" bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced" newline bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes" bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes" newline bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes" bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes" newline bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes" bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled" newline bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced" bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced" newline bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled" bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled" newline bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled" bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced" newline bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes" bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled" newline bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled" bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled" newline bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes" bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes" newline bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes" bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled" group.quad spr:0x31F21++0x00 line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register" bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes" bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 requests,1 request,2 requests,3 requests" newline bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "16 requests,18 requests,20 requests,22 requests" bitfld.quad 0x00 6. "SMPEN,Enables the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster" "Disabled,Enabled" newline bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad spr:0x31F22++0x00 line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,Indicates the index address of the first memory error" group.quad spr:0x34101++0x0 line.quad 0x00 "ACTLR_EL2,Auxiliary Control Register" bitfld.quad 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" group.quad spr:0x36101++0x0 line.quad 0x00 "ACTLR_EL3,Auxiliary Control Register" bitfld.quad 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" group.quad spr:0x30102++0x00 line.quad 0x00 "CPACR_EL1,Architectural Feature Access Control Register" bitfld.quad 0x00 20.--21. "FPEN,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution to trap to EL1 when executed from EL0 or EL1" "Trap EL0/EL1,Trap EL0,Trap EL0/EL1,No trap" group.quad spr:0x36110++0x0 line.quad 0x00 "SCR_EL3,Secure Configuration Register" bitfld.quad 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped" bitfld.quad 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped" newline bitfld.quad 0x00 11. "ST,Enable secure EL1 access" "Disabled,Enabled" bitfld.quad 0x00 10. "RW,Register width control for lower exception levels" "AArch32,AArch64" newline bitfld.quad 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.quad 0x00 8. "HCE,Hypervisor Call enable" "Disabled,Enabled" newline bitfld.quad 0x00 7. "SMD,Secure Monitor Call disable" "No,Yes" bitfld.quad 0x00 3. "EA,External Abort and SError Interrupt Routing" "Not to EL3,To EL3" newline bitfld.quad 0x00 2. "FIQ,Physical FIQ Routing" "Not to EL3,To EL3" bitfld.quad 0x00 1. "IRQ,Physical IRQ Routing" "Not to EL3,To EL3" newline bitfld.quad 0x00 0. "NS,Secure mode " "Secure,Non-secure" group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes" newline bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit" bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" newline bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled" bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled" newline bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" newline bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" newline bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending" bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending" newline bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending" bitfld.quad 0x00 5. "AMO,Asynchronous abort and error interrupt routing" "Disabled,Enabled" newline bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled" bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled" newline bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled" newline bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled" group.quad spr:0x30510++0x00 line.quad 0x00 "AFSR0_EL1,Auxiliary Fault Status Registers 0 (EL1)" group.quad spr:0x30511++0x00 line.quad 0x00 "AFSR1_EL1,Auxiliary Fault Status Registers 1 (EL1)" group.quad spr:0x34510++0x00 line.quad 0x00 "AFSR0_EL2,Auxiliary Fault Status Registers 0 (EL2)" group.quad spr:0x34511++0x00 line.quad 0x00 "AFSR1_EL2,Auxiliary Fault Status Registers 1 (EL2)" group.quad spr:0x36510++0x00 line.quad 0x00 "AFSR0_EL3,Auxiliary Fault Status Registers 0 (EL3)" group.quad spr:0x36511++0x00 line.quad 0x00 "AFSR1_EL3,Auxiliary Fault Status Registers 1 (EL3)" tree.open "Exception Syndrome Registers" if (((per.q(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((per.q(spr:0x30520))&0xFC000000)==0x04000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((per.q(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x30520))&0xFC000000)==0x18000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x30520))&0xFC000000)==0x1C000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((per.q(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.q(spr:0x30520))&0xFC000000)==0x60000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3" newline bitfld.quad 0x00 17.--19. "OP2,Op2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OP1,Op1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..." elif (((per.q(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.q(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.q(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((per.q(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((per.q(spr:0x30520))&0xFD000000)==0xBD000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 15. "UNASE,Unattributable System Error" "Attributable,Unattributable" newline bitfld.quad 0x00 14. "UNCSE,Uncontainable System Error" "Containable,Uncontainable" bitfld.quad 0x00 0.--1. "SES,System Error Source" "Decode,ECC,Slave," elif (((per.q(spr:0x30520))&0xFD000000)==0xBC000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((per.q(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.q(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.q(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.q(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((per.q(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((per.q(spr:0x34520))&0xFC000000)==0x04000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((per.q(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x34520))&0xFC000000)==0x18000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x34520))&0xFC000000)==0x1C000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((per.q(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.q(spr:0x34520))&0xFC000000)==0x5C000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((per.q(spr:0x34520))&0xFC000000)==0x60000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3" newline bitfld.quad 0x00 17.--19. "OP2,Op2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OP1,Op1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((per.q(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.q(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.q(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((per.q(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((per.q(spr:0x34520))&0xFD000000)==0xBD000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.quad.tbyte 0x00 0.--23. 1. "IS,Additional information about the SError interrupt" elif (((per.q(spr:0x34520))&0xFD000000)==0xBC000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((per.q(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.q(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.q(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.q(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((per.q(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((per.q(spr:0x36520))&0xFC000000)==0x04000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((per.q(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x36520))&0xFC000000)==0x18000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x36520))&0xFC000000)==0x1C000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((per.q(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.q(spr:0x36520))&0xFC000000)==0x5C000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((per.q(spr:0x36520))&0xFC000000)==0x60000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3" newline bitfld.quad 0x00 17.--19. "OP2,Op2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OP1,Op1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x36520))&0xFC000000)==0x7C000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.long 0x00 0.--24. 1. "IMPL_DEF,Implementation defined" elif (((per.q(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..." elif (((per.q(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.q(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.q(spr:0x36520))&0xFC800000)==0xB0800000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((per.q(spr:0x36520))&0xFC800000)==0xB0000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((per.q(spr:0x36520))&0xFD000000)==0xBD000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.quad.tbyte 0x00 0.--23. 1. "IS,Additional information about the SError interrupt" elif (((per.q(spr:0x36520))&0xFD000000)==0xBC000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((per.q(spr:0x36520))&0xFC000000)==0xF0000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif tree.end newline if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External abort type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Large physical address extension" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status bits" "Address size/0th level,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External abort type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Large physical address extension" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS[3:0],Fault Status bits" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external,Reserved,Async. parity/on memory access,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif group.quad spr:0x30600++0x00 line.quad 0x00 "FAR_EL1,Fault Address Register (EL1)" group.quad spr:0x34600++0x00 line.quad 0x00 "FAR_EL2,Fault Address Register (EL2)" group.quad spr:0x36600++0x00 line.quad 0x00 "FAR_EL3,Fault Address Register (EL3)" group.quad spr:0x34604++0x00 line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register" hexmask.quad 0x00 4.--39. 0x10 "FIPA,Faulting intermediate physical address" group.quad spr:0x30C00++0x00 line.quad 0x00 "VBAR_EL1,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x8 "VBA,Base address of the exception vectors for exceptions taken in this exception level" group.quad spr:0x34C00++0x00 line.quad 0x00 "VBAR_EL2,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x8 "VBA,Base address of the exception vectors for exceptions taken in this exception level" group.quad spr:0x36C00++0x00 line.quad 0x00 "VBAR_EL3,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x8 "VBA,Base address of the exception vectors for exceptions taken in this exception level" rgroup.quad spr:0x30C10++0x00 line.quad 0x00 "ISR_EL1,Interrupt Status Register" bitfld.quad 0x00 8. "A,External abort pending flag" "Not pending,Pending" bitfld.quad 0x00 7. "I,Interrupt pending flag" "Not pending,Pending" bitfld.quad 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending" group.quad spr:0x36C02++0x00 line.quad 0x00 "RMR_EL3,Reset Management Register" bitfld.quad 0x00 1. "RR,Reset Request" "Not requested,Requested" bitfld.quad 0x00 0. "AA64,Determines which execution state the processor boots into after a warmreset" "AArch32,AArch64" rgroup.quad spr:0x36C01++0x00 line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register" hexmask.quad 0x00 2.--43. 0x4 "RVBA,Reset Vector Base Address" rgroup.quad spr:0x31F30++0x00 line.quad 0x00 "CBAR_EL1,Configuration Base Address Register" hexmask.quad.long 0x00 18.--43. 1. "PERIPHBASE[43:18],Periphbase[43:18]" group.quad spr:0x30D01++0x00 line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register" group.quad spr:0x33D02++0x00 line.quad 0x00 "TPIDR_EL0,Software Thread ID registers" group.quad spr:0x33D03++0x00 line.quad 0x00 "TPIDRRO_EL0,Software Thread ID registers" group.quad spr:0x30D04++0x00 line.quad 0x00 "TPIDR_EL1,Software Thread ID registers" group.quad spr:0x34D02++0x00 line.quad 0x00 "TPIDR_EL2,Software Thread ID registers" group.quad spr:0x36D02++0x00 line.quad 0x00 "TPIDR_EL3,Software Thread ID registers" tree.end tree "Memory Management Unit" group.quad spr:0x30100++0x0 line.quad 0x00 "SCTLR_EL1,Control Register (EL1)" bitfld.quad 0x00 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled" bitfld.quad 0x00 25. "EE,Exception endianess" "Little,Big" newline bitfld.quad 0x00 24. "E0E,Endianness of explicit data access at EL0" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 18. "NTWE,Not trap WFE" "No,Yes" bitfld.quad 0x00 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.quad 0x00 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled" bitfld.quad 0x00 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 9. "UMA,User Mask Access" "Disabled,Enabled" newline bitfld.quad 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.quad 0x00 7. "ITD,IT instruction disable" "No,Yes" newline bitfld.quad 0x00 6. "THEE,Thumb EE enable" "Disabled,Enabled" bitfld.quad 0x00 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.quad 0x00 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34100++0x0 line.quad 0x00 "SCTLR_EL2,Control Register (EL2)" bitfld.quad 0x00 25. "EE,Exception endianess" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x36100++0x0 line.quad 0x00 "SCTLR_EL3,Control Register (EL3)" bitfld.quad 0x00 25. "EE,Exception endianess" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes" newline bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit" bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" newline bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled" bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled" newline bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" newline bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade - determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" newline bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort" "No pending,Pending" bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending" newline bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending" bitfld.quad 0x00 5. "AMO,Asynchronous abort and error interrupt routing" "Disabled,Enabled" newline bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled" bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled" newline bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled" newline bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled" group.quad spr:0x30200++0x00 line.quad 0x00 "TTBR0_EL1,Translation Table Base Register 0 (EL1)" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad spr:0x30201++0x00 line.quad 0x00 "TTBR1_EL1,Translation Table Base Register 1 (EL1)" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad spr:0x30202++0x00 line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)" bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored" bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored" newline bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit" bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,Reserved,Reserved" newline bitfld.quad 0x00 30. "TG1,TTBR1_EL1 granule size" "4 KB,64 KB" bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled" bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1" newline bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.quad 0x00 14. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB" newline bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.quad spr:0x34200++0x00 line.quad 0x00 "TTBR0_EL2,Translation Table Base Register 0 (EL2)" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad spr:0x34202++0x00 line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,Reserved,Reserved,Reserved,Reserved,Reserved" newline bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB,16 KB,Reserved" bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associatedwith translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memoryregion addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.quad spr:0x36200++0x00 line.quad 0x00 "TTBR0_EL3,Translation Table Base Register 0 (EL3)" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad spr:0x36202++0x00 line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,Reserved,Reserved,Reserved,Reserved,Reserved" newline bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL3 granule size" "4 KB,64 KB,16 KB,Reserved" bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associatedwith translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memoryregion addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.quad spr:0x34300++0x00 line.quad 0x00 "DACR32_EL2,Domain Access Control Register" bitfld.quad 0x00 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager" if (((per.q(spr:0x30740))&0xF000000000000001)==0x0000000000000000) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Device-nGnRnE,Reserved,Reserved,Reserved,Device,?..." newline hexmask.quad 0x00 12.--43. 0x1000 "PA[43:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif ((((per.q(spr:0x30740))&0x01)==0x00)&&(((per.q(spr:0x30740))&0xF000000000000000)==(0x1000000000000000||0x2000000000000000||0x3000000000000000||0x5000000000000000||0x6000000000000000||0x7000000000000000))) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" newline hexmask.quad 0x00 12.--43. 0x1000 "PA[43:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif (((per.q(spr:0x30740))&0x01)==0x00) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Reserved,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" newline hexmask.quad 0x00 12.--47. 0x1000 "PA[47:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" else group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" newline bitfld.quad 0x00 9. "S,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2" bitfld.quad 0x00 8. "PTW,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes" newline bitfld.quad 0x00 1.--6. "FST,Fault Status Field" "TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Synchronous external abort,Reserved,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,Synchronous parity error on memory access,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/1st level,Synchronous parity error on memory access on translation table walk/2nd level,Synchronous parity error on memory access on translation table walk/3rd level,Reserved,Alignment fault,Debug event,?..." newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" endif tree.open "Memory Attribute Indirection Registers" group.quad spr:0x30A20++0x00 line.quad 0x00 "MAIR_EL1,Memory Attribute Indirection Register (EL1)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.quad spr:0x34A20++0x00 line.quad 0x00 "MAIR_EL2,Memory Attribute Indirection Register (EL2)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.quad spr:0x36A20++0x00 line.quad 0x00 "MAIR_EL3,Memory Attribute Indirection Register (EL3)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" tree.end newline group.quad spr:0x30D01++0x00 line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register" tree.end tree "Virtualization Extensions" group.quad spr:0x34000++0x0 line.quad 0x00 "VPIDR_EL2,Virtualization Processor ID Register" group.quad spr:0x34005++0x00 line.quad 0x00 "VMPIDR_EL2,Virtualization Multiprocessor ID Register" hexmask.quad.long 0x00 0.--31. 1. "VMPIDR_EL2,MPIDR value returned by Non-secure EL1 reads of the MPIDR_EL1" group.quad spr:0x34100++0x0 line.quad 0x00 "SCTLR_EL2,Control Register (EL2)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" newline bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 33. "ID,Stage 2 instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 data cache disable" "No,Yes" bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,AArch64" newline bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" bitfld.quad 0x00 28. "TDZ,Traps DC ZVA instruction" "Disabled,Enabled" bitfld.quad 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled" newline bitfld.quad 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled" bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled" newline bitfld.quad 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled" bitfld.quad 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled" bitfld.quad 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled" newline bitfld.quad 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled" bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" newline bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3" bitfld.quad 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled" bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort" "Not aborted,Aborted" newline bitfld.quad 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 5. "AMO,A-bit Mask Override" "Not routed,Routed" newline bitfld.quad 0x00 4. "IMO,I-bit Mask Override" "Not routed,Routed" bitfld.quad 0x00 3. "FMO,F-bit Mask Override" "Not routed,Routed" bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" newline bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override" bitfld.quad 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled" group.quad spr:0x34111++0x00 line.quad 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)" bitfld.quad 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid" bitfld.quad 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" bitfld.quad 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" newline bitfld.quad 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid" bitfld.quad 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.quad 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" newline bitfld.quad 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.quad 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.quad spr:0x36131++0x00 line.quad 0x00 "MDCR_EL3,Hypervisor Debug Control Register (EL3)" bitfld.quad 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes" bitfld.quad 0x00 20. "EDAD,External debugger access to breakpoint and watchpointregisters disabled" "No,Yes" bitfld.quad 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled" newline bitfld.quad 0x00 16. "SDD,AArch64 secure debug disable" "No,Yes" bitfld.quad 0x00 14.--15. "SPD32,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled" bitfld.quad 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" newline bitfld.quad 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" bitfld.quad 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" group.quad spr:0x34112++0x00 line.quad 0x00 "CPTR_EL2,Architectural Feature Trap Register (EL2)" bitfld.quad 0x00 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.quad 0x00 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped" group.quad spr:0x36112++0x00 line.quad 0x00 "CPTR_EL3,Architectural Feature Trap Register (EL3)" bitfld.quad 0x00 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.quad 0x00 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped" group.quad spr:0x34113++0x00 line.quad 0x00 "HSTR_EL2,Hypervisor System Trap Register" bitfld.quad 0x00 16. "TTEE,Trap T32EE" "Disabled,Enabled" bitfld.quad 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "No effect,Trap" bitfld.quad 0x00 13. "T13,Trap to Hypervisor mode Non-secure priv 13" "No effect,Trap" newline bitfld.quad 0x00 12. "T12,Trap to Hypervisor mode Non-secure priv 12" "No effect,Trap" bitfld.quad 0x00 11. "T11,Trap to Hypervisor mode Non-secure priv 11" "No effect,Trap" bitfld.quad 0x00 10. "T10,Trap to Hypervisor mode Non-secure priv 10" "No effect,Trap" newline bitfld.quad 0x00 9. "T9,Trap to Hypervisor mode Non-secure priv 9" "No effect,Trap" bitfld.quad 0x00 8. "T8,Trap to Hypervisor mode Non-secure priv 8" "No effect,Trap" bitfld.quad 0x00 7. "T7,Trap to Hypervisor mode Non-secure priv 7" "No effect,Trap" newline bitfld.quad 0x00 6. "T6,Trap to Hypervisor mode Non-secure priv 6" "No effect,Trap" bitfld.quad 0x00 5. "T5,Trap to Hypervisor mode Non-secure priv 5" "No effect,Trap" bitfld.quad 0x00 4. "T4,Trap to Hypervisor mode Non-secure priv 4" "No effect,Trap" newline bitfld.quad 0x00 3. "T3,Trap to Hypervisor mode Non-secure priv 3" "No effect,Trap" bitfld.quad 0x00 2. "T2,Trap to Hypervisor mode Non-secure priv 2" "No effect,Trap" bitfld.quad 0x00 1. "T1,Trap to Hypervisor mode Non-secure priv 1" "No effect,Trap" newline bitfld.quad 0x00 0. "T0,Trap to Hypervisor mode Non-secure priv 0" "No effect,Trap" group.quad spr:0x34210++0x00 line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,VMID for the translation table" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" if (((per.q(spr:0x34212))&0xC000)==0x0000) group.quad spr:0x34212++0x00 line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register" bitfld.quad 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,42 bits/4TB,44 bits/16TB,48 bits/256TB,?..." bitfld.quad 0x00 14.--15. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB,16 KB,?..." bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "Non-shareable,Outer Shareable,Inner Shareable,?..." newline bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "Normal/Non-cacheable,Normal/Write-Back Write-Allocate,Normal/Write-Through,Normal/Write-Back no Write-Allocate" bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Normal/Non-cacheable,Normal/Write-Back Write-Allocate,Normal/Write-Through,Normal/Write-Back no Write-Allocate" bitfld.quad 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "Level 2,Level 1,Level 0,?..." newline bitfld.quad 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.quad spr:0x34212++0x00 line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register" bitfld.quad 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,42 bits/4TB,44 bits/16TB,48 bits/256TB,?..." bitfld.quad 0x00 14.--15. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB,16 KB,?..." bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "Non-shareable,Outer Shareable,Inner Shareable,?..." newline bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "Normal/Non-cacheable,Normal/Write-Back Write-Allocate,Normal/Write-Through,Normal/Write-Back no Write-Allocate" bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Normal/Non-cacheable,Normal/Write-Back Write-Allocate,Normal/Write-Through,Normal/Write-Back no Write-Allocate" bitfld.quad 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "Level 3,Level 2,Level 1,?..." newline bitfld.quad 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad spr:0x30600++0x00 line.quad 0x00 "FAR_EL1,Fault Address Register (EL1)" group.quad spr:0x34600++0x00 line.quad 0x00 "FAR_EL2,Fault Address Register (EL2)" group.quad spr:0x36600++0x00 line.quad 0x00 "FAR_EL3,Fault Address Register (EL3)" group.quad spr:0x34604++0x00 line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register" hexmask.quad 0x00 4.--39. 0x10 "FIPA,Faulting intermediate physical address" tree.end tree "Cache Control and Configuration" rgroup.quad spr:0x33001++0x00 line.quad 0x00 "CTR_EL0,CTR_EL0" bitfld.quad 0x0 29.--31. "FORMAT,Format" "Reserved,Reserved,Reserved,Reserved,ARMv7,?..." bitfld.quad 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.quad 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.quad 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.quad 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,Physical" bitfld.quad 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,8 words,16 words,?..." group.quad spr:0x32000++0x0 line.quad 0x00 "CSSELR_EL1,Cache Size Selection Register" bitfld.quad 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..." bitfld.quad 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction" rgroup.quad spr:0x31001++0x0 line.quad 0x00 "CLIDR_EL1,Cache Level ID Register" bitfld.quad 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.quad 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..." bitfld.quad 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..." newline bitfld.quad 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..." bitfld.quad 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..." bitfld.quad 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..." newline bitfld.quad 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..." bitfld.quad 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.quad 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.quad 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate,?..." rgroup.quad spr:0x31000++0x0 line.quad 0x00 "CCSIDR_EL1,Current Cache Size ID Register" bitfld.quad 0x00 31. "WT,Write-Through" "Not Supported,Supported" bitfld.quad 0x00 30. "WB,Write-Back" "Not Supported,Supported" bitfld.quad 0x00 29. "RA,Read-Allocate" "Not Supported,Supported" newline bitfld.quad 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" hexmask.quad.word 0x00 13.--27. 1. 1. "SETS,Number of Sets" hexmask.quad.word 0x00 3.--12. 1. 1. "ASSOC,Associativity" newline bitfld.quad 0x00 0.--2. "LSIZE,Line Size" "16 bytes,32bytes,64 bytes,128 bytes,?..." tree "Level 1 memory system" group.quad spr:0x30F10++0x00 line.quad 0x00 "DL1DATA0_EL1,Data L1 Data 0 Register" group.quad spr:0x30F11++0x00 line.quad 0x00 "DL1DATA1_EL1,Data L1 Data 1 Register" group.quad spr:0x30F12++0x00 line.quad 0x00 "DL1DATA2_EL1,Data L1 Data 2 Register" group.quad spr:0x30F13++0x00 line.quad 0x00 "DL1DATA3_EL1,Data L1 Data 3 Register" group.quad spr:0x30F14++0x00 line.quad 0x00 "DL1DATA4_EL1,Data L1 Data 3 Register" group.quad spr:0x30F00++0x00 line.quad 0x00 "IL1DATA0_EL1,Instruction L1 Data 0 Register" group.quad spr:0x30F01++0x00 line.quad 0x00 "IL1DATA1_EL1,Instruction L1 Data 1 Register" group.quad spr:0x30F02++0x00 line.quad 0x00 "IL1DATA2_EL1,Instruction L1 Data 2 Register" group.quad spr:0x30F03++0x00 line.quad 0x00 "IL1DATA3_EL1,Instruction L1 Data 3 Register" tree.end tree "Level 2 memory system" group.quad spr:0x31B02++0x0 line.quad 0x00 "L2CTLR_EL1,L2 Control Register" bitfld.quad 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "Reset,No reset" bitfld.quad 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4" rbitfld.quad 0x00 23. "L2CP,L2 cache ECC protection" "Not supported,Supported" newline rbitfld.quad 0x00 22. "L1CECCPP,L1 Cache ECC and Parity protection" "Not supported,Supported" bitfld.quad 0x00 21. "ECCPPEN,ECC and parity enable" "Disabled,Enabled" bitfld.quad 0x00 20. "DIECCE,Data inline ECC enable" "Disabled,Enabled" newline rbitfld.quad 0x00 13. "L2AS,L2 arbitration slice" "Not present,Present" rbitfld.quad 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not present,Present" rbitfld.quad 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not present,1 present,2 present,?..." newline bitfld.quad 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle" bitfld.quad 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles" rbitfld.quad 0x00 5. "DRAMIL,L2 data RAM input latency" "0 cycle,1 cycle" newline bitfld.quad 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,6 cycles,6 cycles" group.quad spr:0x31B03++0x0 line.quad 0x00 "L2ECTLR_EL1,L2 Extended Control Register" bitfld.quad 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.quad 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" bitfld.quad 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad spr:0x31F00++0x00 line.quad 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register" bitfld.quad 0x00 30.--31. "L2PLRUIP,Select the L2 PLRU insertion point" "MRU/LRU,MRU,3/4 LRU,LRU" bitfld.quad 0x00 29. "L2RPLCPOL,Select the L2 cache replacement policy" "PLRU,Pseudo random" bitfld.quad 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled" newline bitfld.quad 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled" bitfld.quad 0x00 26. "FL2GICRCGEA,Force L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced" bitfld.quad 0x00 25. "ESIAA,Enable single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled" newline bitfld.quad 0x00 24. "L2PLRUMD,Disable PLRU dynamic insertion and update policy" "No,Yes" bitfld.quad 0x00 23. "DACPMUWLUT,Disable ACP MakeUnique and WriteLineUnique transactions" "No,Yes" bitfld.quad 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes" newline bitfld.quad 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit" bitfld.quad 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes" bitfld.quad 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled" newline bitfld.quad 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes" bitfld.quad 0x00 14. "EUCE,Enable UniqueClean evictions with data" "Disabled,Enabled" bitfld.quad 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes" newline bitfld.quad 0x00 12. "DPSHO,Disable set hazard optimization against prefetch entries" "No,Yes" bitfld.quad 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes" bitfld.quad 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes" newline bitfld.quad 0x00 9. "DWHOBBRRQ,Disable set/way hazard optimization on back to back reads from the same CPU targeting the same set" "No,Yes" bitfld.quad 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes" bitfld.quad 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled" newline bitfld.quad 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes" bitfld.quad 0x00 5. "DSWHOWWM,Disables set/way hazard optimization for WBNA/WT memory" "No,Yes" bitfld.quad 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled" newline bitfld.quad 0x00 3. "DCEPTE,Disable clean/evict push to external" "No,Yes" bitfld.quad 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited" bitfld.quad 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled" newline bitfld.quad 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes" group.quad spr:0x31F23++0x00 line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index" tree.end tree.end tree "System Performance Monitor" group.quad spr:0x339C0++0x00 line.quad 0x00 "PMCR_EL0,Performance Monitor Control Register" hexmask.quad.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.quad.byte 0x00 16.--23. 1. "IDCODE,Identification code" rbitfld.quad 0x00 11.--15. "N,Number of counters implemented" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." bitfld.quad 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled" newline bitfld.quad 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes" bitfld.quad 0x00 4. "X,Export Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "D,Clock Divider" "Every cycle,64th cycle" bitfld.quad 0x00 2. "C,Clock Counter Reset" "No reset,Reset" newline bitfld.quad 0x00 1. "P,Performance Counter Reset" "No reset,Reset" bitfld.quad 0x00 0. "E,All Counters Enable" "Disabled,Enabled" group.quad spr:0x339C1++0x00 line.quad 0x00 "PMCNTENSET_EL0,Count Enable Set Register " bitfld.quad 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" newline bitfld.quad 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled" bitfld.quad 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled" bitfld.quad 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled" newline bitfld.quad 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled" bitfld.quad 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled" bitfld.quad 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled" group.quad spr:0x339C2++0x00 line.quad 0x00 "PMCNTENCLR_EL0,Count Enable Clear Register" bitfld.quad 0x00 31. "C,PMCCNTR enable" "Disabled/No effect,Enabled/Disable" newline eventfld.long 0x00 5. "P5,Event Counter 5 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 4. "P4,Event Counter 4 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 3. "P3,Event Counter 3 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.long 0x00 2. "P2,Event Counter 2 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 1. "P1,Event Counter 1 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 0. "P0,Event Counter 0 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" group.quad spr:0x339C3++0x00 line.quad 0x00 "PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register" bitfld.quad 0x00 31. "C,PMCCNTR overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" newline eventfld.long 0x00 5. "P5,Event Counter 5 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 4. "P4,Event Counter 4 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 3. "P3,Event Counter 3 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" newline eventfld.long 0x00 2. "P2,Event Counter 2 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 1. "P1,Event Counter 1 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 0. "P0,Event Counter 0 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" wgroup.quad spr:0x339C4++0x00 line.quad 0x00 "PMSWINC_EL0,Performance Monitors Software Increment Register" bitfld.quad 0x00 5. "P5,Increment PMN5" "No action,Increment" bitfld.quad 0x00 4. "P4,Increment PMN4" "No action,Increment" bitfld.quad 0x00 3. "P3,Increment PMN3" "No action,Increment" newline bitfld.quad 0x00 2. "P2,Increment PMN2" "No action,Increment" bitfld.quad 0x00 1. "P1,Increment PMN1" "No action,Increment" bitfld.quad 0x00 0. "P0,Increment PMN0" "No action,Increment" group.quad spr:0x339C5++0x00 line.quad 0x00 "PMSELR_EL0,Performance Monitor Select Register" bitfld.quad 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,%d..." tree.open "Common Event Identification Registers" group.quad spr:0x339c6++0x00 line.quad 0x00 "PMCEID0_EL0,Common Event Identification Register 0" bitfld.quad 0x00 30. "CH,Chain" "Not implemented,Implemented" newline bitfld.quad 0x00 29. "BC,Bus cycle" "Not implemented,Implemented" bitfld.quad 0x00 28. "TW,Instruction architecturally executed condition check pass" "Not implemented,Implemented" bitfld.quad 0x00 27. "IS,Instruction speculatively executed" "Not implemented,Implemented" newline bitfld.quad 0x00 26. "ME,Local memory error" "Not implemented,Implemented" bitfld.quad 0x00 25. "BA,Bus access" "Not implemented,Implemented" bitfld.quad 0x00 24. "DC2W,Level 2 data cache write-back" "Not implemented,Implemented" newline bitfld.quad 0x00 23. "DC2R,Level 2 data cache refill" "Not implemented,Implemented" bitfld.quad 0x00 22. "DC2A,Level 2 data cache access" "Not implemented,Implemented" bitfld.quad 0x00 21. "DC1W,Level 1 data cache write-back" "Not implemented,Implemented" newline bitfld.quad 0x00 20. "IC1A,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.quad 0x00 19. "MA,Data memory access" "Not implemented,Implemented" bitfld.quad 0x00 18. "BP,Predictable branch speculatively executed" "Not implemented,Implemented" newline bitfld.quad 0x00 17. "CC,Cycle" "Not implemented,Implemented" bitfld.quad 0x00 16. "BM,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" bitfld.quad 0x00 15. "UL,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" newline bitfld.quad 0x00 14. "BR,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.quad 0x00 13. "BI,Instruction architecturally executed immediate branch" "Not implemented,Implemented" bitfld.quad 0x00 12. "PW,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" newline bitfld.quad 0x00 11. "CW,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.quad 0x00 10. "ER,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" bitfld.quad 0x00 9. "ET,Exception taken" "Not implemented,Implemented" newline bitfld.quad 0x00 8. "IA,Instruction architecturally executed" "Not implemented,Implemented" bitfld.quad 0x00 7. "ST,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" bitfld.quad 0x00 6. "LD,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "DT1R,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.quad 0x00 4. "DC1A,Level 1 data cache access" "Not implemented,Implemented" bitfld.quad 0x00 3. "DC1R,Level 1 data cache refill" "Not implemented,Implemented" newline bitfld.quad 0x00 2. "IT1R,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.quad 0x00 1. "IC1R,Level 1 instruction cache refill" "Not implemented,Implemented" bitfld.quad 0x00 0. "SI,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" tree.end newline group.quad spr:0x339D0++0x00 line.quad 0x00 "PMCCNTR_EL0,Performance Monitor Cycle Count Register" group.quad spr:0x339D1++0x00 line.quad 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register" group.quad spr:0x339D2++0x00 line.quad 0x00 "PMXEVCNTR_EL0,Performance Monitor Event Count Register" group.quad spr:0x339E0++0x00 line.quad 0x00 "PMUSERENR_EL0,Performance Monitor User Enable Register" bitfld.quad 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.quad 0x00 2. "EC,Cycle counter read enable" "Disabled,Enabled" bitfld.quad 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" newline bitfld.quad 0x00 0. "EN,User mode access enable" "Disabled,Enabled" group.quad spr:0x309E1++0x00 line.quad 0x00 "PMINTENSET_EL1,Performance Monitor Interrupt Enable Set" bitfld.quad 0x00 31. "C,Cycle counter Overflow Interrupt clear" "Disabled,Enabled" newline bitfld.quad 0x00 6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.quad spr:0x309E2++0x00 line.quad 0x00 "PMINTENCLR_EL1,Performance Monitor Interrupt Enable Clear" eventfld.long 0x00 31. "C,PMCCNTR enable [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.long 0x00 5. "P5,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 4. "P4,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 3. "P3,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.long 0x00 2. "P2,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 1. "P1,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 0. "P0,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" group.quad spr:0x339E3++0x00 line.quad 0x00 "PMOVSSET_EL0,Performance Monitor Overflow Flag Status Set Register" group.quad spr:(0x33E80+0x0)++0x00 line.quad 0x00 "PMEVCNTR0_EL0,Performance Monitors Event Count Register 0" group.quad spr:(0x33EC0+0x0)++0x00 line.quad 0x00 "PMEVTYPER0_EL0,Performance Monitors Selected Event Type Register 0" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:(0x33E80+0x1)++0x00 line.quad 0x00 "PMEVCNTR1_EL0,Performance Monitors Event Count Register 1" group.quad spr:(0x33EC0+0x1)++0x00 line.quad 0x00 "PMEVTYPER1_EL0,Performance Monitors Selected Event Type Register 1" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:(0x33E80+0x2)++0x00 line.quad 0x00 "PMEVCNTR2_EL0,Performance Monitors Event Count Register 2" group.quad spr:(0x33EC0+0x2)++0x00 line.quad 0x00 "PMEVTYPER2_EL0,Performance Monitors Selected Event Type Register 2" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:(0x33E80+0x3)++0x00 line.quad 0x00 "PMEVCNTR3_EL0,Performance Monitors Event Count Register 3" group.quad spr:(0x33EC0+0x3)++0x00 line.quad 0x00 "PMEVTYPER3_EL0,Performance Monitors Selected Event Type Register 3" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:(0x33E80+0x4)++0x00 line.quad 0x00 "PMEVCNTR4_EL0,Performance Monitors Event Count Register 4" group.quad spr:(0x33EC0+0x4)++0x00 line.quad 0x00 "PMEVTYPER4_EL0,Performance Monitors Selected Event Type Register 4" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:(0x33E80+0x5)++0x00 line.quad 0x00 "PMEVCNTR5_EL0,Performance Monitors Event Count Register 5" group.quad spr:(0x33EC0+0x5)++0x00 line.quad 0x00 "PMEVTYPER5_EL0,Performance Monitors Selected Event Type Register 5" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:0x33EF7++0x00 line.quad 0x00 "PMCCFILTR_EL0,Performance Monitors Cycle Count Filter Register" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" tree.end tree "System Timer Registers" group.quad spr:0x33E00++0x00 line.quad 0x00 "CNTFRQ_EL0,Counter Frequency Register" rgroup.quad spr:0x33E01++0x00 line.quad 0x00 "CNTPCT_EL0,Counter Physical Count Register" group.quad spr:0x30E10++0x00 line.quad 0x00 "CNTKCTL_EL1,Timer PL1 Control Register" bitfld.quad 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.quad 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" newline bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.quad spr:0x33E20++0x00 line.quad 0x00 "CNTP_TVAL_EL0,Counter PL1 Physical Compare Value Register" group.quad spr:0x33E21++0x00 line.quad 0x00 "CNTP_CTL_EL0,Counter PL1 Physical Timer Control Register" bitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x33E30++0x00 line.quad 0x00 "CNTV_TVAL_EL0,Counter PL1 Virtual Timer Value Register" group.quad spr:0x33E31++0x00 line.quad 0x00 "CNTV_CTL_EL0,Counter PL1 Virtual Timer Control Register" bitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x33E02++0x00 line.quad 0x00 "CNTVCT_EL0,Counter Virtual Count Register" group.quad spr:0x33E22++0x00 line.quad 0x00 "CNTP_CVAL_EL0,Counter PL1 Physical Compare Value Register" group.quad spr:0x33E32++0x00 line.quad 0x00 "CNTV_CVAL_EL0,Counter PL1 Virtual Compare Value Register" group.quad spr:0x34E03++0x00 line.quad 0x00 "CNTVOFF_EL2,Counter Virtual Offset Register" group.quad spr:0x34E10++0x00 line.quad 0x00 "CNTHCTL_EL2,Counter Non-secure PL2 Control Register" bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit is the trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" newline bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.quad spr:0x34E20++0x00 line.quad 0x00 "CNTHP_TVAL_EL2,Counter Non-secure PL2 Physical Timer Value Register" group.quad spr:0x34E21++0x00 line.quad 0x00 "CNTHP_CTL_EL2,Counter Non-secure PL2 Physical Timer Control Register" bitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x34E22++0x00 line.quad 0x00 "CNTHP_CVAL_EL2,Counter Non-secure PL2 Physical Compare Value Register" group.quad spr:0x37E20++0x00 line.quad 0x00 "CNTPS_TVAL_EL1,Counter-timer Physical SecureTimer TimerValue register" group.quad spr:0x37E21++0x00 line.quad 0x00 "CNTPS_CTL_EL1,Counter-timer Physical Secure Timer Control register" bitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x37E22++0x00 line.quad 0x00 "CNTPS_CVAL_EL1,Counter-timer Physical Secure Timer CompareValue register" tree.end tree "Generic Interrupt Controller CPU Interface" tree "AArch64 GIC Physical CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.quad spr:0x30C84++0x00 line.quad 0x00 "ICC_AP0R0_EL1,Active Priorities 0 Register 0" bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.quad spr:0x30C90++0x00 line.quad 0x00 "ICC_AP1R0_EL1,Active Priorities 1 Register 0" bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline wgroup.quad spr:0x30CB6++0x00 line.quad 0x00 "ICC_ASGI1R_EL1,Alternate SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" group.quad spr:0x30C83++0x00 line.quad 0x00 "ICC_BPR0_EL1,Binary Point Register 0" bitfld.quad 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7" group.quad spr:0x30CC3++0x00 line.quad 0x00 "ICC_BPR1_EL1,Binary Point Register 1" bitfld.quad 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7" group.quad spr:0x30CC4++0x00 line.quad 0x00 "ICC_CTLR_EL1,Interrupt Control Registers for EL1" rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported" rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.quad 0x00 14. "SEIS,SEI Support" "Not supported,Supported" bitfld.quad 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline rbitfld.quad 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" bitfld.quad 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1" newline bitfld.quad 0x00 0. "CBPR,Common Binary Point Register" "0,1" group.quad spr:0x36CC4++0x00 line.quad 0x00 "ICC_CTLR_EL3,Interrupt Control Registers for EL3" rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported" rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.quad 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported" newline rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.quad 0x00 14. "SEIS,SEI Support" "Not supported,Supported" bitfld.quad 0x00 11.--13. "IDBITS,Number of physical interruptidentifier bits supported" "16 bits,24 bits,?..." newline rbitfld.quad 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" bitfld.quad 0x00 5. "RM,Routing Modifier" "Normal,Special values" newline bitfld.quad 0x00 4. "EOIMODE_EL1NS,EOI mode for interrupts handledat non-secure EL1 and EL2" "0,1" bitfld.quad 0x00 3. "EOIMODE_EL1S,EOI mode for interrupts handled at secure EL1" "0,1" bitfld.quad 0x00 2. "EOIMODE_EL3,EOI mode for interrupts handled at EL3" "0,1" newline bitfld.quad 0x00 1. "CBPR_EL1NS,Non-secure accesses to GICC_BPR allowed." "Not allowed,Allowed" bitfld.quad 0x00 0. "CBPR_EL1S,Secure EL1 accesses to ICC_BPR1 allowed" "Not allowed,Allowed" wgroup.quad spr:0x30CB1++0x00 line.quad 0x00 "ICC_DIR_EL1,Deactivate Interrupt Register" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.quad spr:0x30C81++0x00 line.quad 0x00 "ICC_EOIR0_EL1,End Of Interrupt Register 0" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0_EL1 access" wgroup.quad spr:0x30CC1++0x00 line.quad 0x00 "ICC_EOIR1_EL1,End Of Interrupt Register 1" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1_EL1 access" rgroup.quad spr:0x30C82++0x00 line.quad 0x00 "ICC_HPPIR0_EL1,Highest Priority Pending Interrupt Register 0" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt" rgroup.quad spr:0x30CC2++0x00 line.quad 0x00 "ICC_HPPIR1_EL1,Highest Priority Pending Interrupt Register 1" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt" hgroup.quad spr:0x30C80++0x00 hide.long 0x00 "ICC_IAR0_EL1,Interrupt Acknowledge Register 0" in hgroup.quad spr:0x30CC0++0x00 hide.long 0x00 "ICC_IAR1_EL1,Interrupt Acknowledge Register 1" in newline group.quad spr:0x30CC6++0x00 line.quad 0x00 "ICC_IGRPEN0_EL1,Interrupt Group Enable Register 0" bitfld.quad 0x00 0. "ENABLE,Enable" "Disabled,Enabled" group.quad spr:0x30CC7++0x00 line.quad 0x00 "ICC_IGRPEN1_EL1,Interrupt Group Enable Register 1 (EL1)" bitfld.quad 0x00 0. "ENABLE,Enable" "Disabled,Enabled" group.quad spr:0x36CC7++0x00 line.quad 0x00 "ICC_IGRPEN1_EL3,Interrupt Group Enable Register 1 (EL3)" bitfld.quad 0x00 1. "ENABLEGRP1S,Enable Group 1 interrupts for the Secure state" "Disabled,Enabled" bitfld.quad 0x00 0. "ENABLEGRP1NS,Enable Group 1 interrupts for the Non-secure state" "Disabled,Enabled" group.quad spr:0x30460++0x00 line.quad 0x00 "ICC_PMR_EL1,Priority Mask Register" hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface" rgroup.quad spr:0x30CB3++0x00 line.quad 0x00 "ICC_RPR_EL1,Running Priority Register" hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" wgroup.quad spr:0x30CB7++0x00 line.quad 0x00 "ICC_SGI0R_EL1,SGI Generation Register 0" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" wgroup.quad spr:0x30CB5++0x00 line.quad 0x00 "ICC_SGI1R_EL1,SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" group.quad spr:0x30CC5++0x00 line.quad 0x00 "ICC_SRE_EL1,System Register Enable Register for EL1" bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.quad spr:0x34C95++0x00 line.quad 0x00 "ICC_SRE_EL2,System Register Enable Register for EL2" bitfld.quad 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled" bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.quad spr:0x36CC5++0x00 line.quad 0x00 "ICC_SRE_EL3,System Register Enable Register for EL3" bitfld.quad 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled" bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" tree.end tree "AArch64 Virtual Interface Control System Registers" group.quad spr:0x34C80++0x00 line.quad 0x00 "ICH_AP0R0_EL2,Interrupt Controller Hypervisor Active Priorities Register 0-0" rgroup.quad spr:0x34CB3++0x00 line.quad 0x00 "ICH_EISR_EL2,Interrupt Controller End of Interrupt Status Register" bitfld.quad 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt" bitfld.quad 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt" newline bitfld.quad 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt" rgroup.quad spr:0x34CB5++0x00 line.quad 0x00 "ICH_ELRSR_EL2,Interrupt Controller Empty List Register Status Register" bitfld.quad 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt" bitfld.quad 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt" bitfld.quad 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt" newline bitfld.quad 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt" group.quad spr:0x34CB0++0x00 line.quad 0x00 "ICH_HCR_EL2,Interrupt Controller Hypervisor Control Register" bitfld.quad 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped" bitfld.quad 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped" newline bitfld.quad 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped" bitfld.quad 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.quad 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" if (((per.q(spr:(0x34CC0+0x0)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x0)++0x00 line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x0)++0x00 line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((per.q(spr:(0x34CC0+0x1)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x1)++0x00 line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x1)++0x00 line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((per.q(spr:(0x34CC0+0x2)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x2)++0x00 line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x2)++0x00 line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((per.q(spr:(0x34CC0+0x3)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x3)++0x00 line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x3)++0x00 line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif rgroup.quad spr:0x34CB2++0x00 line.quad 0x00 "ICH_MISR_EL2,Interrupt Controller Maintenance Interrupt State Register" bitfld.quad 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted" bitfld.quad 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted" bitfld.quad 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted" newline bitfld.quad 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted" bitfld.quad 0x00 3. "NP,No Pending" "Not asserted,Asserted" bitfld.quad 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted" newline bitfld.quad 0x00 1. "U,Underflow" "Not asserted,Asserted" bitfld.quad 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted" group.quad spr:0x34CB7++0x00 line.quad 0x00 "ICH_VMCR_EL2,Interrupt Controller Virtual Machine Control Register" hexmask.quad.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface" bitfld.quad 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" bitfld.quad 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" newline bitfld.quad 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled" bitfld.quad 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register" bitfld.quad 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs" newline bitfld.quad 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt" bitfld.quad 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled" bitfld.quad 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled" group.quad spr:0x34C94++0x00 line.quad 0x00 "ICH_VSEIR_EL2,Interrupt Controller Virtual System Error Interrupt Register" rgroup.quad spr:0x34CB1++0x00 line.quad 0x00 "ICH_VTR_EL2,Interrupt Controller VGIC Type Register" bitfld.quad 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline bitfld.quad 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" bitfld.quad 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported" bitfld.quad 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported" newline bitfld.quad 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported" bitfld.quad 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree.end tree "Debug Registers" rgroup.quad spr:0x23010++0x00 line.quad 0x00 "MDCCSR_EL0,Debug Comms Channel Status Register" bitfld.quad 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.quad 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" group.quad spr:0x20020++0x00 line.quad 0x00 "MDCCINT_EL1,Debug Comms Channel Interrupt Enable Register" bitfld.quad 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled" bitfld.quad 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled" group.quad spr:0x23040++0x00 line.quad 0x00 "DBGDTR_EL0,Half Duplex Data Transfer Register" hexmask.quad.long 0x00 32.--63. 1. "HW,HighWord - Write/read DTRRX/DTRTX value without changing RXfull/TXfull" hexmask.quad.long 0x00 0.--31. 1. "LW,LowWord - Write/read DTRTX/DTRRX value without changing TXfull/RXfull" hgroup.quad spr:0x23050++0x00 hide.long 0x00 "DBGDTRRX_EL0,Full Duplex Receive Data Transfer Register" in wgroup.quad spr:0x23050++0x00 line.quad 0x00 "DBGDTRTX_EL0,Full Duplex Transmit Data Transfer Register" group.quad spr:0x24070++0x00 line.quad 0x00 "DBGVCR32_EL2,Vector Catch Register" bitfld.quad 0x00 31. "NSF,FIQ vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.quad 0x00 30. "NSI,IRQ vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.quad 0x00 28. "NSD,Data Abort vector catch enable in Non-secure state" "Disabled,Enabled" newline bitfld.quad 0x00 27. "NSP,Prefetch Abort vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.quad 0x00 26. "NSS,Supervisor Call (SVC) vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.quad 0x00 25. "NSU,Undefined Instruction vector catch enable in Non-secure state" "Disabled,Enabled" newline bitfld.quad 0x00 7. "SF,FIQ vector catch enable in Secure state" "Disabled,Enabled" bitfld.quad 0x00 6. "SI,IRQ vector catch enable in Secure state" "Disabled,Enabled" bitfld.quad 0x00 4. "SD,Data Abort vector catch enable in Secure state" "Disabled,Enabled" newline bitfld.quad 0x00 3. "SP,Prefetch Abort vector catch enable in Secure state" "Disabled,Enabled" bitfld.quad 0x00 2. "SS,Supervisor Call (SVC) vector catch enable in Secure state" "Disabled,Enabled" bitfld.quad 0x00 1. "SU,Undefined Instruction vector catch enable in Secure state" "Disabled,Enabled" group.quad spr:0x20002++0x00 line.quad 0x00 "OSDTRRX_EL1,OS Lock Data Transfer Register" if (((per.q(spr:0x20114)&0x02)==0x00)) group.quad spr:0x20022++0x00 line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register" rbitfld.quad 0x00 30. "RXFULL,Save/restore of EDSCR.RXfull" "Empty,Full" rbitfld.quad 0x00 29. "TXFULL,Save/restore of EDSCR.TXfull" "Empty,Full" newline rbitfld.quad 0x00 27. "RXO,Save/restore of EDSCR.RXO" "Low,High" rbitfld.quad 0x00 26. "TXU,Save/restore of EDSCR.TXU" "Low,High" newline rbitfld.quad 0x00 22.--23. "INTDIS,Save/restore of EDSCR.INTdis" "0,1,2,3" rbitfld.quad 0x00 21. "TDA,Save/restore of EDSCR.TDA" "Low,High" newline bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled" rbitfld.quad 0x00 14. "HDE,Save/restore of EDSCR.HDE" "Low,High" newline bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled" bitfld.quad 0x00 12. "TDCC,Traps EL0 accesses to the DCC registers to EL1" "Disabled,Enabled" newline bitfld.quad 0x00 6. "ERR,Save/restore of EDSCR.ERR" "Low,High" bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled" else group.quad spr:0x20022++0x00 line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register" bitfld.quad 0x00 30. "RXFULL,Save/restore of EDSCR.RXfull" "Empty,Full" bitfld.quad 0x00 29. "TXFULL,Save/restore of EDSCR.TXfull" "Empty,Full" newline bitfld.quad 0x00 27. "RXO,Save/restore of EDSCR.RXO" "Low,High" bitfld.quad 0x00 26. "TXU,Save/restore of EDSCR.TXU" "Low,High" newline bitfld.quad 0x00 22.--23. "INTDIS,Save/restore of EDSCR.INTdis" "0,1,2,3" bitfld.quad 0x00 21. "TDA,Save/restore of EDSCR.TDA" "Low,High" newline bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled" bitfld.quad 0x00 14. "HDE,Save/restore of EDSCR.HDE" "Low,High" newline bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled" bitfld.quad 0x00 12. "TDCC,Traps EL0 accesses to the DCC registers to EL1" "Disabled,Enabled" newline bitfld.quad 0x00 6. "ERR,Save/restore of EDSCR.ERR" "Low,High" bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled" endif group.quad spr:0x20032++0x00 line.quad 0x00 "OSDTRTX_EL1,OS Lock Data Transfer Register" group.quad spr:0x20062++0x00 line.quad 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register" rgroup.quad spr:0x20100++0x00 line.quad 0x00 "MDRAR_EL1,Debug ROM Address Register" hexmask.quad 0x00 12.--43. 0x10 "ROMADDR,ROM base physical address" bitfld.quad 0x00 0.--1. "VALID,ROM address valid" "Invalid,Reserved,Reserved,Valid" wgroup.quad spr:0x20104++0x00 line.quad 0x00 "OSLAR_EL1,OS Lock Access Register" bitfld.quad 0x00 0. "OSLK,OS lock" "Unlock,Lock" rgroup.quad spr:0x20114++0x00 line.quad 0x00 "OSLSR_EL1,OS Lock Status Register" bitfld.quad 0x00 2. "NTT,Not 32-bit access" "Low,High" bitfld.quad 0x00 1. "OSLK,OS lock status" "Not locked,Locked" bitfld.quad 0x00 0. 3. "OSLM,OS lock model implemented field" "Reserved,Reserved,Implemented,?..." group.quad spr:0x20134++0x00 line.quad 0x00 "OSDLR_EL1,OS Double-lock Register" bitfld.quad 0x00 0. "DLK,OS double-lock control" "Not locked,Locked" group.quad spr:0x20144++0x00 line.quad 0x00 "DBGPRCR_EL1,Debug Power/Reset Control Register" bitfld.quad 0x00 0. "CORENPDRQ,Core no powerdown request" "No,Yes" group.quad spr:0x20786++0x00 line.quad 0x00 "DBGCLAIMSET_EL1,Claim Tag register Set" bitfld.quad 0x00 7. "CT7,Claim Tag 7 Set" "Not set,Set" bitfld.quad 0x00 6. "CT6,Claim Tag 6 Set" "Not set,Set" newline bitfld.quad 0x00 5. "CT5,Claim Tag 5 Set" "Not set,Set" bitfld.quad 0x00 4. "CT4,Claim Tag 4 Set" "Not set,Set" newline bitfld.quad 0x00 3. "CT3,Claim Tag 3 Set" "Not set,Set" bitfld.quad 0x00 2. "CT2,Claim Tag 2 Set" "Not set,Set" newline bitfld.quad 0x00 1. "CT1,Claim Tag 1 Set" "Not set,Set" bitfld.quad 0x00 0. "CT0,Claim Tag 0 Set" "Not set,Set" group.quad spr:0x20796++0x00 line.quad 0x00 "DBGCLAIMCLR_EL1,Claim Tag register Clear" bitfld.quad 0x00 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.quad 0x00 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared" newline bitfld.quad 0x00 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared" bitfld.quad 0x00 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared" newline bitfld.quad 0x00 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.quad 0x00 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared" newline bitfld.quad 0x00 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.quad 0x00 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared" if (((per.q(spr:0x207e6))&0xAA)==0xAA) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0xA8) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.q(spr:0x207e6))&0xAA)==0xA2) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0xA0) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.q(spr:0x207e6))&0xAA)==0x8A) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0x88) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.q(spr:0x207e6))&0xAA)==0x82) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0x80) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.q(spr:0x207e6))&0xAA)==0x2A) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0x28) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.q(spr:0x207e6))&0xAA)==0x22) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0x20) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.q(spr:0x207e6))&0xAA)==0x0A) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0x08) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.q(spr:0x207e6))&0xAA)==0x02) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0x00) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" endif group.quad spr:0x33450++0x00 line.quad 0x00 "DSPSR_EL0,Debug Saved Processor Status Register" group.quad spr:0x33451++0x00 line.quad 0x00 "DLR_EL0,Debug Link Register" tree.end tree "Breakpoint Registers" tree "Breakpoint 0" if (((per.q(spr:(0x20005+0x0)))&0xA00000)==0x000000) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.q(spr:(0x20005+0x0)))&0xA00000)==0x800000) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" elif (((per.q(spr:(0x20005+0x0)))&0xA00000)==0x200000) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" else group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif if (((per.q(spr:0x20005+0x0))&0x400000)==0x400000) group.quad spr:(0x20005+0x0)++0x0 line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x0))&0x800000)==0x800000) group.quad spr:(0x20005+0x0)++0x0 line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x0)++0x0 line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 1" if (((per.q(spr:(0x20005+0x10)))&0xA00000)==0x000000) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.q(spr:(0x20005+0x10)))&0xA00000)==0x800000) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" elif (((per.q(spr:(0x20005+0x10)))&0xA00000)==0x200000) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" else group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif if (((per.q(spr:0x20005+0x10))&0x400000)==0x400000) group.quad spr:(0x20005+0x10)++0x0 line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x10))&0x800000)==0x800000) group.quad spr:(0x20005+0x10)++0x0 line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x10)++0x0 line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 2" if (((per.q(spr:(0x20005+0x20)))&0xA00000)==0x000000) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.q(spr:(0x20005+0x20)))&0xA00000)==0x800000) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" elif (((per.q(spr:(0x20005+0x20)))&0xA00000)==0x200000) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" else group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif if (((per.q(spr:0x20005+0x20))&0x400000)==0x400000) group.quad spr:(0x20005+0x20)++0x0 line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x20))&0x800000)==0x800000) group.quad spr:(0x20005+0x20)++0x0 line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x20)++0x0 line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 3" if (((per.q(spr:(0x20005+0x30)))&0xA00000)==0x000000) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.q(spr:(0x20005+0x30)))&0xA00000)==0x800000) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" elif (((per.q(spr:(0x20005+0x30)))&0xA00000)==0x200000) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" else group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif if (((per.q(spr:0x20005+0x30))&0x400000)==0x400000) group.quad spr:(0x20005+0x30)++0x0 line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x30))&0x800000)==0x800000) group.quad spr:(0x20005+0x30)++0x0 line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x30)++0x0 line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 4" if (((per.q(spr:(0x20005+0x40)))&0xA00000)==0x000000) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.q(spr:(0x20005+0x40)))&0xA00000)==0x800000) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" elif (((per.q(spr:(0x20005+0x40)))&0xA00000)==0x200000) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" else group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif if (((per.q(spr:0x20005+0x40))&0x400000)==0x400000) group.quad spr:(0x20005+0x40)++0x0 line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x40))&0x800000)==0x800000) group.quad spr:(0x20005+0x40)++0x0 line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x40)++0x0 line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 5" if (((per.q(spr:(0x20005+0x50)))&0xA00000)==0x000000) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.q(spr:(0x20005+0x50)))&0xA00000)==0x800000) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" elif (((per.q(spr:(0x20005+0x50)))&0xA00000)==0x200000) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" else group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif if (((per.q(spr:0x20005+0x50))&0x400000)==0x400000) group.quad spr:(0x20005+0x50)++0x0 line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x50))&0x800000)==0x800000) group.quad spr:(0x20005+0x50)++0x0 line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x50)++0x0 line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif tree.end tree.end tree "Watchpoint Control Registers" tree "Watchpoint 0" group.quad spr:(0x20006+0x0)++0x00 line.quad 0x00 "DBGWVR0_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x0)++0x00 line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree "Watchpoint 1" group.quad spr:(0x20006+0x10)++0x00 line.quad 0x00 "DBGWVR1_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x10)++0x00 line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree "Watchpoint 2" group.quad spr:(0x20006+0x20)++0x00 line.quad 0x00 "DBGWVR2_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x20)++0x00 line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree "Watchpoint 3" group.quad spr:(0x20006+0x30)++0x00 line.quad 0x00 "DBGWVR3_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x30)++0x00 line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree.end tree.end tree.open "AArch32" tree "ID Registers" rgroup.long c15:0x0000++0x00 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x00 24.--31. 1. "IMPL,Implementer code" bitfld.long 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "ARCH, Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8" newline hexmask.long.word 0x00 4.--15. 1. "PART,Primary Part Number" bitfld.long 0x00 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x0100++0x00 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x00 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.long 0x00 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." rgroup.long c15:0x0300++0x00 line.long 0x00 "TLBTR,TLB Type Register" bitfld.long 0x00 0. "NU,Not Unified. Indicates whether the implementation has a unified TLB" "Unified," rgroup.long c15:0x0500++0x00 line.long 0x00 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor" newline bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largery independent,Very interdependent" hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" newline bitfld.long 0x00 0.--1. "CPUID,CPU ID" "1,2,3,4" rgroup.long c15:0x0600++0x00 line.long 0x00 "REVIDR,Revision ID Register" rgroup.long c15:0x0410++0x00 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Reserved,ACTLR/AIFSR/ADFSR,?..." newline bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..." bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..." newline bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." newline bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..." bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..." bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup.long c15:0x0620++0x00 line.long 0x00 "ID_MMFR4,ID_MMFR4" bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented, implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" rgroup.long c15:0x0020++0x00 line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..." newline bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..." rgroup.long c15:0x0120++0x00 line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0220++0x00 line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0320++0x00 line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..." bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0420++0x00 line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4" bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..." bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..." newline bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0520++0x00 line.long 0x00 "ID_ISAR5,Instruction Set Attribute Register 5" bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..." newline bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..." bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c15:0x0110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Not supported,Supported,?..." newline bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup.long c15:0x0210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,PMUv3,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." newline rgroup.long c15:0x6C9++0x00 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 30. "CH,Chain" "Not implemented,Implemented" bitfld.long 0x00 29. "BC,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. "TW,Instruction architecturally executed condition check pass" "Not implemented,Implemented" newline bitfld.long 0x00 27. "IS,Instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 26. "ME,Local memory error" "Not implemented,Implemented" bitfld.long 0x00 25. "BA,Bus access" "Not implemented,Implemented" newline bitfld.long 0x00 24. "DC2W,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 23. "DC2R,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. "DC2A,Level 2 data cache access" "Not implemented,Implemented" newline bitfld.long 0x00 21. "DC1W,Level 1 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 20. "IC1A,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. "MA,Data memory access" "Not implemented,Implemented" newline bitfld.long 0x00 18. "BP,Predictable branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 17. "CC,Cycle" "Not implemented,Implemented" bitfld.long 0x00 16. "BM,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 15. "UL,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" bitfld.long 0x00 14. "BR,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.long 0x00 13. "BI,Instruction architecturally executed immediate branch" "Not implemented,Implemented" newline bitfld.long 0x00 12. "PW,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" bitfld.long 0x00 11. "CW,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.long 0x00 10. "ER,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" newline bitfld.long 0x00 9. "ET,Exception taken" "Not implemented,Implemented" bitfld.long 0x00 8. "IA,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 7. "ST,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" newline bitfld.long 0x00 6. "LD,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" bitfld.long 0x00 5. "DT1R,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.long 0x00 4. "DC1A,Level 1 data cache access" "Not implemented,Implemented" newline bitfld.long 0x00 3. "DC1R,Level 1 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 2. "IT1R,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. "IC1R,Level 1 instruction cache refill" "Not implemented,Implemented" newline bitfld.long 0x00 0. "SI,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,User Read-Only Thread ID Register" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,EL1 only Thread ID Register" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register" tree.end tree "System Control and Configuration" if (((per.l(c15:0x202))&0x80000000)==0x00000000) group.long c15:0x0001++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x00 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x00 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x00 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x00 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x00 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x00 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x00 6. "THEE,ThumbEE Disable" "No,Yes" bitfld.long 0x00 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" else group.long c15:0x0001++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x00 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x00 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x00 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x00 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x00 6. "THEE,ThumbEE Disable" "No,Yes" bitfld.long 0x00 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" endif group.quad c15:0x100F0++0x01 line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register" bitfld.quad 0x00 63. "FPMRCGEA,Force processor RCG enables active" "Not forced,Forced" bitfld.quad 0x00 62. "FPNMRCGEA,Force processor non-memory-system RCG enables active" "Not forced,Forced" newline bitfld.quad 0x00 61. "FPDIERCGEA,Force processor Decode and Integer Execute idle RCG enables active" "Not forced,Forced" bitfld.quad 0x00 60. "FPDRCGEA,Force processor Dispatch idle RCG enables active" "Not forced,Forced" newline bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes" bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes" newline bitfld.quad 0x00 57. "TA,Treat DMB st/st and DMB ld/allas DMB all/all" "Disabled,Enabled" bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes" newline bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes" bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled" newline bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled" bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes" newline bitfld.quad 0x00 51. "ECDAFEMP,Enable contention detection and fast exclusive monitor path" "Disabled,Enabled" bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes" newline bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes" bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes" newline bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes" bitfld.quad 0x00 46. "DML1DTLBM,Disable multiple outstanding L1 Data TLB misses and L2 TLB hit under miss" "No,Yes" newline bitfld.quad 0x00 45. "Dl1DCWT,Disable L1-DCache way tracker" "No,Yes" bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled" newline bitfld.quad 0x00 43. "DVABHWPREF,Disable the Load/Store hardware prefetcher from using VA to cross page boundaries" "No,Yes" bitfld.quad 0x00 42. "DPREFREQRUT,Disable prefetch requests from ReadUnique transactions" "No,Yes" newline bitfld.quad 0x00 41. "ESHWSHAEP,Enable snoop hazard while waiting for second half of atomic exclusive pair" "Disabled,Enabled" bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes" newline bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced" bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes" newline bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced" bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes" newline bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes" bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes" newline bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled" bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced" newline bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled" bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled" newline bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled" newline bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced" bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced" newline bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes" bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes" newline bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes" bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes" newline bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes" bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled" newline bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced" bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced" newline bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled" bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled" newline bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled" bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced" newline bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes" bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled" newline bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled" bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled" newline bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes" bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes" newline bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes" bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled" group.quad c15:0x110F0++0x01 line.quad 0x00 "CPUECTLR,CPU Extended Control Register" bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes" bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 requests,1 request,2 requests,3 requests" newline bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "16 requests,18 requests,20 requests,22 requests" bitfld.quad 0x00 6. "SMPEN,Enables the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster" "Disabled,Enabled" newline bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad c15:0x120F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,Indicates the index address of the first memory error" group.long c15:0x0101++0x00 line.long 0x00 "ACTLR,Auxiliary Control Register" group.long c15:0x0201++0x00 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 28. "TRCDIS,Disable CP14 access to trace registers" "No," newline bitfld.long 0x00 22.--23. "CP11,Coprocesor access control" "Denied,EL1 or higher,Reserved,Full" bitfld.long 0x00 20.--21. "CP10,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full" group.long c15:0x0011++0x00 line.long 0x00 "SCR,Secure Configuration Register" bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped" bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped" newline bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "Disabled,Enabled" newline bitfld.long 0x00 7. "SCD,Secure Monitor Call disable" "No,Yes" bitfld.long 0x00 5. "AW,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed" newline bitfld.long 0x00 4. "FW,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" newline bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" newline bitfld.long 0x00 0. "NS,Secure mode " "Secure,Non-secure" group.long c15:0x0111++0x00 line.long 0x00 "SDER,Secure Debug Enable Register" bitfld.long 0x00 1. "SUNIDEN,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted" bitfld.long 0x00 0. "SUIDEN,Invasive Secure User Debug Enable bit" "Denied,Permitted" group.long c15:0x0131++0x00 line.long 0x00 "SDCR,Secure Debug Control Register" bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes" bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes" newline bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. "SPD,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled" group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 15. "NSASEDIS,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 11. "CP11,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted" newline bitfld.long 0x00 10. "CP10,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted" group.long c15:0x000C++0x00 line.long 0x00 "VBAR,Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address" group.long c15:0x010C++0x00 line.long 0x00 "MVBAR,Monitor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address" rgroup.long c15:0x001C++0x00 line.long 0x00 "ISR,Interrupt Status Register" bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending" bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending" newline bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending" group.long c15:0x020C++0x00 line.long 0x00 "RMR,Reset Management Register" bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested" bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64" rgroup.long c15:0x0015++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" rgroup.long c15:0x0115++0x00 line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable" bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable" newline bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 0.--5. "STATUS,Fault Status bits" "Address size/0th level,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable" bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable" newline bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. "FS[3:0],Fault Status bits" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external,Reserved,Async. parity/on memory access,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External abort type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Short,Long" newline bitfld.long 0x00 0.--5. "STATUS,Fault Status bits" "Address size/0th level,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Short,Long" newline bitfld.long 0x00 0.--3. 10. "FS[3:0],Fault Status bits" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external,Reserved,Async. parity/on memory access,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif group.long c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" group.long c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" rgroup.long c15:0x103F++0x00 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]" hexmask.long.word 0x00 0.--11. 1. "PERIPHBASE[43:32],Periphbase[43:32]" group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,PL0 Read/Write Software Thread ID Register" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,PL0 Read-Only Software Thread ID Register" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,PL1 Software Thread ID Register" tree.end tree "Memory Management Unit" group.long c15:0x0001++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x00 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x00 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x00 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x00 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x00 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x00 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x00 6. "THEE,ThumbEE Enable" "Not implemented," bitfld.long 0x00 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "C,Cache enable" "Disabled,Enabled" bitfld.long 0x00 1. "A,Alignment check enable" "Disabled,Enabled" newline bitfld.long 0x00 0. "M,MMU enable" "Disabled,Enabled" group.long c15:0x4001++0x00 line.long 0x00 "HSCTLR,Hypervisor System Control Register" bitfld.long 0x00 30. "TE,Thumb exception enable" "ARM,Thumb" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x00 19. "WXN,Write permission implies XN" "Not forced,Forced" bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x00 5. "CP15BEN,AArch32 CP15 barrier enable" "Disabled,Enabled" bitfld.long 0x00 2. "C,Cache enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "A,Alignment check enable" "Disabled,Enabled" bitfld.long 0x00 0. "M,MMU enable" "Disabled,Enabled" if ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0002))&0x02)==0x02)) group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Registers" hexmask.long 0x00 6.--31. 0x40 "TTB0,Translation table base 0 address" bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner" newline bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable" newline bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable" elif ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0002))&0x02)==0x00)) group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Registers" hexmask.long 0x00 6.--31. 0x40 "TTB0,Translation table base 0 address" bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable" bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable" else group.quad c15:0x10020++0x01 line.quad 0x00 "TTBR0,Translation Table Base Registers" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base 0 address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base 0 address" endif if ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0102))&0x02)==0x02)) group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base 1 Registers" hexmask.long 0x00 6.--31. 0x40 "TTB1,Translation table base 1 address" bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner" newline bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable" newline bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable" elif ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0102))&0x02)==0x00)) group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Registers" hexmask.long 0x00 6.--31. 0x40 "TTB1,Translation table base 1 address" bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable" bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable" else group.quad c15:0x11020++0x01 line.quad 0x00 "TTBR1,Translation Table Base Registers" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base 0 address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base 0 address" endif if (((per.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" newline bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes" bitfld.long 0x00 22. "A1,Select ASID from TTBR0/TTBR1 ASID field" "TTBR0,TTBR1" newline bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" newline bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" else group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes" newline bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes" bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7" endif if (((per.l(c15:0x4202))&0x07)==0x00) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 5.--47. 0x20 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x01) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 4.--47. 0x10 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x02) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 12.--47. 0x10 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x03) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 11.--47. 0x8 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x04) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 10.--47. 0x4 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x05) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 9.--47. 0x2 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x06) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 8.--47. 0x1 "BADDR,Translation table base address" else group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 7.--47. 0x80 "BADDR,Translation table base address" endif group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hypervisor Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer cacheability attribute, Normal memory" "Outer Non-cacheable,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 8.--9. "IRGN0, ,Inner cacheability attribute, Normal memory" "Inner Non-cacheable,Inner Write-Back Write-Allocate Cacheable,Inner Write-Through Cacheable,Inner Write-Back no Write-Allocate Cacheable" hexmask.long.byte 0x00 0.--2. 0x1 "T0SZ, ,Size offset of the memory region addressed by HTTBR" group.long c15:0x0003++0x00 line.long 0x00 "DACR,Domain Access Control Register" bitfld.long 0x00 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x00 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager" newline bitfld.long 0x00 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.long 0x00 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager" newline bitfld.long 0x00 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x00 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager" newline bitfld.long 0x00 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x00 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager" newline bitfld.long 0x00 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.long 0x00 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager" newline bitfld.long 0x00 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x00 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager" newline bitfld.long 0x00 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x00 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager" newline bitfld.long 0x00 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.long 0x00 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager" if ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0047))&0x1)==0x0)) group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 "PA,Physical Address" newline bitfld.long 0x00 11. "LPAE,Descriptor translation table format" "Short,Long" bitfld.long 0x00 10. "NOS,Not Outer Shareable attribute for the region" "No,Yes" newline bitfld.long 0x00 9. "NS,Non-secure" "No,Yes" bitfld.long 0x00 7. "SH,Shareable attribute for the region" "No,Yes" newline bitfld.long 0x00 4.--6. "INNER,Inner memory attributes for the region" "Non-cacheable,Strongly-ordered,Reserved,Device,Reserved,Write-Back/Write-Allocate,Write-Through,Write-Back/No Write-Allocate" newline bitfld.long 0x00 2.--3. "OUTER,Outer memory attributes for the region" "Non-cacheable,Write-Back/Write-Allocate,Write-Through/No Write-Allocate,Write-Back/No Write-Allocate" newline bitfld.long 0x00 1. "SS,Supersection" "Disabled,Enabled" newline bitfld.long 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0047))&0x1)==0x1)) group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" newline bitfld.long 0x00 11. "LPAE,Descriptor translation table format" "Short,Long" newline newline newline bitfld.long 0x00 6. "FS[5],Fault status bit - External abort type" "DECERR,SLVERR" newline bitfld.long 0x00 1.--5. "FS[0:4],Fault status bit - Fault source" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external abort/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external abort on translation table walk/1st level,Permission/1st level,Sync. external abort on translation table walk/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external abort,Reserved,Async. parity error on memory access,Sync. parity error on memory access,Reserved,Reserved,Sync. parity error on translation table walk/1st level,Reserved,Sync. parity error on translation table walk/2nd level,?..." newline bitfld.long 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif ((((per.l(c15:0x0202))&0x80000000)==0x80000000)&&(((per.l(c15:0x10070))&0x1)==0x0)) group.quad c15:0x10070++0x01 line.quad 0x00 "PAR,Physical Address Register" hexmask.quad.byte 0x00 56.--63. 1. "ATTR,Memory attributes for the returned PA" hexmask.quad.long 0x00 12.--39. 0x10 "PA,Physical Address" newline bitfld.quad 0x00 11. "LPAE,Descriptor translation table format" "Short,Long" newline bitfld.quad 0x00 9. "NS,Non-secure" "No,Yes" bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline newline newline newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" else group.quad c15:0x10070++0x01 line.quad 0x00 "PAR,Physical Address Register" newline bitfld.quad 0x00 11. "LPAE,Descriptor translation table format" "Short,Long" newline bitfld.quad 0x00 9. "FSTAGE,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2" bitfld.quad 0x00 8. "S2WLK,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes" newline newline bitfld.quad 0x00 1.--6. "FST,Fault Status Field" "Address/0th level,Address/1st level,Address/2nd level,Address/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. ext. abort,Async. external abort,Reserved,Reserved,Sync. ext. abort/0th level,Sync. ext. abort/1st level,Sync. ext. abort/2nd level,Sync. ext. abort/3rd level,Sync. parity error on memory access,Async. parity error on memory access,Reserved,Reserved,Reserved,Sync. parity error on translation table walk/0th level,Sync. parity error on translation table walk/1st level,Sync. parity error on translation table walk/2nd level,Sync. parity error on translation table walk/3rd level,Reserved,Alignment,Debug event,?..." newline newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" endif tree.open "Memory Attribute Indirection Registers" if ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" else hgroup.long c15:0x002A++0x00 hide.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" endif if ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" else hgroup.long c15:0x012A++0x00 hide.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" endif if ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" else hgroup.long c15:0x402A++0x00 hide.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" endif if ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" else hgroup.long c15:0x412A++0x00 hide.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" endif if (((per.l(c15:0x202))&0x80000000)==0x00000000) group.long c15:0x002A++0x00 line.long 0x00 "PRRR,Primary Region Remap Register" bitfld.long 0x00 31. "NOS7,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 30. "NOS6,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 29. "NOS5,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 28. "NOS4,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 27. "NOS3,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 26. "NOS2,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 25. "NOS1,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 24. "NOS0,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "Non-shareable,Shareable" bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "Non-shareable,Shareable" newline bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "Non-shareable,Shareable" bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "Non-shareable,Shareable" newline bitfld.long 0x00 14.--15. "TR7,{TEX[0] C B} = b111 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 12.--13. "TR6,{TEX[0] C B} = b110 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 10.--11. "TR5,{TEX[0] C B} = b101 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 8.--9. "TR4,{TEX[0] C B} = b100 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 6.--7. "TR3,{TEX[0] C B} = b011 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 4.--5. "TR2,{TEX[0] C B} = b010 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 2.--3. "TR1,{TEX[0] C B} = b001 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 0.--1. "TR0,{TEX[0] C B} = b000 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." group.long c15:0x012A++0x00 line.long 0x00 "NMRR,Normal Memory Remap Register" bitfld.long 0x00 30.--31. "OR7,Outer Attribute for {TEX[0] C B} = b111 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 28.--29. "OR6,Outer Attribute for {TEX[0] C B} = b110 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 26.--27. "OR5,Outer Attribute for {TEX[0] C B} = b101 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 24.--25. "OR4,Outer Attribute for {TEX[0] C B} = b100 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 22.--23. "OR3,Outer Attribute for {TEX[0] C B} = b011 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 20.--21. "OR2,Outer Attribute for {TEX[0] C B} = b010 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 18.--19. "OR1,Outer Attribute for {TEX[0] C B} = b001 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 16.--17. "OR0,Outer Attribute for {TEX[0] C B} = b000 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 14.--15. "IR7,Inner attribute for {TEX[0] C B} = b111 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 12.--13. "IR6,Inner attribute for {TEX[0] C B} = b110 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 10.--11. "IR5,Inner attribute for {TEX[0] C B} = b101 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 8.--9. "IR4,Inner attribute for {TEX[0] C B} = b100 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 6.--7. "IR3,Inner attribute for {TEX[0] C B} = b011 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 4.--5. "IR2,Inner attribute for {TEX[0] C B} = b010 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 2.--3. "IR1,Inner attribute for {TEX[0] C B} = b001 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 0.--1. "IR0,Inner attribute for {TEX[0] C B} = b000 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline group.long c15:0x10d++0x00 line.long 0x00 "CONTEXTIDR,Context ID Register" hexmask.long.tbyte 0x00 8.--31. 1. "PROCID,Process identifier" hexmask.long.byte 0x00 0.--7. 1. "ASID,Address space identifier" else hgroup.long c15:0x002A++0x00 hide.long 0x00 "PRRR,Primary Region Remap Register" hgroup.long c15:0x012A++0x00 hide.long 0x00 "NMRR,Normal Memory Remap Register" group.long c15:0x10d++0x00 line.long 0x00 "CONTEXTIDR,Context ID Register" endif tree.end tree.end tree "Virtualization Extensions" group.long c15:0x4000++0x00 line.long 0x00 "VPIDR,Virtualization Processor ID Register" group.long c15:0x4500++0x00 line.long 0x00 "VMPIDR,Virtualization Multiprocessor ID Register" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register" group.long c15:0x4001++0x00 line.long 0x00 "HSCTLR,Hypervisor System Control Register" bitfld.long 0x00 30. "TE,Thumb exception enable" "ARM,Thumb" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x00 19. "WXN,Write permission implies XN" "Not forced,Forced" bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x00 5. "CP15BEN,AArch32 CP15 barrier enable" "Disabled,Enabled" bitfld.long 0x00 2. "C,Cache enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "A,Alignment check enable" "Disabled,Enabled" bitfld.long 0x00 0. "M,MMU enable" "Disabled,Enabled" group.long c15:0x4101++0x00 line.long 0x00 "HACTLR,Hypervisor Auxiliary Control Register" bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR access control" "Disabled,Enabled" bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR access control" "Disabled,Enabled" newline bitfld.long 0x00 4. "L2CTLRAC,L2CTLR access control" "Disabled,Enabled" bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR access control" "Disabled,Enabled" newline bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR access control" "Disabled,Enabled" group.long c15:0x4011++0x00 line.long 0x00 "HCR,Hypervisor Configuration Register" bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled" newline bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled" bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled" newline bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled" bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled" newline bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled" bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled" newline bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled" bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" newline bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" newline bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" newline bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" newline bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "No effect,Inner,Outer,Full" newline bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled" bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "Not aborted,Aborted" newline bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt" bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 5. "AMO,A-bit Mask Override" "Not routed,Routed" bitfld.long 0x00 4. "IMO,I-bit Mask Override" "Not routed,Routed" newline bitfld.long 0x00 3. "FMO,F-bit Mask Override" "Not routed,Routed" bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" newline bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override" bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled" group.long c15:0x4411++0x00 line.long 0x00 "HCR2,Hypervisor Configuration Register 2" bitfld.long 0x00 1. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.long 0x00 0. "CD,Stage 2 Data cache disable" "No,Yes" group.long c15:0x4111++0x00 line.long 0x00 "HDCR,Hypervisor Debug Control Register" bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid" bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" newline bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid" newline bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" newline bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long c15:0x4211++0x00 line.long 0x00 "HCPTR,Hypervisor Architectural Feature Trap Register" bitfld.long 0x00 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.long 0x00 20. "TTA,Trap Trace Access" "Not supported," newline bitfld.long 0x00 15. "TASE,Trap Advanced SIMD extensions" "Not trapped,Trapped" bitfld.long 0x00 11. "TCP11,Trap coprocessor 11" "Not trapped,Trapped" newline bitfld.long 0x00 10. "TCP10,Trap coprocessor 10" "Not trapped,Trapped" group.long c15:0x4311++0x00 line.long 0x00 "HSTR,Hypervisor System Trap Register" bitfld.long 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "No effect,Trap" bitfld.long 0x00 13. "T13,Trap to Hypervisor mode Non-secure priv 13" "No effect,Trap" newline bitfld.long 0x00 12. "T12,Trap to Hypervisor mode Non-secure priv 12" "No effect,Trap" bitfld.long 0x00 11. "T11,Trap to Hypervisor mode Non-secure priv 11" "No effect,Trap" newline bitfld.long 0x00 10. "T10,Trap to Hypervisor mode Non-secure priv 10" "No effect,Trap" bitfld.long 0x00 9. "T9,Trap to Hypervisor mode Non-secure priv 9" "No effect,Trap" newline bitfld.long 0x00 8. "T8,Trap to Hypervisor mode Non-secure priv 8" "No effect,Trap" bitfld.long 0x00 7. "T7,Trap to Hypervisor mode Non-secure priv 7" "No effect,Trap" newline bitfld.long 0x00 6. "T6,Trap to Hypervisor mode Non-secure priv 6" "No effect,Trap" bitfld.long 0x00 5. "T5,Trap to Hypervisor mode Non-secure priv 5" "No effect,Trap" newline bitfld.long 0x00 3. "T3,Trap to Hypervisor mode Non-secure priv 3" "No effect,Trap" bitfld.long 0x00 2. "T2,Trap to Hypervisor mode Non-secure priv 2" "No effect,Trap" newline bitfld.long 0x00 1. "T1,Trap to Hypervisor mode Non-secure priv 1" "No effect,Trap" bitfld.long 0x00 0. "T0,Trap to Hypervisor mode Non-secure priv 0" "No effect,Trap" rgroup.long c15:0x4711++0x00 line.long 0x00 "HACR,Hypervisor Auxiliary Configuration Register" if (((per.l(c15:0x4202))&0x07)==0x00) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 5.--47. 0x20 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x01) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 4.--47. 0x10 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x02) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 12.--47. 0x10 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x03) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 11.--47. 0x8 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x04) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 10.--47. 0x4 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x05) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 9.--47. 0x2 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x06) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 8.--47. 0x1 "BADDR,Translation table base address" else group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 7.--47. 0x80 "BADDR,Translation table base address" endif group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hypervisor Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate,Write-Through,Write-Back no Write-Allocate" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate,Write-Through,Write-Back no Write-Allocate" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" if (((per.l(c15:0x4212))&0x0F)==0x00) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 5.--47. 0x20 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x01) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 4.--47. 0x10 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x02) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 12.--47. 0x10 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x03) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 11.--47. 0x8 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x04) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 10.--47. 0x4 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x05) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 9.--47. 0x2 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x06) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 8.--47. 0x1 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x07) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 7.--47. 0x80 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x08) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad.long 0x00 22.--47. 0x40 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x09) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad.long 0x00 21.--47. 0x20 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x0A) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad.long 0x00 20.--47. 0x10 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x0B) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad.long 0x00 19.--47. 0x8 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x0C) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad.long 0x00 18.--47. 0x4 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x0D) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad.long 0x00 17.--47. 0x2 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x0E) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad.long 0x00 16.--47. 0x1 "BADDR,Translation table base address" else group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 15.--47. 0x80 "BADDR,Translation table base address" endif group.long c15:0x4212++0x00 line.long 0x00 "VTCR,Virtualization Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "Non-cacheable,Write-Back Write-Allocate,Write-Through,Write-Back no Write-Allocate" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Non-cacheable,Write-Back Write-Allocate,Write-Through,Write-Back no Write-Allocate" bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "2nd level,1st level,," newline bitfld.long 0x00 4. "S,Sign-extension of the T0SZ field" "Low,High" bitfld.long 0x00 0.--3. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1" group.long c15:0x4006++0x00 line.long 0x00 "HDFAR,Hypervisor Data Fault Address Register" if (((per.l(c15:0x4025))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((per.l(c15:0x4025))&0xFC000000)==0x04000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((per.l(c15:0x4025))&0xFC000000)==(0x0C000000||0x14000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.l(c15:0x4025))&0xFC000000)==(0x10000000||0x30000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.l(c15:0x4025))&0xFC000000)==0x18000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.l(c15:0x4025))&0xFC000000)==0x1C000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((per.l(c15:0x4025))&0xFC000000)==(0x44000000||0x54000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.l(c15:0x4025))&0xFC000000)==0x60000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3" newline bitfld.long 0x00 17.--19. "OP2,Op2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "OP1,Op1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.l(c15:0x4025))&0xFC000000)==(0x80000000||0x84000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..." elif (((per.l(c15:0x4025))&0xFD000000)==(0x91000000||0x95000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.l(c15:0x4025))&0xFD000000)==(0x90000000||0x94000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.l(c15:0x4025))&0xFC800000)==(0xA0800000||0xB0800000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((per.l(c15:0x4025))&0xFC800000)==(0xA0000000||0xB0000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((per.l(c15:0x4025))&0xFD000000)==0xBD000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 15. "UNASE,Unattributable System Error" "Attributable,Unattributable" newline bitfld.long 0x00 14. "UNCSE,Uncontainable System Error" "Containable,Uncontainable" bitfld.long 0x00 0.--1. "SES,System Error Source" "Decode,ECC,Slave," elif (((per.l(c15:0x4025))&0xFD000000)==0xBC000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((per.l(c15:0x4025))&0xFC000000)==(0xC0000000||0xC4000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.l(c15:0x4025))&0xFC000000)==(0xC8000000||0xCC000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.l(c15:0x4025))&0xFC000000)==(0xD0000000||0xD4000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.l(c15:0x4025))&0xFC000000)==(0xE0000000||0xF0000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif group.long c15:0x4206++0x00 line.long 0x00 "HIFAR,Hypervisor Instruction Fault Address Register" group.long c15:0x4406++0x00 line.long 0x00 "HPFAR,Hypervisor IPA Fault Address Register" hexmask.long 0x00 4.--31. 1. "FIPA,Bits [39:12] of the faulting intermediate physical address" group.long c15:0x400C++0x00 line.long 0x00 "HVBAR,Hypervisor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "HVBADDR,Hypervisor Vector Base Address" tree.end tree "Cache Control and Configuration" rgroup.long c15:0x0100++0x00 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x00 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.long 0x00 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." rgroup.long c15:0x1100++0x00 line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,Reserved,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..." newline bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..." bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..." newline bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..." bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..." newline bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." newline bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..." bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate I/D,?..." rgroup.long c15:0x1700++0x0 line.long 0x00 "AIDR,Auxiliary ID Register" rgroup.long c15:0x1000++0x00 line.long 0x00 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. "WT,Write-Through" "Not Supported," bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported" newline bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported" bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" newline hexmask.long.word 0x00 13.--27. 1. "SETS,Number of Sets" hexmask.long.word 0x00 3.--12. 1. "ASSOC,Associativity" newline bitfld.long 0x00 0.--2. "LSIZE,Line Size" "Reserved,Reserved,64 bytes,?..." group.long c15:0x2000++0x00 line.long 0x00 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..." bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction" tree "Level 1 memory system" group.long c15:0x001F++0x00 line.long 0x00 "DL1DATA0,Data L1 Data 0 Register" group.long c15:0x011F++0x00 line.long 0x00 "DL1DATA1,Data L1 Data 1 Register" group.long c15:0x021F++0x00 line.long 0x00 "DL1DATA2,Data L1 Data 2 Register" group.long c15:0x031F++0x00 line.long 0x00 "DL1DATA3,Data L1 Data 3 Register" group.long c15:0x041F++0x00 line.long 0x00 "DL1DATA4,Data L1 Data 4 Register" group.long c15:0x000F++0x00 line.long 0x00 "IL1DATA0,Instruction L1 Data 0 Register" group.long c15:0x010F++0x00 line.long 0x00 "IL1DATA1,Instruction L1 Data 1 Register" group.long c15:0x020F++0x00 line.long 0x00 "IL1DATA2,Instruction L1 Data 2 Register" group.long c15:0x030F++0x00 line.long 0x00 "IL1DATA3,Instruction L1 Data 3 Register" wgroup.long c15:0x04F++0x00 line.long 0x00 "RAMINDEX,RAM Index Operation Register" hexmask.long.byte 0x00 24.--31. 1. "RAMID,RAM identifier" bitfld.long 0x00 18.--21. "WAY,Indicates the way of the RAM that is being accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x00 0.--17. 1. "INDEX,Indicates the index address of the RAM that is being accessed" tree.end tree "Level 2 memory system" group.long c15:0x1209++0x00 line.long 0x00 "L2CTLR,L2 Control Register" bitfld.long 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "Reset,No reset" bitfld.long 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4" rbitfld.long 0x00 23. "L2CP,L2 cache ECC protection" "Not supported,Supported" newline rbitfld.long 0x00 22. "L1CECCPP,L1 Cache ECC and Parity protection" "Not supported,Supported" bitfld.long 0x00 21. "ECCPPEN,ECC and parity enable" "Disabled,Enabled" bitfld.long 0x00 20. "DIECCE,Data inline ECC enable" "Disabled,Enabled" newline rbitfld.long 0x00 13. "L2AS,L2 arbitration slice" "Not present,Present" rbitfld.long 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not present,Present" rbitfld.long 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not present,1 present,2 present,?..." newline bitfld.long 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle" bitfld.long 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles" rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "0 cycle,1 cycle" newline bitfld.long 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,6 cycles,6 cycles" group.long c15:0x1309++0x00 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.long c15:0x100F++0x00 line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register" bitfld.long 0x00 30.--31. "L2PLRUIP,Select the L2 PLRU insertion point" "MRU/LRU,MRU,3/4 LRU,LRU" bitfld.long 0x00 29. "L2RPLCPOL,Select the L2 cache replacement policy" "PLRU,Pseudo random" bitfld.long 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled" newline bitfld.long 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled" bitfld.long 0x00 26. "FL2GICRCGEA,Force L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced" bitfld.long 0x00 25. "ESIAA,Enable single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled" newline bitfld.long 0x00 24. "L2PLRUMD,Disable PLRU dynamic insertion and update policy" "No,Yes" bitfld.long 0x00 23. "DACPMUWLU,Disable ACP MakeUnique and WriteLineUnique transactions" "No,Yes" bitfld.long 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes" newline bitfld.long 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit" bitfld.long 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes" bitfld.long 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled" newline bitfld.long 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes" bitfld.long 0x00 14. "EUCE,Enable UniqueClean evictions with data" "Disabled,Enabled" bitfld.long 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes" newline bitfld.long 0x00 12. "DPSHO,Disable set hazard optimization against prefetch entries" "No,Yes" bitfld.long 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes" bitfld.long 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes" newline bitfld.long 0x00 9. "DWHOBBRRQ,Disable set/way hazard optimization on back to back reads from the same CPU targeting the same set" "No,Yes" bitfld.long 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes" bitfld.long 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled" newline bitfld.long 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes" bitfld.long 0x00 5. "DSWHOWWM,Disables set/way hazard optimization for WBNA/WT memory" "No,Yes" bitfld.long 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled" newline bitfld.long 0x00 3. "DCEPTE,Disable clean/evict push to external" "No,Yes" bitfld.long 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited" bitfld.long 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled" newline bitfld.long 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes" group.quad c15:0x130F0++0x01 line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index" tree.end tree.end tree "System Performance Monitor" group.long c15:0xc9++0x00 line.long 0x00 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code" rbitfld.long 0x00 11.--15. "N,Number of counters implemented" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes" bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled" bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle" bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset" newline bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset" bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled" newline group.long c15:0x1c9++0x00 line.long 0x00 "PMCNTENSET,Count Enable Set Register " bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled" bitfld.long 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled" bitfld.long 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled" bitfld.long 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled" group.long c15:0x2c9++0x00 line.long 0x00 "PMCNTENCLR,Count Enable Clear Register" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" newline eventfld.long 0x00 5. "P5,Event Counter 5 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 4. "P4,Event Counter 4 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 3. "P3,Event Counter 3 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.long 0x00 2. "P2,Event Counter 2 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 1. "P1,Event Counter 1 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 0. "P0,Event Counter 0 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" group.long c15:0x3c9++0x00 line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register" eventfld.long 0x00 31. "C,PMCCNTR overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" newline eventfld.long 0x00 5. "P5,PMN5 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 4. "P4,PMN4 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 3. "P3,PMN3 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" newline eventfld.long 0x00 2. "P2,PMN2 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 1. "P1,PMN1 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 0. "P0,PMN0 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" group.long c15:0x4c9++0x00 line.long 0x00 "PMSWINC,Performance Monitor Software Increment" bitfld.long 0x00 5. "P5,Increment PMN5" "No action,Increment" bitfld.long 0x00 4. "P4,Increment PMN4" "No action,Increment" bitfld.long 0x00 3. "P3,Increment PMN3" "No action,Increment" newline bitfld.long 0x00 2. "P2,Increment PMN2" "No action,Increment" bitfld.long 0x00 1. "P1,Increment PMN1" "No action,Increment" bitfld.long 0x00 0. "P0,Increment PMN0" "No action,Increment" group.long c15:0x5c9++0x00 line.long 0x00 "PMSELR,Performance Monitor Select Register" bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..." group.long c15:0xd9++0x00 line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register" group.long c15:0x1d9++0x00 line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register" group.long c15:0x2d9++0x00 line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register" bitfld.long 0x00 5. "EVENT[5],Value of 5 event counter" "0,1" bitfld.long 0x00 4. "EVENT[4],Value of 4 event counter" "0,1" bitfld.long 0x00 3. "EVENT[3],Value of 3 event counter" "0,1" newline bitfld.long 0x00 2. "EVENT[2],Value of 2 event counter" "0,1" bitfld.long 0x00 1. "EVENT[1],Value of 1 event counter" "0,1" bitfld.long 0x00 0. "EVENT[0],Value of 0 event counter" "0,1" newline group.long c15:0xe9++0x00 line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register" bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.long 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled" bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" newline bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled" group.long c15:0x1e9++0x00 line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.long c15:0x2e9++0x00 line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear" eventfld.long 0x00 31. "C,PMCCNTR enable [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.long 0x00 5. "P5,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 4. "P4,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 3. "P3,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.long 0x00 2. "P2,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 1. "P1,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 0. "P0,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" group.long c15:0x3e9++0x00 line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register" group.long c15:0x8E++0x00 line.long 0x00 "PMEVCNTR0,Performance Monitors Event Count Register 0" group.long c15:(0x8E+0x40)++0x00 line.long 0x00 "PMEVTYPER0,Performance Monitors Selected Event Type Register 0" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x18E++0x00 line.long 0x00 "PMEVCNTR1,Performance Monitors Event Count Register 1" group.long c15:(0x18E+0x40)++0x00 line.long 0x00 "PMEVTYPER1,Performance Monitors Selected Event Type Register 1" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x28E++0x00 line.long 0x00 "PMEVCNTR2,Performance Monitors Event Count Register 2" group.long c15:(0x28E+0x40)++0x00 line.long 0x00 "PMEVTYPER2,Performance Monitors Selected Event Type Register 2" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x38E++0x00 line.long 0x00 "PMEVCNTR3,Performance Monitors Event Count Register 3" group.long c15:(0x38E+0x40)++0x00 line.long 0x00 "PMEVTYPER3,Performance Monitors Selected Event Type Register 3" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x48E++0x00 line.long 0x00 "PMEVCNTR4,Performance Monitors Event Count Register 4" group.long c15:(0x48E+0x40)++0x00 line.long 0x00 "PMEVTYPER4,Performance Monitors Selected Event Type Register 4" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x58E++0x00 line.long 0x00 "PMEVCNTR5,Performance Monitors Event Count Register 5" group.long c15:(0x58E+0x40)++0x00 line.long 0x00 "PMEVTYPER5,Performance Monitors Selected Event Type Register 5" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x07FE++0x00 line.long 0x00 "PMCCFILTR,Performance Monitors Cycle Count Filter Register" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" tree.end tree "System Timer Registers" group.long c15:0x000E++0x00 line.long 0x00 "CNTFRQ,Counter Frequency Register" rgroup.quad c15:0x100E0++0x01 line.quad 0x00 "CNTPCT,Counter Physical Count Register" group.long c15:0x001E++0x00 line.long 0x00 "CNTKCTL,Timer PL1 Control Register" bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" newline bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.long c15:0x002E++0x00 line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Compare Value Register" group.long c15:0x012E++0x00 line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.long c15:0x003E++0x00 line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register" group.long c15:0x013E++0x00 line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x110E0++0x01 line.quad 0x00 "CNTVCT,Counter Virtual Count Register" group.quad c15:0x120E0++0x01 line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register" group.quad c15:0x130E0++0x01 line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register" group.quad c15:0x140E0++0x01 line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register" group.long c15:0x401E++0x00 line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register" bitfld.long 0x00 4.--7. "EVNTI,Select trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" newline bitfld.long 0x00 1. "EL1VCTEN,Controls whether the Non-secure copies of the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL1PCTEN,Controls whether the physical counter, CNTPCT, is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" group.long c15:0x402E++0x00 line.long 0x00 "CNTHP_TVAL,Counter Non-secure PL2 Physical Timer Value Register" group.long c15:0x412E++0x00 line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x160E0++0x01 line.quad 0x00 "CNTHP_CVAL,Counter Non-secure PL2 Physical Compare Value Register" tree.end tree "Generic Interrupt Controller CPU Interface" tree "AArch32 GIC Physical CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.long c15:0x048C++0x00 line.long 0x00 "ICC_AP0R0,Active Priorities 0 Register 0" bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:0x009C++0x00 line.long 0x00 "ICC_AP1R0,Active Priorities 1 Register 0" bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline wgroup.quad c15:0x110C0++0x01 line.quad 0x00 "ICC_ASGI1R,Alternate SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" group.long c15:0x038C++0x00 line.long 0x00 "ICC_BPR0,Binary Point Register 0" bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7" group.long c15:0x03CC++0x00 line.long 0x00 "ICC_BPR1,Binary Point Register 1" bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7" group.long c15:0x04CC++0x00 line.long 0x00 "ICC_CTLR,Interrupt Control Registers for EL1" rbitfld.long 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported" rbitfld.long 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.long 0x00 14. "SEIS,SEI Support" "Not supported,Supported" rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" bitfld.long 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1" newline bitfld.long 0x00 0. "CBPR,Common Binary Point Register" "0,1" group.long c15:0x64CC++0x00 line.long 0x00 "ICC_MCTLR,Interrupt Control Registers for EL3" rbitfld.long 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported" rbitfld.long 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.long 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported" rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported" newline rbitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." rbitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Non-secure EL1 and EL2)" "Enabled,Disabled" bitfld.long 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Secure EL1)" "Enabled,Disabled" bitfld.long 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt register also deactivates the interrupt(EL3)" "Enabled,Disabled" newline bitfld.long 0x00 1. "CBPR_EL1NS,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same register" bitfld.long 0x00 0. "CBPR_EL1S,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same register" wgroup.long c15:0x01BC++0x00 line.long 0x00 "ICC_DIR,Deactivate Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.long c15:0x018C++0x00 line.long 0x00 "ICC_EOIR0,End Of Interrupt Register 0" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.long c15:0x01CC++0x00 line.long 0x00 "ICC_EOIR1,End Of Interrupt Register 1" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access." rgroup.long c15:0x028C++0x00 line.long 0x00 "ICC_HPPIR0,Highest Prioity Pending Interrupt Register 0" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt" rgroup.long c15:0x02CC++0x00 line.long 0x00 "ICC_HPPIR1,Highest Prioity Pending Interrupt Register 1" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt" hgroup.long c15:0x008C++0x00 hide.long 0x00 "ICC_IAR0,Interrupt Acknowledge Register 0" in hgroup.long c15:0x00CC++0x00 hide.long 0x00 "ICC_IAR1,Interrupt Acknowledge Register 1" in group.long c15:0x06CC++0x00 line.long 0x00 "ICC_IGRPEN0,Interrupt Group Enable Register 0" bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled" group.long c15:0x07CC++0x00 line.long 0x00 "ICC_IGRPEN1,Interrupt Group Enable Register 1" bitfld.long 0x00 0. "ENABLE,Enables Group 1 interrupts" "Disabled,Enabled" group.long c15:0x0064++0x00 line.long 0x00 "ICC_PMR,Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface" rgroup.long c15:0x03BC++0x00 line.long 0x00 "ICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" wgroup.quad c15:0x120C0++0x01 line.quad 0x00 "ICC_SGI0R,SGI Generation Register 0" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" wgroup.quad c15:0x100C0++0x01 line.quad 0x00 "ICC_SGI1R,SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" group.long c15:0x05CC++0x00 line.long 0x00 "ICC_SRE,System Register Enable Register for EL1" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.long c15:0x65CC++0x00 line.long 0x00 "ICC_MSRE,System Register Enable Register for EL3" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Disabled,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.long c15:0x67CC++0x00 line.long 0x00 "ICC_MGRPEN1,Monitor Group1 Interrupt Group Enable" bitfld.long 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled" bitfld.long 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled" tree.end tree "AArch32 Virtual Interface Control System Registers" tree.open "Interrupt Controller Hypervisor Active Priorities Registers" group.long c15:0x408C++0x00 line.long 0x00 "ICH_AP0R0,Interrupt Controller Hypervisor Active Priorities Register 0-0" bitfld.long 0x00 31. "P31,Group 0 interrupt active priority 31" "0,1" bitfld.long 0x00 30. "P30,Group 0 interrupt active priority 30" "0,1" bitfld.long 0x00 29. "P29,Group 0 interrupt active priority 29" "0,1" bitfld.long 0x00 28. "P28,Group 0 interrupt active priority 28" "0,1" newline bitfld.long 0x00 27. "P27,Group 0 interrupt active priority 27" "0,1" bitfld.long 0x00 26. "P26,Group 0 interrupt active priority 26" "0,1" bitfld.long 0x00 25. "P25,Group 0 interrupt active priority 25" "0,1" bitfld.long 0x00 24. "P24,Group 0 interrupt active priority 24" "0,1" newline bitfld.long 0x00 23. "P23,Group 0 interrupt active priority 23" "0,1" bitfld.long 0x00 22. "P22,Group 0 interrupt active priority 22" "0,1" bitfld.long 0x00 21. "P21,Group 0 interrupt active priority 21" "0,1" bitfld.long 0x00 20. "P20,Group 0 interrupt active priority 20" "0,1" newline bitfld.long 0x00 19. "P19,Group 0 interrupt active priority 19" "0,1" bitfld.long 0x00 18. "P18,Group 0 interrupt active priority 18" "0,1" bitfld.long 0x00 17. "P17,Group 0 interrupt active priority 17" "0,1" bitfld.long 0x00 16. "P16,Group 0 interrupt active priority 16" "0,1" newline bitfld.long 0x00 15. "P15,Group 0 interrupt active priority 15" "0,1" bitfld.long 0x00 14. "P14,Group 0 interrupt active priority 14" "0,1" bitfld.long 0x00 13. "P13,Group 0 interrupt active priority 13" "0,1" bitfld.long 0x00 12. "P12,Group 0 interrupt active priority 12" "0,1" newline bitfld.long 0x00 11. "P11,Group 0 interrupt active priority 11" "0,1" bitfld.long 0x00 10. "P10,Group 0 interrupt active priority 10" "0,1" bitfld.long 0x00 9. "P9,Group 0 interrupt active priority 9" "0,1" bitfld.long 0x00 8. "P8,Group 0 interrupt active priority 8" "0,1" newline bitfld.long 0x00 7. "P7,Group 0 interrupt active priority 7" "0,1" bitfld.long 0x00 6. "P6,Group 0 interrupt active priority 6" "0,1" bitfld.long 0x00 5. "P5,Group 0 interrupt active priority 5" "0,1" bitfld.long 0x00 4. "P4,Group 0 interrupt active priority 4" "0,1" newline bitfld.long 0x00 3. "P3,Group 0 interrupt active priority 3" "0,1" bitfld.long 0x00 2. "P2,Group 0 interrupt active priority 2" "0,1" bitfld.long 0x00 1. "P1,Group 0 interrupt active priority 1" "0,1" bitfld.long 0x00 0. "P0,Group 0 interrupt active priority 0" "0,1" group.long c15:0x409C++0x00 line.long 0x00 "ICH_AP1R0,Interrupt Controller Hypervisor Active Priorities Register 1-0" bitfld.long 0x00 31. "P31,Group 1 interrupt active priority 31" "0,1" bitfld.long 0x00 30. "P30,Group 1 interrupt active priority 30" "0,1" bitfld.long 0x00 29. "P29,Group 1 interrupt active priority 29" "0,1" bitfld.long 0x00 28. "P28,Group 1 interrupt active priority 28" "0,1" newline bitfld.long 0x00 27. "P27,Group 1 interrupt active priority 27" "0,1" bitfld.long 0x00 26. "P26,Group 1 interrupt active priority 26" "0,1" bitfld.long 0x00 25. "P25,Group 1 interrupt active priority 25" "0,1" bitfld.long 0x00 24. "P24,Group 1 interrupt active priority 24" "0,1" newline bitfld.long 0x00 23. "P23,Group 1 interrupt active priority 23" "0,1" bitfld.long 0x00 22. "P22,Group 1 interrupt active priority 22" "0,1" bitfld.long 0x00 21. "P21,Group 1 interrupt active priority 21" "0,1" bitfld.long 0x00 20. "P20,Group 1 interrupt active priority 20" "0,1" newline bitfld.long 0x00 19. "P19,Group 1 interrupt active priority 19" "0,1" bitfld.long 0x00 18. "P18,Group 1 interrupt active priority 18" "0,1" bitfld.long 0x00 17. "P17,Group 1 interrupt active priority 17" "0,1" bitfld.long 0x00 16. "P16,Group 1 interrupt active priority 16" "0,1" newline bitfld.long 0x00 15. "P15,Group 1 interrupt active priority 15" "0,1" bitfld.long 0x00 14. "P14,Group 1 interrupt active priority 14" "0,1" bitfld.long 0x00 13. "P13,Group 1 interrupt active priority 13" "0,1" bitfld.long 0x00 12. "P12,Group 1 interrupt active priority 12" "0,1" newline bitfld.long 0x00 11. "P11,Group 1 interrupt active priority 11" "0,1" bitfld.long 0x00 10. "P10,Group 1 interrupt active priority 10" "0,1" bitfld.long 0x00 9. "P9,Group 1 interrupt active priority 9" "0,1" bitfld.long 0x00 8. "P8,Group 1 interrupt active priority 8" "0,1" newline bitfld.long 0x00 7. "P7,Group 1 interrupt active priority 7" "0,1" bitfld.long 0x00 6. "P6,Group 1 interrupt active priority 6" "0,1" bitfld.long 0x00 5. "P5,Group 1 interrupt active priority 5" "0,1" bitfld.long 0x00 4. "P4,Group 1 interrupt active priority 4" "0,1" newline bitfld.long 0x00 3. "P3,Group 1 interrupt active priority 3" "0,1" bitfld.long 0x00 2. "P2,Group 1 interrupt active priority 2" "0,1" bitfld.long 0x00 1. "P1,Group 1 interrupt active priority 1" "0,1" bitfld.long 0x00 0. "P0,Group 1 interrupt active priority 0" "0,1" tree.end newline rgroup.long c15:0x43BC++0x00 line.long 0x00 "ICH_EISR,Interrupt Controller End of Interrupt Status Register" bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt" newline bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt" rgroup.long c15:0x45BC++0x00 line.long 0x00 "ICH_ELRSR,Interrupt Controller Empty List Register Status Register" bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt" bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt" bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt" newline bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt" group.long c15:0x40BC++0x00 line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register" bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped" bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped" newline bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" newline bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" group.long c15:(0x40CC+0x0)++0x00 line.long 0x00 "ICH_LR0,Interrupt Controller List Register 0" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x100)++0x00 line.long 0x00 "ICH_LR1,Interrupt Controller List Register 1" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x200)++0x00 line.long 0x00 "ICH_LR2,Interrupt Controller List Register 2" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x300)++0x00 line.long 0x00 "ICH_LR3,Interrupt Controller List Register 3" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40EC+0x0)++0x00 line.long 0x00 "ICH_LRC0,Interrupt Controller List Register Extension 0" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x100)++0x00 line.long 0x00 "ICH_LRC1,Interrupt Controller List Register Extension 1" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x200)++0x00 line.long 0x00 "ICH_LRC2,Interrupt Controller List Register Extension 2" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x300)++0x00 line.long 0x00 "ICH_LRC3,Interrupt Controller List Register Extension 3" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" rgroup.long c15:0x42BC++0x00 line.long 0x00 "ICH_MISR,Interrupt Controller Maintenance Interrupt State Register" bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted" bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted" bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted" newline bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted" bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted" bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted" newline bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted" bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted" group.long c15:0x459C++0x00 line.long 0x00 "ICH_SRE,Hypervisor System Register" group.long c15:0x47BC++0x00 line.long 0x00 "ICH_VMCR,Interrupt Controller Virtual Machine Control Register" hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface" bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" newline bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled" bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register" bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs" newline bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt" bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled" group.long c15:0x449C++0x00 line.long 0x00 "ICH_VSEIR,Virtual System Error Interrupt Register" rgroup.long c15:0x41BC++0x00 line.long 0x00 "ICH_VTR,Interrupt Controller VGIC Type Register" bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported" bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported" newline bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported" bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree.end tree "Debug Registers" tree "Coresight Management Registers" rgroup.long c14:0x0000++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "Reserved,Reserved,Reserved,4,?..." bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "Reserved,2,?..." newline bitfld.long 0x0 16.--19. "VERSION,Debug Architecture Version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8,?..." bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Reserved,Not implemented" bitfld.long 0x0 12. "SE,Security Extensions implemented" "Reserved,Implemented" group.long c14:0x0070++0x0 line.long 0x00 "DBGVCR,Debug Vector Catch register" bitfld.long 0x00 31. "FIQVCE_NS,FIQ vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 30. "IRQVCE_NS,IRG vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 28. "DAVCE_NS,Data Abort vector catch in Non-secure state" "Disabled,Enabled" newline bitfld.long 0x00 27. "PAVCE_NS,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 26. "SVCVCE_NS,SVC vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 25. "UIVCE_NS,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled" newline bitfld.long 0x00 15. "FIQVCE_SM,FIQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 14. "IRQVCE_SM,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 12. "DAVCE_SM,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" newline bitfld.long 0x00 11. "PAVCE_SM,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 10. "SMCVCE_S,SMC vector catch enable in Secure state" "Disabled,Enabled" bitfld.long 0x00 7. "FIQVCE_S,FIQ vector catch in Secure state" "Disabled,Enabled" newline bitfld.long 0x00 6. "IRQVCE_S,IRG vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 4. "DAVCE_S,Data Abort vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 3. "PAVCE_S,Prefetch Abort vector catch in Secure state" "Disabled,Enabled" newline bitfld.long 0x00 2. "SVCVCE_S,SVC vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 1. "UIVCE_S,Undefined instruction vector catch in Secure state" "Disabled,Enabled" group.long c14:0x0020++0x00 line.long 0x00 "DBGDCCINT,DCC Interrupt Enable Register" bitfld.long 0x00 30. "RX,DCC interrupt request enable control for DTRRX" "Disabled,Enabled" bitfld.long 0x00 29. "TX,DCC interrupt request enable control for DTRTX" "Disabled,Enabled" group.long c14:0x0200++0x0 line.long 0x00 "DBGDTRRXEXT,Debug Receive Register (External View)" hgroup.long c14:0x0050++0x0 hide.long 0x00 "DBGDTRRXINT,Debug Receive Register (Internal View)" in group.long c14:0x0220++0x0 line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. "RXO,Used for save/restore of EDSCR.RXO" "Disabled,Enabled" newline bitfld.long 0x00 26. "TXU,Used for save/restore of EDSCR.TXU" "Disabled,Enabled" bitfld.long 0x00 22.--23. "INTDIS,Used for save/restore of EDSCR.INTdis" "0,1,2,3" bitfld.long 0x00 21. "TDA,Used for save/restore of EDSCR.TDA" "Disabled,Enabled" newline bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes" newline bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" bitfld.long 0x00 14. "HDE,Used for save/restore of EDSCR.HDE" "Disabled,Enabled" bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes" newline bitfld.long 0x00 6. "ERR,Used for save/restore of EDSCR.ERR" "Disabled,Enabled" bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." rgroup.long c14:0x0010++0x0 line.long 0x00 "DBGDSCRINT,Debug Status and Control Register (Internal View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" newline bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" newline bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes" bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." wgroup.long c14:0x0230++0x0 line.long 0x00 "DBGDTRTXEXT,Debug Transmit Register (External View)" group.long c14:0x0050++0x0 line.long 0x00 "DBGDTRTXINT,Debug Transmit/Receive Register (Internal View)" group.long c14:0x0687++0x0 line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register" bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set" bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set" bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set" newline bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set" bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set" bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set" newline bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set" bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set" group.long c14:0x0697++0x0 line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register" bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared" bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared" newline bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared" bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared" newline bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared" if (((per.l(c14:0x06E7))&0xAA)==0xAA) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0xA8) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.l(c14:0x06E7))&0xAA)==0xA2) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0xA0) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.l(c14:0x06E7))&0xAA)==0x8A) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0x88) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.l(c14:0x06E7))&0xAA)==0x82) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0x80) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.l(c14:0x06E7))&0xAA)==0x2A) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0x28) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.l(c14:0x06E7))&0xAA)==0x22) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0x20) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.l(c14:0x06E7))&0xAA)==0x0A) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0x08) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.l(c14:0x06E7))&0xAA)==0x02) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0x00) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" endif rgroup.long c14:0x0707++0x0 line.long 0x0 "DBGDEVID2,Debug Device ID Register 2" rgroup.long c14:0x0717++0x0 line.long 0x0 "DBGDEVID1,Debug Device ID Register 1" bitfld.long 0x00 0.--3. "PCSROFFSET,This field defines the offset applied to DBGPCSR samples" ",,No offset,?..." rgroup.long c14:0x0727++0x00 line.long 0x00 "DBGDEVID,Debug Device ID Register 0" bitfld.long 0x00 28.--31. "CIDMASK,Specifies the level of support for the Context ID matching breakpoint masking capability" "Not implemented,?..." bitfld.long 0x00 24.--27. "AUXREGS,Specifies support for the Debug External Auxiliary Control Register" ",Supported,?..." bitfld.long 0x00 20.--23. "DOUBLELOCK,Specifies support for the Debug OS Double Lock Register" "Reserved,Implemented,?..." newline bitfld.long 0x00 16.--19. "VIREXTNS,Specifies whether EL2 is implemented" "Reserved,Implemented,?..." bitfld.long 0x00 12.--15. "VECTORCATCH,Defines the form of the vector catch event implemented" "Implemented,?..." bitfld.long 0x00 8.--11. "BPADDRMASK,Indicates the level of support for the Immediate Virtual Address(IVA) matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" newline bitfld.long 0x00 4.--7. "WPADDRMASK,Indicates the level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..." bitfld.long 0x00 0.--3. "PCSAMPLE,Indicates the level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..." tree.end newline rgroup.quad c14:0x10010++0x1 line.quad 0x0 "DBGDRAR,Debug ROM Address Register" hexmask.quad 0x0 12.--47. 0x10 "ROMADDR,ROM physical address" bitfld.quad 0x0 0.--1. "VALID,ROM table address valid" "Not valid,,,Valid" rgroup.quad c14:0x10020++0x1 line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register" wgroup.long c14:0x0401++0x00 line.long 0x00 "DBGOSLAR,Operating System Lock Access Register" rgroup.long c14:0x0411++0x00 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 2. "NTT,32-Bit Access" "Not required,Required" bitfld.long 0x00 1. "OSLK,Status of the OS Lock" "Not locked,Locked" bitfld.long 0x00 0. 3. "OSLM,OS Lock Model implemented Bit" "Reserved,Reserved,Implemented,?..." if (((per.l(c14:0x0411))&0x2)==0x2) group.long c14:0x0260++0x00 line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" else hgroup.long c14:0x0260++0x00 hide.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" endif group.long c14:0x0431++0x00 line.long 0x00 "DBGOSDLR,Debug OS Double Lock Register" bitfld.long 0x00 0. "DLK,OS Double Lock control bit" "Not locked,Locked" group.long c14:0x0441++0x00 line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 0. "CORENPDRQ,Core No Power down Request" "Power down,Emulate" tree.end tree "Breakpoint Registers" tree "Breakpoint 0" if (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x0)++0x0 line.long 0x00 "DBGBVR0,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) hgroup.long c14:(0x0400+0x0)++0x0 hide.long 0x00 "DBGBVR0,Breakpoint Value Register" else group.long c14:(0x0400+0x0)++0x0 line.long 0x00 "DBGBVR0,Breakpoint ContextID Register" endif group.long c14:(0x0500+0x0)++0x0 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..." bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 1" if (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x10)++0x0 line.long 0x00 "DBGBVR1,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) hgroup.long c14:(0x0400+0x10)++0x0 hide.long 0x00 "DBGBVR1,Breakpoint Value Register" else group.long c14:(0x0400+0x10)++0x0 line.long 0x00 "DBGBVR1,Breakpoint ContextID Register" endif group.long c14:(0x0500+0x10)++0x0 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..." bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 2" if (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x20)++0x0 line.long 0x00 "DBGBVR2,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) hgroup.long c14:(0x0400+0x20)++0x0 hide.long 0x00 "DBGBVR2,Breakpoint Value Register" else group.long c14:(0x0400+0x20)++0x0 line.long 0x00 "DBGBVR2,Breakpoint ContextID Register" endif group.long c14:(0x0500+0x20)++0x0 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..." bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 3" if (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x30)++0x0 line.long 0x00 "DBGBVR3,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) hgroup.long c14:(0x0400+0x30)++0x0 hide.long 0x00 "DBGBVR3,Breakpoint Value Register" else group.long c14:(0x0400+0x30)++0x0 line.long 0x00 "DBGBVR3,Breakpoint ContextID Register" endif group.long c14:(0x0500+0x30)++0x0 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..." bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 4" if (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x40)++0x0 line.long 0x00 "DBGBVR4,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) hgroup.long c14:(0x0400+0x40)++0x0 hide.long 0x00 "DBGBVR4,Breakpoint Value Register" else group.long c14:(0x0400+0x40)++0x0 line.long 0x00 "DBGBVR4,Breakpoint ContextID Register" endif if (((per.l(c14:(0x500+0x40)))&0x800000)==0x800000) group.long c14:(0x0101+0x40)++0x0 line.long 0x00 "DBGBXVR4,Breakpoint Extended Value Register" hexmask.long.byte 0x00 0.--7. 1. "VAMID,VMID value for comparison" else hgroup.long c14:(0x0101+0x40)++0x0 hide.long 0x00 "DBGBXVR4,Breakpoint Extended Value Register" endif group.long c14:(0x0500+0x40)++0x0 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..." bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 5" if (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x50)++0x0 line.long 0x00 "DBGBVR5,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) hgroup.long c14:(0x0400+0x50)++0x0 hide.long 0x00 "DBGBVR5,Breakpoint Value Register" else group.long c14:(0x0400+0x50)++0x0 line.long 0x00 "DBGBVR5,Breakpoint ContextID Register" endif if (((per.l(c14:(0x500+0x50)))&0x800000)==0x800000) group.long c14:(0x0101+0x50)++0x0 line.long 0x00 "DBGBXVR5,Breakpoint Extended Value Register" hexmask.long.byte 0x00 0.--7. 1. "VAMID,VMID value for comparison" else hgroup.long c14:(0x0101+0x50)++0x0 hide.long 0x00 "DBGBXVR5,Breakpoint Extended Value Register" endif group.long c14:(0x0500+0x50)++0x0 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..." bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" tree.end tree.end tree "Watchpoint Control Registers" tree "Watchpoint 0" group.long c14:(0x0600+0x0)++0x00 line.long 0x00 "DBGWVR0,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x0)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked,Linked" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,?..." newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hyp Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" tree.end tree "Watchpoint 1" group.long c14:(0x0600+0x10)++0x00 line.long 0x00 "DBGWVR1,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x10)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked,Linked" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,?..." newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hyp Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" tree.end tree "Watchpoint 2" group.long c14:(0x0600+0x20)++0x00 line.long 0x00 "DBGWVR2,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x20)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked,Linked" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,?..." newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hyp Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" tree.end tree "Watchpoint 3" group.long c14:(0x0600+0x30)++0x00 line.long 0x00 "DBGWVR3,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x30)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked,Linked" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,?..." newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hyp Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" tree.end tree.end tree.end AUTOINDENT.OFF tree.open "Interrupt Controller (GIC-500)" base COMP.BASE("GICD",-1.) width 17. tree "Distributor Interface" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))) group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)" rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending" bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled" bitfld.long 0x00 6. " DS ,Disable Security" "No,Yes" textline " " bitfld.long 0x00 5. " ARE_NS ,Affinity Routing Enable" "Disabled,Enabled" bitfld.long 0x00 4. " ARE_S ,Affinity Routing Enable" "Disabled,Enabled" bitfld.long 0x00 2. " ENABLEGRP1S ,Enable Secure Group 1 interrupts" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ENABLEGRP1NS ,Enable Secure Group 1 interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enable Group 0 interrupts" "Disabled,Enabled" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400) group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Non-secure access)" rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending" bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled" bitfld.long 0x00 4. " ARE_NS ,Affinity Routing Enable" "Reserved,Enabled" textline " " bitfld.long 0x00 1. " ENABLEGRP1A ,Enable Group 1 interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register" rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending" bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled" rbitfld.long 0x00 6. " DS ,Disable Security" "Reserved,Yes" textline " " bitfld.long 0x00 4. " ARE ,Affinity Routing Enable" "Reserved,Enabled" bitfld.long 0x00 1. " ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enable Group 0 interrupts" "Disabled,Enabled" endif rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 25. " NO1N ,Indicates whether 1 of N SPI interrupts are supported" "Supported,Not supported" bitfld.long 0x00 24. " A3V ,Indicates whether the Distributor supports nonzero values of Affinity level 3" "Not supported,Supported" bitfld.long 0x00 19.--23. " IDBITS ,The number of interrupt identifier bits supported" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..." textline " " bitfld.long 0x00 17. " LPIS ,Indicates whether the implementation supports LPIs" "Not supported,Supported" bitfld.long 0x00 16. " MBIS ,Indicates whether the implementation supports message-based interrupts by writing to Distributor registers" "Not supported,Supported" bitfld.long 0x00 10. " SECURITYEXTN ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Reports the number of PEs that can be used when affinity routing is not enabled" "1,2,3,4,5,6,7,8" bitfld.long 0x00 0.--4. " ITLN ,Indicates the maximum SPI INTID that the GIC implementation supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Reserved" rgroup.long 0x0008++0x03 line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x10000)==0x10000) wgroup.long 0x40++0x03 line.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" wgroup.long 0x48++0x03 line.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x50)) wgroup.long 0x50++0x03 line.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Secure access)" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" else hgroup.long 0x50++0x03 hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Non-secure access)" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x58)) wgroup.long 0x58++0x03 line.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Secure access)" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" else hgroup.long 0x58++0x03 hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Non-secure access)" endif else hgroup.long 0x40++0x03 hide.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register" hgroup.long 0x48++0x03 hide.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register" hgroup.long 0x50++0x03 hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register" hgroup.long 0x58++0x03 hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register" endif width 17. tree "Group Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0080)) group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Secure Access)" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Secure,Non-secure Group 1" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00) group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" else hgroup.long 0x0080++0x03 hide.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x84))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 (Secure Access)" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 " bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1" else hgroup.long 0x0084++0x03 hide.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x88))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 (Secure Access)" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 " bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1" else hgroup.long 0x0088++0x03 hide.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x8C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 (Secure Access)" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 " bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1" else hgroup.long 0x008C++0x03 hide.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x90))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 (Secure Access)" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 " bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1" else hgroup.long 0x0090++0x03 hide.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x94))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 (Secure Access)" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 " bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1" else hgroup.long 0x0094++0x03 hide.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x98))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 (Secure Access)" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 " bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1" else hgroup.long 0x0098++0x03 hide.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x9C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 (Secure Access)" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 " bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1" else hgroup.long 0x009C++0x03 hide.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 (Secure Access)" bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 " bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0,Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0,Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0,Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0,Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0,Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0,Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0,Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0,Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0,Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0,Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0,Group 1" else hgroup.long 0x00A0++0x03 hide.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 (Secure Access)" bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 " bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0,Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0,Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0,Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0,Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0,Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0,Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0,Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0,Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0,Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0,Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0,Group 1" else hgroup.long 0x00A4++0x03 hide.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Secure Access)" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0,Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0,Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0,Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0,Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0,Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0,Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0,Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0,Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0,Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0,Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0,Group 1" else hgroup.long 0x00A8++0x03 hide.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xAC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Secure Access)" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0,Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0,Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0,Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0,Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0,Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0,Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0,Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0,Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0,Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0,Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0,Group 1" else hgroup.long 0x00AC++0x03 hide.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Secure Access)" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0,Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0,Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0,Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0,Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0,Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0,Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0,Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0,Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0,Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0,Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0,Group 1" else hgroup.long 0x00B0++0x03 hide.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Secure Access)" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0,Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0,Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0,Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0,Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0,Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0,Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0,Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0,Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0,Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0,Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0,Group 1" else hgroup.long 0x00B4++0x03 hide.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Secure Access)" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0,Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0,Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0,Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0,Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0,Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0,Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0,Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0,Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0,Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0,Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0,Group 1" else hgroup.long 0x00B8++0x03 hide.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xBC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Secure Access)" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0,Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0,Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0,Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0,Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0,Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0,Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0,Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0,Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0,Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0,Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0,Group 1" else hgroup.long 0x00BC++0x03 hide.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Secure Access)" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0,Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0,Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0,Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0,Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0,Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0,Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0,Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0,Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0,Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0,Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0,Group 1" else hgroup.long 0x00C0++0x03 hide.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Secure Access)" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0,Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0,Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0,Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0,Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0,Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0,Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0,Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0,Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0,Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0,Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0,Group 1" else hgroup.long 0x00C4++0x03 hide.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Secure Access)" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0,Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0,Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0,Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0,Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0,Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0,Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0,Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0,Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0,Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0,Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0,Group 1" else hgroup.long 0x00C8++0x03 hide.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xCC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Secure Access)" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0,Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0,Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0,Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0,Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0,Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0,Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0,Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0,Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0,Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0,Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0,Group 1" else hgroup.long 0x00CC++0x03 hide.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Secure Access)" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0,Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0,Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0,Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0,Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0,Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0,Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0,Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0,Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0,Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0,Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0,Group 1" else hgroup.long 0x00D0++0x03 hide.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Secure Access)" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0,Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0,Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0,Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0,Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0,Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0,Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0,Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0,Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0,Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0,Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0,Group 1" else hgroup.long 0x00D4++0x03 hide.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Secure Access)" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0,Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0,Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0,Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0,Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0,Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0,Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0,Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0,Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0,Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0,Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0,Group 1" else hgroup.long 0x00D8++0x03 hide.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xDC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Secure Access)" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0,Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0,Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0,Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0,Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0,Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0,Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0,Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0,Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0,Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0,Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0,Group 1" else hgroup.long 0x00DC++0x03 hide.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Secure Access)" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0,Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0,Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0,Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0,Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0,Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0,Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0,Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0,Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0,Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0,Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0,Group 1" else hgroup.long 0x00E0++0x03 hide.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Secure Access)" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0,Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0,Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0,Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0,Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0,Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0,Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0,Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0,Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0,Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0,Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0,Group 1" else hgroup.long 0x00E4++0x03 hide.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Secure Access)" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0,Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0,Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0,Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0,Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0,Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0,Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0,Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0,Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0,Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0,Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0,Group 1" else hgroup.long 0x00E8++0x03 hide.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Secure Access)" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0,Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0,Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0,Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0,Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0,Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0,Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0,Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0,Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0,Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0,Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0,Group 1" else hgroup.long 0x00EC++0x03 hide.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Secure Access)" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0,Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0,Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0,Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0,Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0,Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0,Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0,Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0,Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0,Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0,Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0,Group 1" else hgroup.long 0x00F0++0x03 hide.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Secure Access)" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0,Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0,Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0,Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0,Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0,Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0,Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0,Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0,Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0,Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0,Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0,Group 1" else hgroup.long 0x00F4++0x03 hide.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Secure Access)" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0,Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0,Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0,Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0,Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0,Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0,Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0,Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0,Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0,Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0,Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0,Group 1" else hgroup.long 0x00F8++0x03 hide.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" endif tree.end width 24. tree "Set/Clear Enable Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0100++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" newline newline newline newline newline newline newline newline newline newline else group.long 0x0100++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB15 ,Set/Clear Enable Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB14 ,Set/Clear Enable Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13 ,Set/Clear Enable Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB12 ,Set/Clear Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB11 ,Set/Clear Enable Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10 ,Set/Clear Enable Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB9 ,Set/Clear Enable Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB8 ,Set/Clear Enable Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7 ,Set/Clear Enable Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB6 ,Set/Clear Enable Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB5 ,Set/Clear Enable Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4 ,Set/Clear Enable Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB3 ,Set/Clear Enable Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB2 ,Set/Clear Enable Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1 ,Set/Clear Enable Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB0 ,Set/Clear Enable Bit 0" "Disabled,Enabled" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63 ,Set/Clear Enable Bit 63" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB62 ,Set/Clear Enable Bit 62" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB61 ,Set/Clear Enable Bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60 ,Set/Clear Enable Bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB59 ,Set/Clear Enable Bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB58 ,Set/Clear Enable Bit 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57 ,Set/Clear Enable Bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB56 ,Set/Clear Enable Bit 56" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB55 ,Set/Clear Enable Bit 55" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54 ,Set/Clear Enable Bit 54" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB53 ,Set/Clear Enable Bit 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB52 ,Set/Clear Enable Bit 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51 ,Set/Clear Enable Bit 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB50 ,Set/Clear Enable Bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB49 ,Set/Clear Enable Bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48 ,Set/Clear Enable Bit 48" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB47 ,Set/Clear Enable Bit 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB46 ,Set/Clear Enable Bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45 ,Set/Clear Enable Bit 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB44 ,Set/Clear Enable Bit 44" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB43 ,Set/Clear Enable Bit 43" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42 ,Set/Clear Enable Bit 42" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB41 ,Set/Clear Enable Bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB40 ,Set/Clear Enable Bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39 ,Set/Clear Enable Bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB38 ,Set/Clear Enable Bit 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB37 ,Set/Clear Enable Bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36 ,Set/Clear Enable Bit 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB35 ,Set/Clear Enable Bit 35" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB34 ,Set/Clear Enable Bit 34" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33 ,Set/Clear Enable Bit 33" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB32 ,Set/Clear Enable Bit 32" "Disabled,Enabled" else hgroup.long 0x0104++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95 ,Set/Clear Enable Bit 95" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB94 ,Set/Clear Enable Bit 94" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB93 ,Set/Clear Enable Bit 93" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92 ,Set/Clear Enable Bit 92" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB91 ,Set/Clear Enable Bit 91" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB90 ,Set/Clear Enable Bit 90" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89 ,Set/Clear Enable Bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB88 ,Set/Clear Enable Bit 88" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB87 ,Set/Clear Enable Bit 87" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86 ,Set/Clear Enable Bit 86" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB85 ,Set/Clear Enable Bit 85" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB84 ,Set/Clear Enable Bit 84" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83 ,Set/Clear Enable Bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB82 ,Set/Clear Enable Bit 82" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB81 ,Set/Clear Enable Bit 81" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80 ,Set/Clear Enable Bit 80" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB79 ,Set/Clear Enable Bit 79" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB78 ,Set/Clear Enable Bit 78" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77 ,Set/Clear Enable Bit 77" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB76 ,Set/Clear Enable Bit 76" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB75 ,Set/Clear Enable Bit 75" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74 ,Set/Clear Enable Bit 74" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB73 ,Set/Clear Enable Bit 73" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB72 ,Set/Clear Enable Bit 72" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71 ,Set/Clear Enable Bit 71" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB70 ,Set/Clear Enable Bit 70" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB69 ,Set/Clear Enable Bit 69" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68 ,Set/Clear Enable Bit 68" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB67 ,Set/Clear Enable Bit 67" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB66 ,Set/Clear Enable Bit 66" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65 ,Set/Clear Enable Bit 65" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB64 ,Set/Clear Enable Bit 64" "Disabled,Enabled" else hgroup.long 0x0108++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127 ,Set/Clear Enable Bit 127" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB126 ,Set/Clear Enable Bit 126" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB125 ,Set/Clear Enable Bit 125" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124 ,Set/Clear Enable Bit 124" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB123 ,Set/Clear Enable Bit 123" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB122 ,Set/Clear Enable Bit 122" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121 ,Set/Clear Enable Bit 121" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB120 ,Set/Clear Enable Bit 120" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB119 ,Set/Clear Enable Bit 119" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118 ,Set/Clear Enable Bit 118" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB117 ,Set/Clear Enable Bit 117" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB116 ,Set/Clear Enable Bit 116" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115 ,Set/Clear Enable Bit 115" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB114 ,Set/Clear Enable Bit 114" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB113 ,Set/Clear Enable Bit 113" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112 ,Set/Clear Enable Bit 112" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB111 ,Set/Clear Enable Bit 111" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB110 ,Set/Clear Enable Bit 110" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109 ,Set/Clear Enable Bit 109" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB108 ,Set/Clear Enable Bit 108" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB107 ,Set/Clear Enable Bit 107" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106 ,Set/Clear Enable Bit 106" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB105 ,Set/Clear Enable Bit 105" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB104 ,Set/Clear Enable Bit 104" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103 ,Set/Clear Enable Bit 103" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB102 ,Set/Clear Enable Bit 102" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB101 ,Set/Clear Enable Bit 101" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100 ,Set/Clear Enable Bit 100" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB99 ,Set/Clear Enable Bit 99" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB98 ,Set/Clear Enable Bit 98" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97 ,Set/Clear Enable Bit 97" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB96 ,Set/Clear Enable Bit 96" "Disabled,Enabled" else hgroup.long 0x010C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159 ,Set/Clear Enable Bit 159" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB158 ,Set/Clear Enable Bit 158" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB157 ,Set/Clear Enable Bit 157" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156 ,Set/Clear Enable Bit 156" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB155 ,Set/Clear Enable Bit 155" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB154 ,Set/Clear Enable Bit 154" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153 ,Set/Clear Enable Bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB152 ,Set/Clear Enable Bit 152" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB151 ,Set/Clear Enable Bit 151" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150 ,Set/Clear Enable Bit 150" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB149 ,Set/Clear Enable Bit 149" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB148 ,Set/Clear Enable Bit 148" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147 ,Set/Clear Enable Bit 147" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB146 ,Set/Clear Enable Bit 146" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB145 ,Set/Clear Enable Bit 145" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144 ,Set/Clear Enable Bit 144" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB143 ,Set/Clear Enable Bit 143" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB142 ,Set/Clear Enable Bit 142" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141 ,Set/Clear Enable Bit 141" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB140 ,Set/Clear Enable Bit 140" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB139 ,Set/Clear Enable Bit 139" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138 ,Set/Clear Enable Bit 138" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB137 ,Set/Clear Enable Bit 137" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB136 ,Set/Clear Enable Bit 136" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135 ,Set/Clear Enable Bit 135" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB134 ,Set/Clear Enable Bit 134" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB133 ,Set/Clear Enable Bit 133" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132 ,Set/Clear Enable Bit 132" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB131 ,Set/Clear Enable Bit 131" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB130 ,Set/Clear Enable Bit 130" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129 ,Set/Clear Enable Bit 129" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB128 ,Set/Clear Enable Bit 128" "Disabled,Enabled" else hgroup.long 0x0110++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191 ,Set/Clear Enable Bit 191" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB190 ,Set/Clear Enable Bit 190" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB189 ,Set/Clear Enable Bit 189" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188 ,Set/Clear Enable Bit 188" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB187 ,Set/Clear Enable Bit 187" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB186 ,Set/Clear Enable Bit 186" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185 ,Set/Clear Enable Bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB184 ,Set/Clear Enable Bit 184" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB183 ,Set/Clear Enable Bit 183" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182 ,Set/Clear Enable Bit 182" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB181 ,Set/Clear Enable Bit 181" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB180 ,Set/Clear Enable Bit 180" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179 ,Set/Clear Enable Bit 179" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB178 ,Set/Clear Enable Bit 178" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB177 ,Set/Clear Enable Bit 177" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176 ,Set/Clear Enable Bit 176" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB175 ,Set/Clear Enable Bit 175" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB174 ,Set/Clear Enable Bit 174" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173 ,Set/Clear Enable Bit 173" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB172 ,Set/Clear Enable Bit 172" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB171 ,Set/Clear Enable Bit 171" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170 ,Set/Clear Enable Bit 170" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB169 ,Set/Clear Enable Bit 169" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB168 ,Set/Clear Enable Bit 168" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167 ,Set/Clear Enable Bit 167" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB166 ,Set/Clear Enable Bit 166" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB165 ,Set/Clear Enable Bit 165" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164 ,Set/Clear Enable Bit 164" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB163 ,Set/Clear Enable Bit 163" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB162 ,Set/Clear Enable Bit 162" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161 ,Set/Clear Enable Bit 161" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB160 ,Set/Clear Enable Bit 160" "Disabled,Enabled" else hgroup.long 0x0114++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223 ,Set/Clear Enable Bit 223" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB222 ,Set/Clear Enable Bit 222" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB221 ,Set/Clear Enable Bit 221" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220 ,Set/Clear Enable Bit 220" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB219 ,Set/Clear Enable Bit 219" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB218 ,Set/Clear Enable Bit 218" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217 ,Set/Clear Enable Bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB216 ,Set/Clear Enable Bit 216" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB215 ,Set/Clear Enable Bit 215" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214 ,Set/Clear Enable Bit 214" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB213 ,Set/Clear Enable Bit 213" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB212 ,Set/Clear Enable Bit 212" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211 ,Set/Clear Enable Bit 211" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB210 ,Set/Clear Enable Bit 210" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB209 ,Set/Clear Enable Bit 209" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208 ,Set/Clear Enable Bit 208" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB207 ,Set/Clear Enable Bit 207" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB206 ,Set/Clear Enable Bit 206" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205 ,Set/Clear Enable Bit 205" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB204 ,Set/Clear Enable Bit 204" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB203 ,Set/Clear Enable Bit 203" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202 ,Set/Clear Enable Bit 202" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB201 ,Set/Clear Enable Bit 201" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB200 ,Set/Clear Enable Bit 200" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199 ,Set/Clear Enable Bit 199" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB198 ,Set/Clear Enable Bit 198" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB197 ,Set/Clear Enable Bit 197" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196 ,Set/Clear Enable Bit 196" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB195 ,Set/Clear Enable Bit 195" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB194 ,Set/Clear Enable Bit 194" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193 ,Set/Clear Enable Bit 193" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB192 ,Set/Clear Enable Bit 192" "Disabled,Enabled" else hgroup.long 0x0118++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255 ,Set/Clear Enable Bit 255" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB254 ,Set/Clear Enable Bit 254" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB253 ,Set/Clear Enable Bit 253" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252 ,Set/Clear Enable Bit 252" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB251 ,Set/Clear Enable Bit 251" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB250 ,Set/Clear Enable Bit 250" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249 ,Set/Clear Enable Bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB248 ,Set/Clear Enable Bit 248" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB247 ,Set/Clear Enable Bit 247" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246 ,Set/Clear Enable Bit 246" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB245 ,Set/Clear Enable Bit 245" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB244 ,Set/Clear Enable Bit 244" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243 ,Set/Clear Enable Bit 243" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB242 ,Set/Clear Enable Bit 242" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB241 ,Set/Clear Enable Bit 241" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240 ,Set/Clear Enable Bit 240" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB239 ,Set/Clear Enable Bit 239" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB238 ,Set/Clear Enable Bit 238" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237 ,Set/Clear Enable Bit 237" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB236 ,Set/Clear Enable Bit 236" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB235 ,Set/Clear Enable Bit 235" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234 ,Set/Clear Enable Bit 234" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB233 ,Set/Clear Enable Bit 233" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB232 ,Set/Clear Enable Bit 232" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231 ,Set/Clear Enable Bit 231" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB230 ,Set/Clear Enable Bit 230" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB229 ,Set/Clear Enable Bit 229" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228 ,Set/Clear Enable Bit 228" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB227 ,Set/Clear Enable Bit 227" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB226 ,Set/Clear Enable Bit 226" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225 ,Set/Clear Enable Bit 225" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB224 ,Set/Clear Enable Bit 224" "Disabled,Enabled" else hgroup.long 0x011C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287 ,Set/Clear Enable Bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB286 ,Set/Clear Enable Bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB285 ,Set/Clear Enable Bit 285" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284 ,Set/Clear Enable Bit 284" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB283 ,Set/Clear Enable Bit 283" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB282 ,Set/Clear Enable Bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281 ,Set/Clear Enable Bit 281" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB280 ,Set/Clear Enable Bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB279 ,Set/Clear Enable Bit 279" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278 ,Set/Clear Enable Bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB277 ,Set/Clear Enable Bit 277" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB276 ,Set/Clear Enable Bit 276" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275 ,Set/Clear Enable Bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB274 ,Set/Clear Enable Bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB273 ,Set/Clear Enable Bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272 ,Set/Clear Enable Bit 272" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB271 ,Set/Clear Enable Bit 271" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB270 ,Set/Clear Enable Bit 270" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269 ,Set/Clear Enable Bit 269" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB268 ,Set/Clear Enable Bit 268" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB267 ,Set/Clear Enable Bit 267" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266 ,Set/Clear Enable Bit 266" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB265 ,Set/Clear Enable Bit 265" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB264 ,Set/Clear Enable Bit 264" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263 ,Set/Clear Enable Bit 263" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB262 ,Set/Clear Enable Bit 262" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB261 ,Set/Clear Enable Bit 261" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260 ,Set/Clear Enable Bit 260" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB259 ,Set/Clear Enable Bit 259" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB258 ,Set/Clear Enable Bit 258" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257 ,Set/Clear Enable Bit 257" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB256 ,Set/Clear Enable Bit 256" "Disabled,Enabled" else hgroup.long 0x0120++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319 ,Set/Clear Enable Bit 319" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB318 ,Set/Clear Enable Bit 318" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB317 ,Set/Clear Enable Bit 317" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316 ,Set/Clear Enable Bit 316" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB315 ,Set/Clear Enable Bit 315" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB314 ,Set/Clear Enable Bit 314" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313 ,Set/Clear Enable Bit 313" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB312 ,Set/Clear Enable Bit 312" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB311 ,Set/Clear Enable Bit 311" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310 ,Set/Clear Enable Bit 310" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB309 ,Set/Clear Enable Bit 309" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB308 ,Set/Clear Enable Bit 308" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307 ,Set/Clear Enable Bit 307" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB306 ,Set/Clear Enable Bit 306" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB305 ,Set/Clear Enable Bit 305" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304 ,Set/Clear Enable Bit 304" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB303 ,Set/Clear Enable Bit 303" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB302 ,Set/Clear Enable Bit 302" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301 ,Set/Clear Enable Bit 301" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB300 ,Set/Clear Enable Bit 300" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB299 ,Set/Clear Enable Bit 299" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298 ,Set/Clear Enable Bit 298" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB297 ,Set/Clear Enable Bit 297" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB296 ,Set/Clear Enable Bit 296" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295 ,Set/Clear Enable Bit 295" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB294 ,Set/Clear Enable Bit 294" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB293 ,Set/Clear Enable Bit 293" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292 ,Set/Clear Enable Bit 292" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB291 ,Set/Clear Enable Bit 291" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB290 ,Set/Clear Enable Bit 290" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289 ,Set/Clear Enable Bit 289" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB288 ,Set/Clear Enable Bit 288" "Disabled,Enabled" else hgroup.long 0x0124++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351 ,Set/Clear Enable Bit 351" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB350 ,Set/Clear Enable Bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB349 ,Set/Clear Enable Bit 349" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348 ,Set/Clear Enable Bit 348" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB347 ,Set/Clear Enable Bit 347" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB346 ,Set/Clear Enable Bit 346" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345 ,Set/Clear Enable Bit 345" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB344 ,Set/Clear Enable Bit 344" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB343 ,Set/Clear Enable Bit 343" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342 ,Set/Clear Enable Bit 342" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB341 ,Set/Clear Enable Bit 341" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB340 ,Set/Clear Enable Bit 340" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339 ,Set/Clear Enable Bit 339" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB338 ,Set/Clear Enable Bit 338" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB337 ,Set/Clear Enable Bit 337" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336 ,Set/Clear Enable Bit 336" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB335 ,Set/Clear Enable Bit 335" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB334 ,Set/Clear Enable Bit 334" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333 ,Set/Clear Enable Bit 333" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB332 ,Set/Clear Enable Bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB331 ,Set/Clear Enable Bit 331" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330 ,Set/Clear Enable Bit 330" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB329 ,Set/Clear Enable Bit 329" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB328 ,Set/Clear Enable Bit 328" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327 ,Set/Clear Enable Bit 327" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB326 ,Set/Clear Enable Bit 326" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB325 ,Set/Clear Enable Bit 325" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324 ,Set/Clear Enable Bit 324" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB323 ,Set/Clear Enable Bit 323" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB322 ,Set/Clear Enable Bit 322" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321 ,Set/Clear Enable Bit 321" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB320 ,Set/Clear Enable Bit 320" "Disabled,Enabled" else hgroup.long 0x0128++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383 ,Set/Clear Enable Bit 383" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB382 ,Set/Clear Enable Bit 382" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB381 ,Set/Clear Enable Bit 381" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380 ,Set/Clear Enable Bit 380" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB379 ,Set/Clear Enable Bit 379" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB378 ,Set/Clear Enable Bit 378" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377 ,Set/Clear Enable Bit 377" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB376 ,Set/Clear Enable Bit 376" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB375 ,Set/Clear Enable Bit 375" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374 ,Set/Clear Enable Bit 374" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB373 ,Set/Clear Enable Bit 373" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB372 ,Set/Clear Enable Bit 372" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371 ,Set/Clear Enable Bit 371" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB370 ,Set/Clear Enable Bit 370" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB369 ,Set/Clear Enable Bit 369" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368 ,Set/Clear Enable Bit 368" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB367 ,Set/Clear Enable Bit 367" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB366 ,Set/Clear Enable Bit 366" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365 ,Set/Clear Enable Bit 365" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB364 ,Set/Clear Enable Bit 364" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB363 ,Set/Clear Enable Bit 363" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362 ,Set/Clear Enable Bit 362" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB361 ,Set/Clear Enable Bit 361" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB360 ,Set/Clear Enable Bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359 ,Set/Clear Enable Bit 359" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB358 ,Set/Clear Enable Bit 358" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB357 ,Set/Clear Enable Bit 357" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356 ,Set/Clear Enable Bit 356" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB355 ,Set/Clear Enable Bit 355" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB354 ,Set/Clear Enable Bit 354" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353 ,Set/Clear Enable Bit 353" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB352 ,Set/Clear Enable Bit 352" "Disabled,Enabled" else hgroup.long 0x012C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415 ,Set/Clear Enable Bit 415" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB414 ,Set/Clear Enable Bit 414" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB413 ,Set/Clear Enable Bit 413" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412 ,Set/Clear Enable Bit 412" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB411 ,Set/Clear Enable Bit 411" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB410 ,Set/Clear Enable Bit 410" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409 ,Set/Clear Enable Bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB408 ,Set/Clear Enable Bit 408" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB407 ,Set/Clear Enable Bit 407" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406 ,Set/Clear Enable Bit 406" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB405 ,Set/Clear Enable Bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB404 ,Set/Clear Enable Bit 404" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403 ,Set/Clear Enable Bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB402 ,Set/Clear Enable Bit 402" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB401 ,Set/Clear Enable Bit 401" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400 ,Set/Clear Enable Bit 400" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB399 ,Set/Clear Enable Bit 399" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB398 ,Set/Clear Enable Bit 398" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397 ,Set/Clear Enable Bit 397" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB396 ,Set/Clear Enable Bit 396" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB395 ,Set/Clear Enable Bit 395" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394 ,Set/Clear Enable Bit 394" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB393 ,Set/Clear Enable Bit 393" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB392 ,Set/Clear Enable Bit 392" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391 ,Set/Clear Enable Bit 391" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB390 ,Set/Clear Enable Bit 390" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB389 ,Set/Clear Enable Bit 389" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388 ,Set/Clear Enable Bit 388" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB387 ,Set/Clear Enable Bit 387" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB386 ,Set/Clear Enable Bit 386" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385 ,Set/Clear Enable Bit 385" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB384 ,Set/Clear Enable Bit 384" "Disabled,Enabled" else hgroup.long 0x0130++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447 ,Set/Clear Enable Bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB446 ,Set/Clear Enable Bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB445 ,Set/Clear Enable Bit 445" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444 ,Set/Clear Enable Bit 444" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB443 ,Set/Clear Enable Bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB442 ,Set/Clear Enable Bit 442" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441 ,Set/Clear Enable Bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB440 ,Set/Clear Enable Bit 440" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB439 ,Set/Clear Enable Bit 439" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438 ,Set/Clear Enable Bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB437 ,Set/Clear Enable Bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB436 ,Set/Clear Enable Bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435 ,Set/Clear Enable Bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB434 ,Set/Clear Enable Bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB433 ,Set/Clear Enable Bit 433" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432 ,Set/Clear Enable Bit 432" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB431 ,Set/Clear Enable Bit 431" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB430 ,Set/Clear Enable Bit 430" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429 ,Set/Clear Enable Bit 429" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB428 ,Set/Clear Enable Bit 428" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB427 ,Set/Clear Enable Bit 427" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426 ,Set/Clear Enable Bit 426" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB425 ,Set/Clear Enable Bit 425" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB424 ,Set/Clear Enable Bit 424" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423 ,Set/Clear Enable Bit 423" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB422 ,Set/Clear Enable Bit 422" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB421 ,Set/Clear Enable Bit 421" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420 ,Set/Clear Enable Bit 420" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB419 ,Set/Clear Enable Bit 419" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB418 ,Set/Clear Enable Bit 418" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417 ,Set/Clear Enable Bit 417" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB416 ,Set/Clear Enable Bit 416" "Disabled,Enabled" else hgroup.long 0x0134++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479 ,Set/Clear Enable Bit 479" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB478 ,Set/Clear Enable Bit 478" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB477 ,Set/Clear Enable Bit 477" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476 ,Set/Clear Enable Bit 476" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB475 ,Set/Clear Enable Bit 475" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB474 ,Set/Clear Enable Bit 474" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473 ,Set/Clear Enable Bit 473" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB472 ,Set/Clear Enable Bit 472" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB471 ,Set/Clear Enable Bit 471" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470 ,Set/Clear Enable Bit 470" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB469 ,Set/Clear Enable Bit 469" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB468 ,Set/Clear Enable Bit 468" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467 ,Set/Clear Enable Bit 467" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB466 ,Set/Clear Enable Bit 466" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB465 ,Set/Clear Enable Bit 465" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464 ,Set/Clear Enable Bit 464" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB463 ,Set/Clear Enable Bit 463" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB462 ,Set/Clear Enable Bit 462" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461 ,Set/Clear Enable Bit 461" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB460 ,Set/Clear Enable Bit 460" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB459 ,Set/Clear Enable Bit 459" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458 ,Set/Clear Enable Bit 458" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB457 ,Set/Clear Enable Bit 457" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB456 ,Set/Clear Enable Bit 456" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455 ,Set/Clear Enable Bit 455" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB454 ,Set/Clear Enable Bit 454" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB453 ,Set/Clear Enable Bit 453" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452 ,Set/Clear Enable Bit 452" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB451 ,Set/Clear Enable Bit 451" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB450 ,Set/Clear Enable Bit 450" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449 ,Set/Clear Enable Bit 449" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB448 ,Set/Clear Enable Bit 448" "Disabled,Enabled" else hgroup.long 0x0138++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511 ,Set/Clear Enable Bit 511" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB510 ,Set/Clear Enable Bit 510" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB509 ,Set/Clear Enable Bit 509" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508 ,Set/Clear Enable Bit 508" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB507 ,Set/Clear Enable Bit 507" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB506 ,Set/Clear Enable Bit 506" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505 ,Set/Clear Enable Bit 505" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB504 ,Set/Clear Enable Bit 504" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB503 ,Set/Clear Enable Bit 503" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502 ,Set/Clear Enable Bit 502" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB501 ,Set/Clear Enable Bit 501" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB500 ,Set/Clear Enable Bit 500" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499 ,Set/Clear Enable Bit 499" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB498 ,Set/Clear Enable Bit 498" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB497 ,Set/Clear Enable Bit 497" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496 ,Set/Clear Enable Bit 496" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB495 ,Set/Clear Enable Bit 495" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB494 ,Set/Clear Enable Bit 494" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493 ,Set/Clear Enable Bit 493" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB492 ,Set/Clear Enable Bit 492" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB491 ,Set/Clear Enable Bit 491" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490 ,Set/Clear Enable Bit 490" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB489 ,Set/Clear Enable Bit 489" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB488 ,Set/Clear Enable Bit 488" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487 ,Set/Clear Enable Bit 487" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB486 ,Set/Clear Enable Bit 486" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB485 ,Set/Clear Enable Bit 485" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484 ,Set/Clear Enable Bit 484" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB483 ,Set/Clear Enable Bit 483" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB482 ,Set/Clear Enable Bit 482" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481 ,Set/Clear Enable Bit 481" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB480 ,Set/Clear Enable Bit 480" "Disabled,Enabled" else hgroup.long 0x013C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543 ,Set/Clear Enable Bit 543" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB542 ,Set/Clear Enable Bit 542" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB541 ,Set/Clear Enable Bit 541" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540 ,Set/Clear Enable Bit 540" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB539 ,Set/Clear Enable Bit 539" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB538 ,Set/Clear Enable Bit 538" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537 ,Set/Clear Enable Bit 537" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB536 ,Set/Clear Enable Bit 536" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB535 ,Set/Clear Enable Bit 535" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534 ,Set/Clear Enable Bit 534" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB533 ,Set/Clear Enable Bit 533" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB532 ,Set/Clear Enable Bit 532" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531 ,Set/Clear Enable Bit 531" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB530 ,Set/Clear Enable Bit 530" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB529 ,Set/Clear Enable Bit 529" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528 ,Set/Clear Enable Bit 528" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB527 ,Set/Clear Enable Bit 527" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB526 ,Set/Clear Enable Bit 526" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525 ,Set/Clear Enable Bit 525" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB524 ,Set/Clear Enable Bit 524" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB523 ,Set/Clear Enable Bit 523" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522 ,Set/Clear Enable Bit 522" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB521 ,Set/Clear Enable Bit 521" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB520 ,Set/Clear Enable Bit 520" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519 ,Set/Clear Enable Bit 519" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB518 ,Set/Clear Enable Bit 518" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB517 ,Set/Clear Enable Bit 517" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516 ,Set/Clear Enable Bit 516" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB515 ,Set/Clear Enable Bit 515" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB514 ,Set/Clear Enable Bit 514" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513 ,Set/Clear Enable Bit 513" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB512 ,Set/Clear Enable Bit 512" "Disabled,Enabled" else hgroup.long 0x0140++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575 ,Set/Clear Enable Bit 575" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB574 ,Set/Clear Enable Bit 574" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB573 ,Set/Clear Enable Bit 573" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572 ,Set/Clear Enable Bit 572" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB571 ,Set/Clear Enable Bit 571" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB570 ,Set/Clear Enable Bit 570" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569 ,Set/Clear Enable Bit 569" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB568 ,Set/Clear Enable Bit 568" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB567 ,Set/Clear Enable Bit 567" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566 ,Set/Clear Enable Bit 566" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB565 ,Set/Clear Enable Bit 565" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB564 ,Set/Clear Enable Bit 564" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563 ,Set/Clear Enable Bit 563" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB562 ,Set/Clear Enable Bit 562" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB561 ,Set/Clear Enable Bit 561" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560 ,Set/Clear Enable Bit 560" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB559 ,Set/Clear Enable Bit 559" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB558 ,Set/Clear Enable Bit 558" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557 ,Set/Clear Enable Bit 557" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB556 ,Set/Clear Enable Bit 556" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB555 ,Set/Clear Enable Bit 555" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554 ,Set/Clear Enable Bit 554" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB553 ,Set/Clear Enable Bit 553" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB552 ,Set/Clear Enable Bit 552" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551 ,Set/Clear Enable Bit 551" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB550 ,Set/Clear Enable Bit 550" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB549 ,Set/Clear Enable Bit 549" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548 ,Set/Clear Enable Bit 548" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB547 ,Set/Clear Enable Bit 547" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB546 ,Set/Clear Enable Bit 546" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545 ,Set/Clear Enable Bit 545" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB544 ,Set/Clear Enable Bit 544" "Disabled,Enabled" else hgroup.long 0x0144++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607 ,Set/Clear Enable Bit 607" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB606 ,Set/Clear Enable Bit 606" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB605 ,Set/Clear Enable Bit 605" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604 ,Set/Clear Enable Bit 604" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB603 ,Set/Clear Enable Bit 603" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB602 ,Set/Clear Enable Bit 602" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601 ,Set/Clear Enable Bit 601" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB600 ,Set/Clear Enable Bit 600" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB599 ,Set/Clear Enable Bit 599" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598 ,Set/Clear Enable Bit 598" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB597 ,Set/Clear Enable Bit 597" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB596 ,Set/Clear Enable Bit 596" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595 ,Set/Clear Enable Bit 595" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB594 ,Set/Clear Enable Bit 594" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB593 ,Set/Clear Enable Bit 593" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592 ,Set/Clear Enable Bit 592" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB591 ,Set/Clear Enable Bit 591" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB590 ,Set/Clear Enable Bit 590" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589 ,Set/Clear Enable Bit 589" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB588 ,Set/Clear Enable Bit 588" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB587 ,Set/Clear Enable Bit 587" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586 ,Set/Clear Enable Bit 586" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB585 ,Set/Clear Enable Bit 585" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB584 ,Set/Clear Enable Bit 584" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583 ,Set/Clear Enable Bit 583" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB582 ,Set/Clear Enable Bit 582" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB581 ,Set/Clear Enable Bit 581" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580 ,Set/Clear Enable Bit 580" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB579 ,Set/Clear Enable Bit 579" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB578 ,Set/Clear Enable Bit 578" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577 ,Set/Clear Enable Bit 577" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB576 ,Set/Clear Enable Bit 576" "Disabled,Enabled" else hgroup.long 0x0148++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639 ,Set/Clear Enable Bit 639" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB638 ,Set/Clear Enable Bit 638" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB637 ,Set/Clear Enable Bit 637" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636 ,Set/Clear Enable Bit 636" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB635 ,Set/Clear Enable Bit 635" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB634 ,Set/Clear Enable Bit 634" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633 ,Set/Clear Enable Bit 633" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB632 ,Set/Clear Enable Bit 632" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB631 ,Set/Clear Enable Bit 631" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630 ,Set/Clear Enable Bit 630" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB629 ,Set/Clear Enable Bit 629" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB628 ,Set/Clear Enable Bit 628" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627 ,Set/Clear Enable Bit 627" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB626 ,Set/Clear Enable Bit 626" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB625 ,Set/Clear Enable Bit 625" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624 ,Set/Clear Enable Bit 624" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB623 ,Set/Clear Enable Bit 623" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB622 ,Set/Clear Enable Bit 622" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621 ,Set/Clear Enable Bit 621" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB620 ,Set/Clear Enable Bit 620" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB619 ,Set/Clear Enable Bit 619" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618 ,Set/Clear Enable Bit 618" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB617 ,Set/Clear Enable Bit 617" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB616 ,Set/Clear Enable Bit 616" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615 ,Set/Clear Enable Bit 615" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB614 ,Set/Clear Enable Bit 614" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB613 ,Set/Clear Enable Bit 613" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612 ,Set/Clear Enable Bit 612" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB611 ,Set/Clear Enable Bit 611" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB610 ,Set/Clear Enable Bit 610" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609 ,Set/Clear Enable Bit 609" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB608 ,Set/Clear Enable Bit 608" "Disabled,Enabled" else hgroup.long 0x014C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671 ,Set/Clear Enable Bit 671" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB670 ,Set/Clear Enable Bit 670" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB669 ,Set/Clear Enable Bit 669" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668 ,Set/Clear Enable Bit 668" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB667 ,Set/Clear Enable Bit 667" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB666 ,Set/Clear Enable Bit 666" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665 ,Set/Clear Enable Bit 665" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB664 ,Set/Clear Enable Bit 664" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB663 ,Set/Clear Enable Bit 663" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662 ,Set/Clear Enable Bit 662" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB661 ,Set/Clear Enable Bit 661" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB660 ,Set/Clear Enable Bit 660" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659 ,Set/Clear Enable Bit 659" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB658 ,Set/Clear Enable Bit 658" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB657 ,Set/Clear Enable Bit 657" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656 ,Set/Clear Enable Bit 656" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB655 ,Set/Clear Enable Bit 655" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB654 ,Set/Clear Enable Bit 654" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653 ,Set/Clear Enable Bit 653" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB652 ,Set/Clear Enable Bit 652" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB651 ,Set/Clear Enable Bit 651" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650 ,Set/Clear Enable Bit 650" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB649 ,Set/Clear Enable Bit 649" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB648 ,Set/Clear Enable Bit 648" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647 ,Set/Clear Enable Bit 647" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB646 ,Set/Clear Enable Bit 646" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB645 ,Set/Clear Enable Bit 645" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644 ,Set/Clear Enable Bit 644" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB643 ,Set/Clear Enable Bit 643" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB642 ,Set/Clear Enable Bit 642" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641 ,Set/Clear Enable Bit 641" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB640 ,Set/Clear Enable Bit 640" "Disabled,Enabled" else hgroup.long 0x0150++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703 ,Set/Clear Enable Bit 703" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB702 ,Set/Clear Enable Bit 702" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB701 ,Set/Clear Enable Bit 701" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700 ,Set/Clear Enable Bit 700" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB699 ,Set/Clear Enable Bit 699" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB698 ,Set/Clear Enable Bit 698" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697 ,Set/Clear Enable Bit 697" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB696 ,Set/Clear Enable Bit 696" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB695 ,Set/Clear Enable Bit 695" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694 ,Set/Clear Enable Bit 694" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB693 ,Set/Clear Enable Bit 693" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB692 ,Set/Clear Enable Bit 692" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691 ,Set/Clear Enable Bit 691" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB690 ,Set/Clear Enable Bit 690" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB689 ,Set/Clear Enable Bit 689" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688 ,Set/Clear Enable Bit 688" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB687 ,Set/Clear Enable Bit 687" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB686 ,Set/Clear Enable Bit 686" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685 ,Set/Clear Enable Bit 685" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB684 ,Set/Clear Enable Bit 684" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB683 ,Set/Clear Enable Bit 683" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682 ,Set/Clear Enable Bit 682" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB681 ,Set/Clear Enable Bit 681" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB680 ,Set/Clear Enable Bit 680" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679 ,Set/Clear Enable Bit 679" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB678 ,Set/Clear Enable Bit 678" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB677 ,Set/Clear Enable Bit 677" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676 ,Set/Clear Enable Bit 676" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB675 ,Set/Clear Enable Bit 675" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB674 ,Set/Clear Enable Bit 674" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673 ,Set/Clear Enable Bit 673" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB672 ,Set/Clear Enable Bit 672" "Disabled,Enabled" else hgroup.long 0x0154++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735 ,Set/Clear Enable Bit 735" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB734 ,Set/Clear Enable Bit 734" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB733 ,Set/Clear Enable Bit 733" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732 ,Set/Clear Enable Bit 732" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB731 ,Set/Clear Enable Bit 731" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB730 ,Set/Clear Enable Bit 730" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729 ,Set/Clear Enable Bit 729" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB728 ,Set/Clear Enable Bit 728" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB727 ,Set/Clear Enable Bit 727" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726 ,Set/Clear Enable Bit 726" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB725 ,Set/Clear Enable Bit 725" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB724 ,Set/Clear Enable Bit 724" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723 ,Set/Clear Enable Bit 723" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB722 ,Set/Clear Enable Bit 722" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB721 ,Set/Clear Enable Bit 721" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720 ,Set/Clear Enable Bit 720" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB719 ,Set/Clear Enable Bit 719" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB718 ,Set/Clear Enable Bit 718" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717 ,Set/Clear Enable Bit 717" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB716 ,Set/Clear Enable Bit 716" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB715 ,Set/Clear Enable Bit 715" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714 ,Set/Clear Enable Bit 714" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB713 ,Set/Clear Enable Bit 713" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB712 ,Set/Clear Enable Bit 712" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711 ,Set/Clear Enable Bit 711" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB710 ,Set/Clear Enable Bit 710" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB709 ,Set/Clear Enable Bit 709" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708 ,Set/Clear Enable Bit 708" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB707 ,Set/Clear Enable Bit 707" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB706 ,Set/Clear Enable Bit 706" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705 ,Set/Clear Enable Bit 705" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB704 ,Set/Clear Enable Bit 704" "Disabled,Enabled" else hgroup.long 0x0158++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767 ,Set/Clear Enable Bit 767" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB766 ,Set/Clear Enable Bit 766" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB765 ,Set/Clear Enable Bit 765" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764 ,Set/Clear Enable Bit 764" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB763 ,Set/Clear Enable Bit 763" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB762 ,Set/Clear Enable Bit 762" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761 ,Set/Clear Enable Bit 761" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB760 ,Set/Clear Enable Bit 760" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB759 ,Set/Clear Enable Bit 759" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758 ,Set/Clear Enable Bit 758" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB757 ,Set/Clear Enable Bit 757" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB756 ,Set/Clear Enable Bit 756" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755 ,Set/Clear Enable Bit 755" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB754 ,Set/Clear Enable Bit 754" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB753 ,Set/Clear Enable Bit 753" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752 ,Set/Clear Enable Bit 752" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB751 ,Set/Clear Enable Bit 751" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB750 ,Set/Clear Enable Bit 750" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749 ,Set/Clear Enable Bit 749" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB748 ,Set/Clear Enable Bit 748" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB747 ,Set/Clear Enable Bit 747" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746 ,Set/Clear Enable Bit 746" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB745 ,Set/Clear Enable Bit 745" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB744 ,Set/Clear Enable Bit 744" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743 ,Set/Clear Enable Bit 743" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB742 ,Set/Clear Enable Bit 742" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB741 ,Set/Clear Enable Bit 741" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740 ,Set/Clear Enable Bit 740" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB739 ,Set/Clear Enable Bit 739" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB738 ,Set/Clear Enable Bit 738" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737 ,Set/Clear Enable Bit 737" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB736 ,Set/Clear Enable Bit 736" "Disabled,Enabled" else hgroup.long 0x015C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799 ,Set/Clear Enable Bit 799" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB798 ,Set/Clear Enable Bit 798" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB797 ,Set/Clear Enable Bit 797" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796 ,Set/Clear Enable Bit 796" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB795 ,Set/Clear Enable Bit 795" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB794 ,Set/Clear Enable Bit 794" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793 ,Set/Clear Enable Bit 793" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB792 ,Set/Clear Enable Bit 792" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB791 ,Set/Clear Enable Bit 791" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790 ,Set/Clear Enable Bit 790" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB789 ,Set/Clear Enable Bit 789" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB788 ,Set/Clear Enable Bit 788" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787 ,Set/Clear Enable Bit 787" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB786 ,Set/Clear Enable Bit 786" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB785 ,Set/Clear Enable Bit 785" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784 ,Set/Clear Enable Bit 784" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB783 ,Set/Clear Enable Bit 783" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB782 ,Set/Clear Enable Bit 782" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781 ,Set/Clear Enable Bit 781" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB780 ,Set/Clear Enable Bit 780" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB779 ,Set/Clear Enable Bit 779" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778 ,Set/Clear Enable Bit 778" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB777 ,Set/Clear Enable Bit 777" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB776 ,Set/Clear Enable Bit 776" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775 ,Set/Clear Enable Bit 775" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB774 ,Set/Clear Enable Bit 774" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB773 ,Set/Clear Enable Bit 773" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772 ,Set/Clear Enable Bit 772" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB771 ,Set/Clear Enable Bit 771" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB770 ,Set/Clear Enable Bit 770" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769 ,Set/Clear Enable Bit 769" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB768 ,Set/Clear Enable Bit 768" "Disabled,Enabled" else hgroup.long 0x0160++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831 ,Set/Clear Enable Bit 831" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB830 ,Set/Clear Enable Bit 830" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB829 ,Set/Clear Enable Bit 829" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828 ,Set/Clear Enable Bit 828" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB827 ,Set/Clear Enable Bit 827" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB826 ,Set/Clear Enable Bit 826" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825 ,Set/Clear Enable Bit 825" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB824 ,Set/Clear Enable Bit 824" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB823 ,Set/Clear Enable Bit 823" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822 ,Set/Clear Enable Bit 822" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB821 ,Set/Clear Enable Bit 821" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB820 ,Set/Clear Enable Bit 820" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819 ,Set/Clear Enable Bit 819" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB818 ,Set/Clear Enable Bit 818" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB817 ,Set/Clear Enable Bit 817" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816 ,Set/Clear Enable Bit 816" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB815 ,Set/Clear Enable Bit 815" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB814 ,Set/Clear Enable Bit 814" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813 ,Set/Clear Enable Bit 813" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB812 ,Set/Clear Enable Bit 812" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB811 ,Set/Clear Enable Bit 811" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810 ,Set/Clear Enable Bit 810" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB809 ,Set/Clear Enable Bit 809" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB808 ,Set/Clear Enable Bit 808" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807 ,Set/Clear Enable Bit 807" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB806 ,Set/Clear Enable Bit 806" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB805 ,Set/Clear Enable Bit 805" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804 ,Set/Clear Enable Bit 804" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB803 ,Set/Clear Enable Bit 803" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB802 ,Set/Clear Enable Bit 802" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801 ,Set/Clear Enable Bit 801" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB800 ,Set/Clear Enable Bit 800" "Disabled,Enabled" else hgroup.long 0x0164++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863 ,Set/Clear Enable Bit 863" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB862 ,Set/Clear Enable Bit 862" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB861 ,Set/Clear Enable Bit 861" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860 ,Set/Clear Enable Bit 860" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB859 ,Set/Clear Enable Bit 859" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB858 ,Set/Clear Enable Bit 858" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857 ,Set/Clear Enable Bit 857" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB856 ,Set/Clear Enable Bit 856" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB855 ,Set/Clear Enable Bit 855" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854 ,Set/Clear Enable Bit 854" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB853 ,Set/Clear Enable Bit 853" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB852 ,Set/Clear Enable Bit 852" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851 ,Set/Clear Enable Bit 851" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB850 ,Set/Clear Enable Bit 850" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB849 ,Set/Clear Enable Bit 849" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848 ,Set/Clear Enable Bit 848" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB847 ,Set/Clear Enable Bit 847" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB846 ,Set/Clear Enable Bit 846" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845 ,Set/Clear Enable Bit 845" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB844 ,Set/Clear Enable Bit 844" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB843 ,Set/Clear Enable Bit 843" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842 ,Set/Clear Enable Bit 842" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB841 ,Set/Clear Enable Bit 841" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB840 ,Set/Clear Enable Bit 840" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839 ,Set/Clear Enable Bit 839" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB838 ,Set/Clear Enable Bit 838" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB837 ,Set/Clear Enable Bit 837" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836 ,Set/Clear Enable Bit 836" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB835 ,Set/Clear Enable Bit 835" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB834 ,Set/Clear Enable Bit 834" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833 ,Set/Clear Enable Bit 833" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB832 ,Set/Clear Enable Bit 832" "Disabled,Enabled" else hgroup.long 0x0168++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895 ,Set/Clear Enable Bit 895" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB894 ,Set/Clear Enable Bit 894" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB893 ,Set/Clear Enable Bit 893" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892 ,Set/Clear Enable Bit 892" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB891 ,Set/Clear Enable Bit 891" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB890 ,Set/Clear Enable Bit 890" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889 ,Set/Clear Enable Bit 889" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB888 ,Set/Clear Enable Bit 888" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB887 ,Set/Clear Enable Bit 887" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886 ,Set/Clear Enable Bit 886" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB885 ,Set/Clear Enable Bit 885" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB884 ,Set/Clear Enable Bit 884" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883 ,Set/Clear Enable Bit 883" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB882 ,Set/Clear Enable Bit 882" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB881 ,Set/Clear Enable Bit 881" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880 ,Set/Clear Enable Bit 880" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB879 ,Set/Clear Enable Bit 879" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB878 ,Set/Clear Enable Bit 878" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877 ,Set/Clear Enable Bit 877" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB876 ,Set/Clear Enable Bit 876" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB875 ,Set/Clear Enable Bit 875" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874 ,Set/Clear Enable Bit 874" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB873 ,Set/Clear Enable Bit 873" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB872 ,Set/Clear Enable Bit 872" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871 ,Set/Clear Enable Bit 871" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB870 ,Set/Clear Enable Bit 870" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB869 ,Set/Clear Enable Bit 869" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868 ,Set/Clear Enable Bit 868" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB867 ,Set/Clear Enable Bit 867" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB866 ,Set/Clear Enable Bit 866" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865 ,Set/Clear Enable Bit 865" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB864 ,Set/Clear Enable Bit 864" "Disabled,Enabled" else hgroup.long 0x016C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927 ,Set/Clear Enable Bit 927" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB926 ,Set/Clear Enable Bit 926" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB925 ,Set/Clear Enable Bit 925" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924 ,Set/Clear Enable Bit 924" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB923 ,Set/Clear Enable Bit 923" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB922 ,Set/Clear Enable Bit 922" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921 ,Set/Clear Enable Bit 921" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB920 ,Set/Clear Enable Bit 920" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB919 ,Set/Clear Enable Bit 919" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918 ,Set/Clear Enable Bit 918" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB917 ,Set/Clear Enable Bit 917" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB916 ,Set/Clear Enable Bit 916" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915 ,Set/Clear Enable Bit 915" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB914 ,Set/Clear Enable Bit 914" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB913 ,Set/Clear Enable Bit 913" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912 ,Set/Clear Enable Bit 912" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB911 ,Set/Clear Enable Bit 911" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB910 ,Set/Clear Enable Bit 910" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909 ,Set/Clear Enable Bit 909" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB908 ,Set/Clear Enable Bit 908" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB907 ,Set/Clear Enable Bit 907" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906 ,Set/Clear Enable Bit 906" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB905 ,Set/Clear Enable Bit 905" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB904 ,Set/Clear Enable Bit 904" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903 ,Set/Clear Enable Bit 903" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB902 ,Set/Clear Enable Bit 902" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB901 ,Set/Clear Enable Bit 901" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900 ,Set/Clear Enable Bit 900" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB899 ,Set/Clear Enable Bit 899" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB898 ,Set/Clear Enable Bit 898" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897 ,Set/Clear Enable Bit 897" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB896 ,Set/Clear Enable Bit 896" "Disabled,Enabled" else hgroup.long 0x0170++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959 ,Set/Clear Enable Bit 959" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB958 ,Set/Clear Enable Bit 958" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB957 ,Set/Clear Enable Bit 957" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956 ,Set/Clear Enable Bit 956" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB955 ,Set/Clear Enable Bit 955" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB954 ,Set/Clear Enable Bit 954" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953 ,Set/Clear Enable Bit 953" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB952 ,Set/Clear Enable Bit 952" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB951 ,Set/Clear Enable Bit 951" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950 ,Set/Clear Enable Bit 950" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB949 ,Set/Clear Enable Bit 949" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB948 ,Set/Clear Enable Bit 948" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947 ,Set/Clear Enable Bit 947" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB946 ,Set/Clear Enable Bit 946" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB945 ,Set/Clear Enable Bit 945" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944 ,Set/Clear Enable Bit 944" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB943 ,Set/Clear Enable Bit 943" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB942 ,Set/Clear Enable Bit 942" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941 ,Set/Clear Enable Bit 941" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB940 ,Set/Clear Enable Bit 940" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB939 ,Set/Clear Enable Bit 939" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938 ,Set/Clear Enable Bit 938" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB937 ,Set/Clear Enable Bit 937" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB936 ,Set/Clear Enable Bit 936" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935 ,Set/Clear Enable Bit 935" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB934 ,Set/Clear Enable Bit 934" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB933 ,Set/Clear Enable Bit 933" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932 ,Set/Clear Enable Bit 932" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB931 ,Set/Clear Enable Bit 931" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB930 ,Set/Clear Enable Bit 930" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929 ,Set/Clear Enable Bit 929" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB928 ,Set/Clear Enable Bit 928" "Disabled,Enabled" else hgroup.long 0x0174++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991 ,Set/Clear Enable Bit 991" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB990 ,Set/Clear Enable Bit 990" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB989 ,Set/Clear Enable Bit 989" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988 ,Set/Clear Enable Bit 988" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB987 ,Set/Clear Enable Bit 987" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB986 ,Set/Clear Enable Bit 986" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985 ,Set/Clear Enable Bit 985" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB984 ,Set/Clear Enable Bit 984" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB983 ,Set/Clear Enable Bit 983" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982 ,Set/Clear Enable Bit 982" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB981 ,Set/Clear Enable Bit 981" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB980 ,Set/Clear Enable Bit 980" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979 ,Set/Clear Enable Bit 979" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB978 ,Set/Clear Enable Bit 978" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB977 ,Set/Clear Enable Bit 977" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976 ,Set/Clear Enable Bit 976" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB975 ,Set/Clear Enable Bit 975" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB974 ,Set/Clear Enable Bit 974" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973 ,Set/Clear Enable Bit 973" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB972 ,Set/Clear Enable Bit 972" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB971 ,Set/Clear Enable Bit 971" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970 ,Set/Clear Enable Bit 970" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB969 ,Set/Clear Enable Bit 969" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB968 ,Set/Clear Enable Bit 968" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967 ,Set/Clear Enable Bit 967" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB966 ,Set/Clear Enable Bit 966" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB965 ,Set/Clear Enable Bit 965" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964 ,Set/Clear Enable Bit 964" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB963 ,Set/Clear Enable Bit 963" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB962 ,Set/Clear Enable Bit 962" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961 ,Set/Clear Enable Bit 961" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB960 ,Set/Clear Enable Bit 960" "Disabled,Enabled" else hgroup.long 0x0178++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" endif tree.end width 22. tree "Set/Clear Pending Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0200++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" newline newline newline newline newline newline newline newline newline newline else group.long 0x0200++0x03 line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Not pending,Pending" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63 ,Set/Clear Pending Bit 63" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND62 ,Set/Clear Pending Bit 62" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND61 ,Set/Clear Pending Bit 61" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60 ,Set/Clear Pending Bit 60" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND59 ,Set/Clear Pending Bit 59" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND58 ,Set/Clear Pending Bit 58" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57 ,Set/Clear Pending Bit 57" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND56 ,Set/Clear Pending Bit 56" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND55 ,Set/Clear Pending Bit 55" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54 ,Set/Clear Pending Bit 54" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND53 ,Set/Clear Pending Bit 53" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND52 ,Set/Clear Pending Bit 52" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51 ,Set/Clear Pending Bit 51" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND50 ,Set/Clear Pending Bit 50" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND49 ,Set/Clear Pending Bit 49" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48 ,Set/Clear Pending Bit 48" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND47 ,Set/Clear Pending Bit 47" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND46 ,Set/Clear Pending Bit 46" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45 ,Set/Clear Pending Bit 45" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND44 ,Set/Clear Pending Bit 44" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND43 ,Set/Clear Pending Bit 43" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42 ,Set/Clear Pending Bit 42" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND41 ,Set/Clear Pending Bit 41" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND40 ,Set/Clear Pending Bit 40" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39 ,Set/Clear Pending Bit 39" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND38 ,Set/Clear Pending Bit 38" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND37 ,Set/Clear Pending Bit 37" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36 ,Set/Clear Pending Bit 36" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND35 ,Set/Clear Pending Bit 35" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND34 ,Set/Clear Pending Bit 34" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33 ,Set/Clear Pending Bit 33" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND32 ,Set/Clear Pending Bit 32" "Not pending,Pending" else hgroup.long 0x0204++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95 ,Set/Clear Pending Bit 95" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND94 ,Set/Clear Pending Bit 94" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND93 ,Set/Clear Pending Bit 93" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92 ,Set/Clear Pending Bit 92" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND91 ,Set/Clear Pending Bit 91" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND90 ,Set/Clear Pending Bit 90" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89 ,Set/Clear Pending Bit 89" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND88 ,Set/Clear Pending Bit 88" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND87 ,Set/Clear Pending Bit 87" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86 ,Set/Clear Pending Bit 86" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND85 ,Set/Clear Pending Bit 85" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND84 ,Set/Clear Pending Bit 84" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83 ,Set/Clear Pending Bit 83" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND82 ,Set/Clear Pending Bit 82" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND81 ,Set/Clear Pending Bit 81" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80 ,Set/Clear Pending Bit 80" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND79 ,Set/Clear Pending Bit 79" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND78 ,Set/Clear Pending Bit 78" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77 ,Set/Clear Pending Bit 77" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND76 ,Set/Clear Pending Bit 76" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND75 ,Set/Clear Pending Bit 75" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74 ,Set/Clear Pending Bit 74" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND73 ,Set/Clear Pending Bit 73" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND72 ,Set/Clear Pending Bit 72" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71 ,Set/Clear Pending Bit 71" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND70 ,Set/Clear Pending Bit 70" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND69 ,Set/Clear Pending Bit 69" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68 ,Set/Clear Pending Bit 68" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND67 ,Set/Clear Pending Bit 67" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND66 ,Set/Clear Pending Bit 66" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65 ,Set/Clear Pending Bit 65" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND64 ,Set/Clear Pending Bit 64" "Not pending,Pending" else hgroup.long 0x0208++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127 ,Set/Clear Pending Bit 127" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND126 ,Set/Clear Pending Bit 126" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND125 ,Set/Clear Pending Bit 125" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124 ,Set/Clear Pending Bit 124" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND123 ,Set/Clear Pending Bit 123" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND122 ,Set/Clear Pending Bit 122" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121 ,Set/Clear Pending Bit 121" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND120 ,Set/Clear Pending Bit 120" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND119 ,Set/Clear Pending Bit 119" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118 ,Set/Clear Pending Bit 118" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND117 ,Set/Clear Pending Bit 117" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND116 ,Set/Clear Pending Bit 116" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115 ,Set/Clear Pending Bit 115" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND114 ,Set/Clear Pending Bit 114" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND113 ,Set/Clear Pending Bit 113" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112 ,Set/Clear Pending Bit 112" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND111 ,Set/Clear Pending Bit 111" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND110 ,Set/Clear Pending Bit 110" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109 ,Set/Clear Pending Bit 109" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND108 ,Set/Clear Pending Bit 108" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND107 ,Set/Clear Pending Bit 107" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106 ,Set/Clear Pending Bit 106" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND105 ,Set/Clear Pending Bit 105" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND104 ,Set/Clear Pending Bit 104" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103 ,Set/Clear Pending Bit 103" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND102 ,Set/Clear Pending Bit 102" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND101 ,Set/Clear Pending Bit 101" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100 ,Set/Clear Pending Bit 100" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND99 ,Set/Clear Pending Bit 99" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND98 ,Set/Clear Pending Bit 98" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97 ,Set/Clear Pending Bit 97" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND96 ,Set/Clear Pending Bit 96" "Not pending,Pending" else hgroup.long 0x020C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159 ,Set/Clear Pending Bit 159" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND158 ,Set/Clear Pending Bit 158" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND157 ,Set/Clear Pending Bit 157" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156 ,Set/Clear Pending Bit 156" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND155 ,Set/Clear Pending Bit 155" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND154 ,Set/Clear Pending Bit 154" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153 ,Set/Clear Pending Bit 153" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND152 ,Set/Clear Pending Bit 152" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND151 ,Set/Clear Pending Bit 151" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150 ,Set/Clear Pending Bit 150" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND149 ,Set/Clear Pending Bit 149" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND148 ,Set/Clear Pending Bit 148" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147 ,Set/Clear Pending Bit 147" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND146 ,Set/Clear Pending Bit 146" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND145 ,Set/Clear Pending Bit 145" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144 ,Set/Clear Pending Bit 144" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND143 ,Set/Clear Pending Bit 143" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND142 ,Set/Clear Pending Bit 142" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141 ,Set/Clear Pending Bit 141" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND140 ,Set/Clear Pending Bit 140" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND139 ,Set/Clear Pending Bit 139" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138 ,Set/Clear Pending Bit 138" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND137 ,Set/Clear Pending Bit 137" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND136 ,Set/Clear Pending Bit 136" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135 ,Set/Clear Pending Bit 135" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND134 ,Set/Clear Pending Bit 134" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND133 ,Set/Clear Pending Bit 133" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132 ,Set/Clear Pending Bit 132" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND131 ,Set/Clear Pending Bit 131" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND130 ,Set/Clear Pending Bit 130" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129 ,Set/Clear Pending Bit 129" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND128 ,Set/Clear Pending Bit 128" "Not pending,Pending" else hgroup.long 0x0210++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191 ,Set/Clear Pending Bit 191" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND190 ,Set/Clear Pending Bit 190" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND189 ,Set/Clear Pending Bit 189" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188 ,Set/Clear Pending Bit 188" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND187 ,Set/Clear Pending Bit 187" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND186 ,Set/Clear Pending Bit 186" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185 ,Set/Clear Pending Bit 185" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND184 ,Set/Clear Pending Bit 184" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND183 ,Set/Clear Pending Bit 183" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182 ,Set/Clear Pending Bit 182" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND181 ,Set/Clear Pending Bit 181" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND180 ,Set/Clear Pending Bit 180" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179 ,Set/Clear Pending Bit 179" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND178 ,Set/Clear Pending Bit 178" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND177 ,Set/Clear Pending Bit 177" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176 ,Set/Clear Pending Bit 176" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND175 ,Set/Clear Pending Bit 175" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND174 ,Set/Clear Pending Bit 174" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173 ,Set/Clear Pending Bit 173" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND172 ,Set/Clear Pending Bit 172" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND171 ,Set/Clear Pending Bit 171" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170 ,Set/Clear Pending Bit 170" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND169 ,Set/Clear Pending Bit 169" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND168 ,Set/Clear Pending Bit 168" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167 ,Set/Clear Pending Bit 167" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND166 ,Set/Clear Pending Bit 166" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND165 ,Set/Clear Pending Bit 165" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164 ,Set/Clear Pending Bit 164" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND163 ,Set/Clear Pending Bit 163" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND162 ,Set/Clear Pending Bit 162" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161 ,Set/Clear Pending Bit 161" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND160 ,Set/Clear Pending Bit 160" "Not pending,Pending" else hgroup.long 0x0214++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223 ,Set/Clear Pending Bit 223" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND222 ,Set/Clear Pending Bit 222" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND221 ,Set/Clear Pending Bit 221" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220 ,Set/Clear Pending Bit 220" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND219 ,Set/Clear Pending Bit 219" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND218 ,Set/Clear Pending Bit 218" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217 ,Set/Clear Pending Bit 217" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND216 ,Set/Clear Pending Bit 216" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND215 ,Set/Clear Pending Bit 215" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214 ,Set/Clear Pending Bit 214" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND213 ,Set/Clear Pending Bit 213" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND212 ,Set/Clear Pending Bit 212" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211 ,Set/Clear Pending Bit 211" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND210 ,Set/Clear Pending Bit 210" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND209 ,Set/Clear Pending Bit 209" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208 ,Set/Clear Pending Bit 208" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND207 ,Set/Clear Pending Bit 207" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND206 ,Set/Clear Pending Bit 206" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205 ,Set/Clear Pending Bit 205" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND204 ,Set/Clear Pending Bit 204" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND203 ,Set/Clear Pending Bit 203" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202 ,Set/Clear Pending Bit 202" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND201 ,Set/Clear Pending Bit 201" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND200 ,Set/Clear Pending Bit 200" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199 ,Set/Clear Pending Bit 199" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND198 ,Set/Clear Pending Bit 198" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND197 ,Set/Clear Pending Bit 197" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196 ,Set/Clear Pending Bit 196" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND195 ,Set/Clear Pending Bit 195" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND194 ,Set/Clear Pending Bit 194" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193 ,Set/Clear Pending Bit 193" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND192 ,Set/Clear Pending Bit 192" "Not pending,Pending" else hgroup.long 0x0218++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255 ,Set/Clear Pending Bit 255" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND254 ,Set/Clear Pending Bit 254" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND253 ,Set/Clear Pending Bit 253" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252 ,Set/Clear Pending Bit 252" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND251 ,Set/Clear Pending Bit 251" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND250 ,Set/Clear Pending Bit 250" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249 ,Set/Clear Pending Bit 249" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND248 ,Set/Clear Pending Bit 248" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND247 ,Set/Clear Pending Bit 247" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246 ,Set/Clear Pending Bit 246" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND245 ,Set/Clear Pending Bit 245" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND244 ,Set/Clear Pending Bit 244" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243 ,Set/Clear Pending Bit 243" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND242 ,Set/Clear Pending Bit 242" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND241 ,Set/Clear Pending Bit 241" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240 ,Set/Clear Pending Bit 240" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND239 ,Set/Clear Pending Bit 239" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND238 ,Set/Clear Pending Bit 238" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237 ,Set/Clear Pending Bit 237" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND236 ,Set/Clear Pending Bit 236" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND235 ,Set/Clear Pending Bit 235" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234 ,Set/Clear Pending Bit 234" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND233 ,Set/Clear Pending Bit 233" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND232 ,Set/Clear Pending Bit 232" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231 ,Set/Clear Pending Bit 231" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND230 ,Set/Clear Pending Bit 230" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND229 ,Set/Clear Pending Bit 229" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228 ,Set/Clear Pending Bit 228" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND227 ,Set/Clear Pending Bit 227" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND226 ,Set/Clear Pending Bit 226" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225 ,Set/Clear Pending Bit 225" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND224 ,Set/Clear Pending Bit 224" "Not pending,Pending" else hgroup.long 0x021C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287 ,Set/Clear Pending Bit 287" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND286 ,Set/Clear Pending Bit 286" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND285 ,Set/Clear Pending Bit 285" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284 ,Set/Clear Pending Bit 284" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND283 ,Set/Clear Pending Bit 283" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND282 ,Set/Clear Pending Bit 282" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281 ,Set/Clear Pending Bit 281" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND280 ,Set/Clear Pending Bit 280" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND279 ,Set/Clear Pending Bit 279" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278 ,Set/Clear Pending Bit 278" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND277 ,Set/Clear Pending Bit 277" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND276 ,Set/Clear Pending Bit 276" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275 ,Set/Clear Pending Bit 275" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND274 ,Set/Clear Pending Bit 274" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND273 ,Set/Clear Pending Bit 273" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272 ,Set/Clear Pending Bit 272" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND271 ,Set/Clear Pending Bit 271" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND270 ,Set/Clear Pending Bit 270" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269 ,Set/Clear Pending Bit 269" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND268 ,Set/Clear Pending Bit 268" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND267 ,Set/Clear Pending Bit 267" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266 ,Set/Clear Pending Bit 266" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND265 ,Set/Clear Pending Bit 265" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND264 ,Set/Clear Pending Bit 264" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263 ,Set/Clear Pending Bit 263" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND262 ,Set/Clear Pending Bit 262" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND261 ,Set/Clear Pending Bit 261" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260 ,Set/Clear Pending Bit 260" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND259 ,Set/Clear Pending Bit 259" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND258 ,Set/Clear Pending Bit 258" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257 ,Set/Clear Pending Bit 257" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND256 ,Set/Clear Pending Bit 256" "Not pending,Pending" else hgroup.long 0x0220++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319 ,Set/Clear Pending Bit 319" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND318 ,Set/Clear Pending Bit 318" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND317 ,Set/Clear Pending Bit 317" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316 ,Set/Clear Pending Bit 316" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND315 ,Set/Clear Pending Bit 315" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND314 ,Set/Clear Pending Bit 314" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313 ,Set/Clear Pending Bit 313" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND312 ,Set/Clear Pending Bit 312" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND311 ,Set/Clear Pending Bit 311" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310 ,Set/Clear Pending Bit 310" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND309 ,Set/Clear Pending Bit 309" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND308 ,Set/Clear Pending Bit 308" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307 ,Set/Clear Pending Bit 307" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND306 ,Set/Clear Pending Bit 306" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND305 ,Set/Clear Pending Bit 305" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304 ,Set/Clear Pending Bit 304" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND303 ,Set/Clear Pending Bit 303" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND302 ,Set/Clear Pending Bit 302" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301 ,Set/Clear Pending Bit 301" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND300 ,Set/Clear Pending Bit 300" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND299 ,Set/Clear Pending Bit 299" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298 ,Set/Clear Pending Bit 298" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND297 ,Set/Clear Pending Bit 297" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND296 ,Set/Clear Pending Bit 296" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295 ,Set/Clear Pending Bit 295" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND294 ,Set/Clear Pending Bit 294" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND293 ,Set/Clear Pending Bit 293" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292 ,Set/Clear Pending Bit 292" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND291 ,Set/Clear Pending Bit 291" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND290 ,Set/Clear Pending Bit 290" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289 ,Set/Clear Pending Bit 289" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND288 ,Set/Clear Pending Bit 288" "Not pending,Pending" else hgroup.long 0x0224++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351 ,Set/Clear Pending Bit 351" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND350 ,Set/Clear Pending Bit 350" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND349 ,Set/Clear Pending Bit 349" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348 ,Set/Clear Pending Bit 348" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND347 ,Set/Clear Pending Bit 347" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND346 ,Set/Clear Pending Bit 346" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345 ,Set/Clear Pending Bit 345" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND344 ,Set/Clear Pending Bit 344" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND343 ,Set/Clear Pending Bit 343" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342 ,Set/Clear Pending Bit 342" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND341 ,Set/Clear Pending Bit 341" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND340 ,Set/Clear Pending Bit 340" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339 ,Set/Clear Pending Bit 339" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND338 ,Set/Clear Pending Bit 338" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND337 ,Set/Clear Pending Bit 337" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336 ,Set/Clear Pending Bit 336" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND335 ,Set/Clear Pending Bit 335" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND334 ,Set/Clear Pending Bit 334" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333 ,Set/Clear Pending Bit 333" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND332 ,Set/Clear Pending Bit 332" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND331 ,Set/Clear Pending Bit 331" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330 ,Set/Clear Pending Bit 330" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND329 ,Set/Clear Pending Bit 329" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND328 ,Set/Clear Pending Bit 328" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327 ,Set/Clear Pending Bit 327" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND326 ,Set/Clear Pending Bit 326" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND325 ,Set/Clear Pending Bit 325" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324 ,Set/Clear Pending Bit 324" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND323 ,Set/Clear Pending Bit 323" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND322 ,Set/Clear Pending Bit 322" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321 ,Set/Clear Pending Bit 321" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND320 ,Set/Clear Pending Bit 320" "Not pending,Pending" else hgroup.long 0x0228++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383 ,Set/Clear Pending Bit 383" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND382 ,Set/Clear Pending Bit 382" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND381 ,Set/Clear Pending Bit 381" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380 ,Set/Clear Pending Bit 380" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND379 ,Set/Clear Pending Bit 379" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND378 ,Set/Clear Pending Bit 378" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377 ,Set/Clear Pending Bit 377" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND376 ,Set/Clear Pending Bit 376" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND375 ,Set/Clear Pending Bit 375" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374 ,Set/Clear Pending Bit 374" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND373 ,Set/Clear Pending Bit 373" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND372 ,Set/Clear Pending Bit 372" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371 ,Set/Clear Pending Bit 371" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND370 ,Set/Clear Pending Bit 370" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND369 ,Set/Clear Pending Bit 369" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368 ,Set/Clear Pending Bit 368" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND367 ,Set/Clear Pending Bit 367" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND366 ,Set/Clear Pending Bit 366" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365 ,Set/Clear Pending Bit 365" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND364 ,Set/Clear Pending Bit 364" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND363 ,Set/Clear Pending Bit 363" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362 ,Set/Clear Pending Bit 362" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND361 ,Set/Clear Pending Bit 361" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND360 ,Set/Clear Pending Bit 360" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359 ,Set/Clear Pending Bit 359" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND358 ,Set/Clear Pending Bit 358" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND357 ,Set/Clear Pending Bit 357" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356 ,Set/Clear Pending Bit 356" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND355 ,Set/Clear Pending Bit 355" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND354 ,Set/Clear Pending Bit 354" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353 ,Set/Clear Pending Bit 353" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND352 ,Set/Clear Pending Bit 352" "Not pending,Pending" else hgroup.long 0x022C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415 ,Set/Clear Pending Bit 415" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND414 ,Set/Clear Pending Bit 414" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND413 ,Set/Clear Pending Bit 413" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412 ,Set/Clear Pending Bit 412" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND411 ,Set/Clear Pending Bit 411" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND410 ,Set/Clear Pending Bit 410" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409 ,Set/Clear Pending Bit 409" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND408 ,Set/Clear Pending Bit 408" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND407 ,Set/Clear Pending Bit 407" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406 ,Set/Clear Pending Bit 406" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND405 ,Set/Clear Pending Bit 405" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND404 ,Set/Clear Pending Bit 404" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403 ,Set/Clear Pending Bit 403" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND402 ,Set/Clear Pending Bit 402" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND401 ,Set/Clear Pending Bit 401" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400 ,Set/Clear Pending Bit 400" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND399 ,Set/Clear Pending Bit 399" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND398 ,Set/Clear Pending Bit 398" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397 ,Set/Clear Pending Bit 397" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND396 ,Set/Clear Pending Bit 396" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND395 ,Set/Clear Pending Bit 395" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394 ,Set/Clear Pending Bit 394" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND393 ,Set/Clear Pending Bit 393" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND392 ,Set/Clear Pending Bit 392" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391 ,Set/Clear Pending Bit 391" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND390 ,Set/Clear Pending Bit 390" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND389 ,Set/Clear Pending Bit 389" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388 ,Set/Clear Pending Bit 388" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND387 ,Set/Clear Pending Bit 387" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND386 ,Set/Clear Pending Bit 386" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385 ,Set/Clear Pending Bit 385" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND384 ,Set/Clear Pending Bit 384" "Not pending,Pending" else hgroup.long 0x0230++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447 ,Set/Clear Pending Bit 447" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND446 ,Set/Clear Pending Bit 446" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND445 ,Set/Clear Pending Bit 445" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444 ,Set/Clear Pending Bit 444" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND443 ,Set/Clear Pending Bit 443" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND442 ,Set/Clear Pending Bit 442" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441 ,Set/Clear Pending Bit 441" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND440 ,Set/Clear Pending Bit 440" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND439 ,Set/Clear Pending Bit 439" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438 ,Set/Clear Pending Bit 438" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND437 ,Set/Clear Pending Bit 437" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND436 ,Set/Clear Pending Bit 436" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435 ,Set/Clear Pending Bit 435" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND434 ,Set/Clear Pending Bit 434" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND433 ,Set/Clear Pending Bit 433" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432 ,Set/Clear Pending Bit 432" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND431 ,Set/Clear Pending Bit 431" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND430 ,Set/Clear Pending Bit 430" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429 ,Set/Clear Pending Bit 429" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND428 ,Set/Clear Pending Bit 428" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND427 ,Set/Clear Pending Bit 427" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426 ,Set/Clear Pending Bit 426" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND425 ,Set/Clear Pending Bit 425" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND424 ,Set/Clear Pending Bit 424" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423 ,Set/Clear Pending Bit 423" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND422 ,Set/Clear Pending Bit 422" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND421 ,Set/Clear Pending Bit 421" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420 ,Set/Clear Pending Bit 420" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND419 ,Set/Clear Pending Bit 419" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND418 ,Set/Clear Pending Bit 418" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417 ,Set/Clear Pending Bit 417" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND416 ,Set/Clear Pending Bit 416" "Not pending,Pending" else hgroup.long 0x0234++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479 ,Set/Clear Pending Bit 479" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND478 ,Set/Clear Pending Bit 478" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND477 ,Set/Clear Pending Bit 477" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476 ,Set/Clear Pending Bit 476" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND475 ,Set/Clear Pending Bit 475" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND474 ,Set/Clear Pending Bit 474" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473 ,Set/Clear Pending Bit 473" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND472 ,Set/Clear Pending Bit 472" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND471 ,Set/Clear Pending Bit 471" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470 ,Set/Clear Pending Bit 470" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND469 ,Set/Clear Pending Bit 469" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND468 ,Set/Clear Pending Bit 468" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467 ,Set/Clear Pending Bit 467" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND466 ,Set/Clear Pending Bit 466" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND465 ,Set/Clear Pending Bit 465" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464 ,Set/Clear Pending Bit 464" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND463 ,Set/Clear Pending Bit 463" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND462 ,Set/Clear Pending Bit 462" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461 ,Set/Clear Pending Bit 461" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND460 ,Set/Clear Pending Bit 460" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND459 ,Set/Clear Pending Bit 459" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458 ,Set/Clear Pending Bit 458" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND457 ,Set/Clear Pending Bit 457" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND456 ,Set/Clear Pending Bit 456" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455 ,Set/Clear Pending Bit 455" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND454 ,Set/Clear Pending Bit 454" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND453 ,Set/Clear Pending Bit 453" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452 ,Set/Clear Pending Bit 452" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND451 ,Set/Clear Pending Bit 451" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND450 ,Set/Clear Pending Bit 450" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449 ,Set/Clear Pending Bit 449" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND448 ,Set/Clear Pending Bit 448" "Not pending,Pending" else hgroup.long 0x0238++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511 ,Set/Clear Pending Bit 511" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND510 ,Set/Clear Pending Bit 510" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND509 ,Set/Clear Pending Bit 509" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508 ,Set/Clear Pending Bit 508" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND507 ,Set/Clear Pending Bit 507" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND506 ,Set/Clear Pending Bit 506" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505 ,Set/Clear Pending Bit 505" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND504 ,Set/Clear Pending Bit 504" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND503 ,Set/Clear Pending Bit 503" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502 ,Set/Clear Pending Bit 502" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND501 ,Set/Clear Pending Bit 501" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND500 ,Set/Clear Pending Bit 500" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499 ,Set/Clear Pending Bit 499" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND498 ,Set/Clear Pending Bit 498" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND497 ,Set/Clear Pending Bit 497" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496 ,Set/Clear Pending Bit 496" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND495 ,Set/Clear Pending Bit 495" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND494 ,Set/Clear Pending Bit 494" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493 ,Set/Clear Pending Bit 493" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND492 ,Set/Clear Pending Bit 492" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND491 ,Set/Clear Pending Bit 491" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490 ,Set/Clear Pending Bit 490" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND489 ,Set/Clear Pending Bit 489" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND488 ,Set/Clear Pending Bit 488" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487 ,Set/Clear Pending Bit 487" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND486 ,Set/Clear Pending Bit 486" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND485 ,Set/Clear Pending Bit 485" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484 ,Set/Clear Pending Bit 484" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND483 ,Set/Clear Pending Bit 483" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND482 ,Set/Clear Pending Bit 482" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481 ,Set/Clear Pending Bit 481" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND480 ,Set/Clear Pending Bit 480" "Not pending,Pending" else hgroup.long 0x023C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543 ,Set/Clear Pending Bit 543" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND542 ,Set/Clear Pending Bit 542" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND541 ,Set/Clear Pending Bit 541" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540 ,Set/Clear Pending Bit 540" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND539 ,Set/Clear Pending Bit 539" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND538 ,Set/Clear Pending Bit 538" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537 ,Set/Clear Pending Bit 537" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND536 ,Set/Clear Pending Bit 536" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND535 ,Set/Clear Pending Bit 535" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534 ,Set/Clear Pending Bit 534" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND533 ,Set/Clear Pending Bit 533" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND532 ,Set/Clear Pending Bit 532" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531 ,Set/Clear Pending Bit 531" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND530 ,Set/Clear Pending Bit 530" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND529 ,Set/Clear Pending Bit 529" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528 ,Set/Clear Pending Bit 528" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND527 ,Set/Clear Pending Bit 527" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND526 ,Set/Clear Pending Bit 526" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525 ,Set/Clear Pending Bit 525" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND524 ,Set/Clear Pending Bit 524" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND523 ,Set/Clear Pending Bit 523" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522 ,Set/Clear Pending Bit 522" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND521 ,Set/Clear Pending Bit 521" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND520 ,Set/Clear Pending Bit 520" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519 ,Set/Clear Pending Bit 519" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND518 ,Set/Clear Pending Bit 518" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND517 ,Set/Clear Pending Bit 517" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516 ,Set/Clear Pending Bit 516" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND515 ,Set/Clear Pending Bit 515" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND514 ,Set/Clear Pending Bit 514" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513 ,Set/Clear Pending Bit 513" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND512 ,Set/Clear Pending Bit 512" "Not pending,Pending" else hgroup.long 0x0240++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575 ,Set/Clear Pending Bit 575" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND574 ,Set/Clear Pending Bit 574" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND573 ,Set/Clear Pending Bit 573" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572 ,Set/Clear Pending Bit 572" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND571 ,Set/Clear Pending Bit 571" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND570 ,Set/Clear Pending Bit 570" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569 ,Set/Clear Pending Bit 569" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND568 ,Set/Clear Pending Bit 568" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND567 ,Set/Clear Pending Bit 567" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566 ,Set/Clear Pending Bit 566" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND565 ,Set/Clear Pending Bit 565" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND564 ,Set/Clear Pending Bit 564" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563 ,Set/Clear Pending Bit 563" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND562 ,Set/Clear Pending Bit 562" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND561 ,Set/Clear Pending Bit 561" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560 ,Set/Clear Pending Bit 560" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND559 ,Set/Clear Pending Bit 559" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND558 ,Set/Clear Pending Bit 558" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557 ,Set/Clear Pending Bit 557" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND556 ,Set/Clear Pending Bit 556" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND555 ,Set/Clear Pending Bit 555" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554 ,Set/Clear Pending Bit 554" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND553 ,Set/Clear Pending Bit 553" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND552 ,Set/Clear Pending Bit 552" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551 ,Set/Clear Pending Bit 551" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND550 ,Set/Clear Pending Bit 550" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND549 ,Set/Clear Pending Bit 549" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548 ,Set/Clear Pending Bit 548" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND547 ,Set/Clear Pending Bit 547" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND546 ,Set/Clear Pending Bit 546" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545 ,Set/Clear Pending Bit 545" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND544 ,Set/Clear Pending Bit 544" "Not pending,Pending" else hgroup.long 0x0244++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607 ,Set/Clear Pending Bit 607" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND606 ,Set/Clear Pending Bit 606" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND605 ,Set/Clear Pending Bit 605" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604 ,Set/Clear Pending Bit 604" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND603 ,Set/Clear Pending Bit 603" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND602 ,Set/Clear Pending Bit 602" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601 ,Set/Clear Pending Bit 601" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND600 ,Set/Clear Pending Bit 600" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND599 ,Set/Clear Pending Bit 599" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598 ,Set/Clear Pending Bit 598" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND597 ,Set/Clear Pending Bit 597" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND596 ,Set/Clear Pending Bit 596" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595 ,Set/Clear Pending Bit 595" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND594 ,Set/Clear Pending Bit 594" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND593 ,Set/Clear Pending Bit 593" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592 ,Set/Clear Pending Bit 592" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND591 ,Set/Clear Pending Bit 591" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND590 ,Set/Clear Pending Bit 590" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589 ,Set/Clear Pending Bit 589" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND588 ,Set/Clear Pending Bit 588" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND587 ,Set/Clear Pending Bit 587" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586 ,Set/Clear Pending Bit 586" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND585 ,Set/Clear Pending Bit 585" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND584 ,Set/Clear Pending Bit 584" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583 ,Set/Clear Pending Bit 583" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND582 ,Set/Clear Pending Bit 582" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND581 ,Set/Clear Pending Bit 581" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580 ,Set/Clear Pending Bit 580" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND579 ,Set/Clear Pending Bit 579" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND578 ,Set/Clear Pending Bit 578" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577 ,Set/Clear Pending Bit 577" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND576 ,Set/Clear Pending Bit 576" "Not pending,Pending" else hgroup.long 0x0248++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639 ,Set/Clear Pending Bit 639" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND638 ,Set/Clear Pending Bit 638" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND637 ,Set/Clear Pending Bit 637" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636 ,Set/Clear Pending Bit 636" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND635 ,Set/Clear Pending Bit 635" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND634 ,Set/Clear Pending Bit 634" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633 ,Set/Clear Pending Bit 633" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND632 ,Set/Clear Pending Bit 632" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND631 ,Set/Clear Pending Bit 631" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630 ,Set/Clear Pending Bit 630" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND629 ,Set/Clear Pending Bit 629" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND628 ,Set/Clear Pending Bit 628" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627 ,Set/Clear Pending Bit 627" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND626 ,Set/Clear Pending Bit 626" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND625 ,Set/Clear Pending Bit 625" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624 ,Set/Clear Pending Bit 624" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND623 ,Set/Clear Pending Bit 623" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND622 ,Set/Clear Pending Bit 622" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621 ,Set/Clear Pending Bit 621" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND620 ,Set/Clear Pending Bit 620" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND619 ,Set/Clear Pending Bit 619" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618 ,Set/Clear Pending Bit 618" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND617 ,Set/Clear Pending Bit 617" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND616 ,Set/Clear Pending Bit 616" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615 ,Set/Clear Pending Bit 615" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND614 ,Set/Clear Pending Bit 614" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND613 ,Set/Clear Pending Bit 613" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612 ,Set/Clear Pending Bit 612" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND611 ,Set/Clear Pending Bit 611" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND610 ,Set/Clear Pending Bit 610" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609 ,Set/Clear Pending Bit 609" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND608 ,Set/Clear Pending Bit 608" "Not pending,Pending" else hgroup.long 0x024C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671 ,Set/Clear Pending Bit 671" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND670 ,Set/Clear Pending Bit 670" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND669 ,Set/Clear Pending Bit 669" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668 ,Set/Clear Pending Bit 668" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND667 ,Set/Clear Pending Bit 667" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND666 ,Set/Clear Pending Bit 666" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665 ,Set/Clear Pending Bit 665" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND664 ,Set/Clear Pending Bit 664" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND663 ,Set/Clear Pending Bit 663" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662 ,Set/Clear Pending Bit 662" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND661 ,Set/Clear Pending Bit 661" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND660 ,Set/Clear Pending Bit 660" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659 ,Set/Clear Pending Bit 659" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND658 ,Set/Clear Pending Bit 658" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND657 ,Set/Clear Pending Bit 657" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656 ,Set/Clear Pending Bit 656" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND655 ,Set/Clear Pending Bit 655" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND654 ,Set/Clear Pending Bit 654" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653 ,Set/Clear Pending Bit 653" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND652 ,Set/Clear Pending Bit 652" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND651 ,Set/Clear Pending Bit 651" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650 ,Set/Clear Pending Bit 650" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND649 ,Set/Clear Pending Bit 649" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND648 ,Set/Clear Pending Bit 648" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647 ,Set/Clear Pending Bit 647" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND646 ,Set/Clear Pending Bit 646" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND645 ,Set/Clear Pending Bit 645" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644 ,Set/Clear Pending Bit 644" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND643 ,Set/Clear Pending Bit 643" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND642 ,Set/Clear Pending Bit 642" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641 ,Set/Clear Pending Bit 641" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND640 ,Set/Clear Pending Bit 640" "Not pending,Pending" else hgroup.long 0x0250++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703 ,Set/Clear Pending Bit 703" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND702 ,Set/Clear Pending Bit 702" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND701 ,Set/Clear Pending Bit 701" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700 ,Set/Clear Pending Bit 700" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND699 ,Set/Clear Pending Bit 699" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND698 ,Set/Clear Pending Bit 698" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697 ,Set/Clear Pending Bit 697" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND696 ,Set/Clear Pending Bit 696" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND695 ,Set/Clear Pending Bit 695" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694 ,Set/Clear Pending Bit 694" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND693 ,Set/Clear Pending Bit 693" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND692 ,Set/Clear Pending Bit 692" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691 ,Set/Clear Pending Bit 691" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND690 ,Set/Clear Pending Bit 690" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND689 ,Set/Clear Pending Bit 689" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688 ,Set/Clear Pending Bit 688" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND687 ,Set/Clear Pending Bit 687" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND686 ,Set/Clear Pending Bit 686" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685 ,Set/Clear Pending Bit 685" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND684 ,Set/Clear Pending Bit 684" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND683 ,Set/Clear Pending Bit 683" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682 ,Set/Clear Pending Bit 682" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND681 ,Set/Clear Pending Bit 681" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND680 ,Set/Clear Pending Bit 680" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679 ,Set/Clear Pending Bit 679" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND678 ,Set/Clear Pending Bit 678" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND677 ,Set/Clear Pending Bit 677" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676 ,Set/Clear Pending Bit 676" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND675 ,Set/Clear Pending Bit 675" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND674 ,Set/Clear Pending Bit 674" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673 ,Set/Clear Pending Bit 673" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND672 ,Set/Clear Pending Bit 672" "Not pending,Pending" else hgroup.long 0x0254++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735 ,Set/Clear Pending Bit 735" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND734 ,Set/Clear Pending Bit 734" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND733 ,Set/Clear Pending Bit 733" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732 ,Set/Clear Pending Bit 732" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND731 ,Set/Clear Pending Bit 731" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND730 ,Set/Clear Pending Bit 730" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729 ,Set/Clear Pending Bit 729" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND728 ,Set/Clear Pending Bit 728" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND727 ,Set/Clear Pending Bit 727" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726 ,Set/Clear Pending Bit 726" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND725 ,Set/Clear Pending Bit 725" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND724 ,Set/Clear Pending Bit 724" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723 ,Set/Clear Pending Bit 723" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND722 ,Set/Clear Pending Bit 722" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND721 ,Set/Clear Pending Bit 721" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720 ,Set/Clear Pending Bit 720" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND719 ,Set/Clear Pending Bit 719" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND718 ,Set/Clear Pending Bit 718" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717 ,Set/Clear Pending Bit 717" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND716 ,Set/Clear Pending Bit 716" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND715 ,Set/Clear Pending Bit 715" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714 ,Set/Clear Pending Bit 714" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND713 ,Set/Clear Pending Bit 713" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND712 ,Set/Clear Pending Bit 712" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711 ,Set/Clear Pending Bit 711" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND710 ,Set/Clear Pending Bit 710" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND709 ,Set/Clear Pending Bit 709" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708 ,Set/Clear Pending Bit 708" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND707 ,Set/Clear Pending Bit 707" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND706 ,Set/Clear Pending Bit 706" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705 ,Set/Clear Pending Bit 705" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND704 ,Set/Clear Pending Bit 704" "Not pending,Pending" else hgroup.long 0x0258++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767 ,Set/Clear Pending Bit 767" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND766 ,Set/Clear Pending Bit 766" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND765 ,Set/Clear Pending Bit 765" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764 ,Set/Clear Pending Bit 764" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND763 ,Set/Clear Pending Bit 763" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND762 ,Set/Clear Pending Bit 762" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761 ,Set/Clear Pending Bit 761" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND760 ,Set/Clear Pending Bit 760" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND759 ,Set/Clear Pending Bit 759" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758 ,Set/Clear Pending Bit 758" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND757 ,Set/Clear Pending Bit 757" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND756 ,Set/Clear Pending Bit 756" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755 ,Set/Clear Pending Bit 755" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND754 ,Set/Clear Pending Bit 754" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND753 ,Set/Clear Pending Bit 753" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752 ,Set/Clear Pending Bit 752" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND751 ,Set/Clear Pending Bit 751" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND750 ,Set/Clear Pending Bit 750" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749 ,Set/Clear Pending Bit 749" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND748 ,Set/Clear Pending Bit 748" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND747 ,Set/Clear Pending Bit 747" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746 ,Set/Clear Pending Bit 746" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND745 ,Set/Clear Pending Bit 745" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND744 ,Set/Clear Pending Bit 744" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743 ,Set/Clear Pending Bit 743" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND742 ,Set/Clear Pending Bit 742" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND741 ,Set/Clear Pending Bit 741" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740 ,Set/Clear Pending Bit 740" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND739 ,Set/Clear Pending Bit 739" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND738 ,Set/Clear Pending Bit 738" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737 ,Set/Clear Pending Bit 737" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND736 ,Set/Clear Pending Bit 736" "Not pending,Pending" else hgroup.long 0x025C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799 ,Set/Clear Pending Bit 799" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND798 ,Set/Clear Pending Bit 798" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND797 ,Set/Clear Pending Bit 797" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796 ,Set/Clear Pending Bit 796" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND795 ,Set/Clear Pending Bit 795" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND794 ,Set/Clear Pending Bit 794" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793 ,Set/Clear Pending Bit 793" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND792 ,Set/Clear Pending Bit 792" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND791 ,Set/Clear Pending Bit 791" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790 ,Set/Clear Pending Bit 790" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND789 ,Set/Clear Pending Bit 789" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND788 ,Set/Clear Pending Bit 788" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787 ,Set/Clear Pending Bit 787" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND786 ,Set/Clear Pending Bit 786" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND785 ,Set/Clear Pending Bit 785" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784 ,Set/Clear Pending Bit 784" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND783 ,Set/Clear Pending Bit 783" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND782 ,Set/Clear Pending Bit 782" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781 ,Set/Clear Pending Bit 781" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND780 ,Set/Clear Pending Bit 780" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND779 ,Set/Clear Pending Bit 779" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778 ,Set/Clear Pending Bit 778" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND777 ,Set/Clear Pending Bit 777" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND776 ,Set/Clear Pending Bit 776" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775 ,Set/Clear Pending Bit 775" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND774 ,Set/Clear Pending Bit 774" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND773 ,Set/Clear Pending Bit 773" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772 ,Set/Clear Pending Bit 772" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND771 ,Set/Clear Pending Bit 771" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND770 ,Set/Clear Pending Bit 770" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769 ,Set/Clear Pending Bit 769" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND768 ,Set/Clear Pending Bit 768" "Not pending,Pending" else hgroup.long 0x0260++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831 ,Set/Clear Pending Bit 831" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND830 ,Set/Clear Pending Bit 830" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND829 ,Set/Clear Pending Bit 829" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828 ,Set/Clear Pending Bit 828" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND827 ,Set/Clear Pending Bit 827" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND826 ,Set/Clear Pending Bit 826" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825 ,Set/Clear Pending Bit 825" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND824 ,Set/Clear Pending Bit 824" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND823 ,Set/Clear Pending Bit 823" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822 ,Set/Clear Pending Bit 822" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND821 ,Set/Clear Pending Bit 821" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND820 ,Set/Clear Pending Bit 820" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819 ,Set/Clear Pending Bit 819" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND818 ,Set/Clear Pending Bit 818" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND817 ,Set/Clear Pending Bit 817" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816 ,Set/Clear Pending Bit 816" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND815 ,Set/Clear Pending Bit 815" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND814 ,Set/Clear Pending Bit 814" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813 ,Set/Clear Pending Bit 813" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND812 ,Set/Clear Pending Bit 812" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND811 ,Set/Clear Pending Bit 811" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810 ,Set/Clear Pending Bit 810" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND809 ,Set/Clear Pending Bit 809" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND808 ,Set/Clear Pending Bit 808" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807 ,Set/Clear Pending Bit 807" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND806 ,Set/Clear Pending Bit 806" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND805 ,Set/Clear Pending Bit 805" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804 ,Set/Clear Pending Bit 804" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND803 ,Set/Clear Pending Bit 803" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND802 ,Set/Clear Pending Bit 802" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801 ,Set/Clear Pending Bit 801" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND800 ,Set/Clear Pending Bit 800" "Not pending,Pending" else hgroup.long 0x0264++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863 ,Set/Clear Pending Bit 863" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND862 ,Set/Clear Pending Bit 862" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND861 ,Set/Clear Pending Bit 861" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860 ,Set/Clear Pending Bit 860" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND859 ,Set/Clear Pending Bit 859" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND858 ,Set/Clear Pending Bit 858" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857 ,Set/Clear Pending Bit 857" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND856 ,Set/Clear Pending Bit 856" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND855 ,Set/Clear Pending Bit 855" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854 ,Set/Clear Pending Bit 854" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND853 ,Set/Clear Pending Bit 853" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND852 ,Set/Clear Pending Bit 852" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851 ,Set/Clear Pending Bit 851" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND850 ,Set/Clear Pending Bit 850" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND849 ,Set/Clear Pending Bit 849" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848 ,Set/Clear Pending Bit 848" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND847 ,Set/Clear Pending Bit 847" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND846 ,Set/Clear Pending Bit 846" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845 ,Set/Clear Pending Bit 845" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND844 ,Set/Clear Pending Bit 844" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND843 ,Set/Clear Pending Bit 843" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842 ,Set/Clear Pending Bit 842" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND841 ,Set/Clear Pending Bit 841" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND840 ,Set/Clear Pending Bit 840" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839 ,Set/Clear Pending Bit 839" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND838 ,Set/Clear Pending Bit 838" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND837 ,Set/Clear Pending Bit 837" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836 ,Set/Clear Pending Bit 836" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND835 ,Set/Clear Pending Bit 835" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND834 ,Set/Clear Pending Bit 834" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833 ,Set/Clear Pending Bit 833" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND832 ,Set/Clear Pending Bit 832" "Not pending,Pending" else hgroup.long 0x0268++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895 ,Set/Clear Pending Bit 895" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND894 ,Set/Clear Pending Bit 894" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND893 ,Set/Clear Pending Bit 893" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892 ,Set/Clear Pending Bit 892" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND891 ,Set/Clear Pending Bit 891" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND890 ,Set/Clear Pending Bit 890" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889 ,Set/Clear Pending Bit 889" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND888 ,Set/Clear Pending Bit 888" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND887 ,Set/Clear Pending Bit 887" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886 ,Set/Clear Pending Bit 886" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND885 ,Set/Clear Pending Bit 885" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND884 ,Set/Clear Pending Bit 884" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883 ,Set/Clear Pending Bit 883" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND882 ,Set/Clear Pending Bit 882" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND881 ,Set/Clear Pending Bit 881" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880 ,Set/Clear Pending Bit 880" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND879 ,Set/Clear Pending Bit 879" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND878 ,Set/Clear Pending Bit 878" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877 ,Set/Clear Pending Bit 877" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND876 ,Set/Clear Pending Bit 876" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND875 ,Set/Clear Pending Bit 875" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874 ,Set/Clear Pending Bit 874" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND873 ,Set/Clear Pending Bit 873" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND872 ,Set/Clear Pending Bit 872" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871 ,Set/Clear Pending Bit 871" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND870 ,Set/Clear Pending Bit 870" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND869 ,Set/Clear Pending Bit 869" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868 ,Set/Clear Pending Bit 868" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND867 ,Set/Clear Pending Bit 867" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND866 ,Set/Clear Pending Bit 866" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865 ,Set/Clear Pending Bit 865" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND864 ,Set/Clear Pending Bit 864" "Not pending,Pending" else hgroup.long 0x026C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927 ,Set/Clear Pending Bit 927" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND926 ,Set/Clear Pending Bit 926" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND925 ,Set/Clear Pending Bit 925" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924 ,Set/Clear Pending Bit 924" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND923 ,Set/Clear Pending Bit 923" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND922 ,Set/Clear Pending Bit 922" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921 ,Set/Clear Pending Bit 921" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND920 ,Set/Clear Pending Bit 920" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND919 ,Set/Clear Pending Bit 919" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918 ,Set/Clear Pending Bit 918" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND917 ,Set/Clear Pending Bit 917" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND916 ,Set/Clear Pending Bit 916" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915 ,Set/Clear Pending Bit 915" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND914 ,Set/Clear Pending Bit 914" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND913 ,Set/Clear Pending Bit 913" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912 ,Set/Clear Pending Bit 912" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND911 ,Set/Clear Pending Bit 911" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND910 ,Set/Clear Pending Bit 910" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909 ,Set/Clear Pending Bit 909" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND908 ,Set/Clear Pending Bit 908" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND907 ,Set/Clear Pending Bit 907" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906 ,Set/Clear Pending Bit 906" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND905 ,Set/Clear Pending Bit 905" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND904 ,Set/Clear Pending Bit 904" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903 ,Set/Clear Pending Bit 903" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND902 ,Set/Clear Pending Bit 902" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND901 ,Set/Clear Pending Bit 901" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900 ,Set/Clear Pending Bit 900" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND899 ,Set/Clear Pending Bit 899" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND898 ,Set/Clear Pending Bit 898" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897 ,Set/Clear Pending Bit 897" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND896 ,Set/Clear Pending Bit 896" "Not pending,Pending" else hgroup.long 0x0270++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959 ,Set/Clear Pending Bit 959" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND958 ,Set/Clear Pending Bit 958" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND957 ,Set/Clear Pending Bit 957" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956 ,Set/Clear Pending Bit 956" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND955 ,Set/Clear Pending Bit 955" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND954 ,Set/Clear Pending Bit 954" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953 ,Set/Clear Pending Bit 953" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND952 ,Set/Clear Pending Bit 952" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND951 ,Set/Clear Pending Bit 951" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950 ,Set/Clear Pending Bit 950" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND949 ,Set/Clear Pending Bit 949" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND948 ,Set/Clear Pending Bit 948" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947 ,Set/Clear Pending Bit 947" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND946 ,Set/Clear Pending Bit 946" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND945 ,Set/Clear Pending Bit 945" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944 ,Set/Clear Pending Bit 944" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND943 ,Set/Clear Pending Bit 943" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND942 ,Set/Clear Pending Bit 942" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941 ,Set/Clear Pending Bit 941" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND940 ,Set/Clear Pending Bit 940" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND939 ,Set/Clear Pending Bit 939" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938 ,Set/Clear Pending Bit 938" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND937 ,Set/Clear Pending Bit 937" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND936 ,Set/Clear Pending Bit 936" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935 ,Set/Clear Pending Bit 935" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND934 ,Set/Clear Pending Bit 934" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND933 ,Set/Clear Pending Bit 933" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932 ,Set/Clear Pending Bit 932" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND931 ,Set/Clear Pending Bit 931" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND930 ,Set/Clear Pending Bit 930" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929 ,Set/Clear Pending Bit 929" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND928 ,Set/Clear Pending Bit 928" "Not pending,Pending" else hgroup.long 0x0274++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991 ,Set/Clear Pending Bit 991" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND990 ,Set/Clear Pending Bit 990" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND989 ,Set/Clear Pending Bit 989" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988 ,Set/Clear Pending Bit 988" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND987 ,Set/Clear Pending Bit 987" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND986 ,Set/Clear Pending Bit 986" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985 ,Set/Clear Pending Bit 985" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND984 ,Set/Clear Pending Bit 984" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND983 ,Set/Clear Pending Bit 983" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982 ,Set/Clear Pending Bit 982" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND981 ,Set/Clear Pending Bit 981" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND980 ,Set/Clear Pending Bit 980" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979 ,Set/Clear Pending Bit 979" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND978 ,Set/Clear Pending Bit 978" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND977 ,Set/Clear Pending Bit 977" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976 ,Set/Clear Pending Bit 976" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND975 ,Set/Clear Pending Bit 975" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND974 ,Set/Clear Pending Bit 974" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973 ,Set/Clear Pending Bit 973" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND972 ,Set/Clear Pending Bit 972" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND971 ,Set/Clear Pending Bit 971" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970 ,Set/Clear Pending Bit 970" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND969 ,Set/Clear Pending Bit 969" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND968 ,Set/Clear Pending Bit 968" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967 ,Set/Clear Pending Bit 967" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND966 ,Set/Clear Pending Bit 966" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND965 ,Set/Clear Pending Bit 965" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964 ,Set/Clear Pending Bit 964" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND963 ,Set/Clear Pending Bit 963" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND962 ,Set/Clear Pending Bit 962" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961 ,Set/Clear Pending Bit 961" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND960 ,Set/Clear Pending Bit 960" "Not pending,Pending" else hgroup.long 0x0278++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" endif tree.end width 24. tree "Set/Clear Active Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0300++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" newline newline newline newline newline newline newline newline newline newline else group.long 0x0300++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE9 ,Set/Clear Active Bit 9" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE8 ,Set/Clear Active Bit 8" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7 ,Set/Clear Active Bit 7" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE6 ,Set/Clear Active Bit 6" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE5 ,Set/Clear Active Bit 5" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4 ,Set/Clear Active Bit 4" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE3 ,Set/Clear Active Bit 3" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE2 ,Set/Clear Active Bit 2" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1 ,Set/Clear Active Bit 1" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE0 ,Set/Clear Active Bit 0" "Not active,Active" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0304++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63 ,Set/Clear Active Bit 63" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE62 ,Set/Clear Active Bit 62" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE61 ,Set/Clear Active Bit 61" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60 ,Set/Clear Active Bit 60" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE59 ,Set/Clear Active Bit 59" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE58 ,Set/Clear Active Bit 58" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57 ,Set/Clear Active Bit 57" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE56 ,Set/Clear Active Bit 56" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE55 ,Set/Clear Active Bit 55" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54 ,Set/Clear Active Bit 54" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE53 ,Set/Clear Active Bit 53" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE52 ,Set/Clear Active Bit 52" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51 ,Set/Clear Active Bit 51" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE50 ,Set/Clear Active Bit 50" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE49 ,Set/Clear Active Bit 49" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48 ,Set/Clear Active Bit 48" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE47 ,Set/Clear Active Bit 47" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE46 ,Set/Clear Active Bit 46" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45 ,Set/Clear Active Bit 45" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE44 ,Set/Clear Active Bit 44" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE43 ,Set/Clear Active Bit 43" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42 ,Set/Clear Active Bit 42" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE41 ,Set/Clear Active Bit 41" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE40 ,Set/Clear Active Bit 40" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39 ,Set/Clear Active Bit 39" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE38 ,Set/Clear Active Bit 38" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE37 ,Set/Clear Active Bit 37" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36 ,Set/Clear Active Bit 36" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE35 ,Set/Clear Active Bit 35" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE34 ,Set/Clear Active Bit 34" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33 ,Set/Clear Active Bit 33" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE32 ,Set/Clear Active Bit 32" "Not active,Active" else hgroup.long 0x0304++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0308++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95 ,Set/Clear Active Bit 95" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE94 ,Set/Clear Active Bit 94" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE93 ,Set/Clear Active Bit 93" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92 ,Set/Clear Active Bit 92" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE91 ,Set/Clear Active Bit 91" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE90 ,Set/Clear Active Bit 90" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89 ,Set/Clear Active Bit 89" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE88 ,Set/Clear Active Bit 88" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE87 ,Set/Clear Active Bit 87" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86 ,Set/Clear Active Bit 86" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE85 ,Set/Clear Active Bit 85" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE84 ,Set/Clear Active Bit 84" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83 ,Set/Clear Active Bit 83" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE82 ,Set/Clear Active Bit 82" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE81 ,Set/Clear Active Bit 81" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80 ,Set/Clear Active Bit 80" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE79 ,Set/Clear Active Bit 79" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE78 ,Set/Clear Active Bit 78" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77 ,Set/Clear Active Bit 77" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE76 ,Set/Clear Active Bit 76" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE75 ,Set/Clear Active Bit 75" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74 ,Set/Clear Active Bit 74" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE73 ,Set/Clear Active Bit 73" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE72 ,Set/Clear Active Bit 72" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71 ,Set/Clear Active Bit 71" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE70 ,Set/Clear Active Bit 70" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE69 ,Set/Clear Active Bit 69" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68 ,Set/Clear Active Bit 68" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE67 ,Set/Clear Active Bit 67" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE66 ,Set/Clear Active Bit 66" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65 ,Set/Clear Active Bit 65" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE64 ,Set/Clear Active Bit 64" "Not active,Active" else hgroup.long 0x0308++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x030C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE99 ,Set/Clear Active Bit 99" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE98 ,Set/Clear Active Bit 98" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97 ,Set/Clear Active Bit 97" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE96 ,Set/Clear Active Bit 96" "Not active,Active" else hgroup.long 0x030C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0310++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active" else hgroup.long 0x0310++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0314++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active" else hgroup.long 0x0314++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0318++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active" else hgroup.long 0x0318++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x031C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active" else hgroup.long 0x031C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0320++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active" else hgroup.long 0x0320++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0324++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active" else hgroup.long 0x0324++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0328++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active" else hgroup.long 0x0328++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x032C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active" else hgroup.long 0x032C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0330++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active" else hgroup.long 0x0330++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0334++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active" else hgroup.long 0x0334++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0338++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active" else hgroup.long 0x0338++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x033C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active" else hgroup.long 0x033C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0340++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE543 ,Set/Clear Active Bit 543" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE542 ,Set/Clear Active Bit 542" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE541 ,Set/Clear Active Bit 541" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE540 ,Set/Clear Active Bit 540" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE539 ,Set/Clear Active Bit 539" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE538 ,Set/Clear Active Bit 538" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE537 ,Set/Clear Active Bit 537" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE536 ,Set/Clear Active Bit 536" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE535 ,Set/Clear Active Bit 535" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE534 ,Set/Clear Active Bit 534" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE533 ,Set/Clear Active Bit 533" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE532 ,Set/Clear Active Bit 532" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE531 ,Set/Clear Active Bit 531" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE530 ,Set/Clear Active Bit 530" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE529 ,Set/Clear Active Bit 529" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE528 ,Set/Clear Active Bit 528" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE527 ,Set/Clear Active Bit 527" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE526 ,Set/Clear Active Bit 526" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE525 ,Set/Clear Active Bit 525" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE524 ,Set/Clear Active Bit 524" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE523 ,Set/Clear Active Bit 523" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE522 ,Set/Clear Active Bit 522" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE521 ,Set/Clear Active Bit 521" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE520 ,Set/Clear Active Bit 520" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE519 ,Set/Clear Active Bit 519" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE518 ,Set/Clear Active Bit 518" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE517 ,Set/Clear Active Bit 517" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE516 ,Set/Clear Active Bit 516" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE515 ,Set/Clear Active Bit 515" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE514 ,Set/Clear Active Bit 514" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE513 ,Set/Clear Active Bit 513" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE512 ,Set/Clear Active Bit 512" "Not active,Active" else hgroup.long 0x0340++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0344++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE575 ,Set/Clear Active Bit 575" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE574 ,Set/Clear Active Bit 574" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE573 ,Set/Clear Active Bit 573" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE572 ,Set/Clear Active Bit 572" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE571 ,Set/Clear Active Bit 571" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE570 ,Set/Clear Active Bit 570" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE569 ,Set/Clear Active Bit 569" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE568 ,Set/Clear Active Bit 568" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE567 ,Set/Clear Active Bit 567" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE566 ,Set/Clear Active Bit 566" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE565 ,Set/Clear Active Bit 565" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE564 ,Set/Clear Active Bit 564" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE563 ,Set/Clear Active Bit 563" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE562 ,Set/Clear Active Bit 562" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE561 ,Set/Clear Active Bit 561" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE560 ,Set/Clear Active Bit 560" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE559 ,Set/Clear Active Bit 559" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE558 ,Set/Clear Active Bit 558" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE557 ,Set/Clear Active Bit 557" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE556 ,Set/Clear Active Bit 556" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE555 ,Set/Clear Active Bit 555" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE554 ,Set/Clear Active Bit 554" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE553 ,Set/Clear Active Bit 553" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE552 ,Set/Clear Active Bit 552" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE551 ,Set/Clear Active Bit 551" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE550 ,Set/Clear Active Bit 550" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE549 ,Set/Clear Active Bit 549" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE548 ,Set/Clear Active Bit 548" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE547 ,Set/Clear Active Bit 547" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE546 ,Set/Clear Active Bit 546" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE545 ,Set/Clear Active Bit 545" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE544 ,Set/Clear Active Bit 544" "Not active,Active" else hgroup.long 0x0344++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0348++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE607 ,Set/Clear Active Bit 607" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE606 ,Set/Clear Active Bit 606" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE605 ,Set/Clear Active Bit 605" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE604 ,Set/Clear Active Bit 604" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE603 ,Set/Clear Active Bit 603" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE602 ,Set/Clear Active Bit 602" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE601 ,Set/Clear Active Bit 601" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE600 ,Set/Clear Active Bit 600" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE599 ,Set/Clear Active Bit 599" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE598 ,Set/Clear Active Bit 598" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE597 ,Set/Clear Active Bit 597" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE596 ,Set/Clear Active Bit 596" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE595 ,Set/Clear Active Bit 595" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE594 ,Set/Clear Active Bit 594" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE593 ,Set/Clear Active Bit 593" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE592 ,Set/Clear Active Bit 592" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE591 ,Set/Clear Active Bit 591" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE590 ,Set/Clear Active Bit 590" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE589 ,Set/Clear Active Bit 589" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE588 ,Set/Clear Active Bit 588" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE587 ,Set/Clear Active Bit 587" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE586 ,Set/Clear Active Bit 586" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE585 ,Set/Clear Active Bit 585" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE584 ,Set/Clear Active Bit 584" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE583 ,Set/Clear Active Bit 583" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE582 ,Set/Clear Active Bit 582" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE581 ,Set/Clear Active Bit 581" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE580 ,Set/Clear Active Bit 580" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE579 ,Set/Clear Active Bit 579" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE578 ,Set/Clear Active Bit 578" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE577 ,Set/Clear Active Bit 577" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE576 ,Set/Clear Active Bit 576" "Not active,Active" else hgroup.long 0x0348++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x034C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE639 ,Set/Clear Active Bit 639" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE638 ,Set/Clear Active Bit 638" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE637 ,Set/Clear Active Bit 637" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE636 ,Set/Clear Active Bit 636" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE635 ,Set/Clear Active Bit 635" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE634 ,Set/Clear Active Bit 634" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE633 ,Set/Clear Active Bit 633" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE632 ,Set/Clear Active Bit 632" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE631 ,Set/Clear Active Bit 631" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE630 ,Set/Clear Active Bit 630" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE629 ,Set/Clear Active Bit 629" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE628 ,Set/Clear Active Bit 628" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE627 ,Set/Clear Active Bit 627" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE626 ,Set/Clear Active Bit 626" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE625 ,Set/Clear Active Bit 625" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE624 ,Set/Clear Active Bit 624" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE623 ,Set/Clear Active Bit 623" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE622 ,Set/Clear Active Bit 622" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE621 ,Set/Clear Active Bit 621" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE620 ,Set/Clear Active Bit 620" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE619 ,Set/Clear Active Bit 619" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE618 ,Set/Clear Active Bit 618" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE617 ,Set/Clear Active Bit 617" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE616 ,Set/Clear Active Bit 616" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE615 ,Set/Clear Active Bit 615" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE614 ,Set/Clear Active Bit 614" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE613 ,Set/Clear Active Bit 613" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE612 ,Set/Clear Active Bit 612" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE611 ,Set/Clear Active Bit 611" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE610 ,Set/Clear Active Bit 610" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE609 ,Set/Clear Active Bit 609" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE608 ,Set/Clear Active Bit 608" "Not active,Active" else hgroup.long 0x034C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0350++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE671 ,Set/Clear Active Bit 671" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE670 ,Set/Clear Active Bit 670" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE669 ,Set/Clear Active Bit 669" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE668 ,Set/Clear Active Bit 668" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE667 ,Set/Clear Active Bit 667" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE666 ,Set/Clear Active Bit 666" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE665 ,Set/Clear Active Bit 665" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE664 ,Set/Clear Active Bit 664" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE663 ,Set/Clear Active Bit 663" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE662 ,Set/Clear Active Bit 662" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE661 ,Set/Clear Active Bit 661" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE660 ,Set/Clear Active Bit 660" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE659 ,Set/Clear Active Bit 659" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE658 ,Set/Clear Active Bit 658" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE657 ,Set/Clear Active Bit 657" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE656 ,Set/Clear Active Bit 656" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE655 ,Set/Clear Active Bit 655" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE654 ,Set/Clear Active Bit 654" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE653 ,Set/Clear Active Bit 653" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE652 ,Set/Clear Active Bit 652" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE651 ,Set/Clear Active Bit 651" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE650 ,Set/Clear Active Bit 650" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE649 ,Set/Clear Active Bit 649" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE648 ,Set/Clear Active Bit 648" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE647 ,Set/Clear Active Bit 647" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE646 ,Set/Clear Active Bit 646" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE645 ,Set/Clear Active Bit 645" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE644 ,Set/Clear Active Bit 644" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE643 ,Set/Clear Active Bit 643" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE642 ,Set/Clear Active Bit 642" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE641 ,Set/Clear Active Bit 641" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE640 ,Set/Clear Active Bit 640" "Not active,Active" else hgroup.long 0x0350++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0354++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE703 ,Set/Clear Active Bit 703" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE702 ,Set/Clear Active Bit 702" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE701 ,Set/Clear Active Bit 701" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE700 ,Set/Clear Active Bit 700" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE699 ,Set/Clear Active Bit 699" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE698 ,Set/Clear Active Bit 698" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE697 ,Set/Clear Active Bit 697" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE696 ,Set/Clear Active Bit 696" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE695 ,Set/Clear Active Bit 695" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE694 ,Set/Clear Active Bit 694" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE693 ,Set/Clear Active Bit 693" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE692 ,Set/Clear Active Bit 692" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE691 ,Set/Clear Active Bit 691" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE690 ,Set/Clear Active Bit 690" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE689 ,Set/Clear Active Bit 689" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE688 ,Set/Clear Active Bit 688" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE687 ,Set/Clear Active Bit 687" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE686 ,Set/Clear Active Bit 686" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE685 ,Set/Clear Active Bit 685" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE684 ,Set/Clear Active Bit 684" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE683 ,Set/Clear Active Bit 683" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE682 ,Set/Clear Active Bit 682" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE681 ,Set/Clear Active Bit 681" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE680 ,Set/Clear Active Bit 680" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE679 ,Set/Clear Active Bit 679" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE678 ,Set/Clear Active Bit 678" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE677 ,Set/Clear Active Bit 677" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE676 ,Set/Clear Active Bit 676" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE675 ,Set/Clear Active Bit 675" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE674 ,Set/Clear Active Bit 674" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE673 ,Set/Clear Active Bit 673" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE672 ,Set/Clear Active Bit 672" "Not active,Active" else hgroup.long 0x0354++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0358++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE735 ,Set/Clear Active Bit 735" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE734 ,Set/Clear Active Bit 734" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE733 ,Set/Clear Active Bit 733" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE732 ,Set/Clear Active Bit 732" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE731 ,Set/Clear Active Bit 731" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE730 ,Set/Clear Active Bit 730" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE729 ,Set/Clear Active Bit 729" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE728 ,Set/Clear Active Bit 728" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE727 ,Set/Clear Active Bit 727" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE726 ,Set/Clear Active Bit 726" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE725 ,Set/Clear Active Bit 725" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE724 ,Set/Clear Active Bit 724" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE723 ,Set/Clear Active Bit 723" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE722 ,Set/Clear Active Bit 722" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE721 ,Set/Clear Active Bit 721" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE720 ,Set/Clear Active Bit 720" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE719 ,Set/Clear Active Bit 719" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE718 ,Set/Clear Active Bit 718" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE717 ,Set/Clear Active Bit 717" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE716 ,Set/Clear Active Bit 716" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE715 ,Set/Clear Active Bit 715" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE714 ,Set/Clear Active Bit 714" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE713 ,Set/Clear Active Bit 713" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE712 ,Set/Clear Active Bit 712" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE711 ,Set/Clear Active Bit 711" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE710 ,Set/Clear Active Bit 710" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE709 ,Set/Clear Active Bit 709" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE708 ,Set/Clear Active Bit 708" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE707 ,Set/Clear Active Bit 707" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE706 ,Set/Clear Active Bit 706" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE705 ,Set/Clear Active Bit 705" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE704 ,Set/Clear Active Bit 704" "Not active,Active" else hgroup.long 0x0358++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x035C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE767 ,Set/Clear Active Bit 767" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE766 ,Set/Clear Active Bit 766" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE765 ,Set/Clear Active Bit 765" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE764 ,Set/Clear Active Bit 764" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE763 ,Set/Clear Active Bit 763" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE762 ,Set/Clear Active Bit 762" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE761 ,Set/Clear Active Bit 761" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE760 ,Set/Clear Active Bit 760" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE759 ,Set/Clear Active Bit 759" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE758 ,Set/Clear Active Bit 758" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE757 ,Set/Clear Active Bit 757" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE756 ,Set/Clear Active Bit 756" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE755 ,Set/Clear Active Bit 755" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE754 ,Set/Clear Active Bit 754" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE753 ,Set/Clear Active Bit 753" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE752 ,Set/Clear Active Bit 752" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE751 ,Set/Clear Active Bit 751" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE750 ,Set/Clear Active Bit 750" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE749 ,Set/Clear Active Bit 749" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE748 ,Set/Clear Active Bit 748" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE747 ,Set/Clear Active Bit 747" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE746 ,Set/Clear Active Bit 746" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE745 ,Set/Clear Active Bit 745" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE744 ,Set/Clear Active Bit 744" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE743 ,Set/Clear Active Bit 743" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE742 ,Set/Clear Active Bit 742" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE741 ,Set/Clear Active Bit 741" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE740 ,Set/Clear Active Bit 740" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE739 ,Set/Clear Active Bit 739" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE738 ,Set/Clear Active Bit 738" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE737 ,Set/Clear Active Bit 737" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE736 ,Set/Clear Active Bit 736" "Not active,Active" else hgroup.long 0x035C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0360++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE799 ,Set/Clear Active Bit 799" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE798 ,Set/Clear Active Bit 798" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE797 ,Set/Clear Active Bit 797" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE796 ,Set/Clear Active Bit 796" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE795 ,Set/Clear Active Bit 795" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE794 ,Set/Clear Active Bit 794" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE793 ,Set/Clear Active Bit 793" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE792 ,Set/Clear Active Bit 792" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE791 ,Set/Clear Active Bit 791" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE790 ,Set/Clear Active Bit 790" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE789 ,Set/Clear Active Bit 789" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE788 ,Set/Clear Active Bit 788" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE787 ,Set/Clear Active Bit 787" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE786 ,Set/Clear Active Bit 786" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE785 ,Set/Clear Active Bit 785" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE784 ,Set/Clear Active Bit 784" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE783 ,Set/Clear Active Bit 783" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE782 ,Set/Clear Active Bit 782" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE781 ,Set/Clear Active Bit 781" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE780 ,Set/Clear Active Bit 780" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE779 ,Set/Clear Active Bit 779" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE778 ,Set/Clear Active Bit 778" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE777 ,Set/Clear Active Bit 777" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE776 ,Set/Clear Active Bit 776" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE775 ,Set/Clear Active Bit 775" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE774 ,Set/Clear Active Bit 774" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE773 ,Set/Clear Active Bit 773" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE772 ,Set/Clear Active Bit 772" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE771 ,Set/Clear Active Bit 771" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE770 ,Set/Clear Active Bit 770" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE769 ,Set/Clear Active Bit 769" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE768 ,Set/Clear Active Bit 768" "Not active,Active" else hgroup.long 0x0360++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0364++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE831 ,Set/Clear Active Bit 831" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE830 ,Set/Clear Active Bit 830" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE829 ,Set/Clear Active Bit 829" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE828 ,Set/Clear Active Bit 828" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE827 ,Set/Clear Active Bit 827" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE826 ,Set/Clear Active Bit 826" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE825 ,Set/Clear Active Bit 825" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE824 ,Set/Clear Active Bit 824" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE823 ,Set/Clear Active Bit 823" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE822 ,Set/Clear Active Bit 822" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE821 ,Set/Clear Active Bit 821" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE820 ,Set/Clear Active Bit 820" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE819 ,Set/Clear Active Bit 819" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE818 ,Set/Clear Active Bit 818" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE817 ,Set/Clear Active Bit 817" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE816 ,Set/Clear Active Bit 816" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE815 ,Set/Clear Active Bit 815" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE814 ,Set/Clear Active Bit 814" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE813 ,Set/Clear Active Bit 813" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE812 ,Set/Clear Active Bit 812" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE811 ,Set/Clear Active Bit 811" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE810 ,Set/Clear Active Bit 810" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE809 ,Set/Clear Active Bit 809" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE808 ,Set/Clear Active Bit 808" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE807 ,Set/Clear Active Bit 807" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE806 ,Set/Clear Active Bit 806" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE805 ,Set/Clear Active Bit 805" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE804 ,Set/Clear Active Bit 804" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE803 ,Set/Clear Active Bit 803" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE802 ,Set/Clear Active Bit 802" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE801 ,Set/Clear Active Bit 801" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE800 ,Set/Clear Active Bit 800" "Not active,Active" else hgroup.long 0x0364++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0368++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE863 ,Set/Clear Active Bit 863" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE862 ,Set/Clear Active Bit 862" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE861 ,Set/Clear Active Bit 861" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE860 ,Set/Clear Active Bit 860" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE859 ,Set/Clear Active Bit 859" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE858 ,Set/Clear Active Bit 858" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE857 ,Set/Clear Active Bit 857" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE856 ,Set/Clear Active Bit 856" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE855 ,Set/Clear Active Bit 855" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE854 ,Set/Clear Active Bit 854" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE853 ,Set/Clear Active Bit 853" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE852 ,Set/Clear Active Bit 852" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE851 ,Set/Clear Active Bit 851" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE850 ,Set/Clear Active Bit 850" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE849 ,Set/Clear Active Bit 849" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE848 ,Set/Clear Active Bit 848" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE847 ,Set/Clear Active Bit 847" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE846 ,Set/Clear Active Bit 846" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE845 ,Set/Clear Active Bit 845" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE844 ,Set/Clear Active Bit 844" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE843 ,Set/Clear Active Bit 843" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE842 ,Set/Clear Active Bit 842" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE841 ,Set/Clear Active Bit 841" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE840 ,Set/Clear Active Bit 840" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE839 ,Set/Clear Active Bit 839" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE838 ,Set/Clear Active Bit 838" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE837 ,Set/Clear Active Bit 837" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE836 ,Set/Clear Active Bit 836" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE835 ,Set/Clear Active Bit 835" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE834 ,Set/Clear Active Bit 834" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE833 ,Set/Clear Active Bit 833" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE832 ,Set/Clear Active Bit 832" "Not active,Active" else hgroup.long 0x0368++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x036C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE895 ,Set/Clear Active Bit 895" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE894 ,Set/Clear Active Bit 894" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE893 ,Set/Clear Active Bit 893" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE892 ,Set/Clear Active Bit 892" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE891 ,Set/Clear Active Bit 891" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE890 ,Set/Clear Active Bit 890" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE889 ,Set/Clear Active Bit 889" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE888 ,Set/Clear Active Bit 888" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE887 ,Set/Clear Active Bit 887" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE886 ,Set/Clear Active Bit 886" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE885 ,Set/Clear Active Bit 885" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE884 ,Set/Clear Active Bit 884" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE883 ,Set/Clear Active Bit 883" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE882 ,Set/Clear Active Bit 882" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE881 ,Set/Clear Active Bit 881" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE880 ,Set/Clear Active Bit 880" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE879 ,Set/Clear Active Bit 879" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE878 ,Set/Clear Active Bit 878" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE877 ,Set/Clear Active Bit 877" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE876 ,Set/Clear Active Bit 876" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE875 ,Set/Clear Active Bit 875" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE874 ,Set/Clear Active Bit 874" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE873 ,Set/Clear Active Bit 873" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE872 ,Set/Clear Active Bit 872" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE871 ,Set/Clear Active Bit 871" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE870 ,Set/Clear Active Bit 870" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE869 ,Set/Clear Active Bit 869" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE868 ,Set/Clear Active Bit 868" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE867 ,Set/Clear Active Bit 867" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE866 ,Set/Clear Active Bit 866" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE865 ,Set/Clear Active Bit 865" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE864 ,Set/Clear Active Bit 864" "Not active,Active" else hgroup.long 0x036C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0370++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE927 ,Set/Clear Active Bit 927" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE926 ,Set/Clear Active Bit 926" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE925 ,Set/Clear Active Bit 925" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE924 ,Set/Clear Active Bit 924" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE923 ,Set/Clear Active Bit 923" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE922 ,Set/Clear Active Bit 922" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE921 ,Set/Clear Active Bit 921" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE920 ,Set/Clear Active Bit 920" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE919 ,Set/Clear Active Bit 919" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE918 ,Set/Clear Active Bit 918" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE917 ,Set/Clear Active Bit 917" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE916 ,Set/Clear Active Bit 916" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE915 ,Set/Clear Active Bit 915" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE914 ,Set/Clear Active Bit 914" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE913 ,Set/Clear Active Bit 913" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE912 ,Set/Clear Active Bit 912" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE911 ,Set/Clear Active Bit 911" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE910 ,Set/Clear Active Bit 910" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE909 ,Set/Clear Active Bit 909" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE908 ,Set/Clear Active Bit 908" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE907 ,Set/Clear Active Bit 907" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE906 ,Set/Clear Active Bit 906" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE905 ,Set/Clear Active Bit 905" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE904 ,Set/Clear Active Bit 904" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE903 ,Set/Clear Active Bit 903" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE902 ,Set/Clear Active Bit 902" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE901 ,Set/Clear Active Bit 901" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE900 ,Set/Clear Active Bit 900" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE899 ,Set/Clear Active Bit 899" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE898 ,Set/Clear Active Bit 898" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE897 ,Set/Clear Active Bit 897" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE896 ,Set/Clear Active Bit 896" "Not active,Active" else hgroup.long 0x0370++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0374++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE959 ,Set/Clear Active Bit 959" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE958 ,Set/Clear Active Bit 958" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE957 ,Set/Clear Active Bit 957" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE956 ,Set/Clear Active Bit 956" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE955 ,Set/Clear Active Bit 955" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE954 ,Set/Clear Active Bit 954" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE953 ,Set/Clear Active Bit 953" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE952 ,Set/Clear Active Bit 952" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE951 ,Set/Clear Active Bit 951" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE950 ,Set/Clear Active Bit 950" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE949 ,Set/Clear Active Bit 949" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE948 ,Set/Clear Active Bit 948" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE947 ,Set/Clear Active Bit 947" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE946 ,Set/Clear Active Bit 946" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE945 ,Set/Clear Active Bit 945" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE944 ,Set/Clear Active Bit 944" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE943 ,Set/Clear Active Bit 943" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE942 ,Set/Clear Active Bit 942" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE941 ,Set/Clear Active Bit 941" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE940 ,Set/Clear Active Bit 940" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE939 ,Set/Clear Active Bit 939" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE938 ,Set/Clear Active Bit 938" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE937 ,Set/Clear Active Bit 937" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE936 ,Set/Clear Active Bit 936" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE935 ,Set/Clear Active Bit 935" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE934 ,Set/Clear Active Bit 934" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE933 ,Set/Clear Active Bit 933" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE932 ,Set/Clear Active Bit 932" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE931 ,Set/Clear Active Bit 931" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE930 ,Set/Clear Active Bit 930" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE929 ,Set/Clear Active Bit 929" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE928 ,Set/Clear Active Bit 928" "Not active,Active" else hgroup.long 0x0374++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0378++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE991 ,Set/Clear Active Bit 991" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE990 ,Set/Clear Active Bit 990" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE989 ,Set/Clear Active Bit 989" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE988 ,Set/Clear Active Bit 988" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE987 ,Set/Clear Active Bit 987" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE986 ,Set/Clear Active Bit 986" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE985 ,Set/Clear Active Bit 985" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE984 ,Set/Clear Active Bit 984" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE983 ,Set/Clear Active Bit 983" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE982 ,Set/Clear Active Bit 982" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE981 ,Set/Clear Active Bit 981" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE980 ,Set/Clear Active Bit 980" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE979 ,Set/Clear Active Bit 979" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE978 ,Set/Clear Active Bit 978" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE977 ,Set/Clear Active Bit 977" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE976 ,Set/Clear Active Bit 976" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE975 ,Set/Clear Active Bit 975" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE974 ,Set/Clear Active Bit 974" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE973 ,Set/Clear Active Bit 973" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE972 ,Set/Clear Active Bit 972" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE971 ,Set/Clear Active Bit 971" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE970 ,Set/Clear Active Bit 970" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE969 ,Set/Clear Active Bit 969" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE968 ,Set/Clear Active Bit 968" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE967 ,Set/Clear Active Bit 967" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE966 ,Set/Clear Active Bit 966" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE965 ,Set/Clear Active Bit 965" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE964 ,Set/Clear Active Bit 964" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE963 ,Set/Clear Active Bit 963" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE962 ,Set/Clear Active Bit 962" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE961 ,Set/Clear Active Bit 961" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE960 ,Set/Clear Active Bit 960" "Not active,Active" else hgroup.long 0x0378++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" endif tree.end width 20. tree "Priority Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x400++0x03 hide.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0" hgroup.long 0x404++0x03 hide.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1" hgroup.long 0x408++0x03 hide.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2" hgroup.long 0x40C++0x03 hide.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3" hgroup.long 0x410++0x03 hide.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4" hgroup.long 0x414++0x03 hide.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5" hgroup.long 0x418++0x03 hide.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6" hgroup.long 0x41C++0x03 hide.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7" else group.long 0x400++0x03 line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x404++0x03 line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x408++0x03 line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x40C++0x03 line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x410++0x03 line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x414++0x03 line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x418++0x03 line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x41C++0x03 line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hexmask.long.byte 0x00 24.--31. 1. " INTID35 ,Interrupt ID35 Priority/Priority Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " INTID34 ,Interrupt ID34 Priority/Priority Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " INTID33 ,Interrupt ID33 Priority/Priority Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " INTID32 ,Interrupt ID32 Priority/Priority Byte Offset 32 " group.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hexmask.long.byte 0x00 24.--31. 1. " INTID39 ,Interrupt ID39 Priority/Priority Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " INTID38 ,Interrupt ID38 Priority/Priority Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " INTID37 ,Interrupt ID37 Priority/Priority Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " INTID36 ,Interrupt ID36 Priority/Priority Byte Offset 36 " group.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hexmask.long.byte 0x00 24.--31. 1. " INTID43 ,Interrupt ID43 Priority/Priority Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " INTID42 ,Interrupt ID42 Priority/Priority Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " INTID41 ,Interrupt ID41 Priority/Priority Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " INTID40 ,Interrupt ID40 Priority/Priority Byte Offset 40 " group.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hexmask.long.byte 0x00 24.--31. 1. " INTID47 ,Interrupt ID47 Priority/Priority Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " INTID46 ,Interrupt ID46 Priority/Priority Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " INTID45 ,Interrupt ID45 Priority/Priority Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " INTID44 ,Interrupt ID44 Priority/Priority Byte Offset 44 " group.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hexmask.long.byte 0x00 24.--31. 1. " INTID51 ,Interrupt ID51 Priority/Priority Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " INTID50 ,Interrupt ID50 Priority/Priority Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " INTID49 ,Interrupt ID49 Priority/Priority Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " INTID48 ,Interrupt ID48 Priority/Priority Byte Offset 48 " group.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hexmask.long.byte 0x00 24.--31. 1. " INTID55 ,Interrupt ID55 Priority/Priority Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " INTID54 ,Interrupt ID54 Priority/Priority Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " INTID53 ,Interrupt ID53 Priority/Priority Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " INTID52 ,Interrupt ID52 Priority/Priority Byte Offset 52 " group.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hexmask.long.byte 0x00 24.--31. 1. " INTID59 ,Interrupt ID59 Priority/Priority Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " INTID58 ,Interrupt ID58 Priority/Priority Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " INTID57 ,Interrupt ID57 Priority/Priority Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " INTID56 ,Interrupt ID56 Priority/Priority Byte Offset 56 " group.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" hexmask.long.byte 0x00 24.--31. 1. " INTID63 ,Interrupt ID63 Priority/Priority Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " INTID62 ,Interrupt ID62 Priority/Priority Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " INTID61 ,Interrupt ID61 Priority/Priority Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " INTID60 ,Interrupt ID60 Priority/Priority Byte Offset 60 " else hgroup.long 0x420++0x03 hide.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hgroup.long 0x424++0x03 hide.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hgroup.long 0x428++0x03 hide.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hgroup.long 0x42C++0x03 hide.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hgroup.long 0x430++0x03 hide.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hgroup.long 0x434++0x03 hide.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hgroup.long 0x438++0x03 hide.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hgroup.long 0x43C++0x03 hide.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hexmask.long.byte 0x00 24.--31. 1. " INTID67 ,Interrupt ID67 Priority/Priority Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " INTID66 ,Interrupt ID66 Priority/Priority Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " INTID65 ,Interrupt ID65 Priority/Priority Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " INTID64 ,Interrupt ID64 Priority/Priority Byte Offset 64 " group.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hexmask.long.byte 0x00 24.--31. 1. " INTID71 ,Interrupt ID71 Priority/Priority Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " INTID70 ,Interrupt ID70 Priority/Priority Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " INTID69 ,Interrupt ID69 Priority/Priority Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " INTID68 ,Interrupt ID68 Priority/Priority Byte Offset 68 " group.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hexmask.long.byte 0x00 24.--31. 1. " INTID75 ,Interrupt ID75 Priority/Priority Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " INTID74 ,Interrupt ID74 Priority/Priority Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " INTID73 ,Interrupt ID73 Priority/Priority Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " INTID72 ,Interrupt ID72 Priority/Priority Byte Offset 72 " group.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hexmask.long.byte 0x00 24.--31. 1. " INTID79 ,Interrupt ID79 Priority/Priority Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " INTID78 ,Interrupt ID78 Priority/Priority Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " INTID77 ,Interrupt ID77 Priority/Priority Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " INTID76 ,Interrupt ID76 Priority/Priority Byte Offset 76 " group.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hexmask.long.byte 0x00 24.--31. 1. " INTID83 ,Interrupt ID83 Priority/Priority Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " INTID82 ,Interrupt ID82 Priority/Priority Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " INTID81 ,Interrupt ID81 Priority/Priority Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " INTID80 ,Interrupt ID80 Priority/Priority Byte Offset 80 " group.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hexmask.long.byte 0x00 24.--31. 1. " INTID87 ,Interrupt ID87 Priority/Priority Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " INTID86 ,Interrupt ID86 Priority/Priority Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " INTID85 ,Interrupt ID85 Priority/Priority Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " INTID84 ,Interrupt ID84 Priority/Priority Byte Offset 84 " group.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hexmask.long.byte 0x00 24.--31. 1. " INTID91 ,Interrupt ID91 Priority/Priority Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " INTID90 ,Interrupt ID90 Priority/Priority Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " INTID89 ,Interrupt ID89 Priority/Priority Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " INTID88 ,Interrupt ID88 Priority/Priority Byte Offset 88 " group.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" hexmask.long.byte 0x00 24.--31. 1. " INTID95 ,Interrupt ID95 Priority/Priority Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " INTID94 ,Interrupt ID94 Priority/Priority Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " INTID93 ,Interrupt ID93 Priority/Priority Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " INTID92 ,Interrupt ID92 Priority/Priority Byte Offset 92 " else hgroup.long 0x440++0x03 hide.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hgroup.long 0x444++0x03 hide.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hgroup.long 0x448++0x03 hide.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hgroup.long 0x44C++0x03 hide.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hgroup.long 0x450++0x03 hide.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hgroup.long 0x454++0x03 hide.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hgroup.long 0x458++0x03 hide.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hgroup.long 0x45C++0x03 hide.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hexmask.long.byte 0x00 24.--31. 1. " INTID99 ,Interrupt ID99 Priority/Priority Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " INTID98 ,Interrupt ID98 Priority/Priority Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " INTID97 ,Interrupt ID97 Priority/Priority Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " INTID96 ,Interrupt ID96 Priority/Priority Byte Offset 96 " group.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hexmask.long.byte 0x00 24.--31. 1. " INTID103 ,Interrupt ID103 Priority/Priority Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " INTID102 ,Interrupt ID102 Priority/Priority Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " INTID101 ,Interrupt ID101 Priority/Priority Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " INTID100 ,Interrupt ID100 Priority/Priority Byte Offset 100 " group.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hexmask.long.byte 0x00 24.--31. 1. " INTID107 ,Interrupt ID107 Priority/Priority Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " INTID106 ,Interrupt ID106 Priority/Priority Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " INTID105 ,Interrupt ID105 Priority/Priority Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " INTID104 ,Interrupt ID104 Priority/Priority Byte Offset 104 " group.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hexmask.long.byte 0x00 24.--31. 1. " INTID111 ,Interrupt ID111 Priority/Priority Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " INTID110 ,Interrupt ID110 Priority/Priority Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " INTID109 ,Interrupt ID109 Priority/Priority Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " INTID108 ,Interrupt ID108 Priority/Priority Byte Offset 108 " group.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hexmask.long.byte 0x00 24.--31. 1. " INTID115 ,Interrupt ID115 Priority/Priority Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " INTID114 ,Interrupt ID114 Priority/Priority Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " INTID113 ,Interrupt ID113 Priority/Priority Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " INTID112 ,Interrupt ID112 Priority/Priority Byte Offset 112 " group.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hexmask.long.byte 0x00 24.--31. 1. " INTID119 ,Interrupt ID119 Priority/Priority Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " INTID118 ,Interrupt ID118 Priority/Priority Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " INTID117 ,Interrupt ID117 Priority/Priority Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " INTID116 ,Interrupt ID116 Priority/Priority Byte Offset 116 " group.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hexmask.long.byte 0x00 24.--31. 1. " INTID123 ,Interrupt ID123 Priority/Priority Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " INTID122 ,Interrupt ID122 Priority/Priority Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " INTID121 ,Interrupt ID121 Priority/Priority Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " INTID120 ,Interrupt ID120 Priority/Priority Byte Offset 120 " group.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" hexmask.long.byte 0x00 24.--31. 1. " INTID127 ,Interrupt ID127 Priority/Priority Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " INTID126 ,Interrupt ID126 Priority/Priority Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " INTID125 ,Interrupt ID125 Priority/Priority Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " INTID124 ,Interrupt ID124 Priority/Priority Byte Offset 124 " else hgroup.long 0x460++0x03 hide.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hgroup.long 0x464++0x03 hide.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hgroup.long 0x468++0x03 hide.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hgroup.long 0x46C++0x03 hide.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hgroup.long 0x470++0x03 hide.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hgroup.long 0x474++0x03 hide.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hgroup.long 0x478++0x03 hide.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hgroup.long 0x47C++0x03 hide.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hexmask.long.byte 0x00 24.--31. 1. " INTID131 ,Interrupt ID131 Priority/Priority Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " INTID130 ,Interrupt ID130 Priority/Priority Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " INTID129 ,Interrupt ID129 Priority/Priority Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " INTID128 ,Interrupt ID128 Priority/Priority Byte Offset 128 " group.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hexmask.long.byte 0x00 24.--31. 1. " INTID135 ,Interrupt ID135 Priority/Priority Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " INTID134 ,Interrupt ID134 Priority/Priority Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " INTID133 ,Interrupt ID133 Priority/Priority Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " INTID132 ,Interrupt ID132 Priority/Priority Byte Offset 132 " group.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hexmask.long.byte 0x00 24.--31. 1. " INTID139 ,Interrupt ID139 Priority/Priority Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " INTID138 ,Interrupt ID138 Priority/Priority Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " INTID137 ,Interrupt ID137 Priority/Priority Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " INTID136 ,Interrupt ID136 Priority/Priority Byte Offset 136 " group.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hexmask.long.byte 0x00 24.--31. 1. " INTID143 ,Interrupt ID143 Priority/Priority Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " INTID142 ,Interrupt ID142 Priority/Priority Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " INTID141 ,Interrupt ID141 Priority/Priority Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " INTID140 ,Interrupt ID140 Priority/Priority Byte Offset 140 " group.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hexmask.long.byte 0x00 24.--31. 1. " INTID147 ,Interrupt ID147 Priority/Priority Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " INTID146 ,Interrupt ID146 Priority/Priority Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " INTID145 ,Interrupt ID145 Priority/Priority Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " INTID144 ,Interrupt ID144 Priority/Priority Byte Offset 144 " group.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hexmask.long.byte 0x00 24.--31. 1. " INTID151 ,Interrupt ID151 Priority/Priority Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " INTID150 ,Interrupt ID150 Priority/Priority Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " INTID149 ,Interrupt ID149 Priority/Priority Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " INTID148 ,Interrupt ID148 Priority/Priority Byte Offset 148 " group.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hexmask.long.byte 0x00 24.--31. 1. " INTID155 ,Interrupt ID155 Priority/Priority Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " INTID154 ,Interrupt ID154 Priority/Priority Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " INTID153 ,Interrupt ID153 Priority/Priority Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " INTID152 ,Interrupt ID152 Priority/Priority Byte Offset 152 " group.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" hexmask.long.byte 0x00 24.--31. 1. " INTID159 ,Interrupt ID159 Priority/Priority Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " INTID158 ,Interrupt ID158 Priority/Priority Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " INTID157 ,Interrupt ID157 Priority/Priority Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " INTID156 ,Interrupt ID156 Priority/Priority Byte Offset 156 " else hgroup.long 0x480++0x03 hide.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hgroup.long 0x484++0x03 hide.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hgroup.long 0x488++0x03 hide.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hgroup.long 0x48C++0x03 hide.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hgroup.long 0x490++0x03 hide.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hgroup.long 0x494++0x03 hide.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hgroup.long 0x498++0x03 hide.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hgroup.long 0x49C++0x03 hide.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hexmask.long.byte 0x00 24.--31. 1. " INTID163 ,Interrupt ID163 Priority/Priority Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " INTID162 ,Interrupt ID162 Priority/Priority Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " INTID161 ,Interrupt ID161 Priority/Priority Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " INTID160 ,Interrupt ID160 Priority/Priority Byte Offset 160 " group.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hexmask.long.byte 0x00 24.--31. 1. " INTID167 ,Interrupt ID167 Priority/Priority Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " INTID166 ,Interrupt ID166 Priority/Priority Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " INTID165 ,Interrupt ID165 Priority/Priority Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " INTID164 ,Interrupt ID164 Priority/Priority Byte Offset 164 " group.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hexmask.long.byte 0x00 24.--31. 1. " INTID171 ,Interrupt ID171 Priority/Priority Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " INTID170 ,Interrupt ID170 Priority/Priority Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " INTID169 ,Interrupt ID169 Priority/Priority Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " INTID168 ,Interrupt ID168 Priority/Priority Byte Offset 168 " group.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hexmask.long.byte 0x00 24.--31. 1. " INTID175 ,Interrupt ID175 Priority/Priority Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " INTID174 ,Interrupt ID174 Priority/Priority Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " INTID173 ,Interrupt ID173 Priority/Priority Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " INTID172 ,Interrupt ID172 Priority/Priority Byte Offset 172 " group.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hexmask.long.byte 0x00 24.--31. 1. " INTID179 ,Interrupt ID179 Priority/Priority Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " INTID178 ,Interrupt ID178 Priority/Priority Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " INTID177 ,Interrupt ID177 Priority/Priority Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " INTID176 ,Interrupt ID176 Priority/Priority Byte Offset 176 " group.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hexmask.long.byte 0x00 24.--31. 1. " INTID183 ,Interrupt ID183 Priority/Priority Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " INTID182 ,Interrupt ID182 Priority/Priority Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " INTID181 ,Interrupt ID181 Priority/Priority Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " INTID180 ,Interrupt ID180 Priority/Priority Byte Offset 180 " group.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hexmask.long.byte 0x00 24.--31. 1. " INTID187 ,Interrupt ID187 Priority/Priority Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " INTID186 ,Interrupt ID186 Priority/Priority Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " INTID185 ,Interrupt ID185 Priority/Priority Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " INTID184 ,Interrupt ID184 Priority/Priority Byte Offset 184 " group.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" hexmask.long.byte 0x00 24.--31. 1. " INTID191 ,Interrupt ID191 Priority/Priority Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " INTID190 ,Interrupt ID190 Priority/Priority Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " INTID189 ,Interrupt ID189 Priority/Priority Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " INTID188 ,Interrupt ID188 Priority/Priority Byte Offset 188 " else hgroup.long 0x4A0++0x03 hide.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hgroup.long 0x4A4++0x03 hide.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hgroup.long 0x4A8++0x03 hide.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hgroup.long 0x4AC++0x03 hide.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hgroup.long 0x4B0++0x03 hide.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hgroup.long 0x4B4++0x03 hide.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hgroup.long 0x4B8++0x03 hide.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hgroup.long 0x4BC++0x03 hide.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hexmask.long.byte 0x00 24.--31. 1. " INTID195 ,Interrupt ID195 Priority/Priority Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " INTID194 ,Interrupt ID194 Priority/Priority Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " INTID193 ,Interrupt ID193 Priority/Priority Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " INTID192 ,Interrupt ID192 Priority/Priority Byte Offset 192 " group.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hexmask.long.byte 0x00 24.--31. 1. " INTID199 ,Interrupt ID199 Priority/Priority Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " INTID198 ,Interrupt ID198 Priority/Priority Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " INTID197 ,Interrupt ID197 Priority/Priority Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " INTID196 ,Interrupt ID196 Priority/Priority Byte Offset 196 " group.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hexmask.long.byte 0x00 24.--31. 1. " INTID203 ,Interrupt ID203 Priority/Priority Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " INTID202 ,Interrupt ID202 Priority/Priority Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " INTID201 ,Interrupt ID201 Priority/Priority Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " INTID200 ,Interrupt ID200 Priority/Priority Byte Offset 200 " group.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hexmask.long.byte 0x00 24.--31. 1. " INTID207 ,Interrupt ID207 Priority/Priority Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " INTID206 ,Interrupt ID206 Priority/Priority Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " INTID205 ,Interrupt ID205 Priority/Priority Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " INTID204 ,Interrupt ID204 Priority/Priority Byte Offset 204 " group.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hexmask.long.byte 0x00 24.--31. 1. " INTID211 ,Interrupt ID211 Priority/Priority Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " INTID210 ,Interrupt ID210 Priority/Priority Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " INTID209 ,Interrupt ID209 Priority/Priority Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " INTID208 ,Interrupt ID208 Priority/Priority Byte Offset 208 " group.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hexmask.long.byte 0x00 24.--31. 1. " INTID215 ,Interrupt ID215 Priority/Priority Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " INTID214 ,Interrupt ID214 Priority/Priority Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " INTID213 ,Interrupt ID213 Priority/Priority Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " INTID212 ,Interrupt ID212 Priority/Priority Byte Offset 212 " group.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hexmask.long.byte 0x00 24.--31. 1. " INTID219 ,Interrupt ID219 Priority/Priority Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " INTID218 ,Interrupt ID218 Priority/Priority Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " INTID217 ,Interrupt ID217 Priority/Priority Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " INTID216 ,Interrupt ID216 Priority/Priority Byte Offset 216 " group.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" hexmask.long.byte 0x00 24.--31. 1. " INTID223 ,Interrupt ID223 Priority/Priority Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " INTID222 ,Interrupt ID222 Priority/Priority Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " INTID221 ,Interrupt ID221 Priority/Priority Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " INTID220 ,Interrupt ID220 Priority/Priority Byte Offset 220 " else hgroup.long 0x4C0++0x03 hide.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hgroup.long 0x4C4++0x03 hide.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hgroup.long 0x4C8++0x03 hide.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hgroup.long 0x4CC++0x03 hide.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hgroup.long 0x4D0++0x03 hide.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hgroup.long 0x4D4++0x03 hide.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hgroup.long 0x4D8++0x03 hide.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hgroup.long 0x4DC++0x03 hide.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hexmask.long.byte 0x00 24.--31. 1. " INTID227 ,Interrupt ID227 Priority/Priority Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " INTID226 ,Interrupt ID226 Priority/Priority Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " INTID225 ,Interrupt ID225 Priority/Priority Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " INTID224 ,Interrupt ID224 Priority/Priority Byte Offset 224 " group.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hexmask.long.byte 0x00 24.--31. 1. " INTID231 ,Interrupt ID231 Priority/Priority Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " INTID230 ,Interrupt ID230 Priority/Priority Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " INTID229 ,Interrupt ID229 Priority/Priority Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " INTID228 ,Interrupt ID228 Priority/Priority Byte Offset 228 " group.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hexmask.long.byte 0x00 24.--31. 1. " INTID235 ,Interrupt ID235 Priority/Priority Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " INTID234 ,Interrupt ID234 Priority/Priority Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " INTID233 ,Interrupt ID233 Priority/Priority Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " INTID232 ,Interrupt ID232 Priority/Priority Byte Offset 232 " group.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hexmask.long.byte 0x00 24.--31. 1. " INTID239 ,Interrupt ID239 Priority/Priority Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " INTID238 ,Interrupt ID238 Priority/Priority Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " INTID237 ,Interrupt ID237 Priority/Priority Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " INTID236 ,Interrupt ID236 Priority/Priority Byte Offset 236 " group.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hexmask.long.byte 0x00 24.--31. 1. " INTID243 ,Interrupt ID243 Priority/Priority Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " INTID242 ,Interrupt ID242 Priority/Priority Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " INTID241 ,Interrupt ID241 Priority/Priority Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " INTID240 ,Interrupt ID240 Priority/Priority Byte Offset 240 " group.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hexmask.long.byte 0x00 24.--31. 1. " INTID247 ,Interrupt ID247 Priority/Priority Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " INTID246 ,Interrupt ID246 Priority/Priority Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " INTID245 ,Interrupt ID245 Priority/Priority Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " INTID244 ,Interrupt ID244 Priority/Priority Byte Offset 244 " group.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hexmask.long.byte 0x00 24.--31. 1. " INTID251 ,Interrupt ID251 Priority/Priority Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " INTID250 ,Interrupt ID250 Priority/Priority Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " INTID249 ,Interrupt ID249 Priority/Priority Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " INTID248 ,Interrupt ID248 Priority/Priority Byte Offset 248 " group.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" hexmask.long.byte 0x00 24.--31. 1. " INTID255 ,Interrupt ID255 Priority/Priority Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " INTID254 ,Interrupt ID254 Priority/Priority Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " INTID253 ,Interrupt ID253 Priority/Priority Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " INTID252 ,Interrupt ID252 Priority/Priority Byte Offset 252 " else hgroup.long 0x4E0++0x03 hide.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hgroup.long 0x4E4++0x03 hide.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hgroup.long 0x4E8++0x03 hide.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hgroup.long 0x4EC++0x03 hide.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hgroup.long 0x4F0++0x03 hide.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hgroup.long 0x4F4++0x03 hide.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hgroup.long 0x4F8++0x03 hide.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hgroup.long 0x4FC++0x03 hide.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hexmask.long.byte 0x00 24.--31. 1. " INTID259 ,Interrupt ID259 Priority/Priority Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " INTID258 ,Interrupt ID258 Priority/Priority Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " INTID257 ,Interrupt ID257 Priority/Priority Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " INTID256 ,Interrupt ID256 Priority/Priority Byte Offset 256 " group.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hexmask.long.byte 0x00 24.--31. 1. " INTID263 ,Interrupt ID263 Priority/Priority Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " INTID262 ,Interrupt ID262 Priority/Priority Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " INTID261 ,Interrupt ID261 Priority/Priority Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " INTID260 ,Interrupt ID260 Priority/Priority Byte Offset 260 " group.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hexmask.long.byte 0x00 24.--31. 1. " INTID267 ,Interrupt ID267 Priority/Priority Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " INTID266 ,Interrupt ID266 Priority/Priority Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " INTID265 ,Interrupt ID265 Priority/Priority Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " INTID264 ,Interrupt ID264 Priority/Priority Byte Offset 264 " group.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hexmask.long.byte 0x00 24.--31. 1. " INTID271 ,Interrupt ID271 Priority/Priority Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " INTID270 ,Interrupt ID270 Priority/Priority Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " INTID269 ,Interrupt ID269 Priority/Priority Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " INTID268 ,Interrupt ID268 Priority/Priority Byte Offset 268 " group.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hexmask.long.byte 0x00 24.--31. 1. " INTID275 ,Interrupt ID275 Priority/Priority Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " INTID274 ,Interrupt ID274 Priority/Priority Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " INTID273 ,Interrupt ID273 Priority/Priority Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " INTID272 ,Interrupt ID272 Priority/Priority Byte Offset 272 " group.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hexmask.long.byte 0x00 24.--31. 1. " INTID279 ,Interrupt ID279 Priority/Priority Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " INTID278 ,Interrupt ID278 Priority/Priority Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " INTID277 ,Interrupt ID277 Priority/Priority Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " INTID276 ,Interrupt ID276 Priority/Priority Byte Offset 276 " group.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hexmask.long.byte 0x00 24.--31. 1. " INTID283 ,Interrupt ID283 Priority/Priority Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " INTID282 ,Interrupt ID282 Priority/Priority Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " INTID281 ,Interrupt ID281 Priority/Priority Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " INTID280 ,Interrupt ID280 Priority/Priority Byte Offset 280 " group.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" hexmask.long.byte 0x00 24.--31. 1. " INTID287 ,Interrupt ID287 Priority/Priority Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " INTID286 ,Interrupt ID286 Priority/Priority Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " INTID285 ,Interrupt ID285 Priority/Priority Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " INTID284 ,Interrupt ID284 Priority/Priority Byte Offset 284 " else hgroup.long 0x500++0x03 hide.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hgroup.long 0x504++0x03 hide.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hgroup.long 0x508++0x03 hide.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hgroup.long 0x50C++0x03 hide.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hgroup.long 0x510++0x03 hide.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hgroup.long 0x514++0x03 hide.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hgroup.long 0x518++0x03 hide.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hgroup.long 0x51C++0x03 hide.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hexmask.long.byte 0x00 24.--31. 1. " INTID291 ,Interrupt ID291 Priority/Priority Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " INTID290 ,Interrupt ID290 Priority/Priority Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " INTID289 ,Interrupt ID289 Priority/Priority Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " INTID288 ,Interrupt ID288 Priority/Priority Byte Offset 288 " group.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hexmask.long.byte 0x00 24.--31. 1. " INTID295 ,Interrupt ID295 Priority/Priority Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " INTID294 ,Interrupt ID294 Priority/Priority Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " INTID293 ,Interrupt ID293 Priority/Priority Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " INTID292 ,Interrupt ID292 Priority/Priority Byte Offset 292 " group.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hexmask.long.byte 0x00 24.--31. 1. " INTID299 ,Interrupt ID299 Priority/Priority Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " INTID298 ,Interrupt ID298 Priority/Priority Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " INTID297 ,Interrupt ID297 Priority/Priority Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " INTID296 ,Interrupt ID296 Priority/Priority Byte Offset 296 " group.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hexmask.long.byte 0x00 24.--31. 1. " INTID303 ,Interrupt ID303 Priority/Priority Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " INTID302 ,Interrupt ID302 Priority/Priority Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " INTID301 ,Interrupt ID301 Priority/Priority Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " INTID300 ,Interrupt ID300 Priority/Priority Byte Offset 300 " group.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hexmask.long.byte 0x00 24.--31. 1. " INTID307 ,Interrupt ID307 Priority/Priority Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " INTID306 ,Interrupt ID306 Priority/Priority Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " INTID305 ,Interrupt ID305 Priority/Priority Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " INTID304 ,Interrupt ID304 Priority/Priority Byte Offset 304 " group.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hexmask.long.byte 0x00 24.--31. 1. " INTID311 ,Interrupt ID311 Priority/Priority Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " INTID310 ,Interrupt ID310 Priority/Priority Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " INTID309 ,Interrupt ID309 Priority/Priority Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " INTID308 ,Interrupt ID308 Priority/Priority Byte Offset 308 " group.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hexmask.long.byte 0x00 24.--31. 1. " INTID315 ,Interrupt ID315 Priority/Priority Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " INTID314 ,Interrupt ID314 Priority/Priority Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " INTID313 ,Interrupt ID313 Priority/Priority Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " INTID312 ,Interrupt ID312 Priority/Priority Byte Offset 312 " group.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" hexmask.long.byte 0x00 24.--31. 1. " INTID319 ,Interrupt ID319 Priority/Priority Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " INTID318 ,Interrupt ID318 Priority/Priority Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " INTID317 ,Interrupt ID317 Priority/Priority Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " INTID316 ,Interrupt ID316 Priority/Priority Byte Offset 316 " else hgroup.long 0x520++0x03 hide.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hgroup.long 0x524++0x03 hide.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hgroup.long 0x528++0x03 hide.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hgroup.long 0x52C++0x03 hide.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hgroup.long 0x530++0x03 hide.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hgroup.long 0x534++0x03 hide.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hgroup.long 0x538++0x03 hide.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hgroup.long 0x53C++0x03 hide.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hexmask.long.byte 0x00 24.--31. 1. " INTID323 ,Interrupt ID323 Priority/Priority Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " INTID322 ,Interrupt ID322 Priority/Priority Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " INTID321 ,Interrupt ID321 Priority/Priority Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " INTID320 ,Interrupt ID320 Priority/Priority Byte Offset 320 " group.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hexmask.long.byte 0x00 24.--31. 1. " INTID327 ,Interrupt ID327 Priority/Priority Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " INTID326 ,Interrupt ID326 Priority/Priority Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " INTID325 ,Interrupt ID325 Priority/Priority Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " INTID324 ,Interrupt ID324 Priority/Priority Byte Offset 324 " group.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hexmask.long.byte 0x00 24.--31. 1. " INTID331 ,Interrupt ID331 Priority/Priority Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " INTID330 ,Interrupt ID330 Priority/Priority Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " INTID329 ,Interrupt ID329 Priority/Priority Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " INTID328 ,Interrupt ID328 Priority/Priority Byte Offset 328 " group.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hexmask.long.byte 0x00 24.--31. 1. " INTID335 ,Interrupt ID335 Priority/Priority Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " INTID334 ,Interrupt ID334 Priority/Priority Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " INTID333 ,Interrupt ID333 Priority/Priority Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " INTID332 ,Interrupt ID332 Priority/Priority Byte Offset 332 " group.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hexmask.long.byte 0x00 24.--31. 1. " INTID339 ,Interrupt ID339 Priority/Priority Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " INTID338 ,Interrupt ID338 Priority/Priority Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " INTID337 ,Interrupt ID337 Priority/Priority Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " INTID336 ,Interrupt ID336 Priority/Priority Byte Offset 336 " group.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hexmask.long.byte 0x00 24.--31. 1. " INTID343 ,Interrupt ID343 Priority/Priority Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " INTID342 ,Interrupt ID342 Priority/Priority Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " INTID341 ,Interrupt ID341 Priority/Priority Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " INTID340 ,Interrupt ID340 Priority/Priority Byte Offset 340 " group.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hexmask.long.byte 0x00 24.--31. 1. " INTID347 ,Interrupt ID347 Priority/Priority Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " INTID346 ,Interrupt ID346 Priority/Priority Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " INTID345 ,Interrupt ID345 Priority/Priority Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " INTID344 ,Interrupt ID344 Priority/Priority Byte Offset 344 " group.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" hexmask.long.byte 0x00 24.--31. 1. " INTID351 ,Interrupt ID351 Priority/Priority Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " INTID350 ,Interrupt ID350 Priority/Priority Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " INTID349 ,Interrupt ID349 Priority/Priority Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " INTID348 ,Interrupt ID348 Priority/Priority Byte Offset 348 " else hgroup.long 0x540++0x03 hide.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hgroup.long 0x544++0x03 hide.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hgroup.long 0x548++0x03 hide.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hgroup.long 0x54C++0x03 hide.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hgroup.long 0x550++0x03 hide.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hgroup.long 0x554++0x03 hide.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hgroup.long 0x558++0x03 hide.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hgroup.long 0x55C++0x03 hide.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hexmask.long.byte 0x00 24.--31. 1. " INTID355 ,Interrupt ID355 Priority/Priority Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " INTID354 ,Interrupt ID354 Priority/Priority Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " INTID353 ,Interrupt ID353 Priority/Priority Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " INTID352 ,Interrupt ID352 Priority/Priority Byte Offset 352 " group.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hexmask.long.byte 0x00 24.--31. 1. " INTID359 ,Interrupt ID359 Priority/Priority Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " INTID358 ,Interrupt ID358 Priority/Priority Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " INTID357 ,Interrupt ID357 Priority/Priority Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " INTID356 ,Interrupt ID356 Priority/Priority Byte Offset 356 " group.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hexmask.long.byte 0x00 24.--31. 1. " INTID363 ,Interrupt ID363 Priority/Priority Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " INTID362 ,Interrupt ID362 Priority/Priority Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " INTID361 ,Interrupt ID361 Priority/Priority Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " INTID360 ,Interrupt ID360 Priority/Priority Byte Offset 360 " group.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hexmask.long.byte 0x00 24.--31. 1. " INTID367 ,Interrupt ID367 Priority/Priority Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " INTID366 ,Interrupt ID366 Priority/Priority Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " INTID365 ,Interrupt ID365 Priority/Priority Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " INTID364 ,Interrupt ID364 Priority/Priority Byte Offset 364 " group.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hexmask.long.byte 0x00 24.--31. 1. " INTID371 ,Interrupt ID371 Priority/Priority Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " INTID370 ,Interrupt ID370 Priority/Priority Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " INTID369 ,Interrupt ID369 Priority/Priority Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " INTID368 ,Interrupt ID368 Priority/Priority Byte Offset 368 " group.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hexmask.long.byte 0x00 24.--31. 1. " INTID375 ,Interrupt ID375 Priority/Priority Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " INTID374 ,Interrupt ID374 Priority/Priority Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " INTID373 ,Interrupt ID373 Priority/Priority Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " INTID372 ,Interrupt ID372 Priority/Priority Byte Offset 372 " group.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hexmask.long.byte 0x00 24.--31. 1. " INTID379 ,Interrupt ID379 Priority/Priority Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " INTID378 ,Interrupt ID378 Priority/Priority Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " INTID377 ,Interrupt ID377 Priority/Priority Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " INTID376 ,Interrupt ID376 Priority/Priority Byte Offset 376 " group.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" hexmask.long.byte 0x00 24.--31. 1. " INTID383 ,Interrupt ID383 Priority/Priority Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " INTID382 ,Interrupt ID382 Priority/Priority Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " INTID381 ,Interrupt ID381 Priority/Priority Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " INTID380 ,Interrupt ID380 Priority/Priority Byte Offset 380 " else hgroup.long 0x560++0x03 hide.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hgroup.long 0x564++0x03 hide.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hgroup.long 0x568++0x03 hide.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hgroup.long 0x56C++0x03 hide.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hgroup.long 0x570++0x03 hide.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hgroup.long 0x574++0x03 hide.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hgroup.long 0x578++0x03 hide.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hgroup.long 0x57C++0x03 hide.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hexmask.long.byte 0x00 24.--31. 1. " INTID387 ,Interrupt ID387 Priority/Priority Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " INTID386 ,Interrupt ID386 Priority/Priority Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " INTID385 ,Interrupt ID385 Priority/Priority Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " INTID384 ,Interrupt ID384 Priority/Priority Byte Offset 384 " group.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hexmask.long.byte 0x00 24.--31. 1. " INTID391 ,Interrupt ID391 Priority/Priority Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " INTID390 ,Interrupt ID390 Priority/Priority Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " INTID389 ,Interrupt ID389 Priority/Priority Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " INTID388 ,Interrupt ID388 Priority/Priority Byte Offset 388 " group.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hexmask.long.byte 0x00 24.--31. 1. " INTID395 ,Interrupt ID395 Priority/Priority Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " INTID394 ,Interrupt ID394 Priority/Priority Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " INTID393 ,Interrupt ID393 Priority/Priority Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " INTID392 ,Interrupt ID392 Priority/Priority Byte Offset 392 " group.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hexmask.long.byte 0x00 24.--31. 1. " INTID399 ,Interrupt ID399 Priority/Priority Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " INTID398 ,Interrupt ID398 Priority/Priority Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " INTID397 ,Interrupt ID397 Priority/Priority Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " INTID396 ,Interrupt ID396 Priority/Priority Byte Offset 396 " group.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hexmask.long.byte 0x00 24.--31. 1. " INTID403 ,Interrupt ID403 Priority/Priority Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " INTID402 ,Interrupt ID402 Priority/Priority Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " INTID401 ,Interrupt ID401 Priority/Priority Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " INTID400 ,Interrupt ID400 Priority/Priority Byte Offset 400 " group.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hexmask.long.byte 0x00 24.--31. 1. " INTID407 ,Interrupt ID407 Priority/Priority Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " INTID406 ,Interrupt ID406 Priority/Priority Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " INTID405 ,Interrupt ID405 Priority/Priority Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " INTID404 ,Interrupt ID404 Priority/Priority Byte Offset 404 " group.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hexmask.long.byte 0x00 24.--31. 1. " INTID411 ,Interrupt ID411 Priority/Priority Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " INTID410 ,Interrupt ID410 Priority/Priority Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " INTID409 ,Interrupt ID409 Priority/Priority Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " INTID408 ,Interrupt ID408 Priority/Priority Byte Offset 408 " group.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" hexmask.long.byte 0x00 24.--31. 1. " INTID415 ,Interrupt ID415 Priority/Priority Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " INTID414 ,Interrupt ID414 Priority/Priority Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " INTID413 ,Interrupt ID413 Priority/Priority Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " INTID412 ,Interrupt ID412 Priority/Priority Byte Offset 412 " else hgroup.long 0x580++0x03 hide.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hgroup.long 0x584++0x03 hide.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hgroup.long 0x588++0x03 hide.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hgroup.long 0x58C++0x03 hide.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hgroup.long 0x590++0x03 hide.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hgroup.long 0x594++0x03 hide.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hgroup.long 0x598++0x03 hide.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hgroup.long 0x59C++0x03 hide.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hexmask.long.byte 0x00 24.--31. 1. " INTID419 ,Interrupt ID419 Priority/Priority Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " INTID418 ,Interrupt ID418 Priority/Priority Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " INTID417 ,Interrupt ID417 Priority/Priority Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " INTID416 ,Interrupt ID416 Priority/Priority Byte Offset 416 " group.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hexmask.long.byte 0x00 24.--31. 1. " INTID423 ,Interrupt ID423 Priority/Priority Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " INTID422 ,Interrupt ID422 Priority/Priority Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " INTID421 ,Interrupt ID421 Priority/Priority Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " INTID420 ,Interrupt ID420 Priority/Priority Byte Offset 420 " group.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hexmask.long.byte 0x00 24.--31. 1. " INTID427 ,Interrupt ID427 Priority/Priority Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " INTID426 ,Interrupt ID426 Priority/Priority Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " INTID425 ,Interrupt ID425 Priority/Priority Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " INTID424 ,Interrupt ID424 Priority/Priority Byte Offset 424 " group.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hexmask.long.byte 0x00 24.--31. 1. " INTID431 ,Interrupt ID431 Priority/Priority Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " INTID430 ,Interrupt ID430 Priority/Priority Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " INTID429 ,Interrupt ID429 Priority/Priority Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " INTID428 ,Interrupt ID428 Priority/Priority Byte Offset 428 " group.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hexmask.long.byte 0x00 24.--31. 1. " INTID435 ,Interrupt ID435 Priority/Priority Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " INTID434 ,Interrupt ID434 Priority/Priority Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " INTID433 ,Interrupt ID433 Priority/Priority Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " INTID432 ,Interrupt ID432 Priority/Priority Byte Offset 432 " group.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hexmask.long.byte 0x00 24.--31. 1. " INTID439 ,Interrupt ID439 Priority/Priority Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " INTID438 ,Interrupt ID438 Priority/Priority Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " INTID437 ,Interrupt ID437 Priority/Priority Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " INTID436 ,Interrupt ID436 Priority/Priority Byte Offset 436 " group.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hexmask.long.byte 0x00 24.--31. 1. " INTID443 ,Interrupt ID443 Priority/Priority Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " INTID442 ,Interrupt ID442 Priority/Priority Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " INTID441 ,Interrupt ID441 Priority/Priority Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " INTID440 ,Interrupt ID440 Priority/Priority Byte Offset 440 " group.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" hexmask.long.byte 0x00 24.--31. 1. " INTID447 ,Interrupt ID447 Priority/Priority Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " INTID446 ,Interrupt ID446 Priority/Priority Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " INTID445 ,Interrupt ID445 Priority/Priority Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " INTID444 ,Interrupt ID444 Priority/Priority Byte Offset 444 " else hgroup.long 0x5A0++0x03 hide.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hgroup.long 0x5A4++0x03 hide.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hgroup.long 0x5A8++0x03 hide.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hgroup.long 0x5AC++0x03 hide.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hgroup.long 0x5B0++0x03 hide.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hgroup.long 0x5B4++0x03 hide.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hgroup.long 0x5B8++0x03 hide.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hgroup.long 0x5BC++0x03 hide.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hexmask.long.byte 0x00 24.--31. 1. " INTID451 ,Interrupt ID451 Priority/Priority Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " INTID450 ,Interrupt ID450 Priority/Priority Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " INTID449 ,Interrupt ID449 Priority/Priority Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " INTID448 ,Interrupt ID448 Priority/Priority Byte Offset 448 " group.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hexmask.long.byte 0x00 24.--31. 1. " INTID455 ,Interrupt ID455 Priority/Priority Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " INTID454 ,Interrupt ID454 Priority/Priority Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " INTID453 ,Interrupt ID453 Priority/Priority Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " INTID452 ,Interrupt ID452 Priority/Priority Byte Offset 452 " group.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hexmask.long.byte 0x00 24.--31. 1. " INTID459 ,Interrupt ID459 Priority/Priority Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " INTID458 ,Interrupt ID458 Priority/Priority Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " INTID457 ,Interrupt ID457 Priority/Priority Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " INTID456 ,Interrupt ID456 Priority/Priority Byte Offset 456 " group.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hexmask.long.byte 0x00 24.--31. 1. " INTID463 ,Interrupt ID463 Priority/Priority Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " INTID462 ,Interrupt ID462 Priority/Priority Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " INTID461 ,Interrupt ID461 Priority/Priority Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " INTID460 ,Interrupt ID460 Priority/Priority Byte Offset 460 " group.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hexmask.long.byte 0x00 24.--31. 1. " INTID467 ,Interrupt ID467 Priority/Priority Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " INTID466 ,Interrupt ID466 Priority/Priority Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " INTID465 ,Interrupt ID465 Priority/Priority Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " INTID464 ,Interrupt ID464 Priority/Priority Byte Offset 464 " group.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hexmask.long.byte 0x00 24.--31. 1. " INTID471 ,Interrupt ID471 Priority/Priority Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " INTID470 ,Interrupt ID470 Priority/Priority Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " INTID469 ,Interrupt ID469 Priority/Priority Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " INTID468 ,Interrupt ID468 Priority/Priority Byte Offset 468 " group.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hexmask.long.byte 0x00 24.--31. 1. " INTID475 ,Interrupt ID475 Priority/Priority Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " INTID474 ,Interrupt ID474 Priority/Priority Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " INTID473 ,Interrupt ID473 Priority/Priority Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " INTID472 ,Interrupt ID472 Priority/Priority Byte Offset 472 " group.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" hexmask.long.byte 0x00 24.--31. 1. " INTID479 ,Interrupt ID479 Priority/Priority Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " INTID478 ,Interrupt ID478 Priority/Priority Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " INTID477 ,Interrupt ID477 Priority/Priority Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " INTID476 ,Interrupt ID476 Priority/Priority Byte Offset 476 " else hgroup.long 0x5C0++0x03 hide.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hgroup.long 0x5C4++0x03 hide.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hgroup.long 0x5C8++0x03 hide.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hgroup.long 0x5CC++0x03 hide.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hgroup.long 0x5D0++0x03 hide.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hgroup.long 0x5D4++0x03 hide.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hgroup.long 0x5D8++0x03 hide.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hgroup.long 0x5DC++0x03 hide.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hexmask.long.byte 0x00 24.--31. 1. " INTID483 ,Interrupt ID483 Priority/Priority Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " INTID482 ,Interrupt ID482 Priority/Priority Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " INTID481 ,Interrupt ID481 Priority/Priority Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " INTID480 ,Interrupt ID480 Priority/Priority Byte Offset 480 " group.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hexmask.long.byte 0x00 24.--31. 1. " INTID487 ,Interrupt ID487 Priority/Priority Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " INTID486 ,Interrupt ID486 Priority/Priority Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " INTID485 ,Interrupt ID485 Priority/Priority Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " INTID484 ,Interrupt ID484 Priority/Priority Byte Offset 484 " group.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hexmask.long.byte 0x00 24.--31. 1. " INTID491 ,Interrupt ID491 Priority/Priority Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " INTID490 ,Interrupt ID490 Priority/Priority Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " INTID489 ,Interrupt ID489 Priority/Priority Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " INTID488 ,Interrupt ID488 Priority/Priority Byte Offset 488 " group.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hexmask.long.byte 0x00 24.--31. 1. " INTID495 ,Interrupt ID495 Priority/Priority Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " INTID494 ,Interrupt ID494 Priority/Priority Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " INTID493 ,Interrupt ID493 Priority/Priority Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " INTID492 ,Interrupt ID492 Priority/Priority Byte Offset 492 " group.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hexmask.long.byte 0x00 24.--31. 1. " INTID499 ,Interrupt ID499 Priority/Priority Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " INTID498 ,Interrupt ID498 Priority/Priority Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " INTID497 ,Interrupt ID497 Priority/Priority Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " INTID496 ,Interrupt ID496 Priority/Priority Byte Offset 496 " group.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hexmask.long.byte 0x00 24.--31. 1. " INTID503 ,Interrupt ID503 Priority/Priority Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " INTID502 ,Interrupt ID502 Priority/Priority Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " INTID501 ,Interrupt ID501 Priority/Priority Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " INTID500 ,Interrupt ID500 Priority/Priority Byte Offset 500 " group.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hexmask.long.byte 0x00 24.--31. 1. " INTID507 ,Interrupt ID507 Priority/Priority Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " INTID506 ,Interrupt ID506 Priority/Priority Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " INTID505 ,Interrupt ID505 Priority/Priority Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " INTID504 ,Interrupt ID504 Priority/Priority Byte Offset 504 " group.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" hexmask.long.byte 0x00 24.--31. 1. " INTID511 ,Interrupt ID511 Priority/Priority Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " INTID510 ,Interrupt ID510 Priority/Priority Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " INTID509 ,Interrupt ID509 Priority/Priority Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " INTID508 ,Interrupt ID508 Priority/Priority Byte Offset 508 " else hgroup.long 0x5E0++0x03 hide.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hgroup.long 0x5E4++0x03 hide.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hgroup.long 0x5E8++0x03 hide.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hgroup.long 0x5EC++0x03 hide.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hgroup.long 0x5F0++0x03 hide.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hgroup.long 0x5F4++0x03 hide.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hgroup.long 0x5F8++0x03 hide.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hgroup.long 0x5FC++0x03 hide.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hexmask.long.byte 0x00 24.--31. 1. " INTID515 ,Interrupt ID515 Priority/Priority Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " INTID514 ,Interrupt ID514 Priority/Priority Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " INTID513 ,Interrupt ID513 Priority/Priority Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " INTID512 ,Interrupt ID512 Priority/Priority Byte Offset 512 " group.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hexmask.long.byte 0x00 24.--31. 1. " INTID519 ,Interrupt ID519 Priority/Priority Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " INTID518 ,Interrupt ID518 Priority/Priority Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " INTID517 ,Interrupt ID517 Priority/Priority Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " INTID516 ,Interrupt ID516 Priority/Priority Byte Offset 516 " group.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hexmask.long.byte 0x00 24.--31. 1. " INTID523 ,Interrupt ID523 Priority/Priority Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " INTID522 ,Interrupt ID522 Priority/Priority Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " INTID521 ,Interrupt ID521 Priority/Priority Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " INTID520 ,Interrupt ID520 Priority/Priority Byte Offset 520 " group.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hexmask.long.byte 0x00 24.--31. 1. " INTID527 ,Interrupt ID527 Priority/Priority Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " INTID526 ,Interrupt ID526 Priority/Priority Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " INTID525 ,Interrupt ID525 Priority/Priority Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " INTID524 ,Interrupt ID524 Priority/Priority Byte Offset 524 " group.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hexmask.long.byte 0x00 24.--31. 1. " INTID531 ,Interrupt ID531 Priority/Priority Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " INTID530 ,Interrupt ID530 Priority/Priority Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " INTID529 ,Interrupt ID529 Priority/Priority Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " INTID528 ,Interrupt ID528 Priority/Priority Byte Offset 528 " group.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hexmask.long.byte 0x00 24.--31. 1. " INTID535 ,Interrupt ID535 Priority/Priority Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " INTID534 ,Interrupt ID534 Priority/Priority Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " INTID533 ,Interrupt ID533 Priority/Priority Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " INTID532 ,Interrupt ID532 Priority/Priority Byte Offset 532 " group.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hexmask.long.byte 0x00 24.--31. 1. " INTID539 ,Interrupt ID539 Priority/Priority Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " INTID538 ,Interrupt ID538 Priority/Priority Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " INTID537 ,Interrupt ID537 Priority/Priority Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " INTID536 ,Interrupt ID536 Priority/Priority Byte Offset 536 " group.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" hexmask.long.byte 0x00 24.--31. 1. " INTID543 ,Interrupt ID543 Priority/Priority Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " INTID542 ,Interrupt ID542 Priority/Priority Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " INTID541 ,Interrupt ID541 Priority/Priority Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " INTID540 ,Interrupt ID540 Priority/Priority Byte Offset 540 " else hgroup.long 0x600++0x03 hide.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hgroup.long 0x604++0x03 hide.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hgroup.long 0x608++0x03 hide.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hgroup.long 0x60C++0x03 hide.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hgroup.long 0x610++0x03 hide.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hgroup.long 0x614++0x03 hide.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hgroup.long 0x618++0x03 hide.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hgroup.long 0x61C++0x03 hide.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hexmask.long.byte 0x00 24.--31. 1. " INTID547 ,Interrupt ID547 Priority/Priority Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " INTID546 ,Interrupt ID546 Priority/Priority Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " INTID545 ,Interrupt ID545 Priority/Priority Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " INTID544 ,Interrupt ID544 Priority/Priority Byte Offset 544 " group.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hexmask.long.byte 0x00 24.--31. 1. " INTID551 ,Interrupt ID551 Priority/Priority Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " INTID550 ,Interrupt ID550 Priority/Priority Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " INTID549 ,Interrupt ID549 Priority/Priority Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " INTID548 ,Interrupt ID548 Priority/Priority Byte Offset 548 " group.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hexmask.long.byte 0x00 24.--31. 1. " INTID555 ,Interrupt ID555 Priority/Priority Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " INTID554 ,Interrupt ID554 Priority/Priority Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " INTID553 ,Interrupt ID553 Priority/Priority Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " INTID552 ,Interrupt ID552 Priority/Priority Byte Offset 552 " group.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hexmask.long.byte 0x00 24.--31. 1. " INTID559 ,Interrupt ID559 Priority/Priority Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " INTID558 ,Interrupt ID558 Priority/Priority Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " INTID557 ,Interrupt ID557 Priority/Priority Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " INTID556 ,Interrupt ID556 Priority/Priority Byte Offset 556 " group.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hexmask.long.byte 0x00 24.--31. 1. " INTID563 ,Interrupt ID563 Priority/Priority Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " INTID562 ,Interrupt ID562 Priority/Priority Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " INTID561 ,Interrupt ID561 Priority/Priority Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " INTID560 ,Interrupt ID560 Priority/Priority Byte Offset 560 " group.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hexmask.long.byte 0x00 24.--31. 1. " INTID567 ,Interrupt ID567 Priority/Priority Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " INTID566 ,Interrupt ID566 Priority/Priority Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " INTID565 ,Interrupt ID565 Priority/Priority Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " INTID564 ,Interrupt ID564 Priority/Priority Byte Offset 564 " group.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hexmask.long.byte 0x00 24.--31. 1. " INTID571 ,Interrupt ID571 Priority/Priority Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " INTID570 ,Interrupt ID570 Priority/Priority Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " INTID569 ,Interrupt ID569 Priority/Priority Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " INTID568 ,Interrupt ID568 Priority/Priority Byte Offset 568 " group.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" hexmask.long.byte 0x00 24.--31. 1. " INTID575 ,Interrupt ID575 Priority/Priority Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " INTID574 ,Interrupt ID574 Priority/Priority Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " INTID573 ,Interrupt ID573 Priority/Priority Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " INTID572 ,Interrupt ID572 Priority/Priority Byte Offset 572 " else hgroup.long 0x620++0x03 hide.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hgroup.long 0x624++0x03 hide.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hgroup.long 0x628++0x03 hide.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hgroup.long 0x62C++0x03 hide.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hgroup.long 0x630++0x03 hide.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hgroup.long 0x634++0x03 hide.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hgroup.long 0x638++0x03 hide.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hgroup.long 0x63C++0x03 hide.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hexmask.long.byte 0x00 24.--31. 1. " INTID579 ,Interrupt ID579 Priority/Priority Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " INTID578 ,Interrupt ID578 Priority/Priority Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " INTID577 ,Interrupt ID577 Priority/Priority Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " INTID576 ,Interrupt ID576 Priority/Priority Byte Offset 576 " group.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hexmask.long.byte 0x00 24.--31. 1. " INTID583 ,Interrupt ID583 Priority/Priority Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " INTID582 ,Interrupt ID582 Priority/Priority Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " INTID581 ,Interrupt ID581 Priority/Priority Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " INTID580 ,Interrupt ID580 Priority/Priority Byte Offset 580 " group.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hexmask.long.byte 0x00 24.--31. 1. " INTID587 ,Interrupt ID587 Priority/Priority Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " INTID586 ,Interrupt ID586 Priority/Priority Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " INTID585 ,Interrupt ID585 Priority/Priority Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " INTID584 ,Interrupt ID584 Priority/Priority Byte Offset 584 " group.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hexmask.long.byte 0x00 24.--31. 1. " INTID591 ,Interrupt ID591 Priority/Priority Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " INTID590 ,Interrupt ID590 Priority/Priority Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " INTID589 ,Interrupt ID589 Priority/Priority Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " INTID588 ,Interrupt ID588 Priority/Priority Byte Offset 588 " group.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hexmask.long.byte 0x00 24.--31. 1. " INTID595 ,Interrupt ID595 Priority/Priority Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " INTID594 ,Interrupt ID594 Priority/Priority Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " INTID593 ,Interrupt ID593 Priority/Priority Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " INTID592 ,Interrupt ID592 Priority/Priority Byte Offset 592 " group.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hexmask.long.byte 0x00 24.--31. 1. " INTID599 ,Interrupt ID599 Priority/Priority Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " INTID598 ,Interrupt ID598 Priority/Priority Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " INTID597 ,Interrupt ID597 Priority/Priority Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " INTID596 ,Interrupt ID596 Priority/Priority Byte Offset 596 " group.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hexmask.long.byte 0x00 24.--31. 1. " INTID603 ,Interrupt ID603 Priority/Priority Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " INTID602 ,Interrupt ID602 Priority/Priority Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " INTID601 ,Interrupt ID601 Priority/Priority Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " INTID600 ,Interrupt ID600 Priority/Priority Byte Offset 600 " group.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" hexmask.long.byte 0x00 24.--31. 1. " INTID607 ,Interrupt ID607 Priority/Priority Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " INTID606 ,Interrupt ID606 Priority/Priority Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " INTID605 ,Interrupt ID605 Priority/Priority Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " INTID604 ,Interrupt ID604 Priority/Priority Byte Offset 604 " else hgroup.long 0x640++0x03 hide.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hgroup.long 0x644++0x03 hide.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hgroup.long 0x648++0x03 hide.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hgroup.long 0x64C++0x03 hide.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hgroup.long 0x650++0x03 hide.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hgroup.long 0x654++0x03 hide.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hgroup.long 0x658++0x03 hide.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hgroup.long 0x65C++0x03 hide.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hexmask.long.byte 0x00 24.--31. 1. " INTID611 ,Interrupt ID611 Priority/Priority Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " INTID610 ,Interrupt ID610 Priority/Priority Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " INTID609 ,Interrupt ID609 Priority/Priority Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " INTID608 ,Interrupt ID608 Priority/Priority Byte Offset 608 " group.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hexmask.long.byte 0x00 24.--31. 1. " INTID615 ,Interrupt ID615 Priority/Priority Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " INTID614 ,Interrupt ID614 Priority/Priority Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " INTID613 ,Interrupt ID613 Priority/Priority Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " INTID612 ,Interrupt ID612 Priority/Priority Byte Offset 612 " group.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hexmask.long.byte 0x00 24.--31. 1. " INTID619 ,Interrupt ID619 Priority/Priority Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " INTID618 ,Interrupt ID618 Priority/Priority Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " INTID617 ,Interrupt ID617 Priority/Priority Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " INTID616 ,Interrupt ID616 Priority/Priority Byte Offset 616 " group.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hexmask.long.byte 0x00 24.--31. 1. " INTID623 ,Interrupt ID623 Priority/Priority Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " INTID622 ,Interrupt ID622 Priority/Priority Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " INTID621 ,Interrupt ID621 Priority/Priority Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " INTID620 ,Interrupt ID620 Priority/Priority Byte Offset 620 " group.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hexmask.long.byte 0x00 24.--31. 1. " INTID627 ,Interrupt ID627 Priority/Priority Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " INTID626 ,Interrupt ID626 Priority/Priority Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " INTID625 ,Interrupt ID625 Priority/Priority Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " INTID624 ,Interrupt ID624 Priority/Priority Byte Offset 624 " group.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hexmask.long.byte 0x00 24.--31. 1. " INTID631 ,Interrupt ID631 Priority/Priority Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " INTID630 ,Interrupt ID630 Priority/Priority Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " INTID629 ,Interrupt ID629 Priority/Priority Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " INTID628 ,Interrupt ID628 Priority/Priority Byte Offset 628 " group.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hexmask.long.byte 0x00 24.--31. 1. " INTID635 ,Interrupt ID635 Priority/Priority Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " INTID634 ,Interrupt ID634 Priority/Priority Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " INTID633 ,Interrupt ID633 Priority/Priority Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " INTID632 ,Interrupt ID632 Priority/Priority Byte Offset 632 " group.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" hexmask.long.byte 0x00 24.--31. 1. " INTID639 ,Interrupt ID639 Priority/Priority Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " INTID638 ,Interrupt ID638 Priority/Priority Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " INTID637 ,Interrupt ID637 Priority/Priority Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " INTID636 ,Interrupt ID636 Priority/Priority Byte Offset 636 " else hgroup.long 0x660++0x03 hide.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hgroup.long 0x664++0x03 hide.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hgroup.long 0x668++0x03 hide.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hgroup.long 0x66C++0x03 hide.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hgroup.long 0x670++0x03 hide.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hgroup.long 0x674++0x03 hide.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hgroup.long 0x678++0x03 hide.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hgroup.long 0x67C++0x03 hide.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hexmask.long.byte 0x00 24.--31. 1. " INTID643 ,Interrupt ID643 Priority/Priority Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " INTID642 ,Interrupt ID642 Priority/Priority Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " INTID641 ,Interrupt ID641 Priority/Priority Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " INTID640 ,Interrupt ID640 Priority/Priority Byte Offset 640 " group.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hexmask.long.byte 0x00 24.--31. 1. " INTID647 ,Interrupt ID647 Priority/Priority Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " INTID646 ,Interrupt ID646 Priority/Priority Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " INTID645 ,Interrupt ID645 Priority/Priority Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " INTID644 ,Interrupt ID644 Priority/Priority Byte Offset 644 " group.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hexmask.long.byte 0x00 24.--31. 1. " INTID651 ,Interrupt ID651 Priority/Priority Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " INTID650 ,Interrupt ID650 Priority/Priority Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " INTID649 ,Interrupt ID649 Priority/Priority Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " INTID648 ,Interrupt ID648 Priority/Priority Byte Offset 648 " group.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hexmask.long.byte 0x00 24.--31. 1. " INTID655 ,Interrupt ID655 Priority/Priority Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " INTID654 ,Interrupt ID654 Priority/Priority Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " INTID653 ,Interrupt ID653 Priority/Priority Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " INTID652 ,Interrupt ID652 Priority/Priority Byte Offset 652 " group.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hexmask.long.byte 0x00 24.--31. 1. " INTID659 ,Interrupt ID659 Priority/Priority Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " INTID658 ,Interrupt ID658 Priority/Priority Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " INTID657 ,Interrupt ID657 Priority/Priority Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " INTID656 ,Interrupt ID656 Priority/Priority Byte Offset 656 " group.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hexmask.long.byte 0x00 24.--31. 1. " INTID663 ,Interrupt ID663 Priority/Priority Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " INTID662 ,Interrupt ID662 Priority/Priority Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " INTID661 ,Interrupt ID661 Priority/Priority Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " INTID660 ,Interrupt ID660 Priority/Priority Byte Offset 660 " group.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hexmask.long.byte 0x00 24.--31. 1. " INTID667 ,Interrupt ID667 Priority/Priority Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " INTID666 ,Interrupt ID666 Priority/Priority Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " INTID665 ,Interrupt ID665 Priority/Priority Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " INTID664 ,Interrupt ID664 Priority/Priority Byte Offset 664 " group.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" hexmask.long.byte 0x00 24.--31. 1. " INTID671 ,Interrupt ID671 Priority/Priority Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " INTID670 ,Interrupt ID670 Priority/Priority Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " INTID669 ,Interrupt ID669 Priority/Priority Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " INTID668 ,Interrupt ID668 Priority/Priority Byte Offset 668 " else hgroup.long 0x680++0x03 hide.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hgroup.long 0x684++0x03 hide.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hgroup.long 0x688++0x03 hide.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hgroup.long 0x68C++0x03 hide.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hgroup.long 0x690++0x03 hide.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hgroup.long 0x694++0x03 hide.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hgroup.long 0x698++0x03 hide.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hgroup.long 0x69C++0x03 hide.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hexmask.long.byte 0x00 24.--31. 1. " INTID675 ,Interrupt ID675 Priority/Priority Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " INTID674 ,Interrupt ID674 Priority/Priority Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " INTID673 ,Interrupt ID673 Priority/Priority Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " INTID672 ,Interrupt ID672 Priority/Priority Byte Offset 672 " group.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hexmask.long.byte 0x00 24.--31. 1. " INTID679 ,Interrupt ID679 Priority/Priority Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " INTID678 ,Interrupt ID678 Priority/Priority Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " INTID677 ,Interrupt ID677 Priority/Priority Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " INTID676 ,Interrupt ID676 Priority/Priority Byte Offset 676 " group.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hexmask.long.byte 0x00 24.--31. 1. " INTID683 ,Interrupt ID683 Priority/Priority Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " INTID682 ,Interrupt ID682 Priority/Priority Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " INTID681 ,Interrupt ID681 Priority/Priority Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " INTID680 ,Interrupt ID680 Priority/Priority Byte Offset 680 " group.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hexmask.long.byte 0x00 24.--31. 1. " INTID687 ,Interrupt ID687 Priority/Priority Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " INTID686 ,Interrupt ID686 Priority/Priority Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " INTID685 ,Interrupt ID685 Priority/Priority Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " INTID684 ,Interrupt ID684 Priority/Priority Byte Offset 684 " group.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hexmask.long.byte 0x00 24.--31. 1. " INTID691 ,Interrupt ID691 Priority/Priority Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " INTID690 ,Interrupt ID690 Priority/Priority Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " INTID689 ,Interrupt ID689 Priority/Priority Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " INTID688 ,Interrupt ID688 Priority/Priority Byte Offset 688 " group.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hexmask.long.byte 0x00 24.--31. 1. " INTID695 ,Interrupt ID695 Priority/Priority Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " INTID694 ,Interrupt ID694 Priority/Priority Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " INTID693 ,Interrupt ID693 Priority/Priority Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " INTID692 ,Interrupt ID692 Priority/Priority Byte Offset 692 " group.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hexmask.long.byte 0x00 24.--31. 1. " INTID699 ,Interrupt ID699 Priority/Priority Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " INTID698 ,Interrupt ID698 Priority/Priority Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " INTID697 ,Interrupt ID697 Priority/Priority Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " INTID696 ,Interrupt ID696 Priority/Priority Byte Offset 696 " group.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" hexmask.long.byte 0x00 24.--31. 1. " INTID703 ,Interrupt ID703 Priority/Priority Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " INTID702 ,Interrupt ID702 Priority/Priority Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " INTID701 ,Interrupt ID701 Priority/Priority Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " INTID700 ,Interrupt ID700 Priority/Priority Byte Offset 700 " else hgroup.long 0x6A0++0x03 hide.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hgroup.long 0x6A4++0x03 hide.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hgroup.long 0x6A8++0x03 hide.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hgroup.long 0x6AC++0x03 hide.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hgroup.long 0x6B0++0x03 hide.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hgroup.long 0x6B4++0x03 hide.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hgroup.long 0x6B8++0x03 hide.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hgroup.long 0x6BC++0x03 hide.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hexmask.long.byte 0x00 24.--31. 1. " INTID707 ,Interrupt ID707 Priority/Priority Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " INTID706 ,Interrupt ID706 Priority/Priority Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " INTID705 ,Interrupt ID705 Priority/Priority Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " INTID704 ,Interrupt ID704 Priority/Priority Byte Offset 704 " group.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hexmask.long.byte 0x00 24.--31. 1. " INTID711 ,Interrupt ID711 Priority/Priority Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " INTID710 ,Interrupt ID710 Priority/Priority Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " INTID709 ,Interrupt ID709 Priority/Priority Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " INTID708 ,Interrupt ID708 Priority/Priority Byte Offset 708 " group.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hexmask.long.byte 0x00 24.--31. 1. " INTID715 ,Interrupt ID715 Priority/Priority Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " INTID714 ,Interrupt ID714 Priority/Priority Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " INTID713 ,Interrupt ID713 Priority/Priority Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " INTID712 ,Interrupt ID712 Priority/Priority Byte Offset 712 " group.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hexmask.long.byte 0x00 24.--31. 1. " INTID719 ,Interrupt ID719 Priority/Priority Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " INTID718 ,Interrupt ID718 Priority/Priority Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " INTID717 ,Interrupt ID717 Priority/Priority Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " INTID716 ,Interrupt ID716 Priority/Priority Byte Offset 716 " group.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hexmask.long.byte 0x00 24.--31. 1. " INTID723 ,Interrupt ID723 Priority/Priority Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " INTID722 ,Interrupt ID722 Priority/Priority Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " INTID721 ,Interrupt ID721 Priority/Priority Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " INTID720 ,Interrupt ID720 Priority/Priority Byte Offset 720 " group.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hexmask.long.byte 0x00 24.--31. 1. " INTID727 ,Interrupt ID727 Priority/Priority Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " INTID726 ,Interrupt ID726 Priority/Priority Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " INTID725 ,Interrupt ID725 Priority/Priority Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " INTID724 ,Interrupt ID724 Priority/Priority Byte Offset 724 " group.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hexmask.long.byte 0x00 24.--31. 1. " INTID731 ,Interrupt ID731 Priority/Priority Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " INTID730 ,Interrupt ID730 Priority/Priority Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " INTID729 ,Interrupt ID729 Priority/Priority Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " INTID728 ,Interrupt ID728 Priority/Priority Byte Offset 728 " group.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" hexmask.long.byte 0x00 24.--31. 1. " INTID735 ,Interrupt ID735 Priority/Priority Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " INTID734 ,Interrupt ID734 Priority/Priority Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " INTID733 ,Interrupt ID733 Priority/Priority Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " INTID732 ,Interrupt ID732 Priority/Priority Byte Offset 732 " else hgroup.long 0x6C0++0x03 hide.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hgroup.long 0x6C4++0x03 hide.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hgroup.long 0x6C8++0x03 hide.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hgroup.long 0x6CC++0x03 hide.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hgroup.long 0x6D0++0x03 hide.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hgroup.long 0x6D4++0x03 hide.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hgroup.long 0x6D8++0x03 hide.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hgroup.long 0x6DC++0x03 hide.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hexmask.long.byte 0x00 24.--31. 1. " INTID739 ,Interrupt ID739 Priority/Priority Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " INTID738 ,Interrupt ID738 Priority/Priority Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " INTID737 ,Interrupt ID737 Priority/Priority Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " INTID736 ,Interrupt ID736 Priority/Priority Byte Offset 736 " group.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hexmask.long.byte 0x00 24.--31. 1. " INTID743 ,Interrupt ID743 Priority/Priority Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " INTID742 ,Interrupt ID742 Priority/Priority Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " INTID741 ,Interrupt ID741 Priority/Priority Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " INTID740 ,Interrupt ID740 Priority/Priority Byte Offset 740 " group.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hexmask.long.byte 0x00 24.--31. 1. " INTID747 ,Interrupt ID747 Priority/Priority Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " INTID746 ,Interrupt ID746 Priority/Priority Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " INTID745 ,Interrupt ID745 Priority/Priority Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " INTID744 ,Interrupt ID744 Priority/Priority Byte Offset 744 " group.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hexmask.long.byte 0x00 24.--31. 1. " INTID751 ,Interrupt ID751 Priority/Priority Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " INTID750 ,Interrupt ID750 Priority/Priority Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " INTID749 ,Interrupt ID749 Priority/Priority Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " INTID748 ,Interrupt ID748 Priority/Priority Byte Offset 748 " group.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hexmask.long.byte 0x00 24.--31. 1. " INTID755 ,Interrupt ID755 Priority/Priority Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " INTID754 ,Interrupt ID754 Priority/Priority Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " INTID753 ,Interrupt ID753 Priority/Priority Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " INTID752 ,Interrupt ID752 Priority/Priority Byte Offset 752 " group.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hexmask.long.byte 0x00 24.--31. 1. " INTID759 ,Interrupt ID759 Priority/Priority Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " INTID758 ,Interrupt ID758 Priority/Priority Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " INTID757 ,Interrupt ID757 Priority/Priority Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " INTID756 ,Interrupt ID756 Priority/Priority Byte Offset 756 " group.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hexmask.long.byte 0x00 24.--31. 1. " INTID763 ,Interrupt ID763 Priority/Priority Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " INTID762 ,Interrupt ID762 Priority/Priority Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " INTID761 ,Interrupt ID761 Priority/Priority Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " INTID760 ,Interrupt ID760 Priority/Priority Byte Offset 760 " group.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" hexmask.long.byte 0x00 24.--31. 1. " INTID767 ,Interrupt ID767 Priority/Priority Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " INTID766 ,Interrupt ID766 Priority/Priority Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " INTID765 ,Interrupt ID765 Priority/Priority Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " INTID764 ,Interrupt ID764 Priority/Priority Byte Offset 764 " else hgroup.long 0x6E0++0x03 hide.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hgroup.long 0x6E4++0x03 hide.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hgroup.long 0x6E8++0x03 hide.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hgroup.long 0x6EC++0x03 hide.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hgroup.long 0x6F0++0x03 hide.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hgroup.long 0x6F4++0x03 hide.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hgroup.long 0x6F8++0x03 hide.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hgroup.long 0x6FC++0x03 hide.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hexmask.long.byte 0x00 24.--31. 1. " INTID771 ,Interrupt ID771 Priority/Priority Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " INTID770 ,Interrupt ID770 Priority/Priority Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " INTID769 ,Interrupt ID769 Priority/Priority Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " INTID768 ,Interrupt ID768 Priority/Priority Byte Offset 768 " group.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hexmask.long.byte 0x00 24.--31. 1. " INTID775 ,Interrupt ID775 Priority/Priority Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " INTID774 ,Interrupt ID774 Priority/Priority Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " INTID773 ,Interrupt ID773 Priority/Priority Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " INTID772 ,Interrupt ID772 Priority/Priority Byte Offset 772 " group.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hexmask.long.byte 0x00 24.--31. 1. " INTID779 ,Interrupt ID779 Priority/Priority Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " INTID778 ,Interrupt ID778 Priority/Priority Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " INTID777 ,Interrupt ID777 Priority/Priority Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " INTID776 ,Interrupt ID776 Priority/Priority Byte Offset 776 " group.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hexmask.long.byte 0x00 24.--31. 1. " INTID783 ,Interrupt ID783 Priority/Priority Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " INTID782 ,Interrupt ID782 Priority/Priority Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " INTID781 ,Interrupt ID781 Priority/Priority Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " INTID780 ,Interrupt ID780 Priority/Priority Byte Offset 780 " group.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hexmask.long.byte 0x00 24.--31. 1. " INTID787 ,Interrupt ID787 Priority/Priority Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " INTID786 ,Interrupt ID786 Priority/Priority Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " INTID785 ,Interrupt ID785 Priority/Priority Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " INTID784 ,Interrupt ID784 Priority/Priority Byte Offset 784 " group.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hexmask.long.byte 0x00 24.--31. 1. " INTID791 ,Interrupt ID791 Priority/Priority Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " INTID790 ,Interrupt ID790 Priority/Priority Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " INTID789 ,Interrupt ID789 Priority/Priority Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " INTID788 ,Interrupt ID788 Priority/Priority Byte Offset 788 " group.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hexmask.long.byte 0x00 24.--31. 1. " INTID795 ,Interrupt ID795 Priority/Priority Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " INTID794 ,Interrupt ID794 Priority/Priority Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " INTID793 ,Interrupt ID793 Priority/Priority Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " INTID792 ,Interrupt ID792 Priority/Priority Byte Offset 792 " group.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" hexmask.long.byte 0x00 24.--31. 1. " INTID799 ,Interrupt ID799 Priority/Priority Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " INTID798 ,Interrupt ID798 Priority/Priority Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " INTID797 ,Interrupt ID797 Priority/Priority Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " INTID796 ,Interrupt ID796 Priority/Priority Byte Offset 796 " else hgroup.long 0x700++0x03 hide.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hgroup.long 0x704++0x03 hide.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hgroup.long 0x708++0x03 hide.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hgroup.long 0x70C++0x03 hide.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hgroup.long 0x710++0x03 hide.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hgroup.long 0x714++0x03 hide.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hgroup.long 0x718++0x03 hide.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hgroup.long 0x71C++0x03 hide.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hexmask.long.byte 0x00 24.--31. 1. " INTID803 ,Interrupt ID803 Priority/Priority Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " INTID802 ,Interrupt ID802 Priority/Priority Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " INTID801 ,Interrupt ID801 Priority/Priority Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " INTID800 ,Interrupt ID800 Priority/Priority Byte Offset 800 " group.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hexmask.long.byte 0x00 24.--31. 1. " INTID807 ,Interrupt ID807 Priority/Priority Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " INTID806 ,Interrupt ID806 Priority/Priority Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " INTID805 ,Interrupt ID805 Priority/Priority Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " INTID804 ,Interrupt ID804 Priority/Priority Byte Offset 804 " group.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hexmask.long.byte 0x00 24.--31. 1. " INTID811 ,Interrupt ID811 Priority/Priority Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " INTID810 ,Interrupt ID810 Priority/Priority Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " INTID809 ,Interrupt ID809 Priority/Priority Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " INTID808 ,Interrupt ID808 Priority/Priority Byte Offset 808 " group.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hexmask.long.byte 0x00 24.--31. 1. " INTID815 ,Interrupt ID815 Priority/Priority Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " INTID814 ,Interrupt ID814 Priority/Priority Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " INTID813 ,Interrupt ID813 Priority/Priority Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " INTID812 ,Interrupt ID812 Priority/Priority Byte Offset 812 " group.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hexmask.long.byte 0x00 24.--31. 1. " INTID819 ,Interrupt ID819 Priority/Priority Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " INTID818 ,Interrupt ID818 Priority/Priority Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " INTID817 ,Interrupt ID817 Priority/Priority Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " INTID816 ,Interrupt ID816 Priority/Priority Byte Offset 816 " group.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hexmask.long.byte 0x00 24.--31. 1. " INTID823 ,Interrupt ID823 Priority/Priority Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " INTID822 ,Interrupt ID822 Priority/Priority Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " INTID821 ,Interrupt ID821 Priority/Priority Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " INTID820 ,Interrupt ID820 Priority/Priority Byte Offset 820 " group.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hexmask.long.byte 0x00 24.--31. 1. " INTID827 ,Interrupt ID827 Priority/Priority Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " INTID826 ,Interrupt ID826 Priority/Priority Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " INTID825 ,Interrupt ID825 Priority/Priority Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " INTID824 ,Interrupt ID824 Priority/Priority Byte Offset 824 " group.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" hexmask.long.byte 0x00 24.--31. 1. " INTID831 ,Interrupt ID831 Priority/Priority Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " INTID830 ,Interrupt ID830 Priority/Priority Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " INTID829 ,Interrupt ID829 Priority/Priority Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " INTID828 ,Interrupt ID828 Priority/Priority Byte Offset 828 " else hgroup.long 0x720++0x03 hide.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hgroup.long 0x724++0x03 hide.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hgroup.long 0x728++0x03 hide.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hgroup.long 0x72C++0x03 hide.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hgroup.long 0x730++0x03 hide.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hgroup.long 0x734++0x03 hide.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hgroup.long 0x738++0x03 hide.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hgroup.long 0x73C++0x03 hide.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hexmask.long.byte 0x00 24.--31. 1. " INTID835 ,Interrupt ID835 Priority/Priority Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " INTID834 ,Interrupt ID834 Priority/Priority Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " INTID833 ,Interrupt ID833 Priority/Priority Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " INTID832 ,Interrupt ID832 Priority/Priority Byte Offset 832 " group.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hexmask.long.byte 0x00 24.--31. 1. " INTID839 ,Interrupt ID839 Priority/Priority Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " INTID838 ,Interrupt ID838 Priority/Priority Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " INTID837 ,Interrupt ID837 Priority/Priority Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " INTID836 ,Interrupt ID836 Priority/Priority Byte Offset 836 " group.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hexmask.long.byte 0x00 24.--31. 1. " INTID843 ,Interrupt ID843 Priority/Priority Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " INTID842 ,Interrupt ID842 Priority/Priority Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " INTID841 ,Interrupt ID841 Priority/Priority Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " INTID840 ,Interrupt ID840 Priority/Priority Byte Offset 840 " group.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hexmask.long.byte 0x00 24.--31. 1. " INTID847 ,Interrupt ID847 Priority/Priority Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " INTID846 ,Interrupt ID846 Priority/Priority Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " INTID845 ,Interrupt ID845 Priority/Priority Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " INTID844 ,Interrupt ID844 Priority/Priority Byte Offset 844 " group.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hexmask.long.byte 0x00 24.--31. 1. " INTID851 ,Interrupt ID851 Priority/Priority Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " INTID850 ,Interrupt ID850 Priority/Priority Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " INTID849 ,Interrupt ID849 Priority/Priority Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " INTID848 ,Interrupt ID848 Priority/Priority Byte Offset 848 " group.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hexmask.long.byte 0x00 24.--31. 1. " INTID855 ,Interrupt ID855 Priority/Priority Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " INTID854 ,Interrupt ID854 Priority/Priority Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " INTID853 ,Interrupt ID853 Priority/Priority Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " INTID852 ,Interrupt ID852 Priority/Priority Byte Offset 852 " group.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hexmask.long.byte 0x00 24.--31. 1. " INTID859 ,Interrupt ID859 Priority/Priority Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " INTID858 ,Interrupt ID858 Priority/Priority Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " INTID857 ,Interrupt ID857 Priority/Priority Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " INTID856 ,Interrupt ID856 Priority/Priority Byte Offset 856 " group.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" hexmask.long.byte 0x00 24.--31. 1. " INTID863 ,Interrupt ID863 Priority/Priority Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " INTID862 ,Interrupt ID862 Priority/Priority Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " INTID861 ,Interrupt ID861 Priority/Priority Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " INTID860 ,Interrupt ID860 Priority/Priority Byte Offset 860 " else hgroup.long 0x740++0x03 hide.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hgroup.long 0x744++0x03 hide.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hgroup.long 0x748++0x03 hide.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hgroup.long 0x74C++0x03 hide.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hgroup.long 0x750++0x03 hide.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hgroup.long 0x754++0x03 hide.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hgroup.long 0x758++0x03 hide.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hgroup.long 0x75C++0x03 hide.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hexmask.long.byte 0x00 24.--31. 1. " INTID867 ,Interrupt ID867 Priority/Priority Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " INTID866 ,Interrupt ID866 Priority/Priority Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " INTID865 ,Interrupt ID865 Priority/Priority Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " INTID864 ,Interrupt ID864 Priority/Priority Byte Offset 864 " group.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hexmask.long.byte 0x00 24.--31. 1. " INTID871 ,Interrupt ID871 Priority/Priority Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " INTID870 ,Interrupt ID870 Priority/Priority Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " INTID869 ,Interrupt ID869 Priority/Priority Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " INTID868 ,Interrupt ID868 Priority/Priority Byte Offset 868 " group.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hexmask.long.byte 0x00 24.--31. 1. " INTID875 ,Interrupt ID875 Priority/Priority Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " INTID874 ,Interrupt ID874 Priority/Priority Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " INTID873 ,Interrupt ID873 Priority/Priority Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " INTID872 ,Interrupt ID872 Priority/Priority Byte Offset 872 " group.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hexmask.long.byte 0x00 24.--31. 1. " INTID879 ,Interrupt ID879 Priority/Priority Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " INTID878 ,Interrupt ID878 Priority/Priority Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " INTID877 ,Interrupt ID877 Priority/Priority Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " INTID876 ,Interrupt ID876 Priority/Priority Byte Offset 876 " group.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hexmask.long.byte 0x00 24.--31. 1. " INTID883 ,Interrupt ID883 Priority/Priority Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " INTID882 ,Interrupt ID882 Priority/Priority Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " INTID881 ,Interrupt ID881 Priority/Priority Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " INTID880 ,Interrupt ID880 Priority/Priority Byte Offset 880 " group.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hexmask.long.byte 0x00 24.--31. 1. " INTID887 ,Interrupt ID887 Priority/Priority Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " INTID886 ,Interrupt ID886 Priority/Priority Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " INTID885 ,Interrupt ID885 Priority/Priority Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " INTID884 ,Interrupt ID884 Priority/Priority Byte Offset 884 " group.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hexmask.long.byte 0x00 24.--31. 1. " INTID891 ,Interrupt ID891 Priority/Priority Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " INTID890 ,Interrupt ID890 Priority/Priority Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " INTID889 ,Interrupt ID889 Priority/Priority Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " INTID888 ,Interrupt ID888 Priority/Priority Byte Offset 888 " group.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" hexmask.long.byte 0x00 24.--31. 1. " INTID895 ,Interrupt ID895 Priority/Priority Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " INTID894 ,Interrupt ID894 Priority/Priority Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " INTID893 ,Interrupt ID893 Priority/Priority Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " INTID892 ,Interrupt ID892 Priority/Priority Byte Offset 892 " else hgroup.long 0x760++0x03 hide.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hgroup.long 0x764++0x03 hide.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hgroup.long 0x768++0x03 hide.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hgroup.long 0x76C++0x03 hide.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hgroup.long 0x770++0x03 hide.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hgroup.long 0x774++0x03 hide.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hgroup.long 0x778++0x03 hide.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hgroup.long 0x77C++0x03 hide.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hexmask.long.byte 0x00 24.--31. 1. " INTID899 ,Interrupt ID899 Priority/Priority Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " INTID898 ,Interrupt ID898 Priority/Priority Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " INTID897 ,Interrupt ID897 Priority/Priority Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " INTID896 ,Interrupt ID896 Priority/Priority Byte Offset 896 " group.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hexmask.long.byte 0x00 24.--31. 1. " INTID903 ,Interrupt ID903 Priority/Priority Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " INTID902 ,Interrupt ID902 Priority/Priority Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " INTID901 ,Interrupt ID901 Priority/Priority Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " INTID900 ,Interrupt ID900 Priority/Priority Byte Offset 900 " group.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hexmask.long.byte 0x00 24.--31. 1. " INTID907 ,Interrupt ID907 Priority/Priority Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " INTID906 ,Interrupt ID906 Priority/Priority Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " INTID905 ,Interrupt ID905 Priority/Priority Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " INTID904 ,Interrupt ID904 Priority/Priority Byte Offset 904 " group.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hexmask.long.byte 0x00 24.--31. 1. " INTID911 ,Interrupt ID911 Priority/Priority Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " INTID910 ,Interrupt ID910 Priority/Priority Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " INTID909 ,Interrupt ID909 Priority/Priority Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " INTID908 ,Interrupt ID908 Priority/Priority Byte Offset 908 " group.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hexmask.long.byte 0x00 24.--31. 1. " INTID915 ,Interrupt ID915 Priority/Priority Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " INTID914 ,Interrupt ID914 Priority/Priority Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " INTID913 ,Interrupt ID913 Priority/Priority Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " INTID912 ,Interrupt ID912 Priority/Priority Byte Offset 912 " group.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hexmask.long.byte 0x00 24.--31. 1. " INTID919 ,Interrupt ID919 Priority/Priority Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " INTID918 ,Interrupt ID918 Priority/Priority Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " INTID917 ,Interrupt ID917 Priority/Priority Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " INTID916 ,Interrupt ID916 Priority/Priority Byte Offset 916 " group.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hexmask.long.byte 0x00 24.--31. 1. " INTID923 ,Interrupt ID923 Priority/Priority Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " INTID922 ,Interrupt ID922 Priority/Priority Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " INTID921 ,Interrupt ID921 Priority/Priority Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " INTID920 ,Interrupt ID920 Priority/Priority Byte Offset 920 " group.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" hexmask.long.byte 0x00 24.--31. 1. " INTID927 ,Interrupt ID927 Priority/Priority Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " INTID926 ,Interrupt ID926 Priority/Priority Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " INTID925 ,Interrupt ID925 Priority/Priority Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " INTID924 ,Interrupt ID924 Priority/Priority Byte Offset 924 " else hgroup.long 0x780++0x03 hide.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hgroup.long 0x784++0x03 hide.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hgroup.long 0x788++0x03 hide.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hgroup.long 0x78C++0x03 hide.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hgroup.long 0x790++0x03 hide.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hgroup.long 0x794++0x03 hide.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hgroup.long 0x798++0x03 hide.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hgroup.long 0x79C++0x03 hide.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hexmask.long.byte 0x00 24.--31. 1. " INTID931 ,Interrupt ID931 Priority/Priority Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " INTID930 ,Interrupt ID930 Priority/Priority Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " INTID929 ,Interrupt ID929 Priority/Priority Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " INTID928 ,Interrupt ID928 Priority/Priority Byte Offset 928 " group.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hexmask.long.byte 0x00 24.--31. 1. " INTID935 ,Interrupt ID935 Priority/Priority Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " INTID934 ,Interrupt ID934 Priority/Priority Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " INTID933 ,Interrupt ID933 Priority/Priority Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " INTID932 ,Interrupt ID932 Priority/Priority Byte Offset 932 " group.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hexmask.long.byte 0x00 24.--31. 1. " INTID939 ,Interrupt ID939 Priority/Priority Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " INTID938 ,Interrupt ID938 Priority/Priority Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " INTID937 ,Interrupt ID937 Priority/Priority Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " INTID936 ,Interrupt ID936 Priority/Priority Byte Offset 936 " group.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hexmask.long.byte 0x00 24.--31. 1. " INTID943 ,Interrupt ID943 Priority/Priority Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " INTID942 ,Interrupt ID942 Priority/Priority Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " INTID941 ,Interrupt ID941 Priority/Priority Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " INTID940 ,Interrupt ID940 Priority/Priority Byte Offset 940 " group.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hexmask.long.byte 0x00 24.--31. 1. " INTID947 ,Interrupt ID947 Priority/Priority Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " INTID946 ,Interrupt ID946 Priority/Priority Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " INTID945 ,Interrupt ID945 Priority/Priority Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " INTID944 ,Interrupt ID944 Priority/Priority Byte Offset 944 " group.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hexmask.long.byte 0x00 24.--31. 1. " INTID951 ,Interrupt ID951 Priority/Priority Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " INTID950 ,Interrupt ID950 Priority/Priority Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " INTID949 ,Interrupt ID949 Priority/Priority Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " INTID948 ,Interrupt ID948 Priority/Priority Byte Offset 948 " group.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hexmask.long.byte 0x00 24.--31. 1. " INTID955 ,Interrupt ID955 Priority/Priority Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " INTID954 ,Interrupt ID954 Priority/Priority Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " INTID953 ,Interrupt ID953 Priority/Priority Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " INTID952 ,Interrupt ID952 Priority/Priority Byte Offset 952 " group.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" hexmask.long.byte 0x00 24.--31. 1. " INTID959 ,Interrupt ID959 Priority/Priority Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " INTID958 ,Interrupt ID958 Priority/Priority Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " INTID957 ,Interrupt ID957 Priority/Priority Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " INTID956 ,Interrupt ID956 Priority/Priority Byte Offset 956 " else hgroup.long 0x7A0++0x03 hide.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hgroup.long 0x7A4++0x03 hide.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hgroup.long 0x7A8++0x03 hide.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hgroup.long 0x7AC++0x03 hide.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hgroup.long 0x7B0++0x03 hide.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hgroup.long 0x7B4++0x03 hide.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hgroup.long 0x7B8++0x03 hide.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hgroup.long 0x7BC++0x03 hide.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hexmask.long.byte 0x00 24.--31. 1. " INTID963 ,Interrupt ID963 Priority/Priority Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " INTID962 ,Interrupt ID962 Priority/Priority Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " INTID961 ,Interrupt ID961 Priority/Priority Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " INTID960 ,Interrupt ID960 Priority/Priority Byte Offset 960 " group.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hexmask.long.byte 0x00 24.--31. 1. " INTID967 ,Interrupt ID967 Priority/Priority Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " INTID966 ,Interrupt ID966 Priority/Priority Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " INTID965 ,Interrupt ID965 Priority/Priority Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " INTID964 ,Interrupt ID964 Priority/Priority Byte Offset 964 " group.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hexmask.long.byte 0x00 24.--31. 1. " INTID971 ,Interrupt ID971 Priority/Priority Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " INTID970 ,Interrupt ID970 Priority/Priority Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " INTID969 ,Interrupt ID969 Priority/Priority Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " INTID968 ,Interrupt ID968 Priority/Priority Byte Offset 968 " group.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hexmask.long.byte 0x00 24.--31. 1. " INTID975 ,Interrupt ID975 Priority/Priority Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " INTID974 ,Interrupt ID974 Priority/Priority Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " INTID973 ,Interrupt ID973 Priority/Priority Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " INTID972 ,Interrupt ID972 Priority/Priority Byte Offset 972 " group.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hexmask.long.byte 0x00 24.--31. 1. " INTID979 ,Interrupt ID979 Priority/Priority Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " INTID978 ,Interrupt ID978 Priority/Priority Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " INTID977 ,Interrupt ID977 Priority/Priority Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " INTID976 ,Interrupt ID976 Priority/Priority Byte Offset 976 " group.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hexmask.long.byte 0x00 24.--31. 1. " INTID983 ,Interrupt ID983 Priority/Priority Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " INTID982 ,Interrupt ID982 Priority/Priority Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " INTID981 ,Interrupt ID981 Priority/Priority Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " INTID980 ,Interrupt ID980 Priority/Priority Byte Offset 980 " group.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hexmask.long.byte 0x00 24.--31. 1. " INTID987 ,Interrupt ID987 Priority/Priority Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " INTID986 ,Interrupt ID986 Priority/Priority Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " INTID985 ,Interrupt ID985 Priority/Priority Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " INTID984 ,Interrupt ID984 Priority/Priority Byte Offset 984 " group.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" hexmask.long.byte 0x00 24.--31. 1. " INTID991 ,Interrupt ID991 Priority/Priority Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " INTID990 ,Interrupt ID990 Priority/Priority Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " INTID989 ,Interrupt ID989 Priority/Priority Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " INTID988 ,Interrupt ID988 Priority/Priority Byte Offset 988 " else hgroup.long 0x7C0++0x03 hide.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hgroup.long 0x7C4++0x03 hide.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hgroup.long 0x7C8++0x03 hide.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hgroup.long 0x7CC++0x03 hide.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hgroup.long 0x7D0++0x03 hide.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hgroup.long 0x7D4++0x03 hide.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hgroup.long 0x7D8++0x03 hide.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hgroup.long 0x7DC++0x03 hide.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" endif tree.end width 19. tree "Interrupt Targets Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x000000E0)>0x1) hgroup.long 0x800++0x03 hide.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0" hgroup.long 0x804++0x03 hide.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1" hgroup.long 0x808++0x03 hide.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2" hgroup.long 0x80C++0x03 hide.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3" hgroup.long 0x810++0x03 hide.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4" hgroup.long 0x814++0x03 hide.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5" hgroup.long 0x818++0x03 hide.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6" hgroup.long 0x81C++0x03 hide.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35 ,CPU Targets Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO34 ,CPU Targets Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO33 ,CPU Targets Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO32 ,CPU Targets Byte Offset 32 " group.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39 ,CPU Targets Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO38 ,CPU Targets Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO37 ,CPU Targets Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO36 ,CPU Targets Byte Offset 36 " group.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43 ,CPU Targets Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO42 ,CPU Targets Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO41 ,CPU Targets Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO40 ,CPU Targets Byte Offset 40 " group.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47 ,CPU Targets Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO46 ,CPU Targets Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO45 ,CPU Targets Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO44 ,CPU Targets Byte Offset 44 " group.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51 ,CPU Targets Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO50 ,CPU Targets Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO49 ,CPU Targets Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO48 ,CPU Targets Byte Offset 48 " group.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55 ,CPU Targets Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO54 ,CPU Targets Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO53 ,CPU Targets Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO52 ,CPU Targets Byte Offset 52 " group.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59 ,CPU Targets Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO58 ,CPU Targets Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO57 ,CPU Targets Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO56 ,CPU Targets Byte Offset 56 " group.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63 ,CPU Targets Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO62 ,CPU Targets Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO61 ,CPU Targets Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO60 ,CPU Targets Byte Offset 60 " else hgroup.long 0x820++0x03 hide.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hgroup.long 0x824++0x03 hide.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hgroup.long 0x828++0x03 hide.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hgroup.long 0x82C++0x03 hide.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hgroup.long 0x830++0x03 hide.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hgroup.long 0x834++0x03 hide.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hgroup.long 0x838++0x03 hide.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hgroup.long 0x83C++0x03 hide.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67 ,CPU Targets Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO66 ,CPU Targets Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO65 ,CPU Targets Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO64 ,CPU Targets Byte Offset 64 " group.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71 ,CPU Targets Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO70 ,CPU Targets Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO69 ,CPU Targets Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO68 ,CPU Targets Byte Offset 68 " group.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75 ,CPU Targets Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO74 ,CPU Targets Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO73 ,CPU Targets Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO72 ,CPU Targets Byte Offset 72 " group.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79 ,CPU Targets Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO78 ,CPU Targets Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO77 ,CPU Targets Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO76 ,CPU Targets Byte Offset 76 " group.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83 ,CPU Targets Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO82 ,CPU Targets Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO81 ,CPU Targets Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO80 ,CPU Targets Byte Offset 80 " group.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87 ,CPU Targets Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO86 ,CPU Targets Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO85 ,CPU Targets Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO84 ,CPU Targets Byte Offset 84 " group.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91 ,CPU Targets Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO90 ,CPU Targets Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO89 ,CPU Targets Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO88 ,CPU Targets Byte Offset 88 " group.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95 ,CPU Targets Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO94 ,CPU Targets Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO93 ,CPU Targets Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO92 ,CPU Targets Byte Offset 92 " else hgroup.long 0x840++0x03 hide.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hgroup.long 0x844++0x03 hide.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hgroup.long 0x848++0x03 hide.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hgroup.long 0x84C++0x03 hide.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hgroup.long 0x850++0x03 hide.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hgroup.long 0x854++0x03 hide.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hgroup.long 0x858++0x03 hide.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hgroup.long 0x85C++0x03 hide.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99 ,CPU Targets Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO98 ,CPU Targets Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO97 ,CPU Targets Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO96 ,CPU Targets Byte Offset 96 " group.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103 ,CPU Targets Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO102 ,CPU Targets Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO101 ,CPU Targets Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO100 ,CPU Targets Byte Offset 100 " group.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107 ,CPU Targets Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO106 ,CPU Targets Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO105 ,CPU Targets Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO104 ,CPU Targets Byte Offset 104 " group.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111 ,CPU Targets Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO110 ,CPU Targets Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO109 ,CPU Targets Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO108 ,CPU Targets Byte Offset 108 " group.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115 ,CPU Targets Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO114 ,CPU Targets Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO113 ,CPU Targets Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO112 ,CPU Targets Byte Offset 112 " group.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119 ,CPU Targets Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO118 ,CPU Targets Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO117 ,CPU Targets Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO116 ,CPU Targets Byte Offset 116 " group.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123 ,CPU Targets Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO122 ,CPU Targets Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO121 ,CPU Targets Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO120 ,CPU Targets Byte Offset 120 " group.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127 ,CPU Targets Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO126 ,CPU Targets Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO125 ,CPU Targets Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO124 ,CPU Targets Byte Offset 124 " else hgroup.long 0x860++0x03 hide.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hgroup.long 0x864++0x03 hide.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hgroup.long 0x868++0x03 hide.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hgroup.long 0x86C++0x03 hide.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hgroup.long 0x870++0x03 hide.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hgroup.long 0x874++0x03 hide.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hgroup.long 0x878++0x03 hide.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hgroup.long 0x87C++0x03 hide.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131 ,CPU Targets Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO130 ,CPU Targets Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO129 ,CPU Targets Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO128 ,CPU Targets Byte Offset 128 " group.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135 ,CPU Targets Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO134 ,CPU Targets Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO133 ,CPU Targets Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO132 ,CPU Targets Byte Offset 132 " group.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139 ,CPU Targets Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO138 ,CPU Targets Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO137 ,CPU Targets Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO136 ,CPU Targets Byte Offset 136 " group.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143 ,CPU Targets Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO142 ,CPU Targets Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO141 ,CPU Targets Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO140 ,CPU Targets Byte Offset 140 " group.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147 ,CPU Targets Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO146 ,CPU Targets Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO145 ,CPU Targets Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO144 ,CPU Targets Byte Offset 144 " group.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151 ,CPU Targets Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO150 ,CPU Targets Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO149 ,CPU Targets Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO148 ,CPU Targets Byte Offset 148 " group.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155 ,CPU Targets Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO154 ,CPU Targets Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO153 ,CPU Targets Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO152 ,CPU Targets Byte Offset 152 " group.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159 ,CPU Targets Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO158 ,CPU Targets Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO157 ,CPU Targets Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO156 ,CPU Targets Byte Offset 156 " else hgroup.long 0x880++0x03 hide.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hgroup.long 0x884++0x03 hide.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hgroup.long 0x888++0x03 hide.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hgroup.long 0x88C++0x03 hide.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hgroup.long 0x890++0x03 hide.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hgroup.long 0x894++0x03 hide.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hgroup.long 0x898++0x03 hide.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hgroup.long 0x89C++0x03 hide.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163 ,CPU Targets Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO162 ,CPU Targets Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO161 ,CPU Targets Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO160 ,CPU Targets Byte Offset 160 " group.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167 ,CPU Targets Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO166 ,CPU Targets Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO165 ,CPU Targets Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO164 ,CPU Targets Byte Offset 164 " group.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171 ,CPU Targets Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO170 ,CPU Targets Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO169 ,CPU Targets Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO168 ,CPU Targets Byte Offset 168 " group.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175 ,CPU Targets Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO174 ,CPU Targets Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO173 ,CPU Targets Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO172 ,CPU Targets Byte Offset 172 " group.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179 ,CPU Targets Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO178 ,CPU Targets Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO177 ,CPU Targets Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO176 ,CPU Targets Byte Offset 176 " group.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183 ,CPU Targets Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO182 ,CPU Targets Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO181 ,CPU Targets Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO180 ,CPU Targets Byte Offset 180 " group.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187 ,CPU Targets Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO186 ,CPU Targets Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO185 ,CPU Targets Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO184 ,CPU Targets Byte Offset 184 " group.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191 ,CPU Targets Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO190 ,CPU Targets Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO189 ,CPU Targets Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO188 ,CPU Targets Byte Offset 188 " else hgroup.long 0x8A0++0x03 hide.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hgroup.long 0x8A4++0x03 hide.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hgroup.long 0x8A8++0x03 hide.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hgroup.long 0x8AC++0x03 hide.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hgroup.long 0x8B0++0x03 hide.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hgroup.long 0x8B4++0x03 hide.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hgroup.long 0x8B8++0x03 hide.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hgroup.long 0x8BC++0x03 hide.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195 ,CPU Targets Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO194 ,CPU Targets Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO193 ,CPU Targets Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO192 ,CPU Targets Byte Offset 192 " group.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199 ,CPU Targets Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO198 ,CPU Targets Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO197 ,CPU Targets Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO196 ,CPU Targets Byte Offset 196 " group.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203 ,CPU Targets Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO202 ,CPU Targets Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO201 ,CPU Targets Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO200 ,CPU Targets Byte Offset 200 " group.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207 ,CPU Targets Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO206 ,CPU Targets Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO205 ,CPU Targets Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO204 ,CPU Targets Byte Offset 204 " group.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211 ,CPU Targets Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO210 ,CPU Targets Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO209 ,CPU Targets Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO208 ,CPU Targets Byte Offset 208 " group.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215 ,CPU Targets Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO214 ,CPU Targets Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO213 ,CPU Targets Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO212 ,CPU Targets Byte Offset 212 " group.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219 ,CPU Targets Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO218 ,CPU Targets Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO217 ,CPU Targets Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO216 ,CPU Targets Byte Offset 216 " group.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223 ,CPU Targets Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO222 ,CPU Targets Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO221 ,CPU Targets Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO220 ,CPU Targets Byte Offset 220 " else hgroup.long 0x8C0++0x03 hide.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hgroup.long 0x8C4++0x03 hide.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hgroup.long 0x8C8++0x03 hide.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hgroup.long 0x8CC++0x03 hide.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hgroup.long 0x8D0++0x03 hide.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hgroup.long 0x8D4++0x03 hide.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hgroup.long 0x8D8++0x03 hide.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hgroup.long 0x8DC++0x03 hide.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227 ,CPU Targets Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO226 ,CPU Targets Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO225 ,CPU Targets Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO224 ,CPU Targets Byte Offset 224 " group.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231 ,CPU Targets Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO230 ,CPU Targets Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO229 ,CPU Targets Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO228 ,CPU Targets Byte Offset 228 " group.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235 ,CPU Targets Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO234 ,CPU Targets Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO233 ,CPU Targets Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO232 ,CPU Targets Byte Offset 232 " group.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239 ,CPU Targets Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO238 ,CPU Targets Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO237 ,CPU Targets Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO236 ,CPU Targets Byte Offset 236 " group.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243 ,CPU Targets Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO242 ,CPU Targets Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO241 ,CPU Targets Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO240 ,CPU Targets Byte Offset 240 " group.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247 ,CPU Targets Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO246 ,CPU Targets Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO245 ,CPU Targets Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO244 ,CPU Targets Byte Offset 244 " group.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251 ,CPU Targets Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO250 ,CPU Targets Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO249 ,CPU Targets Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO248 ,CPU Targets Byte Offset 248 " group.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255 ,CPU Targets Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO254 ,CPU Targets Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO253 ,CPU Targets Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO252 ,CPU Targets Byte Offset 252 " else hgroup.long 0x8E0++0x03 hide.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hgroup.long 0x8E4++0x03 hide.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hgroup.long 0x8E8++0x03 hide.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hgroup.long 0x8EC++0x03 hide.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hgroup.long 0x8F0++0x03 hide.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hgroup.long 0x8F4++0x03 hide.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hgroup.long 0x8F8++0x03 hide.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hgroup.long 0x8FC++0x03 hide.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259 ,CPU Targets Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO258 ,CPU Targets Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO257 ,CPU Targets Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO256 ,CPU Targets Byte Offset 256 " group.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263 ,CPU Targets Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO262 ,CPU Targets Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO261 ,CPU Targets Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO260 ,CPU Targets Byte Offset 260 " group.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267 ,CPU Targets Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO266 ,CPU Targets Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO265 ,CPU Targets Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO264 ,CPU Targets Byte Offset 264 " group.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271 ,CPU Targets Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO270 ,CPU Targets Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO269 ,CPU Targets Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO268 ,CPU Targets Byte Offset 268 " group.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275 ,CPU Targets Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO274 ,CPU Targets Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO273 ,CPU Targets Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO272 ,CPU Targets Byte Offset 272 " group.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279 ,CPU Targets Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO278 ,CPU Targets Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO277 ,CPU Targets Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO276 ,CPU Targets Byte Offset 276 " group.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283 ,CPU Targets Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO282 ,CPU Targets Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO281 ,CPU Targets Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO280 ,CPU Targets Byte Offset 280 " group.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287 ,CPU Targets Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO286 ,CPU Targets Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO285 ,CPU Targets Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO284 ,CPU Targets Byte Offset 284 " else hgroup.long 0x900++0x03 hide.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hgroup.long 0x904++0x03 hide.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hgroup.long 0x908++0x03 hide.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hgroup.long 0x90C++0x03 hide.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hgroup.long 0x910++0x03 hide.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hgroup.long 0x914++0x03 hide.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hgroup.long 0x918++0x03 hide.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hgroup.long 0x91C++0x03 hide.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291 ,CPU Targets Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO290 ,CPU Targets Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO289 ,CPU Targets Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO288 ,CPU Targets Byte Offset 288 " group.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295 ,CPU Targets Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO294 ,CPU Targets Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO293 ,CPU Targets Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO292 ,CPU Targets Byte Offset 292 " group.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299 ,CPU Targets Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO298 ,CPU Targets Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO297 ,CPU Targets Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO296 ,CPU Targets Byte Offset 296 " group.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303 ,CPU Targets Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO302 ,CPU Targets Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO301 ,CPU Targets Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO300 ,CPU Targets Byte Offset 300 " group.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307 ,CPU Targets Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO306 ,CPU Targets Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO305 ,CPU Targets Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO304 ,CPU Targets Byte Offset 304 " group.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311 ,CPU Targets Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO310 ,CPU Targets Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO309 ,CPU Targets Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO308 ,CPU Targets Byte Offset 308 " group.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315 ,CPU Targets Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO314 ,CPU Targets Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO313 ,CPU Targets Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO312 ,CPU Targets Byte Offset 312 " group.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319 ,CPU Targets Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO318 ,CPU Targets Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO317 ,CPU Targets Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO316 ,CPU Targets Byte Offset 316 " else hgroup.long 0x920++0x03 hide.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hgroup.long 0x924++0x03 hide.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hgroup.long 0x928++0x03 hide.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hgroup.long 0x92C++0x03 hide.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hgroup.long 0x930++0x03 hide.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hgroup.long 0x934++0x03 hide.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hgroup.long 0x938++0x03 hide.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hgroup.long 0x93C++0x03 hide.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323 ,CPU Targets Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO322 ,CPU Targets Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO321 ,CPU Targets Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO320 ,CPU Targets Byte Offset 320 " group.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327 ,CPU Targets Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO326 ,CPU Targets Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO325 ,CPU Targets Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO324 ,CPU Targets Byte Offset 324 " group.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331 ,CPU Targets Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO330 ,CPU Targets Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO329 ,CPU Targets Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO328 ,CPU Targets Byte Offset 328 " group.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335 ,CPU Targets Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO334 ,CPU Targets Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO333 ,CPU Targets Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO332 ,CPU Targets Byte Offset 332 " group.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339 ,CPU Targets Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO338 ,CPU Targets Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO337 ,CPU Targets Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO336 ,CPU Targets Byte Offset 336 " group.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343 ,CPU Targets Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO342 ,CPU Targets Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO341 ,CPU Targets Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO340 ,CPU Targets Byte Offset 340 " group.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347 ,CPU Targets Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO346 ,CPU Targets Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO345 ,CPU Targets Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO344 ,CPU Targets Byte Offset 344 " group.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351 ,CPU Targets Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO350 ,CPU Targets Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO349 ,CPU Targets Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO348 ,CPU Targets Byte Offset 348 " else hgroup.long 0x940++0x03 hide.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hgroup.long 0x944++0x03 hide.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hgroup.long 0x948++0x03 hide.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hgroup.long 0x94C++0x03 hide.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hgroup.long 0x950++0x03 hide.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hgroup.long 0x954++0x03 hide.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hgroup.long 0x958++0x03 hide.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hgroup.long 0x95C++0x03 hide.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355 ,CPU Targets Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO354 ,CPU Targets Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO353 ,CPU Targets Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO352 ,CPU Targets Byte Offset 352 " group.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359 ,CPU Targets Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO358 ,CPU Targets Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO357 ,CPU Targets Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO356 ,CPU Targets Byte Offset 356 " group.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363 ,CPU Targets Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO362 ,CPU Targets Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO361 ,CPU Targets Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO360 ,CPU Targets Byte Offset 360 " group.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367 ,CPU Targets Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO366 ,CPU Targets Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO365 ,CPU Targets Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO364 ,CPU Targets Byte Offset 364 " group.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371 ,CPU Targets Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO370 ,CPU Targets Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO369 ,CPU Targets Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO368 ,CPU Targets Byte Offset 368 " group.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375 ,CPU Targets Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO374 ,CPU Targets Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO373 ,CPU Targets Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO372 ,CPU Targets Byte Offset 372 " group.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379 ,CPU Targets Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO378 ,CPU Targets Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO377 ,CPU Targets Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO376 ,CPU Targets Byte Offset 376 " group.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383 ,CPU Targets Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO382 ,CPU Targets Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO381 ,CPU Targets Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO380 ,CPU Targets Byte Offset 380 " else hgroup.long 0x960++0x03 hide.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hgroup.long 0x964++0x03 hide.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hgroup.long 0x968++0x03 hide.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hgroup.long 0x96C++0x03 hide.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hgroup.long 0x970++0x03 hide.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hgroup.long 0x974++0x03 hide.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hgroup.long 0x978++0x03 hide.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hgroup.long 0x97C++0x03 hide.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387 ,CPU Targets Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO386 ,CPU Targets Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO385 ,CPU Targets Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO384 ,CPU Targets Byte Offset 384 " group.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391 ,CPU Targets Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO390 ,CPU Targets Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO389 ,CPU Targets Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO388 ,CPU Targets Byte Offset 388 " group.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395 ,CPU Targets Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO394 ,CPU Targets Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO393 ,CPU Targets Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO392 ,CPU Targets Byte Offset 392 " group.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399 ,CPU Targets Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO398 ,CPU Targets Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO397 ,CPU Targets Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO396 ,CPU Targets Byte Offset 396 " group.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403 ,CPU Targets Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO402 ,CPU Targets Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO401 ,CPU Targets Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO400 ,CPU Targets Byte Offset 400 " group.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407 ,CPU Targets Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO406 ,CPU Targets Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO405 ,CPU Targets Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO404 ,CPU Targets Byte Offset 404 " group.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411 ,CPU Targets Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO410 ,CPU Targets Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO409 ,CPU Targets Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO408 ,CPU Targets Byte Offset 408 " group.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415 ,CPU Targets Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO414 ,CPU Targets Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO413 ,CPU Targets Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO412 ,CPU Targets Byte Offset 412 " else hgroup.long 0x980++0x03 hide.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hgroup.long 0x984++0x03 hide.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hgroup.long 0x988++0x03 hide.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hgroup.long 0x98C++0x03 hide.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hgroup.long 0x990++0x03 hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hgroup.long 0x994++0x03 hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hgroup.long 0x998++0x03 hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hgroup.long 0x99C++0x03 hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419 ,CPU Targets Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO418 ,CPU Targets Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO417 ,CPU Targets Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO416 ,CPU Targets Byte Offset 416 " group.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423 ,CPU Targets Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO422 ,CPU Targets Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO421 ,CPU Targets Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO420 ,CPU Targets Byte Offset 420 " group.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427 ,CPU Targets Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO426 ,CPU Targets Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO425 ,CPU Targets Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO424 ,CPU Targets Byte Offset 424 " group.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431 ,CPU Targets Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO430 ,CPU Targets Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO429 ,CPU Targets Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO428 ,CPU Targets Byte Offset 428 " group.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435 ,CPU Targets Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO434 ,CPU Targets Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO433 ,CPU Targets Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO432 ,CPU Targets Byte Offset 432 " group.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439 ,CPU Targets Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO438 ,CPU Targets Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO437 ,CPU Targets Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO436 ,CPU Targets Byte Offset 436 " group.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443 ,CPU Targets Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO442 ,CPU Targets Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO441 ,CPU Targets Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO440 ,CPU Targets Byte Offset 440 " group.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447 ,CPU Targets Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO446 ,CPU Targets Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO445 ,CPU Targets Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO444 ,CPU Targets Byte Offset 444 " else hgroup.long 0x9A0++0x03 hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hgroup.long 0x9A4++0x03 hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hgroup.long 0x9A8++0x03 hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hgroup.long 0x9AC++0x03 hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hgroup.long 0x9B0++0x03 hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hgroup.long 0x9B4++0x03 hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hgroup.long 0x9B8++0x03 hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hgroup.long 0x9BC++0x03 hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451 ,CPU Targets Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO450 ,CPU Targets Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO449 ,CPU Targets Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO448 ,CPU Targets Byte Offset 448 " group.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455 ,CPU Targets Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO454 ,CPU Targets Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO453 ,CPU Targets Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO452 ,CPU Targets Byte Offset 452 " group.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459 ,CPU Targets Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO458 ,CPU Targets Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO457 ,CPU Targets Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO456 ,CPU Targets Byte Offset 456 " group.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463 ,CPU Targets Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO462 ,CPU Targets Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO461 ,CPU Targets Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO460 ,CPU Targets Byte Offset 460 " group.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467 ,CPU Targets Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO466 ,CPU Targets Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO465 ,CPU Targets Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO464 ,CPU Targets Byte Offset 464 " group.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471 ,CPU Targets Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO470 ,CPU Targets Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO469 ,CPU Targets Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO468 ,CPU Targets Byte Offset 468 " group.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475 ,CPU Targets Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO474 ,CPU Targets Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO473 ,CPU Targets Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO472 ,CPU Targets Byte Offset 472 " group.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479 ,CPU Targets Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO478 ,CPU Targets Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO477 ,CPU Targets Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO476 ,CPU Targets Byte Offset 476 " else hgroup.long 0x9C0++0x03 hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hgroup.long 0x9C4++0x03 hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hgroup.long 0x9C8++0x03 hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hgroup.long 0x9CC++0x03 hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hgroup.long 0x9D0++0x03 hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hgroup.long 0x9D4++0x03 hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hgroup.long 0x9D8++0x03 hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hgroup.long 0x9DC++0x03 hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483 ,CPU Targets Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO482 ,CPU Targets Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO481 ,CPU Targets Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO480 ,CPU Targets Byte Offset 480 " group.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487 ,CPU Targets Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO486 ,CPU Targets Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO485 ,CPU Targets Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO484 ,CPU Targets Byte Offset 484 " group.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491 ,CPU Targets Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO490 ,CPU Targets Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO489 ,CPU Targets Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO488 ,CPU Targets Byte Offset 488 " group.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495 ,CPU Targets Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO494 ,CPU Targets Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO493 ,CPU Targets Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO492 ,CPU Targets Byte Offset 492 " group.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499 ,CPU Targets Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO498 ,CPU Targets Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO497 ,CPU Targets Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO496 ,CPU Targets Byte Offset 496 " group.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503 ,CPU Targets Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO502 ,CPU Targets Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO501 ,CPU Targets Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO500 ,CPU Targets Byte Offset 500 " group.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507 ,CPU Targets Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO506 ,CPU Targets Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO505 ,CPU Targets Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO504 ,CPU Targets Byte Offset 504 " group.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511 ,CPU Targets Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO510 ,CPU Targets Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO509 ,CPU Targets Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO508 ,CPU Targets Byte Offset 508 " else hgroup.long 0x9E0++0x03 hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hgroup.long 0x9E4++0x03 hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hgroup.long 0x9E8++0x03 hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hgroup.long 0x9EC++0x03 hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hgroup.long 0x9F0++0x03 hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hgroup.long 0x9F4++0x03 hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hgroup.long 0x9F8++0x03 hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hgroup.long 0x9FC++0x03 hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515 ,CPU Targets Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO514 ,CPU Targets Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO513 ,CPU Targets Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO512 ,CPU Targets Byte Offset 512 " group.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519 ,CPU Targets Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO518 ,CPU Targets Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO517 ,CPU Targets Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO516 ,CPU Targets Byte Offset 516 " group.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523 ,CPU Targets Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO522 ,CPU Targets Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO521 ,CPU Targets Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO520 ,CPU Targets Byte Offset 520 " group.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527 ,CPU Targets Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO526 ,CPU Targets Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO525 ,CPU Targets Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO524 ,CPU Targets Byte Offset 524 " group.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531 ,CPU Targets Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO530 ,CPU Targets Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO529 ,CPU Targets Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO528 ,CPU Targets Byte Offset 528 " group.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535 ,CPU Targets Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO534 ,CPU Targets Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO533 ,CPU Targets Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO532 ,CPU Targets Byte Offset 532 " group.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539 ,CPU Targets Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO538 ,CPU Targets Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO537 ,CPU Targets Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO536 ,CPU Targets Byte Offset 536 " group.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543 ,CPU Targets Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO542 ,CPU Targets Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO541 ,CPU Targets Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO540 ,CPU Targets Byte Offset 540 " else hgroup.long 0xA00++0x03 hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hgroup.long 0xA04++0x03 hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hgroup.long 0xA08++0x03 hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hgroup.long 0xA0C++0x03 hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hgroup.long 0xA10++0x03 hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hgroup.long 0xA14++0x03 hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hgroup.long 0xA18++0x03 hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hgroup.long 0xA1C++0x03 hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547 ,CPU Targets Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO546 ,CPU Targets Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO545 ,CPU Targets Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO544 ,CPU Targets Byte Offset 544 " group.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551 ,CPU Targets Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO550 ,CPU Targets Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO549 ,CPU Targets Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO548 ,CPU Targets Byte Offset 548 " group.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555 ,CPU Targets Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO554 ,CPU Targets Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO553 ,CPU Targets Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO552 ,CPU Targets Byte Offset 552 " group.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559 ,CPU Targets Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO558 ,CPU Targets Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO557 ,CPU Targets Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO556 ,CPU Targets Byte Offset 556 " group.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563 ,CPU Targets Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO562 ,CPU Targets Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO561 ,CPU Targets Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO560 ,CPU Targets Byte Offset 560 " group.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567 ,CPU Targets Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO566 ,CPU Targets Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO565 ,CPU Targets Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO564 ,CPU Targets Byte Offset 564 " group.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571 ,CPU Targets Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO570 ,CPU Targets Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO569 ,CPU Targets Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO568 ,CPU Targets Byte Offset 568 " group.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575 ,CPU Targets Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO574 ,CPU Targets Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO573 ,CPU Targets Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO572 ,CPU Targets Byte Offset 572 " else hgroup.long 0xA20++0x03 hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hgroup.long 0xA24++0x03 hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hgroup.long 0xA28++0x03 hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hgroup.long 0xA2C++0x03 hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hgroup.long 0xA30++0x03 hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hgroup.long 0xA34++0x03 hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hgroup.long 0xA38++0x03 hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hgroup.long 0xA3C++0x03 hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579 ,CPU Targets Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO578 ,CPU Targets Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO577 ,CPU Targets Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO576 ,CPU Targets Byte Offset 576 " group.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583 ,CPU Targets Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO582 ,CPU Targets Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO581 ,CPU Targets Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO580 ,CPU Targets Byte Offset 580 " group.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587 ,CPU Targets Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO586 ,CPU Targets Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO585 ,CPU Targets Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO584 ,CPU Targets Byte Offset 584 " group.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591 ,CPU Targets Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO590 ,CPU Targets Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO589 ,CPU Targets Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO588 ,CPU Targets Byte Offset 588 " group.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595 ,CPU Targets Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO594 ,CPU Targets Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO593 ,CPU Targets Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO592 ,CPU Targets Byte Offset 592 " group.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599 ,CPU Targets Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO598 ,CPU Targets Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO597 ,CPU Targets Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO596 ,CPU Targets Byte Offset 596 " group.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603 ,CPU Targets Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO602 ,CPU Targets Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO601 ,CPU Targets Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO600 ,CPU Targets Byte Offset 600 " group.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607 ,CPU Targets Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO606 ,CPU Targets Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO605 ,CPU Targets Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO604 ,CPU Targets Byte Offset 604 " else hgroup.long 0xA40++0x03 hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hgroup.long 0xA44++0x03 hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hgroup.long 0xA48++0x03 hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hgroup.long 0xA4C++0x03 hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hgroup.long 0xA50++0x03 hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hgroup.long 0xA54++0x03 hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hgroup.long 0xA58++0x03 hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hgroup.long 0xA5C++0x03 hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611 ,CPU Targets Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO610 ,CPU Targets Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO609 ,CPU Targets Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO608 ,CPU Targets Byte Offset 608 " group.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615 ,CPU Targets Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO614 ,CPU Targets Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO613 ,CPU Targets Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO612 ,CPU Targets Byte Offset 612 " group.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619 ,CPU Targets Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO618 ,CPU Targets Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO617 ,CPU Targets Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO616 ,CPU Targets Byte Offset 616 " group.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623 ,CPU Targets Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO622 ,CPU Targets Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO621 ,CPU Targets Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO620 ,CPU Targets Byte Offset 620 " group.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627 ,CPU Targets Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO626 ,CPU Targets Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO625 ,CPU Targets Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO624 ,CPU Targets Byte Offset 624 " group.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631 ,CPU Targets Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO630 ,CPU Targets Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO629 ,CPU Targets Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO628 ,CPU Targets Byte Offset 628 " group.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635 ,CPU Targets Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO634 ,CPU Targets Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO633 ,CPU Targets Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO632 ,CPU Targets Byte Offset 632 " group.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639 ,CPU Targets Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO638 ,CPU Targets Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO637 ,CPU Targets Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO636 ,CPU Targets Byte Offset 636 " else hgroup.long 0xA60++0x03 hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hgroup.long 0xA64++0x03 hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hgroup.long 0xA68++0x03 hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hgroup.long 0xA6C++0x03 hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hgroup.long 0xA70++0x03 hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hgroup.long 0xA74++0x03 hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hgroup.long 0xA78++0x03 hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hgroup.long 0xA7C++0x03 hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643 ,CPU Targets Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO642 ,CPU Targets Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO641 ,CPU Targets Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO640 ,CPU Targets Byte Offset 640 " group.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647 ,CPU Targets Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO646 ,CPU Targets Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO645 ,CPU Targets Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO644 ,CPU Targets Byte Offset 644 " group.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651 ,CPU Targets Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO650 ,CPU Targets Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO649 ,CPU Targets Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO648 ,CPU Targets Byte Offset 648 " group.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655 ,CPU Targets Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO654 ,CPU Targets Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO653 ,CPU Targets Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO652 ,CPU Targets Byte Offset 652 " group.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659 ,CPU Targets Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO658 ,CPU Targets Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO657 ,CPU Targets Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO656 ,CPU Targets Byte Offset 656 " group.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663 ,CPU Targets Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO662 ,CPU Targets Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO661 ,CPU Targets Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO660 ,CPU Targets Byte Offset 660 " group.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667 ,CPU Targets Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO666 ,CPU Targets Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO665 ,CPU Targets Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO664 ,CPU Targets Byte Offset 664 " group.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671 ,CPU Targets Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO670 ,CPU Targets Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO669 ,CPU Targets Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO668 ,CPU Targets Byte Offset 668 " else hgroup.long 0xA80++0x03 hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hgroup.long 0xA84++0x03 hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hgroup.long 0xA88++0x03 hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hgroup.long 0xA8C++0x03 hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hgroup.long 0xA90++0x03 hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hgroup.long 0xA94++0x03 hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hgroup.long 0xA98++0x03 hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hgroup.long 0xA9C++0x03 hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675 ,CPU Targets Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO674 ,CPU Targets Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO673 ,CPU Targets Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO672 ,CPU Targets Byte Offset 672 " group.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679 ,CPU Targets Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO678 ,CPU Targets Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO677 ,CPU Targets Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO676 ,CPU Targets Byte Offset 676 " group.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683 ,CPU Targets Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO682 ,CPU Targets Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO681 ,CPU Targets Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO680 ,CPU Targets Byte Offset 680 " group.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687 ,CPU Targets Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO686 ,CPU Targets Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO685 ,CPU Targets Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO684 ,CPU Targets Byte Offset 684 " group.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691 ,CPU Targets Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO690 ,CPU Targets Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO689 ,CPU Targets Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO688 ,CPU Targets Byte Offset 688 " group.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695 ,CPU Targets Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO694 ,CPU Targets Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO693 ,CPU Targets Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO692 ,CPU Targets Byte Offset 692 " group.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699 ,CPU Targets Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO698 ,CPU Targets Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO697 ,CPU Targets Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO696 ,CPU Targets Byte Offset 696 " group.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703 ,CPU Targets Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO702 ,CPU Targets Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO701 ,CPU Targets Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO700 ,CPU Targets Byte Offset 700 " else hgroup.long 0xAA0++0x03 hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hgroup.long 0xAA4++0x03 hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hgroup.long 0xAA8++0x03 hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hgroup.long 0xAAC++0x03 hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hgroup.long 0xAB0++0x03 hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hgroup.long 0xAB4++0x03 hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hgroup.long 0xAB8++0x03 hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hgroup.long 0xABC++0x03 hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707 ,CPU Targets Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO706 ,CPU Targets Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO705 ,CPU Targets Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO704 ,CPU Targets Byte Offset 704 " group.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711 ,CPU Targets Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO710 ,CPU Targets Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO709 ,CPU Targets Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO708 ,CPU Targets Byte Offset 708 " group.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715 ,CPU Targets Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO714 ,CPU Targets Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO713 ,CPU Targets Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO712 ,CPU Targets Byte Offset 712 " group.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719 ,CPU Targets Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO718 ,CPU Targets Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO717 ,CPU Targets Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO716 ,CPU Targets Byte Offset 716 " group.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723 ,CPU Targets Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO722 ,CPU Targets Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO721 ,CPU Targets Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO720 ,CPU Targets Byte Offset 720 " group.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727 ,CPU Targets Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO726 ,CPU Targets Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO725 ,CPU Targets Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO724 ,CPU Targets Byte Offset 724 " group.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731 ,CPU Targets Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO730 ,CPU Targets Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO729 ,CPU Targets Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO728 ,CPU Targets Byte Offset 728 " group.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735 ,CPU Targets Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO734 ,CPU Targets Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO733 ,CPU Targets Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO732 ,CPU Targets Byte Offset 732 " else hgroup.long 0xAC0++0x03 hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hgroup.long 0xAC4++0x03 hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hgroup.long 0xAC8++0x03 hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hgroup.long 0xACC++0x03 hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hgroup.long 0xAD0++0x03 hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hgroup.long 0xAD4++0x03 hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hgroup.long 0xAD8++0x03 hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hgroup.long 0xADC++0x03 hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739 ,CPU Targets Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO738 ,CPU Targets Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO737 ,CPU Targets Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO736 ,CPU Targets Byte Offset 736 " group.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743 ,CPU Targets Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO742 ,CPU Targets Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO741 ,CPU Targets Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO740 ,CPU Targets Byte Offset 740 " group.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747 ,CPU Targets Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO746 ,CPU Targets Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO745 ,CPU Targets Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO744 ,CPU Targets Byte Offset 744 " group.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751 ,CPU Targets Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO750 ,CPU Targets Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO749 ,CPU Targets Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO748 ,CPU Targets Byte Offset 748 " group.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755 ,CPU Targets Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO754 ,CPU Targets Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO753 ,CPU Targets Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO752 ,CPU Targets Byte Offset 752 " group.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759 ,CPU Targets Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO758 ,CPU Targets Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO757 ,CPU Targets Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO756 ,CPU Targets Byte Offset 756 " group.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763 ,CPU Targets Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO762 ,CPU Targets Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO761 ,CPU Targets Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO760 ,CPU Targets Byte Offset 760 " group.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767 ,CPU Targets Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO766 ,CPU Targets Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO765 ,CPU Targets Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO764 ,CPU Targets Byte Offset 764 " else hgroup.long 0xAE0++0x03 hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hgroup.long 0xAE4++0x03 hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hgroup.long 0xAE8++0x03 hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hgroup.long 0xAEC++0x03 hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hgroup.long 0xAF0++0x03 hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hgroup.long 0xAF4++0x03 hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hgroup.long 0xAF8++0x03 hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hgroup.long 0xAFC++0x03 hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771 ,CPU Targets Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO770 ,CPU Targets Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO769 ,CPU Targets Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO768 ,CPU Targets Byte Offset 768 " group.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775 ,CPU Targets Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO774 ,CPU Targets Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO773 ,CPU Targets Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO772 ,CPU Targets Byte Offset 772 " group.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779 ,CPU Targets Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO778 ,CPU Targets Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO777 ,CPU Targets Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO776 ,CPU Targets Byte Offset 776 " group.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783 ,CPU Targets Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO782 ,CPU Targets Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO781 ,CPU Targets Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO780 ,CPU Targets Byte Offset 780 " group.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787 ,CPU Targets Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO786 ,CPU Targets Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO785 ,CPU Targets Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO784 ,CPU Targets Byte Offset 784 " group.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791 ,CPU Targets Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO790 ,CPU Targets Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO789 ,CPU Targets Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO788 ,CPU Targets Byte Offset 788 " group.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795 ,CPU Targets Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO794 ,CPU Targets Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO793 ,CPU Targets Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO792 ,CPU Targets Byte Offset 792 " group.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799 ,CPU Targets Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO798 ,CPU Targets Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO797 ,CPU Targets Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO796 ,CPU Targets Byte Offset 796 " else hgroup.long 0xB00++0x03 hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hgroup.long 0xB04++0x03 hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hgroup.long 0xB08++0x03 hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hgroup.long 0xB0C++0x03 hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hgroup.long 0xB10++0x03 hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hgroup.long 0xB14++0x03 hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hgroup.long 0xB18++0x03 hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hgroup.long 0xB1C++0x03 hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803 ,CPU Targets Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO802 ,CPU Targets Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO801 ,CPU Targets Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO800 ,CPU Targets Byte Offset 800 " group.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807 ,CPU Targets Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO806 ,CPU Targets Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO805 ,CPU Targets Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO804 ,CPU Targets Byte Offset 804 " group.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811 ,CPU Targets Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO810 ,CPU Targets Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO809 ,CPU Targets Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO808 ,CPU Targets Byte Offset 808 " group.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815 ,CPU Targets Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO814 ,CPU Targets Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO813 ,CPU Targets Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO812 ,CPU Targets Byte Offset 812 " group.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819 ,CPU Targets Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO818 ,CPU Targets Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO817 ,CPU Targets Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO816 ,CPU Targets Byte Offset 816 " group.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823 ,CPU Targets Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO822 ,CPU Targets Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO821 ,CPU Targets Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO820 ,CPU Targets Byte Offset 820 " group.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827 ,CPU Targets Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO826 ,CPU Targets Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO825 ,CPU Targets Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO824 ,CPU Targets Byte Offset 824 " group.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831 ,CPU Targets Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO830 ,CPU Targets Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO829 ,CPU Targets Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO828 ,CPU Targets Byte Offset 828 " else hgroup.long 0xB20++0x03 hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hgroup.long 0xB24++0x03 hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hgroup.long 0xB28++0x03 hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hgroup.long 0xB2C++0x03 hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hgroup.long 0xB30++0x03 hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hgroup.long 0xB34++0x03 hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hgroup.long 0xB38++0x03 hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hgroup.long 0xB3C++0x03 hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835 ,CPU Targets Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO834 ,CPU Targets Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO833 ,CPU Targets Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO832 ,CPU Targets Byte Offset 832 " group.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839 ,CPU Targets Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO838 ,CPU Targets Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO837 ,CPU Targets Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO836 ,CPU Targets Byte Offset 836 " group.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843 ,CPU Targets Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO842 ,CPU Targets Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO841 ,CPU Targets Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO840 ,CPU Targets Byte Offset 840 " group.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847 ,CPU Targets Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO846 ,CPU Targets Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO845 ,CPU Targets Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO844 ,CPU Targets Byte Offset 844 " group.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851 ,CPU Targets Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO850 ,CPU Targets Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO849 ,CPU Targets Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO848 ,CPU Targets Byte Offset 848 " group.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855 ,CPU Targets Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO854 ,CPU Targets Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO853 ,CPU Targets Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO852 ,CPU Targets Byte Offset 852 " group.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859 ,CPU Targets Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO858 ,CPU Targets Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO857 ,CPU Targets Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO856 ,CPU Targets Byte Offset 856 " group.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863 ,CPU Targets Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO862 ,CPU Targets Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO861 ,CPU Targets Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO860 ,CPU Targets Byte Offset 860 " else hgroup.long 0xB40++0x03 hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hgroup.long 0xB44++0x03 hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hgroup.long 0xB48++0x03 hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hgroup.long 0xB4C++0x03 hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hgroup.long 0xB50++0x03 hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hgroup.long 0xB54++0x03 hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hgroup.long 0xB58++0x03 hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hgroup.long 0xB5C++0x03 hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867 ,CPU Targets Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO866 ,CPU Targets Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO865 ,CPU Targets Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO864 ,CPU Targets Byte Offset 864 " group.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871 ,CPU Targets Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO870 ,CPU Targets Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO869 ,CPU Targets Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO868 ,CPU Targets Byte Offset 868 " group.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875 ,CPU Targets Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO874 ,CPU Targets Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO873 ,CPU Targets Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO872 ,CPU Targets Byte Offset 872 " group.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879 ,CPU Targets Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO878 ,CPU Targets Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO877 ,CPU Targets Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO876 ,CPU Targets Byte Offset 876 " group.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883 ,CPU Targets Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO882 ,CPU Targets Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO881 ,CPU Targets Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO880 ,CPU Targets Byte Offset 880 " group.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887 ,CPU Targets Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO886 ,CPU Targets Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO885 ,CPU Targets Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO884 ,CPU Targets Byte Offset 884 " group.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891 ,CPU Targets Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO890 ,CPU Targets Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO889 ,CPU Targets Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO888 ,CPU Targets Byte Offset 888 " group.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895 ,CPU Targets Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO894 ,CPU Targets Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO893 ,CPU Targets Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO892 ,CPU Targets Byte Offset 892 " else hgroup.long 0xB60++0x03 hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hgroup.long 0xB64++0x03 hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hgroup.long 0xB68++0x03 hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hgroup.long 0xB6C++0x03 hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hgroup.long 0xB70++0x03 hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hgroup.long 0xB74++0x03 hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hgroup.long 0xB78++0x03 hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hgroup.long 0xB7C++0x03 hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899 ,CPU Targets Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO898 ,CPU Targets Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO897 ,CPU Targets Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO896 ,CPU Targets Byte Offset 896 " group.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903 ,CPU Targets Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO902 ,CPU Targets Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO901 ,CPU Targets Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO900 ,CPU Targets Byte Offset 900 " group.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907 ,CPU Targets Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO906 ,CPU Targets Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO905 ,CPU Targets Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO904 ,CPU Targets Byte Offset 904 " group.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911 ,CPU Targets Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO910 ,CPU Targets Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO909 ,CPU Targets Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO908 ,CPU Targets Byte Offset 908 " group.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915 ,CPU Targets Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO914 ,CPU Targets Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO913 ,CPU Targets Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO912 ,CPU Targets Byte Offset 912 " group.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919 ,CPU Targets Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO918 ,CPU Targets Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO917 ,CPU Targets Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO916 ,CPU Targets Byte Offset 916 " group.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923 ,CPU Targets Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO922 ,CPU Targets Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO921 ,CPU Targets Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO920 ,CPU Targets Byte Offset 920 " group.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927 ,CPU Targets Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO926 ,CPU Targets Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO925 ,CPU Targets Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO924 ,CPU Targets Byte Offset 924 " else hgroup.long 0xB80++0x03 hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hgroup.long 0xB84++0x03 hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hgroup.long 0xB88++0x03 hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hgroup.long 0xB8C++0x03 hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hgroup.long 0xB90++0x03 hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hgroup.long 0xB94++0x03 hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hgroup.long 0xB98++0x03 hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hgroup.long 0xB9C++0x03 hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931 ,CPU Targets Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO930 ,CPU Targets Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO929 ,CPU Targets Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO928 ,CPU Targets Byte Offset 928 " group.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935 ,CPU Targets Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO934 ,CPU Targets Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO933 ,CPU Targets Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO932 ,CPU Targets Byte Offset 932 " group.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939 ,CPU Targets Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO938 ,CPU Targets Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO937 ,CPU Targets Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO936 ,CPU Targets Byte Offset 936 " group.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943 ,CPU Targets Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO942 ,CPU Targets Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO941 ,CPU Targets Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO940 ,CPU Targets Byte Offset 940 " group.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947 ,CPU Targets Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO946 ,CPU Targets Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO945 ,CPU Targets Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO944 ,CPU Targets Byte Offset 944 " group.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951 ,CPU Targets Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO950 ,CPU Targets Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO949 ,CPU Targets Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO948 ,CPU Targets Byte Offset 948 " group.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955 ,CPU Targets Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO954 ,CPU Targets Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO953 ,CPU Targets Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO952 ,CPU Targets Byte Offset 952 " group.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959 ,CPU Targets Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO958 ,CPU Targets Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO957 ,CPU Targets Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO956 ,CPU Targets Byte Offset 956 " else hgroup.long 0xBA0++0x03 hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hgroup.long 0xBA4++0x03 hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hgroup.long 0xBA8++0x03 hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hgroup.long 0xBAC++0x03 hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hgroup.long 0xBB0++0x03 hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hgroup.long 0xBB4++0x03 hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hgroup.long 0xBB8++0x03 hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hgroup.long 0xBBC++0x03 hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963 ,CPU Targets Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO962 ,CPU Targets Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO961 ,CPU Targets Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO960 ,CPU Targets Byte Offset 960 " group.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967 ,CPU Targets Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO966 ,CPU Targets Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO965 ,CPU Targets Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO964 ,CPU Targets Byte Offset 964 " group.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971 ,CPU Targets Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO970 ,CPU Targets Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO969 ,CPU Targets Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO968 ,CPU Targets Byte Offset 968 " group.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975 ,CPU Targets Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO974 ,CPU Targets Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO973 ,CPU Targets Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO972 ,CPU Targets Byte Offset 972 " group.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979 ,CPU Targets Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO978 ,CPU Targets Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO977 ,CPU Targets Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO976 ,CPU Targets Byte Offset 976 " group.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983 ,CPU Targets Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO982 ,CPU Targets Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO981 ,CPU Targets Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO980 ,CPU Targets Byte Offset 980 " group.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987 ,CPU Targets Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO986 ,CPU Targets Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO985 ,CPU Targets Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO984 ,CPU Targets Byte Offset 984 " group.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991 ,CPU Targets Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO990 ,CPU Targets Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO989 ,CPU Targets Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO988 ,CPU Targets Byte Offset 988 " else hgroup.long 0xBC0++0x03 hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hgroup.long 0xBC4++0x03 hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hgroup.long 0xBC8++0x03 hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hgroup.long 0xBCC++0x03 hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hgroup.long 0xBD0++0x03 hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hgroup.long 0xBD4++0x03 hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hgroup.long 0xBD8++0x03 hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hgroup.long 0xBDC++0x03 hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" endif else hgroup.long 0x800++0x03 hide.long 0x00 "GICD_ITARGETSR0 ,Interrupt Processor Targets Register 0 " hgroup.long 0x804++0x03 hide.long 0x00 "GICD_ITARGETSR1 ,Interrupt Processor Targets Register 1 " hgroup.long 0x808++0x03 hide.long 0x00 "GICD_ITARGETSR2 ,Interrupt Processor Targets Register 2 " hgroup.long 0x80C++0x03 hide.long 0x00 "GICD_ITARGETSR3 ,Interrupt Processor Targets Register 3 " hgroup.long 0x810++0x03 hide.long 0x00 "GICD_ITARGETSR4 ,Interrupt Processor Targets Register 4 " hgroup.long 0x814++0x03 hide.long 0x00 "GICD_ITARGETSR5 ,Interrupt Processor Targets Register 5 " hgroup.long 0x818++0x03 hide.long 0x00 "GICD_ITARGETSR6 ,Interrupt Processor Targets Register 6 " hgroup.long 0x81C++0x03 hide.long 0x00 "GICD_ITARGETSR7 ,Interrupt Processor Targets Register 7 " hgroup.long 0x820++0x03 hide.long 0x00 "GICD_ITARGETSR8 ,Interrupt Processor Targets Register 8 " hgroup.long 0x824++0x03 hide.long 0x00 "GICD_ITARGETSR9 ,Interrupt Processor Targets Register 9 " hgroup.long 0x828++0x03 hide.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 " hgroup.long 0x82C++0x03 hide.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 " hgroup.long 0x830++0x03 hide.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 " hgroup.long 0x834++0x03 hide.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 " hgroup.long 0x838++0x03 hide.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 " hgroup.long 0x83C++0x03 hide.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 " hgroup.long 0x840++0x03 hide.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 " hgroup.long 0x844++0x03 hide.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 " hgroup.long 0x848++0x03 hide.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 " hgroup.long 0x84C++0x03 hide.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 " hgroup.long 0x850++0x03 hide.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 " hgroup.long 0x854++0x03 hide.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 " hgroup.long 0x858++0x03 hide.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 " hgroup.long 0x85C++0x03 hide.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 " hgroup.long 0x860++0x03 hide.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 " hgroup.long 0x864++0x03 hide.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 " hgroup.long 0x868++0x03 hide.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 " hgroup.long 0x86C++0x03 hide.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 " hgroup.long 0x870++0x03 hide.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 " hgroup.long 0x874++0x03 hide.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 " hgroup.long 0x878++0x03 hide.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 " hgroup.long 0x87C++0x03 hide.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 " hgroup.long 0x880++0x03 hide.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 " hgroup.long 0x884++0x03 hide.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 " hgroup.long 0x888++0x03 hide.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 " hgroup.long 0x88C++0x03 hide.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 " hgroup.long 0x890++0x03 hide.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 " hgroup.long 0x894++0x03 hide.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 " hgroup.long 0x898++0x03 hide.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 " hgroup.long 0x89C++0x03 hide.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 " hgroup.long 0x8A0++0x03 hide.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 " hgroup.long 0x8A4++0x03 hide.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 " hgroup.long 0x8A8++0x03 hide.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 " hgroup.long 0x8AC++0x03 hide.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 " hgroup.long 0x8B0++0x03 hide.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 " hgroup.long 0x8B4++0x03 hide.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 " hgroup.long 0x8B8++0x03 hide.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 " hgroup.long 0x8BC++0x03 hide.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 " hgroup.long 0x8C0++0x03 hide.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 " hgroup.long 0x8C4++0x03 hide.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 " hgroup.long 0x8C8++0x03 hide.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 " hgroup.long 0x8CC++0x03 hide.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 " hgroup.long 0x8D0++0x03 hide.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 " hgroup.long 0x8D4++0x03 hide.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 " hgroup.long 0x8D8++0x03 hide.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 " hgroup.long 0x8DC++0x03 hide.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 " hgroup.long 0x8E0++0x03 hide.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 " hgroup.long 0x8E4++0x03 hide.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 " hgroup.long 0x8E8++0x03 hide.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 " hgroup.long 0x8EC++0x03 hide.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 " hgroup.long 0x8F0++0x03 hide.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 " hgroup.long 0x8F4++0x03 hide.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 " hgroup.long 0x8F8++0x03 hide.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 " hgroup.long 0x8FC++0x03 hide.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 " hgroup.long 0x900++0x03 hide.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 " hgroup.long 0x904++0x03 hide.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 " hgroup.long 0x908++0x03 hide.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 " hgroup.long 0x90C++0x03 hide.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 " hgroup.long 0x910++0x03 hide.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 " hgroup.long 0x914++0x03 hide.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 " hgroup.long 0x918++0x03 hide.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 " hgroup.long 0x91C++0x03 hide.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 " hgroup.long 0x920++0x03 hide.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 " hgroup.long 0x924++0x03 hide.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 " hgroup.long 0x928++0x03 hide.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 " hgroup.long 0x92C++0x03 hide.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 " hgroup.long 0x930++0x03 hide.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 " hgroup.long 0x934++0x03 hide.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 " hgroup.long 0x938++0x03 hide.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 " hgroup.long 0x93C++0x03 hide.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 " hgroup.long 0x940++0x03 hide.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 " hgroup.long 0x944++0x03 hide.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 " hgroup.long 0x948++0x03 hide.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 " hgroup.long 0x94C++0x03 hide.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 " hgroup.long 0x950++0x03 hide.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 " hgroup.long 0x954++0x03 hide.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 " hgroup.long 0x958++0x03 hide.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 " hgroup.long 0x95C++0x03 hide.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 " hgroup.long 0x960++0x03 hide.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 " hgroup.long 0x964++0x03 hide.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 " hgroup.long 0x968++0x03 hide.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 " hgroup.long 0x96C++0x03 hide.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 " hgroup.long 0x970++0x03 hide.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 " hgroup.long 0x974++0x03 hide.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 " hgroup.long 0x978++0x03 hide.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 " hgroup.long 0x97C++0x03 hide.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 " hgroup.long 0x980++0x03 hide.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 " hgroup.long 0x984++0x03 hide.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 " hgroup.long 0x988++0x03 hide.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 " hgroup.long 0x98C++0x03 hide.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 " hgroup.long 0x990++0x03 hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hgroup.long 0x994++0x03 hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hgroup.long 0x998++0x03 hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hgroup.long 0x99C++0x03 hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hgroup.long 0x9A0++0x03 hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hgroup.long 0x9A4++0x03 hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hgroup.long 0x9A8++0x03 hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hgroup.long 0x9AC++0x03 hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hgroup.long 0x9B0++0x03 hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hgroup.long 0x9B4++0x03 hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hgroup.long 0x9B8++0x03 hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hgroup.long 0x9BC++0x03 hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hgroup.long 0x9C0++0x03 hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hgroup.long 0x9C4++0x03 hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hgroup.long 0x9C8++0x03 hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hgroup.long 0x9CC++0x03 hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hgroup.long 0x9D0++0x03 hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hgroup.long 0x9D4++0x03 hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hgroup.long 0x9D8++0x03 hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hgroup.long 0x9DC++0x03 hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hgroup.long 0x9E0++0x03 hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hgroup.long 0x9E4++0x03 hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hgroup.long 0x9E8++0x03 hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hgroup.long 0x9EC++0x03 hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hgroup.long 0x9F0++0x03 hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hgroup.long 0x9F4++0x03 hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hgroup.long 0x9F8++0x03 hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hgroup.long 0x9FC++0x03 hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hgroup.long 0xA00++0x03 hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hgroup.long 0xA04++0x03 hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hgroup.long 0xA08++0x03 hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hgroup.long 0xA0C++0x03 hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hgroup.long 0xA10++0x03 hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hgroup.long 0xA14++0x03 hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hgroup.long 0xA18++0x03 hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hgroup.long 0xA1C++0x03 hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hgroup.long 0xA20++0x03 hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hgroup.long 0xA24++0x03 hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hgroup.long 0xA28++0x03 hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hgroup.long 0xA2C++0x03 hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hgroup.long 0xA30++0x03 hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hgroup.long 0xA34++0x03 hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hgroup.long 0xA38++0x03 hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hgroup.long 0xA3C++0x03 hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hgroup.long 0xA40++0x03 hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hgroup.long 0xA44++0x03 hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hgroup.long 0xA48++0x03 hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hgroup.long 0xA4C++0x03 hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hgroup.long 0xA50++0x03 hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hgroup.long 0xA54++0x03 hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hgroup.long 0xA58++0x03 hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hgroup.long 0xA5C++0x03 hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hgroup.long 0xA60++0x03 hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hgroup.long 0xA64++0x03 hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hgroup.long 0xA68++0x03 hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hgroup.long 0xA6C++0x03 hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hgroup.long 0xA70++0x03 hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hgroup.long 0xA74++0x03 hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hgroup.long 0xA78++0x03 hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hgroup.long 0xA7C++0x03 hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hgroup.long 0xA80++0x03 hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hgroup.long 0xA84++0x03 hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hgroup.long 0xA88++0x03 hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hgroup.long 0xA8C++0x03 hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hgroup.long 0xA90++0x03 hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hgroup.long 0xA94++0x03 hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hgroup.long 0xA98++0x03 hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hgroup.long 0xA9C++0x03 hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hgroup.long 0xAA0++0x03 hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hgroup.long 0xAA4++0x03 hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hgroup.long 0xAA8++0x03 hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hgroup.long 0xAAC++0x03 hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hgroup.long 0xAB0++0x03 hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hgroup.long 0xAB4++0x03 hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hgroup.long 0xAB8++0x03 hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hgroup.long 0xABC++0x03 hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hgroup.long 0xAC0++0x03 hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hgroup.long 0xAC4++0x03 hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hgroup.long 0xAC8++0x03 hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hgroup.long 0xACC++0x03 hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hgroup.long 0xAD0++0x03 hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hgroup.long 0xAD4++0x03 hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hgroup.long 0xAD8++0x03 hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hgroup.long 0xADC++0x03 hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hgroup.long 0xAE0++0x03 hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hgroup.long 0xAE4++0x03 hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hgroup.long 0xAE8++0x03 hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hgroup.long 0xAEC++0x03 hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hgroup.long 0xAF0++0x03 hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hgroup.long 0xAF4++0x03 hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hgroup.long 0xAF8++0x03 hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hgroup.long 0xAFC++0x03 hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hgroup.long 0xB00++0x03 hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hgroup.long 0xB04++0x03 hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hgroup.long 0xB08++0x03 hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hgroup.long 0xB0C++0x03 hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hgroup.long 0xB10++0x03 hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hgroup.long 0xB14++0x03 hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hgroup.long 0xB18++0x03 hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hgroup.long 0xB1C++0x03 hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hgroup.long 0xB20++0x03 hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hgroup.long 0xB24++0x03 hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hgroup.long 0xB28++0x03 hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hgroup.long 0xB2C++0x03 hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hgroup.long 0xB30++0x03 hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hgroup.long 0xB34++0x03 hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hgroup.long 0xB38++0x03 hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hgroup.long 0xB3C++0x03 hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hgroup.long 0xB40++0x03 hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hgroup.long 0xB44++0x03 hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hgroup.long 0xB48++0x03 hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hgroup.long 0xB4C++0x03 hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hgroup.long 0xB50++0x03 hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hgroup.long 0xB54++0x03 hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hgroup.long 0xB58++0x03 hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hgroup.long 0xB5C++0x03 hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hgroup.long 0xB60++0x03 hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hgroup.long 0xB64++0x03 hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hgroup.long 0xB68++0x03 hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hgroup.long 0xB6C++0x03 hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hgroup.long 0xB70++0x03 hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hgroup.long 0xB74++0x03 hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hgroup.long 0xB78++0x03 hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hgroup.long 0xB7C++0x03 hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hgroup.long 0xB80++0x03 hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hgroup.long 0xB84++0x03 hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hgroup.long 0xB88++0x03 hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hgroup.long 0xB8C++0x03 hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hgroup.long 0xB90++0x03 hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hgroup.long 0xB94++0x03 hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hgroup.long 0xB98++0x03 hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hgroup.long 0xB9C++0x03 hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hgroup.long 0xBA0++0x03 hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hgroup.long 0xBA4++0x03 hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hgroup.long 0xBA8++0x03 hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hgroup.long 0xBAC++0x03 hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hgroup.long 0xBB0++0x03 hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hgroup.long 0xBB4++0x03 hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hgroup.long 0xBB8++0x03 hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hgroup.long 0xBBC++0x03 hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hgroup.long 0xBC0++0x03 hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hgroup.long 0xBC4++0x03 hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hgroup.long 0xBC8++0x03 hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hgroup.long 0xBCC++0x03 hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hgroup.long 0xBD0++0x03 hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hgroup.long 0xBD4++0x03 hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hgroup.long 0xBD8++0x03 hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hgroup.long 0xBDC++0x03 hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" endif tree.end width 14. tree "Configuration Registers" rgroup.long 0xC00++0x03 line.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SGI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SGI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SGI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SGI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SGI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SGI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SGI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SGI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SGI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SGI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SGI)" "Level,Edge" group.long 0xC04++0x03 line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (PPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (PPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (PPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (PPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (PPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (PPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (PPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (PPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (PPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (PPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (PPI)" "Level,Edge" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1) group.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC08++0x03 hide.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" hgroup.long 0xC0C++0x03 hide.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2) group.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC10++0x03 hide.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" hgroup.long 0xC14++0x03 hide.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3) group.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC18++0x03 hide.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" hgroup.long 0xC1C++0x03 hide.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4) group.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC20++0x03 hide.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" hgroup.long 0xC24++0x03 hide.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5) group.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC28++0x03 hide.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" hgroup.long 0xC2C++0x03 hide.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6) group.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC30++0x03 hide.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" hgroup.long 0xC34++0x03 hide.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7) group.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC38++0x03 hide.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" hgroup.long 0xC3C++0x03 hide.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8) group.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC40++0x03 hide.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" hgroup.long 0xC44++0x03 hide.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9) group.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC48++0x03 hide.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" hgroup.long 0xC4C++0x03 hide.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA) group.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC50++0x03 hide.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" hgroup.long 0xC54++0x03 hide.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB) group.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC58++0x03 hide.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" hgroup.long 0xC5C++0x03 hide.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC) group.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC60++0x03 hide.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" hgroup.long 0xC64++0x03 hide.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD) group.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC68++0x03 hide.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" hgroup.long 0xC6C++0x03 hide.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE) group.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC70++0x03 hide.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" hgroup.long 0xC74++0x03 hide.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF) group.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC78++0x03 hide.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" hgroup.long 0xC7C++0x03 hide.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC80++0x03 hide.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" hgroup.long 0xC84++0x03 hide.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC88++0x03 hide.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" hgroup.long 0xC8C++0x03 hide.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC90++0x03 hide.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" hgroup.long 0xC94++0x03 hide.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC98++0x03 hide.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" hgroup.long 0xC9C++0x03 hide.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCA0++0x03 hide.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" hgroup.long 0xCA4++0x03 hide.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCA8++0x03 hide.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" hgroup.long 0xCAC++0x03 hide.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCB0++0x03 hide.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" hgroup.long 0xCB4++0x03 hide.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCB8++0x03 hide.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" hgroup.long 0xCBC++0x03 hide.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCC0++0x03 hide.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" hgroup.long 0xCC4++0x03 hide.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCC8++0x03 hide.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" hgroup.long 0xCCC++0x03 hide.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCD0++0x03 hide.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" hgroup.long 0xCD4++0x03 hide.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCD8++0x03 hide.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" hgroup.long 0xCDC++0x03 hide.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCE0++0x03 hide.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" hgroup.long 0xCE4++0x03 hide.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCE8++0x03 hide.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" hgroup.long 0xCEC++0x03 hide.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCF0++0x03 hide.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" hgroup.long 0xCF4++0x03 hide.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" endif tree.end width 17. tree "Interrupt Group Modifier Registers" hgroup.long 0x0D00++0x03 hide.long 0x0 "GICD_IGRPMODR0,Interrupt Group Modifier Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D00))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)) group.long 0x0D04++0x03 line.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1" bitfld.long 0x00 31. " GMB63 ,Group Modifier Bit 63" "0,1" bitfld.long 0x00 30. " GMB62 ,Group Modifier Bit 62" "0,1" bitfld.long 0x00 29. " GMB61 ,Group Modifier Bit 61" "0,1" textline " " bitfld.long 0x00 28. " GMB60 ,Group Modifier Bit 60" "0,1" bitfld.long 0x00 27. " GMB59 ,Group Modifier Bit 59" "0,1" bitfld.long 0x00 26. " GMB58 ,Group Modifier Bit 58" "0,1" textline " " bitfld.long 0x00 25. " GMB57 ,Group Modifier Bit 57" "0,1" bitfld.long 0x00 24. " GMB56 ,Group Modifier Bit 56" "0,1" bitfld.long 0x00 23. " GMB55 ,Group Modifier Bit 55" "0,1" textline " " bitfld.long 0x00 22. " GMB54 ,Group Modifier Bit 54" "0,1" bitfld.long 0x00 21. " GMB53 ,Group Modifier Bit 53" "0,1" bitfld.long 0x00 20. " GMB52 ,Group Modifier Bit 52" "0,1" textline " " bitfld.long 0x00 19. " GMB51 ,Group Modifier Bit 51" "0,1" bitfld.long 0x00 18. " GMB50 ,Group Modifier Bit 50" "0,1" bitfld.long 0x00 17. " GMB49 ,Group Modifier Bit 49" "0,1" textline " " bitfld.long 0x00 16. " GMB48 ,Group Modifier Bit 48" "0,1" bitfld.long 0x00 15. " GMB47 ,Group Modifier Bit 47" "0,1" bitfld.long 0x00 14. " GMB46 ,Group Modifier Bit 46" "0,1" textline " " bitfld.long 0x00 13. " GMB45 ,Group Modifier Bit 45" "0,1" bitfld.long 0x00 12. " GMB44 ,Group Modifier Bit 44" "0,1" bitfld.long 0x00 11. " GMB43 ,Group Modifier Bit 43" "0,1" textline " " bitfld.long 0x00 10. " GMB42 ,Group Modifier Bit 42" "0,1" bitfld.long 0x00 9. " GMB41 ,Group Modifier Bit 41" "0,1" bitfld.long 0x00 8. " GMB40 ,Group Modifier Bit 40" "0,1" textline " " bitfld.long 0x00 7. " GMB39 ,Group Modifier Bit 39" "0,1" bitfld.long 0x00 6. " GMB38 ,Group Modifier Bit 38" "0,1" bitfld.long 0x00 5. " GMB37 ,Group Modifier Bit 37" "0,1" textline " " bitfld.long 0x00 4. " GMB36 ,Group Modifier Bit 36" "0,1" bitfld.long 0x00 3. " GMB35 ,Group Modifier Bit 35" "0,1" bitfld.long 0x00 2. " GMB34 ,Group Modifier Bit 34" "0,1" textline " " bitfld.long 0x00 1. " GMB33 ,Group Modifier Bit 33" "0,1" bitfld.long 0x00 0. " GMB32 ,Group Modifier Bit 32" "0,1" else hgroup.long 0x0D04++0x03 hide.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D08))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)) group.long 0x0D08++0x03 line.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2" bitfld.long 0x00 31. " GMB95 ,Group Modifier Bit 95" "0,1" bitfld.long 0x00 30. " GMB94 ,Group Modifier Bit 94" "0,1" bitfld.long 0x00 29. " GMB93 ,Group Modifier Bit 93" "0,1" textline " " bitfld.long 0x00 28. " GMB92 ,Group Modifier Bit 92" "0,1" bitfld.long 0x00 27. " GMB91 ,Group Modifier Bit 91" "0,1" bitfld.long 0x00 26. " GMB90 ,Group Modifier Bit 90" "0,1" textline " " bitfld.long 0x00 25. " GMB89 ,Group Modifier Bit 89" "0,1" bitfld.long 0x00 24. " GMB88 ,Group Modifier Bit 88" "0,1" bitfld.long 0x00 23. " GMB87 ,Group Modifier Bit 87" "0,1" textline " " bitfld.long 0x00 22. " GMB86 ,Group Modifier Bit 86" "0,1" bitfld.long 0x00 21. " GMB85 ,Group Modifier Bit 85" "0,1" bitfld.long 0x00 20. " GMB84 ,Group Modifier Bit 84" "0,1" textline " " bitfld.long 0x00 19. " GMB83 ,Group Modifier Bit 83" "0,1" bitfld.long 0x00 18. " GMB82 ,Group Modifier Bit 82" "0,1" bitfld.long 0x00 17. " GMB81 ,Group Modifier Bit 81" "0,1" textline " " bitfld.long 0x00 16. " GMB80 ,Group Modifier Bit 80" "0,1" bitfld.long 0x00 15. " GMB79 ,Group Modifier Bit 79" "0,1" bitfld.long 0x00 14. " GMB78 ,Group Modifier Bit 78" "0,1" textline " " bitfld.long 0x00 13. " GMB77 ,Group Modifier Bit 77" "0,1" bitfld.long 0x00 12. " GMB76 ,Group Modifier Bit 76" "0,1" bitfld.long 0x00 11. " GMB75 ,Group Modifier Bit 75" "0,1" textline " " bitfld.long 0x00 10. " GMB74 ,Group Modifier Bit 74" "0,1" bitfld.long 0x00 9. " GMB73 ,Group Modifier Bit 73" "0,1" bitfld.long 0x00 8. " GMB72 ,Group Modifier Bit 72" "0,1" textline " " bitfld.long 0x00 7. " GMB71 ,Group Modifier Bit 71" "0,1" bitfld.long 0x00 6. " GMB70 ,Group Modifier Bit 70" "0,1" bitfld.long 0x00 5. " GMB69 ,Group Modifier Bit 69" "0,1" textline " " bitfld.long 0x00 4. " GMB68 ,Group Modifier Bit 68" "0,1" bitfld.long 0x00 3. " GMB67 ,Group Modifier Bit 67" "0,1" bitfld.long 0x00 2. " GMB66 ,Group Modifier Bit 66" "0,1" textline " " bitfld.long 0x00 1. " GMB65 ,Group Modifier Bit 65" "0,1" bitfld.long 0x00 0. " GMB64 ,Group Modifier Bit 64" "0,1" else hgroup.long 0x0D08++0x03 hide.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D0C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)) group.long 0x0D0C++0x03 line.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3" bitfld.long 0x00 31. " GMB127 ,Group Modifier Bit 127" "0,1" bitfld.long 0x00 30. " GMB126 ,Group Modifier Bit 126" "0,1" bitfld.long 0x00 29. " GMB125 ,Group Modifier Bit 125" "0,1" textline " " bitfld.long 0x00 28. " GMB124 ,Group Modifier Bit 124" "0,1" bitfld.long 0x00 27. " GMB123 ,Group Modifier Bit 123" "0,1" bitfld.long 0x00 26. " GMB122 ,Group Modifier Bit 122" "0,1" textline " " bitfld.long 0x00 25. " GMB121 ,Group Modifier Bit 121" "0,1" bitfld.long 0x00 24. " GMB120 ,Group Modifier Bit 120" "0,1" bitfld.long 0x00 23. " GMB119 ,Group Modifier Bit 119" "0,1" textline " " bitfld.long 0x00 22. " GMB118 ,Group Modifier Bit 118" "0,1" bitfld.long 0x00 21. " GMB117 ,Group Modifier Bit 117" "0,1" bitfld.long 0x00 20. " GMB116 ,Group Modifier Bit 116" "0,1" textline " " bitfld.long 0x00 19. " GMB115 ,Group Modifier Bit 115" "0,1" bitfld.long 0x00 18. " GMB114 ,Group Modifier Bit 114" "0,1" bitfld.long 0x00 17. " GMB113 ,Group Modifier Bit 113" "0,1" textline " " bitfld.long 0x00 16. " GMB112 ,Group Modifier Bit 112" "0,1" bitfld.long 0x00 15. " GMB111 ,Group Modifier Bit 111" "0,1" bitfld.long 0x00 14. " GMB110 ,Group Modifier Bit 110" "0,1" textline " " bitfld.long 0x00 13. " GMB109 ,Group Modifier Bit 109" "0,1" bitfld.long 0x00 12. " GMB108 ,Group Modifier Bit 108" "0,1" bitfld.long 0x00 11. " GMB107 ,Group Modifier Bit 107" "0,1" textline " " bitfld.long 0x00 10. " GMB106 ,Group Modifier Bit 106" "0,1" bitfld.long 0x00 9. " GMB105 ,Group Modifier Bit 105" "0,1" bitfld.long 0x00 8. " GMB104 ,Group Modifier Bit 104" "0,1" textline " " bitfld.long 0x00 7. " GMB103 ,Group Modifier Bit 103" "0,1" bitfld.long 0x00 6. " GMB102 ,Group Modifier Bit 102" "0,1" bitfld.long 0x00 5. " GMB101 ,Group Modifier Bit 101" "0,1" textline " " bitfld.long 0x00 4. " GMB100 ,Group Modifier Bit 100" "0,1" bitfld.long 0x00 3. " GMB99 ,Group Modifier Bit 99" "0,1" bitfld.long 0x00 2. " GMB98 ,Group Modifier Bit 98" "0,1" textline " " bitfld.long 0x00 1. " GMB97 ,Group Modifier Bit 97" "0,1" bitfld.long 0x00 0. " GMB96 ,Group Modifier Bit 96" "0,1" else hgroup.long 0x0D0C++0x03 hide.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D10))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)) group.long 0x0D10++0x03 line.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4" bitfld.long 0x00 31. " GMB159 ,Group Modifier Bit 159" "0,1" bitfld.long 0x00 30. " GMB158 ,Group Modifier Bit 158" "0,1" bitfld.long 0x00 29. " GMB157 ,Group Modifier Bit 157" "0,1" textline " " bitfld.long 0x00 28. " GMB156 ,Group Modifier Bit 156" "0,1" bitfld.long 0x00 27. " GMB155 ,Group Modifier Bit 155" "0,1" bitfld.long 0x00 26. " GMB154 ,Group Modifier Bit 154" "0,1" textline " " bitfld.long 0x00 25. " GMB153 ,Group Modifier Bit 153" "0,1" bitfld.long 0x00 24. " GMB152 ,Group Modifier Bit 152" "0,1" bitfld.long 0x00 23. " GMB151 ,Group Modifier Bit 151" "0,1" textline " " bitfld.long 0x00 22. " GMB150 ,Group Modifier Bit 150" "0,1" bitfld.long 0x00 21. " GMB149 ,Group Modifier Bit 149" "0,1" bitfld.long 0x00 20. " GMB148 ,Group Modifier Bit 148" "0,1" textline " " bitfld.long 0x00 19. " GMB147 ,Group Modifier Bit 147" "0,1" bitfld.long 0x00 18. " GMB146 ,Group Modifier Bit 146" "0,1" bitfld.long 0x00 17. " GMB145 ,Group Modifier Bit 145" "0,1" textline " " bitfld.long 0x00 16. " GMB144 ,Group Modifier Bit 144" "0,1" bitfld.long 0x00 15. " GMB143 ,Group Modifier Bit 143" "0,1" bitfld.long 0x00 14. " GMB142 ,Group Modifier Bit 142" "0,1" textline " " bitfld.long 0x00 13. " GMB141 ,Group Modifier Bit 141" "0,1" bitfld.long 0x00 12. " GMB140 ,Group Modifier Bit 140" "0,1" bitfld.long 0x00 11. " GMB139 ,Group Modifier Bit 139" "0,1" textline " " bitfld.long 0x00 10. " GMB138 ,Group Modifier Bit 138" "0,1" bitfld.long 0x00 9. " GMB137 ,Group Modifier Bit 137" "0,1" bitfld.long 0x00 8. " GMB136 ,Group Modifier Bit 136" "0,1" textline " " bitfld.long 0x00 7. " GMB135 ,Group Modifier Bit 135" "0,1" bitfld.long 0x00 6. " GMB134 ,Group Modifier Bit 134" "0,1" bitfld.long 0x00 5. " GMB133 ,Group Modifier Bit 133" "0,1" textline " " bitfld.long 0x00 4. " GMB132 ,Group Modifier Bit 132" "0,1" bitfld.long 0x00 3. " GMB131 ,Group Modifier Bit 131" "0,1" bitfld.long 0x00 2. " GMB130 ,Group Modifier Bit 130" "0,1" textline " " bitfld.long 0x00 1. " GMB129 ,Group Modifier Bit 129" "0,1" bitfld.long 0x00 0. " GMB128 ,Group Modifier Bit 128" "0,1" else hgroup.long 0x0D10++0x03 hide.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D14))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)) group.long 0x0D14++0x03 line.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5" bitfld.long 0x00 31. " GMB191 ,Group Modifier Bit 191" "0,1" bitfld.long 0x00 30. " GMB190 ,Group Modifier Bit 190" "0,1" bitfld.long 0x00 29. " GMB189 ,Group Modifier Bit 189" "0,1" textline " " bitfld.long 0x00 28. " GMB188 ,Group Modifier Bit 188" "0,1" bitfld.long 0x00 27. " GMB187 ,Group Modifier Bit 187" "0,1" bitfld.long 0x00 26. " GMB186 ,Group Modifier Bit 186" "0,1" textline " " bitfld.long 0x00 25. " GMB185 ,Group Modifier Bit 185" "0,1" bitfld.long 0x00 24. " GMB184 ,Group Modifier Bit 184" "0,1" bitfld.long 0x00 23. " GMB183 ,Group Modifier Bit 183" "0,1" textline " " bitfld.long 0x00 22. " GMB182 ,Group Modifier Bit 182" "0,1" bitfld.long 0x00 21. " GMB181 ,Group Modifier Bit 181" "0,1" bitfld.long 0x00 20. " GMB180 ,Group Modifier Bit 180" "0,1" textline " " bitfld.long 0x00 19. " GMB179 ,Group Modifier Bit 179" "0,1" bitfld.long 0x00 18. " GMB178 ,Group Modifier Bit 178" "0,1" bitfld.long 0x00 17. " GMB177 ,Group Modifier Bit 177" "0,1" textline " " bitfld.long 0x00 16. " GMB176 ,Group Modifier Bit 176" "0,1" bitfld.long 0x00 15. " GMB175 ,Group Modifier Bit 175" "0,1" bitfld.long 0x00 14. " GMB174 ,Group Modifier Bit 174" "0,1" textline " " bitfld.long 0x00 13. " GMB173 ,Group Modifier Bit 173" "0,1" bitfld.long 0x00 12. " GMB172 ,Group Modifier Bit 172" "0,1" bitfld.long 0x00 11. " GMB171 ,Group Modifier Bit 171" "0,1" textline " " bitfld.long 0x00 10. " GMB170 ,Group Modifier Bit 170" "0,1" bitfld.long 0x00 9. " GMB169 ,Group Modifier Bit 169" "0,1" bitfld.long 0x00 8. " GMB168 ,Group Modifier Bit 168" "0,1" textline " " bitfld.long 0x00 7. " GMB167 ,Group Modifier Bit 167" "0,1" bitfld.long 0x00 6. " GMB166 ,Group Modifier Bit 166" "0,1" bitfld.long 0x00 5. " GMB165 ,Group Modifier Bit 165" "0,1" textline " " bitfld.long 0x00 4. " GMB164 ,Group Modifier Bit 164" "0,1" bitfld.long 0x00 3. " GMB163 ,Group Modifier Bit 163" "0,1" bitfld.long 0x00 2. " GMB162 ,Group Modifier Bit 162" "0,1" textline " " bitfld.long 0x00 1. " GMB161 ,Group Modifier Bit 161" "0,1" bitfld.long 0x00 0. " GMB160 ,Group Modifier Bit 160" "0,1" else hgroup.long 0x0D14++0x03 hide.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D18))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)) group.long 0x0D18++0x03 line.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6" bitfld.long 0x00 31. " GMB223 ,Group Modifier Bit 223" "0,1" bitfld.long 0x00 30. " GMB222 ,Group Modifier Bit 222" "0,1" bitfld.long 0x00 29. " GMB221 ,Group Modifier Bit 221" "0,1" textline " " bitfld.long 0x00 28. " GMB220 ,Group Modifier Bit 220" "0,1" bitfld.long 0x00 27. " GMB219 ,Group Modifier Bit 219" "0,1" bitfld.long 0x00 26. " GMB218 ,Group Modifier Bit 218" "0,1" textline " " bitfld.long 0x00 25. " GMB217 ,Group Modifier Bit 217" "0,1" bitfld.long 0x00 24. " GMB216 ,Group Modifier Bit 216" "0,1" bitfld.long 0x00 23. " GMB215 ,Group Modifier Bit 215" "0,1" textline " " bitfld.long 0x00 22. " GMB214 ,Group Modifier Bit 214" "0,1" bitfld.long 0x00 21. " GMB213 ,Group Modifier Bit 213" "0,1" bitfld.long 0x00 20. " GMB212 ,Group Modifier Bit 212" "0,1" textline " " bitfld.long 0x00 19. " GMB211 ,Group Modifier Bit 211" "0,1" bitfld.long 0x00 18. " GMB210 ,Group Modifier Bit 210" "0,1" bitfld.long 0x00 17. " GMB209 ,Group Modifier Bit 209" "0,1" textline " " bitfld.long 0x00 16. " GMB208 ,Group Modifier Bit 208" "0,1" bitfld.long 0x00 15. " GMB207 ,Group Modifier Bit 207" "0,1" bitfld.long 0x00 14. " GMB206 ,Group Modifier Bit 206" "0,1" textline " " bitfld.long 0x00 13. " GMB205 ,Group Modifier Bit 205" "0,1" bitfld.long 0x00 12. " GMB204 ,Group Modifier Bit 204" "0,1" bitfld.long 0x00 11. " GMB203 ,Group Modifier Bit 203" "0,1" textline " " bitfld.long 0x00 10. " GMB202 ,Group Modifier Bit 202" "0,1" bitfld.long 0x00 9. " GMB201 ,Group Modifier Bit 201" "0,1" bitfld.long 0x00 8. " GMB200 ,Group Modifier Bit 200" "0,1" textline " " bitfld.long 0x00 7. " GMB199 ,Group Modifier Bit 199" "0,1" bitfld.long 0x00 6. " GMB198 ,Group Modifier Bit 198" "0,1" bitfld.long 0x00 5. " GMB197 ,Group Modifier Bit 197" "0,1" textline " " bitfld.long 0x00 4. " GMB196 ,Group Modifier Bit 196" "0,1" bitfld.long 0x00 3. " GMB195 ,Group Modifier Bit 195" "0,1" bitfld.long 0x00 2. " GMB194 ,Group Modifier Bit 194" "0,1" textline " " bitfld.long 0x00 1. " GMB193 ,Group Modifier Bit 193" "0,1" bitfld.long 0x00 0. " GMB192 ,Group Modifier Bit 192" "0,1" else hgroup.long 0x0D18++0x03 hide.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D1C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)) group.long 0x0D1C++0x03 line.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7" bitfld.long 0x00 31. " GMB255 ,Group Modifier Bit 255" "0,1" bitfld.long 0x00 30. " GMB254 ,Group Modifier Bit 254" "0,1" bitfld.long 0x00 29. " GMB253 ,Group Modifier Bit 253" "0,1" textline " " bitfld.long 0x00 28. " GMB252 ,Group Modifier Bit 252" "0,1" bitfld.long 0x00 27. " GMB251 ,Group Modifier Bit 251" "0,1" bitfld.long 0x00 26. " GMB250 ,Group Modifier Bit 250" "0,1" textline " " bitfld.long 0x00 25. " GMB249 ,Group Modifier Bit 249" "0,1" bitfld.long 0x00 24. " GMB248 ,Group Modifier Bit 248" "0,1" bitfld.long 0x00 23. " GMB247 ,Group Modifier Bit 247" "0,1" textline " " bitfld.long 0x00 22. " GMB246 ,Group Modifier Bit 246" "0,1" bitfld.long 0x00 21. " GMB245 ,Group Modifier Bit 245" "0,1" bitfld.long 0x00 20. " GMB244 ,Group Modifier Bit 244" "0,1" textline " " bitfld.long 0x00 19. " GMB243 ,Group Modifier Bit 243" "0,1" bitfld.long 0x00 18. " GMB242 ,Group Modifier Bit 242" "0,1" bitfld.long 0x00 17. " GMB241 ,Group Modifier Bit 241" "0,1" textline " " bitfld.long 0x00 16. " GMB240 ,Group Modifier Bit 240" "0,1" bitfld.long 0x00 15. " GMB239 ,Group Modifier Bit 239" "0,1" bitfld.long 0x00 14. " GMB238 ,Group Modifier Bit 238" "0,1" textline " " bitfld.long 0x00 13. " GMB237 ,Group Modifier Bit 237" "0,1" bitfld.long 0x00 12. " GMB236 ,Group Modifier Bit 236" "0,1" bitfld.long 0x00 11. " GMB235 ,Group Modifier Bit 235" "0,1" textline " " bitfld.long 0x00 10. " GMB234 ,Group Modifier Bit 234" "0,1" bitfld.long 0x00 9. " GMB233 ,Group Modifier Bit 233" "0,1" bitfld.long 0x00 8. " GMB232 ,Group Modifier Bit 232" "0,1" textline " " bitfld.long 0x00 7. " GMB231 ,Group Modifier Bit 231" "0,1" bitfld.long 0x00 6. " GMB230 ,Group Modifier Bit 230" "0,1" bitfld.long 0x00 5. " GMB229 ,Group Modifier Bit 229" "0,1" textline " " bitfld.long 0x00 4. " GMB228 ,Group Modifier Bit 228" "0,1" bitfld.long 0x00 3. " GMB227 ,Group Modifier Bit 227" "0,1" bitfld.long 0x00 2. " GMB226 ,Group Modifier Bit 226" "0,1" textline " " bitfld.long 0x00 1. " GMB225 ,Group Modifier Bit 225" "0,1" bitfld.long 0x00 0. " GMB224 ,Group Modifier Bit 224" "0,1" else hgroup.long 0x0D1C++0x03 hide.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D20))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)) group.long 0x0D20++0x03 line.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8" bitfld.long 0x00 31. " GMB287 ,Group Modifier Bit 287" "0,1" bitfld.long 0x00 30. " GMB286 ,Group Modifier Bit 286" "0,1" bitfld.long 0x00 29. " GMB285 ,Group Modifier Bit 285" "0,1" textline " " bitfld.long 0x00 28. " GMB284 ,Group Modifier Bit 284" "0,1" bitfld.long 0x00 27. " GMB283 ,Group Modifier Bit 283" "0,1" bitfld.long 0x00 26. " GMB282 ,Group Modifier Bit 282" "0,1" textline " " bitfld.long 0x00 25. " GMB281 ,Group Modifier Bit 281" "0,1" bitfld.long 0x00 24. " GMB280 ,Group Modifier Bit 280" "0,1" bitfld.long 0x00 23. " GMB279 ,Group Modifier Bit 279" "0,1" textline " " bitfld.long 0x00 22. " GMB278 ,Group Modifier Bit 278" "0,1" bitfld.long 0x00 21. " GMB277 ,Group Modifier Bit 277" "0,1" bitfld.long 0x00 20. " GMB276 ,Group Modifier Bit 276" "0,1" textline " " bitfld.long 0x00 19. " GMB275 ,Group Modifier Bit 275" "0,1" bitfld.long 0x00 18. " GMB274 ,Group Modifier Bit 274" "0,1" bitfld.long 0x00 17. " GMB273 ,Group Modifier Bit 273" "0,1" textline " " bitfld.long 0x00 16. " GMB272 ,Group Modifier Bit 272" "0,1" bitfld.long 0x00 15. " GMB271 ,Group Modifier Bit 271" "0,1" bitfld.long 0x00 14. " GMB270 ,Group Modifier Bit 270" "0,1" textline " " bitfld.long 0x00 13. " GMB269 ,Group Modifier Bit 269" "0,1" bitfld.long 0x00 12. " GMB268 ,Group Modifier Bit 268" "0,1" bitfld.long 0x00 11. " GMB267 ,Group Modifier Bit 267" "0,1" textline " " bitfld.long 0x00 10. " GMB266 ,Group Modifier Bit 266" "0,1" bitfld.long 0x00 9. " GMB265 ,Group Modifier Bit 265" "0,1" bitfld.long 0x00 8. " GMB264 ,Group Modifier Bit 264" "0,1" textline " " bitfld.long 0x00 7. " GMB263 ,Group Modifier Bit 263" "0,1" bitfld.long 0x00 6. " GMB262 ,Group Modifier Bit 262" "0,1" bitfld.long 0x00 5. " GMB261 ,Group Modifier Bit 261" "0,1" textline " " bitfld.long 0x00 4. " GMB260 ,Group Modifier Bit 260" "0,1" bitfld.long 0x00 3. " GMB259 ,Group Modifier Bit 259" "0,1" bitfld.long 0x00 2. " GMB258 ,Group Modifier Bit 258" "0,1" textline " " bitfld.long 0x00 1. " GMB257 ,Group Modifier Bit 257" "0,1" bitfld.long 0x00 0. " GMB256 ,Group Modifier Bit 256" "0,1" else hgroup.long 0x0D20++0x03 hide.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D24))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)) group.long 0x0D24++0x03 line.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9" bitfld.long 0x00 31. " GMB319 ,Group Modifier Bit 319" "0,1" bitfld.long 0x00 30. " GMB318 ,Group Modifier Bit 318" "0,1" bitfld.long 0x00 29. " GMB317 ,Group Modifier Bit 317" "0,1" textline " " bitfld.long 0x00 28. " GMB316 ,Group Modifier Bit 316" "0,1" bitfld.long 0x00 27. " GMB315 ,Group Modifier Bit 315" "0,1" bitfld.long 0x00 26. " GMB314 ,Group Modifier Bit 314" "0,1" textline " " bitfld.long 0x00 25. " GMB313 ,Group Modifier Bit 313" "0,1" bitfld.long 0x00 24. " GMB312 ,Group Modifier Bit 312" "0,1" bitfld.long 0x00 23. " GMB311 ,Group Modifier Bit 311" "0,1" textline " " bitfld.long 0x00 22. " GMB310 ,Group Modifier Bit 310" "0,1" bitfld.long 0x00 21. " GMB309 ,Group Modifier Bit 309" "0,1" bitfld.long 0x00 20. " GMB308 ,Group Modifier Bit 308" "0,1" textline " " bitfld.long 0x00 19. " GMB307 ,Group Modifier Bit 307" "0,1" bitfld.long 0x00 18. " GMB306 ,Group Modifier Bit 306" "0,1" bitfld.long 0x00 17. " GMB305 ,Group Modifier Bit 305" "0,1" textline " " bitfld.long 0x00 16. " GMB304 ,Group Modifier Bit 304" "0,1" bitfld.long 0x00 15. " GMB303 ,Group Modifier Bit 303" "0,1" bitfld.long 0x00 14. " GMB302 ,Group Modifier Bit 302" "0,1" textline " " bitfld.long 0x00 13. " GMB301 ,Group Modifier Bit 301" "0,1" bitfld.long 0x00 12. " GMB300 ,Group Modifier Bit 300" "0,1" bitfld.long 0x00 11. " GMB299 ,Group Modifier Bit 299" "0,1" textline " " bitfld.long 0x00 10. " GMB298 ,Group Modifier Bit 298" "0,1" bitfld.long 0x00 9. " GMB297 ,Group Modifier Bit 297" "0,1" bitfld.long 0x00 8. " GMB296 ,Group Modifier Bit 296" "0,1" textline " " bitfld.long 0x00 7. " GMB295 ,Group Modifier Bit 295" "0,1" bitfld.long 0x00 6. " GMB294 ,Group Modifier Bit 294" "0,1" bitfld.long 0x00 5. " GMB293 ,Group Modifier Bit 293" "0,1" textline " " bitfld.long 0x00 4. " GMB292 ,Group Modifier Bit 292" "0,1" bitfld.long 0x00 3. " GMB291 ,Group Modifier Bit 291" "0,1" bitfld.long 0x00 2. " GMB290 ,Group Modifier Bit 290" "0,1" textline " " bitfld.long 0x00 1. " GMB289 ,Group Modifier Bit 289" "0,1" bitfld.long 0x00 0. " GMB288 ,Group Modifier Bit 288" "0,1" else hgroup.long 0x0D24++0x03 hide.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D28))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)) group.long 0x0D28++0x03 line.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10" bitfld.long 0x00 31. " GMB351 ,Group Modifier Bit 351" "0,1" bitfld.long 0x00 30. " GMB350 ,Group Modifier Bit 350" "0,1" bitfld.long 0x00 29. " GMB349 ,Group Modifier Bit 349" "0,1" textline " " bitfld.long 0x00 28. " GMB348 ,Group Modifier Bit 348" "0,1" bitfld.long 0x00 27. " GMB347 ,Group Modifier Bit 347" "0,1" bitfld.long 0x00 26. " GMB346 ,Group Modifier Bit 346" "0,1" textline " " bitfld.long 0x00 25. " GMB345 ,Group Modifier Bit 345" "0,1" bitfld.long 0x00 24. " GMB344 ,Group Modifier Bit 344" "0,1" bitfld.long 0x00 23. " GMB343 ,Group Modifier Bit 343" "0,1" textline " " bitfld.long 0x00 22. " GMB342 ,Group Modifier Bit 342" "0,1" bitfld.long 0x00 21. " GMB341 ,Group Modifier Bit 341" "0,1" bitfld.long 0x00 20. " GMB340 ,Group Modifier Bit 340" "0,1" textline " " bitfld.long 0x00 19. " GMB339 ,Group Modifier Bit 339" "0,1" bitfld.long 0x00 18. " GMB338 ,Group Modifier Bit 338" "0,1" bitfld.long 0x00 17. " GMB337 ,Group Modifier Bit 337" "0,1" textline " " bitfld.long 0x00 16. " GMB336 ,Group Modifier Bit 336" "0,1" bitfld.long 0x00 15. " GMB335 ,Group Modifier Bit 335" "0,1" bitfld.long 0x00 14. " GMB334 ,Group Modifier Bit 334" "0,1" textline " " bitfld.long 0x00 13. " GMB333 ,Group Modifier Bit 333" "0,1" bitfld.long 0x00 12. " GMB332 ,Group Modifier Bit 332" "0,1" bitfld.long 0x00 11. " GMB331 ,Group Modifier Bit 331" "0,1" textline " " bitfld.long 0x00 10. " GMB330 ,Group Modifier Bit 330" "0,1" bitfld.long 0x00 9. " GMB329 ,Group Modifier Bit 329" "0,1" bitfld.long 0x00 8. " GMB328 ,Group Modifier Bit 328" "0,1" textline " " bitfld.long 0x00 7. " GMB327 ,Group Modifier Bit 327" "0,1" bitfld.long 0x00 6. " GMB326 ,Group Modifier Bit 326" "0,1" bitfld.long 0x00 5. " GMB325 ,Group Modifier Bit 325" "0,1" textline " " bitfld.long 0x00 4. " GMB324 ,Group Modifier Bit 324" "0,1" bitfld.long 0x00 3. " GMB323 ,Group Modifier Bit 323" "0,1" bitfld.long 0x00 2. " GMB322 ,Group Modifier Bit 322" "0,1" textline " " bitfld.long 0x00 1. " GMB321 ,Group Modifier Bit 321" "0,1" bitfld.long 0x00 0. " GMB320 ,Group Modifier Bit 320" "0,1" else hgroup.long 0x0D28++0x03 hide.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D2C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)) group.long 0x0D2C++0x03 line.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11" bitfld.long 0x00 31. " GMB383 ,Group Modifier Bit 383" "0,1" bitfld.long 0x00 30. " GMB382 ,Group Modifier Bit 382" "0,1" bitfld.long 0x00 29. " GMB381 ,Group Modifier Bit 381" "0,1" textline " " bitfld.long 0x00 28. " GMB380 ,Group Modifier Bit 380" "0,1" bitfld.long 0x00 27. " GMB379 ,Group Modifier Bit 379" "0,1" bitfld.long 0x00 26. " GMB378 ,Group Modifier Bit 378" "0,1" textline " " bitfld.long 0x00 25. " GMB377 ,Group Modifier Bit 377" "0,1" bitfld.long 0x00 24. " GMB376 ,Group Modifier Bit 376" "0,1" bitfld.long 0x00 23. " GMB375 ,Group Modifier Bit 375" "0,1" textline " " bitfld.long 0x00 22. " GMB374 ,Group Modifier Bit 374" "0,1" bitfld.long 0x00 21. " GMB373 ,Group Modifier Bit 373" "0,1" bitfld.long 0x00 20. " GMB372 ,Group Modifier Bit 372" "0,1" textline " " bitfld.long 0x00 19. " GMB371 ,Group Modifier Bit 371" "0,1" bitfld.long 0x00 18. " GMB370 ,Group Modifier Bit 370" "0,1" bitfld.long 0x00 17. " GMB369 ,Group Modifier Bit 369" "0,1" textline " " bitfld.long 0x00 16. " GMB368 ,Group Modifier Bit 368" "0,1" bitfld.long 0x00 15. " GMB367 ,Group Modifier Bit 367" "0,1" bitfld.long 0x00 14. " GMB366 ,Group Modifier Bit 366" "0,1" textline " " bitfld.long 0x00 13. " GMB365 ,Group Modifier Bit 365" "0,1" bitfld.long 0x00 12. " GMB364 ,Group Modifier Bit 364" "0,1" bitfld.long 0x00 11. " GMB363 ,Group Modifier Bit 363" "0,1" textline " " bitfld.long 0x00 10. " GMB362 ,Group Modifier Bit 362" "0,1" bitfld.long 0x00 9. " GMB361 ,Group Modifier Bit 361" "0,1" bitfld.long 0x00 8. " GMB360 ,Group Modifier Bit 360" "0,1" textline " " bitfld.long 0x00 7. " GMB359 ,Group Modifier Bit 359" "0,1" bitfld.long 0x00 6. " GMB358 ,Group Modifier Bit 358" "0,1" bitfld.long 0x00 5. " GMB357 ,Group Modifier Bit 357" "0,1" textline " " bitfld.long 0x00 4. " GMB356 ,Group Modifier Bit 356" "0,1" bitfld.long 0x00 3. " GMB355 ,Group Modifier Bit 355" "0,1" bitfld.long 0x00 2. " GMB354 ,Group Modifier Bit 354" "0,1" textline " " bitfld.long 0x00 1. " GMB353 ,Group Modifier Bit 353" "0,1" bitfld.long 0x00 0. " GMB352 ,Group Modifier Bit 352" "0,1" else hgroup.long 0x0D2C++0x03 hide.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D30))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)) group.long 0x0D30++0x03 line.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12" bitfld.long 0x00 31. " GMB415 ,Group Modifier Bit 415" "0,1" bitfld.long 0x00 30. " GMB414 ,Group Modifier Bit 414" "0,1" bitfld.long 0x00 29. " GMB413 ,Group Modifier Bit 413" "0,1" textline " " bitfld.long 0x00 28. " GMB412 ,Group Modifier Bit 412" "0,1" bitfld.long 0x00 27. " GMB411 ,Group Modifier Bit 411" "0,1" bitfld.long 0x00 26. " GMB410 ,Group Modifier Bit 410" "0,1" textline " " bitfld.long 0x00 25. " GMB409 ,Group Modifier Bit 409" "0,1" bitfld.long 0x00 24. " GMB408 ,Group Modifier Bit 408" "0,1" bitfld.long 0x00 23. " GMB407 ,Group Modifier Bit 407" "0,1" textline " " bitfld.long 0x00 22. " GMB406 ,Group Modifier Bit 406" "0,1" bitfld.long 0x00 21. " GMB405 ,Group Modifier Bit 405" "0,1" bitfld.long 0x00 20. " GMB404 ,Group Modifier Bit 404" "0,1" textline " " bitfld.long 0x00 19. " GMB403 ,Group Modifier Bit 403" "0,1" bitfld.long 0x00 18. " GMB402 ,Group Modifier Bit 402" "0,1" bitfld.long 0x00 17. " GMB401 ,Group Modifier Bit 401" "0,1" textline " " bitfld.long 0x00 16. " GMB400 ,Group Modifier Bit 400" "0,1" bitfld.long 0x00 15. " GMB399 ,Group Modifier Bit 399" "0,1" bitfld.long 0x00 14. " GMB398 ,Group Modifier Bit 398" "0,1" textline " " bitfld.long 0x00 13. " GMB397 ,Group Modifier Bit 397" "0,1" bitfld.long 0x00 12. " GMB396 ,Group Modifier Bit 396" "0,1" bitfld.long 0x00 11. " GMB395 ,Group Modifier Bit 395" "0,1" textline " " bitfld.long 0x00 10. " GMB394 ,Group Modifier Bit 394" "0,1" bitfld.long 0x00 9. " GMB393 ,Group Modifier Bit 393" "0,1" bitfld.long 0x00 8. " GMB392 ,Group Modifier Bit 392" "0,1" textline " " bitfld.long 0x00 7. " GMB391 ,Group Modifier Bit 391" "0,1" bitfld.long 0x00 6. " GMB390 ,Group Modifier Bit 390" "0,1" bitfld.long 0x00 5. " GMB389 ,Group Modifier Bit 389" "0,1" textline " " bitfld.long 0x00 4. " GMB388 ,Group Modifier Bit 388" "0,1" bitfld.long 0x00 3. " GMB387 ,Group Modifier Bit 387" "0,1" bitfld.long 0x00 2. " GMB386 ,Group Modifier Bit 386" "0,1" textline " " bitfld.long 0x00 1. " GMB385 ,Group Modifier Bit 385" "0,1" bitfld.long 0x00 0. " GMB384 ,Group Modifier Bit 384" "0,1" else hgroup.long 0x0D30++0x03 hide.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D34))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)) group.long 0x0D34++0x03 line.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13" bitfld.long 0x00 31. " GMB447 ,Group Modifier Bit 447" "0,1" bitfld.long 0x00 30. " GMB446 ,Group Modifier Bit 446" "0,1" bitfld.long 0x00 29. " GMB445 ,Group Modifier Bit 445" "0,1" textline " " bitfld.long 0x00 28. " GMB444 ,Group Modifier Bit 444" "0,1" bitfld.long 0x00 27. " GMB443 ,Group Modifier Bit 443" "0,1" bitfld.long 0x00 26. " GMB442 ,Group Modifier Bit 442" "0,1" textline " " bitfld.long 0x00 25. " GMB441 ,Group Modifier Bit 441" "0,1" bitfld.long 0x00 24. " GMB440 ,Group Modifier Bit 440" "0,1" bitfld.long 0x00 23. " GMB439 ,Group Modifier Bit 439" "0,1" textline " " bitfld.long 0x00 22. " GMB438 ,Group Modifier Bit 438" "0,1" bitfld.long 0x00 21. " GMB437 ,Group Modifier Bit 437" "0,1" bitfld.long 0x00 20. " GMB436 ,Group Modifier Bit 436" "0,1" textline " " bitfld.long 0x00 19. " GMB435 ,Group Modifier Bit 435" "0,1" bitfld.long 0x00 18. " GMB434 ,Group Modifier Bit 434" "0,1" bitfld.long 0x00 17. " GMB433 ,Group Modifier Bit 433" "0,1" textline " " bitfld.long 0x00 16. " GMB432 ,Group Modifier Bit 432" "0,1" bitfld.long 0x00 15. " GMB431 ,Group Modifier Bit 431" "0,1" bitfld.long 0x00 14. " GMB430 ,Group Modifier Bit 430" "0,1" textline " " bitfld.long 0x00 13. " GMB429 ,Group Modifier Bit 429" "0,1" bitfld.long 0x00 12. " GMB428 ,Group Modifier Bit 428" "0,1" bitfld.long 0x00 11. " GMB427 ,Group Modifier Bit 427" "0,1" textline " " bitfld.long 0x00 10. " GMB426 ,Group Modifier Bit 426" "0,1" bitfld.long 0x00 9. " GMB425 ,Group Modifier Bit 425" "0,1" bitfld.long 0x00 8. " GMB424 ,Group Modifier Bit 424" "0,1" textline " " bitfld.long 0x00 7. " GMB423 ,Group Modifier Bit 423" "0,1" bitfld.long 0x00 6. " GMB422 ,Group Modifier Bit 422" "0,1" bitfld.long 0x00 5. " GMB421 ,Group Modifier Bit 421" "0,1" textline " " bitfld.long 0x00 4. " GMB420 ,Group Modifier Bit 420" "0,1" bitfld.long 0x00 3. " GMB419 ,Group Modifier Bit 419" "0,1" bitfld.long 0x00 2. " GMB418 ,Group Modifier Bit 418" "0,1" textline " " bitfld.long 0x00 1. " GMB417 ,Group Modifier Bit 417" "0,1" bitfld.long 0x00 0. " GMB416 ,Group Modifier Bit 416" "0,1" else hgroup.long 0x0D34++0x03 hide.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D38))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)) group.long 0x0D38++0x03 line.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14" bitfld.long 0x00 31. " GMB479 ,Group Modifier Bit 479" "0,1" bitfld.long 0x00 30. " GMB478 ,Group Modifier Bit 478" "0,1" bitfld.long 0x00 29. " GMB477 ,Group Modifier Bit 477" "0,1" textline " " bitfld.long 0x00 28. " GMB476 ,Group Modifier Bit 476" "0,1" bitfld.long 0x00 27. " GMB475 ,Group Modifier Bit 475" "0,1" bitfld.long 0x00 26. " GMB474 ,Group Modifier Bit 474" "0,1" textline " " bitfld.long 0x00 25. " GMB473 ,Group Modifier Bit 473" "0,1" bitfld.long 0x00 24. " GMB472 ,Group Modifier Bit 472" "0,1" bitfld.long 0x00 23. " GMB471 ,Group Modifier Bit 471" "0,1" textline " " bitfld.long 0x00 22. " GMB470 ,Group Modifier Bit 470" "0,1" bitfld.long 0x00 21. " GMB469 ,Group Modifier Bit 469" "0,1" bitfld.long 0x00 20. " GMB468 ,Group Modifier Bit 468" "0,1" textline " " bitfld.long 0x00 19. " GMB467 ,Group Modifier Bit 467" "0,1" bitfld.long 0x00 18. " GMB466 ,Group Modifier Bit 466" "0,1" bitfld.long 0x00 17. " GMB465 ,Group Modifier Bit 465" "0,1" textline " " bitfld.long 0x00 16. " GMB464 ,Group Modifier Bit 464" "0,1" bitfld.long 0x00 15. " GMB463 ,Group Modifier Bit 463" "0,1" bitfld.long 0x00 14. " GMB462 ,Group Modifier Bit 462" "0,1" textline " " bitfld.long 0x00 13. " GMB461 ,Group Modifier Bit 461" "0,1" bitfld.long 0x00 12. " GMB460 ,Group Modifier Bit 460" "0,1" bitfld.long 0x00 11. " GMB459 ,Group Modifier Bit 459" "0,1" textline " " bitfld.long 0x00 10. " GMB458 ,Group Modifier Bit 458" "0,1" bitfld.long 0x00 9. " GMB457 ,Group Modifier Bit 457" "0,1" bitfld.long 0x00 8. " GMB456 ,Group Modifier Bit 456" "0,1" textline " " bitfld.long 0x00 7. " GMB455 ,Group Modifier Bit 455" "0,1" bitfld.long 0x00 6. " GMB454 ,Group Modifier Bit 454" "0,1" bitfld.long 0x00 5. " GMB453 ,Group Modifier Bit 453" "0,1" textline " " bitfld.long 0x00 4. " GMB452 ,Group Modifier Bit 452" "0,1" bitfld.long 0x00 3. " GMB451 ,Group Modifier Bit 451" "0,1" bitfld.long 0x00 2. " GMB450 ,Group Modifier Bit 450" "0,1" textline " " bitfld.long 0x00 1. " GMB449 ,Group Modifier Bit 449" "0,1" bitfld.long 0x00 0. " GMB448 ,Group Modifier Bit 448" "0,1" else hgroup.long 0x0D38++0x03 hide.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D3C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)) group.long 0x0D3C++0x03 line.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15" bitfld.long 0x00 31. " GMB511 ,Group Modifier Bit 511" "0,1" bitfld.long 0x00 30. " GMB510 ,Group Modifier Bit 510" "0,1" bitfld.long 0x00 29. " GMB509 ,Group Modifier Bit 509" "0,1" textline " " bitfld.long 0x00 28. " GMB508 ,Group Modifier Bit 508" "0,1" bitfld.long 0x00 27. " GMB507 ,Group Modifier Bit 507" "0,1" bitfld.long 0x00 26. " GMB506 ,Group Modifier Bit 506" "0,1" textline " " bitfld.long 0x00 25. " GMB505 ,Group Modifier Bit 505" "0,1" bitfld.long 0x00 24. " GMB504 ,Group Modifier Bit 504" "0,1" bitfld.long 0x00 23. " GMB503 ,Group Modifier Bit 503" "0,1" textline " " bitfld.long 0x00 22. " GMB502 ,Group Modifier Bit 502" "0,1" bitfld.long 0x00 21. " GMB501 ,Group Modifier Bit 501" "0,1" bitfld.long 0x00 20. " GMB500 ,Group Modifier Bit 500" "0,1" textline " " bitfld.long 0x00 19. " GMB499 ,Group Modifier Bit 499" "0,1" bitfld.long 0x00 18. " GMB498 ,Group Modifier Bit 498" "0,1" bitfld.long 0x00 17. " GMB497 ,Group Modifier Bit 497" "0,1" textline " " bitfld.long 0x00 16. " GMB496 ,Group Modifier Bit 496" "0,1" bitfld.long 0x00 15. " GMB495 ,Group Modifier Bit 495" "0,1" bitfld.long 0x00 14. " GMB494 ,Group Modifier Bit 494" "0,1" textline " " bitfld.long 0x00 13. " GMB493 ,Group Modifier Bit 493" "0,1" bitfld.long 0x00 12. " GMB492 ,Group Modifier Bit 492" "0,1" bitfld.long 0x00 11. " GMB491 ,Group Modifier Bit 491" "0,1" textline " " bitfld.long 0x00 10. " GMB490 ,Group Modifier Bit 490" "0,1" bitfld.long 0x00 9. " GMB489 ,Group Modifier Bit 489" "0,1" bitfld.long 0x00 8. " GMB488 ,Group Modifier Bit 488" "0,1" textline " " bitfld.long 0x00 7. " GMB487 ,Group Modifier Bit 487" "0,1" bitfld.long 0x00 6. " GMB486 ,Group Modifier Bit 486" "0,1" bitfld.long 0x00 5. " GMB485 ,Group Modifier Bit 485" "0,1" textline " " bitfld.long 0x00 4. " GMB484 ,Group Modifier Bit 484" "0,1" bitfld.long 0x00 3. " GMB483 ,Group Modifier Bit 483" "0,1" bitfld.long 0x00 2. " GMB482 ,Group Modifier Bit 482" "0,1" textline " " bitfld.long 0x00 1. " GMB481 ,Group Modifier Bit 481" "0,1" bitfld.long 0x00 0. " GMB480 ,Group Modifier Bit 480" "0,1" else hgroup.long 0x0D3C++0x03 hide.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D40))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x0D40++0x03 line.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16" bitfld.long 0x00 31. " GMB543 ,Group Modifier Bit 543" "0,1" bitfld.long 0x00 30. " GMB542 ,Group Modifier Bit 542" "0,1" bitfld.long 0x00 29. " GMB541 ,Group Modifier Bit 541" "0,1" textline " " bitfld.long 0x00 28. " GMB540 ,Group Modifier Bit 540" "0,1" bitfld.long 0x00 27. " GMB539 ,Group Modifier Bit 539" "0,1" bitfld.long 0x00 26. " GMB538 ,Group Modifier Bit 538" "0,1" textline " " bitfld.long 0x00 25. " GMB537 ,Group Modifier Bit 537" "0,1" bitfld.long 0x00 24. " GMB536 ,Group Modifier Bit 536" "0,1" bitfld.long 0x00 23. " GMB535 ,Group Modifier Bit 535" "0,1" textline " " bitfld.long 0x00 22. " GMB534 ,Group Modifier Bit 534" "0,1" bitfld.long 0x00 21. " GMB533 ,Group Modifier Bit 533" "0,1" bitfld.long 0x00 20. " GMB532 ,Group Modifier Bit 532" "0,1" textline " " bitfld.long 0x00 19. " GMB531 ,Group Modifier Bit 531" "0,1" bitfld.long 0x00 18. " GMB530 ,Group Modifier Bit 530" "0,1" bitfld.long 0x00 17. " GMB529 ,Group Modifier Bit 529" "0,1" textline " " bitfld.long 0x00 16. " GMB528 ,Group Modifier Bit 528" "0,1" bitfld.long 0x00 15. " GMB527 ,Group Modifier Bit 527" "0,1" bitfld.long 0x00 14. " GMB526 ,Group Modifier Bit 526" "0,1" textline " " bitfld.long 0x00 13. " GMB525 ,Group Modifier Bit 525" "0,1" bitfld.long 0x00 12. " GMB524 ,Group Modifier Bit 524" "0,1" bitfld.long 0x00 11. " GMB523 ,Group Modifier Bit 523" "0,1" textline " " bitfld.long 0x00 10. " GMB522 ,Group Modifier Bit 522" "0,1" bitfld.long 0x00 9. " GMB521 ,Group Modifier Bit 521" "0,1" bitfld.long 0x00 8. " GMB520 ,Group Modifier Bit 520" "0,1" textline " " bitfld.long 0x00 7. " GMB519 ,Group Modifier Bit 519" "0,1" bitfld.long 0x00 6. " GMB518 ,Group Modifier Bit 518" "0,1" bitfld.long 0x00 5. " GMB517 ,Group Modifier Bit 517" "0,1" textline " " bitfld.long 0x00 4. " GMB516 ,Group Modifier Bit 516" "0,1" bitfld.long 0x00 3. " GMB515 ,Group Modifier Bit 515" "0,1" bitfld.long 0x00 2. " GMB514 ,Group Modifier Bit 514" "0,1" textline " " bitfld.long 0x00 1. " GMB513 ,Group Modifier Bit 513" "0,1" bitfld.long 0x00 0. " GMB512 ,Group Modifier Bit 512" "0,1" else hgroup.long 0x0D40++0x03 hide.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D44))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x0D44++0x03 line.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17" bitfld.long 0x00 31. " GMB575 ,Group Modifier Bit 575" "0,1" bitfld.long 0x00 30. " GMB574 ,Group Modifier Bit 574" "0,1" bitfld.long 0x00 29. " GMB573 ,Group Modifier Bit 573" "0,1" textline " " bitfld.long 0x00 28. " GMB572 ,Group Modifier Bit 572" "0,1" bitfld.long 0x00 27. " GMB571 ,Group Modifier Bit 571" "0,1" bitfld.long 0x00 26. " GMB570 ,Group Modifier Bit 570" "0,1" textline " " bitfld.long 0x00 25. " GMB569 ,Group Modifier Bit 569" "0,1" bitfld.long 0x00 24. " GMB568 ,Group Modifier Bit 568" "0,1" bitfld.long 0x00 23. " GMB567 ,Group Modifier Bit 567" "0,1" textline " " bitfld.long 0x00 22. " GMB566 ,Group Modifier Bit 566" "0,1" bitfld.long 0x00 21. " GMB565 ,Group Modifier Bit 565" "0,1" bitfld.long 0x00 20. " GMB564 ,Group Modifier Bit 564" "0,1" textline " " bitfld.long 0x00 19. " GMB563 ,Group Modifier Bit 563" "0,1" bitfld.long 0x00 18. " GMB562 ,Group Modifier Bit 562" "0,1" bitfld.long 0x00 17. " GMB561 ,Group Modifier Bit 561" "0,1" textline " " bitfld.long 0x00 16. " GMB560 ,Group Modifier Bit 560" "0,1" bitfld.long 0x00 15. " GMB559 ,Group Modifier Bit 559" "0,1" bitfld.long 0x00 14. " GMB558 ,Group Modifier Bit 558" "0,1" textline " " bitfld.long 0x00 13. " GMB557 ,Group Modifier Bit 557" "0,1" bitfld.long 0x00 12. " GMB556 ,Group Modifier Bit 556" "0,1" bitfld.long 0x00 11. " GMB555 ,Group Modifier Bit 555" "0,1" textline " " bitfld.long 0x00 10. " GMB554 ,Group Modifier Bit 554" "0,1" bitfld.long 0x00 9. " GMB553 ,Group Modifier Bit 553" "0,1" bitfld.long 0x00 8. " GMB552 ,Group Modifier Bit 552" "0,1" textline " " bitfld.long 0x00 7. " GMB551 ,Group Modifier Bit 551" "0,1" bitfld.long 0x00 6. " GMB550 ,Group Modifier Bit 550" "0,1" bitfld.long 0x00 5. " GMB549 ,Group Modifier Bit 549" "0,1" textline " " bitfld.long 0x00 4. " GMB548 ,Group Modifier Bit 548" "0,1" bitfld.long 0x00 3. " GMB547 ,Group Modifier Bit 547" "0,1" bitfld.long 0x00 2. " GMB546 ,Group Modifier Bit 546" "0,1" textline " " bitfld.long 0x00 1. " GMB545 ,Group Modifier Bit 545" "0,1" bitfld.long 0x00 0. " GMB544 ,Group Modifier Bit 544" "0,1" else hgroup.long 0x0D44++0x03 hide.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D48))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x0D48++0x03 line.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18" bitfld.long 0x00 31. " GMB607 ,Group Modifier Bit 607" "0,1" bitfld.long 0x00 30. " GMB606 ,Group Modifier Bit 606" "0,1" bitfld.long 0x00 29. " GMB605 ,Group Modifier Bit 605" "0,1" textline " " bitfld.long 0x00 28. " GMB604 ,Group Modifier Bit 604" "0,1" bitfld.long 0x00 27. " GMB603 ,Group Modifier Bit 603" "0,1" bitfld.long 0x00 26. " GMB602 ,Group Modifier Bit 602" "0,1" textline " " bitfld.long 0x00 25. " GMB601 ,Group Modifier Bit 601" "0,1" bitfld.long 0x00 24. " GMB600 ,Group Modifier Bit 600" "0,1" bitfld.long 0x00 23. " GMB599 ,Group Modifier Bit 599" "0,1" textline " " bitfld.long 0x00 22. " GMB598 ,Group Modifier Bit 598" "0,1" bitfld.long 0x00 21. " GMB597 ,Group Modifier Bit 597" "0,1" bitfld.long 0x00 20. " GMB596 ,Group Modifier Bit 596" "0,1" textline " " bitfld.long 0x00 19. " GMB595 ,Group Modifier Bit 595" "0,1" bitfld.long 0x00 18. " GMB594 ,Group Modifier Bit 594" "0,1" bitfld.long 0x00 17. " GMB593 ,Group Modifier Bit 593" "0,1" textline " " bitfld.long 0x00 16. " GMB592 ,Group Modifier Bit 592" "0,1" bitfld.long 0x00 15. " GMB591 ,Group Modifier Bit 591" "0,1" bitfld.long 0x00 14. " GMB590 ,Group Modifier Bit 590" "0,1" textline " " bitfld.long 0x00 13. " GMB589 ,Group Modifier Bit 589" "0,1" bitfld.long 0x00 12. " GMB588 ,Group Modifier Bit 588" "0,1" bitfld.long 0x00 11. " GMB587 ,Group Modifier Bit 587" "0,1" textline " " bitfld.long 0x00 10. " GMB586 ,Group Modifier Bit 586" "0,1" bitfld.long 0x00 9. " GMB585 ,Group Modifier Bit 585" "0,1" bitfld.long 0x00 8. " GMB584 ,Group Modifier Bit 584" "0,1" textline " " bitfld.long 0x00 7. " GMB583 ,Group Modifier Bit 583" "0,1" bitfld.long 0x00 6. " GMB582 ,Group Modifier Bit 582" "0,1" bitfld.long 0x00 5. " GMB581 ,Group Modifier Bit 581" "0,1" textline " " bitfld.long 0x00 4. " GMB580 ,Group Modifier Bit 580" "0,1" bitfld.long 0x00 3. " GMB579 ,Group Modifier Bit 579" "0,1" bitfld.long 0x00 2. " GMB578 ,Group Modifier Bit 578" "0,1" textline " " bitfld.long 0x00 1. " GMB577 ,Group Modifier Bit 577" "0,1" bitfld.long 0x00 0. " GMB576 ,Group Modifier Bit 576" "0,1" else hgroup.long 0x0D48++0x03 hide.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D4C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x0D4C++0x03 line.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19" bitfld.long 0x00 31. " GMB639 ,Group Modifier Bit 639" "0,1" bitfld.long 0x00 30. " GMB638 ,Group Modifier Bit 638" "0,1" bitfld.long 0x00 29. " GMB637 ,Group Modifier Bit 637" "0,1" textline " " bitfld.long 0x00 28. " GMB636 ,Group Modifier Bit 636" "0,1" bitfld.long 0x00 27. " GMB635 ,Group Modifier Bit 635" "0,1" bitfld.long 0x00 26. " GMB634 ,Group Modifier Bit 634" "0,1" textline " " bitfld.long 0x00 25. " GMB633 ,Group Modifier Bit 633" "0,1" bitfld.long 0x00 24. " GMB632 ,Group Modifier Bit 632" "0,1" bitfld.long 0x00 23. " GMB631 ,Group Modifier Bit 631" "0,1" textline " " bitfld.long 0x00 22. " GMB630 ,Group Modifier Bit 630" "0,1" bitfld.long 0x00 21. " GMB629 ,Group Modifier Bit 629" "0,1" bitfld.long 0x00 20. " GMB628 ,Group Modifier Bit 628" "0,1" textline " " bitfld.long 0x00 19. " GMB627 ,Group Modifier Bit 627" "0,1" bitfld.long 0x00 18. " GMB626 ,Group Modifier Bit 626" "0,1" bitfld.long 0x00 17. " GMB625 ,Group Modifier Bit 625" "0,1" textline " " bitfld.long 0x00 16. " GMB624 ,Group Modifier Bit 624" "0,1" bitfld.long 0x00 15. " GMB623 ,Group Modifier Bit 623" "0,1" bitfld.long 0x00 14. " GMB622 ,Group Modifier Bit 622" "0,1" textline " " bitfld.long 0x00 13. " GMB621 ,Group Modifier Bit 621" "0,1" bitfld.long 0x00 12. " GMB620 ,Group Modifier Bit 620" "0,1" bitfld.long 0x00 11. " GMB619 ,Group Modifier Bit 619" "0,1" textline " " bitfld.long 0x00 10. " GMB618 ,Group Modifier Bit 618" "0,1" bitfld.long 0x00 9. " GMB617 ,Group Modifier Bit 617" "0,1" bitfld.long 0x00 8. " GMB616 ,Group Modifier Bit 616" "0,1" textline " " bitfld.long 0x00 7. " GMB615 ,Group Modifier Bit 615" "0,1" bitfld.long 0x00 6. " GMB614 ,Group Modifier Bit 614" "0,1" bitfld.long 0x00 5. " GMB613 ,Group Modifier Bit 613" "0,1" textline " " bitfld.long 0x00 4. " GMB612 ,Group Modifier Bit 612" "0,1" bitfld.long 0x00 3. " GMB611 ,Group Modifier Bit 611" "0,1" bitfld.long 0x00 2. " GMB610 ,Group Modifier Bit 610" "0,1" textline " " bitfld.long 0x00 1. " GMB609 ,Group Modifier Bit 609" "0,1" bitfld.long 0x00 0. " GMB608 ,Group Modifier Bit 608" "0,1" else hgroup.long 0x0D4C++0x03 hide.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D50))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x0D50++0x03 line.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20" bitfld.long 0x00 31. " GMB671 ,Group Modifier Bit 671" "0,1" bitfld.long 0x00 30. " GMB670 ,Group Modifier Bit 670" "0,1" bitfld.long 0x00 29. " GMB669 ,Group Modifier Bit 669" "0,1" textline " " bitfld.long 0x00 28. " GMB668 ,Group Modifier Bit 668" "0,1" bitfld.long 0x00 27. " GMB667 ,Group Modifier Bit 667" "0,1" bitfld.long 0x00 26. " GMB666 ,Group Modifier Bit 666" "0,1" textline " " bitfld.long 0x00 25. " GMB665 ,Group Modifier Bit 665" "0,1" bitfld.long 0x00 24. " GMB664 ,Group Modifier Bit 664" "0,1" bitfld.long 0x00 23. " GMB663 ,Group Modifier Bit 663" "0,1" textline " " bitfld.long 0x00 22. " GMB662 ,Group Modifier Bit 662" "0,1" bitfld.long 0x00 21. " GMB661 ,Group Modifier Bit 661" "0,1" bitfld.long 0x00 20. " GMB660 ,Group Modifier Bit 660" "0,1" textline " " bitfld.long 0x00 19. " GMB659 ,Group Modifier Bit 659" "0,1" bitfld.long 0x00 18. " GMB658 ,Group Modifier Bit 658" "0,1" bitfld.long 0x00 17. " GMB657 ,Group Modifier Bit 657" "0,1" textline " " bitfld.long 0x00 16. " GMB656 ,Group Modifier Bit 656" "0,1" bitfld.long 0x00 15. " GMB655 ,Group Modifier Bit 655" "0,1" bitfld.long 0x00 14. " GMB654 ,Group Modifier Bit 654" "0,1" textline " " bitfld.long 0x00 13. " GMB653 ,Group Modifier Bit 653" "0,1" bitfld.long 0x00 12. " GMB652 ,Group Modifier Bit 652" "0,1" bitfld.long 0x00 11. " GMB651 ,Group Modifier Bit 651" "0,1" textline " " bitfld.long 0x00 10. " GMB650 ,Group Modifier Bit 650" "0,1" bitfld.long 0x00 9. " GMB649 ,Group Modifier Bit 649" "0,1" bitfld.long 0x00 8. " GMB648 ,Group Modifier Bit 648" "0,1" textline " " bitfld.long 0x00 7. " GMB647 ,Group Modifier Bit 647" "0,1" bitfld.long 0x00 6. " GMB646 ,Group Modifier Bit 646" "0,1" bitfld.long 0x00 5. " GMB645 ,Group Modifier Bit 645" "0,1" textline " " bitfld.long 0x00 4. " GMB644 ,Group Modifier Bit 644" "0,1" bitfld.long 0x00 3. " GMB643 ,Group Modifier Bit 643" "0,1" bitfld.long 0x00 2. " GMB642 ,Group Modifier Bit 642" "0,1" textline " " bitfld.long 0x00 1. " GMB641 ,Group Modifier Bit 641" "0,1" bitfld.long 0x00 0. " GMB640 ,Group Modifier Bit 640" "0,1" else hgroup.long 0x0D50++0x03 hide.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D54))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x0D54++0x03 line.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21" bitfld.long 0x00 31. " GMB703 ,Group Modifier Bit 703" "0,1" bitfld.long 0x00 30. " GMB702 ,Group Modifier Bit 702" "0,1" bitfld.long 0x00 29. " GMB701 ,Group Modifier Bit 701" "0,1" textline " " bitfld.long 0x00 28. " GMB700 ,Group Modifier Bit 700" "0,1" bitfld.long 0x00 27. " GMB699 ,Group Modifier Bit 699" "0,1" bitfld.long 0x00 26. " GMB698 ,Group Modifier Bit 698" "0,1" textline " " bitfld.long 0x00 25. " GMB697 ,Group Modifier Bit 697" "0,1" bitfld.long 0x00 24. " GMB696 ,Group Modifier Bit 696" "0,1" bitfld.long 0x00 23. " GMB695 ,Group Modifier Bit 695" "0,1" textline " " bitfld.long 0x00 22. " GMB694 ,Group Modifier Bit 694" "0,1" bitfld.long 0x00 21. " GMB693 ,Group Modifier Bit 693" "0,1" bitfld.long 0x00 20. " GMB692 ,Group Modifier Bit 692" "0,1" textline " " bitfld.long 0x00 19. " GMB691 ,Group Modifier Bit 691" "0,1" bitfld.long 0x00 18. " GMB690 ,Group Modifier Bit 690" "0,1" bitfld.long 0x00 17. " GMB689 ,Group Modifier Bit 689" "0,1" textline " " bitfld.long 0x00 16. " GMB688 ,Group Modifier Bit 688" "0,1" bitfld.long 0x00 15. " GMB687 ,Group Modifier Bit 687" "0,1" bitfld.long 0x00 14. " GMB686 ,Group Modifier Bit 686" "0,1" textline " " bitfld.long 0x00 13. " GMB685 ,Group Modifier Bit 685" "0,1" bitfld.long 0x00 12. " GMB684 ,Group Modifier Bit 684" "0,1" bitfld.long 0x00 11. " GMB683 ,Group Modifier Bit 683" "0,1" textline " " bitfld.long 0x00 10. " GMB682 ,Group Modifier Bit 682" "0,1" bitfld.long 0x00 9. " GMB681 ,Group Modifier Bit 681" "0,1" bitfld.long 0x00 8. " GMB680 ,Group Modifier Bit 680" "0,1" textline " " bitfld.long 0x00 7. " GMB679 ,Group Modifier Bit 679" "0,1" bitfld.long 0x00 6. " GMB678 ,Group Modifier Bit 678" "0,1" bitfld.long 0x00 5. " GMB677 ,Group Modifier Bit 677" "0,1" textline " " bitfld.long 0x00 4. " GMB676 ,Group Modifier Bit 676" "0,1" bitfld.long 0x00 3. " GMB675 ,Group Modifier Bit 675" "0,1" bitfld.long 0x00 2. " GMB674 ,Group Modifier Bit 674" "0,1" textline " " bitfld.long 0x00 1. " GMB673 ,Group Modifier Bit 673" "0,1" bitfld.long 0x00 0. " GMB672 ,Group Modifier Bit 672" "0,1" else hgroup.long 0x0D54++0x03 hide.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D58))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x0D58++0x03 line.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22" bitfld.long 0x00 31. " GMB735 ,Group Modifier Bit 735" "0,1" bitfld.long 0x00 30. " GMB734 ,Group Modifier Bit 734" "0,1" bitfld.long 0x00 29. " GMB733 ,Group Modifier Bit 733" "0,1" textline " " bitfld.long 0x00 28. " GMB732 ,Group Modifier Bit 732" "0,1" bitfld.long 0x00 27. " GMB731 ,Group Modifier Bit 731" "0,1" bitfld.long 0x00 26. " GMB730 ,Group Modifier Bit 730" "0,1" textline " " bitfld.long 0x00 25. " GMB729 ,Group Modifier Bit 729" "0,1" bitfld.long 0x00 24. " GMB728 ,Group Modifier Bit 728" "0,1" bitfld.long 0x00 23. " GMB727 ,Group Modifier Bit 727" "0,1" textline " " bitfld.long 0x00 22. " GMB726 ,Group Modifier Bit 726" "0,1" bitfld.long 0x00 21. " GMB725 ,Group Modifier Bit 725" "0,1" bitfld.long 0x00 20. " GMB724 ,Group Modifier Bit 724" "0,1" textline " " bitfld.long 0x00 19. " GMB723 ,Group Modifier Bit 723" "0,1" bitfld.long 0x00 18. " GMB722 ,Group Modifier Bit 722" "0,1" bitfld.long 0x00 17. " GMB721 ,Group Modifier Bit 721" "0,1" textline " " bitfld.long 0x00 16. " GMB720 ,Group Modifier Bit 720" "0,1" bitfld.long 0x00 15. " GMB719 ,Group Modifier Bit 719" "0,1" bitfld.long 0x00 14. " GMB718 ,Group Modifier Bit 718" "0,1" textline " " bitfld.long 0x00 13. " GMB717 ,Group Modifier Bit 717" "0,1" bitfld.long 0x00 12. " GMB716 ,Group Modifier Bit 716" "0,1" bitfld.long 0x00 11. " GMB715 ,Group Modifier Bit 715" "0,1" textline " " bitfld.long 0x00 10. " GMB714 ,Group Modifier Bit 714" "0,1" bitfld.long 0x00 9. " GMB713 ,Group Modifier Bit 713" "0,1" bitfld.long 0x00 8. " GMB712 ,Group Modifier Bit 712" "0,1" textline " " bitfld.long 0x00 7. " GMB711 ,Group Modifier Bit 711" "0,1" bitfld.long 0x00 6. " GMB710 ,Group Modifier Bit 710" "0,1" bitfld.long 0x00 5. " GMB709 ,Group Modifier Bit 709" "0,1" textline " " bitfld.long 0x00 4. " GMB708 ,Group Modifier Bit 708" "0,1" bitfld.long 0x00 3. " GMB707 ,Group Modifier Bit 707" "0,1" bitfld.long 0x00 2. " GMB706 ,Group Modifier Bit 706" "0,1" textline " " bitfld.long 0x00 1. " GMB705 ,Group Modifier Bit 705" "0,1" bitfld.long 0x00 0. " GMB704 ,Group Modifier Bit 704" "0,1" else hgroup.long 0x0D58++0x03 hide.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D5C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x0D5C++0x03 line.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23" bitfld.long 0x00 31. " GMB767 ,Group Modifier Bit 767" "0,1" bitfld.long 0x00 30. " GMB766 ,Group Modifier Bit 766" "0,1" bitfld.long 0x00 29. " GMB765 ,Group Modifier Bit 765" "0,1" textline " " bitfld.long 0x00 28. " GMB764 ,Group Modifier Bit 764" "0,1" bitfld.long 0x00 27. " GMB763 ,Group Modifier Bit 763" "0,1" bitfld.long 0x00 26. " GMB762 ,Group Modifier Bit 762" "0,1" textline " " bitfld.long 0x00 25. " GMB761 ,Group Modifier Bit 761" "0,1" bitfld.long 0x00 24. " GMB760 ,Group Modifier Bit 760" "0,1" bitfld.long 0x00 23. " GMB759 ,Group Modifier Bit 759" "0,1" textline " " bitfld.long 0x00 22. " GMB758 ,Group Modifier Bit 758" "0,1" bitfld.long 0x00 21. " GMB757 ,Group Modifier Bit 757" "0,1" bitfld.long 0x00 20. " GMB756 ,Group Modifier Bit 756" "0,1" textline " " bitfld.long 0x00 19. " GMB755 ,Group Modifier Bit 755" "0,1" bitfld.long 0x00 18. " GMB754 ,Group Modifier Bit 754" "0,1" bitfld.long 0x00 17. " GMB753 ,Group Modifier Bit 753" "0,1" textline " " bitfld.long 0x00 16. " GMB752 ,Group Modifier Bit 752" "0,1" bitfld.long 0x00 15. " GMB751 ,Group Modifier Bit 751" "0,1" bitfld.long 0x00 14. " GMB750 ,Group Modifier Bit 750" "0,1" textline " " bitfld.long 0x00 13. " GMB749 ,Group Modifier Bit 749" "0,1" bitfld.long 0x00 12. " GMB748 ,Group Modifier Bit 748" "0,1" bitfld.long 0x00 11. " GMB747 ,Group Modifier Bit 747" "0,1" textline " " bitfld.long 0x00 10. " GMB746 ,Group Modifier Bit 746" "0,1" bitfld.long 0x00 9. " GMB745 ,Group Modifier Bit 745" "0,1" bitfld.long 0x00 8. " GMB744 ,Group Modifier Bit 744" "0,1" textline " " bitfld.long 0x00 7. " GMB743 ,Group Modifier Bit 743" "0,1" bitfld.long 0x00 6. " GMB742 ,Group Modifier Bit 742" "0,1" bitfld.long 0x00 5. " GMB741 ,Group Modifier Bit 741" "0,1" textline " " bitfld.long 0x00 4. " GMB740 ,Group Modifier Bit 740" "0,1" bitfld.long 0x00 3. " GMB739 ,Group Modifier Bit 739" "0,1" bitfld.long 0x00 2. " GMB738 ,Group Modifier Bit 738" "0,1" textline " " bitfld.long 0x00 1. " GMB737 ,Group Modifier Bit 737" "0,1" bitfld.long 0x00 0. " GMB736 ,Group Modifier Bit 736" "0,1" else hgroup.long 0x0D5C++0x03 hide.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D60))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x0D60++0x03 line.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24" bitfld.long 0x00 31. " GMB799 ,Group Modifier Bit 799" "0,1" bitfld.long 0x00 30. " GMB798 ,Group Modifier Bit 798" "0,1" bitfld.long 0x00 29. " GMB797 ,Group Modifier Bit 797" "0,1" textline " " bitfld.long 0x00 28. " GMB796 ,Group Modifier Bit 796" "0,1" bitfld.long 0x00 27. " GMB795 ,Group Modifier Bit 795" "0,1" bitfld.long 0x00 26. " GMB794 ,Group Modifier Bit 794" "0,1" textline " " bitfld.long 0x00 25. " GMB793 ,Group Modifier Bit 793" "0,1" bitfld.long 0x00 24. " GMB792 ,Group Modifier Bit 792" "0,1" bitfld.long 0x00 23. " GMB791 ,Group Modifier Bit 791" "0,1" textline " " bitfld.long 0x00 22. " GMB790 ,Group Modifier Bit 790" "0,1" bitfld.long 0x00 21. " GMB789 ,Group Modifier Bit 789" "0,1" bitfld.long 0x00 20. " GMB788 ,Group Modifier Bit 788" "0,1" textline " " bitfld.long 0x00 19. " GMB787 ,Group Modifier Bit 787" "0,1" bitfld.long 0x00 18. " GMB786 ,Group Modifier Bit 786" "0,1" bitfld.long 0x00 17. " GMB785 ,Group Modifier Bit 785" "0,1" textline " " bitfld.long 0x00 16. " GMB784 ,Group Modifier Bit 784" "0,1" bitfld.long 0x00 15. " GMB783 ,Group Modifier Bit 783" "0,1" bitfld.long 0x00 14. " GMB782 ,Group Modifier Bit 782" "0,1" textline " " bitfld.long 0x00 13. " GMB781 ,Group Modifier Bit 781" "0,1" bitfld.long 0x00 12. " GMB780 ,Group Modifier Bit 780" "0,1" bitfld.long 0x00 11. " GMB779 ,Group Modifier Bit 779" "0,1" textline " " bitfld.long 0x00 10. " GMB778 ,Group Modifier Bit 778" "0,1" bitfld.long 0x00 9. " GMB777 ,Group Modifier Bit 777" "0,1" bitfld.long 0x00 8. " GMB776 ,Group Modifier Bit 776" "0,1" textline " " bitfld.long 0x00 7. " GMB775 ,Group Modifier Bit 775" "0,1" bitfld.long 0x00 6. " GMB774 ,Group Modifier Bit 774" "0,1" bitfld.long 0x00 5. " GMB773 ,Group Modifier Bit 773" "0,1" textline " " bitfld.long 0x00 4. " GMB772 ,Group Modifier Bit 772" "0,1" bitfld.long 0x00 3. " GMB771 ,Group Modifier Bit 771" "0,1" bitfld.long 0x00 2. " GMB770 ,Group Modifier Bit 770" "0,1" textline " " bitfld.long 0x00 1. " GMB769 ,Group Modifier Bit 769" "0,1" bitfld.long 0x00 0. " GMB768 ,Group Modifier Bit 768" "0,1" else hgroup.long 0x0D60++0x03 hide.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D64))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x0D64++0x03 line.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25" bitfld.long 0x00 31. " GMB831 ,Group Modifier Bit 831" "0,1" bitfld.long 0x00 30. " GMB830 ,Group Modifier Bit 830" "0,1" bitfld.long 0x00 29. " GMB829 ,Group Modifier Bit 829" "0,1" textline " " bitfld.long 0x00 28. " GMB828 ,Group Modifier Bit 828" "0,1" bitfld.long 0x00 27. " GMB827 ,Group Modifier Bit 827" "0,1" bitfld.long 0x00 26. " GMB826 ,Group Modifier Bit 826" "0,1" textline " " bitfld.long 0x00 25. " GMB825 ,Group Modifier Bit 825" "0,1" bitfld.long 0x00 24. " GMB824 ,Group Modifier Bit 824" "0,1" bitfld.long 0x00 23. " GMB823 ,Group Modifier Bit 823" "0,1" textline " " bitfld.long 0x00 22. " GMB822 ,Group Modifier Bit 822" "0,1" bitfld.long 0x00 21. " GMB821 ,Group Modifier Bit 821" "0,1" bitfld.long 0x00 20. " GMB820 ,Group Modifier Bit 820" "0,1" textline " " bitfld.long 0x00 19. " GMB819 ,Group Modifier Bit 819" "0,1" bitfld.long 0x00 18. " GMB818 ,Group Modifier Bit 818" "0,1" bitfld.long 0x00 17. " GMB817 ,Group Modifier Bit 817" "0,1" textline " " bitfld.long 0x00 16. " GMB816 ,Group Modifier Bit 816" "0,1" bitfld.long 0x00 15. " GMB815 ,Group Modifier Bit 815" "0,1" bitfld.long 0x00 14. " GMB814 ,Group Modifier Bit 814" "0,1" textline " " bitfld.long 0x00 13. " GMB813 ,Group Modifier Bit 813" "0,1" bitfld.long 0x00 12. " GMB812 ,Group Modifier Bit 812" "0,1" bitfld.long 0x00 11. " GMB811 ,Group Modifier Bit 811" "0,1" textline " " bitfld.long 0x00 10. " GMB810 ,Group Modifier Bit 810" "0,1" bitfld.long 0x00 9. " GMB809 ,Group Modifier Bit 809" "0,1" bitfld.long 0x00 8. " GMB808 ,Group Modifier Bit 808" "0,1" textline " " bitfld.long 0x00 7. " GMB807 ,Group Modifier Bit 807" "0,1" bitfld.long 0x00 6. " GMB806 ,Group Modifier Bit 806" "0,1" bitfld.long 0x00 5. " GMB805 ,Group Modifier Bit 805" "0,1" textline " " bitfld.long 0x00 4. " GMB804 ,Group Modifier Bit 804" "0,1" bitfld.long 0x00 3. " GMB803 ,Group Modifier Bit 803" "0,1" bitfld.long 0x00 2. " GMB802 ,Group Modifier Bit 802" "0,1" textline " " bitfld.long 0x00 1. " GMB801 ,Group Modifier Bit 801" "0,1" bitfld.long 0x00 0. " GMB800 ,Group Modifier Bit 800" "0,1" else hgroup.long 0x0D64++0x03 hide.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D68))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01A)) group.long 0x0D68++0x03 line.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26" bitfld.long 0x00 31. " GMB863 ,Group Modifier Bit 863" "0,1" bitfld.long 0x00 30. " GMB862 ,Group Modifier Bit 862" "0,1" bitfld.long 0x00 29. " GMB861 ,Group Modifier Bit 861" "0,1" textline " " bitfld.long 0x00 28. " GMB860 ,Group Modifier Bit 860" "0,1" bitfld.long 0x00 27. " GMB859 ,Group Modifier Bit 859" "0,1" bitfld.long 0x00 26. " GMB858 ,Group Modifier Bit 858" "0,1" textline " " bitfld.long 0x00 25. " GMB857 ,Group Modifier Bit 857" "0,1" bitfld.long 0x00 24. " GMB856 ,Group Modifier Bit 856" "0,1" bitfld.long 0x00 23. " GMB855 ,Group Modifier Bit 855" "0,1" textline " " bitfld.long 0x00 22. " GMB854 ,Group Modifier Bit 854" "0,1" bitfld.long 0x00 21. " GMB853 ,Group Modifier Bit 853" "0,1" bitfld.long 0x00 20. " GMB852 ,Group Modifier Bit 852" "0,1" textline " " bitfld.long 0x00 19. " GMB851 ,Group Modifier Bit 851" "0,1" bitfld.long 0x00 18. " GMB850 ,Group Modifier Bit 850" "0,1" bitfld.long 0x00 17. " GMB849 ,Group Modifier Bit 849" "0,1" textline " " bitfld.long 0x00 16. " GMB848 ,Group Modifier Bit 848" "0,1" bitfld.long 0x00 15. " GMB847 ,Group Modifier Bit 847" "0,1" bitfld.long 0x00 14. " GMB846 ,Group Modifier Bit 846" "0,1" textline " " bitfld.long 0x00 13. " GMB845 ,Group Modifier Bit 845" "0,1" bitfld.long 0x00 12. " GMB844 ,Group Modifier Bit 844" "0,1" bitfld.long 0x00 11. " GMB843 ,Group Modifier Bit 843" "0,1" textline " " bitfld.long 0x00 10. " GMB842 ,Group Modifier Bit 842" "0,1" bitfld.long 0x00 9. " GMB841 ,Group Modifier Bit 841" "0,1" bitfld.long 0x00 8. " GMB840 ,Group Modifier Bit 840" "0,1" textline " " bitfld.long 0x00 7. " GMB839 ,Group Modifier Bit 839" "0,1" bitfld.long 0x00 6. " GMB838 ,Group Modifier Bit 838" "0,1" bitfld.long 0x00 5. " GMB837 ,Group Modifier Bit 837" "0,1" textline " " bitfld.long 0x00 4. " GMB836 ,Group Modifier Bit 836" "0,1" bitfld.long 0x00 3. " GMB835 ,Group Modifier Bit 835" "0,1" bitfld.long 0x00 2. " GMB834 ,Group Modifier Bit 834" "0,1" textline " " bitfld.long 0x00 1. " GMB833 ,Group Modifier Bit 833" "0,1" bitfld.long 0x00 0. " GMB832 ,Group Modifier Bit 832" "0,1" else hgroup.long 0x0D68++0x03 hide.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D6C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x0D6C++0x03 line.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27" bitfld.long 0x00 31. " GMB895 ,Group Modifier Bit 895" "0,1" bitfld.long 0x00 30. " GMB894 ,Group Modifier Bit 894" "0,1" bitfld.long 0x00 29. " GMB893 ,Group Modifier Bit 893" "0,1" textline " " bitfld.long 0x00 28. " GMB892 ,Group Modifier Bit 892" "0,1" bitfld.long 0x00 27. " GMB891 ,Group Modifier Bit 891" "0,1" bitfld.long 0x00 26. " GMB890 ,Group Modifier Bit 890" "0,1" textline " " bitfld.long 0x00 25. " GMB889 ,Group Modifier Bit 889" "0,1" bitfld.long 0x00 24. " GMB888 ,Group Modifier Bit 888" "0,1" bitfld.long 0x00 23. " GMB887 ,Group Modifier Bit 887" "0,1" textline " " bitfld.long 0x00 22. " GMB886 ,Group Modifier Bit 886" "0,1" bitfld.long 0x00 21. " GMB885 ,Group Modifier Bit 885" "0,1" bitfld.long 0x00 20. " GMB884 ,Group Modifier Bit 884" "0,1" textline " " bitfld.long 0x00 19. " GMB883 ,Group Modifier Bit 883" "0,1" bitfld.long 0x00 18. " GMB882 ,Group Modifier Bit 882" "0,1" bitfld.long 0x00 17. " GMB881 ,Group Modifier Bit 881" "0,1" textline " " bitfld.long 0x00 16. " GMB880 ,Group Modifier Bit 880" "0,1" bitfld.long 0x00 15. " GMB879 ,Group Modifier Bit 879" "0,1" bitfld.long 0x00 14. " GMB878 ,Group Modifier Bit 878" "0,1" textline " " bitfld.long 0x00 13. " GMB877 ,Group Modifier Bit 877" "0,1" bitfld.long 0x00 12. " GMB876 ,Group Modifier Bit 876" "0,1" bitfld.long 0x00 11. " GMB875 ,Group Modifier Bit 875" "0,1" textline " " bitfld.long 0x00 10. " GMB874 ,Group Modifier Bit 874" "0,1" bitfld.long 0x00 9. " GMB873 ,Group Modifier Bit 873" "0,1" bitfld.long 0x00 8. " GMB872 ,Group Modifier Bit 872" "0,1" textline " " bitfld.long 0x00 7. " GMB871 ,Group Modifier Bit 871" "0,1" bitfld.long 0x00 6. " GMB870 ,Group Modifier Bit 870" "0,1" bitfld.long 0x00 5. " GMB869 ,Group Modifier Bit 869" "0,1" textline " " bitfld.long 0x00 4. " GMB868 ,Group Modifier Bit 868" "0,1" bitfld.long 0x00 3. " GMB867 ,Group Modifier Bit 867" "0,1" bitfld.long 0x00 2. " GMB866 ,Group Modifier Bit 866" "0,1" textline " " bitfld.long 0x00 1. " GMB865 ,Group Modifier Bit 865" "0,1" bitfld.long 0x00 0. " GMB864 ,Group Modifier Bit 864" "0,1" else hgroup.long 0x0D6C++0x03 hide.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D70))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x0D70++0x03 line.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28" bitfld.long 0x00 31. " GMB927 ,Group Modifier Bit 927" "0,1" bitfld.long 0x00 30. " GMB926 ,Group Modifier Bit 926" "0,1" bitfld.long 0x00 29. " GMB925 ,Group Modifier Bit 925" "0,1" textline " " bitfld.long 0x00 28. " GMB924 ,Group Modifier Bit 924" "0,1" bitfld.long 0x00 27. " GMB923 ,Group Modifier Bit 923" "0,1" bitfld.long 0x00 26. " GMB922 ,Group Modifier Bit 922" "0,1" textline " " bitfld.long 0x00 25. " GMB921 ,Group Modifier Bit 921" "0,1" bitfld.long 0x00 24. " GMB920 ,Group Modifier Bit 920" "0,1" bitfld.long 0x00 23. " GMB919 ,Group Modifier Bit 919" "0,1" textline " " bitfld.long 0x00 22. " GMB918 ,Group Modifier Bit 918" "0,1" bitfld.long 0x00 21. " GMB917 ,Group Modifier Bit 917" "0,1" bitfld.long 0x00 20. " GMB916 ,Group Modifier Bit 916" "0,1" textline " " bitfld.long 0x00 19. " GMB915 ,Group Modifier Bit 915" "0,1" bitfld.long 0x00 18. " GMB914 ,Group Modifier Bit 914" "0,1" bitfld.long 0x00 17. " GMB913 ,Group Modifier Bit 913" "0,1" textline " " bitfld.long 0x00 16. " GMB912 ,Group Modifier Bit 912" "0,1" bitfld.long 0x00 15. " GMB911 ,Group Modifier Bit 911" "0,1" bitfld.long 0x00 14. " GMB910 ,Group Modifier Bit 910" "0,1" textline " " bitfld.long 0x00 13. " GMB909 ,Group Modifier Bit 909" "0,1" bitfld.long 0x00 12. " GMB908 ,Group Modifier Bit 908" "0,1" bitfld.long 0x00 11. " GMB907 ,Group Modifier Bit 907" "0,1" textline " " bitfld.long 0x00 10. " GMB906 ,Group Modifier Bit 906" "0,1" bitfld.long 0x00 9. " GMB905 ,Group Modifier Bit 905" "0,1" bitfld.long 0x00 8. " GMB904 ,Group Modifier Bit 904" "0,1" textline " " bitfld.long 0x00 7. " GMB903 ,Group Modifier Bit 903" "0,1" bitfld.long 0x00 6. " GMB902 ,Group Modifier Bit 902" "0,1" bitfld.long 0x00 5. " GMB901 ,Group Modifier Bit 901" "0,1" textline " " bitfld.long 0x00 4. " GMB900 ,Group Modifier Bit 900" "0,1" bitfld.long 0x00 3. " GMB899 ,Group Modifier Bit 899" "0,1" bitfld.long 0x00 2. " GMB898 ,Group Modifier Bit 898" "0,1" textline " " bitfld.long 0x00 1. " GMB897 ,Group Modifier Bit 897" "0,1" bitfld.long 0x00 0. " GMB896 ,Group Modifier Bit 896" "0,1" else hgroup.long 0x0D70++0x03 hide.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D74))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x0D74++0x03 line.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29" bitfld.long 0x00 31. " GMB959 ,Group Modifier Bit 959" "0,1" bitfld.long 0x00 30. " GMB958 ,Group Modifier Bit 958" "0,1" bitfld.long 0x00 29. " GMB957 ,Group Modifier Bit 957" "0,1" textline " " bitfld.long 0x00 28. " GMB956 ,Group Modifier Bit 956" "0,1" bitfld.long 0x00 27. " GMB955 ,Group Modifier Bit 955" "0,1" bitfld.long 0x00 26. " GMB954 ,Group Modifier Bit 954" "0,1" textline " " bitfld.long 0x00 25. " GMB953 ,Group Modifier Bit 953" "0,1" bitfld.long 0x00 24. " GMB952 ,Group Modifier Bit 952" "0,1" bitfld.long 0x00 23. " GMB951 ,Group Modifier Bit 951" "0,1" textline " " bitfld.long 0x00 22. " GMB950 ,Group Modifier Bit 950" "0,1" bitfld.long 0x00 21. " GMB949 ,Group Modifier Bit 949" "0,1" bitfld.long 0x00 20. " GMB948 ,Group Modifier Bit 948" "0,1" textline " " bitfld.long 0x00 19. " GMB947 ,Group Modifier Bit 947" "0,1" bitfld.long 0x00 18. " GMB946 ,Group Modifier Bit 946" "0,1" bitfld.long 0x00 17. " GMB945 ,Group Modifier Bit 945" "0,1" textline " " bitfld.long 0x00 16. " GMB944 ,Group Modifier Bit 944" "0,1" bitfld.long 0x00 15. " GMB943 ,Group Modifier Bit 943" "0,1" bitfld.long 0x00 14. " GMB942 ,Group Modifier Bit 942" "0,1" textline " " bitfld.long 0x00 13. " GMB941 ,Group Modifier Bit 941" "0,1" bitfld.long 0x00 12. " GMB940 ,Group Modifier Bit 940" "0,1" bitfld.long 0x00 11. " GMB939 ,Group Modifier Bit 939" "0,1" textline " " bitfld.long 0x00 10. " GMB938 ,Group Modifier Bit 938" "0,1" bitfld.long 0x00 9. " GMB937 ,Group Modifier Bit 937" "0,1" bitfld.long 0x00 8. " GMB936 ,Group Modifier Bit 936" "0,1" textline " " bitfld.long 0x00 7. " GMB935 ,Group Modifier Bit 935" "0,1" bitfld.long 0x00 6. " GMB934 ,Group Modifier Bit 934" "0,1" bitfld.long 0x00 5. " GMB933 ,Group Modifier Bit 933" "0,1" textline " " bitfld.long 0x00 4. " GMB932 ,Group Modifier Bit 932" "0,1" bitfld.long 0x00 3. " GMB931 ,Group Modifier Bit 931" "0,1" bitfld.long 0x00 2. " GMB930 ,Group Modifier Bit 930" "0,1" textline " " bitfld.long 0x00 1. " GMB929 ,Group Modifier Bit 929" "0,1" bitfld.long 0x00 0. " GMB928 ,Group Modifier Bit 928" "0,1" else hgroup.long 0x0D74++0x03 hide.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D78))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x0D78++0x03 line.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30" bitfld.long 0x00 31. " GMB991 ,Group Modifier Bit 991" "0,1" bitfld.long 0x00 30. " GMB990 ,Group Modifier Bit 990" "0,1" bitfld.long 0x00 29. " GMB989 ,Group Modifier Bit 989" "0,1" textline " " bitfld.long 0x00 28. " GMB988 ,Group Modifier Bit 988" "0,1" bitfld.long 0x00 27. " GMB987 ,Group Modifier Bit 987" "0,1" bitfld.long 0x00 26. " GMB986 ,Group Modifier Bit 986" "0,1" textline " " bitfld.long 0x00 25. " GMB985 ,Group Modifier Bit 985" "0,1" bitfld.long 0x00 24. " GMB984 ,Group Modifier Bit 984" "0,1" bitfld.long 0x00 23. " GMB983 ,Group Modifier Bit 983" "0,1" textline " " bitfld.long 0x00 22. " GMB982 ,Group Modifier Bit 982" "0,1" bitfld.long 0x00 21. " GMB981 ,Group Modifier Bit 981" "0,1" bitfld.long 0x00 20. " GMB980 ,Group Modifier Bit 980" "0,1" textline " " bitfld.long 0x00 19. " GMB979 ,Group Modifier Bit 979" "0,1" bitfld.long 0x00 18. " GMB978 ,Group Modifier Bit 978" "0,1" bitfld.long 0x00 17. " GMB977 ,Group Modifier Bit 977" "0,1" textline " " bitfld.long 0x00 16. " GMB976 ,Group Modifier Bit 976" "0,1" bitfld.long 0x00 15. " GMB975 ,Group Modifier Bit 975" "0,1" bitfld.long 0x00 14. " GMB974 ,Group Modifier Bit 974" "0,1" textline " " bitfld.long 0x00 13. " GMB973 ,Group Modifier Bit 973" "0,1" bitfld.long 0x00 12. " GMB972 ,Group Modifier Bit 972" "0,1" bitfld.long 0x00 11. " GMB971 ,Group Modifier Bit 971" "0,1" textline " " bitfld.long 0x00 10. " GMB970 ,Group Modifier Bit 970" "0,1" bitfld.long 0x00 9. " GMB969 ,Group Modifier Bit 969" "0,1" bitfld.long 0x00 8. " GMB968 ,Group Modifier Bit 968" "0,1" textline " " bitfld.long 0x00 7. " GMB967 ,Group Modifier Bit 967" "0,1" bitfld.long 0x00 6. " GMB966 ,Group Modifier Bit 966" "0,1" bitfld.long 0x00 5. " GMB965 ,Group Modifier Bit 965" "0,1" textline " " bitfld.long 0x00 4. " GMB964 ,Group Modifier Bit 964" "0,1" bitfld.long 0x00 3. " GMB963 ,Group Modifier Bit 963" "0,1" bitfld.long 0x00 2. " GMB962 ,Group Modifier Bit 962" "0,1" textline " " bitfld.long 0x00 1. " GMB961 ,Group Modifier Bit 961" "0,1" bitfld.long 0x00 0. " GMB960 ,Group Modifier Bit 960" "0,1" else hgroup.long 0x0D78++0x03 hide.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30" endif tree.end width 14. tree "Non-secure Access Control Registers" hgroup.long 0x0E00++0x03 hide.long 0x00 "GICD_NSACR0,Non-secure Access Control Register 0" hgroup.long 0xE04++0x03 hide.long 0x00 "GICD_NSACR1,Non-secure Access Control Register 1" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE08))) group.long 0xE08++0x03 line.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2" bitfld.long 0x00 30.--31. " NS_ACCESS47 ,Controls Non-secure access of the interrupt with ID47 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS46 ,Controls Non-secure access of the interrupt with ID46 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS45 ,Controls Non-secure access of the interrupt with ID45 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS44 ,Controls Non-secure access of the interrupt with ID44 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS43 ,Controls Non-secure access of the interrupt with ID43 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS42 ,Controls Non-secure access of the interrupt with ID42 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS41 ,Controls Non-secure access of the interrupt with ID41 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS40 ,Controls Non-secure access of the interrupt with ID40 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS39 ,Controls Non-secure access of the interrupt with ID39 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS38 ,Controls Non-secure access of the interrupt with ID38 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS37 ,Controls Non-secure access of the interrupt with ID37 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS36 ,Controls Non-secure access of the interrupt with ID36 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS35 ,Controls Non-secure access of the interrupt with ID35 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS34 ,Controls Non-secure access of the interrupt with ID34 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS33 ,Controls Non-secure access of the interrupt with ID33 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS32 ,Controls Non-secure access of the interrupt with ID32 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE08++0x03 hide.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0C))) group.long 0xE0C++0x03 line.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3" bitfld.long 0x00 30.--31. " NS_ACCESS63 ,Controls Non-secure access of the interrupt with ID63 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS62 ,Controls Non-secure access of the interrupt with ID62 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS61 ,Controls Non-secure access of the interrupt with ID61 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS60 ,Controls Non-secure access of the interrupt with ID60 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS59 ,Controls Non-secure access of the interrupt with ID59 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS58 ,Controls Non-secure access of the interrupt with ID58 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS57 ,Controls Non-secure access of the interrupt with ID57 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS56 ,Controls Non-secure access of the interrupt with ID56 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS55 ,Controls Non-secure access of the interrupt with ID55 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS54 ,Controls Non-secure access of the interrupt with ID54 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS53 ,Controls Non-secure access of the interrupt with ID53 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS52 ,Controls Non-secure access of the interrupt with ID52 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS51 ,Controls Non-secure access of the interrupt with ID51 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS50 ,Controls Non-secure access of the interrupt with ID50 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS49 ,Controls Non-secure access of the interrupt with ID49 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS48 ,Controls Non-secure access of the interrupt with ID48 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE0C++0x03 hide.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE10))) group.long 0xE10++0x03 line.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4" bitfld.long 0x00 30.--31. " NS_ACCESS79 ,Controls Non-secure access of the interrupt with ID79 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS78 ,Controls Non-secure access of the interrupt with ID78 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS77 ,Controls Non-secure access of the interrupt with ID77 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS76 ,Controls Non-secure access of the interrupt with ID76 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS75 ,Controls Non-secure access of the interrupt with ID75 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS74 ,Controls Non-secure access of the interrupt with ID74 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS73 ,Controls Non-secure access of the interrupt with ID73 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS72 ,Controls Non-secure access of the interrupt with ID72 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS71 ,Controls Non-secure access of the interrupt with ID71 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS70 ,Controls Non-secure access of the interrupt with ID70 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS69 ,Controls Non-secure access of the interrupt with ID69 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS68 ,Controls Non-secure access of the interrupt with ID68 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS67 ,Controls Non-secure access of the interrupt with ID67 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS66 ,Controls Non-secure access of the interrupt with ID66 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS65 ,Controls Non-secure access of the interrupt with ID65 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS64 ,Controls Non-secure access of the interrupt with ID64 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE10++0x03 hide.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE14))) group.long 0xE14++0x03 line.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5" bitfld.long 0x00 30.--31. " NS_ACCESS95 ,Controls Non-secure access of the interrupt with ID95 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS94 ,Controls Non-secure access of the interrupt with ID94 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS93 ,Controls Non-secure access of the interrupt with ID93 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS92 ,Controls Non-secure access of the interrupt with ID92 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS91 ,Controls Non-secure access of the interrupt with ID91 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS90 ,Controls Non-secure access of the interrupt with ID90 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS89 ,Controls Non-secure access of the interrupt with ID89 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS88 ,Controls Non-secure access of the interrupt with ID88 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS87 ,Controls Non-secure access of the interrupt with ID87 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS86 ,Controls Non-secure access of the interrupt with ID86 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS85 ,Controls Non-secure access of the interrupt with ID85 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS84 ,Controls Non-secure access of the interrupt with ID84 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS83 ,Controls Non-secure access of the interrupt with ID83 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS82 ,Controls Non-secure access of the interrupt with ID82 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS81 ,Controls Non-secure access of the interrupt with ID81 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS80 ,Controls Non-secure access of the interrupt with ID80 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE14++0x03 hide.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE18))) group.long 0xE18++0x03 line.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6" bitfld.long 0x00 30.--31. " NS_ACCESS111 ,Controls Non-secure access of the interrupt with ID111" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS110 ,Controls Non-secure access of the interrupt with ID110" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS109 ,Controls Non-secure access of the interrupt with ID109" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS108 ,Controls Non-secure access of the interrupt with ID108" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS107 ,Controls Non-secure access of the interrupt with ID107" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS106 ,Controls Non-secure access of the interrupt with ID106" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS105 ,Controls Non-secure access of the interrupt with ID105" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS104 ,Controls Non-secure access of the interrupt with ID104" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS103 ,Controls Non-secure access of the interrupt with ID103" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS102 ,Controls Non-secure access of the interrupt with ID102" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS101 ,Controls Non-secure access of the interrupt with ID101" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS100 ,Controls Non-secure access of the interrupt with ID100" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS99 ,Controls Non-secure access of the interrupt with ID99 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS98 ,Controls Non-secure access of the interrupt with ID98 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS97 ,Controls Non-secure access of the interrupt with ID97 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS96 ,Controls Non-secure access of the interrupt with ID96 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE18++0x03 hide.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE1C))) group.long 0xE1C++0x03 line.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7" bitfld.long 0x00 30.--31. " NS_ACCESS127 ,Controls Non-secure access of the interrupt with ID127" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS126 ,Controls Non-secure access of the interrupt with ID126" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS125 ,Controls Non-secure access of the interrupt with ID125" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS124 ,Controls Non-secure access of the interrupt with ID124" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS123 ,Controls Non-secure access of the interrupt with ID123" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS122 ,Controls Non-secure access of the interrupt with ID122" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS121 ,Controls Non-secure access of the interrupt with ID121" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS120 ,Controls Non-secure access of the interrupt with ID120" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS119 ,Controls Non-secure access of the interrupt with ID119" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS118 ,Controls Non-secure access of the interrupt with ID118" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS117 ,Controls Non-secure access of the interrupt with ID117" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS116 ,Controls Non-secure access of the interrupt with ID116" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS115 ,Controls Non-secure access of the interrupt with ID115" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS114 ,Controls Non-secure access of the interrupt with ID114" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS113 ,Controls Non-secure access of the interrupt with ID113" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS112 ,Controls Non-secure access of the interrupt with ID112" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE1C++0x03 hide.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE20))) group.long 0xE20++0x03 line.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8" bitfld.long 0x00 30.--31. " NS_ACCESS143 ,Controls Non-secure access of the interrupt with ID143" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS142 ,Controls Non-secure access of the interrupt with ID142" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS141 ,Controls Non-secure access of the interrupt with ID141" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS140 ,Controls Non-secure access of the interrupt with ID140" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS139 ,Controls Non-secure access of the interrupt with ID139" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS138 ,Controls Non-secure access of the interrupt with ID138" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS137 ,Controls Non-secure access of the interrupt with ID137" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS136 ,Controls Non-secure access of the interrupt with ID136" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS135 ,Controls Non-secure access of the interrupt with ID135" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS134 ,Controls Non-secure access of the interrupt with ID134" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS133 ,Controls Non-secure access of the interrupt with ID133" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS132 ,Controls Non-secure access of the interrupt with ID132" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS131 ,Controls Non-secure access of the interrupt with ID131" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS130 ,Controls Non-secure access of the interrupt with ID130" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS129 ,Controls Non-secure access of the interrupt with ID129" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS128 ,Controls Non-secure access of the interrupt with ID128" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE20++0x03 hide.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE24))) group.long 0xE24++0x03 line.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9" bitfld.long 0x00 30.--31. " NS_ACCESS159 ,Controls Non-secure access of the interrupt with ID159" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS158 ,Controls Non-secure access of the interrupt with ID158" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS157 ,Controls Non-secure access of the interrupt with ID157" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS156 ,Controls Non-secure access of the interrupt with ID156" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS155 ,Controls Non-secure access of the interrupt with ID155" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS154 ,Controls Non-secure access of the interrupt with ID154" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS153 ,Controls Non-secure access of the interrupt with ID153" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS152 ,Controls Non-secure access of the interrupt with ID152" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS151 ,Controls Non-secure access of the interrupt with ID151" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS150 ,Controls Non-secure access of the interrupt with ID150" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS149 ,Controls Non-secure access of the interrupt with ID149" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS148 ,Controls Non-secure access of the interrupt with ID148" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS147 ,Controls Non-secure access of the interrupt with ID147" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS146 ,Controls Non-secure access of the interrupt with ID146" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS145 ,Controls Non-secure access of the interrupt with ID145" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS144 ,Controls Non-secure access of the interrupt with ID144" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE24++0x03 hide.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE28))) group.long 0xE28++0x03 line.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10" bitfld.long 0x00 30.--31. " NS_ACCESS175 ,Controls Non-secure access of the interrupt with ID175" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS174 ,Controls Non-secure access of the interrupt with ID174" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS173 ,Controls Non-secure access of the interrupt with ID173" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS172 ,Controls Non-secure access of the interrupt with ID172" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS171 ,Controls Non-secure access of the interrupt with ID171" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS170 ,Controls Non-secure access of the interrupt with ID170" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS169 ,Controls Non-secure access of the interrupt with ID169" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS168 ,Controls Non-secure access of the interrupt with ID168" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS167 ,Controls Non-secure access of the interrupt with ID167" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS166 ,Controls Non-secure access of the interrupt with ID166" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS165 ,Controls Non-secure access of the interrupt with ID165" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS164 ,Controls Non-secure access of the interrupt with ID164" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS163 ,Controls Non-secure access of the interrupt with ID163" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS162 ,Controls Non-secure access of the interrupt with ID162" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS161 ,Controls Non-secure access of the interrupt with ID161" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS160 ,Controls Non-secure access of the interrupt with ID160" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE28++0x03 hide.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE2C))) group.long 0xE2C++0x03 line.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11" bitfld.long 0x00 30.--31. " NS_ACCESS191 ,Controls Non-secure access of the interrupt with ID191" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS190 ,Controls Non-secure access of the interrupt with ID190" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS189 ,Controls Non-secure access of the interrupt with ID189" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS188 ,Controls Non-secure access of the interrupt with ID188" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS187 ,Controls Non-secure access of the interrupt with ID187" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS186 ,Controls Non-secure access of the interrupt with ID186" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS185 ,Controls Non-secure access of the interrupt with ID185" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS184 ,Controls Non-secure access of the interrupt with ID184" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS183 ,Controls Non-secure access of the interrupt with ID183" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS182 ,Controls Non-secure access of the interrupt with ID182" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS181 ,Controls Non-secure access of the interrupt with ID181" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS180 ,Controls Non-secure access of the interrupt with ID180" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS179 ,Controls Non-secure access of the interrupt with ID179" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS178 ,Controls Non-secure access of the interrupt with ID178" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS177 ,Controls Non-secure access of the interrupt with ID177" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS176 ,Controls Non-secure access of the interrupt with ID176" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE2C++0x03 hide.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE30))) group.long 0xE30++0x03 line.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12" bitfld.long 0x00 30.--31. " NS_ACCESS207 ,Controls Non-secure access of the interrupt with ID207" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS206 ,Controls Non-secure access of the interrupt with ID206" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS205 ,Controls Non-secure access of the interrupt with ID205" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS204 ,Controls Non-secure access of the interrupt with ID204" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS203 ,Controls Non-secure access of the interrupt with ID203" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS202 ,Controls Non-secure access of the interrupt with ID202" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS201 ,Controls Non-secure access of the interrupt with ID201" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS200 ,Controls Non-secure access of the interrupt with ID200" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS199 ,Controls Non-secure access of the interrupt with ID199" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS198 ,Controls Non-secure access of the interrupt with ID198" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS197 ,Controls Non-secure access of the interrupt with ID197" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS196 ,Controls Non-secure access of the interrupt with ID196" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS195 ,Controls Non-secure access of the interrupt with ID195" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS194 ,Controls Non-secure access of the interrupt with ID194" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS193 ,Controls Non-secure access of the interrupt with ID193" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS192 ,Controls Non-secure access of the interrupt with ID192" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE30++0x03 hide.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE34))) group.long 0xE34++0x03 line.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13" bitfld.long 0x00 30.--31. " NS_ACCESS223 ,Controls Non-secure access of the interrupt with ID223" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS222 ,Controls Non-secure access of the interrupt with ID222" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS221 ,Controls Non-secure access of the interrupt with ID221" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS220 ,Controls Non-secure access of the interrupt with ID220" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS219 ,Controls Non-secure access of the interrupt with ID219" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS218 ,Controls Non-secure access of the interrupt with ID218" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS217 ,Controls Non-secure access of the interrupt with ID217" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS216 ,Controls Non-secure access of the interrupt with ID216" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS215 ,Controls Non-secure access of the interrupt with ID215" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS214 ,Controls Non-secure access of the interrupt with ID214" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS213 ,Controls Non-secure access of the interrupt with ID213" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS212 ,Controls Non-secure access of the interrupt with ID212" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS211 ,Controls Non-secure access of the interrupt with ID211" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS210 ,Controls Non-secure access of the interrupt with ID210" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS209 ,Controls Non-secure access of the interrupt with ID209" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS208 ,Controls Non-secure access of the interrupt with ID208" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE34++0x03 hide.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE38))) group.long 0xE38++0x03 line.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14" bitfld.long 0x00 30.--31. " NS_ACCESS239 ,Controls Non-secure access of the interrupt with ID239" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS238 ,Controls Non-secure access of the interrupt with ID238" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS237 ,Controls Non-secure access of the interrupt with ID237" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS236 ,Controls Non-secure access of the interrupt with ID236" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS235 ,Controls Non-secure access of the interrupt with ID235" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS234 ,Controls Non-secure access of the interrupt with ID234" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS233 ,Controls Non-secure access of the interrupt with ID233" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS232 ,Controls Non-secure access of the interrupt with ID232" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS231 ,Controls Non-secure access of the interrupt with ID231" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS230 ,Controls Non-secure access of the interrupt with ID230" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS229 ,Controls Non-secure access of the interrupt with ID229" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS228 ,Controls Non-secure access of the interrupt with ID228" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS227 ,Controls Non-secure access of the interrupt with ID227" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS226 ,Controls Non-secure access of the interrupt with ID226" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS225 ,Controls Non-secure access of the interrupt with ID225" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS224 ,Controls Non-secure access of the interrupt with ID224" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE38++0x03 hide.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE3C))) group.long 0xE3C++0x03 line.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15" bitfld.long 0x00 30.--31. " NS_ACCESS255 ,Controls Non-secure access of the interrupt with ID255" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS254 ,Controls Non-secure access of the interrupt with ID254" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS253 ,Controls Non-secure access of the interrupt with ID253" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS252 ,Controls Non-secure access of the interrupt with ID252" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS251 ,Controls Non-secure access of the interrupt with ID251" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS250 ,Controls Non-secure access of the interrupt with ID250" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS249 ,Controls Non-secure access of the interrupt with ID249" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS248 ,Controls Non-secure access of the interrupt with ID248" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS247 ,Controls Non-secure access of the interrupt with ID247" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS246 ,Controls Non-secure access of the interrupt with ID246" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS245 ,Controls Non-secure access of the interrupt with ID245" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS244 ,Controls Non-secure access of the interrupt with ID244" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS243 ,Controls Non-secure access of the interrupt with ID243" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS242 ,Controls Non-secure access of the interrupt with ID242" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS241 ,Controls Non-secure access of the interrupt with ID241" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS240 ,Controls Non-secure access of the interrupt with ID240" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE3C++0x03 hide.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE40))) group.long 0xE40++0x03 line.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16" bitfld.long 0x00 30.--31. " NS_ACCESS271 ,Controls Non-secure access of the interrupt with ID271" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS270 ,Controls Non-secure access of the interrupt with ID270" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS269 ,Controls Non-secure access of the interrupt with ID269" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS268 ,Controls Non-secure access of the interrupt with ID268" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS267 ,Controls Non-secure access of the interrupt with ID267" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS266 ,Controls Non-secure access of the interrupt with ID266" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS265 ,Controls Non-secure access of the interrupt with ID265" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS264 ,Controls Non-secure access of the interrupt with ID264" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS263 ,Controls Non-secure access of the interrupt with ID263" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS262 ,Controls Non-secure access of the interrupt with ID262" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS261 ,Controls Non-secure access of the interrupt with ID261" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS260 ,Controls Non-secure access of the interrupt with ID260" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS259 ,Controls Non-secure access of the interrupt with ID259" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS258 ,Controls Non-secure access of the interrupt with ID258" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS257 ,Controls Non-secure access of the interrupt with ID257" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS256 ,Controls Non-secure access of the interrupt with ID256" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE40++0x03 hide.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE44))) group.long 0xE44++0x03 line.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17" bitfld.long 0x00 30.--31. " NS_ACCESS287 ,Controls Non-secure access of the interrupt with ID287" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS286 ,Controls Non-secure access of the interrupt with ID286" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS285 ,Controls Non-secure access of the interrupt with ID285" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS284 ,Controls Non-secure access of the interrupt with ID284" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS283 ,Controls Non-secure access of the interrupt with ID283" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS282 ,Controls Non-secure access of the interrupt with ID282" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS281 ,Controls Non-secure access of the interrupt with ID281" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS280 ,Controls Non-secure access of the interrupt with ID280" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS279 ,Controls Non-secure access of the interrupt with ID279" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS278 ,Controls Non-secure access of the interrupt with ID278" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS277 ,Controls Non-secure access of the interrupt with ID277" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS276 ,Controls Non-secure access of the interrupt with ID276" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS275 ,Controls Non-secure access of the interrupt with ID275" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS274 ,Controls Non-secure access of the interrupt with ID274" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS273 ,Controls Non-secure access of the interrupt with ID273" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS272 ,Controls Non-secure access of the interrupt with ID272" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE44++0x03 hide.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE48))) group.long 0xE48++0x03 line.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18" bitfld.long 0x00 30.--31. " NS_ACCESS303 ,Controls Non-secure access of the interrupt with ID303" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS302 ,Controls Non-secure access of the interrupt with ID302" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS301 ,Controls Non-secure access of the interrupt with ID301" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS300 ,Controls Non-secure access of the interrupt with ID300" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS299 ,Controls Non-secure access of the interrupt with ID299" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS298 ,Controls Non-secure access of the interrupt with ID298" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS297 ,Controls Non-secure access of the interrupt with ID297" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS296 ,Controls Non-secure access of the interrupt with ID296" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS295 ,Controls Non-secure access of the interrupt with ID295" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS294 ,Controls Non-secure access of the interrupt with ID294" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS293 ,Controls Non-secure access of the interrupt with ID293" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS292 ,Controls Non-secure access of the interrupt with ID292" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS291 ,Controls Non-secure access of the interrupt with ID291" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS290 ,Controls Non-secure access of the interrupt with ID290" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS289 ,Controls Non-secure access of the interrupt with ID289" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS288 ,Controls Non-secure access of the interrupt with ID288" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE48++0x03 hide.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4C))) group.long 0xE4C++0x03 line.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19" bitfld.long 0x00 30.--31. " NS_ACCESS319 ,Controls Non-secure access of the interrupt with ID319" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS318 ,Controls Non-secure access of the interrupt with ID318" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS317 ,Controls Non-secure access of the interrupt with ID317" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS316 ,Controls Non-secure access of the interrupt with ID316" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS315 ,Controls Non-secure access of the interrupt with ID315" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS314 ,Controls Non-secure access of the interrupt with ID314" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS313 ,Controls Non-secure access of the interrupt with ID313" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS312 ,Controls Non-secure access of the interrupt with ID312" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS311 ,Controls Non-secure access of the interrupt with ID311" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS310 ,Controls Non-secure access of the interrupt with ID310" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS309 ,Controls Non-secure access of the interrupt with ID309" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS308 ,Controls Non-secure access of the interrupt with ID308" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS307 ,Controls Non-secure access of the interrupt with ID307" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS306 ,Controls Non-secure access of the interrupt with ID306" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS305 ,Controls Non-secure access of the interrupt with ID305" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS304 ,Controls Non-secure access of the interrupt with ID304" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE4C++0x03 hide.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE50))) group.long 0xE50++0x03 line.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20" bitfld.long 0x00 30.--31. " NS_ACCESS335 ,Controls Non-secure access of the interrupt with ID335" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS334 ,Controls Non-secure access of the interrupt with ID334" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS333 ,Controls Non-secure access of the interrupt with ID333" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS332 ,Controls Non-secure access of the interrupt with ID332" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS331 ,Controls Non-secure access of the interrupt with ID331" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS330 ,Controls Non-secure access of the interrupt with ID330" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS329 ,Controls Non-secure access of the interrupt with ID329" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS328 ,Controls Non-secure access of the interrupt with ID328" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS327 ,Controls Non-secure access of the interrupt with ID327" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS326 ,Controls Non-secure access of the interrupt with ID326" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS325 ,Controls Non-secure access of the interrupt with ID325" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS324 ,Controls Non-secure access of the interrupt with ID324" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS323 ,Controls Non-secure access of the interrupt with ID323" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS322 ,Controls Non-secure access of the interrupt with ID322" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS321 ,Controls Non-secure access of the interrupt with ID321" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS320 ,Controls Non-secure access of the interrupt with ID320" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE50++0x03 hide.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE54))) group.long 0xE54++0x03 line.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21" bitfld.long 0x00 30.--31. " NS_ACCESS351 ,Controls Non-secure access of the interrupt with ID351" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS350 ,Controls Non-secure access of the interrupt with ID350" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS349 ,Controls Non-secure access of the interrupt with ID349" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS348 ,Controls Non-secure access of the interrupt with ID348" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS347 ,Controls Non-secure access of the interrupt with ID347" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS346 ,Controls Non-secure access of the interrupt with ID346" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS345 ,Controls Non-secure access of the interrupt with ID345" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS344 ,Controls Non-secure access of the interrupt with ID344" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS343 ,Controls Non-secure access of the interrupt with ID343" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS342 ,Controls Non-secure access of the interrupt with ID342" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS341 ,Controls Non-secure access of the interrupt with ID341" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS340 ,Controls Non-secure access of the interrupt with ID340" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS339 ,Controls Non-secure access of the interrupt with ID339" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS338 ,Controls Non-secure access of the interrupt with ID338" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS337 ,Controls Non-secure access of the interrupt with ID337" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS336 ,Controls Non-secure access of the interrupt with ID336" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE54++0x03 hide.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE58))) group.long 0xE58++0x03 line.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22" bitfld.long 0x00 30.--31. " NS_ACCESS367 ,Controls Non-secure access of the interrupt with ID367" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS366 ,Controls Non-secure access of the interrupt with ID366" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS365 ,Controls Non-secure access of the interrupt with ID365" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS364 ,Controls Non-secure access of the interrupt with ID364" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS363 ,Controls Non-secure access of the interrupt with ID363" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS362 ,Controls Non-secure access of the interrupt with ID362" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS361 ,Controls Non-secure access of the interrupt with ID361" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS360 ,Controls Non-secure access of the interrupt with ID360" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS359 ,Controls Non-secure access of the interrupt with ID359" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS358 ,Controls Non-secure access of the interrupt with ID358" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS357 ,Controls Non-secure access of the interrupt with ID357" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS356 ,Controls Non-secure access of the interrupt with ID356" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS355 ,Controls Non-secure access of the interrupt with ID355" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS354 ,Controls Non-secure access of the interrupt with ID354" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS353 ,Controls Non-secure access of the interrupt with ID353" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS352 ,Controls Non-secure access of the interrupt with ID352" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE58++0x03 hide.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE5C))) group.long 0xE5C++0x03 line.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23" bitfld.long 0x00 30.--31. " NS_ACCESS383 ,Controls Non-secure access of the interrupt with ID383" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS382 ,Controls Non-secure access of the interrupt with ID382" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS381 ,Controls Non-secure access of the interrupt with ID381" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS380 ,Controls Non-secure access of the interrupt with ID380" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS379 ,Controls Non-secure access of the interrupt with ID379" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS378 ,Controls Non-secure access of the interrupt with ID378" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS377 ,Controls Non-secure access of the interrupt with ID377" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS376 ,Controls Non-secure access of the interrupt with ID376" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS375 ,Controls Non-secure access of the interrupt with ID375" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS374 ,Controls Non-secure access of the interrupt with ID374" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS373 ,Controls Non-secure access of the interrupt with ID373" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS372 ,Controls Non-secure access of the interrupt with ID372" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS371 ,Controls Non-secure access of the interrupt with ID371" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS370 ,Controls Non-secure access of the interrupt with ID370" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS369 ,Controls Non-secure access of the interrupt with ID369" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS368 ,Controls Non-secure access of the interrupt with ID368" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE5C++0x03 hide.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE60))) group.long 0xE60++0x03 line.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24" bitfld.long 0x00 30.--31. " NS_ACCESS399 ,Controls Non-secure access of the interrupt with ID399" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS398 ,Controls Non-secure access of the interrupt with ID398" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS397 ,Controls Non-secure access of the interrupt with ID397" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS396 ,Controls Non-secure access of the interrupt with ID396" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS395 ,Controls Non-secure access of the interrupt with ID395" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS394 ,Controls Non-secure access of the interrupt with ID394" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS393 ,Controls Non-secure access of the interrupt with ID393" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS392 ,Controls Non-secure access of the interrupt with ID392" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS391 ,Controls Non-secure access of the interrupt with ID391" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS390 ,Controls Non-secure access of the interrupt with ID390" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS389 ,Controls Non-secure access of the interrupt with ID389" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS388 ,Controls Non-secure access of the interrupt with ID388" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS387 ,Controls Non-secure access of the interrupt with ID387" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS386 ,Controls Non-secure access of the interrupt with ID386" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS385 ,Controls Non-secure access of the interrupt with ID385" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS384 ,Controls Non-secure access of the interrupt with ID384" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE60++0x03 hide.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE64))) group.long 0xE64++0x03 line.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25" bitfld.long 0x00 30.--31. " NS_ACCESS415 ,Controls Non-secure access of the interrupt with ID415" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS414 ,Controls Non-secure access of the interrupt with ID414" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS413 ,Controls Non-secure access of the interrupt with ID413" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS412 ,Controls Non-secure access of the interrupt with ID412" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS411 ,Controls Non-secure access of the interrupt with ID411" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS410 ,Controls Non-secure access of the interrupt with ID410" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS409 ,Controls Non-secure access of the interrupt with ID409" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS408 ,Controls Non-secure access of the interrupt with ID408" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS407 ,Controls Non-secure access of the interrupt with ID407" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS406 ,Controls Non-secure access of the interrupt with ID406" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS405 ,Controls Non-secure access of the interrupt with ID405" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS404 ,Controls Non-secure access of the interrupt with ID404" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS403 ,Controls Non-secure access of the interrupt with ID403" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS402 ,Controls Non-secure access of the interrupt with ID402" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS401 ,Controls Non-secure access of the interrupt with ID401" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS400 ,Controls Non-secure access of the interrupt with ID400" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE64++0x03 hide.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE68))) group.long 0xE68++0x03 line.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26" bitfld.long 0x00 30.--31. " NS_ACCESS431 ,Controls Non-secure access of the interrupt with ID431" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS430 ,Controls Non-secure access of the interrupt with ID430" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS429 ,Controls Non-secure access of the interrupt with ID429" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS428 ,Controls Non-secure access of the interrupt with ID428" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS427 ,Controls Non-secure access of the interrupt with ID427" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS426 ,Controls Non-secure access of the interrupt with ID426" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS425 ,Controls Non-secure access of the interrupt with ID425" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS424 ,Controls Non-secure access of the interrupt with ID424" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS423 ,Controls Non-secure access of the interrupt with ID423" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS422 ,Controls Non-secure access of the interrupt with ID422" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS421 ,Controls Non-secure access of the interrupt with ID421" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS420 ,Controls Non-secure access of the interrupt with ID420" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS419 ,Controls Non-secure access of the interrupt with ID419" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS418 ,Controls Non-secure access of the interrupt with ID418" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS417 ,Controls Non-secure access of the interrupt with ID417" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS416 ,Controls Non-secure access of the interrupt with ID416" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE68++0x03 hide.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE6C))) group.long 0xE6C++0x03 line.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27" bitfld.long 0x00 30.--31. " NS_ACCESS447 ,Controls Non-secure access of the interrupt with ID447" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS446 ,Controls Non-secure access of the interrupt with ID446" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS445 ,Controls Non-secure access of the interrupt with ID445" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS444 ,Controls Non-secure access of the interrupt with ID444" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS443 ,Controls Non-secure access of the interrupt with ID443" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS442 ,Controls Non-secure access of the interrupt with ID442" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS441 ,Controls Non-secure access of the interrupt with ID441" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS440 ,Controls Non-secure access of the interrupt with ID440" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS439 ,Controls Non-secure access of the interrupt with ID439" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS438 ,Controls Non-secure access of the interrupt with ID438" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS437 ,Controls Non-secure access of the interrupt with ID437" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS436 ,Controls Non-secure access of the interrupt with ID436" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS435 ,Controls Non-secure access of the interrupt with ID435" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS434 ,Controls Non-secure access of the interrupt with ID434" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS433 ,Controls Non-secure access of the interrupt with ID433" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS432 ,Controls Non-secure access of the interrupt with ID432" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE6C++0x03 hide.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE70))) group.long 0xE70++0x03 line.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28" bitfld.long 0x00 30.--31. " NS_ACCESS463 ,Controls Non-secure access of the interrupt with ID463" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS462 ,Controls Non-secure access of the interrupt with ID462" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS461 ,Controls Non-secure access of the interrupt with ID461" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS460 ,Controls Non-secure access of the interrupt with ID460" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS459 ,Controls Non-secure access of the interrupt with ID459" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS458 ,Controls Non-secure access of the interrupt with ID458" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS457 ,Controls Non-secure access of the interrupt with ID457" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS456 ,Controls Non-secure access of the interrupt with ID456" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS455 ,Controls Non-secure access of the interrupt with ID455" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS454 ,Controls Non-secure access of the interrupt with ID454" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS453 ,Controls Non-secure access of the interrupt with ID453" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS452 ,Controls Non-secure access of the interrupt with ID452" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS451 ,Controls Non-secure access of the interrupt with ID451" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS450 ,Controls Non-secure access of the interrupt with ID450" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS449 ,Controls Non-secure access of the interrupt with ID449" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS448 ,Controls Non-secure access of the interrupt with ID448" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE70++0x03 hide.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE74))) group.long 0xE74++0x03 line.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29" bitfld.long 0x00 30.--31. " NS_ACCESS479 ,Controls Non-secure access of the interrupt with ID479" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS478 ,Controls Non-secure access of the interrupt with ID478" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS477 ,Controls Non-secure access of the interrupt with ID477" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS476 ,Controls Non-secure access of the interrupt with ID476" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS475 ,Controls Non-secure access of the interrupt with ID475" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS474 ,Controls Non-secure access of the interrupt with ID474" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS473 ,Controls Non-secure access of the interrupt with ID473" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS472 ,Controls Non-secure access of the interrupt with ID472" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS471 ,Controls Non-secure access of the interrupt with ID471" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS470 ,Controls Non-secure access of the interrupt with ID470" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS469 ,Controls Non-secure access of the interrupt with ID469" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS468 ,Controls Non-secure access of the interrupt with ID468" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS467 ,Controls Non-secure access of the interrupt with ID467" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS466 ,Controls Non-secure access of the interrupt with ID466" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS465 ,Controls Non-secure access of the interrupt with ID465" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS464 ,Controls Non-secure access of the interrupt with ID464" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE74++0x03 hide.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE78))) group.long 0xE78++0x03 line.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30" bitfld.long 0x00 30.--31. " NS_ACCESS495 ,Controls Non-secure access of the interrupt with ID495" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS494 ,Controls Non-secure access of the interrupt with ID494" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS493 ,Controls Non-secure access of the interrupt with ID493" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS492 ,Controls Non-secure access of the interrupt with ID492" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS491 ,Controls Non-secure access of the interrupt with ID491" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS490 ,Controls Non-secure access of the interrupt with ID490" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS489 ,Controls Non-secure access of the interrupt with ID489" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS488 ,Controls Non-secure access of the interrupt with ID488" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS487 ,Controls Non-secure access of the interrupt with ID487" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS486 ,Controls Non-secure access of the interrupt with ID486" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS485 ,Controls Non-secure access of the interrupt with ID485" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS484 ,Controls Non-secure access of the interrupt with ID484" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS483 ,Controls Non-secure access of the interrupt with ID483" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS482 ,Controls Non-secure access of the interrupt with ID482" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS481 ,Controls Non-secure access of the interrupt with ID481" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS480 ,Controls Non-secure access of the interrupt with ID480" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE78++0x03 hide.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE7C))) group.long 0xE7C++0x03 line.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31" bitfld.long 0x00 30.--31. " NS_ACCESS511 ,Controls Non-secure access of the interrupt with ID511" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS510 ,Controls Non-secure access of the interrupt with ID510" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS509 ,Controls Non-secure access of the interrupt with ID509" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS508 ,Controls Non-secure access of the interrupt with ID508" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS507 ,Controls Non-secure access of the interrupt with ID507" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS506 ,Controls Non-secure access of the interrupt with ID506" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS505 ,Controls Non-secure access of the interrupt with ID505" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS504 ,Controls Non-secure access of the interrupt with ID504" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS503 ,Controls Non-secure access of the interrupt with ID503" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS502 ,Controls Non-secure access of the interrupt with ID502" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS501 ,Controls Non-secure access of the interrupt with ID501" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS500 ,Controls Non-secure access of the interrupt with ID500" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS499 ,Controls Non-secure access of the interrupt with ID499" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS498 ,Controls Non-secure access of the interrupt with ID498" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS497 ,Controls Non-secure access of the interrupt with ID497" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS496 ,Controls Non-secure access of the interrupt with ID496" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE7C++0x03 hide.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE80))) group.long 0xE80++0x03 line.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32" bitfld.long 0x00 30.--31. " NS_ACCESS527 ,Controls Non-secure access of the interrupt with ID527" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS526 ,Controls Non-secure access of the interrupt with ID526" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS525 ,Controls Non-secure access of the interrupt with ID525" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS524 ,Controls Non-secure access of the interrupt with ID524" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS523 ,Controls Non-secure access of the interrupt with ID523" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS522 ,Controls Non-secure access of the interrupt with ID522" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS521 ,Controls Non-secure access of the interrupt with ID521" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS520 ,Controls Non-secure access of the interrupt with ID520" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS519 ,Controls Non-secure access of the interrupt with ID519" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS518 ,Controls Non-secure access of the interrupt with ID518" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS517 ,Controls Non-secure access of the interrupt with ID517" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS516 ,Controls Non-secure access of the interrupt with ID516" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS515 ,Controls Non-secure access of the interrupt with ID515" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS514 ,Controls Non-secure access of the interrupt with ID514" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS513 ,Controls Non-secure access of the interrupt with ID513" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS512 ,Controls Non-secure access of the interrupt with ID512" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE80++0x03 hide.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE84))) group.long 0xE84++0x03 line.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33" bitfld.long 0x00 30.--31. " NS_ACCESS543 ,Controls Non-secure access of the interrupt with ID543" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS542 ,Controls Non-secure access of the interrupt with ID542" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS541 ,Controls Non-secure access of the interrupt with ID541" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS540 ,Controls Non-secure access of the interrupt with ID540" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS539 ,Controls Non-secure access of the interrupt with ID539" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS538 ,Controls Non-secure access of the interrupt with ID538" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS537 ,Controls Non-secure access of the interrupt with ID537" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS536 ,Controls Non-secure access of the interrupt with ID536" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS535 ,Controls Non-secure access of the interrupt with ID535" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS534 ,Controls Non-secure access of the interrupt with ID534" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS533 ,Controls Non-secure access of the interrupt with ID533" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS532 ,Controls Non-secure access of the interrupt with ID532" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS531 ,Controls Non-secure access of the interrupt with ID531" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS530 ,Controls Non-secure access of the interrupt with ID530" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS529 ,Controls Non-secure access of the interrupt with ID529" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS528 ,Controls Non-secure access of the interrupt with ID528" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE84++0x03 hide.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE88))) group.long 0xE88++0x03 line.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34" bitfld.long 0x00 30.--31. " NS_ACCESS559 ,Controls Non-secure access of the interrupt with ID559" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS558 ,Controls Non-secure access of the interrupt with ID558" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS557 ,Controls Non-secure access of the interrupt with ID557" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS556 ,Controls Non-secure access of the interrupt with ID556" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS555 ,Controls Non-secure access of the interrupt with ID555" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS554 ,Controls Non-secure access of the interrupt with ID554" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS553 ,Controls Non-secure access of the interrupt with ID553" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS552 ,Controls Non-secure access of the interrupt with ID552" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS551 ,Controls Non-secure access of the interrupt with ID551" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS550 ,Controls Non-secure access of the interrupt with ID550" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS549 ,Controls Non-secure access of the interrupt with ID549" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS548 ,Controls Non-secure access of the interrupt with ID548" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS547 ,Controls Non-secure access of the interrupt with ID547" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS546 ,Controls Non-secure access of the interrupt with ID546" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS545 ,Controls Non-secure access of the interrupt with ID545" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS544 ,Controls Non-secure access of the interrupt with ID544" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE88++0x03 hide.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8C))) group.long 0xE8C++0x03 line.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35" bitfld.long 0x00 30.--31. " NS_ACCESS575 ,Controls Non-secure access of the interrupt with ID575" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS574 ,Controls Non-secure access of the interrupt with ID574" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS573 ,Controls Non-secure access of the interrupt with ID573" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS572 ,Controls Non-secure access of the interrupt with ID572" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS571 ,Controls Non-secure access of the interrupt with ID571" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS570 ,Controls Non-secure access of the interrupt with ID570" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS569 ,Controls Non-secure access of the interrupt with ID569" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS568 ,Controls Non-secure access of the interrupt with ID568" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS567 ,Controls Non-secure access of the interrupt with ID567" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS566 ,Controls Non-secure access of the interrupt with ID566" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS565 ,Controls Non-secure access of the interrupt with ID565" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS564 ,Controls Non-secure access of the interrupt with ID564" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS563 ,Controls Non-secure access of the interrupt with ID563" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS562 ,Controls Non-secure access of the interrupt with ID562" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS561 ,Controls Non-secure access of the interrupt with ID561" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS560 ,Controls Non-secure access of the interrupt with ID560" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE8C++0x03 hide.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE90))) group.long 0xE90++0x03 line.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36" bitfld.long 0x00 30.--31. " NS_ACCESS591 ,Controls Non-secure access of the interrupt with ID591" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS590 ,Controls Non-secure access of the interrupt with ID590" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS589 ,Controls Non-secure access of the interrupt with ID589" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS588 ,Controls Non-secure access of the interrupt with ID588" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS587 ,Controls Non-secure access of the interrupt with ID587" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS586 ,Controls Non-secure access of the interrupt with ID586" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS585 ,Controls Non-secure access of the interrupt with ID585" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS584 ,Controls Non-secure access of the interrupt with ID584" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS583 ,Controls Non-secure access of the interrupt with ID583" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS582 ,Controls Non-secure access of the interrupt with ID582" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS581 ,Controls Non-secure access of the interrupt with ID581" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS580 ,Controls Non-secure access of the interrupt with ID580" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS579 ,Controls Non-secure access of the interrupt with ID579" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS578 ,Controls Non-secure access of the interrupt with ID578" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS577 ,Controls Non-secure access of the interrupt with ID577" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS576 ,Controls Non-secure access of the interrupt with ID576" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE90++0x03 hide.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE94))) group.long 0xE94++0x03 line.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37" bitfld.long 0x00 30.--31. " NS_ACCESS607 ,Controls Non-secure access of the interrupt with ID607" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS606 ,Controls Non-secure access of the interrupt with ID606" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS605 ,Controls Non-secure access of the interrupt with ID605" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS604 ,Controls Non-secure access of the interrupt with ID604" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS603 ,Controls Non-secure access of the interrupt with ID603" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS602 ,Controls Non-secure access of the interrupt with ID602" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS601 ,Controls Non-secure access of the interrupt with ID601" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS600 ,Controls Non-secure access of the interrupt with ID600" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS599 ,Controls Non-secure access of the interrupt with ID599" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS598 ,Controls Non-secure access of the interrupt with ID598" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS597 ,Controls Non-secure access of the interrupt with ID597" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS596 ,Controls Non-secure access of the interrupt with ID596" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS595 ,Controls Non-secure access of the interrupt with ID595" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS594 ,Controls Non-secure access of the interrupt with ID594" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS593 ,Controls Non-secure access of the interrupt with ID593" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS592 ,Controls Non-secure access of the interrupt with ID592" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE94++0x03 hide.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE98))) group.long 0xE98++0x03 line.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38" bitfld.long 0x00 30.--31. " NS_ACCESS623 ,Controls Non-secure access of the interrupt with ID623" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS622 ,Controls Non-secure access of the interrupt with ID622" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS621 ,Controls Non-secure access of the interrupt with ID621" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS620 ,Controls Non-secure access of the interrupt with ID620" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS619 ,Controls Non-secure access of the interrupt with ID619" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS618 ,Controls Non-secure access of the interrupt with ID618" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS617 ,Controls Non-secure access of the interrupt with ID617" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS616 ,Controls Non-secure access of the interrupt with ID616" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS615 ,Controls Non-secure access of the interrupt with ID615" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS614 ,Controls Non-secure access of the interrupt with ID614" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS613 ,Controls Non-secure access of the interrupt with ID613" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS612 ,Controls Non-secure access of the interrupt with ID612" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS611 ,Controls Non-secure access of the interrupt with ID611" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS610 ,Controls Non-secure access of the interrupt with ID610" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS609 ,Controls Non-secure access of the interrupt with ID609" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS608 ,Controls Non-secure access of the interrupt with ID608" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE98++0x03 hide.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE9C))) group.long 0xE9C++0x03 line.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39" bitfld.long 0x00 30.--31. " NS_ACCESS639 ,Controls Non-secure access of the interrupt with ID639" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS638 ,Controls Non-secure access of the interrupt with ID638" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS637 ,Controls Non-secure access of the interrupt with ID637" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS636 ,Controls Non-secure access of the interrupt with ID636" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS635 ,Controls Non-secure access of the interrupt with ID635" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS634 ,Controls Non-secure access of the interrupt with ID634" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS633 ,Controls Non-secure access of the interrupt with ID633" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS632 ,Controls Non-secure access of the interrupt with ID632" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS631 ,Controls Non-secure access of the interrupt with ID631" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS630 ,Controls Non-secure access of the interrupt with ID630" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS629 ,Controls Non-secure access of the interrupt with ID629" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS628 ,Controls Non-secure access of the interrupt with ID628" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS627 ,Controls Non-secure access of the interrupt with ID627" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS626 ,Controls Non-secure access of the interrupt with ID626" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS625 ,Controls Non-secure access of the interrupt with ID625" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS624 ,Controls Non-secure access of the interrupt with ID624" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE9C++0x03 hide.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA0))) group.long 0xEA0++0x03 line.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40" bitfld.long 0x00 30.--31. " NS_ACCESS655 ,Controls Non-secure access of the interrupt with ID655" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS654 ,Controls Non-secure access of the interrupt with ID654" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS653 ,Controls Non-secure access of the interrupt with ID653" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS652 ,Controls Non-secure access of the interrupt with ID652" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS651 ,Controls Non-secure access of the interrupt with ID651" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS650 ,Controls Non-secure access of the interrupt with ID650" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS649 ,Controls Non-secure access of the interrupt with ID649" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS648 ,Controls Non-secure access of the interrupt with ID648" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS647 ,Controls Non-secure access of the interrupt with ID647" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS646 ,Controls Non-secure access of the interrupt with ID646" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS645 ,Controls Non-secure access of the interrupt with ID645" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS644 ,Controls Non-secure access of the interrupt with ID644" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS643 ,Controls Non-secure access of the interrupt with ID643" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS642 ,Controls Non-secure access of the interrupt with ID642" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS641 ,Controls Non-secure access of the interrupt with ID641" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS640 ,Controls Non-secure access of the interrupt with ID640" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEA0++0x03 hide.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA4))) group.long 0xEA4++0x03 line.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41" bitfld.long 0x00 30.--31. " NS_ACCESS671 ,Controls Non-secure access of the interrupt with ID671" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS670 ,Controls Non-secure access of the interrupt with ID670" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS669 ,Controls Non-secure access of the interrupt with ID669" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS668 ,Controls Non-secure access of the interrupt with ID668" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS667 ,Controls Non-secure access of the interrupt with ID667" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS666 ,Controls Non-secure access of the interrupt with ID666" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS665 ,Controls Non-secure access of the interrupt with ID665" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS664 ,Controls Non-secure access of the interrupt with ID664" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS663 ,Controls Non-secure access of the interrupt with ID663" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS662 ,Controls Non-secure access of the interrupt with ID662" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS661 ,Controls Non-secure access of the interrupt with ID661" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS660 ,Controls Non-secure access of the interrupt with ID660" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS659 ,Controls Non-secure access of the interrupt with ID659" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS658 ,Controls Non-secure access of the interrupt with ID658" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS657 ,Controls Non-secure access of the interrupt with ID657" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS656 ,Controls Non-secure access of the interrupt with ID656" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEA4++0x03 hide.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA8))) group.long 0xEA8++0x03 line.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42" bitfld.long 0x00 30.--31. " NS_ACCESS687 ,Controls Non-secure access of the interrupt with ID687" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS686 ,Controls Non-secure access of the interrupt with ID686" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS685 ,Controls Non-secure access of the interrupt with ID685" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS684 ,Controls Non-secure access of the interrupt with ID684" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS683 ,Controls Non-secure access of the interrupt with ID683" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS682 ,Controls Non-secure access of the interrupt with ID682" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS681 ,Controls Non-secure access of the interrupt with ID681" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS680 ,Controls Non-secure access of the interrupt with ID680" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS679 ,Controls Non-secure access of the interrupt with ID679" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS678 ,Controls Non-secure access of the interrupt with ID678" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS677 ,Controls Non-secure access of the interrupt with ID677" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS676 ,Controls Non-secure access of the interrupt with ID676" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS675 ,Controls Non-secure access of the interrupt with ID675" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS674 ,Controls Non-secure access of the interrupt with ID674" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS673 ,Controls Non-secure access of the interrupt with ID673" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS672 ,Controls Non-secure access of the interrupt with ID672" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEA8++0x03 hide.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEAC))) group.long 0xEAC++0x03 line.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43" bitfld.long 0x00 30.--31. " NS_ACCESS703 ,Controls Non-secure access of the interrupt with ID703" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS702 ,Controls Non-secure access of the interrupt with ID702" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS701 ,Controls Non-secure access of the interrupt with ID701" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS700 ,Controls Non-secure access of the interrupt with ID700" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS699 ,Controls Non-secure access of the interrupt with ID699" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS698 ,Controls Non-secure access of the interrupt with ID698" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS697 ,Controls Non-secure access of the interrupt with ID697" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS696 ,Controls Non-secure access of the interrupt with ID696" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS695 ,Controls Non-secure access of the interrupt with ID695" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS694 ,Controls Non-secure access of the interrupt with ID694" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS693 ,Controls Non-secure access of the interrupt with ID693" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS692 ,Controls Non-secure access of the interrupt with ID692" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS691 ,Controls Non-secure access of the interrupt with ID691" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS690 ,Controls Non-secure access of the interrupt with ID690" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS689 ,Controls Non-secure access of the interrupt with ID689" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS688 ,Controls Non-secure access of the interrupt with ID688" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEAC++0x03 hide.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB0))) group.long 0xEB0++0x03 line.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44" bitfld.long 0x00 30.--31. " NS_ACCESS719 ,Controls Non-secure access of the interrupt with ID719" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS718 ,Controls Non-secure access of the interrupt with ID718" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS717 ,Controls Non-secure access of the interrupt with ID717" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS716 ,Controls Non-secure access of the interrupt with ID716" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS715 ,Controls Non-secure access of the interrupt with ID715" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS714 ,Controls Non-secure access of the interrupt with ID714" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS713 ,Controls Non-secure access of the interrupt with ID713" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS712 ,Controls Non-secure access of the interrupt with ID712" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS711 ,Controls Non-secure access of the interrupt with ID711" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS710 ,Controls Non-secure access of the interrupt with ID710" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS709 ,Controls Non-secure access of the interrupt with ID709" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS708 ,Controls Non-secure access of the interrupt with ID708" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS707 ,Controls Non-secure access of the interrupt with ID707" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS706 ,Controls Non-secure access of the interrupt with ID706" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS705 ,Controls Non-secure access of the interrupt with ID705" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS704 ,Controls Non-secure access of the interrupt with ID704" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEB0++0x03 hide.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB4))) group.long 0xEB4++0x03 line.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45" bitfld.long 0x00 30.--31. " NS_ACCESS735 ,Controls Non-secure access of the interrupt with ID735" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS734 ,Controls Non-secure access of the interrupt with ID734" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS733 ,Controls Non-secure access of the interrupt with ID733" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS732 ,Controls Non-secure access of the interrupt with ID732" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS731 ,Controls Non-secure access of the interrupt with ID731" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS730 ,Controls Non-secure access of the interrupt with ID730" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS729 ,Controls Non-secure access of the interrupt with ID729" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS728 ,Controls Non-secure access of the interrupt with ID728" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS727 ,Controls Non-secure access of the interrupt with ID727" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS726 ,Controls Non-secure access of the interrupt with ID726" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS725 ,Controls Non-secure access of the interrupt with ID725" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS724 ,Controls Non-secure access of the interrupt with ID724" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS723 ,Controls Non-secure access of the interrupt with ID723" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS722 ,Controls Non-secure access of the interrupt with ID722" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS721 ,Controls Non-secure access of the interrupt with ID721" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS720 ,Controls Non-secure access of the interrupt with ID720" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEB4++0x03 hide.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB8))) group.long 0xEB8++0x03 line.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46" bitfld.long 0x00 30.--31. " NS_ACCESS751 ,Controls Non-secure access of the interrupt with ID751" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS750 ,Controls Non-secure access of the interrupt with ID750" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS749 ,Controls Non-secure access of the interrupt with ID749" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS748 ,Controls Non-secure access of the interrupt with ID748" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS747 ,Controls Non-secure access of the interrupt with ID747" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS746 ,Controls Non-secure access of the interrupt with ID746" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS745 ,Controls Non-secure access of the interrupt with ID745" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS744 ,Controls Non-secure access of the interrupt with ID744" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS743 ,Controls Non-secure access of the interrupt with ID743" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS742 ,Controls Non-secure access of the interrupt with ID742" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS741 ,Controls Non-secure access of the interrupt with ID741" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS740 ,Controls Non-secure access of the interrupt with ID740" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS739 ,Controls Non-secure access of the interrupt with ID739" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS738 ,Controls Non-secure access of the interrupt with ID738" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS737 ,Controls Non-secure access of the interrupt with ID737" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS736 ,Controls Non-secure access of the interrupt with ID736" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEB8++0x03 hide.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEBC))) group.long 0xEBC++0x03 line.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47" bitfld.long 0x00 30.--31. " NS_ACCESS767 ,Controls Non-secure access of the interrupt with ID767" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS766 ,Controls Non-secure access of the interrupt with ID766" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS765 ,Controls Non-secure access of the interrupt with ID765" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS764 ,Controls Non-secure access of the interrupt with ID764" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS763 ,Controls Non-secure access of the interrupt with ID763" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS762 ,Controls Non-secure access of the interrupt with ID762" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS761 ,Controls Non-secure access of the interrupt with ID761" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS760 ,Controls Non-secure access of the interrupt with ID760" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS759 ,Controls Non-secure access of the interrupt with ID759" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS758 ,Controls Non-secure access of the interrupt with ID758" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS757 ,Controls Non-secure access of the interrupt with ID757" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS756 ,Controls Non-secure access of the interrupt with ID756" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS755 ,Controls Non-secure access of the interrupt with ID755" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS754 ,Controls Non-secure access of the interrupt with ID754" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS753 ,Controls Non-secure access of the interrupt with ID753" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS752 ,Controls Non-secure access of the interrupt with ID752" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEBC++0x03 hide.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC0))) group.long 0xEC0++0x03 line.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48" bitfld.long 0x00 30.--31. " NS_ACCESS783 ,Controls Non-secure access of the interrupt with ID783" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS782 ,Controls Non-secure access of the interrupt with ID782" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS781 ,Controls Non-secure access of the interrupt with ID781" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS780 ,Controls Non-secure access of the interrupt with ID780" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS779 ,Controls Non-secure access of the interrupt with ID779" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS778 ,Controls Non-secure access of the interrupt with ID778" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS777 ,Controls Non-secure access of the interrupt with ID777" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS776 ,Controls Non-secure access of the interrupt with ID776" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS775 ,Controls Non-secure access of the interrupt with ID775" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS774 ,Controls Non-secure access of the interrupt with ID774" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS773 ,Controls Non-secure access of the interrupt with ID773" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS772 ,Controls Non-secure access of the interrupt with ID772" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS771 ,Controls Non-secure access of the interrupt with ID771" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS770 ,Controls Non-secure access of the interrupt with ID770" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS769 ,Controls Non-secure access of the interrupt with ID769" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS768 ,Controls Non-secure access of the interrupt with ID768" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEC0++0x03 hide.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC4))) group.long 0xEC4++0x03 line.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49" bitfld.long 0x00 30.--31. " NS_ACCESS799 ,Controls Non-secure access of the interrupt with ID799" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS798 ,Controls Non-secure access of the interrupt with ID798" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS797 ,Controls Non-secure access of the interrupt with ID797" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS796 ,Controls Non-secure access of the interrupt with ID796" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS795 ,Controls Non-secure access of the interrupt with ID795" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS794 ,Controls Non-secure access of the interrupt with ID794" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS793 ,Controls Non-secure access of the interrupt with ID793" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS792 ,Controls Non-secure access of the interrupt with ID792" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS791 ,Controls Non-secure access of the interrupt with ID791" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS790 ,Controls Non-secure access of the interrupt with ID790" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS789 ,Controls Non-secure access of the interrupt with ID789" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS788 ,Controls Non-secure access of the interrupt with ID788" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS787 ,Controls Non-secure access of the interrupt with ID787" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS786 ,Controls Non-secure access of the interrupt with ID786" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS785 ,Controls Non-secure access of the interrupt with ID785" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS784 ,Controls Non-secure access of the interrupt with ID784" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEC4++0x03 hide.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC8))) group.long 0xEC8++0x03 line.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50" bitfld.long 0x00 30.--31. " NS_ACCESS815 ,Controls Non-secure access of the interrupt with ID815" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS814 ,Controls Non-secure access of the interrupt with ID814" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS813 ,Controls Non-secure access of the interrupt with ID813" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS812 ,Controls Non-secure access of the interrupt with ID812" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS811 ,Controls Non-secure access of the interrupt with ID811" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS810 ,Controls Non-secure access of the interrupt with ID810" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS809 ,Controls Non-secure access of the interrupt with ID809" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS808 ,Controls Non-secure access of the interrupt with ID808" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS807 ,Controls Non-secure access of the interrupt with ID807" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS806 ,Controls Non-secure access of the interrupt with ID806" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS805 ,Controls Non-secure access of the interrupt with ID805" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS804 ,Controls Non-secure access of the interrupt with ID804" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS803 ,Controls Non-secure access of the interrupt with ID803" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS802 ,Controls Non-secure access of the interrupt with ID802" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS801 ,Controls Non-secure access of the interrupt with ID801" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS800 ,Controls Non-secure access of the interrupt with ID800" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEC8++0x03 hide.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xECC))) group.long 0xECC++0x03 line.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51" bitfld.long 0x00 30.--31. " NS_ACCESS831 ,Controls Non-secure access of the interrupt with ID831" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS830 ,Controls Non-secure access of the interrupt with ID830" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS829 ,Controls Non-secure access of the interrupt with ID829" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS828 ,Controls Non-secure access of the interrupt with ID828" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS827 ,Controls Non-secure access of the interrupt with ID827" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS826 ,Controls Non-secure access of the interrupt with ID826" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS825 ,Controls Non-secure access of the interrupt with ID825" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS824 ,Controls Non-secure access of the interrupt with ID824" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS823 ,Controls Non-secure access of the interrupt with ID823" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS822 ,Controls Non-secure access of the interrupt with ID822" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS821 ,Controls Non-secure access of the interrupt with ID821" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS820 ,Controls Non-secure access of the interrupt with ID820" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS819 ,Controls Non-secure access of the interrupt with ID819" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS818 ,Controls Non-secure access of the interrupt with ID818" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS817 ,Controls Non-secure access of the interrupt with ID817" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS816 ,Controls Non-secure access of the interrupt with ID816" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xECC++0x03 hide.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED0))) group.long 0xED0++0x03 line.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52" bitfld.long 0x00 30.--31. " NS_ACCESS847 ,Controls Non-secure access of the interrupt with ID847" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS846 ,Controls Non-secure access of the interrupt with ID846" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS845 ,Controls Non-secure access of the interrupt with ID845" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS844 ,Controls Non-secure access of the interrupt with ID844" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS843 ,Controls Non-secure access of the interrupt with ID843" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS842 ,Controls Non-secure access of the interrupt with ID842" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS841 ,Controls Non-secure access of the interrupt with ID841" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS840 ,Controls Non-secure access of the interrupt with ID840" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS839 ,Controls Non-secure access of the interrupt with ID839" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS838 ,Controls Non-secure access of the interrupt with ID838" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS837 ,Controls Non-secure access of the interrupt with ID837" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS836 ,Controls Non-secure access of the interrupt with ID836" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS835 ,Controls Non-secure access of the interrupt with ID835" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS834 ,Controls Non-secure access of the interrupt with ID834" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS833 ,Controls Non-secure access of the interrupt with ID833" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS832 ,Controls Non-secure access of the interrupt with ID832" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xED0++0x03 hide.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED4))) group.long 0xED4++0x03 line.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53" bitfld.long 0x00 30.--31. " NS_ACCESS863 ,Controls Non-secure access of the interrupt with ID863" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS862 ,Controls Non-secure access of the interrupt with ID862" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS861 ,Controls Non-secure access of the interrupt with ID861" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS860 ,Controls Non-secure access of the interrupt with ID860" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS859 ,Controls Non-secure access of the interrupt with ID859" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS858 ,Controls Non-secure access of the interrupt with ID858" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS857 ,Controls Non-secure access of the interrupt with ID857" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS856 ,Controls Non-secure access of the interrupt with ID856" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS855 ,Controls Non-secure access of the interrupt with ID855" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS854 ,Controls Non-secure access of the interrupt with ID854" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS853 ,Controls Non-secure access of the interrupt with ID853" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS852 ,Controls Non-secure access of the interrupt with ID852" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS851 ,Controls Non-secure access of the interrupt with ID851" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS850 ,Controls Non-secure access of the interrupt with ID850" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS849 ,Controls Non-secure access of the interrupt with ID849" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS848 ,Controls Non-secure access of the interrupt with ID848" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xED4++0x03 hide.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED8))) group.long 0xED8++0x03 line.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54" bitfld.long 0x00 30.--31. " NS_ACCESS879 ,Controls Non-secure access of the interrupt with ID879" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS878 ,Controls Non-secure access of the interrupt with ID878" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS877 ,Controls Non-secure access of the interrupt with ID877" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS876 ,Controls Non-secure access of the interrupt with ID876" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS875 ,Controls Non-secure access of the interrupt with ID875" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS874 ,Controls Non-secure access of the interrupt with ID874" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS873 ,Controls Non-secure access of the interrupt with ID873" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS872 ,Controls Non-secure access of the interrupt with ID872" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS871 ,Controls Non-secure access of the interrupt with ID871" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS870 ,Controls Non-secure access of the interrupt with ID870" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS869 ,Controls Non-secure access of the interrupt with ID869" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS868 ,Controls Non-secure access of the interrupt with ID868" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS867 ,Controls Non-secure access of the interrupt with ID867" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS866 ,Controls Non-secure access of the interrupt with ID866" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS865 ,Controls Non-secure access of the interrupt with ID865" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS864 ,Controls Non-secure access of the interrupt with ID864" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xED8++0x03 hide.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEDC))) group.long 0xEDC++0x03 line.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55" bitfld.long 0x00 30.--31. " NS_ACCESS895 ,Controls Non-secure access of the interrupt with ID895" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS894 ,Controls Non-secure access of the interrupt with ID894" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS893 ,Controls Non-secure access of the interrupt with ID893" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS892 ,Controls Non-secure access of the interrupt with ID892" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS891 ,Controls Non-secure access of the interrupt with ID891" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS890 ,Controls Non-secure access of the interrupt with ID890" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS889 ,Controls Non-secure access of the interrupt with ID889" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS888 ,Controls Non-secure access of the interrupt with ID888" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS887 ,Controls Non-secure access of the interrupt with ID887" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS886 ,Controls Non-secure access of the interrupt with ID886" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS885 ,Controls Non-secure access of the interrupt with ID885" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS884 ,Controls Non-secure access of the interrupt with ID884" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS883 ,Controls Non-secure access of the interrupt with ID883" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS882 ,Controls Non-secure access of the interrupt with ID882" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS881 ,Controls Non-secure access of the interrupt with ID881" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS880 ,Controls Non-secure access of the interrupt with ID880" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEDC++0x03 hide.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE0))) group.long 0xEE0++0x03 line.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56" bitfld.long 0x00 30.--31. " NS_ACCESS911 ,Controls Non-secure access of the interrupt with ID911" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS910 ,Controls Non-secure access of the interrupt with ID910" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS909 ,Controls Non-secure access of the interrupt with ID909" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS908 ,Controls Non-secure access of the interrupt with ID908" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS907 ,Controls Non-secure access of the interrupt with ID907" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS906 ,Controls Non-secure access of the interrupt with ID906" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS905 ,Controls Non-secure access of the interrupt with ID905" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS904 ,Controls Non-secure access of the interrupt with ID904" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS903 ,Controls Non-secure access of the interrupt with ID903" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS902 ,Controls Non-secure access of the interrupt with ID902" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS901 ,Controls Non-secure access of the interrupt with ID901" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS900 ,Controls Non-secure access of the interrupt with ID900" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS899 ,Controls Non-secure access of the interrupt with ID899" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS898 ,Controls Non-secure access of the interrupt with ID898" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS897 ,Controls Non-secure access of the interrupt with ID897" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS896 ,Controls Non-secure access of the interrupt with ID896" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEE0++0x03 hide.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE4))) group.long 0xEE4++0x03 line.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57" bitfld.long 0x00 30.--31. " NS_ACCESS927 ,Controls Non-secure access of the interrupt with ID927" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS926 ,Controls Non-secure access of the interrupt with ID926" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS925 ,Controls Non-secure access of the interrupt with ID925" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS924 ,Controls Non-secure access of the interrupt with ID924" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS923 ,Controls Non-secure access of the interrupt with ID923" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS922 ,Controls Non-secure access of the interrupt with ID922" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS921 ,Controls Non-secure access of the interrupt with ID921" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS920 ,Controls Non-secure access of the interrupt with ID920" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS919 ,Controls Non-secure access of the interrupt with ID919" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS918 ,Controls Non-secure access of the interrupt with ID918" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS917 ,Controls Non-secure access of the interrupt with ID917" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS916 ,Controls Non-secure access of the interrupt with ID916" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS915 ,Controls Non-secure access of the interrupt with ID915" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS914 ,Controls Non-secure access of the interrupt with ID914" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS913 ,Controls Non-secure access of the interrupt with ID913" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS912 ,Controls Non-secure access of the interrupt with ID912" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEE4++0x03 hide.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE8))) group.long 0xEE8++0x03 line.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58" bitfld.long 0x00 30.--31. " NS_ACCESS943 ,Controls Non-secure access of the interrupt with ID943" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS942 ,Controls Non-secure access of the interrupt with ID942" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS941 ,Controls Non-secure access of the interrupt with ID941" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS940 ,Controls Non-secure access of the interrupt with ID940" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS939 ,Controls Non-secure access of the interrupt with ID939" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS938 ,Controls Non-secure access of the interrupt with ID938" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS937 ,Controls Non-secure access of the interrupt with ID937" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS936 ,Controls Non-secure access of the interrupt with ID936" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS935 ,Controls Non-secure access of the interrupt with ID935" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS934 ,Controls Non-secure access of the interrupt with ID934" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS933 ,Controls Non-secure access of the interrupt with ID933" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS932 ,Controls Non-secure access of the interrupt with ID932" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS931 ,Controls Non-secure access of the interrupt with ID931" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS930 ,Controls Non-secure access of the interrupt with ID930" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS929 ,Controls Non-secure access of the interrupt with ID929" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS928 ,Controls Non-secure access of the interrupt with ID928" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEE8++0x03 hide.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEEC))) group.long 0xEEC++0x03 line.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59" bitfld.long 0x00 30.--31. " NS_ACCESS959 ,Controls Non-secure access of the interrupt with ID959" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS958 ,Controls Non-secure access of the interrupt with ID958" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS957 ,Controls Non-secure access of the interrupt with ID957" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS956 ,Controls Non-secure access of the interrupt with ID956" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS955 ,Controls Non-secure access of the interrupt with ID955" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS954 ,Controls Non-secure access of the interrupt with ID954" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS953 ,Controls Non-secure access of the interrupt with ID953" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS952 ,Controls Non-secure access of the interrupt with ID952" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS951 ,Controls Non-secure access of the interrupt with ID951" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS950 ,Controls Non-secure access of the interrupt with ID950" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS949 ,Controls Non-secure access of the interrupt with ID949" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS948 ,Controls Non-secure access of the interrupt with ID948" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS947 ,Controls Non-secure access of the interrupt with ID947" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS946 ,Controls Non-secure access of the interrupt with ID946" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS945 ,Controls Non-secure access of the interrupt with ID945" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS944 ,Controls Non-secure access of the interrupt with ID944" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEEC++0x03 hide.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF0))) group.long 0xEF0++0x03 line.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60" bitfld.long 0x00 30.--31. " NS_ACCESS975 ,Controls Non-secure access of the interrupt with ID975" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS974 ,Controls Non-secure access of the interrupt with ID974" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS973 ,Controls Non-secure access of the interrupt with ID973" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS972 ,Controls Non-secure access of the interrupt with ID972" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS971 ,Controls Non-secure access of the interrupt with ID971" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS970 ,Controls Non-secure access of the interrupt with ID970" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS969 ,Controls Non-secure access of the interrupt with ID969" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS968 ,Controls Non-secure access of the interrupt with ID968" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS967 ,Controls Non-secure access of the interrupt with ID967" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS966 ,Controls Non-secure access of the interrupt with ID966" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS965 ,Controls Non-secure access of the interrupt with ID965" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS964 ,Controls Non-secure access of the interrupt with ID964" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS963 ,Controls Non-secure access of the interrupt with ID963" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS962 ,Controls Non-secure access of the interrupt with ID962" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS961 ,Controls Non-secure access of the interrupt with ID961" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS960 ,Controls Non-secure access of the interrupt with ID960" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEF0++0x03 hide.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF4))) group.long 0xEF4++0x03 line.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61" bitfld.long 0x00 30.--31. " NS_ACCESS991 ,Controls Non-secure access of the interrupt with ID991" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS990 ,Controls Non-secure access of the interrupt with ID990" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS989 ,Controls Non-secure access of the interrupt with ID989" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS988 ,Controls Non-secure access of the interrupt with ID988" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS987 ,Controls Non-secure access of the interrupt with ID987" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS986 ,Controls Non-secure access of the interrupt with ID986" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS985 ,Controls Non-secure access of the interrupt with ID985" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS984 ,Controls Non-secure access of the interrupt with ID984" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS983 ,Controls Non-secure access of the interrupt with ID983" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS982 ,Controls Non-secure access of the interrupt with ID982" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS981 ,Controls Non-secure access of the interrupt with ID981" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS980 ,Controls Non-secure access of the interrupt with ID980" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS979 ,Controls Non-secure access of the interrupt with ID979" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS978 ,Controls Non-secure access of the interrupt with ID978" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS977 ,Controls Non-secure access of the interrupt with ID977" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS976 ,Controls Non-secure access of the interrupt with ID976" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEF4++0x03 hide.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61" endif tree.end width 25. tree "Software Generated Interrupt" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0F00++0x03 hide.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" hgroup.long 0xF10++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0" hgroup.long 0xF14++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1" hgroup.long 0xF18++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2" hgroup.long 0xF1C++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3" hgroup.long 0xF20++0x03 hide.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0" hgroup.long 0xF24++0x03 hide.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1" hgroup.long 0xF28++0x03 hide.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2" hgroup.long 0xF2C++0x03 hide.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3" else wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" group.long 0xF10++0x03 line.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0" group.long 0xF14++0x03 line.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1" group.long 0xF18++0x03 line.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2" group.long 0xF1C++0x03 line.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3" group.long 0xF20++0x03 line.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0" group.long 0xF24++0x03 line.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1" group.long 0xF28++0x03 line.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2" group.long 0xF2C++0x03 line.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3" endif tree.end width 24. tree "Interrupt Routing Registers" group.quad 0x6100++0x07 line.quad 0x00 "GICD_IROUTER32 ,Interrupt Routing Register 32 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6108++0x07 line.quad 0x00 "GICD_IROUTER33 ,Interrupt Routing Register 33 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6110++0x07 line.quad 0x00 "GICD_IROUTER34 ,Interrupt Routing Register 34 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6118++0x07 line.quad 0x00 "GICD_IROUTER35 ,Interrupt Routing Register 35 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6120++0x07 line.quad 0x00 "GICD_IROUTER36 ,Interrupt Routing Register 36 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6128++0x07 line.quad 0x00 "GICD_IROUTER37 ,Interrupt Routing Register 37 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6130++0x07 line.quad 0x00 "GICD_IROUTER38 ,Interrupt Routing Register 38 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6138++0x07 line.quad 0x00 "GICD_IROUTER39 ,Interrupt Routing Register 39 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6140++0x07 line.quad 0x00 "GICD_IROUTER40 ,Interrupt Routing Register 40 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6148++0x07 line.quad 0x00 "GICD_IROUTER41 ,Interrupt Routing Register 41 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6150++0x07 line.quad 0x00 "GICD_IROUTER42 ,Interrupt Routing Register 42 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6158++0x07 line.quad 0x00 "GICD_IROUTER43 ,Interrupt Routing Register 43 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6160++0x07 line.quad 0x00 "GICD_IROUTER44 ,Interrupt Routing Register 44 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6168++0x07 line.quad 0x00 "GICD_IROUTER45 ,Interrupt Routing Register 45 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6170++0x07 line.quad 0x00 "GICD_IROUTER46 ,Interrupt Routing Register 46 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6178++0x07 line.quad 0x00 "GICD_IROUTER47 ,Interrupt Routing Register 47 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6180++0x07 line.quad 0x00 "GICD_IROUTER48 ,Interrupt Routing Register 48 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6188++0x07 line.quad 0x00 "GICD_IROUTER49 ,Interrupt Routing Register 49 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6190++0x07 line.quad 0x00 "GICD_IROUTER50 ,Interrupt Routing Register 50 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6198++0x07 line.quad 0x00 "GICD_IROUTER51 ,Interrupt Routing Register 51 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61A0++0x07 line.quad 0x00 "GICD_IROUTER52 ,Interrupt Routing Register 52 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61A8++0x07 line.quad 0x00 "GICD_IROUTER53 ,Interrupt Routing Register 53 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61B0++0x07 line.quad 0x00 "GICD_IROUTER54 ,Interrupt Routing Register 54 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61B8++0x07 line.quad 0x00 "GICD_IROUTER55 ,Interrupt Routing Register 55 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61C0++0x07 line.quad 0x00 "GICD_IROUTER56 ,Interrupt Routing Register 56 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61C8++0x07 line.quad 0x00 "GICD_IROUTER57 ,Interrupt Routing Register 57 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61D0++0x07 line.quad 0x00 "GICD_IROUTER58 ,Interrupt Routing Register 58 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61D8++0x07 line.quad 0x00 "GICD_IROUTER59 ,Interrupt Routing Register 59 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61E0++0x07 line.quad 0x00 "GICD_IROUTER60 ,Interrupt Routing Register 60 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61E8++0x07 line.quad 0x00 "GICD_IROUTER61 ,Interrupt Routing Register 61 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61F0++0x07 line.quad 0x00 "GICD_IROUTER62 ,Interrupt Routing Register 62 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61F8++0x07 line.quad 0x00 "GICD_IROUTER63 ,Interrupt Routing Register 63 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6200++0x07 line.quad 0x00 "GICD_IROUTER64 ,Interrupt Routing Register 64 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6208++0x07 line.quad 0x00 "GICD_IROUTER65 ,Interrupt Routing Register 65 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6210++0x07 line.quad 0x00 "GICD_IROUTER66 ,Interrupt Routing Register 66 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6218++0x07 line.quad 0x00 "GICD_IROUTER67 ,Interrupt Routing Register 67 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6220++0x07 line.quad 0x00 "GICD_IROUTER68 ,Interrupt Routing Register 68 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6228++0x07 line.quad 0x00 "GICD_IROUTER69 ,Interrupt Routing Register 69 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6230++0x07 line.quad 0x00 "GICD_IROUTER70 ,Interrupt Routing Register 70 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6238++0x07 line.quad 0x00 "GICD_IROUTER71 ,Interrupt Routing Register 71 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6240++0x07 line.quad 0x00 "GICD_IROUTER72 ,Interrupt Routing Register 72 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6248++0x07 line.quad 0x00 "GICD_IROUTER73 ,Interrupt Routing Register 73 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6250++0x07 line.quad 0x00 "GICD_IROUTER74 ,Interrupt Routing Register 74 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6258++0x07 line.quad 0x00 "GICD_IROUTER75 ,Interrupt Routing Register 75 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6260++0x07 line.quad 0x00 "GICD_IROUTER76 ,Interrupt Routing Register 76 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6268++0x07 line.quad 0x00 "GICD_IROUTER77 ,Interrupt Routing Register 77 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6270++0x07 line.quad 0x00 "GICD_IROUTER78 ,Interrupt Routing Register 78 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6278++0x07 line.quad 0x00 "GICD_IROUTER79 ,Interrupt Routing Register 79 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6280++0x07 line.quad 0x00 "GICD_IROUTER80 ,Interrupt Routing Register 80 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6288++0x07 line.quad 0x00 "GICD_IROUTER81 ,Interrupt Routing Register 81 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6290++0x07 line.quad 0x00 "GICD_IROUTER82 ,Interrupt Routing Register 82 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6298++0x07 line.quad 0x00 "GICD_IROUTER83 ,Interrupt Routing Register 83 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62A0++0x07 line.quad 0x00 "GICD_IROUTER84 ,Interrupt Routing Register 84 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62A8++0x07 line.quad 0x00 "GICD_IROUTER85 ,Interrupt Routing Register 85 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62B0++0x07 line.quad 0x00 "GICD_IROUTER86 ,Interrupt Routing Register 86 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62B8++0x07 line.quad 0x00 "GICD_IROUTER87 ,Interrupt Routing Register 87 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62C0++0x07 line.quad 0x00 "GICD_IROUTER88 ,Interrupt Routing Register 88 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62C8++0x07 line.quad 0x00 "GICD_IROUTER89 ,Interrupt Routing Register 89 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62D0++0x07 line.quad 0x00 "GICD_IROUTER90 ,Interrupt Routing Register 90 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62D8++0x07 line.quad 0x00 "GICD_IROUTER91 ,Interrupt Routing Register 91 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62E0++0x07 line.quad 0x00 "GICD_IROUTER92 ,Interrupt Routing Register 92 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62E8++0x07 line.quad 0x00 "GICD_IROUTER93 ,Interrupt Routing Register 93 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62F0++0x07 line.quad 0x00 "GICD_IROUTER94 ,Interrupt Routing Register 94 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62F8++0x07 line.quad 0x00 "GICD_IROUTER95 ,Interrupt Routing Register 95 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6300++0x07 line.quad 0x00 "GICD_IROUTER96 ,Interrupt Routing Register 96 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6308++0x07 line.quad 0x00 "GICD_IROUTER97 ,Interrupt Routing Register 97 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6310++0x07 line.quad 0x00 "GICD_IROUTER98 ,Interrupt Routing Register 98 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6318++0x07 line.quad 0x00 "GICD_IROUTER99 ,Interrupt Routing Register 99 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6320++0x07 line.quad 0x00 "GICD_IROUTER100,Interrupt Routing Register 100" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6328++0x07 line.quad 0x00 "GICD_IROUTER101,Interrupt Routing Register 101" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6330++0x07 line.quad 0x00 "GICD_IROUTER102,Interrupt Routing Register 102" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6338++0x07 line.quad 0x00 "GICD_IROUTER103,Interrupt Routing Register 103" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6340++0x07 line.quad 0x00 "GICD_IROUTER104,Interrupt Routing Register 104" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6348++0x07 line.quad 0x00 "GICD_IROUTER105,Interrupt Routing Register 105" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6350++0x07 line.quad 0x00 "GICD_IROUTER106,Interrupt Routing Register 106" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6358++0x07 line.quad 0x00 "GICD_IROUTER107,Interrupt Routing Register 107" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6360++0x07 line.quad 0x00 "GICD_IROUTER108,Interrupt Routing Register 108" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6368++0x07 line.quad 0x00 "GICD_IROUTER109,Interrupt Routing Register 109" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6370++0x07 line.quad 0x00 "GICD_IROUTER110,Interrupt Routing Register 110" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6378++0x07 line.quad 0x00 "GICD_IROUTER111,Interrupt Routing Register 111" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6380++0x07 line.quad 0x00 "GICD_IROUTER112,Interrupt Routing Register 112" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6388++0x07 line.quad 0x00 "GICD_IROUTER113,Interrupt Routing Register 113" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6390++0x07 line.quad 0x00 "GICD_IROUTER114,Interrupt Routing Register 114" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6398++0x07 line.quad 0x00 "GICD_IROUTER115,Interrupt Routing Register 115" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63A0++0x07 line.quad 0x00 "GICD_IROUTER116,Interrupt Routing Register 116" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63A8++0x07 line.quad 0x00 "GICD_IROUTER117,Interrupt Routing Register 117" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63B0++0x07 line.quad 0x00 "GICD_IROUTER118,Interrupt Routing Register 118" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63B8++0x07 line.quad 0x00 "GICD_IROUTER119,Interrupt Routing Register 119" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63C0++0x07 line.quad 0x00 "GICD_IROUTER120,Interrupt Routing Register 120" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63C8++0x07 line.quad 0x00 "GICD_IROUTER121,Interrupt Routing Register 121" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63D0++0x07 line.quad 0x00 "GICD_IROUTER122,Interrupt Routing Register 122" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63D8++0x07 line.quad 0x00 "GICD_IROUTER123,Interrupt Routing Register 123" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63E0++0x07 line.quad 0x00 "GICD_IROUTER124,Interrupt Routing Register 124" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63E8++0x07 line.quad 0x00 "GICD_IROUTER125,Interrupt Routing Register 125" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63F0++0x07 line.quad 0x00 "GICD_IROUTER126,Interrupt Routing Register 126" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63F8++0x07 line.quad 0x00 "GICD_IROUTER127,Interrupt Routing Register 127" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6400++0x07 line.quad 0x00 "GICD_IROUTER128,Interrupt Routing Register 128" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6408++0x07 line.quad 0x00 "GICD_IROUTER129,Interrupt Routing Register 129" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6410++0x07 line.quad 0x00 "GICD_IROUTER130,Interrupt Routing Register 130" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6418++0x07 line.quad 0x00 "GICD_IROUTER131,Interrupt Routing Register 131" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6420++0x07 line.quad 0x00 "GICD_IROUTER132,Interrupt Routing Register 132" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6428++0x07 line.quad 0x00 "GICD_IROUTER133,Interrupt Routing Register 133" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6430++0x07 line.quad 0x00 "GICD_IROUTER134,Interrupt Routing Register 134" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6438++0x07 line.quad 0x00 "GICD_IROUTER135,Interrupt Routing Register 135" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6440++0x07 line.quad 0x00 "GICD_IROUTER136,Interrupt Routing Register 136" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6448++0x07 line.quad 0x00 "GICD_IROUTER137,Interrupt Routing Register 137" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6450++0x07 line.quad 0x00 "GICD_IROUTER138,Interrupt Routing Register 138" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6458++0x07 line.quad 0x00 "GICD_IROUTER139,Interrupt Routing Register 139" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6460++0x07 line.quad 0x00 "GICD_IROUTER140,Interrupt Routing Register 140" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6468++0x07 line.quad 0x00 "GICD_IROUTER141,Interrupt Routing Register 141" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6470++0x07 line.quad 0x00 "GICD_IROUTER142,Interrupt Routing Register 142" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6478++0x07 line.quad 0x00 "GICD_IROUTER143,Interrupt Routing Register 143" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6480++0x07 line.quad 0x00 "GICD_IROUTER144,Interrupt Routing Register 144" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6488++0x07 line.quad 0x00 "GICD_IROUTER145,Interrupt Routing Register 145" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6490++0x07 line.quad 0x00 "GICD_IROUTER146,Interrupt Routing Register 146" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6498++0x07 line.quad 0x00 "GICD_IROUTER147,Interrupt Routing Register 147" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64A0++0x07 line.quad 0x00 "GICD_IROUTER148,Interrupt Routing Register 148" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64A8++0x07 line.quad 0x00 "GICD_IROUTER149,Interrupt Routing Register 149" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64B0++0x07 line.quad 0x00 "GICD_IROUTER150,Interrupt Routing Register 150" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64B8++0x07 line.quad 0x00 "GICD_IROUTER151,Interrupt Routing Register 151" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64C0++0x07 line.quad 0x00 "GICD_IROUTER152,Interrupt Routing Register 152" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64C8++0x07 line.quad 0x00 "GICD_IROUTER153,Interrupt Routing Register 153" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64D0++0x07 line.quad 0x00 "GICD_IROUTER154,Interrupt Routing Register 154" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64D8++0x07 line.quad 0x00 "GICD_IROUTER155,Interrupt Routing Register 155" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64E0++0x07 line.quad 0x00 "GICD_IROUTER156,Interrupt Routing Register 156" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64E8++0x07 line.quad 0x00 "GICD_IROUTER157,Interrupt Routing Register 157" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64F0++0x07 line.quad 0x00 "GICD_IROUTER158,Interrupt Routing Register 158" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64F8++0x07 line.quad 0x00 "GICD_IROUTER159,Interrupt Routing Register 159" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6500++0x07 line.quad 0x00 "GICD_IROUTER160,Interrupt Routing Register 160" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6508++0x07 line.quad 0x00 "GICD_IROUTER161,Interrupt Routing Register 161" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6510++0x07 line.quad 0x00 "GICD_IROUTER162,Interrupt Routing Register 162" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6518++0x07 line.quad 0x00 "GICD_IROUTER163,Interrupt Routing Register 163" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6520++0x07 line.quad 0x00 "GICD_IROUTER164,Interrupt Routing Register 164" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6528++0x07 line.quad 0x00 "GICD_IROUTER165,Interrupt Routing Register 165" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6530++0x07 line.quad 0x00 "GICD_IROUTER166,Interrupt Routing Register 166" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6538++0x07 line.quad 0x00 "GICD_IROUTER167,Interrupt Routing Register 167" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6540++0x07 line.quad 0x00 "GICD_IROUTER168,Interrupt Routing Register 168" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6548++0x07 line.quad 0x00 "GICD_IROUTER169,Interrupt Routing Register 169" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6550++0x07 line.quad 0x00 "GICD_IROUTER170,Interrupt Routing Register 170" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6558++0x07 line.quad 0x00 "GICD_IROUTER171,Interrupt Routing Register 171" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6560++0x07 line.quad 0x00 "GICD_IROUTER172,Interrupt Routing Register 172" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6568++0x07 line.quad 0x00 "GICD_IROUTER173,Interrupt Routing Register 173" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6570++0x07 line.quad 0x00 "GICD_IROUTER174,Interrupt Routing Register 174" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6578++0x07 line.quad 0x00 "GICD_IROUTER175,Interrupt Routing Register 175" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6580++0x07 line.quad 0x00 "GICD_IROUTER176,Interrupt Routing Register 176" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6588++0x07 line.quad 0x00 "GICD_IROUTER177,Interrupt Routing Register 177" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6590++0x07 line.quad 0x00 "GICD_IROUTER178,Interrupt Routing Register 178" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6598++0x07 line.quad 0x00 "GICD_IROUTER179,Interrupt Routing Register 179" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65A0++0x07 line.quad 0x00 "GICD_IROUTER180,Interrupt Routing Register 180" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65A8++0x07 line.quad 0x00 "GICD_IROUTER181,Interrupt Routing Register 181" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65B0++0x07 line.quad 0x00 "GICD_IROUTER182,Interrupt Routing Register 182" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65B8++0x07 line.quad 0x00 "GICD_IROUTER183,Interrupt Routing Register 183" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65C0++0x07 line.quad 0x00 "GICD_IROUTER184,Interrupt Routing Register 184" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65C8++0x07 line.quad 0x00 "GICD_IROUTER185,Interrupt Routing Register 185" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65D0++0x07 line.quad 0x00 "GICD_IROUTER186,Interrupt Routing Register 186" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65D8++0x07 line.quad 0x00 "GICD_IROUTER187,Interrupt Routing Register 187" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65E0++0x07 line.quad 0x00 "GICD_IROUTER188,Interrupt Routing Register 188" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65E8++0x07 line.quad 0x00 "GICD_IROUTER189,Interrupt Routing Register 189" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65F0++0x07 line.quad 0x00 "GICD_IROUTER190,Interrupt Routing Register 190" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65F8++0x07 line.quad 0x00 "GICD_IROUTER191,Interrupt Routing Register 191" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6600++0x07 line.quad 0x00 "GICD_IROUTER192,Interrupt Routing Register 192" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6608++0x07 line.quad 0x00 "GICD_IROUTER193,Interrupt Routing Register 193" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6610++0x07 line.quad 0x00 "GICD_IROUTER194,Interrupt Routing Register 194" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6618++0x07 line.quad 0x00 "GICD_IROUTER195,Interrupt Routing Register 195" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6620++0x07 line.quad 0x00 "GICD_IROUTER196,Interrupt Routing Register 196" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6628++0x07 line.quad 0x00 "GICD_IROUTER197,Interrupt Routing Register 197" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6630++0x07 line.quad 0x00 "GICD_IROUTER198,Interrupt Routing Register 198" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6638++0x07 line.quad 0x00 "GICD_IROUTER199,Interrupt Routing Register 199" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6640++0x07 line.quad 0x00 "GICD_IROUTER200,Interrupt Routing Register 200" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6648++0x07 line.quad 0x00 "GICD_IROUTER201,Interrupt Routing Register 201" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6650++0x07 line.quad 0x00 "GICD_IROUTER202,Interrupt Routing Register 202" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6658++0x07 line.quad 0x00 "GICD_IROUTER203,Interrupt Routing Register 203" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6660++0x07 line.quad 0x00 "GICD_IROUTER204,Interrupt Routing Register 204" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6668++0x07 line.quad 0x00 "GICD_IROUTER205,Interrupt Routing Register 205" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6670++0x07 line.quad 0x00 "GICD_IROUTER206,Interrupt Routing Register 206" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6678++0x07 line.quad 0x00 "GICD_IROUTER207,Interrupt Routing Register 207" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6680++0x07 line.quad 0x00 "GICD_IROUTER208,Interrupt Routing Register 208" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6688++0x07 line.quad 0x00 "GICD_IROUTER209,Interrupt Routing Register 209" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6690++0x07 line.quad 0x00 "GICD_IROUTER210,Interrupt Routing Register 210" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6698++0x07 line.quad 0x00 "GICD_IROUTER211,Interrupt Routing Register 211" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66A0++0x07 line.quad 0x00 "GICD_IROUTER212,Interrupt Routing Register 212" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66A8++0x07 line.quad 0x00 "GICD_IROUTER213,Interrupt Routing Register 213" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66B0++0x07 line.quad 0x00 "GICD_IROUTER214,Interrupt Routing Register 214" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66B8++0x07 line.quad 0x00 "GICD_IROUTER215,Interrupt Routing Register 215" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66C0++0x07 line.quad 0x00 "GICD_IROUTER216,Interrupt Routing Register 216" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66C8++0x07 line.quad 0x00 "GICD_IROUTER217,Interrupt Routing Register 217" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66D0++0x07 line.quad 0x00 "GICD_IROUTER218,Interrupt Routing Register 218" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66D8++0x07 line.quad 0x00 "GICD_IROUTER219,Interrupt Routing Register 219" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66E0++0x07 line.quad 0x00 "GICD_IROUTER220,Interrupt Routing Register 220" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66E8++0x07 line.quad 0x00 "GICD_IROUTER221,Interrupt Routing Register 221" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66F0++0x07 line.quad 0x00 "GICD_IROUTER222,Interrupt Routing Register 222" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66F8++0x07 line.quad 0x00 "GICD_IROUTER223,Interrupt Routing Register 223" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6700++0x07 line.quad 0x00 "GICD_IROUTER224,Interrupt Routing Register 224" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6708++0x07 line.quad 0x00 "GICD_IROUTER225,Interrupt Routing Register 225" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6710++0x07 line.quad 0x00 "GICD_IROUTER226,Interrupt Routing Register 226" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6718++0x07 line.quad 0x00 "GICD_IROUTER227,Interrupt Routing Register 227" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6720++0x07 line.quad 0x00 "GICD_IROUTER228,Interrupt Routing Register 228" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6728++0x07 line.quad 0x00 "GICD_IROUTER229,Interrupt Routing Register 229" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6730++0x07 line.quad 0x00 "GICD_IROUTER230,Interrupt Routing Register 230" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6738++0x07 line.quad 0x00 "GICD_IROUTER231,Interrupt Routing Register 231" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6740++0x07 line.quad 0x00 "GICD_IROUTER232,Interrupt Routing Register 232" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6748++0x07 line.quad 0x00 "GICD_IROUTER233,Interrupt Routing Register 233" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6750++0x07 line.quad 0x00 "GICD_IROUTER234,Interrupt Routing Register 234" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6758++0x07 line.quad 0x00 "GICD_IROUTER235,Interrupt Routing Register 235" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6760++0x07 line.quad 0x00 "GICD_IROUTER236,Interrupt Routing Register 236" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6768++0x07 line.quad 0x00 "GICD_IROUTER237,Interrupt Routing Register 237" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6770++0x07 line.quad 0x00 "GICD_IROUTER238,Interrupt Routing Register 238" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6778++0x07 line.quad 0x00 "GICD_IROUTER239,Interrupt Routing Register 239" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6780++0x07 line.quad 0x00 "GICD_IROUTER240,Interrupt Routing Register 240" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6788++0x07 line.quad 0x00 "GICD_IROUTER241,Interrupt Routing Register 241" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6790++0x07 line.quad 0x00 "GICD_IROUTER242,Interrupt Routing Register 242" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6798++0x07 line.quad 0x00 "GICD_IROUTER243,Interrupt Routing Register 243" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67A0++0x07 line.quad 0x00 "GICD_IROUTER244,Interrupt Routing Register 244" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67A8++0x07 line.quad 0x00 "GICD_IROUTER245,Interrupt Routing Register 245" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67B0++0x07 line.quad 0x00 "GICD_IROUTER246,Interrupt Routing Register 246" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67B8++0x07 line.quad 0x00 "GICD_IROUTER247,Interrupt Routing Register 247" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67C0++0x07 line.quad 0x00 "GICD_IROUTER248,Interrupt Routing Register 248" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67C8++0x07 line.quad 0x00 "GICD_IROUTER249,Interrupt Routing Register 249" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67D0++0x07 line.quad 0x00 "GICD_IROUTER250,Interrupt Routing Register 250" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67D8++0x07 line.quad 0x00 "GICD_IROUTER251,Interrupt Routing Register 251" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67E0++0x07 line.quad 0x00 "GICD_IROUTER252,Interrupt Routing Register 252" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67E8++0x07 line.quad 0x00 "GICD_IROUTER253,Interrupt Routing Register 253" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67F0++0x07 line.quad 0x00 "GICD_IROUTER254,Interrupt Routing Register 254" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67F8++0x07 line.quad 0x00 "GICD_IROUTER255,Interrupt Routing Register 255" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6800++0x07 line.quad 0x00 "GICD_IROUTER256,Interrupt Routing Register 256" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6808++0x07 line.quad 0x00 "GICD_IROUTER257,Interrupt Routing Register 257" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6810++0x07 line.quad 0x00 "GICD_IROUTER258,Interrupt Routing Register 258" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6818++0x07 line.quad 0x00 "GICD_IROUTER259,Interrupt Routing Register 259" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6820++0x07 line.quad 0x00 "GICD_IROUTER260,Interrupt Routing Register 260" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6828++0x07 line.quad 0x00 "GICD_IROUTER261,Interrupt Routing Register 261" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6830++0x07 line.quad 0x00 "GICD_IROUTER262,Interrupt Routing Register 262" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6838++0x07 line.quad 0x00 "GICD_IROUTER263,Interrupt Routing Register 263" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6840++0x07 line.quad 0x00 "GICD_IROUTER264,Interrupt Routing Register 264" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6848++0x07 line.quad 0x00 "GICD_IROUTER265,Interrupt Routing Register 265" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6850++0x07 line.quad 0x00 "GICD_IROUTER266,Interrupt Routing Register 266" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6858++0x07 line.quad 0x00 "GICD_IROUTER267,Interrupt Routing Register 267" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6860++0x07 line.quad 0x00 "GICD_IROUTER268,Interrupt Routing Register 268" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6868++0x07 line.quad 0x00 "GICD_IROUTER269,Interrupt Routing Register 269" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6870++0x07 line.quad 0x00 "GICD_IROUTER270,Interrupt Routing Register 270" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6878++0x07 line.quad 0x00 "GICD_IROUTER271,Interrupt Routing Register 271" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6880++0x07 line.quad 0x00 "GICD_IROUTER272,Interrupt Routing Register 272" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6888++0x07 line.quad 0x00 "GICD_IROUTER273,Interrupt Routing Register 273" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6890++0x07 line.quad 0x00 "GICD_IROUTER274,Interrupt Routing Register 274" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6898++0x07 line.quad 0x00 "GICD_IROUTER275,Interrupt Routing Register 275" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68A0++0x07 line.quad 0x00 "GICD_IROUTER276,Interrupt Routing Register 276" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68A8++0x07 line.quad 0x00 "GICD_IROUTER277,Interrupt Routing Register 277" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68B0++0x07 line.quad 0x00 "GICD_IROUTER278,Interrupt Routing Register 278" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68B8++0x07 line.quad 0x00 "GICD_IROUTER279,Interrupt Routing Register 279" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68C0++0x07 line.quad 0x00 "GICD_IROUTER280,Interrupt Routing Register 280" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68C8++0x07 line.quad 0x00 "GICD_IROUTER281,Interrupt Routing Register 281" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68D0++0x07 line.quad 0x00 "GICD_IROUTER282,Interrupt Routing Register 282" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68D8++0x07 line.quad 0x00 "GICD_IROUTER283,Interrupt Routing Register 283" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68E0++0x07 line.quad 0x00 "GICD_IROUTER284,Interrupt Routing Register 284" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68E8++0x07 line.quad 0x00 "GICD_IROUTER285,Interrupt Routing Register 285" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68F0++0x07 line.quad 0x00 "GICD_IROUTER286,Interrupt Routing Register 286" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68F8++0x07 line.quad 0x00 "GICD_IROUTER287,Interrupt Routing Register 287" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6900++0x07 line.quad 0x00 "GICD_IROUTER288,Interrupt Routing Register 288" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6908++0x07 line.quad 0x00 "GICD_IROUTER289,Interrupt Routing Register 289" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6910++0x07 line.quad 0x00 "GICD_IROUTER290,Interrupt Routing Register 290" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6918++0x07 line.quad 0x00 "GICD_IROUTER291,Interrupt Routing Register 291" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6920++0x07 line.quad 0x00 "GICD_IROUTER292,Interrupt Routing Register 292" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6928++0x07 line.quad 0x00 "GICD_IROUTER293,Interrupt Routing Register 293" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6930++0x07 line.quad 0x00 "GICD_IROUTER294,Interrupt Routing Register 294" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6938++0x07 line.quad 0x00 "GICD_IROUTER295,Interrupt Routing Register 295" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6940++0x07 line.quad 0x00 "GICD_IROUTER296,Interrupt Routing Register 296" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6948++0x07 line.quad 0x00 "GICD_IROUTER297,Interrupt Routing Register 297" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6950++0x07 line.quad 0x00 "GICD_IROUTER298,Interrupt Routing Register 298" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6958++0x07 line.quad 0x00 "GICD_IROUTER299,Interrupt Routing Register 299" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6960++0x07 line.quad 0x00 "GICD_IROUTER300,Interrupt Routing Register 300" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6968++0x07 line.quad 0x00 "GICD_IROUTER301,Interrupt Routing Register 301" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6970++0x07 line.quad 0x00 "GICD_IROUTER302,Interrupt Routing Register 302" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6978++0x07 line.quad 0x00 "GICD_IROUTER303,Interrupt Routing Register 303" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6980++0x07 line.quad 0x00 "GICD_IROUTER304,Interrupt Routing Register 304" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6988++0x07 line.quad 0x00 "GICD_IROUTER305,Interrupt Routing Register 305" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6990++0x07 line.quad 0x00 "GICD_IROUTER306,Interrupt Routing Register 306" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6998++0x07 line.quad 0x00 "GICD_IROUTER307,Interrupt Routing Register 307" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69A0++0x07 line.quad 0x00 "GICD_IROUTER308,Interrupt Routing Register 308" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69A8++0x07 line.quad 0x00 "GICD_IROUTER309,Interrupt Routing Register 309" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69B0++0x07 line.quad 0x00 "GICD_IROUTER310,Interrupt Routing Register 310" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69B8++0x07 line.quad 0x00 "GICD_IROUTER311,Interrupt Routing Register 311" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69C0++0x07 line.quad 0x00 "GICD_IROUTER312,Interrupt Routing Register 312" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69C8++0x07 line.quad 0x00 "GICD_IROUTER313,Interrupt Routing Register 313" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69D0++0x07 line.quad 0x00 "GICD_IROUTER314,Interrupt Routing Register 314" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69D8++0x07 line.quad 0x00 "GICD_IROUTER315,Interrupt Routing Register 315" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69E0++0x07 line.quad 0x00 "GICD_IROUTER316,Interrupt Routing Register 316" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69E8++0x07 line.quad 0x00 "GICD_IROUTER317,Interrupt Routing Register 317" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69F0++0x07 line.quad 0x00 "GICD_IROUTER318,Interrupt Routing Register 318" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69F8++0x07 line.quad 0x00 "GICD_IROUTER319,Interrupt Routing Register 319" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A00++0x07 line.quad 0x00 "GICD_IROUTER320,Interrupt Routing Register 320" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A08++0x07 line.quad 0x00 "GICD_IROUTER321,Interrupt Routing Register 321" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A10++0x07 line.quad 0x00 "GICD_IROUTER322,Interrupt Routing Register 322" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A18++0x07 line.quad 0x00 "GICD_IROUTER323,Interrupt Routing Register 323" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A20++0x07 line.quad 0x00 "GICD_IROUTER324,Interrupt Routing Register 324" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A28++0x07 line.quad 0x00 "GICD_IROUTER325,Interrupt Routing Register 325" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A30++0x07 line.quad 0x00 "GICD_IROUTER326,Interrupt Routing Register 326" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A38++0x07 line.quad 0x00 "GICD_IROUTER327,Interrupt Routing Register 327" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A40++0x07 line.quad 0x00 "GICD_IROUTER328,Interrupt Routing Register 328" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A48++0x07 line.quad 0x00 "GICD_IROUTER329,Interrupt Routing Register 329" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A50++0x07 line.quad 0x00 "GICD_IROUTER330,Interrupt Routing Register 330" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A58++0x07 line.quad 0x00 "GICD_IROUTER331,Interrupt Routing Register 331" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A60++0x07 line.quad 0x00 "GICD_IROUTER332,Interrupt Routing Register 332" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A68++0x07 line.quad 0x00 "GICD_IROUTER333,Interrupt Routing Register 333" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A70++0x07 line.quad 0x00 "GICD_IROUTER334,Interrupt Routing Register 334" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A78++0x07 line.quad 0x00 "GICD_IROUTER335,Interrupt Routing Register 335" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A80++0x07 line.quad 0x00 "GICD_IROUTER336,Interrupt Routing Register 336" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A88++0x07 line.quad 0x00 "GICD_IROUTER337,Interrupt Routing Register 337" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A90++0x07 line.quad 0x00 "GICD_IROUTER338,Interrupt Routing Register 338" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A98++0x07 line.quad 0x00 "GICD_IROUTER339,Interrupt Routing Register 339" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AA0++0x07 line.quad 0x00 "GICD_IROUTER340,Interrupt Routing Register 340" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AA8++0x07 line.quad 0x00 "GICD_IROUTER341,Interrupt Routing Register 341" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AB0++0x07 line.quad 0x00 "GICD_IROUTER342,Interrupt Routing Register 342" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AB8++0x07 line.quad 0x00 "GICD_IROUTER343,Interrupt Routing Register 343" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AC0++0x07 line.quad 0x00 "GICD_IROUTER344,Interrupt Routing Register 344" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AC8++0x07 line.quad 0x00 "GICD_IROUTER345,Interrupt Routing Register 345" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AD0++0x07 line.quad 0x00 "GICD_IROUTER346,Interrupt Routing Register 346" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AD8++0x07 line.quad 0x00 "GICD_IROUTER347,Interrupt Routing Register 347" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AE0++0x07 line.quad 0x00 "GICD_IROUTER348,Interrupt Routing Register 348" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AE8++0x07 line.quad 0x00 "GICD_IROUTER349,Interrupt Routing Register 349" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AF0++0x07 line.quad 0x00 "GICD_IROUTER350,Interrupt Routing Register 350" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AF8++0x07 line.quad 0x00 "GICD_IROUTER351,Interrupt Routing Register 351" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B00++0x07 line.quad 0x00 "GICD_IROUTER352,Interrupt Routing Register 352" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B08++0x07 line.quad 0x00 "GICD_IROUTER353,Interrupt Routing Register 353" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B10++0x07 line.quad 0x00 "GICD_IROUTER354,Interrupt Routing Register 354" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B18++0x07 line.quad 0x00 "GICD_IROUTER355,Interrupt Routing Register 355" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B20++0x07 line.quad 0x00 "GICD_IROUTER356,Interrupt Routing Register 356" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B28++0x07 line.quad 0x00 "GICD_IROUTER357,Interrupt Routing Register 357" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B30++0x07 line.quad 0x00 "GICD_IROUTER358,Interrupt Routing Register 358" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B38++0x07 line.quad 0x00 "GICD_IROUTER359,Interrupt Routing Register 359" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B40++0x07 line.quad 0x00 "GICD_IROUTER360,Interrupt Routing Register 360" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B48++0x07 line.quad 0x00 "GICD_IROUTER361,Interrupt Routing Register 361" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B50++0x07 line.quad 0x00 "GICD_IROUTER362,Interrupt Routing Register 362" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B58++0x07 line.quad 0x00 "GICD_IROUTER363,Interrupt Routing Register 363" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B60++0x07 line.quad 0x00 "GICD_IROUTER364,Interrupt Routing Register 364" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B68++0x07 line.quad 0x00 "GICD_IROUTER365,Interrupt Routing Register 365" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B70++0x07 line.quad 0x00 "GICD_IROUTER366,Interrupt Routing Register 366" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B78++0x07 line.quad 0x00 "GICD_IROUTER367,Interrupt Routing Register 367" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B80++0x07 line.quad 0x00 "GICD_IROUTER368,Interrupt Routing Register 368" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B88++0x07 line.quad 0x00 "GICD_IROUTER369,Interrupt Routing Register 369" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B90++0x07 line.quad 0x00 "GICD_IROUTER370,Interrupt Routing Register 370" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B98++0x07 line.quad 0x00 "GICD_IROUTER371,Interrupt Routing Register 371" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BA0++0x07 line.quad 0x00 "GICD_IROUTER372,Interrupt Routing Register 372" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BA8++0x07 line.quad 0x00 "GICD_IROUTER373,Interrupt Routing Register 373" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BB0++0x07 line.quad 0x00 "GICD_IROUTER374,Interrupt Routing Register 374" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BB8++0x07 line.quad 0x00 "GICD_IROUTER375,Interrupt Routing Register 375" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BC0++0x07 line.quad 0x00 "GICD_IROUTER376,Interrupt Routing Register 376" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BC8++0x07 line.quad 0x00 "GICD_IROUTER377,Interrupt Routing Register 377" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BD0++0x07 line.quad 0x00 "GICD_IROUTER378,Interrupt Routing Register 378" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BD8++0x07 line.quad 0x00 "GICD_IROUTER379,Interrupt Routing Register 379" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BE0++0x07 line.quad 0x00 "GICD_IROUTER380,Interrupt Routing Register 380" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BE8++0x07 line.quad 0x00 "GICD_IROUTER381,Interrupt Routing Register 381" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BF0++0x07 line.quad 0x00 "GICD_IROUTER382,Interrupt Routing Register 382" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BF8++0x07 line.quad 0x00 "GICD_IROUTER383,Interrupt Routing Register 383" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C00++0x07 line.quad 0x00 "GICD_IROUTER384,Interrupt Routing Register 384" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C08++0x07 line.quad 0x00 "GICD_IROUTER385,Interrupt Routing Register 385" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C10++0x07 line.quad 0x00 "GICD_IROUTER386,Interrupt Routing Register 386" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C18++0x07 line.quad 0x00 "GICD_IROUTER387,Interrupt Routing Register 387" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C20++0x07 line.quad 0x00 "GICD_IROUTER388,Interrupt Routing Register 388" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C28++0x07 line.quad 0x00 "GICD_IROUTER389,Interrupt Routing Register 389" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C30++0x07 line.quad 0x00 "GICD_IROUTER390,Interrupt Routing Register 390" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C38++0x07 line.quad 0x00 "GICD_IROUTER391,Interrupt Routing Register 391" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C40++0x07 line.quad 0x00 "GICD_IROUTER392,Interrupt Routing Register 392" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C48++0x07 line.quad 0x00 "GICD_IROUTER393,Interrupt Routing Register 393" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C50++0x07 line.quad 0x00 "GICD_IROUTER394,Interrupt Routing Register 394" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C58++0x07 line.quad 0x00 "GICD_IROUTER395,Interrupt Routing Register 395" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C60++0x07 line.quad 0x00 "GICD_IROUTER396,Interrupt Routing Register 396" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C68++0x07 line.quad 0x00 "GICD_IROUTER397,Interrupt Routing Register 397" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C70++0x07 line.quad 0x00 "GICD_IROUTER398,Interrupt Routing Register 398" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C78++0x07 line.quad 0x00 "GICD_IROUTER399,Interrupt Routing Register 399" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C80++0x07 line.quad 0x00 "GICD_IROUTER400,Interrupt Routing Register 400" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C88++0x07 line.quad 0x00 "GICD_IROUTER401,Interrupt Routing Register 401" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C90++0x07 line.quad 0x00 "GICD_IROUTER402,Interrupt Routing Register 402" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C98++0x07 line.quad 0x00 "GICD_IROUTER403,Interrupt Routing Register 403" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CA0++0x07 line.quad 0x00 "GICD_IROUTER404,Interrupt Routing Register 404" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CA8++0x07 line.quad 0x00 "GICD_IROUTER405,Interrupt Routing Register 405" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CB0++0x07 line.quad 0x00 "GICD_IROUTER406,Interrupt Routing Register 406" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CB8++0x07 line.quad 0x00 "GICD_IROUTER407,Interrupt Routing Register 407" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CC0++0x07 line.quad 0x00 "GICD_IROUTER408,Interrupt Routing Register 408" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CC8++0x07 line.quad 0x00 "GICD_IROUTER409,Interrupt Routing Register 409" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CD0++0x07 line.quad 0x00 "GICD_IROUTER410,Interrupt Routing Register 410" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CD8++0x07 line.quad 0x00 "GICD_IROUTER411,Interrupt Routing Register 411" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CE0++0x07 line.quad 0x00 "GICD_IROUTER412,Interrupt Routing Register 412" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CE8++0x07 line.quad 0x00 "GICD_IROUTER413,Interrupt Routing Register 413" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CF0++0x07 line.quad 0x00 "GICD_IROUTER414,Interrupt Routing Register 414" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CF8++0x07 line.quad 0x00 "GICD_IROUTER415,Interrupt Routing Register 415" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D00++0x07 line.quad 0x00 "GICD_IROUTER416,Interrupt Routing Register 416" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D08++0x07 line.quad 0x00 "GICD_IROUTER417,Interrupt Routing Register 417" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D10++0x07 line.quad 0x00 "GICD_IROUTER418,Interrupt Routing Register 418" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D18++0x07 line.quad 0x00 "GICD_IROUTER419,Interrupt Routing Register 419" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D20++0x07 line.quad 0x00 "GICD_IROUTER420,Interrupt Routing Register 420" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D28++0x07 line.quad 0x00 "GICD_IROUTER421,Interrupt Routing Register 421" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D30++0x07 line.quad 0x00 "GICD_IROUTER422,Interrupt Routing Register 422" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D38++0x07 line.quad 0x00 "GICD_IROUTER423,Interrupt Routing Register 423" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D40++0x07 line.quad 0x00 "GICD_IROUTER424,Interrupt Routing Register 424" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D48++0x07 line.quad 0x00 "GICD_IROUTER425,Interrupt Routing Register 425" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D50++0x07 line.quad 0x00 "GICD_IROUTER426,Interrupt Routing Register 426" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D58++0x07 line.quad 0x00 "GICD_IROUTER427,Interrupt Routing Register 427" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D60++0x07 line.quad 0x00 "GICD_IROUTER428,Interrupt Routing Register 428" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D68++0x07 line.quad 0x00 "GICD_IROUTER429,Interrupt Routing Register 429" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D70++0x07 line.quad 0x00 "GICD_IROUTER430,Interrupt Routing Register 430" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D78++0x07 line.quad 0x00 "GICD_IROUTER431,Interrupt Routing Register 431" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D80++0x07 line.quad 0x00 "GICD_IROUTER432,Interrupt Routing Register 432" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D88++0x07 line.quad 0x00 "GICD_IROUTER433,Interrupt Routing Register 433" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D90++0x07 line.quad 0x00 "GICD_IROUTER434,Interrupt Routing Register 434" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D98++0x07 line.quad 0x00 "GICD_IROUTER435,Interrupt Routing Register 435" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DA0++0x07 line.quad 0x00 "GICD_IROUTER436,Interrupt Routing Register 436" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DA8++0x07 line.quad 0x00 "GICD_IROUTER437,Interrupt Routing Register 437" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DB0++0x07 line.quad 0x00 "GICD_IROUTER438,Interrupt Routing Register 438" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DB8++0x07 line.quad 0x00 "GICD_IROUTER439,Interrupt Routing Register 439" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DC0++0x07 line.quad 0x00 "GICD_IROUTER440,Interrupt Routing Register 440" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DC8++0x07 line.quad 0x00 "GICD_IROUTER441,Interrupt Routing Register 441" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DD0++0x07 line.quad 0x00 "GICD_IROUTER442,Interrupt Routing Register 442" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DD8++0x07 line.quad 0x00 "GICD_IROUTER443,Interrupt Routing Register 443" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DE0++0x07 line.quad 0x00 "GICD_IROUTER444,Interrupt Routing Register 444" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DE8++0x07 line.quad 0x00 "GICD_IROUTER445,Interrupt Routing Register 445" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DF0++0x07 line.quad 0x00 "GICD_IROUTER446,Interrupt Routing Register 446" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DF8++0x07 line.quad 0x00 "GICD_IROUTER447,Interrupt Routing Register 447" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E00++0x07 line.quad 0x00 "GICD_IROUTER448,Interrupt Routing Register 448" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E08++0x07 line.quad 0x00 "GICD_IROUTER449,Interrupt Routing Register 449" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E10++0x07 line.quad 0x00 "GICD_IROUTER450,Interrupt Routing Register 450" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E18++0x07 line.quad 0x00 "GICD_IROUTER451,Interrupt Routing Register 451" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E20++0x07 line.quad 0x00 "GICD_IROUTER452,Interrupt Routing Register 452" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E28++0x07 line.quad 0x00 "GICD_IROUTER453,Interrupt Routing Register 453" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E30++0x07 line.quad 0x00 "GICD_IROUTER454,Interrupt Routing Register 454" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E38++0x07 line.quad 0x00 "GICD_IROUTER455,Interrupt Routing Register 455" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E40++0x07 line.quad 0x00 "GICD_IROUTER456,Interrupt Routing Register 456" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E48++0x07 line.quad 0x00 "GICD_IROUTER457,Interrupt Routing Register 457" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E50++0x07 line.quad 0x00 "GICD_IROUTER458,Interrupt Routing Register 458" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E58++0x07 line.quad 0x00 "GICD_IROUTER459,Interrupt Routing Register 459" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E60++0x07 line.quad 0x00 "GICD_IROUTER460,Interrupt Routing Register 460" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E68++0x07 line.quad 0x00 "GICD_IROUTER461,Interrupt Routing Register 461" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E70++0x07 line.quad 0x00 "GICD_IROUTER462,Interrupt Routing Register 462" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E78++0x07 line.quad 0x00 "GICD_IROUTER463,Interrupt Routing Register 463" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E80++0x07 line.quad 0x00 "GICD_IROUTER464,Interrupt Routing Register 464" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E88++0x07 line.quad 0x00 "GICD_IROUTER465,Interrupt Routing Register 465" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E90++0x07 line.quad 0x00 "GICD_IROUTER466,Interrupt Routing Register 466" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E98++0x07 line.quad 0x00 "GICD_IROUTER467,Interrupt Routing Register 467" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EA0++0x07 line.quad 0x00 "GICD_IROUTER468,Interrupt Routing Register 468" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EA8++0x07 line.quad 0x00 "GICD_IROUTER469,Interrupt Routing Register 469" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EB0++0x07 line.quad 0x00 "GICD_IROUTER470,Interrupt Routing Register 470" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EB8++0x07 line.quad 0x00 "GICD_IROUTER471,Interrupt Routing Register 471" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EC0++0x07 line.quad 0x00 "GICD_IROUTER472,Interrupt Routing Register 472" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EC8++0x07 line.quad 0x00 "GICD_IROUTER473,Interrupt Routing Register 473" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6ED0++0x07 line.quad 0x00 "GICD_IROUTER474,Interrupt Routing Register 474" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6ED8++0x07 line.quad 0x00 "GICD_IROUTER475,Interrupt Routing Register 475" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EE0++0x07 line.quad 0x00 "GICD_IROUTER476,Interrupt Routing Register 476" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EE8++0x07 line.quad 0x00 "GICD_IROUTER477,Interrupt Routing Register 477" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EF0++0x07 line.quad 0x00 "GICD_IROUTER478,Interrupt Routing Register 478" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EF8++0x07 line.quad 0x00 "GICD_IROUTER479,Interrupt Routing Register 479" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F00++0x07 line.quad 0x00 "GICD_IROUTER480,Interrupt Routing Register 480" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F08++0x07 line.quad 0x00 "GICD_IROUTER481,Interrupt Routing Register 481" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F10++0x07 line.quad 0x00 "GICD_IROUTER482,Interrupt Routing Register 482" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F18++0x07 line.quad 0x00 "GICD_IROUTER483,Interrupt Routing Register 483" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F20++0x07 line.quad 0x00 "GICD_IROUTER484,Interrupt Routing Register 484" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F28++0x07 line.quad 0x00 "GICD_IROUTER485,Interrupt Routing Register 485" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F30++0x07 line.quad 0x00 "GICD_IROUTER486,Interrupt Routing Register 486" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F38++0x07 line.quad 0x00 "GICD_IROUTER487,Interrupt Routing Register 487" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F40++0x07 line.quad 0x00 "GICD_IROUTER488,Interrupt Routing Register 488" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F48++0x07 line.quad 0x00 "GICD_IROUTER489,Interrupt Routing Register 489" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F50++0x07 line.quad 0x00 "GICD_IROUTER490,Interrupt Routing Register 490" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F58++0x07 line.quad 0x00 "GICD_IROUTER491,Interrupt Routing Register 491" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F60++0x07 line.quad 0x00 "GICD_IROUTER492,Interrupt Routing Register 492" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F68++0x07 line.quad 0x00 "GICD_IROUTER493,Interrupt Routing Register 493" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F70++0x07 line.quad 0x00 "GICD_IROUTER494,Interrupt Routing Register 494" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F78++0x07 line.quad 0x00 "GICD_IROUTER495,Interrupt Routing Register 495" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F80++0x07 line.quad 0x00 "GICD_IROUTER496,Interrupt Routing Register 496" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F88++0x07 line.quad 0x00 "GICD_IROUTER497,Interrupt Routing Register 497" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F90++0x07 line.quad 0x00 "GICD_IROUTER498,Interrupt Routing Register 498" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F98++0x07 line.quad 0x00 "GICD_IROUTER499,Interrupt Routing Register 499" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FA0++0x07 line.quad 0x00 "GICD_IROUTER500,Interrupt Routing Register 500" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FA8++0x07 line.quad 0x00 "GICD_IROUTER501,Interrupt Routing Register 501" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FB0++0x07 line.quad 0x00 "GICD_IROUTER502,Interrupt Routing Register 502" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FB8++0x07 line.quad 0x00 "GICD_IROUTER503,Interrupt Routing Register 503" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FC0++0x07 line.quad 0x00 "GICD_IROUTER504,Interrupt Routing Register 504" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FC8++0x07 line.quad 0x00 "GICD_IROUTER505,Interrupt Routing Register 505" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FD0++0x07 line.quad 0x00 "GICD_IROUTER506,Interrupt Routing Register 506" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FD8++0x07 line.quad 0x00 "GICD_IROUTER507,Interrupt Routing Register 507" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FE0++0x07 line.quad 0x00 "GICD_IROUTER508,Interrupt Routing Register 508" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FE8++0x07 line.quad 0x00 "GICD_IROUTER509,Interrupt Routing Register 509" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FF0++0x07 line.quad 0x00 "GICD_IROUTER510,Interrupt Routing Register 510" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FF8++0x07 line.quad 0x00 "GICD_IROUTER511,Interrupt Routing Register 511" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7000++0x07 line.quad 0x00 "GICD_IROUTER512,Interrupt Routing Register 512" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7008++0x07 line.quad 0x00 "GICD_IROUTER513,Interrupt Routing Register 513" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7010++0x07 line.quad 0x00 "GICD_IROUTER514,Interrupt Routing Register 514" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7018++0x07 line.quad 0x00 "GICD_IROUTER515,Interrupt Routing Register 515" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7020++0x07 line.quad 0x00 "GICD_IROUTER516,Interrupt Routing Register 516" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7028++0x07 line.quad 0x00 "GICD_IROUTER517,Interrupt Routing Register 517" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7030++0x07 line.quad 0x00 "GICD_IROUTER518,Interrupt Routing Register 518" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7038++0x07 line.quad 0x00 "GICD_IROUTER519,Interrupt Routing Register 519" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7040++0x07 line.quad 0x00 "GICD_IROUTER520,Interrupt Routing Register 520" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7048++0x07 line.quad 0x00 "GICD_IROUTER521,Interrupt Routing Register 521" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7050++0x07 line.quad 0x00 "GICD_IROUTER522,Interrupt Routing Register 522" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7058++0x07 line.quad 0x00 "GICD_IROUTER523,Interrupt Routing Register 523" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7060++0x07 line.quad 0x00 "GICD_IROUTER524,Interrupt Routing Register 524" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7068++0x07 line.quad 0x00 "GICD_IROUTER525,Interrupt Routing Register 525" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7070++0x07 line.quad 0x00 "GICD_IROUTER526,Interrupt Routing Register 526" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7078++0x07 line.quad 0x00 "GICD_IROUTER527,Interrupt Routing Register 527" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7080++0x07 line.quad 0x00 "GICD_IROUTER528,Interrupt Routing Register 528" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7088++0x07 line.quad 0x00 "GICD_IROUTER529,Interrupt Routing Register 529" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7090++0x07 line.quad 0x00 "GICD_IROUTER530,Interrupt Routing Register 530" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7098++0x07 line.quad 0x00 "GICD_IROUTER531,Interrupt Routing Register 531" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70A0++0x07 line.quad 0x00 "GICD_IROUTER532,Interrupt Routing Register 532" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70A8++0x07 line.quad 0x00 "GICD_IROUTER533,Interrupt Routing Register 533" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70B0++0x07 line.quad 0x00 "GICD_IROUTER534,Interrupt Routing Register 534" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70B8++0x07 line.quad 0x00 "GICD_IROUTER535,Interrupt Routing Register 535" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70C0++0x07 line.quad 0x00 "GICD_IROUTER536,Interrupt Routing Register 536" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70C8++0x07 line.quad 0x00 "GICD_IROUTER537,Interrupt Routing Register 537" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70D0++0x07 line.quad 0x00 "GICD_IROUTER538,Interrupt Routing Register 538" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70D8++0x07 line.quad 0x00 "GICD_IROUTER539,Interrupt Routing Register 539" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70E0++0x07 line.quad 0x00 "GICD_IROUTER540,Interrupt Routing Register 540" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70E8++0x07 line.quad 0x00 "GICD_IROUTER541,Interrupt Routing Register 541" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70F0++0x07 line.quad 0x00 "GICD_IROUTER542,Interrupt Routing Register 542" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70F8++0x07 line.quad 0x00 "GICD_IROUTER543,Interrupt Routing Register 543" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7100++0x07 line.quad 0x00 "GICD_IROUTER544,Interrupt Routing Register 544" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7108++0x07 line.quad 0x00 "GICD_IROUTER545,Interrupt Routing Register 545" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7110++0x07 line.quad 0x00 "GICD_IROUTER546,Interrupt Routing Register 546" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7118++0x07 line.quad 0x00 "GICD_IROUTER547,Interrupt Routing Register 547" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7120++0x07 line.quad 0x00 "GICD_IROUTER548,Interrupt Routing Register 548" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7128++0x07 line.quad 0x00 "GICD_IROUTER549,Interrupt Routing Register 549" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7130++0x07 line.quad 0x00 "GICD_IROUTER550,Interrupt Routing Register 550" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7138++0x07 line.quad 0x00 "GICD_IROUTER551,Interrupt Routing Register 551" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7140++0x07 line.quad 0x00 "GICD_IROUTER552,Interrupt Routing Register 552" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7148++0x07 line.quad 0x00 "GICD_IROUTER553,Interrupt Routing Register 553" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7150++0x07 line.quad 0x00 "GICD_IROUTER554,Interrupt Routing Register 554" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7158++0x07 line.quad 0x00 "GICD_IROUTER555,Interrupt Routing Register 555" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7160++0x07 line.quad 0x00 "GICD_IROUTER556,Interrupt Routing Register 556" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7168++0x07 line.quad 0x00 "GICD_IROUTER557,Interrupt Routing Register 557" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7170++0x07 line.quad 0x00 "GICD_IROUTER558,Interrupt Routing Register 558" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7178++0x07 line.quad 0x00 "GICD_IROUTER559,Interrupt Routing Register 559" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7180++0x07 line.quad 0x00 "GICD_IROUTER560,Interrupt Routing Register 560" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7188++0x07 line.quad 0x00 "GICD_IROUTER561,Interrupt Routing Register 561" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7190++0x07 line.quad 0x00 "GICD_IROUTER562,Interrupt Routing Register 562" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7198++0x07 line.quad 0x00 "GICD_IROUTER563,Interrupt Routing Register 563" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71A0++0x07 line.quad 0x00 "GICD_IROUTER564,Interrupt Routing Register 564" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71A8++0x07 line.quad 0x00 "GICD_IROUTER565,Interrupt Routing Register 565" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71B0++0x07 line.quad 0x00 "GICD_IROUTER566,Interrupt Routing Register 566" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71B8++0x07 line.quad 0x00 "GICD_IROUTER567,Interrupt Routing Register 567" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71C0++0x07 line.quad 0x00 "GICD_IROUTER568,Interrupt Routing Register 568" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71C8++0x07 line.quad 0x00 "GICD_IROUTER569,Interrupt Routing Register 569" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71D0++0x07 line.quad 0x00 "GICD_IROUTER570,Interrupt Routing Register 570" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71D8++0x07 line.quad 0x00 "GICD_IROUTER571,Interrupt Routing Register 571" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71E0++0x07 line.quad 0x00 "GICD_IROUTER572,Interrupt Routing Register 572" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71E8++0x07 line.quad 0x00 "GICD_IROUTER573,Interrupt Routing Register 573" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71F0++0x07 line.quad 0x00 "GICD_IROUTER574,Interrupt Routing Register 574" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71F8++0x07 line.quad 0x00 "GICD_IROUTER575,Interrupt Routing Register 575" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7200++0x07 line.quad 0x00 "GICD_IROUTER576,Interrupt Routing Register 576" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7208++0x07 line.quad 0x00 "GICD_IROUTER577,Interrupt Routing Register 577" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7210++0x07 line.quad 0x00 "GICD_IROUTER578,Interrupt Routing Register 578" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7218++0x07 line.quad 0x00 "GICD_IROUTER579,Interrupt Routing Register 579" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7220++0x07 line.quad 0x00 "GICD_IROUTER580,Interrupt Routing Register 580" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7228++0x07 line.quad 0x00 "GICD_IROUTER581,Interrupt Routing Register 581" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7230++0x07 line.quad 0x00 "GICD_IROUTER582,Interrupt Routing Register 582" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7238++0x07 line.quad 0x00 "GICD_IROUTER583,Interrupt Routing Register 583" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7240++0x07 line.quad 0x00 "GICD_IROUTER584,Interrupt Routing Register 584" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7248++0x07 line.quad 0x00 "GICD_IROUTER585,Interrupt Routing Register 585" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7250++0x07 line.quad 0x00 "GICD_IROUTER586,Interrupt Routing Register 586" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7258++0x07 line.quad 0x00 "GICD_IROUTER587,Interrupt Routing Register 587" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7260++0x07 line.quad 0x00 "GICD_IROUTER588,Interrupt Routing Register 588" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7268++0x07 line.quad 0x00 "GICD_IROUTER589,Interrupt Routing Register 589" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7270++0x07 line.quad 0x00 "GICD_IROUTER590,Interrupt Routing Register 590" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7278++0x07 line.quad 0x00 "GICD_IROUTER591,Interrupt Routing Register 591" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7280++0x07 line.quad 0x00 "GICD_IROUTER592,Interrupt Routing Register 592" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7288++0x07 line.quad 0x00 "GICD_IROUTER593,Interrupt Routing Register 593" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7290++0x07 line.quad 0x00 "GICD_IROUTER594,Interrupt Routing Register 594" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7298++0x07 line.quad 0x00 "GICD_IROUTER595,Interrupt Routing Register 595" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72A0++0x07 line.quad 0x00 "GICD_IROUTER596,Interrupt Routing Register 596" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72A8++0x07 line.quad 0x00 "GICD_IROUTER597,Interrupt Routing Register 597" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72B0++0x07 line.quad 0x00 "GICD_IROUTER598,Interrupt Routing Register 598" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72B8++0x07 line.quad 0x00 "GICD_IROUTER599,Interrupt Routing Register 599" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72C0++0x07 line.quad 0x00 "GICD_IROUTER600,Interrupt Routing Register 600" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72C8++0x07 line.quad 0x00 "GICD_IROUTER601,Interrupt Routing Register 601" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72D0++0x07 line.quad 0x00 "GICD_IROUTER602,Interrupt Routing Register 602" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72D8++0x07 line.quad 0x00 "GICD_IROUTER603,Interrupt Routing Register 603" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72E0++0x07 line.quad 0x00 "GICD_IROUTER604,Interrupt Routing Register 604" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72E8++0x07 line.quad 0x00 "GICD_IROUTER605,Interrupt Routing Register 605" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72F0++0x07 line.quad 0x00 "GICD_IROUTER606,Interrupt Routing Register 606" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72F8++0x07 line.quad 0x00 "GICD_IROUTER607,Interrupt Routing Register 607" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7300++0x07 line.quad 0x00 "GICD_IROUTER608,Interrupt Routing Register 608" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7308++0x07 line.quad 0x00 "GICD_IROUTER609,Interrupt Routing Register 609" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7310++0x07 line.quad 0x00 "GICD_IROUTER610,Interrupt Routing Register 610" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7318++0x07 line.quad 0x00 "GICD_IROUTER611,Interrupt Routing Register 611" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7320++0x07 line.quad 0x00 "GICD_IROUTER612,Interrupt Routing Register 612" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7328++0x07 line.quad 0x00 "GICD_IROUTER613,Interrupt Routing Register 613" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7330++0x07 line.quad 0x00 "GICD_IROUTER614,Interrupt Routing Register 614" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7338++0x07 line.quad 0x00 "GICD_IROUTER615,Interrupt Routing Register 615" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7340++0x07 line.quad 0x00 "GICD_IROUTER616,Interrupt Routing Register 616" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7348++0x07 line.quad 0x00 "GICD_IROUTER617,Interrupt Routing Register 617" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7350++0x07 line.quad 0x00 "GICD_IROUTER618,Interrupt Routing Register 618" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7358++0x07 line.quad 0x00 "GICD_IROUTER619,Interrupt Routing Register 619" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7360++0x07 line.quad 0x00 "GICD_IROUTER620,Interrupt Routing Register 620" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7368++0x07 line.quad 0x00 "GICD_IROUTER621,Interrupt Routing Register 621" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7370++0x07 line.quad 0x00 "GICD_IROUTER622,Interrupt Routing Register 622" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7378++0x07 line.quad 0x00 "GICD_IROUTER623,Interrupt Routing Register 623" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7380++0x07 line.quad 0x00 "GICD_IROUTER624,Interrupt Routing Register 624" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7388++0x07 line.quad 0x00 "GICD_IROUTER625,Interrupt Routing Register 625" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7390++0x07 line.quad 0x00 "GICD_IROUTER626,Interrupt Routing Register 626" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7398++0x07 line.quad 0x00 "GICD_IROUTER627,Interrupt Routing Register 627" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73A0++0x07 line.quad 0x00 "GICD_IROUTER628,Interrupt Routing Register 628" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73A8++0x07 line.quad 0x00 "GICD_IROUTER629,Interrupt Routing Register 629" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73B0++0x07 line.quad 0x00 "GICD_IROUTER630,Interrupt Routing Register 630" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73B8++0x07 line.quad 0x00 "GICD_IROUTER631,Interrupt Routing Register 631" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73C0++0x07 line.quad 0x00 "GICD_IROUTER632,Interrupt Routing Register 632" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73C8++0x07 line.quad 0x00 "GICD_IROUTER633,Interrupt Routing Register 633" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73D0++0x07 line.quad 0x00 "GICD_IROUTER634,Interrupt Routing Register 634" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73D8++0x07 line.quad 0x00 "GICD_IROUTER635,Interrupt Routing Register 635" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73E0++0x07 line.quad 0x00 "GICD_IROUTER636,Interrupt Routing Register 636" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73E8++0x07 line.quad 0x00 "GICD_IROUTER637,Interrupt Routing Register 637" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73F0++0x07 line.quad 0x00 "GICD_IROUTER638,Interrupt Routing Register 638" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73F8++0x07 line.quad 0x00 "GICD_IROUTER639,Interrupt Routing Register 639" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7400++0x07 line.quad 0x00 "GICD_IROUTER640,Interrupt Routing Register 640" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7408++0x07 line.quad 0x00 "GICD_IROUTER641,Interrupt Routing Register 641" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7410++0x07 line.quad 0x00 "GICD_IROUTER642,Interrupt Routing Register 642" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7418++0x07 line.quad 0x00 "GICD_IROUTER643,Interrupt Routing Register 643" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7420++0x07 line.quad 0x00 "GICD_IROUTER644,Interrupt Routing Register 644" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7428++0x07 line.quad 0x00 "GICD_IROUTER645,Interrupt Routing Register 645" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7430++0x07 line.quad 0x00 "GICD_IROUTER646,Interrupt Routing Register 646" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7438++0x07 line.quad 0x00 "GICD_IROUTER647,Interrupt Routing Register 647" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7440++0x07 line.quad 0x00 "GICD_IROUTER648,Interrupt Routing Register 648" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7448++0x07 line.quad 0x00 "GICD_IROUTER649,Interrupt Routing Register 649" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7450++0x07 line.quad 0x00 "GICD_IROUTER650,Interrupt Routing Register 650" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7458++0x07 line.quad 0x00 "GICD_IROUTER651,Interrupt Routing Register 651" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7460++0x07 line.quad 0x00 "GICD_IROUTER652,Interrupt Routing Register 652" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7468++0x07 line.quad 0x00 "GICD_IROUTER653,Interrupt Routing Register 653" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7470++0x07 line.quad 0x00 "GICD_IROUTER654,Interrupt Routing Register 654" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7478++0x07 line.quad 0x00 "GICD_IROUTER655,Interrupt Routing Register 655" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7480++0x07 line.quad 0x00 "GICD_IROUTER656,Interrupt Routing Register 656" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7488++0x07 line.quad 0x00 "GICD_IROUTER657,Interrupt Routing Register 657" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7490++0x07 line.quad 0x00 "GICD_IROUTER658,Interrupt Routing Register 658" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7498++0x07 line.quad 0x00 "GICD_IROUTER659,Interrupt Routing Register 659" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74A0++0x07 line.quad 0x00 "GICD_IROUTER660,Interrupt Routing Register 660" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74A8++0x07 line.quad 0x00 "GICD_IROUTER661,Interrupt Routing Register 661" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74B0++0x07 line.quad 0x00 "GICD_IROUTER662,Interrupt Routing Register 662" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74B8++0x07 line.quad 0x00 "GICD_IROUTER663,Interrupt Routing Register 663" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74C0++0x07 line.quad 0x00 "GICD_IROUTER664,Interrupt Routing Register 664" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74C8++0x07 line.quad 0x00 "GICD_IROUTER665,Interrupt Routing Register 665" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74D0++0x07 line.quad 0x00 "GICD_IROUTER666,Interrupt Routing Register 666" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74D8++0x07 line.quad 0x00 "GICD_IROUTER667,Interrupt Routing Register 667" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74E0++0x07 line.quad 0x00 "GICD_IROUTER668,Interrupt Routing Register 668" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74E8++0x07 line.quad 0x00 "GICD_IROUTER669,Interrupt Routing Register 669" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74F0++0x07 line.quad 0x00 "GICD_IROUTER670,Interrupt Routing Register 670" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74F8++0x07 line.quad 0x00 "GICD_IROUTER671,Interrupt Routing Register 671" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7500++0x07 line.quad 0x00 "GICD_IROUTER672,Interrupt Routing Register 672" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7508++0x07 line.quad 0x00 "GICD_IROUTER673,Interrupt Routing Register 673" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7510++0x07 line.quad 0x00 "GICD_IROUTER674,Interrupt Routing Register 674" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7518++0x07 line.quad 0x00 "GICD_IROUTER675,Interrupt Routing Register 675" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7520++0x07 line.quad 0x00 "GICD_IROUTER676,Interrupt Routing Register 676" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7528++0x07 line.quad 0x00 "GICD_IROUTER677,Interrupt Routing Register 677" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7530++0x07 line.quad 0x00 "GICD_IROUTER678,Interrupt Routing Register 678" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7538++0x07 line.quad 0x00 "GICD_IROUTER679,Interrupt Routing Register 679" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7540++0x07 line.quad 0x00 "GICD_IROUTER680,Interrupt Routing Register 680" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7548++0x07 line.quad 0x00 "GICD_IROUTER681,Interrupt Routing Register 681" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7550++0x07 line.quad 0x00 "GICD_IROUTER682,Interrupt Routing Register 682" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7558++0x07 line.quad 0x00 "GICD_IROUTER683,Interrupt Routing Register 683" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7560++0x07 line.quad 0x00 "GICD_IROUTER684,Interrupt Routing Register 684" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7568++0x07 line.quad 0x00 "GICD_IROUTER685,Interrupt Routing Register 685" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7570++0x07 line.quad 0x00 "GICD_IROUTER686,Interrupt Routing Register 686" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7578++0x07 line.quad 0x00 "GICD_IROUTER687,Interrupt Routing Register 687" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7580++0x07 line.quad 0x00 "GICD_IROUTER688,Interrupt Routing Register 688" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7588++0x07 line.quad 0x00 "GICD_IROUTER689,Interrupt Routing Register 689" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7590++0x07 line.quad 0x00 "GICD_IROUTER690,Interrupt Routing Register 690" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7598++0x07 line.quad 0x00 "GICD_IROUTER691,Interrupt Routing Register 691" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75A0++0x07 line.quad 0x00 "GICD_IROUTER692,Interrupt Routing Register 692" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75A8++0x07 line.quad 0x00 "GICD_IROUTER693,Interrupt Routing Register 693" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75B0++0x07 line.quad 0x00 "GICD_IROUTER694,Interrupt Routing Register 694" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75B8++0x07 line.quad 0x00 "GICD_IROUTER695,Interrupt Routing Register 695" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75C0++0x07 line.quad 0x00 "GICD_IROUTER696,Interrupt Routing Register 696" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75C8++0x07 line.quad 0x00 "GICD_IROUTER697,Interrupt Routing Register 697" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75D0++0x07 line.quad 0x00 "GICD_IROUTER698,Interrupt Routing Register 698" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75D8++0x07 line.quad 0x00 "GICD_IROUTER699,Interrupt Routing Register 699" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75E0++0x07 line.quad 0x00 "GICD_IROUTER700,Interrupt Routing Register 700" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75E8++0x07 line.quad 0x00 "GICD_IROUTER701,Interrupt Routing Register 701" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75F0++0x07 line.quad 0x00 "GICD_IROUTER702,Interrupt Routing Register 702" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75F8++0x07 line.quad 0x00 "GICD_IROUTER703,Interrupt Routing Register 703" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7600++0x07 line.quad 0x00 "GICD_IROUTER704,Interrupt Routing Register 704" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7608++0x07 line.quad 0x00 "GICD_IROUTER705,Interrupt Routing Register 705" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7610++0x07 line.quad 0x00 "GICD_IROUTER706,Interrupt Routing Register 706" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7618++0x07 line.quad 0x00 "GICD_IROUTER707,Interrupt Routing Register 707" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7620++0x07 line.quad 0x00 "GICD_IROUTER708,Interrupt Routing Register 708" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7628++0x07 line.quad 0x00 "GICD_IROUTER709,Interrupt Routing Register 709" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7630++0x07 line.quad 0x00 "GICD_IROUTER710,Interrupt Routing Register 710" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7638++0x07 line.quad 0x00 "GICD_IROUTER711,Interrupt Routing Register 711" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7640++0x07 line.quad 0x00 "GICD_IROUTER712,Interrupt Routing Register 712" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7648++0x07 line.quad 0x00 "GICD_IROUTER713,Interrupt Routing Register 713" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7650++0x07 line.quad 0x00 "GICD_IROUTER714,Interrupt Routing Register 714" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7658++0x07 line.quad 0x00 "GICD_IROUTER715,Interrupt Routing Register 715" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7660++0x07 line.quad 0x00 "GICD_IROUTER716,Interrupt Routing Register 716" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7668++0x07 line.quad 0x00 "GICD_IROUTER717,Interrupt Routing Register 717" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7670++0x07 line.quad 0x00 "GICD_IROUTER718,Interrupt Routing Register 718" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7678++0x07 line.quad 0x00 "GICD_IROUTER719,Interrupt Routing Register 719" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7680++0x07 line.quad 0x00 "GICD_IROUTER720,Interrupt Routing Register 720" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7688++0x07 line.quad 0x00 "GICD_IROUTER721,Interrupt Routing Register 721" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7690++0x07 line.quad 0x00 "GICD_IROUTER722,Interrupt Routing Register 722" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7698++0x07 line.quad 0x00 "GICD_IROUTER723,Interrupt Routing Register 723" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76A0++0x07 line.quad 0x00 "GICD_IROUTER724,Interrupt Routing Register 724" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76A8++0x07 line.quad 0x00 "GICD_IROUTER725,Interrupt Routing Register 725" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76B0++0x07 line.quad 0x00 "GICD_IROUTER726,Interrupt Routing Register 726" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76B8++0x07 line.quad 0x00 "GICD_IROUTER727,Interrupt Routing Register 727" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76C0++0x07 line.quad 0x00 "GICD_IROUTER728,Interrupt Routing Register 728" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76C8++0x07 line.quad 0x00 "GICD_IROUTER729,Interrupt Routing Register 729" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76D0++0x07 line.quad 0x00 "GICD_IROUTER730,Interrupt Routing Register 730" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76D8++0x07 line.quad 0x00 "GICD_IROUTER731,Interrupt Routing Register 731" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76E0++0x07 line.quad 0x00 "GICD_IROUTER732,Interrupt Routing Register 732" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76E8++0x07 line.quad 0x00 "GICD_IROUTER733,Interrupt Routing Register 733" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76F0++0x07 line.quad 0x00 "GICD_IROUTER734,Interrupt Routing Register 734" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76F8++0x07 line.quad 0x00 "GICD_IROUTER735,Interrupt Routing Register 735" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7700++0x07 line.quad 0x00 "GICD_IROUTER736,Interrupt Routing Register 736" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7708++0x07 line.quad 0x00 "GICD_IROUTER737,Interrupt Routing Register 737" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7710++0x07 line.quad 0x00 "GICD_IROUTER738,Interrupt Routing Register 738" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7718++0x07 line.quad 0x00 "GICD_IROUTER739,Interrupt Routing Register 739" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7720++0x07 line.quad 0x00 "GICD_IROUTER740,Interrupt Routing Register 740" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7728++0x07 line.quad 0x00 "GICD_IROUTER741,Interrupt Routing Register 741" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7730++0x07 line.quad 0x00 "GICD_IROUTER742,Interrupt Routing Register 742" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7738++0x07 line.quad 0x00 "GICD_IROUTER743,Interrupt Routing Register 743" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7740++0x07 line.quad 0x00 "GICD_IROUTER744,Interrupt Routing Register 744" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7748++0x07 line.quad 0x00 "GICD_IROUTER745,Interrupt Routing Register 745" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7750++0x07 line.quad 0x00 "GICD_IROUTER746,Interrupt Routing Register 746" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7758++0x07 line.quad 0x00 "GICD_IROUTER747,Interrupt Routing Register 747" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7760++0x07 line.quad 0x00 "GICD_IROUTER748,Interrupt Routing Register 748" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7768++0x07 line.quad 0x00 "GICD_IROUTER749,Interrupt Routing Register 749" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7770++0x07 line.quad 0x00 "GICD_IROUTER750,Interrupt Routing Register 750" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7778++0x07 line.quad 0x00 "GICD_IROUTER751,Interrupt Routing Register 751" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7780++0x07 line.quad 0x00 "GICD_IROUTER752,Interrupt Routing Register 752" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7788++0x07 line.quad 0x00 "GICD_IROUTER753,Interrupt Routing Register 753" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7790++0x07 line.quad 0x00 "GICD_IROUTER754,Interrupt Routing Register 754" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7798++0x07 line.quad 0x00 "GICD_IROUTER755,Interrupt Routing Register 755" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77A0++0x07 line.quad 0x00 "GICD_IROUTER756,Interrupt Routing Register 756" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77A8++0x07 line.quad 0x00 "GICD_IROUTER757,Interrupt Routing Register 757" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77B0++0x07 line.quad 0x00 "GICD_IROUTER758,Interrupt Routing Register 758" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77B8++0x07 line.quad 0x00 "GICD_IROUTER759,Interrupt Routing Register 759" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77C0++0x07 line.quad 0x00 "GICD_IROUTER760,Interrupt Routing Register 760" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77C8++0x07 line.quad 0x00 "GICD_IROUTER761,Interrupt Routing Register 761" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77D0++0x07 line.quad 0x00 "GICD_IROUTER762,Interrupt Routing Register 762" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77D8++0x07 line.quad 0x00 "GICD_IROUTER763,Interrupt Routing Register 763" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77E0++0x07 line.quad 0x00 "GICD_IROUTER764,Interrupt Routing Register 764" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77E8++0x07 line.quad 0x00 "GICD_IROUTER765,Interrupt Routing Register 765" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77F0++0x07 line.quad 0x00 "GICD_IROUTER766,Interrupt Routing Register 766" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77F8++0x07 line.quad 0x00 "GICD_IROUTER767,Interrupt Routing Register 767" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7800++0x07 line.quad 0x00 "GICD_IROUTER768,Interrupt Routing Register 768" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7808++0x07 line.quad 0x00 "GICD_IROUTER769,Interrupt Routing Register 769" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7810++0x07 line.quad 0x00 "GICD_IROUTER770,Interrupt Routing Register 770" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7818++0x07 line.quad 0x00 "GICD_IROUTER771,Interrupt Routing Register 771" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7820++0x07 line.quad 0x00 "GICD_IROUTER772,Interrupt Routing Register 772" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7828++0x07 line.quad 0x00 "GICD_IROUTER773,Interrupt Routing Register 773" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7830++0x07 line.quad 0x00 "GICD_IROUTER774,Interrupt Routing Register 774" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7838++0x07 line.quad 0x00 "GICD_IROUTER775,Interrupt Routing Register 775" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7840++0x07 line.quad 0x00 "GICD_IROUTER776,Interrupt Routing Register 776" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7848++0x07 line.quad 0x00 "GICD_IROUTER777,Interrupt Routing Register 777" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7850++0x07 line.quad 0x00 "GICD_IROUTER778,Interrupt Routing Register 778" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7858++0x07 line.quad 0x00 "GICD_IROUTER779,Interrupt Routing Register 779" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7860++0x07 line.quad 0x00 "GICD_IROUTER780,Interrupt Routing Register 780" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7868++0x07 line.quad 0x00 "GICD_IROUTER781,Interrupt Routing Register 781" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7870++0x07 line.quad 0x00 "GICD_IROUTER782,Interrupt Routing Register 782" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7878++0x07 line.quad 0x00 "GICD_IROUTER783,Interrupt Routing Register 783" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7880++0x07 line.quad 0x00 "GICD_IROUTER784,Interrupt Routing Register 784" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7888++0x07 line.quad 0x00 "GICD_IROUTER785,Interrupt Routing Register 785" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7890++0x07 line.quad 0x00 "GICD_IROUTER786,Interrupt Routing Register 786" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7898++0x07 line.quad 0x00 "GICD_IROUTER787,Interrupt Routing Register 787" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78A0++0x07 line.quad 0x00 "GICD_IROUTER788,Interrupt Routing Register 788" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78A8++0x07 line.quad 0x00 "GICD_IROUTER789,Interrupt Routing Register 789" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78B0++0x07 line.quad 0x00 "GICD_IROUTER790,Interrupt Routing Register 790" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78B8++0x07 line.quad 0x00 "GICD_IROUTER791,Interrupt Routing Register 791" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78C0++0x07 line.quad 0x00 "GICD_IROUTER792,Interrupt Routing Register 792" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78C8++0x07 line.quad 0x00 "GICD_IROUTER793,Interrupt Routing Register 793" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78D0++0x07 line.quad 0x00 "GICD_IROUTER794,Interrupt Routing Register 794" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78D8++0x07 line.quad 0x00 "GICD_IROUTER795,Interrupt Routing Register 795" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78E0++0x07 line.quad 0x00 "GICD_IROUTER796,Interrupt Routing Register 796" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78E8++0x07 line.quad 0x00 "GICD_IROUTER797,Interrupt Routing Register 797" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78F0++0x07 line.quad 0x00 "GICD_IROUTER798,Interrupt Routing Register 798" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78F8++0x07 line.quad 0x00 "GICD_IROUTER799,Interrupt Routing Register 799" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7900++0x07 line.quad 0x00 "GICD_IROUTER800,Interrupt Routing Register 800" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7908++0x07 line.quad 0x00 "GICD_IROUTER801,Interrupt Routing Register 801" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7910++0x07 line.quad 0x00 "GICD_IROUTER802,Interrupt Routing Register 802" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7918++0x07 line.quad 0x00 "GICD_IROUTER803,Interrupt Routing Register 803" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7920++0x07 line.quad 0x00 "GICD_IROUTER804,Interrupt Routing Register 804" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7928++0x07 line.quad 0x00 "GICD_IROUTER805,Interrupt Routing Register 805" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7930++0x07 line.quad 0x00 "GICD_IROUTER806,Interrupt Routing Register 806" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7938++0x07 line.quad 0x00 "GICD_IROUTER807,Interrupt Routing Register 807" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7940++0x07 line.quad 0x00 "GICD_IROUTER808,Interrupt Routing Register 808" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7948++0x07 line.quad 0x00 "GICD_IROUTER809,Interrupt Routing Register 809" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7950++0x07 line.quad 0x00 "GICD_IROUTER810,Interrupt Routing Register 810" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7958++0x07 line.quad 0x00 "GICD_IROUTER811,Interrupt Routing Register 811" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7960++0x07 line.quad 0x00 "GICD_IROUTER812,Interrupt Routing Register 812" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7968++0x07 line.quad 0x00 "GICD_IROUTER813,Interrupt Routing Register 813" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7970++0x07 line.quad 0x00 "GICD_IROUTER814,Interrupt Routing Register 814" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7978++0x07 line.quad 0x00 "GICD_IROUTER815,Interrupt Routing Register 815" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7980++0x07 line.quad 0x00 "GICD_IROUTER816,Interrupt Routing Register 816" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7988++0x07 line.quad 0x00 "GICD_IROUTER817,Interrupt Routing Register 817" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7990++0x07 line.quad 0x00 "GICD_IROUTER818,Interrupt Routing Register 818" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7998++0x07 line.quad 0x00 "GICD_IROUTER819,Interrupt Routing Register 819" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79A0++0x07 line.quad 0x00 "GICD_IROUTER820,Interrupt Routing Register 820" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79A8++0x07 line.quad 0x00 "GICD_IROUTER821,Interrupt Routing Register 821" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79B0++0x07 line.quad 0x00 "GICD_IROUTER822,Interrupt Routing Register 822" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79B8++0x07 line.quad 0x00 "GICD_IROUTER823,Interrupt Routing Register 823" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79C0++0x07 line.quad 0x00 "GICD_IROUTER824,Interrupt Routing Register 824" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79C8++0x07 line.quad 0x00 "GICD_IROUTER825,Interrupt Routing Register 825" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79D0++0x07 line.quad 0x00 "GICD_IROUTER826,Interrupt Routing Register 826" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79D8++0x07 line.quad 0x00 "GICD_IROUTER827,Interrupt Routing Register 827" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79E0++0x07 line.quad 0x00 "GICD_IROUTER828,Interrupt Routing Register 828" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79E8++0x07 line.quad 0x00 "GICD_IROUTER829,Interrupt Routing Register 829" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79F0++0x07 line.quad 0x00 "GICD_IROUTER830,Interrupt Routing Register 830" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79F8++0x07 line.quad 0x00 "GICD_IROUTER831,Interrupt Routing Register 831" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A00++0x07 line.quad 0x00 "GICD_IROUTER832,Interrupt Routing Register 832" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A08++0x07 line.quad 0x00 "GICD_IROUTER833,Interrupt Routing Register 833" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A10++0x07 line.quad 0x00 "GICD_IROUTER834,Interrupt Routing Register 834" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A18++0x07 line.quad 0x00 "GICD_IROUTER835,Interrupt Routing Register 835" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A20++0x07 line.quad 0x00 "GICD_IROUTER836,Interrupt Routing Register 836" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A28++0x07 line.quad 0x00 "GICD_IROUTER837,Interrupt Routing Register 837" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A30++0x07 line.quad 0x00 "GICD_IROUTER838,Interrupt Routing Register 838" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A38++0x07 line.quad 0x00 "GICD_IROUTER839,Interrupt Routing Register 839" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A40++0x07 line.quad 0x00 "GICD_IROUTER840,Interrupt Routing Register 840" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A48++0x07 line.quad 0x00 "GICD_IROUTER841,Interrupt Routing Register 841" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A50++0x07 line.quad 0x00 "GICD_IROUTER842,Interrupt Routing Register 842" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A58++0x07 line.quad 0x00 "GICD_IROUTER843,Interrupt Routing Register 843" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A60++0x07 line.quad 0x00 "GICD_IROUTER844,Interrupt Routing Register 844" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A68++0x07 line.quad 0x00 "GICD_IROUTER845,Interrupt Routing Register 845" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A70++0x07 line.quad 0x00 "GICD_IROUTER846,Interrupt Routing Register 846" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A78++0x07 line.quad 0x00 "GICD_IROUTER847,Interrupt Routing Register 847" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A80++0x07 line.quad 0x00 "GICD_IROUTER848,Interrupt Routing Register 848" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A88++0x07 line.quad 0x00 "GICD_IROUTER849,Interrupt Routing Register 849" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A90++0x07 line.quad 0x00 "GICD_IROUTER850,Interrupt Routing Register 850" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A98++0x07 line.quad 0x00 "GICD_IROUTER851,Interrupt Routing Register 851" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AA0++0x07 line.quad 0x00 "GICD_IROUTER852,Interrupt Routing Register 852" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AA8++0x07 line.quad 0x00 "GICD_IROUTER853,Interrupt Routing Register 853" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AB0++0x07 line.quad 0x00 "GICD_IROUTER854,Interrupt Routing Register 854" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AB8++0x07 line.quad 0x00 "GICD_IROUTER855,Interrupt Routing Register 855" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AC0++0x07 line.quad 0x00 "GICD_IROUTER856,Interrupt Routing Register 856" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AC8++0x07 line.quad 0x00 "GICD_IROUTER857,Interrupt Routing Register 857" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AD0++0x07 line.quad 0x00 "GICD_IROUTER858,Interrupt Routing Register 858" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AD8++0x07 line.quad 0x00 "GICD_IROUTER859,Interrupt Routing Register 859" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AE0++0x07 line.quad 0x00 "GICD_IROUTER860,Interrupt Routing Register 860" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AE8++0x07 line.quad 0x00 "GICD_IROUTER861,Interrupt Routing Register 861" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AF0++0x07 line.quad 0x00 "GICD_IROUTER862,Interrupt Routing Register 862" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AF8++0x07 line.quad 0x00 "GICD_IROUTER863,Interrupt Routing Register 863" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B00++0x07 line.quad 0x00 "GICD_IROUTER864,Interrupt Routing Register 864" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B08++0x07 line.quad 0x00 "GICD_IROUTER865,Interrupt Routing Register 865" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B10++0x07 line.quad 0x00 "GICD_IROUTER866,Interrupt Routing Register 866" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B18++0x07 line.quad 0x00 "GICD_IROUTER867,Interrupt Routing Register 867" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B20++0x07 line.quad 0x00 "GICD_IROUTER868,Interrupt Routing Register 868" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B28++0x07 line.quad 0x00 "GICD_IROUTER869,Interrupt Routing Register 869" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B30++0x07 line.quad 0x00 "GICD_IROUTER870,Interrupt Routing Register 870" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B38++0x07 line.quad 0x00 "GICD_IROUTER871,Interrupt Routing Register 871" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B40++0x07 line.quad 0x00 "GICD_IROUTER872,Interrupt Routing Register 872" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B48++0x07 line.quad 0x00 "GICD_IROUTER873,Interrupt Routing Register 873" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B50++0x07 line.quad 0x00 "GICD_IROUTER874,Interrupt Routing Register 874" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B58++0x07 line.quad 0x00 "GICD_IROUTER875,Interrupt Routing Register 875" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B60++0x07 line.quad 0x00 "GICD_IROUTER876,Interrupt Routing Register 876" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B68++0x07 line.quad 0x00 "GICD_IROUTER877,Interrupt Routing Register 877" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B70++0x07 line.quad 0x00 "GICD_IROUTER878,Interrupt Routing Register 878" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B78++0x07 line.quad 0x00 "GICD_IROUTER879,Interrupt Routing Register 879" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B80++0x07 line.quad 0x00 "GICD_IROUTER880,Interrupt Routing Register 880" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B88++0x07 line.quad 0x00 "GICD_IROUTER881,Interrupt Routing Register 881" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B90++0x07 line.quad 0x00 "GICD_IROUTER882,Interrupt Routing Register 882" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B98++0x07 line.quad 0x00 "GICD_IROUTER883,Interrupt Routing Register 883" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BA0++0x07 line.quad 0x00 "GICD_IROUTER884,Interrupt Routing Register 884" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BA8++0x07 line.quad 0x00 "GICD_IROUTER885,Interrupt Routing Register 885" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BB0++0x07 line.quad 0x00 "GICD_IROUTER886,Interrupt Routing Register 886" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BB8++0x07 line.quad 0x00 "GICD_IROUTER887,Interrupt Routing Register 887" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BC0++0x07 line.quad 0x00 "GICD_IROUTER888,Interrupt Routing Register 888" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BC8++0x07 line.quad 0x00 "GICD_IROUTER889,Interrupt Routing Register 889" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BD0++0x07 line.quad 0x00 "GICD_IROUTER890,Interrupt Routing Register 890" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BD8++0x07 line.quad 0x00 "GICD_IROUTER891,Interrupt Routing Register 891" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BE0++0x07 line.quad 0x00 "GICD_IROUTER892,Interrupt Routing Register 892" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BE8++0x07 line.quad 0x00 "GICD_IROUTER893,Interrupt Routing Register 893" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BF0++0x07 line.quad 0x00 "GICD_IROUTER894,Interrupt Routing Register 894" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BF8++0x07 line.quad 0x00 "GICD_IROUTER895,Interrupt Routing Register 895" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C00++0x07 line.quad 0x00 "GICD_IROUTER896,Interrupt Routing Register 896" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C08++0x07 line.quad 0x00 "GICD_IROUTER897,Interrupt Routing Register 897" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C10++0x07 line.quad 0x00 "GICD_IROUTER898,Interrupt Routing Register 898" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C18++0x07 line.quad 0x00 "GICD_IROUTER899,Interrupt Routing Register 899" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C20++0x07 line.quad 0x00 "GICD_IROUTER900,Interrupt Routing Register 900" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C28++0x07 line.quad 0x00 "GICD_IROUTER901,Interrupt Routing Register 901" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C30++0x07 line.quad 0x00 "GICD_IROUTER902,Interrupt Routing Register 902" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C38++0x07 line.quad 0x00 "GICD_IROUTER903,Interrupt Routing Register 903" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C40++0x07 line.quad 0x00 "GICD_IROUTER904,Interrupt Routing Register 904" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C48++0x07 line.quad 0x00 "GICD_IROUTER905,Interrupt Routing Register 905" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C50++0x07 line.quad 0x00 "GICD_IROUTER906,Interrupt Routing Register 906" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C58++0x07 line.quad 0x00 "GICD_IROUTER907,Interrupt Routing Register 907" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C60++0x07 line.quad 0x00 "GICD_IROUTER908,Interrupt Routing Register 908" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C68++0x07 line.quad 0x00 "GICD_IROUTER909,Interrupt Routing Register 909" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C70++0x07 line.quad 0x00 "GICD_IROUTER910,Interrupt Routing Register 910" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C78++0x07 line.quad 0x00 "GICD_IROUTER911,Interrupt Routing Register 911" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C80++0x07 line.quad 0x00 "GICD_IROUTER912,Interrupt Routing Register 912" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C88++0x07 line.quad 0x00 "GICD_IROUTER913,Interrupt Routing Register 913" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C90++0x07 line.quad 0x00 "GICD_IROUTER914,Interrupt Routing Register 914" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C98++0x07 line.quad 0x00 "GICD_IROUTER915,Interrupt Routing Register 915" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CA0++0x07 line.quad 0x00 "GICD_IROUTER916,Interrupt Routing Register 916" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CA8++0x07 line.quad 0x00 "GICD_IROUTER917,Interrupt Routing Register 917" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CB0++0x07 line.quad 0x00 "GICD_IROUTER918,Interrupt Routing Register 918" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CB8++0x07 line.quad 0x00 "GICD_IROUTER919,Interrupt Routing Register 919" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CC0++0x07 line.quad 0x00 "GICD_IROUTER920,Interrupt Routing Register 920" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CC8++0x07 line.quad 0x00 "GICD_IROUTER921,Interrupt Routing Register 921" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CD0++0x07 line.quad 0x00 "GICD_IROUTER922,Interrupt Routing Register 922" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CD8++0x07 line.quad 0x00 "GICD_IROUTER923,Interrupt Routing Register 923" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CE0++0x07 line.quad 0x00 "GICD_IROUTER924,Interrupt Routing Register 924" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CE8++0x07 line.quad 0x00 "GICD_IROUTER925,Interrupt Routing Register 925" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CF0++0x07 line.quad 0x00 "GICD_IROUTER926,Interrupt Routing Register 926" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CF8++0x07 line.quad 0x00 "GICD_IROUTER927,Interrupt Routing Register 927" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D00++0x07 line.quad 0x00 "GICD_IROUTER928,Interrupt Routing Register 928" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D08++0x07 line.quad 0x00 "GICD_IROUTER929,Interrupt Routing Register 929" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D10++0x07 line.quad 0x00 "GICD_IROUTER930,Interrupt Routing Register 930" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D18++0x07 line.quad 0x00 "GICD_IROUTER931,Interrupt Routing Register 931" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D20++0x07 line.quad 0x00 "GICD_IROUTER932,Interrupt Routing Register 932" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D28++0x07 line.quad 0x00 "GICD_IROUTER933,Interrupt Routing Register 933" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D30++0x07 line.quad 0x00 "GICD_IROUTER934,Interrupt Routing Register 934" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D38++0x07 line.quad 0x00 "GICD_IROUTER935,Interrupt Routing Register 935" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D40++0x07 line.quad 0x00 "GICD_IROUTER936,Interrupt Routing Register 936" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D48++0x07 line.quad 0x00 "GICD_IROUTER937,Interrupt Routing Register 937" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D50++0x07 line.quad 0x00 "GICD_IROUTER938,Interrupt Routing Register 938" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D58++0x07 line.quad 0x00 "GICD_IROUTER939,Interrupt Routing Register 939" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D60++0x07 line.quad 0x00 "GICD_IROUTER940,Interrupt Routing Register 940" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D68++0x07 line.quad 0x00 "GICD_IROUTER941,Interrupt Routing Register 941" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D70++0x07 line.quad 0x00 "GICD_IROUTER942,Interrupt Routing Register 942" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D78++0x07 line.quad 0x00 "GICD_IROUTER943,Interrupt Routing Register 943" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D80++0x07 line.quad 0x00 "GICD_IROUTER944,Interrupt Routing Register 944" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D88++0x07 line.quad 0x00 "GICD_IROUTER945,Interrupt Routing Register 945" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D90++0x07 line.quad 0x00 "GICD_IROUTER946,Interrupt Routing Register 946" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D98++0x07 line.quad 0x00 "GICD_IROUTER947,Interrupt Routing Register 947" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DA0++0x07 line.quad 0x00 "GICD_IROUTER948,Interrupt Routing Register 948" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DA8++0x07 line.quad 0x00 "GICD_IROUTER949,Interrupt Routing Register 949" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DB0++0x07 line.quad 0x00 "GICD_IROUTER950,Interrupt Routing Register 950" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DB8++0x07 line.quad 0x00 "GICD_IROUTER951,Interrupt Routing Register 951" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DC0++0x07 line.quad 0x00 "GICD_IROUTER952,Interrupt Routing Register 952" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DC8++0x07 line.quad 0x00 "GICD_IROUTER953,Interrupt Routing Register 953" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DD0++0x07 line.quad 0x00 "GICD_IROUTER954,Interrupt Routing Register 954" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DD8++0x07 line.quad 0x00 "GICD_IROUTER955,Interrupt Routing Register 955" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DE0++0x07 line.quad 0x00 "GICD_IROUTER956,Interrupt Routing Register 956" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DE8++0x07 line.quad 0x00 "GICD_IROUTER957,Interrupt Routing Register 957" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DF0++0x07 line.quad 0x00 "GICD_IROUTER958,Interrupt Routing Register 958" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DF8++0x07 line.quad 0x00 "GICD_IROUTER959,Interrupt Routing Register 959" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E00++0x07 line.quad 0x00 "GICD_IROUTER960,Interrupt Routing Register 960" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E08++0x07 line.quad 0x00 "GICD_IROUTER961,Interrupt Routing Register 961" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E10++0x07 line.quad 0x00 "GICD_IROUTER962,Interrupt Routing Register 962" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E18++0x07 line.quad 0x00 "GICD_IROUTER963,Interrupt Routing Register 963" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E20++0x07 line.quad 0x00 "GICD_IROUTER964,Interrupt Routing Register 964" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E28++0x07 line.quad 0x00 "GICD_IROUTER965,Interrupt Routing Register 965" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E30++0x07 line.quad 0x00 "GICD_IROUTER966,Interrupt Routing Register 966" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E38++0x07 line.quad 0x00 "GICD_IROUTER967,Interrupt Routing Register 967" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E40++0x07 line.quad 0x00 "GICD_IROUTER968,Interrupt Routing Register 968" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E48++0x07 line.quad 0x00 "GICD_IROUTER969,Interrupt Routing Register 969" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E50++0x07 line.quad 0x00 "GICD_IROUTER970,Interrupt Routing Register 970" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E58++0x07 line.quad 0x00 "GICD_IROUTER971,Interrupt Routing Register 971" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E60++0x07 line.quad 0x00 "GICD_IROUTER972,Interrupt Routing Register 972" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E68++0x07 line.quad 0x00 "GICD_IROUTER973,Interrupt Routing Register 973" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E70++0x07 line.quad 0x00 "GICD_IROUTER974,Interrupt Routing Register 974" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E78++0x07 line.quad 0x00 "GICD_IROUTER975,Interrupt Routing Register 975" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E80++0x07 line.quad 0x00 "GICD_IROUTER976,Interrupt Routing Register 976" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E88++0x07 line.quad 0x00 "GICD_IROUTER977,Interrupt Routing Register 977" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E90++0x07 line.quad 0x00 "GICD_IROUTER978,Interrupt Routing Register 978" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E98++0x07 line.quad 0x00 "GICD_IROUTER979,Interrupt Routing Register 979" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EA0++0x07 line.quad 0x00 "GICD_IROUTER980,Interrupt Routing Register 980" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EA8++0x07 line.quad 0x00 "GICD_IROUTER981,Interrupt Routing Register 981" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EB0++0x07 line.quad 0x00 "GICD_IROUTER982,Interrupt Routing Register 982" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EB8++0x07 line.quad 0x00 "GICD_IROUTER983,Interrupt Routing Register 983" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EC0++0x07 line.quad 0x00 "GICD_IROUTER984,Interrupt Routing Register 984" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EC8++0x07 line.quad 0x00 "GICD_IROUTER985,Interrupt Routing Register 985" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7ED0++0x07 line.quad 0x00 "GICD_IROUTER986,Interrupt Routing Register 986" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7ED8++0x07 line.quad 0x00 "GICD_IROUTER987,Interrupt Routing Register 987" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EE0++0x07 line.quad 0x00 "GICD_IROUTER988,Interrupt Routing Register 988" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EE8++0x07 line.quad 0x00 "GICD_IROUTER989,Interrupt Routing Register 989" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EF0++0x07 line.quad 0x00 "GICD_IROUTER990,Interrupt Routing Register 990" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EF8++0x07 line.quad 0x00 "GICD_IROUTER991,Interrupt Routing Register 991" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" tree.end width 22. tree "Implementation Defined Test Registers" rgroup.long 0xC000++0x03 line.long 0x00 "GICD_ESTATUSR,GICD_ESTATUSR" bitfld.long 0x00 31. " SRWP ,Super Register Write Pending" "Not pending,Pending" wgroup.long 0xC004++0x03 line.long 0x00 "GICD_ERRTESTR,Error Test Register" bitfld.long 0x00 1. " AXIM_ERR ,Drives the axim_err pin to 0b1 for 1 cycle" "Low,High" bitfld.long 0x00 0. " ECC_FATAL ,Drives the ecc_fatal pin to 0b1 for 1 cycle" "Low,High" textline " " if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) rgroup.long 0xC084++0x03 line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0" bitfld.long 0x00 31. " SPIS63 ,SPI Status Bit 63" "Low,High" bitfld.long 0x00 30. " SPIS62 ,SPI Status Bit 62" "Low,High" bitfld.long 0x00 29. " SPIS61 ,SPI Status Bit 61" "Low,High" textline " " bitfld.long 0x00 28. " SPIS60 ,SPI Status Bit 60" "Low,High" bitfld.long 0x00 27. " SPIS59 ,SPI Status Bit 59" "Low,High" bitfld.long 0x00 26. " SPIS58 ,SPI Status Bit 58" "Low,High" textline " " bitfld.long 0x00 25. " SPIS57 ,SPI Status Bit 57" "Low,High" bitfld.long 0x00 24. " SPIS56 ,SPI Status Bit 56" "Low,High" bitfld.long 0x00 23. " SPIS55 ,SPI Status Bit 55" "Low,High" textline " " bitfld.long 0x00 22. " SPIS54 ,SPI Status Bit 54" "Low,High" bitfld.long 0x00 21. " SPIS53 ,SPI Status Bit 53" "Low,High" bitfld.long 0x00 20. " SPIS52 ,SPI Status Bit 52" "Low,High" textline " " bitfld.long 0x00 19. " SPIS51 ,SPI Status Bit 51" "Low,High" bitfld.long 0x00 18. " SPIS50 ,SPI Status Bit 50" "Low,High" bitfld.long 0x00 17. " SPIS49 ,SPI Status Bit 49" "Low,High" textline " " bitfld.long 0x00 16. " SPIS48 ,SPI Status Bit 48" "Low,High" bitfld.long 0x00 15. " SPIS47 ,SPI Status Bit 47" "Low,High" bitfld.long 0x00 14. " SPIS46 ,SPI Status Bit 46" "Low,High" textline " " bitfld.long 0x00 13. " SPIS45 ,SPI Status Bit 45" "Low,High" bitfld.long 0x00 12. " SPIS44 ,SPI Status Bit 44" "Low,High" bitfld.long 0x00 11. " SPIS43 ,SPI Status Bit 43" "Low,High" textline " " bitfld.long 0x00 10. " SPIS42 ,SPI Status Bit 42" "Low,High" bitfld.long 0x00 9. " SPIS41 ,SPI Status Bit 41" "Low,High" bitfld.long 0x00 8. " SPIS40 ,SPI Status Bit 40" "Low,High" textline " " bitfld.long 0x00 7. " SPIS39 ,SPI Status Bit 39" "Low,High" bitfld.long 0x00 6. " SPIS38 ,SPI Status Bit 38" "Low,High" bitfld.long 0x00 5. " SPIS37 ,SPI Status Bit 37" "Low,High" textline " " bitfld.long 0x00 4. " SPIS36 ,SPI Status Bit 36" "Low,High" bitfld.long 0x00 3. " SPIS35 ,SPI Status Bit 35" "Low,High" bitfld.long 0x00 2. " SPIS34 ,SPI Status Bit 34" "Low,High" textline " " bitfld.long 0x00 1. " SPIS33 ,SPI Status Bit 33" "Low,High" bitfld.long 0x00 0. " SPIS32 ,SPI Status Bit 32" "Low,High" else hgroup.long 0xC084++0x03 hide.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) rgroup.long 0xC088++0x03 line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" bitfld.long 0x00 31. " SPIS95 ,SPI Status Bit 95" "Low,High" bitfld.long 0x00 30. " SPIS94 ,SPI Status Bit 94" "Low,High" bitfld.long 0x00 29. " SPIS93 ,SPI Status Bit 93" "Low,High" textline " " bitfld.long 0x00 28. " SPIS92 ,SPI Status Bit 92" "Low,High" bitfld.long 0x00 27. " SPIS91 ,SPI Status Bit 91" "Low,High" bitfld.long 0x00 26. " SPIS90 ,SPI Status Bit 90" "Low,High" textline " " bitfld.long 0x00 25. " SPIS89 ,SPI Status Bit 89" "Low,High" bitfld.long 0x00 24. " SPIS88 ,SPI Status Bit 88" "Low,High" bitfld.long 0x00 23. " SPIS87 ,SPI Status Bit 87" "Low,High" textline " " bitfld.long 0x00 22. " SPIS86 ,SPI Status Bit 86" "Low,High" bitfld.long 0x00 21. " SPIS85 ,SPI Status Bit 85" "Low,High" bitfld.long 0x00 20. " SPIS84 ,SPI Status Bit 84" "Low,High" textline " " bitfld.long 0x00 19. " SPIS83 ,SPI Status Bit 83" "Low,High" bitfld.long 0x00 18. " SPIS82 ,SPI Status Bit 82" "Low,High" bitfld.long 0x00 17. " SPIS81 ,SPI Status Bit 81" "Low,High" textline " " bitfld.long 0x00 16. " SPIS80 ,SPI Status Bit 80" "Low,High" bitfld.long 0x00 15. " SPIS79 ,SPI Status Bit 79" "Low,High" bitfld.long 0x00 14. " SPIS78 ,SPI Status Bit 78" "Low,High" textline " " bitfld.long 0x00 13. " SPIS77 ,SPI Status Bit 77" "Low,High" bitfld.long 0x00 12. " SPIS76 ,SPI Status Bit 76" "Low,High" bitfld.long 0x00 11. " SPIS75 ,SPI Status Bit 75" "Low,High" textline " " bitfld.long 0x00 10. " SPIS74 ,SPI Status Bit 74" "Low,High" bitfld.long 0x00 9. " SPIS73 ,SPI Status Bit 73" "Low,High" bitfld.long 0x00 8. " SPIS72 ,SPI Status Bit 72" "Low,High" textline " " bitfld.long 0x00 7. " SPIS71 ,SPI Status Bit 71" "Low,High" bitfld.long 0x00 6. " SPIS70 ,SPI Status Bit 70" "Low,High" bitfld.long 0x00 5. " SPIS69 ,SPI Status Bit 69" "Low,High" textline " " bitfld.long 0x00 4. " SPIS68 ,SPI Status Bit 68" "Low,High" bitfld.long 0x00 3. " SPIS67 ,SPI Status Bit 67" "Low,High" bitfld.long 0x00 2. " SPIS66 ,SPI Status Bit 66" "Low,High" textline " " bitfld.long 0x00 1. " SPIS65 ,SPI Status Bit 65" "Low,High" bitfld.long 0x00 0. " SPIS64 ,SPI Status Bit 64" "Low,High" else hgroup.long 0xC088++0x03 hide.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) rgroup.long 0xC08C++0x03 line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" bitfld.long 0x00 31. " SPIS127 ,SPI Status Bit 127" "Low,High" bitfld.long 0x00 30. " SPIS126 ,SPI Status Bit 126" "Low,High" bitfld.long 0x00 29. " SPIS125 ,SPI Status Bit 125" "Low,High" textline " " bitfld.long 0x00 28. " SPIS124 ,SPI Status Bit 124" "Low,High" bitfld.long 0x00 27. " SPIS123 ,SPI Status Bit 123" "Low,High" bitfld.long 0x00 26. " SPIS122 ,SPI Status Bit 122" "Low,High" textline " " bitfld.long 0x00 25. " SPIS121 ,SPI Status Bit 121" "Low,High" bitfld.long 0x00 24. " SPIS120 ,SPI Status Bit 120" "Low,High" bitfld.long 0x00 23. " SPIS119 ,SPI Status Bit 119" "Low,High" textline " " bitfld.long 0x00 22. " SPIS118 ,SPI Status Bit 118" "Low,High" bitfld.long 0x00 21. " SPIS117 ,SPI Status Bit 117" "Low,High" bitfld.long 0x00 20. " SPIS116 ,SPI Status Bit 116" "Low,High" textline " " bitfld.long 0x00 19. " SPIS115 ,SPI Status Bit 115" "Low,High" bitfld.long 0x00 18. " SPIS114 ,SPI Status Bit 114" "Low,High" bitfld.long 0x00 17. " SPIS113 ,SPI Status Bit 113" "Low,High" textline " " bitfld.long 0x00 16. " SPIS112 ,SPI Status Bit 112" "Low,High" bitfld.long 0x00 15. " SPIS111 ,SPI Status Bit 111" "Low,High" bitfld.long 0x00 14. " SPIS110 ,SPI Status Bit 110" "Low,High" textline " " bitfld.long 0x00 13. " SPIS109 ,SPI Status Bit 109" "Low,High" bitfld.long 0x00 12. " SPIS108 ,SPI Status Bit 108" "Low,High" bitfld.long 0x00 11. " SPIS107 ,SPI Status Bit 107" "Low,High" textline " " bitfld.long 0x00 10. " SPIS106 ,SPI Status Bit 106" "Low,High" bitfld.long 0x00 9. " SPIS105 ,SPI Status Bit 105" "Low,High" bitfld.long 0x00 8. " SPIS104 ,SPI Status Bit 104" "Low,High" textline " " bitfld.long 0x00 7. " SPIS103 ,SPI Status Bit 103" "Low,High" bitfld.long 0x00 6. " SPIS102 ,SPI Status Bit 102" "Low,High" bitfld.long 0x00 5. " SPIS101 ,SPI Status Bit 101" "Low,High" textline " " bitfld.long 0x00 4. " SPIS100 ,SPI Status Bit 100" "Low,High" bitfld.long 0x00 3. " SPIS99 ,SPI Status Bit 99" "Low,High" bitfld.long 0x00 2. " SPIS98 ,SPI Status Bit 98" "Low,High" textline " " bitfld.long 0x00 1. " SPIS97 ,SPI Status Bit 97" "Low,High" bitfld.long 0x00 0. " SPIS96 ,SPI Status Bit 96" "Low,High" else hgroup.long 0xC08C++0x03 hide.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) rgroup.long 0xC090++0x03 line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" bitfld.long 0x00 31. " SPIS159 ,SPI Status Bit 159" "Low,High" bitfld.long 0x00 30. " SPIS158 ,SPI Status Bit 158" "Low,High" bitfld.long 0x00 29. " SPIS157 ,SPI Status Bit 157" "Low,High" textline " " bitfld.long 0x00 28. " SPIS156 ,SPI Status Bit 156" "Low,High" bitfld.long 0x00 27. " SPIS155 ,SPI Status Bit 155" "Low,High" bitfld.long 0x00 26. " SPIS154 ,SPI Status Bit 154" "Low,High" textline " " bitfld.long 0x00 25. " SPIS153 ,SPI Status Bit 153" "Low,High" bitfld.long 0x00 24. " SPIS152 ,SPI Status Bit 152" "Low,High" bitfld.long 0x00 23. " SPIS151 ,SPI Status Bit 151" "Low,High" textline " " bitfld.long 0x00 22. " SPIS150 ,SPI Status Bit 150" "Low,High" bitfld.long 0x00 21. " SPIS149 ,SPI Status Bit 149" "Low,High" bitfld.long 0x00 20. " SPIS148 ,SPI Status Bit 148" "Low,High" textline " " bitfld.long 0x00 19. " SPIS147 ,SPI Status Bit 147" "Low,High" bitfld.long 0x00 18. " SPIS146 ,SPI Status Bit 146" "Low,High" bitfld.long 0x00 17. " SPIS145 ,SPI Status Bit 145" "Low,High" textline " " bitfld.long 0x00 16. " SPIS144 ,SPI Status Bit 144" "Low,High" bitfld.long 0x00 15. " SPIS143 ,SPI Status Bit 143" "Low,High" bitfld.long 0x00 14. " SPIS142 ,SPI Status Bit 142" "Low,High" textline " " bitfld.long 0x00 13. " SPIS141 ,SPI Status Bit 141" "Low,High" bitfld.long 0x00 12. " SPIS140 ,SPI Status Bit 140" "Low,High" bitfld.long 0x00 11. " SPIS139 ,SPI Status Bit 139" "Low,High" textline " " bitfld.long 0x00 10. " SPIS138 ,SPI Status Bit 138" "Low,High" bitfld.long 0x00 9. " SPIS137 ,SPI Status Bit 137" "Low,High" bitfld.long 0x00 8. " SPIS136 ,SPI Status Bit 136" "Low,High" textline " " bitfld.long 0x00 7. " SPIS135 ,SPI Status Bit 135" "Low,High" bitfld.long 0x00 6. " SPIS134 ,SPI Status Bit 134" "Low,High" bitfld.long 0x00 5. " SPIS133 ,SPI Status Bit 133" "Low,High" textline " " bitfld.long 0x00 4. " SPIS132 ,SPI Status Bit 132" "Low,High" bitfld.long 0x00 3. " SPIS131 ,SPI Status Bit 131" "Low,High" bitfld.long 0x00 2. " SPIS130 ,SPI Status Bit 130" "Low,High" textline " " bitfld.long 0x00 1. " SPIS129 ,SPI Status Bit 129" "Low,High" bitfld.long 0x00 0. " SPIS128 ,SPI Status Bit 128" "Low,High" else hgroup.long 0xC090++0x03 hide.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) rgroup.long 0xC094++0x03 line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" bitfld.long 0x00 31. " SPIS191 ,SPI Status Bit 191" "Low,High" bitfld.long 0x00 30. " SPIS190 ,SPI Status Bit 190" "Low,High" bitfld.long 0x00 29. " SPIS189 ,SPI Status Bit 189" "Low,High" textline " " bitfld.long 0x00 28. " SPIS188 ,SPI Status Bit 188" "Low,High" bitfld.long 0x00 27. " SPIS187 ,SPI Status Bit 187" "Low,High" bitfld.long 0x00 26. " SPIS186 ,SPI Status Bit 186" "Low,High" textline " " bitfld.long 0x00 25. " SPIS185 ,SPI Status Bit 185" "Low,High" bitfld.long 0x00 24. " SPIS184 ,SPI Status Bit 184" "Low,High" bitfld.long 0x00 23. " SPIS183 ,SPI Status Bit 183" "Low,High" textline " " bitfld.long 0x00 22. " SPIS182 ,SPI Status Bit 182" "Low,High" bitfld.long 0x00 21. " SPIS181 ,SPI Status Bit 181" "Low,High" bitfld.long 0x00 20. " SPIS180 ,SPI Status Bit 180" "Low,High" textline " " bitfld.long 0x00 19. " SPIS179 ,SPI Status Bit 179" "Low,High" bitfld.long 0x00 18. " SPIS178 ,SPI Status Bit 178" "Low,High" bitfld.long 0x00 17. " SPIS177 ,SPI Status Bit 177" "Low,High" textline " " bitfld.long 0x00 16. " SPIS176 ,SPI Status Bit 176" "Low,High" bitfld.long 0x00 15. " SPIS175 ,SPI Status Bit 175" "Low,High" bitfld.long 0x00 14. " SPIS174 ,SPI Status Bit 174" "Low,High" textline " " bitfld.long 0x00 13. " SPIS173 ,SPI Status Bit 173" "Low,High" bitfld.long 0x00 12. " SPIS172 ,SPI Status Bit 172" "Low,High" bitfld.long 0x00 11. " SPIS171 ,SPI Status Bit 171" "Low,High" textline " " bitfld.long 0x00 10. " SPIS170 ,SPI Status Bit 170" "Low,High" bitfld.long 0x00 9. " SPIS169 ,SPI Status Bit 169" "Low,High" bitfld.long 0x00 8. " SPIS168 ,SPI Status Bit 168" "Low,High" textline " " bitfld.long 0x00 7. " SPIS167 ,SPI Status Bit 167" "Low,High" bitfld.long 0x00 6. " SPIS166 ,SPI Status Bit 166" "Low,High" bitfld.long 0x00 5. " SPIS165 ,SPI Status Bit 165" "Low,High" textline " " bitfld.long 0x00 4. " SPIS164 ,SPI Status Bit 164" "Low,High" bitfld.long 0x00 3. " SPIS163 ,SPI Status Bit 163" "Low,High" bitfld.long 0x00 2. " SPIS162 ,SPI Status Bit 162" "Low,High" textline " " bitfld.long 0x00 1. " SPIS161 ,SPI Status Bit 161" "Low,High" bitfld.long 0x00 0. " SPIS160 ,SPI Status Bit 160" "Low,High" else hgroup.long 0xC094++0x03 hide.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) rgroup.long 0xC098++0x03 line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" bitfld.long 0x00 31. " SPIS223 ,SPI Status Bit 223" "Low,High" bitfld.long 0x00 30. " SPIS222 ,SPI Status Bit 222" "Low,High" bitfld.long 0x00 29. " SPIS221 ,SPI Status Bit 221" "Low,High" textline " " bitfld.long 0x00 28. " SPIS220 ,SPI Status Bit 220" "Low,High" bitfld.long 0x00 27. " SPIS219 ,SPI Status Bit 219" "Low,High" bitfld.long 0x00 26. " SPIS218 ,SPI Status Bit 218" "Low,High" textline " " bitfld.long 0x00 25. " SPIS217 ,SPI Status Bit 217" "Low,High" bitfld.long 0x00 24. " SPIS216 ,SPI Status Bit 216" "Low,High" bitfld.long 0x00 23. " SPIS215 ,SPI Status Bit 215" "Low,High" textline " " bitfld.long 0x00 22. " SPIS214 ,SPI Status Bit 214" "Low,High" bitfld.long 0x00 21. " SPIS213 ,SPI Status Bit 213" "Low,High" bitfld.long 0x00 20. " SPIS212 ,SPI Status Bit 212" "Low,High" textline " " bitfld.long 0x00 19. " SPIS211 ,SPI Status Bit 211" "Low,High" bitfld.long 0x00 18. " SPIS210 ,SPI Status Bit 210" "Low,High" bitfld.long 0x00 17. " SPIS209 ,SPI Status Bit 209" "Low,High" textline " " bitfld.long 0x00 16. " SPIS208 ,SPI Status Bit 208" "Low,High" bitfld.long 0x00 15. " SPIS207 ,SPI Status Bit 207" "Low,High" bitfld.long 0x00 14. " SPIS206 ,SPI Status Bit 206" "Low,High" textline " " bitfld.long 0x00 13. " SPIS205 ,SPI Status Bit 205" "Low,High" bitfld.long 0x00 12. " SPIS204 ,SPI Status Bit 204" "Low,High" bitfld.long 0x00 11. " SPIS203 ,SPI Status Bit 203" "Low,High" textline " " bitfld.long 0x00 10. " SPIS202 ,SPI Status Bit 202" "Low,High" bitfld.long 0x00 9. " SPIS201 ,SPI Status Bit 201" "Low,High" bitfld.long 0x00 8. " SPIS200 ,SPI Status Bit 200" "Low,High" textline " " bitfld.long 0x00 7. " SPIS199 ,SPI Status Bit 199" "Low,High" bitfld.long 0x00 6. " SPIS198 ,SPI Status Bit 198" "Low,High" bitfld.long 0x00 5. " SPIS197 ,SPI Status Bit 197" "Low,High" textline " " bitfld.long 0x00 4. " SPIS196 ,SPI Status Bit 196" "Low,High" bitfld.long 0x00 3. " SPIS195 ,SPI Status Bit 195" "Low,High" bitfld.long 0x00 2. " SPIS194 ,SPI Status Bit 194" "Low,High" textline " " bitfld.long 0x00 1. " SPIS193 ,SPI Status Bit 193" "Low,High" bitfld.long 0x00 0. " SPIS192 ,SPI Status Bit 192" "Low,High" else hgroup.long 0xC098++0x03 hide.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) rgroup.long 0xC09C++0x03 line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" bitfld.long 0x00 31. " SPIS255 ,SPI Status Bit 255" "Low,High" bitfld.long 0x00 30. " SPIS254 ,SPI Status Bit 254" "Low,High" bitfld.long 0x00 29. " SPIS253 ,SPI Status Bit 253" "Low,High" textline " " bitfld.long 0x00 28. " SPIS252 ,SPI Status Bit 252" "Low,High" bitfld.long 0x00 27. " SPIS251 ,SPI Status Bit 251" "Low,High" bitfld.long 0x00 26. " SPIS250 ,SPI Status Bit 250" "Low,High" textline " " bitfld.long 0x00 25. " SPIS249 ,SPI Status Bit 249" "Low,High" bitfld.long 0x00 24. " SPIS248 ,SPI Status Bit 248" "Low,High" bitfld.long 0x00 23. " SPIS247 ,SPI Status Bit 247" "Low,High" textline " " bitfld.long 0x00 22. " SPIS246 ,SPI Status Bit 246" "Low,High" bitfld.long 0x00 21. " SPIS245 ,SPI Status Bit 245" "Low,High" bitfld.long 0x00 20. " SPIS244 ,SPI Status Bit 244" "Low,High" textline " " bitfld.long 0x00 19. " SPIS243 ,SPI Status Bit 243" "Low,High" bitfld.long 0x00 18. " SPIS242 ,SPI Status Bit 242" "Low,High" bitfld.long 0x00 17. " SPIS241 ,SPI Status Bit 241" "Low,High" textline " " bitfld.long 0x00 16. " SPIS240 ,SPI Status Bit 240" "Low,High" bitfld.long 0x00 15. " SPIS239 ,SPI Status Bit 239" "Low,High" bitfld.long 0x00 14. " SPIS238 ,SPI Status Bit 238" "Low,High" textline " " bitfld.long 0x00 13. " SPIS237 ,SPI Status Bit 237" "Low,High" bitfld.long 0x00 12. " SPIS236 ,SPI Status Bit 236" "Low,High" bitfld.long 0x00 11. " SPIS235 ,SPI Status Bit 235" "Low,High" textline " " bitfld.long 0x00 10. " SPIS234 ,SPI Status Bit 234" "Low,High" bitfld.long 0x00 9. " SPIS233 ,SPI Status Bit 233" "Low,High" bitfld.long 0x00 8. " SPIS232 ,SPI Status Bit 232" "Low,High" textline " " bitfld.long 0x00 7. " SPIS231 ,SPI Status Bit 231" "Low,High" bitfld.long 0x00 6. " SPIS230 ,SPI Status Bit 230" "Low,High" bitfld.long 0x00 5. " SPIS229 ,SPI Status Bit 229" "Low,High" textline " " bitfld.long 0x00 4. " SPIS228 ,SPI Status Bit 228" "Low,High" bitfld.long 0x00 3. " SPIS227 ,SPI Status Bit 227" "Low,High" bitfld.long 0x00 2. " SPIS226 ,SPI Status Bit 226" "Low,High" textline " " bitfld.long 0x00 1. " SPIS225 ,SPI Status Bit 225" "Low,High" bitfld.long 0x00 0. " SPIS224 ,SPI Status Bit 224" "Low,High" else hgroup.long 0xC09C++0x03 hide.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) rgroup.long 0xC0A0++0x03 line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" bitfld.long 0x00 31. " SPIS287 ,SPI Status Bit 287" "Low,High" bitfld.long 0x00 30. " SPIS286 ,SPI Status Bit 286" "Low,High" bitfld.long 0x00 29. " SPIS285 ,SPI Status Bit 285" "Low,High" textline " " bitfld.long 0x00 28. " SPIS284 ,SPI Status Bit 284" "Low,High" bitfld.long 0x00 27. " SPIS283 ,SPI Status Bit 283" "Low,High" bitfld.long 0x00 26. " SPIS282 ,SPI Status Bit 282" "Low,High" textline " " bitfld.long 0x00 25. " SPIS281 ,SPI Status Bit 281" "Low,High" bitfld.long 0x00 24. " SPIS280 ,SPI Status Bit 280" "Low,High" bitfld.long 0x00 23. " SPIS279 ,SPI Status Bit 279" "Low,High" textline " " bitfld.long 0x00 22. " SPIS278 ,SPI Status Bit 278" "Low,High" bitfld.long 0x00 21. " SPIS277 ,SPI Status Bit 277" "Low,High" bitfld.long 0x00 20. " SPIS276 ,SPI Status Bit 276" "Low,High" textline " " bitfld.long 0x00 19. " SPIS275 ,SPI Status Bit 275" "Low,High" bitfld.long 0x00 18. " SPIS274 ,SPI Status Bit 274" "Low,High" bitfld.long 0x00 17. " SPIS273 ,SPI Status Bit 273" "Low,High" textline " " bitfld.long 0x00 16. " SPIS272 ,SPI Status Bit 272" "Low,High" bitfld.long 0x00 15. " SPIS271 ,SPI Status Bit 271" "Low,High" bitfld.long 0x00 14. " SPIS270 ,SPI Status Bit 270" "Low,High" textline " " bitfld.long 0x00 13. " SPIS269 ,SPI Status Bit 269" "Low,High" bitfld.long 0x00 12. " SPIS268 ,SPI Status Bit 268" "Low,High" bitfld.long 0x00 11. " SPIS267 ,SPI Status Bit 267" "Low,High" textline " " bitfld.long 0x00 10. " SPIS266 ,SPI Status Bit 266" "Low,High" bitfld.long 0x00 9. " SPIS265 ,SPI Status Bit 265" "Low,High" bitfld.long 0x00 8. " SPIS264 ,SPI Status Bit 264" "Low,High" textline " " bitfld.long 0x00 7. " SPIS263 ,SPI Status Bit 263" "Low,High" bitfld.long 0x00 6. " SPIS262 ,SPI Status Bit 262" "Low,High" bitfld.long 0x00 5. " SPIS261 ,SPI Status Bit 261" "Low,High" textline " " bitfld.long 0x00 4. " SPIS260 ,SPI Status Bit 260" "Low,High" bitfld.long 0x00 3. " SPIS259 ,SPI Status Bit 259" "Low,High" bitfld.long 0x00 2. " SPIS258 ,SPI Status Bit 258" "Low,High" textline " " bitfld.long 0x00 1. " SPIS257 ,SPI Status Bit 257" "Low,High" bitfld.long 0x00 0. " SPIS256 ,SPI Status Bit 256" "Low,High" else hgroup.long 0xC0A0++0x03 hide.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) rgroup.long 0xC0A4++0x03 line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" bitfld.long 0x00 31. " SPIS319 ,SPI Status Bit 319" "Low,High" bitfld.long 0x00 30. " SPIS318 ,SPI Status Bit 318" "Low,High" bitfld.long 0x00 29. " SPIS317 ,SPI Status Bit 317" "Low,High" textline " " bitfld.long 0x00 28. " SPIS316 ,SPI Status Bit 316" "Low,High" bitfld.long 0x00 27. " SPIS315 ,SPI Status Bit 315" "Low,High" bitfld.long 0x00 26. " SPIS314 ,SPI Status Bit 314" "Low,High" textline " " bitfld.long 0x00 25. " SPIS313 ,SPI Status Bit 313" "Low,High" bitfld.long 0x00 24. " SPIS312 ,SPI Status Bit 312" "Low,High" bitfld.long 0x00 23. " SPIS311 ,SPI Status Bit 311" "Low,High" textline " " bitfld.long 0x00 22. " SPIS310 ,SPI Status Bit 310" "Low,High" bitfld.long 0x00 21. " SPIS309 ,SPI Status Bit 309" "Low,High" bitfld.long 0x00 20. " SPIS308 ,SPI Status Bit 308" "Low,High" textline " " bitfld.long 0x00 19. " SPIS307 ,SPI Status Bit 307" "Low,High" bitfld.long 0x00 18. " SPIS306 ,SPI Status Bit 306" "Low,High" bitfld.long 0x00 17. " SPIS305 ,SPI Status Bit 305" "Low,High" textline " " bitfld.long 0x00 16. " SPIS304 ,SPI Status Bit 304" "Low,High" bitfld.long 0x00 15. " SPIS303 ,SPI Status Bit 303" "Low,High" bitfld.long 0x00 14. " SPIS302 ,SPI Status Bit 302" "Low,High" textline " " bitfld.long 0x00 13. " SPIS301 ,SPI Status Bit 301" "Low,High" bitfld.long 0x00 12. " SPIS300 ,SPI Status Bit 300" "Low,High" bitfld.long 0x00 11. " SPIS299 ,SPI Status Bit 299" "Low,High" textline " " bitfld.long 0x00 10. " SPIS298 ,SPI Status Bit 298" "Low,High" bitfld.long 0x00 9. " SPIS297 ,SPI Status Bit 297" "Low,High" bitfld.long 0x00 8. " SPIS296 ,SPI Status Bit 296" "Low,High" textline " " bitfld.long 0x00 7. " SPIS295 ,SPI Status Bit 295" "Low,High" bitfld.long 0x00 6. " SPIS294 ,SPI Status Bit 294" "Low,High" bitfld.long 0x00 5. " SPIS293 ,SPI Status Bit 293" "Low,High" textline " " bitfld.long 0x00 4. " SPIS292 ,SPI Status Bit 292" "Low,High" bitfld.long 0x00 3. " SPIS291 ,SPI Status Bit 291" "Low,High" bitfld.long 0x00 2. " SPIS290 ,SPI Status Bit 290" "Low,High" textline " " bitfld.long 0x00 1. " SPIS289 ,SPI Status Bit 289" "Low,High" bitfld.long 0x00 0. " SPIS288 ,SPI Status Bit 288" "Low,High" else hgroup.long 0xC0A4++0x03 hide.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) rgroup.long 0xC0A8++0x03 line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" bitfld.long 0x00 31. " SPIS351 ,SPI Status Bit 351" "Low,High" bitfld.long 0x00 30. " SPIS350 ,SPI Status Bit 350" "Low,High" bitfld.long 0x00 29. " SPIS349 ,SPI Status Bit 349" "Low,High" textline " " bitfld.long 0x00 28. " SPIS348 ,SPI Status Bit 348" "Low,High" bitfld.long 0x00 27. " SPIS347 ,SPI Status Bit 347" "Low,High" bitfld.long 0x00 26. " SPIS346 ,SPI Status Bit 346" "Low,High" textline " " bitfld.long 0x00 25. " SPIS345 ,SPI Status Bit 345" "Low,High" bitfld.long 0x00 24. " SPIS344 ,SPI Status Bit 344" "Low,High" bitfld.long 0x00 23. " SPIS343 ,SPI Status Bit 343" "Low,High" textline " " bitfld.long 0x00 22. " SPIS342 ,SPI Status Bit 342" "Low,High" bitfld.long 0x00 21. " SPIS341 ,SPI Status Bit 341" "Low,High" bitfld.long 0x00 20. " SPIS340 ,SPI Status Bit 340" "Low,High" textline " " bitfld.long 0x00 19. " SPIS339 ,SPI Status Bit 339" "Low,High" bitfld.long 0x00 18. " SPIS338 ,SPI Status Bit 338" "Low,High" bitfld.long 0x00 17. " SPIS337 ,SPI Status Bit 337" "Low,High" textline " " bitfld.long 0x00 16. " SPIS336 ,SPI Status Bit 336" "Low,High" bitfld.long 0x00 15. " SPIS335 ,SPI Status Bit 335" "Low,High" bitfld.long 0x00 14. " SPIS334 ,SPI Status Bit 334" "Low,High" textline " " bitfld.long 0x00 13. " SPIS333 ,SPI Status Bit 333" "Low,High" bitfld.long 0x00 12. " SPIS332 ,SPI Status Bit 332" "Low,High" bitfld.long 0x00 11. " SPIS331 ,SPI Status Bit 331" "Low,High" textline " " bitfld.long 0x00 10. " SPIS330 ,SPI Status Bit 330" "Low,High" bitfld.long 0x00 9. " SPIS329 ,SPI Status Bit 329" "Low,High" bitfld.long 0x00 8. " SPIS328 ,SPI Status Bit 328" "Low,High" textline " " bitfld.long 0x00 7. " SPIS327 ,SPI Status Bit 327" "Low,High" bitfld.long 0x00 6. " SPIS326 ,SPI Status Bit 326" "Low,High" bitfld.long 0x00 5. " SPIS325 ,SPI Status Bit 325" "Low,High" textline " " bitfld.long 0x00 4. " SPIS324 ,SPI Status Bit 324" "Low,High" bitfld.long 0x00 3. " SPIS323 ,SPI Status Bit 323" "Low,High" bitfld.long 0x00 2. " SPIS322 ,SPI Status Bit 322" "Low,High" textline " " bitfld.long 0x00 1. " SPIS321 ,SPI Status Bit 321" "Low,High" bitfld.long 0x00 0. " SPIS320 ,SPI Status Bit 320" "Low,High" else hgroup.long 0xC0A8++0x03 hide.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) rgroup.long 0xC0AC++0x03 line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" bitfld.long 0x00 31. " SPIS383 ,SPI Status Bit 383" "Low,High" bitfld.long 0x00 30. " SPIS382 ,SPI Status Bit 382" "Low,High" bitfld.long 0x00 29. " SPIS381 ,SPI Status Bit 381" "Low,High" textline " " bitfld.long 0x00 28. " SPIS380 ,SPI Status Bit 380" "Low,High" bitfld.long 0x00 27. " SPIS379 ,SPI Status Bit 379" "Low,High" bitfld.long 0x00 26. " SPIS378 ,SPI Status Bit 378" "Low,High" textline " " bitfld.long 0x00 25. " SPIS377 ,SPI Status Bit 377" "Low,High" bitfld.long 0x00 24. " SPIS376 ,SPI Status Bit 376" "Low,High" bitfld.long 0x00 23. " SPIS375 ,SPI Status Bit 375" "Low,High" textline " " bitfld.long 0x00 22. " SPIS374 ,SPI Status Bit 374" "Low,High" bitfld.long 0x00 21. " SPIS373 ,SPI Status Bit 373" "Low,High" bitfld.long 0x00 20. " SPIS372 ,SPI Status Bit 372" "Low,High" textline " " bitfld.long 0x00 19. " SPIS371 ,SPI Status Bit 371" "Low,High" bitfld.long 0x00 18. " SPIS370 ,SPI Status Bit 370" "Low,High" bitfld.long 0x00 17. " SPIS369 ,SPI Status Bit 369" "Low,High" textline " " bitfld.long 0x00 16. " SPIS368 ,SPI Status Bit 368" "Low,High" bitfld.long 0x00 15. " SPIS367 ,SPI Status Bit 367" "Low,High" bitfld.long 0x00 14. " SPIS366 ,SPI Status Bit 366" "Low,High" textline " " bitfld.long 0x00 13. " SPIS365 ,SPI Status Bit 365" "Low,High" bitfld.long 0x00 12. " SPIS364 ,SPI Status Bit 364" "Low,High" bitfld.long 0x00 11. " SPIS363 ,SPI Status Bit 363" "Low,High" textline " " bitfld.long 0x00 10. " SPIS362 ,SPI Status Bit 362" "Low,High" bitfld.long 0x00 9. " SPIS361 ,SPI Status Bit 361" "Low,High" bitfld.long 0x00 8. " SPIS360 ,SPI Status Bit 360" "Low,High" textline " " bitfld.long 0x00 7. " SPIS359 ,SPI Status Bit 359" "Low,High" bitfld.long 0x00 6. " SPIS358 ,SPI Status Bit 358" "Low,High" bitfld.long 0x00 5. " SPIS357 ,SPI Status Bit 357" "Low,High" textline " " bitfld.long 0x00 4. " SPIS356 ,SPI Status Bit 356" "Low,High" bitfld.long 0x00 3. " SPIS355 ,SPI Status Bit 355" "Low,High" bitfld.long 0x00 2. " SPIS354 ,SPI Status Bit 354" "Low,High" textline " " bitfld.long 0x00 1. " SPIS353 ,SPI Status Bit 353" "Low,High" bitfld.long 0x00 0. " SPIS352 ,SPI Status Bit 352" "Low,High" else hgroup.long 0xC0AC++0x03 hide.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) rgroup.long 0xC0B0++0x03 line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" bitfld.long 0x00 31. " SPIS415 ,SPI Status Bit 415" "Low,High" bitfld.long 0x00 30. " SPIS414 ,SPI Status Bit 414" "Low,High" bitfld.long 0x00 29. " SPIS413 ,SPI Status Bit 413" "Low,High" textline " " bitfld.long 0x00 28. " SPIS412 ,SPI Status Bit 412" "Low,High" bitfld.long 0x00 27. " SPIS411 ,SPI Status Bit 411" "Low,High" bitfld.long 0x00 26. " SPIS410 ,SPI Status Bit 410" "Low,High" textline " " bitfld.long 0x00 25. " SPIS409 ,SPI Status Bit 409" "Low,High" bitfld.long 0x00 24. " SPIS408 ,SPI Status Bit 408" "Low,High" bitfld.long 0x00 23. " SPIS407 ,SPI Status Bit 407" "Low,High" textline " " bitfld.long 0x00 22. " SPIS406 ,SPI Status Bit 406" "Low,High" bitfld.long 0x00 21. " SPIS405 ,SPI Status Bit 405" "Low,High" bitfld.long 0x00 20. " SPIS404 ,SPI Status Bit 404" "Low,High" textline " " bitfld.long 0x00 19. " SPIS403 ,SPI Status Bit 403" "Low,High" bitfld.long 0x00 18. " SPIS402 ,SPI Status Bit 402" "Low,High" bitfld.long 0x00 17. " SPIS401 ,SPI Status Bit 401" "Low,High" textline " " bitfld.long 0x00 16. " SPIS400 ,SPI Status Bit 400" "Low,High" bitfld.long 0x00 15. " SPIS399 ,SPI Status Bit 399" "Low,High" bitfld.long 0x00 14. " SPIS398 ,SPI Status Bit 398" "Low,High" textline " " bitfld.long 0x00 13. " SPIS397 ,SPI Status Bit 397" "Low,High" bitfld.long 0x00 12. " SPIS396 ,SPI Status Bit 396" "Low,High" bitfld.long 0x00 11. " SPIS395 ,SPI Status Bit 395" "Low,High" textline " " bitfld.long 0x00 10. " SPIS394 ,SPI Status Bit 394" "Low,High" bitfld.long 0x00 9. " SPIS393 ,SPI Status Bit 393" "Low,High" bitfld.long 0x00 8. " SPIS392 ,SPI Status Bit 392" "Low,High" textline " " bitfld.long 0x00 7. " SPIS391 ,SPI Status Bit 391" "Low,High" bitfld.long 0x00 6. " SPIS390 ,SPI Status Bit 390" "Low,High" bitfld.long 0x00 5. " SPIS389 ,SPI Status Bit 389" "Low,High" textline " " bitfld.long 0x00 4. " SPIS388 ,SPI Status Bit 388" "Low,High" bitfld.long 0x00 3. " SPIS387 ,SPI Status Bit 387" "Low,High" bitfld.long 0x00 2. " SPIS386 ,SPI Status Bit 386" "Low,High" textline " " bitfld.long 0x00 1. " SPIS385 ,SPI Status Bit 385" "Low,High" bitfld.long 0x00 0. " SPIS384 ,SPI Status Bit 384" "Low,High" else hgroup.long 0xC0B0++0x03 hide.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) rgroup.long 0xC0B4++0x03 line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" bitfld.long 0x00 31. " SPIS447 ,SPI Status Bit 447" "Low,High" bitfld.long 0x00 30. " SPIS446 ,SPI Status Bit 446" "Low,High" bitfld.long 0x00 29. " SPIS445 ,SPI Status Bit 445" "Low,High" textline " " bitfld.long 0x00 28. " SPIS444 ,SPI Status Bit 444" "Low,High" bitfld.long 0x00 27. " SPIS443 ,SPI Status Bit 443" "Low,High" bitfld.long 0x00 26. " SPIS442 ,SPI Status Bit 442" "Low,High" textline " " bitfld.long 0x00 25. " SPIS441 ,SPI Status Bit 441" "Low,High" bitfld.long 0x00 24. " SPIS440 ,SPI Status Bit 440" "Low,High" bitfld.long 0x00 23. " SPIS439 ,SPI Status Bit 439" "Low,High" textline " " bitfld.long 0x00 22. " SPIS438 ,SPI Status Bit 438" "Low,High" bitfld.long 0x00 21. " SPIS437 ,SPI Status Bit 437" "Low,High" bitfld.long 0x00 20. " SPIS436 ,SPI Status Bit 436" "Low,High" textline " " bitfld.long 0x00 19. " SPIS435 ,SPI Status Bit 435" "Low,High" bitfld.long 0x00 18. " SPIS434 ,SPI Status Bit 434" "Low,High" bitfld.long 0x00 17. " SPIS433 ,SPI Status Bit 433" "Low,High" textline " " bitfld.long 0x00 16. " SPIS432 ,SPI Status Bit 432" "Low,High" bitfld.long 0x00 15. " SPIS431 ,SPI Status Bit 431" "Low,High" bitfld.long 0x00 14. " SPIS430 ,SPI Status Bit 430" "Low,High" textline " " bitfld.long 0x00 13. " SPIS429 ,SPI Status Bit 429" "Low,High" bitfld.long 0x00 12. " SPIS428 ,SPI Status Bit 428" "Low,High" bitfld.long 0x00 11. " SPIS427 ,SPI Status Bit 427" "Low,High" textline " " bitfld.long 0x00 10. " SPIS426 ,SPI Status Bit 426" "Low,High" bitfld.long 0x00 9. " SPIS425 ,SPI Status Bit 425" "Low,High" bitfld.long 0x00 8. " SPIS424 ,SPI Status Bit 424" "Low,High" textline " " bitfld.long 0x00 7. " SPIS423 ,SPI Status Bit 423" "Low,High" bitfld.long 0x00 6. " SPIS422 ,SPI Status Bit 422" "Low,High" bitfld.long 0x00 5. " SPIS421 ,SPI Status Bit 421" "Low,High" textline " " bitfld.long 0x00 4. " SPIS420 ,SPI Status Bit 420" "Low,High" bitfld.long 0x00 3. " SPIS419 ,SPI Status Bit 419" "Low,High" bitfld.long 0x00 2. " SPIS418 ,SPI Status Bit 418" "Low,High" textline " " bitfld.long 0x00 1. " SPIS417 ,SPI Status Bit 417" "Low,High" bitfld.long 0x00 0. " SPIS416 ,SPI Status Bit 416" "Low,High" else hgroup.long 0xC0B4++0x03 hide.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) rgroup.long 0xC0B8++0x03 line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" bitfld.long 0x00 31. " SPIS479 ,SPI Status Bit 479" "Low,High" bitfld.long 0x00 30. " SPIS478 ,SPI Status Bit 478" "Low,High" bitfld.long 0x00 29. " SPIS477 ,SPI Status Bit 477" "Low,High" textline " " bitfld.long 0x00 28. " SPIS476 ,SPI Status Bit 476" "Low,High" bitfld.long 0x00 27. " SPIS475 ,SPI Status Bit 475" "Low,High" bitfld.long 0x00 26. " SPIS474 ,SPI Status Bit 474" "Low,High" textline " " bitfld.long 0x00 25. " SPIS473 ,SPI Status Bit 473" "Low,High" bitfld.long 0x00 24. " SPIS472 ,SPI Status Bit 472" "Low,High" bitfld.long 0x00 23. " SPIS471 ,SPI Status Bit 471" "Low,High" textline " " bitfld.long 0x00 22. " SPIS470 ,SPI Status Bit 470" "Low,High" bitfld.long 0x00 21. " SPIS469 ,SPI Status Bit 469" "Low,High" bitfld.long 0x00 20. " SPIS468 ,SPI Status Bit 468" "Low,High" textline " " bitfld.long 0x00 19. " SPIS467 ,SPI Status Bit 467" "Low,High" bitfld.long 0x00 18. " SPIS466 ,SPI Status Bit 466" "Low,High" bitfld.long 0x00 17. " SPIS465 ,SPI Status Bit 465" "Low,High" textline " " bitfld.long 0x00 16. " SPIS464 ,SPI Status Bit 464" "Low,High" bitfld.long 0x00 15. " SPIS463 ,SPI Status Bit 463" "Low,High" bitfld.long 0x00 14. " SPIS462 ,SPI Status Bit 462" "Low,High" textline " " bitfld.long 0x00 13. " SPIS461 ,SPI Status Bit 461" "Low,High" bitfld.long 0x00 12. " SPIS460 ,SPI Status Bit 460" "Low,High" bitfld.long 0x00 11. " SPIS459 ,SPI Status Bit 459" "Low,High" textline " " bitfld.long 0x00 10. " SPIS458 ,SPI Status Bit 458" "Low,High" bitfld.long 0x00 9. " SPIS457 ,SPI Status Bit 457" "Low,High" bitfld.long 0x00 8. " SPIS456 ,SPI Status Bit 456" "Low,High" textline " " bitfld.long 0x00 7. " SPIS455 ,SPI Status Bit 455" "Low,High" bitfld.long 0x00 6. " SPIS454 ,SPI Status Bit 454" "Low,High" bitfld.long 0x00 5. " SPIS453 ,SPI Status Bit 453" "Low,High" textline " " bitfld.long 0x00 4. " SPIS452 ,SPI Status Bit 452" "Low,High" bitfld.long 0x00 3. " SPIS451 ,SPI Status Bit 451" "Low,High" bitfld.long 0x00 2. " SPIS450 ,SPI Status Bit 450" "Low,High" textline " " bitfld.long 0x00 1. " SPIS449 ,SPI Status Bit 449" "Low,High" bitfld.long 0x00 0. " SPIS448 ,SPI Status Bit 448" "Low,High" else hgroup.long 0xC0B8++0x03 hide.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) rgroup.long 0xC0BC++0x03 line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" bitfld.long 0x00 31. " SPIS511 ,SPI Status Bit 511" "Low,High" bitfld.long 0x00 30. " SPIS510 ,SPI Status Bit 510" "Low,High" bitfld.long 0x00 29. " SPIS509 ,SPI Status Bit 509" "Low,High" textline " " bitfld.long 0x00 28. " SPIS508 ,SPI Status Bit 508" "Low,High" bitfld.long 0x00 27. " SPIS507 ,SPI Status Bit 507" "Low,High" bitfld.long 0x00 26. " SPIS506 ,SPI Status Bit 506" "Low,High" textline " " bitfld.long 0x00 25. " SPIS505 ,SPI Status Bit 505" "Low,High" bitfld.long 0x00 24. " SPIS504 ,SPI Status Bit 504" "Low,High" bitfld.long 0x00 23. " SPIS503 ,SPI Status Bit 503" "Low,High" textline " " bitfld.long 0x00 22. " SPIS502 ,SPI Status Bit 502" "Low,High" bitfld.long 0x00 21. " SPIS501 ,SPI Status Bit 501" "Low,High" bitfld.long 0x00 20. " SPIS500 ,SPI Status Bit 500" "Low,High" textline " " bitfld.long 0x00 19. " SPIS499 ,SPI Status Bit 499" "Low,High" bitfld.long 0x00 18. " SPIS498 ,SPI Status Bit 498" "Low,High" bitfld.long 0x00 17. " SPIS497 ,SPI Status Bit 497" "Low,High" textline " " bitfld.long 0x00 16. " SPIS496 ,SPI Status Bit 496" "Low,High" bitfld.long 0x00 15. " SPIS495 ,SPI Status Bit 495" "Low,High" bitfld.long 0x00 14. " SPIS494 ,SPI Status Bit 494" "Low,High" textline " " bitfld.long 0x00 13. " SPIS493 ,SPI Status Bit 493" "Low,High" bitfld.long 0x00 12. " SPIS492 ,SPI Status Bit 492" "Low,High" bitfld.long 0x00 11. " SPIS491 ,SPI Status Bit 491" "Low,High" textline " " bitfld.long 0x00 10. " SPIS490 ,SPI Status Bit 490" "Low,High" bitfld.long 0x00 9. " SPIS489 ,SPI Status Bit 489" "Low,High" bitfld.long 0x00 8. " SPIS488 ,SPI Status Bit 488" "Low,High" textline " " bitfld.long 0x00 7. " SPIS487 ,SPI Status Bit 487" "Low,High" bitfld.long 0x00 6. " SPIS486 ,SPI Status Bit 486" "Low,High" bitfld.long 0x00 5. " SPIS485 ,SPI Status Bit 485" "Low,High" textline " " bitfld.long 0x00 4. " SPIS484 ,SPI Status Bit 484" "Low,High" bitfld.long 0x00 3. " SPIS483 ,SPI Status Bit 483" "Low,High" bitfld.long 0x00 2. " SPIS482 ,SPI Status Bit 482" "Low,High" textline " " bitfld.long 0x00 1. " SPIS481 ,SPI Status Bit 481" "Low,High" bitfld.long 0x00 0. " SPIS480 ,SPI Status Bit 480" "Low,High" else hgroup.long 0xC0BC++0x03 hide.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) rgroup.long 0xC0C0++0x03 line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" bitfld.long 0x00 31. " SPIS543 ,SPI Status Bit 543" "Low,High" bitfld.long 0x00 30. " SPIS542 ,SPI Status Bit 542" "Low,High" bitfld.long 0x00 29. " SPIS541 ,SPI Status Bit 541" "Low,High" textline " " bitfld.long 0x00 28. " SPIS540 ,SPI Status Bit 540" "Low,High" bitfld.long 0x00 27. " SPIS539 ,SPI Status Bit 539" "Low,High" bitfld.long 0x00 26. " SPIS538 ,SPI Status Bit 538" "Low,High" textline " " bitfld.long 0x00 25. " SPIS537 ,SPI Status Bit 537" "Low,High" bitfld.long 0x00 24. " SPIS536 ,SPI Status Bit 536" "Low,High" bitfld.long 0x00 23. " SPIS535 ,SPI Status Bit 535" "Low,High" textline " " bitfld.long 0x00 22. " SPIS534 ,SPI Status Bit 534" "Low,High" bitfld.long 0x00 21. " SPIS533 ,SPI Status Bit 533" "Low,High" bitfld.long 0x00 20. " SPIS532 ,SPI Status Bit 532" "Low,High" textline " " bitfld.long 0x00 19. " SPIS531 ,SPI Status Bit 531" "Low,High" bitfld.long 0x00 18. " SPIS530 ,SPI Status Bit 530" "Low,High" bitfld.long 0x00 17. " SPIS529 ,SPI Status Bit 529" "Low,High" textline " " bitfld.long 0x00 16. " SPIS528 ,SPI Status Bit 528" "Low,High" bitfld.long 0x00 15. " SPIS527 ,SPI Status Bit 527" "Low,High" bitfld.long 0x00 14. " SPIS526 ,SPI Status Bit 526" "Low,High" textline " " bitfld.long 0x00 13. " SPIS525 ,SPI Status Bit 525" "Low,High" bitfld.long 0x00 12. " SPIS524 ,SPI Status Bit 524" "Low,High" bitfld.long 0x00 11. " SPIS523 ,SPI Status Bit 523" "Low,High" textline " " bitfld.long 0x00 10. " SPIS522 ,SPI Status Bit 522" "Low,High" bitfld.long 0x00 9. " SPIS521 ,SPI Status Bit 521" "Low,High" bitfld.long 0x00 8. " SPIS520 ,SPI Status Bit 520" "Low,High" textline " " bitfld.long 0x00 7. " SPIS519 ,SPI Status Bit 519" "Low,High" bitfld.long 0x00 6. " SPIS518 ,SPI Status Bit 518" "Low,High" bitfld.long 0x00 5. " SPIS517 ,SPI Status Bit 517" "Low,High" textline " " bitfld.long 0x00 4. " SPIS516 ,SPI Status Bit 516" "Low,High" bitfld.long 0x00 3. " SPIS515 ,SPI Status Bit 515" "Low,High" bitfld.long 0x00 2. " SPIS514 ,SPI Status Bit 514" "Low,High" textline " " bitfld.long 0x00 1. " SPIS513 ,SPI Status Bit 513" "Low,High" bitfld.long 0x00 0. " SPIS512 ,SPI Status Bit 512" "Low,High" else hgroup.long 0xC0C0++0x03 hide.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) rgroup.long 0xC0C4++0x03 line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" bitfld.long 0x00 31. " SPIS575 ,SPI Status Bit 575" "Low,High" bitfld.long 0x00 30. " SPIS574 ,SPI Status Bit 574" "Low,High" bitfld.long 0x00 29. " SPIS573 ,SPI Status Bit 573" "Low,High" textline " " bitfld.long 0x00 28. " SPIS572 ,SPI Status Bit 572" "Low,High" bitfld.long 0x00 27. " SPIS571 ,SPI Status Bit 571" "Low,High" bitfld.long 0x00 26. " SPIS570 ,SPI Status Bit 570" "Low,High" textline " " bitfld.long 0x00 25. " SPIS569 ,SPI Status Bit 569" "Low,High" bitfld.long 0x00 24. " SPIS568 ,SPI Status Bit 568" "Low,High" bitfld.long 0x00 23. " SPIS567 ,SPI Status Bit 567" "Low,High" textline " " bitfld.long 0x00 22. " SPIS566 ,SPI Status Bit 566" "Low,High" bitfld.long 0x00 21. " SPIS565 ,SPI Status Bit 565" "Low,High" bitfld.long 0x00 20. " SPIS564 ,SPI Status Bit 564" "Low,High" textline " " bitfld.long 0x00 19. " SPIS563 ,SPI Status Bit 563" "Low,High" bitfld.long 0x00 18. " SPIS562 ,SPI Status Bit 562" "Low,High" bitfld.long 0x00 17. " SPIS561 ,SPI Status Bit 561" "Low,High" textline " " bitfld.long 0x00 16. " SPIS560 ,SPI Status Bit 560" "Low,High" bitfld.long 0x00 15. " SPIS559 ,SPI Status Bit 559" "Low,High" bitfld.long 0x00 14. " SPIS558 ,SPI Status Bit 558" "Low,High" textline " " bitfld.long 0x00 13. " SPIS557 ,SPI Status Bit 557" "Low,High" bitfld.long 0x00 12. " SPIS556 ,SPI Status Bit 556" "Low,High" bitfld.long 0x00 11. " SPIS555 ,SPI Status Bit 555" "Low,High" textline " " bitfld.long 0x00 10. " SPIS554 ,SPI Status Bit 554" "Low,High" bitfld.long 0x00 9. " SPIS553 ,SPI Status Bit 553" "Low,High" bitfld.long 0x00 8. " SPIS552 ,SPI Status Bit 552" "Low,High" textline " " bitfld.long 0x00 7. " SPIS551 ,SPI Status Bit 551" "Low,High" bitfld.long 0x00 6. " SPIS550 ,SPI Status Bit 550" "Low,High" bitfld.long 0x00 5. " SPIS549 ,SPI Status Bit 549" "Low,High" textline " " bitfld.long 0x00 4. " SPIS548 ,SPI Status Bit 548" "Low,High" bitfld.long 0x00 3. " SPIS547 ,SPI Status Bit 547" "Low,High" bitfld.long 0x00 2. " SPIS546 ,SPI Status Bit 546" "Low,High" textline " " bitfld.long 0x00 1. " SPIS545 ,SPI Status Bit 545" "Low,High" bitfld.long 0x00 0. " SPIS544 ,SPI Status Bit 544" "Low,High" else hgroup.long 0xC0C4++0x03 hide.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) rgroup.long 0xC0C8++0x03 line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" bitfld.long 0x00 31. " SPIS607 ,SPI Status Bit 607" "Low,High" bitfld.long 0x00 30. " SPIS606 ,SPI Status Bit 606" "Low,High" bitfld.long 0x00 29. " SPIS605 ,SPI Status Bit 605" "Low,High" textline " " bitfld.long 0x00 28. " SPIS604 ,SPI Status Bit 604" "Low,High" bitfld.long 0x00 27. " SPIS603 ,SPI Status Bit 603" "Low,High" bitfld.long 0x00 26. " SPIS602 ,SPI Status Bit 602" "Low,High" textline " " bitfld.long 0x00 25. " SPIS601 ,SPI Status Bit 601" "Low,High" bitfld.long 0x00 24. " SPIS600 ,SPI Status Bit 600" "Low,High" bitfld.long 0x00 23. " SPIS599 ,SPI Status Bit 599" "Low,High" textline " " bitfld.long 0x00 22. " SPIS598 ,SPI Status Bit 598" "Low,High" bitfld.long 0x00 21. " SPIS597 ,SPI Status Bit 597" "Low,High" bitfld.long 0x00 20. " SPIS596 ,SPI Status Bit 596" "Low,High" textline " " bitfld.long 0x00 19. " SPIS595 ,SPI Status Bit 595" "Low,High" bitfld.long 0x00 18. " SPIS594 ,SPI Status Bit 594" "Low,High" bitfld.long 0x00 17. " SPIS593 ,SPI Status Bit 593" "Low,High" textline " " bitfld.long 0x00 16. " SPIS592 ,SPI Status Bit 592" "Low,High" bitfld.long 0x00 15. " SPIS591 ,SPI Status Bit 591" "Low,High" bitfld.long 0x00 14. " SPIS590 ,SPI Status Bit 590" "Low,High" textline " " bitfld.long 0x00 13. " SPIS589 ,SPI Status Bit 589" "Low,High" bitfld.long 0x00 12. " SPIS588 ,SPI Status Bit 588" "Low,High" bitfld.long 0x00 11. " SPIS587 ,SPI Status Bit 587" "Low,High" textline " " bitfld.long 0x00 10. " SPIS586 ,SPI Status Bit 586" "Low,High" bitfld.long 0x00 9. " SPIS585 ,SPI Status Bit 585" "Low,High" bitfld.long 0x00 8. " SPIS584 ,SPI Status Bit 584" "Low,High" textline " " bitfld.long 0x00 7. " SPIS583 ,SPI Status Bit 583" "Low,High" bitfld.long 0x00 6. " SPIS582 ,SPI Status Bit 582" "Low,High" bitfld.long 0x00 5. " SPIS581 ,SPI Status Bit 581" "Low,High" textline " " bitfld.long 0x00 4. " SPIS580 ,SPI Status Bit 580" "Low,High" bitfld.long 0x00 3. " SPIS579 ,SPI Status Bit 579" "Low,High" bitfld.long 0x00 2. " SPIS578 ,SPI Status Bit 578" "Low,High" textline " " bitfld.long 0x00 1. " SPIS577 ,SPI Status Bit 577" "Low,High" bitfld.long 0x00 0. " SPIS576 ,SPI Status Bit 576" "Low,High" else hgroup.long 0xC0C8++0x03 hide.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) rgroup.long 0xC0CC++0x03 line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" bitfld.long 0x00 31. " SPIS639 ,SPI Status Bit 639" "Low,High" bitfld.long 0x00 30. " SPIS638 ,SPI Status Bit 638" "Low,High" bitfld.long 0x00 29. " SPIS637 ,SPI Status Bit 637" "Low,High" textline " " bitfld.long 0x00 28. " SPIS636 ,SPI Status Bit 636" "Low,High" bitfld.long 0x00 27. " SPIS635 ,SPI Status Bit 635" "Low,High" bitfld.long 0x00 26. " SPIS634 ,SPI Status Bit 634" "Low,High" textline " " bitfld.long 0x00 25. " SPIS633 ,SPI Status Bit 633" "Low,High" bitfld.long 0x00 24. " SPIS632 ,SPI Status Bit 632" "Low,High" bitfld.long 0x00 23. " SPIS631 ,SPI Status Bit 631" "Low,High" textline " " bitfld.long 0x00 22. " SPIS630 ,SPI Status Bit 630" "Low,High" bitfld.long 0x00 21. " SPIS629 ,SPI Status Bit 629" "Low,High" bitfld.long 0x00 20. " SPIS628 ,SPI Status Bit 628" "Low,High" textline " " bitfld.long 0x00 19. " SPIS627 ,SPI Status Bit 627" "Low,High" bitfld.long 0x00 18. " SPIS626 ,SPI Status Bit 626" "Low,High" bitfld.long 0x00 17. " SPIS625 ,SPI Status Bit 625" "Low,High" textline " " bitfld.long 0x00 16. " SPIS624 ,SPI Status Bit 624" "Low,High" bitfld.long 0x00 15. " SPIS623 ,SPI Status Bit 623" "Low,High" bitfld.long 0x00 14. " SPIS622 ,SPI Status Bit 622" "Low,High" textline " " bitfld.long 0x00 13. " SPIS621 ,SPI Status Bit 621" "Low,High" bitfld.long 0x00 12. " SPIS620 ,SPI Status Bit 620" "Low,High" bitfld.long 0x00 11. " SPIS619 ,SPI Status Bit 619" "Low,High" textline " " bitfld.long 0x00 10. " SPIS618 ,SPI Status Bit 618" "Low,High" bitfld.long 0x00 9. " SPIS617 ,SPI Status Bit 617" "Low,High" bitfld.long 0x00 8. " SPIS616 ,SPI Status Bit 616" "Low,High" textline " " bitfld.long 0x00 7. " SPIS615 ,SPI Status Bit 615" "Low,High" bitfld.long 0x00 6. " SPIS614 ,SPI Status Bit 614" "Low,High" bitfld.long 0x00 5. " SPIS613 ,SPI Status Bit 613" "Low,High" textline " " bitfld.long 0x00 4. " SPIS612 ,SPI Status Bit 612" "Low,High" bitfld.long 0x00 3. " SPIS611 ,SPI Status Bit 611" "Low,High" bitfld.long 0x00 2. " SPIS610 ,SPI Status Bit 610" "Low,High" textline " " bitfld.long 0x00 1. " SPIS609 ,SPI Status Bit 609" "Low,High" bitfld.long 0x00 0. " SPIS608 ,SPI Status Bit 608" "Low,High" else hgroup.long 0xC0CC++0x03 hide.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) rgroup.long 0xC0D0++0x03 line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" bitfld.long 0x00 31. " SPIS671 ,SPI Status Bit 671" "Low,High" bitfld.long 0x00 30. " SPIS670 ,SPI Status Bit 670" "Low,High" bitfld.long 0x00 29. " SPIS669 ,SPI Status Bit 669" "Low,High" textline " " bitfld.long 0x00 28. " SPIS668 ,SPI Status Bit 668" "Low,High" bitfld.long 0x00 27. " SPIS667 ,SPI Status Bit 667" "Low,High" bitfld.long 0x00 26. " SPIS666 ,SPI Status Bit 666" "Low,High" textline " " bitfld.long 0x00 25. " SPIS665 ,SPI Status Bit 665" "Low,High" bitfld.long 0x00 24. " SPIS664 ,SPI Status Bit 664" "Low,High" bitfld.long 0x00 23. " SPIS663 ,SPI Status Bit 663" "Low,High" textline " " bitfld.long 0x00 22. " SPIS662 ,SPI Status Bit 662" "Low,High" bitfld.long 0x00 21. " SPIS661 ,SPI Status Bit 661" "Low,High" bitfld.long 0x00 20. " SPIS660 ,SPI Status Bit 660" "Low,High" textline " " bitfld.long 0x00 19. " SPIS659 ,SPI Status Bit 659" "Low,High" bitfld.long 0x00 18. " SPIS658 ,SPI Status Bit 658" "Low,High" bitfld.long 0x00 17. " SPIS657 ,SPI Status Bit 657" "Low,High" textline " " bitfld.long 0x00 16. " SPIS656 ,SPI Status Bit 656" "Low,High" bitfld.long 0x00 15. " SPIS655 ,SPI Status Bit 655" "Low,High" bitfld.long 0x00 14. " SPIS654 ,SPI Status Bit 654" "Low,High" textline " " bitfld.long 0x00 13. " SPIS653 ,SPI Status Bit 653" "Low,High" bitfld.long 0x00 12. " SPIS652 ,SPI Status Bit 652" "Low,High" bitfld.long 0x00 11. " SPIS651 ,SPI Status Bit 651" "Low,High" textline " " bitfld.long 0x00 10. " SPIS650 ,SPI Status Bit 650" "Low,High" bitfld.long 0x00 9. " SPIS649 ,SPI Status Bit 649" "Low,High" bitfld.long 0x00 8. " SPIS648 ,SPI Status Bit 648" "Low,High" textline " " bitfld.long 0x00 7. " SPIS647 ,SPI Status Bit 647" "Low,High" bitfld.long 0x00 6. " SPIS646 ,SPI Status Bit 646" "Low,High" bitfld.long 0x00 5. " SPIS645 ,SPI Status Bit 645" "Low,High" textline " " bitfld.long 0x00 4. " SPIS644 ,SPI Status Bit 644" "Low,High" bitfld.long 0x00 3. " SPIS643 ,SPI Status Bit 643" "Low,High" bitfld.long 0x00 2. " SPIS642 ,SPI Status Bit 642" "Low,High" textline " " bitfld.long 0x00 1. " SPIS641 ,SPI Status Bit 641" "Low,High" bitfld.long 0x00 0. " SPIS640 ,SPI Status Bit 640" "Low,High" else hgroup.long 0xC0D0++0x03 hide.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) rgroup.long 0xC0D4++0x03 line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" bitfld.long 0x00 31. " SPIS703 ,SPI Status Bit 703" "Low,High" bitfld.long 0x00 30. " SPIS702 ,SPI Status Bit 702" "Low,High" bitfld.long 0x00 29. " SPIS701 ,SPI Status Bit 701" "Low,High" textline " " bitfld.long 0x00 28. " SPIS700 ,SPI Status Bit 700" "Low,High" bitfld.long 0x00 27. " SPIS699 ,SPI Status Bit 699" "Low,High" bitfld.long 0x00 26. " SPIS698 ,SPI Status Bit 698" "Low,High" textline " " bitfld.long 0x00 25. " SPIS697 ,SPI Status Bit 697" "Low,High" bitfld.long 0x00 24. " SPIS696 ,SPI Status Bit 696" "Low,High" bitfld.long 0x00 23. " SPIS695 ,SPI Status Bit 695" "Low,High" textline " " bitfld.long 0x00 22. " SPIS694 ,SPI Status Bit 694" "Low,High" bitfld.long 0x00 21. " SPIS693 ,SPI Status Bit 693" "Low,High" bitfld.long 0x00 20. " SPIS692 ,SPI Status Bit 692" "Low,High" textline " " bitfld.long 0x00 19. " SPIS691 ,SPI Status Bit 691" "Low,High" bitfld.long 0x00 18. " SPIS690 ,SPI Status Bit 690" "Low,High" bitfld.long 0x00 17. " SPIS689 ,SPI Status Bit 689" "Low,High" textline " " bitfld.long 0x00 16. " SPIS688 ,SPI Status Bit 688" "Low,High" bitfld.long 0x00 15. " SPIS687 ,SPI Status Bit 687" "Low,High" bitfld.long 0x00 14. " SPIS686 ,SPI Status Bit 686" "Low,High" textline " " bitfld.long 0x00 13. " SPIS685 ,SPI Status Bit 685" "Low,High" bitfld.long 0x00 12. " SPIS684 ,SPI Status Bit 684" "Low,High" bitfld.long 0x00 11. " SPIS683 ,SPI Status Bit 683" "Low,High" textline " " bitfld.long 0x00 10. " SPIS682 ,SPI Status Bit 682" "Low,High" bitfld.long 0x00 9. " SPIS681 ,SPI Status Bit 681" "Low,High" bitfld.long 0x00 8. " SPIS680 ,SPI Status Bit 680" "Low,High" textline " " bitfld.long 0x00 7. " SPIS679 ,SPI Status Bit 679" "Low,High" bitfld.long 0x00 6. " SPIS678 ,SPI Status Bit 678" "Low,High" bitfld.long 0x00 5. " SPIS677 ,SPI Status Bit 677" "Low,High" textline " " bitfld.long 0x00 4. " SPIS676 ,SPI Status Bit 676" "Low,High" bitfld.long 0x00 3. " SPIS675 ,SPI Status Bit 675" "Low,High" bitfld.long 0x00 2. " SPIS674 ,SPI Status Bit 674" "Low,High" textline " " bitfld.long 0x00 1. " SPIS673 ,SPI Status Bit 673" "Low,High" bitfld.long 0x00 0. " SPIS672 ,SPI Status Bit 672" "Low,High" else hgroup.long 0xC0D4++0x03 hide.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) rgroup.long 0xC0D8++0x03 line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" bitfld.long 0x00 31. " SPIS735 ,SPI Status Bit 735" "Low,High" bitfld.long 0x00 30. " SPIS734 ,SPI Status Bit 734" "Low,High" bitfld.long 0x00 29. " SPIS733 ,SPI Status Bit 733" "Low,High" textline " " bitfld.long 0x00 28. " SPIS732 ,SPI Status Bit 732" "Low,High" bitfld.long 0x00 27. " SPIS731 ,SPI Status Bit 731" "Low,High" bitfld.long 0x00 26. " SPIS730 ,SPI Status Bit 730" "Low,High" textline " " bitfld.long 0x00 25. " SPIS729 ,SPI Status Bit 729" "Low,High" bitfld.long 0x00 24. " SPIS728 ,SPI Status Bit 728" "Low,High" bitfld.long 0x00 23. " SPIS727 ,SPI Status Bit 727" "Low,High" textline " " bitfld.long 0x00 22. " SPIS726 ,SPI Status Bit 726" "Low,High" bitfld.long 0x00 21. " SPIS725 ,SPI Status Bit 725" "Low,High" bitfld.long 0x00 20. " SPIS724 ,SPI Status Bit 724" "Low,High" textline " " bitfld.long 0x00 19. " SPIS723 ,SPI Status Bit 723" "Low,High" bitfld.long 0x00 18. " SPIS722 ,SPI Status Bit 722" "Low,High" bitfld.long 0x00 17. " SPIS721 ,SPI Status Bit 721" "Low,High" textline " " bitfld.long 0x00 16. " SPIS720 ,SPI Status Bit 720" "Low,High" bitfld.long 0x00 15. " SPIS719 ,SPI Status Bit 719" "Low,High" bitfld.long 0x00 14. " SPIS718 ,SPI Status Bit 718" "Low,High" textline " " bitfld.long 0x00 13. " SPIS717 ,SPI Status Bit 717" "Low,High" bitfld.long 0x00 12. " SPIS716 ,SPI Status Bit 716" "Low,High" bitfld.long 0x00 11. " SPIS715 ,SPI Status Bit 715" "Low,High" textline " " bitfld.long 0x00 10. " SPIS714 ,SPI Status Bit 714" "Low,High" bitfld.long 0x00 9. " SPIS713 ,SPI Status Bit 713" "Low,High" bitfld.long 0x00 8. " SPIS712 ,SPI Status Bit 712" "Low,High" textline " " bitfld.long 0x00 7. " SPIS711 ,SPI Status Bit 711" "Low,High" bitfld.long 0x00 6. " SPIS710 ,SPI Status Bit 710" "Low,High" bitfld.long 0x00 5. " SPIS709 ,SPI Status Bit 709" "Low,High" textline " " bitfld.long 0x00 4. " SPIS708 ,SPI Status Bit 708" "Low,High" bitfld.long 0x00 3. " SPIS707 ,SPI Status Bit 707" "Low,High" bitfld.long 0x00 2. " SPIS706 ,SPI Status Bit 706" "Low,High" textline " " bitfld.long 0x00 1. " SPIS705 ,SPI Status Bit 705" "Low,High" bitfld.long 0x00 0. " SPIS704 ,SPI Status Bit 704" "Low,High" else hgroup.long 0xC0D8++0x03 hide.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) rgroup.long 0xC0DC++0x03 line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" bitfld.long 0x00 31. " SPIS767 ,SPI Status Bit 767" "Low,High" bitfld.long 0x00 30. " SPIS766 ,SPI Status Bit 766" "Low,High" bitfld.long 0x00 29. " SPIS765 ,SPI Status Bit 765" "Low,High" textline " " bitfld.long 0x00 28. " SPIS764 ,SPI Status Bit 764" "Low,High" bitfld.long 0x00 27. " SPIS763 ,SPI Status Bit 763" "Low,High" bitfld.long 0x00 26. " SPIS762 ,SPI Status Bit 762" "Low,High" textline " " bitfld.long 0x00 25. " SPIS761 ,SPI Status Bit 761" "Low,High" bitfld.long 0x00 24. " SPIS760 ,SPI Status Bit 760" "Low,High" bitfld.long 0x00 23. " SPIS759 ,SPI Status Bit 759" "Low,High" textline " " bitfld.long 0x00 22. " SPIS758 ,SPI Status Bit 758" "Low,High" bitfld.long 0x00 21. " SPIS757 ,SPI Status Bit 757" "Low,High" bitfld.long 0x00 20. " SPIS756 ,SPI Status Bit 756" "Low,High" textline " " bitfld.long 0x00 19. " SPIS755 ,SPI Status Bit 755" "Low,High" bitfld.long 0x00 18. " SPIS754 ,SPI Status Bit 754" "Low,High" bitfld.long 0x00 17. " SPIS753 ,SPI Status Bit 753" "Low,High" textline " " bitfld.long 0x00 16. " SPIS752 ,SPI Status Bit 752" "Low,High" bitfld.long 0x00 15. " SPIS751 ,SPI Status Bit 751" "Low,High" bitfld.long 0x00 14. " SPIS750 ,SPI Status Bit 750" "Low,High" textline " " bitfld.long 0x00 13. " SPIS749 ,SPI Status Bit 749" "Low,High" bitfld.long 0x00 12. " SPIS748 ,SPI Status Bit 748" "Low,High" bitfld.long 0x00 11. " SPIS747 ,SPI Status Bit 747" "Low,High" textline " " bitfld.long 0x00 10. " SPIS746 ,SPI Status Bit 746" "Low,High" bitfld.long 0x00 9. " SPIS745 ,SPI Status Bit 745" "Low,High" bitfld.long 0x00 8. " SPIS744 ,SPI Status Bit 744" "Low,High" textline " " bitfld.long 0x00 7. " SPIS743 ,SPI Status Bit 743" "Low,High" bitfld.long 0x00 6. " SPIS742 ,SPI Status Bit 742" "Low,High" bitfld.long 0x00 5. " SPIS741 ,SPI Status Bit 741" "Low,High" textline " " bitfld.long 0x00 4. " SPIS740 ,SPI Status Bit 740" "Low,High" bitfld.long 0x00 3. " SPIS739 ,SPI Status Bit 739" "Low,High" bitfld.long 0x00 2. " SPIS738 ,SPI Status Bit 738" "Low,High" textline " " bitfld.long 0x00 1. " SPIS737 ,SPI Status Bit 737" "Low,High" bitfld.long 0x00 0. " SPIS736 ,SPI Status Bit 736" "Low,High" else hgroup.long 0xC0DC++0x03 hide.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) rgroup.long 0xC0E0++0x03 line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" bitfld.long 0x00 31. " SPIS799 ,SPI Status Bit 799" "Low,High" bitfld.long 0x00 30. " SPIS798 ,SPI Status Bit 798" "Low,High" bitfld.long 0x00 29. " SPIS797 ,SPI Status Bit 797" "Low,High" textline " " bitfld.long 0x00 28. " SPIS796 ,SPI Status Bit 796" "Low,High" bitfld.long 0x00 27. " SPIS795 ,SPI Status Bit 795" "Low,High" bitfld.long 0x00 26. " SPIS794 ,SPI Status Bit 794" "Low,High" textline " " bitfld.long 0x00 25. " SPIS793 ,SPI Status Bit 793" "Low,High" bitfld.long 0x00 24. " SPIS792 ,SPI Status Bit 792" "Low,High" bitfld.long 0x00 23. " SPIS791 ,SPI Status Bit 791" "Low,High" textline " " bitfld.long 0x00 22. " SPIS790 ,SPI Status Bit 790" "Low,High" bitfld.long 0x00 21. " SPIS789 ,SPI Status Bit 789" "Low,High" bitfld.long 0x00 20. " SPIS788 ,SPI Status Bit 788" "Low,High" textline " " bitfld.long 0x00 19. " SPIS787 ,SPI Status Bit 787" "Low,High" bitfld.long 0x00 18. " SPIS786 ,SPI Status Bit 786" "Low,High" bitfld.long 0x00 17. " SPIS785 ,SPI Status Bit 785" "Low,High" textline " " bitfld.long 0x00 16. " SPIS784 ,SPI Status Bit 784" "Low,High" bitfld.long 0x00 15. " SPIS783 ,SPI Status Bit 783" "Low,High" bitfld.long 0x00 14. " SPIS782 ,SPI Status Bit 782" "Low,High" textline " " bitfld.long 0x00 13. " SPIS781 ,SPI Status Bit 781" "Low,High" bitfld.long 0x00 12. " SPIS780 ,SPI Status Bit 780" "Low,High" bitfld.long 0x00 11. " SPIS779 ,SPI Status Bit 779" "Low,High" textline " " bitfld.long 0x00 10. " SPIS778 ,SPI Status Bit 778" "Low,High" bitfld.long 0x00 9. " SPIS777 ,SPI Status Bit 777" "Low,High" bitfld.long 0x00 8. " SPIS776 ,SPI Status Bit 776" "Low,High" textline " " bitfld.long 0x00 7. " SPIS775 ,SPI Status Bit 775" "Low,High" bitfld.long 0x00 6. " SPIS774 ,SPI Status Bit 774" "Low,High" bitfld.long 0x00 5. " SPIS773 ,SPI Status Bit 773" "Low,High" textline " " bitfld.long 0x00 4. " SPIS772 ,SPI Status Bit 772" "Low,High" bitfld.long 0x00 3. " SPIS771 ,SPI Status Bit 771" "Low,High" bitfld.long 0x00 2. " SPIS770 ,SPI Status Bit 770" "Low,High" textline " " bitfld.long 0x00 1. " SPIS769 ,SPI Status Bit 769" "Low,High" bitfld.long 0x00 0. " SPIS768 ,SPI Status Bit 768" "Low,High" else hgroup.long 0xC0E0++0x03 hide.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) rgroup.long 0xC0E4++0x03 line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" bitfld.long 0x00 31. " SPIS831 ,SPI Status Bit 831" "Low,High" bitfld.long 0x00 30. " SPIS830 ,SPI Status Bit 830" "Low,High" bitfld.long 0x00 29. " SPIS829 ,SPI Status Bit 829" "Low,High" textline " " bitfld.long 0x00 28. " SPIS828 ,SPI Status Bit 828" "Low,High" bitfld.long 0x00 27. " SPIS827 ,SPI Status Bit 827" "Low,High" bitfld.long 0x00 26. " SPIS826 ,SPI Status Bit 826" "Low,High" textline " " bitfld.long 0x00 25. " SPIS825 ,SPI Status Bit 825" "Low,High" bitfld.long 0x00 24. " SPIS824 ,SPI Status Bit 824" "Low,High" bitfld.long 0x00 23. " SPIS823 ,SPI Status Bit 823" "Low,High" textline " " bitfld.long 0x00 22. " SPIS822 ,SPI Status Bit 822" "Low,High" bitfld.long 0x00 21. " SPIS821 ,SPI Status Bit 821" "Low,High" bitfld.long 0x00 20. " SPIS820 ,SPI Status Bit 820" "Low,High" textline " " bitfld.long 0x00 19. " SPIS819 ,SPI Status Bit 819" "Low,High" bitfld.long 0x00 18. " SPIS818 ,SPI Status Bit 818" "Low,High" bitfld.long 0x00 17. " SPIS817 ,SPI Status Bit 817" "Low,High" textline " " bitfld.long 0x00 16. " SPIS816 ,SPI Status Bit 816" "Low,High" bitfld.long 0x00 15. " SPIS815 ,SPI Status Bit 815" "Low,High" bitfld.long 0x00 14. " SPIS814 ,SPI Status Bit 814" "Low,High" textline " " bitfld.long 0x00 13. " SPIS813 ,SPI Status Bit 813" "Low,High" bitfld.long 0x00 12. " SPIS812 ,SPI Status Bit 812" "Low,High" bitfld.long 0x00 11. " SPIS811 ,SPI Status Bit 811" "Low,High" textline " " bitfld.long 0x00 10. " SPIS810 ,SPI Status Bit 810" "Low,High" bitfld.long 0x00 9. " SPIS809 ,SPI Status Bit 809" "Low,High" bitfld.long 0x00 8. " SPIS808 ,SPI Status Bit 808" "Low,High" textline " " bitfld.long 0x00 7. " SPIS807 ,SPI Status Bit 807" "Low,High" bitfld.long 0x00 6. " SPIS806 ,SPI Status Bit 806" "Low,High" bitfld.long 0x00 5. " SPIS805 ,SPI Status Bit 805" "Low,High" textline " " bitfld.long 0x00 4. " SPIS804 ,SPI Status Bit 804" "Low,High" bitfld.long 0x00 3. " SPIS803 ,SPI Status Bit 803" "Low,High" bitfld.long 0x00 2. " SPIS802 ,SPI Status Bit 802" "Low,High" textline " " bitfld.long 0x00 1. " SPIS801 ,SPI Status Bit 801" "Low,High" bitfld.long 0x00 0. " SPIS800 ,SPI Status Bit 800" "Low,High" else hgroup.long 0xC0E4++0x03 hide.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) rgroup.long 0xC0E8++0x03 line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" bitfld.long 0x00 31. " SPIS863 ,SPI Status Bit 863" "Low,High" bitfld.long 0x00 30. " SPIS862 ,SPI Status Bit 862" "Low,High" bitfld.long 0x00 29. " SPIS861 ,SPI Status Bit 861" "Low,High" textline " " bitfld.long 0x00 28. " SPIS860 ,SPI Status Bit 860" "Low,High" bitfld.long 0x00 27. " SPIS859 ,SPI Status Bit 859" "Low,High" bitfld.long 0x00 26. " SPIS858 ,SPI Status Bit 858" "Low,High" textline " " bitfld.long 0x00 25. " SPIS857 ,SPI Status Bit 857" "Low,High" bitfld.long 0x00 24. " SPIS856 ,SPI Status Bit 856" "Low,High" bitfld.long 0x00 23. " SPIS855 ,SPI Status Bit 855" "Low,High" textline " " bitfld.long 0x00 22. " SPIS854 ,SPI Status Bit 854" "Low,High" bitfld.long 0x00 21. " SPIS853 ,SPI Status Bit 853" "Low,High" bitfld.long 0x00 20. " SPIS852 ,SPI Status Bit 852" "Low,High" textline " " bitfld.long 0x00 19. " SPIS851 ,SPI Status Bit 851" "Low,High" bitfld.long 0x00 18. " SPIS850 ,SPI Status Bit 850" "Low,High" bitfld.long 0x00 17. " SPIS849 ,SPI Status Bit 849" "Low,High" textline " " bitfld.long 0x00 16. " SPIS848 ,SPI Status Bit 848" "Low,High" bitfld.long 0x00 15. " SPIS847 ,SPI Status Bit 847" "Low,High" bitfld.long 0x00 14. " SPIS846 ,SPI Status Bit 846" "Low,High" textline " " bitfld.long 0x00 13. " SPIS845 ,SPI Status Bit 845" "Low,High" bitfld.long 0x00 12. " SPIS844 ,SPI Status Bit 844" "Low,High" bitfld.long 0x00 11. " SPIS843 ,SPI Status Bit 843" "Low,High" textline " " bitfld.long 0x00 10. " SPIS842 ,SPI Status Bit 842" "Low,High" bitfld.long 0x00 9. " SPIS841 ,SPI Status Bit 841" "Low,High" bitfld.long 0x00 8. " SPIS840 ,SPI Status Bit 840" "Low,High" textline " " bitfld.long 0x00 7. " SPIS839 ,SPI Status Bit 839" "Low,High" bitfld.long 0x00 6. " SPIS838 ,SPI Status Bit 838" "Low,High" bitfld.long 0x00 5. " SPIS837 ,SPI Status Bit 837" "Low,High" textline " " bitfld.long 0x00 4. " SPIS836 ,SPI Status Bit 836" "Low,High" bitfld.long 0x00 3. " SPIS835 ,SPI Status Bit 835" "Low,High" bitfld.long 0x00 2. " SPIS834 ,SPI Status Bit 834" "Low,High" textline " " bitfld.long 0x00 1. " SPIS833 ,SPI Status Bit 833" "Low,High" bitfld.long 0x00 0. " SPIS832 ,SPI Status Bit 832" "Low,High" else hgroup.long 0xC0E8++0x03 hide.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) rgroup.long 0xC0EC++0x03 line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" bitfld.long 0x00 31. " SPIS895 ,SPI Status Bit 895" "Low,High" bitfld.long 0x00 30. " SPIS894 ,SPI Status Bit 894" "Low,High" bitfld.long 0x00 29. " SPIS893 ,SPI Status Bit 893" "Low,High" textline " " bitfld.long 0x00 28. " SPIS892 ,SPI Status Bit 892" "Low,High" bitfld.long 0x00 27. " SPIS891 ,SPI Status Bit 891" "Low,High" bitfld.long 0x00 26. " SPIS890 ,SPI Status Bit 890" "Low,High" textline " " bitfld.long 0x00 25. " SPIS889 ,SPI Status Bit 889" "Low,High" bitfld.long 0x00 24. " SPIS888 ,SPI Status Bit 888" "Low,High" bitfld.long 0x00 23. " SPIS887 ,SPI Status Bit 887" "Low,High" textline " " bitfld.long 0x00 22. " SPIS886 ,SPI Status Bit 886" "Low,High" bitfld.long 0x00 21. " SPIS885 ,SPI Status Bit 885" "Low,High" bitfld.long 0x00 20. " SPIS884 ,SPI Status Bit 884" "Low,High" textline " " bitfld.long 0x00 19. " SPIS883 ,SPI Status Bit 883" "Low,High" bitfld.long 0x00 18. " SPIS882 ,SPI Status Bit 882" "Low,High" bitfld.long 0x00 17. " SPIS881 ,SPI Status Bit 881" "Low,High" textline " " bitfld.long 0x00 16. " SPIS880 ,SPI Status Bit 880" "Low,High" bitfld.long 0x00 15. " SPIS879 ,SPI Status Bit 879" "Low,High" bitfld.long 0x00 14. " SPIS878 ,SPI Status Bit 878" "Low,High" textline " " bitfld.long 0x00 13. " SPIS877 ,SPI Status Bit 877" "Low,High" bitfld.long 0x00 12. " SPIS876 ,SPI Status Bit 876" "Low,High" bitfld.long 0x00 11. " SPIS875 ,SPI Status Bit 875" "Low,High" textline " " bitfld.long 0x00 10. " SPIS874 ,SPI Status Bit 874" "Low,High" bitfld.long 0x00 9. " SPIS873 ,SPI Status Bit 873" "Low,High" bitfld.long 0x00 8. " SPIS872 ,SPI Status Bit 872" "Low,High" textline " " bitfld.long 0x00 7. " SPIS871 ,SPI Status Bit 871" "Low,High" bitfld.long 0x00 6. " SPIS870 ,SPI Status Bit 870" "Low,High" bitfld.long 0x00 5. " SPIS869 ,SPI Status Bit 869" "Low,High" textline " " bitfld.long 0x00 4. " SPIS868 ,SPI Status Bit 868" "Low,High" bitfld.long 0x00 3. " SPIS867 ,SPI Status Bit 867" "Low,High" bitfld.long 0x00 2. " SPIS866 ,SPI Status Bit 866" "Low,High" textline " " bitfld.long 0x00 1. " SPIS865 ,SPI Status Bit 865" "Low,High" bitfld.long 0x00 0. " SPIS864 ,SPI Status Bit 864" "Low,High" else hgroup.long 0xC0EC++0x03 hide.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) rgroup.long 0xC0F0++0x03 line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" bitfld.long 0x00 31. " SPIS927 ,SPI Status Bit 927" "Low,High" bitfld.long 0x00 30. " SPIS926 ,SPI Status Bit 926" "Low,High" bitfld.long 0x00 29. " SPIS925 ,SPI Status Bit 925" "Low,High" textline " " bitfld.long 0x00 28. " SPIS924 ,SPI Status Bit 924" "Low,High" bitfld.long 0x00 27. " SPIS923 ,SPI Status Bit 923" "Low,High" bitfld.long 0x00 26. " SPIS922 ,SPI Status Bit 922" "Low,High" textline " " bitfld.long 0x00 25. " SPIS921 ,SPI Status Bit 921" "Low,High" bitfld.long 0x00 24. " SPIS920 ,SPI Status Bit 920" "Low,High" bitfld.long 0x00 23. " SPIS919 ,SPI Status Bit 919" "Low,High" textline " " bitfld.long 0x00 22. " SPIS918 ,SPI Status Bit 918" "Low,High" bitfld.long 0x00 21. " SPIS917 ,SPI Status Bit 917" "Low,High" bitfld.long 0x00 20. " SPIS916 ,SPI Status Bit 916" "Low,High" textline " " bitfld.long 0x00 19. " SPIS915 ,SPI Status Bit 915" "Low,High" bitfld.long 0x00 18. " SPIS914 ,SPI Status Bit 914" "Low,High" bitfld.long 0x00 17. " SPIS913 ,SPI Status Bit 913" "Low,High" textline " " bitfld.long 0x00 16. " SPIS912 ,SPI Status Bit 912" "Low,High" bitfld.long 0x00 15. " SPIS911 ,SPI Status Bit 911" "Low,High" bitfld.long 0x00 14. " SPIS910 ,SPI Status Bit 910" "Low,High" textline " " bitfld.long 0x00 13. " SPIS909 ,SPI Status Bit 909" "Low,High" bitfld.long 0x00 12. " SPIS908 ,SPI Status Bit 908" "Low,High" bitfld.long 0x00 11. " SPIS907 ,SPI Status Bit 907" "Low,High" textline " " bitfld.long 0x00 10. " SPIS906 ,SPI Status Bit 906" "Low,High" bitfld.long 0x00 9. " SPIS905 ,SPI Status Bit 905" "Low,High" bitfld.long 0x00 8. " SPIS904 ,SPI Status Bit 904" "Low,High" textline " " bitfld.long 0x00 7. " SPIS903 ,SPI Status Bit 903" "Low,High" bitfld.long 0x00 6. " SPIS902 ,SPI Status Bit 902" "Low,High" bitfld.long 0x00 5. " SPIS901 ,SPI Status Bit 901" "Low,High" textline " " bitfld.long 0x00 4. " SPIS900 ,SPI Status Bit 900" "Low,High" bitfld.long 0x00 3. " SPIS899 ,SPI Status Bit 899" "Low,High" bitfld.long 0x00 2. " SPIS898 ,SPI Status Bit 898" "Low,High" textline " " bitfld.long 0x00 1. " SPIS897 ,SPI Status Bit 897" "Low,High" bitfld.long 0x00 0. " SPIS896 ,SPI Status Bit 896" "Low,High" else hgroup.long 0xC0F0++0x03 hide.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) rgroup.long 0xC0F4++0x03 line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" bitfld.long 0x00 31. " SPIS959 ,SPI Status Bit 959" "Low,High" bitfld.long 0x00 30. " SPIS958 ,SPI Status Bit 958" "Low,High" bitfld.long 0x00 29. " SPIS957 ,SPI Status Bit 957" "Low,High" textline " " bitfld.long 0x00 28. " SPIS956 ,SPI Status Bit 956" "Low,High" bitfld.long 0x00 27. " SPIS955 ,SPI Status Bit 955" "Low,High" bitfld.long 0x00 26. " SPIS954 ,SPI Status Bit 954" "Low,High" textline " " bitfld.long 0x00 25. " SPIS953 ,SPI Status Bit 953" "Low,High" bitfld.long 0x00 24. " SPIS952 ,SPI Status Bit 952" "Low,High" bitfld.long 0x00 23. " SPIS951 ,SPI Status Bit 951" "Low,High" textline " " bitfld.long 0x00 22. " SPIS950 ,SPI Status Bit 950" "Low,High" bitfld.long 0x00 21. " SPIS949 ,SPI Status Bit 949" "Low,High" bitfld.long 0x00 20. " SPIS948 ,SPI Status Bit 948" "Low,High" textline " " bitfld.long 0x00 19. " SPIS947 ,SPI Status Bit 947" "Low,High" bitfld.long 0x00 18. " SPIS946 ,SPI Status Bit 946" "Low,High" bitfld.long 0x00 17. " SPIS945 ,SPI Status Bit 945" "Low,High" textline " " bitfld.long 0x00 16. " SPIS944 ,SPI Status Bit 944" "Low,High" bitfld.long 0x00 15. " SPIS943 ,SPI Status Bit 943" "Low,High" bitfld.long 0x00 14. " SPIS942 ,SPI Status Bit 942" "Low,High" textline " " bitfld.long 0x00 13. " SPIS941 ,SPI Status Bit 941" "Low,High" bitfld.long 0x00 12. " SPIS940 ,SPI Status Bit 940" "Low,High" bitfld.long 0x00 11. " SPIS939 ,SPI Status Bit 939" "Low,High" textline " " bitfld.long 0x00 10. " SPIS938 ,SPI Status Bit 938" "Low,High" bitfld.long 0x00 9. " SPIS937 ,SPI Status Bit 937" "Low,High" bitfld.long 0x00 8. " SPIS936 ,SPI Status Bit 936" "Low,High" textline " " bitfld.long 0x00 7. " SPIS935 ,SPI Status Bit 935" "Low,High" bitfld.long 0x00 6. " SPIS934 ,SPI Status Bit 934" "Low,High" bitfld.long 0x00 5. " SPIS933 ,SPI Status Bit 933" "Low,High" textline " " bitfld.long 0x00 4. " SPIS932 ,SPI Status Bit 932" "Low,High" bitfld.long 0x00 3. " SPIS931 ,SPI Status Bit 931" "Low,High" bitfld.long 0x00 2. " SPIS930 ,SPI Status Bit 930" "Low,High" textline " " bitfld.long 0x00 1. " SPIS929 ,SPI Status Bit 929" "Low,High" bitfld.long 0x00 0. " SPIS928 ,SPI Status Bit 928" "Low,High" else hgroup.long 0xC0F4++0x03 hide.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) rgroup.long 0xC0F8++0x03 line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" bitfld.long 0x00 31. " SPIS991 ,SPI Status Bit 991" "Low,High" bitfld.long 0x00 30. " SPIS990 ,SPI Status Bit 990" "Low,High" bitfld.long 0x00 29. " SPIS989 ,SPI Status Bit 989" "Low,High" textline " " bitfld.long 0x00 28. " SPIS988 ,SPI Status Bit 988" "Low,High" bitfld.long 0x00 27. " SPIS987 ,SPI Status Bit 987" "Low,High" bitfld.long 0x00 26. " SPIS986 ,SPI Status Bit 986" "Low,High" textline " " bitfld.long 0x00 25. " SPIS985 ,SPI Status Bit 985" "Low,High" bitfld.long 0x00 24. " SPIS984 ,SPI Status Bit 984" "Low,High" bitfld.long 0x00 23. " SPIS983 ,SPI Status Bit 983" "Low,High" textline " " bitfld.long 0x00 22. " SPIS982 ,SPI Status Bit 982" "Low,High" bitfld.long 0x00 21. " SPIS981 ,SPI Status Bit 981" "Low,High" bitfld.long 0x00 20. " SPIS980 ,SPI Status Bit 980" "Low,High" textline " " bitfld.long 0x00 19. " SPIS979 ,SPI Status Bit 979" "Low,High" bitfld.long 0x00 18. " SPIS978 ,SPI Status Bit 978" "Low,High" bitfld.long 0x00 17. " SPIS977 ,SPI Status Bit 977" "Low,High" textline " " bitfld.long 0x00 16. " SPIS976 ,SPI Status Bit 976" "Low,High" bitfld.long 0x00 15. " SPIS975 ,SPI Status Bit 975" "Low,High" bitfld.long 0x00 14. " SPIS974 ,SPI Status Bit 974" "Low,High" textline " " bitfld.long 0x00 13. " SPIS973 ,SPI Status Bit 973" "Low,High" bitfld.long 0x00 12. " SPIS972 ,SPI Status Bit 972" "Low,High" bitfld.long 0x00 11. " SPIS971 ,SPI Status Bit 971" "Low,High" textline " " bitfld.long 0x00 10. " SPIS970 ,SPI Status Bit 970" "Low,High" bitfld.long 0x00 9. " SPIS969 ,SPI Status Bit 969" "Low,High" bitfld.long 0x00 8. " SPIS968 ,SPI Status Bit 968" "Low,High" textline " " bitfld.long 0x00 7. " SPIS967 ,SPI Status Bit 967" "Low,High" bitfld.long 0x00 6. " SPIS966 ,SPI Status Bit 966" "Low,High" bitfld.long 0x00 5. " SPIS965 ,SPI Status Bit 965" "Low,High" textline " " bitfld.long 0x00 4. " SPIS964 ,SPI Status Bit 964" "Low,High" bitfld.long 0x00 3. " SPIS963 ,SPI Status Bit 963" "Low,High" bitfld.long 0x00 2. " SPIS962 ,SPI Status Bit 962" "Low,High" textline " " bitfld.long 0x00 1. " SPIS961 ,SPI Status Bit 961" "Low,High" bitfld.long 0x00 0. " SPIS960 ,SPI Status Bit 960" "Low,High" else hgroup.long 0xC0F8++0x03 hide.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" endif tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.long 0xFFE0++0x03 line.long 0x00 "GICD_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]" rgroup.long 0xFFE4++0x03 line.long 0x00 "GICD_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFE8++0x03 line.long 0x00 "GICD_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..." bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Not Used,Used" bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" rgroup.long 0xFFEC++0x03 line.long 0x00 "GICD_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFD0++0x03 line.long 0x00 "GICD_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFFD4++0x03 hide.long 0x00 "GICD_PIDR5,Peripheral ID5 Register" hgroup.long 0xFFD8++0x03 hide.long 0x00 "GICD_PIDR6,Peripheral ID6 Register" hgroup.long 0xFFDC++0x03 hide.long 0x00 "GICD_PIDR7,Peripheral ID7 Register" rgroup.long 0xFFF0++0x03 line.long 0x00 "GICD_CIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF4++0x03 line.long 0x00 "GICD_CIDR1,Component ID1 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF8++0x03 line.long 0x00 "GICD_CIDR2,Component ID2 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFFC++0x03 line.long 0x00 "GICD_CIDR3,Component ID3 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" tree.end tree.end width 0x0B base (COMP.BASE("GICD",-1.)+0x20000) width 24. tree "Interrupt Translation Service" group.long 0x00++0x03 line.long 0x00 "GITS_CTLR,ITS Control Register" rbitfld.long 0x00 31. " QUIESCENT ,Indicates completion of all ITS operations" "Not quiescent,Quiescent" bitfld.long 0x00 0. " ENABLED ,Controls whether the ITS is enabled" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "GITS_IIDR,ITS Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" if (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0x1000000000)==0x1000000000)&&(((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0xFF000000)!=0x00) rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " bitfld.quad 0x00 32.--35. " CIDBITS ,Number of Collection ID bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" textline " " bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" textline " " bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 2. " CCT ,Cumulative Collection Tables" "0,1" elif (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0x1000000000)==0x1000000000) rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " bitfld.quad 0x00 32.--35. " CIDBITS ,Number of Collection ID bits minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" textline " " bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" textline " " bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0xFF000000)!=0x00) rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" textline " " bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.quad 0x00 2. " CCT ,Cumulative Collection Tables" "0,1" else rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" textline " " bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.quad 0x80++0x07 line.quad 0x00 "GITS_CBASER,The command queue control register" bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the command queue" "Not allocated,Allocated" bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the command queue" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" textline " " bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the command queue" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" hexmask.quad 0x00 12.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:12] of the base physical address of the command queue" textline " " bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the command queue" "Non-shareable,Inner Shareable,Outer Shareable,?..." hexmask.quad.byte 0x00 0.--7. 1. " SIZE ,The number of 4KB pages of physical memory allocated to the command queue minus one" group.quad 0x88++0x7 line.quad 0x00 "GITS_CWRITER,The command queue write pointer" hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET ,Bits [19:5] of the offset from GITS_CBASER" bitfld.quad 0x00 0. " RETRY ,Restarts the processing of commands by the ITS if it stalled because of a command error" "No effect,Restarted" group.quad 0x90++0x07 line.quad 0x00 "GITS_CREADR,The command queue read pointer" hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET ,Bits [19:5] of the offset from GITS_CBASER" bitfld.quad 0x00 0. " STALLED ,Reports whether the processing of commands is stalled because of a command error" "Not stalled,Stalled" if (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0100))&0x700000000000000)==0x00) group.quad 0x100++0x07 line.quad 0x00 "GITS_BASER0,ITS table control register" bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated" bitfld.quad 0x00 62. " INDIRECT ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level" textline " " bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" rbitfld.quad 0x00 56.--58. " TYPE ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..." textline " " bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" rbitfld.quad 0x00 48.--52. " ENTRY_SIZE ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.quad 0x00 12.--47. 1. " PHYSICAL_ADDRESS ,Physical Address" bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..." textline " " bitfld.quad 0x00 8.--9. " PAGE_SIZE ,The size of page that the translation table uses" "4KB,16KB,64KB,?..." else group.quad 0x100++0x07 line.quad 0x00 "GITS_BASER0,ITS table control register" bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated" bitfld.quad 0x00 62. " INDIRECT ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level" textline " " bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" rbitfld.quad 0x00 56.--58. " TYPE ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..." textline " " bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" rbitfld.quad 0x00 48.--52. " ENTRY_SIZE ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.quad 0x00 12.--47. 0x10 " PHYSICAL_ADDRESS ,Physical Address" bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..." textline " " bitfld.quad 0x00 8.--9. " PAGE_SIZE ,The size of page that the translation table uses" "4KB,16KB,64KB,?..." hexmask.quad.byte 0x00 0.--7. 1. " SIZE ,The number of pages of physical memory allocated to the table minus one" endif textline " " wgroup.long 0xC000++0x03 line.long 0x00 "GITS_TRKCTLR,Tracking Control Register" bitfld.long 0x00 1. " LPI_TRACK ,Write 0b1 to capture information about the next interrupt that the ITS generated or failed to generate because of misprogramming" "No effect,Capture" bitfld.long 0x00 0. " CACHE_COUNT_RESET ,Write 0b1 to reset the cache hit and miss counters in GITS_TRKICR and GITS_TRKLCR" "No effect,Reset" if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x1F)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 6. " PID_OUT_OF_RANGE ,Indicates that the LPI PID is larger than that allowed by the IDbits field in the GICR_PROPBASER" "0,1" bitfld.long 0x00 5. " TARGET_OUT_OF_RANGE ,Indicates that target collection has not been successfully mapped using MAPC or that the target core does not have LPIs enabled in GICR_CTLR" "0,1" textline " " bitfld.long 0x00 4. " NO_TRANSLATION ,Indicates that no valid MAPI or MAPVI has successfully been performed for this combination of input ID and Device ID" "0,1" bitfld.long 0x00 3. " INPUT_ID_OUT_OF_RANGE ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1" textline " " bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" textline " " bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0xF)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 4. " NO_TRANSLATION ,Indicates that no valid MAPI or MAPVI has successfully been performed for this combination of input ID and Device ID" "0,1" bitfld.long 0x00 3. " INPUT_ID_OUT_OF_RANGE ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1" textline " " bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" textline " " bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 3. " INPUT_ID_OUT_OF_RANGE ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1" bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" textline " " bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x3)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" textline " " bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" else rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x01)==0x01) rgroup.long 0xC008++0x03 line.long 0x00 "GITS_TRKDIDR,Debug Tracked DID Register" hexmask.long.tbyte 0x00 0.--19. 1. " LPI_DID ,The Device ID for the interrupt that was tracked" else hgroup.long 0xC008++0x03 hide.long 0x00 "GITS_TRKDIDR,Debug Tracked DID Register" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7F)==0x01) rgroup.long 0xC00C++0x03 line.long 0x00 "GITS_TRKPIDR,Debug Tracked PID Register" hexmask.long.word 0x00 0.--15. 1. " LPI_PID ,The ID after translation for an interrupt that was tracked and generated an LPI successfully" else hgroup.long 0xC00C++0x03 hide.long 0x00 "GITS_TRKPIDR,Debug Tracked PID Register" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x01)==0x01) rgroup.long 0xC010++0x03 line.long 0x00 "GITS_TRKVIDR,Debug Tracked ID Register" hexmask.long.word 0x00 0.--15. 1. " LPI_ID ,The ID before translation of the interrupt that was tracked" else hgroup.long 0xC010++0x03 hide.long 0x00 "GITS_TRKVIDR,Debug Tracked ID Register" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7F)==0x01) rgroup.long 0xC014++0x03 line.long 0x00 "GITS_TRKTGTR,Debug Tracked Target Register" hexmask.long.byte 0x00 0.--6. 1. " LPI_TARGET_CORE ,The target core for an interrupt that was tracked and generated an LPI successfully" else hgroup.long 0xC014++0x03 hide.long 0x00 "GITS_TRKTGTR,Debug Tracked Target Register" endif rgroup.long 0xC018++0x03 line.long 0x00 "GITS_TRKICR,Debug ITE Cache Statistics" hexmask.long.word 0x00 16.--31. 1. " ITE_CACHE_HITS ,Number of hits in the ITE cache" hexmask.long.word 0x00 0.--15. 1. " ITE_CACHE_MISSES ,Number of misses in the ITE cache" rgroup.long 0xC01C++0x03 line.long 0x00 "GITS_TRKLCR,Debug LPI Cache Statistics" hexmask.long.word 0x00 16.--31. 1. " LPI_CACHE_HITS ,Number of hits in the LPI cache" hexmask.long.word 0x00 0.--15. 1. " LPI_CACHE_MISSES ,Number of misses in the LPI cache" rgroup.long 0xFFE0++0x03 line.long 0x00 "GITS_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]" rgroup.long 0xFFE4++0x03 line.long 0x00 "GITS_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFE8++0x03 line.long 0x00 "GITS_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..." bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High" textline " " bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" rgroup.long 0xFFEC++0x03 line.long 0x00 "GITS_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFD0++0x03 line.long 0x00 "GITS_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFFD4++0x03 hide.long 0x00 "GITS_PIDR5,Peripheral ID5 Register" hgroup.long 0xFFD8++0x03 hide.long 0x00 "GITS_PIDR6,Peripheral ID6 Register" hgroup.long 0xFFDC++0x03 hide.long 0x00 "GITS_PIDR7,Peripheral ID7 Register" rgroup.long 0xFFF0++0x03 line.long 0x00 "GITS_CIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF4++0x03 line.long 0x00 "GITS_CIDR1,Component ID1 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF8++0x03 line.long 0x00 "GITS_CIDR2,Component ID2 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFFC++0x03 line.long 0x00 "GITS_CIDR3,Component ID3 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" textline " " base (COMP.BASE("GICD",-1.)+0x20000)+0x10000 if (((per.l((COMP.BASE("GICD",-1.)+0x20000)))&0x01)==0x01) wgroup.long 0x40++0x03 line.long 0x00 "GITS_TRANSLATER,ITS Translation Register" else hgroup.long 0x40++0x03 hide.long 0x00 "GITS_TRANSLATER,ITS Translation Register" endif tree.end width 0x0B base COMP.BASE("GICR",-1.) width 17. tree "Redistributor Interface" tree "Control Registers" if (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x21) group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 26. " DPG1S ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes" bitfld.long 0x00 25. " DPG1NS ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes" textline " " bitfld.long 0x00 24. " DPG0 ,Disable Processor selection for Group 0 interrupts" "No,Yes" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" bitfld.long 0x00 0. " ENABLE_LPIS ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled" elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x20) group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 26. " DPG1S ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes" bitfld.long 0x00 25. " DPG1NS ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes" textline " " bitfld.long 0x00 24. " DPG0 ,Disable Processor selection for Group 0 interrupts" "No,Yes" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x01) group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" bitfld.long 0x00 0. " ENABLE_LPIS ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" endif rgroup.long 0x0004++0x03 line.long 0x00 "GICR_IIDR,Distributor Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" rgroup.quad 0x0008++0x07 line.quad 0x00 "GICR_TYPER,Interrupt Controller Type Register" hexmask.quad.byte 0x00 56.--63. 1. " AFF3 ,Affinity level 3 value for the Redistributor" hexmask.quad.byte 0x00 48.--55. 1. " AFF2 ,Affinity level 2 value for the Redistributor" hexmask.quad.byte 0x00 40.--47. 1. " AFF1 ,Affinity level 1 value for the Redistributor" textline " " hexmask.quad.byte 0x00 32.--39. 1. " AFF0 ,Affinity level 0 value for the Redistributor" bitfld.quad 0x00 24.--25. " COMMONLPIAFF ,The affinity level at which Redistributors share a LPI Configuration table" "All levels,AFF3,AFF3/AFF2,AFF3/AFF2/AFF1" hexmask.quad.word 0x00 8.--23. 1. " PROCESSOR_NUMBER ,A unique identifier for the PE" textline " " bitfld.quad 0x00 5. " DPGS ,Sets support for GICR_CTLR.DPG* bits" "Not supported,Supported" bitfld.quad 0x00 4. " LAST ,Indicates whether this Redistributor is the highest-numbered Redistributor in a series of contiguous Redistributor pages" "Not highest,Highest" bitfld.quad 0x00 3. " DIRECTLPI ,Indicates whether this Redistributor supports direct injection of LPIs" "Not supported,Supported" textline " " bitfld.quad 0x00 0. " PLPIS ,Indicates whether the GIC implementation supports physical LPIs" "Not supported,Supported" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)||((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x0014)))) group.long 0x0014++0x03 line.long 0x00 "GICR_WAKER,Power Management Control Register" bitfld.long 0x00 31. " QUIESCENT ,This bit shows that the GIC-500 is idle and can be powered down if required" "Not quiescent,Quiescent" bitfld.long 0x00 2. " CHILDRENASLEEP ,Indicates the bus between the CPU interface and this Redistributor is quiescent" "Not quiescent,Quiescent" bitfld.long 0x00 1. " PROCESSORASLEEP ,Indicates if this Redistributor must assert a WakeRequest if there is a pending interrupt targeted at the connected core" "No,Yes" textline " " bitfld.long 0x00 0. " SLEEP ,Indicates if GIC-500 ensures that all the caches are consistent with external memory and that it is safe to power off" "No,Yes" textline " " else hgroup.long 0x0014++0x03 hide.long 0x00 "GICR_WAKER,Power Management Control Register" endif group.quad 0x070++0x07 line.quad 0x00 "GICR_PROPBASER,Common LPI configuration table base register" bitfld.quad 0x00 56.--58. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the LPI Configuration table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" hexmask.quad 0x00 12.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:12] of the physical address containing the LPI Configuration table" textline " " bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the LPI Configuration table" "Non-shareable,Inner Shareable,Outer Shareable,?..." bitfld.quad 0x00 7.--9. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the LPI Configuration table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" textline " " bitfld.quad 0x00 0.--4. " IDBITS ,The number of bits of LPI INTID supported minus one by the LPI Configuration table starting at Physical_Address" group.quad 0x78++0x07 line.quad 0x00 "GICR_PENDBASER,LPI pending table base register" bitfld.quad 0x00 62. " PTZ ,Pending Table Zero" "Not zero,Zero" bitfld.quad 0x00 56.--58. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the LPI Pending table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" textline " " hexmask.quad 0x00 16.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:16] of the physical address containing the LPI Pending table" bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the LPI Pending table" "Non-shareable,Inner Shareable,Outer Shareable,?..." textline " " bitfld.quad 0x00 7.--9. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the LPI Pending table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" textline " " tree.end tree "SGI and PPI Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10080)) group.long 0x10080++0x03 line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Secure,Non-secure Group 1" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x000) group.long 0x10080++0x03 line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" else hgroup.long 0x10080++0x03 hide.long 0x00 "GICR_IGROUPR0,Interrupt Group Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif textline " " width 24. group.long 0x10100++0x03 line.long 0x0 "GICR_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB15 ,Set/Clear Enable Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB14 ,Set/Clear Enable Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13 ,Set/Clear Enable Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB12 ,Set/Clear Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB11 ,Set/Clear Enable Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10 ,Set/Clear Enable Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB9 ,Set/Clear Enable Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB8 ,Set/Clear Enable Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7 ,Set/Clear Enable Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB6 ,Set/Clear Enable Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB5 ,Set/Clear Enable Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4 ,Set/Clear Enable Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB3 ,Set/Clear Enable Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB2 ,Set/Clear Enable Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1 ,Set/Clear Enable Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB0 ,Set/Clear Enable Bit 0" "Disabled,Enabled" group.long 0x10200++0x03 line.long 0x0 "GICR_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Not pending,Pending" group.long 0x10300++0x03 line.long 0x0 "GICR_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE9 ,Set/Clear Active Bit 9" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE8 ,Set/Clear Active Bit 8" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7 ,Set/Clear Active Bit 7" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE6 ,Set/Clear Active Bit 6" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE5 ,Set/Clear Active Bit 5" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4 ,Set/Clear Active Bit 4" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE3 ,Set/Clear Active Bit 3" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE2 ,Set/Clear Active Bit 2" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1 ,Set/Clear Active Bit 1" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE0 ,Set/Clear Active Bit 0" "Not active,Active" textline " " width 18. group.long 0x10400++0x03 line.long 0x00 "GICR_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x10404++0x03 line.long 0x00 "GICR_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x10408++0x03 line.long 0x00 "GICR_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x1040C++0x03 line.long 0x00 "GICR_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x10410++0x03 line.long 0x00 "GICR_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x10414++0x03 line.long 0x00 "GICR_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x10418++0x03 line.long 0x00 "GICR_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x1041C++0x03 line.long 0x00 "GICR_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " textline " " rgroup.long 0x10C00++0x03 line.long 0x00 "GICR_ICFGR0,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SGI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SGI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SGI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SGI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SGI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SGI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SGI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SGI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SGI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SGI)" "Level,Edge" group.long 0x10C04++0x03 line.long 0x00 "GICR_ICFGR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (PPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (PPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (PPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (PPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (PPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (PPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (PPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (PPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (PPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (PPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (PPI)" "Level,Edge" textline " " width 18. if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10D00)) group.long 0x10D00++0x03 line.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0" bitfld.long 0x00 31. " GMB31 ,Group Modifier Bit 31" "0,1" bitfld.long 0x00 30. " GMB30 ,Group Modifier Bit 30" "0,1" bitfld.long 0x00 29. " GMB29 ,Group Modifier Bit 29" "0,1" textline " " bitfld.long 0x00 28. " GMB28 ,Group Modifier Bit 28" "0,1" bitfld.long 0x00 27. " GMB27 ,Group Modifier Bit 27" "0,1" bitfld.long 0x00 26. " GMB26 ,Group Modifier Bit 26" "0,1" textline " " bitfld.long 0x00 25. " GMB25 ,Group Modifier Bit 25" "0,1" bitfld.long 0x00 24. " GMB24 ,Group Modifier Bit 24" "0,1" bitfld.long 0x00 23. " GMB23 ,Group Modifier Bit 23" "0,1" textline " " bitfld.long 0x00 22. " GMB22 ,Group Modifier Bit 22" "0,1" bitfld.long 0x00 21. " GMB21 ,Group Modifier Bit 21" "0,1" bitfld.long 0x00 20. " GMB20 ,Group Modifier Bit 20" "0,1" textline " " bitfld.long 0x00 19. " GMB19 ,Group Modifier Bit 19" "0,1" bitfld.long 0x00 18. " GMB18 ,Group Modifier Bit 18" "0,1" bitfld.long 0x00 17. " GMB17 ,Group Modifier Bit 17" "0,1" textline " " bitfld.long 0x00 16. " GMB16 ,Group Modifier Bit 16" "0,1" bitfld.long 0x00 15. " GMB15 ,Group Modifier Bit 15" "0,1" bitfld.long 0x00 14. " GMB14 ,Group Modifier Bit 14" "0,1" textline " " bitfld.long 0x00 13. " GMB13 ,Group Modifier Bit 13" "0,1" bitfld.long 0x00 12. " GMB12 ,Group Modifier Bit 12" "0,1" bitfld.long 0x00 11. " GMB11 ,Group Modifier Bit 11" "0,1" textline " " bitfld.long 0x00 10. " GMB10 ,Group Modifier Bit 10" "0,1" bitfld.long 0x00 9. " GMB9 ,Group Modifier Bit 9" "0,1" bitfld.long 0x00 8. " GMB8 ,Group Modifier Bit 8" "0,1" textline " " bitfld.long 0x00 7. " GMB7 ,Group Modifier Bit 7" "0,1" bitfld.long 0x00 6. " GMB6 ,Group Modifier Bit 6" "0,1" bitfld.long 0x00 5. " GMB5 ,Group Modifier Bit 5" "0,1" textline " " bitfld.long 0x00 4. " GMB4 ,Group Modifier Bit 4" "0,1" bitfld.long 0x00 3. " GMB3 ,Group Modifier Bit 3" "0,1" bitfld.long 0x00 2. " GMB2 ,Group Modifier Bit 2" "0,1" textline " " bitfld.long 0x00 1. " GMB1 ,Group Modifier Bit 1" "0,1" bitfld.long 0x00 0. " GMB0 ,Group Modifier Bit 0" "0,1" textline " " else hgroup.long 0x10D00++0x03 hide.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10E00)) group.long 0x10E00++0x03 line.long 0x00 "GICR_NSACR,Non-secure Access Control Register" bitfld.long 0x00 30.--31. " NS_ACCESS15 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID15" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 28.--29. " NS_ACCESS14 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID14" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 26.--27. " NS_ACCESS13 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID13" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 24.--25. " NS_ACCESS12 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID12" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 22.--23. " NS_ACCESS11 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID11" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 20.--21. " NS_ACCESS10 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID10" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 18.--19. " NS_ACCESS9 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID9" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 16.--17. " NS_ACCESS8 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID8" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 14.--15. " NS_ACCESS7 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID7" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 12.--13. " NS_ACCESS6 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID6" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 10.--11. " NS_ACCESS5 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID5" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 8.--9. " NS_ACCESS4 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID4" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 6.--7. " NS_ACCESS3 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID3" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 4.--5. " NS_ACCESS2 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID2" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 2.--3. " NS_ACCESS1 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID1" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 0.--1. " NS_ACCESS0 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID0" "No access,G0S,G0S/G1S,?..." textline " " else hgroup.long 0x10E00++0x03 hide.long 0x00 "GICR_NSACR,Non-secure Access Control Register" textline " " textline " " textline " " textline " " textline " " endif rgroup.long 0x1C000++0x03 line.long 0x00 "GICR_MISCSTATUSR,Miscellaneous Status Register" bitfld.long 0x00 31. " CPU_AS ,CPU active state. This bit returns the actual status of the cpu_active signal for the core corresponding to the Redistributor whose register is being read" "Low,High" bitfld.long 0x00 2. " ENABLEGRP1_S ,EnableGrp1 Secure" "0,1" bitfld.long 0x00 1. " ENABLEGRP1_NS ,EnableGrp1 Non-secure" "0,1" textline " " bitfld.long 0x00 0. " ENABLEGRP0 ,EnableGrp0" "0,1" rgroup.long 0x1C080++0x03 line.long 0x00 "GICR_PPISR,Private Peripheral Interrupt Status Register" bitfld.long 0x00 31. " PPI31S ,Actual status of the PPI31 input signal" "Low,High" bitfld.long 0x00 30. " PPI30S ,Actual status of the PPI30 input signal" "Low,High" bitfld.long 0x00 29. " PPI29S ,Actual status of the PPI29 input signal" "Low,High" textline " " bitfld.long 0x00 28. " PPI28S ,Actual status of the PPI28 input signal" "Low,High" bitfld.long 0x00 27. " PPI27S ,Actual status of the PPI27 input signal" "Low,High" bitfld.long 0x00 26. " PPI26S ,Actual status of the PPI26 input signal" "Low,High" textline " " bitfld.long 0x00 25. " PPI25S ,Actual status of the PPI25 input signal" "Low,High" bitfld.long 0x00 24. " PPI24S ,Actual status of the PPI24 input signal" "Low,High" bitfld.long 0x00 23. " PPI23S ,Actual status of the PPI23 input signal" "Low,High" textline " " bitfld.long 0x00 22. " PPI22S ,Actual status of the PPI22 input signal" "Low,High" bitfld.long 0x00 21. " PPI21S ,Actual status of the PPI21 input signal" "Low,High" bitfld.long 0x00 20. " PPI20S ,Actual status of the PPI20 input signal" "Low,High" textline " " bitfld.long 0x00 19. " PPI19S ,Actual status of the PPI19 input signal" "Low,High" bitfld.long 0x00 18. " PPI18S ,Actual status of the PPI18 input signal" "Low,High" bitfld.long 0x00 17. " PPI17S ,Actual status of the PPI17 input signal" "Low,High" textline " " bitfld.long 0x00 16. " PPI16S ,Actual status of the PPI16 input signal" "Low,High" tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.long 0xFFE0++0x03 line.long 0x00 "GICR_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]" rgroup.long 0xFFE4++0x03 line.long 0x00 "GICR_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFE8++0x03 line.long 0x00 "GICR_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..." bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High" bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" rgroup.long 0xFFEC++0x03 line.long 0x00 "GICR_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFD0++0x03 line.long 0x00 "GICR_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFFD4++0x03 hide.long 0x00 "GICR_PIDR5,Peripheral ID5 Register" hgroup.long 0xFFD8++0x03 hide.long 0x00 "GICR_PIDR6,Peripheral ID6 Register" hgroup.long 0xFFDC++0x03 hide.long 0x00 "GICR_PIDR7,Peripheral ID7 Register" rgroup.long 0xFFF0++0x03 line.long 0x00 "GICR_CIDR0,Component ID0 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF4++0x03 line.long 0x00 "GICR_CIDR1,Component ID1 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF8++0x03 line.long 0x00 "GICR_CIDR2,Component ID2 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFFC++0x03 line.long 0x00 "GICR_CIDR3,Component ID3 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" tree.end tree.end width 0x0B sif COMP.AVAILABLE("GICC") base COMP.BASE("GICC",-1.) width 14. tree "CPU Interface" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICC",-1.))) group.long 0x00++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 10. " EOIMODENS ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 9. " EOIMODES ,Controls the behavior of Secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 8. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" textline " " bitfld.long 0x00 7. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" bitfld.long 0x00 6. " IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" textline " " bitfld.long 0x00 4. " CBPR ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both" bitfld.long 0x00 3. " FIQEN ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ" bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400) group.long 0x00++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 9. " EOIMODENS ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 6. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" textline " " bitfld.long 0x00 0. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 9. " EOIMODE ,Controls the behavior of accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 8. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" bitfld.long 0x00 7. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" textline " " bitfld.long 0x00 6. " IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" bitfld.long 0x00 4. " CBPR ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both" textline " " bitfld.long 0x00 3. " FIQEN ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ" bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled" endif textline " " group.long 0x04++0x03 line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface" group.long 0x08++0x03 line.long 0x00 "GICC_BPR,Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" hgroup.long 0x0C++0x03 hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register" in wgroup.long 0x10++0x03 line.long 0x00 "GICC_EOIR,End Of Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" rgroup.long 0x14++0x03 line.long 0x00 "GICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt" rgroup.long 0x18++0x03 line.long 0x00 "GICC_HPPIR,Highest Priority Pending Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" group.long 0x1C++0x03 line.long 0x00 "GICC_ABPR,Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" hgroup.long 0x20++0x03 hide.long 0x00 "GICC_AIAR,Aliased Interrupt Acknowledge Register" in wgroup.long 0x24++0x03 line.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" rgroup.long 0x28++0x03 line.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" rgroup.long 0x2C++0x03 line.long 0x00 "GICC_STATUSR,CPU Interface Status Register" bitfld.long 0x00 4. " ASV ,Attempted security violation" "Not detected,Detected" bitfld.long 0x00 3. " WROD ,Write to an RO location" "Not detected,Detected" bitfld.long 0x00 2. " RWOD ,Read of a WO location" "Not detected,Detected" textline " " bitfld.long 0x00 1. " WRD ,Write to a reserved location" "Not detected,Detected" bitfld.long 0x00 0. " RRD ,Read of a reserved location" "Not detected,Detected" group.long 0xD0++0x03 line.long 0x00 "GICC_APR0,Active Priorities Register 0" group.long 0xD4++0x03 line.long 0x00 "GICC_APR1,Active Priorities Register 1" group.long 0xD8++0x03 line.long 0x00 "GICC_APR2,Active Priorities Register 2" group.long 0xDC++0x03 line.long 0x00 "GICC_APR3,Active Priorities Register 3" group.long 0xE0++0x03 line.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register 0" group.long 0xE4++0x03 line.long 0x00 "GICC_NSAPR1,Non-Secure Active Priorities Register 1" group.long 0xE8++0x03 line.long 0x00 "GICC_NSAPR2,Non-Secure Active Priorities Register 2" group.long 0xEC++0x03 line.long 0x00 "GICC_NSAPR3,Non-Secure Active Priorities Register 3" rgroup.long 0xFC++0x03 line.long 0x00 "GICC_IIDR,CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCHVER ,The version of the GIC architecture that is implemented" ",,,GICv3,?..." bitfld.long 0x00 12.--15. " REV ,Revision number for the CPU interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICC_DIR,Deactivate Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" tree.end width 0x0b endif sif COMP.AVAILABLE("GICH") base COMP.BASE("GICH",-1.) width 13. tree "Virtual CPU Control Interface" group.long 0x00++0x03 line.long 0x00 "GICH_HCR,Hypervisor Control Register" bitfld.long 0x00 27.--31. " EOICOUNT ,Counts the number of EOIs received that do not have a corresponding entry in the List registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " VGRP1DIE ,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " VGRP1EIE ,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " VGRP0DIE ,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " VGRP0EIE ,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " NPIE ,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " LRENPIE ,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " UIE ,Underflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EN ,Virtual CPU interface Enable" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "GICH_VTR,Virtual Type Register" bitfld.long 0x00 29.--31. " PRIBITS ,Number of priority bits" "1,2,3,4,5,6,7,8" bitfld.long 0x00 26.--28. " PREBITS ,Number of pre-emption bits" "1,2,3,4,5,6,7,8" bitfld.long 0x00 23.--25. " IDBITS ,The number of virtual interrupt identifier bits supported" "16 bits,24 bits,?..." textline " " bitfld.long 0x00 22. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not supported,Supported" bitfld.long 0x00 21. " A3V ,Affinity 3 valid" "Invalid,Valid" bitfld.long 0x00 0.--4. " LISTREGS ,List regs number" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" group.long 0x08++0x03 line.long 0x00 "GICH_VMCR,Virtual Machine Control Register" hexmask.long.byte 0x00 24.--31. 1. " VPMR ,Virtual priority mask" bitfld.long 0x00 21.--23. " VBPR0 ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 0)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " VBPR1 ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 1)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9. " VEOIM ,Virtual EOImode. DP - Drop the priority / ID - interrupt deactivate" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" textline " " bitfld.long 0x00 4. " VCBPR ,Virtual Common Binary Point Register" "ABPR,BPR" bitfld.long 0x00 3. " VFIQEN ,Virtual FIQ enable" "Disabled,Enabled" bitfld.long 0x00 2. " VACKCTL ,Virtual AckCtl" "INTID=1022,INTID=corresponding" bitfld.long 0x00 1. " VENG1 ,Virtual interrupt enable for group 1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " VENG0 ,Virtual interrupt enable for group 0" "Disabled,Enabled" rgroup.long 0x10++0x03 line.long 0x00 "GICH_MISR,Maintenance Interrupt Status Register" bitfld.long 0x00 7. " VGRP1D ,vPE Group 1 Disabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 6. " VGRP1E ,vPE Group 1 Enabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 5. " VGRP0D ,vPE Group 0 Disabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 4. " VGRP0E ,vPE Group 0 Enabled maintenance interrupt assertion" "Not asserted,Asserted" textline " " bitfld.long 0x00 3. " NP ,No Pending maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 2. " LRENP ,List Register Entry Not Present maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 1. " U ,Underflow maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 0. " EOI ,End Of Interrupt maintenance interrupt assertion" "Not asserted,Asserted" rgroup.long 0x20++0x03 line.long 0x00 "GICH_EISR0,End of Interrupt Status Register" bitfld.long 0x00 15. " STATUS15 ,EOI maintenance interrupt status for List register 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " STATUS14 ,EOI maintenance interrupt status for List register 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " STATUS13 ,EOI maintenance interrupt status for List register 13" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " STATUS12 ,EOI maintenance interrupt status for List register 12" "No interrupt,Interrupt" bitfld.long 0x00 11. " STATUS11 ,EOI maintenance interrupt status for List register 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " STATUS10 ,EOI maintenance interrupt status for List register 10" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " STATUS9 ,EOI maintenance interrupt status for List register 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " STATUS8 ,EOI maintenance interrupt status for List register 8" "No interrupt,Interrupt" bitfld.long 0x00 7. " STATUS7 ,EOI maintenance interrupt status for List register 7" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " STATUS6 ,EOI maintenance interrupt status for List register 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " STATUS5 ,EOI maintenance interrupt status for List register 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " STATUS4 ,EOI maintenance interrupt status for List register 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " STATUS3 ,EOI maintenance interrupt status for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " STATUS2 ,EOI maintenance interrupt status for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " STATUS1 ,EOI maintenance interrupt status for List register 1" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " STATUS0 ,EOI maintenance interrupt status for List register 0" "No interrupt,Interrupt" rgroup.long 0x30++0x03 line.long 0x00 "GICH_ELRSR0,Empty List register Status Register" bitfld.long 0x00 15. " STATUS15 ,Status bit for List register 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " STATUS14 ,Status bit for List register 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " STATUS13 ,Status bit for List register 13" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " STATUS12 ,Status bit for List register 12" "No interrupt,Interrupt" bitfld.long 0x00 11. " STATUS11 ,Status bit for List register 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " STATUS10 ,Status bit for List register 10" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " STATUS9 ,Status bit for List register 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " STATUS8 ,Status bit for List register 8" "No interrupt,Interrupt" bitfld.long 0x00 7. " STATUS7 ,Status bit for List register 7" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " STATUS6 ,Status bit for List register 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " STATUS5 ,Status bit for List register 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " STATUS4 ,Status bit for List register 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " STATUS3 ,Status bit for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " STATUS2 ,Status bit for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " STATUS1 ,Status bit for List register 1" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " STATUS0 ,Status bit for List register 0" "No interrupt,Interrupt" textline " " group.long 0xF0++0x03 line.long 0x00 "GICH_APR0,Active Priorities Register 0" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xF4++0x03 line.long 0x00 "GICH_APR1,Active Priorities Register 1" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xF8++0x03 line.long 0x00 "GICH_APR2,Active Priorities Register 2" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xFC++0x03 line.long 0x00 "GICH_APR3,Active Priorities Register 3" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" textline " " group.long 0x100++0x03 line.long 0x00 "GICH_LR0,List Register 0" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x104++0x03 line.long 0x00 "GICH_LR1,List Register 1" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x108++0x03 line.long 0x00 "GICH_LR2,List Register 2" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x10C++0x03 line.long 0x00 "GICH_LR3,List Register 3" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x110++0x03 line.long 0x00 "GICH_LR4,List Register 4" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x114++0x03 line.long 0x00 "GICH_LR5,List Register 5" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x118++0x03 line.long 0x00 "GICH_LR6,List Register 6" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x11C++0x03 line.long 0x00 "GICH_LR7,List Register 7" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x120++0x03 line.long 0x00 "GICH_LR8,List Register 8" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x124++0x03 line.long 0x00 "GICH_LR9,List Register 9" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x128++0x03 line.long 0x00 "GICH_LR10,List Register 10" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x12C++0x03 line.long 0x00 "GICH_LR11,List Register 11" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x130++0x03 line.long 0x00 "GICH_LR12,List Register 12" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x134++0x03 line.long 0x00 "GICH_LR13,List Register 13" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x138++0x03 line.long 0x00 "GICH_LR14,List Register 14" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" tree.end width 0x0b endif sif COMP.AVAILABLE("GICV") base COMP.BASE("GICV",-1.) width 14. tree "Virtual CPU Interface" group.long 0x00++0x03 line.long 0x00 "GICV_CTLR,VM Control Register" bitfld.long 0x00 9. " EOIMODE ,Controls the behaviour of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 4. " CBPR ,Controls whether GICV_BPR affects both Group 0 and Group 1 interrupts" "Group 0,Both" bitfld.long 0x00 3. " FIQEN ,FIQ Enable" "Disabled,Enabled" bitfld.long 0x00 2. " ACKCTL ,Acknowledge control. Return ID of the corresponding interrupt" "1022,Corresponding" textline " " bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signalling of Group 1 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signalling of Group 0 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled" group.long 0x04++0x03 line.long 0x00 "GICV_PMR,VM Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for the virtual CPU interface" group.long 0x08++0x03 line.long 0x00 "GICV_BPR,VM Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" rgroup.long 0x0C++0x03 line.long 0x00 "GICV_IAR,VM Interrupt Acknowledge Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" wgroup.long 0x10++0x03 line.long 0x00 "GICV_EOIR,VM End Of Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" rgroup.long 0x14++0x03 line.long 0x00 "GICV_RPR,VM Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt" rgroup.long 0x18++0x03 line.long 0x00 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" group.long 0x1C++0x03 line.long 0x00 "GICV_ABPR,VM Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" rgroup.long 0x20++0x03 line.long 0x00 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" wgroup.long 0x24++0x03 line.long 0x00 "GICV_AEOIR,VM Aliased End of Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" rgroup.long 0x28++0x03 line.long 0x00 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" textline "" group.long 0xD0++0x03 line.long 0x00 "GICV_APR0,VM Active Priority Register 0" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xD4++0x03 line.long 0x00 "GICV_APR1,VM Active Priority Register 1" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xD8++0x03 line.long 0x00 "GICV_APR2,VM Active Priority Register 2" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xDC++0x03 line.long 0x00 "GICV_APR3,VM Active Priority Register 3" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" textline " " rgroup.long 0xFC++0x03 line.long 0x00 "GICV_IIDR,Virtual Machine CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCHVER ,The version of the GIC architecture that is implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " REV ,Revision number for the CPU interface" ",,,GICv3,?..." hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICV_DIR,VM Deactivate Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" tree.end width 0x0b endif width 0x0B tree.end tree.end elif (CORENAME()=="CORTEXR5F") tree "Core Registers (Cortex-R5F)" AUTOINDENT.PUSH AUTOINDENT.OFF width 0x8 ; -------------------------------------------------------------------------------- ; Identification registers ; -------------------------------------------------------------------------------- tree "ID Registers" rgroup.long c15:0x00++0x00 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH ,Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x100++0x00 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical" textline " " bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" rgroup.long c15:0x400--0x400 line.long 0x0 "MPUIR,MPU type register" hexmask.long.byte 0x00 8.--15. 1. " REGNUM ,Number of regions" bitfld.long 0x00 0. " TYPE ,Type of MPU regions" "Unified,Seperated" rgroup.long c15:0x500++0x00 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30.--31. " MULT_EXT ,Multiprocessing extensions" "No extensions,Reserved,Reserved,Part of a uniprocessor system" textline " " hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitnity Level 2" hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitnity Level 1" hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitnity Level 0" textline " " rgroup.long c15:0x0410++0x00 line.long 0x00 "MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " SL ,Number of Shareability levels implemented" "1,?..." bitfld.long 0x00 8.--11. " OS ,Outermost Shareability domain support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..." bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..." rgroup.long c15:0x020++0x00 line.long 0x00 "ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x120++0x00 line.long 0x00 "ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x220++0x00 line.long 0x00 "ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x320++0x00 line.long 0x00 "ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x420++0x00 line.long 0x00 "ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x00 28.--31. " SWP_FRAC ,SWAP_frac" "Supported,?..." bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0520++0x00 line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)" rgroup.long c15:0x0620++0x00 line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)" rgroup.long c15:0x0720++0x00 line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)" rgroup.long c15:0x010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..." bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c15:0x110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." textline " " rgroup.long c15:0x210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." textline " " bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..." rgroup.long c15:0x310++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long c15:0x02f++0x00 line.long 0x00 "BO1R,Build Options 1 Register" hexmask.long.long 0x00 12.--31. 0x1000 " TCM_HI_INIT_ADDR ,Default high address for the TCM" bitfld.long 0x00 1. " FLOAT_PRECISION ,Indicate whether double-precision floating point is implemented" "Not implemented,Implemented" textline " " bitfld.long 0x00 0. " PP_BUS_ECC ,Indicate whether bus-ECC is implemented" "Not implemented,Implemented" group.long c15:0x12f++0x00 line.long 0x00 "BO2R,Build Options 2 Register" bitfld.long 0x00 31. " NUM_CPU ,Number of CPUs" "1,2" bitfld.long 0x00 30. " LOCK_STEP ,Indicate whether the CPU has redundant logic running in lock step for checking purposes" "Not included,Included" textline " " bitfld.long 0x00 29. " NO_ICACHE ,Indicate whether the CPU contains instruction cache" "Yes,No" bitfld.long 0x00 28. " NO_DCACHE ,Indicate whether the CPU contains data cache" "Yes,No" textline " " bitfld.long 0x00 26.--27. " ATCM_ES ,Indicate whether an error scheme is implemented on the ATCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection" bitfld.long 0x00 23.--25. " BTCM_ES ,Indicate whether an error scheme is implemented on the BTCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection,?..." textline " " bitfld.long 0x00 23. " NO_IE ,Indicate whether the processor supports big-endian instructions" "Yes,No" bitfld.long 0x00 22. " NO_FPU ,Indicate whether the CPU contains a floating point unit" "Yes,No" textline " " bitfld.long 0x00 20.--21. " MPU_REGIONS ,Indicates the number of regions in the included CPU MPU" "No region,Reserved,12 regions,16 regions" bitfld.long 0x00 17.--19. " BREAK_POINTS ,Indicate the number of break points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 14.--16. " WATCH_POINTS ,Indicate the number of watch points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " NO_A_TCM_INF ,Indicate whether the CPUs contain ATCM ports" "Yes,No" textline " " bitfld.long 0x00 12. " NO_B0_TCM_INF ,Indicate whether the CPUs contain B0TCM ports" "Yes,No" bitfld.long 0x00 11. " NO_B1_TCM_INF ,Indicate whether the CPUs contain B1TCM ports" "Yes,No" textline " " bitfld.long 0x00 10. " TCMBUSPARITY ,Indicate whether the processor contains TCM address bus parity logic" "No,Yes" bitfld.long 0x00 9. " NO_SLAVE ,Indicate whether the CPU contains an AXI slave port" "Yes,No" textline " " bitfld.long 0x00 7.--8. " ICACHE_ES ,Indicate whether an error scheme is implemented for the instruction cache" "No error scheme,8-bit parity,Reserved,64-bit ECC" bitfld.long 0x00 5.--6. " DCACHE_ES ,Indicate whether an error scheme is implemented for the data cache" "No error scheme,8-bit parity,32-bit ECC,?..." textline " " bitfld.long 0x00 4. " NO_HARD_ERROR_CACHE ,Indicate whether the processor contains cache for corrected TCM errors" "Yes,No" bitfld.long 0x00 3. " AXI_BUS_ECC ,Indicate whether the processor contains AXI bus ECC logic" "No,Yes" textline " " bitfld.long 0x00 2. " SL ,Indicate whether the processor has been built with split/lock logic" "No,Yes" bitfld.long 0x00 1. " AHB_PP ,Indicate whether the CPU contain AHB peripheral interfaces" "No,Yes" textline " " bitfld.long 0x00 0. " MICRO_SCU ,Indicate whether the processor contain an ACP interface" "No,Yes" group.long c15:0x72f++0x00 line.long 0x00 "POR,Pin Options Register" bitfld.long 0x00 4. " DBGNOCLKSTOP ,Value of the DBGNOCLKSTOP pin" "Low,High" bitfld.long 0x00 3. " INTSYNCEN ,Value of the INTSYNCEN pin" "Low,High" textline " " bitfld.long 0x00 2. " IRQADDRVSYNCEN ,Value of the IRQADDRVSYNCEN pin" "Low,High" bitfld.long 0x00 1. " SLBTCMSB ,Value of the SLBTCMSBm pin" "Low,High" textline " " bitfld.long 0x00 0. " PARITYLEVEL ,Value of the PARITYLEVEL pin" "Low,High" tree.end width 0x8 tree "System Control and Configuration" group.long c15:0x01++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable" bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable" textline " " bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored" bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable" textline " " bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable" bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable" bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable" bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable" bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable" textline " " group.long c15:0x101++0x00 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 31. " DICDI ,Disable Case C dual issue control" "Enable,Disable" bitfld.long 0x00 30. " DIB2DI ,Disable Case B2 dual issue control" "Enable,Disable" bitfld.long 0x00 29. " DIB1DI ,Disable Case B1 dual issue control" "Enable,Disable" textline " " bitfld.long 0x00 28. " DIADI ,Disable Case A dual issue control" "Enable,Disable" bitfld.long 0x00 27. " B1TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" bitfld.long 0x00 26. " B0TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" textline " " bitfld.long 0x00 25. " ATCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" bitfld.long 0x00 24. " AXISCEN ,AXI slave cache access enable" "Disable,Enable" bitfld.long 0x00 23. " AXISCUEN ,AXI slave cache User mode access enable" "Disable,Enable" textline " " bitfld.long 0x00 22. " DILSM ,Disable LIL on load/store multiples" "Enable,Disable" bitfld.long 0x00 21. " DEOLP ,Disable end of loop prediction" "Enable,Disable" bitfld.long 0x00 20. " DBHE ,Disable BH extension" "Enable,Disable" textline " " bitfld.long 0x00 19. " FRCDIS ,Fetch rate control disable" "Enable,Disable" bitfld.long 0x00 17. " RSDIS ,Return stack disable" "Enable,Disable" bitfld.long 0x00 15.--16. " BP ,Control of the branch prediction policy" "Normal,Taken,Not taken,?..." textline " " bitfld.long 0x00 14. " DBWR ,Disable write_burst on AXI master" "Enable,Disable" bitfld.long 0x00 13. " DLFO ,Disable linefill optimization in the AXI master" "Enable,Disable" bitfld.long 0x00 12. " ERPEG ,Enable random parity error generation" "Disable,Enable" textline " " bitfld.long 0x00 11. " DNCH ,Disable data forwarding for Non-cacheable accesses in the AXI master" "Enable,Disable" bitfld.long 0x00 10. " FORA ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced" bitfld.long 0x00 9. " FWT ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced" textline " " bitfld.long 0x00 8. " FDSnS ,Force D-side to not-shared when MPU is off" "Not forced,Forced" bitfld.long 0x00 7. " SMOV ,sMOV disabled" "Enabled,Disabled" bitfld.long 0x0 6. " DILS ,Disable low interrupt latency on all load/store instructions" "Enable,Disable" textline " " bitfld.long 0x00 3.--5. " CEC ,Cache error control for cache parity and ECC errors" "Generate abort,Generate abort,Generate abort,Reserved,Disabled parity checking,Not generate abort,Not generate abort,?..." textline " " bitfld.long 0x00 2. " B1TCMECEN ,B1TCM external error enable" "Disable,Enable" bitfld.long 0x00 1. " B0TCMECEN ,B0TCM external error enable" "Disable,Enable" bitfld.long 0x00 0. " ATCMECEN ,ATCM external error enable" "Disable,Enable" textline " " group.long c15:0x0f++0x00 line.long 0x00 "SACTLR,Secondary Auxiliary Control Register" bitfld.long 0x00 22. " DCHE ,Disable hard-error support in the caches" "Enable,Disable" bitfld.long 0x00 21. " DR2B ,Enable random 2-bit error genration in cache RAMs" "Disable,Enable" bitfld.long 0x00 20. " DF6DI ,F6 dual issue control" "Enable,Disable" textline " " bitfld.long 0x00 19. " DF2DI ,F2 dual issue control" "Enable,Disable" bitfld.long 0x00 18. " DDI ,F1/F3/F4 dual issue control" "Enable,Disable" bitfld.long 0x00 17. " DOODPFP ,Out-of-order Double Precision Floating-point control" "Enable,Disable" textline " " bitfld.long 0x00 16. " DOOFMACS ,Out-of-order FMACS control" "Enable,Disable" bitfld.long 0x00 13. " IXC ,Floating-point inexact exception output mask" "Mask,Propagate" bitfld.long 0x00 12. " OFC ,Floating-point overflow exception output mask" "Mask,Propagate" textline " " bitfld.long 0x00 11. " UFC ,Floating-point underflow exception output mask" "Mask,Propagate" bitfld.long 0x00 10. " IOC ,Floating-point invalid operation exception output mask" "Mask,Propagate" bitfld.long 0x00 9. " DZC ,Floating-point divide-by-zero exception output mask" "Mask,Propagate" textline " " bitfld.long 0x00 8. " IDC ,Floating-point input denormal exception output mask" "Mask,Propagate" bitfld.long 0x00 3. " BTCMECC ,Correction for internal ECC logic on BTCM ports" "Enable,Disable" bitfld.long 0x00 2. " ATCMECC ,Correction for internal ECC logic on ATCM port" "Enable,Disable" textline " " bitfld.long 0x00 1. " BTCMRMW ,Enable 64-bit stores on BTCMs" "Disable,Enable" bitfld.long 0x00 0. " ATCMRMW ,Enable 64-bit stores on ATCM" "Disable,Enable" textline " " group.long c15:0x201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 30. " D32DIS ,Disable use of D16-D31 of the VFP register file" "No,Yes" textline " " bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " group.long c15:0x000b++0x00 line.long 0x00 "SPCR,Slave Port Control Register" bitfld.long 0x00 1. " PRIV ,Privilege access only" "User/Privilege,Privilege only" bitfld.long 0x00 0. " AXISLEN ,AXI slave port disable" "Enabled,Disabled" tree.end width 0x8 tree "MPU Control and Configuration" group.long c15:0x01++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable" bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable" textline " " bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored" bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable" textline " " bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable" bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable" bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable" bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable" bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable" textline " " group.long c15:0x05++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x15++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved" textline " " bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable" bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register" group.long c15:0x06++0x00 line.long 0x00 "DFAR,Data Fault Address Register" textline " " group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x115++0x00 line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register" bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved" textline " " bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable" bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register" group.long c15:0x206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" textline " " group.long c15:0x0016++0x00 line.long 0x00 "RBAR,Region Base Address Register" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group.long c15:0x0216++0x00 line.long 0x00 "RSER,Region Size and Enable Register" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group.long c15:0x0416++0x00 line.long 0x00 "RACR,Region Access Control Register" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " TYPE ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" group.long c15:0x0026++0x00 line.long 0x00 "MRNR,Memory Region Number Register" bitfld.long 0x00 0.--3. " REGION ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " group.long c15:0x010d++0x00 line.long 0x00 "CIDR,Context ID Register" group.long c15:0x20d++0x00 line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register" group.long c15:0x30d++0x00 line.long 0x00 "TIDRURO,User read only Thread and Process ID Register" group.long c15:0x40d++0x00 line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register" width 0x08 tree "MPU regions" group c15:0x0016++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RBAR0,Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RSER0,Region Size and Enable Register 0" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RACR0,Region Access Control Register 0" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RBAR1,Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RSER1,Region Size and Enable Register 1" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RACR1,Region Access Control Register 1" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RBAR2,Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RSER2,Region Size and Enable Register 2" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RACR2,Region Access Control Register 2" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RBAR3,Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RSER3,Region Size and Enable Register 3" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RACR3,Region Access Control Register 3" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RBAR4,Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RSER4,Region Size and Enable Register 4" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RACR4,Region Access Control Register 4" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RBAR5,Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RSER5,Region Size and Enable Register 5" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RACR5,Region Access Control Register 5" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RBAR6,Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RSER6,Region Size and Enable Register 6" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RACR6,Region Access Control Register 6" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RBAR7,Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RSER7,Region Size and Enable Register 7" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RACR7,Region Access Control Register 7" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RBAR8,Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RSER8,Region Size and Enable Register 8" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RACR8,Region Access Control Register 8" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RBAR9,Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RSER9,Region Size and Enable Register 9" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RACR9,Region Access Control Register 9" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RBAR10,Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RSER10,Region Size and Enable Register 10" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RACR10,Region Access Control Register 10" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RBAR11,Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RSER11,Region Size and Enable Register 11" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RACR11,Region Access Control Register 11" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RBAR12,Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RSER12,Region Size and Enable Register 12" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RACR12,Region Access Control Register 12" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RBAR13,Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RSER13,Region Size and Enable Register 13" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RACR13,Region Access Control Register 13" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RBAR14,Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RSER14,Region Size and Enable Register 14" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RACR14,Region Access Control Register 14" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RBAR15,Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RSER15,Region Size and Enable Register 15" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RACR15,Region Access Control Register 15" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " tree.end tree.end width 0x9 tree "TCM Control and Configuration" rgroup.long c15:0x200++0x00 line.long 0x00 "TCMTR,TCM Type Register" bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7" group.long c15:0x019++0x00 line.long 0x00 "BTCMRR,BTCM Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)" bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled" group.long c15:0x119++0x00 line.long 0x00 "ATCMRR,ATCM Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)" bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled" rgroup.long c15:0x29++0x00 line.long 0x00 "TCMSEL,TCM Selection Register" textline " " group.long c15:0x10f++0x00 line.long 0x00 "NAXIPIRR,Normal AXI Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" group.long c15:0x20f++0x00 line.long 0x00 "VAXIPIRR,Virtual AXI Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" group.long c15:0x30f++0x00 line.long 0x00 "AHBPIRR,AHB Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" tree.end width 0xC tree "Cache Control and Configuration" rgroup.long c15:0x1100++0x00 line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" textline " " bitfld.long 0x00 21.--23. " CL8 ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " CL7 ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 15.--17. " CL6 ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " CL5 ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 9.--11. " CL4 ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " CL3 ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 3.--5. " CL2 ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " CL1 ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7" rgroup.long c15:0x1700++0x00 line.long 0x00 "AIDR,Auxiliary ID Register" rgroup.long c15:0x1000++0x00 line.long 0x00 "CCSIDR,Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not supported,Supported" textline " " bitfld.long 0x00 29. " RA ,Read-Allocate" "Not supported,Supported" bitfld.long 0x00 28. " WA ,Write-Allocate" "Not supported,Supported" textline " " hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of sets" hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Associativity" textline " " bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7" group.long c15:0x2000++0x00 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Cache level to select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " IND ,Instruction or data or unified cache to use" "Data/unified,Instruction" group.long c15:0x03f++0x00 line.long 0x00 "CFLR,Correctable Fault Location Register" bitfld.long 0x00 26.--29. " WAY ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--25. " SIDE ,Source of the error" "0,1,2,3" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,index of the location where the error occurred" bitfld.long 0x00 0.--1. " TYPE ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP" group.long c15:0x5f++0x00 line.long 0x00 "IADCR,Invalidate All Data Cache Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" group.long c15:0xef++0x00 line.long 0x00 "CSOR,Cache Size Override Register" bitfld.long 0x00 4.--7. " Dcache ,Validation data cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB" bitfld.long 0x00 0.--3. " Icache ,Validation instruction cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB" tree.end width 12. tree "System Performance Monitor" group.long c15:0xc9++0x00 line.long 0x00 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code" hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code" bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DP ,Disable PMCCNTR when prohibited" "No,Yes" textline " " bitfld.long 0x00 4. " X ,Export enable" "Disabled,Enabled" bitfld.long 0x00 3. " D ,Clock divider" "Every cycle,64th cycle" bitfld.long 0x00 2. " C ,Clock counter reset" "No action,Reset" bitfld.long 0x00 1. " P ,Event counter reset" "No action,Reset" textline " " bitfld.long 0x00 0. " E ,Enable" "Disabled,Enabled" group.long c15:0x1c9++0x00 line.long 0x00 "PMCNTENSET,Count Enable Set Register" eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled" group.long c15:0x2c9++0x00 line.long 0x0 "PMCNTENCLR,Count Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled" group.long c15:0x3c9++0x00 line.long 0x0 "PMOVSR,Overflow Flag Status Register" eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow" eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow" eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow" eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow" group.long c15:0x4c9++0x00 line.long 0x0 "PMSWINC,Software Increment Register" eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment" eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment" eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment" group.long c15:0x01d9++0x00 line.long 0x00 "PMXEVTYPER,Event Type Selection Register" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event number selected" group.long c15:0x02d9++0x00 line.long 0x00 "PMXEVCNTR,Event Count Register" group.long c15:0x5c9++0x00 line.long 0x00 "PMSELR,Performance Counter Selection Register" bitfld.long 0x00 0.--4. " SEL ,Counter select" "0,1,2,?..." group.long c15:0xd9++0x00 line.long 0x00 "PMCCNTR,Cycle Count Register" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x0 line.long 0x00 "ESR0,Event Selection Register 0" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x0 line.long 0x00 "PMCR0,Performance Monitor Count Register 0" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x1 line.long 0x00 "ESR1,Event Selection Register 1" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x1 line.long 0x00 "PMCR1,Performance Monitor Count Register 1" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x2 line.long 0x00 "ESR2,Event Selection Register 2" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x2 line.long 0x00 "PMCR2,Performance Monitor Count Register 2" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0xe9++0x00 line.long 0x00 "PMUSERENR,User Enable Register" bitfld.long 0x00 0. " EN ,User mode access to performance monitor and validation registers" "Not allowed,Allowed" group.long c15:0x1e9++0x00 line.long 0x00 "PMINTENSET,Interrupt Enable Set Register" eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" group.long c15:0x2e9++0x00 line.long 0x00 "PMINTENCLR,Interrupt Enable Clear Register" eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" tree "Validation Registers" group.long c15:0x01f++0x00 line.long 0x00 "IRQESR,nVAL IRQ Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested" group.long c15:0x11f++0x00 line.long 0x00 "FIQESR,nVAL FIQ Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested" group.long c15:0x21f++0x00 line.long 0x00 "RESR,nVAL Reset Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested" group.long c15:0x31f++0x00 line.long 0x00 "RESR,VAL Debug Request Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested" group.long c15:0x41f++0x00 line.long 0x00 "IRQECR,VAL IRQ Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested" group.long c15:0x51f++0x00 line.long 0x00 "FIQECR,VAL FIQ Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested" group.long c15:0x61f++0x00 line.long 0x00 "RECR,nVAL Reset Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested" group.long c15:0x71f++0x00 line.long 0x00 "DRECR,VAL Debug Request Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested" tree.end tree.end width 11. width 18. tree "Debug Registers" tree "Processor Identifier Registers" rgroup.long c14:832.++0x00 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number" textline " " hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture" hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number" textline " " hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision" rgroup.long c14:833.++0x00 line.long 0x00 "CACHETYPE,Cache Type Register" bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." rgroup.long c14:834.++0x00 line.long 0x00 "TCMTR,TCM Type Register" group.long c14:835.++0x00 line.long 0x00 "AMIDR,Alias of MIDR" rgroup.long c14:836.++0x00 line.long 0x00 "MPUTR,MPU Type Register" rgroup.long c14:837.++0x00 line.long 0x00 "MPIDR,Multiprocessor Affinity Register" group.long c14:838.++0x00 line.long 0x00 "AMIDR0,Alias of MIDR" group.long c14:839.++0x00 line.long 0x00 "AMIDR1,Alias of MIDR" rgroup.long c14:840.++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c14:841.++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup.long c14:842.++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..." rgroup.long c14:843.++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long c14:844.++0x00 line.long 0x00 "ID_MMFR0,Processor Feature Register 0" bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup.long c14:845.++0x00 line.long 0x00 "ID_MMFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..." rgroup.long c14:846.++0x00 line.long 0x00 "ID_MMFR2,Processor Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c14:847.++0x00 line.long 0x00 "ID_MMFR3,Processor Feature Register 3" bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..." rgroup.long c14:848.++0x00 line.long 0x00 "ID_ISAR0,ISA Feature Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c14:849.++0x00 line.long 0x00 "ID_ISAR1,ISA Feature Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..." rgroup.long c14:850.++0x00 line.long 0x00 "ID_ISAR2,ISA Feature Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c14:851.++0x00 line.long 0x00 "ID_ISAR3,ISA Feature Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c14:852.++0x00 line.long 0x00 "ID_ISAR4,ISA Feature Register 4" bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c14:853.++0x00 line.long 0x00 "ID_ISAR5,ISA Feature Register 5" tree.end width 15. tree "Coresight Management Registers" group.long c14:960.++0x00 line.long 0x00 "DBGITCTRL,Integration Mode Control Register" bitfld.long 0x00 0. " INTMODE ,Processor integration mode" "Normal,Integration" group.long c14:1000.++0x00 line.long 0x00 "DBGCLAIMSET,Claim Tag Set Register" hexmask.long.byte 0x00 0.--7. 1. " CTS ,Claim tag set" group.long c14:1001.++0x00 line.long 0x00 "DBGCLAIMCLR,Claim Tag Clear Register" hexmask.long.byte 0x00 0.--7. 1. " CTC ,Claim tag clear" wgroup.long c14:1004.++0x00 line.long 0x00 "DBGLAR,Lock Access Register" rgroup.long c14:1005.++0x00 line.long 0x00 "DBGLSR,Lock Status Register" bitfld.long 0x00 2. " 32BA ,Indicate that a 32-bit access is required to write the key to the DBGLAR" "No,Yes" textline " " bitfld.long 0x00 1. " LB ,Lock bit" "Not locked,Locked" bitfld.long 0x00 0. " LIB ,Lock implemented bit" "Not locked,Locked" rgroup.long c14:1006.++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status Register" bitfld.long 0x00 7. " SNDFI ,Secure non-invasive debug features implemented" "Not implemented,Implemented" bitfld.long 0x00 6. " SNDFE ,Secure non-invasive debug features enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " SIDFI ,Secure invasive debug features implemented" "Not implemented,Implemented" bitfld.long 0x00 4. " SIDFE ,Secure invasive debug features enabled" "Disabled,Enabled" rgroup.long c14:1011.++0x00 line.long 0x00 "DBGDEVTYPE,Device Type Register" hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE ,Subtype" hexmask.long.byte 0x00 0.--3. 1. " MAIN_CLASS ,Main class" tree.end textline " " width 12. rgroup.long c14:0.++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,?..." bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,?..." textline " " bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.byte 0x0 16.--19. 1. " VERSION ,Debug Architecture Version" textline " " bitfld.long 0x0 15. " DEVID ,Debug Device ID" "Low,High" bitfld.long 0x0 14. " NSUHD ,Secure User halting debug-mode" "Low,High" textline " " bitfld.long 0x0 13. " PCSR ,PC Sample register implemented" "Low,High" bitfld.long 0x0 12. " SE ,Security Extensions implemented" "Low,High" textline " " hexmask.long.byte 0x0 4.--7. 1. " VARIANT ,Implementation-defined Variant Number" hexmask.long.byte 0x0 0.--3. 1. " REVISION ,Implementation-defined Revision Number" group.long c14:34.++0x0 line.long 0x00 "DBGDSCREXT,Debug Status and Control Register" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" textline " " bitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle" bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" textline " " bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted" bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Reserved,BKPT Instruction,External Debug Request,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" group.long c14:0x7++0x0 line.long 0x00 "DBGVCR,Debug Vector Catch register" bitfld.long 0x00 7. " FIQVCE_S ,FIQ vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IRQVCE_S ,IRQ vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 4. " DAVCE_S ,Data Abort vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PAVCE_S ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 2. " SVCVCE_S ,SVC vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " UIVCE_S ,Undefined instruction vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 0. " RVCE ,Reset vector catch enable" "Disabled,Enabled" hgroup.long c14:32.++0x0 hide.long 0x00 "DTRRX,Target -> Host Data Transfer Register" in group.long c14:35.++0x00 line.long 0x0 "DTRTX,Host -> Target Data Transfer Register" hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data" group.long c14:10.++0x0 line.long 0x00 "DBGDSCCR,Debug State Cache Control Register" bitfld.long 0x00 2. " NWT ,Write through disable" "No,Yes" bitfld.long 0x00 1. " NIL ,L1 instruction cache line-fills disable" "No,Yes" textline " " bitfld.long 0x00 0. " NDL ,L1 data cache line-fills disable" "No,Yes" wgroup.long c14:33.++0x0 line.long 0x00 "DBGITR,Instruction Transfer Register" wgroup.long c14:36.++0x0 line.long 0x00 "DBGDRCR,Debug Run Control Register" bitfld.long 0x00 4. " CMR ,Cancel memory requests" "Not cancel,Cancel" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear" textline " " bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear" bitfld.long 0x00 1. " RR ,Restart request" "No effect,Restart" textline " " bitfld.long 0x00 0. " HR ,Halt request" "No effect,Halt" textline " " rgroup.long c14:193.++0x0 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 1. " LOCK_IMP_BIT ,Indicate whether the OS lock functionality is implemented" "Not implemented,Implemented" group.long c14:196.++0x0 line.long 0x00 "DBGPRCR,Device Power-down and Reset Control Register" bitfld.long 0x00 2. " HCWR ,Hold core warm reset" "Not held,Held" textline " " bitfld.long 0x00 1. " CWRR ,Reset reguest" "Not requested,Requested" bitfld.long 0x00 0. " CORENPDRQ ,Core no powerdown request" "Power-down,Emulate" rgroup.long c14:197.++0x0 line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register" bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Not reset,Reset" bitfld.long 0x00 2. " R ,Reset Status" "No reset,Reset" textline " " bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Not reset,Reset" bitfld.long 0x00 0. " PU ,Power-up Status" "Powered down,Powered up" tree.end width 7. tree "Breakpoint Registers" group.long c14:64.++0x0 line.long 0x00 "BVR0,Breakpoint Value 0 Register" hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0" group.long c14:80.++0x0 line.long 0x00 "BCR0,Breakpoint Control 0 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:65.++0x0 line.long 0x00 "BVR1,Breakpoint Value 1 Register" hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1" group.long c14:81.++0x0 line.long 0x00 "BCR1,Breakpoint Control 1 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:66.++0x0 line.long 0x00 "BVR2,Breakpoint Value 2 Register" hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2" group.long c14:82.++0x0 line.long 0x00 "BCR2,Breakpoint Control 2 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:67.++0x0 line.long 0x00 "BVR3,Breakpoint Value 3 Register" hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3" group.long c14:83.++0x0 line.long 0x00 "BCR3,Breakpoint Control 3 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:68.++0x0 line.long 0x00 "BVR4,Breakpoint Value 4 Register" hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4" group.long c14:84.++0x0 line.long 0x00 "BCR4,Breakpoint Control 4 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:69.++0x0 line.long 0x00 "BVR5,Breakpoint Value 5 Register" hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5" group.long c14:85.++0x0 line.long 0x00 "BCR5,Breakpoint Control 5 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:70.++0x0 line.long 0x00 "BVR6,Breakpoint Value 6 Register" hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6" group.long c14:86.++0x0 line.long 0x00 "BCR6,Breakpoint Control 6 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:71.++0x0 line.long 0x00 "BVR7,Breakpoint Value 7 Register" hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7" group.long c14:87.++0x0 line.long 0x00 "BCR7,Breakpoint Control 7 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" tree.end tree "Watchpoint Control Registers" group.long c14:96.++0x0 line.long 0x00 "WVR0,Watchpoint Value 0 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:112.++0x0 line.long 0x00 "WCR0,Watchpoint Control 0 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:97.++0x0 line.long 0x00 "WVR1,Watchpoint Value 1 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:113.++0x0 line.long 0x00 "WCR1,Watchpoint Control 1 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:98.++0x0 line.long 0x00 "WVR2,Watchpoint Value 2 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:114.++0x0 line.long 0x00 "WCR2,Watchpoint Control 2 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:99.++0x0 line.long 0x00 "WVR3,Watchpoint Value 3 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:115.++0x0 line.long 0x00 "WCR3,Watchpoint Control 3 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:100.++0x0 line.long 0x00 "WVR4,Watchpoint Value 4 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:116.++0x0 line.long 0x00 "WCR4,Watchpoint Control 4 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:101.++0x0 line.long 0x00 "WVR5,Watchpoint Value 5 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:117.++0x0 line.long 0x00 "WCR5,Watchpoint Control 5 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:102.++0x0 line.long 0x00 "WVR6,Watchpoint Value 6 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:118.++0x0 line.long 0x00 "WCR6,Watchpoint Control 6 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:103.++0x0 line.long 0x00 "WVR7,Watchpoint Value 7 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:119.++0x0 line.long 0x00 "WCR7,Watchpoint Control 7 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:6.++0x0 line.long 0x00 "WFAR ,Watchpoint Fault Address Register" hexmask.long 0x00 1.--31. 0x2 " WFAR ,Address of the watchpointed instruction" tree.end width 11. AUTOINDENT.POP tree.end elif (CORENAME()=="CORTEXM4F") tree.close "Core Registers (Cortex-M4F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end endif endif sif (CPUFAMILY()=="C7000") tree.close "Core Registers (c71x)" sif (FILE.EXIST(~~/perc71x.per)) INCLUDE ~~/perc71x.per else base AVM:0x00000000 wgroup AVM:0x00++0 textline " Peripheral File Notification - " sif (CORENAME()=="C75X") button "show missing files" "DIALOG.MESSAGE ""Please check your installation for the possibly missing files: perc75x.per""" else button "show missing files" "DIALOG.MESSAGE ""Please check your installation for the possibly missing files: perc71x.per""" endif textline " ---------------------------------------------------------------" textline " The peripheral file for this SoC cannot be displayed. " textline " Possible reasons are: " textline " - it is missing in the local installation or under development " textline " - it is confidential " textline " " textline " As fallback only the core registers are shown. " textline " Please check www.lauterbach.com/scripts.html " textline " or contact support@lauterbach.com . " textline " " endif tree.end endif AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 sif (cpuis("AM68Ax-CR5-MAIN")||cpuis("TDA4AL88-CR5-MAIN")||cpuis("TDA4VE88-CR5-MAIN0")||cpuis("TDA4VE88-CR5-MAIN1")) tree "ARMSS" base ad:0x0 sif (cpuis("TDA4VE88-CR5-MAIN0")||cpuis("TDA4AL88-CR5-MAIN")||cpuis("AM68Ax-CR5-MAIN")||cpuis("TDA4VE88-CR5-MAIN1")) tree "ARMSS_RAT_CFG" base ad:0xFF90000 rgroup.long 0x0++0x7 line.long 0x0 "RAT_PID,This register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." line.long 0x4 "RAT_CONFIG,This register contains the configuration values for the module." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved." hexmask.long.byte 0x4 16.--23. 1. "ADDR_WIDTH,Number of address bits." hexmask.long.byte 0x4 8.--15. 1. "ADDRS,Number of addresses." hexmask.long.byte 0x4 0.--7. 1. "REGIONS,Number of regions." rgroup.long 0x20++0xF line.long 0x0 "RAT_CTRL_j,This region controls the size and the enable for a region. Offset = 20h + (j * 10h); where j = 0h to Fh." bitfld.long 0x0 31. "EN,Enable for the region." "0,1" hexmask.long 0x0 6.--30. 1. "RESERVED,Reserved." hexmask.long.byte 0x0 0.--5. 1. "SIZE,Size of the region in address bits." line.long 0x4 "RAT_BASE_j,This register is used for the base address for a region. This is the source address for matching to a region. Offset = 24h + (j * 10h); where j = 0h to Fh." hexmask.long 0x4 0.--31. 1. "BASE,Base address for the region. It must be aligned to the programmed size." line.long 0x8 "RAT_TRANS_L_j,This register contains the translated lower address bits for a region. Offset = 28h + (j * 10h); where j = 0h to Fh." hexmask.long 0x8 0.--31. 1. "LOWER,Translated lower address bits for the region. It must be aligned to the programmed size." line.long 0xC "RAT_TRANS_U_j,This register contains the translated upper address bits for a region. Offset = 2Ch + (j * 10h); where j = 0h to Fh" hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved." hexmask.long.word 0xC 0.--15. 1. "UPPER,Translated upper address bits for the region." rgroup.long 0x804++0x3 line.long 0x0 "RAT_DESTINATION_ID,This register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." rgroup.long 0x820++0x3 line.long 0x0 "RAT_EXCEPTION_LOGGING_CONTROL,This register controls the exception logging." hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x824++0x17 line.long 0x0 "RAT_EXCEPTION_LOGGING_HEADER0,This register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "RAT_EXCEPTION_LOGGING_HEADER1,This register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED,Reserved." line.long 0x8 "RAT_EXCEPTION_LOGGING_DATA0,This register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "RAT_EXCEPTION_LOGGING_DATA1,This register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 12 bits." line.long 0x10 "RAT_EXCEPTION_LOGGING_DATA2,This register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED,Reserved." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED,Reserved." "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "RAT_EXCEPTION_LOGGING_DATA3,This register contains the fourth word of the data. Reading this register will clear the error pending bit." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED,Reserved." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x840++0x13 line.long 0x0 "RAT_EXCEPTION_PEND_SET,This register allows to set the exception pending signal." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pending signal." "0,1" line.long 0x4 "RAT_EXCEPTION_PEND_CLEAR,This register allows to clear the pend signal." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pending signal." "0,1" line.long 0x8 "RAT_EXCEPTION_ENABLE_SET,This register allows to set the interrupt enable signal." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "RAT_EXCEPTION_ENABLE_CLEAR,This register allows to clear the interrupt enable signal." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "RAT_EOI_REG,EOI Register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt.." hexmask.long.word 0x10 16.--31. 1. "RESERVED,Reserved." hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI value." tree.end endif sif (cpuis("TDA4VE88-CR5-MAIN0")||cpuis("TDA4AL88-CR5-MAIN")||cpuis("AM68Ax-CR5-MAIN")||cpuis("TDA4VE88-CR5-MAIN1")) tree "ARMSS_VIC_CFG" base ad:0xFF80000 rgroup.long 0x0++0x27 line.long 0x0 "VIM_PID,This register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." line.long 0x4 "VIM_INFO,This contains information about the configuration of the VIM." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.word 0x4 0.--10. 1. "INTERRUPTS,Indicates the number of interrupts supported by the VIM." line.long 0x8 "VIM_PRIIRQ,This register contains the number of the highest priority pending IRQ." bitfld.long 0x8 31. "VALID,This field indicates if the NUM field of this register is valid." "0,1" hexmask.long.word 0x8 20.--30. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0x8 16.--19. 1. "PRI,This field indicates the priority of the pending IRQ interrupt." hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.word 0x8 0.--9. 1. "NUM,This field indicates the interrupt number of the pending IRQ interrupt with the highest priority." line.long 0xC "VIM_PRIFIQ,This register contains the number of the highest priority pending FIQ." bitfld.long 0xC 31. "VALID,This field indicates if the NUM field of this register is valid." "0,1" hexmask.long.word 0xC 20.--30. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0xC 16.--19. 1. "PRI,This field indicates the priority of the pending FIQ interrupt." hexmask.long.byte 0xC 10.--15. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.word 0xC 0.--9. 1. "NUM,This field indicates the interrupt number of the pending FIQ interrupt with the highest priority." line.long 0x10 "VIM_IRQGSTS,This register indicates which groups of interrupts have pending. unmasked IRQ interrupts." hexmask.long 0x10 0.--31. 1. "STS,This field indicates that one or more interrupts in group M are mapped to IRQ unmasked and pending. Bit 0 corresponds to group 0 bit 1 corresponds to group 1 etc. The interrupts associated with each group are [(M*32)+31:M*32]" line.long 0x14 "VIM_FIQGSTS,This register indicates which groups of interrupts have pending. unmasked FIQ interrupts." hexmask.long 0x14 0.--31. 1. "STS,This field indicates that one or more interrupts in group M are mapped to FIQ unmasked and pending. Bit 0 corresponds to group 0 bit 1 corresponds to group 1 etc. The interrupts associated with each group are [(M*32)+31:M*32]" line.long 0x18 "VIM_IRQVEC,This register contains the 32-bit interrupt vector address of the currently pending IRQ." hexmask.long 0x18 2.--31. 1. "ADDR,This field contains the upper 30 bits of the 32-bit interrupt vector address (addresses must be 32-bit aligned) of the currently pending highest priority IRQ (as indicated by the" bitfld.long 0x18 0.--1. "RESERVED,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.)" "0,1,2,3" line.long 0x1C "VIM_FIQVEC,This register contains the 32-bit interrupt vector address of the currently pending FIQ." hexmask.long 0x1C 2.--31. 1. "ADDR,This field contains the upper 30 bits of the 32-bit interrupt vector address (addresses must be 32-bit aligned) of the currently pending highest priority FIQ (as indicated by the" bitfld.long 0x1C 0.--1. "RESERVED,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.)" "0,1,2,3" line.long 0x20 "VIM_ACTIRQ,This register contains the number of the active IRQ." bitfld.long 0x20 31. "VALID,This field indicates if the NUM field of this register is valid." "0,1" hexmask.long.word 0x20 20.--30. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0x20 16.--19. 1. "PRI,This field indicates the priority of the active IRQ interrupt." hexmask.long.byte 0x20 10.--15. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.word 0x20 0.--9. 1. "NUM,This field indicates the interrupt number of the active IRQ interrupt." line.long 0x24 "VIM_ACTFIQ,This register contains the number of the active FIQ." bitfld.long 0x24 31. "VALID,This field indicates if the NUM field of this register is valid." "0,1" hexmask.long.word 0x24 20.--30. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0x24 16.--19. 1. "PRI,This field indicates the priority of the active FIQ interrupt." hexmask.long.byte 0x24 10.--15. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.word 0x24 0.--9. 1. "NUM,This field indicates the interrupt number of the active FIQ interrupt." rgroup.long 0x30++0x3 line.long 0x0 "VIM_DEDVEC,This register contains the 32-bit interrupt vector address to be used as a default in case of a DED error in any of the vectors." hexmask.long 0x0 2.--31. 1. "ADDR,This field contains the upper 30 bits of the 32-bit interrupt vector address (the address must be 32-bit aligned) of an interrupt to be used if an uncorrectable double-bit error (DED) is detected in any of the interrupt vector addresses." rbitfld.long 0x0 0.--1. "RESERVED,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.)" "0,1,2,3" rgroup.long 0x400++0x1F line.long 0x0 "VIM_RAW_j,This register indicates the raw status of the events in group M. Offset = 400h + (j * 20h); where j = 0h to Fh." hexmask.long 0x0 0.--31. 1. "STS,This is the raw status of the events in group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x4 "VIM_STS_j,This register indicates the masked status of the events in group M. Offset = 404h + (j * 20h); where j = 0h to Fh." hexmask.long 0x4 0.--31. 1. "MSK,This is the masked status of the events in group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x8 "VIM_INTR_EN_SET_j,This register is used to enable the mask for the events in group M. Offset = 408h + (j * 20h); where j = 0h to Fh." hexmask.long 0x8 0.--31. 1. "MSK,This field is used to enable the mask of events in group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0xC "VIM_INTR_EN_CLR_j,This register is used to disable the mask for the events in group M. Offset = 40Ch + (j * 20h); where j = 0h to Fh." hexmask.long 0xC 0.--31. 1. "MSK,This field is used to disable the mask of events in group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x10 "VIM_IRQSTS_j,This register indicates the masked status of the events in Group M that are also mapped as IRQs. Offset = 410h + (j * 20h); where j = 0h to Fh." hexmask.long 0x10 0.--31. 1. "MSK,This is the masked status of the events in group M that are mapped to IRQ. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x14 "VIM_FIQSTS_j,This register indicates the masked status of the events in group M that are also mapped as FIQs. Offset = 414h + (j * 20h); where j = 0h to Fh." hexmask.long 0x14 0.--31. 1. "MSK,This is the masked status of the events in group M that are mapped to FIQ. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x18 "VIM_INTMAP_j,This register is used to map interrupts as IRQ or FIQ. Offset = 418h + (j * 20h); where j = 0h to Fh." hexmask.long 0x18 0.--31. 1. "MSK,This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x1C "VIM_INTTYPE_j,This register indicates whether an interrupt is a pulse or level source. Offset = 41Ch + (j * 20h); where j = 0h to Fh." hexmask.long 0x1C 0.--31. 1. "MSK,This field is used to indicate whether the source of an interrupt is a level (default) or a pulse for event group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." rgroup.long 0x1000++0x3 line.long 0x0 "VIM_PRI_INT_j,This register is used to set the priority of interrupt Q. Offset = 1000h + (j * 4h); where j = 0h to 1FFh." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0x0 0.--3. 1. "VAL,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration." rgroup.long 0x2000++0x3 line.long 0x0 "VIM_VEC_INT_j,This register contains the vector address associated with interrupt Q. Offset = 2000h + (j * 4h); where j = 0h to 1FFh." hexmask.long 0x0 2.--31. 1. "VAL,These are the upper 30 bits of the 32-bit vector address associated with interrupt Q. It is the address that will be reflected in the" rbitfld.long 0x0 0.--1. "RESERVED,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.)" "0,1,2,3" tree.end endif tree.end endif tree "atl0_REG (atl0_REG)" base ad:0x31F0000 rgroup.long 0x0++0x3 line.long 0x0 "REG_REVISION,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x200++0x3 line.long 0x0 "REG_ATL0_PPMR,The PPM register is used by the Audio re-timing code. The DAC over-sampling clock will slow down or speed up by the PPM written to bits [8:0]." bitfld.long 0x0 15. "PPM_SD,1 = Slow down 0 = Speed up" "0: Speed up,1: Slow down" hexmask.long.word 0x0 0.--8. 1. "PPM_SET,This is the 9-bit parts-per-million value in the adjusting circuit. PPM adjustment = PPMSET/2^20" rgroup.long 0x204++0x3 line.long 0x0 "REG_ATL0_BBSR,The measuring circuit produces a 16-bit Sample Count. Its inputs are the Audio IIS Word Select (AWS) and the Baseband IIS Word Select (BWS) from their respective MCASP pins. The sample count is a read-only register." hexmask.long.word 0x0 0.--15. 1. "SMP_CNT,This is the 16-bit sample count from the measuring circuit" rgroup.long 0x208++0x3 line.long 0x0 "REG_ATL0_ATLCR,The modem Clock Divide Select bit is used during factory calibration of the radio to match latency between the analog and digital signal paths. The ATL Internal Divider divides down the ATL master clock to make ATCLK." bitfld.long 0x0 5. "CLK_DIV_SEL,0: MODCLK = AWS divided by 2^16 1: MODCLK = AWS divided by 2^12" "0: MODCLK = AWS divided by 2^16,1: MODCLK = AWS divided by 2^12" hexmask.long.byte 0x0 0.--4. 1. "INT_DIV,Sets ratio of ATLPCLK to ATCLK" rgroup.long 0x210++0xF line.long 0x0 "REG_ATL0_SWEN,The software enable register is used to enable/disable the ATL." bitfld.long 0x0 0. "ENABLE,When disabled the ATL registers are forced to known states for simulation purposes. Runtime startup doesn't require initial values because measurement is relative to an arbitrary initial value. All registers are reset to zero except ATLCR.INT_DIV.." "0,1" line.long 0x4 "REG_ATL0_BWSMUX,The Baseband IIS Word Select mux select control register" hexmask.long.byte 0x4 0.--3. 1. "SELECT,BWS input select: 0000: atl_io_port_bws[0] 0001: atl_io_port_bws[1] 0010: atl_io_port_bws[2] 0011: atl_io_port_bws[3] 0100: atl_io_port_bws[4] 0101: atl_io_port_bws[5] 0110: atl_io_port_bws[6] 0111: atl_io_port_bws[7] 1000:.." line.long 0x8 "REG_ATL0_AWSMUX,The Audio IIS Word Select mux select control register" hexmask.long.byte 0x8 0.--3. 1. "SELECT,AWS input select: 0000: atl_io_port_aws[0] 0001: atl_io_port_aws[1] 0010: atl_io_port_aws[2] 0011: atl_io_port_aws[3] 0100: atl_io_port_aws[4] 0101: atl_io_port_aws[5] 0110: atl_io_port_aws[6] 0111: atl_io_port_aws[7] 1000:.." line.long 0xC "REG_ATL0_PCLKMUX,ATL core input clock mux select control register" bitfld.long 0xC 0. "SELECT,ATL[0-3] core clock select: 0: vbus_clk 1: atl_clk" "0: vbus_clk,1: atl_clk" rgroup.long 0x280++0x3 line.long 0x0 "REG_ATL1_PPMR,The PPM register is used by the Audio re-timing code. The DAC over-sampling clock will slow down or speed up by the PPM written to bits [8:0]." bitfld.long 0x0 15. "PPM_SD,1 = Slow down 0 = Speed up" "0: Speed up,1: Slow down" hexmask.long.word 0x0 0.--8. 1. "PPM_SET,This is the 9-bit parts-per-million value in the adjusting circuit. PPM adjustment = PPMSET/2^20" rgroup.long 0x284++0x3 line.long 0x0 "REG_ATL1_BBSR,The measuring circuit produces a 16-bit Sample Count. Its inputs are the Audio IIS Word Select (AWS) and the Baseband IIS Word Select (BWS) from their respective MCASP pins. The sample count is a read-only register." hexmask.long.word 0x0 0.--15. 1. "SMP_CNT,This is the 16-bit sample count from the measuring circuit" rgroup.long 0x288++0x3 line.long 0x0 "REG_ATL1_ATLCR,The modem Clock Divide Select bit is used during factory calibration of the radio to match latency between the analog and digital signal paths. The ATL Internal Divider divides down the ATL master clock to make ATCLK." bitfld.long 0x0 5. "CLK_DIV_SEL,0: MODCLK = AWS divided by 2^16 1: MODCLK = AWS divided by 2^12" "0: MODCLK = AWS divided by 2^16,1: MODCLK = AWS divided by 2^12" hexmask.long.byte 0x0 0.--4. 1. "INT_DIV,Sets ratio of ATLPCLK to ATCLK" rgroup.long 0x290++0xF line.long 0x0 "REG_ATL1_SWEN,The software enable register is used to enable/disable the ATL." bitfld.long 0x0 0. "ENABLE,When disabled the ATL registers are forced to known states for simulation purposes. Runtime startup doesn't require initial values because measurement is relative to an arbitrary initial value. All registers are reset to zero except ATLCR.INT_DIV.." "0,1" line.long 0x4 "REG_ATL1_BWSMUX,The Baseband IIS Word Select mux select control register" hexmask.long.byte 0x4 0.--3. 1. "SELECT,BWS input select: 0000: atl_io_port_bws[0] 0001: atl_io_port_bws[1] 0010: atl_io_port_bws[2] 0011: atl_io_port_bws[3] 0100: atl_io_port_bws[4] 0101: atl_io_port_bws[5] 0110: atl_io_port_bws[6] 0111: atl_io_port_bws[7] 1000:.." line.long 0x8 "REG_ATL1_AWSMUX,The Audio IIS Word Select mux select control register" hexmask.long.byte 0x8 0.--3. 1. "SELECT,AWS input select: 0000: atl_io_port_aws[0] 0001: atl_io_port_aws[1] 0010: atl_io_port_aws[2] 0011: atl_io_port_aws[3] 0100: atl_io_port_aws[4] 0101: atl_io_port_aws[5] 0110: atl_io_port_aws[6] 0111: atl_io_port_aws[7] 1000:.." line.long 0xC "REG_ATL1_PCLKMUX,ATL core input clock mux select control register" bitfld.long 0xC 0. "SELECT,Non-functional" "0,1" rgroup.long 0x300++0x3 line.long 0x0 "REG_ATL2_PPMR,The PPM register is used by the Audio re-timing code. The DAC over-sampling clock will slow down or speed up by the PPM written to bits [8:0]." bitfld.long 0x0 15. "PPM_SD,1 = Slow down 0 = Speed up" "0: Speed up,1: Slow down" hexmask.long.word 0x0 0.--8. 1. "PPM_SET,This is the 9-bit parts-per-million value in the adjusting circuit. PPM adjustment = PPMSET/2^20" rgroup.long 0x304++0x3 line.long 0x0 "REG_ATL2_BBSR,The measuring circuit produces a 16-bit Sample Count. Its inputs are the Audio IIS Word Select (AWS) and the Baseband IIS Word Select (BWS) from their respective MCASP pins. The sample count is a read-only register." hexmask.long.word 0x0 0.--15. 1. "SMP_CNT,This is the 16-bit sample count from the measuring circuit" rgroup.long 0x308++0x3 line.long 0x0 "REG_ATL2_ATLCR,The modem Clock Divide Select bit is used during factory calibration of the radio to match latency between the analog and digital signal paths. The ATL Internal Divider divides down the ATL master clock to make ATCLK." bitfld.long 0x0 5. "CLK_DIV_SEL,0: MODCLK = AWS divided by 2^16 1: MODCLK = AWS divided by 2^12" "0: MODCLK = AWS divided by 2^16,1: MODCLK = AWS divided by 2^12" hexmask.long.byte 0x0 0.--4. 1. "INT_DIV,Sets ratio of ATLPCLK to ATCLK" rgroup.long 0x310++0xF line.long 0x0 "REG_ATL2_SWEN,The software enable register is used to enable/disable the ATL." bitfld.long 0x0 0. "ENABLE,When disabled the ATL registers are forced to known states for simulation purposes. Runtime startup doesn't require initial values because measurement is relative to an arbitrary initial value. All registers are reset to zero except ATLCR.INT_DIV.." "0,1" line.long 0x4 "REG_ATL2_BWSMUX,The Baseband IIS Word Select mux select control register" hexmask.long.byte 0x4 0.--3. 1. "SELECT,BWS input select: 0000: atl_io_port_bws[0] 0001: atl_io_port_bws[1] 0010: atl_io_port_bws[2] 0011: atl_io_port_bws[3] 0100: atl_io_port_bws[4] 0101: atl_io_port_bws[5] 0110: atl_io_port_bws[6] 0111: atl_io_port_bws[7] 1000:.." line.long 0x8 "REG_ATL2_AWSMUX,The Audio IIS Word Select mux select control register" hexmask.long.byte 0x8 0.--3. 1. "SELECT,AWS input select: 0000: atl_io_port_aws[0] 0001: atl_io_port_aws[1] 0010: atl_io_port_aws[2] 0011: atl_io_port_aws[3] 0100: atl_io_port_aws[4] 0101: atl_io_port_aws[5] 0110: atl_io_port_aws[6] 0111: atl_io_port_aws[7] 1000:.." line.long 0xC "REG_ATL2_PCLKMUX,ATL core input clock mux select control register" bitfld.long 0xC 0. "SELECT,Non-functional" "0,1" rgroup.long 0x380++0x3 line.long 0x0 "REG_ATL3_PPMR,The PPM register is used by the Audio re-timing code. The DAC over-sampling clock will slow down or speed up by the PPM written to bits [8:0]." bitfld.long 0x0 15. "PPM_SD,1 = Slow down 0 = Speed up" "0: Speed up,1: Slow down" hexmask.long.word 0x0 0.--8. 1. "PPM_SET,This is the 9-bit parts-per-million value in the adjusting circuit. PPM adjustment = PPMSET/2^20" rgroup.long 0x384++0x3 line.long 0x0 "REG_ATL3_BBSR,The measuring circuit produces a 16-bit Sample Count. Its inputs are the Audio IIS Word Select (AWS) and the Baseband IIS Word Select (BWS) from their respective MCASP pins. The sample count is a read-only register." hexmask.long.word 0x0 0.--15. 1. "SMP_CNT,This is the 16-bit sample count from the measuring circuit" rgroup.long 0x388++0x3 line.long 0x0 "REG_ATL3_ATLCR,The modem Clock Divide Select bit is used during factory calibration of the radio to match latency between the analog and digital signal paths. The ATL Internal Divider divides down the ATL master clock to make ATCLK." bitfld.long 0x0 5. "CLK_DIV_SEL,0: MODCLK = AWS divided by 2^16 1: MODCLK = AWS divided by 2^12" "0: MODCLK = AWS divided by 2^16,1: MODCLK = AWS divided by 2^12" hexmask.long.byte 0x0 0.--4. 1. "INT_DIV,Sets ratio of ATLPCLK to ATCLK" rgroup.long 0x390++0xF line.long 0x0 "REG_ATL3_SWEN,The software enable register is used to enable/disable the ATL." bitfld.long 0x0 0. "ENABLE,When disabled the ATL registers are forced to known states for simulation purposes. Runtime startup doesn't require initial values because measurement is relative to an arbitrary initial value. All registers are reset to zero except ATLCR.INT_DIV.." "0,1" line.long 0x4 "REG_ATL3_BWSMUX,The Baseband IIS Word Select mux select control register" hexmask.long.byte 0x4 0.--3. 1. "SELECT,BWS input select: 0000: atl_io_port_bws[0] 0001: atl_io_port_bws[1] 0010: atl_io_port_bws[2] 0011: atl_io_port_bws[3] 0100: atl_io_port_bws[4] 0101: atl_io_port_bws[5] 0110: atl_io_port_bws[6] 0111: atl_io_port_bws[7] 1000:.." line.long 0x8 "REG_ATL3_AWSMUX,The Audio IIS Word Select mux select control register" hexmask.long.byte 0x8 0.--3. 1. "SELECT,AWS input select: 0000: atl_io_port_aws[0] 0001: atl_io_port_aws[1] 0010: atl_io_port_aws[2] 0011: atl_io_port_aws[3] 0100: atl_io_port_aws[4] 0101: atl_io_port_aws[5] 0110: atl_io_port_aws[6] 0111: atl_io_port_aws[7] 1000:.." line.long 0xC "REG_ATL3_PCLKMUX,ATL core input clock mux select control register" bitfld.long 0xC 0. "SELECT,Non-functional" "0,1" tree.end tree "CBASS" base ad:0x0 tree "CBASS_AC" tree "CBASS_AC_CFG0" tree "CBASS_AC_CFG0_ERR (CBASS_AC_CFG0_ERR)" base ad:0x2A84000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end tree "CBASS_AC_CFG0_GLB (CBASS_AC_CFG0_GLB)" base ad:0x45B22C00 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x20++0x3 line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x40++0x7 line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree.end tree "CBASS_AC_CFG_NONSAFE0" tree "CBASS_AC_CFG_NONSAFE0_ERR (CBASS_AC_CFG_NONSAFE0_ERR)" base ad:0x2A97000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end tree "CBASS_AC_CFG_NONSAFE0_GLB (CBASS_AC_CFG_NONSAFE0_GLB)" base ad:0x45B25000 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x20++0x3 line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x40++0x7 line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree.end tree "CBASS_AC_NONSAFE0" tree "CBASS_AC_NONSAFE0_ERR (CBASS_AC_NONSAFE0_ERR)" base ad:0x2A85000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end tree "CBASS_AC_NONSAFE0_GLB (CBASS_AC_NONSAFE0_GLB)" base ad:0x45B08000 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x20++0x3 line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x40++0x7 line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree "CBASS_AC_NONSAFE0_ISC (CBASS_AC_NONSAFE0_ISC)" base ad:0x458C0000 rgroup.long 0xC00++0x3 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC10++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC30++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC50++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC70++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC90++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 4 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 4 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 4 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 4 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 5 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1000++0x3 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1010++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1030++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1050++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1070++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1090++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 4 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 4 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 4 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 4 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 5 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1C00++0x3 line.long 0x0 "ISC_REGS_Ivpac_top_main_0_ldc0_m_mst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ivpac_top_main_0.ldc0_m_mst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1C10++0x13 line.long 0x0 "ISC_REGS_Ivpac_top_main_0_ldc0_m_mst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ivpac_top_main_0.ldc0_m_mst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ivpac_top_main_0_ldc0_m_mst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ivpac_top_main_0.ldc0_m_mst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ivpac_top_main_0_ldc0_m_mst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ivpac_top_main_0.ldc0_m_mst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ivpac_top_main_0_ldc0_m_mst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ivpac_top_main_0.ldc0_m_mst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ivpac_top_main_0_ldc0_m_mst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ivpac_top_main_0.ldc0_m_mst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1C30++0x13 line.long 0x0 "ISC_REGS_Ivpac_top_main_0_ldc0_m_mst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ivpac_top_main_0.ldc0_m_mst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ivpac_top_main_0_ldc0_m_mst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ivpac_top_main_0.ldc0_m_mst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ivpac_top_main_0_ldc0_m_mst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ivpac_top_main_0.ldc0_m_mst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ivpac_top_main_0_ldc0_m_mst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ivpac_top_main_0.ldc0_m_mst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ivpac_top_main_0_ldc0_m_mst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ivpac_top_main_0.ldc0_m_mst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1C50++0x13 line.long 0x0 "ISC_REGS_Ivpac_top_main_0_ldc0_m_mst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ivpac_top_main_0.ldc0_m_mst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ivpac_top_main_0_ldc0_m_mst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ivpac_top_main_0.ldc0_m_mst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ivpac_top_main_0_ldc0_m_mst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ivpac_top_main_0.ldc0_m_mst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ivpac_top_main_0_ldc0_m_mst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ivpac_top_main_0.ldc0_m_mst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ivpac_top_main_0_ldc0_m_mst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ivpac_top_main_0.ldc0_m_mst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2000++0x3 line.long 0x0 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2010++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2030++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2050++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2070++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2090++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 4 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 4 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 4 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 4 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_5_control,The ISC Region 5 Control Register defines the control fields for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 5 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x20B0++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_5_start_address_l,The ISC Region 5 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 5 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_5_start_address_h,The ISC Region 5 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 5 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_5_end_address_l,The ISC Region 5 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 5 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_5_end_address_h,The ISC Region 5 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 5 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_6_control,The ISC Region 6 Control Register defines the control fields for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 6 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x20D0++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_6_start_address_l,The ISC Region 6 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 6 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_6_start_address_h,The ISC Region 6 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 6 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_6_end_address_l,The ISC Region 6 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 6 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_6_end_address_h,The ISC Region 6 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 6 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_7_control,The ISC Region 7 Control Register defines the control fields for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 7 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x20F0++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_7_start_address_l,The ISC Region 7 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 7 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_7_start_address_h,The ISC Region 7 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 7 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_7_end_address_l,The ISC Region 7 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 7 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_7_end_address_h,The ISC Region 7 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 7 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_8_control,The ISC Region 8 Control Register defines the control fields for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 8 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2110++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_8_start_address_l,The ISC Region 8 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 8 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_8_start_address_h,The ISC Region 8 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 8 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_8_end_address_l,The ISC Region 8 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 8 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_8_end_address_h,The ISC Region 8 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 8 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_9_control,The ISC Region 9 Control Register defines the control fields for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 9 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2130++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_9_start_address_l,The ISC Region 9 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 9 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_9_start_address_h,The ISC Region 9 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 9 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_9_end_address_l,The ISC Region 9 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 9 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_9_end_address_h,The ISC Region 9 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 9 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ik3_dss_main_0.dss_inst0_vbusm_dma region 10 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2400++0x3 line.long 0x0 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2410++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2430++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2450++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2470++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2490++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 4 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 4 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 4 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 4 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_5_control,The ISC Region 5 Control Register defines the control fields for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 5 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x24B0++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_5_start_address_l,The ISC Region 5 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 5 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_5_start_address_h,The ISC Region 5 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 5 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_5_end_address_l,The ISC Region 5 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 5 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_5_end_address_h,The ISC Region 5 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 5 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_6_control,The ISC Region 6 Control Register defines the control fields for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 6 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x24D0++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_6_start_address_l,The ISC Region 6 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 6 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_6_start_address_h,The ISC Region 6 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 6 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_6_end_address_l,The ISC Region 6 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 6 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_6_end_address_h,The ISC Region 6 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 6 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_7_control,The ISC Region 7 Control Register defines the control fields for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 7 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x24F0++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_7_start_address_l,The ISC Region 7 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 7 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_7_start_address_h,The ISC Region 7 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 7 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_7_end_address_l,The ISC Region 7 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 7 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_7_end_address_h,The ISC Region 7 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 7 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_8_control,The ISC Region 8 Control Register defines the control fields for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 8 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2510++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_8_start_address_l,The ISC Region 8 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 8 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_8_start_address_h,The ISC Region 8 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 8 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_8_end_address_l,The ISC Region 8 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 8 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_8_end_address_h,The ISC Region 8 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 8 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_9_control,The ISC Region 9 Control Register defines the control fields for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 9 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2530++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_9_start_address_l,The ISC Region 9 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 9 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_9_start_address_h,The ISC Region 9 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 9 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_9_end_address_l,The ISC Region 9 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 9 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_9_end_address_h,The ISC Region 9 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 9 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc region 10 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2800++0x3 line.long 0x0 "ISC_REGS_Ivpac_top_main_1_ldc0_m_mst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ivpac_top_main_1.ldc0_m_mst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2810++0x13 line.long 0x0 "ISC_REGS_Ivpac_top_main_1_ldc0_m_mst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ivpac_top_main_1.ldc0_m_mst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ivpac_top_main_1_ldc0_m_mst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ivpac_top_main_1.ldc0_m_mst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ivpac_top_main_1_ldc0_m_mst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ivpac_top_main_1.ldc0_m_mst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ivpac_top_main_1_ldc0_m_mst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ivpac_top_main_1.ldc0_m_mst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ivpac_top_main_1_ldc0_m_mst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ivpac_top_main_1.ldc0_m_mst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2830++0x13 line.long 0x0 "ISC_REGS_Ivpac_top_main_1_ldc0_m_mst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ivpac_top_main_1.ldc0_m_mst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ivpac_top_main_1_ldc0_m_mst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ivpac_top_main_1.ldc0_m_mst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ivpac_top_main_1_ldc0_m_mst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ivpac_top_main_1.ldc0_m_mst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ivpac_top_main_1_ldc0_m_mst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ivpac_top_main_1.ldc0_m_mst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ivpac_top_main_1_ldc0_m_mst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ivpac_top_main_1.ldc0_m_mst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2850++0x13 line.long 0x0 "ISC_REGS_Ivpac_top_main_1_ldc0_m_mst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ivpac_top_main_1.ldc0_m_mst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ivpac_top_main_1_ldc0_m_mst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ivpac_top_main_1.ldc0_m_mst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ivpac_top_main_1_ldc0_m_mst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ivpac_top_main_1.ldc0_m_mst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ivpac_top_main_1_ldc0_m_mst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ivpac_top_main_1.ldc0_m_mst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ivpac_top_main_1_ldc0_m_mst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ivpac_top_main_1.ldc0_m_mst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3400++0x3 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3410++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3430++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3450++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3470++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3490++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 4 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 4 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 4 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 4 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 5 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3800++0x3 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3810++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3830++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3850++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3870++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3890++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 4 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 4 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 4 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 4 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 5 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3C00++0x3 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3C10++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3C30++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3C50++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3C70++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3C90++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 4 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 4 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 4 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 4 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async region 5 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x4000++0x3 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x4010++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x4030++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x4050++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x4070++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x4090++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 4 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 4 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 4 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 4 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async region 5 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x4400++0x3 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x4410++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x4430++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x4450++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x4470++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x4490++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 4 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 4 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 4 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 4 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async region 5 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x4800++0x3 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x4810++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x4830++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x4850++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x4870++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x4890++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 4 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 4 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 4 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 4 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async region 5 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5000++0x3 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5010++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5030++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5050++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5070++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5090++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 4 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 4 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 4 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 4 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_5_control,The ISC Region 5 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 5 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x50B0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_5_start_address_l,The ISC Region 5 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 5 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_5_start_address_h,The ISC Region 5 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 5 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_5_end_address_l,The ISC Region 5 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 5 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_5_end_address_h,The ISC Region 5 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 5 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_6_control,The ISC Region 6 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 6 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x50D0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_6_start_address_l,The ISC Region 6 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 6 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_6_start_address_h,The ISC Region 6 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 6 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_6_end_address_l,The ISC Region 6 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 6 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_6_end_address_h,The ISC Region 6 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 6 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_7_control,The ISC Region 7 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 7 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x50F0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_7_start_address_l,The ISC Region 7 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 7 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_7_start_address_h,The ISC Region 7 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 7 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_7_end_address_l,The ISC Region 7 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 7 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_7_end_address_h,The ISC Region 7 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 7 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_8_control,The ISC Region 8 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 8 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5110++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_8_start_address_l,The ISC Region 8 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 8 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_8_start_address_h,The ISC Region 8 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 8 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_8_end_address_l,The ISC Region 8 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 8 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_8_end_address_h,The ISC Region 8 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 8 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_9_control,The ISC Region 9 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 9 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5130++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_9_start_address_l,The ISC Region 9 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 9 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_9_start_address_h,The ISC Region 9 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 9 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_9_end_address_l,The ISC Region 9 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 9 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_9_end_address_h,The ISC Region 9 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 9 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_10_control,The ISC Region 10 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 10 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5150++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_10_start_address_l,The ISC Region 10 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 10 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_10_start_address_h,The ISC Region 10 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 10 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_10_end_address_l,The ISC Region 10 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 10 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_10_end_address_h,The ISC Region 10 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 10 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_11_control,The ISC Region 11 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 11 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5170++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_11_start_address_l,The ISC Region 11 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 11 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_11_start_address_h,The ISC Region 11 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 11 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_11_end_address_l,The ISC Region 11 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 11 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_11_end_address_h,The ISC Region 11 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 11 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_12_control,The ISC Region 12 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 12 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5190++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_12_start_address_l,The ISC Region 12 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 12 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_12_start_address_h,The ISC Region 12 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 12 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_12_end_address_l,The ISC Region 12 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 12 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_12_end_address_h,The ISC Region 12 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 12 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_13_control,The ISC Region 13 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 13 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x51B0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_13_start_address_l,The ISC Region 13 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 13 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_13_start_address_h,The ISC Region 13 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 13 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_13_end_address_l,The ISC Region 13 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 13 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_13_end_address_h,The ISC Region 13 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 13 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_14_control,The ISC Region 14 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 14 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x51D0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_14_start_address_l,The ISC Region 14 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 14 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_14_start_address_h,The ISC Region 14 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 14 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_14_end_address_l,The ISC Region 14 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 14 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_14_end_address_h,The ISC Region 14 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 14 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_15_control,The ISC Region 15 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 15 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x51F0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_15_start_address_l,The ISC Region 15 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 15 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_15_start_address_h,The ISC Region 15 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 15 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_15_end_address_l,The ISC Region 15 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 15 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_15_end_address_h,The ISC Region 15 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 15 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_16_control,The ISC Region 16 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 16 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5210++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_16_start_address_l,The ISC Region 16 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 16 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_16_start_address_h,The ISC Region 16 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 16 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_16_end_address_l,The ISC Region 16 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 16 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_16_end_address_h,The ISC Region 16 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 16 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_17_control,The ISC Region 17 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 17 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5230++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_17_start_address_l,The ISC Region 17 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 17 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_17_start_address_h,The ISC Region 17 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 17 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_17_end_address_l,The ISC Region 17 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 17 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_17_end_address_h,The ISC Region 17 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 17 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_18_control,The ISC Region 18 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 18 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5250++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_18_start_address_l,The ISC Region 18 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 18 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_18_start_address_h,The ISC Region 18 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 18 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_18_end_address_l,The ISC Region 18 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 18 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_18_end_address_h,The ISC Region 18 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 18 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_19_control,The ISC Region 19 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 19 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5270++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_19_start_address_l,The ISC Region 19 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 19 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_19_start_address_h,The ISC Region 19 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 19 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_19_end_address_l,The ISC Region 19 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 19 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_19_end_address_h,The ISC Region 19 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 19 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_20_control,The ISC Region 20 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 20 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5290++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_20_start_address_l,The ISC Region 20 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 20 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_20_start_address_h,The ISC Region 20 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 20 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_20_end_address_l,The ISC Region 20 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 20 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_20_end_address_h,The ISC Region 20 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 20 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_21_control,The ISC Region 21 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 21 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x52B0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_21_start_address_l,The ISC Region 21 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 21 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_21_start_address_h,The ISC Region 21 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 21 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_21_end_address_l,The ISC Region 21 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 21 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_21_end_address_h,The ISC Region 21 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 21 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_22_control,The ISC Region 22 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 22 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x52D0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_22_start_address_l,The ISC Region 22 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 22 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_22_start_address_h,The ISC Region 22 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 22 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_22_end_address_l,The ISC Region 22 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 22 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_22_end_address_h,The ISC Region 22 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 22 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_23_control,The ISC Region 23 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 23 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x52F0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_23_start_address_l,The ISC Region 23 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 23 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_23_start_address_h,The ISC Region 23 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 23 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_23_end_address_l,The ISC Region 23 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 23 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_23_end_address_h,The ISC Region 23 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 23 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_24_control,The ISC Region 24 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 24 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5310++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_24_start_address_l,The ISC Region 24 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 24 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_24_start_address_h,The ISC Region 24 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 24 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_24_end_address_l,The ISC Region 24 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 24 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_24_end_address_h,The ISC Region 24 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 24 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_25_control,The ISC Region 25 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 25 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5330++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_25_start_address_l,The ISC Region 25 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 25 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_25_start_address_h,The ISC Region 25 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 25 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_25_end_address_l,The ISC Region 25 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 25 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_25_end_address_h,The ISC Region 25 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 25 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_26_control,The ISC Region 26 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 26 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5350++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_26_start_address_l,The ISC Region 26 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 26 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_26_start_address_h,The ISC Region 26 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 26 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_26_end_address_l,The ISC Region 26 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 26 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_26_end_address_h,The ISC Region 26 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 26 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_27_control,The ISC Region 27 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 27 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5370++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_27_start_address_l,The ISC Region 27 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 27 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_27_start_address_h,The ISC Region 27 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 27 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_27_end_address_l,The ISC Region 27 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 27 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_27_end_address_h,The ISC Region 27 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 27 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_28_control,The ISC Region 28 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 28 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5390++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_28_start_address_l,The ISC Region 28 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 28 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_28_start_address_h,The ISC Region 28 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 28 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_28_end_address_l,The ISC Region 28 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 28 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_28_end_address_h,The ISC Region 28 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 28 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_29_control,The ISC Region 29 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 29 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x53B0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_29_start_address_l,The ISC Region 29 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 29 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_29_start_address_h,The ISC Region 29 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 29 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_29_end_address_l,The ISC Region 29 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 29 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_29_end_address_h,The ISC Region 29 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 29 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_30_control,The ISC Region 30 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 30 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x53D0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_30_start_address_l,The ISC Region 30 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 30 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_30_start_address_h,The ISC Region 30 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 30 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_30_end_address_l,The ISC Region 30 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 30 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_30_end_address_h,The ISC Region 30 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 30 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_31_control,The ISC Region 31 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 31 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x53F0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_31_start_address_l,The ISC Region 31 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 31 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_31_start_address_h,The ISC Region 31 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 31 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_31_end_address_l,The ISC Region 31 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 31 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_31_end_address_h,The ISC Region 31 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 31 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_32_control,The ISC Region 32 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 32 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5410++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_32_start_address_l,The ISC Region 32 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 32 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_32_start_address_h,The ISC Region 32 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 32 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_32_end_address_l,The ISC Region 32 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 32 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_32_end_address_h,The ISC Region 32 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 32 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_33_control,The ISC Region 33 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 33 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5430++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_33_start_address_l,The ISC Region 33 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 33 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_33_start_address_h,The ISC Region 33 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 33 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_33_end_address_l,The ISC Region 33 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 33 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_33_end_address_h,The ISC Region 33 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 33 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_34_control,The ISC Region 34 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 34 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5450++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_34_start_address_l,The ISC Region 34 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 34 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_34_start_address_h,The ISC Region 34 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 34 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_34_end_address_l,The ISC Region 34 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 34 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_34_end_address_h,The ISC Region 34 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 34 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_35_control,The ISC Region 35 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 35 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5470++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_35_start_address_l,The ISC Region 35 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 35 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_35_start_address_h,The ISC Region 35 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 35 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_35_end_address_l,The ISC Region 35 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 35 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_35_end_address_h,The ISC Region 35 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 35 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_36_control,The ISC Region 36 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 36 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5490++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_36_start_address_l,The ISC Region 36 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 36 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_36_start_address_h,The ISC Region 36 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 36 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_36_end_address_l,The ISC Region 36 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 36 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_36_end_address_h,The ISC Region 36 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 36 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_37_control,The ISC Region 37 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 37 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x54B0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_37_start_address_l,The ISC Region 37 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 37 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_37_start_address_h,The ISC Region 37 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 37 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_37_end_address_l,The ISC Region 37 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 37 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_37_end_address_h,The ISC Region 37 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 37 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_38_control,The ISC Region 38 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 38 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x54D0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_38_start_address_l,The ISC Region 38 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 38 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_38_start_address_h,The ISC Region 38 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 38 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_38_end_address_l,The ISC Region 38 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 38 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_38_end_address_h,The ISC Region 38 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 38 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_39_control,The ISC Region 39 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 39 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x54F0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_39_start_address_l,The ISC Region 39 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 39 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_39_start_address_h,The ISC Region 39 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 39 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_39_end_address_l,The ISC Region 39 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 39 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_39_end_address_h,The ISC Region 39 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 39 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_40_control,The ISC Region 40 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 40 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5510++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_40_start_address_l,The ISC Region 40 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 40 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_40_start_address_h,The ISC Region 40 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 40 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_40_end_address_l,The ISC Region 40 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 40 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_40_end_address_h,The ISC Region 40 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 40 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_41_control,The ISC Region 41 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 41 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5530++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_41_start_address_l,The ISC Region 41 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 41 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_41_start_address_h,The ISC Region 41 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 41 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_41_end_address_l,The ISC Region 41 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 41 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_41_end_address_h,The ISC Region 41 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 41 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_42_control,The ISC Region 42 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 42 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5550++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_42_start_address_l,The ISC Region 42 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 42 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_42_start_address_h,The ISC Region 42 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 42 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_42_end_address_l,The ISC Region 42 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 42 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_42_end_address_h,The ISC Region 42 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 42 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_43_control,The ISC Region 43 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 43 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5570++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_43_start_address_l,The ISC Region 43 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 43 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_43_start_address_h,The ISC Region 43 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 43 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_43_end_address_l,The ISC Region 43 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 43 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_43_end_address_h,The ISC Region 43 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 43 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_44_control,The ISC Region 44 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 44 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5590++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_44_start_address_l,The ISC Region 44 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 44 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_44_start_address_h,The ISC Region 44 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 44 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_44_end_address_l,The ISC Region 44 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 44 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_44_end_address_h,The ISC Region 44 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 44 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_45_control,The ISC Region 45 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 45 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x55B0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_45_start_address_l,The ISC Region 45 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 45 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_45_start_address_h,The ISC Region 45 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 45 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_45_end_address_l,The ISC Region 45 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 45 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_45_end_address_h,The ISC Region 45 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 45 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_46_control,The ISC Region 46 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 46 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x55D0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_46_start_address_l,The ISC Region 46 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 46 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_46_start_address_h,The ISC Region 46 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 46 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_46_end_address_l,The ISC Region 46 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 46 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_46_end_address_h,The ISC Region 46 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 46 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_47_control,The ISC Region 47 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 47 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x55F0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_47_start_address_l,The ISC Region 47 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 47 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_47_start_address_h,The ISC Region 47 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 47 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_47_end_address_l,The ISC Region 47 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 47 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_47_end_address_h,The ISC Region 47 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 47 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync region 48 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5800++0x3 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5810++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5830++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5850++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5870++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5890++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 4 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 4 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 4 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 4 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_5_control,The ISC Region 5 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 5 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x58B0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_5_start_address_l,The ISC Region 5 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 5 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_5_start_address_h,The ISC Region 5 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 5 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_5_end_address_l,The ISC Region 5 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 5 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_5_end_address_h,The ISC Region 5 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 5 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_6_control,The ISC Region 6 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 6 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x58D0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_6_start_address_l,The ISC Region 6 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 6 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_6_start_address_h,The ISC Region 6 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 6 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_6_end_address_l,The ISC Region 6 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 6 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_6_end_address_h,The ISC Region 6 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 6 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_7_control,The ISC Region 7 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 7 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x58F0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_7_start_address_l,The ISC Region 7 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 7 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_7_start_address_h,The ISC Region 7 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 7 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_7_end_address_l,The ISC Region 7 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 7 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_7_end_address_h,The ISC Region 7 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 7 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_8_control,The ISC Region 8 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 8 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5910++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_8_start_address_l,The ISC Region 8 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 8 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_8_start_address_h,The ISC Region 8 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 8 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_8_end_address_l,The ISC Region 8 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 8 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_8_end_address_h,The ISC Region 8 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 8 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_9_control,The ISC Region 9 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 9 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5930++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_9_start_address_l,The ISC Region 9 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 9 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_9_start_address_h,The ISC Region 9 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 9 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_9_end_address_l,The ISC Region 9 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 9 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_9_end_address_h,The ISC Region 9 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 9 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_10_control,The ISC Region 10 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 10 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5950++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_10_start_address_l,The ISC Region 10 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 10 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_10_start_address_h,The ISC Region 10 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 10 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_10_end_address_l,The ISC Region 10 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 10 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_10_end_address_h,The ISC Region 10 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 10 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_11_control,The ISC Region 11 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 11 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5970++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_11_start_address_l,The ISC Region 11 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 11 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_11_start_address_h,The ISC Region 11 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 11 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_11_end_address_l,The ISC Region 11 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 11 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_11_end_address_h,The ISC Region 11 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 11 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_12_control,The ISC Region 12 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 12 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5990++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_12_start_address_l,The ISC Region 12 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 12 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_12_start_address_h,The ISC Region 12 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 12 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_12_end_address_l,The ISC Region 12 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 12 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_12_end_address_h,The ISC Region 12 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 12 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_13_control,The ISC Region 13 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 13 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x59B0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_13_start_address_l,The ISC Region 13 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 13 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_13_start_address_h,The ISC Region 13 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 13 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_13_end_address_l,The ISC Region 13 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 13 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_13_end_address_h,The ISC Region 13 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 13 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_14_control,The ISC Region 14 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 14 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x59D0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_14_start_address_l,The ISC Region 14 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 14 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_14_start_address_h,The ISC Region 14 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 14 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_14_end_address_l,The ISC Region 14 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 14 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_14_end_address_h,The ISC Region 14 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 14 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_15_control,The ISC Region 15 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 15 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x59F0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_15_start_address_l,The ISC Region 15 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 15 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_15_start_address_h,The ISC Region 15 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 15 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_15_end_address_l,The ISC Region 15 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 15 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_15_end_address_h,The ISC Region 15 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 15 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_16_control,The ISC Region 16 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 16 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5A10++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_16_start_address_l,The ISC Region 16 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 16 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_16_start_address_h,The ISC Region 16 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 16 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_16_end_address_l,The ISC Region 16 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 16 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_16_end_address_h,The ISC Region 16 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 16 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_17_control,The ISC Region 17 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 17 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5A30++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_17_start_address_l,The ISC Region 17 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 17 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_17_start_address_h,The ISC Region 17 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 17 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_17_end_address_l,The ISC Region 17 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 17 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_17_end_address_h,The ISC Region 17 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 17 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_18_control,The ISC Region 18 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 18 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5A50++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_18_start_address_l,The ISC Region 18 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 18 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_18_start_address_h,The ISC Region 18 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 18 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_18_end_address_l,The ISC Region 18 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 18 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_18_end_address_h,The ISC Region 18 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 18 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_19_control,The ISC Region 19 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 19 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5A70++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_19_start_address_l,The ISC Region 19 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 19 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_19_start_address_h,The ISC Region 19 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 19 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_19_end_address_l,The ISC Region 19 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 19 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_19_end_address_h,The ISC Region 19 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 19 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_20_control,The ISC Region 20 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 20 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5A90++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_20_start_address_l,The ISC Region 20 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 20 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_20_start_address_h,The ISC Region 20 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 20 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_20_end_address_l,The ISC Region 20 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 20 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_20_end_address_h,The ISC Region 20 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 20 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_21_control,The ISC Region 21 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 21 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5AB0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_21_start_address_l,The ISC Region 21 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 21 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_21_start_address_h,The ISC Region 21 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 21 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_21_end_address_l,The ISC Region 21 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 21 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_21_end_address_h,The ISC Region 21 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 21 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_22_control,The ISC Region 22 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 22 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5AD0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_22_start_address_l,The ISC Region 22 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 22 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_22_start_address_h,The ISC Region 22 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 22 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_22_end_address_l,The ISC Region 22 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 22 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_22_end_address_h,The ISC Region 22 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 22 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_23_control,The ISC Region 23 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 23 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5AF0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_23_start_address_l,The ISC Region 23 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 23 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_23_start_address_h,The ISC Region 23 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 23 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_23_end_address_l,The ISC Region 23 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 23 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_23_end_address_h,The ISC Region 23 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 23 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_24_control,The ISC Region 24 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 24 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5B10++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_24_start_address_l,The ISC Region 24 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 24 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_24_start_address_h,The ISC Region 24 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 24 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_24_end_address_l,The ISC Region 24 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 24 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_24_end_address_h,The ISC Region 24 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 24 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_25_control,The ISC Region 25 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 25 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5B30++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_25_start_address_l,The ISC Region 25 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 25 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_25_start_address_h,The ISC Region 25 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 25 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_25_end_address_l,The ISC Region 25 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 25 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_25_end_address_h,The ISC Region 25 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 25 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_26_control,The ISC Region 26 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 26 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5B50++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_26_start_address_l,The ISC Region 26 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 26 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_26_start_address_h,The ISC Region 26 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 26 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_26_end_address_l,The ISC Region 26 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 26 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_26_end_address_h,The ISC Region 26 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 26 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_27_control,The ISC Region 27 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 27 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5B70++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_27_start_address_l,The ISC Region 27 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 27 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_27_start_address_h,The ISC Region 27 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 27 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_27_end_address_l,The ISC Region 27 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 27 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_27_end_address_h,The ISC Region 27 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 27 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_28_control,The ISC Region 28 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 28 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5B90++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_28_start_address_l,The ISC Region 28 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 28 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_28_start_address_h,The ISC Region 28 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 28 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_28_end_address_l,The ISC Region 28 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 28 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_28_end_address_h,The ISC Region 28 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 28 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_29_control,The ISC Region 29 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 29 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5BB0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_29_start_address_l,The ISC Region 29 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 29 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_29_start_address_h,The ISC Region 29 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 29 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_29_end_address_l,The ISC Region 29 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 29 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_29_end_address_h,The ISC Region 29 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 29 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_30_control,The ISC Region 30 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 30 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5BD0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_30_start_address_l,The ISC Region 30 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 30 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_30_start_address_h,The ISC Region 30 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 30 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_30_end_address_l,The ISC Region 30 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 30 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_30_end_address_h,The ISC Region 30 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 30 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_31_control,The ISC Region 31 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 31 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5BF0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_31_start_address_l,The ISC Region 31 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 31 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_31_start_address_h,The ISC Region 31 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 31 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_31_end_address_l,The ISC Region 31 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 31 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_31_end_address_h,The ISC Region 31 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 31 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_32_control,The ISC Region 32 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 32 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5C10++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_32_start_address_l,The ISC Region 32 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 32 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_32_start_address_h,The ISC Region 32 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 32 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_32_end_address_l,The ISC Region 32 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 32 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_32_end_address_h,The ISC Region 32 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 32 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_33_control,The ISC Region 33 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 33 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5C30++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_33_start_address_l,The ISC Region 33 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 33 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_33_start_address_h,The ISC Region 33 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 33 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_33_end_address_l,The ISC Region 33 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 33 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_33_end_address_h,The ISC Region 33 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 33 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_34_control,The ISC Region 34 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 34 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5C50++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_34_start_address_l,The ISC Region 34 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 34 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_34_start_address_h,The ISC Region 34 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 34 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_34_end_address_l,The ISC Region 34 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 34 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_34_end_address_h,The ISC Region 34 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 34 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_35_control,The ISC Region 35 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 35 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5C70++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_35_start_address_l,The ISC Region 35 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 35 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_35_start_address_h,The ISC Region 35 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 35 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_35_end_address_l,The ISC Region 35 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 35 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_35_end_address_h,The ISC Region 35 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 35 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_36_control,The ISC Region 36 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 36 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5C90++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_36_start_address_l,The ISC Region 36 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 36 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_36_start_address_h,The ISC Region 36 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 36 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_36_end_address_l,The ISC Region 36 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 36 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_36_end_address_h,The ISC Region 36 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 36 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_37_control,The ISC Region 37 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 37 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5CB0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_37_start_address_l,The ISC Region 37 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 37 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_37_start_address_h,The ISC Region 37 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 37 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_37_end_address_l,The ISC Region 37 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 37 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_37_end_address_h,The ISC Region 37 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 37 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_38_control,The ISC Region 38 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 38 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5CD0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_38_start_address_l,The ISC Region 38 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 38 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_38_start_address_h,The ISC Region 38 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 38 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_38_end_address_l,The ISC Region 38 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 38 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_38_end_address_h,The ISC Region 38 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 38 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_39_control,The ISC Region 39 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 39 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5CF0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_39_start_address_l,The ISC Region 39 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 39 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_39_start_address_h,The ISC Region 39 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 39 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_39_end_address_l,The ISC Region 39 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 39 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_39_end_address_h,The ISC Region 39 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 39 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_40_control,The ISC Region 40 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 40 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5D10++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_40_start_address_l,The ISC Region 40 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 40 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_40_start_address_h,The ISC Region 40 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 40 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_40_end_address_l,The ISC Region 40 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 40 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_40_end_address_h,The ISC Region 40 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 40 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_41_control,The ISC Region 41 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 41 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5D30++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_41_start_address_l,The ISC Region 41 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 41 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_41_start_address_h,The ISC Region 41 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 41 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_41_end_address_l,The ISC Region 41 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 41 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_41_end_address_h,The ISC Region 41 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 41 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_42_control,The ISC Region 42 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 42 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5D50++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_42_start_address_l,The ISC Region 42 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 42 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_42_start_address_h,The ISC Region 42 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 42 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_42_end_address_l,The ISC Region 42 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 42 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_42_end_address_h,The ISC Region 42 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 42 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_43_control,The ISC Region 43 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 43 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5D70++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_43_start_address_l,The ISC Region 43 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 43 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_43_start_address_h,The ISC Region 43 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 43 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_43_end_address_l,The ISC Region 43 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 43 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_43_end_address_h,The ISC Region 43 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 43 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_44_control,The ISC Region 44 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 44 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5D90++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_44_start_address_l,The ISC Region 44 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 44 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_44_start_address_h,The ISC Region 44 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 44 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_44_end_address_l,The ISC Region 44 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 44 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_44_end_address_h,The ISC Region 44 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 44 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_45_control,The ISC Region 45 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 45 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5DB0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_45_start_address_l,The ISC Region 45 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 45 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_45_start_address_h,The ISC Region 45 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 45 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_45_end_address_l,The ISC Region 45 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 45 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_45_end_address_h,The ISC Region 45 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 45 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_46_control,The ISC Region 46 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 46 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5DD0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_46_start_address_l,The ISC Region 46 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 46 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_46_start_address_h,The ISC Region 46 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 46 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_46_end_address_l,The ISC Region 46 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 46 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_46_end_address_h,The ISC Region 46 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 46 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_47_control,The ISC Region 47 Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 47 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x5DF0++0x13 line.long 0x0 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_47_start_address_l,The ISC Region 47 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 47 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_47_start_address_h,The ISC Region 47 Start Address High Register defines the start address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 47 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_47_end_address_l,The ISC Region 47 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 47 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_47_end_address_h,The ISC Region 47 End Address High Register defines the end address bits 47 to 32 for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 47 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync region 48 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." tree.end tree "CBASS_AC_NONSAFE0_QOS (CBASS_AC_NONSAFE0_QOS)" base ad:0x45DC0000 rgroup.long 0x100++0x7F line.long 0x0 "QOS_REGS_Idmpac_top_main_0_data_mst_map0,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x4 "QOS_REGS_Idmpac_top_main_0_data_mst_map1,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x8 "QOS_REGS_Idmpac_top_main_0_data_mst_map2,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x8 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xC "QOS_REGS_Idmpac_top_main_0_data_mst_map3,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0xC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x10 "QOS_REGS_Idmpac_top_main_0_data_mst_map4,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x10 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x10 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x14 "QOS_REGS_Idmpac_top_main_0_data_mst_map5,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x14 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x14 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x14 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x18 "QOS_REGS_Idmpac_top_main_0_data_mst_map6,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x18 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x18 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x18 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x1C "QOS_REGS_Idmpac_top_main_0_data_mst_map7,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x1C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x1C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x20 "QOS_REGS_Idmpac_top_main_0_data_mst_map8,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x20 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x20 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x20 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x24 "QOS_REGS_Idmpac_top_main_0_data_mst_map9,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x24 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x24 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x24 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x28 "QOS_REGS_Idmpac_top_main_0_data_mst_map10,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x28 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x28 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x28 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x2C "QOS_REGS_Idmpac_top_main_0_data_mst_map11,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x2C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x2C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x2C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x30 "QOS_REGS_Idmpac_top_main_0_data_mst_map12,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x30 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x30 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x30 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x34 "QOS_REGS_Idmpac_top_main_0_data_mst_map13,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x34 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x34 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x34 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x38 "QOS_REGS_Idmpac_top_main_0_data_mst_map14,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x38 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x38 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x38 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x3C "QOS_REGS_Idmpac_top_main_0_data_mst_map15,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x3C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x3C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x3C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x40 "QOS_REGS_Idmpac_top_main_0_data_mst_map16,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x40 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x40 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x40 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x44 "QOS_REGS_Idmpac_top_main_0_data_mst_map17,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x44 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x44 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x44 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x48 "QOS_REGS_Idmpac_top_main_0_data_mst_map18,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x48 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x48 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x48 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x4C "QOS_REGS_Idmpac_top_main_0_data_mst_map19,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x4C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x4C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x50 "QOS_REGS_Idmpac_top_main_0_data_mst_map20,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x50 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x50 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x50 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x54 "QOS_REGS_Idmpac_top_main_0_data_mst_map21,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x54 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x54 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x54 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x58 "QOS_REGS_Idmpac_top_main_0_data_mst_map22,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x58 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x58 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x58 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x5C "QOS_REGS_Idmpac_top_main_0_data_mst_map23,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x5C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x5C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x5C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x60 "QOS_REGS_Idmpac_top_main_0_data_mst_map24,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x60 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x60 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x60 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x64 "QOS_REGS_Idmpac_top_main_0_data_mst_map25,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x64 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x64 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x64 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x68 "QOS_REGS_Idmpac_top_main_0_data_mst_map26,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x68 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x68 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x68 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x6C "QOS_REGS_Idmpac_top_main_0_data_mst_map27,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x6C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x6C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x6C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x70 "QOS_REGS_Idmpac_top_main_0_data_mst_map28,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x70 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x70 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x70 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x74 "QOS_REGS_Idmpac_top_main_0_data_mst_map29,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x74 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x74 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x74 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x78 "QOS_REGS_Idmpac_top_main_0_data_mst_map30,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x78 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x78 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x78 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x7C "QOS_REGS_Idmpac_top_main_0_data_mst_map31,The Map Register defines the fields for the master Idmpac_top_main_0.data_mst per channel." bitfld.long 0x7C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x7C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x7C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." rgroup.long 0xC00++0x7 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async for group slv_linkgrp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async for group slv_linkgrp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0xD00++0x3 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_map0,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x1000++0x7 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async for group slv_linkgrp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async for group slv_linkgrp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x1100++0x3 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_map0,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x1500++0x7F line.long 0x0 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map0,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x4 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map1,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x8 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map2,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x8 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xC "QOS_REGS_Ivpac_top_main_0_data_mst_0_map3,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0xC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x10 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map4,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x10 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x10 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x14 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map5,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x14 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x14 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x14 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x18 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map6,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x18 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x18 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x18 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x1C "QOS_REGS_Ivpac_top_main_0_data_mst_0_map7,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x1C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x1C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x20 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map8,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x20 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x20 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x20 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x24 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map9,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x24 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x24 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x24 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x28 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map10,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x28 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x28 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x28 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x2C "QOS_REGS_Ivpac_top_main_0_data_mst_0_map11,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x2C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x2C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x2C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x30 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map12,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x30 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x30 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x30 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x34 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map13,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x34 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x34 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x34 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x38 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map14,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x38 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x38 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x38 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x3C "QOS_REGS_Ivpac_top_main_0_data_mst_0_map15,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x3C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x3C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x3C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x40 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map16,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x40 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x40 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x40 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x44 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map17,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x44 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x44 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x44 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x48 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map18,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x48 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x48 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x48 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x4C "QOS_REGS_Ivpac_top_main_0_data_mst_0_map19,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x4C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x4C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x50 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map20,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x50 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x50 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x50 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x54 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map21,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x54 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x54 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x54 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x58 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map22,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x58 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x58 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x58 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x5C "QOS_REGS_Ivpac_top_main_0_data_mst_0_map23,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x5C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x5C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x5C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x60 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map24,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x60 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x60 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x60 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x64 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map25,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x64 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x64 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x64 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x68 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map26,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x68 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x68 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x68 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x6C "QOS_REGS_Ivpac_top_main_0_data_mst_0_map27,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x6C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x6C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x6C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x70 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map28,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x70 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x70 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x70 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x74 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map29,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x74 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x74 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x74 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x78 "QOS_REGS_Ivpac_top_main_0_data_mst_0_map30,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x78 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x78 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x78 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x7C "QOS_REGS_Ivpac_top_main_0_data_mst_0_map31,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_0 per channel." bitfld.long 0x7C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x7C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x7C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." rgroup.long 0x1900++0xFF line.long 0x0 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map0,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x4 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map1,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x8 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map2,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x8 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xC "QOS_REGS_Ivpac_top_main_0_data_mst_1_map3,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x10 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map4,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x10 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x10 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x14 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map5,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x14 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x14 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x14 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x18 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map6,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x18 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x18 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x18 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x1C "QOS_REGS_Ivpac_top_main_0_data_mst_1_map7,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x1C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x1C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x20 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map8,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x20 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x20 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x20 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x24 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map9,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x24 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x24 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x24 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x28 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map10,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x28 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x28 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x28 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x2C "QOS_REGS_Ivpac_top_main_0_data_mst_1_map11,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x2C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x2C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x2C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x30 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map12,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x30 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x30 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x30 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x34 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map13,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x34 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x34 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x34 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x38 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map14,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x38 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x38 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x38 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x3C "QOS_REGS_Ivpac_top_main_0_data_mst_1_map15,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x3C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x3C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x3C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x40 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map16,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x40 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x40 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x40 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x44 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map17,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x44 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x44 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x44 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x48 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map18,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x48 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x48 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x48 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x4C "QOS_REGS_Ivpac_top_main_0_data_mst_1_map19,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x4C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x4C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x50 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map20,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x50 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x50 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x50 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x54 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map21,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x54 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x54 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x54 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x58 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map22,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x58 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x58 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x58 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x5C "QOS_REGS_Ivpac_top_main_0_data_mst_1_map23,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x5C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x5C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x5C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x60 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map24,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x60 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x60 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x60 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x64 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map25,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x64 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x64 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x64 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x68 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map26,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x68 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x68 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x68 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x6C "QOS_REGS_Ivpac_top_main_0_data_mst_1_map27,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x6C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x6C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x6C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x70 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map28,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x70 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x70 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x70 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x74 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map29,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x74 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x74 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x74 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x78 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map30,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x78 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x78 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x78 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x7C "QOS_REGS_Ivpac_top_main_0_data_mst_1_map31,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x7C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x7C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x7C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x80 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map32,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x80 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x80 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x80 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x84 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map33,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x84 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x84 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x84 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x88 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map34,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x88 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x88 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x88 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x8C "QOS_REGS_Ivpac_top_main_0_data_mst_1_map35,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x8C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x8C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x8C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x90 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map36,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x90 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x90 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x90 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x94 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map37,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x94 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x94 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x94 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x98 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map38,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x98 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x98 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x98 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x9C "QOS_REGS_Ivpac_top_main_0_data_mst_1_map39,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0x9C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x9C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x9C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xA0 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map40,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xA0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xA0 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xA0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xA4 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map41,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xA4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xA4 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xA4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xA8 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map42,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xA8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xA8 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xA8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xAC "QOS_REGS_Ivpac_top_main_0_data_mst_1_map43,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xAC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xAC 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xAC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xB0 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map44,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xB0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xB0 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xB0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xB4 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map45,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xB4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xB4 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xB4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xB8 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map46,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xB8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xB8 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xB8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xBC "QOS_REGS_Ivpac_top_main_0_data_mst_1_map47,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xBC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xBC 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xBC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xC0 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map48,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xC0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC0 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xC0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xC4 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map49,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xC4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC4 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xC4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xC8 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map50,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xC8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC8 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xC8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xCC "QOS_REGS_Ivpac_top_main_0_data_mst_1_map51,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xCC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xCC 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xCC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xD0 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map52,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xD0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xD0 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xD0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xD4 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map53,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xD4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xD4 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xD4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xD8 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map54,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xD8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xD8 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xD8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xDC "QOS_REGS_Ivpac_top_main_0_data_mst_1_map55,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xDC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xDC 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xDC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xE0 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map56,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xE0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xE0 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xE0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xE4 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map57,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xE4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xE4 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xE4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xE8 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map58,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xE8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xE8 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xE8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xEC "QOS_REGS_Ivpac_top_main_0_data_mst_1_map59,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xEC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xEC 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xEC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xF0 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map60,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xF0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xF0 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xF0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xF4 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map61,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xF4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xF4 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xF4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xF8 "QOS_REGS_Ivpac_top_main_0_data_mst_1_map62,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xF8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xF8 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xF8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xFC "QOS_REGS_Ivpac_top_main_0_data_mst_1_map63,The Map Register defines the fields for the master Ivpac_top_main_0.data_mst_1 per channel." bitfld.long 0xFC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xFC 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xFC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." rgroup.long 0x1C00++0x7 line.long 0x0 "QOS_REGS_Ivpac_top_main_0_ldc0_m_mst_slv_linkgrp_1_grp_map1,The Group Map Register defines the final orderid for the master Ivpac_top_main_0.ldc0_m_mst for group slv_linkgrp_1." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ivpac_top_main_0_ldc0_m_mst_slv_linkgrp_1_grp_map2,The Group Map Register defines the final orderid for the master Ivpac_top_main_0.ldc0_m_mst for group slv_linkgrp_1." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x1D00++0xB line.long 0x0 "QOS_REGS_Ivpac_top_main_0_ldc0_m_mst_map0,The Map Register defines the fields for the master Ivpac_top_main_0.ldc0_m_mst per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Ivpac_top_main_0_ldc0_m_mst_map1,The Map Register defines the fields for the master Ivpac_top_main_0.ldc0_m_mst per channel." bitfld.long 0x4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x8 "QOS_REGS_Ivpac_top_main_0_ldc0_m_mst_map2,The Map Register defines the fields for the master Ivpac_top_main_0.ldc0_m_mst per channel." bitfld.long 0x8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x2000++0x7 line.long 0x0 "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_slv_linkgrp_1_grp_map1,The Group Map Register defines the final orderid for the master Ik3_dss_main_0.dss_inst0_vbusm_dma for group slv_linkgrp_1." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_slv_linkgrp_1_grp_map2,The Group Map Register defines the final orderid for the master Ik3_dss_main_0.dss_inst0_vbusm_dma for group slv_linkgrp_1." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x2100++0x27 line.long 0x0 "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_map0,The Map Register defines the fields for the master Ik3_dss_main_0.dss_inst0_vbusm_dma per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_map1,The Map Register defines the fields for the master Ik3_dss_main_0.dss_inst0_vbusm_dma per channel." bitfld.long 0x4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x8 "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_map2,The Map Register defines the fields for the master Ik3_dss_main_0.dss_inst0_vbusm_dma per channel." bitfld.long 0x8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x8 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." newline hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_map3,The Map Register defines the fields for the master Ik3_dss_main_0.dss_inst0_vbusm_dma per channel." bitfld.long 0xC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." newline hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x10 "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_map4,The Map Register defines the fields for the master Ik3_dss_main_0.dss_inst0_vbusm_dma per channel." bitfld.long 0x10 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x10 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." newline hexmask.long.byte 0x10 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x10 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x14 "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_map5,The Map Register defines the fields for the master Ik3_dss_main_0.dss_inst0_vbusm_dma per channel." bitfld.long 0x14 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x14 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x14 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." newline hexmask.long.byte 0x14 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x14 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x18 "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_map6,The Map Register defines the fields for the master Ik3_dss_main_0.dss_inst0_vbusm_dma per channel." bitfld.long 0x18 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x18 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x18 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." newline hexmask.long.byte 0x18 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x18 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1C "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_map7,The Map Register defines the fields for the master Ik3_dss_main_0.dss_inst0_vbusm_dma per channel." bitfld.long 0x1C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x1C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." newline hexmask.long.byte 0x1C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x20 "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_map8,The Map Register defines the fields for the master Ik3_dss_main_0.dss_inst0_vbusm_dma per channel." bitfld.long 0x20 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x20 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x20 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." newline hexmask.long.byte 0x20 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x20 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x24 "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_dma_map9,The Map Register defines the fields for the master Ik3_dss_main_0.dss_inst0_vbusm_dma per channel." bitfld.long 0x24 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x24 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x24 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." newline hexmask.long.byte 0x24 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x24 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x2400++0x7 line.long 0x0 "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_slv_linkgrp_1_grp_map1,The Group Map Register defines the final orderid for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc for group slv_linkgrp_1." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_slv_linkgrp_1_grp_map2,The Group Map Register defines the final orderid for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc for group slv_linkgrp_1." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x2500++0x27 line.long 0x0 "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_map0,The Map Register defines the fields for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_map1,The Map Register defines the fields for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc per channel." bitfld.long 0x4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x8 "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_map2,The Map Register defines the fields for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc per channel." bitfld.long 0x8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x8 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." newline hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_map3,The Map Register defines the fields for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc per channel." bitfld.long 0xC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." newline hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x10 "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_map4,The Map Register defines the fields for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc per channel." bitfld.long 0x10 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x10 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." newline hexmask.long.byte 0x10 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x10 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x14 "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_map5,The Map Register defines the fields for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc per channel." bitfld.long 0x14 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x14 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x14 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." newline hexmask.long.byte 0x14 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x14 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x18 "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_map6,The Map Register defines the fields for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc per channel." bitfld.long 0x18 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x18 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x18 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." newline hexmask.long.byte 0x18 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x18 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1C "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_map7,The Map Register defines the fields for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc per channel." bitfld.long 0x1C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x1C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." newline hexmask.long.byte 0x1C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x20 "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_map8,The Map Register defines the fields for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc per channel." bitfld.long 0x20 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x20 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x20 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." newline hexmask.long.byte 0x20 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x20 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x24 "QOS_REGS_Ik3_dss_main_0_dss_inst0_vbusm_fbdc_map9,The Map Register defines the fields for the master Ik3_dss_main_0.dss_inst0_vbusm_fbdc per channel." bitfld.long 0x24 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x24 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x24 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." newline hexmask.long.byte 0x24 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x24 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x2800++0x7 line.long 0x0 "QOS_REGS_Ivpac_top_main_1_ldc0_m_mst_slv_linkgrp_1_grp_map1,The Group Map Register defines the final orderid for the master Ivpac_top_main_1.ldc0_m_mst for group slv_linkgrp_1." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ivpac_top_main_1_ldc0_m_mst_slv_linkgrp_1_grp_map2,The Group Map Register defines the final orderid for the master Ivpac_top_main_1.ldc0_m_mst for group slv_linkgrp_1." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x2900++0xB line.long 0x0 "QOS_REGS_Ivpac_top_main_1_ldc0_m_mst_map0,The Map Register defines the fields for the master Ivpac_top_main_1.ldc0_m_mst per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Ivpac_top_main_1_ldc0_m_mst_map1,The Map Register defines the fields for the master Ivpac_top_main_1.ldc0_m_mst per channel." bitfld.long 0x4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x8 "QOS_REGS_Ivpac_top_main_1_ldc0_m_mst_map2,The Map Register defines the fields for the master Ivpac_top_main_1.ldc0_m_mst per channel." bitfld.long 0x8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x2D00++0x7F line.long 0x0 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map0,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x4 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map1,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x8 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map2,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x8 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xC "QOS_REGS_Ivpac_top_main_1_data_mst_0_map3,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0xC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x10 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map4,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x10 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x10 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x14 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map5,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x14 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x14 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x14 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x18 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map6,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x18 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x18 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x18 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x1C "QOS_REGS_Ivpac_top_main_1_data_mst_0_map7,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x1C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x1C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x20 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map8,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x20 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x20 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x20 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x24 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map9,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x24 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x24 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x24 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x28 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map10,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x28 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x28 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x28 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x2C "QOS_REGS_Ivpac_top_main_1_data_mst_0_map11,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x2C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x2C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x2C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x30 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map12,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x30 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x30 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x30 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x34 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map13,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x34 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x34 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x34 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x38 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map14,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x38 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x38 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x38 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x3C "QOS_REGS_Ivpac_top_main_1_data_mst_0_map15,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x3C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x3C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x3C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x40 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map16,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x40 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x40 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x40 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x44 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map17,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x44 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x44 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x44 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x48 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map18,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x48 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x48 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x48 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x4C "QOS_REGS_Ivpac_top_main_1_data_mst_0_map19,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x4C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x4C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x50 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map20,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x50 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x50 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x50 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x54 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map21,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x54 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x54 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x54 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x58 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map22,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x58 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x58 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x58 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x5C "QOS_REGS_Ivpac_top_main_1_data_mst_0_map23,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x5C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x5C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x5C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x60 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map24,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x60 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x60 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x60 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x64 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map25,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x64 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x64 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x64 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x68 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map26,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x68 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x68 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x68 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x6C "QOS_REGS_Ivpac_top_main_1_data_mst_0_map27,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x6C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x6C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x6C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x70 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map28,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x70 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x70 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x70 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x74 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map29,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x74 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x74 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x74 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x78 "QOS_REGS_Ivpac_top_main_1_data_mst_0_map30,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x78 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x78 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x78 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x7C "QOS_REGS_Ivpac_top_main_1_data_mst_0_map31,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_0 per channel." bitfld.long 0x7C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x7C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x7C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." rgroup.long 0x3100++0xFF line.long 0x0 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map0,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x4 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map1,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x8 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map2,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x8 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xC "QOS_REGS_Ivpac_top_main_1_data_mst_1_map3,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x10 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map4,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x10 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x10 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x14 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map5,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x14 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x14 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x14 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x18 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map6,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x18 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x18 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x18 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x1C "QOS_REGS_Ivpac_top_main_1_data_mst_1_map7,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x1C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x1C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x20 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map8,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x20 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x20 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x20 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x24 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map9,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x24 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x24 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x24 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x28 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map10,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x28 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x28 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x28 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x2C "QOS_REGS_Ivpac_top_main_1_data_mst_1_map11,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x2C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x2C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x2C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x30 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map12,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x30 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x30 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x30 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x34 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map13,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x34 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x34 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x34 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x38 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map14,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x38 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x38 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x38 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x3C "QOS_REGS_Ivpac_top_main_1_data_mst_1_map15,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x3C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x3C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x3C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x40 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map16,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x40 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x40 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x40 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x44 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map17,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x44 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x44 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x44 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x48 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map18,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x48 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x48 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x48 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x4C "QOS_REGS_Ivpac_top_main_1_data_mst_1_map19,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x4C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x4C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x50 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map20,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x50 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x50 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x50 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x54 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map21,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x54 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x54 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x54 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x58 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map22,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x58 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x58 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x58 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x5C "QOS_REGS_Ivpac_top_main_1_data_mst_1_map23,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x5C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x5C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x5C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x60 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map24,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x60 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x60 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x60 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x64 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map25,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x64 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x64 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x64 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x68 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map26,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x68 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x68 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x68 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x6C "QOS_REGS_Ivpac_top_main_1_data_mst_1_map27,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x6C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x6C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x6C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x70 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map28,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x70 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x70 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x70 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x74 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map29,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x74 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x74 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x74 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x78 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map30,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x78 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x78 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x78 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x7C "QOS_REGS_Ivpac_top_main_1_data_mst_1_map31,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x7C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x7C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x7C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x80 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map32,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x80 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x80 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x80 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x84 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map33,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x84 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x84 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x84 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x88 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map34,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x88 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x88 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x88 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x8C "QOS_REGS_Ivpac_top_main_1_data_mst_1_map35,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x8C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x8C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x8C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x90 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map36,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x90 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x90 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x90 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x94 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map37,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x94 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x94 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x94 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x98 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map38,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x98 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x98 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x98 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0x9C "QOS_REGS_Ivpac_top_main_1_data_mst_1_map39,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0x9C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x9C 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x9C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xA0 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map40,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xA0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xA0 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xA0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xA4 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map41,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xA4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xA4 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xA4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xA8 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map42,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xA8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xA8 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xA8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xAC "QOS_REGS_Ivpac_top_main_1_data_mst_1_map43,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xAC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xAC 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xAC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xB0 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map44,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xB0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xB0 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xB0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xB4 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map45,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xB4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xB4 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xB4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xB8 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map46,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xB8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xB8 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xB8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xBC "QOS_REGS_Ivpac_top_main_1_data_mst_1_map47,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xBC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xBC 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xBC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xC0 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map48,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xC0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC0 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xC0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xC4 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map49,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xC4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC4 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xC4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xC8 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map50,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xC8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC8 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xC8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xCC "QOS_REGS_Ivpac_top_main_1_data_mst_1_map51,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xCC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xCC 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xCC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xD0 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map52,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xD0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xD0 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xD0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xD4 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map53,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xD4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xD4 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xD4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xD8 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map54,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xD8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xD8 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xD8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xDC "QOS_REGS_Ivpac_top_main_1_data_mst_1_map55,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xDC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xDC 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xDC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xE0 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map56,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xE0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xE0 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xE0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xE4 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map57,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xE4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xE4 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xE4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xE8 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map58,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xE8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xE8 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xE8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xEC "QOS_REGS_Ivpac_top_main_1_data_mst_1_map59,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xEC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xEC 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xEC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xF0 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map60,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xF0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xF0 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xF0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xF4 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map61,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xF4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xF4 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xF4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xF8 "QOS_REGS_Ivpac_top_main_1_data_mst_1_map62,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xF8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xF8 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xF8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." line.long 0xFC "QOS_REGS_Ivpac_top_main_1_data_mst_1_map63,The Map Register defines the fields for the master Ivpac_top_main_1.data_mst_1 per channel." bitfld.long 0xFC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xFC 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0xFC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." rgroup.long 0x3400++0x7 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async for group slv_linkgrp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async for group slv_linkgrp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x3500++0x13 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_map0,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_map1,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async per channel." bitfld.long 0x4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x8 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_map2,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async per channel." bitfld.long 0x8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_map3,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async per channel." bitfld.long 0xC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x10 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_map4,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async per channel." bitfld.long 0x10 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x10 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x10 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x10 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x10 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x3800++0x7 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async for group slv_linkgrp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async for group slv_linkgrp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x3900++0x13 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_map0,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_map1,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async per channel." bitfld.long 0x4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x8 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_map2,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async per channel." bitfld.long 0x8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_map3,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async per channel." bitfld.long 0xC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x10 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_map4,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async per channel." bitfld.long 0x10 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x10 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x10 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x10 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x10 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x3C00++0x7 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async for group slv_linkgrp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async for group slv_linkgrp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x3D00++0x3 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_r_async_map0,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_r_async per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x4000++0x7 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async for group slv_linkgrp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async for group slv_linkgrp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x4100++0x3 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_1_sec_m_vbusm_w_async_map0,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_1.sec_m_vbusm_w_async per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x4400++0x7 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async for group slv_linkgrp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async for group slv_linkgrp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x4500++0x13 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_map0,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_map1,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async per channel." bitfld.long 0x4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x8 "QOS_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_map2,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async per channel." bitfld.long 0x8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC "QOS_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_map3,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async per channel." bitfld.long 0xC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x10 "QOS_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_r_async_map4,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_r_async per channel." bitfld.long 0x10 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x10 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x10 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x10 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x10 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x4800++0x7 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async for group slv_linkgrp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async for group slv_linkgrp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x4900++0x13 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_map0,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_map1,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async per channel." bitfld.long 0x4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x8 "QOS_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_map2,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async per channel." bitfld.long 0x8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC "QOS_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_map3,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async per channel." bitfld.long 0xC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x10 "QOS_REGS_Ik3_vpu_wave521cl_main_1_pri_m_vbusm_w_async_map4,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_1.pri_m_vbusm_w_async per channel." bitfld.long 0x10 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x10 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x10 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x10 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x10 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x5000++0x7 line.long 0x0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync for group slv_linkgrp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync for group slv_linkgrp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x5100++0x27F line.long 0x0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map0,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map1,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map2,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map3,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x10 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map4,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x10 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x10 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x10 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x10 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x10 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x14 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map5,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x14 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x14 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x14 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x14 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x14 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x18 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map6,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x18 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x18 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x18 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x18 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x18 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map7,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x20 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map8,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x20 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x20 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x20 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x20 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x20 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x20 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x24 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map9,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x24 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x24 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x24 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x24 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x24 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x28 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map10,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x28 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x28 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x28 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x28 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x28 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x28 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x2C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map11,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x2C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x2C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x2C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x2C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x2C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x2C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x30 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map12,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x30 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x30 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x30 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x30 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x30 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x30 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x34 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map13,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x34 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x34 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x34 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x34 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x34 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x34 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x38 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map14,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x38 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x38 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x38 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x38 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x38 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x38 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x3C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map15,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x3C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x3C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x3C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x3C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x3C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x3C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x40 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map16,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x40 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x40 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x40 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x40 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x40 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x40 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x44 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map17,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x44 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x44 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x44 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x44 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x44 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x44 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x48 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map18,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x48 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x48 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x48 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x48 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x48 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x48 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map19,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x4C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x4C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x4C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x4C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x50 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map20,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x50 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x50 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x50 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x50 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x50 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x50 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x54 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map21,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x54 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x54 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x54 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x54 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x54 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x54 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x58 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map22,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x58 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x58 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x58 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x58 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x58 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x58 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x5C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map23,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x5C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x5C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x5C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x5C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x5C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x5C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x60 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map24,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x60 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x60 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x60 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x60 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x60 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x60 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x64 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map25,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x64 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x64 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x64 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x64 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x64 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x64 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x68 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map26,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x68 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x68 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x68 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x68 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x68 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x68 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x6C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map27,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x6C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x6C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x6C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x6C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x6C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x6C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x70 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map28,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x70 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x70 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x70 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x70 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x70 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x70 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x74 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map29,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x74 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x74 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x74 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x74 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x74 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x74 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x78 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map30,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x78 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x78 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x78 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x78 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x78 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x78 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x7C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map31,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x7C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x7C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x7C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x7C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x7C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x7C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x80 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map32,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x80 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x80 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x80 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x80 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x80 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x80 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x84 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map33,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x84 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x84 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x84 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x84 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x84 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x84 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x88 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map34,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x88 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x88 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x88 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x88 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x88 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x88 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x8C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map35,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x8C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x8C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x8C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x8C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x8C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x90 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map36,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x90 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x90 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x90 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x90 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x90 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x90 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x94 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map37,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x94 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x94 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x94 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x94 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x94 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x94 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x98 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map38,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x98 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x98 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x98 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x98 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x98 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x98 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x9C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map39,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x9C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x9C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x9C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x9C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x9C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x9C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xA0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map40,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xA0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xA0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xA0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xA0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xA0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xA0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xA4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map41,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xA4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xA4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xA4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xA4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xA4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xA4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xA8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map42,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xA8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xA8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xA8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xA8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xA8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xA8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xAC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map43,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xAC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xAC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xAC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xAC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xAC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xAC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xB0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map44,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xB0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xB0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xB0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xB0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xB0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xB0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xB4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map45,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xB4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xB4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xB4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xB4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xB4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xB4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xB8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map46,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xB8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xB8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xB8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xB8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xB8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xB8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xBC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map47,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xBC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xBC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xBC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xBC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xBC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xBC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map48,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xC0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xC0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xC0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xC0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map49,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xC4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xC4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xC4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xC4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map50,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xC8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xC8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xC8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xC8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xCC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map51,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xCC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xCC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xCC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xCC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xCC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xCC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xD0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map52,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xD0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xD0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xD0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xD0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xD0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xD0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xD4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map53,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xD4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xD4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xD4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xD4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xD4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xD4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xD8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map54,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xD8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xD8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xD8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xD8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xD8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xD8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xDC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map55,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xDC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xDC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xDC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xDC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xDC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xDC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xE0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map56,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xE0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xE0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xE0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xE0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xE0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xE0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xE4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map57,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xE4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xE4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xE4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xE4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xE4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xE4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xE8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map58,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xE8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xE8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xE8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xE8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xE8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xE8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xEC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map59,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xEC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xEC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xEC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xEC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xEC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xEC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xF0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map60,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xF0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xF0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xF0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xF0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xF0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xF0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xF4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map61,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xF4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xF4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xF4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xF4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xF4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xF4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xF8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map62,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xF8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xF8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xF8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xF8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xF8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xF8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xFC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map63,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0xFC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xFC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xFC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xFC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xFC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xFC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x100 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map64,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x100 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x100 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x100 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x100 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x100 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x100 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x104 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map65,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x104 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x104 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x104 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x104 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x104 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x104 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x108 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map66,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x108 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x108 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x108 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x108 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x108 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x108 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x10C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map67,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x10C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x10C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x10C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x10C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x10C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x110 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map68,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x110 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x110 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x110 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x110 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x110 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x110 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x114 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map69,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x114 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x114 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x114 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x114 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x114 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x114 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x118 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map70,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x118 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x118 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x118 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x118 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x118 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x118 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x11C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map71,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x11C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x11C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x11C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x11C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x11C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x11C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x120 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map72,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x120 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x120 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x120 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x120 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x120 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x120 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x124 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map73,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x124 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x124 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x124 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x124 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x124 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x124 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x128 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map74,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x128 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x128 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x128 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x128 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x128 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x128 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x12C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map75,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x12C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x12C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x12C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x12C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x12C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x12C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x130 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map76,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x130 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x130 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x130 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x130 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x130 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x130 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x134 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map77,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x134 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x134 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x134 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x134 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x134 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x134 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x138 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map78,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x138 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x138 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x138 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x138 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x138 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x138 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x13C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map79,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x13C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x13C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x13C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x13C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x13C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x13C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x140 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map80,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x140 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x140 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x140 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x140 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x140 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x140 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x144 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map81,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x144 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x144 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x144 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x144 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x144 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x144 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x148 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map82,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x148 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x148 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x148 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x148 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x148 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x148 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x14C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map83,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x14C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x14C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x14C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x14C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x14C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x150 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map84,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x150 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x150 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x150 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x150 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x150 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x150 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x154 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map85,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x154 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x154 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x154 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x154 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x154 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x154 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x158 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map86,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x158 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x158 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x158 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x158 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x158 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x158 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x15C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map87,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x15C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x15C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x15C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x15C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x15C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x15C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x160 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map88,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x160 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x160 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x160 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x160 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x160 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x160 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x164 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map89,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x164 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x164 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x164 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x164 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x164 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x164 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x168 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map90,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x168 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x168 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x168 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x168 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x168 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x168 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x16C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map91,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x16C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x16C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x16C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x16C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x16C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x16C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x170 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map92,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x170 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x170 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x170 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x170 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x170 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x170 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x174 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map93,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x174 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x174 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x174 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x174 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x174 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x174 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x178 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map94,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x178 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x178 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x178 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x178 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x178 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x178 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x17C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map95,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x17C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x17C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x17C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x17C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x17C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x17C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x180 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map96,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x180 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x180 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x180 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x180 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x180 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x180 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x184 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map97,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x184 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x184 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x184 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x184 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x184 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x184 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x188 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map98,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x188 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x188 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x188 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x188 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x188 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x188 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x18C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map99,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x18C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x18C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x18C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x18C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x18C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x190 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map100,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x190 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x190 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x190 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x190 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x190 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x190 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x194 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map101,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x194 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x194 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x194 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x194 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x194 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x194 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x198 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map102,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x198 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x198 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x198 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x198 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x198 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x198 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x19C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map103,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x19C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x19C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x19C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x19C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x19C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x19C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1A0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map104,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1A0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1A0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1A0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1A0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1A0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1A0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1A4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map105,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1A4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1A4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1A4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1A4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1A4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1A4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1A8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map106,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1A8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1A8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1A8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1A8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1A8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1A8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1AC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map107,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1AC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1AC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1AC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1AC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1AC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1AC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1B0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map108,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1B0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1B0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1B0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1B0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1B0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1B0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1B4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map109,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1B4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1B4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1B4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1B4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1B4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1B4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1B8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map110,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1B8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1B8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1B8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1B8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1B8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1B8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1BC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map111,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1BC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1BC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1BC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1BC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1BC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1BC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1C0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map112,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1C0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1C0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1C0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1C0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1C0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1C4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map113,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1C4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1C4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1C4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1C4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1C4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1C8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map114,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1C8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1C8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1C8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1C8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1C8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1CC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map115,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1CC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1CC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1CC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1CC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1CC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1CC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1D0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map116,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1D0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1D0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1D0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1D0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1D0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1D0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1D4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map117,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1D4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1D4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1D4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1D4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1D4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1D4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1D8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map118,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1D8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1D8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1D8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1D8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1D8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1D8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1DC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map119,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1DC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1DC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1DC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1DC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1DC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1DC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1E0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map120,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1E0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1E0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1E0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1E0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1E0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1E0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1E4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map121,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1E4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1E4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1E4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1E4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1E4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1E4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1E8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map122,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1E8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1E8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1E8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1E8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1E8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1E8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1EC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map123,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1EC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1EC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1EC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1EC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1EC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1EC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1F0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map124,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1F0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1F0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1F0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1F0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1F0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1F0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1F4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map125,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1F4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1F4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1F4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1F4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1F4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1F4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1F8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map126,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1F8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1F8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1F8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1F8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1F8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1F8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1FC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map127,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x1FC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1FC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1FC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1FC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1FC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1FC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x200 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map128,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x200 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x200 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x200 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x200 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x200 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x200 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x204 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map129,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x204 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x204 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x204 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x204 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x204 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x204 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x208 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map130,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x208 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x208 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x208 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x208 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x208 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x208 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x20C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map131,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x20C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x20C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x20C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x20C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x20C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x20C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x210 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map132,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x210 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x210 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x210 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x210 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x210 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x210 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x214 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map133,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x214 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x214 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x214 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x214 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x214 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x214 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x218 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map134,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x218 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x218 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x218 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x218 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x218 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x218 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x21C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map135,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x21C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x21C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x21C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x21C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x21C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x21C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x220 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map136,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x220 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x220 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x220 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x220 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x220 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x220 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x224 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map137,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x224 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x224 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x224 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x224 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x224 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x224 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x228 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map138,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x228 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x228 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x228 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x228 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x228 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x228 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x22C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map139,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x22C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x22C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x22C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x22C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x22C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x22C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x230 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map140,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x230 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x230 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x230 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x230 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x230 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x230 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x234 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map141,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x234 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x234 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x234 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x234 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x234 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x234 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x238 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map142,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x238 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x238 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x238 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x238 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x238 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x238 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x23C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map143,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x23C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x23C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x23C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x23C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x23C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x23C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x240 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map144,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x240 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x240 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x240 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x240 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x240 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x240 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x244 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map145,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x244 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x244 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x244 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x244 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x244 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x244 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x248 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map146,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x248 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x248 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x248 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x248 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x248 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x248 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x24C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map147,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x24C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x24C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x24C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x24C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x24C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x250 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map148,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x250 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x250 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x250 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x250 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x250 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x250 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x254 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map149,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x254 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x254 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x254 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x254 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x254 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x254 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x258 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map150,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x258 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x258 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x258 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x258 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x258 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x258 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x25C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map151,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x25C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x25C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x25C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x25C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x25C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x25C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x260 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map152,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x260 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x260 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x260 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x260 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x260 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x260 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x264 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map153,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x264 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x264 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x264 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x264 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x264 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x264 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x268 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map154,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x268 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x268 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x268 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x268 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x268 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x268 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x26C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map155,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x26C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x26C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x26C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x26C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x26C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x26C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x270 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map156,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x270 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x270 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x270 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x270 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x270 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x270 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x274 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map157,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x274 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x274 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x274 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x274 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x274 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x274 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x278 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map158,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x278 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x278 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x278 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x278 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x278 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x278 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x27C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_r_sync_map159,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_r_sync per channel." bitfld.long 0x27C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x27C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x27C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x27C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x27C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x27C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x5800++0x7 line.long 0x0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync for group slv_linkgrp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync for group slv_linkgrp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x5900++0x27F line.long 0x0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map0,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map1,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map2,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map3,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x10 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map4,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x10 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x10 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x10 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x10 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x10 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x14 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map5,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x14 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x14 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x14 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x14 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x14 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x18 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map6,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x18 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x18 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x18 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x18 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x18 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map7,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x20 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map8,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x20 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x20 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x20 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x20 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x20 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x20 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x24 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map9,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x24 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x24 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x24 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x24 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x24 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x28 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map10,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x28 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x28 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x28 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x28 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x28 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x28 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x2C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map11,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x2C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x2C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x2C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x2C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x2C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x2C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x30 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map12,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x30 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x30 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x30 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x30 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x30 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x30 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x34 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map13,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x34 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x34 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x34 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x34 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x34 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x34 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x38 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map14,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x38 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x38 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x38 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x38 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x38 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x38 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x3C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map15,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x3C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x3C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x3C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x3C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x3C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x3C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x40 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map16,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x40 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x40 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x40 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x40 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x40 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x40 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x44 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map17,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x44 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x44 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x44 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x44 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x44 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x44 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x48 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map18,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x48 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x48 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x48 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x48 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x48 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x48 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map19,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x4C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x4C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x4C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x4C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x50 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map20,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x50 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x50 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x50 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x50 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x50 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x50 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x54 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map21,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x54 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x54 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x54 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x54 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x54 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x54 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x58 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map22,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x58 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x58 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x58 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x58 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x58 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x58 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x5C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map23,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x5C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x5C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x5C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x5C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x5C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x5C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x60 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map24,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x60 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x60 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x60 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x60 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x60 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x60 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x64 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map25,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x64 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x64 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x64 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x64 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x64 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x64 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x68 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map26,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x68 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x68 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x68 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x68 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x68 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x68 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x6C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map27,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x6C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x6C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x6C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x6C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x6C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x6C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x70 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map28,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x70 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x70 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x70 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x70 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x70 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x70 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x74 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map29,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x74 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x74 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x74 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x74 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x74 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x74 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x78 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map30,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x78 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x78 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x78 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x78 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x78 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x78 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x7C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map31,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x7C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x7C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x7C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x7C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x7C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x7C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x80 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map32,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x80 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x80 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x80 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x80 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x80 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x80 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x84 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map33,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x84 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x84 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x84 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x84 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x84 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x84 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x88 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map34,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x88 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x88 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x88 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x88 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x88 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x88 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x8C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map35,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x8C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x8C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x8C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x8C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x8C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x90 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map36,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x90 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x90 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x90 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x90 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x90 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x90 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x94 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map37,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x94 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x94 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x94 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x94 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x94 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x94 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x98 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map38,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x98 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x98 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x98 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x98 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x98 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x98 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x9C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map39,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x9C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x9C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x9C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x9C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x9C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x9C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xA0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map40,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xA0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xA0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xA0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xA0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xA0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xA0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xA4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map41,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xA4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xA4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xA4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xA4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xA4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xA4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xA8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map42,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xA8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xA8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xA8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xA8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xA8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xA8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xAC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map43,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xAC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xAC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xAC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xAC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xAC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xAC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xB0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map44,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xB0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xB0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xB0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xB0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xB0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xB0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xB4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map45,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xB4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xB4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xB4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xB4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xB4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xB4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xB8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map46,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xB8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xB8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xB8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xB8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xB8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xB8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xBC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map47,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xBC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xBC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xBC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xBC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xBC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xBC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map48,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xC0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xC0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xC0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xC0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map49,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xC4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xC4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xC4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xC4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map50,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xC8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xC8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xC8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xC8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xCC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map51,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xCC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xCC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xCC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xCC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xCC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xCC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xD0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map52,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xD0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xD0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xD0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xD0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xD0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xD0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xD4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map53,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xD4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xD4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xD4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xD4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xD4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xD4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xD8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map54,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xD8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xD8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xD8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xD8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xD8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xD8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xDC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map55,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xDC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xDC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xDC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xDC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xDC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xDC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xE0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map56,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xE0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xE0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xE0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xE0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xE0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xE0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xE4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map57,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xE4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xE4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xE4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xE4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xE4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xE4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xE8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map58,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xE8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xE8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xE8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xE8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xE8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xE8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xEC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map59,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xEC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xEC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xEC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xEC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xEC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xEC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xF0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map60,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xF0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xF0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xF0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xF0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xF0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xF0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xF4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map61,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xF4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xF4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xF4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xF4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xF4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xF4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xF8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map62,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xF8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xF8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xF8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xF8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xF8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xF8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xFC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map63,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0xFC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xFC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xFC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xFC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xFC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xFC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x100 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map64,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x100 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x100 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x100 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x100 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x100 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x100 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x104 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map65,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x104 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x104 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x104 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x104 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x104 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x104 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x108 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map66,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x108 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x108 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x108 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x108 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x108 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x108 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x10C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map67,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x10C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x10C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x10C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x10C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x10C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x110 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map68,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x110 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x110 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x110 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x110 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x110 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x110 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x114 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map69,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x114 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x114 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x114 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x114 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x114 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x114 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x118 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map70,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x118 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x118 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x118 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x118 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x118 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x118 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x11C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map71,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x11C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x11C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x11C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x11C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x11C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x11C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x120 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map72,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x120 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x120 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x120 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x120 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x120 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x120 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x124 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map73,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x124 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x124 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x124 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x124 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x124 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x124 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x128 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map74,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x128 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x128 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x128 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x128 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x128 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x128 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x12C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map75,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x12C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x12C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x12C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x12C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x12C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x12C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x130 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map76,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x130 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x130 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x130 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x130 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x130 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x130 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x134 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map77,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x134 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x134 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x134 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x134 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x134 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x134 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x138 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map78,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x138 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x138 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x138 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x138 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x138 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x138 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x13C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map79,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x13C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x13C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x13C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x13C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x13C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x13C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x140 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map80,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x140 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x140 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x140 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x140 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x140 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x140 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x144 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map81,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x144 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x144 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x144 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x144 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x144 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x144 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x148 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map82,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x148 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x148 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x148 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x148 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x148 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x148 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x14C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map83,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x14C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x14C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x14C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x14C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x14C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x150 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map84,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x150 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x150 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x150 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x150 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x150 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x150 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x154 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map85,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x154 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x154 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x154 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x154 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x154 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x154 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x158 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map86,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x158 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x158 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x158 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x158 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x158 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x158 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x15C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map87,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x15C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x15C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x15C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x15C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x15C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x15C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x160 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map88,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x160 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x160 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x160 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x160 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x160 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x160 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x164 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map89,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x164 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x164 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x164 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x164 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x164 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x164 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x168 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map90,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x168 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x168 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x168 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x168 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x168 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x168 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x16C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map91,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x16C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x16C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x16C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x16C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x16C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x16C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x170 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map92,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x170 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x170 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x170 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x170 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x170 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x170 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x174 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map93,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x174 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x174 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x174 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x174 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x174 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x174 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x178 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map94,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x178 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x178 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x178 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x178 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x178 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x178 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x17C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map95,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x17C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x17C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x17C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x17C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x17C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x17C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x180 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map96,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x180 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x180 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x180 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x180 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x180 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x180 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x184 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map97,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x184 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x184 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x184 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x184 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x184 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x184 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x188 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map98,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x188 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x188 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x188 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x188 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x188 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x188 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x18C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map99,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x18C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x18C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x18C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x18C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x18C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x190 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map100,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x190 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x190 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x190 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x190 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x190 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x190 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x194 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map101,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x194 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x194 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x194 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x194 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x194 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x194 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x198 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map102,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x198 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x198 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x198 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x198 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x198 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x198 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x19C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map103,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x19C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x19C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x19C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x19C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x19C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x19C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1A0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map104,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1A0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1A0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1A0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1A0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1A0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1A0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1A4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map105,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1A4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1A4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1A4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1A4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1A4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1A4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1A8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map106,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1A8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1A8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1A8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1A8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1A8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1A8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1AC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map107,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1AC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1AC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1AC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1AC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1AC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1AC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1B0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map108,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1B0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1B0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1B0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1B0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1B0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1B0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1B4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map109,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1B4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1B4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1B4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1B4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1B4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1B4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1B8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map110,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1B8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1B8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1B8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1B8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1B8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1B8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1BC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map111,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1BC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1BC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1BC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1BC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1BC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1BC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1C0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map112,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1C0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1C0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1C0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1C0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1C0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1C4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map113,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1C4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1C4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1C4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1C4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1C4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1C8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map114,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1C8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1C8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1C8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1C8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1C8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1CC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map115,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1CC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1CC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1CC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1CC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1CC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1CC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1D0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map116,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1D0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1D0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1D0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1D0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1D0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1D0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1D4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map117,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1D4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1D4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1D4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1D4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1D4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1D4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1D8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map118,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1D8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1D8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1D8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1D8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1D8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1D8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1DC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map119,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1DC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1DC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1DC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1DC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1DC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1DC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1E0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map120,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1E0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1E0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1E0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1E0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1E0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1E0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1E4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map121,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1E4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1E4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1E4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1E4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1E4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1E4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1E8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map122,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1E8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1E8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1E8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1E8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1E8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1E8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1EC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map123,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1EC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1EC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1EC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1EC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1EC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1EC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1F0 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map124,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1F0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1F0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1F0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1F0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1F0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1F0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1F4 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map125,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1F4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1F4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1F4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1F4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1F4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1F4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1F8 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map126,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1F8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1F8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1F8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1F8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1F8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1F8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1FC "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map127,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x1FC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1FC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1FC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1FC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1FC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1FC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x200 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map128,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x200 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x200 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x200 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x200 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x200 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x200 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x204 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map129,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x204 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x204 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x204 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x204 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x204 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x204 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x208 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map130,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x208 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x208 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x208 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x208 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x208 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x208 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x20C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map131,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x20C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x20C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x20C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x20C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x20C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x20C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x210 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map132,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x210 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x210 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x210 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x210 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x210 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x210 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x214 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map133,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x214 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x214 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x214 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x214 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x214 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x214 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x218 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map134,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x218 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x218 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x218 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x218 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x218 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x218 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x21C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map135,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x21C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x21C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x21C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x21C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x21C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x21C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x220 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map136,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x220 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x220 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x220 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x220 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x220 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x220 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x224 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map137,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x224 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x224 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x224 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x224 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x224 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x224 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x228 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map138,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x228 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x228 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x228 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x228 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x228 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x228 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x22C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map139,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x22C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x22C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x22C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x22C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x22C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x22C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x230 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map140,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x230 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x230 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x230 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x230 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x230 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x230 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x234 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map141,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x234 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x234 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x234 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x234 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x234 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x234 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x238 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map142,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x238 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x238 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x238 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x238 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x238 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x238 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x23C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map143,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x23C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x23C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x23C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x23C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x23C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x23C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x240 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map144,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x240 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x240 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x240 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x240 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x240 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x240 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x244 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map145,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x244 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x244 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x244 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x244 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x244 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x244 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x248 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map146,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x248 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x248 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x248 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x248 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x248 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x248 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x24C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map147,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x24C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x24C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x24C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x24C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x24C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x250 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map148,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x250 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x250 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x250 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x250 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x250 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x250 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x254 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map149,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x254 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x254 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x254 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x254 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x254 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x254 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x258 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map150,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x258 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x258 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x258 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x258 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x258 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x258 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x25C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map151,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x25C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x25C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x25C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x25C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x25C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x25C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x260 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map152,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x260 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x260 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x260 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x260 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x260 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x260 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x264 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map153,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x264 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x264 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x264 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x264 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x264 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x264 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x268 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map154,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x268 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x268 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x268 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x268 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x268 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x268 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x26C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map155,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x26C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x26C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x26C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x26C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x26C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x26C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x270 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map156,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x270 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x270 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x270 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x270 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x270 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x270 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x274 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map157,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x274 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x274 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x274 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x274 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x274 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x274 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x278 "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map158,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x278 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x278 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x278 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x278 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x278 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x278 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x27C "QOS_REGS_Ij7aep_gpu_bxs464_wrap_main_0_m_vbusm_w_sync_map159,The Map Register defines the fields for the master Ij7aep_gpu_bxs464_wrap_main_0.m_vbusm_w_sync per channel." bitfld.long 0x27C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x27C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x27C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x27C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x27C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x27C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" tree.end tree.end tree.end tree "CBASS_CSI0" tree "CBASS_CSI0_ERR (CBASS_CSI0_ERR)" base ad:0x2A88000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end tree "CBASS_CSI0_GLB (CBASS_CSI0_GLB)" base ad:0x45B20400 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x20++0x3 line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x40++0x7 line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree.end tree "CBASS_INFRA_NON_SAFE0" tree "CBASS_INFRA_NON_SAFE0_ERR (CBASS_INFRA_NON_SAFE0_ERR)" base ad:0xB04000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end tree "CBASS_INFRA_NON_SAFE0_GLB (CBASS_INFRA_NON_SAFE0_GLB)" base ad:0x45B24000 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x20++0x3 line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x40++0x7 line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree.end tree "CBASS_IPPHY0" tree "CBASS_IPPHY0_ERR (CBASS_IPPHY0_ERR)" base ad:0x2A8F000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end tree "CBASS_IPPHY0_GLB (CBASS_IPPHY0_GLB)" base ad:0x45B21400 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x20++0x3 line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x40++0x7 line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree.end tree "CBASS_IPPHY_SAFE0" tree "CBASS_IPPHY_SAFE0_ERR (CBASS_IPPHY_SAFE0_ERR)" base ad:0x2A94000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end tree "CBASS_IPPHY_SAFE0_GLB (CBASS_IPPHY_SAFE0_GLB)" base ad:0x45B24400 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x20++0x3 line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x40++0x7 line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree "CBASS_IPPHY_SAFE0_ISC (CBASS_IPPHY_SAFE0_ISC)" base ad:0x45878000 rgroup.long 0x0++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst0_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_0.pbdg_rmst0 region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x10++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst0_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_rmst0 region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst0_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_rmst0 region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst0_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_rmst0 region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst0_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_rmst0 region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst0_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_0.pbdg_rmst0 region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x30++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst0_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_rmst0 region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst0_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_rmst0 region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst0_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_rmst0 region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst0_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_rmst0 region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst0_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_0.pbdg_rmst0 region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x50++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst0_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_rmst0 region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst0_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_rmst0 region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst0_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_rmst0 region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst0_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_rmst0 region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst0_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_0.pbdg_rmst0 region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x70++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst0_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_rmst0 region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst0_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_rmst0 region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst0_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_rmst0 region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst0_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_rmst0 region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst0_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_0.pbdg_rmst0 region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x400++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst0_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_0.pbdg_wmst0 region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x410++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst0_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_wmst0 region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst0_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_wmst0 region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst0_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_wmst0 region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst0_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_wmst0 region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst0_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_0.pbdg_wmst0 region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x430++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst0_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_wmst0 region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst0_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_wmst0 region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst0_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_wmst0 region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst0_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_wmst0 region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst0_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_0.pbdg_wmst0 region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x450++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst0_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_wmst0 region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst0_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_wmst0 region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst0_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_wmst0 region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst0_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_wmst0 region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst0_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_0.pbdg_wmst0 region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x470++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst0_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_wmst0 region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst0_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_wmst0 region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst0_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_wmst0 region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst0_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_wmst0 region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst0_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_0.pbdg_wmst0 region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x800++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst1_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_0.pbdg_rmst1 region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x810++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst1_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_rmst1 region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst1_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_rmst1 region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst1_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_rmst1 region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst1_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_rmst1 region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst1_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_0.pbdg_rmst1 region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x830++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst1_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_rmst1 region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst1_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_rmst1 region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst1_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_rmst1 region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst1_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_rmst1 region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst1_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_0.pbdg_rmst1 region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x850++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst1_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_rmst1 region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst1_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_rmst1 region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst1_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_rmst1 region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst1_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_rmst1 region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst1_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_0.pbdg_rmst1 region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x870++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst1_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_rmst1 region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst1_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_rmst1 region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst1_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_rmst1 region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst1_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_rmst1 region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_pbdg_rmst1_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_0.pbdg_rmst1 region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC00++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst1_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_0.pbdg_wmst1 region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC10++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst1_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_wmst1 region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst1_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_wmst1 region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst1_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_wmst1 region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst1_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_wmst1 region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst1_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_0.pbdg_wmst1 region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC30++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst1_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_wmst1 region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst1_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_wmst1 region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst1_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_wmst1 region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst1_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_wmst1 region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst1_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_0.pbdg_wmst1 region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC50++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst1_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_wmst1 region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst1_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_wmst1 region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst1_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_wmst1 region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst1_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_wmst1 region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst1_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_0.pbdg_wmst1 region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC70++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst1_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_wmst1 region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst1_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_wmst1 region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst1_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.pbdg_wmst1 region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst1_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.pbdg_wmst1 region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_pbdg_wmst1_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_0.pbdg_wmst1 region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." tree.end tree "CBASS_IPPHY_SAFE0_QOS (CBASS_IPPHY_SAFE0_QOS)" base ad:0x45D78000 rgroup.long 0x100++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_0_pbdg_rmst0_map0,The Map Register defines the fields for the master Ipulsar_sl_main_0.pbdg_rmst0 per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x500++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_0_pbdg_wmst0_map0,The Map Register defines the fields for the master Ipulsar_sl_main_0.pbdg_wmst0 per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x900++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_0_pbdg_rmst1_map0,The Map Register defines the fields for the master Ipulsar_sl_main_0.pbdg_rmst1 per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0xD00++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_0_pbdg_wmst1_map0,The Map Register defines the fields for the master Ipulsar_sl_main_0.pbdg_wmst1 per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" tree.end tree.end tree "CBASS_RC0" tree "CBASS_RC0_ERR (CBASS_RC0_ERR)" base ad:0x2A8C000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end tree "CBASS_RC0_GLB (CBASS_RC0_GLB)" base ad:0x45B22000 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x20++0x3 line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x40++0x7 line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree "CBASS_RC0_ISC (CBASS_RC0_ISC)" base ad:0x45880000 rgroup.long 0x2800++0x3 line.long 0x0 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iemmcsd4ss_main_0.emmcsdss_rd region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2810++0x13 line.long 0x0 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iemmcsd4ss_main_0.emmcsdss_rd region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iemmcsd4ss_main_0.emmcsdss_rd region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iemmcsd4ss_main_0.emmcsdss_rd region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iemmcsd4ss_main_0.emmcsdss_rd region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iemmcsd4ss_main_0.emmcsdss_rd region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2C00++0x3 line.long 0x0 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iemmcsd4ss_main_0.emmcsdss_wr region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2C10++0x13 line.long 0x0 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iemmcsd4ss_main_0.emmcsdss_wr region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iemmcsd4ss_main_0.emmcsdss_wr region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iemmcsd4ss_main_0.emmcsdss_wr region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iemmcsd4ss_main_0.emmcsdss_wr region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iemmcsd4ss_main_0.emmcsdss_wr region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x6000++0x3 line.long 0x0 "ISC_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_rd_vbusm_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Icompute_cluster_j7ahp_main_0.gic_mem_rd_vbusm region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x6010++0x13 line.long 0x0 "ISC_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_rd_vbusm_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Icompute_cluster_j7ahp_main_0.gic_mem_rd_vbusm region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_rd_vbusm_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Icompute_cluster_j7ahp_main_0.gic_mem_rd_vbusm region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_rd_vbusm_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Icompute_cluster_j7ahp_main_0.gic_mem_rd_vbusm region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_rd_vbusm_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Icompute_cluster_j7ahp_main_0.gic_mem_rd_vbusm region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_rd_vbusm_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Icompute_cluster_j7ahp_main_0.gic_mem_rd_vbusm region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x6400++0x3 line.long 0x0 "ISC_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_wr_vbusm_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Icompute_cluster_j7ahp_main_0.gic_mem_wr_vbusm region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x6410++0x13 line.long 0x0 "ISC_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_wr_vbusm_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Icompute_cluster_j7ahp_main_0.gic_mem_wr_vbusm region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_wr_vbusm_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Icompute_cluster_j7ahp_main_0.gic_mem_wr_vbusm region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_wr_vbusm_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Icompute_cluster_j7ahp_main_0.gic_mem_wr_vbusm region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_wr_vbusm_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Icompute_cluster_j7ahp_main_0.gic_mem_wr_vbusm region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_wr_vbusm_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Icompute_cluster_j7ahp_main_0.gic_mem_wr_vbusm region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x8000++0x3 line.long 0x0 "ISC_REGS_Ij7_led_main_0_vbusp_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ij7_led_main_0.vbusp region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x8010++0x13 line.long 0x0 "ISC_REGS_Ij7_led_main_0_vbusp_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7_led_main_0.vbusp region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ij7_led_main_0_vbusp_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ij7_led_main_0.vbusp region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ij7_led_main_0_vbusp_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7_led_main_0.vbusp region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ij7_led_main_0_vbusp_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ij7_led_main_0.vbusp region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ij7_led_main_0_vbusp_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ij7_led_main_0.vbusp region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." tree.end tree "CBASS_RC0_QOS (CBASS_RC0_QOS)" base ad:0x45D80000 rgroup.long 0x2800++0x17 line.long 0x0 "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Iemmcsd4ss_main_0.emmcsdss_rd for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Iemmcsd4ss_main_0.emmcsdss_rd for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." line.long 0x8 "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Iemmcsd4ss_main_0.emmcsdss_rd for group slv_linkgrp_0." hexmask.long.byte 0x8 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x8 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x8 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x8 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x8 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x8 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x8 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x8 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0xC "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Iemmcsd4ss_main_0.emmcsdss_rd for group slv_linkgrp_0." hexmask.long.byte 0xC 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0xC 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0xC 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0xC 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0xC 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0xC 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0xC 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0xC 0.--3. 1. "ORDERID8,orderid signal for 0." line.long 0x10 "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_slv_grp_1_grp_map1,The Group Map Register defines the final orderid for the master Iemmcsd4ss_main_0.emmcsdss_rd for group slv_grp_1." hexmask.long.byte 0x10 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x10 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x10 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x10 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x10 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x10 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x10 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x10 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x14 "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_slv_grp_1_grp_map2,The Group Map Register defines the final orderid for the master Iemmcsd4ss_main_0.emmcsdss_rd for group slv_grp_1." hexmask.long.byte 0x14 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x14 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x14 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x14 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x14 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x14 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x14 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x14 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x2900++0x3 line.long 0x0 "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_map0,The Map Register defines the fields for the master Iemmcsd4ss_main_0.emmcsdss_rd per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x2C00++0x17 line.long 0x0 "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Iemmcsd4ss_main_0.emmcsdss_wr for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Iemmcsd4ss_main_0.emmcsdss_wr for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." line.long 0x8 "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Iemmcsd4ss_main_0.emmcsdss_wr for group slv_linkgrp_0." hexmask.long.byte 0x8 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x8 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x8 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x8 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x8 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x8 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x8 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x8 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0xC "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Iemmcsd4ss_main_0.emmcsdss_wr for group slv_linkgrp_0." hexmask.long.byte 0xC 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0xC 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0xC 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0xC 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0xC 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0xC 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0xC 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0xC 0.--3. 1. "ORDERID8,orderid signal for 0." line.long 0x10 "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_slv_grp_1_grp_map1,The Group Map Register defines the final orderid for the master Iemmcsd4ss_main_0.emmcsdss_wr for group slv_grp_1." hexmask.long.byte 0x10 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x10 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x10 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x10 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x10 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x10 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x10 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x10 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x14 "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_slv_grp_1_grp_map2,The Group Map Register defines the final orderid for the master Iemmcsd4ss_main_0.emmcsdss_wr for group slv_grp_1." hexmask.long.byte 0x14 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x14 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x14 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x14 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x14 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x14 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x14 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x14 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x2D00++0x3 line.long 0x0 "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_map0,The Map Register defines the fields for the master Iemmcsd4ss_main_0.emmcsdss_wr per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x6000++0x17 line.long 0x0 "QOS_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_rd_vbusm_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Icompute_cluster_j7ahp_main_0.gic_mem_rd_vbusm for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_rd_vbusm_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Icompute_cluster_j7ahp_main_0.gic_mem_rd_vbusm for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." line.long 0x8 "QOS_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_rd_vbusm_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Icompute_cluster_j7ahp_main_0.gic_mem_rd_vbusm for group slv_linkgrp_0." hexmask.long.byte 0x8 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x8 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x8 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x8 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x8 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x8 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x8 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x8 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0xC "QOS_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_rd_vbusm_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Icompute_cluster_j7ahp_main_0.gic_mem_rd_vbusm for group slv_linkgrp_0." hexmask.long.byte 0xC 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0xC 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0xC 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0xC 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0xC 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0xC 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0xC 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0xC 0.--3. 1. "ORDERID8,orderid signal for 0." line.long 0x10 "QOS_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_rd_vbusm_slv_grp_1_grp_map1,The Group Map Register defines the final orderid for the master Icompute_cluster_j7ahp_main_0.gic_mem_rd_vbusm for group slv_grp_1." hexmask.long.byte 0x10 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x10 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x10 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x10 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x10 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x10 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x10 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x10 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x14 "QOS_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_rd_vbusm_slv_grp_1_grp_map2,The Group Map Register defines the final orderid for the master Icompute_cluster_j7ahp_main_0.gic_mem_rd_vbusm for group slv_grp_1." hexmask.long.byte 0x14 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x14 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x14 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x14 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x14 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x14 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x14 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x14 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x6100++0x3 line.long 0x0 "QOS_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_rd_vbusm_map0,The Map Register defines the fields for the master Icompute_cluster_j7ahp_main_0.gic_mem_rd_vbusm per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x6400++0x17 line.long 0x0 "QOS_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_wr_vbusm_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Icompute_cluster_j7ahp_main_0.gic_mem_wr_vbusm for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_wr_vbusm_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Icompute_cluster_j7ahp_main_0.gic_mem_wr_vbusm for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." line.long 0x8 "QOS_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_wr_vbusm_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Icompute_cluster_j7ahp_main_0.gic_mem_wr_vbusm for group slv_linkgrp_0." hexmask.long.byte 0x8 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x8 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x8 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x8 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x8 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x8 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x8 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x8 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0xC "QOS_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_wr_vbusm_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Icompute_cluster_j7ahp_main_0.gic_mem_wr_vbusm for group slv_linkgrp_0." hexmask.long.byte 0xC 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0xC 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0xC 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0xC 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0xC 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0xC 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0xC 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0xC 0.--3. 1. "ORDERID8,orderid signal for 0." line.long 0x10 "QOS_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_wr_vbusm_slv_grp_1_grp_map1,The Group Map Register defines the final orderid for the master Icompute_cluster_j7ahp_main_0.gic_mem_wr_vbusm for group slv_grp_1." hexmask.long.byte 0x10 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x10 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x10 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x10 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x10 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x10 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x10 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x10 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x14 "QOS_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_wr_vbusm_slv_grp_1_grp_map2,The Group Map Register defines the final orderid for the master Icompute_cluster_j7ahp_main_0.gic_mem_wr_vbusm for group slv_grp_1." hexmask.long.byte 0x14 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x14 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x14 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x14 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x14 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x14 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x14 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x14 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x6500++0x3 line.long 0x0 "QOS_REGS_Icompute_cluster_j7ahp_main_0_gic_mem_wr_vbusm_map0,The Map Register defines the fields for the master Icompute_cluster_j7ahp_main_0.gic_mem_wr_vbusm per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" tree.end tree.end tree "CBASS_RC_CFG0" tree "CBASS_RC_CFG0_ERR (CBASS_RC_CFG0_ERR)" base ad:0x2A8D000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end tree "CBASS_RC_CFG0_GLB (CBASS_RC_CFG0_GLB)" base ad:0x45B22400 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x20++0x3 line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x40++0x7 line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree.end tree.end tree "CMPEVENT_INTRTR0_CFG (CMPEVENT_INTRTR0_CFG)" base ad:0xA30000 rgroup.long 0x0++0x3 line.long 0x0 "INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" rgroup.long 0x4++0x3 line.long 0x0 "INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.byte 0x0 0.--3. 1. "MUX_CNTL,Mux control for interrupt N" tree.end tree "CODEC0_VPU (CODEC0_VPU)" base ad:0x4210000 wgroup.long 0x0++0x3 line.long 0x0 "VPU_REGS_VPU_PO_CONF,Power On Configuration" bitfld.long 0x0 3. "USE_PO_CONF,Host processor should set 0 when initialization" "0,1" bitfld.long 0x0 0. "DEBUGMODE,Power on Debug Mode" "0,1" rgroup.long 0x4++0x7 line.long 0x0 "VPU_REGS_VCPU_CUR_PC,Current PC" hexmask.long 0x0 0.--31. 1. "CUR_PC,PC value represents the address of instruction which is executed in V-CPU" line.long 0x4 "VPU_REGS_VCPU_CUR_LR,Current LR" hexmask.long 0x4 0.--31. 1. "CUR_LR,Current LR (Link Register) to find out caller address" rgroup.long 0xC++0x3 line.long 0x0 "VPU_REGS_VPU_PDBG_STEP_MASK,V-CPU Debugger Step Mask" bitfld.long 0x0 0. "STEP_MASK_ENABLE,Interrupt Disable at step for debugger" "0,1" rgroup.long 0x10++0xF line.long 0x0 "VPU_REGS_VPU_PDBG_CTRL,V-CPU Debugger Control" bitfld.long 0x0 3. "IMMBRK,Immediate break" "0,1" bitfld.long 0x0 2. "STABLEBRK,Stable break" "0,1" bitfld.long 0x0 1. "RESUME,Resume" "0,1" newline bitfld.long 0x0 0. "STEP,Step" "0,1" line.long 0x4 "VPU_REGS_VPU_PDBG_IDX_REG,V-CPU Debugger Index" bitfld.long 0x4 9. "RDDBG,Read Operation Request" "0,1" bitfld.long 0x4 8. "WRDBG,Write Operation Request" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DBGIDX,Debug Index" line.long 0x8 "VPU_REGS_VPU_PDBG_WDATA_REG,V-CPU Debugger Write Data" hexmask.long 0x8 0.--31. 1. "VPU_PDBG_WDATA_REG,Write data to the debugger" line.long 0xC "VPU_REGS_VPU_PDBG_RDATA_REG,V-CPU Debugger Read Data" hexmask.long 0xC 0.--31. 1. "VPU_PDBG_RDATA_REG,Read data to the debugger" rgroup.long 0x20++0x7 line.long 0x0 "VPU_REGS_VPU_FIO_CTRL_ADDR,FastIO Control/Address" rbitfld.long 0x0 31. "READY,Ready for the transaction" "0,1" bitfld.long 0x0 16. "RW_FLAG,Read/Write transaction control" "0,1" hexmask.long.word 0x0 0.--15. 1. "FIO_ADDR,FIO Address" line.long 0x4 "VPU_REGS_VPU_FIO_DATA,FastIO Data" hexmask.long 0x4 0.--31. 1. "FIO_DATA,FIO DATA" rgroup.long 0x30++0x3 line.long 0x0 "VPU_REGS_VPU_VINT_REASON_USR,Interrupt Reason User" bitfld.long 0x0 15. "BSEMPTY_INTR_USER,Bitstream empty feeding request interrupt" "0,1" bitfld.long 0x0 14. "CMDE_INTR_USER,QUERY command done interrupt" "0,1" bitfld.long 0x0 13. "CMDD_INTR_USER,Low latency interrupt. Valid if low latency feature is enabled." "0,1" newline bitfld.long 0x0 10. "REL_SRC_INTR_USER,Release source buffer interrupt. Valid only if feature of release src buf is enabled" "0,1" bitfld.long 0x0 9. "CMD9_INTR_USER,ENC_SET_PARAM command done interrupt" "0,1" bitfld.long 0x0 8. "CMD8_INTR_USER,DEC_PIC/ENC_PIC command done interrupt" "0,1" newline bitfld.long 0x0 7. "CMD7_INTR_USER,SET_FRAMEBUFFER command done interrupt" "0,1" bitfld.long 0x0 6. "CMD6_INTR_USER,INIT_SEQ command done interrupt" "0,1" bitfld.long 0x0 5. "CMD5_INTR_USER,DESTROY_INSTANCE command done interrupt" "0,1" newline bitfld.long 0x0 4. "CMD4_INTR_USER,FLUSH_INSTANCE command done interrupt" "0,1" bitfld.long 0x0 3. "CMD3_INTR_USER,CREATE_INSTANCE command done interrupt" "0,1" bitfld.long 0x0 2. "CMD2_INTR_USER,SLEEP_VPU command done interrupt" "0,1" newline bitfld.long 0x0 1. "CMD1_INTR_USER,WAKE_VPU command done interrupt" "0,1" bitfld.long 0x0 0. "CMD0_INTR_USER,INIT_VPU command done interrupt" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "VPU_REGS_VPU_VINT_REASON_CLR,Interrupt Reason Clear" bitfld.long 0x0 15. "BSEMPTY_CLR,Bitstream empty bitstream feeding request interrupt clear" "0,1" bitfld.long 0x0 14. "CMDE_CLR,QUERY command done interrupt clear" "0,1" bitfld.long 0x0 13. "CMDD_CLR,Low Latency interrupt clear. Valid only if low latency feature is enabled" "0,1" newline bitfld.long 0x0 11. "INSUFFICIENT_VLC_BUFFER,VLC buffer realloc request interrupt enable. Valid only if VLC BUFFER CUSTOMIZATION features in VPU" "0,1" bitfld.long 0x0 10. "REL_SRC_CLR,Release source buffer interrupt. Valid only if the feature of release src buf is enabled" "0,1" bitfld.long 0x0 9. "CMD9_CLR,ENC_SET_PARAM command done interrupt clear" "0,1" newline bitfld.long 0x0 8. "CMD8_CLR,DEC_PIC/ENC_PIC command done interrupt clear" "0,1" bitfld.long 0x0 7. "CMD7_CLR,SET_FRAMEBUFFER command done interrupt clear" "0,1" bitfld.long 0x0 6. "CMD6_CLR,INIT_SEQ command done interrupt clear" "0,1" newline bitfld.long 0x0 5. "CMD5_CLR,DESTROY_INSTANCE command done interrupt clear" "0,1" bitfld.long 0x0 4. "CMD4_CLR,FLSUH_INSTANCE command done interrupt clear" "0,1" bitfld.long 0x0 3. "CMD3_CLR,CREATE_INSTANCE command done interrupt clear" "0,1" newline bitfld.long 0x0 2. "CMD2_CLR,SLEEP_VPU command done interrupt clear" "0,1" bitfld.long 0x0 1. "CMD1_CLR,WAKE_VPU command done interrupt clear" "0,1" bitfld.long 0x0 0. "CMD0_CLR,INIT_VPU command done interrupt clear" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "VPU_REGS_VPU_HOST_INT_REQ,Host Interrupt Request" bitfld.long 0x0 0. "HINTREQ,If this is set to 1 an interrupt named HOST interrupt is sent to VPU." "0,1" rgroup.long 0x3C++0x3 line.long 0x0 "VPU_REGS_VPU_VINT_CLEAR,VPU Interrupt Clear" bitfld.long 0x0 0. "VINTREQ,Clear VPU interrupt." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VPU_REGS_VPU_HINT_CLEAR,Host Interrupt Clear" bitfld.long 0x0 0. "HINTCLR,Check Host Command Interrupt is cleared." "0,1" rgroup.long 0x44++0x3 line.long 0x0 "VPU_REGS_VPU_VPU_INT_STS,VPU Interrupt Status" bitfld.long 0x0 0. "VPU_VPU_INT_STS,Interrupt Status" "0,1" rgroup.long 0x48++0xB line.long 0x0 "VPU_REGS_VPU_VINT_ENABLE,VPU Interrupt Enable" bitfld.long 0x0 15. "CMDF_EN,UPDATE_BS command done interrupt enable" "0,1" bitfld.long 0x0 14. "CMDE_EN,QUERY command done interrupt enable" "0,1" bitfld.long 0x0 13. "CMDD_EN,Low latency interrupt enable" "0,1" newline bitfld.long 0x0 11. "INSUFFICIENT_VLC_BUFFER,VLC Buffer Realloc request interrupt enable. Valid only if VLC BUFFER CUSTOMIZATION feature in VPU" "0,1" bitfld.long 0x0 10. "REL_SRC_EN,Release Source buffer interrupt enable. Valid only if feature of release src buf is enabled." "0,1" bitfld.long 0x0 9. "CMD9_EN,ENC_SET_PARAM command done interrupt enable" "0,1" newline bitfld.long 0x0 8. "CMD8_EN,DEC_PIC/ENC_PIC command done interrupt enable" "0,1" bitfld.long 0x0 7. "CMD7_EN,SET_FRAMEBUFFER command done interrupt enable" "0,1" bitfld.long 0x0 6. "CMD6_EN,SET_FRAMEBUFFER command done interrupt enable" "0,1" newline bitfld.long 0x0 5. "CMD5_EN,DESTROY_INSTANCE command done interrupt enable" "0,1" bitfld.long 0x0 4. "CMD4_EN,FLUSH INSTANCE command done interrupt enable" "0,1" bitfld.long 0x0 3. "CMD3_EN,CREATE INSTANCE command done interrupt enable" "0,1" newline bitfld.long 0x0 2. "CMD2_EN,SLEEP_VPU command done interrupt enable" "0,1" bitfld.long 0x0 1. "CMD1_EN,WAKE_VPU command done interrupt enable" "0,1" bitfld.long 0x0 0. "CMD0_EN,INIT_VPU command done interrupt enable" "0,1" line.long 0x4 "VPU_REGS_VPU_VINT_REASON,VPU Interrupt Reason" bitfld.long 0x4 15. "BSEMPTY_INTR,Bitstream empty bitstream feeding request." "0,1" bitfld.long 0x4 14. "CMDE_INTR,QUERY command done interrupt" "0,1" bitfld.long 0x4 13. "CMDD_INTR,Low latency interrupt" "0,1" newline bitfld.long 0x4 11. "INSUFFICIENT_VLC_BUFFER,VLC Buffer realloc request interrupt. Valid only if VLC BUFFER CUSTOMIZATION feature in VPU" "0,1" bitfld.long 0x4 10. "REL_SRC_INTR,Release source buffer Interrupt. Valid only if the feature of release src buf is enabled" "0,1" bitfld.long 0x4 9. "CMD9_INTR,ENC_SET_PARAM command done interrupt" "0,1" newline bitfld.long 0x4 8. "CMD8_INTR,DEC_PIC/ENC_PIC command done interrupt" "0,1" bitfld.long 0x4 7. "CMD7_INTR,SET_FRAMEBUFFER command done interrupt" "0,1" bitfld.long 0x4 6. "CMD6_INTR,INIT_SEQ command done interrupt" "0,1" newline bitfld.long 0x4 5. "CMD5_INTR,DESTROY_INSTANCE command done interrupt" "0,1" bitfld.long 0x4 4. "CMD4_INTR,FLUSH_INSTANCE command done interrupt" "0,1" bitfld.long 0x4 3. "CMD3_INTR,CREATE_INSTANCE command done interrupt" "0,1" newline bitfld.long 0x4 2. "CMD2_INTR,SLEEP_VPU command done interrupt" "0,1" bitfld.long 0x4 1. "CMD1_INTR,WAKE_VPU command done interrupt" "0,1" bitfld.long 0x4 0. "CMD0_INTR,INIT_VPU command done interrupt" "0,1" line.long 0x8 "VPU_REGS_VPU_RESET_REQ,VPU Reset Request" bitfld.long 0x8 26. "VCRST_REQ,CCLK domain for V-CPU Reset request" "0,1" bitfld.long 0x8 25. "VBRST_REQ,BCLK domain for V-CPU Reset request" "0,1" bitfld.long 0x8 24. "VARST_REQ,ACLK domain for V-CPU Reset request" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "ARST_REQ,ACLK domain reset request for each vCORE" hexmask.long.byte 0x8 8.--11. 1. "BRST_REQ,BCLK domain reset request for each vCORE" hexmask.long.byte 0x8 0.--3. 1. "CRST_REQ,CCLK domain reset request for each vCORE" rgroup.long 0x54++0x3 line.long 0x0 "VPU_REGS_VPU_RESET_STATUS,VPU Reset Status" bitfld.long 0x0 26. "VCRST_STS,CCLK domain for V-CPU reset status" "0,1" bitfld.long 0x0 25. "VBRST_STS,BCLK domain for V-CPU reset status" "0,1" bitfld.long 0x0 24. "VARST_STS,ACLK domain for V-CPU reset status" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "ARST_STS,ACLK domain for each V-Core reset status" hexmask.long.byte 0x0 8.--15. 1. "BRST_STS,BCLK domain for each V-Core reset status" hexmask.long.byte 0x0 0.--7. 1. "CRST_STS,CCLK domain for each V-Core reset status" rgroup.long 0x58++0x3 line.long 0x0 "VPU_REGS_VCPU_RESTART,V-CPU Restart Request" bitfld.long 0x0 0. "VCPU_RESTART_FIELD,This register restarts V-CPU from the reset vector without clearing H/W logic" "0,1" rgroup.long 0x5C++0x17 line.long 0x0 "VPU_REGS_VPU_CLK_MASK,VPU Clock Control" bitfld.long 0x0 26. "CCLK_CPU_EN,CCLK domain for V-CPU Gating" "0,1" bitfld.long 0x0 25. "BCLK_CPU_EN,BCLK domain for V-CPU Gating" "0,1" bitfld.long 0x0 24. "ACLK_CPU_EN,ACLK domain for V-CPU Gating" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "ACLK_EN,ACLK domain for V-Core Gating" hexmask.long.byte 0x0 8.--15. 1. "BCLK_EN,BCLK domain for V-Core Gating" hexmask.long.byte 0x0 0.--7. 1. "CCLK_EN,CCLK domain for V-Core Gating" line.long 0x4 "VPU_REGS_VPU_REMAP_CTRL,Remap Control" rbitfld.long 0x4 31. "REMAP_GLOBEN,Set 1 if you want to change the [30:12] part of this register" "0,1" hexmask.long.byte 0x4 20.--23. 1. "AXIID_PROC,Upper AXI-ID for processor bus to distinguish guest OS" hexmask.long.byte 0x4 16.--19. 1. "ENDIAN,Endianness for memory access" newline hexmask.long.byte 0x4 12.--15. 1. "REMAP_IDX,Remap index" bitfld.long 0x4 11. "REMAP_PAGE_SIZE_EN,Set 1 if you want to change the REMAP_PSIZE field" "0,1" hexmask.long.word 0x4 0.--8. 1. "REMAP_PSIZE,Remap Page Size" line.long 0x8 "VPU_REGS_VPU_REMAP_VADDR,Remap Virutal Address" hexmask.long.tbyte 0x8 12.--31. 1. "VPU_REMAP_VADDR,Remap region base address in virtual address space." line.long 0xC "VPU_REGS_VPU_REMAP_PADDR,Remap Physical Address" hexmask.long.tbyte 0xC 12.--31. 1. "VPU_REMAP_PADDR,Real address (physical address) as a pair of virtual address." line.long 0x10 "VPU_REGS_VPU_REMAP_CORE_START,VPU Start Request" bitfld.long 0x10 0. "VPU_REMAP_CORE_START,It starts VPU after initial setting has been done." "0,1" line.long 0x14 "VPU_REGS_VPU_BUSY_STATUS,VPU Busy Status" bitfld.long 0x14 0. "VPU_BUSY_STATUS,Command Reentrance Check [0]" "0,1" rgroup.long 0x74++0x7 line.long 0x0 "VPU_REGS_VPU_HALT_STATUS,VPU Halt Status" bitfld.long 0x0 4. "VPU_HALT_STATUS,V-CPU is on the HALT Status" "0,1" hexmask.long.byte 0x0 0.--3. 1. "VPU_HALT_STATUS_DEBUG,For debugging" line.long 0x4 "VPU_REGS_VPU_VCPU_STATUS,VCPU STATUS" hexmask.long.word 0x4 0.--14. 1. "VPU_VCPU_STATUS,If [15:0] is 0x0040 V-CPU is on the halt status.Thus the value returns 0x40 power for VPU can be turnned-off" rgroup.long 0x7C++0x3 line.long 0x0 "VPU_REGS_RSVD,RSVD" rgroup.long 0x80++0x3 line.long 0x0 "VPU_REGS_RET_FIO_STATUS,RETURN FIO STATUS" hexmask.long 0x0 0.--31. 1. "RESERVED,RET FIO STATUS" rgroup.long 0x90++0xB line.long 0x0 "VPU_REGS_RET_PRODUCT_NAME,HW product name" bitfld.long 0x0 0.--2. "HW_NAME,VPU hardware product name" "0,1,2,3,4,5,6,7" line.long 0x4 "VPU_REGS_RET_PRODUCT_VERSION,HW product version" bitfld.long 0x4 0.--2. "HW_VERSION,VPU hardware product version" "0,1,2,3,4,5,6,7" line.long 0x8 "VPU_REGS_RET_VCPU_CONFIG0,Configuration Information 0" hexmask.long 0x8 0.--31. 1. "RESERVED,Configuration Information 0" rgroup.long 0x98++0x3 line.long 0x0 "VPU_REGS_RET_VCPU_CONFIG1,Configuration Information 0" hexmask.long 0x0 4.--31. 1. "RESERVED,Configuration Information 0" bitfld.long 0x0 3. "AVC_DEC_EN,AVC decoder Enable" "0,1" bitfld.long 0x0 2. "HEVC_DEC_EN,HEVC decoder Enable" "0,1" newline bitfld.long 0x0 1. "AVC_ENC_EN,AVC encoder Enable" "0,1" bitfld.long 0x0 0. "HEVC_ENC_EN,HEVC encoder Enable" "0,1" rgroup.long 0xA0++0x23 line.long 0x0 "VPU_REGS_RET_CODEC_STD,Standard Definition" hexmask.long 0x0 0.--31. 1. "CODEC_STD,General Configuration Information - Internal Use only" line.long 0x4 "VPU_REGS_RET_CONF_DATE,Configuration Date" hexmask.long 0x4 0.--31. 1. "HW_DATE,The date that the hardware has been configured in YYYYMMDD. Internal Use only." line.long 0x8 "VPU_REGS_RET_CONF_REVISION,The revision of H/W configuration" hexmask.long 0x8 0.--31. 1. "HW_VERSION,Revision Number when the hardware has been configured. Internal Use only" line.long 0xC "VPU_REGS_RET_CONF_TYPE,The define value of H/W configuration" hexmask.long 0xC 0.--31. 1. "HW_TYPE,The define value used in hardware configuration. Internal Use only." line.long 0x10 "VPU_REGS_RET_VCORE0_CFG,Configuration Information of VCORE0" hexmask.long 0x10 0.--31. 1. "CONFIG_VCORE0,The VCORE0 configuration information. Internal Use only" line.long 0x14 "VPU_REGS_RET_VCORE1_CFG,Configuration Information of VCORE1" hexmask.long 0x14 0.--31. 1. "CONFIG_VCORE1,The VCORE1 configuration information. Internal Use only" line.long 0x18 "VPU_REGS_RET_VCORE2_CFG,Configuration Information of VCORE2" hexmask.long 0x18 0.--31. 1. "CONFIG_VCORE2,The VCORE2 configuration information. Internal Use only" line.long 0x1C "VPU_REGS_RET_VCORE3_CFG,Configuration Information of VCORE3" hexmask.long 0x1C 0.--31. 1. "CONFIG_VCORE3,The VCORE3 configuration information. Internal Use only" line.long 0x20 "VPU_REGS_VPU_RET_VCORE_PRESET,Number of VCOREs present" hexmask.long.byte 0x20 0.--3. 1. "VCORE_PRESENT,Each bit represent turn-on VCORE" tree.end sif (cpuis("AM68Ax")||cpuis("TDA4AL88")||cpuis("TDA4VE88")) tree "COMPUTE_CLUSTER0" base ad:0x0 sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_0_DSP0_ECC_AGGR (COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_0_DSP0_ECC_AGGR)" base ad:0x4D20050000 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 18. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x4 17. "PMC_BUSECC_PEND,Interrupt Pending Status for pmc_busecc_pend" "0,1" newline bitfld.long 0x4 16. "SE_1_BUSECC_PEND,Interrupt Pending Status for se_1_busecc_pend" "0,1" newline bitfld.long 0x4 15. "SE_0_BUSECC_PEND,Interrupt Pending Status for se_0_busecc_pend" "0,1" newline bitfld.long 0x4 14. "BUSECC_TAGRAM_DMC_PEND,Interrupt Pending Status for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x4 13. "BUSECC_DMC_PEND,Interrupt Pending Status for busecc_dmc_pend" "0,1" newline bitfld.long 0x4 12. "BUSECC_PIPE3_P2_PEND,Interrupt Pending Status for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x4 11. "BUSECC_PIPE3_DP_PEND,Interrupt Pending Status for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x4 10. "BUSECC_PIPE2_P2_PEND,Interrupt Pending Status for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x4 9. "BUSECC_PIPE2_DP_PEND,Interrupt Pending Status for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x4 8. "BUSECC_PIPE1_P2_PEND,Interrupt Pending Status for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x4 7. "BUSECC_PIPE1_DP_PEND,Interrupt Pending Status for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x4 6. "BUSECC_PIPE0_P2_PEND,Interrupt Pending Status for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x4 5. "BUSECC_PIPE0_DP_PEND,Interrupt Pending Status for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x4 4. "UMC_FW_MDMA_BUSECC_PEND,Interrupt Pending Status for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x4 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x3 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 18. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x0 17. "PMC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for pmc_busecc_pend" "0,1" newline bitfld.long 0x0 16. "SE_1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for se_1_busecc_pend" "0,1" newline bitfld.long 0x0 15. "SE_0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for se_0_busecc_pend" "0,1" newline bitfld.long 0x0 14. "BUSECC_TAGRAM_DMC_ENABLE_SET,Interrupt Enable Set Register for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x0 13. "BUSECC_DMC_ENABLE_SET,Interrupt Enable Set Register for busecc_dmc_pend" "0,1" newline bitfld.long 0x0 12. "BUSECC_PIPE3_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x0 11. "BUSECC_PIPE3_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x0 10. "BUSECC_PIPE2_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x0 9. "BUSECC_PIPE2_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x0 8. "BUSECC_PIPE1_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x0 7. "BUSECC_PIPE1_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x0 6. "BUSECC_PIPE0_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x0 5. "BUSECC_PIPE0_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x0 4. "UMC_FW_MDMA_BUSECC_ENABLE_SET,Interrupt Enable Set Register for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x0 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 18. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x0 17. "PMC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for pmc_busecc_pend" "0,1" newline bitfld.long 0x0 16. "SE_1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for se_1_busecc_pend" "0,1" newline bitfld.long 0x0 15. "SE_0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for se_0_busecc_pend" "0,1" newline bitfld.long 0x0 14. "BUSECC_TAGRAM_DMC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x0 13. "BUSECC_DMC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_dmc_pend" "0,1" newline bitfld.long 0x0 12. "BUSECC_PIPE3_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x0 11. "BUSECC_PIPE3_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x0 10. "BUSECC_PIPE2_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x0 9. "BUSECC_PIPE2_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x0 8. "BUSECC_PIPE1_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x0 7. "BUSECC_PIPE1_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x0 6. "BUSECC_PIPE0_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x0 5. "BUSECC_PIPE0_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x0 4. "UMC_FW_MDMA_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x0 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 18. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x4 17. "PMC_BUSECC_PEND,Interrupt Pending Status for pmc_busecc_pend" "0,1" newline bitfld.long 0x4 16. "SE_1_BUSECC_PEND,Interrupt Pending Status for se_1_busecc_pend" "0,1" newline bitfld.long 0x4 15. "SE_0_BUSECC_PEND,Interrupt Pending Status for se_0_busecc_pend" "0,1" newline bitfld.long 0x4 14. "BUSECC_TAGRAM_DMC_PEND,Interrupt Pending Status for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x4 13. "BUSECC_DMC_PEND,Interrupt Pending Status for busecc_dmc_pend" "0,1" newline bitfld.long 0x4 12. "BUSECC_PIPE3_P2_PEND,Interrupt Pending Status for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x4 11. "BUSECC_PIPE3_DP_PEND,Interrupt Pending Status for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x4 10. "BUSECC_PIPE2_P2_PEND,Interrupt Pending Status for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x4 9. "BUSECC_PIPE2_DP_PEND,Interrupt Pending Status for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x4 8. "BUSECC_PIPE1_P2_PEND,Interrupt Pending Status for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x4 7. "BUSECC_PIPE1_DP_PEND,Interrupt Pending Status for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x4 6. "BUSECC_PIPE0_P2_PEND,Interrupt Pending Status for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x4 5. "BUSECC_PIPE0_DP_PEND,Interrupt Pending Status for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x4 4. "UMC_FW_MDMA_BUSECC_PEND,Interrupt Pending Status for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x4 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x3 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 18. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x0 17. "PMC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for pmc_busecc_pend" "0,1" newline bitfld.long 0x0 16. "SE_1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for se_1_busecc_pend" "0,1" newline bitfld.long 0x0 15. "SE_0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for se_0_busecc_pend" "0,1" newline bitfld.long 0x0 14. "BUSECC_TAGRAM_DMC_ENABLE_SET,Interrupt Enable Set Register for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x0 13. "BUSECC_DMC_ENABLE_SET,Interrupt Enable Set Register for busecc_dmc_pend" "0,1" newline bitfld.long 0x0 12. "BUSECC_PIPE3_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x0 11. "BUSECC_PIPE3_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x0 10. "BUSECC_PIPE2_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x0 9. "BUSECC_PIPE2_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x0 8. "BUSECC_PIPE1_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x0 7. "BUSECC_PIPE1_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x0 6. "BUSECC_PIPE0_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x0 5. "BUSECC_PIPE0_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x0 4. "UMC_FW_MDMA_BUSECC_ENABLE_SET,Interrupt Enable Set Register for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x0 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 18. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x0 17. "PMC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for pmc_busecc_pend" "0,1" newline bitfld.long 0x0 16. "SE_1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for se_1_busecc_pend" "0,1" newline bitfld.long 0x0 15. "SE_0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for se_0_busecc_pend" "0,1" newline bitfld.long 0x0 14. "BUSECC_TAGRAM_DMC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x0 13. "BUSECC_DMC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_dmc_pend" "0,1" newline bitfld.long 0x0 12. "BUSECC_PIPE3_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x0 11. "BUSECC_PIPE3_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x0 10. "BUSECC_PIPE2_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x0 9. "BUSECC_PIPE2_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x0 8. "BUSECC_PIPE1_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x0 7. "BUSECC_PIPE1_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x0 6. "BUSECC_PIPE0_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x0 5. "BUSECC_PIPE0_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x0 4. "UMC_FW_MDMA_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x0 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_C71SS1_ECC_AGGR_0_DSP1_ECCAGGR (COMPUTE_CLUSTER0_C71SS1_ECC_AGGR_0_DSP1_ECCAGGR)" base ad:0x4D20060000 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 18. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x4 17. "PMC_BUSECC_PEND,Interrupt Pending Status for pmc_busecc_pend" "0,1" newline bitfld.long 0x4 16. "SE_1_BUSECC_PEND,Interrupt Pending Status for se_1_busecc_pend" "0,1" newline bitfld.long 0x4 15. "SE_0_BUSECC_PEND,Interrupt Pending Status for se_0_busecc_pend" "0,1" newline bitfld.long 0x4 14. "BUSECC_TAGRAM_DMC_PEND,Interrupt Pending Status for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x4 13. "BUSECC_DMC_PEND,Interrupt Pending Status for busecc_dmc_pend" "0,1" newline bitfld.long 0x4 12. "BUSECC_PIPE3_P2_PEND,Interrupt Pending Status for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x4 11. "BUSECC_PIPE3_DP_PEND,Interrupt Pending Status for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x4 10. "BUSECC_PIPE2_P2_PEND,Interrupt Pending Status for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x4 9. "BUSECC_PIPE2_DP_PEND,Interrupt Pending Status for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x4 8. "BUSECC_PIPE1_P2_PEND,Interrupt Pending Status for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x4 7. "BUSECC_PIPE1_DP_PEND,Interrupt Pending Status for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x4 6. "BUSECC_PIPE0_P2_PEND,Interrupt Pending Status for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x4 5. "BUSECC_PIPE0_DP_PEND,Interrupt Pending Status for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x4 4. "UMC_FW_MDMA_BUSECC_PEND,Interrupt Pending Status for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x4 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x3 line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 18. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x0 17. "PMC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for pmc_busecc_pend" "0,1" newline bitfld.long 0x0 16. "SE_1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for se_1_busecc_pend" "0,1" newline bitfld.long 0x0 15. "SE_0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for se_0_busecc_pend" "0,1" newline bitfld.long 0x0 14. "BUSECC_TAGRAM_DMC_ENABLE_SET,Interrupt Enable Set Register for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x0 13. "BUSECC_DMC_ENABLE_SET,Interrupt Enable Set Register for busecc_dmc_pend" "0,1" newline bitfld.long 0x0 12. "BUSECC_PIPE3_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x0 11. "BUSECC_PIPE3_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x0 10. "BUSECC_PIPE2_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x0 9. "BUSECC_PIPE2_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x0 8. "BUSECC_PIPE1_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x0 7. "BUSECC_PIPE1_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x0 6. "BUSECC_PIPE0_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x0 5. "BUSECC_PIPE0_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x0 4. "UMC_FW_MDMA_BUSECC_ENABLE_SET,Interrupt Enable Set Register for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x0 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 18. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x0 17. "PMC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for pmc_busecc_pend" "0,1" newline bitfld.long 0x0 16. "SE_1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for se_1_busecc_pend" "0,1" newline bitfld.long 0x0 15. "SE_0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for se_0_busecc_pend" "0,1" newline bitfld.long 0x0 14. "BUSECC_TAGRAM_DMC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x0 13. "BUSECC_DMC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_dmc_pend" "0,1" newline bitfld.long 0x0 12. "BUSECC_PIPE3_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x0 11. "BUSECC_PIPE3_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x0 10. "BUSECC_PIPE2_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x0 9. "BUSECC_PIPE2_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x0 8. "BUSECC_PIPE1_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x0 7. "BUSECC_PIPE1_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x0 6. "BUSECC_PIPE0_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x0 5. "BUSECC_PIPE0_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x0 4. "UMC_FW_MDMA_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x0 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 18. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x4 17. "PMC_BUSECC_PEND,Interrupt Pending Status for pmc_busecc_pend" "0,1" newline bitfld.long 0x4 16. "SE_1_BUSECC_PEND,Interrupt Pending Status for se_1_busecc_pend" "0,1" newline bitfld.long 0x4 15. "SE_0_BUSECC_PEND,Interrupt Pending Status for se_0_busecc_pend" "0,1" newline bitfld.long 0x4 14. "BUSECC_TAGRAM_DMC_PEND,Interrupt Pending Status for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x4 13. "BUSECC_DMC_PEND,Interrupt Pending Status for busecc_dmc_pend" "0,1" newline bitfld.long 0x4 12. "BUSECC_PIPE3_P2_PEND,Interrupt Pending Status for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x4 11. "BUSECC_PIPE3_DP_PEND,Interrupt Pending Status for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x4 10. "BUSECC_PIPE2_P2_PEND,Interrupt Pending Status for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x4 9. "BUSECC_PIPE2_DP_PEND,Interrupt Pending Status for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x4 8. "BUSECC_PIPE1_P2_PEND,Interrupt Pending Status for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x4 7. "BUSECC_PIPE1_DP_PEND,Interrupt Pending Status for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x4 6. "BUSECC_PIPE0_P2_PEND,Interrupt Pending Status for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x4 5. "BUSECC_PIPE0_DP_PEND,Interrupt Pending Status for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x4 4. "UMC_FW_MDMA_BUSECC_PEND,Interrupt Pending Status for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x4 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x3 line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 18. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x0 17. "PMC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for pmc_busecc_pend" "0,1" newline bitfld.long 0x0 16. "SE_1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for se_1_busecc_pend" "0,1" newline bitfld.long 0x0 15. "SE_0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for se_0_busecc_pend" "0,1" newline bitfld.long 0x0 14. "BUSECC_TAGRAM_DMC_ENABLE_SET,Interrupt Enable Set Register for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x0 13. "BUSECC_DMC_ENABLE_SET,Interrupt Enable Set Register for busecc_dmc_pend" "0,1" newline bitfld.long 0x0 12. "BUSECC_PIPE3_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x0 11. "BUSECC_PIPE3_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x0 10. "BUSECC_PIPE2_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x0 9. "BUSECC_PIPE2_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x0 8. "BUSECC_PIPE1_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x0 7. "BUSECC_PIPE1_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x0 6. "BUSECC_PIPE0_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x0 5. "BUSECC_PIPE0_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x0 4. "UMC_FW_MDMA_BUSECC_ENABLE_SET,Interrupt Enable Set Register for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x0 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 18. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x0 17. "PMC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for pmc_busecc_pend" "0,1" newline bitfld.long 0x0 16. "SE_1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for se_1_busecc_pend" "0,1" newline bitfld.long 0x0 15. "SE_0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for se_0_busecc_pend" "0,1" newline bitfld.long 0x0 14. "BUSECC_TAGRAM_DMC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x0 13. "BUSECC_DMC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_dmc_pend" "0,1" newline bitfld.long 0x0 12. "BUSECC_PIPE3_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x0 11. "BUSECC_PIPE3_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x0 10. "BUSECC_PIPE2_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x0 9. "BUSECC_PIPE2_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x0 8. "BUSECC_PIPE1_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x0 7. "BUSECC_PIPE1_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x0 6. "BUSECC_PIPE0_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x0 5. "BUSECC_PIPE0_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x0 4. "UMC_FW_MDMA_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x0 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_CLEC_CLEC (COMPUTE_CLUSTER0_CLEC_CLEC)" base ad:0x78000000 rgroup.long 0x0++0x3 line.long 0x0 "CLEC_REGS_PID,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAX,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0xC000++0x3 line.long 0x0 "CLEC_REGS_GELRS,Event Lock reg for secure claim" bitfld.long 0x0 0. "LOCK,GELRS.LOCK" "0,1" rgroup.long 0xD000++0x3 line.long 0x0 "CLEC_REGS_GELRNS,Event Lock reg for non-secure claim" bitfld.long 0x0 0. "LOCK,GELRNS.LOCK" "0,1" rgroup.long 0x11000++0x3 line.long 0x0 "CLEC_REGS_MRR,Map and routing register" bitfld.long 0x0 31. "S,MRR.S" "0,1" bitfld.long 0x0 30. "ESE,MRR.ESE" "0,1" hexmask.long.byte 0x0 16.--21. 1. "RTMAP,MRR.EXT_EVTNUM" hexmask.long.byte 0x0 8.--13. 1. "EXT_EVTNUM,MRR.EXT_EVTNUM" hexmask.long.byte 0x0 0.--5. 1. "C7X_EVTNUM,MRR.C7x_EVTNUM" rgroup.long 0x13000++0x3 line.long 0x0 "CLEC_REGS_ESR,Event send reg" rgroup.long 0x14000++0x3 line.long 0x0 "CLEC_REGS_ECR,Event clear reg" rgroup.long 0xA000++0x3 line.long 0x0 "CLEC_REGS_EFR,CLEC event flags" hexmask.long 0x0 0.--31. 1. "EVNTFR,event flags" rgroup.long 0xB000++0x3 line.long 0x0 "CLEC_REGS_EDR,CLEC dropped event flags" hexmask.long 0x0 0.--31. 1. "EVNTFR,dropped event flags" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_CORE_CORE_MSMC_CFGS0 (COMPUTE_CLUSTER0_CORE_CORE_MSMC_CFGS0)" base ad:0x6E000000 rgroup.quad 0x0++0x7 line.quad 0x0 "MSMC_CFGS0_pid," hexmask.quad.long 0x0 32.--63. 1. "RSVD," hexmask.quad.long 0x0 0.--31. 1. "REVISION," rgroup.quad 0x1000++0x7 line.quad 0x0 "MSMC_CFGS0_cache_ctrl," hexmask.quad 0x0 11.--63. 1. "RSVD2," bitfld.quad 0x0 10. "ALLOCATION_POLICY," "0,1" rbitfld.quad 0x0 9. "RSVD1," "0,1" newline bitfld.quad 0x0 8. "REPLACEMENT_POLICY," "0,1" rbitfld.quad 0x0 5.--7. "RSVD0," "0,1,2,3,4,5,6,7" rbitfld.quad 0x0 4. "SZ_TRANSITION," "0,1" newline hexmask.quad.byte 0x0 0.--3. 1. "CACHE_SIZE," rgroup.quad 0x1008++0x7 line.quad 0x0 "MSMC_CFGS0_cache_stat," hexmask.quad 0x0 0.--63. 1. "RSVD," rgroup.quad 0x1010++0xF line.quad 0x0 "MSMC_CFGS0_rt_way_select," hexmask.quad 0x0 7.--63. 1. "RSVD1," bitfld.quad 0x0 5.--6. "OR_MASK," "0,1,2,3" rbitfld.quad 0x0 2.--4. "RSVD0," "0,1,2,3,4,5,6,7" newline bitfld.quad 0x0 0.--1. "AND_MASK," "0,1,2,3" line.quad 0x8 "MSMC_CFGS0_nrt_way_select," hexmask.quad 0x8 7.--63. 1. "RSVD1," bitfld.quad 0x8 5.--6. "OR_MASK," "0,1,2,3" rbitfld.quad 0x8 2.--4. "RSVD0," "0,1,2,3,4,5,6,7" newline bitfld.quad 0x8 0.--1. "AND_MASK," "0,1,2,3" rgroup.quad 0x2048++0x7 line.quad 0x0 "MSMC_CFGS0_cohctrl," hexmask.quad 0x0 1.--63. 1. "RSVD0," bitfld.quad 0x0 0. "BCM," "0,1" rgroup.quad 0x3080++0x7 line.quad 0x0 "MSMC_CFGS0_smedcc," hexmask.quad.long 0x0 32.--63. 1. "RSVD1," bitfld.quad 0x0 31. "SEN," "0,1" hexmask.quad.tbyte 0x0 8.--30. 1. "RSVD0," newline hexmask.quad.byte 0x0 0.--7. 1. "REFDEL," rgroup.quad 0x5000++0xF line.quad 0x0 "MSMC_CFGS0_smestat," hexmask.quad 0x0 1.--63. 1. "RSVD0," bitfld.quad 0x0 0. "NULL_SLV," "0,1" line.quad 0x8 "MSMC_CFGS0_smirstat," hexmask.quad 0x8 1.--63. 1. "RSVD0," bitfld.quad 0x8 0. "NULL_SLV," "0,1" rgroup.quad 0x5008++0xF line.quad 0x0 "MSMC_CFGS0_smirws," hexmask.quad 0x0 1.--63. 1. "RSVD0," bitfld.quad 0x0 0. "NULL_SLV," "0,1" line.quad 0x8 "MSMC_CFGS0_smirc," hexmask.quad 0x8 1.--63. 1. "RSVD0," bitfld.quad 0x8 0. "NULL_SLV," "0,1" rgroup.quad 0x5018++0x7 line.quad 0x0 "MSMC_CFGS0_smiestat," hexmask.quad 0x0 1.--63. 1. "RSVD0," bitfld.quad 0x0 0. "NULL_SLV," "0,1" rgroup.quad 0x5018++0xF line.quad 0x0 "MSMC_CFGS0_smiews," hexmask.quad 0x0 1.--63. 1. "RSVD0," bitfld.quad 0x0 0. "NULL_SLV," "0,1" line.quad 0x8 "MSMC_CFGS0_smiec," hexmask.quad 0x8 1.--63. 1. "RSVD0," bitfld.quad 0x8 0. "NULL_SLV," "0,1" rgroup.quad 0x6000++0x67 line.quad 0x0 "MSMC_CFGS0_sbndcoh0," hexmask.quad.byte 0x0 56.--63. 1. "RSVD3," hexmask.quad.byte 0x0 48.--55. 1. "SBNDE_RT," hexmask.quad.byte 0x0 40.--47. 1. "RSVD2," newline hexmask.quad.byte 0x0 32.--39. 1. "SBNDM_RT," hexmask.quad.byte 0x0 24.--31. 1. "RSVD1," hexmask.quad.byte 0x0 16.--23. 1. "SBNDE_NRT," newline hexmask.quad.byte 0x0 8.--15. 1. "RSVD0," hexmask.quad.byte 0x0 0.--7. 1. "SBNDM_NRT," line.quad 0x8 "MSMC_CFGS0_sbndcoh1," hexmask.quad.byte 0x8 56.--63. 1. "RSVD3," hexmask.quad.byte 0x8 48.--55. 1. "SBNDE_RT," hexmask.quad.byte 0x8 40.--47. 1. "RSVD2," newline hexmask.quad.byte 0x8 32.--39. 1. "SBNDM_RT," hexmask.quad.byte 0x8 24.--31. 1. "RSVD1," hexmask.quad.byte 0x8 16.--23. 1. "SBNDE_NRT," newline hexmask.quad.byte 0x8 8.--15. 1. "RSVD0," hexmask.quad.byte 0x8 0.--7. 1. "SBNDM_NRT," line.quad 0x10 "MSMC_CFGS0_sbndcoh2," hexmask.quad.byte 0x10 56.--63. 1. "RSVD3," hexmask.quad.byte 0x10 48.--55. 1. "SBNDE_RT," hexmask.quad.byte 0x10 40.--47. 1. "RSVD2," newline hexmask.quad.byte 0x10 32.--39. 1. "SBNDM_RT," hexmask.quad.byte 0x10 24.--31. 1. "RSVD1," hexmask.quad.byte 0x10 16.--23. 1. "SBNDE_NRT," newline hexmask.quad.byte 0x10 8.--15. 1. "RSVD0," hexmask.quad.byte 0x10 0.--7. 1. "SBNDM_NRT," line.quad 0x18 "MSMC_CFGS0_sbndcoh3," hexmask.quad.byte 0x18 56.--63. 1. "RSVD3," hexmask.quad.byte 0x18 48.--55. 1. "SBNDE_RT," hexmask.quad.byte 0x18 40.--47. 1. "RSVD2," newline hexmask.quad.byte 0x18 32.--39. 1. "SBNDM_RT," hexmask.quad.byte 0x18 24.--31. 1. "RSVD1," hexmask.quad.byte 0x18 16.--23. 1. "SBNDE_NRT," newline hexmask.quad.byte 0x18 8.--15. 1. "RSVD0," hexmask.quad.byte 0x18 0.--7. 1. "SBNDM_NRT," line.quad 0x20 "MSMC_CFGS0_sbndcoh4," hexmask.quad.byte 0x20 56.--63. 1. "RSVD3," hexmask.quad.byte 0x20 48.--55. 1. "SBNDE_RT," hexmask.quad.byte 0x20 40.--47. 1. "RSVD2," newline hexmask.quad.byte 0x20 32.--39. 1. "SBNDM_RT," hexmask.quad.byte 0x20 24.--31. 1. "RSVD1," hexmask.quad.byte 0x20 16.--23. 1. "SBNDE_NRT," newline hexmask.quad.byte 0x20 8.--15. 1. "RSVD0," hexmask.quad.byte 0x20 0.--7. 1. "SBNDM_NRT," line.quad 0x28 "MSMC_CFGS0_sbndcoh5," hexmask.quad.byte 0x28 56.--63. 1. "RSVD3," hexmask.quad.byte 0x28 48.--55. 1. "SBNDE_RT," hexmask.quad.byte 0x28 40.--47. 1. "RSVD2," newline hexmask.quad.byte 0x28 32.--39. 1. "SBNDM_RT," hexmask.quad.byte 0x28 24.--31. 1. "RSVD1," hexmask.quad.byte 0x28 16.--23. 1. "SBNDE_NRT," newline hexmask.quad.byte 0x28 8.--15. 1. "RSVD0," hexmask.quad.byte 0x28 0.--7. 1. "SBNDM_NRT," line.quad 0x30 "MSMC_CFGS0_sbndcoh6," hexmask.quad.byte 0x30 56.--63. 1. "RSVD3," hexmask.quad.byte 0x30 48.--55. 1. "SBNDE_RT," hexmask.quad.byte 0x30 40.--47. 1. "RSVD2," newline hexmask.quad.byte 0x30 32.--39. 1. "SBNDM_RT," hexmask.quad.byte 0x30 24.--31. 1. "RSVD1," hexmask.quad.byte 0x30 16.--23. 1. "SBNDE_NRT," newline hexmask.quad.byte 0x30 8.--15. 1. "RSVD0," hexmask.quad.byte 0x30 0.--7. 1. "SBNDM_NRT," line.quad 0x38 "MSMC_CFGS0_sbndcoh7," hexmask.quad.byte 0x38 56.--63. 1. "RSVD3," hexmask.quad.byte 0x38 48.--55. 1. "SBNDE_RT," hexmask.quad.byte 0x38 40.--47. 1. "RSVD2," newline hexmask.quad.byte 0x38 32.--39. 1. "SBNDM_RT," hexmask.quad.byte 0x38 24.--31. 1. "RSVD1," hexmask.quad.byte 0x38 16.--23. 1. "SBNDE_NRT," newline hexmask.quad.byte 0x38 8.--15. 1. "RSVD0," hexmask.quad.byte 0x38 0.--7. 1. "SBNDM_NRT," line.quad 0x40 "MSMC_CFGS0_sbndcoh8," hexmask.quad.byte 0x40 56.--63. 1. "RSVD3," hexmask.quad.byte 0x40 48.--55. 1. "SBNDE_RT," hexmask.quad.byte 0x40 40.--47. 1. "RSVD2," newline hexmask.quad.byte 0x40 32.--39. 1. "SBNDM_RT," hexmask.quad.byte 0x40 24.--31. 1. "RSVD1," hexmask.quad.byte 0x40 16.--23. 1. "SBNDE_NRT," newline hexmask.quad.byte 0x40 8.--15. 1. "RSVD0," hexmask.quad.byte 0x40 0.--7. 1. "SBNDM_NRT," line.quad 0x48 "MSMC_CFGS0_sbndcoh9," hexmask.quad.byte 0x48 56.--63. 1. "RSVD3," hexmask.quad.byte 0x48 48.--55. 1. "SBNDE_RT," hexmask.quad.byte 0x48 40.--47. 1. "RSVD2," newline hexmask.quad.byte 0x48 32.--39. 1. "SBNDM_RT," hexmask.quad.byte 0x48 24.--31. 1. "RSVD1," hexmask.quad.byte 0x48 16.--23. 1. "SBNDE_NRT," newline hexmask.quad.byte 0x48 8.--15. 1. "RSVD0," hexmask.quad.byte 0x48 0.--7. 1. "SBNDM_NRT," line.quad 0x50 "MSMC_CFGS0_sbndcoh10," hexmask.quad.byte 0x50 56.--63. 1. "RSVD3," hexmask.quad.byte 0x50 48.--55. 1. "SBNDE_RT," hexmask.quad.byte 0x50 40.--47. 1. "RSVD2," newline hexmask.quad.byte 0x50 32.--39. 1. "SBNDM_RT," hexmask.quad.byte 0x50 24.--31. 1. "RSVD1," hexmask.quad.byte 0x50 16.--23. 1. "SBNDE_NRT," newline hexmask.quad.byte 0x50 8.--15. 1. "RSVD0," hexmask.quad.byte 0x50 0.--7. 1. "SBNDM_NRT," line.quad 0x58 "MSMC_CFGS0_sbndcoh11," hexmask.quad.byte 0x58 56.--63. 1. "RSVD3," hexmask.quad.byte 0x58 48.--55. 1. "SBNDE_RT," hexmask.quad.byte 0x58 40.--47. 1. "RSVD2," newline hexmask.quad.byte 0x58 32.--39. 1. "SBNDM_RT," hexmask.quad.byte 0x58 24.--31. 1. "RSVD1," hexmask.quad.byte 0x58 16.--23. 1. "SBNDE_NRT," newline hexmask.quad.byte 0x58 8.--15. 1. "RSVD0," hexmask.quad.byte 0x58 0.--7. 1. "SBNDM_NRT," line.quad 0x60 "MSMC_CFGS0_sbndcoh12," hexmask.quad.byte 0x60 56.--63. 1. "RSVD3," hexmask.quad.byte 0x60 48.--55. 1. "SBNDE_RT," hexmask.quad.byte 0x60 40.--47. 1. "RSVD2," newline hexmask.quad.byte 0x60 32.--39. 1. "SBNDM_RT," hexmask.quad.byte 0x60 24.--31. 1. "RSVD1," hexmask.quad.byte 0x60 16.--23. 1. "SBNDE_NRT," newline hexmask.quad.byte 0x60 8.--15. 1. "RSVD0," hexmask.quad.byte 0x60 0.--7. 1. "SBNDM_NRT," rgroup.quad 0x6100++0x7 line.quad 0x0 "MSMC_CFGS0_sbnddru," hexmask.quad.byte 0x0 56.--63. 1. "RSVD3," hexmask.quad.byte 0x0 48.--55. 1. "SBNDE_RT," hexmask.quad.byte 0x0 40.--47. 1. "RSVD2," newline hexmask.quad.byte 0x0 32.--39. 1. "SBNDM_RT," hexmask.quad.byte 0x0 24.--31. 1. "RSVD1," hexmask.quad.byte 0x0 16.--23. 1. "SBNDE_NRT," newline hexmask.quad.byte 0x0 8.--15. 1. "RSVD0," hexmask.quad.byte 0x0 0.--7. 1. "SBNDM_NRT," rgroup.quad 0x6200++0x7 line.quad 0x0 "MSMC_CFGS0_sbndresp," hexmask.quad.byte 0x0 56.--63. 1. "RSVD3," hexmask.quad.byte 0x0 48.--55. 1. "SBNDE_RT," hexmask.quad.byte 0x0 40.--47. 1. "RSVD2," newline hexmask.quad.byte 0x0 32.--39. 1. "SBNDM_RT," hexmask.quad.byte 0x0 24.--31. 1. "RSVD1," hexmask.quad.byte 0x0 16.--23. 1. "SBNDE_NRT," newline hexmask.quad.byte 0x0 8.--15. 1. "RSVD0," hexmask.quad.byte 0x0 0.--7. 1. "SBNDM_NRT," rgroup.quad 0x7000++0x7 line.quad 0x0 "MSMC_CFGS0_dbgtagctl," hexmask.quad.tbyte 0x0 41.--63. 1. "RSVD3," bitfld.quad 0x0 40. "L3CACHE," "0,1" hexmask.quad.byte 0x0 34.--39. 1. "RSVD2," newline bitfld.quad 0x0 32.--33. "BANK," "0,1,2,3" rbitfld.quad 0x0 30.--31. "RSVD1," "0,1,2,3" hexmask.quad.word 0x0 16.--29. 1. "INDEX," newline hexmask.quad.word 0x0 5.--15. 1. "RSVD0," hexmask.quad.byte 0x0 0.--4. 1. "WAY," rgroup.quad 0x7080++0x7 line.quad 0x0 "MSMC_CFGS0_dbgtagview," hexmask.quad.byte 0x0 59.--63. 1. "RSVD4," hexmask.quad.byte 0x0 54.--58. 1. "SF," bitfld.quad 0x0 53. "RSVD3," "0,1" newline bitfld.quad 0x0 52. "DIRTY," "0,1" bitfld.quad 0x0 51. "RSVD2," "0,1" bitfld.quad 0x0 50. "DATA_VALID," "0,1" newline bitfld.quad 0x0 49. "RSVD1," "0,1" bitfld.quad 0x0 48. "ADDR_VALID," "0,1" hexmask.quad 0x0 2.--47. 1. "ADDRESS," newline bitfld.quad 0x0 1. "RSVD0," "0,1" bitfld.quad 0x0 0. "SECURE," "0,1" rgroup.quad 0xA000++0xF line.quad 0x0 "MSMC_CFGS0_null_slv_stat0," hexmask.quad 0x0 0.--63. 1. "ADDR," line.quad 0x8 "MSMC_CFGS0_null_slv_stat1," hexmask.quad.word 0x8 54.--63. 1. "RSVD5," bitfld.quad 0x8 52.--53. "PRIV," "0,1,2,3" bitfld.quad 0x8 49.--51. "RSVD4," "0,1,2,3,4,5,6,7" newline bitfld.quad 0x8 48. "SECURE," "0,1" bitfld.quad 0x8 45.--47. "RSVD3," "0,1,2,3,4,5,6,7" bitfld.quad 0x8 44. "EMU," "0,1" newline bitfld.quad 0x8 42.--43. "RSVD2," "0,1,2,3" bitfld.quad 0x8 40.--41. "MEMTYPE," "0,1,2,3" bitfld.quad 0x8 38.--39. "RSVD1," "0,1,2,3" newline hexmask.quad.byte 0x8 32.--37. 1. "OPCODE," hexmask.quad.byte 0x8 24.--31. 1. "PRIVID," hexmask.quad.word 0x8 12.--23. 1. "ROUTEID," newline bitfld.quad 0x8 10.--11. "RSVD0," "0,1,2,3" hexmask.quad.word 0x8 0.--9. 1. "BYTECNT," rgroup.quad 0xA018++0x7 line.quad 0x0 "MSMC_CFGS0_null_slv_cnt," hexmask.quad 0x0 8.--63. 1. "RSVD0," hexmask.quad.byte 0x0 0.--7. 1. "COUNT," tree.end endif tree "COMPUTE_CLUSTER0_A72SS0" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_MPU0_CORE0_ECC_AGGR (COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_MPU0_CORE0_ECC_AGGR)" base ad:0x4D20010400 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_CORE0_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_CORE0_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_CORE0_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_CORE0_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_CORE0_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_CFG0__CFG_ARM_ECC_CORE0_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 24. "EDC_CTRL_ECCAGGR_CPU0_PEND,Interrupt Pending Status for edc_ctrl_eccaggr_cpu0_pend" "0,1" newline bitfld.long 0x4 23. "CPU0_L2_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 22. "CPU0_L2_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 21. "CPU0_L2_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 20. "CPU0_L2_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_LS_TAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 18. "CPU0_LS_TAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_LS_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 16. "CPU0_LS_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_LS_DATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 14. "CPU0_LS_DATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_LS_DATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 12. "CPU0_LS_DATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_LS_DATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 10. "CPU0_LS_DATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_LS_DATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 8. "CPU0_LS_DATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_IF_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_if_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 6. "CPU0_IF_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_IF_DATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_if_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 4. "CPU0_IF_DATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_IF_DATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_if_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 2. "CPU0_IF_DATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_IF_DATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_if_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_IF_DATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_if_data_spram_bank0_ecc_svbus_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_CORE0_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 24. "EDC_CTRL_ECCAGGR_CPU0_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_eccaggr_cpu0_pend" "0,1" newline bitfld.long 0x0 23. "CPU0_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU0_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU0_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_if_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_if_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_if_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_if_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_if_data_spram_bank0_ecc_svbus_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_CORE0_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 24. "EDC_CTRL_ECCAGGR_CPU0_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_eccaggr_cpu0_pend" "0,1" newline bitfld.long 0x0 23. "CPU0_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU0_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU0_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_if_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_if_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_if_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_if_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_if_data_spram_bank0_ecc_svbus_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_CORE0_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_CFG0__CFG_ARM_ECC_CORE0_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 24. "EDC_CTRL_ECCAGGR_CPU0_PEND,Interrupt Pending Status for edc_ctrl_eccaggr_cpu0_pend" "0,1" newline bitfld.long 0x4 23. "CPU0_L2_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 22. "CPU0_L2_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 21. "CPU0_L2_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 20. "CPU0_L2_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_LS_TAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 18. "CPU0_LS_TAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_LS_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 16. "CPU0_LS_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_LS_DATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 14. "CPU0_LS_DATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_LS_DATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 12. "CPU0_LS_DATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_LS_DATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 10. "CPU0_LS_DATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_LS_DATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 8. "CPU0_LS_DATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_IF_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_if_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 6. "CPU0_IF_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_IF_DATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_if_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 4. "CPU0_IF_DATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_IF_DATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_if_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 2. "CPU0_IF_DATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_IF_DATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_if_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_IF_DATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_if_data_spram_bank0_ecc_svbus_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_CORE0_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 24. "EDC_CTRL_ECCAGGR_CPU0_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_eccaggr_cpu0_pend" "0,1" newline bitfld.long 0x0 23. "CPU0_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU0_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU0_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_if_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_if_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_if_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_if_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_if_data_spram_bank0_ecc_svbus_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_CORE0_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 24. "EDC_CTRL_ECCAGGR_CPU0_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_eccaggr_cpu0_pend" "0,1" newline bitfld.long 0x0 23. "CPU0_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU0_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU0_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_if_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_if_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_if_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_if_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_if_data_spram_bank0_ecc_svbus_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_CORE0_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP_CFG0__CFG_ARM_ECC_CORE0_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP_CFG0__CFG_ARM_ECC_CORE0_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP_CFG0__CFG_ARM_ECC_CORE0_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_MPU0_CORE1_ECC_AGGR (COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_MPU0_CORE1_ECC_AGGR)" base ad:0x4D20010800 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_CORE1_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_CORE1_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_CORE1_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_CORE1_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_CORE1_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_CFG0__CFG_ARM_ECC_CORE1_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 24. "EDC_CTRL_ECCAGGR_CPU1_PEND,Interrupt Pending Status for edc_ctrl_eccaggr_cpu1_pend" "0,1" newline bitfld.long 0x4 23. "CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 22. "CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 21. "CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 20. "CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 18. "CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 16. "CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 14. "CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 12. "CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 10. "CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 8. "CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_if_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 6. "CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_if_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 4. "CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_if_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 2. "CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_if_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 0. "CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_if_data_spram_bank0_ecc_svbus_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_CORE1_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 24. "EDC_CTRL_ECCAGGR_CPU1_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_eccaggr_cpu1_pend" "0,1" newline bitfld.long 0x0 23. "CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_if_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_if_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_if_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_if_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_if_data_spram_bank0_ecc_svbus_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_CORE1_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 24. "EDC_CTRL_ECCAGGR_CPU1_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_eccaggr_cpu1_pend" "0,1" newline bitfld.long 0x0 23. "CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_if_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_if_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_if_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_if_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_if_data_spram_bank0_ecc_svbus_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_CORE1_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_CFG0__CFG_ARM_ECC_CORE1_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 24. "EDC_CTRL_ECCAGGR_CPU1_PEND,Interrupt Pending Status for edc_ctrl_eccaggr_cpu1_pend" "0,1" newline bitfld.long 0x4 23. "CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 22. "CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 21. "CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 20. "CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 18. "CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 16. "CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 14. "CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 12. "CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 10. "CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 8. "CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_if_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 6. "CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_if_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 4. "CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_if_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 2. "CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_if_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 0. "CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_if_data_spram_bank0_ecc_svbus_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_CORE1_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 24. "EDC_CTRL_ECCAGGR_CPU1_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_eccaggr_cpu1_pend" "0,1" newline bitfld.long 0x0 23. "CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_if_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_if_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_if_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_if_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_if_data_spram_bank0_ecc_svbus_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_CORE1_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 24. "EDC_CTRL_ECCAGGR_CPU1_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_eccaggr_cpu1_pend" "0,1" newline bitfld.long 0x0 23. "CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_if_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_if_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_if_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_if_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_if_data_spram_bank0_ecc_svbus_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_CORE1_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP_CFG0__CFG_ARM_ECC_CORE1_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP_CFG0__CFG_ARM_ECC_CORE1_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP_CFG0__CFG_ARM_ECC_CORE1_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_MPU0_COREPAC_ECC_AGGR (COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_MPU0_COREPAC_ECC_AGGR)" base ad:0x4D20010000 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_COREPAC_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_COREPAC_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_COREPAC_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_COREPAC_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_COREPAC_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_CFG0__CFG_ARM_ECC_COREPAC_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for l2_incl_plru_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 30. "L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for l2_incl_plru_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 29. "L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for l2_dirty_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 28. "L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for l2_dirty_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 27. "L2_TAG_SPRAM_BANK15_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank15_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 26. "L2_TAG_SPRAM_BANK14_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank14_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 25. "L2_TAG_SPRAM_BANK13_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank13_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 24. "L2_TAG_SPRAM_BANK12_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank12_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 23. "L2_TAG_SPRAM_BANK11_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank11_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 22. "L2_TAG_SPRAM_BANK10_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank10_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 21. "L2_TAG_SPRAM_BANK9_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank9_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 20. "L2_TAG_SPRAM_BANK8_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank8_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 19. "L2_TAG_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 18. "L2_TAG_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 17. "L2_TAG_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 16. "L2_TAG_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 15. "L2_TAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 14. "L2_TAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 13. "L2_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 12. "L2_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 11. "L2_DATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for l2_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 10. "L2_DATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for l2_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 9. "L2_DATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for l2_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 8. "L2_DATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for l2_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 7. "L2_DATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for l2_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 6. "L2_DATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for l2_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 5. "L2_DATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for l2_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 4. "L2_DATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for l2_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 3. "L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for l2_snp_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 2. "L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for l2_snp_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 1. "L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for l2_snp_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 0. "L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for l2_snp_tag_spram_bank0_ecc_svbus_pend" "0,1" line.long 0x8 "__VBUSP_CFG0__CFG_ARM_ECC_COREPAC_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 9. "VBUSP_CFG_DST_M2P_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_dst_m2p_dst_busecc_pend" "0,1" newline bitfld.long 0x8 8. "VBUSP_CFG_M2M_M2M_VBUSS_PEND,Interrupt Pending Status for vbusp_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x8 7. "VBUSP_CFG_M2M_DST_VBUSS_PEND,Interrupt Pending Status for vbusp_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x8 6. "VBUSP_CFG_DST_M2P_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x8 5. "A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_PEND,Interrupt Pending Status for a72_j7_corepac_cbass_divh_clk2_clk_clk_edc_ctrl_cbass_int_divh_clk2_clk_busecc_pend" "0,1" newline bitfld.long 0x8 4. "A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for a72_j7_corepac_cbass_scr1_scr_a72_j7_corepac_cbass_scr1_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 3. "A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_PEND,Interrupt Pending Status for a72_j7_corepac_cbass_vbusp_ecc_corepac_p2p_bridge_vbusp_ecc_corepac_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 2. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_PEND,Interrupt Pending Status for a72_j7_corepac_cbass_vbusp_ecc_core1_p2p_bridge_vbusp_ecc_core1_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 1. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for a72_j7_corepac_cbass_vbusp_ecc_core0_p2p_bridge_vbusp_ecc_core0_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 0. "EDC_CTRL_ECCAGGR_COREPAC_PEND,Interrupt Pending Status for edc_ctrl_eccaggr_corepac_pend" "0,1" rgroup.long 0x80++0x7 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_COREPAC_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_incl_plru_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 30. "L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_incl_plru_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 29. "L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_dirty_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 28. "L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_dirty_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 27. "L2_TAG_SPRAM_BANK15_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank15_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 26. "L2_TAG_SPRAM_BANK14_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank14_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "L2_TAG_SPRAM_BANK13_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank13_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "L2_TAG_SPRAM_BANK12_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank12_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "L2_TAG_SPRAM_BANK11_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank11_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "L2_TAG_SPRAM_BANK10_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank10_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "L2_TAG_SPRAM_BANK9_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank9_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "L2_TAG_SPRAM_BANK8_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank8_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "L2_TAG_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "L2_TAG_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "L2_TAG_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "L2_TAG_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "L2_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "L2_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "L2_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "L2_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "L2_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "L2_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "L2_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "L2_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "L2_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "L2_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "L2_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "L2_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_snp_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_snp_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_snp_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_snp_tag_spram_bank0_ecc_svbus_pend" "0,1" line.long 0x4 "__VBUSP_CFG0__CFG_ARM_ECC_COREPAC_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 9. "VBUSP_CFG_DST_M2P_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_dst_m2p_dst_busecc_pend" "0,1" newline bitfld.long 0x4 8. "VBUSP_CFG_M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 7. "VBUSP_CFG_M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 6. "VBUSP_CFG_DST_M2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 5. "A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_ENABLE_SET,Interrupt Enable Set Register for a72_j7_corepac_cbass_divh_clk2_clk_clk_edc_ctrl_cbass_int_divh_clk2_clk_busecc_pend" "0,1" newline bitfld.long 0x4 4. "A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for a72_j7_corepac_cbass_scr1_scr_a72_j7_corepac_cbass_scr1_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for a72_j7_corepac_cbass_vbusp_ecc_corepac_p2p_bridge_vbusp_ecc_corepac_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 2. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for a72_j7_corepac_cbass_vbusp_ecc_core1_p2p_bridge_vbusp_ecc_core1_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 1. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for a72_j7_corepac_cbass_vbusp_ecc_core0_p2p_bridge_vbusp_ecc_core0_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 0. "EDC_CTRL_ECCAGGR_COREPAC_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_eccaggr_corepac_pend" "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_COREPAC_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_incl_plru_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 30. "L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_incl_plru_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 29. "L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_dirty_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 28. "L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_dirty_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 27. "L2_TAG_SPRAM_BANK15_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank15_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 26. "L2_TAG_SPRAM_BANK14_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank14_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "L2_TAG_SPRAM_BANK13_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank13_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "L2_TAG_SPRAM_BANK12_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank12_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "L2_TAG_SPRAM_BANK11_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank11_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "L2_TAG_SPRAM_BANK10_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank10_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "L2_TAG_SPRAM_BANK9_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank9_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "L2_TAG_SPRAM_BANK8_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank8_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "L2_TAG_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "L2_TAG_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "L2_TAG_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "L2_TAG_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "L2_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "L2_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "L2_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "L2_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "L2_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "L2_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "L2_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "L2_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "L2_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "L2_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "L2_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "L2_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_snp_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_snp_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_snp_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_snp_tag_spram_bank0_ecc_svbus_pend" "0,1" line.long 0x4 "__VBUSP_CFG0__CFG_ARM_ECC_COREPAC_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 9. "VBUSP_CFG_DST_M2P_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_dst_m2p_dst_busecc_pend" "0,1" newline bitfld.long 0x4 8. "VBUSP_CFG_M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 7. "VBUSP_CFG_M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 6. "VBUSP_CFG_DST_M2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 5. "A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for a72_j7_corepac_cbass_divh_clk2_clk_clk_edc_ctrl_cbass_int_divh_clk2_clk_busecc_pend" "0,1" newline bitfld.long 0x4 4. "A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for a72_j7_corepac_cbass_scr1_scr_a72_j7_corepac_cbass_scr1_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for a72_j7_corepac_cbass_vbusp_ecc_corepac_p2p_bridge_vbusp_ecc_corepac_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 2. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for a72_j7_corepac_cbass_vbusp_ecc_core1_p2p_bridge_vbusp_ecc_core1_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 1. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for a72_j7_corepac_cbass_vbusp_ecc_core0_p2p_bridge_vbusp_ecc_core0_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 0. "EDC_CTRL_ECCAGGR_COREPAC_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_eccaggr_corepac_pend" "0,1" rgroup.long 0x13C++0xB line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_COREPAC_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_CFG0__CFG_ARM_ECC_COREPAC_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for l2_incl_plru_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 30. "L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for l2_incl_plru_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 29. "L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for l2_dirty_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 28. "L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for l2_dirty_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 27. "L2_TAG_SPRAM_BANK15_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank15_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 26. "L2_TAG_SPRAM_BANK14_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank14_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 25. "L2_TAG_SPRAM_BANK13_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank13_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 24. "L2_TAG_SPRAM_BANK12_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank12_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 23. "L2_TAG_SPRAM_BANK11_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank11_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 22. "L2_TAG_SPRAM_BANK10_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank10_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 21. "L2_TAG_SPRAM_BANK9_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank9_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 20. "L2_TAG_SPRAM_BANK8_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank8_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 19. "L2_TAG_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 18. "L2_TAG_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 17. "L2_TAG_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 16. "L2_TAG_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 15. "L2_TAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 14. "L2_TAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 13. "L2_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 12. "L2_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for l2_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 11. "L2_DATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for l2_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 10. "L2_DATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for l2_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 9. "L2_DATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for l2_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 8. "L2_DATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for l2_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 7. "L2_DATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for l2_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 6. "L2_DATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for l2_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 5. "L2_DATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for l2_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 4. "L2_DATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for l2_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 3. "L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for l2_snp_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 2. "L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for l2_snp_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 1. "L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for l2_snp_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 0. "L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for l2_snp_tag_spram_bank0_ecc_svbus_pend" "0,1" line.long 0x8 "__VBUSP_CFG0__CFG_ARM_ECC_COREPAC_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 9. "VBUSP_CFG_DST_M2P_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_dst_m2p_dst_busecc_pend" "0,1" newline bitfld.long 0x8 8. "VBUSP_CFG_M2M_M2M_VBUSS_PEND,Interrupt Pending Status for vbusp_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x8 7. "VBUSP_CFG_M2M_DST_VBUSS_PEND,Interrupt Pending Status for vbusp_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x8 6. "VBUSP_CFG_DST_M2P_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x8 5. "A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_PEND,Interrupt Pending Status for a72_j7_corepac_cbass_divh_clk2_clk_clk_edc_ctrl_cbass_int_divh_clk2_clk_busecc_pend" "0,1" newline bitfld.long 0x8 4. "A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for a72_j7_corepac_cbass_scr1_scr_a72_j7_corepac_cbass_scr1_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 3. "A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_PEND,Interrupt Pending Status for a72_j7_corepac_cbass_vbusp_ecc_corepac_p2p_bridge_vbusp_ecc_corepac_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 2. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_PEND,Interrupt Pending Status for a72_j7_corepac_cbass_vbusp_ecc_core1_p2p_bridge_vbusp_ecc_core1_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 1. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for a72_j7_corepac_cbass_vbusp_ecc_core0_p2p_bridge_vbusp_ecc_core0_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 0. "EDC_CTRL_ECCAGGR_COREPAC_PEND,Interrupt Pending Status for edc_ctrl_eccaggr_corepac_pend" "0,1" rgroup.long 0x180++0x7 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_COREPAC_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_incl_plru_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 30. "L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_incl_plru_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 29. "L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_dirty_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 28. "L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_dirty_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 27. "L2_TAG_SPRAM_BANK15_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank15_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 26. "L2_TAG_SPRAM_BANK14_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank14_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "L2_TAG_SPRAM_BANK13_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank13_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "L2_TAG_SPRAM_BANK12_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank12_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "L2_TAG_SPRAM_BANK11_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank11_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "L2_TAG_SPRAM_BANK10_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank10_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "L2_TAG_SPRAM_BANK9_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank9_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "L2_TAG_SPRAM_BANK8_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank8_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "L2_TAG_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "L2_TAG_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "L2_TAG_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "L2_TAG_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "L2_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "L2_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "L2_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "L2_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "L2_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "L2_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "L2_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "L2_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "L2_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "L2_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "L2_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "L2_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_snp_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_snp_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_snp_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for l2_snp_tag_spram_bank0_ecc_svbus_pend" "0,1" line.long 0x4 "__VBUSP_CFG0__CFG_ARM_ECC_COREPAC_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 9. "VBUSP_CFG_DST_M2P_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_dst_m2p_dst_busecc_pend" "0,1" newline bitfld.long 0x4 8. "VBUSP_CFG_M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 7. "VBUSP_CFG_M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 6. "VBUSP_CFG_DST_M2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 5. "A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_ENABLE_SET,Interrupt Enable Set Register for a72_j7_corepac_cbass_divh_clk2_clk_clk_edc_ctrl_cbass_int_divh_clk2_clk_busecc_pend" "0,1" newline bitfld.long 0x4 4. "A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for a72_j7_corepac_cbass_scr1_scr_a72_j7_corepac_cbass_scr1_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for a72_j7_corepac_cbass_vbusp_ecc_corepac_p2p_bridge_vbusp_ecc_corepac_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 2. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for a72_j7_corepac_cbass_vbusp_ecc_core1_p2p_bridge_vbusp_ecc_core1_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 1. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for a72_j7_corepac_cbass_vbusp_ecc_core0_p2p_bridge_vbusp_ecc_core0_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 0. "EDC_CTRL_ECCAGGR_COREPAC_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_eccaggr_corepac_pend" "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_COREPAC_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_incl_plru_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 30. "L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_incl_plru_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 29. "L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_dirty_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 28. "L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_dirty_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 27. "L2_TAG_SPRAM_BANK15_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank15_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 26. "L2_TAG_SPRAM_BANK14_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank14_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "L2_TAG_SPRAM_BANK13_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank13_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "L2_TAG_SPRAM_BANK12_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank12_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "L2_TAG_SPRAM_BANK11_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank11_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "L2_TAG_SPRAM_BANK10_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank10_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "L2_TAG_SPRAM_BANK9_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank9_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "L2_TAG_SPRAM_BANK8_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank8_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "L2_TAG_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "L2_TAG_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "L2_TAG_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "L2_TAG_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "L2_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "L2_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "L2_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "L2_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "L2_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "L2_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "L2_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "L2_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "L2_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "L2_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "L2_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "L2_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_snp_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_snp_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_snp_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for l2_snp_tag_spram_bank0_ecc_svbus_pend" "0,1" line.long 0x4 "__VBUSP_CFG0__CFG_ARM_ECC_COREPAC_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 9. "VBUSP_CFG_DST_M2P_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_dst_m2p_dst_busecc_pend" "0,1" newline bitfld.long 0x4 8. "VBUSP_CFG_M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 7. "VBUSP_CFG_M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 6. "VBUSP_CFG_DST_M2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 5. "A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for a72_j7_corepac_cbass_divh_clk2_clk_clk_edc_ctrl_cbass_int_divh_clk2_clk_busecc_pend" "0,1" newline bitfld.long 0x4 4. "A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for a72_j7_corepac_cbass_scr1_scr_a72_j7_corepac_cbass_scr1_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for a72_j7_corepac_cbass_vbusp_ecc_corepac_p2p_bridge_vbusp_ecc_corepac_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 2. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for a72_j7_corepac_cbass_vbusp_ecc_core1_p2p_bridge_vbusp_ecc_core1_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 1. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for a72_j7_corepac_cbass_vbusp_ecc_core0_p2p_bridge_vbusp_ecc_core0_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 0. "EDC_CTRL_ECCAGGR_COREPAC_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_eccaggr_corepac_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP_CFG0__CFG_ARM_ECC_COREPAC_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP_CFG0__CFG_ARM_ECC_COREPAC_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP_CFG0__CFG_ARM_ECC_COREPAC_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP_CFG0__CFG_ARM_ECC_COREPAC_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif tree.end tree "COMPUTE_CLUSTER0_CFG" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_CFG_WRAP_0_MSMC_PBIST0 (COMPUTE_CLUSTER0_CFG_WRAP_0_MSMC_PBIST0)" base ad:0x4D10000000 rgroup.long 0x100++0x27 line.long 0x0 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_A0,Variable Address Registers" hexmask.long.word 0x0 0.--15. 1. "A0,Variable Address Register 0 [A0]" line.long 0x4 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_A1,Variable Address Registers" hexmask.long.word 0x4 0.--15. 1. "A1,Variable Address Register 1 [A1]" line.long 0x8 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_A2,Variable Address Registers" hexmask.long.word 0x8 0.--15. 1. "A2,Variable Address Register 2 [A2]" line.long 0xC "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_A3,Variable Address Registers" hexmask.long.word 0xC 0.--15. 1. "A3,Variable Address Register 3 [A3]" line.long 0x10 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_L0,Variable Loop Count Registers" hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 [L0]" line.long 0x14 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_L1,Variable Loop Count Registers" hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 [L1]" line.long 0x18 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_L2,Variable Loop Count Registers" hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 [L2]" line.long 0x1C "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_L3,Variable Loop Count Registers" hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 [L3]" line.long 0x20 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_D,Data Registers" hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 [D1]" hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 [D0]" line.long 0x24 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_E,Data Registers" hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 [E1]" hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 [E0]" rgroup.long 0x130++0x3F line.long 0x0 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_CA0,Constant Address Registers" hexmask.long.word 0x0 0.--15. 1. "CA0,Constant Address Register 0 [CA0]" line.long 0x4 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_CA1,Constant Address Registers" hexmask.long.word 0x4 0.--15. 1. "CA1,Constant Address Register 1 [CA1]" line.long 0x8 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_CA2,Constant Address Registers" hexmask.long.word 0x8 0.--15. 1. "CA2,Constant Address Register 2 [CA2]" line.long 0xC "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_CA3,Constant Address Registers" hexmask.long.word 0xC 0.--15. 1. "CA3,Constant Address Register 3 [CA3]" line.long 0x10 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_CL0,Constant Loop Count Registers" hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 [CL0]" line.long 0x14 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_CL1,Constant Loop Count Registers" hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 [CL1]" line.long 0x18 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_CL2,Constant Loop Count Registers" hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 [CL2]" line.long 0x1C "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_CL3,Constant Loop Count Registers" hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 [CL3]" line.long 0x20 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_I0,Constant Increment Registers" hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 [I0]" line.long 0x24 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_I1,Constant Increment Registers" hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 [I1]" line.long 0x28 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_I2,Constant Increment Registers" hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 [I2]" line.long 0x2C "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_I3,Constant Increment Registers" hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 [I3]" line.long 0x30 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_RAMT,RAM Configuration Register" hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS" hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS" hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR" newline hexmask.long.byte 0x30 2.--5. 1. "PLS,Pipeline Latency Select" bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3" line.long 0x34 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_DLR,Datalogger Register" hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 [BRP]" bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1" bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1" newline bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode [mainly for ROM testing]" "0,1" bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1" bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1" newline bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1" bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1" bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1" newline bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1" bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1" bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1" line.long 0x38 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_CMS,Clock-Mux Select Register" hexmask.long.byte 0x38 0.--3. 1. "CMS,Clock Mux Select [CMS]" line.long 0x3C "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_STR,Program Control Register" bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1" bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1" bitfld.long 0x3C 2. "STOP,Stop" "0,1" newline bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1" bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1" rgroup.quad 0x170++0x7 line.quad 0x0 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_SCR,Address Scrambling Register" hexmask.quad.byte 0x0 56.--63. 1. "SCR7,Address Scrambling Register 7" hexmask.quad.byte 0x0 48.--55. 1. "SCR6,Address Scrambling Register 6" hexmask.quad.byte 0x0 40.--47. 1. "SCR5,Address Scrambling Register 5" newline hexmask.quad.byte 0x0 32.--39. 1. "SCR4,Address Scrambling Register 4" hexmask.quad.byte 0x0 24.--31. 1. "SCR3,Address Scrambling Register 3" hexmask.quad.byte 0x0 16.--23. 1. "SCR2,Address Scrambling Register 2" newline hexmask.quad.byte 0x0 8.--15. 1. "SCR1,Address Scrambling Register 1" hexmask.quad.byte 0x0 0.--7. 1. "SCR0,Address Scrambling Register 0" rgroup.long 0x178++0x13 line.long 0x0 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_CSR,Chip Select Register" hexmask.long.byte 0x0 24.--31. 1. "CSR3,Chip Select 3 [CSR3]" hexmask.long.byte 0x0 16.--23. 1. "CSR2,Chip Select 2 [CSR2]" hexmask.long.byte 0x0 8.--15. 1. "CSR1,Chip Select 1[CSR1]" newline hexmask.long.byte 0x0 0.--7. 1. "CSR0,Chip Select 0 [CSR0]" line.long 0x4 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_FDLY,Fail Delay Register" hexmask.long.byte 0x4 0.--7. 1. "FDLY,Fail Delay [FDLY]" line.long 0x8 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_PACT,PACT Register" bitfld.long 0x8 0. "PACT,PBIST Activate [PACT]" "0,1" line.long 0xC "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_PID,PBIST_ID Register" hexmask.long.byte 0xC 0.--4. 1. "PID,PBIST ID" line.long 0x10 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_OVER,Override Register" bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1" bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1" bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1" newline bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1" rgroup.quad 0x190++0x17 line.quad 0x0 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_FSRF,Fail Status Fail Register" bitfld.quad 0x0 32. "FRSF1,Fail Status Fail - Port 1 [FSRF1]" "0,1" bitfld.quad 0x0 0. "FRSF0,Fail Status Fail - Port 0 [FSRF0]" "0,1" line.quad 0x8 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_FSRC,Fail Status Count Register" hexmask.quad.byte 0x8 32.--35. 1. "FSRC1,Fail Status Count - Port 1 [FSRC1]" hexmask.quad.byte 0x8 0.--3. 1. "FSRC0,Fail Status Count - Port 0 [FSRC0]" line.quad 0x10 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_FSRA,Fail Status Address Register" hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 [FSRA1]" hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 [FSRA0]" rgroup.long 0x1A8++0x3 line.long 0x0 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_FSRDL0,Fail Status Data Registers" hexmask.long 0x0 0.--31. 1. "FSRDL0,Fail Status Data - Port 0 [FSRDL0]" rgroup.long 0x1B0++0xF line.long 0x0 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_FSRDL1,Fail Status Data Registers" hexmask.long 0x0 0.--31. 1. "FSRDL1,Fail Status Data - Port 1 [FSRDL1]" line.long 0x4 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_MARGIN_MODE,Fail Status Fail Register" bitfld.long 0x4 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3" bitfld.long 0x4 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3" line.long 0x8 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_WRENZ,Fail Status Fail Register" bitfld.long 0x8 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3" line.long 0xC "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_PAGE_PGS,Fail Status Fail Register" bitfld.long 0xC 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3" rgroup.long 0x1C0++0x7 line.long 0x0 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_ROM,ROM Mask Register" bitfld.long 0x0 0.--1. "ROM,ROM Mask [ROM]" "0,1,2,3" line.long 0x4 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_ALGO,Algorithm Mask Register" hexmask.long.byte 0x4 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 [ALGO 3]" hexmask.long.byte 0x4 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 [ALGO 2]" hexmask.long.byte 0x4 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 [ALGO 1]" newline hexmask.long.byte 0x4 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 [ALGO 0]" rgroup.quad 0x1C8++0x7 line.quad 0x0 "__VBUSP4_CFG_MSMC_PBIST0__CFG_MSMC_PBIST0_RINFO,RAM Info Mask Register" hexmask.quad.byte 0x0 56.--63. 1. "U3,RAM Info Mask Upper 3 [RINFOU3]" hexmask.quad.byte 0x0 48.--55. 1. "U2,RAM Info Mask Upper 2 [RINFOU2]" hexmask.quad.byte 0x0 40.--47. 1. "U1,RAM Info Mask Upper 1 [RINFOU1]" newline hexmask.quad.byte 0x0 32.--39. 1. "U0,RAM Info Mask Upper 0 [RINFOU0]" hexmask.quad.byte 0x0 24.--31. 1. "L3,RAM Info Mask Lower 3 [RINFOL3]" hexmask.quad.byte 0x0 16.--23. 1. "L2,RAM Info Mask Lower 2 [RINFOL2]" newline hexmask.quad.byte 0x0 8.--15. 1. "L1,RAM Info Mask Lower 1 [RINFOL1]" hexmask.quad.byte 0x0 0.--7. 1. "L0,RAM Info Mask Lower 0 [RINFOL0]" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_CFG_WRAP_0_MPU_PBIST0 (COMPUTE_CLUSTER0_CFG_WRAP_0_MPU_PBIST0)" base ad:0x4D10010000 rgroup.long 0x100++0x27 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_PBIST0_A0,Variable Address Registers" hexmask.long.word 0x0 0.--15. 1. "A0,Variable Address Register 0 [A0]" line.long 0x4 "__VBUSP_CFG0__CFG_ARM_PBIST0_A1,Variable Address Registers" hexmask.long.word 0x4 0.--15. 1. "A1,Variable Address Register 1 [A1]" line.long 0x8 "__VBUSP_CFG0__CFG_ARM_PBIST0_A2,Variable Address Registers" hexmask.long.word 0x8 0.--15. 1. "A2,Variable Address Register 2 [A2]" line.long 0xC "__VBUSP_CFG0__CFG_ARM_PBIST0_A3,Variable Address Registers" hexmask.long.word 0xC 0.--15. 1. "A3,Variable Address Register 3 [A3]" line.long 0x10 "__VBUSP_CFG0__CFG_ARM_PBIST0_L0,Variable Loop Count Registers" hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 [L0]" line.long 0x14 "__VBUSP_CFG0__CFG_ARM_PBIST0_L1,Variable Loop Count Registers" hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 [L1]" line.long 0x18 "__VBUSP_CFG0__CFG_ARM_PBIST0_L2,Variable Loop Count Registers" hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 [L2]" line.long 0x1C "__VBUSP_CFG0__CFG_ARM_PBIST0_L3,Variable Loop Count Registers" hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 [L3]" line.long 0x20 "__VBUSP_CFG0__CFG_ARM_PBIST0_D,Data Registers" hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 [D1]" hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 [D0]" line.long 0x24 "__VBUSP_CFG0__CFG_ARM_PBIST0_E,Data Registers" hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 [E1]" hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 [E0]" rgroup.long 0x130++0x3F line.long 0x0 "__VBUSP_CFG0__CFG_ARM_PBIST0_CA0,Constant Address Registers" hexmask.long.word 0x0 0.--15. 1. "CA0,Constant Address Register 0 [CA0]" line.long 0x4 "__VBUSP_CFG0__CFG_ARM_PBIST0_CA1,Constant Address Registers" hexmask.long.word 0x4 0.--15. 1. "CA1,Constant Address Register 1 [CA1]" line.long 0x8 "__VBUSP_CFG0__CFG_ARM_PBIST0_CA2,Constant Address Registers" hexmask.long.word 0x8 0.--15. 1. "CA2,Constant Address Register 2 [CA2]" line.long 0xC "__VBUSP_CFG0__CFG_ARM_PBIST0_CA3,Constant Address Registers" hexmask.long.word 0xC 0.--15. 1. "CA3,Constant Address Register 3 [CA3]" line.long 0x10 "__VBUSP_CFG0__CFG_ARM_PBIST0_CL0,Constant Loop Count Registers" hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 [CL0]" line.long 0x14 "__VBUSP_CFG0__CFG_ARM_PBIST0_CL1,Constant Loop Count Registers" hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 [CL1]" line.long 0x18 "__VBUSP_CFG0__CFG_ARM_PBIST0_CL2,Constant Loop Count Registers" hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 [CL2]" line.long 0x1C "__VBUSP_CFG0__CFG_ARM_PBIST0_CL3,Constant Loop Count Registers" hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 [CL3]" line.long 0x20 "__VBUSP_CFG0__CFG_ARM_PBIST0_I0,Constant Increment Registers" hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 [I0]" line.long 0x24 "__VBUSP_CFG0__CFG_ARM_PBIST0_I1,Constant Increment Registers" hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 [I1]" line.long 0x28 "__VBUSP_CFG0__CFG_ARM_PBIST0_I2,Constant Increment Registers" hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 [I2]" line.long 0x2C "__VBUSP_CFG0__CFG_ARM_PBIST0_I3,Constant Increment Registers" hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 [I3]" line.long 0x30 "__VBUSP_CFG0__CFG_ARM_PBIST0_RAMT,RAM Configuration Register" hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS" hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS" hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR" hexmask.long.byte 0x30 2.--5. 1. "PLS,Pipeline Latency Select" newline bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3" line.long 0x34 "__VBUSP_CFG0__CFG_ARM_PBIST0_DLR,Datalogger Register" hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 [BRP]" bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1" bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1" bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode [mainly for ROM testing]" "0,1" newline bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1" bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1" bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1" bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1" newline bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1" bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1" bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1" bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1" line.long 0x38 "__VBUSP_CFG0__CFG_ARM_PBIST0_CMS,Clock-Mux Select Register" hexmask.long.byte 0x38 0.--3. 1. "CMS,Clock Mux Select [CMS]" line.long 0x3C "__VBUSP_CFG0__CFG_ARM_PBIST0_STR,Program Control Register" bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1" bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1" bitfld.long 0x3C 2. "STOP,Stop" "0,1" bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1" newline bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1" rgroup.quad 0x170++0x7 line.quad 0x0 "__VBUSP_CFG0__CFG_ARM_PBIST0_SCR,Address Scrambling Register" hexmask.quad.byte 0x0 56.--63. 1. "SCR7,Address Scrambling Register 7" hexmask.quad.byte 0x0 48.--55. 1. "SCR6,Address Scrambling Register 6" hexmask.quad.byte 0x0 40.--47. 1. "SCR5,Address Scrambling Register 5" hexmask.quad.byte 0x0 32.--39. 1. "SCR4,Address Scrambling Register 4" newline hexmask.quad.byte 0x0 24.--31. 1. "SCR3,Address Scrambling Register 3" hexmask.quad.byte 0x0 16.--23. 1. "SCR2,Address Scrambling Register 2" hexmask.quad.byte 0x0 8.--15. 1. "SCR1,Address Scrambling Register 1" hexmask.quad.byte 0x0 0.--7. 1. "SCR0,Address Scrambling Register 0" rgroup.long 0x178++0x13 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_PBIST0_CSR,Chip Select Register" hexmask.long.byte 0x0 24.--31. 1. "CSR3,Chip Select 3 [CSR3]" hexmask.long.byte 0x0 16.--23. 1. "CSR2,Chip Select 2 [CSR2]" hexmask.long.byte 0x0 8.--15. 1. "CSR1,Chip Select 1[CSR1]" hexmask.long.byte 0x0 0.--7. 1. "CSR0,Chip Select 0 [CSR0]" line.long 0x4 "__VBUSP_CFG0__CFG_ARM_PBIST0_FDLY,Fail Delay Register" hexmask.long.byte 0x4 0.--7. 1. "FDLY,Fail Delay [FDLY]" line.long 0x8 "__VBUSP_CFG0__CFG_ARM_PBIST0_PACT,PACT Register" bitfld.long 0x8 0. "PACT,PBIST Activate [PACT]" "0,1" line.long 0xC "__VBUSP_CFG0__CFG_ARM_PBIST0_PID,PBIST_ID Register" hexmask.long.byte 0xC 0.--4. 1. "PID,PBIST ID" line.long 0x10 "__VBUSP_CFG0__CFG_ARM_PBIST0_OVER,Override Register" bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1" bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1" bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1" bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1" rgroup.quad 0x190++0x17 line.quad 0x0 "__VBUSP_CFG0__CFG_ARM_PBIST0_FSRF,Fail Status Fail Register" bitfld.quad 0x0 32. "FRSF1,Fail Status Fail - Port 1 [FSRF1]" "0,1" bitfld.quad 0x0 0. "FRSF0,Fail Status Fail - Port 0 [FSRF0]" "0,1" line.quad 0x8 "__VBUSP_CFG0__CFG_ARM_PBIST0_FSRC,Fail Status Count Register" hexmask.quad.byte 0x8 32.--35. 1. "FSRC1,Fail Status Count - Port 1 [FSRC1]" hexmask.quad.byte 0x8 0.--3. 1. "FSRC0,Fail Status Count - Port 0 [FSRC0]" line.quad 0x10 "__VBUSP_CFG0__CFG_ARM_PBIST0_FSRA,Fail Status Address Register" hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 [FSRA1]" hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 [FSRA0]" rgroup.long 0x1A8++0x3 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_PBIST0_FSRDL0,Fail Status Data Registers" hexmask.long 0x0 0.--31. 1. "FSRDL0,Fail Status Data - Port 0 [FSRDL0]" rgroup.long 0x1B0++0xF line.long 0x0 "__VBUSP_CFG0__CFG_ARM_PBIST0_FSRDL1,Fail Status Data Registers" hexmask.long 0x0 0.--31. 1. "FSRDL1,Fail Status Data - Port 1 [FSRDL1]" line.long 0x4 "__VBUSP_CFG0__CFG_ARM_PBIST0_MARGIN_MODE,Fail Status Fail Register" bitfld.long 0x4 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3" bitfld.long 0x4 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3" line.long 0x8 "__VBUSP_CFG0__CFG_ARM_PBIST0_WRENZ,Fail Status Fail Register" bitfld.long 0x8 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3" line.long 0xC "__VBUSP_CFG0__CFG_ARM_PBIST0_PAGE_PGS,Fail Status Fail Register" bitfld.long 0xC 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3" rgroup.long 0x1C0++0x7 line.long 0x0 "__VBUSP_CFG0__CFG_ARM_PBIST0_ROM,ROM Mask Register" bitfld.long 0x0 0.--1. "ROM,ROM Mask [ROM]" "0,1,2,3" line.long 0x4 "__VBUSP_CFG0__CFG_ARM_PBIST0_ALGO,Algorithm Mask Register" hexmask.long.byte 0x4 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 [ALGO 3]" hexmask.long.byte 0x4 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 [ALGO 2]" hexmask.long.byte 0x4 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 [ALGO 1]" hexmask.long.byte 0x4 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 [ALGO 0]" rgroup.quad 0x1C8++0x7 line.quad 0x0 "__VBUSP_CFG0__CFG_ARM_PBIST0_RINFO,RAM Info Mask Register" hexmask.quad.byte 0x0 56.--63. 1. "U3,RAM Info Mask Upper 3 [RINFOU3]" hexmask.quad.byte 0x0 48.--55. 1. "U2,RAM Info Mask Upper 2 [RINFOU2]" hexmask.quad.byte 0x0 40.--47. 1. "U1,RAM Info Mask Upper 1 [RINFOU1]" hexmask.quad.byte 0x0 32.--39. 1. "U0,RAM Info Mask Upper 0 [RINFOU0]" newline hexmask.quad.byte 0x0 24.--31. 1. "L3,RAM Info Mask Lower 3 [RINFOL3]" hexmask.quad.byte 0x0 16.--23. 1. "L2,RAM Info Mask Lower 2 [RINFOL2]" hexmask.quad.byte 0x0 8.--15. 1. "L1,RAM Info Mask Lower 1 [RINFOL1]" hexmask.quad.byte 0x0 0.--7. 1. "L0,RAM Info Mask Lower 0 [RINFOL0]" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_CFG_WRAP_0_DSP0_PBIST (COMPUTE_CLUSTER0_CFG_WRAP_0_DSP0_PBIST)" base ad:0x4D10050000 rgroup.long 0x100++0x27 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_A0,Variable Address Registers" hexmask.long.word 0x0 0.--15. 1. "A0,Variable Address Register 0 [A0]" line.long 0x4 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_A1,Variable Address Registers" hexmask.long.word 0x4 0.--15. 1. "A1,Variable Address Register 1 [A1]" line.long 0x8 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_A2,Variable Address Registers" hexmask.long.word 0x8 0.--15. 1. "A2,Variable Address Register 2 [A2]" line.long 0xC "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_A3,Variable Address Registers" hexmask.long.word 0xC 0.--15. 1. "A3,Variable Address Register 3 [A3]" line.long 0x10 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_L0,Variable Loop Count Registers" hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 [L0]" line.long 0x14 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_L1,Variable Loop Count Registers" hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 [L1]" line.long 0x18 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_L2,Variable Loop Count Registers" hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 [L2]" line.long 0x1C "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_L3,Variable Loop Count Registers" hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 [L3]" line.long 0x20 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_D,Data Registers" hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 [D1]" hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 [D0]" line.long 0x24 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_E,Data Registers" hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 [E1]" hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 [E0]" rgroup.long 0x130++0x3F line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_CA0,Constant Address Registers" hexmask.long.word 0x0 0.--15. 1. "CA0,Constant Address Register 0 [CA0]" line.long 0x4 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_CA1,Constant Address Registers" hexmask.long.word 0x4 0.--15. 1. "CA1,Constant Address Register 1 [CA1]" line.long 0x8 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_CA2,Constant Address Registers" hexmask.long.word 0x8 0.--15. 1. "CA2,Constant Address Register 2 [CA2]" line.long 0xC "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_CA3,Constant Address Registers" hexmask.long.word 0xC 0.--15. 1. "CA3,Constant Address Register 3 [CA3]" line.long 0x10 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_CL0,Constant Loop Count Registers" hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 [CL0]" line.long 0x14 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_CL1,Constant Loop Count Registers" hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 [CL1]" line.long 0x18 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_CL2,Constant Loop Count Registers" hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 [CL2]" line.long 0x1C "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_CL3,Constant Loop Count Registers" hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 [CL3]" line.long 0x20 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_I0,Constant Increment Registers" hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 [I0]" line.long 0x24 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_I1,Constant Increment Registers" hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 [I1]" line.long 0x28 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_I2,Constant Increment Registers" hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 [I2]" line.long 0x2C "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_I3,Constant Increment Registers" hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 [I3]" line.long 0x30 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_RAMT,RAM Configuration Register" hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS" hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS" hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR" hexmask.long.byte 0x30 2.--5. 1. "PLS,Pipeline Latency Select" newline bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3" line.long 0x34 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_DLR,Datalogger Register" hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 [BRP]" bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1" bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1" bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode [mainly for ROM testing]" "0,1" newline bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1" bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1" bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1" bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1" newline bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1" bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1" bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1" bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1" line.long 0x38 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_CMS,Clock-Mux Select Register" hexmask.long.byte 0x38 0.--3. 1. "CMS,Clock Mux Select [CMS]" line.long 0x3C "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_STR,Program Control Register" bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1" bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1" bitfld.long 0x3C 2. "STOP,Stop" "0,1" bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1" newline bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1" rgroup.quad 0x170++0x7 line.quad 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_SCR,Address Scrambling Register" hexmask.quad.byte 0x0 56.--63. 1. "SCR7,Address Scrambling Register 7" hexmask.quad.byte 0x0 48.--55. 1. "SCR6,Address Scrambling Register 6" hexmask.quad.byte 0x0 40.--47. 1. "SCR5,Address Scrambling Register 5" hexmask.quad.byte 0x0 32.--39. 1. "SCR4,Address Scrambling Register 4" newline hexmask.quad.byte 0x0 24.--31. 1. "SCR3,Address Scrambling Register 3" hexmask.quad.byte 0x0 16.--23. 1. "SCR2,Address Scrambling Register 2" hexmask.quad.byte 0x0 8.--15. 1. "SCR1,Address Scrambling Register 1" hexmask.quad.byte 0x0 0.--7. 1. "SCR0,Address Scrambling Register 0" rgroup.long 0x178++0x13 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_CSR,Chip Select Register" hexmask.long.byte 0x0 24.--31. 1. "CSR3,Chip Select 3 [CSR3]" hexmask.long.byte 0x0 16.--23. 1. "CSR2,Chip Select 2 [CSR2]" hexmask.long.byte 0x0 8.--15. 1. "CSR1,Chip Select 1[CSR1]" hexmask.long.byte 0x0 0.--7. 1. "CSR0,Chip Select 0 [CSR0]" line.long 0x4 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_FDLY,Fail Delay Register" hexmask.long.byte 0x4 0.--7. 1. "FDLY,Fail Delay [FDLY]" line.long 0x8 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_PACT,PACT Register" bitfld.long 0x8 0. "PACT,PBIST Activate [PACT]" "0,1" line.long 0xC "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_PID,PBIST_ID Register" hexmask.long.byte 0xC 0.--4. 1. "PID,PBIST ID" line.long 0x10 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_OVER,Override Register" bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1" bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1" bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1" bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1" rgroup.quad 0x190++0x17 line.quad 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_FSRF,Fail Status Fail Register" bitfld.quad 0x0 32. "FRSF1,Fail Status Fail - Port 1 [FSRF1]" "0,1" bitfld.quad 0x0 0. "FRSF0,Fail Status Fail - Port 0 [FSRF0]" "0,1" line.quad 0x8 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_FSRC,Fail Status Count Register" hexmask.quad.byte 0x8 32.--35. 1. "FSRC1,Fail Status Count - Port 1 [FSRC1]" hexmask.quad.byte 0x8 0.--3. 1. "FSRC0,Fail Status Count - Port 0 [FSRC0]" line.quad 0x10 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_FSRA,Fail Status Address Register" hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 [FSRA1]" hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 [FSRA0]" rgroup.long 0x1A8++0x3 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_FSRDL0,Fail Status Data Registers" hexmask.long 0x0 0.--31. 1. "FSRDL0,Fail Status Data - Port 0 [FSRDL0]" rgroup.long 0x1B0++0xF line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_FSRDL1,Fail Status Data Registers" hexmask.long 0x0 0.--31. 1. "FSRDL1,Fail Status Data - Port 1 [FSRDL1]" line.long 0x4 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_MARGIN_MODE,Fail Status Fail Register" bitfld.long 0x4 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3" bitfld.long 0x4 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3" line.long 0x8 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_WRENZ,Fail Status Fail Register" bitfld.long 0x8 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3" line.long 0xC "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_PAGE_PGS,Fail Status Fail Register" bitfld.long 0xC 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3" rgroup.long 0x1C0++0x7 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_ROM,ROM Mask Register" bitfld.long 0x0 0.--1. "ROM,ROM Mask [ROM]" "0,1,2,3" line.long 0x4 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_ALGO,Algorithm Mask Register" hexmask.long.byte 0x4 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 [ALGO 3]" hexmask.long.byte 0x4 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 [ALGO 2]" hexmask.long.byte 0x4 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 [ALGO 1]" hexmask.long.byte 0x4 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 [ALGO 0]" rgroup.quad 0x1C8++0x7 line.quad 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_PBIST4_RINFO,RAM Info Mask Register" hexmask.quad.byte 0x0 56.--63. 1. "U3,RAM Info Mask Upper 3 [RINFOU3]" hexmask.quad.byte 0x0 48.--55. 1. "U2,RAM Info Mask Upper 2 [RINFOU2]" hexmask.quad.byte 0x0 40.--47. 1. "U1,RAM Info Mask Upper 1 [RINFOU1]" hexmask.quad.byte 0x0 32.--39. 1. "U0,RAM Info Mask Upper 0 [RINFOU0]" newline hexmask.quad.byte 0x0 24.--31. 1. "L3,RAM Info Mask Lower 3 [RINFOL3]" hexmask.quad.byte 0x0 16.--23. 1. "L2,RAM Info Mask Lower 2 [RINFOL2]" hexmask.quad.byte 0x0 8.--15. 1. "L1,RAM Info Mask Lower 1 [RINFOL1]" hexmask.quad.byte 0x0 0.--7. 1. "L0,RAM Info Mask Lower 0 [RINFOL0]" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_CFG_WRAP_0_DSP1_PBIST (COMPUTE_CLUSTER0_CFG_WRAP_0_DSP1_PBIST)" base ad:0x4D10060000 rgroup.long 0x100++0x27 line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_A0,Variable Address Registers" hexmask.long.word 0x0 0.--15. 1. "A0,Variable Address Register 0 [A0]" line.long 0x4 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_A1,Variable Address Registers" hexmask.long.word 0x4 0.--15. 1. "A1,Variable Address Register 1 [A1]" line.long 0x8 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_A2,Variable Address Registers" hexmask.long.word 0x8 0.--15. 1. "A2,Variable Address Register 2 [A2]" line.long 0xC "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_A3,Variable Address Registers" hexmask.long.word 0xC 0.--15. 1. "A3,Variable Address Register 3 [A3]" line.long 0x10 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_L0,Variable Loop Count Registers" hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 [L0]" line.long 0x14 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_L1,Variable Loop Count Registers" hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 [L1]" line.long 0x18 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_L2,Variable Loop Count Registers" hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 [L2]" line.long 0x1C "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_L3,Variable Loop Count Registers" hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 [L3]" line.long 0x20 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_D,Data Registers" hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 [D1]" hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 [D0]" line.long 0x24 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_E,Data Registers" hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 [E1]" hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 [E0]" rgroup.long 0x130++0x3F line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_CA0,Constant Address Registers" hexmask.long.word 0x0 0.--15. 1. "CA0,Constant Address Register 0 [CA0]" line.long 0x4 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_CA1,Constant Address Registers" hexmask.long.word 0x4 0.--15. 1. "CA1,Constant Address Register 1 [CA1]" line.long 0x8 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_CA2,Constant Address Registers" hexmask.long.word 0x8 0.--15. 1. "CA2,Constant Address Register 2 [CA2]" line.long 0xC "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_CA3,Constant Address Registers" hexmask.long.word 0xC 0.--15. 1. "CA3,Constant Address Register 3 [CA3]" line.long 0x10 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_CL0,Constant Loop Count Registers" hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 [CL0]" line.long 0x14 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_CL1,Constant Loop Count Registers" hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 [CL1]" line.long 0x18 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_CL2,Constant Loop Count Registers" hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 [CL2]" line.long 0x1C "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_CL3,Constant Loop Count Registers" hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 [CL3]" line.long 0x20 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_I0,Constant Increment Registers" hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 [I0]" line.long 0x24 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_I1,Constant Increment Registers" hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 [I1]" line.long 0x28 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_I2,Constant Increment Registers" hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 [I2]" line.long 0x2C "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_I3,Constant Increment Registers" hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 [I3]" line.long 0x30 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_RAMT,RAM Configuration Register" hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS" hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS" hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR" hexmask.long.byte 0x30 2.--5. 1. "PLS,Pipeline Latency Select" newline bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3" line.long 0x34 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_DLR,Datalogger Register" hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 [BRP]" bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1" bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1" bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode [mainly for ROM testing]" "0,1" newline bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1" bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1" bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1" bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1" newline bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1" bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1" bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1" bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1" line.long 0x38 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_CMS,Clock-Mux Select Register" hexmask.long.byte 0x38 0.--3. 1. "CMS,Clock Mux Select [CMS]" line.long 0x3C "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_STR,Program Control Register" bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1" bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1" bitfld.long 0x3C 2. "STOP,Stop" "0,1" bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1" newline bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1" rgroup.quad 0x170++0xF line.quad 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_SCR,Address Scrambling Register" hexmask.quad.byte 0x0 56.--63. 1. "SCR7,Address Scrambling Register 7" hexmask.quad.byte 0x0 48.--55. 1. "SCR6,Address Scrambling Register 6" hexmask.quad.byte 0x0 40.--47. 1. "SCR5,Address Scrambling Register 5" hexmask.quad.byte 0x0 32.--39. 1. "SCR4,Address Scrambling Register 4" newline hexmask.quad.byte 0x0 24.--31. 1. "SCR3,Address Scrambling Register 3" hexmask.quad.byte 0x0 16.--23. 1. "SCR2,Address Scrambling Register 2" hexmask.quad.byte 0x0 8.--15. 1. "SCR1,Address Scrambling Register 1" hexmask.quad.byte 0x0 0.--7. 1. "SCR0,Address Scrambling Register 0" line.quad 0x8 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_CSR,Chip Select Register" hexmask.quad.byte 0x8 24.--31. 1. "CSR3,Chip Select 3 [CSR3]" hexmask.quad.byte 0x8 16.--23. 1. "CSR2,Chip Select 2 [CSR2]" hexmask.quad.byte 0x8 8.--15. 1. "CSR1,Chip Select 1[CSR1]" hexmask.quad.byte 0x8 0.--7. 1. "CSR0,Chip Select 0 [CSR0]" rgroup.long 0x17C++0xF line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_FDLY,Fail Delay Register" hexmask.long.byte 0x0 0.--7. 1. "FDLY,Fail Delay [FDLY]" line.long 0x4 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_PACT,PACT Register" bitfld.long 0x4 0. "PACT,PBIST Activate [PACT]" "0,1" line.long 0x8 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_PID,PBIST_ID Register" hexmask.long.byte 0x8 0.--4. 1. "PID,PBIST ID" line.long 0xC "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_OVER,Override Register" bitfld.long 0xC 3. "ALGO,PBIST Override Algorithm Override" "0,1" bitfld.long 0xC 2. "MM,PBIST Override Multiple Memory" "0,1" bitfld.long 0xC 1. "READ,PBIST Override READ Override" "0,1" bitfld.long 0xC 0. "RINFO,PBIST Override RINFO Override" "0,1" rgroup.quad 0x190++0x17 line.quad 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_FSRF,Fail Status Fail Register" bitfld.quad 0x0 32. "FRSF1,Fail Status Fail - Port 1 [FSRF1]" "0,1" bitfld.quad 0x0 0. "FRSF0,Fail Status Fail - Port 0 [FSRF0]" "0,1" line.quad 0x8 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_FSRC,Fail Status Count Register" hexmask.quad.byte 0x8 32.--35. 1. "FSRC1,Fail Status Count - Port 1 [FSRC1]" hexmask.quad.byte 0x8 0.--3. 1. "FSRC0,Fail Status Count - Port 0 [FSRC0]" line.quad 0x10 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_FSRA,Fail Status Address Register" hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 [FSRA1]" hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 [FSRA0]" rgroup.long 0x1A8++0x3 line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_FSRDL0,Fail Status Data Registers" hexmask.long 0x0 0.--31. 1. "FSRDL0,Fail Status Data - Port 0 [FSRDL0]" rgroup.long 0x1B0++0xF line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_FSRDL1,Fail Status Data Registers" hexmask.long 0x0 0.--31. 1. "FSRDL1,Fail Status Data - Port 1 [FSRDL1]" line.long 0x4 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_MARGIN_MODE,Fail Status Fail Register" bitfld.long 0x4 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3" bitfld.long 0x4 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3" line.long 0x8 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_WRENZ,Fail Status Fail Register" bitfld.long 0x8 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3" line.long 0xC "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_PAGE_PGS,Fail Status Fail Register" bitfld.long 0xC 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3" rgroup.long 0x1C0++0x7 line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_ROM,ROM Mask Register" bitfld.long 0x0 0.--1. "ROM,ROM Mask [ROM]" "0,1,2,3" line.long 0x4 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_ALGO,Algorithm Mask Register" hexmask.long.byte 0x4 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 [ALGO 3]" hexmask.long.byte 0x4 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 [ALGO 2]" hexmask.long.byte 0x4 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 [ALGO 1]" hexmask.long.byte 0x4 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 [ALGO 0]" rgroup.quad 0x1C8++0x7 line.quad 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_PBIST5_RINFO,RAM Info Mask Register" hexmask.quad.byte 0x0 56.--63. 1. "U3,RAM Info Mask Upper 3 [RINFOU3]" hexmask.quad.byte 0x0 48.--55. 1. "U2,RAM Info Mask Upper 2 [RINFOU2]" hexmask.quad.byte 0x0 40.--47. 1. "U1,RAM Info Mask Upper 1 [RINFOU1]" hexmask.quad.byte 0x0 32.--39. 1. "U0,RAM Info Mask Upper 0 [RINFOU0]" newline hexmask.quad.byte 0x0 24.--31. 1. "L3,RAM Info Mask Lower 3 [RINFOL3]" hexmask.quad.byte 0x0 16.--23. 1. "L2,RAM Info Mask Lower 2 [RINFOL2]" hexmask.quad.byte 0x0 8.--15. 1. "L1,RAM Info Mask Lower 1 [RINFOL1]" hexmask.quad.byte 0x0 0.--7. 1. "L0,RAM Info Mask Lower 0 [RINFOL0]" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_CFG_WRAP_0_MSMC_ECC_AGGR0 (COMPUTE_CLUSTER0_CFG_WRAP_0_MSMC_ECC_AGGR0)" base ad:0x4D20000000 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x13 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "CPU5_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu5_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 30. "CPU5_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu5_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 29. "CPU4_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu4_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 28. "CPU4_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu4_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 27. "CPU0_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 26. "CPU0_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 25. "EMIF0_MST_PIPE_BUSECC_PEND,Interrupt Pending Status for emif0_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 24. "EMIF0_SLV_PIPE_BUSECC_PEND,Interrupt Pending Status for emif0_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 23. "DRU1_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru1_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 22. "DRU0_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 21. "DRU1_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru1_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 20. "DRU0_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 19. "POSTARB_PIPE_CFG_BUSECC_PEND,Interrupt Pending Status for postarb_pipe_cfg_busecc_pend" "0,1" newline bitfld.long 0x4 18. "MSMC_MMR_BUSECC_PEND,Interrupt Pending Status for msmc_mmr_busecc_pend" "0,1" newline bitfld.long 0x4 17. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_dru0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 16. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 15. "DRU0_RD_BUF_EDC_PEND,Interrupt Pending Status for dru0_rd_buf_edc_pend" "0,1" newline bitfld.long 0x4 14. "DRU0_QUEUE_EDC_PEND,Interrupt Pending Status for dru0_queue_edc_pend" "0,1" newline bitfld.long 0x4 13. "DRU0_ENG_EDC_PEND,Interrupt Pending Status for dru0_eng_edc_pend" "0,1" newline bitfld.long 0x4 12. "DRU0_1_EDC_PEND,Interrupt Pending Status for dru0_1_edc_pend" "0,1" newline bitfld.long 0x4 11. "DRU0_0_EDC_PEND,Interrupt Pending Status for dru0_0_edc_pend" "0,1" newline bitfld.long 0x4 10. "DRU0_PSI_EDC_PEND,Interrupt Pending Status for dru0_psi_edc_pend" "0,1" newline bitfld.long 0x4 9. "DRU0_MMR_FW_EDC_CTL_PEND,Interrupt Pending Status for dru0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0x4 8. "DRU0_CBASS_SCR_EDC_PEND,Interrupt Pending Status for dru0_cbass_scr_edc_pend" "0,1" newline bitfld.long 0x4 7. "DRU0_CBASS_MMR_FW_CH_EDC_PEND,Interrupt Pending Status for dru0_cbass_mmr_fw_ch_edc_pend" "0,1" newline bitfld.long 0x4 6. "DRU0_CBASS_MMR_FW_CH_BR_EDC_PEND,Interrupt Pending Status for dru0_cbass_mmr_fw_ch_br_edc_pend" "0,1" newline bitfld.long 0x4 5. "DRU0_CBASS_MMR_EDC_PEND,Interrupt Pending Status for dru0_cbass_mmr_edc_pend" "0,1" newline bitfld.long 0x4 4. "DRU0_CBASS_MMR_CFG_EDC_PEND,Interrupt Pending Status for dru0_cbass_mmr_cfg_edc_pend" "0,1" newline bitfld.long 0x4 3. "DRU0_CBASS_MMR_BRDG_EDC_PEND,Interrupt Pending Status for dru0_cbass_mmr_brdg_edc_pend" "0,1" newline bitfld.long 0x4 2. "DRU0_CBASS_EDC_CTRL_PEND,Interrupt Pending Status for dru0_cbass_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 1. "DRU0_CBASS_DMSC_SLV_BRDG_EDC_PEND,Interrupt Pending Status for dru0_cbass_dmsc_slv_brdg_edc_pend" "0,1" newline bitfld.long 0x4 0. "DRU0_CBASS_DMSC_SCR_EDC_PEND,Interrupt Pending Status for dru0_cbass_dmsc_scr_edc_pend" "0,1" line.long 0x8 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 31. "SRAM2_BUSECC_PEND,Interrupt Pending Status for sram2_busecc_pend" "0,1" newline bitfld.long 0x8 30. "RMW2_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw2_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 29. "RMW2_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw2_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x8 28. "RMW2_QUEUE_BUSECC_2_PEND,Interrupt Pending Status for rmw2_queue_busecc_2_pend" "0,1" newline bitfld.long 0x8 27. "RMW2_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw2_queue_busecc_1_pend" "0,1" newline bitfld.long 0x8 26. "RMW2_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw2_queue_busecc_0_pend" "0,1" newline bitfld.long 0x8 25. "RMW2_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw2_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 24. "RMW2_BUSECC_PEND,Interrupt Pending Status for rmw2_busecc_pend" "0,1" newline bitfld.long 0x8 23. "DATARAM_BANK1_BUSECC_PEND,Interrupt Pending Status for dataram_bank1_busecc_pend" "0,1" newline bitfld.long 0x8 22. "SRAM1_BUSECC_PEND,Interrupt Pending Status for sram1_busecc_pend" "0,1" newline bitfld.long 0x8 21. "RMW1_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw1_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 20. "RMW1_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw1_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x8 19. "RMW1_QUEUE_BUSECC_2_PEND,Interrupt Pending Status for rmw1_queue_busecc_2_pend" "0,1" newline bitfld.long 0x8 18. "RMW1_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw1_queue_busecc_1_pend" "0,1" newline bitfld.long 0x8 17. "RMW1_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw1_queue_busecc_0_pend" "0,1" newline bitfld.long 0x8 16. "RMW1_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw1_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 15. "RMW1_BUSECC_PEND,Interrupt Pending Status for rmw1_busecc_pend" "0,1" newline bitfld.long 0x8 14. "DATARAM_BANK0_BUSECC_PEND,Interrupt Pending Status for dataram_bank0_busecc_pend" "0,1" newline bitfld.long 0x8 13. "SRAM0_BUSECC_PEND,Interrupt Pending Status for sram0_busecc_pend" "0,1" newline bitfld.long 0x8 12. "RMW0_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw0_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 11. "RMW0_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw0_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x8 10. "RMW0_QUEUE_BUSECC_2_PEND,Interrupt Pending Status for rmw0_queue_busecc_2_pend" "0,1" newline bitfld.long 0x8 9. "RMW0_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw0_queue_busecc_1_pend" "0,1" newline bitfld.long 0x8 8. "RMW0_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw0_queue_busecc_0_pend" "0,1" newline bitfld.long 0x8 7. "RMW0_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw0_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 6. "RMW0_BUSECC_PEND,Interrupt Pending Status for rmw0_busecc_pend" "0,1" newline bitfld.long 0x8 5. "EN_MSMC_P0_BUSECC_0_PEND,Interrupt Pending Status for en_msmc_p0_busecc_0_pend" "0,1" newline bitfld.long 0x8 4. "EN_MSMC_P0_BUSECC_DATA_PEND,Interrupt Pending Status for en_msmc_p0_busecc_data_pend" "0,1" newline bitfld.long 0x8 3. "CPU9_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu9_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x8 2. "CPU9_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu9_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x8 1. "CPU8_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu8_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x8 0. "CPU8_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu8_slv_local_arb_busecc_pend" "0,1" line.long 0xC "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_status_reg2,Interrupt Status Register 2" bitfld.long 0xC 31. "EN_MSMC_P0_BUSECC_1_PEND,Interrupt Pending Status for en_msmc_p0_busecc_1_pend" "0,1" newline bitfld.long 0xC 30. "EN_MSMC_P0_BUSECC_WRITE_RESP_PEND,Interrupt Pending Status for en_msmc_p0_busecc_write_resp_pend" "0,1" newline bitfld.long 0xC 29. "EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE_PEND,Interrupt Pending Status for en_msmc_p0_busecc_wr_barrier_queue_pend" "0,1" newline bitfld.long 0xC 28. "EN_MSMC_P0_BUSECC_WACK_CID_QUEUE_PEND,Interrupt Pending Status for en_msmc_p0_busecc_wack_cid_queue_pend" "0,1" newline bitfld.long 0xC 27. "EN_MSMC_P0_BUSECC_SNP_RESP_BUF_PEND,Interrupt Pending Status for en_msmc_p0_busecc_snp_resp_buf_pend" "0,1" newline bitfld.long 0xC 26. "EN_MSMC_P0_BUSECC_SNP_DATA_BUF_PEND,Interrupt Pending Status for en_msmc_p0_busecc_snp_data_buf_pend" "0,1" newline bitfld.long 0xC 25. "EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE_PEND,Interrupt Pending Status for en_msmc_p0_busecc_snoop_cmd_id_queue_pend" "0,1" newline bitfld.long 0xC 24. "EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE_PEND,Interrupt Pending Status for en_msmc_p0_busecc_rd_barrier_queue_pend" "0,1" newline bitfld.long 0xC 23. "EN_MSMC_P0_BUSECC_RACK_CID_QUEUE_PEND,Interrupt Pending Status for en_msmc_p0_busecc_rack_cid_queue_pend" "0,1" newline bitfld.long 0xC 22. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0xC 21. "EN_MSMC_P0_MMR_FW_EDC_CTL_PEND,Interrupt Pending Status for en_msmc_p0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0xC 20. "CLEC_J7AE_CLEC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for clec_j7ae_clec_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 19. "EMIF_1_VSAFE_SI_PEND,Interrupt Pending Status for emif_1_vsafe_si_pend" "0,1" newline bitfld.long 0xC 18. "EMIF_0_VSAFE_SI_PEND,Interrupt Pending Status for emif_0_vsafe_si_pend" "0,1" newline bitfld.long 0xC 17. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac5_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0xC 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 15. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac4_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0xC 14. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 13. "EMIF1_MST_PIPE_BUSECC_PEND,Interrupt Pending Status for emif1_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0xC 12. "EMIF1_SLV_PIPE_BUSECC_PEND,Interrupt Pending Status for emif1_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0xC 11. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 10. "CLEC_SRAM_RAMECC_PEND,Interrupt Pending Status for clec_sram_ramecc_pend" "0,1" newline bitfld.long 0xC 9. "DATARAM_BANK3_BUSECC_PEND,Interrupt Pending Status for dataram_bank3_busecc_pend" "0,1" newline bitfld.long 0xC 8. "SRAM3_BUSECC_PEND,Interrupt Pending Status for sram3_busecc_pend" "0,1" newline bitfld.long 0xC 7. "RMW3_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw3_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0xC 6. "RMW3_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw3_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0xC 5. "RMW3_QUEUE_BUSECC_2_PEND,Interrupt Pending Status for rmw3_queue_busecc_2_pend" "0,1" newline bitfld.long 0xC 4. "RMW3_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw3_queue_busecc_1_pend" "0,1" newline bitfld.long 0xC 3. "RMW3_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw3_queue_busecc_0_pend" "0,1" newline bitfld.long 0xC 2. "RMW3_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw3_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0xC 1. "RMW3_BUSECC_PEND,Interrupt Pending Status for rmw3_busecc_pend" "0,1" newline bitfld.long 0xC 0. "DATARAM_BANK2_BUSECC_PEND,Interrupt Pending Status for dataram_bank2_busecc_pend" "0,1" line.long 0x10 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_status_reg3,Interrupt Status Register 3" bitfld.long 0x10 1. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x10 0. "EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_PEND,Interrupt Pending Status for en_msmc_p0_busecc_msmc_cmd_buffer_pend" "0,1" rgroup.long 0x80++0xF line.long 0x0 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "CPU5_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu5_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 30. "CPU5_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu5_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU4_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu4_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 28. "CPU4_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu4_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 26. "CPU0_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 25. "EMIF0_MST_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for emif0_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0x0 24. "EMIF0_SLV_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for emif0_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0x0 23. "DRU1_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru1_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 22. "DRU0_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 21. "DRU1_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru1_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 20. "DRU0_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 19. "POSTARB_PIPE_CFG_BUSECC_ENABLE_SET,Interrupt Enable Set Register for postarb_pipe_cfg_busecc_pend" "0,1" newline bitfld.long 0x0 18. "MSMC_MMR_BUSECC_ENABLE_SET,Interrupt Enable Set Register for msmc_mmr_busecc_pend" "0,1" newline bitfld.long 0x0 17. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_dru0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 16. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 15. "DRU0_RD_BUF_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_rd_buf_edc_pend" "0,1" newline bitfld.long 0x0 14. "DRU0_QUEUE_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_queue_edc_pend" "0,1" newline bitfld.long 0x0 13. "DRU0_ENG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_eng_edc_pend" "0,1" newline bitfld.long 0x0 12. "DRU0_1_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_1_edc_pend" "0,1" newline bitfld.long 0x0 11. "DRU0_0_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_0_edc_pend" "0,1" newline bitfld.long 0x0 10. "DRU0_PSI_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_psi_edc_pend" "0,1" newline bitfld.long 0x0 9. "DRU0_MMR_FW_EDC_CTL_ENABLE_SET,Interrupt Enable Set Register for dru0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0x0 8. "DRU0_CBASS_SCR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_scr_edc_pend" "0,1" newline bitfld.long 0x0 7. "DRU0_CBASS_MMR_FW_CH_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_mmr_fw_ch_edc_pend" "0,1" newline bitfld.long 0x0 6. "DRU0_CBASS_MMR_FW_CH_BR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_mmr_fw_ch_br_edc_pend" "0,1" newline bitfld.long 0x0 5. "DRU0_CBASS_MMR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_mmr_edc_pend" "0,1" newline bitfld.long 0x0 4. "DRU0_CBASS_MMR_CFG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_mmr_cfg_edc_pend" "0,1" newline bitfld.long 0x0 3. "DRU0_CBASS_MMR_BRDG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_mmr_brdg_edc_pend" "0,1" newline bitfld.long 0x0 2. "DRU0_CBASS_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 1. "DRU0_CBASS_DMSC_SLV_BRDG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_dmsc_slv_brdg_edc_pend" "0,1" newline bitfld.long 0x0 0. "DRU0_CBASS_DMSC_SCR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_dmsc_scr_edc_pend" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 31. "SRAM2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram2_busecc_pend" "0,1" newline bitfld.long 0x4 30. "RMW2_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 29. "RMW2_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 28. "RMW2_QUEUE_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for rmw2_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 27. "RMW2_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw2_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 26. "RMW2_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw2_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 25. "RMW2_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 24. "RMW2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_busecc_pend" "0,1" newline bitfld.long 0x4 23. "DATARAM_BANK1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank1_busecc_pend" "0,1" newline bitfld.long 0x4 22. "SRAM1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram1_busecc_pend" "0,1" newline bitfld.long 0x4 21. "RMW1_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 20. "RMW1_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 19. "RMW1_QUEUE_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for rmw1_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 18. "RMW1_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw1_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 17. "RMW1_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw1_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 16. "RMW1_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 15. "RMW1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_busecc_pend" "0,1" newline bitfld.long 0x4 14. "DATARAM_BANK0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank0_busecc_pend" "0,1" newline bitfld.long 0x4 13. "SRAM0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram0_busecc_pend" "0,1" newline bitfld.long 0x4 12. "RMW0_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 11. "RMW0_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 10. "RMW0_QUEUE_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for rmw0_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 9. "RMW0_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw0_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 8. "RMW0_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw0_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 7. "RMW0_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 6. "RMW0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_busecc_pend" "0,1" newline bitfld.long 0x4 5. "EN_MSMC_P0_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_0_pend" "0,1" newline bitfld.long 0x4 4. "EN_MSMC_P0_BUSECC_DATA_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_data_pend" "0,1" newline bitfld.long 0x4 3. "CPU9_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu9_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 2. "CPU9_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu9_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 1. "CPU8_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu8_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 0. "CPU8_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu8_slv_local_arb_busecc_pend" "0,1" line.long 0x8 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_enable_set_reg2,Interrupt Enable Set Register 2" bitfld.long 0x8 31. "EN_MSMC_P0_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_1_pend" "0,1" newline bitfld.long 0x8 30. "EN_MSMC_P0_BUSECC_WRITE_RESP_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_write_resp_pend" "0,1" newline bitfld.long 0x8 29. "EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_wr_barrier_queue_pend" "0,1" newline bitfld.long 0x8 28. "EN_MSMC_P0_BUSECC_WACK_CID_QUEUE_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_wack_cid_queue_pend" "0,1" newline bitfld.long 0x8 27. "EN_MSMC_P0_BUSECC_SNP_RESP_BUF_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_snp_resp_buf_pend" "0,1" newline bitfld.long 0x8 26. "EN_MSMC_P0_BUSECC_SNP_DATA_BUF_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_snp_data_buf_pend" "0,1" newline bitfld.long 0x8 25. "EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_snoop_cmd_id_queue_pend" "0,1" newline bitfld.long 0x8 24. "EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_rd_barrier_queue_pend" "0,1" newline bitfld.long 0x8 23. "EN_MSMC_P0_BUSECC_RACK_CID_QUEUE_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_rack_cid_queue_pend" "0,1" newline bitfld.long 0x8 22. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 21. "EN_MSMC_P0_MMR_FW_EDC_CTL_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0x8 20. "CLEC_J7AE_CLEC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for clec_j7ae_clec_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "EMIF_1_VSAFE_SI_ENABLE_SET,Interrupt Enable Set Register for emif_1_vsafe_si_pend" "0,1" newline bitfld.long 0x8 18. "EMIF_0_VSAFE_SI_ENABLE_SET,Interrupt Enable Set Register for emif_0_vsafe_si_pend" "0,1" newline bitfld.long 0x8 17. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac5_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 15. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac4_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 14. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 13. "EMIF1_MST_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for emif1_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 12. "EMIF1_SLV_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for emif1_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 11. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 10. "CLEC_SRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clec_sram_ramecc_pend" "0,1" newline bitfld.long 0x8 9. "DATARAM_BANK3_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank3_busecc_pend" "0,1" newline bitfld.long 0x8 8. "SRAM3_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram3_busecc_pend" "0,1" newline bitfld.long 0x8 7. "RMW3_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 6. "RMW3_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x8 5. "RMW3_QUEUE_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for rmw3_queue_busecc_2_pend" "0,1" newline bitfld.long 0x8 4. "RMW3_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw3_queue_busecc_1_pend" "0,1" newline bitfld.long 0x8 3. "RMW3_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw3_queue_busecc_0_pend" "0,1" newline bitfld.long 0x8 2. "RMW3_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 1. "RMW3_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_busecc_pend" "0,1" newline bitfld.long 0x8 0. "DATARAM_BANK2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank2_busecc_pend" "0,1" line.long 0xC "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_enable_set_reg3,Interrupt Enable Set Register 3" bitfld.long 0xC 1. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0xC 0. "EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_msmc_cmd_buffer_pend" "0,1" rgroup.long 0xC0++0xF line.long 0x0 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "CPU5_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu5_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 30. "CPU5_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu5_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU4_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu4_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 28. "CPU4_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu4_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 26. "CPU0_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 25. "EMIF0_MST_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for emif0_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0x0 24. "EMIF0_SLV_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for emif0_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0x0 23. "DRU1_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru1_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 22. "DRU0_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 21. "DRU1_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru1_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 20. "DRU0_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 19. "POSTARB_PIPE_CFG_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for postarb_pipe_cfg_busecc_pend" "0,1" newline bitfld.long 0x0 18. "MSMC_MMR_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for msmc_mmr_busecc_pend" "0,1" newline bitfld.long 0x0 17. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_dru0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 16. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 15. "DRU0_RD_BUF_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_rd_buf_edc_pend" "0,1" newline bitfld.long 0x0 14. "DRU0_QUEUE_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_queue_edc_pend" "0,1" newline bitfld.long 0x0 13. "DRU0_ENG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_eng_edc_pend" "0,1" newline bitfld.long 0x0 12. "DRU0_1_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_1_edc_pend" "0,1" newline bitfld.long 0x0 11. "DRU0_0_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_0_edc_pend" "0,1" newline bitfld.long 0x0 10. "DRU0_PSI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_psi_edc_pend" "0,1" newline bitfld.long 0x0 9. "DRU0_MMR_FW_EDC_CTL_ENABLE_CLR,Interrupt Enable Clear Register for dru0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0x0 8. "DRU0_CBASS_SCR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_scr_edc_pend" "0,1" newline bitfld.long 0x0 7. "DRU0_CBASS_MMR_FW_CH_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_mmr_fw_ch_edc_pend" "0,1" newline bitfld.long 0x0 6. "DRU0_CBASS_MMR_FW_CH_BR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_mmr_fw_ch_br_edc_pend" "0,1" newline bitfld.long 0x0 5. "DRU0_CBASS_MMR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_mmr_edc_pend" "0,1" newline bitfld.long 0x0 4. "DRU0_CBASS_MMR_CFG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_mmr_cfg_edc_pend" "0,1" newline bitfld.long 0x0 3. "DRU0_CBASS_MMR_BRDG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_mmr_brdg_edc_pend" "0,1" newline bitfld.long 0x0 2. "DRU0_CBASS_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 1. "DRU0_CBASS_DMSC_SLV_BRDG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_dmsc_slv_brdg_edc_pend" "0,1" newline bitfld.long 0x0 0. "DRU0_CBASS_DMSC_SCR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_dmsc_scr_edc_pend" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 31. "SRAM2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram2_busecc_pend" "0,1" newline bitfld.long 0x4 30. "RMW2_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 29. "RMW2_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 28. "RMW2_QUEUE_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 27. "RMW2_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 26. "RMW2_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 25. "RMW2_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 24. "RMW2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_busecc_pend" "0,1" newline bitfld.long 0x4 23. "DATARAM_BANK1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank1_busecc_pend" "0,1" newline bitfld.long 0x4 22. "SRAM1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram1_busecc_pend" "0,1" newline bitfld.long 0x4 21. "RMW1_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 20. "RMW1_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 19. "RMW1_QUEUE_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 18. "RMW1_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 17. "RMW1_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 16. "RMW1_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 15. "RMW1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_busecc_pend" "0,1" newline bitfld.long 0x4 14. "DATARAM_BANK0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank0_busecc_pend" "0,1" newline bitfld.long 0x4 13. "SRAM0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram0_busecc_pend" "0,1" newline bitfld.long 0x4 12. "RMW0_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 11. "RMW0_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 10. "RMW0_QUEUE_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 9. "RMW0_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 8. "RMW0_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 7. "RMW0_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 6. "RMW0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_busecc_pend" "0,1" newline bitfld.long 0x4 5. "EN_MSMC_P0_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_0_pend" "0,1" newline bitfld.long 0x4 4. "EN_MSMC_P0_BUSECC_DATA_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_data_pend" "0,1" newline bitfld.long 0x4 3. "CPU9_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu9_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 2. "CPU9_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu9_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 1. "CPU8_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu8_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 0. "CPU8_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu8_slv_local_arb_busecc_pend" "0,1" line.long 0x8 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_enable_clr_reg2,Interrupt Enable Clear Register 2" bitfld.long 0x8 31. "EN_MSMC_P0_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_1_pend" "0,1" newline bitfld.long 0x8 30. "EN_MSMC_P0_BUSECC_WRITE_RESP_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_write_resp_pend" "0,1" newline bitfld.long 0x8 29. "EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_wr_barrier_queue_pend" "0,1" newline bitfld.long 0x8 28. "EN_MSMC_P0_BUSECC_WACK_CID_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_wack_cid_queue_pend" "0,1" newline bitfld.long 0x8 27. "EN_MSMC_P0_BUSECC_SNP_RESP_BUF_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_snp_resp_buf_pend" "0,1" newline bitfld.long 0x8 26. "EN_MSMC_P0_BUSECC_SNP_DATA_BUF_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_snp_data_buf_pend" "0,1" newline bitfld.long 0x8 25. "EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_snoop_cmd_id_queue_pend" "0,1" newline bitfld.long 0x8 24. "EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_rd_barrier_queue_pend" "0,1" newline bitfld.long 0x8 23. "EN_MSMC_P0_BUSECC_RACK_CID_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_rack_cid_queue_pend" "0,1" newline bitfld.long 0x8 22. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 21. "EN_MSMC_P0_MMR_FW_EDC_CTL_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0x8 20. "CLEC_J7AE_CLEC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for clec_j7ae_clec_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "EMIF_1_VSAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for emif_1_vsafe_si_pend" "0,1" newline bitfld.long 0x8 18. "EMIF_0_VSAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for emif_0_vsafe_si_pend" "0,1" newline bitfld.long 0x8 17. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac5_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 15. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac4_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 14. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 13. "EMIF1_MST_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for emif1_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 12. "EMIF1_SLV_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for emif1_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 11. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 10. "CLEC_SRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clec_sram_ramecc_pend" "0,1" newline bitfld.long 0x8 9. "DATARAM_BANK3_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank3_busecc_pend" "0,1" newline bitfld.long 0x8 8. "SRAM3_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram3_busecc_pend" "0,1" newline bitfld.long 0x8 7. "RMW3_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 6. "RMW3_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x8 5. "RMW3_QUEUE_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_queue_busecc_2_pend" "0,1" newline bitfld.long 0x8 4. "RMW3_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_queue_busecc_1_pend" "0,1" newline bitfld.long 0x8 3. "RMW3_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_queue_busecc_0_pend" "0,1" newline bitfld.long 0x8 2. "RMW3_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 1. "RMW3_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_busecc_pend" "0,1" newline bitfld.long 0x8 0. "DATARAM_BANK2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank2_busecc_pend" "0,1" line.long 0xC "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_enable_clr_reg3,Interrupt Enable Clear Register 3" bitfld.long 0xC 1. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0xC 0. "EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_msmc_cmd_buffer_pend" "0,1" rgroup.long 0x13C++0x13 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "CPU5_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu5_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 30. "CPU5_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu5_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 29. "CPU4_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu4_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 28. "CPU4_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu4_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 27. "CPU0_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 26. "CPU0_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 25. "EMIF0_MST_PIPE_BUSECC_PEND,Interrupt Pending Status for emif0_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 24. "EMIF0_SLV_PIPE_BUSECC_PEND,Interrupt Pending Status for emif0_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 23. "DRU1_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru1_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 22. "DRU0_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 21. "DRU1_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru1_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 20. "DRU0_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 19. "POSTARB_PIPE_CFG_BUSECC_PEND,Interrupt Pending Status for postarb_pipe_cfg_busecc_pend" "0,1" newline bitfld.long 0x4 18. "MSMC_MMR_BUSECC_PEND,Interrupt Pending Status for msmc_mmr_busecc_pend" "0,1" newline bitfld.long 0x4 17. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_dru0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 16. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 15. "DRU0_RD_BUF_EDC_PEND,Interrupt Pending Status for dru0_rd_buf_edc_pend" "0,1" newline bitfld.long 0x4 14. "DRU0_QUEUE_EDC_PEND,Interrupt Pending Status for dru0_queue_edc_pend" "0,1" newline bitfld.long 0x4 13. "DRU0_ENG_EDC_PEND,Interrupt Pending Status for dru0_eng_edc_pend" "0,1" newline bitfld.long 0x4 12. "DRU0_1_EDC_PEND,Interrupt Pending Status for dru0_1_edc_pend" "0,1" newline bitfld.long 0x4 11. "DRU0_0_EDC_PEND,Interrupt Pending Status for dru0_0_edc_pend" "0,1" newline bitfld.long 0x4 10. "DRU0_PSI_EDC_PEND,Interrupt Pending Status for dru0_psi_edc_pend" "0,1" newline bitfld.long 0x4 9. "DRU0_MMR_FW_EDC_CTL_PEND,Interrupt Pending Status for dru0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0x4 8. "DRU0_CBASS_SCR_EDC_PEND,Interrupt Pending Status for dru0_cbass_scr_edc_pend" "0,1" newline bitfld.long 0x4 7. "DRU0_CBASS_MMR_FW_CH_EDC_PEND,Interrupt Pending Status for dru0_cbass_mmr_fw_ch_edc_pend" "0,1" newline bitfld.long 0x4 6. "DRU0_CBASS_MMR_FW_CH_BR_EDC_PEND,Interrupt Pending Status for dru0_cbass_mmr_fw_ch_br_edc_pend" "0,1" newline bitfld.long 0x4 5. "DRU0_CBASS_MMR_EDC_PEND,Interrupt Pending Status for dru0_cbass_mmr_edc_pend" "0,1" newline bitfld.long 0x4 4. "DRU0_CBASS_MMR_CFG_EDC_PEND,Interrupt Pending Status for dru0_cbass_mmr_cfg_edc_pend" "0,1" newline bitfld.long 0x4 3. "DRU0_CBASS_MMR_BRDG_EDC_PEND,Interrupt Pending Status for dru0_cbass_mmr_brdg_edc_pend" "0,1" newline bitfld.long 0x4 2. "DRU0_CBASS_EDC_CTRL_PEND,Interrupt Pending Status for dru0_cbass_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 1. "DRU0_CBASS_DMSC_SLV_BRDG_EDC_PEND,Interrupt Pending Status for dru0_cbass_dmsc_slv_brdg_edc_pend" "0,1" newline bitfld.long 0x4 0. "DRU0_CBASS_DMSC_SCR_EDC_PEND,Interrupt Pending Status for dru0_cbass_dmsc_scr_edc_pend" "0,1" line.long 0x8 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 31. "SRAM2_BUSECC_PEND,Interrupt Pending Status for sram2_busecc_pend" "0,1" newline bitfld.long 0x8 30. "RMW2_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw2_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 29. "RMW2_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw2_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x8 28. "RMW2_QUEUE_BUSECC_2_PEND,Interrupt Pending Status for rmw2_queue_busecc_2_pend" "0,1" newline bitfld.long 0x8 27. "RMW2_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw2_queue_busecc_1_pend" "0,1" newline bitfld.long 0x8 26. "RMW2_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw2_queue_busecc_0_pend" "0,1" newline bitfld.long 0x8 25. "RMW2_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw2_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 24. "RMW2_BUSECC_PEND,Interrupt Pending Status for rmw2_busecc_pend" "0,1" newline bitfld.long 0x8 23. "DATARAM_BANK1_BUSECC_PEND,Interrupt Pending Status for dataram_bank1_busecc_pend" "0,1" newline bitfld.long 0x8 22. "SRAM1_BUSECC_PEND,Interrupt Pending Status for sram1_busecc_pend" "0,1" newline bitfld.long 0x8 21. "RMW1_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw1_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 20. "RMW1_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw1_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x8 19. "RMW1_QUEUE_BUSECC_2_PEND,Interrupt Pending Status for rmw1_queue_busecc_2_pend" "0,1" newline bitfld.long 0x8 18. "RMW1_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw1_queue_busecc_1_pend" "0,1" newline bitfld.long 0x8 17. "RMW1_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw1_queue_busecc_0_pend" "0,1" newline bitfld.long 0x8 16. "RMW1_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw1_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 15. "RMW1_BUSECC_PEND,Interrupt Pending Status for rmw1_busecc_pend" "0,1" newline bitfld.long 0x8 14. "DATARAM_BANK0_BUSECC_PEND,Interrupt Pending Status for dataram_bank0_busecc_pend" "0,1" newline bitfld.long 0x8 13. "SRAM0_BUSECC_PEND,Interrupt Pending Status for sram0_busecc_pend" "0,1" newline bitfld.long 0x8 12. "RMW0_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw0_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 11. "RMW0_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw0_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x8 10. "RMW0_QUEUE_BUSECC_2_PEND,Interrupt Pending Status for rmw0_queue_busecc_2_pend" "0,1" newline bitfld.long 0x8 9. "RMW0_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw0_queue_busecc_1_pend" "0,1" newline bitfld.long 0x8 8. "RMW0_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw0_queue_busecc_0_pend" "0,1" newline bitfld.long 0x8 7. "RMW0_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw0_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 6. "RMW0_BUSECC_PEND,Interrupt Pending Status for rmw0_busecc_pend" "0,1" newline bitfld.long 0x8 5. "EN_MSMC_P0_BUSECC_0_PEND,Interrupt Pending Status for en_msmc_p0_busecc_0_pend" "0,1" newline bitfld.long 0x8 4. "EN_MSMC_P0_BUSECC_DATA_PEND,Interrupt Pending Status for en_msmc_p0_busecc_data_pend" "0,1" newline bitfld.long 0x8 3. "CPU9_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu9_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x8 2. "CPU9_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu9_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x8 1. "CPU8_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu8_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x8 0. "CPU8_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu8_slv_local_arb_busecc_pend" "0,1" line.long 0xC "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_status_reg2,Interrupt Status Register 2" bitfld.long 0xC 31. "EN_MSMC_P0_BUSECC_1_PEND,Interrupt Pending Status for en_msmc_p0_busecc_1_pend" "0,1" newline bitfld.long 0xC 30. "EN_MSMC_P0_BUSECC_WRITE_RESP_PEND,Interrupt Pending Status for en_msmc_p0_busecc_write_resp_pend" "0,1" newline bitfld.long 0xC 29. "EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE_PEND,Interrupt Pending Status for en_msmc_p0_busecc_wr_barrier_queue_pend" "0,1" newline bitfld.long 0xC 28. "EN_MSMC_P0_BUSECC_WACK_CID_QUEUE_PEND,Interrupt Pending Status for en_msmc_p0_busecc_wack_cid_queue_pend" "0,1" newline bitfld.long 0xC 27. "EN_MSMC_P0_BUSECC_SNP_RESP_BUF_PEND,Interrupt Pending Status for en_msmc_p0_busecc_snp_resp_buf_pend" "0,1" newline bitfld.long 0xC 26. "EN_MSMC_P0_BUSECC_SNP_DATA_BUF_PEND,Interrupt Pending Status for en_msmc_p0_busecc_snp_data_buf_pend" "0,1" newline bitfld.long 0xC 25. "EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE_PEND,Interrupt Pending Status for en_msmc_p0_busecc_snoop_cmd_id_queue_pend" "0,1" newline bitfld.long 0xC 24. "EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE_PEND,Interrupt Pending Status for en_msmc_p0_busecc_rd_barrier_queue_pend" "0,1" newline bitfld.long 0xC 23. "EN_MSMC_P0_BUSECC_RACK_CID_QUEUE_PEND,Interrupt Pending Status for en_msmc_p0_busecc_rack_cid_queue_pend" "0,1" newline bitfld.long 0xC 22. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0xC 21. "EN_MSMC_P0_MMR_FW_EDC_CTL_PEND,Interrupt Pending Status for en_msmc_p0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0xC 20. "CLEC_J7AE_CLEC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for clec_j7ae_clec_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 19. "EMIF_1_VSAFE_SI_PEND,Interrupt Pending Status for emif_1_vsafe_si_pend" "0,1" newline bitfld.long 0xC 18. "EMIF_0_VSAFE_SI_PEND,Interrupt Pending Status for emif_0_vsafe_si_pend" "0,1" newline bitfld.long 0xC 17. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac5_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0xC 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 15. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac4_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0xC 14. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 13. "EMIF1_MST_PIPE_BUSECC_PEND,Interrupt Pending Status for emif1_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0xC 12. "EMIF1_SLV_PIPE_BUSECC_PEND,Interrupt Pending Status for emif1_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0xC 11. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 10. "CLEC_SRAM_RAMECC_PEND,Interrupt Pending Status for clec_sram_ramecc_pend" "0,1" newline bitfld.long 0xC 9. "DATARAM_BANK3_BUSECC_PEND,Interrupt Pending Status for dataram_bank3_busecc_pend" "0,1" newline bitfld.long 0xC 8. "SRAM3_BUSECC_PEND,Interrupt Pending Status for sram3_busecc_pend" "0,1" newline bitfld.long 0xC 7. "RMW3_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw3_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0xC 6. "RMW3_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw3_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0xC 5. "RMW3_QUEUE_BUSECC_2_PEND,Interrupt Pending Status for rmw3_queue_busecc_2_pend" "0,1" newline bitfld.long 0xC 4. "RMW3_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw3_queue_busecc_1_pend" "0,1" newline bitfld.long 0xC 3. "RMW3_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw3_queue_busecc_0_pend" "0,1" newline bitfld.long 0xC 2. "RMW3_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw3_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0xC 1. "RMW3_BUSECC_PEND,Interrupt Pending Status for rmw3_busecc_pend" "0,1" newline bitfld.long 0xC 0. "DATARAM_BANK2_BUSECC_PEND,Interrupt Pending Status for dataram_bank2_busecc_pend" "0,1" line.long 0x10 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_status_reg3,Interrupt Status Register 3" bitfld.long 0x10 1. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x10 0. "EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_PEND,Interrupt Pending Status for en_msmc_p0_busecc_msmc_cmd_buffer_pend" "0,1" rgroup.long 0x180++0xF line.long 0x0 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "CPU5_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu5_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 30. "CPU5_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu5_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU4_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu4_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 28. "CPU4_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu4_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 26. "CPU0_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 25. "EMIF0_MST_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for emif0_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0x0 24. "EMIF0_SLV_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for emif0_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0x0 23. "DRU1_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru1_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 22. "DRU0_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 21. "DRU1_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru1_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 20. "DRU0_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 19. "POSTARB_PIPE_CFG_BUSECC_ENABLE_SET,Interrupt Enable Set Register for postarb_pipe_cfg_busecc_pend" "0,1" newline bitfld.long 0x0 18. "MSMC_MMR_BUSECC_ENABLE_SET,Interrupt Enable Set Register for msmc_mmr_busecc_pend" "0,1" newline bitfld.long 0x0 17. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_dru0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 16. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 15. "DRU0_RD_BUF_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_rd_buf_edc_pend" "0,1" newline bitfld.long 0x0 14. "DRU0_QUEUE_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_queue_edc_pend" "0,1" newline bitfld.long 0x0 13. "DRU0_ENG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_eng_edc_pend" "0,1" newline bitfld.long 0x0 12. "DRU0_1_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_1_edc_pend" "0,1" newline bitfld.long 0x0 11. "DRU0_0_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_0_edc_pend" "0,1" newline bitfld.long 0x0 10. "DRU0_PSI_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_psi_edc_pend" "0,1" newline bitfld.long 0x0 9. "DRU0_MMR_FW_EDC_CTL_ENABLE_SET,Interrupt Enable Set Register for dru0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0x0 8. "DRU0_CBASS_SCR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_scr_edc_pend" "0,1" newline bitfld.long 0x0 7. "DRU0_CBASS_MMR_FW_CH_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_mmr_fw_ch_edc_pend" "0,1" newline bitfld.long 0x0 6. "DRU0_CBASS_MMR_FW_CH_BR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_mmr_fw_ch_br_edc_pend" "0,1" newline bitfld.long 0x0 5. "DRU0_CBASS_MMR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_mmr_edc_pend" "0,1" newline bitfld.long 0x0 4. "DRU0_CBASS_MMR_CFG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_mmr_cfg_edc_pend" "0,1" newline bitfld.long 0x0 3. "DRU0_CBASS_MMR_BRDG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_mmr_brdg_edc_pend" "0,1" newline bitfld.long 0x0 2. "DRU0_CBASS_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 1. "DRU0_CBASS_DMSC_SLV_BRDG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_dmsc_slv_brdg_edc_pend" "0,1" newline bitfld.long 0x0 0. "DRU0_CBASS_DMSC_SCR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_dmsc_scr_edc_pend" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 31. "SRAM2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram2_busecc_pend" "0,1" newline bitfld.long 0x4 30. "RMW2_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 29. "RMW2_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 28. "RMW2_QUEUE_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for rmw2_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 27. "RMW2_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw2_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 26. "RMW2_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw2_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 25. "RMW2_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 24. "RMW2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_busecc_pend" "0,1" newline bitfld.long 0x4 23. "DATARAM_BANK1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank1_busecc_pend" "0,1" newline bitfld.long 0x4 22. "SRAM1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram1_busecc_pend" "0,1" newline bitfld.long 0x4 21. "RMW1_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 20. "RMW1_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 19. "RMW1_QUEUE_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for rmw1_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 18. "RMW1_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw1_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 17. "RMW1_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw1_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 16. "RMW1_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 15. "RMW1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_busecc_pend" "0,1" newline bitfld.long 0x4 14. "DATARAM_BANK0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank0_busecc_pend" "0,1" newline bitfld.long 0x4 13. "SRAM0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram0_busecc_pend" "0,1" newline bitfld.long 0x4 12. "RMW0_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 11. "RMW0_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 10. "RMW0_QUEUE_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for rmw0_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 9. "RMW0_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw0_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 8. "RMW0_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw0_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 7. "RMW0_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 6. "RMW0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_busecc_pend" "0,1" newline bitfld.long 0x4 5. "EN_MSMC_P0_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_0_pend" "0,1" newline bitfld.long 0x4 4. "EN_MSMC_P0_BUSECC_DATA_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_data_pend" "0,1" newline bitfld.long 0x4 3. "CPU9_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu9_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 2. "CPU9_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu9_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 1. "CPU8_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu8_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 0. "CPU8_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu8_slv_local_arb_busecc_pend" "0,1" line.long 0x8 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_enable_set_reg2,Interrupt Enable Set Register 2" bitfld.long 0x8 31. "EN_MSMC_P0_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_1_pend" "0,1" newline bitfld.long 0x8 30. "EN_MSMC_P0_BUSECC_WRITE_RESP_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_write_resp_pend" "0,1" newline bitfld.long 0x8 29. "EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_wr_barrier_queue_pend" "0,1" newline bitfld.long 0x8 28. "EN_MSMC_P0_BUSECC_WACK_CID_QUEUE_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_wack_cid_queue_pend" "0,1" newline bitfld.long 0x8 27. "EN_MSMC_P0_BUSECC_SNP_RESP_BUF_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_snp_resp_buf_pend" "0,1" newline bitfld.long 0x8 26. "EN_MSMC_P0_BUSECC_SNP_DATA_BUF_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_snp_data_buf_pend" "0,1" newline bitfld.long 0x8 25. "EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_snoop_cmd_id_queue_pend" "0,1" newline bitfld.long 0x8 24. "EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_rd_barrier_queue_pend" "0,1" newline bitfld.long 0x8 23. "EN_MSMC_P0_BUSECC_RACK_CID_QUEUE_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_rack_cid_queue_pend" "0,1" newline bitfld.long 0x8 22. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 21. "EN_MSMC_P0_MMR_FW_EDC_CTL_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0x8 20. "CLEC_J7AE_CLEC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for clec_j7ae_clec_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "EMIF_1_VSAFE_SI_ENABLE_SET,Interrupt Enable Set Register for emif_1_vsafe_si_pend" "0,1" newline bitfld.long 0x8 18. "EMIF_0_VSAFE_SI_ENABLE_SET,Interrupt Enable Set Register for emif_0_vsafe_si_pend" "0,1" newline bitfld.long 0x8 17. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac5_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 15. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac4_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 14. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 13. "EMIF1_MST_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for emif1_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 12. "EMIF1_SLV_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for emif1_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 11. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 10. "CLEC_SRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clec_sram_ramecc_pend" "0,1" newline bitfld.long 0x8 9. "DATARAM_BANK3_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank3_busecc_pend" "0,1" newline bitfld.long 0x8 8. "SRAM3_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram3_busecc_pend" "0,1" newline bitfld.long 0x8 7. "RMW3_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 6. "RMW3_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x8 5. "RMW3_QUEUE_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for rmw3_queue_busecc_2_pend" "0,1" newline bitfld.long 0x8 4. "RMW3_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw3_queue_busecc_1_pend" "0,1" newline bitfld.long 0x8 3. "RMW3_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw3_queue_busecc_0_pend" "0,1" newline bitfld.long 0x8 2. "RMW3_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 1. "RMW3_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_busecc_pend" "0,1" newline bitfld.long 0x8 0. "DATARAM_BANK2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank2_busecc_pend" "0,1" line.long 0xC "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_enable_set_reg3,Interrupt Enable Set Register 3" bitfld.long 0xC 1. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0xC 0. "EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_msmc_cmd_buffer_pend" "0,1" rgroup.long 0x1C0++0xF line.long 0x0 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "CPU5_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu5_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 30. "CPU5_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu5_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU4_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu4_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 28. "CPU4_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu4_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 26. "CPU0_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 25. "EMIF0_MST_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for emif0_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0x0 24. "EMIF0_SLV_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for emif0_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0x0 23. "DRU1_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru1_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 22. "DRU0_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 21. "DRU1_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru1_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 20. "DRU0_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 19. "POSTARB_PIPE_CFG_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for postarb_pipe_cfg_busecc_pend" "0,1" newline bitfld.long 0x0 18. "MSMC_MMR_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for msmc_mmr_busecc_pend" "0,1" newline bitfld.long 0x0 17. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_dru0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 16. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 15. "DRU0_RD_BUF_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_rd_buf_edc_pend" "0,1" newline bitfld.long 0x0 14. "DRU0_QUEUE_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_queue_edc_pend" "0,1" newline bitfld.long 0x0 13. "DRU0_ENG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_eng_edc_pend" "0,1" newline bitfld.long 0x0 12. "DRU0_1_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_1_edc_pend" "0,1" newline bitfld.long 0x0 11. "DRU0_0_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_0_edc_pend" "0,1" newline bitfld.long 0x0 10. "DRU0_PSI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_psi_edc_pend" "0,1" newline bitfld.long 0x0 9. "DRU0_MMR_FW_EDC_CTL_ENABLE_CLR,Interrupt Enable Clear Register for dru0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0x0 8. "DRU0_CBASS_SCR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_scr_edc_pend" "0,1" newline bitfld.long 0x0 7. "DRU0_CBASS_MMR_FW_CH_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_mmr_fw_ch_edc_pend" "0,1" newline bitfld.long 0x0 6. "DRU0_CBASS_MMR_FW_CH_BR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_mmr_fw_ch_br_edc_pend" "0,1" newline bitfld.long 0x0 5. "DRU0_CBASS_MMR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_mmr_edc_pend" "0,1" newline bitfld.long 0x0 4. "DRU0_CBASS_MMR_CFG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_mmr_cfg_edc_pend" "0,1" newline bitfld.long 0x0 3. "DRU0_CBASS_MMR_BRDG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_mmr_brdg_edc_pend" "0,1" newline bitfld.long 0x0 2. "DRU0_CBASS_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 1. "DRU0_CBASS_DMSC_SLV_BRDG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_dmsc_slv_brdg_edc_pend" "0,1" newline bitfld.long 0x0 0. "DRU0_CBASS_DMSC_SCR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_dmsc_scr_edc_pend" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 31. "SRAM2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram2_busecc_pend" "0,1" newline bitfld.long 0x4 30. "RMW2_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 29. "RMW2_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 28. "RMW2_QUEUE_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 27. "RMW2_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 26. "RMW2_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 25. "RMW2_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 24. "RMW2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_busecc_pend" "0,1" newline bitfld.long 0x4 23. "DATARAM_BANK1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank1_busecc_pend" "0,1" newline bitfld.long 0x4 22. "SRAM1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram1_busecc_pend" "0,1" newline bitfld.long 0x4 21. "RMW1_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 20. "RMW1_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 19. "RMW1_QUEUE_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 18. "RMW1_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 17. "RMW1_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 16. "RMW1_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 15. "RMW1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_busecc_pend" "0,1" newline bitfld.long 0x4 14. "DATARAM_BANK0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank0_busecc_pend" "0,1" newline bitfld.long 0x4 13. "SRAM0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram0_busecc_pend" "0,1" newline bitfld.long 0x4 12. "RMW0_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 11. "RMW0_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 10. "RMW0_QUEUE_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 9. "RMW0_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 8. "RMW0_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 7. "RMW0_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 6. "RMW0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_busecc_pend" "0,1" newline bitfld.long 0x4 5. "EN_MSMC_P0_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_0_pend" "0,1" newline bitfld.long 0x4 4. "EN_MSMC_P0_BUSECC_DATA_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_data_pend" "0,1" newline bitfld.long 0x4 3. "CPU9_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu9_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 2. "CPU9_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu9_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 1. "CPU8_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu8_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 0. "CPU8_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu8_slv_local_arb_busecc_pend" "0,1" line.long 0x8 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_enable_clr_reg2,Interrupt Enable Clear Register 2" bitfld.long 0x8 31. "EN_MSMC_P0_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_1_pend" "0,1" newline bitfld.long 0x8 30. "EN_MSMC_P0_BUSECC_WRITE_RESP_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_write_resp_pend" "0,1" newline bitfld.long 0x8 29. "EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_wr_barrier_queue_pend" "0,1" newline bitfld.long 0x8 28. "EN_MSMC_P0_BUSECC_WACK_CID_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_wack_cid_queue_pend" "0,1" newline bitfld.long 0x8 27. "EN_MSMC_P0_BUSECC_SNP_RESP_BUF_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_snp_resp_buf_pend" "0,1" newline bitfld.long 0x8 26. "EN_MSMC_P0_BUSECC_SNP_DATA_BUF_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_snp_data_buf_pend" "0,1" newline bitfld.long 0x8 25. "EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_snoop_cmd_id_queue_pend" "0,1" newline bitfld.long 0x8 24. "EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_rd_barrier_queue_pend" "0,1" newline bitfld.long 0x8 23. "EN_MSMC_P0_BUSECC_RACK_CID_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_rack_cid_queue_pend" "0,1" newline bitfld.long 0x8 22. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 21. "EN_MSMC_P0_MMR_FW_EDC_CTL_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0x8 20. "CLEC_J7AE_CLEC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for clec_j7ae_clec_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "EMIF_1_VSAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for emif_1_vsafe_si_pend" "0,1" newline bitfld.long 0x8 18. "EMIF_0_VSAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for emif_0_vsafe_si_pend" "0,1" newline bitfld.long 0x8 17. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac5_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 15. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac4_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 14. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 13. "EMIF1_MST_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for emif1_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 12. "EMIF1_SLV_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for emif1_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 11. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 10. "CLEC_SRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clec_sram_ramecc_pend" "0,1" newline bitfld.long 0x8 9. "DATARAM_BANK3_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank3_busecc_pend" "0,1" newline bitfld.long 0x8 8. "SRAM3_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram3_busecc_pend" "0,1" newline bitfld.long 0x8 7. "RMW3_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 6. "RMW3_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x8 5. "RMW3_QUEUE_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_queue_busecc_2_pend" "0,1" newline bitfld.long 0x8 4. "RMW3_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_queue_busecc_1_pend" "0,1" newline bitfld.long 0x8 3. "RMW3_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_queue_busecc_0_pend" "0,1" newline bitfld.long 0x8 2. "RMW3_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 1. "RMW3_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_busecc_pend" "0,1" newline bitfld.long 0x8 0. "DATARAM_BANK2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank2_busecc_pend" "0,1" line.long 0xC "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_enable_clr_reg3,Interrupt Enable Clear Register 3" bitfld.long 0xC 1. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0xC 0. "EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_msmc_cmd_buffer_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_CFG_WRAP_0_MSMC_ECC_AGGR1 (COMPUTE_CLUSTER0_CFG_WRAP_0_MSMC_ECC_AGGR1)" base ad:0x4D20000400 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "VBUSP_CFG_ECC_AGGR3_P2P_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_ecc_aggr3_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 30. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR2_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_ecc_aggr2_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 28. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "J7AE_MSMC_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_gicss_m2m_bridge_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 25. "J7AE_MSMC_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_gicss_m2m_bridge_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 24. "DDRSS1_SRC_P2M_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for ddrss1_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x4 23. "DDRSS1_SRC_P2M_BUSECC_PEND,Interrupt Pending Status for ddrss1_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x4 22. "DDRSS1_M2M_SRC_VBUSS_PEND,Interrupt Pending Status for ddrss1_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x4 21. "DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for ddrss0_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x4 20. "DDRSS0_SRC_P2M_BUSECC_PEND,Interrupt Pending Status for ddrss0_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x4 19. "DDRSS0_M2M_SRC_VBUSS_PEND,Interrupt Pending Status for ddrss0_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x4 18. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS1_P2P_BRIDGE_VBUSP_DDRSS1_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss1_p2p_bridge_vbusp_ddrss1_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 17. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_VBUSP_DDRSS0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss0_p2p_bridge_vbusp_ddrss0_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusm_gicss_p2m_bridge_vbusm_gicss_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 14. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x4 13. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_pend" "0,1" newline bitfld.long 0x4 12. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x4 11. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_pend" "0,1" newline bitfld.long 0x4 10. "VBUSP_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_wrap_cbass_cbass_clk4_clk_clk_edc_busecc_pend" "0,1" newline bitfld.long 0x4 9. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR1_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 8. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 7. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_scr1_scr_j7ae_msmc_cfg_wrap_cbass_scr1_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 6. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_CBASS_INT_CLK4_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_clk4_clk_edc_ctrl_cbass_int_clk4_busecc_pend" "0,1" newline bitfld.long 0x4 5. "DMSC_MMR_PRIVID_EDC_CTRL_BUSECC_BUSECC_PEND,Interrupt Pending Status for dmsc_mmr_privid_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x4 4. "DMSC_MMR_EMULATION_EDC_CTRL_BUSECC_BUSECC_PEND,Interrupt Pending Status for dmsc_mmr_emulation_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x4 3. "DMSC_MMR_BOOT_EDC_CTRL_BUSECC_BUSECC_PEND,Interrupt Pending Status for dmsc_mmr_boot_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x4 2. "VBUSP_DMSC_CBASS_CBASS_SCR_SCR_EDC_BUSECC_0_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cbass_scr_scr_edc_busecc_0_pend" "0,1" newline bitfld.long 0x4 1. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_dru0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 0. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_src_busecc_pend" "0,1" line.long 0x8 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 8. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x8 7. "GICSS_VBUSM_GASKET_EDC_CTRL_PEND,Interrupt Pending Status for gicss_vbusm_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 6. "GICSS_VBUSM_GASKET_RD_RAMECC_PEND,Interrupt Pending Status for gicss_vbusm_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x8 5. "GICSS_VBUSM_GASKET_WR_RAMECC_PEND,Interrupt Pending Status for gicss_vbusm_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x8 4. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_GICSS_VBUSM_GASKET_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac5_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x8 2. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac4_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x8 1. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x8 0. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR3_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR3_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x7 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "VBUSP_CFG_ECC_AGGR3_P2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_ecc_aggr3_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 30. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR2_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_ecc_aggr2_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 28. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "J7AE_MSMC_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_gicss_m2m_bridge_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 25. "J7AE_MSMC_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_gicss_m2m_bridge_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 24. "DDRSS1_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddrss1_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 23. "DDRSS1_SRC_P2M_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddrss1_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x0 22. "DDRSS1_M2M_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ddrss1_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 21. "DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddrss0_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 20. "DDRSS0_SRC_P2M_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddrss0_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x0 19. "DDRSS0_M2M_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ddrss0_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 18. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS1_P2P_BRIDGE_VBUSP_DDRSS1_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss1_p2p_bridge_vbusp_ddrss1_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 17. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_VBUSP_DDRSS0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss0_p2p_bridge_vbusp_ddrss0_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusm_gicss_p2m_bridge_vbusm_gicss_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 14. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 13. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 12. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 11. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_pend" "0,1" newline bitfld.long 0x0 10. "VBUSP_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_wrap_cbass_cbass_clk4_clk_clk_edc_busecc_pend" "0,1" newline bitfld.long 0x0 9. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR1_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 8. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 7. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 6. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_CBASS_INT_CLK4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_clk4_clk_edc_ctrl_cbass_int_clk4_busecc_pend" "0,1" newline bitfld.long 0x0 5. "DMSC_MMR_PRIVID_EDC_CTRL_BUSECC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dmsc_mmr_privid_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 4. "DMSC_MMR_EMULATION_EDC_CTRL_BUSECC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dmsc_mmr_emulation_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 3. "DMSC_MMR_BOOT_EDC_CTRL_BUSECC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dmsc_mmr_boot_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 2. "VBUSP_DMSC_CBASS_CBASS_SCR_SCR_EDC_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cbass_scr_scr_edc_busecc_0_pend" "0,1" newline bitfld.long 0x0 1. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_dru0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 0. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_src_busecc_pend" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 8. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x4 7. "GICSS_VBUSM_GASKET_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for gicss_vbusm_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 6. "GICSS_VBUSM_GASKET_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for gicss_vbusm_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "GICSS_VBUSM_GASKET_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for gicss_vbusm_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_GICSS_VBUSM_GASKET_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac5_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 2. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac4_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 1. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 0. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR3_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR3_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "VBUSP_CFG_ECC_AGGR3_P2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_ecc_aggr3_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 30. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR2_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_ecc_aggr2_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 28. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "J7AE_MSMC_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_gicss_m2m_bridge_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 25. "J7AE_MSMC_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_gicss_m2m_bridge_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 24. "DDRSS1_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddrss1_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 23. "DDRSS1_SRC_P2M_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddrss1_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x0 22. "DDRSS1_M2M_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ddrss1_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 21. "DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddrss0_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 20. "DDRSS0_SRC_P2M_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddrss0_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x0 19. "DDRSS0_M2M_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ddrss0_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 18. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS1_P2P_BRIDGE_VBUSP_DDRSS1_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss1_p2p_bridge_vbusp_ddrss1_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 17. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_VBUSP_DDRSS0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss0_p2p_bridge_vbusp_ddrss0_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusm_gicss_p2m_bridge_vbusm_gicss_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 14. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 13. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 12. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 11. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_pend" "0,1" newline bitfld.long 0x0 10. "VBUSP_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_wrap_cbass_cbass_clk4_clk_clk_edc_busecc_pend" "0,1" newline bitfld.long 0x0 9. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR1_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 8. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 7. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 6. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_CBASS_INT_CLK4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_clk4_clk_edc_ctrl_cbass_int_clk4_busecc_pend" "0,1" newline bitfld.long 0x0 5. "DMSC_MMR_PRIVID_EDC_CTRL_BUSECC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dmsc_mmr_privid_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 4. "DMSC_MMR_EMULATION_EDC_CTRL_BUSECC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dmsc_mmr_emulation_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 3. "DMSC_MMR_BOOT_EDC_CTRL_BUSECC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dmsc_mmr_boot_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 2. "VBUSP_DMSC_CBASS_CBASS_SCR_SCR_EDC_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cbass_scr_scr_edc_busecc_0_pend" "0,1" newline bitfld.long 0x0 1. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_dru0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 0. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_src_busecc_pend" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 8. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x4 7. "GICSS_VBUSM_GASKET_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for gicss_vbusm_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 6. "GICSS_VBUSM_GASKET_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for gicss_vbusm_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "GICSS_VBUSM_GASKET_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for gicss_vbusm_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_GICSS_VBUSM_GASKET_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac5_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 2. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac4_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 1. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 0. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR3_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR3_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0xB line.long 0x0 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "VBUSP_CFG_ECC_AGGR3_P2P_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_ecc_aggr3_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 30. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR2_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_ecc_aggr2_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 28. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "J7AE_MSMC_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_gicss_m2m_bridge_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 25. "J7AE_MSMC_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_gicss_m2m_bridge_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 24. "DDRSS1_SRC_P2M_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for ddrss1_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x4 23. "DDRSS1_SRC_P2M_BUSECC_PEND,Interrupt Pending Status for ddrss1_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x4 22. "DDRSS1_M2M_SRC_VBUSS_PEND,Interrupt Pending Status for ddrss1_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x4 21. "DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for ddrss0_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x4 20. "DDRSS0_SRC_P2M_BUSECC_PEND,Interrupt Pending Status for ddrss0_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x4 19. "DDRSS0_M2M_SRC_VBUSS_PEND,Interrupt Pending Status for ddrss0_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x4 18. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS1_P2P_BRIDGE_VBUSP_DDRSS1_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss1_p2p_bridge_vbusp_ddrss1_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 17. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_VBUSP_DDRSS0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss0_p2p_bridge_vbusp_ddrss0_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusm_gicss_p2m_bridge_vbusm_gicss_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 14. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x4 13. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_pend" "0,1" newline bitfld.long 0x4 12. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x4 11. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_pend" "0,1" newline bitfld.long 0x4 10. "VBUSP_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_wrap_cbass_cbass_clk4_clk_clk_edc_busecc_pend" "0,1" newline bitfld.long 0x4 9. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR1_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 8. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 7. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_scr1_scr_j7ae_msmc_cfg_wrap_cbass_scr1_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 6. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_CBASS_INT_CLK4_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_clk4_clk_edc_ctrl_cbass_int_clk4_busecc_pend" "0,1" newline bitfld.long 0x4 5. "DMSC_MMR_PRIVID_EDC_CTRL_BUSECC_BUSECC_PEND,Interrupt Pending Status for dmsc_mmr_privid_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x4 4. "DMSC_MMR_EMULATION_EDC_CTRL_BUSECC_BUSECC_PEND,Interrupt Pending Status for dmsc_mmr_emulation_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x4 3. "DMSC_MMR_BOOT_EDC_CTRL_BUSECC_BUSECC_PEND,Interrupt Pending Status for dmsc_mmr_boot_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x4 2. "VBUSP_DMSC_CBASS_CBASS_SCR_SCR_EDC_BUSECC_0_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cbass_scr_scr_edc_busecc_0_pend" "0,1" newline bitfld.long 0x4 1. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_dru0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 0. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_src_busecc_pend" "0,1" line.long 0x8 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 8. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x8 7. "GICSS_VBUSM_GASKET_EDC_CTRL_PEND,Interrupt Pending Status for gicss_vbusm_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 6. "GICSS_VBUSM_GASKET_RD_RAMECC_PEND,Interrupt Pending Status for gicss_vbusm_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x8 5. "GICSS_VBUSM_GASKET_WR_RAMECC_PEND,Interrupt Pending Status for gicss_vbusm_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x8 4. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_GICSS_VBUSM_GASKET_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac5_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x8 2. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac4_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x8 1. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x8 0. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR3_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR3_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x7 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "VBUSP_CFG_ECC_AGGR3_P2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_ecc_aggr3_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 30. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR2_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_ecc_aggr2_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 28. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "J7AE_MSMC_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_gicss_m2m_bridge_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 25. "J7AE_MSMC_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_gicss_m2m_bridge_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 24. "DDRSS1_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddrss1_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 23. "DDRSS1_SRC_P2M_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddrss1_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x0 22. "DDRSS1_M2M_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ddrss1_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 21. "DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddrss0_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 20. "DDRSS0_SRC_P2M_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddrss0_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x0 19. "DDRSS0_M2M_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ddrss0_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 18. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS1_P2P_BRIDGE_VBUSP_DDRSS1_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss1_p2p_bridge_vbusp_ddrss1_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 17. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_VBUSP_DDRSS0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss0_p2p_bridge_vbusp_ddrss0_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusm_gicss_p2m_bridge_vbusm_gicss_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 14. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 13. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 12. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 11. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_pend" "0,1" newline bitfld.long 0x0 10. "VBUSP_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_wrap_cbass_cbass_clk4_clk_clk_edc_busecc_pend" "0,1" newline bitfld.long 0x0 9. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR1_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 8. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 7. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 6. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_CBASS_INT_CLK4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_clk4_clk_edc_ctrl_cbass_int_clk4_busecc_pend" "0,1" newline bitfld.long 0x0 5. "DMSC_MMR_PRIVID_EDC_CTRL_BUSECC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dmsc_mmr_privid_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 4. "DMSC_MMR_EMULATION_EDC_CTRL_BUSECC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dmsc_mmr_emulation_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 3. "DMSC_MMR_BOOT_EDC_CTRL_BUSECC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dmsc_mmr_boot_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 2. "VBUSP_DMSC_CBASS_CBASS_SCR_SCR_EDC_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cbass_scr_scr_edc_busecc_0_pend" "0,1" newline bitfld.long 0x0 1. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_dru0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 0. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_src_busecc_pend" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 8. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x4 7. "GICSS_VBUSM_GASKET_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for gicss_vbusm_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 6. "GICSS_VBUSM_GASKET_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for gicss_vbusm_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "GICSS_VBUSM_GASKET_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for gicss_vbusm_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_GICSS_VBUSM_GASKET_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac5_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 2. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac4_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 1. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 0. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR3_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR3_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "VBUSP_CFG_ECC_AGGR3_P2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_ecc_aggr3_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 30. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR2_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_ecc_aggr2_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 28. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "J7AE_MSMC_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_gicss_m2m_bridge_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 25. "J7AE_MSMC_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_gicss_m2m_bridge_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 24. "DDRSS1_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddrss1_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 23. "DDRSS1_SRC_P2M_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddrss1_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x0 22. "DDRSS1_M2M_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ddrss1_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 21. "DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddrss0_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 20. "DDRSS0_SRC_P2M_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddrss0_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x0 19. "DDRSS0_M2M_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ddrss0_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 18. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS1_P2P_BRIDGE_VBUSP_DDRSS1_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss1_p2p_bridge_vbusp_ddrss1_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 17. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_VBUSP_DDRSS0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss0_p2p_bridge_vbusp_ddrss0_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusm_gicss_p2m_bridge_vbusm_gicss_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 14. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 13. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 12. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 11. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_pend" "0,1" newline bitfld.long 0x0 10. "VBUSP_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_wrap_cbass_cbass_clk4_clk_clk_edc_busecc_pend" "0,1" newline bitfld.long 0x0 9. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR1_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 8. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 7. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 6. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_CBASS_INT_CLK4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_clk4_clk_edc_ctrl_cbass_int_clk4_busecc_pend" "0,1" newline bitfld.long 0x0 5. "DMSC_MMR_PRIVID_EDC_CTRL_BUSECC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dmsc_mmr_privid_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 4. "DMSC_MMR_EMULATION_EDC_CTRL_BUSECC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dmsc_mmr_emulation_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 3. "DMSC_MMR_BOOT_EDC_CTRL_BUSECC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dmsc_mmr_boot_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 2. "VBUSP_DMSC_CBASS_CBASS_SCR_SCR_EDC_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cbass_scr_scr_edc_busecc_0_pend" "0,1" newline bitfld.long 0x0 1. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_dru0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 0. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_src_busecc_pend" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 8. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x4 7. "GICSS_VBUSM_GASKET_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for gicss_vbusm_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 6. "GICSS_VBUSM_GASKET_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for gicss_vbusm_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "GICSS_VBUSM_GASKET_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for gicss_vbusm_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_GICSS_VBUSM_GASKET_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac5_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 2. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac4_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 1. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 0. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR3_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR3_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_CFG_WRAP_0_MSMC_DDR_0_ECC_AGGR2 (COMPUTE_CLUSTER0_CFG_WRAP_0_MSMC_DDR_0_ECC_AGGR2)" base ad:0x4D20000800 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP_MSMC_DDR_0_ECC_AGGR_CFG_MSMC_ECC2_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP_MSMC_DDR_0_ECC_AGGR_CFG_MSMC_ECC2_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP_MSMC_DDR_0_ECC_AGGR_CFG_MSMC_ECC2_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP_MSMC_DDR_0_ECC_AGGR_CFG_MSMC_ECC2_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "__VBUSP_MSMC_DDR_0_ECC_AGGR_CFG_MSMC_ECC2_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_MSMC_DDR_0_ECC_AGGR_CFG_MSMC_ECC2_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x4 1. "VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_ecc_aggr2_p2p_dst_busecc_pend" "0,1" newline bitfld.long 0x4 0. "DDRSS0_ASAFE_SI_PEND,Interrupt Pending Status for ddrss0_asafe_si_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "__VBUSP_MSMC_DDR_0_ECC_AGGR_CFG_MSMC_ECC2_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x0 1. "VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_ecc_aggr2_p2p_dst_busecc_pend" "0,1" newline bitfld.long 0x0 0. "DDRSS0_ASAFE_SI_ENABLE_SET,Interrupt Enable Set Register for ddrss0_asafe_si_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "__VBUSP_MSMC_DDR_0_ECC_AGGR_CFG_MSMC_ECC2_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x0 1. "VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_ecc_aggr2_p2p_dst_busecc_pend" "0,1" newline bitfld.long 0x0 0. "DDRSS0_ASAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for ddrss0_asafe_si_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "__VBUSP_MSMC_DDR_0_ECC_AGGR_CFG_MSMC_ECC2_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_MSMC_DDR_0_ECC_AGGR_CFG_MSMC_ECC2_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x4 1. "VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_ecc_aggr2_p2p_dst_busecc_pend" "0,1" newline bitfld.long 0x4 0. "DDRSS0_ASAFE_SI_PEND,Interrupt Pending Status for ddrss0_asafe_si_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "__VBUSP_MSMC_DDR_0_ECC_AGGR_CFG_MSMC_ECC2_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x0 1. "VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_ecc_aggr2_p2p_dst_busecc_pend" "0,1" newline bitfld.long 0x0 0. "DDRSS0_ASAFE_SI_ENABLE_SET,Interrupt Enable Set Register for ddrss0_asafe_si_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "__VBUSP_MSMC_DDR_0_ECC_AGGR_CFG_MSMC_ECC2_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x0 1. "VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_ecc_aggr2_p2p_dst_busecc_pend" "0,1" newline bitfld.long 0x0 0. "DDRSS0_ASAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for ddrss0_asafe_si_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP_MSMC_DDR_0_ECC_AGGR_CFG_MSMC_ECC2_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP_MSMC_DDR_0_ECC_AGGR_CFG_MSMC_ECC2_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP_MSMC_DDR_0_ECC_AGGR_CFG_MSMC_ECC2_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP_MSMC_DDR_0_ECC_AGGR_CFG_MSMC_ECC2_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_CFG_WRAP_0_MSMC_DDR_1_ECC_AGGR3 (COMPUTE_CLUSTER0_CFG_WRAP_0_MSMC_DDR_1_ECC_AGGR3)" base ad:0x4D20000C00 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP_MSMC_DDR_1_ECC_AGGR_CFG_MSMC_ECC3_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP_MSMC_DDR_1_ECC_AGGR_CFG_MSMC_ECC3_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP_MSMC_DDR_1_ECC_AGGR_CFG_MSMC_ECC3_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP_MSMC_DDR_1_ECC_AGGR_CFG_MSMC_ECC3_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "__VBUSP_MSMC_DDR_1_ECC_AGGR_CFG_MSMC_ECC3_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_MSMC_DDR_1_ECC_AGGR_CFG_MSMC_ECC3_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x4 1. "VBUSP_CFG_ECC_AGGR3_P2P_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_ecc_aggr3_p2p_dst_busecc_pend" "0,1" newline bitfld.long 0x4 0. "DDRSS1_ASAFE_SI_PEND,Interrupt Pending Status for ddrss1_asafe_si_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "__VBUSP_MSMC_DDR_1_ECC_AGGR_CFG_MSMC_ECC3_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x0 1. "VBUSP_CFG_ECC_AGGR3_P2P_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_ecc_aggr3_p2p_dst_busecc_pend" "0,1" newline bitfld.long 0x0 0. "DDRSS1_ASAFE_SI_ENABLE_SET,Interrupt Enable Set Register for ddrss1_asafe_si_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "__VBUSP_MSMC_DDR_1_ECC_AGGR_CFG_MSMC_ECC3_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x0 1. "VBUSP_CFG_ECC_AGGR3_P2P_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_ecc_aggr3_p2p_dst_busecc_pend" "0,1" newline bitfld.long 0x0 0. "DDRSS1_ASAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for ddrss1_asafe_si_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "__VBUSP_MSMC_DDR_1_ECC_AGGR_CFG_MSMC_ECC3_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_MSMC_DDR_1_ECC_AGGR_CFG_MSMC_ECC3_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x4 1. "VBUSP_CFG_ECC_AGGR3_P2P_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_ecc_aggr3_p2p_dst_busecc_pend" "0,1" newline bitfld.long 0x4 0. "DDRSS1_ASAFE_SI_PEND,Interrupt Pending Status for ddrss1_asafe_si_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "__VBUSP_MSMC_DDR_1_ECC_AGGR_CFG_MSMC_ECC3_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x0 1. "VBUSP_CFG_ECC_AGGR3_P2P_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_ecc_aggr3_p2p_dst_busecc_pend" "0,1" newline bitfld.long 0x0 0. "DDRSS1_ASAFE_SI_ENABLE_SET,Interrupt Enable Set Register for ddrss1_asafe_si_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "__VBUSP_MSMC_DDR_1_ECC_AGGR_CFG_MSMC_ECC3_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x0 1. "VBUSP_CFG_ECC_AGGR3_P2P_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_ecc_aggr3_p2p_dst_busecc_pend" "0,1" newline bitfld.long 0x0 0. "DDRSS1_ASAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for ddrss1_asafe_si_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP_MSMC_DDR_1_ECC_AGGR_CFG_MSMC_ECC3_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP_MSMC_DDR_1_ECC_AGGR_CFG_MSMC_ECC3_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP_MSMC_DDR_1_ECC_AGGR_CFG_MSMC_ECC3_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP_MSMC_DDR_1_ECC_AGGR_CFG_MSMC_ECC3_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_CFG_WRAP_0_DSP0_ECC_AGGR (COMPUTE_CLUSTER0_CFG_WRAP_0_DSP0_ECC_AGGR)" base ad:0x4D20050000 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 18. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x4 17. "PMC_BUSECC_PEND,Interrupt Pending Status for pmc_busecc_pend" "0,1" newline bitfld.long 0x4 16. "SE_1_BUSECC_PEND,Interrupt Pending Status for se_1_busecc_pend" "0,1" newline bitfld.long 0x4 15. "SE_0_BUSECC_PEND,Interrupt Pending Status for se_0_busecc_pend" "0,1" newline bitfld.long 0x4 14. "BUSECC_TAGRAM_DMC_PEND,Interrupt Pending Status for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x4 13. "BUSECC_DMC_PEND,Interrupt Pending Status for busecc_dmc_pend" "0,1" newline bitfld.long 0x4 12. "BUSECC_PIPE3_P2_PEND,Interrupt Pending Status for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x4 11. "BUSECC_PIPE3_DP_PEND,Interrupt Pending Status for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x4 10. "BUSECC_PIPE2_P2_PEND,Interrupt Pending Status for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x4 9. "BUSECC_PIPE2_DP_PEND,Interrupt Pending Status for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x4 8. "BUSECC_PIPE1_P2_PEND,Interrupt Pending Status for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x4 7. "BUSECC_PIPE1_DP_PEND,Interrupt Pending Status for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x4 6. "BUSECC_PIPE0_P2_PEND,Interrupt Pending Status for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x4 5. "BUSECC_PIPE0_DP_PEND,Interrupt Pending Status for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x4 4. "UMC_FW_MDMA_BUSECC_PEND,Interrupt Pending Status for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x4 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x3 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 18. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x0 17. "PMC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for pmc_busecc_pend" "0,1" newline bitfld.long 0x0 16. "SE_1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for se_1_busecc_pend" "0,1" newline bitfld.long 0x0 15. "SE_0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for se_0_busecc_pend" "0,1" newline bitfld.long 0x0 14. "BUSECC_TAGRAM_DMC_ENABLE_SET,Interrupt Enable Set Register for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x0 13. "BUSECC_DMC_ENABLE_SET,Interrupt Enable Set Register for busecc_dmc_pend" "0,1" newline bitfld.long 0x0 12. "BUSECC_PIPE3_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x0 11. "BUSECC_PIPE3_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x0 10. "BUSECC_PIPE2_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x0 9. "BUSECC_PIPE2_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x0 8. "BUSECC_PIPE1_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x0 7. "BUSECC_PIPE1_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x0 6. "BUSECC_PIPE0_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x0 5. "BUSECC_PIPE0_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x0 4. "UMC_FW_MDMA_BUSECC_ENABLE_SET,Interrupt Enable Set Register for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x0 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 18. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x0 17. "PMC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for pmc_busecc_pend" "0,1" newline bitfld.long 0x0 16. "SE_1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for se_1_busecc_pend" "0,1" newline bitfld.long 0x0 15. "SE_0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for se_0_busecc_pend" "0,1" newline bitfld.long 0x0 14. "BUSECC_TAGRAM_DMC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x0 13. "BUSECC_DMC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_dmc_pend" "0,1" newline bitfld.long 0x0 12. "BUSECC_PIPE3_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x0 11. "BUSECC_PIPE3_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x0 10. "BUSECC_PIPE2_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x0 9. "BUSECC_PIPE2_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x0 8. "BUSECC_PIPE1_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x0 7. "BUSECC_PIPE1_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x0 6. "BUSECC_PIPE0_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x0 5. "BUSECC_PIPE0_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x0 4. "UMC_FW_MDMA_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x0 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 18. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x4 17. "PMC_BUSECC_PEND,Interrupt Pending Status for pmc_busecc_pend" "0,1" newline bitfld.long 0x4 16. "SE_1_BUSECC_PEND,Interrupt Pending Status for se_1_busecc_pend" "0,1" newline bitfld.long 0x4 15. "SE_0_BUSECC_PEND,Interrupt Pending Status for se_0_busecc_pend" "0,1" newline bitfld.long 0x4 14. "BUSECC_TAGRAM_DMC_PEND,Interrupt Pending Status for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x4 13. "BUSECC_DMC_PEND,Interrupt Pending Status for busecc_dmc_pend" "0,1" newline bitfld.long 0x4 12. "BUSECC_PIPE3_P2_PEND,Interrupt Pending Status for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x4 11. "BUSECC_PIPE3_DP_PEND,Interrupt Pending Status for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x4 10. "BUSECC_PIPE2_P2_PEND,Interrupt Pending Status for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x4 9. "BUSECC_PIPE2_DP_PEND,Interrupt Pending Status for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x4 8. "BUSECC_PIPE1_P2_PEND,Interrupt Pending Status for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x4 7. "BUSECC_PIPE1_DP_PEND,Interrupt Pending Status for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x4 6. "BUSECC_PIPE0_P2_PEND,Interrupt Pending Status for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x4 5. "BUSECC_PIPE0_DP_PEND,Interrupt Pending Status for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x4 4. "UMC_FW_MDMA_BUSECC_PEND,Interrupt Pending Status for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x4 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x3 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 18. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x0 17. "PMC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for pmc_busecc_pend" "0,1" newline bitfld.long 0x0 16. "SE_1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for se_1_busecc_pend" "0,1" newline bitfld.long 0x0 15. "SE_0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for se_0_busecc_pend" "0,1" newline bitfld.long 0x0 14. "BUSECC_TAGRAM_DMC_ENABLE_SET,Interrupt Enable Set Register for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x0 13. "BUSECC_DMC_ENABLE_SET,Interrupt Enable Set Register for busecc_dmc_pend" "0,1" newline bitfld.long 0x0 12. "BUSECC_PIPE3_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x0 11. "BUSECC_PIPE3_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x0 10. "BUSECC_PIPE2_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x0 9. "BUSECC_PIPE2_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x0 8. "BUSECC_PIPE1_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x0 7. "BUSECC_PIPE1_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x0 6. "BUSECC_PIPE0_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x0 5. "BUSECC_PIPE0_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x0 4. "UMC_FW_MDMA_BUSECC_ENABLE_SET,Interrupt Enable Set Register for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x0 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 18. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x0 17. "PMC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for pmc_busecc_pend" "0,1" newline bitfld.long 0x0 16. "SE_1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for se_1_busecc_pend" "0,1" newline bitfld.long 0x0 15. "SE_0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for se_0_busecc_pend" "0,1" newline bitfld.long 0x0 14. "BUSECC_TAGRAM_DMC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x0 13. "BUSECC_DMC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_dmc_pend" "0,1" newline bitfld.long 0x0 12. "BUSECC_PIPE3_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x0 11. "BUSECC_PIPE3_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x0 10. "BUSECC_PIPE2_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x0 9. "BUSECC_PIPE2_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x0 8. "BUSECC_PIPE1_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x0 7. "BUSECC_PIPE1_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x0 6. "BUSECC_PIPE0_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x0 5. "BUSECC_PIPE0_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x0 4. "UMC_FW_MDMA_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x0 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP4_CFG_DSP4__CFG_DSP_ECCAGGR4_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_CFG_WRAP_0_DSP1_ECCAGGR (COMPUTE_CLUSTER0_CFG_WRAP_0_DSP1_ECCAGGR)" base ad:0x4D20060000 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 18. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x4 17. "PMC_BUSECC_PEND,Interrupt Pending Status for pmc_busecc_pend" "0,1" newline bitfld.long 0x4 16. "SE_1_BUSECC_PEND,Interrupt Pending Status for se_1_busecc_pend" "0,1" newline bitfld.long 0x4 15. "SE_0_BUSECC_PEND,Interrupt Pending Status for se_0_busecc_pend" "0,1" newline bitfld.long 0x4 14. "BUSECC_TAGRAM_DMC_PEND,Interrupt Pending Status for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x4 13. "BUSECC_DMC_PEND,Interrupt Pending Status for busecc_dmc_pend" "0,1" newline bitfld.long 0x4 12. "BUSECC_PIPE3_P2_PEND,Interrupt Pending Status for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x4 11. "BUSECC_PIPE3_DP_PEND,Interrupt Pending Status for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x4 10. "BUSECC_PIPE2_P2_PEND,Interrupt Pending Status for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x4 9. "BUSECC_PIPE2_DP_PEND,Interrupt Pending Status for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x4 8. "BUSECC_PIPE1_P2_PEND,Interrupt Pending Status for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x4 7. "BUSECC_PIPE1_DP_PEND,Interrupt Pending Status for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x4 6. "BUSECC_PIPE0_P2_PEND,Interrupt Pending Status for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x4 5. "BUSECC_PIPE0_DP_PEND,Interrupt Pending Status for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x4 4. "UMC_FW_MDMA_BUSECC_PEND,Interrupt Pending Status for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x4 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x3 line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 18. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x0 17. "PMC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for pmc_busecc_pend" "0,1" newline bitfld.long 0x0 16. "SE_1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for se_1_busecc_pend" "0,1" newline bitfld.long 0x0 15. "SE_0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for se_0_busecc_pend" "0,1" newline bitfld.long 0x0 14. "BUSECC_TAGRAM_DMC_ENABLE_SET,Interrupt Enable Set Register for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x0 13. "BUSECC_DMC_ENABLE_SET,Interrupt Enable Set Register for busecc_dmc_pend" "0,1" newline bitfld.long 0x0 12. "BUSECC_PIPE3_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x0 11. "BUSECC_PIPE3_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x0 10. "BUSECC_PIPE2_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x0 9. "BUSECC_PIPE2_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x0 8. "BUSECC_PIPE1_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x0 7. "BUSECC_PIPE1_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x0 6. "BUSECC_PIPE0_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x0 5. "BUSECC_PIPE0_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x0 4. "UMC_FW_MDMA_BUSECC_ENABLE_SET,Interrupt Enable Set Register for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x0 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 18. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x0 17. "PMC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for pmc_busecc_pend" "0,1" newline bitfld.long 0x0 16. "SE_1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for se_1_busecc_pend" "0,1" newline bitfld.long 0x0 15. "SE_0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for se_0_busecc_pend" "0,1" newline bitfld.long 0x0 14. "BUSECC_TAGRAM_DMC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x0 13. "BUSECC_DMC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_dmc_pend" "0,1" newline bitfld.long 0x0 12. "BUSECC_PIPE3_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x0 11. "BUSECC_PIPE3_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x0 10. "BUSECC_PIPE2_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x0 9. "BUSECC_PIPE2_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x0 8. "BUSECC_PIPE1_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x0 7. "BUSECC_PIPE1_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x0 6. "BUSECC_PIPE0_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x0 5. "BUSECC_PIPE0_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x0 4. "UMC_FW_MDMA_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x0 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 18. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x4 17. "PMC_BUSECC_PEND,Interrupt Pending Status for pmc_busecc_pend" "0,1" newline bitfld.long 0x4 16. "SE_1_BUSECC_PEND,Interrupt Pending Status for se_1_busecc_pend" "0,1" newline bitfld.long 0x4 15. "SE_0_BUSECC_PEND,Interrupt Pending Status for se_0_busecc_pend" "0,1" newline bitfld.long 0x4 14. "BUSECC_TAGRAM_DMC_PEND,Interrupt Pending Status for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x4 13. "BUSECC_DMC_PEND,Interrupt Pending Status for busecc_dmc_pend" "0,1" newline bitfld.long 0x4 12. "BUSECC_PIPE3_P2_PEND,Interrupt Pending Status for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x4 11. "BUSECC_PIPE3_DP_PEND,Interrupt Pending Status for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x4 10. "BUSECC_PIPE2_P2_PEND,Interrupt Pending Status for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x4 9. "BUSECC_PIPE2_DP_PEND,Interrupt Pending Status for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x4 8. "BUSECC_PIPE1_P2_PEND,Interrupt Pending Status for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x4 7. "BUSECC_PIPE1_DP_PEND,Interrupt Pending Status for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x4 6. "BUSECC_PIPE0_P2_PEND,Interrupt Pending Status for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x4 5. "BUSECC_PIPE0_DP_PEND,Interrupt Pending Status for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x4 4. "UMC_FW_MDMA_BUSECC_PEND,Interrupt Pending Status for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x4 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x3 line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 18. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x0 17. "PMC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for pmc_busecc_pend" "0,1" newline bitfld.long 0x0 16. "SE_1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for se_1_busecc_pend" "0,1" newline bitfld.long 0x0 15. "SE_0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for se_0_busecc_pend" "0,1" newline bitfld.long 0x0 14. "BUSECC_TAGRAM_DMC_ENABLE_SET,Interrupt Enable Set Register for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x0 13. "BUSECC_DMC_ENABLE_SET,Interrupt Enable Set Register for busecc_dmc_pend" "0,1" newline bitfld.long 0x0 12. "BUSECC_PIPE3_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x0 11. "BUSECC_PIPE3_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x0 10. "BUSECC_PIPE2_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x0 9. "BUSECC_PIPE2_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x0 8. "BUSECC_PIPE1_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x0 7. "BUSECC_PIPE1_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x0 6. "BUSECC_PIPE0_P2_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x0 5. "BUSECC_PIPE0_DP_ENABLE_SET,Interrupt Enable Set Register for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x0 4. "UMC_FW_MDMA_BUSECC_ENABLE_SET,Interrupt Enable Set Register for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x0 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 18. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x0 17. "PMC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for pmc_busecc_pend" "0,1" newline bitfld.long 0x0 16. "SE_1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for se_1_busecc_pend" "0,1" newline bitfld.long 0x0 15. "SE_0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for se_0_busecc_pend" "0,1" newline bitfld.long 0x0 14. "BUSECC_TAGRAM_DMC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_tagram_dmc_pend" "0,1" newline bitfld.long 0x0 13. "BUSECC_DMC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_dmc_pend" "0,1" newline bitfld.long 0x0 12. "BUSECC_PIPE3_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe3_p2_pend" "0,1" newline bitfld.long 0x0 11. "BUSECC_PIPE3_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe3_dp_pend" "0,1" newline bitfld.long 0x0 10. "BUSECC_PIPE2_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe2_p2_pend" "0,1" newline bitfld.long 0x0 9. "BUSECC_PIPE2_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe2_dp_pend" "0,1" newline bitfld.long 0x0 8. "BUSECC_PIPE1_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe1_p2_pend" "0,1" newline bitfld.long 0x0 7. "BUSECC_PIPE1_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe1_dp_pend" "0,1" newline bitfld.long 0x0 6. "BUSECC_PIPE0_P2_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe0_p2_pend" "0,1" newline bitfld.long 0x0 5. "BUSECC_PIPE0_DP_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pipe0_dp_pend" "0,1" newline bitfld.long 0x0 4. "UMC_FW_MDMA_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for umc_fw_mdma_busecc_pend" "0,1" newline bitfld.long 0x0 3. "AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_AC71_COREPAC_DMSC_CBASS_DMSC_FW_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 2. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 1. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_AC71_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 0. "AC71_COREPAC_CFG_CBASS_CFG_CBASS_AC71_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP4_CFG_DSP5__CFG_DSP_ECCAGGR5_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_CFG_WRAP_0_DDR0_0_ECC_AGGR_CTL (COMPUTE_CLUSTER0_CFG_WRAP_0_DDR0_0_ECC_AGGR_CTL)" base ad:0x4D200B0000 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 4. "V2A_EDC_CTRL_PEND,Interrupt Pending Status for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 3. "ASAFE_3_SI_PEND,Interrupt Pending Status for asafe_3_si_pend" "0,1" newline bitfld.long 0x4 2. "ASAFE_2_SI_PEND,Interrupt Pending Status for asafe_2_si_pend" "0,1" newline bitfld.long 0x4 1. "ASAFE_1_SI_PEND,Interrupt Pending Status for asafe_1_si_pend" "0,1" newline bitfld.long 0x4 0. "ASAFE_0_SI_PEND,Interrupt Pending Status for asafe_0_si_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 4. "V2A_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 3. "ASAFE_3_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_3_si_pend" "0,1" newline bitfld.long 0x0 2. "ASAFE_2_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_2_si_pend" "0,1" newline bitfld.long 0x0 1. "ASAFE_1_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_1_si_pend" "0,1" newline bitfld.long 0x0 0. "ASAFE_0_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_0_si_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 4. "V2A_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 3. "ASAFE_3_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_3_si_pend" "0,1" newline bitfld.long 0x0 2. "ASAFE_2_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_2_si_pend" "0,1" newline bitfld.long 0x0 1. "ASAFE_1_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_1_si_pend" "0,1" newline bitfld.long 0x0 0. "ASAFE_0_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_0_si_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 4. "V2A_EDC_CTRL_PEND,Interrupt Pending Status for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 3. "ASAFE_3_SI_PEND,Interrupt Pending Status for asafe_3_si_pend" "0,1" newline bitfld.long 0x4 2. "ASAFE_2_SI_PEND,Interrupt Pending Status for asafe_2_si_pend" "0,1" newline bitfld.long 0x4 1. "ASAFE_1_SI_PEND,Interrupt Pending Status for asafe_1_si_pend" "0,1" newline bitfld.long 0x4 0. "ASAFE_0_SI_PEND,Interrupt Pending Status for asafe_0_si_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 4. "V2A_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 3. "ASAFE_3_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_3_si_pend" "0,1" newline bitfld.long 0x0 2. "ASAFE_2_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_2_si_pend" "0,1" newline bitfld.long 0x0 1. "ASAFE_1_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_1_si_pend" "0,1" newline bitfld.long 0x0 0. "ASAFE_0_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_0_si_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 4. "V2A_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 3. "ASAFE_3_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_3_si_pend" "0,1" newline bitfld.long 0x0 2. "ASAFE_2_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_2_si_pend" "0,1" newline bitfld.long 0x0 1. "ASAFE_1_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_1_si_pend" "0,1" newline bitfld.long 0x0 0. "ASAFE_0_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_0_si_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_CFG_WRAP_0_DDR0_0_ECC_AGGR_VBUS (COMPUTE_CLUSTER0_CFG_WRAP_0_DDR0_0_ECC_AGGR_VBUS)" base ad:0x4D200B0400 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "VSAFE_SI_PEND,Interrupt Pending Status for vsafe_si_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "VSAFE_SI_ENABLE_SET,Interrupt Enable Set Register for vsafe_si_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "VSAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for vsafe_si_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "VSAFE_SI_PEND,Interrupt Pending Status for vsafe_si_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "VSAFE_SI_ENABLE_SET,Interrupt Enable Set Register for vsafe_si_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "VSAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for vsafe_si_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_CFG_WRAP_0_DDR0_0_ECC_AGGR_CFG (COMPUTE_CLUSTER0_CFG_WRAP_0_DDR0_0_ECC_AGGR_CFG)" base ad:0x4D200B0800 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x4 2. "DST_M2P_BUSECC_PEND,Interrupt Pending Status for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x4 1. "M2M_M2M_VBUSS_PEND,Interrupt Pending Status for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 0. "M2M_DST_VBUSS_PEND,Interrupt Pending Status for m2m_dst_vbuss_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x0 2. "DST_M2P_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 1. "M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_dst_vbuss_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x0 2. "DST_M2P_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 1. "M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_dst_vbuss_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x4 2. "DST_M2P_BUSECC_PEND,Interrupt Pending Status for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x4 1. "M2M_M2M_VBUSS_PEND,Interrupt Pending Status for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 0. "M2M_DST_VBUSS_PEND,Interrupt Pending Status for m2m_dst_vbuss_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x0 2. "DST_M2P_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 1. "M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_dst_vbuss_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x0 2. "DST_M2P_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 1. "M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_dst_vbuss_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_CFG_WRAP_0_DDR1_1_ECC_AGGR_CTL (COMPUTE_CLUSTER0_CFG_WRAP_0_DDR1_1_ECC_AGGR_CTL)" base ad:0x4D200B0C00 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CTL_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CTL_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CTL_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CTL_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CTL_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CTL_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 4. "V2A_EDC_CTRL_PEND,Interrupt Pending Status for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 3. "ASAFE_3_SI_PEND,Interrupt Pending Status for asafe_3_si_pend" "0,1" newline bitfld.long 0x4 2. "ASAFE_2_SI_PEND,Interrupt Pending Status for asafe_2_si_pend" "0,1" newline bitfld.long 0x4 1. "ASAFE_1_SI_PEND,Interrupt Pending Status for asafe_1_si_pend" "0,1" newline bitfld.long 0x4 0. "ASAFE_0_SI_PEND,Interrupt Pending Status for asafe_0_si_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CTL_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 4. "V2A_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 3. "ASAFE_3_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_3_si_pend" "0,1" newline bitfld.long 0x0 2. "ASAFE_2_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_2_si_pend" "0,1" newline bitfld.long 0x0 1. "ASAFE_1_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_1_si_pend" "0,1" newline bitfld.long 0x0 0. "ASAFE_0_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_0_si_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CTL_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 4. "V2A_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 3. "ASAFE_3_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_3_si_pend" "0,1" newline bitfld.long 0x0 2. "ASAFE_2_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_2_si_pend" "0,1" newline bitfld.long 0x0 1. "ASAFE_1_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_1_si_pend" "0,1" newline bitfld.long 0x0 0. "ASAFE_0_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_0_si_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CTL_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CTL_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 4. "V2A_EDC_CTRL_PEND,Interrupt Pending Status for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 3. "ASAFE_3_SI_PEND,Interrupt Pending Status for asafe_3_si_pend" "0,1" newline bitfld.long 0x4 2. "ASAFE_2_SI_PEND,Interrupt Pending Status for asafe_2_si_pend" "0,1" newline bitfld.long 0x4 1. "ASAFE_1_SI_PEND,Interrupt Pending Status for asafe_1_si_pend" "0,1" newline bitfld.long 0x4 0. "ASAFE_0_SI_PEND,Interrupt Pending Status for asafe_0_si_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CTL_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 4. "V2A_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 3. "ASAFE_3_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_3_si_pend" "0,1" newline bitfld.long 0x0 2. "ASAFE_2_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_2_si_pend" "0,1" newline bitfld.long 0x0 1. "ASAFE_1_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_1_si_pend" "0,1" newline bitfld.long 0x0 0. "ASAFE_0_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_0_si_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CTL_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 4. "V2A_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 3. "ASAFE_3_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_3_si_pend" "0,1" newline bitfld.long 0x0 2. "ASAFE_2_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_2_si_pend" "0,1" newline bitfld.long 0x0 1. "ASAFE_1_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_1_si_pend" "0,1" newline bitfld.long 0x0 0. "ASAFE_0_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_0_si_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CTL_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CTL_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CTL_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CTL_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_CFG_WRAP_0_DDR1_1_ECC_AGGR_VBUS (COMPUTE_CLUSTER0_CFG_WRAP_0_DDR1_1_ECC_AGGR_VBUS)" base ad:0x4D200B1000 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_VBUS_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_VBUS_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_VBUS_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_VBUS_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_VBUS_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_VBUS_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "VSAFE_SI_PEND,Interrupt Pending Status for vsafe_si_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_VBUS_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "VSAFE_SI_ENABLE_SET,Interrupt Enable Set Register for vsafe_si_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_VBUS_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "VSAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for vsafe_si_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_VBUS_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_VBUS_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "VSAFE_SI_PEND,Interrupt Pending Status for vsafe_si_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_VBUS_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "VSAFE_SI_ENABLE_SET,Interrupt Enable Set Register for vsafe_si_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_VBUS_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "VSAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for vsafe_si_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_VBUS_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_VBUS_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_VBUS_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_VBUS_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_CFG_WRAP_0_DDR1_1_ECC_AGGR_CFG (COMPUTE_CLUSTER0_CFG_WRAP_0_DDR1_1_ECC_AGGR_CFG)" base ad:0x4D200B1400 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x4 2. "DST_M2P_BUSECC_PEND,Interrupt Pending Status for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x4 1. "M2M_M2M_VBUSS_PEND,Interrupt Pending Status for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 0. "M2M_DST_VBUSS_PEND,Interrupt Pending Status for m2m_dst_vbuss_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x0 2. "DST_M2P_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 1. "M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_dst_vbuss_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x0 2. "DST_M2P_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 1. "M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_dst_vbuss_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x4 2. "DST_M2P_BUSECC_PEND,Interrupt Pending Status for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x4 1. "M2M_M2M_VBUSS_PEND,Interrupt Pending Status for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 0. "M2M_DST_VBUSS_PEND,Interrupt Pending Status for m2m_dst_vbuss_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x0 2. "DST_M2P_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 1. "M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_dst_vbuss_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x0 2. "DST_M2P_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 1. "M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_dst_vbuss_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_CFG_WRAP_0_ECC_AGGR (COMPUTE_CLUSTER0_CFG_WRAP_0_ECC_AGGR)" base ad:0x4D200C0000 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP_GICSS_ECC_AGGR__GIC_ECC_AGGR_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP_GICSS_ECC_AGGR__GIC_ECC_AGGR_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP_GICSS_ECC_AGGR__GIC_ECC_AGGR_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP_GICSS_ECC_AGGR__GIC_ECC_AGGR_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "__VBUSP_GICSS_ECC_AGGR__GIC_ECC_AGGR_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_GICSS_ECC_AGGR__GIC_ECC_AGGR_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 5. "GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for gic500ss_4_2_axi2vbusm_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 4. "RAMECC_PEND,Interrupt Pending Status for ramecc_pend" "0,1" newline bitfld.long 0x4 3. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1" newline bitfld.long 0x4 2. "LPI_RAMECC_PEND,Interrupt Pending Status for lpi_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "ITE_RAMECC_PEND,Interrupt Pending Status for ite_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "ICB_RAMECC_PEND,Interrupt Pending Status for icb_ramecc_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "__VBUSP_GICSS_ECC_AGGR__GIC_ECC_AGGR_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 5. "GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for gic500ss_4_2_axi2vbusm_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "RAMECC_ENABLE_SET,Interrupt Enable Set Register for ramecc_pend" "0,1" newline bitfld.long 0x0 3. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1" newline bitfld.long 0x0 2. "LPI_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lpi_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "ITE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for ite_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "ICB_RAMECC_ENABLE_SET,Interrupt Enable Set Register for icb_ramecc_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "__VBUSP_GICSS_ECC_AGGR__GIC_ECC_AGGR_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 5. "GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for gic500ss_4_2_axi2vbusm_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pend" "0,1" newline bitfld.long 0x0 3. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1" newline bitfld.long 0x0 2. "LPI_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lpi_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "ITE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ite_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "ICB_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for icb_ramecc_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "__VBUSP_GICSS_ECC_AGGR__GIC_ECC_AGGR_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_GICSS_ECC_AGGR__GIC_ECC_AGGR_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 5. "GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for gic500ss_4_2_axi2vbusm_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 4. "RAMECC_PEND,Interrupt Pending Status for ramecc_pend" "0,1" newline bitfld.long 0x4 3. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1" newline bitfld.long 0x4 2. "LPI_RAMECC_PEND,Interrupt Pending Status for lpi_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "ITE_RAMECC_PEND,Interrupt Pending Status for ite_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "ICB_RAMECC_PEND,Interrupt Pending Status for icb_ramecc_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "__VBUSP_GICSS_ECC_AGGR__GIC_ECC_AGGR_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 5. "GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for gic500ss_4_2_axi2vbusm_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "RAMECC_ENABLE_SET,Interrupt Enable Set Register for ramecc_pend" "0,1" newline bitfld.long 0x0 3. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1" newline bitfld.long 0x0 2. "LPI_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lpi_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "ITE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for ite_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "ICB_RAMECC_ENABLE_SET,Interrupt Enable Set Register for icb_ramecc_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "__VBUSP_GICSS_ECC_AGGR__GIC_ECC_AGGR_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 5. "GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for gic500ss_4_2_axi2vbusm_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pend" "0,1" newline bitfld.long 0x0 3. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1" newline bitfld.long 0x0 2. "LPI_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lpi_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "ITE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ite_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "ICB_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for icb_ramecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP_GICSS_ECC_AGGR__GIC_ECC_AGGR_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP_GICSS_ECC_AGGR__GIC_ECC_AGGR_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP_GICSS_ECC_AGGR__GIC_ECC_AGGR_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP_GICSS_ECC_AGGR__GIC_ECC_AGGR_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_CFG_WRAP_0_CC (COMPUTE_CLUSTER0_CFG_WRAP_0_CC)" base ad:0x4D21000000 rgroup.long 0x0++0x3 line.long 0x0 "CC_REGS_ARM_0_REV,ARM REVISION parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Scheme" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAX,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x100++0x3 line.long 0x0 "CC_REGS_ARM_0_PBIST_BISOR_CNTRL,ARM BISOR control register" bitfld.long 0x0 0. "CC_ARM0_DFT_SELF_REPAIR_MODE_OVERRIDE,bisor override for cpu0" "0,1" rgroup.long 0x200++0x3 line.long 0x0 "CC_REGS_CC_CNTRL,CC misc control register" bitfld.long 0x0 9. "DSP_5_DEBUG_CLKEN_OVERRIDE,DSP I0/I1 clock gate override. Can be used to override DSP I0/I1 clock enables for debug on all instances. This bit has to set before AC71 powerup. 1 - Override I0/I1 clock enable on all DSP instances in compute cluster." "?,1: Override I0/I1 clock enable on all DSP instances.." newline bitfld.long 0x0 8. "DSP_4_DEBUG_CLKEN_OVERRIDE,DSP I0/I1 clock gate override. Can be used to override DSP I0/I1 clock enables for debug on all instances. This bit has to set before AC71 powerup. 1 - Override I0/I1 clock enable on all DSP instances in compute cluster." "?,1: Override I0/I1 clock enable on all DSP instances.." newline bitfld.long 0x0 0.--1. "DRU_CTSET_SEL,DRU ctset mux control. 00 - DRU0 ctset and CMMU events are connected to debug_wrap hwdbg event. 01 - DRU1 ctset and CMMU events are connected to debug_wrap hwdbg event. 10 - Unused. 11 - Unused" "0: DRU0 ctset and CMMU events are connected to..,1: DRU1 ctset and CMMU events are connected to..,?,?" tree.end endif tree.end tree "COMPUTE_CLUSTER0_DDR32SS" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_DDR32SS_16FFC_EW_BRCTL_SC_ECC_AGGR_CFG_0_DDR0_0_ECC_AGGR_CFG (COMPUTE_CLUSTER0_DDR32SS_16FFC_EW_BRCTL_SC_ECC_AGGR_CFG_0_DDR0_0_ECC_AGGR_CFG)" base ad:0x4D200B0800 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x4 2. "DST_M2P_BUSECC_PEND,Interrupt Pending Status for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x4 1. "M2M_M2M_VBUSS_PEND,Interrupt Pending Status for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 0. "M2M_DST_VBUSS_PEND,Interrupt Pending Status for m2m_dst_vbuss_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x0 2. "DST_M2P_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 1. "M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_dst_vbuss_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x0 2. "DST_M2P_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 1. "M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_dst_vbuss_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x4 2. "DST_M2P_BUSECC_PEND,Interrupt Pending Status for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x4 1. "M2M_M2M_VBUSS_PEND,Interrupt Pending Status for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 0. "M2M_DST_VBUSS_PEND,Interrupt Pending Status for m2m_dst_vbuss_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x0 2. "DST_M2P_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 1. "M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_dst_vbuss_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x0 2. "DST_M2P_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 1. "M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_dst_vbuss_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CFG_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_DDR32SS_16FFC_EW_BRCTL_SC_ECC_AGGR_CFG_1_DDR1_1_ECC_AGGR_CFG (COMPUTE_CLUSTER0_DDR32SS_16FFC_EW_BRCTL_SC_ECC_AGGR_CFG_1_DDR1_1_ECC_AGGR_CFG)" base ad:0x4D200B1400 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x4 2. "DST_M2P_BUSECC_PEND,Interrupt Pending Status for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x4 1. "M2M_M2M_VBUSS_PEND,Interrupt Pending Status for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 0. "M2M_DST_VBUSS_PEND,Interrupt Pending Status for m2m_dst_vbuss_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x0 2. "DST_M2P_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 1. "M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_dst_vbuss_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x0 2. "DST_M2P_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 1. "M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_dst_vbuss_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x4 2. "DST_M2P_BUSECC_PEND,Interrupt Pending Status for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x4 1. "M2M_M2M_VBUSS_PEND,Interrupt Pending Status for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 0. "M2M_DST_VBUSS_PEND,Interrupt Pending Status for m2m_dst_vbuss_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x0 2. "DST_M2P_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 1. "M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_dst_vbuss_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_j7am_ddr_ew_wrap_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x0 2. "DST_M2P_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 1. "M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_dst_vbuss_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP_DDRSS1__DDRSS1_ECC_AGGR_CFG_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_DDR32SS_16FFC_EW_BRCTL_SC_ECC_AGGR_CTL_0_DDR0_0_ECC_AGGR_CTL (COMPUTE_CLUSTER0_DDR32SS_16FFC_EW_BRCTL_SC_ECC_AGGR_CTL_0_DDR0_0_ECC_AGGR_CTL)" base ad:0x4D200B0000 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 4. "V2A_EDC_CTRL_PEND,Interrupt Pending Status for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 3. "ASAFE_3_SI_PEND,Interrupt Pending Status for asafe_3_si_pend" "0,1" newline bitfld.long 0x4 2. "ASAFE_2_SI_PEND,Interrupt Pending Status for asafe_2_si_pend" "0,1" newline bitfld.long 0x4 1. "ASAFE_1_SI_PEND,Interrupt Pending Status for asafe_1_si_pend" "0,1" newline bitfld.long 0x4 0. "ASAFE_0_SI_PEND,Interrupt Pending Status for asafe_0_si_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 4. "V2A_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 3. "ASAFE_3_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_3_si_pend" "0,1" newline bitfld.long 0x0 2. "ASAFE_2_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_2_si_pend" "0,1" newline bitfld.long 0x0 1. "ASAFE_1_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_1_si_pend" "0,1" newline bitfld.long 0x0 0. "ASAFE_0_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_0_si_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 4. "V2A_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 3. "ASAFE_3_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_3_si_pend" "0,1" newline bitfld.long 0x0 2. "ASAFE_2_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_2_si_pend" "0,1" newline bitfld.long 0x0 1. "ASAFE_1_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_1_si_pend" "0,1" newline bitfld.long 0x0 0. "ASAFE_0_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_0_si_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 4. "V2A_EDC_CTRL_PEND,Interrupt Pending Status for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 3. "ASAFE_3_SI_PEND,Interrupt Pending Status for asafe_3_si_pend" "0,1" newline bitfld.long 0x4 2. "ASAFE_2_SI_PEND,Interrupt Pending Status for asafe_2_si_pend" "0,1" newline bitfld.long 0x4 1. "ASAFE_1_SI_PEND,Interrupt Pending Status for asafe_1_si_pend" "0,1" newline bitfld.long 0x4 0. "ASAFE_0_SI_PEND,Interrupt Pending Status for asafe_0_si_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 4. "V2A_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 3. "ASAFE_3_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_3_si_pend" "0,1" newline bitfld.long 0x0 2. "ASAFE_2_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_2_si_pend" "0,1" newline bitfld.long 0x0 1. "ASAFE_1_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_1_si_pend" "0,1" newline bitfld.long 0x0 0. "ASAFE_0_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_0_si_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 5. "J7AM_DDR_EW_WRAP_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_ddr_ew_wrap_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 4. "V2A_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 3. "ASAFE_3_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_3_si_pend" "0,1" newline bitfld.long 0x0 2. "ASAFE_2_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_2_si_pend" "0,1" newline bitfld.long 0x0 1. "ASAFE_1_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_1_si_pend" "0,1" newline bitfld.long 0x0 0. "ASAFE_0_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_0_si_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_CTL_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_DDR32SS_16FFC_EW_BRCTL_SC_ECC_AGGR_VBUS_0_DDR0_0_ECC_AGGR_VBUS (COMPUTE_CLUSTER0_DDR32SS_16FFC_EW_BRCTL_SC_ECC_AGGR_VBUS_0_DDR0_0_ECC_AGGR_VBUS)" base ad:0x4D200B0400 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "VSAFE_SI_PEND,Interrupt Pending Status for vsafe_si_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "VSAFE_SI_ENABLE_SET,Interrupt Enable Set Register for vsafe_si_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "VSAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for vsafe_si_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "VSAFE_SI_PEND,Interrupt Pending Status for vsafe_si_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "VSAFE_SI_ENABLE_SET,Interrupt Enable Set Register for vsafe_si_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "VSAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for vsafe_si_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP_DDRSS0__DDRSS0_ECC_AGGR_VBUS_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif tree.end tree "COMPUTE_CLUSTER0_DRU" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU (COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU)" base ad:0x6D000000 rgroup.quad 0x0++0xF line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_dru_pid,Peripheral ID Register" bitfld.quad 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.quad 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.quad.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.quad.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.quad 0x8 "MMR__DRU0_MMR_CFG__DRU_dru_capabilities,DRU Capabilities: Lists the capabilities of the channel for TR TYPE and formatting functions" bitfld.quad 0x8 48. "VCOMP," "0,1" bitfld.quad 0x8 47. "ACOMP," "0,1" hexmask.quad.byte 0x8 43.--46. 1. "SECTR,Maximum second TR function that is supported" hexmask.quad.byte 0x8 39.--42. 1. "DFMT,Maximum data reformatting function that is supported" hexmask.quad.byte 0x8 35.--38. 1. "ELTYPE,Maximum element type value that is supported" newline bitfld.quad 0x8 32.--34. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1,2,3,4,5,6,7" hexmask.quad.word 0x8 20.--31. 1. "RSVD_CONF_SPEC,Reserved for Configuration Specific Features. This implementation has no configuration specific features." bitfld.quad 0x8 19. "GLOBAL_TRIG,Global Triggers 0 and 1 are supported" "0,1" bitfld.quad 0x8 18. "LOCAL_TRIG,Dedicated Local Trigger is supported" "0,1" bitfld.quad 0x8 17. "EOL,EOL Field is supported" "0,1" newline bitfld.quad 0x8 16. "TRSTATIC,STATIC Field is supported" "0,1" bitfld.quad 0x8 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.quad 0x8 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.quad 0x8 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.quad 0x8 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.quad 0x8 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.quad 0x8 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.quad 0x8 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.quad 0x8 8. "TYPE8,Type 8 TR is supported" "0,1" bitfld.quad 0x8 7. "TYPE7,Type 7 TR is supported" "0,1" newline bitfld.quad 0x8 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.quad 0x8 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.quad 0x8 4. "TYPE4,Type 4 TR is supported" "0,1" bitfld.quad 0x8 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.quad 0x8 2. "TYPE2,Type 2 TR is supported" "0,1" newline bitfld.quad 0x8 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.quad 0x8 0. "TYPE0,Type 0 TR is supported" "0,1" rgroup.quad 0x40++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_dru_pri_mask0,DRU Priority Masks: Enables locking a buffer to be used only by the priority queues" bitfld.quad 0x0 63. "MASK63,Buffer 63 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 62. "MASK62,Buffer 62 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 61. "MASK61,Buffer 61 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 60. "MASK60,Buffer 60 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 59. "MASK59,Buffer 59 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 58. "MASK58,Buffer 58 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 57. "MASK57,Buffer 57 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 56. "MASK56,Buffer 56 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 55. "MASK55,Buffer 55 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 54. "MASK54,Buffer 54 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 53. "MASK53,Buffer 53 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 52. "MASK52,Buffer 52 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 51. "MASK51,Buffer 51 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 50. "MASK50,Buffer 50 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 49. "MASK49,Buffer 49 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 48. "MASK48,Buffer 48 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 47. "MASK47,Buffer 47 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 46. "MASK46,Buffer 46 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 45. "MASK45,Buffer 45 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 44. "MASK44,Buffer 44 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 43. "MASK43,Buffer 43 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 42. "MASK42,Buffer 42 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 41. "MASK41,Buffer 41 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 40. "MASK40,Buffer 40 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 39. "MASK39,Buffer 39 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 38. "MASK38,Buffer 38 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 37. "MASK37,Buffer 37 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 36. "MASK36,Buffer 36 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 35. "MASK35,Buffer 35 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 34. "MASK34,Buffer 34 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 33. "MASK33,Buffer 33 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 32. "MASK32,Buffer 32 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 31. "MASK31,Buffer 31 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 30. "MASK30,Buffer 30 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 29. "MASK29,Buffer 29 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 28. "MASK28,Buffer 28 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 27. "MASK27,Buffer 27 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 26. "MASK26,Buffer 26 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 25. "MASK25,Buffer 25 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 24. "MASK24,Buffer 24 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 23. "MASK23,Buffer 23 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 22. "MASK22,Buffer 22 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 21. "MASK21,Buffer 21 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 20. "MASK20,Buffer 20 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 19. "MASK19,Buffer 19 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 18. "MASK18,Buffer 18 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 17. "MASK17,Buffer 17 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 16. "MASK16,Buffer 16 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 15. "MASK15,Buffer 15 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 14. "MASK14,Buffer 14 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 13. "MASK13,Buffer 13 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 12. "MASK12,Buffer 12 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 11. "MASK11,Buffer 11 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 10. "MASK10,Buffer 10 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 9. "MASK9,Buffer 9 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 8. "MASK8,Buffer 8 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 7. "MASK7,Buffer 7 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 6. "MASK6,Buffer 6 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 5. "MASK5,Buffer 5 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 4. "MASK4,Buffer 4 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 3. "MASK3,Buffer 3 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 2. "MASK2,Buffer 2 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 1. "MASK1,Buffer 1 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 0. "MASK0,Buffer 0 can only be used by the Priority queue if set to 1." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU_SET (COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU_SET)" base ad:0x6D004000 rgroup.quad 0x0++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_SET_dru_shared_evt_set,DRU Shared Event Set Register" bitfld.quad 0x0 0. "PROT_ERR,Set the Prot Error event" "0,1" rgroup.quad 0x40++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_SET_dru_comp_evt_set0,DRU Completion Event Set Register" bitfld.quad 0x0 31. "COMP_EVT31,Set the Completion Event for channel 31" "0,1" bitfld.quad 0x0 30. "COMP_EVT30,Set the Completion Event for channel 30" "0,1" bitfld.quad 0x0 29. "COMP_EVT29,Set the Completion Event for channel 29" "0,1" bitfld.quad 0x0 28. "COMP_EVT28,Set the Completion Event for channel 28" "0,1" bitfld.quad 0x0 27. "COMP_EVT27,Set the Completion Event for channel 27" "0,1" bitfld.quad 0x0 26. "COMP_EVT26,Set the Completion Event for channel 26" "0,1" newline bitfld.quad 0x0 25. "COMP_EVT25,Set the Completion Event for channel 25" "0,1" bitfld.quad 0x0 24. "COMP_EVT24,Set the Completion Event for channel 24" "0,1" bitfld.quad 0x0 23. "COMP_EVT23,Set the Completion Event for channel 23" "0,1" bitfld.quad 0x0 22. "COMP_EVT22,Set the Completion Event for channel 22" "0,1" bitfld.quad 0x0 21. "COMP_EVT21,Set the Completion Event for channel 21" "0,1" bitfld.quad 0x0 20. "COMP_EVT20,Set the Completion Event for channel 20" "0,1" newline bitfld.quad 0x0 19. "COMP_EVT19,Set the Completion Event for channel 19" "0,1" bitfld.quad 0x0 18. "COMP_EVT18,Set the Completion Event for channel 18" "0,1" bitfld.quad 0x0 17. "COMP_EVT17,Set the Completion Event for channel 17" "0,1" bitfld.quad 0x0 16. "COMP_EVT16,Set the Completion Event for channel 16" "0,1" bitfld.quad 0x0 15. "COMP_EVT15,Set the Completion Event for channel 15" "0,1" bitfld.quad 0x0 14. "COMP_EVT14,Set the Completion Event for channel 14" "0,1" newline bitfld.quad 0x0 13. "COMP_EVT13,Set the Completion Event for channel 13" "0,1" bitfld.quad 0x0 12. "COMP_EVT12,Set the Completion Event for channel 12" "0,1" bitfld.quad 0x0 11. "COMP_EVT11,Set the Completion Event for channel 11" "0,1" bitfld.quad 0x0 10. "COMP_EVT10,Set the Completion Event for channel 10" "0,1" bitfld.quad 0x0 9. "COMP_EVT9,Set the Completion Event for channel 9" "0,1" bitfld.quad 0x0 8. "COMP_EVT8,Set the Completion Event for channel 8" "0,1" newline bitfld.quad 0x0 7. "COMP_EVT7,Set the Completion Event for channel 7" "0,1" bitfld.quad 0x0 6. "COMP_EVT6,Set the Completion Event for channel 6" "0,1" bitfld.quad 0x0 5. "COMP_EVT5,Set the Completion Event for channel 5" "0,1" bitfld.quad 0x0 4. "COMP_EVT4,Set the Completion Event for channel 4" "0,1" bitfld.quad 0x0 3. "COMP_EVT3,Set the Completion Event for channel 3" "0,1" bitfld.quad 0x0 2. "COMP_EVT2,Set the Completion Event for channel 2" "0,1" newline bitfld.quad 0x0 1. "COMP_EVT1,Set the Completion Event for channel 1" "0,1" bitfld.quad 0x0 0. "COMP_EVT0,Set the Completion Event for channel 0" "0,1" rgroup.quad 0x80++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_SET_dru_err_evt_set0,DRU Error Event Set Register" bitfld.quad 0x0 31. "ERR_EVT31,Set the Error Event for channel 31" "0,1" bitfld.quad 0x0 30. "ERR_EVT30,Set the Error Event for channel 30" "0,1" bitfld.quad 0x0 29. "ERR_EVT29,Set the Error Event for channel 29" "0,1" bitfld.quad 0x0 28. "ERR_EVT28,Set the Error Event for channel 28" "0,1" bitfld.quad 0x0 27. "ERR_EVT27,Set the Error Event for channel 27" "0,1" bitfld.quad 0x0 26. "ERR_EVT26,Set the Error Event for channel 26" "0,1" newline bitfld.quad 0x0 25. "ERR_EVT25,Set the Error Event for channel 25" "0,1" bitfld.quad 0x0 24. "ERR_EVT24,Set the Error Event for channel 24" "0,1" bitfld.quad 0x0 23. "ERR_EVT23,Set the Error Event for channel 23" "0,1" bitfld.quad 0x0 22. "ERR_EVT22,Set the Error Event for channel 22" "0,1" bitfld.quad 0x0 21. "ERR_EVT21,Set the Error Event for channel 21" "0,1" bitfld.quad 0x0 20. "ERR_EVT20,Set the Error Event for channel 20" "0,1" newline bitfld.quad 0x0 19. "ERR_EVT19,Set the Error Event for channel 19" "0,1" bitfld.quad 0x0 18. "ERR_EVT18,Set the Error Event for channel 18" "0,1" bitfld.quad 0x0 17. "ERR_EVT17,Set the Error Event for channel 17" "0,1" bitfld.quad 0x0 16. "ERR_EVT16,Set the Error Event for channel 16" "0,1" bitfld.quad 0x0 15. "ERR_EVT15,Set the Error Event for channel 15" "0,1" bitfld.quad 0x0 14. "ERR_EVT14,Set the Error Event for channel 14" "0,1" newline bitfld.quad 0x0 13. "ERR_EVT13,Set the Error Event for channel 13" "0,1" bitfld.quad 0x0 12. "ERR_EVT12,Set the Error Event for channel 12" "0,1" bitfld.quad 0x0 11. "ERR_EVT11,Set the Error Event for channel 11" "0,1" bitfld.quad 0x0 10. "ERR_EVT10,Set the Error Event for channel 10" "0,1" bitfld.quad 0x0 9. "ERR_EVT9,Set the Error Event for channel 9" "0,1" bitfld.quad 0x0 8. "ERR_EVT8,Set the Error Event for channel 8" "0,1" newline bitfld.quad 0x0 7. "ERR_EVT7,Set the Error Event for channel 7" "0,1" bitfld.quad 0x0 6. "ERR_EVT6,Set the Error Event for channel 6" "0,1" bitfld.quad 0x0 5. "ERR_EVT5,Set the Error Event for channel 5" "0,1" bitfld.quad 0x0 4. "ERR_EVT4,Set the Error Event for channel 4" "0,1" bitfld.quad 0x0 3. "ERR_EVT3,Set the Error Event for channel 3" "0,1" bitfld.quad 0x0 2. "ERR_EVT2,Set the Error Event for channel 2" "0,1" newline bitfld.quad 0x0 1. "ERR_EVT1,Set the Error Event for channel 1" "0,1" bitfld.quad 0x0 0. "ERR_EVT0,Set the Error Event for channel 0" "0,1" rgroup.quad 0xC0++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_SET_dru_local_evt_set0,DRU Local Event Set Register" bitfld.quad 0x0 31. "COMP_EVT31,Set the Local Event for channel 31" "0,1" bitfld.quad 0x0 30. "COMP_EVT30,Set the Local Event for channel 30" "0,1" bitfld.quad 0x0 29. "COMP_EVT29,Set the Local Event for channel 29" "0,1" bitfld.quad 0x0 28. "COMP_EVT28,Set the Local Event for channel 28" "0,1" bitfld.quad 0x0 27. "COMP_EVT27,Set the Local Event for channel 27" "0,1" bitfld.quad 0x0 26. "COMP_EVT26,Set the Local Event for channel 26" "0,1" newline bitfld.quad 0x0 25. "COMP_EVT25,Set the Local Event for channel 25" "0,1" bitfld.quad 0x0 24. "COMP_EVT24,Set the Local Event for channel 24" "0,1" bitfld.quad 0x0 23. "COMP_EVT23,Set the Local Event for channel 23" "0,1" bitfld.quad 0x0 22. "COMP_EVT22,Set the Local Event for channel 22" "0,1" bitfld.quad 0x0 21. "COMP_EVT21,Set the Local Event for channel 21" "0,1" bitfld.quad 0x0 20. "COMP_EVT20,Set the Local Event for channel 20" "0,1" newline bitfld.quad 0x0 19. "COMP_EVT19,Set the Local Event for channel 19" "0,1" bitfld.quad 0x0 18. "COMP_EVT18,Set the Local Event for channel 18" "0,1" bitfld.quad 0x0 17. "COMP_EVT17,Set the Local Event for channel 17" "0,1" bitfld.quad 0x0 16. "COMP_EVT16,Set the Local Event for channel 16" "0,1" bitfld.quad 0x0 15. "COMP_EVT15,Set the Local Event for channel 15" "0,1" bitfld.quad 0x0 14. "COMP_EVT14,Set the Local Event for channel 14" "0,1" newline bitfld.quad 0x0 13. "COMP_EVT13,Set the Local Event for channel 13" "0,1" bitfld.quad 0x0 12. "COMP_EVT12,Set the Local Event for channel 12" "0,1" bitfld.quad 0x0 11. "COMP_EVT11,Set the Local Event for channel 11" "0,1" bitfld.quad 0x0 10. "COMP_EVT10,Set the Local Event for channel 10" "0,1" bitfld.quad 0x0 9. "COMP_EVT9,Set the Local Event for channel 9" "0,1" bitfld.quad 0x0 8. "COMP_EVT8,Set the Local Event for channel 8" "0,1" newline bitfld.quad 0x0 7. "COMP_EVT7,Set the Local Event for channel 7" "0,1" bitfld.quad 0x0 6. "COMP_EVT6,Set the Local Event for channel 6" "0,1" bitfld.quad 0x0 5. "COMP_EVT5,Set the Local Event for channel 5" "0,1" bitfld.quad 0x0 4. "COMP_EVT4,Set the Local Event for channel 4" "0,1" bitfld.quad 0x0 3. "COMP_EVT3,Set the Local Event for channel 3" "0,1" bitfld.quad 0x0 2. "COMP_EVT2,Set the Local Event for channel 2" "0,1" newline bitfld.quad 0x0 1. "COMP_EVT1,Set the Local Event for channel 1" "0,1" bitfld.quad 0x0 0. "COMP_EVT0,Set the Local Event for channel 0" "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU_QUEUE (COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU_QUEUE)" base ad:0x6D008000 rgroup.quad 0x0++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_QUEUE_cfg,Configuration Register for Queue 0" hexmask.quad.long 0x0 32.--63. 1. "RSVD,Reserved." hexmask.quad.byte 0x0 24.--31. 1. "REARB_WAIT,This is the number of commands that will be sent by other queues before allowing the queue to arbitrate again for the right to send commands. This is only started when a queue exhausted its consecutive trans count." hexmask.quad.byte 0x0 16.--23. 1. "CONSECUTIVE_TRANS,This is the number of consecutive transactions that will be sent before allowing another queue of equal level to arbitrate to send commands. This is the maximum number of commands that it can send. If the queue has any delays such as.." bitfld.quad 0x0 8.--10. "QOS,This configures the QOS for QUEUE0. This should only be set for fixed priority queues and the lower queue should have the lower QoS." "0,1,2,3,4,5,6,7" newline hexmask.quad.byte 0x0 4.--7. 1. "ORDERID,This configures the orderid for QUEUE0." bitfld.quad 0x0 0.--2. "PRI,This configures the priority for QUEUE0. This will be the priority that will be presented on the External bus for all commands from this queue." "0,1,2,3,4,5,6,7" rgroup.quad 0x40++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_QUEUE_status,Status Register for Queue 0" hexmask.quad.word 0x0 27.--35. 1. "RD_TOTAL,This is the channel that the read half is currently working on." hexmask.quad.word 0x0 18.--26. 1. "RD_TOP,This is the channel that the read half is currently working on." hexmask.quad.word 0x0 9.--17. 1. "WR_TOTAL,This is the channel that the read half is currently working on." hexmask.quad.word 0x0 0.--8. 1. "WR_TOP,This is the channel that the write half is currently working on." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU_MMU (COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU_MMU)" base ad:0x6D00A000 rgroup.quad 0x0++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_MMU_PID,Reserved" bitfld.quad 0x0 30.--31. "SCHEME,PID naming scheme" "0,1,2,3" bitfld.quad 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.quad.word 0x0 16.--27. 1. "FUNC,MMU Function code" newline hexmask.quad.byte 0x0 11.--15. 1. "R,Minor Revision" bitfld.quad 0x0 8.--10. "X,Architecture Revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Reuseable/Custom" "0,1,2,3" newline hexmask.quad.byte 0x0 0.--5. 1. "Y,Configuration Revision" rgroup.quad 0x100++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_TDRR,Translation Completion Bit" hexmask.quad.byte 0x0 57.--62. 1. "RSVD0,Reserved" bitfld.quad 0x0 56. "PREF,Prefetchable" "0,1" bitfld.quad 0x0 54.--55. "OUTER,Outer Cacheability" "0,1,2,3" newline bitfld.quad 0x0 52.--53. "INNER,Inner Cacheability" "0,1,2,3" bitfld.quad 0x0 50.--51. "MEMTYPE,Memory Type" "0,1,2,3" bitfld.quad 0x0 48.--49. "SHARE,Shareability" "0,1,2,3" newline hexmask.quad.byte 0x0 40.--47. 1. "RSVD1,Reserved" hexmask.quad.long 0x0 12.--39. 1. "ADDR,Output Address Faulting Stage-2 IPA" hexmask.quad.word 0x0 0.--11. 1. "STATUS,Translation Response Status" rgroup.quad 0x140++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_TDFAR,Faulted Input Address" rgroup.quad 0x200++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_TLB_INV,Reserved" hexmask.quad.byte 0x0 48.--55. 1. "ID,ASID Value" hexmask.quad.byte 0x0 43.--47. 1. "RSVD1,Reserved" bitfld.quad 0x0 40.--42. "INV_TYPE,Invalidation Type" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x0 39. "ASID,ASID Match" "0,1" bitfld.quad 0x0 38. "VA,VA Match" "0,1" bitfld.quad 0x0 37. "LL,Last Level Only" "0,1" newline hexmask.quad 0x0 0.--36. 1. "ADDR,VA/IPA" rgroup.quad 0x280++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_TLB_INVC,Reserved" bitfld.quad 0x0 0. "COMP,Invalidation Completed" "0,1" rgroup.quad 0x2C0++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_TLB_DBG,Reserved" bitfld.quad 0x0 16.--17. "TLB,TLB Type" "0,1,2,3" rbitfld.quad 0x0 14.--15. "RSVD1,Reserved" "0,1,2,3" bitfld.quad 0x0 12.--13. "WAY,Way" "0,1,2,3" newline hexmask.quad.byte 0x0 7.--11. 1. "RSVD2,Reserved" hexmask.quad.byte 0x0 0.--6. 1. "INDEX,Index" rgroup.quad 0x300++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_TLB_DBG_DATA0,Non-Secure Page. NSTable accumulation" hexmask.quad.byte 0x0 59.--62. 1. "DS_SIZE,Descriptor Size" bitfld.quad 0x0 58. "DS_TYPE,Descriptor Type" "0,1" hexmask.quad.long 0x0 28.--57. 1. "IADDR,Input Address" newline hexmask.quad.byte 0x0 20.--27. 1. "VMID,VMID" hexmask.quad.byte 0x0 12.--19. 1. "RSVD0,Reserved" hexmask.quad.byte 0x0 4.--11. 1. "ASID,ASID" newline bitfld.quad 0x0 3. "GBL,Global Page" "0,1" bitfld.quad 0x0 2. "ROOT,Root Context" "0,1" bitfld.quad 0x0 1. "SEC,Security Context" "0,1" newline bitfld.quad 0x0 0. "VALID,Valid Entry" "0,1" rgroup.quad 0x340++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_TLB_DBG_DATA1,Reserved" bitfld.quad 0x0 46.--47. "SHARE,Shareability" "0,1,2,3" bitfld.quad 0x0 44.--45. "S2_LVL,Stage 2 Level" "0,1,2,3" hexmask.quad.byte 0x0 40.--43. 1. "S2_MEM_TYPE,Stage 2 Memory Type" newline hexmask.quad.byte 0x0 36.--39. 1. "S2_PERM,S2 Access Permissions" bitfld.quad 0x0 33.--35. "S1_MEM_INDEX,Stage 1 Memory Attribute Index" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x0 28.--32. 1. "S1_PERM,Stage 1 Access Permissions" newline hexmask.quad.long 0x0 0.--27. 1. "OADDR,Output Address" rgroup.quad 0x400++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_SCR,HW Mode" hexmask.quad 0x0 8.--62. 1. "RSVD0,Reserved" bitfld.quad 0x0 7. "INSTC,Stage 1 Instruction Caching" "0,1" bitfld.quad 0x0 6. "DATAC,Stage 1 Data Caching" "0,1" newline bitfld.quad 0x0 5. "FAULT,Caching faults in uTLBs" "0,1" bitfld.quad 0x0 4. "ASEL,ASID Selection" "0,1" bitfld.quad 0x0 3. "WXN,Writeable memory Execute Never" "0,1" newline bitfld.quad 0x0 2. "ENDIAN1,Stage 1 Region 1 Endian" "0,1" bitfld.quad 0x0 1. "ENDIAN0,Stage 1 Region 0 Endian" "0,1" bitfld.quad 0x0 0. "S1_EN,Enable Stage 1 Address Translation" "0,1" rgroup.quad 0x440++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_TCR0,Reserved" bitfld.quad 0x0 15.--16. "MEMTYPE,Memory Type of Translation Table Walks" "0,1,2,3" bitfld.quad 0x0 13.--14. "COUTER,Outer Cacheability attribute of memory for Translation Table Walks" "0,1,2,3" bitfld.quad 0x0 11.--12. "CINNER,Inner Cacheability attribute of memory for Translation Table Walks" "0,1,2,3" newline bitfld.quad 0x0 9.--10. "SHARE,Shareability attribute of memory for Translation Table Walks" "0,1,2,3" bitfld.quad 0x0 7.--8. "GRANULE,Translation Table Page Granule Size" "0,1,2,3" hexmask.quad.byte 0x0 1.--6. 1. "TBL_SZ,Translation Table Region Size" newline bitfld.quad 0x0 0. "WALK_EN,Enable Translation Table Walks" "0,1" rgroup.quad 0x480++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_TCR1,Reserved" bitfld.quad 0x0 15.--16. "MEMTYPE,Memory Type of Translation Table Walks" "0,1,2,3" bitfld.quad 0x0 13.--14. "COUTER,Outer Cacheability attribute of memory for Translation Table Walks" "0,1,2,3" bitfld.quad 0x0 11.--12. "CINNER,Inner Cacheability attribute of memory for Translation Table Walks" "0,1,2,3" newline bitfld.quad 0x0 9.--10. "SHARE,Shareability attribute of memory for Translation Table Walks" "0,1,2,3" bitfld.quad 0x0 7.--8. "GRANULE,Translation Table Page Granule Size" "0,1,2,3" hexmask.quad.byte 0x0 1.--6. 1. "TBL_SZ,Translation Table Region Size" newline bitfld.quad 0x0 0. "WALK_EN,Enable Translation Table Walks" "0,1" rgroup.quad 0x4C0++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_TBR0,Reserved" hexmask.quad.byte 0x0 48.--55. 1. "ASID,Application Space ID" hexmask.quad.byte 0x0 40.--47. 1. "RSVD1,Reserved" hexmask.quad 0x0 0.--39. 1. "BADDR,Table Base Address" rgroup.quad 0x500++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_TBR1,Reserved" hexmask.quad.byte 0x0 48.--55. 1. "ASID,Application Space ID" hexmask.quad.byte 0x0 40.--47. 1. "RSVD1,Reserved" hexmask.quad 0x0 0.--39. 1. "BADDR,Table Base Address" rgroup.quad 0x540++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_MAR,Memory Attribute Index 7" hexmask.quad.byte 0x0 48.--55. 1. "ATTR6,Memory Attribute Index 6" hexmask.quad.byte 0x0 40.--47. 1. "ATTR5,Memory Attribute Index 5" hexmask.quad.byte 0x0 32.--39. 1. "ATTR4,Memory Attribute Index 4" newline hexmask.quad.byte 0x0 24.--31. 1. "ATTR3,Memory Attribute Index 3" hexmask.quad.byte 0x0 16.--23. 1. "ATTR2,Memory Attribute Index 2" hexmask.quad.byte 0x0 8.--15. 1. "ATTR1,Memory Attribute Index 1" newline hexmask.quad.byte 0x0 0.--7. 1. "ATTR0,Memory Attribute Index 0" rgroup.quad 0x580++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_TDAR,Input Address" bitfld.quad 0x0 3. "INTEREST,Interest Flag" "0,1" bitfld.quad 0x0 1.--2. "ACC_TYPE,Access Type" "0,1,2,3" bitfld.quad 0x0 0. "PRIV,Supervisor Access" "0,1" rgroup.quad 0x800++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_SCR_GS,HW Mode" hexmask.quad 0x0 8.--62. 1. "RSVD0,Reserved" bitfld.quad 0x0 7. "INSTC,Stage 1 Instruction Caching" "0,1" bitfld.quad 0x0 6. "DATAC,Stage 1 Data Caching" "0,1" newline bitfld.quad 0x0 5. "FAULT,Caching faults in uTLBs" "0,1" bitfld.quad 0x0 4. "ASEL,ASID Selection" "0,1" bitfld.quad 0x0 3. "WXN,Writeable memory Execute Never" "0,1" newline bitfld.quad 0x0 2. "ENDIAN1,Stage 1 Region 1 Endian" "0,1" bitfld.quad 0x0 1. "ENDIAN0,Stage 1 Region 0 Endian" "0,1" bitfld.quad 0x0 0. "S1_EN,Enable Stage 1 Address Translation" "0,1" rgroup.quad 0x840++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_TCR0_GS,Reserved" bitfld.quad 0x0 15.--16. "MEMTYPE,Memory Type of Translation Table Walks" "0,1,2,3" bitfld.quad 0x0 13.--14. "COUTER,Outer Cacheability attribute of memory for Translation Table Walks" "0,1,2,3" bitfld.quad 0x0 11.--12. "CINNER,Inner Cacheability attribute of memory for Translation Table Walks" "0,1,2,3" newline bitfld.quad 0x0 9.--10. "SHARE,Shareability attribute of memory for Translation Table Walks" "0,1,2,3" bitfld.quad 0x0 7.--8. "GRANULE,Translation Table Page Granule Size" "0,1,2,3" hexmask.quad.byte 0x0 1.--6. 1. "TBL_SZ,Translation Table Region Size" newline bitfld.quad 0x0 0. "WALK_EN,Enable Translation Table Walks" "0,1" rgroup.quad 0x880++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_TCR1_GS,Reserved" bitfld.quad 0x0 15.--16. "MEMTYPE,Memory Type of Translation Table Walks" "0,1,2,3" bitfld.quad 0x0 13.--14. "COUTER,Outer Cacheability attribute of memory for Translation Table Walks" "0,1,2,3" bitfld.quad 0x0 11.--12. "CINNER,Inner Cacheability attribute of memory for Translation Table Walks" "0,1,2,3" newline bitfld.quad 0x0 9.--10. "SHARE,Shareability attribute of memory for Translation Table Walks" "0,1,2,3" bitfld.quad 0x0 7.--8. "GRANULE,Translation Table Page Granule Size" "0,1,2,3" hexmask.quad.byte 0x0 1.--6. 1. "TBL_SZ,Translation Table Region Size" newline bitfld.quad 0x0 0. "WALK_EN,Enable Translation Table Walks" "0,1" rgroup.quad 0x8C0++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_TBR0_GS,Reserved" hexmask.quad.byte 0x0 48.--55. 1. "ASID,Application Space ID" hexmask.quad.byte 0x0 40.--47. 1. "RSVD1,Reserved" hexmask.quad 0x0 0.--39. 1. "BADDR,Table Base Address" rgroup.quad 0x900++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_TBR1_GS,Reserved" hexmask.quad.byte 0x0 48.--55. 1. "ASID,Application Space ID" hexmask.quad.byte 0x0 40.--47. 1. "RSVD1,Reserved" hexmask.quad 0x0 0.--39. 1. "BADDR,Table Base Address" rgroup.quad 0x940++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_MAR_GS,Memory Attribute Index 7" hexmask.quad.byte 0x0 48.--55. 1. "ATTR6,Memory Attribute Index 6" hexmask.quad.byte 0x0 40.--47. 1. "ATTR5,Memory Attribute Index 5" hexmask.quad.byte 0x0 32.--39. 1. "ATTR4,Memory Attribute Index 4" newline hexmask.quad.byte 0x0 24.--31. 1. "ATTR3,Memory Attribute Index 3" hexmask.quad.byte 0x0 16.--23. 1. "ATTR2,Memory Attribute Index 2" hexmask.quad.byte 0x0 8.--15. 1. "ATTR1,Memory Attribute Index 1" newline hexmask.quad.byte 0x0 0.--7. 1. "ATTR0,Memory Attribute Index 0" rgroup.quad 0x980++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_TDAR_GS,Input Address" bitfld.quad 0x0 3. "INTEREST,Interest Flag" "0,1" bitfld.quad 0x0 1.--2. "ACC_TYPE,Access Type" "0,1,2,3" bitfld.quad 0x0 0. "PRIV,Supervisor Access" "0,1" rgroup.quad 0xC00++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_SCR_S,HW Mode" hexmask.quad 0x0 8.--62. 1. "RSVD0,Reserved" bitfld.quad 0x0 7. "INSTC,Stage 1 Instruction Caching" "0,1" bitfld.quad 0x0 6. "DATAC,Stage 1 Data Caching" "0,1" newline bitfld.quad 0x0 5. "FAULT,Caching faults in uTLBs" "0,1" bitfld.quad 0x0 4. "ASEL,ASID Selection" "0,1" bitfld.quad 0x0 3. "WXN,Writeable memory Execute Never" "0,1" newline bitfld.quad 0x0 2. "ENDIAN1,Stage 1 Region 1 Endian" "0,1" bitfld.quad 0x0 1. "ENDIAN0,Stage 1 Region 0 Endian" "0,1" bitfld.quad 0x0 0. "S1_EN,Enable Stage 1 Address Translation" "0,1" rgroup.quad 0xC40++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_TCR0_S,Reserved" bitfld.quad 0x0 15.--16. "MEMTYPE,Memory Type of Translation Table Walks" "0,1,2,3" bitfld.quad 0x0 13.--14. "COUTER,Outer Cacheability attribute of memory for Translation Table Walks" "0,1,2,3" bitfld.quad 0x0 11.--12. "CINNER,Inner Cacheability attribute of memory for Translation Table Walks" "0,1,2,3" newline bitfld.quad 0x0 9.--10. "SHARE,Shareability attribute of memory for Translation Table Walks" "0,1,2,3" bitfld.quad 0x0 7.--8. "GRANULE,Translation Table Page Granule Size" "0,1,2,3" hexmask.quad.byte 0x0 1.--6. 1. "TBL_SZ,Translation Table Region Size" newline bitfld.quad 0x0 0. "WALK_EN,Enable Translation Table Walks" "0,1" rgroup.quad 0xC80++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_TCR1_S,Reserved" bitfld.quad 0x0 15.--16. "MEMTYPE,Memory Type of Translation Table Walks" "0,1,2,3" bitfld.quad 0x0 13.--14. "COUTER,Outer Cacheability attribute of memory for Translation Table Walks" "0,1,2,3" bitfld.quad 0x0 11.--12. "CINNER,Inner Cacheability attribute of memory for Translation Table Walks" "0,1,2,3" newline bitfld.quad 0x0 9.--10. "SHARE,Shareability attribute of memory for Translation Table Walks" "0,1,2,3" bitfld.quad 0x0 7.--8. "GRANULE,Translation Table Page Granule Size" "0,1,2,3" hexmask.quad.byte 0x0 1.--6. 1. "TBL_SZ,Translation Table Region Size" newline bitfld.quad 0x0 0. "WALK_EN,Enable Translation Table Walks" "0,1" rgroup.quad 0xCC0++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_TBR0_S,Reserved" hexmask.quad.byte 0x0 48.--55. 1. "ASID,Application Space ID" hexmask.quad.byte 0x0 40.--47. 1. "RSVD1,Reserved" hexmask.quad 0x0 0.--39. 1. "BADDR,Table Base Address" rgroup.quad 0xD00++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_TBR1_S,Reserved" hexmask.quad.byte 0x0 48.--55. 1. "ASID,Application Space ID" hexmask.quad.byte 0x0 40.--47. 1. "RSVD1,Reserved" hexmask.quad 0x0 0.--39. 1. "BADDR,Table Base Address" rgroup.quad 0xD40++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_MAR_S,Memory Attribute Index 7" hexmask.quad.byte 0x0 48.--55. 1. "ATTR6,Memory Attribute Index 6" hexmask.quad.byte 0x0 40.--47. 1. "ATTR5,Memory Attribute Index 5" hexmask.quad.byte 0x0 32.--39. 1. "ATTR4,Memory Attribute Index 4" newline hexmask.quad.byte 0x0 24.--31. 1. "ATTR3,Memory Attribute Index 3" hexmask.quad.byte 0x0 16.--23. 1. "ATTR2,Memory Attribute Index 2" hexmask.quad.byte 0x0 8.--15. 1. "ATTR1,Memory Attribute Index 1" newline hexmask.quad.byte 0x0 0.--7. 1. "ATTR0,Memory Attribute Index 0" rgroup.quad 0xD80++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_TDAR_S,Input Address" bitfld.quad 0x0 3. "INTEREST,Interest Flag" "0,1" bitfld.quad 0x0 1.--2. "ACC_TYPE,Access Type" "0,1,2,3" bitfld.quad 0x0 0. "PRIV,Supervisor Access" "0,1" rgroup.quad 0x1800++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_VCR,Reserved" bitfld.quad 0x0 5. "ID,Stage 2 Instruction Cache Disable" "0,1" bitfld.quad 0x0 4. "CD,Stage 2 Data Cache Disable" "0,1" bitfld.quad 0x0 3. "DC,Default Cacheable Mode" "0,1" newline bitfld.quad 0x0 2. "PROT,Protected Table Walk" "0,1" bitfld.quad 0x0 1. "ENDIAN,Stage 2 Endian" "0,1" bitfld.quad 0x0 0. "S2_EN,Enable Stage 2 Address Translation" "0,1" rgroup.quad 0x1840++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_VTCR,Reserved" bitfld.quad 0x0 17.--18. "SLEVEL,Stage 2 Starting Translation Level" "0,1,2,3" bitfld.quad 0x0 15.--16. "MEMTYPE,Memory Type of Translation Table Walks" "0,1,2,3" bitfld.quad 0x0 13.--14. "COUTER,Outer Cacheability attribute of memory for Translation Table Walks" "0,1,2,3" newline bitfld.quad 0x0 11.--12. "CINNER,Inner Cacheability attribute of memory for Translation Table Walks" "0,1,2,3" bitfld.quad 0x0 9.--10. "SHARE,Shareability attribute of memory for Translation Table Walks" "0,1,2,3" bitfld.quad 0x0 7.--8. "GRANULE,Translation Table Page Granule Size" "0,1,2,3" newline hexmask.quad.byte 0x0 1.--6. 1. "TBL_SZ,Translation Table Region Size" rbitfld.quad 0x0 0. "RSVD1,Reserved" "0,1" rgroup.quad 0x1880++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_VTBR,Reserved" hexmask.quad.byte 0x0 48.--55. 1. "VMID,Virtual Machine ID" hexmask.quad.byte 0x0 40.--47. 1. "RSVD1,Reserved" hexmask.quad 0x0 0.--39. 1. "BADDR,Table Base Address" rgroup.quad 0x18C0++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_MMU_VTDAR,Input Address" bitfld.quad 0x0 3. "INTEREST,Interest Flag" "0,1" bitfld.quad 0x0 1.--2. "ACC_TYPE,Access Type" "0,1,2,3" bitfld.quad 0x0 0. "PRIV,Supervisor Access" "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU_UTLB (COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU_UTLB)" base ad:0x6D00C000 rgroup.quad 0x0++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_UTLB_MATCH,Entry Valid" bitfld.quad 0x0 62. "SECURE,Secure Page" "0,1" bitfld.quad 0x0 61. "ROOT,Root Page" "0,1" bitfld.quad 0x0 60. "GBL,Global Page" "0,1" hexmask.quad.byte 0x0 52.--59. 1. "VMID,VMID" hexmask.quad.byte 0x0 44.--51. 1. "ASID,ASID" newline rbitfld.quad 0x0 43. "RSVD0,Reserved" "0,1" bitfld.quad 0x0 40.--42. "PG_SIZE,Page Size" "0,1,2,3,4,5,6,7" rbitfld.quad 0x0 37.--39. "RSVD1,Reserved" "0,1,2,3,4,5,6,7" hexmask.quad 0x0 0.--36. 1. "IADDR,Input Address" rgroup.quad 0x1000++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_UTLB_ATTR,Entry Valid" hexmask.quad.word 0x0 51.--62. 1. "STATUS,TLB Status" hexmask.quad.word 0x0 42.--50. 1. "ACC_PERM,Access Permissions" bitfld.quad 0x0 41. "PG_NSEC,Page Non-Secure" "0,1" hexmask.quad.word 0x0 32.--40. 1. "MEMTYPE,Page Memory Type" hexmask.quad.byte 0x0 28.--31. 1. "RSVD0,Reserved" newline hexmask.quad.long 0x0 0.--27. 1. "OADDR,Output Address" rgroup.quad 0x2000++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_UTLB_MATCH,Entry Valid" bitfld.quad 0x0 62. "SECURE,Secure Page" "0,1" bitfld.quad 0x0 61. "ROOT,Root Page" "0,1" bitfld.quad 0x0 60. "GBL,Global Page" "0,1" hexmask.quad.byte 0x0 52.--59. 1. "VMID,VMID" hexmask.quad.byte 0x0 44.--51. 1. "ASID,ASID" newline rbitfld.quad 0x0 43. "RSVD0,Reserved" "0,1" bitfld.quad 0x0 40.--42. "PG_SIZE,Page Size" "0,1,2,3,4,5,6,7" rbitfld.quad 0x0 37.--39. "RSVD1,Reserved" "0,1,2,3,4,5,6,7" hexmask.quad 0x0 0.--36. 1. "IADDR,Input Address" rgroup.quad 0x3000++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_UTLB_ATTR,Entry Valid" hexmask.quad.word 0x0 51.--62. 1. "STATUS,TLB Status" hexmask.quad.word 0x0 42.--50. 1. "ACC_PERM,Access Permissions" bitfld.quad 0x0 41. "PG_NSEC,Page Non-Secure" "0,1" hexmask.quad.word 0x0 32.--40. 1. "MEMTYPE,Page Memory Type" hexmask.quad.byte 0x0 28.--31. 1. "RSVD0,Reserved" newline hexmask.quad.long 0x0 0.--27. 1. "OADDR,Output Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU_CHNRT (COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU_CHNRT)" base ad:0x6D040000 rgroup.quad 0x0++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_CHNRT_cfg,Channel Configuration Register. The Channel Configuration Register is used to initialize static mode settings for the DMA Channel. The register may only be written when the chanel is disable in the ch_enable field in the.." bitfld.quad 0x0 31. "PAUSE_ON_ERR,Pause on Error. This field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW to.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.quad 0x0 25. "ATYPE,Address type. This field controls how the pointers are interpreted for TRs on this channel. This field is encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are virtual addresses which require virtual to physical translation.." "0: Pointers are physical addresses,1: Pointers are virtual addresses which require.." newline bitfld.quad 0x0 19. "CHAN_TYPE_OWNER,This field controls how the TR is received by the UTC. If it is 0 then the SUBMISSION registers must be written to submit it. If it is a 1 then the TR will be received through PSIL." "0,1" newline rbitfld.quad 0x0 16.--18. "CHAN_TYPE,This field states the TR type that is being used it along with CHAN_TYPE_OWNER field make up the 4 bit CHAN_TYPE for a KS3 DMA UTC. The value of this is all zeroes. To reflect that the UTC DRU only does TRs through pass by value mechanisms." "0,1,2,3,4,5,6,7" rgroup.quad 0x20++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_CHNRT_choes0,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the.." hexmask.quad.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated." rgroup.quad 0x60++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_CHNRT_chst_sched,Channel Static Scheduler Config Register" bitfld.quad 0x0 0.--2. "QUEUE,This is the queue number that is written" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU_CHRT (COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU_CHRT)" base ad:0x6D060000 rgroup.quad 0x0++0xF line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_CHRT_chrt_ctl,The channel realtime control register contains real-time cotrol and status information for the DMA Channel. The fields in this regsiter can be changed while the channel is in operation." bitfld.quad 0x0 31. "ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared.." bitfld.quad 0x0 30. "TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" newline bitfld.quad 0x0 29. "PAUSE,Channel pause: Setting this bit will request the channel to pause processing at the next packet boundary. This is a more graceful method of halting processing than disabling the channel as it will not allow any current packets to underflow." "0,1" bitfld.quad 0x0 28. "FORCED_TEARDOWN,Channel forced teardown: Setting this bit will request the channel to be torn down forcefulyy. This field will clear after a channel teardown is complete." "0,1" line.quad 0x8 "MMR__DRU0_MMR_CFG__DRU_CHRT_chrt_swtrig,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way." bitfld.quad 0x8 2. "LOCAL_TRIGGER0,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel. This will trigger LOCAL Event" "0,1" bitfld.quad 0x8 1. "GLOBAL_TRIGGER1,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel. This will trigger Global Event 1" "0,1" newline bitfld.quad 0x8 0. "GLOBAL_TRIGGER0,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel. This will trigger Global Event 0" "0,1" rgroup.quad 0x10++0xF line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_CHRT_chrt_status_det,The channel status details" hexmask.quad.byte 0x0 8.--15. 1. "CMD_ID,The last cmd_id given to the write queue" hexmask.quad.byte 0x0 4.--7. 1. "INFO,The info of the error that was received" newline hexmask.quad.byte 0x0 0.--3. 1. "STATUS_TYPE,The type of error that was received" line.quad 0x8 "MMR__DRU0_MMR_CFG__DRU_CHRT_chrt_status_cnt,The channel count details" hexmask.quad.word 0x8 48.--63. 1. "ICNT3,The last icnt3 given to the write queue" hexmask.quad.word 0x8 32.--47. 1. "ICNT2,The last icnt2 given to the write queue" newline hexmask.quad.word 0x8 16.--31. 1. "ICNT1,The last icnt1 given to the write queue" hexmask.quad.word 0x8 0.--15. 1. "ICNT0,The last icnt0 given to the write queue" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU_CHCORE (COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU_CHCORE)" base ad:0x6D0A0000 rgroup.quad 0x0++0x3F line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_CHCORE_submit_word0_1,The first TR submission word" hexmask.quad.word 0x0 48.--63. 1. "ICNT1,Lines in a transfer" hexmask.quad.word 0x0 32.--47. 1. "ICNT0,Bytes in a transfer" hexmask.quad.long 0x0 0.--31. 1. "FLAGS,Flags for the operation and type of descriptor" line.quad 0x8 "MMR__DRU0_MMR_CFG__DRU_CHCORE_submit_word2_3,The second TR submission word" hexmask.quad 0x8 0.--47. 1. "SRC_ADDR,Source transfer address virtual or physical allowed" line.quad 0x10 "MMR__DRU0_MMR_CFG__DRU_CHCORE_submit_word4_5,The third TR submission word" hexmask.quad.word 0x10 48.--63. 1. "ICNT3,The size of the 4th loop in the TR transfer" hexmask.quad.word 0x10 32.--47. 1. "ICNT2,The size of the 3rd loop in the TR transfer" hexmask.quad.long 0x10 0.--31. 1. "DIM1,The first dimension width of the source data" line.quad 0x18 "MMR__DRU0_MMR_CFG__DRU_CHCORE_submit_word6_7,The fourth TR submission word" hexmask.quad.long 0x18 32.--63. 1. "DIM3,The third dimension width of the source data" hexmask.quad.long 0x18 0.--31. 1. "DIM2,The second dimension width of the source data" line.quad 0x20 "MMR__DRU0_MMR_CFG__DRU_CHCORE_submit_word8_9,The fifth TR submission word" hexmask.quad.long 0x20 32.--63. 1. "DDIM1,The first dimension width of the destination data" hexmask.quad.long 0x20 0.--31. 1. "FMTFLAGS,The data formatting flags to be used for the TR" line.quad 0x28 "MMR__DRU0_MMR_CFG__DRU_CHCORE_submit_word10_11,The sixth TR submission word" hexmask.quad 0x28 0.--47. 1. "DADDR,Destination transfer address virtual or physical allowed" line.quad 0x30 "MMR__DRU0_MMR_CFG__DRU_CHCORE_submit_word12_13,The seventh TR submission word" hexmask.quad.long 0x30 32.--63. 1. "DDIM3,The third dimension width of the destination data" hexmask.quad.long 0x30 0.--31. 1. "DDIM2,The second dimension width of the destination data" line.quad 0x38 "MMR__DRU0_MMR_CFG__DRU_CHCORE_submit_word14_15,The eight TR submission word" hexmask.quad.word 0x38 48.--63. 1. "DICNT3,The fourth count of the destination if different than the source" hexmask.quad.word 0x38 32.--47. 1. "DICNT2,The third count of the destination if different than the source" hexmask.quad.word 0x38 16.--31. 1. "DICNT1,The second innermost count of the destination if different than the source" newline hexmask.quad.word 0x38 0.--15. 1. "DICNT0,The innermost count of the destination if different than the source" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU_CAUSE (COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU_CAUSE)" base ad:0x6D0E0000 rgroup.quad 0x0++0x7 line.quad 0x0 "MMR__DRU0_MMR_CFG__DRU_CAUSE_cause,Error Register cause for channels 0 to 15" bitfld.quad 0x0 63. "R_ERR15,Masked error bit for Tx channel n+15" "0,1" bitfld.quad 0x0 62. "R_PEND15,Masked completion ring pending bit for Rx channel n+15" "0,1" bitfld.quad 0x0 61. "T_ERR15,Masked error bit for Tx channel n+15" "0,1" bitfld.quad 0x0 60. "T_PEND15,Masked completion ring pending bit for Tx channel n+15" "0,1" bitfld.quad 0x0 59. "R_ERR14,Masked error bit for Tx channel n+14" "0,1" bitfld.quad 0x0 58. "R_PEND14,Masked completion ring pending bit for Rx channel n+14" "0,1" bitfld.quad 0x0 57. "T_ERR14,Masked error bit for Tx channel n+14" "0,1" bitfld.quad 0x0 56. "T_PEND14,Masked completion ring pending bit for Tx channel n+14" "0,1" newline bitfld.quad 0x0 55. "R_ERR13,Masked error bit for Tx channel n+13" "0,1" bitfld.quad 0x0 54. "R_PEND13,Masked completion ring pending bit for Rx channel n+13" "0,1" bitfld.quad 0x0 53. "T_ERR13,Masked error bit for Tx channel n+13" "0,1" bitfld.quad 0x0 52. "T_PEND13,Masked completion ring pending bit for Tx channel n+13" "0,1" bitfld.quad 0x0 51. "R_ERR12,Masked error bit for Tx channel n+12" "0,1" bitfld.quad 0x0 50. "R_PEND12,Masked completion ring pending bit for Rx channel n+12" "0,1" bitfld.quad 0x0 49. "T_ERR12,Masked error bit for Tx channel n+12" "0,1" bitfld.quad 0x0 48. "T_PEND12,Masked completion ring pending bit for Tx channel n+12" "0,1" newline bitfld.quad 0x0 47. "R_ERR11,Masked error bit for Tx channel n+11" "0,1" bitfld.quad 0x0 46. "R_PEND11,Masked completion ring pending bit for Rx channel n+11" "0,1" bitfld.quad 0x0 45. "T_ERR11,Masked error bit for Tx channel n+11" "0,1" bitfld.quad 0x0 44. "T_PEND11,Masked completion ring pending bit for Tx channel n+11" "0,1" bitfld.quad 0x0 43. "R_ERR10,Masked error bit for Tx channel n+10" "0,1" bitfld.quad 0x0 42. "R_PEND10,Masked completion ring pending bit for Rx channel n+10" "0,1" bitfld.quad 0x0 41. "T_ERR10,Masked error bit for Tx channel n+10" "0,1" bitfld.quad 0x0 40. "T_PEND10,Masked completion ring pending bit for Tx channel n+10" "0,1" newline bitfld.quad 0x0 39. "R_ERR9,Masked error bit for Tx channel n+9" "0,1" bitfld.quad 0x0 38. "R_PEND9,Masked completion ring pending bit for Rx channel n+9" "0,1" bitfld.quad 0x0 37. "T_ERR9,Masked error bit for Tx channel n+9" "0,1" bitfld.quad 0x0 36. "T_PEND9,Masked completion ring pending bit for Tx channel n+9" "0,1" bitfld.quad 0x0 35. "R_ERR8,Masked error bit for Tx channel n+8" "0,1" bitfld.quad 0x0 34. "R_PEND8,Masked completion ring pending bit for Rx channel n+8" "0,1" bitfld.quad 0x0 33. "T_ERR8,Masked error bit for Tx channel n+8" "0,1" bitfld.quad 0x0 32. "T_PEND8,Masked completion ring pending bit for Tx channel n+8" "0,1" newline bitfld.quad 0x0 31. "R_ERR7,Masked error bit for Tx channel n+7" "0,1" bitfld.quad 0x0 30. "R_PEND7,Masked completion ring pending bit for Rx channel n+7" "0,1" bitfld.quad 0x0 29. "T_ERR7,Masked error bit for Tx channel n+7" "0,1" bitfld.quad 0x0 28. "T_PEND7,Masked completion ring pending bit for Tx channel n+7" "0,1" bitfld.quad 0x0 27. "R_ERR6,Masked error bit for Tx channel n+6" "0,1" bitfld.quad 0x0 26. "R_PEND6,Masked completion ring pending bit for Rx channel n+6" "0,1" bitfld.quad 0x0 25. "T_ERR6,Masked error bit for Tx channel n+6" "0,1" bitfld.quad 0x0 24. "T_PEND6,Masked completion ring pending bit for Tx channel n+6" "0,1" newline bitfld.quad 0x0 23. "R_ERR5,Masked error bit for Tx channel n+5" "0,1" bitfld.quad 0x0 22. "R_PEND5,Masked completion ring pending bit for Rx channel n+5" "0,1" bitfld.quad 0x0 21. "T_ERR5,Masked error bit for Tx channel n+5" "0,1" bitfld.quad 0x0 20. "T_PEND5,Masked completion ring pending bit for Tx channel n+5" "0,1" bitfld.quad 0x0 19. "R_ERR4,Masked error bit for Tx channel n+4" "0,1" bitfld.quad 0x0 18. "R_PEND4,Masked completion ring pending bit for Rx channel n+4" "0,1" bitfld.quad 0x0 17. "T_ERR4,Masked error bit for Tx channel n+4" "0,1" bitfld.quad 0x0 16. "T_PEND4,Masked completion ring pending bit for Tx channel n+4" "0,1" newline bitfld.quad 0x0 15. "R_ERR3,Masked error bit for Tx channel n+3" "0,1" bitfld.quad 0x0 14. "R_PEND3,Masked completion ring pending bit for Rx channel n+3" "0,1" bitfld.quad 0x0 13. "T_ERR3,Masked error bit for Tx channel n+3" "0,1" bitfld.quad 0x0 12. "T_PEND3,Masked completion ring pending bit for Tx channel n+3" "0,1" bitfld.quad 0x0 11. "R_ERR2,Masked error bit for Tx channel n+2" "0,1" bitfld.quad 0x0 10. "R_PEND2,Masked completion ring pending bit for Rx channel n+2" "0,1" bitfld.quad 0x0 9. "T_ERR2,Masked error bit for Tx channel n+2" "0,1" bitfld.quad 0x0 8. "T_PEND2,Masked completion ring pending bit for Tx channel n+2" "0,1" newline bitfld.quad 0x0 7. "R_ERR1,Masked error bit for Tx channel n+1" "0,1" bitfld.quad 0x0 6. "R_PEND1,Masked completion ring pending bit for Rx channel n+1" "0,1" bitfld.quad 0x0 5. "T_ERR1,Masked error bit for Tx channel n+1" "0,1" bitfld.quad 0x0 4. "T_PEND1,Masked completion ring pending bit for Tx channel n+1" "0,1" bitfld.quad 0x0 3. "R_ERR0,Masked error bit for Tx channel n" "0,1" bitfld.quad 0x0 2. "R_PEND0,Masked completion ring pending bit for Rx channel n" "0,1" bitfld.quad 0x0 1. "T_ERR0,Masked error bit for Tx channel n" "0,1" bitfld.quad 0x0 0. "T_PEND0,Masked completion ring pending bit for Tx channel n" "0,1" tree.end endif tree.end tree "COMPUTE_CLUSTER0_GIC500SS" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_GIC500SS_GIC_TRANSLATER (COMPUTE_CLUSTER0_GIC500SS_GIC_TRANSLATER)" base ad:0x1000000 rgroup.long 0x40++0x3 line.long 0x0 "GIC_TRANSLATER_TRANSLATER__1_GITS_TRANSLATER,ITS Translation Register" hexmask.long 0x0 0.--31. 1. "TRANSLATER__1_GITS_TRANSLATER__0_32," tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_GIC500SS_GIC_DISTRIBUTOR (COMPUTE_CLUSTER0_GIC500SS_GIC_DISTRIBUTOR)" base ad:0x1800000 rgroup.long 0x0++0xB line.long 0x0 "GIC_DISTRIBUTOR_Distributor__1_GICD_CTLR,Distributor Control Register" bitfld.long 0x0 31. "DISTRIBUTOR__1_GICD_CTLR__31_1," "0,1" bitfld.long 0x0 6. "DISTRIBUTOR__1_GICD_CTLR__6_1," "0,1" newline bitfld.long 0x0 5. "DISTRIBUTOR__1_GICD_CTLR__5_1," "0,1" bitfld.long 0x0 4. "DISTRIBUTOR__1_GICD_CTLR__4_1," "0,1" newline bitfld.long 0x0 2. "DISTRIBUTOR__1_GICD_CTLR__2_1," "0,1" bitfld.long 0x0 1. "DISTRIBUTOR__1_GICD_CTLR__1_1," "0,1" newline bitfld.long 0x0 0. "DISTRIBUTOR__1_GICD_CTLR__0_1," "0,1" line.long 0x4 "GIC_DISTRIBUTOR_Distributor__3_GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x4 24. "DISTRIBUTOR__3_GICD_TYPER__24_1," "0,1" hexmask.long.byte 0x4 19.--23. 1. "DISTRIBUTOR__3_GICD_TYPER__19_5," newline bitfld.long 0x4 18. "DISTRIBUTOR__3_GICD_TYPER__18_1," "0,1" bitfld.long 0x4 17. "DISTRIBUTOR__3_GICD_TYPER__17_1," "0,1" newline bitfld.long 0x4 16. "DISTRIBUTOR__3_GICD_TYPER__16_1," "0,1" hexmask.long.byte 0x4 11.--15. 1. "DISTRIBUTOR__3_GICD_TYPER__11_5," newline bitfld.long 0x4 10. "DISTRIBUTOR__3_GICD_TYPER__10_1," "0,1" bitfld.long 0x4 5.--7. "DISTRIBUTOR__3_GICD_TYPER__5_3," "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--4. 1. "DISTRIBUTOR__3_GICD_TYPER__0_5," line.long 0x8 "GIC_DISTRIBUTOR_Distributor__4_GICD_IIDR,Distributor Implementer Identification Register" hexmask.long.byte 0x8 24.--31. 1. "DISTRIBUTOR__4_GICD_IIDR__24_8," hexmask.long.byte 0x8 16.--19. 1. "DISTRIBUTOR__4_GICD_IIDR__16_4," newline hexmask.long.byte 0x8 12.--15. 1. "DISTRIBUTOR__4_GICD_IIDR__12_4," hexmask.long.word 0x8 0.--11. 1. "DISTRIBUTOR__4_GICD_IIDR__0_12," rgroup.long 0x40++0x3 line.long 0x0 "GIC_DISTRIBUTOR_Distributor__5_GICD_SETSPI_NSR,Non-Secure SPI Set Register" hexmask.long.word 0x0 0.--9. 1. "DISTRIBUTOR__5_GICD_SETSPI_NSR__0_10," rgroup.long 0x48++0x3 line.long 0x0 "GIC_DISTRIBUTOR_Distributor__6_GICD_CLRSPI_NSR,Non-Secure SPI Clear Register" hexmask.long.word 0x0 0.--9. 1. "DISTRIBUTOR__6_GICD_CLRSPI_NSR__0_10," rgroup.long 0x50++0x3 line.long 0x0 "GIC_DISTRIBUTOR_Distributor__7_GICD_SETSPI_SR,Secure SPI Set Register" hexmask.long.word 0x0 0.--9. 1. "DISTRIBUTOR__7_GICD_SETSPI_SR__0_10," rgroup.long 0x58++0x3 line.long 0x0 "GIC_DISTRIBUTOR_Distributor__8_GICD_CLRSPI_SR,Secure SPI Clear Register" hexmask.long.word 0x0 0.--9. 1. "DISTRIBUTOR__8_GICD_CLRSPI_SR__0_10," rgroup.long 0x80++0x7B line.long 0x0 "GIC_DISTRIBUTOR_Distributor__9_GICD_IGROUPR0,Interrupt Group Registers" line.long 0x4 "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR1,Interrupt Group Registers" line.long 0x8 "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR2,Interrupt Group Registers" line.long 0xC "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR3,Interrupt Group Registers" line.long 0x10 "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR4,Interrupt Group Registers" line.long 0x14 "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR5,Interrupt Group Registers" line.long 0x18 "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR6,Interrupt Group Registers" line.long 0x1C "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR7,Interrupt Group Registers" line.long 0x20 "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR8,Interrupt Group Registers" line.long 0x24 "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR9,Interrupt Group Registers" line.long 0x28 "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR10,Interrupt Group Registers" line.long 0x2C "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR11,Interrupt Group Registers" line.long 0x30 "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR12,Interrupt Group Registers" line.long 0x34 "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR13,Interrupt Group Registers" line.long 0x38 "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR14,Interrupt Group Registers" line.long 0x3C "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR15,Interrupt Group Registers" line.long 0x40 "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR16,Interrupt Group Registers" line.long 0x44 "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR17,Interrupt Group Registers" line.long 0x48 "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR18,Interrupt Group Registers" line.long 0x4C "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR19,Interrupt Group Registers" line.long 0x50 "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR20,Interrupt Group Registers" line.long 0x54 "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR21,Interrupt Group Registers" line.long 0x58 "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR22,Interrupt Group Registers" line.long 0x5C "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR23,Interrupt Group Registers" line.long 0x60 "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR24,Interrupt Group Registers" line.long 0x64 "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR25,Interrupt Group Registers" line.long 0x68 "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR26,Interrupt Group Registers" line.long 0x6C "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR27,Interrupt Group Registers" line.long 0x70 "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR28,Interrupt Group Registers" line.long 0x74 "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR29,Interrupt Group Registers" line.long 0x78 "GIC_DISTRIBUTOR_Distributor__10_GICD_IGROUPR30,Interrupt Group Registers" rgroup.long 0x104++0x77 line.long 0x0 "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER1,Interrupt Set-Enable Registers" line.long 0x4 "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER2,Interrupt Set-Enable Registers" line.long 0x8 "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER3,Interrupt Set-Enable Registers" line.long 0xC "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER4,Interrupt Set-Enable Registers" line.long 0x10 "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER5,Interrupt Set-Enable Registers" line.long 0x14 "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER6,Interrupt Set-Enable Registers" line.long 0x18 "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER7,Interrupt Set-Enable Registers" line.long 0x1C "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER8,Interrupt Set-Enable Registers" line.long 0x20 "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER9,Interrupt Set-Enable Registers" line.long 0x24 "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER10,Interrupt Set-Enable Registers" line.long 0x28 "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER11,Interrupt Set-Enable Registers" line.long 0x2C "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER12,Interrupt Set-Enable Registers" line.long 0x30 "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER13,Interrupt Set-Enable Registers" line.long 0x34 "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER14,Interrupt Set-Enable Registers" line.long 0x38 "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER15,Interrupt Set-Enable Registers" line.long 0x3C "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER16,Interrupt Set-Enable Registers" line.long 0x40 "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER17,Interrupt Set-Enable Registers" line.long 0x44 "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER18,Interrupt Set-Enable Registers" line.long 0x48 "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER19,Interrupt Set-Enable Registers" line.long 0x4C "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER20,Interrupt Set-Enable Registers" line.long 0x50 "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER21,Interrupt Set-Enable Registers" line.long 0x54 "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER22,Interrupt Set-Enable Registers" line.long 0x58 "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER23,Interrupt Set-Enable Registers" line.long 0x5C "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER24,Interrupt Set-Enable Registers" line.long 0x60 "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER25,Interrupt Set-Enable Registers" line.long 0x64 "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER26,Interrupt Set-Enable Registers" line.long 0x68 "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER27,Interrupt Set-Enable Registers" line.long 0x6C "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER28,Interrupt Set-Enable Registers" line.long 0x70 "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER29,Interrupt Set-Enable Registers" line.long 0x74 "GIC_DISTRIBUTOR_Distributor__12_GICD_ISENABLER30,Interrupt Set-Enable Registers" rgroup.long 0x184++0x77 line.long 0x0 "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER1,Interrupt Clear-Enable Registers" line.long 0x4 "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER2,Interrupt Clear-Enable Registers" line.long 0x8 "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER3,Interrupt Clear-Enable Registers" line.long 0xC "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER4,Interrupt Clear-Enable Registers" line.long 0x10 "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER5,Interrupt Clear-Enable Registers" line.long 0x14 "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER6,Interrupt Clear-Enable Registers" line.long 0x18 "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER7,Interrupt Clear-Enable Registers" line.long 0x1C "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER8,Interrupt Clear-Enable Registers" line.long 0x20 "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER9,Interrupt Clear-Enable Registers" line.long 0x24 "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER10,Interrupt Clear-Enable Registers" line.long 0x28 "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER11,Interrupt Clear-Enable Registers" line.long 0x2C "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER12,Interrupt Clear-Enable Registers" line.long 0x30 "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER13,Interrupt Clear-Enable Registers" line.long 0x34 "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER14,Interrupt Clear-Enable Registers" line.long 0x38 "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER15,Interrupt Clear-Enable Registers" line.long 0x3C "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER16,Interrupt Clear-Enable Registers" line.long 0x40 "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER17,Interrupt Clear-Enable Registers" line.long 0x44 "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER18,Interrupt Clear-Enable Registers" line.long 0x48 "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER19,Interrupt Clear-Enable Registers" line.long 0x4C "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER20,Interrupt Clear-Enable Registers" line.long 0x50 "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER21,Interrupt Clear-Enable Registers" line.long 0x54 "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER22,Interrupt Clear-Enable Registers" line.long 0x58 "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER23,Interrupt Clear-Enable Registers" line.long 0x5C "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER24,Interrupt Clear-Enable Registers" line.long 0x60 "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER25,Interrupt Clear-Enable Registers" line.long 0x64 "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER26,Interrupt Clear-Enable Registers" line.long 0x68 "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER27,Interrupt Clear-Enable Registers" line.long 0x6C "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER28,Interrupt Clear-Enable Registers" line.long 0x70 "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER29,Interrupt Clear-Enable Registers" line.long 0x74 "GIC_DISTRIBUTOR_Distributor__14_GICD_ICENABLER30,Interrupt Clear-Enable Registers" rgroup.long 0x204++0x77 line.long 0x0 "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR1,Interrupt Set-Pending Registers" line.long 0x4 "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR2,Interrupt Set-Pending Registers" line.long 0x8 "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR3,Interrupt Set-Pending Registers" line.long 0xC "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR4,Interrupt Set-Pending Registers" line.long 0x10 "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR5,Interrupt Set-Pending Registers" line.long 0x14 "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR6,Interrupt Set-Pending Registers" line.long 0x18 "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR7,Interrupt Set-Pending Registers" line.long 0x1C "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR8,Interrupt Set-Pending Registers" line.long 0x20 "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR9,Interrupt Set-Pending Registers" line.long 0x24 "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR10,Interrupt Set-Pending Registers" line.long 0x28 "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR11,Interrupt Set-Pending Registers" line.long 0x2C "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR12,Interrupt Set-Pending Registers" line.long 0x30 "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR13,Interrupt Set-Pending Registers" line.long 0x34 "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR14,Interrupt Set-Pending Registers" line.long 0x38 "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR15,Interrupt Set-Pending Registers" line.long 0x3C "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR16,Interrupt Set-Pending Registers" line.long 0x40 "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR17,Interrupt Set-Pending Registers" line.long 0x44 "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR18,Interrupt Set-Pending Registers" line.long 0x48 "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR19,Interrupt Set-Pending Registers" line.long 0x4C "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR20,Interrupt Set-Pending Registers" line.long 0x50 "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR21,Interrupt Set-Pending Registers" line.long 0x54 "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR22,Interrupt Set-Pending Registers" line.long 0x58 "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR23,Interrupt Set-Pending Registers" line.long 0x5C "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR24,Interrupt Set-Pending Registers" line.long 0x60 "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR25,Interrupt Set-Pending Registers" line.long 0x64 "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR26,Interrupt Set-Pending Registers" line.long 0x68 "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR27,Interrupt Set-Pending Registers" line.long 0x6C "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR28,Interrupt Set-Pending Registers" line.long 0x70 "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR29,Interrupt Set-Pending Registers" line.long 0x74 "GIC_DISTRIBUTOR_Distributor__16_GICD_ISPENDR30,Interrupt Set-Pending Registers" rgroup.long 0x284++0x77 line.long 0x0 "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR1,Interrupt Clear-Pending Registers" line.long 0x4 "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR2,Interrupt Clear-Pending Registers" line.long 0x8 "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR3,Interrupt Clear-Pending Registers" line.long 0xC "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR4,Interrupt Clear-Pending Registers" line.long 0x10 "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR5,Interrupt Clear-Pending Registers" line.long 0x14 "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR6,Interrupt Clear-Pending Registers" line.long 0x18 "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR7,Interrupt Clear-Pending Registers" line.long 0x1C "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR8,Interrupt Clear-Pending Registers" line.long 0x20 "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR9,Interrupt Clear-Pending Registers" line.long 0x24 "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR10,Interrupt Clear-Pending Registers" line.long 0x28 "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR11,Interrupt Clear-Pending Registers" line.long 0x2C "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR12,Interrupt Clear-Pending Registers" line.long 0x30 "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR13,Interrupt Clear-Pending Registers" line.long 0x34 "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR14,Interrupt Clear-Pending Registers" line.long 0x38 "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR15,Interrupt Clear-Pending Registers" line.long 0x3C "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR16,Interrupt Clear-Pending Registers" line.long 0x40 "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR17,Interrupt Clear-Pending Registers" line.long 0x44 "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR18,Interrupt Clear-Pending Registers" line.long 0x48 "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR19,Interrupt Clear-Pending Registers" line.long 0x4C "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR20,Interrupt Clear-Pending Registers" line.long 0x50 "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR21,Interrupt Clear-Pending Registers" line.long 0x54 "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR22,Interrupt Clear-Pending Registers" line.long 0x58 "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR23,Interrupt Clear-Pending Registers" line.long 0x5C "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR24,Interrupt Clear-Pending Registers" line.long 0x60 "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR25,Interrupt Clear-Pending Registers" line.long 0x64 "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR26,Interrupt Clear-Pending Registers" line.long 0x68 "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR27,Interrupt Clear-Pending Registers" line.long 0x6C "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR28,Interrupt Clear-Pending Registers" line.long 0x70 "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR29,Interrupt Clear-Pending Registers" line.long 0x74 "GIC_DISTRIBUTOR_Distributor__18_GICD_ICPENDR30,Interrupt Clear-Pending Registers" rgroup.long 0x304++0x77 line.long 0x0 "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER1,Interrupt Set-Active Registers" line.long 0x4 "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER2,Interrupt Set-Active Registers" line.long 0x8 "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER3,Interrupt Set-Active Registers" line.long 0xC "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER4,Interrupt Set-Active Registers" line.long 0x10 "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER5,Interrupt Set-Active Registers" line.long 0x14 "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER6,Interrupt Set-Active Registers" line.long 0x18 "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER7,Interrupt Set-Active Registers" line.long 0x1C "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER8,Interrupt Set-Active Registers" line.long 0x20 "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER9,Interrupt Set-Active Registers" line.long 0x24 "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER10,Interrupt Set-Active Registers" line.long 0x28 "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER11,Interrupt Set-Active Registers" line.long 0x2C "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER12,Interrupt Set-Active Registers" line.long 0x30 "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER13,Interrupt Set-Active Registers" line.long 0x34 "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER14,Interrupt Set-Active Registers" line.long 0x38 "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER15,Interrupt Set-Active Registers" line.long 0x3C "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER16,Interrupt Set-Active Registers" line.long 0x40 "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER17,Interrupt Set-Active Registers" line.long 0x44 "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER18,Interrupt Set-Active Registers" line.long 0x48 "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER19,Interrupt Set-Active Registers" line.long 0x4C "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER20,Interrupt Set-Active Registers" line.long 0x50 "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER21,Interrupt Set-Active Registers" line.long 0x54 "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER22,Interrupt Set-Active Registers" line.long 0x58 "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER23,Interrupt Set-Active Registers" line.long 0x5C "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER24,Interrupt Set-Active Registers" line.long 0x60 "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER25,Interrupt Set-Active Registers" line.long 0x64 "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER26,Interrupt Set-Active Registers" line.long 0x68 "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER27,Interrupt Set-Active Registers" line.long 0x6C "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER28,Interrupt Set-Active Registers" line.long 0x70 "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER29,Interrupt Set-Active Registers" line.long 0x74 "GIC_DISTRIBUTOR_Distributor__20_GICD_ISACTIVER30,Interrupt Set-Active Registers" rgroup.long 0x384++0x77 line.long 0x0 "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER1,Interrupt Clear-Active Registers" line.long 0x4 "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER2,Interrupt Clear-Active Registers" line.long 0x8 "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER3,Interrupt Clear-Active Registers" line.long 0xC "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER4,Interrupt Clear-Active Registers" line.long 0x10 "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER5,Interrupt Clear-Active Registers" line.long 0x14 "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER6,Interrupt Clear-Active Registers" line.long 0x18 "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER7,Interrupt Clear-Active Registers" line.long 0x1C "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER8,Interrupt Clear-Active Registers" line.long 0x20 "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER9,Interrupt Clear-Active Registers" line.long 0x24 "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER10,Interrupt Clear-Active Registers" line.long 0x28 "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER11,Interrupt Clear-Active Registers" line.long 0x2C "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER12,Interrupt Clear-Active Registers" line.long 0x30 "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER13,Interrupt Clear-Active Registers" line.long 0x34 "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER14,Interrupt Clear-Active Registers" line.long 0x38 "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER15,Interrupt Clear-Active Registers" line.long 0x3C "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER16,Interrupt Clear-Active Registers" line.long 0x40 "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER17,Interrupt Clear-Active Registers" line.long 0x44 "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER18,Interrupt Clear-Active Registers" line.long 0x48 "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER19,Interrupt Clear-Active Registers" line.long 0x4C "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER20,Interrupt Clear-Active Registers" line.long 0x50 "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER21,Interrupt Clear-Active Registers" line.long 0x54 "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER22,Interrupt Clear-Active Registers" line.long 0x58 "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER23,Interrupt Clear-Active Registers" line.long 0x5C "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER24,Interrupt Clear-Active Registers" line.long 0x60 "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER25,Interrupt Clear-Active Registers" line.long 0x64 "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER26,Interrupt Clear-Active Registers" line.long 0x68 "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER27,Interrupt Clear-Active Registers" line.long 0x6C "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER28,Interrupt Clear-Active Registers" line.long 0x70 "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER29,Interrupt Clear-Active Registers" line.long 0x74 "GIC_DISTRIBUTOR_Distributor__22_GICD_ICACTIVER30,Interrupt Clear-Active Registers" rgroup.long 0x420++0x3BF line.long 0x0 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR8,Interrupt Priority Registers" line.long 0x4 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR9,Interrupt Priority Registers" line.long 0x8 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR10,Interrupt Priority Registers" line.long 0xC "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR11,Interrupt Priority Registers" line.long 0x10 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR12,Interrupt Priority Registers" line.long 0x14 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR13,Interrupt Priority Registers" line.long 0x18 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR14,Interrupt Priority Registers" line.long 0x1C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR15,Interrupt Priority Registers" line.long 0x20 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR16,Interrupt Priority Registers" line.long 0x24 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR17,Interrupt Priority Registers" line.long 0x28 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR18,Interrupt Priority Registers" line.long 0x2C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR19,Interrupt Priority Registers" line.long 0x30 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR20,Interrupt Priority Registers" line.long 0x34 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR21,Interrupt Priority Registers" line.long 0x38 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR22,Interrupt Priority Registers" line.long 0x3C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR23,Interrupt Priority Registers" line.long 0x40 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR24,Interrupt Priority Registers" line.long 0x44 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR25,Interrupt Priority Registers" line.long 0x48 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR26,Interrupt Priority Registers" line.long 0x4C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR27,Interrupt Priority Registers" line.long 0x50 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR28,Interrupt Priority Registers" line.long 0x54 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR29,Interrupt Priority Registers" line.long 0x58 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR30,Interrupt Priority Registers" line.long 0x5C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR31,Interrupt Priority Registers" line.long 0x60 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR32,Interrupt Priority Registers" line.long 0x64 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR33,Interrupt Priority Registers" line.long 0x68 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR34,Interrupt Priority Registers" line.long 0x6C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR35,Interrupt Priority Registers" line.long 0x70 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR36,Interrupt Priority Registers" line.long 0x74 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR37,Interrupt Priority Registers" line.long 0x78 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR38,Interrupt Priority Registers" line.long 0x7C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR39,Interrupt Priority Registers" line.long 0x80 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR40,Interrupt Priority Registers" line.long 0x84 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR41,Interrupt Priority Registers" line.long 0x88 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR42,Interrupt Priority Registers" line.long 0x8C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR43,Interrupt Priority Registers" line.long 0x90 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR44,Interrupt Priority Registers" line.long 0x94 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR45,Interrupt Priority Registers" line.long 0x98 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR46,Interrupt Priority Registers" line.long 0x9C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR47,Interrupt Priority Registers" line.long 0xA0 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR48,Interrupt Priority Registers" line.long 0xA4 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR49,Interrupt Priority Registers" line.long 0xA8 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR50,Interrupt Priority Registers" line.long 0xAC "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR51,Interrupt Priority Registers" line.long 0xB0 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR52,Interrupt Priority Registers" line.long 0xB4 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR53,Interrupt Priority Registers" line.long 0xB8 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR54,Interrupt Priority Registers" line.long 0xBC "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR55,Interrupt Priority Registers" line.long 0xC0 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR56,Interrupt Priority Registers" line.long 0xC4 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR57,Interrupt Priority Registers" line.long 0xC8 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR58,Interrupt Priority Registers" line.long 0xCC "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR59,Interrupt Priority Registers" line.long 0xD0 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR60,Interrupt Priority Registers" line.long 0xD4 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR61,Interrupt Priority Registers" line.long 0xD8 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR62,Interrupt Priority Registers" line.long 0xDC "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR63,Interrupt Priority Registers" line.long 0xE0 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR64,Interrupt Priority Registers" line.long 0xE4 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR65,Interrupt Priority Registers" line.long 0xE8 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR66,Interrupt Priority Registers" line.long 0xEC "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR67,Interrupt Priority Registers" line.long 0xF0 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR68,Interrupt Priority Registers" line.long 0xF4 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR69,Interrupt Priority Registers" line.long 0xF8 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR70,Interrupt Priority Registers" line.long 0xFC "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR71,Interrupt Priority Registers" line.long 0x100 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR72,Interrupt Priority Registers" line.long 0x104 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR73,Interrupt Priority Registers" line.long 0x108 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR74,Interrupt Priority Registers" line.long 0x10C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR75,Interrupt Priority Registers" line.long 0x110 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR76,Interrupt Priority Registers" line.long 0x114 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR77,Interrupt Priority Registers" line.long 0x118 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR78,Interrupt Priority Registers" line.long 0x11C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR79,Interrupt Priority Registers" line.long 0x120 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR80,Interrupt Priority Registers" line.long 0x124 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR81,Interrupt Priority Registers" line.long 0x128 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR82,Interrupt Priority Registers" line.long 0x12C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR83,Interrupt Priority Registers" line.long 0x130 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR84,Interrupt Priority Registers" line.long 0x134 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR85,Interrupt Priority Registers" line.long 0x138 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR86,Interrupt Priority Registers" line.long 0x13C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR87,Interrupt Priority Registers" line.long 0x140 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR88,Interrupt Priority Registers" line.long 0x144 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR89,Interrupt Priority Registers" line.long 0x148 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR90,Interrupt Priority Registers" line.long 0x14C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR91,Interrupt Priority Registers" line.long 0x150 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR92,Interrupt Priority Registers" line.long 0x154 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR93,Interrupt Priority Registers" line.long 0x158 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR94,Interrupt Priority Registers" line.long 0x15C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR95,Interrupt Priority Registers" line.long 0x160 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR96,Interrupt Priority Registers" line.long 0x164 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR97,Interrupt Priority Registers" line.long 0x168 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR98,Interrupt Priority Registers" line.long 0x16C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR99,Interrupt Priority Registers" line.long 0x170 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR100,Interrupt Priority Registers" line.long 0x174 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR101,Interrupt Priority Registers" line.long 0x178 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR102,Interrupt Priority Registers" line.long 0x17C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR103,Interrupt Priority Registers" line.long 0x180 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR104,Interrupt Priority Registers" line.long 0x184 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR105,Interrupt Priority Registers" line.long 0x188 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR106,Interrupt Priority Registers" line.long 0x18C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR107,Interrupt Priority Registers" line.long 0x190 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR108,Interrupt Priority Registers" line.long 0x194 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR109,Interrupt Priority Registers" line.long 0x198 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR110,Interrupt Priority Registers" line.long 0x19C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR111,Interrupt Priority Registers" line.long 0x1A0 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR112,Interrupt Priority Registers" line.long 0x1A4 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR113,Interrupt Priority Registers" line.long 0x1A8 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR114,Interrupt Priority Registers" line.long 0x1AC "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR115,Interrupt Priority Registers" line.long 0x1B0 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR116,Interrupt Priority Registers" line.long 0x1B4 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR117,Interrupt Priority Registers" line.long 0x1B8 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR118,Interrupt Priority Registers" line.long 0x1BC "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR119,Interrupt Priority Registers" line.long 0x1C0 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR120,Interrupt Priority Registers" line.long 0x1C4 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR121,Interrupt Priority Registers" line.long 0x1C8 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR122,Interrupt Priority Registers" line.long 0x1CC "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR123,Interrupt Priority Registers" line.long 0x1D0 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR124,Interrupt Priority Registers" line.long 0x1D4 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR125,Interrupt Priority Registers" line.long 0x1D8 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR126,Interrupt Priority Registers" line.long 0x1DC "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR127,Interrupt Priority Registers" line.long 0x1E0 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR128,Interrupt Priority Registers" line.long 0x1E4 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR129,Interrupt Priority Registers" line.long 0x1E8 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR130,Interrupt Priority Registers" line.long 0x1EC "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR131,Interrupt Priority Registers" line.long 0x1F0 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR132,Interrupt Priority Registers" line.long 0x1F4 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR133,Interrupt Priority Registers" line.long 0x1F8 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR134,Interrupt Priority Registers" line.long 0x1FC "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR135,Interrupt Priority Registers" line.long 0x200 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR136,Interrupt Priority Registers" line.long 0x204 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR137,Interrupt Priority Registers" line.long 0x208 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR138,Interrupt Priority Registers" line.long 0x20C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR139,Interrupt Priority Registers" line.long 0x210 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR140,Interrupt Priority Registers" line.long 0x214 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR141,Interrupt Priority Registers" line.long 0x218 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR142,Interrupt Priority Registers" line.long 0x21C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR143,Interrupt Priority Registers" line.long 0x220 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR144,Interrupt Priority Registers" line.long 0x224 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR145,Interrupt Priority Registers" line.long 0x228 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR146,Interrupt Priority Registers" line.long 0x22C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR147,Interrupt Priority Registers" line.long 0x230 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR148,Interrupt Priority Registers" line.long 0x234 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR149,Interrupt Priority Registers" line.long 0x238 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR150,Interrupt Priority Registers" line.long 0x23C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR151,Interrupt Priority Registers" line.long 0x240 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR152,Interrupt Priority Registers" line.long 0x244 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR153,Interrupt Priority Registers" line.long 0x248 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR154,Interrupt Priority Registers" line.long 0x24C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR155,Interrupt Priority Registers" line.long 0x250 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR156,Interrupt Priority Registers" line.long 0x254 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR157,Interrupt Priority Registers" line.long 0x258 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR158,Interrupt Priority Registers" line.long 0x25C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR159,Interrupt Priority Registers" line.long 0x260 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR160,Interrupt Priority Registers" line.long 0x264 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR161,Interrupt Priority Registers" line.long 0x268 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR162,Interrupt Priority Registers" line.long 0x26C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR163,Interrupt Priority Registers" line.long 0x270 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR164,Interrupt Priority Registers" line.long 0x274 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR165,Interrupt Priority Registers" line.long 0x278 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR166,Interrupt Priority Registers" line.long 0x27C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR167,Interrupt Priority Registers" line.long 0x280 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR168,Interrupt Priority Registers" line.long 0x284 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR169,Interrupt Priority Registers" line.long 0x288 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR170,Interrupt Priority Registers" line.long 0x28C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR171,Interrupt Priority Registers" line.long 0x290 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR172,Interrupt Priority Registers" line.long 0x294 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR173,Interrupt Priority Registers" line.long 0x298 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR174,Interrupt Priority Registers" line.long 0x29C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR175,Interrupt Priority Registers" line.long 0x2A0 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR176,Interrupt Priority Registers" line.long 0x2A4 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR177,Interrupt Priority Registers" line.long 0x2A8 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR178,Interrupt Priority Registers" line.long 0x2AC "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR179,Interrupt Priority Registers" line.long 0x2B0 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR180,Interrupt Priority Registers" line.long 0x2B4 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR181,Interrupt Priority Registers" line.long 0x2B8 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR182,Interrupt Priority Registers" line.long 0x2BC "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR183,Interrupt Priority Registers" line.long 0x2C0 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR184,Interrupt Priority Registers" line.long 0x2C4 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR185,Interrupt Priority Registers" line.long 0x2C8 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR186,Interrupt Priority Registers" line.long 0x2CC "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR187,Interrupt Priority Registers" line.long 0x2D0 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR188,Interrupt Priority Registers" line.long 0x2D4 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR189,Interrupt Priority Registers" line.long 0x2D8 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR190,Interrupt Priority Registers" line.long 0x2DC "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR191,Interrupt Priority Registers" line.long 0x2E0 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR192,Interrupt Priority Registers" line.long 0x2E4 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR193,Interrupt Priority Registers" line.long 0x2E8 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR194,Interrupt Priority Registers" line.long 0x2EC "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR195,Interrupt Priority Registers" line.long 0x2F0 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR196,Interrupt Priority Registers" line.long 0x2F4 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR197,Interrupt Priority Registers" line.long 0x2F8 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR198,Interrupt Priority Registers" line.long 0x2FC "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR199,Interrupt Priority Registers" line.long 0x300 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR200,Interrupt Priority Registers" line.long 0x304 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR201,Interrupt Priority Registers" line.long 0x308 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR202,Interrupt Priority Registers" line.long 0x30C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR203,Interrupt Priority Registers" line.long 0x310 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR204,Interrupt Priority Registers" line.long 0x314 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR205,Interrupt Priority Registers" line.long 0x318 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR206,Interrupt Priority Registers" line.long 0x31C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR207,Interrupt Priority Registers" line.long 0x320 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR208,Interrupt Priority Registers" line.long 0x324 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR209,Interrupt Priority Registers" line.long 0x328 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR210,Interrupt Priority Registers" line.long 0x32C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR211,Interrupt Priority Registers" line.long 0x330 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR212,Interrupt Priority Registers" line.long 0x334 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR213,Interrupt Priority Registers" line.long 0x338 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR214,Interrupt Priority Registers" line.long 0x33C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR215,Interrupt Priority Registers" line.long 0x340 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR216,Interrupt Priority Registers" line.long 0x344 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR217,Interrupt Priority Registers" line.long 0x348 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR218,Interrupt Priority Registers" line.long 0x34C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR219,Interrupt Priority Registers" line.long 0x350 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR220,Interrupt Priority Registers" line.long 0x354 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR221,Interrupt Priority Registers" line.long 0x358 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR222,Interrupt Priority Registers" line.long 0x35C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR223,Interrupt Priority Registers" line.long 0x360 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR224,Interrupt Priority Registers" line.long 0x364 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR225,Interrupt Priority Registers" line.long 0x368 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR226,Interrupt Priority Registers" line.long 0x36C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR227,Interrupt Priority Registers" line.long 0x370 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR228,Interrupt Priority Registers" line.long 0x374 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR229,Interrupt Priority Registers" line.long 0x378 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR230,Interrupt Priority Registers" line.long 0x37C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR231,Interrupt Priority Registers" line.long 0x380 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR232,Interrupt Priority Registers" line.long 0x384 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR233,Interrupt Priority Registers" line.long 0x388 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR234,Interrupt Priority Registers" line.long 0x38C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR235,Interrupt Priority Registers" line.long 0x390 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR236,Interrupt Priority Registers" line.long 0x394 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR237,Interrupt Priority Registers" line.long 0x398 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR238,Interrupt Priority Registers" line.long 0x39C "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR239,Interrupt Priority Registers" line.long 0x3A0 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR240,Interrupt Priority Registers" line.long 0x3A4 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR241,Interrupt Priority Registers" line.long 0x3A8 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR242,Interrupt Priority Registers" line.long 0x3AC "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR243,Interrupt Priority Registers" line.long 0x3B0 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR244,Interrupt Priority Registers" line.long 0x3B4 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR245,Interrupt Priority Registers" line.long 0x3B8 "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR246,Interrupt Priority Registers" line.long 0x3BC "GIC_DISTRIBUTOR_Distributor__24_GICD_IPRIORITYR247,Interrupt Priority Registers" rgroup.long 0x820++0x3BF line.long 0x0 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR8,Interrupt Processor Targets Registers" line.long 0x4 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR9,Interrupt Processor Targets Registers" line.long 0x8 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR10,Interrupt Processor Targets Registers" line.long 0xC "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR11,Interrupt Processor Targets Registers" line.long 0x10 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR12,Interrupt Processor Targets Registers" line.long 0x14 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR13,Interrupt Processor Targets Registers" line.long 0x18 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR14,Interrupt Processor Targets Registers" line.long 0x1C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR15,Interrupt Processor Targets Registers" line.long 0x20 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR16,Interrupt Processor Targets Registers" line.long 0x24 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR17,Interrupt Processor Targets Registers" line.long 0x28 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR18,Interrupt Processor Targets Registers" line.long 0x2C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR19,Interrupt Processor Targets Registers" line.long 0x30 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR20,Interrupt Processor Targets Registers" line.long 0x34 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR21,Interrupt Processor Targets Registers" line.long 0x38 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR22,Interrupt Processor Targets Registers" line.long 0x3C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR23,Interrupt Processor Targets Registers" line.long 0x40 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR24,Interrupt Processor Targets Registers" line.long 0x44 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR25,Interrupt Processor Targets Registers" line.long 0x48 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR26,Interrupt Processor Targets Registers" line.long 0x4C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR27,Interrupt Processor Targets Registers" line.long 0x50 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR28,Interrupt Processor Targets Registers" line.long 0x54 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR29,Interrupt Processor Targets Registers" line.long 0x58 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR30,Interrupt Processor Targets Registers" line.long 0x5C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR31,Interrupt Processor Targets Registers" line.long 0x60 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR32,Interrupt Processor Targets Registers" line.long 0x64 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR33,Interrupt Processor Targets Registers" line.long 0x68 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR34,Interrupt Processor Targets Registers" line.long 0x6C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR35,Interrupt Processor Targets Registers" line.long 0x70 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR36,Interrupt Processor Targets Registers" line.long 0x74 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR37,Interrupt Processor Targets Registers" line.long 0x78 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR38,Interrupt Processor Targets Registers" line.long 0x7C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR39,Interrupt Processor Targets Registers" line.long 0x80 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR40,Interrupt Processor Targets Registers" line.long 0x84 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR41,Interrupt Processor Targets Registers" line.long 0x88 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR42,Interrupt Processor Targets Registers" line.long 0x8C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR43,Interrupt Processor Targets Registers" line.long 0x90 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR44,Interrupt Processor Targets Registers" line.long 0x94 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR45,Interrupt Processor Targets Registers" line.long 0x98 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR46,Interrupt Processor Targets Registers" line.long 0x9C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR47,Interrupt Processor Targets Registers" line.long 0xA0 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR48,Interrupt Processor Targets Registers" line.long 0xA4 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR49,Interrupt Processor Targets Registers" line.long 0xA8 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR50,Interrupt Processor Targets Registers" line.long 0xAC "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR51,Interrupt Processor Targets Registers" line.long 0xB0 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR52,Interrupt Processor Targets Registers" line.long 0xB4 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR53,Interrupt Processor Targets Registers" line.long 0xB8 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR54,Interrupt Processor Targets Registers" line.long 0xBC "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR55,Interrupt Processor Targets Registers" line.long 0xC0 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR56,Interrupt Processor Targets Registers" line.long 0xC4 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR57,Interrupt Processor Targets Registers" line.long 0xC8 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR58,Interrupt Processor Targets Registers" line.long 0xCC "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR59,Interrupt Processor Targets Registers" line.long 0xD0 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR60,Interrupt Processor Targets Registers" line.long 0xD4 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR61,Interrupt Processor Targets Registers" line.long 0xD8 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR62,Interrupt Processor Targets Registers" line.long 0xDC "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR63,Interrupt Processor Targets Registers" line.long 0xE0 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR64,Interrupt Processor Targets Registers" line.long 0xE4 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR65,Interrupt Processor Targets Registers" line.long 0xE8 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR66,Interrupt Processor Targets Registers" line.long 0xEC "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR67,Interrupt Processor Targets Registers" line.long 0xF0 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR68,Interrupt Processor Targets Registers" line.long 0xF4 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR69,Interrupt Processor Targets Registers" line.long 0xF8 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR70,Interrupt Processor Targets Registers" line.long 0xFC "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR71,Interrupt Processor Targets Registers" line.long 0x100 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR72,Interrupt Processor Targets Registers" line.long 0x104 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR73,Interrupt Processor Targets Registers" line.long 0x108 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR74,Interrupt Processor Targets Registers" line.long 0x10C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR75,Interrupt Processor Targets Registers" line.long 0x110 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR76,Interrupt Processor Targets Registers" line.long 0x114 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR77,Interrupt Processor Targets Registers" line.long 0x118 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR78,Interrupt Processor Targets Registers" line.long 0x11C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR79,Interrupt Processor Targets Registers" line.long 0x120 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR80,Interrupt Processor Targets Registers" line.long 0x124 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR81,Interrupt Processor Targets Registers" line.long 0x128 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR82,Interrupt Processor Targets Registers" line.long 0x12C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR83,Interrupt Processor Targets Registers" line.long 0x130 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR84,Interrupt Processor Targets Registers" line.long 0x134 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR85,Interrupt Processor Targets Registers" line.long 0x138 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR86,Interrupt Processor Targets Registers" line.long 0x13C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR87,Interrupt Processor Targets Registers" line.long 0x140 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR88,Interrupt Processor Targets Registers" line.long 0x144 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR89,Interrupt Processor Targets Registers" line.long 0x148 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR90,Interrupt Processor Targets Registers" line.long 0x14C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR91,Interrupt Processor Targets Registers" line.long 0x150 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR92,Interrupt Processor Targets Registers" line.long 0x154 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR93,Interrupt Processor Targets Registers" line.long 0x158 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR94,Interrupt Processor Targets Registers" line.long 0x15C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR95,Interrupt Processor Targets Registers" line.long 0x160 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR96,Interrupt Processor Targets Registers" line.long 0x164 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR97,Interrupt Processor Targets Registers" line.long 0x168 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR98,Interrupt Processor Targets Registers" line.long 0x16C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR99,Interrupt Processor Targets Registers" line.long 0x170 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR100,Interrupt Processor Targets Registers" line.long 0x174 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR101,Interrupt Processor Targets Registers" line.long 0x178 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR102,Interrupt Processor Targets Registers" line.long 0x17C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR103,Interrupt Processor Targets Registers" line.long 0x180 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR104,Interrupt Processor Targets Registers" line.long 0x184 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR105,Interrupt Processor Targets Registers" line.long 0x188 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR106,Interrupt Processor Targets Registers" line.long 0x18C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR107,Interrupt Processor Targets Registers" line.long 0x190 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR108,Interrupt Processor Targets Registers" line.long 0x194 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR109,Interrupt Processor Targets Registers" line.long 0x198 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR110,Interrupt Processor Targets Registers" line.long 0x19C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR111,Interrupt Processor Targets Registers" line.long 0x1A0 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR112,Interrupt Processor Targets Registers" line.long 0x1A4 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR113,Interrupt Processor Targets Registers" line.long 0x1A8 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR114,Interrupt Processor Targets Registers" line.long 0x1AC "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR115,Interrupt Processor Targets Registers" line.long 0x1B0 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR116,Interrupt Processor Targets Registers" line.long 0x1B4 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR117,Interrupt Processor Targets Registers" line.long 0x1B8 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR118,Interrupt Processor Targets Registers" line.long 0x1BC "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR119,Interrupt Processor Targets Registers" line.long 0x1C0 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR120,Interrupt Processor Targets Registers" line.long 0x1C4 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR121,Interrupt Processor Targets Registers" line.long 0x1C8 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR122,Interrupt Processor Targets Registers" line.long 0x1CC "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR123,Interrupt Processor Targets Registers" line.long 0x1D0 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR124,Interrupt Processor Targets Registers" line.long 0x1D4 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR125,Interrupt Processor Targets Registers" line.long 0x1D8 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR126,Interrupt Processor Targets Registers" line.long 0x1DC "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR127,Interrupt Processor Targets Registers" line.long 0x1E0 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR128,Interrupt Processor Targets Registers" line.long 0x1E4 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR129,Interrupt Processor Targets Registers" line.long 0x1E8 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR130,Interrupt Processor Targets Registers" line.long 0x1EC "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR131,Interrupt Processor Targets Registers" line.long 0x1F0 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR132,Interrupt Processor Targets Registers" line.long 0x1F4 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR133,Interrupt Processor Targets Registers" line.long 0x1F8 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR134,Interrupt Processor Targets Registers" line.long 0x1FC "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR135,Interrupt Processor Targets Registers" line.long 0x200 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR136,Interrupt Processor Targets Registers" line.long 0x204 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR137,Interrupt Processor Targets Registers" line.long 0x208 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR138,Interrupt Processor Targets Registers" line.long 0x20C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR139,Interrupt Processor Targets Registers" line.long 0x210 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR140,Interrupt Processor Targets Registers" line.long 0x214 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR141,Interrupt Processor Targets Registers" line.long 0x218 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR142,Interrupt Processor Targets Registers" line.long 0x21C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR143,Interrupt Processor Targets Registers" line.long 0x220 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR144,Interrupt Processor Targets Registers" line.long 0x224 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR145,Interrupt Processor Targets Registers" line.long 0x228 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR146,Interrupt Processor Targets Registers" line.long 0x22C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR147,Interrupt Processor Targets Registers" line.long 0x230 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR148,Interrupt Processor Targets Registers" line.long 0x234 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR149,Interrupt Processor Targets Registers" line.long 0x238 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR150,Interrupt Processor Targets Registers" line.long 0x23C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR151,Interrupt Processor Targets Registers" line.long 0x240 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR152,Interrupt Processor Targets Registers" line.long 0x244 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR153,Interrupt Processor Targets Registers" line.long 0x248 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR154,Interrupt Processor Targets Registers" line.long 0x24C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR155,Interrupt Processor Targets Registers" line.long 0x250 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR156,Interrupt Processor Targets Registers" line.long 0x254 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR157,Interrupt Processor Targets Registers" line.long 0x258 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR158,Interrupt Processor Targets Registers" line.long 0x25C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR159,Interrupt Processor Targets Registers" line.long 0x260 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR160,Interrupt Processor Targets Registers" line.long 0x264 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR161,Interrupt Processor Targets Registers" line.long 0x268 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR162,Interrupt Processor Targets Registers" line.long 0x26C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR163,Interrupt Processor Targets Registers" line.long 0x270 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR164,Interrupt Processor Targets Registers" line.long 0x274 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR165,Interrupt Processor Targets Registers" line.long 0x278 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR166,Interrupt Processor Targets Registers" line.long 0x27C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR167,Interrupt Processor Targets Registers" line.long 0x280 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR168,Interrupt Processor Targets Registers" line.long 0x284 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR169,Interrupt Processor Targets Registers" line.long 0x288 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR170,Interrupt Processor Targets Registers" line.long 0x28C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR171,Interrupt Processor Targets Registers" line.long 0x290 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR172,Interrupt Processor Targets Registers" line.long 0x294 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR173,Interrupt Processor Targets Registers" line.long 0x298 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR174,Interrupt Processor Targets Registers" line.long 0x29C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR175,Interrupt Processor Targets Registers" line.long 0x2A0 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR176,Interrupt Processor Targets Registers" line.long 0x2A4 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR177,Interrupt Processor Targets Registers" line.long 0x2A8 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR178,Interrupt Processor Targets Registers" line.long 0x2AC "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR179,Interrupt Processor Targets Registers" line.long 0x2B0 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR180,Interrupt Processor Targets Registers" line.long 0x2B4 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR181,Interrupt Processor Targets Registers" line.long 0x2B8 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR182,Interrupt Processor Targets Registers" line.long 0x2BC "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR183,Interrupt Processor Targets Registers" line.long 0x2C0 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR184,Interrupt Processor Targets Registers" line.long 0x2C4 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR185,Interrupt Processor Targets Registers" line.long 0x2C8 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR186,Interrupt Processor Targets Registers" line.long 0x2CC "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR187,Interrupt Processor Targets Registers" line.long 0x2D0 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR188,Interrupt Processor Targets Registers" line.long 0x2D4 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR189,Interrupt Processor Targets Registers" line.long 0x2D8 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR190,Interrupt Processor Targets Registers" line.long 0x2DC "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR191,Interrupt Processor Targets Registers" line.long 0x2E0 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR192,Interrupt Processor Targets Registers" line.long 0x2E4 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR193,Interrupt Processor Targets Registers" line.long 0x2E8 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR194,Interrupt Processor Targets Registers" line.long 0x2EC "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR195,Interrupt Processor Targets Registers" line.long 0x2F0 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR196,Interrupt Processor Targets Registers" line.long 0x2F4 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR197,Interrupt Processor Targets Registers" line.long 0x2F8 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR198,Interrupt Processor Targets Registers" line.long 0x2FC "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR199,Interrupt Processor Targets Registers" line.long 0x300 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR200,Interrupt Processor Targets Registers" line.long 0x304 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR201,Interrupt Processor Targets Registers" line.long 0x308 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR202,Interrupt Processor Targets Registers" line.long 0x30C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR203,Interrupt Processor Targets Registers" line.long 0x310 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR204,Interrupt Processor Targets Registers" line.long 0x314 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR205,Interrupt Processor Targets Registers" line.long 0x318 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR206,Interrupt Processor Targets Registers" line.long 0x31C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR207,Interrupt Processor Targets Registers" line.long 0x320 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR208,Interrupt Processor Targets Registers" line.long 0x324 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR209,Interrupt Processor Targets Registers" line.long 0x328 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR210,Interrupt Processor Targets Registers" line.long 0x32C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR211,Interrupt Processor Targets Registers" line.long 0x330 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR212,Interrupt Processor Targets Registers" line.long 0x334 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR213,Interrupt Processor Targets Registers" line.long 0x338 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR214,Interrupt Processor Targets Registers" line.long 0x33C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR215,Interrupt Processor Targets Registers" line.long 0x340 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR216,Interrupt Processor Targets Registers" line.long 0x344 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR217,Interrupt Processor Targets Registers" line.long 0x348 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR218,Interrupt Processor Targets Registers" line.long 0x34C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR219,Interrupt Processor Targets Registers" line.long 0x350 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR220,Interrupt Processor Targets Registers" line.long 0x354 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR221,Interrupt Processor Targets Registers" line.long 0x358 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR222,Interrupt Processor Targets Registers" line.long 0x35C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR223,Interrupt Processor Targets Registers" line.long 0x360 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR224,Interrupt Processor Targets Registers" line.long 0x364 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR225,Interrupt Processor Targets Registers" line.long 0x368 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR226,Interrupt Processor Targets Registers" line.long 0x36C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR227,Interrupt Processor Targets Registers" line.long 0x370 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR228,Interrupt Processor Targets Registers" line.long 0x374 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR229,Interrupt Processor Targets Registers" line.long 0x378 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR230,Interrupt Processor Targets Registers" line.long 0x37C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR231,Interrupt Processor Targets Registers" line.long 0x380 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR232,Interrupt Processor Targets Registers" line.long 0x384 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR233,Interrupt Processor Targets Registers" line.long 0x388 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR234,Interrupt Processor Targets Registers" line.long 0x38C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR235,Interrupt Processor Targets Registers" line.long 0x390 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR236,Interrupt Processor Targets Registers" line.long 0x394 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR237,Interrupt Processor Targets Registers" line.long 0x398 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR238,Interrupt Processor Targets Registers" line.long 0x39C "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR239,Interrupt Processor Targets Registers" line.long 0x3A0 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR240,Interrupt Processor Targets Registers" line.long 0x3A4 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR241,Interrupt Processor Targets Registers" line.long 0x3A8 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR242,Interrupt Processor Targets Registers" line.long 0x3AC "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR243,Interrupt Processor Targets Registers" line.long 0x3B0 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR244,Interrupt Processor Targets Registers" line.long 0x3B4 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR245,Interrupt Processor Targets Registers" line.long 0x3B8 "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR246,Interrupt Processor Targets Registers" line.long 0x3BC "GIC_DISTRIBUTOR_Distributor__26_GICD_ITARGETSR247,Interrupt Processor Targets Registers" rgroup.long 0xC08++0xEF line.long 0x0 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR2,Interrupt Configuration Registers" line.long 0x4 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR3,Interrupt Configuration Registers" line.long 0x8 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR4,Interrupt Configuration Registers" line.long 0xC "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR5,Interrupt Configuration Registers" line.long 0x10 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR6,Interrupt Configuration Registers" line.long 0x14 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR7,Interrupt Configuration Registers" line.long 0x18 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR8,Interrupt Configuration Registers" line.long 0x1C "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR9,Interrupt Configuration Registers" line.long 0x20 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR10,Interrupt Configuration Registers" line.long 0x24 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR11,Interrupt Configuration Registers" line.long 0x28 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR12,Interrupt Configuration Registers" line.long 0x2C "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR13,Interrupt Configuration Registers" line.long 0x30 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR14,Interrupt Configuration Registers" line.long 0x34 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR15,Interrupt Configuration Registers" line.long 0x38 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR16,Interrupt Configuration Registers" line.long 0x3C "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR17,Interrupt Configuration Registers" line.long 0x40 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR18,Interrupt Configuration Registers" line.long 0x44 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR19,Interrupt Configuration Registers" line.long 0x48 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR20,Interrupt Configuration Registers" line.long 0x4C "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR21,Interrupt Configuration Registers" line.long 0x50 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR22,Interrupt Configuration Registers" line.long 0x54 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR23,Interrupt Configuration Registers" line.long 0x58 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR24,Interrupt Configuration Registers" line.long 0x5C "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR25,Interrupt Configuration Registers" line.long 0x60 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR26,Interrupt Configuration Registers" line.long 0x64 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR27,Interrupt Configuration Registers" line.long 0x68 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR28,Interrupt Configuration Registers" line.long 0x6C "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR29,Interrupt Configuration Registers" line.long 0x70 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR30,Interrupt Configuration Registers" line.long 0x74 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR31,Interrupt Configuration Registers" line.long 0x78 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR32,Interrupt Configuration Registers" line.long 0x7C "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR33,Interrupt Configuration Registers" line.long 0x80 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR34,Interrupt Configuration Registers" line.long 0x84 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR35,Interrupt Configuration Registers" line.long 0x88 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR36,Interrupt Configuration Registers" line.long 0x8C "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR37,Interrupt Configuration Registers" line.long 0x90 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR38,Interrupt Configuration Registers" line.long 0x94 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR39,Interrupt Configuration Registers" line.long 0x98 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR40,Interrupt Configuration Registers" line.long 0x9C "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR41,Interrupt Configuration Registers" line.long 0xA0 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR42,Interrupt Configuration Registers" line.long 0xA4 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR43,Interrupt Configuration Registers" line.long 0xA8 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR44,Interrupt Configuration Registers" line.long 0xAC "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR45,Interrupt Configuration Registers" line.long 0xB0 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR46,Interrupt Configuration Registers" line.long 0xB4 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR47,Interrupt Configuration Registers" line.long 0xB8 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR48,Interrupt Configuration Registers" line.long 0xBC "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR49,Interrupt Configuration Registers" line.long 0xC0 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR50,Interrupt Configuration Registers" line.long 0xC4 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR51,Interrupt Configuration Registers" line.long 0xC8 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR52,Interrupt Configuration Registers" line.long 0xCC "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR53,Interrupt Configuration Registers" line.long 0xD0 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR54,Interrupt Configuration Registers" line.long 0xD4 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR55,Interrupt Configuration Registers" line.long 0xD8 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR56,Interrupt Configuration Registers" line.long 0xDC "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR57,Interrupt Configuration Registers" line.long 0xE0 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR58,Interrupt Configuration Registers" line.long 0xE4 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR59,Interrupt Configuration Registers" line.long 0xE8 "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR60,Interrupt Configuration Registers" line.long 0xEC "GIC_DISTRIBUTOR_Distributor__29_GICD_ICFGR61,Interrupt Configuration Registers" rgroup.long 0xD00++0x7B line.long 0x0 "GIC_DISTRIBUTOR_Distributor__30_GICD_IGRPMODR0,Interrupt Group Modifier Registers" line.long 0x4 "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR1,Interrupt Group Modifier Registers" line.long 0x8 "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR2,Interrupt Group Modifier Registers" line.long 0xC "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR3,Interrupt Group Modifier Registers" line.long 0x10 "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR4,Interrupt Group Modifier Registers" line.long 0x14 "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR5,Interrupt Group Modifier Registers" line.long 0x18 "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR6,Interrupt Group Modifier Registers" line.long 0x1C "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR7,Interrupt Group Modifier Registers" line.long 0x20 "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR8,Interrupt Group Modifier Registers" line.long 0x24 "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR9,Interrupt Group Modifier Registers" line.long 0x28 "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR10,Interrupt Group Modifier Registers" line.long 0x2C "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR11,Interrupt Group Modifier Registers" line.long 0x30 "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR12,Interrupt Group Modifier Registers" line.long 0x34 "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR13,Interrupt Group Modifier Registers" line.long 0x38 "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR14,Interrupt Group Modifier Registers" line.long 0x3C "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR15,Interrupt Group Modifier Registers" line.long 0x40 "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR16,Interrupt Group Modifier Registers" line.long 0x44 "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR17,Interrupt Group Modifier Registers" line.long 0x48 "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR18,Interrupt Group Modifier Registers" line.long 0x4C "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR19,Interrupt Group Modifier Registers" line.long 0x50 "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR20,Interrupt Group Modifier Registers" line.long 0x54 "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR21,Interrupt Group Modifier Registers" line.long 0x58 "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR22,Interrupt Group Modifier Registers" line.long 0x5C "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR23,Interrupt Group Modifier Registers" line.long 0x60 "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR24,Interrupt Group Modifier Registers" line.long 0x64 "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR25,Interrupt Group Modifier Registers" line.long 0x68 "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR26,Interrupt Group Modifier Registers" line.long 0x6C "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR27,Interrupt Group Modifier Registers" line.long 0x70 "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR28,Interrupt Group Modifier Registers" line.long 0x74 "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR29,Interrupt Group Modifier Registers" line.long 0x78 "GIC_DISTRIBUTOR_Distributor__31_GICD_IGRPMODR30,Interrupt Group Modifier Registers" rgroup.long 0xE00++0xF7 line.long 0x0 "GIC_DISTRIBUTOR_Distributor__32_GICD_NSACR0,Non-Secure Access Control Registers" line.long 0x4 "GIC_DISTRIBUTOR_Distributor__32_GICD_NSACR1,Non-Secure Access Control Registers" line.long 0x8 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR2,Non-Secure Access Control Registers" line.long 0xC "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR3,Non-Secure Access Control Registers" line.long 0x10 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR4,Non-Secure Access Control Registers" line.long 0x14 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR5,Non-Secure Access Control Registers" line.long 0x18 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR6,Non-Secure Access Control Registers" line.long 0x1C "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR7,Non-Secure Access Control Registers" line.long 0x20 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR8,Non-Secure Access Control Registers" line.long 0x24 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR9,Non-Secure Access Control Registers" line.long 0x28 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR10,Non-Secure Access Control Registers" line.long 0x2C "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR11,Non-Secure Access Control Registers" line.long 0x30 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR12,Non-Secure Access Control Registers" line.long 0x34 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR13,Non-Secure Access Control Registers" line.long 0x38 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR14,Non-Secure Access Control Registers" line.long 0x3C "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR15,Non-Secure Access Control Registers" line.long 0x40 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR16,Non-Secure Access Control Registers" line.long 0x44 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR17,Non-Secure Access Control Registers" line.long 0x48 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR18,Non-Secure Access Control Registers" line.long 0x4C "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR19,Non-Secure Access Control Registers" line.long 0x50 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR20,Non-Secure Access Control Registers" line.long 0x54 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR21,Non-Secure Access Control Registers" line.long 0x58 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR22,Non-Secure Access Control Registers" line.long 0x5C "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR23,Non-Secure Access Control Registers" line.long 0x60 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR24,Non-Secure Access Control Registers" line.long 0x64 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR25,Non-Secure Access Control Registers" line.long 0x68 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR26,Non-Secure Access Control Registers" line.long 0x6C "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR27,Non-Secure Access Control Registers" line.long 0x70 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR28,Non-Secure Access Control Registers" line.long 0x74 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR29,Non-Secure Access Control Registers" line.long 0x78 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR30,Non-Secure Access Control Registers" line.long 0x7C "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR31,Non-Secure Access Control Registers" line.long 0x80 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR32,Non-Secure Access Control Registers" line.long 0x84 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR33,Non-Secure Access Control Registers" line.long 0x88 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR34,Non-Secure Access Control Registers" line.long 0x8C "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR35,Non-Secure Access Control Registers" line.long 0x90 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR36,Non-Secure Access Control Registers" line.long 0x94 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR37,Non-Secure Access Control Registers" line.long 0x98 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR38,Non-Secure Access Control Registers" line.long 0x9C "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR39,Non-Secure Access Control Registers" line.long 0xA0 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR40,Non-Secure Access Control Registers" line.long 0xA4 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR41,Non-Secure Access Control Registers" line.long 0xA8 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR42,Non-Secure Access Control Registers" line.long 0xAC "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR43,Non-Secure Access Control Registers" line.long 0xB0 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR44,Non-Secure Access Control Registers" line.long 0xB4 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR45,Non-Secure Access Control Registers" line.long 0xB8 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR46,Non-Secure Access Control Registers" line.long 0xBC "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR47,Non-Secure Access Control Registers" line.long 0xC0 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR48,Non-Secure Access Control Registers" line.long 0xC4 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR49,Non-Secure Access Control Registers" line.long 0xC8 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR50,Non-Secure Access Control Registers" line.long 0xCC "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR51,Non-Secure Access Control Registers" line.long 0xD0 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR52,Non-Secure Access Control Registers" line.long 0xD4 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR53,Non-Secure Access Control Registers" line.long 0xD8 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR54,Non-Secure Access Control Registers" line.long 0xDC "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR55,Non-Secure Access Control Registers" line.long 0xE0 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR56,Non-Secure Access Control Registers" line.long 0xE4 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR57,Non-Secure Access Control Registers" line.long 0xE8 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR58,Non-Secure Access Control Registers" line.long 0xEC "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR59,Non-Secure Access Control Registers" line.long 0xF0 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR60,Non-Secure Access Control Registers" line.long 0xF4 "GIC_DISTRIBUTOR_Distributor__33_GICD_NSACR61,Non-Secure Access Control Registers" rgroup.long 0x6100++0xFFF line.long 0x0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER32_lower,Interrupt Routing Registers" bitfld.long 0x0 31. "DISTRIBUTOR__37_GICD_IROUTER32_LOWER__31_1," "0,1" hexmask.long.byte 0x0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER32_LOWER__8_8," newline hexmask.long.byte 0x0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER32_LOWER__0_8," line.long 0x4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER32_upper,Interrupt Routing Registers" line.long 0x8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER33_lower,Interrupt Routing Registers" bitfld.long 0x8 31. "DISTRIBUTOR__37_GICD_IROUTER33_LOWER__31_1," "0,1" hexmask.long.byte 0x8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER33_LOWER__8_8," newline hexmask.long.byte 0x8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER33_LOWER__0_8," line.long 0xC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER33_upper,Interrupt Routing Registers" line.long 0x10 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER34_lower,Interrupt Routing Registers" bitfld.long 0x10 31. "DISTRIBUTOR__37_GICD_IROUTER34_LOWER__31_1," "0,1" hexmask.long.byte 0x10 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER34_LOWER__8_8," newline hexmask.long.byte 0x10 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER34_LOWER__0_8," line.long 0x14 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER34_upper,Interrupt Routing Registers" line.long 0x18 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER35_lower,Interrupt Routing Registers" bitfld.long 0x18 31. "DISTRIBUTOR__37_GICD_IROUTER35_LOWER__31_1," "0,1" hexmask.long.byte 0x18 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER35_LOWER__8_8," newline hexmask.long.byte 0x18 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER35_LOWER__0_8," line.long 0x1C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER35_upper,Interrupt Routing Registers" line.long 0x20 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER36_lower,Interrupt Routing Registers" bitfld.long 0x20 31. "DISTRIBUTOR__37_GICD_IROUTER36_LOWER__31_1," "0,1" hexmask.long.byte 0x20 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER36_LOWER__8_8," newline hexmask.long.byte 0x20 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER36_LOWER__0_8," line.long 0x24 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER36_upper,Interrupt Routing Registers" line.long 0x28 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER37_lower,Interrupt Routing Registers" bitfld.long 0x28 31. "DISTRIBUTOR__37_GICD_IROUTER37_LOWER__31_1," "0,1" hexmask.long.byte 0x28 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER37_LOWER__8_8," newline hexmask.long.byte 0x28 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER37_LOWER__0_8," line.long 0x2C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER37_upper,Interrupt Routing Registers" line.long 0x30 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER38_lower,Interrupt Routing Registers" bitfld.long 0x30 31. "DISTRIBUTOR__37_GICD_IROUTER38_LOWER__31_1," "0,1" hexmask.long.byte 0x30 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER38_LOWER__8_8," newline hexmask.long.byte 0x30 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER38_LOWER__0_8," line.long 0x34 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER38_upper,Interrupt Routing Registers" line.long 0x38 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER39_lower,Interrupt Routing Registers" bitfld.long 0x38 31. "DISTRIBUTOR__37_GICD_IROUTER39_LOWER__31_1," "0,1" hexmask.long.byte 0x38 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER39_LOWER__8_8," newline hexmask.long.byte 0x38 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER39_LOWER__0_8," line.long 0x3C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER39_upper,Interrupt Routing Registers" line.long 0x40 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER40_lower,Interrupt Routing Registers" bitfld.long 0x40 31. "DISTRIBUTOR__37_GICD_IROUTER40_LOWER__31_1," "0,1" hexmask.long.byte 0x40 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER40_LOWER__8_8," newline hexmask.long.byte 0x40 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER40_LOWER__0_8," line.long 0x44 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER40_upper,Interrupt Routing Registers" line.long 0x48 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER41_lower,Interrupt Routing Registers" bitfld.long 0x48 31. "DISTRIBUTOR__37_GICD_IROUTER41_LOWER__31_1," "0,1" hexmask.long.byte 0x48 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER41_LOWER__8_8," newline hexmask.long.byte 0x48 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER41_LOWER__0_8," line.long 0x4C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER41_upper,Interrupt Routing Registers" line.long 0x50 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER42_lower,Interrupt Routing Registers" bitfld.long 0x50 31. "DISTRIBUTOR__37_GICD_IROUTER42_LOWER__31_1," "0,1" hexmask.long.byte 0x50 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER42_LOWER__8_8," newline hexmask.long.byte 0x50 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER42_LOWER__0_8," line.long 0x54 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER42_upper,Interrupt Routing Registers" line.long 0x58 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER43_lower,Interrupt Routing Registers" bitfld.long 0x58 31. "DISTRIBUTOR__37_GICD_IROUTER43_LOWER__31_1," "0,1" hexmask.long.byte 0x58 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER43_LOWER__8_8," newline hexmask.long.byte 0x58 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER43_LOWER__0_8," line.long 0x5C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER43_upper,Interrupt Routing Registers" line.long 0x60 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER44_lower,Interrupt Routing Registers" bitfld.long 0x60 31. "DISTRIBUTOR__37_GICD_IROUTER44_LOWER__31_1," "0,1" hexmask.long.byte 0x60 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER44_LOWER__8_8," newline hexmask.long.byte 0x60 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER44_LOWER__0_8," line.long 0x64 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER44_upper,Interrupt Routing Registers" line.long 0x68 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER45_lower,Interrupt Routing Registers" bitfld.long 0x68 31. "DISTRIBUTOR__37_GICD_IROUTER45_LOWER__31_1," "0,1" hexmask.long.byte 0x68 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER45_LOWER__8_8," newline hexmask.long.byte 0x68 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER45_LOWER__0_8," line.long 0x6C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER45_upper,Interrupt Routing Registers" line.long 0x70 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER46_lower,Interrupt Routing Registers" bitfld.long 0x70 31. "DISTRIBUTOR__37_GICD_IROUTER46_LOWER__31_1," "0,1" hexmask.long.byte 0x70 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER46_LOWER__8_8," newline hexmask.long.byte 0x70 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER46_LOWER__0_8," line.long 0x74 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER46_upper,Interrupt Routing Registers" line.long 0x78 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER47_lower,Interrupt Routing Registers" bitfld.long 0x78 31. "DISTRIBUTOR__37_GICD_IROUTER47_LOWER__31_1," "0,1" hexmask.long.byte 0x78 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER47_LOWER__8_8," newline hexmask.long.byte 0x78 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER47_LOWER__0_8," line.long 0x7C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER47_upper,Interrupt Routing Registers" line.long 0x80 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER48_lower,Interrupt Routing Registers" bitfld.long 0x80 31. "DISTRIBUTOR__37_GICD_IROUTER48_LOWER__31_1," "0,1" hexmask.long.byte 0x80 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER48_LOWER__8_8," newline hexmask.long.byte 0x80 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER48_LOWER__0_8," line.long 0x84 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER48_upper,Interrupt Routing Registers" line.long 0x88 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER49_lower,Interrupt Routing Registers" bitfld.long 0x88 31. "DISTRIBUTOR__37_GICD_IROUTER49_LOWER__31_1," "0,1" hexmask.long.byte 0x88 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER49_LOWER__8_8," newline hexmask.long.byte 0x88 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER49_LOWER__0_8," line.long 0x8C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER49_upper,Interrupt Routing Registers" line.long 0x90 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER50_lower,Interrupt Routing Registers" bitfld.long 0x90 31. "DISTRIBUTOR__37_GICD_IROUTER50_LOWER__31_1," "0,1" hexmask.long.byte 0x90 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER50_LOWER__8_8," newline hexmask.long.byte 0x90 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER50_LOWER__0_8," line.long 0x94 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER50_upper,Interrupt Routing Registers" line.long 0x98 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER51_lower,Interrupt Routing Registers" bitfld.long 0x98 31. "DISTRIBUTOR__37_GICD_IROUTER51_LOWER__31_1," "0,1" hexmask.long.byte 0x98 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER51_LOWER__8_8," newline hexmask.long.byte 0x98 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER51_LOWER__0_8," line.long 0x9C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER51_upper,Interrupt Routing Registers" line.long 0xA0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER52_lower,Interrupt Routing Registers" bitfld.long 0xA0 31. "DISTRIBUTOR__37_GICD_IROUTER52_LOWER__31_1," "0,1" hexmask.long.byte 0xA0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER52_LOWER__8_8," newline hexmask.long.byte 0xA0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER52_LOWER__0_8," line.long 0xA4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER52_upper,Interrupt Routing Registers" line.long 0xA8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER53_lower,Interrupt Routing Registers" bitfld.long 0xA8 31. "DISTRIBUTOR__37_GICD_IROUTER53_LOWER__31_1," "0,1" hexmask.long.byte 0xA8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER53_LOWER__8_8," newline hexmask.long.byte 0xA8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER53_LOWER__0_8," line.long 0xAC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER53_upper,Interrupt Routing Registers" line.long 0xB0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER54_lower,Interrupt Routing Registers" bitfld.long 0xB0 31. "DISTRIBUTOR__37_GICD_IROUTER54_LOWER__31_1," "0,1" hexmask.long.byte 0xB0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER54_LOWER__8_8," newline hexmask.long.byte 0xB0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER54_LOWER__0_8," line.long 0xB4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER54_upper,Interrupt Routing Registers" line.long 0xB8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER55_lower,Interrupt Routing Registers" bitfld.long 0xB8 31. "DISTRIBUTOR__37_GICD_IROUTER55_LOWER__31_1," "0,1" hexmask.long.byte 0xB8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER55_LOWER__8_8," newline hexmask.long.byte 0xB8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER55_LOWER__0_8," line.long 0xBC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER55_upper,Interrupt Routing Registers" line.long 0xC0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER56_lower,Interrupt Routing Registers" bitfld.long 0xC0 31. "DISTRIBUTOR__37_GICD_IROUTER56_LOWER__31_1," "0,1" hexmask.long.byte 0xC0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER56_LOWER__8_8," newline hexmask.long.byte 0xC0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER56_LOWER__0_8," line.long 0xC4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER56_upper,Interrupt Routing Registers" line.long 0xC8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER57_lower,Interrupt Routing Registers" bitfld.long 0xC8 31. "DISTRIBUTOR__37_GICD_IROUTER57_LOWER__31_1," "0,1" hexmask.long.byte 0xC8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER57_LOWER__8_8," newline hexmask.long.byte 0xC8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER57_LOWER__0_8," line.long 0xCC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER57_upper,Interrupt Routing Registers" line.long 0xD0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER58_lower,Interrupt Routing Registers" bitfld.long 0xD0 31. "DISTRIBUTOR__37_GICD_IROUTER58_LOWER__31_1," "0,1" hexmask.long.byte 0xD0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER58_LOWER__8_8," newline hexmask.long.byte 0xD0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER58_LOWER__0_8," line.long 0xD4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER58_upper,Interrupt Routing Registers" line.long 0xD8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER59_lower,Interrupt Routing Registers" bitfld.long 0xD8 31. "DISTRIBUTOR__37_GICD_IROUTER59_LOWER__31_1," "0,1" hexmask.long.byte 0xD8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER59_LOWER__8_8," newline hexmask.long.byte 0xD8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER59_LOWER__0_8," line.long 0xDC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER59_upper,Interrupt Routing Registers" line.long 0xE0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER60_lower,Interrupt Routing Registers" bitfld.long 0xE0 31. "DISTRIBUTOR__37_GICD_IROUTER60_LOWER__31_1," "0,1" hexmask.long.byte 0xE0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER60_LOWER__8_8," newline hexmask.long.byte 0xE0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER60_LOWER__0_8," line.long 0xE4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER60_upper,Interrupt Routing Registers" line.long 0xE8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER61_lower,Interrupt Routing Registers" bitfld.long 0xE8 31. "DISTRIBUTOR__37_GICD_IROUTER61_LOWER__31_1," "0,1" hexmask.long.byte 0xE8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER61_LOWER__8_8," newline hexmask.long.byte 0xE8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER61_LOWER__0_8," line.long 0xEC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER61_upper,Interrupt Routing Registers" line.long 0xF0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER62_lower,Interrupt Routing Registers" bitfld.long 0xF0 31. "DISTRIBUTOR__37_GICD_IROUTER62_LOWER__31_1," "0,1" hexmask.long.byte 0xF0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER62_LOWER__8_8," newline hexmask.long.byte 0xF0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER62_LOWER__0_8," line.long 0xF4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER62_upper,Interrupt Routing Registers" line.long 0xF8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER63_lower,Interrupt Routing Registers" bitfld.long 0xF8 31. "DISTRIBUTOR__37_GICD_IROUTER63_LOWER__31_1," "0,1" hexmask.long.byte 0xF8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER63_LOWER__8_8," newline hexmask.long.byte 0xF8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER63_LOWER__0_8," line.long 0xFC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER63_upper,Interrupt Routing Registers" line.long 0x100 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER64_lower,Interrupt Routing Registers" bitfld.long 0x100 31. "DISTRIBUTOR__37_GICD_IROUTER64_LOWER__31_1," "0,1" hexmask.long.byte 0x100 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER64_LOWER__8_8," newline hexmask.long.byte 0x100 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER64_LOWER__0_8," line.long 0x104 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER64_upper,Interrupt Routing Registers" line.long 0x108 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER65_lower,Interrupt Routing Registers" bitfld.long 0x108 31. "DISTRIBUTOR__37_GICD_IROUTER65_LOWER__31_1," "0,1" hexmask.long.byte 0x108 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER65_LOWER__8_8," newline hexmask.long.byte 0x108 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER65_LOWER__0_8," line.long 0x10C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER65_upper,Interrupt Routing Registers" line.long 0x110 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER66_lower,Interrupt Routing Registers" bitfld.long 0x110 31. "DISTRIBUTOR__37_GICD_IROUTER66_LOWER__31_1," "0,1" hexmask.long.byte 0x110 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER66_LOWER__8_8," newline hexmask.long.byte 0x110 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER66_LOWER__0_8," line.long 0x114 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER66_upper,Interrupt Routing Registers" line.long 0x118 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER67_lower,Interrupt Routing Registers" bitfld.long 0x118 31. "DISTRIBUTOR__37_GICD_IROUTER67_LOWER__31_1," "0,1" hexmask.long.byte 0x118 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER67_LOWER__8_8," newline hexmask.long.byte 0x118 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER67_LOWER__0_8," line.long 0x11C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER67_upper,Interrupt Routing Registers" line.long 0x120 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER68_lower,Interrupt Routing Registers" bitfld.long 0x120 31. "DISTRIBUTOR__37_GICD_IROUTER68_LOWER__31_1," "0,1" hexmask.long.byte 0x120 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER68_LOWER__8_8," newline hexmask.long.byte 0x120 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER68_LOWER__0_8," line.long 0x124 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER68_upper,Interrupt Routing Registers" line.long 0x128 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER69_lower,Interrupt Routing Registers" bitfld.long 0x128 31. "DISTRIBUTOR__37_GICD_IROUTER69_LOWER__31_1," "0,1" hexmask.long.byte 0x128 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER69_LOWER__8_8," newline hexmask.long.byte 0x128 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER69_LOWER__0_8," line.long 0x12C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER69_upper,Interrupt Routing Registers" line.long 0x130 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER70_lower,Interrupt Routing Registers" bitfld.long 0x130 31. "DISTRIBUTOR__37_GICD_IROUTER70_LOWER__31_1," "0,1" hexmask.long.byte 0x130 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER70_LOWER__8_8," newline hexmask.long.byte 0x130 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER70_LOWER__0_8," line.long 0x134 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER70_upper,Interrupt Routing Registers" line.long 0x138 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER71_lower,Interrupt Routing Registers" bitfld.long 0x138 31. "DISTRIBUTOR__37_GICD_IROUTER71_LOWER__31_1," "0,1" hexmask.long.byte 0x138 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER71_LOWER__8_8," newline hexmask.long.byte 0x138 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER71_LOWER__0_8," line.long 0x13C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER71_upper,Interrupt Routing Registers" line.long 0x140 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER72_lower,Interrupt Routing Registers" bitfld.long 0x140 31. "DISTRIBUTOR__37_GICD_IROUTER72_LOWER__31_1," "0,1" hexmask.long.byte 0x140 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER72_LOWER__8_8," newline hexmask.long.byte 0x140 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER72_LOWER__0_8," line.long 0x144 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER72_upper,Interrupt Routing Registers" line.long 0x148 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER73_lower,Interrupt Routing Registers" bitfld.long 0x148 31. "DISTRIBUTOR__37_GICD_IROUTER73_LOWER__31_1," "0,1" hexmask.long.byte 0x148 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER73_LOWER__8_8," newline hexmask.long.byte 0x148 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER73_LOWER__0_8," line.long 0x14C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER73_upper,Interrupt Routing Registers" line.long 0x150 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER74_lower,Interrupt Routing Registers" bitfld.long 0x150 31. "DISTRIBUTOR__37_GICD_IROUTER74_LOWER__31_1," "0,1" hexmask.long.byte 0x150 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER74_LOWER__8_8," newline hexmask.long.byte 0x150 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER74_LOWER__0_8," line.long 0x154 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER74_upper,Interrupt Routing Registers" line.long 0x158 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER75_lower,Interrupt Routing Registers" bitfld.long 0x158 31. "DISTRIBUTOR__37_GICD_IROUTER75_LOWER__31_1," "0,1" hexmask.long.byte 0x158 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER75_LOWER__8_8," newline hexmask.long.byte 0x158 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER75_LOWER__0_8," line.long 0x15C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER75_upper,Interrupt Routing Registers" line.long 0x160 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER76_lower,Interrupt Routing Registers" bitfld.long 0x160 31. "DISTRIBUTOR__37_GICD_IROUTER76_LOWER__31_1," "0,1" hexmask.long.byte 0x160 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER76_LOWER__8_8," newline hexmask.long.byte 0x160 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER76_LOWER__0_8," line.long 0x164 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER76_upper,Interrupt Routing Registers" line.long 0x168 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER77_lower,Interrupt Routing Registers" bitfld.long 0x168 31. "DISTRIBUTOR__37_GICD_IROUTER77_LOWER__31_1," "0,1" hexmask.long.byte 0x168 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER77_LOWER__8_8," newline hexmask.long.byte 0x168 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER77_LOWER__0_8," line.long 0x16C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER77_upper,Interrupt Routing Registers" line.long 0x170 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER78_lower,Interrupt Routing Registers" bitfld.long 0x170 31. "DISTRIBUTOR__37_GICD_IROUTER78_LOWER__31_1," "0,1" hexmask.long.byte 0x170 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER78_LOWER__8_8," newline hexmask.long.byte 0x170 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER78_LOWER__0_8," line.long 0x174 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER78_upper,Interrupt Routing Registers" line.long 0x178 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER79_lower,Interrupt Routing Registers" bitfld.long 0x178 31. "DISTRIBUTOR__37_GICD_IROUTER79_LOWER__31_1," "0,1" hexmask.long.byte 0x178 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER79_LOWER__8_8," newline hexmask.long.byte 0x178 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER79_LOWER__0_8," line.long 0x17C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER79_upper,Interrupt Routing Registers" line.long 0x180 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER80_lower,Interrupt Routing Registers" bitfld.long 0x180 31. "DISTRIBUTOR__37_GICD_IROUTER80_LOWER__31_1," "0,1" hexmask.long.byte 0x180 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER80_LOWER__8_8," newline hexmask.long.byte 0x180 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER80_LOWER__0_8," line.long 0x184 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER80_upper,Interrupt Routing Registers" line.long 0x188 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER81_lower,Interrupt Routing Registers" bitfld.long 0x188 31. "DISTRIBUTOR__37_GICD_IROUTER81_LOWER__31_1," "0,1" hexmask.long.byte 0x188 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER81_LOWER__8_8," newline hexmask.long.byte 0x188 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER81_LOWER__0_8," line.long 0x18C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER81_upper,Interrupt Routing Registers" line.long 0x190 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER82_lower,Interrupt Routing Registers" bitfld.long 0x190 31. "DISTRIBUTOR__37_GICD_IROUTER82_LOWER__31_1," "0,1" hexmask.long.byte 0x190 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER82_LOWER__8_8," newline hexmask.long.byte 0x190 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER82_LOWER__0_8," line.long 0x194 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER82_upper,Interrupt Routing Registers" line.long 0x198 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER83_lower,Interrupt Routing Registers" bitfld.long 0x198 31. "DISTRIBUTOR__37_GICD_IROUTER83_LOWER__31_1," "0,1" hexmask.long.byte 0x198 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER83_LOWER__8_8," newline hexmask.long.byte 0x198 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER83_LOWER__0_8," line.long 0x19C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER83_upper,Interrupt Routing Registers" line.long 0x1A0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER84_lower,Interrupt Routing Registers" bitfld.long 0x1A0 31. "DISTRIBUTOR__37_GICD_IROUTER84_LOWER__31_1," "0,1" hexmask.long.byte 0x1A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER84_LOWER__8_8," newline hexmask.long.byte 0x1A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER84_LOWER__0_8," line.long 0x1A4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER84_upper,Interrupt Routing Registers" line.long 0x1A8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER85_lower,Interrupt Routing Registers" bitfld.long 0x1A8 31. "DISTRIBUTOR__37_GICD_IROUTER85_LOWER__31_1," "0,1" hexmask.long.byte 0x1A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER85_LOWER__8_8," newline hexmask.long.byte 0x1A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER85_LOWER__0_8," line.long 0x1AC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER85_upper,Interrupt Routing Registers" line.long 0x1B0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER86_lower,Interrupt Routing Registers" bitfld.long 0x1B0 31. "DISTRIBUTOR__37_GICD_IROUTER86_LOWER__31_1," "0,1" hexmask.long.byte 0x1B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER86_LOWER__8_8," newline hexmask.long.byte 0x1B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER86_LOWER__0_8," line.long 0x1B4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER86_upper,Interrupt Routing Registers" line.long 0x1B8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER87_lower,Interrupt Routing Registers" bitfld.long 0x1B8 31. "DISTRIBUTOR__37_GICD_IROUTER87_LOWER__31_1," "0,1" hexmask.long.byte 0x1B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER87_LOWER__8_8," newline hexmask.long.byte 0x1B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER87_LOWER__0_8," line.long 0x1BC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER87_upper,Interrupt Routing Registers" line.long 0x1C0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER88_lower,Interrupt Routing Registers" bitfld.long 0x1C0 31. "DISTRIBUTOR__37_GICD_IROUTER88_LOWER__31_1," "0,1" hexmask.long.byte 0x1C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER88_LOWER__8_8," newline hexmask.long.byte 0x1C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER88_LOWER__0_8," line.long 0x1C4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER88_upper,Interrupt Routing Registers" line.long 0x1C8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER89_lower,Interrupt Routing Registers" bitfld.long 0x1C8 31. "DISTRIBUTOR__37_GICD_IROUTER89_LOWER__31_1," "0,1" hexmask.long.byte 0x1C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER89_LOWER__8_8," newline hexmask.long.byte 0x1C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER89_LOWER__0_8," line.long 0x1CC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER89_upper,Interrupt Routing Registers" line.long 0x1D0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER90_lower,Interrupt Routing Registers" bitfld.long 0x1D0 31. "DISTRIBUTOR__37_GICD_IROUTER90_LOWER__31_1," "0,1" hexmask.long.byte 0x1D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER90_LOWER__8_8," newline hexmask.long.byte 0x1D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER90_LOWER__0_8," line.long 0x1D4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER90_upper,Interrupt Routing Registers" line.long 0x1D8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER91_lower,Interrupt Routing Registers" bitfld.long 0x1D8 31. "DISTRIBUTOR__37_GICD_IROUTER91_LOWER__31_1," "0,1" hexmask.long.byte 0x1D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER91_LOWER__8_8," newline hexmask.long.byte 0x1D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER91_LOWER__0_8," line.long 0x1DC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER91_upper,Interrupt Routing Registers" line.long 0x1E0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER92_lower,Interrupt Routing Registers" bitfld.long 0x1E0 31. "DISTRIBUTOR__37_GICD_IROUTER92_LOWER__31_1," "0,1" hexmask.long.byte 0x1E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER92_LOWER__8_8," newline hexmask.long.byte 0x1E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER92_LOWER__0_8," line.long 0x1E4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER92_upper,Interrupt Routing Registers" line.long 0x1E8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER93_lower,Interrupt Routing Registers" bitfld.long 0x1E8 31. "DISTRIBUTOR__37_GICD_IROUTER93_LOWER__31_1," "0,1" hexmask.long.byte 0x1E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER93_LOWER__8_8," newline hexmask.long.byte 0x1E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER93_LOWER__0_8," line.long 0x1EC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER93_upper,Interrupt Routing Registers" line.long 0x1F0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER94_lower,Interrupt Routing Registers" bitfld.long 0x1F0 31. "DISTRIBUTOR__37_GICD_IROUTER94_LOWER__31_1," "0,1" hexmask.long.byte 0x1F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER94_LOWER__8_8," newline hexmask.long.byte 0x1F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER94_LOWER__0_8," line.long 0x1F4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER94_upper,Interrupt Routing Registers" line.long 0x1F8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER95_lower,Interrupt Routing Registers" bitfld.long 0x1F8 31. "DISTRIBUTOR__37_GICD_IROUTER95_LOWER__31_1," "0,1" hexmask.long.byte 0x1F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER95_LOWER__8_8," newline hexmask.long.byte 0x1F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER95_LOWER__0_8," line.long 0x1FC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER95_upper,Interrupt Routing Registers" line.long 0x200 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER96_lower,Interrupt Routing Registers" bitfld.long 0x200 31. "DISTRIBUTOR__37_GICD_IROUTER96_LOWER__31_1," "0,1" hexmask.long.byte 0x200 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER96_LOWER__8_8," newline hexmask.long.byte 0x200 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER96_LOWER__0_8," line.long 0x204 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER96_upper,Interrupt Routing Registers" line.long 0x208 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER97_lower,Interrupt Routing Registers" bitfld.long 0x208 31. "DISTRIBUTOR__37_GICD_IROUTER97_LOWER__31_1," "0,1" hexmask.long.byte 0x208 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER97_LOWER__8_8," newline hexmask.long.byte 0x208 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER97_LOWER__0_8," line.long 0x20C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER97_upper,Interrupt Routing Registers" line.long 0x210 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER98_lower,Interrupt Routing Registers" bitfld.long 0x210 31. "DISTRIBUTOR__37_GICD_IROUTER98_LOWER__31_1," "0,1" hexmask.long.byte 0x210 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER98_LOWER__8_8," newline hexmask.long.byte 0x210 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER98_LOWER__0_8," line.long 0x214 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER98_upper,Interrupt Routing Registers" line.long 0x218 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER99_lower,Interrupt Routing Registers" bitfld.long 0x218 31. "DISTRIBUTOR__37_GICD_IROUTER99_LOWER__31_1," "0,1" hexmask.long.byte 0x218 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER99_LOWER__8_8," newline hexmask.long.byte 0x218 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER99_LOWER__0_8," line.long 0x21C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER99_upper,Interrupt Routing Registers" line.long 0x220 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER100_lower,Interrupt Routing Registers" bitfld.long 0x220 31. "DISTRIBUTOR__37_GICD_IROUTER100_LOWER__31_1," "0,1" hexmask.long.byte 0x220 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER100_LOWER__8_8," newline hexmask.long.byte 0x220 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER100_LOWER__0_8," line.long 0x224 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER100_upper,Interrupt Routing Registers" line.long 0x228 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER101_lower,Interrupt Routing Registers" bitfld.long 0x228 31. "DISTRIBUTOR__37_GICD_IROUTER101_LOWER__31_1," "0,1" hexmask.long.byte 0x228 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER101_LOWER__8_8," newline hexmask.long.byte 0x228 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER101_LOWER__0_8," line.long 0x22C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER101_upper,Interrupt Routing Registers" line.long 0x230 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER102_lower,Interrupt Routing Registers" bitfld.long 0x230 31. "DISTRIBUTOR__37_GICD_IROUTER102_LOWER__31_1," "0,1" hexmask.long.byte 0x230 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER102_LOWER__8_8," newline hexmask.long.byte 0x230 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER102_LOWER__0_8," line.long 0x234 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER102_upper,Interrupt Routing Registers" line.long 0x238 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER103_lower,Interrupt Routing Registers" bitfld.long 0x238 31. "DISTRIBUTOR__37_GICD_IROUTER103_LOWER__31_1," "0,1" hexmask.long.byte 0x238 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER103_LOWER__8_8," newline hexmask.long.byte 0x238 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER103_LOWER__0_8," line.long 0x23C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER103_upper,Interrupt Routing Registers" line.long 0x240 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER104_lower,Interrupt Routing Registers" bitfld.long 0x240 31. "DISTRIBUTOR__37_GICD_IROUTER104_LOWER__31_1," "0,1" hexmask.long.byte 0x240 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER104_LOWER__8_8," newline hexmask.long.byte 0x240 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER104_LOWER__0_8," line.long 0x244 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER104_upper,Interrupt Routing Registers" line.long 0x248 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER105_lower,Interrupt Routing Registers" bitfld.long 0x248 31. "DISTRIBUTOR__37_GICD_IROUTER105_LOWER__31_1," "0,1" hexmask.long.byte 0x248 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER105_LOWER__8_8," newline hexmask.long.byte 0x248 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER105_LOWER__0_8," line.long 0x24C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER105_upper,Interrupt Routing Registers" line.long 0x250 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER106_lower,Interrupt Routing Registers" bitfld.long 0x250 31. "DISTRIBUTOR__37_GICD_IROUTER106_LOWER__31_1," "0,1" hexmask.long.byte 0x250 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER106_LOWER__8_8," newline hexmask.long.byte 0x250 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER106_LOWER__0_8," line.long 0x254 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER106_upper,Interrupt Routing Registers" line.long 0x258 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER107_lower,Interrupt Routing Registers" bitfld.long 0x258 31. "DISTRIBUTOR__37_GICD_IROUTER107_LOWER__31_1," "0,1" hexmask.long.byte 0x258 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER107_LOWER__8_8," newline hexmask.long.byte 0x258 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER107_LOWER__0_8," line.long 0x25C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER107_upper,Interrupt Routing Registers" line.long 0x260 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER108_lower,Interrupt Routing Registers" bitfld.long 0x260 31. "DISTRIBUTOR__37_GICD_IROUTER108_LOWER__31_1," "0,1" hexmask.long.byte 0x260 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER108_LOWER__8_8," newline hexmask.long.byte 0x260 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER108_LOWER__0_8," line.long 0x264 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER108_upper,Interrupt Routing Registers" line.long 0x268 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER109_lower,Interrupt Routing Registers" bitfld.long 0x268 31. "DISTRIBUTOR__37_GICD_IROUTER109_LOWER__31_1," "0,1" hexmask.long.byte 0x268 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER109_LOWER__8_8," newline hexmask.long.byte 0x268 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER109_LOWER__0_8," line.long 0x26C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER109_upper,Interrupt Routing Registers" line.long 0x270 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER110_lower,Interrupt Routing Registers" bitfld.long 0x270 31. "DISTRIBUTOR__37_GICD_IROUTER110_LOWER__31_1," "0,1" hexmask.long.byte 0x270 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER110_LOWER__8_8," newline hexmask.long.byte 0x270 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER110_LOWER__0_8," line.long 0x274 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER110_upper,Interrupt Routing Registers" line.long 0x278 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER111_lower,Interrupt Routing Registers" bitfld.long 0x278 31. "DISTRIBUTOR__37_GICD_IROUTER111_LOWER__31_1," "0,1" hexmask.long.byte 0x278 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER111_LOWER__8_8," newline hexmask.long.byte 0x278 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER111_LOWER__0_8," line.long 0x27C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER111_upper,Interrupt Routing Registers" line.long 0x280 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER112_lower,Interrupt Routing Registers" bitfld.long 0x280 31. "DISTRIBUTOR__37_GICD_IROUTER112_LOWER__31_1," "0,1" hexmask.long.byte 0x280 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER112_LOWER__8_8," newline hexmask.long.byte 0x280 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER112_LOWER__0_8," line.long 0x284 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER112_upper,Interrupt Routing Registers" line.long 0x288 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER113_lower,Interrupt Routing Registers" bitfld.long 0x288 31. "DISTRIBUTOR__37_GICD_IROUTER113_LOWER__31_1," "0,1" hexmask.long.byte 0x288 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER113_LOWER__8_8," newline hexmask.long.byte 0x288 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER113_LOWER__0_8," line.long 0x28C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER113_upper,Interrupt Routing Registers" line.long 0x290 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER114_lower,Interrupt Routing Registers" bitfld.long 0x290 31. "DISTRIBUTOR__37_GICD_IROUTER114_LOWER__31_1," "0,1" hexmask.long.byte 0x290 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER114_LOWER__8_8," newline hexmask.long.byte 0x290 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER114_LOWER__0_8," line.long 0x294 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER114_upper,Interrupt Routing Registers" line.long 0x298 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER115_lower,Interrupt Routing Registers" bitfld.long 0x298 31. "DISTRIBUTOR__37_GICD_IROUTER115_LOWER__31_1," "0,1" hexmask.long.byte 0x298 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER115_LOWER__8_8," newline hexmask.long.byte 0x298 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER115_LOWER__0_8," line.long 0x29C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER115_upper,Interrupt Routing Registers" line.long 0x2A0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER116_lower,Interrupt Routing Registers" bitfld.long 0x2A0 31. "DISTRIBUTOR__37_GICD_IROUTER116_LOWER__31_1," "0,1" hexmask.long.byte 0x2A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER116_LOWER__8_8," newline hexmask.long.byte 0x2A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER116_LOWER__0_8," line.long 0x2A4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER116_upper,Interrupt Routing Registers" line.long 0x2A8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER117_lower,Interrupt Routing Registers" bitfld.long 0x2A8 31. "DISTRIBUTOR__37_GICD_IROUTER117_LOWER__31_1," "0,1" hexmask.long.byte 0x2A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER117_LOWER__8_8," newline hexmask.long.byte 0x2A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER117_LOWER__0_8," line.long 0x2AC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER117_upper,Interrupt Routing Registers" line.long 0x2B0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER118_lower,Interrupt Routing Registers" bitfld.long 0x2B0 31. "DISTRIBUTOR__37_GICD_IROUTER118_LOWER__31_1," "0,1" hexmask.long.byte 0x2B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER118_LOWER__8_8," newline hexmask.long.byte 0x2B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER118_LOWER__0_8," line.long 0x2B4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER118_upper,Interrupt Routing Registers" line.long 0x2B8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER119_lower,Interrupt Routing Registers" bitfld.long 0x2B8 31. "DISTRIBUTOR__37_GICD_IROUTER119_LOWER__31_1," "0,1" hexmask.long.byte 0x2B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER119_LOWER__8_8," newline hexmask.long.byte 0x2B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER119_LOWER__0_8," line.long 0x2BC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER119_upper,Interrupt Routing Registers" line.long 0x2C0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER120_lower,Interrupt Routing Registers" bitfld.long 0x2C0 31. "DISTRIBUTOR__37_GICD_IROUTER120_LOWER__31_1," "0,1" hexmask.long.byte 0x2C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER120_LOWER__8_8," newline hexmask.long.byte 0x2C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER120_LOWER__0_8," line.long 0x2C4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER120_upper,Interrupt Routing Registers" line.long 0x2C8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER121_lower,Interrupt Routing Registers" bitfld.long 0x2C8 31. "DISTRIBUTOR__37_GICD_IROUTER121_LOWER__31_1," "0,1" hexmask.long.byte 0x2C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER121_LOWER__8_8," newline hexmask.long.byte 0x2C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER121_LOWER__0_8," line.long 0x2CC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER121_upper,Interrupt Routing Registers" line.long 0x2D0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER122_lower,Interrupt Routing Registers" bitfld.long 0x2D0 31. "DISTRIBUTOR__37_GICD_IROUTER122_LOWER__31_1," "0,1" hexmask.long.byte 0x2D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER122_LOWER__8_8," newline hexmask.long.byte 0x2D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER122_LOWER__0_8," line.long 0x2D4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER122_upper,Interrupt Routing Registers" line.long 0x2D8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER123_lower,Interrupt Routing Registers" bitfld.long 0x2D8 31. "DISTRIBUTOR__37_GICD_IROUTER123_LOWER__31_1," "0,1" hexmask.long.byte 0x2D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER123_LOWER__8_8," newline hexmask.long.byte 0x2D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER123_LOWER__0_8," line.long 0x2DC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER123_upper,Interrupt Routing Registers" line.long 0x2E0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER124_lower,Interrupt Routing Registers" bitfld.long 0x2E0 31. "DISTRIBUTOR__37_GICD_IROUTER124_LOWER__31_1," "0,1" hexmask.long.byte 0x2E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER124_LOWER__8_8," newline hexmask.long.byte 0x2E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER124_LOWER__0_8," line.long 0x2E4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER124_upper,Interrupt Routing Registers" line.long 0x2E8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER125_lower,Interrupt Routing Registers" bitfld.long 0x2E8 31. "DISTRIBUTOR__37_GICD_IROUTER125_LOWER__31_1," "0,1" hexmask.long.byte 0x2E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER125_LOWER__8_8," newline hexmask.long.byte 0x2E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER125_LOWER__0_8," line.long 0x2EC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER125_upper,Interrupt Routing Registers" line.long 0x2F0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER126_lower,Interrupt Routing Registers" bitfld.long 0x2F0 31. "DISTRIBUTOR__37_GICD_IROUTER126_LOWER__31_1," "0,1" hexmask.long.byte 0x2F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER126_LOWER__8_8," newline hexmask.long.byte 0x2F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER126_LOWER__0_8," line.long 0x2F4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER126_upper,Interrupt Routing Registers" line.long 0x2F8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER127_lower,Interrupt Routing Registers" bitfld.long 0x2F8 31. "DISTRIBUTOR__37_GICD_IROUTER127_LOWER__31_1," "0,1" hexmask.long.byte 0x2F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER127_LOWER__8_8," newline hexmask.long.byte 0x2F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER127_LOWER__0_8," line.long 0x2FC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER127_upper,Interrupt Routing Registers" line.long 0x300 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER128_lower,Interrupt Routing Registers" bitfld.long 0x300 31. "DISTRIBUTOR__37_GICD_IROUTER128_LOWER__31_1," "0,1" hexmask.long.byte 0x300 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER128_LOWER__8_8," newline hexmask.long.byte 0x300 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER128_LOWER__0_8," line.long 0x304 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER128_upper,Interrupt Routing Registers" line.long 0x308 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER129_lower,Interrupt Routing Registers" bitfld.long 0x308 31. "DISTRIBUTOR__37_GICD_IROUTER129_LOWER__31_1," "0,1" hexmask.long.byte 0x308 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER129_LOWER__8_8," newline hexmask.long.byte 0x308 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER129_LOWER__0_8," line.long 0x30C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER129_upper,Interrupt Routing Registers" line.long 0x310 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER130_lower,Interrupt Routing Registers" bitfld.long 0x310 31. "DISTRIBUTOR__37_GICD_IROUTER130_LOWER__31_1," "0,1" hexmask.long.byte 0x310 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER130_LOWER__8_8," newline hexmask.long.byte 0x310 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER130_LOWER__0_8," line.long 0x314 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER130_upper,Interrupt Routing Registers" line.long 0x318 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER131_lower,Interrupt Routing Registers" bitfld.long 0x318 31. "DISTRIBUTOR__37_GICD_IROUTER131_LOWER__31_1," "0,1" hexmask.long.byte 0x318 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER131_LOWER__8_8," newline hexmask.long.byte 0x318 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER131_LOWER__0_8," line.long 0x31C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER131_upper,Interrupt Routing Registers" line.long 0x320 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER132_lower,Interrupt Routing Registers" bitfld.long 0x320 31. "DISTRIBUTOR__37_GICD_IROUTER132_LOWER__31_1," "0,1" hexmask.long.byte 0x320 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER132_LOWER__8_8," newline hexmask.long.byte 0x320 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER132_LOWER__0_8," line.long 0x324 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER132_upper,Interrupt Routing Registers" line.long 0x328 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER133_lower,Interrupt Routing Registers" bitfld.long 0x328 31. "DISTRIBUTOR__37_GICD_IROUTER133_LOWER__31_1," "0,1" hexmask.long.byte 0x328 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER133_LOWER__8_8," newline hexmask.long.byte 0x328 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER133_LOWER__0_8," line.long 0x32C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER133_upper,Interrupt Routing Registers" line.long 0x330 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER134_lower,Interrupt Routing Registers" bitfld.long 0x330 31. "DISTRIBUTOR__37_GICD_IROUTER134_LOWER__31_1," "0,1" hexmask.long.byte 0x330 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER134_LOWER__8_8," newline hexmask.long.byte 0x330 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER134_LOWER__0_8," line.long 0x334 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER134_upper,Interrupt Routing Registers" line.long 0x338 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER135_lower,Interrupt Routing Registers" bitfld.long 0x338 31. "DISTRIBUTOR__37_GICD_IROUTER135_LOWER__31_1," "0,1" hexmask.long.byte 0x338 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER135_LOWER__8_8," newline hexmask.long.byte 0x338 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER135_LOWER__0_8," line.long 0x33C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER135_upper,Interrupt Routing Registers" line.long 0x340 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER136_lower,Interrupt Routing Registers" bitfld.long 0x340 31. "DISTRIBUTOR__37_GICD_IROUTER136_LOWER__31_1," "0,1" hexmask.long.byte 0x340 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER136_LOWER__8_8," newline hexmask.long.byte 0x340 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER136_LOWER__0_8," line.long 0x344 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER136_upper,Interrupt Routing Registers" line.long 0x348 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER137_lower,Interrupt Routing Registers" bitfld.long 0x348 31. "DISTRIBUTOR__37_GICD_IROUTER137_LOWER__31_1," "0,1" hexmask.long.byte 0x348 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER137_LOWER__8_8," newline hexmask.long.byte 0x348 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER137_LOWER__0_8," line.long 0x34C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER137_upper,Interrupt Routing Registers" line.long 0x350 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER138_lower,Interrupt Routing Registers" bitfld.long 0x350 31. "DISTRIBUTOR__37_GICD_IROUTER138_LOWER__31_1," "0,1" hexmask.long.byte 0x350 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER138_LOWER__8_8," newline hexmask.long.byte 0x350 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER138_LOWER__0_8," line.long 0x354 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER138_upper,Interrupt Routing Registers" line.long 0x358 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER139_lower,Interrupt Routing Registers" bitfld.long 0x358 31. "DISTRIBUTOR__37_GICD_IROUTER139_LOWER__31_1," "0,1" hexmask.long.byte 0x358 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER139_LOWER__8_8," newline hexmask.long.byte 0x358 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER139_LOWER__0_8," line.long 0x35C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER139_upper,Interrupt Routing Registers" line.long 0x360 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER140_lower,Interrupt Routing Registers" bitfld.long 0x360 31. "DISTRIBUTOR__37_GICD_IROUTER140_LOWER__31_1," "0,1" hexmask.long.byte 0x360 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER140_LOWER__8_8," newline hexmask.long.byte 0x360 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER140_LOWER__0_8," line.long 0x364 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER140_upper,Interrupt Routing Registers" line.long 0x368 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER141_lower,Interrupt Routing Registers" bitfld.long 0x368 31. "DISTRIBUTOR__37_GICD_IROUTER141_LOWER__31_1," "0,1" hexmask.long.byte 0x368 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER141_LOWER__8_8," newline hexmask.long.byte 0x368 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER141_LOWER__0_8," line.long 0x36C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER141_upper,Interrupt Routing Registers" line.long 0x370 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER142_lower,Interrupt Routing Registers" bitfld.long 0x370 31. "DISTRIBUTOR__37_GICD_IROUTER142_LOWER__31_1," "0,1" hexmask.long.byte 0x370 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER142_LOWER__8_8," newline hexmask.long.byte 0x370 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER142_LOWER__0_8," line.long 0x374 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER142_upper,Interrupt Routing Registers" line.long 0x378 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER143_lower,Interrupt Routing Registers" bitfld.long 0x378 31. "DISTRIBUTOR__37_GICD_IROUTER143_LOWER__31_1," "0,1" hexmask.long.byte 0x378 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER143_LOWER__8_8," newline hexmask.long.byte 0x378 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER143_LOWER__0_8," line.long 0x37C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER143_upper,Interrupt Routing Registers" line.long 0x380 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER144_lower,Interrupt Routing Registers" bitfld.long 0x380 31. "DISTRIBUTOR__37_GICD_IROUTER144_LOWER__31_1," "0,1" hexmask.long.byte 0x380 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER144_LOWER__8_8," newline hexmask.long.byte 0x380 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER144_LOWER__0_8," line.long 0x384 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER144_upper,Interrupt Routing Registers" line.long 0x388 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER145_lower,Interrupt Routing Registers" bitfld.long 0x388 31. "DISTRIBUTOR__37_GICD_IROUTER145_LOWER__31_1," "0,1" hexmask.long.byte 0x388 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER145_LOWER__8_8," newline hexmask.long.byte 0x388 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER145_LOWER__0_8," line.long 0x38C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER145_upper,Interrupt Routing Registers" line.long 0x390 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER146_lower,Interrupt Routing Registers" bitfld.long 0x390 31. "DISTRIBUTOR__37_GICD_IROUTER146_LOWER__31_1," "0,1" hexmask.long.byte 0x390 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER146_LOWER__8_8," newline hexmask.long.byte 0x390 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER146_LOWER__0_8," line.long 0x394 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER146_upper,Interrupt Routing Registers" line.long 0x398 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER147_lower,Interrupt Routing Registers" bitfld.long 0x398 31. "DISTRIBUTOR__37_GICD_IROUTER147_LOWER__31_1," "0,1" hexmask.long.byte 0x398 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER147_LOWER__8_8," newline hexmask.long.byte 0x398 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER147_LOWER__0_8," line.long 0x39C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER147_upper,Interrupt Routing Registers" line.long 0x3A0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER148_lower,Interrupt Routing Registers" bitfld.long 0x3A0 31. "DISTRIBUTOR__37_GICD_IROUTER148_LOWER__31_1," "0,1" hexmask.long.byte 0x3A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER148_LOWER__8_8," newline hexmask.long.byte 0x3A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER148_LOWER__0_8," line.long 0x3A4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER148_upper,Interrupt Routing Registers" line.long 0x3A8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER149_lower,Interrupt Routing Registers" bitfld.long 0x3A8 31. "DISTRIBUTOR__37_GICD_IROUTER149_LOWER__31_1," "0,1" hexmask.long.byte 0x3A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER149_LOWER__8_8," newline hexmask.long.byte 0x3A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER149_LOWER__0_8," line.long 0x3AC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER149_upper,Interrupt Routing Registers" line.long 0x3B0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER150_lower,Interrupt Routing Registers" bitfld.long 0x3B0 31. "DISTRIBUTOR__37_GICD_IROUTER150_LOWER__31_1," "0,1" hexmask.long.byte 0x3B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER150_LOWER__8_8," newline hexmask.long.byte 0x3B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER150_LOWER__0_8," line.long 0x3B4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER150_upper,Interrupt Routing Registers" line.long 0x3B8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER151_lower,Interrupt Routing Registers" bitfld.long 0x3B8 31. "DISTRIBUTOR__37_GICD_IROUTER151_LOWER__31_1," "0,1" hexmask.long.byte 0x3B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER151_LOWER__8_8," newline hexmask.long.byte 0x3B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER151_LOWER__0_8," line.long 0x3BC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER151_upper,Interrupt Routing Registers" line.long 0x3C0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER152_lower,Interrupt Routing Registers" bitfld.long 0x3C0 31. "DISTRIBUTOR__37_GICD_IROUTER152_LOWER__31_1," "0,1" hexmask.long.byte 0x3C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER152_LOWER__8_8," newline hexmask.long.byte 0x3C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER152_LOWER__0_8," line.long 0x3C4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER152_upper,Interrupt Routing Registers" line.long 0x3C8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER153_lower,Interrupt Routing Registers" bitfld.long 0x3C8 31. "DISTRIBUTOR__37_GICD_IROUTER153_LOWER__31_1," "0,1" hexmask.long.byte 0x3C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER153_LOWER__8_8," newline hexmask.long.byte 0x3C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER153_LOWER__0_8," line.long 0x3CC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER153_upper,Interrupt Routing Registers" line.long 0x3D0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER154_lower,Interrupt Routing Registers" bitfld.long 0x3D0 31. "DISTRIBUTOR__37_GICD_IROUTER154_LOWER__31_1," "0,1" hexmask.long.byte 0x3D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER154_LOWER__8_8," newline hexmask.long.byte 0x3D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER154_LOWER__0_8," line.long 0x3D4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER154_upper,Interrupt Routing Registers" line.long 0x3D8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER155_lower,Interrupt Routing Registers" bitfld.long 0x3D8 31. "DISTRIBUTOR__37_GICD_IROUTER155_LOWER__31_1," "0,1" hexmask.long.byte 0x3D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER155_LOWER__8_8," newline hexmask.long.byte 0x3D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER155_LOWER__0_8," line.long 0x3DC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER155_upper,Interrupt Routing Registers" line.long 0x3E0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER156_lower,Interrupt Routing Registers" bitfld.long 0x3E0 31. "DISTRIBUTOR__37_GICD_IROUTER156_LOWER__31_1," "0,1" hexmask.long.byte 0x3E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER156_LOWER__8_8," newline hexmask.long.byte 0x3E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER156_LOWER__0_8," line.long 0x3E4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER156_upper,Interrupt Routing Registers" line.long 0x3E8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER157_lower,Interrupt Routing Registers" bitfld.long 0x3E8 31. "DISTRIBUTOR__37_GICD_IROUTER157_LOWER__31_1," "0,1" hexmask.long.byte 0x3E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER157_LOWER__8_8," newline hexmask.long.byte 0x3E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER157_LOWER__0_8," line.long 0x3EC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER157_upper,Interrupt Routing Registers" line.long 0x3F0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER158_lower,Interrupt Routing Registers" bitfld.long 0x3F0 31. "DISTRIBUTOR__37_GICD_IROUTER158_LOWER__31_1," "0,1" hexmask.long.byte 0x3F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER158_LOWER__8_8," newline hexmask.long.byte 0x3F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER158_LOWER__0_8," line.long 0x3F4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER158_upper,Interrupt Routing Registers" line.long 0x3F8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER159_lower,Interrupt Routing Registers" bitfld.long 0x3F8 31. "DISTRIBUTOR__37_GICD_IROUTER159_LOWER__31_1," "0,1" hexmask.long.byte 0x3F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER159_LOWER__8_8," newline hexmask.long.byte 0x3F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER159_LOWER__0_8," line.long 0x3FC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER159_upper,Interrupt Routing Registers" line.long 0x400 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER160_lower,Interrupt Routing Registers" bitfld.long 0x400 31. "DISTRIBUTOR__37_GICD_IROUTER160_LOWER__31_1," "0,1" hexmask.long.byte 0x400 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER160_LOWER__8_8," newline hexmask.long.byte 0x400 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER160_LOWER__0_8," line.long 0x404 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER160_upper,Interrupt Routing Registers" line.long 0x408 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER161_lower,Interrupt Routing Registers" bitfld.long 0x408 31. "DISTRIBUTOR__37_GICD_IROUTER161_LOWER__31_1," "0,1" hexmask.long.byte 0x408 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER161_LOWER__8_8," newline hexmask.long.byte 0x408 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER161_LOWER__0_8," line.long 0x40C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER161_upper,Interrupt Routing Registers" line.long 0x410 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER162_lower,Interrupt Routing Registers" bitfld.long 0x410 31. "DISTRIBUTOR__37_GICD_IROUTER162_LOWER__31_1," "0,1" hexmask.long.byte 0x410 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER162_LOWER__8_8," newline hexmask.long.byte 0x410 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER162_LOWER__0_8," line.long 0x414 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER162_upper,Interrupt Routing Registers" line.long 0x418 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER163_lower,Interrupt Routing Registers" bitfld.long 0x418 31. "DISTRIBUTOR__37_GICD_IROUTER163_LOWER__31_1," "0,1" hexmask.long.byte 0x418 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER163_LOWER__8_8," newline hexmask.long.byte 0x418 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER163_LOWER__0_8," line.long 0x41C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER163_upper,Interrupt Routing Registers" line.long 0x420 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER164_lower,Interrupt Routing Registers" bitfld.long 0x420 31. "DISTRIBUTOR__37_GICD_IROUTER164_LOWER__31_1," "0,1" hexmask.long.byte 0x420 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER164_LOWER__8_8," newline hexmask.long.byte 0x420 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER164_LOWER__0_8," line.long 0x424 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER164_upper,Interrupt Routing Registers" line.long 0x428 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER165_lower,Interrupt Routing Registers" bitfld.long 0x428 31. "DISTRIBUTOR__37_GICD_IROUTER165_LOWER__31_1," "0,1" hexmask.long.byte 0x428 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER165_LOWER__8_8," newline hexmask.long.byte 0x428 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER165_LOWER__0_8," line.long 0x42C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER165_upper,Interrupt Routing Registers" line.long 0x430 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER166_lower,Interrupt Routing Registers" bitfld.long 0x430 31. "DISTRIBUTOR__37_GICD_IROUTER166_LOWER__31_1," "0,1" hexmask.long.byte 0x430 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER166_LOWER__8_8," newline hexmask.long.byte 0x430 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER166_LOWER__0_8," line.long 0x434 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER166_upper,Interrupt Routing Registers" line.long 0x438 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER167_lower,Interrupt Routing Registers" bitfld.long 0x438 31. "DISTRIBUTOR__37_GICD_IROUTER167_LOWER__31_1," "0,1" hexmask.long.byte 0x438 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER167_LOWER__8_8," newline hexmask.long.byte 0x438 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER167_LOWER__0_8," line.long 0x43C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER167_upper,Interrupt Routing Registers" line.long 0x440 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER168_lower,Interrupt Routing Registers" bitfld.long 0x440 31. "DISTRIBUTOR__37_GICD_IROUTER168_LOWER__31_1," "0,1" hexmask.long.byte 0x440 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER168_LOWER__8_8," newline hexmask.long.byte 0x440 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER168_LOWER__0_8," line.long 0x444 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER168_upper,Interrupt Routing Registers" line.long 0x448 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER169_lower,Interrupt Routing Registers" bitfld.long 0x448 31. "DISTRIBUTOR__37_GICD_IROUTER169_LOWER__31_1," "0,1" hexmask.long.byte 0x448 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER169_LOWER__8_8," newline hexmask.long.byte 0x448 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER169_LOWER__0_8," line.long 0x44C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER169_upper,Interrupt Routing Registers" line.long 0x450 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER170_lower,Interrupt Routing Registers" bitfld.long 0x450 31. "DISTRIBUTOR__37_GICD_IROUTER170_LOWER__31_1," "0,1" hexmask.long.byte 0x450 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER170_LOWER__8_8," newline hexmask.long.byte 0x450 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER170_LOWER__0_8," line.long 0x454 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER170_upper,Interrupt Routing Registers" line.long 0x458 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER171_lower,Interrupt Routing Registers" bitfld.long 0x458 31. "DISTRIBUTOR__37_GICD_IROUTER171_LOWER__31_1," "0,1" hexmask.long.byte 0x458 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER171_LOWER__8_8," newline hexmask.long.byte 0x458 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER171_LOWER__0_8," line.long 0x45C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER171_upper,Interrupt Routing Registers" line.long 0x460 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER172_lower,Interrupt Routing Registers" bitfld.long 0x460 31. "DISTRIBUTOR__37_GICD_IROUTER172_LOWER__31_1," "0,1" hexmask.long.byte 0x460 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER172_LOWER__8_8," newline hexmask.long.byte 0x460 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER172_LOWER__0_8," line.long 0x464 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER172_upper,Interrupt Routing Registers" line.long 0x468 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER173_lower,Interrupt Routing Registers" bitfld.long 0x468 31. "DISTRIBUTOR__37_GICD_IROUTER173_LOWER__31_1," "0,1" hexmask.long.byte 0x468 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER173_LOWER__8_8," newline hexmask.long.byte 0x468 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER173_LOWER__0_8," line.long 0x46C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER173_upper,Interrupt Routing Registers" line.long 0x470 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER174_lower,Interrupt Routing Registers" bitfld.long 0x470 31. "DISTRIBUTOR__37_GICD_IROUTER174_LOWER__31_1," "0,1" hexmask.long.byte 0x470 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER174_LOWER__8_8," newline hexmask.long.byte 0x470 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER174_LOWER__0_8," line.long 0x474 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER174_upper,Interrupt Routing Registers" line.long 0x478 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER175_lower,Interrupt Routing Registers" bitfld.long 0x478 31. "DISTRIBUTOR__37_GICD_IROUTER175_LOWER__31_1," "0,1" hexmask.long.byte 0x478 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER175_LOWER__8_8," newline hexmask.long.byte 0x478 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER175_LOWER__0_8," line.long 0x47C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER175_upper,Interrupt Routing Registers" line.long 0x480 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER176_lower,Interrupt Routing Registers" bitfld.long 0x480 31. "DISTRIBUTOR__37_GICD_IROUTER176_LOWER__31_1," "0,1" hexmask.long.byte 0x480 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER176_LOWER__8_8," newline hexmask.long.byte 0x480 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER176_LOWER__0_8," line.long 0x484 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER176_upper,Interrupt Routing Registers" line.long 0x488 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER177_lower,Interrupt Routing Registers" bitfld.long 0x488 31. "DISTRIBUTOR__37_GICD_IROUTER177_LOWER__31_1," "0,1" hexmask.long.byte 0x488 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER177_LOWER__8_8," newline hexmask.long.byte 0x488 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER177_LOWER__0_8," line.long 0x48C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER177_upper,Interrupt Routing Registers" line.long 0x490 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER178_lower,Interrupt Routing Registers" bitfld.long 0x490 31. "DISTRIBUTOR__37_GICD_IROUTER178_LOWER__31_1," "0,1" hexmask.long.byte 0x490 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER178_LOWER__8_8," newline hexmask.long.byte 0x490 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER178_LOWER__0_8," line.long 0x494 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER178_upper,Interrupt Routing Registers" line.long 0x498 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER179_lower,Interrupt Routing Registers" bitfld.long 0x498 31. "DISTRIBUTOR__37_GICD_IROUTER179_LOWER__31_1," "0,1" hexmask.long.byte 0x498 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER179_LOWER__8_8," newline hexmask.long.byte 0x498 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER179_LOWER__0_8," line.long 0x49C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER179_upper,Interrupt Routing Registers" line.long 0x4A0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER180_lower,Interrupt Routing Registers" bitfld.long 0x4A0 31. "DISTRIBUTOR__37_GICD_IROUTER180_LOWER__31_1," "0,1" hexmask.long.byte 0x4A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER180_LOWER__8_8," newline hexmask.long.byte 0x4A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER180_LOWER__0_8," line.long 0x4A4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER180_upper,Interrupt Routing Registers" line.long 0x4A8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER181_lower,Interrupt Routing Registers" bitfld.long 0x4A8 31. "DISTRIBUTOR__37_GICD_IROUTER181_LOWER__31_1," "0,1" hexmask.long.byte 0x4A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER181_LOWER__8_8," newline hexmask.long.byte 0x4A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER181_LOWER__0_8," line.long 0x4AC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER181_upper,Interrupt Routing Registers" line.long 0x4B0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER182_lower,Interrupt Routing Registers" bitfld.long 0x4B0 31. "DISTRIBUTOR__37_GICD_IROUTER182_LOWER__31_1," "0,1" hexmask.long.byte 0x4B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER182_LOWER__8_8," newline hexmask.long.byte 0x4B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER182_LOWER__0_8," line.long 0x4B4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER182_upper,Interrupt Routing Registers" line.long 0x4B8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER183_lower,Interrupt Routing Registers" bitfld.long 0x4B8 31. "DISTRIBUTOR__37_GICD_IROUTER183_LOWER__31_1," "0,1" hexmask.long.byte 0x4B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER183_LOWER__8_8," newline hexmask.long.byte 0x4B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER183_LOWER__0_8," line.long 0x4BC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER183_upper,Interrupt Routing Registers" line.long 0x4C0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER184_lower,Interrupt Routing Registers" bitfld.long 0x4C0 31. "DISTRIBUTOR__37_GICD_IROUTER184_LOWER__31_1," "0,1" hexmask.long.byte 0x4C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER184_LOWER__8_8," newline hexmask.long.byte 0x4C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER184_LOWER__0_8," line.long 0x4C4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER184_upper,Interrupt Routing Registers" line.long 0x4C8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER185_lower,Interrupt Routing Registers" bitfld.long 0x4C8 31. "DISTRIBUTOR__37_GICD_IROUTER185_LOWER__31_1," "0,1" hexmask.long.byte 0x4C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER185_LOWER__8_8," newline hexmask.long.byte 0x4C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER185_LOWER__0_8," line.long 0x4CC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER185_upper,Interrupt Routing Registers" line.long 0x4D0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER186_lower,Interrupt Routing Registers" bitfld.long 0x4D0 31. "DISTRIBUTOR__37_GICD_IROUTER186_LOWER__31_1," "0,1" hexmask.long.byte 0x4D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER186_LOWER__8_8," newline hexmask.long.byte 0x4D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER186_LOWER__0_8," line.long 0x4D4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER186_upper,Interrupt Routing Registers" line.long 0x4D8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER187_lower,Interrupt Routing Registers" bitfld.long 0x4D8 31. "DISTRIBUTOR__37_GICD_IROUTER187_LOWER__31_1," "0,1" hexmask.long.byte 0x4D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER187_LOWER__8_8," newline hexmask.long.byte 0x4D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER187_LOWER__0_8," line.long 0x4DC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER187_upper,Interrupt Routing Registers" line.long 0x4E0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER188_lower,Interrupt Routing Registers" bitfld.long 0x4E0 31. "DISTRIBUTOR__37_GICD_IROUTER188_LOWER__31_1," "0,1" hexmask.long.byte 0x4E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER188_LOWER__8_8," newline hexmask.long.byte 0x4E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER188_LOWER__0_8," line.long 0x4E4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER188_upper,Interrupt Routing Registers" line.long 0x4E8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER189_lower,Interrupt Routing Registers" bitfld.long 0x4E8 31. "DISTRIBUTOR__37_GICD_IROUTER189_LOWER__31_1," "0,1" hexmask.long.byte 0x4E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER189_LOWER__8_8," newline hexmask.long.byte 0x4E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER189_LOWER__0_8," line.long 0x4EC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER189_upper,Interrupt Routing Registers" line.long 0x4F0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER190_lower,Interrupt Routing Registers" bitfld.long 0x4F0 31. "DISTRIBUTOR__37_GICD_IROUTER190_LOWER__31_1," "0,1" hexmask.long.byte 0x4F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER190_LOWER__8_8," newline hexmask.long.byte 0x4F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER190_LOWER__0_8," line.long 0x4F4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER190_upper,Interrupt Routing Registers" line.long 0x4F8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER191_lower,Interrupt Routing Registers" bitfld.long 0x4F8 31. "DISTRIBUTOR__37_GICD_IROUTER191_LOWER__31_1," "0,1" hexmask.long.byte 0x4F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER191_LOWER__8_8," newline hexmask.long.byte 0x4F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER191_LOWER__0_8," line.long 0x4FC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER191_upper,Interrupt Routing Registers" line.long 0x500 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER192_lower,Interrupt Routing Registers" bitfld.long 0x500 31. "DISTRIBUTOR__37_GICD_IROUTER192_LOWER__31_1," "0,1" hexmask.long.byte 0x500 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER192_LOWER__8_8," newline hexmask.long.byte 0x500 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER192_LOWER__0_8," line.long 0x504 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER192_upper,Interrupt Routing Registers" line.long 0x508 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER193_lower,Interrupt Routing Registers" bitfld.long 0x508 31. "DISTRIBUTOR__37_GICD_IROUTER193_LOWER__31_1," "0,1" hexmask.long.byte 0x508 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER193_LOWER__8_8," newline hexmask.long.byte 0x508 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER193_LOWER__0_8," line.long 0x50C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER193_upper,Interrupt Routing Registers" line.long 0x510 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER194_lower,Interrupt Routing Registers" bitfld.long 0x510 31. "DISTRIBUTOR__37_GICD_IROUTER194_LOWER__31_1," "0,1" hexmask.long.byte 0x510 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER194_LOWER__8_8," newline hexmask.long.byte 0x510 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER194_LOWER__0_8," line.long 0x514 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER194_upper,Interrupt Routing Registers" line.long 0x518 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER195_lower,Interrupt Routing Registers" bitfld.long 0x518 31. "DISTRIBUTOR__37_GICD_IROUTER195_LOWER__31_1," "0,1" hexmask.long.byte 0x518 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER195_LOWER__8_8," newline hexmask.long.byte 0x518 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER195_LOWER__0_8," line.long 0x51C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER195_upper,Interrupt Routing Registers" line.long 0x520 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER196_lower,Interrupt Routing Registers" bitfld.long 0x520 31. "DISTRIBUTOR__37_GICD_IROUTER196_LOWER__31_1," "0,1" hexmask.long.byte 0x520 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER196_LOWER__8_8," newline hexmask.long.byte 0x520 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER196_LOWER__0_8," line.long 0x524 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER196_upper,Interrupt Routing Registers" line.long 0x528 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER197_lower,Interrupt Routing Registers" bitfld.long 0x528 31. "DISTRIBUTOR__37_GICD_IROUTER197_LOWER__31_1," "0,1" hexmask.long.byte 0x528 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER197_LOWER__8_8," newline hexmask.long.byte 0x528 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER197_LOWER__0_8," line.long 0x52C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER197_upper,Interrupt Routing Registers" line.long 0x530 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER198_lower,Interrupt Routing Registers" bitfld.long 0x530 31. "DISTRIBUTOR__37_GICD_IROUTER198_LOWER__31_1," "0,1" hexmask.long.byte 0x530 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER198_LOWER__8_8," newline hexmask.long.byte 0x530 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER198_LOWER__0_8," line.long 0x534 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER198_upper,Interrupt Routing Registers" line.long 0x538 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER199_lower,Interrupt Routing Registers" bitfld.long 0x538 31. "DISTRIBUTOR__37_GICD_IROUTER199_LOWER__31_1," "0,1" hexmask.long.byte 0x538 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER199_LOWER__8_8," newline hexmask.long.byte 0x538 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER199_LOWER__0_8," line.long 0x53C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER199_upper,Interrupt Routing Registers" line.long 0x540 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER200_lower,Interrupt Routing Registers" bitfld.long 0x540 31. "DISTRIBUTOR__37_GICD_IROUTER200_LOWER__31_1," "0,1" hexmask.long.byte 0x540 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER200_LOWER__8_8," newline hexmask.long.byte 0x540 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER200_LOWER__0_8," line.long 0x544 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER200_upper,Interrupt Routing Registers" line.long 0x548 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER201_lower,Interrupt Routing Registers" bitfld.long 0x548 31. "DISTRIBUTOR__37_GICD_IROUTER201_LOWER__31_1," "0,1" hexmask.long.byte 0x548 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER201_LOWER__8_8," newline hexmask.long.byte 0x548 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER201_LOWER__0_8," line.long 0x54C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER201_upper,Interrupt Routing Registers" line.long 0x550 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER202_lower,Interrupt Routing Registers" bitfld.long 0x550 31. "DISTRIBUTOR__37_GICD_IROUTER202_LOWER__31_1," "0,1" hexmask.long.byte 0x550 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER202_LOWER__8_8," newline hexmask.long.byte 0x550 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER202_LOWER__0_8," line.long 0x554 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER202_upper,Interrupt Routing Registers" line.long 0x558 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER203_lower,Interrupt Routing Registers" bitfld.long 0x558 31. "DISTRIBUTOR__37_GICD_IROUTER203_LOWER__31_1," "0,1" hexmask.long.byte 0x558 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER203_LOWER__8_8," newline hexmask.long.byte 0x558 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER203_LOWER__0_8," line.long 0x55C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER203_upper,Interrupt Routing Registers" line.long 0x560 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER204_lower,Interrupt Routing Registers" bitfld.long 0x560 31. "DISTRIBUTOR__37_GICD_IROUTER204_LOWER__31_1," "0,1" hexmask.long.byte 0x560 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER204_LOWER__8_8," newline hexmask.long.byte 0x560 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER204_LOWER__0_8," line.long 0x564 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER204_upper,Interrupt Routing Registers" line.long 0x568 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER205_lower,Interrupt Routing Registers" bitfld.long 0x568 31. "DISTRIBUTOR__37_GICD_IROUTER205_LOWER__31_1," "0,1" hexmask.long.byte 0x568 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER205_LOWER__8_8," newline hexmask.long.byte 0x568 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER205_LOWER__0_8," line.long 0x56C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER205_upper,Interrupt Routing Registers" line.long 0x570 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER206_lower,Interrupt Routing Registers" bitfld.long 0x570 31. "DISTRIBUTOR__37_GICD_IROUTER206_LOWER__31_1," "0,1" hexmask.long.byte 0x570 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER206_LOWER__8_8," newline hexmask.long.byte 0x570 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER206_LOWER__0_8," line.long 0x574 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER206_upper,Interrupt Routing Registers" line.long 0x578 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER207_lower,Interrupt Routing Registers" bitfld.long 0x578 31. "DISTRIBUTOR__37_GICD_IROUTER207_LOWER__31_1," "0,1" hexmask.long.byte 0x578 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER207_LOWER__8_8," newline hexmask.long.byte 0x578 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER207_LOWER__0_8," line.long 0x57C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER207_upper,Interrupt Routing Registers" line.long 0x580 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER208_lower,Interrupt Routing Registers" bitfld.long 0x580 31. "DISTRIBUTOR__37_GICD_IROUTER208_LOWER__31_1," "0,1" hexmask.long.byte 0x580 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER208_LOWER__8_8," newline hexmask.long.byte 0x580 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER208_LOWER__0_8," line.long 0x584 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER208_upper,Interrupt Routing Registers" line.long 0x588 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER209_lower,Interrupt Routing Registers" bitfld.long 0x588 31. "DISTRIBUTOR__37_GICD_IROUTER209_LOWER__31_1," "0,1" hexmask.long.byte 0x588 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER209_LOWER__8_8," newline hexmask.long.byte 0x588 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER209_LOWER__0_8," line.long 0x58C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER209_upper,Interrupt Routing Registers" line.long 0x590 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER210_lower,Interrupt Routing Registers" bitfld.long 0x590 31. "DISTRIBUTOR__37_GICD_IROUTER210_LOWER__31_1," "0,1" hexmask.long.byte 0x590 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER210_LOWER__8_8," newline hexmask.long.byte 0x590 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER210_LOWER__0_8," line.long 0x594 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER210_upper,Interrupt Routing Registers" line.long 0x598 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER211_lower,Interrupt Routing Registers" bitfld.long 0x598 31. "DISTRIBUTOR__37_GICD_IROUTER211_LOWER__31_1," "0,1" hexmask.long.byte 0x598 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER211_LOWER__8_8," newline hexmask.long.byte 0x598 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER211_LOWER__0_8," line.long 0x59C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER211_upper,Interrupt Routing Registers" line.long 0x5A0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER212_lower,Interrupt Routing Registers" bitfld.long 0x5A0 31. "DISTRIBUTOR__37_GICD_IROUTER212_LOWER__31_1," "0,1" hexmask.long.byte 0x5A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER212_LOWER__8_8," newline hexmask.long.byte 0x5A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER212_LOWER__0_8," line.long 0x5A4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER212_upper,Interrupt Routing Registers" line.long 0x5A8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER213_lower,Interrupt Routing Registers" bitfld.long 0x5A8 31. "DISTRIBUTOR__37_GICD_IROUTER213_LOWER__31_1," "0,1" hexmask.long.byte 0x5A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER213_LOWER__8_8," newline hexmask.long.byte 0x5A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER213_LOWER__0_8," line.long 0x5AC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER213_upper,Interrupt Routing Registers" line.long 0x5B0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER214_lower,Interrupt Routing Registers" bitfld.long 0x5B0 31. "DISTRIBUTOR__37_GICD_IROUTER214_LOWER__31_1," "0,1" hexmask.long.byte 0x5B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER214_LOWER__8_8," newline hexmask.long.byte 0x5B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER214_LOWER__0_8," line.long 0x5B4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER214_upper,Interrupt Routing Registers" line.long 0x5B8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER215_lower,Interrupt Routing Registers" bitfld.long 0x5B8 31. "DISTRIBUTOR__37_GICD_IROUTER215_LOWER__31_1," "0,1" hexmask.long.byte 0x5B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER215_LOWER__8_8," newline hexmask.long.byte 0x5B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER215_LOWER__0_8," line.long 0x5BC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER215_upper,Interrupt Routing Registers" line.long 0x5C0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER216_lower,Interrupt Routing Registers" bitfld.long 0x5C0 31. "DISTRIBUTOR__37_GICD_IROUTER216_LOWER__31_1," "0,1" hexmask.long.byte 0x5C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER216_LOWER__8_8," newline hexmask.long.byte 0x5C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER216_LOWER__0_8," line.long 0x5C4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER216_upper,Interrupt Routing Registers" line.long 0x5C8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER217_lower,Interrupt Routing Registers" bitfld.long 0x5C8 31. "DISTRIBUTOR__37_GICD_IROUTER217_LOWER__31_1," "0,1" hexmask.long.byte 0x5C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER217_LOWER__8_8," newline hexmask.long.byte 0x5C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER217_LOWER__0_8," line.long 0x5CC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER217_upper,Interrupt Routing Registers" line.long 0x5D0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER218_lower,Interrupt Routing Registers" bitfld.long 0x5D0 31. "DISTRIBUTOR__37_GICD_IROUTER218_LOWER__31_1," "0,1" hexmask.long.byte 0x5D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER218_LOWER__8_8," newline hexmask.long.byte 0x5D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER218_LOWER__0_8," line.long 0x5D4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER218_upper,Interrupt Routing Registers" line.long 0x5D8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER219_lower,Interrupt Routing Registers" bitfld.long 0x5D8 31. "DISTRIBUTOR__37_GICD_IROUTER219_LOWER__31_1," "0,1" hexmask.long.byte 0x5D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER219_LOWER__8_8," newline hexmask.long.byte 0x5D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER219_LOWER__0_8," line.long 0x5DC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER219_upper,Interrupt Routing Registers" line.long 0x5E0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER220_lower,Interrupt Routing Registers" bitfld.long 0x5E0 31. "DISTRIBUTOR__37_GICD_IROUTER220_LOWER__31_1," "0,1" hexmask.long.byte 0x5E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER220_LOWER__8_8," newline hexmask.long.byte 0x5E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER220_LOWER__0_8," line.long 0x5E4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER220_upper,Interrupt Routing Registers" line.long 0x5E8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER221_lower,Interrupt Routing Registers" bitfld.long 0x5E8 31. "DISTRIBUTOR__37_GICD_IROUTER221_LOWER__31_1," "0,1" hexmask.long.byte 0x5E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER221_LOWER__8_8," newline hexmask.long.byte 0x5E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER221_LOWER__0_8," line.long 0x5EC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER221_upper,Interrupt Routing Registers" line.long 0x5F0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER222_lower,Interrupt Routing Registers" bitfld.long 0x5F0 31. "DISTRIBUTOR__37_GICD_IROUTER222_LOWER__31_1," "0,1" hexmask.long.byte 0x5F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER222_LOWER__8_8," newline hexmask.long.byte 0x5F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER222_LOWER__0_8," line.long 0x5F4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER222_upper,Interrupt Routing Registers" line.long 0x5F8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER223_lower,Interrupt Routing Registers" bitfld.long 0x5F8 31. "DISTRIBUTOR__37_GICD_IROUTER223_LOWER__31_1," "0,1" hexmask.long.byte 0x5F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER223_LOWER__8_8," newline hexmask.long.byte 0x5F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER223_LOWER__0_8," line.long 0x5FC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER223_upper,Interrupt Routing Registers" line.long 0x600 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER224_lower,Interrupt Routing Registers" bitfld.long 0x600 31. "DISTRIBUTOR__37_GICD_IROUTER224_LOWER__31_1," "0,1" hexmask.long.byte 0x600 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER224_LOWER__8_8," newline hexmask.long.byte 0x600 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER224_LOWER__0_8," line.long 0x604 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER224_upper,Interrupt Routing Registers" line.long 0x608 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER225_lower,Interrupt Routing Registers" bitfld.long 0x608 31. "DISTRIBUTOR__37_GICD_IROUTER225_LOWER__31_1," "0,1" hexmask.long.byte 0x608 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER225_LOWER__8_8," newline hexmask.long.byte 0x608 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER225_LOWER__0_8," line.long 0x60C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER225_upper,Interrupt Routing Registers" line.long 0x610 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER226_lower,Interrupt Routing Registers" bitfld.long 0x610 31. "DISTRIBUTOR__37_GICD_IROUTER226_LOWER__31_1," "0,1" hexmask.long.byte 0x610 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER226_LOWER__8_8," newline hexmask.long.byte 0x610 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER226_LOWER__0_8," line.long 0x614 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER226_upper,Interrupt Routing Registers" line.long 0x618 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER227_lower,Interrupt Routing Registers" bitfld.long 0x618 31. "DISTRIBUTOR__37_GICD_IROUTER227_LOWER__31_1," "0,1" hexmask.long.byte 0x618 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER227_LOWER__8_8," newline hexmask.long.byte 0x618 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER227_LOWER__0_8," line.long 0x61C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER227_upper,Interrupt Routing Registers" line.long 0x620 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER228_lower,Interrupt Routing Registers" bitfld.long 0x620 31. "DISTRIBUTOR__37_GICD_IROUTER228_LOWER__31_1," "0,1" hexmask.long.byte 0x620 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER228_LOWER__8_8," newline hexmask.long.byte 0x620 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER228_LOWER__0_8," line.long 0x624 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER228_upper,Interrupt Routing Registers" line.long 0x628 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER229_lower,Interrupt Routing Registers" bitfld.long 0x628 31. "DISTRIBUTOR__37_GICD_IROUTER229_LOWER__31_1," "0,1" hexmask.long.byte 0x628 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER229_LOWER__8_8," newline hexmask.long.byte 0x628 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER229_LOWER__0_8," line.long 0x62C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER229_upper,Interrupt Routing Registers" line.long 0x630 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER230_lower,Interrupt Routing Registers" bitfld.long 0x630 31. "DISTRIBUTOR__37_GICD_IROUTER230_LOWER__31_1," "0,1" hexmask.long.byte 0x630 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER230_LOWER__8_8," newline hexmask.long.byte 0x630 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER230_LOWER__0_8," line.long 0x634 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER230_upper,Interrupt Routing Registers" line.long 0x638 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER231_lower,Interrupt Routing Registers" bitfld.long 0x638 31. "DISTRIBUTOR__37_GICD_IROUTER231_LOWER__31_1," "0,1" hexmask.long.byte 0x638 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER231_LOWER__8_8," newline hexmask.long.byte 0x638 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER231_LOWER__0_8," line.long 0x63C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER231_upper,Interrupt Routing Registers" line.long 0x640 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER232_lower,Interrupt Routing Registers" bitfld.long 0x640 31. "DISTRIBUTOR__37_GICD_IROUTER232_LOWER__31_1," "0,1" hexmask.long.byte 0x640 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER232_LOWER__8_8," newline hexmask.long.byte 0x640 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER232_LOWER__0_8," line.long 0x644 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER232_upper,Interrupt Routing Registers" line.long 0x648 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER233_lower,Interrupt Routing Registers" bitfld.long 0x648 31. "DISTRIBUTOR__37_GICD_IROUTER233_LOWER__31_1," "0,1" hexmask.long.byte 0x648 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER233_LOWER__8_8," newline hexmask.long.byte 0x648 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER233_LOWER__0_8," line.long 0x64C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER233_upper,Interrupt Routing Registers" line.long 0x650 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER234_lower,Interrupt Routing Registers" bitfld.long 0x650 31. "DISTRIBUTOR__37_GICD_IROUTER234_LOWER__31_1," "0,1" hexmask.long.byte 0x650 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER234_LOWER__8_8," newline hexmask.long.byte 0x650 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER234_LOWER__0_8," line.long 0x654 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER234_upper,Interrupt Routing Registers" line.long 0x658 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER235_lower,Interrupt Routing Registers" bitfld.long 0x658 31. "DISTRIBUTOR__37_GICD_IROUTER235_LOWER__31_1," "0,1" hexmask.long.byte 0x658 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER235_LOWER__8_8," newline hexmask.long.byte 0x658 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER235_LOWER__0_8," line.long 0x65C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER235_upper,Interrupt Routing Registers" line.long 0x660 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER236_lower,Interrupt Routing Registers" bitfld.long 0x660 31. "DISTRIBUTOR__37_GICD_IROUTER236_LOWER__31_1," "0,1" hexmask.long.byte 0x660 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER236_LOWER__8_8," newline hexmask.long.byte 0x660 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER236_LOWER__0_8," line.long 0x664 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER236_upper,Interrupt Routing Registers" line.long 0x668 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER237_lower,Interrupt Routing Registers" bitfld.long 0x668 31. "DISTRIBUTOR__37_GICD_IROUTER237_LOWER__31_1," "0,1" hexmask.long.byte 0x668 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER237_LOWER__8_8," newline hexmask.long.byte 0x668 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER237_LOWER__0_8," line.long 0x66C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER237_upper,Interrupt Routing Registers" line.long 0x670 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER238_lower,Interrupt Routing Registers" bitfld.long 0x670 31. "DISTRIBUTOR__37_GICD_IROUTER238_LOWER__31_1," "0,1" hexmask.long.byte 0x670 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER238_LOWER__8_8," newline hexmask.long.byte 0x670 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER238_LOWER__0_8," line.long 0x674 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER238_upper,Interrupt Routing Registers" line.long 0x678 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER239_lower,Interrupt Routing Registers" bitfld.long 0x678 31. "DISTRIBUTOR__37_GICD_IROUTER239_LOWER__31_1," "0,1" hexmask.long.byte 0x678 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER239_LOWER__8_8," newline hexmask.long.byte 0x678 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER239_LOWER__0_8," line.long 0x67C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER239_upper,Interrupt Routing Registers" line.long 0x680 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER240_lower,Interrupt Routing Registers" bitfld.long 0x680 31. "DISTRIBUTOR__37_GICD_IROUTER240_LOWER__31_1," "0,1" hexmask.long.byte 0x680 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER240_LOWER__8_8," newline hexmask.long.byte 0x680 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER240_LOWER__0_8," line.long 0x684 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER240_upper,Interrupt Routing Registers" line.long 0x688 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER241_lower,Interrupt Routing Registers" bitfld.long 0x688 31. "DISTRIBUTOR__37_GICD_IROUTER241_LOWER__31_1," "0,1" hexmask.long.byte 0x688 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER241_LOWER__8_8," newline hexmask.long.byte 0x688 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER241_LOWER__0_8," line.long 0x68C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER241_upper,Interrupt Routing Registers" line.long 0x690 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER242_lower,Interrupt Routing Registers" bitfld.long 0x690 31. "DISTRIBUTOR__37_GICD_IROUTER242_LOWER__31_1," "0,1" hexmask.long.byte 0x690 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER242_LOWER__8_8," newline hexmask.long.byte 0x690 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER242_LOWER__0_8," line.long 0x694 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER242_upper,Interrupt Routing Registers" line.long 0x698 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER243_lower,Interrupt Routing Registers" bitfld.long 0x698 31. "DISTRIBUTOR__37_GICD_IROUTER243_LOWER__31_1," "0,1" hexmask.long.byte 0x698 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER243_LOWER__8_8," newline hexmask.long.byte 0x698 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER243_LOWER__0_8," line.long 0x69C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER243_upper,Interrupt Routing Registers" line.long 0x6A0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER244_lower,Interrupt Routing Registers" bitfld.long 0x6A0 31. "DISTRIBUTOR__37_GICD_IROUTER244_LOWER__31_1," "0,1" hexmask.long.byte 0x6A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER244_LOWER__8_8," newline hexmask.long.byte 0x6A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER244_LOWER__0_8," line.long 0x6A4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER244_upper,Interrupt Routing Registers" line.long 0x6A8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER245_lower,Interrupt Routing Registers" bitfld.long 0x6A8 31. "DISTRIBUTOR__37_GICD_IROUTER245_LOWER__31_1," "0,1" hexmask.long.byte 0x6A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER245_LOWER__8_8," newline hexmask.long.byte 0x6A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER245_LOWER__0_8," line.long 0x6AC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER245_upper,Interrupt Routing Registers" line.long 0x6B0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER246_lower,Interrupt Routing Registers" bitfld.long 0x6B0 31. "DISTRIBUTOR__37_GICD_IROUTER246_LOWER__31_1," "0,1" hexmask.long.byte 0x6B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER246_LOWER__8_8," newline hexmask.long.byte 0x6B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER246_LOWER__0_8," line.long 0x6B4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER246_upper,Interrupt Routing Registers" line.long 0x6B8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER247_lower,Interrupt Routing Registers" bitfld.long 0x6B8 31. "DISTRIBUTOR__37_GICD_IROUTER247_LOWER__31_1," "0,1" hexmask.long.byte 0x6B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER247_LOWER__8_8," newline hexmask.long.byte 0x6B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER247_LOWER__0_8," line.long 0x6BC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER247_upper,Interrupt Routing Registers" line.long 0x6C0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER248_lower,Interrupt Routing Registers" bitfld.long 0x6C0 31. "DISTRIBUTOR__37_GICD_IROUTER248_LOWER__31_1," "0,1" hexmask.long.byte 0x6C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER248_LOWER__8_8," newline hexmask.long.byte 0x6C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER248_LOWER__0_8," line.long 0x6C4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER248_upper,Interrupt Routing Registers" line.long 0x6C8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER249_lower,Interrupt Routing Registers" bitfld.long 0x6C8 31. "DISTRIBUTOR__37_GICD_IROUTER249_LOWER__31_1," "0,1" hexmask.long.byte 0x6C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER249_LOWER__8_8," newline hexmask.long.byte 0x6C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER249_LOWER__0_8," line.long 0x6CC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER249_upper,Interrupt Routing Registers" line.long 0x6D0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER250_lower,Interrupt Routing Registers" bitfld.long 0x6D0 31. "DISTRIBUTOR__37_GICD_IROUTER250_LOWER__31_1," "0,1" hexmask.long.byte 0x6D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER250_LOWER__8_8," newline hexmask.long.byte 0x6D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER250_LOWER__0_8," line.long 0x6D4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER250_upper,Interrupt Routing Registers" line.long 0x6D8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER251_lower,Interrupt Routing Registers" bitfld.long 0x6D8 31. "DISTRIBUTOR__37_GICD_IROUTER251_LOWER__31_1," "0,1" hexmask.long.byte 0x6D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER251_LOWER__8_8," newline hexmask.long.byte 0x6D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER251_LOWER__0_8," line.long 0x6DC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER251_upper,Interrupt Routing Registers" line.long 0x6E0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER252_lower,Interrupt Routing Registers" bitfld.long 0x6E0 31. "DISTRIBUTOR__37_GICD_IROUTER252_LOWER__31_1," "0,1" hexmask.long.byte 0x6E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER252_LOWER__8_8," newline hexmask.long.byte 0x6E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER252_LOWER__0_8," line.long 0x6E4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER252_upper,Interrupt Routing Registers" line.long 0x6E8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER253_lower,Interrupt Routing Registers" bitfld.long 0x6E8 31. "DISTRIBUTOR__37_GICD_IROUTER253_LOWER__31_1," "0,1" hexmask.long.byte 0x6E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER253_LOWER__8_8," newline hexmask.long.byte 0x6E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER253_LOWER__0_8," line.long 0x6EC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER253_upper,Interrupt Routing Registers" line.long 0x6F0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER254_lower,Interrupt Routing Registers" bitfld.long 0x6F0 31. "DISTRIBUTOR__37_GICD_IROUTER254_LOWER__31_1," "0,1" hexmask.long.byte 0x6F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER254_LOWER__8_8," newline hexmask.long.byte 0x6F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER254_LOWER__0_8," line.long 0x6F4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER254_upper,Interrupt Routing Registers" line.long 0x6F8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER255_lower,Interrupt Routing Registers" bitfld.long 0x6F8 31. "DISTRIBUTOR__37_GICD_IROUTER255_LOWER__31_1," "0,1" hexmask.long.byte 0x6F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER255_LOWER__8_8," newline hexmask.long.byte 0x6F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER255_LOWER__0_8," line.long 0x6FC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER255_upper,Interrupt Routing Registers" line.long 0x700 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER256_lower,Interrupt Routing Registers" bitfld.long 0x700 31. "DISTRIBUTOR__37_GICD_IROUTER256_LOWER__31_1," "0,1" hexmask.long.byte 0x700 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER256_LOWER__8_8," newline hexmask.long.byte 0x700 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER256_LOWER__0_8," line.long 0x704 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER256_upper,Interrupt Routing Registers" line.long 0x708 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER257_lower,Interrupt Routing Registers" bitfld.long 0x708 31. "DISTRIBUTOR__37_GICD_IROUTER257_LOWER__31_1," "0,1" hexmask.long.byte 0x708 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER257_LOWER__8_8," newline hexmask.long.byte 0x708 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER257_LOWER__0_8," line.long 0x70C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER257_upper,Interrupt Routing Registers" line.long 0x710 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER258_lower,Interrupt Routing Registers" bitfld.long 0x710 31. "DISTRIBUTOR__37_GICD_IROUTER258_LOWER__31_1," "0,1" hexmask.long.byte 0x710 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER258_LOWER__8_8," newline hexmask.long.byte 0x710 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER258_LOWER__0_8," line.long 0x714 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER258_upper,Interrupt Routing Registers" line.long 0x718 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER259_lower,Interrupt Routing Registers" bitfld.long 0x718 31. "DISTRIBUTOR__37_GICD_IROUTER259_LOWER__31_1," "0,1" hexmask.long.byte 0x718 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER259_LOWER__8_8," newline hexmask.long.byte 0x718 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER259_LOWER__0_8," line.long 0x71C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER259_upper,Interrupt Routing Registers" line.long 0x720 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER260_lower,Interrupt Routing Registers" bitfld.long 0x720 31. "DISTRIBUTOR__37_GICD_IROUTER260_LOWER__31_1," "0,1" hexmask.long.byte 0x720 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER260_LOWER__8_8," newline hexmask.long.byte 0x720 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER260_LOWER__0_8," line.long 0x724 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER260_upper,Interrupt Routing Registers" line.long 0x728 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER261_lower,Interrupt Routing Registers" bitfld.long 0x728 31. "DISTRIBUTOR__37_GICD_IROUTER261_LOWER__31_1," "0,1" hexmask.long.byte 0x728 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER261_LOWER__8_8," newline hexmask.long.byte 0x728 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER261_LOWER__0_8," line.long 0x72C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER261_upper,Interrupt Routing Registers" line.long 0x730 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER262_lower,Interrupt Routing Registers" bitfld.long 0x730 31. "DISTRIBUTOR__37_GICD_IROUTER262_LOWER__31_1," "0,1" hexmask.long.byte 0x730 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER262_LOWER__8_8," newline hexmask.long.byte 0x730 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER262_LOWER__0_8," line.long 0x734 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER262_upper,Interrupt Routing Registers" line.long 0x738 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER263_lower,Interrupt Routing Registers" bitfld.long 0x738 31. "DISTRIBUTOR__37_GICD_IROUTER263_LOWER__31_1," "0,1" hexmask.long.byte 0x738 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER263_LOWER__8_8," newline hexmask.long.byte 0x738 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER263_LOWER__0_8," line.long 0x73C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER263_upper,Interrupt Routing Registers" line.long 0x740 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER264_lower,Interrupt Routing Registers" bitfld.long 0x740 31. "DISTRIBUTOR__37_GICD_IROUTER264_LOWER__31_1," "0,1" hexmask.long.byte 0x740 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER264_LOWER__8_8," newline hexmask.long.byte 0x740 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER264_LOWER__0_8," line.long 0x744 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER264_upper,Interrupt Routing Registers" line.long 0x748 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER265_lower,Interrupt Routing Registers" bitfld.long 0x748 31. "DISTRIBUTOR__37_GICD_IROUTER265_LOWER__31_1," "0,1" hexmask.long.byte 0x748 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER265_LOWER__8_8," newline hexmask.long.byte 0x748 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER265_LOWER__0_8," line.long 0x74C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER265_upper,Interrupt Routing Registers" line.long 0x750 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER266_lower,Interrupt Routing Registers" bitfld.long 0x750 31. "DISTRIBUTOR__37_GICD_IROUTER266_LOWER__31_1," "0,1" hexmask.long.byte 0x750 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER266_LOWER__8_8," newline hexmask.long.byte 0x750 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER266_LOWER__0_8," line.long 0x754 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER266_upper,Interrupt Routing Registers" line.long 0x758 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER267_lower,Interrupt Routing Registers" bitfld.long 0x758 31. "DISTRIBUTOR__37_GICD_IROUTER267_LOWER__31_1," "0,1" hexmask.long.byte 0x758 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER267_LOWER__8_8," newline hexmask.long.byte 0x758 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER267_LOWER__0_8," line.long 0x75C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER267_upper,Interrupt Routing Registers" line.long 0x760 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER268_lower,Interrupt Routing Registers" bitfld.long 0x760 31. "DISTRIBUTOR__37_GICD_IROUTER268_LOWER__31_1," "0,1" hexmask.long.byte 0x760 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER268_LOWER__8_8," newline hexmask.long.byte 0x760 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER268_LOWER__0_8," line.long 0x764 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER268_upper,Interrupt Routing Registers" line.long 0x768 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER269_lower,Interrupt Routing Registers" bitfld.long 0x768 31. "DISTRIBUTOR__37_GICD_IROUTER269_LOWER__31_1," "0,1" hexmask.long.byte 0x768 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER269_LOWER__8_8," newline hexmask.long.byte 0x768 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER269_LOWER__0_8," line.long 0x76C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER269_upper,Interrupt Routing Registers" line.long 0x770 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER270_lower,Interrupt Routing Registers" bitfld.long 0x770 31. "DISTRIBUTOR__37_GICD_IROUTER270_LOWER__31_1," "0,1" hexmask.long.byte 0x770 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER270_LOWER__8_8," newline hexmask.long.byte 0x770 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER270_LOWER__0_8," line.long 0x774 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER270_upper,Interrupt Routing Registers" line.long 0x778 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER271_lower,Interrupt Routing Registers" bitfld.long 0x778 31. "DISTRIBUTOR__37_GICD_IROUTER271_LOWER__31_1," "0,1" hexmask.long.byte 0x778 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER271_LOWER__8_8," newline hexmask.long.byte 0x778 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER271_LOWER__0_8," line.long 0x77C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER271_upper,Interrupt Routing Registers" line.long 0x780 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER272_lower,Interrupt Routing Registers" bitfld.long 0x780 31. "DISTRIBUTOR__37_GICD_IROUTER272_LOWER__31_1," "0,1" hexmask.long.byte 0x780 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER272_LOWER__8_8," newline hexmask.long.byte 0x780 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER272_LOWER__0_8," line.long 0x784 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER272_upper,Interrupt Routing Registers" line.long 0x788 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER273_lower,Interrupt Routing Registers" bitfld.long 0x788 31. "DISTRIBUTOR__37_GICD_IROUTER273_LOWER__31_1," "0,1" hexmask.long.byte 0x788 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER273_LOWER__8_8," newline hexmask.long.byte 0x788 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER273_LOWER__0_8," line.long 0x78C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER273_upper,Interrupt Routing Registers" line.long 0x790 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER274_lower,Interrupt Routing Registers" bitfld.long 0x790 31. "DISTRIBUTOR__37_GICD_IROUTER274_LOWER__31_1," "0,1" hexmask.long.byte 0x790 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER274_LOWER__8_8," newline hexmask.long.byte 0x790 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER274_LOWER__0_8," line.long 0x794 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER274_upper,Interrupt Routing Registers" line.long 0x798 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER275_lower,Interrupt Routing Registers" bitfld.long 0x798 31. "DISTRIBUTOR__37_GICD_IROUTER275_LOWER__31_1," "0,1" hexmask.long.byte 0x798 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER275_LOWER__8_8," newline hexmask.long.byte 0x798 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER275_LOWER__0_8," line.long 0x79C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER275_upper,Interrupt Routing Registers" line.long 0x7A0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER276_lower,Interrupt Routing Registers" bitfld.long 0x7A0 31. "DISTRIBUTOR__37_GICD_IROUTER276_LOWER__31_1," "0,1" hexmask.long.byte 0x7A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER276_LOWER__8_8," newline hexmask.long.byte 0x7A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER276_LOWER__0_8," line.long 0x7A4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER276_upper,Interrupt Routing Registers" line.long 0x7A8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER277_lower,Interrupt Routing Registers" bitfld.long 0x7A8 31. "DISTRIBUTOR__37_GICD_IROUTER277_LOWER__31_1," "0,1" hexmask.long.byte 0x7A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER277_LOWER__8_8," newline hexmask.long.byte 0x7A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER277_LOWER__0_8," line.long 0x7AC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER277_upper,Interrupt Routing Registers" line.long 0x7B0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER278_lower,Interrupt Routing Registers" bitfld.long 0x7B0 31. "DISTRIBUTOR__37_GICD_IROUTER278_LOWER__31_1," "0,1" hexmask.long.byte 0x7B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER278_LOWER__8_8," newline hexmask.long.byte 0x7B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER278_LOWER__0_8," line.long 0x7B4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER278_upper,Interrupt Routing Registers" line.long 0x7B8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER279_lower,Interrupt Routing Registers" bitfld.long 0x7B8 31. "DISTRIBUTOR__37_GICD_IROUTER279_LOWER__31_1," "0,1" hexmask.long.byte 0x7B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER279_LOWER__8_8," newline hexmask.long.byte 0x7B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER279_LOWER__0_8," line.long 0x7BC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER279_upper,Interrupt Routing Registers" line.long 0x7C0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER280_lower,Interrupt Routing Registers" bitfld.long 0x7C0 31. "DISTRIBUTOR__37_GICD_IROUTER280_LOWER__31_1," "0,1" hexmask.long.byte 0x7C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER280_LOWER__8_8," newline hexmask.long.byte 0x7C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER280_LOWER__0_8," line.long 0x7C4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER280_upper,Interrupt Routing Registers" line.long 0x7C8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER281_lower,Interrupt Routing Registers" bitfld.long 0x7C8 31. "DISTRIBUTOR__37_GICD_IROUTER281_LOWER__31_1," "0,1" hexmask.long.byte 0x7C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER281_LOWER__8_8," newline hexmask.long.byte 0x7C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER281_LOWER__0_8," line.long 0x7CC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER281_upper,Interrupt Routing Registers" line.long 0x7D0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER282_lower,Interrupt Routing Registers" bitfld.long 0x7D0 31. "DISTRIBUTOR__37_GICD_IROUTER282_LOWER__31_1," "0,1" hexmask.long.byte 0x7D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER282_LOWER__8_8," newline hexmask.long.byte 0x7D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER282_LOWER__0_8," line.long 0x7D4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER282_upper,Interrupt Routing Registers" line.long 0x7D8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER283_lower,Interrupt Routing Registers" bitfld.long 0x7D8 31. "DISTRIBUTOR__37_GICD_IROUTER283_LOWER__31_1," "0,1" hexmask.long.byte 0x7D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER283_LOWER__8_8," newline hexmask.long.byte 0x7D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER283_LOWER__0_8," line.long 0x7DC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER283_upper,Interrupt Routing Registers" line.long 0x7E0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER284_lower,Interrupt Routing Registers" bitfld.long 0x7E0 31. "DISTRIBUTOR__37_GICD_IROUTER284_LOWER__31_1," "0,1" hexmask.long.byte 0x7E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER284_LOWER__8_8," newline hexmask.long.byte 0x7E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER284_LOWER__0_8," line.long 0x7E4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER284_upper,Interrupt Routing Registers" line.long 0x7E8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER285_lower,Interrupt Routing Registers" bitfld.long 0x7E8 31. "DISTRIBUTOR__37_GICD_IROUTER285_LOWER__31_1," "0,1" hexmask.long.byte 0x7E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER285_LOWER__8_8," newline hexmask.long.byte 0x7E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER285_LOWER__0_8," line.long 0x7EC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER285_upper,Interrupt Routing Registers" line.long 0x7F0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER286_lower,Interrupt Routing Registers" bitfld.long 0x7F0 31. "DISTRIBUTOR__37_GICD_IROUTER286_LOWER__31_1," "0,1" hexmask.long.byte 0x7F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER286_LOWER__8_8," newline hexmask.long.byte 0x7F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER286_LOWER__0_8," line.long 0x7F4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER286_upper,Interrupt Routing Registers" line.long 0x7F8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER287_lower,Interrupt Routing Registers" bitfld.long 0x7F8 31. "DISTRIBUTOR__37_GICD_IROUTER287_LOWER__31_1," "0,1" hexmask.long.byte 0x7F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER287_LOWER__8_8," newline hexmask.long.byte 0x7F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER287_LOWER__0_8," line.long 0x7FC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER287_upper,Interrupt Routing Registers" line.long 0x800 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER288_lower,Interrupt Routing Registers" bitfld.long 0x800 31. "DISTRIBUTOR__37_GICD_IROUTER288_LOWER__31_1," "0,1" hexmask.long.byte 0x800 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER288_LOWER__8_8," newline hexmask.long.byte 0x800 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER288_LOWER__0_8," line.long 0x804 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER288_upper,Interrupt Routing Registers" line.long 0x808 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER289_lower,Interrupt Routing Registers" bitfld.long 0x808 31. "DISTRIBUTOR__37_GICD_IROUTER289_LOWER__31_1," "0,1" hexmask.long.byte 0x808 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER289_LOWER__8_8," newline hexmask.long.byte 0x808 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER289_LOWER__0_8," line.long 0x80C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER289_upper,Interrupt Routing Registers" line.long 0x810 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER290_lower,Interrupt Routing Registers" bitfld.long 0x810 31. "DISTRIBUTOR__37_GICD_IROUTER290_LOWER__31_1," "0,1" hexmask.long.byte 0x810 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER290_LOWER__8_8," newline hexmask.long.byte 0x810 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER290_LOWER__0_8," line.long 0x814 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER290_upper,Interrupt Routing Registers" line.long 0x818 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER291_lower,Interrupt Routing Registers" bitfld.long 0x818 31. "DISTRIBUTOR__37_GICD_IROUTER291_LOWER__31_1," "0,1" hexmask.long.byte 0x818 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER291_LOWER__8_8," newline hexmask.long.byte 0x818 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER291_LOWER__0_8," line.long 0x81C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER291_upper,Interrupt Routing Registers" line.long 0x820 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER292_lower,Interrupt Routing Registers" bitfld.long 0x820 31. "DISTRIBUTOR__37_GICD_IROUTER292_LOWER__31_1," "0,1" hexmask.long.byte 0x820 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER292_LOWER__8_8," newline hexmask.long.byte 0x820 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER292_LOWER__0_8," line.long 0x824 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER292_upper,Interrupt Routing Registers" line.long 0x828 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER293_lower,Interrupt Routing Registers" bitfld.long 0x828 31. "DISTRIBUTOR__37_GICD_IROUTER293_LOWER__31_1," "0,1" hexmask.long.byte 0x828 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER293_LOWER__8_8," newline hexmask.long.byte 0x828 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER293_LOWER__0_8," line.long 0x82C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER293_upper,Interrupt Routing Registers" line.long 0x830 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER294_lower,Interrupt Routing Registers" bitfld.long 0x830 31. "DISTRIBUTOR__37_GICD_IROUTER294_LOWER__31_1," "0,1" hexmask.long.byte 0x830 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER294_LOWER__8_8," newline hexmask.long.byte 0x830 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER294_LOWER__0_8," line.long 0x834 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER294_upper,Interrupt Routing Registers" line.long 0x838 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER295_lower,Interrupt Routing Registers" bitfld.long 0x838 31. "DISTRIBUTOR__37_GICD_IROUTER295_LOWER__31_1," "0,1" hexmask.long.byte 0x838 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER295_LOWER__8_8," newline hexmask.long.byte 0x838 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER295_LOWER__0_8," line.long 0x83C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER295_upper,Interrupt Routing Registers" line.long 0x840 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER296_lower,Interrupt Routing Registers" bitfld.long 0x840 31. "DISTRIBUTOR__37_GICD_IROUTER296_LOWER__31_1," "0,1" hexmask.long.byte 0x840 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER296_LOWER__8_8," newline hexmask.long.byte 0x840 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER296_LOWER__0_8," line.long 0x844 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER296_upper,Interrupt Routing Registers" line.long 0x848 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER297_lower,Interrupt Routing Registers" bitfld.long 0x848 31. "DISTRIBUTOR__37_GICD_IROUTER297_LOWER__31_1," "0,1" hexmask.long.byte 0x848 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER297_LOWER__8_8," newline hexmask.long.byte 0x848 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER297_LOWER__0_8," line.long 0x84C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER297_upper,Interrupt Routing Registers" line.long 0x850 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER298_lower,Interrupt Routing Registers" bitfld.long 0x850 31. "DISTRIBUTOR__37_GICD_IROUTER298_LOWER__31_1," "0,1" hexmask.long.byte 0x850 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER298_LOWER__8_8," newline hexmask.long.byte 0x850 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER298_LOWER__0_8," line.long 0x854 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER298_upper,Interrupt Routing Registers" line.long 0x858 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER299_lower,Interrupt Routing Registers" bitfld.long 0x858 31. "DISTRIBUTOR__37_GICD_IROUTER299_LOWER__31_1," "0,1" hexmask.long.byte 0x858 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER299_LOWER__8_8," newline hexmask.long.byte 0x858 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER299_LOWER__0_8," line.long 0x85C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER299_upper,Interrupt Routing Registers" line.long 0x860 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER300_lower,Interrupt Routing Registers" bitfld.long 0x860 31. "DISTRIBUTOR__37_GICD_IROUTER300_LOWER__31_1," "0,1" hexmask.long.byte 0x860 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER300_LOWER__8_8," newline hexmask.long.byte 0x860 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER300_LOWER__0_8," line.long 0x864 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER300_upper,Interrupt Routing Registers" line.long 0x868 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER301_lower,Interrupt Routing Registers" bitfld.long 0x868 31. "DISTRIBUTOR__37_GICD_IROUTER301_LOWER__31_1," "0,1" hexmask.long.byte 0x868 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER301_LOWER__8_8," newline hexmask.long.byte 0x868 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER301_LOWER__0_8," line.long 0x86C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER301_upper,Interrupt Routing Registers" line.long 0x870 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER302_lower,Interrupt Routing Registers" bitfld.long 0x870 31. "DISTRIBUTOR__37_GICD_IROUTER302_LOWER__31_1," "0,1" hexmask.long.byte 0x870 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER302_LOWER__8_8," newline hexmask.long.byte 0x870 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER302_LOWER__0_8," line.long 0x874 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER302_upper,Interrupt Routing Registers" line.long 0x878 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER303_lower,Interrupt Routing Registers" bitfld.long 0x878 31. "DISTRIBUTOR__37_GICD_IROUTER303_LOWER__31_1," "0,1" hexmask.long.byte 0x878 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER303_LOWER__8_8," newline hexmask.long.byte 0x878 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER303_LOWER__0_8," line.long 0x87C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER303_upper,Interrupt Routing Registers" line.long 0x880 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER304_lower,Interrupt Routing Registers" bitfld.long 0x880 31. "DISTRIBUTOR__37_GICD_IROUTER304_LOWER__31_1," "0,1" hexmask.long.byte 0x880 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER304_LOWER__8_8," newline hexmask.long.byte 0x880 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER304_LOWER__0_8," line.long 0x884 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER304_upper,Interrupt Routing Registers" line.long 0x888 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER305_lower,Interrupt Routing Registers" bitfld.long 0x888 31. "DISTRIBUTOR__37_GICD_IROUTER305_LOWER__31_1," "0,1" hexmask.long.byte 0x888 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER305_LOWER__8_8," newline hexmask.long.byte 0x888 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER305_LOWER__0_8," line.long 0x88C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER305_upper,Interrupt Routing Registers" line.long 0x890 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER306_lower,Interrupt Routing Registers" bitfld.long 0x890 31. "DISTRIBUTOR__37_GICD_IROUTER306_LOWER__31_1," "0,1" hexmask.long.byte 0x890 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER306_LOWER__8_8," newline hexmask.long.byte 0x890 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER306_LOWER__0_8," line.long 0x894 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER306_upper,Interrupt Routing Registers" line.long 0x898 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER307_lower,Interrupt Routing Registers" bitfld.long 0x898 31. "DISTRIBUTOR__37_GICD_IROUTER307_LOWER__31_1," "0,1" hexmask.long.byte 0x898 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER307_LOWER__8_8," newline hexmask.long.byte 0x898 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER307_LOWER__0_8," line.long 0x89C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER307_upper,Interrupt Routing Registers" line.long 0x8A0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER308_lower,Interrupt Routing Registers" bitfld.long 0x8A0 31. "DISTRIBUTOR__37_GICD_IROUTER308_LOWER__31_1," "0,1" hexmask.long.byte 0x8A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER308_LOWER__8_8," newline hexmask.long.byte 0x8A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER308_LOWER__0_8," line.long 0x8A4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER308_upper,Interrupt Routing Registers" line.long 0x8A8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER309_lower,Interrupt Routing Registers" bitfld.long 0x8A8 31. "DISTRIBUTOR__37_GICD_IROUTER309_LOWER__31_1," "0,1" hexmask.long.byte 0x8A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER309_LOWER__8_8," newline hexmask.long.byte 0x8A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER309_LOWER__0_8," line.long 0x8AC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER309_upper,Interrupt Routing Registers" line.long 0x8B0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER310_lower,Interrupt Routing Registers" bitfld.long 0x8B0 31. "DISTRIBUTOR__37_GICD_IROUTER310_LOWER__31_1," "0,1" hexmask.long.byte 0x8B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER310_LOWER__8_8," newline hexmask.long.byte 0x8B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER310_LOWER__0_8," line.long 0x8B4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER310_upper,Interrupt Routing Registers" line.long 0x8B8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER311_lower,Interrupt Routing Registers" bitfld.long 0x8B8 31. "DISTRIBUTOR__37_GICD_IROUTER311_LOWER__31_1," "0,1" hexmask.long.byte 0x8B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER311_LOWER__8_8," newline hexmask.long.byte 0x8B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER311_LOWER__0_8," line.long 0x8BC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER311_upper,Interrupt Routing Registers" line.long 0x8C0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER312_lower,Interrupt Routing Registers" bitfld.long 0x8C0 31. "DISTRIBUTOR__37_GICD_IROUTER312_LOWER__31_1," "0,1" hexmask.long.byte 0x8C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER312_LOWER__8_8," newline hexmask.long.byte 0x8C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER312_LOWER__0_8," line.long 0x8C4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER312_upper,Interrupt Routing Registers" line.long 0x8C8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER313_lower,Interrupt Routing Registers" bitfld.long 0x8C8 31. "DISTRIBUTOR__37_GICD_IROUTER313_LOWER__31_1," "0,1" hexmask.long.byte 0x8C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER313_LOWER__8_8," newline hexmask.long.byte 0x8C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER313_LOWER__0_8," line.long 0x8CC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER313_upper,Interrupt Routing Registers" line.long 0x8D0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER314_lower,Interrupt Routing Registers" bitfld.long 0x8D0 31. "DISTRIBUTOR__37_GICD_IROUTER314_LOWER__31_1," "0,1" hexmask.long.byte 0x8D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER314_LOWER__8_8," newline hexmask.long.byte 0x8D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER314_LOWER__0_8," line.long 0x8D4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER314_upper,Interrupt Routing Registers" line.long 0x8D8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER315_lower,Interrupt Routing Registers" bitfld.long 0x8D8 31. "DISTRIBUTOR__37_GICD_IROUTER315_LOWER__31_1," "0,1" hexmask.long.byte 0x8D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER315_LOWER__8_8," newline hexmask.long.byte 0x8D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER315_LOWER__0_8," line.long 0x8DC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER315_upper,Interrupt Routing Registers" line.long 0x8E0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER316_lower,Interrupt Routing Registers" bitfld.long 0x8E0 31. "DISTRIBUTOR__37_GICD_IROUTER316_LOWER__31_1," "0,1" hexmask.long.byte 0x8E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER316_LOWER__8_8," newline hexmask.long.byte 0x8E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER316_LOWER__0_8," line.long 0x8E4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER316_upper,Interrupt Routing Registers" line.long 0x8E8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER317_lower,Interrupt Routing Registers" bitfld.long 0x8E8 31. "DISTRIBUTOR__37_GICD_IROUTER317_LOWER__31_1," "0,1" hexmask.long.byte 0x8E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER317_LOWER__8_8," newline hexmask.long.byte 0x8E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER317_LOWER__0_8," line.long 0x8EC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER317_upper,Interrupt Routing Registers" line.long 0x8F0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER318_lower,Interrupt Routing Registers" bitfld.long 0x8F0 31. "DISTRIBUTOR__37_GICD_IROUTER318_LOWER__31_1," "0,1" hexmask.long.byte 0x8F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER318_LOWER__8_8," newline hexmask.long.byte 0x8F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER318_LOWER__0_8," line.long 0x8F4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER318_upper,Interrupt Routing Registers" line.long 0x8F8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER319_lower,Interrupt Routing Registers" bitfld.long 0x8F8 31. "DISTRIBUTOR__37_GICD_IROUTER319_LOWER__31_1," "0,1" hexmask.long.byte 0x8F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER319_LOWER__8_8," newline hexmask.long.byte 0x8F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER319_LOWER__0_8," line.long 0x8FC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER319_upper,Interrupt Routing Registers" line.long 0x900 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER320_lower,Interrupt Routing Registers" bitfld.long 0x900 31. "DISTRIBUTOR__37_GICD_IROUTER320_LOWER__31_1," "0,1" hexmask.long.byte 0x900 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER320_LOWER__8_8," newline hexmask.long.byte 0x900 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER320_LOWER__0_8," line.long 0x904 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER320_upper,Interrupt Routing Registers" line.long 0x908 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER321_lower,Interrupt Routing Registers" bitfld.long 0x908 31. "DISTRIBUTOR__37_GICD_IROUTER321_LOWER__31_1," "0,1" hexmask.long.byte 0x908 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER321_LOWER__8_8," newline hexmask.long.byte 0x908 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER321_LOWER__0_8," line.long 0x90C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER321_upper,Interrupt Routing Registers" line.long 0x910 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER322_lower,Interrupt Routing Registers" bitfld.long 0x910 31. "DISTRIBUTOR__37_GICD_IROUTER322_LOWER__31_1," "0,1" hexmask.long.byte 0x910 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER322_LOWER__8_8," newline hexmask.long.byte 0x910 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER322_LOWER__0_8," line.long 0x914 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER322_upper,Interrupt Routing Registers" line.long 0x918 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER323_lower,Interrupt Routing Registers" bitfld.long 0x918 31. "DISTRIBUTOR__37_GICD_IROUTER323_LOWER__31_1," "0,1" hexmask.long.byte 0x918 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER323_LOWER__8_8," newline hexmask.long.byte 0x918 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER323_LOWER__0_8," line.long 0x91C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER323_upper,Interrupt Routing Registers" line.long 0x920 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER324_lower,Interrupt Routing Registers" bitfld.long 0x920 31. "DISTRIBUTOR__37_GICD_IROUTER324_LOWER__31_1," "0,1" hexmask.long.byte 0x920 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER324_LOWER__8_8," newline hexmask.long.byte 0x920 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER324_LOWER__0_8," line.long 0x924 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER324_upper,Interrupt Routing Registers" line.long 0x928 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER325_lower,Interrupt Routing Registers" bitfld.long 0x928 31. "DISTRIBUTOR__37_GICD_IROUTER325_LOWER__31_1," "0,1" hexmask.long.byte 0x928 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER325_LOWER__8_8," newline hexmask.long.byte 0x928 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER325_LOWER__0_8," line.long 0x92C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER325_upper,Interrupt Routing Registers" line.long 0x930 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER326_lower,Interrupt Routing Registers" bitfld.long 0x930 31. "DISTRIBUTOR__37_GICD_IROUTER326_LOWER__31_1," "0,1" hexmask.long.byte 0x930 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER326_LOWER__8_8," newline hexmask.long.byte 0x930 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER326_LOWER__0_8," line.long 0x934 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER326_upper,Interrupt Routing Registers" line.long 0x938 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER327_lower,Interrupt Routing Registers" bitfld.long 0x938 31. "DISTRIBUTOR__37_GICD_IROUTER327_LOWER__31_1," "0,1" hexmask.long.byte 0x938 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER327_LOWER__8_8," newline hexmask.long.byte 0x938 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER327_LOWER__0_8," line.long 0x93C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER327_upper,Interrupt Routing Registers" line.long 0x940 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER328_lower,Interrupt Routing Registers" bitfld.long 0x940 31. "DISTRIBUTOR__37_GICD_IROUTER328_LOWER__31_1," "0,1" hexmask.long.byte 0x940 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER328_LOWER__8_8," newline hexmask.long.byte 0x940 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER328_LOWER__0_8," line.long 0x944 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER328_upper,Interrupt Routing Registers" line.long 0x948 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER329_lower,Interrupt Routing Registers" bitfld.long 0x948 31. "DISTRIBUTOR__37_GICD_IROUTER329_LOWER__31_1," "0,1" hexmask.long.byte 0x948 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER329_LOWER__8_8," newline hexmask.long.byte 0x948 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER329_LOWER__0_8," line.long 0x94C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER329_upper,Interrupt Routing Registers" line.long 0x950 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER330_lower,Interrupt Routing Registers" bitfld.long 0x950 31. "DISTRIBUTOR__37_GICD_IROUTER330_LOWER__31_1," "0,1" hexmask.long.byte 0x950 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER330_LOWER__8_8," newline hexmask.long.byte 0x950 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER330_LOWER__0_8," line.long 0x954 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER330_upper,Interrupt Routing Registers" line.long 0x958 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER331_lower,Interrupt Routing Registers" bitfld.long 0x958 31. "DISTRIBUTOR__37_GICD_IROUTER331_LOWER__31_1," "0,1" hexmask.long.byte 0x958 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER331_LOWER__8_8," newline hexmask.long.byte 0x958 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER331_LOWER__0_8," line.long 0x95C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER331_upper,Interrupt Routing Registers" line.long 0x960 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER332_lower,Interrupt Routing Registers" bitfld.long 0x960 31. "DISTRIBUTOR__37_GICD_IROUTER332_LOWER__31_1," "0,1" hexmask.long.byte 0x960 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER332_LOWER__8_8," newline hexmask.long.byte 0x960 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER332_LOWER__0_8," line.long 0x964 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER332_upper,Interrupt Routing Registers" line.long 0x968 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER333_lower,Interrupt Routing Registers" bitfld.long 0x968 31. "DISTRIBUTOR__37_GICD_IROUTER333_LOWER__31_1," "0,1" hexmask.long.byte 0x968 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER333_LOWER__8_8," newline hexmask.long.byte 0x968 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER333_LOWER__0_8," line.long 0x96C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER333_upper,Interrupt Routing Registers" line.long 0x970 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER334_lower,Interrupt Routing Registers" bitfld.long 0x970 31. "DISTRIBUTOR__37_GICD_IROUTER334_LOWER__31_1," "0,1" hexmask.long.byte 0x970 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER334_LOWER__8_8," newline hexmask.long.byte 0x970 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER334_LOWER__0_8," line.long 0x974 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER334_upper,Interrupt Routing Registers" line.long 0x978 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER335_lower,Interrupt Routing Registers" bitfld.long 0x978 31. "DISTRIBUTOR__37_GICD_IROUTER335_LOWER__31_1," "0,1" hexmask.long.byte 0x978 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER335_LOWER__8_8," newline hexmask.long.byte 0x978 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER335_LOWER__0_8," line.long 0x97C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER335_upper,Interrupt Routing Registers" line.long 0x980 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER336_lower,Interrupt Routing Registers" bitfld.long 0x980 31. "DISTRIBUTOR__37_GICD_IROUTER336_LOWER__31_1," "0,1" hexmask.long.byte 0x980 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER336_LOWER__8_8," newline hexmask.long.byte 0x980 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER336_LOWER__0_8," line.long 0x984 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER336_upper,Interrupt Routing Registers" line.long 0x988 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER337_lower,Interrupt Routing Registers" bitfld.long 0x988 31. "DISTRIBUTOR__37_GICD_IROUTER337_LOWER__31_1," "0,1" hexmask.long.byte 0x988 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER337_LOWER__8_8," newline hexmask.long.byte 0x988 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER337_LOWER__0_8," line.long 0x98C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER337_upper,Interrupt Routing Registers" line.long 0x990 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER338_lower,Interrupt Routing Registers" bitfld.long 0x990 31. "DISTRIBUTOR__37_GICD_IROUTER338_LOWER__31_1," "0,1" hexmask.long.byte 0x990 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER338_LOWER__8_8," newline hexmask.long.byte 0x990 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER338_LOWER__0_8," line.long 0x994 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER338_upper,Interrupt Routing Registers" line.long 0x998 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER339_lower,Interrupt Routing Registers" bitfld.long 0x998 31. "DISTRIBUTOR__37_GICD_IROUTER339_LOWER__31_1," "0,1" hexmask.long.byte 0x998 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER339_LOWER__8_8," newline hexmask.long.byte 0x998 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER339_LOWER__0_8," line.long 0x99C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER339_upper,Interrupt Routing Registers" line.long 0x9A0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER340_lower,Interrupt Routing Registers" bitfld.long 0x9A0 31. "DISTRIBUTOR__37_GICD_IROUTER340_LOWER__31_1," "0,1" hexmask.long.byte 0x9A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER340_LOWER__8_8," newline hexmask.long.byte 0x9A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER340_LOWER__0_8," line.long 0x9A4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER340_upper,Interrupt Routing Registers" line.long 0x9A8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER341_lower,Interrupt Routing Registers" bitfld.long 0x9A8 31. "DISTRIBUTOR__37_GICD_IROUTER341_LOWER__31_1," "0,1" hexmask.long.byte 0x9A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER341_LOWER__8_8," newline hexmask.long.byte 0x9A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER341_LOWER__0_8," line.long 0x9AC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER341_upper,Interrupt Routing Registers" line.long 0x9B0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER342_lower,Interrupt Routing Registers" bitfld.long 0x9B0 31. "DISTRIBUTOR__37_GICD_IROUTER342_LOWER__31_1," "0,1" hexmask.long.byte 0x9B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER342_LOWER__8_8," newline hexmask.long.byte 0x9B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER342_LOWER__0_8," line.long 0x9B4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER342_upper,Interrupt Routing Registers" line.long 0x9B8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER343_lower,Interrupt Routing Registers" bitfld.long 0x9B8 31. "DISTRIBUTOR__37_GICD_IROUTER343_LOWER__31_1," "0,1" hexmask.long.byte 0x9B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER343_LOWER__8_8," newline hexmask.long.byte 0x9B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER343_LOWER__0_8," line.long 0x9BC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER343_upper,Interrupt Routing Registers" line.long 0x9C0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER344_lower,Interrupt Routing Registers" bitfld.long 0x9C0 31. "DISTRIBUTOR__37_GICD_IROUTER344_LOWER__31_1," "0,1" hexmask.long.byte 0x9C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER344_LOWER__8_8," newline hexmask.long.byte 0x9C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER344_LOWER__0_8," line.long 0x9C4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER344_upper,Interrupt Routing Registers" line.long 0x9C8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER345_lower,Interrupt Routing Registers" bitfld.long 0x9C8 31. "DISTRIBUTOR__37_GICD_IROUTER345_LOWER__31_1," "0,1" hexmask.long.byte 0x9C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER345_LOWER__8_8," newline hexmask.long.byte 0x9C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER345_LOWER__0_8," line.long 0x9CC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER345_upper,Interrupt Routing Registers" line.long 0x9D0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER346_lower,Interrupt Routing Registers" bitfld.long 0x9D0 31. "DISTRIBUTOR__37_GICD_IROUTER346_LOWER__31_1," "0,1" hexmask.long.byte 0x9D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER346_LOWER__8_8," newline hexmask.long.byte 0x9D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER346_LOWER__0_8," line.long 0x9D4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER346_upper,Interrupt Routing Registers" line.long 0x9D8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER347_lower,Interrupt Routing Registers" bitfld.long 0x9D8 31. "DISTRIBUTOR__37_GICD_IROUTER347_LOWER__31_1," "0,1" hexmask.long.byte 0x9D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER347_LOWER__8_8," newline hexmask.long.byte 0x9D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER347_LOWER__0_8," line.long 0x9DC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER347_upper,Interrupt Routing Registers" line.long 0x9E0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER348_lower,Interrupt Routing Registers" bitfld.long 0x9E0 31. "DISTRIBUTOR__37_GICD_IROUTER348_LOWER__31_1," "0,1" hexmask.long.byte 0x9E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER348_LOWER__8_8," newline hexmask.long.byte 0x9E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER348_LOWER__0_8," line.long 0x9E4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER348_upper,Interrupt Routing Registers" line.long 0x9E8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER349_lower,Interrupt Routing Registers" bitfld.long 0x9E8 31. "DISTRIBUTOR__37_GICD_IROUTER349_LOWER__31_1," "0,1" hexmask.long.byte 0x9E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER349_LOWER__8_8," newline hexmask.long.byte 0x9E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER349_LOWER__0_8," line.long 0x9EC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER349_upper,Interrupt Routing Registers" line.long 0x9F0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER350_lower,Interrupt Routing Registers" bitfld.long 0x9F0 31. "DISTRIBUTOR__37_GICD_IROUTER350_LOWER__31_1," "0,1" hexmask.long.byte 0x9F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER350_LOWER__8_8," newline hexmask.long.byte 0x9F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER350_LOWER__0_8," line.long 0x9F4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER350_upper,Interrupt Routing Registers" line.long 0x9F8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER351_lower,Interrupt Routing Registers" bitfld.long 0x9F8 31. "DISTRIBUTOR__37_GICD_IROUTER351_LOWER__31_1," "0,1" hexmask.long.byte 0x9F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER351_LOWER__8_8," newline hexmask.long.byte 0x9F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER351_LOWER__0_8," line.long 0x9FC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER351_upper,Interrupt Routing Registers" line.long 0xA00 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER352_lower,Interrupt Routing Registers" bitfld.long 0xA00 31. "DISTRIBUTOR__37_GICD_IROUTER352_LOWER__31_1," "0,1" hexmask.long.byte 0xA00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER352_LOWER__8_8," newline hexmask.long.byte 0xA00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER352_LOWER__0_8," line.long 0xA04 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER352_upper,Interrupt Routing Registers" line.long 0xA08 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER353_lower,Interrupt Routing Registers" bitfld.long 0xA08 31. "DISTRIBUTOR__37_GICD_IROUTER353_LOWER__31_1," "0,1" hexmask.long.byte 0xA08 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER353_LOWER__8_8," newline hexmask.long.byte 0xA08 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER353_LOWER__0_8," line.long 0xA0C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER353_upper,Interrupt Routing Registers" line.long 0xA10 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER354_lower,Interrupt Routing Registers" bitfld.long 0xA10 31. "DISTRIBUTOR__37_GICD_IROUTER354_LOWER__31_1," "0,1" hexmask.long.byte 0xA10 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER354_LOWER__8_8," newline hexmask.long.byte 0xA10 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER354_LOWER__0_8," line.long 0xA14 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER354_upper,Interrupt Routing Registers" line.long 0xA18 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER355_lower,Interrupt Routing Registers" bitfld.long 0xA18 31. "DISTRIBUTOR__37_GICD_IROUTER355_LOWER__31_1," "0,1" hexmask.long.byte 0xA18 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER355_LOWER__8_8," newline hexmask.long.byte 0xA18 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER355_LOWER__0_8," line.long 0xA1C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER355_upper,Interrupt Routing Registers" line.long 0xA20 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER356_lower,Interrupt Routing Registers" bitfld.long 0xA20 31. "DISTRIBUTOR__37_GICD_IROUTER356_LOWER__31_1," "0,1" hexmask.long.byte 0xA20 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER356_LOWER__8_8," newline hexmask.long.byte 0xA20 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER356_LOWER__0_8," line.long 0xA24 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER356_upper,Interrupt Routing Registers" line.long 0xA28 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER357_lower,Interrupt Routing Registers" bitfld.long 0xA28 31. "DISTRIBUTOR__37_GICD_IROUTER357_LOWER__31_1," "0,1" hexmask.long.byte 0xA28 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER357_LOWER__8_8," newline hexmask.long.byte 0xA28 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER357_LOWER__0_8," line.long 0xA2C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER357_upper,Interrupt Routing Registers" line.long 0xA30 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER358_lower,Interrupt Routing Registers" bitfld.long 0xA30 31. "DISTRIBUTOR__37_GICD_IROUTER358_LOWER__31_1," "0,1" hexmask.long.byte 0xA30 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER358_LOWER__8_8," newline hexmask.long.byte 0xA30 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER358_LOWER__0_8," line.long 0xA34 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER358_upper,Interrupt Routing Registers" line.long 0xA38 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER359_lower,Interrupt Routing Registers" bitfld.long 0xA38 31. "DISTRIBUTOR__37_GICD_IROUTER359_LOWER__31_1," "0,1" hexmask.long.byte 0xA38 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER359_LOWER__8_8," newline hexmask.long.byte 0xA38 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER359_LOWER__0_8," line.long 0xA3C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER359_upper,Interrupt Routing Registers" line.long 0xA40 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER360_lower,Interrupt Routing Registers" bitfld.long 0xA40 31. "DISTRIBUTOR__37_GICD_IROUTER360_LOWER__31_1," "0,1" hexmask.long.byte 0xA40 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER360_LOWER__8_8," newline hexmask.long.byte 0xA40 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER360_LOWER__0_8," line.long 0xA44 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER360_upper,Interrupt Routing Registers" line.long 0xA48 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER361_lower,Interrupt Routing Registers" bitfld.long 0xA48 31. "DISTRIBUTOR__37_GICD_IROUTER361_LOWER__31_1," "0,1" hexmask.long.byte 0xA48 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER361_LOWER__8_8," newline hexmask.long.byte 0xA48 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER361_LOWER__0_8," line.long 0xA4C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER361_upper,Interrupt Routing Registers" line.long 0xA50 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER362_lower,Interrupt Routing Registers" bitfld.long 0xA50 31. "DISTRIBUTOR__37_GICD_IROUTER362_LOWER__31_1," "0,1" hexmask.long.byte 0xA50 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER362_LOWER__8_8," newline hexmask.long.byte 0xA50 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER362_LOWER__0_8," line.long 0xA54 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER362_upper,Interrupt Routing Registers" line.long 0xA58 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER363_lower,Interrupt Routing Registers" bitfld.long 0xA58 31. "DISTRIBUTOR__37_GICD_IROUTER363_LOWER__31_1," "0,1" hexmask.long.byte 0xA58 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER363_LOWER__8_8," newline hexmask.long.byte 0xA58 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER363_LOWER__0_8," line.long 0xA5C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER363_upper,Interrupt Routing Registers" line.long 0xA60 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER364_lower,Interrupt Routing Registers" bitfld.long 0xA60 31. "DISTRIBUTOR__37_GICD_IROUTER364_LOWER__31_1," "0,1" hexmask.long.byte 0xA60 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER364_LOWER__8_8," newline hexmask.long.byte 0xA60 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER364_LOWER__0_8," line.long 0xA64 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER364_upper,Interrupt Routing Registers" line.long 0xA68 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER365_lower,Interrupt Routing Registers" bitfld.long 0xA68 31. "DISTRIBUTOR__37_GICD_IROUTER365_LOWER__31_1," "0,1" hexmask.long.byte 0xA68 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER365_LOWER__8_8," newline hexmask.long.byte 0xA68 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER365_LOWER__0_8," line.long 0xA6C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER365_upper,Interrupt Routing Registers" line.long 0xA70 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER366_lower,Interrupt Routing Registers" bitfld.long 0xA70 31. "DISTRIBUTOR__37_GICD_IROUTER366_LOWER__31_1," "0,1" hexmask.long.byte 0xA70 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER366_LOWER__8_8," newline hexmask.long.byte 0xA70 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER366_LOWER__0_8," line.long 0xA74 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER366_upper,Interrupt Routing Registers" line.long 0xA78 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER367_lower,Interrupt Routing Registers" bitfld.long 0xA78 31. "DISTRIBUTOR__37_GICD_IROUTER367_LOWER__31_1," "0,1" hexmask.long.byte 0xA78 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER367_LOWER__8_8," newline hexmask.long.byte 0xA78 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER367_LOWER__0_8," line.long 0xA7C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER367_upper,Interrupt Routing Registers" line.long 0xA80 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER368_lower,Interrupt Routing Registers" bitfld.long 0xA80 31. "DISTRIBUTOR__37_GICD_IROUTER368_LOWER__31_1," "0,1" hexmask.long.byte 0xA80 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER368_LOWER__8_8," newline hexmask.long.byte 0xA80 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER368_LOWER__0_8," line.long 0xA84 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER368_upper,Interrupt Routing Registers" line.long 0xA88 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER369_lower,Interrupt Routing Registers" bitfld.long 0xA88 31. "DISTRIBUTOR__37_GICD_IROUTER369_LOWER__31_1," "0,1" hexmask.long.byte 0xA88 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER369_LOWER__8_8," newline hexmask.long.byte 0xA88 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER369_LOWER__0_8," line.long 0xA8C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER369_upper,Interrupt Routing Registers" line.long 0xA90 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER370_lower,Interrupt Routing Registers" bitfld.long 0xA90 31. "DISTRIBUTOR__37_GICD_IROUTER370_LOWER__31_1," "0,1" hexmask.long.byte 0xA90 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER370_LOWER__8_8," newline hexmask.long.byte 0xA90 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER370_LOWER__0_8," line.long 0xA94 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER370_upper,Interrupt Routing Registers" line.long 0xA98 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER371_lower,Interrupt Routing Registers" bitfld.long 0xA98 31. "DISTRIBUTOR__37_GICD_IROUTER371_LOWER__31_1," "0,1" hexmask.long.byte 0xA98 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER371_LOWER__8_8," newline hexmask.long.byte 0xA98 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER371_LOWER__0_8," line.long 0xA9C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER371_upper,Interrupt Routing Registers" line.long 0xAA0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER372_lower,Interrupt Routing Registers" bitfld.long 0xAA0 31. "DISTRIBUTOR__37_GICD_IROUTER372_LOWER__31_1," "0,1" hexmask.long.byte 0xAA0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER372_LOWER__8_8," newline hexmask.long.byte 0xAA0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER372_LOWER__0_8," line.long 0xAA4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER372_upper,Interrupt Routing Registers" line.long 0xAA8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER373_lower,Interrupt Routing Registers" bitfld.long 0xAA8 31. "DISTRIBUTOR__37_GICD_IROUTER373_LOWER__31_1," "0,1" hexmask.long.byte 0xAA8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER373_LOWER__8_8," newline hexmask.long.byte 0xAA8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER373_LOWER__0_8," line.long 0xAAC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER373_upper,Interrupt Routing Registers" line.long 0xAB0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER374_lower,Interrupt Routing Registers" bitfld.long 0xAB0 31. "DISTRIBUTOR__37_GICD_IROUTER374_LOWER__31_1," "0,1" hexmask.long.byte 0xAB0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER374_LOWER__8_8," newline hexmask.long.byte 0xAB0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER374_LOWER__0_8," line.long 0xAB4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER374_upper,Interrupt Routing Registers" line.long 0xAB8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER375_lower,Interrupt Routing Registers" bitfld.long 0xAB8 31. "DISTRIBUTOR__37_GICD_IROUTER375_LOWER__31_1," "0,1" hexmask.long.byte 0xAB8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER375_LOWER__8_8," newline hexmask.long.byte 0xAB8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER375_LOWER__0_8," line.long 0xABC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER375_upper,Interrupt Routing Registers" line.long 0xAC0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER376_lower,Interrupt Routing Registers" bitfld.long 0xAC0 31. "DISTRIBUTOR__37_GICD_IROUTER376_LOWER__31_1," "0,1" hexmask.long.byte 0xAC0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER376_LOWER__8_8," newline hexmask.long.byte 0xAC0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER376_LOWER__0_8," line.long 0xAC4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER376_upper,Interrupt Routing Registers" line.long 0xAC8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER377_lower,Interrupt Routing Registers" bitfld.long 0xAC8 31. "DISTRIBUTOR__37_GICD_IROUTER377_LOWER__31_1," "0,1" hexmask.long.byte 0xAC8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER377_LOWER__8_8," newline hexmask.long.byte 0xAC8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER377_LOWER__0_8," line.long 0xACC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER377_upper,Interrupt Routing Registers" line.long 0xAD0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER378_lower,Interrupt Routing Registers" bitfld.long 0xAD0 31. "DISTRIBUTOR__37_GICD_IROUTER378_LOWER__31_1," "0,1" hexmask.long.byte 0xAD0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER378_LOWER__8_8," newline hexmask.long.byte 0xAD0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER378_LOWER__0_8," line.long 0xAD4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER378_upper,Interrupt Routing Registers" line.long 0xAD8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER379_lower,Interrupt Routing Registers" bitfld.long 0xAD8 31. "DISTRIBUTOR__37_GICD_IROUTER379_LOWER__31_1," "0,1" hexmask.long.byte 0xAD8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER379_LOWER__8_8," newline hexmask.long.byte 0xAD8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER379_LOWER__0_8," line.long 0xADC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER379_upper,Interrupt Routing Registers" line.long 0xAE0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER380_lower,Interrupt Routing Registers" bitfld.long 0xAE0 31. "DISTRIBUTOR__37_GICD_IROUTER380_LOWER__31_1," "0,1" hexmask.long.byte 0xAE0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER380_LOWER__8_8," newline hexmask.long.byte 0xAE0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER380_LOWER__0_8," line.long 0xAE4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER380_upper,Interrupt Routing Registers" line.long 0xAE8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER381_lower,Interrupt Routing Registers" bitfld.long 0xAE8 31. "DISTRIBUTOR__37_GICD_IROUTER381_LOWER__31_1," "0,1" hexmask.long.byte 0xAE8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER381_LOWER__8_8," newline hexmask.long.byte 0xAE8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER381_LOWER__0_8," line.long 0xAEC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER381_upper,Interrupt Routing Registers" line.long 0xAF0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER382_lower,Interrupt Routing Registers" bitfld.long 0xAF0 31. "DISTRIBUTOR__37_GICD_IROUTER382_LOWER__31_1," "0,1" hexmask.long.byte 0xAF0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER382_LOWER__8_8," newline hexmask.long.byte 0xAF0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER382_LOWER__0_8," line.long 0xAF4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER382_upper,Interrupt Routing Registers" line.long 0xAF8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER383_lower,Interrupt Routing Registers" bitfld.long 0xAF8 31. "DISTRIBUTOR__37_GICD_IROUTER383_LOWER__31_1," "0,1" hexmask.long.byte 0xAF8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER383_LOWER__8_8," newline hexmask.long.byte 0xAF8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER383_LOWER__0_8," line.long 0xAFC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER383_upper,Interrupt Routing Registers" line.long 0xB00 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER384_lower,Interrupt Routing Registers" bitfld.long 0xB00 31. "DISTRIBUTOR__37_GICD_IROUTER384_LOWER__31_1," "0,1" hexmask.long.byte 0xB00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER384_LOWER__8_8," newline hexmask.long.byte 0xB00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER384_LOWER__0_8," line.long 0xB04 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER384_upper,Interrupt Routing Registers" line.long 0xB08 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER385_lower,Interrupt Routing Registers" bitfld.long 0xB08 31. "DISTRIBUTOR__37_GICD_IROUTER385_LOWER__31_1," "0,1" hexmask.long.byte 0xB08 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER385_LOWER__8_8," newline hexmask.long.byte 0xB08 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER385_LOWER__0_8," line.long 0xB0C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER385_upper,Interrupt Routing Registers" line.long 0xB10 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER386_lower,Interrupt Routing Registers" bitfld.long 0xB10 31. "DISTRIBUTOR__37_GICD_IROUTER386_LOWER__31_1," "0,1" hexmask.long.byte 0xB10 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER386_LOWER__8_8," newline hexmask.long.byte 0xB10 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER386_LOWER__0_8," line.long 0xB14 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER386_upper,Interrupt Routing Registers" line.long 0xB18 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER387_lower,Interrupt Routing Registers" bitfld.long 0xB18 31. "DISTRIBUTOR__37_GICD_IROUTER387_LOWER__31_1," "0,1" hexmask.long.byte 0xB18 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER387_LOWER__8_8," newline hexmask.long.byte 0xB18 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER387_LOWER__0_8," line.long 0xB1C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER387_upper,Interrupt Routing Registers" line.long 0xB20 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER388_lower,Interrupt Routing Registers" bitfld.long 0xB20 31. "DISTRIBUTOR__37_GICD_IROUTER388_LOWER__31_1," "0,1" hexmask.long.byte 0xB20 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER388_LOWER__8_8," newline hexmask.long.byte 0xB20 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER388_LOWER__0_8," line.long 0xB24 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER388_upper,Interrupt Routing Registers" line.long 0xB28 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER389_lower,Interrupt Routing Registers" bitfld.long 0xB28 31. "DISTRIBUTOR__37_GICD_IROUTER389_LOWER__31_1," "0,1" hexmask.long.byte 0xB28 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER389_LOWER__8_8," newline hexmask.long.byte 0xB28 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER389_LOWER__0_8," line.long 0xB2C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER389_upper,Interrupt Routing Registers" line.long 0xB30 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER390_lower,Interrupt Routing Registers" bitfld.long 0xB30 31. "DISTRIBUTOR__37_GICD_IROUTER390_LOWER__31_1," "0,1" hexmask.long.byte 0xB30 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER390_LOWER__8_8," newline hexmask.long.byte 0xB30 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER390_LOWER__0_8," line.long 0xB34 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER390_upper,Interrupt Routing Registers" line.long 0xB38 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER391_lower,Interrupt Routing Registers" bitfld.long 0xB38 31. "DISTRIBUTOR__37_GICD_IROUTER391_LOWER__31_1," "0,1" hexmask.long.byte 0xB38 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER391_LOWER__8_8," newline hexmask.long.byte 0xB38 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER391_LOWER__0_8," line.long 0xB3C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER391_upper,Interrupt Routing Registers" line.long 0xB40 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER392_lower,Interrupt Routing Registers" bitfld.long 0xB40 31. "DISTRIBUTOR__37_GICD_IROUTER392_LOWER__31_1," "0,1" hexmask.long.byte 0xB40 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER392_LOWER__8_8," newline hexmask.long.byte 0xB40 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER392_LOWER__0_8," line.long 0xB44 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER392_upper,Interrupt Routing Registers" line.long 0xB48 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER393_lower,Interrupt Routing Registers" bitfld.long 0xB48 31. "DISTRIBUTOR__37_GICD_IROUTER393_LOWER__31_1," "0,1" hexmask.long.byte 0xB48 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER393_LOWER__8_8," newline hexmask.long.byte 0xB48 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER393_LOWER__0_8," line.long 0xB4C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER393_upper,Interrupt Routing Registers" line.long 0xB50 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER394_lower,Interrupt Routing Registers" bitfld.long 0xB50 31. "DISTRIBUTOR__37_GICD_IROUTER394_LOWER__31_1," "0,1" hexmask.long.byte 0xB50 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER394_LOWER__8_8," newline hexmask.long.byte 0xB50 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER394_LOWER__0_8," line.long 0xB54 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER394_upper,Interrupt Routing Registers" line.long 0xB58 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER395_lower,Interrupt Routing Registers" bitfld.long 0xB58 31. "DISTRIBUTOR__37_GICD_IROUTER395_LOWER__31_1," "0,1" hexmask.long.byte 0xB58 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER395_LOWER__8_8," newline hexmask.long.byte 0xB58 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER395_LOWER__0_8," line.long 0xB5C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER395_upper,Interrupt Routing Registers" line.long 0xB60 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER396_lower,Interrupt Routing Registers" bitfld.long 0xB60 31. "DISTRIBUTOR__37_GICD_IROUTER396_LOWER__31_1," "0,1" hexmask.long.byte 0xB60 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER396_LOWER__8_8," newline hexmask.long.byte 0xB60 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER396_LOWER__0_8," line.long 0xB64 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER396_upper,Interrupt Routing Registers" line.long 0xB68 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER397_lower,Interrupt Routing Registers" bitfld.long 0xB68 31. "DISTRIBUTOR__37_GICD_IROUTER397_LOWER__31_1," "0,1" hexmask.long.byte 0xB68 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER397_LOWER__8_8," newline hexmask.long.byte 0xB68 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER397_LOWER__0_8," line.long 0xB6C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER397_upper,Interrupt Routing Registers" line.long 0xB70 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER398_lower,Interrupt Routing Registers" bitfld.long 0xB70 31. "DISTRIBUTOR__37_GICD_IROUTER398_LOWER__31_1," "0,1" hexmask.long.byte 0xB70 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER398_LOWER__8_8," newline hexmask.long.byte 0xB70 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER398_LOWER__0_8," line.long 0xB74 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER398_upper,Interrupt Routing Registers" line.long 0xB78 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER399_lower,Interrupt Routing Registers" bitfld.long 0xB78 31. "DISTRIBUTOR__37_GICD_IROUTER399_LOWER__31_1," "0,1" hexmask.long.byte 0xB78 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER399_LOWER__8_8," newline hexmask.long.byte 0xB78 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER399_LOWER__0_8," line.long 0xB7C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER399_upper,Interrupt Routing Registers" line.long 0xB80 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER400_lower,Interrupt Routing Registers" bitfld.long 0xB80 31. "DISTRIBUTOR__37_GICD_IROUTER400_LOWER__31_1," "0,1" hexmask.long.byte 0xB80 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER400_LOWER__8_8," newline hexmask.long.byte 0xB80 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER400_LOWER__0_8," line.long 0xB84 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER400_upper,Interrupt Routing Registers" line.long 0xB88 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER401_lower,Interrupt Routing Registers" bitfld.long 0xB88 31. "DISTRIBUTOR__37_GICD_IROUTER401_LOWER__31_1," "0,1" hexmask.long.byte 0xB88 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER401_LOWER__8_8," newline hexmask.long.byte 0xB88 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER401_LOWER__0_8," line.long 0xB8C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER401_upper,Interrupt Routing Registers" line.long 0xB90 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER402_lower,Interrupt Routing Registers" bitfld.long 0xB90 31. "DISTRIBUTOR__37_GICD_IROUTER402_LOWER__31_1," "0,1" hexmask.long.byte 0xB90 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER402_LOWER__8_8," newline hexmask.long.byte 0xB90 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER402_LOWER__0_8," line.long 0xB94 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER402_upper,Interrupt Routing Registers" line.long 0xB98 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER403_lower,Interrupt Routing Registers" bitfld.long 0xB98 31. "DISTRIBUTOR__37_GICD_IROUTER403_LOWER__31_1," "0,1" hexmask.long.byte 0xB98 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER403_LOWER__8_8," newline hexmask.long.byte 0xB98 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER403_LOWER__0_8," line.long 0xB9C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER403_upper,Interrupt Routing Registers" line.long 0xBA0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER404_lower,Interrupt Routing Registers" bitfld.long 0xBA0 31. "DISTRIBUTOR__37_GICD_IROUTER404_LOWER__31_1," "0,1" hexmask.long.byte 0xBA0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER404_LOWER__8_8," newline hexmask.long.byte 0xBA0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER404_LOWER__0_8," line.long 0xBA4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER404_upper,Interrupt Routing Registers" line.long 0xBA8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER405_lower,Interrupt Routing Registers" bitfld.long 0xBA8 31. "DISTRIBUTOR__37_GICD_IROUTER405_LOWER__31_1," "0,1" hexmask.long.byte 0xBA8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER405_LOWER__8_8," newline hexmask.long.byte 0xBA8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER405_LOWER__0_8," line.long 0xBAC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER405_upper,Interrupt Routing Registers" line.long 0xBB0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER406_lower,Interrupt Routing Registers" bitfld.long 0xBB0 31. "DISTRIBUTOR__37_GICD_IROUTER406_LOWER__31_1," "0,1" hexmask.long.byte 0xBB0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER406_LOWER__8_8," newline hexmask.long.byte 0xBB0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER406_LOWER__0_8," line.long 0xBB4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER406_upper,Interrupt Routing Registers" line.long 0xBB8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER407_lower,Interrupt Routing Registers" bitfld.long 0xBB8 31. "DISTRIBUTOR__37_GICD_IROUTER407_LOWER__31_1," "0,1" hexmask.long.byte 0xBB8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER407_LOWER__8_8," newline hexmask.long.byte 0xBB8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER407_LOWER__0_8," line.long 0xBBC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER407_upper,Interrupt Routing Registers" line.long 0xBC0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER408_lower,Interrupt Routing Registers" bitfld.long 0xBC0 31. "DISTRIBUTOR__37_GICD_IROUTER408_LOWER__31_1," "0,1" hexmask.long.byte 0xBC0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER408_LOWER__8_8," newline hexmask.long.byte 0xBC0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER408_LOWER__0_8," line.long 0xBC4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER408_upper,Interrupt Routing Registers" line.long 0xBC8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER409_lower,Interrupt Routing Registers" bitfld.long 0xBC8 31. "DISTRIBUTOR__37_GICD_IROUTER409_LOWER__31_1," "0,1" hexmask.long.byte 0xBC8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER409_LOWER__8_8," newline hexmask.long.byte 0xBC8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER409_LOWER__0_8," line.long 0xBCC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER409_upper,Interrupt Routing Registers" line.long 0xBD0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER410_lower,Interrupt Routing Registers" bitfld.long 0xBD0 31. "DISTRIBUTOR__37_GICD_IROUTER410_LOWER__31_1," "0,1" hexmask.long.byte 0xBD0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER410_LOWER__8_8," newline hexmask.long.byte 0xBD0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER410_LOWER__0_8," line.long 0xBD4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER410_upper,Interrupt Routing Registers" line.long 0xBD8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER411_lower,Interrupt Routing Registers" bitfld.long 0xBD8 31. "DISTRIBUTOR__37_GICD_IROUTER411_LOWER__31_1," "0,1" hexmask.long.byte 0xBD8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER411_LOWER__8_8," newline hexmask.long.byte 0xBD8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER411_LOWER__0_8," line.long 0xBDC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER411_upper,Interrupt Routing Registers" line.long 0xBE0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER412_lower,Interrupt Routing Registers" bitfld.long 0xBE0 31. "DISTRIBUTOR__37_GICD_IROUTER412_LOWER__31_1," "0,1" hexmask.long.byte 0xBE0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER412_LOWER__8_8," newline hexmask.long.byte 0xBE0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER412_LOWER__0_8," line.long 0xBE4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER412_upper,Interrupt Routing Registers" line.long 0xBE8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER413_lower,Interrupt Routing Registers" bitfld.long 0xBE8 31. "DISTRIBUTOR__37_GICD_IROUTER413_LOWER__31_1," "0,1" hexmask.long.byte 0xBE8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER413_LOWER__8_8," newline hexmask.long.byte 0xBE8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER413_LOWER__0_8," line.long 0xBEC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER413_upper,Interrupt Routing Registers" line.long 0xBF0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER414_lower,Interrupt Routing Registers" bitfld.long 0xBF0 31. "DISTRIBUTOR__37_GICD_IROUTER414_LOWER__31_1," "0,1" hexmask.long.byte 0xBF0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER414_LOWER__8_8," newline hexmask.long.byte 0xBF0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER414_LOWER__0_8," line.long 0xBF4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER414_upper,Interrupt Routing Registers" line.long 0xBF8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER415_lower,Interrupt Routing Registers" bitfld.long 0xBF8 31. "DISTRIBUTOR__37_GICD_IROUTER415_LOWER__31_1," "0,1" hexmask.long.byte 0xBF8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER415_LOWER__8_8," newline hexmask.long.byte 0xBF8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER415_LOWER__0_8," line.long 0xBFC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER415_upper,Interrupt Routing Registers" line.long 0xC00 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER416_lower,Interrupt Routing Registers" bitfld.long 0xC00 31. "DISTRIBUTOR__37_GICD_IROUTER416_LOWER__31_1," "0,1" hexmask.long.byte 0xC00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER416_LOWER__8_8," newline hexmask.long.byte 0xC00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER416_LOWER__0_8," line.long 0xC04 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER416_upper,Interrupt Routing Registers" line.long 0xC08 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER417_lower,Interrupt Routing Registers" bitfld.long 0xC08 31. "DISTRIBUTOR__37_GICD_IROUTER417_LOWER__31_1," "0,1" hexmask.long.byte 0xC08 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER417_LOWER__8_8," newline hexmask.long.byte 0xC08 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER417_LOWER__0_8," line.long 0xC0C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER417_upper,Interrupt Routing Registers" line.long 0xC10 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER418_lower,Interrupt Routing Registers" bitfld.long 0xC10 31. "DISTRIBUTOR__37_GICD_IROUTER418_LOWER__31_1," "0,1" hexmask.long.byte 0xC10 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER418_LOWER__8_8," newline hexmask.long.byte 0xC10 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER418_LOWER__0_8," line.long 0xC14 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER418_upper,Interrupt Routing Registers" line.long 0xC18 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER419_lower,Interrupt Routing Registers" bitfld.long 0xC18 31. "DISTRIBUTOR__37_GICD_IROUTER419_LOWER__31_1," "0,1" hexmask.long.byte 0xC18 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER419_LOWER__8_8," newline hexmask.long.byte 0xC18 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER419_LOWER__0_8," line.long 0xC1C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER419_upper,Interrupt Routing Registers" line.long 0xC20 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER420_lower,Interrupt Routing Registers" bitfld.long 0xC20 31. "DISTRIBUTOR__37_GICD_IROUTER420_LOWER__31_1," "0,1" hexmask.long.byte 0xC20 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER420_LOWER__8_8," newline hexmask.long.byte 0xC20 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER420_LOWER__0_8," line.long 0xC24 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER420_upper,Interrupt Routing Registers" line.long 0xC28 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER421_lower,Interrupt Routing Registers" bitfld.long 0xC28 31. "DISTRIBUTOR__37_GICD_IROUTER421_LOWER__31_1," "0,1" hexmask.long.byte 0xC28 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER421_LOWER__8_8," newline hexmask.long.byte 0xC28 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER421_LOWER__0_8," line.long 0xC2C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER421_upper,Interrupt Routing Registers" line.long 0xC30 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER422_lower,Interrupt Routing Registers" bitfld.long 0xC30 31. "DISTRIBUTOR__37_GICD_IROUTER422_LOWER__31_1," "0,1" hexmask.long.byte 0xC30 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER422_LOWER__8_8," newline hexmask.long.byte 0xC30 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER422_LOWER__0_8," line.long 0xC34 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER422_upper,Interrupt Routing Registers" line.long 0xC38 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER423_lower,Interrupt Routing Registers" bitfld.long 0xC38 31. "DISTRIBUTOR__37_GICD_IROUTER423_LOWER__31_1," "0,1" hexmask.long.byte 0xC38 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER423_LOWER__8_8," newline hexmask.long.byte 0xC38 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER423_LOWER__0_8," line.long 0xC3C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER423_upper,Interrupt Routing Registers" line.long 0xC40 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER424_lower,Interrupt Routing Registers" bitfld.long 0xC40 31. "DISTRIBUTOR__37_GICD_IROUTER424_LOWER__31_1," "0,1" hexmask.long.byte 0xC40 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER424_LOWER__8_8," newline hexmask.long.byte 0xC40 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER424_LOWER__0_8," line.long 0xC44 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER424_upper,Interrupt Routing Registers" line.long 0xC48 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER425_lower,Interrupt Routing Registers" bitfld.long 0xC48 31. "DISTRIBUTOR__37_GICD_IROUTER425_LOWER__31_1," "0,1" hexmask.long.byte 0xC48 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER425_LOWER__8_8," newline hexmask.long.byte 0xC48 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER425_LOWER__0_8," line.long 0xC4C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER425_upper,Interrupt Routing Registers" line.long 0xC50 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER426_lower,Interrupt Routing Registers" bitfld.long 0xC50 31. "DISTRIBUTOR__37_GICD_IROUTER426_LOWER__31_1," "0,1" hexmask.long.byte 0xC50 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER426_LOWER__8_8," newline hexmask.long.byte 0xC50 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER426_LOWER__0_8," line.long 0xC54 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER426_upper,Interrupt Routing Registers" line.long 0xC58 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER427_lower,Interrupt Routing Registers" bitfld.long 0xC58 31. "DISTRIBUTOR__37_GICD_IROUTER427_LOWER__31_1," "0,1" hexmask.long.byte 0xC58 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER427_LOWER__8_8," newline hexmask.long.byte 0xC58 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER427_LOWER__0_8," line.long 0xC5C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER427_upper,Interrupt Routing Registers" line.long 0xC60 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER428_lower,Interrupt Routing Registers" bitfld.long 0xC60 31. "DISTRIBUTOR__37_GICD_IROUTER428_LOWER__31_1," "0,1" hexmask.long.byte 0xC60 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER428_LOWER__8_8," newline hexmask.long.byte 0xC60 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER428_LOWER__0_8," line.long 0xC64 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER428_upper,Interrupt Routing Registers" line.long 0xC68 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER429_lower,Interrupt Routing Registers" bitfld.long 0xC68 31. "DISTRIBUTOR__37_GICD_IROUTER429_LOWER__31_1," "0,1" hexmask.long.byte 0xC68 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER429_LOWER__8_8," newline hexmask.long.byte 0xC68 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER429_LOWER__0_8," line.long 0xC6C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER429_upper,Interrupt Routing Registers" line.long 0xC70 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER430_lower,Interrupt Routing Registers" bitfld.long 0xC70 31. "DISTRIBUTOR__37_GICD_IROUTER430_LOWER__31_1," "0,1" hexmask.long.byte 0xC70 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER430_LOWER__8_8," newline hexmask.long.byte 0xC70 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER430_LOWER__0_8," line.long 0xC74 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER430_upper,Interrupt Routing Registers" line.long 0xC78 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER431_lower,Interrupt Routing Registers" bitfld.long 0xC78 31. "DISTRIBUTOR__37_GICD_IROUTER431_LOWER__31_1," "0,1" hexmask.long.byte 0xC78 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER431_LOWER__8_8," newline hexmask.long.byte 0xC78 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER431_LOWER__0_8," line.long 0xC7C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER431_upper,Interrupt Routing Registers" line.long 0xC80 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER432_lower,Interrupt Routing Registers" bitfld.long 0xC80 31. "DISTRIBUTOR__37_GICD_IROUTER432_LOWER__31_1," "0,1" hexmask.long.byte 0xC80 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER432_LOWER__8_8," newline hexmask.long.byte 0xC80 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER432_LOWER__0_8," line.long 0xC84 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER432_upper,Interrupt Routing Registers" line.long 0xC88 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER433_lower,Interrupt Routing Registers" bitfld.long 0xC88 31. "DISTRIBUTOR__37_GICD_IROUTER433_LOWER__31_1," "0,1" hexmask.long.byte 0xC88 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER433_LOWER__8_8," newline hexmask.long.byte 0xC88 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER433_LOWER__0_8," line.long 0xC8C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER433_upper,Interrupt Routing Registers" line.long 0xC90 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER434_lower,Interrupt Routing Registers" bitfld.long 0xC90 31. "DISTRIBUTOR__37_GICD_IROUTER434_LOWER__31_1," "0,1" hexmask.long.byte 0xC90 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER434_LOWER__8_8," newline hexmask.long.byte 0xC90 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER434_LOWER__0_8," line.long 0xC94 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER434_upper,Interrupt Routing Registers" line.long 0xC98 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER435_lower,Interrupt Routing Registers" bitfld.long 0xC98 31. "DISTRIBUTOR__37_GICD_IROUTER435_LOWER__31_1," "0,1" hexmask.long.byte 0xC98 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER435_LOWER__8_8," newline hexmask.long.byte 0xC98 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER435_LOWER__0_8," line.long 0xC9C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER435_upper,Interrupt Routing Registers" line.long 0xCA0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER436_lower,Interrupt Routing Registers" bitfld.long 0xCA0 31. "DISTRIBUTOR__37_GICD_IROUTER436_LOWER__31_1," "0,1" hexmask.long.byte 0xCA0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER436_LOWER__8_8," newline hexmask.long.byte 0xCA0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER436_LOWER__0_8," line.long 0xCA4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER436_upper,Interrupt Routing Registers" line.long 0xCA8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER437_lower,Interrupt Routing Registers" bitfld.long 0xCA8 31. "DISTRIBUTOR__37_GICD_IROUTER437_LOWER__31_1," "0,1" hexmask.long.byte 0xCA8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER437_LOWER__8_8," newline hexmask.long.byte 0xCA8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER437_LOWER__0_8," line.long 0xCAC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER437_upper,Interrupt Routing Registers" line.long 0xCB0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER438_lower,Interrupt Routing Registers" bitfld.long 0xCB0 31. "DISTRIBUTOR__37_GICD_IROUTER438_LOWER__31_1," "0,1" hexmask.long.byte 0xCB0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER438_LOWER__8_8," newline hexmask.long.byte 0xCB0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER438_LOWER__0_8," line.long 0xCB4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER438_upper,Interrupt Routing Registers" line.long 0xCB8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER439_lower,Interrupt Routing Registers" bitfld.long 0xCB8 31. "DISTRIBUTOR__37_GICD_IROUTER439_LOWER__31_1," "0,1" hexmask.long.byte 0xCB8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER439_LOWER__8_8," newline hexmask.long.byte 0xCB8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER439_LOWER__0_8," line.long 0xCBC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER439_upper,Interrupt Routing Registers" line.long 0xCC0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER440_lower,Interrupt Routing Registers" bitfld.long 0xCC0 31. "DISTRIBUTOR__37_GICD_IROUTER440_LOWER__31_1," "0,1" hexmask.long.byte 0xCC0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER440_LOWER__8_8," newline hexmask.long.byte 0xCC0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER440_LOWER__0_8," line.long 0xCC4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER440_upper,Interrupt Routing Registers" line.long 0xCC8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER441_lower,Interrupt Routing Registers" bitfld.long 0xCC8 31. "DISTRIBUTOR__37_GICD_IROUTER441_LOWER__31_1," "0,1" hexmask.long.byte 0xCC8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER441_LOWER__8_8," newline hexmask.long.byte 0xCC8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER441_LOWER__0_8," line.long 0xCCC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER441_upper,Interrupt Routing Registers" line.long 0xCD0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER442_lower,Interrupt Routing Registers" bitfld.long 0xCD0 31. "DISTRIBUTOR__37_GICD_IROUTER442_LOWER__31_1," "0,1" hexmask.long.byte 0xCD0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER442_LOWER__8_8," newline hexmask.long.byte 0xCD0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER442_LOWER__0_8," line.long 0xCD4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER442_upper,Interrupt Routing Registers" line.long 0xCD8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER443_lower,Interrupt Routing Registers" bitfld.long 0xCD8 31. "DISTRIBUTOR__37_GICD_IROUTER443_LOWER__31_1," "0,1" hexmask.long.byte 0xCD8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER443_LOWER__8_8," newline hexmask.long.byte 0xCD8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER443_LOWER__0_8," line.long 0xCDC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER443_upper,Interrupt Routing Registers" line.long 0xCE0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER444_lower,Interrupt Routing Registers" bitfld.long 0xCE0 31. "DISTRIBUTOR__37_GICD_IROUTER444_LOWER__31_1," "0,1" hexmask.long.byte 0xCE0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER444_LOWER__8_8," newline hexmask.long.byte 0xCE0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER444_LOWER__0_8," line.long 0xCE4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER444_upper,Interrupt Routing Registers" line.long 0xCE8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER445_lower,Interrupt Routing Registers" bitfld.long 0xCE8 31. "DISTRIBUTOR__37_GICD_IROUTER445_LOWER__31_1," "0,1" hexmask.long.byte 0xCE8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER445_LOWER__8_8," newline hexmask.long.byte 0xCE8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER445_LOWER__0_8," line.long 0xCEC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER445_upper,Interrupt Routing Registers" line.long 0xCF0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER446_lower,Interrupt Routing Registers" bitfld.long 0xCF0 31. "DISTRIBUTOR__37_GICD_IROUTER446_LOWER__31_1," "0,1" hexmask.long.byte 0xCF0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER446_LOWER__8_8," newline hexmask.long.byte 0xCF0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER446_LOWER__0_8," line.long 0xCF4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER446_upper,Interrupt Routing Registers" line.long 0xCF8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER447_lower,Interrupt Routing Registers" bitfld.long 0xCF8 31. "DISTRIBUTOR__37_GICD_IROUTER447_LOWER__31_1," "0,1" hexmask.long.byte 0xCF8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER447_LOWER__8_8," newline hexmask.long.byte 0xCF8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER447_LOWER__0_8," line.long 0xCFC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER447_upper,Interrupt Routing Registers" line.long 0xD00 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER448_lower,Interrupt Routing Registers" bitfld.long 0xD00 31. "DISTRIBUTOR__37_GICD_IROUTER448_LOWER__31_1," "0,1" hexmask.long.byte 0xD00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER448_LOWER__8_8," newline hexmask.long.byte 0xD00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER448_LOWER__0_8," line.long 0xD04 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER448_upper,Interrupt Routing Registers" line.long 0xD08 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER449_lower,Interrupt Routing Registers" bitfld.long 0xD08 31. "DISTRIBUTOR__37_GICD_IROUTER449_LOWER__31_1," "0,1" hexmask.long.byte 0xD08 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER449_LOWER__8_8," newline hexmask.long.byte 0xD08 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER449_LOWER__0_8," line.long 0xD0C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER449_upper,Interrupt Routing Registers" line.long 0xD10 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER450_lower,Interrupt Routing Registers" bitfld.long 0xD10 31. "DISTRIBUTOR__37_GICD_IROUTER450_LOWER__31_1," "0,1" hexmask.long.byte 0xD10 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER450_LOWER__8_8," newline hexmask.long.byte 0xD10 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER450_LOWER__0_8," line.long 0xD14 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER450_upper,Interrupt Routing Registers" line.long 0xD18 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER451_lower,Interrupt Routing Registers" bitfld.long 0xD18 31. "DISTRIBUTOR__37_GICD_IROUTER451_LOWER__31_1," "0,1" hexmask.long.byte 0xD18 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER451_LOWER__8_8," newline hexmask.long.byte 0xD18 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER451_LOWER__0_8," line.long 0xD1C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER451_upper,Interrupt Routing Registers" line.long 0xD20 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER452_lower,Interrupt Routing Registers" bitfld.long 0xD20 31. "DISTRIBUTOR__37_GICD_IROUTER452_LOWER__31_1," "0,1" hexmask.long.byte 0xD20 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER452_LOWER__8_8," newline hexmask.long.byte 0xD20 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER452_LOWER__0_8," line.long 0xD24 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER452_upper,Interrupt Routing Registers" line.long 0xD28 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER453_lower,Interrupt Routing Registers" bitfld.long 0xD28 31. "DISTRIBUTOR__37_GICD_IROUTER453_LOWER__31_1," "0,1" hexmask.long.byte 0xD28 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER453_LOWER__8_8," newline hexmask.long.byte 0xD28 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER453_LOWER__0_8," line.long 0xD2C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER453_upper,Interrupt Routing Registers" line.long 0xD30 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER454_lower,Interrupt Routing Registers" bitfld.long 0xD30 31. "DISTRIBUTOR__37_GICD_IROUTER454_LOWER__31_1," "0,1" hexmask.long.byte 0xD30 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER454_LOWER__8_8," newline hexmask.long.byte 0xD30 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER454_LOWER__0_8," line.long 0xD34 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER454_upper,Interrupt Routing Registers" line.long 0xD38 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER455_lower,Interrupt Routing Registers" bitfld.long 0xD38 31. "DISTRIBUTOR__37_GICD_IROUTER455_LOWER__31_1," "0,1" hexmask.long.byte 0xD38 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER455_LOWER__8_8," newline hexmask.long.byte 0xD38 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER455_LOWER__0_8," line.long 0xD3C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER455_upper,Interrupt Routing Registers" line.long 0xD40 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER456_lower,Interrupt Routing Registers" bitfld.long 0xD40 31. "DISTRIBUTOR__37_GICD_IROUTER456_LOWER__31_1," "0,1" hexmask.long.byte 0xD40 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER456_LOWER__8_8," newline hexmask.long.byte 0xD40 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER456_LOWER__0_8," line.long 0xD44 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER456_upper,Interrupt Routing Registers" line.long 0xD48 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER457_lower,Interrupt Routing Registers" bitfld.long 0xD48 31. "DISTRIBUTOR__37_GICD_IROUTER457_LOWER__31_1," "0,1" hexmask.long.byte 0xD48 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER457_LOWER__8_8," newline hexmask.long.byte 0xD48 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER457_LOWER__0_8," line.long 0xD4C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER457_upper,Interrupt Routing Registers" line.long 0xD50 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER458_lower,Interrupt Routing Registers" bitfld.long 0xD50 31. "DISTRIBUTOR__37_GICD_IROUTER458_LOWER__31_1," "0,1" hexmask.long.byte 0xD50 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER458_LOWER__8_8," newline hexmask.long.byte 0xD50 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER458_LOWER__0_8," line.long 0xD54 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER458_upper,Interrupt Routing Registers" line.long 0xD58 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER459_lower,Interrupt Routing Registers" bitfld.long 0xD58 31. "DISTRIBUTOR__37_GICD_IROUTER459_LOWER__31_1," "0,1" hexmask.long.byte 0xD58 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER459_LOWER__8_8," newline hexmask.long.byte 0xD58 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER459_LOWER__0_8," line.long 0xD5C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER459_upper,Interrupt Routing Registers" line.long 0xD60 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER460_lower,Interrupt Routing Registers" bitfld.long 0xD60 31. "DISTRIBUTOR__37_GICD_IROUTER460_LOWER__31_1," "0,1" hexmask.long.byte 0xD60 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER460_LOWER__8_8," newline hexmask.long.byte 0xD60 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER460_LOWER__0_8," line.long 0xD64 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER460_upper,Interrupt Routing Registers" line.long 0xD68 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER461_lower,Interrupt Routing Registers" bitfld.long 0xD68 31. "DISTRIBUTOR__37_GICD_IROUTER461_LOWER__31_1," "0,1" hexmask.long.byte 0xD68 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER461_LOWER__8_8," newline hexmask.long.byte 0xD68 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER461_LOWER__0_8," line.long 0xD6C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER461_upper,Interrupt Routing Registers" line.long 0xD70 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER462_lower,Interrupt Routing Registers" bitfld.long 0xD70 31. "DISTRIBUTOR__37_GICD_IROUTER462_LOWER__31_1," "0,1" hexmask.long.byte 0xD70 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER462_LOWER__8_8," newline hexmask.long.byte 0xD70 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER462_LOWER__0_8," line.long 0xD74 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER462_upper,Interrupt Routing Registers" line.long 0xD78 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER463_lower,Interrupt Routing Registers" bitfld.long 0xD78 31. "DISTRIBUTOR__37_GICD_IROUTER463_LOWER__31_1," "0,1" hexmask.long.byte 0xD78 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER463_LOWER__8_8," newline hexmask.long.byte 0xD78 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER463_LOWER__0_8," line.long 0xD7C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER463_upper,Interrupt Routing Registers" line.long 0xD80 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER464_lower,Interrupt Routing Registers" bitfld.long 0xD80 31. "DISTRIBUTOR__37_GICD_IROUTER464_LOWER__31_1," "0,1" hexmask.long.byte 0xD80 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER464_LOWER__8_8," newline hexmask.long.byte 0xD80 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER464_LOWER__0_8," line.long 0xD84 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER464_upper,Interrupt Routing Registers" line.long 0xD88 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER465_lower,Interrupt Routing Registers" bitfld.long 0xD88 31. "DISTRIBUTOR__37_GICD_IROUTER465_LOWER__31_1," "0,1" hexmask.long.byte 0xD88 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER465_LOWER__8_8," newline hexmask.long.byte 0xD88 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER465_LOWER__0_8," line.long 0xD8C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER465_upper,Interrupt Routing Registers" line.long 0xD90 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER466_lower,Interrupt Routing Registers" bitfld.long 0xD90 31. "DISTRIBUTOR__37_GICD_IROUTER466_LOWER__31_1," "0,1" hexmask.long.byte 0xD90 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER466_LOWER__8_8," newline hexmask.long.byte 0xD90 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER466_LOWER__0_8," line.long 0xD94 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER466_upper,Interrupt Routing Registers" line.long 0xD98 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER467_lower,Interrupt Routing Registers" bitfld.long 0xD98 31. "DISTRIBUTOR__37_GICD_IROUTER467_LOWER__31_1," "0,1" hexmask.long.byte 0xD98 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER467_LOWER__8_8," newline hexmask.long.byte 0xD98 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER467_LOWER__0_8," line.long 0xD9C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER467_upper,Interrupt Routing Registers" line.long 0xDA0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER468_lower,Interrupt Routing Registers" bitfld.long 0xDA0 31. "DISTRIBUTOR__37_GICD_IROUTER468_LOWER__31_1," "0,1" hexmask.long.byte 0xDA0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER468_LOWER__8_8," newline hexmask.long.byte 0xDA0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER468_LOWER__0_8," line.long 0xDA4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER468_upper,Interrupt Routing Registers" line.long 0xDA8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER469_lower,Interrupt Routing Registers" bitfld.long 0xDA8 31. "DISTRIBUTOR__37_GICD_IROUTER469_LOWER__31_1," "0,1" hexmask.long.byte 0xDA8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER469_LOWER__8_8," newline hexmask.long.byte 0xDA8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER469_LOWER__0_8," line.long 0xDAC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER469_upper,Interrupt Routing Registers" line.long 0xDB0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER470_lower,Interrupt Routing Registers" bitfld.long 0xDB0 31. "DISTRIBUTOR__37_GICD_IROUTER470_LOWER__31_1," "0,1" hexmask.long.byte 0xDB0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER470_LOWER__8_8," newline hexmask.long.byte 0xDB0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER470_LOWER__0_8," line.long 0xDB4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER470_upper,Interrupt Routing Registers" line.long 0xDB8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER471_lower,Interrupt Routing Registers" bitfld.long 0xDB8 31. "DISTRIBUTOR__37_GICD_IROUTER471_LOWER__31_1," "0,1" hexmask.long.byte 0xDB8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER471_LOWER__8_8," newline hexmask.long.byte 0xDB8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER471_LOWER__0_8," line.long 0xDBC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER471_upper,Interrupt Routing Registers" line.long 0xDC0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER472_lower,Interrupt Routing Registers" bitfld.long 0xDC0 31. "DISTRIBUTOR__37_GICD_IROUTER472_LOWER__31_1," "0,1" hexmask.long.byte 0xDC0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER472_LOWER__8_8," newline hexmask.long.byte 0xDC0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER472_LOWER__0_8," line.long 0xDC4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER472_upper,Interrupt Routing Registers" line.long 0xDC8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER473_lower,Interrupt Routing Registers" bitfld.long 0xDC8 31. "DISTRIBUTOR__37_GICD_IROUTER473_LOWER__31_1," "0,1" hexmask.long.byte 0xDC8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER473_LOWER__8_8," newline hexmask.long.byte 0xDC8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER473_LOWER__0_8," line.long 0xDCC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER473_upper,Interrupt Routing Registers" line.long 0xDD0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER474_lower,Interrupt Routing Registers" bitfld.long 0xDD0 31. "DISTRIBUTOR__37_GICD_IROUTER474_LOWER__31_1," "0,1" hexmask.long.byte 0xDD0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER474_LOWER__8_8," newline hexmask.long.byte 0xDD0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER474_LOWER__0_8," line.long 0xDD4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER474_upper,Interrupt Routing Registers" line.long 0xDD8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER475_lower,Interrupt Routing Registers" bitfld.long 0xDD8 31. "DISTRIBUTOR__37_GICD_IROUTER475_LOWER__31_1," "0,1" hexmask.long.byte 0xDD8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER475_LOWER__8_8," newline hexmask.long.byte 0xDD8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER475_LOWER__0_8," line.long 0xDDC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER475_upper,Interrupt Routing Registers" line.long 0xDE0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER476_lower,Interrupt Routing Registers" bitfld.long 0xDE0 31. "DISTRIBUTOR__37_GICD_IROUTER476_LOWER__31_1," "0,1" hexmask.long.byte 0xDE0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER476_LOWER__8_8," newline hexmask.long.byte 0xDE0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER476_LOWER__0_8," line.long 0xDE4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER476_upper,Interrupt Routing Registers" line.long 0xDE8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER477_lower,Interrupt Routing Registers" bitfld.long 0xDE8 31. "DISTRIBUTOR__37_GICD_IROUTER477_LOWER__31_1," "0,1" hexmask.long.byte 0xDE8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER477_LOWER__8_8," newline hexmask.long.byte 0xDE8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER477_LOWER__0_8," line.long 0xDEC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER477_upper,Interrupt Routing Registers" line.long 0xDF0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER478_lower,Interrupt Routing Registers" bitfld.long 0xDF0 31. "DISTRIBUTOR__37_GICD_IROUTER478_LOWER__31_1," "0,1" hexmask.long.byte 0xDF0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER478_LOWER__8_8," newline hexmask.long.byte 0xDF0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER478_LOWER__0_8," line.long 0xDF4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER478_upper,Interrupt Routing Registers" line.long 0xDF8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER479_lower,Interrupt Routing Registers" bitfld.long 0xDF8 31. "DISTRIBUTOR__37_GICD_IROUTER479_LOWER__31_1," "0,1" hexmask.long.byte 0xDF8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER479_LOWER__8_8," newline hexmask.long.byte 0xDF8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER479_LOWER__0_8," line.long 0xDFC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER479_upper,Interrupt Routing Registers" line.long 0xE00 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER480_lower,Interrupt Routing Registers" bitfld.long 0xE00 31. "DISTRIBUTOR__37_GICD_IROUTER480_LOWER__31_1," "0,1" hexmask.long.byte 0xE00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER480_LOWER__8_8," newline hexmask.long.byte 0xE00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER480_LOWER__0_8," line.long 0xE04 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER480_upper,Interrupt Routing Registers" line.long 0xE08 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER481_lower,Interrupt Routing Registers" bitfld.long 0xE08 31. "DISTRIBUTOR__37_GICD_IROUTER481_LOWER__31_1," "0,1" hexmask.long.byte 0xE08 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER481_LOWER__8_8," newline hexmask.long.byte 0xE08 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER481_LOWER__0_8," line.long 0xE0C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER481_upper,Interrupt Routing Registers" line.long 0xE10 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER482_lower,Interrupt Routing Registers" bitfld.long 0xE10 31. "DISTRIBUTOR__37_GICD_IROUTER482_LOWER__31_1," "0,1" hexmask.long.byte 0xE10 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER482_LOWER__8_8," newline hexmask.long.byte 0xE10 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER482_LOWER__0_8," line.long 0xE14 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER482_upper,Interrupt Routing Registers" line.long 0xE18 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER483_lower,Interrupt Routing Registers" bitfld.long 0xE18 31. "DISTRIBUTOR__37_GICD_IROUTER483_LOWER__31_1," "0,1" hexmask.long.byte 0xE18 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER483_LOWER__8_8," newline hexmask.long.byte 0xE18 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER483_LOWER__0_8," line.long 0xE1C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER483_upper,Interrupt Routing Registers" line.long 0xE20 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER484_lower,Interrupt Routing Registers" bitfld.long 0xE20 31. "DISTRIBUTOR__37_GICD_IROUTER484_LOWER__31_1," "0,1" hexmask.long.byte 0xE20 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER484_LOWER__8_8," newline hexmask.long.byte 0xE20 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER484_LOWER__0_8," line.long 0xE24 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER484_upper,Interrupt Routing Registers" line.long 0xE28 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER485_lower,Interrupt Routing Registers" bitfld.long 0xE28 31. "DISTRIBUTOR__37_GICD_IROUTER485_LOWER__31_1," "0,1" hexmask.long.byte 0xE28 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER485_LOWER__8_8," newline hexmask.long.byte 0xE28 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER485_LOWER__0_8," line.long 0xE2C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER485_upper,Interrupt Routing Registers" line.long 0xE30 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER486_lower,Interrupt Routing Registers" bitfld.long 0xE30 31. "DISTRIBUTOR__37_GICD_IROUTER486_LOWER__31_1," "0,1" hexmask.long.byte 0xE30 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER486_LOWER__8_8," newline hexmask.long.byte 0xE30 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER486_LOWER__0_8," line.long 0xE34 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER486_upper,Interrupt Routing Registers" line.long 0xE38 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER487_lower,Interrupt Routing Registers" bitfld.long 0xE38 31. "DISTRIBUTOR__37_GICD_IROUTER487_LOWER__31_1," "0,1" hexmask.long.byte 0xE38 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER487_LOWER__8_8," newline hexmask.long.byte 0xE38 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER487_LOWER__0_8," line.long 0xE3C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER487_upper,Interrupt Routing Registers" line.long 0xE40 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER488_lower,Interrupt Routing Registers" bitfld.long 0xE40 31. "DISTRIBUTOR__37_GICD_IROUTER488_LOWER__31_1," "0,1" hexmask.long.byte 0xE40 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER488_LOWER__8_8," newline hexmask.long.byte 0xE40 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER488_LOWER__0_8," line.long 0xE44 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER488_upper,Interrupt Routing Registers" line.long 0xE48 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER489_lower,Interrupt Routing Registers" bitfld.long 0xE48 31. "DISTRIBUTOR__37_GICD_IROUTER489_LOWER__31_1," "0,1" hexmask.long.byte 0xE48 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER489_LOWER__8_8," newline hexmask.long.byte 0xE48 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER489_LOWER__0_8," line.long 0xE4C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER489_upper,Interrupt Routing Registers" line.long 0xE50 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER490_lower,Interrupt Routing Registers" bitfld.long 0xE50 31. "DISTRIBUTOR__37_GICD_IROUTER490_LOWER__31_1," "0,1" hexmask.long.byte 0xE50 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER490_LOWER__8_8," newline hexmask.long.byte 0xE50 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER490_LOWER__0_8," line.long 0xE54 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER490_upper,Interrupt Routing Registers" line.long 0xE58 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER491_lower,Interrupt Routing Registers" bitfld.long 0xE58 31. "DISTRIBUTOR__37_GICD_IROUTER491_LOWER__31_1," "0,1" hexmask.long.byte 0xE58 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER491_LOWER__8_8," newline hexmask.long.byte 0xE58 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER491_LOWER__0_8," line.long 0xE5C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER491_upper,Interrupt Routing Registers" line.long 0xE60 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER492_lower,Interrupt Routing Registers" bitfld.long 0xE60 31. "DISTRIBUTOR__37_GICD_IROUTER492_LOWER__31_1," "0,1" hexmask.long.byte 0xE60 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER492_LOWER__8_8," newline hexmask.long.byte 0xE60 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER492_LOWER__0_8," line.long 0xE64 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER492_upper,Interrupt Routing Registers" line.long 0xE68 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER493_lower,Interrupt Routing Registers" bitfld.long 0xE68 31. "DISTRIBUTOR__37_GICD_IROUTER493_LOWER__31_1," "0,1" hexmask.long.byte 0xE68 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER493_LOWER__8_8," newline hexmask.long.byte 0xE68 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER493_LOWER__0_8," line.long 0xE6C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER493_upper,Interrupt Routing Registers" line.long 0xE70 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER494_lower,Interrupt Routing Registers" bitfld.long 0xE70 31. "DISTRIBUTOR__37_GICD_IROUTER494_LOWER__31_1," "0,1" hexmask.long.byte 0xE70 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER494_LOWER__8_8," newline hexmask.long.byte 0xE70 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER494_LOWER__0_8," line.long 0xE74 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER494_upper,Interrupt Routing Registers" line.long 0xE78 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER495_lower,Interrupt Routing Registers" bitfld.long 0xE78 31. "DISTRIBUTOR__37_GICD_IROUTER495_LOWER__31_1," "0,1" hexmask.long.byte 0xE78 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER495_LOWER__8_8," newline hexmask.long.byte 0xE78 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER495_LOWER__0_8," line.long 0xE7C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER495_upper,Interrupt Routing Registers" line.long 0xE80 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER496_lower,Interrupt Routing Registers" bitfld.long 0xE80 31. "DISTRIBUTOR__37_GICD_IROUTER496_LOWER__31_1," "0,1" hexmask.long.byte 0xE80 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER496_LOWER__8_8," newline hexmask.long.byte 0xE80 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER496_LOWER__0_8," line.long 0xE84 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER496_upper,Interrupt Routing Registers" line.long 0xE88 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER497_lower,Interrupt Routing Registers" bitfld.long 0xE88 31. "DISTRIBUTOR__37_GICD_IROUTER497_LOWER__31_1," "0,1" hexmask.long.byte 0xE88 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER497_LOWER__8_8," newline hexmask.long.byte 0xE88 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER497_LOWER__0_8," line.long 0xE8C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER497_upper,Interrupt Routing Registers" line.long 0xE90 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER498_lower,Interrupt Routing Registers" bitfld.long 0xE90 31. "DISTRIBUTOR__37_GICD_IROUTER498_LOWER__31_1," "0,1" hexmask.long.byte 0xE90 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER498_LOWER__8_8," newline hexmask.long.byte 0xE90 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER498_LOWER__0_8," line.long 0xE94 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER498_upper,Interrupt Routing Registers" line.long 0xE98 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER499_lower,Interrupt Routing Registers" bitfld.long 0xE98 31. "DISTRIBUTOR__37_GICD_IROUTER499_LOWER__31_1," "0,1" hexmask.long.byte 0xE98 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER499_LOWER__8_8," newline hexmask.long.byte 0xE98 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER499_LOWER__0_8," line.long 0xE9C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER499_upper,Interrupt Routing Registers" line.long 0xEA0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER500_lower,Interrupt Routing Registers" bitfld.long 0xEA0 31. "DISTRIBUTOR__37_GICD_IROUTER500_LOWER__31_1," "0,1" hexmask.long.byte 0xEA0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER500_LOWER__8_8," newline hexmask.long.byte 0xEA0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER500_LOWER__0_8," line.long 0xEA4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER500_upper,Interrupt Routing Registers" line.long 0xEA8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER501_lower,Interrupt Routing Registers" bitfld.long 0xEA8 31. "DISTRIBUTOR__37_GICD_IROUTER501_LOWER__31_1," "0,1" hexmask.long.byte 0xEA8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER501_LOWER__8_8," newline hexmask.long.byte 0xEA8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER501_LOWER__0_8," line.long 0xEAC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER501_upper,Interrupt Routing Registers" line.long 0xEB0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER502_lower,Interrupt Routing Registers" bitfld.long 0xEB0 31. "DISTRIBUTOR__37_GICD_IROUTER502_LOWER__31_1," "0,1" hexmask.long.byte 0xEB0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER502_LOWER__8_8," newline hexmask.long.byte 0xEB0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER502_LOWER__0_8," line.long 0xEB4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER502_upper,Interrupt Routing Registers" line.long 0xEB8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER503_lower,Interrupt Routing Registers" bitfld.long 0xEB8 31. "DISTRIBUTOR__37_GICD_IROUTER503_LOWER__31_1," "0,1" hexmask.long.byte 0xEB8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER503_LOWER__8_8," newline hexmask.long.byte 0xEB8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER503_LOWER__0_8," line.long 0xEBC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER503_upper,Interrupt Routing Registers" line.long 0xEC0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER504_lower,Interrupt Routing Registers" bitfld.long 0xEC0 31. "DISTRIBUTOR__37_GICD_IROUTER504_LOWER__31_1," "0,1" hexmask.long.byte 0xEC0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER504_LOWER__8_8," newline hexmask.long.byte 0xEC0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER504_LOWER__0_8," line.long 0xEC4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER504_upper,Interrupt Routing Registers" line.long 0xEC8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER505_lower,Interrupt Routing Registers" bitfld.long 0xEC8 31. "DISTRIBUTOR__37_GICD_IROUTER505_LOWER__31_1," "0,1" hexmask.long.byte 0xEC8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER505_LOWER__8_8," newline hexmask.long.byte 0xEC8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER505_LOWER__0_8," line.long 0xECC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER505_upper,Interrupt Routing Registers" line.long 0xED0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER506_lower,Interrupt Routing Registers" bitfld.long 0xED0 31. "DISTRIBUTOR__37_GICD_IROUTER506_LOWER__31_1," "0,1" hexmask.long.byte 0xED0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER506_LOWER__8_8," newline hexmask.long.byte 0xED0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER506_LOWER__0_8," line.long 0xED4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER506_upper,Interrupt Routing Registers" line.long 0xED8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER507_lower,Interrupt Routing Registers" bitfld.long 0xED8 31. "DISTRIBUTOR__37_GICD_IROUTER507_LOWER__31_1," "0,1" hexmask.long.byte 0xED8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER507_LOWER__8_8," newline hexmask.long.byte 0xED8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER507_LOWER__0_8," line.long 0xEDC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER507_upper,Interrupt Routing Registers" line.long 0xEE0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER508_lower,Interrupt Routing Registers" bitfld.long 0xEE0 31. "DISTRIBUTOR__37_GICD_IROUTER508_LOWER__31_1," "0,1" hexmask.long.byte 0xEE0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER508_LOWER__8_8," newline hexmask.long.byte 0xEE0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER508_LOWER__0_8," line.long 0xEE4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER508_upper,Interrupt Routing Registers" line.long 0xEE8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER509_lower,Interrupt Routing Registers" bitfld.long 0xEE8 31. "DISTRIBUTOR__37_GICD_IROUTER509_LOWER__31_1," "0,1" hexmask.long.byte 0xEE8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER509_LOWER__8_8," newline hexmask.long.byte 0xEE8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER509_LOWER__0_8," line.long 0xEEC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER509_upper,Interrupt Routing Registers" line.long 0xEF0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER510_lower,Interrupt Routing Registers" bitfld.long 0xEF0 31. "DISTRIBUTOR__37_GICD_IROUTER510_LOWER__31_1," "0,1" hexmask.long.byte 0xEF0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER510_LOWER__8_8," newline hexmask.long.byte 0xEF0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER510_LOWER__0_8," line.long 0xEF4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER510_upper,Interrupt Routing Registers" line.long 0xEF8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER511_lower,Interrupt Routing Registers" bitfld.long 0xEF8 31. "DISTRIBUTOR__37_GICD_IROUTER511_LOWER__31_1," "0,1" hexmask.long.byte 0xEF8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER511_LOWER__8_8," newline hexmask.long.byte 0xEF8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER511_LOWER__0_8," line.long 0xEFC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER511_upper,Interrupt Routing Registers" line.long 0xF00 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER512_lower,Interrupt Routing Registers" bitfld.long 0xF00 31. "DISTRIBUTOR__37_GICD_IROUTER512_LOWER__31_1," "0,1" hexmask.long.byte 0xF00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER512_LOWER__8_8," newline hexmask.long.byte 0xF00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER512_LOWER__0_8," line.long 0xF04 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER512_upper,Interrupt Routing Registers" line.long 0xF08 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER513_lower,Interrupt Routing Registers" bitfld.long 0xF08 31. "DISTRIBUTOR__37_GICD_IROUTER513_LOWER__31_1," "0,1" hexmask.long.byte 0xF08 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER513_LOWER__8_8," newline hexmask.long.byte 0xF08 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER513_LOWER__0_8," line.long 0xF0C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER513_upper,Interrupt Routing Registers" line.long 0xF10 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER514_lower,Interrupt Routing Registers" bitfld.long 0xF10 31. "DISTRIBUTOR__37_GICD_IROUTER514_LOWER__31_1," "0,1" hexmask.long.byte 0xF10 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER514_LOWER__8_8," newline hexmask.long.byte 0xF10 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER514_LOWER__0_8," line.long 0xF14 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER514_upper,Interrupt Routing Registers" line.long 0xF18 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER515_lower,Interrupt Routing Registers" bitfld.long 0xF18 31. "DISTRIBUTOR__37_GICD_IROUTER515_LOWER__31_1," "0,1" hexmask.long.byte 0xF18 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER515_LOWER__8_8," newline hexmask.long.byte 0xF18 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER515_LOWER__0_8," line.long 0xF1C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER515_upper,Interrupt Routing Registers" line.long 0xF20 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER516_lower,Interrupt Routing Registers" bitfld.long 0xF20 31. "DISTRIBUTOR__37_GICD_IROUTER516_LOWER__31_1," "0,1" hexmask.long.byte 0xF20 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER516_LOWER__8_8," newline hexmask.long.byte 0xF20 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER516_LOWER__0_8," line.long 0xF24 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER516_upper,Interrupt Routing Registers" line.long 0xF28 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER517_lower,Interrupt Routing Registers" bitfld.long 0xF28 31. "DISTRIBUTOR__37_GICD_IROUTER517_LOWER__31_1," "0,1" hexmask.long.byte 0xF28 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER517_LOWER__8_8," newline hexmask.long.byte 0xF28 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER517_LOWER__0_8," line.long 0xF2C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER517_upper,Interrupt Routing Registers" line.long 0xF30 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER518_lower,Interrupt Routing Registers" bitfld.long 0xF30 31. "DISTRIBUTOR__37_GICD_IROUTER518_LOWER__31_1," "0,1" hexmask.long.byte 0xF30 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER518_LOWER__8_8," newline hexmask.long.byte 0xF30 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER518_LOWER__0_8," line.long 0xF34 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER518_upper,Interrupt Routing Registers" line.long 0xF38 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER519_lower,Interrupt Routing Registers" bitfld.long 0xF38 31. "DISTRIBUTOR__37_GICD_IROUTER519_LOWER__31_1," "0,1" hexmask.long.byte 0xF38 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER519_LOWER__8_8," newline hexmask.long.byte 0xF38 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER519_LOWER__0_8," line.long 0xF3C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER519_upper,Interrupt Routing Registers" line.long 0xF40 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER520_lower,Interrupt Routing Registers" bitfld.long 0xF40 31. "DISTRIBUTOR__37_GICD_IROUTER520_LOWER__31_1," "0,1" hexmask.long.byte 0xF40 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER520_LOWER__8_8," newline hexmask.long.byte 0xF40 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER520_LOWER__0_8," line.long 0xF44 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER520_upper,Interrupt Routing Registers" line.long 0xF48 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER521_lower,Interrupt Routing Registers" bitfld.long 0xF48 31. "DISTRIBUTOR__37_GICD_IROUTER521_LOWER__31_1," "0,1" hexmask.long.byte 0xF48 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER521_LOWER__8_8," newline hexmask.long.byte 0xF48 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER521_LOWER__0_8," line.long 0xF4C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER521_upper,Interrupt Routing Registers" line.long 0xF50 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER522_lower,Interrupt Routing Registers" bitfld.long 0xF50 31. "DISTRIBUTOR__37_GICD_IROUTER522_LOWER__31_1," "0,1" hexmask.long.byte 0xF50 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER522_LOWER__8_8," newline hexmask.long.byte 0xF50 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER522_LOWER__0_8," line.long 0xF54 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER522_upper,Interrupt Routing Registers" line.long 0xF58 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER523_lower,Interrupt Routing Registers" bitfld.long 0xF58 31. "DISTRIBUTOR__37_GICD_IROUTER523_LOWER__31_1," "0,1" hexmask.long.byte 0xF58 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER523_LOWER__8_8," newline hexmask.long.byte 0xF58 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER523_LOWER__0_8," line.long 0xF5C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER523_upper,Interrupt Routing Registers" line.long 0xF60 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER524_lower,Interrupt Routing Registers" bitfld.long 0xF60 31. "DISTRIBUTOR__37_GICD_IROUTER524_LOWER__31_1," "0,1" hexmask.long.byte 0xF60 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER524_LOWER__8_8," newline hexmask.long.byte 0xF60 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER524_LOWER__0_8," line.long 0xF64 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER524_upper,Interrupt Routing Registers" line.long 0xF68 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER525_lower,Interrupt Routing Registers" bitfld.long 0xF68 31. "DISTRIBUTOR__37_GICD_IROUTER525_LOWER__31_1," "0,1" hexmask.long.byte 0xF68 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER525_LOWER__8_8," newline hexmask.long.byte 0xF68 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER525_LOWER__0_8," line.long 0xF6C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER525_upper,Interrupt Routing Registers" line.long 0xF70 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER526_lower,Interrupt Routing Registers" bitfld.long 0xF70 31. "DISTRIBUTOR__37_GICD_IROUTER526_LOWER__31_1," "0,1" hexmask.long.byte 0xF70 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER526_LOWER__8_8," newline hexmask.long.byte 0xF70 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER526_LOWER__0_8," line.long 0xF74 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER526_upper,Interrupt Routing Registers" line.long 0xF78 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER527_lower,Interrupt Routing Registers" bitfld.long 0xF78 31. "DISTRIBUTOR__37_GICD_IROUTER527_LOWER__31_1," "0,1" hexmask.long.byte 0xF78 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER527_LOWER__8_8," newline hexmask.long.byte 0xF78 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER527_LOWER__0_8," line.long 0xF7C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER527_upper,Interrupt Routing Registers" line.long 0xF80 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER528_lower,Interrupt Routing Registers" bitfld.long 0xF80 31. "DISTRIBUTOR__37_GICD_IROUTER528_LOWER__31_1," "0,1" hexmask.long.byte 0xF80 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER528_LOWER__8_8," newline hexmask.long.byte 0xF80 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER528_LOWER__0_8," line.long 0xF84 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER528_upper,Interrupt Routing Registers" line.long 0xF88 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER529_lower,Interrupt Routing Registers" bitfld.long 0xF88 31. "DISTRIBUTOR__37_GICD_IROUTER529_LOWER__31_1," "0,1" hexmask.long.byte 0xF88 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER529_LOWER__8_8," newline hexmask.long.byte 0xF88 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER529_LOWER__0_8," line.long 0xF8C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER529_upper,Interrupt Routing Registers" line.long 0xF90 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER530_lower,Interrupt Routing Registers" bitfld.long 0xF90 31. "DISTRIBUTOR__37_GICD_IROUTER530_LOWER__31_1," "0,1" hexmask.long.byte 0xF90 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER530_LOWER__8_8," newline hexmask.long.byte 0xF90 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER530_LOWER__0_8," line.long 0xF94 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER530_upper,Interrupt Routing Registers" line.long 0xF98 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER531_lower,Interrupt Routing Registers" bitfld.long 0xF98 31. "DISTRIBUTOR__37_GICD_IROUTER531_LOWER__31_1," "0,1" hexmask.long.byte 0xF98 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER531_LOWER__8_8," newline hexmask.long.byte 0xF98 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER531_LOWER__0_8," line.long 0xF9C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER531_upper,Interrupt Routing Registers" line.long 0xFA0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER532_lower,Interrupt Routing Registers" bitfld.long 0xFA0 31. "DISTRIBUTOR__37_GICD_IROUTER532_LOWER__31_1," "0,1" hexmask.long.byte 0xFA0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER532_LOWER__8_8," newline hexmask.long.byte 0xFA0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER532_LOWER__0_8," line.long 0xFA4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER532_upper,Interrupt Routing Registers" line.long 0xFA8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER533_lower,Interrupt Routing Registers" bitfld.long 0xFA8 31. "DISTRIBUTOR__37_GICD_IROUTER533_LOWER__31_1," "0,1" hexmask.long.byte 0xFA8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER533_LOWER__8_8," newline hexmask.long.byte 0xFA8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER533_LOWER__0_8," line.long 0xFAC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER533_upper,Interrupt Routing Registers" line.long 0xFB0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER534_lower,Interrupt Routing Registers" bitfld.long 0xFB0 31. "DISTRIBUTOR__37_GICD_IROUTER534_LOWER__31_1," "0,1" hexmask.long.byte 0xFB0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER534_LOWER__8_8," newline hexmask.long.byte 0xFB0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER534_LOWER__0_8," line.long 0xFB4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER534_upper,Interrupt Routing Registers" line.long 0xFB8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER535_lower,Interrupt Routing Registers" bitfld.long 0xFB8 31. "DISTRIBUTOR__37_GICD_IROUTER535_LOWER__31_1," "0,1" hexmask.long.byte 0xFB8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER535_LOWER__8_8," newline hexmask.long.byte 0xFB8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER535_LOWER__0_8," line.long 0xFBC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER535_upper,Interrupt Routing Registers" line.long 0xFC0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER536_lower,Interrupt Routing Registers" bitfld.long 0xFC0 31. "DISTRIBUTOR__37_GICD_IROUTER536_LOWER__31_1," "0,1" hexmask.long.byte 0xFC0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER536_LOWER__8_8," newline hexmask.long.byte 0xFC0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER536_LOWER__0_8," line.long 0xFC4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER536_upper,Interrupt Routing Registers" line.long 0xFC8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER537_lower,Interrupt Routing Registers" bitfld.long 0xFC8 31. "DISTRIBUTOR__37_GICD_IROUTER537_LOWER__31_1," "0,1" hexmask.long.byte 0xFC8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER537_LOWER__8_8," newline hexmask.long.byte 0xFC8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER537_LOWER__0_8," line.long 0xFCC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER537_upper,Interrupt Routing Registers" line.long 0xFD0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER538_lower,Interrupt Routing Registers" bitfld.long 0xFD0 31. "DISTRIBUTOR__37_GICD_IROUTER538_LOWER__31_1," "0,1" hexmask.long.byte 0xFD0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER538_LOWER__8_8," newline hexmask.long.byte 0xFD0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER538_LOWER__0_8," line.long 0xFD4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER538_upper,Interrupt Routing Registers" line.long 0xFD8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER539_lower,Interrupt Routing Registers" bitfld.long 0xFD8 31. "DISTRIBUTOR__37_GICD_IROUTER539_LOWER__31_1," "0,1" hexmask.long.byte 0xFD8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER539_LOWER__8_8," newline hexmask.long.byte 0xFD8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER539_LOWER__0_8," line.long 0xFDC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER539_upper,Interrupt Routing Registers" line.long 0xFE0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER540_lower,Interrupt Routing Registers" bitfld.long 0xFE0 31. "DISTRIBUTOR__37_GICD_IROUTER540_LOWER__31_1," "0,1" hexmask.long.byte 0xFE0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER540_LOWER__8_8," newline hexmask.long.byte 0xFE0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER540_LOWER__0_8," line.long 0xFE4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER540_upper,Interrupt Routing Registers" line.long 0xFE8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER541_lower,Interrupt Routing Registers" bitfld.long 0xFE8 31. "DISTRIBUTOR__37_GICD_IROUTER541_LOWER__31_1," "0,1" hexmask.long.byte 0xFE8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER541_LOWER__8_8," newline hexmask.long.byte 0xFE8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER541_LOWER__0_8," line.long 0xFEC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER541_upper,Interrupt Routing Registers" line.long 0xFF0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER542_lower,Interrupt Routing Registers" bitfld.long 0xFF0 31. "DISTRIBUTOR__37_GICD_IROUTER542_LOWER__31_1," "0,1" hexmask.long.byte 0xFF0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER542_LOWER__8_8," newline hexmask.long.byte 0xFF0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER542_LOWER__0_8," line.long 0xFF4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER542_upper,Interrupt Routing Registers" line.long 0xFF8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER543_lower,Interrupt Routing Registers" bitfld.long 0xFF8 31. "DISTRIBUTOR__37_GICD_IROUTER543_LOWER__31_1," "0,1" hexmask.long.byte 0xFF8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER543_LOWER__8_8," newline hexmask.long.byte 0xFF8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER543_LOWER__0_8," line.long 0xFFC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER543_upper,Interrupt Routing Registers" rgroup.long 0x7100++0xDFF line.long 0x0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER544_lower,Interrupt Routing Registers" bitfld.long 0x0 31. "DISTRIBUTOR__37_GICD_IROUTER544_LOWER__31_1," "0,1" hexmask.long.byte 0x0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER544_LOWER__8_8," newline hexmask.long.byte 0x0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER544_LOWER__0_8," line.long 0x4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER544_upper,Interrupt Routing Registers" line.long 0x8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER545_lower,Interrupt Routing Registers" bitfld.long 0x8 31. "DISTRIBUTOR__37_GICD_IROUTER545_LOWER__31_1," "0,1" hexmask.long.byte 0x8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER545_LOWER__8_8," newline hexmask.long.byte 0x8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER545_LOWER__0_8," line.long 0xC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER545_upper,Interrupt Routing Registers" line.long 0x10 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER546_lower,Interrupt Routing Registers" bitfld.long 0x10 31. "DISTRIBUTOR__37_GICD_IROUTER546_LOWER__31_1," "0,1" hexmask.long.byte 0x10 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER546_LOWER__8_8," newline hexmask.long.byte 0x10 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER546_LOWER__0_8," line.long 0x14 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER546_upper,Interrupt Routing Registers" line.long 0x18 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER547_lower,Interrupt Routing Registers" bitfld.long 0x18 31. "DISTRIBUTOR__37_GICD_IROUTER547_LOWER__31_1," "0,1" hexmask.long.byte 0x18 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER547_LOWER__8_8," newline hexmask.long.byte 0x18 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER547_LOWER__0_8," line.long 0x1C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER547_upper,Interrupt Routing Registers" line.long 0x20 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER548_lower,Interrupt Routing Registers" bitfld.long 0x20 31. "DISTRIBUTOR__37_GICD_IROUTER548_LOWER__31_1," "0,1" hexmask.long.byte 0x20 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER548_LOWER__8_8," newline hexmask.long.byte 0x20 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER548_LOWER__0_8," line.long 0x24 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER548_upper,Interrupt Routing Registers" line.long 0x28 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER549_lower,Interrupt Routing Registers" bitfld.long 0x28 31. "DISTRIBUTOR__37_GICD_IROUTER549_LOWER__31_1," "0,1" hexmask.long.byte 0x28 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER549_LOWER__8_8," newline hexmask.long.byte 0x28 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER549_LOWER__0_8," line.long 0x2C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER549_upper,Interrupt Routing Registers" line.long 0x30 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER550_lower,Interrupt Routing Registers" bitfld.long 0x30 31. "DISTRIBUTOR__37_GICD_IROUTER550_LOWER__31_1," "0,1" hexmask.long.byte 0x30 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER550_LOWER__8_8," newline hexmask.long.byte 0x30 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER550_LOWER__0_8," line.long 0x34 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER550_upper,Interrupt Routing Registers" line.long 0x38 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER551_lower,Interrupt Routing Registers" bitfld.long 0x38 31. "DISTRIBUTOR__37_GICD_IROUTER551_LOWER__31_1," "0,1" hexmask.long.byte 0x38 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER551_LOWER__8_8," newline hexmask.long.byte 0x38 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER551_LOWER__0_8," line.long 0x3C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER551_upper,Interrupt Routing Registers" line.long 0x40 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER552_lower,Interrupt Routing Registers" bitfld.long 0x40 31. "DISTRIBUTOR__37_GICD_IROUTER552_LOWER__31_1," "0,1" hexmask.long.byte 0x40 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER552_LOWER__8_8," newline hexmask.long.byte 0x40 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER552_LOWER__0_8," line.long 0x44 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER552_upper,Interrupt Routing Registers" line.long 0x48 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER553_lower,Interrupt Routing Registers" bitfld.long 0x48 31. "DISTRIBUTOR__37_GICD_IROUTER553_LOWER__31_1," "0,1" hexmask.long.byte 0x48 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER553_LOWER__8_8," newline hexmask.long.byte 0x48 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER553_LOWER__0_8," line.long 0x4C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER553_upper,Interrupt Routing Registers" line.long 0x50 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER554_lower,Interrupt Routing Registers" bitfld.long 0x50 31. "DISTRIBUTOR__37_GICD_IROUTER554_LOWER__31_1," "0,1" hexmask.long.byte 0x50 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER554_LOWER__8_8," newline hexmask.long.byte 0x50 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER554_LOWER__0_8," line.long 0x54 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER554_upper,Interrupt Routing Registers" line.long 0x58 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER555_lower,Interrupt Routing Registers" bitfld.long 0x58 31. "DISTRIBUTOR__37_GICD_IROUTER555_LOWER__31_1," "0,1" hexmask.long.byte 0x58 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER555_LOWER__8_8," newline hexmask.long.byte 0x58 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER555_LOWER__0_8," line.long 0x5C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER555_upper,Interrupt Routing Registers" line.long 0x60 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER556_lower,Interrupt Routing Registers" bitfld.long 0x60 31. "DISTRIBUTOR__37_GICD_IROUTER556_LOWER__31_1," "0,1" hexmask.long.byte 0x60 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER556_LOWER__8_8," newline hexmask.long.byte 0x60 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER556_LOWER__0_8," line.long 0x64 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER556_upper,Interrupt Routing Registers" line.long 0x68 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER557_lower,Interrupt Routing Registers" bitfld.long 0x68 31. "DISTRIBUTOR__37_GICD_IROUTER557_LOWER__31_1," "0,1" hexmask.long.byte 0x68 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER557_LOWER__8_8," newline hexmask.long.byte 0x68 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER557_LOWER__0_8," line.long 0x6C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER557_upper,Interrupt Routing Registers" line.long 0x70 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER558_lower,Interrupt Routing Registers" bitfld.long 0x70 31. "DISTRIBUTOR__37_GICD_IROUTER558_LOWER__31_1," "0,1" hexmask.long.byte 0x70 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER558_LOWER__8_8," newline hexmask.long.byte 0x70 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER558_LOWER__0_8," line.long 0x74 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER558_upper,Interrupt Routing Registers" line.long 0x78 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER559_lower,Interrupt Routing Registers" bitfld.long 0x78 31. "DISTRIBUTOR__37_GICD_IROUTER559_LOWER__31_1," "0,1" hexmask.long.byte 0x78 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER559_LOWER__8_8," newline hexmask.long.byte 0x78 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER559_LOWER__0_8," line.long 0x7C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER559_upper,Interrupt Routing Registers" line.long 0x80 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER560_lower,Interrupt Routing Registers" bitfld.long 0x80 31. "DISTRIBUTOR__37_GICD_IROUTER560_LOWER__31_1," "0,1" hexmask.long.byte 0x80 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER560_LOWER__8_8," newline hexmask.long.byte 0x80 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER560_LOWER__0_8," line.long 0x84 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER560_upper,Interrupt Routing Registers" line.long 0x88 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER561_lower,Interrupt Routing Registers" bitfld.long 0x88 31. "DISTRIBUTOR__37_GICD_IROUTER561_LOWER__31_1," "0,1" hexmask.long.byte 0x88 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER561_LOWER__8_8," newline hexmask.long.byte 0x88 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER561_LOWER__0_8," line.long 0x8C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER561_upper,Interrupt Routing Registers" line.long 0x90 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER562_lower,Interrupt Routing Registers" bitfld.long 0x90 31. "DISTRIBUTOR__37_GICD_IROUTER562_LOWER__31_1," "0,1" hexmask.long.byte 0x90 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER562_LOWER__8_8," newline hexmask.long.byte 0x90 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER562_LOWER__0_8," line.long 0x94 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER562_upper,Interrupt Routing Registers" line.long 0x98 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER563_lower,Interrupt Routing Registers" bitfld.long 0x98 31. "DISTRIBUTOR__37_GICD_IROUTER563_LOWER__31_1," "0,1" hexmask.long.byte 0x98 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER563_LOWER__8_8," newline hexmask.long.byte 0x98 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER563_LOWER__0_8," line.long 0x9C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER563_upper,Interrupt Routing Registers" line.long 0xA0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER564_lower,Interrupt Routing Registers" bitfld.long 0xA0 31. "DISTRIBUTOR__37_GICD_IROUTER564_LOWER__31_1," "0,1" hexmask.long.byte 0xA0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER564_LOWER__8_8," newline hexmask.long.byte 0xA0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER564_LOWER__0_8," line.long 0xA4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER564_upper,Interrupt Routing Registers" line.long 0xA8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER565_lower,Interrupt Routing Registers" bitfld.long 0xA8 31. "DISTRIBUTOR__37_GICD_IROUTER565_LOWER__31_1," "0,1" hexmask.long.byte 0xA8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER565_LOWER__8_8," newline hexmask.long.byte 0xA8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER565_LOWER__0_8," line.long 0xAC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER565_upper,Interrupt Routing Registers" line.long 0xB0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER566_lower,Interrupt Routing Registers" bitfld.long 0xB0 31. "DISTRIBUTOR__37_GICD_IROUTER566_LOWER__31_1," "0,1" hexmask.long.byte 0xB0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER566_LOWER__8_8," newline hexmask.long.byte 0xB0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER566_LOWER__0_8," line.long 0xB4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER566_upper,Interrupt Routing Registers" line.long 0xB8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER567_lower,Interrupt Routing Registers" bitfld.long 0xB8 31. "DISTRIBUTOR__37_GICD_IROUTER567_LOWER__31_1," "0,1" hexmask.long.byte 0xB8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER567_LOWER__8_8," newline hexmask.long.byte 0xB8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER567_LOWER__0_8," line.long 0xBC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER567_upper,Interrupt Routing Registers" line.long 0xC0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER568_lower,Interrupt Routing Registers" bitfld.long 0xC0 31. "DISTRIBUTOR__37_GICD_IROUTER568_LOWER__31_1," "0,1" hexmask.long.byte 0xC0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER568_LOWER__8_8," newline hexmask.long.byte 0xC0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER568_LOWER__0_8," line.long 0xC4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER568_upper,Interrupt Routing Registers" line.long 0xC8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER569_lower,Interrupt Routing Registers" bitfld.long 0xC8 31. "DISTRIBUTOR__37_GICD_IROUTER569_LOWER__31_1," "0,1" hexmask.long.byte 0xC8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER569_LOWER__8_8," newline hexmask.long.byte 0xC8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER569_LOWER__0_8," line.long 0xCC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER569_upper,Interrupt Routing Registers" line.long 0xD0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER570_lower,Interrupt Routing Registers" bitfld.long 0xD0 31. "DISTRIBUTOR__37_GICD_IROUTER570_LOWER__31_1," "0,1" hexmask.long.byte 0xD0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER570_LOWER__8_8," newline hexmask.long.byte 0xD0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER570_LOWER__0_8," line.long 0xD4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER570_upper,Interrupt Routing Registers" line.long 0xD8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER571_lower,Interrupt Routing Registers" bitfld.long 0xD8 31. "DISTRIBUTOR__37_GICD_IROUTER571_LOWER__31_1," "0,1" hexmask.long.byte 0xD8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER571_LOWER__8_8," newline hexmask.long.byte 0xD8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER571_LOWER__0_8," line.long 0xDC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER571_upper,Interrupt Routing Registers" line.long 0xE0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER572_lower,Interrupt Routing Registers" bitfld.long 0xE0 31. "DISTRIBUTOR__37_GICD_IROUTER572_LOWER__31_1," "0,1" hexmask.long.byte 0xE0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER572_LOWER__8_8," newline hexmask.long.byte 0xE0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER572_LOWER__0_8," line.long 0xE4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER572_upper,Interrupt Routing Registers" line.long 0xE8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER573_lower,Interrupt Routing Registers" bitfld.long 0xE8 31. "DISTRIBUTOR__37_GICD_IROUTER573_LOWER__31_1," "0,1" hexmask.long.byte 0xE8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER573_LOWER__8_8," newline hexmask.long.byte 0xE8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER573_LOWER__0_8," line.long 0xEC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER573_upper,Interrupt Routing Registers" line.long 0xF0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER574_lower,Interrupt Routing Registers" bitfld.long 0xF0 31. "DISTRIBUTOR__37_GICD_IROUTER574_LOWER__31_1," "0,1" hexmask.long.byte 0xF0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER574_LOWER__8_8," newline hexmask.long.byte 0xF0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER574_LOWER__0_8," line.long 0xF4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER574_upper,Interrupt Routing Registers" line.long 0xF8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER575_lower,Interrupt Routing Registers" bitfld.long 0xF8 31. "DISTRIBUTOR__37_GICD_IROUTER575_LOWER__31_1," "0,1" hexmask.long.byte 0xF8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER575_LOWER__8_8," newline hexmask.long.byte 0xF8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER575_LOWER__0_8," line.long 0xFC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER575_upper,Interrupt Routing Registers" line.long 0x100 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER576_lower,Interrupt Routing Registers" bitfld.long 0x100 31. "DISTRIBUTOR__37_GICD_IROUTER576_LOWER__31_1," "0,1" hexmask.long.byte 0x100 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER576_LOWER__8_8," newline hexmask.long.byte 0x100 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER576_LOWER__0_8," line.long 0x104 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER576_upper,Interrupt Routing Registers" line.long 0x108 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER577_lower,Interrupt Routing Registers" bitfld.long 0x108 31. "DISTRIBUTOR__37_GICD_IROUTER577_LOWER__31_1," "0,1" hexmask.long.byte 0x108 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER577_LOWER__8_8," newline hexmask.long.byte 0x108 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER577_LOWER__0_8," line.long 0x10C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER577_upper,Interrupt Routing Registers" line.long 0x110 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER578_lower,Interrupt Routing Registers" bitfld.long 0x110 31. "DISTRIBUTOR__37_GICD_IROUTER578_LOWER__31_1," "0,1" hexmask.long.byte 0x110 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER578_LOWER__8_8," newline hexmask.long.byte 0x110 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER578_LOWER__0_8," line.long 0x114 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER578_upper,Interrupt Routing Registers" line.long 0x118 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER579_lower,Interrupt Routing Registers" bitfld.long 0x118 31. "DISTRIBUTOR__37_GICD_IROUTER579_LOWER__31_1," "0,1" hexmask.long.byte 0x118 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER579_LOWER__8_8," newline hexmask.long.byte 0x118 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER579_LOWER__0_8," line.long 0x11C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER579_upper,Interrupt Routing Registers" line.long 0x120 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER580_lower,Interrupt Routing Registers" bitfld.long 0x120 31. "DISTRIBUTOR__37_GICD_IROUTER580_LOWER__31_1," "0,1" hexmask.long.byte 0x120 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER580_LOWER__8_8," newline hexmask.long.byte 0x120 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER580_LOWER__0_8," line.long 0x124 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER580_upper,Interrupt Routing Registers" line.long 0x128 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER581_lower,Interrupt Routing Registers" bitfld.long 0x128 31. "DISTRIBUTOR__37_GICD_IROUTER581_LOWER__31_1," "0,1" hexmask.long.byte 0x128 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER581_LOWER__8_8," newline hexmask.long.byte 0x128 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER581_LOWER__0_8," line.long 0x12C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER581_upper,Interrupt Routing Registers" line.long 0x130 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER582_lower,Interrupt Routing Registers" bitfld.long 0x130 31. "DISTRIBUTOR__37_GICD_IROUTER582_LOWER__31_1," "0,1" hexmask.long.byte 0x130 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER582_LOWER__8_8," newline hexmask.long.byte 0x130 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER582_LOWER__0_8," line.long 0x134 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER582_upper,Interrupt Routing Registers" line.long 0x138 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER583_lower,Interrupt Routing Registers" bitfld.long 0x138 31. "DISTRIBUTOR__37_GICD_IROUTER583_LOWER__31_1," "0,1" hexmask.long.byte 0x138 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER583_LOWER__8_8," newline hexmask.long.byte 0x138 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER583_LOWER__0_8," line.long 0x13C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER583_upper,Interrupt Routing Registers" line.long 0x140 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER584_lower,Interrupt Routing Registers" bitfld.long 0x140 31. "DISTRIBUTOR__37_GICD_IROUTER584_LOWER__31_1," "0,1" hexmask.long.byte 0x140 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER584_LOWER__8_8," newline hexmask.long.byte 0x140 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER584_LOWER__0_8," line.long 0x144 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER584_upper,Interrupt Routing Registers" line.long 0x148 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER585_lower,Interrupt Routing Registers" bitfld.long 0x148 31. "DISTRIBUTOR__37_GICD_IROUTER585_LOWER__31_1," "0,1" hexmask.long.byte 0x148 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER585_LOWER__8_8," newline hexmask.long.byte 0x148 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER585_LOWER__0_8," line.long 0x14C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER585_upper,Interrupt Routing Registers" line.long 0x150 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER586_lower,Interrupt Routing Registers" bitfld.long 0x150 31. "DISTRIBUTOR__37_GICD_IROUTER586_LOWER__31_1," "0,1" hexmask.long.byte 0x150 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER586_LOWER__8_8," newline hexmask.long.byte 0x150 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER586_LOWER__0_8," line.long 0x154 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER586_upper,Interrupt Routing Registers" line.long 0x158 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER587_lower,Interrupt Routing Registers" bitfld.long 0x158 31. "DISTRIBUTOR__37_GICD_IROUTER587_LOWER__31_1," "0,1" hexmask.long.byte 0x158 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER587_LOWER__8_8," newline hexmask.long.byte 0x158 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER587_LOWER__0_8," line.long 0x15C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER587_upper,Interrupt Routing Registers" line.long 0x160 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER588_lower,Interrupt Routing Registers" bitfld.long 0x160 31. "DISTRIBUTOR__37_GICD_IROUTER588_LOWER__31_1," "0,1" hexmask.long.byte 0x160 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER588_LOWER__8_8," newline hexmask.long.byte 0x160 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER588_LOWER__0_8," line.long 0x164 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER588_upper,Interrupt Routing Registers" line.long 0x168 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER589_lower,Interrupt Routing Registers" bitfld.long 0x168 31. "DISTRIBUTOR__37_GICD_IROUTER589_LOWER__31_1," "0,1" hexmask.long.byte 0x168 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER589_LOWER__8_8," newline hexmask.long.byte 0x168 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER589_LOWER__0_8," line.long 0x16C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER589_upper,Interrupt Routing Registers" line.long 0x170 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER590_lower,Interrupt Routing Registers" bitfld.long 0x170 31. "DISTRIBUTOR__37_GICD_IROUTER590_LOWER__31_1," "0,1" hexmask.long.byte 0x170 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER590_LOWER__8_8," newline hexmask.long.byte 0x170 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER590_LOWER__0_8," line.long 0x174 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER590_upper,Interrupt Routing Registers" line.long 0x178 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER591_lower,Interrupt Routing Registers" bitfld.long 0x178 31. "DISTRIBUTOR__37_GICD_IROUTER591_LOWER__31_1," "0,1" hexmask.long.byte 0x178 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER591_LOWER__8_8," newline hexmask.long.byte 0x178 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER591_LOWER__0_8," line.long 0x17C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER591_upper,Interrupt Routing Registers" line.long 0x180 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER592_lower,Interrupt Routing Registers" bitfld.long 0x180 31. "DISTRIBUTOR__37_GICD_IROUTER592_LOWER__31_1," "0,1" hexmask.long.byte 0x180 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER592_LOWER__8_8," newline hexmask.long.byte 0x180 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER592_LOWER__0_8," line.long 0x184 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER592_upper,Interrupt Routing Registers" line.long 0x188 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER593_lower,Interrupt Routing Registers" bitfld.long 0x188 31. "DISTRIBUTOR__37_GICD_IROUTER593_LOWER__31_1," "0,1" hexmask.long.byte 0x188 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER593_LOWER__8_8," newline hexmask.long.byte 0x188 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER593_LOWER__0_8," line.long 0x18C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER593_upper,Interrupt Routing Registers" line.long 0x190 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER594_lower,Interrupt Routing Registers" bitfld.long 0x190 31. "DISTRIBUTOR__37_GICD_IROUTER594_LOWER__31_1," "0,1" hexmask.long.byte 0x190 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER594_LOWER__8_8," newline hexmask.long.byte 0x190 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER594_LOWER__0_8," line.long 0x194 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER594_upper,Interrupt Routing Registers" line.long 0x198 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER595_lower,Interrupt Routing Registers" bitfld.long 0x198 31. "DISTRIBUTOR__37_GICD_IROUTER595_LOWER__31_1," "0,1" hexmask.long.byte 0x198 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER595_LOWER__8_8," newline hexmask.long.byte 0x198 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER595_LOWER__0_8," line.long 0x19C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER595_upper,Interrupt Routing Registers" line.long 0x1A0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER596_lower,Interrupt Routing Registers" bitfld.long 0x1A0 31. "DISTRIBUTOR__37_GICD_IROUTER596_LOWER__31_1," "0,1" hexmask.long.byte 0x1A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER596_LOWER__8_8," newline hexmask.long.byte 0x1A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER596_LOWER__0_8," line.long 0x1A4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER596_upper,Interrupt Routing Registers" line.long 0x1A8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER597_lower,Interrupt Routing Registers" bitfld.long 0x1A8 31. "DISTRIBUTOR__37_GICD_IROUTER597_LOWER__31_1," "0,1" hexmask.long.byte 0x1A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER597_LOWER__8_8," newline hexmask.long.byte 0x1A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER597_LOWER__0_8," line.long 0x1AC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER597_upper,Interrupt Routing Registers" line.long 0x1B0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER598_lower,Interrupt Routing Registers" bitfld.long 0x1B0 31. "DISTRIBUTOR__37_GICD_IROUTER598_LOWER__31_1," "0,1" hexmask.long.byte 0x1B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER598_LOWER__8_8," newline hexmask.long.byte 0x1B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER598_LOWER__0_8," line.long 0x1B4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER598_upper,Interrupt Routing Registers" line.long 0x1B8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER599_lower,Interrupt Routing Registers" bitfld.long 0x1B8 31. "DISTRIBUTOR__37_GICD_IROUTER599_LOWER__31_1," "0,1" hexmask.long.byte 0x1B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER599_LOWER__8_8," newline hexmask.long.byte 0x1B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER599_LOWER__0_8," line.long 0x1BC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER599_upper,Interrupt Routing Registers" line.long 0x1C0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER600_lower,Interrupt Routing Registers" bitfld.long 0x1C0 31. "DISTRIBUTOR__37_GICD_IROUTER600_LOWER__31_1," "0,1" hexmask.long.byte 0x1C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER600_LOWER__8_8," newline hexmask.long.byte 0x1C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER600_LOWER__0_8," line.long 0x1C4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER600_upper,Interrupt Routing Registers" line.long 0x1C8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER601_lower,Interrupt Routing Registers" bitfld.long 0x1C8 31. "DISTRIBUTOR__37_GICD_IROUTER601_LOWER__31_1," "0,1" hexmask.long.byte 0x1C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER601_LOWER__8_8," newline hexmask.long.byte 0x1C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER601_LOWER__0_8," line.long 0x1CC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER601_upper,Interrupt Routing Registers" line.long 0x1D0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER602_lower,Interrupt Routing Registers" bitfld.long 0x1D0 31. "DISTRIBUTOR__37_GICD_IROUTER602_LOWER__31_1," "0,1" hexmask.long.byte 0x1D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER602_LOWER__8_8," newline hexmask.long.byte 0x1D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER602_LOWER__0_8," line.long 0x1D4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER602_upper,Interrupt Routing Registers" line.long 0x1D8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER603_lower,Interrupt Routing Registers" bitfld.long 0x1D8 31. "DISTRIBUTOR__37_GICD_IROUTER603_LOWER__31_1," "0,1" hexmask.long.byte 0x1D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER603_LOWER__8_8," newline hexmask.long.byte 0x1D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER603_LOWER__0_8," line.long 0x1DC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER603_upper,Interrupt Routing Registers" line.long 0x1E0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER604_lower,Interrupt Routing Registers" bitfld.long 0x1E0 31. "DISTRIBUTOR__37_GICD_IROUTER604_LOWER__31_1," "0,1" hexmask.long.byte 0x1E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER604_LOWER__8_8," newline hexmask.long.byte 0x1E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER604_LOWER__0_8," line.long 0x1E4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER604_upper,Interrupt Routing Registers" line.long 0x1E8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER605_lower,Interrupt Routing Registers" bitfld.long 0x1E8 31. "DISTRIBUTOR__37_GICD_IROUTER605_LOWER__31_1," "0,1" hexmask.long.byte 0x1E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER605_LOWER__8_8," newline hexmask.long.byte 0x1E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER605_LOWER__0_8," line.long 0x1EC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER605_upper,Interrupt Routing Registers" line.long 0x1F0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER606_lower,Interrupt Routing Registers" bitfld.long 0x1F0 31. "DISTRIBUTOR__37_GICD_IROUTER606_LOWER__31_1," "0,1" hexmask.long.byte 0x1F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER606_LOWER__8_8," newline hexmask.long.byte 0x1F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER606_LOWER__0_8," line.long 0x1F4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER606_upper,Interrupt Routing Registers" line.long 0x1F8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER607_lower,Interrupt Routing Registers" bitfld.long 0x1F8 31. "DISTRIBUTOR__37_GICD_IROUTER607_LOWER__31_1," "0,1" hexmask.long.byte 0x1F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER607_LOWER__8_8," newline hexmask.long.byte 0x1F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER607_LOWER__0_8," line.long 0x1FC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER607_upper,Interrupt Routing Registers" line.long 0x200 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER608_lower,Interrupt Routing Registers" bitfld.long 0x200 31. "DISTRIBUTOR__37_GICD_IROUTER608_LOWER__31_1," "0,1" hexmask.long.byte 0x200 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER608_LOWER__8_8," newline hexmask.long.byte 0x200 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER608_LOWER__0_8," line.long 0x204 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER608_upper,Interrupt Routing Registers" line.long 0x208 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER609_lower,Interrupt Routing Registers" bitfld.long 0x208 31. "DISTRIBUTOR__37_GICD_IROUTER609_LOWER__31_1," "0,1" hexmask.long.byte 0x208 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER609_LOWER__8_8," newline hexmask.long.byte 0x208 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER609_LOWER__0_8," line.long 0x20C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER609_upper,Interrupt Routing Registers" line.long 0x210 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER610_lower,Interrupt Routing Registers" bitfld.long 0x210 31. "DISTRIBUTOR__37_GICD_IROUTER610_LOWER__31_1," "0,1" hexmask.long.byte 0x210 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER610_LOWER__8_8," newline hexmask.long.byte 0x210 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER610_LOWER__0_8," line.long 0x214 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER610_upper,Interrupt Routing Registers" line.long 0x218 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER611_lower,Interrupt Routing Registers" bitfld.long 0x218 31. "DISTRIBUTOR__37_GICD_IROUTER611_LOWER__31_1," "0,1" hexmask.long.byte 0x218 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER611_LOWER__8_8," newline hexmask.long.byte 0x218 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER611_LOWER__0_8," line.long 0x21C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER611_upper,Interrupt Routing Registers" line.long 0x220 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER612_lower,Interrupt Routing Registers" bitfld.long 0x220 31. "DISTRIBUTOR__37_GICD_IROUTER612_LOWER__31_1," "0,1" hexmask.long.byte 0x220 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER612_LOWER__8_8," newline hexmask.long.byte 0x220 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER612_LOWER__0_8," line.long 0x224 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER612_upper,Interrupt Routing Registers" line.long 0x228 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER613_lower,Interrupt Routing Registers" bitfld.long 0x228 31. "DISTRIBUTOR__37_GICD_IROUTER613_LOWER__31_1," "0,1" hexmask.long.byte 0x228 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER613_LOWER__8_8," newline hexmask.long.byte 0x228 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER613_LOWER__0_8," line.long 0x22C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER613_upper,Interrupt Routing Registers" line.long 0x230 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER614_lower,Interrupt Routing Registers" bitfld.long 0x230 31. "DISTRIBUTOR__37_GICD_IROUTER614_LOWER__31_1," "0,1" hexmask.long.byte 0x230 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER614_LOWER__8_8," newline hexmask.long.byte 0x230 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER614_LOWER__0_8," line.long 0x234 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER614_upper,Interrupt Routing Registers" line.long 0x238 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER615_lower,Interrupt Routing Registers" bitfld.long 0x238 31. "DISTRIBUTOR__37_GICD_IROUTER615_LOWER__31_1," "0,1" hexmask.long.byte 0x238 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER615_LOWER__8_8," newline hexmask.long.byte 0x238 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER615_LOWER__0_8," line.long 0x23C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER615_upper,Interrupt Routing Registers" line.long 0x240 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER616_lower,Interrupt Routing Registers" bitfld.long 0x240 31. "DISTRIBUTOR__37_GICD_IROUTER616_LOWER__31_1," "0,1" hexmask.long.byte 0x240 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER616_LOWER__8_8," newline hexmask.long.byte 0x240 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER616_LOWER__0_8," line.long 0x244 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER616_upper,Interrupt Routing Registers" line.long 0x248 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER617_lower,Interrupt Routing Registers" bitfld.long 0x248 31. "DISTRIBUTOR__37_GICD_IROUTER617_LOWER__31_1," "0,1" hexmask.long.byte 0x248 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER617_LOWER__8_8," newline hexmask.long.byte 0x248 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER617_LOWER__0_8," line.long 0x24C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER617_upper,Interrupt Routing Registers" line.long 0x250 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER618_lower,Interrupt Routing Registers" bitfld.long 0x250 31. "DISTRIBUTOR__37_GICD_IROUTER618_LOWER__31_1," "0,1" hexmask.long.byte 0x250 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER618_LOWER__8_8," newline hexmask.long.byte 0x250 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER618_LOWER__0_8," line.long 0x254 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER618_upper,Interrupt Routing Registers" line.long 0x258 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER619_lower,Interrupt Routing Registers" bitfld.long 0x258 31. "DISTRIBUTOR__37_GICD_IROUTER619_LOWER__31_1," "0,1" hexmask.long.byte 0x258 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER619_LOWER__8_8," newline hexmask.long.byte 0x258 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER619_LOWER__0_8," line.long 0x25C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER619_upper,Interrupt Routing Registers" line.long 0x260 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER620_lower,Interrupt Routing Registers" bitfld.long 0x260 31. "DISTRIBUTOR__37_GICD_IROUTER620_LOWER__31_1," "0,1" hexmask.long.byte 0x260 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER620_LOWER__8_8," newline hexmask.long.byte 0x260 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER620_LOWER__0_8," line.long 0x264 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER620_upper,Interrupt Routing Registers" line.long 0x268 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER621_lower,Interrupt Routing Registers" bitfld.long 0x268 31. "DISTRIBUTOR__37_GICD_IROUTER621_LOWER__31_1," "0,1" hexmask.long.byte 0x268 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER621_LOWER__8_8," newline hexmask.long.byte 0x268 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER621_LOWER__0_8," line.long 0x26C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER621_upper,Interrupt Routing Registers" line.long 0x270 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER622_lower,Interrupt Routing Registers" bitfld.long 0x270 31. "DISTRIBUTOR__37_GICD_IROUTER622_LOWER__31_1," "0,1" hexmask.long.byte 0x270 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER622_LOWER__8_8," newline hexmask.long.byte 0x270 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER622_LOWER__0_8," line.long 0x274 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER622_upper,Interrupt Routing Registers" line.long 0x278 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER623_lower,Interrupt Routing Registers" bitfld.long 0x278 31. "DISTRIBUTOR__37_GICD_IROUTER623_LOWER__31_1," "0,1" hexmask.long.byte 0x278 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER623_LOWER__8_8," newline hexmask.long.byte 0x278 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER623_LOWER__0_8," line.long 0x27C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER623_upper,Interrupt Routing Registers" line.long 0x280 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER624_lower,Interrupt Routing Registers" bitfld.long 0x280 31. "DISTRIBUTOR__37_GICD_IROUTER624_LOWER__31_1," "0,1" hexmask.long.byte 0x280 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER624_LOWER__8_8," newline hexmask.long.byte 0x280 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER624_LOWER__0_8," line.long 0x284 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER624_upper,Interrupt Routing Registers" line.long 0x288 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER625_lower,Interrupt Routing Registers" bitfld.long 0x288 31. "DISTRIBUTOR__37_GICD_IROUTER625_LOWER__31_1," "0,1" hexmask.long.byte 0x288 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER625_LOWER__8_8," newline hexmask.long.byte 0x288 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER625_LOWER__0_8," line.long 0x28C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER625_upper,Interrupt Routing Registers" line.long 0x290 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER626_lower,Interrupt Routing Registers" bitfld.long 0x290 31. "DISTRIBUTOR__37_GICD_IROUTER626_LOWER__31_1," "0,1" hexmask.long.byte 0x290 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER626_LOWER__8_8," newline hexmask.long.byte 0x290 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER626_LOWER__0_8," line.long 0x294 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER626_upper,Interrupt Routing Registers" line.long 0x298 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER627_lower,Interrupt Routing Registers" bitfld.long 0x298 31. "DISTRIBUTOR__37_GICD_IROUTER627_LOWER__31_1," "0,1" hexmask.long.byte 0x298 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER627_LOWER__8_8," newline hexmask.long.byte 0x298 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER627_LOWER__0_8," line.long 0x29C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER627_upper,Interrupt Routing Registers" line.long 0x2A0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER628_lower,Interrupt Routing Registers" bitfld.long 0x2A0 31. "DISTRIBUTOR__37_GICD_IROUTER628_LOWER__31_1," "0,1" hexmask.long.byte 0x2A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER628_LOWER__8_8," newline hexmask.long.byte 0x2A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER628_LOWER__0_8," line.long 0x2A4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER628_upper,Interrupt Routing Registers" line.long 0x2A8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER629_lower,Interrupt Routing Registers" bitfld.long 0x2A8 31. "DISTRIBUTOR__37_GICD_IROUTER629_LOWER__31_1," "0,1" hexmask.long.byte 0x2A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER629_LOWER__8_8," newline hexmask.long.byte 0x2A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER629_LOWER__0_8," line.long 0x2AC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER629_upper,Interrupt Routing Registers" line.long 0x2B0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER630_lower,Interrupt Routing Registers" bitfld.long 0x2B0 31. "DISTRIBUTOR__37_GICD_IROUTER630_LOWER__31_1," "0,1" hexmask.long.byte 0x2B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER630_LOWER__8_8," newline hexmask.long.byte 0x2B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER630_LOWER__0_8," line.long 0x2B4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER630_upper,Interrupt Routing Registers" line.long 0x2B8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER631_lower,Interrupt Routing Registers" bitfld.long 0x2B8 31. "DISTRIBUTOR__37_GICD_IROUTER631_LOWER__31_1," "0,1" hexmask.long.byte 0x2B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER631_LOWER__8_8," newline hexmask.long.byte 0x2B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER631_LOWER__0_8," line.long 0x2BC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER631_upper,Interrupt Routing Registers" line.long 0x2C0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER632_lower,Interrupt Routing Registers" bitfld.long 0x2C0 31. "DISTRIBUTOR__37_GICD_IROUTER632_LOWER__31_1," "0,1" hexmask.long.byte 0x2C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER632_LOWER__8_8," newline hexmask.long.byte 0x2C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER632_LOWER__0_8," line.long 0x2C4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER632_upper,Interrupt Routing Registers" line.long 0x2C8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER633_lower,Interrupt Routing Registers" bitfld.long 0x2C8 31. "DISTRIBUTOR__37_GICD_IROUTER633_LOWER__31_1," "0,1" hexmask.long.byte 0x2C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER633_LOWER__8_8," newline hexmask.long.byte 0x2C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER633_LOWER__0_8," line.long 0x2CC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER633_upper,Interrupt Routing Registers" line.long 0x2D0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER634_lower,Interrupt Routing Registers" bitfld.long 0x2D0 31. "DISTRIBUTOR__37_GICD_IROUTER634_LOWER__31_1," "0,1" hexmask.long.byte 0x2D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER634_LOWER__8_8," newline hexmask.long.byte 0x2D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER634_LOWER__0_8," line.long 0x2D4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER634_upper,Interrupt Routing Registers" line.long 0x2D8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER635_lower,Interrupt Routing Registers" bitfld.long 0x2D8 31. "DISTRIBUTOR__37_GICD_IROUTER635_LOWER__31_1," "0,1" hexmask.long.byte 0x2D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER635_LOWER__8_8," newline hexmask.long.byte 0x2D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER635_LOWER__0_8," line.long 0x2DC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER635_upper,Interrupt Routing Registers" line.long 0x2E0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER636_lower,Interrupt Routing Registers" bitfld.long 0x2E0 31. "DISTRIBUTOR__37_GICD_IROUTER636_LOWER__31_1," "0,1" hexmask.long.byte 0x2E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER636_LOWER__8_8," newline hexmask.long.byte 0x2E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER636_LOWER__0_8," line.long 0x2E4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER636_upper,Interrupt Routing Registers" line.long 0x2E8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER637_lower,Interrupt Routing Registers" bitfld.long 0x2E8 31. "DISTRIBUTOR__37_GICD_IROUTER637_LOWER__31_1," "0,1" hexmask.long.byte 0x2E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER637_LOWER__8_8," newline hexmask.long.byte 0x2E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER637_LOWER__0_8," line.long 0x2EC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER637_upper,Interrupt Routing Registers" line.long 0x2F0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER638_lower,Interrupt Routing Registers" bitfld.long 0x2F0 31. "DISTRIBUTOR__37_GICD_IROUTER638_LOWER__31_1," "0,1" hexmask.long.byte 0x2F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER638_LOWER__8_8," newline hexmask.long.byte 0x2F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER638_LOWER__0_8," line.long 0x2F4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER638_upper,Interrupt Routing Registers" line.long 0x2F8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER639_lower,Interrupt Routing Registers" bitfld.long 0x2F8 31. "DISTRIBUTOR__37_GICD_IROUTER639_LOWER__31_1," "0,1" hexmask.long.byte 0x2F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER639_LOWER__8_8," newline hexmask.long.byte 0x2F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER639_LOWER__0_8," line.long 0x2FC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER639_upper,Interrupt Routing Registers" line.long 0x300 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER640_lower,Interrupt Routing Registers" bitfld.long 0x300 31. "DISTRIBUTOR__37_GICD_IROUTER640_LOWER__31_1," "0,1" hexmask.long.byte 0x300 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER640_LOWER__8_8," newline hexmask.long.byte 0x300 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER640_LOWER__0_8," line.long 0x304 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER640_upper,Interrupt Routing Registers" line.long 0x308 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER641_lower,Interrupt Routing Registers" bitfld.long 0x308 31. "DISTRIBUTOR__37_GICD_IROUTER641_LOWER__31_1," "0,1" hexmask.long.byte 0x308 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER641_LOWER__8_8," newline hexmask.long.byte 0x308 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER641_LOWER__0_8," line.long 0x30C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER641_upper,Interrupt Routing Registers" line.long 0x310 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER642_lower,Interrupt Routing Registers" bitfld.long 0x310 31. "DISTRIBUTOR__37_GICD_IROUTER642_LOWER__31_1," "0,1" hexmask.long.byte 0x310 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER642_LOWER__8_8," newline hexmask.long.byte 0x310 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER642_LOWER__0_8," line.long 0x314 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER642_upper,Interrupt Routing Registers" line.long 0x318 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER643_lower,Interrupt Routing Registers" bitfld.long 0x318 31. "DISTRIBUTOR__37_GICD_IROUTER643_LOWER__31_1," "0,1" hexmask.long.byte 0x318 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER643_LOWER__8_8," newline hexmask.long.byte 0x318 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER643_LOWER__0_8," line.long 0x31C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER643_upper,Interrupt Routing Registers" line.long 0x320 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER644_lower,Interrupt Routing Registers" bitfld.long 0x320 31. "DISTRIBUTOR__37_GICD_IROUTER644_LOWER__31_1," "0,1" hexmask.long.byte 0x320 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER644_LOWER__8_8," newline hexmask.long.byte 0x320 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER644_LOWER__0_8," line.long 0x324 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER644_upper,Interrupt Routing Registers" line.long 0x328 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER645_lower,Interrupt Routing Registers" bitfld.long 0x328 31. "DISTRIBUTOR__37_GICD_IROUTER645_LOWER__31_1," "0,1" hexmask.long.byte 0x328 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER645_LOWER__8_8," newline hexmask.long.byte 0x328 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER645_LOWER__0_8," line.long 0x32C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER645_upper,Interrupt Routing Registers" line.long 0x330 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER646_lower,Interrupt Routing Registers" bitfld.long 0x330 31. "DISTRIBUTOR__37_GICD_IROUTER646_LOWER__31_1," "0,1" hexmask.long.byte 0x330 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER646_LOWER__8_8," newline hexmask.long.byte 0x330 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER646_LOWER__0_8," line.long 0x334 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER646_upper,Interrupt Routing Registers" line.long 0x338 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER647_lower,Interrupt Routing Registers" bitfld.long 0x338 31. "DISTRIBUTOR__37_GICD_IROUTER647_LOWER__31_1," "0,1" hexmask.long.byte 0x338 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER647_LOWER__8_8," newline hexmask.long.byte 0x338 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER647_LOWER__0_8," line.long 0x33C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER647_upper,Interrupt Routing Registers" line.long 0x340 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER648_lower,Interrupt Routing Registers" bitfld.long 0x340 31. "DISTRIBUTOR__37_GICD_IROUTER648_LOWER__31_1," "0,1" hexmask.long.byte 0x340 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER648_LOWER__8_8," newline hexmask.long.byte 0x340 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER648_LOWER__0_8," line.long 0x344 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER648_upper,Interrupt Routing Registers" line.long 0x348 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER649_lower,Interrupt Routing Registers" bitfld.long 0x348 31. "DISTRIBUTOR__37_GICD_IROUTER649_LOWER__31_1," "0,1" hexmask.long.byte 0x348 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER649_LOWER__8_8," newline hexmask.long.byte 0x348 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER649_LOWER__0_8," line.long 0x34C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER649_upper,Interrupt Routing Registers" line.long 0x350 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER650_lower,Interrupt Routing Registers" bitfld.long 0x350 31. "DISTRIBUTOR__37_GICD_IROUTER650_LOWER__31_1," "0,1" hexmask.long.byte 0x350 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER650_LOWER__8_8," newline hexmask.long.byte 0x350 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER650_LOWER__0_8," line.long 0x354 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER650_upper,Interrupt Routing Registers" line.long 0x358 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER651_lower,Interrupt Routing Registers" bitfld.long 0x358 31. "DISTRIBUTOR__37_GICD_IROUTER651_LOWER__31_1," "0,1" hexmask.long.byte 0x358 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER651_LOWER__8_8," newline hexmask.long.byte 0x358 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER651_LOWER__0_8," line.long 0x35C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER651_upper,Interrupt Routing Registers" line.long 0x360 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER652_lower,Interrupt Routing Registers" bitfld.long 0x360 31. "DISTRIBUTOR__37_GICD_IROUTER652_LOWER__31_1," "0,1" hexmask.long.byte 0x360 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER652_LOWER__8_8," newline hexmask.long.byte 0x360 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER652_LOWER__0_8," line.long 0x364 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER652_upper,Interrupt Routing Registers" line.long 0x368 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER653_lower,Interrupt Routing Registers" bitfld.long 0x368 31. "DISTRIBUTOR__37_GICD_IROUTER653_LOWER__31_1," "0,1" hexmask.long.byte 0x368 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER653_LOWER__8_8," newline hexmask.long.byte 0x368 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER653_LOWER__0_8," line.long 0x36C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER653_upper,Interrupt Routing Registers" line.long 0x370 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER654_lower,Interrupt Routing Registers" bitfld.long 0x370 31. "DISTRIBUTOR__37_GICD_IROUTER654_LOWER__31_1," "0,1" hexmask.long.byte 0x370 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER654_LOWER__8_8," newline hexmask.long.byte 0x370 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER654_LOWER__0_8," line.long 0x374 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER654_upper,Interrupt Routing Registers" line.long 0x378 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER655_lower,Interrupt Routing Registers" bitfld.long 0x378 31. "DISTRIBUTOR__37_GICD_IROUTER655_LOWER__31_1," "0,1" hexmask.long.byte 0x378 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER655_LOWER__8_8," newline hexmask.long.byte 0x378 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER655_LOWER__0_8," line.long 0x37C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER655_upper,Interrupt Routing Registers" line.long 0x380 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER656_lower,Interrupt Routing Registers" bitfld.long 0x380 31. "DISTRIBUTOR__37_GICD_IROUTER656_LOWER__31_1," "0,1" hexmask.long.byte 0x380 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER656_LOWER__8_8," newline hexmask.long.byte 0x380 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER656_LOWER__0_8," line.long 0x384 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER656_upper,Interrupt Routing Registers" line.long 0x388 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER657_lower,Interrupt Routing Registers" bitfld.long 0x388 31. "DISTRIBUTOR__37_GICD_IROUTER657_LOWER__31_1," "0,1" hexmask.long.byte 0x388 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER657_LOWER__8_8," newline hexmask.long.byte 0x388 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER657_LOWER__0_8," line.long 0x38C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER657_upper,Interrupt Routing Registers" line.long 0x390 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER658_lower,Interrupt Routing Registers" bitfld.long 0x390 31. "DISTRIBUTOR__37_GICD_IROUTER658_LOWER__31_1," "0,1" hexmask.long.byte 0x390 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER658_LOWER__8_8," newline hexmask.long.byte 0x390 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER658_LOWER__0_8," line.long 0x394 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER658_upper,Interrupt Routing Registers" line.long 0x398 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER659_lower,Interrupt Routing Registers" bitfld.long 0x398 31. "DISTRIBUTOR__37_GICD_IROUTER659_LOWER__31_1," "0,1" hexmask.long.byte 0x398 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER659_LOWER__8_8," newline hexmask.long.byte 0x398 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER659_LOWER__0_8," line.long 0x39C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER659_upper,Interrupt Routing Registers" line.long 0x3A0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER660_lower,Interrupt Routing Registers" bitfld.long 0x3A0 31. "DISTRIBUTOR__37_GICD_IROUTER660_LOWER__31_1," "0,1" hexmask.long.byte 0x3A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER660_LOWER__8_8," newline hexmask.long.byte 0x3A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER660_LOWER__0_8," line.long 0x3A4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER660_upper,Interrupt Routing Registers" line.long 0x3A8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER661_lower,Interrupt Routing Registers" bitfld.long 0x3A8 31. "DISTRIBUTOR__37_GICD_IROUTER661_LOWER__31_1," "0,1" hexmask.long.byte 0x3A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER661_LOWER__8_8," newline hexmask.long.byte 0x3A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER661_LOWER__0_8," line.long 0x3AC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER661_upper,Interrupt Routing Registers" line.long 0x3B0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER662_lower,Interrupt Routing Registers" bitfld.long 0x3B0 31. "DISTRIBUTOR__37_GICD_IROUTER662_LOWER__31_1," "0,1" hexmask.long.byte 0x3B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER662_LOWER__8_8," newline hexmask.long.byte 0x3B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER662_LOWER__0_8," line.long 0x3B4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER662_upper,Interrupt Routing Registers" line.long 0x3B8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER663_lower,Interrupt Routing Registers" bitfld.long 0x3B8 31. "DISTRIBUTOR__37_GICD_IROUTER663_LOWER__31_1," "0,1" hexmask.long.byte 0x3B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER663_LOWER__8_8," newline hexmask.long.byte 0x3B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER663_LOWER__0_8," line.long 0x3BC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER663_upper,Interrupt Routing Registers" line.long 0x3C0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER664_lower,Interrupt Routing Registers" bitfld.long 0x3C0 31. "DISTRIBUTOR__37_GICD_IROUTER664_LOWER__31_1," "0,1" hexmask.long.byte 0x3C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER664_LOWER__8_8," newline hexmask.long.byte 0x3C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER664_LOWER__0_8," line.long 0x3C4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER664_upper,Interrupt Routing Registers" line.long 0x3C8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER665_lower,Interrupt Routing Registers" bitfld.long 0x3C8 31. "DISTRIBUTOR__37_GICD_IROUTER665_LOWER__31_1," "0,1" hexmask.long.byte 0x3C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER665_LOWER__8_8," newline hexmask.long.byte 0x3C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER665_LOWER__0_8," line.long 0x3CC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER665_upper,Interrupt Routing Registers" line.long 0x3D0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER666_lower,Interrupt Routing Registers" bitfld.long 0x3D0 31. "DISTRIBUTOR__37_GICD_IROUTER666_LOWER__31_1," "0,1" hexmask.long.byte 0x3D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER666_LOWER__8_8," newline hexmask.long.byte 0x3D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER666_LOWER__0_8," line.long 0x3D4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER666_upper,Interrupt Routing Registers" line.long 0x3D8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER667_lower,Interrupt Routing Registers" bitfld.long 0x3D8 31. "DISTRIBUTOR__37_GICD_IROUTER667_LOWER__31_1," "0,1" hexmask.long.byte 0x3D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER667_LOWER__8_8," newline hexmask.long.byte 0x3D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER667_LOWER__0_8," line.long 0x3DC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER667_upper,Interrupt Routing Registers" line.long 0x3E0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER668_lower,Interrupt Routing Registers" bitfld.long 0x3E0 31. "DISTRIBUTOR__37_GICD_IROUTER668_LOWER__31_1," "0,1" hexmask.long.byte 0x3E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER668_LOWER__8_8," newline hexmask.long.byte 0x3E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER668_LOWER__0_8," line.long 0x3E4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER668_upper,Interrupt Routing Registers" line.long 0x3E8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER669_lower,Interrupt Routing Registers" bitfld.long 0x3E8 31. "DISTRIBUTOR__37_GICD_IROUTER669_LOWER__31_1," "0,1" hexmask.long.byte 0x3E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER669_LOWER__8_8," newline hexmask.long.byte 0x3E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER669_LOWER__0_8," line.long 0x3EC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER669_upper,Interrupt Routing Registers" line.long 0x3F0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER670_lower,Interrupt Routing Registers" bitfld.long 0x3F0 31. "DISTRIBUTOR__37_GICD_IROUTER670_LOWER__31_1," "0,1" hexmask.long.byte 0x3F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER670_LOWER__8_8," newline hexmask.long.byte 0x3F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER670_LOWER__0_8," line.long 0x3F4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER670_upper,Interrupt Routing Registers" line.long 0x3F8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER671_lower,Interrupt Routing Registers" bitfld.long 0x3F8 31. "DISTRIBUTOR__37_GICD_IROUTER671_LOWER__31_1," "0,1" hexmask.long.byte 0x3F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER671_LOWER__8_8," newline hexmask.long.byte 0x3F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER671_LOWER__0_8," line.long 0x3FC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER671_upper,Interrupt Routing Registers" line.long 0x400 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER672_lower,Interrupt Routing Registers" bitfld.long 0x400 31. "DISTRIBUTOR__37_GICD_IROUTER672_LOWER__31_1," "0,1" hexmask.long.byte 0x400 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER672_LOWER__8_8," newline hexmask.long.byte 0x400 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER672_LOWER__0_8," line.long 0x404 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER672_upper,Interrupt Routing Registers" line.long 0x408 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER673_lower,Interrupt Routing Registers" bitfld.long 0x408 31. "DISTRIBUTOR__37_GICD_IROUTER673_LOWER__31_1," "0,1" hexmask.long.byte 0x408 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER673_LOWER__8_8," newline hexmask.long.byte 0x408 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER673_LOWER__0_8," line.long 0x40C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER673_upper,Interrupt Routing Registers" line.long 0x410 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER674_lower,Interrupt Routing Registers" bitfld.long 0x410 31. "DISTRIBUTOR__37_GICD_IROUTER674_LOWER__31_1," "0,1" hexmask.long.byte 0x410 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER674_LOWER__8_8," newline hexmask.long.byte 0x410 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER674_LOWER__0_8," line.long 0x414 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER674_upper,Interrupt Routing Registers" line.long 0x418 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER675_lower,Interrupt Routing Registers" bitfld.long 0x418 31. "DISTRIBUTOR__37_GICD_IROUTER675_LOWER__31_1," "0,1" hexmask.long.byte 0x418 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER675_LOWER__8_8," newline hexmask.long.byte 0x418 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER675_LOWER__0_8," line.long 0x41C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER675_upper,Interrupt Routing Registers" line.long 0x420 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER676_lower,Interrupt Routing Registers" bitfld.long 0x420 31. "DISTRIBUTOR__37_GICD_IROUTER676_LOWER__31_1," "0,1" hexmask.long.byte 0x420 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER676_LOWER__8_8," newline hexmask.long.byte 0x420 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER676_LOWER__0_8," line.long 0x424 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER676_upper,Interrupt Routing Registers" line.long 0x428 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER677_lower,Interrupt Routing Registers" bitfld.long 0x428 31. "DISTRIBUTOR__37_GICD_IROUTER677_LOWER__31_1," "0,1" hexmask.long.byte 0x428 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER677_LOWER__8_8," newline hexmask.long.byte 0x428 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER677_LOWER__0_8," line.long 0x42C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER677_upper,Interrupt Routing Registers" line.long 0x430 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER678_lower,Interrupt Routing Registers" bitfld.long 0x430 31. "DISTRIBUTOR__37_GICD_IROUTER678_LOWER__31_1," "0,1" hexmask.long.byte 0x430 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER678_LOWER__8_8," newline hexmask.long.byte 0x430 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER678_LOWER__0_8," line.long 0x434 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER678_upper,Interrupt Routing Registers" line.long 0x438 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER679_lower,Interrupt Routing Registers" bitfld.long 0x438 31. "DISTRIBUTOR__37_GICD_IROUTER679_LOWER__31_1," "0,1" hexmask.long.byte 0x438 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER679_LOWER__8_8," newline hexmask.long.byte 0x438 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER679_LOWER__0_8," line.long 0x43C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER679_upper,Interrupt Routing Registers" line.long 0x440 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER680_lower,Interrupt Routing Registers" bitfld.long 0x440 31. "DISTRIBUTOR__37_GICD_IROUTER680_LOWER__31_1," "0,1" hexmask.long.byte 0x440 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER680_LOWER__8_8," newline hexmask.long.byte 0x440 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER680_LOWER__0_8," line.long 0x444 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER680_upper,Interrupt Routing Registers" line.long 0x448 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER681_lower,Interrupt Routing Registers" bitfld.long 0x448 31. "DISTRIBUTOR__37_GICD_IROUTER681_LOWER__31_1," "0,1" hexmask.long.byte 0x448 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER681_LOWER__8_8," newline hexmask.long.byte 0x448 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER681_LOWER__0_8," line.long 0x44C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER681_upper,Interrupt Routing Registers" line.long 0x450 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER682_lower,Interrupt Routing Registers" bitfld.long 0x450 31. "DISTRIBUTOR__37_GICD_IROUTER682_LOWER__31_1," "0,1" hexmask.long.byte 0x450 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER682_LOWER__8_8," newline hexmask.long.byte 0x450 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER682_LOWER__0_8," line.long 0x454 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER682_upper,Interrupt Routing Registers" line.long 0x458 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER683_lower,Interrupt Routing Registers" bitfld.long 0x458 31. "DISTRIBUTOR__37_GICD_IROUTER683_LOWER__31_1," "0,1" hexmask.long.byte 0x458 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER683_LOWER__8_8," newline hexmask.long.byte 0x458 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER683_LOWER__0_8," line.long 0x45C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER683_upper,Interrupt Routing Registers" line.long 0x460 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER684_lower,Interrupt Routing Registers" bitfld.long 0x460 31. "DISTRIBUTOR__37_GICD_IROUTER684_LOWER__31_1," "0,1" hexmask.long.byte 0x460 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER684_LOWER__8_8," newline hexmask.long.byte 0x460 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER684_LOWER__0_8," line.long 0x464 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER684_upper,Interrupt Routing Registers" line.long 0x468 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER685_lower,Interrupt Routing Registers" bitfld.long 0x468 31. "DISTRIBUTOR__37_GICD_IROUTER685_LOWER__31_1," "0,1" hexmask.long.byte 0x468 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER685_LOWER__8_8," newline hexmask.long.byte 0x468 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER685_LOWER__0_8," line.long 0x46C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER685_upper,Interrupt Routing Registers" line.long 0x470 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER686_lower,Interrupt Routing Registers" bitfld.long 0x470 31. "DISTRIBUTOR__37_GICD_IROUTER686_LOWER__31_1," "0,1" hexmask.long.byte 0x470 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER686_LOWER__8_8," newline hexmask.long.byte 0x470 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER686_LOWER__0_8," line.long 0x474 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER686_upper,Interrupt Routing Registers" line.long 0x478 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER687_lower,Interrupt Routing Registers" bitfld.long 0x478 31. "DISTRIBUTOR__37_GICD_IROUTER687_LOWER__31_1," "0,1" hexmask.long.byte 0x478 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER687_LOWER__8_8," newline hexmask.long.byte 0x478 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER687_LOWER__0_8," line.long 0x47C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER687_upper,Interrupt Routing Registers" line.long 0x480 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER688_lower,Interrupt Routing Registers" bitfld.long 0x480 31. "DISTRIBUTOR__37_GICD_IROUTER688_LOWER__31_1," "0,1" hexmask.long.byte 0x480 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER688_LOWER__8_8," newline hexmask.long.byte 0x480 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER688_LOWER__0_8," line.long 0x484 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER688_upper,Interrupt Routing Registers" line.long 0x488 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER689_lower,Interrupt Routing Registers" bitfld.long 0x488 31. "DISTRIBUTOR__37_GICD_IROUTER689_LOWER__31_1," "0,1" hexmask.long.byte 0x488 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER689_LOWER__8_8," newline hexmask.long.byte 0x488 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER689_LOWER__0_8," line.long 0x48C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER689_upper,Interrupt Routing Registers" line.long 0x490 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER690_lower,Interrupt Routing Registers" bitfld.long 0x490 31. "DISTRIBUTOR__37_GICD_IROUTER690_LOWER__31_1," "0,1" hexmask.long.byte 0x490 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER690_LOWER__8_8," newline hexmask.long.byte 0x490 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER690_LOWER__0_8," line.long 0x494 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER690_upper,Interrupt Routing Registers" line.long 0x498 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER691_lower,Interrupt Routing Registers" bitfld.long 0x498 31. "DISTRIBUTOR__37_GICD_IROUTER691_LOWER__31_1," "0,1" hexmask.long.byte 0x498 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER691_LOWER__8_8," newline hexmask.long.byte 0x498 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER691_LOWER__0_8," line.long 0x49C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER691_upper,Interrupt Routing Registers" line.long 0x4A0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER692_lower,Interrupt Routing Registers" bitfld.long 0x4A0 31. "DISTRIBUTOR__37_GICD_IROUTER692_LOWER__31_1," "0,1" hexmask.long.byte 0x4A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER692_LOWER__8_8," newline hexmask.long.byte 0x4A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER692_LOWER__0_8," line.long 0x4A4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER692_upper,Interrupt Routing Registers" line.long 0x4A8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER693_lower,Interrupt Routing Registers" bitfld.long 0x4A8 31. "DISTRIBUTOR__37_GICD_IROUTER693_LOWER__31_1," "0,1" hexmask.long.byte 0x4A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER693_LOWER__8_8," newline hexmask.long.byte 0x4A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER693_LOWER__0_8," line.long 0x4AC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER693_upper,Interrupt Routing Registers" line.long 0x4B0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER694_lower,Interrupt Routing Registers" bitfld.long 0x4B0 31. "DISTRIBUTOR__37_GICD_IROUTER694_LOWER__31_1," "0,1" hexmask.long.byte 0x4B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER694_LOWER__8_8," newline hexmask.long.byte 0x4B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER694_LOWER__0_8," line.long 0x4B4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER694_upper,Interrupt Routing Registers" line.long 0x4B8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER695_lower,Interrupt Routing Registers" bitfld.long 0x4B8 31. "DISTRIBUTOR__37_GICD_IROUTER695_LOWER__31_1," "0,1" hexmask.long.byte 0x4B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER695_LOWER__8_8," newline hexmask.long.byte 0x4B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER695_LOWER__0_8," line.long 0x4BC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER695_upper,Interrupt Routing Registers" line.long 0x4C0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER696_lower,Interrupt Routing Registers" bitfld.long 0x4C0 31. "DISTRIBUTOR__37_GICD_IROUTER696_LOWER__31_1," "0,1" hexmask.long.byte 0x4C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER696_LOWER__8_8," newline hexmask.long.byte 0x4C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER696_LOWER__0_8," line.long 0x4C4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER696_upper,Interrupt Routing Registers" line.long 0x4C8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER697_lower,Interrupt Routing Registers" bitfld.long 0x4C8 31. "DISTRIBUTOR__37_GICD_IROUTER697_LOWER__31_1," "0,1" hexmask.long.byte 0x4C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER697_LOWER__8_8," newline hexmask.long.byte 0x4C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER697_LOWER__0_8," line.long 0x4CC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER697_upper,Interrupt Routing Registers" line.long 0x4D0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER698_lower,Interrupt Routing Registers" bitfld.long 0x4D0 31. "DISTRIBUTOR__37_GICD_IROUTER698_LOWER__31_1," "0,1" hexmask.long.byte 0x4D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER698_LOWER__8_8," newline hexmask.long.byte 0x4D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER698_LOWER__0_8," line.long 0x4D4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER698_upper,Interrupt Routing Registers" line.long 0x4D8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER699_lower,Interrupt Routing Registers" bitfld.long 0x4D8 31. "DISTRIBUTOR__37_GICD_IROUTER699_LOWER__31_1," "0,1" hexmask.long.byte 0x4D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER699_LOWER__8_8," newline hexmask.long.byte 0x4D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER699_LOWER__0_8," line.long 0x4DC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER699_upper,Interrupt Routing Registers" line.long 0x4E0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER700_lower,Interrupt Routing Registers" bitfld.long 0x4E0 31. "DISTRIBUTOR__37_GICD_IROUTER700_LOWER__31_1," "0,1" hexmask.long.byte 0x4E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER700_LOWER__8_8," newline hexmask.long.byte 0x4E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER700_LOWER__0_8," line.long 0x4E4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER700_upper,Interrupt Routing Registers" line.long 0x4E8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER701_lower,Interrupt Routing Registers" bitfld.long 0x4E8 31. "DISTRIBUTOR__37_GICD_IROUTER701_LOWER__31_1," "0,1" hexmask.long.byte 0x4E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER701_LOWER__8_8," newline hexmask.long.byte 0x4E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER701_LOWER__0_8," line.long 0x4EC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER701_upper,Interrupt Routing Registers" line.long 0x4F0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER702_lower,Interrupt Routing Registers" bitfld.long 0x4F0 31. "DISTRIBUTOR__37_GICD_IROUTER702_LOWER__31_1," "0,1" hexmask.long.byte 0x4F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER702_LOWER__8_8," newline hexmask.long.byte 0x4F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER702_LOWER__0_8," line.long 0x4F4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER702_upper,Interrupt Routing Registers" line.long 0x4F8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER703_lower,Interrupt Routing Registers" bitfld.long 0x4F8 31. "DISTRIBUTOR__37_GICD_IROUTER703_LOWER__31_1," "0,1" hexmask.long.byte 0x4F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER703_LOWER__8_8," newline hexmask.long.byte 0x4F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER703_LOWER__0_8," line.long 0x4FC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER703_upper,Interrupt Routing Registers" line.long 0x500 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER704_lower,Interrupt Routing Registers" bitfld.long 0x500 31. "DISTRIBUTOR__37_GICD_IROUTER704_LOWER__31_1," "0,1" hexmask.long.byte 0x500 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER704_LOWER__8_8," newline hexmask.long.byte 0x500 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER704_LOWER__0_8," line.long 0x504 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER704_upper,Interrupt Routing Registers" line.long 0x508 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER705_lower,Interrupt Routing Registers" bitfld.long 0x508 31. "DISTRIBUTOR__37_GICD_IROUTER705_LOWER__31_1," "0,1" hexmask.long.byte 0x508 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER705_LOWER__8_8," newline hexmask.long.byte 0x508 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER705_LOWER__0_8," line.long 0x50C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER705_upper,Interrupt Routing Registers" line.long 0x510 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER706_lower,Interrupt Routing Registers" bitfld.long 0x510 31. "DISTRIBUTOR__37_GICD_IROUTER706_LOWER__31_1," "0,1" hexmask.long.byte 0x510 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER706_LOWER__8_8," newline hexmask.long.byte 0x510 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER706_LOWER__0_8," line.long 0x514 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER706_upper,Interrupt Routing Registers" line.long 0x518 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER707_lower,Interrupt Routing Registers" bitfld.long 0x518 31. "DISTRIBUTOR__37_GICD_IROUTER707_LOWER__31_1," "0,1" hexmask.long.byte 0x518 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER707_LOWER__8_8," newline hexmask.long.byte 0x518 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER707_LOWER__0_8," line.long 0x51C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER707_upper,Interrupt Routing Registers" line.long 0x520 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER708_lower,Interrupt Routing Registers" bitfld.long 0x520 31. "DISTRIBUTOR__37_GICD_IROUTER708_LOWER__31_1," "0,1" hexmask.long.byte 0x520 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER708_LOWER__8_8," newline hexmask.long.byte 0x520 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER708_LOWER__0_8," line.long 0x524 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER708_upper,Interrupt Routing Registers" line.long 0x528 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER709_lower,Interrupt Routing Registers" bitfld.long 0x528 31. "DISTRIBUTOR__37_GICD_IROUTER709_LOWER__31_1," "0,1" hexmask.long.byte 0x528 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER709_LOWER__8_8," newline hexmask.long.byte 0x528 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER709_LOWER__0_8," line.long 0x52C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER709_upper,Interrupt Routing Registers" line.long 0x530 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER710_lower,Interrupt Routing Registers" bitfld.long 0x530 31. "DISTRIBUTOR__37_GICD_IROUTER710_LOWER__31_1," "0,1" hexmask.long.byte 0x530 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER710_LOWER__8_8," newline hexmask.long.byte 0x530 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER710_LOWER__0_8," line.long 0x534 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER710_upper,Interrupt Routing Registers" line.long 0x538 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER711_lower,Interrupt Routing Registers" bitfld.long 0x538 31. "DISTRIBUTOR__37_GICD_IROUTER711_LOWER__31_1," "0,1" hexmask.long.byte 0x538 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER711_LOWER__8_8," newline hexmask.long.byte 0x538 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER711_LOWER__0_8," line.long 0x53C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER711_upper,Interrupt Routing Registers" line.long 0x540 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER712_lower,Interrupt Routing Registers" bitfld.long 0x540 31. "DISTRIBUTOR__37_GICD_IROUTER712_LOWER__31_1," "0,1" hexmask.long.byte 0x540 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER712_LOWER__8_8," newline hexmask.long.byte 0x540 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER712_LOWER__0_8," line.long 0x544 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER712_upper,Interrupt Routing Registers" line.long 0x548 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER713_lower,Interrupt Routing Registers" bitfld.long 0x548 31. "DISTRIBUTOR__37_GICD_IROUTER713_LOWER__31_1," "0,1" hexmask.long.byte 0x548 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER713_LOWER__8_8," newline hexmask.long.byte 0x548 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER713_LOWER__0_8," line.long 0x54C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER713_upper,Interrupt Routing Registers" line.long 0x550 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER714_lower,Interrupt Routing Registers" bitfld.long 0x550 31. "DISTRIBUTOR__37_GICD_IROUTER714_LOWER__31_1," "0,1" hexmask.long.byte 0x550 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER714_LOWER__8_8," newline hexmask.long.byte 0x550 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER714_LOWER__0_8," line.long 0x554 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER714_upper,Interrupt Routing Registers" line.long 0x558 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER715_lower,Interrupt Routing Registers" bitfld.long 0x558 31. "DISTRIBUTOR__37_GICD_IROUTER715_LOWER__31_1," "0,1" hexmask.long.byte 0x558 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER715_LOWER__8_8," newline hexmask.long.byte 0x558 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER715_LOWER__0_8," line.long 0x55C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER715_upper,Interrupt Routing Registers" line.long 0x560 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER716_lower,Interrupt Routing Registers" bitfld.long 0x560 31. "DISTRIBUTOR__37_GICD_IROUTER716_LOWER__31_1," "0,1" hexmask.long.byte 0x560 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER716_LOWER__8_8," newline hexmask.long.byte 0x560 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER716_LOWER__0_8," line.long 0x564 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER716_upper,Interrupt Routing Registers" line.long 0x568 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER717_lower,Interrupt Routing Registers" bitfld.long 0x568 31. "DISTRIBUTOR__37_GICD_IROUTER717_LOWER__31_1," "0,1" hexmask.long.byte 0x568 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER717_LOWER__8_8," newline hexmask.long.byte 0x568 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER717_LOWER__0_8," line.long 0x56C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER717_upper,Interrupt Routing Registers" line.long 0x570 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER718_lower,Interrupt Routing Registers" bitfld.long 0x570 31. "DISTRIBUTOR__37_GICD_IROUTER718_LOWER__31_1," "0,1" hexmask.long.byte 0x570 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER718_LOWER__8_8," newline hexmask.long.byte 0x570 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER718_LOWER__0_8," line.long 0x574 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER718_upper,Interrupt Routing Registers" line.long 0x578 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER719_lower,Interrupt Routing Registers" bitfld.long 0x578 31. "DISTRIBUTOR__37_GICD_IROUTER719_LOWER__31_1," "0,1" hexmask.long.byte 0x578 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER719_LOWER__8_8," newline hexmask.long.byte 0x578 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER719_LOWER__0_8," line.long 0x57C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER719_upper,Interrupt Routing Registers" line.long 0x580 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER720_lower,Interrupt Routing Registers" bitfld.long 0x580 31. "DISTRIBUTOR__37_GICD_IROUTER720_LOWER__31_1," "0,1" hexmask.long.byte 0x580 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER720_LOWER__8_8," newline hexmask.long.byte 0x580 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER720_LOWER__0_8," line.long 0x584 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER720_upper,Interrupt Routing Registers" line.long 0x588 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER721_lower,Interrupt Routing Registers" bitfld.long 0x588 31. "DISTRIBUTOR__37_GICD_IROUTER721_LOWER__31_1," "0,1" hexmask.long.byte 0x588 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER721_LOWER__8_8," newline hexmask.long.byte 0x588 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER721_LOWER__0_8," line.long 0x58C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER721_upper,Interrupt Routing Registers" line.long 0x590 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER722_lower,Interrupt Routing Registers" bitfld.long 0x590 31. "DISTRIBUTOR__37_GICD_IROUTER722_LOWER__31_1," "0,1" hexmask.long.byte 0x590 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER722_LOWER__8_8," newline hexmask.long.byte 0x590 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER722_LOWER__0_8," line.long 0x594 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER722_upper,Interrupt Routing Registers" line.long 0x598 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER723_lower,Interrupt Routing Registers" bitfld.long 0x598 31. "DISTRIBUTOR__37_GICD_IROUTER723_LOWER__31_1," "0,1" hexmask.long.byte 0x598 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER723_LOWER__8_8," newline hexmask.long.byte 0x598 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER723_LOWER__0_8," line.long 0x59C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER723_upper,Interrupt Routing Registers" line.long 0x5A0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER724_lower,Interrupt Routing Registers" bitfld.long 0x5A0 31. "DISTRIBUTOR__37_GICD_IROUTER724_LOWER__31_1," "0,1" hexmask.long.byte 0x5A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER724_LOWER__8_8," newline hexmask.long.byte 0x5A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER724_LOWER__0_8," line.long 0x5A4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER724_upper,Interrupt Routing Registers" line.long 0x5A8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER725_lower,Interrupt Routing Registers" bitfld.long 0x5A8 31. "DISTRIBUTOR__37_GICD_IROUTER725_LOWER__31_1," "0,1" hexmask.long.byte 0x5A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER725_LOWER__8_8," newline hexmask.long.byte 0x5A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER725_LOWER__0_8," line.long 0x5AC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER725_upper,Interrupt Routing Registers" line.long 0x5B0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER726_lower,Interrupt Routing Registers" bitfld.long 0x5B0 31. "DISTRIBUTOR__37_GICD_IROUTER726_LOWER__31_1," "0,1" hexmask.long.byte 0x5B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER726_LOWER__8_8," newline hexmask.long.byte 0x5B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER726_LOWER__0_8," line.long 0x5B4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER726_upper,Interrupt Routing Registers" line.long 0x5B8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER727_lower,Interrupt Routing Registers" bitfld.long 0x5B8 31. "DISTRIBUTOR__37_GICD_IROUTER727_LOWER__31_1," "0,1" hexmask.long.byte 0x5B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER727_LOWER__8_8," newline hexmask.long.byte 0x5B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER727_LOWER__0_8," line.long 0x5BC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER727_upper,Interrupt Routing Registers" line.long 0x5C0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER728_lower,Interrupt Routing Registers" bitfld.long 0x5C0 31. "DISTRIBUTOR__37_GICD_IROUTER728_LOWER__31_1," "0,1" hexmask.long.byte 0x5C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER728_LOWER__8_8," newline hexmask.long.byte 0x5C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER728_LOWER__0_8," line.long 0x5C4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER728_upper,Interrupt Routing Registers" line.long 0x5C8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER729_lower,Interrupt Routing Registers" bitfld.long 0x5C8 31. "DISTRIBUTOR__37_GICD_IROUTER729_LOWER__31_1," "0,1" hexmask.long.byte 0x5C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER729_LOWER__8_8," newline hexmask.long.byte 0x5C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER729_LOWER__0_8," line.long 0x5CC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER729_upper,Interrupt Routing Registers" line.long 0x5D0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER730_lower,Interrupt Routing Registers" bitfld.long 0x5D0 31. "DISTRIBUTOR__37_GICD_IROUTER730_LOWER__31_1," "0,1" hexmask.long.byte 0x5D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER730_LOWER__8_8," newline hexmask.long.byte 0x5D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER730_LOWER__0_8," line.long 0x5D4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER730_upper,Interrupt Routing Registers" line.long 0x5D8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER731_lower,Interrupt Routing Registers" bitfld.long 0x5D8 31. "DISTRIBUTOR__37_GICD_IROUTER731_LOWER__31_1," "0,1" hexmask.long.byte 0x5D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER731_LOWER__8_8," newline hexmask.long.byte 0x5D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER731_LOWER__0_8," line.long 0x5DC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER731_upper,Interrupt Routing Registers" line.long 0x5E0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER732_lower,Interrupt Routing Registers" bitfld.long 0x5E0 31. "DISTRIBUTOR__37_GICD_IROUTER732_LOWER__31_1," "0,1" hexmask.long.byte 0x5E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER732_LOWER__8_8," newline hexmask.long.byte 0x5E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER732_LOWER__0_8," line.long 0x5E4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER732_upper,Interrupt Routing Registers" line.long 0x5E8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER733_lower,Interrupt Routing Registers" bitfld.long 0x5E8 31. "DISTRIBUTOR__37_GICD_IROUTER733_LOWER__31_1," "0,1" hexmask.long.byte 0x5E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER733_LOWER__8_8," newline hexmask.long.byte 0x5E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER733_LOWER__0_8," line.long 0x5EC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER733_upper,Interrupt Routing Registers" line.long 0x5F0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER734_lower,Interrupt Routing Registers" bitfld.long 0x5F0 31. "DISTRIBUTOR__37_GICD_IROUTER734_LOWER__31_1," "0,1" hexmask.long.byte 0x5F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER734_LOWER__8_8," newline hexmask.long.byte 0x5F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER734_LOWER__0_8," line.long 0x5F4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER734_upper,Interrupt Routing Registers" line.long 0x5F8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER735_lower,Interrupt Routing Registers" bitfld.long 0x5F8 31. "DISTRIBUTOR__37_GICD_IROUTER735_LOWER__31_1," "0,1" hexmask.long.byte 0x5F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER735_LOWER__8_8," newline hexmask.long.byte 0x5F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER735_LOWER__0_8," line.long 0x5FC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER735_upper,Interrupt Routing Registers" line.long 0x600 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER736_lower,Interrupt Routing Registers" bitfld.long 0x600 31. "DISTRIBUTOR__37_GICD_IROUTER736_LOWER__31_1," "0,1" hexmask.long.byte 0x600 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER736_LOWER__8_8," newline hexmask.long.byte 0x600 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER736_LOWER__0_8," line.long 0x604 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER736_upper,Interrupt Routing Registers" line.long 0x608 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER737_lower,Interrupt Routing Registers" bitfld.long 0x608 31. "DISTRIBUTOR__37_GICD_IROUTER737_LOWER__31_1," "0,1" hexmask.long.byte 0x608 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER737_LOWER__8_8," newline hexmask.long.byte 0x608 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER737_LOWER__0_8," line.long 0x60C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER737_upper,Interrupt Routing Registers" line.long 0x610 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER738_lower,Interrupt Routing Registers" bitfld.long 0x610 31. "DISTRIBUTOR__37_GICD_IROUTER738_LOWER__31_1," "0,1" hexmask.long.byte 0x610 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER738_LOWER__8_8," newline hexmask.long.byte 0x610 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER738_LOWER__0_8," line.long 0x614 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER738_upper,Interrupt Routing Registers" line.long 0x618 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER739_lower,Interrupt Routing Registers" bitfld.long 0x618 31. "DISTRIBUTOR__37_GICD_IROUTER739_LOWER__31_1," "0,1" hexmask.long.byte 0x618 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER739_LOWER__8_8," newline hexmask.long.byte 0x618 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER739_LOWER__0_8," line.long 0x61C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER739_upper,Interrupt Routing Registers" line.long 0x620 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER740_lower,Interrupt Routing Registers" bitfld.long 0x620 31. "DISTRIBUTOR__37_GICD_IROUTER740_LOWER__31_1," "0,1" hexmask.long.byte 0x620 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER740_LOWER__8_8," newline hexmask.long.byte 0x620 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER740_LOWER__0_8," line.long 0x624 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER740_upper,Interrupt Routing Registers" line.long 0x628 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER741_lower,Interrupt Routing Registers" bitfld.long 0x628 31. "DISTRIBUTOR__37_GICD_IROUTER741_LOWER__31_1," "0,1" hexmask.long.byte 0x628 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER741_LOWER__8_8," newline hexmask.long.byte 0x628 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER741_LOWER__0_8," line.long 0x62C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER741_upper,Interrupt Routing Registers" line.long 0x630 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER742_lower,Interrupt Routing Registers" bitfld.long 0x630 31. "DISTRIBUTOR__37_GICD_IROUTER742_LOWER__31_1," "0,1" hexmask.long.byte 0x630 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER742_LOWER__8_8," newline hexmask.long.byte 0x630 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER742_LOWER__0_8," line.long 0x634 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER742_upper,Interrupt Routing Registers" line.long 0x638 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER743_lower,Interrupt Routing Registers" bitfld.long 0x638 31. "DISTRIBUTOR__37_GICD_IROUTER743_LOWER__31_1," "0,1" hexmask.long.byte 0x638 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER743_LOWER__8_8," newline hexmask.long.byte 0x638 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER743_LOWER__0_8," line.long 0x63C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER743_upper,Interrupt Routing Registers" line.long 0x640 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER744_lower,Interrupt Routing Registers" bitfld.long 0x640 31. "DISTRIBUTOR__37_GICD_IROUTER744_LOWER__31_1," "0,1" hexmask.long.byte 0x640 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER744_LOWER__8_8," newline hexmask.long.byte 0x640 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER744_LOWER__0_8," line.long 0x644 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER744_upper,Interrupt Routing Registers" line.long 0x648 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER745_lower,Interrupt Routing Registers" bitfld.long 0x648 31. "DISTRIBUTOR__37_GICD_IROUTER745_LOWER__31_1," "0,1" hexmask.long.byte 0x648 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER745_LOWER__8_8," newline hexmask.long.byte 0x648 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER745_LOWER__0_8," line.long 0x64C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER745_upper,Interrupt Routing Registers" line.long 0x650 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER746_lower,Interrupt Routing Registers" bitfld.long 0x650 31. "DISTRIBUTOR__37_GICD_IROUTER746_LOWER__31_1," "0,1" hexmask.long.byte 0x650 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER746_LOWER__8_8," newline hexmask.long.byte 0x650 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER746_LOWER__0_8," line.long 0x654 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER746_upper,Interrupt Routing Registers" line.long 0x658 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER747_lower,Interrupt Routing Registers" bitfld.long 0x658 31. "DISTRIBUTOR__37_GICD_IROUTER747_LOWER__31_1," "0,1" hexmask.long.byte 0x658 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER747_LOWER__8_8," newline hexmask.long.byte 0x658 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER747_LOWER__0_8," line.long 0x65C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER747_upper,Interrupt Routing Registers" line.long 0x660 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER748_lower,Interrupt Routing Registers" bitfld.long 0x660 31. "DISTRIBUTOR__37_GICD_IROUTER748_LOWER__31_1," "0,1" hexmask.long.byte 0x660 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER748_LOWER__8_8," newline hexmask.long.byte 0x660 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER748_LOWER__0_8," line.long 0x664 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER748_upper,Interrupt Routing Registers" line.long 0x668 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER749_lower,Interrupt Routing Registers" bitfld.long 0x668 31. "DISTRIBUTOR__37_GICD_IROUTER749_LOWER__31_1," "0,1" hexmask.long.byte 0x668 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER749_LOWER__8_8," newline hexmask.long.byte 0x668 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER749_LOWER__0_8," line.long 0x66C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER749_upper,Interrupt Routing Registers" line.long 0x670 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER750_lower,Interrupt Routing Registers" bitfld.long 0x670 31. "DISTRIBUTOR__37_GICD_IROUTER750_LOWER__31_1," "0,1" hexmask.long.byte 0x670 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER750_LOWER__8_8," newline hexmask.long.byte 0x670 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER750_LOWER__0_8," line.long 0x674 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER750_upper,Interrupt Routing Registers" line.long 0x678 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER751_lower,Interrupt Routing Registers" bitfld.long 0x678 31. "DISTRIBUTOR__37_GICD_IROUTER751_LOWER__31_1," "0,1" hexmask.long.byte 0x678 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER751_LOWER__8_8," newline hexmask.long.byte 0x678 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER751_LOWER__0_8," line.long 0x67C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER751_upper,Interrupt Routing Registers" line.long 0x680 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER752_lower,Interrupt Routing Registers" bitfld.long 0x680 31. "DISTRIBUTOR__37_GICD_IROUTER752_LOWER__31_1," "0,1" hexmask.long.byte 0x680 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER752_LOWER__8_8," newline hexmask.long.byte 0x680 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER752_LOWER__0_8," line.long 0x684 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER752_upper,Interrupt Routing Registers" line.long 0x688 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER753_lower,Interrupt Routing Registers" bitfld.long 0x688 31. "DISTRIBUTOR__37_GICD_IROUTER753_LOWER__31_1," "0,1" hexmask.long.byte 0x688 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER753_LOWER__8_8," newline hexmask.long.byte 0x688 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER753_LOWER__0_8," line.long 0x68C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER753_upper,Interrupt Routing Registers" line.long 0x690 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER754_lower,Interrupt Routing Registers" bitfld.long 0x690 31. "DISTRIBUTOR__37_GICD_IROUTER754_LOWER__31_1," "0,1" hexmask.long.byte 0x690 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER754_LOWER__8_8," newline hexmask.long.byte 0x690 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER754_LOWER__0_8," line.long 0x694 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER754_upper,Interrupt Routing Registers" line.long 0x698 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER755_lower,Interrupt Routing Registers" bitfld.long 0x698 31. "DISTRIBUTOR__37_GICD_IROUTER755_LOWER__31_1," "0,1" hexmask.long.byte 0x698 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER755_LOWER__8_8," newline hexmask.long.byte 0x698 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER755_LOWER__0_8," line.long 0x69C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER755_upper,Interrupt Routing Registers" line.long 0x6A0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER756_lower,Interrupt Routing Registers" bitfld.long 0x6A0 31. "DISTRIBUTOR__37_GICD_IROUTER756_LOWER__31_1," "0,1" hexmask.long.byte 0x6A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER756_LOWER__8_8," newline hexmask.long.byte 0x6A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER756_LOWER__0_8," line.long 0x6A4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER756_upper,Interrupt Routing Registers" line.long 0x6A8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER757_lower,Interrupt Routing Registers" bitfld.long 0x6A8 31. "DISTRIBUTOR__37_GICD_IROUTER757_LOWER__31_1," "0,1" hexmask.long.byte 0x6A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER757_LOWER__8_8," newline hexmask.long.byte 0x6A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER757_LOWER__0_8," line.long 0x6AC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER757_upper,Interrupt Routing Registers" line.long 0x6B0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER758_lower,Interrupt Routing Registers" bitfld.long 0x6B0 31. "DISTRIBUTOR__37_GICD_IROUTER758_LOWER__31_1," "0,1" hexmask.long.byte 0x6B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER758_LOWER__8_8," newline hexmask.long.byte 0x6B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER758_LOWER__0_8," line.long 0x6B4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER758_upper,Interrupt Routing Registers" line.long 0x6B8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER759_lower,Interrupt Routing Registers" bitfld.long 0x6B8 31. "DISTRIBUTOR__37_GICD_IROUTER759_LOWER__31_1," "0,1" hexmask.long.byte 0x6B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER759_LOWER__8_8," newline hexmask.long.byte 0x6B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER759_LOWER__0_8," line.long 0x6BC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER759_upper,Interrupt Routing Registers" line.long 0x6C0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER760_lower,Interrupt Routing Registers" bitfld.long 0x6C0 31. "DISTRIBUTOR__37_GICD_IROUTER760_LOWER__31_1," "0,1" hexmask.long.byte 0x6C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER760_LOWER__8_8," newline hexmask.long.byte 0x6C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER760_LOWER__0_8," line.long 0x6C4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER760_upper,Interrupt Routing Registers" line.long 0x6C8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER761_lower,Interrupt Routing Registers" bitfld.long 0x6C8 31. "DISTRIBUTOR__37_GICD_IROUTER761_LOWER__31_1," "0,1" hexmask.long.byte 0x6C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER761_LOWER__8_8," newline hexmask.long.byte 0x6C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER761_LOWER__0_8," line.long 0x6CC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER761_upper,Interrupt Routing Registers" line.long 0x6D0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER762_lower,Interrupt Routing Registers" bitfld.long 0x6D0 31. "DISTRIBUTOR__37_GICD_IROUTER762_LOWER__31_1," "0,1" hexmask.long.byte 0x6D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER762_LOWER__8_8," newline hexmask.long.byte 0x6D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER762_LOWER__0_8," line.long 0x6D4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER762_upper,Interrupt Routing Registers" line.long 0x6D8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER763_lower,Interrupt Routing Registers" bitfld.long 0x6D8 31. "DISTRIBUTOR__37_GICD_IROUTER763_LOWER__31_1," "0,1" hexmask.long.byte 0x6D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER763_LOWER__8_8," newline hexmask.long.byte 0x6D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER763_LOWER__0_8," line.long 0x6DC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER763_upper,Interrupt Routing Registers" line.long 0x6E0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER764_lower,Interrupt Routing Registers" bitfld.long 0x6E0 31. "DISTRIBUTOR__37_GICD_IROUTER764_LOWER__31_1," "0,1" hexmask.long.byte 0x6E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER764_LOWER__8_8," newline hexmask.long.byte 0x6E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER764_LOWER__0_8," line.long 0x6E4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER764_upper,Interrupt Routing Registers" line.long 0x6E8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER765_lower,Interrupt Routing Registers" bitfld.long 0x6E8 31. "DISTRIBUTOR__37_GICD_IROUTER765_LOWER__31_1," "0,1" hexmask.long.byte 0x6E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER765_LOWER__8_8," newline hexmask.long.byte 0x6E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER765_LOWER__0_8," line.long 0x6EC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER765_upper,Interrupt Routing Registers" line.long 0x6F0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER766_lower,Interrupt Routing Registers" bitfld.long 0x6F0 31. "DISTRIBUTOR__37_GICD_IROUTER766_LOWER__31_1," "0,1" hexmask.long.byte 0x6F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER766_LOWER__8_8," newline hexmask.long.byte 0x6F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER766_LOWER__0_8," line.long 0x6F4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER766_upper,Interrupt Routing Registers" line.long 0x6F8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER767_lower,Interrupt Routing Registers" bitfld.long 0x6F8 31. "DISTRIBUTOR__37_GICD_IROUTER767_LOWER__31_1," "0,1" hexmask.long.byte 0x6F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER767_LOWER__8_8," newline hexmask.long.byte 0x6F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER767_LOWER__0_8," line.long 0x6FC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER767_upper,Interrupt Routing Registers" line.long 0x700 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER768_lower,Interrupt Routing Registers" bitfld.long 0x700 31. "DISTRIBUTOR__37_GICD_IROUTER768_LOWER__31_1," "0,1" hexmask.long.byte 0x700 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER768_LOWER__8_8," newline hexmask.long.byte 0x700 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER768_LOWER__0_8," line.long 0x704 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER768_upper,Interrupt Routing Registers" line.long 0x708 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER769_lower,Interrupt Routing Registers" bitfld.long 0x708 31. "DISTRIBUTOR__37_GICD_IROUTER769_LOWER__31_1," "0,1" hexmask.long.byte 0x708 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER769_LOWER__8_8," newline hexmask.long.byte 0x708 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER769_LOWER__0_8," line.long 0x70C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER769_upper,Interrupt Routing Registers" line.long 0x710 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER770_lower,Interrupt Routing Registers" bitfld.long 0x710 31. "DISTRIBUTOR__37_GICD_IROUTER770_LOWER__31_1," "0,1" hexmask.long.byte 0x710 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER770_LOWER__8_8," newline hexmask.long.byte 0x710 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER770_LOWER__0_8," line.long 0x714 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER770_upper,Interrupt Routing Registers" line.long 0x718 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER771_lower,Interrupt Routing Registers" bitfld.long 0x718 31. "DISTRIBUTOR__37_GICD_IROUTER771_LOWER__31_1," "0,1" hexmask.long.byte 0x718 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER771_LOWER__8_8," newline hexmask.long.byte 0x718 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER771_LOWER__0_8," line.long 0x71C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER771_upper,Interrupt Routing Registers" line.long 0x720 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER772_lower,Interrupt Routing Registers" bitfld.long 0x720 31. "DISTRIBUTOR__37_GICD_IROUTER772_LOWER__31_1," "0,1" hexmask.long.byte 0x720 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER772_LOWER__8_8," newline hexmask.long.byte 0x720 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER772_LOWER__0_8," line.long 0x724 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER772_upper,Interrupt Routing Registers" line.long 0x728 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER773_lower,Interrupt Routing Registers" bitfld.long 0x728 31. "DISTRIBUTOR__37_GICD_IROUTER773_LOWER__31_1," "0,1" hexmask.long.byte 0x728 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER773_LOWER__8_8," newline hexmask.long.byte 0x728 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER773_LOWER__0_8," line.long 0x72C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER773_upper,Interrupt Routing Registers" line.long 0x730 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER774_lower,Interrupt Routing Registers" bitfld.long 0x730 31. "DISTRIBUTOR__37_GICD_IROUTER774_LOWER__31_1," "0,1" hexmask.long.byte 0x730 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER774_LOWER__8_8," newline hexmask.long.byte 0x730 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER774_LOWER__0_8," line.long 0x734 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER774_upper,Interrupt Routing Registers" line.long 0x738 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER775_lower,Interrupt Routing Registers" bitfld.long 0x738 31. "DISTRIBUTOR__37_GICD_IROUTER775_LOWER__31_1," "0,1" hexmask.long.byte 0x738 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER775_LOWER__8_8," newline hexmask.long.byte 0x738 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER775_LOWER__0_8," line.long 0x73C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER775_upper,Interrupt Routing Registers" line.long 0x740 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER776_lower,Interrupt Routing Registers" bitfld.long 0x740 31. "DISTRIBUTOR__37_GICD_IROUTER776_LOWER__31_1," "0,1" hexmask.long.byte 0x740 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER776_LOWER__8_8," newline hexmask.long.byte 0x740 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER776_LOWER__0_8," line.long 0x744 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER776_upper,Interrupt Routing Registers" line.long 0x748 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER777_lower,Interrupt Routing Registers" bitfld.long 0x748 31. "DISTRIBUTOR__37_GICD_IROUTER777_LOWER__31_1," "0,1" hexmask.long.byte 0x748 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER777_LOWER__8_8," newline hexmask.long.byte 0x748 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER777_LOWER__0_8," line.long 0x74C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER777_upper,Interrupt Routing Registers" line.long 0x750 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER778_lower,Interrupt Routing Registers" bitfld.long 0x750 31. "DISTRIBUTOR__37_GICD_IROUTER778_LOWER__31_1," "0,1" hexmask.long.byte 0x750 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER778_LOWER__8_8," newline hexmask.long.byte 0x750 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER778_LOWER__0_8," line.long 0x754 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER778_upper,Interrupt Routing Registers" line.long 0x758 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER779_lower,Interrupt Routing Registers" bitfld.long 0x758 31. "DISTRIBUTOR__37_GICD_IROUTER779_LOWER__31_1," "0,1" hexmask.long.byte 0x758 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER779_LOWER__8_8," newline hexmask.long.byte 0x758 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER779_LOWER__0_8," line.long 0x75C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER779_upper,Interrupt Routing Registers" line.long 0x760 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER780_lower,Interrupt Routing Registers" bitfld.long 0x760 31. "DISTRIBUTOR__37_GICD_IROUTER780_LOWER__31_1," "0,1" hexmask.long.byte 0x760 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER780_LOWER__8_8," newline hexmask.long.byte 0x760 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER780_LOWER__0_8," line.long 0x764 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER780_upper,Interrupt Routing Registers" line.long 0x768 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER781_lower,Interrupt Routing Registers" bitfld.long 0x768 31. "DISTRIBUTOR__37_GICD_IROUTER781_LOWER__31_1," "0,1" hexmask.long.byte 0x768 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER781_LOWER__8_8," newline hexmask.long.byte 0x768 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER781_LOWER__0_8," line.long 0x76C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER781_upper,Interrupt Routing Registers" line.long 0x770 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER782_lower,Interrupt Routing Registers" bitfld.long 0x770 31. "DISTRIBUTOR__37_GICD_IROUTER782_LOWER__31_1," "0,1" hexmask.long.byte 0x770 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER782_LOWER__8_8," newline hexmask.long.byte 0x770 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER782_LOWER__0_8," line.long 0x774 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER782_upper,Interrupt Routing Registers" line.long 0x778 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER783_lower,Interrupt Routing Registers" bitfld.long 0x778 31. "DISTRIBUTOR__37_GICD_IROUTER783_LOWER__31_1," "0,1" hexmask.long.byte 0x778 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER783_LOWER__8_8," newline hexmask.long.byte 0x778 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER783_LOWER__0_8," line.long 0x77C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER783_upper,Interrupt Routing Registers" line.long 0x780 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER784_lower,Interrupt Routing Registers" bitfld.long 0x780 31. "DISTRIBUTOR__37_GICD_IROUTER784_LOWER__31_1," "0,1" hexmask.long.byte 0x780 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER784_LOWER__8_8," newline hexmask.long.byte 0x780 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER784_LOWER__0_8," line.long 0x784 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER784_upper,Interrupt Routing Registers" line.long 0x788 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER785_lower,Interrupt Routing Registers" bitfld.long 0x788 31. "DISTRIBUTOR__37_GICD_IROUTER785_LOWER__31_1," "0,1" hexmask.long.byte 0x788 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER785_LOWER__8_8," newline hexmask.long.byte 0x788 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER785_LOWER__0_8," line.long 0x78C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER785_upper,Interrupt Routing Registers" line.long 0x790 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER786_lower,Interrupt Routing Registers" bitfld.long 0x790 31. "DISTRIBUTOR__37_GICD_IROUTER786_LOWER__31_1," "0,1" hexmask.long.byte 0x790 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER786_LOWER__8_8," newline hexmask.long.byte 0x790 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER786_LOWER__0_8," line.long 0x794 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER786_upper,Interrupt Routing Registers" line.long 0x798 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER787_lower,Interrupt Routing Registers" bitfld.long 0x798 31. "DISTRIBUTOR__37_GICD_IROUTER787_LOWER__31_1," "0,1" hexmask.long.byte 0x798 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER787_LOWER__8_8," newline hexmask.long.byte 0x798 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER787_LOWER__0_8," line.long 0x79C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER787_upper,Interrupt Routing Registers" line.long 0x7A0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER788_lower,Interrupt Routing Registers" bitfld.long 0x7A0 31. "DISTRIBUTOR__37_GICD_IROUTER788_LOWER__31_1," "0,1" hexmask.long.byte 0x7A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER788_LOWER__8_8," newline hexmask.long.byte 0x7A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER788_LOWER__0_8," line.long 0x7A4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER788_upper,Interrupt Routing Registers" line.long 0x7A8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER789_lower,Interrupt Routing Registers" bitfld.long 0x7A8 31. "DISTRIBUTOR__37_GICD_IROUTER789_LOWER__31_1," "0,1" hexmask.long.byte 0x7A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER789_LOWER__8_8," newline hexmask.long.byte 0x7A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER789_LOWER__0_8," line.long 0x7AC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER789_upper,Interrupt Routing Registers" line.long 0x7B0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER790_lower,Interrupt Routing Registers" bitfld.long 0x7B0 31. "DISTRIBUTOR__37_GICD_IROUTER790_LOWER__31_1," "0,1" hexmask.long.byte 0x7B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER790_LOWER__8_8," newline hexmask.long.byte 0x7B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER790_LOWER__0_8," line.long 0x7B4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER790_upper,Interrupt Routing Registers" line.long 0x7B8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER791_lower,Interrupt Routing Registers" bitfld.long 0x7B8 31. "DISTRIBUTOR__37_GICD_IROUTER791_LOWER__31_1," "0,1" hexmask.long.byte 0x7B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER791_LOWER__8_8," newline hexmask.long.byte 0x7B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER791_LOWER__0_8," line.long 0x7BC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER791_upper,Interrupt Routing Registers" line.long 0x7C0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER792_lower,Interrupt Routing Registers" bitfld.long 0x7C0 31. "DISTRIBUTOR__37_GICD_IROUTER792_LOWER__31_1," "0,1" hexmask.long.byte 0x7C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER792_LOWER__8_8," newline hexmask.long.byte 0x7C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER792_LOWER__0_8," line.long 0x7C4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER792_upper,Interrupt Routing Registers" line.long 0x7C8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER793_lower,Interrupt Routing Registers" bitfld.long 0x7C8 31. "DISTRIBUTOR__37_GICD_IROUTER793_LOWER__31_1," "0,1" hexmask.long.byte 0x7C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER793_LOWER__8_8," newline hexmask.long.byte 0x7C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER793_LOWER__0_8," line.long 0x7CC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER793_upper,Interrupt Routing Registers" line.long 0x7D0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER794_lower,Interrupt Routing Registers" bitfld.long 0x7D0 31. "DISTRIBUTOR__37_GICD_IROUTER794_LOWER__31_1," "0,1" hexmask.long.byte 0x7D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER794_LOWER__8_8," newline hexmask.long.byte 0x7D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER794_LOWER__0_8," line.long 0x7D4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER794_upper,Interrupt Routing Registers" line.long 0x7D8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER795_lower,Interrupt Routing Registers" bitfld.long 0x7D8 31. "DISTRIBUTOR__37_GICD_IROUTER795_LOWER__31_1," "0,1" hexmask.long.byte 0x7D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER795_LOWER__8_8," newline hexmask.long.byte 0x7D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER795_LOWER__0_8," line.long 0x7DC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER795_upper,Interrupt Routing Registers" line.long 0x7E0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER796_lower,Interrupt Routing Registers" bitfld.long 0x7E0 31. "DISTRIBUTOR__37_GICD_IROUTER796_LOWER__31_1," "0,1" hexmask.long.byte 0x7E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER796_LOWER__8_8," newline hexmask.long.byte 0x7E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER796_LOWER__0_8," line.long 0x7E4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER796_upper,Interrupt Routing Registers" line.long 0x7E8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER797_lower,Interrupt Routing Registers" bitfld.long 0x7E8 31. "DISTRIBUTOR__37_GICD_IROUTER797_LOWER__31_1," "0,1" hexmask.long.byte 0x7E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER797_LOWER__8_8," newline hexmask.long.byte 0x7E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER797_LOWER__0_8," line.long 0x7EC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER797_upper,Interrupt Routing Registers" line.long 0x7F0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER798_lower,Interrupt Routing Registers" bitfld.long 0x7F0 31. "DISTRIBUTOR__37_GICD_IROUTER798_LOWER__31_1," "0,1" hexmask.long.byte 0x7F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER798_LOWER__8_8," newline hexmask.long.byte 0x7F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER798_LOWER__0_8," line.long 0x7F4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER798_upper,Interrupt Routing Registers" line.long 0x7F8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER799_lower,Interrupt Routing Registers" bitfld.long 0x7F8 31. "DISTRIBUTOR__37_GICD_IROUTER799_LOWER__31_1," "0,1" hexmask.long.byte 0x7F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER799_LOWER__8_8," newline hexmask.long.byte 0x7F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER799_LOWER__0_8," line.long 0x7FC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER799_upper,Interrupt Routing Registers" line.long 0x800 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER800_lower,Interrupt Routing Registers" bitfld.long 0x800 31. "DISTRIBUTOR__37_GICD_IROUTER800_LOWER__31_1," "0,1" hexmask.long.byte 0x800 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER800_LOWER__8_8," newline hexmask.long.byte 0x800 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER800_LOWER__0_8," line.long 0x804 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER800_upper,Interrupt Routing Registers" line.long 0x808 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER801_lower,Interrupt Routing Registers" bitfld.long 0x808 31. "DISTRIBUTOR__37_GICD_IROUTER801_LOWER__31_1," "0,1" hexmask.long.byte 0x808 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER801_LOWER__8_8," newline hexmask.long.byte 0x808 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER801_LOWER__0_8," line.long 0x80C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER801_upper,Interrupt Routing Registers" line.long 0x810 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER802_lower,Interrupt Routing Registers" bitfld.long 0x810 31. "DISTRIBUTOR__37_GICD_IROUTER802_LOWER__31_1," "0,1" hexmask.long.byte 0x810 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER802_LOWER__8_8," newline hexmask.long.byte 0x810 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER802_LOWER__0_8," line.long 0x814 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER802_upper,Interrupt Routing Registers" line.long 0x818 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER803_lower,Interrupt Routing Registers" bitfld.long 0x818 31. "DISTRIBUTOR__37_GICD_IROUTER803_LOWER__31_1," "0,1" hexmask.long.byte 0x818 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER803_LOWER__8_8," newline hexmask.long.byte 0x818 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER803_LOWER__0_8," line.long 0x81C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER803_upper,Interrupt Routing Registers" line.long 0x820 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER804_lower,Interrupt Routing Registers" bitfld.long 0x820 31. "DISTRIBUTOR__37_GICD_IROUTER804_LOWER__31_1," "0,1" hexmask.long.byte 0x820 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER804_LOWER__8_8," newline hexmask.long.byte 0x820 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER804_LOWER__0_8," line.long 0x824 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER804_upper,Interrupt Routing Registers" line.long 0x828 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER805_lower,Interrupt Routing Registers" bitfld.long 0x828 31. "DISTRIBUTOR__37_GICD_IROUTER805_LOWER__31_1," "0,1" hexmask.long.byte 0x828 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER805_LOWER__8_8," newline hexmask.long.byte 0x828 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER805_LOWER__0_8," line.long 0x82C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER805_upper,Interrupt Routing Registers" line.long 0x830 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER806_lower,Interrupt Routing Registers" bitfld.long 0x830 31. "DISTRIBUTOR__37_GICD_IROUTER806_LOWER__31_1," "0,1" hexmask.long.byte 0x830 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER806_LOWER__8_8," newline hexmask.long.byte 0x830 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER806_LOWER__0_8," line.long 0x834 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER806_upper,Interrupt Routing Registers" line.long 0x838 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER807_lower,Interrupt Routing Registers" bitfld.long 0x838 31. "DISTRIBUTOR__37_GICD_IROUTER807_LOWER__31_1," "0,1" hexmask.long.byte 0x838 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER807_LOWER__8_8," newline hexmask.long.byte 0x838 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER807_LOWER__0_8," line.long 0x83C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER807_upper,Interrupt Routing Registers" line.long 0x840 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER808_lower,Interrupt Routing Registers" bitfld.long 0x840 31. "DISTRIBUTOR__37_GICD_IROUTER808_LOWER__31_1," "0,1" hexmask.long.byte 0x840 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER808_LOWER__8_8," newline hexmask.long.byte 0x840 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER808_LOWER__0_8," line.long 0x844 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER808_upper,Interrupt Routing Registers" line.long 0x848 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER809_lower,Interrupt Routing Registers" bitfld.long 0x848 31. "DISTRIBUTOR__37_GICD_IROUTER809_LOWER__31_1," "0,1" hexmask.long.byte 0x848 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER809_LOWER__8_8," newline hexmask.long.byte 0x848 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER809_LOWER__0_8," line.long 0x84C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER809_upper,Interrupt Routing Registers" line.long 0x850 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER810_lower,Interrupt Routing Registers" bitfld.long 0x850 31. "DISTRIBUTOR__37_GICD_IROUTER810_LOWER__31_1," "0,1" hexmask.long.byte 0x850 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER810_LOWER__8_8," newline hexmask.long.byte 0x850 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER810_LOWER__0_8," line.long 0x854 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER810_upper,Interrupt Routing Registers" line.long 0x858 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER811_lower,Interrupt Routing Registers" bitfld.long 0x858 31. "DISTRIBUTOR__37_GICD_IROUTER811_LOWER__31_1," "0,1" hexmask.long.byte 0x858 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER811_LOWER__8_8," newline hexmask.long.byte 0x858 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER811_LOWER__0_8," line.long 0x85C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER811_upper,Interrupt Routing Registers" line.long 0x860 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER812_lower,Interrupt Routing Registers" bitfld.long 0x860 31. "DISTRIBUTOR__37_GICD_IROUTER812_LOWER__31_1," "0,1" hexmask.long.byte 0x860 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER812_LOWER__8_8," newline hexmask.long.byte 0x860 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER812_LOWER__0_8," line.long 0x864 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER812_upper,Interrupt Routing Registers" line.long 0x868 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER813_lower,Interrupt Routing Registers" bitfld.long 0x868 31. "DISTRIBUTOR__37_GICD_IROUTER813_LOWER__31_1," "0,1" hexmask.long.byte 0x868 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER813_LOWER__8_8," newline hexmask.long.byte 0x868 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER813_LOWER__0_8," line.long 0x86C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER813_upper,Interrupt Routing Registers" line.long 0x870 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER814_lower,Interrupt Routing Registers" bitfld.long 0x870 31. "DISTRIBUTOR__37_GICD_IROUTER814_LOWER__31_1," "0,1" hexmask.long.byte 0x870 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER814_LOWER__8_8," newline hexmask.long.byte 0x870 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER814_LOWER__0_8," line.long 0x874 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER814_upper,Interrupt Routing Registers" line.long 0x878 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER815_lower,Interrupt Routing Registers" bitfld.long 0x878 31. "DISTRIBUTOR__37_GICD_IROUTER815_LOWER__31_1," "0,1" hexmask.long.byte 0x878 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER815_LOWER__8_8," newline hexmask.long.byte 0x878 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER815_LOWER__0_8," line.long 0x87C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER815_upper,Interrupt Routing Registers" line.long 0x880 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER816_lower,Interrupt Routing Registers" bitfld.long 0x880 31. "DISTRIBUTOR__37_GICD_IROUTER816_LOWER__31_1," "0,1" hexmask.long.byte 0x880 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER816_LOWER__8_8," newline hexmask.long.byte 0x880 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER816_LOWER__0_8," line.long 0x884 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER816_upper,Interrupt Routing Registers" line.long 0x888 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER817_lower,Interrupt Routing Registers" bitfld.long 0x888 31. "DISTRIBUTOR__37_GICD_IROUTER817_LOWER__31_1," "0,1" hexmask.long.byte 0x888 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER817_LOWER__8_8," newline hexmask.long.byte 0x888 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER817_LOWER__0_8," line.long 0x88C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER817_upper,Interrupt Routing Registers" line.long 0x890 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER818_lower,Interrupt Routing Registers" bitfld.long 0x890 31. "DISTRIBUTOR__37_GICD_IROUTER818_LOWER__31_1," "0,1" hexmask.long.byte 0x890 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER818_LOWER__8_8," newline hexmask.long.byte 0x890 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER818_LOWER__0_8," line.long 0x894 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER818_upper,Interrupt Routing Registers" line.long 0x898 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER819_lower,Interrupt Routing Registers" bitfld.long 0x898 31. "DISTRIBUTOR__37_GICD_IROUTER819_LOWER__31_1," "0,1" hexmask.long.byte 0x898 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER819_LOWER__8_8," newline hexmask.long.byte 0x898 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER819_LOWER__0_8," line.long 0x89C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER819_upper,Interrupt Routing Registers" line.long 0x8A0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER820_lower,Interrupt Routing Registers" bitfld.long 0x8A0 31. "DISTRIBUTOR__37_GICD_IROUTER820_LOWER__31_1," "0,1" hexmask.long.byte 0x8A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER820_LOWER__8_8," newline hexmask.long.byte 0x8A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER820_LOWER__0_8," line.long 0x8A4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER820_upper,Interrupt Routing Registers" line.long 0x8A8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER821_lower,Interrupt Routing Registers" bitfld.long 0x8A8 31. "DISTRIBUTOR__37_GICD_IROUTER821_LOWER__31_1," "0,1" hexmask.long.byte 0x8A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER821_LOWER__8_8," newline hexmask.long.byte 0x8A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER821_LOWER__0_8," line.long 0x8AC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER821_upper,Interrupt Routing Registers" line.long 0x8B0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER822_lower,Interrupt Routing Registers" bitfld.long 0x8B0 31. "DISTRIBUTOR__37_GICD_IROUTER822_LOWER__31_1," "0,1" hexmask.long.byte 0x8B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER822_LOWER__8_8," newline hexmask.long.byte 0x8B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER822_LOWER__0_8," line.long 0x8B4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER822_upper,Interrupt Routing Registers" line.long 0x8B8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER823_lower,Interrupt Routing Registers" bitfld.long 0x8B8 31. "DISTRIBUTOR__37_GICD_IROUTER823_LOWER__31_1," "0,1" hexmask.long.byte 0x8B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER823_LOWER__8_8," newline hexmask.long.byte 0x8B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER823_LOWER__0_8," line.long 0x8BC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER823_upper,Interrupt Routing Registers" line.long 0x8C0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER824_lower,Interrupt Routing Registers" bitfld.long 0x8C0 31. "DISTRIBUTOR__37_GICD_IROUTER824_LOWER__31_1," "0,1" hexmask.long.byte 0x8C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER824_LOWER__8_8," newline hexmask.long.byte 0x8C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER824_LOWER__0_8," line.long 0x8C4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER824_upper,Interrupt Routing Registers" line.long 0x8C8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER825_lower,Interrupt Routing Registers" bitfld.long 0x8C8 31. "DISTRIBUTOR__37_GICD_IROUTER825_LOWER__31_1," "0,1" hexmask.long.byte 0x8C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER825_LOWER__8_8," newline hexmask.long.byte 0x8C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER825_LOWER__0_8," line.long 0x8CC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER825_upper,Interrupt Routing Registers" line.long 0x8D0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER826_lower,Interrupt Routing Registers" bitfld.long 0x8D0 31. "DISTRIBUTOR__37_GICD_IROUTER826_LOWER__31_1," "0,1" hexmask.long.byte 0x8D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER826_LOWER__8_8," newline hexmask.long.byte 0x8D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER826_LOWER__0_8," line.long 0x8D4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER826_upper,Interrupt Routing Registers" line.long 0x8D8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER827_lower,Interrupt Routing Registers" bitfld.long 0x8D8 31. "DISTRIBUTOR__37_GICD_IROUTER827_LOWER__31_1," "0,1" hexmask.long.byte 0x8D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER827_LOWER__8_8," newline hexmask.long.byte 0x8D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER827_LOWER__0_8," line.long 0x8DC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER827_upper,Interrupt Routing Registers" line.long 0x8E0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER828_lower,Interrupt Routing Registers" bitfld.long 0x8E0 31. "DISTRIBUTOR__37_GICD_IROUTER828_LOWER__31_1," "0,1" hexmask.long.byte 0x8E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER828_LOWER__8_8," newline hexmask.long.byte 0x8E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER828_LOWER__0_8," line.long 0x8E4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER828_upper,Interrupt Routing Registers" line.long 0x8E8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER829_lower,Interrupt Routing Registers" bitfld.long 0x8E8 31. "DISTRIBUTOR__37_GICD_IROUTER829_LOWER__31_1," "0,1" hexmask.long.byte 0x8E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER829_LOWER__8_8," newline hexmask.long.byte 0x8E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER829_LOWER__0_8," line.long 0x8EC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER829_upper,Interrupt Routing Registers" line.long 0x8F0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER830_lower,Interrupt Routing Registers" bitfld.long 0x8F0 31. "DISTRIBUTOR__37_GICD_IROUTER830_LOWER__31_1," "0,1" hexmask.long.byte 0x8F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER830_LOWER__8_8," newline hexmask.long.byte 0x8F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER830_LOWER__0_8," line.long 0x8F4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER830_upper,Interrupt Routing Registers" line.long 0x8F8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER831_lower,Interrupt Routing Registers" bitfld.long 0x8F8 31. "DISTRIBUTOR__37_GICD_IROUTER831_LOWER__31_1," "0,1" hexmask.long.byte 0x8F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER831_LOWER__8_8," newline hexmask.long.byte 0x8F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER831_LOWER__0_8," line.long 0x8FC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER831_upper,Interrupt Routing Registers" line.long 0x900 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER832_lower,Interrupt Routing Registers" bitfld.long 0x900 31. "DISTRIBUTOR__37_GICD_IROUTER832_LOWER__31_1," "0,1" hexmask.long.byte 0x900 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER832_LOWER__8_8," newline hexmask.long.byte 0x900 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER832_LOWER__0_8," line.long 0x904 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER832_upper,Interrupt Routing Registers" line.long 0x908 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER833_lower,Interrupt Routing Registers" bitfld.long 0x908 31. "DISTRIBUTOR__37_GICD_IROUTER833_LOWER__31_1," "0,1" hexmask.long.byte 0x908 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER833_LOWER__8_8," newline hexmask.long.byte 0x908 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER833_LOWER__0_8," line.long 0x90C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER833_upper,Interrupt Routing Registers" line.long 0x910 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER834_lower,Interrupt Routing Registers" bitfld.long 0x910 31. "DISTRIBUTOR__37_GICD_IROUTER834_LOWER__31_1," "0,1" hexmask.long.byte 0x910 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER834_LOWER__8_8," newline hexmask.long.byte 0x910 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER834_LOWER__0_8," line.long 0x914 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER834_upper,Interrupt Routing Registers" line.long 0x918 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER835_lower,Interrupt Routing Registers" bitfld.long 0x918 31. "DISTRIBUTOR__37_GICD_IROUTER835_LOWER__31_1," "0,1" hexmask.long.byte 0x918 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER835_LOWER__8_8," newline hexmask.long.byte 0x918 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER835_LOWER__0_8," line.long 0x91C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER835_upper,Interrupt Routing Registers" line.long 0x920 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER836_lower,Interrupt Routing Registers" bitfld.long 0x920 31. "DISTRIBUTOR__37_GICD_IROUTER836_LOWER__31_1," "0,1" hexmask.long.byte 0x920 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER836_LOWER__8_8," newline hexmask.long.byte 0x920 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER836_LOWER__0_8," line.long 0x924 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER836_upper,Interrupt Routing Registers" line.long 0x928 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER837_lower,Interrupt Routing Registers" bitfld.long 0x928 31. "DISTRIBUTOR__37_GICD_IROUTER837_LOWER__31_1," "0,1" hexmask.long.byte 0x928 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER837_LOWER__8_8," newline hexmask.long.byte 0x928 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER837_LOWER__0_8," line.long 0x92C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER837_upper,Interrupt Routing Registers" line.long 0x930 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER838_lower,Interrupt Routing Registers" bitfld.long 0x930 31. "DISTRIBUTOR__37_GICD_IROUTER838_LOWER__31_1," "0,1" hexmask.long.byte 0x930 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER838_LOWER__8_8," newline hexmask.long.byte 0x930 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER838_LOWER__0_8," line.long 0x934 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER838_upper,Interrupt Routing Registers" line.long 0x938 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER839_lower,Interrupt Routing Registers" bitfld.long 0x938 31. "DISTRIBUTOR__37_GICD_IROUTER839_LOWER__31_1," "0,1" hexmask.long.byte 0x938 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER839_LOWER__8_8," newline hexmask.long.byte 0x938 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER839_LOWER__0_8," line.long 0x93C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER839_upper,Interrupt Routing Registers" line.long 0x940 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER840_lower,Interrupt Routing Registers" bitfld.long 0x940 31. "DISTRIBUTOR__37_GICD_IROUTER840_LOWER__31_1," "0,1" hexmask.long.byte 0x940 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER840_LOWER__8_8," newline hexmask.long.byte 0x940 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER840_LOWER__0_8," line.long 0x944 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER840_upper,Interrupt Routing Registers" line.long 0x948 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER841_lower,Interrupt Routing Registers" bitfld.long 0x948 31. "DISTRIBUTOR__37_GICD_IROUTER841_LOWER__31_1," "0,1" hexmask.long.byte 0x948 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER841_LOWER__8_8," newline hexmask.long.byte 0x948 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER841_LOWER__0_8," line.long 0x94C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER841_upper,Interrupt Routing Registers" line.long 0x950 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER842_lower,Interrupt Routing Registers" bitfld.long 0x950 31. "DISTRIBUTOR__37_GICD_IROUTER842_LOWER__31_1," "0,1" hexmask.long.byte 0x950 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER842_LOWER__8_8," newline hexmask.long.byte 0x950 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER842_LOWER__0_8," line.long 0x954 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER842_upper,Interrupt Routing Registers" line.long 0x958 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER843_lower,Interrupt Routing Registers" bitfld.long 0x958 31. "DISTRIBUTOR__37_GICD_IROUTER843_LOWER__31_1," "0,1" hexmask.long.byte 0x958 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER843_LOWER__8_8," newline hexmask.long.byte 0x958 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER843_LOWER__0_8," line.long 0x95C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER843_upper,Interrupt Routing Registers" line.long 0x960 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER844_lower,Interrupt Routing Registers" bitfld.long 0x960 31. "DISTRIBUTOR__37_GICD_IROUTER844_LOWER__31_1," "0,1" hexmask.long.byte 0x960 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER844_LOWER__8_8," newline hexmask.long.byte 0x960 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER844_LOWER__0_8," line.long 0x964 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER844_upper,Interrupt Routing Registers" line.long 0x968 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER845_lower,Interrupt Routing Registers" bitfld.long 0x968 31. "DISTRIBUTOR__37_GICD_IROUTER845_LOWER__31_1," "0,1" hexmask.long.byte 0x968 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER845_LOWER__8_8," newline hexmask.long.byte 0x968 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER845_LOWER__0_8," line.long 0x96C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER845_upper,Interrupt Routing Registers" line.long 0x970 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER846_lower,Interrupt Routing Registers" bitfld.long 0x970 31. "DISTRIBUTOR__37_GICD_IROUTER846_LOWER__31_1," "0,1" hexmask.long.byte 0x970 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER846_LOWER__8_8," newline hexmask.long.byte 0x970 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER846_LOWER__0_8," line.long 0x974 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER846_upper,Interrupt Routing Registers" line.long 0x978 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER847_lower,Interrupt Routing Registers" bitfld.long 0x978 31. "DISTRIBUTOR__37_GICD_IROUTER847_LOWER__31_1," "0,1" hexmask.long.byte 0x978 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER847_LOWER__8_8," newline hexmask.long.byte 0x978 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER847_LOWER__0_8," line.long 0x97C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER847_upper,Interrupt Routing Registers" line.long 0x980 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER848_lower,Interrupt Routing Registers" bitfld.long 0x980 31. "DISTRIBUTOR__37_GICD_IROUTER848_LOWER__31_1," "0,1" hexmask.long.byte 0x980 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER848_LOWER__8_8," newline hexmask.long.byte 0x980 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER848_LOWER__0_8," line.long 0x984 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER848_upper,Interrupt Routing Registers" line.long 0x988 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER849_lower,Interrupt Routing Registers" bitfld.long 0x988 31. "DISTRIBUTOR__37_GICD_IROUTER849_LOWER__31_1," "0,1" hexmask.long.byte 0x988 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER849_LOWER__8_8," newline hexmask.long.byte 0x988 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER849_LOWER__0_8," line.long 0x98C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER849_upper,Interrupt Routing Registers" line.long 0x990 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER850_lower,Interrupt Routing Registers" bitfld.long 0x990 31. "DISTRIBUTOR__37_GICD_IROUTER850_LOWER__31_1," "0,1" hexmask.long.byte 0x990 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER850_LOWER__8_8," newline hexmask.long.byte 0x990 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER850_LOWER__0_8," line.long 0x994 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER850_upper,Interrupt Routing Registers" line.long 0x998 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER851_lower,Interrupt Routing Registers" bitfld.long 0x998 31. "DISTRIBUTOR__37_GICD_IROUTER851_LOWER__31_1," "0,1" hexmask.long.byte 0x998 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER851_LOWER__8_8," newline hexmask.long.byte 0x998 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER851_LOWER__0_8," line.long 0x99C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER851_upper,Interrupt Routing Registers" line.long 0x9A0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER852_lower,Interrupt Routing Registers" bitfld.long 0x9A0 31. "DISTRIBUTOR__37_GICD_IROUTER852_LOWER__31_1," "0,1" hexmask.long.byte 0x9A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER852_LOWER__8_8," newline hexmask.long.byte 0x9A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER852_LOWER__0_8," line.long 0x9A4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER852_upper,Interrupt Routing Registers" line.long 0x9A8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER853_lower,Interrupt Routing Registers" bitfld.long 0x9A8 31. "DISTRIBUTOR__37_GICD_IROUTER853_LOWER__31_1," "0,1" hexmask.long.byte 0x9A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER853_LOWER__8_8," newline hexmask.long.byte 0x9A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER853_LOWER__0_8," line.long 0x9AC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER853_upper,Interrupt Routing Registers" line.long 0x9B0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER854_lower,Interrupt Routing Registers" bitfld.long 0x9B0 31. "DISTRIBUTOR__37_GICD_IROUTER854_LOWER__31_1," "0,1" hexmask.long.byte 0x9B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER854_LOWER__8_8," newline hexmask.long.byte 0x9B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER854_LOWER__0_8," line.long 0x9B4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER854_upper,Interrupt Routing Registers" line.long 0x9B8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER855_lower,Interrupt Routing Registers" bitfld.long 0x9B8 31. "DISTRIBUTOR__37_GICD_IROUTER855_LOWER__31_1," "0,1" hexmask.long.byte 0x9B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER855_LOWER__8_8," newline hexmask.long.byte 0x9B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER855_LOWER__0_8," line.long 0x9BC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER855_upper,Interrupt Routing Registers" line.long 0x9C0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER856_lower,Interrupt Routing Registers" bitfld.long 0x9C0 31. "DISTRIBUTOR__37_GICD_IROUTER856_LOWER__31_1," "0,1" hexmask.long.byte 0x9C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER856_LOWER__8_8," newline hexmask.long.byte 0x9C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER856_LOWER__0_8," line.long 0x9C4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER856_upper,Interrupt Routing Registers" line.long 0x9C8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER857_lower,Interrupt Routing Registers" bitfld.long 0x9C8 31. "DISTRIBUTOR__37_GICD_IROUTER857_LOWER__31_1," "0,1" hexmask.long.byte 0x9C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER857_LOWER__8_8," newline hexmask.long.byte 0x9C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER857_LOWER__0_8," line.long 0x9CC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER857_upper,Interrupt Routing Registers" line.long 0x9D0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER858_lower,Interrupt Routing Registers" bitfld.long 0x9D0 31. "DISTRIBUTOR__37_GICD_IROUTER858_LOWER__31_1," "0,1" hexmask.long.byte 0x9D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER858_LOWER__8_8," newline hexmask.long.byte 0x9D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER858_LOWER__0_8," line.long 0x9D4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER858_upper,Interrupt Routing Registers" line.long 0x9D8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER859_lower,Interrupt Routing Registers" bitfld.long 0x9D8 31. "DISTRIBUTOR__37_GICD_IROUTER859_LOWER__31_1," "0,1" hexmask.long.byte 0x9D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER859_LOWER__8_8," newline hexmask.long.byte 0x9D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER859_LOWER__0_8," line.long 0x9DC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER859_upper,Interrupt Routing Registers" line.long 0x9E0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER860_lower,Interrupt Routing Registers" bitfld.long 0x9E0 31. "DISTRIBUTOR__37_GICD_IROUTER860_LOWER__31_1," "0,1" hexmask.long.byte 0x9E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER860_LOWER__8_8," newline hexmask.long.byte 0x9E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER860_LOWER__0_8," line.long 0x9E4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER860_upper,Interrupt Routing Registers" line.long 0x9E8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER861_lower,Interrupt Routing Registers" bitfld.long 0x9E8 31. "DISTRIBUTOR__37_GICD_IROUTER861_LOWER__31_1," "0,1" hexmask.long.byte 0x9E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER861_LOWER__8_8," newline hexmask.long.byte 0x9E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER861_LOWER__0_8," line.long 0x9EC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER861_upper,Interrupt Routing Registers" line.long 0x9F0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER862_lower,Interrupt Routing Registers" bitfld.long 0x9F0 31. "DISTRIBUTOR__37_GICD_IROUTER862_LOWER__31_1," "0,1" hexmask.long.byte 0x9F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER862_LOWER__8_8," newline hexmask.long.byte 0x9F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER862_LOWER__0_8," line.long 0x9F4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER862_upper,Interrupt Routing Registers" line.long 0x9F8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER863_lower,Interrupt Routing Registers" bitfld.long 0x9F8 31. "DISTRIBUTOR__37_GICD_IROUTER863_LOWER__31_1," "0,1" hexmask.long.byte 0x9F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER863_LOWER__8_8," newline hexmask.long.byte 0x9F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER863_LOWER__0_8," line.long 0x9FC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER863_upper,Interrupt Routing Registers" line.long 0xA00 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER864_lower,Interrupt Routing Registers" bitfld.long 0xA00 31. "DISTRIBUTOR__37_GICD_IROUTER864_LOWER__31_1," "0,1" hexmask.long.byte 0xA00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER864_LOWER__8_8," newline hexmask.long.byte 0xA00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER864_LOWER__0_8," line.long 0xA04 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER864_upper,Interrupt Routing Registers" line.long 0xA08 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER865_lower,Interrupt Routing Registers" bitfld.long 0xA08 31. "DISTRIBUTOR__37_GICD_IROUTER865_LOWER__31_1," "0,1" hexmask.long.byte 0xA08 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER865_LOWER__8_8," newline hexmask.long.byte 0xA08 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER865_LOWER__0_8," line.long 0xA0C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER865_upper,Interrupt Routing Registers" line.long 0xA10 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER866_lower,Interrupt Routing Registers" bitfld.long 0xA10 31. "DISTRIBUTOR__37_GICD_IROUTER866_LOWER__31_1," "0,1" hexmask.long.byte 0xA10 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER866_LOWER__8_8," newline hexmask.long.byte 0xA10 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER866_LOWER__0_8," line.long 0xA14 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER866_upper,Interrupt Routing Registers" line.long 0xA18 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER867_lower,Interrupt Routing Registers" bitfld.long 0xA18 31. "DISTRIBUTOR__37_GICD_IROUTER867_LOWER__31_1," "0,1" hexmask.long.byte 0xA18 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER867_LOWER__8_8," newline hexmask.long.byte 0xA18 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER867_LOWER__0_8," line.long 0xA1C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER867_upper,Interrupt Routing Registers" line.long 0xA20 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER868_lower,Interrupt Routing Registers" bitfld.long 0xA20 31. "DISTRIBUTOR__37_GICD_IROUTER868_LOWER__31_1," "0,1" hexmask.long.byte 0xA20 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER868_LOWER__8_8," newline hexmask.long.byte 0xA20 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER868_LOWER__0_8," line.long 0xA24 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER868_upper,Interrupt Routing Registers" line.long 0xA28 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER869_lower,Interrupt Routing Registers" bitfld.long 0xA28 31. "DISTRIBUTOR__37_GICD_IROUTER869_LOWER__31_1," "0,1" hexmask.long.byte 0xA28 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER869_LOWER__8_8," newline hexmask.long.byte 0xA28 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER869_LOWER__0_8," line.long 0xA2C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER869_upper,Interrupt Routing Registers" line.long 0xA30 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER870_lower,Interrupt Routing Registers" bitfld.long 0xA30 31. "DISTRIBUTOR__37_GICD_IROUTER870_LOWER__31_1," "0,1" hexmask.long.byte 0xA30 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER870_LOWER__8_8," newline hexmask.long.byte 0xA30 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER870_LOWER__0_8," line.long 0xA34 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER870_upper,Interrupt Routing Registers" line.long 0xA38 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER871_lower,Interrupt Routing Registers" bitfld.long 0xA38 31. "DISTRIBUTOR__37_GICD_IROUTER871_LOWER__31_1," "0,1" hexmask.long.byte 0xA38 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER871_LOWER__8_8," newline hexmask.long.byte 0xA38 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER871_LOWER__0_8," line.long 0xA3C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER871_upper,Interrupt Routing Registers" line.long 0xA40 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER872_lower,Interrupt Routing Registers" bitfld.long 0xA40 31. "DISTRIBUTOR__37_GICD_IROUTER872_LOWER__31_1," "0,1" hexmask.long.byte 0xA40 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER872_LOWER__8_8," newline hexmask.long.byte 0xA40 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER872_LOWER__0_8," line.long 0xA44 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER872_upper,Interrupt Routing Registers" line.long 0xA48 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER873_lower,Interrupt Routing Registers" bitfld.long 0xA48 31. "DISTRIBUTOR__37_GICD_IROUTER873_LOWER__31_1," "0,1" hexmask.long.byte 0xA48 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER873_LOWER__8_8," newline hexmask.long.byte 0xA48 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER873_LOWER__0_8," line.long 0xA4C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER873_upper,Interrupt Routing Registers" line.long 0xA50 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER874_lower,Interrupt Routing Registers" bitfld.long 0xA50 31. "DISTRIBUTOR__37_GICD_IROUTER874_LOWER__31_1," "0,1" hexmask.long.byte 0xA50 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER874_LOWER__8_8," newline hexmask.long.byte 0xA50 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER874_LOWER__0_8," line.long 0xA54 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER874_upper,Interrupt Routing Registers" line.long 0xA58 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER875_lower,Interrupt Routing Registers" bitfld.long 0xA58 31. "DISTRIBUTOR__37_GICD_IROUTER875_LOWER__31_1," "0,1" hexmask.long.byte 0xA58 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER875_LOWER__8_8," newline hexmask.long.byte 0xA58 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER875_LOWER__0_8," line.long 0xA5C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER875_upper,Interrupt Routing Registers" line.long 0xA60 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER876_lower,Interrupt Routing Registers" bitfld.long 0xA60 31. "DISTRIBUTOR__37_GICD_IROUTER876_LOWER__31_1," "0,1" hexmask.long.byte 0xA60 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER876_LOWER__8_8," newline hexmask.long.byte 0xA60 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER876_LOWER__0_8," line.long 0xA64 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER876_upper,Interrupt Routing Registers" line.long 0xA68 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER877_lower,Interrupt Routing Registers" bitfld.long 0xA68 31. "DISTRIBUTOR__37_GICD_IROUTER877_LOWER__31_1," "0,1" hexmask.long.byte 0xA68 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER877_LOWER__8_8," newline hexmask.long.byte 0xA68 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER877_LOWER__0_8," line.long 0xA6C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER877_upper,Interrupt Routing Registers" line.long 0xA70 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER878_lower,Interrupt Routing Registers" bitfld.long 0xA70 31. "DISTRIBUTOR__37_GICD_IROUTER878_LOWER__31_1," "0,1" hexmask.long.byte 0xA70 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER878_LOWER__8_8," newline hexmask.long.byte 0xA70 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER878_LOWER__0_8," line.long 0xA74 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER878_upper,Interrupt Routing Registers" line.long 0xA78 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER879_lower,Interrupt Routing Registers" bitfld.long 0xA78 31. "DISTRIBUTOR__37_GICD_IROUTER879_LOWER__31_1," "0,1" hexmask.long.byte 0xA78 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER879_LOWER__8_8," newline hexmask.long.byte 0xA78 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER879_LOWER__0_8," line.long 0xA7C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER879_upper,Interrupt Routing Registers" line.long 0xA80 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER880_lower,Interrupt Routing Registers" bitfld.long 0xA80 31. "DISTRIBUTOR__37_GICD_IROUTER880_LOWER__31_1," "0,1" hexmask.long.byte 0xA80 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER880_LOWER__8_8," newline hexmask.long.byte 0xA80 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER880_LOWER__0_8," line.long 0xA84 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER880_upper,Interrupt Routing Registers" line.long 0xA88 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER881_lower,Interrupt Routing Registers" bitfld.long 0xA88 31. "DISTRIBUTOR__37_GICD_IROUTER881_LOWER__31_1," "0,1" hexmask.long.byte 0xA88 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER881_LOWER__8_8," newline hexmask.long.byte 0xA88 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER881_LOWER__0_8," line.long 0xA8C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER881_upper,Interrupt Routing Registers" line.long 0xA90 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER882_lower,Interrupt Routing Registers" bitfld.long 0xA90 31. "DISTRIBUTOR__37_GICD_IROUTER882_LOWER__31_1," "0,1" hexmask.long.byte 0xA90 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER882_LOWER__8_8," newline hexmask.long.byte 0xA90 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER882_LOWER__0_8," line.long 0xA94 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER882_upper,Interrupt Routing Registers" line.long 0xA98 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER883_lower,Interrupt Routing Registers" bitfld.long 0xA98 31. "DISTRIBUTOR__37_GICD_IROUTER883_LOWER__31_1," "0,1" hexmask.long.byte 0xA98 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER883_LOWER__8_8," newline hexmask.long.byte 0xA98 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER883_LOWER__0_8," line.long 0xA9C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER883_upper,Interrupt Routing Registers" line.long 0xAA0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER884_lower,Interrupt Routing Registers" bitfld.long 0xAA0 31. "DISTRIBUTOR__37_GICD_IROUTER884_LOWER__31_1," "0,1" hexmask.long.byte 0xAA0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER884_LOWER__8_8," newline hexmask.long.byte 0xAA0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER884_LOWER__0_8," line.long 0xAA4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER884_upper,Interrupt Routing Registers" line.long 0xAA8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER885_lower,Interrupt Routing Registers" bitfld.long 0xAA8 31. "DISTRIBUTOR__37_GICD_IROUTER885_LOWER__31_1," "0,1" hexmask.long.byte 0xAA8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER885_LOWER__8_8," newline hexmask.long.byte 0xAA8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER885_LOWER__0_8," line.long 0xAAC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER885_upper,Interrupt Routing Registers" line.long 0xAB0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER886_lower,Interrupt Routing Registers" bitfld.long 0xAB0 31. "DISTRIBUTOR__37_GICD_IROUTER886_LOWER__31_1," "0,1" hexmask.long.byte 0xAB0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER886_LOWER__8_8," newline hexmask.long.byte 0xAB0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER886_LOWER__0_8," line.long 0xAB4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER886_upper,Interrupt Routing Registers" line.long 0xAB8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER887_lower,Interrupt Routing Registers" bitfld.long 0xAB8 31. "DISTRIBUTOR__37_GICD_IROUTER887_LOWER__31_1," "0,1" hexmask.long.byte 0xAB8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER887_LOWER__8_8," newline hexmask.long.byte 0xAB8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER887_LOWER__0_8," line.long 0xABC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER887_upper,Interrupt Routing Registers" line.long 0xAC0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER888_lower,Interrupt Routing Registers" bitfld.long 0xAC0 31. "DISTRIBUTOR__37_GICD_IROUTER888_LOWER__31_1," "0,1" hexmask.long.byte 0xAC0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER888_LOWER__8_8," newline hexmask.long.byte 0xAC0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER888_LOWER__0_8," line.long 0xAC4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER888_upper,Interrupt Routing Registers" line.long 0xAC8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER889_lower,Interrupt Routing Registers" bitfld.long 0xAC8 31. "DISTRIBUTOR__37_GICD_IROUTER889_LOWER__31_1," "0,1" hexmask.long.byte 0xAC8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER889_LOWER__8_8," newline hexmask.long.byte 0xAC8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER889_LOWER__0_8," line.long 0xACC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER889_upper,Interrupt Routing Registers" line.long 0xAD0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER890_lower,Interrupt Routing Registers" bitfld.long 0xAD0 31. "DISTRIBUTOR__37_GICD_IROUTER890_LOWER__31_1," "0,1" hexmask.long.byte 0xAD0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER890_LOWER__8_8," newline hexmask.long.byte 0xAD0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER890_LOWER__0_8," line.long 0xAD4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER890_upper,Interrupt Routing Registers" line.long 0xAD8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER891_lower,Interrupt Routing Registers" bitfld.long 0xAD8 31. "DISTRIBUTOR__37_GICD_IROUTER891_LOWER__31_1," "0,1" hexmask.long.byte 0xAD8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER891_LOWER__8_8," newline hexmask.long.byte 0xAD8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER891_LOWER__0_8," line.long 0xADC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER891_upper,Interrupt Routing Registers" line.long 0xAE0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER892_lower,Interrupt Routing Registers" bitfld.long 0xAE0 31. "DISTRIBUTOR__37_GICD_IROUTER892_LOWER__31_1," "0,1" hexmask.long.byte 0xAE0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER892_LOWER__8_8," newline hexmask.long.byte 0xAE0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER892_LOWER__0_8," line.long 0xAE4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER892_upper,Interrupt Routing Registers" line.long 0xAE8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER893_lower,Interrupt Routing Registers" bitfld.long 0xAE8 31. "DISTRIBUTOR__37_GICD_IROUTER893_LOWER__31_1," "0,1" hexmask.long.byte 0xAE8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER893_LOWER__8_8," newline hexmask.long.byte 0xAE8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER893_LOWER__0_8," line.long 0xAEC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER893_upper,Interrupt Routing Registers" line.long 0xAF0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER894_lower,Interrupt Routing Registers" bitfld.long 0xAF0 31. "DISTRIBUTOR__37_GICD_IROUTER894_LOWER__31_1," "0,1" hexmask.long.byte 0xAF0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER894_LOWER__8_8," newline hexmask.long.byte 0xAF0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER894_LOWER__0_8," line.long 0xAF4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER894_upper,Interrupt Routing Registers" line.long 0xAF8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER895_lower,Interrupt Routing Registers" bitfld.long 0xAF8 31. "DISTRIBUTOR__37_GICD_IROUTER895_LOWER__31_1," "0,1" hexmask.long.byte 0xAF8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER895_LOWER__8_8," newline hexmask.long.byte 0xAF8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER895_LOWER__0_8," line.long 0xAFC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER895_upper,Interrupt Routing Registers" line.long 0xB00 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER896_lower,Interrupt Routing Registers" bitfld.long 0xB00 31. "DISTRIBUTOR__37_GICD_IROUTER896_LOWER__31_1," "0,1" hexmask.long.byte 0xB00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER896_LOWER__8_8," newline hexmask.long.byte 0xB00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER896_LOWER__0_8," line.long 0xB04 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER896_upper,Interrupt Routing Registers" line.long 0xB08 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER897_lower,Interrupt Routing Registers" bitfld.long 0xB08 31. "DISTRIBUTOR__37_GICD_IROUTER897_LOWER__31_1," "0,1" hexmask.long.byte 0xB08 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER897_LOWER__8_8," newline hexmask.long.byte 0xB08 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER897_LOWER__0_8," line.long 0xB0C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER897_upper,Interrupt Routing Registers" line.long 0xB10 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER898_lower,Interrupt Routing Registers" bitfld.long 0xB10 31. "DISTRIBUTOR__37_GICD_IROUTER898_LOWER__31_1," "0,1" hexmask.long.byte 0xB10 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER898_LOWER__8_8," newline hexmask.long.byte 0xB10 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER898_LOWER__0_8," line.long 0xB14 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER898_upper,Interrupt Routing Registers" line.long 0xB18 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER899_lower,Interrupt Routing Registers" bitfld.long 0xB18 31. "DISTRIBUTOR__37_GICD_IROUTER899_LOWER__31_1," "0,1" hexmask.long.byte 0xB18 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER899_LOWER__8_8," newline hexmask.long.byte 0xB18 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER899_LOWER__0_8," line.long 0xB1C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER899_upper,Interrupt Routing Registers" line.long 0xB20 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER900_lower,Interrupt Routing Registers" bitfld.long 0xB20 31. "DISTRIBUTOR__37_GICD_IROUTER900_LOWER__31_1," "0,1" hexmask.long.byte 0xB20 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER900_LOWER__8_8," newline hexmask.long.byte 0xB20 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER900_LOWER__0_8," line.long 0xB24 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER900_upper,Interrupt Routing Registers" line.long 0xB28 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER901_lower,Interrupt Routing Registers" bitfld.long 0xB28 31. "DISTRIBUTOR__37_GICD_IROUTER901_LOWER__31_1," "0,1" hexmask.long.byte 0xB28 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER901_LOWER__8_8," newline hexmask.long.byte 0xB28 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER901_LOWER__0_8," line.long 0xB2C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER901_upper,Interrupt Routing Registers" line.long 0xB30 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER902_lower,Interrupt Routing Registers" bitfld.long 0xB30 31. "DISTRIBUTOR__37_GICD_IROUTER902_LOWER__31_1," "0,1" hexmask.long.byte 0xB30 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER902_LOWER__8_8," newline hexmask.long.byte 0xB30 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER902_LOWER__0_8," line.long 0xB34 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER902_upper,Interrupt Routing Registers" line.long 0xB38 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER903_lower,Interrupt Routing Registers" bitfld.long 0xB38 31. "DISTRIBUTOR__37_GICD_IROUTER903_LOWER__31_1," "0,1" hexmask.long.byte 0xB38 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER903_LOWER__8_8," newline hexmask.long.byte 0xB38 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER903_LOWER__0_8," line.long 0xB3C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER903_upper,Interrupt Routing Registers" line.long 0xB40 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER904_lower,Interrupt Routing Registers" bitfld.long 0xB40 31. "DISTRIBUTOR__37_GICD_IROUTER904_LOWER__31_1," "0,1" hexmask.long.byte 0xB40 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER904_LOWER__8_8," newline hexmask.long.byte 0xB40 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER904_LOWER__0_8," line.long 0xB44 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER904_upper,Interrupt Routing Registers" line.long 0xB48 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER905_lower,Interrupt Routing Registers" bitfld.long 0xB48 31. "DISTRIBUTOR__37_GICD_IROUTER905_LOWER__31_1," "0,1" hexmask.long.byte 0xB48 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER905_LOWER__8_8," newline hexmask.long.byte 0xB48 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER905_LOWER__0_8," line.long 0xB4C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER905_upper,Interrupt Routing Registers" line.long 0xB50 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER906_lower,Interrupt Routing Registers" bitfld.long 0xB50 31. "DISTRIBUTOR__37_GICD_IROUTER906_LOWER__31_1," "0,1" hexmask.long.byte 0xB50 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER906_LOWER__8_8," newline hexmask.long.byte 0xB50 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER906_LOWER__0_8," line.long 0xB54 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER906_upper,Interrupt Routing Registers" line.long 0xB58 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER907_lower,Interrupt Routing Registers" bitfld.long 0xB58 31. "DISTRIBUTOR__37_GICD_IROUTER907_LOWER__31_1," "0,1" hexmask.long.byte 0xB58 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER907_LOWER__8_8," newline hexmask.long.byte 0xB58 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER907_LOWER__0_8," line.long 0xB5C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER907_upper,Interrupt Routing Registers" line.long 0xB60 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER908_lower,Interrupt Routing Registers" bitfld.long 0xB60 31. "DISTRIBUTOR__37_GICD_IROUTER908_LOWER__31_1," "0,1" hexmask.long.byte 0xB60 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER908_LOWER__8_8," newline hexmask.long.byte 0xB60 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER908_LOWER__0_8," line.long 0xB64 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER908_upper,Interrupt Routing Registers" line.long 0xB68 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER909_lower,Interrupt Routing Registers" bitfld.long 0xB68 31. "DISTRIBUTOR__37_GICD_IROUTER909_LOWER__31_1," "0,1" hexmask.long.byte 0xB68 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER909_LOWER__8_8," newline hexmask.long.byte 0xB68 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER909_LOWER__0_8," line.long 0xB6C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER909_upper,Interrupt Routing Registers" line.long 0xB70 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER910_lower,Interrupt Routing Registers" bitfld.long 0xB70 31. "DISTRIBUTOR__37_GICD_IROUTER910_LOWER__31_1," "0,1" hexmask.long.byte 0xB70 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER910_LOWER__8_8," newline hexmask.long.byte 0xB70 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER910_LOWER__0_8," line.long 0xB74 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER910_upper,Interrupt Routing Registers" line.long 0xB78 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER911_lower,Interrupt Routing Registers" bitfld.long 0xB78 31. "DISTRIBUTOR__37_GICD_IROUTER911_LOWER__31_1," "0,1" hexmask.long.byte 0xB78 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER911_LOWER__8_8," newline hexmask.long.byte 0xB78 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER911_LOWER__0_8," line.long 0xB7C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER911_upper,Interrupt Routing Registers" line.long 0xB80 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER912_lower,Interrupt Routing Registers" bitfld.long 0xB80 31. "DISTRIBUTOR__37_GICD_IROUTER912_LOWER__31_1," "0,1" hexmask.long.byte 0xB80 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER912_LOWER__8_8," newline hexmask.long.byte 0xB80 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER912_LOWER__0_8," line.long 0xB84 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER912_upper,Interrupt Routing Registers" line.long 0xB88 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER913_lower,Interrupt Routing Registers" bitfld.long 0xB88 31. "DISTRIBUTOR__37_GICD_IROUTER913_LOWER__31_1," "0,1" hexmask.long.byte 0xB88 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER913_LOWER__8_8," newline hexmask.long.byte 0xB88 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER913_LOWER__0_8," line.long 0xB8C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER913_upper,Interrupt Routing Registers" line.long 0xB90 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER914_lower,Interrupt Routing Registers" bitfld.long 0xB90 31. "DISTRIBUTOR__37_GICD_IROUTER914_LOWER__31_1," "0,1" hexmask.long.byte 0xB90 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER914_LOWER__8_8," newline hexmask.long.byte 0xB90 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER914_LOWER__0_8," line.long 0xB94 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER914_upper,Interrupt Routing Registers" line.long 0xB98 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER915_lower,Interrupt Routing Registers" bitfld.long 0xB98 31. "DISTRIBUTOR__37_GICD_IROUTER915_LOWER__31_1," "0,1" hexmask.long.byte 0xB98 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER915_LOWER__8_8," newline hexmask.long.byte 0xB98 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER915_LOWER__0_8," line.long 0xB9C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER915_upper,Interrupt Routing Registers" line.long 0xBA0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER916_lower,Interrupt Routing Registers" bitfld.long 0xBA0 31. "DISTRIBUTOR__37_GICD_IROUTER916_LOWER__31_1," "0,1" hexmask.long.byte 0xBA0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER916_LOWER__8_8," newline hexmask.long.byte 0xBA0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER916_LOWER__0_8," line.long 0xBA4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER916_upper,Interrupt Routing Registers" line.long 0xBA8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER917_lower,Interrupt Routing Registers" bitfld.long 0xBA8 31. "DISTRIBUTOR__37_GICD_IROUTER917_LOWER__31_1," "0,1" hexmask.long.byte 0xBA8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER917_LOWER__8_8," newline hexmask.long.byte 0xBA8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER917_LOWER__0_8," line.long 0xBAC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER917_upper,Interrupt Routing Registers" line.long 0xBB0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER918_lower,Interrupt Routing Registers" bitfld.long 0xBB0 31. "DISTRIBUTOR__37_GICD_IROUTER918_LOWER__31_1," "0,1" hexmask.long.byte 0xBB0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER918_LOWER__8_8," newline hexmask.long.byte 0xBB0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER918_LOWER__0_8," line.long 0xBB4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER918_upper,Interrupt Routing Registers" line.long 0xBB8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER919_lower,Interrupt Routing Registers" bitfld.long 0xBB8 31. "DISTRIBUTOR__37_GICD_IROUTER919_LOWER__31_1," "0,1" hexmask.long.byte 0xBB8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER919_LOWER__8_8," newline hexmask.long.byte 0xBB8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER919_LOWER__0_8," line.long 0xBBC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER919_upper,Interrupt Routing Registers" line.long 0xBC0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER920_lower,Interrupt Routing Registers" bitfld.long 0xBC0 31. "DISTRIBUTOR__37_GICD_IROUTER920_LOWER__31_1," "0,1" hexmask.long.byte 0xBC0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER920_LOWER__8_8," newline hexmask.long.byte 0xBC0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER920_LOWER__0_8," line.long 0xBC4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER920_upper,Interrupt Routing Registers" line.long 0xBC8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER921_lower,Interrupt Routing Registers" bitfld.long 0xBC8 31. "DISTRIBUTOR__37_GICD_IROUTER921_LOWER__31_1," "0,1" hexmask.long.byte 0xBC8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER921_LOWER__8_8," newline hexmask.long.byte 0xBC8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER921_LOWER__0_8," line.long 0xBCC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER921_upper,Interrupt Routing Registers" line.long 0xBD0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER922_lower,Interrupt Routing Registers" bitfld.long 0xBD0 31. "DISTRIBUTOR__37_GICD_IROUTER922_LOWER__31_1," "0,1" hexmask.long.byte 0xBD0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER922_LOWER__8_8," newline hexmask.long.byte 0xBD0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER922_LOWER__0_8," line.long 0xBD4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER922_upper,Interrupt Routing Registers" line.long 0xBD8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER923_lower,Interrupt Routing Registers" bitfld.long 0xBD8 31. "DISTRIBUTOR__37_GICD_IROUTER923_LOWER__31_1," "0,1" hexmask.long.byte 0xBD8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER923_LOWER__8_8," newline hexmask.long.byte 0xBD8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER923_LOWER__0_8," line.long 0xBDC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER923_upper,Interrupt Routing Registers" line.long 0xBE0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER924_lower,Interrupt Routing Registers" bitfld.long 0xBE0 31. "DISTRIBUTOR__37_GICD_IROUTER924_LOWER__31_1," "0,1" hexmask.long.byte 0xBE0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER924_LOWER__8_8," newline hexmask.long.byte 0xBE0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER924_LOWER__0_8," line.long 0xBE4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER924_upper,Interrupt Routing Registers" line.long 0xBE8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER925_lower,Interrupt Routing Registers" bitfld.long 0xBE8 31. "DISTRIBUTOR__37_GICD_IROUTER925_LOWER__31_1," "0,1" hexmask.long.byte 0xBE8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER925_LOWER__8_8," newline hexmask.long.byte 0xBE8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER925_LOWER__0_8," line.long 0xBEC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER925_upper,Interrupt Routing Registers" line.long 0xBF0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER926_lower,Interrupt Routing Registers" bitfld.long 0xBF0 31. "DISTRIBUTOR__37_GICD_IROUTER926_LOWER__31_1," "0,1" hexmask.long.byte 0xBF0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER926_LOWER__8_8," newline hexmask.long.byte 0xBF0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER926_LOWER__0_8," line.long 0xBF4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER926_upper,Interrupt Routing Registers" line.long 0xBF8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER927_lower,Interrupt Routing Registers" bitfld.long 0xBF8 31. "DISTRIBUTOR__37_GICD_IROUTER927_LOWER__31_1," "0,1" hexmask.long.byte 0xBF8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER927_LOWER__8_8," newline hexmask.long.byte 0xBF8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER927_LOWER__0_8," line.long 0xBFC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER927_upper,Interrupt Routing Registers" line.long 0xC00 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER928_lower,Interrupt Routing Registers" bitfld.long 0xC00 31. "DISTRIBUTOR__37_GICD_IROUTER928_LOWER__31_1," "0,1" hexmask.long.byte 0xC00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER928_LOWER__8_8," newline hexmask.long.byte 0xC00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER928_LOWER__0_8," line.long 0xC04 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER928_upper,Interrupt Routing Registers" line.long 0xC08 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER929_lower,Interrupt Routing Registers" bitfld.long 0xC08 31. "DISTRIBUTOR__37_GICD_IROUTER929_LOWER__31_1," "0,1" hexmask.long.byte 0xC08 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER929_LOWER__8_8," newline hexmask.long.byte 0xC08 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER929_LOWER__0_8," line.long 0xC0C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER929_upper,Interrupt Routing Registers" line.long 0xC10 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER930_lower,Interrupt Routing Registers" bitfld.long 0xC10 31. "DISTRIBUTOR__37_GICD_IROUTER930_LOWER__31_1," "0,1" hexmask.long.byte 0xC10 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER930_LOWER__8_8," newline hexmask.long.byte 0xC10 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER930_LOWER__0_8," line.long 0xC14 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER930_upper,Interrupt Routing Registers" line.long 0xC18 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER931_lower,Interrupt Routing Registers" bitfld.long 0xC18 31. "DISTRIBUTOR__37_GICD_IROUTER931_LOWER__31_1," "0,1" hexmask.long.byte 0xC18 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER931_LOWER__8_8," newline hexmask.long.byte 0xC18 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER931_LOWER__0_8," line.long 0xC1C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER931_upper,Interrupt Routing Registers" line.long 0xC20 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER932_lower,Interrupt Routing Registers" bitfld.long 0xC20 31. "DISTRIBUTOR__37_GICD_IROUTER932_LOWER__31_1," "0,1" hexmask.long.byte 0xC20 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER932_LOWER__8_8," newline hexmask.long.byte 0xC20 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER932_LOWER__0_8," line.long 0xC24 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER932_upper,Interrupt Routing Registers" line.long 0xC28 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER933_lower,Interrupt Routing Registers" bitfld.long 0xC28 31. "DISTRIBUTOR__37_GICD_IROUTER933_LOWER__31_1," "0,1" hexmask.long.byte 0xC28 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER933_LOWER__8_8," newline hexmask.long.byte 0xC28 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER933_LOWER__0_8," line.long 0xC2C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER933_upper,Interrupt Routing Registers" line.long 0xC30 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER934_lower,Interrupt Routing Registers" bitfld.long 0xC30 31. "DISTRIBUTOR__37_GICD_IROUTER934_LOWER__31_1," "0,1" hexmask.long.byte 0xC30 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER934_LOWER__8_8," newline hexmask.long.byte 0xC30 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER934_LOWER__0_8," line.long 0xC34 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER934_upper,Interrupt Routing Registers" line.long 0xC38 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER935_lower,Interrupt Routing Registers" bitfld.long 0xC38 31. "DISTRIBUTOR__37_GICD_IROUTER935_LOWER__31_1," "0,1" hexmask.long.byte 0xC38 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER935_LOWER__8_8," newline hexmask.long.byte 0xC38 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER935_LOWER__0_8," line.long 0xC3C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER935_upper,Interrupt Routing Registers" line.long 0xC40 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER936_lower,Interrupt Routing Registers" bitfld.long 0xC40 31. "DISTRIBUTOR__37_GICD_IROUTER936_LOWER__31_1," "0,1" hexmask.long.byte 0xC40 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER936_LOWER__8_8," newline hexmask.long.byte 0xC40 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER936_LOWER__0_8," line.long 0xC44 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER936_upper,Interrupt Routing Registers" line.long 0xC48 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER937_lower,Interrupt Routing Registers" bitfld.long 0xC48 31. "DISTRIBUTOR__37_GICD_IROUTER937_LOWER__31_1," "0,1" hexmask.long.byte 0xC48 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER937_LOWER__8_8," newline hexmask.long.byte 0xC48 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER937_LOWER__0_8," line.long 0xC4C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER937_upper,Interrupt Routing Registers" line.long 0xC50 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER938_lower,Interrupt Routing Registers" bitfld.long 0xC50 31. "DISTRIBUTOR__37_GICD_IROUTER938_LOWER__31_1," "0,1" hexmask.long.byte 0xC50 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER938_LOWER__8_8," newline hexmask.long.byte 0xC50 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER938_LOWER__0_8," line.long 0xC54 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER938_upper,Interrupt Routing Registers" line.long 0xC58 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER939_lower,Interrupt Routing Registers" bitfld.long 0xC58 31. "DISTRIBUTOR__37_GICD_IROUTER939_LOWER__31_1," "0,1" hexmask.long.byte 0xC58 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER939_LOWER__8_8," newline hexmask.long.byte 0xC58 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER939_LOWER__0_8," line.long 0xC5C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER939_upper,Interrupt Routing Registers" line.long 0xC60 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER940_lower,Interrupt Routing Registers" bitfld.long 0xC60 31. "DISTRIBUTOR__37_GICD_IROUTER940_LOWER__31_1," "0,1" hexmask.long.byte 0xC60 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER940_LOWER__8_8," newline hexmask.long.byte 0xC60 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER940_LOWER__0_8," line.long 0xC64 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER940_upper,Interrupt Routing Registers" line.long 0xC68 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER941_lower,Interrupt Routing Registers" bitfld.long 0xC68 31. "DISTRIBUTOR__37_GICD_IROUTER941_LOWER__31_1," "0,1" hexmask.long.byte 0xC68 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER941_LOWER__8_8," newline hexmask.long.byte 0xC68 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER941_LOWER__0_8," line.long 0xC6C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER941_upper,Interrupt Routing Registers" line.long 0xC70 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER942_lower,Interrupt Routing Registers" bitfld.long 0xC70 31. "DISTRIBUTOR__37_GICD_IROUTER942_LOWER__31_1," "0,1" hexmask.long.byte 0xC70 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER942_LOWER__8_8," newline hexmask.long.byte 0xC70 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER942_LOWER__0_8," line.long 0xC74 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER942_upper,Interrupt Routing Registers" line.long 0xC78 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER943_lower,Interrupt Routing Registers" bitfld.long 0xC78 31. "DISTRIBUTOR__37_GICD_IROUTER943_LOWER__31_1," "0,1" hexmask.long.byte 0xC78 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER943_LOWER__8_8," newline hexmask.long.byte 0xC78 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER943_LOWER__0_8," line.long 0xC7C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER943_upper,Interrupt Routing Registers" line.long 0xC80 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER944_lower,Interrupt Routing Registers" bitfld.long 0xC80 31. "DISTRIBUTOR__37_GICD_IROUTER944_LOWER__31_1," "0,1" hexmask.long.byte 0xC80 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER944_LOWER__8_8," newline hexmask.long.byte 0xC80 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER944_LOWER__0_8," line.long 0xC84 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER944_upper,Interrupt Routing Registers" line.long 0xC88 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER945_lower,Interrupt Routing Registers" bitfld.long 0xC88 31. "DISTRIBUTOR__37_GICD_IROUTER945_LOWER__31_1," "0,1" hexmask.long.byte 0xC88 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER945_LOWER__8_8," newline hexmask.long.byte 0xC88 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER945_LOWER__0_8," line.long 0xC8C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER945_upper,Interrupt Routing Registers" line.long 0xC90 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER946_lower,Interrupt Routing Registers" bitfld.long 0xC90 31. "DISTRIBUTOR__37_GICD_IROUTER946_LOWER__31_1," "0,1" hexmask.long.byte 0xC90 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER946_LOWER__8_8," newline hexmask.long.byte 0xC90 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER946_LOWER__0_8," line.long 0xC94 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER946_upper,Interrupt Routing Registers" line.long 0xC98 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER947_lower,Interrupt Routing Registers" bitfld.long 0xC98 31. "DISTRIBUTOR__37_GICD_IROUTER947_LOWER__31_1," "0,1" hexmask.long.byte 0xC98 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER947_LOWER__8_8," newline hexmask.long.byte 0xC98 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER947_LOWER__0_8," line.long 0xC9C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER947_upper,Interrupt Routing Registers" line.long 0xCA0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER948_lower,Interrupt Routing Registers" bitfld.long 0xCA0 31. "DISTRIBUTOR__37_GICD_IROUTER948_LOWER__31_1," "0,1" hexmask.long.byte 0xCA0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER948_LOWER__8_8," newline hexmask.long.byte 0xCA0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER948_LOWER__0_8," line.long 0xCA4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER948_upper,Interrupt Routing Registers" line.long 0xCA8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER949_lower,Interrupt Routing Registers" bitfld.long 0xCA8 31. "DISTRIBUTOR__37_GICD_IROUTER949_LOWER__31_1," "0,1" hexmask.long.byte 0xCA8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER949_LOWER__8_8," newline hexmask.long.byte 0xCA8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER949_LOWER__0_8," line.long 0xCAC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER949_upper,Interrupt Routing Registers" line.long 0xCB0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER950_lower,Interrupt Routing Registers" bitfld.long 0xCB0 31. "DISTRIBUTOR__37_GICD_IROUTER950_LOWER__31_1," "0,1" hexmask.long.byte 0xCB0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER950_LOWER__8_8," newline hexmask.long.byte 0xCB0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER950_LOWER__0_8," line.long 0xCB4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER950_upper,Interrupt Routing Registers" line.long 0xCB8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER951_lower,Interrupt Routing Registers" bitfld.long 0xCB8 31. "DISTRIBUTOR__37_GICD_IROUTER951_LOWER__31_1," "0,1" hexmask.long.byte 0xCB8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER951_LOWER__8_8," newline hexmask.long.byte 0xCB8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER951_LOWER__0_8," line.long 0xCBC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER951_upper,Interrupt Routing Registers" line.long 0xCC0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER952_lower,Interrupt Routing Registers" bitfld.long 0xCC0 31. "DISTRIBUTOR__37_GICD_IROUTER952_LOWER__31_1," "0,1" hexmask.long.byte 0xCC0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER952_LOWER__8_8," newline hexmask.long.byte 0xCC0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER952_LOWER__0_8," line.long 0xCC4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER952_upper,Interrupt Routing Registers" line.long 0xCC8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER953_lower,Interrupt Routing Registers" bitfld.long 0xCC8 31. "DISTRIBUTOR__37_GICD_IROUTER953_LOWER__31_1," "0,1" hexmask.long.byte 0xCC8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER953_LOWER__8_8," newline hexmask.long.byte 0xCC8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER953_LOWER__0_8," line.long 0xCCC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER953_upper,Interrupt Routing Registers" line.long 0xCD0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER954_lower,Interrupt Routing Registers" bitfld.long 0xCD0 31. "DISTRIBUTOR__37_GICD_IROUTER954_LOWER__31_1," "0,1" hexmask.long.byte 0xCD0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER954_LOWER__8_8," newline hexmask.long.byte 0xCD0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER954_LOWER__0_8," line.long 0xCD4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER954_upper,Interrupt Routing Registers" line.long 0xCD8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER955_lower,Interrupt Routing Registers" bitfld.long 0xCD8 31. "DISTRIBUTOR__37_GICD_IROUTER955_LOWER__31_1," "0,1" hexmask.long.byte 0xCD8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER955_LOWER__8_8," newline hexmask.long.byte 0xCD8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER955_LOWER__0_8," line.long 0xCDC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER955_upper,Interrupt Routing Registers" line.long 0xCE0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER956_lower,Interrupt Routing Registers" bitfld.long 0xCE0 31. "DISTRIBUTOR__37_GICD_IROUTER956_LOWER__31_1," "0,1" hexmask.long.byte 0xCE0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER956_LOWER__8_8," newline hexmask.long.byte 0xCE0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER956_LOWER__0_8," line.long 0xCE4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER956_upper,Interrupt Routing Registers" line.long 0xCE8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER957_lower,Interrupt Routing Registers" bitfld.long 0xCE8 31. "DISTRIBUTOR__37_GICD_IROUTER957_LOWER__31_1," "0,1" hexmask.long.byte 0xCE8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER957_LOWER__8_8," newline hexmask.long.byte 0xCE8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER957_LOWER__0_8," line.long 0xCEC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER957_upper,Interrupt Routing Registers" line.long 0xCF0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER958_lower,Interrupt Routing Registers" bitfld.long 0xCF0 31. "DISTRIBUTOR__37_GICD_IROUTER958_LOWER__31_1," "0,1" hexmask.long.byte 0xCF0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER958_LOWER__8_8," newline hexmask.long.byte 0xCF0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER958_LOWER__0_8," line.long 0xCF4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER958_upper,Interrupt Routing Registers" line.long 0xCF8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER959_lower,Interrupt Routing Registers" bitfld.long 0xCF8 31. "DISTRIBUTOR__37_GICD_IROUTER959_LOWER__31_1," "0,1" hexmask.long.byte 0xCF8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER959_LOWER__8_8," newline hexmask.long.byte 0xCF8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER959_LOWER__0_8," line.long 0xCFC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER959_upper,Interrupt Routing Registers" line.long 0xD00 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER960_lower,Interrupt Routing Registers" bitfld.long 0xD00 31. "DISTRIBUTOR__37_GICD_IROUTER960_LOWER__31_1," "0,1" hexmask.long.byte 0xD00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER960_LOWER__8_8," newline hexmask.long.byte 0xD00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER960_LOWER__0_8," line.long 0xD04 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER960_upper,Interrupt Routing Registers" line.long 0xD08 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER961_lower,Interrupt Routing Registers" bitfld.long 0xD08 31. "DISTRIBUTOR__37_GICD_IROUTER961_LOWER__31_1," "0,1" hexmask.long.byte 0xD08 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER961_LOWER__8_8," newline hexmask.long.byte 0xD08 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER961_LOWER__0_8," line.long 0xD0C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER961_upper,Interrupt Routing Registers" line.long 0xD10 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER962_lower,Interrupt Routing Registers" bitfld.long 0xD10 31. "DISTRIBUTOR__37_GICD_IROUTER962_LOWER__31_1," "0,1" hexmask.long.byte 0xD10 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER962_LOWER__8_8," newline hexmask.long.byte 0xD10 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER962_LOWER__0_8," line.long 0xD14 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER962_upper,Interrupt Routing Registers" line.long 0xD18 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER963_lower,Interrupt Routing Registers" bitfld.long 0xD18 31. "DISTRIBUTOR__37_GICD_IROUTER963_LOWER__31_1," "0,1" hexmask.long.byte 0xD18 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER963_LOWER__8_8," newline hexmask.long.byte 0xD18 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER963_LOWER__0_8," line.long 0xD1C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER963_upper,Interrupt Routing Registers" line.long 0xD20 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER964_lower,Interrupt Routing Registers" bitfld.long 0xD20 31. "DISTRIBUTOR__37_GICD_IROUTER964_LOWER__31_1," "0,1" hexmask.long.byte 0xD20 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER964_LOWER__8_8," newline hexmask.long.byte 0xD20 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER964_LOWER__0_8," line.long 0xD24 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER964_upper,Interrupt Routing Registers" line.long 0xD28 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER965_lower,Interrupt Routing Registers" bitfld.long 0xD28 31. "DISTRIBUTOR__37_GICD_IROUTER965_LOWER__31_1," "0,1" hexmask.long.byte 0xD28 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER965_LOWER__8_8," newline hexmask.long.byte 0xD28 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER965_LOWER__0_8," line.long 0xD2C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER965_upper,Interrupt Routing Registers" line.long 0xD30 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER966_lower,Interrupt Routing Registers" bitfld.long 0xD30 31. "DISTRIBUTOR__37_GICD_IROUTER966_LOWER__31_1," "0,1" hexmask.long.byte 0xD30 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER966_LOWER__8_8," newline hexmask.long.byte 0xD30 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER966_LOWER__0_8," line.long 0xD34 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER966_upper,Interrupt Routing Registers" line.long 0xD38 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER967_lower,Interrupt Routing Registers" bitfld.long 0xD38 31. "DISTRIBUTOR__37_GICD_IROUTER967_LOWER__31_1," "0,1" hexmask.long.byte 0xD38 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER967_LOWER__8_8," newline hexmask.long.byte 0xD38 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER967_LOWER__0_8," line.long 0xD3C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER967_upper,Interrupt Routing Registers" line.long 0xD40 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER968_lower,Interrupt Routing Registers" bitfld.long 0xD40 31. "DISTRIBUTOR__37_GICD_IROUTER968_LOWER__31_1," "0,1" hexmask.long.byte 0xD40 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER968_LOWER__8_8," newline hexmask.long.byte 0xD40 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER968_LOWER__0_8," line.long 0xD44 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER968_upper,Interrupt Routing Registers" line.long 0xD48 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER969_lower,Interrupt Routing Registers" bitfld.long 0xD48 31. "DISTRIBUTOR__37_GICD_IROUTER969_LOWER__31_1," "0,1" hexmask.long.byte 0xD48 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER969_LOWER__8_8," newline hexmask.long.byte 0xD48 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER969_LOWER__0_8," line.long 0xD4C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER969_upper,Interrupt Routing Registers" line.long 0xD50 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER970_lower,Interrupt Routing Registers" bitfld.long 0xD50 31. "DISTRIBUTOR__37_GICD_IROUTER970_LOWER__31_1," "0,1" hexmask.long.byte 0xD50 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER970_LOWER__8_8," newline hexmask.long.byte 0xD50 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER970_LOWER__0_8," line.long 0xD54 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER970_upper,Interrupt Routing Registers" line.long 0xD58 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER971_lower,Interrupt Routing Registers" bitfld.long 0xD58 31. "DISTRIBUTOR__37_GICD_IROUTER971_LOWER__31_1," "0,1" hexmask.long.byte 0xD58 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER971_LOWER__8_8," newline hexmask.long.byte 0xD58 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER971_LOWER__0_8," line.long 0xD5C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER971_upper,Interrupt Routing Registers" line.long 0xD60 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER972_lower,Interrupt Routing Registers" bitfld.long 0xD60 31. "DISTRIBUTOR__37_GICD_IROUTER972_LOWER__31_1," "0,1" hexmask.long.byte 0xD60 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER972_LOWER__8_8," newline hexmask.long.byte 0xD60 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER972_LOWER__0_8," line.long 0xD64 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER972_upper,Interrupt Routing Registers" line.long 0xD68 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER973_lower,Interrupt Routing Registers" bitfld.long 0xD68 31. "DISTRIBUTOR__37_GICD_IROUTER973_LOWER__31_1," "0,1" hexmask.long.byte 0xD68 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER973_LOWER__8_8," newline hexmask.long.byte 0xD68 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER973_LOWER__0_8," line.long 0xD6C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER973_upper,Interrupt Routing Registers" line.long 0xD70 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER974_lower,Interrupt Routing Registers" bitfld.long 0xD70 31. "DISTRIBUTOR__37_GICD_IROUTER974_LOWER__31_1," "0,1" hexmask.long.byte 0xD70 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER974_LOWER__8_8," newline hexmask.long.byte 0xD70 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER974_LOWER__0_8," line.long 0xD74 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER974_upper,Interrupt Routing Registers" line.long 0xD78 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER975_lower,Interrupt Routing Registers" bitfld.long 0xD78 31. "DISTRIBUTOR__37_GICD_IROUTER975_LOWER__31_1," "0,1" hexmask.long.byte 0xD78 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER975_LOWER__8_8," newline hexmask.long.byte 0xD78 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER975_LOWER__0_8," line.long 0xD7C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER975_upper,Interrupt Routing Registers" line.long 0xD80 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER976_lower,Interrupt Routing Registers" bitfld.long 0xD80 31. "DISTRIBUTOR__37_GICD_IROUTER976_LOWER__31_1," "0,1" hexmask.long.byte 0xD80 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER976_LOWER__8_8," newline hexmask.long.byte 0xD80 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER976_LOWER__0_8," line.long 0xD84 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER976_upper,Interrupt Routing Registers" line.long 0xD88 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER977_lower,Interrupt Routing Registers" bitfld.long 0xD88 31. "DISTRIBUTOR__37_GICD_IROUTER977_LOWER__31_1," "0,1" hexmask.long.byte 0xD88 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER977_LOWER__8_8," newline hexmask.long.byte 0xD88 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER977_LOWER__0_8," line.long 0xD8C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER977_upper,Interrupt Routing Registers" line.long 0xD90 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER978_lower,Interrupt Routing Registers" bitfld.long 0xD90 31. "DISTRIBUTOR__37_GICD_IROUTER978_LOWER__31_1," "0,1" hexmask.long.byte 0xD90 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER978_LOWER__8_8," newline hexmask.long.byte 0xD90 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER978_LOWER__0_8," line.long 0xD94 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER978_upper,Interrupt Routing Registers" line.long 0xD98 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER979_lower,Interrupt Routing Registers" bitfld.long 0xD98 31. "DISTRIBUTOR__37_GICD_IROUTER979_LOWER__31_1," "0,1" hexmask.long.byte 0xD98 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER979_LOWER__8_8," newline hexmask.long.byte 0xD98 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER979_LOWER__0_8," line.long 0xD9C "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER979_upper,Interrupt Routing Registers" line.long 0xDA0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER980_lower,Interrupt Routing Registers" bitfld.long 0xDA0 31. "DISTRIBUTOR__37_GICD_IROUTER980_LOWER__31_1," "0,1" hexmask.long.byte 0xDA0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER980_LOWER__8_8," newline hexmask.long.byte 0xDA0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER980_LOWER__0_8," line.long 0xDA4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER980_upper,Interrupt Routing Registers" line.long 0xDA8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER981_lower,Interrupt Routing Registers" bitfld.long 0xDA8 31. "DISTRIBUTOR__37_GICD_IROUTER981_LOWER__31_1," "0,1" hexmask.long.byte 0xDA8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER981_LOWER__8_8," newline hexmask.long.byte 0xDA8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER981_LOWER__0_8," line.long 0xDAC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER981_upper,Interrupt Routing Registers" line.long 0xDB0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER982_lower,Interrupt Routing Registers" bitfld.long 0xDB0 31. "DISTRIBUTOR__37_GICD_IROUTER982_LOWER__31_1," "0,1" hexmask.long.byte 0xDB0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER982_LOWER__8_8," newline hexmask.long.byte 0xDB0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER982_LOWER__0_8," line.long 0xDB4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER982_upper,Interrupt Routing Registers" line.long 0xDB8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER983_lower,Interrupt Routing Registers" bitfld.long 0xDB8 31. "DISTRIBUTOR__37_GICD_IROUTER983_LOWER__31_1," "0,1" hexmask.long.byte 0xDB8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER983_LOWER__8_8," newline hexmask.long.byte 0xDB8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER983_LOWER__0_8," line.long 0xDBC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER983_upper,Interrupt Routing Registers" line.long 0xDC0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER984_lower,Interrupt Routing Registers" bitfld.long 0xDC0 31. "DISTRIBUTOR__37_GICD_IROUTER984_LOWER__31_1," "0,1" hexmask.long.byte 0xDC0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER984_LOWER__8_8," newline hexmask.long.byte 0xDC0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER984_LOWER__0_8," line.long 0xDC4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER984_upper,Interrupt Routing Registers" line.long 0xDC8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER985_lower,Interrupt Routing Registers" bitfld.long 0xDC8 31. "DISTRIBUTOR__37_GICD_IROUTER985_LOWER__31_1," "0,1" hexmask.long.byte 0xDC8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER985_LOWER__8_8," newline hexmask.long.byte 0xDC8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER985_LOWER__0_8," line.long 0xDCC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER985_upper,Interrupt Routing Registers" line.long 0xDD0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER986_lower,Interrupt Routing Registers" bitfld.long 0xDD0 31. "DISTRIBUTOR__37_GICD_IROUTER986_LOWER__31_1," "0,1" hexmask.long.byte 0xDD0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER986_LOWER__8_8," newline hexmask.long.byte 0xDD0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER986_LOWER__0_8," line.long 0xDD4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER986_upper,Interrupt Routing Registers" line.long 0xDD8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER987_lower,Interrupt Routing Registers" bitfld.long 0xDD8 31. "DISTRIBUTOR__37_GICD_IROUTER987_LOWER__31_1," "0,1" hexmask.long.byte 0xDD8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER987_LOWER__8_8," newline hexmask.long.byte 0xDD8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER987_LOWER__0_8," line.long 0xDDC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER987_upper,Interrupt Routing Registers" line.long 0xDE0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER988_lower,Interrupt Routing Registers" bitfld.long 0xDE0 31. "DISTRIBUTOR__37_GICD_IROUTER988_LOWER__31_1," "0,1" hexmask.long.byte 0xDE0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER988_LOWER__8_8," newline hexmask.long.byte 0xDE0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER988_LOWER__0_8," line.long 0xDE4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER988_upper,Interrupt Routing Registers" line.long 0xDE8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER989_lower,Interrupt Routing Registers" bitfld.long 0xDE8 31. "DISTRIBUTOR__37_GICD_IROUTER989_LOWER__31_1," "0,1" hexmask.long.byte 0xDE8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER989_LOWER__8_8," newline hexmask.long.byte 0xDE8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER989_LOWER__0_8," line.long 0xDEC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER989_upper,Interrupt Routing Registers" line.long 0xDF0 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER990_lower,Interrupt Routing Registers" bitfld.long 0xDF0 31. "DISTRIBUTOR__37_GICD_IROUTER990_LOWER__31_1," "0,1" hexmask.long.byte 0xDF0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER990_LOWER__8_8," newline hexmask.long.byte 0xDF0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER990_LOWER__0_8," line.long 0xDF4 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER990_upper,Interrupt Routing Registers" line.long 0xDF8 "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER991_lower,Interrupt Routing Registers" bitfld.long 0xDF8 31. "DISTRIBUTOR__37_GICD_IROUTER991_LOWER__31_1," "0,1" hexmask.long.byte 0xDF8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER991_LOWER__8_8," newline hexmask.long.byte 0xDF8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER991_LOWER__0_8," line.long 0xDFC "GIC_DISTRIBUTOR_Distributor__37_GICD_IROUTER991_upper,Interrupt Routing Registers" rgroup.long 0xC000++0x7 line.long 0x0 "GIC_DISTRIBUTOR_Distributor__38_GICD_ESTATUSR,GIC-500 Extended Status Register" bitfld.long 0x0 31. "DISTRIBUTOR__38_GICD_ESTATUSR__31_1," "0,1" line.long 0x4 "GIC_DISTRIBUTOR_Distributor__39_GICD_ERRTESTR,GIC-500 Error Test Register" bitfld.long 0x4 1. "DISTRIBUTOR__39_GICD_ERRTESTR__1_1," "0,1" bitfld.long 0x4 0. "DISTRIBUTOR__39_GICD_ERRTESTR__0_1," "0,1" rgroup.long 0xC084++0x77 line.long 0x0 "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR0,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x4 "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR1,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x8 "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR2,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0xC "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR3,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x10 "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR4,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x14 "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR5,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x18 "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR6,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x1C "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR7,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x20 "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR8,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x24 "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR9,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x28 "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR10,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x2C "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR11,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x30 "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR12,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x34 "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR13,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x38 "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR14,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x3C "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR15,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x40 "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR16,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x44 "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR17,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x48 "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR18,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x4C "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR19,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x50 "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR20,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x54 "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR21,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x58 "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR22,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x5C "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR23,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x60 "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR24,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x64 "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR25,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x68 "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR26,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x6C "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR27,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x70 "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR28,GIC-500 Shared Peipheral Interrupt Status Registers" line.long 0x74 "GIC_DISTRIBUTOR_Distributor__40_GICD_SPISR29,GIC-500 Shared Peipheral Interrupt Status Registers" rgroup.long 0xFFD0++0x2F line.long 0x0 "GIC_DISTRIBUTOR_Distributor__41_GICD_PIDR4,Peripheral ID4 Register" line.long 0x4 "GIC_DISTRIBUTOR_Distributor__42_GICD_PIDR5,Peripheral ID5 Register" line.long 0x8 "GIC_DISTRIBUTOR_Distributor__43_GICD_PIDR6,Peripheral ID6 Register" line.long 0xC "GIC_DISTRIBUTOR_Distributor__44_GICD_PIDR7,Peripheral ID7 Register" line.long 0x10 "GIC_DISTRIBUTOR_Distributor__45_GICD_PIDR0,Peripheral ID0 Register" line.long 0x14 "GIC_DISTRIBUTOR_Distributor__46_GICD_PIDR1,Peripheral ID1 Register" line.long 0x18 "GIC_DISTRIBUTOR_Distributor__47_GICD_PIDR2,Peripheral ID2 Register" line.long 0x1C "GIC_DISTRIBUTOR_Distributor__48_GICD_PIDR3,Peripheral ID3 Register" line.long 0x20 "GIC_DISTRIBUTOR_Distributor__49_GICD_CIDR0,Component ID0 Register" line.long 0x24 "GIC_DISTRIBUTOR_Distributor__50_GICD_CIDR1,Component ID1 Register" line.long 0x28 "GIC_DISTRIBUTOR_Distributor__51_GICD_CIDR2,Component ID2 Register" line.long 0x2C "GIC_DISTRIBUTOR_Distributor__52_GICD_CIDR3,Component ID3 Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_GIC500SS_GIC_MESSAGE_BASED_SPIS (COMPUTE_CLUSTER0_GIC500SS_GIC_MESSAGE_BASED_SPIS)" base ad:0x1810000 rgroup.long 0x40++0x3 line.long 0x0 "GIC_MESSAGE_BASED_SPIS_Message_based_SPIs__1_GICD_SETSPI_NSR,Non-Secure SPI Set Register" hexmask.long.word 0x0 0.--9. 1. "MESSAGE_BASED_SPIS__1_GICD_SETSPI_NSR__0_10," rgroup.long 0x48++0x3 line.long 0x0 "GIC_MESSAGE_BASED_SPIS_Message_based_SPIs__2_GICD_CLRSPI_NSR,Non-Secure SPI Clear Register" hexmask.long.word 0x0 0.--9. 1. "MESSAGE_BASED_SPIS__2_GICD_CLRSPI_NSR__0_10," rgroup.long 0x50++0x3 line.long 0x0 "GIC_MESSAGE_BASED_SPIS_Message_based_SPIs__3_GICD_SETSPI_SR,Secure SPI Set Register" hexmask.long.word 0x0 0.--9. 1. "MESSAGE_BASED_SPIS__3_GICD_SETSPI_SR__0_10," rgroup.long 0x58++0x3 line.long 0x0 "GIC_MESSAGE_BASED_SPIS_Message_based_SPIs__4_GICD_CLRSPI_SR,Secure SPI Clear Register" hexmask.long.word 0x0 0.--9. 1. "MESSAGE_BASED_SPIS__4_GICD_CLRSPI_SR__0_10," tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_GIC500SS_GIC_ITS (COMPUTE_CLUSTER0_GIC500SS_GIC_ITS)" base ad:0x1820000 rgroup.long 0x0++0xF line.long 0x0 "GIC_ITS_ITS__1_GITS_CTLR,ITS Control Register" bitfld.long 0x0 31. "ITS__1_GITS_CTLR__31_1," "0,1" bitfld.long 0x0 0. "ITS__1_GITS_CTLR__0_1," "0,1" line.long 0x4 "GIC_ITS_ITS__2_GITS_IIDR,ITS Implementer Identification Register" hexmask.long.byte 0x4 24.--31. 1. "ITS__2_GITS_IIDR__24_8," hexmask.long.byte 0x4 16.--19. 1. "ITS__2_GITS_IIDR__16_4," newline hexmask.long.byte 0x4 12.--15. 1. "ITS__2_GITS_IIDR__12_4," hexmask.long.word 0x4 0.--11. 1. "ITS__2_GITS_IIDR__0_12," line.long 0x8 "GIC_ITS_ITS__3_GITS_TYPER_lower,ITS Type Register (lower)" hexmask.long.byte 0x8 24.--31. 1. "ITS__3_GITS_TYPER_LOWER__24_8," bitfld.long 0x8 19. "ITS__3_GITS_TYPER_LOWER__19_1," "0,1" newline hexmask.long.byte 0x8 13.--17. 1. "ITS__3_GITS_TYPER_LOWER__13_5," hexmask.long.byte 0x8 8.--12. 1. "ITS__3_GITS_TYPER_LOWER__8_5," newline hexmask.long.byte 0x8 4.--7. 1. "ITS__3_GITS_TYPER_LOWER__4_4," bitfld.long 0x8 3. "ITS__3_GITS_TYPER_LOWER__3_1," "0,1" newline bitfld.long 0x8 1. "ITS__3_GITS_TYPER_LOWER__1_1," "0,1" bitfld.long 0x8 0. "ITS__3_GITS_TYPER_LOWER__0_1," "0,1" line.long 0xC "GIC_ITS_ITS__4_GITS_TYPER_upper,ITS Type Register (upper)" rgroup.long 0x80++0x17 line.long 0x0 "GIC_ITS_ITS__5_GITS_CBASER_lower,Command Queue Control Register (lower)" hexmask.long.tbyte 0x0 12.--31. 1. "ITS__5_GITS_CBASER_LOWER__12_20," hexmask.long.byte 0x0 0.--7. 1. "ITS__5_GITS_CBASER_LOWER__0_8," line.long 0x4 "GIC_ITS_ITS__6_GITS_CBASER_upper,Command Queue Control Register (upper)" bitfld.long 0x4 31. "ITS__6_GITS_CBASER_UPPER__31_1," "0,1" bitfld.long 0x4 27.--29. "ITS__6_GITS_CBASER_UPPER__27_3," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 0.--15. 1. "ITS__6_GITS_CBASER_UPPER__0_16," line.long 0x8 "GIC_ITS_ITS__7_GITS_CWRITER_lower,Command Queue Write Pointer (lower)" hexmask.long.word 0x8 5.--19. 1. "ITS__7_GITS_CWRITER_LOWER__5_15," line.long 0xC "GIC_ITS_ITS__8_GITS_CWRITER_upper,Command Queue Write Pointer (upper)" line.long 0x10 "GIC_ITS_ITS__9_GITS_CREADR_lower,Command Queue Read Pointer (lower)" hexmask.long.word 0x10 5.--19. 1. "ITS__9_GITS_CREADR_LOWER__5_15," line.long 0x14 "GIC_ITS_ITS__10_GITS_CREADR_upper,Command Queue Read Pointer (upper)" rgroup.long 0x100++0x7 line.long 0x0 "GIC_ITS_ITS__11_GITS_BASER0_lower,ITS Table Control Register (lower)" hexmask.long.tbyte 0x0 12.--31. 1. "ITS__11_GITS_BASER0_LOWER__12_20," bitfld.long 0x0 8.--9. "ITS__11_GITS_BASER0_LOWER__8_2," "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "ITS__11_GITS_BASER0_LOWER__0_8," line.long 0x4 "GIC_ITS_ITS__12_GITS_BASER0_upper,ITS Table Control Register (upper)" bitfld.long 0x4 24.--26. "ITS__12_GITS_BASER0_UPPER__24_3," "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--23. 1. "ITS__12_GITS_BASER0_UPPER__16_8," newline hexmask.long.word 0x4 0.--15. 1. "ITS__12_GITS_BASER0_UPPER__0_16," rgroup.long 0xC000++0x1F line.long 0x0 "GIC_ITS_ITS__13_GITS_TRKCTLR,GIC-500 ITS Tracking Control Register" bitfld.long 0x0 1. "ITS__13_GITS_TRKCTLR__1_1," "0,1" bitfld.long 0x0 0. "ITS__13_GITS_TRKCTLR__0_1," "0,1" line.long 0x4 "GIC_ITS_ITS__14_GITS_TRKR,GIC-500 ITS Tracking Status Register" bitfld.long 0x4 5. "ITS__14_GITS_TRKR__5_1," "0,1" bitfld.long 0x4 4. "ITS__14_GITS_TRKR__4_1," "0,1" newline bitfld.long 0x4 3. "ITS__14_GITS_TRKR__3_1," "0,1" bitfld.long 0x4 2. "ITS__14_GITS_TRKR__2_1," "0,1" newline bitfld.long 0x4 1. "ITS__14_GITS_TRKR__1_1," "0,1" bitfld.long 0x4 0. "ITS__14_GITS_TRKR__0_1," "0,1" line.long 0x8 "GIC_ITS_ITS__15_GITS_TRKDIDR,GIC-500 ITS Tracked DID Register" hexmask.long.tbyte 0x8 0.--19. 1. "ITS__15_GITS_TRKDIDR__0_20," line.long 0xC "GIC_ITS_ITS__16_GITS_TRKPIDR,GIC-500 ITS Tracked PID Register" hexmask.long.word 0xC 0.--15. 1. "ITS__16_GITS_TRKPIDR__0_16," line.long 0x10 "GIC_ITS_ITS__17_GITS_TRKVIDR,GIC-500 ITS Tracked ID Register" hexmask.long.word 0x10 0.--15. 1. "ITS__17_GITS_TRKVIDR__0_16," line.long 0x14 "GIC_ITS_ITS__18_GITS_TRKTGTR,GIC-500 ITS Tracked TGT Register" hexmask.long.byte 0x14 0.--6. 1. "ITS__18_GITS_TRKTGTR__0_7," line.long 0x18 "GIC_ITS_ITS__19_GITS_TRKICR,GIC-500 ITE Cache Statistics Register" hexmask.long.word 0x18 16.--31. 1. "ITS__19_GITS_TRKICR__16_16," hexmask.long.word 0x18 0.--15. 1. "ITS__19_GITS_TRKICR__0_16," line.long 0x1C "GIC_ITS_ITS__20_GITS_TRKLCR,GIC-500 LPI Cache Statistics Register" hexmask.long.word 0x1C 16.--31. 1. "ITS__20_GITS_TRKLCR__16_16," hexmask.long.word 0x1C 0.--15. 1. "ITS__20_GITS_TRKLCR__0_16," rgroup.long 0xFFD0++0x2F line.long 0x0 "GIC_ITS_ITS__21_GITS_PIDR4,Peripheral ID4 Register" line.long 0x4 "GIC_ITS_ITS__22_GITS_PIDR5,Peripheral ID5 Register" line.long 0x8 "GIC_ITS_ITS__23_GITS_PIDR6,Peripheral ID6 Register" line.long 0xC "GIC_ITS_ITS__24_GITS_PIDR7,Peripheral ID7 Register" line.long 0x10 "GIC_ITS_ITS__25_GITS_PIDR0,Peripheral ID0 Register" line.long 0x14 "GIC_ITS_ITS__26_GITS_PIDR1,Peripheral ID1 Register" line.long 0x18 "GIC_ITS_ITS__27_GITS_PIDR2,Peripheral ID2 Register" line.long 0x1C "GIC_ITS_ITS__28_GITS_PIDR3,Peripheral ID3 Register" line.long 0x20 "GIC_ITS_ITS__29_GITS_CIDR0,Component ID0 Register" line.long 0x24 "GIC_ITS_ITS__30_GITS_CIDR1,Component ID1 Register" line.long 0x28 "GIC_ITS_ITS__31_GITS_CIDR2,Component ID2 Register" line.long 0x2C "GIC_ITS_ITS__32_GITS_CIDR3,Component ID3 Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_CONTROL_LPI_0 (COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_CONTROL_LPI_0)" base ad:0x1900000 rgroup.long 0x0++0xF line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_0_Redistributor_control_LPI_0__2_GICR_CTLR,Re-Distributor Control Register" bitfld.long 0x0 31. "REDISTRIBUTOR_CONTROL_LPI_0__2_GICR_CTLR__31_1," "0,1" newline bitfld.long 0x0 3. "REDISTRIBUTOR_CONTROL_LPI_0__2_GICR_CTLR__3_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_CONTROL_LPI_0__2_GICR_CTLR__0_1," "0,1" line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_0_Redistributor_control_LPI_0__3_GICR_IIDR,Re-Distributor Implementer Identification Register" hexmask.long.byte 0x4 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_0__3_GICR_IIDR__24_8," newline hexmask.long.byte 0x4 16.--19. 1. "REDISTRIBUTOR_CONTROL_LPI_0__3_GICR_IIDR__16_4," newline hexmask.long.byte 0x4 12.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_0__3_GICR_IIDR__12_4," newline hexmask.long.word 0x4 0.--11. 1. "REDISTRIBUTOR_CONTROL_LPI_0__3_GICR_IIDR__0_12," line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_0_Redistributor_control_LPI_0__4_GICR_TYPER_lower,Re-Distributor Type Register (lower)" hexmask.long.word 0x8 8.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_0__4_GICR_TYPER_LOWER__8_16," newline bitfld.long 0x8 4. "REDISTRIBUTOR_CONTROL_LPI_0__4_GICR_TYPER_LOWER__4_1," "0,1" newline bitfld.long 0x8 3. "REDISTRIBUTOR_CONTROL_LPI_0__4_GICR_TYPER_LOWER__3_1," "0,1" newline bitfld.long 0x8 1. "REDISTRIBUTOR_CONTROL_LPI_0__4_GICR_TYPER_LOWER__1_1," "0,1" newline bitfld.long 0x8 0. "REDISTRIBUTOR_CONTROL_LPI_0__4_GICR_TYPER_LOWER__0_1," "0,1" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_0_Redistributor_control_LPI_0__5_GICR_TYPER_upper,Re-Distributor Type Register (upper)" hexmask.long.byte 0xC 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_0__5_GICR_TYPER_UPPER__24_8," newline hexmask.long.byte 0xC 16.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_0__5_GICR_TYPER_UPPER__16_8," newline hexmask.long.byte 0xC 8.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_0__5_GICR_TYPER_UPPER__8_8," newline hexmask.long.byte 0xC 0.--7. 1. "REDISTRIBUTOR_CONTROL_LPI_0__5_GICR_TYPER_UPPER__0_8," rgroup.long 0x14++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_0_Redistributor_control_LPI_0__6_GICR_WAKER,Power Management Control Register" bitfld.long 0x0 31. "REDISTRIBUTOR_CONTROL_LPI_0__6_GICR_WAKER__31_1," "0,1" newline bitfld.long 0x0 2. "REDISTRIBUTOR_CONTROL_LPI_0__6_GICR_WAKER__2_1," "0,1" newline bitfld.long 0x0 1. "REDISTRIBUTOR_CONTROL_LPI_0__6_GICR_WAKER__1_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_CONTROL_LPI_0__6_GICR_WAKER__0_1," "0,1" rgroup.long 0x70++0xF line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_0_Redistributor_control_LPI_0__7_GICR_PROPBASER_lower,LPI Configuration Table Control Register (lower)" hexmask.long.tbyte 0x0 12.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_0__7_GICR_PROPBASER_LOWER__12_20," newline bitfld.long 0x0 7.--9. "REDISTRIBUTOR_CONTROL_LPI_0__7_GICR_PROPBASER_LOWER__7_3," "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "REDISTRIBUTOR_CONTROL_LPI_0__7_GICR_PROPBASER_LOWER__0_5," line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_0_Redistributor_control_LPI_0__8_GICR_PROPBASER_upper,LPI Configuration Table Control Register (upper)" hexmask.long.word 0x4 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_0__8_GICR_PROPBASER_UPPER__0_16," line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_0_Redistributor_control_LPI_0__9_GICR_PENDBASER_lower,LPI Pending Table Control Register (lower)" hexmask.long.word 0x8 16.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_0__9_GICR_PENDBASER_LOWER__16_16," newline bitfld.long 0x8 7.--9. "REDISTRIBUTOR_CONTROL_LPI_0__9_GICR_PENDBASER_LOWER__7_3," "0,1,2,3,4,5,6,7" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_0_Redistributor_control_LPI_0__10_GICR_PENDBASER_upper,LPI Pending Table Control Register (upper)" bitfld.long 0xC 30. "REDISTRIBUTOR_CONTROL_LPI_0__10_GICR_PENDBASER_UPPER__30_1," "0,1" newline hexmask.long.word 0xC 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_0__10_GICR_PENDBASER_UPPER__0_16," rgroup.long 0xFFD0++0x2F line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_0_Redistributor_control_LPI_0__11_GICR_PIDR4,Peripheral ID4 Register" line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_0_Redistributor_control_LPI_0__12_GICR_PIDR5,Peripheral ID5 Register" line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_0_Redistributor_control_LPI_0__13_GICR_PIDR6,Peripheral ID6 Register" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_0_Redistributor_control_LPI_0__14_GICR_PIDR7,Peripheral ID7 Register" line.long 0x10 "GIC_REDISTRIBUTOR_CONTROL_LPI_0_Redistributor_control_LPI_0__15_GICR_PIDR0,Peripheral ID0 Register" line.long 0x14 "GIC_REDISTRIBUTOR_CONTROL_LPI_0_Redistributor_control_LPI_0__16_GICR_PIDR1,Peripheral ID1 Register" line.long 0x18 "GIC_REDISTRIBUTOR_CONTROL_LPI_0_Redistributor_control_LPI_0__17_GICR_PIDR2,Peripheral ID2 Register" line.long 0x1C "GIC_REDISTRIBUTOR_CONTROL_LPI_0_Redistributor_control_LPI_0__18_GICR_PIDR3,Peripheral ID3 Register" line.long 0x20 "GIC_REDISTRIBUTOR_CONTROL_LPI_0_Redistributor_control_LPI_0__19_GICR_CIDR0,Component ID0 Register" line.long 0x24 "GIC_REDISTRIBUTOR_CONTROL_LPI_0_Redistributor_control_LPI_0__20_GICR_CIDR1,Component ID1 Register" line.long 0x28 "GIC_REDISTRIBUTOR_CONTROL_LPI_0_Redistributor_control_LPI_0__21_GICR_CIDR2,Component ID2 Register" line.long 0x2C "GIC_REDISTRIBUTOR_CONTROL_LPI_0_Redistributor_control_LPI_0__22_GICR_CIDR3,Component ID3 Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_SGI_PPI_0 (COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_SGI_PPI_0)" base ad:0x1910000 rgroup.long 0x80++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_0_Redistributor_SGI_PPI_0__1_GICR_IGROUPR0,Interrupt Group Registers" rgroup.long 0x100++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_0_Redistributor_SGI_PPI_0__2_GICR_ISENABLER0,Interrupt Set-Enable Registers" rgroup.long 0x180++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_0_Redistributor_SGI_PPI_0__3_GICR_ICENABLER0,Interrupt Clear-Enable Registers" rgroup.long 0x200++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_0_Redistributor_SGI_PPI_0__4_GICR_ISPENDR0,Interrupt Set-Pending Registers" rgroup.long 0x280++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_0_Redistributor_SGI_PPI_0__5_GICR_ICPENDR0,Interrupt Clear-Pending Registers" rgroup.long 0x300++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_0_Redistributor_SGI_PPI_0__6_GICR_ISACTIVER0,Interrupt Set-Active Registers" rgroup.long 0x380++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_0_Redistributor_SGI_PPI_0__7_GICR_ICACTIVER0,Interrupt Clear-Active Registers" rgroup.long 0x400++0x1F line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_0_Redistributor_SGI_PPI_0__8_GICR_IPRIORITYR0,Interrupt Priority Registers" line.long 0x4 "GIC_REDISTRIBUTOR_SGI_PPI_0_Redistributor_SGI_PPI_0__8_GICR_IPRIORITYR1,Interrupt Priority Registers" line.long 0x8 "GIC_REDISTRIBUTOR_SGI_PPI_0_Redistributor_SGI_PPI_0__8_GICR_IPRIORITYR2,Interrupt Priority Registers" line.long 0xC "GIC_REDISTRIBUTOR_SGI_PPI_0_Redistributor_SGI_PPI_0__8_GICR_IPRIORITYR3,Interrupt Priority Registers" line.long 0x10 "GIC_REDISTRIBUTOR_SGI_PPI_0_Redistributor_SGI_PPI_0__8_GICR_IPRIORITYR4,Interrupt Priority Registers" line.long 0x14 "GIC_REDISTRIBUTOR_SGI_PPI_0_Redistributor_SGI_PPI_0__8_GICR_IPRIORITYR5,Interrupt Priority Registers" line.long 0x18 "GIC_REDISTRIBUTOR_SGI_PPI_0_Redistributor_SGI_PPI_0__8_GICR_IPRIORITYR6,Interrupt Priority Registers" line.long 0x1C "GIC_REDISTRIBUTOR_SGI_PPI_0_Redistributor_SGI_PPI_0__8_GICR_IPRIORITYR7,Interrupt Priority Registers" rgroup.long 0xC00++0x7 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_0_Redistributor_SGI_PPI_0__9_GICR_ICFGR0,Interrupt Configuration Registers" line.long 0x4 "GIC_REDISTRIBUTOR_SGI_PPI_0_Redistributor_SGI_PPI_0__10_GICR_ICFGR1,Interrupt Configuration Registers" rgroup.long 0xD00++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_0_Redistributor_SGI_PPI_0__11_GICR_IGRPMODR0,Interrupt Group Modifier Registers" rgroup.long 0xE00++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_0_Redistributor_SGI_PPI_0__12_GICR_NSACR,Non-Secure Access Control Registers" rgroup.long 0xC000++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_0_Redistributor_SGI_PPI_0__13_GICR_MISCSTATUSR,GIC-500 Miscellaneous Status Register" bitfld.long 0x0 31. "REDISTRIBUTOR_SGI_PPI_0__13_GICR_MISCSTATUSR__31_1," "0,1" newline bitfld.long 0x0 2. "REDISTRIBUTOR_SGI_PPI_0__13_GICR_MISCSTATUSR__2_1," "0,1" newline bitfld.long 0x0 1. "REDISTRIBUTOR_SGI_PPI_0__13_GICR_MISCSTATUSR__1_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_SGI_PPI_0__13_GICR_MISCSTATUSR__0_1," "0,1" rgroup.long 0xC080++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_0_Redistributor_SGI_PPI_0__14_GICR_PPISR,GIC-500 Private Peripheral Interrupt Status Register" hexmask.long.word 0x0 16.--31. 1. "REDISTRIBUTOR_SGI_PPI_0__14_GICR_PPISR__16_16," tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_CONTROL_LPI_1 (COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_CONTROL_LPI_1)" base ad:0x1920000 rgroup.long 0x0++0xF line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_1_Redistributor_control_LPI_1__2_GICR_CTLR,Re-Distributor Control Register" bitfld.long 0x0 31. "REDISTRIBUTOR_CONTROL_LPI_1__2_GICR_CTLR__31_1," "0,1" newline bitfld.long 0x0 3. "REDISTRIBUTOR_CONTROL_LPI_1__2_GICR_CTLR__3_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_CONTROL_LPI_1__2_GICR_CTLR__0_1," "0,1" line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_1_Redistributor_control_LPI_1__3_GICR_IIDR,Re-Distributor Implementer Identification Register" hexmask.long.byte 0x4 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_1__3_GICR_IIDR__24_8," newline hexmask.long.byte 0x4 16.--19. 1. "REDISTRIBUTOR_CONTROL_LPI_1__3_GICR_IIDR__16_4," newline hexmask.long.byte 0x4 12.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_1__3_GICR_IIDR__12_4," newline hexmask.long.word 0x4 0.--11. 1. "REDISTRIBUTOR_CONTROL_LPI_1__3_GICR_IIDR__0_12," line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_1_Redistributor_control_LPI_1__4_GICR_TYPER_lower,Re-Distributor Type Register (lower)" hexmask.long.word 0x8 8.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_1__4_GICR_TYPER_LOWER__8_16," newline bitfld.long 0x8 4. "REDISTRIBUTOR_CONTROL_LPI_1__4_GICR_TYPER_LOWER__4_1," "0,1" newline bitfld.long 0x8 3. "REDISTRIBUTOR_CONTROL_LPI_1__4_GICR_TYPER_LOWER__3_1," "0,1" newline bitfld.long 0x8 1. "REDISTRIBUTOR_CONTROL_LPI_1__4_GICR_TYPER_LOWER__1_1," "0,1" newline bitfld.long 0x8 0. "REDISTRIBUTOR_CONTROL_LPI_1__4_GICR_TYPER_LOWER__0_1," "0,1" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_1_Redistributor_control_LPI_1__5_GICR_TYPER_upper,Re-Distributor Type Register (upper)" hexmask.long.byte 0xC 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_1__5_GICR_TYPER_UPPER__24_8," newline hexmask.long.byte 0xC 16.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_1__5_GICR_TYPER_UPPER__16_8," newline hexmask.long.byte 0xC 8.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_1__5_GICR_TYPER_UPPER__8_8," newline hexmask.long.byte 0xC 0.--7. 1. "REDISTRIBUTOR_CONTROL_LPI_1__5_GICR_TYPER_UPPER__0_8," rgroup.long 0x14++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_1_Redistributor_control_LPI_1__6_GICR_WAKER,Power Management Control Register" bitfld.long 0x0 31. "REDISTRIBUTOR_CONTROL_LPI_1__6_GICR_WAKER__31_1," "0,1" newline bitfld.long 0x0 2. "REDISTRIBUTOR_CONTROL_LPI_1__6_GICR_WAKER__2_1," "0,1" newline bitfld.long 0x0 1. "REDISTRIBUTOR_CONTROL_LPI_1__6_GICR_WAKER__1_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_CONTROL_LPI_1__6_GICR_WAKER__0_1," "0,1" rgroup.long 0x70++0xF line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_1_Redistributor_control_LPI_1__7_GICR_PROPBASER_lower,LPI Configuration Table Control Register (lower)" hexmask.long.tbyte 0x0 12.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_1__7_GICR_PROPBASER_LOWER__12_20," newline bitfld.long 0x0 7.--9. "REDISTRIBUTOR_CONTROL_LPI_1__7_GICR_PROPBASER_LOWER__7_3," "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "REDISTRIBUTOR_CONTROL_LPI_1__7_GICR_PROPBASER_LOWER__0_5," line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_1_Redistributor_control_LPI_1__8_GICR_PROPBASER_upper,LPI Configuration Table Control Register (upper)" hexmask.long.word 0x4 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_1__8_GICR_PROPBASER_UPPER__0_16," line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_1_Redistributor_control_LPI_1__9_GICR_PENDBASER_lower,LPI Pending Table Control Register (lower)" hexmask.long.word 0x8 16.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_1__9_GICR_PENDBASER_LOWER__16_16," newline bitfld.long 0x8 7.--9. "REDISTRIBUTOR_CONTROL_LPI_1__9_GICR_PENDBASER_LOWER__7_3," "0,1,2,3,4,5,6,7" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_1_Redistributor_control_LPI_1__10_GICR_PENDBASER_upper,LPI Pending Table Control Register (upper)" bitfld.long 0xC 30. "REDISTRIBUTOR_CONTROL_LPI_1__10_GICR_PENDBASER_UPPER__30_1," "0,1" newline hexmask.long.word 0xC 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_1__10_GICR_PENDBASER_UPPER__0_16," rgroup.long 0xFFD0++0x2F line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_1_Redistributor_control_LPI_1__11_GICR_PIDR4,Peripheral ID4 Register" line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_1_Redistributor_control_LPI_1__12_GICR_PIDR5,Peripheral ID5 Register" line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_1_Redistributor_control_LPI_1__13_GICR_PIDR6,Peripheral ID6 Register" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_1_Redistributor_control_LPI_1__14_GICR_PIDR7,Peripheral ID7 Register" line.long 0x10 "GIC_REDISTRIBUTOR_CONTROL_LPI_1_Redistributor_control_LPI_1__15_GICR_PIDR0,Peripheral ID0 Register" line.long 0x14 "GIC_REDISTRIBUTOR_CONTROL_LPI_1_Redistributor_control_LPI_1__16_GICR_PIDR1,Peripheral ID1 Register" line.long 0x18 "GIC_REDISTRIBUTOR_CONTROL_LPI_1_Redistributor_control_LPI_1__17_GICR_PIDR2,Peripheral ID2 Register" line.long 0x1C "GIC_REDISTRIBUTOR_CONTROL_LPI_1_Redistributor_control_LPI_1__18_GICR_PIDR3,Peripheral ID3 Register" line.long 0x20 "GIC_REDISTRIBUTOR_CONTROL_LPI_1_Redistributor_control_LPI_1__19_GICR_CIDR0,Component ID0 Register" line.long 0x24 "GIC_REDISTRIBUTOR_CONTROL_LPI_1_Redistributor_control_LPI_1__20_GICR_CIDR1,Component ID1 Register" line.long 0x28 "GIC_REDISTRIBUTOR_CONTROL_LPI_1_Redistributor_control_LPI_1__21_GICR_CIDR2,Component ID2 Register" line.long 0x2C "GIC_REDISTRIBUTOR_CONTROL_LPI_1_Redistributor_control_LPI_1__22_GICR_CIDR3,Component ID3 Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_SGI_PPI_1 (COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_SGI_PPI_1)" base ad:0x1930000 rgroup.long 0x80++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_1_Redistributor_SGI_PPI_1__1_GICR_IGROUPR0,Interrupt Group Registers" rgroup.long 0x100++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_1_Redistributor_SGI_PPI_1__2_GICR_ISENABLER0,Interrupt Set-Enable Registers" rgroup.long 0x180++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_1_Redistributor_SGI_PPI_1__3_GICR_ICENABLER0,Interrupt Clear-Enable Registers" rgroup.long 0x200++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_1_Redistributor_SGI_PPI_1__4_GICR_ISPENDR0,Interrupt Set-Pending Registers" rgroup.long 0x280++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_1_Redistributor_SGI_PPI_1__5_GICR_ICPENDR0,Interrupt Clear-Pending Registers" rgroup.long 0x300++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_1_Redistributor_SGI_PPI_1__6_GICR_ISACTIVER0,Interrupt Set-Active Registers" rgroup.long 0x380++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_1_Redistributor_SGI_PPI_1__7_GICR_ICACTIVER0,Interrupt Clear-Active Registers" rgroup.long 0x400++0x1F line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_1_Redistributor_SGI_PPI_1__8_GICR_IPRIORITYR0,Interrupt Priority Registers" line.long 0x4 "GIC_REDISTRIBUTOR_SGI_PPI_1_Redistributor_SGI_PPI_1__8_GICR_IPRIORITYR1,Interrupt Priority Registers" line.long 0x8 "GIC_REDISTRIBUTOR_SGI_PPI_1_Redistributor_SGI_PPI_1__8_GICR_IPRIORITYR2,Interrupt Priority Registers" line.long 0xC "GIC_REDISTRIBUTOR_SGI_PPI_1_Redistributor_SGI_PPI_1__8_GICR_IPRIORITYR3,Interrupt Priority Registers" line.long 0x10 "GIC_REDISTRIBUTOR_SGI_PPI_1_Redistributor_SGI_PPI_1__8_GICR_IPRIORITYR4,Interrupt Priority Registers" line.long 0x14 "GIC_REDISTRIBUTOR_SGI_PPI_1_Redistributor_SGI_PPI_1__8_GICR_IPRIORITYR5,Interrupt Priority Registers" line.long 0x18 "GIC_REDISTRIBUTOR_SGI_PPI_1_Redistributor_SGI_PPI_1__8_GICR_IPRIORITYR6,Interrupt Priority Registers" line.long 0x1C "GIC_REDISTRIBUTOR_SGI_PPI_1_Redistributor_SGI_PPI_1__8_GICR_IPRIORITYR7,Interrupt Priority Registers" rgroup.long 0xC00++0x7 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_1_Redistributor_SGI_PPI_1__9_GICR_ICFGR0,Interrupt Configuration Registers" line.long 0x4 "GIC_REDISTRIBUTOR_SGI_PPI_1_Redistributor_SGI_PPI_1__10_GICR_ICFGR1,Interrupt Configuration Registers" rgroup.long 0xD00++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_1_Redistributor_SGI_PPI_1__11_GICR_IGRPMODR0,Interrupt Group Modifier Registers" rgroup.long 0xE00++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_1_Redistributor_SGI_PPI_1__12_GICR_NSACR,Non-Secure Access Control Registers" rgroup.long 0xC000++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_1_Redistributor_SGI_PPI_1__13_GICR_MISCSTATUSR,GIC-500 Miscellaneous Status Register" bitfld.long 0x0 31. "REDISTRIBUTOR_SGI_PPI_1__13_GICR_MISCSTATUSR__31_1," "0,1" newline bitfld.long 0x0 2. "REDISTRIBUTOR_SGI_PPI_1__13_GICR_MISCSTATUSR__2_1," "0,1" newline bitfld.long 0x0 1. "REDISTRIBUTOR_SGI_PPI_1__13_GICR_MISCSTATUSR__1_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_SGI_PPI_1__13_GICR_MISCSTATUSR__0_1," "0,1" rgroup.long 0xC080++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_1_Redistributor_SGI_PPI_1__14_GICR_PPISR,GIC-500 Private Peripheral Interrupt Status Register" hexmask.long.word 0x0 16.--31. 1. "REDISTRIBUTOR_SGI_PPI_1__14_GICR_PPISR__16_16," tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_CONTROL_LPI_2 (COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_CONTROL_LPI_2)" base ad:0x1940000 rgroup.long 0x0++0xF line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_2_Redistributor_control_LPI_2__2_GICR_CTLR,Re-Distributor Control Register" bitfld.long 0x0 31. "REDISTRIBUTOR_CONTROL_LPI_2__2_GICR_CTLR__31_1," "0,1" newline bitfld.long 0x0 3. "REDISTRIBUTOR_CONTROL_LPI_2__2_GICR_CTLR__3_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_CONTROL_LPI_2__2_GICR_CTLR__0_1," "0,1" line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_2_Redistributor_control_LPI_2__3_GICR_IIDR,Re-Distributor Implementer Identification Register" hexmask.long.byte 0x4 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_2__3_GICR_IIDR__24_8," newline hexmask.long.byte 0x4 16.--19. 1. "REDISTRIBUTOR_CONTROL_LPI_2__3_GICR_IIDR__16_4," newline hexmask.long.byte 0x4 12.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_2__3_GICR_IIDR__12_4," newline hexmask.long.word 0x4 0.--11. 1. "REDISTRIBUTOR_CONTROL_LPI_2__3_GICR_IIDR__0_12," line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_2_Redistributor_control_LPI_2__4_GICR_TYPER_lower,Re-Distributor Type Register (lower)" hexmask.long.word 0x8 8.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_2__4_GICR_TYPER_LOWER__8_16," newline bitfld.long 0x8 4. "REDISTRIBUTOR_CONTROL_LPI_2__4_GICR_TYPER_LOWER__4_1," "0,1" newline bitfld.long 0x8 3. "REDISTRIBUTOR_CONTROL_LPI_2__4_GICR_TYPER_LOWER__3_1," "0,1" newline bitfld.long 0x8 1. "REDISTRIBUTOR_CONTROL_LPI_2__4_GICR_TYPER_LOWER__1_1," "0,1" newline bitfld.long 0x8 0. "REDISTRIBUTOR_CONTROL_LPI_2__4_GICR_TYPER_LOWER__0_1," "0,1" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_2_Redistributor_control_LPI_2__5_GICR_TYPER_upper,Re-Distributor Type Register (upper)" hexmask.long.byte 0xC 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_2__5_GICR_TYPER_UPPER__24_8," newline hexmask.long.byte 0xC 16.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_2__5_GICR_TYPER_UPPER__16_8," newline hexmask.long.byte 0xC 8.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_2__5_GICR_TYPER_UPPER__8_8," newline hexmask.long.byte 0xC 0.--7. 1. "REDISTRIBUTOR_CONTROL_LPI_2__5_GICR_TYPER_UPPER__0_8," rgroup.long 0x14++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_2_Redistributor_control_LPI_2__6_GICR_WAKER,Power Management Control Register" bitfld.long 0x0 31. "REDISTRIBUTOR_CONTROL_LPI_2__6_GICR_WAKER__31_1," "0,1" newline bitfld.long 0x0 2. "REDISTRIBUTOR_CONTROL_LPI_2__6_GICR_WAKER__2_1," "0,1" newline bitfld.long 0x0 1. "REDISTRIBUTOR_CONTROL_LPI_2__6_GICR_WAKER__1_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_CONTROL_LPI_2__6_GICR_WAKER__0_1," "0,1" rgroup.long 0x70++0xF line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_2_Redistributor_control_LPI_2__7_GICR_PROPBASER_lower,LPI Configuration Table Control Register (lower)" hexmask.long.tbyte 0x0 12.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_2__7_GICR_PROPBASER_LOWER__12_20," newline bitfld.long 0x0 7.--9. "REDISTRIBUTOR_CONTROL_LPI_2__7_GICR_PROPBASER_LOWER__7_3," "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "REDISTRIBUTOR_CONTROL_LPI_2__7_GICR_PROPBASER_LOWER__0_5," line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_2_Redistributor_control_LPI_2__8_GICR_PROPBASER_upper,LPI Configuration Table Control Register (upper)" hexmask.long.word 0x4 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_2__8_GICR_PROPBASER_UPPER__0_16," line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_2_Redistributor_control_LPI_2__9_GICR_PENDBASER_lower,LPI Pending Table Control Register (lower)" hexmask.long.word 0x8 16.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_2__9_GICR_PENDBASER_LOWER__16_16," newline bitfld.long 0x8 7.--9. "REDISTRIBUTOR_CONTROL_LPI_2__9_GICR_PENDBASER_LOWER__7_3," "0,1,2,3,4,5,6,7" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_2_Redistributor_control_LPI_2__10_GICR_PENDBASER_upper,LPI Pending Table Control Register (upper)" bitfld.long 0xC 30. "REDISTRIBUTOR_CONTROL_LPI_2__10_GICR_PENDBASER_UPPER__30_1," "0,1" newline hexmask.long.word 0xC 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_2__10_GICR_PENDBASER_UPPER__0_16," rgroup.long 0xFFD0++0x2F line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_2_Redistributor_control_LPI_2__11_GICR_PIDR4,Peripheral ID4 Register" line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_2_Redistributor_control_LPI_2__12_GICR_PIDR5,Peripheral ID5 Register" line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_2_Redistributor_control_LPI_2__13_GICR_PIDR6,Peripheral ID6 Register" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_2_Redistributor_control_LPI_2__14_GICR_PIDR7,Peripheral ID7 Register" line.long 0x10 "GIC_REDISTRIBUTOR_CONTROL_LPI_2_Redistributor_control_LPI_2__15_GICR_PIDR0,Peripheral ID0 Register" line.long 0x14 "GIC_REDISTRIBUTOR_CONTROL_LPI_2_Redistributor_control_LPI_2__16_GICR_PIDR1,Peripheral ID1 Register" line.long 0x18 "GIC_REDISTRIBUTOR_CONTROL_LPI_2_Redistributor_control_LPI_2__17_GICR_PIDR2,Peripheral ID2 Register" line.long 0x1C "GIC_REDISTRIBUTOR_CONTROL_LPI_2_Redistributor_control_LPI_2__18_GICR_PIDR3,Peripheral ID3 Register" line.long 0x20 "GIC_REDISTRIBUTOR_CONTROL_LPI_2_Redistributor_control_LPI_2__19_GICR_CIDR0,Component ID0 Register" line.long 0x24 "GIC_REDISTRIBUTOR_CONTROL_LPI_2_Redistributor_control_LPI_2__20_GICR_CIDR1,Component ID1 Register" line.long 0x28 "GIC_REDISTRIBUTOR_CONTROL_LPI_2_Redistributor_control_LPI_2__21_GICR_CIDR2,Component ID2 Register" line.long 0x2C "GIC_REDISTRIBUTOR_CONTROL_LPI_2_Redistributor_control_LPI_2__22_GICR_CIDR3,Component ID3 Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_SGI_PPI_2 (COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_SGI_PPI_2)" base ad:0x1950000 rgroup.long 0x80++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_2_Redistributor_SGI_PPI_2__1_GICR_IGROUPR0,Interrupt Group Registers" rgroup.long 0x100++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_2_Redistributor_SGI_PPI_2__2_GICR_ISENABLER0,Interrupt Set-Enable Registers" rgroup.long 0x180++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_2_Redistributor_SGI_PPI_2__3_GICR_ICENABLER0,Interrupt Clear-Enable Registers" rgroup.long 0x200++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_2_Redistributor_SGI_PPI_2__4_GICR_ISPENDR0,Interrupt Set-Pending Registers" rgroup.long 0x280++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_2_Redistributor_SGI_PPI_2__5_GICR_ICPENDR0,Interrupt Clear-Pending Registers" rgroup.long 0x300++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_2_Redistributor_SGI_PPI_2__6_GICR_ISACTIVER0,Interrupt Set-Active Registers" rgroup.long 0x380++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_2_Redistributor_SGI_PPI_2__7_GICR_ICACTIVER0,Interrupt Clear-Active Registers" rgroup.long 0x400++0x1F line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_2_Redistributor_SGI_PPI_2__8_GICR_IPRIORITYR0,Interrupt Priority Registers" line.long 0x4 "GIC_REDISTRIBUTOR_SGI_PPI_2_Redistributor_SGI_PPI_2__8_GICR_IPRIORITYR1,Interrupt Priority Registers" line.long 0x8 "GIC_REDISTRIBUTOR_SGI_PPI_2_Redistributor_SGI_PPI_2__8_GICR_IPRIORITYR2,Interrupt Priority Registers" line.long 0xC "GIC_REDISTRIBUTOR_SGI_PPI_2_Redistributor_SGI_PPI_2__8_GICR_IPRIORITYR3,Interrupt Priority Registers" line.long 0x10 "GIC_REDISTRIBUTOR_SGI_PPI_2_Redistributor_SGI_PPI_2__8_GICR_IPRIORITYR4,Interrupt Priority Registers" line.long 0x14 "GIC_REDISTRIBUTOR_SGI_PPI_2_Redistributor_SGI_PPI_2__8_GICR_IPRIORITYR5,Interrupt Priority Registers" line.long 0x18 "GIC_REDISTRIBUTOR_SGI_PPI_2_Redistributor_SGI_PPI_2__8_GICR_IPRIORITYR6,Interrupt Priority Registers" line.long 0x1C "GIC_REDISTRIBUTOR_SGI_PPI_2_Redistributor_SGI_PPI_2__8_GICR_IPRIORITYR7,Interrupt Priority Registers" rgroup.long 0xC00++0x7 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_2_Redistributor_SGI_PPI_2__9_GICR_ICFGR0,Interrupt Configuration Registers" line.long 0x4 "GIC_REDISTRIBUTOR_SGI_PPI_2_Redistributor_SGI_PPI_2__10_GICR_ICFGR1,Interrupt Configuration Registers" rgroup.long 0xD00++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_2_Redistributor_SGI_PPI_2__11_GICR_IGRPMODR0,Interrupt Group Modifier Registers" rgroup.long 0xE00++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_2_Redistributor_SGI_PPI_2__12_GICR_NSACR,Non-Secure Access Control Registers" rgroup.long 0xC000++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_2_Redistributor_SGI_PPI_2__13_GICR_MISCSTATUSR,GIC-500 Miscellaneous Status Register" bitfld.long 0x0 31. "REDISTRIBUTOR_SGI_PPI_2__13_GICR_MISCSTATUSR__31_1," "0,1" newline bitfld.long 0x0 2. "REDISTRIBUTOR_SGI_PPI_2__13_GICR_MISCSTATUSR__2_1," "0,1" newline bitfld.long 0x0 1. "REDISTRIBUTOR_SGI_PPI_2__13_GICR_MISCSTATUSR__1_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_SGI_PPI_2__13_GICR_MISCSTATUSR__0_1," "0,1" rgroup.long 0xC080++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_2_Redistributor_SGI_PPI_2__14_GICR_PPISR,GIC-500 Private Peripheral Interrupt Status Register" hexmask.long.word 0x0 16.--31. 1. "REDISTRIBUTOR_SGI_PPI_2__14_GICR_PPISR__16_16," tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_CONTROL_LPI_3 (COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_CONTROL_LPI_3)" base ad:0x1960000 rgroup.long 0x0++0xF line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_3_Redistributor_control_LPI_3__2_GICR_CTLR,Re-Distributor Control Register" bitfld.long 0x0 31. "REDISTRIBUTOR_CONTROL_LPI_3__2_GICR_CTLR__31_1," "0,1" newline bitfld.long 0x0 3. "REDISTRIBUTOR_CONTROL_LPI_3__2_GICR_CTLR__3_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_CONTROL_LPI_3__2_GICR_CTLR__0_1," "0,1" line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_3_Redistributor_control_LPI_3__3_GICR_IIDR,Re-Distributor Implementer Identification Register" hexmask.long.byte 0x4 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_3__3_GICR_IIDR__24_8," newline hexmask.long.byte 0x4 16.--19. 1. "REDISTRIBUTOR_CONTROL_LPI_3__3_GICR_IIDR__16_4," newline hexmask.long.byte 0x4 12.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_3__3_GICR_IIDR__12_4," newline hexmask.long.word 0x4 0.--11. 1. "REDISTRIBUTOR_CONTROL_LPI_3__3_GICR_IIDR__0_12," line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_3_Redistributor_control_LPI_3__4_GICR_TYPER_lower,Re-Distributor Type Register (lower)" hexmask.long.word 0x8 8.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_3__4_GICR_TYPER_LOWER__8_16," newline bitfld.long 0x8 4. "REDISTRIBUTOR_CONTROL_LPI_3__4_GICR_TYPER_LOWER__4_1," "0,1" newline bitfld.long 0x8 3. "REDISTRIBUTOR_CONTROL_LPI_3__4_GICR_TYPER_LOWER__3_1," "0,1" newline bitfld.long 0x8 1. "REDISTRIBUTOR_CONTROL_LPI_3__4_GICR_TYPER_LOWER__1_1," "0,1" newline bitfld.long 0x8 0. "REDISTRIBUTOR_CONTROL_LPI_3__4_GICR_TYPER_LOWER__0_1," "0,1" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_3_Redistributor_control_LPI_3__5_GICR_TYPER_upper,Re-Distributor Type Register (upper)" hexmask.long.byte 0xC 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_3__5_GICR_TYPER_UPPER__24_8," newline hexmask.long.byte 0xC 16.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_3__5_GICR_TYPER_UPPER__16_8," newline hexmask.long.byte 0xC 8.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_3__5_GICR_TYPER_UPPER__8_8," newline hexmask.long.byte 0xC 0.--7. 1. "REDISTRIBUTOR_CONTROL_LPI_3__5_GICR_TYPER_UPPER__0_8," rgroup.long 0x14++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_3_Redistributor_control_LPI_3__6_GICR_WAKER,Power Management Control Register" bitfld.long 0x0 31. "REDISTRIBUTOR_CONTROL_LPI_3__6_GICR_WAKER__31_1," "0,1" newline bitfld.long 0x0 2. "REDISTRIBUTOR_CONTROL_LPI_3__6_GICR_WAKER__2_1," "0,1" newline bitfld.long 0x0 1. "REDISTRIBUTOR_CONTROL_LPI_3__6_GICR_WAKER__1_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_CONTROL_LPI_3__6_GICR_WAKER__0_1," "0,1" rgroup.long 0x70++0xF line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_3_Redistributor_control_LPI_3__7_GICR_PROPBASER_lower,LPI Configuration Table Control Register (lower)" hexmask.long.tbyte 0x0 12.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_3__7_GICR_PROPBASER_LOWER__12_20," newline bitfld.long 0x0 7.--9. "REDISTRIBUTOR_CONTROL_LPI_3__7_GICR_PROPBASER_LOWER__7_3," "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "REDISTRIBUTOR_CONTROL_LPI_3__7_GICR_PROPBASER_LOWER__0_5," line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_3_Redistributor_control_LPI_3__8_GICR_PROPBASER_upper,LPI Configuration Table Control Register (upper)" hexmask.long.word 0x4 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_3__8_GICR_PROPBASER_UPPER__0_16," line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_3_Redistributor_control_LPI_3__9_GICR_PENDBASER_lower,LPI Pending Table Control Register (lower)" hexmask.long.word 0x8 16.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_3__9_GICR_PENDBASER_LOWER__16_16," newline bitfld.long 0x8 7.--9. "REDISTRIBUTOR_CONTROL_LPI_3__9_GICR_PENDBASER_LOWER__7_3," "0,1,2,3,4,5,6,7" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_3_Redistributor_control_LPI_3__10_GICR_PENDBASER_upper,LPI Pending Table Control Register (upper)" bitfld.long 0xC 30. "REDISTRIBUTOR_CONTROL_LPI_3__10_GICR_PENDBASER_UPPER__30_1," "0,1" newline hexmask.long.word 0xC 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_3__10_GICR_PENDBASER_UPPER__0_16," rgroup.long 0xFFD0++0x2F line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_3_Redistributor_control_LPI_3__11_GICR_PIDR4,Peripheral ID4 Register" line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_3_Redistributor_control_LPI_3__12_GICR_PIDR5,Peripheral ID5 Register" line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_3_Redistributor_control_LPI_3__13_GICR_PIDR6,Peripheral ID6 Register" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_3_Redistributor_control_LPI_3__14_GICR_PIDR7,Peripheral ID7 Register" line.long 0x10 "GIC_REDISTRIBUTOR_CONTROL_LPI_3_Redistributor_control_LPI_3__15_GICR_PIDR0,Peripheral ID0 Register" line.long 0x14 "GIC_REDISTRIBUTOR_CONTROL_LPI_3_Redistributor_control_LPI_3__16_GICR_PIDR1,Peripheral ID1 Register" line.long 0x18 "GIC_REDISTRIBUTOR_CONTROL_LPI_3_Redistributor_control_LPI_3__17_GICR_PIDR2,Peripheral ID2 Register" line.long 0x1C "GIC_REDISTRIBUTOR_CONTROL_LPI_3_Redistributor_control_LPI_3__18_GICR_PIDR3,Peripheral ID3 Register" line.long 0x20 "GIC_REDISTRIBUTOR_CONTROL_LPI_3_Redistributor_control_LPI_3__19_GICR_CIDR0,Component ID0 Register" line.long 0x24 "GIC_REDISTRIBUTOR_CONTROL_LPI_3_Redistributor_control_LPI_3__20_GICR_CIDR1,Component ID1 Register" line.long 0x28 "GIC_REDISTRIBUTOR_CONTROL_LPI_3_Redistributor_control_LPI_3__21_GICR_CIDR2,Component ID2 Register" line.long 0x2C "GIC_REDISTRIBUTOR_CONTROL_LPI_3_Redistributor_control_LPI_3__22_GICR_CIDR3,Component ID3 Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_SGI_PPI_3 (COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_SGI_PPI_3)" base ad:0x1970000 rgroup.long 0x80++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_3_Redistributor_SGI_PPI_3__1_GICR_IGROUPR0,Interrupt Group Registers" rgroup.long 0x100++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_3_Redistributor_SGI_PPI_3__2_GICR_ISENABLER0,Interrupt Set-Enable Registers" rgroup.long 0x180++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_3_Redistributor_SGI_PPI_3__3_GICR_ICENABLER0,Interrupt Clear-Enable Registers" rgroup.long 0x200++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_3_Redistributor_SGI_PPI_3__4_GICR_ISPENDR0,Interrupt Set-Pending Registers" rgroup.long 0x280++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_3_Redistributor_SGI_PPI_3__5_GICR_ICPENDR0,Interrupt Clear-Pending Registers" rgroup.long 0x300++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_3_Redistributor_SGI_PPI_3__6_GICR_ISACTIVER0,Interrupt Set-Active Registers" rgroup.long 0x380++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_3_Redistributor_SGI_PPI_3__7_GICR_ICACTIVER0,Interrupt Clear-Active Registers" rgroup.long 0x400++0x1F line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_3_Redistributor_SGI_PPI_3__8_GICR_IPRIORITYR0,Interrupt Priority Registers" line.long 0x4 "GIC_REDISTRIBUTOR_SGI_PPI_3_Redistributor_SGI_PPI_3__8_GICR_IPRIORITYR1,Interrupt Priority Registers" line.long 0x8 "GIC_REDISTRIBUTOR_SGI_PPI_3_Redistributor_SGI_PPI_3__8_GICR_IPRIORITYR2,Interrupt Priority Registers" line.long 0xC "GIC_REDISTRIBUTOR_SGI_PPI_3_Redistributor_SGI_PPI_3__8_GICR_IPRIORITYR3,Interrupt Priority Registers" line.long 0x10 "GIC_REDISTRIBUTOR_SGI_PPI_3_Redistributor_SGI_PPI_3__8_GICR_IPRIORITYR4,Interrupt Priority Registers" line.long 0x14 "GIC_REDISTRIBUTOR_SGI_PPI_3_Redistributor_SGI_PPI_3__8_GICR_IPRIORITYR5,Interrupt Priority Registers" line.long 0x18 "GIC_REDISTRIBUTOR_SGI_PPI_3_Redistributor_SGI_PPI_3__8_GICR_IPRIORITYR6,Interrupt Priority Registers" line.long 0x1C "GIC_REDISTRIBUTOR_SGI_PPI_3_Redistributor_SGI_PPI_3__8_GICR_IPRIORITYR7,Interrupt Priority Registers" rgroup.long 0xC00++0x7 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_3_Redistributor_SGI_PPI_3__9_GICR_ICFGR0,Interrupt Configuration Registers" line.long 0x4 "GIC_REDISTRIBUTOR_SGI_PPI_3_Redistributor_SGI_PPI_3__10_GICR_ICFGR1,Interrupt Configuration Registers" rgroup.long 0xD00++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_3_Redistributor_SGI_PPI_3__11_GICR_IGRPMODR0,Interrupt Group Modifier Registers" rgroup.long 0xE00++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_3_Redistributor_SGI_PPI_3__12_GICR_NSACR,Non-Secure Access Control Registers" rgroup.long 0xC000++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_3_Redistributor_SGI_PPI_3__13_GICR_MISCSTATUSR,GIC-500 Miscellaneous Status Register" bitfld.long 0x0 31. "REDISTRIBUTOR_SGI_PPI_3__13_GICR_MISCSTATUSR__31_1," "0,1" newline bitfld.long 0x0 2. "REDISTRIBUTOR_SGI_PPI_3__13_GICR_MISCSTATUSR__2_1," "0,1" newline bitfld.long 0x0 1. "REDISTRIBUTOR_SGI_PPI_3__13_GICR_MISCSTATUSR__1_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_SGI_PPI_3__13_GICR_MISCSTATUSR__0_1," "0,1" rgroup.long 0xC080++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_3_Redistributor_SGI_PPI_3__14_GICR_PPISR,GIC-500 Private Peripheral Interrupt Status Register" hexmask.long.word 0x0 16.--31. 1. "REDISTRIBUTOR_SGI_PPI_3__14_GICR_PPISR__16_16," tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_CONTROL_LPI_4 (COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_CONTROL_LPI_4)" base ad:0x1980000 rgroup.long 0x0++0xF line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_4_Redistributor_control_LPI_4__2_GICR_CTLR,Re-Distributor Control Register" bitfld.long 0x0 31. "REDISTRIBUTOR_CONTROL_LPI_4__2_GICR_CTLR__31_1," "0,1" newline bitfld.long 0x0 3. "REDISTRIBUTOR_CONTROL_LPI_4__2_GICR_CTLR__3_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_CONTROL_LPI_4__2_GICR_CTLR__0_1," "0,1" line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_4_Redistributor_control_LPI_4__3_GICR_IIDR,Re-Distributor Implementer Identification Register" hexmask.long.byte 0x4 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_4__3_GICR_IIDR__24_8," newline hexmask.long.byte 0x4 16.--19. 1. "REDISTRIBUTOR_CONTROL_LPI_4__3_GICR_IIDR__16_4," newline hexmask.long.byte 0x4 12.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_4__3_GICR_IIDR__12_4," newline hexmask.long.word 0x4 0.--11. 1. "REDISTRIBUTOR_CONTROL_LPI_4__3_GICR_IIDR__0_12," line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_4_Redistributor_control_LPI_4__4_GICR_TYPER_lower,Re-Distributor Type Register (lower)" hexmask.long.word 0x8 8.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_4__4_GICR_TYPER_LOWER__8_16," newline bitfld.long 0x8 4. "REDISTRIBUTOR_CONTROL_LPI_4__4_GICR_TYPER_LOWER__4_1," "0,1" newline bitfld.long 0x8 3. "REDISTRIBUTOR_CONTROL_LPI_4__4_GICR_TYPER_LOWER__3_1," "0,1" newline bitfld.long 0x8 1. "REDISTRIBUTOR_CONTROL_LPI_4__4_GICR_TYPER_LOWER__1_1," "0,1" newline bitfld.long 0x8 0. "REDISTRIBUTOR_CONTROL_LPI_4__4_GICR_TYPER_LOWER__0_1," "0,1" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_4_Redistributor_control_LPI_4__5_GICR_TYPER_upper,Re-Distributor Type Register (upper)" hexmask.long.byte 0xC 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_4__5_GICR_TYPER_UPPER__24_8," newline hexmask.long.byte 0xC 16.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_4__5_GICR_TYPER_UPPER__16_8," newline hexmask.long.byte 0xC 8.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_4__5_GICR_TYPER_UPPER__8_8," newline hexmask.long.byte 0xC 0.--7. 1. "REDISTRIBUTOR_CONTROL_LPI_4__5_GICR_TYPER_UPPER__0_8," rgroup.long 0x14++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_4_Redistributor_control_LPI_4__6_GICR_WAKER,Power Management Control Register" bitfld.long 0x0 31. "REDISTRIBUTOR_CONTROL_LPI_4__6_GICR_WAKER__31_1," "0,1" newline bitfld.long 0x0 2. "REDISTRIBUTOR_CONTROL_LPI_4__6_GICR_WAKER__2_1," "0,1" newline bitfld.long 0x0 1. "REDISTRIBUTOR_CONTROL_LPI_4__6_GICR_WAKER__1_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_CONTROL_LPI_4__6_GICR_WAKER__0_1," "0,1" rgroup.long 0x70++0xF line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_4_Redistributor_control_LPI_4__7_GICR_PROPBASER_lower,LPI Configuration Table Control Register (lower)" hexmask.long.tbyte 0x0 12.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_4__7_GICR_PROPBASER_LOWER__12_20," newline bitfld.long 0x0 7.--9. "REDISTRIBUTOR_CONTROL_LPI_4__7_GICR_PROPBASER_LOWER__7_3," "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "REDISTRIBUTOR_CONTROL_LPI_4__7_GICR_PROPBASER_LOWER__0_5," line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_4_Redistributor_control_LPI_4__8_GICR_PROPBASER_upper,LPI Configuration Table Control Register (upper)" hexmask.long.word 0x4 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_4__8_GICR_PROPBASER_UPPER__0_16," line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_4_Redistributor_control_LPI_4__9_GICR_PENDBASER_lower,LPI Pending Table Control Register (lower)" hexmask.long.word 0x8 16.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_4__9_GICR_PENDBASER_LOWER__16_16," newline bitfld.long 0x8 7.--9. "REDISTRIBUTOR_CONTROL_LPI_4__9_GICR_PENDBASER_LOWER__7_3," "0,1,2,3,4,5,6,7" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_4_Redistributor_control_LPI_4__10_GICR_PENDBASER_upper,LPI Pending Table Control Register (upper)" bitfld.long 0xC 30. "REDISTRIBUTOR_CONTROL_LPI_4__10_GICR_PENDBASER_UPPER__30_1," "0,1" newline hexmask.long.word 0xC 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_4__10_GICR_PENDBASER_UPPER__0_16," rgroup.long 0xFFD0++0x2F line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_4_Redistributor_control_LPI_4__11_GICR_PIDR4,Peripheral ID4 Register" line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_4_Redistributor_control_LPI_4__12_GICR_PIDR5,Peripheral ID5 Register" line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_4_Redistributor_control_LPI_4__13_GICR_PIDR6,Peripheral ID6 Register" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_4_Redistributor_control_LPI_4__14_GICR_PIDR7,Peripheral ID7 Register" line.long 0x10 "GIC_REDISTRIBUTOR_CONTROL_LPI_4_Redistributor_control_LPI_4__15_GICR_PIDR0,Peripheral ID0 Register" line.long 0x14 "GIC_REDISTRIBUTOR_CONTROL_LPI_4_Redistributor_control_LPI_4__16_GICR_PIDR1,Peripheral ID1 Register" line.long 0x18 "GIC_REDISTRIBUTOR_CONTROL_LPI_4_Redistributor_control_LPI_4__17_GICR_PIDR2,Peripheral ID2 Register" line.long 0x1C "GIC_REDISTRIBUTOR_CONTROL_LPI_4_Redistributor_control_LPI_4__18_GICR_PIDR3,Peripheral ID3 Register" line.long 0x20 "GIC_REDISTRIBUTOR_CONTROL_LPI_4_Redistributor_control_LPI_4__19_GICR_CIDR0,Component ID0 Register" line.long 0x24 "GIC_REDISTRIBUTOR_CONTROL_LPI_4_Redistributor_control_LPI_4__20_GICR_CIDR1,Component ID1 Register" line.long 0x28 "GIC_REDISTRIBUTOR_CONTROL_LPI_4_Redistributor_control_LPI_4__21_GICR_CIDR2,Component ID2 Register" line.long 0x2C "GIC_REDISTRIBUTOR_CONTROL_LPI_4_Redistributor_control_LPI_4__22_GICR_CIDR3,Component ID3 Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_SGI_PPI_4 (COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_SGI_PPI_4)" base ad:0x1990000 rgroup.long 0x80++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_4_Redistributor_SGI_PPI_4__1_GICR_IGROUPR0,Interrupt Group Registers" rgroup.long 0x100++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_4_Redistributor_SGI_PPI_4__2_GICR_ISENABLER0,Interrupt Set-Enable Registers" rgroup.long 0x180++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_4_Redistributor_SGI_PPI_4__3_GICR_ICENABLER0,Interrupt Clear-Enable Registers" rgroup.long 0x200++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_4_Redistributor_SGI_PPI_4__4_GICR_ISPENDR0,Interrupt Set-Pending Registers" rgroup.long 0x280++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_4_Redistributor_SGI_PPI_4__5_GICR_ICPENDR0,Interrupt Clear-Pending Registers" rgroup.long 0x300++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_4_Redistributor_SGI_PPI_4__6_GICR_ISACTIVER0,Interrupt Set-Active Registers" rgroup.long 0x380++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_4_Redistributor_SGI_PPI_4__7_GICR_ICACTIVER0,Interrupt Clear-Active Registers" rgroup.long 0x400++0x1F line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_4_Redistributor_SGI_PPI_4__8_GICR_IPRIORITYR0,Interrupt Priority Registers" line.long 0x4 "GIC_REDISTRIBUTOR_SGI_PPI_4_Redistributor_SGI_PPI_4__8_GICR_IPRIORITYR1,Interrupt Priority Registers" line.long 0x8 "GIC_REDISTRIBUTOR_SGI_PPI_4_Redistributor_SGI_PPI_4__8_GICR_IPRIORITYR2,Interrupt Priority Registers" line.long 0xC "GIC_REDISTRIBUTOR_SGI_PPI_4_Redistributor_SGI_PPI_4__8_GICR_IPRIORITYR3,Interrupt Priority Registers" line.long 0x10 "GIC_REDISTRIBUTOR_SGI_PPI_4_Redistributor_SGI_PPI_4__8_GICR_IPRIORITYR4,Interrupt Priority Registers" line.long 0x14 "GIC_REDISTRIBUTOR_SGI_PPI_4_Redistributor_SGI_PPI_4__8_GICR_IPRIORITYR5,Interrupt Priority Registers" line.long 0x18 "GIC_REDISTRIBUTOR_SGI_PPI_4_Redistributor_SGI_PPI_4__8_GICR_IPRIORITYR6,Interrupt Priority Registers" line.long 0x1C "GIC_REDISTRIBUTOR_SGI_PPI_4_Redistributor_SGI_PPI_4__8_GICR_IPRIORITYR7,Interrupt Priority Registers" rgroup.long 0xC00++0x7 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_4_Redistributor_SGI_PPI_4__9_GICR_ICFGR0,Interrupt Configuration Registers" line.long 0x4 "GIC_REDISTRIBUTOR_SGI_PPI_4_Redistributor_SGI_PPI_4__10_GICR_ICFGR1,Interrupt Configuration Registers" rgroup.long 0xD00++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_4_Redistributor_SGI_PPI_4__11_GICR_IGRPMODR0,Interrupt Group Modifier Registers" rgroup.long 0xE00++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_4_Redistributor_SGI_PPI_4__12_GICR_NSACR,Non-Secure Access Control Registers" rgroup.long 0xC000++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_4_Redistributor_SGI_PPI_4__13_GICR_MISCSTATUSR,GIC-500 Miscellaneous Status Register" bitfld.long 0x0 31. "REDISTRIBUTOR_SGI_PPI_4__13_GICR_MISCSTATUSR__31_1," "0,1" newline bitfld.long 0x0 2. "REDISTRIBUTOR_SGI_PPI_4__13_GICR_MISCSTATUSR__2_1," "0,1" newline bitfld.long 0x0 1. "REDISTRIBUTOR_SGI_PPI_4__13_GICR_MISCSTATUSR__1_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_SGI_PPI_4__13_GICR_MISCSTATUSR__0_1," "0,1" rgroup.long 0xC080++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_4_Redistributor_SGI_PPI_4__14_GICR_PPISR,GIC-500 Private Peripheral Interrupt Status Register" hexmask.long.word 0x0 16.--31. 1. "REDISTRIBUTOR_SGI_PPI_4__14_GICR_PPISR__16_16," tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_CONTROL_LPI_5 (COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_CONTROL_LPI_5)" base ad:0x19A0000 rgroup.long 0x0++0xF line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_5_Redistributor_control_LPI_5__2_GICR_CTLR,Re-Distributor Control Register" bitfld.long 0x0 31. "REDISTRIBUTOR_CONTROL_LPI_5__2_GICR_CTLR__31_1," "0,1" newline bitfld.long 0x0 3. "REDISTRIBUTOR_CONTROL_LPI_5__2_GICR_CTLR__3_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_CONTROL_LPI_5__2_GICR_CTLR__0_1," "0,1" line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_5_Redistributor_control_LPI_5__3_GICR_IIDR,Re-Distributor Implementer Identification Register" hexmask.long.byte 0x4 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_5__3_GICR_IIDR__24_8," newline hexmask.long.byte 0x4 16.--19. 1. "REDISTRIBUTOR_CONTROL_LPI_5__3_GICR_IIDR__16_4," newline hexmask.long.byte 0x4 12.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_5__3_GICR_IIDR__12_4," newline hexmask.long.word 0x4 0.--11. 1. "REDISTRIBUTOR_CONTROL_LPI_5__3_GICR_IIDR__0_12," line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_5_Redistributor_control_LPI_5__4_GICR_TYPER_lower,Re-Distributor Type Register (lower)" hexmask.long.word 0x8 8.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_5__4_GICR_TYPER_LOWER__8_16," newline bitfld.long 0x8 4. "REDISTRIBUTOR_CONTROL_LPI_5__4_GICR_TYPER_LOWER__4_1," "0,1" newline bitfld.long 0x8 3. "REDISTRIBUTOR_CONTROL_LPI_5__4_GICR_TYPER_LOWER__3_1," "0,1" newline bitfld.long 0x8 1. "REDISTRIBUTOR_CONTROL_LPI_5__4_GICR_TYPER_LOWER__1_1," "0,1" newline bitfld.long 0x8 0. "REDISTRIBUTOR_CONTROL_LPI_5__4_GICR_TYPER_LOWER__0_1," "0,1" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_5_Redistributor_control_LPI_5__5_GICR_TYPER_upper,Re-Distributor Type Register (upper)" hexmask.long.byte 0xC 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_5__5_GICR_TYPER_UPPER__24_8," newline hexmask.long.byte 0xC 16.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_5__5_GICR_TYPER_UPPER__16_8," newline hexmask.long.byte 0xC 8.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_5__5_GICR_TYPER_UPPER__8_8," newline hexmask.long.byte 0xC 0.--7. 1. "REDISTRIBUTOR_CONTROL_LPI_5__5_GICR_TYPER_UPPER__0_8," rgroup.long 0x14++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_5_Redistributor_control_LPI_5__6_GICR_WAKER,Power Management Control Register" bitfld.long 0x0 31. "REDISTRIBUTOR_CONTROL_LPI_5__6_GICR_WAKER__31_1," "0,1" newline bitfld.long 0x0 2. "REDISTRIBUTOR_CONTROL_LPI_5__6_GICR_WAKER__2_1," "0,1" newline bitfld.long 0x0 1. "REDISTRIBUTOR_CONTROL_LPI_5__6_GICR_WAKER__1_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_CONTROL_LPI_5__6_GICR_WAKER__0_1," "0,1" rgroup.long 0x70++0xF line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_5_Redistributor_control_LPI_5__7_GICR_PROPBASER_lower,LPI Configuration Table Control Register (lower)" hexmask.long.tbyte 0x0 12.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_5__7_GICR_PROPBASER_LOWER__12_20," newline bitfld.long 0x0 7.--9. "REDISTRIBUTOR_CONTROL_LPI_5__7_GICR_PROPBASER_LOWER__7_3," "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "REDISTRIBUTOR_CONTROL_LPI_5__7_GICR_PROPBASER_LOWER__0_5," line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_5_Redistributor_control_LPI_5__8_GICR_PROPBASER_upper,LPI Configuration Table Control Register (upper)" hexmask.long.word 0x4 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_5__8_GICR_PROPBASER_UPPER__0_16," line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_5_Redistributor_control_LPI_5__9_GICR_PENDBASER_lower,LPI Pending Table Control Register (lower)" hexmask.long.word 0x8 16.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_5__9_GICR_PENDBASER_LOWER__16_16," newline bitfld.long 0x8 7.--9. "REDISTRIBUTOR_CONTROL_LPI_5__9_GICR_PENDBASER_LOWER__7_3," "0,1,2,3,4,5,6,7" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_5_Redistributor_control_LPI_5__10_GICR_PENDBASER_upper,LPI Pending Table Control Register (upper)" bitfld.long 0xC 30. "REDISTRIBUTOR_CONTROL_LPI_5__10_GICR_PENDBASER_UPPER__30_1," "0,1" newline hexmask.long.word 0xC 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_5__10_GICR_PENDBASER_UPPER__0_16," rgroup.long 0xFFD0++0x2F line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_5_Redistributor_control_LPI_5__11_GICR_PIDR4,Peripheral ID4 Register" line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_5_Redistributor_control_LPI_5__12_GICR_PIDR5,Peripheral ID5 Register" line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_5_Redistributor_control_LPI_5__13_GICR_PIDR6,Peripheral ID6 Register" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_5_Redistributor_control_LPI_5__14_GICR_PIDR7,Peripheral ID7 Register" line.long 0x10 "GIC_REDISTRIBUTOR_CONTROL_LPI_5_Redistributor_control_LPI_5__15_GICR_PIDR0,Peripheral ID0 Register" line.long 0x14 "GIC_REDISTRIBUTOR_CONTROL_LPI_5_Redistributor_control_LPI_5__16_GICR_PIDR1,Peripheral ID1 Register" line.long 0x18 "GIC_REDISTRIBUTOR_CONTROL_LPI_5_Redistributor_control_LPI_5__17_GICR_PIDR2,Peripheral ID2 Register" line.long 0x1C "GIC_REDISTRIBUTOR_CONTROL_LPI_5_Redistributor_control_LPI_5__18_GICR_PIDR3,Peripheral ID3 Register" line.long 0x20 "GIC_REDISTRIBUTOR_CONTROL_LPI_5_Redistributor_control_LPI_5__19_GICR_CIDR0,Component ID0 Register" line.long 0x24 "GIC_REDISTRIBUTOR_CONTROL_LPI_5_Redistributor_control_LPI_5__20_GICR_CIDR1,Component ID1 Register" line.long 0x28 "GIC_REDISTRIBUTOR_CONTROL_LPI_5_Redistributor_control_LPI_5__21_GICR_CIDR2,Component ID2 Register" line.long 0x2C "GIC_REDISTRIBUTOR_CONTROL_LPI_5_Redistributor_control_LPI_5__22_GICR_CIDR3,Component ID3 Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_SGI_PPI_5 (COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_SGI_PPI_5)" base ad:0x19B0000 rgroup.long 0x80++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_5_Redistributor_SGI_PPI_5__1_GICR_IGROUPR0,Interrupt Group Registers" rgroup.long 0x100++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_5_Redistributor_SGI_PPI_5__2_GICR_ISENABLER0,Interrupt Set-Enable Registers" rgroup.long 0x180++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_5_Redistributor_SGI_PPI_5__3_GICR_ICENABLER0,Interrupt Clear-Enable Registers" rgroup.long 0x200++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_5_Redistributor_SGI_PPI_5__4_GICR_ISPENDR0,Interrupt Set-Pending Registers" rgroup.long 0x280++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_5_Redistributor_SGI_PPI_5__5_GICR_ICPENDR0,Interrupt Clear-Pending Registers" rgroup.long 0x300++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_5_Redistributor_SGI_PPI_5__6_GICR_ISACTIVER0,Interrupt Set-Active Registers" rgroup.long 0x380++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_5_Redistributor_SGI_PPI_5__7_GICR_ICACTIVER0,Interrupt Clear-Active Registers" rgroup.long 0x400++0x1F line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_5_Redistributor_SGI_PPI_5__8_GICR_IPRIORITYR0,Interrupt Priority Registers" line.long 0x4 "GIC_REDISTRIBUTOR_SGI_PPI_5_Redistributor_SGI_PPI_5__8_GICR_IPRIORITYR1,Interrupt Priority Registers" line.long 0x8 "GIC_REDISTRIBUTOR_SGI_PPI_5_Redistributor_SGI_PPI_5__8_GICR_IPRIORITYR2,Interrupt Priority Registers" line.long 0xC "GIC_REDISTRIBUTOR_SGI_PPI_5_Redistributor_SGI_PPI_5__8_GICR_IPRIORITYR3,Interrupt Priority Registers" line.long 0x10 "GIC_REDISTRIBUTOR_SGI_PPI_5_Redistributor_SGI_PPI_5__8_GICR_IPRIORITYR4,Interrupt Priority Registers" line.long 0x14 "GIC_REDISTRIBUTOR_SGI_PPI_5_Redistributor_SGI_PPI_5__8_GICR_IPRIORITYR5,Interrupt Priority Registers" line.long 0x18 "GIC_REDISTRIBUTOR_SGI_PPI_5_Redistributor_SGI_PPI_5__8_GICR_IPRIORITYR6,Interrupt Priority Registers" line.long 0x1C "GIC_REDISTRIBUTOR_SGI_PPI_5_Redistributor_SGI_PPI_5__8_GICR_IPRIORITYR7,Interrupt Priority Registers" rgroup.long 0xC00++0x7 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_5_Redistributor_SGI_PPI_5__9_GICR_ICFGR0,Interrupt Configuration Registers" line.long 0x4 "GIC_REDISTRIBUTOR_SGI_PPI_5_Redistributor_SGI_PPI_5__10_GICR_ICFGR1,Interrupt Configuration Registers" rgroup.long 0xD00++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_5_Redistributor_SGI_PPI_5__11_GICR_IGRPMODR0,Interrupt Group Modifier Registers" rgroup.long 0xE00++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_5_Redistributor_SGI_PPI_5__12_GICR_NSACR,Non-Secure Access Control Registers" rgroup.long 0xC000++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_5_Redistributor_SGI_PPI_5__13_GICR_MISCSTATUSR,GIC-500 Miscellaneous Status Register" bitfld.long 0x0 31. "REDISTRIBUTOR_SGI_PPI_5__13_GICR_MISCSTATUSR__31_1," "0,1" newline bitfld.long 0x0 2. "REDISTRIBUTOR_SGI_PPI_5__13_GICR_MISCSTATUSR__2_1," "0,1" newline bitfld.long 0x0 1. "REDISTRIBUTOR_SGI_PPI_5__13_GICR_MISCSTATUSR__1_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_SGI_PPI_5__13_GICR_MISCSTATUSR__0_1," "0,1" rgroup.long 0xC080++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_5_Redistributor_SGI_PPI_5__14_GICR_PPISR,GIC-500 Private Peripheral Interrupt Status Register" hexmask.long.word 0x0 16.--31. 1. "REDISTRIBUTOR_SGI_PPI_5__14_GICR_PPISR__16_16," tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_CONTROL_LPI_6 (COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_CONTROL_LPI_6)" base ad:0x19C0000 rgroup.long 0x0++0xF line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_6_Redistributor_control_LPI_6__2_GICR_CTLR,Re-Distributor Control Register" bitfld.long 0x0 31. "REDISTRIBUTOR_CONTROL_LPI_6__2_GICR_CTLR__31_1," "0,1" newline bitfld.long 0x0 3. "REDISTRIBUTOR_CONTROL_LPI_6__2_GICR_CTLR__3_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_CONTROL_LPI_6__2_GICR_CTLR__0_1," "0,1" line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_6_Redistributor_control_LPI_6__3_GICR_IIDR,Re-Distributor Implementer Identification Register" hexmask.long.byte 0x4 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_6__3_GICR_IIDR__24_8," newline hexmask.long.byte 0x4 16.--19. 1. "REDISTRIBUTOR_CONTROL_LPI_6__3_GICR_IIDR__16_4," newline hexmask.long.byte 0x4 12.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_6__3_GICR_IIDR__12_4," newline hexmask.long.word 0x4 0.--11. 1. "REDISTRIBUTOR_CONTROL_LPI_6__3_GICR_IIDR__0_12," line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_6_Redistributor_control_LPI_6__4_GICR_TYPER_lower,Re-Distributor Type Register (lower)" hexmask.long.word 0x8 8.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_6__4_GICR_TYPER_LOWER__8_16," newline bitfld.long 0x8 4. "REDISTRIBUTOR_CONTROL_LPI_6__4_GICR_TYPER_LOWER__4_1," "0,1" newline bitfld.long 0x8 3. "REDISTRIBUTOR_CONTROL_LPI_6__4_GICR_TYPER_LOWER__3_1," "0,1" newline bitfld.long 0x8 1. "REDISTRIBUTOR_CONTROL_LPI_6__4_GICR_TYPER_LOWER__1_1," "0,1" newline bitfld.long 0x8 0. "REDISTRIBUTOR_CONTROL_LPI_6__4_GICR_TYPER_LOWER__0_1," "0,1" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_6_Redistributor_control_LPI_6__5_GICR_TYPER_upper,Re-Distributor Type Register (upper)" hexmask.long.byte 0xC 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_6__5_GICR_TYPER_UPPER__24_8," newline hexmask.long.byte 0xC 16.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_6__5_GICR_TYPER_UPPER__16_8," newline hexmask.long.byte 0xC 8.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_6__5_GICR_TYPER_UPPER__8_8," newline hexmask.long.byte 0xC 0.--7. 1. "REDISTRIBUTOR_CONTROL_LPI_6__5_GICR_TYPER_UPPER__0_8," rgroup.long 0x14++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_6_Redistributor_control_LPI_6__6_GICR_WAKER,Power Management Control Register" bitfld.long 0x0 31. "REDISTRIBUTOR_CONTROL_LPI_6__6_GICR_WAKER__31_1," "0,1" newline bitfld.long 0x0 2. "REDISTRIBUTOR_CONTROL_LPI_6__6_GICR_WAKER__2_1," "0,1" newline bitfld.long 0x0 1. "REDISTRIBUTOR_CONTROL_LPI_6__6_GICR_WAKER__1_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_CONTROL_LPI_6__6_GICR_WAKER__0_1," "0,1" rgroup.long 0x70++0xF line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_6_Redistributor_control_LPI_6__7_GICR_PROPBASER_lower,LPI Configuration Table Control Register (lower)" hexmask.long.tbyte 0x0 12.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_6__7_GICR_PROPBASER_LOWER__12_20," newline bitfld.long 0x0 7.--9. "REDISTRIBUTOR_CONTROL_LPI_6__7_GICR_PROPBASER_LOWER__7_3," "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "REDISTRIBUTOR_CONTROL_LPI_6__7_GICR_PROPBASER_LOWER__0_5," line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_6_Redistributor_control_LPI_6__8_GICR_PROPBASER_upper,LPI Configuration Table Control Register (upper)" hexmask.long.word 0x4 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_6__8_GICR_PROPBASER_UPPER__0_16," line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_6_Redistributor_control_LPI_6__9_GICR_PENDBASER_lower,LPI Pending Table Control Register (lower)" hexmask.long.word 0x8 16.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_6__9_GICR_PENDBASER_LOWER__16_16," newline bitfld.long 0x8 7.--9. "REDISTRIBUTOR_CONTROL_LPI_6__9_GICR_PENDBASER_LOWER__7_3," "0,1,2,3,4,5,6,7" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_6_Redistributor_control_LPI_6__10_GICR_PENDBASER_upper,LPI Pending Table Control Register (upper)" bitfld.long 0xC 30. "REDISTRIBUTOR_CONTROL_LPI_6__10_GICR_PENDBASER_UPPER__30_1," "0,1" newline hexmask.long.word 0xC 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_6__10_GICR_PENDBASER_UPPER__0_16," rgroup.long 0xFFD0++0x2F line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_6_Redistributor_control_LPI_6__11_GICR_PIDR4,Peripheral ID4 Register" line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_6_Redistributor_control_LPI_6__12_GICR_PIDR5,Peripheral ID5 Register" line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_6_Redistributor_control_LPI_6__13_GICR_PIDR6,Peripheral ID6 Register" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_6_Redistributor_control_LPI_6__14_GICR_PIDR7,Peripheral ID7 Register" line.long 0x10 "GIC_REDISTRIBUTOR_CONTROL_LPI_6_Redistributor_control_LPI_6__15_GICR_PIDR0,Peripheral ID0 Register" line.long 0x14 "GIC_REDISTRIBUTOR_CONTROL_LPI_6_Redistributor_control_LPI_6__16_GICR_PIDR1,Peripheral ID1 Register" line.long 0x18 "GIC_REDISTRIBUTOR_CONTROL_LPI_6_Redistributor_control_LPI_6__17_GICR_PIDR2,Peripheral ID2 Register" line.long 0x1C "GIC_REDISTRIBUTOR_CONTROL_LPI_6_Redistributor_control_LPI_6__18_GICR_PIDR3,Peripheral ID3 Register" line.long 0x20 "GIC_REDISTRIBUTOR_CONTROL_LPI_6_Redistributor_control_LPI_6__19_GICR_CIDR0,Component ID0 Register" line.long 0x24 "GIC_REDISTRIBUTOR_CONTROL_LPI_6_Redistributor_control_LPI_6__20_GICR_CIDR1,Component ID1 Register" line.long 0x28 "GIC_REDISTRIBUTOR_CONTROL_LPI_6_Redistributor_control_LPI_6__21_GICR_CIDR2,Component ID2 Register" line.long 0x2C "GIC_REDISTRIBUTOR_CONTROL_LPI_6_Redistributor_control_LPI_6__22_GICR_CIDR3,Component ID3 Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_SGI_PPI_6 (COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_SGI_PPI_6)" base ad:0x19D0000 rgroup.long 0x80++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_6_Redistributor_SGI_PPI_6__1_GICR_IGROUPR0,Interrupt Group Registers" rgroup.long 0x100++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_6_Redistributor_SGI_PPI_6__2_GICR_ISENABLER0,Interrupt Set-Enable Registers" rgroup.long 0x180++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_6_Redistributor_SGI_PPI_6__3_GICR_ICENABLER0,Interrupt Clear-Enable Registers" rgroup.long 0x200++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_6_Redistributor_SGI_PPI_6__4_GICR_ISPENDR0,Interrupt Set-Pending Registers" rgroup.long 0x280++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_6_Redistributor_SGI_PPI_6__5_GICR_ICPENDR0,Interrupt Clear-Pending Registers" rgroup.long 0x300++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_6_Redistributor_SGI_PPI_6__6_GICR_ISACTIVER0,Interrupt Set-Active Registers" rgroup.long 0x380++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_6_Redistributor_SGI_PPI_6__7_GICR_ICACTIVER0,Interrupt Clear-Active Registers" rgroup.long 0x400++0x1F line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_6_Redistributor_SGI_PPI_6__8_GICR_IPRIORITYR0,Interrupt Priority Registers" line.long 0x4 "GIC_REDISTRIBUTOR_SGI_PPI_6_Redistributor_SGI_PPI_6__8_GICR_IPRIORITYR1,Interrupt Priority Registers" line.long 0x8 "GIC_REDISTRIBUTOR_SGI_PPI_6_Redistributor_SGI_PPI_6__8_GICR_IPRIORITYR2,Interrupt Priority Registers" line.long 0xC "GIC_REDISTRIBUTOR_SGI_PPI_6_Redistributor_SGI_PPI_6__8_GICR_IPRIORITYR3,Interrupt Priority Registers" line.long 0x10 "GIC_REDISTRIBUTOR_SGI_PPI_6_Redistributor_SGI_PPI_6__8_GICR_IPRIORITYR4,Interrupt Priority Registers" line.long 0x14 "GIC_REDISTRIBUTOR_SGI_PPI_6_Redistributor_SGI_PPI_6__8_GICR_IPRIORITYR5,Interrupt Priority Registers" line.long 0x18 "GIC_REDISTRIBUTOR_SGI_PPI_6_Redistributor_SGI_PPI_6__8_GICR_IPRIORITYR6,Interrupt Priority Registers" line.long 0x1C "GIC_REDISTRIBUTOR_SGI_PPI_6_Redistributor_SGI_PPI_6__8_GICR_IPRIORITYR7,Interrupt Priority Registers" rgroup.long 0xC00++0x7 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_6_Redistributor_SGI_PPI_6__9_GICR_ICFGR0,Interrupt Configuration Registers" line.long 0x4 "GIC_REDISTRIBUTOR_SGI_PPI_6_Redistributor_SGI_PPI_6__10_GICR_ICFGR1,Interrupt Configuration Registers" rgroup.long 0xD00++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_6_Redistributor_SGI_PPI_6__11_GICR_IGRPMODR0,Interrupt Group Modifier Registers" rgroup.long 0xE00++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_6_Redistributor_SGI_PPI_6__12_GICR_NSACR,Non-Secure Access Control Registers" rgroup.long 0xC000++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_6_Redistributor_SGI_PPI_6__13_GICR_MISCSTATUSR,GIC-500 Miscellaneous Status Register" bitfld.long 0x0 31. "REDISTRIBUTOR_SGI_PPI_6__13_GICR_MISCSTATUSR__31_1," "0,1" newline bitfld.long 0x0 2. "REDISTRIBUTOR_SGI_PPI_6__13_GICR_MISCSTATUSR__2_1," "0,1" newline bitfld.long 0x0 1. "REDISTRIBUTOR_SGI_PPI_6__13_GICR_MISCSTATUSR__1_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_SGI_PPI_6__13_GICR_MISCSTATUSR__0_1," "0,1" rgroup.long 0xC080++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_6_Redistributor_SGI_PPI_6__14_GICR_PPISR,GIC-500 Private Peripheral Interrupt Status Register" hexmask.long.word 0x0 16.--31. 1. "REDISTRIBUTOR_SGI_PPI_6__14_GICR_PPISR__16_16," tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_CONTROL_LPI_7 (COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_CONTROL_LPI_7)" base ad:0x19E0000 rgroup.long 0x0++0xF line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_7_Redistributor_control_LPI_7__2_GICR_CTLR,Re-Distributor Control Register" bitfld.long 0x0 31. "REDISTRIBUTOR_CONTROL_LPI_7__2_GICR_CTLR__31_1," "0,1" newline bitfld.long 0x0 3. "REDISTRIBUTOR_CONTROL_LPI_7__2_GICR_CTLR__3_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_CONTROL_LPI_7__2_GICR_CTLR__0_1," "0,1" line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_7_Redistributor_control_LPI_7__3_GICR_IIDR,Re-Distributor Implementer Identification Register" hexmask.long.byte 0x4 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_7__3_GICR_IIDR__24_8," newline hexmask.long.byte 0x4 16.--19. 1. "REDISTRIBUTOR_CONTROL_LPI_7__3_GICR_IIDR__16_4," newline hexmask.long.byte 0x4 12.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_7__3_GICR_IIDR__12_4," newline hexmask.long.word 0x4 0.--11. 1. "REDISTRIBUTOR_CONTROL_LPI_7__3_GICR_IIDR__0_12," line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_7_Redistributor_control_LPI_7__4_GICR_TYPER_lower,Re-Distributor Type Register (lower)" hexmask.long.word 0x8 8.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_7__4_GICR_TYPER_LOWER__8_16," newline bitfld.long 0x8 4. "REDISTRIBUTOR_CONTROL_LPI_7__4_GICR_TYPER_LOWER__4_1," "0,1" newline bitfld.long 0x8 3. "REDISTRIBUTOR_CONTROL_LPI_7__4_GICR_TYPER_LOWER__3_1," "0,1" newline bitfld.long 0x8 1. "REDISTRIBUTOR_CONTROL_LPI_7__4_GICR_TYPER_LOWER__1_1," "0,1" newline bitfld.long 0x8 0. "REDISTRIBUTOR_CONTROL_LPI_7__4_GICR_TYPER_LOWER__0_1," "0,1" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_7_Redistributor_control_LPI_7__5_GICR_TYPER_upper,Re-Distributor Type Register (upper)" hexmask.long.byte 0xC 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_7__5_GICR_TYPER_UPPER__24_8," newline hexmask.long.byte 0xC 16.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_7__5_GICR_TYPER_UPPER__16_8," newline hexmask.long.byte 0xC 8.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_7__5_GICR_TYPER_UPPER__8_8," newline hexmask.long.byte 0xC 0.--7. 1. "REDISTRIBUTOR_CONTROL_LPI_7__5_GICR_TYPER_UPPER__0_8," rgroup.long 0x14++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_7_Redistributor_control_LPI_7__6_GICR_WAKER,Power Management Control Register" bitfld.long 0x0 31. "REDISTRIBUTOR_CONTROL_LPI_7__6_GICR_WAKER__31_1," "0,1" newline bitfld.long 0x0 2. "REDISTRIBUTOR_CONTROL_LPI_7__6_GICR_WAKER__2_1," "0,1" newline bitfld.long 0x0 1. "REDISTRIBUTOR_CONTROL_LPI_7__6_GICR_WAKER__1_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_CONTROL_LPI_7__6_GICR_WAKER__0_1," "0,1" rgroup.long 0x70++0xF line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_7_Redistributor_control_LPI_7__7_GICR_PROPBASER_lower,LPI Configuration Table Control Register (lower)" hexmask.long.tbyte 0x0 12.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_7__7_GICR_PROPBASER_LOWER__12_20," newline bitfld.long 0x0 7.--9. "REDISTRIBUTOR_CONTROL_LPI_7__7_GICR_PROPBASER_LOWER__7_3," "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "REDISTRIBUTOR_CONTROL_LPI_7__7_GICR_PROPBASER_LOWER__0_5," line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_7_Redistributor_control_LPI_7__8_GICR_PROPBASER_upper,LPI Configuration Table Control Register (upper)" hexmask.long.word 0x4 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_7__8_GICR_PROPBASER_UPPER__0_16," line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_7_Redistributor_control_LPI_7__9_GICR_PENDBASER_lower,LPI Pending Table Control Register (lower)" hexmask.long.word 0x8 16.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_7__9_GICR_PENDBASER_LOWER__16_16," newline bitfld.long 0x8 7.--9. "REDISTRIBUTOR_CONTROL_LPI_7__9_GICR_PENDBASER_LOWER__7_3," "0,1,2,3,4,5,6,7" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_7_Redistributor_control_LPI_7__10_GICR_PENDBASER_upper,LPI Pending Table Control Register (upper)" bitfld.long 0xC 30. "REDISTRIBUTOR_CONTROL_LPI_7__10_GICR_PENDBASER_UPPER__30_1," "0,1" newline hexmask.long.word 0xC 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_7__10_GICR_PENDBASER_UPPER__0_16," rgroup.long 0xFFD0++0x2F line.long 0x0 "GIC_REDISTRIBUTOR_CONTROL_LPI_7_Redistributor_control_LPI_7__11_GICR_PIDR4,Peripheral ID4 Register" line.long 0x4 "GIC_REDISTRIBUTOR_CONTROL_LPI_7_Redistributor_control_LPI_7__12_GICR_PIDR5,Peripheral ID5 Register" line.long 0x8 "GIC_REDISTRIBUTOR_CONTROL_LPI_7_Redistributor_control_LPI_7__13_GICR_PIDR6,Peripheral ID6 Register" line.long 0xC "GIC_REDISTRIBUTOR_CONTROL_LPI_7_Redistributor_control_LPI_7__14_GICR_PIDR7,Peripheral ID7 Register" line.long 0x10 "GIC_REDISTRIBUTOR_CONTROL_LPI_7_Redistributor_control_LPI_7__15_GICR_PIDR0,Peripheral ID0 Register" line.long 0x14 "GIC_REDISTRIBUTOR_CONTROL_LPI_7_Redistributor_control_LPI_7__16_GICR_PIDR1,Peripheral ID1 Register" line.long 0x18 "GIC_REDISTRIBUTOR_CONTROL_LPI_7_Redistributor_control_LPI_7__17_GICR_PIDR2,Peripheral ID2 Register" line.long 0x1C "GIC_REDISTRIBUTOR_CONTROL_LPI_7_Redistributor_control_LPI_7__18_GICR_PIDR3,Peripheral ID3 Register" line.long 0x20 "GIC_REDISTRIBUTOR_CONTROL_LPI_7_Redistributor_control_LPI_7__19_GICR_CIDR0,Component ID0 Register" line.long 0x24 "GIC_REDISTRIBUTOR_CONTROL_LPI_7_Redistributor_control_LPI_7__20_GICR_CIDR1,Component ID1 Register" line.long 0x28 "GIC_REDISTRIBUTOR_CONTROL_LPI_7_Redistributor_control_LPI_7__21_GICR_CIDR2,Component ID2 Register" line.long 0x2C "GIC_REDISTRIBUTOR_CONTROL_LPI_7_Redistributor_control_LPI_7__22_GICR_CIDR3,Component ID3 Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_SGI_PPI_7 (COMPUTE_CLUSTER0_GIC500SS_GIC_REDISTRIBUTOR_SGI_PPI_7)" base ad:0x19F0000 rgroup.long 0x80++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_7_Redistributor_SGI_PPI_7__1_GICR_IGROUPR0,Interrupt Group Registers" rgroup.long 0x100++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_7_Redistributor_SGI_PPI_7__2_GICR_ISENABLER0,Interrupt Set-Enable Registers" rgroup.long 0x180++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_7_Redistributor_SGI_PPI_7__3_GICR_ICENABLER0,Interrupt Clear-Enable Registers" rgroup.long 0x200++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_7_Redistributor_SGI_PPI_7__4_GICR_ISPENDR0,Interrupt Set-Pending Registers" rgroup.long 0x280++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_7_Redistributor_SGI_PPI_7__5_GICR_ICPENDR0,Interrupt Clear-Pending Registers" rgroup.long 0x300++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_7_Redistributor_SGI_PPI_7__6_GICR_ISACTIVER0,Interrupt Set-Active Registers" rgroup.long 0x380++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_7_Redistributor_SGI_PPI_7__7_GICR_ICACTIVER0,Interrupt Clear-Active Registers" rgroup.long 0x400++0x1F line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_7_Redistributor_SGI_PPI_7__8_GICR_IPRIORITYR0,Interrupt Priority Registers" line.long 0x4 "GIC_REDISTRIBUTOR_SGI_PPI_7_Redistributor_SGI_PPI_7__8_GICR_IPRIORITYR1,Interrupt Priority Registers" line.long 0x8 "GIC_REDISTRIBUTOR_SGI_PPI_7_Redistributor_SGI_PPI_7__8_GICR_IPRIORITYR2,Interrupt Priority Registers" line.long 0xC "GIC_REDISTRIBUTOR_SGI_PPI_7_Redistributor_SGI_PPI_7__8_GICR_IPRIORITYR3,Interrupt Priority Registers" line.long 0x10 "GIC_REDISTRIBUTOR_SGI_PPI_7_Redistributor_SGI_PPI_7__8_GICR_IPRIORITYR4,Interrupt Priority Registers" line.long 0x14 "GIC_REDISTRIBUTOR_SGI_PPI_7_Redistributor_SGI_PPI_7__8_GICR_IPRIORITYR5,Interrupt Priority Registers" line.long 0x18 "GIC_REDISTRIBUTOR_SGI_PPI_7_Redistributor_SGI_PPI_7__8_GICR_IPRIORITYR6,Interrupt Priority Registers" line.long 0x1C "GIC_REDISTRIBUTOR_SGI_PPI_7_Redistributor_SGI_PPI_7__8_GICR_IPRIORITYR7,Interrupt Priority Registers" rgroup.long 0xC00++0x7 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_7_Redistributor_SGI_PPI_7__9_GICR_ICFGR0,Interrupt Configuration Registers" line.long 0x4 "GIC_REDISTRIBUTOR_SGI_PPI_7_Redistributor_SGI_PPI_7__10_GICR_ICFGR1,Interrupt Configuration Registers" rgroup.long 0xD00++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_7_Redistributor_SGI_PPI_7__11_GICR_IGRPMODR0,Interrupt Group Modifier Registers" rgroup.long 0xE00++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_7_Redistributor_SGI_PPI_7__12_GICR_NSACR,Non-Secure Access Control Registers" rgroup.long 0xC000++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_7_Redistributor_SGI_PPI_7__13_GICR_MISCSTATUSR,GIC-500 Miscellaneous Status Register" bitfld.long 0x0 31. "REDISTRIBUTOR_SGI_PPI_7__13_GICR_MISCSTATUSR__31_1," "0,1" newline bitfld.long 0x0 2. "REDISTRIBUTOR_SGI_PPI_7__13_GICR_MISCSTATUSR__2_1," "0,1" newline bitfld.long 0x0 1. "REDISTRIBUTOR_SGI_PPI_7__13_GICR_MISCSTATUSR__1_1," "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_SGI_PPI_7__13_GICR_MISCSTATUSR__0_1," "0,1" rgroup.long 0xC080++0x3 line.long 0x0 "GIC_REDISTRIBUTOR_SGI_PPI_7_Redistributor_SGI_PPI_7__14_GICR_PPISR,GIC-500 Private Peripheral Interrupt Status Register" hexmask.long.word 0x0 16.--31. 1. "REDISTRIBUTOR_SGI_PPI_7__14_GICR_PPISR__16_16," tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_GIC500SS_GICSS_VBUSM_GASKET_CFG_GICSS_VBUSM_GASKET_CFG (COMPUTE_CLUSTER0_GIC500SS_GICSS_VBUSM_GASKET_CFG_GICSS_VBUSM_GASKET_CFG)" base ad:0x4D200C0400 rgroup.long 0x0++0xB line.long 0x0 "__GICSS_VBUSM_GASKET_CFG__GICSS_VBUSM_GASKET_CFG_REGS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "__GICSS_VBUSM_GASKET_CFG__GICSS_VBUSM_GASKET_CFG_REGS_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "__GICSS_VBUSM_GASKET_CFG__GICSS_VBUSM_GASKET_CFG_REGS_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "__GICSS_VBUSM_GASKET_CFG__GICSS_VBUSM_GASKET_CFG_REGS_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "__GICSS_VBUSM_GASKET_CFG__GICSS_VBUSM_GASKET_CFG_REGS_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "__GICSS_VBUSM_GASKET_CFG__GICSS_VBUSM_GASKET_CFG_REGS_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "__GICSS_VBUSM_GASKET_CFG__GICSS_VBUSM_GASKET_CFG_REGS_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "__GICSS_VBUSM_GASKET_CFG__GICSS_VBUSM_GASKET_CFG_REGS_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "__GICSS_VBUSM_GASKET_CFG__GICSS_VBUSM_GASKET_CFG_REGS_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "__GICSS_VBUSM_GASKET_CFG__GICSS_VBUSM_GASKET_CFG_REGS_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "__GICSS_VBUSM_GASKET_CFG__GICSS_VBUSM_GASKET_CFG_REGS_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "__GICSS_VBUSM_GASKET_CFG__GICSS_VBUSM_GASKET_CFG_REGS_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "__GICSS_VBUSM_GASKET_CFG__GICSS_VBUSM_GASKET_CFG_REGS_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "__GICSS_VBUSM_GASKET_CFG__GICSS_VBUSM_GASKET_CFG_REGS_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" newline bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "__GICSS_VBUSM_GASKET_CFG__GICSS_VBUSM_GASKET_CFG_REGS_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "__GICSS_VBUSM_GASKET_CFG__GICSS_VBUSM_GASKET_CFG_REGS_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "__GICSS_VBUSM_GASKET_CFG__GICSS_VBUSM_GASKET_CFG_REGS_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "__GICSS_VBUSM_GASKET_CFG__GICSS_VBUSM_GASKET_CFG_REGS_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif tree.end tree "COMPUTE_CLUSTER0_MSMC" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_ECC_AGGR0 (COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_ECC_AGGR0)" base ad:0x4D20000000 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x13 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "CPU5_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu5_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 30. "CPU5_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu5_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 29. "CPU4_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu4_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 28. "CPU4_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu4_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 27. "CPU0_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 26. "CPU0_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 25. "EMIF0_MST_PIPE_BUSECC_PEND,Interrupt Pending Status for emif0_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 24. "EMIF0_SLV_PIPE_BUSECC_PEND,Interrupt Pending Status for emif0_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 23. "DRU1_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru1_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 22. "DRU0_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 21. "DRU1_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru1_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 20. "DRU0_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 19. "POSTARB_PIPE_CFG_BUSECC_PEND,Interrupt Pending Status for postarb_pipe_cfg_busecc_pend" "0,1" newline bitfld.long 0x4 18. "MSMC_MMR_BUSECC_PEND,Interrupt Pending Status for msmc_mmr_busecc_pend" "0,1" newline bitfld.long 0x4 17. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_dru0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 16. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 15. "DRU0_RD_BUF_EDC_PEND,Interrupt Pending Status for dru0_rd_buf_edc_pend" "0,1" newline bitfld.long 0x4 14. "DRU0_QUEUE_EDC_PEND,Interrupt Pending Status for dru0_queue_edc_pend" "0,1" newline bitfld.long 0x4 13. "DRU0_ENG_EDC_PEND,Interrupt Pending Status for dru0_eng_edc_pend" "0,1" newline bitfld.long 0x4 12. "DRU0_1_EDC_PEND,Interrupt Pending Status for dru0_1_edc_pend" "0,1" newline bitfld.long 0x4 11. "DRU0_0_EDC_PEND,Interrupt Pending Status for dru0_0_edc_pend" "0,1" newline bitfld.long 0x4 10. "DRU0_PSI_EDC_PEND,Interrupt Pending Status for dru0_psi_edc_pend" "0,1" newline bitfld.long 0x4 9. "DRU0_MMR_FW_EDC_CTL_PEND,Interrupt Pending Status for dru0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0x4 8. "DRU0_CBASS_SCR_EDC_PEND,Interrupt Pending Status for dru0_cbass_scr_edc_pend" "0,1" newline bitfld.long 0x4 7. "DRU0_CBASS_MMR_FW_CH_EDC_PEND,Interrupt Pending Status for dru0_cbass_mmr_fw_ch_edc_pend" "0,1" newline bitfld.long 0x4 6. "DRU0_CBASS_MMR_FW_CH_BR_EDC_PEND,Interrupt Pending Status for dru0_cbass_mmr_fw_ch_br_edc_pend" "0,1" newline bitfld.long 0x4 5. "DRU0_CBASS_MMR_EDC_PEND,Interrupt Pending Status for dru0_cbass_mmr_edc_pend" "0,1" newline bitfld.long 0x4 4. "DRU0_CBASS_MMR_CFG_EDC_PEND,Interrupt Pending Status for dru0_cbass_mmr_cfg_edc_pend" "0,1" newline bitfld.long 0x4 3. "DRU0_CBASS_MMR_BRDG_EDC_PEND,Interrupt Pending Status for dru0_cbass_mmr_brdg_edc_pend" "0,1" newline bitfld.long 0x4 2. "DRU0_CBASS_EDC_CTRL_PEND,Interrupt Pending Status for dru0_cbass_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 1. "DRU0_CBASS_DMSC_SLV_BRDG_EDC_PEND,Interrupt Pending Status for dru0_cbass_dmsc_slv_brdg_edc_pend" "0,1" newline bitfld.long 0x4 0. "DRU0_CBASS_DMSC_SCR_EDC_PEND,Interrupt Pending Status for dru0_cbass_dmsc_scr_edc_pend" "0,1" line.long 0x8 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 31. "SRAM2_BUSECC_PEND,Interrupt Pending Status for sram2_busecc_pend" "0,1" newline bitfld.long 0x8 30. "RMW2_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw2_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 29. "RMW2_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw2_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x8 28. "RMW2_QUEUE_BUSECC_2_PEND,Interrupt Pending Status for rmw2_queue_busecc_2_pend" "0,1" newline bitfld.long 0x8 27. "RMW2_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw2_queue_busecc_1_pend" "0,1" newline bitfld.long 0x8 26. "RMW2_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw2_queue_busecc_0_pend" "0,1" newline bitfld.long 0x8 25. "RMW2_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw2_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 24. "RMW2_BUSECC_PEND,Interrupt Pending Status for rmw2_busecc_pend" "0,1" newline bitfld.long 0x8 23. "DATARAM_BANK1_BUSECC_PEND,Interrupt Pending Status for dataram_bank1_busecc_pend" "0,1" newline bitfld.long 0x8 22. "SRAM1_BUSECC_PEND,Interrupt Pending Status for sram1_busecc_pend" "0,1" newline bitfld.long 0x8 21. "RMW1_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw1_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 20. "RMW1_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw1_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x8 19. "RMW1_QUEUE_BUSECC_2_PEND,Interrupt Pending Status for rmw1_queue_busecc_2_pend" "0,1" newline bitfld.long 0x8 18. "RMW1_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw1_queue_busecc_1_pend" "0,1" newline bitfld.long 0x8 17. "RMW1_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw1_queue_busecc_0_pend" "0,1" newline bitfld.long 0x8 16. "RMW1_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw1_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 15. "RMW1_BUSECC_PEND,Interrupt Pending Status for rmw1_busecc_pend" "0,1" newline bitfld.long 0x8 14. "DATARAM_BANK0_BUSECC_PEND,Interrupt Pending Status for dataram_bank0_busecc_pend" "0,1" newline bitfld.long 0x8 13. "SRAM0_BUSECC_PEND,Interrupt Pending Status for sram0_busecc_pend" "0,1" newline bitfld.long 0x8 12. "RMW0_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw0_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 11. "RMW0_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw0_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x8 10. "RMW0_QUEUE_BUSECC_2_PEND,Interrupt Pending Status for rmw0_queue_busecc_2_pend" "0,1" newline bitfld.long 0x8 9. "RMW0_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw0_queue_busecc_1_pend" "0,1" newline bitfld.long 0x8 8. "RMW0_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw0_queue_busecc_0_pend" "0,1" newline bitfld.long 0x8 7. "RMW0_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw0_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 6. "RMW0_BUSECC_PEND,Interrupt Pending Status for rmw0_busecc_pend" "0,1" newline bitfld.long 0x8 5. "EN_MSMC_P0_BUSECC_0_PEND,Interrupt Pending Status for en_msmc_p0_busecc_0_pend" "0,1" newline bitfld.long 0x8 4. "EN_MSMC_P0_BUSECC_DATA_PEND,Interrupt Pending Status for en_msmc_p0_busecc_data_pend" "0,1" newline bitfld.long 0x8 3. "CPU9_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu9_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x8 2. "CPU9_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu9_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x8 1. "CPU8_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu8_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x8 0. "CPU8_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu8_slv_local_arb_busecc_pend" "0,1" line.long 0xC "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_status_reg2,Interrupt Status Register 2" bitfld.long 0xC 31. "EN_MSMC_P0_BUSECC_1_PEND,Interrupt Pending Status for en_msmc_p0_busecc_1_pend" "0,1" newline bitfld.long 0xC 30. "EN_MSMC_P0_BUSECC_WRITE_RESP_PEND,Interrupt Pending Status for en_msmc_p0_busecc_write_resp_pend" "0,1" newline bitfld.long 0xC 29. "EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE_PEND,Interrupt Pending Status for en_msmc_p0_busecc_wr_barrier_queue_pend" "0,1" newline bitfld.long 0xC 28. "EN_MSMC_P0_BUSECC_WACK_CID_QUEUE_PEND,Interrupt Pending Status for en_msmc_p0_busecc_wack_cid_queue_pend" "0,1" newline bitfld.long 0xC 27. "EN_MSMC_P0_BUSECC_SNP_RESP_BUF_PEND,Interrupt Pending Status for en_msmc_p0_busecc_snp_resp_buf_pend" "0,1" newline bitfld.long 0xC 26. "EN_MSMC_P0_BUSECC_SNP_DATA_BUF_PEND,Interrupt Pending Status for en_msmc_p0_busecc_snp_data_buf_pend" "0,1" newline bitfld.long 0xC 25. "EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE_PEND,Interrupt Pending Status for en_msmc_p0_busecc_snoop_cmd_id_queue_pend" "0,1" newline bitfld.long 0xC 24. "EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE_PEND,Interrupt Pending Status for en_msmc_p0_busecc_rd_barrier_queue_pend" "0,1" newline bitfld.long 0xC 23. "EN_MSMC_P0_BUSECC_RACK_CID_QUEUE_PEND,Interrupt Pending Status for en_msmc_p0_busecc_rack_cid_queue_pend" "0,1" newline bitfld.long 0xC 22. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0xC 21. "EN_MSMC_P0_MMR_FW_EDC_CTL_PEND,Interrupt Pending Status for en_msmc_p0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0xC 20. "CLEC_J7AE_CLEC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for clec_j7ae_clec_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 19. "EMIF_1_VSAFE_SI_PEND,Interrupt Pending Status for emif_1_vsafe_si_pend" "0,1" newline bitfld.long 0xC 18. "EMIF_0_VSAFE_SI_PEND,Interrupt Pending Status for emif_0_vsafe_si_pend" "0,1" newline bitfld.long 0xC 17. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac5_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0xC 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 15. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac4_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0xC 14. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 13. "EMIF1_MST_PIPE_BUSECC_PEND,Interrupt Pending Status for emif1_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0xC 12. "EMIF1_SLV_PIPE_BUSECC_PEND,Interrupt Pending Status for emif1_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0xC 11. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 10. "CLEC_SRAM_RAMECC_PEND,Interrupt Pending Status for clec_sram_ramecc_pend" "0,1" newline bitfld.long 0xC 9. "DATARAM_BANK3_BUSECC_PEND,Interrupt Pending Status for dataram_bank3_busecc_pend" "0,1" newline bitfld.long 0xC 8. "SRAM3_BUSECC_PEND,Interrupt Pending Status for sram3_busecc_pend" "0,1" newline bitfld.long 0xC 7. "RMW3_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw3_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0xC 6. "RMW3_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw3_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0xC 5. "RMW3_QUEUE_BUSECC_2_PEND,Interrupt Pending Status for rmw3_queue_busecc_2_pend" "0,1" newline bitfld.long 0xC 4. "RMW3_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw3_queue_busecc_1_pend" "0,1" newline bitfld.long 0xC 3. "RMW3_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw3_queue_busecc_0_pend" "0,1" newline bitfld.long 0xC 2. "RMW3_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw3_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0xC 1. "RMW3_BUSECC_PEND,Interrupt Pending Status for rmw3_busecc_pend" "0,1" newline bitfld.long 0xC 0. "DATARAM_BANK2_BUSECC_PEND,Interrupt Pending Status for dataram_bank2_busecc_pend" "0,1" line.long 0x10 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_status_reg3,Interrupt Status Register 3" bitfld.long 0x10 1. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x10 0. "EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_PEND,Interrupt Pending Status for en_msmc_p0_busecc_msmc_cmd_buffer_pend" "0,1" rgroup.long 0x80++0xF line.long 0x0 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "CPU5_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu5_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 30. "CPU5_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu5_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU4_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu4_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 28. "CPU4_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu4_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 26. "CPU0_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 25. "EMIF0_MST_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for emif0_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0x0 24. "EMIF0_SLV_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for emif0_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0x0 23. "DRU1_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru1_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 22. "DRU0_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 21. "DRU1_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru1_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 20. "DRU0_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 19. "POSTARB_PIPE_CFG_BUSECC_ENABLE_SET,Interrupt Enable Set Register for postarb_pipe_cfg_busecc_pend" "0,1" newline bitfld.long 0x0 18. "MSMC_MMR_BUSECC_ENABLE_SET,Interrupt Enable Set Register for msmc_mmr_busecc_pend" "0,1" newline bitfld.long 0x0 17. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_dru0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 16. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 15. "DRU0_RD_BUF_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_rd_buf_edc_pend" "0,1" newline bitfld.long 0x0 14. "DRU0_QUEUE_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_queue_edc_pend" "0,1" newline bitfld.long 0x0 13. "DRU0_ENG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_eng_edc_pend" "0,1" newline bitfld.long 0x0 12. "DRU0_1_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_1_edc_pend" "0,1" newline bitfld.long 0x0 11. "DRU0_0_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_0_edc_pend" "0,1" newline bitfld.long 0x0 10. "DRU0_PSI_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_psi_edc_pend" "0,1" newline bitfld.long 0x0 9. "DRU0_MMR_FW_EDC_CTL_ENABLE_SET,Interrupt Enable Set Register for dru0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0x0 8. "DRU0_CBASS_SCR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_scr_edc_pend" "0,1" newline bitfld.long 0x0 7. "DRU0_CBASS_MMR_FW_CH_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_mmr_fw_ch_edc_pend" "0,1" newline bitfld.long 0x0 6. "DRU0_CBASS_MMR_FW_CH_BR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_mmr_fw_ch_br_edc_pend" "0,1" newline bitfld.long 0x0 5. "DRU0_CBASS_MMR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_mmr_edc_pend" "0,1" newline bitfld.long 0x0 4. "DRU0_CBASS_MMR_CFG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_mmr_cfg_edc_pend" "0,1" newline bitfld.long 0x0 3. "DRU0_CBASS_MMR_BRDG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_mmr_brdg_edc_pend" "0,1" newline bitfld.long 0x0 2. "DRU0_CBASS_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 1. "DRU0_CBASS_DMSC_SLV_BRDG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_dmsc_slv_brdg_edc_pend" "0,1" newline bitfld.long 0x0 0. "DRU0_CBASS_DMSC_SCR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_dmsc_scr_edc_pend" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 31. "SRAM2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram2_busecc_pend" "0,1" newline bitfld.long 0x4 30. "RMW2_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 29. "RMW2_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 28. "RMW2_QUEUE_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for rmw2_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 27. "RMW2_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw2_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 26. "RMW2_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw2_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 25. "RMW2_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 24. "RMW2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_busecc_pend" "0,1" newline bitfld.long 0x4 23. "DATARAM_BANK1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank1_busecc_pend" "0,1" newline bitfld.long 0x4 22. "SRAM1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram1_busecc_pend" "0,1" newline bitfld.long 0x4 21. "RMW1_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 20. "RMW1_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 19. "RMW1_QUEUE_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for rmw1_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 18. "RMW1_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw1_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 17. "RMW1_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw1_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 16. "RMW1_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 15. "RMW1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_busecc_pend" "0,1" newline bitfld.long 0x4 14. "DATARAM_BANK0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank0_busecc_pend" "0,1" newline bitfld.long 0x4 13. "SRAM0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram0_busecc_pend" "0,1" newline bitfld.long 0x4 12. "RMW0_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 11. "RMW0_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 10. "RMW0_QUEUE_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for rmw0_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 9. "RMW0_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw0_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 8. "RMW0_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw0_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 7. "RMW0_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 6. "RMW0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_busecc_pend" "0,1" newline bitfld.long 0x4 5. "EN_MSMC_P0_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_0_pend" "0,1" newline bitfld.long 0x4 4. "EN_MSMC_P0_BUSECC_DATA_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_data_pend" "0,1" newline bitfld.long 0x4 3. "CPU9_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu9_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 2. "CPU9_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu9_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 1. "CPU8_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu8_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 0. "CPU8_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu8_slv_local_arb_busecc_pend" "0,1" line.long 0x8 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_enable_set_reg2,Interrupt Enable Set Register 2" bitfld.long 0x8 31. "EN_MSMC_P0_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_1_pend" "0,1" newline bitfld.long 0x8 30. "EN_MSMC_P0_BUSECC_WRITE_RESP_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_write_resp_pend" "0,1" newline bitfld.long 0x8 29. "EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_wr_barrier_queue_pend" "0,1" newline bitfld.long 0x8 28. "EN_MSMC_P0_BUSECC_WACK_CID_QUEUE_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_wack_cid_queue_pend" "0,1" newline bitfld.long 0x8 27. "EN_MSMC_P0_BUSECC_SNP_RESP_BUF_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_snp_resp_buf_pend" "0,1" newline bitfld.long 0x8 26. "EN_MSMC_P0_BUSECC_SNP_DATA_BUF_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_snp_data_buf_pend" "0,1" newline bitfld.long 0x8 25. "EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_snoop_cmd_id_queue_pend" "0,1" newline bitfld.long 0x8 24. "EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_rd_barrier_queue_pend" "0,1" newline bitfld.long 0x8 23. "EN_MSMC_P0_BUSECC_RACK_CID_QUEUE_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_rack_cid_queue_pend" "0,1" newline bitfld.long 0x8 22. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 21. "EN_MSMC_P0_MMR_FW_EDC_CTL_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0x8 20. "CLEC_J7AE_CLEC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for clec_j7ae_clec_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "EMIF_1_VSAFE_SI_ENABLE_SET,Interrupt Enable Set Register for emif_1_vsafe_si_pend" "0,1" newline bitfld.long 0x8 18. "EMIF_0_VSAFE_SI_ENABLE_SET,Interrupt Enable Set Register for emif_0_vsafe_si_pend" "0,1" newline bitfld.long 0x8 17. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac5_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 15. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac4_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 14. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 13. "EMIF1_MST_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for emif1_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 12. "EMIF1_SLV_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for emif1_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 11. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 10. "CLEC_SRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clec_sram_ramecc_pend" "0,1" newline bitfld.long 0x8 9. "DATARAM_BANK3_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank3_busecc_pend" "0,1" newline bitfld.long 0x8 8. "SRAM3_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram3_busecc_pend" "0,1" newline bitfld.long 0x8 7. "RMW3_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 6. "RMW3_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x8 5. "RMW3_QUEUE_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for rmw3_queue_busecc_2_pend" "0,1" newline bitfld.long 0x8 4. "RMW3_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw3_queue_busecc_1_pend" "0,1" newline bitfld.long 0x8 3. "RMW3_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw3_queue_busecc_0_pend" "0,1" newline bitfld.long 0x8 2. "RMW3_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 1. "RMW3_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_busecc_pend" "0,1" newline bitfld.long 0x8 0. "DATARAM_BANK2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank2_busecc_pend" "0,1" line.long 0xC "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_enable_set_reg3,Interrupt Enable Set Register 3" bitfld.long 0xC 1. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0xC 0. "EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_msmc_cmd_buffer_pend" "0,1" rgroup.long 0xC0++0xF line.long 0x0 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "CPU5_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu5_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 30. "CPU5_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu5_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU4_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu4_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 28. "CPU4_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu4_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 26. "CPU0_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 25. "EMIF0_MST_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for emif0_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0x0 24. "EMIF0_SLV_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for emif0_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0x0 23. "DRU1_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru1_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 22. "DRU0_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 21. "DRU1_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru1_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 20. "DRU0_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 19. "POSTARB_PIPE_CFG_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for postarb_pipe_cfg_busecc_pend" "0,1" newline bitfld.long 0x0 18. "MSMC_MMR_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for msmc_mmr_busecc_pend" "0,1" newline bitfld.long 0x0 17. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_dru0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 16. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 15. "DRU0_RD_BUF_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_rd_buf_edc_pend" "0,1" newline bitfld.long 0x0 14. "DRU0_QUEUE_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_queue_edc_pend" "0,1" newline bitfld.long 0x0 13. "DRU0_ENG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_eng_edc_pend" "0,1" newline bitfld.long 0x0 12. "DRU0_1_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_1_edc_pend" "0,1" newline bitfld.long 0x0 11. "DRU0_0_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_0_edc_pend" "0,1" newline bitfld.long 0x0 10. "DRU0_PSI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_psi_edc_pend" "0,1" newline bitfld.long 0x0 9. "DRU0_MMR_FW_EDC_CTL_ENABLE_CLR,Interrupt Enable Clear Register for dru0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0x0 8. "DRU0_CBASS_SCR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_scr_edc_pend" "0,1" newline bitfld.long 0x0 7. "DRU0_CBASS_MMR_FW_CH_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_mmr_fw_ch_edc_pend" "0,1" newline bitfld.long 0x0 6. "DRU0_CBASS_MMR_FW_CH_BR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_mmr_fw_ch_br_edc_pend" "0,1" newline bitfld.long 0x0 5. "DRU0_CBASS_MMR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_mmr_edc_pend" "0,1" newline bitfld.long 0x0 4. "DRU0_CBASS_MMR_CFG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_mmr_cfg_edc_pend" "0,1" newline bitfld.long 0x0 3. "DRU0_CBASS_MMR_BRDG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_mmr_brdg_edc_pend" "0,1" newline bitfld.long 0x0 2. "DRU0_CBASS_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 1. "DRU0_CBASS_DMSC_SLV_BRDG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_dmsc_slv_brdg_edc_pend" "0,1" newline bitfld.long 0x0 0. "DRU0_CBASS_DMSC_SCR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_dmsc_scr_edc_pend" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 31. "SRAM2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram2_busecc_pend" "0,1" newline bitfld.long 0x4 30. "RMW2_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 29. "RMW2_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 28. "RMW2_QUEUE_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 27. "RMW2_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 26. "RMW2_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 25. "RMW2_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 24. "RMW2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_busecc_pend" "0,1" newline bitfld.long 0x4 23. "DATARAM_BANK1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank1_busecc_pend" "0,1" newline bitfld.long 0x4 22. "SRAM1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram1_busecc_pend" "0,1" newline bitfld.long 0x4 21. "RMW1_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 20. "RMW1_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 19. "RMW1_QUEUE_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 18. "RMW1_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 17. "RMW1_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 16. "RMW1_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 15. "RMW1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_busecc_pend" "0,1" newline bitfld.long 0x4 14. "DATARAM_BANK0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank0_busecc_pend" "0,1" newline bitfld.long 0x4 13. "SRAM0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram0_busecc_pend" "0,1" newline bitfld.long 0x4 12. "RMW0_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 11. "RMW0_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 10. "RMW0_QUEUE_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 9. "RMW0_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 8. "RMW0_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 7. "RMW0_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 6. "RMW0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_busecc_pend" "0,1" newline bitfld.long 0x4 5. "EN_MSMC_P0_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_0_pend" "0,1" newline bitfld.long 0x4 4. "EN_MSMC_P0_BUSECC_DATA_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_data_pend" "0,1" newline bitfld.long 0x4 3. "CPU9_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu9_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 2. "CPU9_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu9_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 1. "CPU8_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu8_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 0. "CPU8_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu8_slv_local_arb_busecc_pend" "0,1" line.long 0x8 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_enable_clr_reg2,Interrupt Enable Clear Register 2" bitfld.long 0x8 31. "EN_MSMC_P0_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_1_pend" "0,1" newline bitfld.long 0x8 30. "EN_MSMC_P0_BUSECC_WRITE_RESP_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_write_resp_pend" "0,1" newline bitfld.long 0x8 29. "EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_wr_barrier_queue_pend" "0,1" newline bitfld.long 0x8 28. "EN_MSMC_P0_BUSECC_WACK_CID_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_wack_cid_queue_pend" "0,1" newline bitfld.long 0x8 27. "EN_MSMC_P0_BUSECC_SNP_RESP_BUF_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_snp_resp_buf_pend" "0,1" newline bitfld.long 0x8 26. "EN_MSMC_P0_BUSECC_SNP_DATA_BUF_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_snp_data_buf_pend" "0,1" newline bitfld.long 0x8 25. "EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_snoop_cmd_id_queue_pend" "0,1" newline bitfld.long 0x8 24. "EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_rd_barrier_queue_pend" "0,1" newline bitfld.long 0x8 23. "EN_MSMC_P0_BUSECC_RACK_CID_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_rack_cid_queue_pend" "0,1" newline bitfld.long 0x8 22. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 21. "EN_MSMC_P0_MMR_FW_EDC_CTL_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0x8 20. "CLEC_J7AE_CLEC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for clec_j7ae_clec_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "EMIF_1_VSAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for emif_1_vsafe_si_pend" "0,1" newline bitfld.long 0x8 18. "EMIF_0_VSAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for emif_0_vsafe_si_pend" "0,1" newline bitfld.long 0x8 17. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac5_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 15. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac4_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 14. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 13. "EMIF1_MST_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for emif1_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 12. "EMIF1_SLV_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for emif1_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 11. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 10. "CLEC_SRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clec_sram_ramecc_pend" "0,1" newline bitfld.long 0x8 9. "DATARAM_BANK3_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank3_busecc_pend" "0,1" newline bitfld.long 0x8 8. "SRAM3_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram3_busecc_pend" "0,1" newline bitfld.long 0x8 7. "RMW3_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 6. "RMW3_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x8 5. "RMW3_QUEUE_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_queue_busecc_2_pend" "0,1" newline bitfld.long 0x8 4. "RMW3_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_queue_busecc_1_pend" "0,1" newline bitfld.long 0x8 3. "RMW3_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_queue_busecc_0_pend" "0,1" newline bitfld.long 0x8 2. "RMW3_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 1. "RMW3_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_busecc_pend" "0,1" newline bitfld.long 0x8 0. "DATARAM_BANK2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank2_busecc_pend" "0,1" line.long 0xC "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_sec_enable_clr_reg3,Interrupt Enable Clear Register 3" bitfld.long 0xC 1. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0xC 0. "EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_msmc_cmd_buffer_pend" "0,1" rgroup.long 0x13C++0x13 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "CPU5_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu5_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 30. "CPU5_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu5_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 29. "CPU4_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu4_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 28. "CPU4_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu4_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 27. "CPU0_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 26. "CPU0_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 25. "EMIF0_MST_PIPE_BUSECC_PEND,Interrupt Pending Status for emif0_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 24. "EMIF0_SLV_PIPE_BUSECC_PEND,Interrupt Pending Status for emif0_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 23. "DRU1_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru1_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 22. "DRU0_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 21. "DRU1_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru1_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 20. "DRU0_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 19. "POSTARB_PIPE_CFG_BUSECC_PEND,Interrupt Pending Status for postarb_pipe_cfg_busecc_pend" "0,1" newline bitfld.long 0x4 18. "MSMC_MMR_BUSECC_PEND,Interrupt Pending Status for msmc_mmr_busecc_pend" "0,1" newline bitfld.long 0x4 17. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_dru0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 16. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 15. "DRU0_RD_BUF_EDC_PEND,Interrupt Pending Status for dru0_rd_buf_edc_pend" "0,1" newline bitfld.long 0x4 14. "DRU0_QUEUE_EDC_PEND,Interrupt Pending Status for dru0_queue_edc_pend" "0,1" newline bitfld.long 0x4 13. "DRU0_ENG_EDC_PEND,Interrupt Pending Status for dru0_eng_edc_pend" "0,1" newline bitfld.long 0x4 12. "DRU0_1_EDC_PEND,Interrupt Pending Status for dru0_1_edc_pend" "0,1" newline bitfld.long 0x4 11. "DRU0_0_EDC_PEND,Interrupt Pending Status for dru0_0_edc_pend" "0,1" newline bitfld.long 0x4 10. "DRU0_PSI_EDC_PEND,Interrupt Pending Status for dru0_psi_edc_pend" "0,1" newline bitfld.long 0x4 9. "DRU0_MMR_FW_EDC_CTL_PEND,Interrupt Pending Status for dru0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0x4 8. "DRU0_CBASS_SCR_EDC_PEND,Interrupt Pending Status for dru0_cbass_scr_edc_pend" "0,1" newline bitfld.long 0x4 7. "DRU0_CBASS_MMR_FW_CH_EDC_PEND,Interrupt Pending Status for dru0_cbass_mmr_fw_ch_edc_pend" "0,1" newline bitfld.long 0x4 6. "DRU0_CBASS_MMR_FW_CH_BR_EDC_PEND,Interrupt Pending Status for dru0_cbass_mmr_fw_ch_br_edc_pend" "0,1" newline bitfld.long 0x4 5. "DRU0_CBASS_MMR_EDC_PEND,Interrupt Pending Status for dru0_cbass_mmr_edc_pend" "0,1" newline bitfld.long 0x4 4. "DRU0_CBASS_MMR_CFG_EDC_PEND,Interrupt Pending Status for dru0_cbass_mmr_cfg_edc_pend" "0,1" newline bitfld.long 0x4 3. "DRU0_CBASS_MMR_BRDG_EDC_PEND,Interrupt Pending Status for dru0_cbass_mmr_brdg_edc_pend" "0,1" newline bitfld.long 0x4 2. "DRU0_CBASS_EDC_CTRL_PEND,Interrupt Pending Status for dru0_cbass_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 1. "DRU0_CBASS_DMSC_SLV_BRDG_EDC_PEND,Interrupt Pending Status for dru0_cbass_dmsc_slv_brdg_edc_pend" "0,1" newline bitfld.long 0x4 0. "DRU0_CBASS_DMSC_SCR_EDC_PEND,Interrupt Pending Status for dru0_cbass_dmsc_scr_edc_pend" "0,1" line.long 0x8 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 31. "SRAM2_BUSECC_PEND,Interrupt Pending Status for sram2_busecc_pend" "0,1" newline bitfld.long 0x8 30. "RMW2_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw2_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 29. "RMW2_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw2_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x8 28. "RMW2_QUEUE_BUSECC_2_PEND,Interrupt Pending Status for rmw2_queue_busecc_2_pend" "0,1" newline bitfld.long 0x8 27. "RMW2_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw2_queue_busecc_1_pend" "0,1" newline bitfld.long 0x8 26. "RMW2_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw2_queue_busecc_0_pend" "0,1" newline bitfld.long 0x8 25. "RMW2_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw2_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 24. "RMW2_BUSECC_PEND,Interrupt Pending Status for rmw2_busecc_pend" "0,1" newline bitfld.long 0x8 23. "DATARAM_BANK1_BUSECC_PEND,Interrupt Pending Status for dataram_bank1_busecc_pend" "0,1" newline bitfld.long 0x8 22. "SRAM1_BUSECC_PEND,Interrupt Pending Status for sram1_busecc_pend" "0,1" newline bitfld.long 0x8 21. "RMW1_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw1_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 20. "RMW1_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw1_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x8 19. "RMW1_QUEUE_BUSECC_2_PEND,Interrupt Pending Status for rmw1_queue_busecc_2_pend" "0,1" newline bitfld.long 0x8 18. "RMW1_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw1_queue_busecc_1_pend" "0,1" newline bitfld.long 0x8 17. "RMW1_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw1_queue_busecc_0_pend" "0,1" newline bitfld.long 0x8 16. "RMW1_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw1_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 15. "RMW1_BUSECC_PEND,Interrupt Pending Status for rmw1_busecc_pend" "0,1" newline bitfld.long 0x8 14. "DATARAM_BANK0_BUSECC_PEND,Interrupt Pending Status for dataram_bank0_busecc_pend" "0,1" newline bitfld.long 0x8 13. "SRAM0_BUSECC_PEND,Interrupt Pending Status for sram0_busecc_pend" "0,1" newline bitfld.long 0x8 12. "RMW0_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw0_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 11. "RMW0_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw0_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x8 10. "RMW0_QUEUE_BUSECC_2_PEND,Interrupt Pending Status for rmw0_queue_busecc_2_pend" "0,1" newline bitfld.long 0x8 9. "RMW0_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw0_queue_busecc_1_pend" "0,1" newline bitfld.long 0x8 8. "RMW0_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw0_queue_busecc_0_pend" "0,1" newline bitfld.long 0x8 7. "RMW0_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw0_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 6. "RMW0_BUSECC_PEND,Interrupt Pending Status for rmw0_busecc_pend" "0,1" newline bitfld.long 0x8 5. "EN_MSMC_P0_BUSECC_0_PEND,Interrupt Pending Status for en_msmc_p0_busecc_0_pend" "0,1" newline bitfld.long 0x8 4. "EN_MSMC_P0_BUSECC_DATA_PEND,Interrupt Pending Status for en_msmc_p0_busecc_data_pend" "0,1" newline bitfld.long 0x8 3. "CPU9_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu9_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x8 2. "CPU9_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu9_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x8 1. "CPU8_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu8_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x8 0. "CPU8_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu8_slv_local_arb_busecc_pend" "0,1" line.long 0xC "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_status_reg2,Interrupt Status Register 2" bitfld.long 0xC 31. "EN_MSMC_P0_BUSECC_1_PEND,Interrupt Pending Status for en_msmc_p0_busecc_1_pend" "0,1" newline bitfld.long 0xC 30. "EN_MSMC_P0_BUSECC_WRITE_RESP_PEND,Interrupt Pending Status for en_msmc_p0_busecc_write_resp_pend" "0,1" newline bitfld.long 0xC 29. "EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE_PEND,Interrupt Pending Status for en_msmc_p0_busecc_wr_barrier_queue_pend" "0,1" newline bitfld.long 0xC 28. "EN_MSMC_P0_BUSECC_WACK_CID_QUEUE_PEND,Interrupt Pending Status for en_msmc_p0_busecc_wack_cid_queue_pend" "0,1" newline bitfld.long 0xC 27. "EN_MSMC_P0_BUSECC_SNP_RESP_BUF_PEND,Interrupt Pending Status for en_msmc_p0_busecc_snp_resp_buf_pend" "0,1" newline bitfld.long 0xC 26. "EN_MSMC_P0_BUSECC_SNP_DATA_BUF_PEND,Interrupt Pending Status for en_msmc_p0_busecc_snp_data_buf_pend" "0,1" newline bitfld.long 0xC 25. "EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE_PEND,Interrupt Pending Status for en_msmc_p0_busecc_snoop_cmd_id_queue_pend" "0,1" newline bitfld.long 0xC 24. "EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE_PEND,Interrupt Pending Status for en_msmc_p0_busecc_rd_barrier_queue_pend" "0,1" newline bitfld.long 0xC 23. "EN_MSMC_P0_BUSECC_RACK_CID_QUEUE_PEND,Interrupt Pending Status for en_msmc_p0_busecc_rack_cid_queue_pend" "0,1" newline bitfld.long 0xC 22. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0xC 21. "EN_MSMC_P0_MMR_FW_EDC_CTL_PEND,Interrupt Pending Status for en_msmc_p0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0xC 20. "CLEC_J7AE_CLEC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for clec_j7ae_clec_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 19. "EMIF_1_VSAFE_SI_PEND,Interrupt Pending Status for emif_1_vsafe_si_pend" "0,1" newline bitfld.long 0xC 18. "EMIF_0_VSAFE_SI_PEND,Interrupt Pending Status for emif_0_vsafe_si_pend" "0,1" newline bitfld.long 0xC 17. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac5_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0xC 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 15. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac4_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0xC 14. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 13. "EMIF1_MST_PIPE_BUSECC_PEND,Interrupt Pending Status for emif1_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0xC 12. "EMIF1_SLV_PIPE_BUSECC_PEND,Interrupt Pending Status for emif1_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0xC 11. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 10. "CLEC_SRAM_RAMECC_PEND,Interrupt Pending Status for clec_sram_ramecc_pend" "0,1" newline bitfld.long 0xC 9. "DATARAM_BANK3_BUSECC_PEND,Interrupt Pending Status for dataram_bank3_busecc_pend" "0,1" newline bitfld.long 0xC 8. "SRAM3_BUSECC_PEND,Interrupt Pending Status for sram3_busecc_pend" "0,1" newline bitfld.long 0xC 7. "RMW3_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw3_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0xC 6. "RMW3_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw3_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0xC 5. "RMW3_QUEUE_BUSECC_2_PEND,Interrupt Pending Status for rmw3_queue_busecc_2_pend" "0,1" newline bitfld.long 0xC 4. "RMW3_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw3_queue_busecc_1_pend" "0,1" newline bitfld.long 0xC 3. "RMW3_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw3_queue_busecc_0_pend" "0,1" newline bitfld.long 0xC 2. "RMW3_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw3_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0xC 1. "RMW3_BUSECC_PEND,Interrupt Pending Status for rmw3_busecc_pend" "0,1" newline bitfld.long 0xC 0. "DATARAM_BANK2_BUSECC_PEND,Interrupt Pending Status for dataram_bank2_busecc_pend" "0,1" line.long 0x10 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_status_reg3,Interrupt Status Register 3" bitfld.long 0x10 1. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x10 0. "EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_PEND,Interrupt Pending Status for en_msmc_p0_busecc_msmc_cmd_buffer_pend" "0,1" rgroup.long 0x180++0xF line.long 0x0 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "CPU5_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu5_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 30. "CPU5_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu5_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU4_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu4_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 28. "CPU4_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu4_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 26. "CPU0_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 25. "EMIF0_MST_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for emif0_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0x0 24. "EMIF0_SLV_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for emif0_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0x0 23. "DRU1_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru1_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 22. "DRU0_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 21. "DRU1_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru1_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 20. "DRU0_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 19. "POSTARB_PIPE_CFG_BUSECC_ENABLE_SET,Interrupt Enable Set Register for postarb_pipe_cfg_busecc_pend" "0,1" newline bitfld.long 0x0 18. "MSMC_MMR_BUSECC_ENABLE_SET,Interrupt Enable Set Register for msmc_mmr_busecc_pend" "0,1" newline bitfld.long 0x0 17. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_dru0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 16. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 15. "DRU0_RD_BUF_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_rd_buf_edc_pend" "0,1" newline bitfld.long 0x0 14. "DRU0_QUEUE_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_queue_edc_pend" "0,1" newline bitfld.long 0x0 13. "DRU0_ENG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_eng_edc_pend" "0,1" newline bitfld.long 0x0 12. "DRU0_1_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_1_edc_pend" "0,1" newline bitfld.long 0x0 11. "DRU0_0_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_0_edc_pend" "0,1" newline bitfld.long 0x0 10. "DRU0_PSI_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_psi_edc_pend" "0,1" newline bitfld.long 0x0 9. "DRU0_MMR_FW_EDC_CTL_ENABLE_SET,Interrupt Enable Set Register for dru0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0x0 8. "DRU0_CBASS_SCR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_scr_edc_pend" "0,1" newline bitfld.long 0x0 7. "DRU0_CBASS_MMR_FW_CH_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_mmr_fw_ch_edc_pend" "0,1" newline bitfld.long 0x0 6. "DRU0_CBASS_MMR_FW_CH_BR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_mmr_fw_ch_br_edc_pend" "0,1" newline bitfld.long 0x0 5. "DRU0_CBASS_MMR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_mmr_edc_pend" "0,1" newline bitfld.long 0x0 4. "DRU0_CBASS_MMR_CFG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_mmr_cfg_edc_pend" "0,1" newline bitfld.long 0x0 3. "DRU0_CBASS_MMR_BRDG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_mmr_brdg_edc_pend" "0,1" newline bitfld.long 0x0 2. "DRU0_CBASS_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 1. "DRU0_CBASS_DMSC_SLV_BRDG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_dmsc_slv_brdg_edc_pend" "0,1" newline bitfld.long 0x0 0. "DRU0_CBASS_DMSC_SCR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru0_cbass_dmsc_scr_edc_pend" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 31. "SRAM2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram2_busecc_pend" "0,1" newline bitfld.long 0x4 30. "RMW2_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 29. "RMW2_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 28. "RMW2_QUEUE_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for rmw2_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 27. "RMW2_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw2_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 26. "RMW2_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw2_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 25. "RMW2_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 24. "RMW2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_busecc_pend" "0,1" newline bitfld.long 0x4 23. "DATARAM_BANK1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank1_busecc_pend" "0,1" newline bitfld.long 0x4 22. "SRAM1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram1_busecc_pend" "0,1" newline bitfld.long 0x4 21. "RMW1_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 20. "RMW1_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 19. "RMW1_QUEUE_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for rmw1_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 18. "RMW1_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw1_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 17. "RMW1_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw1_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 16. "RMW1_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 15. "RMW1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_busecc_pend" "0,1" newline bitfld.long 0x4 14. "DATARAM_BANK0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank0_busecc_pend" "0,1" newline bitfld.long 0x4 13. "SRAM0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram0_busecc_pend" "0,1" newline bitfld.long 0x4 12. "RMW0_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 11. "RMW0_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 10. "RMW0_QUEUE_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for rmw0_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 9. "RMW0_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw0_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 8. "RMW0_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw0_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 7. "RMW0_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 6. "RMW0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_busecc_pend" "0,1" newline bitfld.long 0x4 5. "EN_MSMC_P0_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_0_pend" "0,1" newline bitfld.long 0x4 4. "EN_MSMC_P0_BUSECC_DATA_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_data_pend" "0,1" newline bitfld.long 0x4 3. "CPU9_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu9_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 2. "CPU9_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu9_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 1. "CPU8_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu8_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 0. "CPU8_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu8_slv_local_arb_busecc_pend" "0,1" line.long 0x8 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_enable_set_reg2,Interrupt Enable Set Register 2" bitfld.long 0x8 31. "EN_MSMC_P0_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_1_pend" "0,1" newline bitfld.long 0x8 30. "EN_MSMC_P0_BUSECC_WRITE_RESP_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_write_resp_pend" "0,1" newline bitfld.long 0x8 29. "EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_wr_barrier_queue_pend" "0,1" newline bitfld.long 0x8 28. "EN_MSMC_P0_BUSECC_WACK_CID_QUEUE_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_wack_cid_queue_pend" "0,1" newline bitfld.long 0x8 27. "EN_MSMC_P0_BUSECC_SNP_RESP_BUF_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_snp_resp_buf_pend" "0,1" newline bitfld.long 0x8 26. "EN_MSMC_P0_BUSECC_SNP_DATA_BUF_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_snp_data_buf_pend" "0,1" newline bitfld.long 0x8 25. "EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_snoop_cmd_id_queue_pend" "0,1" newline bitfld.long 0x8 24. "EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_rd_barrier_queue_pend" "0,1" newline bitfld.long 0x8 23. "EN_MSMC_P0_BUSECC_RACK_CID_QUEUE_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_rack_cid_queue_pend" "0,1" newline bitfld.long 0x8 22. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 21. "EN_MSMC_P0_MMR_FW_EDC_CTL_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0x8 20. "CLEC_J7AE_CLEC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for clec_j7ae_clec_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "EMIF_1_VSAFE_SI_ENABLE_SET,Interrupt Enable Set Register for emif_1_vsafe_si_pend" "0,1" newline bitfld.long 0x8 18. "EMIF_0_VSAFE_SI_ENABLE_SET,Interrupt Enable Set Register for emif_0_vsafe_si_pend" "0,1" newline bitfld.long 0x8 17. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac5_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 15. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac4_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 14. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 13. "EMIF1_MST_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for emif1_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 12. "EMIF1_SLV_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for emif1_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 11. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 10. "CLEC_SRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clec_sram_ramecc_pend" "0,1" newline bitfld.long 0x8 9. "DATARAM_BANK3_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank3_busecc_pend" "0,1" newline bitfld.long 0x8 8. "SRAM3_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram3_busecc_pend" "0,1" newline bitfld.long 0x8 7. "RMW3_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 6. "RMW3_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x8 5. "RMW3_QUEUE_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for rmw3_queue_busecc_2_pend" "0,1" newline bitfld.long 0x8 4. "RMW3_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw3_queue_busecc_1_pend" "0,1" newline bitfld.long 0x8 3. "RMW3_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw3_queue_busecc_0_pend" "0,1" newline bitfld.long 0x8 2. "RMW3_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 1. "RMW3_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_busecc_pend" "0,1" newline bitfld.long 0x8 0. "DATARAM_BANK2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank2_busecc_pend" "0,1" line.long 0xC "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_enable_set_reg3,Interrupt Enable Set Register 3" bitfld.long 0xC 1. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0xC 0. "EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_msmc_cmd_buffer_pend" "0,1" rgroup.long 0x1C0++0xF line.long 0x0 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "CPU5_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu5_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 30. "CPU5_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu5_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU4_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu4_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 28. "CPU4_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu4_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 26. "CPU0_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 25. "EMIF0_MST_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for emif0_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0x0 24. "EMIF0_SLV_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for emif0_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0x0 23. "DRU1_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru1_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 22. "DRU0_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 21. "DRU1_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru1_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 20. "DRU0_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x0 19. "POSTARB_PIPE_CFG_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for postarb_pipe_cfg_busecc_pend" "0,1" newline bitfld.long 0x0 18. "MSMC_MMR_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for msmc_mmr_busecc_pend" "0,1" newline bitfld.long 0x0 17. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_dru0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 16. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 15. "DRU0_RD_BUF_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_rd_buf_edc_pend" "0,1" newline bitfld.long 0x0 14. "DRU0_QUEUE_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_queue_edc_pend" "0,1" newline bitfld.long 0x0 13. "DRU0_ENG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_eng_edc_pend" "0,1" newline bitfld.long 0x0 12. "DRU0_1_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_1_edc_pend" "0,1" newline bitfld.long 0x0 11. "DRU0_0_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_0_edc_pend" "0,1" newline bitfld.long 0x0 10. "DRU0_PSI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_psi_edc_pend" "0,1" newline bitfld.long 0x0 9. "DRU0_MMR_FW_EDC_CTL_ENABLE_CLR,Interrupt Enable Clear Register for dru0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0x0 8. "DRU0_CBASS_SCR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_scr_edc_pend" "0,1" newline bitfld.long 0x0 7. "DRU0_CBASS_MMR_FW_CH_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_mmr_fw_ch_edc_pend" "0,1" newline bitfld.long 0x0 6. "DRU0_CBASS_MMR_FW_CH_BR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_mmr_fw_ch_br_edc_pend" "0,1" newline bitfld.long 0x0 5. "DRU0_CBASS_MMR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_mmr_edc_pend" "0,1" newline bitfld.long 0x0 4. "DRU0_CBASS_MMR_CFG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_mmr_cfg_edc_pend" "0,1" newline bitfld.long 0x0 3. "DRU0_CBASS_MMR_BRDG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_mmr_brdg_edc_pend" "0,1" newline bitfld.long 0x0 2. "DRU0_CBASS_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 1. "DRU0_CBASS_DMSC_SLV_BRDG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_dmsc_slv_brdg_edc_pend" "0,1" newline bitfld.long 0x0 0. "DRU0_CBASS_DMSC_SCR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_cbass_dmsc_scr_edc_pend" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 31. "SRAM2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram2_busecc_pend" "0,1" newline bitfld.long 0x4 30. "RMW2_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 29. "RMW2_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 28. "RMW2_QUEUE_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 27. "RMW2_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 26. "RMW2_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 25. "RMW2_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 24. "RMW2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_busecc_pend" "0,1" newline bitfld.long 0x4 23. "DATARAM_BANK1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank1_busecc_pend" "0,1" newline bitfld.long 0x4 22. "SRAM1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram1_busecc_pend" "0,1" newline bitfld.long 0x4 21. "RMW1_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 20. "RMW1_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 19. "RMW1_QUEUE_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 18. "RMW1_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 17. "RMW1_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 16. "RMW1_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 15. "RMW1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_busecc_pend" "0,1" newline bitfld.long 0x4 14. "DATARAM_BANK0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank0_busecc_pend" "0,1" newline bitfld.long 0x4 13. "SRAM0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram0_busecc_pend" "0,1" newline bitfld.long 0x4 12. "RMW0_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 11. "RMW0_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x4 10. "RMW0_QUEUE_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_queue_busecc_2_pend" "0,1" newline bitfld.long 0x4 9. "RMW0_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_queue_busecc_1_pend" "0,1" newline bitfld.long 0x4 8. "RMW0_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_queue_busecc_0_pend" "0,1" newline bitfld.long 0x4 7. "RMW0_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x4 6. "RMW0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_busecc_pend" "0,1" newline bitfld.long 0x4 5. "EN_MSMC_P0_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_0_pend" "0,1" newline bitfld.long 0x4 4. "EN_MSMC_P0_BUSECC_DATA_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_data_pend" "0,1" newline bitfld.long 0x4 3. "CPU9_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu9_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 2. "CPU9_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu9_slv_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 1. "CPU8_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu8_mst_local_arb_busecc_pend" "0,1" newline bitfld.long 0x4 0. "CPU8_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu8_slv_local_arb_busecc_pend" "0,1" line.long 0x8 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_enable_clr_reg2,Interrupt Enable Clear Register 2" bitfld.long 0x8 31. "EN_MSMC_P0_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_1_pend" "0,1" newline bitfld.long 0x8 30. "EN_MSMC_P0_BUSECC_WRITE_RESP_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_write_resp_pend" "0,1" newline bitfld.long 0x8 29. "EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_wr_barrier_queue_pend" "0,1" newline bitfld.long 0x8 28. "EN_MSMC_P0_BUSECC_WACK_CID_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_wack_cid_queue_pend" "0,1" newline bitfld.long 0x8 27. "EN_MSMC_P0_BUSECC_SNP_RESP_BUF_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_snp_resp_buf_pend" "0,1" newline bitfld.long 0x8 26. "EN_MSMC_P0_BUSECC_SNP_DATA_BUF_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_snp_data_buf_pend" "0,1" newline bitfld.long 0x8 25. "EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_snoop_cmd_id_queue_pend" "0,1" newline bitfld.long 0x8 24. "EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_rd_barrier_queue_pend" "0,1" newline bitfld.long 0x8 23. "EN_MSMC_P0_BUSECC_RACK_CID_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_rack_cid_queue_pend" "0,1" newline bitfld.long 0x8 22. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac0_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 21. "EN_MSMC_P0_MMR_FW_EDC_CTL_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_mmr_fw_edc_ctl_pend" "0,1" newline bitfld.long 0x8 20. "CLEC_J7AE_CLEC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for clec_j7ae_clec_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "EMIF_1_VSAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for emif_1_vsafe_si_pend" "0,1" newline bitfld.long 0x8 18. "EMIF_0_VSAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for emif_0_vsafe_si_pend" "0,1" newline bitfld.long 0x8 17. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac5_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 15. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac4_fw_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x8 14. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 13. "EMIF1_MST_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for emif1_mst_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 12. "EMIF1_SLV_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for emif1_slv_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 11. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 10. "CLEC_SRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clec_sram_ramecc_pend" "0,1" newline bitfld.long 0x8 9. "DATARAM_BANK3_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank3_busecc_pend" "0,1" newline bitfld.long 0x8 8. "SRAM3_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram3_busecc_pend" "0,1" newline bitfld.long 0x8 7. "RMW3_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_sram_sf_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 6. "RMW3_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_rmw_tag_update_busecc_pend" "0,1" newline bitfld.long 0x8 5. "RMW3_QUEUE_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_queue_busecc_2_pend" "0,1" newline bitfld.long 0x8 4. "RMW3_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_queue_busecc_1_pend" "0,1" newline bitfld.long 0x8 3. "RMW3_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_queue_busecc_0_pend" "0,1" newline bitfld.long 0x8 2. "RMW3_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_cache_tag_pipe_busecc_pend" "0,1" newline bitfld.long 0x8 1. "RMW3_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_busecc_pend" "0,1" newline bitfld.long 0x8 0. "DATARAM_BANK2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank2_busecc_pend" "0,1" line.long 0xC "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_ded_enable_clr_reg3,Interrupt Enable Clear Register 3" bitfld.long 0xC 1. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0xC 0. "EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_msmc_cmd_buffer_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP_MSMC_ECC_AGGR0__CFG_MSMC_ECC0_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_ECC_AGGR1 (COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_ECC_AGGR1)" base ad:0x4D20000400 rgroup.long 0x0++0x3 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "VBUSP_CFG_ECC_AGGR3_P2P_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_ecc_aggr3_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 30. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR2_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_ecc_aggr2_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 28. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "J7AE_MSMC_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_gicss_m2m_bridge_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 25. "J7AE_MSMC_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_gicss_m2m_bridge_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 24. "DDRSS1_SRC_P2M_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for ddrss1_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x4 23. "DDRSS1_SRC_P2M_BUSECC_PEND,Interrupt Pending Status for ddrss1_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x4 22. "DDRSS1_M2M_SRC_VBUSS_PEND,Interrupt Pending Status for ddrss1_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x4 21. "DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for ddrss0_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x4 20. "DDRSS0_SRC_P2M_BUSECC_PEND,Interrupt Pending Status for ddrss0_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x4 19. "DDRSS0_M2M_SRC_VBUSS_PEND,Interrupt Pending Status for ddrss0_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x4 18. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS1_P2P_BRIDGE_VBUSP_DDRSS1_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss1_p2p_bridge_vbusp_ddrss1_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 17. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_VBUSP_DDRSS0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss0_p2p_bridge_vbusp_ddrss0_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusm_gicss_p2m_bridge_vbusm_gicss_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 14. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x4 13. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_pend" "0,1" newline bitfld.long 0x4 12. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x4 11. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_pend" "0,1" newline bitfld.long 0x4 10. "VBUSP_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_wrap_cbass_cbass_clk4_clk_clk_edc_busecc_pend" "0,1" newline bitfld.long 0x4 9. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR1_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 8. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 7. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_scr1_scr_j7ae_msmc_cfg_wrap_cbass_scr1_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 6. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_CBASS_INT_CLK4_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_clk4_clk_edc_ctrl_cbass_int_clk4_busecc_pend" "0,1" newline bitfld.long 0x4 5. "DMSC_MMR_PRIVID_EDC_CTRL_BUSECC_BUSECC_PEND,Interrupt Pending Status for dmsc_mmr_privid_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x4 4. "DMSC_MMR_EMULATION_EDC_CTRL_BUSECC_BUSECC_PEND,Interrupt Pending Status for dmsc_mmr_emulation_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x4 3. "DMSC_MMR_BOOT_EDC_CTRL_BUSECC_BUSECC_PEND,Interrupt Pending Status for dmsc_mmr_boot_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x4 2. "VBUSP_DMSC_CBASS_CBASS_SCR_SCR_EDC_BUSECC_0_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cbass_scr_scr_edc_busecc_0_pend" "0,1" newline bitfld.long 0x4 1. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_dru0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 0. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_src_busecc_pend" "0,1" line.long 0x8 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 8. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x8 7. "GICSS_VBUSM_GASKET_EDC_CTRL_PEND,Interrupt Pending Status for gicss_vbusm_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 6. "GICSS_VBUSM_GASKET_RD_RAMECC_PEND,Interrupt Pending Status for gicss_vbusm_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x8 5. "GICSS_VBUSM_GASKET_WR_RAMECC_PEND,Interrupt Pending Status for gicss_vbusm_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x8 4. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_GICSS_VBUSM_GASKET_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac5_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x8 2. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac4_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x8 1. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x8 0. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR3_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR3_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x7 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "VBUSP_CFG_ECC_AGGR3_P2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_ecc_aggr3_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 30. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR2_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_ecc_aggr2_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 28. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "J7AE_MSMC_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_gicss_m2m_bridge_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 25. "J7AE_MSMC_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_gicss_m2m_bridge_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 24. "DDRSS1_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddrss1_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 23. "DDRSS1_SRC_P2M_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddrss1_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x0 22. "DDRSS1_M2M_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ddrss1_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 21. "DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddrss0_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 20. "DDRSS0_SRC_P2M_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddrss0_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x0 19. "DDRSS0_M2M_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ddrss0_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 18. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS1_P2P_BRIDGE_VBUSP_DDRSS1_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss1_p2p_bridge_vbusp_ddrss1_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 17. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_VBUSP_DDRSS0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss0_p2p_bridge_vbusp_ddrss0_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusm_gicss_p2m_bridge_vbusm_gicss_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 14. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 13. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 12. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 11. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_pend" "0,1" newline bitfld.long 0x0 10. "VBUSP_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_wrap_cbass_cbass_clk4_clk_clk_edc_busecc_pend" "0,1" newline bitfld.long 0x0 9. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR1_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 8. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 7. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 6. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_CBASS_INT_CLK4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_clk4_clk_edc_ctrl_cbass_int_clk4_busecc_pend" "0,1" newline bitfld.long 0x0 5. "DMSC_MMR_PRIVID_EDC_CTRL_BUSECC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dmsc_mmr_privid_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 4. "DMSC_MMR_EMULATION_EDC_CTRL_BUSECC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dmsc_mmr_emulation_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 3. "DMSC_MMR_BOOT_EDC_CTRL_BUSECC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dmsc_mmr_boot_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 2. "VBUSP_DMSC_CBASS_CBASS_SCR_SCR_EDC_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cbass_scr_scr_edc_busecc_0_pend" "0,1" newline bitfld.long 0x0 1. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_dru0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 0. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_src_busecc_pend" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 8. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x4 7. "GICSS_VBUSM_GASKET_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for gicss_vbusm_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 6. "GICSS_VBUSM_GASKET_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for gicss_vbusm_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "GICSS_VBUSM_GASKET_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for gicss_vbusm_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_GICSS_VBUSM_GASKET_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac5_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 2. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac4_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 1. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 0. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR3_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR3_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "VBUSP_CFG_ECC_AGGR3_P2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_ecc_aggr3_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 30. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR2_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_ecc_aggr2_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 28. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "J7AE_MSMC_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_gicss_m2m_bridge_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 25. "J7AE_MSMC_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_gicss_m2m_bridge_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 24. "DDRSS1_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddrss1_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 23. "DDRSS1_SRC_P2M_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddrss1_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x0 22. "DDRSS1_M2M_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ddrss1_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 21. "DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddrss0_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 20. "DDRSS0_SRC_P2M_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddrss0_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x0 19. "DDRSS0_M2M_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ddrss0_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 18. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS1_P2P_BRIDGE_VBUSP_DDRSS1_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss1_p2p_bridge_vbusp_ddrss1_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 17. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_VBUSP_DDRSS0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss0_p2p_bridge_vbusp_ddrss0_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusm_gicss_p2m_bridge_vbusm_gicss_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 14. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 13. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 12. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 11. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_pend" "0,1" newline bitfld.long 0x0 10. "VBUSP_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_wrap_cbass_cbass_clk4_clk_clk_edc_busecc_pend" "0,1" newline bitfld.long 0x0 9. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR1_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 8. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 7. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 6. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_CBASS_INT_CLK4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_clk4_clk_edc_ctrl_cbass_int_clk4_busecc_pend" "0,1" newline bitfld.long 0x0 5. "DMSC_MMR_PRIVID_EDC_CTRL_BUSECC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dmsc_mmr_privid_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 4. "DMSC_MMR_EMULATION_EDC_CTRL_BUSECC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dmsc_mmr_emulation_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 3. "DMSC_MMR_BOOT_EDC_CTRL_BUSECC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dmsc_mmr_boot_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 2. "VBUSP_DMSC_CBASS_CBASS_SCR_SCR_EDC_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cbass_scr_scr_edc_busecc_0_pend" "0,1" newline bitfld.long 0x0 1. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_dru0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 0. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_src_busecc_pend" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 8. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x4 7. "GICSS_VBUSM_GASKET_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for gicss_vbusm_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 6. "GICSS_VBUSM_GASKET_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for gicss_vbusm_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "GICSS_VBUSM_GASKET_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for gicss_vbusm_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_GICSS_VBUSM_GASKET_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac5_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 2. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac4_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 1. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 0. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR3_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR3_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0xB line.long 0x0 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "VBUSP_CFG_ECC_AGGR3_P2P_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_ecc_aggr3_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 30. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR2_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_ecc_aggr2_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 28. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "J7AE_MSMC_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_gicss_m2m_bridge_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 25. "J7AE_MSMC_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_gicss_m2m_bridge_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 24. "DDRSS1_SRC_P2M_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for ddrss1_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x4 23. "DDRSS1_SRC_P2M_BUSECC_PEND,Interrupt Pending Status for ddrss1_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x4 22. "DDRSS1_M2M_SRC_VBUSS_PEND,Interrupt Pending Status for ddrss1_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x4 21. "DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for ddrss0_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x4 20. "DDRSS0_SRC_P2M_BUSECC_PEND,Interrupt Pending Status for ddrss0_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x4 19. "DDRSS0_M2M_SRC_VBUSS_PEND,Interrupt Pending Status for ddrss0_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x4 18. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS1_P2P_BRIDGE_VBUSP_DDRSS1_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss1_p2p_bridge_vbusp_ddrss1_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 17. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_VBUSP_DDRSS0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss0_p2p_bridge_vbusp_ddrss0_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusm_gicss_p2m_bridge_vbusm_gicss_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 14. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x4 13. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_pend" "0,1" newline bitfld.long 0x4 12. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x4 11. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_pend" "0,1" newline bitfld.long 0x4 10. "VBUSP_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_wrap_cbass_cbass_clk4_clk_clk_edc_busecc_pend" "0,1" newline bitfld.long 0x4 9. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR1_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 8. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 7. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_scr1_scr_j7ae_msmc_cfg_wrap_cbass_scr1_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 6. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_CBASS_INT_CLK4_BUSECC_PEND,Interrupt Pending Status for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_clk4_clk_edc_ctrl_cbass_int_clk4_busecc_pend" "0,1" newline bitfld.long 0x4 5. "DMSC_MMR_PRIVID_EDC_CTRL_BUSECC_BUSECC_PEND,Interrupt Pending Status for dmsc_mmr_privid_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x4 4. "DMSC_MMR_EMULATION_EDC_CTRL_BUSECC_BUSECC_PEND,Interrupt Pending Status for dmsc_mmr_emulation_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x4 3. "DMSC_MMR_BOOT_EDC_CTRL_BUSECC_BUSECC_PEND,Interrupt Pending Status for dmsc_mmr_boot_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x4 2. "VBUSP_DMSC_CBASS_CBASS_SCR_SCR_EDC_BUSECC_0_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cbass_scr_scr_edc_busecc_0_pend" "0,1" newline bitfld.long 0x4 1. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_dru0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 0. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_src_busecc_pend" "0,1" line.long 0x8 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 8. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x8 7. "GICSS_VBUSM_GASKET_EDC_CTRL_PEND,Interrupt Pending Status for gicss_vbusm_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 6. "GICSS_VBUSM_GASKET_RD_RAMECC_PEND,Interrupt Pending Status for gicss_vbusm_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x8 5. "GICSS_VBUSM_GASKET_WR_RAMECC_PEND,Interrupt Pending Status for gicss_vbusm_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x8 4. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_GICSS_VBUSM_GASKET_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac5_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x8 2. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac4_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x8 1. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x8 0. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR3_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR3_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x7 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "VBUSP_CFG_ECC_AGGR3_P2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_ecc_aggr3_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 30. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR2_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_ecc_aggr2_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 28. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "J7AE_MSMC_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_gicss_m2m_bridge_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 25. "J7AE_MSMC_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_gicss_m2m_bridge_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 24. "DDRSS1_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddrss1_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 23. "DDRSS1_SRC_P2M_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddrss1_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x0 22. "DDRSS1_M2M_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ddrss1_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 21. "DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddrss0_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 20. "DDRSS0_SRC_P2M_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddrss0_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x0 19. "DDRSS0_M2M_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ddrss0_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 18. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS1_P2P_BRIDGE_VBUSP_DDRSS1_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss1_p2p_bridge_vbusp_ddrss1_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 17. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_VBUSP_DDRSS0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss0_p2p_bridge_vbusp_ddrss0_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusm_gicss_p2m_bridge_vbusm_gicss_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 14. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 13. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 12. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 11. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_pend" "0,1" newline bitfld.long 0x0 10. "VBUSP_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_wrap_cbass_cbass_clk4_clk_clk_edc_busecc_pend" "0,1" newline bitfld.long 0x0 9. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR1_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 8. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 7. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 6. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_CBASS_INT_CLK4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_clk4_clk_edc_ctrl_cbass_int_clk4_busecc_pend" "0,1" newline bitfld.long 0x0 5. "DMSC_MMR_PRIVID_EDC_CTRL_BUSECC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dmsc_mmr_privid_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 4. "DMSC_MMR_EMULATION_EDC_CTRL_BUSECC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dmsc_mmr_emulation_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 3. "DMSC_MMR_BOOT_EDC_CTRL_BUSECC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dmsc_mmr_boot_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 2. "VBUSP_DMSC_CBASS_CBASS_SCR_SCR_EDC_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cbass_scr_scr_edc_busecc_0_pend" "0,1" newline bitfld.long 0x0 1. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_dru0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 0. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_src_busecc_pend" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 8. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x4 7. "GICSS_VBUSM_GASKET_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for gicss_vbusm_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 6. "GICSS_VBUSM_GASKET_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for gicss_vbusm_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "GICSS_VBUSM_GASKET_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for gicss_vbusm_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_GICSS_VBUSM_GASKET_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac5_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 2. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac4_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 1. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 0. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR3_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR3_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "VBUSP_CFG_ECC_AGGR3_P2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_ecc_aggr3_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 30. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR2_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_ecc_aggr2_p2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 28. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP5_P2P_BRIDGE_VBUSP4_CFG_DSP5_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP4_CFG_DSP4_P2P_BRIDGE_VBUSP4_CFG_DSP4_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "J7AE_MSMC_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_gicss_m2m_bridge_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 25. "J7AE_MSMC_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_gicss_m2m_bridge_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 24. "DDRSS1_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddrss1_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 23. "DDRSS1_SRC_P2M_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddrss1_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x0 22. "DDRSS1_M2M_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ddrss1_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 21. "DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddrss0_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 20. "DDRSS0_SRC_P2M_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddrss0_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x0 19. "DDRSS0_M2M_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ddrss0_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 18. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS1_P2P_BRIDGE_VBUSP_DDRSS1_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss1_p2p_bridge_vbusp_ddrss1_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 17. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_VBUSP_DDRSS0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusp_ddrss0_p2p_bridge_vbusp_ddrss0_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 16. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSM_GICSS_P2M_BRIDGE_VBUSM_GICSS_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_vbusm_gicss_p2m_bridge_vbusm_gicss_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 14. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_p2m_reassembly_busecc_pend" "0,1" newline bitfld.long 0x0 13. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 12. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 11. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_pend" "0,1" newline bitfld.long 0x0 10. "VBUSP_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_wrap_cbass_cbass_clk4_clk_clk_edc_busecc_pend" "0,1" newline bitfld.long 0x0 9. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR1_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 8. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 7. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_J7AE_MSMC_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 6. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_CBASS_INT_CLK4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7ae_msmc_cfg_wrap_cbass_j7ae_msmc_cfg_wrap_cbass_clk4_clk_edc_ctrl_cbass_int_clk4_busecc_pend" "0,1" newline bitfld.long 0x0 5. "DMSC_MMR_PRIVID_EDC_CTRL_BUSECC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dmsc_mmr_privid_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 4. "DMSC_MMR_EMULATION_EDC_CTRL_BUSECC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dmsc_mmr_emulation_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 3. "DMSC_MMR_BOOT_EDC_CTRL_BUSECC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dmsc_mmr_boot_edc_ctrl_busecc_busecc_pend" "0,1" newline bitfld.long 0x0 2. "VBUSP_DMSC_CBASS_CBASS_SCR_SCR_EDC_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cbass_scr_scr_edc_busecc_0_pend" "0,1" newline bitfld.long 0x0 1. "VBUSP_DMSC_CBASS_DRU0_FW_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_dru0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 0. "VBUSP_DMSC_CBASS_DRU0_MMR_FW_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_dru0_mmr_fw_bridge_src_busecc_pend" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 8. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x4 7. "GICSS_VBUSM_GASKET_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for gicss_vbusm_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 6. "GICSS_VBUSM_GASKET_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for gicss_vbusm_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "GICSS_VBUSM_GASKET_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for gicss_vbusm_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_GICSS_VBUSM_GASKET_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "VBUSP_DMSC_CBASS_CPAC5_FW_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac5_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 2. "VBUSP_DMSC_CBASS_CPAC4_FW_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac4_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 1. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac0_fw_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 0. "J7AE_MSMC_CFG_WRAP_CBASS_J7AE_MSMC_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR3_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR3_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "__VBUSP_MSMC_ECC_AGGR1__CFG_MSMC_ECC1_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif tree.end tree.end endif tree "CPSW" base ad:0x0 tree "CPSW1_ECC (CPSW1_ECC)" base ad:0x2A22000 rgroup.long 0x0++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_ECC_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_ECC_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_ECC_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_ECC_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_ECC_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "CPSW_NUSS_VBUSP_ECC_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1" bitfld.long 0x4 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1" bitfld.long 0x4 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1" newline bitfld.long 0x4 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1" bitfld.long 0x4 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1" bitfld.long 0x4 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1" newline bitfld.long 0x4 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1" bitfld.long 0x4 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1" bitfld.long 0x4 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1" newline bitfld.long 0x4 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1" bitfld.long 0x4 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1" bitfld.long 0x4 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1" newline bitfld.long 0x4 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1" bitfld.long 0x4 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1" bitfld.long 0x4 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1" newline bitfld.long 0x4 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1" bitfld.long 0x4 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1" bitfld.long 0x4 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1" newline bitfld.long 0x4 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1" bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_ECC_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1" bitfld.long 0x0 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1" bitfld.long 0x0 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1" newline bitfld.long 0x0 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1" bitfld.long 0x0 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1" bitfld.long 0x0 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1" newline bitfld.long 0x0 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1" bitfld.long 0x0 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1" bitfld.long 0x0 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1" newline bitfld.long 0x0 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1" bitfld.long 0x0 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1" bitfld.long 0x0 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1" newline bitfld.long 0x0 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1" bitfld.long 0x0 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1" bitfld.long 0x0 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1" newline bitfld.long 0x0 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1" bitfld.long 0x0 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1" bitfld.long 0x0 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1" newline bitfld.long 0x0 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_ECC_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1" bitfld.long 0x0 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1" bitfld.long 0x0 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1" newline bitfld.long 0x0 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1" bitfld.long 0x0 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1" bitfld.long 0x0 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1" newline bitfld.long 0x0 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1" bitfld.long 0x0 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1" bitfld.long 0x0 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1" newline bitfld.long 0x0 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1" bitfld.long 0x0 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1" bitfld.long 0x0 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1" newline bitfld.long 0x0 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1" bitfld.long 0x0 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1" bitfld.long 0x0 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1" newline bitfld.long 0x0 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1" bitfld.long 0x0 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1" bitfld.long 0x0 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1" newline bitfld.long 0x0 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_ECC_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "CPSW_NUSS_VBUSP_ECC_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1" bitfld.long 0x4 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1" bitfld.long 0x4 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1" newline bitfld.long 0x4 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1" bitfld.long 0x4 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1" bitfld.long 0x4 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1" newline bitfld.long 0x4 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1" bitfld.long 0x4 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1" bitfld.long 0x4 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1" newline bitfld.long 0x4 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1" bitfld.long 0x4 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1" bitfld.long 0x4 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1" newline bitfld.long 0x4 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1" bitfld.long 0x4 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1" bitfld.long 0x4 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1" newline bitfld.long 0x4 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1" bitfld.long 0x4 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1" bitfld.long 0x4 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1" newline bitfld.long 0x4 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1" bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_ECC_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1" bitfld.long 0x0 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1" bitfld.long 0x0 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1" newline bitfld.long 0x0 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1" bitfld.long 0x0 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1" bitfld.long 0x0 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1" newline bitfld.long 0x0 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1" bitfld.long 0x0 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1" bitfld.long 0x0 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1" newline bitfld.long 0x0 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1" bitfld.long 0x0 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1" bitfld.long 0x0 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1" newline bitfld.long 0x0 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1" bitfld.long 0x0 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1" bitfld.long 0x0 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1" newline bitfld.long 0x0 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1" bitfld.long 0x0 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1" bitfld.long 0x0 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1" newline bitfld.long 0x0 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_ECC_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1" bitfld.long 0x0 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1" bitfld.long 0x0 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1" newline bitfld.long 0x0 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1" bitfld.long 0x0 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1" bitfld.long 0x0 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1" newline bitfld.long 0x0 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1" bitfld.long 0x0 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1" bitfld.long 0x0 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1" newline bitfld.long 0x0 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1" bitfld.long 0x0 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1" bitfld.long 0x0 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1" newline bitfld.long 0x0 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1" bitfld.long 0x0 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1" bitfld.long 0x0 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1" newline bitfld.long 0x0 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1" bitfld.long 0x0 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1" bitfld.long 0x0 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1" newline bitfld.long 0x0 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "CPSW_NUSS_VBUSP_ECC_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "CPSW_NUSS_VBUSP_ECC_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "CPSW_NUSS_VBUSP_ECC_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "CPSW_NUSS_VBUSP_ECC_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "CPSW1_NUSS (CPSW1_NUSS)" base ad:0xC200000 rgroup.long 0x0++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_CPSW_NUSS_IDVER_REG,CPSW_NUSS ID Version Register" hexmask.long.word 0x0 16.--31. 1. "IDENT,Identification value" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" rgroup.long 0x4++0xF line.long 0x0 "CPSW_NUSS_VBUSP_SYNCE_COUNT_REG,CPSW_NUSS SYNCE Count Register" hexmask.long 0x0 0.--31. 1. "SYNCE_CNT,Sync E Count Value" line.long 0x4 "CPSW_NUSS_VBUSP_SYNCE_MUX_REG,CPSW_NUSS Synce Mux Register" hexmask.long.byte 0x4 0.--5. 1. "SYNCE_SEL,Sync E Select Value" line.long 0x8 "CPSW_NUSS_VBUSP_CONTROL_REG,CPSW_NUSS Control Register" bitfld.long 0x8 1. "EEE_PHY_ONLY,Energy Efficient Enable Phy Only Mode: 0=The low power indicate state includes gating off the CPPI_GCLK to the CPSW 1=The low power indicate state does not gate the clock to the CPSW" "0: The low power indicate state includes gating off..,1: The low power indicate state does not gate the.." newline bitfld.long 0x8 0. "EEE_EN,Energy Efficient Ethernet Enable: 0=EEE is disabled 1=EEE is enabled" "0: EEE is disabled,1: EEE is enabled" line.long 0xC "CPSW_NUSS_VBUSP_SGMII_MODE_REG,CPSW_NUSS SyncE Mux Register" bitfld.long 0xC 0. "SYNCE_SEL,SGMII_MODE Input" "0,1" rgroup.long 0x18++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_RGMII_STATUS_REG,CPSW_NUSS RGMII Status Register" bitfld.long 0x0 3. "FULLDUPLEX,Rgmii full dulex: 0=Half-duplex 1=Full-duplex" "0: Half-duplex,1: Full-duplex" newline bitfld.long 0x0 1.--2. "SPEED,Rgmii speed: 00=10Mbps 01=100Mbps 10=1000Mbps 11=reserved" "0,1,2,3" newline bitfld.long 0x0 0. "LINK,Rgmii link indicator: 0=Link is down 1=Link is up" "0: Link is down,1: Link is up" line.long 0x4 "CPSW_NUSS_VBUSP_SUBSSYSTEM_STATUS_REG,CPSW_NUSS Status Register" bitfld.long 0x4 0. "EEE_CLKSTOP_ACK,Energy Efficient Ethernet clockstop acknowledge from CPSW" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_SGMII_IDVER_REG,SGMII IDVER register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Module value" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" rgroup.long 0x104++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_SOFT_RESET_REG,SGMII Soft Reset Register" bitfld.long 0x0 1. "RT_SOFT_RESET,Transmit and receive software reset" "0,1" newline bitfld.long 0x0 0. "SOFT_RESET,Software reset" "0,1" rgroup.long 0x110++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_CONTROL_REG,SGMII Control Register" bitfld.long 0x0 6. "TEST_PATTERN_EN,Test pattern enable" "0,1" newline bitfld.long 0x0 5. "MASTER,Master mode" "0,1" newline bitfld.long 0x0 4. "LOOPBACK,Loopback mode" "0,1" newline bitfld.long 0x0 3. "MR_NP_LOADED,Next page loaded" "0,1" newline bitfld.long 0x0 2. "FAST_LINK_TIMER,Fast link timer" "0,1" newline bitfld.long 0x0 1. "MR_AN_RESTART,Auto-negotiation restart" "0,1" newline bitfld.long 0x0 0. "MR_AN_ENABLE,Auto-negotiation enable" "0,1" rgroup.long 0x114++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_STATUS_REG,SGMII Status Register" bitfld.long 0x0 5. "FIB_SIG_DETECT,Fiber signal detect" "0,1" newline bitfld.long 0x0 4. "LOCK,Lock" "0,1" newline bitfld.long 0x0 3. "MR_PAGE_RX,Next page received" "0,1" newline bitfld.long 0x0 2. "MR_AN_COMPLETE,Auto-negotiation complete" "0,1" newline bitfld.long 0x0 1. "AN_ERROR,Auto-negotiation error" "0,1" newline bitfld.long 0x0 0. "LINK,Link indicator" "0,1" rgroup.long 0x118++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_MR_ADV_ABILITY_REG,SGMII MR Advertized Ability Register" hexmask.long.word 0x0 0.--15. 1. "MR_ADV_ABILITY,Advertised ability" line.long 0x4 "CPSW_NUSS_VBUSP_MR_NP_TX_REG,SGMII Next Pate Transmit Register" hexmask.long.word 0x4 0.--15. 1. "MR_NP_TX,Next page transmit" rgroup.long 0x120++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_MR_LP_ADV_ABILITY_REG,SGMII Link Partner Advertized Ability Register" hexmask.long.word 0x0 0.--15. 1. "MR_LP_ADV_ABILITY,Link partner advertised ability" line.long 0x4 "CPSW_NUSS_VBUSP_MR_LP_NP_RX_REG,SGMII Link Partner Next Page Receive Register" hexmask.long.word 0x4 0.--15. 1. "MR_LP_NP_RX,Link Partner Next Page Received" rgroup.long 0x130++0xB line.long 0x0 "CPSW_NUSS_VBUSP_TX_CFG_REG,SGMII Transmit Configuration Register" hexmask.long 0x0 0.--31. 1. "TX_CFG,Transmit configuration register output" line.long 0x4 "CPSW_NUSS_VBUSP_RX_CFG_REG,SGMII Receive Configuration Register" hexmask.long 0x4 0.--31. 1. "RX_CFG,Receive configuration register output" line.long 0x8 "CPSW_NUSS_VBUSP_AUX_CFG_REG,SGMII Auxiliary Configuration Register" hexmask.long 0x8 0.--31. 1. "AUX_CFG,Auxiliary configuration register output" rgroup.long 0x140++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_DIAG_CLEAR_REG,SGMII Diagnostics Clear Register" bitfld.long 0x0 0. "DIAG_CLEAR,Diagnostics clear" "0,1" line.long 0x4 "CPSW_NUSS_VBUSP_DIAG_CONTROL_REG,SGMII Diagnostics Control Register" bitfld.long 0x4 4.--6. "DIAG_SM_SEL,Diagnostic select" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--1. "DIAG_EDGE_SEL,Diagnostics hold signals edge select" "0,1,2,3" rgroup.long 0x148++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_DIAG_STATUS_REG,SGMII Diagnostics Status Register" hexmask.long.word 0x0 0.--15. 1. "DIAG_STATUS,Diagnostics status" rgroup.long 0xF00++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_MDIO_VERSION_REG,MDIO Version Register" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0xF04++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_CONTROL_REG,MDIO Control Register" rbitfld.long 0x0 31. "IDLE,MDIO state machine idle" "0,1" newline bitfld.long 0x0 30. "ENABLE,Enable control" "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "HIGHEST_USER_CHANNEL,Highest user channel" newline bitfld.long 0x0 20. "PREAMBLE,Preamble disable" "0,1" newline bitfld.long 0x0 19. "FAULT,Fault indicator" "0,1" newline bitfld.long 0x0 18. "FAULT_DETECT_ENABLE,Fault detect enable" "0,1" newline bitfld.long 0x0 17. "INT_TEST_ENABLE,Interrupt test enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "CLKDIV,Clock divider" line.long 0x4 "CPSW_NUSS_VBUSP_ALIVE_REG,MDIO Alive Register" hexmask.long 0x4 0.--31. 1. "ALIVE,MDIO alive" rgroup.long 0xF0C++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_LINK_REG,MDIO Link Register" hexmask.long 0x0 0.--31. 1. "LINK,MDIO link state" rgroup.long 0xF10++0x37 line.long 0x0 "CPSW_NUSS_VBUSP_LINK_INT_RAW_REG,MDIO Link Interrupt Raw Register" bitfld.long 0x0 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3" line.long 0x4 "CPSW_NUSS_VBUSP_LINK_INT_MASKED_REG,MDIO Link Interrupt Masked Register" bitfld.long 0x4 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3" line.long 0x8 "CPSW_NUSS_VBUSP_LINK_INT_MASK_SET_REG,MDIO Link Interrupt Mask Set Register" bitfld.long 0x8 0. "LINKINTMASKSET,MDIO link interrupt mask set" "0,1" line.long 0xC "CPSW_NUSS_VBUSP_LINK_INT_MASK_CLEAR_REG,MDIO Link Interrupt Mask Clear Register" bitfld.long 0xC 0. "LINKINTMASKCLR,MDIO link interrupt mask clear" "0,1" line.long 0x10 "CPSW_NUSS_VBUSP_USER_INT_RAW_REG,MDIO User Interrupt Raw Register" bitfld.long 0x10 0.--1. "USERINTRAW,User interrupt raw" "0,1,2,3" line.long 0x14 "CPSW_NUSS_VBUSP_USER_INT_MASKED_REG,MDIO User Interrupt Masked Register" bitfld.long 0x14 0.--1. "USERINTMASKED,User interrupt masked" "0,1,2,3" line.long 0x18 "CPSW_NUSS_VBUSP_USER_INT_MASK_SET_REG,MDIO User Interrupt Mask Set Register" bitfld.long 0x18 0.--1. "USERINTMASKSET,MDIO user interrupt mask set" "0,1,2,3" line.long 0x1C "CPSW_NUSS_VBUSP_USER_INT_MASK_CLEAR_REG,MDIO User Interrupt Mask Clear Register" bitfld.long 0x1C 0.--1. "USERINTMASKCLR,MDIO user interrupt mask clear" "0,1,2,3" line.long 0x20 "CPSW_NUSS_VBUSP_MANUAL_IF_REG,MDIO Manual Interface Register" bitfld.long 0x20 2. "MDIO_MDCLK_O,MDIO Clock Output" "0,1" newline bitfld.long 0x20 1. "MDIO_OE,MDIO Output Enable" "0,1" newline bitfld.long 0x20 0. "MDIO_PIN,MDIO Pin" "0,1" line.long 0x24 "CPSW_NUSS_VBUSP_POLL_REG,MDIO Poll Register" bitfld.long 0x24 31. "MANUALMODE,MDIO Manual Mode" "0,1" newline bitfld.long 0x24 30. "STATECHANGEMODE,MDIO State Change Mode" "0,1" newline hexmask.long.byte 0x24 0.--7. 1. "IPG,MDIO IPG" line.long 0x28 "CPSW_NUSS_VBUSP_POLL_EN_REG,MDIO Poll Enable Register" hexmask.long 0x28 0.--31. 1. "POLL_EN,MDIO Poll Enable" line.long 0x2C "CPSW_NUSS_VBUSP_CLAUS45_REG,MDIO Clause45 Register" hexmask.long 0x2C 0.--31. 1. "CLAUSE45,MDIO Clause 45" line.long 0x30 "CPSW_NUSS_VBUSP_USER_ADDR0_REG,MDIO Address 0 Register" hexmask.long.word 0x30 0.--15. 1. "USER_ADDR0,MDIO USER Address 0" line.long 0x34 "CPSW_NUSS_VBUSP_USER_ADDR1_REG,MDIO Address 1 Register" hexmask.long.word 0x34 0.--15. 1. "USER_ADDR1,MDIO USER Address 1" rgroup.long 0x1000++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_REVISION,Revision Register" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTLVER,RTL revisions" newline bitfld.long 0x0 8.--10. "MAJREV,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,Minor revision" rgroup.long 0x1010++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_eoi_reg,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector" rgroup.long 0x1014++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_intr_vector_reg,Interrupt Vector Register" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR,Interrupt Vector Register" rgroup.long 0x1100++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_enable_reg_out_pulse_0,Enable Register 0" bitfld.long 0x0 2. "ENABLE_OUT_PULSE_EN_STAT_PENDA,Enable Set for out_pulse_en_stat_penda" "0,1" newline bitfld.long 0x0 1. "ENABLE_OUT_PULSE_EN_MDIO_PENDA,Enable Set for out_pulse_en_mdio_penda" "0,1" newline bitfld.long 0x0 0. "ENABLE_OUT_PULSE_EN_EVNT_PENDA,Enable Set for out_pulse_en_evnt_penda" "0,1" rgroup.long 0x1300++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_enable_clr_reg_out_pulse_0,Enable Clear Register 0" bitfld.long 0x0 2. "ENABLE_OUT_PULSE_EN_STAT_PENDA_CLR,Enable Clear for out_pulse_en_stat_penda" "0,1" newline bitfld.long 0x0 1. "ENABLE_OUT_PULSE_EN_MDIO_PENDA_CLR,Enable Clear for out_pulse_en_mdio_penda" "0,1" newline bitfld.long 0x0 0. "ENABLE_OUT_PULSE_EN_EVNT_PENDA_CLR,Enable Clear for out_pulse_en_evnt_penda" "0,1" rgroup.long 0x1500++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_status_reg_out_pulse_0,Status Register 0" bitfld.long 0x0 2. "STATUS_OUT_PULSE_STAT_PENDA,Status for out_pulse_en_stat_penda" "0,1" newline bitfld.long 0x0 1. "STATUS_OUT_PULSE_MDIO_PENDA,Status for out_pulse_en_mdio_penda" "0,1" newline bitfld.long 0x0 0. "STATUS_OUT_PULSE_EVNT_PENDA,Status for out_pulse_en_evnt_penda" "0,1" rgroup.long 0x1A80++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_intr_vector_reg_out_pulse,Interrupt Vector for out_pulse" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR_OUT_PULSE,Interrupt Vector" rgroup.long 0x20000++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_CPSW_ID_VER_REG,CPSW ID Version" hexmask.long.word 0x0 16.--31. 1. "IDENT,Identification Value" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL Version Value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major Version Value" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM_VER,Custom Version Value" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_VER,Minor Version Value" rgroup.long 0x20004++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_CONTROL_REG,CPSW Switch Control" bitfld.long 0x0 31. "ECC_CRC_MODE,ECC CRC Mode" "0,1" newline bitfld.long 0x0 18. "EST_ENABLE,Intersperced Express Traffic enable" "0,1" newline bitfld.long 0x0 17. "IET_ENABLE,Intersperced Express Traffic enable" "0,1" newline bitfld.long 0x0 16. "EEE_ENABLE,Energy Efficient Ethernet enable" "0,1" newline bitfld.long 0x0 15. "P0_RX_PASS_CRC_ERR,Port 0 Pass Received CRC errors" "0,1" newline bitfld.long 0x0 14. "P0_RX_PAD,Port 0 Receive Short Packet Pad" "0,1" newline bitfld.long 0x0 13. "P0_TX_CRC_REMOVE,Port 0 Transmit CRC remove" "0,1" newline bitfld.long 0x0 11. "P8_PASS_PRI_TAGGED,Port 8 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 10. "P7_PASS_PRI_TAGGED,Port 7 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 9. "P6_PASS_PRI_TAGGED,Port 6 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 8. "P5_PASS_PRI_TAGGED,Port 5 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 7. "P4_PASS_PRI_TAGGED,Port 4 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 6. "P3_PASS_PRI_TAGGED,Port 3 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 5. "P2_PASS_PRI_TAGGED,Port 2 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 4. "P1_PASS_PRI_TAGGED,Port 1 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 3. "P0_PASS_PRI_TAGGED,Port 0 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 2. "P0_ENABLE,Port 0 Enable" "0,1" newline bitfld.long 0x0 1. "VLAN_AWARE,VLAN Aware Mode" "0,1" newline bitfld.long 0x0 0. "S_CN_SWITCH,VLAN Aware Mode" "0,1" rgroup.long 0x20010++0x37 line.long 0x0 "CPSW_NUSS_VBUSP_EM_CONTROL_REG,CPSW Emulation Control" bitfld.long 0x0 1. "SOFT,Emulation Soft Bit" "0,1" newline bitfld.long 0x0 0. "FREE,Emulation Free Bit" "0,1" line.long 0x4 "CPSW_NUSS_VBUSP_STAT_PORT_EN_REG,CPSW Statistics Port Enable" bitfld.long 0x4 8. "P8_STAT_EN,Port 8 Statistics Enable" "0,1" newline bitfld.long 0x4 7. "P7_STAT_EN,Port 7 Statistics Enable" "0,1" newline bitfld.long 0x4 6. "P6_STAT_EN,Port 6 Statistics Enable" "0,1" newline bitfld.long 0x4 5. "P5_STAT_EN,Port 5 Statistics Enable" "0,1" newline bitfld.long 0x4 4. "P4_STAT_EN,Port 4 Statistics Enable" "0,1" newline bitfld.long 0x4 3. "P3_STAT_EN,Port 3 Statistics Enable" "0,1" newline bitfld.long 0x4 2. "P2_STAT_EN,Port 2 Statistics Enable" "0,1" newline bitfld.long 0x4 1. "P1_STAT_EN,Port 1 Statistics Enable" "0,1" newline bitfld.long 0x4 0. "P0_STAT_EN,Port 0 Statistics Enable" "0,1" line.long 0x8 "CPSW_NUSS_VBUSP_PTYPE_REG,CPSW Transmit Priority Type" bitfld.long 0x8 16. "P8_PTYPE_ESC,Port 8 Priority Type Escalate" "0,1" newline bitfld.long 0x8 15. "P7_PTYPE_ESC,Port 7 Priority Type Escalate" "0,1" newline bitfld.long 0x8 14. "P6_PTYPE_ESC,Port 6 Priority Type Escalate" "0,1" newline bitfld.long 0x8 13. "P5_PTYPE_ESC,Port 5 Priority Type Escalate" "0,1" newline bitfld.long 0x8 12. "P4_PTYPE_ESC,Port 4 Priority Type Escalate" "0,1" newline bitfld.long 0x8 11. "P3_PTYPE_ESC,Port 3 Priority Type Escalate" "0,1" newline bitfld.long 0x8 10. "P2_PTYPE_ESC,Port 2 Priority Type Escalate" "0,1" newline bitfld.long 0x8 9. "P1_PTYPE_ESC,Port 1 Priority Type Escalate" "0,1" newline bitfld.long 0x8 8. "P0_PTYPE_ESC,Port 0 Priority Type Escalate" "0,1" newline hexmask.long.byte 0x8 0.--4. 1. "ESC_PRI_LD_VAL,Escalate Priority Load Value" line.long 0xC "CPSW_NUSS_VBUSP_SOFT_IDLE_REG,CPSW Software Idle" bitfld.long 0xC 0. "SOFT_IDLE,Software Idle" "0,1" line.long 0x10 "CPSW_NUSS_VBUSP_THRU_RATE_REG,CPSW Thru Rate" hexmask.long.byte 0x10 12.--15. 1. "SL_RX_THRU_RATE,Switch FIFO receive through rate" newline hexmask.long.byte 0x10 0.--3. 1. "P0_RX_THRU_RATE,CPPI FIFO receive through rate" line.long 0x14 "CPSW_NUSS_VBUSP_GAP_THRESH_REG,CPSW Transmit FIFO Short Gap Threshold" hexmask.long.byte 0x14 0.--4. 1. "GAP_THRESH,Short Gap Threshold" line.long 0x18 "CPSW_NUSS_VBUSP_TX_START_WDS_REG,CPSW Transmit FIFO Start Words" hexmask.long.word 0x18 0.--10. 1. "TX_START_WDS,FIFO Packet Transmit Start Words" line.long 0x1C "CPSW_NUSS_VBUSP_EEE_PRESCALE_REG,CPSW Energy Efficient Ethernet Prescale Value" hexmask.long.word 0x1C 0.--11. 1. "EEE_PRESCALE,Energy Efficient Ethernet Pre-scale count load value" line.long 0x20 "CPSW_NUSS_VBUSP_TX_G_OFLOW_THRESH_SET_REG,CPSW PFC Tx Global Out Flow Threshold Set" hexmask.long.byte 0x20 28.--31. 1. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" newline hexmask.long.byte 0x20 24.--27. 1. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" newline hexmask.long.byte 0x20 20.--23. 1. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" newline hexmask.long.byte 0x20 16.--19. 1. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" newline hexmask.long.byte 0x20 12.--15. 1. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" newline hexmask.long.byte 0x20 8.--11. 1. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" newline hexmask.long.byte 0x20 4.--7. 1. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" newline hexmask.long.byte 0x20 0.--3. 1. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" line.long 0x24 "CPSW_NUSS_VBUSP_TX_G_OFLOW_THRESH_CLR_REG,CPSW PFC Tx Global Out Flow Threshold Clear" hexmask.long.byte 0x24 28.--31. 1. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" newline hexmask.long.byte 0x24 24.--27. 1. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" newline hexmask.long.byte 0x24 20.--23. 1. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" newline hexmask.long.byte 0x24 16.--19. 1. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" newline hexmask.long.byte 0x24 12.--15. 1. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" newline hexmask.long.byte 0x24 8.--11. 1. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" newline hexmask.long.byte 0x24 4.--7. 1. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" newline hexmask.long.byte 0x24 0.--3. 1. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" line.long 0x28 "CPSW_NUSS_VBUSP_TX_G_BUF_THRESH_SET_L_REG,CPSW PFC Global Tx Buffer Threshold Set Low" hexmask.long.byte 0x28 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3" newline hexmask.long.byte 0x28 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2" newline hexmask.long.byte 0x28 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1" newline hexmask.long.byte 0x28 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0" line.long 0x2C "CPSW_NUSS_VBUSP_TX_G_BUF_THRESH_SET_H_REG,CPSW PFC Global Tx Buffer Threshold Set High" hexmask.long.byte 0x2C 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7" newline hexmask.long.byte 0x2C 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6" newline hexmask.long.byte 0x2C 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5" newline hexmask.long.byte 0x2C 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4" line.long 0x30 "CPSW_NUSS_VBUSP_TX_G_BUF_THRESH_CLR_L_REG,CPSW PFC Global Tx Buffer Threshold Clear Low" hexmask.long.byte 0x30 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3" newline hexmask.long.byte 0x30 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2" newline hexmask.long.byte 0x30 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1" newline hexmask.long.byte 0x30 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0" line.long 0x34 "CPSW_NUSS_VBUSP_TX_G_BUF_THRESH_CLR_H_REG,CPSW PFC Global Tx Buffer Threshold Clear High" hexmask.long.byte 0x34 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7" newline hexmask.long.byte 0x34 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6" newline hexmask.long.byte 0x34 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5" newline hexmask.long.byte 0x34 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4" rgroup.long 0x20050++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_VLAN_LTYPE_REG,VLAN Length/type" hexmask.long.word 0x0 16.--31. 1. "VLAN_LTYPE_OUTER,Outer VLAN LType" newline hexmask.long.word 0x0 0.--15. 1. "VLAN_LTYPE_INNER,Inner VLAN LType" line.long 0x4 "CPSW_NUSS_VBUSP_EST_TS_DOMAIN_REG,Enhanced Scheduled Traffic Host Event Domain" hexmask.long.byte 0x4 0.--7. 1. "EST_TS_DOMAIN,Enhanced Scheduled Traffic Host Event Domain" rgroup.long 0x20100++0x1F line.long 0x0 "CPSW_NUSS_VBUSP_TX_PRI0_MAXLEN_REG,Transmit Priority 0 Maximum Length" hexmask.long.word 0x0 0.--13. 1. "TX_PRI0_MAXLEN,Transmit Priority 0 Maximum Length" line.long 0x4 "CPSW_NUSS_VBUSP_TX_PRI1_MAXLEN_REG,Transmit Priority 1 Maximum Length" hexmask.long.word 0x4 0.--13. 1. "TX_PRI1_MAXLEN,Transmit Priority 1 Maximum Length" line.long 0x8 "CPSW_NUSS_VBUSP_TX_PRI2_MAXLEN_REG,Transmit Priority 2 Maximum Length" hexmask.long.word 0x8 0.--13. 1. "TX_PRI2_MAXLEN,Transmit Priority 2 Maximum Length" line.long 0xC "CPSW_NUSS_VBUSP_TX_PRI3_MAXLEN_REG,Transmit Priority 3 Maximum Length" hexmask.long.word 0xC 0.--13. 1. "TX_PRI3_MAXLEN,Transmit Priority 3 Maximum Length" line.long 0x10 "CPSW_NUSS_VBUSP_TX_PRI4_MAXLEN_REG,Transmit Priority 4 Maximum Length" hexmask.long.word 0x10 0.--13. 1. "TX_PRI4_MAXLEN,Transmit Priority 4 Maximum Length" line.long 0x14 "CPSW_NUSS_VBUSP_TX_PRI5_MAXLEN_REG,Transmit Priority 5 Maximum Length" hexmask.long.word 0x14 0.--13. 1. "TX_PRI5_MAXLEN,Transmit Priority 5 Maximum Length" line.long 0x18 "CPSW_NUSS_VBUSP_TX_PRI6_MAXLEN_REG,Transmit Priority 6 Maximum Length" hexmask.long.word 0x18 0.--13. 1. "TX_PRI6_MAXLEN,Transmit Priority 6 Maximum Length" line.long 0x1C "CPSW_NUSS_VBUSP_TX_PRI7_MAXLEN_REG,Transmit Priority 7 Maximum Length" hexmask.long.word 0x1C 0.--13. 1. "TX_PRI7_MAXLEN,Transmit Priority 7 Maximum Length" rgroup.long 0xF80++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_USER_ACCESS_REG,MDIO User Access Register" bitfld.long 0x0 31. "GO,Go" "0,1" newline bitfld.long 0x0 30. "WRITE,Write" "0,1" newline bitfld.long 0x0 29. "ACK,Acknowledge" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "REGADR,Register address" newline hexmask.long.byte 0x0 16.--20. 1. "PHYADR,PHY address" newline hexmask.long.word 0x0 0.--15. 1. "DATA,User data" line.long 0x4 "CPSW_NUSS_VBUSP_USER_PHY_SEL_REG,MDIO User PHY Select Register" bitfld.long 0x4 7. "LINKSEL,Link status determination select" "0,1" newline bitfld.long 0x4 6. "LINKINT_ENABLE,Link change interrupt enable" "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "PHYADR_MON,PHY address whose link status is monitored" rgroup.long 0x21004++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_P0_CONTROL_REG,CPPI Port 0 Control" bitfld.long 0x0 18. "RX_REMAP_DSCP_V6,Port 0 Remap DSCP_V6 Enable" "0,1" newline bitfld.long 0x0 17. "RX_REMAP_DSCP_V4,Port 0 Remap DSCP_V4 Enable" "0,1" newline bitfld.long 0x0 16. "RX_REMAP_VLAN,Port 0 Remap VLAN Enable" "0,1" newline bitfld.long 0x0 15. "RX_ECC_ERR_EN,Port 0 Receive ECC Error Enable" "0,1" newline bitfld.long 0x0 14. "TX_ECC_ERR_EN,Port 0 Transmit ECC Error Enable" "0,1" newline bitfld.long 0x0 2. "DSCP_IPV6_EN,Port 0 IPv6 DSCP enable" "0,1" newline bitfld.long 0x0 1. "DSCP_IPV4_EN,Port 0 IPv4 DSCP enable" "0,1" newline bitfld.long 0x0 0. "RX_CHECKSUM_EN,Port 0 Receive Checksum Enable" "0,1" line.long 0x4 "CPSW_NUSS_VBUSP_P0_FLOW_ID_OFFSET_REG,CPPI Port 0 Flow ID Offset" hexmask.long.word 0x4 0.--13. 1. "VALUE,This value is added to the thread/Flow_ID in CPPI transmit PSI Info Word 0" rgroup.long 0x21010++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_P0_BLK_CNT_REG,CPPI Port 0 FIFO Block Usage Count" hexmask.long.byte 0x0 8.--12. 1. "TX_BLK_CNT,Port 0 Transmit Block Count Usage" newline hexmask.long.byte 0x0 0.--5. 1. "RX_BLK_CNT,Port 0 Receive Block Count Usage" rgroup.long 0x21014++0x17 line.long 0x0 "CPSW_NUSS_VBUSP_P0_PORT_VLAN_REG,CPPI Port 0 VLAN" bitfld.long 0x0 13.--15. "PORT_PRI,Port VLAN Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12. "PORT_CFI,Port CFI bit" "0,1" newline hexmask.long.word 0x0 0.--11. 1. "PORT_VID,Port VLAN ID" line.long 0x4 "CPSW_NUSS_VBUSP_P0_TX_PRI_MAP_REG,CPPI Port 0 Tx Header Pri to Switch Pri Mapping" bitfld.long 0x4 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7" line.long 0x8 "CPSW_NUSS_VBUSP_P0_PRI_CTL_REG,CPPI Port 0 Priority Control" hexmask.long.byte 0x8 16.--23. 1. "RX_FLOW_PRI,Receive Priority Based Flow Control Enable (per priority)" newline bitfld.long 0x8 8. "RX_PTYPE,Receive Priority Type" "0,1" line.long 0xC "CPSW_NUSS_VBUSP_P0_RX_PRI_MAP_REG,CPPI Port 0 RX Pkt Pri to Header Pri Map" bitfld.long 0xC 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7" line.long 0x10 "CPSW_NUSS_VBUSP_P0_RX_MAXLEN_REG,CPPI Port 0 Receive Frame Max Length" hexmask.long.word 0x10 0.--13. 1. "RX_MAXLEN,Rx Maximum Frame Length" line.long 0x14 "CPSW_NUSS_VBUSP_P0_TX_BLKS_PRI_REG,CPPI Port 0 Transmit Block Sub Per Priority" hexmask.long.byte 0x14 28.--31. 1. "PRI7,Priority 7 Port Transmit Blocks" newline hexmask.long.byte 0x14 24.--27. 1. "PRI6,Priority 6 Port Transmit Blocks" newline hexmask.long.byte 0x14 20.--23. 1. "PRI5,Priority 5 Port Transmit Blocks" newline hexmask.long.byte 0x14 16.--19. 1. "PRI4,Priority 4 Port Transmit Blocks" newline hexmask.long.byte 0x14 12.--15. 1. "PRI3,Priority 3 Port Transmit Blocks" newline hexmask.long.byte 0x14 8.--11. 1. "PRI2,Priority 2 Port Transmit Blocks" newline hexmask.long.byte 0x14 4.--7. 1. "PRI1,Priority 1 Port Transmit Blocks" newline hexmask.long.byte 0x14 0.--3. 1. "PRI0,Priority 0 Port Transmit Blocks" rgroup.long 0x21030++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_P0_IDLE2LPI_REG,Port 0 EEE Idle to LPI counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Port 0 EEE Idle to LPI counter load value" line.long 0x4 "CPSW_NUSS_VBUSP_P0_LPI2WAKE_REG,Port 0 EEE LPI to wake counter" hexmask.long.tbyte 0x4 0.--23. 1. "COUNT,Port 0 EEE LPI to wake counter load value" rgroup.long 0x21038++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_P0_EEE_STATUS_REG,Port 0 EEE status" bitfld.long 0x0 6. "TX_FIFO_EMPTY,CPPI port 0 transmit FIFO (switch egress) is empty - contains no packets" "0,1" newline bitfld.long 0x0 5. "RX_FIFO_EMPTY,CPPI port 0 receive FIFO (switch ingress) is empty - contains no packets" "0,1" newline bitfld.long 0x0 4. "TX_FIFO_HOLD,CPPI port 0 transmit FIFO hold - asserted in the LPI state and during the LPI2WAKE count time" "0,1" newline bitfld.long 0x0 3. "TX_WAKE,CPPI port 0 transmit wakeup - asserted in the transmit LPI2WAKE count time" "0,1" newline bitfld.long 0x0 2. "TX_LPI,CPPI port 0 transmit LPI state - asserted when the port 0 transmit is in the LPI state" "0,1" newline bitfld.long 0x0 1. "RX_LPI,CPPI port 0 receive LPI state - asserted when the port 0 receive is in the LPI state" "0,1" newline bitfld.long 0x0 0. "WAIT_IDLE2LPI,CPPI port 0 wait idle to LPI - asserted when port 0 is counting the IDLE2LPI time" "0,1" rgroup.long 0x2103C++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_P0_RX_PKTS_PRI_REG,CPPI Port Receive Packets per priority" hexmask.long.byte 0x0 28.--31. 1. "PRI7,Priority 7 Port Port 0 Receive Packets" newline hexmask.long.byte 0x0 24.--27. 1. "PRI6,Priority 6 Port Port 0 Receive Packets" newline hexmask.long.byte 0x0 20.--23. 1. "PRI5,Priority 5 Port Port 0 Receive Packets" newline hexmask.long.byte 0x0 16.--19. 1. "PRI4,Priority 4 Port Port 0 Receive Packets" newline hexmask.long.byte 0x0 12.--15. 1. "PRI3,Priority 3 Port Port 0 Receive Packets" newline hexmask.long.byte 0x0 8.--11. 1. "PRI2,Priority 2 Port Port 0 Receive Packets" newline hexmask.long.byte 0x0 4.--7. 1. "PRI1,Priority 1 Port Port 0 Receive Packets" newline hexmask.long.byte 0x0 0.--3. 1. "PRI0,Priority 0 Port Port 0 Receive Packets" rgroup.long 0x2104C++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_P0_RX_GAP_REG,Port 0 Receive Gap Register" hexmask.long.word 0x0 16.--25. 1. "RX_GAP_CNT,Port 0 Receive Gap Count" newline hexmask.long.byte 0x0 0.--7. 1. "RX_GAP_EN,Port 0 Receive Gap Enable" rgroup.long 0x21050++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_P0_FIFO_STATUS_REG,Port 0 FIFO Status" hexmask.long.byte 0x0 0.--7. 1. "TX_PRI_ACTIVE,Port 0 FIFO Status" rgroup.long 0x21120++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_P0_RX_DSCP_MAP_REG,CPPI Port 0 Receive IPV4/IPV6 DSCP Map N" bitfld.long 0x0 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority" "0,1,2,3,4,5,6,7" rgroup.long 0x21140++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_P0_PRI_CIR_REG,CPPI Port 0 Rx Priority P Committed Information Rate" hexmask.long 0x0 0.--27. 1. "PRI_CIR,Priority N CIR" rgroup.long 0x21160++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_P0_PRI_EIR_REG,CPPI Port 0 Rx Priority P Excess Information Rate" hexmask.long 0x0 0.--27. 1. "PRI_EIR,Priority N EIR" rgroup.long 0x21180++0x1F line.long 0x0 "CPSW_NUSS_VBUSP_P0_TX_D_THRESH_SET_L_REG,CPPI Port 0 Tx PFC Destination Threshold Set Low" hexmask.long.byte 0x0 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" newline hexmask.long.byte 0x0 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" newline hexmask.long.byte 0x0 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" newline hexmask.long.byte 0x0 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" line.long 0x4 "CPSW_NUSS_VBUSP_P0_TX_D_THRESH_SET_H_REG,CPPI Port 0 Tx PFC Destination Threshold Set High" hexmask.long.byte 0x4 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" newline hexmask.long.byte 0x4 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" newline hexmask.long.byte 0x4 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" newline hexmask.long.byte 0x4 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" line.long 0x8 "CPSW_NUSS_VBUSP_P0_TX_D_THRESH_CLR_L_REG,CPPI Port 0 Tx PFC Destination Threshold Clr Low" hexmask.long.byte 0x8 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" newline hexmask.long.byte 0x8 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" newline hexmask.long.byte 0x8 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" newline hexmask.long.byte 0x8 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" line.long 0xC "CPSW_NUSS_VBUSP_P0_TX_D_THRESH_CLR_H_REG,CPPI Port 0 Tx PFC Destination Threshold Clr High" hexmask.long.byte 0xC 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" newline hexmask.long.byte 0xC 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" newline hexmask.long.byte 0xC 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" newline hexmask.long.byte 0xC 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" line.long 0x10 "CPSW_NUSS_VBUSP_P0_TX_G_BUF_THRESH_SET_L_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Set Low" hexmask.long.byte 0x10 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" newline hexmask.long.byte 0x10 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" newline hexmask.long.byte 0x10 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" newline hexmask.long.byte 0x10 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" line.long 0x14 "CPSW_NUSS_VBUSP_P0_TX_G_BUF_THRESH_SET_H_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Set High" hexmask.long.byte 0x14 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" newline hexmask.long.byte 0x14 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" newline hexmask.long.byte 0x14 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" newline hexmask.long.byte 0x14 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" line.long 0x18 "CPSW_NUSS_VBUSP_P0_TX_G_BUF_THRESH_CLR_L_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Clr Low" hexmask.long.byte 0x18 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" newline hexmask.long.byte 0x18 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" newline hexmask.long.byte 0x18 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" newline hexmask.long.byte 0x18 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" line.long 0x1C "CPSW_NUSS_VBUSP_P0_TX_G_BUF_THRESH_CLR_H_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Clr High" hexmask.long.byte 0x1C 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" newline hexmask.long.byte 0x1C 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" newline hexmask.long.byte 0x1C 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" newline hexmask.long.byte 0x1C 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" rgroup.long 0x21300++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_P0_SRC_ID_A_REG,CPPI Port 0 CPPI Source ID A" hexmask.long.byte 0x0 24.--31. 1. "PORT4,Port 4 CPPI Info Word0 Source ID Value" newline hexmask.long.byte 0x0 16.--23. 1. "PORT3,Port 3 CPPI Info Word0 Source ID Value" newline hexmask.long.byte 0x0 8.--15. 1. "PORT2,Port 2 CPPI Info Word0 Source ID Value" newline hexmask.long.byte 0x0 0.--7. 1. "PORT1,Port 1 CPPI Info Word0 Source ID Value" line.long 0x4 "CPSW_NUSS_VBUSP_P0_SRC_ID_B_REG,CPPI Port 0 CPPI Source ID B" hexmask.long.byte 0x4 24.--31. 1. "PORT8,Port 8 CPPI Info Word0 Source ID Value" newline hexmask.long.byte 0x4 16.--23. 1. "PORT7,Port 7 CPPI Info Word0 Source ID Value" newline hexmask.long.byte 0x4 8.--15. 1. "PORT6,Port 6 CPPI Info Word0 Source ID Value" newline hexmask.long.byte 0x4 0.--7. 1. "PORT5,Port 5 CPPI Info Word0 Source ID Value" rgroup.long 0x21320++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_P0_HOST_BLKS_PRI_REG,CPPI Port 0 Host Blocks Priority" hexmask.long.byte 0x0 28.--31. 1. "PRI7,Priority 7 Host Blocks" newline hexmask.long.byte 0x0 24.--27. 1. "PRI6,Priority 6 Host Blocks" newline hexmask.long.byte 0x0 20.--23. 1. "PRI5,Priority 5 Host Blocks" newline hexmask.long.byte 0x0 16.--19. 1. "PRI4,Priority 4 Host Blocks" newline hexmask.long.byte 0x0 12.--15. 1. "PRI3,Priority 3 Host Blocks" newline hexmask.long.byte 0x0 8.--11. 1. "PRI2,Priority 2 Host Blocks" newline hexmask.long.byte 0x0 4.--7. 1. "PRI1,Priority 1 Host Blocks" newline hexmask.long.byte 0x0 0.--3. 1. "PRI0,Priority 0 Host Blocks" rgroup.long 0x22000++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_PN_RESERVED_REG,Reserved" hexmask.long 0x0 0.--31. 1. "RESERVED,Reserved register for memory map alignment" rgroup.long 0x22004++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_PN_CONTROL_REG,Enet Port N Control" bitfld.long 0x0 17. "EST_PORT_EN,EST Port Enable" "0,1" newline bitfld.long 0x0 16. "IET_PORT_EN,IET Port Enable" "0,1" newline bitfld.long 0x0 15. "RX_ECC_ERR_EN,Port 0 Receive ECC Error Enable" "0,1" newline bitfld.long 0x0 14. "TX_ECC_ERR_EN,Port 0 Transmit ECC Error Enable" "0,1" newline bitfld.long 0x0 12. "TX_LPI_CLKSTOP_EN,Transmit LPI clockstop enable" "0,1" newline bitfld.long 0x0 2. "DSCP_IPV6_EN,IPv6 DSCP enable" "0,1" newline bitfld.long 0x0 1. "DSCP_IPV4_EN,IPv4 DSCP enable" "0,1" line.long 0x4 "CPSW_NUSS_VBUSP_PN_MAX_BLKS_REG,Enet Port N FIFO Max Blocks" hexmask.long.byte 0x4 8.--15. 1. "TX_MAX_BLKS,Transmit FIFO maximum blocks" newline hexmask.long.byte 0x4 0.--7. 1. "RX_MAX_BLKS,Receive FIFO maximum blocks" rgroup.long 0x22010++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_PN_BLK_CNT_REG,Enet Port N FIFO Block Usage Count" hexmask.long.byte 0x0 16.--21. 1. "RX_BLK_CNT_P,Receive Prempt Queue Block Count Usage" newline hexmask.long.byte 0x0 8.--12. 1. "TX_BLK_CNT,Transmit Block Count Usage" newline hexmask.long.byte 0x0 0.--5. 1. "RX_BLK_CNT_E,Receive Block Count Usage" rgroup.long 0x22014++0x23 line.long 0x0 "CPSW_NUSS_VBUSP_PN_PORT_VLAN_REG,Enet Port N VLAN" bitfld.long 0x0 13.--15. "PORT_PRI,Port VLAN Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12. "PORT_CFI,Port CFI bit" "0,1" newline hexmask.long.word 0x0 0.--11. 1. "PORT_VID,Port VLAN ID" line.long 0x4 "CPSW_NUSS_VBUSP_PN_TX_PRI_MAP_REG,Enet Port N Tx Header Pri to Switch Pri Mapping" bitfld.long 0x4 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7" line.long 0x8 "CPSW_NUSS_VBUSP_PN_PRI_CTL_REG,Enet Port N Priority Control" hexmask.long.byte 0x8 24.--31. 1. "TX_FLOW_PRI,Transmit Priority Based Flow Control Enable (per priority)" newline hexmask.long.byte 0x8 16.--23. 1. "RX_FLOW_PRI,Receive Priority Based Flow Control Enable (per priority)" newline hexmask.long.byte 0x8 12.--15. 1. "TX_HOST_BLKS_REM,Transmit FIFO Blocks that must be free before a non rate-limited CPPI Port 0 receive thread can begin sending a packet" line.long 0xC "CPSW_NUSS_VBUSP_PN_RX_PRI_MAP_REG,Enet Port N RX Pkt Pri to Header Pri Map" bitfld.long 0xC 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7" line.long 0x10 "CPSW_NUSS_VBUSP_PN_RX_MAXLEN_REG,Enet Port N Receive Frame Max Length" hexmask.long.word 0x10 0.--13. 1. "RX_MAXLEN,Rx Maximum Frame Length" line.long 0x14 "CPSW_NUSS_VBUSP_PN_TX_BLKS_PRI_REG,Enet Port N Transmit Block Sub Per Priority" hexmask.long.byte 0x14 28.--31. 1. "PRI7,Priority 7 Port Transmit Blocks" newline hexmask.long.byte 0x14 24.--27. 1. "PRI6,Priority 6 Port Transmit Blocks" newline hexmask.long.byte 0x14 20.--23. 1. "PRI5,Priority 5 Port Transmit Blocks" newline hexmask.long.byte 0x14 16.--19. 1. "PRI4,Priority 4 Port Transmit Blocks" newline hexmask.long.byte 0x14 12.--15. 1. "PRI3,Priority 3 Port Transmit Blocks" newline hexmask.long.byte 0x14 8.--11. 1. "PRI2,Priority 2 Port Transmit Blocks" newline hexmask.long.byte 0x14 4.--7. 1. "PRI1,Priority 1 Port Transmit Blocks" newline hexmask.long.byte 0x14 0.--3. 1. "PRI0,Priority 0 Port Transmit Blocks" line.long 0x18 "CPSW_NUSS_VBUSP_PN_RX_FLOW_THRESH_REG,Enet MAC Receive Flow Threshold in Receive Buffer Words" hexmask.long.word 0x18 0.--8. 1. "COUNT,Receive Flow Threshold in Words" line.long 0x1C "CPSW_NUSS_VBUSP_PN_IDLE2LPI_REG,Enet Port N EEE Idle to LPI counter" hexmask.long.tbyte 0x1C 0.--23. 1. "COUNT,EEE Idle to LPI counter load value" line.long 0x20 "CPSW_NUSS_VBUSP_PN_LPI2WAKE_REG,Enet Port N EEE LPI to wake counter" hexmask.long.tbyte 0x20 0.--23. 1. "COUNT,EEE LPI to wake counter load value" rgroup.long 0x22038++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_PN_EEE_STATUS_REG,Enet Port N EEE status" bitfld.long 0x0 6. "TX_FIFO_EMPTY,Transmit FIFO (switch egress) is empty - contains no packets" "0,1" newline bitfld.long 0x0 5. "RX_FIFO_EMPTY,Receive FIFO (switch ingress) is empty - contains no packets" "0,1" newline bitfld.long 0x0 4. "TX_FIFO_HOLD,Transmit FIFO hold - asserted in the LPI state and during the LPI2WAKE count time" "0,1" newline bitfld.long 0x0 3. "TX_WAKE,Transmit wakeup - asserted in the transmit LPI2WAKE count time" "0,1" newline bitfld.long 0x0 2. "TX_LPI,Transmit LPI state - asserted when the port 0 transmit is in the LPI state" "0,1" newline bitfld.long 0x0 1. "RX_LPI,Receive LPI state - asserted when the port 0 receive is in the LPI state" "0,1" newline bitfld.long 0x0 0. "WAIT_IDLE2LPI,CPPI port 0 wait idle to LPI - asserted when port 0 is counting the IDLE2LPI time" "0,1" rgroup.long 0x22040++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_PN_IET_CONTROL_REG,Enet Port N IET Control" hexmask.long.byte 0x0 16.--23. 1. "MAC_PREMPT,IET MAC Fragment Size" newline bitfld.long 0x0 8.--10. "MAC_ADDFRAGSIZE,IET MAC Fragment Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "MAC_LINKFAIL,IET MAC LINK Fail Reset" "0,1" newline bitfld.long 0x0 2. "MAC_DISABLEVERIFY,IET MAC Disable Verify" "0,1" newline bitfld.long 0x0 1. "MAC_HOLD,IET MAC HOLD" "0,1" newline bitfld.long 0x0 0. "MAC_PENABLE,IET MAC Penable" "0,1" rgroup.long 0x22044++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_PN_IET_STATUS_REG,Enet Port N IET Status" bitfld.long 0x0 3. "MAC_VERIFY_ERR,IET MAC VERIFY ERROR" "0,1" newline bitfld.long 0x0 2. "MAC_RESPOND_ERR,IET MAC RESPONSE ERROR" "0,1" newline bitfld.long 0x0 1. "MAC_VERIFY_FAIL,IET MAC VERIFY FAIL" "0,1" newline bitfld.long 0x0 0. "MAC_VERIFIED,IET MAC VERIFIED" "0,1" rgroup.long 0x22048++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_PN_IET_VERIFY_REG,Enet Port N IET VERIFY" hexmask.long.tbyte 0x0 0.--23. 1. "MAC_VERIFY_CNT,IET MAC VERIFY COUNT" rgroup.long 0x22050++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_PN_FIFO_STATUS_REG,Enet Port N FIFO STATUS" bitfld.long 0x0 18. "EST_BUFACT,Transmit FIFO EST Buffer Active" "0,1" newline bitfld.long 0x0 17. "EST_ADD_ERR,Transmit FIFO EST Address Error" "0,1" newline bitfld.long 0x0 16. "EST_CNT_ERR,Transmit FIFO EST Count Error" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "TX_E_MAC_ALLOW,Transmit FIFO Express Queue Priority Allow" newline hexmask.long.byte 0x0 0.--7. 1. "TX_PRI_ACTIVE,Transmit FIFO Priority Active" rgroup.long 0x22060++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_PN_EST_CONTROL_REG,Enet Port N EST CONTROL" hexmask.long.word 0x0 16.--25. 1. "EST_FILL_MARGIN,Transmit FIFO EST Fill Margin" newline hexmask.long.byte 0x0 9.--15. 1. "EST_PREMPT_COMP,Transmit FIFO EST Prempt Comparision Value" newline bitfld.long 0x0 8. "EST_FILL_EN,Transmit FIFO EST Fill Enable" "0,1" newline bitfld.long 0x0 5.--7. "EST_TS_PRI,Transmit FIFO EST TimeStamp Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "EST_TS_ONEPRI,Transmit FIFO EST TimeStamp One Priority" "0,1" newline bitfld.long 0x0 3. "EST_TS_FIRST,Transmit FIFO EST TimeStamp First Express Packet" "0,1" newline bitfld.long 0x0 2. "EST_TS_EN,Transmit FIFO EST TimeStamp Enable" "0,1" newline bitfld.long 0x0 1. "EST_BUFSEL,Transmit FIFO EST Buffer Select" "0,1" newline bitfld.long 0x0 0. "EST_ONEBUF,Transmit FIFO EST One Buffer" "0,1" rgroup.long 0x22120++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_PN_RX_DSCP_MAP_REG,Enet Port N Receive IPV4/IPV6 DSCP Map M" bitfld.long 0x0 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority" "0,1,2,3,4,5,6,7" rgroup.long 0x22140++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_PN_PRI_CIR_REG,Enet Port N Rx Priority P Committed Information Rate Value" hexmask.long 0x0 0.--27. 1. "PRI_CIR,Priority N committed information rate" rgroup.long 0x22160++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_PN_PRI_EIR_REG,Enet Port N Rx Priority P Excess Informatoin Rate Value" hexmask.long 0x0 0.--27. 1. "PRI_EIR,Priority N Excess Information Rate count" rgroup.long 0x22180++0x1F line.long 0x0 "CPSW_NUSS_VBUSP_PN_TX_D_THRESH_SET_L_REG,Enet Port N Tx PFC Destination Threshold Set Low" hexmask.long.byte 0x0 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" newline hexmask.long.byte 0x0 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" newline hexmask.long.byte 0x0 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" newline hexmask.long.byte 0x0 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" line.long 0x4 "CPSW_NUSS_VBUSP_PN_TX_D_THRESH_SET_H_REG,Enet Port N Tx PFC Destination Threshold Set High" hexmask.long.byte 0x4 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" newline hexmask.long.byte 0x4 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" newline hexmask.long.byte 0x4 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" newline hexmask.long.byte 0x4 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" line.long 0x8 "CPSW_NUSS_VBUSP_PN_TX_D_THRESH_CLR_L_REG,Enet Port N Tx PFC Destination Threshold Clr Low" hexmask.long.byte 0x8 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" newline hexmask.long.byte 0x8 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" newline hexmask.long.byte 0x8 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" newline hexmask.long.byte 0x8 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" line.long 0xC "CPSW_NUSS_VBUSP_PN_TX_D_THRESH_CLR_H_REG,Enet Port N Tx PFC Destination Threshold Clr High" hexmask.long.byte 0xC 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" newline hexmask.long.byte 0xC 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" newline hexmask.long.byte 0xC 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" newline hexmask.long.byte 0xC 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" line.long 0x10 "CPSW_NUSS_VBUSP_PN_TX_G_BUF_THRESH_SET_L_REG,Enet Port N Tx PFC Global Buffer Threshold Set Low" hexmask.long.byte 0x10 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" newline hexmask.long.byte 0x10 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" newline hexmask.long.byte 0x10 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" newline hexmask.long.byte 0x10 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" line.long 0x14 "CPSW_NUSS_VBUSP_PN_TX_G_BUF_THRESH_SET_H_REG,Enet Port N Tx PFC Global Buffer Threshold Set High" hexmask.long.byte 0x14 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" newline hexmask.long.byte 0x14 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" newline hexmask.long.byte 0x14 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" newline hexmask.long.byte 0x14 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" line.long 0x18 "CPSW_NUSS_VBUSP_PN_TX_G_BUF_THRESH_CLR_L_REG,Enet Port N Tx PFC Global Buffer Threshold Clr Low" hexmask.long.byte 0x18 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" newline hexmask.long.byte 0x18 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" newline hexmask.long.byte 0x18 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" newline hexmask.long.byte 0x18 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" line.long 0x1C "CPSW_NUSS_VBUSP_PN_TX_G_BUF_THRESH_CLR_H_REG,Enet Port N Tx PFC Global Buffer Threshold Clr High" hexmask.long.byte 0x1C 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" newline hexmask.long.byte 0x1C 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" newline hexmask.long.byte 0x1C 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" newline hexmask.long.byte 0x1C 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" rgroup.long 0x22300++0x23 line.long 0x0 "CPSW_NUSS_VBUSP_PN_TX_D_OFLOW_ADDVAL_L_REG,Enet Port N Tx Destination Out Flow Add Values Low" hexmask.long.byte 0x0 24.--28. 1. "PRI3,Port PFC Destination Based Out Flow Add Value for Priority 3" newline hexmask.long.byte 0x0 16.--20. 1. "PRI2,Port PFC Destination Based Out Flow Add Value for Priority 2" newline hexmask.long.byte 0x0 8.--12. 1. "PRI1,Port PFC Destination Based Out Flow Add Value for Priority 1" newline hexmask.long.byte 0x0 0.--4. 1. "PRI0,Port PFC Destination Based Out Flow Add Value for Priority 0" line.long 0x4 "CPSW_NUSS_VBUSP_PN_TX_D_OFLOW_ADDVAL_H_REG,Enet Port N Tx Destination Out Flow Add Values High" hexmask.long.byte 0x4 24.--28. 1. "PRI7,Port PFC Destination Based Out Flow Add Value for Priority 7" newline hexmask.long.byte 0x4 16.--20. 1. "PRI6,Port PFC Destination Based Out Flow Add Value for Priority 6" newline hexmask.long.byte 0x4 8.--12. 1. "PRI5,Port PFC Destination Based Out Flow Add Value for Priority 5" newline hexmask.long.byte 0x4 0.--4. 1. "PRI4,Port PFC Destination Based Out Flow Add Value for Priority 4" line.long 0x8 "CPSW_NUSS_VBUSP_PN_SA_L_REG,Enet Port N Tx Pause Frame Source Address Low" hexmask.long.byte 0x8 8.--15. 1. "MACSRCADDR_7_0,Source Address Lower 8 bits" newline hexmask.long.byte 0x8 0.--7. 1. "MACSRCADDR_15_8,Source Address bits 15:8" line.long 0xC "CPSW_NUSS_VBUSP_PN_SA_H_REG,Enet Port N Tx Pause Frame Source Address High" hexmask.long.byte 0xC 24.--31. 1. "MACSRCADDR_23_16,Source Address bits 23:16" newline hexmask.long.byte 0xC 16.--23. 1. "MACSRCADDR_31_24,Source Address bits 31:24" newline hexmask.long.byte 0xC 8.--15. 1. "MACSRCADDR_39_32,Source Address bits 39:32" newline hexmask.long.byte 0xC 0.--7. 1. "MACSRCADDR_47_40,Source Address bits 47:40" line.long 0x10 "CPSW_NUSS_VBUSP_PN_TS_CTL_REG,Enet Port N Time Sync Control" hexmask.long.word 0x10 16.--31. 1. "TS_MSG_TYPE_EN,Time Sync Message Type Enable" newline bitfld.long 0x10 11. "TS_TX_HOST_TS_EN,Time Sync Transmit Host Time Stamp Enable" "0,1" newline bitfld.long 0x10 10. "TS_TX_ANNEX_E_EN,Time Synce Transmit Annex E Enable" "0,1" newline bitfld.long 0x10 9. "TS_RX_ANNEX_E_EN,Time Synce Receive Annex E Enable" "0,1" newline bitfld.long 0x10 8. "TS_LTYPE2_EN,Time Sync LTYPE 2 enable transmit and receive" "0,1" newline bitfld.long 0x10 7. "TS_TX_ANNEX_D_EN,Time Synce Transmit Annex D Enable" "0,1" newline bitfld.long 0x10 6. "TS_TX_VLAN_LTYPE2_EN,Time Sync Transmit VLAN LTYPE 2 enable" "0,1" newline bitfld.long 0x10 5. "TS_TX_VLAN_LTYPE1_EN,Time Sync Transmit VLAN LTYPE 1 enable" "0,1" newline bitfld.long 0x10 4. "TS_TX_ANNEX_F_EN,Time Synce Transmit Annex F Enable" "0,1" newline bitfld.long 0x10 3. "TS_RX_ANNEX_D_EN,Time Synce Receive Annex D Enable" "0,1" newline bitfld.long 0x10 2. "TS_RX_VLAN_LTYPE2_EN,Time Sync Receive VLAN LTYPE 2 enable" "0,1" newline bitfld.long 0x10 1. "TS_RX_VLAN_LTYPE1_EN,Time Sync Receive VLAN LTYPE 1 enable" "0,1" newline bitfld.long 0x10 0. "TS_RX_ANNEX_F_EN,Time Synce Receive Annex F Enable" "0,1" line.long 0x14 "CPSW_NUSS_VBUSP_PN_TS_SEQ_LTYPE_REG,Enet Port N Time Sync LTYPE (and SEQ_ID_OFFSET)" hexmask.long.byte 0x14 16.--21. 1. "TS_SEQ_ID_OFFSET,Time Sync Sequence ID Offset" newline hexmask.long.word 0x14 0.--15. 1. "TS_LTYPE1,Time Sync LTYPE1" line.long 0x18 "CPSW_NUSS_VBUSP_PN_TS_VLAN_LTYPE_REG,Enet Port N Time Sync VLAN2 and VLAN2" hexmask.long.word 0x18 16.--31. 1. "TS_VLAN_LTYPE2,Time Sync VLAN LTYPE2" newline hexmask.long.word 0x18 0.--15. 1. "TS_VLAN_LTYPE1,Time Sync VLAN LTYPE1" line.long 0x1C "CPSW_NUSS_VBUSP_PN_TS_CTL_LTYPE2_REG,Enet Port N Time Sync Control and LTYPE 2" bitfld.long 0x1C 24. "TS_UNI_EN,Time Sync Unicast Enable" "0,1" newline bitfld.long 0x1C 23. "TS_TTL_NONZERO,Time Sync Time to Live Non-zero Enable" "0,1" newline bitfld.long 0x1C 22. "TS_320,Time Sync Destination IP Address 320 Enable" "0,1" newline bitfld.long 0x1C 21. "TS_319,Time Sync Destination IP Address 319 Enable" "0,1" newline bitfld.long 0x1C 20. "TS_132,Time Sync Destination IP Address 132 Enable" "0,1" newline bitfld.long 0x1C 19. "TS_131,Time Sync Destination IP Address 131 Enable" "0,1" newline bitfld.long 0x1C 18. "TS_130,Time Sync Destination IP Address 130 Enable" "0,1" newline bitfld.long 0x1C 17. "TS_129,Time Sync Destination IP Address 129 Enable" "0,1" newline bitfld.long 0x1C 16. "TS_107,Time Sync Destination IP Address 107 Enable" "0,1" newline hexmask.long.word 0x1C 0.--15. 1. "TS_LTYPE2,Time Sync LTYPE2" line.long 0x20 "CPSW_NUSS_VBUSP_PN_TS_CTL2_REG,Enet Port N Time Sync Control 2" hexmask.long.byte 0x20 16.--21. 1. "TS_DOMAIN_OFFSET,Time Sync Domain Offset" newline hexmask.long.word 0x20 0.--15. 1. "TS_MCAST_TYPE_EN,Time Sync Multicast Destination Address Type Enable" rgroup.long 0x22330++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_PN_MAC_CONTROL_REG,Enet Port N Mac Control" bitfld.long 0x0 24. "RX_CMF_EN,RX Copy MAC Control Frames Enable" "0,1" newline bitfld.long 0x0 23. "RX_CSF_EN,RX Copy Short Frames Enable" "0,1" newline bitfld.long 0x0 22. "RX_CEF_EN,RX Copy Error Frames Enable" "0,1" newline bitfld.long 0x0 21. "TX_SHORT_GAP_LIM_EN,Transmit Short Gap Limit Enable" "0,1" newline bitfld.long 0x0 20. "EXT_TX_FLOW_EN,External Transmit Flow Control Enable" "0,1" newline bitfld.long 0x0 19. "EXT_RX_FLOW_EN,External Receive Flow Control Enable" "0,1" newline bitfld.long 0x0 18. "CTL_EN,Control Enable" "0,1" newline bitfld.long 0x0 17. "GIG_FORCE,Gigabit Mode Force" "0,1" newline bitfld.long 0x0 16. "IFCTL_B,Interface Control B" "0,1" newline bitfld.long 0x0 15. "IFCTL_A,Interface Control A" "0,1" newline bitfld.long 0x0 12. "CRC_TYPE,Port CRC Type" "0,1" newline bitfld.long 0x0 11. "CMD_IDLE,Command Idle" "0,1" newline bitfld.long 0x0 10. "TX_SHORT_GAP_ENABLE,Transmit Short Gap Enable" "0,1" newline bitfld.long 0x0 7. "GIG,Gigabit Mode" "0,1" newline bitfld.long 0x0 6. "TX_PACE,Transmit Pacing Enable" "0,1" newline bitfld.long 0x0 5. "GMII_EN,GMII Enable" "0,1" newline bitfld.long 0x0 4. "TX_FLOW_EN,Transmit Flow Control Enable" "0,1" newline bitfld.long 0x0 3. "RX_FLOW_EN,Receive Flow Control Enable" "0,1" newline bitfld.long 0x0 2. "MTEST,Manufacturing Test Mode" "0,1" newline bitfld.long 0x0 1. "LOOPBACK,Loop Back Mode" "0,1" newline bitfld.long 0x0 0. "FULLDUPLEX,Full Duplex mode" "0,1" rgroup.long 0x22334++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_PN_MAC_STATUS_REG,Enet Port N Mac Status" bitfld.long 0x0 31. "IDLE,cpxmac_sl IDLE" "0,1" newline bitfld.long 0x0 30. "E_IDLE,cpxmac_sl IDLE" "0,1" newline bitfld.long 0x0 29. "P_IDLE,cpxmac_sl IDLE" "0,1" newline bitfld.long 0x0 28. "TX_IDLE,cpxmac_sl IDLE" "0,1" newline bitfld.long 0x0 27. "TORF,Top of receive FIFO flow control trigger occurred. This bit is write one to clear." "0,1" newline bitfld.long 0x0 24.--26. "TORF_PRI,The lowest priority that caused top of receive FIFO flow control trigger since the last write to clear. This field is write 0x7 to clear." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--23. 1. "TX_PFC_FLOW_ACT,Transmit Priority Based Flow Control Active (priority 7 down to 0)" newline hexmask.long.byte 0x0 8.--15. 1. "RX_PFC_FLOW_ACT,Receive Priority Based Flow Control Active (priority 7 down to 0)" newline bitfld.long 0x0 6. "EXT_RX_FLOW_EN,External Transmit Flow Control Enable" "0,1" newline bitfld.long 0x0 5. "EXT_TX_FLOW_EN,External Receive Flow Control Enable" "0,1" newline bitfld.long 0x0 4. "EXT_GIG,External GIG mode" "0,1" newline bitfld.long 0x0 3. "EXT_FULLDUPLEX,External Fullduplex" "0,1" newline bitfld.long 0x0 1. "RX_FLOW_ACT,Receive Flow Control Active" "0,1" newline bitfld.long 0x0 0. "TX_FLOW_ACT,Transmit Flow Control Active" "0,1" rgroup.long 0x22338++0xB line.long 0x0 "CPSW_NUSS_VBUSP_PN_MAC_SOFT_RESET_REG,Enet Port N Mac Soft Reset" bitfld.long 0x0 0. "SOFT_RESET,Software reset" "0,1" line.long 0x4 "CPSW_NUSS_VBUSP_PN_MAC_BOFFTEST_REG,Enet Port N Mac Backoff Test" hexmask.long.byte 0x4 26.--30. 1. "PACEVAL,Pacing Register Current Value" newline hexmask.long.word 0x4 16.--25. 1. "RNDNUM,Backoff Random Number Generator" newline hexmask.long.byte 0x4 12.--15. 1. "COLL_COUNT,Collision Count" newline hexmask.long.word 0x4 0.--9. 1. "TX_BACKOFF,Backoff Count" line.long 0x8 "CPSW_NUSS_VBUSP_PN_MAC_RX_PAUSETIMER_REG,Enet Port N 802.3 Receive Pause Timer" hexmask.long.word 0x8 0.--15. 1. "RX_PAUSETIMER,RX Pause Timer Value" rgroup.long 0x22350++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_PN_MAC_RXN_PAUSETIMER_REG,Enet Port N PFC Priority P Rx Pause Timer" hexmask.long.word 0x0 0.--15. 1. "RX_PAUSETIMER,RX Pause Timer Value" rgroup.long 0x22370++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_PN_MAC_TX_PAUSETIMER_REG,Enet Port N 802.3 Tx Pause Timer" hexmask.long.word 0x0 0.--15. 1. "TX_PAUSETIMER,TX Pause Timer Value" rgroup.long 0x22380++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_PN_MAC_TXN_PAUSETIMER_REG,Enet Port N PFC Priority P Tx Pause Timer" hexmask.long.word 0x0 0.--15. 1. "TX_PAUSETIMER,TX Pause Timer Value" rgroup.long 0x223A0++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_PN_MAC_EMCONTROL_REG,Enet Port N Emulation Control" bitfld.long 0x0 1. "SOFT,Emulation Soft Bit" "0,1" newline bitfld.long 0x0 0. "FREE,Emulation Free Bit" "0,1" line.long 0x4 "CPSW_NUSS_VBUSP_PN_MAC_TX_GAP_REG,Enet Port N Tx Inter Packet Gap" hexmask.long.word 0x4 0.--15. 1. "TX_GAP,Transmit Inter-Packet Gap" rgroup.long 0x223A8++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_PN_MAC_PORT_CONFIG,Enet Port N Port Configuration" bitfld.long 0x0 9. "IET,IET support" "0,1" newline bitfld.long 0x0 8. "XGMII,XGMII support" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "INTERVLAN_ROUTES,The number of InterVLAN routes" rgroup.long 0x223AC++0x13 line.long 0x0 "CPSW_NUSS_VBUSP_PN_INTERVLAN_OPX_POINTER_REG,Enet Port N Tx Egress InterVLAN Operation Pointer" bitfld.long 0x0 0.--2. "POINTER,InterVLAN location pointer: This field points to the InterVLAN location that will be read/written by accesses to Enet_Pn_InterVLANx_A/B." "0,1,2,3,4,5,6,7" line.long 0x4 "CPSW_NUSS_VBUSP_PN_INTERVLAN_OPX_A_REG,Enet Port N Tx Egress InterVLAN A" hexmask.long.byte 0x4 24.--31. 1. "DA_23_16,Destination Address bits 23:16" newline hexmask.long.byte 0x4 16.--23. 1. "DA_31_24,Destination Address bits 31:24" newline hexmask.long.byte 0x4 8.--15. 1. "DA_39_32,Destination Address bits 39:32" newline hexmask.long.byte 0x4 0.--7. 1. "DA_47_40,Destination Address bits 47:40" line.long 0x8 "CPSW_NUSS_VBUSP_PN_INTERVLAN_OPX_B_REG,Enet Port N Tx Egress InterVLAN B" hexmask.long.byte 0x8 24.--31. 1. "SA_39_32,Source Address bits 39:32" newline hexmask.long.byte 0x8 16.--23. 1. "SA_47_40,Source Address bits 47:40" newline hexmask.long.byte 0x8 8.--15. 1. "DA_7_0,Destination Address bits 7:0" newline hexmask.long.byte 0x8 0.--7. 1. "DA_15_8,Destination Address bits 15:8" line.long 0xC "CPSW_NUSS_VBUSP_PN_INTERVLAN_OPX_C_REG,Enet Port N Tx Egress InterVLAN C" hexmask.long.byte 0xC 24.--31. 1. "SA_7_0,Source Address bits 7:0" newline hexmask.long.byte 0xC 16.--23. 1. "SA_15_8,Source Address bits 15:8" newline hexmask.long.byte 0xC 8.--15. 1. "SA_23_16,Source Address bits 23:16" newline hexmask.long.byte 0xC 0.--7. 1. "SA_31_24,Source Address bits 31:24" line.long 0x10 "CPSW_NUSS_VBUSP_PN_INTERVLAN_OPX_D_REG,Enet Port N Tx Egress InterVLAN D" bitfld.long 0x10 15. "DECREMENT_TTL,Decrement Time To Live: When set the Time To Live (TTL) field in the header is decremented." "0,1" newline bitfld.long 0x10 14. "DEST_FORCE_UNTAGGED_EGRESS,Destination VLAN Force Untagged Egress: When set this bit indicates that the VLAN should be removed on egress for the routed packet." "0,1" newline bitfld.long 0x10 13. "REPLACE_DA_SA,Replace Destination Address and Source Address: When set this bit indicates that the routed packet destination address should be replaced by da[47:0] and the source address should be replaced by sa[47:0]." "0,1" newline bitfld.long 0x10 12. "REPLACE_VID,Replace VLAN ID: When set this bit indicates that the VLAN ID should be replaced for the routed packet." "0,1" newline hexmask.long.word 0x10 0.--11. 1. "VID,VLAN ID" rgroup.long 0x32000++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_FETCH_LOC,These are the RAM locations for one ethernet port" hexmask.long.tbyte 0x0 0.--21. 1. "LOC,RAM Location" rgroup.long 0x3A000++0xB line.long 0x0 "CPSW_NUSS_VBUSP_RXGOODFRAMES,Total number of good frames received" hexmask.long 0x0 0.--31. 1. "COUNT,Total number of good frames received" line.long 0x4 "CPSW_NUSS_VBUSP_RXBROADCASTFRAMES,Total number of good broadcast frames received" hexmask.long 0x4 0.--31. 1. "COUNT,Total number of good broadcast frames received" line.long 0x8 "CPSW_NUSS_VBUSP_RXMULTICASTFRAMES,Total number of good multicast frames received" hexmask.long 0x8 0.--31. 1. "COUNT,Total number of good multicast frames received" rgroup.long 0x3A010++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_RXCRCERRORS,Total number of CRC errors frames received" hexmask.long 0x0 0.--31. 1. "COUNT,Total number of CRC errors frames received" rgroup.long 0x3A018++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_RXOVERSIZEDFRAMES,Total number of oversized frames received" hexmask.long 0x0 0.--31. 1. "COUNT,Total number of oversized frames received" rgroup.long 0x3A020++0x1F line.long 0x0 "CPSW_NUSS_VBUSP_RXUNDERSIZEDFRAMES,Total number of undersized frames received" hexmask.long 0x0 0.--31. 1. "COUNT,Total number of undersized frames received" line.long 0x4 "CPSW_NUSS_VBUSP_RXFRAGMENTS,Total number of fragmented frames received" hexmask.long 0x4 0.--31. 1. "COUNT,Total number of fragmented frames received" line.long 0x8 "CPSW_NUSS_VBUSP_ALE_DROP,Total number of frames dropped by the ALE" hexmask.long 0x8 0.--31. 1. "COUNT,Total number of frames dropped by the ALE" line.long 0xC "CPSW_NUSS_VBUSP_ALE_OVERRUN_DROP,Total number of overrun frames dropped by the ALE" hexmask.long 0xC 0.--31. 1. "COUNT,Total number of overrun frames dropped by the ALE" line.long 0x10 "CPSW_NUSS_VBUSP_RXOCTETS,Total number of received bytes in good frames" hexmask.long 0x10 0.--31. 1. "COUNT,Total number of received bytes in good frames" line.long 0x14 "CPSW_NUSS_VBUSP_TXGOODFRAMES,Total number of good frames transmitted" hexmask.long 0x14 0.--31. 1. "COUNT,Total number of good frames transmitted" line.long 0x18 "CPSW_NUSS_VBUSP_TXBROADCASTFRAMES,Total number of good broadcast frames transmitted" hexmask.long 0x18 0.--31. 1. "COUNT,Total number of good broadcast frames transmitted" line.long 0x1C "CPSW_NUSS_VBUSP_TXMULTICASTFRAMES,Total number of good multicast frames transmitted" hexmask.long 0x1C 0.--31. 1. "COUNT,Total number of good multicast frames transmitted" rgroup.long 0x3A064++0x7B line.long 0x0 "CPSW_NUSS_VBUSP_TXOCTETS,Total number of bytes in all good frames transmitted" hexmask.long 0x0 0.--31. 1. "COUNT,Total number of bytes in all good frames transmitted" line.long 0x4 "CPSW_NUSS_VBUSP_OCTETFRAMES64,Total number of 64-byte frames received and transmitted" hexmask.long 0x4 0.--31. 1. "COUNT,Total number of 64-byte frames received and transmitted" line.long 0x8 "CPSW_NUSS_VBUSP_OCTETFRAMES65T127,Total number of frames of size 65 to 127 bytes received and transmitted" hexmask.long 0x8 0.--31. 1. "COUNT,Total number of frames of size 65 to 127 bytes received and transmitted" line.long 0xC "CPSW_NUSS_VBUSP_OCTETFRAMES128T255,Total number of frames of size 128 to 255 bytes received and transmitted" hexmask.long 0xC 0.--31. 1. "COUNT,Total number of frames of size 128 to 255 bytes received and transmitted" line.long 0x10 "CPSW_NUSS_VBUSP_OCTETFRAMES256T511,Total number of frames of size 256 to 511 bytes received and transmitted" hexmask.long 0x10 0.--31. 1. "COUNT,Total number of frames of size 256 to 511 bytes received and transmitted" line.long 0x14 "CPSW_NUSS_VBUSP_OCTETFRAMES512T1023,Total number of frames of size 512 to 1023 bytes received and transmitted" hexmask.long 0x14 0.--31. 1. "COUNT,Total number of frames of size 512 to 1023 bytes received and transmitted" line.long 0x18 "CPSW_NUSS_VBUSP_OCTETFRAMES1024TUP,Total number of frames of size 1024 to rx_maxlen bytes received and 1024 bytes or greater transmitted" hexmask.long 0x18 0.--31. 1. "COUNT,Total number of frames of size 1024 to rx_maxlen bytes received and 1024 bytes or greater transmitted" line.long 0x1C "CPSW_NUSS_VBUSP_NETOCTETS,Total number of bytes received and transmitted" hexmask.long 0x1C 0.--31. 1. "COUNT,Total number of bytes received and transmitted" line.long 0x20 "CPSW_NUSS_VBUSP_RX_BOTTOM_OF_FIFO_DROP,Receive Bottom of FIFO Drop" hexmask.long 0x20 0.--31. 1. "COUNT,Receive Bottom of FIFO Drop" line.long 0x24 "CPSW_NUSS_VBUSP_PORTMASK_DROP,Total number of dropped frames received due to portmask" hexmask.long 0x24 0.--31. 1. "COUNT,Total number of dropped frames received due to portmask" line.long 0x28 "CPSW_NUSS_VBUSP_RX_TOP_OF_FIFO_DROP,Receive Top of FIFO Drop" hexmask.long 0x28 0.--31. 1. "COUNT,Receive Top of FIFO Drop" line.long 0x2C "CPSW_NUSS_VBUSP_ALE_RATE_LIMIT_DROP,Total number of dropped frames due to ALE Rate Limiting" hexmask.long 0x2C 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Rate Limiting" line.long 0x30 "CPSW_NUSS_VBUSP_ALE_VID_INGRESS_DROP,Total number of dropped frames due to ALE VID Ingress" hexmask.long 0x30 0.--31. 1. "COUNT,Total number of dropped frames due to ALE VID Ingress" line.long 0x34 "CPSW_NUSS_VBUSP_ALE_DA_EQ_SA_DROP,Total number of dropped frames due to DA=SA" hexmask.long 0x34 0.--31. 1. "COUNT,Total number of dropped frames due to DA=SA" line.long 0x38 "CPSW_NUSS_VBUSP_ALE_BLOCK_DROP,Total number of dropped frames due to ALE Block Mode" hexmask.long 0x38 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Block Mode" line.long 0x3C "CPSW_NUSS_VBUSP_ALE_SECURE_DROP,Total number of dropped frames due to ALE Secure Mode" hexmask.long 0x3C 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Secure Mode" line.long 0x40 "CPSW_NUSS_VBUSP_ALE_AUTH_DROP,Total number of dropped frames due to ALE Authentication" hexmask.long 0x40 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Authentication" line.long 0x44 "CPSW_NUSS_VBUSP_ALE_UNKN_UNI,ALE Receive Unknown Unicast" hexmask.long 0x44 0.--31. 1. "COUNT,ALE Receive Unknown Unicast" line.long 0x48 "CPSW_NUSS_VBUSP_ALE_UNKN_UNI_BCNT,ALE Receive Unknown Unicast Bytecount" hexmask.long 0x48 0.--31. 1. "COUNT,ALE Receive Unknown Unicast Bytecount" line.long 0x4C "CPSW_NUSS_VBUSP_ALE_UNKN_MLT,ALE Receive Unknown Multicast" hexmask.long 0x4C 0.--31. 1. "COUNT,ALE Receive Unknown Multicast" line.long 0x50 "CPSW_NUSS_VBUSP_ALE_UNKN_MLT_BCNT,ALE Receive Unknown Multicast Bytecount" hexmask.long 0x50 0.--31. 1. "COUNT,ALE Receive Unknown Multicast Bytecount" line.long 0x54 "CPSW_NUSS_VBUSP_ALE_UNKN_BRD,ALE Receive Unknown Broadcast" hexmask.long 0x54 0.--31. 1. "COUNT,ALE Receive Unknown Broadcast" line.long 0x58 "CPSW_NUSS_VBUSP_ALE_UNKN_BRD_BCNT,ALE Receive Unknown Broadcast Bytecount" hexmask.long 0x58 0.--31. 1. "COUNT,ALE Receive Unknown Broadcast Bytecount" line.long 0x5C "CPSW_NUSS_VBUSP_ALE_POL_MATCH,ALE Policer Matched" hexmask.long 0x5C 0.--31. 1. "COUNT,ALE Policer Matched" line.long 0x60 "CPSW_NUSS_VBUSP_ALE_POL_MATCH_RED,ALE Policer Matched and Condition Red" hexmask.long 0x60 0.--31. 1. "COUNT,ALE Policer Matched and Condition Red" line.long 0x64 "CPSW_NUSS_VBUSP_ALE_POL_MATCH_YELLOW,ALE Policer Matched and Condition Yellow" hexmask.long 0x64 0.--31. 1. "COUNT,ALE Policer Matched and Condition Yellow" line.long 0x68 "CPSW_NUSS_VBUSP_ALE_MULT_SA_DROP,ALE Multicast Source Address Drop" hexmask.long 0x68 0.--31. 1. "COUNT,ALE Multicast Source Address drop" line.long 0x6C "CPSW_NUSS_VBUSP_ALE_DUAL_VLAN_DROP,ALE Dual VLAN Drop" hexmask.long 0x6C 0.--31. 1. "COUNT,ALE Dual VLAN drop" line.long 0x70 "CPSW_NUSS_VBUSP_ALE_LEN_ERROR_DROP,ALE Length Error Drop" hexmask.long 0x70 0.--31. 1. "COUNT,ALE Length Error drop" line.long 0x74 "CPSW_NUSS_VBUSP_ALE_IP_NEXT_HDR_DROP,ALE IP Next Header Drop" hexmask.long 0x74 0.--31. 1. "COUNT,ALE Next Header drop" line.long 0x78 "CPSW_NUSS_VBUSP_ALE_IPV4_FRAG_DROP,ALE IPV4 Frag Drop" hexmask.long 0x78 0.--31. 1. "COUNT,ALE IPV4 Fragment drop" rgroup.long 0x3A140++0x17 line.long 0x0 "CPSW_NUSS_VBUSP_IET_RX_ASSEMBLY_ERROR_REG,IET Receive Assembly Error" hexmask.long 0x0 0.--31. 1. "IET_RX_ASSEMBLY_ERROR,IET Receive Assembly Error" line.long 0x4 "CPSW_NUSS_VBUSP_IET_RX_ASSEMBLY_OK_REG,IET Receive Assembly Ok" hexmask.long 0x4 0.--31. 1. "IET_RX_ASSEMBLY_OK,IET Receive Assembly Ok" line.long 0x8 "CPSW_NUSS_VBUSP_IET_RX_SMD_ERROR_REG,IET Receive Smd Error" hexmask.long 0x8 0.--31. 1. "IET_RX_SMD_ERROR,IET Receive Smd Error" line.long 0xC "CPSW_NUSS_VBUSP_IET_RX_FRAG_REG,IET Receive Frag" hexmask.long 0xC 0.--31. 1. "IET_RX_FRAG,IET Receive Frag" line.long 0x10 "CPSW_NUSS_VBUSP_IET_TX_HOLD_REG,IET Transmit Hold" hexmask.long 0x10 0.--31. 1. "IET_TX_HOLD,IET Transmit Hold" line.long 0x14 "CPSW_NUSS_VBUSP_IET_TX_FRAG_REG,IET Transmit Frag" hexmask.long 0x14 0.--31. 1. "IET_TX_FRAG,IET Transmit Frag" rgroup.long 0x3A17C++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_TX_MEMORY_PROTECT_ERROR,Transmit Memory Protect CRC Error" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Transmit Memory Protect CRC Error" rgroup.long 0x3A200++0xDF line.long 0x0 "CPSW_NUSS_VBUSP_RXGOODFRAMES,Total number of good frames received" hexmask.long 0x0 0.--31. 1. "COUNT,Total number of good frames received" line.long 0x4 "CPSW_NUSS_VBUSP_RXBROADCASTFRAMES,Total number of good broadcast frames received" hexmask.long 0x4 0.--31. 1. "COUNT,Total number of good broadcast frames received" line.long 0x8 "CPSW_NUSS_VBUSP_RXMULTICASTFRAMES,Total number of good multicast frames received" hexmask.long 0x8 0.--31. 1. "COUNT,Total number of good multicast frames received" line.long 0xC "CPSW_NUSS_VBUSP_RXPAUSEFRAMES,Total number of pause frames received" hexmask.long 0xC 0.--31. 1. "COUNT,Total number of pause frames received" line.long 0x10 "CPSW_NUSS_VBUSP_RXCRCERRORS,Total number of CRC errors frames received" hexmask.long 0x10 0.--31. 1. "COUNT,Total number of CRC errors frames received" line.long 0x14 "CPSW_NUSS_VBUSP_RXALIGNCODEERRORS,Total number of alignment/code errors received" hexmask.long 0x14 0.--31. 1. "COUNT,Total number of alignment/code errors received" line.long 0x18 "CPSW_NUSS_VBUSP_RXOVERSIZEDFRAMES,Total number of oversized frames received" hexmask.long 0x18 0.--31. 1. "COUNT,Total number of oversized frames received" line.long 0x1C "CPSW_NUSS_VBUSP_RXJABBERFRAMES,Total number of jabber frames received" hexmask.long 0x1C 0.--31. 1. "COUNT,Total number of jabber frames received" line.long 0x20 "CPSW_NUSS_VBUSP_RXUNDERSIZEDFRAMES,Total number of undersized frames received" hexmask.long 0x20 0.--31. 1. "COUNT,Total number of undersized frames received" line.long 0x24 "CPSW_NUSS_VBUSP_RXFRAGMENTS,Total number of fragmented frames received" hexmask.long 0x24 0.--31. 1. "COUNT,Total number of fragmented frames received" line.long 0x28 "CPSW_NUSS_VBUSP_ALE_DROP,Total number of frames dropped by the ALE" hexmask.long 0x28 0.--31. 1. "COUNT,Total number of frames dropped by the ALE" line.long 0x2C "CPSW_NUSS_VBUSP_ALE_OVERRUN_DROP,Total number of overrun frames dropped by the ALE" hexmask.long 0x2C 0.--31. 1. "COUNT,Total number of overrun frames dropped by the ALE" line.long 0x30 "CPSW_NUSS_VBUSP_RXOCTETS,Total number of received bytes in good frames" hexmask.long 0x30 0.--31. 1. "COUNT,Total number of received bytes in good frames" line.long 0x34 "CPSW_NUSS_VBUSP_TXGOODFRAMES,Total number of good frames transmitted" hexmask.long 0x34 0.--31. 1. "COUNT,Total number of good frames transmitted" line.long 0x38 "CPSW_NUSS_VBUSP_TXBROADCASTFRAMES,Total number of good broadcast frames transmitted" hexmask.long 0x38 0.--31. 1. "COUNT,Total number of good broadcast frames transmitted" line.long 0x3C "CPSW_NUSS_VBUSP_TXMULTICASTFRAMES,Total number of good multicast frames transmitted" hexmask.long 0x3C 0.--31. 1. "COUNT,Total number of good multicast frames transmitted" line.long 0x40 "CPSW_NUSS_VBUSP_TXPAUSEFRAMES,Total number of pause frames transmitted" hexmask.long 0x40 0.--31. 1. "COUNT,Total number of pause frames transmitted" line.long 0x44 "CPSW_NUSS_VBUSP_TXDEFERREDFRAMES,Total number of deferred frames transmitted" hexmask.long 0x44 0.--31. 1. "COUNT,Total number of deferred frames transmitted" line.long 0x48 "CPSW_NUSS_VBUSP_TXCOLLISIONFRAMES,Total number of transmitted frames experiencing a collision" hexmask.long 0x48 0.--31. 1. "COUNT,Total number of transmitted frames experiencing a collision" line.long 0x4C "CPSW_NUSS_VBUSP_TXSINGLECOLLFRAMES,Total number of transmitted frames experiencing a single collision" hexmask.long 0x4C 0.--31. 1. "COUNT,Total number of transmitted frames experiencing a single collision" line.long 0x50 "CPSW_NUSS_VBUSP_TXMULTCOLLFRAMES,Total number of transmitted frames experiencing multiple collisions" hexmask.long 0x50 0.--31. 1. "COUNT,Total number of transmitted frames experiencing multiple collisions" line.long 0x54 "CPSW_NUSS_VBUSP_TXEXCESSIVECOLLISIONS,Total number of transmitted frames abandoned due to excessive collisions" hexmask.long 0x54 0.--31. 1. "COUNT,Total number of transmitted frames abandoned due to excessive collisions" line.long 0x58 "CPSW_NUSS_VBUSP_TXLATECOLLISIONS,Total number of transmitted frames abandoned due to a late collision" hexmask.long 0x58 0.--31. 1. "COUNT,Total number of transmitted frames abandoned due to a late collision" line.long 0x5C "CPSW_NUSS_VBUSP_RXIPGERROR,Total number of receive inter-packet gap errors (10G only)" hexmask.long 0x5C 0.--31. 1. "COUNT,Total number of receive inter-packet gap errors (10G only)" line.long 0x60 "CPSW_NUSS_VBUSP_TXCARRIERSENSEERRORS,Total number of transmitted frames that experienced a carrier loss" hexmask.long 0x60 0.--31. 1. "COUNT,Total number of transmitted frames that experienced a carrier loss" line.long 0x64 "CPSW_NUSS_VBUSP_TXOCTETS,Total number of bytes in all good frames transmitted" hexmask.long 0x64 0.--31. 1. "COUNT,Total number of bytes in all good frames transmitted" line.long 0x68 "CPSW_NUSS_VBUSP_OCTETFRAMES64,Total number of 64-byte frames received and transmitted" hexmask.long 0x68 0.--31. 1. "COUNT,Total number of 64-byte frames received and transmitted" line.long 0x6C "CPSW_NUSS_VBUSP_OCTETFRAMES65T127,Total number of frames of size 65 to 127 bytes received and transmitted" hexmask.long 0x6C 0.--31. 1. "COUNT,Total number of frames of size 65 to 127 bytes received and transmitted" line.long 0x70 "CPSW_NUSS_VBUSP_OCTETFRAMES128T255,Total number of frames of size 128 to 255 bytes received and transmitted" hexmask.long 0x70 0.--31. 1. "COUNT,Total number of frames of size 128 to 255 bytes received and transmitted" line.long 0x74 "CPSW_NUSS_VBUSP_OCTETFRAMES256T511,Total number of frames of size 256 to 511 bytes received and transmitted" hexmask.long 0x74 0.--31. 1. "COUNT,Total number of frames of size 256 to 511 bytes received and transmitted" line.long 0x78 "CPSW_NUSS_VBUSP_OCTETFRAMES512T1023,Total number of frames of size 512 to 1023 bytes received and transmitted" hexmask.long 0x78 0.--31. 1. "COUNT,Total number of frames of size 512 to 1023 bytes received and transmitted" line.long 0x7C "CPSW_NUSS_VBUSP_OCTETFRAMES1024TUP,Total number of frames of size 1024 to rx_maxlen bytes received and 1024 bytes or greater transmitted" hexmask.long 0x7C 0.--31. 1. "COUNT,Total number of frames of size 1024 to rx_maxlen bytes received and 1024 bytes or greater transmitted" line.long 0x80 "CPSW_NUSS_VBUSP_NETOCTETS,Total number of bytes received and transmitted" hexmask.long 0x80 0.--31. 1. "COUNT,Total number of bytes received and transmitted" line.long 0x84 "CPSW_NUSS_VBUSP_RX_BOTTOM_OF_FIFO_DROP,Receive Bottom of FIFO Drop" hexmask.long 0x84 0.--31. 1. "COUNT,Receive Bottom of FIFO Drop" line.long 0x88 "CPSW_NUSS_VBUSP_PORTMASK_DROP,Total number of dropped frames received due to portmask" hexmask.long 0x88 0.--31. 1. "COUNT,Total number of dropped frames received due to portmask" line.long 0x8C "CPSW_NUSS_VBUSP_RX_TOP_OF_FIFO_DROP,Receive Top of FIFO Drop" hexmask.long 0x8C 0.--31. 1. "COUNT,Receive Top of FIFO Drop" line.long 0x90 "CPSW_NUSS_VBUSP_ALE_RATE_LIMIT_DROP,Total number of dropped frames due to ALE Rate Limiting" hexmask.long 0x90 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Rate Limiting" line.long 0x94 "CPSW_NUSS_VBUSP_ALE_VID_INGRESS_DROP,Total number of dropped frames due to ALE VID Ingress" hexmask.long 0x94 0.--31. 1. "COUNT,Total number of dropped frames due to ALE VID Ingress" line.long 0x98 "CPSW_NUSS_VBUSP_ALE_DA_EQ_SA_DROP,Total number of dropped frames due to DA=SA" hexmask.long 0x98 0.--31. 1. "COUNT,Total number of dropped frames due to DA=SA" line.long 0x9C "CPSW_NUSS_VBUSP_ALE_BLOCK_DROP,Total number of dropped frames due to ALE Block Mode" hexmask.long 0x9C 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Block Mode" line.long 0xA0 "CPSW_NUSS_VBUSP_ALE_SECURE_DROP,Total number of dropped frames due to ALE Secure Mode" hexmask.long 0xA0 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Secure Mode" line.long 0xA4 "CPSW_NUSS_VBUSP_ALE_AUTH_DROP,Total number of dropped frames due to ALE Authentication" hexmask.long 0xA4 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Authentication" line.long 0xA8 "CPSW_NUSS_VBUSP_ALE_UNKN_UNI,ALE Receive Unknown Unicast" hexmask.long 0xA8 0.--31. 1. "COUNT,ALE Receive Unknown Unicast" line.long 0xAC "CPSW_NUSS_VBUSP_ALE_UNKN_UNI_BCNT,ALE Receive Unknown Unicast Bytecount" hexmask.long 0xAC 0.--31. 1. "COUNT,ALE Receive Unknown Unicast Bytecount" line.long 0xB0 "CPSW_NUSS_VBUSP_ALE_UNKN_MLT,ALE Receive Unknown Multicast" hexmask.long 0xB0 0.--31. 1. "COUNT,ALE Receive Unknown Multicast" line.long 0xB4 "CPSW_NUSS_VBUSP_ALE_UNKN_MLT_BCNT,ALE Receive Unknown Multicast Bytecount" hexmask.long 0xB4 0.--31. 1. "COUNT,ALE Receive Unknown Multicast Bytecount" line.long 0xB8 "CPSW_NUSS_VBUSP_ALE_UNKN_BRD,ALE Receive Unknown Broadcast" hexmask.long 0xB8 0.--31. 1. "COUNT,ALE Receive Unknown Broadcast" line.long 0xBC "CPSW_NUSS_VBUSP_ALE_UNKN_BRD_BCNT,ALE Receive Unknown Broadcast Bytecount" hexmask.long 0xBC 0.--31. 1. "COUNT,ALE Receive Unknown Broadcast Bytecount" line.long 0xC0 "CPSW_NUSS_VBUSP_ALE_POL_MATCH,ALE Policer Matched" hexmask.long 0xC0 0.--31. 1. "COUNT,ALE Policer Matched" line.long 0xC4 "CPSW_NUSS_VBUSP_ALE_POL_MATCH_RED,ALE Policer Matched and Condition Red" hexmask.long 0xC4 0.--31. 1. "COUNT,ALE Policer Matched and Condition Red" line.long 0xC8 "CPSW_NUSS_VBUSP_ALE_POL_MATCH_YELLOW,ALE Policer Matched and Condition Yellow" hexmask.long 0xC8 0.--31. 1. "COUNT,ALE Policer Matched and Condition Yellow" line.long 0xCC "CPSW_NUSS_VBUSP_ALE_MULT_SA_DROP,ALE Multicast Source Address Drop" hexmask.long 0xCC 0.--31. 1. "COUNT,ALE Multicast Source Address drop" line.long 0xD0 "CPSW_NUSS_VBUSP_ALE_DUAL_VLAN_DROP,ALE Dual VLAN Drop" hexmask.long 0xD0 0.--31. 1. "COUNT,ALE Dual VLAN drop" line.long 0xD4 "CPSW_NUSS_VBUSP_ALE_LEN_ERROR_DROP,ALE Length Error Drop" hexmask.long 0xD4 0.--31. 1. "COUNT,ALE Length Error drop" line.long 0xD8 "CPSW_NUSS_VBUSP_ALE_IP_NEXT_HDR_DROP,ALE IP Next Header Drop" hexmask.long 0xD8 0.--31. 1. "COUNT,ALE Next Header drop" line.long 0xDC "CPSW_NUSS_VBUSP_ALE_IPV4_FRAG_DROP,ALE IPV4 Frag Drop" hexmask.long 0xDC 0.--31. 1. "COUNT,ALE IPV4 Fragment drop" rgroup.long 0x3A340++0x17 line.long 0x0 "CPSW_NUSS_VBUSP_IET_RX_ASSEMBLY_ERROR_REG,IET Receive Assembly Error" hexmask.long 0x0 0.--31. 1. "IET_RX_ASSEMBLY_ERROR,IET Receive Assembly Error" line.long 0x4 "CPSW_NUSS_VBUSP_IET_RX_ASSEMBLY_OK_REG,IET Receive Assembly Ok" hexmask.long 0x4 0.--31. 1. "IET_RX_ASSEMBLY_OK,IET Receive Assembly Ok" line.long 0x8 "CPSW_NUSS_VBUSP_IET_RX_SMD_ERROR_REG,IET Receive Smd Error" hexmask.long 0x8 0.--31. 1. "IET_RX_SMD_ERROR,IET Receive Smd Error" line.long 0xC "CPSW_NUSS_VBUSP_IET_RX_FRAG_REG,IET Receive Frag" hexmask.long 0xC 0.--31. 1. "IET_RX_FRAG,IET Receive Frag" line.long 0x10 "CPSW_NUSS_VBUSP_IET_TX_HOLD_REG,IET Transmit Hold" hexmask.long 0x10 0.--31. 1. "IET_TX_HOLD,IET Transmit Hold" line.long 0x14 "CPSW_NUSS_VBUSP_IET_TX_FRAG_REG,IET Transmit Frag" hexmask.long 0x14 0.--31. 1. "IET_TX_FRAG,IET Transmit Frag" rgroup.long 0x3A37C++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_TX_MEMORY_PROTECT_ERROR,Transmit Memory Protect CRC Error" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Transmit Memory Protect CRC Error" line.long 0x4 "CPSW_NUSS_VBUSP_ENET_PN_TX_PRI_REG,ENET Port n PRIORITY N Packet Count" hexmask.long 0x4 0.--31. 1. "PN_TX_PRIN,Enet Port n Priority N Packet Count" rgroup.long 0x3A3A0++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_ENET_PN_TX_PRI_BCNT_REG,ENET Port n PRIORITY N Packet Byte Count" hexmask.long 0x0 0.--31. 1. "PN_TX_PRIN_BCNT,ENET Port n PRIORITY N Packet Byte Count" rgroup.long 0x3A3C0++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_ENET_PN_TX_PRI_DROP_REG,ENET Port n PRIORITY N Packet Drop Count" hexmask.long 0x0 0.--31. 1. "PN_TX_PRIN_DROP,ENET Port n PRIORITY N Packet Drop Count" rgroup.long 0x3A3E0++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_ENET_PN_TX_PRI_DROP_BCNT_REG,ENET Port n PRIORITY N Packet Drop Byte Count" hexmask.long 0x0 0.--31. 1. "PN_TX_PRIN_DROP_BCNT,ENET Port n PRIORITY N Packet Drop Byte Count" rgroup.long 0x3D000++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_CPTS_IDVER_REG,Identification and Version Register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" rgroup.long 0x3D004++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_CONTROL_REG,Time Sync Control Register" hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" newline bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1" newline bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1" newline bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1" newline bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1" newline bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" newline bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" newline bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" newline bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" newline bitfld.long 0x0 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1" newline bitfld.long 0x0 6. "TS_COMP_TOG,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode 1=TS_COMP is in toggle mode" "0: TS_COMP is in non-toggle mode,1: TS_COMP is in toggle mode" newline bitfld.long 0x0 5. "MODE,Timestamp mode" "0,1" newline bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable" "0,1" newline bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1" newline bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1" newline bitfld.long 0x0 1. "INT_TEST,Interrupt test" "0,1" newline bitfld.long 0x0 0. "CPTS_EN,Time sync enable" "0,1" line.long 0x4 "CPSW_NUSS_VBUSP_RFTCLK_SEL_REG,RFTCLK Select Register" hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select" rgroup.long 0x3D00C++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_TS_PUSH_REG,Time Stamp Event Push Register" bitfld.long 0x0 0. "TS_PUSH,Time stamp event push" "0,1" rgroup.long 0x3D010++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_TS_LOAD_LOW_VAL_REG,Time Stamp Load Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value" rgroup.long 0x3D014++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_TS_LOAD_EN_REG,Time Stamp Load Enable Register" bitfld.long 0x0 0. "TS_LOAD_EN,Time stamp load enable" "0,1" rgroup.long 0x3D018++0xB line.long 0x0 "CPSW_NUSS_VBUSP_TS_COMP_LOW_VAL_REG,Time Stamp Comparison Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time stamp comparison low value" line.long 0x4 "CPSW_NUSS_VBUSP_TS_COMP_LEN_REG,Time Stamp Comparison Length Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time stamp comparison length" line.long 0x8 "CPSW_NUSS_VBUSP_INTSTAT_RAW_REG,Interrupt Status Register Raw" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" rgroup.long 0x3D024++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_INTSTAT_MASKED_REG,Interrupt Status Register Masked" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" rgroup.long 0x3D028++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_INT_ENABLE_REG,Interrupt Enable Register" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" line.long 0x4 "CPSW_NUSS_VBUSP_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount" rgroup.long 0x3D030++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_EVENT_POP_REG,Event Pop Register" bitfld.long 0x0 0. "EVENT_POP,Event pop" "0,1" rgroup.long 0x3D034++0xF line.long 0x0 "CPSW_NUSS_VBUSP_EVENT_0_REG,Event 0 Register" hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp" line.long 0x4 "CPSW_NUSS_VBUSP_EVENT_1_REG,Event 1 Register" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1" newline hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port number" newline hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Event type" newline hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type" newline hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID" line.long 0x8 "CPSW_NUSS_VBUSP_EVENT_2_REG,Event 2 Register" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain" line.long 0xC "CPSW_NUSS_VBUSP_EVENT_3_REG,Event 3 Register" hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp" rgroup.long 0x3D044++0x17 line.long 0x0 "CPSW_NUSS_VBUSP_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load high value" line.long 0x4 "CPSW_NUSS_VBUSP_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time stamp comparison high value" line.long 0x8 "CPSW_NUSS_VBUSP_TS_ADD_VAL_REG,TS Add Value Register" bitfld.long 0x8 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7" line.long 0xC "CPSW_NUSS_VBUSP_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register" hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time stamp PPM Low value" line.long 0x10 "CPSW_NUSS_VBUSP_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value" line.long 0x14 "CPSW_NUSS_VBUSP_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value" rgroup.long 0x3E000++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_MOD_VER,The Module and Version Register identifies the module identifier and revision of the ALE_2g64i module." hexmask.long.word 0x0 16.--31. 1. "MODULE_ID,ALE_2g64i module ID." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VERSION,RTL Version." newline bitfld.long 0x0 8.--10. "MAJOR_REVISION,Major Revision." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM_REVISION,Custom Revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REVISION,Minor Revision." line.long 0x4 "CPSW_NUSS_VBUSP_ALE_STATUS,The ALE status provides information on the ALE configuration and state. The ~iramdepth is used to determine how IPv6 entries are stored in the table. IPv6 entries are stored in two entries where IPv6 Entry hi is designated by.." hexmask.long.byte 0x4 8.--15. 1. "POLCNTDIV8,This is the number of policer engines the ALE implements divided by 8. A value of 4 indicates 32 policer engines total." newline bitfld.long 0x4 7. "RAMDEPTH128,The number of ALE entries per slice of the table when this is set it indicates the depth is 128 if both ramdepth128 and ramdepth32 are zero the depth is 64." "0,1" newline bitfld.long 0x4 6. "RAMDEPTH32,The number of ALE entries per slice of the table when this is set it indicates the depth is 32 if both ramdepth128 and ramdepth32 are zero the depth is 64." "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "KLUENTRIES,This is the number of table entries total divided by 1024. A value of 1 indicates 1024 table entries. A value of 8 indicates 8192 table entries." rgroup.long 0x3E008++0xF line.long 0x0 "CPSW_NUSS_VBUSP_ALE_CONTROL,The ALE Control Register is used to set the ALE modes used for all ports." bitfld.long 0x0 31. "ENABLE_ALE,Enable ALE 0 - Drop all packets 1 - Enable ALE packet processing" "0: Drop all packets 1,?" newline bitfld.long 0x0 30. "CLEAR_TABLE,Clear ALE address table - Setting this bit causes the ALE hardware to write all table bit values to zero. Software must perform a clear table operation as part of the ALE setup/configuration process. Setting this bit causes all ALE accesses.." "0,1" newline bitfld.long 0x0 29. "AGE_OUT_NOW,Age Out Address Table Now - Setting this bit causes the ALE hardware to remove (free up) any ageable table entry that does not have a set touch bit. This bit is cleared when the age out process has completed. This bit may be read. The age out.." "0,1" newline bitfld.long 0x0 24. "MIRROR_DP,Mirror Destination Port - This field defines the port to which destination traffic destined will be duplicated. That is all traffic that is forwarded to this port will also be mirrored to the ~imirror_top port." "0,1" newline bitfld.long 0x0 21.--23. "UPD_BW_CTRL,The ~iupd_bw_ctrl field allows for up to 8 times the rate in which adds updates touches writes and aging updates can occur. At frequencies of 350Mhz the table update rate should be at it lowest or 5 Million updates per second. When.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "MIRROR_TOP,Mirror To Port - This field defines the destination port for the mirror traffic. If the traffic is received or transmitted on the mirror destination port it will not be duplicated. Traffic defined as mirror traffic only may be dropped by the.." "0,1" newline bitfld.long 0x0 15. "UPD_STATIC,Update Static Entries - A static Entry is an entry that is not agable. When clear this bit will prevent any static entry (agable bit clear) from being updated due to port change. When set it allows static entries (agable bit clear) to update.." "0,1" newline bitfld.long 0x0 13. "UVLAN_NO_LEARN,Unknown VLAN No Learn - This field when set will prevent source addresses of unknown VLAN IDs from being automatically added into the look up table if learning is enabled." "0,1" newline bitfld.long 0x0 12. "MIRROR_MEN,Mirror Match Entry Enable - This field enables the match mirror option. When this bit is set any traffic whose destination source VLAN or OUI matches the ~imirror_midx entry index will have that traffic also sent to the ~imirror_top port." "0,1" newline bitfld.long 0x0 11. "MIRROR_DEN,Mirror Destination Port Enable - This field enables the destination port mirror option. When this bit is set any traffic destined for the ~imirror_dp port will have its transmit traffic also sent to the ~imirror_top port." "0,1" newline bitfld.long 0x0 10. "MIRROR_SEN,Mirror Source Port Enable - This field enables the source port mirror option. When this bit is set any port with the ~ipX_mirror_sp set in the ALE Port Control registers set will have its received traffic also sent to the ~imirror_top port." "0,1" newline bitfld.long 0x0 8. "EN_HOST_UNI_FLOOD,Unknown unicast packets flood to host 0 - unknown unicast packets are not sent to the host 1 - unknown unicast packets flood to host port as well as other ports" "0: unknown unicast packets are not sent to the host..,?" newline bitfld.long 0x0 7. "LEARN_NO_VLANID,Learn No VID - 0 - VID is learned with the source address 1 - VID is not learned with the source address (source address is not tied to VID). Determines the entry type." "0: VID is learned with the source address 1,?" newline bitfld.long 0x0 6. "ENABLE_VID0_MODE,Enable VLAN ID = 0 Mode 0 - Process the priority tagged packet with VID = PORT_VLAN[11:0]. 1 - Process the priority tagged packet with VID = 0." "0: Process the priority tagged packet with VID =..,1: Process the priority tagged packet with VID = 0" newline bitfld.long 0x0 5. "ENABLE_OUI_DENY,Enable OUI Deny Mode - When set any packet with a non-matching OUI source address will be dropped to the host unless the packet destination address matches a supervisory destination address table entry. When cleared any packet source.." "0,1" newline bitfld.long 0x0 4. "ENABLE_BYPASS,ALE Bypass - When set packets received on non-host ports are sent to the host. It is expected that packets from the host are directed to the particular port. 0 - no bypass 1 - bypass the ALE" "0: no bypass 1,?" newline bitfld.long 0x0 3. "BCAST_MCAST_CTL,Rate Limit Transmit mode 0 - Broadcast and multicast rate limit counters are received port based 1 - Broadcast and multicast rate limit counters are transmit port based" "0: Broadcast and multicast rate limit counters are..,?" newline bitfld.long 0x0 2. "ALE_VLAN_AWARE,ALE VLAN Aware - Determines how traffic is forwarded using VLAN rules. 0 - Simple switch rules packets forwarded to all ports for unknown destinations. 1 - VLAN Aware rules packets forwarded based on VLAN members" "0: Simple switch rules,1: VLAN Aware rules" newline bitfld.long 0x0 1. "ENABLE_AUTH_MODE,Enable MAC Authorization Mode - Mac authorization mode requires that all table entries be made by the host software. There is no auto learning of addresses in authorization mode and the packet will be dropped if the source address is not.." "0: The ALE is not in MAC authorization mode 1,?" newline bitfld.long 0x0 0. "ENABLE_RATE_LIMIT,Enable Broadcast and Multicast Rate Limit 0 - Broadcast/Multicast rates not limited 1 - Broadcast/Multicast packet reception limited to the port control register rate limit fields." "0: Broadcast/Multicast rates not limited 1,?" line.long 0x4 "CPSW_NUSS_VBUSP_ALE_CTRL2,The ALE Control 2 Register is used to set the extended features used for all ports." bitfld.long 0x4 31. "TRK_EN_DST,Trunk Enable Destination Address - This field enables the destination MAC address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination." "0,1" newline bitfld.long 0x4 30. "TRK_EN_SRC,Trunk Enable Source Address - This field enables the source MAC address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination." "0,1" newline bitfld.long 0x4 29. "TRK_EN_PRI,Trunk Enable Priority - This field enables the VLAN Priority bits to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. In the event that DSCP mapping is enabled and there is no VLAN the.." "0,1" newline bitfld.long 0x4 27. "TRK_EN_IVLAN,Trunk Enable Inner VLAN - This field enables the inner VLAN ID value (C-VLANID) to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination." "0,1" newline bitfld.long 0x4 25. "TRK_EN_SIP,Trunk Enable Source IP Address - This field enables the source IP address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. This feature supports No tag Priority tagged VLAN tagged .." "0,1" newline bitfld.long 0x4 24. "TRK_EN_DIP,Trunk Enable Destination IP Address - This field enables the destination IP address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. This feature supports No tag Priority tagged VLAN.." "0,1" newline bitfld.long 0x4 23. "DROP_BADLEN,Drop Bad Length will drop any packet that the 802.3 length field is larger than the packet. Ethertypes 0-1500 are 802.3 lengths all others are Ether types." "0,1" newline bitfld.long 0x4 22. "NODROP_SRCMCST,No Drop Source Multicast will disable the dropping of any source address with the multicast bit set." "0,1" newline bitfld.long 0x4 21. "DEFNOFRAG,Default No Frag field will cause an IPv4 fragmented packet to be dropped if a VLAN entry is not found." "0,1" newline bitfld.long 0x4 20. "DEFLMTNXTHDR,Default limit next header field will cause an IPv4 protocol or IPv6 next header packet to be dropped if a VLAN entry is not found and the protocol or next header does not match the ~iALE_NXT_HDR register values." "0,1" newline bitfld.long 0x4 16.--18. "TRK_BASE,Trunk Base - This field is the hash formula starting value. Changing this value will cause the packet distribution on trunk ports to be changed. If all the ~itrk_en_dst ~itrk_en_src ~itrk_en_pri and ~itrk_en_vlan are '0' this value is used as.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--5. 1. "MIRROR_MIDX,Mirror Index - This field is the ALE lookup table entry index that when a match occurs will cause this traffic to be mirrored to the ~imirror_top port. That is any VLAN ONU or address with or withou VLAN can be selected for traffic mirroring." line.long 0x8 "CPSW_NUSS_VBUSP_ALE_PRESCALE,The ALE Prescale Register is used to set the Broadcast and Multicast rate limiting prescaler value." hexmask.long.tbyte 0x8 0.--19. 1. "ALE_PRESCALE,ALE Prescale - The input clock is divided by this value for use in the multicast/broadcast rate limiters. The minimum operating value is 0x10. The prescaler is off when the value is zero." line.long 0xC "CPSW_NUSS_VBUSP_ALE_AGING_CTRL,The ALE Aging Control sets the aging interval which will cause periodic aging to occur. This value specifies the minimum time between aging starts." bitfld.long 0xC 31. "PRESCALE_2_DISABLE,ALE Prescaler 2 Disable - When set will divide the aging interval by 1000. This bit is designed for device verification and should not be used in production software. Combination of PreScale1Disable and PreScale2Disable will divide the.." "0,1" newline bitfld.long 0xC 30. "PRESCALE_1_DISABLE,ALE Prescaler 1 Disable - When set will divide the aging interval by 1000. This bit is designed for device verification and should not be used in production software. Combination of PreScale1Disable and PreScale2Disable will divide the.." "0,1" newline hexmask.long.tbyte 0xC 0.--23. 1. "ALE_AGING_TIMER,ALE Aging Timer - This field specifies the number of clock cycles times 1 000 000 between aging operations." rgroup.long 0x3E01C++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_ALE_NXT_HDR,The ALE Next Header is used to limit the IPv6 Next header or IPv4 Protocol values found in the IP header. It is enabled via the ~iLmtNxtHdr bit in the VLAN entry. All four ~iip_nxt_hdr0-3 are compared when enabled. so if only.." hexmask.long.byte 0x0 24.--31. 1. "IP_NXT_HDR3,The ~iip_nxt_hdr3 is the forth protocol or next header compared when enabled." newline hexmask.long.byte 0x0 16.--23. 1. "IP_NXT_HDR2,The ~iip_nxt_hdr2 is the third protocol or next header compared when enabled." newline hexmask.long.byte 0x0 8.--15. 1. "IP_NXT_HDR1,The ~iip_nxt_hdr1 is the second protocol or next header compared when enabled." newline hexmask.long.byte 0x0 0.--7. 1. "IP_NXT_HDR0,The ~iip_nxt_hdr0 is the first protocol or next header compared when enabled." line.long 0x4 "CPSW_NUSS_VBUSP_ALE_TBLCTL,The ALE table control register is used to read or write that ALE table entries. After writing to this register any read or write to any ALE register will be stalled until the read or write operation completes." bitfld.long 0x4 31. "TABLEWR,Table Write - This bit is used to write the table words to the lookup table. 0 - Table Read Operation is performed. The contents of the ~b TABLEIDX entry will be read into the ~b ALE_TBLWx registers 1 - Table write operation is performed. This.." "0: Table Read Operation is performed,1: Table write operation is performed" newline hexmask.long.byte 0x4 0.--5. 1. "TABLEIDX,The table index is used to determine which lookup table entry is read or written." rgroup.long 0x3E034++0xF line.long 0x0 "CPSW_NUSS_VBUSP_ALE_TBLW2,The ALE Table Word 2 is the most significant word of an ALE table entry." hexmask.long.byte 0x0 0.--6. 1. "TABLEWRD2,Table Entry bits [71:64]" line.long 0x4 "CPSW_NUSS_VBUSP_ALE_TBLW1,The ALE Table Word 1 is the middle word of an ALE table entry." hexmask.long 0x4 0.--31. 1. "TABLEWRD1,Table Entry bits [63:32]" line.long 0x8 "CPSW_NUSS_VBUSP_ALE_TBLW0,The ALE Table Word 0 is the least significant word of an ALE table entry." hexmask.long 0x8 0.--31. 1. "TABLEWRD0,Table Entry bits [31:0]" line.long 0xC "CPSW_NUSS_VBUSP_I0_ALE_PORTCTL0,The ALE Port Control Register sets the port specific modes of operation." hexmask.long.byte 0xC 24.--31. 1. "I0_REG_P0_BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter. The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or.." newline hexmask.long.byte 0xC 16.--23. 1. "I0_REG_P0_MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter. The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or.." newline bitfld.long 0xC 15. "I0_REG_P0_DROP_DOUBLE_VLAN,Drop Double VLAN - When set cause any received packet with double VLANs to be dropped. That is if there are two ctag or two stag fields in the packet it will be dropped." "0,1" newline bitfld.long 0xC 14. "I0_REG_P0_DROP_DUAL_VLAN,Drop Dual VLAN - When set will cause any received packet with dual VLAN stag followed by ctag to be dropped." "0,1" newline bitfld.long 0xC 13. "I0_REG_P0_MACONLY_CAF,Mac Only Copy All Frames - When set a Mac Only port will transfer all received good frames to the host. When clear a Mac Only port will transfer packets to the host based on ALE destination address lookup operation (which operates.." "0,1" newline bitfld.long 0xC 12. "I0_REG_P0_DIS_PAUTHMOD,Disable Port authorization - When set will allow unknown addresses to arrive on a switch in authorization mode. It is intended for device to device network connection on ports which do not require MACSEC encryption." "0,1" newline bitfld.long 0xC 11. "I0_REG_P0_MACONLY,MAC Only - When set enables this port be treated like a MAC port for the host. All traffic received is only sent to the host. The host must direct traffic to this port as the lookup engine will not send traffic to the ports with the.." "0,1" newline bitfld.long 0xC 10. "I0_REG_P0_TRUNKEN,Trunk Enable - This field is used to enable a port into a trunk. Any port can be used as a trunk port any two or more ports with the ~ip0_trunken its set and having the same ~ip0_trunknum will be placed in the same trunk. There is no.." "0,1" newline bitfld.long 0xC 8.--9. "I0_REG_P0_TRUNKNUM,Trunk Number - This field is used as the trunk number when the ~ip0_trunken is also set. Ports with the same trunk number that have the ~ip0_trunken also set will have traffic distributed within the trunk based on the result of the.." "0,1,2,3" newline bitfld.long 0xC 7. "I0_REG_P0_MIRROR_SP,Mirror Source Port - This field enables the source port mirror option. When this bit is set any traffic received on the port with the reg_p0_mirror_sp bit set will have its received traffic also sent to the ~imirror_top port." "0,1" newline bitfld.long 0xC 5. "I0_REG_P0_NO_SA_UPDATE,No Source Address Update - When set will not update the source addresses for this port." "0,1" newline bitfld.long 0xC 4. "I0_REG_P0_NO_LEARN,No Learn - When set will not learn the source addresses for this port." "0,1" newline bitfld.long 0xC 3. "I0_REG_P0_VID_INGRESS_CHECK,VLAN Ingress Check - When set if a packet received is not a member of the VLAN the packet will be dropped." "0,1" newline bitfld.long 0xC 2. "I0_REG_P0_DROP_UN_TAGGED,If Drop Untagged - When set will drop packets without a VLAN tag." "0,1" newline bitfld.long 0xC 0.--1. "I0_REG_P0_PORTSTATE,Port State - Defins the current port state used for lookup operations. 0 - Disabled 1 - Blocked 2 - Learning 3 - Forwarding" "0: Disabled 1,?,2: Learning 3,?" rgroup.long 0x3E090++0xF line.long 0x0 "CPSW_NUSS_VBUSP_ALE_UVLAN_MEMBER,The ALE Unknown VLAN Member Mask Register is used to specify the member list for unknown VLAN ID." bitfld.long 0x0 0.--1. "UVLAN_MEMBER_LIST,Unknown VLAN Member List - Each bit represents the port member status for unknown VLANs." "0,1,2,3" line.long 0x4 "CPSW_NUSS_VBUSP_ALE_UVLAN_URCAST,The ALE Unknown VLAN Unregistered Multicast Flood Mask Register is used to specify which egress ports unregistered multicast addresses egress for the unregistered VLAN ID." bitfld.long 0x4 0.--1. "UVLAN_UNREG_MCAST_FLOOD_MASK,Unknown VLAN Unregister Multicast Flood Mask - Each bit represents the port to which unregistered multicast are sent for unregistered VLANs." "0,1,2,3" line.long 0x8 "CPSW_NUSS_VBUSP_ALE_UVLAN_RMCAST,The ALE Unknown VLAN Registered Multicast Flood Mask Register is used to specify which egress ports registered multicast addresses egress for the unregistered VLAN ID." bitfld.long 0x8 0.--1. "UVLAN_REG_MCAST_FLOOD_MASK,Unknown VLAN Register Multicast Flood Mask - Each bit represents the port to which registered multicast are sent for unregistered VLANs. This field is ANDed with the registered multicast mask to determine the destinations for.." "0,1,2,3" line.long 0xC "CPSW_NUSS_VBUSP_ALE_UVLAN_UNTAG,The ALE Unknown VLAN force Untagged Egress Mask Register is used to specify which egress ports the VLAN ID will be removed." bitfld.long 0xC 0.--1. "UVLAN_FORCE_UNTAGGED_EGRESS,Unknown VLAN Force Untagged Egress Mask - Each bit represents the port where the VLAN will be removed for unregistered VLANs." "0,1,2,3" rgroup.long 0x3E0B8++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_ALE_STAT_DIAG,The ALE Statistic Output Diagnostic Register allows the output statistics to diagnose the SW counters. This register is for diagnostice only." bitfld.long 0x0 15. "PBCAST_DIAG,When set and the ~iport_diag is set to zero will allow all ports to see the same stat diagnostic increment." "0,1" newline bitfld.long 0x0 8. "PORT_DIAG,The port selected that a received packet will cause the selected error to increment" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "STAT_DIAG,When non-zero will cause the selected statistic to increment on the next frame received. For the selected Port. 0: Disabled 1: Destination Equal Source Drop Stat will count 2: VLAN Ingress Check Drop Stat will count 3: Source Multicast.." line.long 0x4 "CPSW_NUSS_VBUSP_ALE_OAM_LB_CTRL,The ALE OAM Control allows ports to be put into OAM Loopback. only non-supervisor packet are looped back to the source port." bitfld.long 0x4 0.--1. "OAM_LB_CTRL,The ~ioam_lb_ctrl allows any port to be put into OAM loopback that is any packet received will be returned to the same port with an egressop of 0xFF which swaps the source and destination address. BPDUs will still flow through as normal so.." "0,1,2,3" rgroup.long 0x3E0C0++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_ALE_MSK_MUX0,VLAN Mask Mux x - The ALE Mask Mux registers are used along with the VLAN registered/unregistered index selectors from the Lookup Table to determine the value for vlan registered and unregister mask respectively." bitfld.long 0x0 0.--1. "VLAN_MASK_MUX_0,VLAN Mask Mux x - When selected by the VLAN lookup table entry FwdUnRegIdx or FwdAllRegIdx is used as the FwdUnRegMask or FwdUnRegMask values anded with the member list to determine the forwarding of packets. The Value of vlan_mask_mux_0.." "0,1,2,3" rgroup.long 0x3E0C4++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_I1_ALE_MSK_MUX1,VLAN Mask Mux x - The ALE Mask Mux registers are used along with the VLAN registered/unregistered index selectors from the Lookup Table to determine the value for vlan registered and unregister mask respectively." bitfld.long 0x0 0.--1. "I1_REG_VLAN_MASK_MUX_1,VLAN Mask Mux x - When selected by the VLAN lookup table entry FwdUnRegIdx or FwdAllRegIdx is used as the FwdUnRegMask or FwdUnRegMask values anded with the member list to determine the forwarding of packets. The Value of.." "0,1,2,3" rgroup.long 0x3E0FC++0x17 line.long 0x0 "CPSW_NUSS_VBUSP_EGRESSOP,The Egress Operation register allows enabled classifiers with IPSA or IPDA match to use the CPSW Egress Packet Operations Inter VLAN Routing sub functions. If the packet was destined for the host. but matches a clasifier that has.." hexmask.long.byte 0x0 24.--31. 1. "EGRESS_OP,The Egress Operation defines the operation performed by the CPSW Egress Packet Operations 0: NOP : 1-n: Defines which egress Operation will be performed. This allows Inter VLAN routing to be configured for high bandwidth traffic reducing CPU.." newline bitfld.long 0x0 21.--23. "EGRESS_TRK,The Egress Trunk Index is the calculated trunk index from the SA DA or VLAN if modified to that InterVLAN routing will work on trunks as well. The DA SA and VLAN are ignored for trunk generation on InterVLAN Routing so that this field is the.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "TTL_CHECK,The TTL Check will cause any packet that fails TTL checks to not be routed to the Inter VLAN Routing sub functions. The packet will be routed to the host it was destined to." "0,1" newline bitfld.long 0x0 0.--1. "DEST_PORTS,The Destination Ports is a list of the ports the classified packet will be set to. If a destination is a Trunk all the port bits for that trunck must be set." "0,1,2,3" line.long 0x4 "CPSW_NUSS_VBUSP_POLICECFG0,The Policing Config 0 holds the port. frame priority and ONU address index as well as match enables for port. frame priority and ONU address matching." bitfld.long 0x4 31. "PORT_MEN,Port Match Enable - Enabled port match for the selected policing/classifier entry" "0,1" newline bitfld.long 0x4 30. "TRUNKID,Trunk ID - When set indicates the port number is a trunk group." "0,1" newline bitfld.long 0x4 25. "PORT_NUM,Port Number - Specifies the port address to match for the selected policing/classifier entry" "0,1" newline bitfld.long 0x4 19. "PRI_MEN,Priority Match Enable - Enables frame priority match for the selected policing/classifier entry" "0,1" newline bitfld.long 0x4 16.--18. "PRI_VAL,Priority Value - Specifies the frame priority to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "ONU_MEN,OUI Match Enable - Enables frame ONU address match for the selected policing/classifier entry" "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "ONU_INDEX,OUI Table Entry Index - Specifies the ALE ONU address lookup table index to match for the selected policing/classifier entry" line.long 0x8 "CPSW_NUSS_VBUSP_POLICECFG1,The Policing Config 1 holds the match enable/match index for the L2 Destination and L2 source addresses" bitfld.long 0x8 31. "DST_MEN,Destination Address Match Enable - Enables frame L2 destination address match for the selected policing/classifier entry" "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "DST_INDEX,Destination Address Table Entry Index - Specifies the ALE L2 destination address lookup table index to match for the selected policing/classifier entry" newline bitfld.long 0x8 15. "SRC_MEN,Source Address Match Enable - Enables frame L2 source address match for the selected policing/classifier entry" "0,1" newline hexmask.long.byte 0x8 0.--5. 1. "SRC_INDEX,Source Address Table Entry Index - Specifies the ALE L2 source address lookup table index to match for the selected policing/classifier entry" line.long 0xC "CPSW_NUSS_VBUSP_POLICECFG2,The Policing Config 2 holds the match enable/match index for the Outer VLAN and Inner VLAN addresses" bitfld.long 0xC 31. "OVLAN_MEN,Outer VLAN Match Enable - Enables frame Outer VLAN address match for the selected policing/classifier entry" "0,1" newline hexmask.long.byte 0xC 16.--21. 1. "OVLAN_INDEX,Outer VLAN Table Entry Index - Specifies the ALE Outer VLAN address lookup table index to match for the selected policing/classifier entry" newline bitfld.long 0xC 15. "IVLAN_MEN,Inner VLAN Match Enable - Enables frame Inner VLAN address match for the selected policing/classifier entry" "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "IVLAN_INDEX,Inner VLAN Table Entry Index - Specifies the ALE Inner VLAN address lookup table index to match for the selected policing/classifier entry" line.long 0x10 "CPSW_NUSS_VBUSP_POLICECFG3,The Policing Config 3 holds the match enable/match index for the Ether Type and IP Source address" bitfld.long 0x10 31. "ETHERTYPE_MEN,EtherType Match Enable - Enables frame Ether Type match for the selected policing/classifier entry" "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "ETHERTYPE_INDEX,EtherType Table Entry Index - Specifies the ALE Ether Type lookup table index to match for the selected policing/classifier entry" newline bitfld.long 0x10 15. "IPSRC_MEN,IP Source Address Match Enable - Enables frame IP Source address match for the selected policing/classifier entry" "0,1" newline hexmask.long.byte 0x10 0.--5. 1. "IPSRC_INDEX,IP Source Address Table Entry Index - Specifies the ALE IP Source address lookup table index to match for the selected policing/classifier entry" line.long 0x14 "CPSW_NUSS_VBUSP_POLICECFG4,The Policing Config 4 holds the match enable/match index for the IP Destination address" bitfld.long 0x14 31. "IPDST_MEN,IP Destination Address Match Enable - Enables frame IP Destination address match for the selected policing/classifier entry" "0,1" newline hexmask.long.byte 0x14 16.--21. 1. "IPDST_INDEX,IP Destination Address Table Entry Index - Specifies the ALE IP Destination address lookup table index to match for the selected policing/classifier entry" rgroup.long 0x3E118++0x13 line.long 0x0 "CPSW_NUSS_VBUSP_POLICECFG6,The PIR counter is a 37 bit internal counter where ~ipir_idle_inc_val is added every clock and the frame size << 18 is subtracted at EOF if not RED at LUT time. If the counter is negative the packet will be marked RED. else it.." hexmask.long 0x0 0.--31. 1. "PIR_IDLE_INC_VAL,Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle. If zero the PIR counter is disabled and packets will never be marked or processed as RED." line.long 0x4 "CPSW_NUSS_VBUSP_POLICECFG7,The CIR counter is a 37 bit internal counter where ~icir_idle_inc_val is added every clock and the frame size << 18 is subtracted at EOF if not RED or YELLOW at LUT time. If the counter is positive the packet will be marked.." hexmask.long 0x4 0.--31. 1. "CIR_IDLE_INC_VAL,Committed Information Idle Increment Value - The number added to the CIR counter every clock cycle. If zero the CIR counter is disabled and packets will never be marked or processed as YELLOW." line.long 0x8 "CPSW_NUSS_VBUSP_POLICETBLCTL,The Policing Table Control is used to read or write the selected policing/classifier entry. The selected policing/classifier entry is only read or written after this register is written based on the value of the.." bitfld.long 0x8 31. "WRITE_ENABLE,Write Enable - Setting this bit will write the POLICECFG0-7 to the ~ipol_tbl_idx selected policing/classifier entry. Clearing this bit will read the ~ipol_tbl_idx selected policing/classifier entry into the POLICECFG0-7 registers." "0,1" newline bitfld.long 0x8 0.--2. "POL_TBL_IDX,Policer Entry Index - This field specifies the policing/classifier entry to be read or written. When writing to this field without setting the ~iwrite_enable=1 will cause the selected policing/classifier entry to be loaded into the.." "0,1,2,3,4,5,6,7" line.long 0xC "CPSW_NUSS_VBUSP_POLICECONTROL,The Control Enables color marking as well as internal ALE packet dropping rules." bitfld.long 0xC 31. "POLICING_EN,Policing Enable - Enables the policing to color the packets this also enables red or yellow drop capabilities." "0,1" newline bitfld.long 0xC 29. "RED_DROP_EN,RED Drop Enable - Enables the ALE to drop the red colored packets." "0,1" newline bitfld.long 0xC 28. "YELLOW_DROP_EN,WELLOW Drop Enable - Enables the ALE to drop yellow packets based on the ~iyellowthresh value. This field would normally not be used as to let the switch drop packets at a buffer threshold instead. In the event that the switch does not.." "0,1" newline bitfld.long 0xC 24.--26. "YELLOWTHRESH,Yellow Threshold - When set enables a portion of the yellow packets to be dropped based on the ~iyellow_drop_en enable. 0-100% 1=50% 2-33% 3-25% 4=20% 5-17% 6-14% 7-13%" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 22.--23. "POLMCHMODE,Policing Match Mode - This field determines what happens to packets that fail to hit any policing/classifier entry. 0 - No Hit packets are marked GREEN 1 - No Hit packets are marked YELLOW 2 - No Hit packets are marked RED 3 - No Hit.." "0: No Hit packets are marked GREEN 1,?,2: No Hit packets are marked RED 3,?" newline bitfld.long 0xC 21. "PRIORITY_THREAD_EN,Priority Thread Enable - This field determines if priority is OR'd to the default thread when no classifiers hit and the default thread is enabled." "0,1" newline bitfld.long 0xC 20. "MAC_ONLY_DEF_DIS,MAC Only Default Disable - This field when set disables the default thread on MAC Only Ports. That is the default thread will be {port priority}. If the traffic matches a classifier with a thread mapping the classifier thread mapping.." "0,1" line.long 0x10 "CPSW_NUSS_VBUSP_POLICETESTCTL,The Policing Test Control enables the ability to determine which policing entry has been hit and whether they reported a red or yellow rate condition." bitfld.long 0x10 31. "POL_CLRALL_HIT,Policer Clear - This bit clears all the policing/classifier hit bits. This bit is self clearing. This can be used to test the fact that a policing/classifier entry has been hit." "0,1" newline bitfld.long 0x10 30. "POL_CLRALL_REDHIT,Policer Clear RED - This bit clears all the policing/classifier RED hit bits. This bit is self clearing. This can be used to test the fact that a policing/classifier entry has been hit during a RED condition." "0,1" newline bitfld.long 0x10 29. "POL_CLRALL_YELLOWHIT,Policer Clear YELLOW - This bit clears all the policing/classifier YELLOW hit bits. This bit is self clearing. This can be used to test the fact that a policing/classifier entry has been hit during a YELLOW condition." "0,1" newline bitfld.long 0x10 28. "POL_CLRSEL_ALL,Police Clear Selected - This bit clears the selected policing/classifier hit redhit and yellowhit bits. This bit is self clearing." "0,1" newline bitfld.long 0x10 0.--2. "POL_TEST_IDX,Policer Test Index - This field selects which policing/classifier hit bits will be read or written." "0,1,2,3,4,5,6,7" rgroup.long 0x3E12C++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_POLICEHSTAT,The policing hit status is a read only register that reads the hit bits of the selected policing/classifier." bitfld.long 0x0 31. "POL_HIT,Policer Hit - This indicates that the selected policing/classifier via the ~ipol_test_idx field has been hit by a packet seen on any port that matches the policing/classifier entry match." "0,1" newline bitfld.long 0x0 30. "POL_REDHIT,Policer Hit RED - This indicates that the selected policing/classifier via the ~ipol_test_idx field has been hit during a RED condition by a packet seen on any port that matches the policing/classifier entry match." "0,1" newline bitfld.long 0x0 29. "POL_YELLOWHIT,Policer Hit YELLOW - This indicates that the selected policing/classifier via the ~ipol_test_idx field has been hit during a YELLOW condition by a packet seen on any port that matches the policing/classifier entry match." "0,1" rgroup.long 0x3E134++0xB line.long 0x0 "CPSW_NUSS_VBUSP_THREADMAPDEF,The THREAD Mapping Default Value register is used to set the default thread ID when no classifier is matched." bitfld.long 0x0 15. "DEFTHREAD_EN,Default Tread Enable - When set the switch will use the ~idefthreadval for the host interface thread ID if no classifier is matched. If clear the switch will generate its own thread ID based on port and priority if there is no classifier.." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "DEFTHREADVAL,Default Thread Value - This field specifies the default thread ID value." line.long 0x4 "CPSW_NUSS_VBUSP_THREADMAPCTL,The THREAD Mapping Control register allows the highest matched classifier to return a particular thread ID for traffic sent to the host. This allows particular classifier matched traffic to be placed an a particular hosts.." bitfld.long 0x4 0.--2. "CLASSINDEX,Classifier Index - This is the classifier index entry that the thread enable and thread value will be read or written by the ~bTHREADMAPVAL register." "0,1,2,3,4,5,6,7" line.long 0x8 "CPSW_NUSS_VBUSP_THREADMAPVAL,The THREAD Mapping Value register is used to set the thread ID for a particular classifier entry." bitfld.long 0x8 15. "THREAD_EN,Thread Enable - When set the switch will use the ~ithreadval for the selected classifier match. If clear the the thread ID will be determined by the ~bTHREADMAPDEF register settings." "0,1" newline hexmask.long.byte 0x8 0.--5. 1. "THREADVAL,Thread Value - This field is the thread ID value that is used to map a classifier hit to thread ID for host traffic." rgroup.long 0x3D0E0++0x1B line.long 0x0 "CPSW_NUSS_VBUSP_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value" line.long 0x4 "CPSW_NUSS_VBUSP_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value" line.long 0x8 "CPSW_NUSS_VBUSP_CONTROL_REG,Time Stamp Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1" newline bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1" line.long 0xC "CPSW_NUSS_VBUSP_LENGTH_REG,Time Stamp Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value" line.long 0x10 "CPSW_NUSS_VBUSP_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value" line.long 0x14 "CPSW_NUSS_VBUSP_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value" line.long 0x18 "CPSW_NUSS_VBUSP_NUDGE_REG,Time Stamp Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value" rgroup.long 0x3D200++0x1B line.long 0x0 "CPSW_NUSS_VBUSP_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp ESTF Generate Function Comparison Low Value" line.long 0x4 "CPSW_NUSS_VBUSP_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp ESTF Generate Function Comparison High Value" line.long 0x8 "CPSW_NUSS_VBUSP_CONTROL_REG,Time Stamp ESTF Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1" newline bitfld.long 0x8 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1" line.long 0xC "CPSW_NUSS_VBUSP_LENGTH_REG,Time Stamp ESTF Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp ESTF Generate Function Length Value" line.long 0x10 "CPSW_NUSS_VBUSP_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp ESTF Generate Function PPM Low Value" line.long 0x14 "CPSW_NUSS_VBUSP_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value" line.long 0x18 "CPSW_NUSS_VBUSP_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value" tree.end tree "CPSW_PSILSS0_MMRS (CPSW_PSILSS0_MMRS)" base ad:0x3404000 rgroup.long 0x0++0x7 line.long 0x0 "MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." rgroup.long 0x10++0x3 line.long 0x0 "MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." rgroup.long 0x40++0x3 line.long 0x0 "MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end tree.end tree "csi" base ad:0x0 tree "CSI_PSILSS0_MMRS (CSI_PSILSS0_MMRS)" base ad:0x3410000 rgroup.long 0x0++0x7 line.long 0x0 "MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." rgroup.long 0x10++0x3 line.long 0x0 "MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." rgroup.long 0x40++0x3 line.long 0x0 "MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end tree "csi_rx" tree "csi_rx_if0" tree "csi_rx_if0_CP_INTD_CFG_INTD_CFG (csi_rx_if0_CP_INTD_CFG_INTD_CFG)" base ad:0x4508000 rgroup.long 0x0++0x3 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_REVISION,Revision Register" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTLVER,RTL revisions" newline bitfld.long 0x0 8.--10. "MAJREV,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_eoi_reg,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector" rgroup.long 0x14++0x3 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg,Interrupt Vector Register" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR,Interrupt Vector Register" rgroup.long 0x100++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_0,Enable Register 0" bitfld.long 0x0 4. "ENABLE_LEVEL_EN_INT_VP1_ERROVERFLOW,Enable Set for level_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x0 3. "ENABLE_LEVEL_EN_INT_VP1_ERRINLNFRM,Enable Set for level_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x0 2. "ENABLE_LEVEL_EN_INT_VP0_ERROVERFLOW,Enable Set for level_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x0 1. "ENABLE_LEVEL_EN_INT_VP0_ERRINLNFRM,Enable Set for level_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x0 0. "ENABLE_LEVEL_EN_FIFO_OVERFLOW,Enable Set for level_en_fifo_overflow" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_0,Enable Register 1" bitfld.long 0x4 4. "ENABLE_PULSE_EN_INT_VP1_ERROVERFLOW,Enable Set for pulse_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x4 3. "ENABLE_PULSE_EN_INT_VP1_ERRINLNFRM,Enable Set for pulse_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x4 2. "ENABLE_PULSE_EN_INT_VP0_ERROVERFLOW,Enable Set for pulse_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x4 1. "ENABLE_PULSE_EN_INT_VP0_ERRINLNFRM,Enable Set for pulse_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x4 0. "ENABLE_PULSE_EN_FIFO_OVERFLOW,Enable Set for pulse_en_fifo_overflow" "0,1" rgroup.long 0x300++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_0,Enable Clear Register 0" bitfld.long 0x0 4. "ENABLE_LEVEL_EN_INT_VP1_ERROVERFLOW_CLR,Enable Clear for level_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x0 3. "ENABLE_LEVEL_EN_INT_VP1_ERRINLNFRM_CLR,Enable Clear for level_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x0 2. "ENABLE_LEVEL_EN_INT_VP0_ERROVERFLOW_CLR,Enable Clear for level_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x0 1. "ENABLE_LEVEL_EN_INT_VP0_ERRINLNFRM_CLR,Enable Clear for level_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x0 0. "ENABLE_LEVEL_EN_FIFO_OVERFLOW_CLR,Enable Clear for level_en_fifo_overflow" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_0,Enable Clear Register 1" bitfld.long 0x4 4. "ENABLE_PULSE_EN_INT_VP1_ERROVERFLOW_CLR,Enable Clear for pulse_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x4 3. "ENABLE_PULSE_EN_INT_VP1_ERRINLNFRM_CLR,Enable Clear for pulse_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x4 2. "ENABLE_PULSE_EN_INT_VP0_ERROVERFLOW_CLR,Enable Clear for pulse_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x4 1. "ENABLE_PULSE_EN_INT_VP0_ERRINLNFRM_CLR,Enable Clear for pulse_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x4 0. "ENABLE_PULSE_EN_FIFO_OVERFLOW_CLR,Enable Clear for pulse_en_fifo_overflow" "0,1" rgroup.long 0x500++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_0,Status Register 0" bitfld.long 0x0 4. "STATUS_LEVEL_INT_VP1_ERROVERFLOW,Status write 1 to set for level_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x0 3. "STATUS_LEVEL_INT_VP1_ERRINLNFRM,Status write 1 to set for level_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x0 2. "STATUS_LEVEL_INT_VP0_ERROVERFLOW,Status write 1 to set for level_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x0 1. "STATUS_LEVEL_INT_VP0_ERRINLNFRM,Status write 1 to set for level_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x0 0. "STATUS_LEVEL_FIFO_OVERFLOW,Status write 1 to set for level_en_fifo_overflow" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_0,Status Register 1" bitfld.long 0x4 4. "STATUS_PULSE_INT_VP1_ERROVERFLOW,Status write 1 to set for pulse_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x4 3. "STATUS_PULSE_INT_VP1_ERRINLNFRM,Status write 1 to set for pulse_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x4 2. "STATUS_PULSE_INT_VP0_ERROVERFLOW,Status write 1 to set for pulse_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x4 1. "STATUS_PULSE_INT_VP0_ERRINLNFRM,Status write 1 to set for pulse_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x4 0. "STATUS_PULSE_FIFO_OVERFLOW,Status write 1 to set for pulse_en_fifo_overflow" "0,1" rgroup.long 0x700++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_0,Status Clear Register 0" bitfld.long 0x0 4. "STATUS_LEVEL_INT_VP1_ERROVERFLOW_CLR,Status write 1 to clear for level_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x0 3. "STATUS_LEVEL_INT_VP1_ERRINLNFRM_CLR,Status write 1 to clear for level_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x0 2. "STATUS_LEVEL_INT_VP0_ERROVERFLOW_CLR,Status write 1 to clear for level_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x0 1. "STATUS_LEVEL_INT_VP0_ERRINLNFRM_CLR,Status write 1 to clear for level_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x0 0. "STATUS_LEVEL_FIFO_OVERFLOW_CLR,Status write 1 to clear for level_en_fifo_overflow" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_0,Status Clear Register 1" bitfld.long 0x4 4. "STATUS_PULSE_INT_VP1_ERROVERFLOW_CLR,Status write 1 to clear for pulse_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x4 3. "STATUS_PULSE_INT_VP1_ERRINLNFRM_CLR,Status write 1 to clear for pulse_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x4 2. "STATUS_PULSE_INT_VP0_ERROVERFLOW_CLR,Status write 1 to clear for pulse_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x4 1. "STATUS_PULSE_INT_VP0_ERRINLNFRM_CLR,Status write 1 to clear for pulse_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x4 0. "STATUS_PULSE_FIFO_OVERFLOW_CLR,Status write 1 to clear for pulse_en_fifo_overflow" "0,1" rgroup.long 0xA80++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_level,Interrupt Vector for level" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR_LEVEL,Interrupt Vector" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_pulse,Interrupt Vector for pulse" hexmask.long 0x4 0.--31. 1. "INTR_VECTOR_PULSE,Interrupt Vector" tree.end tree "csi_rx_if0_ECC_AGGR_CFG (csi_rx_if0_ECC_AGGR_CFG)" base ad:0x2A30000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 7. "VP1_FIFO_RAMECC_PEND,Interrupt Pending Status for vp1_fifo_ramecc_pend" "0,1" bitfld.long 0x4 6. "VP0_FIFO_RAMECC_PEND,Interrupt Pending Status for vp0_fifo_ramecc_pend" "0,1" bitfld.long 0x4 5. "RAM_RAMECC3_PEND,Interrupt Pending Status for ram_ramecc3_pend" "0,1" newline bitfld.long 0x4 4. "RAM_RAMECC2_PEND,Interrupt Pending Status for ram_ramecc2_pend" "0,1" bitfld.long 0x4 3. "RAM_RAMECC1_PEND,Interrupt Pending Status for ram_ramecc1_pend" "0,1" bitfld.long 0x4 2. "RAM_RAMECC0_PEND,Interrupt Pending Status for ram_ramecc0_pend" "0,1" newline bitfld.long 0x4 1. "PSIL_FIFO_RAMECC_PEND,Interrupt Pending Status for psil_fifo_ramecc_pend" "0,1" bitfld.long 0x4 0. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 7. "VP1_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp1_fifo_ramecc_pend" "0,1" bitfld.long 0x0 6. "VP0_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp0_fifo_ramecc_pend" "0,1" bitfld.long 0x0 5. "RAM_RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc3_pend" "0,1" newline bitfld.long 0x0 4. "RAM_RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc2_pend" "0,1" bitfld.long 0x0 3. "RAM_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc1_pend" "0,1" bitfld.long 0x0 2. "RAM_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc0_pend" "0,1" newline bitfld.long 0x0 1. "PSIL_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for psil_fifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 7. "VP1_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp1_fifo_ramecc_pend" "0,1" bitfld.long 0x0 6. "VP0_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp0_fifo_ramecc_pend" "0,1" bitfld.long 0x0 5. "RAM_RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc3_pend" "0,1" newline bitfld.long 0x0 4. "RAM_RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc2_pend" "0,1" bitfld.long 0x0 3. "RAM_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc1_pend" "0,1" bitfld.long 0x0 2. "RAM_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc0_pend" "0,1" newline bitfld.long 0x0 1. "PSIL_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for psil_fifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 7. "VP1_FIFO_RAMECC_PEND,Interrupt Pending Status for vp1_fifo_ramecc_pend" "0,1" bitfld.long 0x4 6. "VP0_FIFO_RAMECC_PEND,Interrupt Pending Status for vp0_fifo_ramecc_pend" "0,1" bitfld.long 0x4 5. "RAM_RAMECC3_PEND,Interrupt Pending Status for ram_ramecc3_pend" "0,1" newline bitfld.long 0x4 4. "RAM_RAMECC2_PEND,Interrupt Pending Status for ram_ramecc2_pend" "0,1" bitfld.long 0x4 3. "RAM_RAMECC1_PEND,Interrupt Pending Status for ram_ramecc1_pend" "0,1" bitfld.long 0x4 2. "RAM_RAMECC0_PEND,Interrupt Pending Status for ram_ramecc0_pend" "0,1" newline bitfld.long 0x4 1. "PSIL_FIFO_RAMECC_PEND,Interrupt Pending Status for psil_fifo_ramecc_pend" "0,1" bitfld.long 0x4 0. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 7. "VP1_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp1_fifo_ramecc_pend" "0,1" bitfld.long 0x0 6. "VP0_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp0_fifo_ramecc_pend" "0,1" bitfld.long 0x0 5. "RAM_RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc3_pend" "0,1" newline bitfld.long 0x0 4. "RAM_RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc2_pend" "0,1" bitfld.long 0x0 3. "RAM_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc1_pend" "0,1" bitfld.long 0x0 2. "RAM_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc0_pend" "0,1" newline bitfld.long 0x0 1. "PSIL_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for psil_fifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 7. "VP1_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp1_fifo_ramecc_pend" "0,1" bitfld.long 0x0 6. "VP0_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp0_fifo_ramecc_pend" "0,1" bitfld.long 0x0 5. "RAM_RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc3_pend" "0,1" newline bitfld.long 0x0 4. "RAM_RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc2_pend" "0,1" bitfld.long 0x0 3. "RAM_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc1_pend" "0,1" bitfld.long 0x0 2. "RAM_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc0_pend" "0,1" newline bitfld.long 0x0 1. "PSIL_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for psil_fifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "csi_rx_if0_RX_SHIM_VBUSP_MMR_CSI2RXIF (csi_rx_if0_RX_SHIM_VBUSP_MMR_CSI2RXIF)" base ad:0x4500000 rgroup.long 0x0++0x3 line.long 0x0 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_csirx_id,nothing" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" newline bitfld.long 0x0 8.--10. "MAJREV,major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom revision" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,min revision" rgroup.long 0x8++0xB line.long 0x0 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_vp0,Video Port 0 configuration" bitfld.long 0x0 31. "EN_CFG,Video Port enable. Disable:drops pixel data Enable: start on VS captures and sends frame data. Will force ih and iw size by zero pad or trunc. When 1 prevents writing rest of fields in this register." "0,1" hexmask.long.word 0x0 16.--28. 1. "IH_CFG,(U13) input height in units of lines. Only writable when vp0_en_cfg=0. writes blockes when vp0_en_cfg=1" hexmask.long.word 0x0 0.--12. 1. "IW_CFG,(U13) input width in units of RAW data samples. Max usable value determined by populated line buffer RAM size. Only writable when vp0_en_cfg=0. writes blockes when vp0_en_cfg=1. You should read this value first and if set to 0 then you should.." line.long 0x4 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_vp1,Video Port 1 configuration" bitfld.long 0x4 31. "EN_CFG,Video Port enable. Disable:drops pixel data Enable: start on VS captures and sends frame data. Will force ih and iw size by zero pad or trunc. When 1 prevents writing rest of fields in this register." "0,1" hexmask.long.word 0x4 16.--28. 1. "IH_CFG,(U13) input height in units of lines. Only writable when vp0_en_cfg=0. writes blovkes when vp1_en_cfg=1" hexmask.long.word 0x4 0.--12. 1. "IW_CFG,(U13) input width in units of RAW data samples. Max usable value determined by populated line buffer RAM size. Only writable when vp1_en_cfg=0. writes blockes when vp1_en_cfg=1. You should read this value first and if set to 0 then you should.." line.long 0x8 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_cntl,control register for csi rx wrapper" rbitfld.long 0x8 11. "STREAM3_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1" rbitfld.long 0x8 10. "STREAM2_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1" rbitfld.long 0x8 9. "STREAM1_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1" rbitfld.long 0x8 8. "STREAM0_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1" newline bitfld.long 0x8 0. "PIXEL_RESET,reset for the pixeal interface. 0-reset 1 not in reset. this shoud be asserted till after you program the csi controller configuration registers" "0: reset,?" rgroup.long 0x20++0xB line.long 0x0 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_dmaCntx,DMA Channel Context. Configuration for each of 32 possible channel contexts. Illegal to program 2 chanCntx with same extraction values." bitfld.long 0x0 31. "EN_CFG,DMA context is enabled. Will extract channel if input matches dataType and VirtualChan" "0,1" bitfld.long 0x0 29. "RSV0,reserved" "0,1" bitfld.long 0x0 26.--27. "YUV422_MODE_CFG,yuv422 mode 00:UYVY 01:VYUY 10:YUYV 11:YVYU" "0: UYVY,1: VYUY,?,?" bitfld.long 0x0 24. "DUAL_PCK_CFG,dual packed format extraction for 8 bits or less" "0,1" newline bitfld.long 0x0 20.--21. "SIZE_CFG,data size shift when unpacking 00=8 01=16 10=32 11=RSVD" "0,1,2,3" bitfld.long 0x0 18. "PCK12_CFG,12-bit packing enable" "0,1" hexmask.long.byte 0x0 6.--9. 1. "VIRTCH_CFG,CSI virtual channel index. Supplied by MIPI CSI protocol to DPHY. For CSIver1.3 program 2MSb==0" hexmask.long.byte 0x0 0.--5. 1. "DATTYP_CFG,CSI data type index. Supplied by MIPI CSI protocol to DPHY" line.long 0x4 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_psi_cfg0,psi configuration register0" hexmask.long.word 0x4 16.--31. 1. "DST_TAG,psi dst tag" hexmask.long.word 0x4 0.--15. 1. "SRC_TAG,psi source tag" line.long 0x8 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_psi_cfg1,psi configuration register1" hexmask.long.byte 0x8 8.--11. 1. "PS_FLAGS,ps flags" hexmask.long.byte 0x8 0.--4. 1. "PKT_TYPE,psi packet type" tree.end tree "csi_rx_if0_VBUS2APB_WRAP_VBUSP_APB_CSI2RX (csi_rx_if0_VBUS2APB_WRAP_VBUSP_APB_CSI2RX)" base ad:0x4504000 rgroup.long 0x0++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_device_config,This register provides information related to the current configuration." bitfld.long 0x0 31. "STREAM3_MONITOR_PRESENT,Pixel stream 3 Monitor present 1 = implemented" "?,1: implemented" newline bitfld.long 0x0 29.--30. "STREAM3_NUM_PIXELS,The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be output in a single cycle. Default will be 1 pixel per clock. 00 -> 1.." "0,1,2,3" newline bitfld.long 0x0 27.--28. "STREAM3_FIFO_MODE,Stream 3 FIFO Mode." "0,1,2,3" newline bitfld.long 0x0 26. "STREAM2_MONITOR_PRESENT,Pixel stream 2 Monitor present 1 = implemented" "?,1: implemented" newline bitfld.long 0x0 24.--25. "STREAM2_NUM_PIXELS,The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be output in a single cycle. Default will be 1 pixel per clock. 00 -> 1.." "0,1,2,3" newline bitfld.long 0x0 22.--23. "STREAM2_FIFO_MODE,Stream 2 FIFO Mode." "0,1,2,3" newline bitfld.long 0x0 21. "STREAM1_MONITOR_PRESENT,Pixel stream 1 Monitor present 1 = implemented" "?,1: implemented" newline bitfld.long 0x0 19.--20. "STREAM1_NUM_PIXELS,The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be output in a single cycle. Default will be 1 pixel per clock. 00 -> 1.." "0,1,2,3" newline bitfld.long 0x0 17.--18. "STREAM1_FIFO_MODE,Stream 1 FIFO Mode." "0,1,2,3" newline bitfld.long 0x0 16. "STREAM0_MONITOR_PRESENT,Pixel stream 0 Monitor present 1 = implemented" "?,1: implemented" newline bitfld.long 0x0 14.--15. "STREAM0_NUM_PIXELS,The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be output in a single cycle. Default will be 1 pixel per clock. 00 -> 1.." "0,1,2,3" newline bitfld.long 0x0 12.--13. "STREAM0_FIFO_MODE,Stream 0 FIFO Mode." "0,1,2,3" newline bitfld.long 0x0 10. "ASF_CONFIG,Additional Safety Features [ASF] Configuration: 0 = None; 1 = Full ASF." "0: None;,1: Full ASF" newline bitfld.long 0x0 9. "VCX_CONFIG,Extended Virtual Channel [VCX] Configuration: 0 = 4 VCs; 1 = 16 VCs" "0,1" newline bitfld.long 0x0 7.--8. "DATAPATH_SIZE,Internal Datapath width 00 - 32 bit 01 - 64bit 10 - 16 bit 11 - 8 Bits." "0,1,2,3" newline bitfld.long 0x0 4.--6. "NUM_STREAMS,Number of Stream interfaces [1-4]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "CDNS_PHY_PRESENT,Cadence DPDHY present 1 = Yes" "?,1: Yes" newline bitfld.long 0x0 0.--2. "MAX_LANE_NB,Max Number of Lanes [1-4]" "0,1,2,3,4,5,6,7" rgroup.long 0x4++0x7 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_soft_reset,CSI2 Slave Controller Individual Soft Reset for Front and Protocol blocks." bitfld.long 0x0 1. "PROTOCOL,writing 1'b1 will apply a synchronous soft reset to the protocol module" "0,1" newline bitfld.long 0x0 0. "FRONT,writing 1'b1 will apply a synchronous soft reset to the Front module" "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_static_cfg,Configuration register to set the physical/logical DPHY lane mapping." bitfld.long 0x4 28.--30. "DL3_MAP,physical mapping of logical data lane 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 24.--26. "DL2_MAP,physical mapping of logical data lane 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20.--22. "DL1_MAP,physical mapping of logical data lane 1." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16.--18. "DL0_MAP,physical mapping of logical data lane 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "LANE_NB,The number of lanes" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4. "V2P0_SUPPORT_ENABLE,Support extended VC up to 16 virtual channels [4-bits] and RAW16/20. as per CSI2RX v2.0. Default is up to 4 virtual channels [3-bits] as per CSI2RX v1.3" "0,1" newline bitfld.long 0x4 0.--1. "SEL,selection of DPHY used as input of CSI2RX module" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_bypass_cfg,Error detection event flag configuration." bitfld.long 0x0 2. "DATA_ID,Enables Data ID error bypass for stream outputs. When enabled Data ID errors in packets are signalled as interrupt events however the data is still passed to the pixel/packed data outputs. The system must decide to.." "0,1" newline bitfld.long 0x0 1. "ECC,Enables ECC error bypass for stream outputs. When enabled CRC errors in packets are signalled as interrupt events however the data is still passed to the pixel/packed data outputs. The system must decide to mask of use the.." "0,1" newline bitfld.long 0x0 0. "CRC,Enables CRC error bypass for stream outputs. When enabled CRC errors in packets are signalled as interrupt events however the data is still passed to the pixel/packed data outputs. The system must decide to mask of use the.." "0,1" rgroup.long 0x18++0x17 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_monitor_irqs,Information type Interrupt status (non-error conditions)" bitfld.long 0x0 31. "STREAM3_LINE_CNT_ERROR_IRQ,Stream 3 Line count error interrupt" "0,1" newline bitfld.long 0x0 30. "STREAM3_FRAME_MISMATCH_IRQ,Stream 3 Frame mismatch error interrupt" "0,1" newline bitfld.long 0x0 29. "STREAM3_FRAME_CNT_ERROR_IRQ,Stream 3 Frame count error interrupt" "0,1" newline bitfld.long 0x0 28. "STREAM3_FCC_STOP_IRQ,Stream 3 FCC stop interrupt" "0,1" newline bitfld.long 0x0 27. "STREAM3_FCC_START_IRQ,Stream 3 FCC start interrupt" "0,1" newline bitfld.long 0x0 26. "STREAM3_FRAME_IRQ,Stream 3 Frame interrupt" "0,1" newline bitfld.long 0x0 25. "STREAM3_LB_IRQ,Stream 3 Line/byte interrupt" "0,1" newline bitfld.long 0x0 24. "STREAM3_TIMER_IRQ,Stream 3 Timer interrupt" "0,1" newline bitfld.long 0x0 23. "STREAM2_LINE_CNT_ERROR_IRQ,Stream 2 Line count error interrupt" "0,1" newline bitfld.long 0x0 22. "STREAM2_FRAME_MISMATCH_IRQ,Stream 2 Frame mismatch error interrupt" "0,1" newline bitfld.long 0x0 21. "STREAM2_FRAME_CNT_ERROR_IRQ,Stream 2 Frame count error interrupt" "0,1" newline bitfld.long 0x0 20. "STREAM2_FCC_STOP_IRQ,Stream 2 FCC stop interrupt" "0,1" newline bitfld.long 0x0 19. "STREAM2_FCC_START_IRQ,Stream 2 FCC start interrupt" "0,1" newline bitfld.long 0x0 18. "STREAM2_FRAME_IRQ,Stream 2 Frame interrupt" "0,1" newline bitfld.long 0x0 17. "STREAM2_LB_IRQ,Stream 2 Line/byte interrupt" "0,1" newline bitfld.long 0x0 16. "STREAM2_TIMER_IRQ,Stream 2 Timer interrupt" "0,1" newline bitfld.long 0x0 15. "STREAM1_LINE_CNT_ERROR_IRQ,Stream 1 Line count error interrupt" "0,1" newline bitfld.long 0x0 14. "STREAM1_FRAME_MISMATCH_IRQ,Stream 1 Frame mismatch error interrupt" "0,1" newline bitfld.long 0x0 13. "STREAM1_FRAME_CNT_ERROR_IRQ,Stream 1 Frame count error interrupt" "0,1" newline bitfld.long 0x0 12. "STREAM1_FCC_STOP_IRQ,Stream 1 FCC stop interrupt" "0,1" newline bitfld.long 0x0 11. "STREAM1_FCC_START_IRQ,Stream 1 FCC start interrupt" "0,1" newline bitfld.long 0x0 10. "STREAM1_FRAME_IRQ,Stream 1 Frame interrupt" "0,1" newline bitfld.long 0x0 9. "STREAM1_LB_IRQ,Stream 1 Line/byte interrupt" "0,1" newline bitfld.long 0x0 8. "STREAM1_TIMER_IRQ,Stream 1 Timer interrupt" "0,1" newline bitfld.long 0x0 7. "STREAM0_LINE_CNT_ERROR_IRQ,Stream 0 Line count error interrupt" "0,1" newline bitfld.long 0x0 6. "STREAM0_FRAME_MISMATCH_IRQ,Stream 0 Frame mismatch error interrupt" "0,1" newline bitfld.long 0x0 5. "STREAM0_FRAME_CNT_ERROR_IRQ,Stream 0 Frame count error interrupt" "0,1" newline bitfld.long 0x0 4. "STREAM0_FCC_STOP_IRQ,Stream 0 FCC stop interrupt" "0,1" newline bitfld.long 0x0 3. "STREAM0_FCC_START_IRQ,Stream 0 FCC start interrupt" "0,1" newline bitfld.long 0x0 2. "STREAM0_FRAME_IRQ,Stream 0 Frame interrupt" "0,1" newline bitfld.long 0x0 1. "STREAM0_LB_IRQ,Stream 0 Line/byte interrupt" "0,1" newline bitfld.long 0x0 0. "STREAM0_TIMER_IRQ,Stream 0 Timer interrupt" "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_monitor_irqs_mask_cfg,Monitor interrupt mask. Bit addressable mask register in order to independently enable" bitfld.long 0x4 31. "STREAM3_LINE_CNT_ERROR_IRQM,Interrupt mask for stream 3 Line count error." "0,1" newline bitfld.long 0x4 30. "STREAM3_FRAME_MISMATCH_IRQM,Interrupt mask for stream 3 Frame mismatch error." "0,1" newline bitfld.long 0x4 29. "STREAM3_FRAME_CNT_ERROR_IRQM,Interrupt mask for stream 3 Frame count error." "0,1" newline bitfld.long 0x4 28. "STREAM3_FCC_STOP_IRQM,Interrupt mask for stream 3 FCC stop." "0,1" newline bitfld.long 0x4 27. "STREAM3_FCC_START_IRQM,Interrupt mask for stream 3 FCC start." "0,1" newline bitfld.long 0x4 26. "STREAM3_FRAME_IRQM,Interrupt mask for stream 3 Frame." "0,1" newline bitfld.long 0x4 25. "STREAM3_LB_IRQM,Interrupt mask for stream 3 Line/byte." "0,1" newline bitfld.long 0x4 24. "STREAM3_TIMER_IRQM,Interrupt mask stream 3 Timer" "0,1" newline bitfld.long 0x4 23. "STREAM2_LINE_CNT_ERROR_IRQM,Interrupt mask for stream 2 Line count error." "0,1" newline bitfld.long 0x4 22. "STREAM2_FRAME_MISMATCH_IRQM,Interrupt mask for stream 2 Frame mismatch error." "0,1" newline bitfld.long 0x4 21. "STREAM2_FRAME_CNT_ERROR_IRQM,Interrupt mask for stream 2 Frame count error." "0,1" newline bitfld.long 0x4 20. "STREAM2_FCC_STOP_IRQM,Interrupt mask for stream 2 FCC stop." "0,1" newline bitfld.long 0x4 19. "STREAM2_FCC_START_IRQM,Interrupt mask for stream 2 FCC start." "0,1" newline bitfld.long 0x4 18. "STREAM2_FRAME_IRQM,Interrupt mask for stream 2 Frame." "0,1" newline bitfld.long 0x4 17. "STREAM2_LB_IRQM,Interrupt mask for stream 2 Line/byte." "0,1" newline bitfld.long 0x4 16. "STREAM2_TIMER_IRQM,Interrupt mask stream 2 Timer" "0,1" newline bitfld.long 0x4 15. "STREAM1_LINE_CNT_ERROR_IRQM,Interrupt mask for stream 1 Line count error." "0,1" newline bitfld.long 0x4 14. "STREAM1_FRAME_MISMATCH_IRQM,Interrupt mask for stream 1 Frame mismatch error." "0,1" newline bitfld.long 0x4 13. "STREAM1_FRAME_CNT_ERROR_IRQM,Interrupt mask for stream 1 Frame count error." "0,1" newline bitfld.long 0x4 12. "STREAM1_FCC_STOP_IRQM,Interrupt mask for stream 1 FCC stop." "0,1" newline bitfld.long 0x4 11. "STREAM1_FCC_START_IRQM,Interrupt mask for stream 1 FCC start." "0,1" newline bitfld.long 0x4 10. "STREAM1_FRAME_IRQM,Interrupt mask for stream 1 Frame." "0,1" newline bitfld.long 0x4 9. "STREAM1_LB_IRQM,Interrupt mask for stream 1 Line/byte." "0,1" newline bitfld.long 0x4 8. "STREAM1_TIMER_IRQM,Interrupt mask stream 1 Timer" "0,1" newline bitfld.long 0x4 7. "STREAM0_LINE_CNT_ERROR_IRQM,Interrupt mask for stream 0 Line count error." "0,1" newline bitfld.long 0x4 6. "STREAM0_FRAME_MISMATCH_IRQM,Interrupt mask for stream 0 Frame mismatch error." "0,1" newline bitfld.long 0x4 5. "STREAM0_FRAME_CNT_ERROR_IRQM,Interrupt mask for stream 0 Frame count error." "0,1" newline bitfld.long 0x4 4. "STREAM0_FCC_STOP_IRQM,Interrupt mask for stream 0 FCC stop." "0,1" newline bitfld.long 0x4 3. "STREAM0_FCC_START_IRQM,Interrupt mask for stream 0 FCC start." "0,1" newline bitfld.long 0x4 2. "STREAM0_FRAME_IRQM,Interrupt mask for stream 0 Frame." "0,1" newline bitfld.long 0x4 1. "STREAM0_LB_IRQM,Interrupt mask for stream 0 Line/byte." "0,1" newline bitfld.long 0x4 0. "STREAM0_TIMER_IRQM,Interrupt mask stream 0 Timer" "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_info_irqs,Information type Interrupt status (non-error conditions)" bitfld.long 0x8 14. "STREAM3_ABORT_IRQ,Stream 3 Abort process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 13. "STREAM3_STOP_IRQ,Stream 3 Stop process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 12. "STREAM2_ABORT_IRQ,Stream 2 Abort process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 11. "STREAM2_STOP_IRQ,Stream 2 Stop process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 10. "STREAM1_ABORT_IRQ,Stream 1 Abort process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 9. "STREAM1_STOP_IRQ,Stream 1 Stop process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 8. "STREAM0_ABORT_IRQ,Stream 0 Abort process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 7. "STREAM0_STOP_IRQ,Stream 0 Stop process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 6. "SP_GENERIC_RCVD_IRQ,A generic short packet has been received." "0,1" newline bitfld.long 0x8 5. "DESKEW_ENTRY_IRQ,Either clock or any datalane has entered deskew" "0,1" newline bitfld.long 0x8 4. "ECC_SPARES_NONZERO_IRQ,Bits 7:6 of the ECC byte are non-zero. Indicates non compliance with the MIPI specification although the core will continue to operate as normal." "0,1" newline bitfld.long 0x8 3. "WAKEUP_IRQ,Wake-up interrupt." "0,1" newline bitfld.long 0x8 2. "SLEEP_IRQ,Sleep interrupt." "0,1" newline bitfld.long 0x8 1. "LP_RCVD_IRQ,Long Packet received by the protocol module" "0,1" newline bitfld.long 0x8 0. "SP_RCVD_IRQ,Short Packet received by the protocol module" "0,1" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_info_irqs_mask_cfg,Information interrupt mask. Bit addressable mask register in order to independently enable" bitfld.long 0xC 14. "STREAM3_ABORT_IRQM,Interrupt mask for stream 3 Abort process." "0,1" newline bitfld.long 0xC 13. "STREAM3_STOP_IRQM,Interrupt mask for Stream 3 Stop process complete." "0,1" newline bitfld.long 0xC 12. "STREAM2_ABORT_IRQM,Interrupt mask for stream 2 Abort process." "0,1" newline bitfld.long 0xC 11. "STREAM2_STOP_IRQM,Interrupt mask for Stream 2 Stop process complete." "0,1" newline bitfld.long 0xC 10. "STREAM1_ABORT_IRQM,Interrupt mask for stream 1 Abort process." "0,1" newline bitfld.long 0xC 9. "STREAM1_STOP_IRQM,Interrupt mask for Stream 1 Stop process complete." "0,1" newline bitfld.long 0xC 8. "STREAM0_ABORT_IRQM,Interrupt mask for stream 0 Abort process." "0,1" newline bitfld.long 0xC 7. "STREAM0_STOP_IRQM,Interrupt mask for Stream 0 Stop process complete." "0,1" newline bitfld.long 0xC 6. "SP_GENERIC_RCVD_IRQM,Interrupt mask for Generic Short Packet received" "0,1" newline bitfld.long 0xC 5. "DESKEW_ENTRY_IRQM,Interrupt mask for Deskew entry check" "0,1" newline bitfld.long 0xC 4. "ECC_SPARES_NONZERO_IRQM,Interrupt mask for ECC spares check" "0,1" newline bitfld.long 0xC 3. "WAKEUP_IRQM,Interrupt mask for Wake-up interrupt." "0,1" newline bitfld.long 0xC 2. "SLEEP_IRQM,Interrupt mask for Sleep interrupt." "0,1" newline bitfld.long 0xC 1. "LP_RCVD_IRQM,Interrupt mask for Long Packet received flag" "0,1" newline bitfld.long 0xC 0. "SP_RCVD_IRQM,Interrupt mask for Short Packet received" "0,1" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_irqs,Datapath error interrupt status." bitfld.long 0x10 19. "STREAM3_FIFO_OVERFLOW_IRQ,Overflow of the Stream FIFO detected: stream_fifo_overflow[19] -> Stream 3 overflow" "0,1" newline bitfld.long 0x10 18. "STREAM2_FIFO_OVERFLOW_IRQ,Overflow of the Stream FIFO detected: stream_fifo_overflow[18] -> Stream 2 overflow" "0,1" newline bitfld.long 0x10 17. "STREAM1_FIFO_OVERFLOW_IRQ,Overflow of the Stream FIFO detected: stream_fifo_overflow[17] -> Stream 1 overflow" "0,1" newline bitfld.long 0x10 16. "STREAM0_FIFO_OVERFLOW_IRQ,Overflow of the Stream FIFO detected: stream_fifo_overflow[16] -> Stream 0 overflow" "0,1" newline bitfld.long 0x10 12. "FRONT_TRUNC_HDR_IRQ,A truncated header [short or Long] has been received" "0,1" newline bitfld.long 0x10 11. "PROT_TRUNCATED_PACKET_IRQ,A truncated Long packet has been received. Too few/many bytes" "0,1" newline bitfld.long 0x10 10. "FRONT_LP_NO_PAYLOAD_IRQ,A truncated Long packet has been received. No payload" "0,1" newline bitfld.long 0x10 9. "SP_INVALID_RCVD_IRQ,A reserved or invalid short packet has been received" "0,1" newline bitfld.long 0x10 8. "INVALID_ACCESS_IRQ,Invalid access to the configuration register space." "0,1" newline bitfld.long 0x10 7. "DATA_ID_IRQ,Data ID error has been detected in the header packet" "0,1" newline bitfld.long 0x10 6. "HEADER_CORRECTED_ECC_IRQ,ECC error has been detected and corrected." "0,1" newline bitfld.long 0x10 5. "HEADER_ECC_IRQ,Unrecoverable ECC error has been detected." "0,1" newline bitfld.long 0x10 4. "PAYLOAD_CRC_IRQ,CRC error has been detected." "0,1" newline bitfld.long 0x10 0. "FRONT_FIFO_OVERFLOW_IRQ,Overflow detected in resynchronization FIFO between DPHY Lane Management and Protocol blocks. This will occur if sys_clk is not fast enough and should be increased since the byte clock frequency is fixed" "0,1" line.long 0x14 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_irqs_mask_cfg,Datapath error interrupt enable Bits. This register is used to independently enable each event" bitfld.long 0x14 19. "STREAM3_FIFO_OVERFLOW_IRQM,Interrupt enable bit for: stream_fifo_overflow[19] -> Stream 3 overflow" "0,1" newline bitfld.long 0x14 18. "STREAM2_FIFO_OVERFLOW_IRQM,Interrupt enable bit for: stream_fifo_overflow[18] -> Stream 2 overflow" "0,1" newline bitfld.long 0x14 17. "STREAM1_FIFO_OVERFLOW_IRQM,Interrupt enable bit for: stream_fifo_overflow[17] -> Stream 1 overflow" "0,1" newline bitfld.long 0x14 16. "STREAM0_FIFO_OVERFLOW_IRQM,Interrupt enable bit for: stream_fifo_overflow[16] -> Stream 0 overflow" "0,1" newline bitfld.long 0x14 12. "FRONT_TRUNC_HDR_IRQM,Interrupt enable bit for truncated hdr." "0,1" newline bitfld.long 0x14 11. "PROT_TRUNCATED_PACKET_IRQM,Interrupt enable bit for long packet payload with too many/few bytes" "0,1" newline bitfld.long 0x14 10. "FRONT_LP_NO_PAYLOAD_IRQM,Interrupt enable bit for long packet header received with no payload" "0,1" newline bitfld.long 0x14 9. "SP_INVALID_RCVD_IRQM,Interrupt enable bit for invalid short packet" "0,1" newline bitfld.long 0x14 8. "INVALID_ACCESS_IRQM,Interrupt enable bit for error_irqs_invalid_access." "0,1" newline bitfld.long 0x14 7. "DATA_ID_IRQM,Interrupt enable bit for error_irqs_data_id" "0,1" newline bitfld.long 0x14 6. "HEADER_CORRECTED_ECC_IRQM,Interrupt enable bit for error_irqs_header_corrected_ecc" "0,1" newline bitfld.long 0x14 5. "HEADER_ECC_IRQM,Interrupt enable bit for error_irqs_header_ecc" "0,1" newline bitfld.long 0x14 4. "PAYLOAD_CRC_IRQM,Interrupt enable bit for error_irqs_payload_crc" "0,1" newline bitfld.long 0x14 0. "FRONT_FIFO_OVERFLOW_IRQM,Interrupt enable bit for error_irqs_front_fifo_overflow" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_lane_control,DPHY lane control for data and clock lanes enables and resets" bitfld.long 0x0 16. "CL_RESET,DPHY Clock lane Reset" "0,1" newline bitfld.long 0x0 15. "DL3_RESET,DPHY data lane 3 Reset" "0,1" newline bitfld.long 0x0 14. "DL2_RESET,DPHY data lane 2 Reset" "0,1" newline bitfld.long 0x0 13. "DL1_RESET,DPHY data lane 1 Reset" "0,1" newline bitfld.long 0x0 12. "DL0_RESET,DPHY data lane 0 Reset" "0,1" newline bitfld.long 0x0 4. "CL_ENABLE,DPHY Clock lane Enable" "0,1" newline bitfld.long 0x0 3. "DL3_ENABLE,DPHY data lane 3 Enable" "0,1" newline bitfld.long 0x0 2. "DL2_ENABLE,DPHY data lane 2 Enable" "0,1" newline bitfld.long 0x0 1. "DL1_ENABLE,DPHY data lane 1 Enable" "0,1" newline bitfld.long 0x0 0. "DL0_ENABLE,DPHY data lane 0 Enable" "0,1" rgroup.long 0x48++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_status,DPHY Clock and Data Lane mode status" bitfld.long 0x0 22. "DL3_RXULPSESC,DPHY Data lane 3 ULPS Esc" "0,1" newline bitfld.long 0x0 21. "DL3_ULPSACTIVENOT,DPHY Data lane 3 ULPSActiveNot" "0,1" newline bitfld.long 0x0 20. "DL3_STOPSTATE,DPHY Data lane 3 Stop State" "0,1" newline bitfld.long 0x0 18. "DL2_RXULPSESC,DPHY Data lane 2 ULPS Esc" "0,1" newline bitfld.long 0x0 17. "DL2_ULPSACTIVENOT,DPHY Data lane 2 ULPSActiveNot" "0,1" newline bitfld.long 0x0 16. "DL2_STOPSTATE,DPHY Data lane 2 Stop State" "0,1" newline bitfld.long 0x0 14. "DL1_RXULPSESC,DPHY Data lane 1 ULPS Esc" "0,1" newline bitfld.long 0x0 13. "DL1_ULPSACTIVENOT,DPHY Data lane 1 ULPSActiveNot" "0,1" newline bitfld.long 0x0 12. "DL1_STOPSTATE,DPHY Data lane 1 Stop State" "0,1" newline bitfld.long 0x0 10. "DL0_RXULPSESC,DPHY Data lane 0 ULPS Esc" "0,1" newline bitfld.long 0x0 9. "DL0_ULPSACTIVENOT,DPHY Data lane 0 ULPSActiveNot" "0,1" newline bitfld.long 0x0 8. "DL0_STOPSTATE,DPHY Data lane 0 Stop State" "0,1" newline bitfld.long 0x0 2. "CL_RXULPSCLKNOT,DPHY Clock lane RxULPSClkNot" "0,1" newline bitfld.long 0x0 1. "CL_ULPSACTIVENOT,DPHY Clock lane ULPSActiveNot" "0,1" newline bitfld.long 0x0 0. "CL_STOPSTATE,DPHY Clock lane Stop State" "0,1" rgroup.long 0x4C++0x7 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_err_status_irq,DPHY error interrupt status" bitfld.long 0x0 20. "DL3_ERRSOTHS_IRQ,DPHY Data lane 3 ErrSotHS" "0,1" newline bitfld.long 0x0 16. "DL2_ERRSOTHS_IRQ,DPHY Data lane 2 ErrSotHS" "0,1" newline bitfld.long 0x0 12. "DL1_ERRSOTHS_IRQ,DPHY Data lane 1 ErrSotHS" "0,1" newline bitfld.long 0x0 8. "DL0_ERRSOTHS_IRQ,DPHY Data lane 0 ErrSotHS" "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_err_irq_mask_cfg,DPHY error interrupt status" bitfld.long 0x4 20. "DL3_ERRSOTHS_IRQM,DPHY Data lane 3 ErrSotHS mask" "0,1" newline bitfld.long 0x4 16. "DL2_ERRSOTHS_IRQM,DPHY Data lane 2 ErrSotHS mask" "0,1" newline bitfld.long 0x4 12. "DL1_ERRSOTHS_IRQM,DPHY Data lane 1 ErrSotHS mask" "0,1" newline bitfld.long 0x4 8. "DL0_ERRSOTHS_IRQM,DPHY Data lane 0 ErrSotHS mask" "0,1" rgroup.long 0x60++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_integration_debug,Used to observe the current data field. extracted by the protocol block from the last" hexmask.long.byte 0x0 28.--31. 1. "PROT_FSM_STATE,csi2rx_fsm_state 0x1: WAIT_FOR_PACKET 0x2: PAYLOAD_DATA 0x4: PACKET_FOOTER_CHECK" newline hexmask.long.byte 0x0 22.--25. 1. "PROT_VC,Protocol Virtual Channel" newline hexmask.long.byte 0x0 16.--21. 1. "PROT_DT,Protocol Datatype" newline hexmask.long.word 0x0 0.--15. 1. "PROT_WORD_COUNT,Protocol Word Count [Data Field]" rgroup.long 0x74++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_debug,Error condition debug. After an error is detected by the CSI2RX. this register indicates which virtual channel." hexmask.long.word 0x0 16.--31. 1. "DATA_FIELD,Indicates the Data Field for an invalid CRC/ECC/Data ID" newline hexmask.long.byte 0x0 6.--9. 1. "VC,Indicates the Virtual Channel for a invalid CRC/ECC/Data ID" newline hexmask.long.byte 0x0 0.--5. 1. "DT,Indicates the Data Type for a invalid CRC/ECC/Data ID" rgroup.long 0x80++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_test_generic,Generic test control and status register that controls and reads primary I/O." hexmask.long.word 0x0 16.--31. 1. "STATUS,Test status - Directly reflects after resynchronisation into the pclk domain the state of 'test_generic_status' primary inputs." newline hexmask.long.word 0x0 0.--15. 1. "CTRL,Test control - Directly controls primary outputs 'test_generic_ctrl'" rgroup.long 0x100++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_ctrl,CSI2RX Stream Data output datapath control." bitfld.long 0x0 4. "SOFT_RST,Writing 1'b1 will apply a synchronous soft reset of this stream registers/FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT,Writing 1 this register will cause the csi2rx to stop streaming on the corresponding output immediately. This may corrupt the output protocol. stream_abort_irq is generated on completion of the abort operation." "0,1" newline bitfld.long 0x0 1. "STOP,Writing 1 in this register will cause csi2rx to stop streaming on the corresponding output at the end of the current frame. If the command is issued during frame blanking then the datapath will immediately stop streaming.." "0,1" newline bitfld.long 0x0 0. "START,Writing 1 in this register enables the corresponding datapath output. It will start streaming data at the start of the next frame that complies with the output configuration. stream_status[31] running indicates when data.." "0,1" rgroup.long 0x104++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_status,CSI2 Slave Controller Status. Contains useful debug information such as" bitfld.long 0x0 31. "RUNNING,The Stream is enabled" "0,1" newline bitfld.long 0x0 8. "READY_STATE,Indicates the state of the pushback signal pixel_ready_if for this stream" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "STREAM_FSM,Output to Stream FSM states: 0x0: STREAM_IDLE 0x1: STREAM_WAIT_CTRL_DATA // Expecting control data next 0x2: STREAM_CTRL // Check contents of Ctrl packet and extract header.." newline bitfld.long 0x0 0.--1. "PROTOCOL_FSM,Input to Stream FSM states: 0x0: PROT_IDLE 0x1: PROT_WAIT_CTRL 0x2: PROT_CTRL 0x3: PROT_DATA" "0: PROT_IDLE 0x1: PROT_WAIT_CTRL 0x2: PROT_CTRL..,?,?,?" rgroup.long 0x108++0xB line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_data_cfg,Secondary CSI2 Slave Controller Data outputs configuration." hexmask.long.word 0x0 16.--31. 1. "VC_SELECT,Selection of Virtual Channels to be processed: Default '0' -> All Virtual Channels are processed vc_select0[16] -> Virtual Channel Select 0 is processed vc_select1[17] -> Virtual Channel Select 1 is processed vc_select2[18] ->.." newline bitfld.long 0x0 15. "ENABLE_DT1,Enable processing of dt1" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "DATATYPE_SELECT1,Second data type format that this stream will process" newline bitfld.long 0x0 7. "ENABLE_DT0,Enable processing of dt0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "DATATYPE_SELECT0,First data type format that this stream will process" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_cfg,Primary CSI2 Slave Controller Data pixel outputs configuration." hexmask.long.word 0x4 16.--31. 1. "FIFO_FILL,Set the FIFO_FILL_LEVEL which is used to hold data in the FIFO until this level is reached before allow data to be pulled. This setting is only used when fifo_mode is set for Large Buffer operation" newline bitfld.long 0x4 12.--14. "BPP_BYPASS,Force unpacking of any Data type as selected RAW type. 0 - No bypass 1 - unpack as RAW6 2 - unpack as RAW7 3 - unpack as RAW8 4 - unpack as RAW10 5 - unpack as.." "0: No bypass 1,?,2: unpack as RAW7 3,?,4: unpack as RAW10 5,?,6: unpack as RAW14 7,?" newline bitfld.long 0x4 8.--9. "FIFO_MODE,Stream FIFO configuration which must be set in accordance to FIFO sizing flow control and the relationship between the link and pixel interface data rates. Refer to Use Case descriptions for further guidance on FIFO sizing and.." "0: Full Line Buffer,1: Large Buffer [Fill Level Controlled],?,?" newline bitfld.long 0x4 4.--5. "NUM_PIXELS,Number of pixels to output from the stream. Valid values are 1 2 4 and 8. The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be.." "0,1,2,3" newline bitfld.long 0x4 1. "LS_LE_MODE,Enable LS/LE control of HYSNC_VALID output. By default LS and LE short packets are not required and HYSC_VALID will be generated from the start and end of payload data." "0,1" newline bitfld.long 0x4 0. "INTERFACE_MODE,Select the output configuration. Pixel = 0 [default] Packed = 1" "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_monitor_ctrl,Stream Monitor configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_LENGTH,Indicates the frame length in lines to detect truncated frames. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low. 0x0000 means truncated.." newline bitfld.long 0x8 15. "FRAME_MON_EN,Enables monitor. This bit must only be set high after the frame_mon_vc and frame_length have been set." "0,1" newline hexmask.long.byte 0x8 11.--14. 1. "FRAME_MON_VC,Indicates virtual channel for monitor. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low." newline bitfld.long 0x8 10. "TIMER_EOF,Select the starting point of the timer: 0x0: Start of Frame event on selected virtual channel 0x1: End of Frame event on selected virtual channel. This value must not change while timer_en is enabled" "0: Start of Frame event on selected virtual channel..,?" newline bitfld.long 0x8 9. "TIMER_EN,Enables timer based interrupt. This bit must only be set high after the timer_eof and timer_vc have been set." "0,1" newline hexmask.long.byte 0x8 5.--8. 1. "TIMER_VC,Indicates which VC should be used to generate timer based interrupt. This value must not change while timer_en is enabled." newline bitfld.long 0x8 4. "LB_EN,Enables line/byte counter. This bit must only be set high after the lb_vc line_count and byte_count have been set." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "LB_VC,Indicates which VC should be used to generate line/byte counter interrupt. This value must not change while lb_en is enabled" rgroup.long 0x114++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_monitor_frame,Stream Monitor Frame." hexmask.long.word 0x0 16.--31. 1. "PACKET_SIZE,Size of the current payload" newline hexmask.long.word 0x0 0.--15. 1. "NB,Number of the last frame processed." rgroup.long 0x118++0x13 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_monitor_lb,Stream Monitor Line." hexmask.long.word 0x0 16.--31. 1. "LINE_COUNT,Indicates the line number to generate an interrupt. [First line of a Frame is line number 0]" newline hexmask.long.word 0x0 0.--15. 1. "BYTE_COUNT,Indicates the byte number of the line to generate an interrupt. [First byte of a line is byte number 0]" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_timer,Stream Timer." hexmask.long 0x4 0.--24. 1. "COUNT,Number of clock cycles" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_fcc_cfg,Stream Frame Capture Control configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_COUNT_STOP,Indicates the frame number on which the interrupt should be generated and the stream will stop outputting data on the pixel interface. [0x0000 will be continuous frames.]" newline hexmask.long.word 0x8 0.--15. 1. "FRAME_COUNT_START,Indicates the frame number on which the interrupt should be generated and the stream will start outputting data on the pixel interface. [0x0000 will be the current frame.]" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_fcc_ctrl,Stream Frame Capture Counter control." hexmask.long.word 0xC 16.--31. 1. "FRAME_COUNTER,Current Frame number being processed" newline hexmask.long.byte 0xC 1.--4. 1. "FCC_VC,Indicates which VC should be used to generate FCC interrupts. This value must not change while fcc_en is enabled" newline bitfld.long 0xC 0. "FCC_EN,Frame Capture Counter enable." "0,1" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_fifo_fill_lvl,Stream FIFO fill level monitor. This can operate in 2 modes:" bitfld.long 0x10 12.--13. "MODE,00 -> Fill level detection disabled 01 -> Mode 1 10 -> Mode 2 11 -> Reserved" "0: Fill level detection disabled 01,?,?,?" newline hexmask.long.word 0x10 0.--9. 1. "COUNT,Peak fill level of FIFO." rgroup.long 0x200++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_ctrl,CSI2RX Stream Data output datapath control." bitfld.long 0x0 4. "SOFT_RST,Writing 1'b1 will apply a synchronous soft reset of this stream registers/FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT,Writing 1 this register will cause the csi2rx to stop streaming on the corresponding output immediately. This may corrupt the output protocol. stream_abort_irq is generated on completion of the abort operation." "0,1" newline bitfld.long 0x0 1. "STOP,Writing 1 in this register will cause csi2rx to stop streaming on the corresponding output at the end of the current frame. If the command is issued during frame blanking then the datapath will immediately stop streaming.." "0,1" newline bitfld.long 0x0 0. "START,Writing 1 in this register enables the corresponding datapath output. It will start streaming data at the start of the next frame that complies with the output configuration. stream_status[31] running indicates when data.." "0,1" rgroup.long 0x204++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_status,CSI2 Slave Controller Status. Contains useful debug information such as" bitfld.long 0x0 31. "RUNNING,The Stream is enabled" "0,1" newline bitfld.long 0x0 8. "READY_STATE,Indicates the state of the pushback signal pixel_ready_if for this stream" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "STREAM_FSM,Output to Stream FSM states: 0x0: STREAM_IDLE 0x1: STREAM_WAIT_CTRL_DATA // Expecting control data next 0x2: STREAM_CTRL // Check contents of Ctrl packet and extract header.." newline bitfld.long 0x0 0.--1. "PROTOCOL_FSM,Input to Stream FSM states: 0x0: PROT_IDLE 0x1: PROT_WAIT_CTRL 0x2: PROT_CTRL 0x3: PROT_DATA" "0: PROT_IDLE 0x1: PROT_WAIT_CTRL 0x2: PROT_CTRL..,?,?,?" rgroup.long 0x208++0xB line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_data_cfg,Secondary CSI2 Slave Controller Data outputs configuration." hexmask.long.word 0x0 16.--31. 1. "VC_SELECT,Selection of Virtual Channels to be processed: Default '0' -> All Virtual Channels are processed vc_select0[16] -> Virtual Channel Select 0 is processed vc_select1[17] -> Virtual Channel Select 1 is processed vc_select2[18] ->.." newline bitfld.long 0x0 15. "ENABLE_DT1,Enable processing of dt1" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "DATATYPE_SELECT1,Second data type format that this stream will process" newline bitfld.long 0x0 7. "ENABLE_DT0,Enable processing of dt0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "DATATYPE_SELECT0,First data type format that this stream will process" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_cfg,Primary CSI2 Slave Controller Data pixel outputs configuration." hexmask.long.word 0x4 16.--31. 1. "FIFO_FILL,Set the FIFO_FILL_LEVEL which is used to hold data in the FIFO until this level is reached before allow data to be pulled. This setting is only used when fifo_mode is set for Large Buffer operation" newline bitfld.long 0x4 12.--14. "BPP_BYPASS,Force unpacking of any Data type as selected RAW type. 0 - No bypass 1 - unpack as RAW6 2 - unpack as RAW7 3 - unpack as RAW8 4 - unpack as RAW10 5 - unpack as.." "0: No bypass 1,?,2: unpack as RAW7 3,?,4: unpack as RAW10 5,?,6: unpack as RAW14 7,?" newline bitfld.long 0x4 8.--9. "FIFO_MODE,Stream FIFO configuration which must be set in accordance to FIFO sizing flow control and the relationship between the link and pixel interface data rates. Refer to Use Case descriptions for further guidance on FIFO sizing and.." "0: Full Line Buffer,1: Large Buffer [Fill Level Controlled],?,?" newline bitfld.long 0x4 4.--5. "NUM_PIXELS,Number of pixels to output from the stream. Valid values are 1 2 4 and 8. The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be.." "0,1,2,3" newline bitfld.long 0x4 1. "LS_LE_MODE,Enable LS/LE control of HYSNC_VALID output. By default LS and LE short packets are not required and HYSC_VALID will be generated from the start and end of payload data." "0,1" newline bitfld.long 0x4 0. "INTERFACE_MODE,Select the output configuration. Pixel = 0 [default] Packed = 1" "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_monitor_ctrl,Stream Monitor configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_LENGTH,Indicates the frame length in lines to detect truncated frames. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low. 0x0000 means truncated.." newline bitfld.long 0x8 15. "FRAME_MON_EN,Enables monitor. This bit must only be set high after the frame_mon_vc and frame_length have been set." "0,1" newline hexmask.long.byte 0x8 11.--14. 1. "FRAME_MON_VC,Indicates virtual channel for monitor. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low." newline bitfld.long 0x8 10. "TIMER_EOF,Select the starting point of the timer: 0x0: Start of Frame event on selected virtual channel 0x1: End of Frame event on selected virtual channel. This value must not change while timer_en is enabled" "0: Start of Frame event on selected virtual channel..,?" newline bitfld.long 0x8 9. "TIMER_EN,Enables timer based interrupt. This bit must only be set high after the timer_eof and timer_vc have been set." "0,1" newline hexmask.long.byte 0x8 5.--8. 1. "TIMER_VC,Indicates which VC should be used to generate timer based interrupt. This value must not change while timer_en is enabled." newline bitfld.long 0x8 4. "LB_EN,Enables line/byte counter. This bit must only be set high after the lb_vc line_count and byte_count have been set." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "LB_VC,Indicates which VC should be used to generate line/byte counter interrupt. This value must not change while lb_en is enabled" rgroup.long 0x214++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_monitor_frame,Stream Monitor Frame." hexmask.long.word 0x0 16.--31. 1. "PACKET_SIZE,Size of the current payload" newline hexmask.long.word 0x0 0.--15. 1. "NB,Number of the last frame processed." rgroup.long 0x218++0x13 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_monitor_lb,Stream Monitor Line." hexmask.long.word 0x0 16.--31. 1. "LINE_COUNT,Indicates the line number to generate an interrupt. [First line of a Frame is line number 0]" newline hexmask.long.word 0x0 0.--15. 1. "BYTE_COUNT,Indicates the byte number of the line to generate an interrupt. [First byte of a line is byte number 0]" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_timer,Stream Timer." hexmask.long 0x4 0.--24. 1. "COUNT,Number of clock cycles" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_fcc_cfg,Stream Frame Capture Control configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_COUNT_STOP,Indicates the frame number on which the interrupt should be generated and the stream will stop outputting data on the pixel interface. [0x0000 will be continuous frames.]" newline hexmask.long.word 0x8 0.--15. 1. "FRAME_COUNT_START,Indicates the frame number on which the interrupt should be generated and the stream will start outputting data on the pixel interface. [0x0000 will be the current frame.]" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_fcc_ctrl,Stream Frame Capture Counter control." hexmask.long.word 0xC 16.--31. 1. "FRAME_COUNTER,Current Frame number being processed" newline hexmask.long.byte 0xC 1.--4. 1. "FCC_VC,Indicates which VC should be used to generate FCC interrupts. This value must not change while fcc_en is enabled" newline bitfld.long 0xC 0. "FCC_EN,Frame Capture Counter enable." "0,1" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_fifo_fill_lvl,Stream FIFO fill level monitor. This can operate in 2 modes:" bitfld.long 0x10 12.--13. "MODE,00 -> Fill level detection disabled 01 -> Mode 1 10 -> Mode 2 11 -> Reserved" "0: Fill level detection disabled 01,?,?,?" newline hexmask.long.word 0x10 0.--9. 1. "COUNT,Peak fill level of FIFO." rgroup.long 0x300++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_ctrl,CSI2RX Stream Data output datapath control." bitfld.long 0x0 4. "SOFT_RST,Writing 1'b1 will apply a synchronous soft reset of this stream registers/FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT,Writing 1 this register will cause the csi2rx to stop streaming on the corresponding output immediately. This may corrupt the output protocol. stream_abort_irq is generated on completion of the abort operation." "0,1" newline bitfld.long 0x0 1. "STOP,Writing 1 in this register will cause csi2rx to stop streaming on the corresponding output at the end of the current frame. If the command is issued during frame blanking then the datapath will immediately stop streaming.." "0,1" newline bitfld.long 0x0 0. "START,Writing 1 in this register enables the corresponding datapath output. It will start streaming data at the start of the next frame that complies with the output configuration. stream_status[31] running indicates when data.." "0,1" rgroup.long 0x304++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_status,CSI2 Slave Controller Status. Contains useful debug information such as" bitfld.long 0x0 31. "RUNNING,The Stream is enabled" "0,1" newline bitfld.long 0x0 8. "READY_STATE,Indicates the state of the pushback signal pixel_ready_if for this stream" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "STREAM_FSM,Output to Stream FSM states: 0x0: STREAM_IDLE 0x1: STREAM_WAIT_CTRL_DATA // Expecting control data next 0x2: STREAM_CTRL // Check contents of Ctrl packet and extract header.." newline bitfld.long 0x0 0.--1. "PROTOCOL_FSM,Input to Stream FSM states: 0x0: PROT_IDLE 0x1: PROT_WAIT_CTRL 0x2: PROT_CTRL 0x3: PROT_DATA" "0: PROT_IDLE 0x1: PROT_WAIT_CTRL 0x2: PROT_CTRL..,?,?,?" rgroup.long 0x308++0xB line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_data_cfg,Secondary CSI2 Slave Controller Data outputs configuration." hexmask.long.word 0x0 16.--31. 1. "VC_SELECT,Selection of Virtual Channels to be processed: Default '0' -> All Virtual Channels are processed vc_select0[16] -> Virtual Channel Select 0 is processed vc_select1[17] -> Virtual Channel Select 1 is processed vc_select2[18] ->.." newline bitfld.long 0x0 15. "ENABLE_DT1,Enable processing of dt1" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "DATATYPE_SELECT1,Second data type format that this stream will process" newline bitfld.long 0x0 7. "ENABLE_DT0,Enable processing of dt0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "DATATYPE_SELECT0,First data type format that this stream will process" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_cfg,Primary CSI2 Slave Controller Data pixel outputs configuration." hexmask.long.word 0x4 16.--31. 1. "FIFO_FILL,Set the FIFO_FILL_LEVEL which is used to hold data in the FIFO until this level is reached before allow data to be pulled. This setting is only used when fifo_mode is set for Large Buffer operation" newline bitfld.long 0x4 12.--14. "BPP_BYPASS,Force unpacking of any Data type as selected RAW type. 0 - No bypass 1 - unpack as RAW6 2 - unpack as RAW7 3 - unpack as RAW8 4 - unpack as RAW10 5 - unpack as.." "0: No bypass 1,?,2: unpack as RAW7 3,?,4: unpack as RAW10 5,?,6: unpack as RAW14 7,?" newline bitfld.long 0x4 8.--9. "FIFO_MODE,Stream FIFO configuration which must be set in accordance to FIFO sizing flow control and the relationship between the link and pixel interface data rates. Refer to Use Case descriptions for further guidance on FIFO sizing and.." "0: Full Line Buffer,1: Large Buffer [Fill Level Controlled],?,?" newline bitfld.long 0x4 4.--5. "NUM_PIXELS,Number of pixels to output from the stream. Valid values are 1 2 4 and 8. The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be.." "0,1,2,3" newline bitfld.long 0x4 1. "LS_LE_MODE,Enable LS/LE control of HYSNC_VALID output. By default LS and LE short packets are not required and HYSC_VALID will be generated from the start and end of payload data." "0,1" newline bitfld.long 0x4 0. "INTERFACE_MODE,Select the output configuration. Pixel = 0 [default] Packed = 1" "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_monitor_ctrl,Stream Monitor configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_LENGTH,Indicates the frame length in lines to detect truncated frames. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low. 0x0000 means truncated.." newline bitfld.long 0x8 15. "FRAME_MON_EN,Enables monitor. This bit must only be set high after the frame_mon_vc and frame_length have been set." "0,1" newline hexmask.long.byte 0x8 11.--14. 1. "FRAME_MON_VC,Indicates virtual channel for monitor. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low." newline bitfld.long 0x8 10. "TIMER_EOF,Select the starting point of the timer: 0x0: Start of Frame event on selected virtual channel 0x1: End of Frame event on selected virtual channel. This value must not change while timer_en is enabled" "0: Start of Frame event on selected virtual channel..,?" newline bitfld.long 0x8 9. "TIMER_EN,Enables timer based interrupt. This bit must only be set high after the timer_eof and timer_vc have been set." "0,1" newline hexmask.long.byte 0x8 5.--8. 1. "TIMER_VC,Indicates which VC should be used to generate timer based interrupt. This value must not change while timer_en is enabled." newline bitfld.long 0x8 4. "LB_EN,Enables line/byte counter. This bit must only be set high after the lb_vc line_count and byte_count have been set." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "LB_VC,Indicates which VC should be used to generate line/byte counter interrupt. This value must not change while lb_en is enabled" rgroup.long 0x314++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_monitor_frame,Stream Monitor Frame." hexmask.long.word 0x0 16.--31. 1. "PACKET_SIZE,Size of the current payload" newline hexmask.long.word 0x0 0.--15. 1. "NB,Number of the last frame processed." rgroup.long 0x318++0x13 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_monitor_lb,Stream Monitor Line." hexmask.long.word 0x0 16.--31. 1. "LINE_COUNT,Indicates the line number to generate an interrupt. [First line of a Frame is line number 0]" newline hexmask.long.word 0x0 0.--15. 1. "BYTE_COUNT,Indicates the byte number of the line to generate an interrupt. [First byte of a line is byte number 0]" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_timer,Stream Timer." hexmask.long 0x4 0.--24. 1. "COUNT,Number of clock cycles" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_fcc_cfg,Stream Frame Capture Control configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_COUNT_STOP,Indicates the frame number on which the interrupt should be generated and the stream will stop outputting data on the pixel interface. [0x0000 will be continuous frames.]" newline hexmask.long.word 0x8 0.--15. 1. "FRAME_COUNT_START,Indicates the frame number on which the interrupt should be generated and the stream will start outputting data on the pixel interface. [0x0000 will be the current frame.]" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_fcc_ctrl,Stream Frame Capture Counter control." hexmask.long.word 0xC 16.--31. 1. "FRAME_COUNTER,Current Frame number being processed" newline hexmask.long.byte 0xC 1.--4. 1. "FCC_VC,Indicates which VC should be used to generate FCC interrupts. This value must not change while fcc_en is enabled" newline bitfld.long 0xC 0. "FCC_EN,Frame Capture Counter enable." "0,1" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_fifo_fill_lvl,Stream FIFO fill level monitor. This can operate in 2 modes:" bitfld.long 0x10 12.--13. "MODE,00 -> Fill level detection disabled 01 -> Mode 1 10 -> Mode 2 11 -> Reserved" "0: Fill level detection disabled 01,?,?,?" newline hexmask.long.word 0x10 0.--9. 1. "COUNT,Peak fill level of FIFO." rgroup.long 0x400++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_ctrl,CSI2RX Stream Data output datapath control." bitfld.long 0x0 4. "SOFT_RST,Writing 1'b1 will apply a synchronous soft reset of this stream registers/FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT,Writing 1 this register will cause the csi2rx to stop streaming on the corresponding output immediately. This may corrupt the output protocol. stream_abort_irq is generated on completion of the abort operation." "0,1" newline bitfld.long 0x0 1. "STOP,Writing 1 in this register will cause csi2rx to stop streaming on the corresponding output at the end of the current frame. If the command is issued during frame blanking then the datapath will immediately stop streaming.." "0,1" newline bitfld.long 0x0 0. "START,Writing 1 in this register enables the corresponding datapath output. It will start streaming data at the start of the next frame that complies with the output configuration. stream_status[31] running indicates when data.." "0,1" rgroup.long 0x404++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_status,CSI2 Slave Controller Status. Contains useful debug information such as" bitfld.long 0x0 31. "RUNNING,The Stream is enabled" "0,1" newline bitfld.long 0x0 8. "READY_STATE,Indicates the state of the pushback signal pixel_ready_if for this stream" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "STREAM_FSM,Output to Stream FSM states: 0x0: STREAM_IDLE 0x1: STREAM_WAIT_CTRL_DATA // Expecting control data next 0x2: STREAM_CTRL // Check contents of Ctrl packet and extract header.." newline bitfld.long 0x0 0.--1. "PROTOCOL_FSM,Input to Stream FSM states: 0x0: PROT_IDLE 0x1: PROT_WAIT_CTRL 0x2: PROT_CTRL 0x3: PROT_DATA" "0: PROT_IDLE 0x1: PROT_WAIT_CTRL 0x2: PROT_CTRL..,?,?,?" rgroup.long 0x408++0xB line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_data_cfg,Secondary CSI2 Slave Controller Data outputs configuration." hexmask.long.word 0x0 16.--31. 1. "VC_SELECT,Selection of Virtual Channels to be processed: Default '0' -> All Virtual Channels are processed vc_select0[16] -> Virtual Channel Select 0 is processed vc_select1[17] -> Virtual Channel Select 1 is processed vc_select2[18] ->.." newline bitfld.long 0x0 15. "ENABLE_DT1,Enable processing of dt1" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "DATATYPE_SELECT1,Second data type format that this stream will process" newline bitfld.long 0x0 7. "ENABLE_DT0,Enable processing of dt0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "DATATYPE_SELECT0,First data type format that this stream will process" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_cfg,Primary CSI2 Slave Controller Data pixel outputs configuration." hexmask.long.word 0x4 16.--31. 1. "FIFO_FILL,Set the FIFO_FILL_LEVEL which is used to hold data in the FIFO until this level is reached before allow data to be pulled. This setting is only used when fifo_mode is set for Large Buffer operation" newline bitfld.long 0x4 12.--14. "BPP_BYPASS,Force unpacking of any Data type as selected RAW type. 0 - No bypass 1 - unpack as RAW6 2 - unpack as RAW7 3 - unpack as RAW8 4 - unpack as RAW10 5 - unpack as.." "0: No bypass 1,?,2: unpack as RAW7 3,?,4: unpack as RAW10 5,?,6: unpack as RAW14 7,?" newline bitfld.long 0x4 8.--9. "FIFO_MODE,Stream FIFO configuration which must be set in accordance to FIFO sizing flow control and the relationship between the link and pixel interface data rates. Refer to Use Case descriptions for further guidance on FIFO sizing and.." "0: Full Line Buffer,1: Large Buffer [Fill Level Controlled],?,?" newline bitfld.long 0x4 4.--5. "NUM_PIXELS,Number of pixels to output from the stream. Valid values are 1 2 4 and 8. The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be.." "0,1,2,3" newline bitfld.long 0x4 1. "LS_LE_MODE,Enable LS/LE control of HYSNC_VALID output. By default LS and LE short packets are not required and HYSC_VALID will be generated from the start and end of payload data." "0,1" newline bitfld.long 0x4 0. "INTERFACE_MODE,Select the output configuration. Pixel = 0 [default] Packed = 1" "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_monitor_ctrl,Stream Monitor configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_LENGTH,Indicates the frame length in lines to detect truncated frames. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low. 0x0000 means truncated.." newline bitfld.long 0x8 15. "FRAME_MON_EN,Enables monitor. This bit must only be set high after the frame_mon_vc and frame_length have been set." "0,1" newline hexmask.long.byte 0x8 11.--14. 1. "FRAME_MON_VC,Indicates virtual channel for monitor. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low." newline bitfld.long 0x8 10. "TIMER_EOF,Select the starting point of the timer: 0x0: Start of Frame event on selected virtual channel 0x1: End of Frame event on selected virtual channel. This value must not change while timer_en is enabled" "0: Start of Frame event on selected virtual channel..,?" newline bitfld.long 0x8 9. "TIMER_EN,Enables timer based interrupt. This bit must only be set high after the timer_eof and timer_vc have been set." "0,1" newline hexmask.long.byte 0x8 5.--8. 1. "TIMER_VC,Indicates which VC should be used to generate timer based interrupt. This value must not change while timer_en is enabled." newline bitfld.long 0x8 4. "LB_EN,Enables line/byte counter. This bit must only be set high after the lb_vc line_count and byte_count have been set." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "LB_VC,Indicates which VC should be used to generate line/byte counter interrupt. This value must not change while lb_en is enabled" rgroup.long 0x414++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_monitor_frame,Stream Monitor Frame." hexmask.long.word 0x0 16.--31. 1. "PACKET_SIZE,Size of the current payload" newline hexmask.long.word 0x0 0.--15. 1. "NB,Number of the last frame processed." rgroup.long 0x418++0x13 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_monitor_lb,Stream Monitor Line." hexmask.long.word 0x0 16.--31. 1. "LINE_COUNT,Indicates the line number to generate an interrupt. [First line of a Frame is line number 0]" newline hexmask.long.word 0x0 0.--15. 1. "BYTE_COUNT,Indicates the byte number of the line to generate an interrupt. [First byte of a line is byte number 0]" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_timer,Stream Timer." hexmask.long 0x4 0.--24. 1. "COUNT,Number of clock cycles" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_fcc_cfg,Stream Frame Capture Control configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_COUNT_STOP,Indicates the frame number on which the interrupt should be generated and the stream will stop outputting data on the pixel interface. [0x0000 will be continuous frames.]" newline hexmask.long.word 0x8 0.--15. 1. "FRAME_COUNT_START,Indicates the frame number on which the interrupt should be generated and the stream will start outputting data on the pixel interface. [0x0000 will be the current frame.]" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_fcc_ctrl,Stream Frame Capture Counter control." hexmask.long.word 0xC 16.--31. 1. "FRAME_COUNTER,Current Frame number being processed" newline hexmask.long.byte 0xC 1.--4. 1. "FCC_VC,Indicates which VC should be used to generate FCC interrupts. This value must not change while fcc_en is enabled" newline bitfld.long 0xC 0. "FCC_EN,Frame Capture Counter enable." "0,1" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_fifo_fill_lvl,Stream FIFO fill level monitor. This can operate in 2 modes:" bitfld.long 0x10 12.--13. "MODE,00 -> Fill level detection disabled 01 -> Mode 1 10 -> Mode 2 11 -> Reserved" "0: Fill level detection disabled 01,?,?,?" newline hexmask.long.word 0x10 0.--9. 1. "COUNT,Peak fill level of FIFO." rgroup.long 0x900++0x13 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_int_status,ASF Interrupt Status Register. This register indicates the source of ASF interrupts. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register the.." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x0 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1" newline bitfld.long 0x0 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1" newline bitfld.long 0x0 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1" newline bitfld.long 0x0 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x0 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1" newline bitfld.long 0x0 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x0 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_int_raw_status,ASF Interrupt Raw Status Register. A bit set in this raw register indicates a source of ASF fault in the corresponding feature. Writing to either raw or masked status registers. clear both.." hexmask.long 0x4 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x4 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1" newline bitfld.long 0x4 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1" newline bitfld.long 0x4 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1" newline bitfld.long 0x4 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x4 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1" newline bitfld.long 0x4 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x4 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_int_mask,The ASF interrupt mask register indicating which interrupt bits in the ASF interrupt status register are masked. All bits are set at reset. Clear the individual bit to enable the corresponding interrupt." hexmask.long 0x8 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x8 6. "ASF_INTEGRITY_ERR_MASK,Mask bit for integrity error interrupt" "0,1" newline bitfld.long 0x8 5. "ASF_PROTOCOL_ERR_MASK,Mask bit for protocol error interrupt." "0,1" newline bitfld.long 0x8 4. "ASF_TRANS_TO_ERR_MASK,Mask bit for transaction timeouts error interrupt." "0,1" newline bitfld.long 0x8 3. "ASF_CSR_ERR_MASK,Mask bit for configuration and status registers error interrupt." "0,1" newline bitfld.long 0x8 2. "ASF_DAP_ERR_MASK,Mask bit for data and address paths parity error interrupt." "0,1" newline bitfld.long 0x8 1. "ASF_SRAM_UNCORR_ERR_MASK,Mask bit for SRAM uncorrectable error interrupt." "0,1" newline bitfld.long 0x8 0. "ASF_SRAM_CORR_ERR_MASK,Mask bit for SRAM correctable error interrupt." "0,1" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_int_test,The ASF interrupt test register emulate hardware even. Write one to individual bit to trigger single event in (masked and raw) status registers according to mask and will generate interrupt accordingly." hexmask.long 0xC 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0xC 6. "ASF_INTEGRITY_ERR_TEST,Test bit for integrity error interrupt" "0,1" newline bitfld.long 0xC 5. "ASF_PROTOCOL_ERR_TEST,Test bit for protocol error interrupt." "0,1" newline bitfld.long 0xC 4. "ASF_TRANS_TO_ERR_TEST,Test bit for transaction timeouts error interrupt." "0,1" newline bitfld.long 0xC 3. "ASF_CSR_ERR_TEST,Test bit for configuration and status registers error interrupt." "0,1" newline bitfld.long 0xC 2. "ASF_DAP_ERR_TEST,Test bit for data and address paths parity error interrupt." "0,1" newline bitfld.long 0xC 1. "ASF_SRAM_UNCORR_ERR_TEST,Test bit for SRAM uncorrectable error interrupt." "0,1" newline bitfld.long 0xC 0. "ASF_SRAM_CORR_ERR_TEST,Test bit for SRAM correctable error interrupt." "0,1" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_fatal_nonfatal_select,The fatal or non-fatal interrupt register selects whether a fatal (asf_int_fatal) or non-fatal (asf_int_nonfatal) interrupt is triggered. If the bit of the event will be set to one then.." hexmask.long 0x10 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x10 6. "ASF_INTEGRITY_ERR,Enable integrity error interrupt as fatal" "0,1" newline bitfld.long 0x10 5. "ASF_PROTOCOL_ERR,Enable protocol error interrupt as fatal." "0,1" newline bitfld.long 0x10 4. "ASF_TRANS_TO_ERR,Enable transaction timeouts error interrupt as fatal." "0,1" newline bitfld.long 0x10 3. "ASF_CSR_ERR,Enable configuration and status registers error interrupt as fatal." "0,1" newline bitfld.long 0x10 2. "ASF_DAP_ERR,Enable data and address paths parity error interrupt as fatal." "0,1" newline bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR,Enable SRAM uncorrectable error interrupt as fatal." "0,1" newline bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR,Enable SRAM correctable error interrupt as fatal." "0,1" rgroup.long 0x920++0x7 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_sram_corr_fault_status,Status register for SRAM correctable fault. These fields are updated whenever asf_sram_corr_fault input is active." hexmask.long.byte 0x0 24.--31. 1. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault." newline hexmask.long.tbyte 0x0 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault." line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_sram_uncorr_fault_status,Status register for SRAM uncorrectable fault. These fields are updated whenever asf_sram_uncorr_fault input is active." hexmask.long.byte 0x4 24.--31. 1. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault." newline hexmask.long.tbyte 0x4 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault." rgroup.long 0x928++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_sram_fault_stats,Statistics register for SRAM faults. Note that this register clears when software writes to any field." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline hexmask.long.word 0x0 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS,Count of number of correctable errors if implemented. Count value will saturate at 0xffff." rgroup.long 0x930++0xB line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_trans_to_ctrl,Control register to configure the ASF transaction timeout monitors." bitfld.long 0x0 31. "ASF_TRANS_TO_EN,Enable transaction timeout monitoring." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "ASF_TRANS_TO_CTRL,Timer value to use for transaction timeout monitor." line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_trans_to_fault_mask,Control register to mask out ASF transaction timeout faults from triggering interrupts. On reset. all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt.." bitfld.long 0x4 0. "ASF_TRANS_TO_FAULT_0_MASK,Mask register for each ASF transaction timeout fault source." "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_trans_to_fault_status,Status register for transaction timeouts fault. If a fault occurs the revelant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit." bitfld.long 0x8 0. "ASF_TRANS_TO_FAULT_0_STATUS,Status bits for transaction timeouts faults." "0,1" rgroup.long 0x940++0x7 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_protocol_fault_mask,Control register to mask out ASF Protocol faults from triggering interrupts. On reset. all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt source. The.." bitfld.long 0x0 13. "ASF_PROTOCOL_FAULT_13_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 12. "ASF_PROTOCOL_FAULT_12_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 11. "ASF_PROTOCOL_FAULT_11_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 10. "ASF_PROTOCOL_FAULT_10_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 9. "ASF_PROTOCOL_FAULT_9_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 8. "ASF_PROTOCOL_FAULT_8_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 7. "ASF_PROTOCOL_FAULT_7_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 6. "ASF_PROTOCOL_FAULT_6_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 5. "ASF_PROTOCOL_FAULT_5_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 4. "ASF_PROTOCOL_FAULT_4_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 3. "ASF_PROTOCOL_FAULT_3_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 2. "ASF_PROTOCOL_FAULT_2_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 1. "ASF_PROTOCOL_FAULT_1_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 0. "ASF_PROTOCOL_FAULT_0_MASK,Mask register for each ASF protocol fault source." "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_protocol_fault_status,Status register for protocol faults. If a fault occurs the revelant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit" bitfld.long 0x4 13. "ASF_PROTOCOL_FAULT_13_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 12. "ASF_PROTOCOL_FAULT_12_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 11. "ASF_PROTOCOL_FAULT_11_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 10. "ASF_PROTOCOL_FAULT_10_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 9. "ASF_PROTOCOL_FAULT_9_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 8. "ASF_PROTOCOL_FAULT_8_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 7. "ASF_PROTOCOL_FAULT_7_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 6. "ASF_PROTOCOL_FAULT_6_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 5. "ASF_PROTOCOL_FAULT_5_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 4. "ASF_PROTOCOL_FAULT_4_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 3. "ASF_PROTOCOL_FAULT_3_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 2. "ASF_PROTOCOL_FAULT_2_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 1. "ASF_PROTOCOL_FAULT_1_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 0. "ASF_PROTOCOL_FAULT_0_STATUS,Status bits for protocol faults." "0,1" rgroup.long 0xFFC++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_id_prod_ver,This register is hard-coded in order to allow software to identify the product and its" hexmask.long.word 0x0 16.--31. 1. "PRODUCT_ID,Product Identification Number [IP5022/IP5022A]." newline hexmask.long.word 0x0 0.--15. 1. "VERSION_ID,Product Version Number [R200]." tree.end tree.end tree "csi_rx_if1" tree "csi_rx_if1_CP_INTD_CFG_INTD_CFG (csi_rx_if1_CP_INTD_CFG_INTD_CFG)" base ad:0x4518000 rgroup.long 0x0++0x3 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_REVISION,Revision Register" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTLVER,RTL revisions" newline bitfld.long 0x0 8.--10. "MAJREV,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_eoi_reg,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector" rgroup.long 0x14++0x3 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg,Interrupt Vector Register" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR,Interrupt Vector Register" rgroup.long 0x100++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_0,Enable Register 0" bitfld.long 0x0 4. "ENABLE_LEVEL_EN_INT_VP1_ERROVERFLOW,Enable Set for level_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x0 3. "ENABLE_LEVEL_EN_INT_VP1_ERRINLNFRM,Enable Set for level_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x0 2. "ENABLE_LEVEL_EN_INT_VP0_ERROVERFLOW,Enable Set for level_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x0 1. "ENABLE_LEVEL_EN_INT_VP0_ERRINLNFRM,Enable Set for level_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x0 0. "ENABLE_LEVEL_EN_FIFO_OVERFLOW,Enable Set for level_en_fifo_overflow" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_0,Enable Register 1" bitfld.long 0x4 4. "ENABLE_PULSE_EN_INT_VP1_ERROVERFLOW,Enable Set for pulse_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x4 3. "ENABLE_PULSE_EN_INT_VP1_ERRINLNFRM,Enable Set for pulse_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x4 2. "ENABLE_PULSE_EN_INT_VP0_ERROVERFLOW,Enable Set for pulse_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x4 1. "ENABLE_PULSE_EN_INT_VP0_ERRINLNFRM,Enable Set for pulse_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x4 0. "ENABLE_PULSE_EN_FIFO_OVERFLOW,Enable Set for pulse_en_fifo_overflow" "0,1" rgroup.long 0x300++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_0,Enable Clear Register 0" bitfld.long 0x0 4. "ENABLE_LEVEL_EN_INT_VP1_ERROVERFLOW_CLR,Enable Clear for level_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x0 3. "ENABLE_LEVEL_EN_INT_VP1_ERRINLNFRM_CLR,Enable Clear for level_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x0 2. "ENABLE_LEVEL_EN_INT_VP0_ERROVERFLOW_CLR,Enable Clear for level_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x0 1. "ENABLE_LEVEL_EN_INT_VP0_ERRINLNFRM_CLR,Enable Clear for level_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x0 0. "ENABLE_LEVEL_EN_FIFO_OVERFLOW_CLR,Enable Clear for level_en_fifo_overflow" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_0,Enable Clear Register 1" bitfld.long 0x4 4. "ENABLE_PULSE_EN_INT_VP1_ERROVERFLOW_CLR,Enable Clear for pulse_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x4 3. "ENABLE_PULSE_EN_INT_VP1_ERRINLNFRM_CLR,Enable Clear for pulse_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x4 2. "ENABLE_PULSE_EN_INT_VP0_ERROVERFLOW_CLR,Enable Clear for pulse_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x4 1. "ENABLE_PULSE_EN_INT_VP0_ERRINLNFRM_CLR,Enable Clear for pulse_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x4 0. "ENABLE_PULSE_EN_FIFO_OVERFLOW_CLR,Enable Clear for pulse_en_fifo_overflow" "0,1" rgroup.long 0x500++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_0,Status Register 0" bitfld.long 0x0 4. "STATUS_LEVEL_INT_VP1_ERROVERFLOW,Status write 1 to set for level_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x0 3. "STATUS_LEVEL_INT_VP1_ERRINLNFRM,Status write 1 to set for level_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x0 2. "STATUS_LEVEL_INT_VP0_ERROVERFLOW,Status write 1 to set for level_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x0 1. "STATUS_LEVEL_INT_VP0_ERRINLNFRM,Status write 1 to set for level_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x0 0. "STATUS_LEVEL_FIFO_OVERFLOW,Status write 1 to set for level_en_fifo_overflow" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_0,Status Register 1" bitfld.long 0x4 4. "STATUS_PULSE_INT_VP1_ERROVERFLOW,Status write 1 to set for pulse_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x4 3. "STATUS_PULSE_INT_VP1_ERRINLNFRM,Status write 1 to set for pulse_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x4 2. "STATUS_PULSE_INT_VP0_ERROVERFLOW,Status write 1 to set for pulse_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x4 1. "STATUS_PULSE_INT_VP0_ERRINLNFRM,Status write 1 to set for pulse_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x4 0. "STATUS_PULSE_FIFO_OVERFLOW,Status write 1 to set for pulse_en_fifo_overflow" "0,1" rgroup.long 0x700++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_0,Status Clear Register 0" bitfld.long 0x0 4. "STATUS_LEVEL_INT_VP1_ERROVERFLOW_CLR,Status write 1 to clear for level_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x0 3. "STATUS_LEVEL_INT_VP1_ERRINLNFRM_CLR,Status write 1 to clear for level_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x0 2. "STATUS_LEVEL_INT_VP0_ERROVERFLOW_CLR,Status write 1 to clear for level_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x0 1. "STATUS_LEVEL_INT_VP0_ERRINLNFRM_CLR,Status write 1 to clear for level_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x0 0. "STATUS_LEVEL_FIFO_OVERFLOW_CLR,Status write 1 to clear for level_en_fifo_overflow" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_0,Status Clear Register 1" bitfld.long 0x4 4. "STATUS_PULSE_INT_VP1_ERROVERFLOW_CLR,Status write 1 to clear for pulse_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x4 3. "STATUS_PULSE_INT_VP1_ERRINLNFRM_CLR,Status write 1 to clear for pulse_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x4 2. "STATUS_PULSE_INT_VP0_ERROVERFLOW_CLR,Status write 1 to clear for pulse_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x4 1. "STATUS_PULSE_INT_VP0_ERRINLNFRM_CLR,Status write 1 to clear for pulse_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x4 0. "STATUS_PULSE_FIFO_OVERFLOW_CLR,Status write 1 to clear for pulse_en_fifo_overflow" "0,1" rgroup.long 0xA80++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_level,Interrupt Vector for level" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR_LEVEL,Interrupt Vector" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_pulse,Interrupt Vector for pulse" hexmask.long 0x4 0.--31. 1. "INTR_VECTOR_PULSE,Interrupt Vector" tree.end tree "csi_rx_if1_ECC_AGGR_CFG (csi_rx_if1_ECC_AGGR_CFG)" base ad:0x2A31000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 7. "VP1_FIFO_RAMECC_PEND,Interrupt Pending Status for vp1_fifo_ramecc_pend" "0,1" bitfld.long 0x4 6. "VP0_FIFO_RAMECC_PEND,Interrupt Pending Status for vp0_fifo_ramecc_pend" "0,1" bitfld.long 0x4 5. "RAM_RAMECC3_PEND,Interrupt Pending Status for ram_ramecc3_pend" "0,1" newline bitfld.long 0x4 4. "RAM_RAMECC2_PEND,Interrupt Pending Status for ram_ramecc2_pend" "0,1" bitfld.long 0x4 3. "RAM_RAMECC1_PEND,Interrupt Pending Status for ram_ramecc1_pend" "0,1" bitfld.long 0x4 2. "RAM_RAMECC0_PEND,Interrupt Pending Status for ram_ramecc0_pend" "0,1" newline bitfld.long 0x4 1. "PSIL_FIFO_RAMECC_PEND,Interrupt Pending Status for psil_fifo_ramecc_pend" "0,1" bitfld.long 0x4 0. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 7. "VP1_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp1_fifo_ramecc_pend" "0,1" bitfld.long 0x0 6. "VP0_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp0_fifo_ramecc_pend" "0,1" bitfld.long 0x0 5. "RAM_RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc3_pend" "0,1" newline bitfld.long 0x0 4. "RAM_RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc2_pend" "0,1" bitfld.long 0x0 3. "RAM_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc1_pend" "0,1" bitfld.long 0x0 2. "RAM_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc0_pend" "0,1" newline bitfld.long 0x0 1. "PSIL_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for psil_fifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 7. "VP1_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp1_fifo_ramecc_pend" "0,1" bitfld.long 0x0 6. "VP0_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp0_fifo_ramecc_pend" "0,1" bitfld.long 0x0 5. "RAM_RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc3_pend" "0,1" newline bitfld.long 0x0 4. "RAM_RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc2_pend" "0,1" bitfld.long 0x0 3. "RAM_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc1_pend" "0,1" bitfld.long 0x0 2. "RAM_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc0_pend" "0,1" newline bitfld.long 0x0 1. "PSIL_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for psil_fifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 7. "VP1_FIFO_RAMECC_PEND,Interrupt Pending Status for vp1_fifo_ramecc_pend" "0,1" bitfld.long 0x4 6. "VP0_FIFO_RAMECC_PEND,Interrupt Pending Status for vp0_fifo_ramecc_pend" "0,1" bitfld.long 0x4 5. "RAM_RAMECC3_PEND,Interrupt Pending Status for ram_ramecc3_pend" "0,1" newline bitfld.long 0x4 4. "RAM_RAMECC2_PEND,Interrupt Pending Status for ram_ramecc2_pend" "0,1" bitfld.long 0x4 3. "RAM_RAMECC1_PEND,Interrupt Pending Status for ram_ramecc1_pend" "0,1" bitfld.long 0x4 2. "RAM_RAMECC0_PEND,Interrupt Pending Status for ram_ramecc0_pend" "0,1" newline bitfld.long 0x4 1. "PSIL_FIFO_RAMECC_PEND,Interrupt Pending Status for psil_fifo_ramecc_pend" "0,1" bitfld.long 0x4 0. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 7. "VP1_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp1_fifo_ramecc_pend" "0,1" bitfld.long 0x0 6. "VP0_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp0_fifo_ramecc_pend" "0,1" bitfld.long 0x0 5. "RAM_RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc3_pend" "0,1" newline bitfld.long 0x0 4. "RAM_RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc2_pend" "0,1" bitfld.long 0x0 3. "RAM_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc1_pend" "0,1" bitfld.long 0x0 2. "RAM_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc0_pend" "0,1" newline bitfld.long 0x0 1. "PSIL_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for psil_fifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 7. "VP1_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp1_fifo_ramecc_pend" "0,1" bitfld.long 0x0 6. "VP0_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp0_fifo_ramecc_pend" "0,1" bitfld.long 0x0 5. "RAM_RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc3_pend" "0,1" newline bitfld.long 0x0 4. "RAM_RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc2_pend" "0,1" bitfld.long 0x0 3. "RAM_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc1_pend" "0,1" bitfld.long 0x0 2. "RAM_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc0_pend" "0,1" newline bitfld.long 0x0 1. "PSIL_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for psil_fifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "csi_rx_if1_RX_SHIM_VBUSP_MMR_CSI2RXIF (csi_rx_if1_RX_SHIM_VBUSP_MMR_CSI2RXIF)" base ad:0x4510000 rgroup.long 0x0++0x3 line.long 0x0 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_csirx_id,nothing" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,min revision" rgroup.long 0x8++0xB line.long 0x0 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_vp0,Video Port 0 configuration" bitfld.long 0x0 31. "EN_CFG,Video Port enable. Disable:drops pixel data Enable: start on VS captures and sends frame data. Will force ih and iw size by zero pad or trunc. When 1 prevents writing rest of fields in this register." "0,1" hexmask.long.word 0x0 16.--28. 1. "IH_CFG,(U13) input height in units of lines. Only writable when vp0_en_cfg=0. writes blockes when vp0_en_cfg=1" hexmask.long.word 0x0 0.--12. 1. "IW_CFG,(U13) input width in units of RAW data samples. Max usable value determined by populated line buffer RAM size. Only writable when vp0_en_cfg=0. writes blockes when vp0_en_cfg=1. You should read this value first and if set to 0 then you should.." line.long 0x4 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_vp1,Video Port 1 configuration" bitfld.long 0x4 31. "EN_CFG,Video Port enable. Disable:drops pixel data Enable: start on VS captures and sends frame data. Will force ih and iw size by zero pad or trunc. When 1 prevents writing rest of fields in this register." "0,1" hexmask.long.word 0x4 16.--28. 1. "IH_CFG,(U13) input height in units of lines. Only writable when vp0_en_cfg=0. writes blovkes when vp1_en_cfg=1" hexmask.long.word 0x4 0.--12. 1. "IW_CFG,(U13) input width in units of RAW data samples. Max usable value determined by populated line buffer RAM size. Only writable when vp1_en_cfg=0. writes blockes when vp1_en_cfg=1. You should read this value first and if set to 0 then you should.." line.long 0x8 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_cntl,control register for csi rx wrapper" rbitfld.long 0x8 11. "STREAM3_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1" rbitfld.long 0x8 10. "STREAM2_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1" rbitfld.long 0x8 9. "STREAM1_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1" rbitfld.long 0x8 8. "STREAM0_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1" bitfld.long 0x8 0. "PIXEL_RESET,reset for the pixeal interface. 0-reset 1 not in reset. this shoud be asserted till after you program the csi controller configuration registers" "0: reset,?" tree.end tree "csi_rx_if1_VBUS2APB_WRAP_VBUSP_APB_CSI2RX (csi_rx_if1_VBUS2APB_WRAP_VBUSP_APB_CSI2RX)" base ad:0x4514000 rgroup.long 0x0++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_device_config,This register provides information related to the current configuration." bitfld.long 0x0 31. "STREAM3_MONITOR_PRESENT,Pixel stream 3 Monitor present 1 = implemented" "?,1: implemented" newline bitfld.long 0x0 29.--30. "STREAM3_NUM_PIXELS,The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be output in a single cycle. Default will be 1 pixel per clock. 00 -> 1.." "0,1,2,3" newline bitfld.long 0x0 27.--28. "STREAM3_FIFO_MODE,Stream 3 FIFO Mode." "0,1,2,3" newline bitfld.long 0x0 26. "STREAM2_MONITOR_PRESENT,Pixel stream 2 Monitor present 1 = implemented" "?,1: implemented" newline bitfld.long 0x0 24.--25. "STREAM2_NUM_PIXELS,The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be output in a single cycle. Default will be 1 pixel per clock. 00 -> 1.." "0,1,2,3" newline bitfld.long 0x0 22.--23. "STREAM2_FIFO_MODE,Stream 2 FIFO Mode." "0,1,2,3" newline bitfld.long 0x0 21. "STREAM1_MONITOR_PRESENT,Pixel stream 1 Monitor present 1 = implemented" "?,1: implemented" newline bitfld.long 0x0 19.--20. "STREAM1_NUM_PIXELS,The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be output in a single cycle. Default will be 1 pixel per clock. 00 -> 1.." "0,1,2,3" newline bitfld.long 0x0 17.--18. "STREAM1_FIFO_MODE,Stream 1 FIFO Mode." "0,1,2,3" newline bitfld.long 0x0 16. "STREAM0_MONITOR_PRESENT,Pixel stream 0 Monitor present 1 = implemented" "?,1: implemented" newline bitfld.long 0x0 14.--15. "STREAM0_NUM_PIXELS,The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be output in a single cycle. Default will be 1 pixel per clock. 00 -> 1.." "0,1,2,3" newline bitfld.long 0x0 12.--13. "STREAM0_FIFO_MODE,Stream 0 FIFO Mode." "0,1,2,3" newline bitfld.long 0x0 10. "ASF_CONFIG,Additional Safety Features [ASF] Configuration: 0 = None; 1 = Full ASF." "0: None;,1: Full ASF" newline bitfld.long 0x0 9. "VCX_CONFIG,Extended Virtual Channel [VCX] Configuration: 0 = 4 VCs; 1 = 16 VCs" "0,1" newline bitfld.long 0x0 7.--8. "DATAPATH_SIZE,Internal Datapath width 00 - 32 bit 01 - 64bit 10 - 16 bit 11 - 8 Bits." "0,1,2,3" newline bitfld.long 0x0 4.--6. "NUM_STREAMS,Number of Stream interfaces [1-4]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "CDNS_PHY_PRESENT,Cadence DPDHY present 1 = Yes" "?,1: Yes" newline bitfld.long 0x0 0.--2. "MAX_LANE_NB,Max Number of Lanes [1-4]" "0,1,2,3,4,5,6,7" rgroup.long 0x4++0x7 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_soft_reset,CSI2 Slave Controller Individual Soft Reset for Front and Protocol blocks." bitfld.long 0x0 1. "PROTOCOL,writing 1'b1 will apply a synchronous soft reset to the protocol module" "0,1" newline bitfld.long 0x0 0. "FRONT,writing 1'b1 will apply a synchronous soft reset to the Front module" "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_static_cfg,Configuration register to set the physical/logical DPHY lane mapping." bitfld.long 0x4 28.--30. "DL3_MAP,physical mapping of logical data lane 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 24.--26. "DL2_MAP,physical mapping of logical data lane 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20.--22. "DL1_MAP,physical mapping of logical data lane 1." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16.--18. "DL0_MAP,physical mapping of logical data lane 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "LANE_NB,The number of lanes" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4. "V2P0_SUPPORT_ENABLE,Support extended VC up to 16 virtual channels [4-bits] and RAW16/20. as per CSI2RX v2.0. Default is up to 4 virtual channels [3-bits] as per CSI2RX v1.3" "0,1" newline bitfld.long 0x4 0.--1. "SEL,selection of DPHY used as input of CSI2RX module" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_bypass_cfg,Error detection event flag configuration." bitfld.long 0x0 2. "DATA_ID,Enables Data ID error bypass for stream outputs. When enabled Data ID errors in packets are signalled as interrupt events however the data is still passed to the pixel/packed data outputs. The system must decide to.." "0,1" newline bitfld.long 0x0 1. "ECC,Enables ECC error bypass for stream outputs. When enabled CRC errors in packets are signalled as interrupt events however the data is still passed to the pixel/packed data outputs. The system must decide to mask of use the.." "0,1" newline bitfld.long 0x0 0. "CRC,Enables CRC error bypass for stream outputs. When enabled CRC errors in packets are signalled as interrupt events however the data is still passed to the pixel/packed data outputs. The system must decide to mask of use the.." "0,1" rgroup.long 0x18++0x17 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_monitor_irqs,Information type Interrupt status (non-error conditions)" bitfld.long 0x0 31. "STREAM3_LINE_CNT_ERROR_IRQ,Stream 3 Line count error interrupt" "0,1" newline bitfld.long 0x0 30. "STREAM3_FRAME_MISMATCH_IRQ,Stream 3 Frame mismatch error interrupt" "0,1" newline bitfld.long 0x0 29. "STREAM3_FRAME_CNT_ERROR_IRQ,Stream 3 Frame count error interrupt" "0,1" newline bitfld.long 0x0 28. "STREAM3_FCC_STOP_IRQ,Stream 3 FCC stop interrupt" "0,1" newline bitfld.long 0x0 27. "STREAM3_FCC_START_IRQ,Stream 3 FCC start interrupt" "0,1" newline bitfld.long 0x0 26. "STREAM3_FRAME_IRQ,Stream 3 Frame interrupt" "0,1" newline bitfld.long 0x0 25. "STREAM3_LB_IRQ,Stream 3 Line/byte interrupt" "0,1" newline bitfld.long 0x0 24. "STREAM3_TIMER_IRQ,Stream 3 Timer interrupt" "0,1" newline bitfld.long 0x0 23. "STREAM2_LINE_CNT_ERROR_IRQ,Stream 2 Line count error interrupt" "0,1" newline bitfld.long 0x0 22. "STREAM2_FRAME_MISMATCH_IRQ,Stream 2 Frame mismatch error interrupt" "0,1" newline bitfld.long 0x0 21. "STREAM2_FRAME_CNT_ERROR_IRQ,Stream 2 Frame count error interrupt" "0,1" newline bitfld.long 0x0 20. "STREAM2_FCC_STOP_IRQ,Stream 2 FCC stop interrupt" "0,1" newline bitfld.long 0x0 19. "STREAM2_FCC_START_IRQ,Stream 2 FCC start interrupt" "0,1" newline bitfld.long 0x0 18. "STREAM2_FRAME_IRQ,Stream 2 Frame interrupt" "0,1" newline bitfld.long 0x0 17. "STREAM2_LB_IRQ,Stream 2 Line/byte interrupt" "0,1" newline bitfld.long 0x0 16. "STREAM2_TIMER_IRQ,Stream 2 Timer interrupt" "0,1" newline bitfld.long 0x0 15. "STREAM1_LINE_CNT_ERROR_IRQ,Stream 1 Line count error interrupt" "0,1" newline bitfld.long 0x0 14. "STREAM1_FRAME_MISMATCH_IRQ,Stream 1 Frame mismatch error interrupt" "0,1" newline bitfld.long 0x0 13. "STREAM1_FRAME_CNT_ERROR_IRQ,Stream 1 Frame count error interrupt" "0,1" newline bitfld.long 0x0 12. "STREAM1_FCC_STOP_IRQ,Stream 1 FCC stop interrupt" "0,1" newline bitfld.long 0x0 11. "STREAM1_FCC_START_IRQ,Stream 1 FCC start interrupt" "0,1" newline bitfld.long 0x0 10. "STREAM1_FRAME_IRQ,Stream 1 Frame interrupt" "0,1" newline bitfld.long 0x0 9. "STREAM1_LB_IRQ,Stream 1 Line/byte interrupt" "0,1" newline bitfld.long 0x0 8. "STREAM1_TIMER_IRQ,Stream 1 Timer interrupt" "0,1" newline bitfld.long 0x0 7. "STREAM0_LINE_CNT_ERROR_IRQ,Stream 0 Line count error interrupt" "0,1" newline bitfld.long 0x0 6. "STREAM0_FRAME_MISMATCH_IRQ,Stream 0 Frame mismatch error interrupt" "0,1" newline bitfld.long 0x0 5. "STREAM0_FRAME_CNT_ERROR_IRQ,Stream 0 Frame count error interrupt" "0,1" newline bitfld.long 0x0 4. "STREAM0_FCC_STOP_IRQ,Stream 0 FCC stop interrupt" "0,1" newline bitfld.long 0x0 3. "STREAM0_FCC_START_IRQ,Stream 0 FCC start interrupt" "0,1" newline bitfld.long 0x0 2. "STREAM0_FRAME_IRQ,Stream 0 Frame interrupt" "0,1" newline bitfld.long 0x0 1. "STREAM0_LB_IRQ,Stream 0 Line/byte interrupt" "0,1" newline bitfld.long 0x0 0. "STREAM0_TIMER_IRQ,Stream 0 Timer interrupt" "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_monitor_irqs_mask_cfg,Monitor interrupt mask. Bit addressable mask register in order to independently enable" bitfld.long 0x4 31. "STREAM3_LINE_CNT_ERROR_IRQM,Interrupt mask for stream 3 Line count error." "0,1" newline bitfld.long 0x4 30. "STREAM3_FRAME_MISMATCH_IRQM,Interrupt mask for stream 3 Frame mismatch error." "0,1" newline bitfld.long 0x4 29. "STREAM3_FRAME_CNT_ERROR_IRQM,Interrupt mask for stream 3 Frame count error." "0,1" newline bitfld.long 0x4 28. "STREAM3_FCC_STOP_IRQM,Interrupt mask for stream 3 FCC stop." "0,1" newline bitfld.long 0x4 27. "STREAM3_FCC_START_IRQM,Interrupt mask for stream 3 FCC start." "0,1" newline bitfld.long 0x4 26. "STREAM3_FRAME_IRQM,Interrupt mask for stream 3 Frame." "0,1" newline bitfld.long 0x4 25. "STREAM3_LB_IRQM,Interrupt mask for stream 3 Line/byte." "0,1" newline bitfld.long 0x4 24. "STREAM3_TIMER_IRQM,Interrupt mask stream 3 Timer" "0,1" newline bitfld.long 0x4 23. "STREAM2_LINE_CNT_ERROR_IRQM,Interrupt mask for stream 2 Line count error." "0,1" newline bitfld.long 0x4 22. "STREAM2_FRAME_MISMATCH_IRQM,Interrupt mask for stream 2 Frame mismatch error." "0,1" newline bitfld.long 0x4 21. "STREAM2_FRAME_CNT_ERROR_IRQM,Interrupt mask for stream 2 Frame count error." "0,1" newline bitfld.long 0x4 20. "STREAM2_FCC_STOP_IRQM,Interrupt mask for stream 2 FCC stop." "0,1" newline bitfld.long 0x4 19. "STREAM2_FCC_START_IRQM,Interrupt mask for stream 2 FCC start." "0,1" newline bitfld.long 0x4 18. "STREAM2_FRAME_IRQM,Interrupt mask for stream 2 Frame." "0,1" newline bitfld.long 0x4 17. "STREAM2_LB_IRQM,Interrupt mask for stream 2 Line/byte." "0,1" newline bitfld.long 0x4 16. "STREAM2_TIMER_IRQM,Interrupt mask stream 2 Timer" "0,1" newline bitfld.long 0x4 15. "STREAM1_LINE_CNT_ERROR_IRQM,Interrupt mask for stream 1 Line count error." "0,1" newline bitfld.long 0x4 14. "STREAM1_FRAME_MISMATCH_IRQM,Interrupt mask for stream 1 Frame mismatch error." "0,1" newline bitfld.long 0x4 13. "STREAM1_FRAME_CNT_ERROR_IRQM,Interrupt mask for stream 1 Frame count error." "0,1" newline bitfld.long 0x4 12. "STREAM1_FCC_STOP_IRQM,Interrupt mask for stream 1 FCC stop." "0,1" newline bitfld.long 0x4 11. "STREAM1_FCC_START_IRQM,Interrupt mask for stream 1 FCC start." "0,1" newline bitfld.long 0x4 10. "STREAM1_FRAME_IRQM,Interrupt mask for stream 1 Frame." "0,1" newline bitfld.long 0x4 9. "STREAM1_LB_IRQM,Interrupt mask for stream 1 Line/byte." "0,1" newline bitfld.long 0x4 8. "STREAM1_TIMER_IRQM,Interrupt mask stream 1 Timer" "0,1" newline bitfld.long 0x4 7. "STREAM0_LINE_CNT_ERROR_IRQM,Interrupt mask for stream 0 Line count error." "0,1" newline bitfld.long 0x4 6. "STREAM0_FRAME_MISMATCH_IRQM,Interrupt mask for stream 0 Frame mismatch error." "0,1" newline bitfld.long 0x4 5. "STREAM0_FRAME_CNT_ERROR_IRQM,Interrupt mask for stream 0 Frame count error." "0,1" newline bitfld.long 0x4 4. "STREAM0_FCC_STOP_IRQM,Interrupt mask for stream 0 FCC stop." "0,1" newline bitfld.long 0x4 3. "STREAM0_FCC_START_IRQM,Interrupt mask for stream 0 FCC start." "0,1" newline bitfld.long 0x4 2. "STREAM0_FRAME_IRQM,Interrupt mask for stream 0 Frame." "0,1" newline bitfld.long 0x4 1. "STREAM0_LB_IRQM,Interrupt mask for stream 0 Line/byte." "0,1" newline bitfld.long 0x4 0. "STREAM0_TIMER_IRQM,Interrupt mask stream 0 Timer" "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_info_irqs,Information type Interrupt status (non-error conditions)" bitfld.long 0x8 14. "STREAM3_ABORT_IRQ,Stream 3 Abort process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 13. "STREAM3_STOP_IRQ,Stream 3 Stop process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 12. "STREAM2_ABORT_IRQ,Stream 2 Abort process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 11. "STREAM2_STOP_IRQ,Stream 2 Stop process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 10. "STREAM1_ABORT_IRQ,Stream 1 Abort process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 9. "STREAM1_STOP_IRQ,Stream 1 Stop process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 8. "STREAM0_ABORT_IRQ,Stream 0 Abort process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 7. "STREAM0_STOP_IRQ,Stream 0 Stop process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 6. "SP_GENERIC_RCVD_IRQ,A generic short packet has been received." "0,1" newline bitfld.long 0x8 5. "DESKEW_ENTRY_IRQ,Either clock or any datalane has entered deskew" "0,1" newline bitfld.long 0x8 4. "ECC_SPARES_NONZERO_IRQ,Bits 7:6 of the ECC byte are non-zero. Indicates non compliance with the MIPI specification although the core will continue to operate as normal." "0,1" newline bitfld.long 0x8 3. "WAKEUP_IRQ,Wake-up interrupt." "0,1" newline bitfld.long 0x8 2. "SLEEP_IRQ,Sleep interrupt." "0,1" newline bitfld.long 0x8 1. "LP_RCVD_IRQ,Long Packet received by the protocol module" "0,1" newline bitfld.long 0x8 0. "SP_RCVD_IRQ,Short Packet received by the protocol module" "0,1" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_info_irqs_mask_cfg,Information interrupt mask. Bit addressable mask register in order to independently enable" bitfld.long 0xC 14. "STREAM3_ABORT_IRQM,Interrupt mask for stream 3 Abort process." "0,1" newline bitfld.long 0xC 13. "STREAM3_STOP_IRQM,Interrupt mask for Stream 3 Stop process complete." "0,1" newline bitfld.long 0xC 12. "STREAM2_ABORT_IRQM,Interrupt mask for stream 2 Abort process." "0,1" newline bitfld.long 0xC 11. "STREAM2_STOP_IRQM,Interrupt mask for Stream 2 Stop process complete." "0,1" newline bitfld.long 0xC 10. "STREAM1_ABORT_IRQM,Interrupt mask for stream 1 Abort process." "0,1" newline bitfld.long 0xC 9. "STREAM1_STOP_IRQM,Interrupt mask for Stream 1 Stop process complete." "0,1" newline bitfld.long 0xC 8. "STREAM0_ABORT_IRQM,Interrupt mask for stream 0 Abort process." "0,1" newline bitfld.long 0xC 7. "STREAM0_STOP_IRQM,Interrupt mask for Stream 0 Stop process complete." "0,1" newline bitfld.long 0xC 6. "SP_GENERIC_RCVD_IRQM,Interrupt mask for Generic Short Packet received" "0,1" newline bitfld.long 0xC 5. "DESKEW_ENTRY_IRQM,Interrupt mask for Deskew entry check" "0,1" newline bitfld.long 0xC 4. "ECC_SPARES_NONZERO_IRQM,Interrupt mask for ECC spares check" "0,1" newline bitfld.long 0xC 3. "WAKEUP_IRQM,Interrupt mask for Wake-up interrupt." "0,1" newline bitfld.long 0xC 2. "SLEEP_IRQM,Interrupt mask for Sleep interrupt." "0,1" newline bitfld.long 0xC 1. "LP_RCVD_IRQM,Interrupt mask for Long Packet received flag" "0,1" newline bitfld.long 0xC 0. "SP_RCVD_IRQM,Interrupt mask for Short Packet received" "0,1" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_irqs,Datapath error interrupt status." bitfld.long 0x10 19. "STREAM3_FIFO_OVERFLOW_IRQ,Overflow of the Stream FIFO detected: stream_fifo_overflow[19] -> Stream 3 overflow" "0,1" newline bitfld.long 0x10 18. "STREAM2_FIFO_OVERFLOW_IRQ,Overflow of the Stream FIFO detected: stream_fifo_overflow[18] -> Stream 2 overflow" "0,1" newline bitfld.long 0x10 17. "STREAM1_FIFO_OVERFLOW_IRQ,Overflow of the Stream FIFO detected: stream_fifo_overflow[17] -> Stream 1 overflow" "0,1" newline bitfld.long 0x10 16. "STREAM0_FIFO_OVERFLOW_IRQ,Overflow of the Stream FIFO detected: stream_fifo_overflow[16] -> Stream 0 overflow" "0,1" newline bitfld.long 0x10 12. "FRONT_TRUNC_HDR_IRQ,A truncated header [short or Long] has been received" "0,1" newline bitfld.long 0x10 11. "PROT_TRUNCATED_PACKET_IRQ,A truncated Long packet has been received. Too few/many bytes" "0,1" newline bitfld.long 0x10 10. "FRONT_LP_NO_PAYLOAD_IRQ,A truncated Long packet has been received. No payload" "0,1" newline bitfld.long 0x10 9. "SP_INVALID_RCVD_IRQ,A reserved or invalid short packet has been received" "0,1" newline bitfld.long 0x10 8. "INVALID_ACCESS_IRQ,Invalid access to the configuration register space." "0,1" newline bitfld.long 0x10 7. "DATA_ID_IRQ,Data ID error has been detected in the header packet" "0,1" newline bitfld.long 0x10 6. "HEADER_CORRECTED_ECC_IRQ,ECC error has been detected and corrected." "0,1" newline bitfld.long 0x10 5. "HEADER_ECC_IRQ,Unrecoverable ECC error has been detected." "0,1" newline bitfld.long 0x10 4. "PAYLOAD_CRC_IRQ,CRC error has been detected." "0,1" newline bitfld.long 0x10 0. "FRONT_FIFO_OVERFLOW_IRQ,Overflow detected in resynchronization FIFO between DPHY Lane Management and Protocol blocks. This will occur if sys_clk is not fast enough and should be increased since the byte clock frequency is fixed" "0,1" line.long 0x14 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_irqs_mask_cfg,Datapath error interrupt enable Bits. This register is used to independently enable each event" bitfld.long 0x14 19. "STREAM3_FIFO_OVERFLOW_IRQM,Interrupt enable bit for: stream_fifo_overflow[19] -> Stream 3 overflow" "0,1" newline bitfld.long 0x14 18. "STREAM2_FIFO_OVERFLOW_IRQM,Interrupt enable bit for: stream_fifo_overflow[18] -> Stream 2 overflow" "0,1" newline bitfld.long 0x14 17. "STREAM1_FIFO_OVERFLOW_IRQM,Interrupt enable bit for: stream_fifo_overflow[17] -> Stream 1 overflow" "0,1" newline bitfld.long 0x14 16. "STREAM0_FIFO_OVERFLOW_IRQM,Interrupt enable bit for: stream_fifo_overflow[16] -> Stream 0 overflow" "0,1" newline bitfld.long 0x14 12. "FRONT_TRUNC_HDR_IRQM,Interrupt enable bit for truncated hdr." "0,1" newline bitfld.long 0x14 11. "PROT_TRUNCATED_PACKET_IRQM,Interrupt enable bit for long packet payload with too many/few bytes" "0,1" newline bitfld.long 0x14 10. "FRONT_LP_NO_PAYLOAD_IRQM,Interrupt enable bit for long packet header received with no payload" "0,1" newline bitfld.long 0x14 9. "SP_INVALID_RCVD_IRQM,Interrupt enable bit for invalid short packet" "0,1" newline bitfld.long 0x14 8. "INVALID_ACCESS_IRQM,Interrupt enable bit for error_irqs_invalid_access." "0,1" newline bitfld.long 0x14 7. "DATA_ID_IRQM,Interrupt enable bit for error_irqs_data_id" "0,1" newline bitfld.long 0x14 6. "HEADER_CORRECTED_ECC_IRQM,Interrupt enable bit for error_irqs_header_corrected_ecc" "0,1" newline bitfld.long 0x14 5. "HEADER_ECC_IRQM,Interrupt enable bit for error_irqs_header_ecc" "0,1" newline bitfld.long 0x14 4. "PAYLOAD_CRC_IRQM,Interrupt enable bit for error_irqs_payload_crc" "0,1" newline bitfld.long 0x14 0. "FRONT_FIFO_OVERFLOW_IRQM,Interrupt enable bit for error_irqs_front_fifo_overflow" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_lane_control,DPHY lane control for data and clock lanes enables and resets" bitfld.long 0x0 16. "CL_RESET,DPHY Clock lane Reset" "0,1" newline bitfld.long 0x0 15. "DL3_RESET,DPHY data lane 3 Reset" "0,1" newline bitfld.long 0x0 14. "DL2_RESET,DPHY data lane 2 Reset" "0,1" newline bitfld.long 0x0 13. "DL1_RESET,DPHY data lane 1 Reset" "0,1" newline bitfld.long 0x0 12. "DL0_RESET,DPHY data lane 0 Reset" "0,1" newline bitfld.long 0x0 4. "CL_ENABLE,DPHY Clock lane Enable" "0,1" newline bitfld.long 0x0 3. "DL3_ENABLE,DPHY data lane 3 Enable" "0,1" newline bitfld.long 0x0 2. "DL2_ENABLE,DPHY data lane 2 Enable" "0,1" newline bitfld.long 0x0 1. "DL1_ENABLE,DPHY data lane 1 Enable" "0,1" newline bitfld.long 0x0 0. "DL0_ENABLE,DPHY data lane 0 Enable" "0,1" rgroup.long 0x48++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_status,DPHY Clock and Data Lane mode status" bitfld.long 0x0 22. "DL3_RXULPSESC,DPHY Data lane 3 ULPS Esc" "0,1" newline bitfld.long 0x0 21. "DL3_ULPSACTIVENOT,DPHY Data lane 3 ULPSActiveNot" "0,1" newline bitfld.long 0x0 20. "DL3_STOPSTATE,DPHY Data lane 3 Stop State" "0,1" newline bitfld.long 0x0 18. "DL2_RXULPSESC,DPHY Data lane 2 ULPS Esc" "0,1" newline bitfld.long 0x0 17. "DL2_ULPSACTIVENOT,DPHY Data lane 2 ULPSActiveNot" "0,1" newline bitfld.long 0x0 16. "DL2_STOPSTATE,DPHY Data lane 2 Stop State" "0,1" newline bitfld.long 0x0 14. "DL1_RXULPSESC,DPHY Data lane 1 ULPS Esc" "0,1" newline bitfld.long 0x0 13. "DL1_ULPSACTIVENOT,DPHY Data lane 1 ULPSActiveNot" "0,1" newline bitfld.long 0x0 12. "DL1_STOPSTATE,DPHY Data lane 1 Stop State" "0,1" newline bitfld.long 0x0 10. "DL0_RXULPSESC,DPHY Data lane 0 ULPS Esc" "0,1" newline bitfld.long 0x0 9. "DL0_ULPSACTIVENOT,DPHY Data lane 0 ULPSActiveNot" "0,1" newline bitfld.long 0x0 8. "DL0_STOPSTATE,DPHY Data lane 0 Stop State" "0,1" newline bitfld.long 0x0 2. "CL_RXULPSCLKNOT,DPHY Clock lane RxULPSClkNot" "0,1" newline bitfld.long 0x0 1. "CL_ULPSACTIVENOT,DPHY Clock lane ULPSActiveNot" "0,1" newline bitfld.long 0x0 0. "CL_STOPSTATE,DPHY Clock lane Stop State" "0,1" rgroup.long 0x4C++0x7 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_err_status_irq,DPHY error interrupt status" bitfld.long 0x0 20. "DL3_ERRSOTHS_IRQ,DPHY Data lane 3 ErrSotHS" "0,1" newline bitfld.long 0x0 16. "DL2_ERRSOTHS_IRQ,DPHY Data lane 2 ErrSotHS" "0,1" newline bitfld.long 0x0 12. "DL1_ERRSOTHS_IRQ,DPHY Data lane 1 ErrSotHS" "0,1" newline bitfld.long 0x0 8. "DL0_ERRSOTHS_IRQ,DPHY Data lane 0 ErrSotHS" "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_err_irq_mask_cfg,DPHY error interrupt status" bitfld.long 0x4 20. "DL3_ERRSOTHS_IRQM,DPHY Data lane 3 ErrSotHS mask" "0,1" newline bitfld.long 0x4 16. "DL2_ERRSOTHS_IRQM,DPHY Data lane 2 ErrSotHS mask" "0,1" newline bitfld.long 0x4 12. "DL1_ERRSOTHS_IRQM,DPHY Data lane 1 ErrSotHS mask" "0,1" newline bitfld.long 0x4 8. "DL0_ERRSOTHS_IRQM,DPHY Data lane 0 ErrSotHS mask" "0,1" rgroup.long 0x60++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_integration_debug,Used to observe the current data field. extracted by the protocol block from the last" hexmask.long.byte 0x0 28.--31. 1. "PROT_FSM_STATE,csi2rx_fsm_state 0x1: WAIT_FOR_PACKET 0x2: PAYLOAD_DATA 0x4: PACKET_FOOTER_CHECK" newline hexmask.long.byte 0x0 22.--25. 1. "PROT_VC,Protocol Virtual Channel" newline hexmask.long.byte 0x0 16.--21. 1. "PROT_DT,Protocol Datatype" newline hexmask.long.word 0x0 0.--15. 1. "PROT_WORD_COUNT,Protocol Word Count [Data Field]" rgroup.long 0x74++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_debug,Error condition debug. After an error is detected by the CSI2RX. this register indicates which virtual channel." hexmask.long.word 0x0 16.--31. 1. "DATA_FIELD,Indicates the Data Field for an invalid CRC/ECC/Data ID" newline hexmask.long.byte 0x0 6.--9. 1. "VC,Indicates the Virtual Channel for a invalid CRC/ECC/Data ID" newline hexmask.long.byte 0x0 0.--5. 1. "DT,Indicates the Data Type for a invalid CRC/ECC/Data ID" rgroup.long 0x80++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_test_generic,Generic test control and status register that controls and reads primary I/O." hexmask.long.word 0x0 16.--31. 1. "STATUS,Test status - Directly reflects after resynchronisation into the pclk domain the state of 'test_generic_status' primary inputs." newline hexmask.long.word 0x0 0.--15. 1. "CTRL,Test control - Directly controls primary outputs 'test_generic_ctrl'" rgroup.long 0x100++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_ctrl,CSI2RX Stream Data output datapath control." bitfld.long 0x0 4. "SOFT_RST,Writing 1'b1 will apply a synchronous soft reset of this stream registers/FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT,Writing 1 this register will cause the csi2rx to stop streaming on the corresponding output immediately. This may corrupt the output protocol. stream_abort_irq is generated on completion of the abort operation." "0,1" newline bitfld.long 0x0 1. "STOP,Writing 1 in this register will cause csi2rx to stop streaming on the corresponding output at the end of the current frame. If the command is issued during frame blanking then the datapath will immediately stop streaming.." "0,1" newline bitfld.long 0x0 0. "START,Writing 1 in this register enables the corresponding datapath output. It will start streaming data at the start of the next frame that complies with the output configuration. stream_status[31] running indicates when data.." "0,1" rgroup.long 0x104++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_status,CSI2 Slave Controller Status. Contains useful debug information such as" bitfld.long 0x0 31. "RUNNING,The Stream is enabled" "0,1" newline bitfld.long 0x0 8. "READY_STATE,Indicates the state of the pushback signal pixel_ready_if for this stream" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "STREAM_FSM,Output to Stream FSM states: 0x0: STREAM_IDLE 0x1: STREAM_WAIT_CTRL_DATA // Expecting control data next 0x2: STREAM_CTRL // Check contents of Ctrl packet and extract header.." newline bitfld.long 0x0 0.--1. "PROTOCOL_FSM,Input to Stream FSM states: 0x0: PROT_IDLE 0x1: PROT_WAIT_CTRL 0x2: PROT_CTRL 0x3: PROT_DATA" "0: PROT_IDLE 0x1: PROT_WAIT_CTRL 0x2: PROT_CTRL..,?,?,?" rgroup.long 0x108++0xB line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_data_cfg,Secondary CSI2 Slave Controller Data outputs configuration." hexmask.long.word 0x0 16.--31. 1. "VC_SELECT,Selection of Virtual Channels to be processed: Default '0' -> All Virtual Channels are processed vc_select0[16] -> Virtual Channel Select 0 is processed vc_select1[17] -> Virtual Channel Select 1 is processed vc_select2[18] ->.." newline bitfld.long 0x0 15. "ENABLE_DT1,Enable processing of dt1" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "DATATYPE_SELECT1,Second data type format that this stream will process" newline bitfld.long 0x0 7. "ENABLE_DT0,Enable processing of dt0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "DATATYPE_SELECT0,First data type format that this stream will process" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_cfg,Primary CSI2 Slave Controller Data pixel outputs configuration." hexmask.long.word 0x4 16.--31. 1. "FIFO_FILL,Set the FIFO_FILL_LEVEL which is used to hold data in the FIFO until this level is reached before allow data to be pulled. This setting is only used when fifo_mode is set for Large Buffer operation" newline bitfld.long 0x4 12.--14. "BPP_BYPASS,Force unpacking of any Data type as selected RAW type. 0 - No bypass 1 - unpack as RAW6 2 - unpack as RAW7 3 - unpack as RAW8 4 - unpack as RAW10 5 - unpack as.." "0: No bypass 1,?,2: unpack as RAW7 3,?,4: unpack as RAW10 5,?,6: unpack as RAW14 7,?" newline bitfld.long 0x4 8.--9. "FIFO_MODE,Stream FIFO configuration which must be set in accordance to FIFO sizing flow control and the relationship between the link and pixel interface data rates. Refer to Use Case descriptions for further guidance on FIFO sizing and.." "0: Full Line Buffer,1: Large Buffer [Fill Level Controlled],?,?" newline bitfld.long 0x4 4.--5. "NUM_PIXELS,Number of pixels to output from the stream. Valid values are 1 2 4 and 8. The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be.." "0,1,2,3" newline bitfld.long 0x4 1. "LS_LE_MODE,Enable LS/LE control of HYSNC_VALID output. By default LS and LE short packets are not required and HYSC_VALID will be generated from the start and end of payload data." "0,1" newline bitfld.long 0x4 0. "INTERFACE_MODE,Select the output configuration. Pixel = 0 [default] Packed = 1" "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_monitor_ctrl,Stream Monitor configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_LENGTH,Indicates the frame length in lines to detect truncated frames. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low. 0x0000 means truncated.." newline bitfld.long 0x8 15. "FRAME_MON_EN,Enables monitor. This bit must only be set high after the frame_mon_vc and frame_length have been set." "0,1" newline hexmask.long.byte 0x8 11.--14. 1. "FRAME_MON_VC,Indicates virtual channel for monitor. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low." newline bitfld.long 0x8 10. "TIMER_EOF,Select the starting point of the timer: 0x0: Start of Frame event on selected virtual channel 0x1: End of Frame event on selected virtual channel. This value must not change while timer_en is enabled" "0: Start of Frame event on selected virtual channel..,?" newline bitfld.long 0x8 9. "TIMER_EN,Enables timer based interrupt. This bit must only be set high after the timer_eof and timer_vc have been set." "0,1" newline hexmask.long.byte 0x8 5.--8. 1. "TIMER_VC,Indicates which VC should be used to generate timer based interrupt. This value must not change while timer_en is enabled." newline bitfld.long 0x8 4. "LB_EN,Enables line/byte counter. This bit must only be set high after the lb_vc line_count and byte_count have been set." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "LB_VC,Indicates which VC should be used to generate line/byte counter interrupt. This value must not change while lb_en is enabled" rgroup.long 0x114++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_monitor_frame,Stream Monitor Frame." hexmask.long.word 0x0 16.--31. 1. "PACKET_SIZE,Size of the current payload" newline hexmask.long.word 0x0 0.--15. 1. "NB,Number of the last frame processed." rgroup.long 0x118++0x13 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_monitor_lb,Stream Monitor Line." hexmask.long.word 0x0 16.--31. 1. "LINE_COUNT,Indicates the line number to generate an interrupt. [First line of a Frame is line number 0]" newline hexmask.long.word 0x0 0.--15. 1. "BYTE_COUNT,Indicates the byte number of the line to generate an interrupt. [First byte of a line is byte number 0]" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_timer,Stream Timer." hexmask.long 0x4 0.--24. 1. "COUNT,Number of clock cycles" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_fcc_cfg,Stream Frame Capture Control configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_COUNT_STOP,Indicates the frame number on which the interrupt should be generated and the stream will stop outputting data on the pixel interface. [0x0000 will be continuous frames.]" newline hexmask.long.word 0x8 0.--15. 1. "FRAME_COUNT_START,Indicates the frame number on which the interrupt should be generated and the stream will start outputting data on the pixel interface. [0x0000 will be the current frame.]" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_fcc_ctrl,Stream Frame Capture Counter control." hexmask.long.word 0xC 16.--31. 1. "FRAME_COUNTER,Current Frame number being processed" newline hexmask.long.byte 0xC 1.--4. 1. "FCC_VC,Indicates which VC should be used to generate FCC interrupts. This value must not change while fcc_en is enabled" newline bitfld.long 0xC 0. "FCC_EN,Frame Capture Counter enable." "0,1" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_fifo_fill_lvl,Stream FIFO fill level monitor. This can operate in 2 modes:" bitfld.long 0x10 12.--13. "MODE,00 -> Fill level detection disabled 01 -> Mode 1 10 -> Mode 2 11 -> Reserved" "0: Fill level detection disabled 01,?,?,?" newline hexmask.long.word 0x10 0.--9. 1. "COUNT,Peak fill level of FIFO." rgroup.long 0x200++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_ctrl,CSI2RX Stream Data output datapath control." bitfld.long 0x0 4. "SOFT_RST,Writing 1'b1 will apply a synchronous soft reset of this stream registers/FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT,Writing 1 this register will cause the csi2rx to stop streaming on the corresponding output immediately. This may corrupt the output protocol. stream_abort_irq is generated on completion of the abort operation." "0,1" newline bitfld.long 0x0 1. "STOP,Writing 1 in this register will cause csi2rx to stop streaming on the corresponding output at the end of the current frame. If the command is issued during frame blanking then the datapath will immediately stop streaming.." "0,1" newline bitfld.long 0x0 0. "START,Writing 1 in this register enables the corresponding datapath output. It will start streaming data at the start of the next frame that complies with the output configuration. stream_status[31] running indicates when data.." "0,1" rgroup.long 0x204++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_status,CSI2 Slave Controller Status. Contains useful debug information such as" bitfld.long 0x0 31. "RUNNING,The Stream is enabled" "0,1" newline bitfld.long 0x0 8. "READY_STATE,Indicates the state of the pushback signal pixel_ready_if for this stream" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "STREAM_FSM,Output to Stream FSM states: 0x0: STREAM_IDLE 0x1: STREAM_WAIT_CTRL_DATA // Expecting control data next 0x2: STREAM_CTRL // Check contents of Ctrl packet and extract header.." newline bitfld.long 0x0 0.--1. "PROTOCOL_FSM,Input to Stream FSM states: 0x0: PROT_IDLE 0x1: PROT_WAIT_CTRL 0x2: PROT_CTRL 0x3: PROT_DATA" "0: PROT_IDLE 0x1: PROT_WAIT_CTRL 0x2: PROT_CTRL..,?,?,?" rgroup.long 0x208++0xB line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_data_cfg,Secondary CSI2 Slave Controller Data outputs configuration." hexmask.long.word 0x0 16.--31. 1. "VC_SELECT,Selection of Virtual Channels to be processed: Default '0' -> All Virtual Channels are processed vc_select0[16] -> Virtual Channel Select 0 is processed vc_select1[17] -> Virtual Channel Select 1 is processed vc_select2[18] ->.." newline bitfld.long 0x0 15. "ENABLE_DT1,Enable processing of dt1" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "DATATYPE_SELECT1,Second data type format that this stream will process" newline bitfld.long 0x0 7. "ENABLE_DT0,Enable processing of dt0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "DATATYPE_SELECT0,First data type format that this stream will process" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_cfg,Primary CSI2 Slave Controller Data pixel outputs configuration." hexmask.long.word 0x4 16.--31. 1. "FIFO_FILL,Set the FIFO_FILL_LEVEL which is used to hold data in the FIFO until this level is reached before allow data to be pulled. This setting is only used when fifo_mode is set for Large Buffer operation" newline bitfld.long 0x4 12.--14. "BPP_BYPASS,Force unpacking of any Data type as selected RAW type. 0 - No bypass 1 - unpack as RAW6 2 - unpack as RAW7 3 - unpack as RAW8 4 - unpack as RAW10 5 - unpack as.." "0: No bypass 1,?,2: unpack as RAW7 3,?,4: unpack as RAW10 5,?,6: unpack as RAW14 7,?" newline bitfld.long 0x4 8.--9. "FIFO_MODE,Stream FIFO configuration which must be set in accordance to FIFO sizing flow control and the relationship between the link and pixel interface data rates. Refer to Use Case descriptions for further guidance on FIFO sizing and.." "0: Full Line Buffer,1: Large Buffer [Fill Level Controlled],?,?" newline bitfld.long 0x4 4.--5. "NUM_PIXELS,Number of pixels to output from the stream. Valid values are 1 2 4 and 8. The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be.." "0,1,2,3" newline bitfld.long 0x4 1. "LS_LE_MODE,Enable LS/LE control of HYSNC_VALID output. By default LS and LE short packets are not required and HYSC_VALID will be generated from the start and end of payload data." "0,1" newline bitfld.long 0x4 0. "INTERFACE_MODE,Select the output configuration. Pixel = 0 [default] Packed = 1" "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_monitor_ctrl,Stream Monitor configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_LENGTH,Indicates the frame length in lines to detect truncated frames. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low. 0x0000 means truncated.." newline bitfld.long 0x8 15. "FRAME_MON_EN,Enables monitor. This bit must only be set high after the frame_mon_vc and frame_length have been set." "0,1" newline hexmask.long.byte 0x8 11.--14. 1. "FRAME_MON_VC,Indicates virtual channel for monitor. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low." newline bitfld.long 0x8 10. "TIMER_EOF,Select the starting point of the timer: 0x0: Start of Frame event on selected virtual channel 0x1: End of Frame event on selected virtual channel. This value must not change while timer_en is enabled" "0: Start of Frame event on selected virtual channel..,?" newline bitfld.long 0x8 9. "TIMER_EN,Enables timer based interrupt. This bit must only be set high after the timer_eof and timer_vc have been set." "0,1" newline hexmask.long.byte 0x8 5.--8. 1. "TIMER_VC,Indicates which VC should be used to generate timer based interrupt. This value must not change while timer_en is enabled." newline bitfld.long 0x8 4. "LB_EN,Enables line/byte counter. This bit must only be set high after the lb_vc line_count and byte_count have been set." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "LB_VC,Indicates which VC should be used to generate line/byte counter interrupt. This value must not change while lb_en is enabled" rgroup.long 0x214++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_monitor_frame,Stream Monitor Frame." hexmask.long.word 0x0 16.--31. 1. "PACKET_SIZE,Size of the current payload" newline hexmask.long.word 0x0 0.--15. 1. "NB,Number of the last frame processed." rgroup.long 0x218++0x13 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_monitor_lb,Stream Monitor Line." hexmask.long.word 0x0 16.--31. 1. "LINE_COUNT,Indicates the line number to generate an interrupt. [First line of a Frame is line number 0]" newline hexmask.long.word 0x0 0.--15. 1. "BYTE_COUNT,Indicates the byte number of the line to generate an interrupt. [First byte of a line is byte number 0]" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_timer,Stream Timer." hexmask.long 0x4 0.--24. 1. "COUNT,Number of clock cycles" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_fcc_cfg,Stream Frame Capture Control configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_COUNT_STOP,Indicates the frame number on which the interrupt should be generated and the stream will stop outputting data on the pixel interface. [0x0000 will be continuous frames.]" newline hexmask.long.word 0x8 0.--15. 1. "FRAME_COUNT_START,Indicates the frame number on which the interrupt should be generated and the stream will start outputting data on the pixel interface. [0x0000 will be the current frame.]" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_fcc_ctrl,Stream Frame Capture Counter control." hexmask.long.word 0xC 16.--31. 1. "FRAME_COUNTER,Current Frame number being processed" newline hexmask.long.byte 0xC 1.--4. 1. "FCC_VC,Indicates which VC should be used to generate FCC interrupts. This value must not change while fcc_en is enabled" newline bitfld.long 0xC 0. "FCC_EN,Frame Capture Counter enable." "0,1" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_fifo_fill_lvl,Stream FIFO fill level monitor. This can operate in 2 modes:" bitfld.long 0x10 12.--13. "MODE,00 -> Fill level detection disabled 01 -> Mode 1 10 -> Mode 2 11 -> Reserved" "0: Fill level detection disabled 01,?,?,?" newline hexmask.long.word 0x10 0.--9. 1. "COUNT,Peak fill level of FIFO." rgroup.long 0x300++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_ctrl,CSI2RX Stream Data output datapath control." bitfld.long 0x0 4. "SOFT_RST,Writing 1'b1 will apply a synchronous soft reset of this stream registers/FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT,Writing 1 this register will cause the csi2rx to stop streaming on the corresponding output immediately. This may corrupt the output protocol. stream_abort_irq is generated on completion of the abort operation." "0,1" newline bitfld.long 0x0 1. "STOP,Writing 1 in this register will cause csi2rx to stop streaming on the corresponding output at the end of the current frame. If the command is issued during frame blanking then the datapath will immediately stop streaming.." "0,1" newline bitfld.long 0x0 0. "START,Writing 1 in this register enables the corresponding datapath output. It will start streaming data at the start of the next frame that complies with the output configuration. stream_status[31] running indicates when data.." "0,1" rgroup.long 0x304++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_status,CSI2 Slave Controller Status. Contains useful debug information such as" bitfld.long 0x0 31. "RUNNING,The Stream is enabled" "0,1" newline bitfld.long 0x0 8. "READY_STATE,Indicates the state of the pushback signal pixel_ready_if for this stream" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "STREAM_FSM,Output to Stream FSM states: 0x0: STREAM_IDLE 0x1: STREAM_WAIT_CTRL_DATA // Expecting control data next 0x2: STREAM_CTRL // Check contents of Ctrl packet and extract header.." newline bitfld.long 0x0 0.--1. "PROTOCOL_FSM,Input to Stream FSM states: 0x0: PROT_IDLE 0x1: PROT_WAIT_CTRL 0x2: PROT_CTRL 0x3: PROT_DATA" "0: PROT_IDLE 0x1: PROT_WAIT_CTRL 0x2: PROT_CTRL..,?,?,?" rgroup.long 0x308++0xB line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_data_cfg,Secondary CSI2 Slave Controller Data outputs configuration." hexmask.long.word 0x0 16.--31. 1. "VC_SELECT,Selection of Virtual Channels to be processed: Default '0' -> All Virtual Channels are processed vc_select0[16] -> Virtual Channel Select 0 is processed vc_select1[17] -> Virtual Channel Select 1 is processed vc_select2[18] ->.." newline bitfld.long 0x0 15. "ENABLE_DT1,Enable processing of dt1" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "DATATYPE_SELECT1,Second data type format that this stream will process" newline bitfld.long 0x0 7. "ENABLE_DT0,Enable processing of dt0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "DATATYPE_SELECT0,First data type format that this stream will process" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_cfg,Primary CSI2 Slave Controller Data pixel outputs configuration." hexmask.long.word 0x4 16.--31. 1. "FIFO_FILL,Set the FIFO_FILL_LEVEL which is used to hold data in the FIFO until this level is reached before allow data to be pulled. This setting is only used when fifo_mode is set for Large Buffer operation" newline bitfld.long 0x4 12.--14. "BPP_BYPASS,Force unpacking of any Data type as selected RAW type. 0 - No bypass 1 - unpack as RAW6 2 - unpack as RAW7 3 - unpack as RAW8 4 - unpack as RAW10 5 - unpack as.." "0: No bypass 1,?,2: unpack as RAW7 3,?,4: unpack as RAW10 5,?,6: unpack as RAW14 7,?" newline bitfld.long 0x4 8.--9. "FIFO_MODE,Stream FIFO configuration which must be set in accordance to FIFO sizing flow control and the relationship between the link and pixel interface data rates. Refer to Use Case descriptions for further guidance on FIFO sizing and.." "0: Full Line Buffer,1: Large Buffer [Fill Level Controlled],?,?" newline bitfld.long 0x4 4.--5. "NUM_PIXELS,Number of pixels to output from the stream. Valid values are 1 2 4 and 8. The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be.." "0,1,2,3" newline bitfld.long 0x4 1. "LS_LE_MODE,Enable LS/LE control of HYSNC_VALID output. By default LS and LE short packets are not required and HYSC_VALID will be generated from the start and end of payload data." "0,1" newline bitfld.long 0x4 0. "INTERFACE_MODE,Select the output configuration. Pixel = 0 [default] Packed = 1" "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_monitor_ctrl,Stream Monitor configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_LENGTH,Indicates the frame length in lines to detect truncated frames. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low. 0x0000 means truncated.." newline bitfld.long 0x8 15. "FRAME_MON_EN,Enables monitor. This bit must only be set high after the frame_mon_vc and frame_length have been set." "0,1" newline hexmask.long.byte 0x8 11.--14. 1. "FRAME_MON_VC,Indicates virtual channel for monitor. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low." newline bitfld.long 0x8 10. "TIMER_EOF,Select the starting point of the timer: 0x0: Start of Frame event on selected virtual channel 0x1: End of Frame event on selected virtual channel. This value must not change while timer_en is enabled" "0: Start of Frame event on selected virtual channel..,?" newline bitfld.long 0x8 9. "TIMER_EN,Enables timer based interrupt. This bit must only be set high after the timer_eof and timer_vc have been set." "0,1" newline hexmask.long.byte 0x8 5.--8. 1. "TIMER_VC,Indicates which VC should be used to generate timer based interrupt. This value must not change while timer_en is enabled." newline bitfld.long 0x8 4. "LB_EN,Enables line/byte counter. This bit must only be set high after the lb_vc line_count and byte_count have been set." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "LB_VC,Indicates which VC should be used to generate line/byte counter interrupt. This value must not change while lb_en is enabled" rgroup.long 0x314++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_monitor_frame,Stream Monitor Frame." hexmask.long.word 0x0 16.--31. 1. "PACKET_SIZE,Size of the current payload" newline hexmask.long.word 0x0 0.--15. 1. "NB,Number of the last frame processed." rgroup.long 0x318++0x13 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_monitor_lb,Stream Monitor Line." hexmask.long.word 0x0 16.--31. 1. "LINE_COUNT,Indicates the line number to generate an interrupt. [First line of a Frame is line number 0]" newline hexmask.long.word 0x0 0.--15. 1. "BYTE_COUNT,Indicates the byte number of the line to generate an interrupt. [First byte of a line is byte number 0]" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_timer,Stream Timer." hexmask.long 0x4 0.--24. 1. "COUNT,Number of clock cycles" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_fcc_cfg,Stream Frame Capture Control configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_COUNT_STOP,Indicates the frame number on which the interrupt should be generated and the stream will stop outputting data on the pixel interface. [0x0000 will be continuous frames.]" newline hexmask.long.word 0x8 0.--15. 1. "FRAME_COUNT_START,Indicates the frame number on which the interrupt should be generated and the stream will start outputting data on the pixel interface. [0x0000 will be the current frame.]" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_fcc_ctrl,Stream Frame Capture Counter control." hexmask.long.word 0xC 16.--31. 1. "FRAME_COUNTER,Current Frame number being processed" newline hexmask.long.byte 0xC 1.--4. 1. "FCC_VC,Indicates which VC should be used to generate FCC interrupts. This value must not change while fcc_en is enabled" newline bitfld.long 0xC 0. "FCC_EN,Frame Capture Counter enable." "0,1" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_fifo_fill_lvl,Stream FIFO fill level monitor. This can operate in 2 modes:" bitfld.long 0x10 12.--13. "MODE,00 -> Fill level detection disabled 01 -> Mode 1 10 -> Mode 2 11 -> Reserved" "0: Fill level detection disabled 01,?,?,?" newline hexmask.long.word 0x10 0.--9. 1. "COUNT,Peak fill level of FIFO." rgroup.long 0x400++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_ctrl,CSI2RX Stream Data output datapath control." bitfld.long 0x0 4. "SOFT_RST,Writing 1'b1 will apply a synchronous soft reset of this stream registers/FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT,Writing 1 this register will cause the csi2rx to stop streaming on the corresponding output immediately. This may corrupt the output protocol. stream_abort_irq is generated on completion of the abort operation." "0,1" newline bitfld.long 0x0 1. "STOP,Writing 1 in this register will cause csi2rx to stop streaming on the corresponding output at the end of the current frame. If the command is issued during frame blanking then the datapath will immediately stop streaming.." "0,1" newline bitfld.long 0x0 0. "START,Writing 1 in this register enables the corresponding datapath output. It will start streaming data at the start of the next frame that complies with the output configuration. stream_status[31] running indicates when data.." "0,1" rgroup.long 0x404++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_status,CSI2 Slave Controller Status. Contains useful debug information such as" bitfld.long 0x0 31. "RUNNING,The Stream is enabled" "0,1" newline bitfld.long 0x0 8. "READY_STATE,Indicates the state of the pushback signal pixel_ready_if for this stream" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "STREAM_FSM,Output to Stream FSM states: 0x0: STREAM_IDLE 0x1: STREAM_WAIT_CTRL_DATA // Expecting control data next 0x2: STREAM_CTRL // Check contents of Ctrl packet and extract header.." newline bitfld.long 0x0 0.--1. "PROTOCOL_FSM,Input to Stream FSM states: 0x0: PROT_IDLE 0x1: PROT_WAIT_CTRL 0x2: PROT_CTRL 0x3: PROT_DATA" "0: PROT_IDLE 0x1: PROT_WAIT_CTRL 0x2: PROT_CTRL..,?,?,?" rgroup.long 0x408++0xB line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_data_cfg,Secondary CSI2 Slave Controller Data outputs configuration." hexmask.long.word 0x0 16.--31. 1. "VC_SELECT,Selection of Virtual Channels to be processed: Default '0' -> All Virtual Channels are processed vc_select0[16] -> Virtual Channel Select 0 is processed vc_select1[17] -> Virtual Channel Select 1 is processed vc_select2[18] ->.." newline bitfld.long 0x0 15. "ENABLE_DT1,Enable processing of dt1" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "DATATYPE_SELECT1,Second data type format that this stream will process" newline bitfld.long 0x0 7. "ENABLE_DT0,Enable processing of dt0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "DATATYPE_SELECT0,First data type format that this stream will process" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_cfg,Primary CSI2 Slave Controller Data pixel outputs configuration." hexmask.long.word 0x4 16.--31. 1. "FIFO_FILL,Set the FIFO_FILL_LEVEL which is used to hold data in the FIFO until this level is reached before allow data to be pulled. This setting is only used when fifo_mode is set for Large Buffer operation" newline bitfld.long 0x4 12.--14. "BPP_BYPASS,Force unpacking of any Data type as selected RAW type. 0 - No bypass 1 - unpack as RAW6 2 - unpack as RAW7 3 - unpack as RAW8 4 - unpack as RAW10 5 - unpack as.." "0: No bypass 1,?,2: unpack as RAW7 3,?,4: unpack as RAW10 5,?,6: unpack as RAW14 7,?" newline bitfld.long 0x4 8.--9. "FIFO_MODE,Stream FIFO configuration which must be set in accordance to FIFO sizing flow control and the relationship between the link and pixel interface data rates. Refer to Use Case descriptions for further guidance on FIFO sizing and.." "0: Full Line Buffer,1: Large Buffer [Fill Level Controlled],?,?" newline bitfld.long 0x4 4.--5. "NUM_PIXELS,Number of pixels to output from the stream. Valid values are 1 2 4 and 8. The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be.." "0,1,2,3" newline bitfld.long 0x4 1. "LS_LE_MODE,Enable LS/LE control of HYSNC_VALID output. By default LS and LE short packets are not required and HYSC_VALID will be generated from the start and end of payload data." "0,1" newline bitfld.long 0x4 0. "INTERFACE_MODE,Select the output configuration. Pixel = 0 [default] Packed = 1" "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_monitor_ctrl,Stream Monitor configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_LENGTH,Indicates the frame length in lines to detect truncated frames. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low. 0x0000 means truncated.." newline bitfld.long 0x8 15. "FRAME_MON_EN,Enables monitor. This bit must only be set high after the frame_mon_vc and frame_length have been set." "0,1" newline hexmask.long.byte 0x8 11.--14. 1. "FRAME_MON_VC,Indicates virtual channel for monitor. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low." newline bitfld.long 0x8 10. "TIMER_EOF,Select the starting point of the timer: 0x0: Start of Frame event on selected virtual channel 0x1: End of Frame event on selected virtual channel. This value must not change while timer_en is enabled" "0: Start of Frame event on selected virtual channel..,?" newline bitfld.long 0x8 9. "TIMER_EN,Enables timer based interrupt. This bit must only be set high after the timer_eof and timer_vc have been set." "0,1" newline hexmask.long.byte 0x8 5.--8. 1. "TIMER_VC,Indicates which VC should be used to generate timer based interrupt. This value must not change while timer_en is enabled." newline bitfld.long 0x8 4. "LB_EN,Enables line/byte counter. This bit must only be set high after the lb_vc line_count and byte_count have been set." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "LB_VC,Indicates which VC should be used to generate line/byte counter interrupt. This value must not change while lb_en is enabled" rgroup.long 0x414++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_monitor_frame,Stream Monitor Frame." hexmask.long.word 0x0 16.--31. 1. "PACKET_SIZE,Size of the current payload" newline hexmask.long.word 0x0 0.--15. 1. "NB,Number of the last frame processed." rgroup.long 0x418++0x13 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_monitor_lb,Stream Monitor Line." hexmask.long.word 0x0 16.--31. 1. "LINE_COUNT,Indicates the line number to generate an interrupt. [First line of a Frame is line number 0]" newline hexmask.long.word 0x0 0.--15. 1. "BYTE_COUNT,Indicates the byte number of the line to generate an interrupt. [First byte of a line is byte number 0]" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_timer,Stream Timer." hexmask.long 0x4 0.--24. 1. "COUNT,Number of clock cycles" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_fcc_cfg,Stream Frame Capture Control configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_COUNT_STOP,Indicates the frame number on which the interrupt should be generated and the stream will stop outputting data on the pixel interface. [0x0000 will be continuous frames.]" newline hexmask.long.word 0x8 0.--15. 1. "FRAME_COUNT_START,Indicates the frame number on which the interrupt should be generated and the stream will start outputting data on the pixel interface. [0x0000 will be the current frame.]" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_fcc_ctrl,Stream Frame Capture Counter control." hexmask.long.word 0xC 16.--31. 1. "FRAME_COUNTER,Current Frame number being processed" newline hexmask.long.byte 0xC 1.--4. 1. "FCC_VC,Indicates which VC should be used to generate FCC interrupts. This value must not change while fcc_en is enabled" newline bitfld.long 0xC 0. "FCC_EN,Frame Capture Counter enable." "0,1" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_fifo_fill_lvl,Stream FIFO fill level monitor. This can operate in 2 modes:" bitfld.long 0x10 12.--13. "MODE,00 -> Fill level detection disabled 01 -> Mode 1 10 -> Mode 2 11 -> Reserved" "0: Fill level detection disabled 01,?,?,?" newline hexmask.long.word 0x10 0.--9. 1. "COUNT,Peak fill level of FIFO." rgroup.long 0x900++0x13 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_int_status,ASF Interrupt Status Register. This register indicates the source of ASF interrupts. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register the.." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x0 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1" newline bitfld.long 0x0 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1" newline bitfld.long 0x0 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1" newline bitfld.long 0x0 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x0 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1" newline bitfld.long 0x0 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x0 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_int_raw_status,ASF Interrupt Raw Status Register. A bit set in this raw register indicates a source of ASF fault in the corresponding feature. Writing to either raw or masked status registers. clear both.." hexmask.long 0x4 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x4 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1" newline bitfld.long 0x4 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1" newline bitfld.long 0x4 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1" newline bitfld.long 0x4 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x4 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1" newline bitfld.long 0x4 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x4 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_int_mask,The ASF interrupt mask register indicating which interrupt bits in the ASF interrupt status register are masked. All bits are set at reset. Clear the individual bit to enable the corresponding interrupt." hexmask.long 0x8 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x8 6. "ASF_INTEGRITY_ERR_MASK,Mask bit for integrity error interrupt" "0,1" newline bitfld.long 0x8 5. "ASF_PROTOCOL_ERR_MASK,Mask bit for protocol error interrupt." "0,1" newline bitfld.long 0x8 4. "ASF_TRANS_TO_ERR_MASK,Mask bit for transaction timeouts error interrupt." "0,1" newline bitfld.long 0x8 3. "ASF_CSR_ERR_MASK,Mask bit for configuration and status registers error interrupt." "0,1" newline bitfld.long 0x8 2. "ASF_DAP_ERR_MASK,Mask bit for data and address paths parity error interrupt." "0,1" newline bitfld.long 0x8 1. "ASF_SRAM_UNCORR_ERR_MASK,Mask bit for SRAM uncorrectable error interrupt." "0,1" newline bitfld.long 0x8 0. "ASF_SRAM_CORR_ERR_MASK,Mask bit for SRAM correctable error interrupt." "0,1" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_int_test,The ASF interrupt test register emulate hardware even. Write one to individual bit to trigger single event in (masked and raw) status registers according to mask and will generate interrupt accordingly." hexmask.long 0xC 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0xC 6. "ASF_INTEGRITY_ERR_TEST,Test bit for integrity error interrupt" "0,1" newline bitfld.long 0xC 5. "ASF_PROTOCOL_ERR_TEST,Test bit for protocol error interrupt." "0,1" newline bitfld.long 0xC 4. "ASF_TRANS_TO_ERR_TEST,Test bit for transaction timeouts error interrupt." "0,1" newline bitfld.long 0xC 3. "ASF_CSR_ERR_TEST,Test bit for configuration and status registers error interrupt." "0,1" newline bitfld.long 0xC 2. "ASF_DAP_ERR_TEST,Test bit for data and address paths parity error interrupt." "0,1" newline bitfld.long 0xC 1. "ASF_SRAM_UNCORR_ERR_TEST,Test bit for SRAM uncorrectable error interrupt." "0,1" newline bitfld.long 0xC 0. "ASF_SRAM_CORR_ERR_TEST,Test bit for SRAM correctable error interrupt." "0,1" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_fatal_nonfatal_select,The fatal or non-fatal interrupt register selects whether a fatal (asf_int_fatal) or non-fatal (asf_int_nonfatal) interrupt is triggered. If the bit of the event will be set to one then.." hexmask.long 0x10 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x10 6. "ASF_INTEGRITY_ERR,Enable integrity error interrupt as fatal" "0,1" newline bitfld.long 0x10 5. "ASF_PROTOCOL_ERR,Enable protocol error interrupt as fatal." "0,1" newline bitfld.long 0x10 4. "ASF_TRANS_TO_ERR,Enable transaction timeouts error interrupt as fatal." "0,1" newline bitfld.long 0x10 3. "ASF_CSR_ERR,Enable configuration and status registers error interrupt as fatal." "0,1" newline bitfld.long 0x10 2. "ASF_DAP_ERR,Enable data and address paths parity error interrupt as fatal." "0,1" newline bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR,Enable SRAM uncorrectable error interrupt as fatal." "0,1" newline bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR,Enable SRAM correctable error interrupt as fatal." "0,1" rgroup.long 0x920++0x7 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_sram_corr_fault_status,Status register for SRAM correctable fault. These fields are updated whenever asf_sram_corr_fault input is active." hexmask.long.byte 0x0 24.--31. 1. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault." newline hexmask.long.tbyte 0x0 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault." line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_sram_uncorr_fault_status,Status register for SRAM uncorrectable fault. These fields are updated whenever asf_sram_uncorr_fault input is active." hexmask.long.byte 0x4 24.--31. 1. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault." newline hexmask.long.tbyte 0x4 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault." rgroup.long 0x928++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_sram_fault_stats,Statistics register for SRAM faults. Note that this register clears when software writes to any field." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline hexmask.long.word 0x0 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS,Count of number of correctable errors if implemented. Count value will saturate at 0xffff." rgroup.long 0x930++0xB line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_trans_to_ctrl,Control register to configure the ASF transaction timeout monitors." bitfld.long 0x0 31. "ASF_TRANS_TO_EN,Enable transaction timeout monitoring." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "ASF_TRANS_TO_CTRL,Timer value to use for transaction timeout monitor." line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_trans_to_fault_mask,Control register to mask out ASF transaction timeout faults from triggering interrupts. On reset. all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt.." bitfld.long 0x4 0. "ASF_TRANS_TO_FAULT_0_MASK,Mask register for each ASF transaction timeout fault source." "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_trans_to_fault_status,Status register for transaction timeouts fault. If a fault occurs the revelant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit." bitfld.long 0x8 0. "ASF_TRANS_TO_FAULT_0_STATUS,Status bits for transaction timeouts faults." "0,1" rgroup.long 0x940++0x7 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_protocol_fault_mask,Control register to mask out ASF Protocol faults from triggering interrupts. On reset. all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt source. The.." bitfld.long 0x0 13. "ASF_PROTOCOL_FAULT_13_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 12. "ASF_PROTOCOL_FAULT_12_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 11. "ASF_PROTOCOL_FAULT_11_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 10. "ASF_PROTOCOL_FAULT_10_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 9. "ASF_PROTOCOL_FAULT_9_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 8. "ASF_PROTOCOL_FAULT_8_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 7. "ASF_PROTOCOL_FAULT_7_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 6. "ASF_PROTOCOL_FAULT_6_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 5. "ASF_PROTOCOL_FAULT_5_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 4. "ASF_PROTOCOL_FAULT_4_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 3. "ASF_PROTOCOL_FAULT_3_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 2. "ASF_PROTOCOL_FAULT_2_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 1. "ASF_PROTOCOL_FAULT_1_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 0. "ASF_PROTOCOL_FAULT_0_MASK,Mask register for each ASF protocol fault source." "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_protocol_fault_status,Status register for protocol faults. If a fault occurs the revelant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit" bitfld.long 0x4 13. "ASF_PROTOCOL_FAULT_13_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 12. "ASF_PROTOCOL_FAULT_12_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 11. "ASF_PROTOCOL_FAULT_11_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 10. "ASF_PROTOCOL_FAULT_10_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 9. "ASF_PROTOCOL_FAULT_9_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 8. "ASF_PROTOCOL_FAULT_8_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 7. "ASF_PROTOCOL_FAULT_7_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 6. "ASF_PROTOCOL_FAULT_6_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 5. "ASF_PROTOCOL_FAULT_5_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 4. "ASF_PROTOCOL_FAULT_4_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 3. "ASF_PROTOCOL_FAULT_3_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 2. "ASF_PROTOCOL_FAULT_2_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 1. "ASF_PROTOCOL_FAULT_1_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 0. "ASF_PROTOCOL_FAULT_0_STATUS,Status bits for protocol faults." "0,1" rgroup.long 0xFFC++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_id_prod_ver,This register is hard-coded in order to allow software to identify the product and its" hexmask.long.word 0x0 16.--31. 1. "PRODUCT_ID,Product Identification Number [IP5022/IP5022A]." newline hexmask.long.word 0x0 0.--15. 1. "VERSION_ID,Product Version Number [R200]." tree.end tree.end tree.end tree "csi_tx_if_v2" tree "csi_tx_if_v2_0_CP_INTD_CFG_INTD_CFG (csi_tx_if_v2_0_CP_INTD_CFG_INTD_CFG)" base ad:0x4408000 rgroup.long 0x0++0x3 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_REVISION,Revision Register" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,RTL revisions" newline bitfld.long 0x0 8.--10. "MAJREV,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom revision" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_eoi_reg,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector" rgroup.long 0x14++0x3 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg,Interrupt Vector Register" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR,Interrupt Vector Register" rgroup.long 0x100++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_0,Enable Register 0" bitfld.long 0x0 1. "ENABLE_LEVEL_EN_STRM_SEL,Enable Set for level_en_strm_sel" "0,1" bitfld.long 0x0 0. "ENABLE_LEVEL_EN_RETRANS,Enable Set for level_en_retrans" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_0,Enable Register 1" bitfld.long 0x4 1. "ENABLE_PULSE_EN_STRM_SEL,Enable Set for pulse_en_strm_sel" "0,1" bitfld.long 0x4 0. "ENABLE_PULSE_EN_RETRANS,Enable Set for pulse_en_retrans" "0,1" rgroup.long 0x300++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_0,Enable Clear Register 0" bitfld.long 0x0 1. "ENABLE_LEVEL_EN_STRM_SEL_CLR,Enable Clear for level_en_strm_sel" "0,1" bitfld.long 0x0 0. "ENABLE_LEVEL_EN_RETRANS_CLR,Enable Clear for level_en_retrans" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_0,Enable Clear Register 1" bitfld.long 0x4 1. "ENABLE_PULSE_EN_STRM_SEL_CLR,Enable Clear for pulse_en_strm_sel" "0,1" bitfld.long 0x4 0. "ENABLE_PULSE_EN_RETRANS_CLR,Enable Clear for pulse_en_retrans" "0,1" rgroup.long 0x500++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_0,Status Register 0" bitfld.long 0x0 1. "STATUS_LEVEL_STRM_SEL,Status write 1 to set for level_en_strm_sel" "0,1" bitfld.long 0x0 0. "STATUS_LEVEL_RETRANS,Status write 1 to set for level_en_retrans" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_0,Status Register 1" bitfld.long 0x4 1. "STATUS_PULSE_STRM_SEL,Status write 1 to set for pulse_en_strm_sel" "0,1" bitfld.long 0x4 0. "STATUS_PULSE_RETRANS,Status write 1 to set for pulse_en_retrans" "0,1" rgroup.long 0x700++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_0,Status Clear Register 0" bitfld.long 0x0 1. "STATUS_LEVEL_STRM_SEL_CLR,Status write 1 to clear for level_en_strm_sel" "0,1" bitfld.long 0x0 0. "STATUS_LEVEL_RETRANS_CLR,Status write 1 to clear for level_en_retrans" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_0,Status Clear Register 1" bitfld.long 0x4 1. "STATUS_PULSE_STRM_SEL_CLR,Status write 1 to clear for pulse_en_strm_sel" "0,1" bitfld.long 0x4 0. "STATUS_PULSE_RETRANS_CLR,Status write 1 to clear for pulse_en_retrans" "0,1" rgroup.long 0xA80++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_level,Interrupt Vector for level" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR_LEVEL,Interrupt Vector" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_pulse,Interrupt Vector for pulse" hexmask.long 0x4 0.--31. 1. "INTR_VECTOR_PULSE,Interrupt Vector" tree.end tree "csi_tx_if_v2_0_ECC_AGGR_BYTE_CFG (csi_tx_if_v2_0_ECC_AGGR_BYTE_CFG)" base ad:0x2A38400 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_BYTE__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "ECC_AGGR_BYTE__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_BYTE__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "ECC_AGGR_BYTE__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_BYTE__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_BYTE__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "RAM_RAMECC1_PEND,Interrupt Pending Status for ram_ramecc1_pend" "0,1" bitfld.long 0x4 0. "RAM_RAMECC0_PEND,Interrupt Pending Status for ram_ramecc0_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "ECC_AGGR_BYTE__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "RAM_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc1_pend" "0,1" bitfld.long 0x0 0. "RAM_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc0_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_BYTE__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "RAM_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc1_pend" "0,1" bitfld.long 0x0 0. "RAM_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc0_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_BYTE__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_BYTE__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "RAM_RAMECC1_PEND,Interrupt Pending Status for ram_ramecc1_pend" "0,1" bitfld.long 0x4 0. "RAM_RAMECC0_PEND,Interrupt Pending Status for ram_ramecc0_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "ECC_AGGR_BYTE__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "RAM_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc1_pend" "0,1" bitfld.long 0x0 0. "RAM_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc0_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_BYTE__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "RAM_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc1_pend" "0,1" bitfld.long 0x0 0. "RAM_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc0_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "ECC_AGGR_BYTE__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_BYTE__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_BYTE__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_BYTE__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "csi_tx_if_v2_0_ECC_AGGR_CFG (csi_tx_if_v2_0_ECC_AGGR_CFG)" base ad:0x2A38000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "FDRAM_RAMECC_PEND,Interrupt Pending Status for fdram_ramecc_pend" "0,1" bitfld.long 0x4 1. "FIFO_RAMECC_PEND,Interrupt Pending Status for fifo_ramecc_pend" "0,1" bitfld.long 0x4 0. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "FDRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fdram_ramecc_pend" "0,1" bitfld.long 0x0 1. "FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "FDRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fdram_ramecc_pend" "0,1" bitfld.long 0x0 1. "FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "FDRAM_RAMECC_PEND,Interrupt Pending Status for fdram_ramecc_pend" "0,1" bitfld.long 0x4 1. "FIFO_RAMECC_PEND,Interrupt Pending Status for fifo_ramecc_pend" "0,1" bitfld.long 0x4 0. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "FDRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fdram_ramecc_pend" "0,1" bitfld.long 0x0 1. "FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "FDRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fdram_ramecc_pend" "0,1" bitfld.long 0x0 1. "FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "csi_tx_if_v2_0_TX_SHIM_VBUSP_MMR_CSI2TXIF_V2 (csi_tx_if_v2_0_TX_SHIM_VBUSP_MMR_CSI2TXIF_V2)" base ad:0x4400000 rgroup.long 0x0++0x3 line.long 0x0 "TX_SHIM__VBUSP_MMR__CSI2TXIF_V2_REGS_csitx_id,PID" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,function" newline hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom revision" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,min revision" rgroup.long 0x4++0xB line.long 0x0 "TX_SHIM__VBUSP_MMR__CSI2TXIF_V2_REGS_color_cntl,color bar control register" hexmask.long.byte 0x0 16.--19. 1. "VCHNL,color bar virtual channel" bitfld.long 0x0 8.--10. "DTYPE,color bar data type data sel" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "EN,1: enable" "?,1: enable" line.long 0x4 "TX_SHIM__VBUSP_MMR__CSI2TXIF_V2_REGS_color_param,color bar frame parameters" hexmask.long.word 0x4 16.--28. 1. "IH_CFG,input height in units of pixels minus 1." hexmask.long.word 0x4 0.--12. 1. "IW_CFG,input width in units of pixels minus 1." line.long 0x8 "TX_SHIM__VBUSP_MMR__CSI2TXIF_V2_REGS_color_start_delay,delay from starting first line after enabling" hexmask.long 0x8 0.--31. 1. "LINE_DELAY,delay in terms of main clock cycles before sending first line after enabling." rgroup.long 0x20++0x7 line.long 0x0 "TX_SHIM__VBUSP_MMR__CSI2TXIF_V2_REGS_color_line_delay,last line start to next line start delay" hexmask.long 0x0 0.--31. 1. "LINE_DELAY,delay in terms of main clock cycles from line start to next line start" line.long 0x4 "TX_SHIM__VBUSP_MMR__CSI2TXIF_V2_REGS_color_frame_delay,line start to next frame start delay" hexmask.long 0x4 0.--31. 1. "FRAME_DELAY,delay in terms of main clock cycles from last line start to start of next frame" rgroup.long 0x2C++0x3 line.long 0x0 "TX_SHIM__VBUSP_MMR__CSI2TXIF_V2_REGS_control1,control register for csi tx wrapper" bitfld.long 0x0 16. "STRM_SEL,select to switch dma versus retransmit interface mux 0=dma 1=retransmit" "0: dma,1: retransmit" rbitfld.long 0x0 9. "STREAM1_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1" rbitfld.long 0x0 8. "STREAM0_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1" newline bitfld.long 0x0 0. "PIXEL_RESET,reset for the pixeal interface. 0=reset 1 not in reset. this should be asserted till after you program the csi controller configuration registers" "0: reset,?" rgroup.long 0x40++0x3 line.long 0x0 "TX_SHIM__VBUSP_MMR__CSI2TXIF_V2_REGS_f2f_delay,last line start to next frame start. Configuration for each of 16 virtual channels." hexmask.long 0x0 0.--31. 1. "DELAY,counter value delay of last line start of frame to first line of next frame" rgroup.long 0x100++0xF line.long 0x0 "TX_SHIM__VBUSP_MMR__CSI2TXIF_V2_REGS_dmaCntx,DMA Channel Context. Configuration for each of 32 possible threads. Illegal to program 2 threads with same virtual channel and data type values" bitfld.long 0x0 26.--27. "YUV422_MODE_CFG,yuv422 mode 00:UYVY 01:VYUY 10:YUYV 11:YVYU" "0: UYVY,1: VYUY,?,?" bitfld.long 0x0 23. "PACK12_CFG,pack12 format enable 0. used in conjunction with size for proper packing: not pack12 /n 1: pack12" "?,1: pack12" bitfld.long 0x0 20.--21. "SIZE_CFG,data size shift when unpacking 00=8 01=16 10=32 11=RSVD" "0,1,2,3" newline hexmask.long.byte 0x0 6.--9. 1. "VIRTCH_CFG,CSI virtual channel index. Supplied by MIPI CSI protocol to DPHY. For CSIver1.3 program 2MSb==0" hexmask.long.byte 0x0 0.--5. 1. "DATATYPE_CFG,CSI data type. Supplied by MIPI CSI protocol to DPHY" line.long 0x4 "TX_SHIM__VBUSP_MMR__CSI2TXIF_V2_REGS_l2l_delay,line to line delay. Configuration for each of 32 possible channel contexts." hexmask.long 0x4 0.--31. 1. "DELAY,counter value delay line start to next line start within a frame" line.long 0x8 "TX_SHIM__VBUSP_MMR__CSI2TXIF_V2_REGS_bytecnt,number of bytes in a line per context thread" hexmask.long.word 0x8 0.--15. 1. "BYTECNT,byte count in a line" line.long 0xC "TX_SHIM__VBUSP_MMR__CSI2TXIF_V2_REGS_l2f_delay,line to frame delay. Configuration for each of 32 possible channel contexts." hexmask.long 0xC 0.--31. 1. "DELAY,counter value delay line end to end of frame" tree.end tree "csi_tx_if_v2_0_VBUS2APB_WRAP_VBUSP_APB_CSI2TX_V2 (csi_tx_if_v2_0_VBUS2APB_WRAP_VBUSP_APB_CSI2TX_V2)" base ad:0x4404000 rgroup.long 0x0++0x7 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_device_config,CSI-2 Transmitter Device Configuration Register" bitfld.long 0x0 26. "V1_3_FEATURES,: 1=CSI-2 v1.3 features only 0=v2.1 features available" "0: v2,1: CSI-2 v1" newline bitfld.long 0x0 25. "RX_COMP_MODE_PRESENT,RX Compatibility Mode: 1=implemented" "?,1: implemented" newline bitfld.long 0x0 20. "SCRAMBLER_PRESENT,Scrambler: 1=implemented" "?,1: implemented" newline bitfld.long 0x0 19. "ASF_PRESENT,Automotive Safety Features: 1=implemented" "?,1: implemented" newline hexmask.long.byte 0x0 14.--18. 1. "NUM_DTS,Number of Datatypes supported 8 or 16 only" newline hexmask.long.byte 0x0 9.--13. 1. "NUM_VCS,Number of Virtual Channels supported 4 or 16 only" newline bitfld.long 0x0 7.--8. "DATAPATH_SIZE,Internal datapath width 00: 32-bit." "0,1,2,3" newline bitfld.long 0x0 4.--6. "NUM_STREAMS,Number of Stream interfaces 1 2 or 4 only using direct encoding" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "CDNS_PHY_PRESENT,Cadence D-PHY present 1 = Yes" "?,1: Yes" newline bitfld.long 0x0 0.--2. "MAX_LANE_NB,Max Number of Lanes [1-4]" "0,1,2,3,4,5,6,7" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_status,CSI-2 Transmitter Status Register" bitfld.long 0x4 7. "RX_COMP_MODE_ACTIVE,RX Compatibility Mode Active Flag. When HIGH this bit indicates that RX Compatibility Mode is enabled." "0,1" newline bitfld.long 0x4 6. "ULP_MODE_ACTIVE,Ultra Low Power Mode Active Flag When HIGH this bit indicates that Ultra Low Power mode is active." "0,1" newline bitfld.long 0x4 5. "HS_MODE_ACTIVE,High Speed Mode Active Flag When HIGH this bit indicates that High Speed mode is active." "0,1" newline bitfld.long 0x4 4. "FRAME_TRANSMISSION_ACTIVE,Frame Transmission Active Flag When HIGH this bit indicates that frame transmission is active." "0,1" newline bitfld.long 0x4 3. "SCRAMBLER_ACTIVE,Scrambler Active Flag. When HIGH this bit indicates that the scrambler is enabled." "0,1" newline bitfld.long 0x4 2. "CONFIGURATION_ACTIVE,Configuration Mode Active Flag When HIGH this bit indicates that the CSI2TX module is in the configuration mode." "0,1" newline bitfld.long 0x4 1. "SOFT_RESET_ACTIVE,Soft Reset Active Flag When HIGH this bit indicates that soft reset is active." "0,1" newline bitfld.long 0x4 0. "BYPASS_MODE_ACTIVE,Bypass Mode Active Flag When HIGH this bit indicates that bypass mode is active." "0,1" rgroup.long 0x8++0xF line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_irq,CSI-2 Transmitter Interrupt Register. Write '1' to clear" bitfld.long 0x0 31. "LINE_NUMBER_ERROR3,Pixel IF 3 Line Number Error Flag - When HIGH this bit indicates that a line number error occurred." "0,1" newline bitfld.long 0x0 30. "BYTE_COUNT_MISMATCH_IRQ3,Pixel IF 3 Byte Count Mismatch Flag - When HIGH this bit indicates that a byte count mismatch occurred." "0,1" newline bitfld.long 0x0 29. "DATA_FLOW_ERR_IRQ3,Pixel IF 3 Data Flow Error Flag - When HIGH this bit indicates that data flow error has occurred caused by the Frame/Line valid being asserted when the D-PHY is not ready." "0,1" newline bitfld.long 0x0 28. "FIFO_UNDERFLOW_IRQ3,Pixel IF 3 FIFO Underflow Flag - When HIGH this bit indicates that at least one internal FIFO underflow occurred." "0,1" newline bitfld.long 0x0 27. "LINE_END_IRQ3,Pixel IF 3 Line End Flag - When HIGH this bit indicates that a line end occurred." "0,1" newline bitfld.long 0x0 26. "LINE_START_IRQ3,Pixel IF 3 Line Start Flag - When HIGH this bit indicates that a line start occurred." "0,1" newline bitfld.long 0x0 25. "FRAME_END_IRQ3,Pixel IF 3 Frame End Flag - When HIGH this bit indicates that a frame end occurred." "0,1" newline bitfld.long 0x0 24. "FRAME_START_IRQ3,Pixel IF 3 Frame Start Flag - When HIGH this bit indicates that a frame start occurred." "0,1" newline bitfld.long 0x0 23. "LINE_NUMBER_ERROR2,Pixel IF 2 Line Number Error Flag - When HIGH this bit indicates that a line number error occurred." "0,1" newline bitfld.long 0x0 22. "BYTE_COUNT_MISMATCH_IRQ2,Pixel IF 2 Byte Count Mismatch Flag - When HIGH this bit indicates that a byte count mismatch occurred." "0,1" newline bitfld.long 0x0 21. "DATA_FLOW_ERR_IRQ2,Pixel IF 2 Data Flow Error Flag - When HIGH this bit indicates that data flow error has occurred caused by the Frame/Line valid being asserted when the D-PHY is not ready." "0,1" newline bitfld.long 0x0 20. "FIFO_UNDERFLOW_IRQ2,Pixel IF 2 FIFO Underflow Flag - When HIGH this bit indicates that at least one internal FIFO underflow occurred." "0,1" newline bitfld.long 0x0 19. "LINE_END_IRQ2,Pixel IF 2 Line End Flag - When HIGH this bit indicates that a line end occurred." "0,1" newline bitfld.long 0x0 18. "LINE_START_IRQ2,Pixel IF 2 Line Start Flag - When HIGH this bit indicates that a line start occurred." "0,1" newline bitfld.long 0x0 17. "FRAME_END_IRQ2,Pixel IF 2 Frame End Flag - When HIGH this bit indicates that a frame end occurred." "0,1" newline bitfld.long 0x0 16. "FRAME_START_IRQ2,Pixel IF 2 Frame Start Flag - When HIGH this bit indicates that a frame start occurred." "0,1" newline bitfld.long 0x0 15. "LINE_NUMBER_ERROR1,Pixel IF 1 Line Number Error Flag - When HIGH this bit indicates that a line number error occurred." "0,1" newline bitfld.long 0x0 14. "BYTE_COUNT_MISMATCH_IRQ1,Pixel IF 1 Byte Count Mismatch Flag - When HIGH this bit indicates that a byte count mismatch occurred." "0,1" newline bitfld.long 0x0 13. "DATA_FLOW_ERR_IRQ1,Pixel IF 1 Data Flow Error Flag - When HIGH this bit indicates that data flow error has occurred caused by the Frame/Line valid being asserted when the D-PHY is not ready." "0,1" newline bitfld.long 0x0 12. "FIFO_UNDERFLOW_IRQ1,Pixel IF 1 FIFO Underflow Flag - When HIGH this bit indicates that at least one internal FIFO underflow occurred." "0,1" newline bitfld.long 0x0 11. "LINE_END_IRQ1,Pixel IF 1 Line End Flag - When HIGH this bit indicates that a line end occurred." "0,1" newline bitfld.long 0x0 10. "LINE_START_IRQ1,Pixel IF 1 Line Start Flag - When HIGH this bit indicates that a line start occurred." "0,1" newline bitfld.long 0x0 9. "FRAME_END_IRQ1,Pixel IF 1 Frame End Flag - When HIGH this bit indicates that a frame end occurred." "0,1" newline bitfld.long 0x0 8. "FRAME_START_IRQ1,Pixel IF 1 Frame Start Flag - When HIGH this bit indicates that a frame start occurred." "0,1" newline bitfld.long 0x0 7. "LINE_NUMBER_ERROR0,Pixel IF 0 Line Number Error Flag - When HIGH this bit indicates that a line number error occurred." "0,1" newline bitfld.long 0x0 6. "BYTE_COUNT_MISMATCH_IRQ0,Pixel IF 0 Byte Count Mismatch Flag - When HIGH this bit indicates that a byte count mismatch occurred." "0,1" newline bitfld.long 0x0 5. "DATA_FLOW_ERR_IRQ0,Pixel IF 0 Data Flow Error Flag - When HIGH this bit indicates that data flow error has occurred caused by the Frame/Line valid being asserted when the D-PHY is not ready." "0,1" newline bitfld.long 0x0 4. "FIFO_UNDERFLOW_IRQ0,Pixel IF 0 FIFO Underflow Flag - When HIGH this bit indicates that at least one internal FIFO underflow occurred." "0,1" newline bitfld.long 0x0 3. "LINE_END_IRQ0,Pixel IF 0 Line End Flag - When HIGH this bit indicates that a line end occurred." "0,1" newline bitfld.long 0x0 2. "LINE_START_IRQ0,Pixel IF 0 Line Start Flag - When HIGH this bit indicates that a line start occurred." "0,1" newline bitfld.long 0x0 1. "FRAME_END_IRQ0,Pixel IF 0 Frame End Flag - When HIGH this bit indicates that a frame end occurred." "0,1" newline bitfld.long 0x0 0. "FRAME_START_IRQ0,Pixel IF 0 Frame Start Flag - When HIGH this bit indicates that a frame start occurred." "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_irq_mask,CSI-2 Transmitter Interrupt Mask Register." bitfld.long 0x4 15. "MASK_LINE_NUMBER_ERROR1,Pixel IF 1 Line Number Error Mask - Writing 1 to this bit enables interrupt generation from the line_number_error_irq bit." "0,1" newline bitfld.long 0x4 14. "MASK_BYTE_COUNT_MISMATCH_IRQ1,Pixel IF 1 Byte Count Mismatch Mask - Writing 1 to this bit enables interrupt generation from the byte_count_mismatch_irq bit." "0,1" newline bitfld.long 0x4 13. "MASK_DATA_FLOW_ERR_IRQ1,Pixel IF 1 Data Flow Error Mask - Writing 1 to this bit enables interrupt generation from the data_flow_err_irq bit." "0,1" newline bitfld.long 0x4 12. "MASK_FIFO_UNDERFLOW_IRQ1,Pixel IF 1 FIFO Underflow Mask - Writing 1 to this bit enables interrupt generation from the fifo_underflow_irq bit." "0,1" newline bitfld.long 0x4 11. "MASK_LINE_END_IRQ1,Pixel IF 1 Line End Mask - Writing 1 to this bit enables interrupt generation from the line_en_irq bit." "0,1" newline bitfld.long 0x4 10. "MASK_LINE_START_IRQ1,Pixel IF 1 Line Start Mask - Writing 1 to this bit enables interrupt generation from the line_start_irq bit." "0,1" newline bitfld.long 0x4 9. "MASK_FRAME_END_IRQ1,Pixel IF 1 Frame End Mask - Writing 1 to this bit enables interrupt generation from the frame_end_irq bit." "0,1" newline bitfld.long 0x4 8. "MASK_FRAME_START_IRQ1,Pixel IF 1 Frame Start Mask - Writing 1 to this bit enables interrupt generation from the frame_start_irq bit." "0,1" newline bitfld.long 0x4 7. "MASK_LINE_NUMBER_ERROR0,Pixel IF 0 Line Number Error Mask - Writing 1 to this bit enables interrupt generation from the line_number_error_irq bit." "0,1" newline bitfld.long 0x4 6. "MASK_BYTE_COUNT_MISMATCH_IRQ0,Pixel IF 0 Byte Count Mismatch Mask - Writing 1 to this bit enables interrupt generation from the byte_count_mismatch_irq bit." "0,1" newline bitfld.long 0x4 5. "MASK_DATA_FLOW_ERR_IRQ0,Pixel IF 0 Data Flow Error Mask - Writing 1 to this bit enables interrupt generation from the data_flow_err_irq bit." "0,1" newline bitfld.long 0x4 4. "MASK_FIFO_UNDERFLOW_IRQ0,Pixel IF 0 FIFO Underflow Mask - Writing 1 to this bit enables interrupt generation from the fifo_underflow_irq bit." "0,1" newline bitfld.long 0x4 3. "MASK_LINE_END_IRQ0,Pixel IF 0 Line End Mask - Writing 1 to this bit enables interrupt generation from the line_en_irq bit." "0,1" newline bitfld.long 0x4 2. "MASK_LINE_START_IRQ0,Pixel IF 0 Line Start Mask - Writing 1 to this bit enables interrupt generation from the line_start_irq bit." "0,1" newline bitfld.long 0x4 1. "MASK_FRAME_END_IRQ0,Pixel IF 0 Frame End Mask - Writing 1 to this bit enables interrupt generation from the frame_end_irq bit." "0,1" newline bitfld.long 0x4 0. "MASK_FRAME_START_IRQ0,Pixel IF 0 Frame Start Mask - Writing 1 to this bit enables interrupt generation from the frame_start_irq bit." "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dphy_irq,D-PHY Transmitter Interrupt Status. Level sensitive interrupt bits driven by D-PHY signal pins. Write 1 to clear" bitfld.long 0x8 15. "ERR_CTRL_TX3_IRQ,D-PHY Transmitter Lane 3 ERR_CONTROL_IRQ" "0,1" newline bitfld.long 0x8 14. "ERR_CTRL_TX2_IRQ,D-PHY Transmitter Lane 2 ERR_CONTROL_IRQ" "0,1" newline bitfld.long 0x8 13. "ERR_CTRL_TX1_IRQ,D-PHY Transmitter Lane 1 ERR_CONTROL_IRQ" "0,1" newline bitfld.long 0x8 12. "ERR_CTRL_TX0_IRQ,D-PHY Transmitter Lane 0 ERR_CONTROL_IRQ" "0,1" newline bitfld.long 0x8 11. "ERR_ESC_TX3_IRQ,D-PHY Transmitter Lane 3 ERR_ESC_IRQ" "0,1" newline bitfld.long 0x8 10. "ERR_ESC_TX2_IRQ,D-PHY Transmitter Lane 2 ERR_ESC_IRQ" "0,1" newline bitfld.long 0x8 9. "ERR_ESC_TX1_IRQ,D-PHY Transmitter Lane 1 ERR_ESC_IRQ" "0,1" newline bitfld.long 0x8 8. "ERR_ESC_TX0_IRQ,D-PHY Transmitter Lane 0 ERR_ESC_IRQ" "0,1" newline bitfld.long 0x8 7. "ERR_SYNC_TX3_IRQ,D-PHY Transmitter Lane 3 ERR_SYNC_ESC_IRQ" "0,1" newline bitfld.long 0x8 6. "ERR_SYNC_TX2_IRQ,D-PHY Transmitter Lane 2 ERR_SYNC_ESC_IRQ" "0,1" newline bitfld.long 0x8 5. "ERR_SYNC_TX1_IRQ,D-PHY Transmitter Lane 1 ERR_SYNC_ESC_IRQ" "0,1" newline bitfld.long 0x8 4. "ERR_SYNC_TX0_IRQ,D-PHY Transmitter Lane 0 ERR_SYNC_ESC_IRQ" "0,1" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dphy_irq_mask,D-PHY Transmitter Interrupt Mask. Writing '1' to any bit enables interrupt generation when interrupt source signal is set and interrupts are enabled." bitfld.long 0xC 15. "MASK_ERR_CTRL_TX3_IRQ,D-PHY Transmitter Mask Lane 3 ERR_CONTROL_IRQ" "0,1" newline bitfld.long 0xC 14. "MASK_ERR_CTRL_TX2_IRQ,D-PHY Transmitter Mask Lane 2 ERR_CONTROL_IRQ" "0,1" newline bitfld.long 0xC 13. "MASK_ERR_CTRL_TX1_IRQ,D-PHY Transmitter Mask Lane 1 ERR_CONTROL_IRQ" "0,1" newline bitfld.long 0xC 12. "MASK_ERR_CTRL_TX0_IRQ,D-PHY Transmitter Mask Lane 0 ERR_CONTROL_IRQ" "0,1" newline bitfld.long 0xC 11. "MASK_ERR_ESC_TX3_IRQ,D-PHY Transmitter Mask Lane 3 ERR_ESC_IRQ" "0,1" newline bitfld.long 0xC 10. "MASK_ERR_ESC_TX2_IRQ,D-PHY Transmitter Mask Lane 2 ERR_ESC_IRQ" "0,1" newline bitfld.long 0xC 9. "MASK_ERR_ESC_TX1_IRQ,D-PHY Transmitter Mask Lane 1 ERR_ESC_IRQ" "0,1" newline bitfld.long 0xC 8. "MASK_ERR_ESC_TX0_IRQ,D-PHY Transmitter Mask Lane 0 ERR_ESC_IRQ" "0,1" newline bitfld.long 0xC 7. "MASK_ERR_SYNC_TX3_IRQ,D-PHY Transmitter Mask Lane 3 ERR_SYNC_ESC_IRQ" "0,1" newline bitfld.long 0xC 6. "MASK_ERR_SYNC_TX2_IRQ,D-PHY Transmitter Mask Lane 2 ERR_SYNC_ESC_IRQ" "0,1" newline bitfld.long 0xC 5. "MASK_ERR_SYNC_TX1_IRQ,D-PHY Transmitter Mask Lane 1 ERR_SYNC_ESC_IRQ" "0,1" newline bitfld.long 0xC 4. "MASK_ERR_SYNC_TX0_IRQ,D-PHY Transmitter Mask Lane 0 ERR_SYNC_ESC_IRQ" "0,1" rgroup.long 0x20++0x17 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_tx_conf,CSI-2 Transmitter Configuration Register." bitfld.long 0x0 31. "IRQ_ENABLE,Interrupt Enable - Writing 1 to this bit enables interrupts." "0,1" newline bitfld.long 0x0 5. "RX_V1_3_MAPPING,RX v1.3 Mapping Enable - Writing 1 to this bit make the TX Controller use pixel mappings for 8-bit data types which match that of the Cadence CSI-2 RX v1.3 Controller. This includes RAW8 Null .." "0,1" newline bitfld.long 0x0 4. "RX_COMP_ENABLE,RX Compatibility Mode Enable - Writing 1 to this bit enables RX Compatibility Mode." "0,1" newline bitfld.long 0x0 3. "SCRAMBLER_ENABLE,Scrambler Enable - Writing 1 to this bit enables scrambling on the ppi tx data bus." "0,1" newline bitfld.long 0x0 2. "CONFIGURATION_REQUEST,Configuration Request - Writing 1 to this bit enables configuration mode." "0,1" newline bitfld.long 0x0 1. "SOFT_RESET_REQUEST,Soft Reset Request - Writing 1 to this bit enables soft reset." "0,1" newline bitfld.long 0x0 0. "BYPASS_MODE_ENABLE,Bypass Mode - Enable Writing 1 to this bit enables bypass mode." "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_wait_burst_time,CSI-2 Transmitter D-PHY Wait Time Configuration Register." hexmask.long.byte 0x4 16.--23. 1. "TX_CLOCK_EXIT_TIME,Tx clock exit time - Number of ppi_tx_word_hs_clk cycles corresponding to the HS clock exit time." newline hexmask.long.byte 0x4 0.--7. 1. "WAIT_BURST_TIME_CNT,Wait Burst Time - Number of ppi_tx_word_hs_clk cycles corresponding to the inter HS burst gap." line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dphy_cfg,CSI-2 Transmitter D-PHY Lane Enable Configuration Register." bitfld.long 0x8 12. "DPHY_RESET_N,D-PHY Reset - Active low reset for D-PHY." "0,1" newline bitfld.long 0x8 11. "DPHY_CAL_ENABLE,D-PHY Calibration Enable. Enables calibration for D-PHY speeds over 1.5G." "0,1" newline bitfld.long 0x8 10. "DPHY_CLOCK_MODE,D-PHY Clock Mode. Select the D-PHY Clock Lane mode 0: Continuous 1: Non Continuous" "0: Continuous,1: Non Continuous" newline bitfld.long 0x8 8.--9. "DPHY_MODE,D-PHY Mode. Select the D-PHY clock mode during Non Continuous operation 00: Ultra Low Power 01: High Speed 10: Low Power Stop State 11: Reserved" "0: Ultra Low Power,1: High Speed,?,?" newline bitfld.long 0x8 4. "DPHY_CLK_ENABLE,D-PHY Clock Lane - Active high enable for D-PHY clock lane." "0,1" newline bitfld.long 0x8 3. "DPHY_LN_3_ENABLE,D-PHY Lane 3 Enable - Active high enable for D-PHY data lane 0." "0,1" newline bitfld.long 0x8 2. "DPHY_LN_2_ENABLE,D-PHY Lane 2 Enable - Active high enable for D-PHY data lane 0." "0,1" newline bitfld.long 0x8 1. "DPHY_LN_1_ENABLE,D-PHY Lane 1 Enable - Active high enable for D-PHY data lane 0." "0,1" newline bitfld.long 0x8 0. "DPHY_LN_0_ENABLE,D-PHY Lane 0 Enable - Active high enable for D-PHY data lane 0." "0,1" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dphy_clk_wakeup,CSI-2 Transmitter D-PHY Clock Lane Wakeup Time Configuration Register." hexmask.long.word 0xC 0.--15. 1. "ULPS_CLK_LANE_WAKEUP,D-PHY clock lane wakeup time in ppi_tx_esc_clk cycles." line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dphy_ulps_wakeup,CSI-2 Transmitter D-PHY Data Lane Wakeup Time Configuration Register." hexmask.long.word 0x10 0.--15. 1. "ULPS_DATA_LANE_WAKEUP,D-PHY data lane wakeup time in in ppi_tx_esc_clk cycles." line.long 0x14 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dphy_cfg1,D-PHY Transmitter Configuration." bitfld.long 0x14 8. "DPHY_DIFF_INVERT_C,D-PHY Transmitter invert differential pair on TX Clock Lane" "0,1" newline bitfld.long 0x14 7. "DPHY_DIFF_INVERT_LN_3,D-PHY Transmitter invert differential pair on TX Data Lane 3." "0,1" newline bitfld.long 0x14 6. "DPHY_DIFF_INVERT_LN_2,D-PHY Transmitter invert differential pair on TX Data Lane 2." "0,1" newline bitfld.long 0x14 5. "DPHY_DIFF_INVERT_LN_1,D-PHY Transmitter invert differential pair on TX Data Lane 1." "0,1" newline bitfld.long 0x14 4. "DPHY_DIFF_INVERT_LN_0,D-PHY Transmitter invert differential pair on TX Data Lane 0." "0,1" newline bitfld.long 0x14 3. "FORCE_STOP_MODE_LN_3,D-PHY Transmitter FORCE_STOP_MODE TX Data Lane 3." "0,1" newline bitfld.long 0x14 2. "FORCE_STOP_MODE_LN_2,D-PHY Transmitter FORCE_STOP_MODE TX Data Lane 2." "0,1" newline bitfld.long 0x14 1. "FORCE_STOP_MODE_LN_1,D-PHY Transmitter FORCE_STOP_MODE TX Data Lane 1." "0,1" newline bitfld.long 0x14 0. "FORCE_STOP_MODE_LN_0,D-PHY Transmitter FORCE_STOP_MODE TX Data Lane 0." "0,1" rgroup.long 0x38++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dphy_status,D-PHY Transmitter Status." bitfld.long 0x0 12. "DPHY_ULPS_ACTIVE_N_CLK,D-PHY Transmitter ULPS_ACTIVE_N Clock Lane Status." "0,1" newline bitfld.long 0x0 11. "DPHY_ULPS_ACTIVE_N_LN_3,D-PHY Transmitter ULPS_ACTIVE_N Data Lane 3 Status." "0,1" newline bitfld.long 0x0 10. "DPHY_ULPS_ACTIVE_N_LN_2,D-PHY Transmitter ULPS_ACTIVE_N Data Lane 2 Status." "0,1" newline bitfld.long 0x0 9. "DPHY_ULPS_ACTIVE_N_LN_1,D-PHY Transmitter ULPS_ACTIVE_N Data Lane 1 Status." "0,1" newline bitfld.long 0x0 8. "DPHY_ULPS_ACTIVE_N_LN_0,D-PHY Transmitter ULPS_ACTIVE_N Data Lane 0 Status." "0,1" newline bitfld.long 0x0 4. "DPHY_STOPSTATE_CLK,D-PHY Transmitter STOP_STATE Clock Lane Status." "0,1" newline bitfld.long 0x0 3. "DPHY_STOPSTATE_LN_3,D-PHY Transmitter STOP_STATE Data Lane 3 Status." "0,1" newline bitfld.long 0x0 2. "DPHY_STOPSTATE_LN_2,D-PHY Transmitter STOP_STATE Data Lane 2 Status." "0,1" newline bitfld.long 0x0 1. "DPHY_STOPSTATE_LN_1,D-PHY Transmitter STOP_STATE Data Lane 1 Status." "0,1" newline bitfld.long 0x0 0. "DPHY_STOPSTATE_LN_0,D-PHY Transmitter STOP_STATE Data Lane 0 Status." "0,1" rgroup.long 0x40++0x7F line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc0_cfg,CSI-2 Transmitter Virtual Channel 0 Configuration Register." hexmask.long.word 0x0 16.--31. 1. "VC_0_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 0." newline bitfld.long 0x0 0. "VC_0_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 0." "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc1_cfg,CSI-2 Transmitter Virtual Channel 1 Configuration Register." hexmask.long.word 0x4 16.--31. 1. "VC_1_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 1." newline bitfld.long 0x4 0. "VC_1_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 1." "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc2_cfg,CSI-2 Transmitter Virtual Channel 2 Configuration Register." hexmask.long.word 0x8 16.--31. 1. "VC_2_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 2." newline bitfld.long 0x8 0. "VC_2_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 2." "0,1" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc3_cfg,CSI-2 Transmitter Virtual Channel 3 Configuration Register." hexmask.long.word 0xC 16.--31. 1. "VC_3_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 3." newline bitfld.long 0xC 0. "VC_3_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 3." "0,1" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc4_cfg,CSI-2 Transmitter Virtual Channel 4 Configuration Register." hexmask.long.word 0x10 16.--31. 1. "VC_4_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 4." newline bitfld.long 0x10 0. "VC_4_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 4." "0,1" line.long 0x14 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc5_cfg,CSI-2 Transmitter Virtual Channel 5 Configuration Register." hexmask.long.word 0x14 16.--31. 1. "VC_5_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 5." newline bitfld.long 0x14 0. "VC_5_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 5." "0,1" line.long 0x18 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc6_cfg,CSI-2 Transmitter Virtual Channel 6 Configuration Register." hexmask.long.word 0x18 16.--31. 1. "VC_6_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 6." newline bitfld.long 0x18 0. "VC_6_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 6." "0,1" line.long 0x1C "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc7_cfg,CSI-2 Transmitter Virtual Channel 7 Configuration Register." hexmask.long.word 0x1C 16.--31. 1. "VC_7_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 7." newline bitfld.long 0x1C 0. "VC_7_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 7." "0,1" line.long 0x20 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc8_cfg,CSI-2 Transmitter Virtual Channel 8 Configuration Register." hexmask.long.word 0x20 16.--31. 1. "VC_8_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 8." newline bitfld.long 0x20 0. "VC_8_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 8." "0,1" line.long 0x24 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc9_cfg,CSI-2 Transmitter Virtual Channel 9 Configuration Register." hexmask.long.word 0x24 16.--31. 1. "VC_9_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 9." newline bitfld.long 0x24 0. "VC_9_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 9." "0,1" line.long 0x28 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc10_cfg,CSI-2 Transmitter Virtual Channel 10 Configuration Register." hexmask.long.word 0x28 16.--31. 1. "VC_10_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 10." newline bitfld.long 0x28 0. "VC_10_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 10." "0,1" line.long 0x2C "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc11_cfg,CSI-2 Transmitter Virtual Channel 11 Configuration Register." hexmask.long.word 0x2C 16.--31. 1. "VC_11_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 11." newline bitfld.long 0x2C 0. "VC_11_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 11." "0,1" line.long 0x30 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc12_cfg,CSI-2 Transmitter Virtual Channel 12 Configuration Register." hexmask.long.word 0x30 16.--31. 1. "VC_12_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 12." newline bitfld.long 0x30 0. "VC_12_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 12." "0,1" line.long 0x34 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc13_cfg,CSI-2 Transmitter Virtual Channel 13 Configuration Register." hexmask.long.word 0x34 16.--31. 1. "VC_13_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 13." newline bitfld.long 0x34 0. "VC_13_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 13." "0,1" line.long 0x38 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc14_cfg,CSI-2 Transmitter Virtual Channel 14 Configuration Register." hexmask.long.word 0x38 16.--31. 1. "VC_14_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 14." newline bitfld.long 0x38 0. "VC_14_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 14." "0,1" line.long 0x3C "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc15_cfg,CSI-2 Transmitter Virtual Channel 15 Configuration Register." hexmask.long.word 0x3C 16.--31. 1. "VC_15_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 15." newline bitfld.long 0x3C 0. "VC_15_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 15." "0,1" line.long 0x40 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt0_cfg,CSI-2 Transmitter Data Type 0 Configuration Register with pixel_dt_sel[:] = 0." bitfld.long 0x40 9. "DT_0_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32-bit words on the pixel interface the data is sent with the defined Data Type 0 with pixel_dt_sel[:] = 0. This bit is also used for quad pixel 8-bit data types." "0,1" newline bitfld.long 0x40 8. "DT_0_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 0 with pixel_dt_sel[:] = 0." "0,1" newline hexmask.long.byte 0x40 2.--7. 1. "DT_0_DATA_TYPE,Data Type - Type of data on Data Type 0 with pixel_dt_sel[:] = 0. Default ED [0x12]" newline bitfld.long 0x40 1. "DT_0_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 0." "0,1" newline bitfld.long 0x40 0. "DT_0_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 0." "0,1" line.long 0x44 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt0_format,CSI-2 Transmitter Data Type 0 Format Register." hexmask.long.word 0x44 16.--31. 1. "DT_0_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 0 with pixel_dt_sel[:] = 0." newline hexmask.long.word 0x44 0.--15. 1. "DT_0_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 0 with pixel_dt_sel[:] = 0." line.long 0x48 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt1_cfg,CSI-2 Transmitter Data Type 1 Configuration Register with pixel_dt_sel[:] = 1." bitfld.long 0x48 9. "DT_1_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32-bit words on the pixel interface the data is sent with the defined Data Type 1 with pixel_dt_sel[:] = 1. This bit is also used for quad pixel 8-bit data types." "0,1" newline bitfld.long 0x48 8. "DT_1_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 1 with pixel_dt_sel[:] = 1." "0,1" newline hexmask.long.byte 0x48 2.--7. 1. "DT_1_DATA_TYPE,Data Type - Type of data on Data Type 1 with pixel_dt_sel[:] = 1. Default YUV422 8bit [0x1E]" newline bitfld.long 0x48 1. "DT_1_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 1." "0,1" newline bitfld.long 0x48 0. "DT_1_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 1." "0,1" line.long 0x4C "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt1_format,CSI-2 Transmitter Data Type 1 Format Register." hexmask.long.word 0x4C 16.--31. 1. "DT_1_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 1 with pixel_dt_sel[:] = 1." newline hexmask.long.word 0x4C 0.--15. 1. "DT_1_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 1 with pixel_dt_sel[:] = 1." line.long 0x50 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt2_cfg,CSI-2 Transmitter Data Type 2 Configuration Register with pixel_dt_sel[:] = 2." bitfld.long 0x50 9. "DT_2_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32-bit words on the pixel interface the data is sent with the defined Data Type 2 with pixel_dt_sel[:] = 2. This bit is also used for quad pixel 8-bit data types." "0,1" newline bitfld.long 0x50 8. "DT_2_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 2 with pixel_dt_sel[:] = 2." "0,1" newline hexmask.long.byte 0x50 2.--7. 1. "DT_2_DATA_TYPE,Data Type - Type of data on Data Type 2 with pixel_dt_sel[:] = 2. Default RAW8 [0x2A]" newline bitfld.long 0x50 1. "DT_2_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 2." "0,1" newline bitfld.long 0x50 0. "DT_2_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 2." "0,1" line.long 0x54 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt2_format,CSI-2 Transmitter Data Type 2 Format Register." hexmask.long.word 0x54 16.--31. 1. "DT_2_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 2 with pixel_dt_sel[:] = 2." newline hexmask.long.word 0x54 0.--15. 1. "DT_2_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 2 with pixel_dt_sel[:] = 2." line.long 0x58 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt3_cfg,CSI-2 Transmitter Data Type 3 Configuration Register with pixel_dt_sel[:] = 3." bitfld.long 0x58 9. "DT_3_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32-bit words on the pixel interface the data is sent with the defined Data Type 3 with pixel_dt_sel[:] = 3. This bit is also used for quad pixel 8-bit data types." "0,1" newline bitfld.long 0x58 8. "DT_3_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 3 with pixel_dt_sel[:] = 3." "0,1" newline hexmask.long.byte 0x58 2.--7. 1. "DT_3_DATA_TYPE,Data Type - Type of data on Data Type 3 with pixel_dt_sel[:] = 3. Default RGB888 [0x24]" newline bitfld.long 0x58 1. "DT_3_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 3." "0,1" newline bitfld.long 0x58 0. "DT_3_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 3." "0,1" line.long 0x5C "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt3_format,CSI-2 Transmitter Data Type 3 Format Register." hexmask.long.word 0x5C 16.--31. 1. "DT_3_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 3 with pixel_dt_sel[:] = 3." newline hexmask.long.word 0x5C 0.--15. 1. "DT_3_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 3 with pixel_dt_sel[:] = 3." line.long 0x60 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt4_cfg,CSI-2 Transmitter Data Type 4 Configuration Register with pixel_dt_sel[:] = 4." bitfld.long 0x60 9. "DT_4_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32-bit words on the pixel interface the data is sent with the defined Data Type 4 with pixel_dt_sel[:] = 4. This bit is also used for quad pixel 8-bit data types." "0,1" newline bitfld.long 0x60 8. "DT_4_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 4 with pixel_dt_sel[:] = 4." "0,1" newline hexmask.long.byte 0x60 2.--7. 1. "DT_4_DATA_TYPE,Data Type - Type of data on Data Type 4 with pixel_dt_sel[:] = 4." newline bitfld.long 0x60 1. "DT_4_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 4." "0,1" newline bitfld.long 0x60 0. "DT_4_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 4." "0,1" line.long 0x64 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt4_format,CSI-2 Transmitter Data Type 4 Format Register." hexmask.long.word 0x64 16.--31. 1. "DT_4_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 4 with pixel_dt_sel[:] = 4." newline hexmask.long.word 0x64 0.--15. 1. "DT_4_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 4 with pixel_dt_sel[:] = 4." line.long 0x68 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt5_cfg,CSI-2 Transmitter Data Type 5 Configuration Register with pixel_dt_sel[:] = 5." bitfld.long 0x68 9. "DT_5_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32-bit words on the pixel interface the data is sent with the defined Data Type 5 with pixel_dt_sel[:] = 5. This bit is also used for quad pixel 8-bit data types." "0,1" newline bitfld.long 0x68 8. "DT_5_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 5 with pixel_dt_sel[:] = 5." "0,1" newline hexmask.long.byte 0x68 2.--7. 1. "DT_5_DATA_TYPE,Data Type - Type of data on Data Type 5 with pixel_dt_sel[:] = 5." newline bitfld.long 0x68 1. "DT_5_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 5." "0,1" newline bitfld.long 0x68 0. "DT_5_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 5." "0,1" line.long 0x6C "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt5_format,CSI-2 Transmitter Data Type 5 Format Register." hexmask.long.word 0x6C 16.--31. 1. "DT_5_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 5 with pixel_dt_sel[:] = 5." newline hexmask.long.word 0x6C 0.--15. 1. "DT_5_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 5 with pixel_dt_sel[:] = 5." line.long 0x70 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt6_cfg,CSI-2 Transmitter Data Type 6 Configuration Register with pixel_dt_sel[:] = 6." bitfld.long 0x70 9. "DT_6_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32-bit words on the pixel interface the data is sent with the defined Data Type 6 with pixel_dt_sel[:] = 6. This bit is also used for quad pixel 8-bit data types." "0,1" newline bitfld.long 0x70 8. "DT_6_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 6 with pixel_dt_sel[:] = 6." "0,1" newline hexmask.long.byte 0x70 2.--7. 1. "DT_6_DATA_TYPE,Data Type - Type of data on Data Type 6 with pixel_dt_sel[:] = 6." newline bitfld.long 0x70 1. "DT_6_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 6." "0,1" newline bitfld.long 0x70 0. "DT_6_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 6." "0,1" line.long 0x74 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt6_format,CSI-2 Transmitter Data Type 6 Format Register." hexmask.long.word 0x74 16.--31. 1. "DT_6_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 6 with pixel_dt_sel[:] = 6." newline hexmask.long.word 0x74 0.--15. 1. "DT_6_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 6 with pixel_dt_sel[:] = 6." line.long 0x78 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt7_cfg,CSI-2 Transmitter Data Type 7 Configuration Register with pixel_dt_sel[:] = 7." bitfld.long 0x78 9. "DT_7_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32-bit words on the pixel interface the data is sent with the defined Data Type 7 with pixel_dt_sel[:] = 7. This bit is also used for quad pixel 8-bit data types." "0,1" newline bitfld.long 0x78 8. "DT_7_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 7 with pixel_dt_sel[:] = 7." "0,1" newline hexmask.long.byte 0x78 2.--7. 1. "DT_7_DATA_TYPE,Data Type - Type of data on Data Type 7 with pixel_dt_sel[:] = 7." newline bitfld.long 0x78 1. "DT_7_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 7." "0,1" newline bitfld.long 0x78 0. "DT_7_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 7." "0,1" line.long 0x7C "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt7_format,CSI-2 Transmitter Data Type 7 Format Register." hexmask.long.word 0x7C 16.--31. 1. "DT_7_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 7 with pixel_dt_sel[:] = 7." newline hexmask.long.word 0x7C 0.--15. 1. "DT_7_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 7 with pixel_dt_sel[:] = 7." rgroup.long 0x100++0x7 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_stream_if_0_cfg,CSI-2 Stream 0 Configuration Register." hexmask.long.word 0x0 0.--11. 1. "STREAM_IF_0_FILL_LEVEL,Fill Level - Minimum number of packed 32 words loaded into the stream fifo before Tx will start for Stream if 0." line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_stream_if_1_cfg,CSI-2 Stream 1 Configuration Register." bitfld.long 0x4 23. "STREAM_IF_1_SLAVE_MODE,Stream Slave Mode suppresses frame start/end packets in stream 1. To be used when DT interleving is required in the same VC. NOTE: the stream must then be paired with stream O as the master on the StreamIF" "0,1" newline hexmask.long.word 0x4 0.--11. 1. "STREAM_IF_1_FILL_LEVEL,Fill Level - Minimum number of packed 32 words loaded into the stream fifo before Tx will start for Stream if 1." rgroup.long 0x200++0xB line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_epd_en_ssp,CSI-2 Transmitter EPD Enable and Short Packet Spacers Register" bitfld.long 0x0 15. "EPD_ENABLE,EPD enable. Set high to enable EPD operation." "0,1" newline hexmask.long.word 0x0 0.--14. 1. "EPD_SP_SPACERS,EPD Short Packet Spacers: EPD Option 1: Minimum number of Spacer Bytes per Lane following a Short Packet. EPD Option 2: Fixed number of Spacer Bytes per Lane following a.." line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_epd_op_slp,CSI-2 Transmitter EPD Option and Long Packet Spacers Register" bitfld.long 0x4 15. "EPD_OPTION,EPD Option. 1'b0: D-PHY EPD Option 1 1'b1: D-PHY EPD Option 2" "0: D-PHY EPD Option 1 1'b1: D-PHY EPD Option 2,?" newline hexmask.long.word 0x4 0.--14. 1. "EPD_LP_SPACERS,EPD Long Packet Spacers: EPD Option 1: Minimum number of Spacer Bytes per Lane following a Long Packet. EPD Option 2: Fixed number of Spacer Bytes per Lane following a.." line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_epd_clkidlehs_min,CSI-2 Transmitter EPD Minimum HS Clock Idle Time Register" hexmask.long.word 0x8 0.--15. 1. "EPD_OPTION1_CLKIDLEHS_MIN,For LRTE EPD Option 1 this sets the minimum number of pclk cycles required to meet the D-PHY timing requirement for THS-IDLE-CLKHS0." rgroup.long 0xD00++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_debug_cfg,CSI-2 Transmitter Debug Enable Register." bitfld.long 0x0 0. "DBG_EN,Debug Enable. This bit enables debug when high. If low then other DEBUG registers read 0." "0,1" rgroup.long 0xD04++0x1B line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_debug_ln_fsm,Debug Register for Lane FSM." bitfld.long 0x0 9. "NEW_BURST_ALLOWED,Lane Mangement FSM. New burst allowed - WAIT_BURST_TIME expired" "0,1" newline bitfld.long 0x0 8. "PACKET_VALID_R,Lane Mangement FSM. Valid packet in packet register" "0,1" newline bitfld.long 0x0 7. "PACKET_VALID_IN,Lane Mangement FSM. Valid packet at input" "0,1" newline bitfld.long 0x0 6. "END_OF_BURST,Lane Mangement FSM. End of High speed burst" "0,1" newline bitfld.long 0x0 5. "TRANS_ACTIVE,Lane Mangement FSM. HS transmission active" "0,1" newline bitfld.long 0x0 4. "START_HS_TRANS,Lane Mangement FSM. HS transmission ready" "0,1" newline bitfld.long 0x0 0.--2. "LANE_MGR_FSM_ST,Lane Mangement FSM. State of Lane Management FSM" "0,1,2,3,4,5,6,7" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_debug_clk_ln_fsm,Debug Register for Clock Lane FSM" bitfld.long 0x4 13. "ULPS_ACTIVE_CLK,Clock Lane FSM. ULPS active from D-PHY" "0,1" newline bitfld.long 0x4 12. "ULPS_MODE_ACTIVE,Clock Lane FSM. ULPS mode active" "0,1" newline bitfld.long 0x4 11. "ULPS_EXIT_CLK_PPI,Clock Lane FSM. ULPS EXIT Request to D-PHY" "0,1" newline bitfld.long 0x4 10. "ULPS_REQUEST_CLK_PPI,Clock Lane FSM. ULPS request to D-PHY" "0,1" newline bitfld.long 0x4 9. "HS_MODE_ACTIVE_CLK,Clock Lane FSM. High speed mode active" "0,1" newline bitfld.long 0x4 8. "REQUEST_HS_CLK_PPI,Clock Lane FSM. High speed clock request" "0,1" newline bitfld.long 0x4 7. "READY_HS_CLK,Clock Lane FSM. High speed clock active from D-PHY" "0,1" newline bitfld.long 0x4 6. "ULPS_WAKEUP_COUNT_DONE_CL,Clock Lane FSM. Clock lane ULPS wakeup counter expired" "0,1" newline bitfld.long 0x4 5. "ULPS_REQUEST_CLK,Clock Lane FSM. Request ULPS mode" "0,1" newline bitfld.long 0x4 4. "HS_MODE_REQ,Clock Lane FSM. Request High Speed mode" "0,1" newline bitfld.long 0x4 2.--3. "ULPS_CLK_FSM,Clock Lane FSM. State of ULPS control FSM." "0,1,2,3" newline bitfld.long 0x4 0.--1. "HS_CLK_FSM,Clock Lane FSM. State of High Speed Clock FSM." "0,1,2,3" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_debug_data_ln_fsm,Debug Register for Data Lane FSM." bitfld.long 0x8 16. "ULPS_ACTIVE,Data Lane FSM. Clock and data lane ULPS active" "0,1" newline bitfld.long 0x8 15. "DATA_ULPS_ACTIVE,Debug Register for Data Lane FSM. Data lane ULPS active" "0,1" newline bitfld.long 0x8 14. "TX_ULPS_EXIT_ESC,Data Lane FSM. Exit escape mode to D-PHY" "0,1" newline bitfld.long 0x8 13. "TX_ULPS_ESC,Data Lane FSM. ULPS escape mode to D-PHY" "0,1" newline bitfld.long 0x8 12. "TX_REQUEST_ESC,Data Lane FSM. Request escape mode to D-PHY" "0,1" newline bitfld.long 0x8 10. "ULPS_WAKEUP_COUNT_DONE_DL,Data Lane FSM. Data Lane ULPS wakeup counter expired" "0,1" newline hexmask.long.byte 0x8 6.--9. 1. "ULPS_ACTIVE_N,Data Lane FSM. Data Lane ULPS active from D-PHY" newline bitfld.long 0x8 5. "HS_MODE_REQ_SYNC,Data Lane FSM. HS Mode request" "0,1" newline bitfld.long 0x8 4. "ULPS_REQ_SYNC,Data Lane FSM. ULPS Request" "0,1" newline bitfld.long 0x8 0.--1. "ULPS_DATA_LANE_FSM,Data Lane FSM. State of Data Lane FSM FSM" "0,1,2,3" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_debug_prot0_fsm,Debug Register for Pixel IF0 Protocol FSM." hexmask.long.byte 0xC 15.--18. 1. "VIRTUAL_CHANNEL_IF0,Pixel IF0 Protocol FSM. State of the top level Virtual Channel select signals State of the Virtual Channel[3:2] select signals when VCX enabled otherwise '00' and state of the Virtual Channel[1:0]" newline bitfld.long 0xC 12.--14. "DATA_TYPE_IF0,Pixel IF0 Protocol FSM. State of the Data Type select signals" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 11. "FRAME_VALID_IF0,Pixel IF0 Protocol FSM. State of the Frame Valid signal" "0,1" newline bitfld.long 0xC 10. "LINE_VALID_IF0,Pixel IF0 Protocol FSM. State of the Line Valid signal" "0,1" newline bitfld.long 0xC 8. "LAST_PAYLOAD_DATA_IF0,Pixel IF0 Protocol FSM. Last payload data in long packet" "0,1" newline bitfld.long 0xC 7. "PAYLOAD_FIFO_EMPTY_IF0,Pixel IF0 Protocol FSM. Payload FIFO empty" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "PROT_FSM_IF0,Pixel IF0 Protocol FSM. State of Protocol Control FSM" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_debug_prot1_fsm,Debug Register for Pixel IF1 Protocol FSM. (Optional: Available when PIXEL_IF2 or 4)" hexmask.long.byte 0x10 15.--18. 1. "VIRTUAL_CHANNEL_IF1,Pixel IF1 Protocol FSM. State of the top level Virtual Channel select signals State of the Virtual Channel[3:2] select signals when VCX enabled otherwise '00' and state of the Virtual Channel[1:0]" newline bitfld.long 0x10 12.--14. "DATA_TYPE_IF1,Pixel IF1 Protocol FSM. State of the Data Type select signals" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 11. "FRAME_VALID_IF1,Pixel IF1 Protocol FSM. State of the Frame Valid signal" "0,1" newline bitfld.long 0x10 10. "LINE_VALID_IF1,Pixel IF1 Protocol FSM. State of the Line Valid signal" "0,1" newline bitfld.long 0x10 8. "LAST_PAYLOAD_DATA_IF1,Pixel IF1 Protocol FSM. Last payload data in long packet" "0,1" newline bitfld.long 0x10 7. "PAYLOAD_FIFO_EMPTY_IF1,Pixel IF1 Protocol FSM. Payload FIFO empty" "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "PROT_FSM_IF1,Pixel IF1 Protocol FSM. State of Protocol Control FSM" line.long 0x14 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_debug_prot2_fsm,Debug Register for Pixel IF2 Protocol FSM. (Optional: Available when PIXEL_IF4)" hexmask.long.byte 0x14 15.--18. 1. "VIRTUAL_CHANNEL_IF2,Pixel IF2 Protocol FSM. State of the top level Virtual Channel select signals State of the Virtual Channel[3:2] select signals when VCX enabled otherwise '00' and state of the Virtual Channel[1:0]" newline bitfld.long 0x14 12.--14. "DATA_TYPE_IF2,Pixel IF2 Protocol FSM. State of the Data Type select signals" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 11. "FRAME_VALID_IF2,Pixel IF2 Protocol FSM. State of the Frame Valid signal" "0,1" newline bitfld.long 0x14 10. "LINE_VALID_IF2,Pixel IF2 Protocol FSM. State of the Line Valid signal" "0,1" newline bitfld.long 0x14 8. "LAST_PAYLOAD_DATA_IF2,Pixel IF2 Protocol FSM. Last payload data in long packet" "0,1" newline bitfld.long 0x14 7. "PAYLOAD_FIFO_EMPTY_IF2,Pixel IF2 Protocol FSM. Payload FIFO empty" "0,1" newline hexmask.long.byte 0x14 0.--6. 1. "PROT_FSM_IF2,Pixel IF2 Protocol FSM. State of Protocol Control FSM" line.long 0x18 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_debug_prot3_fsm,Debug Register for Pixel IF3 Protocol FSM. (Optional: Available when PIXEL_IF4)" hexmask.long.byte 0x18 15.--18. 1. "VIRTUAL_CHANNEL_IF3,Pixel IF3 Protocol FSM. State of the top level Virtual Channel select signals State of the Virtual Channel[3:2] select signals when VCX enabled otherwise '00' and state of the Virtual Channel[1:0]" newline bitfld.long 0x18 12.--14. "DATA_TYPE_IF3,Pixel IF3 Protocol FSM. State of the Data Type select signals" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 11. "FRAME_VALID_IF3,Pixel IF3 Protocol FSM. State of the Frame Valid signal" "0,1" newline bitfld.long 0x18 10. "LINE_VALID_IF3,Pixel IF3 Protocol FSM. State of the Line Valid signal" "0,1" newline bitfld.long 0x18 8. "LAST_PAYLOAD_DATA_IF3,Pixel IF3 Protocol FSM. Last payload data in long packet" "0,1" newline bitfld.long 0x18 7. "PAYLOAD_FIFO_EMPTY_IF3,Pixel IF3 Protocol FSM. Payload FIFO empty" "0,1" newline hexmask.long.byte 0x18 0.--6. 1. "PROT_FSM_IF3,Pixel IF3 Protocol FSM. State of Protocol Control FSM" rgroup.long 0xDF8++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_test_generic_status,GPIO - Generic test status register that read primary inputs: test_generic_status" hexmask.long.word 0x0 0.--15. 1. "STATUS,Test status - Directly reflects after resynchronisation into the pclk domain the state of 'test_generic_status' primary inputs." rgroup.long 0xDFC++0x17 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_test_generic_ctrl,GPIO - Generic test control register that controls primary outputs: test_generic_ctrl." hexmask.long.word 0x0 0.--15. 1. "CTRL,Test control - Directly controls primary outputs 'test_generic_ctrl'" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_int_status,ASF Interrupt Status Register. This register indicates the source of ASF interrupts. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register.." hexmask.long 0x4 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x4 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1" newline bitfld.long 0x4 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1" newline bitfld.long 0x4 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1" newline bitfld.long 0x4 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x4 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1" newline bitfld.long 0x4 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x4 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_int_raw_status,ASF Interrupt Raw Status Register. A bit set in this raw register indicates a source of ASF fault in the corresponding feature. Writing to either raw or masked status registers. clear both.." hexmask.long 0x8 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x8 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1" newline bitfld.long 0x8 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1" newline bitfld.long 0x8 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1" newline bitfld.long 0x8 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x8 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1" newline bitfld.long 0x8 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x8 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_int_mask,The ASF interrupt mask register indicating which interrupt bits in the ASF interrupt status register are masked. All bits are set at reset. Clear the individual bit to enable the corresponding.." hexmask.long 0xC 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0xC 6. "ASF_INTEGRITY_ERR_MASK,Mask bit for integrity error interrupt" "0,1" newline bitfld.long 0xC 5. "ASF_PROTOCOL_ERR_MASK,Mask bit for protocol error interrupt." "0,1" newline bitfld.long 0xC 4. "ASF_TRANS_TO_ERR_MASK,Mask bit for transaction timeouts error interrupt." "0,1" newline bitfld.long 0xC 3. "ASF_CSR_ERR_MASK,Mask bit for configuration and status registers error interrupt." "0,1" newline bitfld.long 0xC 2. "ASF_DAP_ERR_MASK,Mask bit for data and address paths parity error interrupt." "0,1" newline bitfld.long 0xC 1. "ASF_SRAM_UNCORR_ERR_MASK,Mask bit for SRAM uncorrectable error interrupt." "0,1" newline bitfld.long 0xC 0. "ASF_SRAM_CORR_ERR_MASK,Mask bit for SRAM correctable error interrupt." "0,1" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_int_test,The ASF interrupt test register emulate hardware even. Write one to individual bit to trigger single event in (masked and raw) status registers according to mask and will generate interrupt accordingly." hexmask.long 0x10 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x10 6. "ASF_INTEGRITY_ERR_TEST,Test bit for integrity error interrupt" "0,1" newline bitfld.long 0x10 5. "ASF_PROTOCOL_ERR_TEST,Test bit for protocol error interrupt." "0,1" newline bitfld.long 0x10 4. "ASF_TRANS_TO_ERR_TEST,Test bit for transaction timeouts error interrupt." "0,1" newline bitfld.long 0x10 3. "ASF_CSR_ERR_TEST,Test bit for configuration and status registers error interrupt." "0,1" newline bitfld.long 0x10 2. "ASF_DAP_ERR_TEST,Test bit for data and address paths parity error interrupt." "0,1" newline bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR_TEST,Test bit for SRAM uncorrectable error interrupt." "0,1" newline bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR_TEST,Test bit for SRAM correctable error interrupt." "0,1" line.long 0x14 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_fatal_nonfatal_select,The fatal or non-fatal interrupt register selects whether a fatal (asf_int_fatal) or non-fatal (asf_int_nonfatal) interrupt is triggered. If the bit of the event will be set to one then.." hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x14 6. "ASF_INTEGRITY_ERR,Enable integrity error interrupt as fatal" "0,1" newline bitfld.long 0x14 5. "ASF_PROTOCOL_ERR,Enable protocol error interrupt as fatal." "0,1" newline bitfld.long 0x14 4. "ASF_TRANS_TO_ERR,Enable transaction timeouts error interrupt as fatal." "0,1" newline bitfld.long 0x14 3. "ASF_CSR_ERR,Enable configuration and status registers error interrupt as fatal." "0,1" newline bitfld.long 0x14 2. "ASF_DAP_ERR,Enable data and address paths parity error interrupt as fatal." "0,1" newline bitfld.long 0x14 1. "ASF_SRAM_UNCORR_ERR,Enable SRAM uncorrectable error interrupt as fatal." "0,1" newline bitfld.long 0x14 0. "ASF_SRAM_CORR_ERR,Enable SRAM correctable error interrupt as fatal." "0,1" rgroup.long 0xE20++0x7 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_sram_corr_fault_status,Status register for SRAM correctable fault. These fields are updated whenever asf_sram_corr_fault input is active." hexmask.long.byte 0x0 24.--31. 1. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault." newline hexmask.long.tbyte 0x0 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault." line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_sram_uncorr_fault_status,Status register for SRAM uncorrectable fault. These fields are updated whenever asf_sram_uncorr_fault input is active." hexmask.long.byte 0x4 24.--31. 1. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault." newline hexmask.long.tbyte 0x4 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault." rgroup.long 0xE28++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_sram_fault_stats,Statistics register for SRAM faults. Note that this register clears when software writes to any field." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline hexmask.long.word 0x0 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS,Count of number of correctable errors if implemented. Count value will saturate at 0xffff." rgroup.long 0xE30++0xB line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_trans_to_ctrl,Control register to configure the ASF transaction timeout monitors." bitfld.long 0x0 31. "ASF_TRANS_TO_EN,Enable transaction timeout monitoring." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "ASF_TRANS_TO_CTRL,Timer value to use for transaction timeout monitor." line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_trans_to_fault_mask,Control register to mask out ASF transaction timeout faults from triggering interrupts. On reset. all bits are set to mask out all sources. Clear the corresponding bit to enable the.." bitfld.long 0x4 4. "ASF_TRANS_TO_FAULT_4_MASK,Mask register for each ASF transaction timeout fault source." "0,1" newline bitfld.long 0x4 3. "ASF_TRANS_TO_FAULT_3_MASK,Mask register for each ASF transaction timeout fault source." "0,1" newline bitfld.long 0x4 2. "ASF_TRANS_TO_FAULT_2_MASK,Mask register for each ASF transaction timeout fault source." "0,1" newline bitfld.long 0x4 1. "ASF_TRANS_TO_FAULT_1_MASK,Mask register for each ASF transaction timeout fault source." "0,1" newline bitfld.long 0x4 0. "ASF_TRANS_TO_FAULT_0_MASK,Mask register for each ASF transaction timeout fault source." "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_trans_to_fault_status,Status register for transaction timeouts fault. If a fault occurs the revelant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit." bitfld.long 0x8 4. "ASF_TRANS_TO_FAULT_4_STATUS,Status bits for transaction timeouts faults." "0,1" newline bitfld.long 0x8 3. "ASF_TRANS_TO_FAULT_3_STATUS,Status bits for transaction timeouts faults." "0,1" newline bitfld.long 0x8 2. "ASF_TRANS_TO_FAULT_2_STATUS,Status bits for transaction timeouts faults." "0,1" newline bitfld.long 0x8 1. "ASF_TRANS_TO_FAULT_1_STATUS,Status bits for transaction timeouts faults." "0,1" newline bitfld.long 0x8 0. "ASF_TRANS_TO_FAULT_0_STATUS,Status bits for transaction timeouts faults." "0,1" rgroup.long 0xE40++0x7 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_protocol_fault_mask,Control register to mask out ASF Protocol faults from triggering interrupts. On reset. all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt source." bitfld.long 0x0 16. "ASF_PROTOCOL_FAULT_16_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 15. "ASF_PROTOCOL_FAULT_15_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 14. "ASF_PROTOCOL_FAULT_14_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 13. "ASF_PROTOCOL_FAULT_13_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 12. "ASF_PROTOCOL_FAULT_12_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 11. "ASF_PROTOCOL_FAULT_11_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 10. "ASF_PROTOCOL_FAULT_10_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 9. "ASF_PROTOCOL_FAULT_9_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 8. "ASF_PROTOCOL_FAULT_8_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 7. "ASF_PROTOCOL_FAULT_7_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 6. "ASF_PROTOCOL_FAULT_6_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 5. "ASF_PROTOCOL_FAULT_5_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 4. "ASF_PROTOCOL_FAULT_4_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 3. "ASF_PROTOCOL_FAULT_3_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 2. "ASF_PROTOCOL_FAULT_2_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 1. "ASF_PROTOCOL_FAULT_1_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 0. "ASF_PROTOCOL_FAULT_0_MASK,Mask register for each ASF protocol fault source." "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_protocol_fault_status,Status register for protocol faults. If a fault occurs the revelant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit" bitfld.long 0x4 16. "ASF_PROTOCOL_FAULT_16_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 15. "ASF_PROTOCOL_FAULT_15_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 14. "ASF_PROTOCOL_FAULT_14_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 13. "ASF_PROTOCOL_FAULT_13_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 12. "ASF_PROTOCOL_FAULT_12_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 11. "ASF_PROTOCOL_FAULT_11_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 10. "ASF_PROTOCOL_FAULT_10_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 9. "ASF_PROTOCOL_FAULT_9_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 8. "ASF_PROTOCOL_FAULT_8_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 7. "ASF_PROTOCOL_FAULT_7_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 6. "ASF_PROTOCOL_FAULT_6_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 5. "ASF_PROTOCOL_FAULT_5_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 4. "ASF_PROTOCOL_FAULT_4_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 3. "ASF_PROTOCOL_FAULT_3_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 2. "ASF_PROTOCOL_FAULT_2_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 1. "ASF_PROTOCOL_FAULT_1_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 0. "ASF_PROTOCOL_FAULT_0_STATUS,Status bits for protocol faults." "0,1" rgroup.long 0xFFC++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_id_prod_ver,CSI-2 Transmitter Product ID and Version Register." hexmask.long.word 0x0 16.--31. 1. "PRODUCT_ID,CSI-2 Transmitter Product Identification Number." newline hexmask.long.word 0x0 0.--15. 1. "VERSION_ID,CSI-2 Transmitter Product Version Number." tree.end tree "csi_tx_if_v2_1_CP_INTD_CFG_INTD_CFG (csi_tx_if_v2_1_CP_INTD_CFG_INTD_CFG)" base ad:0x4418000 rgroup.long 0x0++0x3 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_REVISION,Revision Register" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,RTL revisions" newline bitfld.long 0x0 8.--10. "MAJREV,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom revision" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_eoi_reg,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector" rgroup.long 0x14++0x3 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg,Interrupt Vector Register" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR,Interrupt Vector Register" rgroup.long 0x100++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_0,Enable Register 0" bitfld.long 0x0 1. "ENABLE_LEVEL_EN_STRM_SEL,Enable Set for level_en_strm_sel" "0,1" bitfld.long 0x0 0. "ENABLE_LEVEL_EN_RETRANS,Enable Set for level_en_retrans" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_0,Enable Register 1" bitfld.long 0x4 1. "ENABLE_PULSE_EN_STRM_SEL,Enable Set for pulse_en_strm_sel" "0,1" bitfld.long 0x4 0. "ENABLE_PULSE_EN_RETRANS,Enable Set for pulse_en_retrans" "0,1" rgroup.long 0x300++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_0,Enable Clear Register 0" bitfld.long 0x0 1. "ENABLE_LEVEL_EN_STRM_SEL_CLR,Enable Clear for level_en_strm_sel" "0,1" bitfld.long 0x0 0. "ENABLE_LEVEL_EN_RETRANS_CLR,Enable Clear for level_en_retrans" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_0,Enable Clear Register 1" bitfld.long 0x4 1. "ENABLE_PULSE_EN_STRM_SEL_CLR,Enable Clear for pulse_en_strm_sel" "0,1" bitfld.long 0x4 0. "ENABLE_PULSE_EN_RETRANS_CLR,Enable Clear for pulse_en_retrans" "0,1" rgroup.long 0x500++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_0,Status Register 0" bitfld.long 0x0 1. "STATUS_LEVEL_STRM_SEL,Status write 1 to set for level_en_strm_sel" "0,1" bitfld.long 0x0 0. "STATUS_LEVEL_RETRANS,Status write 1 to set for level_en_retrans" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_0,Status Register 1" bitfld.long 0x4 1. "STATUS_PULSE_STRM_SEL,Status write 1 to set for pulse_en_strm_sel" "0,1" bitfld.long 0x4 0. "STATUS_PULSE_RETRANS,Status write 1 to set for pulse_en_retrans" "0,1" rgroup.long 0x700++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_0,Status Clear Register 0" bitfld.long 0x0 1. "STATUS_LEVEL_STRM_SEL_CLR,Status write 1 to clear for level_en_strm_sel" "0,1" bitfld.long 0x0 0. "STATUS_LEVEL_RETRANS_CLR,Status write 1 to clear for level_en_retrans" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_0,Status Clear Register 1" bitfld.long 0x4 1. "STATUS_PULSE_STRM_SEL_CLR,Status write 1 to clear for pulse_en_strm_sel" "0,1" bitfld.long 0x4 0. "STATUS_PULSE_RETRANS_CLR,Status write 1 to clear for pulse_en_retrans" "0,1" rgroup.long 0xA80++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_level,Interrupt Vector for level" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR_LEVEL,Interrupt Vector" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_pulse,Interrupt Vector for pulse" hexmask.long 0x4 0.--31. 1. "INTR_VECTOR_PULSE,Interrupt Vector" tree.end tree "csi_tx_if_v2_1_ECC_AGGR_BYTE_CFG (csi_tx_if_v2_1_ECC_AGGR_BYTE_CFG)" base ad:0x2A39400 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_BYTE__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "ECC_AGGR_BYTE__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_BYTE__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "ECC_AGGR_BYTE__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_BYTE__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_BYTE__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "RAM_RAMECC1_PEND,Interrupt Pending Status for ram_ramecc1_pend" "0,1" bitfld.long 0x4 0. "RAM_RAMECC0_PEND,Interrupt Pending Status for ram_ramecc0_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "ECC_AGGR_BYTE__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "RAM_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc1_pend" "0,1" bitfld.long 0x0 0. "RAM_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc0_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_BYTE__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "RAM_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc1_pend" "0,1" bitfld.long 0x0 0. "RAM_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc0_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_BYTE__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_BYTE__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "RAM_RAMECC1_PEND,Interrupt Pending Status for ram_ramecc1_pend" "0,1" bitfld.long 0x4 0. "RAM_RAMECC0_PEND,Interrupt Pending Status for ram_ramecc0_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "ECC_AGGR_BYTE__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "RAM_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc1_pend" "0,1" bitfld.long 0x0 0. "RAM_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc0_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_BYTE__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "RAM_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc1_pend" "0,1" bitfld.long 0x0 0. "RAM_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc0_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "ECC_AGGR_BYTE__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_BYTE__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_BYTE__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_BYTE__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "csi_tx_if_v2_1_ECC_AGGR_CFG (csi_tx_if_v2_1_ECC_AGGR_CFG)" base ad:0x2A39000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "FDRAM_RAMECC_PEND,Interrupt Pending Status for fdram_ramecc_pend" "0,1" bitfld.long 0x4 1. "FIFO_RAMECC_PEND,Interrupt Pending Status for fifo_ramecc_pend" "0,1" bitfld.long 0x4 0. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "FDRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fdram_ramecc_pend" "0,1" bitfld.long 0x0 1. "FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "FDRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fdram_ramecc_pend" "0,1" bitfld.long 0x0 1. "FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "FDRAM_RAMECC_PEND,Interrupt Pending Status for fdram_ramecc_pend" "0,1" bitfld.long 0x4 1. "FIFO_RAMECC_PEND,Interrupt Pending Status for fifo_ramecc_pend" "0,1" bitfld.long 0x4 0. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "FDRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fdram_ramecc_pend" "0,1" bitfld.long 0x0 1. "FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "FDRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fdram_ramecc_pend" "0,1" bitfld.long 0x0 1. "FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "csi_tx_if_v2_1_TX_SHIM_VBUSP_MMR_CSI2TXIF_V2 (csi_tx_if_v2_1_TX_SHIM_VBUSP_MMR_CSI2TXIF_V2)" base ad:0x4410000 rgroup.long 0x0++0x3 line.long 0x0 "TX_SHIM__VBUSP_MMR__CSI2TXIF_V2_REGS_csitx_id,PID" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" newline bitfld.long 0x0 8.--10. "MAJREV,major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom revision" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,min revision" rgroup.long 0x4++0xB line.long 0x0 "TX_SHIM__VBUSP_MMR__CSI2TXIF_V2_REGS_color_cntl,color bar control register" hexmask.long.byte 0x0 16.--19. 1. "VCHNL,color bar virtual channel" bitfld.long 0x0 8.--10. "DTYPE,color bar data type data sel" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "EN,1: enable" "?,1: enable" line.long 0x4 "TX_SHIM__VBUSP_MMR__CSI2TXIF_V2_REGS_color_param,color bar frame parameters" hexmask.long.word 0x4 16.--28. 1. "IH_CFG,input height in units of pixels minus 1." hexmask.long.word 0x4 0.--12. 1. "IW_CFG,input width in units of pixels minus 1." line.long 0x8 "TX_SHIM__VBUSP_MMR__CSI2TXIF_V2_REGS_color_start_delay,delay from starting first line after enabling" hexmask.long 0x8 0.--31. 1. "LINE_DELAY,delay in terms of main clock cycles before sending first line after enabling." rgroup.long 0x20++0x7 line.long 0x0 "TX_SHIM__VBUSP_MMR__CSI2TXIF_V2_REGS_color_line_delay,last line start to next line start delay" hexmask.long 0x0 0.--31. 1. "LINE_DELAY,delay in terms of main clock cycles from line start to next line start" line.long 0x4 "TX_SHIM__VBUSP_MMR__CSI2TXIF_V2_REGS_color_frame_delay,line start to next frame start delay" hexmask.long 0x4 0.--31. 1. "FRAME_DELAY,delay in terms of main clock cycles from last line start to start of next frame" rgroup.long 0x2C++0x3 line.long 0x0 "TX_SHIM__VBUSP_MMR__CSI2TXIF_V2_REGS_control1,control register for csi tx wrapper" bitfld.long 0x0 16. "STRM_SEL,select to switch dma versus retransmit interface mux 0=dma 1=retransmit" "0: dma,1: retransmit" rbitfld.long 0x0 9. "STREAM1_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1" rbitfld.long 0x0 8. "STREAM0_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1" bitfld.long 0x0 0. "PIXEL_RESET,reset for the pixeal interface. 0=reset 1 not in reset. this should be asserted till after you program the csi controller configuration registers" "0: reset,?" rgroup.long 0x40++0x3 line.long 0x0 "TX_SHIM__VBUSP_MMR__CSI2TXIF_V2_REGS_f2f_delay,last line start to next frame start. Configuration for each of 16 virtual channels." hexmask.long 0x0 0.--31. 1. "DELAY,counter value delay of last line start of frame to first line of next frame" tree.end tree "csi_tx_if_v2_1_VBUS2APB_WRAP_VBUSP_APB_CSI2TX_V2 (csi_tx_if_v2_1_VBUS2APB_WRAP_VBUSP_APB_CSI2TX_V2)" base ad:0x4414000 rgroup.long 0x0++0x7 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_device_config,CSI-2 Transmitter Device Configuration Register" bitfld.long 0x0 26. "V1_3_FEATURES,: 1=CSI-2 v1.3 features only 0=v2.1 features available" "0: v2,1: CSI-2 v1" newline bitfld.long 0x0 25. "RX_COMP_MODE_PRESENT,RX Compatibility Mode: 1=implemented" "?,1: implemented" newline bitfld.long 0x0 20. "SCRAMBLER_PRESENT,Scrambler: 1=implemented" "?,1: implemented" newline bitfld.long 0x0 19. "ASF_PRESENT,Automotive Safety Features: 1=implemented" "?,1: implemented" newline hexmask.long.byte 0x0 14.--18. 1. "NUM_DTS,Number of Datatypes supported 8 or 16 only" newline hexmask.long.byte 0x0 9.--13. 1. "NUM_VCS,Number of Virtual Channels supported 4 or 16 only" newline bitfld.long 0x0 7.--8. "DATAPATH_SIZE,Internal datapath width 00: 32-bit." "0,1,2,3" newline bitfld.long 0x0 4.--6. "NUM_STREAMS,Number of Stream interfaces 1 2 or 4 only using direct encoding" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "CDNS_PHY_PRESENT,Cadence D-PHY present 1 = Yes" "?,1: Yes" newline bitfld.long 0x0 0.--2. "MAX_LANE_NB,Max Number of Lanes [1-4]" "0,1,2,3,4,5,6,7" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_status,CSI-2 Transmitter Status Register" bitfld.long 0x4 7. "RX_COMP_MODE_ACTIVE,RX Compatibility Mode Active Flag. When HIGH this bit indicates that RX Compatibility Mode is enabled." "0,1" newline bitfld.long 0x4 6. "ULP_MODE_ACTIVE,Ultra Low Power Mode Active Flag When HIGH this bit indicates that Ultra Low Power mode is active." "0,1" newline bitfld.long 0x4 5. "HS_MODE_ACTIVE,High Speed Mode Active Flag When HIGH this bit indicates that High Speed mode is active." "0,1" newline bitfld.long 0x4 4. "FRAME_TRANSMISSION_ACTIVE,Frame Transmission Active Flag When HIGH this bit indicates that frame transmission is active." "0,1" newline bitfld.long 0x4 3. "SCRAMBLER_ACTIVE,Scrambler Active Flag. When HIGH this bit indicates that the scrambler is enabled." "0,1" newline bitfld.long 0x4 2. "CONFIGURATION_ACTIVE,Configuration Mode Active Flag When HIGH this bit indicates that the CSI2TX module is in the configuration mode." "0,1" newline bitfld.long 0x4 1. "SOFT_RESET_ACTIVE,Soft Reset Active Flag When HIGH this bit indicates that soft reset is active." "0,1" newline bitfld.long 0x4 0. "BYPASS_MODE_ACTIVE,Bypass Mode Active Flag When HIGH this bit indicates that bypass mode is active." "0,1" rgroup.long 0x8++0xF line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_irq,CSI-2 Transmitter Interrupt Register. Write '1' to clear" bitfld.long 0x0 31. "LINE_NUMBER_ERROR3,Pixel IF 3 Line Number Error Flag - When HIGH this bit indicates that a line number error occurred." "0,1" newline bitfld.long 0x0 30. "BYTE_COUNT_MISMATCH_IRQ3,Pixel IF 3 Byte Count Mismatch Flag - When HIGH this bit indicates that a byte count mismatch occurred." "0,1" newline bitfld.long 0x0 29. "DATA_FLOW_ERR_IRQ3,Pixel IF 3 Data Flow Error Flag - When HIGH this bit indicates that data flow error has occurred caused by the Frame/Line valid being asserted when the D-PHY is not ready." "0,1" newline bitfld.long 0x0 28. "FIFO_UNDERFLOW_IRQ3,Pixel IF 3 FIFO Underflow Flag - When HIGH this bit indicates that at least one internal FIFO underflow occurred." "0,1" newline bitfld.long 0x0 27. "LINE_END_IRQ3,Pixel IF 3 Line End Flag - When HIGH this bit indicates that a line end occurred." "0,1" newline bitfld.long 0x0 26. "LINE_START_IRQ3,Pixel IF 3 Line Start Flag - When HIGH this bit indicates that a line start occurred." "0,1" newline bitfld.long 0x0 25. "FRAME_END_IRQ3,Pixel IF 3 Frame End Flag - When HIGH this bit indicates that a frame end occurred." "0,1" newline bitfld.long 0x0 24. "FRAME_START_IRQ3,Pixel IF 3 Frame Start Flag - When HIGH this bit indicates that a frame start occurred." "0,1" newline bitfld.long 0x0 23. "LINE_NUMBER_ERROR2,Pixel IF 2 Line Number Error Flag - When HIGH this bit indicates that a line number error occurred." "0,1" newline bitfld.long 0x0 22. "BYTE_COUNT_MISMATCH_IRQ2,Pixel IF 2 Byte Count Mismatch Flag - When HIGH this bit indicates that a byte count mismatch occurred." "0,1" newline bitfld.long 0x0 21. "DATA_FLOW_ERR_IRQ2,Pixel IF 2 Data Flow Error Flag - When HIGH this bit indicates that data flow error has occurred caused by the Frame/Line valid being asserted when the D-PHY is not ready." "0,1" newline bitfld.long 0x0 20. "FIFO_UNDERFLOW_IRQ2,Pixel IF 2 FIFO Underflow Flag - When HIGH this bit indicates that at least one internal FIFO underflow occurred." "0,1" newline bitfld.long 0x0 19. "LINE_END_IRQ2,Pixel IF 2 Line End Flag - When HIGH this bit indicates that a line end occurred." "0,1" newline bitfld.long 0x0 18. "LINE_START_IRQ2,Pixel IF 2 Line Start Flag - When HIGH this bit indicates that a line start occurred." "0,1" newline bitfld.long 0x0 17. "FRAME_END_IRQ2,Pixel IF 2 Frame End Flag - When HIGH this bit indicates that a frame end occurred." "0,1" newline bitfld.long 0x0 16. "FRAME_START_IRQ2,Pixel IF 2 Frame Start Flag - When HIGH this bit indicates that a frame start occurred." "0,1" newline bitfld.long 0x0 15. "LINE_NUMBER_ERROR1,Pixel IF 1 Line Number Error Flag - When HIGH this bit indicates that a line number error occurred." "0,1" newline bitfld.long 0x0 14. "BYTE_COUNT_MISMATCH_IRQ1,Pixel IF 1 Byte Count Mismatch Flag - When HIGH this bit indicates that a byte count mismatch occurred." "0,1" newline bitfld.long 0x0 13. "DATA_FLOW_ERR_IRQ1,Pixel IF 1 Data Flow Error Flag - When HIGH this bit indicates that data flow error has occurred caused by the Frame/Line valid being asserted when the D-PHY is not ready." "0,1" newline bitfld.long 0x0 12. "FIFO_UNDERFLOW_IRQ1,Pixel IF 1 FIFO Underflow Flag - When HIGH this bit indicates that at least one internal FIFO underflow occurred." "0,1" newline bitfld.long 0x0 11. "LINE_END_IRQ1,Pixel IF 1 Line End Flag - When HIGH this bit indicates that a line end occurred." "0,1" newline bitfld.long 0x0 10. "LINE_START_IRQ1,Pixel IF 1 Line Start Flag - When HIGH this bit indicates that a line start occurred." "0,1" newline bitfld.long 0x0 9. "FRAME_END_IRQ1,Pixel IF 1 Frame End Flag - When HIGH this bit indicates that a frame end occurred." "0,1" newline bitfld.long 0x0 8. "FRAME_START_IRQ1,Pixel IF 1 Frame Start Flag - When HIGH this bit indicates that a frame start occurred." "0,1" newline bitfld.long 0x0 7. "LINE_NUMBER_ERROR0,Pixel IF 0 Line Number Error Flag - When HIGH this bit indicates that a line number error occurred." "0,1" newline bitfld.long 0x0 6. "BYTE_COUNT_MISMATCH_IRQ0,Pixel IF 0 Byte Count Mismatch Flag - When HIGH this bit indicates that a byte count mismatch occurred." "0,1" newline bitfld.long 0x0 5. "DATA_FLOW_ERR_IRQ0,Pixel IF 0 Data Flow Error Flag - When HIGH this bit indicates that data flow error has occurred caused by the Frame/Line valid being asserted when the D-PHY is not ready." "0,1" newline bitfld.long 0x0 4. "FIFO_UNDERFLOW_IRQ0,Pixel IF 0 FIFO Underflow Flag - When HIGH this bit indicates that at least one internal FIFO underflow occurred." "0,1" newline bitfld.long 0x0 3. "LINE_END_IRQ0,Pixel IF 0 Line End Flag - When HIGH this bit indicates that a line end occurred." "0,1" newline bitfld.long 0x0 2. "LINE_START_IRQ0,Pixel IF 0 Line Start Flag - When HIGH this bit indicates that a line start occurred." "0,1" newline bitfld.long 0x0 1. "FRAME_END_IRQ0,Pixel IF 0 Frame End Flag - When HIGH this bit indicates that a frame end occurred." "0,1" newline bitfld.long 0x0 0. "FRAME_START_IRQ0,Pixel IF 0 Frame Start Flag - When HIGH this bit indicates that a frame start occurred." "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_irq_mask,CSI-2 Transmitter Interrupt Mask Register." bitfld.long 0x4 15. "MASK_LINE_NUMBER_ERROR1,Pixel IF 1 Line Number Error Mask - Writing 1 to this bit enables interrupt generation from the line_number_error_irq bit." "0,1" newline bitfld.long 0x4 14. "MASK_BYTE_COUNT_MISMATCH_IRQ1,Pixel IF 1 Byte Count Mismatch Mask - Writing 1 to this bit enables interrupt generation from the byte_count_mismatch_irq bit." "0,1" newline bitfld.long 0x4 13. "MASK_DATA_FLOW_ERR_IRQ1,Pixel IF 1 Data Flow Error Mask - Writing 1 to this bit enables interrupt generation from the data_flow_err_irq bit." "0,1" newline bitfld.long 0x4 12. "MASK_FIFO_UNDERFLOW_IRQ1,Pixel IF 1 FIFO Underflow Mask - Writing 1 to this bit enables interrupt generation from the fifo_underflow_irq bit." "0,1" newline bitfld.long 0x4 11. "MASK_LINE_END_IRQ1,Pixel IF 1 Line End Mask - Writing 1 to this bit enables interrupt generation from the line_en_irq bit." "0,1" newline bitfld.long 0x4 10. "MASK_LINE_START_IRQ1,Pixel IF 1 Line Start Mask - Writing 1 to this bit enables interrupt generation from the line_start_irq bit." "0,1" newline bitfld.long 0x4 9. "MASK_FRAME_END_IRQ1,Pixel IF 1 Frame End Mask - Writing 1 to this bit enables interrupt generation from the frame_end_irq bit." "0,1" newline bitfld.long 0x4 8. "MASK_FRAME_START_IRQ1,Pixel IF 1 Frame Start Mask - Writing 1 to this bit enables interrupt generation from the frame_start_irq bit." "0,1" newline bitfld.long 0x4 7. "MASK_LINE_NUMBER_ERROR0,Pixel IF 0 Line Number Error Mask - Writing 1 to this bit enables interrupt generation from the line_number_error_irq bit." "0,1" newline bitfld.long 0x4 6. "MASK_BYTE_COUNT_MISMATCH_IRQ0,Pixel IF 0 Byte Count Mismatch Mask - Writing 1 to this bit enables interrupt generation from the byte_count_mismatch_irq bit." "0,1" newline bitfld.long 0x4 5. "MASK_DATA_FLOW_ERR_IRQ0,Pixel IF 0 Data Flow Error Mask - Writing 1 to this bit enables interrupt generation from the data_flow_err_irq bit." "0,1" newline bitfld.long 0x4 4. "MASK_FIFO_UNDERFLOW_IRQ0,Pixel IF 0 FIFO Underflow Mask - Writing 1 to this bit enables interrupt generation from the fifo_underflow_irq bit." "0,1" newline bitfld.long 0x4 3. "MASK_LINE_END_IRQ0,Pixel IF 0 Line End Mask - Writing 1 to this bit enables interrupt generation from the line_en_irq bit." "0,1" newline bitfld.long 0x4 2. "MASK_LINE_START_IRQ0,Pixel IF 0 Line Start Mask - Writing 1 to this bit enables interrupt generation from the line_start_irq bit." "0,1" newline bitfld.long 0x4 1. "MASK_FRAME_END_IRQ0,Pixel IF 0 Frame End Mask - Writing 1 to this bit enables interrupt generation from the frame_end_irq bit." "0,1" newline bitfld.long 0x4 0. "MASK_FRAME_START_IRQ0,Pixel IF 0 Frame Start Mask - Writing 1 to this bit enables interrupt generation from the frame_start_irq bit." "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dphy_irq,D-PHY Transmitter Interrupt Status. Level sensitive interrupt bits driven by D-PHY signal pins. Write 1 to clear" bitfld.long 0x8 15. "ERR_CTRL_TX3_IRQ,D-PHY Transmitter Lane 3 ERR_CONTROL_IRQ" "0,1" newline bitfld.long 0x8 14. "ERR_CTRL_TX2_IRQ,D-PHY Transmitter Lane 2 ERR_CONTROL_IRQ" "0,1" newline bitfld.long 0x8 13. "ERR_CTRL_TX1_IRQ,D-PHY Transmitter Lane 1 ERR_CONTROL_IRQ" "0,1" newline bitfld.long 0x8 12. "ERR_CTRL_TX0_IRQ,D-PHY Transmitter Lane 0 ERR_CONTROL_IRQ" "0,1" newline bitfld.long 0x8 11. "ERR_ESC_TX3_IRQ,D-PHY Transmitter Lane 3 ERR_ESC_IRQ" "0,1" newline bitfld.long 0x8 10. "ERR_ESC_TX2_IRQ,D-PHY Transmitter Lane 2 ERR_ESC_IRQ" "0,1" newline bitfld.long 0x8 9. "ERR_ESC_TX1_IRQ,D-PHY Transmitter Lane 1 ERR_ESC_IRQ" "0,1" newline bitfld.long 0x8 8. "ERR_ESC_TX0_IRQ,D-PHY Transmitter Lane 0 ERR_ESC_IRQ" "0,1" newline bitfld.long 0x8 7. "ERR_SYNC_TX3_IRQ,D-PHY Transmitter Lane 3 ERR_SYNC_ESC_IRQ" "0,1" newline bitfld.long 0x8 6. "ERR_SYNC_TX2_IRQ,D-PHY Transmitter Lane 2 ERR_SYNC_ESC_IRQ" "0,1" newline bitfld.long 0x8 5. "ERR_SYNC_TX1_IRQ,D-PHY Transmitter Lane 1 ERR_SYNC_ESC_IRQ" "0,1" newline bitfld.long 0x8 4. "ERR_SYNC_TX0_IRQ,D-PHY Transmitter Lane 0 ERR_SYNC_ESC_IRQ" "0,1" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dphy_irq_mask,D-PHY Transmitter Interrupt Mask. Writing '1' to any bit enables interrupt generation when interrupt source signal is set and interrupts are enabled." bitfld.long 0xC 15. "MASK_ERR_CTRL_TX3_IRQ,D-PHY Transmitter Mask Lane 3 ERR_CONTROL_IRQ" "0,1" newline bitfld.long 0xC 14. "MASK_ERR_CTRL_TX2_IRQ,D-PHY Transmitter Mask Lane 2 ERR_CONTROL_IRQ" "0,1" newline bitfld.long 0xC 13. "MASK_ERR_CTRL_TX1_IRQ,D-PHY Transmitter Mask Lane 1 ERR_CONTROL_IRQ" "0,1" newline bitfld.long 0xC 12. "MASK_ERR_CTRL_TX0_IRQ,D-PHY Transmitter Mask Lane 0 ERR_CONTROL_IRQ" "0,1" newline bitfld.long 0xC 11. "MASK_ERR_ESC_TX3_IRQ,D-PHY Transmitter Mask Lane 3 ERR_ESC_IRQ" "0,1" newline bitfld.long 0xC 10. "MASK_ERR_ESC_TX2_IRQ,D-PHY Transmitter Mask Lane 2 ERR_ESC_IRQ" "0,1" newline bitfld.long 0xC 9. "MASK_ERR_ESC_TX1_IRQ,D-PHY Transmitter Mask Lane 1 ERR_ESC_IRQ" "0,1" newline bitfld.long 0xC 8. "MASK_ERR_ESC_TX0_IRQ,D-PHY Transmitter Mask Lane 0 ERR_ESC_IRQ" "0,1" newline bitfld.long 0xC 7. "MASK_ERR_SYNC_TX3_IRQ,D-PHY Transmitter Mask Lane 3 ERR_SYNC_ESC_IRQ" "0,1" newline bitfld.long 0xC 6. "MASK_ERR_SYNC_TX2_IRQ,D-PHY Transmitter Mask Lane 2 ERR_SYNC_ESC_IRQ" "0,1" newline bitfld.long 0xC 5. "MASK_ERR_SYNC_TX1_IRQ,D-PHY Transmitter Mask Lane 1 ERR_SYNC_ESC_IRQ" "0,1" newline bitfld.long 0xC 4. "MASK_ERR_SYNC_TX0_IRQ,D-PHY Transmitter Mask Lane 0 ERR_SYNC_ESC_IRQ" "0,1" rgroup.long 0x20++0x17 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_tx_conf,CSI-2 Transmitter Configuration Register." bitfld.long 0x0 31. "IRQ_ENABLE,Interrupt Enable - Writing 1 to this bit enables interrupts." "0,1" newline bitfld.long 0x0 5. "RX_V1_3_MAPPING,RX v1.3 Mapping Enable - Writing 1 to this bit make the TX Controller use pixel mappings for 8-bit data types which match that of the Cadence CSI-2 RX v1.3 Controller. This includes RAW8 Null .." "0,1" newline bitfld.long 0x0 4. "RX_COMP_ENABLE,RX Compatibility Mode Enable - Writing 1 to this bit enables RX Compatibility Mode." "0,1" newline bitfld.long 0x0 3. "SCRAMBLER_ENABLE,Scrambler Enable - Writing 1 to this bit enables scrambling on the ppi tx data bus." "0,1" newline bitfld.long 0x0 2. "CONFIGURATION_REQUEST,Configuration Request - Writing 1 to this bit enables configuration mode." "0,1" newline bitfld.long 0x0 1. "SOFT_RESET_REQUEST,Soft Reset Request - Writing 1 to this bit enables soft reset." "0,1" newline bitfld.long 0x0 0. "BYPASS_MODE_ENABLE,Bypass Mode - Enable Writing 1 to this bit enables bypass mode." "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_wait_burst_time,CSI-2 Transmitter D-PHY Wait Time Configuration Register." hexmask.long.byte 0x4 16.--23. 1. "TX_CLOCK_EXIT_TIME,Tx clock exit time - Number of ppi_tx_word_hs_clk cycles corresponding to the HS clock exit time." newline hexmask.long.byte 0x4 0.--7. 1. "WAIT_BURST_TIME_CNT,Wait Burst Time - Number of ppi_tx_word_hs_clk cycles corresponding to the inter HS burst gap." line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dphy_cfg,CSI-2 Transmitter D-PHY Lane Enable Configuration Register." bitfld.long 0x8 12. "DPHY_RESET_N,D-PHY Reset - Active low reset for D-PHY." "0,1" newline bitfld.long 0x8 11. "DPHY_CAL_ENABLE,D-PHY Calibration Enable. Enables calibration for D-PHY speeds over 1.5G." "0,1" newline bitfld.long 0x8 10. "DPHY_CLOCK_MODE,D-PHY Clock Mode. Select the D-PHY Clock Lane mode 0: Continuous 1: Non Continuous" "0: Continuous,1: Non Continuous" newline bitfld.long 0x8 8.--9. "DPHY_MODE,D-PHY Mode. Select the D-PHY clock mode during Non Continuous operation 00: Ultra Low Power 01: High Speed 10: Low Power Stop State 11: Reserved" "0: Ultra Low Power,1: High Speed,?,?" newline bitfld.long 0x8 4. "DPHY_CLK_ENABLE,D-PHY Clock Lane - Active high enable for D-PHY clock lane." "0,1" newline bitfld.long 0x8 3. "DPHY_LN_3_ENABLE,D-PHY Lane 3 Enable - Active high enable for D-PHY data lane 0." "0,1" newline bitfld.long 0x8 2. "DPHY_LN_2_ENABLE,D-PHY Lane 2 Enable - Active high enable for D-PHY data lane 0." "0,1" newline bitfld.long 0x8 1. "DPHY_LN_1_ENABLE,D-PHY Lane 1 Enable - Active high enable for D-PHY data lane 0." "0,1" newline bitfld.long 0x8 0. "DPHY_LN_0_ENABLE,D-PHY Lane 0 Enable - Active high enable for D-PHY data lane 0." "0,1" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dphy_clk_wakeup,CSI-2 Transmitter D-PHY Clock Lane Wakeup Time Configuration Register." hexmask.long.word 0xC 0.--15. 1. "ULPS_CLK_LANE_WAKEUP,D-PHY clock lane wakeup time in ppi_tx_esc_clk cycles." line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dphy_ulps_wakeup,CSI-2 Transmitter D-PHY Data Lane Wakeup Time Configuration Register." hexmask.long.word 0x10 0.--15. 1. "ULPS_DATA_LANE_WAKEUP,D-PHY data lane wakeup time in in ppi_tx_esc_clk cycles." line.long 0x14 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dphy_cfg1,D-PHY Transmitter Configuration." bitfld.long 0x14 8. "DPHY_DIFF_INVERT_C,D-PHY Transmitter invert differential pair on TX Clock Lane" "0,1" newline bitfld.long 0x14 7. "DPHY_DIFF_INVERT_LN_3,D-PHY Transmitter invert differential pair on TX Data Lane 3." "0,1" newline bitfld.long 0x14 6. "DPHY_DIFF_INVERT_LN_2,D-PHY Transmitter invert differential pair on TX Data Lane 2." "0,1" newline bitfld.long 0x14 5. "DPHY_DIFF_INVERT_LN_1,D-PHY Transmitter invert differential pair on TX Data Lane 1." "0,1" newline bitfld.long 0x14 4. "DPHY_DIFF_INVERT_LN_0,D-PHY Transmitter invert differential pair on TX Data Lane 0." "0,1" newline bitfld.long 0x14 3. "FORCE_STOP_MODE_LN_3,D-PHY Transmitter FORCE_STOP_MODE TX Data Lane 3." "0,1" newline bitfld.long 0x14 2. "FORCE_STOP_MODE_LN_2,D-PHY Transmitter FORCE_STOP_MODE TX Data Lane 2." "0,1" newline bitfld.long 0x14 1. "FORCE_STOP_MODE_LN_1,D-PHY Transmitter FORCE_STOP_MODE TX Data Lane 1." "0,1" newline bitfld.long 0x14 0. "FORCE_STOP_MODE_LN_0,D-PHY Transmitter FORCE_STOP_MODE TX Data Lane 0." "0,1" rgroup.long 0x38++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dphy_status,D-PHY Transmitter Status." bitfld.long 0x0 12. "DPHY_ULPS_ACTIVE_N_CLK,D-PHY Transmitter ULPS_ACTIVE_N Clock Lane Status." "0,1" newline bitfld.long 0x0 11. "DPHY_ULPS_ACTIVE_N_LN_3,D-PHY Transmitter ULPS_ACTIVE_N Data Lane 3 Status." "0,1" newline bitfld.long 0x0 10. "DPHY_ULPS_ACTIVE_N_LN_2,D-PHY Transmitter ULPS_ACTIVE_N Data Lane 2 Status." "0,1" newline bitfld.long 0x0 9. "DPHY_ULPS_ACTIVE_N_LN_1,D-PHY Transmitter ULPS_ACTIVE_N Data Lane 1 Status." "0,1" newline bitfld.long 0x0 8. "DPHY_ULPS_ACTIVE_N_LN_0,D-PHY Transmitter ULPS_ACTIVE_N Data Lane 0 Status." "0,1" newline bitfld.long 0x0 4. "DPHY_STOPSTATE_CLK,D-PHY Transmitter STOP_STATE Clock Lane Status." "0,1" newline bitfld.long 0x0 3. "DPHY_STOPSTATE_LN_3,D-PHY Transmitter STOP_STATE Data Lane 3 Status." "0,1" newline bitfld.long 0x0 2. "DPHY_STOPSTATE_LN_2,D-PHY Transmitter STOP_STATE Data Lane 2 Status." "0,1" newline bitfld.long 0x0 1. "DPHY_STOPSTATE_LN_1,D-PHY Transmitter STOP_STATE Data Lane 1 Status." "0,1" newline bitfld.long 0x0 0. "DPHY_STOPSTATE_LN_0,D-PHY Transmitter STOP_STATE Data Lane 0 Status." "0,1" rgroup.long 0x40++0x7F line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc0_cfg,CSI-2 Transmitter Virtual Channel 0 Configuration Register." hexmask.long.word 0x0 16.--31. 1. "VC_0_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 0." newline bitfld.long 0x0 0. "VC_0_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 0." "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc1_cfg,CSI-2 Transmitter Virtual Channel 1 Configuration Register." hexmask.long.word 0x4 16.--31. 1. "VC_1_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 1." newline bitfld.long 0x4 0. "VC_1_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 1." "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc2_cfg,CSI-2 Transmitter Virtual Channel 2 Configuration Register." hexmask.long.word 0x8 16.--31. 1. "VC_2_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 2." newline bitfld.long 0x8 0. "VC_2_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 2." "0,1" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc3_cfg,CSI-2 Transmitter Virtual Channel 3 Configuration Register." hexmask.long.word 0xC 16.--31. 1. "VC_3_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 3." newline bitfld.long 0xC 0. "VC_3_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 3." "0,1" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc4_cfg,CSI-2 Transmitter Virtual Channel 4 Configuration Register." hexmask.long.word 0x10 16.--31. 1. "VC_4_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 4." newline bitfld.long 0x10 0. "VC_4_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 4." "0,1" line.long 0x14 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc5_cfg,CSI-2 Transmitter Virtual Channel 5 Configuration Register." hexmask.long.word 0x14 16.--31. 1. "VC_5_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 5." newline bitfld.long 0x14 0. "VC_5_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 5." "0,1" line.long 0x18 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc6_cfg,CSI-2 Transmitter Virtual Channel 6 Configuration Register." hexmask.long.word 0x18 16.--31. 1. "VC_6_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 6." newline bitfld.long 0x18 0. "VC_6_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 6." "0,1" line.long 0x1C "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc7_cfg,CSI-2 Transmitter Virtual Channel 7 Configuration Register." hexmask.long.word 0x1C 16.--31. 1. "VC_7_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 7." newline bitfld.long 0x1C 0. "VC_7_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 7." "0,1" line.long 0x20 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc8_cfg,CSI-2 Transmitter Virtual Channel 8 Configuration Register." hexmask.long.word 0x20 16.--31. 1. "VC_8_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 8." newline bitfld.long 0x20 0. "VC_8_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 8." "0,1" line.long 0x24 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc9_cfg,CSI-2 Transmitter Virtual Channel 9 Configuration Register." hexmask.long.word 0x24 16.--31. 1. "VC_9_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 9." newline bitfld.long 0x24 0. "VC_9_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 9." "0,1" line.long 0x28 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc10_cfg,CSI-2 Transmitter Virtual Channel 10 Configuration Register." hexmask.long.word 0x28 16.--31. 1. "VC_10_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 10." newline bitfld.long 0x28 0. "VC_10_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 10." "0,1" line.long 0x2C "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc11_cfg,CSI-2 Transmitter Virtual Channel 11 Configuration Register." hexmask.long.word 0x2C 16.--31. 1. "VC_11_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 11." newline bitfld.long 0x2C 0. "VC_11_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 11." "0,1" line.long 0x30 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc12_cfg,CSI-2 Transmitter Virtual Channel 12 Configuration Register." hexmask.long.word 0x30 16.--31. 1. "VC_12_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 12." newline bitfld.long 0x30 0. "VC_12_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 12." "0,1" line.long 0x34 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc13_cfg,CSI-2 Transmitter Virtual Channel 13 Configuration Register." hexmask.long.word 0x34 16.--31. 1. "VC_13_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 13." newline bitfld.long 0x34 0. "VC_13_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 13." "0,1" line.long 0x38 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc14_cfg,CSI-2 Transmitter Virtual Channel 14 Configuration Register." hexmask.long.word 0x38 16.--31. 1. "VC_14_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 14." newline bitfld.long 0x38 0. "VC_14_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 14." "0,1" line.long 0x3C "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_vc15_cfg,CSI-2 Transmitter Virtual Channel 15 Configuration Register." hexmask.long.word 0x3C 16.--31. 1. "VC_15_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 15." newline bitfld.long 0x3C 0. "VC_15_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 15." "0,1" line.long 0x40 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt0_cfg,CSI-2 Transmitter Data Type 0 Configuration Register with pixel_dt_sel[:] = 0." bitfld.long 0x40 9. "DT_0_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32-bit words on the pixel interface the data is sent with the defined Data Type 0 with pixel_dt_sel[:] = 0. This bit is also used for quad pixel 8-bit data types." "0,1" newline bitfld.long 0x40 8. "DT_0_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 0 with pixel_dt_sel[:] = 0." "0,1" newline hexmask.long.byte 0x40 2.--7. 1. "DT_0_DATA_TYPE,Data Type - Type of data on Data Type 0 with pixel_dt_sel[:] = 0. Default ED [0x12]" newline bitfld.long 0x40 1. "DT_0_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 0." "0,1" newline bitfld.long 0x40 0. "DT_0_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 0." "0,1" line.long 0x44 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt0_format,CSI-2 Transmitter Data Type 0 Format Register." hexmask.long.word 0x44 16.--31. 1. "DT_0_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 0 with pixel_dt_sel[:] = 0." newline hexmask.long.word 0x44 0.--15. 1. "DT_0_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 0 with pixel_dt_sel[:] = 0." line.long 0x48 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt1_cfg,CSI-2 Transmitter Data Type 1 Configuration Register with pixel_dt_sel[:] = 1." bitfld.long 0x48 9. "DT_1_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32-bit words on the pixel interface the data is sent with the defined Data Type 1 with pixel_dt_sel[:] = 1. This bit is also used for quad pixel 8-bit data types." "0,1" newline bitfld.long 0x48 8. "DT_1_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 1 with pixel_dt_sel[:] = 1." "0,1" newline hexmask.long.byte 0x48 2.--7. 1. "DT_1_DATA_TYPE,Data Type - Type of data on Data Type 1 with pixel_dt_sel[:] = 1. Default YUV422 8bit [0x1E]" newline bitfld.long 0x48 1. "DT_1_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 1." "0,1" newline bitfld.long 0x48 0. "DT_1_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 1." "0,1" line.long 0x4C "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt1_format,CSI-2 Transmitter Data Type 1 Format Register." hexmask.long.word 0x4C 16.--31. 1. "DT_1_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 1 with pixel_dt_sel[:] = 1." newline hexmask.long.word 0x4C 0.--15. 1. "DT_1_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 1 with pixel_dt_sel[:] = 1." line.long 0x50 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt2_cfg,CSI-2 Transmitter Data Type 2 Configuration Register with pixel_dt_sel[:] = 2." bitfld.long 0x50 9. "DT_2_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32-bit words on the pixel interface the data is sent with the defined Data Type 2 with pixel_dt_sel[:] = 2. This bit is also used for quad pixel 8-bit data types." "0,1" newline bitfld.long 0x50 8. "DT_2_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 2 with pixel_dt_sel[:] = 2." "0,1" newline hexmask.long.byte 0x50 2.--7. 1. "DT_2_DATA_TYPE,Data Type - Type of data on Data Type 2 with pixel_dt_sel[:] = 2. Default RAW8 [0x2A]" newline bitfld.long 0x50 1. "DT_2_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 2." "0,1" newline bitfld.long 0x50 0. "DT_2_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 2." "0,1" line.long 0x54 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt2_format,CSI-2 Transmitter Data Type 2 Format Register." hexmask.long.word 0x54 16.--31. 1. "DT_2_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 2 with pixel_dt_sel[:] = 2." newline hexmask.long.word 0x54 0.--15. 1. "DT_2_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 2 with pixel_dt_sel[:] = 2." line.long 0x58 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt3_cfg,CSI-2 Transmitter Data Type 3 Configuration Register with pixel_dt_sel[:] = 3." bitfld.long 0x58 9. "DT_3_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32-bit words on the pixel interface the data is sent with the defined Data Type 3 with pixel_dt_sel[:] = 3. This bit is also used for quad pixel 8-bit data types." "0,1" newline bitfld.long 0x58 8. "DT_3_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 3 with pixel_dt_sel[:] = 3." "0,1" newline hexmask.long.byte 0x58 2.--7. 1. "DT_3_DATA_TYPE,Data Type - Type of data on Data Type 3 with pixel_dt_sel[:] = 3. Default RGB888 [0x24]" newline bitfld.long 0x58 1. "DT_3_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 3." "0,1" newline bitfld.long 0x58 0. "DT_3_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 3." "0,1" line.long 0x5C "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt3_format,CSI-2 Transmitter Data Type 3 Format Register." hexmask.long.word 0x5C 16.--31. 1. "DT_3_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 3 with pixel_dt_sel[:] = 3." newline hexmask.long.word 0x5C 0.--15. 1. "DT_3_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 3 with pixel_dt_sel[:] = 3." line.long 0x60 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt4_cfg,CSI-2 Transmitter Data Type 4 Configuration Register with pixel_dt_sel[:] = 4." bitfld.long 0x60 9. "DT_4_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32-bit words on the pixel interface the data is sent with the defined Data Type 4 with pixel_dt_sel[:] = 4. This bit is also used for quad pixel 8-bit data types." "0,1" newline bitfld.long 0x60 8. "DT_4_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 4 with pixel_dt_sel[:] = 4." "0,1" newline hexmask.long.byte 0x60 2.--7. 1. "DT_4_DATA_TYPE,Data Type - Type of data on Data Type 4 with pixel_dt_sel[:] = 4." newline bitfld.long 0x60 1. "DT_4_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 4." "0,1" newline bitfld.long 0x60 0. "DT_4_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 4." "0,1" line.long 0x64 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt4_format,CSI-2 Transmitter Data Type 4 Format Register." hexmask.long.word 0x64 16.--31. 1. "DT_4_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 4 with pixel_dt_sel[:] = 4." newline hexmask.long.word 0x64 0.--15. 1. "DT_4_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 4 with pixel_dt_sel[:] = 4." line.long 0x68 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt5_cfg,CSI-2 Transmitter Data Type 5 Configuration Register with pixel_dt_sel[:] = 5." bitfld.long 0x68 9. "DT_5_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32-bit words on the pixel interface the data is sent with the defined Data Type 5 with pixel_dt_sel[:] = 5. This bit is also used for quad pixel 8-bit data types." "0,1" newline bitfld.long 0x68 8. "DT_5_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 5 with pixel_dt_sel[:] = 5." "0,1" newline hexmask.long.byte 0x68 2.--7. 1. "DT_5_DATA_TYPE,Data Type - Type of data on Data Type 5 with pixel_dt_sel[:] = 5." newline bitfld.long 0x68 1. "DT_5_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 5." "0,1" newline bitfld.long 0x68 0. "DT_5_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 5." "0,1" line.long 0x6C "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt5_format,CSI-2 Transmitter Data Type 5 Format Register." hexmask.long.word 0x6C 16.--31. 1. "DT_5_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 5 with pixel_dt_sel[:] = 5." newline hexmask.long.word 0x6C 0.--15. 1. "DT_5_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 5 with pixel_dt_sel[:] = 5." line.long 0x70 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt6_cfg,CSI-2 Transmitter Data Type 6 Configuration Register with pixel_dt_sel[:] = 6." bitfld.long 0x70 9. "DT_6_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32-bit words on the pixel interface the data is sent with the defined Data Type 6 with pixel_dt_sel[:] = 6. This bit is also used for quad pixel 8-bit data types." "0,1" newline bitfld.long 0x70 8. "DT_6_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 6 with pixel_dt_sel[:] = 6." "0,1" newline hexmask.long.byte 0x70 2.--7. 1. "DT_6_DATA_TYPE,Data Type - Type of data on Data Type 6 with pixel_dt_sel[:] = 6." newline bitfld.long 0x70 1. "DT_6_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 6." "0,1" newline bitfld.long 0x70 0. "DT_6_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 6." "0,1" line.long 0x74 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt6_format,CSI-2 Transmitter Data Type 6 Format Register." hexmask.long.word 0x74 16.--31. 1. "DT_6_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 6 with pixel_dt_sel[:] = 6." newline hexmask.long.word 0x74 0.--15. 1. "DT_6_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 6 with pixel_dt_sel[:] = 6." line.long 0x78 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt7_cfg,CSI-2 Transmitter Data Type 7 Configuration Register with pixel_dt_sel[:] = 7." bitfld.long 0x78 9. "DT_7_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32-bit words on the pixel interface the data is sent with the defined Data Type 7 with pixel_dt_sel[:] = 7. This bit is also used for quad pixel 8-bit data types." "0,1" newline bitfld.long 0x78 8. "DT_7_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 7 with pixel_dt_sel[:] = 7." "0,1" newline hexmask.long.byte 0x78 2.--7. 1. "DT_7_DATA_TYPE,Data Type - Type of data on Data Type 7 with pixel_dt_sel[:] = 7." newline bitfld.long 0x78 1. "DT_7_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 7." "0,1" newline bitfld.long 0x78 0. "DT_7_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 7." "0,1" line.long 0x7C "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_dt7_format,CSI-2 Transmitter Data Type 7 Format Register." hexmask.long.word 0x7C 16.--31. 1. "DT_7_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 7 with pixel_dt_sel[:] = 7." newline hexmask.long.word 0x7C 0.--15. 1. "DT_7_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 7 with pixel_dt_sel[:] = 7." rgroup.long 0x100++0x7 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_stream_if_0_cfg,CSI-2 Stream 0 Configuration Register." hexmask.long.word 0x0 0.--11. 1. "STREAM_IF_0_FILL_LEVEL,Fill Level - Minimum number of packed 32 words loaded into the stream fifo before Tx will start for Stream if 0." line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_stream_if_1_cfg,CSI-2 Stream 1 Configuration Register." bitfld.long 0x4 23. "STREAM_IF_1_SLAVE_MODE,Stream Slave Mode suppresses frame start/end packets in stream 1. To be used when DT interleving is required in the same VC. NOTE: the stream must then be paired with stream O as the master on the StreamIF" "0,1" newline hexmask.long.word 0x4 0.--11. 1. "STREAM_IF_1_FILL_LEVEL,Fill Level - Minimum number of packed 32 words loaded into the stream fifo before Tx will start for Stream if 1." rgroup.long 0x200++0xB line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_epd_en_ssp,CSI-2 Transmitter EPD Enable and Short Packet Spacers Register" bitfld.long 0x0 15. "EPD_ENABLE,EPD enable. Set high to enable EPD operation." "0,1" newline hexmask.long.word 0x0 0.--14. 1. "EPD_SP_SPACERS,EPD Short Packet Spacers: EPD Option 1: Minimum number of Spacer Bytes per Lane following a Short Packet. EPD Option 2: Fixed number of Spacer Bytes per Lane following a.." line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_epd_op_slp,CSI-2 Transmitter EPD Option and Long Packet Spacers Register" bitfld.long 0x4 15. "EPD_OPTION,EPD Option. 1'b0: D-PHY EPD Option 1 1'b1: D-PHY EPD Option 2" "0: D-PHY EPD Option 1 1'b1: D-PHY EPD Option 2,?" newline hexmask.long.word 0x4 0.--14. 1. "EPD_LP_SPACERS,EPD Long Packet Spacers: EPD Option 1: Minimum number of Spacer Bytes per Lane following a Long Packet. EPD Option 2: Fixed number of Spacer Bytes per Lane following a.." line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_epd_clkidlehs_min,CSI-2 Transmitter EPD Minimum HS Clock Idle Time Register" hexmask.long.word 0x8 0.--15. 1. "EPD_OPTION1_CLKIDLEHS_MIN,For LRTE EPD Option 1 this sets the minimum number of pclk cycles required to meet the D-PHY timing requirement for THS-IDLE-CLKHS0." rgroup.long 0xD00++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_debug_cfg,CSI-2 Transmitter Debug Enable Register." bitfld.long 0x0 0. "DBG_EN,Debug Enable. This bit enables debug when high. If low then other DEBUG registers read 0." "0,1" rgroup.long 0xD04++0x1B line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_debug_ln_fsm,Debug Register for Lane FSM." bitfld.long 0x0 9. "NEW_BURST_ALLOWED,Lane Mangement FSM. New burst allowed - WAIT_BURST_TIME expired" "0,1" newline bitfld.long 0x0 8. "PACKET_VALID_R,Lane Mangement FSM. Valid packet in packet register" "0,1" newline bitfld.long 0x0 7. "PACKET_VALID_IN,Lane Mangement FSM. Valid packet at input" "0,1" newline bitfld.long 0x0 6. "END_OF_BURST,Lane Mangement FSM. End of High speed burst" "0,1" newline bitfld.long 0x0 5. "TRANS_ACTIVE,Lane Mangement FSM. HS transmission active" "0,1" newline bitfld.long 0x0 4. "START_HS_TRANS,Lane Mangement FSM. HS transmission ready" "0,1" newline bitfld.long 0x0 0.--2. "LANE_MGR_FSM_ST,Lane Mangement FSM. State of Lane Management FSM" "0,1,2,3,4,5,6,7" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_debug_clk_ln_fsm,Debug Register for Clock Lane FSM" bitfld.long 0x4 13. "ULPS_ACTIVE_CLK,Clock Lane FSM. ULPS active from D-PHY" "0,1" newline bitfld.long 0x4 12. "ULPS_MODE_ACTIVE,Clock Lane FSM. ULPS mode active" "0,1" newline bitfld.long 0x4 11. "ULPS_EXIT_CLK_PPI,Clock Lane FSM. ULPS EXIT Request to D-PHY" "0,1" newline bitfld.long 0x4 10. "ULPS_REQUEST_CLK_PPI,Clock Lane FSM. ULPS request to D-PHY" "0,1" newline bitfld.long 0x4 9. "HS_MODE_ACTIVE_CLK,Clock Lane FSM. High speed mode active" "0,1" newline bitfld.long 0x4 8. "REQUEST_HS_CLK_PPI,Clock Lane FSM. High speed clock request" "0,1" newline bitfld.long 0x4 7. "READY_HS_CLK,Clock Lane FSM. High speed clock active from D-PHY" "0,1" newline bitfld.long 0x4 6. "ULPS_WAKEUP_COUNT_DONE_CL,Clock Lane FSM. Clock lane ULPS wakeup counter expired" "0,1" newline bitfld.long 0x4 5. "ULPS_REQUEST_CLK,Clock Lane FSM. Request ULPS mode" "0,1" newline bitfld.long 0x4 4. "HS_MODE_REQ,Clock Lane FSM. Request High Speed mode" "0,1" newline bitfld.long 0x4 2.--3. "ULPS_CLK_FSM,Clock Lane FSM. State of ULPS control FSM." "0,1,2,3" newline bitfld.long 0x4 0.--1. "HS_CLK_FSM,Clock Lane FSM. State of High Speed Clock FSM." "0,1,2,3" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_debug_data_ln_fsm,Debug Register for Data Lane FSM." bitfld.long 0x8 16. "ULPS_ACTIVE,Data Lane FSM. Clock and data lane ULPS active" "0,1" newline bitfld.long 0x8 15. "DATA_ULPS_ACTIVE,Debug Register for Data Lane FSM. Data lane ULPS active" "0,1" newline bitfld.long 0x8 14. "TX_ULPS_EXIT_ESC,Data Lane FSM. Exit escape mode to D-PHY" "0,1" newline bitfld.long 0x8 13. "TX_ULPS_ESC,Data Lane FSM. ULPS escape mode to D-PHY" "0,1" newline bitfld.long 0x8 12. "TX_REQUEST_ESC,Data Lane FSM. Request escape mode to D-PHY" "0,1" newline bitfld.long 0x8 10. "ULPS_WAKEUP_COUNT_DONE_DL,Data Lane FSM. Data Lane ULPS wakeup counter expired" "0,1" newline hexmask.long.byte 0x8 6.--9. 1. "ULPS_ACTIVE_N,Data Lane FSM. Data Lane ULPS active from D-PHY" newline bitfld.long 0x8 5. "HS_MODE_REQ_SYNC,Data Lane FSM. HS Mode request" "0,1" newline bitfld.long 0x8 4. "ULPS_REQ_SYNC,Data Lane FSM. ULPS Request" "0,1" newline bitfld.long 0x8 0.--1. "ULPS_DATA_LANE_FSM,Data Lane FSM. State of Data Lane FSM FSM" "0,1,2,3" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_debug_prot0_fsm,Debug Register for Pixel IF0 Protocol FSM." hexmask.long.byte 0xC 15.--18. 1. "VIRTUAL_CHANNEL_IF0,Pixel IF0 Protocol FSM. State of the top level Virtual Channel select signals State of the Virtual Channel[3:2] select signals when VCX enabled otherwise '00' and state of the Virtual Channel[1:0]" newline bitfld.long 0xC 12.--14. "DATA_TYPE_IF0,Pixel IF0 Protocol FSM. State of the Data Type select signals" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 11. "FRAME_VALID_IF0,Pixel IF0 Protocol FSM. State of the Frame Valid signal" "0,1" newline bitfld.long 0xC 10. "LINE_VALID_IF0,Pixel IF0 Protocol FSM. State of the Line Valid signal" "0,1" newline bitfld.long 0xC 8. "LAST_PAYLOAD_DATA_IF0,Pixel IF0 Protocol FSM. Last payload data in long packet" "0,1" newline bitfld.long 0xC 7. "PAYLOAD_FIFO_EMPTY_IF0,Pixel IF0 Protocol FSM. Payload FIFO empty" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "PROT_FSM_IF0,Pixel IF0 Protocol FSM. State of Protocol Control FSM" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_debug_prot1_fsm,Debug Register for Pixel IF1 Protocol FSM. (Optional: Available when PIXEL_IF2 or 4)" hexmask.long.byte 0x10 15.--18. 1. "VIRTUAL_CHANNEL_IF1,Pixel IF1 Protocol FSM. State of the top level Virtual Channel select signals State of the Virtual Channel[3:2] select signals when VCX enabled otherwise '00' and state of the Virtual Channel[1:0]" newline bitfld.long 0x10 12.--14. "DATA_TYPE_IF1,Pixel IF1 Protocol FSM. State of the Data Type select signals" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 11. "FRAME_VALID_IF1,Pixel IF1 Protocol FSM. State of the Frame Valid signal" "0,1" newline bitfld.long 0x10 10. "LINE_VALID_IF1,Pixel IF1 Protocol FSM. State of the Line Valid signal" "0,1" newline bitfld.long 0x10 8. "LAST_PAYLOAD_DATA_IF1,Pixel IF1 Protocol FSM. Last payload data in long packet" "0,1" newline bitfld.long 0x10 7. "PAYLOAD_FIFO_EMPTY_IF1,Pixel IF1 Protocol FSM. Payload FIFO empty" "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "PROT_FSM_IF1,Pixel IF1 Protocol FSM. State of Protocol Control FSM" line.long 0x14 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_debug_prot2_fsm,Debug Register for Pixel IF2 Protocol FSM. (Optional: Available when PIXEL_IF4)" hexmask.long.byte 0x14 15.--18. 1. "VIRTUAL_CHANNEL_IF2,Pixel IF2 Protocol FSM. State of the top level Virtual Channel select signals State of the Virtual Channel[3:2] select signals when VCX enabled otherwise '00' and state of the Virtual Channel[1:0]" newline bitfld.long 0x14 12.--14. "DATA_TYPE_IF2,Pixel IF2 Protocol FSM. State of the Data Type select signals" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 11. "FRAME_VALID_IF2,Pixel IF2 Protocol FSM. State of the Frame Valid signal" "0,1" newline bitfld.long 0x14 10. "LINE_VALID_IF2,Pixel IF2 Protocol FSM. State of the Line Valid signal" "0,1" newline bitfld.long 0x14 8. "LAST_PAYLOAD_DATA_IF2,Pixel IF2 Protocol FSM. Last payload data in long packet" "0,1" newline bitfld.long 0x14 7. "PAYLOAD_FIFO_EMPTY_IF2,Pixel IF2 Protocol FSM. Payload FIFO empty" "0,1" newline hexmask.long.byte 0x14 0.--6. 1. "PROT_FSM_IF2,Pixel IF2 Protocol FSM. State of Protocol Control FSM" line.long 0x18 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_debug_prot3_fsm,Debug Register for Pixel IF3 Protocol FSM. (Optional: Available when PIXEL_IF4)" hexmask.long.byte 0x18 15.--18. 1. "VIRTUAL_CHANNEL_IF3,Pixel IF3 Protocol FSM. State of the top level Virtual Channel select signals State of the Virtual Channel[3:2] select signals when VCX enabled otherwise '00' and state of the Virtual Channel[1:0]" newline bitfld.long 0x18 12.--14. "DATA_TYPE_IF3,Pixel IF3 Protocol FSM. State of the Data Type select signals" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 11. "FRAME_VALID_IF3,Pixel IF3 Protocol FSM. State of the Frame Valid signal" "0,1" newline bitfld.long 0x18 10. "LINE_VALID_IF3,Pixel IF3 Protocol FSM. State of the Line Valid signal" "0,1" newline bitfld.long 0x18 8. "LAST_PAYLOAD_DATA_IF3,Pixel IF3 Protocol FSM. Last payload data in long packet" "0,1" newline bitfld.long 0x18 7. "PAYLOAD_FIFO_EMPTY_IF3,Pixel IF3 Protocol FSM. Payload FIFO empty" "0,1" newline hexmask.long.byte 0x18 0.--6. 1. "PROT_FSM_IF3,Pixel IF3 Protocol FSM. State of Protocol Control FSM" rgroup.long 0xDF8++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_test_generic_status,GPIO - Generic test status register that read primary inputs: test_generic_status" hexmask.long.word 0x0 0.--15. 1. "STATUS,Test status - Directly reflects after resynchronisation into the pclk domain the state of 'test_generic_status' primary inputs." rgroup.long 0xDFC++0x17 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_test_generic_ctrl,GPIO - Generic test control register that controls primary outputs: test_generic_ctrl." hexmask.long.word 0x0 0.--15. 1. "CTRL,Test control - Directly controls primary outputs 'test_generic_ctrl'" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_int_status,ASF Interrupt Status Register. This register indicates the source of ASF interrupts. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register.." hexmask.long 0x4 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x4 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1" newline bitfld.long 0x4 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1" newline bitfld.long 0x4 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1" newline bitfld.long 0x4 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x4 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1" newline bitfld.long 0x4 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x4 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_int_raw_status,ASF Interrupt Raw Status Register. A bit set in this raw register indicates a source of ASF fault in the corresponding feature. Writing to either raw or masked status registers. clear both.." hexmask.long 0x8 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x8 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1" newline bitfld.long 0x8 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1" newline bitfld.long 0x8 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1" newline bitfld.long 0x8 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x8 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1" newline bitfld.long 0x8 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x8 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_int_mask,The ASF interrupt mask register indicating which interrupt bits in the ASF interrupt status register are masked. All bits are set at reset. Clear the individual bit to enable the corresponding.." hexmask.long 0xC 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0xC 6. "ASF_INTEGRITY_ERR_MASK,Mask bit for integrity error interrupt" "0,1" newline bitfld.long 0xC 5. "ASF_PROTOCOL_ERR_MASK,Mask bit for protocol error interrupt." "0,1" newline bitfld.long 0xC 4. "ASF_TRANS_TO_ERR_MASK,Mask bit for transaction timeouts error interrupt." "0,1" newline bitfld.long 0xC 3. "ASF_CSR_ERR_MASK,Mask bit for configuration and status registers error interrupt." "0,1" newline bitfld.long 0xC 2. "ASF_DAP_ERR_MASK,Mask bit for data and address paths parity error interrupt." "0,1" newline bitfld.long 0xC 1. "ASF_SRAM_UNCORR_ERR_MASK,Mask bit for SRAM uncorrectable error interrupt." "0,1" newline bitfld.long 0xC 0. "ASF_SRAM_CORR_ERR_MASK,Mask bit for SRAM correctable error interrupt." "0,1" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_int_test,The ASF interrupt test register emulate hardware even. Write one to individual bit to trigger single event in (masked and raw) status registers according to mask and will generate interrupt accordingly." hexmask.long 0x10 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x10 6. "ASF_INTEGRITY_ERR_TEST,Test bit for integrity error interrupt" "0,1" newline bitfld.long 0x10 5. "ASF_PROTOCOL_ERR_TEST,Test bit for protocol error interrupt." "0,1" newline bitfld.long 0x10 4. "ASF_TRANS_TO_ERR_TEST,Test bit for transaction timeouts error interrupt." "0,1" newline bitfld.long 0x10 3. "ASF_CSR_ERR_TEST,Test bit for configuration and status registers error interrupt." "0,1" newline bitfld.long 0x10 2. "ASF_DAP_ERR_TEST,Test bit for data and address paths parity error interrupt." "0,1" newline bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR_TEST,Test bit for SRAM uncorrectable error interrupt." "0,1" newline bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR_TEST,Test bit for SRAM correctable error interrupt." "0,1" line.long 0x14 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_fatal_nonfatal_select,The fatal or non-fatal interrupt register selects whether a fatal (asf_int_fatal) or non-fatal (asf_int_nonfatal) interrupt is triggered. If the bit of the event will be set to one then.." hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x14 6. "ASF_INTEGRITY_ERR,Enable integrity error interrupt as fatal" "0,1" newline bitfld.long 0x14 5. "ASF_PROTOCOL_ERR,Enable protocol error interrupt as fatal." "0,1" newline bitfld.long 0x14 4. "ASF_TRANS_TO_ERR,Enable transaction timeouts error interrupt as fatal." "0,1" newline bitfld.long 0x14 3. "ASF_CSR_ERR,Enable configuration and status registers error interrupt as fatal." "0,1" newline bitfld.long 0x14 2. "ASF_DAP_ERR,Enable data and address paths parity error interrupt as fatal." "0,1" newline bitfld.long 0x14 1. "ASF_SRAM_UNCORR_ERR,Enable SRAM uncorrectable error interrupt as fatal." "0,1" newline bitfld.long 0x14 0. "ASF_SRAM_CORR_ERR,Enable SRAM correctable error interrupt as fatal." "0,1" rgroup.long 0xE20++0x7 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_sram_corr_fault_status,Status register for SRAM correctable fault. These fields are updated whenever asf_sram_corr_fault input is active." hexmask.long.byte 0x0 24.--31. 1. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault." newline hexmask.long.tbyte 0x0 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault." line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_sram_uncorr_fault_status,Status register for SRAM uncorrectable fault. These fields are updated whenever asf_sram_uncorr_fault input is active." hexmask.long.byte 0x4 24.--31. 1. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault." newline hexmask.long.tbyte 0x4 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault." rgroup.long 0xE28++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_sram_fault_stats,Statistics register for SRAM faults. Note that this register clears when software writes to any field." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline hexmask.long.word 0x0 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS,Count of number of correctable errors if implemented. Count value will saturate at 0xffff." rgroup.long 0xE30++0xB line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_trans_to_ctrl,Control register to configure the ASF transaction timeout monitors." bitfld.long 0x0 31. "ASF_TRANS_TO_EN,Enable transaction timeout monitoring." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "ASF_TRANS_TO_CTRL,Timer value to use for transaction timeout monitor." line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_trans_to_fault_mask,Control register to mask out ASF transaction timeout faults from triggering interrupts. On reset. all bits are set to mask out all sources. Clear the corresponding bit to enable the.." bitfld.long 0x4 4. "ASF_TRANS_TO_FAULT_4_MASK,Mask register for each ASF transaction timeout fault source." "0,1" newline bitfld.long 0x4 3. "ASF_TRANS_TO_FAULT_3_MASK,Mask register for each ASF transaction timeout fault source." "0,1" newline bitfld.long 0x4 2. "ASF_TRANS_TO_FAULT_2_MASK,Mask register for each ASF transaction timeout fault source." "0,1" newline bitfld.long 0x4 1. "ASF_TRANS_TO_FAULT_1_MASK,Mask register for each ASF transaction timeout fault source." "0,1" newline bitfld.long 0x4 0. "ASF_TRANS_TO_FAULT_0_MASK,Mask register for each ASF transaction timeout fault source." "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_trans_to_fault_status,Status register for transaction timeouts fault. If a fault occurs the revelant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit." bitfld.long 0x8 4. "ASF_TRANS_TO_FAULT_4_STATUS,Status bits for transaction timeouts faults." "0,1" newline bitfld.long 0x8 3. "ASF_TRANS_TO_FAULT_3_STATUS,Status bits for transaction timeouts faults." "0,1" newline bitfld.long 0x8 2. "ASF_TRANS_TO_FAULT_2_STATUS,Status bits for transaction timeouts faults." "0,1" newline bitfld.long 0x8 1. "ASF_TRANS_TO_FAULT_1_STATUS,Status bits for transaction timeouts faults." "0,1" newline bitfld.long 0x8 0. "ASF_TRANS_TO_FAULT_0_STATUS,Status bits for transaction timeouts faults." "0,1" rgroup.long 0xE40++0x7 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_protocol_fault_mask,Control register to mask out ASF Protocol faults from triggering interrupts. On reset. all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt source." bitfld.long 0x0 16. "ASF_PROTOCOL_FAULT_16_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 15. "ASF_PROTOCOL_FAULT_15_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 14. "ASF_PROTOCOL_FAULT_14_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 13. "ASF_PROTOCOL_FAULT_13_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 12. "ASF_PROTOCOL_FAULT_12_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 11. "ASF_PROTOCOL_FAULT_11_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 10. "ASF_PROTOCOL_FAULT_10_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 9. "ASF_PROTOCOL_FAULT_9_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 8. "ASF_PROTOCOL_FAULT_8_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 7. "ASF_PROTOCOL_FAULT_7_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 6. "ASF_PROTOCOL_FAULT_6_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 5. "ASF_PROTOCOL_FAULT_5_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 4. "ASF_PROTOCOL_FAULT_4_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 3. "ASF_PROTOCOL_FAULT_3_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 2. "ASF_PROTOCOL_FAULT_2_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 1. "ASF_PROTOCOL_FAULT_1_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 0. "ASF_PROTOCOL_FAULT_0_MASK,Mask register for each ASF protocol fault source." "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_asf_protocol_fault_status,Status register for protocol faults. If a fault occurs the revelant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit" bitfld.long 0x4 16. "ASF_PROTOCOL_FAULT_16_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 15. "ASF_PROTOCOL_FAULT_15_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 14. "ASF_PROTOCOL_FAULT_14_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 13. "ASF_PROTOCOL_FAULT_13_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 12. "ASF_PROTOCOL_FAULT_12_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 11. "ASF_PROTOCOL_FAULT_11_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 10. "ASF_PROTOCOL_FAULT_10_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 9. "ASF_PROTOCOL_FAULT_9_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 8. "ASF_PROTOCOL_FAULT_8_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 7. "ASF_PROTOCOL_FAULT_7_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 6. "ASF_PROTOCOL_FAULT_6_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 5. "ASF_PROTOCOL_FAULT_5_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 4. "ASF_PROTOCOL_FAULT_4_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 3. "ASF_PROTOCOL_FAULT_3_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 2. "ASF_PROTOCOL_FAULT_2_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 1. "ASF_PROTOCOL_FAULT_1_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 0. "ASF_PROTOCOL_FAULT_0_STATUS,Status bits for protocol faults." "0,1" rgroup.long 0xFFC++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2TX_V2_REGS_id_prod_ver,CSI-2 Transmitter Product ID and Version Register." hexmask.long.word 0x0 16.--31. 1. "PRODUCT_ID,CSI-2 Transmitter Product Identification Number." newline hexmask.long.word 0x0 0.--15. 1. "VERSION_ID,CSI-2 Transmitter Product Version Number." tree.end tree.end tree.end tree "CTRL_MMR0_CFG0 (CTRL_MMR0_CFG0)" base ad:0x100000 rgroup.long 0x0++0x3 line.long 0x0 "CFG0_PID,Peripheral release details" hexmask.long.word 0x0 16.--31. 1. "PID_MSB16," newline hexmask.long.byte 0x0 11.--15. 1. "PID_MISC," newline bitfld.long 0x0 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "PID_CUSTOM,Custom revision number - actual value determined by RTL" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR," rgroup.long 0x8++0x3 line.long 0x0 "CFG0_MMR_CFG1,Indicates the MMR configuration" bitfld.long 0x0 31. "MMR_CFG1_PROXY_EN,Proxy addressing enabled" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "MMR_CFG1_PARTITIONS,Indicates present partitions" rgroup.long 0x30++0x3 line.long 0x0 "CFG0_MAIN_DEVSTAT,Indicates SoC bootstrap selection. The default value of this register is determined by the SoC bootstrap pins" hexmask.long.byte 0x0 0.--7. 1. "MAIN_DEVSTAT_BOOTMODE,Specifies the device Primary and Backup boot media." rgroup.long 0x34++0x3 line.long 0x0 "CFG0_MAIN_BOOTCFG,Indicates SoC bootstrap selection latched at power-on reset. The default value of this register is determined by the SoC bootstrap pins." hexmask.long.byte 0x0 0.--7. 1. "MAIN_BOOTCFG_BOOTMODE,Specifies the device Primary and Backup boot media as latched at PORz" rgroup.long 0x40++0x7 line.long 0x0 "CFG0_MAIN_FEATURE_STAT0,Indicates enable status of MAIN domain IP features" bitfld.long 0x0 20. "MAIN_FEATURE_STAT0_EDP0_CRYPTO_DIS,HDCP Cryptography disabled on eDP0" "0,1" newline bitfld.long 0x0 18. "MAIN_FEATURE_STAT0_CRYPTO_PKA_DIS,SA2_UL Crypto Module PKA disabled" "0,1" newline bitfld.long 0x0 17. "MAIN_FEATURE_STAT0_CRYPTO_ENCR_DIS,SA2_UL Crypto Module AES/3DES/DBRG disabled" "0,1" newline bitfld.long 0x0 16. "MAIN_FEATURE_STAT0_CRYPTO_SHA_DIS,SA2_UL Crypto Module SHA/MD5 disabled" "0,1" newline bitfld.long 0x0 9. "MAIN_FEATURE_STAT0_DMPAC_SDE_DIS,DMPAC Stereo Disparity Engine disabled" "0,1" newline bitfld.long 0x0 8. "MAIN_FEATURE_STAT0_DMPAC_DOF_DIS,DMPAC Dense Optical Flow disabled" "0,1" line.long 0x4 "CFG0_MAIN_FEATURE_STAT1,Indicates enable status of MAIN domain IP features" bitfld.long 0x4 19. "MAIN_FEATURE_STAT1_VENDEC_AVC_DEC_EN,Video Codec AVC/H.264 decode function enable" "0,1" newline bitfld.long 0x4 18. "MAIN_FEATURE_STAT1_VENDEC_AVC_ENC_EN,Video Codec AVC/H.264 encode function enable" "0,1" newline bitfld.long 0x4 16. "MAIN_FEATURE_STAT1_MCAN_FD_EN,FD mode is supported on MAIN MCAN interfaces when set" "0,1" newline bitfld.long 0x4 15. "MAIN_FEATURE_STAT1_GPU_ASTC_EN,GPU Adaptive Scalable Texture Compression is supported when set" "0,1" newline bitfld.long 0x4 13. "MAIN_FEATURE_STAT1_VENDEC_HEV_DEC_EN,Video Codec HEVC/H.265 decode function enable" "0,1" newline bitfld.long 0x4 12. "MAIN_FEATURE_STAT1_VENDEC_HEV_ENC_EN,Video Codec HEVC/H.265 encode function enable" "0,1" rgroup.long 0x100++0x7 line.long 0x0 "CFG0_IPC_SET0,Generate interprocessor communication interrupt to C71x core0" hexmask.long 0x0 4.--31. 1. "IPC_SET0_IPC_SRC_SET,Read returns current valueWrite: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0x0 0. "IPC_SET0_IPC_SET,Read returns 0Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0: No effect 1,?" line.long 0x4 "CFG0_IPC_SET1,Generate interprocessor communication interrupt to C71x core1" hexmask.long 0x4 4.--31. 1. "IPC_SET1_IPC_SRC_SET,Read returns current valueWrite: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0x4 0. "IPC_SET1_IPC_SET,Read returns 0Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0: No effect 1,?" rgroup.long 0x120++0x7 line.long 0x0 "CFG0_IPC_SET8,Generate interprocessor communication interrupt to ARM MPU cluster0 core0" hexmask.long 0x0 4.--31. 1. "IPC_SET8_IPC_SRC_SET,Read returns current valueWrite: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0x0 0. "IPC_SET8_IPC_SET,Read returns 0Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0: No effect 1,?" line.long 0x4 "CFG0_IPC_SET9,Generate interprocessor communication interrupt to ARM MPU cluster0 core1" hexmask.long 0x4 4.--31. 1. "IPC_SET9_IPC_SRC_SET,Read returns current valueWrite: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0x4 0. "IPC_SET9_IPC_SET,Read returns 0Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0: No effect 1,?" rgroup.long 0x140++0xF line.long 0x0 "CFG0_IPC_SET16,Generate interprocessor communication interrupt to MAIN R5 cluster0 core0" hexmask.long 0x0 4.--31. 1. "IPC_SET16_IPC_SRC_SET,Read returns current valueWrite: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0x0 0. "IPC_SET16_IPC_SET,Read returns 0Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0: No effect 1,?" line.long 0x4 "CFG0_IPC_SET17,Generate interprocessor communication interrupt to MAIN R5 cluster0 core1" hexmask.long 0x4 4.--31. 1. "IPC_SET17_IPC_SRC_SET,Read returns current valueWrite: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0x4 0. "IPC_SET17_IPC_SET,Read returns 0Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0: No effect 1,?" line.long 0x8 "CFG0_IPC_SET18,Generate interprocessor communication interrupt to MAIN R5 cluster1 core0" hexmask.long 0x8 4.--31. 1. "IPC_SET18_IPC_SRC_SET,Read returns current valueWrite: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0x8 0. "IPC_SET18_IPC_SET,Read returns 0Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0: No effect 1,?" line.long 0xC "CFG0_IPC_SET19,Generate interprocessor communication interrupt to MAIN R5 cluster1 core1" hexmask.long 0xC 4.--31. 1. "IPC_SET19_IPC_SRC_SET,Read returns current valueWrite: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0xC 0. "IPC_SET19_IPC_SET,Read returns 0Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0: No effect 1,?" rgroup.long 0x180++0x7 line.long 0x0 "CFG0_IPC_CLR0,Acknowledge interprocessor communication interrupt to C71x core0" hexmask.long 0x0 4.--31. 1. "IPC_CLR0_IPC_SRC_CLR,Read returns current valueWrite: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0x0 0. "IPC_CLR0_IPC_CLR,Read returns current valueWrite: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0: No effect 1,?" line.long 0x4 "CFG0_IPC_CLR1,Acknowledge interprocessor communication interrupt to C71x core1" hexmask.long 0x4 4.--31. 1. "IPC_CLR1_IPC_SRC_CLR,Read returns current valueWrite: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0x4 0. "IPC_CLR1_IPC_CLR,Read returns current valueWrite: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0: No effect 1,?" rgroup.long 0x1A0++0x7 line.long 0x0 "CFG0_IPC_CLR8,Acknowledge interprocessor communication interrupt to ARM MPU cluster0 core0" hexmask.long 0x0 4.--31. 1. "IPC_CLR8_IPC_SRC_CLR,Read returns current valueWrite: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0x0 0. "IPC_CLR8_IPC_CLR,Read returns current valueWrite: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0: No effect 1,?" line.long 0x4 "CFG0_IPC_CLR9,Acknowledge interprocessor communication interrupt to ARM MPU cluster0 core1" hexmask.long 0x4 4.--31. 1. "IPC_CLR9_IPC_SRC_CLR,Read returns current valueWrite: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0x4 0. "IPC_CLR9_IPC_CLR,Read returns current valueWrite: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0: No effect 1,?" rgroup.long 0x1C0++0xF line.long 0x0 "CFG0_IPC_CLR16,Acknowledge interprocessor communication interrupt to MAIN R5 cluster0 core0" hexmask.long 0x0 4.--31. 1. "IPC_CLR16_IPC_SRC_CLR,Read returns current valueWrite: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0x0 0. "IPC_CLR16_IPC_CLR,Read returns current valueWrite: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0: No effect 1,?" line.long 0x4 "CFG0_IPC_CLR17,Acknowledge interprocessor communication interrupt to MAIN R5 cluster0 core1" hexmask.long 0x4 4.--31. 1. "IPC_CLR17_IPC_SRC_CLR,Read returns current valueWrite: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0x4 0. "IPC_CLR17_IPC_CLR,Read returns current valueWrite: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0: No effect 1,?" line.long 0x8 "CFG0_IPC_CLR18,Acknowledge interprocessor communication interrupt to MAIN R5 cluster1 core0" hexmask.long 0x8 4.--31. 1. "IPC_CLR18_IPC_SRC_CLR,Read returns current valueWrite: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0x8 0. "IPC_CLR18_IPC_CLR,Read returns current valueWrite: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0: No effect 1,?" line.long 0xC "CFG0_IPC_CLR19,Acknowledge interprocessor communication interrupt to MAIN R5 cluster1 core1" hexmask.long 0xC 4.--31. 1. "IPC_CLR19_IPC_SRC_CLR,Read returns current valueWrite: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0xC 0. "IPC_CLR19_IPC_CLR,Read returns current valueWrite: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0: No effect 1,?" rgroup.long 0x210++0x3 line.long 0x0 "CFG0_PCI_DEVICE_ID,PCIe device ID and vendor ID register" hexmask.long.word 0x0 16.--31. 1. "PCI_DEVICE_ID_DEVICE_ID,Product ID defaults to 16'hB013" newline hexmask.long.word 0x0 0.--15. 1. "PCI_DEVICE_ID_VENDOR_ID,TI Vendor ID" rgroup.long 0x220++0x3 line.long 0x0 "CFG0_USB_DEVICE_ID,USB device and vendor ID register" hexmask.long.word 0x0 16.--31. 1. "USB_DEVICE_ID_DEVICE_ID,Product ID defaults to 16'h6168" newline hexmask.long.word 0x0 0.--15. 1. "USB_DEVICE_ID_VENDOR_ID,TI Vendor ID" rgroup.long 0x1008++0x1B line.long 0x0 "CFG0_LOCK0_KICK0,This register must be written with the designated key value followed by a write to LOCK0_KICK1 with its key value before write-protected Partition 0 registers can be written." hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK0_KICK1,This register must be written with the designated key value after a write to LOCK0_KICK0 with its key value before write-protected Partition 0 registers can be written." hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1,- KICK1 component" line.long 0x8 "CFG0_intr_raw_status," bitfld.long 0x8 3. "PROXY_ERR,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 2. "KICK_ERR,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 1. "ADDR_ERR,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0xC "CFG0_intr_enabled_status_clear," bitfld.long 0xC 3. "ENABLED_PROXY_ERR,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 2. "ENABLED_KICK_ERR,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x10 "CFG0_intr_enable," bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0x14 "CFG0_intr_enable_clear," bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x18 "CFG0_eoi,This register should be written with interrupt distribution value required by the device architecture to indicate service completion of the MMR interrupt. This value is not used on this device." hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x1024++0xB line.long 0x0 "CFG0_fault_address," hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault Address." line.long 0x4 "CFG0_fault_type_status," bitfld.long 0x4 6. "FAULT_NS,Non-secure access." "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir.." line.long 0x8 "CFG0_fault_attr_status," hexmask.long.word 0x8 20.--31. 1. "FAULT_XID,XID." newline hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID,Route ID." newline hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID,Privilege ID." rgroup.long 0x1030++0x3 line.long 0x0 "CFG0_fault_clear," bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" rgroup.long 0x1100++0x1B line.long 0x0 "CFG0_CLAIMREG_P0_R0_READONLY," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P0_R0_READONLY,Claim bits for Partition 0" line.long 0x4 "CFG0_CLAIMREG_P0_R1_READONLY," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P0_R1_READONLY,Claim bits for Partition 0" line.long 0x8 "CFG0_CLAIMREG_P0_R2_READONLY," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P0_R2_READONLY,Claim bits for Partition 0" line.long 0xC "CFG0_CLAIMREG_P0_R3_READONLY," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P0_R3_READONLY,Claim bits for Partition 0" line.long 0x10 "CFG0_CLAIMREG_P0_R4_READONLY," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P0_R4_READONLY,Claim bits for Partition 0" line.long 0x14 "CFG0_CLAIMREG_P0_R5_READONLY," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P0_R5_READONLY,Claim bits for Partition 0" line.long 0x18 "CFG0_CLAIMREG_P0_R6_READONLY," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P0_R6_READONLY,Claim bits for Partition 0" rgroup.long 0x2000++0x3 line.long 0x0 "CFG0_PID_PROXY,Peripheral release details" hexmask.long.word 0x0 16.--31. 1. "PID_MSB16_PROXY," newline hexmask.long.byte 0x0 11.--15. 1. "PID_MISC_PROXY," newline bitfld.long 0x0 8.--10. "PID_MAJOR_PROXY," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "PID_CUSTOM_PROXY,Custom revision number - actual value determined by RTL" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR_PROXY," rgroup.long 0x2008++0x3 line.long 0x0 "CFG0_MMR_CFG1_PROXY,Indicates the MMR configuration" bitfld.long 0x0 31. "MMR_CFG1_PROXY_EN_PROXY,Proxy addressing enabled" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "MMR_CFG1_PARTITIONS_PROXY,Indicates present partitions" rgroup.long 0x2030++0x3 line.long 0x0 "CFG0_MAIN_DEVSTAT_PROXY,Indicates SoC bootstrap selection. The default value of this register is determined by the SoC bootstrap pins" hexmask.long.byte 0x0 0.--7. 1. "MAIN_DEVSTAT_BOOTMODE_PROXY,Specifies the device Primary and Backup boot media." rgroup.long 0x2034++0x3 line.long 0x0 "CFG0_MAIN_BOOTCFG_PROXY,Indicates SoC bootstrap selection latched at power-on reset. The default value of this register is determined by the SoC bootstrap pins." hexmask.long.byte 0x0 0.--7. 1. "MAIN_BOOTCFG_BOOTMODE_PROXY,Specifies the device Primary and Backup boot media as latched at PORz" rgroup.long 0x2040++0x7 line.long 0x0 "CFG0_MAIN_FEATURE_STAT0_PROXY,Indicates enable status of MAIN domain IP features" bitfld.long 0x0 20. "MAIN_FEATURE_STAT0_EDP0_CRYPTO_DIS_PROXY,HDCP Cryptography disabled on eDP0" "0,1" newline bitfld.long 0x0 18. "MAIN_FEATURE_STAT0_CRYPTO_PKA_DIS_PROXY,SA2_UL Crypto Module PKA disabled" "0,1" newline bitfld.long 0x0 17. "MAIN_FEATURE_STAT0_CRYPTO_ENCR_DIS_PROXY,SA2_UL Crypto Module AES/3DES/DBRG disabled" "0,1" newline bitfld.long 0x0 16. "MAIN_FEATURE_STAT0_CRYPTO_SHA_DIS_PROXY,SA2_UL Crypto Module SHA/MD5 disabled" "0,1" newline bitfld.long 0x0 9. "MAIN_FEATURE_STAT0_DMPAC_SDE_DIS_PROXY,DMPAC Stereo Disparity Engine disabled" "0,1" newline bitfld.long 0x0 8. "MAIN_FEATURE_STAT0_DMPAC_DOF_DIS_PROXY,DMPAC Dense Optical Flow disabled" "0,1" line.long 0x4 "CFG0_MAIN_FEATURE_STAT1_PROXY,Indicates enable status of MAIN domain IP features" bitfld.long 0x4 19. "MAIN_FEATURE_STAT1_VENDEC_AVC_DEC_EN_PROXY,Video Codec AVC/H.264 decode function enable" "0,1" newline bitfld.long 0x4 18. "MAIN_FEATURE_STAT1_VENDEC_AVC_ENC_EN_PROXY,Video Codec AVC/H.264 encode function enable" "0,1" newline bitfld.long 0x4 16. "MAIN_FEATURE_STAT1_MCAN_FD_EN_PROXY,FD mode is supported on MAIN MCAN interfaces when set" "0,1" newline bitfld.long 0x4 15. "MAIN_FEATURE_STAT1_GPU_ASTC_EN_PROXY,GPU Adaptive Scalable Texture Compression is supported when set" "0,1" newline bitfld.long 0x4 13. "MAIN_FEATURE_STAT1_VENDEC_HEV_DEC_EN_PROXY,Video Codec HEVC/H.265 decode function enable" "0,1" newline bitfld.long 0x4 12. "MAIN_FEATURE_STAT1_VENDEC_HEV_ENC_EN_PROXY,Video Codec HEVC/H.265 encode function enable" "0,1" rgroup.long 0x2100++0x7 line.long 0x0 "CFG0_IPC_SET0_PROXY,Generate interprocessor communication interrupt to C71x core0" hexmask.long 0x0 4.--31. 1. "IPC_SET0_IPC_SRC_SET_PROXY,Read returns current valueWrite: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0x0 0. "IPC_SET0_IPC_SET_PROXY,Read returns 0Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0: No effect 1,?" line.long 0x4 "CFG0_IPC_SET1_PROXY,Generate interprocessor communication interrupt to C71x core1" hexmask.long 0x4 4.--31. 1. "IPC_SET1_IPC_SRC_SET_PROXY,Read returns current valueWrite: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0x4 0. "IPC_SET1_IPC_SET_PROXY,Read returns 0Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0: No effect 1,?" rgroup.long 0x2120++0x7 line.long 0x0 "CFG0_IPC_SET8_PROXY,Generate interprocessor communication interrupt to ARM MPU cluster0 core0" hexmask.long 0x0 4.--31. 1. "IPC_SET8_IPC_SRC_SET_PROXY,Read returns current valueWrite: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0x0 0. "IPC_SET8_IPC_SET_PROXY,Read returns 0Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0: No effect 1,?" line.long 0x4 "CFG0_IPC_SET9_PROXY,Generate interprocessor communication interrupt to ARM MPU cluster0 core1" hexmask.long 0x4 4.--31. 1. "IPC_SET9_IPC_SRC_SET_PROXY,Read returns current valueWrite: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0x4 0. "IPC_SET9_IPC_SET_PROXY,Read returns 0Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0: No effect 1,?" rgroup.long 0x2140++0xF line.long 0x0 "CFG0_IPC_SET16_PROXY,Generate interprocessor communication interrupt to MAIN R5 cluster0 core0" hexmask.long 0x0 4.--31. 1. "IPC_SET16_IPC_SRC_SET_PROXY,Read returns current valueWrite: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0x0 0. "IPC_SET16_IPC_SET_PROXY,Read returns 0Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0: No effect 1,?" line.long 0x4 "CFG0_IPC_SET17_PROXY,Generate interprocessor communication interrupt to MAIN R5 cluster0 core1" hexmask.long 0x4 4.--31. 1. "IPC_SET17_IPC_SRC_SET_PROXY,Read returns current valueWrite: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0x4 0. "IPC_SET17_IPC_SET_PROXY,Read returns 0Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0: No effect 1,?" line.long 0x8 "CFG0_IPC_SET18_PROXY,Generate interprocessor communication interrupt to MAIN R5 cluster1 core0" hexmask.long 0x8 4.--31. 1. "IPC_SET18_IPC_SRC_SET_PROXY,Read returns current valueWrite: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0x8 0. "IPC_SET18_IPC_SET_PROXY,Read returns 0Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0: No effect 1,?" line.long 0xC "CFG0_IPC_SET19_PROXY,Generate interprocessor communication interrupt to MAIN R5 cluster1 core1" hexmask.long 0xC 4.--31. 1. "IPC_SET19_IPC_SRC_SET_PROXY,Read returns current valueWrite: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0xC 0. "IPC_SET19_IPC_SET_PROXY,Read returns 0Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0: No effect 1,?" rgroup.long 0x2180++0x7 line.long 0x0 "CFG0_IPC_CLR0_PROXY,Acknowledge interprocessor communication interrupt to C71x core0" hexmask.long 0x0 4.--31. 1. "IPC_CLR0_IPC_SRC_CLR_PROXY,Read returns current valueWrite: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0x0 0. "IPC_CLR0_IPC_CLR_PROXY,Read returns current valueWrite: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0: No effect 1,?" line.long 0x4 "CFG0_IPC_CLR1_PROXY,Acknowledge interprocessor communication interrupt to C71x core1" hexmask.long 0x4 4.--31. 1. "IPC_CLR1_IPC_SRC_CLR_PROXY,Read returns current valueWrite: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0x4 0. "IPC_CLR1_IPC_CLR_PROXY,Read returns current valueWrite: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0: No effect 1,?" rgroup.long 0x21A0++0x7 line.long 0x0 "CFG0_IPC_CLR8_PROXY,Acknowledge interprocessor communication interrupt to ARM MPU cluster0 core0" hexmask.long 0x0 4.--31. 1. "IPC_CLR8_IPC_SRC_CLR_PROXY,Read returns current valueWrite: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0x0 0. "IPC_CLR8_IPC_CLR_PROXY,Read returns current valueWrite: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0: No effect 1,?" line.long 0x4 "CFG0_IPC_CLR9_PROXY,Acknowledge interprocessor communication interrupt to ARM MPU cluster0 core1" hexmask.long 0x4 4.--31. 1. "IPC_CLR9_IPC_SRC_CLR_PROXY,Read returns current valueWrite: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0x4 0. "IPC_CLR9_IPC_CLR_PROXY,Read returns current valueWrite: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0: No effect 1,?" rgroup.long 0x21C0++0xF line.long 0x0 "CFG0_IPC_CLR16_PROXY,Acknowledge interprocessor communication interrupt to MAIN R5 cluster0 core0" hexmask.long 0x0 4.--31. 1. "IPC_CLR16_IPC_SRC_CLR_PROXY,Read returns current valueWrite: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0x0 0. "IPC_CLR16_IPC_CLR_PROXY,Read returns current valueWrite: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0: No effect 1,?" line.long 0x4 "CFG0_IPC_CLR17_PROXY,Acknowledge interprocessor communication interrupt to MAIN R5 cluster0 core1" hexmask.long 0x4 4.--31. 1. "IPC_CLR17_IPC_SRC_CLR_PROXY,Read returns current valueWrite: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0x4 0. "IPC_CLR17_IPC_CLR_PROXY,Read returns current valueWrite: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0: No effect 1,?" line.long 0x8 "CFG0_IPC_CLR18_PROXY,Acknowledge interprocessor communication interrupt to MAIN R5 cluster1 core0" hexmask.long 0x8 4.--31. 1. "IPC_CLR18_IPC_SRC_CLR_PROXY,Read returns current valueWrite: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0x8 0. "IPC_CLR18_IPC_CLR_PROXY,Read returns current valueWrite: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0: No effect 1,?" line.long 0xC "CFG0_IPC_CLR19_PROXY,Acknowledge interprocessor communication interrupt to MAIN R5 cluster1 core1" hexmask.long 0xC 4.--31. 1. "IPC_CLR19_IPC_SRC_CLR_PROXY,Read returns current valueWrite: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0xC 0. "IPC_CLR19_IPC_CLR_PROXY,Read returns current valueWrite: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0: No effect 1,?" rgroup.long 0x2210++0x3 line.long 0x0 "CFG0_PCI_DEVICE_ID_PROXY,PCIe device ID and vendor ID register" hexmask.long.word 0x0 16.--31. 1. "PCI_DEVICE_ID_DEVICE_ID_PROXY,Product ID defaults to 16'hB013" newline hexmask.long.word 0x0 0.--15. 1. "PCI_DEVICE_ID_VENDOR_ID_PROXY,TI Vendor ID" rgroup.long 0x2220++0x3 line.long 0x0 "CFG0_USB_DEVICE_ID_PROXY,USB device and vendor ID register" hexmask.long.word 0x0 16.--31. 1. "USB_DEVICE_ID_DEVICE_ID_PROXY,Product ID defaults to 16'h6168" newline hexmask.long.word 0x0 0.--15. 1. "USB_DEVICE_ID_VENDOR_ID_PROXY,TI Vendor ID" rgroup.long 0x3008++0x1B line.long 0x0 "CFG0_LOCK0_KICK0_PROXY,This register must be written with the designated key value followed by a write to LOCK0_KICK1 with its key value before write-protected Partition 0 registers can be written." hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK0_KICK1_PROXY,This register must be written with the designated key value after a write to LOCK0_KICK0 with its key value before write-protected Partition 0 registers can be written." hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1_PROXY,- KICK1 component" line.long 0x8 "CFG0_intr_raw_status_PROXY," bitfld.long 0x8 3. "PROXY_ERR_PROXY,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 2. "KICK_ERR_PROXY,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 1. "ADDR_ERR_PROXY,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 0. "PROT_ERR_PROXY,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0xC "CFG0_intr_enabled_status_clear_PROXY," bitfld.long 0xC 3. "ENABLED_PROXY_ERR_PROXY,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 2. "ENABLED_KICK_ERR_PROXY,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 1. "ENABLED_ADDR_ERR_PROXY,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 0. "ENABLED_PROT_ERR_PROXY,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x10 "CFG0_intr_enable_PROXY," bitfld.long 0x10 3. "PROXY_ERR_EN_PROXY,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 2. "KICK_ERR_EN_PROXY,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 1. "ADDR_ERR_EN_PROXY,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 0. "PROT_ERR_EN_PROXY,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0x14 "CFG0_intr_enable_clear_PROXY," bitfld.long 0x14 3. "PROXY_ERR_EN_CLR_PROXY,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 2. "KICK_ERR_EN_CLR_PROXY,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 1. "ADDR_ERR_EN_CLR_PROXY,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 0. "PROT_ERR_EN_CLR_PROXY,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x18 "CFG0_eoi_PROXY,This register should be written with interrupt distribution value required by the device architecture to indicate service completion of the MMR interrupt. This value is not used on this device." hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR_PROXY,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x3024++0xB line.long 0x0 "CFG0_fault_address_PROXY," hexmask.long 0x0 0.--31. 1. "FAULT_ADDR_PROXY,Fault Address." line.long 0x4 "CFG0_fault_type_status_PROXY," bitfld.long 0x4 6. "FAULT_NS_PROXY,Non-secure access." "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE_PROXY,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv =.." line.long 0x8 "CFG0_fault_attr_status_PROXY," hexmask.long.word 0x8 20.--31. 1. "FAULT_XID_PROXY,XID." newline hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID_PROXY,Route ID." newline hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID_PROXY,Privilege ID." rgroup.long 0x3030++0x3 line.long 0x0 "CFG0_fault_clear_PROXY," bitfld.long 0x0 0. "FAULT_CLR_PROXY,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" rgroup.long 0x3100++0x1B line.long 0x0 "CFG0_CLAIMREG_P0_R0," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P0_R0,Claim bits for Partition 0" line.long 0x4 "CFG0_CLAIMREG_P0_R1," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P0_R1,Claim bits for Partition 0" line.long 0x8 "CFG0_CLAIMREG_P0_R2," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P0_R2,Claim bits for Partition 0" line.long 0xC "CFG0_CLAIMREG_P0_R3," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P0_R3,Claim bits for Partition 0" line.long 0x10 "CFG0_CLAIMREG_P0_R4," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P0_R4,Claim bits for Partition 0" line.long 0x14 "CFG0_CLAIMREG_P0_R5," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P0_R5,Claim bits for Partition 0" line.long 0x18 "CFG0_CLAIMREG_P0_R6," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P0_R6,Claim bits for Partition 0" rgroup.long 0x4000++0x3 line.long 0x0 "CFG0_USB0_CTRL,Controls USB0 operation" bitfld.long 0x0 27. "USB0_CTRL_SERDES_SEL,Serdes Selection.The USB3_0 interface can be mapped to 2 different SERDES lanes. This bit selects which SERDES drives the USB3 PIPE interface input clock data and control signals. Programming should align with the.." "0: SERDES0 Ln3 drives USB3_0 inputs 1,?" rgroup.long 0x4008++0x3 line.long 0x0 "CFG0_USB0_PHY_CTRL,Configures the USB0 Phy operation" bitfld.long 0x0 31. "USB0_PHY_CTRL_CORE_VOLTAGE,Selects the USB PHY core voltage 0 - Core voltage is 0.85 V 1 - Core voltage is 0.80 V" "0: Core voltage is 0,1: Core voltage is 0" rgroup.long 0x4034++0x3 line.long 0x0 "CFG0_CPSW2_ENET1_CTRL,Controls MAIN CPSW_2G Ethernet Port1 operation" bitfld.long 0x0 4. "CPSW2_ENET1_CTRL_RGMII_ID_MODE,Port 1 RGMII internal transmit delay selection 0 - Internal transmit delay 1 - No internal transmit delay" "0: Internal transmit delay 1,?" newline bitfld.long 0x0 0.--1. "CPSW2_ENET1_CTRL_MODE_SEL,Selects Ethernet switch Port1 interface Field values (Others are reserved): 2'b00 - GMII/MII (not supported) 2'b01 - RMII 2'b10 - RGMII 2'b11 - SGMII (not supported)" "0: GMII/MII,1: RMII 2'b10,?,3: SGMII" rgroup.long 0x4074++0x3 line.long 0x0 "CFG0_PCIE1_CTRL,Controls PCIe1 operation" bitfld.long 0x0 8.--9. "PCIE1_CTRL_LANE_COUNT,Configures the PCIe lane count 00 - Select 1-lane operation 01 - Select 2-lane operation 1x - Select 4-lane operation" "0: Select 1-lane operation 01,?,2: lane operation 1x,?" newline bitfld.long 0x0 7. "PCIE1_CTRL_MODE_SEL,Selects the operating mode 0 - Endpoint 1 - Root Complex" "0: Endpoint 1,?" newline bitfld.long 0x0 0.--1. "PCIE1_CTRL_GENERATION_SEL,Configures the PCIe generation support in the PCIe capabilities linked-list Field values (Others are reserved): 2'b01 - Gen2 - Controller advertises Gen1 & Gen2 capability and link operates at either speed 2'b10 - Gen3.." "?,1: Gen2,2: Gen3,3: Reserved" rgroup.long 0x4080++0xF line.long 0x0 "CFG0_SERDES0_LN0_CTRL,Controls SERDES0 lane0 selection" bitfld.long 0x0 0.--1. "SERDES0_LN0_CTRL_LANE_FUNC_SEL,Selects the SERDES0 lane0 function Field values (Others are reserved): 2'b00 - IP1 - eDP0 Lane 0 2'b01 - IP2 - PCIe1 Lane 0 2'b10 - IP3 - Not used 2'b11 - IP4 - Hyperlink (VUSR) Lane 0" "0: IP1,1: IP2,2: IP3,3: IP4" line.long 0x4 "CFG0_SERDES0_LN1_CTRL,Controls SERDES0 lane1 selection" bitfld.long 0x4 0.--1. "SERDES0_LN1_CTRL_LANE_FUNC_SEL,Selects the SERDES0 lane1 function Field values (Others are reserved): 2'b00 - IP1 - eDP0 Lane 1 2'b01 - IP2 - PCIe1 Lane 1 2'b10 - IP3 - USB3_0 2'b11 - IP4 - Hyperlink (VUSR) Lane 1" "0: IP1,1: IP2,2: IP3,3: IP4" line.long 0x8 "CFG0_SERDES0_LN2_CTRL,Controls SERDES0 lane2 selection" bitfld.long 0x8 0.--1. "SERDES0_LN2_CTRL_LANE_FUNC_SEL,Selects the SERDES0 lane2 function Field values (Others are reserved): 2'b00 - IP1 - eDP0 Lane 2/0 2'b01 - IP2 - PCIe1 Lane 2 2'b10 - IP3 - Not Used 2'b11 - Ip4 - Hyperlink (VUSR) Lane 2" "0: IP1,1: IP2,2: IP3,3: Ip4" line.long 0xC "CFG0_SERDES0_LN3_CTRL,Controls SERDES0 lane3 selection" bitfld.long 0xC 0.--1. "SERDES0_LN3_CTRL_LANE_FUNC_SEL,Selects the SERDES0 lane3 function Field values (Others are reserved): 2'b00 - IP1 - eDP0 Lane 3/1 2'b01 - IP2 - PCIe1 Lane 3 2'b10 - IP3 - USB3_0 2'b11 - IP4 - Hyperlink (VUSR) Lane 3" "0: IP1,1: IP2,2: IP3,3: IP4" rgroup.long 0x40E0++0x3 line.long 0x0 "CFG0_SERDES0_CTRL,Controls SERDES0 operation" bitfld.long 0x0 8. "SERDES0_CTRL_RET_EN,Retention enable" "0,1" rgroup.long 0x4140++0x17 line.long 0x0 "CFG0_EPWM0_CTRL,Controls ePWM0 Operation" bitfld.long 0x0 4. "EPWM0_CTRL_EALLOW,Enable write access to ePWM tripzone and HRPWM config registers 0 - Disabled 1 - Enabled" "0: Disabled 1,?" newline bitfld.long 0x0 0. "EPWM0_CTRL_TB_CLKEN,Enable ePWM timebase clock 0 - Disabled 1 - EnabledThis bit is OR'd with SUP_CTRL7_pwm0_tb_clken. Setting the tb_clken in either register will start the timebase counter." "0: Disabled 1,?" line.long 0x4 "CFG0_EPWM1_CTRL,Controls ePWM1 Operation" bitfld.long 0x4 4. "EPWM1_CTRL_EALLOW,Enable write access to ePWM tripzone and HRPWM config registers 0 - Disabled 1 - Enabled" "0: Disabled 1,?" newline bitfld.long 0x4 0. "EPWM1_CTRL_TB_CLKEN,Enable ePWM timebase clock 0 - Disabled 1 - EnabledThis bit is OR'd with SUP_CTRL7_pwm1_tb_clken. Setting the tb_clken in either register will start the timebase counter." "0: Disabled 1,?" line.long 0x8 "CFG0_EPWM2_CTRL,Controls ePWM2 Operation" bitfld.long 0x8 4. "EPWM2_CTRL_EALLOW,Enable write access to ePWM tripzone and HRPWM config registers 0 - Disabled 1 - Enabled" "0: Disabled 1,?" newline bitfld.long 0x8 0. "EPWM2_CTRL_TB_CLKEN,Enable ePWM timebase clock 0 - Disabled 1 - EnabledThis bit is OR'd with SUP_CTRL7_pwm2_tb_clken. Setting the tb_clken in either register will start the timebase counter." "0: Disabled 1,?" line.long 0xC "CFG0_EPWM3_CTRL,Controls ePWM3 Operation" bitfld.long 0xC 8.--10. "EPWM3_CTRL_SYNCIN_SEL,Selects the source of the PWM3 synchronization input Field values (Others are reserved): 3'b000 - PWM3_SYNCIN Pin 3'b001 - PWM2 syncout signal daisy chained 3'b010 - None 3'b011 - None 3'b100 - None 3'b101 -.." "0: PWM3_SYNCIN Pin 3'b001,?,2: None 3'b011,?,4: None 3'b101,?,6: None 3'b111,?" newline bitfld.long 0xC 4. "EPWM3_CTRL_EALLOW,Enable write access to ePWM tripzone and HRPWM config registers 0 - Disabled 1 - Enabled" "0: Disabled 1,?" newline bitfld.long 0xC 0. "EPWM3_CTRL_TB_CLKEN,Enable ePWM timebase clock 0 - Disabled 1 - EnabledThis bit is OR'd with SUP_CTRL7_pwm3_tb_clken. Setting the tb_clken in either register will start the timebase counter." "0: Disabled 1,?" line.long 0x10 "CFG0_EPWM4_CTRL,Controls ePWM4 Operation" bitfld.long 0x10 4. "EPWM4_CTRL_EALLOW,Enable write access to ePWM tripzone and HRPWM config registers 0 - Disabled 1 - Enabled" "0: Disabled 1,?" newline bitfld.long 0x10 0. "EPWM4_CTRL_TB_CLKEN,Enable ePWM timebase clock 0 - Disabled 1 - EnabledThis bit is OR'd with SUP_CTRL7_pwm4_tb_clken. Setting the tb_clken in either register will start the timebase counter." "0: Disabled 1,?" line.long 0x14 "CFG0_EPWM5_CTRL,Controls ePWM5 Operation" bitfld.long 0x14 4. "EPWM5_CTRL_EALLOW,Enable write access to ePWM tripzone and HRPWM config registers 0 - Disabled 1 - Enabled" "0: Disabled 1,?" newline bitfld.long 0x14 0. "EPWM5_CTRL_TB_CLKEN,Enable ePWM timebase clock 0 - Disabled 1 - EnabledThis bit is OR'd with SUP_CTRL7_pwm5_tb_clken. Setting the tb_clken in either register will start the timebase counter." "0: Disabled 1,?" rgroup.long 0x4160++0x7 line.long 0x0 "CFG0_SOCA_SEL,Selects Start of Conversion A output signal source. Each ePWM provides a SOCA event that can be used to trigger external ADCs. All ePWM SOCA events are ORed together allowing any of the 6 ePWMs to generate the event (if enabled within the.." bitfld.long 0x0 0.--1. "SOCA_SEL_SOCA_SEL,Selects the SOC A output source Field values (Others are reserved): 2'b00 - OR of all eHRPWM SOCA outputs 2'b01 - None 2'b10 - None 2'b11 - None" "0: OR of all eHRPWM SOCA outputs 2'b01,?,2: None 2'b11,?" line.long 0x4 "CFG0_SOCB_SEL,Selects Start of Conversion B output signal source.. Each ePWM provides a SOCB event that can be used to trigger external ADCs. All ePWM SOCB events are ORed together allowing any of the 6 ePWMs to generate the event (if enabled within the.." bitfld.long 0x4 0.--1. "SOCB_SEL_SOCB_SEL,Selects the SOC B output source Field values (Others are reserved): 2'b00 - OR of all eHRPWM SOCB ouputs 2'b01 - None 2'b10 - None 2'b11 - None" "0: OR of all eHRPWM SOCB ouputs 2'b01,?,2: None 2'b11,?" rgroup.long 0x41A0++0x3 line.long 0x0 "CFG0_EQEP_STAT,Displays status of EQEP modules" bitfld.long 0x0 2. "EQEP_STAT_PHASE_ERR2,eQEP2 Phase error status 0 - No error 1 - Phase error occurred" "0: No error 1,?" newline bitfld.long 0x0 1. "EQEP_STAT_PHASE_ERR1,eQEP1 Phase error status 0 - No error 1 - Phase error occurred" "0: No error 1,?" newline bitfld.long 0x0 0. "EQEP_STAT_PHASE_ERR0,eQEP0 Phase error status 0 - No error 1 - Phase error occurred" "0: No error 1,?" rgroup.long 0x41B4++0x3 line.long 0x0 "CFG0_SDIO1_CTRL,Controls drive strength of MMC1 SDIO mode pins" hexmask.long.byte 0x0 0.--4. 1. "SDIO1_CTRL_DRV_STR,Selects the SDIO drive strength" rgroup.long 0x4200++0x4F line.long 0x0 "CFG0_TIMER0_CTRL,Controls TIMER0 operation" bitfld.long 0x0 0.--2. "TIMER0_CTRL_CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER0 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x4 "CFG0_TIMER1_CTRL,Controls TIMER1 operation" bitfld.long 0x4 8. "TIMER1_CTRL_CASCADE_EN,Enables cascading of TIMER1 to TIMER0" "0,1" newline bitfld.long 0x4 0.--2. "TIMER1_CTRL_CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER1 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x8 "CFG0_TIMER2_CTRL,Controls TIMER2 operation" bitfld.long 0x8 0.--2. "TIMER2_CTRL_CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER2 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0xC "CFG0_TIMER3_CTRL,Controls TIMER3 operation" bitfld.long 0xC 8. "TIMER3_CTRL_CASCADE_EN,Enables cascading of TIMER3 to TIMER2" "0,1" newline bitfld.long 0xC 0.--2. "TIMER3_CTRL_CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER3 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x10 "CFG0_TIMER4_CTRL,Controls TIMER4 operation" bitfld.long 0x10 0.--2. "TIMER4_CTRL_CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER4 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x14 "CFG0_TIMER5_CTRL,Controls TIMER5 operation" bitfld.long 0x14 8. "TIMER5_CTRL_CASCADE_EN,Enables cascading of TIMER5 to TIMER4" "0,1" newline bitfld.long 0x14 0.--2. "TIMER5_CTRL_CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER5 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x18 "CFG0_TIMER6_CTRL,Controls TIMER6 operation" bitfld.long 0x18 0.--2. "TIMER6_CTRL_CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER6 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x1C "CFG0_TIMER7_CTRL,Controls TIMER7 operation" bitfld.long 0x1C 8. "TIMER7_CTRL_CASCADE_EN,Enables cascading of TIMER7 to TIMER6" "0,1" newline bitfld.long 0x1C 0.--2. "TIMER7_CTRL_CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER7 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x20 "CFG0_TIMER8_CTRL,Controls TIMER8 operation" bitfld.long 0x20 0.--2. "TIMER8_CTRL_CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER8 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x24 "CFG0_TIMER9_CTRL,Controls TIMER9 operation" bitfld.long 0x24 8. "TIMER9_CTRL_CASCADE_EN,Enables cascading of TIMER9 to TIMER8" "0,1" newline bitfld.long 0x24 0.--2. "TIMER9_CTRL_CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER9 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x28 "CFG0_TIMER10_CTRL,Controls TIMER10 operation" bitfld.long 0x28 0.--2. "TIMER10_CTRL_CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER10 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x2C "CFG0_TIMER11_CTRL,Controls TIMER11 operation" bitfld.long 0x2C 8. "TIMER11_CTRL_CASCADE_EN,Enables cascading of TIMER11 to TIMER10" "0,1" newline bitfld.long 0x2C 0.--2. "TIMER11_CTRL_CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER11 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x30 "CFG0_TIMER12_CTRL,Controls TIMER12 operation" bitfld.long 0x30 0.--2. "TIMER12_CTRL_CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER12 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x34 "CFG0_TIMER13_CTRL,Controls TIMER13 operation" bitfld.long 0x34 8. "TIMER13_CTRL_CASCADE_EN,Enables cascading of TIMER13 to TIMER12" "0,1" newline bitfld.long 0x34 0.--2. "TIMER13_CTRL_CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER13 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x38 "CFG0_TIMER14_CTRL,Controls TIMER14 operation" bitfld.long 0x38 0.--2. "TIMER14_CTRL_CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER14 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x3C "CFG0_TIMER15_CTRL,Controls TIMER15 operation" bitfld.long 0x3C 8. "TIMER15_CTRL_CASCADE_EN,Enables cascading of TIMER15 to TIMER14" "0,1" newline bitfld.long 0x3C 0.--2. "TIMER15_CTRL_CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER15 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x40 "CFG0_TIMER16_CTRL,Controls TIMER16 operation" bitfld.long 0x40 0.--2. "TIMER16_CTRL_CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER16 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x44 "CFG0_TIMER17_CTRL,Controls TIMER17 operation" bitfld.long 0x44 8. "TIMER17_CTRL_CASCADE_EN,Enables cascading of TIMER17 to TIMER16" "0,1" newline bitfld.long 0x44 0.--2. "TIMER17_CTRL_CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER17 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x48 "CFG0_TIMER18_CTRL,Controls TIMER18 operation" bitfld.long 0x48 0.--2. "TIMER18_CTRL_CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER18 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x4C "CFG0_TIMER19_CTRL,Controls TIMER19 operation" bitfld.long 0x4C 8. "TIMER19_CTRL_CASCADE_EN,Enables cascading of TIMER19 to TIMER18" "0,1" newline bitfld.long 0x4C 0.--2. "TIMER19_CTRL_CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER19 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" rgroup.long 0x4280++0x1F line.long 0x0 "CFG0_TIMERIO0_CTRL,Controls Timer IO muxing" hexmask.long.byte 0x0 0.--4. 1. "TIMERIO0_CTRL_OUT_SEL,Selects the source of the TIMERIO0 output Field values (Others are reserved): 5'b00000 - TIMERIO0 is driven by TIMER0 output 5'b00001 - TIMERIO0 is driven by TIMER1 output 5'b00010 - TIMERIO0 is driven by TIMER2 output.." line.long 0x4 "CFG0_TIMERIO1_CTRL,Controls Timer IO muxing" hexmask.long.byte 0x4 0.--4. 1. "TIMERIO1_CTRL_OUT_SEL,Selects the source of the TIMERIO1 output Field values (Others are reserved): 5'b00000 - TIMERIO1 is driven by TIMER0 output 5'b00001 - TIMERIO1 is driven by TIMER1 output 5'b00010 - TIMERIO1 is driven by TIMER2 output.." line.long 0x8 "CFG0_TIMERIO2_CTRL,Controls Timer IO muxing" hexmask.long.byte 0x8 0.--4. 1. "TIMERIO2_CTRL_OUT_SEL,Selects the source of the TIMERIO2 output Field values (Others are reserved): 5'b00000 - TIMERIO2 is driven by TIMER0 output 5'b00001 - TIMERIO2 is driven by TIMER1 output 5'b00010 - TIMERIO2 is driven by TIMER2 output.." line.long 0xC "CFG0_TIMERIO3_CTRL,Controls Timer IO muxing" hexmask.long.byte 0xC 0.--4. 1. "TIMERIO3_CTRL_OUT_SEL,Selects the source of the TIMERIO3 output Field values (Others are reserved): 5'b00000 - TIMERIO3 is driven by TIMER0 output 5'b00001 - TIMERIO3 is driven by TIMER1 output 5'b00010 - TIMERIO3 is driven by TIMER2 output.." line.long 0x10 "CFG0_TIMERIO4_CTRL,Controls Timer IO muxing" hexmask.long.byte 0x10 0.--4. 1. "TIMERIO4_CTRL_OUT_SEL,Selects the source of the TIMERIO4 output Field values (Others are reserved): 5'b00000 - TIMERIO4 is driven by TIMER0 output 5'b00001 - TIMERIO4 is driven by TIMER1 output 5'b00010 - TIMERIO4 is driven by TIMER2 output.." line.long 0x14 "CFG0_TIMERIO5_CTRL,Controls Timer IO muxing" hexmask.long.byte 0x14 0.--4. 1. "TIMERIO5_CTRL_OUT_SEL,Selects the source of the TIMERIO5 output Field values (Others are reserved): 5'b00000 - TIMERIO5 is driven by TIMER0 output 5'b00001 - TIMERIO5 is driven by TIMER1 output 5'b00010 - TIMERIO5 is driven by TIMER2 output.." line.long 0x18 "CFG0_TIMERIO6_CTRL,Controls Timer IO muxing" hexmask.long.byte 0x18 0.--4. 1. "TIMERIO6_CTRL_OUT_SEL,Selects the source of the TIMERIO6 output Field values (Others are reserved): 5'b00000 - TIMERIO6 is driven by TIMER0 output 5'b00001 - TIMERIO6 is driven by TIMER1 output 5'b00010 - TIMERIO6 is driven by TIMER2 output.." line.long 0x1C "CFG0_TIMERIO7_CTRL,Controls Timer IO muxing" hexmask.long.byte 0x1C 0.--4. 1. "TIMERIO7_CTRL_OUT_SEL,Selects the source of the TIMERIO7 output Field values (Others are reserved): 5'b00000 - TIMERIO7 is driven by TIMER0 output 5'b00001 - TIMERIO7 is driven by TIMER1 output 5'b00010 - TIMERIO7 is driven by TIMER2 output.." rgroup.long 0x42E0++0x3 line.long 0x0 "CFG0_I2C0_CTRL,Controls I2C0 operation for open drain I/Os" bitfld.long 0x0 0. "I2C0_CTRL_HS_MCS_EN,HS Mode master current source enable.When set enables the current-source pull-up on the SCL output. Only one master on the I2C bus should enable SCL current sourcing." "0,1" rgroup.long 0x4300++0x7 line.long 0x0 "CFG0_DPHY_TX0_CTRL,Controls DPHY_TX0 operation" bitfld.long 0x0 0.--1. "DPHY_TX0_CTRL_LANE_FUNC_SEL,Selects the source for the 4 lanes of DPHY_TX 0 Field values (Others are reserved): 2'b00 - IP1 (DSI_0 PPI0) 2'b01 - IP2 (CSI-TX0)" "0: IP1,1: IP2,?,?" line.long 0x4 "CFG0_DPHY_TX1_CTRL,Controls DPHY_TX1 operation" bitfld.long 0x4 0.--1. "DPHY_TX1_CTRL_LANE_FUNC_SEL,Selects the source for the 4 lanes of DPHY_TX 1 Field values (Others are reserved): 2'b00 - IP1 (DSI_1 PPI0) 2'b01 - IP2 (CSI-TX1)" "0: IP1,1: IP2,?,?" rgroup.long 0x4310++0x3 line.long 0x0 "CFG0_EDP0_CTRL,Controls eDP0 operation" bitfld.long 0x0 28. "EDP0_CTRL_SERDES_SEL,Serdes Selection.In 1-Lane or 2-Lane mode the eDP0 Lane 0/1 interface can be mapped to 2 different SerDes lanes. This bit selects which SerDes lane drives the eDP0 Lane 0/1 interface input clock data and control signals and.." "0: eDP0 Lane 0/1 map to Serdes0 Lane 0/1 and eDP..,1: eDP0 Lane 0/1 map to Serdes0 Lane 2/3" newline bitfld.long 0x0 8. "EDP0_CTRL_RESET_ISO,Reset isolationWhen set enables reset isolation of eDP PHY" "0,1" rgroup.long 0x4320++0x3 line.long 0x0 "CFG0_VPAC0_CAL0_CTRL,Controls VPAC0 Camera Adaptive Layer 0 interface operation" bitfld.long 0x0 0.--1. "VPAC0_CAL0_CTRL_CAL_SEL,Selects the CSI_RX source for the VPAC CAL0 input Field values (Others are reserved): 2'b00 - CSI-RX 0 2'b01 - CSI-RX 1 2'b10 - Reserved 2'b11 - Reserved" "0: CSI-RX 0 2'b01,?,2: Reserved 2'b11,?" rgroup.long 0x43F0++0x3 line.long 0x0 "CFG0_CSI_RX_LOOPBACK,Controls loopback of CSI-RX inputs to CSI-TX inputs for diagnostics." bitfld.long 0x0 2.--3. "CSI_RX_LOOPBACK_CSITX1_LB_SEL,Selects the CSI-RX loopback source for CSI-TX1 Field values (Others are reserved): 2'b00 - CSI-RX 0 2'b01 - CSI-RX 1 2'b10 - Reserved 2'b11 - Reserved" "0: CSI-RX 0 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 0.--1. "CSI_RX_LOOPBACK_CSITX0_LB_SEL,Selects the CSI-RX loopback source for CSI-TX0. Field values (Others are reserved): 2'b00 - CSI-RX 0 2'b01 - CSI-RX 1 2'b10 - Reserved 2'b11 - Reserved" "0: CSI-RX 0 2'b01,?,2: Reserved 2'b11,?" rgroup.long 0x4500++0x3 line.long 0x0 "CFG0_GPU0_GP_IN_REQ,Generates GPIO input event to GPU0" bitfld.long 0x0 15. "GPU0_GP_IN_REQ_REQ,Input request. This bit is set to generate a GPIO request to the GPU to read the requestor data input. This bit should be cleared by the requestor after the GPU has acknowledged the request." "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "GPU0_GP_IN_REQ_DATA,GPIO requestor data input to the GPU" rgroup.long 0x4504++0x7 line.long 0x0 "CFG0_GPU0_GP_IN_ACK,Acknowledge for GPIO input event from GPU0" bitfld.long 0x0 15. "GPU0_GP_IN_ACK_ACK,Input acknowledge. The GPU will set this bit to acknowledge a GPIO input request. This will generate a gpu_gpio_ack interrupt which will be cleared when the requestor clears the req bit in the GPU_GP_IN_REQ register." "0,1" line.long 0x4 "CFG0_GPU0_GP_OUT_REQ,Generates GPIO output event from GPU0" bitfld.long 0x4 15. "GPU0_GP_OUT_REQ_REQ,Output request. This bit is set to generate a GPIO request from the GPU to read the requestor data output. This will generate a gpu_gpio_req interrupt which will be cleared when the receiver clears the ack bit in the.." "0,1" newline hexmask.long.byte 0x4 0.--7. 1. "GPU0_GP_OUT_REQ_DATA,GPIO requestor data output from the GPU" rgroup.long 0x450C++0x3 line.long 0x0 "CFG0_GPU0_GP_OUT_ACK,Acknowledge for GPIO output event to GPU0" bitfld.long 0x0 15. "GPU0_GP_OUT_ACK_ACK,Output acknowledge. The receiver of the gpu_gpio_req interrupt will set this bit to acknowledge the GPIO output request. This bit is cleared when the GPU deasserts its gpio_output_req signal." "0,1" rgroup.long 0x4520++0x3 line.long 0x0 "CFG0_VUSR_CTRL,Controls operation of the dual VUSR (Hyperlink) module" bitfld.long 0x0 16. "VUSR_CTRL_DUAL_VUSR_EN,Selects single or dual VUSR interface operation 0 - Single VUSR interface (VUSR0) enabled 1 - Dual VUSR interface (VUSR0 & VUSR1) enabled" "0: Single VUSR interface,1: Dual VUSR interface" newline bitfld.long 0x0 8. "VUSR_CTRL_V1_K3_MODE,VUSR1 interface operational mode 0 - Legacy (KS2) addressing/interface mode 1 - Enhanced (KS3) addressing/interface mode" "0: Legacy,1: Enhanced" newline bitfld.long 0x0 0. "VUSR_CTRL_V0_K3_MODE,VUSR0 interface operational mode 0 - Legacy (KS2) addressing/interface mode 1 - Enhanced (KS3) addressing/interface mode" "0: Legacy,1: Enhanced" rgroup.long 0x4584++0xF line.long 0x0 "CFG0_MCASP1_CTRL,Controls McASP1 operation" bitfld.long 0x0 23. "MCASP1_CTRL_AXR15_EN,Enable AXR15 receive data. 0 - AXR15 input driven 1'b0 1 - AXR15 input driven by AFSR/X input selected by axr15_src value" "0: AXR15 input driven 1'b0 1,?" newline hexmask.long.byte 0x0 16.--19. 1. "MCASP1_CTRL_AXR15_SRC,Selects one of the AFSX or AFSR inputs as the AXR15 data input Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX 4'b0100 - McASP2_AFSR.." newline bitfld.long 0x0 7. "MCASP1_CTRL_AXR14_EN,Enable AXR14 receive data. 0 - AXR14 input driven 1'b0 1 - AXR14 input driven by AFSR/X input selected by axr14_src value" "0: AXR14 input driven 1'b0 1,?" newline hexmask.long.byte 0x0 0.--3. 1. "MCASP1_CTRL_AXR14_SRC,Selects one of the AFSX or AFSR inputs as the AXR14 data input Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX 4'b0100 - McASP2_AFSR.." line.long 0x4 "CFG0_MCASP2_CTRL,Controls McASP2 operation" bitfld.long 0x4 23. "MCASP2_CTRL_AXR15_EN,Enable AXR15 receive data. 0 - AXR15 input driven 1'b0 1 - AXR15 input driven by AFSR/X input selected by axr15_src value" "0: AXR15 input driven 1'b0 1,?" newline hexmask.long.byte 0x4 16.--19. 1. "MCASP2_CTRL_AXR15_SRC,Selects one of the AFSX or AFSR inputs as the AXR15 data input Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX 4'b0100 - McASP2_AFSR.." newline bitfld.long 0x4 7. "MCASP2_CTRL_AXR14_EN,Enable AXR14 receive data. 0 - AXR14 input driven 1'b0 1 - AXR14 input driven by AFSR/X input selected by axr14_src value" "0: AXR14 input driven 1'b0 1,?" newline hexmask.long.byte 0x4 0.--3. 1. "MCASP2_CTRL_AXR14_SRC,Selects one of the AFSX or AFSR inputs as the AXR14 data input Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX 4'b0100 - McASP2_AFSR.." line.long 0x8 "CFG0_MCASP3_CTRL,Controls McASP3 operation" bitfld.long 0x8 23. "MCASP3_CTRL_AXR15_EN,Enable AXR15 receive data. 0 - AXR15 input driven 1'b0 1 - AXR15 input driven by AFSR/X input selected by axr15_src value" "0: AXR15 input driven 1'b0 1,?" newline hexmask.long.byte 0x8 16.--19. 1. "MCASP3_CTRL_AXR15_SRC,Selects one of the AFSX or AFSR inputs as the AXR15 data input Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX 4'b0100 - McASP2_AFSR.." newline bitfld.long 0x8 7. "MCASP3_CTRL_AXR14_EN,Enable AXR14 receive data. 0 - AXR14 input driven 1'b0 1 - AXR14 input driven by AFSR/X input selected by axr14_src value" "0: AXR14 input driven 1'b0 1,?" newline hexmask.long.byte 0x8 0.--3. 1. "MCASP3_CTRL_AXR14_SRC,Selects one of the AFSX or AFSR inputs as the AXR14 data input Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX 4'b0100 - McASP2_AFSR.." line.long 0xC "CFG0_MCASP4_CTRL,Controls McASP4 operation" bitfld.long 0xC 23. "MCASP4_CTRL_AXR15_EN,Enable AXR15 receive data. 0 - AXR15 input driven 1'b0 1 - AXR15 input driven by AFSR/X input selected by axr15_src value" "0: AXR15 input driven 1'b0 1,?" newline hexmask.long.byte 0xC 16.--19. 1. "MCASP4_CTRL_AXR15_SRC,Selects one of the AFSX or AFSR inputs as the AXR15 data input Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX 4'b0100 - McASP2_AFSR.." newline bitfld.long 0xC 7. "MCASP4_CTRL_AXR14_EN,Enable AXR14 receive data. 0 - AXR14 input driven 1'b0 1 - AXR14 input driven by AFSR/X input selected by axr14_src value" "0: AXR14 input driven 1'b0 1,?" newline hexmask.long.byte 0xC 0.--3. 1. "MCASP4_CTRL_AXR14_SRC,Selects one of the AFSX or AFSR inputs as the AXR14 data input Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX 4'b0100 - McASP2_AFSR.." rgroup.long 0x45B0++0x3 line.long 0x0 "CFG0_GPU0_CFG,Configures GPU core operation" hexmask.long.byte 0x0 8.--11. 1. "GPU0_CFG_GPU_COUNT,Indicates number of GPU core used in multi-core operation. Should be set to 1 for GPU0 operation as independent GPU." newline bitfld.long 0x0 0.--2. "GPU0_CFG_GPU_ID,GPU Multi-core core identificationShould always be set as 0 for GPU0" "0,1,2,3,4,5,6,7" rgroup.long 0x45C0++0x3 line.long 0x0 "CFG0_GPU0_PWR_REQ,Indicates GPU0 power control interface requests" bitfld.long 0x0 16. "GPU0_PWR_REQ_REQ,Power control request. This bit is set by the GPU to request a Power Management event to the PM processor. This will generate a gpu0_pwr_req interrupt. The interrupt is cleared only when the GPU clears its pwrctrl_gpu_req output." "0,1" newline bitfld.long 0x0 12. "GPU0_PWR_REQ_TYPE,GPU request type. 0 - Power Down request 1 - Power Up request" "0: Power Down request 1,?" newline bitfld.long 0x0 8.--10. "GPU0_PWR_REQ_DOMAIN,GPU request mask. Indicates GPU domain to which the power event applies. For mapping refer to GPU RGX_CR_POWER_EVENT register." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "GPU0_PWR_REQ_GPU_MASK,GPU request mask. One bit per GPU indicating to which GPUs the power event applies. Mask bits are indexed by GPU_ID" rgroup.long 0x45C4++0x3 line.long 0x0 "CFG0_GPU0_PWR_ACK,Controls GPU0 power control interface request acknowledgement" bitfld.long 0x0 16. "GPU0_PWR_ACK_ABORT,Power control abort. This bit is set by the PM processor to that the GPU power control request could not be completed. The bit is cleared to 0 when gpu0_pwr_req goes low." "0,1" newline bitfld.long 0x0 0. "GPU0_PWR_ACK_COMPLETE,Power control complete. This bit is set by the PM processor to indicate sucessful completion of the GPU power control request. The bit is cleared to 0 when gpu0_pwr_req goes low." "0,1" rgroup.long 0x4600++0x7 line.long 0x0 "CFG0_MAIN_MTOG0_CTRL,Controls timeout operation of read transactions from the GIC master port" rbitfld.long 0x0 31. "MAIN_MTOG0_CTRL_IDLE_STAT,Idle statusWhen high indicates MTOG0 is idle." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN_MTOG0_CTRL_FORCE_TIMEOUT,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared to.." newline bitfld.long 0x0 15. "MAIN_MTOG0_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x0 0.--2. "MAIN_MTOG0_CTRL_TIMEOUT_VAL,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 - 16 384.." "0,1,2,3,4,5,6,7" line.long 0x4 "CFG0_MAIN_MTOG1_CTRL,Controls timeout operation of write transactions from the GIC master port" rbitfld.long 0x4 31. "MAIN_MTOG1_CTRL_IDLE_STAT,Idle statusWhen high indicates MTOG1 is idle." "0,1" newline hexmask.long.byte 0x4 16.--23. 1. "MAIN_MTOG1_CTRL_FORCE_TIMEOUT,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared to.." newline bitfld.long 0x4 15. "MAIN_MTOG1_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x4 0.--2. "MAIN_MTOG1_CTRL_TIMEOUT_VAL,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 - 16 384.." "0,1,2,3,4,5,6,7" rgroup.long 0x4610++0x7 line.long 0x0 "CFG0_MAIN_MTOG4_CTRL,Controls timeout operation of read transactions from the eMMC1 master port" rbitfld.long 0x0 31. "MAIN_MTOG4_CTRL_IDLE_STAT,Idle statusWhen high indicates MTOG4 is idle." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN_MTOG4_CTRL_FORCE_TIMEOUT,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared to.." newline bitfld.long 0x0 15. "MAIN_MTOG4_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x0 0.--2. "MAIN_MTOG4_CTRL_TIMEOUT_VAL,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 - 16 384.." "0,1,2,3,4,5,6,7" line.long 0x4 "CFG0_MAIN_MTOG5_CTRL,Controls timeout operation of write transactions from the eMMC1 master port" rbitfld.long 0x4 31. "MAIN_MTOG5_CTRL_IDLE_STAT,Idle statusWhen high indicates MTOG5 is idle." "0,1" newline hexmask.long.byte 0x4 16.--23. 1. "MAIN_MTOG5_CTRL_FORCE_TIMEOUT,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared to.." newline bitfld.long 0x4 15. "MAIN_MTOG5_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x4 0.--2. "MAIN_MTOG5_CTRL_TIMEOUT_VAL,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 - 16 384.." "0,1,2,3,4,5,6,7" rgroup.long 0x4638++0x3 line.long 0x0 "CFG0_MAIN_MTOG14_CTRL,Controls timeout operation of transactions from the NavSS PVU to VIRTSS" rbitfld.long 0x0 31. "MAIN_MTOG14_CTRL_IDLE_STAT,Idle statusWhen high indicates MTOG14 is idle." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN_MTOG14_CTRL_FORCE_TIMEOUT,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared.." newline bitfld.long 0x0 15. "MAIN_MTOG14_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x0 0.--2. "MAIN_MTOG14_CTRL_TIMEOUT_VAL,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" rgroup.long 0x4640++0x27 line.long 0x0 "CFG0_MAIN_MTOG16_CTRL,Controls timeout operation of read transactions from the MAIN R5 Clstr0 Core0 VBUSM Memory master port" rbitfld.long 0x0 31. "MAIN_MTOG16_CTRL_IDLE_STAT,Idle statusWhen high indicates MTOG16 is idle." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN_MTOG16_CTRL_FORCE_TIMEOUT,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared.." newline bitfld.long 0x0 15. "MAIN_MTOG16_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x0 0.--2. "MAIN_MTOG16_CTRL_TIMEOUT_VAL,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x4 "CFG0_MAIN_MTOG17_CTRL,Controls timeout operation of write transactions from the MAIN R5 Clstr0 Core0 VBUSM Memory master port" rbitfld.long 0x4 31. "MAIN_MTOG17_CTRL_IDLE_STAT,Idle statusWhen high indicates MTOG17 is idle." "0,1" newline hexmask.long.byte 0x4 16.--23. 1. "MAIN_MTOG17_CTRL_FORCE_TIMEOUT,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared.." newline bitfld.long 0x4 15. "MAIN_MTOG17_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x4 0.--2. "MAIN_MTOG17_CTRL_TIMEOUT_VAL,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x8 "CFG0_MAIN_MTOG18_CTRL,Controls timeout operation of read transactions from the MAIN R5 Clstr0 Core1 VBUSM Memory master port" rbitfld.long 0x8 31. "MAIN_MTOG18_CTRL_IDLE_STAT,Idle statusWhen high indicates MTOG18 is idle." "0,1" newline hexmask.long.byte 0x8 16.--23. 1. "MAIN_MTOG18_CTRL_FORCE_TIMEOUT,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared.." newline bitfld.long 0x8 15. "MAIN_MTOG18_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x8 0.--2. "MAIN_MTOG18_CTRL_TIMEOUT_VAL,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0xC "CFG0_MAIN_MTOG19_CTRL,Controls timeout operation of write transactions from the MAIN R5 Clstr0 Core1 VBUSM Memory master port" rbitfld.long 0xC 31. "MAIN_MTOG19_CTRL_IDLE_STAT,Idle statusWhen high indicates MTOG19 is idle." "0,1" newline hexmask.long.byte 0xC 16.--23. 1. "MAIN_MTOG19_CTRL_FORCE_TIMEOUT,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared.." newline bitfld.long 0xC 15. "MAIN_MTOG19_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0xC 0.--2. "MAIN_MTOG19_CTRL_TIMEOUT_VAL,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x10 "CFG0_MAIN_MTOG20_CTRL,Controls timeout operation of read transactions from the MAIN R5 Clstr1 Core0 VBUSM Memory master port" rbitfld.long 0x10 31. "MAIN_MTOG20_CTRL_IDLE_STAT,Idle statusWhen high indicates MTOG20 is idle." "0,1" newline hexmask.long.byte 0x10 16.--23. 1. "MAIN_MTOG20_CTRL_FORCE_TIMEOUT,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared.." newline bitfld.long 0x10 15. "MAIN_MTOG20_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x10 0.--2. "MAIN_MTOG20_CTRL_TIMEOUT_VAL,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x14 "CFG0_MAIN_MTOG21_CTRL,Controls timeout operation of write transactions from the MAIN R5 Clstr1 Core0 VBUSM Memory master port" rbitfld.long 0x14 31. "MAIN_MTOG21_CTRL_IDLE_STAT,Idle statusWhen high indicates MTOG21 is idle." "0,1" newline hexmask.long.byte 0x14 16.--23. 1. "MAIN_MTOG21_CTRL_FORCE_TIMEOUT,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared.." newline bitfld.long 0x14 15. "MAIN_MTOG21_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x14 0.--2. "MAIN_MTOG21_CTRL_TIMEOUT_VAL,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x18 "CFG0_MAIN_MTOG22_CTRL,Controls timeout operation of read transactions from the MAIN R5 Clstr1 Core1 VBUSM Memory master port" rbitfld.long 0x18 31. "MAIN_MTOG22_CTRL_IDLE_STAT,Idle statusWhen high indicates MTOG22 is idle." "0,1" newline hexmask.long.byte 0x18 16.--23. 1. "MAIN_MTOG22_CTRL_FORCE_TIMEOUT,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared.." newline bitfld.long 0x18 15. "MAIN_MTOG22_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x18 0.--2. "MAIN_MTOG22_CTRL_TIMEOUT_VAL,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x1C "CFG0_MAIN_MTOG23_CTRL,Controls timeout operation of write transactions from the MAIN R5 Clstr1 Core 1 VBUSM Memory master port" rbitfld.long 0x1C 31. "MAIN_MTOG23_CTRL_IDLE_STAT,Idle statusWhen high indicates MTOG23 is idle." "0,1" newline hexmask.long.byte 0x1C 16.--23. 1. "MAIN_MTOG23_CTRL_FORCE_TIMEOUT,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared.." newline bitfld.long 0x1C 15. "MAIN_MTOG23_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x1C 0.--2. "MAIN_MTOG23_CTRL_TIMEOUT_VAL,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x20 "CFG0_MAIN_MTOG24_CTRL,Controls timeout operation of real time transactions from High Speed IO masters" rbitfld.long 0x20 31. "MAIN_MTOG24_CTRL_IDLE_STAT,Idle statusWhen high indicates MTOG24 is idle." "0,1" newline hexmask.long.byte 0x20 16.--23. 1. "MAIN_MTOG24_CTRL_FORCE_TIMEOUT,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared.." newline bitfld.long 0x20 15. "MAIN_MTOG24_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x20 0.--2. "MAIN_MTOG24_CTRL_TIMEOUT_VAL,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x24 "CFG0_MAIN_MTOG25_CTRL,Controls timeout operation of non-real time transactions from High Speed IO masters" rbitfld.long 0x24 31. "MAIN_MTOG25_CTRL_IDLE_STAT,Idle statusWhen high indicates MTOG25 is idle." "0,1" newline hexmask.long.byte 0x24 16.--23. 1. "MAIN_MTOG25_CTRL_FORCE_TIMEOUT,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared.." newline bitfld.long 0x24 15. "MAIN_MTOG25_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x24 0.--2. "MAIN_MTOG25_CTRL_TIMEOUT_VAL,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" rgroup.long 0x4680++0x1F line.long 0x0 "CFG0_MAIN_MTOG32_CTRL,Controls timeout operation of Accelerator Cluster ASIL-B master accesses to MSMC (L2) SRAM" rbitfld.long 0x0 31. "MAIN_MTOG32_CTRL_IDLE_STAT,Idle statusWhen high indicates MTOG32 is idle." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN_MTOG32_CTRL_FORCE_TIMEOUT,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared.." newline bitfld.long 0x0 15. "MAIN_MTOG32_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x0 0.--2. "MAIN_MTOG32_CTRL_TIMEOUT_VAL,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x4 "CFG0_MAIN_MTOG33_CTRL,Controls timeout operation of Accelerator Cluster QueueManager master accesses to MSMC (L2) SRAM" rbitfld.long 0x4 31. "MAIN_MTOG33_CTRL_IDLE_STAT,Idle statusWhen high indicates MTOG33 is idle." "0,1" newline hexmask.long.byte 0x4 16.--23. 1. "MAIN_MTOG33_CTRL_FORCE_TIMEOUT,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared.." newline bitfld.long 0x4 15. "MAIN_MTOG33_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x4 0.--2. "MAIN_MTOG33_CTRL_TIMEOUT_VAL,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x8 "CFG0_MAIN_MTOG34_CTRL,Controls timeout operation of Accelerator Cluster ASIL-B master accesses to DDR for OrderIDs 0-4" rbitfld.long 0x8 31. "MAIN_MTOG34_CTRL_IDLE_STAT,Idle statusWhen high indicates MTOG34 is idle." "0,1" newline hexmask.long.byte 0x8 16.--23. 1. "MAIN_MTOG34_CTRL_FORCE_TIMEOUT,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared.." newline bitfld.long 0x8 15. "MAIN_MTOG34_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x8 0.--2. "MAIN_MTOG34_CTRL_TIMEOUT_VAL,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0xC "CFG0_MAIN_MTOG35_CTRL,Controls timeout operation of Accelerator Cluster QueueManager master accesses to DDR fro OrderIDs 0-4" rbitfld.long 0xC 31. "MAIN_MTOG35_CTRL_IDLE_STAT,Idle statusWhen high indicates MTOG35 is idle." "0,1" newline hexmask.long.byte 0xC 16.--23. 1. "MAIN_MTOG35_CTRL_FORCE_TIMEOUT,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared.." newline bitfld.long 0xC 15. "MAIN_MTOG35_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0xC 0.--2. "MAIN_MTOG35_CTRL_TIMEOUT_VAL,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x10 "CFG0_MAIN_MTOG36_CTRL,Controls timeout operation of Accelerator Cluster ASIL-B master accesses to DDR for OrderIDs 5-9" rbitfld.long 0x10 31. "MAIN_MTOG36_CTRL_IDLE_STAT,Idle statusWhen high indicates MTOG36 is idle." "0,1" newline hexmask.long.byte 0x10 16.--23. 1. "MAIN_MTOG36_CTRL_FORCE_TIMEOUT,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared.." newline bitfld.long 0x10 15. "MAIN_MTOG36_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x10 0.--2. "MAIN_MTOG36_CTRL_TIMEOUT_VAL,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x14 "CFG0_MAIN_MTOG37_CTRL,Controls timeout operation of Accelerator Cluster QueueManager master accesses to DDR for OrderIDs 5-9" rbitfld.long 0x14 31. "MAIN_MTOG37_CTRL_IDLE_STAT,Idle statusWhen high indicates MTOG37 is idle." "0,1" newline hexmask.long.byte 0x14 16.--23. 1. "MAIN_MTOG37_CTRL_FORCE_TIMEOUT,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared.." newline bitfld.long 0x14 15. "MAIN_MTOG37_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x14 0.--2. "MAIN_MTOG37_CTRL_TIMEOUT_VAL,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x18 "CFG0_MAIN_MTOG38_CTRL,Controls timeout operation of Accelerator Cluster ASIL-B master accesses to DDR for OrderIDs 10-15" rbitfld.long 0x18 31. "MAIN_MTOG38_CTRL_IDLE_STAT,Idle statusWhen high indicates MTOG38 is idle." "0,1" newline hexmask.long.byte 0x18 16.--23. 1. "MAIN_MTOG38_CTRL_FORCE_TIMEOUT,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared.." newline bitfld.long 0x18 15. "MAIN_MTOG38_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x18 0.--2. "MAIN_MTOG38_CTRL_TIMEOUT_VAL,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x1C "CFG0_MAIN_MTOG39_CTRL,Controls timeout operation of Accelerator Cluster QueueManager master accesses to DDR for OrderIDs 10-15" rbitfld.long 0x1C 31. "MAIN_MTOG39_CTRL_IDLE_STAT,Idle statusWhen high indicates MTOG39 is idle." "0,1" newline hexmask.long.byte 0x1C 16.--23. 1. "MAIN_MTOG39_CTRL_FORCE_TIMEOUT,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared.." newline bitfld.long 0x1C 15. "MAIN_MTOG39_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x1C 0.--2. "MAIN_MTOG39_CTRL_TIMEOUT_VAL,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" rgroup.long 0x46C0++0x3 line.long 0x0 "CFG0_CC_FLUSH_CTRL0,This register is used isolate the MSMC ARM Corepac 0 interface from other MSMC transactions in case of an ARM Corepac access hang. This allows continuation of other MSMC traffic (e.g. R5 processors) without interference. After.." hexmask.long.byte 0x0 0.--7. 1. "CC_FLUSH_CTRL0_FLUSH,Flush ARM / MSMC Interface TransactionsForces a flush of the A72 MSMC interface. This bit field can be used to force a flush of A72 transactions to the MSMC and force an auto response of any MSMC snoop requests to the A72. An.." rgroup.long 0x46D0++0x7 line.long 0x0 "CFG0_CC_FLUSH_CTRL4,This register is used isolate the MSMC C7x Corepac 4 (C71x_0) interface from other MSMC transactions in case of an C7x Corepac access hang. This allows continuation of other MSMC traffic (e.g. R5 processors) without interference." hexmask.long.byte 0x0 0.--7. 1. "CC_FLUSH_CTRL4_FLUSH,Flush C7x / MSMC Interface TransactionsForces a flush of the C7x MSMC interface. This bit field can be used to force a flush of C7x transactions to the MSMC and force an auto response of any MSMC snoop requests to the C7x. An.." line.long 0x4 "CFG0_CC_FLUSH_CTRL5,This register is used isolate the MSMC C7x Corepac 5 (C71x_1) interface from other MSMC transactions in case of an C7x Corepac access hang. This allows continuation of other MSMC traffic (e.g. R5 processors) without interference." hexmask.long.byte 0x4 0.--7. 1. "CC_FLUSH_CTRL5_FLUSH,Flush C7x / MSMC Interface TransactionsForces a flush of the C7x MSMC interface. This bit field can be used to force a flush of C7x transactions to the MSMC and force an auto response of any MSMC snoop requests to the C7x. An.." rgroup.long 0x46E0++0x3 line.long 0x0 "CFG0_CC_FLUSH_CTRL8,This register is used isolate the MSMC DRU 0 Interfaces from other MSMC transactions in case of a DRU 0 access hang. This allows continuation of other MSMC traffic (e.g. R5 processors) without interference. After asserting this.." hexmask.long.byte 0x0 0.--7. 1. "CC_FLUSH_CTRL8_FLUSH,Flush DRU 0 / MSMC Interface TransactionsForces a flush of the DRU 0 MSMC interface. This bit field can be used to force a flush of DRU 0 transactions to the MSMC and force an auto response of any MSMC snoop requests to the DRU. An.." rgroup.long 0x5008++0x7 line.long 0x0 "CFG0_LOCK1_KICK0,This register must be written with the designated key value followed by a write to LOCK1_KICK1 with its key value before write-protected Partition 1 registers can be written." hexmask.long 0x0 0.--31. 1. "LOCK1_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK1_KICK1,This register must be written with the designated key value after a write to LOCK1_KICK0 with its key value before write-protected Partition 1 registers can be written." hexmask.long 0x4 0.--31. 1. "LOCK1_KICK1,- KICK1 component" rgroup.long 0x5100++0x3B line.long 0x0 "CFG0_CLAIMREG_P1_R0_READONLY," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P1_R0_READONLY,Claim bits for Partition 1" line.long 0x4 "CFG0_CLAIMREG_P1_R1_READONLY," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P1_R1_READONLY,Claim bits for Partition 1" line.long 0x8 "CFG0_CLAIMREG_P1_R2_READONLY," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P1_R2_READONLY,Claim bits for Partition 1" line.long 0xC "CFG0_CLAIMREG_P1_R3_READONLY," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P1_R3_READONLY,Claim bits for Partition 1" line.long 0x10 "CFG0_CLAIMREG_P1_R4_READONLY," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P1_R4_READONLY,Claim bits for Partition 1" line.long 0x14 "CFG0_CLAIMREG_P1_R5_READONLY," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P1_R5_READONLY,Claim bits for Partition 1" line.long 0x18 "CFG0_CLAIMREG_P1_R6_READONLY," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P1_R6_READONLY,Claim bits for Partition 1" line.long 0x1C "CFG0_CLAIMREG_P1_R7_READONLY," hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P1_R7_READONLY,Claim bits for Partition 1" line.long 0x20 "CFG0_CLAIMREG_P1_R8_READONLY," hexmask.long 0x20 0.--31. 1. "CLAIMREG_P1_R8_READONLY,Claim bits for Partition 1" line.long 0x24 "CFG0_CLAIMREG_P1_R9_READONLY," hexmask.long 0x24 0.--31. 1. "CLAIMREG_P1_R9_READONLY,Claim bits for Partition 1" line.long 0x28 "CFG0_CLAIMREG_P1_R10_READONLY," hexmask.long 0x28 0.--31. 1. "CLAIMREG_P1_R10_READONLY,Claim bits for Partition 1" line.long 0x2C "CFG0_CLAIMREG_P1_R11_READONLY," hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P1_R11_READONLY,Claim bits for Partition 1" line.long 0x30 "CFG0_CLAIMREG_P1_R12_READONLY," hexmask.long 0x30 0.--31. 1. "CLAIMREG_P1_R12_READONLY,Claim bits for Partition 1" line.long 0x34 "CFG0_CLAIMREG_P1_R13_READONLY," hexmask.long 0x34 0.--31. 1. "CLAIMREG_P1_R13_READONLY,Claim bits for Partition 1" line.long 0x38 "CFG0_CLAIMREG_P1_R14_READONLY," hexmask.long 0x38 0.--31. 1. "CLAIMREG_P1_R14_READONLY,Claim bits for Partition 1" rgroup.long 0x6000++0x3 line.long 0x0 "CFG0_USB0_CTRL_PROXY,Controls USB0 operation" bitfld.long 0x0 27. "USB0_CTRL_SERDES_SEL_PROXY,Serdes Selection.The USB3_0 interface can be mapped to 2 different SERDES lanes. This bit selects which SERDES drives the USB3 PIPE interface input clock data and control signals. Programming should align with the.." "0: SERDES0 Ln3 drives USB3_0 inputs 1,?" rgroup.long 0x6008++0x3 line.long 0x0 "CFG0_USB0_PHY_CTRL_PROXY,Configures the USB0 Phy operation" bitfld.long 0x0 31. "USB0_PHY_CTRL_CORE_VOLTAGE_PROXY,Selects the USB PHY core voltage 0 - Core voltage is 0.85 V 1 - Core voltage is 0.80 V" "0: Core voltage is 0,1: Core voltage is 0" rgroup.long 0x6034++0x3 line.long 0x0 "CFG0_CPSW2_ENET1_CTRL_PROXY,Controls MAIN CPSW_2G Ethernet Port1 operation" bitfld.long 0x0 4. "CPSW2_ENET1_CTRL_RGMII_ID_MODE_PROXY,Port 1 RGMII internal transmit delay selection 0 - Internal transmit delay 1 - No internal transmit delay" "0: Internal transmit delay 1,?" newline bitfld.long 0x0 0.--1. "CPSW2_ENET1_CTRL_MODE_SEL_PROXY,Selects Ethernet switch Port1 interface Field values (Others are reserved): 2'b00 - GMII/MII (not supported) 2'b01 - RMII 2'b10 - RGMII 2'b11 - SGMII (not supported)" "0: GMII/MII,1: RMII 2'b10,?,3: SGMII" rgroup.long 0x6074++0x3 line.long 0x0 "CFG0_PCIE1_CTRL_PROXY,Controls PCIe1 operation" bitfld.long 0x0 8.--9. "PCIE1_CTRL_LANE_COUNT_PROXY,Configures the PCIe lane count 00 - Select 1-lane operation 01 - Select 2-lane operation 1x - Select 4-lane operation" "0: Select 1-lane operation 01,?,2: lane operation 1x,?" newline bitfld.long 0x0 7. "PCIE1_CTRL_MODE_SEL_PROXY,Selects the operating mode 0 - Endpoint 1 - Root Complex" "0: Endpoint 1,?" newline bitfld.long 0x0 0.--1. "PCIE1_CTRL_GENERATION_SEL_PROXY,Configures the PCIe generation support in the PCIe capabilities linked-list Field values (Others are reserved): 2'b01 - Gen2 - Controller advertises Gen1 & Gen2 capability and link operates at either speed 2'b10 -.." "?,1: Gen2,2: Gen3,3: Reserved" rgroup.long 0x6080++0xF line.long 0x0 "CFG0_SERDES0_LN0_CTRL_PROXY,Controls SERDES0 lane0 selection" bitfld.long 0x0 0.--1. "SERDES0_LN0_CTRL_LANE_FUNC_SEL_PROXY,Selects the SERDES0 lane0 function Field values (Others are reserved): 2'b00 - IP1 - eDP0 Lane 0 2'b01 - IP2 - PCIe1 Lane 0 2'b10 - IP3 - Not used 2'b11 - IP4 - Hyperlink (VUSR) Lane 0" "0: IP1,1: IP2,2: IP3,3: IP4" line.long 0x4 "CFG0_SERDES0_LN1_CTRL_PROXY,Controls SERDES0 lane1 selection" bitfld.long 0x4 0.--1. "SERDES0_LN1_CTRL_LANE_FUNC_SEL_PROXY,Selects the SERDES0 lane1 function Field values (Others are reserved): 2'b00 - IP1 - eDP0 Lane 1 2'b01 - IP2 - PCIe1 Lane 1 2'b10 - IP3 - USB3_0 2'b11 - IP4 - Hyperlink (VUSR) Lane 1" "0: IP1,1: IP2,2: IP3,3: IP4" line.long 0x8 "CFG0_SERDES0_LN2_CTRL_PROXY,Controls SERDES0 lane2 selection" bitfld.long 0x8 0.--1. "SERDES0_LN2_CTRL_LANE_FUNC_SEL_PROXY,Selects the SERDES0 lane2 function Field values (Others are reserved): 2'b00 - IP1 - eDP0 Lane 2/0 2'b01 - IP2 - PCIe1 Lane 2 2'b10 - IP3 - Not Used 2'b11 - Ip4 - Hyperlink (VUSR) Lane 2" "0: IP1,1: IP2,2: IP3,3: Ip4" line.long 0xC "CFG0_SERDES0_LN3_CTRL_PROXY,Controls SERDES0 lane3 selection" bitfld.long 0xC 0.--1. "SERDES0_LN3_CTRL_LANE_FUNC_SEL_PROXY,Selects the SERDES0 lane3 function Field values (Others are reserved): 2'b00 - IP1 - eDP0 Lane 3/1 2'b01 - IP2 - PCIe1 Lane 3 2'b10 - IP3 - USB3_0 2'b11 - IP4 - Hyperlink (VUSR) Lane 3" "0: IP1,1: IP2,2: IP3,3: IP4" rgroup.long 0x60E0++0x3 line.long 0x0 "CFG0_SERDES0_CTRL_PROXY,Controls SERDES0 operation" bitfld.long 0x0 8. "SERDES0_CTRL_RET_EN_PROXY,Retention enable" "0,1" rgroup.long 0x6140++0x17 line.long 0x0 "CFG0_EPWM0_CTRL_PROXY,Controls ePWM0 Operation" bitfld.long 0x0 4. "EPWM0_CTRL_EALLOW_PROXY,Enable write access to ePWM tripzone and HRPWM config registers 0 - Disabled 1 - Enabled" "0: Disabled 1,?" newline bitfld.long 0x0 0. "EPWM0_CTRL_TB_CLKEN_PROXY,Enable ePWM timebase clock 0 - Disabled 1 - EnabledThis bit is OR'd with SUP_CTRL7_pwm0_tb_clken. Setting the tb_clken in either register will start the timebase counter." "0: Disabled 1,?" line.long 0x4 "CFG0_EPWM1_CTRL_PROXY,Controls ePWM1 Operation" bitfld.long 0x4 4. "EPWM1_CTRL_EALLOW_PROXY,Enable write access to ePWM tripzone and HRPWM config registers 0 - Disabled 1 - Enabled" "0: Disabled 1,?" newline bitfld.long 0x4 0. "EPWM1_CTRL_TB_CLKEN_PROXY,Enable ePWM timebase clock 0 - Disabled 1 - EnabledThis bit is OR'd with SUP_CTRL7_pwm1_tb_clken. Setting the tb_clken in either register will start the timebase counter." "0: Disabled 1,?" line.long 0x8 "CFG0_EPWM2_CTRL_PROXY,Controls ePWM2 Operation" bitfld.long 0x8 4. "EPWM2_CTRL_EALLOW_PROXY,Enable write access to ePWM tripzone and HRPWM config registers 0 - Disabled 1 - Enabled" "0: Disabled 1,?" newline bitfld.long 0x8 0. "EPWM2_CTRL_TB_CLKEN_PROXY,Enable ePWM timebase clock 0 - Disabled 1 - EnabledThis bit is OR'd with SUP_CTRL7_pwm2_tb_clken. Setting the tb_clken in either register will start the timebase counter." "0: Disabled 1,?" line.long 0xC "CFG0_EPWM3_CTRL_PROXY,Controls ePWM3 Operation" bitfld.long 0xC 8.--10. "EPWM3_CTRL_SYNCIN_SEL_PROXY,Selects the source of the PWM3 synchronization input Field values (Others are reserved): 3'b000 - PWM3_SYNCIN Pin 3'b001 - PWM2 syncout signal daisy chained 3'b010 - None 3'b011 - None 3'b100 - None.." "0: PWM3_SYNCIN Pin 3'b001,?,2: None 3'b011,?,4: None 3'b101,?,6: None 3'b111,?" newline bitfld.long 0xC 4. "EPWM3_CTRL_EALLOW_PROXY,Enable write access to ePWM tripzone and HRPWM config registers 0 - Disabled 1 - Enabled" "0: Disabled 1,?" newline bitfld.long 0xC 0. "EPWM3_CTRL_TB_CLKEN_PROXY,Enable ePWM timebase clock 0 - Disabled 1 - EnabledThis bit is OR'd with SUP_CTRL7_pwm3_tb_clken. Setting the tb_clken in either register will start the timebase counter." "0: Disabled 1,?" line.long 0x10 "CFG0_EPWM4_CTRL_PROXY,Controls ePWM4 Operation" bitfld.long 0x10 4. "EPWM4_CTRL_EALLOW_PROXY,Enable write access to ePWM tripzone and HRPWM config registers 0 - Disabled 1 - Enabled" "0: Disabled 1,?" newline bitfld.long 0x10 0. "EPWM4_CTRL_TB_CLKEN_PROXY,Enable ePWM timebase clock 0 - Disabled 1 - EnabledThis bit is OR'd with SUP_CTRL7_pwm4_tb_clken. Setting the tb_clken in either register will start the timebase counter." "0: Disabled 1,?" line.long 0x14 "CFG0_EPWM5_CTRL_PROXY,Controls ePWM5 Operation" bitfld.long 0x14 4. "EPWM5_CTRL_EALLOW_PROXY,Enable write access to ePWM tripzone and HRPWM config registers 0 - Disabled 1 - Enabled" "0: Disabled 1,?" newline bitfld.long 0x14 0. "EPWM5_CTRL_TB_CLKEN_PROXY,Enable ePWM timebase clock 0 - Disabled 1 - EnabledThis bit is OR'd with SUP_CTRL7_pwm5_tb_clken. Setting the tb_clken in either register will start the timebase counter." "0: Disabled 1,?" rgroup.long 0x6160++0x7 line.long 0x0 "CFG0_SOCA_SEL_PROXY,Selects Start of Conversion A output signal source. Each ePWM provides a SOCA event that can be used to trigger external ADCs. All ePWM SOCA events are ORed together allowing any of the 6 ePWMs to generate the event (if enabled.." bitfld.long 0x0 0.--1. "SOCA_SEL_SOCA_SEL_PROXY,Selects the SOC A output source Field values (Others are reserved): 2'b00 - OR of all eHRPWM SOCA outputs 2'b01 - None 2'b10 - None 2'b11 - None" "0: OR of all eHRPWM SOCA outputs 2'b01,?,2: None 2'b11,?" line.long 0x4 "CFG0_SOCB_SEL_PROXY,Selects Start of Conversion B output signal source.. Each ePWM provides a SOCB event that can be used to trigger external ADCs. All ePWM SOCB events are ORed together allowing any of the 6 ePWMs to generate the event (if enabled.." bitfld.long 0x4 0.--1. "SOCB_SEL_SOCB_SEL_PROXY,Selects the SOC B output source Field values (Others are reserved): 2'b00 - OR of all eHRPWM SOCB ouputs 2'b01 - None 2'b10 - None 2'b11 - None" "0: OR of all eHRPWM SOCB ouputs 2'b01,?,2: None 2'b11,?" rgroup.long 0x61A0++0x3 line.long 0x0 "CFG0_EQEP_STAT_PROXY,Displays status of EQEP modules" bitfld.long 0x0 2. "EQEP_STAT_PHASE_ERR2_PROXY,eQEP2 Phase error status 0 - No error 1 - Phase error occurred" "0: No error 1,?" newline bitfld.long 0x0 1. "EQEP_STAT_PHASE_ERR1_PROXY,eQEP1 Phase error status 0 - No error 1 - Phase error occurred" "0: No error 1,?" newline bitfld.long 0x0 0. "EQEP_STAT_PHASE_ERR0_PROXY,eQEP0 Phase error status 0 - No error 1 - Phase error occurred" "0: No error 1,?" rgroup.long 0x61B4++0x3 line.long 0x0 "CFG0_SDIO1_CTRL_PROXY,Controls drive strength of MMC1 SDIO mode pins" hexmask.long.byte 0x0 0.--4. 1. "SDIO1_CTRL_DRV_STR_PROXY,Selects the SDIO drive strength" rgroup.long 0x6200++0x4F line.long 0x0 "CFG0_TIMER0_CTRL_PROXY,Controls TIMER0 operation" bitfld.long 0x0 0.--2. "TIMER0_CTRL_CAP_SEL_PROXY,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER0 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x4 "CFG0_TIMER1_CTRL_PROXY,Controls TIMER1 operation" bitfld.long 0x4 8. "TIMER1_CTRL_CASCADE_EN_PROXY,Enables cascading of TIMER1 to TIMER0" "0,1" newline bitfld.long 0x4 0.--2. "TIMER1_CTRL_CAP_SEL_PROXY,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER1 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x8 "CFG0_TIMER2_CTRL_PROXY,Controls TIMER2 operation" bitfld.long 0x8 0.--2. "TIMER2_CTRL_CAP_SEL_PROXY,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER2 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0xC "CFG0_TIMER3_CTRL_PROXY,Controls TIMER3 operation" bitfld.long 0xC 8. "TIMER3_CTRL_CASCADE_EN_PROXY,Enables cascading of TIMER3 to TIMER2" "0,1" newline bitfld.long 0xC 0.--2. "TIMER3_CTRL_CAP_SEL_PROXY,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER3 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x10 "CFG0_TIMER4_CTRL_PROXY,Controls TIMER4 operation" bitfld.long 0x10 0.--2. "TIMER4_CTRL_CAP_SEL_PROXY,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER4 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x14 "CFG0_TIMER5_CTRL_PROXY,Controls TIMER5 operation" bitfld.long 0x14 8. "TIMER5_CTRL_CASCADE_EN_PROXY,Enables cascading of TIMER5 to TIMER4" "0,1" newline bitfld.long 0x14 0.--2. "TIMER5_CTRL_CAP_SEL_PROXY,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER5 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x18 "CFG0_TIMER6_CTRL_PROXY,Controls TIMER6 operation" bitfld.long 0x18 0.--2. "TIMER6_CTRL_CAP_SEL_PROXY,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER6 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x1C "CFG0_TIMER7_CTRL_PROXY,Controls TIMER7 operation" bitfld.long 0x1C 8. "TIMER7_CTRL_CASCADE_EN_PROXY,Enables cascading of TIMER7 to TIMER6" "0,1" newline bitfld.long 0x1C 0.--2. "TIMER7_CTRL_CAP_SEL_PROXY,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER7 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x20 "CFG0_TIMER8_CTRL_PROXY,Controls TIMER8 operation" bitfld.long 0x20 0.--2. "TIMER8_CTRL_CAP_SEL_PROXY,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER8 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x24 "CFG0_TIMER9_CTRL_PROXY,Controls TIMER9 operation" bitfld.long 0x24 8. "TIMER9_CTRL_CASCADE_EN_PROXY,Enables cascading of TIMER9 to TIMER8" "0,1" newline bitfld.long 0x24 0.--2. "TIMER9_CTRL_CAP_SEL_PROXY,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER9 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1 pin.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x28 "CFG0_TIMER10_CTRL_PROXY,Controls TIMER10 operation" bitfld.long 0x28 0.--2. "TIMER10_CTRL_CAP_SEL_PROXY,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER10 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x2C "CFG0_TIMER11_CTRL_PROXY,Controls TIMER11 operation" bitfld.long 0x2C 8. "TIMER11_CTRL_CASCADE_EN_PROXY,Enables cascading of TIMER11 to TIMER10" "0,1" newline bitfld.long 0x2C 0.--2. "TIMER11_CTRL_CAP_SEL_PROXY,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER11 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x30 "CFG0_TIMER12_CTRL_PROXY,Controls TIMER12 operation" bitfld.long 0x30 0.--2. "TIMER12_CTRL_CAP_SEL_PROXY,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER12 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x34 "CFG0_TIMER13_CTRL_PROXY,Controls TIMER13 operation" bitfld.long 0x34 8. "TIMER13_CTRL_CASCADE_EN_PROXY,Enables cascading of TIMER13 to TIMER12" "0,1" newline bitfld.long 0x34 0.--2. "TIMER13_CTRL_CAP_SEL_PROXY,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER13 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x38 "CFG0_TIMER14_CTRL_PROXY,Controls TIMER14 operation" bitfld.long 0x38 0.--2. "TIMER14_CTRL_CAP_SEL_PROXY,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER14 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x3C "CFG0_TIMER15_CTRL_PROXY,Controls TIMER15 operation" bitfld.long 0x3C 8. "TIMER15_CTRL_CASCADE_EN_PROXY,Enables cascading of TIMER15 to TIMER14" "0,1" newline bitfld.long 0x3C 0.--2. "TIMER15_CTRL_CAP_SEL_PROXY,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER15 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x40 "CFG0_TIMER16_CTRL_PROXY,Controls TIMER16 operation" bitfld.long 0x40 0.--2. "TIMER16_CTRL_CAP_SEL_PROXY,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER16 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x44 "CFG0_TIMER17_CTRL_PROXY,Controls TIMER17 operation" bitfld.long 0x44 8. "TIMER17_CTRL_CASCADE_EN_PROXY,Enables cascading of TIMER17 to TIMER16" "0,1" newline bitfld.long 0x44 0.--2. "TIMER17_CTRL_CAP_SEL_PROXY,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER17 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x48 "CFG0_TIMER18_CTRL_PROXY,Controls TIMER18 operation" bitfld.long 0x48 0.--2. "TIMER18_CTRL_CAP_SEL_PROXY,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER18 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" line.long 0x4C "CFG0_TIMER19_CTRL_PROXY,Controls TIMER19 operation" bitfld.long 0x4C 8. "TIMER19_CTRL_CASCADE_EN_PROXY,Enables cascading of TIMER19 to TIMER18" "0,1" newline bitfld.long 0x4C 0.--2. "TIMER19_CTRL_CAP_SEL_PROXY,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER19 is configured for capture operation. Field values (Others are reserved): 3'b000 - Use TIMERIO0 pin 3'b001 - Use TIMERIO1.." "0: Use TIMERIO0 pin 3'b001,?,2: Use TIMERIO2 pin 3'b011,?,4: Use TIMERIO4 pin 3'b101,?,6: Use TIMERIO6 pin 3'b111,?" rgroup.long 0x6280++0x1F line.long 0x0 "CFG0_TIMERIO0_CTRL_PROXY,Controls Timer IO muxing" hexmask.long.byte 0x0 0.--4. 1. "TIMERIO0_CTRL_OUT_SEL_PROXY,Selects the source of the TIMERIO0 output Field values (Others are reserved): 5'b00000 - TIMERIO0 is driven by TIMER0 output 5'b00001 - TIMERIO0 is driven by TIMER1 output 5'b00010 - TIMERIO0 is driven by TIMER2.." line.long 0x4 "CFG0_TIMERIO1_CTRL_PROXY,Controls Timer IO muxing" hexmask.long.byte 0x4 0.--4. 1. "TIMERIO1_CTRL_OUT_SEL_PROXY,Selects the source of the TIMERIO1 output Field values (Others are reserved): 5'b00000 - TIMERIO1 is driven by TIMER0 output 5'b00001 - TIMERIO1 is driven by TIMER1 output 5'b00010 - TIMERIO1 is driven by TIMER2.." line.long 0x8 "CFG0_TIMERIO2_CTRL_PROXY,Controls Timer IO muxing" hexmask.long.byte 0x8 0.--4. 1. "TIMERIO2_CTRL_OUT_SEL_PROXY,Selects the source of the TIMERIO2 output Field values (Others are reserved): 5'b00000 - TIMERIO2 is driven by TIMER0 output 5'b00001 - TIMERIO2 is driven by TIMER1 output 5'b00010 - TIMERIO2 is driven by TIMER2.." line.long 0xC "CFG0_TIMERIO3_CTRL_PROXY,Controls Timer IO muxing" hexmask.long.byte 0xC 0.--4. 1. "TIMERIO3_CTRL_OUT_SEL_PROXY,Selects the source of the TIMERIO3 output Field values (Others are reserved): 5'b00000 - TIMERIO3 is driven by TIMER0 output 5'b00001 - TIMERIO3 is driven by TIMER1 output 5'b00010 - TIMERIO3 is driven by TIMER2.." line.long 0x10 "CFG0_TIMERIO4_CTRL_PROXY,Controls Timer IO muxing" hexmask.long.byte 0x10 0.--4. 1. "TIMERIO4_CTRL_OUT_SEL_PROXY,Selects the source of the TIMERIO4 output Field values (Others are reserved): 5'b00000 - TIMERIO4 is driven by TIMER0 output 5'b00001 - TIMERIO4 is driven by TIMER1 output 5'b00010 - TIMERIO4 is driven by TIMER2.." line.long 0x14 "CFG0_TIMERIO5_CTRL_PROXY,Controls Timer IO muxing" hexmask.long.byte 0x14 0.--4. 1. "TIMERIO5_CTRL_OUT_SEL_PROXY,Selects the source of the TIMERIO5 output Field values (Others are reserved): 5'b00000 - TIMERIO5 is driven by TIMER0 output 5'b00001 - TIMERIO5 is driven by TIMER1 output 5'b00010 - TIMERIO5 is driven by TIMER2.." line.long 0x18 "CFG0_TIMERIO6_CTRL_PROXY,Controls Timer IO muxing" hexmask.long.byte 0x18 0.--4. 1. "TIMERIO6_CTRL_OUT_SEL_PROXY,Selects the source of the TIMERIO6 output Field values (Others are reserved): 5'b00000 - TIMERIO6 is driven by TIMER0 output 5'b00001 - TIMERIO6 is driven by TIMER1 output 5'b00010 - TIMERIO6 is driven by TIMER2.." line.long 0x1C "CFG0_TIMERIO7_CTRL_PROXY,Controls Timer IO muxing" hexmask.long.byte 0x1C 0.--4. 1. "TIMERIO7_CTRL_OUT_SEL_PROXY,Selects the source of the TIMERIO7 output Field values (Others are reserved): 5'b00000 - TIMERIO7 is driven by TIMER0 output 5'b00001 - TIMERIO7 is driven by TIMER1 output 5'b00010 - TIMERIO7 is driven by TIMER2.." rgroup.long 0x62E0++0x3 line.long 0x0 "CFG0_I2C0_CTRL_PROXY,Controls I2C0 operation for open drain I/Os" bitfld.long 0x0 0. "I2C0_CTRL_HS_MCS_EN_PROXY,HS Mode master current source enable.When set enables the current-source pull-up on the SCL output. Only one master on the I2C bus should enable SCL current sourcing." "0,1" rgroup.long 0x6300++0x7 line.long 0x0 "CFG0_DPHY_TX0_CTRL_PROXY,Controls DPHY_TX0 operation" bitfld.long 0x0 0.--1. "DPHY_TX0_CTRL_LANE_FUNC_SEL_PROXY,Selects the source for the 4 lanes of DPHY_TX 0 Field values (Others are reserved): 2'b00 - IP1 (DSI_0 PPI0) 2'b01 - IP2 (CSI-TX0)" "0: IP1,1: IP2,?,?" line.long 0x4 "CFG0_DPHY_TX1_CTRL_PROXY,Controls DPHY_TX1 operation" bitfld.long 0x4 0.--1. "DPHY_TX1_CTRL_LANE_FUNC_SEL_PROXY,Selects the source for the 4 lanes of DPHY_TX 1 Field values (Others are reserved): 2'b00 - IP1 (DSI_1 PPI0) 2'b01 - IP2 (CSI-TX1)" "0: IP1,1: IP2,?,?" rgroup.long 0x6310++0x3 line.long 0x0 "CFG0_EDP0_CTRL_PROXY,Controls eDP0 operation" bitfld.long 0x0 28. "EDP0_CTRL_SERDES_SEL_PROXY,Serdes Selection.In 1-Lane or 2-Lane mode the eDP0 Lane 0/1 interface can be mapped to 2 different SerDes lanes. This bit selects which SerDes lane drives the eDP0 Lane 0/1 interface input clock data and control signals.." "0: eDP0 Lane 0/1 map to Serdes0 Lane 0/1 and eDP..,1: eDP0 Lane 0/1 map to Serdes0 Lane 2/3" newline bitfld.long 0x0 8. "EDP0_CTRL_RESET_ISO_PROXY,Reset isolationWhen set enables reset isolation of eDP PHY" "0,1" rgroup.long 0x6320++0x3 line.long 0x0 "CFG0_VPAC0_CAL0_CTRL_PROXY,Controls VPAC0 Camera Adaptive Layer 0 interface operation" bitfld.long 0x0 0.--1. "VPAC0_CAL0_CTRL_CAL_SEL_PROXY,Selects the CSI_RX source for the VPAC CAL0 input Field values (Others are reserved): 2'b00 - CSI-RX 0 2'b01 - CSI-RX 1 2'b10 - Reserved 2'b11 - Reserved" "0: CSI-RX 0 2'b01,?,2: Reserved 2'b11,?" rgroup.long 0x63F0++0x3 line.long 0x0 "CFG0_CSI_RX_LOOPBACK_PROXY,Controls loopback of CSI-RX inputs to CSI-TX inputs for diagnostics." bitfld.long 0x0 2.--3. "CSI_RX_LOOPBACK_CSITX1_LB_SEL_PROXY,Selects the CSI-RX loopback source for CSI-TX1 Field values (Others are reserved): 2'b00 - CSI-RX 0 2'b01 - CSI-RX 1 2'b10 - Reserved 2'b11 - Reserved" "0: CSI-RX 0 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 0.--1. "CSI_RX_LOOPBACK_CSITX0_LB_SEL_PROXY,Selects the CSI-RX loopback source for CSI-TX0. Field values (Others are reserved): 2'b00 - CSI-RX 0 2'b01 - CSI-RX 1 2'b10 - Reserved 2'b11 - Reserved" "0: CSI-RX 0 2'b01,?,2: Reserved 2'b11,?" rgroup.long 0x6500++0x3 line.long 0x0 "CFG0_GPU0_GP_IN_REQ_PROXY,Generates GPIO input event to GPU0" bitfld.long 0x0 15. "GPU0_GP_IN_REQ_REQ_PROXY,Input request. This bit is set to generate a GPIO request to the GPU to read the requestor data input. This bit should be cleared by the requestor after the GPU has acknowledged the request." "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "GPU0_GP_IN_REQ_DATA_PROXY,GPIO requestor data input to the GPU" rgroup.long 0x6504++0x7 line.long 0x0 "CFG0_GPU0_GP_IN_ACK_PROXY,Acknowledge for GPIO input event from GPU0" bitfld.long 0x0 15. "GPU0_GP_IN_ACK_ACK_PROXY,Input acknowledge. The GPU will set this bit to acknowledge a GPIO input request. This will generate a gpu_gpio_ack interrupt which will be cleared when the requestor clears the req bit in the GPU_GP_IN_REQ register." "0,1" line.long 0x4 "CFG0_GPU0_GP_OUT_REQ_PROXY,Generates GPIO output event from GPU0" bitfld.long 0x4 15. "GPU0_GP_OUT_REQ_REQ_PROXY,Output request. This bit is set to generate a GPIO request from the GPU to read the requestor data output. This will generate a gpu_gpio_req interrupt which will be cleared when the receiver clears the ack bit in the.." "0,1" newline hexmask.long.byte 0x4 0.--7. 1. "GPU0_GP_OUT_REQ_DATA_PROXY,GPIO requestor data output from the GPU" rgroup.long 0x650C++0x3 line.long 0x0 "CFG0_GPU0_GP_OUT_ACK_PROXY,Acknowledge for GPIO output event to GPU0" bitfld.long 0x0 15. "GPU0_GP_OUT_ACK_ACK_PROXY,Output acknowledge. The receiver of the gpu_gpio_req interrupt will set this bit to acknowledge the GPIO output request. This bit is cleared when the GPU deasserts its gpio_output_req signal." "0,1" rgroup.long 0x6520++0x3 line.long 0x0 "CFG0_VUSR_CTRL_PROXY,Controls operation of the dual VUSR (Hyperlink) module" bitfld.long 0x0 16. "VUSR_CTRL_DUAL_VUSR_EN_PROXY,Selects single or dual VUSR interface operation 0 - Single VUSR interface (VUSR0) enabled 1 - Dual VUSR interface (VUSR0 & VUSR1) enabled" "0: Single VUSR interface,1: Dual VUSR interface" newline bitfld.long 0x0 8. "VUSR_CTRL_V1_K3_MODE_PROXY,VUSR1 interface operational mode 0 - Legacy (KS2) addressing/interface mode 1 - Enhanced (KS3) addressing/interface mode" "0: Legacy,1: Enhanced" newline bitfld.long 0x0 0. "VUSR_CTRL_V0_K3_MODE_PROXY,VUSR0 interface operational mode 0 - Legacy (KS2) addressing/interface mode 1 - Enhanced (KS3) addressing/interface mode" "0: Legacy,1: Enhanced" rgroup.long 0x6584++0xF line.long 0x0 "CFG0_MCASP1_CTRL_PROXY,Controls McASP1 operation" bitfld.long 0x0 23. "MCASP1_CTRL_AXR15_EN_PROXY,Enable AXR15 receive data. 0 - AXR15 input driven 1'b0 1 - AXR15 input driven by AFSR/X input selected by axr15_src value" "0: AXR15 input driven 1'b0 1,?" newline hexmask.long.byte 0x0 16.--19. 1. "MCASP1_CTRL_AXR15_SRC_PROXY,Selects one of the AFSX or AFSR inputs as the AXR15 data input Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX 4'b0100 -.." newline bitfld.long 0x0 7. "MCASP1_CTRL_AXR14_EN_PROXY,Enable AXR14 receive data. 0 - AXR14 input driven 1'b0 1 - AXR14 input driven by AFSR/X input selected by axr14_src value" "0: AXR14 input driven 1'b0 1,?" newline hexmask.long.byte 0x0 0.--3. 1. "MCASP1_CTRL_AXR14_SRC_PROXY,Selects one of the AFSX or AFSR inputs as the AXR14 data input Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX 4'b0100 -.." line.long 0x4 "CFG0_MCASP2_CTRL_PROXY,Controls McASP2 operation" bitfld.long 0x4 23. "MCASP2_CTRL_AXR15_EN_PROXY,Enable AXR15 receive data. 0 - AXR15 input driven 1'b0 1 - AXR15 input driven by AFSR/X input selected by axr15_src value" "0: AXR15 input driven 1'b0 1,?" newline hexmask.long.byte 0x4 16.--19. 1. "MCASP2_CTRL_AXR15_SRC_PROXY,Selects one of the AFSX or AFSR inputs as the AXR15 data input Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX 4'b0100 -.." newline bitfld.long 0x4 7. "MCASP2_CTRL_AXR14_EN_PROXY,Enable AXR14 receive data. 0 - AXR14 input driven 1'b0 1 - AXR14 input driven by AFSR/X input selected by axr14_src value" "0: AXR14 input driven 1'b0 1,?" newline hexmask.long.byte 0x4 0.--3. 1. "MCASP2_CTRL_AXR14_SRC_PROXY,Selects one of the AFSX or AFSR inputs as the AXR14 data input Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX 4'b0100 -.." line.long 0x8 "CFG0_MCASP3_CTRL_PROXY,Controls McASP3 operation" bitfld.long 0x8 23. "MCASP3_CTRL_AXR15_EN_PROXY,Enable AXR15 receive data. 0 - AXR15 input driven 1'b0 1 - AXR15 input driven by AFSR/X input selected by axr15_src value" "0: AXR15 input driven 1'b0 1,?" newline hexmask.long.byte 0x8 16.--19. 1. "MCASP3_CTRL_AXR15_SRC_PROXY,Selects one of the AFSX or AFSR inputs as the AXR15 data input Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX 4'b0100 -.." newline bitfld.long 0x8 7. "MCASP3_CTRL_AXR14_EN_PROXY,Enable AXR14 receive data. 0 - AXR14 input driven 1'b0 1 - AXR14 input driven by AFSR/X input selected by axr14_src value" "0: AXR14 input driven 1'b0 1,?" newline hexmask.long.byte 0x8 0.--3. 1. "MCASP3_CTRL_AXR14_SRC_PROXY,Selects one of the AFSX or AFSR inputs as the AXR14 data input Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX 4'b0100 -.." line.long 0xC "CFG0_MCASP4_CTRL_PROXY,Controls McASP4 operation" bitfld.long 0xC 23. "MCASP4_CTRL_AXR15_EN_PROXY,Enable AXR15 receive data. 0 - AXR15 input driven 1'b0 1 - AXR15 input driven by AFSR/X input selected by axr15_src value" "0: AXR15 input driven 1'b0 1,?" newline hexmask.long.byte 0xC 16.--19. 1. "MCASP4_CTRL_AXR15_SRC_PROXY,Selects one of the AFSX or AFSR inputs as the AXR15 data input Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX 4'b0100 -.." newline bitfld.long 0xC 7. "MCASP4_CTRL_AXR14_EN_PROXY,Enable AXR14 receive data. 0 - AXR14 input driven 1'b0 1 - AXR14 input driven by AFSR/X input selected by axr14_src value" "0: AXR14 input driven 1'b0 1,?" newline hexmask.long.byte 0xC 0.--3. 1. "MCASP4_CTRL_AXR14_SRC_PROXY,Selects one of the AFSX or AFSR inputs as the AXR14 data input Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX 4'b0100 -.." rgroup.long 0x65B0++0x3 line.long 0x0 "CFG0_GPU0_CFG_PROXY,Configures GPU core operation" hexmask.long.byte 0x0 8.--11. 1. "GPU0_CFG_GPU_COUNT_PROXY,Indicates number of GPU core used in multi-core operation. Should be set to 1 for GPU0 operation as independent GPU." newline bitfld.long 0x0 0.--2. "GPU0_CFG_GPU_ID_PROXY,GPU Multi-core core identificationShould always be set as 0 for GPU0" "0,1,2,3,4,5,6,7" rgroup.long 0x65C0++0x3 line.long 0x0 "CFG0_GPU0_PWR_REQ_PROXY,Indicates GPU0 power control interface requests" bitfld.long 0x0 16. "GPU0_PWR_REQ_REQ_PROXY,Power control request. This bit is set by the GPU to request a Power Management event to the PM processor. This will generate a gpu0_pwr_req interrupt. The interrupt is cleared only when the GPU clears its pwrctrl_gpu_req output." "0,1" newline bitfld.long 0x0 12. "GPU0_PWR_REQ_TYPE_PROXY,GPU request type. 0 - Power Down request 1 - Power Up request" "0: Power Down request 1,?" newline bitfld.long 0x0 8.--10. "GPU0_PWR_REQ_DOMAIN_PROXY,GPU request mask. Indicates GPU domain to which the power event applies. For mapping refer to GPU RGX_CR_POWER_EVENT register." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "GPU0_PWR_REQ_GPU_MASK_PROXY,GPU request mask. One bit per GPU indicating to which GPUs the power event applies. Mask bits are indexed by GPU_ID" rgroup.long 0x65C4++0x3 line.long 0x0 "CFG0_GPU0_PWR_ACK_PROXY,Controls GPU0 power control interface request acknowledgement" bitfld.long 0x0 16. "GPU0_PWR_ACK_ABORT_PROXY,Power control abort. This bit is set by the PM processor to that the GPU power control request could not be completed. The bit is cleared to 0 when gpu0_pwr_req goes low." "0,1" newline bitfld.long 0x0 0. "GPU0_PWR_ACK_COMPLETE_PROXY,Power control complete. This bit is set by the PM processor to indicate sucessful completion of the GPU power control request. The bit is cleared to 0 when gpu0_pwr_req goes low." "0,1" rgroup.long 0x6600++0x7 line.long 0x0 "CFG0_MAIN_MTOG0_CTRL_PROXY,Controls timeout operation of read transactions from the GIC master port" rbitfld.long 0x0 31. "MAIN_MTOG0_CTRL_IDLE_STAT_PROXY,Idle statusWhen high indicates MTOG0 is idle." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN_MTOG0_CTRL_FORCE_TIMEOUT_PROXY,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0x0 15. "MAIN_MTOG0_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x0 0.--2. "MAIN_MTOG0_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x4 "CFG0_MAIN_MTOG1_CTRL_PROXY,Controls timeout operation of write transactions from the GIC master port" rbitfld.long 0x4 31. "MAIN_MTOG1_CTRL_IDLE_STAT_PROXY,Idle statusWhen high indicates MTOG1 is idle." "0,1" newline hexmask.long.byte 0x4 16.--23. 1. "MAIN_MTOG1_CTRL_FORCE_TIMEOUT_PROXY,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0x4 15. "MAIN_MTOG1_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x4 0.--2. "MAIN_MTOG1_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" rgroup.long 0x6610++0x7 line.long 0x0 "CFG0_MAIN_MTOG4_CTRL_PROXY,Controls timeout operation of read transactions from the eMMC1 master port" rbitfld.long 0x0 31. "MAIN_MTOG4_CTRL_IDLE_STAT_PROXY,Idle statusWhen high indicates MTOG4 is idle." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN_MTOG4_CTRL_FORCE_TIMEOUT_PROXY,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0x0 15. "MAIN_MTOG4_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x0 0.--2. "MAIN_MTOG4_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x4 "CFG0_MAIN_MTOG5_CTRL_PROXY,Controls timeout operation of write transactions from the eMMC1 master port" rbitfld.long 0x4 31. "MAIN_MTOG5_CTRL_IDLE_STAT_PROXY,Idle statusWhen high indicates MTOG5 is idle." "0,1" newline hexmask.long.byte 0x4 16.--23. 1. "MAIN_MTOG5_CTRL_FORCE_TIMEOUT_PROXY,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0x4 15. "MAIN_MTOG5_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x4 0.--2. "MAIN_MTOG5_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" rgroup.long 0x6638++0x3 line.long 0x0 "CFG0_MAIN_MTOG14_CTRL_PROXY,Controls timeout operation of transactions from the NavSS PVU to VIRTSS" rbitfld.long 0x0 31. "MAIN_MTOG14_CTRL_IDLE_STAT_PROXY,Idle statusWhen high indicates MTOG14 is idle." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN_MTOG14_CTRL_FORCE_TIMEOUT_PROXY,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0x0 15. "MAIN_MTOG14_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x0 0.--2. "MAIN_MTOG14_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" rgroup.long 0x6640++0x27 line.long 0x0 "CFG0_MAIN_MTOG16_CTRL_PROXY,Controls timeout operation of read transactions from the MAIN R5 Clstr0 Core0 VBUSM Memory master port" rbitfld.long 0x0 31. "MAIN_MTOG16_CTRL_IDLE_STAT_PROXY,Idle statusWhen high indicates MTOG16 is idle." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN_MTOG16_CTRL_FORCE_TIMEOUT_PROXY,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0x0 15. "MAIN_MTOG16_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x0 0.--2. "MAIN_MTOG16_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x4 "CFG0_MAIN_MTOG17_CTRL_PROXY,Controls timeout operation of write transactions from the MAIN R5 Clstr0 Core0 VBUSM Memory master port" rbitfld.long 0x4 31. "MAIN_MTOG17_CTRL_IDLE_STAT_PROXY,Idle statusWhen high indicates MTOG17 is idle." "0,1" newline hexmask.long.byte 0x4 16.--23. 1. "MAIN_MTOG17_CTRL_FORCE_TIMEOUT_PROXY,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0x4 15. "MAIN_MTOG17_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x4 0.--2. "MAIN_MTOG17_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x8 "CFG0_MAIN_MTOG18_CTRL_PROXY,Controls timeout operation of read transactions from the MAIN R5 Clstr0 Core1 VBUSM Memory master port" rbitfld.long 0x8 31. "MAIN_MTOG18_CTRL_IDLE_STAT_PROXY,Idle statusWhen high indicates MTOG18 is idle." "0,1" newline hexmask.long.byte 0x8 16.--23. 1. "MAIN_MTOG18_CTRL_FORCE_TIMEOUT_PROXY,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0x8 15. "MAIN_MTOG18_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x8 0.--2. "MAIN_MTOG18_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0xC "CFG0_MAIN_MTOG19_CTRL_PROXY,Controls timeout operation of write transactions from the MAIN R5 Clstr0 Core1 VBUSM Memory master port" rbitfld.long 0xC 31. "MAIN_MTOG19_CTRL_IDLE_STAT_PROXY,Idle statusWhen high indicates MTOG19 is idle." "0,1" newline hexmask.long.byte 0xC 16.--23. 1. "MAIN_MTOG19_CTRL_FORCE_TIMEOUT_PROXY,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0xC 15. "MAIN_MTOG19_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0xC 0.--2. "MAIN_MTOG19_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x10 "CFG0_MAIN_MTOG20_CTRL_PROXY,Controls timeout operation of read transactions from the MAIN R5 Clstr1 Core0 VBUSM Memory master port" rbitfld.long 0x10 31. "MAIN_MTOG20_CTRL_IDLE_STAT_PROXY,Idle statusWhen high indicates MTOG20 is idle." "0,1" newline hexmask.long.byte 0x10 16.--23. 1. "MAIN_MTOG20_CTRL_FORCE_TIMEOUT_PROXY,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0x10 15. "MAIN_MTOG20_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x10 0.--2. "MAIN_MTOG20_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x14 "CFG0_MAIN_MTOG21_CTRL_PROXY,Controls timeout operation of write transactions from the MAIN R5 Clstr1 Core0 VBUSM Memory master port" rbitfld.long 0x14 31. "MAIN_MTOG21_CTRL_IDLE_STAT_PROXY,Idle statusWhen high indicates MTOG21 is idle." "0,1" newline hexmask.long.byte 0x14 16.--23. 1. "MAIN_MTOG21_CTRL_FORCE_TIMEOUT_PROXY,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0x14 15. "MAIN_MTOG21_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x14 0.--2. "MAIN_MTOG21_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x18 "CFG0_MAIN_MTOG22_CTRL_PROXY,Controls timeout operation of read transactions from the MAIN R5 Clstr1 Core1 VBUSM Memory master port" rbitfld.long 0x18 31. "MAIN_MTOG22_CTRL_IDLE_STAT_PROXY,Idle statusWhen high indicates MTOG22 is idle." "0,1" newline hexmask.long.byte 0x18 16.--23. 1. "MAIN_MTOG22_CTRL_FORCE_TIMEOUT_PROXY,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0x18 15. "MAIN_MTOG22_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x18 0.--2. "MAIN_MTOG22_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x1C "CFG0_MAIN_MTOG23_CTRL_PROXY,Controls timeout operation of write transactions from the MAIN R5 Clstr1 Core 1 VBUSM Memory master port" rbitfld.long 0x1C 31. "MAIN_MTOG23_CTRL_IDLE_STAT_PROXY,Idle statusWhen high indicates MTOG23 is idle." "0,1" newline hexmask.long.byte 0x1C 16.--23. 1. "MAIN_MTOG23_CTRL_FORCE_TIMEOUT_PROXY,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0x1C 15. "MAIN_MTOG23_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x1C 0.--2. "MAIN_MTOG23_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x20 "CFG0_MAIN_MTOG24_CTRL_PROXY,Controls timeout operation of real time transactions from High Speed IO masters" rbitfld.long 0x20 31. "MAIN_MTOG24_CTRL_IDLE_STAT_PROXY,Idle statusWhen high indicates MTOG24 is idle." "0,1" newline hexmask.long.byte 0x20 16.--23. 1. "MAIN_MTOG24_CTRL_FORCE_TIMEOUT_PROXY,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0x20 15. "MAIN_MTOG24_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x20 0.--2. "MAIN_MTOG24_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x24 "CFG0_MAIN_MTOG25_CTRL_PROXY,Controls timeout operation of non-real time transactions from High Speed IO masters" rbitfld.long 0x24 31. "MAIN_MTOG25_CTRL_IDLE_STAT_PROXY,Idle statusWhen high indicates MTOG25 is idle." "0,1" newline hexmask.long.byte 0x24 16.--23. 1. "MAIN_MTOG25_CTRL_FORCE_TIMEOUT_PROXY,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0x24 15. "MAIN_MTOG25_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x24 0.--2. "MAIN_MTOG25_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" rgroup.long 0x6680++0x1F line.long 0x0 "CFG0_MAIN_MTOG32_CTRL_PROXY,Controls timeout operation of Accelerator Cluster ASIL-B master accesses to MSMC (L2) SRAM" rbitfld.long 0x0 31. "MAIN_MTOG32_CTRL_IDLE_STAT_PROXY,Idle statusWhen high indicates MTOG32 is idle." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN_MTOG32_CTRL_FORCE_TIMEOUT_PROXY,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0x0 15. "MAIN_MTOG32_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x0 0.--2. "MAIN_MTOG32_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x4 "CFG0_MAIN_MTOG33_CTRL_PROXY,Controls timeout operation of Accelerator Cluster QueueManager master accesses to MSMC (L2) SRAM" rbitfld.long 0x4 31. "MAIN_MTOG33_CTRL_IDLE_STAT_PROXY,Idle statusWhen high indicates MTOG33 is idle." "0,1" newline hexmask.long.byte 0x4 16.--23. 1. "MAIN_MTOG33_CTRL_FORCE_TIMEOUT_PROXY,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0x4 15. "MAIN_MTOG33_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x4 0.--2. "MAIN_MTOG33_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x8 "CFG0_MAIN_MTOG34_CTRL_PROXY,Controls timeout operation of Accelerator Cluster ASIL-B master accesses to DDR for OrderIDs 0-4" rbitfld.long 0x8 31. "MAIN_MTOG34_CTRL_IDLE_STAT_PROXY,Idle statusWhen high indicates MTOG34 is idle." "0,1" newline hexmask.long.byte 0x8 16.--23. 1. "MAIN_MTOG34_CTRL_FORCE_TIMEOUT_PROXY,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0x8 15. "MAIN_MTOG34_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x8 0.--2. "MAIN_MTOG34_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0xC "CFG0_MAIN_MTOG35_CTRL_PROXY,Controls timeout operation of Accelerator Cluster QueueManager master accesses to DDR fro OrderIDs 0-4" rbitfld.long 0xC 31. "MAIN_MTOG35_CTRL_IDLE_STAT_PROXY,Idle statusWhen high indicates MTOG35 is idle." "0,1" newline hexmask.long.byte 0xC 16.--23. 1. "MAIN_MTOG35_CTRL_FORCE_TIMEOUT_PROXY,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0xC 15. "MAIN_MTOG35_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0xC 0.--2. "MAIN_MTOG35_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x10 "CFG0_MAIN_MTOG36_CTRL_PROXY,Controls timeout operation of Accelerator Cluster ASIL-B master accesses to DDR for OrderIDs 5-9" rbitfld.long 0x10 31. "MAIN_MTOG36_CTRL_IDLE_STAT_PROXY,Idle statusWhen high indicates MTOG36 is idle." "0,1" newline hexmask.long.byte 0x10 16.--23. 1. "MAIN_MTOG36_CTRL_FORCE_TIMEOUT_PROXY,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0x10 15. "MAIN_MTOG36_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x10 0.--2. "MAIN_MTOG36_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x14 "CFG0_MAIN_MTOG37_CTRL_PROXY,Controls timeout operation of Accelerator Cluster QueueManager master accesses to DDR for OrderIDs 5-9" rbitfld.long 0x14 31. "MAIN_MTOG37_CTRL_IDLE_STAT_PROXY,Idle statusWhen high indicates MTOG37 is idle." "0,1" newline hexmask.long.byte 0x14 16.--23. 1. "MAIN_MTOG37_CTRL_FORCE_TIMEOUT_PROXY,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0x14 15. "MAIN_MTOG37_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x14 0.--2. "MAIN_MTOG37_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x18 "CFG0_MAIN_MTOG38_CTRL_PROXY,Controls timeout operation of Accelerator Cluster ASIL-B master accesses to DDR for OrderIDs 10-15" rbitfld.long 0x18 31. "MAIN_MTOG38_CTRL_IDLE_STAT_PROXY,Idle statusWhen high indicates MTOG38 is idle." "0,1" newline hexmask.long.byte 0x18 16.--23. 1. "MAIN_MTOG38_CTRL_FORCE_TIMEOUT_PROXY,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0x18 15. "MAIN_MTOG38_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x18 0.--2. "MAIN_MTOG38_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" line.long 0x1C "CFG0_MAIN_MTOG39_CTRL_PROXY,Controls timeout operation of Accelerator Cluster QueueManager master accesses to DDR for OrderIDs 10-15" rbitfld.long 0x1C 31. "MAIN_MTOG39_CTRL_IDLE_STAT_PROXY,Idle statusWhen high indicates MTOG39 is idle." "0,1" newline hexmask.long.byte 0x1C 16.--23. 1. "MAIN_MTOG39_CTRL_FORCE_TIMEOUT_PROXY,Force TimeoutForces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0x1C 15. "MAIN_MTOG39_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x1C 0.--2. "MAIN_MTOG39_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout ValueSelects the number of clock cycles before the interface is considered to have timed out Field values (Others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 -.." "0,1,2,3,4,5,6,7" rgroup.long 0x66C0++0x3 line.long 0x0 "CFG0_CC_FLUSH_CTRL0_PROXY,This register is used isolate the MSMC ARM Corepac 0 interface from other MSMC transactions in case of an ARM Corepac access hang. This allows continuation of other MSMC traffic (e.g. R5 processors) without interference. After.." hexmask.long.byte 0x0 0.--7. 1. "CC_FLUSH_CTRL0_FLUSH_PROXY,Flush ARM / MSMC Interface TransactionsForces a flush of the A72 MSMC interface. This bit field can be used to force a flush of A72 transactions to the MSMC and force an auto response of any MSMC snoop requests to the A72. An.." rgroup.long 0x66D0++0x7 line.long 0x0 "CFG0_CC_FLUSH_CTRL4_PROXY,This register is used isolate the MSMC C7x Corepac 4 (C71x_0) interface from other MSMC transactions in case of an C7x Corepac access hang. This allows continuation of other MSMC traffic (e.g. R5 processors) without.." hexmask.long.byte 0x0 0.--7. 1. "CC_FLUSH_CTRL4_FLUSH_PROXY,Flush C7x / MSMC Interface TransactionsForces a flush of the C7x MSMC interface. This bit field can be used to force a flush of C7x transactions to the MSMC and force an auto response of any MSMC snoop requests to the C7x. An.." line.long 0x4 "CFG0_CC_FLUSH_CTRL5_PROXY,This register is used isolate the MSMC C7x Corepac 5 (C71x_1) interface from other MSMC transactions in case of an C7x Corepac access hang. This allows continuation of other MSMC traffic (e.g. R5 processors) without.." hexmask.long.byte 0x4 0.--7. 1. "CC_FLUSH_CTRL5_FLUSH_PROXY,Flush C7x / MSMC Interface TransactionsForces a flush of the C7x MSMC interface. This bit field can be used to force a flush of C7x transactions to the MSMC and force an auto response of any MSMC snoop requests to the C7x. An.." rgroup.long 0x66E0++0x3 line.long 0x0 "CFG0_CC_FLUSH_CTRL8_PROXY,This register is used isolate the MSMC DRU 0 Interfaces from other MSMC transactions in case of a DRU 0 access hang. This allows continuation of other MSMC traffic (e.g. R5 processors) without interference. After asserting.." hexmask.long.byte 0x0 0.--7. 1. "CC_FLUSH_CTRL8_FLUSH_PROXY,Flush DRU 0 / MSMC Interface TransactionsForces a flush of the DRU 0 MSMC interface. This bit field can be used to force a flush of DRU 0 transactions to the MSMC and force an auto response of any MSMC snoop requests to the.." rgroup.long 0x7008++0x7 line.long 0x0 "CFG0_LOCK1_KICK0_PROXY,This register must be written with the designated key value followed by a write to LOCK1_KICK1 with its key value before write-protected Partition 1 registers can be written." hexmask.long 0x0 0.--31. 1. "LOCK1_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK1_KICK1_PROXY,This register must be written with the designated key value after a write to LOCK1_KICK0 with its key value before write-protected Partition 1 registers can be written." hexmask.long 0x4 0.--31. 1. "LOCK1_KICK1_PROXY,- KICK1 component" rgroup.long 0x7100++0x3B line.long 0x0 "CFG0_CLAIMREG_P1_R0," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P1_R0,Claim bits for Partition 1" line.long 0x4 "CFG0_CLAIMREG_P1_R1," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P1_R1,Claim bits for Partition 1" line.long 0x8 "CFG0_CLAIMREG_P1_R2," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P1_R2,Claim bits for Partition 1" line.long 0xC "CFG0_CLAIMREG_P1_R3," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P1_R3,Claim bits for Partition 1" line.long 0x10 "CFG0_CLAIMREG_P1_R4," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P1_R4,Claim bits for Partition 1" line.long 0x14 "CFG0_CLAIMREG_P1_R5," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P1_R5,Claim bits for Partition 1" line.long 0x18 "CFG0_CLAIMREG_P1_R6," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P1_R6,Claim bits for Partition 1" line.long 0x1C "CFG0_CLAIMREG_P1_R7," hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P1_R7,Claim bits for Partition 1" line.long 0x20 "CFG0_CLAIMREG_P1_R8," hexmask.long 0x20 0.--31. 1. "CLAIMREG_P1_R8,Claim bits for Partition 1" line.long 0x24 "CFG0_CLAIMREG_P1_R9," hexmask.long 0x24 0.--31. 1. "CLAIMREG_P1_R9,Claim bits for Partition 1" line.long 0x28 "CFG0_CLAIMREG_P1_R10," hexmask.long 0x28 0.--31. 1. "CLAIMREG_P1_R10,Claim bits for Partition 1" line.long 0x2C "CFG0_CLAIMREG_P1_R11," hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P1_R11,Claim bits for Partition 1" line.long 0x30 "CFG0_CLAIMREG_P1_R12," hexmask.long 0x30 0.--31. 1. "CLAIMREG_P1_R12,Claim bits for Partition 1" line.long 0x34 "CFG0_CLAIMREG_P1_R13," hexmask.long 0x34 0.--31. 1. "CLAIMREG_P1_R13,Claim bits for Partition 1" line.long 0x38 "CFG0_CLAIMREG_P1_R14," hexmask.long 0x38 0.--31. 1. "CLAIMREG_P1_R14,Claim bits for Partition 1" rgroup.long 0x8000++0x7 line.long 0x0 "CFG0_OBSCLK0_CTRL,This register controls which internal clock is made observable on the OBSCLK[2:0] output pins" bitfld.long 0x0 16. "OBSCLK0_CTRL_CLK_DIV_LD,Load the output divider valueWriting 1 to this bit will generate a load pulse to load the OBSCLK0 divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "OBSCLK0_CTRL_CLK_DIV,OBSCLK0 output dividerDivides the selected clock by clkdiv+1 for output to the OBSCLK[2:0] pins. Supports divide by 1 to 256 (default to 1). To load the new divider value the clk_div_ld bit must be cleared and then set to 1." newline hexmask.long.byte 0x0 0.--4. 1. "OBSCLK0_CTRL_CLK_SEL,OBSCLK0 clock source selection.Selects the source of the clock to be divided by the OBSCLK0 divider and output on the OBSCLK[2:0] pins. Field values (Others are reserved): 5'b00000 - MAIN_PLL0_HSDIV0_CLKOUT 5'b00001 -.." line.long 0x4 "CFG0_OBSCLK1_CTRL,This register controls which internal clock is made observable on the OBSCLK1_OUT internal clock signal" bitfld.long 0x4 0.--1. "OBSCLK1_CTRL_CLK_SEL,OBSCLK1_OUT signal output clock source selection Field values (Others are reserved): 2'b00 - MAIN_PLL7_HSDIV0_CLKOUT / DIV4 2'b01 - MAIN_PLL8_HSDIV0_CLKOUT / DIV8 2'b10 - 0 2'b11 - 0" "0: MAIN_PLL7_HSDIV0_CLKOUT / DIV4 2'b01,?,?,?" rgroup.long 0x8010++0x3 line.long 0x0 "CFG0_CLKOUT_CTRL,Enables and selects clock source of CPSW CLKOUT pin" bitfld.long 0x0 4. "CLKOUT_CTRL_CLK_EN,When set enables CLKOUT output" "0,1" newline bitfld.long 0x0 0. "CLKOUT_CTRL_CLK_SEL,Selects CLKOUT clock source 1'b0 - RGMII_MHZ_50_CLK (50 MHz) 1'b1 -RGMII_MHZ_50_CLK_DIV2 (25 MHz)" "0: RGMII_MHZ_50_CLK,1: RGMII_MHZ_50_CLK_DIV2" rgroup.long 0x8030++0x3 line.long 0x0 "CFG0_GTC_CLKSEL,Selects the timebase clock source for the Global Timebase Counter" hexmask.long.byte 0x0 0.--3. 1. "GTC_CLKSEL_CLK_SEL,Selects the GTC timebase clock source Field values (Others are reserved): 4'b0000 - MAIN_PLL3_HSDIV1_CLKOUT 4'b0001 - MAIN_PLL0_HSDIV6_CLKOUT 4'b0010 - MCU_CPTS_REF_CLK (pin) 4'b0011 - CPTS_RFT_CLK (pin) 4'b0100 -.." rgroup.long 0x803C++0x3 line.long 0x0 "CFG0_EFUSE_CLKSEL,Selects the functional clock source for the MAIN domain eFuse Controller" bitfld.long 0x0 0. "EFUSE_CLKSEL_CLK_SEL,Selects the clock source Field values (Others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - MAIN_SYSCLK0 / 4" "0: HFOSC0_CLKOUT 1'b1,?" rgroup.long 0x8074++0x3 line.long 0x0 "CFG0_PCIE_REFCLK1_CLKSEL,PCIE_REFCLK1 P/N are driven by ACSPCIE0 PAD 0" bitfld.long 0x0 8. "PCIE_REFCLK1_CLKSEL_OUT_CLK_EN,Enables the output of the ACSPCIE buffer to drive the PCIE1 REFCLK P/N pins" "0,1" newline bitfld.long 0x0 0.--1. "PCIE_REFCLK1_CLKSEL_OUT_CLKSEL,Selects the PCIE1 REFCLK output clock source.Controls the ACSPCIE0 buffer PAD0 clock mux. Field values (Others are reserved): 2'b00 - SERDES0_REF_DER_OUT_CLK 2'b01 - MAIN_PLL2_HSDIV4_CLKOUT 2'b10 -.." "0: SERDES0_REF_DER_OUT_CLK 2'b01,?,2: SERDES0_REF_OUT_CLK 2'b11,?" rgroup.long 0x8084++0x3 line.long 0x0 "CFG0_PCIE1_CLKSEL,Selects PCIe1 functional clock sources" hexmask.long.byte 0x0 0.--3. 1. "PCIE1_CLKSEL_CPTS_CLKSEL,Selects the clock source for the PCIE1 Common Platform Time Stamp module Field values (Others are reserved): 4'b0000 - MAIN_PLL3_HSDIV1_CLKOUT 4'b0001 - MAIN_PLL0_HSDIV6_CLKOUT 4'b0010 - MCU_CPTS_REF_CLK (pin).." rgroup.long 0x8094++0x7 line.long 0x0 "CFG0_CPSW2_CLKSEL,Selects the 2 port CP Switch clock sources" hexmask.long.byte 0x0 0.--3. 1. "CPSW2_CLKSEL_CPTS_CLKSEL,Selects the clock source for the CPSW2G Ethernet switch Common Platform Time Stamp module Field values (Others are reserved): 4'b0000 - MAIN_PLL3_HSDIV1_CLKOUT 4'b0001 - MAIN_PLL0_HSDIV6_CLKOUT 4'b0010 -.." line.long 0x4 "CFG0_NAVSS_CLKSEL,Selects the clock source for the NavSS Subsystem" hexmask.long.byte 0x4 0.--3. 1. "NAVSS_CLKSEL_CPTS_CLKSEL,Selects the clock source for the SoC] Common Platform Time Stamp module located within the Nav Subsystem Field values (Others are reserved): 4'b0000 - MAIN_PLL3_HSDIV1_CLKOUT 4'b0001 - MAIN_PLL0_HSDIV6_CLKOUT 4'b0010.." rgroup.long 0x80B0++0x7 line.long 0x0 "CFG0_EMMC0_CLKSEL,Selects the functional clock source for 8-bit eMMC0" bitfld.long 0x0 0.--1. "EMMC0_CLKSEL_CLK_SEL,eMMC XIN_CLK selection 2'b00 - MAIN_PLL0_HSDIV2_CLKOUT 2'b01 - MAIN_PLL1_HSDIV2_CLKOUT 2'b10 - MAIN_PLL2_HSDIV2_CLKOUT 2'b11 - MAIN_PLL3_HSDIV2_CLKOUT" "0: MAIN_PLL0_HSDIV2_CLKOUT 2'b01,?,2: MAIN_PLL2_HSDIV2_CLKOUT 2'b11,?" line.long 0x4 "CFG0_EMMC1_CLKSEL,Selects the functional clock source for 4-bit eMMC1" bitfld.long 0x4 16. "EMMC1_CLKSEL_LB_CLKSEL,eMMC Loopback clock selection 1'b0 - Loopback clock from MMC1_CLKLB pad 1'b1 - Loopback clock from MMC1_CLK pin" "0: Loopback clock from MMC1_CLKLB pad 1'b1,?" newline bitfld.long 0x4 0.--1. "EMMC1_CLKSEL_CLK_SEL,eMMC XIN_CLK selection 2'b00 - MAIN_PLL0_HSDIV2_CLKOUT 2'b01 - MAIN_PLL1_HSDIV2_CLKOUT 2'b10 - MAIN_PLL2_HSDIV2_CLKOUT 2'b11 - MAIN_PLL3_HSDIV2_CLKOUT" "0: MAIN_PLL0_HSDIV2_CLKOUT 2'b01,?,2: MAIN_PLL2_HSDIV2_CLKOUT 2'b11,?" rgroup.long 0x80D0++0x3 line.long 0x0 "CFG0_GPMC_CLKSEL,Selects the bus and functional clock source for the GPMC module. This allows the GPMC to run asynchronously to the bus fabric in order to optimize parallel port performance." bitfld.long 0x0 0.--1. "GPMC_CLKSEL_CLK_SEL,Selects the GPMC clock source 2'b00 - MAIN_PLL0_HSDIV3_CLKOUT 2'b01 - MAIN_PLL2_HSDIV1_CLKOUT / 6 2'b10 - MAIN_PLL2_HSDIV1_CLKOUT / 4 2'b11 - MAIN_SYSCLK0 / 4" "0: MAIN_PLL0_HSDIV3_CLKOUT 2'b01,?,2: MAIN_PLL2_HSDIV1_CLKOUT / 4 2'b11,?" rgroup.long 0x80E0++0x3 line.long 0x0 "CFG0_USB0_CLKSEL,Selects the functional clock sources for USB0" bitfld.long 0x0 0. "USB0_CLKSEL_REFCLK_SEL,Selects the clock source for the USB0 ref_clk. 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" rgroup.long 0x80F0++0x3 line.long 0x0 "CFG0_VPAC_CLKSEL,Selects the functional clock sources for VPAC0" bitfld.long 0x0 0. "VPAC_CLKSEL_CLK_SEL,VPAC clock selection 1'b0 - MAIN_PLL25_HSDIV1_CLKOUT 1'b1 - MAIN_PLL2_HSDIV1_CLKOUT" "0: MAIN_PLL25_HSDIV1_CLKOUT 1'b1,?" rgroup.long 0x8100++0x4F line.long 0x0 "CFG0_TIMER0_CLKSEL,Timer0 functional clock selection control" hexmask.long.byte 0x0 0.--3. 1. "TIMER0_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT 4'b0011 -.." line.long 0x4 "CFG0_TIMER1_CLKSEL,Timer1 functional clock selection control" hexmask.long.byte 0x4 0.--3. 1. "TIMER1_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT 4'b0011 -.." line.long 0x8 "CFG0_TIMER2_CLKSEL,Timer2 functional clock selection control" hexmask.long.byte 0x8 0.--3. 1. "TIMER2_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT 4'b0011 -.." line.long 0xC "CFG0_TIMER3_CLKSEL,Timer3 functional clock selection control" hexmask.long.byte 0xC 0.--3. 1. "TIMER3_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT 4'b0011 -.." line.long 0x10 "CFG0_TIMER4_CLKSEL,Timer4 functional clock selection control" hexmask.long.byte 0x10 0.--3. 1. "TIMER4_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT 4'b0011 -.." line.long 0x14 "CFG0_TIMER5_CLKSEL,Timer5 functional clock selection control" hexmask.long.byte 0x14 0.--3. 1. "TIMER5_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT 4'b0011 -.." line.long 0x18 "CFG0_TIMER6_CLKSEL,Timer6 functional clock selection control" hexmask.long.byte 0x18 0.--3. 1. "TIMER6_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT 4'b0011 -.." line.long 0x1C "CFG0_TIMER7_CLKSEL,Timer7 functional clock selection control" hexmask.long.byte 0x1C 0.--3. 1. "TIMER7_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT 4'b0011 -.." line.long 0x20 "CFG0_TIMER8_CLKSEL,Timer8 functional clock selection control" hexmask.long.byte 0x20 0.--3. 1. "TIMER8_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT 4'b0011 -.." line.long 0x24 "CFG0_TIMER9_CLKSEL,Timer9 functional clock selection control" hexmask.long.byte 0x24 0.--3. 1. "TIMER9_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT 4'b0011 -.." line.long 0x28 "CFG0_TIMER10_CLKSEL,Timer10 functional clock selection control" hexmask.long.byte 0x28 0.--3. 1. "TIMER10_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT 4'b0011 -.." line.long 0x2C "CFG0_TIMER11_CLKSEL,Timer11 functional clock selection control" hexmask.long.byte 0x2C 0.--3. 1. "TIMER11_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT 4'b0011 -.." line.long 0x30 "CFG0_TIMER12_CLKSEL,Timer12 functional clock selection control" hexmask.long.byte 0x30 0.--3. 1. "TIMER12_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT 4'b0011 -.." line.long 0x34 "CFG0_TIMER13_CLKSEL,Timer13 functional clock selection control" hexmask.long.byte 0x34 0.--3. 1. "TIMER13_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT 4'b0011 -.." line.long 0x38 "CFG0_TIMER14_CLKSEL,Timer14 functional clock selection control" hexmask.long.byte 0x38 0.--3. 1. "TIMER14_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT 4'b0011 -.." line.long 0x3C "CFG0_TIMER15_CLKSEL,Timer15 functional clock selection control" hexmask.long.byte 0x3C 0.--3. 1. "TIMER15_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT 4'b0011 -.." line.long 0x40 "CFG0_TIMER16_CLKSEL,Timer16 functional clock selection control" bitfld.long 0x40 23. "TIMER16_CLKSEL_AFS_SRC_EN,Enable AFS source mux output as the Timer clock source. Note that for TIMER17 and TIMER19 this selection will be overridden if cascade_en in the associated TIMERn_CTRL register is set. 0 - Use functional clock selected by.." "0: Use functional clock selected by clk_sel value 1,?" newline hexmask.long.byte 0x40 16.--19. 1. "TIMER16_CLKSEL_AFS_SRC_SEL,Selects the ASFR/AFSX input to use as a timer clock when afs_src_en is set. Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX 4'b0100.." newline hexmask.long.byte 0x40 0.--3. 1. "TIMER16_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT 4'b0011 -.." line.long 0x44 "CFG0_TIMER17_CLKSEL,Timer17 functional clock selection control" bitfld.long 0x44 23. "TIMER17_CLKSEL_AFS_SRC_EN,Enable AFS source mux output as the Timer clock source. Note that for TIMER17 and TIMER19 this selection will be overridden if cascade_en in the associated TIMERn_CTRL register is set. 0 - Use functional clock selected by.." "0: Use functional clock selected by clk_sel value 1,?" newline hexmask.long.byte 0x44 16.--19. 1. "TIMER17_CLKSEL_AFS_SRC_SEL,Selects the ASFR/AFSX input to use as a timer clock when afs_src_en is set. Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX 4'b0100.." newline hexmask.long.byte 0x44 0.--3. 1. "TIMER17_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT 4'b0011 -.." line.long 0x48 "CFG0_TIMER18_CLKSEL,Timer18 functional clock selection control" bitfld.long 0x48 23. "TIMER18_CLKSEL_AFS_SRC_EN,Enable AFS source mux output as the Timer clock source. Note that for TIMER17 and TIMER19 this selection will be overridden if cascade_en in the associated TIMERn_CTRL register is set. 0 - Use functional clock selected by.." "0: Use functional clock selected by clk_sel value 1,?" newline hexmask.long.byte 0x48 16.--19. 1. "TIMER18_CLKSEL_AFS_SRC_SEL,Selects the ASFR/AFSX input to use as a timer clock when afs_src_en is set. Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX 4'b0100.." newline hexmask.long.byte 0x48 0.--3. 1. "TIMER18_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT 4'b0011 -.." line.long 0x4C "CFG0_TIMER19_CLKSEL,Timer19 functional clock selection control" bitfld.long 0x4C 23. "TIMER19_CLKSEL_AFS_SRC_EN,Enable AFS source mux output as the Timer clock source. Note that for TIMER17 and TIMER19 this selection will be overridden if cascade_en in the associated TIMERn_CTRL register is set. 0 - Use functional clock selected by.." "0: Use functional clock selected by clk_sel value 1,?" newline hexmask.long.byte 0x4C 16.--19. 1. "TIMER19_CLKSEL_AFS_SRC_SEL,Selects the ASFR/AFSX input to use as a timer clock when afs_src_en is set. Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX 4'b0100.." newline hexmask.long.byte 0x4C 0.--3. 1. "TIMER19_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT 4'b0011 -.." rgroup.long 0x8190++0xF line.long 0x0 "CFG0_SPI0_CLKSEL,SPI0 clock control" bitfld.long 0x0 16. "SPI0_CLKSEL_MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection 1'b0 - Internal clock loopback 1'b1 - Loopback from pad" "0: Internal clock loopback 1'b1,?" line.long 0x4 "CFG0_SPI1_CLKSEL,SPI1 clock control" bitfld.long 0x4 16. "SPI1_CLKSEL_MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection 1'b0 - Internal clock loopback 1'b1 - Loopback from pad" "0: Internal clock loopback 1'b1,?" line.long 0x8 "CFG0_SPI2_CLKSEL,SPI2 clock control" bitfld.long 0x8 16. "SPI2_CLKSEL_MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection 1'b0 - Internal clock loopback 1'b1 - Loopback from pad" "0: Internal clock loopback 1'b1,?" line.long 0xC "CFG0_SPI3_CLKSEL,SPI3 clock control" bitfld.long 0xC 16. "SPI3_CLKSEL_MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection 1'b0 - Internal clock loopback 1'b1 - Loopback from pad" "0: Internal clock loopback 1'b1,?" rgroup.long 0x81A4++0xB line.long 0x0 "CFG0_SPI5_CLKSEL,SPI5 clock control" bitfld.long 0x0 16. "SPI5_CLKSEL_MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection 1'b0 - Internal clock loopback 1'b1 - Loopback from pad" "0: Internal clock loopback 1'b1,?" line.long 0x4 "CFG0_SPI6_CLKSEL,SPI6 clock control" bitfld.long 0x4 16. "SPI6_CLKSEL_MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection 1'b0 - Internal clock loopback 1'b1 - Loopback from pad" "0: Internal clock loopback 1'b1,?" line.long 0x8 "CFG0_SPI7_CLKSEL,SPI7 clock control" bitfld.long 0x8 16. "SPI7_CLKSEL_MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection 1'b0 - Internal clock loopback 1'b1 - Loopback from pad" "0: Internal clock loopback 1'b1,?" rgroup.long 0x81C0++0x27 line.long 0x0 "CFG0_USART0_CLK_CTRL,Selects the clock divider of the USART0 functional clock" bitfld.long 0x0 16. "USART0_CLK_CTRL_CLK_DIV_LD,Load the output divider valueWriting 1 to this bit will generate a load pulse to load the USART0 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value.." "0,1" newline bitfld.long 0x0 0.--1. "USART0_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (Others are reserved): 2'b00 - Divide by 1.." "0: Divide by 1 2'b01,?,2: Divide by 3 2'b11,?" line.long 0x4 "CFG0_USART1_CLK_CTRL,Selects the clock divider of the USART1 functional clock" bitfld.long 0x4 16. "USART1_CLK_CTRL_CLK_DIV_LD,Load the output divider valueWriting 1 to this bit will generate a load pulse to load the USART1 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value.." "0,1" newline bitfld.long 0x4 0.--1. "USART1_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (Others are reserved): 2'b00 - Divide by 1.." "0: Divide by 1 2'b01,?,2: Divide by 3 2'b11,?" line.long 0x8 "CFG0_USART2_CLK_CTRL,Selects the clock divider of the USART2 functional clock" bitfld.long 0x8 16. "USART2_CLK_CTRL_CLK_DIV_LD,Load the output divider valueWriting 1 to this bit will generate a load pulse to load the USART2 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value.." "0,1" newline bitfld.long 0x8 0.--1. "USART2_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (Others are reserved): 2'b00 - Divide by 1.." "0: Divide by 1 2'b01,?,2: Divide by 3 2'b11,?" line.long 0xC "CFG0_USART3_CLK_CTRL,Selects the clock divider of the USART3 functional clock" bitfld.long 0xC 16. "USART3_CLK_CTRL_CLK_DIV_LD,Load the output divider valueWriting 1 to this bit will generate a load pulse to load the USART3 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value.." "0,1" newline bitfld.long 0xC 0.--1. "USART3_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (Others are reserved): 2'b00 - Divide by 1.." "0: Divide by 1 2'b01,?,2: Divide by 3 2'b11,?" line.long 0x10 "CFG0_USART4_CLK_CTRL,Selects the clock divider of the USART4 functional clock" bitfld.long 0x10 16. "USART4_CLK_CTRL_CLK_DIV_LD,Load the output divider valueWriting 1 to this bit will generate a load pulse to load the USART4 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value.." "0,1" newline bitfld.long 0x10 0.--1. "USART4_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (Others are reserved): 2'b00 - Divide by 1.." "0: Divide by 1 2'b01,?,2: Divide by 3 2'b11,?" line.long 0x14 "CFG0_USART5_CLK_CTRL,Selects the clock divider of the USART5 functional clock" bitfld.long 0x14 16. "USART5_CLK_CTRL_CLK_DIV_LD,Load the output divider valueWriting 1 to this bit will generate a load pulse to load the USART5 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value.." "0,1" newline bitfld.long 0x14 0.--1. "USART5_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (Others are reserved): 2'b00 - Divide by 1.." "0: Divide by 1 2'b01,?,2: Divide by 3 2'b11,?" line.long 0x18 "CFG0_USART6_CLK_CTRL,Selects the clock divider of the USART6 functional clock" bitfld.long 0x18 16. "USART6_CLK_CTRL_CLK_DIV_LD,Load the output divider valueWriting 1 to this bit will generate a load pulse to load the USART6 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value.." "0,1" newline bitfld.long 0x18 0.--1. "USART6_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (Others are reserved): 2'b00 - Divide by 1.." "0: Divide by 1 2'b01,?,2: Divide by 3 2'b11,?" line.long 0x1C "CFG0_USART7_CLK_CTRL,Selects the clock divider of the USART7 functional clock" bitfld.long 0x1C 16. "USART7_CLK_CTRL_CLK_DIV_LD,Load the output divider valueWriting 1 to this bit will generate a load pulse to load the USART7 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value.." "0,1" newline bitfld.long 0x1C 0.--1. "USART7_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (Others are reserved): 2'b00 - Divide by 1.." "0: Divide by 1 2'b01,?,2: Divide by 3 2'b11,?" line.long 0x20 "CFG0_USART8_CLK_CTRL,Selects the clock divider of the USART8 functional clock" bitfld.long 0x20 16. "USART8_CLK_CTRL_CLK_DIV_LD,Load the output divider valueWriting 1 to this bit will generate a load pulse to load the USART8 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value.." "0,1" newline bitfld.long 0x20 0.--1. "USART8_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (Others are reserved): 2'b00 - Divide by 1.." "0: Divide by 1 2'b01,?,2: Divide by 3 2'b11,?" line.long 0x24 "CFG0_USART9_CLK_CTRL,Selects the clock divider of the USART9 functional clock" bitfld.long 0x24 16. "USART9_CLK_CTRL_CLK_DIV_LD,Load the output divider valueWriting 1 to this bit will generate a load pulse to load the USART9 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value.." "0,1" newline bitfld.long 0x24 0.--1. "USART9_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (Others are reserved): 2'b00 - Divide by 1.." "0: Divide by 1 2'b01,?,2: Divide by 3 2'b11,?" rgroup.long 0x8200++0x13 line.long 0x0 "CFG0_MCASP0_CLKSEL,Selects the functional clock source for McASP0" bitfld.long 0x0 0.--2. "MCASP0_CLKSEL_AUXCLK_SEL,Selects the McASP0 auxclk clock source Reserved values default to HFOSC1_CLK Field values (Others are reserved): 3'b000 - MAIN_PLL4_HSDIV0_CLKOUT 3'b001 - MAIN_PLL2_HSDIV2_CLKOUT 3'b010 - 0 3'b011 - 0 3'b100.." "0: MAIN_PLL4_HSDIV0_CLKOUT 3'b001,?,?,?,4: ATCLK0 3'b101,?,6: ATCLK2 3'b111,?" line.long 0x4 "CFG0_MCASP1_CLKSEL,Selects the functional clock source for McASP1" bitfld.long 0x4 0.--2. "MCASP1_CLKSEL_AUXCLK_SEL,Selects the McASP1 auxclk clock source Reserved values default to HFOSC1_CLK Field values (Others are reserved): 3'b000 - MAIN_PLL4_HSDIV0_CLKOUT 3'b001 - MAIN_PLL2_HSDIV2_CLKOUT 3'b010 - 0 3'b011 - 0 3'b100.." "0: MAIN_PLL4_HSDIV0_CLKOUT 3'b001,?,?,?,4: ATCLK0 3'b101,?,6: ATCLK2 3'b111,?" line.long 0x8 "CFG0_MCASP2_CLKSEL,Selects the functional clock source for McASP2" bitfld.long 0x8 0.--2. "MCASP2_CLKSEL_AUXCLK_SEL,Selects the McASP2 auxclk clock source Reserved values default to HFOSC1_CLK Field values (Others are reserved): 3'b000 - MAIN_PLL4_HSDIV0_CLKOUT 3'b001 - MAIN_PLL2_HSDIV2_CLKOUT 3'b010 - 0 3'b011 - 0 3'b100.." "0: MAIN_PLL4_HSDIV0_CLKOUT 3'b001,?,?,?,4: ATCLK0 3'b101,?,6: ATCLK2 3'b111,?" line.long 0xC "CFG0_MCASP3_CLKSEL,Selects the functional clock source for McASP3" bitfld.long 0xC 0.--2. "MCASP3_CLKSEL_AUXCLK_SEL,Selects the McASP3 auxclk clock source Reserved values default to HFOSC1_CLK Field values (Others are reserved): 3'b000 - MAIN_PLL4_HSDIV0_CLKOUT 3'b001 - MAIN_PLL2_HSDIV2_CLKOUT 3'b010 - 0 3'b011 - 0 3'b100.." "0: MAIN_PLL4_HSDIV0_CLKOUT 3'b001,?,?,?,4: ATCLK0 3'b101,?,6: ATCLK2 3'b111,?" line.long 0x10 "CFG0_MCASP4_CLKSEL,Selects the functional clock source for McASP4" bitfld.long 0x10 0.--2. "MCASP4_CLKSEL_AUXCLK_SEL,Selects the McASP4 auxclk clock source Reserved values default to HFOSC1_CLK Field values (Others are reserved): 3'b000 - MAIN_PLL4_HSDIV0_CLKOUT 3'b001 - MAIN_PLL2_HSDIV2_CLKOUT 3'b010 - 0 3'b011 - 0 3'b100.." "0: MAIN_PLL4_HSDIV0_CLKOUT 3'b001,?,?,?,4: ATCLK0 3'b101,?,6: ATCLK2 3'b111,?" rgroup.long 0x8240++0x13 line.long 0x0 "CFG0_MCASP0_AHCLKSEL,Selects the AHCLKX and AHCLKR clock source for McASP0" hexmask.long.byte 0x0 8.--11. 1. "MCASP0_AHCLKSEL_AHCLKX_SEL,Selects the AHCLKX input source for McASP0 Field values (Others are reserved): 4'b0000 - HFOSC1_CLKOUT 4'b0001 - HFOSC0_CLKOUT 4'b0010 - AUDIO_EXT_REFCLK0_IN 4'b0011 - AUDIO_EXT_REFCLK1_IN 4'b0100 - 0.." newline hexmask.long.byte 0x0 0.--3. 1. "MCASP0_AHCLKSEL_AHCLKR_SEL,Selects the AHCLKR input source for McASP0 Field values (Others are reserved): 4'b0000 - HFOSC1_CLKOUT 4'b0001 - HFOSC0_CLKOUT 4'b0010 - AUDIO_EXT_REFCLK0_IN 4'b0011 - AUDIO_EXT_REFCLK1_IN 4'b0100 - 0.." line.long 0x4 "CFG0_MCASP1_AHCLKSEL,Selects the AHCLKX and AHCLKR clock source for McASP1" hexmask.long.byte 0x4 8.--11. 1. "MCASP1_AHCLKSEL_AHCLKX_SEL,Selects the AHCLKX input source for McASP1 Field values (Others are reserved): 4'b0000 - HFOSC1_CLKOUT 4'b0001 - HFOSC0_CLKOUT 4'b0010 - AUDIO_EXT_REFCLK0_IN 4'b0011 - AUDIO_EXT_REFCLK1_IN 4'b0100 - 0.." newline hexmask.long.byte 0x4 0.--3. 1. "MCASP1_AHCLKSEL_AHCLKR_SEL,Selects the AHCLKR input source for McASP1 Field values (Others are reserved): 4'b0000 - HFOSC1_CLKOUT 4'b0001 - HFOSC0_CLKOUT 4'b0010 - AUDIO_EXT_REFCLK0_IN 4'b0011 - AUDIO_EXT_REFCLK1_IN 4'b0100 - 0.." line.long 0x8 "CFG0_MCASP2_AHCLKSEL,Selects the AHCLKX and AHCLKR clock source for McASP2" hexmask.long.byte 0x8 8.--11. 1. "MCASP2_AHCLKSEL_AHCLKX_SEL,Selects the AHCLKX input source for McASP2 Field values (Others are reserved): 4'b0000 - HFOSC1_CLKOUT 4'b0001 - HFOSC0_CLKOUT 4'b0010 - AUDIO_EXT_REFCLK0_IN 4'b0011 - AUDIO_EXT_REFCLK1_IN 4'b0100 - 0.." newline hexmask.long.byte 0x8 0.--3. 1. "MCASP2_AHCLKSEL_AHCLKR_SEL,Selects the AHCLKR input source for McASP2 Field values (Others are reserved): 4'b0000 - HFOSC1_CLKOUT 4'b0001 - HFOSC0_CLKOUT 4'b0010 - AUDIO_EXT_REFCLK0_IN 4'b0011 - AUDIO_EXT_REFCLK1_IN 4'b0100 - 0.." line.long 0xC "CFG0_MCASP3_AHCLKSEL,Selects the AHCLKX and AHCLKR clock source for McASP3" hexmask.long.byte 0xC 8.--11. 1. "MCASP3_AHCLKSEL_AHCLKX_SEL,Selects the AHCLKX input source for McASP3 Field values (Others are reserved): 4'b0000 - HFOSC1_CLKOUT 4'b0001 - HFOSC0_CLKOUT 4'b0010 - AUDIO_EXT_REFCLK0_IN 4'b0011 - AUDIO_EXT_REFCLK1_IN 4'b0100 - 0.." newline hexmask.long.byte 0xC 0.--3. 1. "MCASP3_AHCLKSEL_AHCLKR_SEL,Selects the AHCLKR input source for McASP3 Field values (Others are reserved): 4'b0000 - HFOSC1_CLKOUT 4'b0001 - HFOSC0_CLKOUT 4'b0010 - AUDIO_EXT_REFCLK0_IN 4'b0011 - AUDIO_EXT_REFCLK1_IN 4'b0100 - 0.." line.long 0x10 "CFG0_MCASP4_AHCLKSEL,Selects the AHCLKX and AHCLKR clock source for McASP4" hexmask.long.byte 0x10 8.--11. 1. "MCASP4_AHCLKSEL_AHCLKX_SEL,Selects the AHCLKX input source for McASP4 Field values (Others are reserved): 4'b0000 - HFOSC1_CLKOUT 4'b0001 - HFOSC0_CLKOUT 4'b0010 - AUDIO_EXT_REFCLK0_IN 4'b0011 - AUDIO_EXT_REFCLK1_IN 4'b0100 - 0.." newline hexmask.long.byte 0x10 0.--3. 1. "MCASP4_AHCLKSEL_AHCLKR_SEL,Selects the AHCLKR input source for McASP4 Field values (Others are reserved): 4'b0000 - HFOSC1_CLKOUT 4'b0001 - HFOSC0_CLKOUT 4'b0010 - AUDIO_EXT_REFCLK0_IN 4'b0011 - AUDIO_EXT_REFCLK1_IN 4'b0100 - 0.." rgroup.long 0x82A0++0x23 line.long 0x0 "CFG0_ATL_BWS0_SEL,Selects the source of ATL Baseband Word Select 0" hexmask.long.byte 0x0 0.--4. 1. "ATL_BWS0_SEL_WD_SEL,BWS source signal Field values (Others are reserved): 5'b00000 - McASP0 AFSR Pin Input 5'b00001 - McASP1 AFSR Pin Input 5'b00010 - McASP2 AFSR Pin Input 5'b00011 - McASP3 AFSR Pin Input 5'b00100 - McASP4 AFSR Pin.." line.long 0x4 "CFG0_ATL_BWS1_SEL,Selects the source of ATL Baseband Word Select 1" hexmask.long.byte 0x4 0.--4. 1. "ATL_BWS1_SEL_WD_SEL,BWS source signal Field values (Others are reserved): 5'b00000 - McASP0 AFSR Pin Input 5'b00001 - McASP1 AFSR Pin Input 5'b00010 - McASP2 AFSR Pin Input 5'b00011 - McASP3 AFSR Pin Input 5'b00100 - McASP4 AFSR Pin.." line.long 0x8 "CFG0_ATL_BWS2_SEL,Selects the source of ATL Baseband Word Select 2" hexmask.long.byte 0x8 0.--4. 1. "ATL_BWS2_SEL_WD_SEL,BWS source signal Field values (Others are reserved): 5'b00000 - McASP0 AFSR Pin Input 5'b00001 - McASP1 AFSR Pin Input 5'b00010 - McASP2 AFSR Pin Input 5'b00011 - McASP3 AFSR Pin Input 5'b00100 - McASP4 AFSR Pin.." line.long 0xC "CFG0_ATL_BWS3_SEL,Selects the source of ATL Baseband Word Select 3" hexmask.long.byte 0xC 0.--4. 1. "ATL_BWS3_SEL_WD_SEL,BWS source signal Field values (Others are reserved): 5'b00000 - McASP0 AFSR Pin Input 5'b00001 - McASP1 AFSR Pin Input 5'b00010 - McASP2 AFSR Pin Input 5'b00011 - McASP3 AFSR Pin Input 5'b00100 - McASP4 AFSR Pin.." line.long 0x10 "CFG0_ATL_AWS0_SEL,Selects the source of ATL Audio Word Select 0" hexmask.long.byte 0x10 0.--4. 1. "ATL_AWS0_SEL_WD_SEL,AWS source signal Field values (Others are reserved): 5'b00000 - McASP0 AFSX Pin Input 5'b00001 - McASP1 AFSX Pin Input 5'b00010 - McASP2 AFSX Pin Input 5'b00011 - McASP3 AFSX Pin Input 5'b00100 - McASP4 AFSX Pin.." line.long 0x14 "CFG0_ATL_AWS1_SEL,Selects the source of ATL Audio Word Select 1" hexmask.long.byte 0x14 0.--4. 1. "ATL_AWS1_SEL_WD_SEL,AWS source signal Field values (Others are reserved): 5'b00000 - McASP0 AFSX Pin Input 5'b00001 - McASP1 AFSX Pin Input 5'b00010 - McASP2 AFSX Pin Input 5'b00011 - McASP3 AFSX Pin Input 5'b00100 - McASP4 AFSX Pin.." line.long 0x18 "CFG0_ATL_AWS2_SEL,Selects the source of ATL Audio Word Select 2" hexmask.long.byte 0x18 0.--4. 1. "ATL_AWS2_SEL_WD_SEL,AWS source signal Field values (Others are reserved): 5'b00000 - McASP0 AFSX Pin Input 5'b00001 - McASP1 AFSX Pin Input 5'b00010 - McASP2 AFSX Pin Input 5'b00011 - McASP3 AFSX Pin Input 5'b00100 - McASP4 AFSX Pin.." line.long 0x1C "CFG0_ATL_AWS3_SEL,Selects the source of ATL Audio Word Select 3" hexmask.long.byte 0x1C 0.--4. 1. "ATL_AWS3_SEL_WD_SEL,AWS source signal Field values (Others are reserved): 5'b00000 - McASP0 AFSX Pin Input 5'b00001 - McASP1 AFSX Pin Input 5'b00010 - McASP2 AFSX Pin Input 5'b00011 - McASP3 AFSX Pin Input 5'b00100 - McASP4 AFSX Pin.." line.long 0x20 "CFG0_ATL_CLKSEL,Selects the source of the ATL PCLK" hexmask.long.byte 0x20 0.--3. 1. "ATL_CLKSEL_PCLK_SEL,Selects the PCLK clock source Field values (Others are reserved): 3'b000 - MAIN_PLL4_HSDIV1_CLKOUT 3'b001 - MAIN_PLL2_HSDIV2_CLKOUT 3'b010 - 0 3'b011 - 0 3'b100 - MAIN_PLL0_HSDIV7_CLKOUT 3'b101 -.." rgroup.long 0x82E0++0x7 line.long 0x0 "CFG0_AUDIO_REFCLK0_CTRL,Selects the clock source for the AUDIO_EXT_REFCLK0 output" bitfld.long 0x0 15. "AUDIO_REFCLK0_CTRL_CLKOUT_EN,AUDIO_REFCLK 0 output enableThis bit is inverted to drive the active low output buffer enable 0 - AUDIO_EXT_REFCLK0 pin is configured as an input 1 - AUDIO_EXT_REFCLK0 pin is configured as an output" "0: AUDIO_EXT_REFCLK0 pin is configured as an input 1,?" newline hexmask.long.byte 0x0 0.--4. 1. "AUDIO_REFCLK0_CTRL_CLK_SEL,Clock source (default selects a tie-off of 0 for no output) Field values (Others are reserved): 5'b00000 - MCASP0 AHCLKR Output 5'b00001 - MCASP1 AHCLKR Output 5'b00010 - MCASP2 AHCLKR Output 5'b00011 - MCASP3.." line.long 0x4 "CFG0_AUDIO_REFCLK1_CTRL,Selects the clock source for the AUDIO_EXT_REFCLK1 output" bitfld.long 0x4 15. "AUDIO_REFCLK1_CTRL_CLKOUT_EN,AUDIO_REFCLK 1 output enableThis bit is inverted to drive the active low output buffer enable 0 - AUDIO_EXT_REFCLK1 pin is configured as an input 1 - AUDIO_EXT_REFCLK1 pin is configured as an output" "0: AUDIO_EXT_REFCLK1 pin is configured as an input 1,?" newline hexmask.long.byte 0x4 0.--4. 1. "AUDIO_REFCLK1_CTRL_CLK_SEL,Clock source (default selects a tie-off of 0 for no output) Field values (Others are reserved): 5'b00000 - MCASP0 AHCLKR Output 5'b00001 - MCASP1 AHCLKR Output 5'b00010 - MCASP2 AHCLKR Output 5'b00011 - MCASP3.." rgroup.long 0x8300++0x3 line.long 0x0 "CFG0_DPI0_CLK_CTRL,Selects the clock source for the DPI0 video output" bitfld.long 0x0 9. "DPI0_CLK_CTRL_SYNC_CLK_INVDIS,Clock edge select for DPI0 sync outputs 0 - HSYNC and VSYNC are driven on the falling edge of clk 1 - HSYNC and VSYNC are driven on the rising edge of clkNote that this value should align with the programmed value of the.." "0: HSYNC and VSYNC are driven on the falling edge..,?" newline bitfld.long 0x0 8. "DPI0_CLK_CTRL_DATA_CLK_INVDIS,Clock edge select for DPI0 data outputs 0 - DATA and DE are driven on the falling edge of clk 1 - DATA and DE are driven on the rising edge of clkNote that this value should align with the programmed value of the DSS.." "0: DATA and DE are driven on the falling edge of..,?" newline bitfld.long 0x0 0. "DPI0_CLK_CTRL_EXT_CLKSEL,Selects whether to use DSS PLL3 or an external pin as a DPI clock source. (See the J7AM Clock Specification for more details.) 0 - Use internal clock : MAIN_PLL19_HSDIV0_CLKOUT 1 - Use external clock : VOUT0_EXTPCLKIN" "0: Use internal clock : MAIN_PLL19_HSDIV0_CLKOUT 1,?" rgroup.long 0x8310++0x7 line.long 0x0 "CFG0_DPHY0_CLKSEL,Selects the clock source for the DSI0 transmit PHY" bitfld.long 0x0 0.--1. "DPHY0_CLKSEL_REF_CLK_SEL,DPHY reference clock source 2'b00 - HFOSC0_CLKOUT 2'b01 - HFOSC1_CLKOUT 2'b10 - MAIN_PLL3_HSDIV4_CLKOUT 2'b11 - MAIN_PLL2_HSDIV4_CLKOUT" "0: HFOSC0_CLKOUT 2'b01,?,2: MAIN_PLL3_HSDIV4_CLKOUT 2'b11,?" line.long 0x4 "CFG0_DPHY1_CLKSEL,Selects the clock source for the DSI1 transmit PHY" bitfld.long 0x4 0.--1. "DPHY1_CLKSEL_REF_CLK_SEL,DPHY reference clock source 2'b00 - HFOSC0_CLKOUT 2'b01 - HFOSC1_CLKOUT 2'b10 - MAIN_PLL3_HSDIV4_CLKOUT 2'b11 - MAIN_PLL2_HSDIV4_CLKOUT" "0: HFOSC0_CLKOUT 2'b01,?,2: MAIN_PLL3_HSDIV4_CLKOUT 2'b11,?" rgroup.long 0x8324++0xB line.long 0x0 "CFG0_DSS_DISPC0_CLKSEL1,Selects the clock source for DPI Lane 1 of Display Controller Instance 0" bitfld.long 0x0 0.--1. "DSS_DISPC0_CLKSEL1_DPI1_PCLK,DPI lane 1 pixel clock source Field values (Others are reserved): 2'b00 - MAIN_PLL17_HSDIV0_CLKOUT 2'b01 - MAIN_PLL19_HSDIV0_CLKOUT_EXTPCLKIN 2'b10 - MAIN_PLL19_HSDIV0_CLKOUT_EXTPCLKIN 2'b11 -.." "0: MAIN_PLL17_HSDIV0_CLKOUT 2'b01,?,2: MAIN_PLL19_HSDIV0_CLKOUT_EXTPCLKIN 2'b11,?" line.long 0x4 "CFG0_DSS_DISPC0_CLKSEL2,Selects the clock source for DPI Lane 2 of Display Controller Instance 0" bitfld.long 0x4 0. "DSS_DISPC0_CLKSEL2_DPI2_PCLK,DPI lane 2 pixel clock source Field values (Others are reserved): 1'b0 - MAIN_PLL16_HSDIV0_CLKOUT 1'b1 - MAIN_PLL17_HSDIV0_CLKOUT" "0: MAIN_PLL16_HSDIV0_CLKOUT 1'b1,?" line.long 0x8 "CFG0_DSS_DISPC0_CLKSEL3,Can also override the DPI Lane 0 and DPI Lane 2 clock source for certain values." bitfld.long 0x8 0.--2. "DSS_DISPC0_CLKSEL3_DPI3_PCLK,DPI lane 3 pixel clock sourceNote that values of 3'b1x1 also change the DPI lane 0 pixel clock source and values of 3'b11x change the DPI lane 2 pixel clock source Field values (Others are reserved): 3'b000 -.." "0: MAIN_PLL16_HSDIV1_CLKOUT 3'b001,?,2: MAIN_PLL17_HSDIV1_CLKOUT 3'b011,?,4: MAIN_PLL19_HSDIV0_CLKOUT_EXTPCLKIN 3'b101,?,6: MAIN_PLL19_HSDIV0_CLKOUT_EXTPCLKIN and dpi2_pclk..,?" rgroup.long 0x8350++0x3 line.long 0x0 "CFG0_EDP0_CLK_CTRL,Controls clock operation for Embedded Display Port 0" bitfld.long 0x0 8. "EDP0_CLK_CTRL_DSI_CLK_DYN_SWTCH_DIS,EDP0 DSI clock dynamic switch disable.This bit controls whether the EDP source clock is dynamically switched (to MAIN_PLL2_HSDIV7_CLKOUT) on a warm reset event. (See PLL Bypass Logic during Main WarmReset details in.." "0: Dynamic switching on warm reset is enabled 1,?" rgroup.long 0x8380++0x7 line.long 0x0 "CFG0_WWD0_CLKSEL,ARM MPU Cluster 0 Core 0 Windowed watchdog timer functional clock selection control" bitfld.long 0x0 31. "WWD0_CLKSEL_WRTLOCK,When set locks WWD0_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x0 0.--2. "WWD0_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control Field values (Others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - LFXOSC_CLKOUT 3'b010 - CLK_12M_RC 3'b011 - CLK_32K 3'b100 - HFOSC1_CLKOUT.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: HFOSC1_CLKOUT 3'b101,?,6: reserved,7: reserved" line.long 0x4 "CFG0_WWD1_CLKSEL,ARM MPU Cluster 0 Core 1 Windowed watchdog timer functional clock selection control" bitfld.long 0x4 31. "WWD1_CLKSEL_WRTLOCK,When set locks WWD1_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x4 0.--2. "WWD1_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control Field values (Others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - LFXOSC_CLKOUT 3'b010 - CLK_12M_RC 3'b011 - CLK_32K 3'b100 - HFOSC1_CLKOUT.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: HFOSC1_CLKOUT 3'b101,?,6: reserved,7: reserved" rgroup.long 0x83BC++0xB line.long 0x0 "CFG0_WWD15_CLKSEL,GPU Windowed watchdog timer functional clock selection control" bitfld.long 0x0 31. "WWD15_CLKSEL_WRTLOCK,When set locks WWD15_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x0 0.--2. "WWD15_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control Field values (Others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - LFXOSC_CLKOUT 3'b010 - CLK_12M_RC 3'b011 - CLK_32K 3'b100 - HFOSC1_CLKOUT.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: HFOSC1_CLKOUT 3'b101,?,6: reserved,7: reserved" line.long 0x4 "CFG0_WWD16_CLKSEL,C71x Core 0 Windowed watchdog timer functional clock selection control" bitfld.long 0x4 31. "WWD16_CLKSEL_WRTLOCK,When set locks WWD16_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x4 0.--2. "WWD16_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control Field values (Others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - LFXOSC_CLKOUT 3'b010 - CLK_12M_RC 3'b011 - CLK_32K 3'b100 - HFOSC1_CLKOUT.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: HFOSC1_CLKOUT 3'b101,?,6: reserved,7: reserved" line.long 0x8 "CFG0_WWD17_CLKSEL,C71x Core 1 Windowed watchdog timer functional clock selection control" bitfld.long 0x8 31. "WWD17_CLKSEL_WRTLOCK,When set locks WWD17_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x8 0.--2. "WWD17_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control Field values (Others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - LFXOSC_CLKOUT 3'b010 - CLK_12M_RC 3'b011 - CLK_32K 3'b100 - HFOSC1_CLKOUT.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: HFOSC1_CLKOUT 3'b101,?,6: reserved,7: reserved" rgroup.long 0x83F0++0x13 line.long 0x0 "CFG0_WWD28_CLKSEL,Main R5 Clstr0 Core0 Windowed watchdog timer functional clock selection control." bitfld.long 0x0 31. "WWD28_CLKSEL_WRTLOCK,When set locks WWD28_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x0 0.--2. "WWD28_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux controlThese bits are warm reset isolated to preserve R5 RTI clock selection. Field values (Others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - LFXOSC_CLKOUT.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: HFOSC1_CLKOUT 3'b101,?,6: reserved,7: reserved" line.long 0x4 "CFG0_WWD29_CLKSEL,Main R5 Clstr0 Core1 Windowed watchdog timer functional clock selection control." bitfld.long 0x4 31. "WWD29_CLKSEL_WRTLOCK,When set locks WWD29_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x4 0.--2. "WWD29_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux controlThese bits are warm reset isolated to preserve R5 RTI clock selection. Field values (Others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - LFXOSC_CLKOUT.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: HFOSC1_CLKOUT 3'b101,?,6: reserved,7: reserved" line.long 0x8 "CFG0_WWD30_CLKSEL,Main R5 Clstr1 Core0 Windowed watchdog timer functional clock selection control." bitfld.long 0x8 31. "WWD30_CLKSEL_WRTLOCK,When set locks WWD30_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x8 0.--2. "WWD30_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux controlThese bits are warm reset isolated to preserve R5 RTI clock selection. Field values (Others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - LFXOSC_CLKOUT.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: HFOSC1_CLKOUT 3'b101,?,6: reserved,7: reserved" line.long 0xC "CFG0_WWD31_CLKSEL,Main R5 Clstr1 Core1 Windowed watchdog timer functional clock selection control." bitfld.long 0xC 31. "WWD31_CLKSEL_WRTLOCK,When set locks WWD31_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0xC 0.--2. "WWD31_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux controlThese bits are warm reset isolated to preserve R5 RTI clock selection. Field values (Others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - LFXOSC_CLKOUT.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: HFOSC1_CLKOUT 3'b101,?,6: reserved,7: reserved" line.long 0x10 "CFG0_SERDES0_CLKSEL,Selects the clock source for Serdes0." bitfld.long 0x10 0.--1. "SERDES0_CLKSEL_CORE_REFCLK_SEL,Selects the source for the core_refclk input Field values (Others are reserved): 2'b00 - HFOSC0_CLKOUT 2'b01 - HFOSC1_CLKOUT 2'b10 - MAIN_PLL3_HSDIV4_CLKOUT 2'b11 - MAIN_PLL2_HSDIV4_CLKOUT" "0: HFOSC0_CLKOUT 2'b01,?,2: MAIN_PLL3_HSDIV4_CLKOUT 2'b11,?" rgroup.long 0x8480++0x47 line.long 0x0 "CFG0_MCAN0_CLKSEL,Controls the functional clock source MCAN0" bitfld.long 0x0 0.--1. "MCAN0_CLKSEL_CLK_SEL,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x4 "CFG0_MCAN1_CLKSEL,Controls the functional clock source MCAN1" bitfld.long 0x4 0.--1. "MCAN1_CLKSEL_CLK_SEL,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x8 "CFG0_MCAN2_CLKSEL,Controls the functional clock source MCAN2" bitfld.long 0x8 0.--1. "MCAN2_CLKSEL_CLK_SEL,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0xC "CFG0_MCAN3_CLKSEL,Controls the functional clock source MCAN3" bitfld.long 0xC 0.--1. "MCAN3_CLKSEL_CLK_SEL,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x10 "CFG0_MCAN4_CLKSEL,Controls the functional clock source MCAN4" bitfld.long 0x10 0.--1. "MCAN4_CLKSEL_CLK_SEL,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x14 "CFG0_MCAN5_CLKSEL,Controls the functional clock source MCAN5" bitfld.long 0x14 0.--1. "MCAN5_CLKSEL_CLK_SEL,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x18 "CFG0_MCAN6_CLKSEL,Controls the functional clock source MCAN6" bitfld.long 0x18 0.--1. "MCAN6_CLKSEL_CLK_SEL,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x1C "CFG0_MCAN7_CLKSEL,Controls the functional clock source MCAN7" bitfld.long 0x1C 0.--1. "MCAN7_CLKSEL_CLK_SEL,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x20 "CFG0_MCAN8_CLKSEL,Controls the functional clock source MCAN8" bitfld.long 0x20 0.--1. "MCAN8_CLKSEL_CLK_SEL,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x24 "CFG0_MCAN9_CLKSEL,Controls the functional clock source MCAN9" bitfld.long 0x24 0.--1. "MCAN9_CLKSEL_CLK_SEL,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x28 "CFG0_MCAN10_CLKSEL,Controls the functional clock source MCAN10" bitfld.long 0x28 0.--1. "MCAN10_CLKSEL_CLK_SEL,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x2C "CFG0_MCAN11_CLKSEL,Controls the functional clock source MCAN11" bitfld.long 0x2C 0.--1. "MCAN11_CLKSEL_CLK_SEL,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x30 "CFG0_MCAN12_CLKSEL,Controls the functional clock source MCAN12" bitfld.long 0x30 0.--1. "MCAN12_CLKSEL_CLK_SEL,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x34 "CFG0_MCAN13_CLKSEL,Controls the functional clock source MCAN13" bitfld.long 0x34 0.--1. "MCAN13_CLKSEL_CLK_SEL,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x38 "CFG0_MCAN14_CLKSEL,Controls the functional clock source MCAN14" bitfld.long 0x38 0.--1. "MCAN14_CLKSEL_CLK_SEL,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x3C "CFG0_MCAN15_CLKSEL,Controls the functional clock source MCAN15" bitfld.long 0x3C 0.--1. "MCAN15_CLKSEL_CLK_SEL,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x40 "CFG0_MCAN16_CLKSEL,Controls the functional clock source MCAN16" bitfld.long 0x40 0.--1. "MCAN16_CLKSEL_CLK_SEL,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x44 "CFG0_MCAN17_CLKSEL,Controls the functional clock source MCAN17" bitfld.long 0x44 0.--1. "MCAN17_CLKSEL_CLK_SEL,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" rgroup.long 0x9008++0x7 line.long 0x0 "CFG0_LOCK2_KICK0,This register must be written with the designated key value followed by a write to LOCK2_KICK1 with its key value before write-protected Partition 2 registers can be written." hexmask.long 0x0 0.--31. 1. "LOCK2_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK2_KICK1,This register must be written with the designated key value after a write to LOCK2_KICK0 with its key value before write-protected Partition 2 registers can be written." hexmask.long 0x4 0.--31. 1. "LOCK2_KICK1,- KICK1 component" rgroup.long 0x9100++0x33 line.long 0x0 "CFG0_CLAIMREG_P2_R0_READONLY," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P2_R0_READONLY,Claim bits for Partition 2" line.long 0x4 "CFG0_CLAIMREG_P2_R1_READONLY," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P2_R1_READONLY,Claim bits for Partition 2" line.long 0x8 "CFG0_CLAIMREG_P2_R2_READONLY," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P2_R2_READONLY,Claim bits for Partition 2" line.long 0xC "CFG0_CLAIMREG_P2_R3_READONLY," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P2_R3_READONLY,Claim bits for Partition 2" line.long 0x10 "CFG0_CLAIMREG_P2_R4_READONLY," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P2_R4_READONLY,Claim bits for Partition 2" line.long 0x14 "CFG0_CLAIMREG_P2_R5_READONLY," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P2_R5_READONLY,Claim bits for Partition 2" line.long 0x18 "CFG0_CLAIMREG_P2_R6_READONLY," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P2_R6_READONLY,Claim bits for Partition 2" line.long 0x1C "CFG0_CLAIMREG_P2_R7_READONLY," hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P2_R7_READONLY,Claim bits for Partition 2" line.long 0x20 "CFG0_CLAIMREG_P2_R8_READONLY," hexmask.long 0x20 0.--31. 1. "CLAIMREG_P2_R8_READONLY,Claim bits for Partition 2" line.long 0x24 "CFG0_CLAIMREG_P2_R9_READONLY," hexmask.long 0x24 0.--31. 1. "CLAIMREG_P2_R9_READONLY,Claim bits for Partition 2" line.long 0x28 "CFG0_CLAIMREG_P2_R10_READONLY," hexmask.long 0x28 0.--31. 1. "CLAIMREG_P2_R10_READONLY,Claim bits for Partition 2" line.long 0x2C "CFG0_CLAIMREG_P2_R11_READONLY," hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P2_R11_READONLY,Claim bits for Partition 2" line.long 0x30 "CFG0_CLAIMREG_P2_R12_READONLY," hexmask.long 0x30 0.--31. 1. "CLAIMREG_P2_R12_READONLY,Claim bits for Partition 2" rgroup.long 0xA000++0x7 line.long 0x0 "CFG0_OBSCLK0_CTRL_PROXY,This register controls which internal clock is made observable on the OBSCLK[2:0] output pins" bitfld.long 0x0 16. "OBSCLK0_CTRL_CLK_DIV_LD_PROXY,Load the output divider valueWriting 1 to this bit will generate a load pulse to load the OBSCLK0 divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "OBSCLK0_CTRL_CLK_DIV_PROXY,OBSCLK0 output dividerDivides the selected clock by clkdiv+1 for output to the OBSCLK[2:0] pins. Supports divide by 1 to 256 (default to 1). To load the new divider value the clk_div_ld bit must be cleared and then set to 1." newline hexmask.long.byte 0x0 0.--4. 1. "OBSCLK0_CTRL_CLK_SEL_PROXY,OBSCLK0 clock source selection.Selects the source of the clock to be divided by the OBSCLK0 divider and output on the OBSCLK[2:0] pins. Field values (Others are reserved): 5'b00000 - MAIN_PLL0_HSDIV0_CLKOUT 5'b00001 -.." line.long 0x4 "CFG0_OBSCLK1_CTRL_PROXY,This register controls which internal clock is made observable on the OBSCLK1_OUT internal clock signal" bitfld.long 0x4 0.--1. "OBSCLK1_CTRL_CLK_SEL_PROXY,OBSCLK1_OUT signal output clock source selection Field values (Others are reserved): 2'b00 - MAIN_PLL7_HSDIV0_CLKOUT / DIV4 2'b01 - MAIN_PLL8_HSDIV0_CLKOUT / DIV8 2'b10 - 0 2'b11 - 0" "0: MAIN_PLL7_HSDIV0_CLKOUT / DIV4 2'b01,?,?,?" rgroup.long 0xA010++0x3 line.long 0x0 "CFG0_CLKOUT_CTRL_PROXY,Enables and selects clock source of CPSW CLKOUT pin" bitfld.long 0x0 4. "CLKOUT_CTRL_CLK_EN_PROXY,When set enables CLKOUT output" "0,1" newline bitfld.long 0x0 0. "CLKOUT_CTRL_CLK_SEL_PROXY,Selects CLKOUT clock source 1'b0 - RGMII_MHZ_50_CLK (50 MHz) 1'b1 -RGMII_MHZ_50_CLK_DIV2 (25 MHz)" "0: RGMII_MHZ_50_CLK,1: RGMII_MHZ_50_CLK_DIV2" rgroup.long 0xA030++0x3 line.long 0x0 "CFG0_GTC_CLKSEL_PROXY,Selects the timebase clock source for the Global Timebase Counter" hexmask.long.byte 0x0 0.--3. 1. "GTC_CLKSEL_CLK_SEL_PROXY,Selects the GTC timebase clock source Field values (Others are reserved): 4'b0000 - MAIN_PLL3_HSDIV1_CLKOUT 4'b0001 - MAIN_PLL0_HSDIV6_CLKOUT 4'b0010 - MCU_CPTS_REF_CLK (pin) 4'b0011 - CPTS_RFT_CLK (pin).." rgroup.long 0xA03C++0x3 line.long 0x0 "CFG0_EFUSE_CLKSEL_PROXY,Selects the functional clock source for the MAIN domain eFuse Controller" bitfld.long 0x0 0. "EFUSE_CLKSEL_CLK_SEL_PROXY,Selects the clock source Field values (Others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - MAIN_SYSCLK0 / 4" "0: HFOSC0_CLKOUT 1'b1,?" rgroup.long 0xA074++0x3 line.long 0x0 "CFG0_PCIE_REFCLK1_CLKSEL_PROXY,PCIE_REFCLK1 P/N are driven by ACSPCIE0 PAD 0" bitfld.long 0x0 8. "PCIE_REFCLK1_CLKSEL_OUT_CLK_EN_PROXY,Enables the output of the ACSPCIE buffer to drive the PCIE1 REFCLK P/N pins" "0,1" newline bitfld.long 0x0 0.--1. "PCIE_REFCLK1_CLKSEL_OUT_CLKSEL_PROXY,Selects the PCIE1 REFCLK output clock source.Controls the ACSPCIE0 buffer PAD0 clock mux. Field values (Others are reserved): 2'b00 - SERDES0_REF_DER_OUT_CLK 2'b01 - MAIN_PLL2_HSDIV4_CLKOUT 2'b10 -.." "0: SERDES0_REF_DER_OUT_CLK 2'b01,?,2: SERDES0_REF_OUT_CLK 2'b11,?" rgroup.long 0xA084++0x3 line.long 0x0 "CFG0_PCIE1_CLKSEL_PROXY,Selects PCIe1 functional clock sources" hexmask.long.byte 0x0 0.--3. 1. "PCIE1_CLKSEL_CPTS_CLKSEL_PROXY,Selects the clock source for the PCIE1 Common Platform Time Stamp module Field values (Others are reserved): 4'b0000 - MAIN_PLL3_HSDIV1_CLKOUT 4'b0001 - MAIN_PLL0_HSDIV6_CLKOUT 4'b0010 - MCU_CPTS_REF_CLK (pin).." rgroup.long 0xA094++0x7 line.long 0x0 "CFG0_CPSW2_CLKSEL_PROXY,Selects the 2 port CP Switch clock sources" hexmask.long.byte 0x0 0.--3. 1. "CPSW2_CLKSEL_CPTS_CLKSEL_PROXY,Selects the clock source for the CPSW2G Ethernet switch Common Platform Time Stamp module Field values (Others are reserved): 4'b0000 - MAIN_PLL3_HSDIV1_CLKOUT 4'b0001 - MAIN_PLL0_HSDIV6_CLKOUT 4'b0010 -.." line.long 0x4 "CFG0_NAVSS_CLKSEL_PROXY,Selects the clock source for the NavSS Subsystem" hexmask.long.byte 0x4 0.--3. 1. "NAVSS_CLKSEL_CPTS_CLKSEL_PROXY,Selects the clock source for the SoC] Common Platform Time Stamp module located within the Nav Subsystem Field values (Others are reserved): 4'b0000 - MAIN_PLL3_HSDIV1_CLKOUT 4'b0001 - MAIN_PLL0_HSDIV6_CLKOUT.." rgroup.long 0xA0B0++0x7 line.long 0x0 "CFG0_EMMC0_CLKSEL_PROXY,Selects the functional clock source for 8-bit eMMC0" bitfld.long 0x0 0.--1. "EMMC0_CLKSEL_CLK_SEL_PROXY,eMMC XIN_CLK selection 2'b00 - MAIN_PLL0_HSDIV2_CLKOUT 2'b01 - MAIN_PLL1_HSDIV2_CLKOUT 2'b10 - MAIN_PLL2_HSDIV2_CLKOUT 2'b11 - MAIN_PLL3_HSDIV2_CLKOUT" "0: MAIN_PLL0_HSDIV2_CLKOUT 2'b01,?,2: MAIN_PLL2_HSDIV2_CLKOUT 2'b11,?" line.long 0x4 "CFG0_EMMC1_CLKSEL_PROXY,Selects the functional clock source for 4-bit eMMC1" bitfld.long 0x4 16. "EMMC1_CLKSEL_LB_CLKSEL_PROXY,eMMC Loopback clock selection 1'b0 - Loopback clock from MMC1_CLKLB pad 1'b1 - Loopback clock from MMC1_CLK pin" "0: Loopback clock from MMC1_CLKLB pad 1'b1,?" newline bitfld.long 0x4 0.--1. "EMMC1_CLKSEL_CLK_SEL_PROXY,eMMC XIN_CLK selection 2'b00 - MAIN_PLL0_HSDIV2_CLKOUT 2'b01 - MAIN_PLL1_HSDIV2_CLKOUT 2'b10 - MAIN_PLL2_HSDIV2_CLKOUT 2'b11 - MAIN_PLL3_HSDIV2_CLKOUT" "0: MAIN_PLL0_HSDIV2_CLKOUT 2'b01,?,2: MAIN_PLL2_HSDIV2_CLKOUT 2'b11,?" rgroup.long 0xA0D0++0x3 line.long 0x0 "CFG0_GPMC_CLKSEL_PROXY,Selects the bus and functional clock source for the GPMC module. This allows the GPMC to run asynchronously to the bus fabric in order to optimize parallel port performance." bitfld.long 0x0 0.--1. "GPMC_CLKSEL_CLK_SEL_PROXY,Selects the GPMC clock source 2'b00 - MAIN_PLL0_HSDIV3_CLKOUT 2'b01 - MAIN_PLL2_HSDIV1_CLKOUT / 6 2'b10 - MAIN_PLL2_HSDIV1_CLKOUT / 4 2'b11 - MAIN_SYSCLK0 / 4" "0: MAIN_PLL0_HSDIV3_CLKOUT 2'b01,?,2: MAIN_PLL2_HSDIV1_CLKOUT / 4 2'b11,?" rgroup.long 0xA0E0++0x3 line.long 0x0 "CFG0_USB0_CLKSEL_PROXY,Selects the functional clock sources for USB0" bitfld.long 0x0 0. "USB0_CLKSEL_REFCLK_SEL_PROXY,Selects the clock source for the USB0 ref_clk. 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" rgroup.long 0xA0F0++0x3 line.long 0x0 "CFG0_VPAC_CLKSEL_PROXY,Selects the functional clock sources for VPAC0" bitfld.long 0x0 0. "VPAC_CLKSEL_CLK_SEL_PROXY,VPAC clock selection 1'b0 - MAIN_PLL25_HSDIV1_CLKOUT 1'b1 - MAIN_PLL2_HSDIV1_CLKOUT" "0: MAIN_PLL25_HSDIV1_CLKOUT 1'b1,?" rgroup.long 0xA100++0x4F line.long 0x0 "CFG0_TIMER0_CLKSEL_PROXY,Timer0 functional clock selection control" hexmask.long.byte 0x0 0.--3. 1. "TIMER0_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT.." line.long 0x4 "CFG0_TIMER1_CLKSEL_PROXY,Timer1 functional clock selection control" hexmask.long.byte 0x4 0.--3. 1. "TIMER1_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT.." line.long 0x8 "CFG0_TIMER2_CLKSEL_PROXY,Timer2 functional clock selection control" hexmask.long.byte 0x8 0.--3. 1. "TIMER2_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT.." line.long 0xC "CFG0_TIMER3_CLKSEL_PROXY,Timer3 functional clock selection control" hexmask.long.byte 0xC 0.--3. 1. "TIMER3_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT.." line.long 0x10 "CFG0_TIMER4_CLKSEL_PROXY,Timer4 functional clock selection control" hexmask.long.byte 0x10 0.--3. 1. "TIMER4_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT.." line.long 0x14 "CFG0_TIMER5_CLKSEL_PROXY,Timer5 functional clock selection control" hexmask.long.byte 0x14 0.--3. 1. "TIMER5_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT.." line.long 0x18 "CFG0_TIMER6_CLKSEL_PROXY,Timer6 functional clock selection control" hexmask.long.byte 0x18 0.--3. 1. "TIMER6_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT.." line.long 0x1C "CFG0_TIMER7_CLKSEL_PROXY,Timer7 functional clock selection control" hexmask.long.byte 0x1C 0.--3. 1. "TIMER7_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT.." line.long 0x20 "CFG0_TIMER8_CLKSEL_PROXY,Timer8 functional clock selection control" hexmask.long.byte 0x20 0.--3. 1. "TIMER8_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT.." line.long 0x24 "CFG0_TIMER9_CLKSEL_PROXY,Timer9 functional clock selection control" hexmask.long.byte 0x24 0.--3. 1. "TIMER9_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT.." line.long 0x28 "CFG0_TIMER10_CLKSEL_PROXY,Timer10 functional clock selection control" hexmask.long.byte 0x28 0.--3. 1. "TIMER10_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT.." line.long 0x2C "CFG0_TIMER11_CLKSEL_PROXY,Timer11 functional clock selection control" hexmask.long.byte 0x2C 0.--3. 1. "TIMER11_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT.." line.long 0x30 "CFG0_TIMER12_CLKSEL_PROXY,Timer12 functional clock selection control" hexmask.long.byte 0x30 0.--3. 1. "TIMER12_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT.." line.long 0x34 "CFG0_TIMER13_CLKSEL_PROXY,Timer13 functional clock selection control" hexmask.long.byte 0x34 0.--3. 1. "TIMER13_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT.." line.long 0x38 "CFG0_TIMER14_CLKSEL_PROXY,Timer14 functional clock selection control" hexmask.long.byte 0x38 0.--3. 1. "TIMER14_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT.." line.long 0x3C "CFG0_TIMER15_CLKSEL_PROXY,Timer15 functional clock selection control" hexmask.long.byte 0x3C 0.--3. 1. "TIMER15_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT.." line.long 0x40 "CFG0_TIMER16_CLKSEL_PROXY,Timer16 functional clock selection control" bitfld.long 0x40 23. "TIMER16_CLKSEL_AFS_SRC_EN_PROXY,Enable AFS source mux output as the Timer clock source. Note that for TIMER17 and TIMER19 this selection will be overridden if cascade_en in the associated TIMERn_CTRL register is set. 0 - Use functional clock selected.." "0: Use functional clock selected by clk_sel value 1,?" newline hexmask.long.byte 0x40 16.--19. 1. "TIMER16_CLKSEL_AFS_SRC_SEL_PROXY,Selects the ASFR/AFSX input to use as a timer clock when afs_src_en is set. Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX.." newline hexmask.long.byte 0x40 0.--3. 1. "TIMER16_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT.." line.long 0x44 "CFG0_TIMER17_CLKSEL_PROXY,Timer17 functional clock selection control" bitfld.long 0x44 23. "TIMER17_CLKSEL_AFS_SRC_EN_PROXY,Enable AFS source mux output as the Timer clock source. Note that for TIMER17 and TIMER19 this selection will be overridden if cascade_en in the associated TIMERn_CTRL register is set. 0 - Use functional clock selected.." "0: Use functional clock selected by clk_sel value 1,?" newline hexmask.long.byte 0x44 16.--19. 1. "TIMER17_CLKSEL_AFS_SRC_SEL_PROXY,Selects the ASFR/AFSX input to use as a timer clock when afs_src_en is set. Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX.." newline hexmask.long.byte 0x44 0.--3. 1. "TIMER17_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT.." line.long 0x48 "CFG0_TIMER18_CLKSEL_PROXY,Timer18 functional clock selection control" bitfld.long 0x48 23. "TIMER18_CLKSEL_AFS_SRC_EN_PROXY,Enable AFS source mux output as the Timer clock source. Note that for TIMER17 and TIMER19 this selection will be overridden if cascade_en in the associated TIMERn_CTRL register is set. 0 - Use functional clock selected.." "0: Use functional clock selected by clk_sel value 1,?" newline hexmask.long.byte 0x48 16.--19. 1. "TIMER18_CLKSEL_AFS_SRC_SEL_PROXY,Selects the ASFR/AFSX input to use as a timer clock when afs_src_en is set. Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX.." newline hexmask.long.byte 0x48 0.--3. 1. "TIMER18_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT.." line.long 0x4C "CFG0_TIMER19_CLKSEL_PROXY,Timer19 functional clock selection control" bitfld.long 0x4C 23. "TIMER19_CLKSEL_AFS_SRC_EN_PROXY,Enable AFS source mux output as the Timer clock source. Note that for TIMER17 and TIMER19 this selection will be overridden if cascade_en in the associated TIMERn_CTRL register is set. 0 - Use functional clock selected.." "0: Use functional clock selected by clk_sel value 1,?" newline hexmask.long.byte 0x4C 16.--19. 1. "TIMER19_CLKSEL_AFS_SRC_SEL_PROXY,Selects the ASFR/AFSX input to use as a timer clock when afs_src_en is set. Field values (Others are reserved): 4'b0000 - McASP0_AFSR 4'b0001 - McASP0_AFSX 4'b0010 - McASP1_AFSR 4'b0011 - McASP1_AFSX.." newline hexmask.long.byte 0x4C 0.--3. 1. "TIMER19_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (Others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - HFOSC1_CLKOUT 4'b0010 - MAIN_PLL0_HSDIV1_CLKOUT.." rgroup.long 0xA190++0xF line.long 0x0 "CFG0_SPI0_CLKSEL_PROXY,SPI0 clock control" bitfld.long 0x0 16. "SPI0_CLKSEL_MSTR_LB_CLKSEL_PROXY,Master mode receive capture clock loopback selection 1'b0 - Internal clock loopback 1'b1 - Loopback from pad" "0: Internal clock loopback 1'b1,?" line.long 0x4 "CFG0_SPI1_CLKSEL_PROXY,SPI1 clock control" bitfld.long 0x4 16. "SPI1_CLKSEL_MSTR_LB_CLKSEL_PROXY,Master mode receive capture clock loopback selection 1'b0 - Internal clock loopback 1'b1 - Loopback from pad" "0: Internal clock loopback 1'b1,?" line.long 0x8 "CFG0_SPI2_CLKSEL_PROXY,SPI2 clock control" bitfld.long 0x8 16. "SPI2_CLKSEL_MSTR_LB_CLKSEL_PROXY,Master mode receive capture clock loopback selection 1'b0 - Internal clock loopback 1'b1 - Loopback from pad" "0: Internal clock loopback 1'b1,?" line.long 0xC "CFG0_SPI3_CLKSEL_PROXY,SPI3 clock control" bitfld.long 0xC 16. "SPI3_CLKSEL_MSTR_LB_CLKSEL_PROXY,Master mode receive capture clock loopback selection 1'b0 - Internal clock loopback 1'b1 - Loopback from pad" "0: Internal clock loopback 1'b1,?" rgroup.long 0xA1A4++0xB line.long 0x0 "CFG0_SPI5_CLKSEL_PROXY,SPI5 clock control" bitfld.long 0x0 16. "SPI5_CLKSEL_MSTR_LB_CLKSEL_PROXY,Master mode receive capture clock loopback selection 1'b0 - Internal clock loopback 1'b1 - Loopback from pad" "0: Internal clock loopback 1'b1,?" line.long 0x4 "CFG0_SPI6_CLKSEL_PROXY,SPI6 clock control" bitfld.long 0x4 16. "SPI6_CLKSEL_MSTR_LB_CLKSEL_PROXY,Master mode receive capture clock loopback selection 1'b0 - Internal clock loopback 1'b1 - Loopback from pad" "0: Internal clock loopback 1'b1,?" line.long 0x8 "CFG0_SPI7_CLKSEL_PROXY,SPI7 clock control" bitfld.long 0x8 16. "SPI7_CLKSEL_MSTR_LB_CLKSEL_PROXY,Master mode receive capture clock loopback selection 1'b0 - Internal clock loopback 1'b1 - Loopback from pad" "0: Internal clock loopback 1'b1,?" rgroup.long 0xA1C0++0x27 line.long 0x0 "CFG0_USART0_CLK_CTRL_PROXY,Selects the clock divider of the USART0 functional clock" bitfld.long 0x0 16. "USART0_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider valueWriting 1 to this bit will generate a load pulse to load the USART0 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div.." "0,1" newline bitfld.long 0x0 0.--1. "USART0_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (Others are reserved): 2'b00 - Divide.." "0: Divide by 1 2'b01,?,2: Divide by 3 2'b11,?" line.long 0x4 "CFG0_USART1_CLK_CTRL_PROXY,Selects the clock divider of the USART1 functional clock" bitfld.long 0x4 16. "USART1_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider valueWriting 1 to this bit will generate a load pulse to load the USART1 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div.." "0,1" newline bitfld.long 0x4 0.--1. "USART1_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (Others are reserved): 2'b00 - Divide.." "0: Divide by 1 2'b01,?,2: Divide by 3 2'b11,?" line.long 0x8 "CFG0_USART2_CLK_CTRL_PROXY,Selects the clock divider of the USART2 functional clock" bitfld.long 0x8 16. "USART2_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider valueWriting 1 to this bit will generate a load pulse to load the USART2 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div.." "0,1" newline bitfld.long 0x8 0.--1. "USART2_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (Others are reserved): 2'b00 - Divide.." "0: Divide by 1 2'b01,?,2: Divide by 3 2'b11,?" line.long 0xC "CFG0_USART3_CLK_CTRL_PROXY,Selects the clock divider of the USART3 functional clock" bitfld.long 0xC 16. "USART3_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider valueWriting 1 to this bit will generate a load pulse to load the USART3 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div.." "0,1" newline bitfld.long 0xC 0.--1. "USART3_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (Others are reserved): 2'b00 - Divide.." "0: Divide by 1 2'b01,?,2: Divide by 3 2'b11,?" line.long 0x10 "CFG0_USART4_CLK_CTRL_PROXY,Selects the clock divider of the USART4 functional clock" bitfld.long 0x10 16. "USART4_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider valueWriting 1 to this bit will generate a load pulse to load the USART4 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div.." "0,1" newline bitfld.long 0x10 0.--1. "USART4_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (Others are reserved): 2'b00 - Divide.." "0: Divide by 1 2'b01,?,2: Divide by 3 2'b11,?" line.long 0x14 "CFG0_USART5_CLK_CTRL_PROXY,Selects the clock divider of the USART5 functional clock" bitfld.long 0x14 16. "USART5_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider valueWriting 1 to this bit will generate a load pulse to load the USART5 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div.." "0,1" newline bitfld.long 0x14 0.--1. "USART5_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (Others are reserved): 2'b00 - Divide.." "0: Divide by 1 2'b01,?,2: Divide by 3 2'b11,?" line.long 0x18 "CFG0_USART6_CLK_CTRL_PROXY,Selects the clock divider of the USART6 functional clock" bitfld.long 0x18 16. "USART6_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider valueWriting 1 to this bit will generate a load pulse to load the USART6 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div.." "0,1" newline bitfld.long 0x18 0.--1. "USART6_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (Others are reserved): 2'b00 - Divide.." "0: Divide by 1 2'b01,?,2: Divide by 3 2'b11,?" line.long 0x1C "CFG0_USART7_CLK_CTRL_PROXY,Selects the clock divider of the USART7 functional clock" bitfld.long 0x1C 16. "USART7_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider valueWriting 1 to this bit will generate a load pulse to load the USART7 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div.." "0,1" newline bitfld.long 0x1C 0.--1. "USART7_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (Others are reserved): 2'b00 - Divide.." "0: Divide by 1 2'b01,?,2: Divide by 3 2'b11,?" line.long 0x20 "CFG0_USART8_CLK_CTRL_PROXY,Selects the clock divider of the USART8 functional clock" bitfld.long 0x20 16. "USART8_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider valueWriting 1 to this bit will generate a load pulse to load the USART8 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div.." "0,1" newline bitfld.long 0x20 0.--1. "USART8_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (Others are reserved): 2'b00 - Divide.." "0: Divide by 1 2'b01,?,2: Divide by 3 2'b11,?" line.long 0x24 "CFG0_USART9_CLK_CTRL_PROXY,Selects the clock divider of the USART9 functional clock" bitfld.long 0x24 16. "USART9_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider valueWriting 1 to this bit will generate a load pulse to load the USART9 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div.." "0,1" newline bitfld.long 0x24 0.--1. "USART9_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (Others are reserved): 2'b00 - Divide.." "0: Divide by 1 2'b01,?,2: Divide by 3 2'b11,?" rgroup.long 0xA200++0x13 line.long 0x0 "CFG0_MCASP0_CLKSEL_PROXY,Selects the functional clock source for McASP0" bitfld.long 0x0 0.--2. "MCASP0_CLKSEL_AUXCLK_SEL_PROXY,Selects the McASP0 auxclk clock source Reserved values default to HFOSC1_CLK Field values (Others are reserved): 3'b000 - MAIN_PLL4_HSDIV0_CLKOUT 3'b001 - MAIN_PLL2_HSDIV2_CLKOUT 3'b010 - 0 3'b011 - 0.." "0: MAIN_PLL4_HSDIV0_CLKOUT 3'b001,?,?,?,4: ATCLK0 3'b101,?,6: ATCLK2 3'b111,?" line.long 0x4 "CFG0_MCASP1_CLKSEL_PROXY,Selects the functional clock source for McASP1" bitfld.long 0x4 0.--2. "MCASP1_CLKSEL_AUXCLK_SEL_PROXY,Selects the McASP1 auxclk clock source Reserved values default to HFOSC1_CLK Field values (Others are reserved): 3'b000 - MAIN_PLL4_HSDIV0_CLKOUT 3'b001 - MAIN_PLL2_HSDIV2_CLKOUT 3'b010 - 0 3'b011 - 0.." "0: MAIN_PLL4_HSDIV0_CLKOUT 3'b001,?,?,?,4: ATCLK0 3'b101,?,6: ATCLK2 3'b111,?" line.long 0x8 "CFG0_MCASP2_CLKSEL_PROXY,Selects the functional clock source for McASP2" bitfld.long 0x8 0.--2. "MCASP2_CLKSEL_AUXCLK_SEL_PROXY,Selects the McASP2 auxclk clock source Reserved values default to HFOSC1_CLK Field values (Others are reserved): 3'b000 - MAIN_PLL4_HSDIV0_CLKOUT 3'b001 - MAIN_PLL2_HSDIV2_CLKOUT 3'b010 - 0 3'b011 - 0.." "0: MAIN_PLL4_HSDIV0_CLKOUT 3'b001,?,?,?,4: ATCLK0 3'b101,?,6: ATCLK2 3'b111,?" line.long 0xC "CFG0_MCASP3_CLKSEL_PROXY,Selects the functional clock source for McASP3" bitfld.long 0xC 0.--2. "MCASP3_CLKSEL_AUXCLK_SEL_PROXY,Selects the McASP3 auxclk clock source Reserved values default to HFOSC1_CLK Field values (Others are reserved): 3'b000 - MAIN_PLL4_HSDIV0_CLKOUT 3'b001 - MAIN_PLL2_HSDIV2_CLKOUT 3'b010 - 0 3'b011 - 0.." "0: MAIN_PLL4_HSDIV0_CLKOUT 3'b001,?,?,?,4: ATCLK0 3'b101,?,6: ATCLK2 3'b111,?" line.long 0x10 "CFG0_MCASP4_CLKSEL_PROXY,Selects the functional clock source for McASP4" bitfld.long 0x10 0.--2. "MCASP4_CLKSEL_AUXCLK_SEL_PROXY,Selects the McASP4 auxclk clock source Reserved values default to HFOSC1_CLK Field values (Others are reserved): 3'b000 - MAIN_PLL4_HSDIV0_CLKOUT 3'b001 - MAIN_PLL2_HSDIV2_CLKOUT 3'b010 - 0 3'b011 - 0.." "0: MAIN_PLL4_HSDIV0_CLKOUT 3'b001,?,?,?,4: ATCLK0 3'b101,?,6: ATCLK2 3'b111,?" rgroup.long 0xA240++0x13 line.long 0x0 "CFG0_MCASP0_AHCLKSEL_PROXY,Selects the AHCLKX and AHCLKR clock source for McASP0" hexmask.long.byte 0x0 8.--11. 1. "MCASP0_AHCLKSEL_AHCLKX_SEL_PROXY,Selects the AHCLKX input source for McASP0 Field values (Others are reserved): 4'b0000 - HFOSC1_CLKOUT 4'b0001 - HFOSC0_CLKOUT 4'b0010 - AUDIO_EXT_REFCLK0_IN 4'b0011 - AUDIO_EXT_REFCLK1_IN 4'b0100 - 0.." newline hexmask.long.byte 0x0 0.--3. 1. "MCASP0_AHCLKSEL_AHCLKR_SEL_PROXY,Selects the AHCLKR input source for McASP0 Field values (Others are reserved): 4'b0000 - HFOSC1_CLKOUT 4'b0001 - HFOSC0_CLKOUT 4'b0010 - AUDIO_EXT_REFCLK0_IN 4'b0011 - AUDIO_EXT_REFCLK1_IN 4'b0100 - 0.." line.long 0x4 "CFG0_MCASP1_AHCLKSEL_PROXY,Selects the AHCLKX and AHCLKR clock source for McASP1" hexmask.long.byte 0x4 8.--11. 1. "MCASP1_AHCLKSEL_AHCLKX_SEL_PROXY,Selects the AHCLKX input source for McASP1 Field values (Others are reserved): 4'b0000 - HFOSC1_CLKOUT 4'b0001 - HFOSC0_CLKOUT 4'b0010 - AUDIO_EXT_REFCLK0_IN 4'b0011 - AUDIO_EXT_REFCLK1_IN 4'b0100 - 0.." newline hexmask.long.byte 0x4 0.--3. 1. "MCASP1_AHCLKSEL_AHCLKR_SEL_PROXY,Selects the AHCLKR input source for McASP1 Field values (Others are reserved): 4'b0000 - HFOSC1_CLKOUT 4'b0001 - HFOSC0_CLKOUT 4'b0010 - AUDIO_EXT_REFCLK0_IN 4'b0011 - AUDIO_EXT_REFCLK1_IN 4'b0100 - 0.." line.long 0x8 "CFG0_MCASP2_AHCLKSEL_PROXY,Selects the AHCLKX and AHCLKR clock source for McASP2" hexmask.long.byte 0x8 8.--11. 1. "MCASP2_AHCLKSEL_AHCLKX_SEL_PROXY,Selects the AHCLKX input source for McASP2 Field values (Others are reserved): 4'b0000 - HFOSC1_CLKOUT 4'b0001 - HFOSC0_CLKOUT 4'b0010 - AUDIO_EXT_REFCLK0_IN 4'b0011 - AUDIO_EXT_REFCLK1_IN 4'b0100 - 0.." newline hexmask.long.byte 0x8 0.--3. 1. "MCASP2_AHCLKSEL_AHCLKR_SEL_PROXY,Selects the AHCLKR input source for McASP2 Field values (Others are reserved): 4'b0000 - HFOSC1_CLKOUT 4'b0001 - HFOSC0_CLKOUT 4'b0010 - AUDIO_EXT_REFCLK0_IN 4'b0011 - AUDIO_EXT_REFCLK1_IN 4'b0100 - 0.." line.long 0xC "CFG0_MCASP3_AHCLKSEL_PROXY,Selects the AHCLKX and AHCLKR clock source for McASP3" hexmask.long.byte 0xC 8.--11. 1. "MCASP3_AHCLKSEL_AHCLKX_SEL_PROXY,Selects the AHCLKX input source for McASP3 Field values (Others are reserved): 4'b0000 - HFOSC1_CLKOUT 4'b0001 - HFOSC0_CLKOUT 4'b0010 - AUDIO_EXT_REFCLK0_IN 4'b0011 - AUDIO_EXT_REFCLK1_IN 4'b0100 - 0.." newline hexmask.long.byte 0xC 0.--3. 1. "MCASP3_AHCLKSEL_AHCLKR_SEL_PROXY,Selects the AHCLKR input source for McASP3 Field values (Others are reserved): 4'b0000 - HFOSC1_CLKOUT 4'b0001 - HFOSC0_CLKOUT 4'b0010 - AUDIO_EXT_REFCLK0_IN 4'b0011 - AUDIO_EXT_REFCLK1_IN 4'b0100 - 0.." line.long 0x10 "CFG0_MCASP4_AHCLKSEL_PROXY,Selects the AHCLKX and AHCLKR clock source for McASP4" hexmask.long.byte 0x10 8.--11. 1. "MCASP4_AHCLKSEL_AHCLKX_SEL_PROXY,Selects the AHCLKX input source for McASP4 Field values (Others are reserved): 4'b0000 - HFOSC1_CLKOUT 4'b0001 - HFOSC0_CLKOUT 4'b0010 - AUDIO_EXT_REFCLK0_IN 4'b0011 - AUDIO_EXT_REFCLK1_IN 4'b0100 - 0.." newline hexmask.long.byte 0x10 0.--3. 1. "MCASP4_AHCLKSEL_AHCLKR_SEL_PROXY,Selects the AHCLKR input source for McASP4 Field values (Others are reserved): 4'b0000 - HFOSC1_CLKOUT 4'b0001 - HFOSC0_CLKOUT 4'b0010 - AUDIO_EXT_REFCLK0_IN 4'b0011 - AUDIO_EXT_REFCLK1_IN 4'b0100 - 0.." rgroup.long 0xA2A0++0x23 line.long 0x0 "CFG0_ATL_BWS0_SEL_PROXY,Selects the source of ATL Baseband Word Select 0" hexmask.long.byte 0x0 0.--4. 1. "ATL_BWS0_SEL_WD_SEL_PROXY,BWS source signal Field values (Others are reserved): 5'b00000 - McASP0 AFSR Pin Input 5'b00001 - McASP1 AFSR Pin Input 5'b00010 - McASP2 AFSR Pin Input 5'b00011 - McASP3 AFSR Pin Input 5'b00100 - McASP4.." line.long 0x4 "CFG0_ATL_BWS1_SEL_PROXY,Selects the source of ATL Baseband Word Select 1" hexmask.long.byte 0x4 0.--4. 1. "ATL_BWS1_SEL_WD_SEL_PROXY,BWS source signal Field values (Others are reserved): 5'b00000 - McASP0 AFSR Pin Input 5'b00001 - McASP1 AFSR Pin Input 5'b00010 - McASP2 AFSR Pin Input 5'b00011 - McASP3 AFSR Pin Input 5'b00100 - McASP4.." line.long 0x8 "CFG0_ATL_BWS2_SEL_PROXY,Selects the source of ATL Baseband Word Select 2" hexmask.long.byte 0x8 0.--4. 1. "ATL_BWS2_SEL_WD_SEL_PROXY,BWS source signal Field values (Others are reserved): 5'b00000 - McASP0 AFSR Pin Input 5'b00001 - McASP1 AFSR Pin Input 5'b00010 - McASP2 AFSR Pin Input 5'b00011 - McASP3 AFSR Pin Input 5'b00100 - McASP4.." line.long 0xC "CFG0_ATL_BWS3_SEL_PROXY,Selects the source of ATL Baseband Word Select 3" hexmask.long.byte 0xC 0.--4. 1. "ATL_BWS3_SEL_WD_SEL_PROXY,BWS source signal Field values (Others are reserved): 5'b00000 - McASP0 AFSR Pin Input 5'b00001 - McASP1 AFSR Pin Input 5'b00010 - McASP2 AFSR Pin Input 5'b00011 - McASP3 AFSR Pin Input 5'b00100 - McASP4.." line.long 0x10 "CFG0_ATL_AWS0_SEL_PROXY,Selects the source of ATL Audio Word Select 0" hexmask.long.byte 0x10 0.--4. 1. "ATL_AWS0_SEL_WD_SEL_PROXY,AWS source signal Field values (Others are reserved): 5'b00000 - McASP0 AFSX Pin Input 5'b00001 - McASP1 AFSX Pin Input 5'b00010 - McASP2 AFSX Pin Input 5'b00011 - McASP3 AFSX Pin Input 5'b00100 - McASP4.." line.long 0x14 "CFG0_ATL_AWS1_SEL_PROXY,Selects the source of ATL Audio Word Select 1" hexmask.long.byte 0x14 0.--4. 1. "ATL_AWS1_SEL_WD_SEL_PROXY,AWS source signal Field values (Others are reserved): 5'b00000 - McASP0 AFSX Pin Input 5'b00001 - McASP1 AFSX Pin Input 5'b00010 - McASP2 AFSX Pin Input 5'b00011 - McASP3 AFSX Pin Input 5'b00100 - McASP4.." line.long 0x18 "CFG0_ATL_AWS2_SEL_PROXY,Selects the source of ATL Audio Word Select 2" hexmask.long.byte 0x18 0.--4. 1. "ATL_AWS2_SEL_WD_SEL_PROXY,AWS source signal Field values (Others are reserved): 5'b00000 - McASP0 AFSX Pin Input 5'b00001 - McASP1 AFSX Pin Input 5'b00010 - McASP2 AFSX Pin Input 5'b00011 - McASP3 AFSX Pin Input 5'b00100 - McASP4.." line.long 0x1C "CFG0_ATL_AWS3_SEL_PROXY,Selects the source of ATL Audio Word Select 3" hexmask.long.byte 0x1C 0.--4. 1. "ATL_AWS3_SEL_WD_SEL_PROXY,AWS source signal Field values (Others are reserved): 5'b00000 - McASP0 AFSX Pin Input 5'b00001 - McASP1 AFSX Pin Input 5'b00010 - McASP2 AFSX Pin Input 5'b00011 - McASP3 AFSX Pin Input 5'b00100 - McASP4.." line.long 0x20 "CFG0_ATL_CLKSEL_PROXY,Selects the source of the ATL PCLK" hexmask.long.byte 0x20 0.--3. 1. "ATL_CLKSEL_PCLK_SEL_PROXY,Selects the PCLK clock source Field values (Others are reserved): 3'b000 - MAIN_PLL4_HSDIV1_CLKOUT 3'b001 - MAIN_PLL2_HSDIV2_CLKOUT 3'b010 - 0 3'b011 - 0 3'b100 - MAIN_PLL0_HSDIV7_CLKOUT 3'b101 -.." rgroup.long 0xA2E0++0x7 line.long 0x0 "CFG0_AUDIO_REFCLK0_CTRL_PROXY,Selects the clock source for the AUDIO_EXT_REFCLK0 output" bitfld.long 0x0 15. "AUDIO_REFCLK0_CTRL_CLKOUT_EN_PROXY,AUDIO_REFCLK 0 output enableThis bit is inverted to drive the active low output buffer enable 0 - AUDIO_EXT_REFCLK0 pin is configured as an input 1 - AUDIO_EXT_REFCLK0 pin is configured as an output" "0: AUDIO_EXT_REFCLK0 pin is configured as an input 1,?" newline hexmask.long.byte 0x0 0.--4. 1. "AUDIO_REFCLK0_CTRL_CLK_SEL_PROXY,Clock source (default selects a tie-off of 0 for no output) Field values (Others are reserved): 5'b00000 - MCASP0 AHCLKR Output 5'b00001 - MCASP1 AHCLKR Output 5'b00010 - MCASP2 AHCLKR Output 5'b00011 -.." line.long 0x4 "CFG0_AUDIO_REFCLK1_CTRL_PROXY,Selects the clock source for the AUDIO_EXT_REFCLK1 output" bitfld.long 0x4 15. "AUDIO_REFCLK1_CTRL_CLKOUT_EN_PROXY,AUDIO_REFCLK 1 output enableThis bit is inverted to drive the active low output buffer enable 0 - AUDIO_EXT_REFCLK1 pin is configured as an input 1 - AUDIO_EXT_REFCLK1 pin is configured as an output" "0: AUDIO_EXT_REFCLK1 pin is configured as an input 1,?" newline hexmask.long.byte 0x4 0.--4. 1. "AUDIO_REFCLK1_CTRL_CLK_SEL_PROXY,Clock source (default selects a tie-off of 0 for no output) Field values (Others are reserved): 5'b00000 - MCASP0 AHCLKR Output 5'b00001 - MCASP1 AHCLKR Output 5'b00010 - MCASP2 AHCLKR Output 5'b00011 -.." rgroup.long 0xA300++0x3 line.long 0x0 "CFG0_DPI0_CLK_CTRL_PROXY,Selects the clock source for the DPI0 video output" bitfld.long 0x0 9. "DPI0_CLK_CTRL_SYNC_CLK_INVDIS_PROXY,Clock edge select for DPI0 sync outputs 0 - HSYNC and VSYNC are driven on the falling edge of clk 1 - HSYNC and VSYNC are driven on the rising edge of clkNote that this value should align with the programmed value.." "0: HSYNC and VSYNC are driven on the falling edge..,?" newline bitfld.long 0x0 8. "DPI0_CLK_CTRL_DATA_CLK_INVDIS_PROXY,Clock edge select for DPI0 data outputs 0 - DATA and DE are driven on the falling edge of clk 1 - DATA and DE are driven on the rising edge of clkNote that this value should align with the programmed value of the.." "0: DATA and DE are driven on the falling edge of..,?" newline bitfld.long 0x0 0. "DPI0_CLK_CTRL_EXT_CLKSEL_PROXY,Selects whether to use DSS PLL3 or an external pin as a DPI clock source. (See the J7AM Clock Specification for more details.) 0 - Use internal clock : MAIN_PLL19_HSDIV0_CLKOUT 1 - Use external clock : VOUT0_EXTPCLKIN" "0: Use internal clock : MAIN_PLL19_HSDIV0_CLKOUT 1,?" rgroup.long 0xA310++0x7 line.long 0x0 "CFG0_DPHY0_CLKSEL_PROXY,Selects the clock source for the DSI0 transmit PHY" bitfld.long 0x0 0.--1. "DPHY0_CLKSEL_REF_CLK_SEL_PROXY,DPHY reference clock source 2'b00 - HFOSC0_CLKOUT 2'b01 - HFOSC1_CLKOUT 2'b10 - MAIN_PLL3_HSDIV4_CLKOUT 2'b11 - MAIN_PLL2_HSDIV4_CLKOUT" "0: HFOSC0_CLKOUT 2'b01,?,2: MAIN_PLL3_HSDIV4_CLKOUT 2'b11,?" line.long 0x4 "CFG0_DPHY1_CLKSEL_PROXY,Selects the clock source for the DSI1 transmit PHY" bitfld.long 0x4 0.--1. "DPHY1_CLKSEL_REF_CLK_SEL_PROXY,DPHY reference clock source 2'b00 - HFOSC0_CLKOUT 2'b01 - HFOSC1_CLKOUT 2'b10 - MAIN_PLL3_HSDIV4_CLKOUT 2'b11 - MAIN_PLL2_HSDIV4_CLKOUT" "0: HFOSC0_CLKOUT 2'b01,?,2: MAIN_PLL3_HSDIV4_CLKOUT 2'b11,?" rgroup.long 0xA324++0xB line.long 0x0 "CFG0_DSS_DISPC0_CLKSEL1_PROXY,Selects the clock source for DPI Lane 1 of Display Controller Instance 0" bitfld.long 0x0 0.--1. "DSS_DISPC0_CLKSEL1_DPI1_PCLK_PROXY,DPI lane 1 pixel clock source Field values (Others are reserved): 2'b00 - MAIN_PLL17_HSDIV0_CLKOUT 2'b01 - MAIN_PLL19_HSDIV0_CLKOUT_EXTPCLKIN 2'b10 - MAIN_PLL19_HSDIV0_CLKOUT_EXTPCLKIN 2'b11 -.." "0: MAIN_PLL17_HSDIV0_CLKOUT 2'b01,?,2: MAIN_PLL19_HSDIV0_CLKOUT_EXTPCLKIN 2'b11,?" line.long 0x4 "CFG0_DSS_DISPC0_CLKSEL2_PROXY,Selects the clock source for DPI Lane 2 of Display Controller Instance 0" bitfld.long 0x4 0. "DSS_DISPC0_CLKSEL2_DPI2_PCLK_PROXY,DPI lane 2 pixel clock source Field values (Others are reserved): 1'b0 - MAIN_PLL16_HSDIV0_CLKOUT 1'b1 - MAIN_PLL17_HSDIV0_CLKOUT" "0: MAIN_PLL16_HSDIV0_CLKOUT 1'b1,?" line.long 0x8 "CFG0_DSS_DISPC0_CLKSEL3_PROXY,Can also override the DPI Lane 0 and DPI Lane 2 clock source for certain values." bitfld.long 0x8 0.--2. "DSS_DISPC0_CLKSEL3_DPI3_PCLK_PROXY,DPI lane 3 pixel clock sourceNote that values of 3'b1x1 also change the DPI lane 0 pixel clock source and values of 3'b11x change the DPI lane 2 pixel clock source Field values (Others are reserved): 3'b000 -.." "0: MAIN_PLL16_HSDIV1_CLKOUT 3'b001,?,2: MAIN_PLL17_HSDIV1_CLKOUT 3'b011,?,4: MAIN_PLL19_HSDIV0_CLKOUT_EXTPCLKIN 3'b101,?,6: MAIN_PLL19_HSDIV0_CLKOUT_EXTPCLKIN and dpi2_pclk..,?" rgroup.long 0xA350++0x3 line.long 0x0 "CFG0_EDP0_CLK_CTRL_PROXY,Controls clock operation for Embedded Display Port 0" bitfld.long 0x0 8. "EDP0_CLK_CTRL_DSI_CLK_DYN_SWTCH_DIS_PROXY,EDP0 DSI clock dynamic switch disable.This bit controls whether the EDP source clock is dynamically switched (to MAIN_PLL2_HSDIV7_CLKOUT) on a warm reset event. (See PLL Bypass Logic during Main WarmReset.." "0: Dynamic switching on warm reset is enabled 1,?" rgroup.long 0xA380++0x7 line.long 0x0 "CFG0_WWD0_CLKSEL_PROXY,ARM MPU Cluster 0 Core 0 Windowed watchdog timer functional clock selection control" bitfld.long 0x0 31. "WWD0_CLKSEL_WRTLOCK_PROXY,When set locks WWD0_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x0 0.--2. "WWD0_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control Field values (Others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - LFXOSC_CLKOUT 3'b010 - CLK_12M_RC 3'b011 - CLK_32K 3'b100 - HFOSC1_CLKOUT.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: HFOSC1_CLKOUT 3'b101,?,6: reserved,7: reserved" line.long 0x4 "CFG0_WWD1_CLKSEL_PROXY,ARM MPU Cluster 0 Core 1 Windowed watchdog timer functional clock selection control" bitfld.long 0x4 31. "WWD1_CLKSEL_WRTLOCK_PROXY,When set locks WWD1_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x4 0.--2. "WWD1_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control Field values (Others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - LFXOSC_CLKOUT 3'b010 - CLK_12M_RC 3'b011 - CLK_32K 3'b100 - HFOSC1_CLKOUT.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: HFOSC1_CLKOUT 3'b101,?,6: reserved,7: reserved" rgroup.long 0xA3BC++0xB line.long 0x0 "CFG0_WWD15_CLKSEL_PROXY,GPU Windowed watchdog timer functional clock selection control" bitfld.long 0x0 31. "WWD15_CLKSEL_WRTLOCK_PROXY,When set locks WWD15_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x0 0.--2. "WWD15_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control Field values (Others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - LFXOSC_CLKOUT 3'b010 - CLK_12M_RC 3'b011 - CLK_32K 3'b100 -.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: HFOSC1_CLKOUT 3'b101,?,6: reserved,7: reserved" line.long 0x4 "CFG0_WWD16_CLKSEL_PROXY,C71x Core 0 Windowed watchdog timer functional clock selection control" bitfld.long 0x4 31. "WWD16_CLKSEL_WRTLOCK_PROXY,When set locks WWD16_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x4 0.--2. "WWD16_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control Field values (Others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - LFXOSC_CLKOUT 3'b010 - CLK_12M_RC 3'b011 - CLK_32K 3'b100 -.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: HFOSC1_CLKOUT 3'b101,?,6: reserved,7: reserved" line.long 0x8 "CFG0_WWD17_CLKSEL_PROXY,C71x Core 1 Windowed watchdog timer functional clock selection control" bitfld.long 0x8 31. "WWD17_CLKSEL_WRTLOCK_PROXY,When set locks WWD17_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x8 0.--2. "WWD17_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control Field values (Others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - LFXOSC_CLKOUT 3'b010 - CLK_12M_RC 3'b011 - CLK_32K 3'b100 -.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: HFOSC1_CLKOUT 3'b101,?,6: reserved,7: reserved" rgroup.long 0xA3F0++0x13 line.long 0x0 "CFG0_WWD28_CLKSEL_PROXY,Main R5 Clstr0 Core0 Windowed watchdog timer functional clock selection control." bitfld.long 0x0 31. "WWD28_CLKSEL_WRTLOCK_PROXY,When set locks WWD28_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x0 0.--2. "WWD28_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux controlThese bits are warm reset isolated to preserve R5 RTI clock selection. Field values (Others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - LFXOSC_CLKOUT.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: HFOSC1_CLKOUT 3'b101,?,6: reserved,7: reserved" line.long 0x4 "CFG0_WWD29_CLKSEL_PROXY,Main R5 Clstr0 Core1 Windowed watchdog timer functional clock selection control." bitfld.long 0x4 31. "WWD29_CLKSEL_WRTLOCK_PROXY,When set locks WWD29_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x4 0.--2. "WWD29_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux controlThese bits are warm reset isolated to preserve R5 RTI clock selection. Field values (Others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - LFXOSC_CLKOUT.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: HFOSC1_CLKOUT 3'b101,?,6: reserved,7: reserved" line.long 0x8 "CFG0_WWD30_CLKSEL_PROXY,Main R5 Clstr1 Core0 Windowed watchdog timer functional clock selection control." bitfld.long 0x8 31. "WWD30_CLKSEL_WRTLOCK_PROXY,When set locks WWD30_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x8 0.--2. "WWD30_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux controlThese bits are warm reset isolated to preserve R5 RTI clock selection. Field values (Others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - LFXOSC_CLKOUT.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: HFOSC1_CLKOUT 3'b101,?,6: reserved,7: reserved" line.long 0xC "CFG0_WWD31_CLKSEL_PROXY,Main R5 Clstr1 Core1 Windowed watchdog timer functional clock selection control." bitfld.long 0xC 31. "WWD31_CLKSEL_WRTLOCK_PROXY,When set locks WWD31_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0xC 0.--2. "WWD31_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux controlThese bits are warm reset isolated to preserve R5 RTI clock selection. Field values (Others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - LFXOSC_CLKOUT.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: HFOSC1_CLKOUT 3'b101,?,6: reserved,7: reserved" line.long 0x10 "CFG0_SERDES0_CLKSEL_PROXY,Selects the clock source for Serdes0." bitfld.long 0x10 0.--1. "SERDES0_CLKSEL_CORE_REFCLK_SEL_PROXY,Selects the source for the core_refclk input Field values (Others are reserved): 2'b00 - HFOSC0_CLKOUT 2'b01 - HFOSC1_CLKOUT 2'b10 - MAIN_PLL3_HSDIV4_CLKOUT 2'b11 - MAIN_PLL2_HSDIV4_CLKOUT" "0: HFOSC0_CLKOUT 2'b01,?,2: MAIN_PLL3_HSDIV4_CLKOUT 2'b11,?" rgroup.long 0xA480++0x47 line.long 0x0 "CFG0_MCAN0_CLKSEL_PROXY,Controls the functional clock source MCAN0" bitfld.long 0x0 0.--1. "MCAN0_CLKSEL_CLK_SEL_PROXY,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x4 "CFG0_MCAN1_CLKSEL_PROXY,Controls the functional clock source MCAN1" bitfld.long 0x4 0.--1. "MCAN1_CLKSEL_CLK_SEL_PROXY,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x8 "CFG0_MCAN2_CLKSEL_PROXY,Controls the functional clock source MCAN2" bitfld.long 0x8 0.--1. "MCAN2_CLKSEL_CLK_SEL_PROXY,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0xC "CFG0_MCAN3_CLKSEL_PROXY,Controls the functional clock source MCAN3" bitfld.long 0xC 0.--1. "MCAN3_CLKSEL_CLK_SEL_PROXY,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x10 "CFG0_MCAN4_CLKSEL_PROXY,Controls the functional clock source MCAN4" bitfld.long 0x10 0.--1. "MCAN4_CLKSEL_CLK_SEL_PROXY,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x14 "CFG0_MCAN5_CLKSEL_PROXY,Controls the functional clock source MCAN5" bitfld.long 0x14 0.--1. "MCAN5_CLKSEL_CLK_SEL_PROXY,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x18 "CFG0_MCAN6_CLKSEL_PROXY,Controls the functional clock source MCAN6" bitfld.long 0x18 0.--1. "MCAN6_CLKSEL_CLK_SEL_PROXY,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x1C "CFG0_MCAN7_CLKSEL_PROXY,Controls the functional clock source MCAN7" bitfld.long 0x1C 0.--1. "MCAN7_CLKSEL_CLK_SEL_PROXY,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x20 "CFG0_MCAN8_CLKSEL_PROXY,Controls the functional clock source MCAN8" bitfld.long 0x20 0.--1. "MCAN8_CLKSEL_CLK_SEL_PROXY,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x24 "CFG0_MCAN9_CLKSEL_PROXY,Controls the functional clock source MCAN9" bitfld.long 0x24 0.--1. "MCAN9_CLKSEL_CLK_SEL_PROXY,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x28 "CFG0_MCAN10_CLKSEL_PROXY,Controls the functional clock source MCAN10" bitfld.long 0x28 0.--1. "MCAN10_CLKSEL_CLK_SEL_PROXY,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x2C "CFG0_MCAN11_CLKSEL_PROXY,Controls the functional clock source MCAN11" bitfld.long 0x2C 0.--1. "MCAN11_CLKSEL_CLK_SEL_PROXY,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x30 "CFG0_MCAN12_CLKSEL_PROXY,Controls the functional clock source MCAN12" bitfld.long 0x30 0.--1. "MCAN12_CLKSEL_CLK_SEL_PROXY,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x34 "CFG0_MCAN13_CLKSEL_PROXY,Controls the functional clock source MCAN13" bitfld.long 0x34 0.--1. "MCAN13_CLKSEL_CLK_SEL_PROXY,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x38 "CFG0_MCAN14_CLKSEL_PROXY,Controls the functional clock source MCAN14" bitfld.long 0x38 0.--1. "MCAN14_CLKSEL_CLK_SEL_PROXY,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x3C "CFG0_MCAN15_CLKSEL_PROXY,Controls the functional clock source MCAN15" bitfld.long 0x3C 0.--1. "MCAN15_CLKSEL_CLK_SEL_PROXY,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x40 "CFG0_MCAN16_CLKSEL_PROXY,Controls the functional clock source MCAN16" bitfld.long 0x40 0.--1. "MCAN16_CLKSEL_CLK_SEL_PROXY,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" line.long 0x44 "CFG0_MCAN17_CLKSEL_PROXY,Controls the functional clock source MCAN17" bitfld.long 0x44 0.--1. "MCAN17_CLKSEL_CLK_SEL_PROXY,MAIN MCAN_CLK selection 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (pin) 2'b10 - HFOSC1_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MAIN_PLL0_HSDIV4_CLKOUT 2'b01,?,2: HFOSC1_CLKOUT 2'b11,?" rgroup.long 0xB008++0x7 line.long 0x0 "CFG0_LOCK2_KICK0_PROXY,This register must be written with the designated key value followed by a write to LOCK2_KICK1 with its key value before write-protected Partition 2 registers can be written." hexmask.long 0x0 0.--31. 1. "LOCK2_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK2_KICK1_PROXY,This register must be written with the designated key value after a write to LOCK2_KICK0 with its key value before write-protected Partition 2 registers can be written." hexmask.long 0x4 0.--31. 1. "LOCK2_KICK1_PROXY,- KICK1 component" rgroup.long 0xB100++0x33 line.long 0x0 "CFG0_CLAIMREG_P2_R0," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P2_R0,Claim bits for Partition 2" line.long 0x4 "CFG0_CLAIMREG_P2_R1," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P2_R1,Claim bits for Partition 2" line.long 0x8 "CFG0_CLAIMREG_P2_R2," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P2_R2,Claim bits for Partition 2" line.long 0xC "CFG0_CLAIMREG_P2_R3," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P2_R3,Claim bits for Partition 2" line.long 0x10 "CFG0_CLAIMREG_P2_R4," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P2_R4,Claim bits for Partition 2" line.long 0x14 "CFG0_CLAIMREG_P2_R5," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P2_R5,Claim bits for Partition 2" line.long 0x18 "CFG0_CLAIMREG_P2_R6," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P2_R6,Claim bits for Partition 2" line.long 0x1C "CFG0_CLAIMREG_P2_R7," hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P2_R7,Claim bits for Partition 2" line.long 0x20 "CFG0_CLAIMREG_P2_R8," hexmask.long 0x20 0.--31. 1. "CLAIMREG_P2_R8,Claim bits for Partition 2" line.long 0x24 "CFG0_CLAIMREG_P2_R9," hexmask.long 0x24 0.--31. 1. "CLAIMREG_P2_R9,Claim bits for Partition 2" line.long 0x28 "CFG0_CLAIMREG_P2_R10," hexmask.long 0x28 0.--31. 1. "CLAIMREG_P2_R10,Claim bits for Partition 2" line.long 0x2C "CFG0_CLAIMREG_P2_R11," hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P2_R11,Claim bits for Partition 2" line.long 0x30 "CFG0_CLAIMREG_P2_R12," hexmask.long 0x30 0.--31. 1. "CLAIMREG_P2_R12,Claim bits for Partition 2" rgroup.long 0xC000++0x1B line.long 0x0 "CFG0_MCU0_LBIST_CTRL,Configures and enables LBIST operation" bitfld.long 0x0 31. "MCU0_LBIST_CTRL_BIST_RESET,Reset LBIST macro" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "MCU0_LBIST_CTRL_BIST_RUN,Starts LBIST if all bits are 1" newline hexmask.long.byte 0x0 12.--15. 1. "MCU0_LBIST_CTRL_RUNBIST_MODE,Runbist mode enable if all bits are 1" newline bitfld.long 0x0 8.--9. "MCU0_LBIST_CTRL_DC_DEF,Clock delay after scan_enable switching" "0,1,2,3" newline bitfld.long 0x0 7. "MCU0_LBIST_CTRL_LOAD_DIV,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "MCU0_LBIST_CTRL_DIVIDE_RATIO,LBIST clock divide ratio" line.long 0x4 "CFG0_MCU0_LBIST_PATCOUNT,Specifies the number of LBIST patterns to run" hexmask.long.word 0x4 16.--29. 1. "MCU0_LBIST_PATCOUNT_STATIC_PC_DEF,Number of stuck-at patterns to run" newline hexmask.long.byte 0x4 8.--11. 1. "MCU0_LBIST_PATCOUNT_SET_PC_DEF,Number of set patterns to run" newline hexmask.long.byte 0x4 4.--7. 1. "MCU0_LBIST_PATCOUNT_RESET_PC_DEF,Number of reset patterns to run" newline hexmask.long.byte 0x4 0.--3. 1. "MCU0_LBIST_PATCOUNT_SCAN_PC_DEF,Number of chain test patterns to run" line.long 0x8 "CFG0_MCU0_LBIST_SEED0,Specifies the 32 LSBs of the PRPG seed" hexmask.long 0x8 0.--31. 1. "MCU0_LBIST_SEED0_PRPG_DEF,Initial seed for PRPG (bits 31:0)" line.long 0xC "CFG0_MCU0_LBIST_SEED1,Specifies the 21 MSBs of the PRPG seed" hexmask.long.tbyte 0xC 0.--20. 1. "MCU0_LBIST_SEED1_PRPG_DEF,Initial seed for PRPG (bits 52:32)" line.long 0x10 "CFG0_MCU0_LBIST_SPARE0,Spare LBIST control bits" hexmask.long 0x10 2.--31. 1. "MCU0_LBIST_SPARE0_SPARE0,LBIST spare bits" newline bitfld.long 0x10 1. "MCU0_LBIST_SPARE0_PBIST_SELFTEST_EN,PBIST isolation control" "0,1" newline bitfld.long 0x10 0. "MCU0_LBIST_SPARE0_LBIST_SELFTEST_EN,LBIST isolation control" "0,1" line.long 0x14 "CFG0_MCU0_LBIST_SPARE1,Spare LBIST control bits" hexmask.long 0x14 0.--31. 1. "MCU0_LBIST_SPARE1_SPARE1,LBIST spare bits" line.long 0x18 "CFG0_MCU0_LBIST_STAT,Indicates LBIST status and provides MISR selection control" rbitfld.long 0x18 31. "MCU0_LBIST_STAT_BIST_DONE,LBIST is done" "0,1" newline rbitfld.long 0x18 15. "MCU0_LBIST_STAT_BIST_RUNNING,LBIST is running" "0,1" newline bitfld.long 0x18 8.--9. "MCU0_LBIST_STAT_OUT_MUX_CTL,Selects source of LBIST output 00 - LBIST IP PID value 01 - LBIST CTRL ID value 1x - MISR value" "0: LBIST IP PID value 01,?,?,?" newline hexmask.long.byte 0x18 0.--7. 1. "MCU0_LBIST_STAT_MISR_MUX_CTL,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR." rgroup.long 0xC01C++0x3 line.long 0x0 "CFG0_MCU0_LBIST_MISR,Contains LBIST MISR output value" hexmask.long 0x0 0.--31. 1. "MCU0_LBIST_MISR_MISR_RESULT,32-bits of MISR value selected by misr_mux_ctl" rgroup.long 0xC020++0x1B line.long 0x0 "CFG0_MCU1_LBIST_CTRL,Configures and enables LBIST operation" bitfld.long 0x0 31. "MCU1_LBIST_CTRL_BIST_RESET,Reset LBIST macro" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "MCU1_LBIST_CTRL_BIST_RUN,Starts LBIST if all bits are 1" newline hexmask.long.byte 0x0 12.--15. 1. "MCU1_LBIST_CTRL_RUNBIST_MODE,Runbist mode enable if all bits are 1" newline bitfld.long 0x0 8.--9. "MCU1_LBIST_CTRL_DC_DEF,Clock delay after scan_enable switching" "0,1,2,3" newline bitfld.long 0x0 7. "MCU1_LBIST_CTRL_LOAD_DIV,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "MCU1_LBIST_CTRL_DIVIDE_RATIO,LBIST clock divide ratio" line.long 0x4 "CFG0_MCU1_LBIST_PATCOUNT,Specifies the number of LBIST patterns to run" hexmask.long.word 0x4 16.--29. 1. "MCU1_LBIST_PATCOUNT_STATIC_PC_DEF,Number of stuck-at patterns to run" newline hexmask.long.byte 0x4 8.--11. 1. "MCU1_LBIST_PATCOUNT_SET_PC_DEF,Number of set patterns to run" newline hexmask.long.byte 0x4 4.--7. 1. "MCU1_LBIST_PATCOUNT_RESET_PC_DEF,Number of reset patterns to run" newline hexmask.long.byte 0x4 0.--3. 1. "MCU1_LBIST_PATCOUNT_SCAN_PC_DEF,Number of chain test patterns to run" line.long 0x8 "CFG0_MCU1_LBIST_SEED0,Specifies the 32 LSBs of the PRPG seed" hexmask.long 0x8 0.--31. 1. "MCU1_LBIST_SEED0_PRPG_DEF,Initial seed for PRPG (bits 31:0)" line.long 0xC "CFG0_MCU1_LBIST_SEED1,Specifies the 21 MSBs of the PRPG seed" hexmask.long.tbyte 0xC 0.--20. 1. "MCU1_LBIST_SEED1_PRPG_DEF,Initial seed for PRPG (bits 52:32)" line.long 0x10 "CFG0_MCU1_LBIST_SPARE0,Spare LBIST control bits" hexmask.long 0x10 2.--31. 1. "MCU1_LBIST_SPARE0_SPARE0,LBIST spare bits" newline bitfld.long 0x10 1. "MCU1_LBIST_SPARE0_PBIST_SELFTEST_EN,PBIST isolation control" "0,1" newline bitfld.long 0x10 0. "MCU1_LBIST_SPARE0_LBIST_SELFTEST_EN,LBIST isolation control" "0,1" line.long 0x14 "CFG0_MCU1_LBIST_SPARE1,Spare LBIST control bits" hexmask.long 0x14 0.--31. 1. "MCU1_LBIST_SPARE1_SPARE1,LBIST spare bits" line.long 0x18 "CFG0_MCU1_LBIST_STAT,Indicates LBIST status and provides MISR selection control" rbitfld.long 0x18 31. "MCU1_LBIST_STAT_BIST_DONE,LBIST is done" "0,1" newline rbitfld.long 0x18 15. "MCU1_LBIST_STAT_BIST_RUNNING,LBIST is running" "0,1" newline bitfld.long 0x18 8.--9. "MCU1_LBIST_STAT_OUT_MUX_CTL,Selects source of LBIST output 00 - LBIST IP PID value 01 - LBIST CTRL ID value 1x - MISR value" "0: LBIST IP PID value 01,?,?,?" newline hexmask.long.byte 0x18 0.--7. 1. "MCU1_LBIST_STAT_MISR_MUX_CTL,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR." rgroup.long 0xC03C++0x3 line.long 0x0 "CFG0_MCU1_LBIST_MISR,Contains LBIST MISR output value" hexmask.long 0x0 0.--31. 1. "MCU1_LBIST_MISR_MISR_RESULT,32-bits of MISR value selected by misr_mux_ctl" rgroup.long 0xC040++0x1B line.long 0x0 "CFG0_DMPAC_LBIST_CTRL,Configures and enables LBIST operation" bitfld.long 0x0 31. "DMPAC_LBIST_CTRL_BIST_RESET,Reset LBIST macro" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "DMPAC_LBIST_CTRL_BIST_RUN,Starts LBIST if all bits are 1" newline hexmask.long.byte 0x0 12.--15. 1. "DMPAC_LBIST_CTRL_RUNBIST_MODE,Runbist mode enable if all bits are 1" newline bitfld.long 0x0 8.--9. "DMPAC_LBIST_CTRL_DC_DEF,Clock delay after scan_enable switching" "0,1,2,3" newline bitfld.long 0x0 7. "DMPAC_LBIST_CTRL_LOAD_DIV,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "DMPAC_LBIST_CTRL_DIVIDE_RATIO,LBIST clock divide ratio" line.long 0x4 "CFG0_DMPAC_LBIST_PATCOUNT,Specifies the number of LBIST patterns to run" hexmask.long.word 0x4 16.--29. 1. "DMPAC_LBIST_PATCOUNT_STATIC_PC_DEF,Number of stuck-at patterns to run" newline hexmask.long.byte 0x4 8.--11. 1. "DMPAC_LBIST_PATCOUNT_SET_PC_DEF,Number of set patterns to run" newline hexmask.long.byte 0x4 4.--7. 1. "DMPAC_LBIST_PATCOUNT_RESET_PC_DEF,Number of reset patterns to run" newline hexmask.long.byte 0x4 0.--3. 1. "DMPAC_LBIST_PATCOUNT_SCAN_PC_DEF,Number of chain test patterns to run" line.long 0x8 "CFG0_DMPAC_LBIST_SEED0,Specifies the 32 LSBs of the PRPG seed" hexmask.long 0x8 0.--31. 1. "DMPAC_LBIST_SEED0_PRPG_DEF,Initial seed for PRPG (bits 31:0)" line.long 0xC "CFG0_DMPAC_LBIST_SEED1,Specifies the 21 MSBs of the PRPG seed" hexmask.long.tbyte 0xC 0.--20. 1. "DMPAC_LBIST_SEED1_PRPG_DEF,Initial seed for PRPG (bits 52:32)" line.long 0x10 "CFG0_DMPAC_LBIST_SPARE0,Spare LBIST control bits" hexmask.long 0x10 2.--31. 1. "DMPAC_LBIST_SPARE0_SPARE0,LBIST spare bits" newline bitfld.long 0x10 1. "DMPAC_LBIST_SPARE0_PBIST_SELFTEST_EN,PBIST isolation control" "0,1" newline bitfld.long 0x10 0. "DMPAC_LBIST_SPARE0_LBIST_SELFTEST_EN,LBIST isolation control" "0,1" line.long 0x14 "CFG0_DMPAC_LBIST_SPARE1,Spare LBIST control bits" hexmask.long 0x14 0.--31. 1. "DMPAC_LBIST_SPARE1_SPARE1,LBIST spare bits" line.long 0x18 "CFG0_DMPAC_LBIST_STAT,Indicates LBIST status and provides MISR selection control" rbitfld.long 0x18 31. "DMPAC_LBIST_STAT_BIST_DONE,LBIST is done" "0,1" newline rbitfld.long 0x18 15. "DMPAC_LBIST_STAT_BIST_RUNNING,LBIST is running" "0,1" newline bitfld.long 0x18 8.--9. "DMPAC_LBIST_STAT_OUT_MUX_CTL,Selects source of LBIST output 00 - LBIST IP PID value 01 - LBIST CTRL ID value 1x - MISR value" "0: LBIST IP PID value 01,?,?,?" newline hexmask.long.byte 0x18 0.--7. 1. "DMPAC_LBIST_STAT_MISR_MUX_CTL,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR." rgroup.long 0xC05C++0x3 line.long 0x0 "CFG0_DMPAC_LBIST_MISR,Contains LBIST MISR output value" hexmask.long 0x0 0.--31. 1. "DMPAC_LBIST_MISR_MISR_RESULT,32-bits of MISR value selected by misr_mux_ctl" rgroup.long 0xC060++0x1B line.long 0x0 "CFG0_VPAC0_LBIST_CTRL,Configures and enables LBIST operation" bitfld.long 0x0 31. "VPAC0_LBIST_CTRL_BIST_RESET,Reset LBIST macro" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "VPAC0_LBIST_CTRL_BIST_RUN,Starts LBIST if all bits are 1" newline hexmask.long.byte 0x0 12.--15. 1. "VPAC0_LBIST_CTRL_RUNBIST_MODE,Runbist mode enable if all bits are 1" newline bitfld.long 0x0 8.--9. "VPAC0_LBIST_CTRL_DC_DEF,Clock delay after scan_enable switching" "0,1,2,3" newline bitfld.long 0x0 7. "VPAC0_LBIST_CTRL_LOAD_DIV,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "VPAC0_LBIST_CTRL_DIVIDE_RATIO,LBIST clock divide ratio" line.long 0x4 "CFG0_VPAC0_LBIST_PATCOUNT,Specifies the number of LBIST patterns to run" hexmask.long.word 0x4 16.--29. 1. "VPAC0_LBIST_PATCOUNT_STATIC_PC_DEF,Number of stuck-at patterns to run" newline hexmask.long.byte 0x4 8.--11. 1. "VPAC0_LBIST_PATCOUNT_SET_PC_DEF,Number of set patterns to run" newline hexmask.long.byte 0x4 4.--7. 1. "VPAC0_LBIST_PATCOUNT_RESET_PC_DEF,Number of reset patterns to run" newline hexmask.long.byte 0x4 0.--3. 1. "VPAC0_LBIST_PATCOUNT_SCAN_PC_DEF,Number of chain test patterns to run" line.long 0x8 "CFG0_VPAC0_LBIST_SEED0,Specifies the 32 LSBs of the PRPG seed" hexmask.long 0x8 0.--31. 1. "VPAC0_LBIST_SEED0_PRPG_DEF,Initial seed for PRPG (bits 31:0)" line.long 0xC "CFG0_VPAC0_LBIST_SEED1,Specifies the 21 MSBs of the PRPG seed" hexmask.long.tbyte 0xC 0.--20. 1. "VPAC0_LBIST_SEED1_PRPG_DEF,Initial seed for PRPG (bits 52:32)" line.long 0x10 "CFG0_VPAC0_LBIST_SPARE0,Spare LBIST control bits" hexmask.long 0x10 2.--31. 1. "VPAC0_LBIST_SPARE0_SPARE0,LBIST spare bits" newline bitfld.long 0x10 1. "VPAC0_LBIST_SPARE0_PBIST_SELFTEST_EN,PBIST isolation control" "0,1" newline bitfld.long 0x10 0. "VPAC0_LBIST_SPARE0_LBIST_SELFTEST_EN,LBIST isolation control" "0,1" line.long 0x14 "CFG0_VPAC0_LBIST_SPARE1,Spare LBIST control bits" hexmask.long 0x14 0.--31. 1. "VPAC0_LBIST_SPARE1_SPARE1,LBIST spare bits" line.long 0x18 "CFG0_VPAC0_LBIST_STAT,Indicates LBIST status and provides MISR selection control" rbitfld.long 0x18 31. "VPAC0_LBIST_STAT_BIST_DONE,LBIST is done" "0,1" newline rbitfld.long 0x18 15. "VPAC0_LBIST_STAT_BIST_RUNNING,LBIST is running" "0,1" newline bitfld.long 0x18 8.--9. "VPAC0_LBIST_STAT_OUT_MUX_CTL,Selects source of LBIST output 00 - LBIST IP PID value 01 - LBIST CTRL ID value 1x - MISR value" "0: LBIST IP PID value 01,?,?,?" newline hexmask.long.byte 0x18 0.--7. 1. "VPAC0_LBIST_STAT_MISR_MUX_CTL,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR." rgroup.long 0xC07C++0x3 line.long 0x0 "CFG0_VPAC0_LBIST_MISR,Contains LBIST MISR output value" hexmask.long 0x0 0.--31. 1. "VPAC0_LBIST_MISR_MISR_RESULT,32-bits of MISR value selected by misr_mux_ctl" rgroup.long 0xC080++0x1B line.long 0x0 "CFG0_DSP0_LBIST_CTRL,Configures and enables LBIST operation" bitfld.long 0x0 31. "DSP0_LBIST_CTRL_BIST_RESET,Reset LBIST macro" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "DSP0_LBIST_CTRL_BIST_RUN,Starts LBIST if all bits are 1" newline hexmask.long.byte 0x0 12.--15. 1. "DSP0_LBIST_CTRL_RUNBIST_MODE,Runbist mode enable if all bits are 1" newline bitfld.long 0x0 8.--9. "DSP0_LBIST_CTRL_DC_DEF,Clock delay after scan_enable switching" "0,1,2,3" newline bitfld.long 0x0 7. "DSP0_LBIST_CTRL_LOAD_DIV,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "DSP0_LBIST_CTRL_DIVIDE_RATIO,LBIST clock divide ratio" line.long 0x4 "CFG0_DSP0_LBIST_PATCOUNT,Specifies the number of LBIST patterns to run" hexmask.long.word 0x4 16.--29. 1. "DSP0_LBIST_PATCOUNT_STATIC_PC_DEF,Number of stuck-at patterns to run" newline hexmask.long.byte 0x4 8.--11. 1. "DSP0_LBIST_PATCOUNT_SET_PC_DEF,Number of set patterns to run" newline hexmask.long.byte 0x4 4.--7. 1. "DSP0_LBIST_PATCOUNT_RESET_PC_DEF,Number of reset patterns to run" newline hexmask.long.byte 0x4 0.--3. 1. "DSP0_LBIST_PATCOUNT_SCAN_PC_DEF,Number of chain test patterns to run" line.long 0x8 "CFG0_DSP0_LBIST_SEED0,Specifies the 32 LSBs of the PRPG seed" hexmask.long 0x8 0.--31. 1. "DSP0_LBIST_SEED0_PRPG_DEF,Initial seed for PRPG (bits 31:0)" line.long 0xC "CFG0_DSP0_LBIST_SEED1,Specifies the 21 MSBs of the PRPG seed" hexmask.long.tbyte 0xC 0.--20. 1. "DSP0_LBIST_SEED1_PRPG_DEF,Initial seed for PRPG (bits 52:32)" line.long 0x10 "CFG0_DSP0_LBIST_SPARE0,Spare LBIST control bits" hexmask.long 0x10 2.--31. 1. "DSP0_LBIST_SPARE0_SPARE0,LBIST spare bits" newline bitfld.long 0x10 1. "DSP0_LBIST_SPARE0_PBIST_SELFTEST_EN,PBIST isolation control" "0,1" newline bitfld.long 0x10 0. "DSP0_LBIST_SPARE0_LBIST_SELFTEST_EN,LBIST isolation control" "0,1" line.long 0x14 "CFG0_DSP0_LBIST_SPARE1,Spare LBIST control bits" hexmask.long 0x14 0.--31. 1. "DSP0_LBIST_SPARE1_SPARE1,LBIST spare bits" line.long 0x18 "CFG0_DSP0_LBIST_STAT,Indicates LBIST status and provides MISR selection control" rbitfld.long 0x18 31. "DSP0_LBIST_STAT_BIST_DONE,LBIST is done" "0,1" newline rbitfld.long 0x18 15. "DSP0_LBIST_STAT_BIST_RUNNING,LBIST is running" "0,1" newline bitfld.long 0x18 8.--9. "DSP0_LBIST_STAT_OUT_MUX_CTL,Selects source of LBIST output 00 - LBIST IP PID value 01 - LBIST CTRL ID value 1x - MISR value" "0: LBIST IP PID value 01,?,?,?" newline hexmask.long.byte 0x18 0.--7. 1. "DSP0_LBIST_STAT_MISR_MUX_CTL,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR." rgroup.long 0xC09C++0x3 line.long 0x0 "CFG0_DSP0_LBIST_MISR,Contains LBIST MISR output value" hexmask.long 0x0 0.--31. 1. "DSP0_LBIST_MISR_MISR_RESULT,32-bits of MISR value selected by misr_mux_ctl" rgroup.long 0xC0A0++0x1B line.long 0x0 "CFG0_DSP1_LBIST_CTRL,Configures and enables LBIST operation" bitfld.long 0x0 31. "DSP1_LBIST_CTRL_BIST_RESET,Reset LBIST macro" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "DSP1_LBIST_CTRL_BIST_RUN,Starts LBIST if all bits are 1" newline hexmask.long.byte 0x0 12.--15. 1. "DSP1_LBIST_CTRL_RUNBIST_MODE,Runbist mode enable if all bits are 1" newline bitfld.long 0x0 8.--9. "DSP1_LBIST_CTRL_DC_DEF,Clock delay after scan_enable switching" "0,1,2,3" newline bitfld.long 0x0 7. "DSP1_LBIST_CTRL_LOAD_DIV,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "DSP1_LBIST_CTRL_DIVIDE_RATIO,LBIST clock divide ratio" line.long 0x4 "CFG0_DSP1_LBIST_PATCOUNT,Specifies the number of LBIST patterns to run" hexmask.long.word 0x4 16.--29. 1. "DSP1_LBIST_PATCOUNT_STATIC_PC_DEF,Number of stuck-at patterns to run" newline hexmask.long.byte 0x4 8.--11. 1. "DSP1_LBIST_PATCOUNT_SET_PC_DEF,Number of set patterns to run" newline hexmask.long.byte 0x4 4.--7. 1. "DSP1_LBIST_PATCOUNT_RESET_PC_DEF,Number of reset patterns to run" newline hexmask.long.byte 0x4 0.--3. 1. "DSP1_LBIST_PATCOUNT_SCAN_PC_DEF,Number of chain test patterns to run" line.long 0x8 "CFG0_DSP1_LBIST_SEED0,Specifies the 32 LSBs of the PRPG seed" hexmask.long 0x8 0.--31. 1. "DSP1_LBIST_SEED0_PRPG_DEF,Initial seed for PRPG (bits 31:0)" line.long 0xC "CFG0_DSP1_LBIST_SEED1,Specifies the 21 MSBs of the PRPG seed" hexmask.long.tbyte 0xC 0.--20. 1. "DSP1_LBIST_SEED1_PRPG_DEF,Initial seed for PRPG (bits 52:32)" line.long 0x10 "CFG0_DSP1_LBIST_SPARE0,Spare LBIST control bits" hexmask.long 0x10 2.--31. 1. "DSP1_LBIST_SPARE0_SPARE0,LBIST spare bits" newline bitfld.long 0x10 1. "DSP1_LBIST_SPARE0_PBIST_SELFTEST_EN,PBIST isolation control" "0,1" newline bitfld.long 0x10 0. "DSP1_LBIST_SPARE0_LBIST_SELFTEST_EN,LBIST isolation control" "0,1" line.long 0x14 "CFG0_DSP1_LBIST_SPARE1,Spare LBIST control bits" hexmask.long 0x14 0.--31. 1. "DSP1_LBIST_SPARE1_SPARE1,LBIST spare bits" line.long 0x18 "CFG0_DSP1_LBIST_STAT,Indicates LBIST status and provides MISR selection control" rbitfld.long 0x18 31. "DSP1_LBIST_STAT_BIST_DONE,LBIST is done" "0,1" newline rbitfld.long 0x18 15. "DSP1_LBIST_STAT_BIST_RUNNING,LBIST is running" "0,1" newline bitfld.long 0x18 8.--9. "DSP1_LBIST_STAT_OUT_MUX_CTL,Selects source of LBIST output 00 - LBIST IP PID value 01 - LBIST CTRL ID value 1x - MISR value" "0: LBIST IP PID value 01,?,?,?" newline hexmask.long.byte 0x18 0.--7. 1. "DSP1_LBIST_STAT_MISR_MUX_CTL,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR." rgroup.long 0xC0BC++0x3 line.long 0x0 "CFG0_DSP1_LBIST_MISR,Contains LBIST MISR output value" hexmask.long 0x0 0.--31. 1. "DSP1_LBIST_MISR_MISR_RESULT,32-bits of MISR value selected by misr_mux_ctl" rgroup.long 0xC100++0x1B line.long 0x0 "CFG0_MPU0_LBIST_CTRL,Configures and enables LBIST operation" bitfld.long 0x0 31. "MPU0_LBIST_CTRL_BIST_RESET,Reset LBIST macro" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "MPU0_LBIST_CTRL_BIST_RUN,Starts LBIST if all bits are 1" newline hexmask.long.byte 0x0 12.--15. 1. "MPU0_LBIST_CTRL_RUNBIST_MODE,Runbist mode enable if all bits are 1" newline bitfld.long 0x0 8.--9. "MPU0_LBIST_CTRL_DC_DEF,Clock delay after scan_enable switching" "0,1,2,3" newline bitfld.long 0x0 7. "MPU0_LBIST_CTRL_LOAD_DIV,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "MPU0_LBIST_CTRL_DIVIDE_RATIO,LBIST clock divide ratio" line.long 0x4 "CFG0_MPU0_LBIST_PATCOUNT,Specifies the number of LBIST patterns to run" hexmask.long.word 0x4 16.--29. 1. "MPU0_LBIST_PATCOUNT_STATIC_PC_DEF,Number of stuck-at patterns to run" newline hexmask.long.byte 0x4 8.--11. 1. "MPU0_LBIST_PATCOUNT_SET_PC_DEF,Number of set patterns to run" newline hexmask.long.byte 0x4 4.--7. 1. "MPU0_LBIST_PATCOUNT_RESET_PC_DEF,Number of reset patterns to run" newline hexmask.long.byte 0x4 0.--3. 1. "MPU0_LBIST_PATCOUNT_SCAN_PC_DEF,Number of chain test patterns to run" line.long 0x8 "CFG0_MPU0_LBIST_SEED0,Specifies the 32 LSBs of the PRPG seed" hexmask.long 0x8 0.--31. 1. "MPU0_LBIST_SEED0_PRPG_DEF,Initial seed for PRPG (bits 31:0)" line.long 0xC "CFG0_MPU0_LBIST_SEED1,Specifies the 21 MSBs of the PRPG seed" hexmask.long.tbyte 0xC 0.--20. 1. "MPU0_LBIST_SEED1_PRPG_DEF,Initial seed for PRPG (bits 52:32)" line.long 0x10 "CFG0_MPU0_LBIST_SPARE0,Spare LBIST control bits" hexmask.long 0x10 2.--31. 1. "MPU0_LBIST_SPARE0_SPARE0,LBIST spare bits" newline bitfld.long 0x10 1. "MPU0_LBIST_SPARE0_PBIST_SELFTEST_EN,PBIST isolation control" "0,1" newline bitfld.long 0x10 0. "MPU0_LBIST_SPARE0_LBIST_SELFTEST_EN,LBIST isolation control" "0,1" line.long 0x14 "CFG0_MPU0_LBIST_SPARE1,Spare LBIST control bits" hexmask.long 0x14 0.--31. 1. "MPU0_LBIST_SPARE1_SPARE1,LBIST spare bits" line.long 0x18 "CFG0_MPU0_LBIST_STAT,Indicates LBIST status and provides MISR selection control" rbitfld.long 0x18 31. "MPU0_LBIST_STAT_BIST_DONE,LBIST is done" "0,1" newline rbitfld.long 0x18 15. "MPU0_LBIST_STAT_BIST_RUNNING,LBIST is running" "0,1" newline bitfld.long 0x18 8.--9. "MPU0_LBIST_STAT_OUT_MUX_CTL,Selects source of LBIST output 00 - LBIST IP PID value 01 - LBIST CTRL ID value 1x - MISR value" "0: LBIST IP PID value 01,?,?,?" newline hexmask.long.byte 0x18 0.--7. 1. "MPU0_LBIST_STAT_MISR_MUX_CTL,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR." rgroup.long 0xC11C++0x3 line.long 0x0 "CFG0_MPU0_LBIST_MISR,Contains LBIST MISR output value" hexmask.long 0x0 0.--31. 1. "MPU0_LBIST_MISR_MISR_RESULT,32-bits of MISR value selected by misr_mux_ctl" rgroup.long 0xC280++0x17 line.long 0x0 "CFG0_MCU0_LBIST_SIG,Contains expected MISR output value" hexmask.long 0x0 0.--31. 1. "MCU0_LBIST_SIG_MISR_SIG,MISR signature" line.long 0x4 "CFG0_MCU1_LBIST_SIG,Contains expected MISR output value" hexmask.long 0x4 0.--31. 1. "MCU1_LBIST_SIG_MISR_SIG,MISR signature" line.long 0x8 "CFG0_DMPAC_LBIST_SIG,Contains expected MISR output value" hexmask.long 0x8 0.--31. 1. "DMPAC_LBIST_SIG_MISR_SIG,MISR signature" line.long 0xC "CFG0_VPAC0_LBIST_SIG,Contains expected MISR output value" hexmask.long 0xC 0.--31. 1. "VPAC0_LBIST_SIG_MISR_SIG,MISR signature" line.long 0x10 "CFG0_DSP0_LBIST_SIG,Contains expected MISR output value" hexmask.long 0x10 0.--31. 1. "DSP0_LBIST_SIG_MISR_SIG,MISR signature" line.long 0x14 "CFG0_DSP1_LBIST_SIG,Contains expected MISR output value" hexmask.long 0x14 0.--31. 1. "DSP1_LBIST_SIG_MISR_SIG,MISR signature" rgroup.long 0xC2A0++0x3 line.long 0x0 "CFG0_MPU0_LBIST_SIG,Contains expected MISR output value" hexmask.long 0x0 0.--31. 1. "MPU0_LBIST_SIG_MISR_SIG,MISR signature" rgroup.long 0xC320++0x3 line.long 0x0 "CFG0_FUSE_CRC_STAT,Indicates status of fuse chain CRC" bitfld.long 0x0 31. "FUSE_CRC_STAT_AUTOLD_ERR,Indicates eFuse autoload or programmation error on any chain" "0,1" newline bitfld.long 0x0 15. "FUSE_CRC_STAT_GRP1_CRC_ERR_7,Indicates eFuse CRC error on group1 chain 7" "0,1" newline bitfld.long 0x0 14. "FUSE_CRC_STAT_GRP1_CRC_ERR_6,Indicates eFuse CRC error on group1 chain 6" "0,1" newline bitfld.long 0x0 13. "FUSE_CRC_STAT_GRP1_CRC_ERR_5,Indicates eFuse CRC error on group1 chain 5" "0,1" newline bitfld.long 0x0 12. "FUSE_CRC_STAT_GRP1_CRC_ERR_4,Indicates eFuse CRC error on group1 chain 4" "0,1" newline bitfld.long 0x0 11. "FUSE_CRC_STAT_GRP1_CRC_ERR_3,Indicates eFuse CRC error on group1 chain 3" "0,1" newline bitfld.long 0x0 10. "FUSE_CRC_STAT_GRP1_CRC_ERR_2,Indicates eFuse CRC error on group1 chain 2" "0,1" newline bitfld.long 0x0 9. "FUSE_CRC_STAT_GRP1_CRC_ERR_1,Indicates eFuse CRC error on group1 chain 1" "0,1" newline bitfld.long 0x0 8. "FUSE_CRC_STAT_GRP1_CRC_ERR_0,Indicates eFuse CRC error on group1 chain 0" "0,1" newline bitfld.long 0x0 7. "FUSE_CRC_STAT_CRC_ERR_7,Indicates eFuse CRC error on chain 7" "0,1" newline bitfld.long 0x0 6. "FUSE_CRC_STAT_CRC_ERR_6,Indicates eFuse CRC error on chain 6" "0,1" newline bitfld.long 0x0 5. "FUSE_CRC_STAT_CRC_ERR_5,Indicates eFuse CRC error on chain 5" "0,1" newline bitfld.long 0x0 4. "FUSE_CRC_STAT_CRC_ERR_4,Indicates eFuse CRC error on chain 4" "0,1" newline bitfld.long 0x0 3. "FUSE_CRC_STAT_CRC_ERR_3,Indicates eFuse CRC error on chain 3" "0,1" newline bitfld.long 0x0 2. "FUSE_CRC_STAT_CRC_ERR_2,Indicates eFuse CRC error on chain 2" "0,1" newline bitfld.long 0x0 1. "FUSE_CRC_STAT_CRC_ERR_1,Indicates eFuse CRC error on chain 1" "0,1" rgroup.long 0xD008++0x7 line.long 0x0 "CFG0_LOCK3_KICK0,This register must be written with the designated key value followed by a write to LOCK3_KICK1 with its key value before write-protected Partition 3 registers can be written." hexmask.long 0x0 0.--31. 1. "LOCK3_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK3_KICK1,This register must be written with the designated key value after a write to LOCK3_KICK0 with its key value before write-protected Partition 3 registers can be written." hexmask.long 0x4 0.--31. 1. "LOCK3_KICK1,- KICK1 component" rgroup.long 0xD100++0x37 line.long 0x0 "CFG0_CLAIMREG_P3_R0_READONLY," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P3_R0_READONLY,Claim bits for Partition 3" line.long 0x4 "CFG0_CLAIMREG_P3_R1_READONLY," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P3_R1_READONLY,Claim bits for Partition 3" line.long 0x8 "CFG0_CLAIMREG_P3_R2_READONLY," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P3_R2_READONLY,Claim bits for Partition 3" line.long 0xC "CFG0_CLAIMREG_P3_R3_READONLY," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P3_R3_READONLY,Claim bits for Partition 3" line.long 0x10 "CFG0_CLAIMREG_P3_R4_READONLY," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P3_R4_READONLY,Claim bits for Partition 3" line.long 0x14 "CFG0_CLAIMREG_P3_R5_READONLY," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P3_R5_READONLY,Claim bits for Partition 3" line.long 0x18 "CFG0_CLAIMREG_P3_R6_READONLY," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P3_R6_READONLY,Claim bits for Partition 3" line.long 0x1C "CFG0_CLAIMREG_P3_R7_READONLY," hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P3_R7_READONLY,Claim bits for Partition 3" line.long 0x20 "CFG0_CLAIMREG_P3_R8_READONLY," hexmask.long 0x20 0.--31. 1. "CLAIMREG_P3_R8_READONLY,Claim bits for Partition 3" line.long 0x24 "CFG0_CLAIMREG_P3_R9_READONLY," hexmask.long 0x24 0.--31. 1. "CLAIMREG_P3_R9_READONLY,Claim bits for Partition 3" line.long 0x28 "CFG0_CLAIMREG_P3_R10_READONLY," hexmask.long 0x28 0.--31. 1. "CLAIMREG_P3_R10_READONLY,Claim bits for Partition 3" line.long 0x2C "CFG0_CLAIMREG_P3_R11_READONLY," hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P3_R11_READONLY,Claim bits for Partition 3" line.long 0x30 "CFG0_CLAIMREG_P3_R12_READONLY," hexmask.long 0x30 0.--31. 1. "CLAIMREG_P3_R12_READONLY,Claim bits for Partition 3" line.long 0x34 "CFG0_CLAIMREG_P3_R13_READONLY," hexmask.long 0x34 0.--31. 1. "CLAIMREG_P3_R13_READONLY,Claim bits for Partition 3" rgroup.long 0xE000++0x1B line.long 0x0 "CFG0_MCU0_LBIST_CTRL_PROXY,Configures and enables LBIST operation" bitfld.long 0x0 31. "MCU0_LBIST_CTRL_BIST_RESET_PROXY,Reset LBIST macro" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "MCU0_LBIST_CTRL_BIST_RUN_PROXY,Starts LBIST if all bits are 1" newline hexmask.long.byte 0x0 12.--15. 1. "MCU0_LBIST_CTRL_RUNBIST_MODE_PROXY,Runbist mode enable if all bits are 1" newline bitfld.long 0x0 8.--9. "MCU0_LBIST_CTRL_DC_DEF_PROXY,Clock delay after scan_enable switching" "0,1,2,3" newline bitfld.long 0x0 7. "MCU0_LBIST_CTRL_LOAD_DIV_PROXY,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "MCU0_LBIST_CTRL_DIVIDE_RATIO_PROXY,LBIST clock divide ratio" line.long 0x4 "CFG0_MCU0_LBIST_PATCOUNT_PROXY,Specifies the number of LBIST patterns to run" hexmask.long.word 0x4 16.--29. 1. "MCU0_LBIST_PATCOUNT_STATIC_PC_DEF_PROXY,Number of stuck-at patterns to run" newline hexmask.long.byte 0x4 8.--11. 1. "MCU0_LBIST_PATCOUNT_SET_PC_DEF_PROXY,Number of set patterns to run" newline hexmask.long.byte 0x4 4.--7. 1. "MCU0_LBIST_PATCOUNT_RESET_PC_DEF_PROXY,Number of reset patterns to run" newline hexmask.long.byte 0x4 0.--3. 1. "MCU0_LBIST_PATCOUNT_SCAN_PC_DEF_PROXY,Number of chain test patterns to run" line.long 0x8 "CFG0_MCU0_LBIST_SEED0_PROXY,Specifies the 32 LSBs of the PRPG seed" hexmask.long 0x8 0.--31. 1. "MCU0_LBIST_SEED0_PRPG_DEF_PROXY,Initial seed for PRPG (bits 31:0)" line.long 0xC "CFG0_MCU0_LBIST_SEED1_PROXY,Specifies the 21 MSBs of the PRPG seed" hexmask.long.tbyte 0xC 0.--20. 1. "MCU0_LBIST_SEED1_PRPG_DEF_PROXY,Initial seed for PRPG (bits 52:32)" line.long 0x10 "CFG0_MCU0_LBIST_SPARE0_PROXY,Spare LBIST control bits" hexmask.long 0x10 2.--31. 1. "MCU0_LBIST_SPARE0_SPARE0_PROXY,LBIST spare bits" newline bitfld.long 0x10 1. "MCU0_LBIST_SPARE0_PBIST_SELFTEST_EN_PROXY,PBIST isolation control" "0,1" newline bitfld.long 0x10 0. "MCU0_LBIST_SPARE0_LBIST_SELFTEST_EN_PROXY,LBIST isolation control" "0,1" line.long 0x14 "CFG0_MCU0_LBIST_SPARE1_PROXY,Spare LBIST control bits" hexmask.long 0x14 0.--31. 1. "MCU0_LBIST_SPARE1_SPARE1_PROXY,LBIST spare bits" line.long 0x18 "CFG0_MCU0_LBIST_STAT_PROXY,Indicates LBIST status and provides MISR selection control" rbitfld.long 0x18 31. "MCU0_LBIST_STAT_BIST_DONE_PROXY,LBIST is done" "0,1" newline rbitfld.long 0x18 15. "MCU0_LBIST_STAT_BIST_RUNNING_PROXY,LBIST is running" "0,1" newline bitfld.long 0x18 8.--9. "MCU0_LBIST_STAT_OUT_MUX_CTL_PROXY,Selects source of LBIST output 00 - LBIST IP PID value 01 - LBIST CTRL ID value 1x - MISR value" "0: LBIST IP PID value 01,?,?,?" newline hexmask.long.byte 0x18 0.--7. 1. "MCU0_LBIST_STAT_MISR_MUX_CTL_PROXY,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR." rgroup.long 0xE01C++0x3 line.long 0x0 "CFG0_MCU0_LBIST_MISR_PROXY,Contains LBIST MISR output value" hexmask.long 0x0 0.--31. 1. "MCU0_LBIST_MISR_MISR_RESULT_PROXY,32-bits of MISR value selected by misr_mux_ctl" rgroup.long 0xE020++0x1B line.long 0x0 "CFG0_MCU1_LBIST_CTRL_PROXY,Configures and enables LBIST operation" bitfld.long 0x0 31. "MCU1_LBIST_CTRL_BIST_RESET_PROXY,Reset LBIST macro" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "MCU1_LBIST_CTRL_BIST_RUN_PROXY,Starts LBIST if all bits are 1" newline hexmask.long.byte 0x0 12.--15. 1. "MCU1_LBIST_CTRL_RUNBIST_MODE_PROXY,Runbist mode enable if all bits are 1" newline bitfld.long 0x0 8.--9. "MCU1_LBIST_CTRL_DC_DEF_PROXY,Clock delay after scan_enable switching" "0,1,2,3" newline bitfld.long 0x0 7. "MCU1_LBIST_CTRL_LOAD_DIV_PROXY,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "MCU1_LBIST_CTRL_DIVIDE_RATIO_PROXY,LBIST clock divide ratio" line.long 0x4 "CFG0_MCU1_LBIST_PATCOUNT_PROXY,Specifies the number of LBIST patterns to run" hexmask.long.word 0x4 16.--29. 1. "MCU1_LBIST_PATCOUNT_STATIC_PC_DEF_PROXY,Number of stuck-at patterns to run" newline hexmask.long.byte 0x4 8.--11. 1. "MCU1_LBIST_PATCOUNT_SET_PC_DEF_PROXY,Number of set patterns to run" newline hexmask.long.byte 0x4 4.--7. 1. "MCU1_LBIST_PATCOUNT_RESET_PC_DEF_PROXY,Number of reset patterns to run" newline hexmask.long.byte 0x4 0.--3. 1. "MCU1_LBIST_PATCOUNT_SCAN_PC_DEF_PROXY,Number of chain test patterns to run" line.long 0x8 "CFG0_MCU1_LBIST_SEED0_PROXY,Specifies the 32 LSBs of the PRPG seed" hexmask.long 0x8 0.--31. 1. "MCU1_LBIST_SEED0_PRPG_DEF_PROXY,Initial seed for PRPG (bits 31:0)" line.long 0xC "CFG0_MCU1_LBIST_SEED1_PROXY,Specifies the 21 MSBs of the PRPG seed" hexmask.long.tbyte 0xC 0.--20. 1. "MCU1_LBIST_SEED1_PRPG_DEF_PROXY,Initial seed for PRPG (bits 52:32)" line.long 0x10 "CFG0_MCU1_LBIST_SPARE0_PROXY,Spare LBIST control bits" hexmask.long 0x10 2.--31. 1. "MCU1_LBIST_SPARE0_SPARE0_PROXY,LBIST spare bits" newline bitfld.long 0x10 1. "MCU1_LBIST_SPARE0_PBIST_SELFTEST_EN_PROXY,PBIST isolation control" "0,1" newline bitfld.long 0x10 0. "MCU1_LBIST_SPARE0_LBIST_SELFTEST_EN_PROXY,LBIST isolation control" "0,1" line.long 0x14 "CFG0_MCU1_LBIST_SPARE1_PROXY,Spare LBIST control bits" hexmask.long 0x14 0.--31. 1. "MCU1_LBIST_SPARE1_SPARE1_PROXY,LBIST spare bits" line.long 0x18 "CFG0_MCU1_LBIST_STAT_PROXY,Indicates LBIST status and provides MISR selection control" rbitfld.long 0x18 31. "MCU1_LBIST_STAT_BIST_DONE_PROXY,LBIST is done" "0,1" newline rbitfld.long 0x18 15. "MCU1_LBIST_STAT_BIST_RUNNING_PROXY,LBIST is running" "0,1" newline bitfld.long 0x18 8.--9. "MCU1_LBIST_STAT_OUT_MUX_CTL_PROXY,Selects source of LBIST output 00 - LBIST IP PID value 01 - LBIST CTRL ID value 1x - MISR value" "0: LBIST IP PID value 01,?,?,?" newline hexmask.long.byte 0x18 0.--7. 1. "MCU1_LBIST_STAT_MISR_MUX_CTL_PROXY,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR." rgroup.long 0xE03C++0x3 line.long 0x0 "CFG0_MCU1_LBIST_MISR_PROXY,Contains LBIST MISR output value" hexmask.long 0x0 0.--31. 1. "MCU1_LBIST_MISR_MISR_RESULT_PROXY,32-bits of MISR value selected by misr_mux_ctl" rgroup.long 0xE040++0x1B line.long 0x0 "CFG0_DMPAC_LBIST_CTRL_PROXY,Configures and enables LBIST operation" bitfld.long 0x0 31. "DMPAC_LBIST_CTRL_BIST_RESET_PROXY,Reset LBIST macro" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "DMPAC_LBIST_CTRL_BIST_RUN_PROXY,Starts LBIST if all bits are 1" newline hexmask.long.byte 0x0 12.--15. 1. "DMPAC_LBIST_CTRL_RUNBIST_MODE_PROXY,Runbist mode enable if all bits are 1" newline bitfld.long 0x0 8.--9. "DMPAC_LBIST_CTRL_DC_DEF_PROXY,Clock delay after scan_enable switching" "0,1,2,3" newline bitfld.long 0x0 7. "DMPAC_LBIST_CTRL_LOAD_DIV_PROXY,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "DMPAC_LBIST_CTRL_DIVIDE_RATIO_PROXY,LBIST clock divide ratio" line.long 0x4 "CFG0_DMPAC_LBIST_PATCOUNT_PROXY,Specifies the number of LBIST patterns to run" hexmask.long.word 0x4 16.--29. 1. "DMPAC_LBIST_PATCOUNT_STATIC_PC_DEF_PROXY,Number of stuck-at patterns to run" newline hexmask.long.byte 0x4 8.--11. 1. "DMPAC_LBIST_PATCOUNT_SET_PC_DEF_PROXY,Number of set patterns to run" newline hexmask.long.byte 0x4 4.--7. 1. "DMPAC_LBIST_PATCOUNT_RESET_PC_DEF_PROXY,Number of reset patterns to run" newline hexmask.long.byte 0x4 0.--3. 1. "DMPAC_LBIST_PATCOUNT_SCAN_PC_DEF_PROXY,Number of chain test patterns to run" line.long 0x8 "CFG0_DMPAC_LBIST_SEED0_PROXY,Specifies the 32 LSBs of the PRPG seed" hexmask.long 0x8 0.--31. 1. "DMPAC_LBIST_SEED0_PRPG_DEF_PROXY,Initial seed for PRPG (bits 31:0)" line.long 0xC "CFG0_DMPAC_LBIST_SEED1_PROXY,Specifies the 21 MSBs of the PRPG seed" hexmask.long.tbyte 0xC 0.--20. 1. "DMPAC_LBIST_SEED1_PRPG_DEF_PROXY,Initial seed for PRPG (bits 52:32)" line.long 0x10 "CFG0_DMPAC_LBIST_SPARE0_PROXY,Spare LBIST control bits" hexmask.long 0x10 2.--31. 1. "DMPAC_LBIST_SPARE0_SPARE0_PROXY,LBIST spare bits" newline bitfld.long 0x10 1. "DMPAC_LBIST_SPARE0_PBIST_SELFTEST_EN_PROXY,PBIST isolation control" "0,1" newline bitfld.long 0x10 0. "DMPAC_LBIST_SPARE0_LBIST_SELFTEST_EN_PROXY,LBIST isolation control" "0,1" line.long 0x14 "CFG0_DMPAC_LBIST_SPARE1_PROXY,Spare LBIST control bits" hexmask.long 0x14 0.--31. 1. "DMPAC_LBIST_SPARE1_SPARE1_PROXY,LBIST spare bits" line.long 0x18 "CFG0_DMPAC_LBIST_STAT_PROXY,Indicates LBIST status and provides MISR selection control" rbitfld.long 0x18 31. "DMPAC_LBIST_STAT_BIST_DONE_PROXY,LBIST is done" "0,1" newline rbitfld.long 0x18 15. "DMPAC_LBIST_STAT_BIST_RUNNING_PROXY,LBIST is running" "0,1" newline bitfld.long 0x18 8.--9. "DMPAC_LBIST_STAT_OUT_MUX_CTL_PROXY,Selects source of LBIST output 00 - LBIST IP PID value 01 - LBIST CTRL ID value 1x - MISR value" "0: LBIST IP PID value 01,?,?,?" newline hexmask.long.byte 0x18 0.--7. 1. "DMPAC_LBIST_STAT_MISR_MUX_CTL_PROXY,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR." rgroup.long 0xE05C++0x3 line.long 0x0 "CFG0_DMPAC_LBIST_MISR_PROXY,Contains LBIST MISR output value" hexmask.long 0x0 0.--31. 1. "DMPAC_LBIST_MISR_MISR_RESULT_PROXY,32-bits of MISR value selected by misr_mux_ctl" rgroup.long 0xE060++0x1B line.long 0x0 "CFG0_VPAC0_LBIST_CTRL_PROXY,Configures and enables LBIST operation" bitfld.long 0x0 31. "VPAC0_LBIST_CTRL_BIST_RESET_PROXY,Reset LBIST macro" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "VPAC0_LBIST_CTRL_BIST_RUN_PROXY,Starts LBIST if all bits are 1" newline hexmask.long.byte 0x0 12.--15. 1. "VPAC0_LBIST_CTRL_RUNBIST_MODE_PROXY,Runbist mode enable if all bits are 1" newline bitfld.long 0x0 8.--9. "VPAC0_LBIST_CTRL_DC_DEF_PROXY,Clock delay after scan_enable switching" "0,1,2,3" newline bitfld.long 0x0 7. "VPAC0_LBIST_CTRL_LOAD_DIV_PROXY,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "VPAC0_LBIST_CTRL_DIVIDE_RATIO_PROXY,LBIST clock divide ratio" line.long 0x4 "CFG0_VPAC0_LBIST_PATCOUNT_PROXY,Specifies the number of LBIST patterns to run" hexmask.long.word 0x4 16.--29. 1. "VPAC0_LBIST_PATCOUNT_STATIC_PC_DEF_PROXY,Number of stuck-at patterns to run" newline hexmask.long.byte 0x4 8.--11. 1. "VPAC0_LBIST_PATCOUNT_SET_PC_DEF_PROXY,Number of set patterns to run" newline hexmask.long.byte 0x4 4.--7. 1. "VPAC0_LBIST_PATCOUNT_RESET_PC_DEF_PROXY,Number of reset patterns to run" newline hexmask.long.byte 0x4 0.--3. 1. "VPAC0_LBIST_PATCOUNT_SCAN_PC_DEF_PROXY,Number of chain test patterns to run" line.long 0x8 "CFG0_VPAC0_LBIST_SEED0_PROXY,Specifies the 32 LSBs of the PRPG seed" hexmask.long 0x8 0.--31. 1. "VPAC0_LBIST_SEED0_PRPG_DEF_PROXY,Initial seed for PRPG (bits 31:0)" line.long 0xC "CFG0_VPAC0_LBIST_SEED1_PROXY,Specifies the 21 MSBs of the PRPG seed" hexmask.long.tbyte 0xC 0.--20. 1. "VPAC0_LBIST_SEED1_PRPG_DEF_PROXY,Initial seed for PRPG (bits 52:32)" line.long 0x10 "CFG0_VPAC0_LBIST_SPARE0_PROXY,Spare LBIST control bits" hexmask.long 0x10 2.--31. 1. "VPAC0_LBIST_SPARE0_SPARE0_PROXY,LBIST spare bits" newline bitfld.long 0x10 1. "VPAC0_LBIST_SPARE0_PBIST_SELFTEST_EN_PROXY,PBIST isolation control" "0,1" newline bitfld.long 0x10 0. "VPAC0_LBIST_SPARE0_LBIST_SELFTEST_EN_PROXY,LBIST isolation control" "0,1" line.long 0x14 "CFG0_VPAC0_LBIST_SPARE1_PROXY,Spare LBIST control bits" hexmask.long 0x14 0.--31. 1. "VPAC0_LBIST_SPARE1_SPARE1_PROXY,LBIST spare bits" line.long 0x18 "CFG0_VPAC0_LBIST_STAT_PROXY,Indicates LBIST status and provides MISR selection control" rbitfld.long 0x18 31. "VPAC0_LBIST_STAT_BIST_DONE_PROXY,LBIST is done" "0,1" newline rbitfld.long 0x18 15. "VPAC0_LBIST_STAT_BIST_RUNNING_PROXY,LBIST is running" "0,1" newline bitfld.long 0x18 8.--9. "VPAC0_LBIST_STAT_OUT_MUX_CTL_PROXY,Selects source of LBIST output 00 - LBIST IP PID value 01 - LBIST CTRL ID value 1x - MISR value" "0: LBIST IP PID value 01,?,?,?" newline hexmask.long.byte 0x18 0.--7. 1. "VPAC0_LBIST_STAT_MISR_MUX_CTL_PROXY,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR." rgroup.long 0xE07C++0x3 line.long 0x0 "CFG0_VPAC0_LBIST_MISR_PROXY,Contains LBIST MISR output value" hexmask.long 0x0 0.--31. 1. "VPAC0_LBIST_MISR_MISR_RESULT_PROXY,32-bits of MISR value selected by misr_mux_ctl" rgroup.long 0xE080++0x1B line.long 0x0 "CFG0_DSP0_LBIST_CTRL_PROXY,Configures and enables LBIST operation" bitfld.long 0x0 31. "DSP0_LBIST_CTRL_BIST_RESET_PROXY,Reset LBIST macro" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "DSP0_LBIST_CTRL_BIST_RUN_PROXY,Starts LBIST if all bits are 1" newline hexmask.long.byte 0x0 12.--15. 1. "DSP0_LBIST_CTRL_RUNBIST_MODE_PROXY,Runbist mode enable if all bits are 1" newline bitfld.long 0x0 8.--9. "DSP0_LBIST_CTRL_DC_DEF_PROXY,Clock delay after scan_enable switching" "0,1,2,3" newline bitfld.long 0x0 7. "DSP0_LBIST_CTRL_LOAD_DIV_PROXY,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "DSP0_LBIST_CTRL_DIVIDE_RATIO_PROXY,LBIST clock divide ratio" line.long 0x4 "CFG0_DSP0_LBIST_PATCOUNT_PROXY,Specifies the number of LBIST patterns to run" hexmask.long.word 0x4 16.--29. 1. "DSP0_LBIST_PATCOUNT_STATIC_PC_DEF_PROXY,Number of stuck-at patterns to run" newline hexmask.long.byte 0x4 8.--11. 1. "DSP0_LBIST_PATCOUNT_SET_PC_DEF_PROXY,Number of set patterns to run" newline hexmask.long.byte 0x4 4.--7. 1. "DSP0_LBIST_PATCOUNT_RESET_PC_DEF_PROXY,Number of reset patterns to run" newline hexmask.long.byte 0x4 0.--3. 1. "DSP0_LBIST_PATCOUNT_SCAN_PC_DEF_PROXY,Number of chain test patterns to run" line.long 0x8 "CFG0_DSP0_LBIST_SEED0_PROXY,Specifies the 32 LSBs of the PRPG seed" hexmask.long 0x8 0.--31. 1. "DSP0_LBIST_SEED0_PRPG_DEF_PROXY,Initial seed for PRPG (bits 31:0)" line.long 0xC "CFG0_DSP0_LBIST_SEED1_PROXY,Specifies the 21 MSBs of the PRPG seed" hexmask.long.tbyte 0xC 0.--20. 1. "DSP0_LBIST_SEED1_PRPG_DEF_PROXY,Initial seed for PRPG (bits 52:32)" line.long 0x10 "CFG0_DSP0_LBIST_SPARE0_PROXY,Spare LBIST control bits" hexmask.long 0x10 2.--31. 1. "DSP0_LBIST_SPARE0_SPARE0_PROXY,LBIST spare bits" newline bitfld.long 0x10 1. "DSP0_LBIST_SPARE0_PBIST_SELFTEST_EN_PROXY,PBIST isolation control" "0,1" newline bitfld.long 0x10 0. "DSP0_LBIST_SPARE0_LBIST_SELFTEST_EN_PROXY,LBIST isolation control" "0,1" line.long 0x14 "CFG0_DSP0_LBIST_SPARE1_PROXY,Spare LBIST control bits" hexmask.long 0x14 0.--31. 1. "DSP0_LBIST_SPARE1_SPARE1_PROXY,LBIST spare bits" line.long 0x18 "CFG0_DSP0_LBIST_STAT_PROXY,Indicates LBIST status and provides MISR selection control" rbitfld.long 0x18 31. "DSP0_LBIST_STAT_BIST_DONE_PROXY,LBIST is done" "0,1" newline rbitfld.long 0x18 15. "DSP0_LBIST_STAT_BIST_RUNNING_PROXY,LBIST is running" "0,1" newline bitfld.long 0x18 8.--9. "DSP0_LBIST_STAT_OUT_MUX_CTL_PROXY,Selects source of LBIST output 00 - LBIST IP PID value 01 - LBIST CTRL ID value 1x - MISR value" "0: LBIST IP PID value 01,?,?,?" newline hexmask.long.byte 0x18 0.--7. 1. "DSP0_LBIST_STAT_MISR_MUX_CTL_PROXY,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR." rgroup.long 0xE09C++0x3 line.long 0x0 "CFG0_DSP0_LBIST_MISR_PROXY,Contains LBIST MISR output value" hexmask.long 0x0 0.--31. 1. "DSP0_LBIST_MISR_MISR_RESULT_PROXY,32-bits of MISR value selected by misr_mux_ctl" rgroup.long 0xE0A0++0x1B line.long 0x0 "CFG0_DSP1_LBIST_CTRL_PROXY,Configures and enables LBIST operation" bitfld.long 0x0 31. "DSP1_LBIST_CTRL_BIST_RESET_PROXY,Reset LBIST macro" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "DSP1_LBIST_CTRL_BIST_RUN_PROXY,Starts LBIST if all bits are 1" newline hexmask.long.byte 0x0 12.--15. 1. "DSP1_LBIST_CTRL_RUNBIST_MODE_PROXY,Runbist mode enable if all bits are 1" newline bitfld.long 0x0 8.--9. "DSP1_LBIST_CTRL_DC_DEF_PROXY,Clock delay after scan_enable switching" "0,1,2,3" newline bitfld.long 0x0 7. "DSP1_LBIST_CTRL_LOAD_DIV_PROXY,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "DSP1_LBIST_CTRL_DIVIDE_RATIO_PROXY,LBIST clock divide ratio" line.long 0x4 "CFG0_DSP1_LBIST_PATCOUNT_PROXY,Specifies the number of LBIST patterns to run" hexmask.long.word 0x4 16.--29. 1. "DSP1_LBIST_PATCOUNT_STATIC_PC_DEF_PROXY,Number of stuck-at patterns to run" newline hexmask.long.byte 0x4 8.--11. 1. "DSP1_LBIST_PATCOUNT_SET_PC_DEF_PROXY,Number of set patterns to run" newline hexmask.long.byte 0x4 4.--7. 1. "DSP1_LBIST_PATCOUNT_RESET_PC_DEF_PROXY,Number of reset patterns to run" newline hexmask.long.byte 0x4 0.--3. 1. "DSP1_LBIST_PATCOUNT_SCAN_PC_DEF_PROXY,Number of chain test patterns to run" line.long 0x8 "CFG0_DSP1_LBIST_SEED0_PROXY,Specifies the 32 LSBs of the PRPG seed" hexmask.long 0x8 0.--31. 1. "DSP1_LBIST_SEED0_PRPG_DEF_PROXY,Initial seed for PRPG (bits 31:0)" line.long 0xC "CFG0_DSP1_LBIST_SEED1_PROXY,Specifies the 21 MSBs of the PRPG seed" hexmask.long.tbyte 0xC 0.--20. 1. "DSP1_LBIST_SEED1_PRPG_DEF_PROXY,Initial seed for PRPG (bits 52:32)" line.long 0x10 "CFG0_DSP1_LBIST_SPARE0_PROXY,Spare LBIST control bits" hexmask.long 0x10 2.--31. 1. "DSP1_LBIST_SPARE0_SPARE0_PROXY,LBIST spare bits" newline bitfld.long 0x10 1. "DSP1_LBIST_SPARE0_PBIST_SELFTEST_EN_PROXY,PBIST isolation control" "0,1" newline bitfld.long 0x10 0. "DSP1_LBIST_SPARE0_LBIST_SELFTEST_EN_PROXY,LBIST isolation control" "0,1" line.long 0x14 "CFG0_DSP1_LBIST_SPARE1_PROXY,Spare LBIST control bits" hexmask.long 0x14 0.--31. 1. "DSP1_LBIST_SPARE1_SPARE1_PROXY,LBIST spare bits" line.long 0x18 "CFG0_DSP1_LBIST_STAT_PROXY,Indicates LBIST status and provides MISR selection control" rbitfld.long 0x18 31. "DSP1_LBIST_STAT_BIST_DONE_PROXY,LBIST is done" "0,1" newline rbitfld.long 0x18 15. "DSP1_LBIST_STAT_BIST_RUNNING_PROXY,LBIST is running" "0,1" newline bitfld.long 0x18 8.--9. "DSP1_LBIST_STAT_OUT_MUX_CTL_PROXY,Selects source of LBIST output 00 - LBIST IP PID value 01 - LBIST CTRL ID value 1x - MISR value" "0: LBIST IP PID value 01,?,?,?" newline hexmask.long.byte 0x18 0.--7. 1. "DSP1_LBIST_STAT_MISR_MUX_CTL_PROXY,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR." rgroup.long 0xE0BC++0x3 line.long 0x0 "CFG0_DSP1_LBIST_MISR_PROXY,Contains LBIST MISR output value" hexmask.long 0x0 0.--31. 1. "DSP1_LBIST_MISR_MISR_RESULT_PROXY,32-bits of MISR value selected by misr_mux_ctl" rgroup.long 0xE100++0x1B line.long 0x0 "CFG0_MPU0_LBIST_CTRL_PROXY,Configures and enables LBIST operation" bitfld.long 0x0 31. "MPU0_LBIST_CTRL_BIST_RESET_PROXY,Reset LBIST macro" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "MPU0_LBIST_CTRL_BIST_RUN_PROXY,Starts LBIST if all bits are 1" newline hexmask.long.byte 0x0 12.--15. 1. "MPU0_LBIST_CTRL_RUNBIST_MODE_PROXY,Runbist mode enable if all bits are 1" newline bitfld.long 0x0 8.--9. "MPU0_LBIST_CTRL_DC_DEF_PROXY,Clock delay after scan_enable switching" "0,1,2,3" newline bitfld.long 0x0 7. "MPU0_LBIST_CTRL_LOAD_DIV_PROXY,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "MPU0_LBIST_CTRL_DIVIDE_RATIO_PROXY,LBIST clock divide ratio" line.long 0x4 "CFG0_MPU0_LBIST_PATCOUNT_PROXY,Specifies the number of LBIST patterns to run" hexmask.long.word 0x4 16.--29. 1. "MPU0_LBIST_PATCOUNT_STATIC_PC_DEF_PROXY,Number of stuck-at patterns to run" newline hexmask.long.byte 0x4 8.--11. 1. "MPU0_LBIST_PATCOUNT_SET_PC_DEF_PROXY,Number of set patterns to run" newline hexmask.long.byte 0x4 4.--7. 1. "MPU0_LBIST_PATCOUNT_RESET_PC_DEF_PROXY,Number of reset patterns to run" newline hexmask.long.byte 0x4 0.--3. 1. "MPU0_LBIST_PATCOUNT_SCAN_PC_DEF_PROXY,Number of chain test patterns to run" line.long 0x8 "CFG0_MPU0_LBIST_SEED0_PROXY,Specifies the 32 LSBs of the PRPG seed" hexmask.long 0x8 0.--31. 1. "MPU0_LBIST_SEED0_PRPG_DEF_PROXY,Initial seed for PRPG (bits 31:0)" line.long 0xC "CFG0_MPU0_LBIST_SEED1_PROXY,Specifies the 21 MSBs of the PRPG seed" hexmask.long.tbyte 0xC 0.--20. 1. "MPU0_LBIST_SEED1_PRPG_DEF_PROXY,Initial seed for PRPG (bits 52:32)" line.long 0x10 "CFG0_MPU0_LBIST_SPARE0_PROXY,Spare LBIST control bits" hexmask.long 0x10 2.--31. 1. "MPU0_LBIST_SPARE0_SPARE0_PROXY,LBIST spare bits" newline bitfld.long 0x10 1. "MPU0_LBIST_SPARE0_PBIST_SELFTEST_EN_PROXY,PBIST isolation control" "0,1" newline bitfld.long 0x10 0. "MPU0_LBIST_SPARE0_LBIST_SELFTEST_EN_PROXY,LBIST isolation control" "0,1" line.long 0x14 "CFG0_MPU0_LBIST_SPARE1_PROXY,Spare LBIST control bits" hexmask.long 0x14 0.--31. 1. "MPU0_LBIST_SPARE1_SPARE1_PROXY,LBIST spare bits" line.long 0x18 "CFG0_MPU0_LBIST_STAT_PROXY,Indicates LBIST status and provides MISR selection control" rbitfld.long 0x18 31. "MPU0_LBIST_STAT_BIST_DONE_PROXY,LBIST is done" "0,1" newline rbitfld.long 0x18 15. "MPU0_LBIST_STAT_BIST_RUNNING_PROXY,LBIST is running" "0,1" newline bitfld.long 0x18 8.--9. "MPU0_LBIST_STAT_OUT_MUX_CTL_PROXY,Selects source of LBIST output 00 - LBIST IP PID value 01 - LBIST CTRL ID value 1x - MISR value" "0: LBIST IP PID value 01,?,?,?" newline hexmask.long.byte 0x18 0.--7. 1. "MPU0_LBIST_STAT_MISR_MUX_CTL_PROXY,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR." rgroup.long 0xE11C++0x3 line.long 0x0 "CFG0_MPU0_LBIST_MISR_PROXY,Contains LBIST MISR output value" hexmask.long 0x0 0.--31. 1. "MPU0_LBIST_MISR_MISR_RESULT_PROXY,32-bits of MISR value selected by misr_mux_ctl" rgroup.long 0xE280++0x17 line.long 0x0 "CFG0_MCU0_LBIST_SIG_PROXY,Contains expected MISR output value" hexmask.long 0x0 0.--31. 1. "MCU0_LBIST_SIG_MISR_SIG_PROXY,MISR signature" line.long 0x4 "CFG0_MCU1_LBIST_SIG_PROXY,Contains expected MISR output value" hexmask.long 0x4 0.--31. 1. "MCU1_LBIST_SIG_MISR_SIG_PROXY,MISR signature" line.long 0x8 "CFG0_DMPAC_LBIST_SIG_PROXY,Contains expected MISR output value" hexmask.long 0x8 0.--31. 1. "DMPAC_LBIST_SIG_MISR_SIG_PROXY,MISR signature" line.long 0xC "CFG0_VPAC0_LBIST_SIG_PROXY,Contains expected MISR output value" hexmask.long 0xC 0.--31. 1. "VPAC0_LBIST_SIG_MISR_SIG_PROXY,MISR signature" line.long 0x10 "CFG0_DSP0_LBIST_SIG_PROXY,Contains expected MISR output value" hexmask.long 0x10 0.--31. 1. "DSP0_LBIST_SIG_MISR_SIG_PROXY,MISR signature" line.long 0x14 "CFG0_DSP1_LBIST_SIG_PROXY,Contains expected MISR output value" hexmask.long 0x14 0.--31. 1. "DSP1_LBIST_SIG_MISR_SIG_PROXY,MISR signature" rgroup.long 0xE2A0++0x3 line.long 0x0 "CFG0_MPU0_LBIST_SIG_PROXY,Contains expected MISR output value" hexmask.long 0x0 0.--31. 1. "MPU0_LBIST_SIG_MISR_SIG_PROXY,MISR signature" rgroup.long 0xE320++0x3 line.long 0x0 "CFG0_FUSE_CRC_STAT_PROXY,Indicates status of fuse chain CRC" bitfld.long 0x0 31. "FUSE_CRC_STAT_AUTOLD_ERR_PROXY,Indicates eFuse autoload or programmation error on any chain" "0,1" newline bitfld.long 0x0 15. "FUSE_CRC_STAT_GRP1_CRC_ERR_7_PROXY,Indicates eFuse CRC error on group1 chain 7" "0,1" newline bitfld.long 0x0 14. "FUSE_CRC_STAT_GRP1_CRC_ERR_6_PROXY,Indicates eFuse CRC error on group1 chain 6" "0,1" newline bitfld.long 0x0 13. "FUSE_CRC_STAT_GRP1_CRC_ERR_5_PROXY,Indicates eFuse CRC error on group1 chain 5" "0,1" newline bitfld.long 0x0 12. "FUSE_CRC_STAT_GRP1_CRC_ERR_4_PROXY,Indicates eFuse CRC error on group1 chain 4" "0,1" newline bitfld.long 0x0 11. "FUSE_CRC_STAT_GRP1_CRC_ERR_3_PROXY,Indicates eFuse CRC error on group1 chain 3" "0,1" newline bitfld.long 0x0 10. "FUSE_CRC_STAT_GRP1_CRC_ERR_2_PROXY,Indicates eFuse CRC error on group1 chain 2" "0,1" newline bitfld.long 0x0 9. "FUSE_CRC_STAT_GRP1_CRC_ERR_1_PROXY,Indicates eFuse CRC error on group1 chain 1" "0,1" newline bitfld.long 0x0 8. "FUSE_CRC_STAT_GRP1_CRC_ERR_0_PROXY,Indicates eFuse CRC error on group1 chain 0" "0,1" newline bitfld.long 0x0 7. "FUSE_CRC_STAT_CRC_ERR_7_PROXY,Indicates eFuse CRC error on chain 7" "0,1" newline bitfld.long 0x0 6. "FUSE_CRC_STAT_CRC_ERR_6_PROXY,Indicates eFuse CRC error on chain 6" "0,1" newline bitfld.long 0x0 5. "FUSE_CRC_STAT_CRC_ERR_5_PROXY,Indicates eFuse CRC error on chain 5" "0,1" newline bitfld.long 0x0 4. "FUSE_CRC_STAT_CRC_ERR_4_PROXY,Indicates eFuse CRC error on chain 4" "0,1" newline bitfld.long 0x0 3. "FUSE_CRC_STAT_CRC_ERR_3_PROXY,Indicates eFuse CRC error on chain 3" "0,1" newline bitfld.long 0x0 2. "FUSE_CRC_STAT_CRC_ERR_2_PROXY,Indicates eFuse CRC error on chain 2" "0,1" newline bitfld.long 0x0 1. "FUSE_CRC_STAT_CRC_ERR_1_PROXY,Indicates eFuse CRC error on chain 1" "0,1" rgroup.long 0xF008++0x7 line.long 0x0 "CFG0_LOCK3_KICK0_PROXY,This register must be written with the designated key value followed by a write to LOCK3_KICK1 with its key value before write-protected Partition 3 registers can be written." hexmask.long 0x0 0.--31. 1. "LOCK3_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK3_KICK1_PROXY,This register must be written with the designated key value after a write to LOCK3_KICK0 with its key value before write-protected Partition 3 registers can be written." hexmask.long 0x4 0.--31. 1. "LOCK3_KICK1_PROXY,- KICK1 component" rgroup.long 0xF100++0x37 line.long 0x0 "CFG0_CLAIMREG_P3_R0," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P3_R0,Claim bits for Partition 3" line.long 0x4 "CFG0_CLAIMREG_P3_R1," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P3_R1,Claim bits for Partition 3" line.long 0x8 "CFG0_CLAIMREG_P3_R2," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P3_R2,Claim bits for Partition 3" line.long 0xC "CFG0_CLAIMREG_P3_R3," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P3_R3,Claim bits for Partition 3" line.long 0x10 "CFG0_CLAIMREG_P3_R4," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P3_R4,Claim bits for Partition 3" line.long 0x14 "CFG0_CLAIMREG_P3_R5," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P3_R5,Claim bits for Partition 3" line.long 0x18 "CFG0_CLAIMREG_P3_R6," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P3_R6,Claim bits for Partition 3" line.long 0x1C "CFG0_CLAIMREG_P3_R7," hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P3_R7,Claim bits for Partition 3" line.long 0x20 "CFG0_CLAIMREG_P3_R8," hexmask.long 0x20 0.--31. 1. "CLAIMREG_P3_R8,Claim bits for Partition 3" line.long 0x24 "CFG0_CLAIMREG_P3_R9," hexmask.long 0x24 0.--31. 1. "CLAIMREG_P3_R9,Claim bits for Partition 3" line.long 0x28 "CFG0_CLAIMREG_P3_R10," hexmask.long 0x28 0.--31. 1. "CLAIMREG_P3_R10,Claim bits for Partition 3" line.long 0x2C "CFG0_CLAIMREG_P3_R11," hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P3_R11,Claim bits for Partition 3" line.long 0x30 "CFG0_CLAIMREG_P3_R12," hexmask.long 0x30 0.--31. 1. "CLAIMREG_P3_R12,Claim bits for Partition 3" line.long 0x34 "CFG0_CLAIMREG_P3_R13," hexmask.long 0x34 0.--31. 1. "CLAIMREG_P3_R13,Claim bits for Partition 3" rgroup.long 0x10000++0x1F line.long 0x0 "CFG0_DV_REG0,Register for general purpose DV use." hexmask.long 0x0 0.--31. 1. "DV_REG0_BIT,Defined by DV usage" line.long 0x4 "CFG0_DV_REG1,Register for general purpose DV use." hexmask.long 0x4 0.--31. 1. "DV_REG1_BIT,Defined by DV usage" line.long 0x8 "CFG0_DV_REG2,Register for general purpose DV use." hexmask.long 0x8 0.--31. 1. "DV_REG2_BIT,Defined by DV usage" line.long 0xC "CFG0_DV_REG3,Register for general purpose DV use." hexmask.long 0xC 0.--31. 1. "DV_REG3_BIT,Defined by DV usage" line.long 0x10 "CFG0_DV_REG4,Register for general purpose DV use." hexmask.long 0x10 0.--31. 1. "DV_REG4_BIT,Defined by DV usage" line.long 0x14 "CFG0_DV_REG5,Register for general purpose DV use." hexmask.long 0x14 0.--31. 1. "DV_REG5_BIT,Defined by DV usage" line.long 0x18 "CFG0_DV_REG6,Register for general purpose DV use." hexmask.long 0x18 0.--31. 1. "DV_REG6_BIT,Defined by DV usage" line.long 0x1C "CFG0_DV_REG7,Register for general purpose DV use." hexmask.long 0x1C 0.--31. 1. "DV_REG7_BIT,Defined by DV usage" rgroup.long 0x10200++0xF line.long 0x0 "CFG0_DV_REG0_SET,Set register for DV use" hexmask.long 0x0 0.--31. 1. "DV_REG0_SET_BIT,Defined by DV usage" line.long 0x4 "CFG0_DV_REG1_SET,Set register for DV use" hexmask.long 0x4 0.--31. 1. "DV_REG1_SET_BIT,Defined by DV usage" line.long 0x8 "CFG0_DV_REG2_SET,Set register for DV use" hexmask.long 0x8 0.--31. 1. "DV_REG2_SET_BIT,Defined by DV usage" line.long 0xC "CFG0_DV_REG3_SET,Set register for DV use" hexmask.long 0xC 0.--31. 1. "DV_REG3_SET_BIT,Defined by DV usage" rgroup.long 0x10300++0xF line.long 0x0 "CFG0_DV_REG0_CLR,Clear register for DV use" hexmask.long 0x0 0.--31. 1. "DV_REG0_CLR_BIT,Defined by DV usage" line.long 0x4 "CFG0_DV_REG1_CLR,Clear register for DV use" hexmask.long 0x4 0.--31. 1. "DV_REG1_CLR_BIT,Defined by DV usage" line.long 0x8 "CFG0_DV_REG2_CLR,Clear register for DV use" hexmask.long 0x8 0.--31. 1. "DV_REG2_CLR_BIT,Defined by DV usage" line.long 0xC "CFG0_DV_REG3_CLR,Clear register for DV use" hexmask.long 0xC 0.--31. 1. "DV_REG3_CLR_BIT,Defined by DV usage" rgroup.long 0x10500++0x27 line.long 0x0 "CFG0_AVS_CORE_MRGN_MODE0,Controls AVS domain memory margin for DFT" hexmask.long.word 0x0 0.--11. 1. "AVS_CORE_MRGN_MODE0_HS2PARF_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x4 "CFG0_AVS_CORE_MRGN_MODE1,Controls AVS domain memory margin for DFT" hexmask.long.word 0x4 0.--11. 1. "AVS_CORE_MRGN_MODE1_HDDP_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x8 "CFG0_AVS_CORE_MRGN_MODE2,Controls AVS domain memory margin for DFT" hexmask.long.word 0x8 0.--11. 1. "AVS_CORE_MRGN_MODE2_EHDSP_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0xC "CFG0_AVS_CORE_MRGN_MODE3,Controls AVS domain memory margin for DFT" hexmask.long.word 0xC 0.--11. 1. "AVS_CORE_MRGN_MODE3_HD2PRF_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x10 "CFG0_AVS_CORE_MRGN_MODE4,Controls AVS domain memory margin for DFT" hexmask.long.word 0x10 0.--11. 1. "AVS_CORE_MRGN_MODE4_UHD2PRF_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x14 "CFG0_AVS_CORE_MRGN_MODE5,Controls AVS domain memory margin for DFT" hexmask.long.word 0x14 0.--11. 1. "AVS_CORE_MRGN_MODE5_ROM_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x18 "CFG0_AVS_CORE_MRGN_MODE6,Controls AVS domain memory margin for DFT" hexmask.long.word 0x18 0.--11. 1. "AVS_CORE_MRGN_MODE6_HDSP_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x1C "CFG0_AVS_CORE_MRGN_MODE7,Controls AVS domain memory margin for DFT" hexmask.long.word 0x1C 0.--11. 1. "AVS_CORE_MRGN_MODE7_HSSP_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x20 "CFG0_AVS_CORE_MRGN_MODE8,Controls AVS domain memory margin for DFT" hexmask.long.word 0x20 0.--11. 1. "AVS_CORE_MRGN_MODE8_HD1PRF_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x24 "CFG0_AVS_CORE_MRGN_MODE9,Controls AVS domain memory margin for DFT" hexmask.long.word 0x24 0.--11. 1. "AVS_CORE_MRGN_MODE9_HS1PRF_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" rgroup.long 0x10540++0x27 line.long 0x0 "CFG0_NON_AVS_MRGN_MODE0,Controls non-AVS domain memory margin for DFT" hexmask.long.word 0x0 0.--11. 1. "NON_AVS_MRGN_MODE0_HS2PARF_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x4 "CFG0_NON_AVS_MRGN_MODE1,Controls non-AVS domain memory margin for DFT" hexmask.long.word 0x4 0.--11. 1. "NON_AVS_MRGN_MODE1_HDDP_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x8 "CFG0_NON_AVS_MRGN_MODE2,Controls non-AVS domain memory margin for DFT" hexmask.long.word 0x8 0.--11. 1. "NON_AVS_MRGN_MODE2_EHDSP_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0xC "CFG0_NON_AVS_MRGN_MODE3,Controls non-AVS domain memory margin for DFT" hexmask.long.word 0xC 0.--11. 1. "NON_AVS_MRGN_MODE3_HD2PRF_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x10 "CFG0_NON_AVS_MRGN_MODE4,Controls non-AVS domain memory margin for DFT" hexmask.long.word 0x10 0.--11. 1. "NON_AVS_MRGN_MODE4_UHD2PRF_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x14 "CFG0_NON_AVS_MRGN_MODE5,Controls non-AVS domain memory margin for DFT" hexmask.long.word 0x14 0.--11. 1. "NON_AVS_MRGN_MODE5_ROM_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x18 "CFG0_NON_AVS_MRGN_MODE6,Controls non-AVS domain memory margin for DFT" hexmask.long.word 0x18 0.--11. 1. "NON_AVS_MRGN_MODE6_HDSP_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x1C "CFG0_NON_AVS_MRGN_MODE7,Controls non-AVS domain memory margin for DFT" hexmask.long.word 0x1C 0.--11. 1. "NON_AVS_MRGN_MODE7_HSSP_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x20 "CFG0_NON_AVS_MRGN_MODE8,Controls non-AVS domain memory margin for DFT" hexmask.long.word 0x20 0.--11. 1. "NON_AVS_MRGN_MODE8_HD1PRF_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x24 "CFG0_NON_AVS_MRGN_MODE9,Controls non-AVS domain memory margin for DFT" hexmask.long.word 0x24 0.--11. 1. "NON_AVS_MRGN_MODE9_HS1PRF_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" rgroup.long 0x10580++0x27 line.long 0x0 "CFG0_FAST_MRGN_MODE0,Controls fast memory margin for DFT" hexmask.long.word 0x0 0.--11. 1. "FAST_MRGN_MODE0_HS2PARF_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x4 "CFG0_FAST_MRGN_MODE1,Controls fast memory margin for DFT" hexmask.long.word 0x4 0.--11. 1. "FAST_MRGN_MODE1_HDDP_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x8 "CFG0_FAST_MRGN_MODE2,Controls fast memory margin for DFT" hexmask.long.word 0x8 0.--11. 1. "FAST_MRGN_MODE2_EHDSP_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0xC "CFG0_FAST_MRGN_MODE3,Controls fast memory margin for DFT" hexmask.long.word 0xC 0.--11. 1. "FAST_MRGN_MODE3_HD2PRF_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x10 "CFG0_FAST_MRGN_MODE4,Controls fast memory margin for DFT" hexmask.long.word 0x10 0.--11. 1. "FAST_MRGN_MODE4_UHD2PRF_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x14 "CFG0_FAST_MRGN_MODE5,Controls fast memory margin for DFT" hexmask.long.word 0x14 0.--11. 1. "FAST_MRGN_MODE5_ROM_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x18 "CFG0_FAST_MRGN_MODE6,Controls fast memory margin for DFT" hexmask.long.word 0x18 0.--11. 1. "FAST_MRGN_MODE6_HDSP_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x1C "CFG0_FAST_MRGN_MODE7,Controls fast memory margin for DFT" hexmask.long.word 0x1C 0.--11. 1. "FAST_MRGN_MODE7_HSSP_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x20 "CFG0_FAST_MRGN_MODE8,Controls fast memory margin for DFT" hexmask.long.word 0x20 0.--11. 1. "FAST_MRGN_MODE8_HD1PRF_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x24 "CFG0_FAST_MRGN_MODE9,Controls fast memory margin for DFT" hexmask.long.word 0x24 0.--11. 1. "FAST_MRGN_MODE9_HS1PRF_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" rgroup.long 0x11100++0x2F line.long 0x0 "CFG0_CLAIMREG_P4_R0_READONLY," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P4_R0_READONLY,Claim bits for Partition 4" line.long 0x4 "CFG0_CLAIMREG_P4_R1_READONLY," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P4_R1_READONLY,Claim bits for Partition 4" line.long 0x8 "CFG0_CLAIMREG_P4_R2_READONLY," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P4_R2_READONLY,Claim bits for Partition 4" line.long 0xC "CFG0_CLAIMREG_P4_R3_READONLY," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P4_R3_READONLY,Claim bits for Partition 4" line.long 0x10 "CFG0_CLAIMREG_P4_R4_READONLY," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P4_R4_READONLY,Claim bits for Partition 4" line.long 0x14 "CFG0_CLAIMREG_P4_R5_READONLY," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P4_R5_READONLY,Claim bits for Partition 4" line.long 0x18 "CFG0_CLAIMREG_P4_R6_READONLY," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P4_R6_READONLY,Claim bits for Partition 4" line.long 0x1C "CFG0_CLAIMREG_P4_R7_READONLY," hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P4_R7_READONLY,Claim bits for Partition 4" line.long 0x20 "CFG0_CLAIMREG_P4_R8_READONLY," hexmask.long 0x20 0.--31. 1. "CLAIMREG_P4_R8_READONLY,Claim bits for Partition 4" line.long 0x24 "CFG0_CLAIMREG_P4_R9_READONLY," hexmask.long 0x24 0.--31. 1. "CLAIMREG_P4_R9_READONLY,Claim bits for Partition 4" line.long 0x28 "CFG0_CLAIMREG_P4_R10_READONLY," hexmask.long 0x28 0.--31. 1. "CLAIMREG_P4_R10_READONLY,Claim bits for Partition 4" line.long 0x2C "CFG0_CLAIMREG_P4_R11_READONLY," hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P4_R11_READONLY,Claim bits for Partition 4" rgroup.long 0x12000++0x1F line.long 0x0 "CFG0_DV_REG0_PROXY,Register for general purpose DV use." hexmask.long 0x0 0.--31. 1. "DV_REG0_BIT_PROXY,Defined by DV usage" line.long 0x4 "CFG0_DV_REG1_PROXY,Register for general purpose DV use." hexmask.long 0x4 0.--31. 1. "DV_REG1_BIT_PROXY,Defined by DV usage" line.long 0x8 "CFG0_DV_REG2_PROXY,Register for general purpose DV use." hexmask.long 0x8 0.--31. 1. "DV_REG2_BIT_PROXY,Defined by DV usage" line.long 0xC "CFG0_DV_REG3_PROXY,Register for general purpose DV use." hexmask.long 0xC 0.--31. 1. "DV_REG3_BIT_PROXY,Defined by DV usage" line.long 0x10 "CFG0_DV_REG4_PROXY,Register for general purpose DV use." hexmask.long 0x10 0.--31. 1. "DV_REG4_BIT_PROXY,Defined by DV usage" line.long 0x14 "CFG0_DV_REG5_PROXY,Register for general purpose DV use." hexmask.long 0x14 0.--31. 1. "DV_REG5_BIT_PROXY,Defined by DV usage" line.long 0x18 "CFG0_DV_REG6_PROXY,Register for general purpose DV use." hexmask.long 0x18 0.--31. 1. "DV_REG6_BIT_PROXY,Defined by DV usage" line.long 0x1C "CFG0_DV_REG7_PROXY,Register for general purpose DV use." hexmask.long 0x1C 0.--31. 1. "DV_REG7_BIT_PROXY,Defined by DV usage" rgroup.long 0x12200++0xF line.long 0x0 "CFG0_DV_REG0_SET_PROXY,Set register for DV use" hexmask.long 0x0 0.--31. 1. "DV_REG0_SET_BIT_PROXY,Defined by DV usage" line.long 0x4 "CFG0_DV_REG1_SET_PROXY,Set register for DV use" hexmask.long 0x4 0.--31. 1. "DV_REG1_SET_BIT_PROXY,Defined by DV usage" line.long 0x8 "CFG0_DV_REG2_SET_PROXY,Set register for DV use" hexmask.long 0x8 0.--31. 1. "DV_REG2_SET_BIT_PROXY,Defined by DV usage" line.long 0xC "CFG0_DV_REG3_SET_PROXY,Set register for DV use" hexmask.long 0xC 0.--31. 1. "DV_REG3_SET_BIT_PROXY,Defined by DV usage" rgroup.long 0x12300++0xF line.long 0x0 "CFG0_DV_REG0_CLR_PROXY,Clear register for DV use" hexmask.long 0x0 0.--31. 1. "DV_REG0_CLR_BIT_PROXY,Defined by DV usage" line.long 0x4 "CFG0_DV_REG1_CLR_PROXY,Clear register for DV use" hexmask.long 0x4 0.--31. 1. "DV_REG1_CLR_BIT_PROXY,Defined by DV usage" line.long 0x8 "CFG0_DV_REG2_CLR_PROXY,Clear register for DV use" hexmask.long 0x8 0.--31. 1. "DV_REG2_CLR_BIT_PROXY,Defined by DV usage" line.long 0xC "CFG0_DV_REG3_CLR_PROXY,Clear register for DV use" hexmask.long 0xC 0.--31. 1. "DV_REG3_CLR_BIT_PROXY,Defined by DV usage" rgroup.long 0x12500++0x27 line.long 0x0 "CFG0_AVS_CORE_MRGN_MODE0_PROXY,Controls AVS domain memory margin for DFT" hexmask.long.word 0x0 0.--11. 1. "AVS_CORE_MRGN_MODE0_HS2PARF_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x4 "CFG0_AVS_CORE_MRGN_MODE1_PROXY,Controls AVS domain memory margin for DFT" hexmask.long.word 0x4 0.--11. 1. "AVS_CORE_MRGN_MODE1_HDDP_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x8 "CFG0_AVS_CORE_MRGN_MODE2_PROXY,Controls AVS domain memory margin for DFT" hexmask.long.word 0x8 0.--11. 1. "AVS_CORE_MRGN_MODE2_EHDSP_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0xC "CFG0_AVS_CORE_MRGN_MODE3_PROXY,Controls AVS domain memory margin for DFT" hexmask.long.word 0xC 0.--11. 1. "AVS_CORE_MRGN_MODE3_HD2PRF_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x10 "CFG0_AVS_CORE_MRGN_MODE4_PROXY,Controls AVS domain memory margin for DFT" hexmask.long.word 0x10 0.--11. 1. "AVS_CORE_MRGN_MODE4_UHD2PRF_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x14 "CFG0_AVS_CORE_MRGN_MODE5_PROXY,Controls AVS domain memory margin for DFT" hexmask.long.word 0x14 0.--11. 1. "AVS_CORE_MRGN_MODE5_ROM_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x18 "CFG0_AVS_CORE_MRGN_MODE6_PROXY,Controls AVS domain memory margin for DFT" hexmask.long.word 0x18 0.--11. 1. "AVS_CORE_MRGN_MODE6_HDSP_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x1C "CFG0_AVS_CORE_MRGN_MODE7_PROXY,Controls AVS domain memory margin for DFT" hexmask.long.word 0x1C 0.--11. 1. "AVS_CORE_MRGN_MODE7_HSSP_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x20 "CFG0_AVS_CORE_MRGN_MODE8_PROXY,Controls AVS domain memory margin for DFT" hexmask.long.word 0x20 0.--11. 1. "AVS_CORE_MRGN_MODE8_HD1PRF_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x24 "CFG0_AVS_CORE_MRGN_MODE9_PROXY,Controls AVS domain memory margin for DFT" hexmask.long.word 0x24 0.--11. 1. "AVS_CORE_MRGN_MODE9_HS1PRF_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" rgroup.long 0x12540++0x27 line.long 0x0 "CFG0_NON_AVS_MRGN_MODE0_PROXY,Controls non-AVS domain memory margin for DFT" hexmask.long.word 0x0 0.--11. 1. "NON_AVS_MRGN_MODE0_HS2PARF_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x4 "CFG0_NON_AVS_MRGN_MODE1_PROXY,Controls non-AVS domain memory margin for DFT" hexmask.long.word 0x4 0.--11. 1. "NON_AVS_MRGN_MODE1_HDDP_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x8 "CFG0_NON_AVS_MRGN_MODE2_PROXY,Controls non-AVS domain memory margin for DFT" hexmask.long.word 0x8 0.--11. 1. "NON_AVS_MRGN_MODE2_EHDSP_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0xC "CFG0_NON_AVS_MRGN_MODE3_PROXY,Controls non-AVS domain memory margin for DFT" hexmask.long.word 0xC 0.--11. 1. "NON_AVS_MRGN_MODE3_HD2PRF_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x10 "CFG0_NON_AVS_MRGN_MODE4_PROXY,Controls non-AVS domain memory margin for DFT" hexmask.long.word 0x10 0.--11. 1. "NON_AVS_MRGN_MODE4_UHD2PRF_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x14 "CFG0_NON_AVS_MRGN_MODE5_PROXY,Controls non-AVS domain memory margin for DFT" hexmask.long.word 0x14 0.--11. 1. "NON_AVS_MRGN_MODE5_ROM_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x18 "CFG0_NON_AVS_MRGN_MODE6_PROXY,Controls non-AVS domain memory margin for DFT" hexmask.long.word 0x18 0.--11. 1. "NON_AVS_MRGN_MODE6_HDSP_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x1C "CFG0_NON_AVS_MRGN_MODE7_PROXY,Controls non-AVS domain memory margin for DFT" hexmask.long.word 0x1C 0.--11. 1. "NON_AVS_MRGN_MODE7_HSSP_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x20 "CFG0_NON_AVS_MRGN_MODE8_PROXY,Controls non-AVS domain memory margin for DFT" hexmask.long.word 0x20 0.--11. 1. "NON_AVS_MRGN_MODE8_HD1PRF_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x24 "CFG0_NON_AVS_MRGN_MODE9_PROXY,Controls non-AVS domain memory margin for DFT" hexmask.long.word 0x24 0.--11. 1. "NON_AVS_MRGN_MODE9_HS1PRF_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" rgroup.long 0x12580++0x27 line.long 0x0 "CFG0_FAST_MRGN_MODE0_PROXY,Controls fast memory margin for DFT" hexmask.long.word 0x0 0.--11. 1. "FAST_MRGN_MODE0_HS2PARF_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x4 "CFG0_FAST_MRGN_MODE1_PROXY,Controls fast memory margin for DFT" hexmask.long.word 0x4 0.--11. 1. "FAST_MRGN_MODE1_HDDP_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x8 "CFG0_FAST_MRGN_MODE2_PROXY,Controls fast memory margin for DFT" hexmask.long.word 0x8 0.--11. 1. "FAST_MRGN_MODE2_EHDSP_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0xC "CFG0_FAST_MRGN_MODE3_PROXY,Controls fast memory margin for DFT" hexmask.long.word 0xC 0.--11. 1. "FAST_MRGN_MODE3_HD2PRF_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x10 "CFG0_FAST_MRGN_MODE4_PROXY,Controls fast memory margin for DFT" hexmask.long.word 0x10 0.--11. 1. "FAST_MRGN_MODE4_UHD2PRF_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x14 "CFG0_FAST_MRGN_MODE5_PROXY,Controls fast memory margin for DFT" hexmask.long.word 0x14 0.--11. 1. "FAST_MRGN_MODE5_ROM_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x18 "CFG0_FAST_MRGN_MODE6_PROXY,Controls fast memory margin for DFT" hexmask.long.word 0x18 0.--11. 1. "FAST_MRGN_MODE6_HDSP_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x1C "CFG0_FAST_MRGN_MODE7_PROXY,Controls fast memory margin for DFT" hexmask.long.word 0x1C 0.--11. 1. "FAST_MRGN_MODE7_HSSP_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x20 "CFG0_FAST_MRGN_MODE8_PROXY,Controls fast memory margin for DFT" hexmask.long.word 0x20 0.--11. 1. "FAST_MRGN_MODE8_HD1PRF_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x24 "CFG0_FAST_MRGN_MODE9_PROXY,Controls fast memory margin for DFT" hexmask.long.word 0x24 0.--11. 1. "FAST_MRGN_MODE9_HS1PRF_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" rgroup.long 0x13100++0x2F line.long 0x0 "CFG0_CLAIMREG_P4_R0," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P4_R0,Claim bits for Partition 4" line.long 0x4 "CFG0_CLAIMREG_P4_R1," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P4_R1,Claim bits for Partition 4" line.long 0x8 "CFG0_CLAIMREG_P4_R2," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P4_R2,Claim bits for Partition 4" line.long 0xC "CFG0_CLAIMREG_P4_R3," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P4_R3,Claim bits for Partition 4" line.long 0x10 "CFG0_CLAIMREG_P4_R4," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P4_R4,Claim bits for Partition 4" line.long 0x14 "CFG0_CLAIMREG_P4_R5," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P4_R5,Claim bits for Partition 4" line.long 0x18 "CFG0_CLAIMREG_P4_R6," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P4_R6,Claim bits for Partition 4" line.long 0x1C "CFG0_CLAIMREG_P4_R7," hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P4_R7,Claim bits for Partition 4" line.long 0x20 "CFG0_CLAIMREG_P4_R8," hexmask.long 0x20 0.--31. 1. "CLAIMREG_P4_R8,Claim bits for Partition 4" line.long 0x24 "CFG0_CLAIMREG_P4_R9," hexmask.long 0x24 0.--31. 1. "CLAIMREG_P4_R9,Claim bits for Partition 4" line.long 0x28 "CFG0_CLAIMREG_P4_R10," hexmask.long 0x28 0.--31. 1. "CLAIMREG_P4_R10,Claim bits for Partition 4" line.long 0x2C "CFG0_CLAIMREG_P4_R11," hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P4_R11,Claim bits for Partition 4" rgroup.long 0x14000++0x3 line.long 0x0 "CFG0_CHNG_DDR4_FSP_REQ0,This register is used to initiate a LPDDR4 frequency set point change to the DDR 0 Controller" bitfld.long 0x0 8. "CHNG_DDR4_FSP_REQ0_REQ,Initiate FSP frequency change" "0,1" newline bitfld.long 0x0 0.--1. "CHNG_DDR4_FSP_REQ0_REQ_TYPE,Frequency request typeIndicates which DDR4 frequency set point to change to" "0,1,2,3" rgroup.long 0x14004++0x3 line.long 0x0 "CFG0_CHNG_DDR4_FSP_ACK0,This register is used by the DDR 0 Controller to acknowledge the LPDDR4 frequency set point change request" bitfld.long 0x0 7. "CHNG_DDR4_FSP_ACK0_ACK,Frequency change acknowledge.This bit is only valid when CHNG_DDR4_FSP_REQ_req = 1Indication from the DDR Controller that the FSP change operation is complete 0 - FSP change operation in progress 1 - FSP change operation complete" "0: FSP change operation in progress 1,?" newline bitfld.long 0x0 0. "CHNG_DDR4_FSP_ACK0_ERROR,Frequency change errorThis bit is only valid when CHNG_DDR4_FSP_REQ_req = 1 0 - FSP change was successful 1 - FSP change was not successful" "0: FSP change was successful 1,?" rgroup.long 0x14010++0x3 line.long 0x0 "CFG0_CHNG_DDR4_FSP_REQ1,This register is used to initiate a LPDDR4 frequency set point change to the DDR 1 Controller" bitfld.long 0x0 8. "CHNG_DDR4_FSP_REQ1_REQ,Initiate FSP frequency change" "0,1" newline bitfld.long 0x0 0.--1. "CHNG_DDR4_FSP_REQ1_REQ_TYPE,Frequency request typeIndicates which DDR4 frequency set point to change to" "0,1,2,3" rgroup.long 0x14014++0x3 line.long 0x0 "CFG0_CHNG_DDR4_FSP_ACK1,This register is used by the DDR 1 Controller to acknowledge the LPDDR4 frequency set point change request" bitfld.long 0x0 7. "CHNG_DDR4_FSP_ACK1_ACK,Frequency change acknowledge.This bit is only valid when CHNG_DDR4_FSP_REQ_req = 1Indication from the DDR Controller that the FSP change operation is complete 0 - FSP change operation in progress 1 - FSP change operation complete" "0: FSP change operation in progress 1,?" newline bitfld.long 0x0 0. "CHNG_DDR4_FSP_ACK1_ERROR,Frequency change errorThis bit is only valid when CHNG_DDR4_FSP_REQ_req = 1 0 - FSP change was successful 1 - FSP change was not successful" "0: FSP change was successful 1,?" rgroup.long 0x14080++0x3 line.long 0x0 "CFG0_DDR4_FSP_CLKCHNG_REQ0,This register is used by the DDR 0 Controller to request the DDR0 PLL clock frequency change. This can occur as part of DDR4 initialization and training or in response to a LPDDR4 FSP change request." bitfld.long 0x0 7. "DDR4_FSP_CLKCHNG_REQ0_REQ,DDR Controller FSP clock change requestIndicates that the DDR controller needs the DDR clock changed to the frequency indicated by the req_type field. This bit is cleared when the DDR4_FSP_CLKCHNG_ACK_ack bit is set." "0,1" newline bitfld.long 0x0 0.--1. "DDR4_FSP_CLKCHNG_REQ0_REQ_TYPE,Frequency request typeIndicates which DDR4 FSP frequency to which the DDR Controller wants the DDR clock set" "0,1,2,3" rgroup.long 0x14090++0x3 line.long 0x0 "CFG0_DDR4_FSP_CLKCHNG_REQ1,This register is used by the DDR 1 Controller to request the DDR1 PLL clock frequency change. This can occur as part of DDR4 initialization and training or in response to a LPDDR4 FSP change request." bitfld.long 0x0 7. "DDR4_FSP_CLKCHNG_REQ1_REQ,DDR Controller FSP clock change requestIndicates that the DDR controller needs the DDR clock changed to the frequency indicated by the req_type field. This bit is cleared when the DDR4_FSP_CLKCHNG_ACK_ack bit is set." "0,1" newline bitfld.long 0x0 0.--1. "DDR4_FSP_CLKCHNG_REQ1_REQ_TYPE,Frequency request typeIndicates which DDR4 FSP frequency to which the DDR Controller wants the DDR clock set" "0,1,2,3" rgroup.long 0x140C0++0x3 line.long 0x0 "CFG0_DDR4_FSP_CLKCHNG_ACK0,This register is used to acknowledge a DDR0 PLL clock frequency change to the DDR0 Controller." bitfld.long 0x0 0. "DDR4_FSP_CLKCHNG_ACK0_ACK,DDR FSP clock change acknowledgeThis bit should be set once the DDR clock has been successfully changed to the value requested by DDR4_FSP_CLKCHNG_REQ_req_type. Setting this bit will clear the DDR4_FSP_CLKCHNG_REQ_req bit and.." "0,1" rgroup.long 0x140D0++0x3 line.long 0x0 "CFG0_DDR4_FSP_CLKCHNG_ACK1,This register is used to acknowledge a DDR1 PLL clock frequency change to the DDR1 Controller." bitfld.long 0x0 0. "DDR4_FSP_CLKCHNG_ACK1_ACK,DDR FSP clock change acknowledgeThis bit should be set once the DDR clock has been successfully changed to the value requested by DDR4_FSP_CLKCHNG_REQ_req_type. Setting this bit will clear the DDR4_FSP_CLKCHNG_REQ_req bit and.." "0,1" rgroup.long 0x14100++0x7 line.long 0x0 "CFG0_MULTI_DDR_CFG0,Configures DDR interleaving" hexmask.long.byte 0x0 24.--29. 1. "MULTI_DDR_CFG0_DDR_INTRLV_GRAN,Defines the size of each memory stripe for interleaved memory space. Value takes effect when MULTI_DDR_CFG1_ddr_cfg _load field is set as 4'b0110. Field values (Others are reserved): 6'b000000 - 128 B 6'b000001 -.." newline hexmask.long.byte 0x0 16.--21. 1. "MULTI_DDR_CFG0_DDR_INTRLV_SIZE,Defines the memory window size for the interleaved region starting at the bottom of the external memory address range. Value takes effect when MULTI_DDR_CFG1_ddr_cfg _load field is set as 4'b0110. Field values (Others are.." newline hexmask.long.byte 0x0 0.--4. 1. "MULTI_DDR_CFG0_HEARTBEAT_PER,Determines number of cycles of unsuccessful EMIF arbitration to wait before arbitrating for a different EMIF port. Value takes effect when MULTI_DDR_CFG1_ddr_cfg _load field is set as 4'b0110. 0 - Heartbeat is disabled.." line.long 0x4 "CFG0_MULTI_DDR_CFG1,Configures DDR interleaving" hexmask.long.byte 0x4 16.--19. 1. "MULTI_DDR_CFG1_ECC_ENABLE,Determines which EMIFs have ECC enabled. Value takes effect when MULTI_DDR_CFG1_ddr_cfg _load field is set as 4'b0110. Field values (Others are reserved): 4'b0000 - ECC disabled on all EMIFs 4'b0001 - ECC enabled on.." newline hexmask.long.byte 0x4 8.--12. 1. "MULTI_DDR_CFG1_HYBRID_SELECT,Determines interleaved EMIF space location. Usage is based on number of EMIFs present. Value takes effect when MULTI_DDR_CFG1_ddr_cfg _load field is set as 4'b0110. Field values (Others are reserved): 4'b00000 - Entire.." newline hexmask.long.byte 0x4 0.--3. 1. "MULTI_DDR_CFG1_EMIFS_ACTIVE,Indicates which EMIF (DDR) interfaces are active. Value takes effect when MULTI_DDR_CFG1_ddr_cfg _load field is set as 4'b0110. Field values (Others are reserved): 4'b0000 - Reserved 4'b0001 - EMIF 0 Active 4'b0010.." rgroup.long 0x14110++0x3 line.long 0x0 "CFG0_DDR_CFG_LOAD,Implements Multi-DDR configuration load and load status" hexmask.long.byte 0x0 28.--31. 1. "DDR_CFG_LOAD_DDR_CFG_LOAD,When set to 4'b0110 latches the ddr configuration bits into ComputeCluster. Once latched the ComputeCluster ignores further transitions on its latch input so any further changes to this field have no effect." newline rbitfld.long 0x0 0. "DDR_CFG_LOAD_DDR_LOAD_STAT,DDR configuration lock status bit indicating that DDR config load is complete" "0,1" rgroup.long 0x15008++0x7 line.long 0x0 "CFG0_LOCK5_KICK0,This register must be written with the designated key value followed by a write to LOCK5_KICK1 with its key value before write-protected Partition 5 registers can be written." hexmask.long 0x0 0.--31. 1. "LOCK5_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK5_KICK1,This register must be written with the designated key value after a write to LOCK5_KICK0 with its key value before write-protected Partition 5 registers can be written." hexmask.long 0x4 0.--31. 1. "LOCK5_KICK1,- KICK1 component" rgroup.long 0x15100++0xB line.long 0x0 "CFG0_CLAIMREG_P5_R0_READONLY," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P5_R0_READONLY,Claim bits for Partition 5" line.long 0x4 "CFG0_CLAIMREG_P5_R1_READONLY," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P5_R1_READONLY,Claim bits for Partition 5" line.long 0x8 "CFG0_CLAIMREG_P5_R2_READONLY," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P5_R2_READONLY,Claim bits for Partition 5" rgroup.long 0x16000++0x3 line.long 0x0 "CFG0_CHNG_DDR4_FSP_REQ0_PROXY,This register is used to initiate a LPDDR4 frequency set point change to the DDR 0 Controller" bitfld.long 0x0 8. "CHNG_DDR4_FSP_REQ0_REQ_PROXY,Initiate FSP frequency change" "0,1" newline bitfld.long 0x0 0.--1. "CHNG_DDR4_FSP_REQ0_REQ_TYPE_PROXY,Frequency request typeIndicates which DDR4 frequency set point to change to" "0,1,2,3" rgroup.long 0x16004++0x3 line.long 0x0 "CFG0_CHNG_DDR4_FSP_ACK0_PROXY,This register is used by the DDR 0 Controller to acknowledge the LPDDR4 frequency set point change request" bitfld.long 0x0 7. "CHNG_DDR4_FSP_ACK0_ACK_PROXY,Frequency change acknowledge.This bit is only valid when CHNG_DDR4_FSP_REQ_req = 1Indication from the DDR Controller that the FSP change operation is complete 0 - FSP change operation in progress 1 - FSP change operation.." "0: FSP change operation in progress 1,?" newline bitfld.long 0x0 0. "CHNG_DDR4_FSP_ACK0_ERROR_PROXY,Frequency change errorThis bit is only valid when CHNG_DDR4_FSP_REQ_req = 1 0 - FSP change was successful 1 - FSP change was not successful" "0: FSP change was successful 1,?" rgroup.long 0x16010++0x3 line.long 0x0 "CFG0_CHNG_DDR4_FSP_REQ1_PROXY,This register is used to initiate a LPDDR4 frequency set point change to the DDR 1 Controller" bitfld.long 0x0 8. "CHNG_DDR4_FSP_REQ1_REQ_PROXY,Initiate FSP frequency change" "0,1" newline bitfld.long 0x0 0.--1. "CHNG_DDR4_FSP_REQ1_REQ_TYPE_PROXY,Frequency request typeIndicates which DDR4 frequency set point to change to" "0,1,2,3" rgroup.long 0x16014++0x3 line.long 0x0 "CFG0_CHNG_DDR4_FSP_ACK1_PROXY,This register is used by the DDR 1 Controller to acknowledge the LPDDR4 frequency set point change request" bitfld.long 0x0 7. "CHNG_DDR4_FSP_ACK1_ACK_PROXY,Frequency change acknowledge.This bit is only valid when CHNG_DDR4_FSP_REQ_req = 1Indication from the DDR Controller that the FSP change operation is complete 0 - FSP change operation in progress 1 - FSP change operation.." "0: FSP change operation in progress 1,?" newline bitfld.long 0x0 0. "CHNG_DDR4_FSP_ACK1_ERROR_PROXY,Frequency change errorThis bit is only valid when CHNG_DDR4_FSP_REQ_req = 1 0 - FSP change was successful 1 - FSP change was not successful" "0: FSP change was successful 1,?" rgroup.long 0x16080++0x3 line.long 0x0 "CFG0_DDR4_FSP_CLKCHNG_REQ0_PROXY,This register is used by the DDR 0 Controller to request the DDR0 PLL clock frequency change. This can occur as part of DDR4 initialization and training or in response to a LPDDR4 FSP change request." bitfld.long 0x0 7. "DDR4_FSP_CLKCHNG_REQ0_REQ_PROXY,DDR Controller FSP clock change requestIndicates that the DDR controller needs the DDR clock changed to the frequency indicated by the req_type field. This bit is cleared when the DDR4_FSP_CLKCHNG_ACK_ack bit is set." "0,1" newline bitfld.long 0x0 0.--1. "DDR4_FSP_CLKCHNG_REQ0_REQ_TYPE_PROXY,Frequency request typeIndicates which DDR4 FSP frequency to which the DDR Controller wants the DDR clock set" "0,1,2,3" rgroup.long 0x16090++0x3 line.long 0x0 "CFG0_DDR4_FSP_CLKCHNG_REQ1_PROXY,This register is used by the DDR 1 Controller to request the DDR1 PLL clock frequency change. This can occur as part of DDR4 initialization and training or in response to a LPDDR4 FSP change request." bitfld.long 0x0 7. "DDR4_FSP_CLKCHNG_REQ1_REQ_PROXY,DDR Controller FSP clock change requestIndicates that the DDR controller needs the DDR clock changed to the frequency indicated by the req_type field. This bit is cleared when the DDR4_FSP_CLKCHNG_ACK_ack bit is set." "0,1" newline bitfld.long 0x0 0.--1. "DDR4_FSP_CLKCHNG_REQ1_REQ_TYPE_PROXY,Frequency request typeIndicates which DDR4 FSP frequency to which the DDR Controller wants the DDR clock set" "0,1,2,3" rgroup.long 0x160C0++0x3 line.long 0x0 "CFG0_DDR4_FSP_CLKCHNG_ACK0_PROXY,This register is used to acknowledge a DDR0 PLL clock frequency change to the DDR0 Controller." bitfld.long 0x0 0. "DDR4_FSP_CLKCHNG_ACK0_ACK_PROXY,DDR FSP clock change acknowledgeThis bit should be set once the DDR clock has been successfully changed to the value requested by DDR4_FSP_CLKCHNG_REQ_req_type. Setting this bit will clear the DDR4_FSP_CLKCHNG_REQ_req bit.." "0,1" rgroup.long 0x160D0++0x3 line.long 0x0 "CFG0_DDR4_FSP_CLKCHNG_ACK1_PROXY,This register is used to acknowledge a DDR1 PLL clock frequency change to the DDR1 Controller." bitfld.long 0x0 0. "DDR4_FSP_CLKCHNG_ACK1_ACK_PROXY,DDR FSP clock change acknowledgeThis bit should be set once the DDR clock has been successfully changed to the value requested by DDR4_FSP_CLKCHNG_REQ_req_type. Setting this bit will clear the DDR4_FSP_CLKCHNG_REQ_req bit.." "0,1" rgroup.long 0x16100++0x7 line.long 0x0 "CFG0_MULTI_DDR_CFG0_PROXY,Configures DDR interleaving" hexmask.long.byte 0x0 24.--29. 1. "MULTI_DDR_CFG0_DDR_INTRLV_GRAN_PROXY,Defines the size of each memory stripe for interleaved memory space. Value takes effect when MULTI_DDR_CFG1_ddr_cfg _load field is set as 4'b0110. Field values (Others are reserved): 6'b000000 - 128 B.." newline hexmask.long.byte 0x0 16.--21. 1. "MULTI_DDR_CFG0_DDR_INTRLV_SIZE_PROXY,Defines the memory window size for the interleaved region starting at the bottom of the external memory address range. Value takes effect when MULTI_DDR_CFG1_ddr_cfg _load field is set as 4'b0110. Field values.." newline hexmask.long.byte 0x0 0.--4. 1. "MULTI_DDR_CFG0_HEARTBEAT_PER_PROXY,Determines number of cycles of unsuccessful EMIF arbitration to wait before arbitrating for a different EMIF port. Value takes effect when MULTI_DDR_CFG1_ddr_cfg _load field is set as 4'b0110. 0 - Heartbeat is.." line.long 0x4 "CFG0_MULTI_DDR_CFG1_PROXY,Configures DDR interleaving" hexmask.long.byte 0x4 16.--19. 1. "MULTI_DDR_CFG1_ECC_ENABLE_PROXY,Determines which EMIFs have ECC enabled. Value takes effect when MULTI_DDR_CFG1_ddr_cfg _load field is set as 4'b0110. Field values (Others are reserved): 4'b0000 - ECC disabled on all EMIFs 4'b0001 - ECC enabled.." newline hexmask.long.byte 0x4 8.--12. 1. "MULTI_DDR_CFG1_HYBRID_SELECT_PROXY,Determines interleaved EMIF space location. Usage is based on number of EMIFs present. Value takes effect when MULTI_DDR_CFG1_ddr_cfg _load field is set as 4'b0110. Field values (Others are reserved): 4'b00000 -.." newline hexmask.long.byte 0x4 0.--3. 1. "MULTI_DDR_CFG1_EMIFS_ACTIVE_PROXY,Indicates which EMIF (DDR) interfaces are active. Value takes effect when MULTI_DDR_CFG1_ddr_cfg _load field is set as 4'b0110. Field values (Others are reserved): 4'b0000 - Reserved 4'b0001 - EMIF 0 Active.." rgroup.long 0x16110++0x3 line.long 0x0 "CFG0_DDR_CFG_LOAD_PROXY,Implements Multi-DDR configuration load and load status" hexmask.long.byte 0x0 28.--31. 1. "DDR_CFG_LOAD_DDR_CFG_LOAD_PROXY,When set to 4'b0110 latches the ddr configuration bits into ComputeCluster. Once latched the ComputeCluster ignores further transitions on its latch input so any further changes to this field have no effect." newline rbitfld.long 0x0 0. "DDR_CFG_LOAD_DDR_LOAD_STAT_PROXY,DDR configuration lock status bit indicating that DDR config load is complete" "0,1" rgroup.long 0x17008++0x7 line.long 0x0 "CFG0_LOCK5_KICK0_PROXY,This register must be written with the designated key value followed by a write to LOCK5_KICK1 with its key value before write-protected Partition 5 registers can be written." hexmask.long 0x0 0.--31. 1. "LOCK5_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK5_KICK1_PROXY,This register must be written with the designated key value after a write to LOCK5_KICK0 with its key value before write-protected Partition 5 registers can be written." hexmask.long 0x4 0.--31. 1. "LOCK5_KICK1_PROXY,- KICK1 component" rgroup.long 0x17100++0xB line.long 0x0 "CFG0_CLAIMREG_P5_R0," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P5_R0,Claim bits for Partition 5" line.long 0x4 "CFG0_CLAIMREG_P5_R1," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P5_R1,Claim bits for Partition 5" line.long 0x8 "CFG0_CLAIMREG_P5_R2," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P5_R2,Claim bits for Partition 5" rgroup.long 0x18080++0x3 line.long 0x0 "CFG0_ACSPCIE0_TRIM,Trims the ACSPCIE0 module Bandgap Regulator" hexmask.long.byte 0x0 16.--19. 1. "ACSPCIE0_TRIM_DTRBGAPI_LOWV,Bandgap output current trim bits" newline hexmask.long.byte 0x0 8.--15. 1. "ACSPCIE0_TRIM_DTRBGAPV_LOWV,Bandgap output voltage magnitude trim bits" newline hexmask.long.byte 0x0 0.--7. 1. "ACSPCIE0_TRIM_DTRBGAPC_LOWV,Bandgap slope trim bits. Bit7 is used to calculate the offset" rgroup.long 0x18090++0x3 line.long 0x0 "CFG0_ACSPCIE0_CTRL,Controls the ACSPCIE0 module" rbitfld.long 0x0 24. "ACSPCIE0_CTRL_BANDGAP_OK,Bandgap output okay" "0,1" newline bitfld.long 0x0 8. "ACSPCIE0_CTRL_AIPOFF,Testmode enable" "0,1" newline bitfld.long 0x0 1. "ACSPCIE0_CTRL_PWRDN1,Disable (tristate) PAD1 IO buffers" "0,1" newline bitfld.long 0x0 0. "ACSPCIE0_CTRL_PWRDN0,Disable (tristate) PAD0 IO buffers" "0,1" rgroup.long 0x19100++0x7 line.long 0x0 "CFG0_CLAIMREG_P6_R0_READONLY," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P6_R0_READONLY,Claim bits for Partition 6" line.long 0x4 "CFG0_CLAIMREG_P6_R1_READONLY," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P6_R1_READONLY,Claim bits for Partition 6" rgroup.long 0x1A080++0x3 line.long 0x0 "CFG0_ACSPCIE0_TRIM_PROXY,Trims the ACSPCIE0 module Bandgap Regulator" hexmask.long.byte 0x0 16.--19. 1. "ACSPCIE0_TRIM_DTRBGAPI_LOWV_PROXY,Bandgap output current trim bits" newline hexmask.long.byte 0x0 8.--15. 1. "ACSPCIE0_TRIM_DTRBGAPV_LOWV_PROXY,Bandgap output voltage magnitude trim bits" newline hexmask.long.byte 0x0 0.--7. 1. "ACSPCIE0_TRIM_DTRBGAPC_LOWV_PROXY,Bandgap slope trim bits. Bit7 is used to calculate the offset" rgroup.long 0x1A090++0x3 line.long 0x0 "CFG0_ACSPCIE0_CTRL_PROXY,Controls the ACSPCIE0 module" rbitfld.long 0x0 24. "ACSPCIE0_CTRL_BANDGAP_OK_PROXY,Bandgap output okay" "0,1" newline bitfld.long 0x0 8. "ACSPCIE0_CTRL_AIPOFF_PROXY,Testmode enable" "0,1" newline bitfld.long 0x0 1. "ACSPCIE0_CTRL_PWRDN1_PROXY,Disable (tristate) PAD1 IO buffers" "0,1" newline bitfld.long 0x0 0. "ACSPCIE0_CTRL_PWRDN0_PROXY,Disable (tristate) PAD0 IO buffers" "0,1" rgroup.long 0x1B100++0x7 line.long 0x0 "CFG0_CLAIMREG_P6_R0," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P6_R0,Claim bits for Partition 6" line.long 0x4 "CFG0_CLAIMREG_P6_R1," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P6_R1,Claim bits for Partition 6" rgroup.long 0x1C000++0x11F line.long 0x0 "CFG0_PADCONFIG0,Register to control pin configuration and muxing" bitfld.long 0x0 31. "PADCONFIG0_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x0 30. "PADCONFIG0_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x0 29. "PADCONFIG0_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x0 26. "PADCONFIG0_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x0 25. "PADCONFIG0_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x0 24. "PADCONFIG0_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x0 23. "PADCONFIG0_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x0 22. "PADCONFIG0_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x0 21. "PADCONFIG0_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x0 18. "PADCONFIG0_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x0 15. "PADCONFIG0_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x0 14. "PADCONFIG0_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x0 11.--13. "PADCONFIG0_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "PADCONFIG0_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x0 7. "PADCONFIG0_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g." "0: Disabled,1: Enabled" newline bitfld.long 0x0 4.--5. "PADCONFIG0_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x0 0.--3. 1. "PADCONFIG0_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 -.." line.long 0x4 "CFG0_PADCONFIG1,Register to control pin configuration and muxing" bitfld.long 0x4 31. "PADCONFIG1_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x4 30. "PADCONFIG1_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x4 29. "PADCONFIG1_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x4 28. "PADCONFIG1_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x4 27. "PADCONFIG1_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x4 26. "PADCONFIG1_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x4 25. "PADCONFIG1_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x4 24. "PADCONFIG1_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x4 23. "PADCONFIG1_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x4 22. "PADCONFIG1_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x4 21. "PADCONFIG1_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x4 19.--20. "PADCONFIG1_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4 18. "PADCONFIG1_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x4 17. "PADCONFIG1_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x4 16. "PADCONFIG1_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x4 15. "PADCONFIG1_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x4 14. "PADCONFIG1_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x4 11.--13. "PADCONFIG1_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8. "PADCONFIG1_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x4 7. "PADCONFIG1_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g." "0: Disabled,1: Enabled" newline bitfld.long 0x4 4.--5. "PADCONFIG1_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x4 0.--3. 1. "PADCONFIG1_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 -.." line.long 0x8 "CFG0_PADCONFIG2,Register to control pin configuration and muxing" bitfld.long 0x8 31. "PADCONFIG2_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x8 30. "PADCONFIG2_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x8 29. "PADCONFIG2_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x8 28. "PADCONFIG2_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x8 27. "PADCONFIG2_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x8 26. "PADCONFIG2_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x8 25. "PADCONFIG2_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x8 24. "PADCONFIG2_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x8 23. "PADCONFIG2_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x8 22. "PADCONFIG2_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x8 21. "PADCONFIG2_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x8 19.--20. "PADCONFIG2_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8 18. "PADCONFIG2_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x8 17. "PADCONFIG2_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x8 16. "PADCONFIG2_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x8 15. "PADCONFIG2_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x8 14. "PADCONFIG2_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x8 11.--13. "PADCONFIG2_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "PADCONFIG2_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x8 7. "PADCONFIG2_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g." "0: Disabled,1: Enabled" newline bitfld.long 0x8 4.--5. "PADCONFIG2_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x8 0.--3. 1. "PADCONFIG2_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 -.." line.long 0xC "CFG0_PADCONFIG3,Register to control pin configuration and muxing" bitfld.long 0xC 31. "PADCONFIG3_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xC 30. "PADCONFIG3_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xC 29. "PADCONFIG3_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xC 28. "PADCONFIG3_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xC 27. "PADCONFIG3_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xC 26. "PADCONFIG3_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xC 25. "PADCONFIG3_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xC 24. "PADCONFIG3_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xC 23. "PADCONFIG3_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xC 22. "PADCONFIG3_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xC 21. "PADCONFIG3_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xC 19.--20. "PADCONFIG3_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC 18. "PADCONFIG3_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xC 17. "PADCONFIG3_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xC 16. "PADCONFIG3_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xC 15. "PADCONFIG3_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xC 14. "PADCONFIG3_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xC 11.--13. "PADCONFIG3_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "PADCONFIG3_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xC 7. "PADCONFIG3_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g." "0: Disabled,1: Enabled" newline bitfld.long 0xC 4.--5. "PADCONFIG3_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xC 0.--3. 1. "PADCONFIG3_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 -.." line.long 0x10 "CFG0_PADCONFIG4,Register to control pin configuration and muxing" bitfld.long 0x10 31. "PADCONFIG4_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x10 30. "PADCONFIG4_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x10 29. "PADCONFIG4_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x10 28. "PADCONFIG4_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x10 27. "PADCONFIG4_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x10 26. "PADCONFIG4_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x10 25. "PADCONFIG4_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x10 24. "PADCONFIG4_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x10 23. "PADCONFIG4_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x10 22. "PADCONFIG4_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x10 21. "PADCONFIG4_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x10 19.--20. "PADCONFIG4_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x10 18. "PADCONFIG4_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x10 17. "PADCONFIG4_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x10 16. "PADCONFIG4_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x10 15. "PADCONFIG4_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x10 14. "PADCONFIG4_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x10 11.--13. "PADCONFIG4_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "PADCONFIG4_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x10 7. "PADCONFIG4_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g." "0: Disabled,1: Enabled" newline bitfld.long 0x10 4.--5. "PADCONFIG4_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x10 0.--3. 1. "PADCONFIG4_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 -.." line.long 0x14 "CFG0_PADCONFIG5,Register to control pin configuration and muxing" bitfld.long 0x14 31. "PADCONFIG5_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x14 30. "PADCONFIG5_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x14 29. "PADCONFIG5_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x14 28. "PADCONFIG5_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x14 27. "PADCONFIG5_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x14 26. "PADCONFIG5_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x14 25. "PADCONFIG5_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x14 24. "PADCONFIG5_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x14 23. "PADCONFIG5_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x14 22. "PADCONFIG5_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x14 21. "PADCONFIG5_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x14 19.--20. "PADCONFIG5_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x14 18. "PADCONFIG5_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x14 17. "PADCONFIG5_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x14 16. "PADCONFIG5_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x14 15. "PADCONFIG5_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x14 14. "PADCONFIG5_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x14 11.--13. "PADCONFIG5_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "PADCONFIG5_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x14 7. "PADCONFIG5_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g." "0: Disabled,1: Enabled" newline bitfld.long 0x14 4.--5. "PADCONFIG5_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x14 0.--3. 1. "PADCONFIG5_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 -.." line.long 0x18 "CFG0_PADCONFIG6,Register to control pin configuration and muxing" bitfld.long 0x18 31. "PADCONFIG6_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x18 30. "PADCONFIG6_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x18 29. "PADCONFIG6_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x18 28. "PADCONFIG6_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x18 27. "PADCONFIG6_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x18 26. "PADCONFIG6_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x18 25. "PADCONFIG6_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x18 24. "PADCONFIG6_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x18 23. "PADCONFIG6_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x18 22. "PADCONFIG6_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x18 21. "PADCONFIG6_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x18 19.--20. "PADCONFIG6_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x18 18. "PADCONFIG6_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x18 17. "PADCONFIG6_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x18 16. "PADCONFIG6_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x18 15. "PADCONFIG6_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x18 14. "PADCONFIG6_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x18 11.--13. "PADCONFIG6_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8. "PADCONFIG6_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x18 7. "PADCONFIG6_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g." "0: Disabled,1: Enabled" newline bitfld.long 0x18 4.--5. "PADCONFIG6_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x18 0.--3. 1. "PADCONFIG6_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 -.." line.long 0x1C "CFG0_PADCONFIG7,Register to control pin configuration and muxing" bitfld.long 0x1C 31. "PADCONFIG7_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x1C 30. "PADCONFIG7_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x1C 29. "PADCONFIG7_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x1C 28. "PADCONFIG7_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x1C 27. "PADCONFIG7_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x1C 26. "PADCONFIG7_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x1C 25. "PADCONFIG7_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x1C 24. "PADCONFIG7_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x1C 23. "PADCONFIG7_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x1C 22. "PADCONFIG7_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x1C 21. "PADCONFIG7_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x1C 19.--20. "PADCONFIG7_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1C 18. "PADCONFIG7_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x1C 17. "PADCONFIG7_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x1C 16. "PADCONFIG7_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x1C 15. "PADCONFIG7_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x1C 14. "PADCONFIG7_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x1C 11.--13. "PADCONFIG7_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "PADCONFIG7_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x1C 7. "PADCONFIG7_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g." "0: Disabled,1: Enabled" newline bitfld.long 0x1C 4.--5. "PADCONFIG7_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x1C 0.--3. 1. "PADCONFIG7_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 -.." line.long 0x20 "CFG0_PADCONFIG8,Register to control pin configuration and muxing" bitfld.long 0x20 31. "PADCONFIG8_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x20 30. "PADCONFIG8_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x20 29. "PADCONFIG8_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x20 28. "PADCONFIG8_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x20 27. "PADCONFIG8_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x20 26. "PADCONFIG8_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x20 25. "PADCONFIG8_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x20 24. "PADCONFIG8_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x20 23. "PADCONFIG8_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x20 22. "PADCONFIG8_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x20 21. "PADCONFIG8_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x20 19.--20. "PADCONFIG8_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x20 18. "PADCONFIG8_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x20 17. "PADCONFIG8_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x20 16. "PADCONFIG8_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x20 15. "PADCONFIG8_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x20 14. "PADCONFIG8_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x20 11.--13. "PADCONFIG8_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 8. "PADCONFIG8_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x20 7. "PADCONFIG8_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g." "0: Disabled,1: Enabled" newline bitfld.long 0x20 4.--5. "PADCONFIG8_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x20 0.--3. 1. "PADCONFIG8_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 -.." line.long 0x24 "CFG0_PADCONFIG9,Register to control pin configuration and muxing" bitfld.long 0x24 31. "PADCONFIG9_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x24 30. "PADCONFIG9_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x24 29. "PADCONFIG9_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x24 28. "PADCONFIG9_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x24 27. "PADCONFIG9_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x24 26. "PADCONFIG9_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x24 25. "PADCONFIG9_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x24 24. "PADCONFIG9_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x24 23. "PADCONFIG9_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x24 22. "PADCONFIG9_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x24 21. "PADCONFIG9_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x24 19.--20. "PADCONFIG9_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x24 18. "PADCONFIG9_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x24 17. "PADCONFIG9_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x24 16. "PADCONFIG9_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x24 15. "PADCONFIG9_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x24 14. "PADCONFIG9_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x24 11.--13. "PADCONFIG9_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 8. "PADCONFIG9_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x24 7. "PADCONFIG9_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g." "0: Disabled,1: Enabled" newline bitfld.long 0x24 4.--5. "PADCONFIG9_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x24 0.--3. 1. "PADCONFIG9_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 -.." line.long 0x28 "CFG0_PADCONFIG10,Register to control pin configuration and muxing" bitfld.long 0x28 31. "PADCONFIG10_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x28 30. "PADCONFIG10_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x28 29. "PADCONFIG10_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x28 28. "PADCONFIG10_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x28 27. "PADCONFIG10_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x28 26. "PADCONFIG10_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x28 25. "PADCONFIG10_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x28 24. "PADCONFIG10_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x28 23. "PADCONFIG10_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x28 22. "PADCONFIG10_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x28 21. "PADCONFIG10_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x28 19.--20. "PADCONFIG10_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x28 18. "PADCONFIG10_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x28 17. "PADCONFIG10_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x28 16. "PADCONFIG10_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x28 15. "PADCONFIG10_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x28 14. "PADCONFIG10_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x28 11.--13. "PADCONFIG10_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8. "PADCONFIG10_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x28 7. "PADCONFIG10_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x28 4.--5. "PADCONFIG10_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x28 0.--3. 1. "PADCONFIG10_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x2C "CFG0_PADCONFIG11,Register to control pin configuration and muxing" bitfld.long 0x2C 31. "PADCONFIG11_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x2C 30. "PADCONFIG11_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x2C 29. "PADCONFIG11_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x2C 28. "PADCONFIG11_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x2C 27. "PADCONFIG11_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x2C 26. "PADCONFIG11_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x2C 25. "PADCONFIG11_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x2C 24. "PADCONFIG11_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x2C 23. "PADCONFIG11_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x2C 22. "PADCONFIG11_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x2C 21. "PADCONFIG11_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x2C 19.--20. "PADCONFIG11_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x2C 18. "PADCONFIG11_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x2C 17. "PADCONFIG11_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x2C 16. "PADCONFIG11_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x2C 15. "PADCONFIG11_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x2C 14. "PADCONFIG11_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x2C 11.--13. "PADCONFIG11_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 8. "PADCONFIG11_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x2C 7. "PADCONFIG11_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x2C 4.--5. "PADCONFIG11_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x2C 0.--3. 1. "PADCONFIG11_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x30 "CFG0_PADCONFIG12,Register to control pin configuration and muxing" bitfld.long 0x30 31. "PADCONFIG12_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x30 30. "PADCONFIG12_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x30 29. "PADCONFIG12_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x30 28. "PADCONFIG12_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x30 27. "PADCONFIG12_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x30 26. "PADCONFIG12_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x30 25. "PADCONFIG12_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x30 24. "PADCONFIG12_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x30 23. "PADCONFIG12_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x30 22. "PADCONFIG12_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x30 21. "PADCONFIG12_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x30 19.--20. "PADCONFIG12_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x30 18. "PADCONFIG12_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x30 17. "PADCONFIG12_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x30 16. "PADCONFIG12_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x30 15. "PADCONFIG12_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x30 14. "PADCONFIG12_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x30 11.--13. "PADCONFIG12_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 8. "PADCONFIG12_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x30 7. "PADCONFIG12_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x30 4.--5. "PADCONFIG12_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x30 0.--3. 1. "PADCONFIG12_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x34 "CFG0_PADCONFIG13,Register to control pin configuration and muxing" bitfld.long 0x34 31. "PADCONFIG13_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x34 30. "PADCONFIG13_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x34 29. "PADCONFIG13_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x34 28. "PADCONFIG13_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x34 27. "PADCONFIG13_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x34 26. "PADCONFIG13_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x34 25. "PADCONFIG13_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x34 24. "PADCONFIG13_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x34 23. "PADCONFIG13_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x34 22. "PADCONFIG13_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x34 21. "PADCONFIG13_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x34 19.--20. "PADCONFIG13_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x34 18. "PADCONFIG13_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x34 17. "PADCONFIG13_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x34 16. "PADCONFIG13_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x34 15. "PADCONFIG13_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x34 14. "PADCONFIG13_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x34 11.--13. "PADCONFIG13_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 8. "PADCONFIG13_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x34 7. "PADCONFIG13_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x34 4.--5. "PADCONFIG13_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x34 0.--3. 1. "PADCONFIG13_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x38 "CFG0_PADCONFIG14,Register to control pin configuration and muxing" bitfld.long 0x38 31. "PADCONFIG14_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x38 30. "PADCONFIG14_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x38 29. "PADCONFIG14_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x38 28. "PADCONFIG14_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x38 27. "PADCONFIG14_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x38 26. "PADCONFIG14_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x38 25. "PADCONFIG14_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x38 24. "PADCONFIG14_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x38 23. "PADCONFIG14_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x38 22. "PADCONFIG14_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x38 21. "PADCONFIG14_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x38 19.--20. "PADCONFIG14_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x38 18. "PADCONFIG14_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x38 17. "PADCONFIG14_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x38 16. "PADCONFIG14_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x38 15. "PADCONFIG14_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x38 14. "PADCONFIG14_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x38 11.--13. "PADCONFIG14_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 8. "PADCONFIG14_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x38 7. "PADCONFIG14_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x38 4.--5. "PADCONFIG14_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x38 0.--3. 1. "PADCONFIG14_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x3C "CFG0_PADCONFIG15,Register to control pin configuration and muxing" bitfld.long 0x3C 31. "PADCONFIG15_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x3C 30. "PADCONFIG15_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x3C 29. "PADCONFIG15_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x3C 28. "PADCONFIG15_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x3C 27. "PADCONFIG15_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x3C 26. "PADCONFIG15_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x3C 25. "PADCONFIG15_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x3C 24. "PADCONFIG15_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x3C 23. "PADCONFIG15_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x3C 22. "PADCONFIG15_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x3C 21. "PADCONFIG15_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x3C 19.--20. "PADCONFIG15_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x3C 18. "PADCONFIG15_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x3C 17. "PADCONFIG15_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x3C 16. "PADCONFIG15_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x3C 15. "PADCONFIG15_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x3C 14. "PADCONFIG15_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x3C 11.--13. "PADCONFIG15_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x3C 8. "PADCONFIG15_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x3C 7. "PADCONFIG15_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x3C 4.--5. "PADCONFIG15_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x3C 0.--3. 1. "PADCONFIG15_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x40 "CFG0_PADCONFIG16,Register to control pin configuration and muxing" bitfld.long 0x40 31. "PADCONFIG16_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x40 30. "PADCONFIG16_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x40 29. "PADCONFIG16_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x40 28. "PADCONFIG16_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x40 27. "PADCONFIG16_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x40 26. "PADCONFIG16_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x40 25. "PADCONFIG16_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x40 24. "PADCONFIG16_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x40 23. "PADCONFIG16_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x40 22. "PADCONFIG16_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x40 21. "PADCONFIG16_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x40 19.--20. "PADCONFIG16_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x40 18. "PADCONFIG16_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x40 17. "PADCONFIG16_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x40 16. "PADCONFIG16_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x40 15. "PADCONFIG16_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x40 14. "PADCONFIG16_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x40 11.--13. "PADCONFIG16_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 8. "PADCONFIG16_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x40 7. "PADCONFIG16_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x40 4.--5. "PADCONFIG16_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x40 0.--3. 1. "PADCONFIG16_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x44 "CFG0_PADCONFIG17,Register to control pin configuration and muxing" bitfld.long 0x44 31. "PADCONFIG17_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x44 30. "PADCONFIG17_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x44 29. "PADCONFIG17_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x44 28. "PADCONFIG17_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x44 27. "PADCONFIG17_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x44 26. "PADCONFIG17_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x44 25. "PADCONFIG17_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x44 24. "PADCONFIG17_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x44 23. "PADCONFIG17_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x44 22. "PADCONFIG17_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x44 21. "PADCONFIG17_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x44 19.--20. "PADCONFIG17_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x44 18. "PADCONFIG17_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x44 17. "PADCONFIG17_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x44 16. "PADCONFIG17_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x44 15. "PADCONFIG17_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x44 14. "PADCONFIG17_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x44 11.--13. "PADCONFIG17_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x44 8. "PADCONFIG17_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x44 7. "PADCONFIG17_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x44 4.--5. "PADCONFIG17_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x44 0.--3. 1. "PADCONFIG17_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x48 "CFG0_PADCONFIG18,Register to control pin configuration and muxing" bitfld.long 0x48 31. "PADCONFIG18_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x48 30. "PADCONFIG18_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x48 29. "PADCONFIG18_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x48 28. "PADCONFIG18_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x48 27. "PADCONFIG18_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x48 26. "PADCONFIG18_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x48 25. "PADCONFIG18_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x48 24. "PADCONFIG18_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x48 23. "PADCONFIG18_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x48 22. "PADCONFIG18_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x48 21. "PADCONFIG18_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x48 19.--20. "PADCONFIG18_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x48 18. "PADCONFIG18_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x48 17. "PADCONFIG18_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x48 16. "PADCONFIG18_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x48 15. "PADCONFIG18_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x48 14. "PADCONFIG18_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x48 11.--13. "PADCONFIG18_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 8. "PADCONFIG18_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x48 7. "PADCONFIG18_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x48 4.--5. "PADCONFIG18_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x48 0.--3. 1. "PADCONFIG18_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x4C "CFG0_PADCONFIG19,Register to control pin configuration and muxing" bitfld.long 0x4C 31. "PADCONFIG19_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x4C 30. "PADCONFIG19_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x4C 29. "PADCONFIG19_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x4C 28. "PADCONFIG19_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x4C 27. "PADCONFIG19_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x4C 26. "PADCONFIG19_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x4C 25. "PADCONFIG19_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x4C 24. "PADCONFIG19_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x4C 23. "PADCONFIG19_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x4C 22. "PADCONFIG19_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x4C 21. "PADCONFIG19_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x4C 19.--20. "PADCONFIG19_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4C 18. "PADCONFIG19_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x4C 17. "PADCONFIG19_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x4C 16. "PADCONFIG19_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x4C 15. "PADCONFIG19_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x4C 14. "PADCONFIG19_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x4C 11.--13. "PADCONFIG19_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4C 8. "PADCONFIG19_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x4C 7. "PADCONFIG19_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x4C 4.--5. "PADCONFIG19_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x4C 0.--3. 1. "PADCONFIG19_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x50 "CFG0_PADCONFIG20,Register to control pin configuration and muxing" bitfld.long 0x50 31. "PADCONFIG20_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x50 30. "PADCONFIG20_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x50 29. "PADCONFIG20_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x50 28. "PADCONFIG20_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x50 27. "PADCONFIG20_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x50 26. "PADCONFIG20_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x50 25. "PADCONFIG20_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x50 24. "PADCONFIG20_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x50 23. "PADCONFIG20_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x50 22. "PADCONFIG20_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x50 21. "PADCONFIG20_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x50 19.--20. "PADCONFIG20_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x50 18. "PADCONFIG20_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x50 17. "PADCONFIG20_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x50 16. "PADCONFIG20_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x50 15. "PADCONFIG20_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x50 14. "PADCONFIG20_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x50 11.--13. "PADCONFIG20_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 8. "PADCONFIG20_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x50 7. "PADCONFIG20_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x50 4.--5. "PADCONFIG20_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x50 0.--3. 1. "PADCONFIG20_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x54 "CFG0_PADCONFIG21,Register to control pin configuration and muxing" bitfld.long 0x54 31. "PADCONFIG21_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x54 30. "PADCONFIG21_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x54 29. "PADCONFIG21_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x54 28. "PADCONFIG21_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x54 27. "PADCONFIG21_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x54 26. "PADCONFIG21_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x54 25. "PADCONFIG21_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x54 24. "PADCONFIG21_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x54 23. "PADCONFIG21_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x54 22. "PADCONFIG21_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x54 21. "PADCONFIG21_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x54 19.--20. "PADCONFIG21_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x54 18. "PADCONFIG21_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x54 17. "PADCONFIG21_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x54 16. "PADCONFIG21_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x54 15. "PADCONFIG21_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x54 14. "PADCONFIG21_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x54 11.--13. "PADCONFIG21_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x54 8. "PADCONFIG21_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x54 7. "PADCONFIG21_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x54 4.--5. "PADCONFIG21_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x54 0.--3. 1. "PADCONFIG21_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x58 "CFG0_PADCONFIG22,Register to control pin configuration and muxing" bitfld.long 0x58 31. "PADCONFIG22_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x58 30. "PADCONFIG22_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x58 29. "PADCONFIG22_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x58 28. "PADCONFIG22_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x58 27. "PADCONFIG22_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x58 26. "PADCONFIG22_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x58 25. "PADCONFIG22_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x58 24. "PADCONFIG22_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x58 23. "PADCONFIG22_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x58 22. "PADCONFIG22_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x58 21. "PADCONFIG22_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x58 19.--20. "PADCONFIG22_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x58 18. "PADCONFIG22_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x58 17. "PADCONFIG22_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x58 16. "PADCONFIG22_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x58 15. "PADCONFIG22_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x58 14. "PADCONFIG22_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x58 11.--13. "PADCONFIG22_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 8. "PADCONFIG22_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x58 7. "PADCONFIG22_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x58 4.--5. "PADCONFIG22_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x58 0.--3. 1. "PADCONFIG22_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x5C "CFG0_PADCONFIG23,Register to control pin configuration and muxing" bitfld.long 0x5C 31. "PADCONFIG23_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x5C 30. "PADCONFIG23_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x5C 29. "PADCONFIG23_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x5C 28. "PADCONFIG23_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x5C 27. "PADCONFIG23_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x5C 26. "PADCONFIG23_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x5C 25. "PADCONFIG23_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x5C 24. "PADCONFIG23_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x5C 23. "PADCONFIG23_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x5C 22. "PADCONFIG23_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x5C 21. "PADCONFIG23_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x5C 19.--20. "PADCONFIG23_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x5C 18. "PADCONFIG23_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x5C 17. "PADCONFIG23_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x5C 16. "PADCONFIG23_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x5C 15. "PADCONFIG23_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x5C 14. "PADCONFIG23_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x5C 11.--13. "PADCONFIG23_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x5C 8. "PADCONFIG23_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x5C 7. "PADCONFIG23_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x5C 4.--5. "PADCONFIG23_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x5C 0.--3. 1. "PADCONFIG23_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x60 "CFG0_PADCONFIG24,Register to control pin configuration and muxing" bitfld.long 0x60 31. "PADCONFIG24_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x60 30. "PADCONFIG24_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x60 29. "PADCONFIG24_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x60 28. "PADCONFIG24_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x60 27. "PADCONFIG24_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x60 26. "PADCONFIG24_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x60 25. "PADCONFIG24_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x60 24. "PADCONFIG24_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x60 23. "PADCONFIG24_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x60 22. "PADCONFIG24_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x60 21. "PADCONFIG24_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x60 19.--20. "PADCONFIG24_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x60 18. "PADCONFIG24_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x60 17. "PADCONFIG24_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x60 16. "PADCONFIG24_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x60 15. "PADCONFIG24_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x60 14. "PADCONFIG24_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x60 11.--13. "PADCONFIG24_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 8. "PADCONFIG24_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x60 7. "PADCONFIG24_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x60 4.--5. "PADCONFIG24_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x60 0.--3. 1. "PADCONFIG24_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x64 "CFG0_PADCONFIG25,Register to control pin configuration and muxing" bitfld.long 0x64 31. "PADCONFIG25_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x64 30. "PADCONFIG25_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x64 29. "PADCONFIG25_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x64 28. "PADCONFIG25_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x64 27. "PADCONFIG25_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x64 26. "PADCONFIG25_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x64 25. "PADCONFIG25_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x64 24. "PADCONFIG25_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x64 23. "PADCONFIG25_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x64 22. "PADCONFIG25_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x64 21. "PADCONFIG25_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x64 19.--20. "PADCONFIG25_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x64 18. "PADCONFIG25_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x64 17. "PADCONFIG25_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x64 16. "PADCONFIG25_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x64 15. "PADCONFIG25_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x64 14. "PADCONFIG25_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x64 11.--13. "PADCONFIG25_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x64 8. "PADCONFIG25_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x64 7. "PADCONFIG25_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x64 4.--5. "PADCONFIG25_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x64 0.--3. 1. "PADCONFIG25_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x68 "CFG0_PADCONFIG26,Register to control pin configuration and muxing" bitfld.long 0x68 31. "PADCONFIG26_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x68 30. "PADCONFIG26_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x68 29. "PADCONFIG26_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x68 28. "PADCONFIG26_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x68 27. "PADCONFIG26_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x68 26. "PADCONFIG26_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x68 25. "PADCONFIG26_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x68 24. "PADCONFIG26_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x68 23. "PADCONFIG26_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x68 22. "PADCONFIG26_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x68 21. "PADCONFIG26_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x68 19.--20. "PADCONFIG26_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x68 18. "PADCONFIG26_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x68 17. "PADCONFIG26_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x68 16. "PADCONFIG26_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x68 15. "PADCONFIG26_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x68 14. "PADCONFIG26_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x68 11.--13. "PADCONFIG26_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 8. "PADCONFIG26_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x68 7. "PADCONFIG26_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x68 4.--5. "PADCONFIG26_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x68 0.--3. 1. "PADCONFIG26_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x6C "CFG0_PADCONFIG27,Register to control pin configuration and muxing" bitfld.long 0x6C 31. "PADCONFIG27_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x6C 30. "PADCONFIG27_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x6C 29. "PADCONFIG27_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x6C 28. "PADCONFIG27_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x6C 27. "PADCONFIG27_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x6C 26. "PADCONFIG27_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x6C 25. "PADCONFIG27_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x6C 24. "PADCONFIG27_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x6C 23. "PADCONFIG27_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x6C 22. "PADCONFIG27_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x6C 21. "PADCONFIG27_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x6C 19.--20. "PADCONFIG27_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x6C 18. "PADCONFIG27_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x6C 17. "PADCONFIG27_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x6C 16. "PADCONFIG27_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x6C 15. "PADCONFIG27_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x6C 14. "PADCONFIG27_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x6C 11.--13. "PADCONFIG27_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x6C 8. "PADCONFIG27_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x6C 7. "PADCONFIG27_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x6C 4.--5. "PADCONFIG27_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x6C 0.--3. 1. "PADCONFIG27_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x70 "CFG0_PADCONFIG28,Register to control pin configuration and muxing" bitfld.long 0x70 31. "PADCONFIG28_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x70 30. "PADCONFIG28_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x70 29. "PADCONFIG28_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x70 28. "PADCONFIG28_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x70 27. "PADCONFIG28_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x70 26. "PADCONFIG28_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x70 25. "PADCONFIG28_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x70 24. "PADCONFIG28_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x70 23. "PADCONFIG28_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x70 22. "PADCONFIG28_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x70 21. "PADCONFIG28_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x70 19.--20. "PADCONFIG28_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x70 18. "PADCONFIG28_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x70 17. "PADCONFIG28_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x70 16. "PADCONFIG28_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x70 15. "PADCONFIG28_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x70 14. "PADCONFIG28_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x70 11.--13. "PADCONFIG28_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 8. "PADCONFIG28_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x70 7. "PADCONFIG28_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x70 4.--5. "PADCONFIG28_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x70 0.--3. 1. "PADCONFIG28_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x74 "CFG0_PADCONFIG29,Register to control pin configuration and muxing" bitfld.long 0x74 31. "PADCONFIG29_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x74 30. "PADCONFIG29_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x74 29. "PADCONFIG29_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x74 28. "PADCONFIG29_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x74 27. "PADCONFIG29_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x74 26. "PADCONFIG29_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x74 25. "PADCONFIG29_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x74 24. "PADCONFIG29_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x74 23. "PADCONFIG29_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x74 22. "PADCONFIG29_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x74 21. "PADCONFIG29_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x74 19.--20. "PADCONFIG29_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x74 18. "PADCONFIG29_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x74 17. "PADCONFIG29_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x74 16. "PADCONFIG29_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x74 15. "PADCONFIG29_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x74 14. "PADCONFIG29_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x74 11.--13. "PADCONFIG29_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x74 8. "PADCONFIG29_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x74 7. "PADCONFIG29_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x74 4.--5. "PADCONFIG29_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x74 0.--3. 1. "PADCONFIG29_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x78 "CFG0_PADCONFIG30,Register to control pin configuration and muxing" bitfld.long 0x78 31. "PADCONFIG30_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x78 30. "PADCONFIG30_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x78 29. "PADCONFIG30_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x78 28. "PADCONFIG30_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x78 27. "PADCONFIG30_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x78 26. "PADCONFIG30_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x78 25. "PADCONFIG30_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x78 24. "PADCONFIG30_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x78 23. "PADCONFIG30_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x78 22. "PADCONFIG30_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x78 21. "PADCONFIG30_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x78 19.--20. "PADCONFIG30_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x78 18. "PADCONFIG30_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x78 17. "PADCONFIG30_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x78 16. "PADCONFIG30_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x78 15. "PADCONFIG30_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x78 14. "PADCONFIG30_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x78 11.--13. "PADCONFIG30_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 8. "PADCONFIG30_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x78 7. "PADCONFIG30_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x78 4.--5. "PADCONFIG30_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x78 0.--3. 1. "PADCONFIG30_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x7C "CFG0_PADCONFIG31,Register to control pin configuration and muxing" bitfld.long 0x7C 31. "PADCONFIG31_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x7C 30. "PADCONFIG31_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x7C 29. "PADCONFIG31_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x7C 28. "PADCONFIG31_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x7C 27. "PADCONFIG31_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x7C 26. "PADCONFIG31_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x7C 25. "PADCONFIG31_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x7C 24. "PADCONFIG31_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x7C 23. "PADCONFIG31_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x7C 22. "PADCONFIG31_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x7C 21. "PADCONFIG31_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x7C 19.--20. "PADCONFIG31_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x7C 18. "PADCONFIG31_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x7C 17. "PADCONFIG31_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x7C 16. "PADCONFIG31_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x7C 15. "PADCONFIG31_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x7C 14. "PADCONFIG31_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x7C 11.--13. "PADCONFIG31_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x7C 8. "PADCONFIG31_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x7C 7. "PADCONFIG31_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x7C 4.--5. "PADCONFIG31_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x7C 0.--3. 1. "PADCONFIG31_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x80 "CFG0_PADCONFIG32,Register to control pin configuration and muxing" bitfld.long 0x80 31. "PADCONFIG32_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x80 30. "PADCONFIG32_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x80 29. "PADCONFIG32_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x80 28. "PADCONFIG32_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x80 27. "PADCONFIG32_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x80 26. "PADCONFIG32_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x80 25. "PADCONFIG32_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x80 24. "PADCONFIG32_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x80 23. "PADCONFIG32_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x80 22. "PADCONFIG32_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x80 21. "PADCONFIG32_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x80 19.--20. "PADCONFIG32_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x80 18. "PADCONFIG32_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x80 17. "PADCONFIG32_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x80 16. "PADCONFIG32_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x80 15. "PADCONFIG32_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x80 14. "PADCONFIG32_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x80 11.--13. "PADCONFIG32_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 8. "PADCONFIG32_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x80 7. "PADCONFIG32_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x80 4.--5. "PADCONFIG32_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x80 0.--3. 1. "PADCONFIG32_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x84 "CFG0_PADCONFIG33,Register to control pin configuration and muxing" bitfld.long 0x84 31. "PADCONFIG33_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x84 30. "PADCONFIG33_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x84 29. "PADCONFIG33_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x84 28. "PADCONFIG33_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x84 27. "PADCONFIG33_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x84 26. "PADCONFIG33_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x84 25. "PADCONFIG33_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x84 24. "PADCONFIG33_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x84 23. "PADCONFIG33_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x84 22. "PADCONFIG33_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x84 21. "PADCONFIG33_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x84 19.--20. "PADCONFIG33_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x84 18. "PADCONFIG33_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x84 17. "PADCONFIG33_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x84 16. "PADCONFIG33_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x84 15. "PADCONFIG33_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x84 14. "PADCONFIG33_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x84 11.--13. "PADCONFIG33_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x84 8. "PADCONFIG33_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x84 7. "PADCONFIG33_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x84 4.--5. "PADCONFIG33_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x84 0.--3. 1. "PADCONFIG33_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x88 "CFG0_PADCONFIG34,Register to control pin configuration and muxing" bitfld.long 0x88 31. "PADCONFIG34_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x88 30. "PADCONFIG34_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x88 29. "PADCONFIG34_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x88 28. "PADCONFIG34_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x88 27. "PADCONFIG34_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x88 26. "PADCONFIG34_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x88 25. "PADCONFIG34_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x88 24. "PADCONFIG34_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x88 23. "PADCONFIG34_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x88 22. "PADCONFIG34_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x88 21. "PADCONFIG34_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x88 19.--20. "PADCONFIG34_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x88 18. "PADCONFIG34_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x88 17. "PADCONFIG34_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x88 16. "PADCONFIG34_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x88 15. "PADCONFIG34_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x88 14. "PADCONFIG34_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x88 11.--13. "PADCONFIG34_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 8. "PADCONFIG34_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x88 7. "PADCONFIG34_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x88 4.--5. "PADCONFIG34_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x88 0.--3. 1. "PADCONFIG34_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x8C "CFG0_PADCONFIG35,Register to control pin configuration and muxing" bitfld.long 0x8C 31. "PADCONFIG35_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x8C 30. "PADCONFIG35_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x8C 29. "PADCONFIG35_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x8C 28. "PADCONFIG35_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x8C 27. "PADCONFIG35_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x8C 26. "PADCONFIG35_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x8C 25. "PADCONFIG35_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x8C 24. "PADCONFIG35_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x8C 23. "PADCONFIG35_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x8C 22. "PADCONFIG35_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x8C 21. "PADCONFIG35_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x8C 19.--20. "PADCONFIG35_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8C 18. "PADCONFIG35_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x8C 17. "PADCONFIG35_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x8C 16. "PADCONFIG35_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x8C 15. "PADCONFIG35_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x8C 14. "PADCONFIG35_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x8C 11.--13. "PADCONFIG35_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8C 8. "PADCONFIG35_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x8C 7. "PADCONFIG35_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x8C 4.--5. "PADCONFIG35_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x8C 0.--3. 1. "PADCONFIG35_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x90 "CFG0_PADCONFIG36,Register to control pin configuration and muxing" bitfld.long 0x90 31. "PADCONFIG36_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x90 30. "PADCONFIG36_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x90 29. "PADCONFIG36_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x90 28. "PADCONFIG36_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x90 27. "PADCONFIG36_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x90 26. "PADCONFIG36_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x90 25. "PADCONFIG36_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x90 24. "PADCONFIG36_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x90 23. "PADCONFIG36_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x90 22. "PADCONFIG36_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x90 21. "PADCONFIG36_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x90 19.--20. "PADCONFIG36_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x90 18. "PADCONFIG36_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x90 17. "PADCONFIG36_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x90 16. "PADCONFIG36_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x90 15. "PADCONFIG36_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x90 14. "PADCONFIG36_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x90 11.--13. "PADCONFIG36_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 8. "PADCONFIG36_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x90 7. "PADCONFIG36_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x90 4.--5. "PADCONFIG36_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x90 0.--3. 1. "PADCONFIG36_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x94 "CFG0_PADCONFIG37,Register to control pin configuration and muxing" bitfld.long 0x94 31. "PADCONFIG37_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x94 30. "PADCONFIG37_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x94 29. "PADCONFIG37_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x94 28. "PADCONFIG37_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x94 27. "PADCONFIG37_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x94 26. "PADCONFIG37_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x94 25. "PADCONFIG37_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x94 24. "PADCONFIG37_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x94 23. "PADCONFIG37_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x94 22. "PADCONFIG37_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x94 21. "PADCONFIG37_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x94 19.--20. "PADCONFIG37_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x94 18. "PADCONFIG37_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x94 17. "PADCONFIG37_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x94 16. "PADCONFIG37_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x94 15. "PADCONFIG37_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x94 14. "PADCONFIG37_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x94 11.--13. "PADCONFIG37_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x94 8. "PADCONFIG37_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x94 7. "PADCONFIG37_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x94 4.--5. "PADCONFIG37_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x94 0.--3. 1. "PADCONFIG37_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x98 "CFG0_PADCONFIG38,Register to control pin configuration and muxing" bitfld.long 0x98 31. "PADCONFIG38_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x98 30. "PADCONFIG38_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x98 29. "PADCONFIG38_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x98 28. "PADCONFIG38_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x98 27. "PADCONFIG38_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x98 26. "PADCONFIG38_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x98 25. "PADCONFIG38_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x98 24. "PADCONFIG38_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x98 23. "PADCONFIG38_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x98 22. "PADCONFIG38_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x98 21. "PADCONFIG38_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x98 19.--20. "PADCONFIG38_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x98 18. "PADCONFIG38_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x98 17. "PADCONFIG38_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x98 16. "PADCONFIG38_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x98 15. "PADCONFIG38_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x98 14. "PADCONFIG38_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x98 11.--13. "PADCONFIG38_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 8. "PADCONFIG38_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x98 7. "PADCONFIG38_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x98 4.--5. "PADCONFIG38_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x98 0.--3. 1. "PADCONFIG38_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x9C "CFG0_PADCONFIG39,Register to control pin configuration and muxing" bitfld.long 0x9C 31. "PADCONFIG39_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x9C 30. "PADCONFIG39_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x9C 29. "PADCONFIG39_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x9C 28. "PADCONFIG39_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x9C 27. "PADCONFIG39_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x9C 26. "PADCONFIG39_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x9C 25. "PADCONFIG39_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x9C 24. "PADCONFIG39_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x9C 23. "PADCONFIG39_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x9C 22. "PADCONFIG39_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x9C 21. "PADCONFIG39_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x9C 19.--20. "PADCONFIG39_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x9C 18. "PADCONFIG39_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x9C 17. "PADCONFIG39_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x9C 16. "PADCONFIG39_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x9C 15. "PADCONFIG39_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x9C 14. "PADCONFIG39_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x9C 11.--13. "PADCONFIG39_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x9C 8. "PADCONFIG39_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x9C 7. "PADCONFIG39_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x9C 4.--5. "PADCONFIG39_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x9C 0.--3. 1. "PADCONFIG39_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xA0 "CFG0_PADCONFIG40,Register to control pin configuration and muxing" bitfld.long 0xA0 31. "PADCONFIG40_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xA0 30. "PADCONFIG40_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xA0 29. "PADCONFIG40_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xA0 28. "PADCONFIG40_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xA0 27. "PADCONFIG40_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xA0 26. "PADCONFIG40_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xA0 25. "PADCONFIG40_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xA0 24. "PADCONFIG40_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xA0 23. "PADCONFIG40_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xA0 22. "PADCONFIG40_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xA0 21. "PADCONFIG40_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xA0 19.--20. "PADCONFIG40_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xA0 18. "PADCONFIG40_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xA0 17. "PADCONFIG40_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xA0 16. "PADCONFIG40_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xA0 15. "PADCONFIG40_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xA0 14. "PADCONFIG40_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xA0 11.--13. "PADCONFIG40_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 8. "PADCONFIG40_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xA0 7. "PADCONFIG40_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xA0 4.--5. "PADCONFIG40_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xA0 0.--3. 1. "PADCONFIG40_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xA4 "CFG0_PADCONFIG41,Register to control pin configuration and muxing" bitfld.long 0xA4 31. "PADCONFIG41_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xA4 30. "PADCONFIG41_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xA4 29. "PADCONFIG41_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xA4 28. "PADCONFIG41_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xA4 27. "PADCONFIG41_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xA4 26. "PADCONFIG41_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xA4 25. "PADCONFIG41_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xA4 24. "PADCONFIG41_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xA4 23. "PADCONFIG41_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xA4 22. "PADCONFIG41_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xA4 21. "PADCONFIG41_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xA4 19.--20. "PADCONFIG41_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xA4 18. "PADCONFIG41_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xA4 17. "PADCONFIG41_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xA4 16. "PADCONFIG41_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xA4 15. "PADCONFIG41_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xA4 14. "PADCONFIG41_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xA4 11.--13. "PADCONFIG41_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA4 8. "PADCONFIG41_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xA4 7. "PADCONFIG41_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xA4 4.--5. "PADCONFIG41_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xA4 0.--3. 1. "PADCONFIG41_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xA8 "CFG0_PADCONFIG42,Register to control pin configuration and muxing" bitfld.long 0xA8 31. "PADCONFIG42_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xA8 30. "PADCONFIG42_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xA8 29. "PADCONFIG42_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xA8 28. "PADCONFIG42_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xA8 27. "PADCONFIG42_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xA8 26. "PADCONFIG42_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xA8 25. "PADCONFIG42_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xA8 24. "PADCONFIG42_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xA8 23. "PADCONFIG42_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xA8 22. "PADCONFIG42_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xA8 21. "PADCONFIG42_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xA8 19.--20. "PADCONFIG42_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xA8 18. "PADCONFIG42_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xA8 17. "PADCONFIG42_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xA8 16. "PADCONFIG42_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xA8 15. "PADCONFIG42_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xA8 14. "PADCONFIG42_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xA8 11.--13. "PADCONFIG42_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 8. "PADCONFIG42_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xA8 7. "PADCONFIG42_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xA8 4.--5. "PADCONFIG42_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xA8 0.--3. 1. "PADCONFIG42_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xAC "CFG0_PADCONFIG43,Register to control pin configuration and muxing" bitfld.long 0xAC 31. "PADCONFIG43_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xAC 30. "PADCONFIG43_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xAC 29. "PADCONFIG43_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xAC 28. "PADCONFIG43_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xAC 27. "PADCONFIG43_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xAC 26. "PADCONFIG43_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xAC 25. "PADCONFIG43_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xAC 24. "PADCONFIG43_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xAC 23. "PADCONFIG43_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xAC 22. "PADCONFIG43_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xAC 21. "PADCONFIG43_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xAC 19.--20. "PADCONFIG43_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xAC 18. "PADCONFIG43_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xAC 17. "PADCONFIG43_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xAC 16. "PADCONFIG43_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xAC 15. "PADCONFIG43_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xAC 14. "PADCONFIG43_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xAC 11.--13. "PADCONFIG43_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xAC 8. "PADCONFIG43_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xAC 7. "PADCONFIG43_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xAC 4.--5. "PADCONFIG43_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xAC 0.--3. 1. "PADCONFIG43_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xB0 "CFG0_PADCONFIG44,Register to control pin configuration and muxing" bitfld.long 0xB0 31. "PADCONFIG44_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xB0 30. "PADCONFIG44_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xB0 29. "PADCONFIG44_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xB0 28. "PADCONFIG44_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xB0 27. "PADCONFIG44_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xB0 26. "PADCONFIG44_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xB0 25. "PADCONFIG44_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xB0 24. "PADCONFIG44_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xB0 23. "PADCONFIG44_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xB0 22. "PADCONFIG44_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xB0 21. "PADCONFIG44_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xB0 19.--20. "PADCONFIG44_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB0 18. "PADCONFIG44_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xB0 17. "PADCONFIG44_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xB0 16. "PADCONFIG44_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xB0 15. "PADCONFIG44_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xB0 14. "PADCONFIG44_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xB0 11.--13. "PADCONFIG44_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 8. "PADCONFIG44_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xB0 7. "PADCONFIG44_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xB0 4.--5. "PADCONFIG44_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xB0 0.--3. 1. "PADCONFIG44_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xB4 "CFG0_PADCONFIG45,Register to control pin configuration and muxing" bitfld.long 0xB4 31. "PADCONFIG45_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xB4 30. "PADCONFIG45_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xB4 29. "PADCONFIG45_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xB4 28. "PADCONFIG45_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xB4 27. "PADCONFIG45_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xB4 26. "PADCONFIG45_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xB4 25. "PADCONFIG45_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xB4 24. "PADCONFIG45_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xB4 23. "PADCONFIG45_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xB4 22. "PADCONFIG45_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xB4 21. "PADCONFIG45_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xB4 19.--20. "PADCONFIG45_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB4 18. "PADCONFIG45_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xB4 17. "PADCONFIG45_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xB4 16. "PADCONFIG45_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xB4 15. "PADCONFIG45_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xB4 14. "PADCONFIG45_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xB4 11.--13. "PADCONFIG45_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB4 8. "PADCONFIG45_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xB4 7. "PADCONFIG45_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xB4 4.--5. "PADCONFIG45_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xB4 0.--3. 1. "PADCONFIG45_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xB8 "CFG0_PADCONFIG46,Register to control pin configuration and muxing" bitfld.long 0xB8 31. "PADCONFIG46_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xB8 30. "PADCONFIG46_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xB8 29. "PADCONFIG46_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xB8 28. "PADCONFIG46_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xB8 27. "PADCONFIG46_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xB8 26. "PADCONFIG46_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xB8 25. "PADCONFIG46_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xB8 24. "PADCONFIG46_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xB8 23. "PADCONFIG46_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xB8 22. "PADCONFIG46_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xB8 21. "PADCONFIG46_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xB8 19.--20. "PADCONFIG46_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB8 18. "PADCONFIG46_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xB8 17. "PADCONFIG46_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xB8 16. "PADCONFIG46_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xB8 15. "PADCONFIG46_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xB8 14. "PADCONFIG46_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xB8 11.--13. "PADCONFIG46_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 8. "PADCONFIG46_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xB8 7. "PADCONFIG46_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xB8 4.--5. "PADCONFIG46_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xB8 0.--3. 1. "PADCONFIG46_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xBC "CFG0_PADCONFIG47,Register to control pin configuration and muxing" bitfld.long 0xBC 31. "PADCONFIG47_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xBC 30. "PADCONFIG47_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xBC 29. "PADCONFIG47_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xBC 28. "PADCONFIG47_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xBC 27. "PADCONFIG47_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xBC 26. "PADCONFIG47_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xBC 25. "PADCONFIG47_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xBC 24. "PADCONFIG47_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xBC 23. "PADCONFIG47_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xBC 22. "PADCONFIG47_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xBC 21. "PADCONFIG47_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xBC 19.--20. "PADCONFIG47_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xBC 18. "PADCONFIG47_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xBC 17. "PADCONFIG47_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xBC 16. "PADCONFIG47_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xBC 15. "PADCONFIG47_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xBC 14. "PADCONFIG47_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xBC 11.--13. "PADCONFIG47_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xBC 8. "PADCONFIG47_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xBC 7. "PADCONFIG47_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xBC 4.--5. "PADCONFIG47_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xBC 0.--3. 1. "PADCONFIG47_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xC0 "CFG0_PADCONFIG48,Register to control pin configuration and muxing" bitfld.long 0xC0 31. "PADCONFIG48_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xC0 30. "PADCONFIG48_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xC0 29. "PADCONFIG48_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xC0 28. "PADCONFIG48_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xC0 27. "PADCONFIG48_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xC0 26. "PADCONFIG48_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xC0 25. "PADCONFIG48_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xC0 24. "PADCONFIG48_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xC0 23. "PADCONFIG48_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xC0 22. "PADCONFIG48_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xC0 21. "PADCONFIG48_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xC0 19.--20. "PADCONFIG48_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC0 18. "PADCONFIG48_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xC0 17. "PADCONFIG48_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xC0 16. "PADCONFIG48_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xC0 15. "PADCONFIG48_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xC0 14. "PADCONFIG48_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xC0 11.--13. "PADCONFIG48_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 8. "PADCONFIG48_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xC0 7. "PADCONFIG48_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xC0 4.--5. "PADCONFIG48_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xC0 0.--3. 1. "PADCONFIG48_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xC4 "CFG0_PADCONFIG49,Register to control pin configuration and muxing" bitfld.long 0xC4 31. "PADCONFIG49_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xC4 30. "PADCONFIG49_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xC4 29. "PADCONFIG49_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xC4 28. "PADCONFIG49_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xC4 27. "PADCONFIG49_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xC4 26. "PADCONFIG49_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xC4 25. "PADCONFIG49_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xC4 24. "PADCONFIG49_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xC4 23. "PADCONFIG49_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xC4 22. "PADCONFIG49_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xC4 21. "PADCONFIG49_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xC4 19.--20. "PADCONFIG49_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC4 18. "PADCONFIG49_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xC4 17. "PADCONFIG49_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xC4 16. "PADCONFIG49_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xC4 15. "PADCONFIG49_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xC4 14. "PADCONFIG49_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xC4 11.--13. "PADCONFIG49_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC4 8. "PADCONFIG49_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xC4 7. "PADCONFIG49_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xC4 4.--5. "PADCONFIG49_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xC4 0.--3. 1. "PADCONFIG49_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xC8 "CFG0_PADCONFIG50,Register to control pin configuration and muxing" bitfld.long 0xC8 31. "PADCONFIG50_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xC8 30. "PADCONFIG50_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xC8 29. "PADCONFIG50_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xC8 28. "PADCONFIG50_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xC8 27. "PADCONFIG50_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xC8 26. "PADCONFIG50_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xC8 25. "PADCONFIG50_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xC8 24. "PADCONFIG50_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xC8 23. "PADCONFIG50_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xC8 22. "PADCONFIG50_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xC8 21. "PADCONFIG50_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xC8 19.--20. "PADCONFIG50_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC8 18. "PADCONFIG50_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xC8 17. "PADCONFIG50_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xC8 16. "PADCONFIG50_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xC8 15. "PADCONFIG50_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xC8 14. "PADCONFIG50_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xC8 11.--13. "PADCONFIG50_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 8. "PADCONFIG50_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xC8 7. "PADCONFIG50_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xC8 4.--5. "PADCONFIG50_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xC8 0.--3. 1. "PADCONFIG50_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xCC "CFG0_PADCONFIG51,Register to control pin configuration and muxing" bitfld.long 0xCC 31. "PADCONFIG51_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xCC 30. "PADCONFIG51_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xCC 29. "PADCONFIG51_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xCC 28. "PADCONFIG51_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xCC 27. "PADCONFIG51_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xCC 26. "PADCONFIG51_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xCC 25. "PADCONFIG51_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xCC 24. "PADCONFIG51_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xCC 23. "PADCONFIG51_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xCC 22. "PADCONFIG51_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xCC 21. "PADCONFIG51_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xCC 19.--20. "PADCONFIG51_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xCC 18. "PADCONFIG51_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xCC 17. "PADCONFIG51_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xCC 16. "PADCONFIG51_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xCC 15. "PADCONFIG51_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xCC 14. "PADCONFIG51_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xCC 11.--13. "PADCONFIG51_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xCC 8. "PADCONFIG51_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xCC 7. "PADCONFIG51_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xCC 4.--5. "PADCONFIG51_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xCC 0.--3. 1. "PADCONFIG51_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xD0 "CFG0_PADCONFIG52,Register to control pin configuration and muxing" bitfld.long 0xD0 31. "PADCONFIG52_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xD0 30. "PADCONFIG52_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xD0 29. "PADCONFIG52_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xD0 28. "PADCONFIG52_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xD0 27. "PADCONFIG52_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xD0 26. "PADCONFIG52_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xD0 25. "PADCONFIG52_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xD0 24. "PADCONFIG52_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xD0 23. "PADCONFIG52_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xD0 22. "PADCONFIG52_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xD0 21. "PADCONFIG52_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xD0 19.--20. "PADCONFIG52_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xD0 18. "PADCONFIG52_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xD0 17. "PADCONFIG52_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xD0 16. "PADCONFIG52_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xD0 15. "PADCONFIG52_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xD0 14. "PADCONFIG52_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xD0 11.--13. "PADCONFIG52_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 8. "PADCONFIG52_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xD0 7. "PADCONFIG52_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xD0 4.--5. "PADCONFIG52_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xD0 0.--3. 1. "PADCONFIG52_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xD4 "CFG0_PADCONFIG53,Register to control pin configuration and muxing" bitfld.long 0xD4 31. "PADCONFIG53_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xD4 30. "PADCONFIG53_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xD4 29. "PADCONFIG53_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xD4 28. "PADCONFIG53_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xD4 27. "PADCONFIG53_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xD4 26. "PADCONFIG53_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xD4 25. "PADCONFIG53_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xD4 24. "PADCONFIG53_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xD4 23. "PADCONFIG53_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xD4 22. "PADCONFIG53_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xD4 21. "PADCONFIG53_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xD4 19.--20. "PADCONFIG53_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xD4 18. "PADCONFIG53_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xD4 17. "PADCONFIG53_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xD4 16. "PADCONFIG53_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xD4 15. "PADCONFIG53_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xD4 14. "PADCONFIG53_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xD4 11.--13. "PADCONFIG53_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD4 8. "PADCONFIG53_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xD4 7. "PADCONFIG53_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xD4 4.--5. "PADCONFIG53_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xD4 0.--3. 1. "PADCONFIG53_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xD8 "CFG0_PADCONFIG54,Register to control pin configuration and muxing" bitfld.long 0xD8 31. "PADCONFIG54_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xD8 30. "PADCONFIG54_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xD8 29. "PADCONFIG54_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xD8 28. "PADCONFIG54_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xD8 27. "PADCONFIG54_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xD8 26. "PADCONFIG54_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xD8 25. "PADCONFIG54_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xD8 24. "PADCONFIG54_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xD8 23. "PADCONFIG54_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xD8 22. "PADCONFIG54_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xD8 21. "PADCONFIG54_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xD8 19.--20. "PADCONFIG54_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xD8 18. "PADCONFIG54_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xD8 17. "PADCONFIG54_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xD8 16. "PADCONFIG54_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xD8 15. "PADCONFIG54_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xD8 14. "PADCONFIG54_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xD8 11.--13. "PADCONFIG54_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 8. "PADCONFIG54_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xD8 7. "PADCONFIG54_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xD8 4.--5. "PADCONFIG54_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xD8 0.--3. 1. "PADCONFIG54_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xDC "CFG0_PADCONFIG55,Register to control pin configuration and muxing" bitfld.long 0xDC 31. "PADCONFIG55_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xDC 30. "PADCONFIG55_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xDC 29. "PADCONFIG55_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xDC 28. "PADCONFIG55_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xDC 27. "PADCONFIG55_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xDC 26. "PADCONFIG55_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xDC 25. "PADCONFIG55_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xDC 24. "PADCONFIG55_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xDC 23. "PADCONFIG55_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xDC 22. "PADCONFIG55_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xDC 21. "PADCONFIG55_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xDC 19.--20. "PADCONFIG55_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xDC 18. "PADCONFIG55_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xDC 17. "PADCONFIG55_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xDC 16. "PADCONFIG55_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xDC 15. "PADCONFIG55_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xDC 14. "PADCONFIG55_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xDC 11.--13. "PADCONFIG55_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xDC 8. "PADCONFIG55_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xDC 7. "PADCONFIG55_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xDC 4.--5. "PADCONFIG55_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xDC 0.--3. 1. "PADCONFIG55_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xE0 "CFG0_PADCONFIG56,Register to control pin configuration and muxing" bitfld.long 0xE0 31. "PADCONFIG56_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xE0 30. "PADCONFIG56_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xE0 29. "PADCONFIG56_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xE0 26. "PADCONFIG56_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xE0 25. "PADCONFIG56_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xE0 24. "PADCONFIG56_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xE0 23. "PADCONFIG56_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xE0 22. "PADCONFIG56_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xE0 21. "PADCONFIG56_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xE0 18. "PADCONFIG56_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xE0 15. "PADCONFIG56_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xE0 14. "PADCONFIG56_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xE0 11.--13. "PADCONFIG56_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 8. "PADCONFIG56_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xE0 7. "PADCONFIG56_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xE0 4.--5. "PADCONFIG56_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xE0 0.--3. 1. "PADCONFIG56_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xE4 "CFG0_PADCONFIG57,Register to control pin configuration and muxing" bitfld.long 0xE4 31. "PADCONFIG57_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xE4 30. "PADCONFIG57_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xE4 29. "PADCONFIG57_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xE4 26. "PADCONFIG57_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xE4 25. "PADCONFIG57_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xE4 24. "PADCONFIG57_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xE4 23. "PADCONFIG57_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xE4 22. "PADCONFIG57_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xE4 21. "PADCONFIG57_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xE4 18. "PADCONFIG57_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xE4 15. "PADCONFIG57_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xE4 14. "PADCONFIG57_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xE4 11.--13. "PADCONFIG57_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE4 8. "PADCONFIG57_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xE4 7. "PADCONFIG57_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xE4 4.--5. "PADCONFIG57_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xE4 0.--3. 1. "PADCONFIG57_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xE8 "CFG0_PADCONFIG58,Register to control pin configuration and muxing" bitfld.long 0xE8 31. "PADCONFIG58_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xE8 30. "PADCONFIG58_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xE8 29. "PADCONFIG58_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xE8 28. "PADCONFIG58_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xE8 27. "PADCONFIG58_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xE8 26. "PADCONFIG58_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xE8 25. "PADCONFIG58_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xE8 24. "PADCONFIG58_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xE8 23. "PADCONFIG58_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xE8 22. "PADCONFIG58_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xE8 21. "PADCONFIG58_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xE8 19.--20. "PADCONFIG58_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xE8 18. "PADCONFIG58_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xE8 17. "PADCONFIG58_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xE8 16. "PADCONFIG58_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xE8 15. "PADCONFIG58_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xE8 14. "PADCONFIG58_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xE8 11.--13. "PADCONFIG58_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 8. "PADCONFIG58_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xE8 7. "PADCONFIG58_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xE8 4.--5. "PADCONFIG58_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xE8 0.--3. 1. "PADCONFIG58_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xEC "CFG0_PADCONFIG59,Register to control pin configuration and muxing" bitfld.long 0xEC 31. "PADCONFIG59_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xEC 30. "PADCONFIG59_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xEC 29. "PADCONFIG59_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xEC 28. "PADCONFIG59_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xEC 27. "PADCONFIG59_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xEC 26. "PADCONFIG59_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xEC 25. "PADCONFIG59_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xEC 24. "PADCONFIG59_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xEC 23. "PADCONFIG59_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xEC 22. "PADCONFIG59_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xEC 21. "PADCONFIG59_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xEC 19.--20. "PADCONFIG59_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xEC 18. "PADCONFIG59_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xEC 17. "PADCONFIG59_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xEC 16. "PADCONFIG59_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xEC 15. "PADCONFIG59_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xEC 14. "PADCONFIG59_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xEC 11.--13. "PADCONFIG59_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xEC 8. "PADCONFIG59_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xEC 7. "PADCONFIG59_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xEC 4.--5. "PADCONFIG59_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xEC 0.--3. 1. "PADCONFIG59_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xF0 "CFG0_PADCONFIG60,Register to control pin configuration and muxing" bitfld.long 0xF0 31. "PADCONFIG60_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xF0 30. "PADCONFIG60_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xF0 29. "PADCONFIG60_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xF0 28. "PADCONFIG60_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xF0 27. "PADCONFIG60_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xF0 26. "PADCONFIG60_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xF0 25. "PADCONFIG60_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xF0 24. "PADCONFIG60_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xF0 23. "PADCONFIG60_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xF0 22. "PADCONFIG60_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xF0 21. "PADCONFIG60_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xF0 18. "PADCONFIG60_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xF0 17. "PADCONFIG60_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xF0 16. "PADCONFIG60_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xF0 15. "PADCONFIG60_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xF0 14. "PADCONFIG60_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xF0 11.--13. "PADCONFIG60_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 8. "PADCONFIG60_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xF0 7. "PADCONFIG60_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xF0 4.--5. "PADCONFIG60_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xF0 0.--3. 1. "PADCONFIG60_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xF4 "CFG0_PADCONFIG61,Register to control pin configuration and muxing" bitfld.long 0xF4 31. "PADCONFIG61_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xF4 30. "PADCONFIG61_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xF4 29. "PADCONFIG61_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xF4 28. "PADCONFIG61_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xF4 27. "PADCONFIG61_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xF4 26. "PADCONFIG61_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xF4 25. "PADCONFIG61_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xF4 24. "PADCONFIG61_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xF4 23. "PADCONFIG61_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xF4 22. "PADCONFIG61_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xF4 21. "PADCONFIG61_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xF4 18. "PADCONFIG61_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xF4 17. "PADCONFIG61_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xF4 16. "PADCONFIG61_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xF4 15. "PADCONFIG61_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xF4 14. "PADCONFIG61_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xF4 11.--13. "PADCONFIG61_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF4 8. "PADCONFIG61_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xF4 7. "PADCONFIG61_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xF4 4.--5. "PADCONFIG61_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xF4 0.--3. 1. "PADCONFIG61_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xF8 "CFG0_PADCONFIG62,Register to control pin configuration and muxing" bitfld.long 0xF8 31. "PADCONFIG62_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xF8 30. "PADCONFIG62_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xF8 29. "PADCONFIG62_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xF8 28. "PADCONFIG62_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xF8 27. "PADCONFIG62_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xF8 26. "PADCONFIG62_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xF8 25. "PADCONFIG62_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xF8 24. "PADCONFIG62_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xF8 23. "PADCONFIG62_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xF8 22. "PADCONFIG62_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xF8 21. "PADCONFIG62_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xF8 18. "PADCONFIG62_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xF8 17. "PADCONFIG62_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xF8 16. "PADCONFIG62_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xF8 15. "PADCONFIG62_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xF8 14. "PADCONFIG62_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xF8 11.--13. "PADCONFIG62_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 8. "PADCONFIG62_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xF8 7. "PADCONFIG62_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xF8 4.--5. "PADCONFIG62_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xF8 0.--3. 1. "PADCONFIG62_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0xFC "CFG0_PADCONFIG63,Register to control pin configuration and muxing" bitfld.long 0xFC 31. "PADCONFIG63_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xFC 30. "PADCONFIG63_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xFC 29. "PADCONFIG63_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xFC 28. "PADCONFIG63_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xFC 27. "PADCONFIG63_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xFC 26. "PADCONFIG63_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xFC 25. "PADCONFIG63_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xFC 24. "PADCONFIG63_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xFC 23. "PADCONFIG63_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xFC 22. "PADCONFIG63_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xFC 21. "PADCONFIG63_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xFC 18. "PADCONFIG63_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xFC 17. "PADCONFIG63_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xFC 16. "PADCONFIG63_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xFC 15. "PADCONFIG63_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xFC 14. "PADCONFIG63_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xFC 11.--13. "PADCONFIG63_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xFC 8. "PADCONFIG63_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xFC 7. "PADCONFIG63_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xFC 4.--5. "PADCONFIG63_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xFC 0.--3. 1. "PADCONFIG63_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x100 "CFG0_PADCONFIG64,Register to control pin configuration and muxing" bitfld.long 0x100 31. "PADCONFIG64_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x100 30. "PADCONFIG64_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x100 29. "PADCONFIG64_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x100 28. "PADCONFIG64_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x100 27. "PADCONFIG64_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x100 26. "PADCONFIG64_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x100 25. "PADCONFIG64_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x100 24. "PADCONFIG64_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x100 23. "PADCONFIG64_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x100 22. "PADCONFIG64_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x100 21. "PADCONFIG64_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x100 18. "PADCONFIG64_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x100 17. "PADCONFIG64_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x100 16. "PADCONFIG64_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x100 15. "PADCONFIG64_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x100 14. "PADCONFIG64_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x100 11.--13. "PADCONFIG64_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x100 8. "PADCONFIG64_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x100 7. "PADCONFIG64_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x100 4.--5. "PADCONFIG64_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x100 0.--3. 1. "PADCONFIG64_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x104 "CFG0_PADCONFIG65,Register to control pin configuration and muxing" bitfld.long 0x104 31. "PADCONFIG65_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x104 30. "PADCONFIG65_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x104 29. "PADCONFIG65_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x104 28. "PADCONFIG65_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x104 27. "PADCONFIG65_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x104 26. "PADCONFIG65_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x104 25. "PADCONFIG65_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x104 24. "PADCONFIG65_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x104 23. "PADCONFIG65_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x104 22. "PADCONFIG65_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x104 21. "PADCONFIG65_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x104 18. "PADCONFIG65_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x104 17. "PADCONFIG65_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x104 16. "PADCONFIG65_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x104 15. "PADCONFIG65_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x104 14. "PADCONFIG65_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x104 11.--13. "PADCONFIG65_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x104 8. "PADCONFIG65_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x104 7. "PADCONFIG65_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x104 4.--5. "PADCONFIG65_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x104 0.--3. 1. "PADCONFIG65_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x108 "CFG0_PADCONFIG66,Register to control pin configuration and muxing" bitfld.long 0x108 31. "PADCONFIG66_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x108 30. "PADCONFIG66_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x108 29. "PADCONFIG66_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x108 28. "PADCONFIG66_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x108 27. "PADCONFIG66_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x108 26. "PADCONFIG66_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x108 25. "PADCONFIG66_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x108 24. "PADCONFIG66_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x108 23. "PADCONFIG66_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x108 22. "PADCONFIG66_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x108 21. "PADCONFIG66_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x108 18. "PADCONFIG66_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x108 17. "PADCONFIG66_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x108 16. "PADCONFIG66_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x108 15. "PADCONFIG66_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x108 14. "PADCONFIG66_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x108 11.--13. "PADCONFIG66_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x108 8. "PADCONFIG66_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x108 7. "PADCONFIG66_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x108 4.--5. "PADCONFIG66_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x108 0.--3. 1. "PADCONFIG66_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x10C "CFG0_PADCONFIG67,Register to control pin configuration and muxing" bitfld.long 0x10C 31. "PADCONFIG67_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x10C 30. "PADCONFIG67_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x10C 29. "PADCONFIG67_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x10C 28. "PADCONFIG67_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x10C 27. "PADCONFIG67_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x10C 26. "PADCONFIG67_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x10C 25. "PADCONFIG67_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x10C 24. "PADCONFIG67_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x10C 23. "PADCONFIG67_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x10C 22. "PADCONFIG67_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x10C 21. "PADCONFIG67_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x10C 19.--20. "PADCONFIG67_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x10C 18. "PADCONFIG67_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x10C 17. "PADCONFIG67_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x10C 16. "PADCONFIG67_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x10C 15. "PADCONFIG67_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x10C 14. "PADCONFIG67_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x10C 11.--13. "PADCONFIG67_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10C 8. "PADCONFIG67_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x10C 7. "PADCONFIG67_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x10C 4.--5. "PADCONFIG67_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x10C 0.--3. 1. "PADCONFIG67_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x110 "CFG0_PADCONFIG68,Register to control pin configuration and muxing" bitfld.long 0x110 31. "PADCONFIG68_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x110 30. "PADCONFIG68_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x110 29. "PADCONFIG68_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x110 28. "PADCONFIG68_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x110 27. "PADCONFIG68_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x110 26. "PADCONFIG68_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x110 25. "PADCONFIG68_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x110 24. "PADCONFIG68_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x110 23. "PADCONFIG68_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x110 22. "PADCONFIG68_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x110 21. "PADCONFIG68_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x110 19.--20. "PADCONFIG68_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x110 18. "PADCONFIG68_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x110 17. "PADCONFIG68_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x110 16. "PADCONFIG68_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x110 15. "PADCONFIG68_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x110 14. "PADCONFIG68_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x110 11.--13. "PADCONFIG68_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x110 8. "PADCONFIG68_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x110 7. "PADCONFIG68_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x110 4.--5. "PADCONFIG68_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x110 0.--3. 1. "PADCONFIG68_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x114 "CFG0_PADCONFIG69,Register to control pin configuration and muxing" bitfld.long 0x114 31. "PADCONFIG69_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x114 30. "PADCONFIG69_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x114 29. "PADCONFIG69_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x114 28. "PADCONFIG69_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x114 27. "PADCONFIG69_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x114 26. "PADCONFIG69_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x114 25. "PADCONFIG69_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x114 24. "PADCONFIG69_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x114 23. "PADCONFIG69_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x114 22. "PADCONFIG69_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x114 21. "PADCONFIG69_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x114 19.--20. "PADCONFIG69_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x114 18. "PADCONFIG69_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x114 17. "PADCONFIG69_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x114 16. "PADCONFIG69_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x114 15. "PADCONFIG69_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x114 14. "PADCONFIG69_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x114 11.--13. "PADCONFIG69_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x114 8. "PADCONFIG69_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x114 7. "PADCONFIG69_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x114 4.--5. "PADCONFIG69_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x114 0.--3. 1. "PADCONFIG69_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x118 "CFG0_PADCONFIG70,Register to control pin configuration and muxing" bitfld.long 0x118 31. "PADCONFIG70_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x118 30. "PADCONFIG70_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x118 29. "PADCONFIG70_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x118 28. "PADCONFIG70_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x118 27. "PADCONFIG70_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x118 26. "PADCONFIG70_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x118 25. "PADCONFIG70_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x118 24. "PADCONFIG70_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x118 23. "PADCONFIG70_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x118 22. "PADCONFIG70_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x118 21. "PADCONFIG70_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x118 19.--20. "PADCONFIG70_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x118 18. "PADCONFIG70_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x118 17. "PADCONFIG70_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x118 16. "PADCONFIG70_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x118 15. "PADCONFIG70_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x118 14. "PADCONFIG70_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x118 11.--13. "PADCONFIG70_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x118 8. "PADCONFIG70_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x118 7. "PADCONFIG70_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x118 4.--5. "PADCONFIG70_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x118 0.--3. 1. "PADCONFIG70_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." line.long 0x11C "CFG0_PADCONFIG71,Register to control pin configuration and muxing" bitfld.long 0x11C 31. "PADCONFIG71_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x11C 30. "PADCONFIG71_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x11C 29. "PADCONFIG71_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x11C 28. "PADCONFIG71_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x11C 27. "PADCONFIG71_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x11C 26. "PADCONFIG71_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x11C 25. "PADCONFIG71_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x11C 24. "PADCONFIG71_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x11C 23. "PADCONFIG71_ISO_BYP,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x11C 22. "PADCONFIG71_ISO_OVR,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x11C 21. "PADCONFIG71_TX_DIS,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x11C 19.--20. "PADCONFIG71_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x11C 18. "PADCONFIG71_RXACTIVE,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x11C 17. "PADCONFIG71_PULLTYPESEL,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x11C 16. "PADCONFIG71_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x11C 15. "PADCONFIG71_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x11C 14. "PADCONFIG71_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x11C 11.--13. "PADCONFIG71_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x11C 8. "PADCONFIG71_WK_LVL_POL,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x11C 7. "PADCONFIG71_WK_LVL_EN,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x11C 4.--5. "PADCONFIG71_VGPIO_SEL,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x11C 0.--3. 1. "PADCONFIG71_MUXMODE,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110.." rgroup.long 0x1D008++0x7 line.long 0x0 "CFG0_LOCK7_KICK0,This register must be written with the designated key value followed by a write to LOCK7_KICK1 with its key value before write-protected Partition 7 registers can be written." hexmask.long 0x0 0.--31. 1. "LOCK7_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK7_KICK1,This register must be written with the designated key value after a write to LOCK7_KICK0 with its key value before write-protected Partition 7 registers can be written." hexmask.long 0x4 0.--31. 1. "LOCK7_KICK1,- KICK1 component" rgroup.long 0x1D100++0xB line.long 0x0 "CFG0_CLAIMREG_P7_R0_READONLY," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P7_R0_READONLY,Claim bits for Partition 7" line.long 0x4 "CFG0_CLAIMREG_P7_R1_READONLY," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P7_R1_READONLY,Claim bits for Partition 7" line.long 0x8 "CFG0_CLAIMREG_P7_R2_READONLY," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P7_R2_READONLY,Claim bits for Partition 7" rgroup.long 0x1E000++0x11F line.long 0x0 "CFG0_PADCONFIG0_PROXY,Register to control pin configuration and muxing" bitfld.long 0x0 31. "PADCONFIG0_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x0 30. "PADCONFIG0_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x0 29. "PADCONFIG0_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x0 26. "PADCONFIG0_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x0 25. "PADCONFIG0_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x0 24. "PADCONFIG0_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x0 23. "PADCONFIG0_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x0 22. "PADCONFIG0_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x0 21. "PADCONFIG0_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x0 18. "PADCONFIG0_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x0 15. "PADCONFIG0_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x0 14. "PADCONFIG0_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x0 11.--13. "PADCONFIG0_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "PADCONFIG0_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x0 7. "PADCONFIG0_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x0 4.--5. "PADCONFIG0_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x0 0.--3. 1. "PADCONFIG0_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x4 "CFG0_PADCONFIG1_PROXY,Register to control pin configuration and muxing" bitfld.long 0x4 31. "PADCONFIG1_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x4 30. "PADCONFIG1_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x4 29. "PADCONFIG1_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x4 28. "PADCONFIG1_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x4 27. "PADCONFIG1_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x4 26. "PADCONFIG1_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x4 25. "PADCONFIG1_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x4 24. "PADCONFIG1_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x4 23. "PADCONFIG1_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x4 22. "PADCONFIG1_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x4 21. "PADCONFIG1_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x4 19.--20. "PADCONFIG1_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4 18. "PADCONFIG1_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x4 17. "PADCONFIG1_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x4 16. "PADCONFIG1_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x4 15. "PADCONFIG1_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x4 14. "PADCONFIG1_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x4 11.--13. "PADCONFIG1_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8. "PADCONFIG1_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x4 7. "PADCONFIG1_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x4 4.--5. "PADCONFIG1_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x4 0.--3. 1. "PADCONFIG1_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x8 "CFG0_PADCONFIG2_PROXY,Register to control pin configuration and muxing" bitfld.long 0x8 31. "PADCONFIG2_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x8 30. "PADCONFIG2_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x8 29. "PADCONFIG2_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x8 28. "PADCONFIG2_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x8 27. "PADCONFIG2_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x8 26. "PADCONFIG2_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x8 25. "PADCONFIG2_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x8 24. "PADCONFIG2_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x8 23. "PADCONFIG2_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x8 22. "PADCONFIG2_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x8 21. "PADCONFIG2_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x8 19.--20. "PADCONFIG2_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8 18. "PADCONFIG2_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x8 17. "PADCONFIG2_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x8 16. "PADCONFIG2_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x8 15. "PADCONFIG2_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x8 14. "PADCONFIG2_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x8 11.--13. "PADCONFIG2_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "PADCONFIG2_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x8 7. "PADCONFIG2_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x8 4.--5. "PADCONFIG2_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x8 0.--3. 1. "PADCONFIG2_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xC "CFG0_PADCONFIG3_PROXY,Register to control pin configuration and muxing" bitfld.long 0xC 31. "PADCONFIG3_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xC 30. "PADCONFIG3_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xC 29. "PADCONFIG3_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xC 28. "PADCONFIG3_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xC 27. "PADCONFIG3_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xC 26. "PADCONFIG3_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xC 25. "PADCONFIG3_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xC 24. "PADCONFIG3_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xC 23. "PADCONFIG3_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xC 22. "PADCONFIG3_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xC 21. "PADCONFIG3_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xC 19.--20. "PADCONFIG3_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC 18. "PADCONFIG3_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xC 17. "PADCONFIG3_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xC 16. "PADCONFIG3_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xC 15. "PADCONFIG3_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xC 14. "PADCONFIG3_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xC 11.--13. "PADCONFIG3_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "PADCONFIG3_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xC 7. "PADCONFIG3_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xC 4.--5. "PADCONFIG3_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xC 0.--3. 1. "PADCONFIG3_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x10 "CFG0_PADCONFIG4_PROXY,Register to control pin configuration and muxing" bitfld.long 0x10 31. "PADCONFIG4_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x10 30. "PADCONFIG4_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x10 29. "PADCONFIG4_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x10 28. "PADCONFIG4_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x10 27. "PADCONFIG4_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x10 26. "PADCONFIG4_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x10 25. "PADCONFIG4_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x10 24. "PADCONFIG4_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x10 23. "PADCONFIG4_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x10 22. "PADCONFIG4_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x10 21. "PADCONFIG4_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x10 19.--20. "PADCONFIG4_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x10 18. "PADCONFIG4_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x10 17. "PADCONFIG4_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x10 16. "PADCONFIG4_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x10 15. "PADCONFIG4_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x10 14. "PADCONFIG4_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x10 11.--13. "PADCONFIG4_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "PADCONFIG4_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x10 7. "PADCONFIG4_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x10 4.--5. "PADCONFIG4_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x10 0.--3. 1. "PADCONFIG4_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x14 "CFG0_PADCONFIG5_PROXY,Register to control pin configuration and muxing" bitfld.long 0x14 31. "PADCONFIG5_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x14 30. "PADCONFIG5_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x14 29. "PADCONFIG5_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x14 28. "PADCONFIG5_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x14 27. "PADCONFIG5_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x14 26. "PADCONFIG5_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x14 25. "PADCONFIG5_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x14 24. "PADCONFIG5_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x14 23. "PADCONFIG5_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x14 22. "PADCONFIG5_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x14 21. "PADCONFIG5_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x14 19.--20. "PADCONFIG5_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x14 18. "PADCONFIG5_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x14 17. "PADCONFIG5_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x14 16. "PADCONFIG5_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x14 15. "PADCONFIG5_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x14 14. "PADCONFIG5_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x14 11.--13. "PADCONFIG5_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "PADCONFIG5_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x14 7. "PADCONFIG5_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x14 4.--5. "PADCONFIG5_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x14 0.--3. 1. "PADCONFIG5_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x18 "CFG0_PADCONFIG6_PROXY,Register to control pin configuration and muxing" bitfld.long 0x18 31. "PADCONFIG6_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x18 30. "PADCONFIG6_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x18 29. "PADCONFIG6_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x18 28. "PADCONFIG6_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x18 27. "PADCONFIG6_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x18 26. "PADCONFIG6_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x18 25. "PADCONFIG6_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x18 24. "PADCONFIG6_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x18 23. "PADCONFIG6_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x18 22. "PADCONFIG6_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x18 21. "PADCONFIG6_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x18 19.--20. "PADCONFIG6_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x18 18. "PADCONFIG6_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x18 17. "PADCONFIG6_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x18 16. "PADCONFIG6_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x18 15. "PADCONFIG6_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x18 14. "PADCONFIG6_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x18 11.--13. "PADCONFIG6_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8. "PADCONFIG6_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x18 7. "PADCONFIG6_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x18 4.--5. "PADCONFIG6_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x18 0.--3. 1. "PADCONFIG6_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x1C "CFG0_PADCONFIG7_PROXY,Register to control pin configuration and muxing" bitfld.long 0x1C 31. "PADCONFIG7_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x1C 30. "PADCONFIG7_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x1C 29. "PADCONFIG7_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x1C 28. "PADCONFIG7_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x1C 27. "PADCONFIG7_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x1C 26. "PADCONFIG7_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x1C 25. "PADCONFIG7_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x1C 24. "PADCONFIG7_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x1C 23. "PADCONFIG7_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x1C 22. "PADCONFIG7_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x1C 21. "PADCONFIG7_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x1C 19.--20. "PADCONFIG7_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1C 18. "PADCONFIG7_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x1C 17. "PADCONFIG7_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x1C 16. "PADCONFIG7_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x1C 15. "PADCONFIG7_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x1C 14. "PADCONFIG7_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x1C 11.--13. "PADCONFIG7_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "PADCONFIG7_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x1C 7. "PADCONFIG7_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x1C 4.--5. "PADCONFIG7_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x1C 0.--3. 1. "PADCONFIG7_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x20 "CFG0_PADCONFIG8_PROXY,Register to control pin configuration and muxing" bitfld.long 0x20 31. "PADCONFIG8_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x20 30. "PADCONFIG8_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x20 29. "PADCONFIG8_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x20 28. "PADCONFIG8_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x20 27. "PADCONFIG8_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x20 26. "PADCONFIG8_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x20 25. "PADCONFIG8_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x20 24. "PADCONFIG8_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x20 23. "PADCONFIG8_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x20 22. "PADCONFIG8_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x20 21. "PADCONFIG8_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x20 19.--20. "PADCONFIG8_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x20 18. "PADCONFIG8_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x20 17. "PADCONFIG8_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x20 16. "PADCONFIG8_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x20 15. "PADCONFIG8_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x20 14. "PADCONFIG8_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x20 11.--13. "PADCONFIG8_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 8. "PADCONFIG8_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x20 7. "PADCONFIG8_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x20 4.--5. "PADCONFIG8_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x20 0.--3. 1. "PADCONFIG8_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x24 "CFG0_PADCONFIG9_PROXY,Register to control pin configuration and muxing" bitfld.long 0x24 31. "PADCONFIG9_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x24 30. "PADCONFIG9_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x24 29. "PADCONFIG9_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x24 28. "PADCONFIG9_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x24 27. "PADCONFIG9_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x24 26. "PADCONFIG9_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x24 25. "PADCONFIG9_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x24 24. "PADCONFIG9_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x24 23. "PADCONFIG9_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x24 22. "PADCONFIG9_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x24 21. "PADCONFIG9_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x24 19.--20. "PADCONFIG9_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x24 18. "PADCONFIG9_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x24 17. "PADCONFIG9_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x24 16. "PADCONFIG9_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x24 15. "PADCONFIG9_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x24 14. "PADCONFIG9_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x24 11.--13. "PADCONFIG9_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 8. "PADCONFIG9_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x24 7. "PADCONFIG9_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x24 4.--5. "PADCONFIG9_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x24 0.--3. 1. "PADCONFIG9_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x28 "CFG0_PADCONFIG10_PROXY,Register to control pin configuration and muxing" bitfld.long 0x28 31. "PADCONFIG10_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x28 30. "PADCONFIG10_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x28 29. "PADCONFIG10_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x28 28. "PADCONFIG10_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x28 27. "PADCONFIG10_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x28 26. "PADCONFIG10_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x28 25. "PADCONFIG10_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x28 24. "PADCONFIG10_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x28 23. "PADCONFIG10_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x28 22. "PADCONFIG10_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x28 21. "PADCONFIG10_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x28 19.--20. "PADCONFIG10_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x28 18. "PADCONFIG10_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x28 17. "PADCONFIG10_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x28 16. "PADCONFIG10_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x28 15. "PADCONFIG10_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x28 14. "PADCONFIG10_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x28 11.--13. "PADCONFIG10_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8. "PADCONFIG10_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x28 7. "PADCONFIG10_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x28 4.--5. "PADCONFIG10_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x28 0.--3. 1. "PADCONFIG10_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x2C "CFG0_PADCONFIG11_PROXY,Register to control pin configuration and muxing" bitfld.long 0x2C 31. "PADCONFIG11_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x2C 30. "PADCONFIG11_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x2C 29. "PADCONFIG11_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x2C 28. "PADCONFIG11_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x2C 27. "PADCONFIG11_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x2C 26. "PADCONFIG11_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x2C 25. "PADCONFIG11_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x2C 24. "PADCONFIG11_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x2C 23. "PADCONFIG11_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x2C 22. "PADCONFIG11_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x2C 21. "PADCONFIG11_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x2C 19.--20. "PADCONFIG11_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x2C 18. "PADCONFIG11_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x2C 17. "PADCONFIG11_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x2C 16. "PADCONFIG11_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x2C 15. "PADCONFIG11_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x2C 14. "PADCONFIG11_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x2C 11.--13. "PADCONFIG11_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 8. "PADCONFIG11_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x2C 7. "PADCONFIG11_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x2C 4.--5. "PADCONFIG11_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x2C 0.--3. 1. "PADCONFIG11_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x30 "CFG0_PADCONFIG12_PROXY,Register to control pin configuration and muxing" bitfld.long 0x30 31. "PADCONFIG12_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x30 30. "PADCONFIG12_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x30 29. "PADCONFIG12_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x30 28. "PADCONFIG12_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x30 27. "PADCONFIG12_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x30 26. "PADCONFIG12_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x30 25. "PADCONFIG12_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x30 24. "PADCONFIG12_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x30 23. "PADCONFIG12_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x30 22. "PADCONFIG12_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x30 21. "PADCONFIG12_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x30 19.--20. "PADCONFIG12_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x30 18. "PADCONFIG12_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x30 17. "PADCONFIG12_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x30 16. "PADCONFIG12_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x30 15. "PADCONFIG12_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x30 14. "PADCONFIG12_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x30 11.--13. "PADCONFIG12_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 8. "PADCONFIG12_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x30 7. "PADCONFIG12_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x30 4.--5. "PADCONFIG12_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x30 0.--3. 1. "PADCONFIG12_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x34 "CFG0_PADCONFIG13_PROXY,Register to control pin configuration and muxing" bitfld.long 0x34 31. "PADCONFIG13_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x34 30. "PADCONFIG13_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x34 29. "PADCONFIG13_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x34 28. "PADCONFIG13_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x34 27. "PADCONFIG13_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x34 26. "PADCONFIG13_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x34 25. "PADCONFIG13_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x34 24. "PADCONFIG13_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x34 23. "PADCONFIG13_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x34 22. "PADCONFIG13_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x34 21. "PADCONFIG13_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x34 19.--20. "PADCONFIG13_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x34 18. "PADCONFIG13_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x34 17. "PADCONFIG13_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x34 16. "PADCONFIG13_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x34 15. "PADCONFIG13_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x34 14. "PADCONFIG13_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x34 11.--13. "PADCONFIG13_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 8. "PADCONFIG13_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x34 7. "PADCONFIG13_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x34 4.--5. "PADCONFIG13_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x34 0.--3. 1. "PADCONFIG13_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x38 "CFG0_PADCONFIG14_PROXY,Register to control pin configuration and muxing" bitfld.long 0x38 31. "PADCONFIG14_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x38 30. "PADCONFIG14_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x38 29. "PADCONFIG14_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x38 28. "PADCONFIG14_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x38 27. "PADCONFIG14_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x38 26. "PADCONFIG14_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x38 25. "PADCONFIG14_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x38 24. "PADCONFIG14_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x38 23. "PADCONFIG14_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x38 22. "PADCONFIG14_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x38 21. "PADCONFIG14_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x38 19.--20. "PADCONFIG14_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x38 18. "PADCONFIG14_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x38 17. "PADCONFIG14_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x38 16. "PADCONFIG14_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x38 15. "PADCONFIG14_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x38 14. "PADCONFIG14_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x38 11.--13. "PADCONFIG14_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 8. "PADCONFIG14_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x38 7. "PADCONFIG14_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x38 4.--5. "PADCONFIG14_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x38 0.--3. 1. "PADCONFIG14_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x3C "CFG0_PADCONFIG15_PROXY,Register to control pin configuration and muxing" bitfld.long 0x3C 31. "PADCONFIG15_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x3C 30. "PADCONFIG15_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x3C 29. "PADCONFIG15_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x3C 28. "PADCONFIG15_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x3C 27. "PADCONFIG15_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x3C 26. "PADCONFIG15_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x3C 25. "PADCONFIG15_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x3C 24. "PADCONFIG15_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x3C 23. "PADCONFIG15_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x3C 22. "PADCONFIG15_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x3C 21. "PADCONFIG15_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x3C 19.--20. "PADCONFIG15_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x3C 18. "PADCONFIG15_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x3C 17. "PADCONFIG15_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x3C 16. "PADCONFIG15_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x3C 15. "PADCONFIG15_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x3C 14. "PADCONFIG15_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x3C 11.--13. "PADCONFIG15_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x3C 8. "PADCONFIG15_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x3C 7. "PADCONFIG15_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x3C 4.--5. "PADCONFIG15_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x3C 0.--3. 1. "PADCONFIG15_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x40 "CFG0_PADCONFIG16_PROXY,Register to control pin configuration and muxing" bitfld.long 0x40 31. "PADCONFIG16_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x40 30. "PADCONFIG16_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x40 29. "PADCONFIG16_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x40 28. "PADCONFIG16_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x40 27. "PADCONFIG16_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x40 26. "PADCONFIG16_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x40 25. "PADCONFIG16_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x40 24. "PADCONFIG16_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x40 23. "PADCONFIG16_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x40 22. "PADCONFIG16_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x40 21. "PADCONFIG16_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x40 19.--20. "PADCONFIG16_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x40 18. "PADCONFIG16_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x40 17. "PADCONFIG16_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x40 16. "PADCONFIG16_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x40 15. "PADCONFIG16_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x40 14. "PADCONFIG16_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x40 11.--13. "PADCONFIG16_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 8. "PADCONFIG16_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x40 7. "PADCONFIG16_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x40 4.--5. "PADCONFIG16_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x40 0.--3. 1. "PADCONFIG16_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x44 "CFG0_PADCONFIG17_PROXY,Register to control pin configuration and muxing" bitfld.long 0x44 31. "PADCONFIG17_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x44 30. "PADCONFIG17_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x44 29. "PADCONFIG17_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x44 28. "PADCONFIG17_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x44 27. "PADCONFIG17_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x44 26. "PADCONFIG17_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x44 25. "PADCONFIG17_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x44 24. "PADCONFIG17_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x44 23. "PADCONFIG17_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x44 22. "PADCONFIG17_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x44 21. "PADCONFIG17_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x44 19.--20. "PADCONFIG17_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x44 18. "PADCONFIG17_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x44 17. "PADCONFIG17_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x44 16. "PADCONFIG17_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x44 15. "PADCONFIG17_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x44 14. "PADCONFIG17_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x44 11.--13. "PADCONFIG17_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x44 8. "PADCONFIG17_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x44 7. "PADCONFIG17_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x44 4.--5. "PADCONFIG17_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x44 0.--3. 1. "PADCONFIG17_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x48 "CFG0_PADCONFIG18_PROXY,Register to control pin configuration and muxing" bitfld.long 0x48 31. "PADCONFIG18_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x48 30. "PADCONFIG18_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x48 29. "PADCONFIG18_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x48 28. "PADCONFIG18_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x48 27. "PADCONFIG18_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x48 26. "PADCONFIG18_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x48 25. "PADCONFIG18_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x48 24. "PADCONFIG18_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x48 23. "PADCONFIG18_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x48 22. "PADCONFIG18_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x48 21. "PADCONFIG18_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x48 19.--20. "PADCONFIG18_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x48 18. "PADCONFIG18_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x48 17. "PADCONFIG18_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x48 16. "PADCONFIG18_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x48 15. "PADCONFIG18_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x48 14. "PADCONFIG18_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x48 11.--13. "PADCONFIG18_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 8. "PADCONFIG18_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x48 7. "PADCONFIG18_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x48 4.--5. "PADCONFIG18_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x48 0.--3. 1. "PADCONFIG18_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x4C "CFG0_PADCONFIG19_PROXY,Register to control pin configuration and muxing" bitfld.long 0x4C 31. "PADCONFIG19_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x4C 30. "PADCONFIG19_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x4C 29. "PADCONFIG19_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x4C 28. "PADCONFIG19_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x4C 27. "PADCONFIG19_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x4C 26. "PADCONFIG19_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x4C 25. "PADCONFIG19_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x4C 24. "PADCONFIG19_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x4C 23. "PADCONFIG19_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x4C 22. "PADCONFIG19_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x4C 21. "PADCONFIG19_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x4C 19.--20. "PADCONFIG19_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4C 18. "PADCONFIG19_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x4C 17. "PADCONFIG19_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x4C 16. "PADCONFIG19_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x4C 15. "PADCONFIG19_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x4C 14. "PADCONFIG19_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x4C 11.--13. "PADCONFIG19_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4C 8. "PADCONFIG19_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x4C 7. "PADCONFIG19_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x4C 4.--5. "PADCONFIG19_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x4C 0.--3. 1. "PADCONFIG19_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x50 "CFG0_PADCONFIG20_PROXY,Register to control pin configuration and muxing" bitfld.long 0x50 31. "PADCONFIG20_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x50 30. "PADCONFIG20_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x50 29. "PADCONFIG20_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x50 28. "PADCONFIG20_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x50 27. "PADCONFIG20_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x50 26. "PADCONFIG20_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x50 25. "PADCONFIG20_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x50 24. "PADCONFIG20_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x50 23. "PADCONFIG20_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x50 22. "PADCONFIG20_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x50 21. "PADCONFIG20_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x50 19.--20. "PADCONFIG20_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x50 18. "PADCONFIG20_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x50 17. "PADCONFIG20_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x50 16. "PADCONFIG20_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x50 15. "PADCONFIG20_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x50 14. "PADCONFIG20_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x50 11.--13. "PADCONFIG20_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 8. "PADCONFIG20_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x50 7. "PADCONFIG20_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x50 4.--5. "PADCONFIG20_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x50 0.--3. 1. "PADCONFIG20_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x54 "CFG0_PADCONFIG21_PROXY,Register to control pin configuration and muxing" bitfld.long 0x54 31. "PADCONFIG21_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x54 30. "PADCONFIG21_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x54 29. "PADCONFIG21_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x54 28. "PADCONFIG21_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x54 27. "PADCONFIG21_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x54 26. "PADCONFIG21_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x54 25. "PADCONFIG21_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x54 24. "PADCONFIG21_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x54 23. "PADCONFIG21_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x54 22. "PADCONFIG21_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x54 21. "PADCONFIG21_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x54 19.--20. "PADCONFIG21_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x54 18. "PADCONFIG21_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x54 17. "PADCONFIG21_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x54 16. "PADCONFIG21_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x54 15. "PADCONFIG21_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x54 14. "PADCONFIG21_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x54 11.--13. "PADCONFIG21_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x54 8. "PADCONFIG21_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x54 7. "PADCONFIG21_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x54 4.--5. "PADCONFIG21_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x54 0.--3. 1. "PADCONFIG21_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x58 "CFG0_PADCONFIG22_PROXY,Register to control pin configuration and muxing" bitfld.long 0x58 31. "PADCONFIG22_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x58 30. "PADCONFIG22_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x58 29. "PADCONFIG22_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x58 28. "PADCONFIG22_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x58 27. "PADCONFIG22_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x58 26. "PADCONFIG22_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x58 25. "PADCONFIG22_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x58 24. "PADCONFIG22_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x58 23. "PADCONFIG22_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x58 22. "PADCONFIG22_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x58 21. "PADCONFIG22_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x58 19.--20. "PADCONFIG22_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x58 18. "PADCONFIG22_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x58 17. "PADCONFIG22_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x58 16. "PADCONFIG22_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x58 15. "PADCONFIG22_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x58 14. "PADCONFIG22_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x58 11.--13. "PADCONFIG22_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 8. "PADCONFIG22_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x58 7. "PADCONFIG22_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x58 4.--5. "PADCONFIG22_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x58 0.--3. 1. "PADCONFIG22_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x5C "CFG0_PADCONFIG23_PROXY,Register to control pin configuration and muxing" bitfld.long 0x5C 31. "PADCONFIG23_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x5C 30. "PADCONFIG23_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x5C 29. "PADCONFIG23_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x5C 28. "PADCONFIG23_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x5C 27. "PADCONFIG23_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x5C 26. "PADCONFIG23_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x5C 25. "PADCONFIG23_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x5C 24. "PADCONFIG23_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x5C 23. "PADCONFIG23_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x5C 22. "PADCONFIG23_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x5C 21. "PADCONFIG23_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x5C 19.--20. "PADCONFIG23_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x5C 18. "PADCONFIG23_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x5C 17. "PADCONFIG23_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x5C 16. "PADCONFIG23_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x5C 15. "PADCONFIG23_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x5C 14. "PADCONFIG23_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x5C 11.--13. "PADCONFIG23_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x5C 8. "PADCONFIG23_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x5C 7. "PADCONFIG23_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x5C 4.--5. "PADCONFIG23_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x5C 0.--3. 1. "PADCONFIG23_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x60 "CFG0_PADCONFIG24_PROXY,Register to control pin configuration and muxing" bitfld.long 0x60 31. "PADCONFIG24_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x60 30. "PADCONFIG24_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x60 29. "PADCONFIG24_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x60 28. "PADCONFIG24_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x60 27. "PADCONFIG24_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x60 26. "PADCONFIG24_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x60 25. "PADCONFIG24_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x60 24. "PADCONFIG24_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x60 23. "PADCONFIG24_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x60 22. "PADCONFIG24_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x60 21. "PADCONFIG24_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x60 19.--20. "PADCONFIG24_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x60 18. "PADCONFIG24_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x60 17. "PADCONFIG24_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x60 16. "PADCONFIG24_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x60 15. "PADCONFIG24_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x60 14. "PADCONFIG24_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x60 11.--13. "PADCONFIG24_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 8. "PADCONFIG24_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x60 7. "PADCONFIG24_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x60 4.--5. "PADCONFIG24_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x60 0.--3. 1. "PADCONFIG24_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x64 "CFG0_PADCONFIG25_PROXY,Register to control pin configuration and muxing" bitfld.long 0x64 31. "PADCONFIG25_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x64 30. "PADCONFIG25_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x64 29. "PADCONFIG25_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x64 28. "PADCONFIG25_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x64 27. "PADCONFIG25_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x64 26. "PADCONFIG25_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x64 25. "PADCONFIG25_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x64 24. "PADCONFIG25_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x64 23. "PADCONFIG25_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x64 22. "PADCONFIG25_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x64 21. "PADCONFIG25_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x64 19.--20. "PADCONFIG25_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x64 18. "PADCONFIG25_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x64 17. "PADCONFIG25_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x64 16. "PADCONFIG25_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x64 15. "PADCONFIG25_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x64 14. "PADCONFIG25_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x64 11.--13. "PADCONFIG25_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x64 8. "PADCONFIG25_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x64 7. "PADCONFIG25_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x64 4.--5. "PADCONFIG25_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x64 0.--3. 1. "PADCONFIG25_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x68 "CFG0_PADCONFIG26_PROXY,Register to control pin configuration and muxing" bitfld.long 0x68 31. "PADCONFIG26_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x68 30. "PADCONFIG26_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x68 29. "PADCONFIG26_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x68 28. "PADCONFIG26_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x68 27. "PADCONFIG26_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x68 26. "PADCONFIG26_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x68 25. "PADCONFIG26_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x68 24. "PADCONFIG26_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x68 23. "PADCONFIG26_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x68 22. "PADCONFIG26_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x68 21. "PADCONFIG26_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x68 19.--20. "PADCONFIG26_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x68 18. "PADCONFIG26_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x68 17. "PADCONFIG26_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x68 16. "PADCONFIG26_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x68 15. "PADCONFIG26_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x68 14. "PADCONFIG26_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x68 11.--13. "PADCONFIG26_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 8. "PADCONFIG26_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x68 7. "PADCONFIG26_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x68 4.--5. "PADCONFIG26_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x68 0.--3. 1. "PADCONFIG26_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x6C "CFG0_PADCONFIG27_PROXY,Register to control pin configuration and muxing" bitfld.long 0x6C 31. "PADCONFIG27_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x6C 30. "PADCONFIG27_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x6C 29. "PADCONFIG27_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x6C 28. "PADCONFIG27_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x6C 27. "PADCONFIG27_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x6C 26. "PADCONFIG27_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x6C 25. "PADCONFIG27_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x6C 24. "PADCONFIG27_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x6C 23. "PADCONFIG27_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x6C 22. "PADCONFIG27_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x6C 21. "PADCONFIG27_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x6C 19.--20. "PADCONFIG27_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x6C 18. "PADCONFIG27_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x6C 17. "PADCONFIG27_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x6C 16. "PADCONFIG27_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x6C 15. "PADCONFIG27_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x6C 14. "PADCONFIG27_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x6C 11.--13. "PADCONFIG27_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x6C 8. "PADCONFIG27_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x6C 7. "PADCONFIG27_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x6C 4.--5. "PADCONFIG27_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x6C 0.--3. 1. "PADCONFIG27_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x70 "CFG0_PADCONFIG28_PROXY,Register to control pin configuration and muxing" bitfld.long 0x70 31. "PADCONFIG28_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x70 30. "PADCONFIG28_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x70 29. "PADCONFIG28_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x70 28. "PADCONFIG28_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x70 27. "PADCONFIG28_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x70 26. "PADCONFIG28_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x70 25. "PADCONFIG28_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x70 24. "PADCONFIG28_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x70 23. "PADCONFIG28_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x70 22. "PADCONFIG28_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x70 21. "PADCONFIG28_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x70 19.--20. "PADCONFIG28_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x70 18. "PADCONFIG28_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x70 17. "PADCONFIG28_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x70 16. "PADCONFIG28_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x70 15. "PADCONFIG28_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x70 14. "PADCONFIG28_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x70 11.--13. "PADCONFIG28_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 8. "PADCONFIG28_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x70 7. "PADCONFIG28_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x70 4.--5. "PADCONFIG28_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x70 0.--3. 1. "PADCONFIG28_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x74 "CFG0_PADCONFIG29_PROXY,Register to control pin configuration and muxing" bitfld.long 0x74 31. "PADCONFIG29_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x74 30. "PADCONFIG29_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x74 29. "PADCONFIG29_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x74 28. "PADCONFIG29_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x74 27. "PADCONFIG29_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x74 26. "PADCONFIG29_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x74 25. "PADCONFIG29_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x74 24. "PADCONFIG29_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x74 23. "PADCONFIG29_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x74 22. "PADCONFIG29_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x74 21. "PADCONFIG29_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x74 19.--20. "PADCONFIG29_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x74 18. "PADCONFIG29_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x74 17. "PADCONFIG29_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x74 16. "PADCONFIG29_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x74 15. "PADCONFIG29_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x74 14. "PADCONFIG29_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x74 11.--13. "PADCONFIG29_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x74 8. "PADCONFIG29_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x74 7. "PADCONFIG29_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x74 4.--5. "PADCONFIG29_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x74 0.--3. 1. "PADCONFIG29_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x78 "CFG0_PADCONFIG30_PROXY,Register to control pin configuration and muxing" bitfld.long 0x78 31. "PADCONFIG30_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x78 30. "PADCONFIG30_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x78 29. "PADCONFIG30_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x78 28. "PADCONFIG30_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x78 27. "PADCONFIG30_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x78 26. "PADCONFIG30_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x78 25. "PADCONFIG30_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x78 24. "PADCONFIG30_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x78 23. "PADCONFIG30_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x78 22. "PADCONFIG30_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x78 21. "PADCONFIG30_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x78 19.--20. "PADCONFIG30_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x78 18. "PADCONFIG30_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x78 17. "PADCONFIG30_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x78 16. "PADCONFIG30_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x78 15. "PADCONFIG30_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x78 14. "PADCONFIG30_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x78 11.--13. "PADCONFIG30_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 8. "PADCONFIG30_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x78 7. "PADCONFIG30_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x78 4.--5. "PADCONFIG30_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x78 0.--3. 1. "PADCONFIG30_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x7C "CFG0_PADCONFIG31_PROXY,Register to control pin configuration and muxing" bitfld.long 0x7C 31. "PADCONFIG31_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x7C 30. "PADCONFIG31_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x7C 29. "PADCONFIG31_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x7C 28. "PADCONFIG31_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x7C 27. "PADCONFIG31_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x7C 26. "PADCONFIG31_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x7C 25. "PADCONFIG31_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x7C 24. "PADCONFIG31_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x7C 23. "PADCONFIG31_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x7C 22. "PADCONFIG31_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x7C 21. "PADCONFIG31_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x7C 19.--20. "PADCONFIG31_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x7C 18. "PADCONFIG31_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x7C 17. "PADCONFIG31_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x7C 16. "PADCONFIG31_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x7C 15. "PADCONFIG31_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x7C 14. "PADCONFIG31_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x7C 11.--13. "PADCONFIG31_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x7C 8. "PADCONFIG31_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x7C 7. "PADCONFIG31_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x7C 4.--5. "PADCONFIG31_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x7C 0.--3. 1. "PADCONFIG31_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x80 "CFG0_PADCONFIG32_PROXY,Register to control pin configuration and muxing" bitfld.long 0x80 31. "PADCONFIG32_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x80 30. "PADCONFIG32_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x80 29. "PADCONFIG32_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x80 28. "PADCONFIG32_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x80 27. "PADCONFIG32_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x80 26. "PADCONFIG32_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x80 25. "PADCONFIG32_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x80 24. "PADCONFIG32_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x80 23. "PADCONFIG32_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x80 22. "PADCONFIG32_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x80 21. "PADCONFIG32_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x80 19.--20. "PADCONFIG32_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x80 18. "PADCONFIG32_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x80 17. "PADCONFIG32_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x80 16. "PADCONFIG32_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x80 15. "PADCONFIG32_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x80 14. "PADCONFIG32_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x80 11.--13. "PADCONFIG32_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 8. "PADCONFIG32_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x80 7. "PADCONFIG32_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x80 4.--5. "PADCONFIG32_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x80 0.--3. 1. "PADCONFIG32_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x84 "CFG0_PADCONFIG33_PROXY,Register to control pin configuration and muxing" bitfld.long 0x84 31. "PADCONFIG33_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x84 30. "PADCONFIG33_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x84 29. "PADCONFIG33_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x84 28. "PADCONFIG33_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x84 27. "PADCONFIG33_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x84 26. "PADCONFIG33_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x84 25. "PADCONFIG33_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x84 24. "PADCONFIG33_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x84 23. "PADCONFIG33_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x84 22. "PADCONFIG33_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x84 21. "PADCONFIG33_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x84 19.--20. "PADCONFIG33_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x84 18. "PADCONFIG33_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x84 17. "PADCONFIG33_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x84 16. "PADCONFIG33_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x84 15. "PADCONFIG33_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x84 14. "PADCONFIG33_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x84 11.--13. "PADCONFIG33_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x84 8. "PADCONFIG33_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x84 7. "PADCONFIG33_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x84 4.--5. "PADCONFIG33_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x84 0.--3. 1. "PADCONFIG33_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x88 "CFG0_PADCONFIG34_PROXY,Register to control pin configuration and muxing" bitfld.long 0x88 31. "PADCONFIG34_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x88 30. "PADCONFIG34_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x88 29. "PADCONFIG34_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x88 28. "PADCONFIG34_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x88 27. "PADCONFIG34_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x88 26. "PADCONFIG34_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x88 25. "PADCONFIG34_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x88 24. "PADCONFIG34_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x88 23. "PADCONFIG34_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x88 22. "PADCONFIG34_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x88 21. "PADCONFIG34_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x88 19.--20. "PADCONFIG34_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x88 18. "PADCONFIG34_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x88 17. "PADCONFIG34_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x88 16. "PADCONFIG34_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x88 15. "PADCONFIG34_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x88 14. "PADCONFIG34_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x88 11.--13. "PADCONFIG34_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 8. "PADCONFIG34_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x88 7. "PADCONFIG34_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x88 4.--5. "PADCONFIG34_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x88 0.--3. 1. "PADCONFIG34_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x8C "CFG0_PADCONFIG35_PROXY,Register to control pin configuration and muxing" bitfld.long 0x8C 31. "PADCONFIG35_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x8C 30. "PADCONFIG35_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x8C 29. "PADCONFIG35_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x8C 28. "PADCONFIG35_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x8C 27. "PADCONFIG35_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x8C 26. "PADCONFIG35_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x8C 25. "PADCONFIG35_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x8C 24. "PADCONFIG35_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x8C 23. "PADCONFIG35_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x8C 22. "PADCONFIG35_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x8C 21. "PADCONFIG35_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x8C 19.--20. "PADCONFIG35_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8C 18. "PADCONFIG35_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x8C 17. "PADCONFIG35_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x8C 16. "PADCONFIG35_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x8C 15. "PADCONFIG35_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x8C 14. "PADCONFIG35_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x8C 11.--13. "PADCONFIG35_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8C 8. "PADCONFIG35_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x8C 7. "PADCONFIG35_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x8C 4.--5. "PADCONFIG35_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x8C 0.--3. 1. "PADCONFIG35_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x90 "CFG0_PADCONFIG36_PROXY,Register to control pin configuration and muxing" bitfld.long 0x90 31. "PADCONFIG36_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x90 30. "PADCONFIG36_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x90 29. "PADCONFIG36_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x90 28. "PADCONFIG36_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x90 27. "PADCONFIG36_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x90 26. "PADCONFIG36_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x90 25. "PADCONFIG36_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x90 24. "PADCONFIG36_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x90 23. "PADCONFIG36_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x90 22. "PADCONFIG36_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x90 21. "PADCONFIG36_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x90 19.--20. "PADCONFIG36_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x90 18. "PADCONFIG36_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x90 17. "PADCONFIG36_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x90 16. "PADCONFIG36_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x90 15. "PADCONFIG36_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x90 14. "PADCONFIG36_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x90 11.--13. "PADCONFIG36_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 8. "PADCONFIG36_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x90 7. "PADCONFIG36_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x90 4.--5. "PADCONFIG36_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x90 0.--3. 1. "PADCONFIG36_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x94 "CFG0_PADCONFIG37_PROXY,Register to control pin configuration and muxing" bitfld.long 0x94 31. "PADCONFIG37_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x94 30. "PADCONFIG37_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x94 29. "PADCONFIG37_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x94 28. "PADCONFIG37_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x94 27. "PADCONFIG37_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x94 26. "PADCONFIG37_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x94 25. "PADCONFIG37_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x94 24. "PADCONFIG37_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x94 23. "PADCONFIG37_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x94 22. "PADCONFIG37_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x94 21. "PADCONFIG37_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x94 19.--20. "PADCONFIG37_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x94 18. "PADCONFIG37_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x94 17. "PADCONFIG37_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x94 16. "PADCONFIG37_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x94 15. "PADCONFIG37_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x94 14. "PADCONFIG37_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x94 11.--13. "PADCONFIG37_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x94 8. "PADCONFIG37_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x94 7. "PADCONFIG37_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x94 4.--5. "PADCONFIG37_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x94 0.--3. 1. "PADCONFIG37_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x98 "CFG0_PADCONFIG38_PROXY,Register to control pin configuration and muxing" bitfld.long 0x98 31. "PADCONFIG38_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x98 30. "PADCONFIG38_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x98 29. "PADCONFIG38_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x98 28. "PADCONFIG38_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x98 27. "PADCONFIG38_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x98 26. "PADCONFIG38_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x98 25. "PADCONFIG38_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x98 24. "PADCONFIG38_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x98 23. "PADCONFIG38_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x98 22. "PADCONFIG38_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x98 21. "PADCONFIG38_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x98 19.--20. "PADCONFIG38_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x98 18. "PADCONFIG38_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x98 17. "PADCONFIG38_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x98 16. "PADCONFIG38_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x98 15. "PADCONFIG38_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x98 14. "PADCONFIG38_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x98 11.--13. "PADCONFIG38_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 8. "PADCONFIG38_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x98 7. "PADCONFIG38_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x98 4.--5. "PADCONFIG38_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x98 0.--3. 1. "PADCONFIG38_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x9C "CFG0_PADCONFIG39_PROXY,Register to control pin configuration and muxing" bitfld.long 0x9C 31. "PADCONFIG39_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x9C 30. "PADCONFIG39_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x9C 29. "PADCONFIG39_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x9C 28. "PADCONFIG39_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x9C 27. "PADCONFIG39_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x9C 26. "PADCONFIG39_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x9C 25. "PADCONFIG39_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x9C 24. "PADCONFIG39_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x9C 23. "PADCONFIG39_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x9C 22. "PADCONFIG39_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x9C 21. "PADCONFIG39_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x9C 19.--20. "PADCONFIG39_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x9C 18. "PADCONFIG39_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x9C 17. "PADCONFIG39_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x9C 16. "PADCONFIG39_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x9C 15. "PADCONFIG39_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x9C 14. "PADCONFIG39_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x9C 11.--13. "PADCONFIG39_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x9C 8. "PADCONFIG39_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x9C 7. "PADCONFIG39_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x9C 4.--5. "PADCONFIG39_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x9C 0.--3. 1. "PADCONFIG39_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xA0 "CFG0_PADCONFIG40_PROXY,Register to control pin configuration and muxing" bitfld.long 0xA0 31. "PADCONFIG40_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xA0 30. "PADCONFIG40_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xA0 29. "PADCONFIG40_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xA0 28. "PADCONFIG40_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xA0 27. "PADCONFIG40_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xA0 26. "PADCONFIG40_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xA0 25. "PADCONFIG40_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xA0 24. "PADCONFIG40_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xA0 23. "PADCONFIG40_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xA0 22. "PADCONFIG40_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xA0 21. "PADCONFIG40_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xA0 19.--20. "PADCONFIG40_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xA0 18. "PADCONFIG40_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xA0 17. "PADCONFIG40_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xA0 16. "PADCONFIG40_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xA0 15. "PADCONFIG40_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xA0 14. "PADCONFIG40_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xA0 11.--13. "PADCONFIG40_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 8. "PADCONFIG40_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xA0 7. "PADCONFIG40_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xA0 4.--5. "PADCONFIG40_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xA0 0.--3. 1. "PADCONFIG40_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xA4 "CFG0_PADCONFIG41_PROXY,Register to control pin configuration and muxing" bitfld.long 0xA4 31. "PADCONFIG41_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xA4 30. "PADCONFIG41_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xA4 29. "PADCONFIG41_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xA4 28. "PADCONFIG41_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xA4 27. "PADCONFIG41_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xA4 26. "PADCONFIG41_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xA4 25. "PADCONFIG41_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xA4 24. "PADCONFIG41_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xA4 23. "PADCONFIG41_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xA4 22. "PADCONFIG41_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xA4 21. "PADCONFIG41_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xA4 19.--20. "PADCONFIG41_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xA4 18. "PADCONFIG41_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xA4 17. "PADCONFIG41_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xA4 16. "PADCONFIG41_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xA4 15. "PADCONFIG41_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xA4 14. "PADCONFIG41_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xA4 11.--13. "PADCONFIG41_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA4 8. "PADCONFIG41_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xA4 7. "PADCONFIG41_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xA4 4.--5. "PADCONFIG41_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xA4 0.--3. 1. "PADCONFIG41_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xA8 "CFG0_PADCONFIG42_PROXY,Register to control pin configuration and muxing" bitfld.long 0xA8 31. "PADCONFIG42_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xA8 30. "PADCONFIG42_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xA8 29. "PADCONFIG42_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xA8 28. "PADCONFIG42_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xA8 27. "PADCONFIG42_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xA8 26. "PADCONFIG42_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xA8 25. "PADCONFIG42_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xA8 24. "PADCONFIG42_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xA8 23. "PADCONFIG42_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xA8 22. "PADCONFIG42_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xA8 21. "PADCONFIG42_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xA8 19.--20. "PADCONFIG42_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xA8 18. "PADCONFIG42_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xA8 17. "PADCONFIG42_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xA8 16. "PADCONFIG42_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xA8 15. "PADCONFIG42_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xA8 14. "PADCONFIG42_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xA8 11.--13. "PADCONFIG42_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 8. "PADCONFIG42_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xA8 7. "PADCONFIG42_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xA8 4.--5. "PADCONFIG42_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xA8 0.--3. 1. "PADCONFIG42_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xAC "CFG0_PADCONFIG43_PROXY,Register to control pin configuration and muxing" bitfld.long 0xAC 31. "PADCONFIG43_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xAC 30. "PADCONFIG43_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xAC 29. "PADCONFIG43_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xAC 28. "PADCONFIG43_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xAC 27. "PADCONFIG43_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xAC 26. "PADCONFIG43_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xAC 25. "PADCONFIG43_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xAC 24. "PADCONFIG43_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xAC 23. "PADCONFIG43_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xAC 22. "PADCONFIG43_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xAC 21. "PADCONFIG43_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xAC 19.--20. "PADCONFIG43_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xAC 18. "PADCONFIG43_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xAC 17. "PADCONFIG43_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xAC 16. "PADCONFIG43_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xAC 15. "PADCONFIG43_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xAC 14. "PADCONFIG43_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xAC 11.--13. "PADCONFIG43_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xAC 8. "PADCONFIG43_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xAC 7. "PADCONFIG43_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xAC 4.--5. "PADCONFIG43_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xAC 0.--3. 1. "PADCONFIG43_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xB0 "CFG0_PADCONFIG44_PROXY,Register to control pin configuration and muxing" bitfld.long 0xB0 31. "PADCONFIG44_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xB0 30. "PADCONFIG44_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xB0 29. "PADCONFIG44_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xB0 28. "PADCONFIG44_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xB0 27. "PADCONFIG44_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xB0 26. "PADCONFIG44_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xB0 25. "PADCONFIG44_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xB0 24. "PADCONFIG44_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xB0 23. "PADCONFIG44_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xB0 22. "PADCONFIG44_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xB0 21. "PADCONFIG44_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xB0 19.--20. "PADCONFIG44_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB0 18. "PADCONFIG44_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xB0 17. "PADCONFIG44_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xB0 16. "PADCONFIG44_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xB0 15. "PADCONFIG44_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xB0 14. "PADCONFIG44_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xB0 11.--13. "PADCONFIG44_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 8. "PADCONFIG44_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xB0 7. "PADCONFIG44_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xB0 4.--5. "PADCONFIG44_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xB0 0.--3. 1. "PADCONFIG44_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xB4 "CFG0_PADCONFIG45_PROXY,Register to control pin configuration and muxing" bitfld.long 0xB4 31. "PADCONFIG45_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xB4 30. "PADCONFIG45_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xB4 29. "PADCONFIG45_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xB4 28. "PADCONFIG45_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xB4 27. "PADCONFIG45_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xB4 26. "PADCONFIG45_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xB4 25. "PADCONFIG45_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xB4 24. "PADCONFIG45_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xB4 23. "PADCONFIG45_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xB4 22. "PADCONFIG45_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xB4 21. "PADCONFIG45_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xB4 19.--20. "PADCONFIG45_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB4 18. "PADCONFIG45_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xB4 17. "PADCONFIG45_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xB4 16. "PADCONFIG45_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xB4 15. "PADCONFIG45_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xB4 14. "PADCONFIG45_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xB4 11.--13. "PADCONFIG45_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB4 8. "PADCONFIG45_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xB4 7. "PADCONFIG45_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xB4 4.--5. "PADCONFIG45_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xB4 0.--3. 1. "PADCONFIG45_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xB8 "CFG0_PADCONFIG46_PROXY,Register to control pin configuration and muxing" bitfld.long 0xB8 31. "PADCONFIG46_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xB8 30. "PADCONFIG46_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xB8 29. "PADCONFIG46_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xB8 28. "PADCONFIG46_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xB8 27. "PADCONFIG46_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xB8 26. "PADCONFIG46_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xB8 25. "PADCONFIG46_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xB8 24. "PADCONFIG46_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xB8 23. "PADCONFIG46_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xB8 22. "PADCONFIG46_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xB8 21. "PADCONFIG46_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xB8 19.--20. "PADCONFIG46_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB8 18. "PADCONFIG46_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xB8 17. "PADCONFIG46_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xB8 16. "PADCONFIG46_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xB8 15. "PADCONFIG46_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xB8 14. "PADCONFIG46_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xB8 11.--13. "PADCONFIG46_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 8. "PADCONFIG46_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xB8 7. "PADCONFIG46_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xB8 4.--5. "PADCONFIG46_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xB8 0.--3. 1. "PADCONFIG46_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xBC "CFG0_PADCONFIG47_PROXY,Register to control pin configuration and muxing" bitfld.long 0xBC 31. "PADCONFIG47_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xBC 30. "PADCONFIG47_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xBC 29. "PADCONFIG47_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xBC 28. "PADCONFIG47_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xBC 27. "PADCONFIG47_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xBC 26. "PADCONFIG47_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xBC 25. "PADCONFIG47_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xBC 24. "PADCONFIG47_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xBC 23. "PADCONFIG47_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xBC 22. "PADCONFIG47_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xBC 21. "PADCONFIG47_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xBC 19.--20. "PADCONFIG47_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xBC 18. "PADCONFIG47_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xBC 17. "PADCONFIG47_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xBC 16. "PADCONFIG47_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xBC 15. "PADCONFIG47_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xBC 14. "PADCONFIG47_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xBC 11.--13. "PADCONFIG47_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xBC 8. "PADCONFIG47_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xBC 7. "PADCONFIG47_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xBC 4.--5. "PADCONFIG47_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xBC 0.--3. 1. "PADCONFIG47_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xC0 "CFG0_PADCONFIG48_PROXY,Register to control pin configuration and muxing" bitfld.long 0xC0 31. "PADCONFIG48_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xC0 30. "PADCONFIG48_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xC0 29. "PADCONFIG48_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xC0 28. "PADCONFIG48_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xC0 27. "PADCONFIG48_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xC0 26. "PADCONFIG48_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xC0 25. "PADCONFIG48_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xC0 24. "PADCONFIG48_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xC0 23. "PADCONFIG48_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xC0 22. "PADCONFIG48_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xC0 21. "PADCONFIG48_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xC0 19.--20. "PADCONFIG48_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC0 18. "PADCONFIG48_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xC0 17. "PADCONFIG48_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xC0 16. "PADCONFIG48_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xC0 15. "PADCONFIG48_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xC0 14. "PADCONFIG48_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xC0 11.--13. "PADCONFIG48_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 8. "PADCONFIG48_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xC0 7. "PADCONFIG48_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xC0 4.--5. "PADCONFIG48_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xC0 0.--3. 1. "PADCONFIG48_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xC4 "CFG0_PADCONFIG49_PROXY,Register to control pin configuration and muxing" bitfld.long 0xC4 31. "PADCONFIG49_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xC4 30. "PADCONFIG49_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xC4 29. "PADCONFIG49_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xC4 28. "PADCONFIG49_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xC4 27. "PADCONFIG49_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xC4 26. "PADCONFIG49_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xC4 25. "PADCONFIG49_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xC4 24. "PADCONFIG49_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xC4 23. "PADCONFIG49_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xC4 22. "PADCONFIG49_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xC4 21. "PADCONFIG49_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xC4 19.--20. "PADCONFIG49_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC4 18. "PADCONFIG49_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xC4 17. "PADCONFIG49_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xC4 16. "PADCONFIG49_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xC4 15. "PADCONFIG49_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xC4 14. "PADCONFIG49_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xC4 11.--13. "PADCONFIG49_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC4 8. "PADCONFIG49_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xC4 7. "PADCONFIG49_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xC4 4.--5. "PADCONFIG49_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xC4 0.--3. 1. "PADCONFIG49_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xC8 "CFG0_PADCONFIG50_PROXY,Register to control pin configuration and muxing" bitfld.long 0xC8 31. "PADCONFIG50_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xC8 30. "PADCONFIG50_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xC8 29. "PADCONFIG50_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xC8 28. "PADCONFIG50_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xC8 27. "PADCONFIG50_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xC8 26. "PADCONFIG50_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xC8 25. "PADCONFIG50_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xC8 24. "PADCONFIG50_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xC8 23. "PADCONFIG50_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xC8 22. "PADCONFIG50_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xC8 21. "PADCONFIG50_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xC8 19.--20. "PADCONFIG50_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC8 18. "PADCONFIG50_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xC8 17. "PADCONFIG50_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xC8 16. "PADCONFIG50_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xC8 15. "PADCONFIG50_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xC8 14. "PADCONFIG50_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xC8 11.--13. "PADCONFIG50_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 8. "PADCONFIG50_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xC8 7. "PADCONFIG50_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xC8 4.--5. "PADCONFIG50_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xC8 0.--3. 1. "PADCONFIG50_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xCC "CFG0_PADCONFIG51_PROXY,Register to control pin configuration and muxing" bitfld.long 0xCC 31. "PADCONFIG51_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xCC 30. "PADCONFIG51_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xCC 29. "PADCONFIG51_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xCC 28. "PADCONFIG51_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xCC 27. "PADCONFIG51_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xCC 26. "PADCONFIG51_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xCC 25. "PADCONFIG51_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xCC 24. "PADCONFIG51_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xCC 23. "PADCONFIG51_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xCC 22. "PADCONFIG51_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xCC 21. "PADCONFIG51_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xCC 19.--20. "PADCONFIG51_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xCC 18. "PADCONFIG51_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xCC 17. "PADCONFIG51_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xCC 16. "PADCONFIG51_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xCC 15. "PADCONFIG51_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xCC 14. "PADCONFIG51_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xCC 11.--13. "PADCONFIG51_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xCC 8. "PADCONFIG51_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xCC 7. "PADCONFIG51_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xCC 4.--5. "PADCONFIG51_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xCC 0.--3. 1. "PADCONFIG51_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xD0 "CFG0_PADCONFIG52_PROXY,Register to control pin configuration and muxing" bitfld.long 0xD0 31. "PADCONFIG52_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xD0 30. "PADCONFIG52_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xD0 29. "PADCONFIG52_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xD0 28. "PADCONFIG52_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xD0 27. "PADCONFIG52_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xD0 26. "PADCONFIG52_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xD0 25. "PADCONFIG52_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xD0 24. "PADCONFIG52_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xD0 23. "PADCONFIG52_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xD0 22. "PADCONFIG52_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xD0 21. "PADCONFIG52_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xD0 19.--20. "PADCONFIG52_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xD0 18. "PADCONFIG52_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xD0 17. "PADCONFIG52_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xD0 16. "PADCONFIG52_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xD0 15. "PADCONFIG52_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xD0 14. "PADCONFIG52_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xD0 11.--13. "PADCONFIG52_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 8. "PADCONFIG52_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xD0 7. "PADCONFIG52_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xD0 4.--5. "PADCONFIG52_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xD0 0.--3. 1. "PADCONFIG52_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xD4 "CFG0_PADCONFIG53_PROXY,Register to control pin configuration and muxing" bitfld.long 0xD4 31. "PADCONFIG53_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xD4 30. "PADCONFIG53_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xD4 29. "PADCONFIG53_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xD4 28. "PADCONFIG53_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xD4 27. "PADCONFIG53_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xD4 26. "PADCONFIG53_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xD4 25. "PADCONFIG53_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xD4 24. "PADCONFIG53_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xD4 23. "PADCONFIG53_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xD4 22. "PADCONFIG53_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xD4 21. "PADCONFIG53_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xD4 19.--20. "PADCONFIG53_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xD4 18. "PADCONFIG53_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xD4 17. "PADCONFIG53_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xD4 16. "PADCONFIG53_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xD4 15. "PADCONFIG53_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xD4 14. "PADCONFIG53_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xD4 11.--13. "PADCONFIG53_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD4 8. "PADCONFIG53_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xD4 7. "PADCONFIG53_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xD4 4.--5. "PADCONFIG53_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xD4 0.--3. 1. "PADCONFIG53_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xD8 "CFG0_PADCONFIG54_PROXY,Register to control pin configuration and muxing" bitfld.long 0xD8 31. "PADCONFIG54_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xD8 30. "PADCONFIG54_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xD8 29. "PADCONFIG54_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xD8 28. "PADCONFIG54_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xD8 27. "PADCONFIG54_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xD8 26. "PADCONFIG54_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xD8 25. "PADCONFIG54_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xD8 24. "PADCONFIG54_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xD8 23. "PADCONFIG54_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xD8 22. "PADCONFIG54_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xD8 21. "PADCONFIG54_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xD8 19.--20. "PADCONFIG54_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xD8 18. "PADCONFIG54_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xD8 17. "PADCONFIG54_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xD8 16. "PADCONFIG54_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xD8 15. "PADCONFIG54_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xD8 14. "PADCONFIG54_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xD8 11.--13. "PADCONFIG54_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 8. "PADCONFIG54_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xD8 7. "PADCONFIG54_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xD8 4.--5. "PADCONFIG54_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xD8 0.--3. 1. "PADCONFIG54_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xDC "CFG0_PADCONFIG55_PROXY,Register to control pin configuration and muxing" bitfld.long 0xDC 31. "PADCONFIG55_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xDC 30. "PADCONFIG55_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xDC 29. "PADCONFIG55_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xDC 28. "PADCONFIG55_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xDC 27. "PADCONFIG55_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xDC 26. "PADCONFIG55_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xDC 25. "PADCONFIG55_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xDC 24. "PADCONFIG55_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xDC 23. "PADCONFIG55_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xDC 22. "PADCONFIG55_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xDC 21. "PADCONFIG55_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xDC 19.--20. "PADCONFIG55_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xDC 18. "PADCONFIG55_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xDC 17. "PADCONFIG55_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xDC 16. "PADCONFIG55_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xDC 15. "PADCONFIG55_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xDC 14. "PADCONFIG55_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xDC 11.--13. "PADCONFIG55_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xDC 8. "PADCONFIG55_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xDC 7. "PADCONFIG55_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xDC 4.--5. "PADCONFIG55_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xDC 0.--3. 1. "PADCONFIG55_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xE0 "CFG0_PADCONFIG56_PROXY,Register to control pin configuration and muxing" bitfld.long 0xE0 31. "PADCONFIG56_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xE0 30. "PADCONFIG56_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xE0 29. "PADCONFIG56_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xE0 26. "PADCONFIG56_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xE0 25. "PADCONFIG56_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xE0 24. "PADCONFIG56_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xE0 23. "PADCONFIG56_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xE0 22. "PADCONFIG56_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xE0 21. "PADCONFIG56_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xE0 18. "PADCONFIG56_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xE0 15. "PADCONFIG56_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xE0 14. "PADCONFIG56_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xE0 11.--13. "PADCONFIG56_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 8. "PADCONFIG56_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xE0 7. "PADCONFIG56_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xE0 4.--5. "PADCONFIG56_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xE0 0.--3. 1. "PADCONFIG56_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xE4 "CFG0_PADCONFIG57_PROXY,Register to control pin configuration and muxing" bitfld.long 0xE4 31. "PADCONFIG57_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xE4 30. "PADCONFIG57_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xE4 29. "PADCONFIG57_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xE4 26. "PADCONFIG57_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xE4 25. "PADCONFIG57_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xE4 24. "PADCONFIG57_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xE4 23. "PADCONFIG57_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xE4 22. "PADCONFIG57_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xE4 21. "PADCONFIG57_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xE4 18. "PADCONFIG57_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xE4 15. "PADCONFIG57_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xE4 14. "PADCONFIG57_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xE4 11.--13. "PADCONFIG57_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE4 8. "PADCONFIG57_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xE4 7. "PADCONFIG57_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xE4 4.--5. "PADCONFIG57_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xE4 0.--3. 1. "PADCONFIG57_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xE8 "CFG0_PADCONFIG58_PROXY,Register to control pin configuration and muxing" bitfld.long 0xE8 31. "PADCONFIG58_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xE8 30. "PADCONFIG58_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xE8 29. "PADCONFIG58_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xE8 28. "PADCONFIG58_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xE8 27. "PADCONFIG58_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xE8 26. "PADCONFIG58_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xE8 25. "PADCONFIG58_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xE8 24. "PADCONFIG58_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xE8 23. "PADCONFIG58_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xE8 22. "PADCONFIG58_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xE8 21. "PADCONFIG58_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xE8 19.--20. "PADCONFIG58_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xE8 18. "PADCONFIG58_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xE8 17. "PADCONFIG58_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xE8 16. "PADCONFIG58_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xE8 15. "PADCONFIG58_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xE8 14. "PADCONFIG58_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xE8 11.--13. "PADCONFIG58_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 8. "PADCONFIG58_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xE8 7. "PADCONFIG58_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xE8 4.--5. "PADCONFIG58_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xE8 0.--3. 1. "PADCONFIG58_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xEC "CFG0_PADCONFIG59_PROXY,Register to control pin configuration and muxing" bitfld.long 0xEC 31. "PADCONFIG59_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xEC 30. "PADCONFIG59_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xEC 29. "PADCONFIG59_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xEC 28. "PADCONFIG59_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xEC 27. "PADCONFIG59_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xEC 26. "PADCONFIG59_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xEC 25. "PADCONFIG59_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xEC 24. "PADCONFIG59_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xEC 23. "PADCONFIG59_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xEC 22. "PADCONFIG59_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xEC 21. "PADCONFIG59_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xEC 19.--20. "PADCONFIG59_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xEC 18. "PADCONFIG59_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xEC 17. "PADCONFIG59_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xEC 16. "PADCONFIG59_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xEC 15. "PADCONFIG59_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xEC 14. "PADCONFIG59_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xEC 11.--13. "PADCONFIG59_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xEC 8. "PADCONFIG59_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xEC 7. "PADCONFIG59_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xEC 4.--5. "PADCONFIG59_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xEC 0.--3. 1. "PADCONFIG59_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xF0 "CFG0_PADCONFIG60_PROXY,Register to control pin configuration and muxing" bitfld.long 0xF0 31. "PADCONFIG60_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xF0 30. "PADCONFIG60_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xF0 29. "PADCONFIG60_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xF0 28. "PADCONFIG60_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xF0 27. "PADCONFIG60_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xF0 26. "PADCONFIG60_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xF0 25. "PADCONFIG60_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xF0 24. "PADCONFIG60_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xF0 23. "PADCONFIG60_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xF0 22. "PADCONFIG60_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xF0 21. "PADCONFIG60_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xF0 18. "PADCONFIG60_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xF0 17. "PADCONFIG60_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xF0 16. "PADCONFIG60_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xF0 15. "PADCONFIG60_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xF0 14. "PADCONFIG60_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xF0 11.--13. "PADCONFIG60_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 8. "PADCONFIG60_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xF0 7. "PADCONFIG60_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xF0 4.--5. "PADCONFIG60_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xF0 0.--3. 1. "PADCONFIG60_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xF4 "CFG0_PADCONFIG61_PROXY,Register to control pin configuration and muxing" bitfld.long 0xF4 31. "PADCONFIG61_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xF4 30. "PADCONFIG61_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xF4 29. "PADCONFIG61_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xF4 28. "PADCONFIG61_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xF4 27. "PADCONFIG61_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xF4 26. "PADCONFIG61_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xF4 25. "PADCONFIG61_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xF4 24. "PADCONFIG61_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xF4 23. "PADCONFIG61_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xF4 22. "PADCONFIG61_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xF4 21. "PADCONFIG61_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xF4 18. "PADCONFIG61_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xF4 17. "PADCONFIG61_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xF4 16. "PADCONFIG61_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xF4 15. "PADCONFIG61_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xF4 14. "PADCONFIG61_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xF4 11.--13. "PADCONFIG61_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF4 8. "PADCONFIG61_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xF4 7. "PADCONFIG61_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xF4 4.--5. "PADCONFIG61_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xF4 0.--3. 1. "PADCONFIG61_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xF8 "CFG0_PADCONFIG62_PROXY,Register to control pin configuration and muxing" bitfld.long 0xF8 31. "PADCONFIG62_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xF8 30. "PADCONFIG62_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xF8 29. "PADCONFIG62_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xF8 28. "PADCONFIG62_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xF8 27. "PADCONFIG62_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xF8 26. "PADCONFIG62_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xF8 25. "PADCONFIG62_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xF8 24. "PADCONFIG62_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xF8 23. "PADCONFIG62_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xF8 22. "PADCONFIG62_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xF8 21. "PADCONFIG62_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xF8 18. "PADCONFIG62_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xF8 17. "PADCONFIG62_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xF8 16. "PADCONFIG62_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xF8 15. "PADCONFIG62_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xF8 14. "PADCONFIG62_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xF8 11.--13. "PADCONFIG62_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 8. "PADCONFIG62_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xF8 7. "PADCONFIG62_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xF8 4.--5. "PADCONFIG62_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xF8 0.--3. 1. "PADCONFIG62_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0xFC "CFG0_PADCONFIG63_PROXY,Register to control pin configuration and muxing" bitfld.long 0xFC 31. "PADCONFIG63_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xFC 30. "PADCONFIG63_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xFC 29. "PADCONFIG63_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xFC 28. "PADCONFIG63_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xFC 27. "PADCONFIG63_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xFC 26. "PADCONFIG63_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xFC 25. "PADCONFIG63_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xFC 24. "PADCONFIG63_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0xFC 23. "PADCONFIG63_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0xFC 22. "PADCONFIG63_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0xFC 21. "PADCONFIG63_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0xFC 18. "PADCONFIG63_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0xFC 17. "PADCONFIG63_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0xFC 16. "PADCONFIG63_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0xFC 15. "PADCONFIG63_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0xFC 14. "PADCONFIG63_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xFC 11.--13. "PADCONFIG63_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xFC 8. "PADCONFIG63_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xFC 7. "PADCONFIG63_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xFC 4.--5. "PADCONFIG63_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0xFC 0.--3. 1. "PADCONFIG63_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x100 "CFG0_PADCONFIG64_PROXY,Register to control pin configuration and muxing" bitfld.long 0x100 31. "PADCONFIG64_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x100 30. "PADCONFIG64_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x100 29. "PADCONFIG64_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x100 28. "PADCONFIG64_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x100 27. "PADCONFIG64_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x100 26. "PADCONFIG64_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x100 25. "PADCONFIG64_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x100 24. "PADCONFIG64_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x100 23. "PADCONFIG64_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x100 22. "PADCONFIG64_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x100 21. "PADCONFIG64_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x100 18. "PADCONFIG64_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x100 17. "PADCONFIG64_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x100 16. "PADCONFIG64_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x100 15. "PADCONFIG64_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x100 14. "PADCONFIG64_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x100 11.--13. "PADCONFIG64_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x100 8. "PADCONFIG64_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x100 7. "PADCONFIG64_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x100 4.--5. "PADCONFIG64_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x100 0.--3. 1. "PADCONFIG64_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x104 "CFG0_PADCONFIG65_PROXY,Register to control pin configuration and muxing" bitfld.long 0x104 31. "PADCONFIG65_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x104 30. "PADCONFIG65_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x104 29. "PADCONFIG65_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x104 28. "PADCONFIG65_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x104 27. "PADCONFIG65_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x104 26. "PADCONFIG65_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x104 25. "PADCONFIG65_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x104 24. "PADCONFIG65_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x104 23. "PADCONFIG65_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x104 22. "PADCONFIG65_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x104 21. "PADCONFIG65_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x104 18. "PADCONFIG65_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x104 17. "PADCONFIG65_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x104 16. "PADCONFIG65_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x104 15. "PADCONFIG65_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x104 14. "PADCONFIG65_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x104 11.--13. "PADCONFIG65_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x104 8. "PADCONFIG65_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x104 7. "PADCONFIG65_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x104 4.--5. "PADCONFIG65_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x104 0.--3. 1. "PADCONFIG65_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x108 "CFG0_PADCONFIG66_PROXY,Register to control pin configuration and muxing" bitfld.long 0x108 31. "PADCONFIG66_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x108 30. "PADCONFIG66_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x108 29. "PADCONFIG66_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x108 28. "PADCONFIG66_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x108 27. "PADCONFIG66_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x108 26. "PADCONFIG66_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x108 25. "PADCONFIG66_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x108 24. "PADCONFIG66_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x108 23. "PADCONFIG66_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x108 22. "PADCONFIG66_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x108 21. "PADCONFIG66_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x108 18. "PADCONFIG66_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x108 17. "PADCONFIG66_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x108 16. "PADCONFIG66_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x108 15. "PADCONFIG66_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x108 14. "PADCONFIG66_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x108 11.--13. "PADCONFIG66_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x108 8. "PADCONFIG66_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x108 7. "PADCONFIG66_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x108 4.--5. "PADCONFIG66_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x108 0.--3. 1. "PADCONFIG66_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x10C "CFG0_PADCONFIG67_PROXY,Register to control pin configuration and muxing" bitfld.long 0x10C 31. "PADCONFIG67_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x10C 30. "PADCONFIG67_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x10C 29. "PADCONFIG67_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x10C 28. "PADCONFIG67_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x10C 27. "PADCONFIG67_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x10C 26. "PADCONFIG67_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x10C 25. "PADCONFIG67_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x10C 24. "PADCONFIG67_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x10C 23. "PADCONFIG67_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x10C 22. "PADCONFIG67_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x10C 21. "PADCONFIG67_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x10C 19.--20. "PADCONFIG67_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x10C 18. "PADCONFIG67_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x10C 17. "PADCONFIG67_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x10C 16. "PADCONFIG67_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x10C 15. "PADCONFIG67_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x10C 14. "PADCONFIG67_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x10C 11.--13. "PADCONFIG67_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10C 8. "PADCONFIG67_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x10C 7. "PADCONFIG67_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x10C 4.--5. "PADCONFIG67_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x10C 0.--3. 1. "PADCONFIG67_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x110 "CFG0_PADCONFIG68_PROXY,Register to control pin configuration and muxing" bitfld.long 0x110 31. "PADCONFIG68_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x110 30. "PADCONFIG68_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x110 29. "PADCONFIG68_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x110 28. "PADCONFIG68_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x110 27. "PADCONFIG68_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x110 26. "PADCONFIG68_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x110 25. "PADCONFIG68_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x110 24. "PADCONFIG68_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x110 23. "PADCONFIG68_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x110 22. "PADCONFIG68_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x110 21. "PADCONFIG68_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x110 19.--20. "PADCONFIG68_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x110 18. "PADCONFIG68_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x110 17. "PADCONFIG68_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x110 16. "PADCONFIG68_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x110 15. "PADCONFIG68_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x110 14. "PADCONFIG68_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x110 11.--13. "PADCONFIG68_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x110 8. "PADCONFIG68_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x110 7. "PADCONFIG68_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x110 4.--5. "PADCONFIG68_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x110 0.--3. 1. "PADCONFIG68_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x114 "CFG0_PADCONFIG69_PROXY,Register to control pin configuration and muxing" bitfld.long 0x114 31. "PADCONFIG69_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x114 30. "PADCONFIG69_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x114 29. "PADCONFIG69_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x114 28. "PADCONFIG69_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x114 27. "PADCONFIG69_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x114 26. "PADCONFIG69_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x114 25. "PADCONFIG69_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x114 24. "PADCONFIG69_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x114 23. "PADCONFIG69_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x114 22. "PADCONFIG69_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x114 21. "PADCONFIG69_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x114 19.--20. "PADCONFIG69_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x114 18. "PADCONFIG69_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x114 17. "PADCONFIG69_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x114 16. "PADCONFIG69_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x114 15. "PADCONFIG69_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x114 14. "PADCONFIG69_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x114 11.--13. "PADCONFIG69_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x114 8. "PADCONFIG69_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x114 7. "PADCONFIG69_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x114 4.--5. "PADCONFIG69_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x114 0.--3. 1. "PADCONFIG69_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x118 "CFG0_PADCONFIG70_PROXY,Register to control pin configuration and muxing" bitfld.long 0x118 31. "PADCONFIG70_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x118 30. "PADCONFIG70_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x118 29. "PADCONFIG70_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x118 28. "PADCONFIG70_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x118 27. "PADCONFIG70_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x118 26. "PADCONFIG70_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x118 25. "PADCONFIG70_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x118 24. "PADCONFIG70_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x118 23. "PADCONFIG70_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x118 22. "PADCONFIG70_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x118 21. "PADCONFIG70_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x118 19.--20. "PADCONFIG70_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x118 18. "PADCONFIG70_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x118 17. "PADCONFIG70_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x118 16. "PADCONFIG70_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x118 15. "PADCONFIG70_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x118 14. "PADCONFIG70_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x118 11.--13. "PADCONFIG70_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x118 8. "PADCONFIG70_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x118 7. "PADCONFIG70_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x118 4.--5. "PADCONFIG70_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x118 0.--3. 1. "PADCONFIG70_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." line.long 0x11C "CFG0_PADCONFIG71_PROXY,Register to control pin configuration and muxing" bitfld.long 0x11C 31. "PADCONFIG71_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x11C 30. "PADCONFIG71_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x11C 29. "PADCONFIG71_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x11C 28. "PADCONFIG71_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x11C 27. "PADCONFIG71_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x11C 26. "PADCONFIG71_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x11C 25. "PADCONFIG71_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x11C 24. "PADCONFIG71_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0: IO keeps its previous state when Deep Sleep mode..,?" newline bitfld.long 0x11C 23. "PADCONFIG71_ISO_BYP_PROXY,Isolation Bypass0 - IO isolation is preserved1 - IO isolation is bypassed" "0: IO isolation is preserved1,?" newline bitfld.long 0x11C 22. "PADCONFIG71_ISO_OVR_PROXY,Isolation Override0 - IO isolation is preserved1 - IO isolation is overridden" "0: IO isolation is preserved1,?" newline bitfld.long 0x11C 21. "PADCONFIG71_TX_DIS_PROXY,Driver Disable0 - Driver is enabled1 - Driver is disabled" "0: Driver is enabled1,?" newline bitfld.long 0x11C 19.--20. "PADCONFIG71_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x11C 18. "PADCONFIG71_RXACTIVE_PROXY,Input enable for the Pad0 - Receiver disabled1 - Receiver enabled" "0: Receiver disabled1,?" newline bitfld.long 0x11C 17. "PADCONFIG71_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection0 - Pulldown selected1 - Pullup selected" "0: Pulldown selected1,?" newline bitfld.long 0x11C 16. "PADCONFIG71_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal.0 - Pullup / Pulldown enabled1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled1,?" newline bitfld.long 0x11C 15. "PADCONFIG71_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating0 - Deep Sleep pad controls are gated by the DMSC1 - Activate Deep Sleep pad controls (override DMSC gating logic)" "0: Deep Sleep pad controls are gated by the DMSC1,?" newline bitfld.long 0x11C 14. "PADCONFIG71_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x11C 11.--13. "PADCONFIG71_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x11C 8. "PADCONFIG71_WK_LVL_POL_PROXY,Level Sensitive Wakeup PolarityThis bit is not relevant unless wk_lvl_en is set to 1'b1.0 - Low. A low (0) value on the pin causes a wakeup1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x11C 7. "PADCONFIG71_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable0 - Disabled. Wakeup is triggered by change of the pin input value1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x11C 4.--5. "PADCONFIG71_VGPIO_SEL_PROXY,Virtual MAIN_GPIO instance select.These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,2: Implement GPIO in GPIO_WKUP_4 instance 2'b11,?" newline hexmask.long.byte 0x11C 0.--3. 1. "PADCONFIG71_MUXMODE_PROXY,Pad functional signal mux selection Field values (Others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5.." rgroup.long 0x1F008++0x7 line.long 0x0 "CFG0_LOCK7_KICK0_PROXY,This register must be written with the designated key value followed by a write to LOCK7_KICK1 with its key value before write-protected Partition 7 registers can be written." hexmask.long 0x0 0.--31. 1. "LOCK7_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK7_KICK1_PROXY,This register must be written with the designated key value after a write to LOCK7_KICK0 with its key value before write-protected Partition 7 registers can be written." hexmask.long 0x4 0.--31. 1. "LOCK7_KICK1_PROXY,- KICK1 component" rgroup.long 0x1F100++0xB line.long 0x0 "CFG0_CLAIMREG_P7_R0," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P7_R0,Claim bits for Partition 7" line.long 0x4 "CFG0_CLAIMREG_P7_R1," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P7_R1,Claim bits for Partition 7" line.long 0x8 "CFG0_CLAIMREG_P7_R2," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P7_R2,Claim bits for Partition 7" tree.end tree "DCC" base ad:0x0 tree "DCC0 (DCC0)" base ad:0x800000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register. User privilege and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User privilege and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User privilege and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.." rgroup.long 0x4++0x3 line.long 0x0 "CFG_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained. User privilege and debug mode (read): 0x0 Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User privilege and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User privilege and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect." rgroup.long 0x8++0xF line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User privilege and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.." line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User privilege and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.." line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User privilege and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.." line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag" bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag" rgroup.long 0x18++0xB line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User privilege and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect." line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User privilege and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect." line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User privilege and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect." rgroup.long 0x24++0xB line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature. User privilege and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC." line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User privilege and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0." line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.." rgroup.long 0x30++0x3 line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User privilege and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User privilege and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User privilege and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User privilege and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User privilege and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User privilege and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty" rgroup.long 0x34++0x3 line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree "DCC1 (DCC1)" base ad:0x804000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register. User privilege and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User privilege and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User privilege and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.." rgroup.long 0x4++0x3 line.long 0x0 "CFG_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained. User privilege and debug mode (read): 0x0 Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User privilege and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User privilege and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect." rgroup.long 0x8++0xF line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User privilege and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.." line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User privilege and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.." line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User privilege and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.." line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag" bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag" rgroup.long 0x18++0xB line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User privilege and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect." line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User privilege and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect." line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User privilege and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect." rgroup.long 0x24++0xB line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature. User privilege and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC." line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User privilege and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0." line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.." rgroup.long 0x30++0x3 line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User privilege and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User privilege and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User privilege and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User privilege and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User privilege and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User privilege and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty" rgroup.long 0x34++0x3 line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree "DCC2 (DCC2)" base ad:0x808000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register. User privilege and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User privilege and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User privilege and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.." rgroup.long 0x4++0x3 line.long 0x0 "CFG_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained. User privilege and debug mode (read): 0x0 Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User privilege and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User privilege and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect." rgroup.long 0x8++0xF line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User privilege and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.." line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User privilege and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.." line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User privilege and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.." line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag" bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag" rgroup.long 0x18++0xB line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User privilege and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect." line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User privilege and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect." line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User privilege and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect." rgroup.long 0x24++0xB line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature. User privilege and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC." line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User privilege and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0." line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.." rgroup.long 0x30++0x3 line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User privilege and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User privilege and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User privilege and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User privilege and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User privilege and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User privilege and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty" rgroup.long 0x34++0x3 line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree "DCC3 (DCC3)" base ad:0x80C000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register. User privilege and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User privilege and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User privilege and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.." rgroup.long 0x4++0x3 line.long 0x0 "CFG_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained. User privilege and debug mode (read): 0x0 Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User privilege and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User privilege and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect." rgroup.long 0x8++0xF line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User privilege and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.." line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User privilege and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.." line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User privilege and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.." line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag" bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag" rgroup.long 0x18++0xB line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User privilege and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect." line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User privilege and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect." line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User privilege and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect." rgroup.long 0x24++0xB line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature. User privilege and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC." line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User privilege and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0." line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.." rgroup.long 0x30++0x3 line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User privilege and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User privilege and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User privilege and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User privilege and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User privilege and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User privilege and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty" rgroup.long 0x34++0x3 line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree "DCC4 (DCC4)" base ad:0x810000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register. User privilege and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User privilege and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User privilege and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.." rgroup.long 0x4++0x3 line.long 0x0 "CFG_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained. User privilege and debug mode (read): 0x0 Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User privilege and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User privilege and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect." rgroup.long 0x8++0xF line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User privilege and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.." line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User privilege and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.." line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User privilege and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.." line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag" bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag" rgroup.long 0x18++0xB line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User privilege and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect." line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User privilege and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect." line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User privilege and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect." rgroup.long 0x24++0xB line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature. User privilege and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC." line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User privilege and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0." line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.." rgroup.long 0x30++0x3 line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User privilege and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User privilege and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User privilege and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User privilege and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User privilege and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User privilege and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty" rgroup.long 0x34++0x3 line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree "DCC5 (DCC5)" base ad:0x814000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register. User privilege and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User privilege and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User privilege and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.." rgroup.long 0x4++0x3 line.long 0x0 "CFG_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained. User privilege and debug mode (read): 0x0 Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User privilege and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User privilege and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect." rgroup.long 0x8++0xF line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User privilege and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.." line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User privilege and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.." line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User privilege and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.." line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag" bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag" rgroup.long 0x18++0xB line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User privilege and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect." line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User privilege and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect." line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User privilege and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect." rgroup.long 0x24++0xB line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature. User privilege and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC." line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User privilege and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0." line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.." rgroup.long 0x30++0x3 line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User privilege and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User privilege and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User privilege and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User privilege and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User privilege and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User privilege and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty" rgroup.long 0x34++0x3 line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree "DCC6 (DCC6)" base ad:0x818000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register. User privilege and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User privilege and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User privilege and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.." rgroup.long 0x4++0x3 line.long 0x0 "CFG_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained. User privilege and debug mode (read): 0x0 Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User privilege and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User privilege and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect." rgroup.long 0x8++0xF line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User privilege and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.." line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User privilege and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.." line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User privilege and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.." line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag" bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag" rgroup.long 0x18++0xB line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User privilege and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect." line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User privilege and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect." line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User privilege and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect." rgroup.long 0x24++0xB line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature. User privilege and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC." line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User privilege and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0." line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.." rgroup.long 0x30++0x3 line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User privilege and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User privilege and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User privilege and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User privilege and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User privilege and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User privilege and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty" rgroup.long 0x34++0x3 line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree "DCC7 (DCC7)" base ad:0x81C000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register. User privilege and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User privilege and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User privilege and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.." rgroup.long 0x4++0x3 line.long 0x0 "CFG_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained. User privilege and debug mode (read): 0x0 Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User privilege and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User privilege and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect." rgroup.long 0x8++0xF line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User privilege and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.." line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User privilege and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.." line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User privilege and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.." line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag" bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag" rgroup.long 0x18++0xB line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User privilege and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect." line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User privilege and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect." line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User privilege and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect." rgroup.long 0x24++0xB line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature. User privilege and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC." line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User privilege and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0." line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.." rgroup.long 0x30++0x3 line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User privilege and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User privilege and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User privilege and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User privilege and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User privilege and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User privilege and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty" rgroup.long 0x34++0x3 line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree "DCC8 (DCC8)" base ad:0x820000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register. User privilege and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User privilege and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User privilege and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.." rgroup.long 0x4++0x3 line.long 0x0 "CFG_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained. User privilege and debug mode (read): 0x0 Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User privilege and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User privilege and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect." rgroup.long 0x8++0xF line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User privilege and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.." line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User privilege and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.." line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User privilege and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.." line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag" bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag" rgroup.long 0x18++0xB line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User privilege and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect." line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User privilege and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect." line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User privilege and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect." rgroup.long 0x24++0xB line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature. User privilege and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC." line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User privilege and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0." line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.." rgroup.long 0x30++0x3 line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User privilege and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User privilege and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User privilege and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User privilege and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User privilege and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User privilege and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty" rgroup.long 0x34++0x3 line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree "DCC9 (DCC9)" base ad:0x824000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register. User privilege and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User privilege and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User privilege and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.." rgroup.long 0x4++0x3 line.long 0x0 "CFG_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained. User privilege and debug mode (read): 0x0 Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User privilege and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User privilege and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect." rgroup.long 0x8++0xF line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User privilege and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.." line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User privilege and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.." line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User privilege and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.." line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag" bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag" rgroup.long 0x18++0xB line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User privilege and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect." line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User privilege and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect." line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User privilege and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect." rgroup.long 0x24++0xB line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature. User privilege and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC." line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User privilege and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0." line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.." rgroup.long 0x30++0x3 line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User privilege and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User privilege and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User privilege and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User privilege and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User privilege and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User privilege and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty" rgroup.long 0x34++0x3 line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree.end tree "DMPAC0" base ad:0x0 tree "DMPAC0_CTSET_0_CTSET2_WRAP_CFG_CTSET2_CFG (DMPAC0_CTSET_0_CTSET2_WRAP_CFG_CTSET2_CFG)" base ad:0xF420000 rgroup.long 0x0++0x3 line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTSETID,CTSET identification register" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old Scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,The value 10b designates this as Processor Business Unit IP" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Function : Indicates a Debug IP (0x2nn) and 0x80 is the identifier for CT-SET" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VERSION,This field changes on bug fix and resets to '0' when either Minor Revision or Major Revision field changes" bitfld.long 0x0 8.--10. "MAJOR_REV,Major Revision. This field changes when there is a major feature change." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device. 0 if non-custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor Revision. This field changes when features are scaled up or down" rgroup.long 0x10++0x3 line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTSETSYSCFG,CTSET system configuration register" hexmask.long 0x0 4.--31. 1. "RESERVED1,Reserved returns 0" bitfld.long 0x0 2.--3. "IDLEMODE,Sets the Idle Mode for CTSET (0=Force Idle 1=No Idle 2=Smart Idle 3= Smart Idle wakeup)" "0: Force Idle,1: No Idle,2: Smart Idle,3: Smart Idle wakeup)" rbitfld.long 0x0 1. "RESERVED,Reserved returns 0" "0,1" newline bitfld.long 0x0 0. "SOFTRESET,This will reset entire CTSET except the registers and the CFG interface. This bit is automatically cleared by hardware. Reads always return 0" "0,1" rgroup.long 0x14++0xB line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_SETSTR,CTSET status register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED1,Reserved returns 0" bitfld.long 0x0 8. "HWFIFOEMPTY,System Event Trace FIFO status 1 is empty 0 means captured data not yet exported" "0,1" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Reserved returns 0" newline bitfld.long 0x0 0. "RESETDONE,Reset status 0 means reset ongoing 1 indicates completed" "0,1" line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_DBGTIMELOW,The 32 low order bits of the debug time value supplied on the time input interface" hexmask.long 0x4 0.--31. 1. "DBGTIME,debug time" line.long 0x8 "CTSET2_WRAP__CFG__CTSET2_CFG_DBGTIMEHI,The 32 high order bits of the debug time value supplied on the time input interface" hexmask.long 0x8 0.--31. 1. "DBGTIME,debug time" rgroup.long 0x24++0x7 line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTSETCFG,The 32 low order bits of the debug time value supplied on the time input interface The 32 high order bits of the debug time value supplied on the time input interface. Reading DBGTIMEHI latches the lower 32 bits of.." hexmask.long.byte 0x0 28.--31. 1. "CLAIM,Claim control and status. To program any bits other than 31 : 28 CTSET ownership must be claimed using bits 31 : 28." hexmask.long.tbyte 0x0 8.--27. 1. "RESERVED2,Reserved returns 0" bitfld.long 0x0 7. "SYSEVENTCAPTEN,When 1 the System event capture is enabled" "0,1" newline rbitfld.long 0x0 5.--6. "RESERVED1,Reserved returns 0" "0,1,2,3" bitfld.long 0x0 4. "EVENTLEVEL,0 enables low level event detection 1 enables high level event detection" "0,1" bitfld.long 0x0 3. "MSGMODE,Message generated based on event detection 0 is sampling window 1 is event detection" "0,1" newline bitfld.long 0x0 2. "STOPCAPT,Stop capturing system events from external trigger detection" "0,1" bitfld.long 0x0 1. "STARTCAPT,Start capturing system events from external trigger detection" "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved returns 0" "0,1" line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_SETSPLREG,System Event Sampling Window register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x4 0.--7. 1. "WINDOWSIZE,System events sampling window size expressed as CTSET cycles" rgroup.long 0x30++0x23 line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL1,System event detection enable register 1" bitfld.long 0x0 31. "EVENT32DETEN,Event(32) Detection Enable" "0,1" bitfld.long 0x0 30. "EVENT31DETEN,Event(31) Detection Enable" "0,1" bitfld.long 0x0 29. "EVENT30DETEN,Event(30) Detection Enable" "0,1" newline bitfld.long 0x0 28. "EVENT29DETEN,Event(29) Detection Enable" "0,1" bitfld.long 0x0 27. "EVENT28DETEN,Event(28) Detection Enable" "0,1" bitfld.long 0x0 26. "EVENT27DETEN,Event(27) Detection Enable" "0,1" newline bitfld.long 0x0 25. "EVENT26DETEN,Event(26) Detection Enable" "0,1" bitfld.long 0x0 24. "EVENT25DETEN,Event(25) Detection Enable" "0,1" bitfld.long 0x0 23. "EVENT24DETEN,Event(24) Detection Enable" "0,1" newline bitfld.long 0x0 22. "EVENT23DETEN,Event(23) Detection Enable" "0,1" bitfld.long 0x0 21. "EVENT22DETEN,Event(22) Detection Enable" "0,1" bitfld.long 0x0 20. "EVENT21DETEN,Event(21) Detection Enable" "0,1" newline bitfld.long 0x0 19. "EVENT20DETEN,Event(20) Detection Enable" "0,1" bitfld.long 0x0 18. "EVENT19DETEN,Event(19) Detection Enable" "0,1" bitfld.long 0x0 17. "EVENT18DETEN,Event(18) Detection Enable" "0,1" newline bitfld.long 0x0 16. "EVENT17DETEN,Event(17) Detection Enable" "0,1" bitfld.long 0x0 15. "EVENT16DETEN,Event(16) Detection Enable" "0,1" bitfld.long 0x0 14. "EVENT15DETEN,Event(15) Detection Enable" "0,1" newline bitfld.long 0x0 13. "EVENT14DETEN,Event(14) Detection Enable" "0,1" bitfld.long 0x0 12. "EVENT13DETEN,Event(13) Detection Enable" "0,1" bitfld.long 0x0 11. "EVENT12DETEN,Event(12) Detection Enable" "0,1" newline bitfld.long 0x0 10. "EVENT11DETEN,Event(11) Detection Enable" "0,1" bitfld.long 0x0 9. "EVENT10DETEN,Event(10) Detection Enable" "0,1" bitfld.long 0x0 8. "EVENT9DETEN,Event(9) Detection Enable" "0,1" newline bitfld.long 0x0 7. "EVENT8DETEN,Event(8) Detection Enable" "0,1" bitfld.long 0x0 6. "EVENT7DETEN,Event(7) Detection Enable" "0,1" bitfld.long 0x0 5. "EVENT6DETEN,Event(6) Detection Enable" "0,1" newline bitfld.long 0x0 4. "EVENT5DETEN,Event(5) Detection Enable" "0,1" bitfld.long 0x0 3. "EVENT4DETEN,Event(4) Detection Enable" "0,1" bitfld.long 0x0 2. "EVENT3DETEN,Event(3) Detection Enable" "0,1" newline bitfld.long 0x0 1. "EVENT2DETEN,Event(2) Detection Enable" "0,1" bitfld.long 0x0 0. "EVENT1DETEN,Event(1) Detection Enable" "0,1" line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL2,System event detection enable register 2 (if number of events > 32)" bitfld.long 0x4 31. "EVENT64DETEN,Event(64) Detection Enable" "0,1" bitfld.long 0x4 30. "EVENT63DETEN,Event(63) Detection Enable" "0,1" bitfld.long 0x4 29. "EVENT62DETEN,Event(62) Detection Enable" "0,1" newline bitfld.long 0x4 28. "EVENT61DETEN,Event(61) Detection Enable" "0,1" bitfld.long 0x4 27. "EVENT60DETEN,Event(60) Detection Enable" "0,1" bitfld.long 0x4 26. "EVENT59DETEN,Event(59) Detection Enable" "0,1" newline bitfld.long 0x4 25. "EVENT58DETEN,Event(58) Detection Enable" "0,1" bitfld.long 0x4 24. "EVENT57DETEN,Event(57) Detection Enable" "0,1" bitfld.long 0x4 23. "EVENT56DETEN,Event(56) Detection Enable" "0,1" newline bitfld.long 0x4 22. "EVENT55DETEN,Event(55) Detection Enable" "0,1" bitfld.long 0x4 21. "EVENT54DETEN,Event(54) Detection Enable" "0,1" bitfld.long 0x4 20. "EVENT53DETEN,Event(53) Detection Enable" "0,1" newline bitfld.long 0x4 19. "EVENT52DETEN,Event(52) Detection Enable" "0,1" bitfld.long 0x4 18. "EVENT51DETEN,Event(51) Detection Enable" "0,1" bitfld.long 0x4 17. "EVENT50DETEN,Event(50) Detection Enable" "0,1" newline bitfld.long 0x4 16. "EVENT49DETEN,Event(49) Detection Enable" "0,1" bitfld.long 0x4 15. "EVENT48DETEN,Event(48) Detection Enable" "0,1" bitfld.long 0x4 14. "EVENT47DETEN,Event(47) Detection Enable" "0,1" newline bitfld.long 0x4 13. "EVENT46DETEN,Event(46) Detection Enable" "0,1" bitfld.long 0x4 12. "EVENT45DETEN,Event(45) Detection Enable" "0,1" bitfld.long 0x4 11. "EVENT44DETEN,Event(44) Detection Enable" "0,1" newline bitfld.long 0x4 10. "EVENT43DETEN,Event(43) Detection Enable" "0,1" bitfld.long 0x4 9. "EVENT42DETEN,Event(42) Detection Enable" "0,1" bitfld.long 0x4 8. "EVENT41DETEN,Event(41) Detection Enable" "0,1" newline bitfld.long 0x4 7. "EVENT40DETEN,Event(40) Detection Enable" "0,1" bitfld.long 0x4 6. "EVENT39DETEN,Event(39) Detection Enable" "0,1" bitfld.long 0x4 5. "EVENT38DETEN,Event(38) Detection Enable" "0,1" newline bitfld.long 0x4 4. "EVENT37DETEN,Event(37) Detection Enable" "0,1" bitfld.long 0x4 3. "EVENT36DETEN,Event(36) Detection Enable" "0,1" bitfld.long 0x4 2. "EVENT35DETEN,Event(35) Detection Enable" "0,1" newline bitfld.long 0x4 1. "EVENT34DETEN,Event(34) Detection Enable" "0,1" bitfld.long 0x4 0. "EVENT33DETEN,Event(33) Detection Enable" "0,1" line.long 0x8 "CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL3,System event detection enable register 3 (if number of events > 64)" bitfld.long 0x8 31. "EVENT96DETEN,Event(96) Detection Enable" "0,1" bitfld.long 0x8 30. "EVENT95DETEN,Event(95) Detection Enable" "0,1" bitfld.long 0x8 29. "EVENT94DETEN,Event(94) Detection Enable" "0,1" newline bitfld.long 0x8 28. "EVENT93DETEN,Event(93) Detection Enable" "0,1" bitfld.long 0x8 27. "EVENT92DETEN,Event(92) Detection Enable" "0,1" bitfld.long 0x8 26. "EVENT91DETEN,Event(91) Detection Enable" "0,1" newline bitfld.long 0x8 25. "EVENT90DETEN,Event(90) Detection Enable" "0,1" bitfld.long 0x8 24. "EVENT89DETEN,Event(89) Detection Enable" "0,1" bitfld.long 0x8 23. "EVENT88DETEN,Event(88) Detection Enable" "0,1" newline bitfld.long 0x8 22. "EVENT87DETEN,Event(87) Detection Enable" "0,1" bitfld.long 0x8 21. "EVENT86DETEN,Event(86) Detection Enable" "0,1" bitfld.long 0x8 20. "EVENT85DETEN,Event(85) Detection Enable" "0,1" newline bitfld.long 0x8 19. "EVENT84DETEN,Event(84) Detection Enable" "0,1" bitfld.long 0x8 18. "EVENT83DETEN,Event(83) Detection Enable" "0,1" bitfld.long 0x8 17. "EVENT82DETEN,Event(82) Detection Enable" "0,1" newline bitfld.long 0x8 16. "EVENT81DETEN,Event(81) Detection Enable" "0,1" bitfld.long 0x8 15. "EVENT80DETEN,Event(80) Detection Enable" "0,1" bitfld.long 0x8 14. "EVENT79DETEN,Event(79) Detection Enable" "0,1" newline bitfld.long 0x8 13. "EVENT78DETEN,Event(78) Detection Enable" "0,1" bitfld.long 0x8 12. "EVENT77DETEN,Event(77) Detection Enable" "0,1" bitfld.long 0x8 11. "EVENT76DETEN,Event(76) Detection Enable" "0,1" newline bitfld.long 0x8 10. "EVENT75DETEN,Event(75) Detection Enable" "0,1" bitfld.long 0x8 9. "EVENT74DETEN,Event(74) Detection Enable" "0,1" bitfld.long 0x8 8. "EVENT73DETEN,Event(73) Detection Enable" "0,1" newline bitfld.long 0x8 7. "EVENT72DETEN,Event(72) Detection Enable" "0,1" bitfld.long 0x8 6. "EVENT71DETEN,Event(71) Detection Enable" "0,1" bitfld.long 0x8 5. "EVENT70DETEN,Event(70) Detection Enable" "0,1" newline bitfld.long 0x8 4. "EVENT69DETEN,Event(69) Detection Enable" "0,1" bitfld.long 0x8 3. "EVENT68DETEN,Event(68) Detection Enable" "0,1" bitfld.long 0x8 2. "EVENT67DETEN,Event(67) Detection Enable" "0,1" newline bitfld.long 0x8 1. "EVENT66DETEN,Event(66) Detection Enable" "0,1" bitfld.long 0x8 0. "EVENT65DETEN,Event(65) Detection Enable" "0,1" line.long 0xC "CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL4,System event detection enable register 4 (if number of events > 96)" bitfld.long 0xC 31. "EVENT128DETEN,Event(128) Detection Enable" "0,1" bitfld.long 0xC 30. "EVENT127DETEN,Event(127) Detection Enable" "0,1" bitfld.long 0xC 29. "EVENT126DETEN,Event(126) Detection Enable" "0,1" newline bitfld.long 0xC 28. "EVENT125DETEN,Event(125) Detection Enable" "0,1" bitfld.long 0xC 27. "EVENT124DETEN,Event(124) Detection Enable" "0,1" bitfld.long 0xC 26. "EVENT123DETEN,Event(123) Detection Enable" "0,1" newline bitfld.long 0xC 25. "EVENT122DETEN,Event(122) Detection Enable" "0,1" bitfld.long 0xC 24. "EVENT121DETEN,Event(121) Detection Enable" "0,1" bitfld.long 0xC 23. "EVENT120DETEN,Event(120) Detection Enable" "0,1" newline bitfld.long 0xC 22. "EVENT119DETEN,Event(119) Detection Enable" "0,1" bitfld.long 0xC 21. "EVENT118DETEN,Event(118) Detection Enable" "0,1" bitfld.long 0xC 20. "EVENT117DETEN,Event(117) Detection Enable" "0,1" newline bitfld.long 0xC 19. "EVENT116DETEN,Event(116) Detection Enable" "0,1" bitfld.long 0xC 18. "EVENT115DETEN,Event(115) Detection Enable" "0,1" bitfld.long 0xC 17. "EVENT114DETEN,Event(114) Detection Enable" "0,1" newline bitfld.long 0xC 16. "EVENT113DETEN,Event(113) Detection Enable" "0,1" bitfld.long 0xC 15. "EVENT112DETEN,Event(112) Detection Enable" "0,1" bitfld.long 0xC 14. "EVENT111DETEN,Event(111) Detection Enable" "0,1" newline bitfld.long 0xC 13. "EVENT110DETEN,Event(110) Detection Enable" "0,1" bitfld.long 0xC 12. "EVENT109DETEN,Event(109) Detection Enable" "0,1" bitfld.long 0xC 11. "EVENT108DETEN,Event(108) Detection Enable" "0,1" newline bitfld.long 0xC 10. "EVENT107DETEN,Event(107) Detection Enable" "0,1" bitfld.long 0xC 9. "EVENT106DETEN,Event(106) Detection Enable" "0,1" bitfld.long 0xC 8. "EVENT105DETEN,Event(105) Detection Enable" "0,1" newline bitfld.long 0xC 7. "EVENT104DETEN,Event(104) Detection Enable" "0,1" bitfld.long 0xC 6. "EVENT103DETEN,Event(103) Detection Enable" "0,1" bitfld.long 0xC 5. "EVENT102DETEN,Event(102) Detection Enable" "0,1" newline bitfld.long 0xC 4. "EVENT101DETEN,Event(101) Detection Enable" "0,1" bitfld.long 0xC 3. "EVENT100DETEN,Event(100) Detection Enable" "0,1" bitfld.long 0xC 2. "EVENT99DETEN,Event(99) Detection Enable" "0,1" newline bitfld.long 0xC 1. "EVENT98DETEN,Event(98) Detection Enable" "0,1" bitfld.long 0xC 0. "EVENT97DETEN,Event(97) Detection Enable" "0,1" line.long 0x10 "CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL5,System event detection enable register 5 (if number of events > 128)" bitfld.long 0x10 31. "EVENT160DETEN,Event(160) Detection Enable" "0,1" bitfld.long 0x10 30. "EVENT159DETEN,Event(159) Detection Enable" "0,1" bitfld.long 0x10 29. "EVENT158DETEN,Event(158) Detection Enable" "0,1" newline bitfld.long 0x10 28. "EVENT157DETEN,Event(157) Detection Enable" "0,1" bitfld.long 0x10 27. "EVENT156DETEN,Event(156) Detection Enable" "0,1" bitfld.long 0x10 26. "EVENT155DETEN,Event(155) Detection Enable" "0,1" newline bitfld.long 0x10 25. "EVENT154DETEN,Event(154) Detection Enable" "0,1" bitfld.long 0x10 24. "EVENT153DETEN,Event(153) Detection Enable" "0,1" bitfld.long 0x10 23. "EVENT152DETEN,Event(152) Detection Enable" "0,1" newline bitfld.long 0x10 22. "EVENT151DETEN,Event(151) Detection Enable" "0,1" bitfld.long 0x10 21. "EVENT150DETEN,Event(150) Detection Enable" "0,1" bitfld.long 0x10 20. "EVENT149DETEN,Event(149) Detection Enable" "0,1" newline bitfld.long 0x10 19. "EVENT148DETEN,Event(148) Detection Enable" "0,1" bitfld.long 0x10 18. "EVENT147DETEN,Event(147) Detection Enable" "0,1" bitfld.long 0x10 17. "EVENT1468DETEN,Event(146) Detection Enable" "0,1" newline bitfld.long 0x10 16. "EVENT145DETEN,Event(145) Detection Enable" "0,1" bitfld.long 0x10 15. "EVENT144DETEN,Event(144) Detection Enable" "0,1" bitfld.long 0x10 14. "EVENT143DETEN,Event(143) Detection Enable" "0,1" newline bitfld.long 0x10 13. "EVENT142DETEN,Event(142) Detection Enable" "0,1" bitfld.long 0x10 12. "EVENT141DETEN,Event(141) Detection Enable" "0,1" bitfld.long 0x10 11. "EVENT140DETEN,Event(140) Detection Enable" "0,1" newline bitfld.long 0x10 10. "EVENT139DETEN,Event(139) Detection Enable" "0,1" bitfld.long 0x10 9. "EVENT138DETEN,Event(138) Detection Enable" "0,1" bitfld.long 0x10 8. "EVENT137DETEN,Event(137) Detection Enable" "0,1" newline bitfld.long 0x10 7. "EVENT136DETEN,Event(136) Detection Enable" "0,1" bitfld.long 0x10 6. "EVENT135DETEN,Event(135) Detection Enable" "0,1" bitfld.long 0x10 5. "EVENT134DETEN,Event(134) Detection Enable" "0,1" newline bitfld.long 0x10 4. "EVENT133DETEN,Event(133) Detection Enable" "0,1" bitfld.long 0x10 3. "EVENT132DETEN,Event(132) Detection Enable" "0,1" bitfld.long 0x10 2. "EVENT131DETEN,Event(131) Detection Enable" "0,1" newline bitfld.long 0x10 1. "EVENT130DETEN,Event(130) Detection Enable" "0,1" bitfld.long 0x10 0. "EVENT129DETEN,Event(129) Detection Enable" "0,1" line.long 0x14 "CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL6,System event detection enable register 6 (if number of events > 160)" bitfld.long 0x14 31. "EVENT192DETEN,Event(192) Detection Enable" "0,1" bitfld.long 0x14 30. "EVENT191DETEN,Event(191) Detection Enable" "0,1" bitfld.long 0x14 29. "EVENT190DETEN,Event(190) Detection Enable" "0,1" newline bitfld.long 0x14 28. "EVENT189DETEN,Event(189) Detection Enable" "0,1" bitfld.long 0x14 27. "EVENT188DETEN,Event(188) Detection Enable" "0,1" bitfld.long 0x14 26. "EVENT187DETEN,Event(187) Detection Enable" "0,1" newline bitfld.long 0x14 25. "EVENT186DETEN,Event(186) Detection Enable" "0,1" bitfld.long 0x14 24. "EVENT185DETEN,Event(185) Detection Enable" "0,1" bitfld.long 0x14 23. "EVENT184DETEN,Event(184) Detection Enable" "0,1" newline bitfld.long 0x14 22. "EVENT183DETEN,Event(183) Detection Enable" "0,1" bitfld.long 0x14 21. "EVENT182DETEN,Event(182) Detection Enable" "0,1" bitfld.long 0x14 20. "EVENT181DETEN,Event(181) Detection Enable" "0,1" newline bitfld.long 0x14 19. "EVENT180DETEN,Event(180) Detection Enable" "0,1" bitfld.long 0x14 18. "EVENT179DETEN,Event(179) Detection Enable" "0,1" bitfld.long 0x14 17. "EVENT178DETEN,Event(178) Detection Enable" "0,1" newline bitfld.long 0x14 16. "EVENT177DETEN,Event(177) Detection Enable" "0,1" bitfld.long 0x14 15. "EVENT176DETEN,Event(176) Detection Enable" "0,1" bitfld.long 0x14 14. "EVENT175DETEN,Event(175) Detection Enable" "0,1" newline bitfld.long 0x14 13. "EVENT174DETEN,Event(174) Detection Enable" "0,1" bitfld.long 0x14 12. "EVENT173DETEN,Event(173) Detection Enable" "0,1" bitfld.long 0x14 11. "EVENT172DETEN,Event(172) Detection Enable" "0,1" newline bitfld.long 0x14 10. "EVENT171DETEN,Event(171) Detection Enable" "0,1" bitfld.long 0x14 9. "EVENT170DETEN,Event(170) Detection Enable" "0,1" bitfld.long 0x14 8. "EVENT169DETEN,Event(169) Detection Enable" "0,1" newline bitfld.long 0x14 7. "EVENT168DETEN,Event(168) Detection Enable" "0,1" bitfld.long 0x14 6. "EVENT167DETEN,Event(167) Detection Enable" "0,1" bitfld.long 0x14 5. "EVENT166DETEN,Event(166) Detection Enable" "0,1" newline bitfld.long 0x14 4. "EVENT165DETEN,Event(165) Detection Enable" "0,1" bitfld.long 0x14 3. "EVENT164DETEN,Event(164) Detection Enable" "0,1" bitfld.long 0x14 2. "EVENT163DETEN,Event(163) Detection Enable" "0,1" newline bitfld.long 0x14 1. "EVENT162DETEN,Event(162) Detection Enable" "0,1" bitfld.long 0x14 0. "EVENT161DETEN,Event(161) Detection Enable" "0,1" line.long 0x18 "CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL7,System event detection enable register 7 (if number of events > 192)" bitfld.long 0x18 31. "EVENT224DETEN,Event(224) Detection Enable" "0,1" bitfld.long 0x18 30. "EVENT223DETEN,Event(223) Detection Enable" "0,1" bitfld.long 0x18 29. "EVENT222DETEN,Event(222) Detection Enable" "0,1" newline bitfld.long 0x18 28. "EVENT221DETEN,Event(221) Detection Enable" "0,1" bitfld.long 0x18 27. "EVENT220DETEN,Event(220) Detection Enable" "0,1" bitfld.long 0x18 26. "EVENT219DETEN,Event(219) Detection Enable" "0,1" newline bitfld.long 0x18 25. "EVENT218DETEN,Event(218) Detection Enable" "0,1" bitfld.long 0x18 24. "EVENT217DETEN,Event(217) Detection Enable" "0,1" bitfld.long 0x18 23. "EVENT216DETEN,Event(216) Detection Enable" "0,1" newline bitfld.long 0x18 22. "EVENT215DETEN,Event(215) Detection Enable" "0,1" bitfld.long 0x18 21. "EVENT214DETEN,Event(214) Detection Enable" "0,1" bitfld.long 0x18 20. "EVENT213DETEN,Event(213) Detection Enable" "0,1" newline bitfld.long 0x18 19. "EVENT212DETEN,Event(212) Detection Enable" "0,1" bitfld.long 0x18 18. "EVENT211DETEN,Event(211) Detection Enable" "0,1" bitfld.long 0x18 17. "EVENT210DETEN,Event(210) Detection Enable" "0,1" newline bitfld.long 0x18 16. "EVENT209DETEN,Event(209) Detection Enable" "0,1" bitfld.long 0x18 15. "EVENT208DETEN,Event(208) Detection Enable" "0,1" bitfld.long 0x18 14. "EVENT207DETEN,Event(207) Detection Enable" "0,1" newline bitfld.long 0x18 13. "EVENT206DETEN,Event(206) Detection Enable" "0,1" bitfld.long 0x18 12. "EVENT205DETEN,Event(205) Detection Enable" "0,1" bitfld.long 0x18 11. "EVENT204DETEN,Event(204) Detection Enable" "0,1" newline bitfld.long 0x18 10. "EVENT203DETEN,Event(203) Detection Enable" "0,1" bitfld.long 0x18 9. "EVENT202DETEN,Event(202) Detection Enable" "0,1" bitfld.long 0x18 8. "EVENT201DETEN,Event(201) Detection Enable" "0,1" newline bitfld.long 0x18 7. "EVENT200DETEN,Event(200) Detection Enable" "0,1" bitfld.long 0x18 6. "EVENT199DETEN,Event(199) Detection Enable" "0,1" bitfld.long 0x18 5. "EVENT198DETEN,Event(198) Detection Enable" "0,1" newline bitfld.long 0x18 4. "EVENT197DETEN,Event(197) Detection Enable" "0,1" bitfld.long 0x18 3. "EVENT196DETEN,Event(196) Detection Enable" "0,1" bitfld.long 0x18 2. "EVENT195DETEN,Event(195) Detection Enable" "0,1" newline bitfld.long 0x18 1. "EVENT194DETEN,Event(194) Detection Enable" "0,1" bitfld.long 0x18 0. "EVENT193DETEN,Event(193) Detection Enable" "0,1" line.long 0x1C "CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL8,System event detection enable register 8 (if number of events > 224)" bitfld.long 0x1C 31. "EVENT256DETEN,Event(256) Detection Enable" "0,1" bitfld.long 0x1C 30. "EVENT255DETEN,Event(255) Detection Enable" "0,1" bitfld.long 0x1C 29. "EVENT254DETEN,Event(254) Detection Enable" "0,1" newline bitfld.long 0x1C 28. "EVENT253DETEN,Event(253) Detection Enable" "0,1" bitfld.long 0x1C 27. "EVENT252DETEN,Event(252) Detection Enable" "0,1" bitfld.long 0x1C 26. "EVENT251DETEN,Event(251) Detection Enable" "0,1" newline bitfld.long 0x1C 25. "EVENT250DETEN,Event(250) Detection Enable" "0,1" bitfld.long 0x1C 24. "EVENT249DETEN,Event(249) Detection Enable" "0,1" bitfld.long 0x1C 23. "EVENT248DETEN,Event(248) Detection Enable" "0,1" newline bitfld.long 0x1C 22. "EVENT247DETEN,Event(247) Detection Enable" "0,1" bitfld.long 0x1C 21. "EVENT246DETEN,Event(246) Detection Enable" "0,1" bitfld.long 0x1C 20. "EVENT245DETEN,Event(245) Detection Enable" "0,1" newline bitfld.long 0x1C 19. "EVENT244DETEN,Event(244) Detection Enable" "0,1" bitfld.long 0x1C 18. "EVENT243DETEN,Event(243) Detection Enable" "0,1" bitfld.long 0x1C 17. "EVENT242DETEN,Event(242) Detection Enable" "0,1" newline bitfld.long 0x1C 16. "EVENT241DETEN,Event(241) Detection Enable" "0,1" bitfld.long 0x1C 15. "EVENT240DETEN,Event(240) Detection Enable" "0,1" bitfld.long 0x1C 14. "EVENT239DETEN,Event(239) Detection Enable" "0,1" newline bitfld.long 0x1C 13. "EVENT238DETEN,Event(238) Detection Enable" "0,1" bitfld.long 0x1C 12. "EVENT237DETEN,Event(237) Detection Enable" "0,1" bitfld.long 0x1C 11. "EVENT236DETEN,Event(236) Detection Enable" "0,1" newline bitfld.long 0x1C 10. "EVENT235DETEN,Event(235) Detection Enable" "0,1" bitfld.long 0x1C 9. "EVENT234DETEN,Event(234) Detection Enable" "0,1" bitfld.long 0x1C 8. "EVENT233DETEN,Event(233) Detection Enable" "0,1" newline bitfld.long 0x1C 7. "EVENT232DETEN,Event(232) Detection Enable" "0,1" bitfld.long 0x1C 6. "EVENT231DETEN,Event(231) Detection Enable" "0,1" bitfld.long 0x1C 5. "EVENT230DETEN,Event(230) Detection Enable" "0,1" newline bitfld.long 0x1C 4. "EVENT229DETEN,Event(229) Detection Enable" "0,1" bitfld.long 0x1C 3. "EVENT228DETEN,Event(228) Detection Enable" "0,1" bitfld.long 0x1C 2. "EVENT227DETEN,Event(227) Detection Enable" "0,1" newline bitfld.long 0x1C 1. "EVENT226DETEN,Event(226) Detection Enable" "0,1" bitfld.long 0x1C 0. "EVENT225DETEN,Event(225) Detection Enable" "0,1" line.long 0x20 "CTSET2_WRAP__CFG__CTSET2_CFG_SETMSTID,System Event Master ID" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x20 0.--7. 1. "MASTID,HW Master ID for System Event module. Software may overwrite the value at any time but this is only recommended for scenarios where top-level configuration errors result in a collision between HW master IDs" rgroup.long 0x800++0x7 line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTL,Counter Timer Control" hexmask.long.byte 0x0 26.--31. 1. "NUMSTM,Number of counters that can export via STM" hexmask.long.byte 0x0 18.--25. 1. "NUMINPT,Number of event input signals" hexmask.long.byte 0x0 13.--17. 1. "NUMTIMR,Number of timers in the module" newline hexmask.long.byte 0x0 7.--12. 1. "NUMCNTR,Number of counters in the module" hexmask.long.byte 0x0 3.--6. 1. "REVID,Revision ID of CTSET" bitfld.long 0x0 1. "RESERVED,Reserved returns 0" "0,1" newline bitfld.long 0x0 0. "NUMCOREMD,Indicated the number of mode bus interfaces 0 is 2 CPU buses 1 is 4 buses" "0,1" line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTNUMDBG,Counter Timer Number Debug Event Register" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x4 0.--2. "NUMEVT,Number of input selectors for debug events" "0,1,2,3,4,5,6,7" rgroup.long 0x808++0x3 line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTUSERACCCTL,Counter Timer User Access Control. can only be written in priviledged mode" hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x0 2. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x0 1. "RUSER,Counter functions while system is in Root-User mode" "0,1" newline bitfld.long 0x0 0. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" rgroup.long 0x820++0x13 line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTSTMCNTL,Counter Timer STM Control register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x0 6.--11. 1. "NUMXPORT,The total number of counters designated for export" rbitfld.long 0x0 5. "XPORTACT,Indicates if a frame is currently being written to the STM." "0,1" newline bitfld.long 0x0 4. "CCMPORT,SW control of CCM message export" "0,1" bitfld.long 0x0 3. "CCMAVAIL,CTSET supports CCM export" "0,1" bitfld.long 0x0 2. "CSMXPORT,SW control of CSM message export" "0,1" newline bitfld.long 0x0 1. "SENDOVR,Send overflow data in CSM frame" "0,1" bitfld.long 0x0 0. "ENBL,CTSET STM global enable for counter/timer messages" "0,1" line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTSTMMSTID,Counter Timer STM Master ID register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x4 0.--7. 1. "MASTID,HW Master ID for System Event module" line.long 0x8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTSTMINTVL,Counter Timer STM Interval Register" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.word 0x8 0.--14. 1. "INTERVAL,Counter Timer Periodic export interval" line.long 0xC "CTSET2_WRAP__CFG__CTSET2_CFG_CTSTMSEL0,Counter Timer STM Counter Select Register 0. This Selects Counter 0 to 31" hexmask.long 0xC 0.--31. 1. "COUNTSEL,The individual bit is this field indicate whether the corresponding counter value is included in the CSM message generated via the STM interface" line.long 0x10 "CTSET2_WRAP__CFG__CTSET2_CFG_CTSTMSEL1,Counter Timer STM Counter Select Register 1. This Selects Counter 32 to 63" hexmask.long 0x10 0.--31. 1. "COUNTSEL,The individual bit is this field indicate whether the corresponding counter value is included in the CSM message generated via the STM interface" rgroup.long 0x840++0x3F line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR0,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x0 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR1,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x4 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR2,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x8 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0xC "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR3,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0xC 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x10 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR4,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x10 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x14 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR5,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x14 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x18 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR6,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x18 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x1C "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR7,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x1C 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x20 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR8,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x20 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x24 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR9,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x24 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x28 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR10,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x28 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x2C "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR11,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x2C 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x30 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR12,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x30 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x34 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR13,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x34 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x38 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR14,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x38 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x3C "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR15,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x3C 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" rgroup.long 0x8A0++0x1F line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL0,Timer Interval Register 0. Interval match value for timer 0 in CTSET Timer Interval Register 1. Interval match value for timer 1 in CTSET Timer Interval Register 2. Interval match value for timer 2 in CTSET Timer.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x0 0.--7. 1. "INPSEL,Counter Timer input selection" line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL1,Counter Timer Debug Event Register 1" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x4 0.--7. 1. "INPSEL,Counter Timer input selection" line.long 0x8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL2,Counter Timer Debug Event Register 2" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x8 0.--7. 1. "INPSEL,Counter Timer input selection" line.long 0xC "CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL3,Counter Timer Debug Event Register 3" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0xC 0.--7. 1. "INPSEL,Counter Timer input selection" line.long 0x10 "CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL4,Counter Timer Debug Event Register 4" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x10 0.--7. 1. "INPSEL,Counter Timer input selection" line.long 0x14 "CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL5,Counter Timer Debug Event Register5" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x14 0.--7. 1. "INPSEL,Counter Timer input selection" line.long 0x18 "CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL6,Counter Timer Debug Event Register 6" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x18 0.--7. 1. "INPSEL,Counter Timer input selection" line.long 0x1C "CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL7,Counter Timer Debug Event Register 7" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x1C 0.--7. 1. "INPSEL,Counter Timer input selection" rgroup.long 0x9F0++0x18F line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTGNBL0,Counter Timer Global Enable Register 0. This enables Counter 0 to 31" hexmask.long.byte 0x0 0.--7. 1. "ENABLE,The individual bit is this field enables the corresponding counter. Bits 30 and 31 will be high if global time stamp output interface is enabled" line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTGNBL1,Counter Timer Global Enable Register 1. This enables Counter 32 to 63" hexmask.long.byte 0x4 0.--7. 1. "ENABLE,The individual bit is this field enables the corresponding counter" line.long 0x8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTGRST0,Counter Timer Global Reset Register 0. This resets Counter 0 to 31" hexmask.long.byte 0x8 0.--7. 1. "RESET,The individual bit is this field resets the corresponding counter. These bits are self-clearing once a '1' is written after the counters are reset these bits are cleared. When Global Time Stamp output interface is enabled counter 31 and counter.." line.long 0xC "CTSET2_WRAP__CFG__CTSET2_CFG_CTGRST1,Counter Timer Global Reset Register 0. This resets Counter 32 to 63" hexmask.long.byte 0xC 0.--7. 1. "RESET,The individual bit is this field resets the corresponding counter. These bits are self-clearing once a '1' is written after the counters are reset these bits are cleared." line.long 0x10 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR0,Counter Timer Control Register 0" hexmask.long.byte 0x10 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x10 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x10 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x10 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x10 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x10 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x10 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x10 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x10 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x10 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x10 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x10 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x10 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x10 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x10 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x10 0. "ENBL,Counter enable control" "0,1" line.long 0x14 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR1,Counter Timer Control Register 1" hexmask.long.byte 0x14 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x14 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x14 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x14 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x14 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x14 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x14 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x14 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x14 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x14 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x14 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x14 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x14 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x14 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x14 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x14 0. "ENBL,Counter enable control" "0,1" line.long 0x18 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR2,Counter Timer Control Register 2" hexmask.long.byte 0x18 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x18 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x18 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x18 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x18 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x18 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x18 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x18 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x18 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x18 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x18 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x18 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x18 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x18 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x18 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x18 0. "ENBL,Counter enable control" "0,1" line.long 0x1C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR3,Counter Timer Control Register 3" hexmask.long.byte 0x1C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x1C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x1C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x1C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x1C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x1C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x1C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x1C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x1C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x1C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x1C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x1C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x1C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x1C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x1C 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x1C 0. "ENBL,Counter enable control" "0,1" line.long 0x20 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR4,Counter Timer Control Register 4" hexmask.long.byte 0x20 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x20 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x20 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x20 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x20 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x20 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x20 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x20 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x20 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x20 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x20 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x20 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x20 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x20 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x20 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x20 0. "ENBL,Counter enable control" "0,1" line.long 0x24 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR5,Counter Timer Control Register 5" hexmask.long.byte 0x24 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x24 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x24 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x24 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x24 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x24 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x24 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x24 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x24 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x24 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x24 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x24 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x24 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x24 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x24 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x24 0. "ENBL,Counter enable control" "0,1" line.long 0x28 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR6,Counter Timer Control Register 6" hexmask.long.byte 0x28 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x28 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x28 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x28 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x28 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x28 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x28 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x28 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x28 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x28 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x28 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x28 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x28 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x28 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x28 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x28 0. "ENBL,Counter enable control" "0,1" line.long 0x2C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR7,Counter Timer Control Register 7" hexmask.long.byte 0x2C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x2C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x2C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x2C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x2C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x2C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x2C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x2C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x2C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x2C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x2C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x2C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x2C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x2C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x2C 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x2C 0. "ENBL,Counter enable control" "0,1" line.long 0x30 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR8,Counter Timer Control Register 8" hexmask.long.byte 0x30 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x30 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x30 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x30 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x30 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x30 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x30 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x30 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x30 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x30 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x30 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x30 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x30 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x30 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x30 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x30 0. "ENBL,Counter enable control" "0,1" line.long 0x34 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR9,Counter Timer Control Register 9" hexmask.long.byte 0x34 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x34 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x34 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x34 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x34 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x34 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x34 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x34 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x34 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x34 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x34 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x34 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x34 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x34 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x34 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x34 0. "ENBL,Counter enable control" "0,1" line.long 0x38 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR10,Counter Timer Control Register 10" hexmask.long.byte 0x38 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x38 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x38 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x38 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x38 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x38 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x38 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x38 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x38 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x38 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x38 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x38 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x38 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x38 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x38 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x38 0. "ENBL,Counter enable control" "0,1" line.long 0x3C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR11,Counter Timer Control Register 11" hexmask.long.byte 0x3C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x3C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x3C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x3C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x3C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x3C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x3C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x3C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x3C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x3C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x3C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x3C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x3C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x3C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x3C 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x3C 0. "ENBL,Counter enable control" "0,1" line.long 0x40 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR12,Counter Timer Control Register 12" hexmask.long.byte 0x40 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x40 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x40 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x40 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x40 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x40 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x40 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x40 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x40 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x40 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x40 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x40 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x40 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x40 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x40 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x40 0. "ENBL,Counter enable control" "0,1" line.long 0x44 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR13,Counter Timer Control Register 13" hexmask.long.byte 0x44 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x44 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x44 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x44 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x44 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x44 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x44 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x44 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x44 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x44 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x44 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x44 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x44 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x44 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x44 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x44 0. "ENBL,Counter enable control" "0,1" line.long 0x48 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR14,Counter Timer Control Register 14" hexmask.long.byte 0x48 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x48 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x48 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x48 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x48 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x48 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x48 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x48 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x48 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x48 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x48 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x48 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x48 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x48 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x48 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x48 0. "ENBL,Counter enable control" "0,1" line.long 0x4C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR15,Counter Timer Control Register 15" hexmask.long.byte 0x4C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x4C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x4C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x4C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x4C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x4C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x4C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x4C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x4C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x4C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x4C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x4C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x4C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x4C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x4C 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x4C 0. "ENBL,Counter enable control" "0,1" line.long 0x50 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR16,Counter Timer Control Register 16" hexmask.long.byte 0x50 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x50 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x50 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x50 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x50 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x50 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x50 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x50 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x50 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x50 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x50 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x50 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x50 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x50 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x50 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x50 0. "ENBL,Counter enable control" "0,1" line.long 0x54 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR17,Counter Timer Control Register 17" hexmask.long.byte 0x54 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x54 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x54 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x54 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x54 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x54 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x54 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x54 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x54 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x54 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x54 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x54 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x54 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x54 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x54 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x54 0. "ENBL,Counter enable control" "0,1" line.long 0x58 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR18,Counter Timer Control Register 18" hexmask.long.byte 0x58 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x58 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x58 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x58 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x58 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x58 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x58 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x58 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x58 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x58 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x58 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x58 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x58 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x58 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x58 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x58 0. "ENBL,Counter enable control" "0,1" line.long 0x5C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR19,Counter Timer Control Register 19" hexmask.long.byte 0x5C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x5C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x5C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x5C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x5C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x5C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x5C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x5C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x5C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x5C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x5C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x5C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x5C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x5C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x5C 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x5C 0. "ENBL,Counter enable control" "0,1" line.long 0x60 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR20,Counter Timer Control Register 20" hexmask.long.byte 0x60 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x60 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x60 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x60 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x60 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x60 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x60 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x60 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x60 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x60 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x60 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x60 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x60 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x60 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x60 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x60 0. "ENBL,Counter enable control" "0,1" line.long 0x64 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR21,Counter Timer Control Register 21" hexmask.long.byte 0x64 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x64 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x64 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x64 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x64 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x64 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x64 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x64 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x64 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x64 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x64 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x64 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x64 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x64 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x64 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x64 0. "ENBL,Counter enable control" "0,1" line.long 0x68 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR22,Counter Timer Control Register 22" hexmask.long.byte 0x68 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x68 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x68 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x68 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x68 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x68 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x68 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x68 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x68 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x68 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x68 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x68 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x68 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x68 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x68 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x68 0. "ENBL,Counter enable control" "0,1" line.long 0x6C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR23,Counter Timer Control Register 23" hexmask.long.byte 0x6C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x6C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x6C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x6C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x6C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x6C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x6C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x6C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x6C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x6C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x6C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x6C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x6C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x6C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x6C 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x6C 0. "ENBL,Counter enable control" "0,1" line.long 0x70 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR24,Counter Timer Control Register 24" hexmask.long.byte 0x70 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x70 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x70 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x70 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x70 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x70 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x70 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x70 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x70 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x70 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x70 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x70 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x70 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x70 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x70 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x70 0. "ENBL,Counter enable control" "0,1" line.long 0x74 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR25,Counter Timer Control Register 25" hexmask.long.byte 0x74 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x74 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x74 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x74 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x74 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x74 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x74 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x74 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x74 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x74 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x74 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x74 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x74 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x74 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x74 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x74 0. "ENBL,Counter enable control" "0,1" line.long 0x78 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR26,Counter Timer Control Register 26" hexmask.long.byte 0x78 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x78 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x78 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x78 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x78 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x78 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x78 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x78 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x78 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x78 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x78 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x78 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x78 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x78 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x78 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x78 0. "ENBL,Counter enable control" "0,1" line.long 0x7C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR27,Counter Timer Control Register 27" hexmask.long.byte 0x7C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x7C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x7C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x7C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x7C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x7C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x7C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x7C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x7C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x7C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x7C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x7C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x7C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x7C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x7C 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x7C 0. "ENBL,Counter enable control" "0,1" line.long 0x80 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR28,Counter Timer Control Register 28" hexmask.long.byte 0x80 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x80 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x80 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x80 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x80 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x80 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x80 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x80 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x80 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x80 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x80 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x80 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x80 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x80 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x80 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x80 0. "ENBL,Counter enable control" "0,1" line.long 0x84 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR29,Counter Timer Control Register 29" hexmask.long.byte 0x84 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x84 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x84 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x84 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x84 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x84 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x84 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x84 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x84 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x84 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x84 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x84 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x84 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x84 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x84 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x84 0. "ENBL,Counter enable control" "0,1" line.long 0x88 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR30,Counter Timer Control Register 30" hexmask.long.byte 0x88 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x88 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x88 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x88 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x88 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x88 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x88 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x88 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x88 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x88 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x88 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x88 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x88 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x88 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x88 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x88 0. "ENBL,Counter enable control" "0,1" line.long 0x8C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR31,Counter Timer Control Register 31" hexmask.long.byte 0x8C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x8C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x8C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x8C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x8C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x8C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x8C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x8C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x8C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x8C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x8C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x8C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x8C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x8C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x8C 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x8C 0. "ENBL,Counter enable control" "0,1" line.long 0x90 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN0,Counter/Timer Ownership register 0" bitfld.long 0x90 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0x90 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0x90 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0x90 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x94 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN1,Counter/Timer Ownership register 1" bitfld.long 0x94 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0x94 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0x94 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0x94 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x98 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN2,Counter/Timer Ownership register 2" bitfld.long 0x98 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0x98 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0x98 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0x98 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x9C "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN3,Counter/Timer Ownership register 3" bitfld.long 0x9C 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0x9C 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0x9C 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0x9C 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xA0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN4,Counter/Timer Ownership register 4" bitfld.long 0xA0 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xA0 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xA0 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xA0 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xA4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN5,Counter/Timer Ownership register 5" bitfld.long 0xA4 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xA4 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xA4 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xA4 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xA8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN6,Counter/Timer Ownership register 6" bitfld.long 0xA8 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xA8 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xA8 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xA8 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xAC "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN7,Counter/Timer Ownership register 7" bitfld.long 0xAC 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xAC 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xAC 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xAC 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xB0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN8,Counter/Timer Ownership register 8" bitfld.long 0xB0 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xB0 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xB0 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xB0 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xB4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN9,Counter/Timer Ownership register 9" bitfld.long 0xB4 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xB4 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xB4 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xB4 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xB8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN10,Counter/Timer Ownership register 10" bitfld.long 0xB8 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xB8 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xB8 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xB8 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xBC "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN11,Counter/Timer Ownership register 11" bitfld.long 0xBC 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xBC 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xBC 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xBC 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xC0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN12,Counter/Timer Ownership register 12" bitfld.long 0xC0 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xC0 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xC0 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xC0 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xC4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN13,Counter/Timer Ownership register 13" bitfld.long 0xC4 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xC4 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xC4 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xC4 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xC8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN14,Counter/Timer Ownership register 14" bitfld.long 0xC8 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xC8 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xC8 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xC8 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xCC "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN15,Counter/Timer Ownership register 15" bitfld.long 0xCC 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xCC 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xCC 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xCC 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xD0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN16,Counter/Timer Ownership register 16" bitfld.long 0xD0 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xD0 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xD0 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xD0 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xD4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN17,Counter/Timer Ownership register 17" bitfld.long 0xD4 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xD4 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xD4 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xD4 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xD8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN18,Counter/Timer Ownership register 18" bitfld.long 0xD8 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xD8 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xD8 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xD8 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xDC "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN19,Counter/Timer Ownership register 19" bitfld.long 0xDC 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xDC 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xDC 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xDC 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xE0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN20,Counter/Timer Ownership register 20" bitfld.long 0xE0 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xE0 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xE0 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xE0 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xE4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN21,Counter/Timer Ownership register 21" bitfld.long 0xE4 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xE4 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xE4 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xE4 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xE8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN22,Counter/Timer Ownership register 22" bitfld.long 0xE8 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xE8 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xE8 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xE8 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xEC "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN23,Counter/Timer Ownership register2 3" bitfld.long 0xEC 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xEC 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xEC 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xEC 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xF0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN24,Counter/Timer Ownership register 24" bitfld.long 0xF0 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xF0 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xF0 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xF0 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xF4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN25,Counter/Timer Ownership register 25" bitfld.long 0xF4 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xF4 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xF4 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xF4 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xF8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN26,Counter/Timer Ownership register 26" bitfld.long 0xF8 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xF8 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xF8 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xF8 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xFC "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN27,Counter/Timer Ownership register 27" bitfld.long 0xFC 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xFC 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xFC 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xFC 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x100 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN28,Counter/Timer Ownership register 28" bitfld.long 0x100 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0x100 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0x100 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0x100 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x104 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN29,Counter/Timer Ownership register 29" bitfld.long 0x104 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0x104 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0x104 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0x104 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x108 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN30,Counter/Timer Ownership register 30" bitfld.long 0x108 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0x108 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0x108 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0x108 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x10C "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN31,Counter/Timer Ownership register 31" bitfld.long 0x10C 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0x10C 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0x10C 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0x10C 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x110 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT0,Counter Timer 0 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x110 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x110 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x110 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x110 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x110 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x110 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x110 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x110 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x110 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x114 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT1,Counter Timer 1 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x114 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x114 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x114 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x114 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x114 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x114 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x114 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x114 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x114 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x118 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT2,Counter Timer 2 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x118 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x118 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x118 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x118 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x118 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x118 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x118 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x118 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x118 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x11C "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT3,Counter Timer 3 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x11C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x11C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x11C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x11C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x11C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x11C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x11C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x11C 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x11C 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x120 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT4,Counter Timer 4 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x120 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x120 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x120 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x120 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x120 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x120 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x120 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x120 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x120 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x124 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT5,Counter Timer 5 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x124 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x124 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x124 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x124 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x124 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x124 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x124 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x124 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x124 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x128 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT6,Counter Timer 6 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x128 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x128 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x128 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x128 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x128 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x128 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x128 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x128 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x128 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x12C "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT7,Counter Timer 7 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x12C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x12C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x12C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x12C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x12C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x12C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x12C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x12C 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x12C 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x130 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT8,Counter Timer 8 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x130 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x130 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x130 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x130 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x130 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x130 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x130 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x130 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x130 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x134 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT9,Counter Timer 9 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x134 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x134 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x134 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x134 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x134 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x134 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x134 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x134 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x134 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x138 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT10,Counter Timer 10 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x138 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x138 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x138 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x138 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x138 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x138 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x138 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x138 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x138 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x13C "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT11,Counter Timer 11 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x13C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x13C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x13C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x13C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x13C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x13C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x13C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x13C 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x13C 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x140 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT12,Counter Timer 12 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x140 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x140 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x140 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x140 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x140 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x140 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x140 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x140 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x140 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x144 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT13,Counter Timer 13 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x144 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x144 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x144 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x144 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x144 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x144 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x144 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x144 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x144 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x148 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT14,Counter Timer 14 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x148 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x148 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x148 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x148 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x148 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x148 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x148 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x148 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x148 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x14C "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT15,Counter Timer 15 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x14C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x14C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x14C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x14C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x14C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x14C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x14C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x14C 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x14C 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x150 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT16,Counter Timer 16 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x150 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x150 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x150 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x150 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x150 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x150 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x150 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x150 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x150 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x154 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT17,Counter Timer 17 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x154 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x154 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x154 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x154 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x154 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x154 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x154 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x154 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x154 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x158 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT18,Counter Timer 18 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x158 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x158 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x158 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x158 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x158 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x158 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x158 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x158 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x158 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x15C "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT19,Counter Timer 19 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x15C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x15C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x15C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x15C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x15C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x15C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x15C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x15C 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x15C 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x160 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT20,Counter Timer 20 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x160 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x160 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x160 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x160 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x160 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x160 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x160 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x160 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x160 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x164 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT21,Counter Timer 21 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x164 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x164 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x164 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x164 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x164 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x164 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x164 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x164 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x164 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x168 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT22,Counter Timer 22 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x168 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x168 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x168 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x168 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x168 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x168 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x168 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x168 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x168 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x16C "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT23,Counter Timer 23 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x16C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x16C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x16C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x16C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x16C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x16C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x16C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x16C 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x16C 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x170 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT24,Counter Timer 24 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x170 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x170 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x170 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x170 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x170 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x170 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x170 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x170 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x170 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x174 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT25,Counter Timer 25 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x174 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x174 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x174 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x174 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x174 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x174 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x174 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x174 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x174 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x178 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT26,Counter Timer 26 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x178 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x178 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x178 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x178 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x178 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x178 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x178 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x178 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x178 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x17C "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT27,Counter Timer 27 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x17C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x17C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x17C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x17C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x17C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x17C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x17C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x17C 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x17C 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x180 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT28,Counter Timer 28 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x180 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x180 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x180 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x180 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x180 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x180 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x180 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x180 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x180 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x184 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT29,Counter Timer 29 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x184 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x184 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x184 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x184 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x184 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x184 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x184 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x184 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x184 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x188 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT30,Counter Timer 30 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x188 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x188 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x188 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x188 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x188 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x188 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x188 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x188 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x188 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x18C "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT31,Counter Timer 31 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x18C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x18C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x18C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x18C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x18C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x18C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x18C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x18C 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x18C 0. "FREE,Counter functions while system/core is halted" "0,1" rgroup.long 0xB80++0x7F line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR0,Counter Timer Counter Register 0" hexmask.long 0x0 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR1,Counter Timer Counter Register 1" hexmask.long 0x4 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR2,Counter Timer Counter Register 2" hexmask.long 0x8 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0xC "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR3,Counter Timer Counter Register 3" hexmask.long 0xC 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x10 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR4,Counter Timer Counter Register 4" hexmask.long 0x10 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x14 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR5,Counter Timer Counter Register 5" hexmask.long 0x14 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x18 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR6,Counter Timer Counter Register 6" hexmask.long 0x18 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x1C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR7,Counter Timer Counter Register 7" hexmask.long 0x1C 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x20 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR8,Counter Timer Counter Register 8" hexmask.long 0x20 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x24 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR9,Counter Timer Counter Register 9" hexmask.long 0x24 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x28 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR10,Counter Timer Counter Register 10" hexmask.long 0x28 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x2C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR11,Counter Timer Counter Register 11" hexmask.long 0x2C 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x30 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR12,Counter Timer Counter Register 12" hexmask.long 0x30 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x34 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR13,Counter Timer Counter Register 13" hexmask.long 0x34 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x38 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR14,Counter Timer Counter Register 14" hexmask.long 0x38 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x3C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR15,Counter Timer Counter Register 15" hexmask.long 0x3C 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x40 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR16,Counter Timer Counter Register 16" hexmask.long 0x40 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x44 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR17,Counter Timer Counter Register 17" hexmask.long 0x44 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x48 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR18,Counter Timer Counter Register 18" hexmask.long 0x48 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x4C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR19,Counter Timer Counter Register 19" hexmask.long 0x4C 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x50 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR20,Counter Timer Counter Register 20" hexmask.long 0x50 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x54 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR21,Counter Timer Counter Register 21" hexmask.long 0x54 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x58 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR22,Counter Timer Counter Register 22" hexmask.long 0x58 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x5C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR23,Counter Timer Counter Register 23" hexmask.long 0x5C 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x60 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR24,Counter Timer Counter Register 24" hexmask.long 0x60 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x64 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR25,Counter Timer Counter Register 25" hexmask.long 0x64 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x68 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR26,Counter Timer Counter Register 26" hexmask.long 0x68 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x6C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR27,Counter Timer Counter Register 27" hexmask.long 0x6C 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x70 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR28,Counter Timer Counter Register 28" hexmask.long 0x70 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x74 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR29,Counter Timer Counter Register 29" hexmask.long 0x74 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x78 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR30,Counter Timer Counter Register 30" hexmask.long 0x78 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x7C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR31,Counter Timer Counter Register 31" hexmask.long 0x7C 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." rgroup.long 0xC00++0x13 line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_CT_EOI,Counter Timer EOI Register. This register is the End of Interrupt used by SW to signal HW that an interrupt event service is complete and an interrupt can be rearmed. This register exists only if NUMTIMR > 0" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x0 0. "EOI,EOI value" "0,1" line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTIRQSTAT_RAW,Counter Timer IRQSTATUS RAW Register. This register indicates the raw status of the interrupt. It can be written by SW for testing. This register exists only if NUMTIMR > 0" hexmask.long 0x4 0.--31. 1. "TIM_INTN_IRQ,IRQSTATUS_RAW value. The individual bits is this field correspond to individual interrupts generated for each timer associated with Counter Timer Control Register (CTCRn : INT)." line.long 0x8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTIRQSTAT,Counter Timer IRQSTATUS Register. This bit clears the interrupt event. SW can also read this bit to indicate that the interrupt is active and enabled. This register exists only if NUMTIMR > 0" hexmask.long 0x8 0.--31. 1. "TIM_INTN_IE,IRQSTATUS value. The individual bits is this field correspond to individual interrupts generated for each timer associated with Counter Timer Control Register (CTCRn : INT)." line.long 0xC "CTSET2_WRAP__CFG__CTSET2_CFG_CTIRQENABLE_SET,Counter Timer IRQENABLE_SET Register. This register is to enable generation of Interrupt Event used by SW. This register exists only if NUMTIMR > 0" hexmask.long 0xC 0.--31. 1. "TIM_INTN_IES,IRQSET value. This bit sets the enable of the interrupt event. SW can also read this bit to determine if the interrupt is enabled. The individual bits is this field correspond to individual interrupts generated for each timer associated with.." line.long 0x10 "CTSET2_WRAP__CFG__CTSET2_CFG_CTIRQENABLE_CLR,Counter Timer IRQENABLE_CLR Register. This register is to disable generation of Interrupt Event used by SW. This register exists only if NUMTIMR > 0" hexmask.long 0x10 0.--31. 1. "TIM_INTN_IEC,IRQCLR value. This bit clears the enable of the interrupt event. SW can also read this bit to determine if the interrupt is enabled. The individual bits is this field correspond to individual interrupts generated for each timer associated.." rgroup.long 0x1800++0x7 line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_STPTCR,STP Trace Control Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED3,Reserved returns 0" rbitfld.long 0x0 24. "MOD_FIFOFULL,STPMI2ATB internal MID packet fifo is full" "0,1" rbitfld.long 0x0 23. "DATA_FIFOFULL,STPMI2ATB internal Data packet fifo is full" "0,1" newline hexmask.long.tbyte 0x0 6.--22. 1. "RESERVED2,Reserved returns 0" bitfld.long 0x0 5. "COMPEN,Compression of Data enable" "0,1" rbitfld.long 0x0 3.--4. "RESERVED1,Reserved returns 0" "0,1,2,3" newline rbitfld.long 0x0 2. "SYNCEN,The value 1 indicates STPASYNC is supported" "0,1" bitfld.long 0x0 1. "TSEN,Timestamp Enable. This bit is static and should not be changed dynamically. This should be changed before client is enabled." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved returns 0" "0,1" line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_STPTID,STP Trace ID Register" hexmask.long 0x4 7.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x4 0.--6. 1. "TRACEID,Trace ID value. Software may overwrite the value at any time but this is only recommended for scenarios where top-level configuration errors result in a collision between HW master IDs" rgroup.long 0x1810++0x7 line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_STPASYNC,STP Synchronization Control Register" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x0 12. "EXPMODE,Exponent mode A value of 1 sets count to 2 to the Nth where Nth is ((bits 11 : 8)+12). A value of 0 sets Count to N (bits 11 : 0)" "0,1" hexmask.long.word 0x0 0.--11. 1. "COUNT,The number of bytes between Synchronization packets" line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_STPFFCR,STP Flush Control Register" hexmask.long 0x4 6.--31. 1. "RESERVED1,Reserved returns 0" bitfld.long 0x4 5. "FORCEFLUSH,Write a 1 to force a flush automatically clears after the operation is complete" "0,1" rbitfld.long 0x4 2.--4. "RESERVED,Reserved returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 1. "ASYNCPE,Async Priority Enable. 0 indicates ASYNC packet priority is lower than trace. 1 indicates priority escalates on second synchronization request" "0,1" bitfld.long 0x4 0. "AUTOFLUSH,Auto flush enable. When set on every complete data (ATDATA : WIDTH) in the fifo written data is exported out when ATREADY is asserted. This should be written before client IP enabled" "0,1" rgroup.long 0x1818++0x3 line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_STPFEAT1,STP Features 1 Register" hexmask.long.byte 0x0 27.--31. 1. "STP_RTLVER,RTL Version. Reset each time major or minor version is updated" bitfld.long 0x0 24.--26. "STP_MAJVER,Functional Major Version. This is the first version of STPMI2ATB" "0,1,2,3,4,5,6,7" bitfld.long 0x0 22.--23. "STP_CUSTVER,Custom Version (not used)" "0,1,2,3" newline hexmask.long.byte 0x0 17.--21. 1. "STP_MINVER,Functional Minor Version" hexmask.long.word 0x0 8.--16. 1. "RESERVED,Reserved returns 0" bitfld.long 0x0 4.--6. "VERSION,STP2.0 Time Stamp Value of 011 indicates Natural binary timestamp a value of 100 indicates gray binary timestamps" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "PROT,Protocol Revision. Value of 0001 indicates STP 2.0" tree.end tree "DMPAC0_DMPAC_REGS_DMPAC_REGS_CFG_IP_MMRS (DMPAC0_DMPAC_REGS_DMPAC_REGS_CFG_IP_MMRS)" base ad:0xF400000 rgroup.long 0x0++0x3 line.long 0x0 "DMPAC_REGS__DMPAC_REGS_CFG__IP_MMRS_PID,DMPAC PID" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and new scheme. Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU indicator DSPS ==> 0x0 WTBU ==> 0x1 Processors ==> 0x2" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family. If there is no level of software compatibility a new FUNC number and hence PID should be assigned." hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version. R as described in PDR with additional clarifications and definitions below. Must be easily ECO-able or controlled during fabrication. Ideally through a top level metal mask or e-fuse. This number is maintained/owned by IP design.." bitfld.long 0x0 8.--10. "MAJOR,Major Revision. X as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. X is part of IP numbering X.Y.R.Z. X changes ONLY when: (1) There is a major feature addition. An.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library (CSL) / Drivers. 0 if non-custom." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision. Y as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. Y changes ONLY when: (1) Features are scaled (up or down). Flexibility exists in that this.." rgroup.long 0x18++0x7 line.long 0x0 "DMPAC_REGS__DMPAC_REGS_CFG__IP_MMRS_ENABLE,DMPAC Enable" bitfld.long 0x0 2. "SDE_EN,Stereo Enable" "0,1" bitfld.long 0x0 1. "DOF_EN,Optical Flow Enable" "0,1" bitfld.long 0x0 0. "DMPAC_EN,DMPAC Enable" "0,1" line.long 0x4 "DMPAC_REGS__DMPAC_REGS_CFG__IP_MMRS_CG_ENABLE_OVERRIDE,Register to override the root clock gating done in DMPAC to reduce power.By default these bits are 0. it should be set to 1 only when we encounter some silicon bug." bitfld.long 0x4 0. "CG_OVERRIDE,clock gating override" "0,1" tree.end tree "DMPAC0_DOF_0_PAR" tree "DMPAC0_DOF_0_PAR_DOF_CFG_VP_MEM_MMRRAM_VBUSP_MMR_RAM (DMPAC0_DOF_0_PAR_DOF_CFG_VP_MEM_MMRRAM_VBUSP_MMR_RAM)" base ad:0xF4C0000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_PSE_MEM_RAM,pse_mem_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0x2000++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_MEM0_RAM,srb_mem0_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0x4000++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_MEM1_RAM,srb_mem1_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0x6000++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_MEM2_RAM,srb_mem2_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0x8000++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_MEM3_RAM,srb_mem3_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0xA000++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_MEM4_RAM,srb_mem4_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0xC000++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_MEM5_RAM,srb_mem5_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0xE000++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_MEM6_RAM,srb_mem6_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0x10000++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_MEM7_RAM,srb_mem7_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0x12000++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_MEM8_RAM,srb_mem8_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0x14000++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_MEM9_RAM,srb_mem9_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0x16000++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_MEM10_RAM,srb_mem10_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0x18000++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_MEM11_RAM,srb_mem11_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0x1A000++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_MEM12_RAM,srb_mem12_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0x1C000++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_MEM13_RAM,srb_mem13_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0x1E000++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_MEM14_RAM,srb_mem14_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0x20000++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_MEM15_RAM,srb_mem15_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0x22000++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_CSRAMGRD_RAM,csRamGrd_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long.word 0x0 20.--31. 1. "RSVD,Always read as 0. Writes have no effect." hexmask.long.tbyte 0x0 0.--19. 1. "DATA,Data read from RAM" rgroup.long 0x24000++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_CSRAMIIR_RAM,csRamIir_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0x28000++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_MFRAM0_RAM,mfRam0_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0x2C000++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_MFRAM1_RAM,mfRam1_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." tree.end tree "DMPAC0_DOF_0_PAR_DOF_CFG_VP_MMR_VBUSP_DOFCORE (DMPAC0_DOF_0_PAR_DOF_CFG_VP_MMR_VBUSP_DOFCORE)" base ad:0xF480000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_PID,DOF PID" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and new scheme. Spare bit to encode future schemes" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU indicator DSPS ==> 0x0 WTBU ==> 0x1 Processors ==> 0x2" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family. If there is no level of software compatibility a new FUNC number and hence PID should be assigned." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version. R as described in PDR with additional clarifications and definitions below. Must be easily ECO-able or controlled during fabrication. Ideally through a top level metal mask or e-fuse. This number is maintained/owned by IP design.." newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision. X as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. X is part of IP numbering X.Y.R.Z. X changes ONLY when: (1) There is a major feature addition. An.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library (CSL) / Drivers. 0 if non-custom." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision. Y as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. Y changes ONLY when: (1) Features are scaled (up or down). Flexibility exists in that this.." rgroup.long 0x4++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_dofcr,Controls DOF operations" bitfld.long 0x0 25. "REF_CT_TYPE_CFG,Census transform type for reference image. 0: 24 bits generated for census transform by using a 5x5 neighborhood around the pixel. 1: 32 bits generated for census transform by using a 7x7 neighborhood around the pixel where only 8 pixels.." "0,1" newline bitfld.long 0x0 24. "CUR_CT_TYPE_CFG,Census transform type for current image. 0: 24 bits generated for census transform by using a 5x5 neighborhood around the pixel. 1: 32 bits generated for census transform by using a 7x7 neighborhood around the pixel where only 8 pixels.." "0,1" newline bitfld.long 0x0 18. "SOFSPARSEEN_CFG,sparse optical flow enable bit. Set to 0x1 to enable sparse optical flow processing." "0,1" newline bitfld.long 0x0 17. "MF_EN_CFG,Median filter enable bit. Set to 0x1 to enable median filter processing." "0,1" newline bitfld.long 0x0 16. "LK_CS_EN_CFG,LK refinement and confidence score generation enable bit. Set to 0x1 to enable LK and CS processing." "0,1" newline bitfld.long 0x0 4. "DL_EN_CFG,Delayed Left Predictor Enable bit. Set to 0x1 to enable use of delayed left predictor during the DOF processing." "0,1" newline bitfld.long 0x0 3. "TP_EN_CFG,Temporal Predictor Enable bit. Set to 0x1 to enable use of temporal predictor during the DOF processing." "0,1" newline bitfld.long 0x0 2. "PYL_EN_CFG,Pyramidal Top Left Predictor Enable bit. Set to 0x1 to enable use of pyramidal top left predictor during DOF processing." "0,1" newline bitfld.long 0x0 1. "PYC_EN_CFG,Pyramidal Top Co-located Predictor Enable bit. Set to 0x1 to enable use of pyramidal top colocated predictor during DOF processing." "0,1" newline bitfld.long 0x0 0. "DOF_EN_CFG,DOF Enable. Set to 0x1 to enable DOF engine." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_dofstat,Provides status info" hexmask.long.word 0x0 10.--19. 1. "CURPAXADDRX_STS,Current Paxel Address X co-ordinate. Provides address of 2x2 paxel currently being processed." newline hexmask.long.word 0x0 1.--9. 1. "CURPAXADDRY_STS,Current Paxel Address Y co-ordinate. Provides address of 2x2 paxel currently being processed." newline bitfld.long 0x0 0. "DOFACT_STS,DOF Active Status. When read as 0x1 indicates DOF engine is in active state processing flow vector for the frame." "0,1" rgroup.long 0x10++0xB line.long 0x0 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_dofres,Set up frame width. height" hexmask.long.word 0x0 16.--26. 1. "HEIGHT_CFG,Height of frame (in pixel) to be processed by Optical Flow engine. 1024 pixel max and 16 pixels min. Refer to algorithm parameter section for restrictions." newline hexmask.long.word 0x0 0.--11. 1. "WIDTH_CFG,Width of frame (in pixel) to be processed by Optical Flow engine. 2048 pixel max and 32 pixels min. Refer to algorithm parameter section for restrictions." line.long 0x4 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_dofsr,Setup horizontal and vertical search range." hexmask.long.byte 0x4 24.--29. 1. "VSR_N_CFG,Negative or Upward direction Vertical Search Range in pixels." newline hexmask.long.byte 0x4 16.--21. 1. "VSR_P_CFG,Positive or Downward direction Vertical Search Range in pixels." newline hexmask.long.byte 0x4 0.--7. 1. "HSR_CFG,Horizontal Search Range in pixels in both the directions." line.long 0x8 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_sof,Controls sparse optical flow output processing" hexmask.long.word 0x8 0.--11. 1. "MAX_OUTPUT_COUNT_PER_LINE_CFG,Maximum number of MV output per line in case of sparse optical flow processing" rgroup.long 0x20++0xB line.long 0x0 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_cfgwbase,Current Frame GW Base address in SL2" hexmask.long.tbyte 0x0 0.--19. 1. "ADDR_CFG,SL2 base byte address. Should be aligned to 64 bytes" line.long 0x4 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_cfgwwidth,CFGW width. Max 2048 pix" hexmask.long.word 0x4 0.--12. 1. "WIDTH_CFG,Width of Frame Growing Window in bytes. Should be multiple of 64 bytes" line.long 0x8 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_cfgwheight,CFGW Height. Max 32 rows" hexmask.long.byte 0x8 0.--4. 1. "HEIGHT_CFG,Height of Frame Growing Window. Max 31 rows." rgroup.long 0x30++0xB line.long 0x0 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_rfgwbase,Reference Frame GW Base address in SL2" hexmask.long.tbyte 0x0 0.--19. 1. "ADDR_CFG,SL2 base byte address. Should be aligned to 64 bytes" line.long 0x4 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_rfgwwidth,RFGW width. Max 2048 pix" hexmask.long.word 0x4 0.--12. 1. "WIDTH_CFG,Width of Frame Growing Window in bytes. Should be multiple of 64 bytes" line.long 0x8 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_rfgwheight,RFGW height. Max 256 rows" hexmask.long.byte 0x8 0.--7. 1. "HEIGHT_CFG,Height of Frame Growing Window. Max 255 rows." rgroup.long 0x40++0xF line.long 0x0 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_spbufbase,Base address in SL2" bitfld.long 0x0 24.--26. "DEPTH_CFG,Depth of SL2 buffer" "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x0 0.--19. 1. "ADDR_CFG,SL2 base byte address. Should be aligned to 64 bytes" line.long 0x4 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_tpbufbase,Base address in SL2" bitfld.long 0x4 24.--26. "DEPTH_CFG,Depth of SL2 buffer" "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x4 0.--19. 1. "ADDR_CFG,SL2 base byte address. Should be aligned to 64 bytes" line.long 0x8 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_bmbufbase,Base address in SL2" bitfld.long 0x8 24.--26. "DEPTH_CFG,Depth of SL2 buffer" "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x8 0.--19. 1. "ADDR_CFG,SL2 base byte address. Should be aligned to 64 bytes" line.long 0xC "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_fvbufbase,Base address in SL2" bitfld.long 0xC 24.--26. "DEPTH_CFG,Depth of SL2 buffer" "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xC 0.--19. 1. "ADDR_CFG,SL2 base byte address. Should be aligned to 64 bytes" rgroup.long 0x60++0x7 line.long 0x0 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_msfr,5b unsigned integer for Step Search cost function" hexmask.long.byte 0x0 0.--4. 1. "MSF_CFG,Motion smoothness factor" line.long 0x4 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_cscfgr,Feature filter parameters. confidence score scaling factor setup" hexmask.long.word 0x4 16.--25. 1. "CS_GAIN_CFG,Multiplier factor (Gain) for the combined confidence score. The sum of individual scores from different decision trees are multiplied by CS Gain before scaling to final 4bit (16 levels) confidence score value." newline hexmask.long.byte 0x4 0.--7. 1. "IIR_ALPHA_CFG,Coefficient for IIR filter used for smoothing horizontal flow vector gradient. The usage can be illustrated as: SmoothU(i j)= [ U(i j)*alpha + SmoothU(i-1 j)*beta + round ]>>8 where beta = 256-alpha round = 128" rgroup.long 0x70++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_psa_ctrl,Control register for calculating 32b CRC signature on flow vector output" bitfld.long 0x0 0. "PSA_EN_CFG,Enable calculating 32b CRC signature on 32b flow vector and confidence score output" "0,1" rgroup.long 0x74++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_psa_signature,32b CRC signature calculated on flow vector output" hexmask.long 0x0 0.--31. 1. "CRC_STS,32b CRC signature value as calculated on 32b flow vector and confidence score output" rgroup.long 0x300++0x3 line.long 0x0 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_dofcshist,Confidence Score Histogram Number of pixels having confidence score value of Bin Index" hexmask.long.tbyte 0x0 0.--23. 1. "BIN_STS,Number of pixels having confidence score value of Bin Index" rgroup.long 0x80++0x1F line.long 0x0 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_th0,Confidence Score Decision Tree[a] Threshold 0. First Branch. There are a total of 16 trees and each tree has 8 programed CFG parameters. Each tree is essentially a 4-1 selector MUX outputs one of 4 MMR.." hexmask.long.word 0x0 0.--15. 1. "THRESHOLD_CFG,Threshold 0 value. If Feature(Index0).ge.Thresh0 then 2ndBranch11 else 2ndBranch10" line.long 0x4 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_th10,Confidence Score Decision Tree[a] Threshold 10. 2nd Branch. only evaluated if failing 1st Branch" hexmask.long.word 0x4 0.--15. 1. "THRESHOLD_CFG,Threshold 10 value. If Feature(Index10).ge.Thresh10 then Weight01 else Weight00" line.long 0x8 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_th11,Confidence Score Decision Tree[a] Threshold 11. 2nd Branch. only evaluated if passing 1st Branch" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD_CFG,Threshold 11 value. If Feature(Index11).ge.Thresh11 then Weight11 else Weight10" line.long 0xC "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_wt00,Confidence Score Decision Tree[a] Weight 00" hexmask.long.word 0xC 0.--15. 1. "WEIGHT_CFG,Weight 00 value for Confidence Score Decision Tree" line.long 0x10 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_wt01,Confidence Score Decision Tree[a] Weight 01" hexmask.long.word 0x10 0.--15. 1. "WEIGHT_CFG,Weight 01 value for Confidence Score Decision Tree" line.long 0x14 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_wt10,Confidence Score Decision Tree Tree[a] Weight 10" hexmask.long.word 0x14 0.--15. 1. "WEIGHT_CFG,Weight 10 value for Confidence Score Decision Tree" line.long 0x18 "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_wt11,Confidence Score Decision Tree[a] Weight 11" hexmask.long.word 0x18 0.--15. 1. "WEIGHT_CFG,Weight 11 value for Confidence Score Decision Tree" line.long 0x1C "PAR_DOF__CFG_VP__MMR__MMR_VBUSP__DOFCORE_REG_fids,Decision Tree n=0-to-15 Feature Indices. Selects one of 8 data values to compare. 0:Winner Cost 1:Texture 2:Flow Grad U 3:Flow Grad V 4:Aggregated Winner Cost 5:Aggregated Texture 6:Aggregated Flow Grad.." bitfld.long 0x1C 6.--8. "INDEX2_CFG,Specifies the index of a feature (in the confidence score feature vector) to be used as the 3rd feature in the decision tree traversal 0: Winner Cost 1: Texture 2: Flow Grad U 3: Flow Grad V 4: Aggregated Winner Cost 5:.." "0: Winner Cost,1: Texture,2: Flow Grad U,3: Flow Grad V,4: Aggregated Winner Cost,5: Aggregated Texture,6: Aggregated Flow Grad U,7: Aggregated Flow Grad V" newline bitfld.long 0x1C 3.--5. "INDEX1_CFG,Specifies the index of a feature (in the confidence score feature vector) to be used as the 2nd feature in the decision tree traversal 0: Winner Cost 1: Texture 2: Flow Grad U 3: Flow Grad V 4: Aggregated Winner Cost 5:.." "0: Winner Cost,1: Texture,2: Flow Grad U,3: Flow Grad V,4: Aggregated Winner Cost,5: Aggregated Texture,6: Aggregated Flow Grad U,7: Aggregated Flow Grad V" newline bitfld.long 0x1C 0.--2. "INDEX0_CFG,Specifies the index of a feature (in the confidence score feature vector) to be used as the 1st feature in the decision tree traversal 0: Winner Cost 1: Texture 2: Flow Grad U 3: Flow Grad V 4: Aggregated Winner Cost 5:.." "0: Winner Cost,1: Texture,2: Flow Grad U,3: Flow Grad V,4: Aggregated Winner Cost,5: Aggregated Texture,6: Aggregated Flow Grad U,7: Aggregated Flow Grad V" tree.end tree.end tree "DMPAC0_DRU_0_DRU" tree "DMPAC0_DRU_0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU (DMPAC0_DRU_0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU)" base ad:0xF600000 rgroup.quad 0x0++0xF line.quad 0x0 "DRU_UTC_DMPAC0__DRU_MMR_CFG__DRU_DRU_dru_pid,Peripheral ID Register" hexmask.quad.long 0x0 0.--31. 1. "REVISION,PID Revision" line.quad 0x8 "DRU_UTC_DMPAC0__DRU_MMR_CFG__DRU_DRU_dru_capabilities,DRU Capabilities: Lists the capabilities of the channel for TR TYPE and formatting functions" hexmask.quad.byte 0x8 43.--46. 1. "SECTR,Maximum second TR function that is supported" hexmask.quad.byte 0x8 39.--42. 1. "DFMT,Maximum data reformatting function that is supported" hexmask.quad.byte 0x8 35.--38. 1. "ELTYPE,Maximum element type value that is supported" bitfld.quad 0x8 32.--34. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x8 20.--31. 1. "RSVD_CONF_SPEC,Reserved for Configuration Specific Features. This implementation has no configuration specific features." bitfld.quad 0x8 19. "GLOBAL_TRIG,Global Triggers 0 and 1 are supported" "0,1" bitfld.quad 0x8 18. "LOCAL_TRIG,Dedicated Local Trigger is supported" "0,1" bitfld.quad 0x8 17. "EOL,EOL Field is supported" "0,1" newline bitfld.quad 0x8 16. "TRSTATIC,STATIC Field is supported" "0,1" bitfld.quad 0x8 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.quad 0x8 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.quad 0x8 13. "TYPE13,Type 13 TR is supported" "0,1" newline bitfld.quad 0x8 12. "TYPE12,Type 12 TR is supported" "0,1" bitfld.quad 0x8 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.quad 0x8 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.quad 0x8 9. "TYPE9,Type 9 TR is supported" "0,1" newline bitfld.quad 0x8 8. "TYPE8,Type 8 TR is supported" "0,1" bitfld.quad 0x8 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.quad 0x8 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.quad 0x8 5. "TYPE5,Type 5 TR is supported" "0,1" newline bitfld.quad 0x8 4. "TYPE4,Type 4 TR is supported" "0,1" bitfld.quad 0x8 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.quad 0x8 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.quad 0x8 1. "TYPE1,Type 1 TR is supported" "0,1" newline bitfld.quad 0x8 0. "TYPE0,Type 0 TR is supported" "0,1" tree.end tree "DMPAC0_DRU_0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CAUSE (DMPAC0_DRU_0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CAUSE)" base ad:0xF6E0000 rgroup.quad 0x0++0x7 line.quad 0x0 "DRU_UTC_DMPAC0__DRU_MMR_CFG__DRU_DRU_CAUSE_cause,Error Register cause for channels 0 to 15" bitfld.quad 0x0 63. "R_ERR15,Masked error bit for Tx channel n+15" "0,1" bitfld.quad 0x0 62. "R_PEND15,Masked completion ring pending bit for Rx channel n+15" "0,1" bitfld.quad 0x0 61. "T_ERR15,Masked error bit for Tx channel n+15" "0,1" bitfld.quad 0x0 60. "T_PEND15,Masked completion ring pending bit for Tx channel n+15" "0,1" bitfld.quad 0x0 59. "R_ERR14,Masked error bit for Tx channel n+14" "0,1" bitfld.quad 0x0 58. "R_PEND14,Masked completion ring pending bit for Rx channel n+14" "0,1" bitfld.quad 0x0 57. "T_ERR14,Masked error bit for Tx channel n+14" "0,1" newline bitfld.quad 0x0 56. "T_PEND14,Masked completion ring pending bit for Tx channel n+14" "0,1" bitfld.quad 0x0 55. "R_ERR13,Masked error bit for Tx channel n+13" "0,1" bitfld.quad 0x0 54. "R_PEND13,Masked completion ring pending bit for Rx channel n+13" "0,1" bitfld.quad 0x0 53. "T_ERR13,Masked error bit for Tx channel n+13" "0,1" bitfld.quad 0x0 52. "T_PEND13,Masked completion ring pending bit for Tx channel n+13" "0,1" bitfld.quad 0x0 51. "R_ERR12,Masked error bit for Tx channel n+12" "0,1" bitfld.quad 0x0 50. "R_PEND12,Masked completion ring pending bit for Rx channel n+12" "0,1" newline bitfld.quad 0x0 49. "T_ERR12,Masked error bit for Tx channel n+12" "0,1" bitfld.quad 0x0 48. "T_PEND12,Masked completion ring pending bit for Tx channel n+12" "0,1" bitfld.quad 0x0 47. "R_ERR11,Masked error bit for Tx channel n+11" "0,1" bitfld.quad 0x0 46. "R_PEND11,Masked completion ring pending bit for Rx channel n+11" "0,1" bitfld.quad 0x0 45. "T_ERR11,Masked error bit for Tx channel n+11" "0,1" bitfld.quad 0x0 44. "T_PEND11,Masked completion ring pending bit for Tx channel n+11" "0,1" bitfld.quad 0x0 43. "R_ERR10,Masked error bit for Tx channel n+10" "0,1" newline bitfld.quad 0x0 42. "R_PEND10,Masked completion ring pending bit for Rx channel n+10" "0,1" bitfld.quad 0x0 41. "T_ERR10,Masked error bit for Tx channel n+10" "0,1" bitfld.quad 0x0 40. "T_PEND10,Masked completion ring pending bit for Tx channel n+10" "0,1" bitfld.quad 0x0 39. "R_ERR9,Masked error bit for Tx channel n+9" "0,1" bitfld.quad 0x0 38. "R_PEND9,Masked completion ring pending bit for Rx channel n+9" "0,1" bitfld.quad 0x0 37. "T_ERR9,Masked error bit for Tx channel n+9" "0,1" bitfld.quad 0x0 36. "T_PEND9,Masked completion ring pending bit for Tx channel n+9" "0,1" newline bitfld.quad 0x0 35. "R_ERR8,Masked error bit for Tx channel n+8" "0,1" bitfld.quad 0x0 34. "R_PEND8,Masked completion ring pending bit for Rx channel n+8" "0,1" bitfld.quad 0x0 33. "T_ERR8,Masked error bit for Tx channel n+8" "0,1" bitfld.quad 0x0 32. "T_PEND8,Masked completion ring pending bit for Tx channel n+8" "0,1" bitfld.quad 0x0 31. "R_ERR7,Masked error bit for Tx channel n+7" "0,1" bitfld.quad 0x0 30. "R_PEND7,Masked completion ring pending bit for Rx channel n+7" "0,1" bitfld.quad 0x0 29. "T_ERR7,Masked error bit for Tx channel n+7" "0,1" newline bitfld.quad 0x0 28. "T_PEND7,Masked completion ring pending bit for Tx channel n+7" "0,1" bitfld.quad 0x0 27. "R_ERR6,Masked error bit for Tx channel n+6" "0,1" bitfld.quad 0x0 26. "R_PEND6,Masked completion ring pending bit for Rx channel n+6" "0,1" bitfld.quad 0x0 25. "T_ERR6,Masked error bit for Tx channel n+6" "0,1" bitfld.quad 0x0 24. "T_PEND6,Masked completion ring pending bit for Tx channel n+6" "0,1" bitfld.quad 0x0 23. "R_ERR5,Masked error bit for Tx channel n+5" "0,1" bitfld.quad 0x0 22. "R_PEND5,Masked completion ring pending bit for Rx channel n+5" "0,1" newline bitfld.quad 0x0 21. "T_ERR5,Masked error bit for Tx channel n+5" "0,1" bitfld.quad 0x0 20. "T_PEND5,Masked completion ring pending bit for Tx channel n+5" "0,1" bitfld.quad 0x0 19. "R_ERR4,Masked error bit for Tx channel n+4" "0,1" bitfld.quad 0x0 18. "R_PEND4,Masked completion ring pending bit for Rx channel n+4" "0,1" bitfld.quad 0x0 17. "T_ERR4,Masked error bit for Tx channel n+4" "0,1" bitfld.quad 0x0 16. "T_PEND4,Masked completion ring pending bit for Tx channel n+4" "0,1" bitfld.quad 0x0 15. "R_ERR3,Masked error bit for Tx channel n+3" "0,1" newline bitfld.quad 0x0 14. "R_PEND3,Masked completion ring pending bit for Rx channel n+3" "0,1" bitfld.quad 0x0 13. "T_ERR3,Masked error bit for Tx channel n+3" "0,1" bitfld.quad 0x0 12. "T_PEND3,Masked completion ring pending bit for Tx channel n+3" "0,1" bitfld.quad 0x0 11. "R_ERR2,Masked error bit for Tx channel n+2" "0,1" bitfld.quad 0x0 10. "R_PEND2,Masked completion ring pending bit for Rx channel n+2" "0,1" bitfld.quad 0x0 9. "T_ERR2,Masked error bit for Tx channel n+2" "0,1" bitfld.quad 0x0 8. "T_PEND2,Masked completion ring pending bit for Tx channel n+2" "0,1" newline bitfld.quad 0x0 7. "R_ERR1,Masked error bit for Tx channel n+1" "0,1" bitfld.quad 0x0 6. "R_PEND1,Masked completion ring pending bit for Rx channel n+1" "0,1" bitfld.quad 0x0 5. "T_ERR1,Masked error bit for Tx channel n+1" "0,1" bitfld.quad 0x0 4. "T_PEND1,Masked completion ring pending bit for Tx channel n+1" "0,1" bitfld.quad 0x0 3. "R_ERR0,Masked error bit for Tx channel n" "0,1" bitfld.quad 0x0 2. "R_PEND0,Masked completion ring pending bit for Rx channel n" "0,1" bitfld.quad 0x0 1. "T_ERR0,Masked error bit for Tx channel n" "0,1" newline bitfld.quad 0x0 0. "T_PEND0,Masked completion ring pending bit for Tx channel n" "0,1" tree.end tree "DMPAC0_DRU_0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CHNRT (DMPAC0_DRU_0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CHNRT)" base ad:0xF640000 rgroup.quad 0x0++0x7 line.quad 0x0 "DRU_UTC_DMPAC0__DRU_MMR_CFG__DRU_DRU_CHNRT_cfg,Channel Configuration Register. The Channel Configuration Register is used to initialize static mode settings for the DMA Channel. The register may only be written when the chanel is disable in the ch_enable.." bitfld.quad 0x0 31. "PAUSE_ON_ERR,Pause on Error. This field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW to.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." bitfld.quad 0x0 19. "CHAN_TYPE_OWNER,This field controls how the TR is received by the UTC. If it is 0 then the SUBMISSION registers must be written to submit it. If it is a 1 then the TR will be received through PSIL." "0,1" newline rbitfld.quad 0x0 16.--18. "CHAN_TYPE,This field states the TR type that is being used it along with CHAN_TYPE_OWNER field make up the 4 bit CHAN_TYPE for a KS3 DMA UTC. The value of this is all zeroes. To reflect that the UTC DRU only does TRs through pass by value mechanisms." "0,1,2,3,4,5,6,7" rgroup.quad 0x20++0x7 line.quad 0x0 "DRU_UTC_DMPAC0__DRU_MMR_CFG__DRU_DRU_CHNRT_choes0,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set.." hexmask.quad.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated." rgroup.quad 0x60++0x7 line.quad 0x0 "DRU_UTC_DMPAC0__DRU_MMR_CFG__DRU_DRU_CHNRT_chst_sched,Channel Static Scheduler Config Register" bitfld.quad 0x0 0.--2. "QUEUE,This is the queue number that is written" "0,1,2,3,4,5,6,7" tree.end tree "DMPAC0_DRU_0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CHRT (DMPAC0_DRU_0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CHRT)" base ad:0xF660000 rgroup.quad 0x0++0xF line.quad 0x0 "DRU_UTC_DMPAC0__DRU_MMR_CFG__DRU_DRU_CHRT_chrt_ctl,The channel realtime control register contains real-time cotrol and status information for the DMA Channel. The fields in this regsiter can be changed while the channel is in operation." bitfld.quad 0x0 31. "ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared.." newline bitfld.quad 0x0 30. "TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" newline bitfld.quad 0x0 29. "PAUSE,Channel pause: Setting this bit will request the channel to pause processing at the next packet boundary. This is a more graceful method of halting processing than disabling the channel as it will not allow any current packets to underflow." "0,1" line.quad 0x8 "DRU_UTC_DMPAC0__DRU_MMR_CFG__DRU_DRU_CHRT_chrt_swtrig,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way." bitfld.quad 0x8 2. "LOCAL_TRIGGER0,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel. This will trigger LOCAL Event" "0,1" newline bitfld.quad 0x8 1. "GLOBAL_TRIGGER1,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel. This will trigger Global Event 1" "0,1" newline bitfld.quad 0x8 0. "GLOBAL_TRIGGER0,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel. This will trigger Global Event 0" "0,1" rgroup.quad 0x10++0xF line.quad 0x0 "DRU_UTC_DMPAC0__DRU_MMR_CFG__DRU_DRU_CHRT_chrt_status_det,The channel status details" hexmask.quad.byte 0x0 8.--15. 1. "CMD_ID,The last cmd_id given to the write queue" newline hexmask.quad.byte 0x0 4.--7. 1. "INFO,The info of the error that was received" newline hexmask.quad.byte 0x0 0.--3. 1. "STATUS_TYPE,The type of error that was received" line.quad 0x8 "DRU_UTC_DMPAC0__DRU_MMR_CFG__DRU_DRU_CHRT_chrt_status_cnt,The channel count details" hexmask.quad.word 0x8 48.--63. 1. "ICNT3,The last icnt3 given to the write queue" newline hexmask.quad.word 0x8 32.--47. 1. "ICNT2,The last icnt2 given to the write queue" newline hexmask.quad.word 0x8 16.--31. 1. "ICNT1,The last icnt1 given to the write queue" newline hexmask.quad.word 0x8 0.--15. 1. "ICNT0,The last icnt0 given to the write queue" tree.end tree "DMPAC0_DRU_0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_QUEUE (DMPAC0_DRU_0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_QUEUE)" base ad:0xF608000 rgroup.quad 0x0++0x7 line.quad 0x0 "DRU_UTC_DMPAC0__DRU_MMR_CFG__DRU_DRU_QUEUE_cfg,Configuration Register for Queue 0" hexmask.quad.long 0x0 32.--63. 1. "RSVD,Reserved." hexmask.quad.byte 0x0 24.--31. 1. "REARB_WAIT,This is the number of commands that will be sent by other queues before allowing the queue to arbitrate again for the right to send commands. This is only started when a queue exhausted its consecutive trans count." hexmask.quad.byte 0x0 16.--23. 1. "CONSECUTIVE_TRANS,This is the number of consecutive transactions that will be sent before allowing another queue of equal level to arbitrate to send commands. This is the maximum number of commands that it can send. If the queue has any delays such as.." newline bitfld.quad 0x0 8.--10. "QOS,This configures the QOS for QUEUE0. This should only be set for fixed priority queues and the lower queue should have the lower QoS." "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x0 4.--7. 1. "ORDERID,This configures the orderid for QUEUE0." bitfld.quad 0x0 0.--2. "PRI,This configures the priority for QUEUE0. This will be the priority that will be presented on the External bus for all commands from this queue." "0,1,2,3,4,5,6,7" rgroup.quad 0x40++0x7 line.quad 0x0 "DRU_UTC_DMPAC0__DRU_MMR_CFG__DRU_DRU_QUEUE_status,Status Register for Queue 0" hexmask.quad.word 0x0 27.--35. 1. "RD_TOTAL,This is the channel that the read half is currently working on." hexmask.quad.word 0x0 18.--26. 1. "RD_TOP,This is the channel that the read half is currently working on." hexmask.quad.word 0x0 9.--17. 1. "WR_TOTAL,This is the channel that the read half is currently working on." newline hexmask.quad.word 0x0 0.--8. 1. "WR_TOP,This is the channel that the write half is currently working on." tree.end tree "DMPAC0_DRU_0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_SET (DMPAC0_DRU_0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_SET)" base ad:0xF604000 rgroup.quad 0x0++0x7 line.quad 0x0 "DRU_UTC_DMPAC0__DRU_MMR_CFG__DRU_DRU_SET_dru_shared_evt_set,DRU Shared Event Set Register" bitfld.quad 0x0 0. "PROT_ERR,Set the Prot Error event" "0,1" rgroup.quad 0x40++0x7 line.quad 0x0 "DRU_UTC_DMPAC0__DRU_MMR_CFG__DRU_DRU_SET_dru_comp_evt_set0,DRU Completion Event Set Register" bitfld.quad 0x0 31. "COMP_EVT31,Set the Completion Event for channel 31" "0,1" bitfld.quad 0x0 30. "COMP_EVT30,Set the Completion Event for channel 30" "0,1" bitfld.quad 0x0 29. "COMP_EVT29,Set the Completion Event for channel 29" "0,1" bitfld.quad 0x0 28. "COMP_EVT28,Set the Completion Event for channel 28" "0,1" bitfld.quad 0x0 27. "COMP_EVT27,Set the Completion Event for channel 27" "0,1" bitfld.quad 0x0 26. "COMP_EVT26,Set the Completion Event for channel 26" "0,1" newline bitfld.quad 0x0 25. "COMP_EVT25,Set the Completion Event for channel 25" "0,1" bitfld.quad 0x0 24. "COMP_EVT24,Set the Completion Event for channel 24" "0,1" bitfld.quad 0x0 23. "COMP_EVT23,Set the Completion Event for channel 23" "0,1" bitfld.quad 0x0 22. "COMP_EVT22,Set the Completion Event for channel 22" "0,1" bitfld.quad 0x0 21. "COMP_EVT21,Set the Completion Event for channel 21" "0,1" bitfld.quad 0x0 20. "COMP_EVT20,Set the Completion Event for channel 20" "0,1" newline bitfld.quad 0x0 19. "COMP_EVT19,Set the Completion Event for channel 19" "0,1" bitfld.quad 0x0 18. "COMP_EVT18,Set the Completion Event for channel 18" "0,1" bitfld.quad 0x0 17. "COMP_EVT17,Set the Completion Event for channel 17" "0,1" bitfld.quad 0x0 16. "COMP_EVT16,Set the Completion Event for channel 16" "0,1" bitfld.quad 0x0 15. "COMP_EVT15,Set the Completion Event for channel 15" "0,1" bitfld.quad 0x0 14. "COMP_EVT14,Set the Completion Event for channel 14" "0,1" newline bitfld.quad 0x0 13. "COMP_EVT13,Set the Completion Event for channel 13" "0,1" bitfld.quad 0x0 12. "COMP_EVT12,Set the Completion Event for channel 12" "0,1" bitfld.quad 0x0 11. "COMP_EVT11,Set the Completion Event for channel 11" "0,1" bitfld.quad 0x0 10. "COMP_EVT10,Set the Completion Event for channel 10" "0,1" bitfld.quad 0x0 9. "COMP_EVT9,Set the Completion Event for channel 9" "0,1" bitfld.quad 0x0 8. "COMP_EVT8,Set the Completion Event for channel 8" "0,1" newline bitfld.quad 0x0 7. "COMP_EVT7,Set the Completion Event for channel 7" "0,1" bitfld.quad 0x0 6. "COMP_EVT6,Set the Completion Event for channel 6" "0,1" bitfld.quad 0x0 5. "COMP_EVT5,Set the Completion Event for channel 5" "0,1" bitfld.quad 0x0 4. "COMP_EVT4,Set the Completion Event for channel 4" "0,1" bitfld.quad 0x0 3. "COMP_EVT3,Set the Completion Event for channel 3" "0,1" bitfld.quad 0x0 2. "COMP_EVT2,Set the Completion Event for channel 2" "0,1" newline bitfld.quad 0x0 1. "COMP_EVT1,Set the Completion Event for channel 1" "0,1" bitfld.quad 0x0 0. "COMP_EVT0,Set the Completion Event for channel 0" "0,1" rgroup.quad 0x80++0x7 line.quad 0x0 "DRU_UTC_DMPAC0__DRU_MMR_CFG__DRU_DRU_SET_dru_err_evt_set0,DRU Error Event Set Register" bitfld.quad 0x0 31. "ERR_EVT31,Set the Error Event for channel 31" "0,1" bitfld.quad 0x0 30. "ERR_EVT30,Set the Error Event for channel 30" "0,1" bitfld.quad 0x0 29. "ERR_EVT29,Set the Error Event for channel 29" "0,1" bitfld.quad 0x0 28. "ERR_EVT28,Set the Error Event for channel 28" "0,1" bitfld.quad 0x0 27. "ERR_EVT27,Set the Error Event for channel 27" "0,1" bitfld.quad 0x0 26. "ERR_EVT26,Set the Error Event for channel 26" "0,1" newline bitfld.quad 0x0 25. "ERR_EVT25,Set the Error Event for channel 25" "0,1" bitfld.quad 0x0 24. "ERR_EVT24,Set the Error Event for channel 24" "0,1" bitfld.quad 0x0 23. "ERR_EVT23,Set the Error Event for channel 23" "0,1" bitfld.quad 0x0 22. "ERR_EVT22,Set the Error Event for channel 22" "0,1" bitfld.quad 0x0 21. "ERR_EVT21,Set the Error Event for channel 21" "0,1" bitfld.quad 0x0 20. "ERR_EVT20,Set the Error Event for channel 20" "0,1" newline bitfld.quad 0x0 19. "ERR_EVT19,Set the Error Event for channel 19" "0,1" bitfld.quad 0x0 18. "ERR_EVT18,Set the Error Event for channel 18" "0,1" bitfld.quad 0x0 17. "ERR_EVT17,Set the Error Event for channel 17" "0,1" bitfld.quad 0x0 16. "ERR_EVT16,Set the Error Event for channel 16" "0,1" bitfld.quad 0x0 15. "ERR_EVT15,Set the Error Event for channel 15" "0,1" bitfld.quad 0x0 14. "ERR_EVT14,Set the Error Event for channel 14" "0,1" newline bitfld.quad 0x0 13. "ERR_EVT13,Set the Error Event for channel 13" "0,1" bitfld.quad 0x0 12. "ERR_EVT12,Set the Error Event for channel 12" "0,1" bitfld.quad 0x0 11. "ERR_EVT11,Set the Error Event for channel 11" "0,1" bitfld.quad 0x0 10. "ERR_EVT10,Set the Error Event for channel 10" "0,1" bitfld.quad 0x0 9. "ERR_EVT9,Set the Error Event for channel 9" "0,1" bitfld.quad 0x0 8. "ERR_EVT8,Set the Error Event for channel 8" "0,1" newline bitfld.quad 0x0 7. "ERR_EVT7,Set the Error Event for channel 7" "0,1" bitfld.quad 0x0 6. "ERR_EVT6,Set the Error Event for channel 6" "0,1" bitfld.quad 0x0 5. "ERR_EVT5,Set the Error Event for channel 5" "0,1" bitfld.quad 0x0 4. "ERR_EVT4,Set the Error Event for channel 4" "0,1" bitfld.quad 0x0 3. "ERR_EVT3,Set the Error Event for channel 3" "0,1" bitfld.quad 0x0 2. "ERR_EVT2,Set the Error Event for channel 2" "0,1" newline bitfld.quad 0x0 1. "ERR_EVT1,Set the Error Event for channel 1" "0,1" bitfld.quad 0x0 0. "ERR_EVT0,Set the Error Event for channel 0" "0,1" rgroup.quad 0xC0++0x7 line.quad 0x0 "DRU_UTC_DMPAC0__DRU_MMR_CFG__DRU_DRU_SET_dru_local_evt_set0,DRU Local Event Set Register" bitfld.quad 0x0 31. "COMP_EVT31,Set the Local Event for channel 31" "0,1" bitfld.quad 0x0 30. "COMP_EVT30,Set the Local Event for channel 30" "0,1" bitfld.quad 0x0 29. "COMP_EVT29,Set the Local Event for channel 29" "0,1" bitfld.quad 0x0 28. "COMP_EVT28,Set the Local Event for channel 28" "0,1" bitfld.quad 0x0 27. "COMP_EVT27,Set the Local Event for channel 27" "0,1" bitfld.quad 0x0 26. "COMP_EVT26,Set the Local Event for channel 26" "0,1" newline bitfld.quad 0x0 25. "COMP_EVT25,Set the Local Event for channel 25" "0,1" bitfld.quad 0x0 24. "COMP_EVT24,Set the Local Event for channel 24" "0,1" bitfld.quad 0x0 23. "COMP_EVT23,Set the Local Event for channel 23" "0,1" bitfld.quad 0x0 22. "COMP_EVT22,Set the Local Event for channel 22" "0,1" bitfld.quad 0x0 21. "COMP_EVT21,Set the Local Event for channel 21" "0,1" bitfld.quad 0x0 20. "COMP_EVT20,Set the Local Event for channel 20" "0,1" newline bitfld.quad 0x0 19. "COMP_EVT19,Set the Local Event for channel 19" "0,1" bitfld.quad 0x0 18. "COMP_EVT18,Set the Local Event for channel 18" "0,1" bitfld.quad 0x0 17. "COMP_EVT17,Set the Local Event for channel 17" "0,1" bitfld.quad 0x0 16. "COMP_EVT16,Set the Local Event for channel 16" "0,1" bitfld.quad 0x0 15. "COMP_EVT15,Set the Local Event for channel 15" "0,1" bitfld.quad 0x0 14. "COMP_EVT14,Set the Local Event for channel 14" "0,1" newline bitfld.quad 0x0 13. "COMP_EVT13,Set the Local Event for channel 13" "0,1" bitfld.quad 0x0 12. "COMP_EVT12,Set the Local Event for channel 12" "0,1" bitfld.quad 0x0 11. "COMP_EVT11,Set the Local Event for channel 11" "0,1" bitfld.quad 0x0 10. "COMP_EVT10,Set the Local Event for channel 10" "0,1" bitfld.quad 0x0 9. "COMP_EVT9,Set the Local Event for channel 9" "0,1" bitfld.quad 0x0 8. "COMP_EVT8,Set the Local Event for channel 8" "0,1" newline bitfld.quad 0x0 7. "COMP_EVT7,Set the Local Event for channel 7" "0,1" bitfld.quad 0x0 6. "COMP_EVT6,Set the Local Event for channel 6" "0,1" bitfld.quad 0x0 5. "COMP_EVT5,Set the Local Event for channel 5" "0,1" bitfld.quad 0x0 4. "COMP_EVT4,Set the Local Event for channel 4" "0,1" bitfld.quad 0x0 3. "COMP_EVT3,Set the Local Event for channel 3" "0,1" bitfld.quad 0x0 2. "COMP_EVT2,Set the Local Event for channel 2" "0,1" newline bitfld.quad 0x0 1. "COMP_EVT1,Set the Local Event for channel 1" "0,1" bitfld.quad 0x0 0. "COMP_EVT0,Set the Local Event for channel 0" "0,1" tree.end tree.end tree "DMPAC0_ECC_AGGR_ECC_AGGR (DMPAC0_ECC_AGGR_ECC_AGGR)" base ad:0x2A6A000 rgroup.long 0x0++0x3 line.long 0x0 "KSDW_ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "KSDW_ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "KSDW_ECC_AGGR__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "KSDW_ECC_AGGR__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "KSDW_ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "KSDW_ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 6. "DRU_PSI_EDC_PEND,Interrupt Pending Status for dru_psi_edc_pend" "0,1" bitfld.long 0x4 5. "DRU_ENG_EDC_PEND,Interrupt Pending Status for dru_eng_edc_pend" "0,1" newline bitfld.long 0x4 4. "DRU_QUEUE_BUFFER2_ECC_PEND,Interrupt Pending Status for dru_queue_buffer2_ecc_pend" "0,1" bitfld.long 0x4 3. "DRU_QUEUE_BUFFER1_ECC_PEND,Interrupt Pending Status for dru_queue_buffer1_ecc_pend" "0,1" newline bitfld.long 0x4 2. "DRU_STATE_BUFFER0_ECC_PEND,Interrupt Pending Status for dru_state_buffer0_ecc_pend" "0,1" bitfld.long 0x4 1. "DRU_QUEUE_BUFFER0_ECC_PEND,Interrupt Pending Status for dru_queue_buffer0_ecc_pend" "0,1" newline bitfld.long 0x4 0. "TPRAM_DRU_RESPONSE_BUFFER0_ECC_PEND,Interrupt Pending Status for tpram_dru_response_buffer0_ecc_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "KSDW_ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 6. "DRU_PSI_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_psi_edc_pend" "0,1" bitfld.long 0x0 5. "DRU_ENG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_eng_edc_pend" "0,1" newline bitfld.long 0x0 4. "DRU_QUEUE_BUFFER2_ECC_ENABLE_SET,Interrupt Enable Set Register for dru_queue_buffer2_ecc_pend" "0,1" bitfld.long 0x0 3. "DRU_QUEUE_BUFFER1_ECC_ENABLE_SET,Interrupt Enable Set Register for dru_queue_buffer1_ecc_pend" "0,1" newline bitfld.long 0x0 2. "DRU_STATE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for dru_state_buffer0_ecc_pend" "0,1" bitfld.long 0x0 1. "DRU_QUEUE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for dru_queue_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 0. "TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for tpram_dru_response_buffer0_ecc_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "KSDW_ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 6. "DRU_PSI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_psi_edc_pend" "0,1" bitfld.long 0x0 5. "DRU_ENG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_eng_edc_pend" "0,1" newline bitfld.long 0x0 4. "DRU_QUEUE_BUFFER2_ECC_ENABLE_CLR,Interrupt Enable Clear Register for dru_queue_buffer2_ecc_pend" "0,1" bitfld.long 0x0 3. "DRU_QUEUE_BUFFER1_ECC_ENABLE_CLR,Interrupt Enable Clear Register for dru_queue_buffer1_ecc_pend" "0,1" newline bitfld.long 0x0 2. "DRU_STATE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for dru_state_buffer0_ecc_pend" "0,1" bitfld.long 0x0 1. "DRU_QUEUE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for dru_queue_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 0. "TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for tpram_dru_response_buffer0_ecc_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "KSDW_ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "KSDW_ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 6. "DRU_PSI_EDC_PEND,Interrupt Pending Status for dru_psi_edc_pend" "0,1" bitfld.long 0x4 5. "DRU_ENG_EDC_PEND,Interrupt Pending Status for dru_eng_edc_pend" "0,1" newline bitfld.long 0x4 4. "DRU_QUEUE_BUFFER2_ECC_PEND,Interrupt Pending Status for dru_queue_buffer2_ecc_pend" "0,1" bitfld.long 0x4 3. "DRU_QUEUE_BUFFER1_ECC_PEND,Interrupt Pending Status for dru_queue_buffer1_ecc_pend" "0,1" newline bitfld.long 0x4 2. "DRU_STATE_BUFFER0_ECC_PEND,Interrupt Pending Status for dru_state_buffer0_ecc_pend" "0,1" bitfld.long 0x4 1. "DRU_QUEUE_BUFFER0_ECC_PEND,Interrupt Pending Status for dru_queue_buffer0_ecc_pend" "0,1" newline bitfld.long 0x4 0. "TPRAM_DRU_RESPONSE_BUFFER0_ECC_PEND,Interrupt Pending Status for tpram_dru_response_buffer0_ecc_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "KSDW_ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 6. "DRU_PSI_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_psi_edc_pend" "0,1" bitfld.long 0x0 5. "DRU_ENG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_eng_edc_pend" "0,1" newline bitfld.long 0x0 4. "DRU_QUEUE_BUFFER2_ECC_ENABLE_SET,Interrupt Enable Set Register for dru_queue_buffer2_ecc_pend" "0,1" bitfld.long 0x0 3. "DRU_QUEUE_BUFFER1_ECC_ENABLE_SET,Interrupt Enable Set Register for dru_queue_buffer1_ecc_pend" "0,1" newline bitfld.long 0x0 2. "DRU_STATE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for dru_state_buffer0_ecc_pend" "0,1" bitfld.long 0x0 1. "DRU_QUEUE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for dru_queue_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 0. "TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for tpram_dru_response_buffer0_ecc_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "KSDW_ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 6. "DRU_PSI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_psi_edc_pend" "0,1" bitfld.long 0x0 5. "DRU_ENG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_eng_edc_pend" "0,1" newline bitfld.long 0x0 4. "DRU_QUEUE_BUFFER2_ECC_ENABLE_CLR,Interrupt Enable Clear Register for dru_queue_buffer2_ecc_pend" "0,1" bitfld.long 0x0 3. "DRU_QUEUE_BUFFER1_ECC_ENABLE_CLR,Interrupt Enable Clear Register for dru_queue_buffer1_ecc_pend" "0,1" newline bitfld.long 0x0 2. "DRU_STATE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for dru_state_buffer0_ecc_pend" "0,1" bitfld.long 0x0 1. "DRU_QUEUE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for dru_queue_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 0. "TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for tpram_dru_response_buffer0_ecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "KSDW_ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "KSDW_ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "KSDW_ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "KSDW_ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "DMPAC0_FOCO" tree "DMPAC0_FOCO_0_DMPAC" tree "DMPAC0_FOCO_0_DMPAC_FOCO_0_CFG_SLV_DMPAC_FOCO_CORE_FOCO_REGS_CFG_IP_MMRS (DMPAC0_FOCO_0_DMPAC_FOCO_0_CFG_SLV_DMPAC_FOCO_CORE_FOCO_REGS_CFG_IP_MMRS)" base ad:0xF424000 rgroup.long 0x0++0x7 line.long 0x0 "DMPAC_FOCO_0__CFG_SLV__DMPAC_FOCO_CORE__FOCO_REGS_CFG__IP_MMRS_CH_CTRL,Defines parameters that control the format conversion for input-output channel pair." hexmask.long.word 0x0 16.--31. 1. "MASK,16b mask value that will be and-ed with the result" hexmask.long.byte 0x0 12.--15. 1. "ROUND,Unsigned Rounding value that will be added" bitfld.long 0x0 8. "DIR,Shift direction - left or right. 0 -> Right 1 -> Left" "0: Right 1,?" bitfld.long 0x0 5.--7. "SHIFT_M1,Amount of bit shift minus 1. Valid values 0 to 7 meaning shift of 1 to 8. For no shift configure SHIFT_EN to 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "SHIFT_EN,Enable for shifting. 0 --> No shift 1 --> Shift determined by SHIFT_M1" "0: No shift 1,?" bitfld.long 0x0 0. "CH_EN,Enable format conversion channel" "0,1" line.long 0x4 "DMPAC_FOCO_0__CFG_SLV__DMPAC_FOCO_CORE__FOCO_REGS_CFG__IP_MMRS_CH_COUNT,Defines count values for pre/post load and functional operation for the format conversion for input-output channel pair." hexmask.long.word 0x4 16.--31. 1. "TRIG,Defines the number of FOCO module operations (HTS starts/dones) for which the actual format conversion happens after PRELOAD number of FOCO module operations. This number cannot be 0 for an active channel" hexmask.long.byte 0x4 8.--15. 1. "POSTLOAD,Defines the number of FOCO module operations (HTS starts/dones) that would be skipped after PRELOAD + TRIG number of FOCO module operations" hexmask.long.byte 0x4 0.--7. 1. "PRELOAD,Defines the number of FOCO module operations (HTS starts/dones) that would be skipped after HTS init" tree.end tree "DMPAC0_FOCO_0_DMPAC_FOCO_0_CFG_SLV_VPAC_FOCO_LSE_CFG_VP (DMPAC0_FOCO_0_DMPAC_FOCO_0_CFG_SLV_VPAC_FOCO_LSE_CFG_VP)" base ad:0xF424200 rgroup.long 0x0++0x3 line.long 0x0 "DMPAC_FOCO_0__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_status_param,The STATUS_PARAM register returns the LSE compile configuration parameters." bitfld.long 0x0 30.--31. "BYPASS_CH,Number of available input channel selection for loopback mode" "0,1,2,3" newline bitfld.long 0x0 29. "OUT_SKIP_EN,Output Auto-Skip Enable" "0,1" newline bitfld.long 0x0 28. "CORE_OUT_2D,1D or 2D output addressing mode(2D if 1)" "0,1" newline hexmask.long.byte 0x0 23.--27. 1. "CORE_OUT_DW,Core Output Channel Data Width" newline bitfld.long 0x0 22. "LINE_SKIP_EN,Source Line Inc by 2 Supported (if 1)" "0,1" newline bitfld.long 0x0 21. "BIT_AOFFSET,Source nibble offset address Supported (if 1)" "0,1" newline bitfld.long 0x0 20. "HV_INSERT,H/VBLANK Insertion Supported (if 1)" "0,1" newline bitfld.long 0x0 17.--19. "PIX_MX_HT,Core_Input Pixel Matrix Height" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 12.--16. 1. "CORE_DW,Core Input Data Bus Width" newline bitfld.long 0x0 10.--11. "SL2_OUT_H3A_CH,Number of SL2 H3A Output Channels" "0,1,2,3" newline hexmask.long.byte 0x0 6.--9. 1. "SL2_OUT_CH,Number of SL2 Output Channels" newline bitfld.long 0x0 3.--5. "SL2_IN_CH_THR,Number of Input Channels per thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "VPORT_THR,Number of VPORT input enabled" "0,1" newline bitfld.long 0x0 0.--1. "NTHR,Number of threads supported" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "DMPAC_FOCO_0__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_status_error,The STATUS_ERROR register returns the LSE error status." hexmask.long.byte 0x0 8.--14. 1. "VM_WR_ERR,VBUSM I/F Last Write Error Status [14:11] Write Channel Number [10:8] VBUSM write error status" newline hexmask.long.byte 0x0 0.--4. 1. "VM_RD_ERR,VBUSM I/F Last Read Error Status [4:3] Read Channel Number [2:0] VBUSM read error status" rgroup.long 0x8++0x3 line.long 0x0 "DMPAC_FOCO_0__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_status_idle_mode,The STATUS_IDLE_MODE register returns IDLE status of LSE VBUSM port and in/output channels - 0: IDLE 1: ACTIVE" hexmask.long.byte 0x0 12.--15. 1. "LSE_OUT_CHAN,Output Channel[3:0] Status" newline hexmask.long.byte 0x0 4.--7. 1. "LSE_IN_CHAN,Input Channel[3:0] Status" newline bitfld.long 0x0 1. "VM_WR_PORT,SL2 vbusm I/F Write Port Status" "0,1" newline bitfld.long 0x0 0. "VM_RD_PORT,SL2 vbusm I/F Read Port Status" "0,1" rgroup.long 0xC++0x3 line.long 0x0 "DMPAC_FOCO_0__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_cfg_lse,The CFG_LSE register configures the LSE general hardware modes." bitfld.long 0x0 8. "PSA_EN,Test mode Output Channel Signature Generation Enable 0: Disable (default) 1: Enable When enabled LSE generates a unique CRC signature for each output channel's frame data at frame completion." "0: Disable,1: Enable When enabled" newline bitfld.long 0x0 4. "VM_ARB_FIXED_MODE,VBUSM Arbitration Fixed Mode select 0: Round-Robin Arbitration (default) 1: Fixed-mode Arbitration" "0: Round-Robin Arbitration,1: Fixed-mode Arbitration" rgroup.long 0x140++0x3 line.long 0x0 "DMPAC_FOCO_0__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_psa_signature,The PSA_SIGNATURE register returns the captured PSA signature value of the last frame data of output channel [a]." hexmask.long 0x0 0.--31. 1. "VALUE,32-bit CRC signature value" rgroup.long 0x1E0++0x3 line.long 0x0 "DMPAC_FOCO_0__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_dbg,The DBG register returns the current status of internal FSM - TI internal use only." hexmask.long 0x0 0.--31. 1. "STATUS,Debug status" rgroup.long 0x10++0x3 line.long 0x0 "DMPAC_FOCO_0__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_cfg,The SRC_CFG register configures the input channels for the processing thread" bitfld.long 0x0 7. "SRC_LN_INC_2,Source Line address Increment by 2 enable 0: Disable 1: Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 4. "PIX_FMT_ALIGN,Input Pixel Container Alignment 0: LSB-aligned 1: MSB-aligned" "0: LSB-aligned,1: MSB-aligned" newline bitfld.long 0x0 2.--3. "PIX_FMT_CNTRSZ,Input Pixel Container Size Sel 0: 8-bit 1: 12-bit 2: 16-bit 3: reserved Input pixel container size must be same or larger than input pixel width." "?,?,?,3: reserved Input pixel container size must be same.." newline bitfld.long 0x0 0.--1. "PIX_FMT_PW,Input Pixel Width Sel 0: 8-bit 1: 12-bit 2: 14-bit 3: 16-bit The width defines the bit-depth of the pixel data to be extracted from the pixel container." "0,1,2,3" rgroup.long 0x18++0xB line.long 0x0 "DMPAC_FOCO_0__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_frame_size,The SRC_FRAME_SIZE register configures the frame size of all input buffers for the processing thread ." hexmask.long.word 0x0 16.--28. 1. "HEIGHT,SL2 - Source Buffer Height (number of lines)" newline hexmask.long.word 0x0 0.--12. 1. "WIDTH,SL2 - Source Buffer Width (number of pixels)" line.long 0x4 "DMPAC_FOCO_0__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_buf_attr,The SRC_BUF_ATTR register configures the common attributes of all SL2 source buffers for the processing thread ." hexmask.long.word 0x4 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)" newline hexmask.long.word 0x4 6.--15. 1. "BUF_STRIDE,Buffer Stride Size [15:6] (64 byte multiple) stride size" newline hexmask.long.byte 0x4 0.--5. 1. "BUF_STRIDE_6_LSB,Buffer Stride Size [5:0] - 6 LSB bits of buffer stride size should always be 0. Writes have no effect. Always read as 0" line.long 0x8 "DMPAC_FOCO_0__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_buf_ba,The SRC_BUF_BA[b] register configures the base address of the SL2 source buffer [b] for the processing thread ." bitfld.long 0x8 31. "ENABLE,Input Buffer Enable 0: Disable 1: Enable When the processing thread is enabled at least one of the input buffer must be enabled" "0: Disable,1: Enable When the processing thread is enabled" newline hexmask.long.tbyte 0x8 6.--23. 1. "ADDR,Base Address[23:6] - (64 Byte aligned) byte address" newline hexmask.long.byte 0x8 0.--5. 1. "ADDR_6_LSB,Base Address[5:0] - 6 LSB bits of address should always be 0. Writes have no effect. Always read as 0" rgroup.long 0x50++0x7 line.long 0x0 "DMPAC_FOCO_0__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_buf_cfg,The DST_BUF_CFG register configures the output buffer channel ." rbitfld.long 0x0 31. "CH_DISABLED,Channel Disable Status (read-only) 0: (Default) Chanel is enabled for Y UV or YUV422 data transfer to SL2 memory. All configurations associated with this DST_BUF[a] are valid. 1: Channel is disabled for SL2 data transfer (because the.." "?,1: Channel is disabled for SL2 data transfer" newline bitfld.long 0x0 29. "YUV422_INTLV_ORDER,YUV422 Interleaving Order Selection 0: UYVY 1: YUYV Only Applicable if this output channel is YUV422 output capable LUMA channel. Otherwise setting has no effect." "0: UYVY 1: YUYV Only Applicable if this output..,?" newline bitfld.long 0x0 28. "YUV422_OUT_EN,YUV422 Interleaved Output Merge Enable 0: Disable 1: Enable When enabled this channel interleaves data from the associated chroma data output channel to output YUV422 interleaved data to the SL2 memory. Only Applicable if this output.." "0: Disable,1: Enable When enabled" newline bitfld.long 0x0 4. "PIX_FMT_ALIGN,Output Pixel Container Alignment 0: LSB-aligned 1: MSB-aligned" "0: LSB-aligned,1: MSB-aligned" newline bitfld.long 0x0 2.--3. "PIX_FMT_CNTRSZ,Output Pixel Container Size Sel 0: 8-bit 1: 12-bit 2: 16-bit 3: reserved Output pixel container size must be same or larger than output pixel width. If yuv422_out_en is set pix_fmt_cntrsz must be 0." "?,?,?,3: reserved Output pixel container size must be.." newline bitfld.long 0x0 0.--1. "PIX_FMT_PW,Output Pixel Width Sel 0: 8-bit 1: 12-bit 2: reserved 3: 16-bit The width defines the bit-depth of the pixel data to be stored in the pixel container." "?,?,2: reserved,?" line.long 0x4 "DMPAC_FOCO_0__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_buf_attr0,The DST_BUF_ATTR0 register configures the attributes of the output SL2 buffer ." hexmask.long.word 0x4 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)" newline hexmask.long.word 0x4 6.--15. 1. "BUF_STRIDE,Buffer Stride Size [15:6] (64 byte multiple) stride size" newline hexmask.long.byte 0x4 0.--5. 1. "BUF_STRIDE_6_LSB,Buffer Stride Size [5:0] - 6 LSB bits of buffer stride size should always be 0. Writes have no effect. Always read as 0" rgroup.long 0x5C++0x3 line.long 0x0 "DMPAC_FOCO_0__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_buf_ba,The DST_BUF_BA register configures the base address of the output SL2 circular buffer ." bitfld.long 0x0 31. "ENABLE,Output Channel Enable 0: Disable 1: Enable" "0: Disable,1: Enable" newline hexmask.long.tbyte 0x0 6.--23. 1. "ADDR,Base Address[23:6] - (64 Byte aligned) byte address" newline hexmask.long.byte 0x0 0.--5. 1. "ADDR_6_LSB,Base Address[5:0] - 6 LSB bits of address should always be 0. Writes have no effect. Always read as 0" tree.end tree.end tree "DMPAC0_FOCO_1_DMPAC" tree "DMPAC0_FOCO_1_DMPAC_FOCO_1_CFG_SLV_DMPAC_FOCO_CORE_FOCO_REGS_CFG_IP_MMRS (DMPAC0_FOCO_1_DMPAC_FOCO_1_CFG_SLV_DMPAC_FOCO_CORE_FOCO_REGS_CFG_IP_MMRS)" base ad:0xF428000 rgroup.long 0x0++0x7 line.long 0x0 "DMPAC_FOCO_1__CFG_SLV__DMPAC_FOCO_CORE__FOCO_REGS_CFG__IP_MMRS_CH_CTRL,Defines parameters that control the format conversion for input-output channel pair." hexmask.long.word 0x0 16.--31. 1. "MASK,16b mask value that will be and-ed with the result" hexmask.long.byte 0x0 12.--15. 1. "ROUND,Unsigned Rounding value that will be added" bitfld.long 0x0 8. "DIR,Shift direction - left or right. 0 -> Right 1 -> Left" "0: Right 1,?" bitfld.long 0x0 5.--7. "SHIFT_M1,Amount of bit shift minus 1. Valid values 0 to 7 meaning shift of 1 to 8. For no shift configure SHIFT_EN to 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "SHIFT_EN,Enable for shifting. 0 --> No shift 1 --> Shift determined by SHIFT_M1" "0: No shift 1,?" bitfld.long 0x0 0. "CH_EN,Enable format conversion channel" "0,1" line.long 0x4 "DMPAC_FOCO_1__CFG_SLV__DMPAC_FOCO_CORE__FOCO_REGS_CFG__IP_MMRS_CH_COUNT,Defines count values for pre/post load and functional operation for the format conversion for input-output channel pair." hexmask.long.word 0x4 16.--31. 1. "TRIG,Defines the number of FOCO module operations (HTS starts/dones) for which the actual format conversion happens after PRELOAD number of FOCO module operations. This number cannot be 0 for an active channel" hexmask.long.byte 0x4 8.--15. 1. "POSTLOAD,Defines the number of FOCO module operations (HTS starts/dones) that would be skipped after PRELOAD + TRIG number of FOCO module operations" hexmask.long.byte 0x4 0.--7. 1. "PRELOAD,Defines the number of FOCO module operations (HTS starts/dones) that would be skipped after HTS init" tree.end tree "DMPAC0_FOCO_1_DMPAC_FOCO_1_CFG_SLV_VPAC_FOCO_LSE_CFG_VP (DMPAC0_FOCO_1_DMPAC_FOCO_1_CFG_SLV_VPAC_FOCO_LSE_CFG_VP)" base ad:0xF428200 rgroup.long 0x0++0x3 line.long 0x0 "DMPAC_FOCO_1__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_status_param,The STATUS_PARAM register returns the LSE compile configuration parameters." bitfld.long 0x0 30.--31. "BYPASS_CH,Number of available input channel selection for loopback mode" "0,1,2,3" newline bitfld.long 0x0 29. "OUT_SKIP_EN,Output Auto-Skip Enable" "0,1" newline bitfld.long 0x0 28. "CORE_OUT_2D,1D or 2D output addressing mode(2D if 1)" "0,1" newline hexmask.long.byte 0x0 23.--27. 1. "CORE_OUT_DW,Core Output Channel Data Width" newline bitfld.long 0x0 22. "LINE_SKIP_EN,Source Line Inc by 2 Supported (if 1)" "0,1" newline bitfld.long 0x0 21. "BIT_AOFFSET,Source nibble offset address Supported (if 1)" "0,1" newline bitfld.long 0x0 20. "HV_INSERT,H/VBLANK Insertion Supported (if 1)" "0,1" newline bitfld.long 0x0 17.--19. "PIX_MX_HT,Core_Input Pixel Matrix Height" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 12.--16. 1. "CORE_DW,Core Input Data Bus Width" newline bitfld.long 0x0 10.--11. "SL2_OUT_H3A_CH,Number of SL2 H3A Output Channels" "0,1,2,3" newline hexmask.long.byte 0x0 6.--9. 1. "SL2_OUT_CH,Number of SL2 Output Channels" newline bitfld.long 0x0 3.--5. "SL2_IN_CH_THR,Number of Input Channels per thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "VPORT_THR,Number of VPORT input enabled" "0,1" newline bitfld.long 0x0 0.--1. "NTHR,Number of threads supported" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "DMPAC_FOCO_1__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_status_error,The STATUS_ERROR register returns the LSE error status." hexmask.long.byte 0x0 8.--14. 1. "VM_WR_ERR,VBUSM I/F Last Write Error Status [14:11] Write Channel Number [10:8] VBUSM write error status" newline hexmask.long.byte 0x0 0.--4. 1. "VM_RD_ERR,VBUSM I/F Last Read Error Status [4:3] Read Channel Number [2:0] VBUSM read error status" rgroup.long 0x8++0x3 line.long 0x0 "DMPAC_FOCO_1__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_status_idle_mode,The STATUS_IDLE_MODE register returns IDLE status of LSE VBUSM port and in/output channels - 0: IDLE 1: ACTIVE" hexmask.long.byte 0x0 12.--15. 1. "LSE_OUT_CHAN,Output Channel[3:0] Status" newline hexmask.long.byte 0x0 4.--7. 1. "LSE_IN_CHAN,Input Channel[3:0] Status" newline bitfld.long 0x0 1. "VM_WR_PORT,SL2 vbusm I/F Write Port Status" "0,1" newline bitfld.long 0x0 0. "VM_RD_PORT,SL2 vbusm I/F Read Port Status" "0,1" rgroup.long 0xC++0x3 line.long 0x0 "DMPAC_FOCO_1__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_cfg_lse,The CFG_LSE register configures the LSE general hardware modes." bitfld.long 0x0 8. "PSA_EN,Test mode Output Channel Signature Generation Enable 0: Disable (default) 1: Enable When enabled LSE generates a unique CRC signature for each output channel's frame data at frame completion." "0: Disable,1: Enable When enabled" newline bitfld.long 0x0 4. "VM_ARB_FIXED_MODE,VBUSM Arbitration Fixed Mode select 0: Round-Robin Arbitration (default) 1: Fixed-mode Arbitration" "0: Round-Robin Arbitration,1: Fixed-mode Arbitration" rgroup.long 0x140++0x3 line.long 0x0 "DMPAC_FOCO_1__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_psa_signature,The PSA_SIGNATURE register returns the captured PSA signature value of the last frame data of output channel [a]." hexmask.long 0x0 0.--31. 1. "VALUE,32-bit CRC signature value" rgroup.long 0x1E0++0x3 line.long 0x0 "DMPAC_FOCO_1__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_dbg,The DBG register returns the current status of internal FSM - TI internal use only." hexmask.long 0x0 0.--31. 1. "STATUS,Debug status" rgroup.long 0x10++0x3 line.long 0x0 "DMPAC_FOCO_1__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_cfg,The SRC_CFG register configures the input channels for the processing thread" bitfld.long 0x0 7. "SRC_LN_INC_2,Source Line address Increment by 2 enable 0: Disable 1: Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 4. "PIX_FMT_ALIGN,Input Pixel Container Alignment 0: LSB-aligned 1: MSB-aligned" "0: LSB-aligned,1: MSB-aligned" newline bitfld.long 0x0 2.--3. "PIX_FMT_CNTRSZ,Input Pixel Container Size Sel 0: 8-bit 1: 12-bit 2: 16-bit 3: reserved Input pixel container size must be same or larger than input pixel width." "?,?,?,3: reserved Input pixel container size must be same.." newline bitfld.long 0x0 0.--1. "PIX_FMT_PW,Input Pixel Width Sel 0: 8-bit 1: 12-bit 2: 14-bit 3: 16-bit The width defines the bit-depth of the pixel data to be extracted from the pixel container." "0,1,2,3" rgroup.long 0x18++0xB line.long 0x0 "DMPAC_FOCO_1__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_frame_size,The SRC_FRAME_SIZE register configures the frame size of all input buffers for the processing thread ." hexmask.long.word 0x0 16.--28. 1. "HEIGHT,SL2 - Source Buffer Height (number of lines)" newline hexmask.long.word 0x0 0.--12. 1. "WIDTH,SL2 - Source Buffer Width (number of pixels)" line.long 0x4 "DMPAC_FOCO_1__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_buf_attr,The SRC_BUF_ATTR register configures the common attributes of all SL2 source buffers for the processing thread ." hexmask.long.word 0x4 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)" newline hexmask.long.word 0x4 6.--15. 1. "BUF_STRIDE,Buffer Stride Size [15:6] (64 byte multiple) stride size" newline hexmask.long.byte 0x4 0.--5. 1. "BUF_STRIDE_6_LSB,Buffer Stride Size [5:0] - 6 LSB bits of buffer stride size should always be 0. Writes have no effect. Always read as 0" line.long 0x8 "DMPAC_FOCO_1__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_buf_ba,The SRC_BUF_BA[b] register configures the base address of the SL2 source buffer [b] for the processing thread ." bitfld.long 0x8 31. "ENABLE,Input Buffer Enable 0: Disable 1: Enable When the processing thread is enabled at least one of the input buffer must be enabled" "0: Disable,1: Enable When the processing thread is enabled" newline hexmask.long.tbyte 0x8 6.--23. 1. "ADDR,Base Address[23:6] - (64 Byte aligned) byte address" newline hexmask.long.byte 0x8 0.--5. 1. "ADDR_6_LSB,Base Address[5:0] - 6 LSB bits of address should always be 0. Writes have no effect. Always read as 0" rgroup.long 0x50++0x7 line.long 0x0 "DMPAC_FOCO_1__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_buf_cfg,The DST_BUF_CFG register configures the output buffer channel ." rbitfld.long 0x0 31. "CH_DISABLED,Channel Disable Status (read-only) 0: (Default) Chanel is enabled for Y UV or YUV422 data transfer to SL2 memory. All configurations associated with this DST_BUF[a] are valid. 1: Channel is disabled for SL2 data transfer (because the.." "?,1: Channel is disabled for SL2 data transfer" newline bitfld.long 0x0 29. "YUV422_INTLV_ORDER,YUV422 Interleaving Order Selection 0: UYVY 1: YUYV Only Applicable if this output channel is YUV422 output capable LUMA channel. Otherwise setting has no effect." "0: UYVY 1: YUYV Only Applicable if this output..,?" newline bitfld.long 0x0 28. "YUV422_OUT_EN,YUV422 Interleaved Output Merge Enable 0: Disable 1: Enable When enabled this channel interleaves data from the associated chroma data output channel to output YUV422 interleaved data to the SL2 memory. Only Applicable if this output.." "0: Disable,1: Enable When enabled" newline bitfld.long 0x0 4. "PIX_FMT_ALIGN,Output Pixel Container Alignment 0: LSB-aligned 1: MSB-aligned" "0: LSB-aligned,1: MSB-aligned" newline bitfld.long 0x0 2.--3. "PIX_FMT_CNTRSZ,Output Pixel Container Size Sel 0: 8-bit 1: 12-bit 2: 16-bit 3: reserved Output pixel container size must be same or larger than output pixel width. If yuv422_out_en is set pix_fmt_cntrsz must be 0." "?,?,?,3: reserved Output pixel container size must be.." newline bitfld.long 0x0 0.--1. "PIX_FMT_PW,Output Pixel Width Sel 0: 8-bit 1: 12-bit 2: reserved 3: 16-bit The width defines the bit-depth of the pixel data to be stored in the pixel container." "?,?,2: reserved,?" line.long 0x4 "DMPAC_FOCO_1__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_buf_attr0,The DST_BUF_ATTR0 register configures the attributes of the output SL2 buffer ." hexmask.long.word 0x4 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)" newline hexmask.long.word 0x4 6.--15. 1. "BUF_STRIDE,Buffer Stride Size [15:6] (64 byte multiple) stride size" newline hexmask.long.byte 0x4 0.--5. 1. "BUF_STRIDE_6_LSB,Buffer Stride Size [5:0] - 6 LSB bits of buffer stride size should always be 0. Writes have no effect. Always read as 0" rgroup.long 0x5C++0x3 line.long 0x0 "DMPAC_FOCO_1__CFG_SLV__VPAC_FOCO_LSE__CFG_VP__REGS_buf_ba,The DST_BUF_BA register configures the base address of the output SL2 circular buffer ." bitfld.long 0x0 31. "ENABLE,Output Channel Enable 0: Disable 1: Enable" "0: Disable,1: Enable" newline hexmask.long.tbyte 0x0 6.--23. 1. "ADDR,Base Address[23:6] - (64 Byte aligned) byte address" newline hexmask.long.byte 0x0 0.--5. 1. "ADDR_6_LSB,Base Address[5:0] - 6 LSB bits of address should always be 0. Writes have no effect. Always read as 0" tree.end tree.end tree.end tree "DMPAC0_HTS_0_HTS_S_VBUSP (DMPAC0_HTS_0_HTS_S_VBUSP)" base ad:0xF408000 rgroup.long 0x0++0x1B line.long 0x0 "HTS__S_VBUSP__REGS_pipeline_control_0,Enable pipeline to activate all connected scheduler" bitfld.long 0x0 0. "PIPE_EN,Pipeline 0 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_pipeline_control_1,Enable pipeline to activate all connected scheduler" bitfld.long 0x4 0. "PIPE_EN,Pipeline 1 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_pipeline_control_2,Enable pipeline to activate all connected scheduler" bitfld.long 0x8 0. "PIPE_EN,Pipeline 2 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_pipeline_control_3,Enable pipeline to activate all connected scheduler" bitfld.long 0xC 0. "PIPE_EN,Pipeline 3 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_pipeline_control_4,Enable pipeline to activate all connected scheduler" bitfld.long 0x10 0. "PIPE_EN,Pipeline 4 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1" line.long 0x14 "HTS__S_VBUSP__REGS_pipeline_control_5,Enable pipeline to activate all connected scheduler" bitfld.long 0x14 0. "PIPE_EN,Pipeline 5 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1" line.long 0x18 "HTS__S_VBUSP__REGS_pipeline_control_6,Enable pipeline to activate all connected scheduler" bitfld.long 0x18 0. "PIPE_EN,Pipeline 6 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1" rgroup.long 0x50++0x5B line.long 0x0 "HTS__S_VBUSP__REGS_HWA0_scheduler_control,Scheduler Control Register" bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA0 Scheduler resources must not be read during halted state. '1'-> HWA0 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA0 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA0 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA0_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further start. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA0_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA0 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA0 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA0_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA0 sch '0' --> Disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA0_cons0_control,Controlling consumer socket 0 for HWA0" hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 0" newline bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x14 "HTS__S_VBUSP__REGS_HWA0_cons1_control,Controlling consumer socket 1 for HWA0" hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 1" newline bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" line.long 0x18 "HTS__S_VBUSP__REGS_HWA0_cons2_control,Controlling consumer socket 2 for HWA0" hexmask.long.word 0x18 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 2" newline bitfld.long 0x18 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1" line.long 0x1C "HTS__S_VBUSP__REGS_HWA0_cons3_control,Controlling consumer socket 3 for HWA0" hexmask.long.word 0x1C 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 3" newline bitfld.long 0x1C 0. "CONS_EN,'1' -> Consumer socket 3 enable '0' Disable" "0,1" line.long 0x20 "HTS__S_VBUSP__REGS_HWA0_cons4_control,Controlling consumer socket 4 for HWA0" hexmask.long.word 0x20 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 4" newline bitfld.long 0x20 0. "CONS_EN,'1' -> Consumer socket 4 enable '0' Disable" "0,1" line.long 0x24 "HTS__S_VBUSP__REGS_HWA0_cons5_control,Controlling consumer socket 5 for HWA0" hexmask.long.word 0x24 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 5" newline bitfld.long 0x24 0. "CONS_EN,'1' -> Consumer socket 5 enable '0' Disable" "0,1" line.long 0x28 "HTS__S_VBUSP__REGS_HWA0_prod0_control,Controlling producer socket0 for HWA0" hexmask.long.byte 0x28 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x28 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x2C "HTS__S_VBUSP__REGS_HWA0_prod0_buf_control,Controlling producer socket0 buffer for HWA0" hexmask.long.byte 0x2C 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x2C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x2C 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x30 "HTS__S_VBUSP__REGS_HWA0_prod0_count,Defining count values for pre/post load for generating pend by HWA0 prod0" hexmask.long.word 0x30 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x30 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x30 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x34 "HTS__S_VBUSP__REGS_HWA0_pa0_control,control register to manage pattern adapter on HWA0 prod socket0" hexmask.long.word 0x34 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x34 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x34 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x34 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x34 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x38 "HTS__S_VBUSP__REGS_HWA0_pa0_prodcount,count values for HWA0 prod socket0" hexmask.long.word 0x38 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x38 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x3C "HTS__S_VBUSP__REGS_HWA0_prod1_control,Controlling producer socket1 for HWA0" hexmask.long.byte 0x3C 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x3C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x40 "HTS__S_VBUSP__REGS_HWA0_prod1_buf_control,Controlling producer socket1 buffer for HWA0" hexmask.long.byte 0x40 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x40 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x40 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x44 "HTS__S_VBUSP__REGS_HWA0_prod1_count,Defining count values for pre/post load for generating pend by HWA0 prod1" hexmask.long.word 0x44 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x44 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x44 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x48 "HTS__S_VBUSP__REGS_HWA0_pa1_control,control register to manage pattern adapter on HWA0 prod socket1" hexmask.long.word 0x48 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x48 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x48 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x48 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x48 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x4C "HTS__S_VBUSP__REGS_HWA0_pa1_prodcount,count values for HWA0 prod socket1" hexmask.long.word 0x4C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x4C 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x50 "HTS__S_VBUSP__REGS_HWA0_prod2_control,Controlling producer socket2 for HWA0" hexmask.long.byte 0x50 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x50 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x54 "HTS__S_VBUSP__REGS_HWA0_prod2_buf_control,Controlling producer socket2 buffer for HWA0" hexmask.long.byte 0x54 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x54 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x54 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x58 "HTS__S_VBUSP__REGS_HWA0_prod2_count,Defining count values for pre/post load for generating pend by HWA0 prod2" hexmask.long.word 0x58 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x58 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x58 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xB4++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA0_prod3_control,Controlling producer socket3 for HWA0" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA0_prod3_buf_control,Controlling producer socket3 buffer for HWA0" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA0_prod3_count,Defining count values for pre/post load for generating pend by HWA0 prod3" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xC8++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA0_prod4_control,Controlling producer socket4 for HWA0" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA0_prod4_buf_control,Controlling producer socket4 buffer for HWA0" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA0_prod4_count,Defining count values for pre/post load for generating pend by HWA0 prod4" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xDC++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA0_prod5_control,Controlling producer socket5 for HWA0" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 5. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA0_prod5_buf_control,Controlling producer socket5 buffer for HWA0" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA0_prod5_count,Defining count values for pre/post load for generating pend by HWA0 prod5" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xF0++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA0_prod6_control,Controlling producer socket6 for HWA0" bitfld.long 0x0 24.--26. "MASK_SELECT,define which tdone_mask apply to prod socket 6. tdone_mask[mask_select] applies to prod_socket6" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 6. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA0_prod6_buf_control,Controlling producer socket6 buffer for HWA0" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA0_prod6_count,Defining count values for pre/post load for generating pend by HWA0 prod6" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x104++0x5B line.long 0x0 "HTS__S_VBUSP__REGS_HWA1_scheduler_control,Scheduler Control Register" bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA1 Scheduler resources must not be read during halted state. '1'-> HWA1 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA1 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA1 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA1_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further start. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA1_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA1 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA1 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA1_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA1 sch '0' --> Disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA1_cons0_control,Controlling consumer socket 0 for HWA1" hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 0" newline bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x14 "HTS__S_VBUSP__REGS_HWA1_cons1_control,Controlling consumer socket 1 for HWA1" hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 1" newline bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" line.long 0x18 "HTS__S_VBUSP__REGS_HWA1_cons2_control,Controlling consumer socket 2 for HWA1" hexmask.long.word 0x18 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 2" newline bitfld.long 0x18 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1" line.long 0x1C "HTS__S_VBUSP__REGS_HWA1_cons3_control,Controlling consumer socket 3 for HWA1" hexmask.long.word 0x1C 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 3" newline bitfld.long 0x1C 0. "CONS_EN,'1' -> Consumer socket 3 enable '0' Disable" "0,1" line.long 0x20 "HTS__S_VBUSP__REGS_HWA1_cons4_control,Controlling consumer socket 4 for HWA1" hexmask.long.word 0x20 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 4" newline bitfld.long 0x20 0. "CONS_EN,'1' -> Consumer socket 4 enable '0' Disable" "0,1" line.long 0x24 "HTS__S_VBUSP__REGS_HWA1_cons5_control,Controlling consumer socket 5 for HWA1" hexmask.long.word 0x24 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 5" newline bitfld.long 0x24 0. "CONS_EN,'1' -> Consumer socket 5 enable '0' Disable" "0,1" line.long 0x28 "HTS__S_VBUSP__REGS_HWA1_prod0_control,Controlling producer socket0 for HWA1" hexmask.long.byte 0x28 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x28 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x2C "HTS__S_VBUSP__REGS_HWA1_prod0_buf_control,Controlling producer socket0 buffer for HWA1" hexmask.long.byte 0x2C 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x2C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x2C 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x30 "HTS__S_VBUSP__REGS_HWA1_prod0_count,Defining count values for pre/post load for generating pend by HWA1 prod0" hexmask.long.word 0x30 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x30 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x30 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x34 "HTS__S_VBUSP__REGS_HWA1_pa0_control,control register to manage pattern adapter on HWA1 prod socket0" hexmask.long.word 0x34 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x34 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x34 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x34 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x34 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x38 "HTS__S_VBUSP__REGS_HWA1_pa0_prodcount,count values for HWA1 prod socket0" hexmask.long.word 0x38 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x38 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x3C "HTS__S_VBUSP__REGS_HWA1_prod1_control,Controlling producer socket1 for HWA1" hexmask.long.byte 0x3C 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x3C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x40 "HTS__S_VBUSP__REGS_HWA1_prod1_buf_control,Controlling producer socket1 buffer for HWA1" hexmask.long.byte 0x40 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x40 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x40 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x44 "HTS__S_VBUSP__REGS_HWA1_prod1_count,Defining count values for pre/post load for generating pend by HWA1 prod1" hexmask.long.word 0x44 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x44 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x44 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x48 "HTS__S_VBUSP__REGS_HWA1_pa1_control,control register to manage pattern adapter on HWA1 prod socket1" hexmask.long.word 0x48 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x48 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x48 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x48 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x48 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x4C "HTS__S_VBUSP__REGS_HWA1_pa1_prodcount,count values for HWA1 prod socket1" hexmask.long.word 0x4C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x4C 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x50 "HTS__S_VBUSP__REGS_HWA1_prod2_control,Controlling producer socket2 for HWA1" hexmask.long.byte 0x50 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x50 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x54 "HTS__S_VBUSP__REGS_HWA1_prod2_buf_control,Controlling producer socket2 buffer for HWA1" hexmask.long.byte 0x54 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x54 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x54 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x58 "HTS__S_VBUSP__REGS_HWA1_prod2_count,Defining count values for pre/post load for generating pend by HWA1 prod2" hexmask.long.word 0x58 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x58 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x58 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x168++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA1_prod3_control,Controlling producer socket3 for HWA1" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA1_prod3_buf_control,Controlling producer socket3 buffer for HWA1" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA1_prod3_count,Defining count values for pre/post load for generating pend by HWA1 prod3" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x17C++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA1_prod4_control,Controlling producer socket4 for HWA1" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA1_prod4_buf_control,Controlling producer socket4 buffer for HWA1" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA1_prod4_count,Defining count values for pre/post load for generating pend by HWA1 prod4" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x190++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA1_prod5_control,Controlling producer socket5 for HWA1" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 5. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA1_prod5_buf_control,Controlling producer socket5 buffer for HWA1" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA1_prod5_count,Defining count values for pre/post load for generating pend by HWA1 prod5" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x1A4++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA1_prod6_control,Controlling producer socket6 for HWA1" bitfld.long 0x0 24.--26. "MASK_SELECT,define which tdone_mask apply to prod socket 6. tdone_mask[mask_select] applies to prod_socket6" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 6. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA1_prod6_buf_control,Controlling producer socket6 buffer for HWA1" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA1_prod6_count,Defining count values for pre/post load for generating pend by HWA1 prod6" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x1B8++0xB3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA2_scheduler_control,Scheduler Control Register" bitfld.long 0x0 22. "EOR_EN,'1' -> LDC REGION/sub-frame feature enabled '0' LDC works in Frame mode only" "0,1" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA2 Scheduler resources must not be read during halted state. '1'-> HWA2 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA2 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA2 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA2_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA2_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA2 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA2 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA2_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA2 sch '0' --> Disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA2_cons0_control,Controlling consumer socket 0 for HWA2" hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA2 cons socket 0" newline bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x14 "HTS__S_VBUSP__REGS_HWA2_cons1_control,Controlling consumer socket 1 for HWA2" hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA2 cons socket 1" newline bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" line.long 0x18 "HTS__S_VBUSP__REGS_HWA2_cons2_control,Controlling consumer socket 2 for HWA2" hexmask.long.word 0x18 1.--9. 1. "PROD_SELECT,producer select for HWA2 cons socket 2" newline bitfld.long 0x18 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1" line.long 0x1C "HTS__S_VBUSP__REGS_HWA2_prod0_control,Controlling producer socket0 for HWA2" bitfld.long 0x1C 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 0 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (0+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior;,1: Prod Socket 0 is used to trigger DMA channel to..,2: Prod Socket 0 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x1C 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x20 "HTS__S_VBUSP__REGS_HWA2_prod0_buf_control,Controlling producer socket0 buffer for HWA2" hexmask.long.byte 0x20 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x24 "HTS__S_VBUSP__REGS_HWA2_prod0_count,Defining count values for pre/post load for generating pend by HWA2 prod0" hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x28 "HTS__S_VBUSP__REGS_HWA2_pa0_control,control register to manage pattern adapter on HWA2 prod socket0" hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x2C "HTS__S_VBUSP__REGS_HWA2_pa0_prodcount,count values for HWA2 prod socket0" hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x2C 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x30 "HTS__S_VBUSP__REGS_HWA2_prod1_control,Controlling producer socket1 for HWA2" bitfld.long 0x30 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 1 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (1+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior;,1: Prod Socket 1 is used to trigger DMA channel to..,2: Prod Socket 1 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x30 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x34 "HTS__S_VBUSP__REGS_HWA2_prod1_buf_control,Controlling producer socket1 buffer for HWA2" hexmask.long.byte 0x34 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x38 "HTS__S_VBUSP__REGS_HWA2_prod1_count,Defining count values for pre/post load for generating pend by HWA2 prod1" hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x3C "HTS__S_VBUSP__REGS_HWA2_pa1_control,control register to manage pattern adapter on HWA2 prod socket1" hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x40 "HTS__S_VBUSP__REGS_HWA2_pa1_prodcount,count values for HWA2 prod socket1" hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x40 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x44 "HTS__S_VBUSP__REGS_HWA2_prod2_control,Controlling producer socket2 for HWA2" bitfld.long 0x44 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 2 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (2+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior;,1: Prod Socket 2 is used to trigger DMA channel to..,2: Prod Socket 2 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x44 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x48 "HTS__S_VBUSP__REGS_HWA2_prod2_buf_control,Controlling producer socket2 buffer for HWA2" hexmask.long.byte 0x48 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x4C "HTS__S_VBUSP__REGS_HWA2_prod2_count,Defining count values for pre/post load for generating pend by HWA2 prod2" hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x50 "HTS__S_VBUSP__REGS_HWA2_pa2_control,control register to manage pattern adapter on HWA2 prod socket2" hexmask.long.word 0x50 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x50 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x50 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x50 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x50 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x54 "HTS__S_VBUSP__REGS_HWA2_pa2_prodcount,count values for HWA2 prod socket2" hexmask.long.word 0x54 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x54 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x58 "HTS__S_VBUSP__REGS_HWA2_prod3_control,Controlling producer socket3 for HWA2" bitfld.long 0x58 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 3 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (3+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior;,1: Prod Socket 3 is used to trigger DMA channel to..,2: Prod Socket 3 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x58 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline hexmask.long.byte 0x58 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x58 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x5C "HTS__S_VBUSP__REGS_HWA2_prod3_buf_control,Controlling producer socket3 buffer for HWA2" hexmask.long.byte 0x5C 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x5C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x5C 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x60 "HTS__S_VBUSP__REGS_HWA2_prod3_count,Defining count values for pre/post load for generating pend by HWA2 prod3" hexmask.long.word 0x60 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x60 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x60 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x64 "HTS__S_VBUSP__REGS_HWA2_pa3_control,control register to manage pattern adapter on HWA2 prod socket3" hexmask.long.word 0x64 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x64 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x64 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x64 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x64 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x68 "HTS__S_VBUSP__REGS_HWA2_pa3_prodcount,count values for HWA2 prod socket3" hexmask.long.word 0x68 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x68 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x6C "HTS__S_VBUSP__REGS_HWA2_prod4_control,Controlling producer socket4 for HWA2" bitfld.long 0x6C 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 4. tdone_mask[mask_select] applies to prod_socket4." "0,1,2,3" newline hexmask.long.byte 0x6C 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x6C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x70 "HTS__S_VBUSP__REGS_HWA2_prod4_buf_control,Controlling producer socket4 buffer for HWA2" hexmask.long.byte 0x70 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x70 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x70 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x74 "HTS__S_VBUSP__REGS_HWA2_prod4_count,Defining count values for pre/post load for generating pend by HWA2 prod4" hexmask.long.word 0x74 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x74 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x74 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x78 "HTS__S_VBUSP__REGS_HWA2_pa4_control,control register to manage pattern adapter on HWA2 prod socket4" hexmask.long.word 0x78 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x78 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x78 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x78 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x78 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x7C "HTS__S_VBUSP__REGS_HWA2_pa4_prodcount,count values for HWA2 prod socket4" hexmask.long.word 0x7C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x7C 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x80 "HTS__S_VBUSP__REGS_HWA2_prod5_control,Controlling producer socket5 for HWA2" bitfld.long 0x80 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 5. tdone_mask[mask_select] applies to prod_socket5." "0,1,2,3" newline hexmask.long.byte 0x80 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 5. Used in decrementing count of producer buffer" newline bitfld.long 0x80 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x84 "HTS__S_VBUSP__REGS_HWA2_prod5_buf_control,Controlling producer socket5 buffer for HWA2" hexmask.long.byte 0x84 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x84 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x84 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x88 "HTS__S_VBUSP__REGS_HWA2_prod5_count,Defining count values for pre/post load for generating pend by HWA2 prod5" hexmask.long.word 0x88 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x88 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x88 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x8C "HTS__S_VBUSP__REGS_HWA2_pa5_control,control register to manage pattern adapter on HWA2 prod socket5" hexmask.long.word 0x8C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x8C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x8C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x8C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x8C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x90 "HTS__S_VBUSP__REGS_HWA2_pa5_prodcount,count values for HWA2 prod socket5" hexmask.long.word 0x90 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x90 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x94 "HTS__S_VBUSP__REGS_HWA2_prod6_control,Controlling producer socket6 for HWA2" bitfld.long 0x94 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 6. tdone_mask[mask_select] applies to prod_socket6." "0,1,2,3" newline hexmask.long.byte 0x94 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 6. Used in decrementing count of producer buffer" newline bitfld.long 0x94 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x98 "HTS__S_VBUSP__REGS_HWA2_prod6_buf_control,Controlling producer socket6 buffer for HWA2" hexmask.long.byte 0x98 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x98 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x98 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x9C "HTS__S_VBUSP__REGS_HWA2_prod6_count,Defining count values for pre/post load for generating pend by HWA2 prod6" hexmask.long.word 0x9C 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x9C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x9C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xA0 "HTS__S_VBUSP__REGS_HWA2_pa6_control,control register to manage pattern adapter on HWA2 prod socket6" hexmask.long.word 0xA0 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xA0 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xA0 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xA0 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xA0 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0xA4 "HTS__S_VBUSP__REGS_HWA2_pa6_prodcount,count values for HWA2 prod socket6" hexmask.long.word 0xA4 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0xA4 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0xA8 "HTS__S_VBUSP__REGS_HWA2_prod7_control,Controlling producer socket7 for HWA2" bitfld.long 0xA8 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 7. tdone_mask[mask_select] applies to prod_socket7." "0,1,2,3" newline hexmask.long.byte 0xA8 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 7. Used in decrementing count of producer buffer" newline bitfld.long 0xA8 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0xAC "HTS__S_VBUSP__REGS_HWA2_prod7_buf_control,Controlling producer socket7 buffer for HWA2" hexmask.long.byte 0xAC 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0xAC 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0xAC 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0xB0 "HTS__S_VBUSP__REGS_HWA2_prod7_count,Defining count values for pre/post load for generating pend by HWA2 prod7" hexmask.long.word 0xB0 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0xB0 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0xB0 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x274++0xB3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA3_scheduler_control,Scheduler Control Register" bitfld.long 0x0 22. "EOR_EN,'1' -> LDC REGION/sub-frame feature enabled '0' LDC works in Frame mode only" "0,1" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA3 Scheduler resources must not be read during halted state. '1'-> HWA3 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA3 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA3 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA3_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA3_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA3 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA3 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA3_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA3 sch '0' --> Disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA3_cons0_control,Controlling consumer socket 0 for HWA3" hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA3 cons socket 0" newline bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x14 "HTS__S_VBUSP__REGS_HWA3_cons1_control,Controlling consumer socket 1 for HWA3" hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA3 cons socket 1" newline bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" line.long 0x18 "HTS__S_VBUSP__REGS_HWA3_cons2_control,Controlling consumer socket 2 for HWA3" hexmask.long.word 0x18 1.--9. 1. "PROD_SELECT,producer select for HWA3 cons socket 2" newline bitfld.long 0x18 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1" line.long 0x1C "HTS__S_VBUSP__REGS_HWA3_prod0_control,Controlling producer socket0 for HWA3" bitfld.long 0x1C 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 0 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (0+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior;,1: Prod Socket 0 is used to trigger DMA channel to..,2: Prod Socket 0 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x1C 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x20 "HTS__S_VBUSP__REGS_HWA3_prod0_buf_control,Controlling producer socket0 buffer for HWA3" hexmask.long.byte 0x20 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x24 "HTS__S_VBUSP__REGS_HWA3_prod0_count,Defining count values for pre/post load for generating pend by HWA3 prod0" hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x28 "HTS__S_VBUSP__REGS_HWA3_pa0_control,control register to manage pattern adapter on HWA3 prod socket0" hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x2C "HTS__S_VBUSP__REGS_HWA3_pa0_prodcount,count values for HWA3 prod socket0" hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x2C 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x30 "HTS__S_VBUSP__REGS_HWA3_prod1_control,Controlling producer socket1 for HWA3" bitfld.long 0x30 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 1 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (1+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior;,1: Prod Socket 1 is used to trigger DMA channel to..,2: Prod Socket 1 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x30 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x34 "HTS__S_VBUSP__REGS_HWA3_prod1_buf_control,Controlling producer socket1 buffer for HWA3" hexmask.long.byte 0x34 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x38 "HTS__S_VBUSP__REGS_HWA3_prod1_count,Defining count values for pre/post load for generating pend by HWA3 prod1" hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x3C "HTS__S_VBUSP__REGS_HWA3_pa1_control,control register to manage pattern adapter on HWA3 prod socket1" hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x40 "HTS__S_VBUSP__REGS_HWA3_pa1_prodcount,count values for HWA3 prod socket1" hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x40 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x44 "HTS__S_VBUSP__REGS_HWA3_prod2_control,Controlling producer socket2 for HWA3" bitfld.long 0x44 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 2 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (2+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior;,1: Prod Socket 2 is used to trigger DMA channel to..,2: Prod Socket 2 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x44 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x48 "HTS__S_VBUSP__REGS_HWA3_prod2_buf_control,Controlling producer socket2 buffer for HWA3" hexmask.long.byte 0x48 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x4C "HTS__S_VBUSP__REGS_HWA3_prod2_count,Defining count values for pre/post load for generating pend by HWA3 prod2" hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x50 "HTS__S_VBUSP__REGS_HWA3_pa2_control,control register to manage pattern adapter on HWA3 prod socket2" hexmask.long.word 0x50 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x50 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x50 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x50 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x50 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x54 "HTS__S_VBUSP__REGS_HWA3_pa2_prodcount,count values for HWA3 prod socket2" hexmask.long.word 0x54 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x54 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x58 "HTS__S_VBUSP__REGS_HWA3_prod3_control,Controlling producer socket3 for HWA3" bitfld.long 0x58 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 3 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (3+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior;,1: Prod Socket 3 is used to trigger DMA channel to..,2: Prod Socket 3 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x58 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline hexmask.long.byte 0x58 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x58 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x5C "HTS__S_VBUSP__REGS_HWA3_prod3_buf_control,Controlling producer socket3 buffer for HWA3" hexmask.long.byte 0x5C 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x5C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x5C 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x60 "HTS__S_VBUSP__REGS_HWA3_prod3_count,Defining count values for pre/post load for generating pend by HWA3 prod3" hexmask.long.word 0x60 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x60 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x60 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x64 "HTS__S_VBUSP__REGS_HWA3_pa3_control,control register to manage pattern adapter on HWA3 prod socket3" hexmask.long.word 0x64 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x64 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x64 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x64 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x64 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x68 "HTS__S_VBUSP__REGS_HWA3_pa3_prodcount,count values for HWA3 prod socket3" hexmask.long.word 0x68 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x68 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x6C "HTS__S_VBUSP__REGS_HWA3_prod4_control,Controlling producer socket4 for HWA3" bitfld.long 0x6C 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 4. tdone_mask[mask_select] applies to prod_socket4." "0,1,2,3" newline hexmask.long.byte 0x6C 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x6C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x70 "HTS__S_VBUSP__REGS_HWA3_prod4_buf_control,Controlling producer socket4 buffer for HWA3" hexmask.long.byte 0x70 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x70 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x70 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x74 "HTS__S_VBUSP__REGS_HWA3_prod4_count,Defining count values for pre/post load for generating pend by HWA3 prod4" hexmask.long.word 0x74 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x74 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x74 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x78 "HTS__S_VBUSP__REGS_HWA3_pa4_control,control register to manage pattern adapter on HWA3 prod socket4" hexmask.long.word 0x78 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x78 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x78 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x78 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x78 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x7C "HTS__S_VBUSP__REGS_HWA3_pa4_prodcount,count values for HWA3 prod socket4" hexmask.long.word 0x7C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x7C 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x80 "HTS__S_VBUSP__REGS_HWA3_prod5_control,Controlling producer socket5 for HWA3" bitfld.long 0x80 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 5. tdone_mask[mask_select] applies to prod_socket5." "0,1,2,3" newline hexmask.long.byte 0x80 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 5. Used in decrementing count of producer buffer" newline bitfld.long 0x80 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x84 "HTS__S_VBUSP__REGS_HWA3_prod5_buf_control,Controlling producer socket5 buffer for HWA3" hexmask.long.byte 0x84 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x84 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x84 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x88 "HTS__S_VBUSP__REGS_HWA3_prod5_count,Defining count values for pre/post load for generating pend by HWA3 prod5" hexmask.long.word 0x88 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x88 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x88 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x8C "HTS__S_VBUSP__REGS_HWA3_pa5_control,control register to manage pattern adapter on HWA3 prod socket5" hexmask.long.word 0x8C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x8C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x8C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x8C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x8C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x90 "HTS__S_VBUSP__REGS_HWA3_pa5_prodcount,count values for HWA3 prod socket5" hexmask.long.word 0x90 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x90 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x94 "HTS__S_VBUSP__REGS_HWA3_prod6_control,Controlling producer socket6 for HWA3" bitfld.long 0x94 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 6. tdone_mask[mask_select] applies to prod_socket6." "0,1,2,3" newline hexmask.long.byte 0x94 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 6. Used in decrementing count of producer buffer" newline bitfld.long 0x94 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x98 "HTS__S_VBUSP__REGS_HWA3_prod6_buf_control,Controlling producer socket6 buffer for HWA3" hexmask.long.byte 0x98 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x98 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x98 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x9C "HTS__S_VBUSP__REGS_HWA3_prod6_count,Defining count values for pre/post load for generating pend by HWA3 prod6" hexmask.long.word 0x9C 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x9C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x9C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xA0 "HTS__S_VBUSP__REGS_HWA3_pa6_control,control register to manage pattern adapter on HWA3 prod socket6" hexmask.long.word 0xA0 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xA0 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xA0 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xA0 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xA0 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0xA4 "HTS__S_VBUSP__REGS_HWA3_pa6_prodcount,count values for HWA3 prod socket6" hexmask.long.word 0xA4 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0xA4 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0xA8 "HTS__S_VBUSP__REGS_HWA3_prod7_control,Controlling producer socket7 for HWA3" bitfld.long 0xA8 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 7. tdone_mask[mask_select] applies to prod_socket7." "0,1,2,3" newline hexmask.long.byte 0xA8 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 7. Used in decrementing count of producer buffer" newline bitfld.long 0xA8 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0xAC "HTS__S_VBUSP__REGS_HWA3_prod7_buf_control,Controlling producer socket7 buffer for HWA3" hexmask.long.byte 0xAC 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0xAC 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0xAC 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0xB0 "HTS__S_VBUSP__REGS_HWA3_prod7_count,Defining count values for pre/post load for generating pend by HWA3 prod7" hexmask.long.word 0xB0 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0xB0 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0xB0 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x330++0x23 line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_scheduler_control,Scheduler Control Register" bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA4 Scheduler resources must not be read during halted state. '1'-> HWA4 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA4 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA4 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA4_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA4_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA4 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA4 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA4_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA4 sch '0' --> Disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA4_cons0_control,Controlling consumer socket 0 for HWA4" hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA4 cons socket 0" newline bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x14 "HTS__S_VBUSP__REGS_HWA4_cons1_control,Controlling consumer socket 1 for HWA4" hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA4 cons socket 1" newline bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" line.long 0x18 "HTS__S_VBUSP__REGS_HWA4_prod0_control,Controlling producer socket0 for HWA4" hexmask.long.byte 0x18 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x18 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x1C "HTS__S_VBUSP__REGS_HWA4_prod0_buf_control,Controlling producer socket0 buffer for HWA4" hexmask.long.byte 0x1C 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x1C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x1C 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x20 "HTS__S_VBUSP__REGS_HWA4_prod0_count,Defining count values for pre/post load for generating pend by HWA4 prod0" hexmask.long.word 0x20 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x20 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x20 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x35C++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_prod1_control,Controlling producer socket1 for HWA4" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA4_prod1_buf_control,Controlling producer socket1 buffer for HWA4" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA4_prod1_count,Defining count values for pre/post load for generating pend by HWA4 prod1" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x370++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_prod2_control,Controlling producer socket2 for HWA4" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA4_prod2_buf_control,Controlling producer socket2 buffer for HWA4" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA4_prod2_count,Defining count values for pre/post load for generating pend by HWA4 prod2" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x384++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_prod3_control,Controlling producer socket3 for HWA4" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA4_prod3_buf_control,Controlling producer socket3 buffer for HWA4" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA4_prod3_count,Defining count values for pre/post load for generating pend by HWA4 prod3" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x398++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_prod4_control,Controlling producer socket4 for HWA4" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA4_prod4_buf_control,Controlling producer socket4 buffer for HWA4" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA4_prod4_count,Defining count values for pre/post load for generating pend by HWA4 prod4" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x3AC++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_prod5_control,Controlling producer socket5 for HWA4" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 5. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA4_prod5_buf_control,Controlling producer socket5 buffer for HWA4" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA4_prod5_count,Defining count values for pre/post load for generating pend by HWA4 prod5" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x3C0++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_prod6_control,Controlling producer socket6 for HWA4" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 6. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA4_prod6_buf_control,Controlling producer socket6 buffer for HWA4" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA4_prod6_count,Defining count values for pre/post load for generating pend by HWA4 prod6" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x3D4++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_prod7_control,Controlling producer socket7 for HWA4" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 7. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA4_prod7_buf_control,Controlling producer socket7 buffer for HWA4" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA4_prod7_count,Defining count values for pre/post load for generating pend by HWA4 prod7" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x3E8++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_prod8_control,Controlling producer socket8 for HWA4" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 8. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA4_prod8_buf_control,Controlling producer socket8 buffer for HWA4" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA4_prod8_count,Defining count values for pre/post load for generating pend by HWA4 prod8" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x3FC++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_prod9_control,Controlling producer socket9 for HWA4" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 9. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA4_prod9_buf_control,Controlling producer socket9 buffer for HWA4" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA4_prod9_count,Defining count values for pre/post load for generating pend by HWA4 prod9" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x410++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_prod10_control,Controlling producer socket10 for HWA4" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 10. tdone_mask[mask_select] applies to prod_socket10" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 10. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA4_prod10_buf_control,Controlling producer socket10 buffer for HWA4" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA4_prod10_count,Defining count values for pre/post load for generating pend by HWA4 prod10" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x424++0x23 line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_scheduler_control,Scheduler Control Register" bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA5 Scheduler resources must not be read during halted state. '1'-> HWA5 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA5 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA5 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA5_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA5_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA5 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA5 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA5_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA5 sch '0' --> Disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA5_cons0_control,Controlling consumer socket 0 for HWA5" hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA5 cons socket 0" newline bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x14 "HTS__S_VBUSP__REGS_HWA5_cons1_control,Controlling consumer socket 1 for HWA5" hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA5 cons socket 1" newline bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" line.long 0x18 "HTS__S_VBUSP__REGS_HWA5_prod0_control,Controlling producer socket0 for HWA5" hexmask.long.byte 0x18 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x18 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x1C "HTS__S_VBUSP__REGS_HWA5_prod0_buf_control,Controlling producer socket0 buffer for HWA5" hexmask.long.byte 0x1C 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x1C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x1C 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x20 "HTS__S_VBUSP__REGS_HWA5_prod0_count,Defining count values for pre/post load for generating pend by HWA5 prod0" hexmask.long.word 0x20 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x20 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x20 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x450++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_prod1_control,Controlling producer socket1 for HWA5" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA5_prod1_buf_control,Controlling producer socket1 buffer for HWA5" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA5_prod1_count,Defining count values for pre/post load for generating pend by HWA5 prod1" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x464++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_prod2_control,Controlling producer socket2 for HWA5" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA5_prod2_buf_control,Controlling producer socket2 buffer for HWA5" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA5_prod2_count,Defining count values for pre/post load for generating pend by HWA5 prod2" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x478++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_prod3_control,Controlling producer socket3 for HWA5" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA5_prod3_buf_control,Controlling producer socket3 buffer for HWA5" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA5_prod3_count,Defining count values for pre/post load for generating pend by HWA5 prod3" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x48C++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_prod4_control,Controlling producer socket4 for HWA5" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA5_prod4_buf_control,Controlling producer socket4 buffer for HWA5" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA5_prod4_count,Defining count values for pre/post load for generating pend by HWA5 prod4" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x4A0++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_prod5_control,Controlling producer socket5 for HWA5" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 5. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA5_prod5_buf_control,Controlling producer socket5 buffer for HWA5" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA5_prod5_count,Defining count values for pre/post load for generating pend by HWA5 prod5" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x4B4++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_prod6_control,Controlling producer socket6 for HWA5" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 6. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA5_prod6_buf_control,Controlling producer socket6 buffer for HWA5" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA5_prod6_count,Defining count values for pre/post load for generating pend by HWA5 prod6" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x4C8++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_prod7_control,Controlling producer socket7 for HWA5" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 7. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA5_prod7_buf_control,Controlling producer socket7 buffer for HWA5" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA5_prod7_count,Defining count values for pre/post load for generating pend by HWA5 prod7" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x4DC++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_prod8_control,Controlling producer socket8 for HWA5" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 8. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA5_prod8_buf_control,Controlling producer socket8 buffer for HWA5" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA5_prod8_count,Defining count values for pre/post load for generating pend by HWA5 prod8" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x4F0++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_prod9_control,Controlling producer socket9 for HWA5" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 9. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA5_prod9_buf_control,Controlling producer socket9 buffer for HWA5" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA5_prod9_count,Defining count values for pre/post load for generating pend by HWA5 prod9" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x504++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_prod10_control,Controlling producer socket10 for HWA5" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 10. tdone_mask[mask_select] applies to prod_socket10" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 10. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA5_prod10_buf_control,Controlling producer socket10 buffer for HWA5" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA5_prod10_count,Defining count values for pre/post load for generating pend by HWA5 prod10" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x518++0x23 line.long 0x0 "HTS__S_VBUSP__REGS_HWA6_scheduler_control,Scheduler Control Register" bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA6 Scheduler resources must not be read during halted state. '1'-> HWA6 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA6 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA6 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA6_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA6_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA6 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA6 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA6_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA6 sch '0' --> Disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA6_cons0_control,Controlling consumer socket 0 for HWA6" hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA6 cons socket 0" newline bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x14 "HTS__S_VBUSP__REGS_HWA6_cons1_control,Controlling consumer socket 1 for HWA6" hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA6 cons socket 1" newline bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" line.long 0x18 "HTS__S_VBUSP__REGS_HWA6_prod0_control,Controlling producer socket0 for HWA6" hexmask.long.byte 0x18 1.--8. 1. "CONS_SELECT,consumer select for HWA6 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x18 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x1C "HTS__S_VBUSP__REGS_HWA6_prod0_buf_control,Controlling producer socket0 buffer for HWA6" hexmask.long.byte 0x1C 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x1C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x1C 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x20 "HTS__S_VBUSP__REGS_HWA6_prod0_count,Defining count values for pre/post load for generating pend by HWA6 prod0" hexmask.long.word 0x20 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x20 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x20 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x544++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA6_prod1_control,Controlling producer socket1 for HWA6" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA6 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA6_prod1_buf_control,Controlling producer socket1 buffer for HWA6" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA6_prod1_count,Defining count values for pre/post load for generating pend by HWA6 prod1" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x558++0x7F line.long 0x0 "HTS__S_VBUSP__REGS_HWA7_scheduler_control,Scheduler Control Register" bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA7 Scheduler resources must not be read during halted state. '1'-> HWA7 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA7 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA7 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA7_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further start. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA7_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA7 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA7 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA7_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA7 sch '0' --> Disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA7_cons0_control,Controlling consumer socket 0 for HWA7" hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 0" newline bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x14 "HTS__S_VBUSP__REGS_HWA7_cons1_control,Controlling consumer socket 1 for HWA7" hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 1" newline bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" line.long 0x18 "HTS__S_VBUSP__REGS_HWA7_cons2_control,Controlling consumer socket 2 for HWA7" hexmask.long.word 0x18 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 2" newline bitfld.long 0x18 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1" line.long 0x1C "HTS__S_VBUSP__REGS_HWA7_cons3_control,Controlling consumer socket 3 for HWA7" hexmask.long.word 0x1C 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 3" newline bitfld.long 0x1C 0. "CONS_EN,'1' -> Consumer socket 3 enable '0' Disable" "0,1" line.long 0x20 "HTS__S_VBUSP__REGS_HWA7_cons4_control,Controlling consumer socket 4 for HWA7" hexmask.long.word 0x20 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 4" newline bitfld.long 0x20 0. "CONS_EN,'1' -> Consumer socket 4 enable '0' Disable" "0,1" line.long 0x24 "HTS__S_VBUSP__REGS_HWA7_prod0_control,Controlling producer socket0 for HWA7" hexmask.long.byte 0x24 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x24 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x28 "HTS__S_VBUSP__REGS_HWA7_prod0_buf_control,Controlling producer socket0 buffer for HWA7" hexmask.long.byte 0x28 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x28 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x28 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x2C "HTS__S_VBUSP__REGS_HWA7_prod0_count,Defining count values for pre/post load for generating pend by HWA7 prod0" hexmask.long.word 0x2C 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x2C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x2C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x30 "HTS__S_VBUSP__REGS_HWA7_pa0_control,control register to manage pattern adapter on HWA7 prod socket0" hexmask.long.word 0x30 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x30 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x30 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x30 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x30 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x34 "HTS__S_VBUSP__REGS_HWA7_pa0_prodcount,count values for HWA7 prod socket0" hexmask.long.word 0x34 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x34 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x38 "HTS__S_VBUSP__REGS_HWA7_prod1_control,Controlling producer socket1 for HWA7" hexmask.long.byte 0x38 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x38 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x3C "HTS__S_VBUSP__REGS_HWA7_prod1_buf_control,Controlling producer socket1 buffer for HWA7" hexmask.long.byte 0x3C 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x3C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x3C 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x40 "HTS__S_VBUSP__REGS_HWA7_prod1_count,Defining count values for pre/post load for generating pend by HWA7 prod1" hexmask.long.word 0x40 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x40 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x40 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x44 "HTS__S_VBUSP__REGS_HWA7_pa1_control,control register to manage pattern adapter on HWA7 prod socket1" hexmask.long.word 0x44 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x44 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x44 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x44 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x44 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x48 "HTS__S_VBUSP__REGS_HWA7_pa1_prodcount,count values for HWA7 prod socket1" hexmask.long.word 0x48 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x48 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x4C "HTS__S_VBUSP__REGS_HWA7_prod2_control,Controlling producer socket2 for HWA7" hexmask.long.byte 0x4C 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x4C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x50 "HTS__S_VBUSP__REGS_HWA7_prod2_buf_control,Controlling producer socket2 buffer for HWA7" hexmask.long.byte 0x50 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x50 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x50 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x54 "HTS__S_VBUSP__REGS_HWA7_prod2_count,Defining count values for pre/post load for generating pend by HWA7 prod2" hexmask.long.word 0x54 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x54 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x54 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x58 "HTS__S_VBUSP__REGS_HWA7_pa2_control,control register to manage pattern adapter on HWA7 prod socket2" hexmask.long.word 0x58 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x58 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x58 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x58 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x58 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x5C "HTS__S_VBUSP__REGS_HWA7_pa2_prodcount,count values for HWA7 prod socket2" hexmask.long.word 0x5C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x5C 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x60 "HTS__S_VBUSP__REGS_HWA7_prod3_control,Controlling producer socket3 for HWA7" hexmask.long.byte 0x60 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x60 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x64 "HTS__S_VBUSP__REGS_HWA7_prod3_buf_control,Controlling producer socket3 buffer for HWA7" hexmask.long.byte 0x64 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x64 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x64 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x68 "HTS__S_VBUSP__REGS_HWA7_prod3_count,Defining count values for pre/post load for generating pend by HWA7 prod3" hexmask.long.word 0x68 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x68 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x68 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x6C "HTS__S_VBUSP__REGS_HWA7_pa3_control,control register to manage pattern adapter on HWA7 prod socket3" hexmask.long.word 0x6C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x6C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x6C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x6C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x6C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x70 "HTS__S_VBUSP__REGS_HWA7_pa3_prodcount,count values for HWA7 prod socket3" hexmask.long.word 0x70 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x70 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x74 "HTS__S_VBUSP__REGS_HWA7_prod4_control,Controlling producer socket4 for HWA7" bitfld.long 0x74 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 4. tdone_mask[mask_select] applies to prod_socket4" "0,1,2,3" newline hexmask.long.byte 0x74 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x74 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x78 "HTS__S_VBUSP__REGS_HWA7_prod4_buf_control,Controlling producer socket4 buffer for HWA7" hexmask.long.byte 0x78 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x78 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x78 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x7C "HTS__S_VBUSP__REGS_HWA7_prod4_count,Defining count values for pre/post load for generating pend by HWA7 prod4" hexmask.long.word 0x7C 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x7C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x7C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x5E0++0x7F line.long 0x0 "HTS__S_VBUSP__REGS_HWA8_scheduler_control,Scheduler Control Register" bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA8 Scheduler resources must not be read during halted state. '1'-> HWA8 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA8 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA8 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA8_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further start. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA8_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA8 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA8 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA8_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA8 sch '0' --> Disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA8_cons0_control,Controlling consumer socket 0 for HWA8" hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 0" newline bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x14 "HTS__S_VBUSP__REGS_HWA8_cons1_control,Controlling consumer socket 1 for HWA8" hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 1" newline bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" line.long 0x18 "HTS__S_VBUSP__REGS_HWA8_cons2_control,Controlling consumer socket 2 for HWA8" hexmask.long.word 0x18 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 2" newline bitfld.long 0x18 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1" line.long 0x1C "HTS__S_VBUSP__REGS_HWA8_cons3_control,Controlling consumer socket 3 for HWA8" hexmask.long.word 0x1C 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 3" newline bitfld.long 0x1C 0. "CONS_EN,'1' -> Consumer socket 3 enable '0' Disable" "0,1" line.long 0x20 "HTS__S_VBUSP__REGS_HWA8_cons4_control,Controlling consumer socket 4 for HWA8" hexmask.long.word 0x20 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 4" newline bitfld.long 0x20 0. "CONS_EN,'1' -> Consumer socket 4 enable '0' Disable" "0,1" line.long 0x24 "HTS__S_VBUSP__REGS_HWA8_prod0_control,Controlling producer socket0 for HWA8" hexmask.long.byte 0x24 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x24 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x28 "HTS__S_VBUSP__REGS_HWA8_prod0_buf_control,Controlling producer socket0 buffer for HWA8" hexmask.long.byte 0x28 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x28 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x28 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x2C "HTS__S_VBUSP__REGS_HWA8_prod0_count,Defining count values for pre/post load for generating pend by HWA8 prod0" hexmask.long.word 0x2C 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x2C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x2C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x30 "HTS__S_VBUSP__REGS_HWA8_pa0_control,control register to manage pattern adapter on HWA8 prod socket0" hexmask.long.word 0x30 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x30 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x30 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x30 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x30 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x34 "HTS__S_VBUSP__REGS_HWA8_pa0_prodcount,count values for HWA8 prod socket0" hexmask.long.word 0x34 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x34 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x38 "HTS__S_VBUSP__REGS_HWA8_prod1_control,Controlling producer socket1 for HWA8" hexmask.long.byte 0x38 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x38 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x3C "HTS__S_VBUSP__REGS_HWA8_prod1_buf_control,Controlling producer socket1 buffer for HWA8" hexmask.long.byte 0x3C 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x3C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x3C 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x40 "HTS__S_VBUSP__REGS_HWA8_prod1_count,Defining count values for pre/post load for generating pend by HWA8 prod1" hexmask.long.word 0x40 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x40 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x40 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x44 "HTS__S_VBUSP__REGS_HWA8_pa1_control,control register to manage pattern adapter on HWA8 prod socket1" hexmask.long.word 0x44 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x44 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x44 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x44 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x44 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x48 "HTS__S_VBUSP__REGS_HWA8_pa1_prodcount,count values for HWA8 prod socket1" hexmask.long.word 0x48 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x48 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x4C "HTS__S_VBUSP__REGS_HWA8_prod2_control,Controlling producer socket2 for HWA8" hexmask.long.byte 0x4C 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x4C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x50 "HTS__S_VBUSP__REGS_HWA8_prod2_buf_control,Controlling producer socket2 buffer for HWA8" hexmask.long.byte 0x50 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x50 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x50 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x54 "HTS__S_VBUSP__REGS_HWA8_prod2_count,Defining count values for pre/post load for generating pend by HWA8 prod2" hexmask.long.word 0x54 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x54 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x54 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x58 "HTS__S_VBUSP__REGS_HWA8_pa2_control,control register to manage pattern adapter on HWA8 prod socket2" hexmask.long.word 0x58 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x58 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x58 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x58 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x58 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x5C "HTS__S_VBUSP__REGS_HWA8_pa2_prodcount,count values for HWA8 prod socket2" hexmask.long.word 0x5C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x5C 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x60 "HTS__S_VBUSP__REGS_HWA8_prod3_control,Controlling producer socket3 for HWA8" hexmask.long.byte 0x60 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x60 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x64 "HTS__S_VBUSP__REGS_HWA8_prod3_buf_control,Controlling producer socket3 buffer for HWA8" hexmask.long.byte 0x64 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x64 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x64 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x68 "HTS__S_VBUSP__REGS_HWA8_prod3_count,Defining count values for pre/post load for generating pend by HWA8 prod3" hexmask.long.word 0x68 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x68 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x68 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x6C "HTS__S_VBUSP__REGS_HWA8_pa3_control,control register to manage pattern adapter on HWA8 prod socket3" hexmask.long.word 0x6C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x6C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x6C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x6C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x6C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x70 "HTS__S_VBUSP__REGS_HWA8_pa3_prodcount,count values for HWA8 prod socket3" hexmask.long.word 0x70 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x70 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x74 "HTS__S_VBUSP__REGS_HWA8_prod4_control,Controlling producer socket4 for HWA8" bitfld.long 0x74 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 4. tdone_mask[mask_select] applies to prod_socket4" "0,1,2,3" newline hexmask.long.byte 0x74 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x74 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x78 "HTS__S_VBUSP__REGS_HWA8_prod4_buf_control,Controlling producer socket4 buffer for HWA8" hexmask.long.byte 0x78 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x78 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x78 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x7C "HTS__S_VBUSP__REGS_HWA8_prod4_count,Defining count values for pre/post load for generating pend by HWA8 prod4" hexmask.long.word 0x7C 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x7C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x7C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x668++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_HWA12_scheduler_control,Scheduler Control Register" bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1" newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA12" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA12 Scheduler resources must not be read during halted state. '1'-> HWA12 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA12 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA12 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA12_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x678++0x4F line.long 0x0 "HTS__S_VBUSP__REGS_HWA12_cons0_control,Controlling consumer socket 0 for HWA12" bitfld.long 0x0 31. "EHWA_PROD,'1' -> spare consumer is connected to external host producer '0' --> no external host producer" "0,1" newline bitfld.long 0x0 30. "SET_PEND,writing '1' sets pend on consumer socket" "0,1" newline hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA12 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA12_cons1_control,Controlling consumer socket 1 for HWA12" hexmask.long.word 0x4 1.--9. 1. "PROD_SELECT,producer select for HWA12 cons socket 1" newline bitfld.long 0x4 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA12_prod0_control,Controlling producer socket0 for HWA12" bitfld.long 0x8 31. "EHWA_CONS,'1' -> spare consumer is connected to external host consumer '0' --> no external host consumer" "0,1" newline bitfld.long 0x8 30. "PROD_DEC,writing '1' decrement prod count value" "0,1" newline hexmask.long.byte 0x8 1.--8. 1. "CONS_SELECT,consumer select for HWA12 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x8 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA12_prod0_buf_control,Controlling producer socket0 buffer for HWA12" hexmask.long.byte 0xC 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0xC 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0xC 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x10 "HTS__S_VBUSP__REGS_HWA12_prod0_count,Defining count values for pre/post load for generating pend by HWA12 prod0" hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x14 "HTS__S_VBUSP__REGS_HWA12_pa0_control,control register to manage pattern adapter on HWA12 prod socket0" hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x18 "HTS__S_VBUSP__REGS_HWA12_pa0_prodcount,count values for HWA12 prod socket0" hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x18 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x1C "HTS__S_VBUSP__REGS_HWA12_prod1_control,Controlling producer socket1 for HWA12" hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA12 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x20 "HTS__S_VBUSP__REGS_HWA12_prod1_buf_control,Controlling producer socket1 buffer for HWA12" hexmask.long.byte 0x20 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x24 "HTS__S_VBUSP__REGS_HWA12_prod1_count,Defining count values for pre/post load for generating pend by HWA12 prod1" hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x28 "HTS__S_VBUSP__REGS_HWA12_pa1_control,control register to manage pattern adapter on HWA12 prod socket1" hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x2C "HTS__S_VBUSP__REGS_HWA12_pa1_prodcount,count values for HWA12 prod socket1" hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x2C 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x30 "HTS__S_VBUSP__REGS_HWA12_prod2_control,Controlling producer socket2 for HWA12" hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA12 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x34 "HTS__S_VBUSP__REGS_HWA12_prod2_buf_control,Controlling producer socket2 buffer for HWA12" hexmask.long.byte 0x34 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x38 "HTS__S_VBUSP__REGS_HWA12_prod2_count,Defining count values for pre/post load for generating pend by HWA12 prod2" hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x3C "HTS__S_VBUSP__REGS_HWA12_pa2_control,control register to manage pattern adapter on HWA12 prod socket2" hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x40 "HTS__S_VBUSP__REGS_HWA12_pa2_prodcount,count values for HWA12 prod socket2" hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x40 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x44 "HTS__S_VBUSP__REGS_HWA12_prod3_control,Controlling producer socket3 for HWA12" hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA12 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x48 "HTS__S_VBUSP__REGS_HWA12_prod3_buf_control,Controlling producer socket3 buffer for HWA12" hexmask.long.byte 0x48 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x4C "HTS__S_VBUSP__REGS_HWA12_prod3_count,Defining count values for pre/post load for generating pend by HWA12 prod3" hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x6D0++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_HWA13_scheduler_control,Scheduler Control Register" bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1" newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA13" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA13 Scheduler resources must not be read during halted state. '1'-> HWA13 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA13 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA13 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA13_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x6E0++0x4F line.long 0x0 "HTS__S_VBUSP__REGS_HWA13_cons0_control,Controlling consumer socket 0 for HWA13" bitfld.long 0x0 31. "EHWA_PROD,'1' -> spare consumer is connected to external host producer '0' --> no external host producer" "0,1" newline bitfld.long 0x0 30. "SET_PEND,writing '1' sets pend on consumer socket" "0,1" newline hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA13 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA13_cons1_control,Controlling consumer socket 1 for HWA13" hexmask.long.word 0x4 1.--9. 1. "PROD_SELECT,producer select for HWA13 cons socket 1" newline bitfld.long 0x4 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA13_prod0_control,Controlling producer socket0 for HWA13" bitfld.long 0x8 31. "EHWA_CONS,'1' -> spare consumer is connected to external host consumer '0' --> no external host consumer" "0,1" newline bitfld.long 0x8 30. "PROD_DEC,writing '1' decrement prod count value" "0,1" newline hexmask.long.byte 0x8 1.--8. 1. "CONS_SELECT,consumer select for HWA13 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x8 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA13_prod0_buf_control,Controlling producer socket0 buffer for HWA13" hexmask.long.byte 0xC 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0xC 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0xC 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x10 "HTS__S_VBUSP__REGS_HWA13_prod0_count,Defining count values for pre/post load for generating pend by HWA13 prod0" hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x14 "HTS__S_VBUSP__REGS_HWA13_pa0_control,control register to manage pattern adapter on HWA13 prod socket0" hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x18 "HTS__S_VBUSP__REGS_HWA13_pa0_prodcount,count values for HWA13 prod socket0" hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x18 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x1C "HTS__S_VBUSP__REGS_HWA13_prod1_control,Controlling producer socket1 for HWA13" hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA13 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x20 "HTS__S_VBUSP__REGS_HWA13_prod1_buf_control,Controlling producer socket1 buffer for HWA13" hexmask.long.byte 0x20 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x24 "HTS__S_VBUSP__REGS_HWA13_prod1_count,Defining count values for pre/post load for generating pend by HWA13 prod1" hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x28 "HTS__S_VBUSP__REGS_HWA13_pa1_control,control register to manage pattern adapter on HWA13 prod socket1" hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x2C "HTS__S_VBUSP__REGS_HWA13_pa1_prodcount,count values for HWA13 prod socket1" hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x2C 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x30 "HTS__S_VBUSP__REGS_HWA13_prod2_control,Controlling producer socket2 for HWA13" hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA13 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x34 "HTS__S_VBUSP__REGS_HWA13_prod2_buf_control,Controlling producer socket2 buffer for HWA13" hexmask.long.byte 0x34 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x38 "HTS__S_VBUSP__REGS_HWA13_prod2_count,Defining count values for pre/post load for generating pend by HWA13 prod2" hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x3C "HTS__S_VBUSP__REGS_HWA13_pa2_control,control register to manage pattern adapter on HWA13 prod socket2" hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x40 "HTS__S_VBUSP__REGS_HWA13_pa2_prodcount,count values for HWA13 prod socket2" hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x40 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x44 "HTS__S_VBUSP__REGS_HWA13_prod3_control,Controlling producer socket3 for HWA13" hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA13 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x48 "HTS__S_VBUSP__REGS_HWA13_prod3_buf_control,Controlling producer socket3 buffer for HWA13" hexmask.long.byte 0x48 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x4C "HTS__S_VBUSP__REGS_HWA13_prod3_count,Defining count values for pre/post load for generating pend by HWA13 prod3" hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x738++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_HWA14_scheduler_control,Scheduler Control Register" bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1" newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA14" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA14 Scheduler resources must not be read during halted state. '1'-> HWA14 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA14 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA14 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA14_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x748++0x4F line.long 0x0 "HTS__S_VBUSP__REGS_HWA14_cons0_control,Controlling consumer socket 0 for HWA14" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA14 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA14_cons1_control,Controlling consumer socket 1 for HWA14" hexmask.long.word 0x4 1.--9. 1. "PROD_SELECT,producer select for HWA14 cons socket 1" newline bitfld.long 0x4 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA14_prod0_control,Controlling producer socket0 for HWA14" hexmask.long.byte 0x8 1.--8. 1. "CONS_SELECT,consumer select for HWA14 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x8 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA14_prod0_buf_control,Controlling producer socket0 buffer for HWA14" hexmask.long.byte 0xC 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0xC 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0xC 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x10 "HTS__S_VBUSP__REGS_HWA14_prod0_count,Defining count values for pre/post load for generating pend by HWA14 prod0" hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x14 "HTS__S_VBUSP__REGS_HWA14_pa0_control,control register to manage pattern adapter on HWA14 prod socket0" hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x18 "HTS__S_VBUSP__REGS_HWA14_pa0_prodcount,count values for HWA14 prod socket0" hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x18 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x1C "HTS__S_VBUSP__REGS_HWA14_prod1_control,Controlling producer socket1 for HWA14" hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA14 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x20 "HTS__S_VBUSP__REGS_HWA14_prod1_buf_control,Controlling producer socket1 buffer for HWA14" hexmask.long.byte 0x20 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x24 "HTS__S_VBUSP__REGS_HWA14_prod1_count,Defining count values for pre/post load for generating pend by HWA14 prod1" hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x28 "HTS__S_VBUSP__REGS_HWA14_pa1_control,control register to manage pattern adapter on HWA14 prod socket1" hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x2C "HTS__S_VBUSP__REGS_HWA14_pa1_prodcount,count values for HWA14 prod socket1" hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x2C 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x30 "HTS__S_VBUSP__REGS_HWA14_prod2_control,Controlling producer socket2 for HWA14" hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA14 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x34 "HTS__S_VBUSP__REGS_HWA14_prod2_buf_control,Controlling producer socket2 buffer for HWA14" hexmask.long.byte 0x34 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x38 "HTS__S_VBUSP__REGS_HWA14_prod2_count,Defining count values for pre/post load for generating pend by HWA14 prod2" hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x3C "HTS__S_VBUSP__REGS_HWA14_pa2_control,control register to manage pattern adapter on HWA14 prod socket2" hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x40 "HTS__S_VBUSP__REGS_HWA14_pa2_prodcount,count values for HWA14 prod socket2" hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x40 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x44 "HTS__S_VBUSP__REGS_HWA14_prod3_control,Controlling producer socket3 for HWA14" hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA14 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x48 "HTS__S_VBUSP__REGS_HWA14_prod3_buf_control,Controlling producer socket3 buffer for HWA14" hexmask.long.byte 0x48 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x4C "HTS__S_VBUSP__REGS_HWA14_prod3_count,Defining count values for pre/post load for generating pend by HWA14 prod3" hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x7A0++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_HWA15_scheduler_control,Scheduler Control Register" bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1" newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA15" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA15 Scheduler resources must not be read during halted state. '1'-> HWA15 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA15 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA15 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA15_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x7B0++0x4F line.long 0x0 "HTS__S_VBUSP__REGS_HWA15_cons0_control,Controlling consumer socket 0 for HWA15" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA15 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA15_cons1_control,Controlling consumer socket 1 for HWA15" hexmask.long.word 0x4 1.--9. 1. "PROD_SELECT,producer select for HWA15 cons socket 1" newline bitfld.long 0x4 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA15_prod0_control,Controlling producer socket0 for HWA15" hexmask.long.byte 0x8 1.--8. 1. "CONS_SELECT,consumer select for HWA15 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x8 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA15_prod0_buf_control,Controlling producer socket0 buffer for HWA15" hexmask.long.byte 0xC 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0xC 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0xC 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x10 "HTS__S_VBUSP__REGS_HWA15_prod0_count,Defining count values for pre/post load for generating pend by HWA15 prod0" hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x14 "HTS__S_VBUSP__REGS_HWA15_pa0_control,control register to manage pattern adapter on HWA15 prod socket0" hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x18 "HTS__S_VBUSP__REGS_HWA15_pa0_prodcount,count values for HWA15 prod socket0" hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x18 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x1C "HTS__S_VBUSP__REGS_HWA15_prod1_control,Controlling producer socket1 for HWA15" hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA15 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x20 "HTS__S_VBUSP__REGS_HWA15_prod1_buf_control,Controlling producer socket1 buffer for HWA15" hexmask.long.byte 0x20 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x24 "HTS__S_VBUSP__REGS_HWA15_prod1_count,Defining count values for pre/post load for generating pend by HWA15 prod1" hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x28 "HTS__S_VBUSP__REGS_HWA15_pa1_control,control register to manage pattern adapter on HWA15 prod socket1" hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x2C "HTS__S_VBUSP__REGS_HWA15_pa1_prodcount,count values for HWA15 prod socket1" hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x2C 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x30 "HTS__S_VBUSP__REGS_HWA15_prod2_control,Controlling producer socket2 for HWA15" hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA15 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x34 "HTS__S_VBUSP__REGS_HWA15_prod2_buf_control,Controlling producer socket2 buffer for HWA15" hexmask.long.byte 0x34 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x38 "HTS__S_VBUSP__REGS_HWA15_prod2_count,Defining count values for pre/post load for generating pend by HWA15 prod2" hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x3C "HTS__S_VBUSP__REGS_HWA15_pa2_control,control register to manage pattern adapter on HWA15 prod socket2" hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x40 "HTS__S_VBUSP__REGS_HWA15_pa2_prodcount,count values for HWA15 prod socket2" hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x40 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x44 "HTS__S_VBUSP__REGS_HWA15_prod3_control,Controlling producer socket3 for HWA15" hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA15 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x48 "HTS__S_VBUSP__REGS_HWA15_prod3_buf_control,Controlling producer socket3 buffer for HWA15" hexmask.long.byte 0x48 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x4C "HTS__S_VBUSP__REGS_HWA15_prod3_count,Defining count values for pre/post load for generating pend by HWA15 prod3" hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x808++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_HWA16_scheduler_control,Scheduler Control Register" bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1" newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA16" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA16 Scheduler resources must not be read during halted state. '1'-> HWA16 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA16 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA16 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA16_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x818++0x4F line.long 0x0 "HTS__S_VBUSP__REGS_HWA16_cons0_control,Controlling consumer socket 0 for HWA16" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA16 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA16_cons1_control,Controlling consumer socket 1 for HWA16" hexmask.long.word 0x4 1.--9. 1. "PROD_SELECT,producer select for HWA16 cons socket 1" newline bitfld.long 0x4 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA16_prod0_control,Controlling producer socket0 for HWA16" hexmask.long.byte 0x8 1.--8. 1. "CONS_SELECT,consumer select for HWA16 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x8 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA16_prod0_buf_control,Controlling producer socket0 buffer for HWA16" hexmask.long.byte 0xC 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0xC 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0xC 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x10 "HTS__S_VBUSP__REGS_HWA16_prod0_count,Defining count values for pre/post load for generating pend by HWA16 prod0" hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x14 "HTS__S_VBUSP__REGS_HWA16_pa0_control,control register to manage pattern adapter on HWA16 prod socket0" hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x18 "HTS__S_VBUSP__REGS_HWA16_pa0_prodcount,count values for HWA16 prod socket0" hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x18 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x1C "HTS__S_VBUSP__REGS_HWA16_prod1_control,Controlling producer socket1 for HWA16" hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA16 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x20 "HTS__S_VBUSP__REGS_HWA16_prod1_buf_control,Controlling producer socket1 buffer for HWA16" hexmask.long.byte 0x20 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x24 "HTS__S_VBUSP__REGS_HWA16_prod1_count,Defining count values for pre/post load for generating pend by HWA16 prod1" hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x28 "HTS__S_VBUSP__REGS_HWA16_pa1_control,control register to manage pattern adapter on HWA16 prod socket1" hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x2C "HTS__S_VBUSP__REGS_HWA16_pa1_prodcount,count values for HWA16 prod socket1" hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x2C 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x30 "HTS__S_VBUSP__REGS_HWA16_prod2_control,Controlling producer socket2 for HWA16" hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA16 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x34 "HTS__S_VBUSP__REGS_HWA16_prod2_buf_control,Controlling producer socket2 buffer for HWA16" hexmask.long.byte 0x34 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x38 "HTS__S_VBUSP__REGS_HWA16_prod2_count,Defining count values for pre/post load for generating pend by HWA16 prod2" hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x3C "HTS__S_VBUSP__REGS_HWA16_pa2_control,control register to manage pattern adapter on HWA16 prod socket2" hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x40 "HTS__S_VBUSP__REGS_HWA16_pa2_prodcount,count values for HWA16 prod socket2" hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x40 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x44 "HTS__S_VBUSP__REGS_HWA16_prod3_control,Controlling producer socket3 for HWA16" hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA16 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x48 "HTS__S_VBUSP__REGS_HWA16_prod3_buf_control,Controlling producer socket3 buffer for HWA16" hexmask.long.byte 0x48 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x4C "HTS__S_VBUSP__REGS_HWA16_prod3_count,Defining count values for pre/post load for generating pend by HWA16 prod3" hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x870++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_HWA17_scheduler_control,Scheduler Control Register" bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1" newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA17" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA17 Scheduler resources must not be read during halted state. '1'-> HWA17 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA17 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA17 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA17_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x880++0x4F line.long 0x0 "HTS__S_VBUSP__REGS_HWA17_cons0_control,Controlling consumer socket 0 for HWA17" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA17 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA17_cons1_control,Controlling consumer socket 1 for HWA17" hexmask.long.word 0x4 1.--9. 1. "PROD_SELECT,producer select for HWA17 cons socket 1" newline bitfld.long 0x4 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA17_prod0_control,Controlling producer socket0 for HWA17" hexmask.long.byte 0x8 1.--8. 1. "CONS_SELECT,consumer select for HWA17 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x8 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA17_prod0_buf_control,Controlling producer socket0 buffer for HWA17" hexmask.long.byte 0xC 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0xC 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0xC 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x10 "HTS__S_VBUSP__REGS_HWA17_prod0_count,Defining count values for pre/post load for generating pend by HWA17 prod0" hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x14 "HTS__S_VBUSP__REGS_HWA17_pa0_control,control register to manage pattern adapter on HWA17 prod socket0" hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x18 "HTS__S_VBUSP__REGS_HWA17_pa0_prodcount,count values for HWA17 prod socket0" hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x18 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x1C "HTS__S_VBUSP__REGS_HWA17_prod1_control,Controlling producer socket1 for HWA17" hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA17 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x20 "HTS__S_VBUSP__REGS_HWA17_prod1_buf_control,Controlling producer socket1 buffer for HWA17" hexmask.long.byte 0x20 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x24 "HTS__S_VBUSP__REGS_HWA17_prod1_count,Defining count values for pre/post load for generating pend by HWA17 prod1" hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x28 "HTS__S_VBUSP__REGS_HWA17_pa1_control,control register to manage pattern adapter on HWA17 prod socket1" hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x2C "HTS__S_VBUSP__REGS_HWA17_pa1_prodcount,count values for HWA17 prod socket1" hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x2C 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x30 "HTS__S_VBUSP__REGS_HWA17_prod2_control,Controlling producer socket2 for HWA17" hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA17 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x34 "HTS__S_VBUSP__REGS_HWA17_prod2_buf_control,Controlling producer socket2 buffer for HWA17" hexmask.long.byte 0x34 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x38 "HTS__S_VBUSP__REGS_HWA17_prod2_count,Defining count values for pre/post load for generating pend by HWA17 prod2" hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x3C "HTS__S_VBUSP__REGS_HWA17_pa2_control,control register to manage pattern adapter on HWA17 prod socket2" hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x40 "HTS__S_VBUSP__REGS_HWA17_pa2_prodcount,count values for HWA17 prod socket2" hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x40 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x44 "HTS__S_VBUSP__REGS_HWA17_prod3_control,Controlling producer socket3 for HWA17" hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA17 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x48 "HTS__S_VBUSP__REGS_HWA17_prod3_buf_control,Controlling producer socket3 buffer for HWA17" hexmask.long.byte 0x48 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x4C "HTS__S_VBUSP__REGS_HWA17_prod3_count,Defining count values for pre/post load for generating pend by HWA17 prod3" hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x8D8++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_HWA18_scheduler_control,Scheduler Control Register" bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1" newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA18" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA18 Scheduler resources must not be read during halted state. '1'-> HWA18 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA18 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA18 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA18_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x8E8++0x4F line.long 0x0 "HTS__S_VBUSP__REGS_HWA18_cons0_control,Controlling consumer socket 0 for HWA18" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA18 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA18_cons1_control,Controlling consumer socket 1 for HWA18" hexmask.long.word 0x4 1.--9. 1. "PROD_SELECT,producer select for HWA18 cons socket 1" newline bitfld.long 0x4 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA18_prod0_control,Controlling producer socket0 for HWA18" hexmask.long.byte 0x8 1.--8. 1. "CONS_SELECT,consumer select for HWA18 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x8 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA18_prod0_buf_control,Controlling producer socket0 buffer for HWA18" hexmask.long.byte 0xC 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0xC 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0xC 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x10 "HTS__S_VBUSP__REGS_HWA18_prod0_count,Defining count values for pre/post load for generating pend by HWA18 prod0" hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x14 "HTS__S_VBUSP__REGS_HWA18_pa0_control,control register to manage pattern adapter on HWA18 prod socket0" hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x18 "HTS__S_VBUSP__REGS_HWA18_pa0_prodcount,count values for HWA18 prod socket0" hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x18 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x1C "HTS__S_VBUSP__REGS_HWA18_prod1_control,Controlling producer socket1 for HWA18" hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA18 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x20 "HTS__S_VBUSP__REGS_HWA18_prod1_buf_control,Controlling producer socket1 buffer for HWA18" hexmask.long.byte 0x20 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x24 "HTS__S_VBUSP__REGS_HWA18_prod1_count,Defining count values for pre/post load for generating pend by HWA18 prod1" hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x28 "HTS__S_VBUSP__REGS_HWA18_pa1_control,control register to manage pattern adapter on HWA18 prod socket1" hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x2C "HTS__S_VBUSP__REGS_HWA18_pa1_prodcount,count values for HWA18 prod socket1" hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x2C 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x30 "HTS__S_VBUSP__REGS_HWA18_prod2_control,Controlling producer socket2 for HWA18" hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA18 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x34 "HTS__S_VBUSP__REGS_HWA18_prod2_buf_control,Controlling producer socket2 buffer for HWA18" hexmask.long.byte 0x34 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x38 "HTS__S_VBUSP__REGS_HWA18_prod2_count,Defining count values for pre/post load for generating pend by HWA18 prod2" hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x3C "HTS__S_VBUSP__REGS_HWA18_pa2_control,control register to manage pattern adapter on HWA18 prod socket2" hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x40 "HTS__S_VBUSP__REGS_HWA18_pa2_prodcount,count values for HWA18 prod socket2" hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x40 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x44 "HTS__S_VBUSP__REGS_HWA18_prod3_control,Controlling producer socket3 for HWA18" hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA18 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x48 "HTS__S_VBUSP__REGS_HWA18_prod3_buf_control,Controlling producer socket3 buffer for HWA18" hexmask.long.byte 0x48 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x4C "HTS__S_VBUSP__REGS_HWA18_prod3_count,Defining count values for pre/post load for generating pend by HWA18 prod3" hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x940++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_HWA19_scheduler_control,Scheduler Control Register" bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1" newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA19" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA19 Scheduler resources must not be read during halted state. '1'-> HWA19 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA19 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA19 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA19_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x950++0x4F line.long 0x0 "HTS__S_VBUSP__REGS_HWA19_cons0_control,Controlling consumer socket 0 for HWA19" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA19 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA19_cons1_control,Controlling consumer socket 1 for HWA19" hexmask.long.word 0x4 1.--9. 1. "PROD_SELECT,producer select for HWA19 cons socket 1" newline bitfld.long 0x4 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA19_prod0_control,Controlling producer socket0 for HWA19" hexmask.long.byte 0x8 1.--8. 1. "CONS_SELECT,consumer select for HWA19 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x8 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA19_prod0_buf_control,Controlling producer socket0 buffer for HWA19" hexmask.long.byte 0xC 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0xC 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0xC 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x10 "HTS__S_VBUSP__REGS_HWA19_prod0_count,Defining count values for pre/post load for generating pend by HWA19 prod0" hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x14 "HTS__S_VBUSP__REGS_HWA19_pa0_control,control register to manage pattern adapter on HWA19 prod socket0" hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x18 "HTS__S_VBUSP__REGS_HWA19_pa0_prodcount,count values for HWA19 prod socket0" hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x18 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x1C "HTS__S_VBUSP__REGS_HWA19_prod1_control,Controlling producer socket1 for HWA19" hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA19 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x20 "HTS__S_VBUSP__REGS_HWA19_prod1_buf_control,Controlling producer socket1 buffer for HWA19" hexmask.long.byte 0x20 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x24 "HTS__S_VBUSP__REGS_HWA19_prod1_count,Defining count values for pre/post load for generating pend by HWA19 prod1" hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x28 "HTS__S_VBUSP__REGS_HWA19_pa1_control,control register to manage pattern adapter on HWA19 prod socket1" hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x2C "HTS__S_VBUSP__REGS_HWA19_pa1_prodcount,count values for HWA19 prod socket1" hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x2C 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x30 "HTS__S_VBUSP__REGS_HWA19_prod2_control,Controlling producer socket2 for HWA19" hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA19 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x34 "HTS__S_VBUSP__REGS_HWA19_prod2_buf_control,Controlling producer socket2 buffer for HWA19" hexmask.long.byte 0x34 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x38 "HTS__S_VBUSP__REGS_HWA19_prod2_count,Defining count values for pre/post load for generating pend by HWA19 prod2" hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0x3C "HTS__S_VBUSP__REGS_HWA19_pa2_control,control register to manage pattern adapter on HWA19 prod socket2" hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x40 "HTS__S_VBUSP__REGS_HWA19_pa2_prodcount,count values for HWA19 prod socket2" hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x40 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x44 "HTS__S_VBUSP__REGS_HWA19_prod3_control,Controlling producer socket3 for HWA19" hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA19 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x48 "HTS__S_VBUSP__REGS_HWA19_prod3_buf_control,Controlling producer socket3 buffer for HWA19" hexmask.long.byte 0x48 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x4C "HTS__S_VBUSP__REGS_HWA19_prod3_count,Defining count values for pre/post load for generating pend by HWA19 prod3" hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x9A8++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA0_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA0" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA0 Scheduler resources must not be read during halted state. '1'-> DMA0 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA0 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA0 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA0_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x9B8++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_DMA0_prod0_control,Controlling producer socket0 for DMA0" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA0 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA0_prod0_buf_control,Controlling producer socket0 buffer for DMA0" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA0_prod0_count,Defining count values for pre/post load for generating pend by DMA0 prod0" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_DMA1_scheduler_control,Scheduler Control Register" hexmask.long.byte 0xC 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA1" newline bitfld.long 0xC 12. "DEBUG_RDY,'0' -> DMA1 Scheduler resources must not be read during halted state. '1'-> DMA1 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0xC 7.--10. 1. "STATE,Current state of DMA1 Scheduler" newline bitfld.long 0xC 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0xC 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0xC 1.--3. "PIPELINE_NUM,Pipeline Number of DMA1 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_DMA1_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x9D4++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_DMA1_prod0_control,Controlling producer socket0 for DMA1" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA1 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA1_prod0_buf_control,Controlling producer socket0 buffer for DMA1" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA1_prod0_count,Defining count values for pre/post load for generating pend by DMA1 prod0" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_DMA2_scheduler_control,Scheduler Control Register" hexmask.long.byte 0xC 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA2" newline bitfld.long 0xC 12. "DEBUG_RDY,'0' -> DMA2 Scheduler resources must not be read during halted state. '1'-> DMA2 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0xC 7.--10. 1. "STATE,Current state of DMA2 Scheduler" newline bitfld.long 0xC 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0xC 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0xC 1.--3. "PIPELINE_NUM,Pipeline Number of DMA2 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_DMA2_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x9F0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_DMA2_prod0_control,Controlling producer socket0 for DMA2" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA2 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA2_prod0_buf_control,Controlling producer socket0 buffer for DMA2" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA2_prod0_count,Defining count values for pre/post load for generating pend by DMA2 prod0" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_DMA3_scheduler_control,Scheduler Control Register" hexmask.long.byte 0xC 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA3" newline bitfld.long 0xC 12. "DEBUG_RDY,'0' -> DMA3 Scheduler resources must not be read during halted state. '1'-> DMA3 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0xC 7.--10. 1. "STATE,Current state of DMA3 Scheduler" newline bitfld.long 0xC 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0xC 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0xC 1.--3. "PIPELINE_NUM,Pipeline Number of DMA3 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_DMA3_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0xA0C++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_DMA3_prod0_control,Controlling producer socket0 for DMA3" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA3 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA3_prod0_buf_control,Controlling producer socket0 buffer for DMA3" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA3_prod0_count,Defining count values for pre/post load for generating pend by DMA3 prod0" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_DMA4_scheduler_control,Scheduler Control Register" hexmask.long.byte 0xC 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA4" newline bitfld.long 0xC 12. "DEBUG_RDY,'0' -> DMA4 Scheduler resources must not be read during halted state. '1'-> DMA4 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0xC 7.--10. 1. "STATE,Current state of DMA4 Scheduler" newline bitfld.long 0xC 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0xC 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0xC 1.--3. "PIPELINE_NUM,Pipeline Number of DMA4 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_DMA4_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0xA28++0xB line.long 0x0 "HTS__S_VBUSP__REGS_DMA4_prod0_control,Controlling producer socket0 for DMA4" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA4 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA4_prod0_buf_control,Controlling producer socket0 buffer for DMA4" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA4_prod0_count,Defining count values for pre/post load for generating pend by DMA4 prod0" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xA88++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA8_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA8" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA8 Scheduler resources must not be read during halted state. '1'-> DMA8 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA8 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA8 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA8_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0xA98++0x1B line.long 0x0 "HTS__S_VBUSP__REGS_DMA8_prod0_control,Controlling producer socket0 for DMA8" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA8 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA8_prod0_buf_control,Controlling producer socket0 buffer for DMA8" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA8_prod0_count,Defining count values for pre/post load for generating pend by DMA8 prod0" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_DMA8_pa0_control,control register to manage pattern adapter on DMA8 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_DMA8_pa0_prodcount,count values for HWA8 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x14 "HTS__S_VBUSP__REGS_DMA9_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x14 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA9" newline bitfld.long 0x14 12. "DEBUG_RDY,'0' -> DMA9 Scheduler resources must not be read during halted state. '1'-> DMA9 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x14 7.--10. 1. "STATE,Current state of DMA9 Scheduler" newline bitfld.long 0x14 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x14 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x14 1.--3. "PIPELINE_NUM,Pipeline Number of DMA9 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x18 "HTS__S_VBUSP__REGS_DMA9_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x18 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x18 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0xABC++0x1B line.long 0x0 "HTS__S_VBUSP__REGS_DMA9_prod0_control,Controlling producer socket0 for DMA9" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA9 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA9_prod0_buf_control,Controlling producer socket0 buffer for DMA9" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA9_prod0_count,Defining count values for pre/post load for generating pend by DMA9 prod0" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_DMA9_pa0_control,control register to manage pattern adapter on DMA9 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_DMA9_pa0_prodcount,count values for HWA9 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" line.long 0x14 "HTS__S_VBUSP__REGS_DMA10_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x14 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA10" newline bitfld.long 0x14 12. "DEBUG_RDY,'0' -> DMA10 Scheduler resources must not be read during halted state. '1'-> DMA10 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x14 7.--10. 1. "STATE,Current state of DMA10 Scheduler" newline bitfld.long 0x14 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x14 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x14 1.--3. "PIPELINE_NUM,Pipeline Number of DMA10 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x18 "HTS__S_VBUSP__REGS_DMA10_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x18 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x18 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0xAE0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_DMA10_prod0_control,Controlling producer socket0 for DMA10" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA10 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA10_prod0_buf_control,Controlling producer socket0 buffer for DMA10" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA10_prod0_count,Defining count values for pre/post load for generating pend by DMA10 prod0" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_DMA10_pa0_control,control register to manage pattern adapter on DMA10 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_DMA10_pa0_prodcount,count values for HWA10 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0xD40++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA32_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA32" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA32 Scheduler resources must not be read during halted state. '1'-> DMA32 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA32 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA32 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA32_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0xD50++0xB line.long 0x0 "HTS__S_VBUSP__REGS_DMA32_prod0_control,Controlling producer socket0 for DMA32" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA32 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA32_prod0_buf_control,Controlling producer socket0 buffer for DMA32" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA32_prod0_count,Defining count values for pre/post load for generating pend by DMA32 prod0" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xE20++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA40_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA40" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA40 Scheduler resources must not be read during halted state. '1'-> DMA40 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA40 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA40 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA40_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0xE30++0xB line.long 0x0 "HTS__S_VBUSP__REGS_DMA40_prod0_control,Controlling producer socket0 for DMA40" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA40 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA40_prod0_buf_control,Controlling producer socket0 buffer for DMA40" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA40_prod0_count,Defining count values for pre/post load for generating pend by DMA40 prod0" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xF00++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA48_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA48" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA48 Scheduler resources must not be read during halted state. '1'-> DMA48 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA48 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA48 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA48_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0xF10++0xB line.long 0x0 "HTS__S_VBUSP__REGS_DMA48_prod0_control,Controlling producer socket0 for DMA48" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA48 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA48_prod0_buf_control,Controlling producer socket0 buffer for DMA48" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA48_prod0_count,Defining count values for pre/post load for generating pend by DMA48 prod0" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xFE0++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA56_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA56" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA56 Scheduler resources must not be read during halted state. '1'-> DMA56 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA56 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA56 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA56_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0xFF0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_DMA56_prod0_control,Controlling producer socket0 for DMA56" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA56 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA56_prod0_buf_control,Controlling producer socket0 buffer for DMA56" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA56_prod0_count,Defining count values for pre/post load for generating pend by DMA56 prod0" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_DMA57_scheduler_control,Scheduler Control Register" hexmask.long.byte 0xC 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA57" newline bitfld.long 0xC 12. "DEBUG_RDY,'0' -> DMA57 Scheduler resources must not be read during halted state. '1'-> DMA57 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0xC 7.--10. 1. "STATE,Current state of DMA57 Scheduler" newline bitfld.long 0xC 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0xC 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0xC 1.--3. "PIPELINE_NUM,Pipeline Number of DMA57 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_DMA57_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x100C++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_DMA57_prod0_control,Controlling producer socket0 for DMA57" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA57 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA57_prod0_buf_control,Controlling producer socket0 buffer for DMA57" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA57_prod0_count,Defining count values for pre/post load for generating pend by DMA57 prod0" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_DMA58_scheduler_control,Scheduler Control Register" hexmask.long.byte 0xC 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA58" newline bitfld.long 0xC 12. "DEBUG_RDY,'0' -> DMA58 Scheduler resources must not be read during halted state. '1'-> DMA58 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0xC 7.--10. 1. "STATE,Current state of DMA58 Scheduler" newline bitfld.long 0xC 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0xC 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0xC 1.--3. "PIPELINE_NUM,Pipeline Number of DMA58 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_DMA58_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x1028++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_DMA58_prod0_control,Controlling producer socket0 for DMA58" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA58 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA58_prod0_buf_control,Controlling producer socket0 buffer for DMA58" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA58_prod0_count,Defining count values for pre/post load for generating pend by DMA58 prod0" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_DMA59_scheduler_control,Scheduler Control Register" hexmask.long.byte 0xC 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA59" newline bitfld.long 0xC 12. "DEBUG_RDY,'0' -> DMA59 Scheduler resources must not be read during halted state. '1'-> DMA59 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0xC 7.--10. 1. "STATE,Current state of DMA59 Scheduler" newline bitfld.long 0xC 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0xC 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0xC 1.--3. "PIPELINE_NUM,Pipeline Number of DMA59 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_DMA59_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x1044++0xB line.long 0x0 "HTS__S_VBUSP__REGS_DMA59_prod0_control,Controlling producer socket0 for DMA59" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA59 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA59_prod0_buf_control,Controlling producer socket0 buffer for DMA59" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA59_prod0_count,Defining count values for pre/post load for generating pend by DMA59 prod0" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x10C0++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA64_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA64" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA64 Scheduler resources must not be read during halted state. '1'-> DMA64 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA64 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA64 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA64_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x10D0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_DMA64_prod0_control,Controlling producer socket0 for DMA64" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA64 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA64_prod0_buf_control,Controlling producer socket0 buffer for DMA64" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA64_prod0_count,Defining count values for pre/post load for generating pend by DMA64 prod0" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_DMA65_scheduler_control,Scheduler Control Register" hexmask.long.byte 0xC 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA65" newline bitfld.long 0xC 12. "DEBUG_RDY,'0' -> DMA65 Scheduler resources must not be read during halted state. '1'-> DMA65 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0xC 7.--10. 1. "STATE,Current state of DMA65 Scheduler" newline bitfld.long 0xC 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0xC 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0xC 1.--3. "PIPELINE_NUM,Pipeline Number of DMA65 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_DMA65_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x10EC++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_DMA65_prod0_control,Controlling producer socket0 for DMA65" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA65 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA65_prod0_buf_control,Controlling producer socket0 buffer for DMA65" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA65_prod0_count,Defining count values for pre/post load for generating pend by DMA65 prod0" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_DMA66_scheduler_control,Scheduler Control Register" hexmask.long.byte 0xC 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA66" newline bitfld.long 0xC 12. "DEBUG_RDY,'0' -> DMA66 Scheduler resources must not be read during halted state. '1'-> DMA66 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0xC 7.--10. 1. "STATE,Current state of DMA66 Scheduler" newline bitfld.long 0xC 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0xC 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0xC 1.--3. "PIPELINE_NUM,Pipeline Number of DMA66 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_DMA66_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x1108++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_DMA66_prod0_control,Controlling producer socket0 for DMA66" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA66 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA66_prod0_buf_control,Controlling producer socket0 buffer for DMA66" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA66_prod0_count,Defining count values for pre/post load for generating pend by DMA66 prod0" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_DMA67_scheduler_control,Scheduler Control Register" hexmask.long.byte 0xC 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA67" newline bitfld.long 0xC 12. "DEBUG_RDY,'0' -> DMA67 Scheduler resources must not be read during halted state. '1'-> DMA67 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0xC 7.--10. 1. "STATE,Current state of DMA67 Scheduler" newline bitfld.long 0xC 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0xC 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0xC 1.--3. "PIPELINE_NUM,Pipeline Number of DMA67 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_DMA67_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x1124++0xB line.long 0x0 "HTS__S_VBUSP__REGS_DMA67_prod0_control,Controlling producer socket0 for DMA67" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA67 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA67_prod0_buf_control,Controlling producer socket0 buffer for DMA67" hexmask.long.byte 0x4 21.--26. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.byte 0x4 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA67_prod0_count,Defining count values for pre/post load for generating pend by DMA67 prod0" hexmask.long.word 0x8 16.--28. 1. "COUNT,current count value" newline hexmask.long.byte 0x8 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.byte 0x8 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x21B4++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA240_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA240" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA240 Scheduler resources must not be read during halted state. '1'-> DMA240 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA240 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA240 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x21C4++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA240_cons0_control,Controlling consumer socket 0 for DMA240" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA240 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA241_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA241" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA241 Scheduler resources must not be read during halted state. '1'-> DMA241 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA241 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA241 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x21D8++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA241_cons0_control,Controlling consumer socket 0 for DMA241" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA241 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA242_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA242" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA242 Scheduler resources must not be read during halted state. '1'-> DMA242 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA242 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA242 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x21EC++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA242_cons0_control,Controlling consumer socket 0 for DMA242" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA242 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA243_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA243" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA243 Scheduler resources must not be read during halted state. '1'-> DMA243 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA243 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA243 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x2200++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA243_cons0_control,Controlling consumer socket 0 for DMA243" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA243 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA244_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA244" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA244 Scheduler resources must not be read during halted state. '1'-> DMA244 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA244 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA244 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x2214++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA244_cons0_control,Controlling consumer socket 0 for DMA244" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA244 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA245_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA245" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA245 Scheduler resources must not be read during halted state. '1'-> DMA245 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA245 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA245 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x2228++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA245_cons0_control,Controlling consumer socket 0 for DMA245" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA245 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA256_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA256" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA256 Scheduler resources must not be read during halted state. '1'-> DMA256 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA256 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA256 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x223C++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA256_cons0_control,Controlling consumer socket 0 for DMA256" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA256 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA257_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA257" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA257 Scheduler resources must not be read during halted state. '1'-> DMA257 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA257 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA257 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x2250++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA257_cons0_control,Controlling consumer socket 0 for DMA257" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA257 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA258_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA258" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA258 Scheduler resources must not be read during halted state. '1'-> DMA258 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA258 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA258 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x2264++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA258_cons0_control,Controlling consumer socket 0 for DMA258" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA258 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA259_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA259" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA259 Scheduler resources must not be read during halted state. '1'-> DMA259 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA259 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA259 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x2278++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA259_cons0_control,Controlling consumer socket 0 for DMA259" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA259 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA260_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA260" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA260 Scheduler resources must not be read during halted state. '1'-> DMA260 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA260 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA260 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x228C++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA260_cons0_control,Controlling consumer socket 0 for DMA260" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA260 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA261_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA261" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA261 Scheduler resources must not be read during halted state. '1'-> DMA261 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA261 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA261 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x22A0++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA261_cons0_control,Controlling consumer socket 0 for DMA261" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA261 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA272_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA272" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA272 Scheduler resources must not be read during halted state. '1'-> DMA272 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA272 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA272 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x22B4++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA272_cons0_control,Controlling consumer socket 0 for DMA272" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA272 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA273_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA273" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA273 Scheduler resources must not be read during halted state. '1'-> DMA273 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA273 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA273 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x22C8++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA273_cons0_control,Controlling consumer socket 0 for DMA273" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA273 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA274_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA274" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA274 Scheduler resources must not be read during halted state. '1'-> DMA274 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA274 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA274 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x22DC++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA274_cons0_control,Controlling consumer socket 0 for DMA274" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA274 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA275_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA275" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA275 Scheduler resources must not be read during halted state. '1'-> DMA275 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA275 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA275 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x22F0++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA275_cons0_control,Controlling consumer socket 0 for DMA275" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA275 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA288_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA288" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA288 Scheduler resources must not be read during halted state. '1'-> DMA288 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA288 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA288 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x2304++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA288_cons0_control,Controlling consumer socket 0 for DMA288" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA288 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA289_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA289" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA289 Scheduler resources must not be read during halted state. '1'-> DMA289 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA289 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA289 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x2318++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA289_cons0_control,Controlling consumer socket 0 for DMA289" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA289 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA290_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA290" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA290 Scheduler resources must not be read during halted state. '1'-> DMA290 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA290 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA290 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x232C++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA290_cons0_control,Controlling consumer socket 0 for DMA290" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA290 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA291_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA291" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA291 Scheduler resources must not be read during halted state. '1'-> DMA291 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA291 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA291 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x2340++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA291_cons0_control,Controlling consumer socket 0 for DMA291" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA291 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA304_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA304" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA304 Scheduler resources must not be read during halted state. '1'-> DMA304 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA304 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA304 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x2354++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA304_cons0_control,Controlling consumer socket 0 for DMA304" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA304 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA305_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA305" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA305 Scheduler resources must not be read during halted state. '1'-> DMA305 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA305 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA305 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x2368++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA305_cons0_control,Controlling consumer socket 0 for DMA305" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA305 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA306_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA306" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA306 Scheduler resources must not be read during halted state. '1'-> DMA306 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA306 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA306 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x237C++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA306_cons0_control,Controlling consumer socket 0 for DMA306" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA306 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA307_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA307" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA307 Scheduler resources must not be read during halted state. '1'-> DMA307 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA307 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA307 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x2390++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA307_cons0_control,Controlling consumer socket 0 for DMA307" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA307 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA308_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA308" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA308 Scheduler resources must not be read during halted state. '1'-> DMA308 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA308 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA308 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x23A4++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA308_cons0_control,Controlling consumer socket 0 for DMA308" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA308 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA309_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA309" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA309 Scheduler resources must not be read during halted state. '1'-> DMA309 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA309 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA309 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x23B8++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA309_cons0_control,Controlling consumer socket 0 for DMA309" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA309 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA310_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA310" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA310 Scheduler resources must not be read during halted state. '1'-> DMA310 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA310 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA310 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x23CC++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA310_cons0_control,Controlling consumer socket 0 for DMA310" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA310 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA311_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA311" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA311 Scheduler resources must not be read during halted state. '1'-> DMA311 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA311 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA311 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x23E0++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA311_cons0_control,Controlling consumer socket 0 for DMA311" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA311 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA312_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA312" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA312 Scheduler resources must not be read during halted state. '1'-> DMA312 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA312 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA312 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x23F4++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA312_cons0_control,Controlling consumer socket 0 for DMA312" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA312 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA313_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA313" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA313 Scheduler resources must not be read during halted state. '1'-> DMA313 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA313 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA313 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x2408++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA313_cons0_control,Controlling consumer socket 0 for DMA313" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA313 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA336_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA336" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA336 Scheduler resources must not be read during halted state. '1'-> DMA336 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA336 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA336 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x241C++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA336_cons0_control,Controlling consumer socket 0 for DMA336" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA336 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA352_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA352" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA352 Scheduler resources must not be read during halted state. '1'-> DMA352 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA352 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA352 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x2430++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA352_cons0_control,Controlling consumer socket 0 for DMA352" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA352 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA353_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA353" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA353 Scheduler resources must not be read during halted state. '1'-> DMA353 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA353 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA353 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x2444++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA353_cons0_control,Controlling consumer socket 0 for DMA353" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA353 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA354_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA354" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA354 Scheduler resources must not be read during halted state. '1'-> DMA354 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA354 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA354 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x2458++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA354_cons0_control,Controlling consumer socket 0 for DMA354" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA354 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA355_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA355" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA355 Scheduler resources must not be read during halted state. '1'-> DMA355 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA355 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA355 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x246C++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA355_cons0_control,Controlling consumer socket 0 for DMA355" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA355 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA368_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA368" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA368 Scheduler resources must not be read during halted state. '1'-> DMA368 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA368 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA368 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x2480++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA368_cons0_control,Controlling consumer socket 0 for DMA368" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA368 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA369_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA369" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA369 Scheduler resources must not be read during halted state. '1'-> DMA369 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA369 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA369 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x2494++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA369_cons0_control,Controlling consumer socket 0 for DMA369" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA369 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA370_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA370" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA370 Scheduler resources must not be read during halted state. '1'-> DMA370 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA370 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA370 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x24A8++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA370_cons0_control,Controlling consumer socket 0 for DMA370" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA370 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA371_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x4 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA371" newline bitfld.long 0x4 12. "DEBUG_RDY,'0' -> DMA371 Scheduler resources must not be read during halted state. '1'-> DMA371 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x4 7.--10. 1. "STATE,Current state of DMA371 Scheduler" newline bitfld.long 0x4 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x4 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x4 1.--3. "PIPELINE_NUM,Pipeline Number of DMA371 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x24BC++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA371_cons0_control,Controlling consumer socket 0 for DMA371" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA371 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x2650++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_pipe_dbg_cntl,Pipeline Debug Control register is used by debug software to control pipeline debug behavior" rbitfld.long 0x0 17.--19. "DEBUG_STATE,Current state of Debug activity" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "ABORT_DEBUG,'1' -> Abort Debug activity on debug enabled pipelines '0' no impact" "0,1" newline bitfld.long 0x0 6. "PIPE_DBG_DIS_6,'1' -> Pipeline6 doesn't respond to debug events '0' Pipeline5 respond to debug events" "0,1" newline bitfld.long 0x0 5. "PIPE_DBG_DIS_5,'1' -> Pipeline5 doesn't respond to debug events '0' Pipeline5 respond to debug events" "0,1" newline bitfld.long 0x0 4. "PIPE_DBG_DIS_4,'1' -> Pipeline4 doesn't respond to debug events '0' Pipeline4 respond to debug events" "0,1" newline bitfld.long 0x0 3. "PIPE_DBG_DIS_3,'1' -> Pipeline3 doesn't respond to debug events '0' Pipeline3 respond to debug events" "0,1" newline bitfld.long 0x0 2. "PIPE_DBG_DIS_2,'1' -> Pipeline2 doesn't respond to debug events '0' Pipeline2 respond to debug events" "0,1" newline bitfld.long 0x0 1. "PIPE_DBG_DIS_1,'1' -> Pipeline1 doesn't respond to debug events '0' Pipeline1 respond to debug events" "0,1" newline bitfld.long 0x0 0. "PIPE_DBG_DIS_0,'1' -> Pipeline0 doesn't respond to debug events '0' Pipeline0 respond to debug events" "0,1" rgroup.long 0x2654++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_dbg_cap,Debug Capability register is used by debug software to determine which optional debug modules are present and how many instances of each module exist." bitfld.long 0x0 30. "DBG_INT_STEP_SUP,Indicates that debug execution control can determine if single step blocks or allows interrupts. b0 No step/interrupt control b1 Step interrupt control via DBG_INT_STEP_IN" "0,1" newline bitfld.long 0x0 29. "DBG_WP_DATA_SUP,Indicates if the WP resources has corresponding data qualification. b0 - Not supported. b1 - Data qualifiers are supported." "0: Not supported,1: Data qualifiers are supported" newline bitfld.long 0x0 28. "DBG_OWN_SUP,Indicates if the HWA supports an module ownership. v2.0 and above. b0 - Not Supported. b1 - Ownership supported." "0: Not Supported,1: Ownership supported" newline bitfld.long 0x0 27. "DBG_INDIRECT_SUP,Indicates if the HWA supports an indirect memory access port. v2.0 and above. b0 - Not Supported. b1 - Indirect port supported." "0: Not Supported,1: Indirect port supported" newline bitfld.long 0x0 26. "DBG_SWBP_SUP,Whether HWA Core supports SWBP or not. b0 - Not Supported. b1 - Supported." "0: Not Supported,1: Supported" newline bitfld.long 0x0 25. "DBQ_RESET_SUP,Whether HWA Core reset is supported or not which does not affect debug logic. b0 - Not Supported. b1 - Supported." "0: Not Supported,1: Supported" newline bitfld.long 0x0 24. "SYS_EXE_REQ,Whether HWA Core Execution status and control is supported. b0 - Not Supported. b1 - Supported." "0: Not Supported,1: Supported" newline bitfld.long 0x0 23. "TRIG_OUTPUT,b0 - Trigger Outputs are not supported. b1 - Trigger Outputs are supported." "0: Trigger Outputs are not supported,1: Trigger Outputs are supported" newline bitfld.long 0x0 22. "TRIG_INPUT,b0 - Trigger Inputs are not supported. b1 - Trigger Inputs are supported." "0: Trigger Inputs are not supported,1: Trigger Inputs are supported" newline bitfld.long 0x0 20.--21. "TRIG_CHNS,Number of Trigger Channels Supported. b00 ------ No channels supported. b01 ------ One channel supported. b10 ------ Two channels supported. Others ---- Reserved." "0: No channels supported,1: One channel supported,2: Two channels supported,?" newline hexmask.long.byte 0x0 16.--19. 1. "NUM_CNTRS,The number of counter modules that exist. The registers supporting the counter modules must be implemented consecutively in the memory map." newline hexmask.long.byte 0x0 12.--15. 1. "NUM_WPS,The number of watchpoint modules that exist. The registers supporting the watchpoint modules must be implemented consecutively in the memory map" newline hexmask.long.byte 0x0 8.--11. 1. "NUM_BPS,The number of breakpoint modules that exist. The registers supporting the breakpoint modules must be implemented consecutively in the memory map." newline hexmask.long.byte 0x0 4.--7. 1. "REV_MAJ,Major Revision" newline hexmask.long.byte 0x0 0.--3. 1. "REV_MIN,Minor Revision" rgroup.long 0x2658++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_dbg_cntl,Debug Control register is used by debug software to control all of the basic debug functions." bitfld.long 0x0 26. "DBG_RESET_OCC,Sticky status bit to reflect reset has been generated" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "DBG_EMU0_CNTL,EMU0 output control. The cross trigger output control. The value in this field determines the behavior of the outputs generated on EMU0. NOTE: The effect of setting any non-zero value is ignored if the HWA Core is currently in HALTED.." newline rbitfld.long 0x0 12. "DBG_HALT_EMU0,Execution halted due to trigger in on EMU0 input Set to '1' when halt due to EMU0 input completes Set to '0' when execution resumes" "0,1" newline rbitfld.long 0x0 11. "DBG_HALT_USER,Execution halted due to register update of DBG_HALT Set to '1' when halt due to DBG_HALT update completes Set to '0' when execution resumes" "0,1" newline rbitfld.long 0x0 10. "DBG_HALT_STEP,Execution halted due to single step completion Set to '1' when the single step completes Set to '0' when execution resumes" "0,1" newline rbitfld.long 0x0 7. "DBG_EXE_STAT,The execution status of the module Set to '1' when halted due to debug event Set to '0' when execution resumes" "0,1" newline bitfld.long 0x0 5. "DBG_EMU0_EN,EMU0 input trigger enable Writing '1' enables halting on the falling edge of the EMU0 input Writing '0' disables halts via EMU0 input" "0,1" newline bitfld.long 0x0 2. "DBG_SINGLE_STEP_EN,Single Step Execution enable. When this bit is set the accelerator core shall be halted upon execution of a single instruction. This is after the accelerator core has left the halted state by clearing the DBG_HALT control bit." "0,1" newline bitfld.long 0x0 1. "DBG_RESTART,Debug Restart Status bit.This bit is normally set when the DBG_HALT bit transitions from '1' to '0' when the natural execution state is entered.It is a sticky bit. It may also be set when a synchronous run causes the accelerator to leave.." "0,1" newline bitfld.long 0x0 0. "DBG_HALT,Global debug run control. The bit will be read as being set upon entry to HALTED state due to halted state being entered because of SWBP HWBP HWWP EMU0 / 1 trigger or manual halt requested through this control. Writing '1' when read '0'.." "0,1" tree.end tree "DMPAC0_INTD_0_CP_INTD_CFG_INTD_CFG (DMPAC0_INTD_0_CP_INTD_CFG_INTD_CFG)" base ad:0xF401000 rgroup.long 0x0++0x3 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_REVISION,Revision Register" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTLVER,RTL revisions" newline bitfld.long 0x0 8.--10. "MAJREV,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_eoi_reg,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector" rgroup.long 0x14++0x3 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg,Interrupt Vector Register" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR,Interrupt Vector Register" rgroup.long 0x100++0x6F line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_dmpac_out_0_0,Enable Register 0" bitfld.long 0x0 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_1_SL2_WR_ERR,Enable Set for level_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1" newline bitfld.long 0x0 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_1_SL2_RD_ERR,Enable Set for level_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1" newline bitfld.long 0x0 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_1_FR_DONE_EVT,Enable Set for level_dmpac_out_0_en_foco_1_fr_done_evt" "0,1" newline bitfld.long 0x0 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_0_SL2_WR_ERR,Enable Set for level_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1" newline bitfld.long 0x0 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_0_SL2_RD_ERR,Enable Set for level_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1" newline bitfld.long 0x0 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_0_FR_DONE_EVT,Enable Set for level_dmpac_out_0_en_foco_0_fr_done_evt" "0,1" newline bitfld.long 0x0 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_WRITE_ERROR,Enable Set for level_dmpac_out_0_en_sde_write_error" "0,1" newline bitfld.long 0x0 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_READ_ERROR,Enable Set for level_dmpac_out_0_en_sde_read_error" "0,1" newline bitfld.long 0x0 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_FRAME_DONE,Enable Set for level_dmpac_out_0_en_sde_frame_done" "0,1" newline bitfld.long 0x0 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_BLK_DONE,Enable Set for level_dmpac_out_0_en_sde_blk_done" "0,1" newline bitfld.long 0x0 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_MP0_RD_STATUS_ERROR,Enable Set for level_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1" newline bitfld.long 0x0 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_WRITE_ERROR,Enable Set for level_dmpac_out_0_en_dof_write_error" "0,1" newline bitfld.long 0x0 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_READ_ERROR,Enable Set for level_dmpac_out_0_en_dof_read_error" "0,1" newline bitfld.long 0x0 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_FRAME_DONE,Enable Set for level_dmpac_out_0_en_dof_frame_done" "0,1" newline bitfld.long 0x0 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_ROW_DONE,Enable Set for level_dmpac_out_0_en_dof_row_done" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_dmpac_out_0_1,Enable Register 1" bitfld.long 0x4 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_8,Enable Set for level_dmpac_out_0_en_tdone_8" "0,1" newline bitfld.long 0x4 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_7,Enable Set for level_dmpac_out_0_en_tdone_7" "0,1" newline bitfld.long 0x4 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_1,Enable Set for level_dmpac_out_0_en_tdone_1" "0,1" newline bitfld.long 0x4 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_0,Enable Set for level_dmpac_out_0_en_tdone_0" "0,1" newline bitfld.long 0x4 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_1_L,Enable Set for level_dmpac_out_0_en_spare_pend_1_l" "0,1" newline bitfld.long 0x4 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_1_P,Enable Set for level_dmpac_out_0_en_spare_pend_1_p" "0,1" newline bitfld.long 0x4 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_0_L,Enable Set for level_dmpac_out_0_en_spare_pend_0_l" "0,1" newline bitfld.long 0x4 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_0_P,Enable Set for level_dmpac_out_0_en_spare_pend_0_p" "0,1" newline bitfld.long 0x4 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_DEC_1,Enable Set for level_dmpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0x4 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_DEC_0,Enable Set for level_dmpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0x4 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_3,Enable Set for level_dmpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0x4 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_2,Enable Set for level_dmpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0x4 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_1,Enable Set for level_dmpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0x4 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_0,Enable Set for level_dmpac_out_0_en_pipe_done_0" "0,1" line.long 0x8 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_dmpac_out_0_2,Enable Register 2" bitfld.long 0x8 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_8,Enable Set for level_dmpac_out_0_en_watchdogtimer_err_8" "0,1" newline bitfld.long 0x8 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_7,Enable Set for level_dmpac_out_0_en_watchdogtimer_err_7" "0,1" newline bitfld.long 0x8 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_1,Enable Set for level_dmpac_out_0_en_watchdogtimer_err_1" "0,1" newline bitfld.long 0x8 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_dmpac_out_0_en_watchdogtimer_err_0" "0,1" line.long 0xC "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_dmpac_out_0_3,Enable Register 3" bitfld.long 0xC 31. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_31,Enable Set for level_dmpac_out_0_en_dru_error_31" "0,1" newline bitfld.long 0xC 30. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_30,Enable Set for level_dmpac_out_0_en_dru_error_30" "0,1" newline bitfld.long 0xC 29. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_29,Enable Set for level_dmpac_out_0_en_dru_error_29" "0,1" newline bitfld.long 0xC 28. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_28,Enable Set for level_dmpac_out_0_en_dru_error_28" "0,1" newline bitfld.long 0xC 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_27,Enable Set for level_dmpac_out_0_en_dru_error_27" "0,1" newline bitfld.long 0xC 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_26,Enable Set for level_dmpac_out_0_en_dru_error_26" "0,1" newline bitfld.long 0xC 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_25,Enable Set for level_dmpac_out_0_en_dru_error_25" "0,1" newline bitfld.long 0xC 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_24,Enable Set for level_dmpac_out_0_en_dru_error_24" "0,1" newline bitfld.long 0xC 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_23,Enable Set for level_dmpac_out_0_en_dru_error_23" "0,1" newline bitfld.long 0xC 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_22,Enable Set for level_dmpac_out_0_en_dru_error_22" "0,1" newline bitfld.long 0xC 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_21,Enable Set for level_dmpac_out_0_en_dru_error_21" "0,1" newline bitfld.long 0xC 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_20,Enable Set for level_dmpac_out_0_en_dru_error_20" "0,1" newline bitfld.long 0xC 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_19,Enable Set for level_dmpac_out_0_en_dru_error_19" "0,1" newline bitfld.long 0xC 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_18,Enable Set for level_dmpac_out_0_en_dru_error_18" "0,1" newline bitfld.long 0xC 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_17,Enable Set for level_dmpac_out_0_en_dru_error_17" "0,1" newline bitfld.long 0xC 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_16,Enable Set for level_dmpac_out_0_en_dru_error_16" "0,1" newline bitfld.long 0xC 15. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_15,Enable Set for level_dmpac_out_0_en_dru_error_15" "0,1" newline bitfld.long 0xC 14. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_14,Enable Set for level_dmpac_out_0_en_dru_error_14" "0,1" newline bitfld.long 0xC 13. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_13,Enable Set for level_dmpac_out_0_en_dru_error_13" "0,1" newline bitfld.long 0xC 12. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_12,Enable Set for level_dmpac_out_0_en_dru_error_12" "0,1" newline bitfld.long 0xC 11. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_11,Enable Set for level_dmpac_out_0_en_dru_error_11" "0,1" newline bitfld.long 0xC 10. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_10,Enable Set for level_dmpac_out_0_en_dru_error_10" "0,1" newline bitfld.long 0xC 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_9,Enable Set for level_dmpac_out_0_en_dru_error_9" "0,1" newline bitfld.long 0xC 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_8,Enable Set for level_dmpac_out_0_en_dru_error_8" "0,1" newline bitfld.long 0xC 7. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_7,Enable Set for level_dmpac_out_0_en_dru_error_7" "0,1" newline bitfld.long 0xC 6. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_6,Enable Set for level_dmpac_out_0_en_dru_error_6" "0,1" newline bitfld.long 0xC 5. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_5,Enable Set for level_dmpac_out_0_en_dru_error_5" "0,1" newline bitfld.long 0xC 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_4,Enable Set for level_dmpac_out_0_en_dru_error_4" "0,1" newline bitfld.long 0xC 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_3,Enable Set for level_dmpac_out_0_en_dru_error_3" "0,1" newline bitfld.long 0xC 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_2,Enable Set for level_dmpac_out_0_en_dru_error_2" "0,1" newline bitfld.long 0xC 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_1,Enable Set for level_dmpac_out_0_en_dru_error_1" "0,1" newline bitfld.long 0xC 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_0,Enable Set for level_dmpac_out_0_en_dru_error_0" "0,1" line.long 0x10 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_dmpac_out_0_4,Enable Register 4" bitfld.long 0x10 31. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_31,Enable Set for level_dmpac_out_0_en_dru_complete_31" "0,1" newline bitfld.long 0x10 30. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_30,Enable Set for level_dmpac_out_0_en_dru_complete_30" "0,1" newline bitfld.long 0x10 29. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_29,Enable Set for level_dmpac_out_0_en_dru_complete_29" "0,1" newline bitfld.long 0x10 28. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_28,Enable Set for level_dmpac_out_0_en_dru_complete_28" "0,1" newline bitfld.long 0x10 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_27,Enable Set for level_dmpac_out_0_en_dru_complete_27" "0,1" newline bitfld.long 0x10 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_26,Enable Set for level_dmpac_out_0_en_dru_complete_26" "0,1" newline bitfld.long 0x10 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_25,Enable Set for level_dmpac_out_0_en_dru_complete_25" "0,1" newline bitfld.long 0x10 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_24,Enable Set for level_dmpac_out_0_en_dru_complete_24" "0,1" newline bitfld.long 0x10 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_23,Enable Set for level_dmpac_out_0_en_dru_complete_23" "0,1" newline bitfld.long 0x10 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_22,Enable Set for level_dmpac_out_0_en_dru_complete_22" "0,1" newline bitfld.long 0x10 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_21,Enable Set for level_dmpac_out_0_en_dru_complete_21" "0,1" newline bitfld.long 0x10 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_20,Enable Set for level_dmpac_out_0_en_dru_complete_20" "0,1" newline bitfld.long 0x10 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_19,Enable Set for level_dmpac_out_0_en_dru_complete_19" "0,1" newline bitfld.long 0x10 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_18,Enable Set for level_dmpac_out_0_en_dru_complete_18" "0,1" newline bitfld.long 0x10 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_17,Enable Set for level_dmpac_out_0_en_dru_complete_17" "0,1" newline bitfld.long 0x10 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_16,Enable Set for level_dmpac_out_0_en_dru_complete_16" "0,1" newline bitfld.long 0x10 15. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_15,Enable Set for level_dmpac_out_0_en_dru_complete_15" "0,1" newline bitfld.long 0x10 14. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_14,Enable Set for level_dmpac_out_0_en_dru_complete_14" "0,1" newline bitfld.long 0x10 13. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_13,Enable Set for level_dmpac_out_0_en_dru_complete_13" "0,1" newline bitfld.long 0x10 12. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_12,Enable Set for level_dmpac_out_0_en_dru_complete_12" "0,1" newline bitfld.long 0x10 11. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_11,Enable Set for level_dmpac_out_0_en_dru_complete_11" "0,1" newline bitfld.long 0x10 10. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_10,Enable Set for level_dmpac_out_0_en_dru_complete_10" "0,1" newline bitfld.long 0x10 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_9,Enable Set for level_dmpac_out_0_en_dru_complete_9" "0,1" newline bitfld.long 0x10 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_8,Enable Set for level_dmpac_out_0_en_dru_complete_8" "0,1" newline bitfld.long 0x10 7. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_7,Enable Set for level_dmpac_out_0_en_dru_complete_7" "0,1" newline bitfld.long 0x10 6. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_6,Enable Set for level_dmpac_out_0_en_dru_complete_6" "0,1" newline bitfld.long 0x10 5. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_5,Enable Set for level_dmpac_out_0_en_dru_complete_5" "0,1" newline bitfld.long 0x10 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_4,Enable Set for level_dmpac_out_0_en_dru_complete_4" "0,1" newline bitfld.long 0x10 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_3,Enable Set for level_dmpac_out_0_en_dru_complete_3" "0,1" newline bitfld.long 0x10 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_2,Enable Set for level_dmpac_out_0_en_dru_complete_2" "0,1" newline bitfld.long 0x10 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_1,Enable Set for level_dmpac_out_0_en_dru_complete_1" "0,1" newline bitfld.long 0x10 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_0,Enable Set for level_dmpac_out_0_en_dru_complete_0" "0,1" line.long 0x14 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_dmpac_out_0_5,Enable Register 5" bitfld.long 0x14 31. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_31,Enable Set for level_dmpac_out_0_en_dru_local_out_event_31" "0,1" newline bitfld.long 0x14 30. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_30,Enable Set for level_dmpac_out_0_en_dru_local_out_event_30" "0,1" newline bitfld.long 0x14 29. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_29,Enable Set for level_dmpac_out_0_en_dru_local_out_event_29" "0,1" newline bitfld.long 0x14 28. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_28,Enable Set for level_dmpac_out_0_en_dru_local_out_event_28" "0,1" newline bitfld.long 0x14 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_27,Enable Set for level_dmpac_out_0_en_dru_local_out_event_27" "0,1" newline bitfld.long 0x14 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_26,Enable Set for level_dmpac_out_0_en_dru_local_out_event_26" "0,1" newline bitfld.long 0x14 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_25,Enable Set for level_dmpac_out_0_en_dru_local_out_event_25" "0,1" newline bitfld.long 0x14 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_24,Enable Set for level_dmpac_out_0_en_dru_local_out_event_24" "0,1" newline bitfld.long 0x14 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_23,Enable Set for level_dmpac_out_0_en_dru_local_out_event_23" "0,1" newline bitfld.long 0x14 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_22,Enable Set for level_dmpac_out_0_en_dru_local_out_event_22" "0,1" newline bitfld.long 0x14 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_21,Enable Set for level_dmpac_out_0_en_dru_local_out_event_21" "0,1" newline bitfld.long 0x14 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_20,Enable Set for level_dmpac_out_0_en_dru_local_out_event_20" "0,1" newline bitfld.long 0x14 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_19,Enable Set for level_dmpac_out_0_en_dru_local_out_event_19" "0,1" newline bitfld.long 0x14 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_18,Enable Set for level_dmpac_out_0_en_dru_local_out_event_18" "0,1" newline bitfld.long 0x14 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_17,Enable Set for level_dmpac_out_0_en_dru_local_out_event_17" "0,1" newline bitfld.long 0x14 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_16,Enable Set for level_dmpac_out_0_en_dru_local_out_event_16" "0,1" newline bitfld.long 0x14 15. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_15,Enable Set for level_dmpac_out_0_en_dru_local_out_event_15" "0,1" newline bitfld.long 0x14 14. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_14,Enable Set for level_dmpac_out_0_en_dru_local_out_event_14" "0,1" newline bitfld.long 0x14 13. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_13,Enable Set for level_dmpac_out_0_en_dru_local_out_event_13" "0,1" newline bitfld.long 0x14 12. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_12,Enable Set for level_dmpac_out_0_en_dru_local_out_event_12" "0,1" newline bitfld.long 0x14 11. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_11,Enable Set for level_dmpac_out_0_en_dru_local_out_event_11" "0,1" newline bitfld.long 0x14 10. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_10,Enable Set for level_dmpac_out_0_en_dru_local_out_event_10" "0,1" newline bitfld.long 0x14 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_9,Enable Set for level_dmpac_out_0_en_dru_local_out_event_9" "0,1" newline bitfld.long 0x14 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_8,Enable Set for level_dmpac_out_0_en_dru_local_out_event_8" "0,1" newline bitfld.long 0x14 7. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_7,Enable Set for level_dmpac_out_0_en_dru_local_out_event_7" "0,1" newline bitfld.long 0x14 6. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_6,Enable Set for level_dmpac_out_0_en_dru_local_out_event_6" "0,1" newline bitfld.long 0x14 5. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_5,Enable Set for level_dmpac_out_0_en_dru_local_out_event_5" "0,1" newline bitfld.long 0x14 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_4,Enable Set for level_dmpac_out_0_en_dru_local_out_event_4" "0,1" newline bitfld.long 0x14 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_3,Enable Set for level_dmpac_out_0_en_dru_local_out_event_3" "0,1" newline bitfld.long 0x14 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_2,Enable Set for level_dmpac_out_0_en_dru_local_out_event_2" "0,1" newline bitfld.long 0x14 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_1,Enable Set for level_dmpac_out_0_en_dru_local_out_event_1" "0,1" newline bitfld.long 0x14 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_0,Enable Set for level_dmpac_out_0_en_dru_local_out_event_0" "0,1" line.long 0x18 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_dmpac_out_0_6,Enable Register 6" bitfld.long 0x18 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_CTM_PULSE,Enable Set for level_dmpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0x18 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_PROT_ERR,Enable Set for level_dmpac_out_0_en_dru_prot_err" "0,1" line.long 0x1C "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_dmpac_out_1_0,Enable Register 7" bitfld.long 0x1C 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_1_SL2_WR_ERR,Enable Set for level_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1" newline bitfld.long 0x1C 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_1_SL2_RD_ERR,Enable Set for level_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1" newline bitfld.long 0x1C 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_1_FR_DONE_EVT,Enable Set for level_dmpac_out_1_en_foco_1_fr_done_evt" "0,1" newline bitfld.long 0x1C 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_0_SL2_WR_ERR,Enable Set for level_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1" newline bitfld.long 0x1C 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_0_SL2_RD_ERR,Enable Set for level_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1" newline bitfld.long 0x1C 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_0_FR_DONE_EVT,Enable Set for level_dmpac_out_1_en_foco_0_fr_done_evt" "0,1" newline bitfld.long 0x1C 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_WRITE_ERROR,Enable Set for level_dmpac_out_1_en_sde_write_error" "0,1" newline bitfld.long 0x1C 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_READ_ERROR,Enable Set for level_dmpac_out_1_en_sde_read_error" "0,1" newline bitfld.long 0x1C 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_FRAME_DONE,Enable Set for level_dmpac_out_1_en_sde_frame_done" "0,1" newline bitfld.long 0x1C 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_BLK_DONE,Enable Set for level_dmpac_out_1_en_sde_blk_done" "0,1" newline bitfld.long 0x1C 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_MP0_RD_STATUS_ERROR,Enable Set for level_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1" newline bitfld.long 0x1C 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_WRITE_ERROR,Enable Set for level_dmpac_out_1_en_dof_write_error" "0,1" newline bitfld.long 0x1C 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_READ_ERROR,Enable Set for level_dmpac_out_1_en_dof_read_error" "0,1" newline bitfld.long 0x1C 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_FRAME_DONE,Enable Set for level_dmpac_out_1_en_dof_frame_done" "0,1" newline bitfld.long 0x1C 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_ROW_DONE,Enable Set for level_dmpac_out_1_en_dof_row_done" "0,1" line.long 0x20 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_dmpac_out_1_1,Enable Register 8" bitfld.long 0x20 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_8,Enable Set for level_dmpac_out_1_en_tdone_8" "0,1" newline bitfld.long 0x20 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_7,Enable Set for level_dmpac_out_1_en_tdone_7" "0,1" newline bitfld.long 0x20 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_1,Enable Set for level_dmpac_out_1_en_tdone_1" "0,1" newline bitfld.long 0x20 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_0,Enable Set for level_dmpac_out_1_en_tdone_0" "0,1" newline bitfld.long 0x20 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_1_L,Enable Set for level_dmpac_out_1_en_spare_pend_1_l" "0,1" newline bitfld.long 0x20 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_1_P,Enable Set for level_dmpac_out_1_en_spare_pend_1_p" "0,1" newline bitfld.long 0x20 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_0_L,Enable Set for level_dmpac_out_1_en_spare_pend_0_l" "0,1" newline bitfld.long 0x20 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_0_P,Enable Set for level_dmpac_out_1_en_spare_pend_0_p" "0,1" newline bitfld.long 0x20 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_DEC_1,Enable Set for level_dmpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0x20 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_DEC_0,Enable Set for level_dmpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0x20 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_3,Enable Set for level_dmpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0x20 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_2,Enable Set for level_dmpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0x20 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_1,Enable Set for level_dmpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0x20 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_0,Enable Set for level_dmpac_out_1_en_pipe_done_0" "0,1" line.long 0x24 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_dmpac_out_1_2,Enable Register 9" bitfld.long 0x24 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_8,Enable Set for level_dmpac_out_1_en_watchdogtimer_err_8" "0,1" newline bitfld.long 0x24 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_7,Enable Set for level_dmpac_out_1_en_watchdogtimer_err_7" "0,1" newline bitfld.long 0x24 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_1,Enable Set for level_dmpac_out_1_en_watchdogtimer_err_1" "0,1" newline bitfld.long 0x24 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_dmpac_out_1_en_watchdogtimer_err_0" "0,1" line.long 0x28 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_dmpac_out_1_3,Enable Register 10" bitfld.long 0x28 31. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_31,Enable Set for level_dmpac_out_1_en_dru_error_31" "0,1" newline bitfld.long 0x28 30. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_30,Enable Set for level_dmpac_out_1_en_dru_error_30" "0,1" newline bitfld.long 0x28 29. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_29,Enable Set for level_dmpac_out_1_en_dru_error_29" "0,1" newline bitfld.long 0x28 28. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_28,Enable Set for level_dmpac_out_1_en_dru_error_28" "0,1" newline bitfld.long 0x28 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_27,Enable Set for level_dmpac_out_1_en_dru_error_27" "0,1" newline bitfld.long 0x28 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_26,Enable Set for level_dmpac_out_1_en_dru_error_26" "0,1" newline bitfld.long 0x28 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_25,Enable Set for level_dmpac_out_1_en_dru_error_25" "0,1" newline bitfld.long 0x28 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_24,Enable Set for level_dmpac_out_1_en_dru_error_24" "0,1" newline bitfld.long 0x28 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_23,Enable Set for level_dmpac_out_1_en_dru_error_23" "0,1" newline bitfld.long 0x28 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_22,Enable Set for level_dmpac_out_1_en_dru_error_22" "0,1" newline bitfld.long 0x28 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_21,Enable Set for level_dmpac_out_1_en_dru_error_21" "0,1" newline bitfld.long 0x28 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_20,Enable Set for level_dmpac_out_1_en_dru_error_20" "0,1" newline bitfld.long 0x28 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_19,Enable Set for level_dmpac_out_1_en_dru_error_19" "0,1" newline bitfld.long 0x28 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_18,Enable Set for level_dmpac_out_1_en_dru_error_18" "0,1" newline bitfld.long 0x28 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_17,Enable Set for level_dmpac_out_1_en_dru_error_17" "0,1" newline bitfld.long 0x28 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_16,Enable Set for level_dmpac_out_1_en_dru_error_16" "0,1" newline bitfld.long 0x28 15. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_15,Enable Set for level_dmpac_out_1_en_dru_error_15" "0,1" newline bitfld.long 0x28 14. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_14,Enable Set for level_dmpac_out_1_en_dru_error_14" "0,1" newline bitfld.long 0x28 13. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_13,Enable Set for level_dmpac_out_1_en_dru_error_13" "0,1" newline bitfld.long 0x28 12. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_12,Enable Set for level_dmpac_out_1_en_dru_error_12" "0,1" newline bitfld.long 0x28 11. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_11,Enable Set for level_dmpac_out_1_en_dru_error_11" "0,1" newline bitfld.long 0x28 10. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_10,Enable Set for level_dmpac_out_1_en_dru_error_10" "0,1" newline bitfld.long 0x28 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_9,Enable Set for level_dmpac_out_1_en_dru_error_9" "0,1" newline bitfld.long 0x28 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_8,Enable Set for level_dmpac_out_1_en_dru_error_8" "0,1" newline bitfld.long 0x28 7. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_7,Enable Set for level_dmpac_out_1_en_dru_error_7" "0,1" newline bitfld.long 0x28 6. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_6,Enable Set for level_dmpac_out_1_en_dru_error_6" "0,1" newline bitfld.long 0x28 5. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_5,Enable Set for level_dmpac_out_1_en_dru_error_5" "0,1" newline bitfld.long 0x28 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_4,Enable Set for level_dmpac_out_1_en_dru_error_4" "0,1" newline bitfld.long 0x28 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_3,Enable Set for level_dmpac_out_1_en_dru_error_3" "0,1" newline bitfld.long 0x28 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_2,Enable Set for level_dmpac_out_1_en_dru_error_2" "0,1" newline bitfld.long 0x28 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_1,Enable Set for level_dmpac_out_1_en_dru_error_1" "0,1" newline bitfld.long 0x28 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_0,Enable Set for level_dmpac_out_1_en_dru_error_0" "0,1" line.long 0x2C "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_dmpac_out_1_4,Enable Register 11" bitfld.long 0x2C 31. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_31,Enable Set for level_dmpac_out_1_en_dru_complete_31" "0,1" newline bitfld.long 0x2C 30. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_30,Enable Set for level_dmpac_out_1_en_dru_complete_30" "0,1" newline bitfld.long 0x2C 29. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_29,Enable Set for level_dmpac_out_1_en_dru_complete_29" "0,1" newline bitfld.long 0x2C 28. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_28,Enable Set for level_dmpac_out_1_en_dru_complete_28" "0,1" newline bitfld.long 0x2C 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_27,Enable Set for level_dmpac_out_1_en_dru_complete_27" "0,1" newline bitfld.long 0x2C 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_26,Enable Set for level_dmpac_out_1_en_dru_complete_26" "0,1" newline bitfld.long 0x2C 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_25,Enable Set for level_dmpac_out_1_en_dru_complete_25" "0,1" newline bitfld.long 0x2C 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_24,Enable Set for level_dmpac_out_1_en_dru_complete_24" "0,1" newline bitfld.long 0x2C 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_23,Enable Set for level_dmpac_out_1_en_dru_complete_23" "0,1" newline bitfld.long 0x2C 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_22,Enable Set for level_dmpac_out_1_en_dru_complete_22" "0,1" newline bitfld.long 0x2C 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_21,Enable Set for level_dmpac_out_1_en_dru_complete_21" "0,1" newline bitfld.long 0x2C 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_20,Enable Set for level_dmpac_out_1_en_dru_complete_20" "0,1" newline bitfld.long 0x2C 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_19,Enable Set for level_dmpac_out_1_en_dru_complete_19" "0,1" newline bitfld.long 0x2C 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_18,Enable Set for level_dmpac_out_1_en_dru_complete_18" "0,1" newline bitfld.long 0x2C 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_17,Enable Set for level_dmpac_out_1_en_dru_complete_17" "0,1" newline bitfld.long 0x2C 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_16,Enable Set for level_dmpac_out_1_en_dru_complete_16" "0,1" newline bitfld.long 0x2C 15. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_15,Enable Set for level_dmpac_out_1_en_dru_complete_15" "0,1" newline bitfld.long 0x2C 14. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_14,Enable Set for level_dmpac_out_1_en_dru_complete_14" "0,1" newline bitfld.long 0x2C 13. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_13,Enable Set for level_dmpac_out_1_en_dru_complete_13" "0,1" newline bitfld.long 0x2C 12. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_12,Enable Set for level_dmpac_out_1_en_dru_complete_12" "0,1" newline bitfld.long 0x2C 11. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_11,Enable Set for level_dmpac_out_1_en_dru_complete_11" "0,1" newline bitfld.long 0x2C 10. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_10,Enable Set for level_dmpac_out_1_en_dru_complete_10" "0,1" newline bitfld.long 0x2C 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_9,Enable Set for level_dmpac_out_1_en_dru_complete_9" "0,1" newline bitfld.long 0x2C 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_8,Enable Set for level_dmpac_out_1_en_dru_complete_8" "0,1" newline bitfld.long 0x2C 7. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_7,Enable Set for level_dmpac_out_1_en_dru_complete_7" "0,1" newline bitfld.long 0x2C 6. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_6,Enable Set for level_dmpac_out_1_en_dru_complete_6" "0,1" newline bitfld.long 0x2C 5. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_5,Enable Set for level_dmpac_out_1_en_dru_complete_5" "0,1" newline bitfld.long 0x2C 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_4,Enable Set for level_dmpac_out_1_en_dru_complete_4" "0,1" newline bitfld.long 0x2C 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_3,Enable Set for level_dmpac_out_1_en_dru_complete_3" "0,1" newline bitfld.long 0x2C 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_2,Enable Set for level_dmpac_out_1_en_dru_complete_2" "0,1" newline bitfld.long 0x2C 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_1,Enable Set for level_dmpac_out_1_en_dru_complete_1" "0,1" newline bitfld.long 0x2C 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_0,Enable Set for level_dmpac_out_1_en_dru_complete_0" "0,1" line.long 0x30 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_dmpac_out_1_5,Enable Register 12" bitfld.long 0x30 31. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_31,Enable Set for level_dmpac_out_1_en_dru_local_out_event_31" "0,1" newline bitfld.long 0x30 30. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_30,Enable Set for level_dmpac_out_1_en_dru_local_out_event_30" "0,1" newline bitfld.long 0x30 29. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_29,Enable Set for level_dmpac_out_1_en_dru_local_out_event_29" "0,1" newline bitfld.long 0x30 28. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_28,Enable Set for level_dmpac_out_1_en_dru_local_out_event_28" "0,1" newline bitfld.long 0x30 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_27,Enable Set for level_dmpac_out_1_en_dru_local_out_event_27" "0,1" newline bitfld.long 0x30 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_26,Enable Set for level_dmpac_out_1_en_dru_local_out_event_26" "0,1" newline bitfld.long 0x30 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_25,Enable Set for level_dmpac_out_1_en_dru_local_out_event_25" "0,1" newline bitfld.long 0x30 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_24,Enable Set for level_dmpac_out_1_en_dru_local_out_event_24" "0,1" newline bitfld.long 0x30 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_23,Enable Set for level_dmpac_out_1_en_dru_local_out_event_23" "0,1" newline bitfld.long 0x30 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_22,Enable Set for level_dmpac_out_1_en_dru_local_out_event_22" "0,1" newline bitfld.long 0x30 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_21,Enable Set for level_dmpac_out_1_en_dru_local_out_event_21" "0,1" newline bitfld.long 0x30 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_20,Enable Set for level_dmpac_out_1_en_dru_local_out_event_20" "0,1" newline bitfld.long 0x30 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_19,Enable Set for level_dmpac_out_1_en_dru_local_out_event_19" "0,1" newline bitfld.long 0x30 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_18,Enable Set for level_dmpac_out_1_en_dru_local_out_event_18" "0,1" newline bitfld.long 0x30 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_17,Enable Set for level_dmpac_out_1_en_dru_local_out_event_17" "0,1" newline bitfld.long 0x30 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_16,Enable Set for level_dmpac_out_1_en_dru_local_out_event_16" "0,1" newline bitfld.long 0x30 15. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_15,Enable Set for level_dmpac_out_1_en_dru_local_out_event_15" "0,1" newline bitfld.long 0x30 14. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_14,Enable Set for level_dmpac_out_1_en_dru_local_out_event_14" "0,1" newline bitfld.long 0x30 13. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_13,Enable Set for level_dmpac_out_1_en_dru_local_out_event_13" "0,1" newline bitfld.long 0x30 12. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_12,Enable Set for level_dmpac_out_1_en_dru_local_out_event_12" "0,1" newline bitfld.long 0x30 11. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_11,Enable Set for level_dmpac_out_1_en_dru_local_out_event_11" "0,1" newline bitfld.long 0x30 10. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_10,Enable Set for level_dmpac_out_1_en_dru_local_out_event_10" "0,1" newline bitfld.long 0x30 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_9,Enable Set for level_dmpac_out_1_en_dru_local_out_event_9" "0,1" newline bitfld.long 0x30 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_8,Enable Set for level_dmpac_out_1_en_dru_local_out_event_8" "0,1" newline bitfld.long 0x30 7. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_7,Enable Set for level_dmpac_out_1_en_dru_local_out_event_7" "0,1" newline bitfld.long 0x30 6. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_6,Enable Set for level_dmpac_out_1_en_dru_local_out_event_6" "0,1" newline bitfld.long 0x30 5. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_5,Enable Set for level_dmpac_out_1_en_dru_local_out_event_5" "0,1" newline bitfld.long 0x30 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_4,Enable Set for level_dmpac_out_1_en_dru_local_out_event_4" "0,1" newline bitfld.long 0x30 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_3,Enable Set for level_dmpac_out_1_en_dru_local_out_event_3" "0,1" newline bitfld.long 0x30 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_2,Enable Set for level_dmpac_out_1_en_dru_local_out_event_2" "0,1" newline bitfld.long 0x30 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_1,Enable Set for level_dmpac_out_1_en_dru_local_out_event_1" "0,1" newline bitfld.long 0x30 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_0,Enable Set for level_dmpac_out_1_en_dru_local_out_event_0" "0,1" line.long 0x34 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_dmpac_out_1_6,Enable Register 13" bitfld.long 0x34 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_CTM_PULSE,Enable Set for level_dmpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0x34 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_PROT_ERR,Enable Set for level_dmpac_out_1_en_dru_prot_err" "0,1" line.long 0x38 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_dmpac_out_0_0,Enable Register 14" bitfld.long 0x38 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_1_SL2_WR_ERR,Enable Set for pulse_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1" newline bitfld.long 0x38 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_1_SL2_RD_ERR,Enable Set for pulse_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1" newline bitfld.long 0x38 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_1_FR_DONE_EVT,Enable Set for pulse_dmpac_out_0_en_foco_1_fr_done_evt" "0,1" newline bitfld.long 0x38 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_0_SL2_WR_ERR,Enable Set for pulse_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1" newline bitfld.long 0x38 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_0_SL2_RD_ERR,Enable Set for pulse_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1" newline bitfld.long 0x38 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_0_FR_DONE_EVT,Enable Set for pulse_dmpac_out_0_en_foco_0_fr_done_evt" "0,1" newline bitfld.long 0x38 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_WRITE_ERROR,Enable Set for pulse_dmpac_out_0_en_sde_write_error" "0,1" newline bitfld.long 0x38 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_READ_ERROR,Enable Set for pulse_dmpac_out_0_en_sde_read_error" "0,1" newline bitfld.long 0x38 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_FRAME_DONE,Enable Set for pulse_dmpac_out_0_en_sde_frame_done" "0,1" newline bitfld.long 0x38 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_BLK_DONE,Enable Set for pulse_dmpac_out_0_en_sde_blk_done" "0,1" newline bitfld.long 0x38 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_MP0_RD_STATUS_ERROR,Enable Set for pulse_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1" newline bitfld.long 0x38 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_WRITE_ERROR,Enable Set for pulse_dmpac_out_0_en_dof_write_error" "0,1" newline bitfld.long 0x38 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_READ_ERROR,Enable Set for pulse_dmpac_out_0_en_dof_read_error" "0,1" newline bitfld.long 0x38 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_FRAME_DONE,Enable Set for pulse_dmpac_out_0_en_dof_frame_done" "0,1" newline bitfld.long 0x38 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_ROW_DONE,Enable Set for pulse_dmpac_out_0_en_dof_row_done" "0,1" line.long 0x3C "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_dmpac_out_0_1,Enable Register 15" bitfld.long 0x3C 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_8,Enable Set for pulse_dmpac_out_0_en_tdone_8" "0,1" newline bitfld.long 0x3C 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_7,Enable Set for pulse_dmpac_out_0_en_tdone_7" "0,1" newline bitfld.long 0x3C 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_1,Enable Set for pulse_dmpac_out_0_en_tdone_1" "0,1" newline bitfld.long 0x3C 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_0,Enable Set for pulse_dmpac_out_0_en_tdone_0" "0,1" newline bitfld.long 0x3C 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_1_L,Enable Set for pulse_dmpac_out_0_en_spare_pend_1_l" "0,1" newline bitfld.long 0x3C 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_1_P,Enable Set for pulse_dmpac_out_0_en_spare_pend_1_p" "0,1" newline bitfld.long 0x3C 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_0_L,Enable Set for pulse_dmpac_out_0_en_spare_pend_0_l" "0,1" newline bitfld.long 0x3C 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_0_P,Enable Set for pulse_dmpac_out_0_en_spare_pend_0_p" "0,1" newline bitfld.long 0x3C 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_DEC_1,Enable Set for pulse_dmpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0x3C 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_DEC_0,Enable Set for pulse_dmpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0x3C 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_3,Enable Set for pulse_dmpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0x3C 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_2,Enable Set for pulse_dmpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0x3C 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_1,Enable Set for pulse_dmpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0x3C 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_0,Enable Set for pulse_dmpac_out_0_en_pipe_done_0" "0,1" line.long 0x40 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_dmpac_out_0_2,Enable Register 16" bitfld.long 0x40 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_8,Enable Set for pulse_dmpac_out_0_en_watchdogtimer_err_8" "0,1" newline bitfld.long 0x40 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_7,Enable Set for pulse_dmpac_out_0_en_watchdogtimer_err_7" "0,1" newline bitfld.long 0x40 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_1,Enable Set for pulse_dmpac_out_0_en_watchdogtimer_err_1" "0,1" newline bitfld.long 0x40 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_dmpac_out_0_en_watchdogtimer_err_0" "0,1" line.long 0x44 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_dmpac_out_0_3,Enable Register 17" bitfld.long 0x44 31. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_31,Enable Set for pulse_dmpac_out_0_en_dru_error_31" "0,1" newline bitfld.long 0x44 30. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_30,Enable Set for pulse_dmpac_out_0_en_dru_error_30" "0,1" newline bitfld.long 0x44 29. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_29,Enable Set for pulse_dmpac_out_0_en_dru_error_29" "0,1" newline bitfld.long 0x44 28. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_28,Enable Set for pulse_dmpac_out_0_en_dru_error_28" "0,1" newline bitfld.long 0x44 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_27,Enable Set for pulse_dmpac_out_0_en_dru_error_27" "0,1" newline bitfld.long 0x44 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_26,Enable Set for pulse_dmpac_out_0_en_dru_error_26" "0,1" newline bitfld.long 0x44 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_25,Enable Set for pulse_dmpac_out_0_en_dru_error_25" "0,1" newline bitfld.long 0x44 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_24,Enable Set for pulse_dmpac_out_0_en_dru_error_24" "0,1" newline bitfld.long 0x44 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_23,Enable Set for pulse_dmpac_out_0_en_dru_error_23" "0,1" newline bitfld.long 0x44 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_22,Enable Set for pulse_dmpac_out_0_en_dru_error_22" "0,1" newline bitfld.long 0x44 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_21,Enable Set for pulse_dmpac_out_0_en_dru_error_21" "0,1" newline bitfld.long 0x44 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_20,Enable Set for pulse_dmpac_out_0_en_dru_error_20" "0,1" newline bitfld.long 0x44 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_19,Enable Set for pulse_dmpac_out_0_en_dru_error_19" "0,1" newline bitfld.long 0x44 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_18,Enable Set for pulse_dmpac_out_0_en_dru_error_18" "0,1" newline bitfld.long 0x44 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_17,Enable Set for pulse_dmpac_out_0_en_dru_error_17" "0,1" newline bitfld.long 0x44 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_16,Enable Set for pulse_dmpac_out_0_en_dru_error_16" "0,1" newline bitfld.long 0x44 15. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_15,Enable Set for pulse_dmpac_out_0_en_dru_error_15" "0,1" newline bitfld.long 0x44 14. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_14,Enable Set for pulse_dmpac_out_0_en_dru_error_14" "0,1" newline bitfld.long 0x44 13. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_13,Enable Set for pulse_dmpac_out_0_en_dru_error_13" "0,1" newline bitfld.long 0x44 12. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_12,Enable Set for pulse_dmpac_out_0_en_dru_error_12" "0,1" newline bitfld.long 0x44 11. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_11,Enable Set for pulse_dmpac_out_0_en_dru_error_11" "0,1" newline bitfld.long 0x44 10. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_10,Enable Set for pulse_dmpac_out_0_en_dru_error_10" "0,1" newline bitfld.long 0x44 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_9,Enable Set for pulse_dmpac_out_0_en_dru_error_9" "0,1" newline bitfld.long 0x44 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_8,Enable Set for pulse_dmpac_out_0_en_dru_error_8" "0,1" newline bitfld.long 0x44 7. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_7,Enable Set for pulse_dmpac_out_0_en_dru_error_7" "0,1" newline bitfld.long 0x44 6. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_6,Enable Set for pulse_dmpac_out_0_en_dru_error_6" "0,1" newline bitfld.long 0x44 5. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_5,Enable Set for pulse_dmpac_out_0_en_dru_error_5" "0,1" newline bitfld.long 0x44 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_4,Enable Set for pulse_dmpac_out_0_en_dru_error_4" "0,1" newline bitfld.long 0x44 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_3,Enable Set for pulse_dmpac_out_0_en_dru_error_3" "0,1" newline bitfld.long 0x44 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_2,Enable Set for pulse_dmpac_out_0_en_dru_error_2" "0,1" newline bitfld.long 0x44 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_1,Enable Set for pulse_dmpac_out_0_en_dru_error_1" "0,1" newline bitfld.long 0x44 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_0,Enable Set for pulse_dmpac_out_0_en_dru_error_0" "0,1" line.long 0x48 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_dmpac_out_0_4,Enable Register 18" bitfld.long 0x48 31. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_31,Enable Set for pulse_dmpac_out_0_en_dru_complete_31" "0,1" newline bitfld.long 0x48 30. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_30,Enable Set for pulse_dmpac_out_0_en_dru_complete_30" "0,1" newline bitfld.long 0x48 29. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_29,Enable Set for pulse_dmpac_out_0_en_dru_complete_29" "0,1" newline bitfld.long 0x48 28. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_28,Enable Set for pulse_dmpac_out_0_en_dru_complete_28" "0,1" newline bitfld.long 0x48 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_27,Enable Set for pulse_dmpac_out_0_en_dru_complete_27" "0,1" newline bitfld.long 0x48 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_26,Enable Set for pulse_dmpac_out_0_en_dru_complete_26" "0,1" newline bitfld.long 0x48 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_25,Enable Set for pulse_dmpac_out_0_en_dru_complete_25" "0,1" newline bitfld.long 0x48 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_24,Enable Set for pulse_dmpac_out_0_en_dru_complete_24" "0,1" newline bitfld.long 0x48 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_23,Enable Set for pulse_dmpac_out_0_en_dru_complete_23" "0,1" newline bitfld.long 0x48 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_22,Enable Set for pulse_dmpac_out_0_en_dru_complete_22" "0,1" newline bitfld.long 0x48 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_21,Enable Set for pulse_dmpac_out_0_en_dru_complete_21" "0,1" newline bitfld.long 0x48 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_20,Enable Set for pulse_dmpac_out_0_en_dru_complete_20" "0,1" newline bitfld.long 0x48 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_19,Enable Set for pulse_dmpac_out_0_en_dru_complete_19" "0,1" newline bitfld.long 0x48 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_18,Enable Set for pulse_dmpac_out_0_en_dru_complete_18" "0,1" newline bitfld.long 0x48 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_17,Enable Set for pulse_dmpac_out_0_en_dru_complete_17" "0,1" newline bitfld.long 0x48 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_16,Enable Set for pulse_dmpac_out_0_en_dru_complete_16" "0,1" newline bitfld.long 0x48 15. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_15,Enable Set for pulse_dmpac_out_0_en_dru_complete_15" "0,1" newline bitfld.long 0x48 14. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_14,Enable Set for pulse_dmpac_out_0_en_dru_complete_14" "0,1" newline bitfld.long 0x48 13. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_13,Enable Set for pulse_dmpac_out_0_en_dru_complete_13" "0,1" newline bitfld.long 0x48 12. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_12,Enable Set for pulse_dmpac_out_0_en_dru_complete_12" "0,1" newline bitfld.long 0x48 11. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_11,Enable Set for pulse_dmpac_out_0_en_dru_complete_11" "0,1" newline bitfld.long 0x48 10. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_10,Enable Set for pulse_dmpac_out_0_en_dru_complete_10" "0,1" newline bitfld.long 0x48 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_9,Enable Set for pulse_dmpac_out_0_en_dru_complete_9" "0,1" newline bitfld.long 0x48 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_8,Enable Set for pulse_dmpac_out_0_en_dru_complete_8" "0,1" newline bitfld.long 0x48 7. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_7,Enable Set for pulse_dmpac_out_0_en_dru_complete_7" "0,1" newline bitfld.long 0x48 6. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_6,Enable Set for pulse_dmpac_out_0_en_dru_complete_6" "0,1" newline bitfld.long 0x48 5. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_5,Enable Set for pulse_dmpac_out_0_en_dru_complete_5" "0,1" newline bitfld.long 0x48 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_4,Enable Set for pulse_dmpac_out_0_en_dru_complete_4" "0,1" newline bitfld.long 0x48 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_3,Enable Set for pulse_dmpac_out_0_en_dru_complete_3" "0,1" newline bitfld.long 0x48 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_2,Enable Set for pulse_dmpac_out_0_en_dru_complete_2" "0,1" newline bitfld.long 0x48 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_1,Enable Set for pulse_dmpac_out_0_en_dru_complete_1" "0,1" newline bitfld.long 0x48 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_0,Enable Set for pulse_dmpac_out_0_en_dru_complete_0" "0,1" line.long 0x4C "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_dmpac_out_0_5,Enable Register 19" bitfld.long 0x4C 31. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_31,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_31" "0,1" newline bitfld.long 0x4C 30. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_30,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_30" "0,1" newline bitfld.long 0x4C 29. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_29,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_29" "0,1" newline bitfld.long 0x4C 28. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_28,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_28" "0,1" newline bitfld.long 0x4C 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_27,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_27" "0,1" newline bitfld.long 0x4C 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_26,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_26" "0,1" newline bitfld.long 0x4C 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_25,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_25" "0,1" newline bitfld.long 0x4C 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_24,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_24" "0,1" newline bitfld.long 0x4C 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_23,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_23" "0,1" newline bitfld.long 0x4C 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_22,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_22" "0,1" newline bitfld.long 0x4C 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_21,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_21" "0,1" newline bitfld.long 0x4C 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_20,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_20" "0,1" newline bitfld.long 0x4C 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_19,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_19" "0,1" newline bitfld.long 0x4C 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_18,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_18" "0,1" newline bitfld.long 0x4C 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_17,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_17" "0,1" newline bitfld.long 0x4C 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_16,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_16" "0,1" newline bitfld.long 0x4C 15. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_15,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_15" "0,1" newline bitfld.long 0x4C 14. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_14,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_14" "0,1" newline bitfld.long 0x4C 13. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_13,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_13" "0,1" newline bitfld.long 0x4C 12. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_12,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_12" "0,1" newline bitfld.long 0x4C 11. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_11,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_11" "0,1" newline bitfld.long 0x4C 10. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_10,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_10" "0,1" newline bitfld.long 0x4C 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_9,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_9" "0,1" newline bitfld.long 0x4C 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_8,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_8" "0,1" newline bitfld.long 0x4C 7. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_7,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_7" "0,1" newline bitfld.long 0x4C 6. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_6,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_6" "0,1" newline bitfld.long 0x4C 5. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_5,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_5" "0,1" newline bitfld.long 0x4C 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_4,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_4" "0,1" newline bitfld.long 0x4C 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_3,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_3" "0,1" newline bitfld.long 0x4C 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_2,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_2" "0,1" newline bitfld.long 0x4C 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_1,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_1" "0,1" newline bitfld.long 0x4C 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_0,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_0" "0,1" line.long 0x50 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_dmpac_out_0_6,Enable Register 20" bitfld.long 0x50 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_CTM_PULSE,Enable Set for pulse_dmpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0x50 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_PROT_ERR,Enable Set for pulse_dmpac_out_0_en_dru_prot_err" "0,1" line.long 0x54 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_dmpac_out_1_0,Enable Register 21" bitfld.long 0x54 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_1_SL2_WR_ERR,Enable Set for pulse_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1" newline bitfld.long 0x54 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_1_SL2_RD_ERR,Enable Set for pulse_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1" newline bitfld.long 0x54 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_1_FR_DONE_EVT,Enable Set for pulse_dmpac_out_1_en_foco_1_fr_done_evt" "0,1" newline bitfld.long 0x54 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_0_SL2_WR_ERR,Enable Set for pulse_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1" newline bitfld.long 0x54 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_0_SL2_RD_ERR,Enable Set for pulse_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1" newline bitfld.long 0x54 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_0_FR_DONE_EVT,Enable Set for pulse_dmpac_out_1_en_foco_0_fr_done_evt" "0,1" newline bitfld.long 0x54 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_WRITE_ERROR,Enable Set for pulse_dmpac_out_1_en_sde_write_error" "0,1" newline bitfld.long 0x54 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_READ_ERROR,Enable Set for pulse_dmpac_out_1_en_sde_read_error" "0,1" newline bitfld.long 0x54 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_FRAME_DONE,Enable Set for pulse_dmpac_out_1_en_sde_frame_done" "0,1" newline bitfld.long 0x54 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_BLK_DONE,Enable Set for pulse_dmpac_out_1_en_sde_blk_done" "0,1" newline bitfld.long 0x54 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_MP0_RD_STATUS_ERROR,Enable Set for pulse_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1" newline bitfld.long 0x54 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_WRITE_ERROR,Enable Set for pulse_dmpac_out_1_en_dof_write_error" "0,1" newline bitfld.long 0x54 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_READ_ERROR,Enable Set for pulse_dmpac_out_1_en_dof_read_error" "0,1" newline bitfld.long 0x54 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_FRAME_DONE,Enable Set for pulse_dmpac_out_1_en_dof_frame_done" "0,1" newline bitfld.long 0x54 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_ROW_DONE,Enable Set for pulse_dmpac_out_1_en_dof_row_done" "0,1" line.long 0x58 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_dmpac_out_1_1,Enable Register 22" bitfld.long 0x58 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_8,Enable Set for pulse_dmpac_out_1_en_tdone_8" "0,1" newline bitfld.long 0x58 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_7,Enable Set for pulse_dmpac_out_1_en_tdone_7" "0,1" newline bitfld.long 0x58 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_1,Enable Set for pulse_dmpac_out_1_en_tdone_1" "0,1" newline bitfld.long 0x58 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_0,Enable Set for pulse_dmpac_out_1_en_tdone_0" "0,1" newline bitfld.long 0x58 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_1_L,Enable Set for pulse_dmpac_out_1_en_spare_pend_1_l" "0,1" newline bitfld.long 0x58 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_1_P,Enable Set for pulse_dmpac_out_1_en_spare_pend_1_p" "0,1" newline bitfld.long 0x58 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_0_L,Enable Set for pulse_dmpac_out_1_en_spare_pend_0_l" "0,1" newline bitfld.long 0x58 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_0_P,Enable Set for pulse_dmpac_out_1_en_spare_pend_0_p" "0,1" newline bitfld.long 0x58 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_DEC_1,Enable Set for pulse_dmpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0x58 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_DEC_0,Enable Set for pulse_dmpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0x58 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_3,Enable Set for pulse_dmpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0x58 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_2,Enable Set for pulse_dmpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0x58 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_1,Enable Set for pulse_dmpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0x58 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_0,Enable Set for pulse_dmpac_out_1_en_pipe_done_0" "0,1" line.long 0x5C "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_dmpac_out_1_2,Enable Register 23" bitfld.long 0x5C 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_8,Enable Set for pulse_dmpac_out_1_en_watchdogtimer_err_8" "0,1" newline bitfld.long 0x5C 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_7,Enable Set for pulse_dmpac_out_1_en_watchdogtimer_err_7" "0,1" newline bitfld.long 0x5C 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_1,Enable Set for pulse_dmpac_out_1_en_watchdogtimer_err_1" "0,1" newline bitfld.long 0x5C 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_dmpac_out_1_en_watchdogtimer_err_0" "0,1" line.long 0x60 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_dmpac_out_1_3,Enable Register 24" bitfld.long 0x60 31. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_31,Enable Set for pulse_dmpac_out_1_en_dru_error_31" "0,1" newline bitfld.long 0x60 30. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_30,Enable Set for pulse_dmpac_out_1_en_dru_error_30" "0,1" newline bitfld.long 0x60 29. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_29,Enable Set for pulse_dmpac_out_1_en_dru_error_29" "0,1" newline bitfld.long 0x60 28. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_28,Enable Set for pulse_dmpac_out_1_en_dru_error_28" "0,1" newline bitfld.long 0x60 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_27,Enable Set for pulse_dmpac_out_1_en_dru_error_27" "0,1" newline bitfld.long 0x60 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_26,Enable Set for pulse_dmpac_out_1_en_dru_error_26" "0,1" newline bitfld.long 0x60 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_25,Enable Set for pulse_dmpac_out_1_en_dru_error_25" "0,1" newline bitfld.long 0x60 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_24,Enable Set for pulse_dmpac_out_1_en_dru_error_24" "0,1" newline bitfld.long 0x60 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_23,Enable Set for pulse_dmpac_out_1_en_dru_error_23" "0,1" newline bitfld.long 0x60 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_22,Enable Set for pulse_dmpac_out_1_en_dru_error_22" "0,1" newline bitfld.long 0x60 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_21,Enable Set for pulse_dmpac_out_1_en_dru_error_21" "0,1" newline bitfld.long 0x60 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_20,Enable Set for pulse_dmpac_out_1_en_dru_error_20" "0,1" newline bitfld.long 0x60 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_19,Enable Set for pulse_dmpac_out_1_en_dru_error_19" "0,1" newline bitfld.long 0x60 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_18,Enable Set for pulse_dmpac_out_1_en_dru_error_18" "0,1" newline bitfld.long 0x60 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_17,Enable Set for pulse_dmpac_out_1_en_dru_error_17" "0,1" newline bitfld.long 0x60 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_16,Enable Set for pulse_dmpac_out_1_en_dru_error_16" "0,1" newline bitfld.long 0x60 15. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_15,Enable Set for pulse_dmpac_out_1_en_dru_error_15" "0,1" newline bitfld.long 0x60 14. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_14,Enable Set for pulse_dmpac_out_1_en_dru_error_14" "0,1" newline bitfld.long 0x60 13. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_13,Enable Set for pulse_dmpac_out_1_en_dru_error_13" "0,1" newline bitfld.long 0x60 12. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_12,Enable Set for pulse_dmpac_out_1_en_dru_error_12" "0,1" newline bitfld.long 0x60 11. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_11,Enable Set for pulse_dmpac_out_1_en_dru_error_11" "0,1" newline bitfld.long 0x60 10. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_10,Enable Set for pulse_dmpac_out_1_en_dru_error_10" "0,1" newline bitfld.long 0x60 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_9,Enable Set for pulse_dmpac_out_1_en_dru_error_9" "0,1" newline bitfld.long 0x60 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_8,Enable Set for pulse_dmpac_out_1_en_dru_error_8" "0,1" newline bitfld.long 0x60 7. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_7,Enable Set for pulse_dmpac_out_1_en_dru_error_7" "0,1" newline bitfld.long 0x60 6. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_6,Enable Set for pulse_dmpac_out_1_en_dru_error_6" "0,1" newline bitfld.long 0x60 5. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_5,Enable Set for pulse_dmpac_out_1_en_dru_error_5" "0,1" newline bitfld.long 0x60 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_4,Enable Set for pulse_dmpac_out_1_en_dru_error_4" "0,1" newline bitfld.long 0x60 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_3,Enable Set for pulse_dmpac_out_1_en_dru_error_3" "0,1" newline bitfld.long 0x60 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_2,Enable Set for pulse_dmpac_out_1_en_dru_error_2" "0,1" newline bitfld.long 0x60 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_1,Enable Set for pulse_dmpac_out_1_en_dru_error_1" "0,1" newline bitfld.long 0x60 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_0,Enable Set for pulse_dmpac_out_1_en_dru_error_0" "0,1" line.long 0x64 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_dmpac_out_1_4,Enable Register 25" bitfld.long 0x64 31. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_31,Enable Set for pulse_dmpac_out_1_en_dru_complete_31" "0,1" newline bitfld.long 0x64 30. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_30,Enable Set for pulse_dmpac_out_1_en_dru_complete_30" "0,1" newline bitfld.long 0x64 29. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_29,Enable Set for pulse_dmpac_out_1_en_dru_complete_29" "0,1" newline bitfld.long 0x64 28. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_28,Enable Set for pulse_dmpac_out_1_en_dru_complete_28" "0,1" newline bitfld.long 0x64 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_27,Enable Set for pulse_dmpac_out_1_en_dru_complete_27" "0,1" newline bitfld.long 0x64 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_26,Enable Set for pulse_dmpac_out_1_en_dru_complete_26" "0,1" newline bitfld.long 0x64 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_25,Enable Set for pulse_dmpac_out_1_en_dru_complete_25" "0,1" newline bitfld.long 0x64 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_24,Enable Set for pulse_dmpac_out_1_en_dru_complete_24" "0,1" newline bitfld.long 0x64 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_23,Enable Set for pulse_dmpac_out_1_en_dru_complete_23" "0,1" newline bitfld.long 0x64 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_22,Enable Set for pulse_dmpac_out_1_en_dru_complete_22" "0,1" newline bitfld.long 0x64 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_21,Enable Set for pulse_dmpac_out_1_en_dru_complete_21" "0,1" newline bitfld.long 0x64 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_20,Enable Set for pulse_dmpac_out_1_en_dru_complete_20" "0,1" newline bitfld.long 0x64 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_19,Enable Set for pulse_dmpac_out_1_en_dru_complete_19" "0,1" newline bitfld.long 0x64 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_18,Enable Set for pulse_dmpac_out_1_en_dru_complete_18" "0,1" newline bitfld.long 0x64 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_17,Enable Set for pulse_dmpac_out_1_en_dru_complete_17" "0,1" newline bitfld.long 0x64 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_16,Enable Set for pulse_dmpac_out_1_en_dru_complete_16" "0,1" newline bitfld.long 0x64 15. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_15,Enable Set for pulse_dmpac_out_1_en_dru_complete_15" "0,1" newline bitfld.long 0x64 14. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_14,Enable Set for pulse_dmpac_out_1_en_dru_complete_14" "0,1" newline bitfld.long 0x64 13. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_13,Enable Set for pulse_dmpac_out_1_en_dru_complete_13" "0,1" newline bitfld.long 0x64 12. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_12,Enable Set for pulse_dmpac_out_1_en_dru_complete_12" "0,1" newline bitfld.long 0x64 11. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_11,Enable Set for pulse_dmpac_out_1_en_dru_complete_11" "0,1" newline bitfld.long 0x64 10. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_10,Enable Set for pulse_dmpac_out_1_en_dru_complete_10" "0,1" newline bitfld.long 0x64 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_9,Enable Set for pulse_dmpac_out_1_en_dru_complete_9" "0,1" newline bitfld.long 0x64 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_8,Enable Set for pulse_dmpac_out_1_en_dru_complete_8" "0,1" newline bitfld.long 0x64 7. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_7,Enable Set for pulse_dmpac_out_1_en_dru_complete_7" "0,1" newline bitfld.long 0x64 6. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_6,Enable Set for pulse_dmpac_out_1_en_dru_complete_6" "0,1" newline bitfld.long 0x64 5. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_5,Enable Set for pulse_dmpac_out_1_en_dru_complete_5" "0,1" newline bitfld.long 0x64 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_4,Enable Set for pulse_dmpac_out_1_en_dru_complete_4" "0,1" newline bitfld.long 0x64 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_3,Enable Set for pulse_dmpac_out_1_en_dru_complete_3" "0,1" newline bitfld.long 0x64 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_2,Enable Set for pulse_dmpac_out_1_en_dru_complete_2" "0,1" newline bitfld.long 0x64 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_1,Enable Set for pulse_dmpac_out_1_en_dru_complete_1" "0,1" newline bitfld.long 0x64 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_0,Enable Set for pulse_dmpac_out_1_en_dru_complete_0" "0,1" line.long 0x68 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_dmpac_out_1_5,Enable Register 26" bitfld.long 0x68 31. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_31,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_31" "0,1" newline bitfld.long 0x68 30. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_30,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_30" "0,1" newline bitfld.long 0x68 29. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_29,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_29" "0,1" newline bitfld.long 0x68 28. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_28,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_28" "0,1" newline bitfld.long 0x68 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_27,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_27" "0,1" newline bitfld.long 0x68 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_26,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_26" "0,1" newline bitfld.long 0x68 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_25,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_25" "0,1" newline bitfld.long 0x68 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_24,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_24" "0,1" newline bitfld.long 0x68 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_23,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_23" "0,1" newline bitfld.long 0x68 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_22,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_22" "0,1" newline bitfld.long 0x68 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_21,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_21" "0,1" newline bitfld.long 0x68 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_20,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_20" "0,1" newline bitfld.long 0x68 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_19,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_19" "0,1" newline bitfld.long 0x68 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_18,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_18" "0,1" newline bitfld.long 0x68 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_17,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_17" "0,1" newline bitfld.long 0x68 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_16,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_16" "0,1" newline bitfld.long 0x68 15. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_15,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_15" "0,1" newline bitfld.long 0x68 14. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_14,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_14" "0,1" newline bitfld.long 0x68 13. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_13,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_13" "0,1" newline bitfld.long 0x68 12. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_12,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_12" "0,1" newline bitfld.long 0x68 11. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_11,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_11" "0,1" newline bitfld.long 0x68 10. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_10,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_10" "0,1" newline bitfld.long 0x68 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_9,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_9" "0,1" newline bitfld.long 0x68 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_8,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_8" "0,1" newline bitfld.long 0x68 7. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_7,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_7" "0,1" newline bitfld.long 0x68 6. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_6,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_6" "0,1" newline bitfld.long 0x68 5. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_5,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_5" "0,1" newline bitfld.long 0x68 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_4,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_4" "0,1" newline bitfld.long 0x68 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_3,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_3" "0,1" newline bitfld.long 0x68 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_2,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_2" "0,1" newline bitfld.long 0x68 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_1,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_1" "0,1" newline bitfld.long 0x68 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_0,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_0" "0,1" line.long 0x6C "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_dmpac_out_1_6,Enable Register 27" bitfld.long 0x6C 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_CTM_PULSE,Enable Set for pulse_dmpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0x6C 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_PROT_ERR,Enable Set for pulse_dmpac_out_1_en_dru_prot_err" "0,1" rgroup.long 0x300++0x6F line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_dmpac_out_0_0,Enable Clear Register 0" bitfld.long 0x0 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_1_SL2_WR_ERR_CLR,Enable Clear for level_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1" newline bitfld.long 0x0 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_1_SL2_RD_ERR_CLR,Enable Clear for level_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1" newline bitfld.long 0x0 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_1_FR_DONE_EVT_CLR,Enable Clear for level_dmpac_out_0_en_foco_1_fr_done_evt" "0,1" newline bitfld.long 0x0 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_0_SL2_WR_ERR_CLR,Enable Clear for level_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1" newline bitfld.long 0x0 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_0_SL2_RD_ERR_CLR,Enable Clear for level_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1" newline bitfld.long 0x0 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_0_FR_DONE_EVT_CLR,Enable Clear for level_dmpac_out_0_en_foco_0_fr_done_evt" "0,1" newline bitfld.long 0x0 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_WRITE_ERROR_CLR,Enable Clear for level_dmpac_out_0_en_sde_write_error" "0,1" newline bitfld.long 0x0 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_READ_ERROR_CLR,Enable Clear for level_dmpac_out_0_en_sde_read_error" "0,1" newline bitfld.long 0x0 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_FRAME_DONE_CLR,Enable Clear for level_dmpac_out_0_en_sde_frame_done" "0,1" newline bitfld.long 0x0 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_BLK_DONE_CLR,Enable Clear for level_dmpac_out_0_en_sde_blk_done" "0,1" newline bitfld.long 0x0 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_MP0_RD_STATUS_ERROR_CLR,Enable Clear for level_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1" newline bitfld.long 0x0 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_WRITE_ERROR_CLR,Enable Clear for level_dmpac_out_0_en_dof_write_error" "0,1" newline bitfld.long 0x0 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_READ_ERROR_CLR,Enable Clear for level_dmpac_out_0_en_dof_read_error" "0,1" newline bitfld.long 0x0 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_FRAME_DONE_CLR,Enable Clear for level_dmpac_out_0_en_dof_frame_done" "0,1" newline bitfld.long 0x0 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_ROW_DONE_CLR,Enable Clear for level_dmpac_out_0_en_dof_row_done" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_dmpac_out_0_1,Enable Clear Register 1" bitfld.long 0x4 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_8_CLR,Enable Clear for level_dmpac_out_0_en_tdone_8" "0,1" newline bitfld.long 0x4 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_7_CLR,Enable Clear for level_dmpac_out_0_en_tdone_7" "0,1" newline bitfld.long 0x4 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_1_CLR,Enable Clear for level_dmpac_out_0_en_tdone_1" "0,1" newline bitfld.long 0x4 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_0_CLR,Enable Clear for level_dmpac_out_0_en_tdone_0" "0,1" newline bitfld.long 0x4 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_1_L_CLR,Enable Clear for level_dmpac_out_0_en_spare_pend_1_l" "0,1" newline bitfld.long 0x4 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_1_P_CLR,Enable Clear for level_dmpac_out_0_en_spare_pend_1_p" "0,1" newline bitfld.long 0x4 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_0_L_CLR,Enable Clear for level_dmpac_out_0_en_spare_pend_0_l" "0,1" newline bitfld.long 0x4 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_0_P_CLR,Enable Clear for level_dmpac_out_0_en_spare_pend_0_p" "0,1" newline bitfld.long 0x4 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_DEC_1_CLR,Enable Clear for level_dmpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0x4 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_DEC_0_CLR,Enable Clear for level_dmpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0x4 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_3_CLR,Enable Clear for level_dmpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0x4 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_2_CLR,Enable Clear for level_dmpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0x4 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_1_CLR,Enable Clear for level_dmpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0x4 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_0_CLR,Enable Clear for level_dmpac_out_0_en_pipe_done_0" "0,1" line.long 0x8 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_dmpac_out_0_2,Enable Clear Register 2" bitfld.long 0x8 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_8_CLR,Enable Clear for level_dmpac_out_0_en_watchdogtimer_err_8" "0,1" newline bitfld.long 0x8 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_7_CLR,Enable Clear for level_dmpac_out_0_en_watchdogtimer_err_7" "0,1" newline bitfld.long 0x8 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_1_CLR,Enable Clear for level_dmpac_out_0_en_watchdogtimer_err_1" "0,1" newline bitfld.long 0x8 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_dmpac_out_0_en_watchdogtimer_err_0" "0,1" line.long 0xC "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_dmpac_out_0_3,Enable Clear Register 3" bitfld.long 0xC 31. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_31_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_31" "0,1" newline bitfld.long 0xC 30. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_30_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_30" "0,1" newline bitfld.long 0xC 29. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_29_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_29" "0,1" newline bitfld.long 0xC 28. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_28_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_28" "0,1" newline bitfld.long 0xC 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_27_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_27" "0,1" newline bitfld.long 0xC 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_26_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_26" "0,1" newline bitfld.long 0xC 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_25_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_25" "0,1" newline bitfld.long 0xC 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_24_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_24" "0,1" newline bitfld.long 0xC 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_23_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_23" "0,1" newline bitfld.long 0xC 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_22_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_22" "0,1" newline bitfld.long 0xC 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_21_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_21" "0,1" newline bitfld.long 0xC 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_20_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_20" "0,1" newline bitfld.long 0xC 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_19_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_19" "0,1" newline bitfld.long 0xC 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_18_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_18" "0,1" newline bitfld.long 0xC 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_17_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_17" "0,1" newline bitfld.long 0xC 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_16_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_16" "0,1" newline bitfld.long 0xC 15. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_15_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_15" "0,1" newline bitfld.long 0xC 14. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_14_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_14" "0,1" newline bitfld.long 0xC 13. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_13_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_13" "0,1" newline bitfld.long 0xC 12. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_12_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_12" "0,1" newline bitfld.long 0xC 11. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_11_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_11" "0,1" newline bitfld.long 0xC 10. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_10_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_10" "0,1" newline bitfld.long 0xC 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_9_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_9" "0,1" newline bitfld.long 0xC 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_8_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_8" "0,1" newline bitfld.long 0xC 7. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_7_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_7" "0,1" newline bitfld.long 0xC 6. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_6_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_6" "0,1" newline bitfld.long 0xC 5. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_5_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_5" "0,1" newline bitfld.long 0xC 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_4_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_4" "0,1" newline bitfld.long 0xC 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_3_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_3" "0,1" newline bitfld.long 0xC 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_2_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_2" "0,1" newline bitfld.long 0xC 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_1_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_1" "0,1" newline bitfld.long 0xC 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_0_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_0" "0,1" line.long 0x10 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_dmpac_out_0_4,Enable Clear Register 4" bitfld.long 0x10 31. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_31_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_31" "0,1" newline bitfld.long 0x10 30. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_30_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_30" "0,1" newline bitfld.long 0x10 29. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_29_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_29" "0,1" newline bitfld.long 0x10 28. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_28_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_28" "0,1" newline bitfld.long 0x10 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_27_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_27" "0,1" newline bitfld.long 0x10 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_26_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_26" "0,1" newline bitfld.long 0x10 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_25_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_25" "0,1" newline bitfld.long 0x10 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_24_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_24" "0,1" newline bitfld.long 0x10 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_23_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_23" "0,1" newline bitfld.long 0x10 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_22_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_22" "0,1" newline bitfld.long 0x10 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_21_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_21" "0,1" newline bitfld.long 0x10 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_20_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_20" "0,1" newline bitfld.long 0x10 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_19_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_19" "0,1" newline bitfld.long 0x10 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_18_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_18" "0,1" newline bitfld.long 0x10 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_17_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_17" "0,1" newline bitfld.long 0x10 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_16_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_16" "0,1" newline bitfld.long 0x10 15. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_15_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_15" "0,1" newline bitfld.long 0x10 14. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_14_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_14" "0,1" newline bitfld.long 0x10 13. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_13_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_13" "0,1" newline bitfld.long 0x10 12. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_12_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_12" "0,1" newline bitfld.long 0x10 11. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_11_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_11" "0,1" newline bitfld.long 0x10 10. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_10_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_10" "0,1" newline bitfld.long 0x10 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_9_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_9" "0,1" newline bitfld.long 0x10 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_8_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_8" "0,1" newline bitfld.long 0x10 7. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_7_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_7" "0,1" newline bitfld.long 0x10 6. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_6_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_6" "0,1" newline bitfld.long 0x10 5. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_5_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_5" "0,1" newline bitfld.long 0x10 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_4_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_4" "0,1" newline bitfld.long 0x10 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_3_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_3" "0,1" newline bitfld.long 0x10 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_2_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_2" "0,1" newline bitfld.long 0x10 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_1_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_1" "0,1" newline bitfld.long 0x10 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_0_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_0" "0,1" line.long 0x14 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_dmpac_out_0_5,Enable Clear Register 5" bitfld.long 0x14 31. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_31_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_31" "0,1" newline bitfld.long 0x14 30. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_30_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_30" "0,1" newline bitfld.long 0x14 29. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_29_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_29" "0,1" newline bitfld.long 0x14 28. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_28_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_28" "0,1" newline bitfld.long 0x14 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_27_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_27" "0,1" newline bitfld.long 0x14 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_26_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_26" "0,1" newline bitfld.long 0x14 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_25_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_25" "0,1" newline bitfld.long 0x14 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_24_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_24" "0,1" newline bitfld.long 0x14 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_23_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_23" "0,1" newline bitfld.long 0x14 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_22_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_22" "0,1" newline bitfld.long 0x14 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_21_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_21" "0,1" newline bitfld.long 0x14 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_20_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_20" "0,1" newline bitfld.long 0x14 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_19_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_19" "0,1" newline bitfld.long 0x14 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_18_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_18" "0,1" newline bitfld.long 0x14 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_17_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_17" "0,1" newline bitfld.long 0x14 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_16_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_16" "0,1" newline bitfld.long 0x14 15. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_15_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_15" "0,1" newline bitfld.long 0x14 14. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_14_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_14" "0,1" newline bitfld.long 0x14 13. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_13_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_13" "0,1" newline bitfld.long 0x14 12. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_12_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_12" "0,1" newline bitfld.long 0x14 11. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_11_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_11" "0,1" newline bitfld.long 0x14 10. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_10_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_10" "0,1" newline bitfld.long 0x14 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_9_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_9" "0,1" newline bitfld.long 0x14 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_8_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_8" "0,1" newline bitfld.long 0x14 7. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_7_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_7" "0,1" newline bitfld.long 0x14 6. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_6_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_6" "0,1" newline bitfld.long 0x14 5. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_5_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_5" "0,1" newline bitfld.long 0x14 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_4_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_4" "0,1" newline bitfld.long 0x14 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_3_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_3" "0,1" newline bitfld.long 0x14 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_2_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_2" "0,1" newline bitfld.long 0x14 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_1_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_1" "0,1" newline bitfld.long 0x14 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_0_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_0" "0,1" line.long 0x18 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_dmpac_out_0_6,Enable Clear Register 6" bitfld.long 0x18 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_CTM_PULSE_CLR,Enable Clear for level_dmpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0x18 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_PROT_ERR_CLR,Enable Clear for level_dmpac_out_0_en_dru_prot_err" "0,1" line.long 0x1C "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_dmpac_out_1_0,Enable Clear Register 7" bitfld.long 0x1C 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_1_SL2_WR_ERR_CLR,Enable Clear for level_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1" newline bitfld.long 0x1C 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_1_SL2_RD_ERR_CLR,Enable Clear for level_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1" newline bitfld.long 0x1C 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_1_FR_DONE_EVT_CLR,Enable Clear for level_dmpac_out_1_en_foco_1_fr_done_evt" "0,1" newline bitfld.long 0x1C 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_0_SL2_WR_ERR_CLR,Enable Clear for level_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1" newline bitfld.long 0x1C 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_0_SL2_RD_ERR_CLR,Enable Clear for level_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1" newline bitfld.long 0x1C 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_0_FR_DONE_EVT_CLR,Enable Clear for level_dmpac_out_1_en_foco_0_fr_done_evt" "0,1" newline bitfld.long 0x1C 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_WRITE_ERROR_CLR,Enable Clear for level_dmpac_out_1_en_sde_write_error" "0,1" newline bitfld.long 0x1C 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_READ_ERROR_CLR,Enable Clear for level_dmpac_out_1_en_sde_read_error" "0,1" newline bitfld.long 0x1C 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_FRAME_DONE_CLR,Enable Clear for level_dmpac_out_1_en_sde_frame_done" "0,1" newline bitfld.long 0x1C 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_BLK_DONE_CLR,Enable Clear for level_dmpac_out_1_en_sde_blk_done" "0,1" newline bitfld.long 0x1C 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_MP0_RD_STATUS_ERROR_CLR,Enable Clear for level_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1" newline bitfld.long 0x1C 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_WRITE_ERROR_CLR,Enable Clear for level_dmpac_out_1_en_dof_write_error" "0,1" newline bitfld.long 0x1C 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_READ_ERROR_CLR,Enable Clear for level_dmpac_out_1_en_dof_read_error" "0,1" newline bitfld.long 0x1C 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_FRAME_DONE_CLR,Enable Clear for level_dmpac_out_1_en_dof_frame_done" "0,1" newline bitfld.long 0x1C 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_ROW_DONE_CLR,Enable Clear for level_dmpac_out_1_en_dof_row_done" "0,1" line.long 0x20 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_dmpac_out_1_1,Enable Clear Register 8" bitfld.long 0x20 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_8_CLR,Enable Clear for level_dmpac_out_1_en_tdone_8" "0,1" newline bitfld.long 0x20 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_7_CLR,Enable Clear for level_dmpac_out_1_en_tdone_7" "0,1" newline bitfld.long 0x20 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_1_CLR,Enable Clear for level_dmpac_out_1_en_tdone_1" "0,1" newline bitfld.long 0x20 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_0_CLR,Enable Clear for level_dmpac_out_1_en_tdone_0" "0,1" newline bitfld.long 0x20 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_1_L_CLR,Enable Clear for level_dmpac_out_1_en_spare_pend_1_l" "0,1" newline bitfld.long 0x20 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_1_P_CLR,Enable Clear for level_dmpac_out_1_en_spare_pend_1_p" "0,1" newline bitfld.long 0x20 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_0_L_CLR,Enable Clear for level_dmpac_out_1_en_spare_pend_0_l" "0,1" newline bitfld.long 0x20 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_0_P_CLR,Enable Clear for level_dmpac_out_1_en_spare_pend_0_p" "0,1" newline bitfld.long 0x20 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_DEC_1_CLR,Enable Clear for level_dmpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0x20 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_DEC_0_CLR,Enable Clear for level_dmpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0x20 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_3_CLR,Enable Clear for level_dmpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0x20 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_2_CLR,Enable Clear for level_dmpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0x20 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_1_CLR,Enable Clear for level_dmpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0x20 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_0_CLR,Enable Clear for level_dmpac_out_1_en_pipe_done_0" "0,1" line.long 0x24 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_dmpac_out_1_2,Enable Clear Register 9" bitfld.long 0x24 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_8_CLR,Enable Clear for level_dmpac_out_1_en_watchdogtimer_err_8" "0,1" newline bitfld.long 0x24 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_7_CLR,Enable Clear for level_dmpac_out_1_en_watchdogtimer_err_7" "0,1" newline bitfld.long 0x24 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_1_CLR,Enable Clear for level_dmpac_out_1_en_watchdogtimer_err_1" "0,1" newline bitfld.long 0x24 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_dmpac_out_1_en_watchdogtimer_err_0" "0,1" line.long 0x28 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_dmpac_out_1_3,Enable Clear Register 10" bitfld.long 0x28 31. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_31_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_31" "0,1" newline bitfld.long 0x28 30. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_30_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_30" "0,1" newline bitfld.long 0x28 29. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_29_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_29" "0,1" newline bitfld.long 0x28 28. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_28_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_28" "0,1" newline bitfld.long 0x28 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_27_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_27" "0,1" newline bitfld.long 0x28 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_26_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_26" "0,1" newline bitfld.long 0x28 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_25_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_25" "0,1" newline bitfld.long 0x28 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_24_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_24" "0,1" newline bitfld.long 0x28 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_23_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_23" "0,1" newline bitfld.long 0x28 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_22_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_22" "0,1" newline bitfld.long 0x28 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_21_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_21" "0,1" newline bitfld.long 0x28 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_20_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_20" "0,1" newline bitfld.long 0x28 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_19_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_19" "0,1" newline bitfld.long 0x28 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_18_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_18" "0,1" newline bitfld.long 0x28 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_17_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_17" "0,1" newline bitfld.long 0x28 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_16_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_16" "0,1" newline bitfld.long 0x28 15. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_15_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_15" "0,1" newline bitfld.long 0x28 14. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_14_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_14" "0,1" newline bitfld.long 0x28 13. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_13_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_13" "0,1" newline bitfld.long 0x28 12. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_12_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_12" "0,1" newline bitfld.long 0x28 11. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_11_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_11" "0,1" newline bitfld.long 0x28 10. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_10_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_10" "0,1" newline bitfld.long 0x28 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_9_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_9" "0,1" newline bitfld.long 0x28 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_8_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_8" "0,1" newline bitfld.long 0x28 7. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_7_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_7" "0,1" newline bitfld.long 0x28 6. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_6_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_6" "0,1" newline bitfld.long 0x28 5. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_5_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_5" "0,1" newline bitfld.long 0x28 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_4_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_4" "0,1" newline bitfld.long 0x28 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_3_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_3" "0,1" newline bitfld.long 0x28 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_2_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_2" "0,1" newline bitfld.long 0x28 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_1_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_1" "0,1" newline bitfld.long 0x28 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_0_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_0" "0,1" line.long 0x2C "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_dmpac_out_1_4,Enable Clear Register 11" bitfld.long 0x2C 31. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_31_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_31" "0,1" newline bitfld.long 0x2C 30. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_30_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_30" "0,1" newline bitfld.long 0x2C 29. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_29_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_29" "0,1" newline bitfld.long 0x2C 28. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_28_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_28" "0,1" newline bitfld.long 0x2C 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_27_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_27" "0,1" newline bitfld.long 0x2C 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_26_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_26" "0,1" newline bitfld.long 0x2C 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_25_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_25" "0,1" newline bitfld.long 0x2C 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_24_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_24" "0,1" newline bitfld.long 0x2C 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_23_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_23" "0,1" newline bitfld.long 0x2C 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_22_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_22" "0,1" newline bitfld.long 0x2C 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_21_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_21" "0,1" newline bitfld.long 0x2C 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_20_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_20" "0,1" newline bitfld.long 0x2C 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_19_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_19" "0,1" newline bitfld.long 0x2C 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_18_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_18" "0,1" newline bitfld.long 0x2C 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_17_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_17" "0,1" newline bitfld.long 0x2C 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_16_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_16" "0,1" newline bitfld.long 0x2C 15. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_15_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_15" "0,1" newline bitfld.long 0x2C 14. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_14_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_14" "0,1" newline bitfld.long 0x2C 13. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_13_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_13" "0,1" newline bitfld.long 0x2C 12. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_12_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_12" "0,1" newline bitfld.long 0x2C 11. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_11_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_11" "0,1" newline bitfld.long 0x2C 10. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_10_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_10" "0,1" newline bitfld.long 0x2C 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_9_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_9" "0,1" newline bitfld.long 0x2C 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_8_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_8" "0,1" newline bitfld.long 0x2C 7. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_7_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_7" "0,1" newline bitfld.long 0x2C 6. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_6_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_6" "0,1" newline bitfld.long 0x2C 5. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_5_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_5" "0,1" newline bitfld.long 0x2C 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_4_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_4" "0,1" newline bitfld.long 0x2C 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_3_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_3" "0,1" newline bitfld.long 0x2C 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_2_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_2" "0,1" newline bitfld.long 0x2C 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_1_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_1" "0,1" newline bitfld.long 0x2C 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_0_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_0" "0,1" line.long 0x30 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_dmpac_out_1_5,Enable Clear Register 12" bitfld.long 0x30 31. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_31_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_31" "0,1" newline bitfld.long 0x30 30. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_30_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_30" "0,1" newline bitfld.long 0x30 29. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_29_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_29" "0,1" newline bitfld.long 0x30 28. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_28_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_28" "0,1" newline bitfld.long 0x30 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_27_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_27" "0,1" newline bitfld.long 0x30 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_26_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_26" "0,1" newline bitfld.long 0x30 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_25_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_25" "0,1" newline bitfld.long 0x30 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_24_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_24" "0,1" newline bitfld.long 0x30 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_23_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_23" "0,1" newline bitfld.long 0x30 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_22_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_22" "0,1" newline bitfld.long 0x30 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_21_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_21" "0,1" newline bitfld.long 0x30 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_20_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_20" "0,1" newline bitfld.long 0x30 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_19_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_19" "0,1" newline bitfld.long 0x30 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_18_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_18" "0,1" newline bitfld.long 0x30 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_17_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_17" "0,1" newline bitfld.long 0x30 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_16_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_16" "0,1" newline bitfld.long 0x30 15. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_15_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_15" "0,1" newline bitfld.long 0x30 14. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_14_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_14" "0,1" newline bitfld.long 0x30 13. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_13_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_13" "0,1" newline bitfld.long 0x30 12. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_12_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_12" "0,1" newline bitfld.long 0x30 11. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_11_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_11" "0,1" newline bitfld.long 0x30 10. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_10_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_10" "0,1" newline bitfld.long 0x30 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_9_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_9" "0,1" newline bitfld.long 0x30 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_8_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_8" "0,1" newline bitfld.long 0x30 7. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_7_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_7" "0,1" newline bitfld.long 0x30 6. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_6_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_6" "0,1" newline bitfld.long 0x30 5. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_5_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_5" "0,1" newline bitfld.long 0x30 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_4_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_4" "0,1" newline bitfld.long 0x30 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_3_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_3" "0,1" newline bitfld.long 0x30 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_2_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_2" "0,1" newline bitfld.long 0x30 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_1_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_1" "0,1" newline bitfld.long 0x30 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_0_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_0" "0,1" line.long 0x34 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_dmpac_out_1_6,Enable Clear Register 13" bitfld.long 0x34 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_CTM_PULSE_CLR,Enable Clear for level_dmpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0x34 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_PROT_ERR_CLR,Enable Clear for level_dmpac_out_1_en_dru_prot_err" "0,1" line.long 0x38 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_dmpac_out_0_0,Enable Clear Register 14" bitfld.long 0x38 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_1_SL2_WR_ERR_CLR,Enable Clear for pulse_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1" newline bitfld.long 0x38 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_1_SL2_RD_ERR_CLR,Enable Clear for pulse_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1" newline bitfld.long 0x38 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_1_FR_DONE_EVT_CLR,Enable Clear for pulse_dmpac_out_0_en_foco_1_fr_done_evt" "0,1" newline bitfld.long 0x38 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_0_SL2_WR_ERR_CLR,Enable Clear for pulse_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1" newline bitfld.long 0x38 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_0_SL2_RD_ERR_CLR,Enable Clear for pulse_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1" newline bitfld.long 0x38 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_0_FR_DONE_EVT_CLR,Enable Clear for pulse_dmpac_out_0_en_foco_0_fr_done_evt" "0,1" newline bitfld.long 0x38 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_WRITE_ERROR_CLR,Enable Clear for pulse_dmpac_out_0_en_sde_write_error" "0,1" newline bitfld.long 0x38 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_READ_ERROR_CLR,Enable Clear for pulse_dmpac_out_0_en_sde_read_error" "0,1" newline bitfld.long 0x38 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_FRAME_DONE_CLR,Enable Clear for pulse_dmpac_out_0_en_sde_frame_done" "0,1" newline bitfld.long 0x38 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_BLK_DONE_CLR,Enable Clear for pulse_dmpac_out_0_en_sde_blk_done" "0,1" newline bitfld.long 0x38 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_MP0_RD_STATUS_ERROR_CLR,Enable Clear for pulse_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1" newline bitfld.long 0x38 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_WRITE_ERROR_CLR,Enable Clear for pulse_dmpac_out_0_en_dof_write_error" "0,1" newline bitfld.long 0x38 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_READ_ERROR_CLR,Enable Clear for pulse_dmpac_out_0_en_dof_read_error" "0,1" newline bitfld.long 0x38 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_FRAME_DONE_CLR,Enable Clear for pulse_dmpac_out_0_en_dof_frame_done" "0,1" newline bitfld.long 0x38 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_ROW_DONE_CLR,Enable Clear for pulse_dmpac_out_0_en_dof_row_done" "0,1" line.long 0x3C "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_dmpac_out_0_1,Enable Clear Register 15" bitfld.long 0x3C 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_8_CLR,Enable Clear for pulse_dmpac_out_0_en_tdone_8" "0,1" newline bitfld.long 0x3C 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_7_CLR,Enable Clear for pulse_dmpac_out_0_en_tdone_7" "0,1" newline bitfld.long 0x3C 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_1_CLR,Enable Clear for pulse_dmpac_out_0_en_tdone_1" "0,1" newline bitfld.long 0x3C 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_0_CLR,Enable Clear for pulse_dmpac_out_0_en_tdone_0" "0,1" newline bitfld.long 0x3C 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_1_L_CLR,Enable Clear for pulse_dmpac_out_0_en_spare_pend_1_l" "0,1" newline bitfld.long 0x3C 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_1_P_CLR,Enable Clear for pulse_dmpac_out_0_en_spare_pend_1_p" "0,1" newline bitfld.long 0x3C 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_0_L_CLR,Enable Clear for pulse_dmpac_out_0_en_spare_pend_0_l" "0,1" newline bitfld.long 0x3C 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_0_P_CLR,Enable Clear for pulse_dmpac_out_0_en_spare_pend_0_p" "0,1" newline bitfld.long 0x3C 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_dmpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0x3C 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_dmpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0x3C 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_dmpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0x3C 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_dmpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0x3C 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_dmpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0x3C 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_dmpac_out_0_en_pipe_done_0" "0,1" line.long 0x40 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_dmpac_out_0_2,Enable Clear Register 16" bitfld.long 0x40 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_8_CLR,Enable Clear for pulse_dmpac_out_0_en_watchdogtimer_err_8" "0,1" newline bitfld.long 0x40 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_7_CLR,Enable Clear for pulse_dmpac_out_0_en_watchdogtimer_err_7" "0,1" newline bitfld.long 0x40 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_1_CLR,Enable Clear for pulse_dmpac_out_0_en_watchdogtimer_err_1" "0,1" newline bitfld.long 0x40 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_dmpac_out_0_en_watchdogtimer_err_0" "0,1" line.long 0x44 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_dmpac_out_0_3,Enable Clear Register 17" bitfld.long 0x44 31. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_31_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_31" "0,1" newline bitfld.long 0x44 30. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_30_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_30" "0,1" newline bitfld.long 0x44 29. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_29_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_29" "0,1" newline bitfld.long 0x44 28. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_28_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_28" "0,1" newline bitfld.long 0x44 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_27_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_27" "0,1" newline bitfld.long 0x44 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_26_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_26" "0,1" newline bitfld.long 0x44 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_25_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_25" "0,1" newline bitfld.long 0x44 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_24_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_24" "0,1" newline bitfld.long 0x44 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_23_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_23" "0,1" newline bitfld.long 0x44 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_22_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_22" "0,1" newline bitfld.long 0x44 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_21_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_21" "0,1" newline bitfld.long 0x44 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_20_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_20" "0,1" newline bitfld.long 0x44 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_19_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_19" "0,1" newline bitfld.long 0x44 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_18_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_18" "0,1" newline bitfld.long 0x44 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_17_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_17" "0,1" newline bitfld.long 0x44 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_16_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_16" "0,1" newline bitfld.long 0x44 15. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_15_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_15" "0,1" newline bitfld.long 0x44 14. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_14_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_14" "0,1" newline bitfld.long 0x44 13. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_13_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_13" "0,1" newline bitfld.long 0x44 12. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_12_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_12" "0,1" newline bitfld.long 0x44 11. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_11_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_11" "0,1" newline bitfld.long 0x44 10. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_10_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_10" "0,1" newline bitfld.long 0x44 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_9_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_9" "0,1" newline bitfld.long 0x44 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_8_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_8" "0,1" newline bitfld.long 0x44 7. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_7_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_7" "0,1" newline bitfld.long 0x44 6. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_6_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_6" "0,1" newline bitfld.long 0x44 5. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_5_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_5" "0,1" newline bitfld.long 0x44 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_4_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_4" "0,1" newline bitfld.long 0x44 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_3_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_3" "0,1" newline bitfld.long 0x44 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_2_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_2" "0,1" newline bitfld.long 0x44 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_1_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_1" "0,1" newline bitfld.long 0x44 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_0_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_0" "0,1" line.long 0x48 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_dmpac_out_0_4,Enable Clear Register 18" bitfld.long 0x48 31. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_31_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_31" "0,1" newline bitfld.long 0x48 30. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_30_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_30" "0,1" newline bitfld.long 0x48 29. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_29_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_29" "0,1" newline bitfld.long 0x48 28. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_28_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_28" "0,1" newline bitfld.long 0x48 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_27_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_27" "0,1" newline bitfld.long 0x48 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_26_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_26" "0,1" newline bitfld.long 0x48 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_25_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_25" "0,1" newline bitfld.long 0x48 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_24_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_24" "0,1" newline bitfld.long 0x48 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_23_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_23" "0,1" newline bitfld.long 0x48 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_22_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_22" "0,1" newline bitfld.long 0x48 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_21_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_21" "0,1" newline bitfld.long 0x48 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_20_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_20" "0,1" newline bitfld.long 0x48 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_19_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_19" "0,1" newline bitfld.long 0x48 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_18_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_18" "0,1" newline bitfld.long 0x48 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_17_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_17" "0,1" newline bitfld.long 0x48 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_16_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_16" "0,1" newline bitfld.long 0x48 15. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_15_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_15" "0,1" newline bitfld.long 0x48 14. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_14_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_14" "0,1" newline bitfld.long 0x48 13. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_13_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_13" "0,1" newline bitfld.long 0x48 12. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_12_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_12" "0,1" newline bitfld.long 0x48 11. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_11_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_11" "0,1" newline bitfld.long 0x48 10. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_10_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_10" "0,1" newline bitfld.long 0x48 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_9_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_9" "0,1" newline bitfld.long 0x48 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_8_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_8" "0,1" newline bitfld.long 0x48 7. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_7_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_7" "0,1" newline bitfld.long 0x48 6. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_6_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_6" "0,1" newline bitfld.long 0x48 5. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_5_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_5" "0,1" newline bitfld.long 0x48 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_4_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_4" "0,1" newline bitfld.long 0x48 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_3_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_3" "0,1" newline bitfld.long 0x48 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_2_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_2" "0,1" newline bitfld.long 0x48 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_1_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_1" "0,1" newline bitfld.long 0x48 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_0_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_0" "0,1" line.long 0x4C "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_dmpac_out_0_5,Enable Clear Register 19" bitfld.long 0x4C 31. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_31_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_31" "0,1" newline bitfld.long 0x4C 30. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_30_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_30" "0,1" newline bitfld.long 0x4C 29. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_29_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_29" "0,1" newline bitfld.long 0x4C 28. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_28_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_28" "0,1" newline bitfld.long 0x4C 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_27_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_27" "0,1" newline bitfld.long 0x4C 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_26_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_26" "0,1" newline bitfld.long 0x4C 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_25_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_25" "0,1" newline bitfld.long 0x4C 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_24_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_24" "0,1" newline bitfld.long 0x4C 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_23_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_23" "0,1" newline bitfld.long 0x4C 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_22_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_22" "0,1" newline bitfld.long 0x4C 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_21_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_21" "0,1" newline bitfld.long 0x4C 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_20_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_20" "0,1" newline bitfld.long 0x4C 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_19_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_19" "0,1" newline bitfld.long 0x4C 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_18_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_18" "0,1" newline bitfld.long 0x4C 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_17_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_17" "0,1" newline bitfld.long 0x4C 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_16_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_16" "0,1" newline bitfld.long 0x4C 15. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_15_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_15" "0,1" newline bitfld.long 0x4C 14. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_14_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_14" "0,1" newline bitfld.long 0x4C 13. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_13_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_13" "0,1" newline bitfld.long 0x4C 12. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_12_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_12" "0,1" newline bitfld.long 0x4C 11. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_11_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_11" "0,1" newline bitfld.long 0x4C 10. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_10_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_10" "0,1" newline bitfld.long 0x4C 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_9_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_9" "0,1" newline bitfld.long 0x4C 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_8_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_8" "0,1" newline bitfld.long 0x4C 7. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_7_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_7" "0,1" newline bitfld.long 0x4C 6. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_6_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_6" "0,1" newline bitfld.long 0x4C 5. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_5_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_5" "0,1" newline bitfld.long 0x4C 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_4_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_4" "0,1" newline bitfld.long 0x4C 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_3_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_3" "0,1" newline bitfld.long 0x4C 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_2_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_2" "0,1" newline bitfld.long 0x4C 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_1_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_1" "0,1" newline bitfld.long 0x4C 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_0_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_0" "0,1" line.long 0x50 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_dmpac_out_0_6,Enable Clear Register 20" bitfld.long 0x50 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_CTM_PULSE_CLR,Enable Clear for pulse_dmpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0x50 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_PROT_ERR_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_prot_err" "0,1" line.long 0x54 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_dmpac_out_1_0,Enable Clear Register 21" bitfld.long 0x54 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_1_SL2_WR_ERR_CLR,Enable Clear for pulse_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1" newline bitfld.long 0x54 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_1_SL2_RD_ERR_CLR,Enable Clear for pulse_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1" newline bitfld.long 0x54 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_1_FR_DONE_EVT_CLR,Enable Clear for pulse_dmpac_out_1_en_foco_1_fr_done_evt" "0,1" newline bitfld.long 0x54 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_0_SL2_WR_ERR_CLR,Enable Clear for pulse_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1" newline bitfld.long 0x54 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_0_SL2_RD_ERR_CLR,Enable Clear for pulse_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1" newline bitfld.long 0x54 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_0_FR_DONE_EVT_CLR,Enable Clear for pulse_dmpac_out_1_en_foco_0_fr_done_evt" "0,1" newline bitfld.long 0x54 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_WRITE_ERROR_CLR,Enable Clear for pulse_dmpac_out_1_en_sde_write_error" "0,1" newline bitfld.long 0x54 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_READ_ERROR_CLR,Enable Clear for pulse_dmpac_out_1_en_sde_read_error" "0,1" newline bitfld.long 0x54 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_FRAME_DONE_CLR,Enable Clear for pulse_dmpac_out_1_en_sde_frame_done" "0,1" newline bitfld.long 0x54 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_BLK_DONE_CLR,Enable Clear for pulse_dmpac_out_1_en_sde_blk_done" "0,1" newline bitfld.long 0x54 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_MP0_RD_STATUS_ERROR_CLR,Enable Clear for pulse_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1" newline bitfld.long 0x54 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_WRITE_ERROR_CLR,Enable Clear for pulse_dmpac_out_1_en_dof_write_error" "0,1" newline bitfld.long 0x54 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_READ_ERROR_CLR,Enable Clear for pulse_dmpac_out_1_en_dof_read_error" "0,1" newline bitfld.long 0x54 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_FRAME_DONE_CLR,Enable Clear for pulse_dmpac_out_1_en_dof_frame_done" "0,1" newline bitfld.long 0x54 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_ROW_DONE_CLR,Enable Clear for pulse_dmpac_out_1_en_dof_row_done" "0,1" line.long 0x58 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_dmpac_out_1_1,Enable Clear Register 22" bitfld.long 0x58 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_8_CLR,Enable Clear for pulse_dmpac_out_1_en_tdone_8" "0,1" newline bitfld.long 0x58 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_7_CLR,Enable Clear for pulse_dmpac_out_1_en_tdone_7" "0,1" newline bitfld.long 0x58 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_1_CLR,Enable Clear for pulse_dmpac_out_1_en_tdone_1" "0,1" newline bitfld.long 0x58 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_0_CLR,Enable Clear for pulse_dmpac_out_1_en_tdone_0" "0,1" newline bitfld.long 0x58 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_1_L_CLR,Enable Clear for pulse_dmpac_out_1_en_spare_pend_1_l" "0,1" newline bitfld.long 0x58 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_1_P_CLR,Enable Clear for pulse_dmpac_out_1_en_spare_pend_1_p" "0,1" newline bitfld.long 0x58 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_0_L_CLR,Enable Clear for pulse_dmpac_out_1_en_spare_pend_0_l" "0,1" newline bitfld.long 0x58 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_0_P_CLR,Enable Clear for pulse_dmpac_out_1_en_spare_pend_0_p" "0,1" newline bitfld.long 0x58 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_dmpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0x58 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_dmpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0x58 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_dmpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0x58 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_dmpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0x58 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_dmpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0x58 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_dmpac_out_1_en_pipe_done_0" "0,1" line.long 0x5C "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_dmpac_out_1_2,Enable Clear Register 23" bitfld.long 0x5C 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_8_CLR,Enable Clear for pulse_dmpac_out_1_en_watchdogtimer_err_8" "0,1" newline bitfld.long 0x5C 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_7_CLR,Enable Clear for pulse_dmpac_out_1_en_watchdogtimer_err_7" "0,1" newline bitfld.long 0x5C 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_1_CLR,Enable Clear for pulse_dmpac_out_1_en_watchdogtimer_err_1" "0,1" newline bitfld.long 0x5C 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_dmpac_out_1_en_watchdogtimer_err_0" "0,1" line.long 0x60 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_dmpac_out_1_3,Enable Clear Register 24" bitfld.long 0x60 31. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_31_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_31" "0,1" newline bitfld.long 0x60 30. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_30_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_30" "0,1" newline bitfld.long 0x60 29. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_29_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_29" "0,1" newline bitfld.long 0x60 28. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_28_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_28" "0,1" newline bitfld.long 0x60 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_27_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_27" "0,1" newline bitfld.long 0x60 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_26_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_26" "0,1" newline bitfld.long 0x60 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_25_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_25" "0,1" newline bitfld.long 0x60 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_24_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_24" "0,1" newline bitfld.long 0x60 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_23_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_23" "0,1" newline bitfld.long 0x60 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_22_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_22" "0,1" newline bitfld.long 0x60 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_21_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_21" "0,1" newline bitfld.long 0x60 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_20_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_20" "0,1" newline bitfld.long 0x60 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_19_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_19" "0,1" newline bitfld.long 0x60 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_18_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_18" "0,1" newline bitfld.long 0x60 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_17_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_17" "0,1" newline bitfld.long 0x60 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_16_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_16" "0,1" newline bitfld.long 0x60 15. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_15_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_15" "0,1" newline bitfld.long 0x60 14. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_14_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_14" "0,1" newline bitfld.long 0x60 13. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_13_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_13" "0,1" newline bitfld.long 0x60 12. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_12_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_12" "0,1" newline bitfld.long 0x60 11. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_11_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_11" "0,1" newline bitfld.long 0x60 10. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_10_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_10" "0,1" newline bitfld.long 0x60 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_9_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_9" "0,1" newline bitfld.long 0x60 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_8_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_8" "0,1" newline bitfld.long 0x60 7. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_7_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_7" "0,1" newline bitfld.long 0x60 6. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_6_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_6" "0,1" newline bitfld.long 0x60 5. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_5_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_5" "0,1" newline bitfld.long 0x60 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_4_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_4" "0,1" newline bitfld.long 0x60 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_3_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_3" "0,1" newline bitfld.long 0x60 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_2_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_2" "0,1" newline bitfld.long 0x60 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_1_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_1" "0,1" newline bitfld.long 0x60 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_0_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_0" "0,1" line.long 0x64 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_dmpac_out_1_4,Enable Clear Register 25" bitfld.long 0x64 31. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_31_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_31" "0,1" newline bitfld.long 0x64 30. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_30_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_30" "0,1" newline bitfld.long 0x64 29. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_29_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_29" "0,1" newline bitfld.long 0x64 28. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_28_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_28" "0,1" newline bitfld.long 0x64 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_27_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_27" "0,1" newline bitfld.long 0x64 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_26_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_26" "0,1" newline bitfld.long 0x64 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_25_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_25" "0,1" newline bitfld.long 0x64 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_24_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_24" "0,1" newline bitfld.long 0x64 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_23_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_23" "0,1" newline bitfld.long 0x64 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_22_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_22" "0,1" newline bitfld.long 0x64 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_21_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_21" "0,1" newline bitfld.long 0x64 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_20_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_20" "0,1" newline bitfld.long 0x64 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_19_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_19" "0,1" newline bitfld.long 0x64 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_18_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_18" "0,1" newline bitfld.long 0x64 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_17_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_17" "0,1" newline bitfld.long 0x64 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_16_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_16" "0,1" newline bitfld.long 0x64 15. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_15_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_15" "0,1" newline bitfld.long 0x64 14. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_14_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_14" "0,1" newline bitfld.long 0x64 13. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_13_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_13" "0,1" newline bitfld.long 0x64 12. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_12_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_12" "0,1" newline bitfld.long 0x64 11. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_11_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_11" "0,1" newline bitfld.long 0x64 10. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_10_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_10" "0,1" newline bitfld.long 0x64 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_9_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_9" "0,1" newline bitfld.long 0x64 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_8_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_8" "0,1" newline bitfld.long 0x64 7. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_7_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_7" "0,1" newline bitfld.long 0x64 6. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_6_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_6" "0,1" newline bitfld.long 0x64 5. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_5_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_5" "0,1" newline bitfld.long 0x64 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_4_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_4" "0,1" newline bitfld.long 0x64 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_3_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_3" "0,1" newline bitfld.long 0x64 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_2_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_2" "0,1" newline bitfld.long 0x64 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_1_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_1" "0,1" newline bitfld.long 0x64 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_0_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_0" "0,1" line.long 0x68 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_dmpac_out_1_5,Enable Clear Register 26" bitfld.long 0x68 31. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_31_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_31" "0,1" newline bitfld.long 0x68 30. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_30_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_30" "0,1" newline bitfld.long 0x68 29. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_29_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_29" "0,1" newline bitfld.long 0x68 28. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_28_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_28" "0,1" newline bitfld.long 0x68 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_27_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_27" "0,1" newline bitfld.long 0x68 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_26_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_26" "0,1" newline bitfld.long 0x68 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_25_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_25" "0,1" newline bitfld.long 0x68 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_24_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_24" "0,1" newline bitfld.long 0x68 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_23_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_23" "0,1" newline bitfld.long 0x68 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_22_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_22" "0,1" newline bitfld.long 0x68 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_21_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_21" "0,1" newline bitfld.long 0x68 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_20_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_20" "0,1" newline bitfld.long 0x68 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_19_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_19" "0,1" newline bitfld.long 0x68 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_18_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_18" "0,1" newline bitfld.long 0x68 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_17_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_17" "0,1" newline bitfld.long 0x68 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_16_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_16" "0,1" newline bitfld.long 0x68 15. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_15_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_15" "0,1" newline bitfld.long 0x68 14. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_14_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_14" "0,1" newline bitfld.long 0x68 13. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_13_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_13" "0,1" newline bitfld.long 0x68 12. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_12_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_12" "0,1" newline bitfld.long 0x68 11. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_11_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_11" "0,1" newline bitfld.long 0x68 10. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_10_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_10" "0,1" newline bitfld.long 0x68 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_9_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_9" "0,1" newline bitfld.long 0x68 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_8_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_8" "0,1" newline bitfld.long 0x68 7. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_7_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_7" "0,1" newline bitfld.long 0x68 6. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_6_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_6" "0,1" newline bitfld.long 0x68 5. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_5_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_5" "0,1" newline bitfld.long 0x68 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_4_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_4" "0,1" newline bitfld.long 0x68 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_3_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_3" "0,1" newline bitfld.long 0x68 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_2_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_2" "0,1" newline bitfld.long 0x68 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_1_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_1" "0,1" newline bitfld.long 0x68 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_0_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_0" "0,1" line.long 0x6C "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_dmpac_out_1_6,Enable Clear Register 27" bitfld.long 0x6C 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_CTM_PULSE_CLR,Enable Clear for pulse_dmpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0x6C 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_PROT_ERR_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_prot_err" "0,1" rgroup.long 0x500++0x6F line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_dmpac_out_0_0,Status Register 0" bitfld.long 0x0 25. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_1_SL2_WR_ERR,Status write 1 to set for level_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1" newline bitfld.long 0x0 24. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_1_SL2_RD_ERR,Status write 1 to set for level_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1" newline bitfld.long 0x0 23. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_1_FR_DONE_EVT,Status write 1 to set for level_dmpac_out_0_en_foco_1_fr_done_evt" "0,1" newline bitfld.long 0x0 22. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_0_SL2_WR_ERR,Status write 1 to set for level_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1" newline bitfld.long 0x0 21. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_0_SL2_RD_ERR,Status write 1 to set for level_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1" newline bitfld.long 0x0 20. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_0_FR_DONE_EVT,Status write 1 to set for level_dmpac_out_0_en_foco_0_fr_done_evt" "0,1" newline bitfld.long 0x0 19. "STATUS_LEVEL_DMPAC_OUT_0_SDE_WRITE_ERROR,Status write 1 to set for level_dmpac_out_0_en_sde_write_error" "0,1" newline bitfld.long 0x0 18. "STATUS_LEVEL_DMPAC_OUT_0_SDE_READ_ERROR,Status write 1 to set for level_dmpac_out_0_en_sde_read_error" "0,1" newline bitfld.long 0x0 17. "STATUS_LEVEL_DMPAC_OUT_0_SDE_FRAME_DONE,Status write 1 to set for level_dmpac_out_0_en_sde_frame_done" "0,1" newline bitfld.long 0x0 16. "STATUS_LEVEL_DMPAC_OUT_0_SDE_BLK_DONE,Status write 1 to set for level_dmpac_out_0_en_sde_blk_done" "0,1" newline bitfld.long 0x0 4. "STATUS_LEVEL_DMPAC_OUT_0_DOF_MP0_RD_STATUS_ERROR,Status write 1 to set for level_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1" newline bitfld.long 0x0 3. "STATUS_LEVEL_DMPAC_OUT_0_DOF_WRITE_ERROR,Status write 1 to set for level_dmpac_out_0_en_dof_write_error" "0,1" newline bitfld.long 0x0 2. "STATUS_LEVEL_DMPAC_OUT_0_DOF_READ_ERROR,Status write 1 to set for level_dmpac_out_0_en_dof_read_error" "0,1" newline bitfld.long 0x0 1. "STATUS_LEVEL_DMPAC_OUT_0_DOF_FRAME_DONE,Status write 1 to set for level_dmpac_out_0_en_dof_frame_done" "0,1" newline bitfld.long 0x0 0. "STATUS_LEVEL_DMPAC_OUT_0_DOF_ROW_DONE,Status write 1 to set for level_dmpac_out_0_en_dof_row_done" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_dmpac_out_0_1,Status Register 1" bitfld.long 0x4 27. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_8,Status write 1 to set for level_dmpac_out_0_en_tdone_8" "0,1" newline bitfld.long 0x4 26. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_7,Status write 1 to set for level_dmpac_out_0_en_tdone_7" "0,1" newline bitfld.long 0x4 25. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_1,Status write 1 to set for level_dmpac_out_0_en_tdone_1" "0,1" newline bitfld.long 0x4 24. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_0,Status write 1 to set for level_dmpac_out_0_en_tdone_0" "0,1" newline rbitfld.long 0x4 19. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_PEND_1_L,Status for level_dmpac_out_0_en_spare_pend_1_l" "0,1" newline rbitfld.long 0x4 18. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_PEND_1_P,Status for level_dmpac_out_0_en_spare_pend_1_p" "0,1" newline rbitfld.long 0x4 17. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_PEND_0_L,Status for level_dmpac_out_0_en_spare_pend_0_l" "0,1" newline rbitfld.long 0x4 16. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_PEND_0_P,Status for level_dmpac_out_0_en_spare_pend_0_p" "0,1" newline bitfld.long 0x4 9. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_DEC_1,Status write 1 to set for level_dmpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0x4 8. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_DEC_0,Status write 1 to set for level_dmpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0x4 3. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_3,Status write 1 to set for level_dmpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0x4 2. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_2,Status write 1 to set for level_dmpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0x4 1. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_1,Status write 1 to set for level_dmpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0x4 0. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_0,Status write 1 to set for level_dmpac_out_0_en_pipe_done_0" "0,1" line.long 0x8 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_dmpac_out_0_2,Status Register 2" bitfld.long 0x8 3. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_8,Status write 1 to set for level_dmpac_out_0_en_watchdogtimer_err_8" "0,1" newline bitfld.long 0x8 2. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_7,Status write 1 to set for level_dmpac_out_0_en_watchdogtimer_err_7" "0,1" newline bitfld.long 0x8 1. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_1,Status write 1 to set for level_dmpac_out_0_en_watchdogtimer_err_1" "0,1" newline bitfld.long 0x8 0. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_dmpac_out_0_en_watchdogtimer_err_0" "0,1" line.long 0xC "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_dmpac_out_0_3,Status Register 3" bitfld.long 0xC 31. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_31,Status write 1 to set for level_dmpac_out_0_en_dru_error_31" "0,1" newline bitfld.long 0xC 30. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_30,Status write 1 to set for level_dmpac_out_0_en_dru_error_30" "0,1" newline bitfld.long 0xC 29. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_29,Status write 1 to set for level_dmpac_out_0_en_dru_error_29" "0,1" newline bitfld.long 0xC 28. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_28,Status write 1 to set for level_dmpac_out_0_en_dru_error_28" "0,1" newline bitfld.long 0xC 27. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_27,Status write 1 to set for level_dmpac_out_0_en_dru_error_27" "0,1" newline bitfld.long 0xC 26. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_26,Status write 1 to set for level_dmpac_out_0_en_dru_error_26" "0,1" newline bitfld.long 0xC 25. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_25,Status write 1 to set for level_dmpac_out_0_en_dru_error_25" "0,1" newline bitfld.long 0xC 24. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_24,Status write 1 to set for level_dmpac_out_0_en_dru_error_24" "0,1" newline bitfld.long 0xC 23. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_23,Status write 1 to set for level_dmpac_out_0_en_dru_error_23" "0,1" newline bitfld.long 0xC 22. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_22,Status write 1 to set for level_dmpac_out_0_en_dru_error_22" "0,1" newline bitfld.long 0xC 21. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_21,Status write 1 to set for level_dmpac_out_0_en_dru_error_21" "0,1" newline bitfld.long 0xC 20. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_20,Status write 1 to set for level_dmpac_out_0_en_dru_error_20" "0,1" newline bitfld.long 0xC 19. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_19,Status write 1 to set for level_dmpac_out_0_en_dru_error_19" "0,1" newline bitfld.long 0xC 18. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_18,Status write 1 to set for level_dmpac_out_0_en_dru_error_18" "0,1" newline bitfld.long 0xC 17. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_17,Status write 1 to set for level_dmpac_out_0_en_dru_error_17" "0,1" newline bitfld.long 0xC 16. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_16,Status write 1 to set for level_dmpac_out_0_en_dru_error_16" "0,1" newline bitfld.long 0xC 15. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_15,Status write 1 to set for level_dmpac_out_0_en_dru_error_15" "0,1" newline bitfld.long 0xC 14. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_14,Status write 1 to set for level_dmpac_out_0_en_dru_error_14" "0,1" newline bitfld.long 0xC 13. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_13,Status write 1 to set for level_dmpac_out_0_en_dru_error_13" "0,1" newline bitfld.long 0xC 12. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_12,Status write 1 to set for level_dmpac_out_0_en_dru_error_12" "0,1" newline bitfld.long 0xC 11. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_11,Status write 1 to set for level_dmpac_out_0_en_dru_error_11" "0,1" newline bitfld.long 0xC 10. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_10,Status write 1 to set for level_dmpac_out_0_en_dru_error_10" "0,1" newline bitfld.long 0xC 9. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_9,Status write 1 to set for level_dmpac_out_0_en_dru_error_9" "0,1" newline bitfld.long 0xC 8. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_8,Status write 1 to set for level_dmpac_out_0_en_dru_error_8" "0,1" newline bitfld.long 0xC 7. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_7,Status write 1 to set for level_dmpac_out_0_en_dru_error_7" "0,1" newline bitfld.long 0xC 6. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_6,Status write 1 to set for level_dmpac_out_0_en_dru_error_6" "0,1" newline bitfld.long 0xC 5. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_5,Status write 1 to set for level_dmpac_out_0_en_dru_error_5" "0,1" newline bitfld.long 0xC 4. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_4,Status write 1 to set for level_dmpac_out_0_en_dru_error_4" "0,1" newline bitfld.long 0xC 3. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_3,Status write 1 to set for level_dmpac_out_0_en_dru_error_3" "0,1" newline bitfld.long 0xC 2. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_2,Status write 1 to set for level_dmpac_out_0_en_dru_error_2" "0,1" newline bitfld.long 0xC 1. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_1,Status write 1 to set for level_dmpac_out_0_en_dru_error_1" "0,1" newline bitfld.long 0xC 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_0,Status write 1 to set for level_dmpac_out_0_en_dru_error_0" "0,1" line.long 0x10 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_dmpac_out_0_4,Status Register 4" bitfld.long 0x10 31. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_31,Status write 1 to set for level_dmpac_out_0_en_dru_complete_31" "0,1" newline bitfld.long 0x10 30. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_30,Status write 1 to set for level_dmpac_out_0_en_dru_complete_30" "0,1" newline bitfld.long 0x10 29. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_29,Status write 1 to set for level_dmpac_out_0_en_dru_complete_29" "0,1" newline bitfld.long 0x10 28. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_28,Status write 1 to set for level_dmpac_out_0_en_dru_complete_28" "0,1" newline bitfld.long 0x10 27. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_27,Status write 1 to set for level_dmpac_out_0_en_dru_complete_27" "0,1" newline bitfld.long 0x10 26. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_26,Status write 1 to set for level_dmpac_out_0_en_dru_complete_26" "0,1" newline bitfld.long 0x10 25. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_25,Status write 1 to set for level_dmpac_out_0_en_dru_complete_25" "0,1" newline bitfld.long 0x10 24. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_24,Status write 1 to set for level_dmpac_out_0_en_dru_complete_24" "0,1" newline bitfld.long 0x10 23. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_23,Status write 1 to set for level_dmpac_out_0_en_dru_complete_23" "0,1" newline bitfld.long 0x10 22. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_22,Status write 1 to set for level_dmpac_out_0_en_dru_complete_22" "0,1" newline bitfld.long 0x10 21. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_21,Status write 1 to set for level_dmpac_out_0_en_dru_complete_21" "0,1" newline bitfld.long 0x10 20. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_20,Status write 1 to set for level_dmpac_out_0_en_dru_complete_20" "0,1" newline bitfld.long 0x10 19. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_19,Status write 1 to set for level_dmpac_out_0_en_dru_complete_19" "0,1" newline bitfld.long 0x10 18. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_18,Status write 1 to set for level_dmpac_out_0_en_dru_complete_18" "0,1" newline bitfld.long 0x10 17. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_17,Status write 1 to set for level_dmpac_out_0_en_dru_complete_17" "0,1" newline bitfld.long 0x10 16. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_16,Status write 1 to set for level_dmpac_out_0_en_dru_complete_16" "0,1" newline bitfld.long 0x10 15. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_15,Status write 1 to set for level_dmpac_out_0_en_dru_complete_15" "0,1" newline bitfld.long 0x10 14. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_14,Status write 1 to set for level_dmpac_out_0_en_dru_complete_14" "0,1" newline bitfld.long 0x10 13. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_13,Status write 1 to set for level_dmpac_out_0_en_dru_complete_13" "0,1" newline bitfld.long 0x10 12. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_12,Status write 1 to set for level_dmpac_out_0_en_dru_complete_12" "0,1" newline bitfld.long 0x10 11. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_11,Status write 1 to set for level_dmpac_out_0_en_dru_complete_11" "0,1" newline bitfld.long 0x10 10. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_10,Status write 1 to set for level_dmpac_out_0_en_dru_complete_10" "0,1" newline bitfld.long 0x10 9. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_9,Status write 1 to set for level_dmpac_out_0_en_dru_complete_9" "0,1" newline bitfld.long 0x10 8. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_8,Status write 1 to set for level_dmpac_out_0_en_dru_complete_8" "0,1" newline bitfld.long 0x10 7. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_7,Status write 1 to set for level_dmpac_out_0_en_dru_complete_7" "0,1" newline bitfld.long 0x10 6. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_6,Status write 1 to set for level_dmpac_out_0_en_dru_complete_6" "0,1" newline bitfld.long 0x10 5. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_5,Status write 1 to set for level_dmpac_out_0_en_dru_complete_5" "0,1" newline bitfld.long 0x10 4. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_4,Status write 1 to set for level_dmpac_out_0_en_dru_complete_4" "0,1" newline bitfld.long 0x10 3. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_3,Status write 1 to set for level_dmpac_out_0_en_dru_complete_3" "0,1" newline bitfld.long 0x10 2. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_2,Status write 1 to set for level_dmpac_out_0_en_dru_complete_2" "0,1" newline bitfld.long 0x10 1. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_1,Status write 1 to set for level_dmpac_out_0_en_dru_complete_1" "0,1" newline bitfld.long 0x10 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_0,Status write 1 to set for level_dmpac_out_0_en_dru_complete_0" "0,1" line.long 0x14 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_dmpac_out_0_5,Status Register 5" bitfld.long 0x14 31. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_31,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_31" "0,1" newline bitfld.long 0x14 30. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_30,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_30" "0,1" newline bitfld.long 0x14 29. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_29,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_29" "0,1" newline bitfld.long 0x14 28. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_28,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_28" "0,1" newline bitfld.long 0x14 27. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_27,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_27" "0,1" newline bitfld.long 0x14 26. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_26,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_26" "0,1" newline bitfld.long 0x14 25. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_25,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_25" "0,1" newline bitfld.long 0x14 24. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_24,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_24" "0,1" newline bitfld.long 0x14 23. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_23,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_23" "0,1" newline bitfld.long 0x14 22. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_22,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_22" "0,1" newline bitfld.long 0x14 21. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_21,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_21" "0,1" newline bitfld.long 0x14 20. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_20,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_20" "0,1" newline bitfld.long 0x14 19. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_19,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_19" "0,1" newline bitfld.long 0x14 18. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_18,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_18" "0,1" newline bitfld.long 0x14 17. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_17,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_17" "0,1" newline bitfld.long 0x14 16. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_16,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_16" "0,1" newline bitfld.long 0x14 15. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_15,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_15" "0,1" newline bitfld.long 0x14 14. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_14,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_14" "0,1" newline bitfld.long 0x14 13. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_13,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_13" "0,1" newline bitfld.long 0x14 12. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_12,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_12" "0,1" newline bitfld.long 0x14 11. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_11,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_11" "0,1" newline bitfld.long 0x14 10. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_10,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_10" "0,1" newline bitfld.long 0x14 9. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_9,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_9" "0,1" newline bitfld.long 0x14 8. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_8,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_8" "0,1" newline bitfld.long 0x14 7. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_7,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_7" "0,1" newline bitfld.long 0x14 6. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_6,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_6" "0,1" newline bitfld.long 0x14 5. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_5,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_5" "0,1" newline bitfld.long 0x14 4. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_4,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_4" "0,1" newline bitfld.long 0x14 3. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_3,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_3" "0,1" newline bitfld.long 0x14 2. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_2,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_2" "0,1" newline bitfld.long 0x14 1. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_1,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_1" "0,1" newline bitfld.long 0x14 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_0,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_0" "0,1" line.long 0x18 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_dmpac_out_0_6,Status Register 6" bitfld.long 0x18 1. "STATUS_LEVEL_DMPAC_OUT_0_CTM_PULSE,Status write 1 to set for level_dmpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0x18 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_PROT_ERR,Status write 1 to set for level_dmpac_out_0_en_dru_prot_err" "0,1" line.long 0x1C "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_dmpac_out_1_0,Status Register 7" bitfld.long 0x1C 25. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_1_SL2_WR_ERR,Status write 1 to set for level_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1" newline bitfld.long 0x1C 24. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_1_SL2_RD_ERR,Status write 1 to set for level_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1" newline bitfld.long 0x1C 23. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_1_FR_DONE_EVT,Status write 1 to set for level_dmpac_out_1_en_foco_1_fr_done_evt" "0,1" newline bitfld.long 0x1C 22. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_0_SL2_WR_ERR,Status write 1 to set for level_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1" newline bitfld.long 0x1C 21. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_0_SL2_RD_ERR,Status write 1 to set for level_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1" newline bitfld.long 0x1C 20. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_0_FR_DONE_EVT,Status write 1 to set for level_dmpac_out_1_en_foco_0_fr_done_evt" "0,1" newline bitfld.long 0x1C 19. "STATUS_LEVEL_DMPAC_OUT_1_SDE_WRITE_ERROR,Status write 1 to set for level_dmpac_out_1_en_sde_write_error" "0,1" newline bitfld.long 0x1C 18. "STATUS_LEVEL_DMPAC_OUT_1_SDE_READ_ERROR,Status write 1 to set for level_dmpac_out_1_en_sde_read_error" "0,1" newline bitfld.long 0x1C 17. "STATUS_LEVEL_DMPAC_OUT_1_SDE_FRAME_DONE,Status write 1 to set for level_dmpac_out_1_en_sde_frame_done" "0,1" newline bitfld.long 0x1C 16. "STATUS_LEVEL_DMPAC_OUT_1_SDE_BLK_DONE,Status write 1 to set for level_dmpac_out_1_en_sde_blk_done" "0,1" newline bitfld.long 0x1C 4. "STATUS_LEVEL_DMPAC_OUT_1_DOF_MP0_RD_STATUS_ERROR,Status write 1 to set for level_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1" newline bitfld.long 0x1C 3. "STATUS_LEVEL_DMPAC_OUT_1_DOF_WRITE_ERROR,Status write 1 to set for level_dmpac_out_1_en_dof_write_error" "0,1" newline bitfld.long 0x1C 2. "STATUS_LEVEL_DMPAC_OUT_1_DOF_READ_ERROR,Status write 1 to set for level_dmpac_out_1_en_dof_read_error" "0,1" newline bitfld.long 0x1C 1. "STATUS_LEVEL_DMPAC_OUT_1_DOF_FRAME_DONE,Status write 1 to set for level_dmpac_out_1_en_dof_frame_done" "0,1" newline bitfld.long 0x1C 0. "STATUS_LEVEL_DMPAC_OUT_1_DOF_ROW_DONE,Status write 1 to set for level_dmpac_out_1_en_dof_row_done" "0,1" line.long 0x20 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_dmpac_out_1_1,Status Register 8" bitfld.long 0x20 27. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_8,Status write 1 to set for level_dmpac_out_1_en_tdone_8" "0,1" newline bitfld.long 0x20 26. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_7,Status write 1 to set for level_dmpac_out_1_en_tdone_7" "0,1" newline bitfld.long 0x20 25. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_1,Status write 1 to set for level_dmpac_out_1_en_tdone_1" "0,1" newline bitfld.long 0x20 24. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_0,Status write 1 to set for level_dmpac_out_1_en_tdone_0" "0,1" newline rbitfld.long 0x20 19. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_PEND_1_L,Status for level_dmpac_out_1_en_spare_pend_1_l" "0,1" newline rbitfld.long 0x20 18. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_PEND_1_P,Status for level_dmpac_out_1_en_spare_pend_1_p" "0,1" newline rbitfld.long 0x20 17. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_PEND_0_L,Status for level_dmpac_out_1_en_spare_pend_0_l" "0,1" newline rbitfld.long 0x20 16. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_PEND_0_P,Status for level_dmpac_out_1_en_spare_pend_0_p" "0,1" newline bitfld.long 0x20 9. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_DEC_1,Status write 1 to set for level_dmpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0x20 8. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_DEC_0,Status write 1 to set for level_dmpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0x20 3. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_3,Status write 1 to set for level_dmpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0x20 2. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_2,Status write 1 to set for level_dmpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0x20 1. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_1,Status write 1 to set for level_dmpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0x20 0. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_0,Status write 1 to set for level_dmpac_out_1_en_pipe_done_0" "0,1" line.long 0x24 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_dmpac_out_1_2,Status Register 9" bitfld.long 0x24 3. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_8,Status write 1 to set for level_dmpac_out_1_en_watchdogtimer_err_8" "0,1" newline bitfld.long 0x24 2. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_7,Status write 1 to set for level_dmpac_out_1_en_watchdogtimer_err_7" "0,1" newline bitfld.long 0x24 1. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_1,Status write 1 to set for level_dmpac_out_1_en_watchdogtimer_err_1" "0,1" newline bitfld.long 0x24 0. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_dmpac_out_1_en_watchdogtimer_err_0" "0,1" line.long 0x28 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_dmpac_out_1_3,Status Register 10" bitfld.long 0x28 31. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_31,Status write 1 to set for level_dmpac_out_1_en_dru_error_31" "0,1" newline bitfld.long 0x28 30. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_30,Status write 1 to set for level_dmpac_out_1_en_dru_error_30" "0,1" newline bitfld.long 0x28 29. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_29,Status write 1 to set for level_dmpac_out_1_en_dru_error_29" "0,1" newline bitfld.long 0x28 28. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_28,Status write 1 to set for level_dmpac_out_1_en_dru_error_28" "0,1" newline bitfld.long 0x28 27. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_27,Status write 1 to set for level_dmpac_out_1_en_dru_error_27" "0,1" newline bitfld.long 0x28 26. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_26,Status write 1 to set for level_dmpac_out_1_en_dru_error_26" "0,1" newline bitfld.long 0x28 25. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_25,Status write 1 to set for level_dmpac_out_1_en_dru_error_25" "0,1" newline bitfld.long 0x28 24. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_24,Status write 1 to set for level_dmpac_out_1_en_dru_error_24" "0,1" newline bitfld.long 0x28 23. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_23,Status write 1 to set for level_dmpac_out_1_en_dru_error_23" "0,1" newline bitfld.long 0x28 22. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_22,Status write 1 to set for level_dmpac_out_1_en_dru_error_22" "0,1" newline bitfld.long 0x28 21. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_21,Status write 1 to set for level_dmpac_out_1_en_dru_error_21" "0,1" newline bitfld.long 0x28 20. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_20,Status write 1 to set for level_dmpac_out_1_en_dru_error_20" "0,1" newline bitfld.long 0x28 19. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_19,Status write 1 to set for level_dmpac_out_1_en_dru_error_19" "0,1" newline bitfld.long 0x28 18. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_18,Status write 1 to set for level_dmpac_out_1_en_dru_error_18" "0,1" newline bitfld.long 0x28 17. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_17,Status write 1 to set for level_dmpac_out_1_en_dru_error_17" "0,1" newline bitfld.long 0x28 16. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_16,Status write 1 to set for level_dmpac_out_1_en_dru_error_16" "0,1" newline bitfld.long 0x28 15. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_15,Status write 1 to set for level_dmpac_out_1_en_dru_error_15" "0,1" newline bitfld.long 0x28 14. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_14,Status write 1 to set for level_dmpac_out_1_en_dru_error_14" "0,1" newline bitfld.long 0x28 13. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_13,Status write 1 to set for level_dmpac_out_1_en_dru_error_13" "0,1" newline bitfld.long 0x28 12. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_12,Status write 1 to set for level_dmpac_out_1_en_dru_error_12" "0,1" newline bitfld.long 0x28 11. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_11,Status write 1 to set for level_dmpac_out_1_en_dru_error_11" "0,1" newline bitfld.long 0x28 10. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_10,Status write 1 to set for level_dmpac_out_1_en_dru_error_10" "0,1" newline bitfld.long 0x28 9. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_9,Status write 1 to set for level_dmpac_out_1_en_dru_error_9" "0,1" newline bitfld.long 0x28 8. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_8,Status write 1 to set for level_dmpac_out_1_en_dru_error_8" "0,1" newline bitfld.long 0x28 7. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_7,Status write 1 to set for level_dmpac_out_1_en_dru_error_7" "0,1" newline bitfld.long 0x28 6. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_6,Status write 1 to set for level_dmpac_out_1_en_dru_error_6" "0,1" newline bitfld.long 0x28 5. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_5,Status write 1 to set for level_dmpac_out_1_en_dru_error_5" "0,1" newline bitfld.long 0x28 4. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_4,Status write 1 to set for level_dmpac_out_1_en_dru_error_4" "0,1" newline bitfld.long 0x28 3. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_3,Status write 1 to set for level_dmpac_out_1_en_dru_error_3" "0,1" newline bitfld.long 0x28 2. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_2,Status write 1 to set for level_dmpac_out_1_en_dru_error_2" "0,1" newline bitfld.long 0x28 1. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_1,Status write 1 to set for level_dmpac_out_1_en_dru_error_1" "0,1" newline bitfld.long 0x28 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_0,Status write 1 to set for level_dmpac_out_1_en_dru_error_0" "0,1" line.long 0x2C "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_dmpac_out_1_4,Status Register 11" bitfld.long 0x2C 31. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_31,Status write 1 to set for level_dmpac_out_1_en_dru_complete_31" "0,1" newline bitfld.long 0x2C 30. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_30,Status write 1 to set for level_dmpac_out_1_en_dru_complete_30" "0,1" newline bitfld.long 0x2C 29. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_29,Status write 1 to set for level_dmpac_out_1_en_dru_complete_29" "0,1" newline bitfld.long 0x2C 28. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_28,Status write 1 to set for level_dmpac_out_1_en_dru_complete_28" "0,1" newline bitfld.long 0x2C 27. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_27,Status write 1 to set for level_dmpac_out_1_en_dru_complete_27" "0,1" newline bitfld.long 0x2C 26. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_26,Status write 1 to set for level_dmpac_out_1_en_dru_complete_26" "0,1" newline bitfld.long 0x2C 25. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_25,Status write 1 to set for level_dmpac_out_1_en_dru_complete_25" "0,1" newline bitfld.long 0x2C 24. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_24,Status write 1 to set for level_dmpac_out_1_en_dru_complete_24" "0,1" newline bitfld.long 0x2C 23. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_23,Status write 1 to set for level_dmpac_out_1_en_dru_complete_23" "0,1" newline bitfld.long 0x2C 22. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_22,Status write 1 to set for level_dmpac_out_1_en_dru_complete_22" "0,1" newline bitfld.long 0x2C 21. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_21,Status write 1 to set for level_dmpac_out_1_en_dru_complete_21" "0,1" newline bitfld.long 0x2C 20. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_20,Status write 1 to set for level_dmpac_out_1_en_dru_complete_20" "0,1" newline bitfld.long 0x2C 19. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_19,Status write 1 to set for level_dmpac_out_1_en_dru_complete_19" "0,1" newline bitfld.long 0x2C 18. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_18,Status write 1 to set for level_dmpac_out_1_en_dru_complete_18" "0,1" newline bitfld.long 0x2C 17. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_17,Status write 1 to set for level_dmpac_out_1_en_dru_complete_17" "0,1" newline bitfld.long 0x2C 16. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_16,Status write 1 to set for level_dmpac_out_1_en_dru_complete_16" "0,1" newline bitfld.long 0x2C 15. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_15,Status write 1 to set for level_dmpac_out_1_en_dru_complete_15" "0,1" newline bitfld.long 0x2C 14. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_14,Status write 1 to set for level_dmpac_out_1_en_dru_complete_14" "0,1" newline bitfld.long 0x2C 13. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_13,Status write 1 to set for level_dmpac_out_1_en_dru_complete_13" "0,1" newline bitfld.long 0x2C 12. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_12,Status write 1 to set for level_dmpac_out_1_en_dru_complete_12" "0,1" newline bitfld.long 0x2C 11. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_11,Status write 1 to set for level_dmpac_out_1_en_dru_complete_11" "0,1" newline bitfld.long 0x2C 10. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_10,Status write 1 to set for level_dmpac_out_1_en_dru_complete_10" "0,1" newline bitfld.long 0x2C 9. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_9,Status write 1 to set for level_dmpac_out_1_en_dru_complete_9" "0,1" newline bitfld.long 0x2C 8. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_8,Status write 1 to set for level_dmpac_out_1_en_dru_complete_8" "0,1" newline bitfld.long 0x2C 7. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_7,Status write 1 to set for level_dmpac_out_1_en_dru_complete_7" "0,1" newline bitfld.long 0x2C 6. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_6,Status write 1 to set for level_dmpac_out_1_en_dru_complete_6" "0,1" newline bitfld.long 0x2C 5. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_5,Status write 1 to set for level_dmpac_out_1_en_dru_complete_5" "0,1" newline bitfld.long 0x2C 4. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_4,Status write 1 to set for level_dmpac_out_1_en_dru_complete_4" "0,1" newline bitfld.long 0x2C 3. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_3,Status write 1 to set for level_dmpac_out_1_en_dru_complete_3" "0,1" newline bitfld.long 0x2C 2. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_2,Status write 1 to set for level_dmpac_out_1_en_dru_complete_2" "0,1" newline bitfld.long 0x2C 1. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_1,Status write 1 to set for level_dmpac_out_1_en_dru_complete_1" "0,1" newline bitfld.long 0x2C 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_0,Status write 1 to set for level_dmpac_out_1_en_dru_complete_0" "0,1" line.long 0x30 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_dmpac_out_1_5,Status Register 12" bitfld.long 0x30 31. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_31,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_31" "0,1" newline bitfld.long 0x30 30. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_30,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_30" "0,1" newline bitfld.long 0x30 29. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_29,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_29" "0,1" newline bitfld.long 0x30 28. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_28,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_28" "0,1" newline bitfld.long 0x30 27. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_27,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_27" "0,1" newline bitfld.long 0x30 26. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_26,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_26" "0,1" newline bitfld.long 0x30 25. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_25,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_25" "0,1" newline bitfld.long 0x30 24. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_24,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_24" "0,1" newline bitfld.long 0x30 23. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_23,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_23" "0,1" newline bitfld.long 0x30 22. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_22,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_22" "0,1" newline bitfld.long 0x30 21. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_21,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_21" "0,1" newline bitfld.long 0x30 20. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_20,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_20" "0,1" newline bitfld.long 0x30 19. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_19,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_19" "0,1" newline bitfld.long 0x30 18. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_18,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_18" "0,1" newline bitfld.long 0x30 17. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_17,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_17" "0,1" newline bitfld.long 0x30 16. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_16,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_16" "0,1" newline bitfld.long 0x30 15. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_15,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_15" "0,1" newline bitfld.long 0x30 14. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_14,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_14" "0,1" newline bitfld.long 0x30 13. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_13,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_13" "0,1" newline bitfld.long 0x30 12. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_12,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_12" "0,1" newline bitfld.long 0x30 11. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_11,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_11" "0,1" newline bitfld.long 0x30 10. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_10,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_10" "0,1" newline bitfld.long 0x30 9. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_9,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_9" "0,1" newline bitfld.long 0x30 8. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_8,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_8" "0,1" newline bitfld.long 0x30 7. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_7,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_7" "0,1" newline bitfld.long 0x30 6. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_6,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_6" "0,1" newline bitfld.long 0x30 5. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_5,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_5" "0,1" newline bitfld.long 0x30 4. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_4,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_4" "0,1" newline bitfld.long 0x30 3. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_3,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_3" "0,1" newline bitfld.long 0x30 2. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_2,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_2" "0,1" newline bitfld.long 0x30 1. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_1,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_1" "0,1" newline bitfld.long 0x30 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_0,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_0" "0,1" line.long 0x34 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_dmpac_out_1_6,Status Register 13" bitfld.long 0x34 1. "STATUS_LEVEL_DMPAC_OUT_1_CTM_PULSE,Status write 1 to set for level_dmpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0x34 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_PROT_ERR,Status write 1 to set for level_dmpac_out_1_en_dru_prot_err" "0,1" line.long 0x38 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_dmpac_out_0_0,Status Register 14" bitfld.long 0x38 25. "STATUS_PULSE_DMPAC_OUT_0_FOCO_1_SL2_WR_ERR,Status write 1 to set for pulse_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1" newline bitfld.long 0x38 24. "STATUS_PULSE_DMPAC_OUT_0_FOCO_1_SL2_RD_ERR,Status write 1 to set for pulse_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1" newline bitfld.long 0x38 23. "STATUS_PULSE_DMPAC_OUT_0_FOCO_1_FR_DONE_EVT,Status write 1 to set for pulse_dmpac_out_0_en_foco_1_fr_done_evt" "0,1" newline bitfld.long 0x38 22. "STATUS_PULSE_DMPAC_OUT_0_FOCO_0_SL2_WR_ERR,Status write 1 to set for pulse_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1" newline bitfld.long 0x38 21. "STATUS_PULSE_DMPAC_OUT_0_FOCO_0_SL2_RD_ERR,Status write 1 to set for pulse_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1" newline bitfld.long 0x38 20. "STATUS_PULSE_DMPAC_OUT_0_FOCO_0_FR_DONE_EVT,Status write 1 to set for pulse_dmpac_out_0_en_foco_0_fr_done_evt" "0,1" newline bitfld.long 0x38 19. "STATUS_PULSE_DMPAC_OUT_0_SDE_WRITE_ERROR,Status write 1 to set for pulse_dmpac_out_0_en_sde_write_error" "0,1" newline bitfld.long 0x38 18. "STATUS_PULSE_DMPAC_OUT_0_SDE_READ_ERROR,Status write 1 to set for pulse_dmpac_out_0_en_sde_read_error" "0,1" newline bitfld.long 0x38 17. "STATUS_PULSE_DMPAC_OUT_0_SDE_FRAME_DONE,Status write 1 to set for pulse_dmpac_out_0_en_sde_frame_done" "0,1" newline bitfld.long 0x38 16. "STATUS_PULSE_DMPAC_OUT_0_SDE_BLK_DONE,Status write 1 to set for pulse_dmpac_out_0_en_sde_blk_done" "0,1" newline bitfld.long 0x38 4. "STATUS_PULSE_DMPAC_OUT_0_DOF_MP0_RD_STATUS_ERROR,Status write 1 to set for pulse_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1" newline bitfld.long 0x38 3. "STATUS_PULSE_DMPAC_OUT_0_DOF_WRITE_ERROR,Status write 1 to set for pulse_dmpac_out_0_en_dof_write_error" "0,1" newline bitfld.long 0x38 2. "STATUS_PULSE_DMPAC_OUT_0_DOF_READ_ERROR,Status write 1 to set for pulse_dmpac_out_0_en_dof_read_error" "0,1" newline bitfld.long 0x38 1. "STATUS_PULSE_DMPAC_OUT_0_DOF_FRAME_DONE,Status write 1 to set for pulse_dmpac_out_0_en_dof_frame_done" "0,1" newline bitfld.long 0x38 0. "STATUS_PULSE_DMPAC_OUT_0_DOF_ROW_DONE,Status write 1 to set for pulse_dmpac_out_0_en_dof_row_done" "0,1" line.long 0x3C "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_dmpac_out_0_1,Status Register 15" bitfld.long 0x3C 27. "STATUS_PULSE_DMPAC_OUT_0_TDONE_8,Status write 1 to set for pulse_dmpac_out_0_en_tdone_8" "0,1" newline bitfld.long 0x3C 26. "STATUS_PULSE_DMPAC_OUT_0_TDONE_7,Status write 1 to set for pulse_dmpac_out_0_en_tdone_7" "0,1" newline bitfld.long 0x3C 25. "STATUS_PULSE_DMPAC_OUT_0_TDONE_1,Status write 1 to set for pulse_dmpac_out_0_en_tdone_1" "0,1" newline bitfld.long 0x3C 24. "STATUS_PULSE_DMPAC_OUT_0_TDONE_0,Status write 1 to set for pulse_dmpac_out_0_en_tdone_0" "0,1" newline rbitfld.long 0x3C 19. "STATUS_PULSE_DMPAC_OUT_0_SPARE_PEND_1_L,Status for pulse_dmpac_out_0_en_spare_pend_1_l" "0,1" newline rbitfld.long 0x3C 18. "STATUS_PULSE_DMPAC_OUT_0_SPARE_PEND_1_P,Status for pulse_dmpac_out_0_en_spare_pend_1_p" "0,1" newline rbitfld.long 0x3C 17. "STATUS_PULSE_DMPAC_OUT_0_SPARE_PEND_0_L,Status for pulse_dmpac_out_0_en_spare_pend_0_l" "0,1" newline rbitfld.long 0x3C 16. "STATUS_PULSE_DMPAC_OUT_0_SPARE_PEND_0_P,Status for pulse_dmpac_out_0_en_spare_pend_0_p" "0,1" newline bitfld.long 0x3C 9. "STATUS_PULSE_DMPAC_OUT_0_SPARE_DEC_1,Status write 1 to set for pulse_dmpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0x3C 8. "STATUS_PULSE_DMPAC_OUT_0_SPARE_DEC_0,Status write 1 to set for pulse_dmpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0x3C 3. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_3,Status write 1 to set for pulse_dmpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0x3C 2. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_2,Status write 1 to set for pulse_dmpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0x3C 1. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_1,Status write 1 to set for pulse_dmpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0x3C 0. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_0,Status write 1 to set for pulse_dmpac_out_0_en_pipe_done_0" "0,1" line.long 0x40 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_dmpac_out_0_2,Status Register 16" bitfld.long 0x40 3. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_8,Status write 1 to set for pulse_dmpac_out_0_en_watchdogtimer_err_8" "0,1" newline bitfld.long 0x40 2. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_7,Status write 1 to set for pulse_dmpac_out_0_en_watchdogtimer_err_7" "0,1" newline bitfld.long 0x40 1. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_1,Status write 1 to set for pulse_dmpac_out_0_en_watchdogtimer_err_1" "0,1" newline bitfld.long 0x40 0. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_dmpac_out_0_en_watchdogtimer_err_0" "0,1" line.long 0x44 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_dmpac_out_0_3,Status Register 17" bitfld.long 0x44 31. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_31,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_31" "0,1" newline bitfld.long 0x44 30. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_30,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_30" "0,1" newline bitfld.long 0x44 29. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_29,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_29" "0,1" newline bitfld.long 0x44 28. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_28,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_28" "0,1" newline bitfld.long 0x44 27. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_27,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_27" "0,1" newline bitfld.long 0x44 26. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_26,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_26" "0,1" newline bitfld.long 0x44 25. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_25,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_25" "0,1" newline bitfld.long 0x44 24. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_24,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_24" "0,1" newline bitfld.long 0x44 23. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_23,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_23" "0,1" newline bitfld.long 0x44 22. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_22,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_22" "0,1" newline bitfld.long 0x44 21. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_21,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_21" "0,1" newline bitfld.long 0x44 20. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_20,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_20" "0,1" newline bitfld.long 0x44 19. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_19,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_19" "0,1" newline bitfld.long 0x44 18. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_18,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_18" "0,1" newline bitfld.long 0x44 17. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_17,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_17" "0,1" newline bitfld.long 0x44 16. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_16,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_16" "0,1" newline bitfld.long 0x44 15. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_15,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_15" "0,1" newline bitfld.long 0x44 14. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_14,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_14" "0,1" newline bitfld.long 0x44 13. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_13,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_13" "0,1" newline bitfld.long 0x44 12. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_12,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_12" "0,1" newline bitfld.long 0x44 11. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_11,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_11" "0,1" newline bitfld.long 0x44 10. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_10,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_10" "0,1" newline bitfld.long 0x44 9. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_9,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_9" "0,1" newline bitfld.long 0x44 8. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_8,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_8" "0,1" newline bitfld.long 0x44 7. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_7,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_7" "0,1" newline bitfld.long 0x44 6. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_6,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_6" "0,1" newline bitfld.long 0x44 5. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_5,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_5" "0,1" newline bitfld.long 0x44 4. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_4,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_4" "0,1" newline bitfld.long 0x44 3. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_3,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_3" "0,1" newline bitfld.long 0x44 2. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_2,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_2" "0,1" newline bitfld.long 0x44 1. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_1,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_1" "0,1" newline bitfld.long 0x44 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_0,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_0" "0,1" line.long 0x48 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_dmpac_out_0_4,Status Register 18" bitfld.long 0x48 31. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_31,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_31" "0,1" newline bitfld.long 0x48 30. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_30,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_30" "0,1" newline bitfld.long 0x48 29. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_29,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_29" "0,1" newline bitfld.long 0x48 28. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_28,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_28" "0,1" newline bitfld.long 0x48 27. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_27,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_27" "0,1" newline bitfld.long 0x48 26. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_26,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_26" "0,1" newline bitfld.long 0x48 25. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_25,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_25" "0,1" newline bitfld.long 0x48 24. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_24,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_24" "0,1" newline bitfld.long 0x48 23. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_23,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_23" "0,1" newline bitfld.long 0x48 22. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_22,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_22" "0,1" newline bitfld.long 0x48 21. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_21,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_21" "0,1" newline bitfld.long 0x48 20. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_20,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_20" "0,1" newline bitfld.long 0x48 19. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_19,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_19" "0,1" newline bitfld.long 0x48 18. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_18,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_18" "0,1" newline bitfld.long 0x48 17. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_17,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_17" "0,1" newline bitfld.long 0x48 16. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_16,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_16" "0,1" newline bitfld.long 0x48 15. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_15,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_15" "0,1" newline bitfld.long 0x48 14. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_14,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_14" "0,1" newline bitfld.long 0x48 13. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_13,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_13" "0,1" newline bitfld.long 0x48 12. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_12,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_12" "0,1" newline bitfld.long 0x48 11. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_11,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_11" "0,1" newline bitfld.long 0x48 10. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_10,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_10" "0,1" newline bitfld.long 0x48 9. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_9,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_9" "0,1" newline bitfld.long 0x48 8. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_8,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_8" "0,1" newline bitfld.long 0x48 7. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_7,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_7" "0,1" newline bitfld.long 0x48 6. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_6,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_6" "0,1" newline bitfld.long 0x48 5. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_5,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_5" "0,1" newline bitfld.long 0x48 4. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_4,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_4" "0,1" newline bitfld.long 0x48 3. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_3,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_3" "0,1" newline bitfld.long 0x48 2. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_2,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_2" "0,1" newline bitfld.long 0x48 1. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_1,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_1" "0,1" newline bitfld.long 0x48 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_0,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_0" "0,1" line.long 0x4C "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_dmpac_out_0_5,Status Register 19" bitfld.long 0x4C 31. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_31,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_31" "0,1" newline bitfld.long 0x4C 30. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_30,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_30" "0,1" newline bitfld.long 0x4C 29. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_29,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_29" "0,1" newline bitfld.long 0x4C 28. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_28,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_28" "0,1" newline bitfld.long 0x4C 27. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_27,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_27" "0,1" newline bitfld.long 0x4C 26. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_26,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_26" "0,1" newline bitfld.long 0x4C 25. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_25,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_25" "0,1" newline bitfld.long 0x4C 24. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_24,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_24" "0,1" newline bitfld.long 0x4C 23. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_23,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_23" "0,1" newline bitfld.long 0x4C 22. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_22,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_22" "0,1" newline bitfld.long 0x4C 21. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_21,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_21" "0,1" newline bitfld.long 0x4C 20. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_20,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_20" "0,1" newline bitfld.long 0x4C 19. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_19,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_19" "0,1" newline bitfld.long 0x4C 18. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_18,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_18" "0,1" newline bitfld.long 0x4C 17. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_17,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_17" "0,1" newline bitfld.long 0x4C 16. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_16,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_16" "0,1" newline bitfld.long 0x4C 15. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_15,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_15" "0,1" newline bitfld.long 0x4C 14. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_14,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_14" "0,1" newline bitfld.long 0x4C 13. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_13,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_13" "0,1" newline bitfld.long 0x4C 12. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_12,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_12" "0,1" newline bitfld.long 0x4C 11. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_11,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_11" "0,1" newline bitfld.long 0x4C 10. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_10,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_10" "0,1" newline bitfld.long 0x4C 9. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_9,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_9" "0,1" newline bitfld.long 0x4C 8. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_8,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_8" "0,1" newline bitfld.long 0x4C 7. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_7,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_7" "0,1" newline bitfld.long 0x4C 6. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_6,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_6" "0,1" newline bitfld.long 0x4C 5. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_5,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_5" "0,1" newline bitfld.long 0x4C 4. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_4,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_4" "0,1" newline bitfld.long 0x4C 3. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_3,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_3" "0,1" newline bitfld.long 0x4C 2. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_2,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_2" "0,1" newline bitfld.long 0x4C 1. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_1,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_1" "0,1" newline bitfld.long 0x4C 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_0,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_0" "0,1" line.long 0x50 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_dmpac_out_0_6,Status Register 20" bitfld.long 0x50 1. "STATUS_PULSE_DMPAC_OUT_0_CTM_PULSE,Status write 1 to set for pulse_dmpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0x50 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_PROT_ERR,Status write 1 to set for pulse_dmpac_out_0_en_dru_prot_err" "0,1" line.long 0x54 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_dmpac_out_1_0,Status Register 21" bitfld.long 0x54 25. "STATUS_PULSE_DMPAC_OUT_1_FOCO_1_SL2_WR_ERR,Status write 1 to set for pulse_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1" newline bitfld.long 0x54 24. "STATUS_PULSE_DMPAC_OUT_1_FOCO_1_SL2_RD_ERR,Status write 1 to set for pulse_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1" newline bitfld.long 0x54 23. "STATUS_PULSE_DMPAC_OUT_1_FOCO_1_FR_DONE_EVT,Status write 1 to set for pulse_dmpac_out_1_en_foco_1_fr_done_evt" "0,1" newline bitfld.long 0x54 22. "STATUS_PULSE_DMPAC_OUT_1_FOCO_0_SL2_WR_ERR,Status write 1 to set for pulse_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1" newline bitfld.long 0x54 21. "STATUS_PULSE_DMPAC_OUT_1_FOCO_0_SL2_RD_ERR,Status write 1 to set for pulse_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1" newline bitfld.long 0x54 20. "STATUS_PULSE_DMPAC_OUT_1_FOCO_0_FR_DONE_EVT,Status write 1 to set for pulse_dmpac_out_1_en_foco_0_fr_done_evt" "0,1" newline bitfld.long 0x54 19. "STATUS_PULSE_DMPAC_OUT_1_SDE_WRITE_ERROR,Status write 1 to set for pulse_dmpac_out_1_en_sde_write_error" "0,1" newline bitfld.long 0x54 18. "STATUS_PULSE_DMPAC_OUT_1_SDE_READ_ERROR,Status write 1 to set for pulse_dmpac_out_1_en_sde_read_error" "0,1" newline bitfld.long 0x54 17. "STATUS_PULSE_DMPAC_OUT_1_SDE_FRAME_DONE,Status write 1 to set for pulse_dmpac_out_1_en_sde_frame_done" "0,1" newline bitfld.long 0x54 16. "STATUS_PULSE_DMPAC_OUT_1_SDE_BLK_DONE,Status write 1 to set for pulse_dmpac_out_1_en_sde_blk_done" "0,1" newline bitfld.long 0x54 4. "STATUS_PULSE_DMPAC_OUT_1_DOF_MP0_RD_STATUS_ERROR,Status write 1 to set for pulse_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1" newline bitfld.long 0x54 3. "STATUS_PULSE_DMPAC_OUT_1_DOF_WRITE_ERROR,Status write 1 to set for pulse_dmpac_out_1_en_dof_write_error" "0,1" newline bitfld.long 0x54 2. "STATUS_PULSE_DMPAC_OUT_1_DOF_READ_ERROR,Status write 1 to set for pulse_dmpac_out_1_en_dof_read_error" "0,1" newline bitfld.long 0x54 1. "STATUS_PULSE_DMPAC_OUT_1_DOF_FRAME_DONE,Status write 1 to set for pulse_dmpac_out_1_en_dof_frame_done" "0,1" newline bitfld.long 0x54 0. "STATUS_PULSE_DMPAC_OUT_1_DOF_ROW_DONE,Status write 1 to set for pulse_dmpac_out_1_en_dof_row_done" "0,1" line.long 0x58 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_dmpac_out_1_1,Status Register 22" bitfld.long 0x58 27. "STATUS_PULSE_DMPAC_OUT_1_TDONE_8,Status write 1 to set for pulse_dmpac_out_1_en_tdone_8" "0,1" newline bitfld.long 0x58 26. "STATUS_PULSE_DMPAC_OUT_1_TDONE_7,Status write 1 to set for pulse_dmpac_out_1_en_tdone_7" "0,1" newline bitfld.long 0x58 25. "STATUS_PULSE_DMPAC_OUT_1_TDONE_1,Status write 1 to set for pulse_dmpac_out_1_en_tdone_1" "0,1" newline bitfld.long 0x58 24. "STATUS_PULSE_DMPAC_OUT_1_TDONE_0,Status write 1 to set for pulse_dmpac_out_1_en_tdone_0" "0,1" newline rbitfld.long 0x58 19. "STATUS_PULSE_DMPAC_OUT_1_SPARE_PEND_1_L,Status for pulse_dmpac_out_1_en_spare_pend_1_l" "0,1" newline rbitfld.long 0x58 18. "STATUS_PULSE_DMPAC_OUT_1_SPARE_PEND_1_P,Status for pulse_dmpac_out_1_en_spare_pend_1_p" "0,1" newline rbitfld.long 0x58 17. "STATUS_PULSE_DMPAC_OUT_1_SPARE_PEND_0_L,Status for pulse_dmpac_out_1_en_spare_pend_0_l" "0,1" newline rbitfld.long 0x58 16. "STATUS_PULSE_DMPAC_OUT_1_SPARE_PEND_0_P,Status for pulse_dmpac_out_1_en_spare_pend_0_p" "0,1" newline bitfld.long 0x58 9. "STATUS_PULSE_DMPAC_OUT_1_SPARE_DEC_1,Status write 1 to set for pulse_dmpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0x58 8. "STATUS_PULSE_DMPAC_OUT_1_SPARE_DEC_0,Status write 1 to set for pulse_dmpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0x58 3. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_3,Status write 1 to set for pulse_dmpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0x58 2. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_2,Status write 1 to set for pulse_dmpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0x58 1. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_1,Status write 1 to set for pulse_dmpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0x58 0. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_0,Status write 1 to set for pulse_dmpac_out_1_en_pipe_done_0" "0,1" line.long 0x5C "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_dmpac_out_1_2,Status Register 23" bitfld.long 0x5C 3. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_8,Status write 1 to set for pulse_dmpac_out_1_en_watchdogtimer_err_8" "0,1" newline bitfld.long 0x5C 2. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_7,Status write 1 to set for pulse_dmpac_out_1_en_watchdogtimer_err_7" "0,1" newline bitfld.long 0x5C 1. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_1,Status write 1 to set for pulse_dmpac_out_1_en_watchdogtimer_err_1" "0,1" newline bitfld.long 0x5C 0. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_dmpac_out_1_en_watchdogtimer_err_0" "0,1" line.long 0x60 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_dmpac_out_1_3,Status Register 24" bitfld.long 0x60 31. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_31,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_31" "0,1" newline bitfld.long 0x60 30. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_30,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_30" "0,1" newline bitfld.long 0x60 29. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_29,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_29" "0,1" newline bitfld.long 0x60 28. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_28,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_28" "0,1" newline bitfld.long 0x60 27. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_27,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_27" "0,1" newline bitfld.long 0x60 26. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_26,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_26" "0,1" newline bitfld.long 0x60 25. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_25,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_25" "0,1" newline bitfld.long 0x60 24. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_24,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_24" "0,1" newline bitfld.long 0x60 23. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_23,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_23" "0,1" newline bitfld.long 0x60 22. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_22,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_22" "0,1" newline bitfld.long 0x60 21. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_21,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_21" "0,1" newline bitfld.long 0x60 20. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_20,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_20" "0,1" newline bitfld.long 0x60 19. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_19,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_19" "0,1" newline bitfld.long 0x60 18. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_18,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_18" "0,1" newline bitfld.long 0x60 17. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_17,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_17" "0,1" newline bitfld.long 0x60 16. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_16,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_16" "0,1" newline bitfld.long 0x60 15. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_15,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_15" "0,1" newline bitfld.long 0x60 14. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_14,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_14" "0,1" newline bitfld.long 0x60 13. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_13,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_13" "0,1" newline bitfld.long 0x60 12. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_12,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_12" "0,1" newline bitfld.long 0x60 11. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_11,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_11" "0,1" newline bitfld.long 0x60 10. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_10,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_10" "0,1" newline bitfld.long 0x60 9. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_9,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_9" "0,1" newline bitfld.long 0x60 8. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_8,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_8" "0,1" newline bitfld.long 0x60 7. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_7,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_7" "0,1" newline bitfld.long 0x60 6. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_6,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_6" "0,1" newline bitfld.long 0x60 5. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_5,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_5" "0,1" newline bitfld.long 0x60 4. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_4,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_4" "0,1" newline bitfld.long 0x60 3. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_3,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_3" "0,1" newline bitfld.long 0x60 2. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_2,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_2" "0,1" newline bitfld.long 0x60 1. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_1,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_1" "0,1" newline bitfld.long 0x60 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_0,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_0" "0,1" line.long 0x64 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_dmpac_out_1_4,Status Register 25" bitfld.long 0x64 31. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_31,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_31" "0,1" newline bitfld.long 0x64 30. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_30,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_30" "0,1" newline bitfld.long 0x64 29. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_29,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_29" "0,1" newline bitfld.long 0x64 28. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_28,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_28" "0,1" newline bitfld.long 0x64 27. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_27,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_27" "0,1" newline bitfld.long 0x64 26. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_26,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_26" "0,1" newline bitfld.long 0x64 25. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_25,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_25" "0,1" newline bitfld.long 0x64 24. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_24,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_24" "0,1" newline bitfld.long 0x64 23. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_23,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_23" "0,1" newline bitfld.long 0x64 22. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_22,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_22" "0,1" newline bitfld.long 0x64 21. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_21,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_21" "0,1" newline bitfld.long 0x64 20. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_20,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_20" "0,1" newline bitfld.long 0x64 19. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_19,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_19" "0,1" newline bitfld.long 0x64 18. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_18,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_18" "0,1" newline bitfld.long 0x64 17. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_17,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_17" "0,1" newline bitfld.long 0x64 16. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_16,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_16" "0,1" newline bitfld.long 0x64 15. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_15,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_15" "0,1" newline bitfld.long 0x64 14. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_14,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_14" "0,1" newline bitfld.long 0x64 13. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_13,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_13" "0,1" newline bitfld.long 0x64 12. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_12,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_12" "0,1" newline bitfld.long 0x64 11. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_11,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_11" "0,1" newline bitfld.long 0x64 10. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_10,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_10" "0,1" newline bitfld.long 0x64 9. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_9,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_9" "0,1" newline bitfld.long 0x64 8. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_8,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_8" "0,1" newline bitfld.long 0x64 7. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_7,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_7" "0,1" newline bitfld.long 0x64 6. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_6,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_6" "0,1" newline bitfld.long 0x64 5. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_5,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_5" "0,1" newline bitfld.long 0x64 4. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_4,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_4" "0,1" newline bitfld.long 0x64 3. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_3,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_3" "0,1" newline bitfld.long 0x64 2. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_2,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_2" "0,1" newline bitfld.long 0x64 1. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_1,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_1" "0,1" newline bitfld.long 0x64 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_0,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_0" "0,1" line.long 0x68 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_dmpac_out_1_5,Status Register 26" bitfld.long 0x68 31. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_31,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_31" "0,1" newline bitfld.long 0x68 30. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_30,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_30" "0,1" newline bitfld.long 0x68 29. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_29,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_29" "0,1" newline bitfld.long 0x68 28. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_28,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_28" "0,1" newline bitfld.long 0x68 27. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_27,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_27" "0,1" newline bitfld.long 0x68 26. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_26,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_26" "0,1" newline bitfld.long 0x68 25. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_25,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_25" "0,1" newline bitfld.long 0x68 24. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_24,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_24" "0,1" newline bitfld.long 0x68 23. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_23,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_23" "0,1" newline bitfld.long 0x68 22. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_22,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_22" "0,1" newline bitfld.long 0x68 21. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_21,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_21" "0,1" newline bitfld.long 0x68 20. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_20,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_20" "0,1" newline bitfld.long 0x68 19. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_19,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_19" "0,1" newline bitfld.long 0x68 18. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_18,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_18" "0,1" newline bitfld.long 0x68 17. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_17,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_17" "0,1" newline bitfld.long 0x68 16. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_16,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_16" "0,1" newline bitfld.long 0x68 15. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_15,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_15" "0,1" newline bitfld.long 0x68 14. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_14,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_14" "0,1" newline bitfld.long 0x68 13. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_13,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_13" "0,1" newline bitfld.long 0x68 12. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_12,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_12" "0,1" newline bitfld.long 0x68 11. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_11,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_11" "0,1" newline bitfld.long 0x68 10. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_10,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_10" "0,1" newline bitfld.long 0x68 9. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_9,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_9" "0,1" newline bitfld.long 0x68 8. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_8,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_8" "0,1" newline bitfld.long 0x68 7. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_7,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_7" "0,1" newline bitfld.long 0x68 6. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_6,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_6" "0,1" newline bitfld.long 0x68 5. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_5,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_5" "0,1" newline bitfld.long 0x68 4. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_4,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_4" "0,1" newline bitfld.long 0x68 3. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_3,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_3" "0,1" newline bitfld.long 0x68 2. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_2,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_2" "0,1" newline bitfld.long 0x68 1. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_1,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_1" "0,1" newline bitfld.long 0x68 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_0,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_0" "0,1" line.long 0x6C "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_dmpac_out_1_6,Status Register 27" bitfld.long 0x6C 1. "STATUS_PULSE_DMPAC_OUT_1_CTM_PULSE,Status write 1 to set for pulse_dmpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0x6C 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_PROT_ERR,Status write 1 to set for pulse_dmpac_out_1_en_dru_prot_err" "0,1" rgroup.long 0x700++0x6F line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_dmpac_out_0_0,Status Clear Register 0" bitfld.long 0x0 25. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_1_SL2_WR_ERR_CLR,Status write 1 to clear for level_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1" newline bitfld.long 0x0 24. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_1_SL2_RD_ERR_CLR,Status write 1 to clear for level_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1" newline bitfld.long 0x0 23. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_1_FR_DONE_EVT_CLR,Status write 1 to clear for level_dmpac_out_0_en_foco_1_fr_done_evt" "0,1" newline bitfld.long 0x0 22. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_0_SL2_WR_ERR_CLR,Status write 1 to clear for level_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1" newline bitfld.long 0x0 21. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_0_SL2_RD_ERR_CLR,Status write 1 to clear for level_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1" newline bitfld.long 0x0 20. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_0_FR_DONE_EVT_CLR,Status write 1 to clear for level_dmpac_out_0_en_foco_0_fr_done_evt" "0,1" newline bitfld.long 0x0 19. "STATUS_LEVEL_DMPAC_OUT_0_SDE_WRITE_ERROR_CLR,Status write 1 to clear for level_dmpac_out_0_en_sde_write_error" "0,1" newline bitfld.long 0x0 18. "STATUS_LEVEL_DMPAC_OUT_0_SDE_READ_ERROR_CLR,Status write 1 to clear for level_dmpac_out_0_en_sde_read_error" "0,1" newline bitfld.long 0x0 17. "STATUS_LEVEL_DMPAC_OUT_0_SDE_FRAME_DONE_CLR,Status write 1 to clear for level_dmpac_out_0_en_sde_frame_done" "0,1" newline bitfld.long 0x0 16. "STATUS_LEVEL_DMPAC_OUT_0_SDE_BLK_DONE_CLR,Status write 1 to clear for level_dmpac_out_0_en_sde_blk_done" "0,1" newline bitfld.long 0x0 4. "STATUS_LEVEL_DMPAC_OUT_0_DOF_MP0_RD_STATUS_ERROR_CLR,Status write 1 to clear for level_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1" newline bitfld.long 0x0 3. "STATUS_LEVEL_DMPAC_OUT_0_DOF_WRITE_ERROR_CLR,Status write 1 to clear for level_dmpac_out_0_en_dof_write_error" "0,1" newline bitfld.long 0x0 2. "STATUS_LEVEL_DMPAC_OUT_0_DOF_READ_ERROR_CLR,Status write 1 to clear for level_dmpac_out_0_en_dof_read_error" "0,1" newline bitfld.long 0x0 1. "STATUS_LEVEL_DMPAC_OUT_0_DOF_FRAME_DONE_CLR,Status write 1 to clear for level_dmpac_out_0_en_dof_frame_done" "0,1" newline bitfld.long 0x0 0. "STATUS_LEVEL_DMPAC_OUT_0_DOF_ROW_DONE_CLR,Status write 1 to clear for level_dmpac_out_0_en_dof_row_done" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_dmpac_out_0_1,Status Clear Register 1" bitfld.long 0x4 27. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_8_CLR,Status write 1 to clear for level_dmpac_out_0_en_tdone_8" "0,1" newline bitfld.long 0x4 26. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_7_CLR,Status write 1 to clear for level_dmpac_out_0_en_tdone_7" "0,1" newline bitfld.long 0x4 25. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_1_CLR,Status write 1 to clear for level_dmpac_out_0_en_tdone_1" "0,1" newline bitfld.long 0x4 24. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_0_CLR,Status write 1 to clear for level_dmpac_out_0_en_tdone_0" "0,1" newline bitfld.long 0x4 9. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_DEC_1_CLR,Status write 1 to clear for level_dmpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0x4 8. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_DEC_0_CLR,Status write 1 to clear for level_dmpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0x4 3. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_3_CLR,Status write 1 to clear for level_dmpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0x4 2. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_2_CLR,Status write 1 to clear for level_dmpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0x4 1. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_1_CLR,Status write 1 to clear for level_dmpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0x4 0. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_0_CLR,Status write 1 to clear for level_dmpac_out_0_en_pipe_done_0" "0,1" line.long 0x8 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_dmpac_out_0_2,Status Clear Register 2" bitfld.long 0x8 3. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_8_CLR,Status write 1 to clear for level_dmpac_out_0_en_watchdogtimer_err_8" "0,1" newline bitfld.long 0x8 2. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_7_CLR,Status write 1 to clear for level_dmpac_out_0_en_watchdogtimer_err_7" "0,1" newline bitfld.long 0x8 1. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_1_CLR,Status write 1 to clear for level_dmpac_out_0_en_watchdogtimer_err_1" "0,1" newline bitfld.long 0x8 0. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_dmpac_out_0_en_watchdogtimer_err_0" "0,1" line.long 0xC "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_dmpac_out_0_3,Status Clear Register 3" bitfld.long 0xC 31. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_31_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_31" "0,1" newline bitfld.long 0xC 30. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_30_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_30" "0,1" newline bitfld.long 0xC 29. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_29_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_29" "0,1" newline bitfld.long 0xC 28. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_28_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_28" "0,1" newline bitfld.long 0xC 27. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_27_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_27" "0,1" newline bitfld.long 0xC 26. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_26_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_26" "0,1" newline bitfld.long 0xC 25. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_25_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_25" "0,1" newline bitfld.long 0xC 24. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_24_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_24" "0,1" newline bitfld.long 0xC 23. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_23_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_23" "0,1" newline bitfld.long 0xC 22. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_22_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_22" "0,1" newline bitfld.long 0xC 21. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_21_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_21" "0,1" newline bitfld.long 0xC 20. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_20_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_20" "0,1" newline bitfld.long 0xC 19. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_19_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_19" "0,1" newline bitfld.long 0xC 18. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_18_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_18" "0,1" newline bitfld.long 0xC 17. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_17_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_17" "0,1" newline bitfld.long 0xC 16. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_16_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_16" "0,1" newline bitfld.long 0xC 15. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_15_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_15" "0,1" newline bitfld.long 0xC 14. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_14_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_14" "0,1" newline bitfld.long 0xC 13. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_13_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_13" "0,1" newline bitfld.long 0xC 12. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_12_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_12" "0,1" newline bitfld.long 0xC 11. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_11_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_11" "0,1" newline bitfld.long 0xC 10. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_10_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_10" "0,1" newline bitfld.long 0xC 9. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_9_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_9" "0,1" newline bitfld.long 0xC 8. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_8_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_8" "0,1" newline bitfld.long 0xC 7. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_7_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_7" "0,1" newline bitfld.long 0xC 6. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_6_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_6" "0,1" newline bitfld.long 0xC 5. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_5_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_5" "0,1" newline bitfld.long 0xC 4. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_4_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_4" "0,1" newline bitfld.long 0xC 3. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_3_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_3" "0,1" newline bitfld.long 0xC 2. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_2_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_2" "0,1" newline bitfld.long 0xC 1. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_1_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_1" "0,1" newline bitfld.long 0xC 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_0_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_0" "0,1" line.long 0x10 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_dmpac_out_0_4,Status Clear Register 4" bitfld.long 0x10 31. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_31_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_31" "0,1" newline bitfld.long 0x10 30. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_30_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_30" "0,1" newline bitfld.long 0x10 29. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_29_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_29" "0,1" newline bitfld.long 0x10 28. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_28_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_28" "0,1" newline bitfld.long 0x10 27. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_27_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_27" "0,1" newline bitfld.long 0x10 26. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_26_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_26" "0,1" newline bitfld.long 0x10 25. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_25_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_25" "0,1" newline bitfld.long 0x10 24. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_24_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_24" "0,1" newline bitfld.long 0x10 23. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_23_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_23" "0,1" newline bitfld.long 0x10 22. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_22_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_22" "0,1" newline bitfld.long 0x10 21. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_21_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_21" "0,1" newline bitfld.long 0x10 20. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_20_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_20" "0,1" newline bitfld.long 0x10 19. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_19_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_19" "0,1" newline bitfld.long 0x10 18. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_18_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_18" "0,1" newline bitfld.long 0x10 17. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_17_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_17" "0,1" newline bitfld.long 0x10 16. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_16_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_16" "0,1" newline bitfld.long 0x10 15. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_15_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_15" "0,1" newline bitfld.long 0x10 14. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_14_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_14" "0,1" newline bitfld.long 0x10 13. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_13_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_13" "0,1" newline bitfld.long 0x10 12. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_12_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_12" "0,1" newline bitfld.long 0x10 11. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_11_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_11" "0,1" newline bitfld.long 0x10 10. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_10_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_10" "0,1" newline bitfld.long 0x10 9. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_9_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_9" "0,1" newline bitfld.long 0x10 8. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_8_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_8" "0,1" newline bitfld.long 0x10 7. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_7_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_7" "0,1" newline bitfld.long 0x10 6. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_6_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_6" "0,1" newline bitfld.long 0x10 5. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_5_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_5" "0,1" newline bitfld.long 0x10 4. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_4_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_4" "0,1" newline bitfld.long 0x10 3. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_3_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_3" "0,1" newline bitfld.long 0x10 2. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_2_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_2" "0,1" newline bitfld.long 0x10 1. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_1_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_1" "0,1" newline bitfld.long 0x10 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_0_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_0" "0,1" line.long 0x14 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_dmpac_out_0_5,Status Clear Register 5" bitfld.long 0x14 31. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_31_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_31" "0,1" newline bitfld.long 0x14 30. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_30_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_30" "0,1" newline bitfld.long 0x14 29. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_29_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_29" "0,1" newline bitfld.long 0x14 28. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_28_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_28" "0,1" newline bitfld.long 0x14 27. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_27_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_27" "0,1" newline bitfld.long 0x14 26. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_26_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_26" "0,1" newline bitfld.long 0x14 25. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_25_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_25" "0,1" newline bitfld.long 0x14 24. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_24_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_24" "0,1" newline bitfld.long 0x14 23. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_23_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_23" "0,1" newline bitfld.long 0x14 22. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_22_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_22" "0,1" newline bitfld.long 0x14 21. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_21_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_21" "0,1" newline bitfld.long 0x14 20. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_20_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_20" "0,1" newline bitfld.long 0x14 19. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_19_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_19" "0,1" newline bitfld.long 0x14 18. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_18_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_18" "0,1" newline bitfld.long 0x14 17. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_17_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_17" "0,1" newline bitfld.long 0x14 16. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_16_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_16" "0,1" newline bitfld.long 0x14 15. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_15_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_15" "0,1" newline bitfld.long 0x14 14. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_14_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_14" "0,1" newline bitfld.long 0x14 13. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_13_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_13" "0,1" newline bitfld.long 0x14 12. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_12_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_12" "0,1" newline bitfld.long 0x14 11. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_11_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_11" "0,1" newline bitfld.long 0x14 10. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_10_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_10" "0,1" newline bitfld.long 0x14 9. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_9_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_9" "0,1" newline bitfld.long 0x14 8. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_8_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_8" "0,1" newline bitfld.long 0x14 7. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_7_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_7" "0,1" newline bitfld.long 0x14 6. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_6_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_6" "0,1" newline bitfld.long 0x14 5. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_5_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_5" "0,1" newline bitfld.long 0x14 4. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_4_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_4" "0,1" newline bitfld.long 0x14 3. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_3_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_3" "0,1" newline bitfld.long 0x14 2. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_2_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_2" "0,1" newline bitfld.long 0x14 1. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_1_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_1" "0,1" newline bitfld.long 0x14 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_0_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_0" "0,1" line.long 0x18 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_dmpac_out_0_6,Status Clear Register 6" bitfld.long 0x18 1. "STATUS_LEVEL_DMPAC_OUT_0_CTM_PULSE_CLR,Status write 1 to clear for level_dmpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0x18 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_PROT_ERR_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_prot_err" "0,1" line.long 0x1C "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_dmpac_out_1_0,Status Clear Register 7" bitfld.long 0x1C 25. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_1_SL2_WR_ERR_CLR,Status write 1 to clear for level_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1" newline bitfld.long 0x1C 24. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_1_SL2_RD_ERR_CLR,Status write 1 to clear for level_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1" newline bitfld.long 0x1C 23. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_1_FR_DONE_EVT_CLR,Status write 1 to clear for level_dmpac_out_1_en_foco_1_fr_done_evt" "0,1" newline bitfld.long 0x1C 22. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_0_SL2_WR_ERR_CLR,Status write 1 to clear for level_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1" newline bitfld.long 0x1C 21. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_0_SL2_RD_ERR_CLR,Status write 1 to clear for level_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1" newline bitfld.long 0x1C 20. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_0_FR_DONE_EVT_CLR,Status write 1 to clear for level_dmpac_out_1_en_foco_0_fr_done_evt" "0,1" newline bitfld.long 0x1C 19. "STATUS_LEVEL_DMPAC_OUT_1_SDE_WRITE_ERROR_CLR,Status write 1 to clear for level_dmpac_out_1_en_sde_write_error" "0,1" newline bitfld.long 0x1C 18. "STATUS_LEVEL_DMPAC_OUT_1_SDE_READ_ERROR_CLR,Status write 1 to clear for level_dmpac_out_1_en_sde_read_error" "0,1" newline bitfld.long 0x1C 17. "STATUS_LEVEL_DMPAC_OUT_1_SDE_FRAME_DONE_CLR,Status write 1 to clear for level_dmpac_out_1_en_sde_frame_done" "0,1" newline bitfld.long 0x1C 16. "STATUS_LEVEL_DMPAC_OUT_1_SDE_BLK_DONE_CLR,Status write 1 to clear for level_dmpac_out_1_en_sde_blk_done" "0,1" newline bitfld.long 0x1C 4. "STATUS_LEVEL_DMPAC_OUT_1_DOF_MP0_RD_STATUS_ERROR_CLR,Status write 1 to clear for level_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1" newline bitfld.long 0x1C 3. "STATUS_LEVEL_DMPAC_OUT_1_DOF_WRITE_ERROR_CLR,Status write 1 to clear for level_dmpac_out_1_en_dof_write_error" "0,1" newline bitfld.long 0x1C 2. "STATUS_LEVEL_DMPAC_OUT_1_DOF_READ_ERROR_CLR,Status write 1 to clear for level_dmpac_out_1_en_dof_read_error" "0,1" newline bitfld.long 0x1C 1. "STATUS_LEVEL_DMPAC_OUT_1_DOF_FRAME_DONE_CLR,Status write 1 to clear for level_dmpac_out_1_en_dof_frame_done" "0,1" newline bitfld.long 0x1C 0. "STATUS_LEVEL_DMPAC_OUT_1_DOF_ROW_DONE_CLR,Status write 1 to clear for level_dmpac_out_1_en_dof_row_done" "0,1" line.long 0x20 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_dmpac_out_1_1,Status Clear Register 8" bitfld.long 0x20 27. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_8_CLR,Status write 1 to clear for level_dmpac_out_1_en_tdone_8" "0,1" newline bitfld.long 0x20 26. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_7_CLR,Status write 1 to clear for level_dmpac_out_1_en_tdone_7" "0,1" newline bitfld.long 0x20 25. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_1_CLR,Status write 1 to clear for level_dmpac_out_1_en_tdone_1" "0,1" newline bitfld.long 0x20 24. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_0_CLR,Status write 1 to clear for level_dmpac_out_1_en_tdone_0" "0,1" newline bitfld.long 0x20 9. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_DEC_1_CLR,Status write 1 to clear for level_dmpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0x20 8. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_DEC_0_CLR,Status write 1 to clear for level_dmpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0x20 3. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_3_CLR,Status write 1 to clear for level_dmpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0x20 2. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_2_CLR,Status write 1 to clear for level_dmpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0x20 1. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_1_CLR,Status write 1 to clear for level_dmpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0x20 0. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_0_CLR,Status write 1 to clear for level_dmpac_out_1_en_pipe_done_0" "0,1" line.long 0x24 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_dmpac_out_1_2,Status Clear Register 9" bitfld.long 0x24 3. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_8_CLR,Status write 1 to clear for level_dmpac_out_1_en_watchdogtimer_err_8" "0,1" newline bitfld.long 0x24 2. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_7_CLR,Status write 1 to clear for level_dmpac_out_1_en_watchdogtimer_err_7" "0,1" newline bitfld.long 0x24 1. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_1_CLR,Status write 1 to clear for level_dmpac_out_1_en_watchdogtimer_err_1" "0,1" newline bitfld.long 0x24 0. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_dmpac_out_1_en_watchdogtimer_err_0" "0,1" line.long 0x28 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_dmpac_out_1_3,Status Clear Register 10" bitfld.long 0x28 31. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_31_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_31" "0,1" newline bitfld.long 0x28 30. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_30_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_30" "0,1" newline bitfld.long 0x28 29. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_29_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_29" "0,1" newline bitfld.long 0x28 28. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_28_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_28" "0,1" newline bitfld.long 0x28 27. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_27_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_27" "0,1" newline bitfld.long 0x28 26. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_26_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_26" "0,1" newline bitfld.long 0x28 25. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_25_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_25" "0,1" newline bitfld.long 0x28 24. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_24_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_24" "0,1" newline bitfld.long 0x28 23. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_23_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_23" "0,1" newline bitfld.long 0x28 22. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_22_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_22" "0,1" newline bitfld.long 0x28 21. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_21_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_21" "0,1" newline bitfld.long 0x28 20. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_20_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_20" "0,1" newline bitfld.long 0x28 19. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_19_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_19" "0,1" newline bitfld.long 0x28 18. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_18_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_18" "0,1" newline bitfld.long 0x28 17. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_17_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_17" "0,1" newline bitfld.long 0x28 16. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_16_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_16" "0,1" newline bitfld.long 0x28 15. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_15_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_15" "0,1" newline bitfld.long 0x28 14. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_14_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_14" "0,1" newline bitfld.long 0x28 13. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_13_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_13" "0,1" newline bitfld.long 0x28 12. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_12_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_12" "0,1" newline bitfld.long 0x28 11. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_11_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_11" "0,1" newline bitfld.long 0x28 10. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_10_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_10" "0,1" newline bitfld.long 0x28 9. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_9_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_9" "0,1" newline bitfld.long 0x28 8. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_8_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_8" "0,1" newline bitfld.long 0x28 7. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_7_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_7" "0,1" newline bitfld.long 0x28 6. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_6_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_6" "0,1" newline bitfld.long 0x28 5. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_5_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_5" "0,1" newline bitfld.long 0x28 4. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_4_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_4" "0,1" newline bitfld.long 0x28 3. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_3_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_3" "0,1" newline bitfld.long 0x28 2. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_2_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_2" "0,1" newline bitfld.long 0x28 1. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_1_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_1" "0,1" newline bitfld.long 0x28 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_0_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_0" "0,1" line.long 0x2C "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_dmpac_out_1_4,Status Clear Register 11" bitfld.long 0x2C 31. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_31_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_31" "0,1" newline bitfld.long 0x2C 30. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_30_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_30" "0,1" newline bitfld.long 0x2C 29. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_29_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_29" "0,1" newline bitfld.long 0x2C 28. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_28_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_28" "0,1" newline bitfld.long 0x2C 27. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_27_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_27" "0,1" newline bitfld.long 0x2C 26. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_26_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_26" "0,1" newline bitfld.long 0x2C 25. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_25_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_25" "0,1" newline bitfld.long 0x2C 24. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_24_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_24" "0,1" newline bitfld.long 0x2C 23. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_23_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_23" "0,1" newline bitfld.long 0x2C 22. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_22_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_22" "0,1" newline bitfld.long 0x2C 21. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_21_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_21" "0,1" newline bitfld.long 0x2C 20. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_20_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_20" "0,1" newline bitfld.long 0x2C 19. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_19_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_19" "0,1" newline bitfld.long 0x2C 18. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_18_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_18" "0,1" newline bitfld.long 0x2C 17. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_17_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_17" "0,1" newline bitfld.long 0x2C 16. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_16_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_16" "0,1" newline bitfld.long 0x2C 15. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_15_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_15" "0,1" newline bitfld.long 0x2C 14. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_14_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_14" "0,1" newline bitfld.long 0x2C 13. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_13_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_13" "0,1" newline bitfld.long 0x2C 12. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_12_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_12" "0,1" newline bitfld.long 0x2C 11. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_11_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_11" "0,1" newline bitfld.long 0x2C 10. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_10_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_10" "0,1" newline bitfld.long 0x2C 9. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_9_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_9" "0,1" newline bitfld.long 0x2C 8. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_8_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_8" "0,1" newline bitfld.long 0x2C 7. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_7_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_7" "0,1" newline bitfld.long 0x2C 6. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_6_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_6" "0,1" newline bitfld.long 0x2C 5. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_5_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_5" "0,1" newline bitfld.long 0x2C 4. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_4_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_4" "0,1" newline bitfld.long 0x2C 3. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_3_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_3" "0,1" newline bitfld.long 0x2C 2. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_2_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_2" "0,1" newline bitfld.long 0x2C 1. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_1_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_1" "0,1" newline bitfld.long 0x2C 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_0_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_0" "0,1" line.long 0x30 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_dmpac_out_1_5,Status Clear Register 12" bitfld.long 0x30 31. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_31_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_31" "0,1" newline bitfld.long 0x30 30. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_30_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_30" "0,1" newline bitfld.long 0x30 29. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_29_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_29" "0,1" newline bitfld.long 0x30 28. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_28_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_28" "0,1" newline bitfld.long 0x30 27. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_27_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_27" "0,1" newline bitfld.long 0x30 26. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_26_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_26" "0,1" newline bitfld.long 0x30 25. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_25_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_25" "0,1" newline bitfld.long 0x30 24. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_24_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_24" "0,1" newline bitfld.long 0x30 23. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_23_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_23" "0,1" newline bitfld.long 0x30 22. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_22_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_22" "0,1" newline bitfld.long 0x30 21. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_21_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_21" "0,1" newline bitfld.long 0x30 20. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_20_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_20" "0,1" newline bitfld.long 0x30 19. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_19_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_19" "0,1" newline bitfld.long 0x30 18. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_18_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_18" "0,1" newline bitfld.long 0x30 17. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_17_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_17" "0,1" newline bitfld.long 0x30 16. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_16_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_16" "0,1" newline bitfld.long 0x30 15. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_15_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_15" "0,1" newline bitfld.long 0x30 14. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_14_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_14" "0,1" newline bitfld.long 0x30 13. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_13_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_13" "0,1" newline bitfld.long 0x30 12. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_12_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_12" "0,1" newline bitfld.long 0x30 11. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_11_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_11" "0,1" newline bitfld.long 0x30 10. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_10_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_10" "0,1" newline bitfld.long 0x30 9. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_9_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_9" "0,1" newline bitfld.long 0x30 8. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_8_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_8" "0,1" newline bitfld.long 0x30 7. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_7_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_7" "0,1" newline bitfld.long 0x30 6. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_6_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_6" "0,1" newline bitfld.long 0x30 5. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_5_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_5" "0,1" newline bitfld.long 0x30 4. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_4_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_4" "0,1" newline bitfld.long 0x30 3. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_3_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_3" "0,1" newline bitfld.long 0x30 2. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_2_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_2" "0,1" newline bitfld.long 0x30 1. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_1_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_1" "0,1" newline bitfld.long 0x30 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_0_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_0" "0,1" line.long 0x34 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_dmpac_out_1_6,Status Clear Register 13" bitfld.long 0x34 1. "STATUS_LEVEL_DMPAC_OUT_1_CTM_PULSE_CLR,Status write 1 to clear for level_dmpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0x34 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_PROT_ERR_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_prot_err" "0,1" line.long 0x38 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_dmpac_out_0_0,Status Clear Register 14" bitfld.long 0x38 25. "STATUS_PULSE_DMPAC_OUT_0_FOCO_1_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1" newline bitfld.long 0x38 24. "STATUS_PULSE_DMPAC_OUT_0_FOCO_1_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1" newline bitfld.long 0x38 23. "STATUS_PULSE_DMPAC_OUT_0_FOCO_1_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_foco_1_fr_done_evt" "0,1" newline bitfld.long 0x38 22. "STATUS_PULSE_DMPAC_OUT_0_FOCO_0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1" newline bitfld.long 0x38 21. "STATUS_PULSE_DMPAC_OUT_0_FOCO_0_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1" newline bitfld.long 0x38 20. "STATUS_PULSE_DMPAC_OUT_0_FOCO_0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_foco_0_fr_done_evt" "0,1" newline bitfld.long 0x38 19. "STATUS_PULSE_DMPAC_OUT_0_SDE_WRITE_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_sde_write_error" "0,1" newline bitfld.long 0x38 18. "STATUS_PULSE_DMPAC_OUT_0_SDE_READ_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_sde_read_error" "0,1" newline bitfld.long 0x38 17. "STATUS_PULSE_DMPAC_OUT_0_SDE_FRAME_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_sde_frame_done" "0,1" newline bitfld.long 0x38 16. "STATUS_PULSE_DMPAC_OUT_0_SDE_BLK_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_sde_blk_done" "0,1" newline bitfld.long 0x38 4. "STATUS_PULSE_DMPAC_OUT_0_DOF_MP0_RD_STATUS_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1" newline bitfld.long 0x38 3. "STATUS_PULSE_DMPAC_OUT_0_DOF_WRITE_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dof_write_error" "0,1" newline bitfld.long 0x38 2. "STATUS_PULSE_DMPAC_OUT_0_DOF_READ_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dof_read_error" "0,1" newline bitfld.long 0x38 1. "STATUS_PULSE_DMPAC_OUT_0_DOF_FRAME_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dof_frame_done" "0,1" newline bitfld.long 0x38 0. "STATUS_PULSE_DMPAC_OUT_0_DOF_ROW_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dof_row_done" "0,1" line.long 0x3C "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_dmpac_out_0_1,Status Clear Register 15" bitfld.long 0x3C 27. "STATUS_PULSE_DMPAC_OUT_0_TDONE_8_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_tdone_8" "0,1" newline bitfld.long 0x3C 26. "STATUS_PULSE_DMPAC_OUT_0_TDONE_7_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_tdone_7" "0,1" newline bitfld.long 0x3C 25. "STATUS_PULSE_DMPAC_OUT_0_TDONE_1_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_tdone_1" "0,1" newline bitfld.long 0x3C 24. "STATUS_PULSE_DMPAC_OUT_0_TDONE_0_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_tdone_0" "0,1" newline bitfld.long 0x3C 9. "STATUS_PULSE_DMPAC_OUT_0_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0x3C 8. "STATUS_PULSE_DMPAC_OUT_0_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0x3C 3. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0x3C 2. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0x3C 1. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0x3C 0. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_pipe_done_0" "0,1" line.long 0x40 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_dmpac_out_0_2,Status Clear Register 16" bitfld.long 0x40 3. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_8_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_watchdogtimer_err_8" "0,1" newline bitfld.long 0x40 2. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_7_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_watchdogtimer_err_7" "0,1" newline bitfld.long 0x40 1. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_1_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_watchdogtimer_err_1" "0,1" newline bitfld.long 0x40 0. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_watchdogtimer_err_0" "0,1" line.long 0x44 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_dmpac_out_0_3,Status Clear Register 17" bitfld.long 0x44 31. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_31_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_31" "0,1" newline bitfld.long 0x44 30. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_30_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_30" "0,1" newline bitfld.long 0x44 29. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_29_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_29" "0,1" newline bitfld.long 0x44 28. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_28_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_28" "0,1" newline bitfld.long 0x44 27. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_27_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_27" "0,1" newline bitfld.long 0x44 26. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_26_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_26" "0,1" newline bitfld.long 0x44 25. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_25_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_25" "0,1" newline bitfld.long 0x44 24. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_24_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_24" "0,1" newline bitfld.long 0x44 23. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_23_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_23" "0,1" newline bitfld.long 0x44 22. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_22_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_22" "0,1" newline bitfld.long 0x44 21. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_21_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_21" "0,1" newline bitfld.long 0x44 20. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_20_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_20" "0,1" newline bitfld.long 0x44 19. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_19_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_19" "0,1" newline bitfld.long 0x44 18. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_18_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_18" "0,1" newline bitfld.long 0x44 17. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_17_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_17" "0,1" newline bitfld.long 0x44 16. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_16_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_16" "0,1" newline bitfld.long 0x44 15. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_15_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_15" "0,1" newline bitfld.long 0x44 14. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_14_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_14" "0,1" newline bitfld.long 0x44 13. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_13_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_13" "0,1" newline bitfld.long 0x44 12. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_12_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_12" "0,1" newline bitfld.long 0x44 11. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_11_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_11" "0,1" newline bitfld.long 0x44 10. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_10_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_10" "0,1" newline bitfld.long 0x44 9. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_9_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_9" "0,1" newline bitfld.long 0x44 8. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_8_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_8" "0,1" newline bitfld.long 0x44 7. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_7_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_7" "0,1" newline bitfld.long 0x44 6. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_6_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_6" "0,1" newline bitfld.long 0x44 5. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_5_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_5" "0,1" newline bitfld.long 0x44 4. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_4_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_4" "0,1" newline bitfld.long 0x44 3. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_3_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_3" "0,1" newline bitfld.long 0x44 2. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_2_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_2" "0,1" newline bitfld.long 0x44 1. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_1_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_1" "0,1" newline bitfld.long 0x44 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_0_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_0" "0,1" line.long 0x48 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_dmpac_out_0_4,Status Clear Register 18" bitfld.long 0x48 31. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_31_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_31" "0,1" newline bitfld.long 0x48 30. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_30_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_30" "0,1" newline bitfld.long 0x48 29. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_29_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_29" "0,1" newline bitfld.long 0x48 28. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_28_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_28" "0,1" newline bitfld.long 0x48 27. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_27_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_27" "0,1" newline bitfld.long 0x48 26. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_26_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_26" "0,1" newline bitfld.long 0x48 25. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_25_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_25" "0,1" newline bitfld.long 0x48 24. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_24_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_24" "0,1" newline bitfld.long 0x48 23. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_23_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_23" "0,1" newline bitfld.long 0x48 22. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_22_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_22" "0,1" newline bitfld.long 0x48 21. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_21_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_21" "0,1" newline bitfld.long 0x48 20. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_20_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_20" "0,1" newline bitfld.long 0x48 19. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_19_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_19" "0,1" newline bitfld.long 0x48 18. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_18_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_18" "0,1" newline bitfld.long 0x48 17. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_17_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_17" "0,1" newline bitfld.long 0x48 16. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_16_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_16" "0,1" newline bitfld.long 0x48 15. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_15_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_15" "0,1" newline bitfld.long 0x48 14. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_14_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_14" "0,1" newline bitfld.long 0x48 13. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_13_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_13" "0,1" newline bitfld.long 0x48 12. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_12_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_12" "0,1" newline bitfld.long 0x48 11. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_11_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_11" "0,1" newline bitfld.long 0x48 10. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_10_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_10" "0,1" newline bitfld.long 0x48 9. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_9_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_9" "0,1" newline bitfld.long 0x48 8. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_8_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_8" "0,1" newline bitfld.long 0x48 7. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_7_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_7" "0,1" newline bitfld.long 0x48 6. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_6_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_6" "0,1" newline bitfld.long 0x48 5. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_5_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_5" "0,1" newline bitfld.long 0x48 4. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_4_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_4" "0,1" newline bitfld.long 0x48 3. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_3_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_3" "0,1" newline bitfld.long 0x48 2. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_2_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_2" "0,1" newline bitfld.long 0x48 1. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_1_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_1" "0,1" newline bitfld.long 0x48 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_0_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_0" "0,1" line.long 0x4C "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_dmpac_out_0_5,Status Clear Register 19" bitfld.long 0x4C 31. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_31_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_31" "0,1" newline bitfld.long 0x4C 30. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_30_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_30" "0,1" newline bitfld.long 0x4C 29. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_29_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_29" "0,1" newline bitfld.long 0x4C 28. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_28_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_28" "0,1" newline bitfld.long 0x4C 27. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_27_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_27" "0,1" newline bitfld.long 0x4C 26. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_26_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_26" "0,1" newline bitfld.long 0x4C 25. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_25_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_25" "0,1" newline bitfld.long 0x4C 24. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_24_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_24" "0,1" newline bitfld.long 0x4C 23. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_23_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_23" "0,1" newline bitfld.long 0x4C 22. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_22_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_22" "0,1" newline bitfld.long 0x4C 21. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_21_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_21" "0,1" newline bitfld.long 0x4C 20. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_20_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_20" "0,1" newline bitfld.long 0x4C 19. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_19_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_19" "0,1" newline bitfld.long 0x4C 18. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_18_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_18" "0,1" newline bitfld.long 0x4C 17. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_17_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_17" "0,1" newline bitfld.long 0x4C 16. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_16_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_16" "0,1" newline bitfld.long 0x4C 15. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_15_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_15" "0,1" newline bitfld.long 0x4C 14. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_14_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_14" "0,1" newline bitfld.long 0x4C 13. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_13_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_13" "0,1" newline bitfld.long 0x4C 12. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_12_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_12" "0,1" newline bitfld.long 0x4C 11. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_11_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_11" "0,1" newline bitfld.long 0x4C 10. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_10_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_10" "0,1" newline bitfld.long 0x4C 9. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_9_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_9" "0,1" newline bitfld.long 0x4C 8. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_8_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_8" "0,1" newline bitfld.long 0x4C 7. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_7_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_7" "0,1" newline bitfld.long 0x4C 6. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_6_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_6" "0,1" newline bitfld.long 0x4C 5. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_5_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_5" "0,1" newline bitfld.long 0x4C 4. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_4_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_4" "0,1" newline bitfld.long 0x4C 3. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_3_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_3" "0,1" newline bitfld.long 0x4C 2. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_2_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_2" "0,1" newline bitfld.long 0x4C 1. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_1_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_1" "0,1" newline bitfld.long 0x4C 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_0_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_0" "0,1" line.long 0x50 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_dmpac_out_0_6,Status Clear Register 20" bitfld.long 0x50 1. "STATUS_PULSE_DMPAC_OUT_0_CTM_PULSE_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0x50 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_PROT_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_prot_err" "0,1" line.long 0x54 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_dmpac_out_1_0,Status Clear Register 21" bitfld.long 0x54 25. "STATUS_PULSE_DMPAC_OUT_1_FOCO_1_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1" newline bitfld.long 0x54 24. "STATUS_PULSE_DMPAC_OUT_1_FOCO_1_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1" newline bitfld.long 0x54 23. "STATUS_PULSE_DMPAC_OUT_1_FOCO_1_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_foco_1_fr_done_evt" "0,1" newline bitfld.long 0x54 22. "STATUS_PULSE_DMPAC_OUT_1_FOCO_0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1" newline bitfld.long 0x54 21. "STATUS_PULSE_DMPAC_OUT_1_FOCO_0_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1" newline bitfld.long 0x54 20. "STATUS_PULSE_DMPAC_OUT_1_FOCO_0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_foco_0_fr_done_evt" "0,1" newline bitfld.long 0x54 19. "STATUS_PULSE_DMPAC_OUT_1_SDE_WRITE_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_sde_write_error" "0,1" newline bitfld.long 0x54 18. "STATUS_PULSE_DMPAC_OUT_1_SDE_READ_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_sde_read_error" "0,1" newline bitfld.long 0x54 17. "STATUS_PULSE_DMPAC_OUT_1_SDE_FRAME_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_sde_frame_done" "0,1" newline bitfld.long 0x54 16. "STATUS_PULSE_DMPAC_OUT_1_SDE_BLK_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_sde_blk_done" "0,1" newline bitfld.long 0x54 4. "STATUS_PULSE_DMPAC_OUT_1_DOF_MP0_RD_STATUS_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1" newline bitfld.long 0x54 3. "STATUS_PULSE_DMPAC_OUT_1_DOF_WRITE_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dof_write_error" "0,1" newline bitfld.long 0x54 2. "STATUS_PULSE_DMPAC_OUT_1_DOF_READ_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dof_read_error" "0,1" newline bitfld.long 0x54 1. "STATUS_PULSE_DMPAC_OUT_1_DOF_FRAME_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dof_frame_done" "0,1" newline bitfld.long 0x54 0. "STATUS_PULSE_DMPAC_OUT_1_DOF_ROW_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dof_row_done" "0,1" line.long 0x58 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_dmpac_out_1_1,Status Clear Register 22" bitfld.long 0x58 27. "STATUS_PULSE_DMPAC_OUT_1_TDONE_8_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_tdone_8" "0,1" newline bitfld.long 0x58 26. "STATUS_PULSE_DMPAC_OUT_1_TDONE_7_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_tdone_7" "0,1" newline bitfld.long 0x58 25. "STATUS_PULSE_DMPAC_OUT_1_TDONE_1_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_tdone_1" "0,1" newline bitfld.long 0x58 24. "STATUS_PULSE_DMPAC_OUT_1_TDONE_0_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_tdone_0" "0,1" newline bitfld.long 0x58 9. "STATUS_PULSE_DMPAC_OUT_1_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0x58 8. "STATUS_PULSE_DMPAC_OUT_1_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0x58 3. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0x58 2. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0x58 1. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0x58 0. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_pipe_done_0" "0,1" line.long 0x5C "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_dmpac_out_1_2,Status Clear Register 23" bitfld.long 0x5C 3. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_8_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_watchdogtimer_err_8" "0,1" newline bitfld.long 0x5C 2. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_7_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_watchdogtimer_err_7" "0,1" newline bitfld.long 0x5C 1. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_1_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_watchdogtimer_err_1" "0,1" newline bitfld.long 0x5C 0. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_watchdogtimer_err_0" "0,1" line.long 0x60 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_dmpac_out_1_3,Status Clear Register 24" bitfld.long 0x60 31. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_31_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_31" "0,1" newline bitfld.long 0x60 30. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_30_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_30" "0,1" newline bitfld.long 0x60 29. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_29_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_29" "0,1" newline bitfld.long 0x60 28. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_28_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_28" "0,1" newline bitfld.long 0x60 27. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_27_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_27" "0,1" newline bitfld.long 0x60 26. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_26_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_26" "0,1" newline bitfld.long 0x60 25. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_25_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_25" "0,1" newline bitfld.long 0x60 24. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_24_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_24" "0,1" newline bitfld.long 0x60 23. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_23_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_23" "0,1" newline bitfld.long 0x60 22. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_22_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_22" "0,1" newline bitfld.long 0x60 21. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_21_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_21" "0,1" newline bitfld.long 0x60 20. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_20_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_20" "0,1" newline bitfld.long 0x60 19. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_19_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_19" "0,1" newline bitfld.long 0x60 18. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_18_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_18" "0,1" newline bitfld.long 0x60 17. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_17_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_17" "0,1" newline bitfld.long 0x60 16. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_16_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_16" "0,1" newline bitfld.long 0x60 15. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_15_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_15" "0,1" newline bitfld.long 0x60 14. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_14_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_14" "0,1" newline bitfld.long 0x60 13. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_13_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_13" "0,1" newline bitfld.long 0x60 12. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_12_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_12" "0,1" newline bitfld.long 0x60 11. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_11_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_11" "0,1" newline bitfld.long 0x60 10. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_10_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_10" "0,1" newline bitfld.long 0x60 9. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_9_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_9" "0,1" newline bitfld.long 0x60 8. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_8_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_8" "0,1" newline bitfld.long 0x60 7. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_7_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_7" "0,1" newline bitfld.long 0x60 6. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_6_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_6" "0,1" newline bitfld.long 0x60 5. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_5_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_5" "0,1" newline bitfld.long 0x60 4. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_4_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_4" "0,1" newline bitfld.long 0x60 3. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_3_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_3" "0,1" newline bitfld.long 0x60 2. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_2_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_2" "0,1" newline bitfld.long 0x60 1. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_1_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_1" "0,1" newline bitfld.long 0x60 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_0_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_0" "0,1" line.long 0x64 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_dmpac_out_1_4,Status Clear Register 25" bitfld.long 0x64 31. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_31_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_31" "0,1" newline bitfld.long 0x64 30. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_30_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_30" "0,1" newline bitfld.long 0x64 29. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_29_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_29" "0,1" newline bitfld.long 0x64 28. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_28_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_28" "0,1" newline bitfld.long 0x64 27. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_27_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_27" "0,1" newline bitfld.long 0x64 26. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_26_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_26" "0,1" newline bitfld.long 0x64 25. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_25_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_25" "0,1" newline bitfld.long 0x64 24. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_24_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_24" "0,1" newline bitfld.long 0x64 23. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_23_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_23" "0,1" newline bitfld.long 0x64 22. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_22_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_22" "0,1" newline bitfld.long 0x64 21. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_21_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_21" "0,1" newline bitfld.long 0x64 20. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_20_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_20" "0,1" newline bitfld.long 0x64 19. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_19_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_19" "0,1" newline bitfld.long 0x64 18. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_18_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_18" "0,1" newline bitfld.long 0x64 17. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_17_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_17" "0,1" newline bitfld.long 0x64 16. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_16_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_16" "0,1" newline bitfld.long 0x64 15. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_15_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_15" "0,1" newline bitfld.long 0x64 14. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_14_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_14" "0,1" newline bitfld.long 0x64 13. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_13_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_13" "0,1" newline bitfld.long 0x64 12. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_12_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_12" "0,1" newline bitfld.long 0x64 11. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_11_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_11" "0,1" newline bitfld.long 0x64 10. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_10_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_10" "0,1" newline bitfld.long 0x64 9. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_9_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_9" "0,1" newline bitfld.long 0x64 8. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_8_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_8" "0,1" newline bitfld.long 0x64 7. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_7_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_7" "0,1" newline bitfld.long 0x64 6. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_6_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_6" "0,1" newline bitfld.long 0x64 5. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_5_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_5" "0,1" newline bitfld.long 0x64 4. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_4_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_4" "0,1" newline bitfld.long 0x64 3. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_3_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_3" "0,1" newline bitfld.long 0x64 2. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_2_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_2" "0,1" newline bitfld.long 0x64 1. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_1_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_1" "0,1" newline bitfld.long 0x64 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_0_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_0" "0,1" line.long 0x68 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_dmpac_out_1_5,Status Clear Register 26" bitfld.long 0x68 31. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_31_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_31" "0,1" newline bitfld.long 0x68 30. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_30_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_30" "0,1" newline bitfld.long 0x68 29. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_29_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_29" "0,1" newline bitfld.long 0x68 28. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_28_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_28" "0,1" newline bitfld.long 0x68 27. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_27_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_27" "0,1" newline bitfld.long 0x68 26. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_26_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_26" "0,1" newline bitfld.long 0x68 25. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_25_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_25" "0,1" newline bitfld.long 0x68 24. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_24_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_24" "0,1" newline bitfld.long 0x68 23. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_23_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_23" "0,1" newline bitfld.long 0x68 22. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_22_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_22" "0,1" newline bitfld.long 0x68 21. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_21_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_21" "0,1" newline bitfld.long 0x68 20. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_20_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_20" "0,1" newline bitfld.long 0x68 19. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_19_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_19" "0,1" newline bitfld.long 0x68 18. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_18_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_18" "0,1" newline bitfld.long 0x68 17. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_17_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_17" "0,1" newline bitfld.long 0x68 16. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_16_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_16" "0,1" newline bitfld.long 0x68 15. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_15_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_15" "0,1" newline bitfld.long 0x68 14. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_14_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_14" "0,1" newline bitfld.long 0x68 13. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_13_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_13" "0,1" newline bitfld.long 0x68 12. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_12_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_12" "0,1" newline bitfld.long 0x68 11. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_11_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_11" "0,1" newline bitfld.long 0x68 10. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_10_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_10" "0,1" newline bitfld.long 0x68 9. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_9_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_9" "0,1" newline bitfld.long 0x68 8. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_8_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_8" "0,1" newline bitfld.long 0x68 7. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_7_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_7" "0,1" newline bitfld.long 0x68 6. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_6_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_6" "0,1" newline bitfld.long 0x68 5. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_5_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_5" "0,1" newline bitfld.long 0x68 4. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_4_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_4" "0,1" newline bitfld.long 0x68 3. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_3_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_3" "0,1" newline bitfld.long 0x68 2. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_2_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_2" "0,1" newline bitfld.long 0x68 1. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_1_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_1" "0,1" newline bitfld.long 0x68 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_0_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_0" "0,1" line.long 0x6C "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_dmpac_out_1_6,Status Clear Register 27" bitfld.long 0x6C 1. "STATUS_PULSE_DMPAC_OUT_1_CTM_PULSE_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0x6C 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_PROT_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_prot_err" "0,1" rgroup.long 0xA80++0xF line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_level_dmpac_out_0,Interrupt Vector for level_dmpac_out_0" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR_LEVEL_DMPAC_OUT_0,Interrupt Vector" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_level_dmpac_out_1,Interrupt Vector for level_dmpac_out_1" hexmask.long 0x4 0.--31. 1. "INTR_VECTOR_LEVEL_DMPAC_OUT_1,Interrupt Vector" line.long 0x8 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_pulse_dmpac_out_0,Interrupt Vector for pulse_dmpac_out_0" hexmask.long 0x8 0.--31. 1. "INTR_VECTOR_PULSE_DMPAC_OUT_0,Interrupt Vector" line.long 0xC "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_pulse_dmpac_out_1,Interrupt Vector for pulse_dmpac_out_1" hexmask.long 0xC 0.--31. 1. "INTR_VECTOR_PULSE_DMPAC_OUT_1,Interrupt Vector" tree.end tree "DMPAC0_SDE_0_PAR" tree "DMPAC0_SDE_0_PAR_PAR_SDE_S_VBUSP_MEM_MMRRAM_VBUSP_MMR_RAM (DMPAC0_SDE_0_PAR_PAR_SDE_S_VBUSP_MEM_MMRRAM_VBUSP_MMR_RAM)" base ad:0xF540000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_CS_HIST_RAM,cs_hist_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long.word 0x0 21.--31. 1. "RSVD,Always read as 0. Writes have no effect." hexmask.long.tbyte 0x0 0.--20. 1. "DATA,Data read from RAM" rgroup.long 0x400++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_S0_RAM,srb_s0_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long.byte 0x0 24.--31. 1. "RSVD,Always read as 0. Writes have no effect." hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data read from RAM" rgroup.long 0x800++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_S1_RAM,srb_s1_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long.byte 0x0 24.--31. 1. "RSVD,Always read as 0. Writes have no effect." hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data read from RAM" rgroup.long 0x1000++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_L0_RAM,srb_l0_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long.byte 0x0 24.--31. 1. "RSVD,Always read as 0. Writes have no effect." hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data read from RAM" rgroup.long 0x1800++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_L1_RAM,srb_l1_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long.byte 0x0 24.--31. 1. "RSVD,Always read as 0. Writes have no effect." hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data read from RAM" rgroup.long 0x2000++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_L2_RAM,srb_l2_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long.byte 0x0 24.--31. 1. "RSVD,Always read as 0. Writes have no effect." hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data read from RAM" rgroup.long 0x2800++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_L3_RAM,srb_l3_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long.byte 0x0 24.--31. 1. "RSVD,Always read as 0. Writes have no effect." hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data read from RAM" rgroup.long 0x3000++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_L4_RAM,srb_l4_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long.byte 0x0 24.--31. 1. "RSVD,Always read as 0. Writes have no effect." hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data read from RAM" rgroup.long 0x3800++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_L5_RAM,srb_l5_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long.byte 0x0 24.--31. 1. "RSVD,Always read as 0. Writes have no effect." hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data read from RAM" rgroup.long 0x4000++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SRB_L6_RAM,srb_l6_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long.byte 0x0 24.--31. 1. "RSVD,Always read as 0. Writes have no effect." hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data read from RAM" rgroup.long 0x6000++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_DRCG_FAST_LR_RAM,drcg_fast_lr_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0x8000++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_LCC_OP0_RAM,lcc_op0_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0xC000++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_LCC_OP1_RAM,lcc_op1_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0x10000++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_LCC_OP2_RAM,lcc_op2_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0x14000++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_LCC_OP3_RAM,lcc_op3_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0x18000++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_LCC_OP4_RAM,lcc_op4_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0x1C000++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_DRCG_DISP_RAM,drcg_disp_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long.word 0x0 20.--31. 1. "RSVD,Always read as 0. Writes have no effect." hexmask.long.tbyte 0x0 0.--19. 1. "DATA,Data read from RAM" rgroup.long 0x20000++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_MF_LINE_RAM,mf_line_ram diagnostic read only port. vbusp will stall until RAM is available for read" bitfld.long 0x0 30.--31. "RSVD,Always read as 0. Writes have no effect." "0,1,2,3" hexmask.long 0x0 0.--29. 1. "DATA,Data read from RAM" rgroup.long 0x28000++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SCA_BRC_RAM,sca_brc_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." rgroup.long 0x30000++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_SCA_BPCC_RAM,sca_bpcc_ram diagnostic read only port. vbusp will stall until RAM is available for read" hexmask.long 0x0 0.--31. 1. "DATA,Data read from RAM. RAM is wider than 32bit vbus. MMR reads are byte addresses into RAM where RAM Width is extended/zero padded to next pwr2." tree.end tree "DMPAC0_SDE_0_PAR_PAR_SDE_S_VBUSP_MMR_VBUSP_MMR (DMPAC0_SDE_0_PAR_PAR_SDE_S_VBUSP_MMR_VBUSP_MMR)" base ad:0xF500000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MMR__MMR_VBUSP__MMR_PID,SDE PID" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and new scheme. Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU indicator DSPS ==> 0x0 WTBU ==> 0x1 Processors ==> 0x2" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family. If there is no level of software compatibility a new FUNC number and hence PID should be assigned." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version. R as described in PDR with additional clarifications and definitions below. Must be easily ECO-able or controlled during fabrication. Ideally through a top level metal mask or e-fuse. This number is maintained/owned by IP design.." bitfld.long 0x0 8.--10. "MAJOR,Major Revision. X as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. X is part of IP numbering X.Y.R.Z. X changes ONLY when: (1) There is a major feature addition. An.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library (CSL) / Drivers. 0 if non-custom." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision. Y as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. Y changes ONLY when: (1) Features are scaled (up or down). Flexibility exists in that this.." rgroup.long 0x4++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MMR__MMR_VBUSP__MMR_CTRL_REG,SDE control register contains fields that can be used to control DMPAC operation." hexmask.long 0x0 4.--31. 1. "RSVD,always read as 0. Write has no effect" bitfld.long 0x0 3. "RRSRCHEN,Enable reduced range search on pixels near right margin where the search range is less than the configured maximum disparity. Write a '1' to enable reduced range search. Default is full range search where disparity is only produced for pixels.." "0,1" bitfld.long 0x0 2. "MEDFEN,Median filter enable. Write a '1' to enable median filter for post processing" "0,1" newline bitfld.long 0x0 1. "SDEEN,SDE enable. Write a '1' to enable DMPAC stereo" "0,1" rbitfld.long 0x0 0. "RSVD1,always read as 0. Write has no effect" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MMR__MMR_VBUSP__MMR_STATUS_REG,SDE status register contains fields that return the DMPAC stereo internal status." hexmask.long.tbyte 0x0 11.--31. 1. "RSVD,always read as 0. Write has no effect" bitfld.long 0x0 10. "SDEIDLE,sdeidle=1 indicate SDE is idle" "0,1" bitfld.long 0x0 8.--9. "LCCSTAT,LCC sub-module status: 2'b00: IDLE 2'b01: ACTIVE 2'b10: PAUSE 2'b11: RSVD" "0: IDLE,1: ACTIVE,2: PAUSE,3: RSVD" newline bitfld.long 0x0 6.--7. "SCASTAT,SCA sub-module status: 2'b00: IDLE 2'b01: ACTIVE 2'b10: PAUSE 2'b11: RSVD" "0: IDLE,1: ACTIVE,2: PAUSE,3: RSVD" bitfld.long 0x0 4.--5. "DRCGSTAT,DRCG sub-module status: 2'b00: IDLE 2'b01: ACTIVE 2'b10: PAUSE 2'b11: RSVD" "0: IDLE,1: ACTIVE,2: PAUSE,3: RSVD" bitfld.long 0x0 2.--3. "MEDFCGSTAT,Median filter sub-module status: 2'b00: IDLE 2'b01: ACTIVE 2'b10: PAUSE 2'b11: RSVD" "0: IDLE,1: ACTIVE,2: PAUSE,3: RSVD" newline bitfld.long 0x0 0.--1. "DPACKSTAT,Disparity packing sub-module status: 2'b00: IDLE 2'b01: ACTIVE 2'b10: PAUSE 2'b11: RSVD" "0: IDLE,1: ACTIVE,2: PAUSE,3: RSVD" rgroup.long 0xC++0x3B line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MMR__MMR_VBUSP__MMR_IMGRES_REG,SDE image resolution register contains fields that can be used to configure input image resolution." hexmask.long.word 0x0 23.--31. 1. "RSVD,always read as 0. Write has no effect" hexmask.long.byte 0x0 16.--22. 1. "IWINC,Image width increment factor. Image width iw=128 + 16*iwinc pixels iwinc=0 1 ... 120. Any value greater than 120 will be treated as 120." hexmask.long.word 0x0 6.--15. 1. "RSVD1,always read as 0. Write has no effect" newline hexmask.long.byte 0x0 0.--5. 1. "IHINC,Image height increment factor. Image height ih=64 + 16*ihinc pixels ihinc=0 1 ... 60. Any value greater than 60 will be treated as 60." line.long 0x4 "PAR_PAR_SDE__S_VBUSP__MMR__MMR_VBUSP__MMR_SRCHRNG_REG,SDE search range register contains fields that can be used to configure disparity search range." hexmask.long 0x4 3.--31. 1. "RSVD,always read as 0. Write has no effect" bitfld.long 0x4 1.--2. "CFGDRANGE,Configure disparity search range in pixels. 2'b00: search range= 64 (-3 to 60 or 0 to 63) 2'b01:search range=128 (-3 to 124 or 0 to 127) others: search range =192 (-3 to 188 or 0 to 191)." "0: search range= 64,1: search range=128,?,?" bitfld.long 0x4 0. "CFGDMIN,Configure minimum disparity (minDisp) to be searched in pixels. 0: minDisp=0 1:minDisp= -3." "0: minDisp=0,1: minDisp= -3" line.long 0x8 "PAR_PAR_SDE__S_VBUSP__MMR__MMR_VBUSP__MMR_LRCHCK_REG,SDE left-right consistence check register contains fields that can be used to configure left-right consistence check." hexmask.long.tbyte 0x8 8.--31. 1. "RSVD,always read as 0. Write has no effect" hexmask.long.byte 0x8 0.--7. 1. "DIFFTHLD,Left-right consistence check threshold in pixels. Program diffThld >= maxDisp-minDisp will disable Left-right consistence check." line.long 0xC "PAR_PAR_SDE__S_VBUSP__MMR__MMR_VBUSP__MMR_TXTFLT_REG,SDE texture based filtering control register contains fields that can be used to configure texture based filtering function." hexmask.long.tbyte 0xC 9.--31. 1. "RSVD,always read as 0. Write has no effect" hexmask.long.byte 0xC 1.--8. 1. "TXTTHLD,Scaled texture threshold. Any pixel whose texture metric is lower than txtthld is considered to be low texture. It is specified as normalized texture threshold times 1024. For instance if txtthld = 204 the normalized texture threshold is.." bitfld.long 0xC 0. "TXTFLTEN,Enable texture based filtering" "0,1" line.long 0x10 "PAR_PAR_SDE__S_VBUSP__MMR__MMR_VBUSP__MMR_PNLTY_REG,SDE cost penalty configuration register contains fields that can be used to configure cost penalty function." hexmask.long.word 0x10 23.--31. 1. "RSVD,always read as 0. Write has no effect" hexmask.long.byte 0x10 16.--22. 1. "P1,SDE aggregation penalty P1. Optimization penalty constant for small disparity change." hexmask.long.byte 0x10 8.--14. 1. "RSVD1,always read as 0. Write has no effect" newline hexmask.long.byte 0x10 0.--7. 1. "P2,SDE aggregation penalty P2. Optimization penalty constant for large disparity change. p2 <= 192. Any value greater than 192 will be treated as 192" line.long 0x14 "PAR_PAR_SDE__S_VBUSP__MMR__MMR_VBUSP__MMR_CONFMAPG0_REG,SDE confidence score mapping configuration register 0 specifies level 0 and 1 mapping threshold." hexmask.long.word 0x14 23.--31. 1. "RSVD0,always read as 0. Write has no effect" hexmask.long.byte 0x14 16.--22. 1. "CONFMAP_0,SDE confidence score mapping 0. Internal confidence score will map to level 0 (of 8 level output) if it is less than confmap_0" hexmask.long.word 0x14 7.--15. 1. "RSVD1,always read as 0. Write has no effect" newline hexmask.long.byte 0x14 0.--6. 1. "CONFMAP_1,SDE confidence score mapping 1. Internal confidence score will map to level 1 if it is less than confmap_1 but greater than or equal to confmap_0" line.long 0x18 "PAR_PAR_SDE__S_VBUSP__MMR__MMR_VBUSP__MMR_CONFMAPG1_REG,SDE confidence score mapping configuration register 1 specifies level 2 and 3 mapping threshold." hexmask.long.word 0x18 23.--31. 1. "RSVD0,always read as 0. Write has no effect" hexmask.long.byte 0x18 16.--22. 1. "CONFMAP_2,SDE confidence score mapping 2. Internal confidence score will map to level 2 if it is less than confmap_2 but greater than or equal to confmap_1" hexmask.long.word 0x18 7.--15. 1. "RSVD1,always read as 0. Write has no effect" newline hexmask.long.byte 0x18 0.--6. 1. "CONFMAP_3,SDE confidence score mapping 3. Internal confidence score will map to level 3 if it is less than confmap_3 but greater than or equal to confmap_2" line.long 0x1C "PAR_PAR_SDE__S_VBUSP__MMR__MMR_VBUSP__MMR_CONFMAPG2_REG,SDE confidence score mapping configuration register 2 specifies level 4 and 5 mapping threshold." hexmask.long.word 0x1C 23.--31. 1. "RSVD0,always read as 0. Write has no effect" hexmask.long.byte 0x1C 16.--22. 1. "CONFMAP_4,SDE confidence score mapping 4. Internal confidence score will map to level 4 if it is less than confmap_4 but greater than or equal to confmap_3" hexmask.long.word 0x1C 7.--15. 1. "RSVD1,always read as 0. Write has no effect" newline hexmask.long.byte 0x1C 0.--6. 1. "CONFMAP_5,SDE confidence score mapping 5. Internal confidence score will map to level 5 if it is less than confmap_5 but greater than or equal to confmap_4" line.long 0x20 "PAR_PAR_SDE__S_VBUSP__MMR__MMR_VBUSP__MMR_CONFMAPG3_REG,SDE confidence score mapping configuration register 3 specifies level 6 and 7 mapping threshold." hexmask.long.word 0x20 23.--31. 1. "RSVD0,always read as 0. Write has no effect" hexmask.long.byte 0x20 16.--22. 1. "CONFMAP_6,SDE confidence score mapping 6. Internal confidence score will map to level 6 if it is less than confmap_6 but greater than or equal to confmap_5" hexmask.long.word 0x20 0.--15. 1. "RSVD1,always read as 0. Write has no effect" line.long 0x24 "PAR_PAR_SDE__S_VBUSP__MMR__MMR_VBUSP__MMR_BASEIMGADDR_REG,SDE base image buffer start address register specifies the base image buffer start address in SL2." hexmask.long.word 0x24 20.--31. 1. "RSVD,always read as 0. Write has no effect" hexmask.long.tbyte 0x24 0.--19. 1. "BASEAD,SL2 base image buffer start address (byte address aligned to 64 byte boundary basead[5:0] should be programmed as 0)." line.long 0x28 "PAR_PAR_SDE__S_VBUSP__MMR__MMR_VBUSP__MMR_BASEIMGWD_REG,SDE base image buffer width register specifies the SL2 base image buffer width (The height is fixed at 24 for growing window)." hexmask.long.tbyte 0x28 12.--31. 1. "RSVD,always read as 0. Write has no effect" hexmask.long.word 0x28 0.--11. 1. "BWIDTH,SL2 base image buffer width in bytes. bwidth has to satisfy bwidth >= 1.5iw (image width) and is aligned to 64 byte boundaries (LSB 6 bits are always programmed as 0)." line.long 0x2C "PAR_PAR_SDE__S_VBUSP__MMR__MMR_VBUSP__MMR_REFIMGADDR_REG,SDE reference image buffer start address register specifies the reference image buffer start address in SL2." hexmask.long.word 0x2C 20.--31. 1. "RSVD,always read as 0. Write has no effect" hexmask.long.tbyte 0x2C 0.--19. 1. "REFAD,SL2 reference image buffer start address (byte address aligned to 64 byte boundary refad[5:0] should be programmed as 0)." line.long 0x30 "PAR_PAR_SDE__S_VBUSP__MMR__MMR_VBUSP__MMR_REFIMGWD_REG,SDE reference image buffer width register specifies the SL2 reference image buffer width (The height is fixed at 24 for growing window)." hexmask.long.tbyte 0x30 12.--31. 1. "RSVD,always read as 0. Write has no effect" hexmask.long.word 0x30 0.--11. 1. "RWIDTH,SL2 reference image buffer width in bytes. rwidth has to satisfy rwidth >= 1.5*iw (image width) and is aligned to 64 byte boundaries (LSB 6 bits are always programmed as 0)." line.long 0x34 "PAR_PAR_SDE__S_VBUSP__MMR__MMR_VBUSP__MMR_DISPBUFCFG_REG,SDE disparity block buffer configuration register specifies the disparity output block buffer start address and number of buffers in SL2." rbitfld.long 0x34 29.--31. "RSVD0,always read as 0. Write has no effect" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x34 24.--28. 1. "NUMDISPBUF_M1,number of SL2 disparity block buffers minus 1. For instance programming numdispbuf_m1 to 1 makes a ping-pong buffer (number of disparity buffers is 2). When SL2 memory is available programming numdispbuf_m1 to a larger value allow SDE to.." hexmask.long.byte 0x34 20.--23. 1. "RSVD1,always read as 0. Write has no effect" newline hexmask.long.tbyte 0x34 0.--19. 1. "DISPBUFAD,SL2 disparity output block buffer start address (byte address aligned to 64 byte boundary dispbufad[5:0] should be programmed as 0)." line.long 0x38 "PAR_PAR_SDE__S_VBUSP__MMR__MMR_VBUSP__MMR_IRCBUF_REG,SDE image row cost buffer configuration register specifies the image row cost buffer start address in SL2." hexmask.long.word 0x38 20.--31. 1. "RSVD1,always read as 0. Write has no effect" hexmask.long.tbyte 0x38 0.--19. 1. "IRCBUFAD,SL2 image row cost buffer start address (byte address aligned to 64 byte boundary ircbufad[5:0] should be programmed as 0)." rgroup.long 0x50++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MMR__MMR_VBUSP__MMR_psa_ctrl,Control register for calculating 32b CRC signature on stereo disparity output" bitfld.long 0x0 0. "PSA_EN_CFG,Enable calculating 32b CRC signature on 16b stereo disparity and confidence score output" "0,1" rgroup.long 0x54++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MMR__MMR_VBUSP__MMR_psa_signature,32b CRC signature calculated on stereo disparity output" hexmask.long 0x0 0.--31. 1. "CRC_STS,32b CRC signature value as calculated on 16b stereo disparity and confidence score output" rgroup.long 0x60++0x3 line.long 0x0 "PAR_PAR_SDE__S_VBUSP__MMR__MMR_VBUSP__MMR_HIST,SDE Histogram registers stores the counter value of how many confidence scores (scaled to 7-bits) have fallen into each bin" hexmask.long.word 0x0 21.--31. 1. "RSVD,Always read as 0. Writes have no effect." hexmask.long.tbyte 0x0 0.--20. 1. "BIN_STS,BIN accumulated counter value. Clear to 0 within a 128 cycle window after hts_sde_init is asserted." tree.end tree.end tree.end tree "DMPAC_VPAC_PSILSS0_MMRS (DMPAC_VPAC_PSILSS0_MMRS)" base ad:0x341C000 rgroup.long 0x0++0x7 line.long 0x0 "MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." rgroup.long 0x10++0x3 line.long 0x0 "MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." rgroup.long 0x40++0x3 line.long 0x0 "MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end tree "DPHY" base ad:0x0 tree "DPHY_RX0" tree "DPHY_RX0_MMR_SLV_K3_DPHY_WRAP (DPHY_RX0_MMR_SLV_K3_DPHY_WRAP)" base ad:0x4581000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__SLV__K3_DPHY_WRAP_REGS_lane,lane control and status" rbitfld.long 0x0 31. "RXCLKACTIVEHSCLK,Receiver high speed clock active: Driven active when the receiver high speed clock is active. 1'b0: Receiver high speed clock not active 1'b1: Receiver high speed clock active" "0: Receiver high speed clock not active,1: Receiver high speed clock active" newline rbitfld.long 0x0 30. "CMN_READY,Common ready indication: Indicates the completion of the startup process of the common module. Once this signal is driven active the PMA lanes may be released from reset. 1'b0 : Indicates that the startup process for the common components is.." "0: Indicates that the startup process for the..,1: Indicates that the startup process for the.." newline bitfld.long 0x0 26. "PSO_DISABLE,Disable power shut off: Disables the ability to switch off the analog switched power islands in the lane when in the ultra low power state. 1'b0: Power islands are switched off and on under the normal control of the escape mode process." "0: Power islands are switched off and on under the..,1: Power island shutoff functions disabled" newline bitfld.long 0x0 24. "PSO_CMN,Disable power shut off: Power Shutoff signal for CMN 1 : CMN is power OFF 0 : CMN is power ON" "0: CMN is power ON,1: CMN is power OFF" newline bitfld.long 0x0 23. "LANE_RSTB_CMN,SW reset for CMN. 0:asserted 1:released" "0: asserted 1:released,?" newline hexmask.long.byte 0x0 16.--22. 1. "PSM_CLOCK_FREQ,PMA state machine clock frequency divider control: This signal specifies a divider value used to create an internal divided clock that is a function of the psm_clock clock. This signal must be driven with a value such that the frequency of.." newline bitfld.long 0x0 9.--11. "IPCONFIG_CMN,This signal decides which clock lane acts as master clock lane to all data lanes. Needed only for RX IP. Bit[2]: Reserved CASE {Bit[1] Bit[0]}: 00: Left RX clk lane provides clock to all left and right data lanes. 01: Left RX clk lane.." "0: Left RX clk lane provides clock to all left and..,1: Left RX clk lane provides clock to all right..,?,?,?,?,?,?" newline bitfld.long 0x0 8. "CLK_SWAPDPDN_DL_L_3,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped 1'b1: Swapped,?" newline bitfld.long 0x0 7. "CLK_SWAPDPDN_DL_L_2,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped 1'b1: Swapped,?" newline bitfld.long 0x0 6. "DATA_SWAPDPDN_DL_L_3,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped 1'b1: Swapped,?" newline bitfld.long 0x0 5. "DATA_SWAPDPDN_DL_L_2,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped 1'b1: Swapped,?" newline bitfld.long 0x0 4. "CLK_SWAPDPDN_DL_L_1,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped 1'b1: Swapped,?" newline bitfld.long 0x0 3. "CLK_SWAPDPDN_DL_L_0,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped 1'b1: Swapped,?" newline bitfld.long 0x0 2. "DATA_SWAPDPDN_DL_L_1,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped 1'b1: Swapped,?" newline bitfld.long 0x0 1. "DATA_SWAPDPDN_DL_L_0,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped 1'b1: Swapped,?" newline bitfld.long 0x0 0. "CLK_SWAPDPDN_CL_L,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped 1'b1: Swapped,?" tree.end tree "DPHY_RX0_VBUS2APB_WRAP_VBUSP_K3_DPHY_RX (DPHY_RX0_VBUS2APB_WRAP_VBUSP_K3_DPHY_RX)" base ad:0x4580000 rgroup.long 0x20++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_CMN0_CMN_DIG_TBIT2,CMN_DIG_TBIT2" bitfld.long 0x0 10. "O_CMN_RX_MODE_EN,Enable CMN RX related StateMachines" "0,1" bitfld.long 0x0 9. "O_CMN_TX_MODE_EN,Enable CMN TX related StateMachines" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "O_SSM_WAIT_BGCAL_EN,Wait time for Calibrations enable after bandgap is enabled [in us]" bitfld.long 0x0 0. "O_CMN_SSM_EN,Enable CMN startup state machine" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_CMN0_CMN_DIG_TBIT10,CMN_DIG_TBIT10" hexmask.long.byte 0x0 20.--27. 1. "O_ANA_PLL_BYTECLK_DIV,Byteclk divider value" hexmask.long.word 0x0 10.--19. 1. "O_ANA_PLL_GM_PWM_DIV_LOW,Low division value setting for the gm PWM control divider" newline hexmask.long.word 0x0 0.--9. 1. "O_ANA_PLL_GM_PWM_DIV_HIGH,High division value setting for the gm PWM control divider" rgroup.long 0x4C++0x7 line.long 0x0 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_CMN0_CMN_DIG_TBIT13,CMN_DIG_TBIT13" hexmask.long.word 0x0 22.--31. 1. "O_ANA_PLL_FB_DIV_LOW_TM,forced value for pll_fb_div_clk_low" bitfld.long 0x0 21. "O_ANA_PLL_FB_DIV_LOW_TM_SEL,pll_fb_div_clk_low forced from test registers" "0,1" newline hexmask.long.word 0x0 11.--20. 1. "O_ANA_PLL_FB_DIV_HIGH_TM,forced value for pll_fb_div_clk_high" bitfld.long 0x0 10. "O_ANA_PLL_FB_DIV_HIGH_TM_SEL,pll_fb_div_clk_high forced from test registers" "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_CMN0_CMN_DIG_TBIT14,CMN_DIG_TBIT14" hexmask.long.byte 0x4 7.--12. 1. "O_ANA_PLL_OP_DIV_TM,forced value for op_div" bitfld.long 0x4 6. "O_ANA_PLL_OP_DIV_TM_SEL,op_div forced from test registers" "0,1" newline hexmask.long.byte 0x4 1.--5. 1. "O_ANA_PLL_IP_DIV_TM,forced value for ip_div" bitfld.long 0x4 0. "O_ANA_PLL_IP_DIV_TM_SEL,ip_div forced from test registers" "0,1" rgroup.long 0xB00++0xF line.long 0x0 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_PCS_TX_DIG_TBIT0,PHY_BAND_CONTROL" hexmask.long.byte 0x0 5.--9. 1. "BAND_CTL_REG_R,Data Rate [80_100] MHz" hexmask.long.byte 0x0 0.--4. 1. "BAND_CTL_REG_L,Data Rate [80_100] MHz" line.long 0x4 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_PCS_TX_DIG_TBIT1,PHY_PSM_CONFIG" hexmask.long.byte 0x4 1.--8. 1. "PSM_CLOCK_FREQ,psm_clock freq value" bitfld.long 0x4 0. "PSM_CLOCK_FREQ_EN,take psm_clock_freq from tbit" "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_PCS_TX_DIG_TBIT2,PHY_PI_PH2_DL_CONFIG" hexmask.long.byte 0x8 28.--31. 1. "POWER_SW_2_TIME_DL_R_3,power_sw_2_time_dl_r_3" hexmask.long.byte 0x8 24.--27. 1. "POWER_SW_2_TIME_DL_R_2,power_sw_2_time_dl_r_2" newline hexmask.long.byte 0x8 20.--23. 1. "POWER_SW_2_TIME_DL_R_1,power_sw_2_time_dl_r_1" hexmask.long.byte 0x8 16.--19. 1. "POWER_SW_2_TIME_DL_R_0,power_sw_2_time_dl_r_0" newline hexmask.long.byte 0x8 12.--15. 1. "POWER_SW_2_TIME_DL_L_3,power_sw_2_time_dl_l_3" hexmask.long.byte 0x8 8.--11. 1. "POWER_SW_2_TIME_DL_L_2,power_sw_2_time_dl_l_2" newline hexmask.long.byte 0x8 4.--7. 1. "POWER_SW_2_TIME_DL_L_1,power_sw_2_time_dl_l_1" hexmask.long.byte 0x8 0.--3. 1. "POWER_SW_2_TIME_DL_L_0,power_sw_2_time_dl_l_0" line.long 0xC "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_PCS_TX_DIG_TBIT3,PHY_PI_PH2_CL_CMN_CONFIG" hexmask.long.byte 0xC 8.--11. 1. "POWER_SW_2_TIME_CMN,power_sw_2_time_cmn" hexmask.long.byte 0xC 4.--7. 1. "POWER_SW_2_TIME_CL_R,power_sw_2_time_cl_r" newline hexmask.long.byte 0xC 0.--3. 1. "POWER_SW_2_TIME_CL_L,power_sw_2_time_cl_l" tree.end tree.end tree "DPHY_RX1" tree "DPHY_RX1_MMR_SLV_K3_DPHY_WRAP (DPHY_RX1_MMR_SLV_K3_DPHY_WRAP)" base ad:0x4591000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__SLV__K3_DPHY_WRAP_REGS_lane,lane control and status" rbitfld.long 0x0 31. "RXCLKACTIVEHSCLK,Receiver high speed clock active: Driven active when the receiver high speed clock is active. 1'b0: Receiver high speed clock not active 1'b1: Receiver high speed clock active" "0: Receiver high speed clock not active,1: Receiver high speed clock active" newline rbitfld.long 0x0 30. "CMN_READY,Common ready indication: Indicates the completion of the startup process of the common module. Once this signal is driven active the PMA lanes may be released from reset. 1'b0 : Indicates that the startup process for the common components is.." "0: Indicates that the startup process for the..,1: Indicates that the startup process for the.." newline bitfld.long 0x0 26. "PSO_DISABLE,Disable power shut off: Disables the ability to switch off the analog switched power islands in the lane when in the ultra low power state. 1'b0: Power islands are switched off and on under the normal control of the escape mode process." "0: Power islands are switched off and on under the..,1: Power island shutoff functions disabled" newline bitfld.long 0x0 24. "PSO_CMN,Disable power shut off: Power Shutoff signal for CMN 1 : CMN is power OFF 0 : CMN is power ON" "0: CMN is power ON,1: CMN is power OFF" newline bitfld.long 0x0 23. "LANE_RSTB_CMN,SW reset for CMN. 0:asserted 1:released" "0: asserted 1:released,?" newline hexmask.long.byte 0x0 16.--22. 1. "PSM_CLOCK_FREQ,PMA state machine clock frequency divider control: This signal specifies a divider value used to create an internal divided clock that is a function of the psm_clock clock. This signal must be driven with a value such that the frequency of.." newline bitfld.long 0x0 9.--11. "IPCONFIG_CMN,This signal decides which clock lane acts as master clock lane to all data lanes. Needed only for RX IP. Bit[2]: Reserved CASE {Bit[1] Bit[0]}: 00: Left RX clk lane provides clock to all left and right data lanes. 01: Left RX clk lane.." "0: Left RX clk lane provides clock to all left and..,1: Left RX clk lane provides clock to all right..,?,?,?,?,?,?" newline bitfld.long 0x0 8. "CLK_SWAPDPDN_DL_L_3,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped 1'b1: Swapped,?" newline bitfld.long 0x0 7. "CLK_SWAPDPDN_DL_L_2,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped 1'b1: Swapped,?" newline bitfld.long 0x0 6. "DATA_SWAPDPDN_DL_L_3,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped 1'b1: Swapped,?" newline bitfld.long 0x0 5. "DATA_SWAPDPDN_DL_L_2,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped 1'b1: Swapped,?" newline bitfld.long 0x0 4. "CLK_SWAPDPDN_DL_L_1,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped 1'b1: Swapped,?" newline bitfld.long 0x0 3. "CLK_SWAPDPDN_DL_L_0,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped 1'b1: Swapped,?" newline bitfld.long 0x0 2. "DATA_SWAPDPDN_DL_L_1,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped 1'b1: Swapped,?" newline bitfld.long 0x0 1. "DATA_SWAPDPDN_DL_L_0,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped 1'b1: Swapped,?" newline bitfld.long 0x0 0. "CLK_SWAPDPDN_CL_L,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped 1'b1: Swapped,?" tree.end tree "DPHY_RX1_VBUS2APB_WRAP_VBUSP_K3_DPHY_RX (DPHY_RX1_VBUS2APB_WRAP_VBUSP_K3_DPHY_RX)" base ad:0x4590000 rgroup.long 0x20++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_CMN0_CMN_DIG_TBIT2,CMN_DIG_TBIT2" bitfld.long 0x0 10. "O_CMN_RX_MODE_EN,Enable CMN RX related StateMachines" "0,1" bitfld.long 0x0 9. "O_CMN_TX_MODE_EN,Enable CMN TX related StateMachines" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "O_SSM_WAIT_BGCAL_EN,Wait time for Calibrations enable after bandgap is enabled [in us]" bitfld.long 0x0 0. "O_CMN_SSM_EN,Enable CMN startup state machine" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_CMN0_CMN_DIG_TBIT10,CMN_DIG_TBIT10" hexmask.long.byte 0x0 20.--27. 1. "O_ANA_PLL_BYTECLK_DIV,Byteclk divider value" hexmask.long.word 0x0 10.--19. 1. "O_ANA_PLL_GM_PWM_DIV_LOW,Low division value setting for the gm PWM control divider" newline hexmask.long.word 0x0 0.--9. 1. "O_ANA_PLL_GM_PWM_DIV_HIGH,High division value setting for the gm PWM control divider" rgroup.long 0x4C++0x7 line.long 0x0 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_CMN0_CMN_DIG_TBIT13,CMN_DIG_TBIT13" hexmask.long.word 0x0 22.--31. 1. "O_ANA_PLL_FB_DIV_LOW_TM,forced value for pll_fb_div_clk_low" bitfld.long 0x0 21. "O_ANA_PLL_FB_DIV_LOW_TM_SEL,pll_fb_div_clk_low forced from test registers" "0,1" newline hexmask.long.word 0x0 11.--20. 1. "O_ANA_PLL_FB_DIV_HIGH_TM,forced value for pll_fb_div_clk_high" bitfld.long 0x0 10. "O_ANA_PLL_FB_DIV_HIGH_TM_SEL,pll_fb_div_clk_high forced from test registers" "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_CMN0_CMN_DIG_TBIT14,CMN_DIG_TBIT14" hexmask.long.byte 0x4 7.--12. 1. "O_ANA_PLL_OP_DIV_TM,forced value for op_div" bitfld.long 0x4 6. "O_ANA_PLL_OP_DIV_TM_SEL,op_div forced from test registers" "0,1" newline hexmask.long.byte 0x4 1.--5. 1. "O_ANA_PLL_IP_DIV_TM,forced value for ip_div" bitfld.long 0x4 0. "O_ANA_PLL_IP_DIV_TM_SEL,ip_div forced from test registers" "0,1" rgroup.long 0xB00++0xF line.long 0x0 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_PCS_TX_DIG_TBIT0,PHY_BAND_CONTROL" hexmask.long.byte 0x0 5.--9. 1. "BAND_CTL_REG_R,Data Rate [80_100] MHz" hexmask.long.byte 0x0 0.--4. 1. "BAND_CTL_REG_L,Data Rate [80_100] MHz" line.long 0x4 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_PCS_TX_DIG_TBIT1,PHY_PSM_CONFIG" hexmask.long.byte 0x4 1.--8. 1. "PSM_CLOCK_FREQ,psm_clock freq value" bitfld.long 0x4 0. "PSM_CLOCK_FREQ_EN,take psm_clock_freq from tbit" "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_PCS_TX_DIG_TBIT2,PHY_PI_PH2_DL_CONFIG" hexmask.long.byte 0x8 28.--31. 1. "POWER_SW_2_TIME_DL_R_3,power_sw_2_time_dl_r_3" hexmask.long.byte 0x8 24.--27. 1. "POWER_SW_2_TIME_DL_R_2,power_sw_2_time_dl_r_2" newline hexmask.long.byte 0x8 20.--23. 1. "POWER_SW_2_TIME_DL_R_1,power_sw_2_time_dl_r_1" hexmask.long.byte 0x8 16.--19. 1. "POWER_SW_2_TIME_DL_R_0,power_sw_2_time_dl_r_0" newline hexmask.long.byte 0x8 12.--15. 1. "POWER_SW_2_TIME_DL_L_3,power_sw_2_time_dl_l_3" hexmask.long.byte 0x8 8.--11. 1. "POWER_SW_2_TIME_DL_L_2,power_sw_2_time_dl_l_2" newline hexmask.long.byte 0x8 4.--7. 1. "POWER_SW_2_TIME_DL_L_1,power_sw_2_time_dl_l_1" hexmask.long.byte 0x8 0.--3. 1. "POWER_SW_2_TIME_DL_L_0,power_sw_2_time_dl_l_0" line.long 0xC "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_PCS_TX_DIG_TBIT3,PHY_PI_PH2_CL_CMN_CONFIG" hexmask.long.byte 0xC 8.--11. 1. "POWER_SW_2_TIME_CMN,power_sw_2_time_cmn" hexmask.long.byte 0xC 4.--7. 1. "POWER_SW_2_TIME_CL_R,power_sw_2_time_cl_r" newline hexmask.long.byte 0xC 0.--3. 1. "POWER_SW_2_TIME_CL_L,power_sw_2_time_cl_l" tree.end tree.end tree "DPHY_TX0 (DPHY_TX0)" base ad:0x4480000 rgroup.long 0x20++0x3 line.long 0x0 "WIZ16B8M4CDT_CMN0_CMN_DIG_TBIT2,CMN_DIG_TBIT2" bitfld.long 0x0 10. "CMN0_O_CMN_RX_MODE_EN,Enable CMN RX related StateMachines" "0,1" newline bitfld.long 0x0 9. "CMN0_O_CMN_TX_MODE_EN,Enable CMN TX related StateMachines" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CMN0_O_SSM_WAIT_BGCAL_EN,Wait time for Calibrations enable after bandgap is enabled (in us)" newline bitfld.long 0x0 0. "CMN0_O_CMN_SSM_EN,Enable CMN startup state machine" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "WIZ16B8M4CDT_CMN0_CMN_DIG_TBIT10,CMN_DIG_TBIT10" hexmask.long.byte 0x0 20.--27. 1. "CMN0_O_ANA_PLL_BYTECLK_DIV,Byteclk divider value" newline hexmask.long.word 0x0 10.--19. 1. "CMN0_O_ANA_PLL_GM_PWM_DIV_LOW,Low division value setting for the gm PWM control divider" newline hexmask.long.word 0x0 0.--9. 1. "CMN0_O_ANA_PLL_GM_PWM_DIV_HIGH,High division value setting for the gm PWM control divider" rgroup.long 0x4C++0x7 line.long 0x0 "WIZ16B8M4CDT_CMN0_CMN_DIG_TBIT13,CMN_DIG_TBIT13" hexmask.long.word 0x0 22.--31. 1. "CMN0_O_ANA_PLL_FB_DIV_LOW_TM,forced value for pll_fb_div_clk_low" newline bitfld.long 0x0 21. "CMN0_O_ANA_PLL_FB_DIV_LOW_TM_SEL,pll_fb_div_clk_low forced from test registers" "0,1" newline hexmask.long.word 0x0 11.--20. 1. "CMN0_O_ANA_PLL_FB_DIV_HIGH_TM,forced value for pll_fb_div_clk_high" newline bitfld.long 0x0 10. "CMN0_O_ANA_PLL_FB_DIV_HIGH_TM_SEL,pll_fb_div_clk_high forced from test registers" "0,1" line.long 0x4 "WIZ16B8M4CDT_CMN0_CMN_DIG_TBIT14,CMN_DIG_TBIT14" hexmask.long.byte 0x4 7.--12. 1. "CMN0_O_ANA_PLL_OP_DIV_TM,forced value for op_div" newline bitfld.long 0x4 6. "CMN0_O_ANA_PLL_OP_DIV_TM_SEL,op_div forced from test registers" "0,1" newline hexmask.long.byte 0x4 1.--5. 1. "CMN0_O_ANA_PLL_IP_DIV_TM,forced value for ip_div" newline bitfld.long 0x4 0. "CMN0_O_ANA_PLL_IP_DIV_TM_SEL,ip_div forced from test registers" "0,1" rgroup.long 0x154++0x3 line.long 0x0 "WIZ16B8M4CDT_CLK0_TX_DIG_TBIT14,digital to analog signals test muxing" bitfld.long 0x0 31. "CLK0_TM_ISO_EN,Enable isolation in test mode" "0,1" newline bitfld.long 0x0 30. "CLK0_TM_LOAD_DPDN_SEL,Take ana_dpdn_load from dig logic" "0,1" newline bitfld.long 0x0 27.--29. "CLK0_TM_LOAD_DPDN,set ana_dpdn_load as per requirement in test mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "CLK0_TM_HSTX_DATA_RATE_SEL,Take ana_hstx_datarate from dig logic" "0,1" newline bitfld.long 0x0 24.--25. "CLK0_TM_HSTX_DATE_RATE,set ana_hstx_datarate as per requirement in test mode" "0,1,2,3" newline bitfld.long 0x0 23. "CLK0_TM_BIST_ULP_RCV_EN_SEL,Take ana_bist_ulps_rcv_en from dig logic" "0,1" newline bitfld.long 0x0 22. "CLK0_TM_BIST_ULP_RCV_EN,set ana_bist_ulps_rcv_en to 0" "0,1" newline bitfld.long 0x0 21. "CLK0_TM_ULPS_PULDN_SEL,Take ana_ulps_puldn from dig logic" "0,1" newline bitfld.long 0x0 20. "CLK0_TM_ULPS_PULDN,set ana_ulps_puldn to 0" "0,1" newline bitfld.long 0x0 19. "CLK0_TM_BIST_SMPLR_CLK_EDGE_SEL,Take ana_bist_smplr_clkedge from dig logic" "0,1" newline bitfld.long 0x0 18. "CLK0_TM_BIST_SMPLR_CLK_EDGE,set ana_bist_smplr_clkedge to posedge" "0,1" newline bitfld.long 0x0 17. "CLK0_TM_BIST_EN_SEL,Take ana_bist_en from dig logic" "0,1" newline bitfld.long 0x0 16. "CLK0_TM_BIST_EN,set ana_bist_en to 0" "0,1" newline bitfld.long 0x0 15. "CLK0_TM_LPTX_TRST_SEL,Take ana_lptx_trst from dig logic" "0,1" newline bitfld.long 0x0 14. "CLK0_TM_LPTX_TRST,set ana_lptx_trst to 0" "0,1" newline bitfld.long 0x0 13. "CLK0_TM_LPTX_RST_SEL,Take ana_lptx_rst from dig logic" "0,1" newline bitfld.long 0x0 12. "CLK0_TM_LPTX_RST,set ana_lptx_rst to 0" "0,1" newline bitfld.long 0x0 11. "CLK0_TM_LPTX_DP_SEL,give output for LPTX DP from dig logic" "0,1" newline bitfld.long 0x0 10. "CLK0_TM_LPTX_DP,send 0 to LP TX Dp" "0,1" newline bitfld.long 0x0 9. "CLK0_TM_LPTX_DN_SEL,give output for LPTX DN from dig logic" "0,1" newline bitfld.long 0x0 8. "CLK0_TM_LPTX_DN,send 0 to LP TX Dn" "0,1" newline bitfld.long 0x0 7. "CLK0_TM_LDO_REF_EN_SEL,Take ana_ldo_ref_en from dig logic" "0,1" newline bitfld.long 0x0 6. "CLK0_TM_LDO_REF_EN,set ana_ldo_ref_en to 0" "0,1" newline bitfld.long 0x0 5. "CLK0_TM_HSTX_TRST_SEL,Take ana_hstx_trst from dig logic" "0,1" newline bitfld.long 0x0 4. "CLK0_TM_HSTX_TRST,set ana_hstx_trst to 0" "0,1" newline bitfld.long 0x0 3. "CLK0_TM_HSTX_RQST_SEL,Take ana_hstx_rqst from dig logic" "0,1" newline bitfld.long 0x0 2. "CLK0_TM_HSTX_RQST,set ana_hstx_rqst to 0" "0,1" newline bitfld.long 0x0 1. "CLK0_TM_GLOBAL_PD_SEL,Take ana_global_pd from dig logic" "0,1" newline bitfld.long 0x0 0. "CLK0_TM_GLOBAL_PD,set ana_global_pd to 0 (powered up)" "0,1" rgroup.long 0x26C++0x3 line.long 0x0 "WIZ16B8M4CDT_DL0_TX_DIG_TBIT20,digital to analog signal muxing" bitfld.long 0x0 31. "DL0_TM_ISO_EN,Enable isolation in test mode" "0,1" newline bitfld.long 0x0 30. "DL0_TM_LOAD_DPDN_SEL,Take ana_dpdn_load from dig logic" "0,1" newline bitfld.long 0x0 27.--29. "DL0_TM_LOAD_DPDN,set ana_dpdn_load as per requirement in test mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DL0_TM_HSTX_DATA_RATE_SEL,Take ana_hstx_datarate from dig logic" "0,1" newline bitfld.long 0x0 24.--25. "DL0_TM_HSTX_DATE_RATE,set ana_hstx_datarate as per requirement in test mode" "0,1,2,3" newline bitfld.long 0x0 23. "DL0_TM_BIST_ULP_RCV_EN_SEL,Take ana_bist_ulps_rcv_en from dig logic" "0,1" newline bitfld.long 0x0 22. "DL0_TM_BIST_ULP_RCV_EN,set ana_bist_ulps_rcv_en to 0" "0,1" newline bitfld.long 0x0 21. "DL0_TM_ULPS_PULDN_SEL,Take ana_ulps_puldn from dig logic" "0,1" newline bitfld.long 0x0 20. "DL0_TM_ULPS_PULDN,set ana_ulps_puldn to 0" "0,1" newline bitfld.long 0x0 19. "DL0_TM_BIST_SMPLR_CLK_EDGE_SEL,Take ana_bist_smplr_clkedge from dig logic" "0,1" newline bitfld.long 0x0 18. "DL0_TM_BIST_SMPLR_CLK_EDGE,set ana_bist_smplr_clkedge to posedge" "0,1" newline bitfld.long 0x0 17. "DL0_TM_BIST_EN_SEL,Take ana_bist_en from dig logic" "0,1" newline bitfld.long 0x0 16. "DL0_TM_BIST_EN,set ana_bist_en to 0" "0,1" newline bitfld.long 0x0 15. "DL0_TM_LPTX_TRST_SEL,Take ana_lptx_trst from dig logic" "0,1" newline bitfld.long 0x0 14. "DL0_TM_LPTX_TRST,set ana_lptx_trst to 0" "0,1" newline bitfld.long 0x0 13. "DL0_TM_LPTX_RST_SEL,Take ana_lptx_rst from dig logic" "0,1" newline bitfld.long 0x0 12. "DL0_TM_LPTX_RST,set ana_lptx_rst to 0" "0,1" newline bitfld.long 0x0 11. "DL0_TM_LPTX_DP_SEL,give output for LPTX DP from dig logic" "0,1" newline bitfld.long 0x0 10. "DL0_TM_LPTX_DP,send 0 to LP TX Dp" "0,1" newline bitfld.long 0x0 9. "DL0_TM_LPTX_DN_SEL,give output for LPTX DN from dig logic" "0,1" newline bitfld.long 0x0 8. "DL0_TM_LPTX_DN,send 0 to LP TX Dn" "0,1" newline bitfld.long 0x0 7. "DL0_TM_LDO_REF_EN_SEL,Take ana_ldo_ref_en from dig logic" "0,1" newline bitfld.long 0x0 6. "DL0_TM_LDO_REF_EN,set ana_ldo_ref_en to 0" "0,1" newline bitfld.long 0x0 5. "DL0_TM_HSTX_TRST_SEL,Take ana_hstx_trst from dig logic" "0,1" newline bitfld.long 0x0 4. "DL0_TM_HSTX_TRST,set ana_hstx_trst to 0" "0,1" newline bitfld.long 0x0 3. "DL0_TM_HSTX_RQST_SEL,Take ana_hstx_rqst from dig logic" "0,1" newline bitfld.long 0x0 2. "DL0_TM_HSTX_RQST,set ana_hstx_rqst to 0" "0,1" newline bitfld.long 0x0 1. "DL0_TM_GLOBAL_PD_SEL,Take ana_global_pd from dig logic" "0,1" newline bitfld.long 0x0 0. "DL0_TM_GLOBAL_PD,set ana_global_pd to 0 (powered up)" "0,1" rgroup.long 0x36C++0x3 line.long 0x0 "WIZ16B8M4CDT_DL1_TX_DIG_TBIT20,digital to analog signal muxing" bitfld.long 0x0 31. "DL1_TM_ISO_EN,Enable isolation in test mode" "0,1" newline bitfld.long 0x0 30. "DL1_TM_LOAD_DPDN_SEL,Take ana_dpdn_load from dig logic" "0,1" newline bitfld.long 0x0 27.--29. "DL1_TM_LOAD_DPDN,set ana_dpdn_load as per requirement in test mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DL1_TM_HSTX_DATA_RATE_SEL,Take ana_hstx_datarate from dig logic" "0,1" newline bitfld.long 0x0 24.--25. "DL1_TM_HSTX_DATE_RATE,set ana_hstx_datarate as per requirement in test mode" "0,1,2,3" newline bitfld.long 0x0 23. "DL1_TM_BIST_ULP_RCV_EN_SEL,Take ana_bist_ulps_rcv_en from dig logic" "0,1" newline bitfld.long 0x0 22. "DL1_TM_BIST_ULP_RCV_EN,set ana_bist_ulps_rcv_en to 0" "0,1" newline bitfld.long 0x0 21. "DL1_TM_ULPS_PULDN_SEL,Take ana_ulps_puldn from dig logic" "0,1" newline bitfld.long 0x0 20. "DL1_TM_ULPS_PULDN,set ana_ulps_puldn to 0" "0,1" newline bitfld.long 0x0 19. "DL1_TM_BIST_SMPLR_CLK_EDGE_SEL,Take ana_bist_smplr_clkedge from dig logic" "0,1" newline bitfld.long 0x0 18. "DL1_TM_BIST_SMPLR_CLK_EDGE,set ana_bist_smplr_clkedge to posedge" "0,1" newline bitfld.long 0x0 17. "DL1_TM_BIST_EN_SEL,Take ana_bist_en from dig logic" "0,1" newline bitfld.long 0x0 16. "DL1_TM_BIST_EN,set ana_bist_en to 0" "0,1" newline bitfld.long 0x0 15. "DL1_TM_LPTX_TRST_SEL,Take ana_lptx_trst from dig logic" "0,1" newline bitfld.long 0x0 14. "DL1_TM_LPTX_TRST,set ana_lptx_trst to 0" "0,1" newline bitfld.long 0x0 13. "DL1_TM_LPTX_RST_SEL,Take ana_lptx_rst from dig logic" "0,1" newline bitfld.long 0x0 12. "DL1_TM_LPTX_RST,set ana_lptx_rst to 0" "0,1" newline bitfld.long 0x0 11. "DL1_TM_LPTX_DP_SEL,give output for LPTX DP from dig logic" "0,1" newline bitfld.long 0x0 10. "DL1_TM_LPTX_DP,send 0 to LP TX Dp" "0,1" newline bitfld.long 0x0 9. "DL1_TM_LPTX_DN_SEL,give output for LPTX DN from dig logic" "0,1" newline bitfld.long 0x0 8. "DL1_TM_LPTX_DN,send 0 to LP TX Dn" "0,1" newline bitfld.long 0x0 7. "DL1_TM_LDO_REF_EN_SEL,Take ana_ldo_ref_en from dig logic" "0,1" newline bitfld.long 0x0 6. "DL1_TM_LDO_REF_EN,set ana_ldo_ref_en to 0" "0,1" newline bitfld.long 0x0 5. "DL1_TM_HSTX_TRST_SEL,Take ana_hstx_trst from dig logic" "0,1" newline bitfld.long 0x0 4. "DL1_TM_HSTX_TRST,set ana_hstx_trst to 0" "0,1" newline bitfld.long 0x0 3. "DL1_TM_HSTX_RQST_SEL,Take ana_hstx_rqst from dig logic" "0,1" newline bitfld.long 0x0 2. "DL1_TM_HSTX_RQST,set ana_hstx_rqst to 0" "0,1" newline bitfld.long 0x0 1. "DL1_TM_GLOBAL_PD_SEL,Take ana_global_pd from dig logic" "0,1" newline bitfld.long 0x0 0. "DL1_TM_GLOBAL_PD,set ana_global_pd to 0 (powered up)" "0,1" rgroup.long 0x46C++0x3 line.long 0x0 "WIZ16B8M4CDT_DL2_TX_DIG_TBIT20,digital to analog signal muxing" bitfld.long 0x0 31. "DL2_TM_ISO_EN,Enable isolation in test mode" "0,1" newline bitfld.long 0x0 30. "DL2_TM_LOAD_DPDN_SEL,Take ana_dpdn_load from dig logic" "0,1" newline bitfld.long 0x0 27.--29. "DL2_TM_LOAD_DPDN,set ana_dpdn_load as per requirement in test mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DL2_TM_HSTX_DATA_RATE_SEL,Take ana_hstx_datarate from dig logic" "0,1" newline bitfld.long 0x0 24.--25. "DL2_TM_HSTX_DATE_RATE,set ana_hstx_datarate as per requirement in test mode" "0,1,2,3" newline bitfld.long 0x0 23. "DL2_TM_BIST_ULP_RCV_EN_SEL,Take ana_bist_ulps_rcv_en from dig logic" "0,1" newline bitfld.long 0x0 22. "DL2_TM_BIST_ULP_RCV_EN,set ana_bist_ulps_rcv_en to 0" "0,1" newline bitfld.long 0x0 21. "DL2_TM_ULPS_PULDN_SEL,Take ana_ulps_puldn from dig logic" "0,1" newline bitfld.long 0x0 20. "DL2_TM_ULPS_PULDN,set ana_ulps_puldn to 0" "0,1" newline bitfld.long 0x0 19. "DL2_TM_BIST_SMPLR_CLK_EDGE_SEL,Take ana_bist_smplr_clkedge from dig logic" "0,1" newline bitfld.long 0x0 18. "DL2_TM_BIST_SMPLR_CLK_EDGE,set ana_bist_smplr_clkedge to posedge" "0,1" newline bitfld.long 0x0 17. "DL2_TM_BIST_EN_SEL,Take ana_bist_en from dig logic" "0,1" newline bitfld.long 0x0 16. "DL2_TM_BIST_EN,set ana_bist_en to 0" "0,1" newline bitfld.long 0x0 15. "DL2_TM_LPTX_TRST_SEL,Take ana_lptx_trst from dig logic" "0,1" newline bitfld.long 0x0 14. "DL2_TM_LPTX_TRST,set ana_lptx_trst to 0" "0,1" newline bitfld.long 0x0 13. "DL2_TM_LPTX_RST_SEL,Take ana_lptx_rst from dig logic" "0,1" newline bitfld.long 0x0 12. "DL2_TM_LPTX_RST,set ana_lptx_rst to 0" "0,1" newline bitfld.long 0x0 11. "DL2_TM_LPTX_DP_SEL,give output for LPTX DP from dig logic" "0,1" newline bitfld.long 0x0 10. "DL2_TM_LPTX_DP,send 0 to LP TX Dp" "0,1" newline bitfld.long 0x0 9. "DL2_TM_LPTX_DN_SEL,give output for LPTX DN from dig logic" "0,1" newline bitfld.long 0x0 8. "DL2_TM_LPTX_DN,send 0 to LP TX Dn" "0,1" newline bitfld.long 0x0 7. "DL2_TM_LDO_REF_EN_SEL,Take ana_ldo_ref_en from dig logic" "0,1" newline bitfld.long 0x0 6. "DL2_TM_LDO_REF_EN,set ana_ldo_ref_en to 0" "0,1" newline bitfld.long 0x0 5. "DL2_TM_HSTX_TRST_SEL,Take ana_hstx_trst from dig logic" "0,1" newline bitfld.long 0x0 4. "DL2_TM_HSTX_TRST,set ana_hstx_trst to 0" "0,1" newline bitfld.long 0x0 3. "DL2_TM_HSTX_RQST_SEL,Take ana_hstx_rqst from dig logic" "0,1" newline bitfld.long 0x0 2. "DL2_TM_HSTX_RQST,set ana_hstx_rqst to 0" "0,1" newline bitfld.long 0x0 1. "DL2_TM_GLOBAL_PD_SEL,Take ana_global_pd from dig logic" "0,1" newline bitfld.long 0x0 0. "DL2_TM_GLOBAL_PD,set ana_global_pd to 0 (powered up)" "0,1" rgroup.long 0x56C++0x3 line.long 0x0 "WIZ16B8M4CDT_DL3_TX_DIG_TBIT20,digital to analog signal muxing" bitfld.long 0x0 31. "DL3_TM_ISO_EN,Enable isolation in test mode" "0,1" newline bitfld.long 0x0 30. "DL3_TM_LOAD_DPDN_SEL,Take ana_dpdn_load from dig logic" "0,1" newline bitfld.long 0x0 27.--29. "DL3_TM_LOAD_DPDN,set ana_dpdn_load as per requirement in test mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DL3_TM_HSTX_DATA_RATE_SEL,Take ana_hstx_datarate from dig logic" "0,1" newline bitfld.long 0x0 24.--25. "DL3_TM_HSTX_DATE_RATE,set ana_hstx_datarate as per requirement in test mode" "0,1,2,3" newline bitfld.long 0x0 23. "DL3_TM_BIST_ULP_RCV_EN_SEL,Take ana_bist_ulps_rcv_en from dig logic" "0,1" newline bitfld.long 0x0 22. "DL3_TM_BIST_ULP_RCV_EN,set ana_bist_ulps_rcv_en to 0" "0,1" newline bitfld.long 0x0 21. "DL3_TM_ULPS_PULDN_SEL,Take ana_ulps_puldn from dig logic" "0,1" newline bitfld.long 0x0 20. "DL3_TM_ULPS_PULDN,set ana_ulps_puldn to 0" "0,1" newline bitfld.long 0x0 19. "DL3_TM_BIST_SMPLR_CLK_EDGE_SEL,Take ana_bist_smplr_clkedge from dig logic" "0,1" newline bitfld.long 0x0 18. "DL3_TM_BIST_SMPLR_CLK_EDGE,set ana_bist_smplr_clkedge to posedge" "0,1" newline bitfld.long 0x0 17. "DL3_TM_BIST_EN_SEL,Take ana_bist_en from dig logic" "0,1" newline bitfld.long 0x0 16. "DL3_TM_BIST_EN,set ana_bist_en to 0" "0,1" newline bitfld.long 0x0 15. "DL3_TM_LPTX_TRST_SEL,Take ana_lptx_trst from dig logic" "0,1" newline bitfld.long 0x0 14. "DL3_TM_LPTX_TRST,set ana_lptx_trst to 0" "0,1" newline bitfld.long 0x0 13. "DL3_TM_LPTX_RST_SEL,Take ana_lptx_rst from dig logic" "0,1" newline bitfld.long 0x0 12. "DL3_TM_LPTX_RST,set ana_lptx_rst to 0" "0,1" newline bitfld.long 0x0 11. "DL3_TM_LPTX_DP_SEL,give output for LPTX DP from dig logic" "0,1" newline bitfld.long 0x0 10. "DL3_TM_LPTX_DP,send 0 to LP TX Dp" "0,1" newline bitfld.long 0x0 9. "DL3_TM_LPTX_DN_SEL,give output for LPTX DN from dig logic" "0,1" newline bitfld.long 0x0 8. "DL3_TM_LPTX_DN,send 0 to LP TX Dn" "0,1" newline bitfld.long 0x0 7. "DL3_TM_LDO_REF_EN_SEL,Take ana_ldo_ref_en from dig logic" "0,1" newline bitfld.long 0x0 6. "DL3_TM_LDO_REF_EN,set ana_ldo_ref_en to 0" "0,1" newline bitfld.long 0x0 5. "DL3_TM_HSTX_TRST_SEL,Take ana_hstx_trst from dig logic" "0,1" newline bitfld.long 0x0 4. "DL3_TM_HSTX_TRST,set ana_hstx_trst to 0" "0,1" newline bitfld.long 0x0 3. "DL3_TM_HSTX_RQST_SEL,Take ana_hstx_rqst from dig logic" "0,1" newline bitfld.long 0x0 2. "DL3_TM_HSTX_RQST,set ana_hstx_rqst to 0" "0,1" newline bitfld.long 0x0 1. "DL3_TM_GLOBAL_PD_SEL,Take ana_global_pd from dig logic" "0,1" newline bitfld.long 0x0 0. "DL3_TM_GLOBAL_PD,set ana_global_pd to 0 (powered up)" "0,1" rgroup.long 0xB00++0x7 line.long 0x0 "WIZ16B8M4CDT_PCS_TX_DIG_TBIT0,PHY_BAND_CONTROL" hexmask.long.byte 0x0 5.--9. 1. "PCS_BAND_CTL_REG_R,Data Rate 80_100 MHz" newline hexmask.long.byte 0x0 0.--4. 1. "PCS_BAND_CTL_REG_L,Data Rate 80_100 MHz" line.long 0x4 "WIZ16B8M4CDT_PCS_TX_DIG_TBIT1,PHY_PSM_CONFIG" hexmask.long.byte 0x4 1.--8. 1. "PCS_PSM_CLOCK_FREQ,psm_clock freq value" newline bitfld.long 0x4 0. "PCS_PSM_CLOCK_FREQ_EN,take psm_clock_freq from tbit" "0,1" rgroup.long 0xF00++0x3 line.long 0x0 "WIZ16B8M4CDT_MOD_VER,The Module and Version Register identifies the module identifier and revision of the WIZ16B8M4CDT module." bitfld.long 0x0 30.--31. "SCHEME,Module Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Module Business Unit" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,WIZ16B8M4CDT module ID." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VERSION,RTL Version." newline bitfld.long 0x0 8.--10. "MAJOR_REVISION,Major Revision." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM_REVISION,Custom Revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REVISION,Minor Revision." rgroup.long 0xF04++0x3 line.long 0x0 "WIZ16B8M4CDT_PLL_CTRL,Sets the PLL info." rbitfld.long 0x0 31. "PLL_LOCK,Signal to indicate that PLL has got locked. 1: PLL locked to required frequency 0: PLL not yet locked" "0: PLL not yet locked,1: PLL locked to required frequency" newline bitfld.long 0x0 30. "PSO_DISABLE,Disables the ability to switch off the analog switched power islands in the lane when in the ultra-low power state" "0,1" newline bitfld.long 0x0 29. "PLL_PSO,Power Shut Off signal for PLL 1: PLL shutoff 0: PLL power ON" "0: PLL power ON,1: PLL shutoff" newline bitfld.long 0x0 28. "PLL_PD,Power down signal for PLL (Does not switch off the PLL supply) 1: PLL is powered down 0: PLL is active" "0: PLL is active,1: PLL is powered down" newline hexmask.long.word 0x0 16.--25. 1. "PLL_FBDIV,DPHY TX PLL VCO Feedback Divider ratio. Feedback divider value = ROUND ((Data Rate * 2 * pll_opdiv * pll_ipdiv) / PLL reference clock frequency)" newline hexmask.long.byte 0x0 8.--13. 1. "PLL_OPDIV,DPHY TX PLL OUTCLK Divider ratio.
6'h01: Div by 1 2.5 Gbps - 1.25 Gbps
6'h02: Div by 2 1.24 Gbps - 630 Mbps
6'h04: Div by 4 620 Mbps - 320 Mbps
6'h08: Div by 8 310 Mbps - 160 Mbps
6'h10: Div by 16 150 Mbps - 80 Mbps" newline hexmask.long.byte 0x0 0.--4. 1. "PLL_IPDIV,DPHY TX PLL REFCLK Input Divider ratio.
5'h01: Div by 1 9.6 MHz - <19.2 MHz
5'h02: Div by 2 19.2 MHz - <38.4 MHz
5'h04: Div by 4 38.4 MHz - < 76.8 MHz
5'h08: Div by 8 76.8 MHz - < 150 MHz" rgroup.long 0xF08++0x3 line.long 0x0 "WIZ16B8M4CDT_STATUS,The status register reports status of the DPHYTS sub module." bitfld.long 0x0 31. "O_CMN_READY,System Should check this during Power up Initialisation" "0,1" newline bitfld.long 0x0 2. "O_SUPPLY_CORE_PG,The indicates the core supply is good." "0,1" newline bitfld.long 0x0 1. "O_SUPPLY_IO_PG,The indicates the IO supply is good." "0,1" rgroup.long 0xF0C++0xB line.long 0x0 "WIZ16B8M4CDT_RST_CTRL,Sets the RST info." bitfld.long 0x0 31. "LANE_RSTB_CMN,DPHY System Reset for Common Module - required to be released after APB register programming; See DPHY PMA specification for details of DPHY power up sequence" "0,1" line.long 0x4 "WIZ16B8M4CDT_PSM_FREQ,The PSM Frequency register configures the so that it knows hoe fast the PSM clock is." hexmask.long.byte 0x4 0.--7. 1. "PSM_CLOCK_FREQ,Static value based on System PSM clock frequency. The signal must be driven with a value such that the internal psm frequency of the divided psm clock is 1 MHz" line.long 0x8 "WIZ16B8M4CDT_IPCONFIG," bitfld.long 0x8 31. "PSO_CMN,Power Shutoff signal for CMN 1: CMN is power OFF 0: CMN is power ON" "0: CMN is power ON,1: CMN is power OFF" newline bitfld.long 0x8 0.--2. "IPCONFIG_CMN,This signal decides which clock lane acts as master clock lane to all data lanes. Needed only for RXIP. Bit[2]: Reserved CASE {Bit[1] Bit[0]}: 00: Left RX clk lane provides clock to all left and right data lanes. 01: Left RX clk lane.." "0: Left RX clk lane provides clock to all left and..,1: Left RX clk lane provides clock to all right..,?,?,?,?,?,?" rgroup.long 0xFF8++0x7 line.long 0x0 "WIZ16B8M4CDT_PLLRES,The PLL Reserved register is not being used currently" hexmask.long.byte 0x0 0.--7. 1. "PLLREFSEL_CMN,PLL frequency range. This signal is not being used currently. Should be 8'd0" line.long 0x4 "WIZ16B8M4CDT_DIAG_TEST,The Diagnostic Test Register allows the system to validate the read and write of all data bits." hexmask.long 0x4 0.--31. 1. "DIAG_REG,Diagnostic register." tree.end tree.end tree "DSS" base ad:0x0 tree "DSS_DSI0_DSI" tree "DSS_DSI0_DSI_TOP" tree "DSS_DSI0_DSI_TOP_ECC_AGGR_SYS_CFG (DSS_DSI0_DSI_TOP_ECC_AGGR_SYS_CFG)" base ad:0x4700000 rgroup.long 0x0++0x3 line.long 0x0 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "EDC_CTRL_SYS_PEND,Interrupt Pending Status for edc_ctrl_sys_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "EDC_CTRL_SYS_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_sys_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "EDC_CTRL_SYS_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_sys_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "EDC_CTRL_SYS_PEND,Interrupt Pending Status for edc_ctrl_sys_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "EDC_CTRL_SYS_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_sys_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "EDC_CTRL_SYS_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_sys_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "DSS_DSI0_DSI_TOP_VBUSP_CFG_DSI_0_DSI (DSS_DSI0_DSI_TOP_VBUSP_CFG_DSI_0_DSI)" base ad:0x4800000 rgroup.long 0x0++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_ip_conf,IP Configuration for Controller" bitfld.long 0x0 31. "ASF_CONFIG,Active Safety Features [ASF] Configuration: 0 = None; 1 = Full ASF." "0: None;,1: Full ASF" newline hexmask.long.byte 0x0 26.--30. 1. "SP_HS_FIFO_DEPTH,SP_HS_FIFO_DEPTH : HS FIFO depth in sending path." newline hexmask.long.byte 0x0 21.--25. 1. "SP_LP_FIFO_DEPTH,SP_LP_FIFO_DEPTH : LP FIFO depth in sending path." newline hexmask.long.byte 0x0 16.--20. 1. "VRS_FIFO_DEPTH,VRS_FIFO_DEPTH : FIFO depth in the VRS block." newline bitfld.long 0x0 13.--15. "DIRCMD_FIFO_DEPTH,Direct Command FIFO Depth [2:0]. Depth in bytes = 2^[value+2]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12. "INTERFACE_DATASIZE,SDI interface data width: 0 = 16 bit 1 = 32bit" "0,1" newline bitfld.long 0x0 10.--11. "DATAPATH_SIZE,Internal Datapath.width 00 - 32 bit 01 - 16bit 11 - 8 Bits." "0,1,2,3" newline bitfld.long 0x0 8.--9. "NUM_INTERFACE,Max Number of SDI interfaces [1-4] = [value+1]" "0,1,2,3" newline bitfld.long 0x0 6.--7. "MAX_LANE_NB,Max Number of Lanes [1-4] = [value+1]" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "RX_FIFO_DEPTH,RX FIFO Depth [5:0]" rgroup.long 0x4++0x1F line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_main_data_ctl,Main Control - main control setting for datapath" bitfld.long 0x0 25. "TE_MIPI_POLLING_EN,TE_MIPI_POLLING_EN: enables TE Polling feature following MIPI recommendations [polling by software]" "0,1" newline bitfld.long 0x0 24. "TE_HW_POLLING_EN,TE_HW_POLLING_EN: enables TE Polling feature following internal solution" "0,1" newline bitfld.long 0x0 18. "DISP_EOT_GEN,DISP_EOT_GEN: display adds an EOT packet to its LPDT transfers" "0,1" newline bitfld.long 0x0 17. "HOST_EOT_GEN,HOST_EOT_GEN: generates or not the EOT packet after a transfer in HS." "0,1" newline bitfld.long 0x0 16. "DISP_GEN_CHECKSUM,DISP_GEN_CHECKSUM: display generates checksum on its response packets." "0,1" newline bitfld.long 0x0 15. "DISP_GEN_ECC,DISP_GEN_ECC: display generates ECC on its response packets" "0,1" newline bitfld.long 0x0 14. "BTA_EN,BTA_EN: enables BTA" "0,1" newline bitfld.long 0x0 13. "READ_EN,READ_EN: enables read operation" "0,1" newline bitfld.long 0x0 12. "REG_TE_EN,REG_TE_EN: enables Tearing Effect from register" "0,1" newline bitfld.long 0x0 10. "SPLIT_PANEL_MODE,SPLIT_PANEL_MODE: when enabled DSC stage controls data for split panel signle DPHY link" "0,1" newline bitfld.long 0x0 9. "IF3_TE_EN,IF3_TE_EN: enables Tearing Effect on interface 3. Note TE on all SDI interfaces is not supported and should be avoided" "0,1" newline bitfld.long 0x0 8. "IF1_TE_EN,IF1_TE_EN: enables Tearing Effect on interface 1. Note TE on all SDI interfaces is not supported and should be avoided" "0,1" newline bitfld.long 0x0 6. "TVG_SEL,TVG_SEL: Test Video Generator is enabled [it is not the start signal!] - should not be set if if1_en = 1 and if1_mode = 1 [see MCTL_MAIN_EN register ]" "0,1" newline bitfld.long 0x0 5. "VID_EN,VID_EN: enables the video stream generator" "0,1" newline bitfld.long 0x0 2.--3. "VID_IF_SELECT,VID_IF_SELECT: Determines which video interface is active [00 : SDI 01 : DPI 10 : DSC]" "0: SDI,1: DPI,?,?" newline bitfld.long 0x0 1. "SDI_IF_VID_MODE,SDI_IF_VID_MODE:1: selected interface is in video mode 0: selected interface is in command mode]" "0: selected interface is in command mode],1: selected interface is in video mode" newline bitfld.long 0x0 0. "LINK_EN,LINK_EN: enables [or not] the link]" "0,1" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_main_phy_ctl,Main control setting for the physical lanes and drive the static signals for D-PHY clock lane" bitfld.long 0x4 30. "HS_SKEWCAL_TIMEOUT_EN,HS_SKEWCAL_TIMEOUT_EN: Activate the HS SkewCal Control to occur after a timeout." "0,1" newline bitfld.long 0x4 29. "HS_SKEWCAL_FORCE_EN,HS_SKEWCAL_FORCE_EN: Force the HS SkewCal Control to occur immediately" "0,1" newline bitfld.long 0x4 28. "HS_SKEWCAL_EN,HS_SKEWCAL_EN: activate the HS SkewCal Control at start of HS Transmission" "0,1" newline bitfld.long 0x4 25. "HS_INVERT_DAT4,HS_INVERT_DAT4: invert HS signal on data lane 4" "0,1" newline bitfld.long 0x4 24. "SWAP_PINS_DAT4,SWAP_PINS_DAT4: swap pins on clock lane 4" "0,1" newline bitfld.long 0x4 23. "HS_INVERT_DAT3,HS_INVERT_DAT3: invert HS signal on data lane 3" "0,1" newline bitfld.long 0x4 22. "SWAP_PINS_DAT3,SWAP_PINS_DAT3: swap pins on clock lane 3" "0,1" newline bitfld.long 0x4 21. "HS_INVERT_DAT2,HS_INVERT_DAT2: invert HS signal on data lane 2" "0,1" newline bitfld.long 0x4 20. "SWAP_PINS_DAT2,SWAP_PINS_DAT2: swap pins on clock lane 2" "0,1" newline bitfld.long 0x4 19. "HS_INVERT_DAT1,HS_INVERT_DAT1: invert HS signal on data lane 1" "?,1: invert HS signal on data lane 1" newline bitfld.long 0x4 18. "SWAP_PINS_DAT1,SWAP_PINS_DAT1: swap pins on data lane 1" "?,1: swap pins on data lane 1" newline bitfld.long 0x4 17. "HS_INVERT_CLK,HS_INVERT_CLK: invert HS signal on clock lane" "0,1" newline bitfld.long 0x4 16. "SWAP_PINS_CLK,SWAP_PINS_CLK: swap pins on clock lane" "0,1" newline hexmask.long.byte 0x4 10.--13. 1. "WAIT_BURST_TIME,WAIT_BURST_TIME: delay to respect between two HS bursts. Value 0 is forbidden" newline bitfld.long 0x4 9. "DAT4_ULPM_EN,DAT4_ULPM_EN: data lane 4 can be switched in ULP mode" "0,1" newline bitfld.long 0x4 8. "DAT3_ULPM_EN,DAT3_ULPM_EN: data lane 3 can be switched in ULP mode" "0,1" newline bitfld.long 0x4 7. "DAT2_ULPM_EN,DAT2_ULPM_EN: data lane 2 can be switched in ULP mode" "0,1" newline bitfld.long 0x4 6. "DAT1_ULPM_EN,DAT1_ULPM_EN: data lane 1 can be switched in ULP mode" "0,1" newline bitfld.long 0x4 5. "CLK_ULPM_EN,CLK_ULPM_EN: specifies that clock lane can be switched in ULP mode [on demand]" "0,1" newline bitfld.long 0x4 4. "CLK_CONTINUOUS,CLK_CONTINUOUS: clock lane should remain in HS sending mode [no return in STOP state]" "0,1" newline bitfld.long 0x4 2. "LANE4_EN,LANE4_EN: enables the fourth lane [ controls DCB FSM]" "0,1" newline bitfld.long 0x4 1. "LANE3_EN,LANE3_EN: enables the third lane [ controls DCB FSM]" "0,1" newline bitfld.long 0x4 0. "LANE2_EN,LANE2_EN: enables the second lane [ controls DCB FSM]" "0,1" line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_main_en,Control start/stop of the DSI link" bitfld.long 0x8 17. "FORCE_STOP_MODE,FORCE_STOP_MODE: when enabled data lanes are forced back in STOP mode - this value should remain asserted for 10 us minimum" "0,1" newline bitfld.long 0x8 16. "CLK_FORCE_STOP,CLK_FORCE_STOP : force clock lanes back in STOP mode - this value should remain asserted for 10 us minimum" "0,1" newline bitfld.long 0x8 15. "IF3_EN,IF3_EN: enables DSC interface [i.e. removes stall signal]" "0,1" newline bitfld.long 0x8 14. "IF2_EN,IF2_EN: enables DPI interface [i.e. removes stall signal]" "0,1" newline bitfld.long 0x8 13. "IF1_EN,IF1_EN: enables SDI interface [i.e. removes stall signal]" "0,1" newline bitfld.long 0x8 12. "DAT4_ULPM_REQ,DAT4_ULPM_REQ: switches data lane 4 in ULP mode" "0,1" newline bitfld.long 0x8 11. "DAT3_ULPM_REQ,DAT3_ULPM_REQ: switches data lane 3 in ULP mode" "0,1" newline bitfld.long 0x8 10. "DAT2_ULPM_REQ,DAT2_ULPM_REQ: switches data lane 2 in ULP mode" "0,1" newline bitfld.long 0x8 9. "DAT1_ULPM_REQ,DAT1_ULPM_REQ: switches data lane 1 in ULP mode" "0,1" newline bitfld.long 0x8 8. "CLKLANE_ULPM_REQ,CLKLANE_ULPM_REQ: switches clock lane in ULP mode" "0,1" newline bitfld.long 0x8 7. "DAT4_EN,DAT4_EN: 1: starts data lane 4 [FSM data lane 4 is stuck in start mode if 0]" "?,1: starts data lane 4 [FSM data lane 4 is stuck in.." newline bitfld.long 0x8 6. "DAT3_EN,DAT3_EN: 1: starts data lane 3 [FSM data lane 3 is stuck in start mode if 0]" "?,1: starts data lane 3 [FSM data lane 3 is stuck in.." newline bitfld.long 0x8 5. "DAT2_EN,DAT2_EN: 1: starts data lane 2 [FSM data lane 2 is stuck in start mode if 0]" "?,1: starts data lane 2 [FSM data lane 2 is stuck in.." newline bitfld.long 0x8 4. "DAT1_EN,DAT1_EN: 1: starts data lane 1 [FSM data lane 1 is stuck in start mode if 0]" "?,1: starts data lane 1 [FSM data lane 1 is stuck in.." newline bitfld.long 0x8 3. "CKLANE_EN,CKLANE_EN: 1: starts the clock lane" "?,1: starts the clock lane" newline bitfld.long 0x8 0. "PLL_START,PLL_START: enables the PLL [when set the PLL is started]" "0,1" line.long 0xC "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_dphy_cfg0,DPHY Power and Reset Control" bitfld.long 0xC 20. "DPHY_C_RSTB,Drives dphy_c_rstb output" "0,1" newline hexmask.long.byte 0xC 16.--19. 1. "DPHY_D_RSTB,Drives dphy_d_rstb output" newline bitfld.long 0xC 10. "DPHY_PLL_PDN,Drives dphy_pll_pdn output" "0,1" newline bitfld.long 0xC 9. "DPHY_CMN_PDN,Drives dphy_cmn_pdn output" "0,1" newline bitfld.long 0xC 8. "DPHY_C_PDN,Drives dphy_c_pdn output" "0,1" newline hexmask.long.byte 0xC 4.--7. 1. "DPHY_D_PDN,Drives dphy_d_pdn output" newline bitfld.long 0xC 1. "DPHY_PLL_PSO,Drives dphy_pll_pso output" "0,1" newline bitfld.long 0xC 0. "DPHY_CMN_PSO,Drives dphy_cmn_pso output" "0,1" line.long 0x10 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_dphy_timeout1,Main DPHY time-out settings. To better understand the way this register is used. please refer to Section :" hexmask.long.tbyte 0x10 4.--21. 1. "HSTX_TO_VAL,HSTX_TO_VAL: HS TX time-out detection value" newline hexmask.long.byte 0x10 0.--3. 1. "CLK_DIV,CLK_DIV: clock division ratio" line.long 0x14 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_dphy_timeout2,To better understand the way this register is used. please refer to Section : DSI checks (DC) - the counters are on tx_byte_hs_clk and not on sys_clk" hexmask.long.tbyte 0x14 0.--17. 1. "LPRX_TO_VAL,LPRX_TO_VAL: LP RX time-out detection value" line.long 0x18 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_ulpout_time,Specify time to leave ULP mode. The time-out is reached when the ulpout counter reaches 1000x xxx_ulpout_time and is based upon the system clock" hexmask.long.word 0x18 9.--17. 1. "DATA_ULPOUT_TIME,DATA_ULPOUT_TIME: specify what the duration is to leave ULP mode is [for data lane[s] in system clock cycles" newline hexmask.long.word 0x18 0.--8. 1. "CKLANE_ULPOUT_TIME,CKLANE_ULPOUT_TIME: specify what the duration is to leave ULP mode is [for clock lane] in system clock cycles" line.long 0x1C "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_3dvideo_ctl,3D Video mode stream control" bitfld.long 0x1C 7. "VID_VSYNC_3D_EN,VID_VSYNC_3D_EN: Enable 3D Control this selects the 3D operation for VSYNC and video data control" "0,1" newline bitfld.long 0x1C 5. "VID_VSYNC_3D_LR,VID_VSYNC_3D_LR: When 3D mode is enabled this allows to choose which field to start the video stream '0' - Data is sent Left first then right '1' - Data is sent Right first then left" "0,1" newline bitfld.long 0x1C 4. "VID_VSYNC_3D_SECOND_EN,VID_VSYNC_3D_SECOND_EN: When 3D mode is enabled this allows to choose if a second VSYNC is enabled between L and R images '0' - No sync pulses between left and right data '1' - Sync pulse [HSYNC .." "0,1" newline bitfld.long 0x1C 2.--3. "VID_VSYNC_3DFORMAT,VID_VSYNC_3DFORMAT: video 3D Format for VSYNC Control Parameter1 '00' - Line Format alternating line of left and right data '01' - Frame Format alternating frames of left and right data '10'.." "0,1,2,3" newline bitfld.long 0x1C 0.--1. "VID_VSYNC_3DMODE,VID_VSYNC_3DMODE: video 3D mode for VSYNC Control Parameter1 '00' - 3D mode Off - 2D Mode only '01' - 3D On - Portrait Orientation '10' - 3D On - Landscape Orientation '11' - Reserved" "0,1,2,3" rgroup.long 0x24++0xB line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_main_sts,Status of the DSI link" bitfld.long 0x0 11. "HS_SKEWCAL_DONE,HS_SKEWCAL_DONE: HS SkewCal Control Done at start of HS Transmission" "0,1" newline bitfld.long 0x0 10. "IF3_UNTERM_PCK,IF3_UNTERM_PCK: Indicates an unterminated packet on DSC interface" "0,1" newline bitfld.long 0x0 9. "IF2_UNTERM_PCK,IF2_UNTERM_PCK: Indicates an unterminated packet on DPI interface" "0,1" newline bitfld.long 0x0 8. "IF1_UNTERM_PCK,IF1_UNTERM_PCK: Indicates an unterminated packet on SDI Interface" "0,1" newline bitfld.long 0x0 7. "LPRX_TO_ERR,LPRX_TO_ERR: Indicates an LP_RX time-out error" "0,1" newline bitfld.long 0x0 6. "HSTX_TO_ERR,HSTX_TO_ERR: Indicates an HS_TX time-out error" "0,1" newline bitfld.long 0x0 5. "DAT4_READY,DAT4_READY: Indicates data lane 4 is ready" "0,1" newline bitfld.long 0x0 4. "DAT3_READY,DAT3_READY: Indicates data lane 3 is ready" "0,1" newline bitfld.long 0x0 3. "DAT2_READY,DAT2_READY: Indicates data lane 2 is ready" "0,1" newline bitfld.long 0x0 2. "DAT1_READY,DAT1_READY: Indicates data lane 1 is ready" "0,1" newline bitfld.long 0x0 1. "CLKLANE_READY,CLKLANE_READY: Indicates the clock lane is ready [normal DSI operation can start]" "0,1" newline bitfld.long 0x0 0. "PLL_LCK,PLL_LCK: Indicates PLL is locked - data coming from DCB [if DSI link is PLL master] or copy of pll_en [if DSI link is slave]" "0,1" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_dphy_err,Errors reported from DPHY lanes - See description in DPHY inputs and outputs" bitfld.long 0x4 25. "ERR_CONT_LP1_4,ERR_CONT_LP1_4" "0,1" newline bitfld.long 0x4 24. "ERR_CONT_LP1_3,ERR_CONT_LP1_3" "0,1" newline bitfld.long 0x4 23. "ERR_CONT_LP1_2,ERR_CONT_LP1_2" "0,1" newline bitfld.long 0x4 22. "ERR_CONT_LP1_1,ERR_CONT_LP1_1" "0,1" newline bitfld.long 0x4 21. "ERR_CONT_LP0_4,ERR_CONT_LP0_4" "0,1" newline bitfld.long 0x4 20. "ERR_CONT_LP0_3,ERR_CONT_LP0_3" "0,1" newline bitfld.long 0x4 19. "ERR_CONT_LP0_2,ERR_CONT_LP0_2" "0,1" newline bitfld.long 0x4 18. "ERR_CONT_LP0_1,ERR_CONT_LP0_1" "0,1" newline bitfld.long 0x4 17. "ERR_CONTROL_4,ERR_CONTROL_4" "0,1" newline bitfld.long 0x4 16. "ERR_CONTROL_3,ERR_CONTROL_3" "0,1" newline bitfld.long 0x4 15. "ERR_CONTROL_2,ERR_CONTROL_2" "0,1" newline bitfld.long 0x4 14. "ERR_CONTROL_1,ERR_CONTROL_1" "0,1" newline bitfld.long 0x4 13. "ERR_SYNCESC_4,ERR_SYNCESC_4" "0,1" newline bitfld.long 0x4 12. "ERR_SYNCESC_3,ERR_SYNCESC_3" "0,1" newline bitfld.long 0x4 11. "ERR_SYNCESC_2,ERR_SYNCESC_2" "0,1" newline bitfld.long 0x4 10. "ERR_SYNCESC_1,ERR_SYNCESC_1" "0,1" newline bitfld.long 0x4 9. "ERR_ESC_4,ERR_ESC_4" "0,1" newline bitfld.long 0x4 8. "ERR_ESC_3,ERR_ESC_3" "0,1" newline bitfld.long 0x4 7. "ERR_ESC_2,ERR_ESC_2" "0,1" newline bitfld.long 0x4 6. "ERR_ESC_1,ERR_ESC_1" "0,1" line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_lane_sts,DPHY Lane and PLL status information" bitfld.long 0x8 18. "PPI_C_TX_READY_HS,Value of ppi_c_tx_ready_hs input" "0,1" newline bitfld.long 0x8 17. "DPHY_PLL_LOCK,Value of dphy_pll_lock input" "0,1" newline hexmask.long.byte 0x8 12.--15. 1. "PPI_D_RX_ULPS_ESC,Value of ppi_d_rx_ulps_esc input" newline bitfld.long 0x8 9.--10. "DATLANE4_STATE,DATLANE4_STATE: state of the data lane 4 [00: start / 01: idle / 10: write / 11: ULPM]" "0: start /,1: idle /,?,?" newline bitfld.long 0x8 7.--8. "DATLANE3_STATE,DATLANE3_STATE: state of the data lane 3 [00: start / 01: idle / 10: write / 11: ULPM]" "0: start /,1: idle /,?,?" newline bitfld.long 0x8 5.--6. "DATLANE2_STATE,DATLANE2_STATE: state of the data lane 2 [00: start / 01: idle / 10: write / 11: ULPM]" "0: start /,1: idle /,?,?" newline bitfld.long 0x8 2.--4. "DATLANE1_STATE,DATLANE1_STATE: state of the data lane 1 [000: start / 001: idle / 010: write / 011: ULPM / 100: read]" "0: start /,1: idle /,?,?,?,?,?,?" newline bitfld.long 0x8 0.--1. "CLKLANE_STATE,CLKLANE_STATE: state of the clock lane [00: start / 01: idle / 10: HS / 11: ULPM]" "0: start /,1: idle /,?,?" rgroup.long 0x30++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_dsc_mode_ctl,DSC Mode Control register" bitfld.long 0x0 0. "DSC_MODE_EN,Enable DSC Mode Controls" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_dsc_cmd_send,DSC Command Control register. Write one to perform PPS set transfer or Execute Queue commands" bitfld.long 0x0 1. "DSC_SEND_PPS,Send PPS Command and Payload to the display" "0,1" newline bitfld.long 0x0 0. "DSC_EXECUTE_QUEUE,Send Execute Queue Command to Synchonise the display drivers" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_dsc_pps_wrdat,DSC PPS Write data to outgoing FIFO Buffer. byte 0 to 3; applicable to either Write or Read commands." hexmask.long.byte 0x0 24.--31. 1. "PPS_WRDAT3,WRDAT3: 4th byte to be sent as part of PPS payload [stored in a FIFO]" newline hexmask.long.byte 0x0 16.--23. 1. "PPS_WRDAT2,WRDAT2: 3rd byte to be sent as part of PPS payload [stored in a FIFO]" newline hexmask.long.byte 0x0 8.--15. 1. "PPS_WRDAT1,WRDAT1: 2nd byte to be sent as part of PPS payload [stored in a FIFO]" newline hexmask.long.byte 0x0 0.--7. 1. "PPS_WRDAT0,WRDAT0: 1st byte to be sent as part of PPS payload [stored in a FIFO]" rgroup.long 0x3C++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_dsc_mode_sts,DSC Event Status Register" bitfld.long 0x0 1. "DSC_PPS_DONE,DSC PPS Command Sent" "0,1" newline bitfld.long 0x0 0. "DSC_EXEC_DONE,DSC Execute Command Sent" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_dphy_skewcal_timeout,Used in conjunction with HS_SKEWCAL_TIMEOUT_EN from MCTL_MAIN_PHY_CTL to control periodic skew calibration" hexmask.long 0x0 0.--31. 1. "SKEWCAL_TO_VAL,SKEWCAL_TO_VAL: Timeout value" rgroup.long 0x70++0x7 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_cmd_mode_ctl,Command mode control" bitfld.long 0x0 10. "IF3_LP_EN,IF3_LP_EN: enable to send command from DSC interface in LP if possible" "0,1" newline bitfld.long 0x0 9. "IF1_LP_EN,IF1_LP_EN: enable to send command from SDI interface in LP if possible" "0,1" newline bitfld.long 0x0 2.--3. "IF3_ID,IF3_ID: Virtual Channel ID of request from DSC interface command" "0,1,2,3" newline bitfld.long 0x0 0.--1. "IF1_ID,IF1_ID: Virtual Channel ID of request from SDI interface command" "0,1,2,3" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_cmd_mode_ctl2,Command mode control" hexmask.long.word 0x4 11.--22. 1. "TE_TIMEOUT,TE_TIMEOUT : on TE request - length of TE response window before timeout." newline hexmask.long.byte 0x4 3.--10. 1. "FIL_VALUE,FIL_VALUE: value to use to fill packet during data underrun or to complete unterminated packet [referred as padding value]" newline bitfld.long 0x4 1.--2. "ARB_PRI,ARB_PRI: in fixed mode specify interface with higher priority SDI 01 DSC 10" "0,1,2,3" newline bitfld.long 0x4 0. "ARB_MODE,ARB_MODE: arbitration mode [1: round robin 0: fixed]" "0: fixed],1: round robin" rgroup.long 0x78++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_cmd_mode_sts,Command Mode status" bitfld.long 0x0 4. "ERR_IF1_UNDERRUN,ERR_IF1_UNDERRUN: Indicates a data shortage occurs on IF1" "0,1" newline bitfld.long 0x0 3. "ERR_UNWANTED_RD,ERR_UNWANTED_RD: Indicates a read request was received while read capability was not enabled" "0,1" newline bitfld.long 0x0 2. "ERR_TE_MISS,ERR_TE_MISS: error: TE window time-out" "0,1" newline bitfld.long 0x0 1. "ERR_NO_TE,ERR_NO_TE: error: no TE generated by display" "0,1" newline bitfld.long 0x0 0. "CSM_RUNNING,CSM_RUNNING: Indicates CSM is running - command[s] are being proceeded" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_send,Direct_cmd_send is not a real register. When this address is written (whatever its value is). it signals to the link that a direct command has to be sent." hexmask.long 0x0 0.--31. 1. "DIRECT_CMD_SEND,Initiate the direct command send operation" rgroup.long 0x84++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_main_settings,Main control of the Direct Command function." hexmask.long.byte 0x0 25.--28. 1. "TRIGGER_VAL,TRIGGER_VAL: trigger value if trigger request [see Note about trigger mapping] - signal is one hot encoding [only one bit out of the 4 should be set to 1]." newline bitfld.long 0x0 24. "CMD_LP_EN,CMD_LP_EN: enables LP sending for the command request" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "CMD_SIZE,CMD_SIZE: size in bytes of the command payload. Note that the value written here by software should comply with certain limits. For write operations any value written which is larger than the FIFO depth [direct_cmd_fifodepth.." newline bitfld.long 0x0 14.--15. "CMD_ID,CMD_ID: For a read/write command Virtual Channel of the command" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "CMD_HEAD,CMD_HEAD: For a read/write command datatype of the command" newline bitfld.long 0x0 3. "CMD_LONGNOTSHORT,CMD_LONGNOTSHORT: Tie this to '1' if a long packet has to be generated." "0,1" newline bitfld.long 0x0 0.--2. "CMD_NAT,CMD_NAT: Type of the direct command: 000: write command 001: read command 100: TE request 101: trigger request 110: BTA request" "0: write command,1: read command,?,?,?,?,?,?" rgroup.long 0x88++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_sts,Direct Command Status: To ensure that the observed status bits are coherent and applicable to the last command message sent." hexmask.long.word 0x0 16.--31. 1. "ACK_VAL,ACK_VAL: if an acknowledge with error has been received this field reports its value" newline hexmask.long.byte 0x0 11.--14. 1. "TRIGGER_VAL,TRIGGER_VAL: if a trigger has been received this field reports its value - refer to Note regarding trigger mapping" newline bitfld.long 0x0 10. "READ_COMPLETED_WITH_ERR,READ_COMPLETED_WITH_ERR: read command terminated with error" "0,1" newline bitfld.long 0x0 9. "BTA_FINISHED,BTA_FINISHED: DSI link recovered link master role after a BTA request" "0,1" newline bitfld.long 0x0 8. "BTA_COMPLETED,BTA_COMPLETED: indicates that BTA request completed" "0,1" newline bitfld.long 0x0 7. "TE_RECEIVED,TE_RECEIVED: TE received" "0,1" newline bitfld.long 0x0 6. "TRIGGER_RECEIVED,TRIGGER_RECEIVED: If command with BTA this bit is set if an trigger was received" "0,1" newline bitfld.long 0x0 5. "ACK_WITH_ERR_RECEIVED,ACKNOWLEDGE_WITH_ERR_RECEIVED: If command with BTA this bit is set if an acknowledge with error was received" "0,1" newline bitfld.long 0x0 4. "ACK_RECEIVED,ACKNOWLEDGE_RECEIVED: If command with BTA this bit is set if an acknowledge with no error was received" "0,1" newline bitfld.long 0x0 3. "READ_COMPLETED,READ_COMPLETED: read command request completed" "0,1" newline bitfld.long 0x0 2. "TRIGGER_COMPLETED,TRIGGER_COMPLETED: trigger command request completed" "0,1" newline bitfld.long 0x0 1. "WRITE_COMPLETED,WRITE_COMPLETED: write command request completed" "0,1" newline bitfld.long 0x0 0. "CMD_TRANSMISSION,CMD_TRANSMISSION: a command is being sent" "0,1" rgroup.long 0x8C++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_rd_init,This register is not a real register - when written it stops the read command process by emptying" hexmask.long 0x0 0.--31. 1. "STOP_READ_OPERATION,Stop Read Operation" rgroup.long 0x90++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_wrdat,Write data to outgoing Direct Command FIFO. byte 0 to 3; applicable to either Write or Read commands." hexmask.long.byte 0x0 24.--31. 1. "WRDAT3,WRDAT3: 4th byte to be sent as part of Direct Command [stored in a FIFO]" newline hexmask.long.byte 0x0 16.--23. 1. "WRDAT2,WRDAT2: 3rd byte to be sent as part of Direct Command [stored in a FIFO]" newline hexmask.long.byte 0x0 8.--15. 1. "WRDAT1,WRDAT1: 2nd byte to be sent as part of Direct Command [stored in a FIFO]" newline hexmask.long.byte 0x0 0.--7. 1. "WRDAT0,WRDAT0: 1st byte to be sent as part of Direct Command [stored in a FIFO]" rgroup.long 0x94++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_fifo_rst,Reset the write FIFO. This register is not a real register - when written it reset the FIFO pointer" hexmask.long 0x0 0.--31. 1. "CMD_FIFO_RST,Direct Command FIFO Reset" rgroup.long 0xA0++0xB line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_rddat,Data from incoming Direct Command receive path. byte 0 to 3." hexmask.long.byte 0x0 24.--31. 1. "RDDAT3,RDDAT3: 4th byte from incoming Direct Command receive path" newline hexmask.long.byte 0x0 16.--23. 1. "RDDAT2,RDDAT2: 3rd byte from incoming Direct Command receive path" newline hexmask.long.byte 0x0 8.--15. 1. "RDDAT1,RDDAT1: 2nd byte from incoming Direct Command receive path" newline hexmask.long.byte 0x0 0.--7. 1. "RDDAT0,RDDAT0: 1st byte from incoming Direct Command receive path" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_rd_property,read command characteristics" bitfld.long 0x4 18. "RD_DCSNOTGENERIC,RD_DCSNOTGENERIC: Type of read command [DCS or generic]" "0,1" newline bitfld.long 0x4 16.--17. "RD_ID,RD_ID: Virtual channel of the read received" "0,1,2,3" newline hexmask.long.word 0x4 0.--15. 1. "RD_SIZE,RD_SIZE: Size of the read data received" line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_rd_sts,Status of the read command received. It is recommended to clear direct_cmd_sts" bitfld.long 0x8 8. "ERR_EOT_WITH_ERR,ERR_EOT_WITH_ERR: EOT received with error" "0,1" newline bitfld.long 0x8 7. "ERR_MISSING_EOT,ERR_MISSING_EOT: EOT requested but not received" "0,1" newline bitfld.long 0x8 6. "ERR_WRONG_LENGTH,ERR_WRONG_LENGTH : length error has been detected. This error indicates that a packet has been received which was shorter than the expected length [longer packets than expected will result in ERR_RECEIVE field being set as it is.." "0,1" newline bitfld.long 0x8 5. "ERR_OVERSIZE,ERR_OVERSIZE : packet size exceeds maximum" "0,1" newline bitfld.long 0x8 4. "ERR_RECEIVE,ERR_RECEIVE : received packet not complete. This is a general error flag indicated that packet reception did not complete for some reason. Example conditions: signalling errors [e.g. unexpected change in PPI.." "0,1" newline bitfld.long 0x8 3. "ERR_UNDECODABLE,ERR_UNDECODABLE : command opcode not understood" "0,1" newline bitfld.long 0x8 2. "ERR_CHECKSUM,ERR_CHECKSUM: error[s] detected by checksum" "0,1" newline bitfld.long 0x8 1. "ERR_UNCORRECTABLE,ERR_UNCORRECTABLE : more than 1 error detected by ECC" "0,1" newline bitfld.long 0x8 0. "ERR_FIXED,ERR_FIXED : one error detected and fixed by ECC" "0,1" rgroup.long 0xB0++0xB line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_main_ctl,Video mode main control" bitfld.long 0x0 31. "VID_IGNORE_MISS_VSYNC,VID_IGNORE_MISSING_SYNC: When mode is enabled this allows the video stream to go to IDLE during VFP and wait for new VSYNC without link failing to recovery" "0,1" newline bitfld.long 0x0 25.--26. "RECOVERY_MODE,RECOVERY_MODE: specify recovery mode" "0,1,2,3" newline bitfld.long 0x0 23.--24. "REG_BLKEOL_MODE,REG_BLKEOL_MODE: behavior during end of line in burst mode - same coding as reg_blkline_mode" "0,1,2,3" newline bitfld.long 0x0 21.--22. "REG_BLKLINE_MODE,REG_BLKLINE_MODE : behavior during blanking time [1x: LP 01: blanking packet - 00: NULL packet]" "0: NULL packet],1: blanking packet,?,?" newline bitfld.long 0x0 20. "SYNC_PULSE_HORIZONTAL,SYNC_PULSE_HORIZONTAL: syncs are pulse [1] or event [0] all the time [DSI protocol v1.00..._r6 and later] - to be set only when sync_pulse_active = 1" "0,1" newline bitfld.long 0x0 19. "SYNC_PULSE_ACTIVE,SYNC_PULSE_ACTIVE: syncs are pulse [1] or event [0] during active area [DSI protocol v1.00..._r3 and before]" "0,1" newline bitfld.long 0x0 18. "BURST_MODE,BURST_MODE: signals if system works in burst mode or not" "0,1" newline hexmask.long.byte 0x0 14.--17. 1. "VID_PIXEL_MODE,VID_PIXEL_MODE: 0000: 16 bits RGB - 0001: 18 bits RGB.." newline hexmask.long.byte 0x0 8.--13. 1. "HEADER,HEADER : specify the datatype of RGB packets" newline bitfld.long 0x0 4.--5. "VID_ID,VID_ID : specify the Virtual Channel Identifier of the video packets" "0,1,2,3" newline bitfld.long 0x0 2.--3. "STOP_MODE,STOP_MODE : video stop point [see description in Video Stream Generator [VSG] section] .[The configurations where the frame stops at the end of any line and at the end of the last active line - start_mode in [1;2] - are.." "0,1,2,3" newline bitfld.long 0x0 0.--1. "START_MODE,START_MODE: video entry point [see description in Video Stream Generator [VSG] section][The configuration where the frame starts with a VFP - start_mode=1 - is being deprecated thus not verified anymore]" "?,1: is being deprecated,?,?" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_vsize1,Image vertical Sync and Blanking settings" hexmask.long.byte 0x4 12.--19. 1. "VFP_LENGTH,VFP_LENGTH: length of the VFP [in lines]" newline hexmask.long.byte 0x4 6.--11. 1. "VBP_LENGTH,VBP_LENGTH: length of the VBP [in lines]" newline hexmask.long.byte 0x4 0.--5. 1. "VSA_LENGTH,VSA_LENGTH: duration of the VSYNC pulse [in lines]" line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_vsize2,Image vertical active line setting" hexmask.long.word 0x8 0.--12. 1. "VACT_LENGTH,VACT_LENGTH: vertical length of active area [in line]" rgroup.long 0xC0++0x7 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_hsize1,Image horizontal sync and Blanking setting" hexmask.long.word 0x0 16.--31. 1. "HBP_LENGTH,HBP_LENGTH: length of HBP [in bytes] - if 0 HBP packet is sent with 0 payload" newline hexmask.long.word 0x0 0.--9. 1. "HSA_LENGTH,HSA_LENGTH: duration of HSYNC pulse [in bytes]" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_hsize2,Image horizontal byte size setting" hexmask.long.word 0x4 16.--26. 1. "HFP_LENGTH,HFP_LENGTH: length of HFP [in bytes] - if 0 no HFP packet is sent" newline hexmask.long.word 0x4 0.--14. 1. "RGB_SIZE,RGB_SIZE: size [in byte] of the RGB packet" rgroup.long 0xCC++0x7 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_blksize1,blanking packet size" hexmask.long.word 0x0 15.--29. 1. "BLKEOL_PCK,BLKEOL_PCK: packet length [in byte] on end of line if burst mode [reg_blkeol_mode = 0b0x]" newline hexmask.long.word 0x0 0.--14. 1. "BLKLINE_EVENT_PCK,BLKLINE_EVENT_PCK: packet length [in byte] in blanking line if line has to be filled with a packet [reg_blkline_mode = 0b0x] and sync is an event Event mode Blank line.." line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_blksize2,Pulse Mode blanking packet size" hexmask.long.word 0x4 0.--14. 1. "BLKLINE_PULSE_PCK,BLKLINE_PULSE_PCK: packet length in blanking line if line has to be filled with a packet [reg_blkline_mode = 0b0x] and sync is a pulse Pulse mode Blank.." rgroup.long 0xD8++0xF line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_pck_time,Packet duration" hexmask.long.word 0x0 0.--14. 1. "BLKEOL_DURATION,BLKEOL_DURATION: specify the duration in clock cycles of the BLLP period [used for burst mode]" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_dphy_time,Time of D-PHY behavior for wakeup time and Line duration for LP during horozontal blanking lines" hexmask.long.word 0x4 17.--27. 1. "REG_WAKEUP_TIME,REG_WAKEUP_TIME: estimated time [in clock cycles] to perform LP->HS on D-PHY |___________reg_wakeup_time________________| | Clk Request.." newline hexmask.long.tbyte 0x4 0.--16. 1. "REG_LINE_DURATION,REG_LINE_DURATION: duration -in clock cycles - of the blanking area for VSA/VBP and VFP lines - considered when reg_blkline_mode = 1b1x Pulse mode Blank LP line EOT disabled.." line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_err_color1,error color (green and red)" hexmask.long.word 0x8 12.--23. 1. "COL_GREEN,COL_GREEN: green component of the fill color" newline hexmask.long.word 0x8 0.--11. 1. "COL_RED,COL_RED: red component of the fill color" line.long 0xC "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_err_color2,error color (blue and padding)" hexmask.long.word 0xC 12.--23. 1. "PAD_VALUE,PAD_VALUE: byte used to pad data [when system does not know exactly where it is]" newline hexmask.long.word 0xC 0.--11. 1. "COL_BLUE,COL_BLUE: blue component of the fill color" rgroup.long 0xE8++0xB line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_vpos,vertical position" hexmask.long.word 0x0 2.--14. 1. "LINE_VAL,LINE_VAL: line number of the current area" newline bitfld.long 0x0 0.--1. "LINE_POS,LINE_POS: position in the frame [see description in Video Stream Generator]" "0,1,2,3" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_hpos,Horizontal Position" hexmask.long.word 0x4 3.--17. 1. "HORIZONTAL_VAL,HORIZONTAL_VAL: position in the current horizontal area [in clock cycles]" newline bitfld.long 0x4 0.--2. "HORIZONTAL_POS,HORIZONTAL_POS: position in the line [see description in Video Stream Generator]" "0,1,2,3,4,5,6,7" line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_mode_sts,Video mode status and error reporting" bitfld.long 0x8 10. "VSG_RECOVERY,VSG_RECOVERY: specifies whether the VSG is in recovery mode or not" "0,1" newline bitfld.long 0x8 9. "ERR_VRS_WRONG_LENGTH,ERR_VRS_WRONG_LENGTH: signals that packets in SDI interface differ from the expected size [as specified by rgb_size]" "0,1" newline bitfld.long 0x8 8. "ERR_LONGREAD,ERR_LONGREAD: signals the read was too long" "0,1" newline bitfld.long 0x8 7. "ERR_LINEWRITE,ERR_LINEWRITE: signals the long packet is too long to pass during a long slot" "0,1" newline bitfld.long 0x8 6. "ERR_BURSTWRITE,ERR_BURSTWRITE: signals a long packet has been sent during active area" "0,1" newline bitfld.long 0x8 5. "REG_ERR_SMALL_HEIGHT,REG_ERR_SMALL_HEIGHT: fewer lines than expected between 2 VSYNC" "0,1" newline bitfld.long 0x8 4. "REG_ERR_SMALL_LENGTH,REG_ERR_SMALL_LENGTH: fewer bytes received than expected between 2 HSYNC. Note that MISSING_DATA error may occur instead of SMALL_LENGTH dependent upon timing." "0,1" newline bitfld.long 0x8 3. "ERR_MISSING_VSYNC,ERR_MISSING_VSYNC: missing VSYNC" "0,1" newline bitfld.long 0x8 2. "ERR_MISSING_HSYNC,ERR_MISSING_HSYNC: missing HSYNC" "0,1" newline bitfld.long 0x8 1. "ERR_MISSING_DATA,ERR_MISSING_DATA: data starvation at input of the VSG. Note that this error report may also be triggered instead of the SMALL_LENGTH error dependent upon timing." "0,1" newline bitfld.long 0x8 0. "VSG_RUNNING,VSG_RUNNING: VSG is running [1] or stopped [0]" "0,1" rgroup.long 0xF4++0x1F line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_vca_setting1,VCA control register 1" bitfld.long 0x0 16. "BURST_LP,BURST_LP: after an active line the system can switch in LP [1] or should complete the line with NULL packet [0]" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "MAX_BURST_LIMIT,MAX_BURST_LIMIT: size of the 'biggest' burst packet [packet that fits after RGB in burst mode]" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_vca_setting2,VCA control register 2" hexmask.long.word 0x4 16.--31. 1. "MAX_LINE_LIMIT,MAX_LINE_LIMIT: maximum size of the line packet [packet that fits in blanking line]" newline hexmask.long.word 0x4 0.--15. 1. "EXACT_BURST_LIMIT,EXACT_BURST_LIMIT: exact maximum size of the burst packet [packet that fits after RGB in burst mode]" line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_tvg_ctl,Main control of the TVG" bitfld.long 0x8 5.--7. "TVG_STRIPE_SIZE,TVG_STRIPE_SIZE: size of the stripe [in pixels] - defined by 2^reg_tvg_stripe_size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--4. "TVG_MODE,TVG_MODE: TVG display mode : 00 : single color ; 01 : reserved ; 10 : vertical stripes ; 11 horizontal stripes" "0: single color ;,1: reserved ;,?,?" newline bitfld.long 0x8 1.--2. "TVG_STOPMODE,TVG_STOPMODE: stop mode: 00: at end of frame 01: at end of line 1x: immediate" "0: at end of frame,1: at end of line,?,?" newline bitfld.long 0x8 0. "TVG_RUN,TVG_RUN: start/stop of the TVG" "0,1" line.long 0xC "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_tvg_img_size,TVG Generated image size" hexmask.long.word 0xC 16.--28. 1. "TVG_NBLINE,TVG_NBLINE: Number of lines per frame" newline hexmask.long.word 0xC 0.--14. 1. "TVG_LINE_SIZE,TVG_LINE_SIZE: Number of bytes per line" line.long 0x10 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_tvg_color1,Color 1 of the dummy frame G. R" hexmask.long.word 0x10 12.--23. 1. "COL1_GREEN,COL1_GREEN: green component of the color 1" newline hexmask.long.word 0x10 0.--11. 1. "COL1_RED,COL1_RED: red component of the color 1" line.long 0x14 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_tvg_color1_bis,Color 1 of the dummy frame . B" hexmask.long.word 0x14 0.--11. 1. "COL1_BLUE,COL1_BLUE: blue component of the color 1" line.long 0x18 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_tvg_color2,Color 2 of the dummy frame. G. R" hexmask.long.word 0x18 12.--23. 1. "COL2_GREEN,COL2_GREEN: green component of the color 2" newline hexmask.long.word 0x18 0.--11. 1. "COL2_RED,COL2_RED: red component of the color 2" line.long 0x1C "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_tvg_color2_bis,Color 2 of the dummy frame. B" hexmask.long.word 0x1C 0.--11. 1. "COL2_BLUE,COL2_BLUE: blue component of the color 2" rgroup.long 0x114++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_tvg_sts,TVG status register" bitfld.long 0x0 0. "TVG_RUNNING,TVG_RUNNING: status of the TVG" "0,1" rgroup.long 0x130++0x1F line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_main_sts_ctl,Controls the enabling and edge detection of main ctrl status bits" bitfld.long 0x0 25. "IF3_UNTERM_PCK_ERR_EDGE,IF3_UNTERM_PCK_ERR_EDGE: edge detection of if3_unterm_pck_err" "0,1" newline bitfld.long 0x0 24. "IF1_UNTERM_PCK_ERR_EDGE,IF1_UNTERM_PCK_ERR_EDGE: edge detection of if1_unterm_pck_err" "0,1" newline bitfld.long 0x0 23. "LPRX_TO_ERR_EDGE,LPRX_TO_ERR_EDGE: edge detection of LP_RX time-out error" "0,1" newline bitfld.long 0x0 22. "HSTX_TO_ERR_EDGE,HSTX_TO_ERR_EDGE: edge detection of HS_TX time-out error" "0,1" newline bitfld.long 0x0 21. "DAT4_READY_EDGE,DAT4_READY_EDGE: edge detection of dat4_ready" "0,1" newline bitfld.long 0x0 20. "DAT3_READY_EDGE,DAT3_READY_EDGE: edge detection of dat3_ready" "0,1" newline bitfld.long 0x0 19. "DAT2_READY_EDGE,DAT2_READY_EDGE: edge detection of dat2_ready" "0,1" newline bitfld.long 0x0 18. "DAT1_READY_EDGE,DAT1_READY_EDGE: edge detection of dat1_ready" "0,1" newline bitfld.long 0x0 17. "CLKLANE_READY_EDGE,CLKLANE_READY_EDGE: edge detection of clklane_ready" "0,1" newline bitfld.long 0x0 16. "PLL_LOCK_EDGE,PLL_LOCK_EDGE: edge detection of PLL lock" "0,1" newline bitfld.long 0x0 9. "IF3_UNTERM_PCK_ERR_EN,IF3_UNTERM_PCK_ERR_EN: enables if3_unterm_pck_err" "0,1" newline bitfld.long 0x0 8. "IF1_UNTERM_PCK_ERR_EN,IF1_UNTERM_PCK_ERR_EN: enables if1_unterm_pck_err" "0,1" newline bitfld.long 0x0 7. "LPRX_TO_ERR_EN,LPRX_TO_ERR_EN: enables lprx_to_err" "0,1" newline bitfld.long 0x0 6. "HSTX_TO_ERR_EN,HSTX_TO_ERR_EN: enables hstx_to_err" "0,1" newline bitfld.long 0x0 5. "DAT4_READY_EN,DAT4_READY_EN: enables dat4_ready" "0,1" newline bitfld.long 0x0 4. "DAT3_READY_EN,DAT3_READY_EN: enables dat3_ready" "0,1" newline bitfld.long 0x0 3. "DAT2_READY_EN,DAT2_READY_EN: enables dat2_ready" "0,1" newline bitfld.long 0x0 2. "DAT1_READY_EN,DAT1_READY_EN: enables dat1_ready" "0,1" newline bitfld.long 0x0 1. "CLKLANE_READY_EN,CLKLANE_READY_EN: enables clklane_ready" "0,1" newline bitfld.long 0x0 0. "PLL_LOCK_EN,PLL_LOCK_EN: enables PLL lock" "0,1" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_cmd_mode_sts_ctl,Controls the enabling and edge detection of command status bits" bitfld.long 0x4 21. "ERR_IF3_UNDERRUN_EDGE,ERR_IF3_UNDERRUN_EDGE: edge detection of err_IF3_underrun" "0,1" newline bitfld.long 0x4 20. "ERR_IF1_UNDERRUN_EDGE,ERR_IF1_UNDERRUN_EDGE: edge detection of err_IF1_underrun" "0,1" newline bitfld.long 0x4 19. "ERR_UNWANTED_RD_EDGE,ERR_UNWANTED_RD_EDGE: edge detection of err_unwanted_rd" "0,1" newline bitfld.long 0x4 18. "ERR_TE_MISS_EDGE,ERR_TE_MISS_EDGE: edge detection of err_te_miss" "0,1" newline bitfld.long 0x4 17. "ERR_NO_TE_EDGE,ERR_NO_TE_EDGE: edge detection of err_no_te" "0,1" newline bitfld.long 0x4 16. "CSM_RUNNING_EDGE,CSM_RUNNING_EDGE: edge detection of CSM running" "0,1" newline bitfld.long 0x4 5. "ERR_IF3_UNDERRUN_EN,ERR_IF3_UNDERRUN_EN: enables err_IF3_underrun" "0,1" newline bitfld.long 0x4 4. "ERR_IF1_UNDERRUN_EN,ERR_IF1_UNDERRUN_EN: enables err_IF1_underrun" "0,1" newline bitfld.long 0x4 3. "ERR_UNWANTED_RD_EN,ERR_UNWANTED_RD_EN: enables err_unwanted_rd" "0,1" newline bitfld.long 0x4 2. "ERR_TE_MISS_EN,ERR_TE_MISS_EN: enables err_te_miss" "0,1" newline bitfld.long 0x4 1. "ERR_NO_TE_EN,ERR_NO_TE_EN: enables err_no_te" "0,1" newline bitfld.long 0x4 0. "CSM_RUNNING_EN,CSM_RUNNING_EN: enables signaling of CSM running" "0,1" line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_sts_ctl,Controls the enabling and edge detection of Direct Command status bits" bitfld.long 0x8 26. "READ_COMPLETED_WITH_ERR_EDGE,READ_COMPLETED_WITH_ERR_EDGE: edge detection of read detection completed with errors" "0,1" newline bitfld.long 0x8 25. "BTA_FINISHED_EDGE,BTA_FINISHED_EDGE: edge detection of BTA completion detection" "0,1" newline bitfld.long 0x8 24. "BTA_COMPLETED_EDGE,BTA_COMPLETED_EDGE: edge detection of BTA request completed" "0,1" newline bitfld.long 0x8 23. "TE_RECEIVED_EDGE,TE_RECEIVED_EDGE: edge detection of TE received" "0,1" newline bitfld.long 0x8 22. "TRIGGER_RECEIVED_EDGE,TRIGGER_RECEIVED_EDGE: edge detection of trigger" "0,1" newline bitfld.long 0x8 21. "ACKNOWLEDGE_WITH_ERR_EDGE,ACKNOWLEDGE_WITH_ERR_EDGE: edge detection of acknowledge with error" "0,1" newline bitfld.long 0x8 20. "ACKNOWLEDGE_RECEIVED_EDGE,ACKNOWLEDGE_RECEIVED_EDGE: edge detection of acknowledge" "0,1" newline bitfld.long 0x8 19. "READ_COMPLETED_EDGE,READ_COMPLETED_EDGE: edge detection of read request completed" "0,1" newline bitfld.long 0x8 18. "TRIGGER_COMPLETED_EDGE,TRIGGER_COMPLETED_EDGE: edge detection of trigger request completed" "0,1" newline bitfld.long 0x8 17. "WRITE_COMPLETED_EDGE,WRITE_COMPLETED_EDGE: edge detection of detection of write request completed" "0,1" newline bitfld.long 0x8 16. "CMD_TRANSMISSION_EDGE,CMD_TRANSMISSION_EDGE: edge detection of cmd_transmission" "0,1" newline bitfld.long 0x8 10. "READ_COMPLETED_WITH_ERR_EN,READ_COMPLETED_WITH_ERR_EN: enables detection of read completed with errors" "0,1" newline bitfld.long 0x8 9. "BTA_FINISHED_EN,BTA_FINISHED_EN: enables BTA completion detection" "0,1" newline bitfld.long 0x8 8. "BTA_COMPLETED_EN,BTA_COMPLETED_EN: enables BTA request completed" "0,1" newline bitfld.long 0x8 7. "TE_RECEIVED_EN,TE_RECEIVED_EN: enables TE received" "0,1" newline bitfld.long 0x8 6. "TRIGGER_RECEIVED_EN,TRIGGER_RECEIVED_EN: enables trigger" "0,1" newline bitfld.long 0x8 5. "ACKNOWLEDGE_WITH_ERR_EN,ACKNOWLEDGE_WITH_ERR_EN: enables acknowledge with error" "0,1" newline bitfld.long 0x8 4. "ACKNOWLEDGE_RECEIVED_EN,ACKNOWLEDGE_RECEIVED_EN: enables acknowledge" "0,1" newline bitfld.long 0x8 3. "READ_COMPLETED_EN,READ_COMPLETED_EN: enables read request completed" "0,1" newline bitfld.long 0x8 2. "TRIGGER_COMPLETED_EN,TRIGGER_COMPLETED_EN: enables trigger_completed" "0,1" newline bitfld.long 0x8 1. "WRITE_COMPLETED_EN,WRITE_COMPLETED_EN: enables write_completed" "0,1" newline bitfld.long 0x8 0. "CMD_TRANSMISSION_EN,CMD_TRANSMISSION_EN: enables detection of cmd_transmission" "0,1" line.long 0xC "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_rd_sts_ctl,Controls the enabling and edge detection of read commands error" bitfld.long 0xC 24. "ERR_EOT_WITH_ERR_EDGE,ERR_EOT_WITH_ERR_EDGE: edge detection of err_eot_with_err" "0,1" newline bitfld.long 0xC 23. "ERR_MISSING_EOT_EDGE,ERR_MISSING_EOT_EDGE: edge detection of err_missing_eot" "0,1" newline bitfld.long 0xC 22. "ERR_WRONG_LENGTH_EDGE,ERR_WRONG_LENGTH_EDGE: edge detection of err_wrong_length" "0,1" newline bitfld.long 0xC 21. "ERR_OVERSIZE_EDGE,ERR_OVERSIZE_EDGE: edge detection of err_oversize" "0,1" newline bitfld.long 0xC 20. "ERR_RECEIVE_EDGE,ERR_RECEIVE_EDGE: edge detection of err_receive" "0,1" newline bitfld.long 0xC 19. "ERR_UNDECODABLE_EDGE,ERR_UNDECODABLE_EDGE: edge detection of err_undecodable" "0,1" newline bitfld.long 0xC 18. "ERR_CHECKSUM_EDGE,ERR_CHECKSUM_EDGE: edge detection of err_checksum" "0,1" newline bitfld.long 0xC 17. "ERR_UNCORRECTABLE_EDGE,ERR_UNCORRECTABLE_EDGE: edge detection of err_uncorrectable" "0,1" newline bitfld.long 0xC 16. "ERR_FIXED_EDGE,ERR_FIXED_EDGE: edge detection of err_fixed" "0,1" newline bitfld.long 0xC 8. "ERR_EOT_WITH_ERR_EN,ERR_EOT_WITH_ERR_EN: enables err_eot_with_err" "0,1" newline bitfld.long 0xC 7. "ERR_MISSING_EOT_EN,ERR_MISSING_EOT_EN: enables err_missing_eot" "0,1" newline bitfld.long 0xC 6. "ERR_WRONG_LENGTH_EN,ERR_WRONG_LENGTH_EN: enables err_wrong_length" "0,1" newline bitfld.long 0xC 5. "ERR_OVERSIZE_EN,ERR_OVERSIZE_EN: enables err_oversize" "0,1" newline bitfld.long 0xC 4. "ERR_RECEIVE_EN,ERR_RECEIVE_EN: enables err_receive" "0,1" newline bitfld.long 0xC 3. "ERR_UNDECODABLE_EN,ERR_UNDECODABLE_EN: enables err_undecodable" "0,1" newline bitfld.long 0xC 2. "ERR_CHECKSUM_EN,ERR_CHECKSUM_EN: enables err_checksum" "0,1" newline bitfld.long 0xC 1. "ERR_UNCORRECTABLE_EN,ERR_UNCORRECTABLE_EN: enables err_uncorrectable" "0,1" newline bitfld.long 0xC 0. "ERR_FIXED_EN,ERR_FIXED_EN: enables err_fixed" "0,1" line.long 0x10 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_mode_sts_ctl,Control the enabling and edge detection of VSG status bits" bitfld.long 0x10 26. "VSG_RECOVERY_EDGE,VSG_RECOVERY_EDGE: edge detection of vsg_recovery" "0,1" newline bitfld.long 0x10 25. "ERR_VRS_WRONG_LENGTH_EDGE,ERR_VRS_WRONG_LENGTH_EDGE: edge detection of err_vrs_wrong_length" "0,1" newline bitfld.long 0x10 24. "ERR_LONGREAD_EDGE,ERR_LONGREAD_EDGE: edge detection of err_longread" "0,1" newline bitfld.long 0x10 23. "ERR_LINEWRITE_EDGE,ERR_LINEWRITE_EDGE: edge detection of err_line_write" "0,1" newline bitfld.long 0x10 22. "ERR_BURSTWRITE_EDGE,ERR_BURSTWRITE_EDGE: edge detection of err_burst_write" "0,1" newline bitfld.long 0x10 21. "ERR_SMALL_HEIGHT_EDGE,ERR_SMALL_HEIGHT_EDGE: edge detection of unaligned line number" "0,1" newline bitfld.long 0x10 20. "ERR_SMALL_LENGTH_EDGE,ERR_SMALL_LENGTH_EDGE: edge detection of unaligned size" "0,1" newline bitfld.long 0x10 19. "ERR_MISSING_VSYNC_EDGE,ERR_MISSING_VSYNC_EDGE: edge detection of detection of missing VSYNC" "0,1" newline bitfld.long 0x10 18. "ERR_MISSING_HSYNC_EDGE,ERR_MISSING_HSYNC_EDGE: edge detection of detection of missing HSYNC" "0,1" newline bitfld.long 0x10 17. "ERR_MISSING_DATA_EDGE,ERR_MISSING_DATA_EDGE: edge detection of data miss detection" "0,1" newline bitfld.long 0x10 16. "VSG_RUNNING_EDGE,VSG_RUNNING_EDGE: edge detection of VSG status observation" "0,1" newline bitfld.long 0x10 10. "VSG_RECOVERY_EN,VSG_RECOVERY_EN: enables vsg_recovery" "0,1" newline bitfld.long 0x10 9. "ERR_VRS_WRONG_LENGTH_EN,ERR_VRS_WRONG_LENGTH_EN: enables err_vrs_wrong_length" "0,1" newline bitfld.long 0x10 8. "ERR_LONGREAD_EN,ERR_LONGREAD_EN: enables err_longread" "0,1" newline bitfld.long 0x10 7. "ERR_LINEWRITE_EN,ERR_LINEWRITE_EN: enables err_line_write" "0,1" newline bitfld.long 0x10 6. "ERR_BURSTWRITE_EN,ERR_BURSTWRITE_EN: enables err_burst_write" "0,1" newline bitfld.long 0x10 5. "ERR_SMALL_HEIGHT_EN,ERR_SMALL_HEIGHT_EN: enables detection of unaligned line number" "0,1" newline bitfld.long 0x10 4. "ERR_SMALL_LENGTH_EN,ERR_SMALL_LENGTH_EN: enables detection of unaligned size" "0,1" newline bitfld.long 0x10 3. "ERR_MISSING_VSYNC_EN,ERR_MISSING_VSYNC_EN: enables detection of missing VSYNC" "0,1" newline bitfld.long 0x10 2. "ERR_MISSING_HSYNC_EN,ERR_MISSING_HSYNC_EN: enables detection of missing HSYNC" "0,1" newline bitfld.long 0x10 1. "ERR_MISSING_DATA_EN,ERR_MISSING_DATA_EN: enables data miss detection" "0,1" newline bitfld.long 0x10 0. "VSG_RUNNING_EN,VSG_RUNNING_EN: enables VSG status observation" "0,1" line.long 0x14 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_tvg_sts_ctl,Control the enabling and edge detection of TVG status bits" bitfld.long 0x14 16. "TVG_STS_EDGE,TVG_STS_EDGE: edge detection of TVG status observation" "0,1" newline bitfld.long 0x14 0. "TVG_STS_EN,TVG_STS_EN: enables TVG status observation" "0,1" line.long 0x18 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_dphy_err_ctl1,Controls the enabling and edge detection of the DPHY errors" bitfld.long 0x18 25. "ERR_CONT_LP1_4_EN,ERR_CONT_LP1_4_EN" "0,1" newline bitfld.long 0x18 24. "ERR_CONT_LP1_3_EN,ERR_CONT_LP1_3_EN" "0,1" newline bitfld.long 0x18 23. "ERR_CONT_LP1_2_EN,ERR_CONT_LP1_2_EN" "0,1" newline bitfld.long 0x18 22. "ERR_CONT_LP1_1_EN,ERR_CONT_LP1_1_EN" "0,1" newline bitfld.long 0x18 21. "ERR_CONT_LP0_4_EN,ERR_CONT_LP0_4_EN" "0,1" newline bitfld.long 0x18 20. "ERR_CONT_LP0_3_EN,ERR_CONT_LP0_3_EN" "0,1" newline bitfld.long 0x18 19. "ERR_CONT_LP0_2_EN,ERR_CONT_LP0_2_EN" "0,1" newline bitfld.long 0x18 18. "ERR_CONT_LP0_1_EN,ERR_CONT_LP0_1_EN" "0,1" newline bitfld.long 0x18 17. "ERR_CONTROL_4_EN,ERR_CONTROL_4_EN" "0,1" newline bitfld.long 0x18 16. "ERR_CONTROL_3_EN,ERR_CONTROL_3_EN" "0,1" newline bitfld.long 0x18 15. "ERR_CONTROL_2_EN,ERR_CONTROL_2_EN" "0,1" newline bitfld.long 0x18 14. "ERR_CONTROL_1_EN,ERR_CONTROL_1_EN" "0,1" newline bitfld.long 0x18 13. "ERR_SYNCESC_4_EN,ERR_SYNCESC_4_EN" "0,1" newline bitfld.long 0x18 12. "ERR_SYNCESC_3_EN,ERR_SYNCESC_3_EN" "0,1" newline bitfld.long 0x18 11. "ERR_SYNCESC_2_EN,ERR_SYNCESC_2_EN" "0,1" newline bitfld.long 0x18 10. "ERR_SYNCESC_1_EN,ERR_SYNCESC_1_EN" "0,1" newline bitfld.long 0x18 9. "ERR_ESC_4_EN,ERR_ESC_4_EN" "0,1" newline bitfld.long 0x18 8. "ERR_ESC_3_EN,ERR_ESC_3_EN" "0,1" newline bitfld.long 0x18 7. "ERR_ESC_2_EN,ERR_ESC_2_EN" "0,1" newline bitfld.long 0x18 6. "ERR_ESC_1_EN,ERR_ESC_1_EN" "0,1" line.long 0x1C "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_dphy_err_ctl2,Controls he enabling and edge detection of the DPHY errors" bitfld.long 0x1C 19. "ERR_CONT_LP1_4_EDGE,ERR_CONT_LP1_4_EDGE" "0,1" newline bitfld.long 0x1C 18. "ERR_CONT_LP1_3_EDGE,ERR_CONT_LP1_3_EDGE" "0,1" newline bitfld.long 0x1C 17. "ERR_CONT_LP1_2_EDGE,ERR_CONT_LP1_2_EDGE" "0,1" newline bitfld.long 0x1C 16. "ERR_CONT_LP1_1_EDGE,ERR_CONT_LP1_1_EDGE" "0,1" newline bitfld.long 0x1C 15. "ERR_CONT_LP0_4_EDGE,ERR_CONT_LP0_4_EDGE" "0,1" newline bitfld.long 0x1C 14. "ERR_CONT_LP0_3_EDGE,ERR_CONT_LP0_3_EDGE" "0,1" newline bitfld.long 0x1C 13. "ERR_CONT_LP0_2_EDGE,ERR_CONT_LP0_2_EDGE" "0,1" newline bitfld.long 0x1C 12. "ERR_CONT_LP0_1_EDGE,ERR_CONT_LP0_1_EDGE" "0,1" newline bitfld.long 0x1C 11. "ERR_CONTROL_4_EDGE,ERR_CONTROL_4_EDGE" "0,1" newline bitfld.long 0x1C 10. "ERR_CONTROL_3_EDGE,ERR_CONTROL_3_EDGE" "0,1" newline bitfld.long 0x1C 9. "ERR_CONTROL_2_EDGE,ERR_CONTROL_2_EDGE" "0,1" newline bitfld.long 0x1C 8. "ERR_CONTROL_1_EDGE,ERR_CONTROL_1_EDGE" "0,1" newline bitfld.long 0x1C 7. "ERR_SYNCESC_4_EDGE,ERR_SYNCESC_4_EDGE" "0,1" newline bitfld.long 0x1C 6. "ERR_SYNCESC_3_EDGE,ERR_SYNCESC_3_EDGE" "0,1" newline bitfld.long 0x1C 5. "ERR_SYNCESC_2_EDGE,ERR_SYNCESC_2_EDGE" "0,1" newline bitfld.long 0x1C 4. "ERR_SYNCESC_1_EDGE,ERR_SYNCESC_1_EDGE" "0,1" newline bitfld.long 0x1C 3. "ERR_ESC_4_EDGE,ERR_ESC_4_EDGE" "0,1" newline bitfld.long 0x1C 2. "ERR_ESC_3_EDGE,ERR_ESC_3_EDGE" "0,1" newline bitfld.long 0x1C 1. "ERR_ESC_2_EDGE,ERR_ESC_2_EDGE" "0,1" newline bitfld.long 0x1C 0. "ERR_ESC_1_EDGE,ERR_ESC_1_EDGE" "0,1" rgroup.long 0x150++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_main_sts_clr,Main control status register clear function. These bits are spread across different register banks." bitfld.long 0x0 9. "IF3_UNTERM_PCK_ERR_CLR,IF3_UNTERM_PCK_ERR_CLR: clears if3_unterm_pck_err" "0,1" newline bitfld.long 0x0 8. "IF1_UNTERM_PCK_ERR_CLR,IF1_UNTERM_PCK_ERR_CLR: clears if1_unterm_pck_err" "0,1" newline bitfld.long 0x0 7. "LPRX_TO_ERR_CLR,LPRX_TO_ERR_CLR: clears lprx_to_err" "0,1" newline bitfld.long 0x0 6. "HSTX_TO_ERR_CLR,HSTX_TO_ERR_CLR: clears hstx_to_err" "0,1" newline bitfld.long 0x0 5. "DAT4_READY_CLR,DAT4_READY_CLR: clears dat4_ready" "0,1" newline bitfld.long 0x0 4. "DAT3_READY_CLR,DAT3_READY_CLR: clears dat3_ready" "0,1" newline bitfld.long 0x0 3. "DAT2_READY_CLR,DAT2_READY_CLR: clears dat2_ready" "0,1" newline bitfld.long 0x0 2. "DAT1_READY_CLR,DAT1_READY_CLR: clears dat1_ready" "0,1" newline bitfld.long 0x0 1. "CLKLANE_READY_CLR,CLKLANE_READY_CLR: clears clklane_ready" "0,1" newline bitfld.long 0x0 0. "PLL_LOCK_CLR,PLL_LOCK_CLR: clears PLL lock" "0,1" rgroup.long 0x154++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_cmd_mode_sts_clr,Command status register clear function. Write '1' to clear" rbitfld.long 0x0 5. "ERR_IF3_UNDERRUN_CLR,ERR_IF3_UNDERRUN_CLR: clears err_IF3_underrun" "0,1" newline bitfld.long 0x0 4. "ERR_IF1_UNDERRUN_CLR,ERR_IF1_UNDERRUN_CLR: clears err_IF1_underrun" "0,1" newline bitfld.long 0x0 3. "ERR_UNWANTED_RD_CLR,ERR_UNWANTED_RD_CLR: clears err_unwanted_rd" "0,1" newline bitfld.long 0x0 2. "ERR_TE_MISS_CLR,ERR_TE_MISS_CLR: clears err_te_miss" "0,1" newline bitfld.long 0x0 1. "ERR_NO_TE_CLR,ERR_NO_TE_CLR: clears err_no_te" "0,1" newline bitfld.long 0x0 0. "CSM_RUNNING_CLR,CSM_RUNNING_CLR: clears CSM running bit" "0,1" rgroup.long 0x158++0x13 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_sts_clr,Direct command status register clear function. Write '1' to clear" bitfld.long 0x0 10. "READ_COMPLETED_WITH_ERR_CLR,READ_COMPLETED_WITH_ERR_CLR: clears detection of read completed with errors" "0,1" newline bitfld.long 0x0 9. "BTA_FINISHED_CLR,BTA_FINISHED_CLR: clears BTA completion detection" "0,1" newline bitfld.long 0x0 8. "BTA_COMPLETED_CLR,BTA_COMPLETED_CLR: clears BTA request completed" "0,1" newline bitfld.long 0x0 7. "TE_RECEIVED_CLR,TE_RECEIVED_CLR: clears TE received" "0,1" newline bitfld.long 0x0 6. "TRIGGER_RECEIVED_CLR,TRIGGER_RECEIVED_CLR: clears trigger" "0,1" newline bitfld.long 0x0 5. "ACK_WITH_ERR_CLR,ACKNOWLEDGE_WITH_ERR_CLR: clears acknowledge with errors" "0,1" newline bitfld.long 0x0 4. "ACK_RECEIVED_CLR,ACKNOWLEDGE_RECEIVED_CLR: clears acknowledge" "0,1" newline bitfld.long 0x0 3. "READ_COMPLETED_CLR,READ_COMPLETED_CLR: clears read request completed" "0,1" newline bitfld.long 0x0 2. "TRIGGER_COMPLETED_CLR,TRIGGER_COMPLETED_CLR: clears trigger request completed" "0,1" newline bitfld.long 0x0 1. "WRITE_COMPLETED_CLR,WRITE_COMPLETED_CLR: clears detection of write request completed" "0,1" newline bitfld.long 0x0 0. "CMD_TRANSMISSION_CLR,CMD_TRANSMISSION_CLR: clears cmd_transmission" "0,1" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_rd_sts_clr,Direct command read status register clear function. Write '1' to clear" bitfld.long 0x4 8. "ERR_EOT_WITH_ERR_CLR,ERR_EOT_WITH_ERR_CLR: clears err_eot_with_err" "0,1" newline bitfld.long 0x4 7. "ERR_MISSING_EOT_CLR,ERR_MISSING_EOT_CLR: clears err_missing_eot" "0,1" newline bitfld.long 0x4 6. "ERR_WRONG_LENGTH_CLR,ERR_WRONG_LENGTH_CLR: clears err_wrong_length" "0,1" newline bitfld.long 0x4 5. "ERR_OVERSIZE_CLR,ERR_OVERSIZE_CLR: clears err_oversize" "0,1" newline bitfld.long 0x4 4. "ERR_RECEIVE_CLR,ERR_RECEIVE_CLR: clears err_receive" "0,1" newline bitfld.long 0x4 3. "ERR_UNDECODABLE_CLR,ERR_UNDECODABLE_CLR: clears err_undecodable" "0,1" newline bitfld.long 0x4 2. "ERR_CHECKSUM_CLR,ERR_CHECKSUM_CLR: clears err_checksum" "0,1" newline bitfld.long 0x4 1. "ERR_UNCORRECTABLE_CLR,ERR_UNCORRECTABLE_CLR: clears err_uncorrectable" "0,1" newline bitfld.long 0x4 0. "ERR_FIXED_CLR,ERR_FIXED_CLR: clears err_fixed" "0,1" line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_mode_sts_clr,VSG status register clear function" bitfld.long 0x8 10. "VSG_RECOVERY_CLR,VSG_RECOVERY_CLR: clears the bit vsg_recovery" "0,1" newline bitfld.long 0x8 9. "ERR_VRS_WRONG_LENGTH_CLR,ERR_VRS_WRONG_LENGTH_CLR: clears the bit err_vid_wrong_length" "0,1" newline bitfld.long 0x8 8. "ERR_LONGREAD_CLR,ERR_LONGREAD_CLR: clears err_longread" "0,1" newline bitfld.long 0x8 7. "ERR_LINEWRITE_CLR,ERR_LINEWRITE_CLR: clears err_linewrite" "0,1" newline bitfld.long 0x8 6. "ERR_BURSTWRITE_CLR,ERR_BURSTWRITE_CLR: clears err_burstwrite" "0,1" newline bitfld.long 0x8 5. "ERR_SMALL_HEIGHT_CLR,ERR_SMALL_HEIGHT_CLR: clears unaligned line number" "0,1" newline bitfld.long 0x8 4. "ERR_SMALL_LENGTH_CLR,ERR_SMALL_LENGTH_CLR: clears analigned size" "0,1" newline bitfld.long 0x8 3. "ERR_MISSING_VSYNC_CLR,ERR_MISSING_VSYNC_CLR: clears missing VSYNC" "0,1" newline bitfld.long 0x8 2. "ERR_MISSING_HSYNC_CLR,ERR_MISSING_HSYNC_CLR: clears missing HSYNC" "0,1" newline bitfld.long 0x8 1. "ERR_MISSING_DATA_CLR,ERR_MISSING_DATA_CLR: clears data miss" "0,1" newline bitfld.long 0x8 0. "VSG_STS_CLR,VSG_STS_CLR: clears VSG status" "0,1" line.long 0xC "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_tg_sts_clr,TVG status register clear function. Write '1' to clear" bitfld.long 0xC 0. "TVG_STS_CLR,TVG_STS_CLR: clears TVG status observation" "0,1" line.long 0x10 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_dphy_err_clr,D_PHY lanes output register clear function. Write '1' to clear" bitfld.long 0x10 25. "ERR_CONT_LP1_4_CLR,ERR_CONT_LP1_4_CLR" "0,1" newline bitfld.long 0x10 24. "ERR_CONT_LP1_3_CLR,ERR_CONT_LP1_3_CLR" "0,1" newline bitfld.long 0x10 23. "ERR_CONT_LP1_2_CLR,ERR_CONT_LP1_2_CLR" "0,1" newline bitfld.long 0x10 22. "ERR_CONT_LP1_1_CLR,ERR_CONT_LP1_1_CLR" "0,1" newline bitfld.long 0x10 21. "ERR_CONT_LP0_4_CLR,ERR_CONT_LP0_4_CLR" "0,1" newline bitfld.long 0x10 20. "ERR_CONT_LP0_3_CLR,ERR_CONT_LP0_3_CLR" "0,1" newline bitfld.long 0x10 19. "ERR_CONT_LP0_2_CLR,ERR_CONT_LP0_2_CLR" "0,1" newline bitfld.long 0x10 18. "ERR_CONT_LP0_1_CLR,ERR_CONT_LP0_1_CLR" "0,1" newline bitfld.long 0x10 17. "ERR_CONTROL_4_CLR,ERR_CONTROL_4_CLR" "0,1" newline bitfld.long 0x10 16. "ERR_CONTROL_3_CLR,ERR_CONTROL_3_CLR" "0,1" newline bitfld.long 0x10 15. "ERR_CONTROL_2_CLR,ERR_CONTROL_2_CLR" "0,1" newline bitfld.long 0x10 14. "ERR_CONTROL_1_CLR,ERR_CONTROL_1_CLR" "0,1" newline bitfld.long 0x10 13. "ERR_SYNCESC_4_CLR,ERR_SYNCESC_4_CLR" "0,1" newline bitfld.long 0x10 12. "ERR_SYNCESC_3_CLR,ERR_SYNCESC_3_CLR" "0,1" newline bitfld.long 0x10 11. "ERR_SYNCESC_2_CLR,ERR_SYNCESC_2_CLR" "0,1" newline bitfld.long 0x10 10. "ERR_SYNCESC_1_CLR,ERR_SYNCESC_1_CLR" "0,1" newline bitfld.long 0x10 9. "ERR_ESC_4_CLR,ERR_ESC_4_CLR" "0,1" newline bitfld.long 0x10 8. "ERR_ESC_3_CLR,ERR_ESC_3_CLR" "0,1" newline bitfld.long 0x10 7. "ERR_ESC_2_CLR,ERR_ESC_2_CLR" "0,1" newline bitfld.long 0x10 6. "ERR_ESC_1_CLR,ERR_ESC_1_CLR" "0,1" rgroup.long 0x170++0x1B line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_main_sts_flag,Main control status Flag registers. The use of these registers is related to status and error bits management (and interrupt too)." bitfld.long 0x0 9. "IF3_UNTERM_PCK_ERR_FLAG,IF3_UNTERM_PCK_ERR_FLAG: flags if3_unterm_pck_err" "0,1" newline bitfld.long 0x0 8. "IF1_UNTERM_PCK_ERR_FLAG,IF1_UNTERM_PCK_ERR_FLAG: flags if1_unterm_pck_err" "0,1" newline bitfld.long 0x0 7. "LPRX_TO_ERR_FLAG,LPRX_TO_ERR_FLAG: flags lprx_to_err" "0,1" newline bitfld.long 0x0 6. "HSTX_TO_ERR_FLAG,HSTX_TO_ERR_FLAG: flags hstx_to_err" "0,1" newline bitfld.long 0x0 5. "DAT4_READY_FLAG,DAT4_READY_FLAG: flags dat4_ready" "0,1" newline bitfld.long 0x0 4. "DAT3_READY_FLAG,DAT3_READY_FLAG: flags dat3_ready" "0,1" newline bitfld.long 0x0 3. "DAT2_READY_FLAG,DAT2_READY_FLAG: flags dat2_ready" "0,1" newline bitfld.long 0x0 2. "DAT1_READY_FLAG,DAT1_READY_FLAG: flags dat1_ready" "0,1" newline bitfld.long 0x0 1. "CLKLANE_READY_FLAG,CLKLANE_READY_FLAG: flags clklane_ready" "0,1" newline bitfld.long 0x0 0. "PLL_LOCK_FLAG,PLL_LOCK_FLAG: flags PLL lock" "0,1" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_cmd_mode_sts_flag,Command Mode status" bitfld.long 0x4 5. "ERR_IF3_UNDERRUN_FLAG,ERR_IF3_UNDERRUN_FLAG: flags err_IF3_underrun" "0,1" newline bitfld.long 0x4 4. "ERR_IF1_UNDERRUN_FLAG,ERR_IF1_UNDERRUN_FLAG: flags err_IF1_underrun" "0,1" newline bitfld.long 0x4 3. "ERR_UNWANTED_RD_FLAG,ERR_UNWANTED_RD_FLAG: flags fixed_err" "0,1" newline bitfld.long 0x4 2. "ERR_TE_MISS_FLAG,ERR_TE_MISS_FLAG: flags err_te_miss" "0,1" newline bitfld.long 0x4 1. "ERR_NO_TE_FLAG,ERR_NO_TE_FLAG: flags err_no_te" "0,1" newline bitfld.long 0x4 0. "CSM_RUNNING_FLAG,CSM_RUNNING_FLAG: flags remaining_err" "0,1" line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_sts_flag,Direct command mode status" bitfld.long 0x8 10. "READ_COMPLETED_WITH_ERR_FLAG,READ_COMPLETED_WITH_ERR_FLAG: flags detection of read completed with errors" "0,1" newline bitfld.long 0x8 9. "BTA_FINISHED_FLAG,BTA_FINISHED_FLAG: flags BTA completion detection" "0,1" newline bitfld.long 0x8 8. "BTA_COMPLETED_FLAG,BTA_COMPLETED_FLAG: flags BTA request completed" "0,1" newline bitfld.long 0x8 7. "TE_RECEIVED_FLAG,TE_RECEIVED_FLAG: flags TE received" "0,1" newline bitfld.long 0x8 6. "TRIGGER_RECEIVED_FLAG,TRIGGER_RECEIVED_FLAG: flags trigger" "0,1" newline bitfld.long 0x8 5. "ACK_WITH_ERR_RECEIVED_FLAG,ACK_WITH_ERR_RECEIVED_FLAG: flag acknowledge with error detection" "0,1" newline bitfld.long 0x8 4. "ACKNOWLEDGE_RECEIVED_FLAG,ACKNOWLEDGE_RECEIVED_FLAG: flags acknowledge" "0,1" newline bitfld.long 0x8 3. "READ_COMPLETED_FLAG,READ_COMPLETED_FLAG: flags read request completed" "0,1" newline bitfld.long 0x8 2. "TRIGGER_COMPLETED_FLAG,TRIGGER_COMPLETED_FLAG: flags trigger request completed" "0,1" newline bitfld.long 0x8 1. "WRITE_COMPLETED_FLAG,WRITE_COMPLETED_FLAG: flags detection of write request completed" "0,1" newline bitfld.long 0x8 0. "CMD_TRANSMISSION_FLAG,CMD_TRANSMISSION_FLAG: flags cmd_transmission" "0,1" line.long 0xC "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_rd_sts_flag,Direct command read status bits" bitfld.long 0xC 8. "ERR_EOT_WITH_ERR_FLAG,ERR_EOT_WITH_ERR_FLAG: flags err_eot_with_err" "0,1" newline bitfld.long 0xC 7. "ERR_MISSING_EOT_FLAG,ERR_MISSING_EOT_FLAG: flags err_missing_eot" "0,1" newline bitfld.long 0xC 6. "ERR_WRONG_LENGTH_FLAG,ERR_WRONG_LENGTH_FLAG: flags err_wrong_length" "0,1" newline bitfld.long 0xC 5. "ERR_OVERSIZE_FLAG,ERR_OVERSIZE_FLAG: flags err_oversize" "0,1" newline bitfld.long 0xC 4. "ERR_RECEIVE_FLAG,ERR_RECEIVE_FLAG: flags err_receive" "0,1" newline bitfld.long 0xC 3. "ERR_UNDECODABLE_FLAG,ERR_UNDECODABLE_FLAG: flags err_undecodable" "0,1" newline bitfld.long 0xC 2. "ERR_CHECKSUM_FLAG,ERR_CHECKSUM_FLAG: flags err_checksum" "0,1" newline bitfld.long 0xC 1. "ERR_UNCORRECTABLE_FLAG,ERR_UNCORRECTABLE_FLAG: flags err_uncorrectable" "0,1" newline bitfld.long 0xC 0. "ERR_FIXED_FLAG,ERR_FIXED_FLAG: flags err_fixed" "0,1" line.long 0x10 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_mode_sts_flag,Video Mode status flag" bitfld.long 0x10 10. "FLAG_VSG_RECOVERY,FLAG_VSG_RECOVERY: lags vsg_recovery" "0,1" newline bitfld.long 0x10 9. "ERR_VRS_WRONG_LENGTH_FLAG,ERR_VRS_WRONG_LENGTH_FLAG: flags err_vrs_wrong_length" "0,1" newline bitfld.long 0x10 8. "ERR_LONGREAD_FLAG,ERR_LONGREAD_FLAG: flags err_longread" "0,1" newline bitfld.long 0x10 7. "ERR_LONGWRITE_FLAG,ERR_LONGWRITE_FLAG: flags err_longwrite" "0,1" newline bitfld.long 0x10 6. "ERR_SHORTWRITE_FLAG,ERR_SHORTWRITE_FLAG: flags err_shortwrite" "0,1" newline bitfld.long 0x10 5. "ERR_SMALL_HEIGHT_FLAG,ERR_SMALL_HEIGHT_FLAG: flags the detection of unaligned line number" "0,1" newline bitfld.long 0x10 4. "ERR_SMALL_LENGTH_FLAG,ERR_SMALL_LENGTH_FLAG: flags the detection of unaligned size" "0,1" newline bitfld.long 0x10 3. "ERR_MISS_VSYNC_FLAG,ERR_MISS_VSYNC_FLAG: flags missing VSYNC" "0,1" newline bitfld.long 0x10 2. "ERR_MISSING_HSYNC_FLAG,ERR_MISSING_HSYNC_FLAG: flags missing HSYNC" "0,1" newline bitfld.long 0x10 1. "ERR_MISSING_DATA_FLAG,ERR_MISSING_DATA_FLAG: flags data miss" "0,1" newline bitfld.long 0x10 0. "VSG_STS_FLAG,VSG_STS_FLAG: flags VSG status" "0,1" line.long 0x14 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_tg_sts_flag,TVG status Flags" bitfld.long 0x14 0. "TVG_STS_FLAG,TVG_STS_FLAG: Indicates TVG status observation" "0,1" line.long 0x18 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_dphy_err_flag,Errors output from D_PHY lanes - flags error bit" bitfld.long 0x18 25. "ERR_CONT_LP1_4_FLAG,ERR_CONT_LP1_4_FLAG" "0,1" newline bitfld.long 0x18 24. "ERR_CONT_LP1_3_FLAG,ERR_CONT_LP1_3_FLAG" "0,1" newline bitfld.long 0x18 23. "ERR_CONT_LP1_2_FLAG,ERR_CONT_LP1_2_FLAG" "0,1" newline bitfld.long 0x18 22. "ERR_CONT_LP1_1_FLAG,ERR_CONT_LP1_1_FLAG" "0,1" newline bitfld.long 0x18 21. "ERR_CONT_LP0_4_FLAG,ERR_CONT_LP0_4_FLAG" "0,1" newline bitfld.long 0x18 20. "ERR_CONT_LP0_3_FLAG,ERR_CONT_LP0_3_FLAG" "0,1" newline bitfld.long 0x18 19. "ERR_CONT_LP0_2_FLAG,ERR_CONT_LP0_2_FLAG" "0,1" newline bitfld.long 0x18 18. "ERR_CONT_LP0_1_FLAG,ERR_CONT_LP0_1_FLAG" "0,1" newline bitfld.long 0x18 17. "ERR_CONTROL_4_FLAG,ERR_CONTROL_4_FLAG" "0,1" newline bitfld.long 0x18 16. "ERR_CONTROL_3_FLAG,ERR_CONTROL_3_FLAG" "0,1" newline bitfld.long 0x18 15. "ERR_CONTROL_2_FLAG,ERR_CONTROL_2_FLAG" "0,1" newline bitfld.long 0x18 14. "ERR_CONTROL_1_FLAG,ERR_CONTROL_1_FLAG" "0,1" newline bitfld.long 0x18 13. "ERR_SYNCESC_4_FLAG,ERR_SYNCESC_4_FLAG" "0,1" newline bitfld.long 0x18 12. "ERR_SYNCESC_3_FLAG,ERR_SYNCESC_3_FLAG" "0,1" newline bitfld.long 0x18 11. "ERR_SYNCESC_2_FLAG,ERR_SYNCESC_2_FLAG" "0,1" newline bitfld.long 0x18 10. "ERR_SYNCESC_1_FLAG,ERR_SYNCESC_1_FLAG" "0,1" newline bitfld.long 0x18 9. "ERR_ESC_4_FLAG,ERR_ESC_4_FLAG" "0,1" newline bitfld.long 0x18 8. "ERR_ESC_3_FLAG,ERR_ESC_3_FLAG" "0,1" newline bitfld.long 0x18 7. "ERR_ESC_2_FLAG,ERR_ESC_2_FLAG" "0,1" newline bitfld.long 0x18 6. "ERR_ESC_1_FLAG,ERR_ESC_1_FLAG" "0,1" rgroup.long 0x1A0++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_dpi_irq_en,DPI interrupt enable" bitfld.long 0x0 0. "PIXEL_BUF_OVERFLOW_IRQ_EN,Enable DPI FIFO Overflow interrupt" "0,1" rgroup.long 0x1A4++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_dpi_irq_clr,DPI interrupt clear register" bitfld.long 0x0 0. "PIXEL_BUF_OVERFLOW_IRQ_CLR,Clear DPI FIFO Overflow interrupt" "0,1" rgroup.long 0x1A8++0x7 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_dpi_irq_sts,DPI interrupt status" bitfld.long 0x0 0. "PIXEL_BUF_OVERFLOW_STS,Status of DPI FIFO Overflow interrupt" "0,1" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_dpi_cfg,DPI interface configuration information" hexmask.long.word 0x4 16.--31. 1. "DPI_CFG_FIFODEPTH,DPI FIFO depth - configuration paramter" newline hexmask.long.word 0x4 0.--15. 1. "DPI_CFG_FIFO_LEVEL,DPI FIFO fill level - can be read mid-line for debug purposes to allow adjustment of settings" rgroup.long 0x1F0++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_test_generic,Generic test control and status register" hexmask.long.word 0x0 16.--31. 1. "STATUS,Test status - Value of test_generic_status input" newline hexmask.long.word 0x0 0.--15. 1. "CTRL,Test control - Drives test_generic_ctrl output" rgroup.long 0x1FC++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_id_reg,ID register for Controller" hexmask.long.word 0x0 20.--31. 1. "REV_VENDOR_ID,VENDOR_ID: IP vendor ID affected to CadenceIP [reset = 0xCAD]." newline hexmask.long.byte 0x0 12.--19. 1. "REV_PRODUCT_ID,PRODUCT_ID: unique IP identifier within IP portfolio [reset = 0xD5]." newline hexmask.long.byte 0x0 8.--11. 1. "REV_HARDWARE,H: Hardware revision number [reset = 0x1]." newline hexmask.long.byte 0x0 4.--7. 1. "REV_X,X: Major revision value [reset = 0x3]." newline hexmask.long.byte 0x0 0.--3. 1. "REV_Y,Y: Minor revision value [reset = 0x1]." rgroup.long 0x200++0x13 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_int_status,ASF Interrupt Status Register. This register indicates the source of ASF interrupts. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register the.." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x0 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1" newline bitfld.long 0x0 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1" newline bitfld.long 0x0 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1" newline bitfld.long 0x0 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x0 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1" newline bitfld.long 0x0 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x0 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_int_raw_status,ASF Interrupt Raw Status Register. A bit set in this raw register indicates a source of ASF fault in the corresponding feature. Writing to either raw or masked status registers. clear both registers." hexmask.long 0x4 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x4 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1" newline bitfld.long 0x4 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1" newline bitfld.long 0x4 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1" newline bitfld.long 0x4 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x4 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1" newline bitfld.long 0x4 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x4 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1" line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_int_mask,The ASF interrupt mask register indicating which interrupt bits in the ASF interrupt status register are masked. All bits are set at reset. Clear the individual bit to enable the corresponding interrupt." hexmask.long 0x8 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x8 6. "ASF_INTEGRITY_ERR_MASK,Mask bit for integrity error interrupt" "0,1" newline bitfld.long 0x8 5. "ASF_PROTOCOL_ERR_MASK,Mask bit for protocol error interrupt." "0,1" newline bitfld.long 0x8 4. "ASF_TRANS_TO_ERR_MASK,Mask bit for transaction timeouts error interrupt." "0,1" newline bitfld.long 0x8 3. "ASF_CSR_ERR_MASK,Mask bit for configuration and status registers error interrupt." "0,1" newline bitfld.long 0x8 2. "ASF_DAP_ERR_MASK,Mask bit for data and address paths parity error interrupt." "0,1" newline bitfld.long 0x8 1. "ASF_SRAM_UNCORR_ERR_MASK,Mask bit for SRAM uncorrectable error interrupt." "0,1" newline bitfld.long 0x8 0. "ASF_SRAM_CORR_ERR_MASK,Mask bit for SRAM correctable error interrupt." "0,1" line.long 0xC "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_int_test,The ASF interrupt test register emulate hardware even. Write one to individual bit to trigger single event in (masked and raw) status registers according to mask and will generate interrupt accordingly." hexmask.long 0xC 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0xC 6. "ASF_INTEGRITY_ERR_TEST,Test bit for integrity error interrupt" "0,1" newline bitfld.long 0xC 5. "ASF_PROTOCOL_ERR_TEST,Test bit for protocol error interrupt." "0,1" newline bitfld.long 0xC 4. "ASF_TRANS_TO_ERR_TEST,Test bit for transaction timeouts error interrupt." "0,1" newline bitfld.long 0xC 3. "ASF_CSR_ERR_TEST,Test bit for configuration and status registers error interrupt." "0,1" newline bitfld.long 0xC 2. "ASF_DAP_ERR_TEST,Test bit for data and address paths parity error interrupt." "0,1" newline bitfld.long 0xC 1. "ASF_SRAM_UNCORR_ERR_TEST,Test bit for SRAM uncorrectable error interrupt." "0,1" newline bitfld.long 0xC 0. "ASF_SRAM_CORR_ERR_TEST,Test bit for SRAM correctable error interrupt." "0,1" line.long 0x10 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_fatal_nonfatal_select,The fatal or non-fatal interrupt register selects whether a fatal (asf_int_fatal) or non-fatal (asf_int_nonfatal) interrupt is triggered. If the bit of the event will be set to one then fatal.." hexmask.long 0x10 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x10 6. "ASF_INTEGRITY_ERR,Enable integrity error interrupt as fatal" "0,1" newline bitfld.long 0x10 5. "ASF_PROTOCOL_ERR,Enable protocol error interrupt as fatal." "0,1" newline bitfld.long 0x10 4. "ASF_TRANS_TO_ERR,Enable transaction timeouts error interrupt as fatal." "0,1" newline bitfld.long 0x10 3. "ASF_CSR_ERR,Enable configuration and status registers error interrupt as fatal." "0,1" newline bitfld.long 0x10 2. "ASF_DAP_ERR,Enable data and address paths parity error interrupt as fatal." "0,1" newline bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR,Enable SRAM uncorrectable error interrupt as fatal." "0,1" newline bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR,Enable SRAM correctable error interrupt as fatal." "0,1" rgroup.long 0x220++0x7 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_sram_corr_fault_status,Status register for SRAM correctable fault. These fields are updated whenever asf_sram_corr_fault input is active." hexmask.long.byte 0x0 24.--31. 1. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault." newline hexmask.long.tbyte 0x0 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault." line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_sram_uncorr_fault_status,Status register for SRAM uncorrectable fault. These fields are updated whenever asf_sram_uncorr_fault input is active." hexmask.long.byte 0x4 24.--31. 1. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault." newline hexmask.long.tbyte 0x4 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault." rgroup.long 0x228++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_sram_fault_stats,Statistics register for SRAM faults. Note that this register clears when software writes to any field." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline hexmask.long.word 0x0 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS,Count of number of correctable errors if implemented. Count value will saturate at 0xffff." rgroup.long 0x230++0xB line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_trans_to_ctrl,Control register to configure the ASF transaction timeout monitors." bitfld.long 0x0 31. "ASF_TRANS_TO_EN,Enable transaction timeout monitoring." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "ASF_TRANS_TO_CTRL,Timer value to use for transaction timeout monitor." line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_trans_to_fault_mask,Control register to mask out ASF transaction timeout faults from triggering interrupts. On reset. all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt.." bitfld.long 0x4 3. "ASF_TRANS_TO_FAULT_3_MASK,Mask register for each ASF transaction timeout fault source." "0,1" newline bitfld.long 0x4 2. "ASF_TRANS_TO_FAULT_2_MASK,Mask register for each ASF transaction timeout fault source." "0,1" newline bitfld.long 0x4 1. "ASF_TRANS_TO_FAULT_1_MASK,Mask register for each ASF transaction timeout fault source." "0,1" newline bitfld.long 0x4 0. "ASF_TRANS_TO_FAULT_0_MASK,Mask register for each ASF transaction timeout fault source." "0,1" line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_trans_to_fault_status,Status register for transaction timeouts fault. If a fault occurs the revelant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit." bitfld.long 0x8 3. "ASF_TRANS_TO_FAULT_3_STATUS,Status bits for transaction timeouts faults." "0,1" newline bitfld.long 0x8 2. "ASF_TRANS_TO_FAULT_2_STATUS,Status bits for transaction timeouts faults." "0,1" newline bitfld.long 0x8 1. "ASF_TRANS_TO_FAULT_1_STATUS,Status bits for transaction timeouts faults." "0,1" newline bitfld.long 0x8 0. "ASF_TRANS_TO_FAULT_0_STATUS,Status bits for transaction timeouts faults." "0,1" rgroup.long 0x240++0x7 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_protocol_fault_mask,Control register to mask out ASF Protocol faults from triggering interrupts. On reset. all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt source. The.." bitfld.long 0x0 3. "ASF_PROTOCOL_FAULT_3_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 2. "ASF_PROTOCOL_FAULT_2_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 1. "ASF_PROTOCOL_FAULT_1_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 0. "ASF_PROTOCOL_FAULT_0_MASK,Mask register for each ASF protocol fault source." "0,1" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_protocol_fault_status,Status register for protocol faults. If a fault occurs the revelant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit" bitfld.long 0x4 3. "ASF_PROTOCOL_FAULT_3_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 2. "ASF_PROTOCOL_FAULT_2_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 1. "ASF_PROTOCOL_FAULT_1_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 0. "ASF_PROTOCOL_FAULT_0_STATUS,Status bits for protocol faults." "0,1" tree.end tree.end tree "DSS_DSI0_DSI_WRAP_MMR_VBUSP_CFG_DSI_WRAP (DSS_DSI0_DSI_WRAP_MMR_VBUSP_CFG_DSI_WRAP)" base ad:0x4710000 rgroup.long 0x0++0x3 line.long 0x0 "DSI_WRAP_MMR__VBUSP_CFG__DSI_WRAP_revision,The REVISION register contains the DSI revision number and PID" hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID Field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Revision" bitfld.long 0x0 8.--10. "REVMAJOR,Major Revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Revision" rgroup.long 0x4++0xB line.long 0x0 "DSI_WRAP_MMR__VBUSP_CFG__DSI_WRAP_DPI_CONTROL,Controls the DPI Video Input ports of the DSI Wrapper" bitfld.long 0x0 4. "DSI2_MUX_SEL,Select between DPI-1 and DPI-2 to drive the DPI input of DSITX2" "0,1" bitfld.long 0x0 0. "DPI_0_EN,Enable for DPI-0 input" "0,1" line.long 0x4 "DSI_WRAP_MMR__VBUSP_CFG__DSI_WRAP_DSC_CONTROL,Controls the DSC Encoder for DSI" line.long 0x8 "DSI_WRAP_MMR__VBUSP_CFG__DSI_WRAP_DPI_SECURE,Controls the DPI Video Input ports SECURE settings" bitfld.long 0x8 1. "DPI_0_SECURE_VIOLATION,SECURE VIOLATION status for DPI-0 input. Write-1 to clear the status" "0,1" bitfld.long 0x8 0. "DPI_0_SECURE,SECURE bit for DPI-0 input" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "DSI_WRAP_MMR__VBUSP_CFG__DSI_WRAP_DSI_0_ASF_STATUS,ASF Status" bitfld.long 0x0 6. "INTEGRITY_ERR,INTEGRITY_ERR" "0,1" bitfld.long 0x0 5. "PROTOCOL_ERR,PROTOCOL_ERR" "0,1" bitfld.long 0x0 4. "TRANS_TO_ERR,TRANS_TO_ERR" "0,1" newline bitfld.long 0x0 3. "CSR_ERR,CSR_ERR" "0,1" bitfld.long 0x0 2. "DAP_ERR,DAP_ERR" "0,1" bitfld.long 0x0 1. "SRAM_UNCORR_ERR,SRAM_UNCORR_ERR" "0,1" newline bitfld.long 0x0 0. "SRAM_CORR_ERR,SRAM_CORR_ERR" "0,1" tree.end tree.end tree "DSS_DSI1_DSI" tree "DSS_DSI1_DSI_TOP" tree "DSS_DSI1_DSI_TOP_ECC_AGGR_SYS_CFG (DSS_DSI1_DSI_TOP_ECC_AGGR_SYS_CFG)" base ad:0x4701000 rgroup.long 0x0++0x3 line.long 0x0 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "EDC_CTRL_SYS_PEND,Interrupt Pending Status for edc_ctrl_sys_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "EDC_CTRL_SYS_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_sys_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "EDC_CTRL_SYS_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_sys_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "EDC_CTRL_SYS_PEND,Interrupt Pending Status for edc_ctrl_sys_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "EDC_CTRL_SYS_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_sys_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "EDC_CTRL_SYS_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_sys_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "DSI_TOP_ECC_AGGR_SYS__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "DSS_DSI1_DSI_TOP_VBUSP_CFG_DSI_0_DSI (DSS_DSI1_DSI_TOP_VBUSP_CFG_DSI_0_DSI)" base ad:0x4900000 rgroup.long 0x0++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_ip_conf,IP Configuration for Controller" bitfld.long 0x0 31. "ASF_CONFIG,Active Safety Features [ASF] Configuration: 0 = None; 1 = Full ASF." "0: None;,1: Full ASF" newline hexmask.long.byte 0x0 26.--30. 1. "SP_HS_FIFO_DEPTH,SP_HS_FIFO_DEPTH : HS FIFO depth in sending path." newline hexmask.long.byte 0x0 21.--25. 1. "SP_LP_FIFO_DEPTH,SP_LP_FIFO_DEPTH : LP FIFO depth in sending path." newline hexmask.long.byte 0x0 16.--20. 1. "VRS_FIFO_DEPTH,VRS_FIFO_DEPTH : FIFO depth in the VRS block." newline bitfld.long 0x0 13.--15. "DIRCMD_FIFO_DEPTH,Direct Command FIFO Depth [2:0]. Depth in bytes = 2^[value+2]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12. "INTERFACE_DATASIZE,SDI interface data width: 0 = 16 bit 1 = 32bit" "0,1" newline bitfld.long 0x0 10.--11. "DATAPATH_SIZE,Internal Datapath.width 00 - 32 bit 01 - 16bit 11 - 8 Bits." "0,1,2,3" newline bitfld.long 0x0 8.--9. "NUM_INTERFACE,Max Number of SDI interfaces [1-4] = [value+1]" "0,1,2,3" newline bitfld.long 0x0 6.--7. "MAX_LANE_NB,Max Number of Lanes [1-4] = [value+1]" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "RX_FIFO_DEPTH,RX FIFO Depth [5:0]" rgroup.long 0x4++0x1F line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_main_data_ctl,Main Control - main control setting for datapath" bitfld.long 0x0 25. "TE_MIPI_POLLING_EN,TE_MIPI_POLLING_EN: enables TE Polling feature following MIPI recommendations [polling by software]" "0,1" newline bitfld.long 0x0 24. "TE_HW_POLLING_EN,TE_HW_POLLING_EN: enables TE Polling feature following internal solution" "0,1" newline bitfld.long 0x0 18. "DISP_EOT_GEN,DISP_EOT_GEN: display adds an EOT packet to its LPDT transfers" "0,1" newline bitfld.long 0x0 17. "HOST_EOT_GEN,HOST_EOT_GEN: generates or not the EOT packet after a transfer in HS." "0,1" newline bitfld.long 0x0 16. "DISP_GEN_CHECKSUM,DISP_GEN_CHECKSUM: display generates checksum on its response packets." "0,1" newline bitfld.long 0x0 15. "DISP_GEN_ECC,DISP_GEN_ECC: display generates ECC on its response packets" "0,1" newline bitfld.long 0x0 14. "BTA_EN,BTA_EN: enables BTA" "0,1" newline bitfld.long 0x0 13. "READ_EN,READ_EN: enables read operation" "0,1" newline bitfld.long 0x0 12. "REG_TE_EN,REG_TE_EN: enables Tearing Effect from register" "0,1" newline bitfld.long 0x0 10. "SPLIT_PANEL_MODE,SPLIT_PANEL_MODE: when enabled DSC stage controls data for split panel signle DPHY link" "0,1" newline bitfld.long 0x0 9. "IF3_TE_EN,IF3_TE_EN: enables Tearing Effect on interface 3. Note TE on all SDI interfaces is not supported and should be avoided" "0,1" newline bitfld.long 0x0 8. "IF1_TE_EN,IF1_TE_EN: enables Tearing Effect on interface 1. Note TE on all SDI interfaces is not supported and should be avoided" "0,1" newline bitfld.long 0x0 6. "TVG_SEL,TVG_SEL: Test Video Generator is enabled [it is not the start signal!] - should not be set if if1_en = 1 and if1_mode = 1 [see MCTL_MAIN_EN register ]" "0,1" newline bitfld.long 0x0 5. "VID_EN,VID_EN: enables the video stream generator" "0,1" newline bitfld.long 0x0 2.--3. "VID_IF_SELECT,VID_IF_SELECT: Determines which video interface is active [00 : SDI 01 : DPI 10 : DSC]" "0: SDI,1: DPI,?,?" newline bitfld.long 0x0 1. "SDI_IF_VID_MODE,SDI_IF_VID_MODE:1: selected interface is in video mode 0: selected interface is in command mode]" "0: selected interface is in command mode],1: selected interface is in video mode" newline bitfld.long 0x0 0. "LINK_EN,LINK_EN: enables [or not] the link]" "0,1" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_main_phy_ctl,Main control setting for the physical lanes and drive the static signals for D-PHY clock lane" bitfld.long 0x4 30. "HS_SKEWCAL_TIMEOUT_EN,HS_SKEWCAL_TIMEOUT_EN: Activate the HS SkewCal Control to occur after a timeout." "0,1" newline bitfld.long 0x4 29. "HS_SKEWCAL_FORCE_EN,HS_SKEWCAL_FORCE_EN: Force the HS SkewCal Control to occur immediately" "0,1" newline bitfld.long 0x4 28. "HS_SKEWCAL_EN,HS_SKEWCAL_EN: activate the HS SkewCal Control at start of HS Transmission" "0,1" newline bitfld.long 0x4 25. "HS_INVERT_DAT4,HS_INVERT_DAT4: invert HS signal on data lane 4" "0,1" newline bitfld.long 0x4 24. "SWAP_PINS_DAT4,SWAP_PINS_DAT4: swap pins on clock lane 4" "0,1" newline bitfld.long 0x4 23. "HS_INVERT_DAT3,HS_INVERT_DAT3: invert HS signal on data lane 3" "0,1" newline bitfld.long 0x4 22. "SWAP_PINS_DAT3,SWAP_PINS_DAT3: swap pins on clock lane 3" "0,1" newline bitfld.long 0x4 21. "HS_INVERT_DAT2,HS_INVERT_DAT2: invert HS signal on data lane 2" "0,1" newline bitfld.long 0x4 20. "SWAP_PINS_DAT2,SWAP_PINS_DAT2: swap pins on clock lane 2" "0,1" newline bitfld.long 0x4 19. "HS_INVERT_DAT1,HS_INVERT_DAT1: invert HS signal on data lane 1" "?,1: invert HS signal on data lane 1" newline bitfld.long 0x4 18. "SWAP_PINS_DAT1,SWAP_PINS_DAT1: swap pins on data lane 1" "?,1: swap pins on data lane 1" newline bitfld.long 0x4 17. "HS_INVERT_CLK,HS_INVERT_CLK: invert HS signal on clock lane" "0,1" newline bitfld.long 0x4 16. "SWAP_PINS_CLK,SWAP_PINS_CLK: swap pins on clock lane" "0,1" newline hexmask.long.byte 0x4 10.--13. 1. "WAIT_BURST_TIME,WAIT_BURST_TIME: delay to respect between two HS bursts. Value 0 is forbidden" newline bitfld.long 0x4 9. "DAT4_ULPM_EN,DAT4_ULPM_EN: data lane 4 can be switched in ULP mode" "0,1" newline bitfld.long 0x4 8. "DAT3_ULPM_EN,DAT3_ULPM_EN: data lane 3 can be switched in ULP mode" "0,1" newline bitfld.long 0x4 7. "DAT2_ULPM_EN,DAT2_ULPM_EN: data lane 2 can be switched in ULP mode" "0,1" newline bitfld.long 0x4 6. "DAT1_ULPM_EN,DAT1_ULPM_EN: data lane 1 can be switched in ULP mode" "0,1" newline bitfld.long 0x4 5. "CLK_ULPM_EN,CLK_ULPM_EN: specifies that clock lane can be switched in ULP mode [on demand]" "0,1" newline bitfld.long 0x4 4. "CLK_CONTINUOUS,CLK_CONTINUOUS: clock lane should remain in HS sending mode [no return in STOP state]" "0,1" newline bitfld.long 0x4 2. "LANE4_EN,LANE4_EN: enables the fourth lane [ controls DCB FSM]" "0,1" newline bitfld.long 0x4 1. "LANE3_EN,LANE3_EN: enables the third lane [ controls DCB FSM]" "0,1" newline bitfld.long 0x4 0. "LANE2_EN,LANE2_EN: enables the second lane [ controls DCB FSM]" "0,1" line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_main_en,Control start/stop of the DSI link" bitfld.long 0x8 17. "FORCE_STOP_MODE,FORCE_STOP_MODE: when enabled data lanes are forced back in STOP mode - this value should remain asserted for 10 us minimum" "0,1" newline bitfld.long 0x8 16. "CLK_FORCE_STOP,CLK_FORCE_STOP : force clock lanes back in STOP mode - this value should remain asserted for 10 us minimum" "0,1" newline bitfld.long 0x8 15. "IF3_EN,IF3_EN: enables DSC interface [i.e. removes stall signal]" "0,1" newline bitfld.long 0x8 14. "IF2_EN,IF2_EN: enables DPI interface [i.e. removes stall signal]" "0,1" newline bitfld.long 0x8 13. "IF1_EN,IF1_EN: enables SDI interface [i.e. removes stall signal]" "0,1" newline bitfld.long 0x8 12. "DAT4_ULPM_REQ,DAT4_ULPM_REQ: switches data lane 4 in ULP mode" "0,1" newline bitfld.long 0x8 11. "DAT3_ULPM_REQ,DAT3_ULPM_REQ: switches data lane 3 in ULP mode" "0,1" newline bitfld.long 0x8 10. "DAT2_ULPM_REQ,DAT2_ULPM_REQ: switches data lane 2 in ULP mode" "0,1" newline bitfld.long 0x8 9. "DAT1_ULPM_REQ,DAT1_ULPM_REQ: switches data lane 1 in ULP mode" "0,1" newline bitfld.long 0x8 8. "CLKLANE_ULPM_REQ,CLKLANE_ULPM_REQ: switches clock lane in ULP mode" "0,1" newline bitfld.long 0x8 7. "DAT4_EN,DAT4_EN: 1: starts data lane 4 [FSM data lane 4 is stuck in start mode if 0]" "?,1: starts data lane 4 [FSM data lane 4 is stuck in.." newline bitfld.long 0x8 6. "DAT3_EN,DAT3_EN: 1: starts data lane 3 [FSM data lane 3 is stuck in start mode if 0]" "?,1: starts data lane 3 [FSM data lane 3 is stuck in.." newline bitfld.long 0x8 5. "DAT2_EN,DAT2_EN: 1: starts data lane 2 [FSM data lane 2 is stuck in start mode if 0]" "?,1: starts data lane 2 [FSM data lane 2 is stuck in.." newline bitfld.long 0x8 4. "DAT1_EN,DAT1_EN: 1: starts data lane 1 [FSM data lane 1 is stuck in start mode if 0]" "?,1: starts data lane 1 [FSM data lane 1 is stuck in.." newline bitfld.long 0x8 3. "CKLANE_EN,CKLANE_EN: 1: starts the clock lane" "?,1: starts the clock lane" newline bitfld.long 0x8 0. "PLL_START,PLL_START: enables the PLL [when set the PLL is started]" "0,1" line.long 0xC "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_dphy_cfg0,DPHY Power and Reset Control" bitfld.long 0xC 20. "DPHY_C_RSTB,Drives dphy_c_rstb output" "0,1" newline hexmask.long.byte 0xC 16.--19. 1. "DPHY_D_RSTB,Drives dphy_d_rstb output" newline bitfld.long 0xC 10. "DPHY_PLL_PDN,Drives dphy_pll_pdn output" "0,1" newline bitfld.long 0xC 9. "DPHY_CMN_PDN,Drives dphy_cmn_pdn output" "0,1" newline bitfld.long 0xC 8. "DPHY_C_PDN,Drives dphy_c_pdn output" "0,1" newline hexmask.long.byte 0xC 4.--7. 1. "DPHY_D_PDN,Drives dphy_d_pdn output" newline bitfld.long 0xC 1. "DPHY_PLL_PSO,Drives dphy_pll_pso output" "0,1" newline bitfld.long 0xC 0. "DPHY_CMN_PSO,Drives dphy_cmn_pso output" "0,1" line.long 0x10 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_dphy_timeout1,Main DPHY time-out settings. To better understand the way this register is used. please refer to Section :" hexmask.long.tbyte 0x10 4.--21. 1. "HSTX_TO_VAL,HSTX_TO_VAL: HS TX time-out detection value" newline hexmask.long.byte 0x10 0.--3. 1. "CLK_DIV,CLK_DIV: clock division ratio" line.long 0x14 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_dphy_timeout2,To better understand the way this register is used. please refer to Section : DSI checks (DC) - the counters are on tx_byte_hs_clk and not on sys_clk" hexmask.long.tbyte 0x14 0.--17. 1. "LPRX_TO_VAL,LPRX_TO_VAL: LP RX time-out detection value" line.long 0x18 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_ulpout_time,Specify time to leave ULP mode. The time-out is reached when the ulpout counter reaches 1000x xxx_ulpout_time and is based upon the system clock" hexmask.long.word 0x18 9.--17. 1. "DATA_ULPOUT_TIME,DATA_ULPOUT_TIME: specify what the duration is to leave ULP mode is [for data lane[s] in system clock cycles" newline hexmask.long.word 0x18 0.--8. 1. "CKLANE_ULPOUT_TIME,CKLANE_ULPOUT_TIME: specify what the duration is to leave ULP mode is [for clock lane] in system clock cycles" line.long 0x1C "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_3dvideo_ctl,3D Video mode stream control" bitfld.long 0x1C 7. "VID_VSYNC_3D_EN,VID_VSYNC_3D_EN: Enable 3D Control this selects the 3D operation for VSYNC and video data control" "0,1" newline bitfld.long 0x1C 5. "VID_VSYNC_3D_LR,VID_VSYNC_3D_LR: When 3D mode is enabled this allows to choose which field to start the video stream '0' - Data is sent Left first then right '1' - Data is sent Right first then left" "0,1" newline bitfld.long 0x1C 4. "VID_VSYNC_3D_SECOND_EN,VID_VSYNC_3D_SECOND_EN: When 3D mode is enabled this allows to choose if a second VSYNC is enabled between L and R images '0' - No sync pulses between left and right data '1' - Sync pulse [HSYNC .." "0,1" newline bitfld.long 0x1C 2.--3. "VID_VSYNC_3DFORMAT,VID_VSYNC_3DFORMAT: video 3D Format for VSYNC Control Parameter1 '00' - Line Format alternating line of left and right data '01' - Frame Format alternating frames of left and right data '10'.." "0,1,2,3" newline bitfld.long 0x1C 0.--1. "VID_VSYNC_3DMODE,VID_VSYNC_3DMODE: video 3D mode for VSYNC Control Parameter1 '00' - 3D mode Off - 2D Mode only '01' - 3D On - Portrait Orientation '10' - 3D On - Landscape Orientation '11' - Reserved" "0,1,2,3" rgroup.long 0x24++0xB line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_main_sts,Status of the DSI link" bitfld.long 0x0 11. "HS_SKEWCAL_DONE,HS_SKEWCAL_DONE: HS SkewCal Control Done at start of HS Transmission" "0,1" newline bitfld.long 0x0 10. "IF3_UNTERM_PCK,IF3_UNTERM_PCK: Indicates an unterminated packet on DSC interface" "0,1" newline bitfld.long 0x0 9. "IF2_UNTERM_PCK,IF2_UNTERM_PCK: Indicates an unterminated packet on DPI interface" "0,1" newline bitfld.long 0x0 8. "IF1_UNTERM_PCK,IF1_UNTERM_PCK: Indicates an unterminated packet on SDI Interface" "0,1" newline bitfld.long 0x0 7. "LPRX_TO_ERR,LPRX_TO_ERR: Indicates an LP_RX time-out error" "0,1" newline bitfld.long 0x0 6. "HSTX_TO_ERR,HSTX_TO_ERR: Indicates an HS_TX time-out error" "0,1" newline bitfld.long 0x0 5. "DAT4_READY,DAT4_READY: Indicates data lane 4 is ready" "0,1" newline bitfld.long 0x0 4. "DAT3_READY,DAT3_READY: Indicates data lane 3 is ready" "0,1" newline bitfld.long 0x0 3. "DAT2_READY,DAT2_READY: Indicates data lane 2 is ready" "0,1" newline bitfld.long 0x0 2. "DAT1_READY,DAT1_READY: Indicates data lane 1 is ready" "0,1" newline bitfld.long 0x0 1. "CLKLANE_READY,CLKLANE_READY: Indicates the clock lane is ready [normal DSI operation can start]" "0,1" newline bitfld.long 0x0 0. "PLL_LCK,PLL_LCK: Indicates PLL is locked - data coming from DCB [if DSI link is PLL master] or copy of pll_en [if DSI link is slave]" "0,1" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_dphy_err,Errors reported from DPHY lanes - See description in DPHY inputs and outputs" bitfld.long 0x4 25. "ERR_CONT_LP1_4,ERR_CONT_LP1_4" "0,1" newline bitfld.long 0x4 24. "ERR_CONT_LP1_3,ERR_CONT_LP1_3" "0,1" newline bitfld.long 0x4 23. "ERR_CONT_LP1_2,ERR_CONT_LP1_2" "0,1" newline bitfld.long 0x4 22. "ERR_CONT_LP1_1,ERR_CONT_LP1_1" "0,1" newline bitfld.long 0x4 21. "ERR_CONT_LP0_4,ERR_CONT_LP0_4" "0,1" newline bitfld.long 0x4 20. "ERR_CONT_LP0_3,ERR_CONT_LP0_3" "0,1" newline bitfld.long 0x4 19. "ERR_CONT_LP0_2,ERR_CONT_LP0_2" "0,1" newline bitfld.long 0x4 18. "ERR_CONT_LP0_1,ERR_CONT_LP0_1" "0,1" newline bitfld.long 0x4 17. "ERR_CONTROL_4,ERR_CONTROL_4" "0,1" newline bitfld.long 0x4 16. "ERR_CONTROL_3,ERR_CONTROL_3" "0,1" newline bitfld.long 0x4 15. "ERR_CONTROL_2,ERR_CONTROL_2" "0,1" newline bitfld.long 0x4 14. "ERR_CONTROL_1,ERR_CONTROL_1" "0,1" newline bitfld.long 0x4 13. "ERR_SYNCESC_4,ERR_SYNCESC_4" "0,1" newline bitfld.long 0x4 12. "ERR_SYNCESC_3,ERR_SYNCESC_3" "0,1" newline bitfld.long 0x4 11. "ERR_SYNCESC_2,ERR_SYNCESC_2" "0,1" newline bitfld.long 0x4 10. "ERR_SYNCESC_1,ERR_SYNCESC_1" "0,1" newline bitfld.long 0x4 9. "ERR_ESC_4,ERR_ESC_4" "0,1" newline bitfld.long 0x4 8. "ERR_ESC_3,ERR_ESC_3" "0,1" newline bitfld.long 0x4 7. "ERR_ESC_2,ERR_ESC_2" "0,1" newline bitfld.long 0x4 6. "ERR_ESC_1,ERR_ESC_1" "0,1" line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_lane_sts,DPHY Lane and PLL status information" bitfld.long 0x8 18. "PPI_C_TX_READY_HS,Value of ppi_c_tx_ready_hs input" "0,1" newline bitfld.long 0x8 17. "DPHY_PLL_LOCK,Value of dphy_pll_lock input" "0,1" newline hexmask.long.byte 0x8 12.--15. 1. "PPI_D_RX_ULPS_ESC,Value of ppi_d_rx_ulps_esc input" newline bitfld.long 0x8 9.--10. "DATLANE4_STATE,DATLANE4_STATE: state of the data lane 4 [00: start / 01: idle / 10: write / 11: ULPM]" "0: start /,1: idle /,?,?" newline bitfld.long 0x8 7.--8. "DATLANE3_STATE,DATLANE3_STATE: state of the data lane 3 [00: start / 01: idle / 10: write / 11: ULPM]" "0: start /,1: idle /,?,?" newline bitfld.long 0x8 5.--6. "DATLANE2_STATE,DATLANE2_STATE: state of the data lane 2 [00: start / 01: idle / 10: write / 11: ULPM]" "0: start /,1: idle /,?,?" newline bitfld.long 0x8 2.--4. "DATLANE1_STATE,DATLANE1_STATE: state of the data lane 1 [000: start / 001: idle / 010: write / 011: ULPM / 100: read]" "0: start /,1: idle /,?,?,?,?,?,?" newline bitfld.long 0x8 0.--1. "CLKLANE_STATE,CLKLANE_STATE: state of the clock lane [00: start / 01: idle / 10: HS / 11: ULPM]" "0: start /,1: idle /,?,?" rgroup.long 0x30++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_dsc_mode_ctl,DSC Mode Control register" bitfld.long 0x0 0. "DSC_MODE_EN,Enable DSC Mode Controls" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_dsc_cmd_send,DSC Command Control register. Write one to perform PPS set transfer or Execute Queue commands" bitfld.long 0x0 1. "DSC_SEND_PPS,Send PPS Command and Payload to the display" "0,1" newline bitfld.long 0x0 0. "DSC_EXECUTE_QUEUE,Send Execute Queue Command to Synchonise the display drivers" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_dsc_pps_wrdat,DSC PPS Write data to outgoing FIFO Buffer. byte 0 to 3; applicable to either Write or Read commands." hexmask.long.byte 0x0 24.--31. 1. "PPS_WRDAT3,WRDAT3: 4th byte to be sent as part of PPS payload [stored in a FIFO]" newline hexmask.long.byte 0x0 16.--23. 1. "PPS_WRDAT2,WRDAT2: 3rd byte to be sent as part of PPS payload [stored in a FIFO]" newline hexmask.long.byte 0x0 8.--15. 1. "PPS_WRDAT1,WRDAT1: 2nd byte to be sent as part of PPS payload [stored in a FIFO]" newline hexmask.long.byte 0x0 0.--7. 1. "PPS_WRDAT0,WRDAT0: 1st byte to be sent as part of PPS payload [stored in a FIFO]" rgroup.long 0x3C++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_dsc_mode_sts,DSC Event Status Register" bitfld.long 0x0 1. "DSC_PPS_DONE,DSC PPS Command Sent" "0,1" newline bitfld.long 0x0 0. "DSC_EXEC_DONE,DSC Execute Command Sent" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_dphy_skewcal_timeout,Used in conjunction with HS_SKEWCAL_TIMEOUT_EN from MCTL_MAIN_PHY_CTL to control periodic skew calibration" hexmask.long 0x0 0.--31. 1. "SKEWCAL_TO_VAL,SKEWCAL_TO_VAL: Timeout value" rgroup.long 0x70++0x7 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_cmd_mode_ctl,Command mode control" bitfld.long 0x0 10. "IF3_LP_EN,IF3_LP_EN: enable to send command from DSC interface in LP if possible" "0,1" newline bitfld.long 0x0 9. "IF1_LP_EN,IF1_LP_EN: enable to send command from SDI interface in LP if possible" "0,1" newline bitfld.long 0x0 2.--3. "IF3_ID,IF3_ID: Virtual Channel ID of request from DSC interface command" "0,1,2,3" newline bitfld.long 0x0 0.--1. "IF1_ID,IF1_ID: Virtual Channel ID of request from SDI interface command" "0,1,2,3" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_cmd_mode_ctl2,Command mode control" hexmask.long.word 0x4 11.--22. 1. "TE_TIMEOUT,TE_TIMEOUT : on TE request - length of TE response window before timeout." newline hexmask.long.byte 0x4 3.--10. 1. "FIL_VALUE,FIL_VALUE: value to use to fill packet during data underrun or to complete unterminated packet [referred as padding value]" newline bitfld.long 0x4 1.--2. "ARB_PRI,ARB_PRI: in fixed mode specify interface with higher priority SDI 01 DSC 10" "0,1,2,3" newline bitfld.long 0x4 0. "ARB_MODE,ARB_MODE: arbitration mode [1: round robin 0: fixed]" "0: fixed],1: round robin" rgroup.long 0x78++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_cmd_mode_sts,Command Mode status" bitfld.long 0x0 4. "ERR_IF1_UNDERRUN,ERR_IF1_UNDERRUN: Indicates a data shortage occurs on IF1" "0,1" newline bitfld.long 0x0 3. "ERR_UNWANTED_RD,ERR_UNWANTED_RD: Indicates a read request was received while read capability was not enabled" "0,1" newline bitfld.long 0x0 2. "ERR_TE_MISS,ERR_TE_MISS: error: TE window time-out" "0,1" newline bitfld.long 0x0 1. "ERR_NO_TE,ERR_NO_TE: error: no TE generated by display" "0,1" newline bitfld.long 0x0 0. "CSM_RUNNING,CSM_RUNNING: Indicates CSM is running - command[s] are being proceeded" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_send,Direct_cmd_send is not a real register. When this address is written (whatever its value is). it signals to the link that a direct command has to be sent." hexmask.long 0x0 0.--31. 1. "DIRECT_CMD_SEND,Initiate the direct command send operation" rgroup.long 0x84++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_main_settings,Main control of the Direct Command function." hexmask.long.byte 0x0 25.--28. 1. "TRIGGER_VAL,TRIGGER_VAL: trigger value if trigger request [see Note about trigger mapping] - signal is one hot encoding [only one bit out of the 4 should be set to 1]." newline bitfld.long 0x0 24. "CMD_LP_EN,CMD_LP_EN: enables LP sending for the command request" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "CMD_SIZE,CMD_SIZE: size in bytes of the command payload. Note that the value written here by software should comply with certain limits. For write operations any value written which is larger than the FIFO depth [direct_cmd_fifodepth.." newline bitfld.long 0x0 14.--15. "CMD_ID,CMD_ID: For a read/write command Virtual Channel of the command" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "CMD_HEAD,CMD_HEAD: For a read/write command datatype of the command" newline bitfld.long 0x0 3. "CMD_LONGNOTSHORT,CMD_LONGNOTSHORT: Tie this to '1' if a long packet has to be generated." "0,1" newline bitfld.long 0x0 0.--2. "CMD_NAT,CMD_NAT: Type of the direct command: 000: write command 001: read command 100: TE request 101: trigger request 110: BTA request" "0: write command,1: read command,?,?,?,?,?,?" rgroup.long 0x88++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_sts,Direct Command Status: To ensure that the observed status bits are coherent and applicable to the last command message sent." hexmask.long.word 0x0 16.--31. 1. "ACK_VAL,ACK_VAL: if an acknowledge with error has been received this field reports its value" newline hexmask.long.byte 0x0 11.--14. 1. "TRIGGER_VAL,TRIGGER_VAL: if a trigger has been received this field reports its value - refer to Note regarding trigger mapping" newline bitfld.long 0x0 10. "READ_COMPLETED_WITH_ERR,READ_COMPLETED_WITH_ERR: read command terminated with error" "0,1" newline bitfld.long 0x0 9. "BTA_FINISHED,BTA_FINISHED: DSI link recovered link master role after a BTA request" "0,1" newline bitfld.long 0x0 8. "BTA_COMPLETED,BTA_COMPLETED: indicates that BTA request completed" "0,1" newline bitfld.long 0x0 7. "TE_RECEIVED,TE_RECEIVED: TE received" "0,1" newline bitfld.long 0x0 6. "TRIGGER_RECEIVED,TRIGGER_RECEIVED: If command with BTA this bit is set if an trigger was received" "0,1" newline bitfld.long 0x0 5. "ACK_WITH_ERR_RECEIVED,ACKNOWLEDGE_WITH_ERR_RECEIVED: If command with BTA this bit is set if an acknowledge with error was received" "0,1" newline bitfld.long 0x0 4. "ACK_RECEIVED,ACKNOWLEDGE_RECEIVED: If command with BTA this bit is set if an acknowledge with no error was received" "0,1" newline bitfld.long 0x0 3. "READ_COMPLETED,READ_COMPLETED: read command request completed" "0,1" newline bitfld.long 0x0 2. "TRIGGER_COMPLETED,TRIGGER_COMPLETED: trigger command request completed" "0,1" newline bitfld.long 0x0 1. "WRITE_COMPLETED,WRITE_COMPLETED: write command request completed" "0,1" newline bitfld.long 0x0 0. "CMD_TRANSMISSION,CMD_TRANSMISSION: a command is being sent" "0,1" rgroup.long 0x8C++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_rd_init,This register is not a real register - when written it stops the read command process by emptying" hexmask.long 0x0 0.--31. 1. "STOP_READ_OPERATION,Stop Read Operation" rgroup.long 0x90++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_wrdat,Write data to outgoing Direct Command FIFO. byte 0 to 3; applicable to either Write or Read commands." hexmask.long.byte 0x0 24.--31. 1. "WRDAT3,WRDAT3: 4th byte to be sent as part of Direct Command [stored in a FIFO]" newline hexmask.long.byte 0x0 16.--23. 1. "WRDAT2,WRDAT2: 3rd byte to be sent as part of Direct Command [stored in a FIFO]" newline hexmask.long.byte 0x0 8.--15. 1. "WRDAT1,WRDAT1: 2nd byte to be sent as part of Direct Command [stored in a FIFO]" newline hexmask.long.byte 0x0 0.--7. 1. "WRDAT0,WRDAT0: 1st byte to be sent as part of Direct Command [stored in a FIFO]" rgroup.long 0x94++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_fifo_rst,Reset the write FIFO. This register is not a real register - when written it reset the FIFO pointer" hexmask.long 0x0 0.--31. 1. "CMD_FIFO_RST,Direct Command FIFO Reset" rgroup.long 0xA0++0xB line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_rddat,Data from incoming Direct Command receive path. byte 0 to 3." hexmask.long.byte 0x0 24.--31. 1. "RDDAT3,RDDAT3: 4th byte from incoming Direct Command receive path" newline hexmask.long.byte 0x0 16.--23. 1. "RDDAT2,RDDAT2: 3rd byte from incoming Direct Command receive path" newline hexmask.long.byte 0x0 8.--15. 1. "RDDAT1,RDDAT1: 2nd byte from incoming Direct Command receive path" newline hexmask.long.byte 0x0 0.--7. 1. "RDDAT0,RDDAT0: 1st byte from incoming Direct Command receive path" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_rd_property,read command characteristics" bitfld.long 0x4 18. "RD_DCSNOTGENERIC,RD_DCSNOTGENERIC: Type of read command [DCS or generic]" "0,1" newline bitfld.long 0x4 16.--17. "RD_ID,RD_ID: Virtual channel of the read received" "0,1,2,3" newline hexmask.long.word 0x4 0.--15. 1. "RD_SIZE,RD_SIZE: Size of the read data received" line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_rd_sts,Status of the read command received. It is recommended to clear direct_cmd_sts" bitfld.long 0x8 8. "ERR_EOT_WITH_ERR,ERR_EOT_WITH_ERR: EOT received with error" "0,1" newline bitfld.long 0x8 7. "ERR_MISSING_EOT,ERR_MISSING_EOT: EOT requested but not received" "0,1" newline bitfld.long 0x8 6. "ERR_WRONG_LENGTH,ERR_WRONG_LENGTH : length error has been detected. This error indicates that a packet has been received which was shorter than the expected length [longer packets than expected will result in ERR_RECEIVE field being set as it is.." "0,1" newline bitfld.long 0x8 5. "ERR_OVERSIZE,ERR_OVERSIZE : packet size exceeds maximum" "0,1" newline bitfld.long 0x8 4. "ERR_RECEIVE,ERR_RECEIVE : received packet not complete. This is a general error flag indicated that packet reception did not complete for some reason. Example conditions: signalling errors [e.g. unexpected change in PPI.." "0,1" newline bitfld.long 0x8 3. "ERR_UNDECODABLE,ERR_UNDECODABLE : command opcode not understood" "0,1" newline bitfld.long 0x8 2. "ERR_CHECKSUM,ERR_CHECKSUM: error[s] detected by checksum" "0,1" newline bitfld.long 0x8 1. "ERR_UNCORRECTABLE,ERR_UNCORRECTABLE : more than 1 error detected by ECC" "0,1" newline bitfld.long 0x8 0. "ERR_FIXED,ERR_FIXED : one error detected and fixed by ECC" "0,1" rgroup.long 0xB0++0xB line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_main_ctl,Video mode main control" bitfld.long 0x0 31. "VID_IGNORE_MISS_VSYNC,VID_IGNORE_MISSING_SYNC: When mode is enabled this allows the video stream to go to IDLE during VFP and wait for new VSYNC without link failing to recovery" "0,1" newline bitfld.long 0x0 25.--26. "RECOVERY_MODE,RECOVERY_MODE: specify recovery mode" "0,1,2,3" newline bitfld.long 0x0 23.--24. "REG_BLKEOL_MODE,REG_BLKEOL_MODE: behavior during end of line in burst mode - same coding as reg_blkline_mode" "0,1,2,3" newline bitfld.long 0x0 21.--22. "REG_BLKLINE_MODE,REG_BLKLINE_MODE : behavior during blanking time [1x: LP 01: blanking packet - 00: NULL packet]" "0: NULL packet],1: blanking packet,?,?" newline bitfld.long 0x0 20. "SYNC_PULSE_HORIZONTAL,SYNC_PULSE_HORIZONTAL: syncs are pulse [1] or event [0] all the time [DSI protocol v1.00..._r6 and later] - to be set only when sync_pulse_active = 1" "0,1" newline bitfld.long 0x0 19. "SYNC_PULSE_ACTIVE,SYNC_PULSE_ACTIVE: syncs are pulse [1] or event [0] during active area [DSI protocol v1.00..._r3 and before]" "0,1" newline bitfld.long 0x0 18. "BURST_MODE,BURST_MODE: signals if system works in burst mode or not" "0,1" newline hexmask.long.byte 0x0 14.--17. 1. "VID_PIXEL_MODE,VID_PIXEL_MODE: 0000: 16 bits RGB - 0001: 18 bits RGB.." newline hexmask.long.byte 0x0 8.--13. 1. "HEADER,HEADER : specify the datatype of RGB packets" newline bitfld.long 0x0 4.--5. "VID_ID,VID_ID : specify the Virtual Channel Identifier of the video packets" "0,1,2,3" newline bitfld.long 0x0 2.--3. "STOP_MODE,STOP_MODE : video stop point [see description in Video Stream Generator [VSG] section] .[The configurations where the frame stops at the end of any line and at the end of the last active line - start_mode in [1;2] - are.." "0,1,2,3" newline bitfld.long 0x0 0.--1. "START_MODE,START_MODE: video entry point [see description in Video Stream Generator [VSG] section][The configuration where the frame starts with a VFP - start_mode=1 - is being deprecated thus not verified anymore]" "?,1: is being deprecated,?,?" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_vsize1,Image vertical Sync and Blanking settings" hexmask.long.byte 0x4 12.--19. 1. "VFP_LENGTH,VFP_LENGTH: length of the VFP [in lines]" newline hexmask.long.byte 0x4 6.--11. 1. "VBP_LENGTH,VBP_LENGTH: length of the VBP [in lines]" newline hexmask.long.byte 0x4 0.--5. 1. "VSA_LENGTH,VSA_LENGTH: duration of the VSYNC pulse [in lines]" line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_vsize2,Image vertical active line setting" hexmask.long.word 0x8 0.--12. 1. "VACT_LENGTH,VACT_LENGTH: vertical length of active area [in line]" rgroup.long 0xC0++0x7 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_hsize1,Image horizontal sync and Blanking setting" hexmask.long.word 0x0 16.--31. 1. "HBP_LENGTH,HBP_LENGTH: length of HBP [in bytes] - if 0 HBP packet is sent with 0 payload" newline hexmask.long.word 0x0 0.--9. 1. "HSA_LENGTH,HSA_LENGTH: duration of HSYNC pulse [in bytes]" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_hsize2,Image horizontal byte size setting" hexmask.long.word 0x4 16.--26. 1. "HFP_LENGTH,HFP_LENGTH: length of HFP [in bytes] - if 0 no HFP packet is sent" newline hexmask.long.word 0x4 0.--14. 1. "RGB_SIZE,RGB_SIZE: size [in byte] of the RGB packet" rgroup.long 0xCC++0x7 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_blksize1,blanking packet size" hexmask.long.word 0x0 15.--29. 1. "BLKEOL_PCK,BLKEOL_PCK: packet length [in byte] on end of line if burst mode [reg_blkeol_mode = 0b0x]" newline hexmask.long.word 0x0 0.--14. 1. "BLKLINE_EVENT_PCK,BLKLINE_EVENT_PCK: packet length [in byte] in blanking line if line has to be filled with a packet [reg_blkline_mode = 0b0x] and sync is an event Event mode Blank line.." line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_blksize2,Pulse Mode blanking packet size" hexmask.long.word 0x4 0.--14. 1. "BLKLINE_PULSE_PCK,BLKLINE_PULSE_PCK: packet length in blanking line if line has to be filled with a packet [reg_blkline_mode = 0b0x] and sync is a pulse Pulse mode Blank.." rgroup.long 0xD8++0xF line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_pck_time,Packet duration" hexmask.long.word 0x0 0.--14. 1. "BLKEOL_DURATION,BLKEOL_DURATION: specify the duration in clock cycles of the BLLP period [used for burst mode]" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_dphy_time,Time of D-PHY behavior for wakeup time and Line duration for LP during horozontal blanking lines" hexmask.long.word 0x4 17.--27. 1. "REG_WAKEUP_TIME,REG_WAKEUP_TIME: estimated time [in clock cycles] to perform LP->HS on D-PHY |___________reg_wakeup_time________________| | Clk Request.." newline hexmask.long.tbyte 0x4 0.--16. 1. "REG_LINE_DURATION,REG_LINE_DURATION: duration -in clock cycles - of the blanking area for VSA/VBP and VFP lines - considered when reg_blkline_mode = 1b1x Pulse mode Blank LP line EOT disabled.." line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_err_color1,error color (green and red)" hexmask.long.word 0x8 12.--23. 1. "COL_GREEN,COL_GREEN: green component of the fill color" newline hexmask.long.word 0x8 0.--11. 1. "COL_RED,COL_RED: red component of the fill color" line.long 0xC "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_err_color2,error color (blue and padding)" hexmask.long.word 0xC 12.--23. 1. "PAD_VALUE,PAD_VALUE: byte used to pad data [when system does not know exactly where it is]" newline hexmask.long.word 0xC 0.--11. 1. "COL_BLUE,COL_BLUE: blue component of the fill color" rgroup.long 0xE8++0xB line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_vpos,vertical position" hexmask.long.word 0x0 2.--14. 1. "LINE_VAL,LINE_VAL: line number of the current area" newline bitfld.long 0x0 0.--1. "LINE_POS,LINE_POS: position in the frame [see description in Video Stream Generator]" "0,1,2,3" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_hpos,Horizontal Position" hexmask.long.word 0x4 3.--17. 1. "HORIZONTAL_VAL,HORIZONTAL_VAL: position in the current horizontal area [in clock cycles]" newline bitfld.long 0x4 0.--2. "HORIZONTAL_POS,HORIZONTAL_POS: position in the line [see description in Video Stream Generator]" "0,1,2,3,4,5,6,7" line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_mode_sts,Video mode status and error reporting" bitfld.long 0x8 10. "VSG_RECOVERY,VSG_RECOVERY: specifies whether the VSG is in recovery mode or not" "0,1" newline bitfld.long 0x8 9. "ERR_VRS_WRONG_LENGTH,ERR_VRS_WRONG_LENGTH: signals that packets in SDI interface differ from the expected size [as specified by rgb_size]" "0,1" newline bitfld.long 0x8 8. "ERR_LONGREAD,ERR_LONGREAD: signals the read was too long" "0,1" newline bitfld.long 0x8 7. "ERR_LINEWRITE,ERR_LINEWRITE: signals the long packet is too long to pass during a long slot" "0,1" newline bitfld.long 0x8 6. "ERR_BURSTWRITE,ERR_BURSTWRITE: signals a long packet has been sent during active area" "0,1" newline bitfld.long 0x8 5. "REG_ERR_SMALL_HEIGHT,REG_ERR_SMALL_HEIGHT: fewer lines than expected between 2 VSYNC" "0,1" newline bitfld.long 0x8 4. "REG_ERR_SMALL_LENGTH,REG_ERR_SMALL_LENGTH: fewer bytes received than expected between 2 HSYNC. Note that MISSING_DATA error may occur instead of SMALL_LENGTH dependent upon timing." "0,1" newline bitfld.long 0x8 3. "ERR_MISSING_VSYNC,ERR_MISSING_VSYNC: missing VSYNC" "0,1" newline bitfld.long 0x8 2. "ERR_MISSING_HSYNC,ERR_MISSING_HSYNC: missing HSYNC" "0,1" newline bitfld.long 0x8 1. "ERR_MISSING_DATA,ERR_MISSING_DATA: data starvation at input of the VSG. Note that this error report may also be triggered instead of the SMALL_LENGTH error dependent upon timing." "0,1" newline bitfld.long 0x8 0. "VSG_RUNNING,VSG_RUNNING: VSG is running [1] or stopped [0]" "0,1" rgroup.long 0xF4++0x1F line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_vca_setting1,VCA control register 1" bitfld.long 0x0 16. "BURST_LP,BURST_LP: after an active line the system can switch in LP [1] or should complete the line with NULL packet [0]" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "MAX_BURST_LIMIT,MAX_BURST_LIMIT: size of the 'biggest' burst packet [packet that fits after RGB in burst mode]" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_vca_setting2,VCA control register 2" hexmask.long.word 0x4 16.--31. 1. "MAX_LINE_LIMIT,MAX_LINE_LIMIT: maximum size of the line packet [packet that fits in blanking line]" newline hexmask.long.word 0x4 0.--15. 1. "EXACT_BURST_LIMIT,EXACT_BURST_LIMIT: exact maximum size of the burst packet [packet that fits after RGB in burst mode]" line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_tvg_ctl,Main control of the TVG" bitfld.long 0x8 5.--7. "TVG_STRIPE_SIZE,TVG_STRIPE_SIZE: size of the stripe [in pixels] - defined by 2^reg_tvg_stripe_size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--4. "TVG_MODE,TVG_MODE: TVG display mode : 00 : single color ; 01 : reserved ; 10 : vertical stripes ; 11 horizontal stripes" "0: single color ;,1: reserved ;,?,?" newline bitfld.long 0x8 1.--2. "TVG_STOPMODE,TVG_STOPMODE: stop mode: 00: at end of frame 01: at end of line 1x: immediate" "0: at end of frame,1: at end of line,?,?" newline bitfld.long 0x8 0. "TVG_RUN,TVG_RUN: start/stop of the TVG" "0,1" line.long 0xC "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_tvg_img_size,TVG Generated image size" hexmask.long.word 0xC 16.--28. 1. "TVG_NBLINE,TVG_NBLINE: Number of lines per frame" newline hexmask.long.word 0xC 0.--14. 1. "TVG_LINE_SIZE,TVG_LINE_SIZE: Number of bytes per line" line.long 0x10 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_tvg_color1,Color 1 of the dummy frame G. R" hexmask.long.word 0x10 12.--23. 1. "COL1_GREEN,COL1_GREEN: green component of the color 1" newline hexmask.long.word 0x10 0.--11. 1. "COL1_RED,COL1_RED: red component of the color 1" line.long 0x14 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_tvg_color1_bis,Color 1 of the dummy frame . B" hexmask.long.word 0x14 0.--11. 1. "COL1_BLUE,COL1_BLUE: blue component of the color 1" line.long 0x18 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_tvg_color2,Color 2 of the dummy frame. G. R" hexmask.long.word 0x18 12.--23. 1. "COL2_GREEN,COL2_GREEN: green component of the color 2" newline hexmask.long.word 0x18 0.--11. 1. "COL2_RED,COL2_RED: red component of the color 2" line.long 0x1C "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_tvg_color2_bis,Color 2 of the dummy frame. B" hexmask.long.word 0x1C 0.--11. 1. "COL2_BLUE,COL2_BLUE: blue component of the color 2" rgroup.long 0x114++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_tvg_sts,TVG status register" bitfld.long 0x0 0. "TVG_RUNNING,TVG_RUNNING: status of the TVG" "0,1" rgroup.long 0x130++0x1F line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_main_sts_ctl,Controls the enabling and edge detection of main ctrl status bits" bitfld.long 0x0 25. "IF3_UNTERM_PCK_ERR_EDGE,IF3_UNTERM_PCK_ERR_EDGE: edge detection of if3_unterm_pck_err" "0,1" newline bitfld.long 0x0 24. "IF1_UNTERM_PCK_ERR_EDGE,IF1_UNTERM_PCK_ERR_EDGE: edge detection of if1_unterm_pck_err" "0,1" newline bitfld.long 0x0 23. "LPRX_TO_ERR_EDGE,LPRX_TO_ERR_EDGE: edge detection of LP_RX time-out error" "0,1" newline bitfld.long 0x0 22. "HSTX_TO_ERR_EDGE,HSTX_TO_ERR_EDGE: edge detection of HS_TX time-out error" "0,1" newline bitfld.long 0x0 21. "DAT4_READY_EDGE,DAT4_READY_EDGE: edge detection of dat4_ready" "0,1" newline bitfld.long 0x0 20. "DAT3_READY_EDGE,DAT3_READY_EDGE: edge detection of dat3_ready" "0,1" newline bitfld.long 0x0 19. "DAT2_READY_EDGE,DAT2_READY_EDGE: edge detection of dat2_ready" "0,1" newline bitfld.long 0x0 18. "DAT1_READY_EDGE,DAT1_READY_EDGE: edge detection of dat1_ready" "0,1" newline bitfld.long 0x0 17. "CLKLANE_READY_EDGE,CLKLANE_READY_EDGE: edge detection of clklane_ready" "0,1" newline bitfld.long 0x0 16. "PLL_LOCK_EDGE,PLL_LOCK_EDGE: edge detection of PLL lock" "0,1" newline bitfld.long 0x0 9. "IF3_UNTERM_PCK_ERR_EN,IF3_UNTERM_PCK_ERR_EN: enables if3_unterm_pck_err" "0,1" newline bitfld.long 0x0 8. "IF1_UNTERM_PCK_ERR_EN,IF1_UNTERM_PCK_ERR_EN: enables if1_unterm_pck_err" "0,1" newline bitfld.long 0x0 7. "LPRX_TO_ERR_EN,LPRX_TO_ERR_EN: enables lprx_to_err" "0,1" newline bitfld.long 0x0 6. "HSTX_TO_ERR_EN,HSTX_TO_ERR_EN: enables hstx_to_err" "0,1" newline bitfld.long 0x0 5. "DAT4_READY_EN,DAT4_READY_EN: enables dat4_ready" "0,1" newline bitfld.long 0x0 4. "DAT3_READY_EN,DAT3_READY_EN: enables dat3_ready" "0,1" newline bitfld.long 0x0 3. "DAT2_READY_EN,DAT2_READY_EN: enables dat2_ready" "0,1" newline bitfld.long 0x0 2. "DAT1_READY_EN,DAT1_READY_EN: enables dat1_ready" "0,1" newline bitfld.long 0x0 1. "CLKLANE_READY_EN,CLKLANE_READY_EN: enables clklane_ready" "0,1" newline bitfld.long 0x0 0. "PLL_LOCK_EN,PLL_LOCK_EN: enables PLL lock" "0,1" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_cmd_mode_sts_ctl,Controls the enabling and edge detection of command status bits" bitfld.long 0x4 21. "ERR_IF3_UNDERRUN_EDGE,ERR_IF3_UNDERRUN_EDGE: edge detection of err_IF3_underrun" "0,1" newline bitfld.long 0x4 20. "ERR_IF1_UNDERRUN_EDGE,ERR_IF1_UNDERRUN_EDGE: edge detection of err_IF1_underrun" "0,1" newline bitfld.long 0x4 19. "ERR_UNWANTED_RD_EDGE,ERR_UNWANTED_RD_EDGE: edge detection of err_unwanted_rd" "0,1" newline bitfld.long 0x4 18. "ERR_TE_MISS_EDGE,ERR_TE_MISS_EDGE: edge detection of err_te_miss" "0,1" newline bitfld.long 0x4 17. "ERR_NO_TE_EDGE,ERR_NO_TE_EDGE: edge detection of err_no_te" "0,1" newline bitfld.long 0x4 16. "CSM_RUNNING_EDGE,CSM_RUNNING_EDGE: edge detection of CSM running" "0,1" newline bitfld.long 0x4 5. "ERR_IF3_UNDERRUN_EN,ERR_IF3_UNDERRUN_EN: enables err_IF3_underrun" "0,1" newline bitfld.long 0x4 4. "ERR_IF1_UNDERRUN_EN,ERR_IF1_UNDERRUN_EN: enables err_IF1_underrun" "0,1" newline bitfld.long 0x4 3. "ERR_UNWANTED_RD_EN,ERR_UNWANTED_RD_EN: enables err_unwanted_rd" "0,1" newline bitfld.long 0x4 2. "ERR_TE_MISS_EN,ERR_TE_MISS_EN: enables err_te_miss" "0,1" newline bitfld.long 0x4 1. "ERR_NO_TE_EN,ERR_NO_TE_EN: enables err_no_te" "0,1" newline bitfld.long 0x4 0. "CSM_RUNNING_EN,CSM_RUNNING_EN: enables signaling of CSM running" "0,1" line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_sts_ctl,Controls the enabling and edge detection of Direct Command status bits" bitfld.long 0x8 26. "READ_COMPLETED_WITH_ERR_EDGE,READ_COMPLETED_WITH_ERR_EDGE: edge detection of read detection completed with errors" "0,1" newline bitfld.long 0x8 25. "BTA_FINISHED_EDGE,BTA_FINISHED_EDGE: edge detection of BTA completion detection" "0,1" newline bitfld.long 0x8 24. "BTA_COMPLETED_EDGE,BTA_COMPLETED_EDGE: edge detection of BTA request completed" "0,1" newline bitfld.long 0x8 23. "TE_RECEIVED_EDGE,TE_RECEIVED_EDGE: edge detection of TE received" "0,1" newline bitfld.long 0x8 22. "TRIGGER_RECEIVED_EDGE,TRIGGER_RECEIVED_EDGE: edge detection of trigger" "0,1" newline bitfld.long 0x8 21. "ACKNOWLEDGE_WITH_ERR_EDGE,ACKNOWLEDGE_WITH_ERR_EDGE: edge detection of acknowledge with error" "0,1" newline bitfld.long 0x8 20. "ACKNOWLEDGE_RECEIVED_EDGE,ACKNOWLEDGE_RECEIVED_EDGE: edge detection of acknowledge" "0,1" newline bitfld.long 0x8 19. "READ_COMPLETED_EDGE,READ_COMPLETED_EDGE: edge detection of read request completed" "0,1" newline bitfld.long 0x8 18. "TRIGGER_COMPLETED_EDGE,TRIGGER_COMPLETED_EDGE: edge detection of trigger request completed" "0,1" newline bitfld.long 0x8 17. "WRITE_COMPLETED_EDGE,WRITE_COMPLETED_EDGE: edge detection of detection of write request completed" "0,1" newline bitfld.long 0x8 16. "CMD_TRANSMISSION_EDGE,CMD_TRANSMISSION_EDGE: edge detection of cmd_transmission" "0,1" newline bitfld.long 0x8 10. "READ_COMPLETED_WITH_ERR_EN,READ_COMPLETED_WITH_ERR_EN: enables detection of read completed with errors" "0,1" newline bitfld.long 0x8 9. "BTA_FINISHED_EN,BTA_FINISHED_EN: enables BTA completion detection" "0,1" newline bitfld.long 0x8 8. "BTA_COMPLETED_EN,BTA_COMPLETED_EN: enables BTA request completed" "0,1" newline bitfld.long 0x8 7. "TE_RECEIVED_EN,TE_RECEIVED_EN: enables TE received" "0,1" newline bitfld.long 0x8 6. "TRIGGER_RECEIVED_EN,TRIGGER_RECEIVED_EN: enables trigger" "0,1" newline bitfld.long 0x8 5. "ACKNOWLEDGE_WITH_ERR_EN,ACKNOWLEDGE_WITH_ERR_EN: enables acknowledge with error" "0,1" newline bitfld.long 0x8 4. "ACKNOWLEDGE_RECEIVED_EN,ACKNOWLEDGE_RECEIVED_EN: enables acknowledge" "0,1" newline bitfld.long 0x8 3. "READ_COMPLETED_EN,READ_COMPLETED_EN: enables read request completed" "0,1" newline bitfld.long 0x8 2. "TRIGGER_COMPLETED_EN,TRIGGER_COMPLETED_EN: enables trigger_completed" "0,1" newline bitfld.long 0x8 1. "WRITE_COMPLETED_EN,WRITE_COMPLETED_EN: enables write_completed" "0,1" newline bitfld.long 0x8 0. "CMD_TRANSMISSION_EN,CMD_TRANSMISSION_EN: enables detection of cmd_transmission" "0,1" line.long 0xC "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_rd_sts_ctl,Controls the enabling and edge detection of read commands error" bitfld.long 0xC 24. "ERR_EOT_WITH_ERR_EDGE,ERR_EOT_WITH_ERR_EDGE: edge detection of err_eot_with_err" "0,1" newline bitfld.long 0xC 23. "ERR_MISSING_EOT_EDGE,ERR_MISSING_EOT_EDGE: edge detection of err_missing_eot" "0,1" newline bitfld.long 0xC 22. "ERR_WRONG_LENGTH_EDGE,ERR_WRONG_LENGTH_EDGE: edge detection of err_wrong_length" "0,1" newline bitfld.long 0xC 21. "ERR_OVERSIZE_EDGE,ERR_OVERSIZE_EDGE: edge detection of err_oversize" "0,1" newline bitfld.long 0xC 20. "ERR_RECEIVE_EDGE,ERR_RECEIVE_EDGE: edge detection of err_receive" "0,1" newline bitfld.long 0xC 19. "ERR_UNDECODABLE_EDGE,ERR_UNDECODABLE_EDGE: edge detection of err_undecodable" "0,1" newline bitfld.long 0xC 18. "ERR_CHECKSUM_EDGE,ERR_CHECKSUM_EDGE: edge detection of err_checksum" "0,1" newline bitfld.long 0xC 17. "ERR_UNCORRECTABLE_EDGE,ERR_UNCORRECTABLE_EDGE: edge detection of err_uncorrectable" "0,1" newline bitfld.long 0xC 16. "ERR_FIXED_EDGE,ERR_FIXED_EDGE: edge detection of err_fixed" "0,1" newline bitfld.long 0xC 8. "ERR_EOT_WITH_ERR_EN,ERR_EOT_WITH_ERR_EN: enables err_eot_with_err" "0,1" newline bitfld.long 0xC 7. "ERR_MISSING_EOT_EN,ERR_MISSING_EOT_EN: enables err_missing_eot" "0,1" newline bitfld.long 0xC 6. "ERR_WRONG_LENGTH_EN,ERR_WRONG_LENGTH_EN: enables err_wrong_length" "0,1" newline bitfld.long 0xC 5. "ERR_OVERSIZE_EN,ERR_OVERSIZE_EN: enables err_oversize" "0,1" newline bitfld.long 0xC 4. "ERR_RECEIVE_EN,ERR_RECEIVE_EN: enables err_receive" "0,1" newline bitfld.long 0xC 3. "ERR_UNDECODABLE_EN,ERR_UNDECODABLE_EN: enables err_undecodable" "0,1" newline bitfld.long 0xC 2. "ERR_CHECKSUM_EN,ERR_CHECKSUM_EN: enables err_checksum" "0,1" newline bitfld.long 0xC 1. "ERR_UNCORRECTABLE_EN,ERR_UNCORRECTABLE_EN: enables err_uncorrectable" "0,1" newline bitfld.long 0xC 0. "ERR_FIXED_EN,ERR_FIXED_EN: enables err_fixed" "0,1" line.long 0x10 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_mode_sts_ctl,Control the enabling and edge detection of VSG status bits" bitfld.long 0x10 26. "VSG_RECOVERY_EDGE,VSG_RECOVERY_EDGE: edge detection of vsg_recovery" "0,1" newline bitfld.long 0x10 25. "ERR_VRS_WRONG_LENGTH_EDGE,ERR_VRS_WRONG_LENGTH_EDGE: edge detection of err_vrs_wrong_length" "0,1" newline bitfld.long 0x10 24. "ERR_LONGREAD_EDGE,ERR_LONGREAD_EDGE: edge detection of err_longread" "0,1" newline bitfld.long 0x10 23. "ERR_LINEWRITE_EDGE,ERR_LINEWRITE_EDGE: edge detection of err_line_write" "0,1" newline bitfld.long 0x10 22. "ERR_BURSTWRITE_EDGE,ERR_BURSTWRITE_EDGE: edge detection of err_burst_write" "0,1" newline bitfld.long 0x10 21. "ERR_SMALL_HEIGHT_EDGE,ERR_SMALL_HEIGHT_EDGE: edge detection of unaligned line number" "0,1" newline bitfld.long 0x10 20. "ERR_SMALL_LENGTH_EDGE,ERR_SMALL_LENGTH_EDGE: edge detection of unaligned size" "0,1" newline bitfld.long 0x10 19. "ERR_MISSING_VSYNC_EDGE,ERR_MISSING_VSYNC_EDGE: edge detection of detection of missing VSYNC" "0,1" newline bitfld.long 0x10 18. "ERR_MISSING_HSYNC_EDGE,ERR_MISSING_HSYNC_EDGE: edge detection of detection of missing HSYNC" "0,1" newline bitfld.long 0x10 17. "ERR_MISSING_DATA_EDGE,ERR_MISSING_DATA_EDGE: edge detection of data miss detection" "0,1" newline bitfld.long 0x10 16. "VSG_RUNNING_EDGE,VSG_RUNNING_EDGE: edge detection of VSG status observation" "0,1" newline bitfld.long 0x10 10. "VSG_RECOVERY_EN,VSG_RECOVERY_EN: enables vsg_recovery" "0,1" newline bitfld.long 0x10 9. "ERR_VRS_WRONG_LENGTH_EN,ERR_VRS_WRONG_LENGTH_EN: enables err_vrs_wrong_length" "0,1" newline bitfld.long 0x10 8. "ERR_LONGREAD_EN,ERR_LONGREAD_EN: enables err_longread" "0,1" newline bitfld.long 0x10 7. "ERR_LINEWRITE_EN,ERR_LINEWRITE_EN: enables err_line_write" "0,1" newline bitfld.long 0x10 6. "ERR_BURSTWRITE_EN,ERR_BURSTWRITE_EN: enables err_burst_write" "0,1" newline bitfld.long 0x10 5. "ERR_SMALL_HEIGHT_EN,ERR_SMALL_HEIGHT_EN: enables detection of unaligned line number" "0,1" newline bitfld.long 0x10 4. "ERR_SMALL_LENGTH_EN,ERR_SMALL_LENGTH_EN: enables detection of unaligned size" "0,1" newline bitfld.long 0x10 3. "ERR_MISSING_VSYNC_EN,ERR_MISSING_VSYNC_EN: enables detection of missing VSYNC" "0,1" newline bitfld.long 0x10 2. "ERR_MISSING_HSYNC_EN,ERR_MISSING_HSYNC_EN: enables detection of missing HSYNC" "0,1" newline bitfld.long 0x10 1. "ERR_MISSING_DATA_EN,ERR_MISSING_DATA_EN: enables data miss detection" "0,1" newline bitfld.long 0x10 0. "VSG_RUNNING_EN,VSG_RUNNING_EN: enables VSG status observation" "0,1" line.long 0x14 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_tvg_sts_ctl,Control the enabling and edge detection of TVG status bits" bitfld.long 0x14 16. "TVG_STS_EDGE,TVG_STS_EDGE: edge detection of TVG status observation" "0,1" newline bitfld.long 0x14 0. "TVG_STS_EN,TVG_STS_EN: enables TVG status observation" "0,1" line.long 0x18 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_dphy_err_ctl1,Controls the enabling and edge detection of the DPHY errors" bitfld.long 0x18 25. "ERR_CONT_LP1_4_EN,ERR_CONT_LP1_4_EN" "0,1" newline bitfld.long 0x18 24. "ERR_CONT_LP1_3_EN,ERR_CONT_LP1_3_EN" "0,1" newline bitfld.long 0x18 23. "ERR_CONT_LP1_2_EN,ERR_CONT_LP1_2_EN" "0,1" newline bitfld.long 0x18 22. "ERR_CONT_LP1_1_EN,ERR_CONT_LP1_1_EN" "0,1" newline bitfld.long 0x18 21. "ERR_CONT_LP0_4_EN,ERR_CONT_LP0_4_EN" "0,1" newline bitfld.long 0x18 20. "ERR_CONT_LP0_3_EN,ERR_CONT_LP0_3_EN" "0,1" newline bitfld.long 0x18 19. "ERR_CONT_LP0_2_EN,ERR_CONT_LP0_2_EN" "0,1" newline bitfld.long 0x18 18. "ERR_CONT_LP0_1_EN,ERR_CONT_LP0_1_EN" "0,1" newline bitfld.long 0x18 17. "ERR_CONTROL_4_EN,ERR_CONTROL_4_EN" "0,1" newline bitfld.long 0x18 16. "ERR_CONTROL_3_EN,ERR_CONTROL_3_EN" "0,1" newline bitfld.long 0x18 15. "ERR_CONTROL_2_EN,ERR_CONTROL_2_EN" "0,1" newline bitfld.long 0x18 14. "ERR_CONTROL_1_EN,ERR_CONTROL_1_EN" "0,1" newline bitfld.long 0x18 13. "ERR_SYNCESC_4_EN,ERR_SYNCESC_4_EN" "0,1" newline bitfld.long 0x18 12. "ERR_SYNCESC_3_EN,ERR_SYNCESC_3_EN" "0,1" newline bitfld.long 0x18 11. "ERR_SYNCESC_2_EN,ERR_SYNCESC_2_EN" "0,1" newline bitfld.long 0x18 10. "ERR_SYNCESC_1_EN,ERR_SYNCESC_1_EN" "0,1" newline bitfld.long 0x18 9. "ERR_ESC_4_EN,ERR_ESC_4_EN" "0,1" newline bitfld.long 0x18 8. "ERR_ESC_3_EN,ERR_ESC_3_EN" "0,1" newline bitfld.long 0x18 7. "ERR_ESC_2_EN,ERR_ESC_2_EN" "0,1" newline bitfld.long 0x18 6. "ERR_ESC_1_EN,ERR_ESC_1_EN" "0,1" line.long 0x1C "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_dphy_err_ctl2,Controls he enabling and edge detection of the DPHY errors" bitfld.long 0x1C 19. "ERR_CONT_LP1_4_EDGE,ERR_CONT_LP1_4_EDGE" "0,1" newline bitfld.long 0x1C 18. "ERR_CONT_LP1_3_EDGE,ERR_CONT_LP1_3_EDGE" "0,1" newline bitfld.long 0x1C 17. "ERR_CONT_LP1_2_EDGE,ERR_CONT_LP1_2_EDGE" "0,1" newline bitfld.long 0x1C 16. "ERR_CONT_LP1_1_EDGE,ERR_CONT_LP1_1_EDGE" "0,1" newline bitfld.long 0x1C 15. "ERR_CONT_LP0_4_EDGE,ERR_CONT_LP0_4_EDGE" "0,1" newline bitfld.long 0x1C 14. "ERR_CONT_LP0_3_EDGE,ERR_CONT_LP0_3_EDGE" "0,1" newline bitfld.long 0x1C 13. "ERR_CONT_LP0_2_EDGE,ERR_CONT_LP0_2_EDGE" "0,1" newline bitfld.long 0x1C 12. "ERR_CONT_LP0_1_EDGE,ERR_CONT_LP0_1_EDGE" "0,1" newline bitfld.long 0x1C 11. "ERR_CONTROL_4_EDGE,ERR_CONTROL_4_EDGE" "0,1" newline bitfld.long 0x1C 10. "ERR_CONTROL_3_EDGE,ERR_CONTROL_3_EDGE" "0,1" newline bitfld.long 0x1C 9. "ERR_CONTROL_2_EDGE,ERR_CONTROL_2_EDGE" "0,1" newline bitfld.long 0x1C 8. "ERR_CONTROL_1_EDGE,ERR_CONTROL_1_EDGE" "0,1" newline bitfld.long 0x1C 7. "ERR_SYNCESC_4_EDGE,ERR_SYNCESC_4_EDGE" "0,1" newline bitfld.long 0x1C 6. "ERR_SYNCESC_3_EDGE,ERR_SYNCESC_3_EDGE" "0,1" newline bitfld.long 0x1C 5. "ERR_SYNCESC_2_EDGE,ERR_SYNCESC_2_EDGE" "0,1" newline bitfld.long 0x1C 4. "ERR_SYNCESC_1_EDGE,ERR_SYNCESC_1_EDGE" "0,1" newline bitfld.long 0x1C 3. "ERR_ESC_4_EDGE,ERR_ESC_4_EDGE" "0,1" newline bitfld.long 0x1C 2. "ERR_ESC_3_EDGE,ERR_ESC_3_EDGE" "0,1" newline bitfld.long 0x1C 1. "ERR_ESC_2_EDGE,ERR_ESC_2_EDGE" "0,1" newline bitfld.long 0x1C 0. "ERR_ESC_1_EDGE,ERR_ESC_1_EDGE" "0,1" rgroup.long 0x150++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_main_sts_clr,Main control status register clear function. These bits are spread across different register banks." bitfld.long 0x0 9. "IF3_UNTERM_PCK_ERR_CLR,IF3_UNTERM_PCK_ERR_CLR: clears if3_unterm_pck_err" "0,1" newline bitfld.long 0x0 8. "IF1_UNTERM_PCK_ERR_CLR,IF1_UNTERM_PCK_ERR_CLR: clears if1_unterm_pck_err" "0,1" newline bitfld.long 0x0 7. "LPRX_TO_ERR_CLR,LPRX_TO_ERR_CLR: clears lprx_to_err" "0,1" newline bitfld.long 0x0 6. "HSTX_TO_ERR_CLR,HSTX_TO_ERR_CLR: clears hstx_to_err" "0,1" newline bitfld.long 0x0 5. "DAT4_READY_CLR,DAT4_READY_CLR: clears dat4_ready" "0,1" newline bitfld.long 0x0 4. "DAT3_READY_CLR,DAT3_READY_CLR: clears dat3_ready" "0,1" newline bitfld.long 0x0 3. "DAT2_READY_CLR,DAT2_READY_CLR: clears dat2_ready" "0,1" newline bitfld.long 0x0 2. "DAT1_READY_CLR,DAT1_READY_CLR: clears dat1_ready" "0,1" newline bitfld.long 0x0 1. "CLKLANE_READY_CLR,CLKLANE_READY_CLR: clears clklane_ready" "0,1" newline bitfld.long 0x0 0. "PLL_LOCK_CLR,PLL_LOCK_CLR: clears PLL lock" "0,1" rgroup.long 0x154++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_cmd_mode_sts_clr,Command status register clear function. Write '1' to clear" rbitfld.long 0x0 5. "ERR_IF3_UNDERRUN_CLR,ERR_IF3_UNDERRUN_CLR: clears err_IF3_underrun" "0,1" newline bitfld.long 0x0 4. "ERR_IF1_UNDERRUN_CLR,ERR_IF1_UNDERRUN_CLR: clears err_IF1_underrun" "0,1" newline bitfld.long 0x0 3. "ERR_UNWANTED_RD_CLR,ERR_UNWANTED_RD_CLR: clears err_unwanted_rd" "0,1" newline bitfld.long 0x0 2. "ERR_TE_MISS_CLR,ERR_TE_MISS_CLR: clears err_te_miss" "0,1" newline bitfld.long 0x0 1. "ERR_NO_TE_CLR,ERR_NO_TE_CLR: clears err_no_te" "0,1" newline bitfld.long 0x0 0. "CSM_RUNNING_CLR,CSM_RUNNING_CLR: clears CSM running bit" "0,1" rgroup.long 0x158++0x13 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_sts_clr,Direct command status register clear function. Write '1' to clear" bitfld.long 0x0 10. "READ_COMPLETED_WITH_ERR_CLR,READ_COMPLETED_WITH_ERR_CLR: clears detection of read completed with errors" "0,1" newline bitfld.long 0x0 9. "BTA_FINISHED_CLR,BTA_FINISHED_CLR: clears BTA completion detection" "0,1" newline bitfld.long 0x0 8. "BTA_COMPLETED_CLR,BTA_COMPLETED_CLR: clears BTA request completed" "0,1" newline bitfld.long 0x0 7. "TE_RECEIVED_CLR,TE_RECEIVED_CLR: clears TE received" "0,1" newline bitfld.long 0x0 6. "TRIGGER_RECEIVED_CLR,TRIGGER_RECEIVED_CLR: clears trigger" "0,1" newline bitfld.long 0x0 5. "ACK_WITH_ERR_CLR,ACKNOWLEDGE_WITH_ERR_CLR: clears acknowledge with errors" "0,1" newline bitfld.long 0x0 4. "ACK_RECEIVED_CLR,ACKNOWLEDGE_RECEIVED_CLR: clears acknowledge" "0,1" newline bitfld.long 0x0 3. "READ_COMPLETED_CLR,READ_COMPLETED_CLR: clears read request completed" "0,1" newline bitfld.long 0x0 2. "TRIGGER_COMPLETED_CLR,TRIGGER_COMPLETED_CLR: clears trigger request completed" "0,1" newline bitfld.long 0x0 1. "WRITE_COMPLETED_CLR,WRITE_COMPLETED_CLR: clears detection of write request completed" "0,1" newline bitfld.long 0x0 0. "CMD_TRANSMISSION_CLR,CMD_TRANSMISSION_CLR: clears cmd_transmission" "0,1" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_rd_sts_clr,Direct command read status register clear function. Write '1' to clear" bitfld.long 0x4 8. "ERR_EOT_WITH_ERR_CLR,ERR_EOT_WITH_ERR_CLR: clears err_eot_with_err" "0,1" newline bitfld.long 0x4 7. "ERR_MISSING_EOT_CLR,ERR_MISSING_EOT_CLR: clears err_missing_eot" "0,1" newline bitfld.long 0x4 6. "ERR_WRONG_LENGTH_CLR,ERR_WRONG_LENGTH_CLR: clears err_wrong_length" "0,1" newline bitfld.long 0x4 5. "ERR_OVERSIZE_CLR,ERR_OVERSIZE_CLR: clears err_oversize" "0,1" newline bitfld.long 0x4 4. "ERR_RECEIVE_CLR,ERR_RECEIVE_CLR: clears err_receive" "0,1" newline bitfld.long 0x4 3. "ERR_UNDECODABLE_CLR,ERR_UNDECODABLE_CLR: clears err_undecodable" "0,1" newline bitfld.long 0x4 2. "ERR_CHECKSUM_CLR,ERR_CHECKSUM_CLR: clears err_checksum" "0,1" newline bitfld.long 0x4 1. "ERR_UNCORRECTABLE_CLR,ERR_UNCORRECTABLE_CLR: clears err_uncorrectable" "0,1" newline bitfld.long 0x4 0. "ERR_FIXED_CLR,ERR_FIXED_CLR: clears err_fixed" "0,1" line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_mode_sts_clr,VSG status register clear function" bitfld.long 0x8 10. "VSG_RECOVERY_CLR,VSG_RECOVERY_CLR: clears the bit vsg_recovery" "0,1" newline bitfld.long 0x8 9. "ERR_VRS_WRONG_LENGTH_CLR,ERR_VRS_WRONG_LENGTH_CLR: clears the bit err_vid_wrong_length" "0,1" newline bitfld.long 0x8 8. "ERR_LONGREAD_CLR,ERR_LONGREAD_CLR: clears err_longread" "0,1" newline bitfld.long 0x8 7. "ERR_LINEWRITE_CLR,ERR_LINEWRITE_CLR: clears err_linewrite" "0,1" newline bitfld.long 0x8 6. "ERR_BURSTWRITE_CLR,ERR_BURSTWRITE_CLR: clears err_burstwrite" "0,1" newline bitfld.long 0x8 5. "ERR_SMALL_HEIGHT_CLR,ERR_SMALL_HEIGHT_CLR: clears unaligned line number" "0,1" newline bitfld.long 0x8 4. "ERR_SMALL_LENGTH_CLR,ERR_SMALL_LENGTH_CLR: clears analigned size" "0,1" newline bitfld.long 0x8 3. "ERR_MISSING_VSYNC_CLR,ERR_MISSING_VSYNC_CLR: clears missing VSYNC" "0,1" newline bitfld.long 0x8 2. "ERR_MISSING_HSYNC_CLR,ERR_MISSING_HSYNC_CLR: clears missing HSYNC" "0,1" newline bitfld.long 0x8 1. "ERR_MISSING_DATA_CLR,ERR_MISSING_DATA_CLR: clears data miss" "0,1" newline bitfld.long 0x8 0. "VSG_STS_CLR,VSG_STS_CLR: clears VSG status" "0,1" line.long 0xC "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_tg_sts_clr,TVG status register clear function. Write '1' to clear" bitfld.long 0xC 0. "TVG_STS_CLR,TVG_STS_CLR: clears TVG status observation" "0,1" line.long 0x10 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_dphy_err_clr,D_PHY lanes output register clear function. Write '1' to clear" bitfld.long 0x10 25. "ERR_CONT_LP1_4_CLR,ERR_CONT_LP1_4_CLR" "0,1" newline bitfld.long 0x10 24. "ERR_CONT_LP1_3_CLR,ERR_CONT_LP1_3_CLR" "0,1" newline bitfld.long 0x10 23. "ERR_CONT_LP1_2_CLR,ERR_CONT_LP1_2_CLR" "0,1" newline bitfld.long 0x10 22. "ERR_CONT_LP1_1_CLR,ERR_CONT_LP1_1_CLR" "0,1" newline bitfld.long 0x10 21. "ERR_CONT_LP0_4_CLR,ERR_CONT_LP0_4_CLR" "0,1" newline bitfld.long 0x10 20. "ERR_CONT_LP0_3_CLR,ERR_CONT_LP0_3_CLR" "0,1" newline bitfld.long 0x10 19. "ERR_CONT_LP0_2_CLR,ERR_CONT_LP0_2_CLR" "0,1" newline bitfld.long 0x10 18. "ERR_CONT_LP0_1_CLR,ERR_CONT_LP0_1_CLR" "0,1" newline bitfld.long 0x10 17. "ERR_CONTROL_4_CLR,ERR_CONTROL_4_CLR" "0,1" newline bitfld.long 0x10 16. "ERR_CONTROL_3_CLR,ERR_CONTROL_3_CLR" "0,1" newline bitfld.long 0x10 15. "ERR_CONTROL_2_CLR,ERR_CONTROL_2_CLR" "0,1" newline bitfld.long 0x10 14. "ERR_CONTROL_1_CLR,ERR_CONTROL_1_CLR" "0,1" newline bitfld.long 0x10 13. "ERR_SYNCESC_4_CLR,ERR_SYNCESC_4_CLR" "0,1" newline bitfld.long 0x10 12. "ERR_SYNCESC_3_CLR,ERR_SYNCESC_3_CLR" "0,1" newline bitfld.long 0x10 11. "ERR_SYNCESC_2_CLR,ERR_SYNCESC_2_CLR" "0,1" newline bitfld.long 0x10 10. "ERR_SYNCESC_1_CLR,ERR_SYNCESC_1_CLR" "0,1" newline bitfld.long 0x10 9. "ERR_ESC_4_CLR,ERR_ESC_4_CLR" "0,1" newline bitfld.long 0x10 8. "ERR_ESC_3_CLR,ERR_ESC_3_CLR" "0,1" newline bitfld.long 0x10 7. "ERR_ESC_2_CLR,ERR_ESC_2_CLR" "0,1" newline bitfld.long 0x10 6. "ERR_ESC_1_CLR,ERR_ESC_1_CLR" "0,1" rgroup.long 0x170++0x1B line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_main_sts_flag,Main control status Flag registers. The use of these registers is related to status and error bits management (and interrupt too)." bitfld.long 0x0 9. "IF3_UNTERM_PCK_ERR_FLAG,IF3_UNTERM_PCK_ERR_FLAG: flags if3_unterm_pck_err" "0,1" newline bitfld.long 0x0 8. "IF1_UNTERM_PCK_ERR_FLAG,IF1_UNTERM_PCK_ERR_FLAG: flags if1_unterm_pck_err" "0,1" newline bitfld.long 0x0 7. "LPRX_TO_ERR_FLAG,LPRX_TO_ERR_FLAG: flags lprx_to_err" "0,1" newline bitfld.long 0x0 6. "HSTX_TO_ERR_FLAG,HSTX_TO_ERR_FLAG: flags hstx_to_err" "0,1" newline bitfld.long 0x0 5. "DAT4_READY_FLAG,DAT4_READY_FLAG: flags dat4_ready" "0,1" newline bitfld.long 0x0 4. "DAT3_READY_FLAG,DAT3_READY_FLAG: flags dat3_ready" "0,1" newline bitfld.long 0x0 3. "DAT2_READY_FLAG,DAT2_READY_FLAG: flags dat2_ready" "0,1" newline bitfld.long 0x0 2. "DAT1_READY_FLAG,DAT1_READY_FLAG: flags dat1_ready" "0,1" newline bitfld.long 0x0 1. "CLKLANE_READY_FLAG,CLKLANE_READY_FLAG: flags clklane_ready" "0,1" newline bitfld.long 0x0 0. "PLL_LOCK_FLAG,PLL_LOCK_FLAG: flags PLL lock" "0,1" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_cmd_mode_sts_flag,Command Mode status" bitfld.long 0x4 5. "ERR_IF3_UNDERRUN_FLAG,ERR_IF3_UNDERRUN_FLAG: flags err_IF3_underrun" "0,1" newline bitfld.long 0x4 4. "ERR_IF1_UNDERRUN_FLAG,ERR_IF1_UNDERRUN_FLAG: flags err_IF1_underrun" "0,1" newline bitfld.long 0x4 3. "ERR_UNWANTED_RD_FLAG,ERR_UNWANTED_RD_FLAG: flags fixed_err" "0,1" newline bitfld.long 0x4 2. "ERR_TE_MISS_FLAG,ERR_TE_MISS_FLAG: flags err_te_miss" "0,1" newline bitfld.long 0x4 1. "ERR_NO_TE_FLAG,ERR_NO_TE_FLAG: flags err_no_te" "0,1" newline bitfld.long 0x4 0. "CSM_RUNNING_FLAG,CSM_RUNNING_FLAG: flags remaining_err" "0,1" line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_sts_flag,Direct command mode status" bitfld.long 0x8 10. "READ_COMPLETED_WITH_ERR_FLAG,READ_COMPLETED_WITH_ERR_FLAG: flags detection of read completed with errors" "0,1" newline bitfld.long 0x8 9. "BTA_FINISHED_FLAG,BTA_FINISHED_FLAG: flags BTA completion detection" "0,1" newline bitfld.long 0x8 8. "BTA_COMPLETED_FLAG,BTA_COMPLETED_FLAG: flags BTA request completed" "0,1" newline bitfld.long 0x8 7. "TE_RECEIVED_FLAG,TE_RECEIVED_FLAG: flags TE received" "0,1" newline bitfld.long 0x8 6. "TRIGGER_RECEIVED_FLAG,TRIGGER_RECEIVED_FLAG: flags trigger" "0,1" newline bitfld.long 0x8 5. "ACK_WITH_ERR_RECEIVED_FLAG,ACK_WITH_ERR_RECEIVED_FLAG: flag acknowledge with error detection" "0,1" newline bitfld.long 0x8 4. "ACKNOWLEDGE_RECEIVED_FLAG,ACKNOWLEDGE_RECEIVED_FLAG: flags acknowledge" "0,1" newline bitfld.long 0x8 3. "READ_COMPLETED_FLAG,READ_COMPLETED_FLAG: flags read request completed" "0,1" newline bitfld.long 0x8 2. "TRIGGER_COMPLETED_FLAG,TRIGGER_COMPLETED_FLAG: flags trigger request completed" "0,1" newline bitfld.long 0x8 1. "WRITE_COMPLETED_FLAG,WRITE_COMPLETED_FLAG: flags detection of write request completed" "0,1" newline bitfld.long 0x8 0. "CMD_TRANSMISSION_FLAG,CMD_TRANSMISSION_FLAG: flags cmd_transmission" "0,1" line.long 0xC "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_direct_cmd_rd_sts_flag,Direct command read status bits" bitfld.long 0xC 8. "ERR_EOT_WITH_ERR_FLAG,ERR_EOT_WITH_ERR_FLAG: flags err_eot_with_err" "0,1" newline bitfld.long 0xC 7. "ERR_MISSING_EOT_FLAG,ERR_MISSING_EOT_FLAG: flags err_missing_eot" "0,1" newline bitfld.long 0xC 6. "ERR_WRONG_LENGTH_FLAG,ERR_WRONG_LENGTH_FLAG: flags err_wrong_length" "0,1" newline bitfld.long 0xC 5. "ERR_OVERSIZE_FLAG,ERR_OVERSIZE_FLAG: flags err_oversize" "0,1" newline bitfld.long 0xC 4. "ERR_RECEIVE_FLAG,ERR_RECEIVE_FLAG: flags err_receive" "0,1" newline bitfld.long 0xC 3. "ERR_UNDECODABLE_FLAG,ERR_UNDECODABLE_FLAG: flags err_undecodable" "0,1" newline bitfld.long 0xC 2. "ERR_CHECKSUM_FLAG,ERR_CHECKSUM_FLAG: flags err_checksum" "0,1" newline bitfld.long 0xC 1. "ERR_UNCORRECTABLE_FLAG,ERR_UNCORRECTABLE_FLAG: flags err_uncorrectable" "0,1" newline bitfld.long 0xC 0. "ERR_FIXED_FLAG,ERR_FIXED_FLAG: flags err_fixed" "0,1" line.long 0x10 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_vid_mode_sts_flag,Video Mode status flag" bitfld.long 0x10 10. "FLAG_VSG_RECOVERY,FLAG_VSG_RECOVERY: lags vsg_recovery" "0,1" newline bitfld.long 0x10 9. "ERR_VRS_WRONG_LENGTH_FLAG,ERR_VRS_WRONG_LENGTH_FLAG: flags err_vrs_wrong_length" "0,1" newline bitfld.long 0x10 8. "ERR_LONGREAD_FLAG,ERR_LONGREAD_FLAG: flags err_longread" "0,1" newline bitfld.long 0x10 7. "ERR_LONGWRITE_FLAG,ERR_LONGWRITE_FLAG: flags err_longwrite" "0,1" newline bitfld.long 0x10 6. "ERR_SHORTWRITE_FLAG,ERR_SHORTWRITE_FLAG: flags err_shortwrite" "0,1" newline bitfld.long 0x10 5. "ERR_SMALL_HEIGHT_FLAG,ERR_SMALL_HEIGHT_FLAG: flags the detection of unaligned line number" "0,1" newline bitfld.long 0x10 4. "ERR_SMALL_LENGTH_FLAG,ERR_SMALL_LENGTH_FLAG: flags the detection of unaligned size" "0,1" newline bitfld.long 0x10 3. "ERR_MISS_VSYNC_FLAG,ERR_MISS_VSYNC_FLAG: flags missing VSYNC" "0,1" newline bitfld.long 0x10 2. "ERR_MISSING_HSYNC_FLAG,ERR_MISSING_HSYNC_FLAG: flags missing HSYNC" "0,1" newline bitfld.long 0x10 1. "ERR_MISSING_DATA_FLAG,ERR_MISSING_DATA_FLAG: flags data miss" "0,1" newline bitfld.long 0x10 0. "VSG_STS_FLAG,VSG_STS_FLAG: flags VSG status" "0,1" line.long 0x14 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_tg_sts_flag,TVG status Flags" bitfld.long 0x14 0. "TVG_STS_FLAG,TVG_STS_FLAG: Indicates TVG status observation" "0,1" line.long 0x18 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_mctl_dphy_err_flag,Errors output from D_PHY lanes - flags error bit" bitfld.long 0x18 25. "ERR_CONT_LP1_4_FLAG,ERR_CONT_LP1_4_FLAG" "0,1" newline bitfld.long 0x18 24. "ERR_CONT_LP1_3_FLAG,ERR_CONT_LP1_3_FLAG" "0,1" newline bitfld.long 0x18 23. "ERR_CONT_LP1_2_FLAG,ERR_CONT_LP1_2_FLAG" "0,1" newline bitfld.long 0x18 22. "ERR_CONT_LP1_1_FLAG,ERR_CONT_LP1_1_FLAG" "0,1" newline bitfld.long 0x18 21. "ERR_CONT_LP0_4_FLAG,ERR_CONT_LP0_4_FLAG" "0,1" newline bitfld.long 0x18 20. "ERR_CONT_LP0_3_FLAG,ERR_CONT_LP0_3_FLAG" "0,1" newline bitfld.long 0x18 19. "ERR_CONT_LP0_2_FLAG,ERR_CONT_LP0_2_FLAG" "0,1" newline bitfld.long 0x18 18. "ERR_CONT_LP0_1_FLAG,ERR_CONT_LP0_1_FLAG" "0,1" newline bitfld.long 0x18 17. "ERR_CONTROL_4_FLAG,ERR_CONTROL_4_FLAG" "0,1" newline bitfld.long 0x18 16. "ERR_CONTROL_3_FLAG,ERR_CONTROL_3_FLAG" "0,1" newline bitfld.long 0x18 15. "ERR_CONTROL_2_FLAG,ERR_CONTROL_2_FLAG" "0,1" newline bitfld.long 0x18 14. "ERR_CONTROL_1_FLAG,ERR_CONTROL_1_FLAG" "0,1" newline bitfld.long 0x18 13. "ERR_SYNCESC_4_FLAG,ERR_SYNCESC_4_FLAG" "0,1" newline bitfld.long 0x18 12. "ERR_SYNCESC_3_FLAG,ERR_SYNCESC_3_FLAG" "0,1" newline bitfld.long 0x18 11. "ERR_SYNCESC_2_FLAG,ERR_SYNCESC_2_FLAG" "0,1" newline bitfld.long 0x18 10. "ERR_SYNCESC_1_FLAG,ERR_SYNCESC_1_FLAG" "0,1" newline bitfld.long 0x18 9. "ERR_ESC_4_FLAG,ERR_ESC_4_FLAG" "0,1" newline bitfld.long 0x18 8. "ERR_ESC_3_FLAG,ERR_ESC_3_FLAG" "0,1" newline bitfld.long 0x18 7. "ERR_ESC_2_FLAG,ERR_ESC_2_FLAG" "0,1" newline bitfld.long 0x18 6. "ERR_ESC_1_FLAG,ERR_ESC_1_FLAG" "0,1" rgroup.long 0x1A0++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_dpi_irq_en,DPI interrupt enable" bitfld.long 0x0 0. "PIXEL_BUF_OVERFLOW_IRQ_EN,Enable DPI FIFO Overflow interrupt" "0,1" rgroup.long 0x1A4++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_dpi_irq_clr,DPI interrupt clear register" bitfld.long 0x0 0. "PIXEL_BUF_OVERFLOW_IRQ_CLR,Clear DPI FIFO Overflow interrupt" "0,1" rgroup.long 0x1A8++0x7 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_dpi_irq_sts,DPI interrupt status" bitfld.long 0x0 0. "PIXEL_BUF_OVERFLOW_STS,Status of DPI FIFO Overflow interrupt" "0,1" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_dpi_cfg,DPI interface configuration information" hexmask.long.word 0x4 16.--31. 1. "DPI_CFG_FIFODEPTH,DPI FIFO depth - configuration paramter" newline hexmask.long.word 0x4 0.--15. 1. "DPI_CFG_FIFO_LEVEL,DPI FIFO fill level - can be read mid-line for debug purposes to allow adjustment of settings" rgroup.long 0x1F0++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_test_generic,Generic test control and status register" hexmask.long.word 0x0 16.--31. 1. "STATUS,Test status - Value of test_generic_status input" newline hexmask.long.word 0x0 0.--15. 1. "CTRL,Test control - Drives test_generic_ctrl output" rgroup.long 0x1FC++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_id_reg,ID register for Controller" hexmask.long.word 0x0 20.--31. 1. "REV_VENDOR_ID,VENDOR_ID: IP vendor ID affected to CadenceIP [reset = 0xCAD]." newline hexmask.long.byte 0x0 12.--19. 1. "REV_PRODUCT_ID,PRODUCT_ID: unique IP identifier within IP portfolio [reset = 0xD5]." newline hexmask.long.byte 0x0 8.--11. 1. "REV_HARDWARE,H: Hardware revision number [reset = 0x1]." newline hexmask.long.byte 0x0 4.--7. 1. "REV_X,X: Major revision value [reset = 0x3]." newline hexmask.long.byte 0x0 0.--3. 1. "REV_Y,Y: Minor revision value [reset = 0x1]." rgroup.long 0x200++0x13 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_int_status,ASF Interrupt Status Register. This register indicates the source of ASF interrupts. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register the.." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x0 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1" newline bitfld.long 0x0 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1" newline bitfld.long 0x0 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1" newline bitfld.long 0x0 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x0 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1" newline bitfld.long 0x0 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x0 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_int_raw_status,ASF Interrupt Raw Status Register. A bit set in this raw register indicates a source of ASF fault in the corresponding feature. Writing to either raw or masked status registers. clear both registers." hexmask.long 0x4 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x4 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1" newline bitfld.long 0x4 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1" newline bitfld.long 0x4 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1" newline bitfld.long 0x4 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x4 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1" newline bitfld.long 0x4 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x4 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1" line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_int_mask,The ASF interrupt mask register indicating which interrupt bits in the ASF interrupt status register are masked. All bits are set at reset. Clear the individual bit to enable the corresponding interrupt." hexmask.long 0x8 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x8 6. "ASF_INTEGRITY_ERR_MASK,Mask bit for integrity error interrupt" "0,1" newline bitfld.long 0x8 5. "ASF_PROTOCOL_ERR_MASK,Mask bit for protocol error interrupt." "0,1" newline bitfld.long 0x8 4. "ASF_TRANS_TO_ERR_MASK,Mask bit for transaction timeouts error interrupt." "0,1" newline bitfld.long 0x8 3. "ASF_CSR_ERR_MASK,Mask bit for configuration and status registers error interrupt." "0,1" newline bitfld.long 0x8 2. "ASF_DAP_ERR_MASK,Mask bit for data and address paths parity error interrupt." "0,1" newline bitfld.long 0x8 1. "ASF_SRAM_UNCORR_ERR_MASK,Mask bit for SRAM uncorrectable error interrupt." "0,1" newline bitfld.long 0x8 0. "ASF_SRAM_CORR_ERR_MASK,Mask bit for SRAM correctable error interrupt." "0,1" line.long 0xC "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_int_test,The ASF interrupt test register emulate hardware even. Write one to individual bit to trigger single event in (masked and raw) status registers according to mask and will generate interrupt accordingly." hexmask.long 0xC 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0xC 6. "ASF_INTEGRITY_ERR_TEST,Test bit for integrity error interrupt" "0,1" newline bitfld.long 0xC 5. "ASF_PROTOCOL_ERR_TEST,Test bit for protocol error interrupt." "0,1" newline bitfld.long 0xC 4. "ASF_TRANS_TO_ERR_TEST,Test bit for transaction timeouts error interrupt." "0,1" newline bitfld.long 0xC 3. "ASF_CSR_ERR_TEST,Test bit for configuration and status registers error interrupt." "0,1" newline bitfld.long 0xC 2. "ASF_DAP_ERR_TEST,Test bit for data and address paths parity error interrupt." "0,1" newline bitfld.long 0xC 1. "ASF_SRAM_UNCORR_ERR_TEST,Test bit for SRAM uncorrectable error interrupt." "0,1" newline bitfld.long 0xC 0. "ASF_SRAM_CORR_ERR_TEST,Test bit for SRAM correctable error interrupt." "0,1" line.long 0x10 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_fatal_nonfatal_select,The fatal or non-fatal interrupt register selects whether a fatal (asf_int_fatal) or non-fatal (asf_int_nonfatal) interrupt is triggered. If the bit of the event will be set to one then fatal.." hexmask.long 0x10 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x10 6. "ASF_INTEGRITY_ERR,Enable integrity error interrupt as fatal" "0,1" newline bitfld.long 0x10 5. "ASF_PROTOCOL_ERR,Enable protocol error interrupt as fatal." "0,1" newline bitfld.long 0x10 4. "ASF_TRANS_TO_ERR,Enable transaction timeouts error interrupt as fatal." "0,1" newline bitfld.long 0x10 3. "ASF_CSR_ERR,Enable configuration and status registers error interrupt as fatal." "0,1" newline bitfld.long 0x10 2. "ASF_DAP_ERR,Enable data and address paths parity error interrupt as fatal." "0,1" newline bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR,Enable SRAM uncorrectable error interrupt as fatal." "0,1" newline bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR,Enable SRAM correctable error interrupt as fatal." "0,1" rgroup.long 0x220++0x7 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_sram_corr_fault_status,Status register for SRAM correctable fault. These fields are updated whenever asf_sram_corr_fault input is active." hexmask.long.byte 0x0 24.--31. 1. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault." newline hexmask.long.tbyte 0x0 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault." line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_sram_uncorr_fault_status,Status register for SRAM uncorrectable fault. These fields are updated whenever asf_sram_uncorr_fault input is active." hexmask.long.byte 0x4 24.--31. 1. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault." newline hexmask.long.tbyte 0x4 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault." rgroup.long 0x228++0x3 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_sram_fault_stats,Statistics register for SRAM faults. Note that this register clears when software writes to any field." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline hexmask.long.word 0x0 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS,Count of number of correctable errors if implemented. Count value will saturate at 0xffff." rgroup.long 0x230++0xB line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_trans_to_ctrl,Control register to configure the ASF transaction timeout monitors." bitfld.long 0x0 31. "ASF_TRANS_TO_EN,Enable transaction timeout monitoring." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "ASF_TRANS_TO_CTRL,Timer value to use for transaction timeout monitor." line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_trans_to_fault_mask,Control register to mask out ASF transaction timeout faults from triggering interrupts. On reset. all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt.." bitfld.long 0x4 3. "ASF_TRANS_TO_FAULT_3_MASK,Mask register for each ASF transaction timeout fault source." "0,1" newline bitfld.long 0x4 2. "ASF_TRANS_TO_FAULT_2_MASK,Mask register for each ASF transaction timeout fault source." "0,1" newline bitfld.long 0x4 1. "ASF_TRANS_TO_FAULT_1_MASK,Mask register for each ASF transaction timeout fault source." "0,1" newline bitfld.long 0x4 0. "ASF_TRANS_TO_FAULT_0_MASK,Mask register for each ASF transaction timeout fault source." "0,1" line.long 0x8 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_trans_to_fault_status,Status register for transaction timeouts fault. If a fault occurs the revelant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit." bitfld.long 0x8 3. "ASF_TRANS_TO_FAULT_3_STATUS,Status bits for transaction timeouts faults." "0,1" newline bitfld.long 0x8 2. "ASF_TRANS_TO_FAULT_2_STATUS,Status bits for transaction timeouts faults." "0,1" newline bitfld.long 0x8 1. "ASF_TRANS_TO_FAULT_1_STATUS,Status bits for transaction timeouts faults." "0,1" newline bitfld.long 0x8 0. "ASF_TRANS_TO_FAULT_0_STATUS,Status bits for transaction timeouts faults." "0,1" rgroup.long 0x240++0x7 line.long 0x0 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_protocol_fault_mask,Control register to mask out ASF Protocol faults from triggering interrupts. On reset. all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt source. The.." bitfld.long 0x0 3. "ASF_PROTOCOL_FAULT_3_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 2. "ASF_PROTOCOL_FAULT_2_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 1. "ASF_PROTOCOL_FAULT_1_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 0. "ASF_PROTOCOL_FAULT_0_MASK,Mask register for each ASF protocol fault source." "0,1" line.long 0x4 "DSI_TOP__VBUSP_CFG_DSI_0__DSI_REGS_asf_protocol_fault_status,Status register for protocol faults. If a fault occurs the revelant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit" bitfld.long 0x4 3. "ASF_PROTOCOL_FAULT_3_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 2. "ASF_PROTOCOL_FAULT_2_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 1. "ASF_PROTOCOL_FAULT_1_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 0. "ASF_PROTOCOL_FAULT_0_STATUS,Status bits for protocol faults." "0,1" tree.end tree.end tree "DSS_DSI1_DSI_WRAP_MMR_VBUSP_CFG_DSI_WRAP (DSS_DSI1_DSI_WRAP_MMR_VBUSP_CFG_DSI_WRAP)" base ad:0x4720000 rgroup.long 0x0++0x3 line.long 0x0 "DSI_WRAP_MMR__VBUSP_CFG__DSI_WRAP_revision,The REVISION register contains the DSI revision number and PID" hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID Field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Revision" bitfld.long 0x0 8.--10. "REVMAJOR,Major Revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Revision" rgroup.long 0x4++0xB line.long 0x0 "DSI_WRAP_MMR__VBUSP_CFG__DSI_WRAP_DPI_CONTROL,Controls the DPI Video Input ports of the DSI Wrapper" bitfld.long 0x0 4. "DSI2_MUX_SEL,Select between DPI-1 and DPI-2 to drive the DPI input of DSITX2" "0,1" bitfld.long 0x0 0. "DPI_0_EN,Enable for DPI-0 input" "0,1" line.long 0x4 "DSI_WRAP_MMR__VBUSP_CFG__DSI_WRAP_DSC_CONTROL,Controls the DSC Encoder for DSI" line.long 0x8 "DSI_WRAP_MMR__VBUSP_CFG__DSI_WRAP_DPI_SECURE,Controls the DPI Video Input ports SECURE settings" bitfld.long 0x8 1. "DPI_0_SECURE_VIOLATION,SECURE VIOLATION status for DPI-0 input. Write-1 to clear the status" "0,1" bitfld.long 0x8 0. "DPI_0_SECURE,SECURE bit for DPI-0 input" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "DSI_WRAP_MMR__VBUSP_CFG__DSI_WRAP_DSI_0_ASF_STATUS,ASF Status" bitfld.long 0x0 6. "INTEGRITY_ERR,INTEGRITY_ERR" "0,1" bitfld.long 0x0 5. "PROTOCOL_ERR,PROTOCOL_ERR" "0,1" bitfld.long 0x0 4. "TRANS_TO_ERR,TRANS_TO_ERR" "0,1" newline bitfld.long 0x0 3. "CSR_ERR,CSR_ERR" "0,1" bitfld.long 0x0 2. "DAP_ERR,DAP_ERR" "0,1" bitfld.long 0x0 1. "SRAM_UNCORR_ERR,SRAM_UNCORR_ERR" "0,1" newline bitfld.long 0x0 0. "SRAM_CORR_ERR,SRAM_CORR_ERR" "0,1" tree.end tree.end tree "DSS_EDP0" tree "DSS_EDP0_INTG_CFG_VP (DSS_EDP0_INTG_CFG_VP)" base ad:0x4F40000 rgroup.long 0x0++0x3 line.long 0x0 "INTG_CFG__VP__REGS_revision,The REVISION Register contains the major and minor revisions for the VPAC dptx HWA module." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and new scheme. Spare bit to encode future schemes" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU indicator DSPS ==> 0x0 WTBU ==> 0x1 Processors ==> 0x2" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family. If there is no level of software compatibility a new FUNC number and hence PID should be assigned." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version. R as described in PDR with additional clarifications and definitions below. Must be easily ECO-able or controlled during fabrication. Ideally through a top level metal mask or e-fuse. This number is maintained/owned by IP design.." newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision. X as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. X is part of IP numbering X.Y.R.Z. X changes ONLY when: (1) There is a major feature addition." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library (CSL) / Drivers. 0 if non-c ustom." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision. Y as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owne r. Y changes ONLY when: (1) Features are scaled (up or down). Flexibility exists in that this.." rgroup.long 0x4++0x13 line.long 0x0 "INTG_CFG__VP__REGS_dptx_ipcfg,The DPTX_IPCFG Register - Configures DPTX Core security mode and fw memory clock enable." bitfld.long 0x0 1. "FW_MEM_CLK_EN,DPTX firmware memory (I/Dram) clock enable (set to 1 by default after a reset) 0: Disable Clock (can be set to 0 when not in use for power saving) 1: Enable Clock (must for normal operation)" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x0 0. "APB_SECURE_REG_BLOCK_EN,DPTX - APB secure region access block enable mode 0: Not Enabled (full access to DPTX memory space including uCPU FW memory regions are permitted) 1: Enabled (only Mailbox and non-secure APB region accesses are permitted via.." "0: Not Enabled,1: Enabled" line.long 0x4 "INTG_CFG__VP__REGS_ecc_mem_cfg,The ECC_MEM_CFG Register - Enables clocks to the ECC-aggregator/memories for ECC logic access. The setting of 1 forces the functional clock gating to be bypassed during memory ECC CTRL/Aggregator accesses during ECC.." bitfld.long 0x4 0. "CLK_EN,Clk Force Enable for ECC access 0: Disable 1: Enable (all clock gatings for the ECC memories/aggregator are bypassed) PHY/IO clocks may not be running during the ECC access. These clocks will still be off even when this parameter is set to 1" "0: Disable,1: Enable" line.long 0x8 "INTG_CFG__VP__REGS_dptx_dsc_cfg,The DPTX_DSC_CFG Register - Configures DSC usaged of the DPTX Core. The settings are used by the wrapper to control the source clock gating for DSC sub-module and also to force enable vif memory clocks as necessary." bitfld.long 0x8 5. "DSC_1_10BPC,DPTX - DSC encoder 1 - 10-bit input enable 0: 8-bit (default) 1: 10-bit This setting must match the DSC_ENC1 input_bpc[0] configuration" "0,1" newline bitfld.long 0x8 4. "DSC_0_10BPC,DPTX - DSC encoder 0 - 10-bit input enable 0: 8-bit (default) 1: 10-bit This setting must match the DSC_ENC0 input_bpc[0] configuration" "0,1" newline bitfld.long 0x8 3. "BOTH_CLK_EN,DPTX - DSC force both clock on whenever DSC is active 0: Disabled (Normal setting - DSC clock enable is controlled based on mode_sel) 1: Enabled (Reserved)" "0: Disabled,1: Enabled" newline bitfld.long 0x8 2. "SPLIT_PANEL_EN,DPTX - DSC encoder mode select 0: Dual Panel (two independent streams) 1: Split Panel (L/R channels of a single source In Split Panel mode the selected vif_0 and vif_1 stream must be video timing synchronized. Both split/dual.." "0: Dual Panel,1: Split Panel" newline bitfld.long 0x8 0.--1. "MODE_SEL,DPTX - DSC encoder mode select 2'b00: Both encoders Disabled (not used) 2'b01: Single Encoder (only enc0 is used) 2'b11: Both Encoders Enabled When both Encoders are enabled it can either be in split panel or dual panel mode" "0: Both encoders Disabled,1: Single Encoder,?,3: Both Encoders Enabled When both Encoders are.." line.long 0xC "INTG_CFG__VP__REGS_dptx_src_cfg,The DPTX_SRC_CFG Register - Configures VIF and AIF port channel enables (for memory clock gating) and VIF source mux selection (for mapping DPI to VIF ports)." hexmask.long.byte 0xC 28.--31. 1. "VIF_FMT_SEL,Reserved - must be set to 0" newline bitfld.long 0xC 16. "AIF_EN,DPTX Audio I2S channel memory clk enable 0 : Disable 1: Enable" "0: Disable,1: Enable" newline bitfld.long 0xC 11. "VIF_3_IN30B,DPTX vif_3 source data width is 30 bits 0: 36 bits (default) 1: 30 bits" "0,1" newline bitfld.long 0xC 10. "VIF_2_IN30B,DPTX vif_2 source data width is 30 bits 0: 36 bits (default) 1: 30 bits" "0,1" newline bitfld.long 0xC 9. "VIF_1_IN30B,DPTX vif_1 source data width is 30 bits 0: 36 bits (default) 1: 30 bits" "0,1" newline bitfld.long 0xC 8. "VIF_0_IN30B,DPTX vif_0 source data width is 30 bits 0: 36 bits (default) 1: 30 bits" "0,1" newline bitfld.long 0xC 7. "VIF_3_SEL,DPTX vif_3 source select - between dpi_3 or dpi_5 0: dpi_3 1: dpi_5" "0: dpi_3,1: dpi_5" newline bitfld.long 0xC 6. "VIF_2_SEL,DPTX vif_2 source select - between dpi_2 or dpi_4 0: dpi_2 1: dpi_4" "0: dpi_2,1: dpi_4" newline bitfld.long 0xC 5. "VIF_1_SEL,DPTX vif_1 source select - between dpi_1 or dpi_3 0: dpi_1 1: dpi_3" "0: dpi_1,1: dpi_3" newline bitfld.long 0xC 4. "VIF_0_SEL,DPTX vif_0 source select - between dpi_0 or dpi_2 0: dpi_0 1: dpi_2" "0: dpi_0,1: dpi_2" newline bitfld.long 0xC 3. "VIF_3_EN,DPTX vif_3 channel memory clk enable 0: Disable 1: Enable" "0: Disable,1: Enable" newline bitfld.long 0xC 2. "VIF_2_EN,DPTX vif_2 channel memory clk enable 0: Disable 1: Enable" "0: Disable,1: Enable" newline bitfld.long 0xC 1. "VIF_1_EN,DPTX vif_1 channel memory clk enable 0: Disable 1: Enable" "0: Disable,1: Enable" newline bitfld.long 0xC 0. "VIF_0_EN,DPTX vif_0 channel memory clk enable 0: Disable 1: Enable" "0: Disable,1: Enable" line.long 0x10 "INTG_CFG__VP__REGS_dptx_vif_secure_mode_cfg,The DPTX_VIF_SECURE_MODE_CFG Register - Configures the security level of the VIF channel (for protecting secure content from going to a non-protected display interface)." bitfld.long 0x10 3. "VIF_3,vif_3 channel secure mode: 0: Non-Secure 1: Secure" "0: Non-Secure,1: Secure" newline bitfld.long 0x10 2. "VIF_2,vif_2 channel secure mode: 0: Non-Secure 1: Secure" "0: Non-Secure,1: Secure" newline bitfld.long 0x10 1. "VIF_1,vif_1 channel secure mode: 0: Non-Secure 1: Secure" "0: Non-Secure,1: Secure" newline bitfld.long 0x10 0. "VIF_0,vif_0 channel secure mode: 0: Non-Secure 1: Secure" "0: Non-Secure,1: Secure" rgroup.long 0x18++0x7 line.long 0x0 "INTG_CFG__VP__REGS_dptx_vif_conn_status,The DPTX_VIF_CONN_STATUS Register - Returns the status of DPI-VIF connection based on the security mode check." bitfld.long 0x0 3. "VIF_3,vif_0 security check status: 0: Conn Allowed - no security issue 1: Connection Not Allowed due to security mismatch" "0: Conn Allowed,1: Connection Not Allowed due to security mismatch" newline bitfld.long 0x0 2. "VIF_2,vif_0 security check status: 0: Conn Allowed - no security issue 1: Connection Not Allowed due to security mismatch" "0: Conn Allowed,1: Connection Not Allowed due to security mismatch" newline bitfld.long 0x0 1. "VIF_1,vif_0 security check status: 0: Conn Allowed - no security issue 1: Connection Not Allowed due to security mismatch" "0: Conn Allowed,1: Connection Not Allowed due to security mismatch" newline bitfld.long 0x0 0. "VIF_0,vif_0 security check status: 0: Conn Allowed - no security issue 1: Connection Not Allowed due to security mismatch" "0: Conn Allowed,1: Connection Not Allowed due to security mismatch" line.long 0x4 "INTG_CFG__VP__REGS_phy_clk_status,The PHY_CLK_STATUS Register - Returns the current status of the phy data clock from DP phy. When the clock is not running. the ECC_aggr_PHY_cfg_regs will return 0x0 on a read" bitfld.long 0x4 0. "VALID,Phy Data Clock Valid Status 0: Clock is not valid/not running 1: Clock is running" "0: Clock is not valid/not running,1: Clock is running" tree.end tree "DSS_EDP0_MHDPTX_WRAPPER" tree "DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_CORE_CFG (DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_CORE_CFG)" base ad:0x2AC0000 rgroup.long 0x0++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_CORE__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_CORE__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_CORE__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_CORE__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_CORE__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MHDPTX_WRAPPER_ECC_AGGR_CORE__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1" bitfld.long 0x4 1. "RAMECC_DRAM_PEND,Interrupt Pending Status for ramecc_dram_pend" "0,1" newline bitfld.long 0x4 0. "RAMECC_IRAM_PEND,Interrupt Pending Status for ramecc_iram_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_CORE__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1" bitfld.long 0x0 1. "RAMECC_DRAM_ENABLE_SET,Interrupt Enable Set Register for ramecc_dram_pend" "0,1" newline bitfld.long 0x0 0. "RAMECC_IRAM_ENABLE_SET,Interrupt Enable Set Register for ramecc_iram_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_CORE__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1" bitfld.long 0x0 1. "RAMECC_DRAM_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_dram_pend" "0,1" newline bitfld.long 0x0 0. "RAMECC_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_iram_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_CORE__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MHDPTX_WRAPPER_ECC_AGGR_CORE__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1" bitfld.long 0x4 1. "RAMECC_DRAM_PEND,Interrupt Pending Status for ramecc_dram_pend" "0,1" newline bitfld.long 0x4 0. "RAMECC_IRAM_PEND,Interrupt Pending Status for ramecc_iram_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_CORE__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1" bitfld.long 0x0 1. "RAMECC_DRAM_ENABLE_SET,Interrupt Enable Set Register for ramecc_dram_pend" "0,1" newline bitfld.long 0x0 0. "RAMECC_IRAM_ENABLE_SET,Interrupt Enable Set Register for ramecc_iram_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_CORE__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1" bitfld.long 0x0 1. "RAMECC_DRAM_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_dram_pend" "0,1" newline bitfld.long 0x0 0. "RAMECC_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_iram_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_CORE__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MHDPTX_WRAPPER_ECC_AGGR_CORE__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MHDPTX_WRAPPER_ECC_AGGR_CORE__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MHDPTX_WRAPPER_ECC_AGGR_CORE__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_DSC_CFG (DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_DSC_CFG)" base ad:0x2AC2000 rgroup.long 0x0++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_DSC__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_DSC__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_DSC__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_DSC__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_DSC__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MHDPTX_WRAPPER_ECC_AGGR_DSC__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 7. "RAMECC_ENC1_OB0_PEND,Interrupt Pending Status for ramecc_enc1_ob0_pend" "0,1" bitfld.long 0x4 6. "RAMECC_ENC1_SSM_D_PEND,Interrupt Pending Status for ramecc_enc1_ssm_d_pend" "0,1" newline bitfld.long 0x4 5. "RAMECC_ENC1_SSM_S_PEND,Interrupt Pending Status for ramecc_enc1_ssm_s_pend" "0,1" bitfld.long 0x4 4. "RAMECC_ENC1_LB_PEND,Interrupt Pending Status for ramecc_enc1_lb_pend" "0,1" newline bitfld.long 0x4 3. "RAMECC_ENC0_OB0_PEND,Interrupt Pending Status for ramecc_enc0_ob0_pend" "0,1" bitfld.long 0x4 2. "RAMECC_ENC0_SSM_D_PEND,Interrupt Pending Status for ramecc_enc0_ssm_d_pend" "0,1" newline bitfld.long 0x4 1. "RAMECC_ENC0_SSM_S_PEND,Interrupt Pending Status for ramecc_enc0_ssm_s_pend" "0,1" bitfld.long 0x4 0. "RAMECC_ENC0_LB_PEND,Interrupt Pending Status for ramecc_enc0_lb_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_DSC__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 7. "RAMECC_ENC1_OB0_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc1_ob0_pend" "0,1" bitfld.long 0x0 6. "RAMECC_ENC1_SSM_D_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc1_ssm_d_pend" "0,1" newline bitfld.long 0x0 5. "RAMECC_ENC1_SSM_S_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc1_ssm_s_pend" "0,1" bitfld.long 0x0 4. "RAMECC_ENC1_LB_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc1_lb_pend" "0,1" newline bitfld.long 0x0 3. "RAMECC_ENC0_OB0_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc0_ob0_pend" "0,1" bitfld.long 0x0 2. "RAMECC_ENC0_SSM_D_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc0_ssm_d_pend" "0,1" newline bitfld.long 0x0 1. "RAMECC_ENC0_SSM_S_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc0_ssm_s_pend" "0,1" bitfld.long 0x0 0. "RAMECC_ENC0_LB_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc0_lb_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_DSC__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 7. "RAMECC_ENC1_OB0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc1_ob0_pend" "0,1" bitfld.long 0x0 6. "RAMECC_ENC1_SSM_D_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc1_ssm_d_pend" "0,1" newline bitfld.long 0x0 5. "RAMECC_ENC1_SSM_S_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc1_ssm_s_pend" "0,1" bitfld.long 0x0 4. "RAMECC_ENC1_LB_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc1_lb_pend" "0,1" newline bitfld.long 0x0 3. "RAMECC_ENC0_OB0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc0_ob0_pend" "0,1" bitfld.long 0x0 2. "RAMECC_ENC0_SSM_D_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc0_ssm_d_pend" "0,1" newline bitfld.long 0x0 1. "RAMECC_ENC0_SSM_S_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc0_ssm_s_pend" "0,1" bitfld.long 0x0 0. "RAMECC_ENC0_LB_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc0_lb_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_DSC__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MHDPTX_WRAPPER_ECC_AGGR_DSC__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 7. "RAMECC_ENC1_OB0_PEND,Interrupt Pending Status for ramecc_enc1_ob0_pend" "0,1" bitfld.long 0x4 6. "RAMECC_ENC1_SSM_D_PEND,Interrupt Pending Status for ramecc_enc1_ssm_d_pend" "0,1" newline bitfld.long 0x4 5. "RAMECC_ENC1_SSM_S_PEND,Interrupt Pending Status for ramecc_enc1_ssm_s_pend" "0,1" bitfld.long 0x4 4. "RAMECC_ENC1_LB_PEND,Interrupt Pending Status for ramecc_enc1_lb_pend" "0,1" newline bitfld.long 0x4 3. "RAMECC_ENC0_OB0_PEND,Interrupt Pending Status for ramecc_enc0_ob0_pend" "0,1" bitfld.long 0x4 2. "RAMECC_ENC0_SSM_D_PEND,Interrupt Pending Status for ramecc_enc0_ssm_d_pend" "0,1" newline bitfld.long 0x4 1. "RAMECC_ENC0_SSM_S_PEND,Interrupt Pending Status for ramecc_enc0_ssm_s_pend" "0,1" bitfld.long 0x4 0. "RAMECC_ENC0_LB_PEND,Interrupt Pending Status for ramecc_enc0_lb_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_DSC__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 7. "RAMECC_ENC1_OB0_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc1_ob0_pend" "0,1" bitfld.long 0x0 6. "RAMECC_ENC1_SSM_D_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc1_ssm_d_pend" "0,1" newline bitfld.long 0x0 5. "RAMECC_ENC1_SSM_S_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc1_ssm_s_pend" "0,1" bitfld.long 0x0 4. "RAMECC_ENC1_LB_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc1_lb_pend" "0,1" newline bitfld.long 0x0 3. "RAMECC_ENC0_OB0_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc0_ob0_pend" "0,1" bitfld.long 0x0 2. "RAMECC_ENC0_SSM_D_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc0_ssm_d_pend" "0,1" newline bitfld.long 0x0 1. "RAMECC_ENC0_SSM_S_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc0_ssm_s_pend" "0,1" bitfld.long 0x0 0. "RAMECC_ENC0_LB_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc0_lb_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_DSC__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 7. "RAMECC_ENC1_OB0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc1_ob0_pend" "0,1" bitfld.long 0x0 6. "RAMECC_ENC1_SSM_D_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc1_ssm_d_pend" "0,1" newline bitfld.long 0x0 5. "RAMECC_ENC1_SSM_S_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc1_ssm_s_pend" "0,1" bitfld.long 0x0 4. "RAMECC_ENC1_LB_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc1_lb_pend" "0,1" newline bitfld.long 0x0 3. "RAMECC_ENC0_OB0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc0_ob0_pend" "0,1" bitfld.long 0x0 2. "RAMECC_ENC0_SSM_D_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc0_ssm_d_pend" "0,1" newline bitfld.long 0x0 1. "RAMECC_ENC0_SSM_S_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc0_ssm_s_pend" "0,1" bitfld.long 0x0 0. "RAMECC_ENC0_LB_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc0_lb_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_DSC__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MHDPTX_WRAPPER_ECC_AGGR_DSC__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MHDPTX_WRAPPER_ECC_AGGR_DSC__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MHDPTX_WRAPPER_ECC_AGGR_DSC__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_PHY_CFG (DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_PHY_CFG)" base ad:0x2AC1000 rgroup.long 0x0++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_PHY__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_PHY__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_PHY__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_PHY__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_PHY__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MHDPTX_WRAPPER_ECC_AGGR_PHY__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 4. "RAMECC_AIF_MEM_PEND,Interrupt Pending Status for ramecc_aif_mem_pend" "0,1" bitfld.long 0x4 3. "RAMECC_PKT_MEM_3_PEND,Interrupt Pending Status for ramecc_pkt_mem_3_pend" "0,1" newline bitfld.long 0x4 2. "RAMECC_PKT_MEM_2_PEND,Interrupt Pending Status for ramecc_pkt_mem_2_pend" "0,1" bitfld.long 0x4 1. "RAMECC_PKT_MEM_1_PEND,Interrupt Pending Status for ramecc_pkt_mem_1_pend" "0,1" newline bitfld.long 0x4 0. "RAMECC_PKT_MEM_0_PEND,Interrupt Pending Status for ramecc_pkt_mem_0_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_PHY__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 4. "RAMECC_AIF_MEM_ENABLE_SET,Interrupt Enable Set Register for ramecc_aif_mem_pend" "0,1" bitfld.long 0x0 3. "RAMECC_PKT_MEM_3_ENABLE_SET,Interrupt Enable Set Register for ramecc_pkt_mem_3_pend" "0,1" newline bitfld.long 0x0 2. "RAMECC_PKT_MEM_2_ENABLE_SET,Interrupt Enable Set Register for ramecc_pkt_mem_2_pend" "0,1" bitfld.long 0x0 1. "RAMECC_PKT_MEM_1_ENABLE_SET,Interrupt Enable Set Register for ramecc_pkt_mem_1_pend" "0,1" newline bitfld.long 0x0 0. "RAMECC_PKT_MEM_0_ENABLE_SET,Interrupt Enable Set Register for ramecc_pkt_mem_0_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_PHY__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 4. "RAMECC_AIF_MEM_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_aif_mem_pend" "0,1" bitfld.long 0x0 3. "RAMECC_PKT_MEM_3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pkt_mem_3_pend" "0,1" newline bitfld.long 0x0 2. "RAMECC_PKT_MEM_2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pkt_mem_2_pend" "0,1" bitfld.long 0x0 1. "RAMECC_PKT_MEM_1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pkt_mem_1_pend" "0,1" newline bitfld.long 0x0 0. "RAMECC_PKT_MEM_0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pkt_mem_0_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_PHY__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MHDPTX_WRAPPER_ECC_AGGR_PHY__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 4. "RAMECC_AIF_MEM_PEND,Interrupt Pending Status for ramecc_aif_mem_pend" "0,1" bitfld.long 0x4 3. "RAMECC_PKT_MEM_3_PEND,Interrupt Pending Status for ramecc_pkt_mem_3_pend" "0,1" newline bitfld.long 0x4 2. "RAMECC_PKT_MEM_2_PEND,Interrupt Pending Status for ramecc_pkt_mem_2_pend" "0,1" bitfld.long 0x4 1. "RAMECC_PKT_MEM_1_PEND,Interrupt Pending Status for ramecc_pkt_mem_1_pend" "0,1" newline bitfld.long 0x4 0. "RAMECC_PKT_MEM_0_PEND,Interrupt Pending Status for ramecc_pkt_mem_0_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_PHY__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 4. "RAMECC_AIF_MEM_ENABLE_SET,Interrupt Enable Set Register for ramecc_aif_mem_pend" "0,1" bitfld.long 0x0 3. "RAMECC_PKT_MEM_3_ENABLE_SET,Interrupt Enable Set Register for ramecc_pkt_mem_3_pend" "0,1" newline bitfld.long 0x0 2. "RAMECC_PKT_MEM_2_ENABLE_SET,Interrupt Enable Set Register for ramecc_pkt_mem_2_pend" "0,1" bitfld.long 0x0 1. "RAMECC_PKT_MEM_1_ENABLE_SET,Interrupt Enable Set Register for ramecc_pkt_mem_1_pend" "0,1" newline bitfld.long 0x0 0. "RAMECC_PKT_MEM_0_ENABLE_SET,Interrupt Enable Set Register for ramecc_pkt_mem_0_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_PHY__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 4. "RAMECC_AIF_MEM_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_aif_mem_pend" "0,1" bitfld.long 0x0 3. "RAMECC_PKT_MEM_3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pkt_mem_3_pend" "0,1" newline bitfld.long 0x0 2. "RAMECC_PKT_MEM_2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pkt_mem_2_pend" "0,1" bitfld.long 0x0 1. "RAMECC_PKT_MEM_1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pkt_mem_1_pend" "0,1" newline bitfld.long 0x0 0. "RAMECC_PKT_MEM_0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pkt_mem_0_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "MHDPTX_WRAPPER_ECC_AGGR_PHY__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MHDPTX_WRAPPER_ECC_AGGR_PHY__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MHDPTX_WRAPPER_ECC_AGGR_PHY__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MHDPTX_WRAPPER_ECC_AGGR_PHY__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree.end tree "DSS_EDP0_V2A" tree "DSS_EDP0_V2A_CORE_VP_REGS_APB (DSS_EDP0_V2A_CORE_VP_REGS_APB)" base ad:0xA000000 rgroup.long 0x0++0x53 line.long 0x0 "V2A__CORE_VP__REGS_APB_APB_CTRL_p,APB main control register" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline bitfld.long 0x0 3. "APB_XT_RUNSTALL,When 1 stalls the CPU from executing further instructions. This bit must be set HIGH during firmware load." "0,1" newline bitfld.long 0x0 2. "APB_IRAM_PATH,Unused. Kept RW for software backward compatibility." "0,1" newline bitfld.long 0x0 1. "APB_DRAM_PATH,Unused. Kept RW for software backward compatibility." "0,1" newline bitfld.long 0x0 0. "APB_XT_RESET,Internal uCPU reset. Active High. Must be cleared to enable firmware load and normal operation of the uCPU." "0,1" line.long 0x4 "V2A__CORE_VP__REGS_APB_xt_int_ctrl_p,Inernal CPU Interrupt Polarity Control Register." hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline bitfld.long 0x4 0.--1. "XT_INT_POLARITY,Each bit inverts appropriate interrupt signal provided do internal CPU interrupt input." "0,1,2,3" line.long 0x8 "V2A__CORE_VP__REGS_APB_MAILBOX_FULL_ADDR_p,Mailbox full indication status register. This register provides a status of the mailbox that is used to send messages from the Host processor to internal uCPU." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline rbitfld.long 0x8 0. "MAILBOX_FULL,Mailbox full indication. 0x1-mailbox full. No more messages can be sent to mailbox 0x0-mailbox not-full. At least 1 write can be performed to mailbox" "0: mailbox not-full,1: mailbox full" line.long 0xC "V2A__CORE_VP__REGS_APB_MAILBOX_EMPTY_ADDR_p,Mailbox empty indication status register. This register provides a status of the mailbox that is used to send responses from the internal uCPU to host processor as a result of previously sent message." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline rbitfld.long 0xC 0. "MAILBOX_EMPTY,Mailbox empty indication. 0x1-mailbox empty. No response available 0x0-mailbox not-empty. There is at least 1 byte of a response in mailbox available to read by Host processor" "0: mailbox not-empty,1: mailbox empty" line.long 0x10 "V2A__CORE_VP__REGS_APB_mailbox0_wr_data_p,Mailbox write data register." hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x10 0.--7. 1. "MAILBOX0_WR_DATA,Mailbox write data." line.long 0x14 "V2A__CORE_VP__REGS_APB_mailbox0_rd_data_p,Mailbox Read data register." hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x14 0.--7. 1. "MAILBOX0_RD_DATA,Mailbox Read data." line.long 0x18 "V2A__CORE_VP__REGS_APB_KEEP_ALIVE_p,Software keep alive counter." hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x18 0.--7. 1. "KEEP_ALIVE_CNT,Software keep alive counter. Counter is initialized to 0x0 after reset and incremented by 0x1 with every FW kernel loop. It can be used to determine if internal CPU started running correctly." line.long 0x1C "V2A__CORE_VP__REGS_APB_VER_L_p,Software Version Register." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x1C 0.--7. 1. "VER_LSB,Software Version lower byte. Loaded by Firmware at the beginning of firmware operation." line.long 0x20 "V2A__CORE_VP__REGS_APB_VER_H_p,Software Version Register." hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x20 0.--7. 1. "VER_MSB,Software Version higher byte. Loaded by Firmware at the beginning of firmware operation." line.long 0x24 "V2A__CORE_VP__REGS_APB_VER_LIB_L_ADDR_p,Software Library Version Register." hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x24 0.--7. 1. "SW_LIB_VER_L,Software Library Version lower byte. Loaded by Firmware at the beginning of firmware operation." line.long 0x28 "V2A__CORE_VP__REGS_APB_VER_LIB_H_ADDR_p,Software Library Version Register." hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x28 0.--7. 1. "SW_LIB_VER_H,Software Library Version higher byte. Loaded by Firmware at the beginning of firmware operation." line.long 0x2C "V2A__CORE_VP__REGS_APB_SW_DEBUG_L_p,Software/Firmware Debug Register." hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x2C 0.--7. 1. "SW_DEBUG_7_0,Register used for debug purposes [lower byte]. Can be written internally by firmware to allow Core Driver to read the internal status. Not used during normal operation since it requires a special version of firmware with a debug capabilities." line.long 0x30 "V2A__CORE_VP__REGS_APB_SW_DEBUG_H_p,Software/Firmware Debug Register." hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x30 0.--7. 1. "SW_DEBUG_15_8,Register used for debug purposes [higher byte]. Can be written internally by firmware to allow Core Driver to read the internal status. Not used during normal operation since it requires a special version of firmware with a debug.." line.long 0x34 "V2A__CORE_VP__REGS_APB_MAILBOX_INT_MASK_p,Mailbox Interrupt mask register." hexmask.long 0x34 2.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline bitfld.long 0x34 1. "MAILBOX_FULL_INT_MASK,Mailbox Full Interrupt mask 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0x34 0. "MAILBOX_EMPTY_INT_MASK,Mailbox Not-empty Interrupt mask 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" line.long 0x38 "V2A__CORE_VP__REGS_APB_MAILBOX_INT_STATUS_p,Mailbox Interrupt Status register." hexmask.long 0x38 2.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline rbitfld.long 0x38 1. "MAILBOX_FULL_INT_STATUS,Mailbox full interrupt. Active HIGH. Cleared on read. This interrupt is set when mailbox becomes full which means there is no more space for messages sent from Host processor to internal uCPU and when this interrupt is enabled in.." "0,1" newline rbitfld.long 0x38 0. "MAILBOX_EMPTY_INT_STATUS,Mailbox not-empty interrupt. Active HIGH. Cleared on read. This interrupt is set when mailbox becomes not-empty which means there is a response in the mailbox available to read by the Host processer and when interrupt is enabled.." "0,1" line.long 0x3C "V2A__CORE_VP__REGS_APB_SW_CLK_L_p,Core Clock frequency" hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x3C 0.--7. 1. "SW_CLOCK_VAL_L,Fractional of the clock decimal value. Should be loaded by API to the value that reflects the frequency of clock provided to core clock input." line.long 0x40 "V2A__CORE_VP__REGS_APB_SW_CLK_H_p,Core Clock frequency" hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x40 0.--7. 1. "SW_CLOCK_VAL_H,Clock frequency in decimal values. Should be loaded by API to the value that reflects the frequency of clock provided to core clock input." line.long 0x44 "V2A__CORE_VP__REGS_APB_SW_EVENTS0_p,Bits [7:0] of the software events status vector. This register is used to report internal events that have been detected by the firmware to the host processor. Register is written by the internal uCPU. It is cleared.." hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x44 0.--7. 1. "SW_EVENTS7_0,Each bit represents a separate event reported by the internal uCPU. If bit is set to 1 event is reported. All events are cleared upon read. Detailed description in Cadence HD Display TX Controller Programming Interface document." line.long 0x48 "V2A__CORE_VP__REGS_APB_SW_EVENTS1_p,SW Event 1 register" hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x48 0.--7. 1. "SW_EVENTS15_8,Each bit represents a separate event reported by the internal uCPU. If bit is set to 1 event is reported. All events are cleared upon read. Detailed description in Cadence HD Display TX Controller Programming Interface document." line.long 0x4C "V2A__CORE_VP__REGS_APB_SW_EVENTS2_p,SW Event 2 register" hexmask.long.tbyte 0x4C 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x4C 0.--7. 1. "SW_EVENTS23_16,Each bit represents a separate event reported by the internal uCPU. If bit is set to 1 event is reported. All events are cleared upon read. Detailed description in Cadence HD Display TX Controller Programming Interface document." line.long 0x50 "V2A__CORE_VP__REGS_APB_SW_EVENTS3_p,SW Event 3 register" hexmask.long.tbyte 0x50 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x50 0.--7. 1. "SW_EVENTS31_24,Each bit represents a separate event reported by the internal uCPU. If bit is set to 1 event is reported. All events are cleared upon read. Detailed description in Cadence HD Display TX Controller Programming Interface document." rgroup.long 0x60++0x7 line.long 0x0 "V2A__CORE_VP__REGS_APB_XT_OCD_CTRL_p,Internal CPU - On Chip Debug (OCD) Ctrl Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline bitfld.long 0x0 1. "XT_OCDHALTONRESET,Internal CPU - Halt On Reget configuration register" "0,1" newline bitfld.long 0x0 0. "XT_DRESET,Internal CPU - Dreset control register" "0,1" line.long 0x4 "V2A__CORE_VP__REGS_APB_XT_OCD_CTRL_RO_p,Internal CPU - OCD R0 mode configuration" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline rbitfld.long 0x4 0. "XT_XOCDMODE,Internal CPU - OCD mode configuration" "0,1" rgroup.long 0x6C++0x7 line.long 0x0 "V2A__CORE_VP__REGS_APB_APB_INT_MASK_p,APB Interrupt Mask Register" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline bitfld.long 0x0 3. "APB_CEC_INTR_MASK,Reserved field. 0x0 when read. Writes ignored." "0,1" newline bitfld.long 0x0 2. "APB_PIF_INTR_MASK,PIF module Interrupt mask 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0x0 1. "APB_SW_INTR_MASK,SW Event Interrupt mask 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0x0 0. "APB_MAILBOX_INTR_MASK,Mailbox Interrupt mask 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" line.long 0x4 "V2A__CORE_VP__REGS_APB_APB_INT_STATUS_p,APB interrupt status register" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline rbitfld.long 0x4 3. "APB_CEC_INTR_STATUS,Reserved." "0,1" newline rbitfld.long 0x4 2. "APB_PIF_INTR_STATUS,PIF module Interrupt status. Active HIGH. If this bit is set further status should be read from SOURCE_PIF_INTERRUPT_SOURCE register. This bit is cleared automatically on read from SOURCE_PIF_INTERRUPT_SOURCE register." "0,1" newline rbitfld.long 0x4 1. "APB_SW_INTR_STATUS,SW Events Interrupt status. Active HIGH. If this bit is set further status should be read from SW_EVENTSn registers. This bit is cleared automatically on read from SW_EVENTSn registers if there are no more events." "0,1" newline rbitfld.long 0x4 0. "APB_MAILBOX_INTR_STATUS,Mailbox Interrupt status. Active HIGH. If this bit is set further status should be read from MAILBOX_INT_STATUS register. This bit is cleared automatically on read from MAILBOX_INT_STATUS register." "0,1" rgroup.long 0xA0++0x3 line.long 0x0 "V2A__CORE_VP__REGS_APB_CDNS_DID_p,Number identifying the IP." hexmask.long 0x0 0.--31. 1. "IPVER,0x8546 - DisplayPort 1.4/EmbeddedDisplayPort 1.4 Tx Combo Controller" rgroup.long 0xA4++0x3 line.long 0x0 "V2A__CORE_VP__REGS_APB_CDNS_RID0_p,Number identifying IP version." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.word 0x0 0.--15. 1. "IP_VERSION,IP version: r[15:4]v[3:0]" rgroup.long 0xA8++0x3 line.long 0x0 "V2A__CORE_VP__REGS_APB_CDNS_RID1_p,Numbers identifying PHY and AUX version" hexmask.long.word 0x0 16.--31. 1. "AUX_VERSION,AUX version: r[31:20]v[19:16]" newline hexmask.long.word 0x0 0.--15. 1. "PHY_VERSION,PHY version: r[15:4]v[3:0]" rgroup.long 0xAC++0x3 line.long 0x0 "V2A__CORE_VP__REGS_APB_CDNS_CFGS0_p,Numbers identifying the capabilities/configuration of the MHDP controller. Values not explicitely listed below ar ereserved for future use." hexmask.long.byte 0x0 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 24.--27. 1. "AUDIO_STREAM_NUMBER,Secondary configuration. Number of audio streams supported" newline hexmask.long.byte 0x0 20.--23. 1. "VIDEO_STREAM_NUMBER,Secondary configuration. Number of video streams supported" newline rbitfld.long 0x0 18.--19. "ASF_SUPPORT,Secondary configuration. ASF support. 0x0: ASF not supported 0x1: ASF supported" "0: ASF not supported,1: ASF supported,?,?" newline rbitfld.long 0x0 16.--17. "DSC_SUPPORT,Secondary configuration. DSC support. 0x0: DSC not supported 0x1: DSC supported" "0: DSC not supported,1: DSC supported,?,?" newline hexmask.long.byte 0x0 8.--15. 1. "IP_NUMBER_FAMILY,Main configuration. IP Family Code. 0x00: Display TX Controller 0x01: Display RX Controller" newline hexmask.long.byte 0x0 0.--7. 1. "IP_NUMBER_CONFIGURATION,Main configuration. IP configuration. 0x00 - HDMI+DP+HDPC 0x01 - HDMI+HDCP 0x02 - DP+HDCP 0x03 - HDMI+DP" rgroup.long 0xB0++0x3 line.long 0x0 "V2A__CORE_VP__REGS_APB_CDNS_CFGS1_p,Numbers identifying type of PHY and AUX are integrated in the IPS. Fixed for a given IPS configuration." hexmask.long.word 0x0 16.--31. 1. "AUX_NUMBER,AUX IP Number according to versioning scheme." newline hexmask.long.word 0x0 0.--15. 1. "PHY_NUMBER,PHY IP Number according to versioning scheme." rgroup.long 0x800++0x1F line.long 0x0 "V2A__CORE_VP__REGS_APB_SHIFT_PATTERN_IN_3_0_p,HDMI shift pattern 3-0" hexmask.long.byte 0x0 24.--31. 1. "SOURCE_PHY_SHIFT_PATTERN3,Input to hdmi_pattern_shift" newline hexmask.long.byte 0x0 16.--23. 1. "SOURCE_PHY_SHIFT_PATTERN2,Input to hdmi_pattern_shift" newline hexmask.long.byte 0x0 8.--15. 1. "SOURCE_PHY_SHIFT_PATTERN1,Input to hdmi_pattern_shift" newline hexmask.long.byte 0x0 0.--7. 1. "SOURCE_PHY_SHIFT_PATTERN0,Input to hdmi_pattern_shift" line.long 0x4 "V2A__CORE_VP__REGS_APB_SHIFT_PATTERN_IN_4_7_p,HDMI shift pattern 4-7" hexmask.long.byte 0x4 24.--31. 1. "SOURCE_PHY_SHIFT_PATTERN7,Input to hdmi_pattern_shift" newline hexmask.long.byte 0x4 16.--23. 1. "SOURCE_PHY_SHIFT_PATTERN6,Input to hdmi_pattern_shift" newline hexmask.long.byte 0x4 8.--15. 1. "SOURCE_PHY_SHIFT_PATTERN5,Input to hdmi_pattern_shift" newline hexmask.long.byte 0x4 0.--7. 1. "SOURCE_PHY_SHIFT_PATTERN4,Input to hdmi_pattern_shift" line.long 0x8 "V2A__CORE_VP__REGS_APB_SHIFT_PATTERN_IN9_8_p,HDMI shift pattern 9-8 with control bits" hexmask.long.word 0x8 21.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline bitfld.long 0x8 18.--20. "SOURCE_PHY_SHIFT_REPETITION,Shift repetition Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 17. "SOURCE_PHY_SHIFT_EN,When 1 enable the Shift pattern Mechanism" "0,1" newline bitfld.long 0x8 16. "SOURCE_PHY_SHIFT_LOAD,When 1 load the 80 bits of data" "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "SOURCE_PHY_SHIFT_PATTERN9,Input to hdmi_pattern_shift" newline hexmask.long.byte 0x8 0.--7. 1. "SOURCE_PHY_SHIFT_PATTERN8,Input to hdmi_pattern_shift" line.long 0xC "V2A__CORE_VP__REGS_APB_PRBS_CNTRL_p,PRBS control" hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline bitfld.long 0xC 14.--15. "SOURCE_PHY_PRBS3_OUT_MODE,00 = idle output all zeros 01 = output 8 bits on pattern[7:0] 10 = output 1 bit on pattern[9] and output inverted bit on pattern[8] 11 = output 10 bits on pattern[9:0]" "0: idle,1: output 8 bits on pattern[7:0],?,?" newline bitfld.long 0xC 12.--13. "SOURCE_PHY_PRBS3_MODE,00 = PRBS11 01 = PRBS15 10 = PRBS7 11 = PRBS31" "0: PRBS11,1: PRBS15,?,?" newline bitfld.long 0xC 10.--11. "SOURCE_PHY_PRBS2_OUT_MODE,00 = idle output all zeros 01 = output 8 bits on pattern[7:0] 10 = output 1 bit on pattern[9] and output inverted bit on pattern[8] 11 = output 10 bits on pattern[9:0]" "0: idle,1: output 8 bits on pattern[7:0],?,?" newline bitfld.long 0xC 8.--9. "SOURCE_PHY_PRBS2_MODE,00 = PRBS11 01 = PRBS15 10 = PRBS7 11 = PRBS31" "0: PRBS11,1: PRBS15,?,?" newline bitfld.long 0xC 6.--7. "SOURCE_PHY_PRBS1_OUT_MODE,00 = idle output all zeros 01 = output 8 bits on pattern[7:0] 10 = output 1 bit on pattern[9] and output inverted bit on pattern[8] 11 = output 10 bits on pattern[9:0]" "0: idle,1: output 8 bits on pattern[7:0],?,?" newline bitfld.long 0xC 4.--5. "SOURCE_PHY_PRBS1_MODE,00 = PRBS11 01 = PRBS15 10 = PRBS7 11 = PRBS31" "0: PRBS11,1: PRBS15,?,?" newline bitfld.long 0xC 2.--3. "SOURCE_PHY_PRBS0_OUT_MODE,00 = idle output all zeros 01 = output 8 bits on pattern[7:0] 10 = output 1 bit on pattern[9] and output inverted bit on pattern[8] 11 = output 10 bits on pattern[9:0]" "0: idle,1: output 8 bits on pattern[7:0],?,?" newline bitfld.long 0xC 0.--1. "SOURCE_PHY_PRBS0_MODE,00 = PRBS11 01 = PRBS15 10 = PRBS7 11 = PRBS31" "0: PRBS11,1: PRBS15,?,?" line.long 0x10 "V2A__CORE_VP__REGS_APB_PRBS_ERR_INSERTION_p,PRBS error insertion" hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x10 19.--23. 1. "NUMBER_OF_ERRORS3,The number of errors to be inserted when add_error is high." newline bitfld.long 0x10 18. "ADD_ERROR3,When high the PRBS generator inserts the number of errors written in number_of_errors field." "0,1" newline hexmask.long.byte 0x10 13.--17. 1. "NUMBER_OF_ERRORS2,The number of errors to be inserted when add_error is high." newline bitfld.long 0x10 12. "ADD_ERROR2,When high the PRBS generator inserts the number of errors written in number_of_errors field." "0,1" newline hexmask.long.byte 0x10 7.--11. 1. "NUMBER_OF_ERRORS1,The number of errors to be inserted when add_error is high." newline bitfld.long 0x10 6. "ADD_ERROR1,When high the PRBS generator inserts the number of errors written in number_of_errors field" "0,1" newline hexmask.long.byte 0x10 1.--5. 1. "NUMBER_OF_ERRORS0,The number of errors to be inserted when add_error is high." newline bitfld.long 0x10 0. "ADD_ERROR0,When high the PRBS generator inserts the number of errors written in number_of_errors field" "0,1" line.long 0x14 "V2A__CORE_VP__REGS_APB_LANES_CONFIG_p,Lane control register: swap. order. polarity" hexmask.long.word 0x14 23.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline bitfld.long 0x14 22. "SOURCE_PHY_20_10,1'b0: Data to PHY is 10 bit with char clock 1'd1: Data to PHY is 20 bit with data clock" "0: Data to PHY is 10 bit with char clock 1'd1: Data..,?" newline bitfld.long 0x14 21. "SOURCE_PHY_COMB_BYPASS,Bypass swap invert and all combination" "0,1" newline bitfld.long 0x14 20. "SOURCE_PHY_DATA_DEL_EN,enable configurable delay of lanes to be activated.if this bit is 0 the delay is only activated for DisplayPort mode with source_phy_data_sel=prbs or shift-mem" "0,1" newline bitfld.long 0x14 19. "SOURCE_PHY_LANE3_POLARITY,Reverse polarity of data lane3" "0,1" newline bitfld.long 0x14 18. "SOURCE_PHY_LANE2_POLARITY,Reverse polarity of data lane2" "0,1" newline bitfld.long 0x14 17. "SOURCE_PHY_LANE1_POLARITY,Reverse polarity of data lane1" "0,1" newline bitfld.long 0x14 16. "SOURCE_PHY_LANE0_POLARITY,Reverse polarity of data lane0" "0,1" newline hexmask.long.byte 0x14 12.--15. 1. "SOURCE_PHY_AUX_SPARE,Spare bits for aux **1.1**" newline bitfld.long 0x14 11. "SOURCE_PHY_LANE3_LSB_MSB,Reverse order of data lane3" "0,1" newline bitfld.long 0x14 10. "SOURCE_PHY_LANE2_LSB_MSB,Reverse order of data lane2" "0,1" newline bitfld.long 0x14 9. "SOURCE_PHY_LANE1_LSB_MSB,Reverse order of data lane1" "0,1" newline bitfld.long 0x14 8. "SOURCE_PHY_LANE0_LSB_MSB,Reverse order of data lane0" "0,1" newline bitfld.long 0x14 6.--7. "SOURCE_PHY_LANE3_SWAP,Swap control lane3" "0,1,2,3" newline bitfld.long 0x14 4.--5. "SOURCE_PHY_LANE2_SWAP,Swap control lane2" "0,1,2,3" newline bitfld.long 0x14 2.--3. "SOURCE_PHY_LANE1_SWAP,Swap control lane1" "0,1,2,3" newline bitfld.long 0x14 0.--1. "SOURCE_PHY_LANE0_SWAP,Swap control lane0" "0,1,2,3" line.long 0x18 "V2A__CORE_VP__REGS_APB_PHY_DATA_SEL_p,PHY data select DP/HDMI and HDMI data source" hexmask.long 0x18 5.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline bitfld.long 0x18 3.--4. "SOURCE_PHY_MHDP_SEL,3'd0: tx_data = DP 3'd1: tx_data = HDMI 3'd2: tx_data = RSRV 3'd3: tx_data = RSRV" "0: tx_data = DP 3'd1: tx_data = HDMI 3'd2: tx_data..,?,?,?" newline bitfld.long 0x18 0.--2. "SOURCE_PHY_DATA_SEL,3'd0: tx_data = phy_dout 3'd1: tx_data = phy_dout_bypass 3'd2: tx_data = source_phy_prbs_pout 3'd3: tx_data = source_phy_shift_pout" "0: tx_data = phy_dout 3'd1: tx_data =..,?,?,?,?,?,?,?" line.long 0x1C "V2A__CORE_VP__REGS_APB_LANES_DEL_VAL_p,Lane delay control" hexmask.long.word 0x1C 16.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x1C 12.--15. 1. "SOURCE_PHY_LANE3_DEL_VAL,delay for lane 3 this parameter can take values from 0 up to 8. All other values are reserved" newline hexmask.long.byte 0x1C 8.--11. 1. "SOURCE_PHY_LANE2_DEL_VAL,delay for lane 2 this parameter can take values from 0 up to 8. All other values are reserved" newline hexmask.long.byte 0x1C 4.--7. 1. "SOURCE_PHY_LANE1_DEL_VAL,delay for lane 1 this parameter can take values from 0 up to 8. All other values are reserved" newline hexmask.long.byte 0x1C 0.--3. 1. "SOURCE_PHY_LANE0_DEL_VAL,delay for lane 0 this parameter can take values from 0 up to 8. All other values are reserved" rgroup.long 0x904++0x7 line.long 0x0 "V2A__CORE_VP__REGS_APB_source_dptx_car_p,DP TX clock and reset ctrl register" hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x0 25. "CFG_DPTX_VIF_CLK_RSTN_EN7,dptx_vif_clk_rstn enable for stream number 7 - active low" "0,1" newline bitfld.long 0x0 24. "CFG_DPTX_VIF_CLK_EN7,dptx_vif_clk enable for stream number 7 - active high" "0,1" newline bitfld.long 0x0 23. "CFG_DPTX_VIF_CLK_RSTN_EN6,dptx_vif_clk_rstn enable for stream number 6 - active low" "0,1" newline bitfld.long 0x0 22. "CFG_DPTX_VIF_CLK_EN6,dptx_vif_clk enable for stream number 6 - active high" "0,1" newline bitfld.long 0x0 21. "CFG_DPTX_VIF_CLK_RSTN_EN5,dptx_vif_clk_rstn enable for stream number 5 - active low" "0,1" newline bitfld.long 0x0 20. "CFG_DPTX_VIF_CLK_EN5,dptx_vif_clk enable for stream number 5 - active high" "0,1" newline bitfld.long 0x0 19. "CFG_DPTX_VIF_CLK_RSTN_EN4,dptx_vif_clk_rstn enable for stream number 4 - active low" "0,1" newline bitfld.long 0x0 18. "CFG_DPTX_VIF_CLK_EN4,dptx_vif_clk enable for stream number 4 - active high" "0,1" newline bitfld.long 0x0 17. "CFG_DPTX_VIF_CLK_RSTN_EN3,dptx_vif_clk_rstn enable for stream number 3 - active low" "0,1" newline bitfld.long 0x0 16. "CFG_DPTX_VIF_CLK_EN3,dptx_vif_clk enable for stream number 3 - active high" "0,1" newline bitfld.long 0x0 15. "CFG_DPTX_VIF_CLK_RSTN_EN2,dptx_vif_clk_rstn enable for stream number 2 - active low" "0,1" newline bitfld.long 0x0 14. "CFG_DPTX_VIF_CLK_EN2,dptx_vif_clk enable for stream number 2 - active high" "0,1" newline bitfld.long 0x0 13. "CFG_DPTX_VIF_CLK_RSTN_EN1,dptx_vif_clk_rstn enable for stream number 1 - active low" "?,1: active low" newline bitfld.long 0x0 12. "CFG_DPTX_VIF_CLK_EN1,dptx_vif_clk enable for stream number 1 - active high" "?,1: active high" newline bitfld.long 0x0 11. "DPTX_FRMR_DATA_CLK_RSTN_EN,dptx_frmr_data_clk_rstn enable - active low" "0,1" newline bitfld.long 0x0 10. "DPTX_FRMR_DATA_CLK_EN,dptx_frmr_data_clk enable - active high" "0,1" newline bitfld.long 0x0 9. "DPTX_PHY_DATA_RSTN_EN,dptx_phy_data_rstn enable - active low" "0,1" newline bitfld.long 0x0 8. "DPTX_PHY_DATA_CLK_EN,dptx_phy_data_clk enable - active high" "0,1" newline bitfld.long 0x0 7. "DPTX_PHY_CHAR_RSTN_EN,dptx_phy_char_rstn enable - active low" "0,1" newline bitfld.long 0x0 6. "DPTX_PHY_CHAR_CLK_EN,dptx_phy_char_clk enable - active high" "0,1" newline bitfld.long 0x0 5. "SOURCE_AUX_SYS_CLK_RSTN_EN,source_aux_sys_clk_rstn enable - active low" "0,1" newline bitfld.long 0x0 4. "SOURCE_AUX_SYS_CLK_EN,source_aux_sys_clk enable - active high" "0,1" newline bitfld.long 0x0 3. "DPTX_SYS_CLK_RSTN_EN,dptx_sys_clk_rstn enable - active low" "0,1" newline bitfld.long 0x0 2. "DPTX_SYS_CLK_EN,dptx_sys_clk enable - active high" "0,1" newline bitfld.long 0x0 1. "CFG_DPTX_VIF_CLK_RSTN_EN,dptx_vif_clk_rstn enable - active low" "0,1" newline bitfld.long 0x0 0. "CFG_DPTX_VIF_CLK_EN,dptx_vif_clk enable - active high" "0,1" line.long 0x4 "V2A__CORE_VP__REGS_APB_source_phy_car_p,Source PHY clock and reset ctrl register" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x4 3. "SOURCE_PHY_CHAR_OUT_CLK_RSTN_EN,source_phy_char_out_clk_rstn enable - active low" "0,1" newline bitfld.long 0x4 2. "SOURCE_PHY_CHAR_OUT_CLK_EN,source_phy_char_out_clk enable - active high" "0,1" newline bitfld.long 0x4 1. "SOURCE_PHY_DATA_OUT_CLK_RSTN_EN,source_phy_data_out_clk_rstn enable - active low" "0,1" newline bitfld.long 0x4 0. "SOURCE_PHY_DATA_OUT_CLK_EN,source_phy_data_out_clk enable - active high" "0,1" rgroup.long 0x918++0x13 line.long 0x0 "V2A__CORE_VP__REGS_APB_source_pkt_car_p,PKT clock and reset ctrl register" hexmask.long.word 0x0 18.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x0 17. "SOURCE_PKT_DATA_RSTN_EN7,source_pkt_data_rstn_en7 - active low" "0,1" newline bitfld.long 0x0 16. "SOURCE_PKT_DATA_CLK_EN7,source_pkt_data_clk_en7 - active high" "0,1" newline bitfld.long 0x0 15. "SOURCE_PKT_DATA_RSTN_EN6,source_pkt_data_rstn_en6 - active low" "0,1" newline bitfld.long 0x0 14. "SOURCE_PKT_DATA_CLK_EN6,source_pkt_data_clk_en6 - active high" "0,1" newline bitfld.long 0x0 13. "SOURCE_PKT_DATA_RSTN_EN5,source_pkt_data_rstn_en5 - active low" "0,1" newline bitfld.long 0x0 12. "SOURCE_PKT_DATA_CLK_EN5,source_pkt_data_clk_en5 - active high" "0,1" newline bitfld.long 0x0 11. "SOURCE_PKT_DATA_RSTN_EN4,source_pkt_data_rstn_en4 - active low" "0,1" newline bitfld.long 0x0 10. "SOURCE_PKT_DATA_CLK_EN4,source_pkt_data_clk_en4 - active high" "0,1" newline bitfld.long 0x0 9. "SOURCE_PKT_DATA_RSTN_EN3,source_pkt_data_rstn_en3 - active low" "0,1" newline bitfld.long 0x0 8. "SOURCE_PKT_DATA_CLK_EN3,source_pkt_data_clk_en3 - active high" "0,1" newline bitfld.long 0x0 7. "SOURCE_PKT_DATA_RSTN_EN2,source_pkt_data_rstn_en2 - active low" "0,1" newline bitfld.long 0x0 6. "SOURCE_PKT_DATA_CLK_EN2,source_pkt_data_clk_en2 - active high" "0,1" newline bitfld.long 0x0 5. "SOURCE_PKT_DATA_RSTN_EN1,source_pkt_data_rstn_en1 - active low" "?,1: active low" newline bitfld.long 0x0 4. "SOURCE_PKT_DATA_CLK_EN1,source_pkt_data_clk_en1 - active high" "?,1: active high" newline bitfld.long 0x0 3. "SOURCE_PKT_SYS_RSTN_EN,source_pkt_sys_rstn_en - active low" "0,1" newline bitfld.long 0x0 2. "SOURCE_PKT_SYS_CLK_EN,source_pkt_sys_clk_en - active high" "0,1" newline bitfld.long 0x0 1. "SOURCE_PKT_DATA_RSTN_EN,source_pkt_data_rstn_en - active low" "0,1" newline bitfld.long 0x0 0. "SOURCE_PKT_DATA_CLK_EN,source_pkt_data_clk_en - active high" "0,1" line.long 0x4 "V2A__CORE_VP__REGS_APB_source_aif_car_p,AIF clock and reset ctrl register" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x4 3. "SOURCE_AIF_SYS_RSTN_EN,source_aif_sys_rstn enable - active low" "0,1" newline bitfld.long 0x4 2. "SOURCE_AIF_SYS_CLK_EN,source_aif_sys_clk enable - active high" "0,1" newline bitfld.long 0x4 1. "SOURCE_AIF_PKT_CLK_RSTN_EN,source_aif_pkt_clk_rstn enable - active low" "0,1" newline bitfld.long 0x4 0. "SOURCE_AIF_PKT_CLK_EN,source_aif_pkt_clk enable - active high" "0,1" line.long 0x8 "V2A__CORE_VP__REGS_APB_source_cipher_car_p,Cipher clock and reset ctrl register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x8 3. "SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN,source_cipher_system_clk_rstn enable - active low [Only when HDCP used]" "0,1" newline bitfld.long 0x8 2. "SOURCE_CIPHER_SYS_CLK_EN,source_cipher_sys_clk enable - active high [Only when HDCP used]" "0,1" newline bitfld.long 0x8 1. "SOURCE_CIPHER_CHAR_CLK_RSTN_EN,source_cipher_char_clk_rstn enable - active low [Only when HDCP used]" "0,1" newline bitfld.long 0x8 0. "SOURCE_CIPHER_CHAR_CLK_EN,source_cipher_char_clk enable - active high [Only when HDCP used]" "0,1" line.long 0xC "V2A__CORE_VP__REGS_APB_source_crypto_car_p,Crypto clock and reset ctrl register" hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0xC 1. "SOURCE_CRYPTO_SYS_CLK_RSTN_EN,source_crypto_sys_clk_rstn enable - active low [Only when HDCP used]" "0,1" newline bitfld.long 0xC 0. "SOURCE_CRYPTO_SYS_CLK_EN,source_crypto_sys_clk enable - active high [Only when HDCP used]" "0,1" line.long 0x10 "V2A__CORE_VP__REGS_APB_source_spdif_car_p,SPDIF clock and reset ctrl register" hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x10 3. "SPDIF_MCLK_RSTN_EN0,spdif_mclk_rstn enable0 - active low" "0: active low,?" newline bitfld.long 0x10 2. "SPDIF_MCLK_EN0,spdif_mclk enable0 - active high" "0: active high,?" newline bitfld.long 0x10 1. "SPDIF_CDR_CLK_RSTN_EN0,spdif_cdr_clk_rstn enable0 - active low" "0: active low,?" newline bitfld.long 0x10 0. "SPDIF_CDR_CLK_EN0,spdif_cdr_clk enable0 - active high" "0: active high,?" rgroup.long 0x2000++0x1F line.long 0x0 "V2A__CORE_VP__REGS_APB_DP_TX_PHY_CONFIG_REG_p,DPTX PHY control" hexmask.long.word 0x0 22.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x0 21. "DP_TX_PHY_10BIT_ENABLE,Used to enable the 10-bit mode. Active high." "0,1" newline bitfld.long 0x0 18.--20. "DP_TX_PHY_LANE3_SKEW,Specifies the programmable lane3 skew." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15.--17. "DP_TX_PHY_LANE2_SKEW,Specifies the programmable lane2 skew." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "DP_TX_PHY_LANE1_SKEW,Specifies the programmable lane1 skew." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 9.--11. "DP_TX_PHY_LANE0_SKEW,Specifies the programmable lane0 skew." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "DP_TX_PHY_TRAINING_AUTOMATIC,When set the dp_tx_phy_scrambler_bypass and the dp_tx_phy_encoder_bypass bits are ignored during training pattern generation. This is a debug feature." "0,1" newline bitfld.long 0x0 7. "DP_TX_PHY_SKEW_BYPASS,Used to bypass the lane skew. Active high. This is a debug feature." "0,1" newline bitfld.long 0x0 6. "DP_TX_PHY_ENCODER_BYPASS,Used to bypass the encoder. Active high. This is a debug feature." "0,1" newline bitfld.long 0x0 5. "DP_TX_PHY_SCRAMBLER_BYPASS,Used to bypass the scrambler. Active high. This is a debug feature." "0,1" newline hexmask.long.byte 0x0 1.--4. 1. "DP_TX_PHY_TRAINING_TYPE,Specifies the training pattern type used as follows: 0000 PRBS7 0001 TPS1 0010 TPS2 0011 TPS3 0100 TPS4 0101 custom 80-bit pattern 0110 D10.2 training pattern 0111 Symbol Error Rate Measurement pattern 1000.." newline bitfld.long 0x0 0. "DP_TX_PHY_TRAINING_ENABLE,Enables the training sequence [when set to 1]." "0,1" line.long 0x4 "V2A__CORE_VP__REGS_APB_DP_TX_PHY_SW_RESET_p,DPTC PHY software reset" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x4 0. "DP_TX_PHY_SW_RST,Software reset. Active high." "0,1" line.long 0x8 "V2A__CORE_VP__REGS_APB_DP_TX_PHY_SCRAMBLER_SEED_p,Scrambler seed" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.word 0x8 0.--15. 1. "DP_TX_PHY_SCRAMBLER_SEED,Scrambler seed range 0-0xFFFF" line.long 0xC "V2A__CORE_VP__REGS_APB_DP_TX_PHY_TRAINING_01_04_p,Custom training value bytes 1-4" hexmask.long.byte 0xC 24.--31. 1. "DP_TX_PHY_TRAINING_04,Byte 4 of the 80-bit custom training data." newline hexmask.long.byte 0xC 16.--23. 1. "DP_TX_PHY_TRAINING_03,Byte 3 of the 80-bit custom training data." newline hexmask.long.byte 0xC 8.--15. 1. "DP_TX_PHY_TRAINING_02,Byte 2 of the 80-bit custom training data." newline hexmask.long.byte 0xC 0.--7. 1. "DP_TX_PHY_TRAINING_01,Byte 1 of the 80-bit custom training data." line.long 0x10 "V2A__CORE_VP__REGS_APB_DP_TX_PHY_TRAINING_05_08_p,Custom training value bytes 5-8" hexmask.long.byte 0x10 24.--31. 1. "DP_TX_PHY_TRAINING_08,Byte 8 of the 80-bit custom training data." newline hexmask.long.byte 0x10 16.--23. 1. "DP_TX_PHY_TRAINING_07,Byte 7 of the 80-bit custom training data." newline hexmask.long.byte 0x10 8.--15. 1. "DP_TX_PHY_TRAINING_06,Byte 6 of the 80-bit custom training data." newline hexmask.long.byte 0x10 0.--7. 1. "DP_TX_PHY_TRAINING_05,Byte 5 of the 80-bit custom training data." line.long 0x14 "V2A__CORE_VP__REGS_APB_DP_TX_PHY_TRAINING_09_10_p,Custom training value bytes 9-10" hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.byte 0x14 8.--15. 1. "DP_TX_PHY_TRAINING_10,Byte 10 of the 80-bit custom training data." newline hexmask.long.byte 0x14 0.--7. 1. "DP_TX_PHY_TRAINING_09,Byte 9 of the 80-bit custom training data." line.long 0x18 "V2A__CORE_VP__REGS_APB_DP_TX_PHY_SR_INTERVAL_p,Custom CP2520 SR interval" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.word 0x18 0.--15. 1. "DP_TX_PHY_SR_INTERVAL,CP2520 test pattern SR Interval definition" line.long 0x1C "V2A__CORE_VP__REGS_APB_DP_TX_PHY_FEC_TEST_p,FEC IP test register. Used for fault injection into the FEC IP to test diagnostic mechanisms." hexmask.long.tbyte 0x1C 10.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x1C 9. "FEC_L23_EXT_DIAG_TEST_EN,Encoder 1 external diagnostic test enable. When asserted a corruption is injected in the external diagnostic reference module which generate an external diagnostic support module fault. To perform external diagnostic test this.." "0,1" newline bitfld.long 0x1C 8. "FEC_L01_EXT_DIAG_TEST_EN,Encoder 0 external diagnostic test enable. When asserted a corruption is injected in the external diagnostic reference module which generate an external diagnostic support module fault. To perform external diagnostic test this.." "0,1" newline bitfld.long 0x1C 7. "FEC_L23_8B10B_TEST,When asserted a corruption is injected at the interface of the internal diagnostic module which generate a fault in the 8b10b check of the FEC IP datapath for lanes 2 and 3. Bit is self cleared." "0,1" newline bitfld.long 0x1C 6. "FEC_L23_PARITY_ENC_TEST,When asserted a corruption is injected at the interface of the internal diagnostic module which generate a fault in the parity enc check of the FEC IP datapath for lanes 2 and 3. Bit is self cleared." "0,1" newline bitfld.long 0x1C 5. "FEC_L23_PARITY_GEN_TEST,When asserted a corruption is injected at the interface of the internal diagnostic module which generate a fault in the parity gen check of the FEC IP datapaths for lanes 2 and 3. Bit is self cleared." "0,1" newline bitfld.long 0x1C 4. "FEC_L23_DATA_BYPASS_TEST,When asserted a corruption is injected at the interface of the internal diagnostic module which generate a fault in the bypass check for of the FEC IP datapathe for lanes 2 and 3. Bit is self cleared." "0,1" newline bitfld.long 0x1C 3. "FEC_L01_8B10B_TEST,When asserted a corruption is injected at the interface of the internal diagnostic module which generate a fault in the 8b10b check of the FEC IP datapath for lanes 0 and 1. Bit is self cleared." "0,1" newline bitfld.long 0x1C 2. "FEC_L01_PARITY_ENC_TEST,When asserted a corruption is injected at the interface of the internal diagnostic module which generate a fault in the parity enc check of the FEC IP datapath for lanes 0 and 1. Bit is self cleared." "0,1" newline bitfld.long 0x1C 1. "FEC_L01_PARITY_GEN_TEST,When asserted a corruption is injected at the interface of the internal diagnostic module which generate a fault in the parity gen check of the FEC IP datapath for lanes 0 and 1. Bit is self cleared." "0,1" newline bitfld.long 0x1C 0. "FEC_L01_DATA_BYPASS_TEST,When asserted a corruption is injected at the interface of the internal diagnostic module which generate a fault in the bypass check for of the FEC IP datapath for lanes 0 and 1. Bit is self cleared." "0,1" rgroup.long 0x2100++0x17 line.long 0x0 "V2A__CORE_VP__REGS_APB_HPD_IRQ_DET_MIN_TIMER_p,HPD min timer for irq. define the minimum pclk cycles that the HPD pulse will be considered as IRQ" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.tbyte 0x0 0.--23. 1. "HPD_IRQ_DET_MIN_TIMER,HPD min timer for interrupt." line.long 0x4 "V2A__CORE_VP__REGS_APB_HPD_IRQ_DET_MAX_TIMER_p,HPD max timer for irq. define the maximum pclk cycles that the HPD pulse will be considered as IRQ" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.tbyte 0x4 0.--23. 1. "HPD_IRQ_DET_MAX_TIMER,HPD max timer" line.long 0x8 "V2A__CORE_VP__REGS_APB_HPD_UNPLGED_DET_MIN_TIMER_p,HPD min timer for HPD detect. define the minimum pclk cycles that the HPD is low" hexmask.long.byte 0x8 24.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.tbyte 0x8 0.--23. 1. "HPD_UNPLGED_DET_MIN_TIMER,HPD unplugged timer" line.long 0xC "V2A__CORE_VP__REGS_APB_HPD_STABLE_TIMER_p,Timer for detecting HPD stable. count in system clock cycles." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.tbyte 0xC 0.--23. 1. "HPD_STABLE_TIMER,HPD stable timer counter setup." line.long 0x10 "V2A__CORE_VP__REGS_APB_HPD_FILTER_TIMER_p,Timer for filtering small pulses on HPD input." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.tbyte 0x10 0.--23. 1. "HPD_FILTER_TIMER,HPD glitch filter counter setup." line.long 0x14 "V2A__CORE_VP__REGS_APB_HPD_DBNC_TIMER_p,HPD debouncer control" hexmask.long.byte 0x14 25.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x14 24. "SEL_HPDTX_DB_22,Debouncer enable 0 - debouncer disabled 1 - debouncer enabled" "0: debouncer disabled 1,?" newline hexmask.long.tbyte 0x14 0.--23. 1. "HPD_DEBOUNCE_TIMER,HPD debounce timer setup." rgroup.long 0x211C++0x7 line.long 0x0 "V2A__CORE_VP__REGS_APB_HPD_EVENT_MASK_p,Mask of HPD interrupt and status" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.byte 0x0 0.--3. 1. "HPD_EVENTS_MASK,HPD mask events" line.long 0x4 "V2A__CORE_VP__REGS_APB_HPD_EVENT_DET_p,HPD interrupt and status" hexmask.long 0x4 5.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline rbitfld.long 0x4 4. "HPD_IN_SYNC,HDP in sync detected" "0,1" newline rbitfld.long 0x4 3. "HPD_RE_PLGED_DET_EVENT,HPD Re-Plugged event detected." "0,1" newline rbitfld.long 0x4 2. "HPD_UNPLUGGED_DET_ACLK,HPD Un-Plugged event detected." "0,1" newline rbitfld.long 0x4 1. "HPD_STABLE,HPD Stable indication" "0,1" newline rbitfld.long 0x4 0. "HPD_IRQ_DET_EVENT,Bit 0 - HPD irq event" "0: HPD irq event,?" rgroup.long 0x2200++0xB line.long 0x0 "V2A__CORE_VP__REGS_APB_DP_FRAMER_GLOBAL_CONFIG_p,Global configuration of the framer module." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x0 7. "WR_VHSYNC_FALL,When set to 1 change the write state machine to sync on falling edge of vsync. Used only for debug purpose." "0,1" newline bitfld.long 0x0 6. "ENC_RST_DIS,Unused. Kept RW for software backward compatibility." "0,1" newline bitfld.long 0x0 5. "NO_VIDEO,No-video mode configuration bit. Relevant only in SST mode. When this bit is set high and framer is enabled then IP operates in no-video mode i.e. BS symbol is generated every 8192 link symbols. In this mode audio data can be transmitted." "0,1" newline bitfld.long 0x0 4. "RESERVED,Reserved. Writes are ignored. 0x0 when read." "0,1" newline bitfld.long 0x0 3. "GLOBAL_EN,Global enable for complete Framer module active high. It is deasserted during configuration phase. Once configuration is finished it is asserted." "0,1" newline bitfld.long 0x0 2. "MST_SST,Mode select: 0 - SST mode 1 - MST mode Static cofiguration bit that must be set before link training." "0: SST mode 1,?" newline bitfld.long 0x0 0.--1. "NUM_LANES,Number of lanes: 0h - One lane [Lane 0 only] 1h - Two lanes [Lanes 0 and 1 only] 2h - Reserved 3h - Four lanes [Lanes 0 1 2 and 3]. This value can only be changed before link training and further it can by modified during link training in.." "0,1,2,3" line.long 0x4 "V2A__CORE_VP__REGS_APB_DP_SW_RESET_p,Unused. Bit [0] kept RW for software backward compatibility." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x4 0. "SW_RST,Unused. Kept RW for software backward compatibility." "0,1" line.long 0x8 "V2A__CORE_VP__REGS_APB_DP_FRAMER_TU_p,Transfer Unit configuration register. Relevant only in SST mode. These register must be set before transitioning to video mode." hexmask.long.byte 0x8 25.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.word 0x8 16.--24. 1. "BS_SR_REPLACE_POSITION,Static debug register. When set to non-zero value the BS counter will be reinitialized to this value that will result in earlier initial SR insertion." newline bitfld.long 0x8 15. "TU_CNT_RST_EN,Unused. Kept RW for software backward compatibility." "0,1" newline hexmask.long.byte 0x8 8.--14. 1. "TU_SIZE,Transfer Unit size. Even values between 32 and 64 are supported." newline bitfld.long 0x8 7. "RESERVED,Reserved. Writes are ignored. 0x0 when read." "0,1" newline bitfld.long 0x8 6. "TU_SST_FAST_DRAIN,Allow the video FIFO to drain faster at end of line. This setting applies only to SST mode." "0,1" newline hexmask.long.byte 0x8 0.--5. 1. "TU_VALID_SYMBOLS,Number of valid symbols per Transfer Unit [TU]. Rounded down to lower integer value [refer to equation in DP specification]. Allowed values are 1 to [TU_size-1]. TU valid smaller than one that would result this register to be set to 0.." rgroup.long 0x2218++0x3 line.long 0x0 "V2A__CORE_VP__REGS_APB_DP_FRAMER_BS_SR_INTRVL_p,SR insertion interval for SST mode." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.word 0x0 0.--9. 1. "BS_SR_INTERVAL,Static debug register. Controls how often BS is replaced by SR in SST mode. Default value of 512 results in every 512th BS being replaced by SR as per DP spec. This register can only be changed for a test purposes in order to speed up.." rgroup.long 0x2258++0xF line.long 0x0 "V2A__CORE_VP__REGS_APB_DP_MTPH_ECF_SLOTS_31_0_p,Bits [31:1] contains which MST timeslot 31-1 should be encrypted." hexmask.long 0x0 0.--31. 1. "TSLOT_ENCRYPT31_0,tslot_encrypt 31 - 0" line.long 0x4 "V2A__CORE_VP__REGS_APB_DP_MTPH_ECF_SLOTS_63_32_p,Contains which MST timeslot 63-32 should be encrypted. This register must be set properly before ECF sequence is triggered. Relevant only in MST mode." hexmask.long 0x4 0.--31. 1. "TSLOT_ENCRYPT63_32,tslot_encrypt 63 - 32" line.long 0x8 "V2A__CORE_VP__REGS_APB_DP_MTPH_LVP_SYMBOL_p,Link Verification Pattern value to be inserted in the MTP header. Relevant only in MST mode." hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.word 0x8 0.--15. 1. "MTPH_LVP_SYM,Symbol value for LINK VERIFICATION PATTERN [LVP]" line.long 0xC "V2A__CORE_VP__REGS_APB_DP_MTPH_CONTROL_p,MTP header control. Relevant only in MST mode." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0xC 2. "MTPH_LVP_EN,Unused. Kept RW for software backward compatibility." "0,1" newline bitfld.long 0xC 1. "MTPH_ACT_EN,MST feature when written with value 1 an ACT sequence will be triggered for slot allocation control. This bit is write only." "0,1" newline bitfld.long 0xC 0. "MTPH_ECF_EN,Unused. Kept RW for software backward compatibility." "0,1" rgroup.long 0x226C++0x3 line.long 0x0 "V2A__CORE_VP__REGS_APB_DP_MTPH_STATUS_p,MTP header status. Relevant only in MST mode." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline rbitfld.long 0x0 0. "MTPH_ACT_STATUS,Status of ACT insertion. Returns 1 until ACT sequence completes." "0,1" rgroup.long 0x2300++0x17 line.long 0x0 "V2A__CORE_VP__REGS_APB_DPTX_LANE_EN_p,DPTX lane enable" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.byte 0x0 0.--3. 1. "DPTX_LANE_ENABLE,DPTX lane enable each lane as a bit when 1 lane is enabled" line.long 0x4 "V2A__CORE_VP__REGS_APB_DPTX_ENHNCD_p,DPTX enhanced mode control register. Relevant only in SST mode. In MST mode it is ignored." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x4 0. "DPTX_ENHANCED_MODE,Enhanced mode control 0x0 - enhanced mode disabled 0x1 - enhanced mode enabled. Enhanced mode should always be enabled if Sink supports it." "0: enhanced mode disabled 0x1,?" line.long 0x8 "V2A__CORE_VP__REGS_APB_DPTX_INT_MASK_p,DPTX Interrupt mask." hexmask.long 0x8 2.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x8 1. "FRAMER_SRC_INT_MASK,Framer mask interrupt 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0x8 0. "HPD_SRC_INT_MASK,HPD mask interrupt 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" line.long 0xC "V2A__CORE_VP__REGS_APB_DPTX_INT_STATUS_p,DPTX interrupt status register. This interrupts are tracked by firmware and not accessible directly to the Host processor." hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline rbitfld.long 0xC 1. "FRAMER_SRC_INT,Framer interrupt - not used." "0,1" newline rbitfld.long 0xC 0. "HPD_SRC_INT,HPD interrupt. Active HIGH. If set further status can be read from HPD_EVENT_DET register. This bit is automatically cleared on read from HPD_EVENT_DET register." "0,1" line.long 0x10 "V2A__CORE_VP__REGS_APB_DPTX_FEC_CTRL_p,DPTX FEC control register." hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x10 1. "CFG_FEC_READY,Equivalent DPCD register FEC_READY enable alternative CP coding. This bit must be set high before link training if FEC is going to be enabled." "0,1" newline bitfld.long 0x10 0. "CFG_FEC_EN,FEC Enable 1-enabled 0-disabled. This bit can be changed on when there is no video transmission [and cfg_fec_ready was set before link training]." "?,1: enabled 0-disabled" line.long 0x14 "V2A__CORE_VP__REGS_APB_DPTX_FEC_STATUS_p,FEC status register." hexmask.long 0x14 5.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.byte 0x14 1.--4. 1. "FEC_FSM_STATUS,FEC FSM status 1-FEC is off 2-generate enable sequence 4-normal work 8-generate disable sequence. Used for debug purposes only." newline rbitfld.long 0x14 0. "FEC_BUSY,FEC Active status. Set in line with first symbol of FEC_DECODE_EN sequence and de-asserts in line with last symbol of FEC_DECODE_DIS sequence." "0,1" rgroup.long 0x2400++0xF line.long 0x0 "V2A__CORE_VP__REGS_APB_HDCP_DP_STATUS_p,HDCP DP status register." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline rbitfld.long 0x0 5. "PSLVERR_HDCP,APB slave error status from HDCP module has been reported when this bit is set to 1." "0,1" newline hexmask.long.byte 0x0 1.--4. 1. "HDCP_DP_ENCRYPTION_ENABLE,Encryption is enabled when this bit is set to 1." newline rbitfld.long 0x0 0. "HDCP_DP_AUTHENTICATED,HDCP 1.3 authentication is enabled when this bit is set to 1." "0,1" line.long 0x4 "V2A__CORE_VP__REGS_APB_HDCP_DP_CONFIG_p,HDCP DP config register." hexmask.long 0x4 7.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x4 6. "SST_HDCP_ENCRYPT_DIS,Disable automatic HDCP encryption in SST mode when cipher is authenticated. This bit can also be set to 1 to disable encryption" "0,1" newline bitfld.long 0x4 5. "HDCP_VBID5_ALIGN_DIS,Debug register no longer used." "0,1" newline bitfld.long 0x4 3.--4. "HDCP_DP_BYPASS,HDCP DP bypass. No-bypass must be set prior link training if HDCP is going to be used. This field must not be changed during operation. 0x0-No bypass; 0x1-Bypass enabled; All other combinations reserved." "0: No bypass; 0x1-Bypass enabled; All other..,?,?,?" newline bitfld.long 0x4 0.--2. "HDCP_DP_VERSION,HDCP version. 0x1-HDCP2.2; 0x2-HDCP1.4; Other-Reserved" "?,1: HDCP2,2: HDCP1,?,?,?,?,?" line.long 0x8 "V2A__CORE_VP__REGS_APB_HDCP_DP_SW_RST_p,HDCP DP software reset register" hexmask.long 0x8 2.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x8 1. "CIPHER_CTRL_SW_RST,Software reset of cipher control logic only." "0,1" newline bitfld.long 0x8 0. "SW_RST,Software reset." "0,1" line.long 0xC "V2A__CORE_VP__REGS_APB_HDCP_DP_FIFO_STATUS_p,HDCP DP FIFO status register." hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline rbitfld.long 0xC 11. "HDCP_DP_SST_1_4_FIFO1_UNDERFLOW,SST HDCP1.4 fifo1 underflow." "0,1" newline rbitfld.long 0xC 10. "HDCP_DP_SST_1_4_FIFO1_OVERFLOW,SST HDCP1.4 fifo1 overflow." "0,1" newline rbitfld.long 0xC 9. "HDCP_DP_SST_1_4_FIFO0_UNDERFLOW,SST HDCP1.4 fifo0 underflow." "0,1" newline rbitfld.long 0xC 8. "HDCP_DP_SST_1_4_FIFO0_OVERFLOW,SST HDCP1.4 fifo0 overflow." "0,1" newline rbitfld.long 0xC 7. "HDCP_DP_SST_2_2_FIFO3_UNDERFLOW,SST HDCP2.2 fifo3 underflow." "0,1" newline rbitfld.long 0xC 6. "HDCP_DP_SST_2_2_FIFO3_OVERFLOW,SST HDCP2.2 fifo3 overflow." "0,1" newline rbitfld.long 0xC 5. "HDCP_DP_SST_2_2_FIFO2_UNDERFLOW,SST HDCP2.2 fifo2 underflow." "0,1" newline rbitfld.long 0xC 4. "HDCP_DP_SST_2_2_FIFO2_OVERFLOW,SST HDCP2.2 fifo2 overflow." "0,1" newline rbitfld.long 0xC 3. "HDCP_DP_SST_2_2_FIFO1_UNDERFLOW,SST HDCP2.2 fifo1 underflow." "0,1" newline rbitfld.long 0xC 2. "HDCP_DP_SST_2_2_FIFO1_OVERFLOW,SST HDCP2.2 fifo1 overflow." "0,1" newline rbitfld.long 0xC 1. "HDCP_DP_SST_2_2_FIFO0_UNDERFLOW,SST HDCP2.2 fifo0 underflow." "0,1" newline rbitfld.long 0xC 0. "HDCP_DP_SST_2_2_FIFO0_OVERFLOW,SST HDCP2.2 fifo0 overflow." "0,1" rgroup.long 0x2800++0x67 line.long 0x0 "V2A__CORE_VP__REGS_APB_DP_AUX_HOST_CONTROL_p,DP AUX control register." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x0 2. "AUX_HOST_TRANSMIT_IMMEDIATE,This bit is used only in DP_OUT mode. If SET a transaction that comes from the adapter will be sent immediately without waiting for send_external_transaction pulse. If CLEAR the MC controls the traffic to/from the adapter." "0,1" newline bitfld.long 0x0 1. "AUX_HOST_PRECHARGE_ENABLE,According to the current standard the tx precharge is done by sending 10 to 16 data_0 on the line before the SYNC. Old standard define the precharge by forcing the AFE to be in precharge mode before transmitting the SYNC." "0,1" newline bitfld.long 0x0 0. "AUX_HOST_ALWAYS_READ,Normally the aux_rx is disabled during transmit. Setting this bit allow loopback operation and all transmit transactions will go to the receiver. Used for debug purpose." "0,1" line.long 0x4 "V2A__CORE_VP__REGS_APB_DP_AUX_INTERRUPT_SOURCE_p,Status of the DP_AUX interrupt sources. These interrupts are tracked by firmware and not accessible directly to the Host processor." hexmask.long.tbyte 0x4 10.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline rbitfld.long 0x4 9. "AUX_MAIN_EXPIRE_TX,Timer expire [external] in DP_OUT. Active HIGH. Clear on read." "0,1" newline rbitfld.long 0x4 8. "AUX_RX_ERROR_CYCLE_TIME,Cycle time error. Asserted if aux_rx_last_cycle is less then aux_host_1m_min or greater then aux_host_1m_max. Active HIGH. Clear on read." "0,1" newline rbitfld.long 0x4 7. "AUX_MAIN_RX_STATUS_CORRUPTED,The received transaction corrupted during the data phase [bad STOP or unaligned STOP]. Active HIGH. Clear on read." "0,1" newline rbitfld.long 0x4 6. "AUX_MAIN_RX_STATUS_LONG_DATA,The received transaction had more than 20 data bytes. Active HIGH. Clear on read." "0,1" newline rbitfld.long 0x4 5. "AUX_MAIN_RX_STATUS_LONG_PREAMBLE,The received transaction had preamble greater than the preamble_max. Active HIGH. Clear on read." "0,1" newline rbitfld.long 0x4 4. "AUX_MAIN_RX_STATUS_SHORT_PREAMBLE,The received transaction had preamble shorter than the preamble_max. Active HIGH. Clear on read." "0,1" newline rbitfld.long 0x4 3. "AUX_MAIN_RX_STATUS_DONE,This module control the packet extraction and packet read from the memory. Active HIGH. Clear on read." "0,1" newline rbitfld.long 0x4 2. "AUX_RX_DATA_TRANSFER_INIT,Rx data transfer may be initiated. Falling edge of the aux_mailbox_empty. Active HIGH. Clear on read." "0,1" newline rbitfld.long 0x4 1. "AUX_TX_DONE,Tx data transfer finished. Active HIGH. Clear on read." "0,1" newline rbitfld.long 0x4 0. "PSLVERR_DPAUX,APB slave error interrupt from DP AUX module. Active HIGH. Clear on read." "0,1" line.long 0x8 "V2A__CORE_VP__REGS_APB_DP_AUX_INTERRUPT_MASK_p,Mask vector of the DP_AUX interrupt sources." hexmask.long.tbyte 0x8 10.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x8 9. "AUX_MAIN_EXPIRE_TX_MASK,aux_main_expire_external mask 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0x8 8. "AUX_RX_ERROR_CYCLE_TIME_MASK,aux_rx_error_cycle_time mask 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0x8 7. "AUX_MAIN_RX_STATUS_CORRUPTED_MASK,aux_main_rx_status_corrupted_mask 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0x8 6. "AUX_MAIN_RX_STATUS_LONG_DATA_MASK,aux_main_rx_status_long_data_mask 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0x8 5. "AUX_MAIN_RX_STATUS_LONG_PREAMBLE_MASK,aux_main_rx_status_long_preamble_mask 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0x8 4. "AUX_MAIN_RX_STATUS_SHORT_PREAMBLE_MASK,aux_main_rx_status_short_preamble_mask 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0x8 3. "AUX_MAIN_RX_STATUS_DONE_MASK,aux_main_rx_status_done_mask 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0x8 2. "AUX_RX_DATA_TRANSFER_INIT_MASK,rx_data_transfer_init mask 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0x8 1. "AUX_TX_DONE_MASK,aux_tx_done_mask 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0x8 0. "PSLVERR_MASK,Mask for pslverr_dpaux interrupt. 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" line.long 0xC "V2A__CORE_VP__REGS_APB_DP_AUX_SWAP_INVERSION_CONTROL_p,Ordering and inversion of transmit/receive on Auxiliary Channel." hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0xC 3. "AUX_HOST_RX_SWAP,Shift right [LSB first] of the income data" "0,1" newline bitfld.long 0xC 2. "AUX_HOST_TX_SWAP,Shift right the output data [LSB first]" "0,1" newline bitfld.long 0xC 1. "AUX_HOST_RX_INVERT,Invert rx input and output data to AUXILIARY CHANNEL" "0,1" newline bitfld.long 0xC 0. "AUX_HOST_TX_INVERT,Invert tx input and output data to AUXILIARY CHANNEL" "0,1" line.long 0x10 "V2A__CORE_VP__REGS_APB_DP_AUX_SEND_NACK_TRANSACTION_p,NACK transaction send" hexmask.long 0x10 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x10 0. "AUX_HOST_SEND_NACK_TRANSACTION,Send nack transaction by AUX_TX. This bit is automatically cleared when operation in completed." "0,1" line.long 0x14 "V2A__CORE_VP__REGS_APB_DP_AUX_CLEAR_RX_p,RX bits clear." hexmask.long 0x14 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x14 0. "AUX_HOST_CLEAR_RX,Clear all rx bits in register 64 65.This command is an indication that the processing of last receive transaction was completed and the AUX_RX can start looking for new receive transaction. This bit is automatically cleared when.." "0,1" line.long 0x18 "V2A__CORE_VP__REGS_APB_DP_AUX_CLEAR_TX_p,TX bits clear." hexmask.long 0x18 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x18 0. "AUX_HOST_CLEAR_TX,Clear all external bits in registers 64 67.This command used in DP_IN mode. It is an indication that the processing of last external transaction was completed and the DP_AUX can start receive new external transaction from the adapter." "0,1" line.long 0x1C "V2A__CORE_VP__REGS_APB_DP_AUX_TIMER_STOP_p,Stop timer operation." hexmask.long 0x1C 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x1C 0. "AUX_HOST_STOP_TIMER,Stop timer operation." "0,1" line.long 0x20 "V2A__CORE_VP__REGS_APB_DP_AUX_TIMER_CLEAR_p,Clear timer operation." hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x20 0. "AUX_HOST_CLEAR_TIMER,Stop timer operation. This bit is automatically cleared when operation in completed." "0,1" line.long 0x24 "V2A__CORE_VP__REGS_APB_DP_AUX_RESET_SW_p,Soft reset of the DP_AUX." hexmask.long 0x24 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x24 0. "AUX_HOST_SW_RESET,Reset all DP_AUX state machines and clear all the status bits. The registers value remains. [S/W reset]. This bit is automatically cleared when operation in completed." "0,1" line.long 0x28 "V2A__CORE_VP__REGS_APB_DP_AUX_DIVIDE_2M_p,SYS_CLK and 2 MHz clock ratio. This register is used to ensure correct AUX channel bitrate for different values of a system clock." hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.byte 0x28 0.--7. 1. "AUX_HOST_DIVIDE_2M,The ratio between sys_clk and 2MHz [[sys_clk frequency/2MHz] - 1] for 25MHz sys_clk the value is 11. This register is used by AUX_TX for generating the AUX_TX clock." line.long 0x2C "V2A__CORE_VP__REGS_APB_DP_AUX_TX_PREACHARGE_LENGTH_p,Pre charge field length." hexmask.long 0x2C 6.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.byte 0x2C 0.--5. 1. "AUX_HOST_PRECHARGE_LENGTH,Length of pre charge field standard definition is 10 to 16 bits/clocks." line.long 0x30 "V2A__CORE_VP__REGS_APB_DP_AUX_FREQUENCY_1M_MAX_p,Maximum legal receiving frequency." hexmask.long.tbyte 0x30 11.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.word 0x30 0.--10. 1. "AUX_HOST_1M_MAX,The maximum legal frequency receiving from the line by the standard is 1.25MHz.The calculation is:[1.25 MHz cycle time]/[sys_clk[-15%] cycle time] 800/46 =17" line.long 0x34 "V2A__CORE_VP__REGS_APB_DP_AUX_FREQUENCY_1M_MIN_p,Minimum legal receiving frequency." hexmask.long.tbyte 0x34 11.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.word 0x34 0.--10. 1. "AUX_HOST_1M_MIN,The minimum legal frequency receiving from the line by the standard is 0.83MHz.The calculation is:[0.83 MHz cycle time]/[sys_clk[+15%] cycle time] 1200/34 =35" line.long 0x38 "V2A__CORE_VP__REGS_APB_DP_AUX_RX_PRE_MIN_p,Minimum received preamble length" hexmask.long 0x38 6.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.byte 0x38 0.--5. 1. "AUX_HOST_PRE_MIN,Valid minimum length of preamble during receive. The standard defines pre_min=26 The value of this register should be greater then the average_number_of_cycles defined in reg 0 [2 4 or 8 ]" line.long 0x3C "V2A__CORE_VP__REGS_APB_DP_AUX_RX_PRE_MAX_p,Maximum received preamble length." hexmask.long 0x3C 6.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.byte 0x3C 0.--5. 1. "AUX_HOST_PRE_MAX,Valid maximum length of preamble during receive. The standard defines pre_max = 32" line.long 0x40 "V2A__CORE_VP__REGS_APB_DP_AUX_TIMER_PRESET_p,DP_AUX_MAIN start value" hexmask.long.word 0x40 16.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.word 0x40 0.--15. 1. "AUX_HOST_TIMER_PRESET,The preset value of the timer in DP_IN mode. With sys_clk= 25MHz the Timer can measure up to ~2500 micro seconds. The defaults value is 300us [0x1D4c]" line.long 0x44 "V2A__CORE_VP__REGS_APB_DP_AUX_NACK_FORMAT_p,Transmit pattern." hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.byte 0x44 0.--7. 1. "AUX_HOST_NACK_FORMAT,Nack or defer pattern for transmit [ 00100000 for defer 00010000 for nack]" line.long 0x48 "V2A__CORE_VP__REGS_APB_DP_AUX_TX_DATA_p,AUX Mailbox write data." hexmask.long.tbyte 0x48 10.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.word 0x48 0.--9. 1. "MAILBOX_TX_DATA,TX data byte written to the mailbox. It is written 20 times and directly transferred into TX mailbox. First 8 bits are regular data. When the first data is transferred into mailbox mailbox_tx_data[8] [frame start] is set to 1. When the.." line.long 0x4C "V2A__CORE_VP__REGS_APB_DP_AUX_RX_DATA_p,AUX Mailbox read data." hexmask.long.tbyte 0x4C 10.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.word 0x4C 0.--9. 1. "MAILBOX_RX_DATA,Read data from the mailbox. Whenever read to this register occurs aux_mailbox_read to RX Mailbox shall be asserted for one clock cycle." line.long 0x50 "V2A__CORE_VP__REGS_APB_DP_AUX_TX_STATUS_p,AUX_TX status." hexmask.long.tbyte 0x50 10.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline rbitfld.long 0x50 9. "MAILBOX_TX_FULL,AUX Mailbox TX full flag." "0,1" newline rbitfld.long 0x50 8. "MAILBOX_TX_EMPTY,AUX Mailbox TX empty flag." "0,1" newline rbitfld.long 0x50 7. "AUX_TX_FRAME_ONGOING,Frame transmission status." "0,1" newline hexmask.long.byte 0x50 0.--6. 1. "AUX_TX_STATE,Aux_tx state machine register." line.long 0x54 "V2A__CORE_VP__REGS_APB_DP_AUX_RX_STATUS_p,AUX_RX status" hexmask.long.byte 0x54 24.--31. 1. "AUX_RX_DATA_STATE,AUX_RX SM state." newline rbitfld.long 0x54 23. "AUX_MAIN_RX_STATUS_LAST_EQUAL,The receive transaction is equal to the previous transaction." "0,1" newline bitfld.long 0x54 20.--22. "RESERVED,Reserved. Writes are ignored. 0x0 when read." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x54 16.--19. 1. "AUX_RX_HHLL_STATE,AUX_RX hhll state machine register." newline bitfld.long 0x54 14.--15. "RESERVED,Reserved. Writes are ignored. 0x0 when read." "0,1,2,3" newline hexmask.long.byte 0x54 8.--13. 1. "AUX_RX_PREAMBLE_STATE,AUX_RX preamble state machine register. Used only for debug." newline rbitfld.long 0x54 7. "MAILBOX_RX_FULL,AUX Mailbox RX full flag." "0,1" newline rbitfld.long 0x54 6. "MAILBOX_RX_EMPTY,AUX Mailbox RX empty flag." "0,1" newline rbitfld.long 0x54 5. "AUX_RX_FRAME_ONGOING,Frame reception status." "0,1" newline hexmask.long.byte 0x54 0.--4. 1. "AUX_RX_MAIN_STATE,AUX_RX main state machine register. Used only for debug purpose." line.long 0x58 "V2A__CORE_VP__REGS_APB_DP_AUX_RX_CYCLE_COUNTER_p,AUX RX counter status." hexmask.long.tbyte 0x58 11.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.word 0x58 0.--10. 1. "AUX_RX_CYCLE_COUNTER,Count system clocks from last change in the auxiliary line input." line.long 0x5C "V2A__CORE_VP__REGS_APB_DP_AUX_MAIN_STATES_p,DP_AUX MAIN State Machines status. Used only for debug purpose." hexmask.long.tbyte 0x5C 14.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.byte 0x5C 10.--13. 1. "AUX_MAIN_EXTERNAL_STATE,AUX_MAIN external state machine register." newline rbitfld.long 0x5C 8.--9. "AUX_MAIN_TIMER_STATE,AUX_MAIN timer state machine." "0,1,2,3" newline bitfld.long 0x5C 7. "RESERVED,Reserved. Writes are ignored. 0x0 when read." "0,1" newline rbitfld.long 0x5C 5.--6. "AUX_MAIN_DP_STATE,AUX_MAIN dp state machine." "0,1,2,3" newline rbitfld.long 0x5C 2.--4. "AUX_MAIN_RX_STATE,AUX_MAIN rx state machine." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x5C 0.--1. "AUX_MAIN_TX_STATE,AUX_MAIN tx state machine." "0,1,2,3" line.long 0x60 "V2A__CORE_VP__REGS_APB_DP_AUX_MAIN_TIMER_p,DP_AUX MAIN timer status." hexmask.long.word 0x60 16.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.word 0x60 0.--15. 1. "AUX_MAIN_TIMER,DP_AUX MAIN timer status." line.long 0x64 "V2A__CORE_VP__REGS_APB_DP_AUX_AFE_OUT_p,Test mode configuration." hexmask.long 0x64 4.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x64 3. "AUX_HOST_AUX_AFE_PRECH,Drive the aux_data_prech output to the AFE when aux_host_afe_if_test_en [bit 0 ] is set." "0,1" newline bitfld.long 0x64 2. "AUX_HOST_AUX_AFE_DATA,Drive the aux_data_out output to the AFE when aux_host_afe_if_test_en [bit 0 ] is set." "0,1" newline bitfld.long 0x64 1. "AUX_HOST_AUX_AFE_CLK,Drive the aux_clk_out output to the AFE when aux_host_afe_if_test_en [bit 0 ] is set." "0,1" newline bitfld.long 0x64 0. "AUX_HOST_AFE_IF_TEST_EN,TESTER mode enable. Give the TESTER direct interface to the AFE_AUX." "0,1" rgroup.long 0x4000++0xF line.long 0x0 "V2A__CORE_VP__REGS_APB_CRYPTO_HDCP_REVISION_p,Contains the revision of the internal HDCP 1.4 and 2.2 module." bitfld.long 0x0 30.--31. "RESERVED,Reserved. Writes are ignored. 0x0 when read." "0,1,2,3" newline hexmask.long.word 0x0 20.--29. 1. "HDCP_CRYP_REV,Revision of the HDCP Crypto block." newline hexmask.long.word 0x0 10.--19. 1. "CRYPTO_HDCP_22_REV,Revision of the HDCP Crypto 2.2 block." newline hexmask.long.word 0x0 0.--9. 1. "CRYPTO_HDCP_14_REV,Revision of the HDCP Crypto 1.4 block." line.long 0x4 "V2A__CORE_VP__REGS_APB_HDCP_CRYPTO_CONFIG_p,Contains global configuration information for the HDCP Crypto module." hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x4 3. "CRYPTO_SW_RST,Software reset for the Crypto module." "0,1" newline bitfld.long 0x4 0.--2. "CRYPTO_HDCP_FUNCTION,Enables a version of the Crypto function: 0x0 - HDCP 1.4 0x1 - HDCP 2.2 Other - Reserved" "0: HDCP 1,1: HDCP 2,?,?,?,?,?,?" line.long 0x8 "V2A__CORE_VP__REGS_APB_CRYPTO_INTERRUPT_SOURCE_p,Contains the status of the HDCP interrupt sources. These interrupts are used by firmware and not directly visible to the Host processor." hexmask.long.tbyte 0x8 11.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline rbitfld.long 0x8 10. "CRYPTO14_PRNM_DONE,LFSR and block output finished calculation. Active HIGH. Clear on read." "0,1" newline rbitfld.long 0x8 9. "CRYPTO14_KM_DONE,Done reading/calculating Km. Active HIGH. Clear on read." "0,1" newline rbitfld.long 0x8 8. "AES_32_DONE,Asserted when the rising edge of the AES-32 done output is detected. Active HIGH. Clear on read." "0,1" newline hexmask.long.byte 0x8 2.--7. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read. Active HIGH. Clear on read." newline rbitfld.long 0x8 1. "APB_SLVERR,APB slave error. Asserted when APB address is out of address range. Active HIGH. Clear on read." "0,1" newline rbitfld.long 0x8 0. "SHA256_NEXT_MESSAGE,Asserted when the rising edge of the SHA256 done output is detected. Active HIGH. Clear on read." "0,1" line.long 0xC "V2A__CORE_VP__REGS_APB_CRYPTO_INTERRUPT_MASK_p,Contains the mask vector of the HDCP interrupt sources." hexmask.long.tbyte 0xC 11.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0xC 10. "CRYPTO14_PRNM_DONE_MASK,Set to 1 to mask the crypto14_prnm_done interrupt. 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0xC 9. "CRYPTO14_KM_DONE_MASK,Set to 1 to mask the crypto14_km_done interrupt. 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0xC 8. "AES_32_DONE_MASK,Set to 1 to mask the AES32_done interrupt. 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline hexmask.long.byte 0xC 2.--7. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0xC 1. "APB_SLVERR_MASK,Set to 1 for the apb_slverr interrupt. 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0xC 0. "SHA256_NEXT_MESSAGE_MASK,Set to 1 to mask the SHA256_done interrupt. 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" rgroup.long 0x4018++0x7 line.long 0x0 "V2A__CORE_VP__REGS_APB_CRYPTO22_CONFIG_p,Contains global configuration information for the HDCP 2.2 Crypto module" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x0 0. "SHA_256_START,Set to 1 for Sha-256 start." "0,1" line.long 0x4 "V2A__CORE_VP__REGS_APB_CRYPTO22_STATUS_p,Crypto 2.2 global status register." hexmask.long.tbyte 0x4 10.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline rbitfld.long 0x4 9. "AES_32_DONE_ST,Asserted when the rising edge of the AES-32 done output is detected." "0,1" newline rbitfld.long 0x4 8. "SHA256_NEXT_MESSAGE_ST,Asserted when the SHA-256 module is ready to receive the next message." "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "AES_32_STATE,AES-32 current state." newline hexmask.long.byte 0x4 0.--3. 1. "SHA_256_STATE,SHA-256 current state." rgroup.long 0x403C++0x3 line.long 0x0 "V2A__CORE_VP__REGS_APB_SHA_256_DATA_IN_p,Holds 32-bit input data word of the SHA-256 module." hexmask.long 0x0 0.--31. 1. "SHA_256_DATA_IN,Holds the 32-bit input data word of the SHA-256 module." rgroup.long 0x4050++0x1F line.long 0x0 "V2A__CORE_VP__REGS_APB_SHA_256_DATA_OUT_0_p,Result of operation SHA-256 - 1' dw" hexmask.long 0x0 0.--31. 1. "SHA_256_DATA_OUT_0,Holds the least significant 32-bits word of the 256-bits output data word of the SHA-256 module." line.long 0x4 "V2A__CORE_VP__REGS_APB_SHA_256_DATA_OUT_1_p,Result of operation SHA-256 - 2' dw" hexmask.long 0x4 0.--31. 1. "SHA_256_DATA_OUT_1,Holds the next significant 32-bits word of the 256-bits output data word of the SHA-256 module." line.long 0x8 "V2A__CORE_VP__REGS_APB_SHA_256_DATA_OUT_2_p,Result of operation SHA-256 - 3' dw" hexmask.long 0x8 0.--31. 1. "SHA_256_DATA_OUT_2,Holds the next significant 32-bits word of the 256-bits output data word of the SHA-256 module" line.long 0xC "V2A__CORE_VP__REGS_APB_SHA_256_DATA_OUT_3_p,Result of operation SHA-256 - 4' dw" hexmask.long 0xC 0.--31. 1. "SHA_256_DATA_OUT_3,Holds the next significant 32-bits word of the 256-bits output data word of the SHA-256 module." line.long 0x10 "V2A__CORE_VP__REGS_APB_SHA_256_DATA_OUT_4_p,Result of operation SHA-256 - 5' dw" hexmask.long 0x10 0.--31. 1. "SHA_256_DATA_OUT_4,Holds the next significant 32-bits word of the 256-bits output data word of the SHA-256 module." line.long 0x14 "V2A__CORE_VP__REGS_APB_SHA_256_DATA_OUT_5_p,Result of operation SHA-256 - 6' dw" hexmask.long 0x14 0.--31. 1. "SHA_256_DATA_OUT_5,Holds the next significant 32-bits word of the 256-bits output data word of the SHA-256 module." line.long 0x18 "V2A__CORE_VP__REGS_APB_SHA_256_DATA_OUT_6_p,Result of operation SHA-256 - 7' dw" hexmask.long 0x18 0.--31. 1. "SHA_256_DATA_OUT_6,Holds the next significant 32-bits word of the 256-bits output data word of the SHA-256 module." line.long 0x1C "V2A__CORE_VP__REGS_APB_SHA_256_DATA_OUT_7_p,Result of operation SHA-256 - 8' dw" hexmask.long 0x1C 0.--31. 1. "SHA_256_DATA_OUT_7,Holds the most significant 32-bits word of the 256-bits output data word of the SHA-256 module." rgroup.long 0x4070++0x13 line.long 0x0 "V2A__CORE_VP__REGS_APB_AES_32_KEY_0_p,Input key word of the AES-32 module - 1' dw" hexmask.long 0x0 0.--31. 1. "AES_32_KEY_0,Holds the least significant 32-bits word of the 128-bits input key word of the AES-32 module." line.long 0x4 "V2A__CORE_VP__REGS_APB_AES_32_KEY_1_p,Input key word of the AES-32 module - 2' dw" hexmask.long 0x4 0.--31. 1. "AES_32_KEY_1,Holds the next significant 32-bits word of the 128-bits input key word of the AES-32 module." line.long 0x8 "V2A__CORE_VP__REGS_APB_AES_32_KEY_2_p,Input key word of the AES-32 module - 3' dw" hexmask.long 0x8 0.--31. 1. "AES_32_KEY_2,Holds the next significant 32-bits word of the 128-bits input key word of the AES-32 module." line.long 0xC "V2A__CORE_VP__REGS_APB_AES_32_KEY_3_p,Input key word of the AES-32 module - 4' dw" hexmask.long 0xC 0.--31. 1. "AES_32_KEY_3,Holds the most significant 32-bits word of the 128-bits input key word of the AES-32 module." line.long 0x10 "V2A__CORE_VP__REGS_APB_AES_32_DATA_IN_p,Input data word to the AES-32 module" hexmask.long 0x10 0.--31. 1. "AES_32_DATA_IN,Holds the input data word to the AES-32 module." rgroup.long 0x4084++0xF line.long 0x0 "V2A__CORE_VP__REGS_APB_AES_32_DATA_OUT_0_p,AES-32 module - 128-bits output data word - 1' dw" hexmask.long 0x0 0.--31. 1. "AES_32_DATA_OUT_0,Holds the least significant 32-bits word of the 128-bits output data word of the AES-32 module." line.long 0x4 "V2A__CORE_VP__REGS_APB_AES_32_DATA_OUT_1_p,AES-32 module - 128-bits output data word - 2' dw" hexmask.long 0x4 0.--31. 1. "AES_32_DATA_OUT_1,Holds the next significant 32-bits word of the 128-bits output data word of the AES-32 module." line.long 0x8 "V2A__CORE_VP__REGS_APB_AES_32_DATA_OUT_2_p,AES-32 module - 128-bits output data word - 3' dw" hexmask.long 0x8 0.--31. 1. "AES_32_DATA_OUT_2,Holds the next significant 32-bits word of the 128-bits output data word of the AES-32 module." line.long 0xC "V2A__CORE_VP__REGS_APB_AES_32_DATA_OUT_3_p,AES-32 module - 128-bits output data word - 4' dw" hexmask.long 0xC 0.--31. 1. "AES_32_DATA_OUT_3,Holds the most significant 32-bits word of the 128-bits output data word of the AES-32 module." rgroup.long 0x40A0++0xB line.long 0x0 "V2A__CORE_VP__REGS_APB_CRYPTO14_CONFIG_p,Contains global configuration information for the HDCP 1.4 Crypto module" hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x0 6. "HDCP_AUTHENTICATED,Authenticated finished." "0,1" newline bitfld.long 0x0 5. "HDCP_REPEATER,Repeater bit : 0: for the receiver 1: for the repeater" "0: for the receiver,1: for the repeater" newline bitfld.long 0x0 4. "START_REKEY,Crypto 1.4 command to start hdcpRekeyCipher" "0,1" newline bitfld.long 0x0 3. "CRYPTO_START_FREE_RUN,Crypto 1.4 command to start free running enable for operation hdcpRngCipher" "0,1" newline bitfld.long 0x0 2. "START_BLOCK_SEQ,Crypto 1.4 command to start LFSR calculation" "0,1" newline bitfld.long 0x0 1. "GET_KSV,Read it's own KSV enable bit.'0' reading not allowed'1' start reading." "0,1" newline bitfld.long 0x0 0. "VALID_KSV,Enable for Km calculation. When high start calculating Km. Indicates a good moment for ri_out sampling." "0,1" line.long 0x4 "V2A__CORE_VP__REGS_APB_CRYPTO14_STATUS_p,Contains global status information for the HDCP 1.4 Crypto module" hexmask.long.word 0x4 21.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline rbitfld.long 0x4 19.--20. "CRYPTO14_STATE,Crypto operation SM state: Possible values: 00- HDCP_RNG_CIPHER 01 - HDCP_BLOCK_CIPHER 10 - HDCP_STREAM_CIPHER 11 - HDCP_REKEY_CIPHER" "0: HDCP_RNG_CIPHER 01,?,?,?" newline rbitfld.long 0x4 18. "SHA1_V_READY,Indication that V value from SHA-1 CRYPTO14_SHA1_V_VALUE_4 is ready." "0,1" newline rbitfld.long 0x4 17. "SHA1_NEXT_MSG,Request for the next message block. When set high CRYPTO14_SHA1_MSG_DATA_0-15 registers shall be written." "0,1" newline hexmask.long.byte 0x4 12.--16. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline rbitfld.long 0x4 9.--11. "SHA1_STATE,Current state for Crypto 1.4 SHA-1 FSM. Used for debug purpose. Possible values: 000 - IDLE 001 - PREPARE 010 - CALCULATE 011 - RESULT 100 - BLOCK_WAIT" "0: IDLE 001,?,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "RESERVED,Reserved. Writes are ignored. 0x0 when read" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 3.--5. "DKS_STATE,Crypto 1.4 DKS current state. Used for debug purpose. Possible values: 000 - HDCP_IDLE_KSV 010 - HDCP_IDLE 100 - HDCP_PRECALC 101 - HDCP_POSTCALC 110 - HDCP_CALC 111 - HDCP_READY" "0: HDCP_IDLE_KSV 010,?,?,?,?,?,?,?" newline rbitfld.long 0x4 2. "PRNM_DONE,LFSR and block output finished calculation." "0,1" newline bitfld.long 0x4 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" "0,1" newline rbitfld.long 0x4 0. "KM_DONE,Done reading/calculating Km. Used as interrupt event." "0,1" line.long 0x8 "V2A__CORE_VP__REGS_APB_CRYPTO14_PRNM_OUT_p,Contains 24-bit pseudo random data" hexmask.long.byte 0x8 24.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.tbyte 0x8 0.--23. 1. "PRNM_OUT,24-bit pseudo-random data." rgroup.long 0x40AC++0x3 line.long 0x0 "V2A__CORE_VP__REGS_APB_CRYPTO14_KM_0_p,Contains the first word of the Km value" hexmask.long 0x0 0.--31. 1. "CRYPTO14_KM_0,Holds the first word of the Km value." rgroup.long 0x40B0++0x13 line.long 0x0 "V2A__CORE_VP__REGS_APB_CRYPTO14_KM_1_p,Contains the most significant 3 bytes of the Km value" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.tbyte 0x0 0.--23. 1. "CRYPTO14_KM_1,Holds the most significant 3 bytes of the Km value." line.long 0x4 "V2A__CORE_VP__REGS_APB_CRYPTO14_AN_0_p,First word of An value generated by hdcpRngCipher operation." hexmask.long 0x4 0.--31. 1. "CRYPTO14_AN_0,Holds the first 4 bytes of the An value." line.long 0x8 "V2A__CORE_VP__REGS_APB_CRYPTO14_AN_1_p,Second word of An value generated by hdcpRngCipher operation" hexmask.long 0x8 0.--31. 1. "CRYPTO14_AN_1,Holds the most significant 4 bytes of the An value." line.long 0xC "V2A__CORE_VP__REGS_APB_CRYPTO14_YOUR_KSV_0_p,First 32 bits of the KSV from the other HDCP device" hexmask.long 0xC 0.--31. 1. "CRYPTO14_YOUR_KSV_0,Holds the first 32 bits of the KSV from the other HDCP device." line.long 0x10 "V2A__CORE_VP__REGS_APB_CRYPTO14_YOUR_KSV_1_p,Last byte of the KSV from other HDCP device" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x10 0.--7. 1. "CRYPTO14_YOUR_KSV_1,Holds the last byte of the KSV from other HDCP device" rgroup.long 0x40C4++0x7 line.long 0x0 "V2A__CORE_VP__REGS_APB_CRYPTO14_MI_0_p,Mi value - 1' dw" hexmask.long 0x0 0.--31. 1. "CRYPTO14_MI_0,Mi value first 32 bits" line.long 0x4 "V2A__CORE_VP__REGS_APB_CRYPTO14_MI_1_p,Mi value - 2' dw" hexmask.long 0x4 0.--31. 1. "CRYPTO14_MI_1,Mi value second 32 bits" rgroup.long 0x40CC++0x3 line.long 0x0 "V2A__CORE_VP__REGS_APB_CRYPTO14_TI_0_p,Ti value" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.word 0x0 0.--15. 1. "CRYPTO14_TI_0,Ti value" rgroup.long 0x40D0++0x3 line.long 0x0 "V2A__CORE_VP__REGS_APB_CRYPTO14_KI_0_p,First 32 bits of the Ki frame key from this HDCP device" hexmask.long 0x0 0.--31. 1. "CRYPTO14_KI_0,Holds the first 32 bits of the Ki frame key from this HDCP device." rgroup.long 0x40D4++0x13 line.long 0x0 "V2A__CORE_VP__REGS_APB_CRYPTO14_KI_1_p,Last 3 bytes of the Ki frame key from this HDCP device." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.tbyte 0x0 0.--23. 1. "CRYPTO14_KI_1,Holds the last 3 bytes of the Ki frame key from this HDCP device." line.long 0x4 "V2A__CORE_VP__REGS_APB_CRYPTO14_BLOCKS_NUM_p,This register defines number of iterations for SHA-1 calculations" hexmask.long 0x4 0.--31. 1. "BLOCKS_NUM,Number of iterations for SHA-1 calculation." line.long 0x8 "V2A__CORE_VP__REGS_APB_CRYPTO14_KEY_MEM_DATA_0_p,Key memory control register. Writing data to this register transfers data to the key RAM. This is input for DKS block. First 32 bits" hexmask.long 0x8 0.--31. 1. "KEY_MEM_DATA_0,Output data from keys RAM. Input for DKS block. First 32 bits." line.long 0xC "V2A__CORE_VP__REGS_APB_CRYPTO14_KEY_MEM_DATA_1_p,Key memory control register. Writing data to this register transfers data to the key RAM. When data is written to this register. pulse key_mem_vld shall be also generated to the core_clk clock domain. as.." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.tbyte 0xC 0.--23. 1. "KEY_MEM_DATA_1,Output data from keys RAM. Input for DKS block. Last 3 bytes." line.long 0x10 "V2A__CORE_VP__REGS_APB_CRYPTO14_SHA1_MSG_DATA_p,SHA1 message control register. 32-bit word for SHA-1 message. Input for SHA-1 block. Writing data to this register transfers data to the SHA-1 block. Write to this register shall be repeated 16 times." hexmask.long 0x10 0.--31. 1. "SHA1_MSG_DATA,32-bit word for SHA-1 message. Input for SHA-1 block." rgroup.long 0x40E8++0x13 line.long 0x0 "V2A__CORE_VP__REGS_APB_CRYPTO14_SHA1_V_VALUE_0_p,SHA1 message status register. First 32-bit word for SHA-1 calculation. Output from SHA-1 block" hexmask.long 0x0 0.--31. 1. "V_VALUE_0,First 32-bit word for SHA-1 calculation value. Output from SHA-1 block." line.long 0x4 "V2A__CORE_VP__REGS_APB_CRYPTO14_SHA1_V_VALUE_1_p,SHA1 message status register. Second 32-bit word for SHA-1 calculation. Output from SHA-1 block" hexmask.long 0x4 0.--31. 1. "V_VALUE_1,Second 32-bit word for SHA-1 calculation value. Output from SHA-1 block." line.long 0x8 "V2A__CORE_VP__REGS_APB_CRYPTO14_SHA1_V_VALUE_2_p,SHA1 message status register. Third 32-bit word for SHA-1 calculation. Output from SHA-1 block" hexmask.long 0x8 0.--31. 1. "V_VALUE_2,Third 32-bit word for SHA-1 calculation value. Output from SHA-1 block." line.long 0xC "V2A__CORE_VP__REGS_APB_CRYPTO14_SHA1_V_VALUE_3_p,SHA1 message status register. Third 32-bit word for SHA-1 calculation. Output from SHA-1 block" hexmask.long 0xC 0.--31. 1. "V_VALUE_3,4th 32-bit word for SHA-1 calculation value. Output from SHA-1 block." line.long 0x10 "V2A__CORE_VP__REGS_APB_CRYPTO14_SHA1_V_VALUE_4_p,SHA1 message status register. 5th 32-bit word for SHA-1 calculation. Output from SHA-1 block" hexmask.long 0x10 0.--31. 1. "V_VALUE_4,5th 32-bit word for SHA-1 calculation value. Output from SHA-1 block." rgroup.long 0x10000++0x3 line.long 0x0 "V2A__CORE_VP__REGS_APB_IRAM_REG_p,Xtensa Instruction RAM address space. Accessed only during boot mode to load firmware." hexmask.long 0x0 0.--31. 1. "IRAM_DATA,IRAM data" rgroup.long 0x20000++0x3 line.long 0x0 "V2A__CORE_VP__REGS_APB_DRAM_REG_p,Xtensa Data RAM address space. Accessed only during boot mode to load firmware." hexmask.long 0x0 0.--31. 1. "DRAM_DATA,DRAM data" rgroup.long 0x30A00++0x13 line.long 0x0 "V2A__CORE_VP__REGS_APB_AUX_CONFIG_p,AUX Configuration Register" bitfld.long 0x0 29.--31. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "TERM_SEG_EN,Enables output resistor segments for termination impedance." newline bitfld.long 0x0 21.--23. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--20. 1. "TX_CURR_CTRL,TX current for output diff pair." newline bitfld.long 0x0 15. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." "0,1" newline bitfld.long 0x0 13.--14. "TX_SLEW_RATE,TX slew rate adjust." "0,1,2,3" newline bitfld.long 0x0 12. "TX_REDUCED_SWING,Control for lowering AUX transmitter swing level." "0,1" newline bitfld.long 0x0 11. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." "0,1" newline bitfld.long 0x0 8.--10. "RX_HYST_LVL,Hysteresis control for AUX receiver front end." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." "0,1,2,3" newline bitfld.long 0x0 4.--5. "RX_DEGLITCH_FILTER,Suppresses high-frequency pulses on AUX receiver output." "0,1,2,3" newline bitfld.long 0x0 3. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." "0,1" newline bitfld.long 0x0 2. "RX_OFFSET_DIS,Disables internal receiver cmn mode offset." "0,1" newline bitfld.long 0x0 0.--1. "BANDGAP_ADJUST,Bandgap startup circuit adjust." "0,1,2,3" line.long 0x4 "V2A__CORE_VP__REGS_APB_AUX_CTRL_p,AUX Control Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." newline bitfld.long 0x4 1. "DECAP_EN,Decap enable. Active HIGH. Asserted as long as DPTX system is enabled." "0,1" newline bitfld.long 0x4 0. "BANDGAP_EN,Bandgap enable. Active HIGH. Asserted when AUX channel needs to be used for request/response traffic - can be disabled after response is received if channel will not be needed for more than 4.5 microseconds." "0,1" line.long 0x8 "V2A__CORE_VP__REGS_APB_AUX_ATBSEL_p,AUX_ATBSEL" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." newline hexmask.long.byte 0x8 0.--7. 1. "AUXIP_ATBSEL_ONEHOT,auxip_atbsel_onehot" line.long 0xC "V2A__CORE_VP__REGS_APB_AUX_TESTMODE_CTL_p,AUX IP test control register." hexmask.long 0xC 5.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." newline bitfld.long 0xC 4. "DECAP_EN_DEL,decap_en_del test value. Reflected at the decap_en_del output when aux_testmode_en=1" "0,1" newline bitfld.long 0xC 3. "AUX_DATA_IN,aux_data_in test value. Reflected at the aux_data_in output when aux_testmode_en=1" "0,1" newline bitfld.long 0xC 2. "TX_EN_CTRL,tx_en test value. Reflected at the tx_en output when aux_testmode_en=1" "0,1" newline bitfld.long 0xC 1. "RX_EN_CTRL,rx_en test value. Reflected at the rx_en output when aux_testmode_en=1" "0,1" newline bitfld.long 0xC 0. "AUX_TESTMODE_EN,AUX test enable. 0 - Test mode disabled 1 - test mode enabled rx_en tx_en aux_data_in and decap_en_del are driven directly from the control rgisters" "0: Test mode disabled 1,?" line.long 0x10 "V2A__CORE_VP__REGS_APB_AUX_TESTMODE_ST_p,AUX IP interface status." hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." newline rbitfld.long 0x10 1. "AUX_DATA_OUT,Raw status of aux_data_out output from AUX IP" "0,1" newline rbitfld.long 0x10 0. "HPD_DATA_OUT,Raw status of HPD output from AUX IP" "0,1" rgroup.long 0x30A20++0x1F line.long 0x0 "V2A__CORE_VP__REGS_APB_PHY_RESET_p,PHY Reset Control Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." newline bitfld.long 0x0 8. "PHY_RESET,0 - reset all PHY logic for the entire PHY with the exception of the PHY APB registers 1 - turn off reset. PHY reset is active LOW." "0: reset all PHY logic for the entire PHY with the..,1: turn off reset" newline bitfld.long 0x0 7. "PMA_TX_ELEC_IDLE_LN_3,PMA Tx electrical idle for line 3. 1 - Tx differential output placed into electrical idle 0 - transmit data." "0: transmit data,1: Tx differential output placed into electrical idle" newline bitfld.long 0x0 6. "PMA_TX_ELEC_IDLE_LN_2,PMA Tx electrical idle for line 2. 1 - Tx differential output placed into electrical idle 0 - transmit data." "0: transmit data,1: Tx differential output placed into electrical idle" newline bitfld.long 0x0 5. "PMA_TX_ELEC_IDLE_LN_1,PMA Tx electrical idle for line 1. 1 - Tx differential output placed into electrical idle 0 - transmit data." "0: transmit data,1: Tx differential output placed into electrical idle" newline bitfld.long 0x0 4. "PMA_TX_ELEC_IDLE_LN_0,PMA Tx electrical idle for line 0. 1 - Tx differential output placed into electrical idle 0 - transmit data." "0: transmit data,1: Tx differential output placed into electrical idle" newline bitfld.long 0x0 3. "PHY_L03_RESET_N,0 - turn on PHY l03 reset with the exception of the PHY APB registers 1 - turn off reset. PHY l03 reset is active LOW." "0: turn on PHY l03 reset with the exception of the..,1: turn off reset" newline bitfld.long 0x0 2. "PHY_L02_RESET_N,0 - turn on PHY l02 reset with the exception of the PHY APB registers 1 - turn off reset. PHY l02 reset is active LOW." "0: turn on PHY l02 reset with the exception of the..,1: turn off reset" newline bitfld.long 0x0 1. "PHY_L01_RESET_N,0 - turn on PHY l01 reset with the exception of the PHY APB registers 1 - turn off reset. PHY l01 reset is active LOW." "0: turn on PHY l01 reset with the exception of the..,1: turn off reset" newline bitfld.long 0x0 0. "PHY_L00_RESET_N,0 - turn on PHY l00 reset with the exception of the PHY APB registers 1 - turn off reset. PHY l00 reset is active LOW." "0: turn on PHY l00 reset with the exception of the..,1: turn off reset" line.long 0x4 "V2A__CORE_VP__REGS_APB_PMA_PLLCLK_EN_p,PHY Link PLL Clock Enable Register" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." newline bitfld.long 0x4 3. "PMA_XCVR_PLLCLK_EN_LN_3,Link PLL clock enable used to cleanly turn off the data rate clock in the PMA for line 3 1 - enable Line 3 PLL clock. 0 - disable PLL clock." "0: disable PLL clock,1: enable Line 3 PLL clock" newline bitfld.long 0x4 2. "PMA_XCVR_PLLCLK_EN_LN_2,Link PLL clock enable used to cleanly turn off the data rate clock in the PMA for line 2 1 - enable Line 2 PLL clock. 0 - disable PLL clock." "0: disable PLL clock,1: enable Line 2 PLL clock" newline bitfld.long 0x4 1. "PMA_XCVR_PLLCLK_EN_LN_1,Link PLL clock enable used to cleanly turn off the data rate clock in the PMA for line 1 1 - enable Line 1 PLL clock. 0 - disable PLL clock." "0: disable PLL clock,1: enable Line 1 PLL clock" newline bitfld.long 0x4 0. "PMA_XCVR_PLLCLK_EN_LN_0,Link PLL clock enable used to cleanly turn off the data rate clock in the PMA for line 0 1 - enable Line 0 PLL clock. 0 - disable PLL clock." "0: disable PLL clock,1: enable Line 0 PLL clock" line.long 0x8 "V2A__CORE_VP__REGS_APB_PMA_PLLCLK_EN_ACK_p,PHY Link PLL Clock Status Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." newline rbitfld.long 0x8 3. "PMA_XCVR_PLLCLK_EN_ACK_LN_3,Link PLL clock enable acknowledgement indicates whether the data rate clock in the PMA for line 3 is running. Active HIGH." "0,1" newline rbitfld.long 0x8 2. "PMA_XCVR_PLLCLK_EN_ACK_LN_2,Link PLL clock enable acknowledgement indicates whether the data rate clock in the PMA for line 2 is running. Active HIGH." "0,1" newline rbitfld.long 0x8 1. "PMA_XCVR_PLLCLK_EN_ACK_LN_1,Link PLL clock enable acknowledgement indicates whether the data rate clock in the PMA for line 1 is running. Active HIGH." "0,1" newline rbitfld.long 0x8 0. "PMA_XCVR_PLLCLK_EN_ACK_LN_0,Link PLL clock enable acknowledgement indicates whether the data rate clock in the PMA for line 0 is running. Active HIGH." "0,1" line.long 0xC "V2A__CORE_VP__REGS_APB_PMA_POWER_STATE_REQ_p,PHY Link Power State Request Register. Please refer to PHY Specification for detailed power state values" bitfld.long 0xC 30.--31. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." "0,1,2,3" newline hexmask.long.byte 0xC 24.--29. 1. "PMA_XCVR_POWER_STATE_REQ_LN_3,Change the link power state. When the link has completed the transition to the requested power state the state will be reflected on pma_xcvr_power_state_ack_ln_3." newline bitfld.long 0xC 22.--23. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." "0,1,2,3" newline hexmask.long.byte 0xC 16.--21. 1. "PMA_XCVR_POWER_STATE_REQ_LN_2,Change the link power state. When the link has completed the transition to the requested power state the state will be reflected on pma_xcvr_power_state_ack_ln_2." newline bitfld.long 0xC 14.--15. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." "0,1,2,3" newline hexmask.long.byte 0xC 8.--13. 1. "PMA_XCVR_POWER_STATE_REQ_LN_1,Change the link power state. When the link has completed the transition to the requested power state the state will be reflected on pma_xcvr_power_state_ack_ln_1." newline bitfld.long 0xC 6.--7. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "PMA_XCVR_POWER_STATE_REQ_LN_0,Change the link power state. When the link has completed the transition to the requested power state the state will be reflected on pma_xcvr_power_state_ack_ln_0." line.long 0x10 "V2A__CORE_VP__REGS_APB_PMA_POWER_STATE_ACK_p,PHY Link Power State Status Register" bitfld.long 0x10 30.--31. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." "0,1,2,3" newline hexmask.long.byte 0x10 24.--29. 1. "PMA_XCVR_POWER_STATE_ACK_LN_3,Link power state acknowledgement this signal provides indication that a power state change request has completed." newline bitfld.long 0x10 22.--23. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." "0,1,2,3" newline hexmask.long.byte 0x10 16.--21. 1. "PMA_XCVR_POWER_STATE_ACK_LN_2,Link power state acknowledgement this signal provides indication that a power state change request has completed." newline bitfld.long 0x10 14.--15. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." "0,1,2,3" newline hexmask.long.byte 0x10 8.--13. 1. "PMA_XCVR_POWER_STATE_ACK_LN_1,Link power state acknowledgement this signal provides indication that a power state change request has completed." newline bitfld.long 0x10 6.--7. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." "0,1,2,3" newline hexmask.long.byte 0x10 0.--5. 1. "PMA_XCVR_POWER_STATE_ACK_LN_0,Link power state acknowledgement this signal provides indication that a power state change request has completed." line.long 0x14 "V2A__CORE_VP__REGS_APB_PMA_CMN_READY_p,PMA Operation Status Register" hexmask.long 0x14 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." newline rbitfld.long 0x14 0. "PMA_CMN_READY,PMA common ready 1 = PMA common is ready for operation. Used as part of Raw SerDes startup sequence and power state changes." "?,1: PMA common is ready for operation" line.long 0x18 "V2A__CORE_VP__REGS_APB_PMA_TX_VMARGIN_p,PMA Tx Voltage Margin Control Register. Please refer to PHY Specification for Voltage Margin settings." hexmask.long.byte 0x18 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." newline bitfld.long 0x18 24.--25. "PMA_TX_VMARGIN_LN_3,Drives PMA input tx_vmargin_ln_3 for the associated lane. Drive with desired initial transit margin upon de-assertion of phy_reset_n." "0,1,2,3" newline hexmask.long.byte 0x18 18.--23. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." newline bitfld.long 0x18 16.--17. "PMA_TX_VMARGIN_LN_2,Drives PMA input tx_vmargin_ln_2 for the associated lane. Drive with desired initial transit margin upon de-assertion of phy_reset_n." "0,1,2,3" newline hexmask.long.byte 0x18 10.--15. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." newline bitfld.long 0x18 8.--9. "PMA_TX_VMARGIN_LN_1,Drives PMA input tx_vmargin_ln_1 for the associated lane. Drive with desired initial transit margin upon de-assertion of phy_reset_n." "0,1,2,3" newline hexmask.long.byte 0x18 2.--7. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." newline bitfld.long 0x18 0.--1. "PMA_TX_VMARGIN_LN_0,Drives PMA input tx_vmargin_ln_0 for the associated lane. Drive with desired initial transit margin upon de-assertion of phy_reset_n." "0,1,2,3" line.long 0x1C "V2A__CORE_VP__REGS_APB_PMA_TX_DEEMPH_p,PMA Tx Deemphasis Level Control Register. Please refer to PHY Specification for Deemphasis Level settings." hexmask.long.byte 0x1C 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." newline bitfld.long 0x1C 24.--25. "PMA_TX_DEEMPHASIS_LN_3,Drives PMA input tx_deemphasis_ln_3 for the associated lane. Drives with desired initial deemphasis setting upon de-assertion of phy_reset_n." "0,1,2,3" newline hexmask.long.byte 0x1C 18.--23. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." newline bitfld.long 0x1C 16.--17. "PMA_TX_DEEMPHASIS_LN_2,Drives PMA input tx_deemphasis_ln_2 for the associated lane. Drives with desired initial deemphasis setting upon de-assertion of phy_reset_n." "0,1,2,3" newline hexmask.long.byte 0x1C 10.--15. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." newline bitfld.long 0x1C 8.--9. "PMA_TX_DEEMPHASIS_LN_1,Drives PMA input tx_deemphasis_ln_1 for the associated lane. Drives with desired initial deemphasis setting upon de-assertion of phy_reset_n." "0,1,2,3" newline hexmask.long.byte 0x1C 2.--7. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read. ignored on write." newline bitfld.long 0x1C 0.--1. "PMA_TX_DEEMPHASIS_LN_0,Drives PMA input tx_deemphasis_ln_0 for the associated lane. Drives with desired initial deemphasis setting upon de-assertion of phy_reset_n." "0,1,2,3" rgroup.long 0x30A60++0x3 line.long 0x0 "V2A__CORE_VP__REGS_APB_asf_ips_ctrl,ASF control register. imlemented only when ASF support is enabled in IP configuration" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x0 0. "IF_ADDR_PARCHECK_EN,When set enables parity check at APB/SAPB address bus. This bit should be enabled during normal operation but disabled in test mode when internal parity checkers are verified" "0,1" rgroup.long 0x30B00++0x13 line.long 0x0 "V2A__CORE_VP__REGS_APB_asf_int_status,ASF Interrupt Status Register. This register indicates the source of ASF interrupts. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register the asf_fatal or.." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x0 6. "ASF_INTEGRITY_ERR,Integrity error interrupt 1 is active 0 is not active" "0,1" newline bitfld.long 0x0 5. "ASF_PROTOCOL_ERR,Protocol error interrupt 1 is active 0 is not active" "0,1" newline bitfld.long 0x0 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt 1 is active 0 is not active" "0,1" newline bitfld.long 0x0 3. "ASF_CSR_ERR,Configuration and status registers error interrupt 1 is active 0 is not active" "0,1" newline bitfld.long 0x0 2. "ASF_DAP_ERR,Data and address paths parity error interrupt 1 is active 0 is not active" "0,1" newline bitfld.long 0x0 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt 1 is active 0 is not active" "0,1" newline bitfld.long 0x0 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt 1 is active 0 is not active" "0,1" line.long 0x4 "V2A__CORE_VP__REGS_APB_asf_int_raw_status,ASF Interrupt Raw Status Register. A bit set in this raw register indicates a source of ASF fault in the corresponding feature. Writing to either raw or masked status registers. clear both registers. For test.." hexmask.long 0x4 7.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x4 6. "SF_INTEGRITY_ERR,Integrity error interrupt 1 is active 0 is not active" "0,1" newline bitfld.long 0x4 5. "ASF_PROTOCOL_ERR,Protocol error interrupt 1 is active 0 is not active" "0,1" newline bitfld.long 0x4 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt 1 is active 0 is not active" "0,1" newline bitfld.long 0x4 3. "ASF_CSR_ERR,Configuration and status registers error interrupt 1 is active 0 is not active" "0,1" newline bitfld.long 0x4 2. "ASF_DAP_ERR,Data and address paths parity error interrupt 1 is active 0 is not active" "0,1" newline bitfld.long 0x4 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt 1 is active 0 is not active" "0,1" newline bitfld.long 0x4 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt 1 is active 0 is not active" "0,1" line.long 0x8 "V2A__CORE_VP__REGS_APB_asf_int_mask,The ASF interrupt mask register indicating which interrupt bits in the ASF interrupt status register are masked. All bits are set at reset. Clear the individual bit to enable the corresponding interrupt." hexmask.long 0x8 7.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x8 6. "ASF_INTEGRITY_ERR_MASK,Mask bit for Integrity error interrupt 0 is active 1 is not active. Interrupt from source which mask is 0 is permitted otherwise interrupt is not permitted" "0,1" newline bitfld.long 0x8 5. "ASF_PROTOCOL_ERR_MASK,Mask bit for Protocol error interrupt 0 is active 1 is not active.Interrupt from source which mask is 0 is permitted otherwise interrupt is not permitted" "0,1" newline bitfld.long 0x8 4. "ASF_TRANS_TO_ERR_MASK,Mask bit for Transaction timeouts error interrupt 0 is active 1 is not active. Interrupt from source which mask is 0 is permitted otherwise interrupt is not permitted" "0,1" newline bitfld.long 0x8 3. "ASF_CSR_ERR_MASK,Mask bit for Configuration and status registers error interrupt 0 is active 1 is not active. Interrupt from source which mask is 0 is permitted otherwise interrupt is not permitted" "0,1" newline bitfld.long 0x8 2. "ASF_DAP_ERR_MASK,Mask bit for Data and address paths parity error interrupt 0 is active 1 is not active. Interrupt from source which mask is 0 is permitted otherwise interrupt is not permitted" "0,1" newline bitfld.long 0x8 1. "ASF_SRAM_UNCORR_ERR_MASK,Mask bit for SRAM uncorrectable error interrupt 0 is active 1 is not active. Interrupt from source which mask is 0 is permitted otherwise interrupt is not permitted" "0,1" newline bitfld.long 0x8 0. "ASF_SRAM_CORR_ERR_MASK,Mask bit for SRAM correctable error interrupt 0 is active 1 is not active. Interrupt from source which mask is 0 is permitted otherwise interrupt is not permitted" "0,1" line.long 0xC "V2A__CORE_VP__REGS_APB_asf_int_test,The ASF interrupt test register emulate hardware even. Write one to individual bit to trigger single event in (masked and raw) status registers according to mask and will generate interrupt accordingly." hexmask.long 0xC 7.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0xC 6. "ASF_INTEGRITY_ERR_TEST,Test bit for Integrity error interrupt 1 is active 0 is not active" "0,1" newline bitfld.long 0xC 5. "ASF_PROTOCOL_ERR_TEST,Test bit for Protocol error interrupt 1 is active 0 is not active" "0,1" newline bitfld.long 0xC 4. "ASF_TRANS_TO_ERR_TEST,Test bit for Transaction timeouts error interrupt 1 is active 0 is not active" "0,1" newline bitfld.long 0xC 3. "ASF_CSR_ERR_TEST,Test bit for Configuration and status registers error interrupt 1 is active 0 is not active" "0,1" newline bitfld.long 0xC 2. "ASF_DAP_ERR_TEST,Test bit for Data and address paths parity error interrupt 1 is active 0 is not active" "0,1" newline bitfld.long 0xC 1. "ASF_SRAM_UNCORR_ERR_TEST,Test bit for SRAM uncorrectable error interrupt 1 is active 0 is not active" "0,1" newline bitfld.long 0xC 0. "ASF_SRAM_CORR_ERR_TEST,Test bit for SRAM correctable error interrupt 1 is active 0 is not active" "0,1" line.long 0x10 "V2A__CORE_VP__REGS_APB_asf_fatal_nonfatal_select,The fatal or non-fatal interrupt register selects whether a fatal (asf_int_fatal) or non-fatal (asf_int_nonfatal) interrupt is triggered. If the bit of the event will be set to one then fatal interrupt.." hexmask.long 0x10 7.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x10 6. "ASF_INTEGRITY_ERR,Enable Integrity error interrupt as fatal 1 is fatal interrupt 0 is non-fatal" "0,1" newline bitfld.long 0x10 5. "ASF_PROTOCOL_ERR,Enable Protocol error interrupt as fatal 1 is fatal interrupt 0 is non-fatal" "0,1" newline bitfld.long 0x10 4. "ASF_TRANS_TO_ERR,Enable Transaction timeouts error interrupt as fatal 1 is fatal interrupt 0 is non-fatal" "0,1" newline bitfld.long 0x10 3. "ASF_CSR_ERR,Enable Configuration and status registers error interrupt as fatal 1 is fatal interrupt 0 is non-fatal" "0,1" newline bitfld.long 0x10 2. "ASF_DAP_ERR,Enable Data and address paths parity error interrupt as fatal 1 is fatal interrupt 0 is non-fatal" "0,1" newline bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR,Enable SRAM uncorrectable error interrupt as fatal 1 is fatal interrupt 0 is non-fatal" "0,1" newline bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR,Enable SRAM correctable error interrupt as fatal 1 is fatal interrupt 0 is non-fatal" "0,1" rgroup.long 0x30B20++0x7 line.long 0x0 "V2A__CORE_VP__REGS_APB_asf_sram_corr_fault_status,Status register for SRAM correctable fault. These fields are updated whenever asf_sram_corr_fault input is active." hexmask.long.byte 0x0 24.--31. 1. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault" newline hexmask.long.tbyte 0x0 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault" line.long 0x4 "V2A__CORE_VP__REGS_APB_asf_sram_uncorr_fault_status,Status register for SRAM uncorrectable fault. These fields are updated whenever asf_sram_uncorr_fault input is active." hexmask.long.byte 0x4 24.--31. 1. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault" newline hexmask.long.tbyte 0x4 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault" rgroup.long 0x30B28++0x3 line.long 0x0 "V2A__CORE_VP__REGS_APB_asf_sram_fault_status,Statistics register for SRAM faults. Note that this register clears when software writes to any field." hexmask.long.word 0x0 16.--31. 1. "ASF_SRAM_FAULT_UNCORR_STATS,Count of number of uncorrectable errors if implemented. Count value will saturate at 0xffff" newline hexmask.long.word 0x0 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS,Count of number of correctable errors if implemented. Count value will saturate at 0xffff" rgroup.long 0x30B30++0xB line.long 0x0 "V2A__CORE_VP__REGS_APB_asf_trans_to_ctrl,Control register to configure the ASF transaction timeout monitors." bitfld.long 0x0 31. "ASF_TRANS_TO_EN,Enable transaction timeout monitoring 1 is active 0 is not active" "0,1" newline hexmask.long.word 0x0 16.--30. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.word 0x0 0.--15. 1. "ASF_TRANS_TO_CTRL,Timer value to use for transaction timeout monitor" line.long 0x4 "V2A__CORE_VP__REGS_APB_asf_trans_to_fault_mask,Control register to mask out ASF transaction timeout faults from triggering interrupts. On reset. all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt source. The.." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x4 2. "ASF_TRANS_TO_FAULT_2_MASK,Mask bit for SAPB interface for transaction timeout fault 0 is active 1 is not active.Interrupt from source which mask is 0 is permitted otherwise interrupt is not permitted" "0,1" newline bitfld.long 0x4 1. "ASF_TRANS_TO_FAULT_1_MASK,Mask bit for APB interface for transaction timeout fault 0 is active 1 is not active.Interrupt from source which mask is 0 is permitted otherwise interrupt is not permitted" "0,1" newline bitfld.long 0x4 0. "ASF_TRANS_TO_FAULT_0_MASK,Mask bit for Xtensa watchdog error for transaction timeout fault 0 is active 1 is not active.Interrupt from source which mask is 0 is permitted otherwise interrupt is not permitted" "0,1" line.long 0x8 "V2A__CORE_VP__REGS_APB_asf_trans_to_fault_status,Status register for transaction timeouts fault. If a fault occurs the revelant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x8 2. "ASF_TRANS_TO_FAULT_2_STATUS,Status bits for SAPB interface for transaction timeout fault 1 is active 0 is not active" "0,1" newline bitfld.long 0x8 1. "ASF_TRANS_TO_FAULT_1_STATUS,Status bits for APB interface for transaction timeout fault 1 is active 0 is not active" "0,1" newline bitfld.long 0x8 0. "ASF_TRANS_TO_FAULT_0_STATUS,Status bits for Xtensa watchdog error for transaction timeout fault 1 is active 0 is not active" "0,1" rgroup.long 0x30B40++0x7 line.long 0x0 "V2A__CORE_VP__REGS_APB_asf_protocol_fault_mask,Control register to mask out ASF Protocol faults from triggering interrupts. On reset. all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt source. The width of this.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x0 3. "ASF_PROTOCOL_FAULT_3_MASK,Mask bit for FEC FSM fault. When 0 interrupt is enabled." "0,1" newline bitfld.long 0x0 2. "ASF_PROTOCOL_FAULT_2_MASK,Mask bit for 8b10b Encoding fault from FEC module. When 0 interrupt is enabled." "0,1" newline bitfld.long 0x0 1. "ASF_PROTOCOL_FAULT_1_MASK,Mask bit for Party Encoding fault from FEC module. When 0 interrupt is enabled." "0,1" newline bitfld.long 0x0 0. "ASF_PROTOCOL_FAULT_0_MASK,Mask bit for Parity Generation fault from FEC module. When 0 interrupt is enabled." "0,1" line.long 0x4 "V2A__CORE_VP__REGS_APB_asf_protocol_fault_status,Status register for protocol faults. If a fault occurs the revelant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x4 3. "ASF_PROTOCOL_FAULT_3_STATUS,FEC symbol injection fault. Active HIGH. Asserten when FEC FSM is in unexpected state." "0,1" newline bitfld.long 0x4 2. "ASF_PROTOCOL_FAULT_2_STATUS,8b10b Encoding fault in FEC module. Active HIGH. Asserted when fault in 8b10b encoding is detected." "0,1" newline bitfld.long 0x4 1. "ASF_PROTOCOL_FAULT_1_STATUS,Party Encoding fault in FEC module. Active HIGH. Asserted when fault in RS parity encoding is detected." "0,1" newline bitfld.long 0x4 0. "ASF_PROTOCOL_FAULT_0_STATUS,Parity Generation fault in FEC module. Active HIGH. Asserted when fault in RS parity generation is detected." "0,1" rgroup.long 0x30C00++0x3 line.long 0x0 "V2A__CORE_VP__REGS_APB_COM_MAIN_CONF_p,Encoder common configuration values" hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x0 6. "AUTO_REGS_DB_UPDATE,Active-High to enable auto update double buffer regs on vsync falling edge. Only available when input_mode=1 [DPI mode]" "0,1" newline bitfld.long 0x0 5. "MULTIPLEX_MODE_EOC_ENABLE,When split_panel and multiplex_mode are set indicates that multiplexer output separated chunks [inserts zeros on partial words at each end of chunk] and signal end of chunks. Active high" "0,1" newline bitfld.long 0x0 4. "INPUT_MODE,Video input interface mode: 0: Native 1: DPI. Input mode set to DPI automatically enable the internal Auto Start Of Frame" "0: Native,1: DPI" newline bitfld.long 0x0 3. "REGS_DE_RASTER_ENABLE,Indicates if the De-Rasterization Buffer is used or bypassed: '1' Active '0' Bypassed" "0,1" newline bitfld.long 0x0 2. "REGS_MULTIPLEX_SEL_OUT,When split_panel and multiplex_mode are set indicates to which output the multiplexed stream is sent: '0': enc0_data_out '1': enc1_data_out" "0,1" newline bitfld.long 0x0 1. "REGS_MULTIPLEX_MODE,Active-High indicates that both encoders are used to produce a multiplex stream on a single Transport link. When set split_panel must also be set." "0,1" newline bitfld.long 0x0 0. "REGS_SPLIT_PANEL,Active-High indicates that both encoders are used in parallel for one video stream [L and R split]. When set the effective width of each encoder is halved [as each encoder is operating on half of the encx_picture_width]. In addition .." "0,1" rgroup.long 0x30D20++0x6B line.long 0x0 "V2A__CORE_VP__REGS_APB_ENC0_MAIN_CONF_p,Encoder Main Configuration values" hexmask.long.byte 0x0 24.--31. 1. "INITIAL_LINES,Number of lines to wait before initiating transport in Command Mode." newline bitfld.long 0x0 21.--23. "RESERVED,Reserved. Writes are ignored. 0x0 when read" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ICH_RST_EOL,Forces the ICH to reset at EOL [when not in split mode]." "0,1" newline bitfld.long 0x0 19. "VIDEO_MODE,MIPI Video/Command mode: '0' Command mode '1' Video mode" "0,1" newline bitfld.long 0x0 18. "BLOCK_PRED_ENABLE,Active-High input Block Prediction Enable" "0,1" newline hexmask.long.word 0x0 8.--17. 1. "BITS_PER_PIXEL,Target bits per pixel. The value is in 6.4 format [4 LSBs for fractional part they should be 0000]" newline hexmask.long.byte 0x0 4.--7. 1. "LINEBUF_DEPTH,Depth of the line buffer used by the decoder [i.e. the number of bits stored for each component of the pixels on the previous line]" newline bitfld.long 0x0 3. "ENABLE_422,Active-High input to indicate the data_in pixels are 4:2:2 sub-sampled. This input is valid only when convert_rgb is low. NOT SUPPORTED MUST BE SET TO '0'" "0,1" newline bitfld.long 0x0 2. "CONVERT_RGB,Active-High input to indicate the data_in pixels are RGB. When set to low input it is YUV and does not require conversion." "0,1" newline bitfld.long 0x0 0.--1. "INPUT_BPC,Indicates the current input pixel stream bits per component: 00: input is 8 bits/component 01: input is 10 bits/component" "0: input is 8 bits/component,1: input is 10 bits/component,?,?" line.long 0x4 "V2A__CORE_VP__REGS_APB_ENC0_PICTURE_SIZE_p,Encoder Picture configuration" hexmask.long.word 0x4 16.--31. 1. "PICTURE_HEIGHT,Picture height" newline hexmask.long.word 0x4 0.--15. 1. "PICTURE_WIDTH,Picture width" line.long 0x8 "V2A__CORE_VP__REGS_APB_ENC0_SLICE_SIZE_p,Encoder Slice(s) configuration" hexmask.long.word 0x8 16.--31. 1. "SLICE_HEIGHT,Slice height" newline hexmask.long.word 0x8 0.--15. 1. "SLICE_WIDTH,Slice width" line.long 0xC "V2A__CORE_VP__REGS_APB_ENC0_MISC_SIZE_p,Encoder Group. Output Buffer(s). and Transport Chunk Size" hexmask.long.word 0xC 16.--31. 1. "CHUNK_SIZE,Chunk size in bytes" newline hexmask.long.word 0xC 2.--15. 1. "OB_MAX_ADDR,Output Buffer[s] max pointer address[es]" newline bitfld.long 0xC 0.--1. "SLICE_LAST_GROUP_SIZE,Size of last group of the slice line [0-based]: 0 = 1 pixel 1 = 2 pixels 2 = 3 pixels [slice_width + 2] % 3" "0: based]:,?,?,?" line.long 0x10 "V2A__CORE_VP__REGS_APB_ENC0_HRD_DELAYS_p,Hypothetical Reference Decoder delays" hexmask.long.word 0x10 16.--31. 1. "INITIAL_DEC_DELAY,Initial Decoder delay" newline hexmask.long.byte 0x10 10.--15. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.word 0x10 0.--9. 1. "INITIAL_XMIT_DELAY,Initial Decoder Transmit delay" line.long 0x14 "V2A__CORE_VP__REGS_APB_ENC0_RC_SCALE_p,RC Calculate Buffer Fullness and Offset. Scale value" hexmask.long 0x14 6.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x14 0.--5. 1. "INITIAL_SCALE_VALUE,Three fractional bits" line.long 0x18 "V2A__CORE_VP__REGS_APB_ENC0_RC_SCALE_INC_DEC_p,RC Calculate Buffer Fullness and Offset. Increment and Decrement Scale values" hexmask.long.byte 0x18 28.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.word 0x18 16.--27. 1. "SCALE_DECREMENT_INTERVAL,RC scale decrement value" newline hexmask.long.word 0x18 0.--15. 1. "SCALE_INCREMENT_INTERVAL,RC scale increment value" line.long 0x1C "V2A__CORE_VP__REGS_APB_ENC0_RC_OFFSETS_1_p,RC Calculate Buffer Fullness and Offset. Various Offset control values 1" hexmask.long 0x1C 5.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x1C 0.--4. 1. "FIRST_LINE_BPG_OFFSET,First Line" line.long 0x20 "V2A__CORE_VP__REGS_APB_ENC0_RC_OFFSETS_2_p,RC Calculate Buffer Fullness and Offset. Various Offset control values 2" hexmask.long.word 0x20 16.--31. 1. "SLICE_BPG_OFFSET,Extra budget per group [11 fractional bits]" newline hexmask.long.word 0x20 0.--15. 1. "NFL_BPG_OFFSET,Non First Line [11 fractional bits]" line.long 0x24 "V2A__CORE_VP__REGS_APB_ENC0_RC_OFFSETS_3_p,RC Calculate Buffer Fullness and Offset. Various Offset control values 3" hexmask.long.word 0x24 16.--31. 1. "FINAL_OFFSET,Final Offset" newline hexmask.long.word 0x24 0.--15. 1. "INITIAL_OFFSET,Initial Offset" line.long 0x28 "V2A__CORE_VP__REGS_APB_ENC0_FLATNESS_DETECTION_p,Flatness Signaling QP Override thresholds" hexmask.long.word 0x28 18.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x28 10.--17. 1. "FLATNESS_DET_THRESH,Flatness Detection Threshold as defined in PPS table of the DSC specification" newline hexmask.long.byte 0x28 5.--9. 1. "FLATNESS_MAX_QP,Maximum threshold" newline hexmask.long.byte 0x28 0.--4. 1. "FLATNESS_MIN_QP,Minimum threshold" line.long 0x2C "V2A__CORE_VP__REGS_APB_ENC0_RC_MODEL_SIZE_p,RC Model Size" hexmask.long.word 0x2C 16.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.word 0x2C 0.--15. 1. "RC_MODEL_SIZE,RC Model Size" line.long 0x30 "V2A__CORE_VP__REGS_APB_ENC0_RC_CONFIG_p,RC Model Various Config" hexmask.long.byte 0x30 28.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x30 24.--27. 1. "RC_TGT_OFFSET_LO,RC Target offset low" newline hexmask.long.byte 0x30 20.--23. 1. "RC_TGT_OFFSET_HI,RC Target offset high" newline bitfld.long 0x30 18.--19. "RESERVED,Reserved. Writes are ignored. 0x0 when read" "0,1,2,3" newline hexmask.long.byte 0x30 13.--17. 1. "RC_QUANT_INCR_LIMIT1,RC quantization increment limit 1" newline hexmask.long.byte 0x30 8.--12. 1. "RC_QUANT_INCR_LIMIT0,RC quantization increment limit 0" newline hexmask.long.byte 0x30 4.--7. 1. "RESERVED,RC Edge factor [1 fractional bit]" newline hexmask.long.byte 0x30 0.--3. 1. "RC_EDGE_FACTOR,Reserved. Writes are ignored. 0x0 when read" line.long 0x34 "V2A__CORE_VP__REGS_APB_ENC0_RC_BUF_THRESH_0_p,RC Model Buffer Thresholds 0" hexmask.long.byte 0x34 24.--31. 1. "RC_BUF_THRESH_3,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" newline hexmask.long.byte 0x34 16.--23. 1. "RC_BUF_THRESH_2,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" newline hexmask.long.byte 0x34 8.--15. 1. "RC_BUF_THRESH_1,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" newline hexmask.long.byte 0x34 0.--7. 1. "RC_BUF_THRESH_0,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" line.long 0x38 "V2A__CORE_VP__REGS_APB_ENC0_RC_BUF_THRESH_1_p,RC Model Buffer Thresholds 1" hexmask.long.byte 0x38 24.--31. 1. "RC_BUF_THRESH_7,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" newline hexmask.long.byte 0x38 16.--23. 1. "RC_BUF_THRESH_6,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" newline hexmask.long.byte 0x38 8.--15. 1. "RC_BUF_THRESH_5,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" newline hexmask.long.byte 0x38 0.--7. 1. "RC_BUF_THRESH_4,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" line.long 0x3C "V2A__CORE_VP__REGS_APB_ENC0_RC_BUF_THRESH_2_p,RC Model Buffer Thresholds 2" hexmask.long.byte 0x3C 24.--31. 1. "RC_BUF_THRESH_11,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" newline hexmask.long.byte 0x3C 16.--23. 1. "RC_BUF_THRESH_10,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" newline hexmask.long.byte 0x3C 8.--15. 1. "RC_BUF_THRESH_9,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" newline hexmask.long.byte 0x3C 0.--7. 1. "RC_BUF_THRESH_8,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" line.long 0x40 "V2A__CORE_VP__REGS_APB_ENC0_RC_BUF_THRESH_3_p,RC Model Buffer Thresholds 3" hexmask.long.word 0x40 16.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x40 8.--15. 1. "RC_BUF_THRESH_13,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" newline hexmask.long.byte 0x40 0.--7. 1. "RC_BUF_THRESH_12,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" line.long 0x44 "V2A__CORE_VP__REGS_APB_ENC0_RC_MIN_QP_0_p,RC Min QP 0" hexmask.long.byte 0x44 25.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x44 20.--24. 1. "RANGE_MIN_QP_4,As per DSC specification" newline hexmask.long.byte 0x44 15.--19. 1. "RANGE_MIN_QP_3,As per DSC specification" newline hexmask.long.byte 0x44 10.--14. 1. "RANGE_MIN_QP_2,As per DSC specification" newline hexmask.long.byte 0x44 5.--9. 1. "RANGE_MIN_QP_1,As per DSC specification" newline hexmask.long.byte 0x44 0.--4. 1. "RANGE_MIN_QP_0,As per DSC specification" line.long 0x48 "V2A__CORE_VP__REGS_APB_ENC0_RC_MIN_QP_1_p,RC Min QP 1" hexmask.long.byte 0x48 25.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x48 20.--24. 1. "RANGE_MIN_QP_9,As per DSC specification" newline hexmask.long.byte 0x48 15.--19. 1. "RANGE_MIN_QP_8,As per DSC specification" newline hexmask.long.byte 0x48 10.--14. 1. "RANGE_MIN_QP_7,As per DSC specification" newline hexmask.long.byte 0x48 5.--9. 1. "RANGE_MIN_QP_6,As per DSC specification" newline hexmask.long.byte 0x48 0.--4. 1. "RANGE_MIN_QP_5,As per DSC specification" line.long 0x4C "V2A__CORE_VP__REGS_APB_ENC0_RC_MIN_QP_2_p,RC Min QP 2" hexmask.long.byte 0x4C 25.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x4C 20.--24. 1. "RANGE_MIN_QP_14,As per DSC specification" newline hexmask.long.byte 0x4C 15.--19. 1. "RANGE_MIN_QP_13,As per DSC specification" newline hexmask.long.byte 0x4C 10.--14. 1. "RANGE_MIN_QP_12,As per DSC specification" newline hexmask.long.byte 0x4C 5.--9. 1. "RANGE_MIN_QP_11,As per DSC specification" newline hexmask.long.byte 0x4C 0.--4. 1. "RANGE_MIN_QP_10,As per DSC specification" line.long 0x50 "V2A__CORE_VP__REGS_APB_ENC0_RC_MAX_QP_0_p,RC Max QP 0" hexmask.long.byte 0x50 25.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x50 20.--24. 1. "RANGE_MAX_QP_4,As per DSC specification" newline hexmask.long.byte 0x50 15.--19. 1. "RANGE_MAX_QP_3,As per DSC specification" newline hexmask.long.byte 0x50 10.--14. 1. "RANGE_MAX_QP_2,As per DSC specification" newline hexmask.long.byte 0x50 5.--9. 1. "RANGE_MAX_QP_1,As per DSC specification" newline hexmask.long.byte 0x50 0.--4. 1. "RANGE_MAX_QP_0,As per DSC specification" line.long 0x54 "V2A__CORE_VP__REGS_APB_ENC0_RC_MAX_QP_1_p,RC Max QP 1" hexmask.long.byte 0x54 25.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x54 20.--24. 1. "RANGE_MAX_QP_9,As per DSC specification" newline hexmask.long.byte 0x54 15.--19. 1. "RANGE_MAX_QP_8,As per DSC specification" newline hexmask.long.byte 0x54 10.--14. 1. "RANGE_MAX_QP_7,As per DSC specification" newline hexmask.long.byte 0x54 5.--9. 1. "RANGE_MAX_QP_6,As per DSC specification" newline hexmask.long.byte 0x54 0.--4. 1. "RANGE_MAX_QP_5,As per DSC specification" line.long 0x58 "V2A__CORE_VP__REGS_APB_ENC0_RC_MAX_QP_2_p,RC Max QP 2" hexmask.long.byte 0x58 25.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x58 20.--24. 1. "RANGE_MAX_QP_14,As per DSC specification" newline hexmask.long.byte 0x58 15.--19. 1. "RANGE_MAX_QP_13,As per DSC specification" newline hexmask.long.byte 0x58 10.--14. 1. "RANGE_MAX_QP_12,As per DSC specification" newline hexmask.long.byte 0x58 5.--9. 1. "RANGE_MAX_QP_11,As per DSC specification" newline hexmask.long.byte 0x58 0.--4. 1. "RANGE_MAX_QP_10,As per DSC specification" line.long 0x5C "V2A__CORE_VP__REGS_APB_ENC0_RC_RANGE_BPG_OFFSETS_0_p,RC Range bpg Offsets 0" bitfld.long 0x5C 30.--31. "RESERVED,Reserved. Writes are ignored. 0x0 when read" "0,1,2,3" newline hexmask.long.byte 0x5C 24.--29. 1. "RANGE_BPG_OFFSET_4,As per DSC specification" newline hexmask.long.byte 0x5C 18.--23. 1. "RANGE_BPG_OFFSET_3,As per DSC specification" newline hexmask.long.byte 0x5C 12.--17. 1. "RANGE_BPG_OFFSET_2,As per DSC specification" newline hexmask.long.byte 0x5C 6.--11. 1. "RANGE_BPG_OFFSET_1,As per DSC specification" newline hexmask.long.byte 0x5C 0.--5. 1. "RANGE_BPG_OFFSET_0,As per DSC specification" line.long 0x60 "V2A__CORE_VP__REGS_APB_ENC0_RC_RANGE_BPG_OFFSETS_1_p,RC Range bpg Offsets 1" bitfld.long 0x60 30.--31. "RESERVED,Reserved. Writes are ignored. 0x0 when read" "0,1,2,3" newline hexmask.long.byte 0x60 24.--29. 1. "RANGE_BPG_OFFSET_9,As per DSC specification" newline hexmask.long.byte 0x60 18.--23. 1. "RANGE_BPG_OFFSET_8,As per DSC specification" newline hexmask.long.byte 0x60 12.--17. 1. "RANGE_BPG_OFFSET_7,As per DSC specification" newline hexmask.long.byte 0x60 6.--11. 1. "RANGE_BPG_OFFSET_6,As per DSC specification" newline hexmask.long.byte 0x60 0.--5. 1. "RANGE_BPG_OFFSET_5,As per DSC specification" line.long 0x64 "V2A__CORE_VP__REGS_APB_ENC0_RC_RANGE_BPG_OFFSETS_2_p,RC Range bpg Offsets 2" bitfld.long 0x64 30.--31. "RESERVED,Reserved. Writes are ignored. 0x0 when read" "0,1,2,3" newline hexmask.long.byte 0x64 24.--29. 1. "RANGE_BPG_OFFSET_14,As per DSC specification" newline hexmask.long.byte 0x64 18.--23. 1. "RANGE_BPG_OFFSET_13,As per DSC specification" newline hexmask.long.byte 0x64 12.--17. 1. "RANGE_BPG_OFFSET_12,As per DSC specification" newline hexmask.long.byte 0x64 6.--11. 1. "RANGE_BPG_OFFSET_11,As per DSC specification" newline hexmask.long.byte 0x64 0.--5. 1. "RANGE_BPG_OFFSET_10,As per DSC specification" line.long 0x68 "V2A__CORE_VP__REGS_APB_ENC0_DPI_CTRL_OUT_DELAY_p,Delay applied to DPI input control signals to generate DPI output control signals" hexmask.long.word 0x68 16.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.word 0x68 0.--15. 1. "DPI_CTRL_OUT_DELAY,Delay in number of encx clock cycles. The delay should equal to InitialLines x Htotal[clk] where Htotal is the upstream source timing controller total line time [in clock cycles not in pixels] including the horizontal blanking.." rgroup.long 0x30DC0++0x3 line.long 0x0 "V2A__CORE_VP__REGS_APB_ENC0_GENERAL_STATUS_p,General Encoder Status" hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline rbitfld.long 0x0 6. "OUT_BUFF_FULL_CONTEXT_1,Output buffer 1 [soft slice 1] is full.For Debug purposes only." "0,1" newline rbitfld.long 0x0 5. "OUT_BUFF_FULL_CONTEXT_0,Output buffer 0 [soft slice 0] is full.For Debug purposes only." "0,1" newline rbitfld.long 0x0 4. "OUT_BUFF_EMPTY_CONTEXT_1,Output buffer 1 [soft slice 1] is empty.For Debug purposes only." "0,1" newline rbitfld.long 0x0 3. "OUT_BUFF_EMPTY_CONTEXT_0,Output buffer 0 [soft slice 0] is empty.For Debug purposes only." "0,1" newline rbitfld.long 0x0 2. "FRAME_DONE,Encoder finished a frame" "0,1" newline rbitfld.long 0x0 1. "FRAME_STARTED,Encoder is currently processing a frame" "0,1" newline rbitfld.long 0x0 0. "CE,Flow control internal clock enable status.For Debug purposes only." "0,1" rgroup.long 0x30DC4++0x7 line.long 0x0 "V2A__CORE_VP__REGS_APB_ENC0_HSLICE_STATUS_p,Hard Slice Encoded Status" hexmask.long.word 0x0 16.--31. 1. "SLICE_COUNT_ENCODED,Actual slice number of current frame being processed at VLC encoder.Not re-synchronized in register clock domain. For Debug purposes only." newline hexmask.long.word 0x0 0.--15. 1. "SLICE_LINE_COUNT_ENCODED,Actual line number of current slice being processed at VLC encoder.Not re-synchronized in register clock domain. For Debug purposes only." line.long 0x4 "V2A__CORE_VP__REGS_APB_ENC0_OUT_STATUS_p,Outputted Slice Status" hexmask.long.word 0x4 16.--31. 1. "SLICE_COUNT_OUT,Actual slice number of current frame being read at output interface.Not re-synchronized in register clock domain. For Debug purposes only." newline hexmask.long.word 0x4 0.--15. 1. "SLICE_LINE_COUNT_OUT,Actual line number of current slice being read at output interface.Not re-synchronized in register clock domain. For Debug purposes only." rgroup.long 0x30DCC++0xF line.long 0x0 "V2A__CORE_VP__REGS_APB_ENC0_INT_STAT_p,Encoder Interrupt Status" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline rbitfld.long 0x0 10. "OUT_BUFF_FULL_CONTEXT_1,Output buffer 1 [soft slice 1] became full" "0,1" newline rbitfld.long 0x0 9. "OUT_BUFF_FULL_CONTEXT_0,Output buffer 0 [soft slice 0] became full" "0,1" newline rbitfld.long 0x0 8. "OUT_BUFF_EMPTY_CONTEXT_1,Output buffer 1 [soft slice 1] became empty" "0,1" newline rbitfld.long 0x0 7. "OUT_BUFF_EMPTY_CONTEXT_0,Output buffer 0 [soft slice 0] became empty" "0,1" newline rbitfld.long 0x0 6. "FRAME_DONE,Encoder finished a frame" "0,1" newline rbitfld.long 0x0 5. "FRAME_STARTED,Encoder is started to process a frame" "0,1" newline rbitfld.long 0x0 4. "CE,Flow control internal clock enable becomes high" "0,1" newline rbitfld.long 0x0 3. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1,rc_model_buffer 1 [soft slice 1] overflow" "0,1" newline rbitfld.long 0x0 2. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0,rc_model_buffer 0 [soft slice 0] overflow" "0,1" newline rbitfld.long 0x0 1. "ENC_UNDERFLOW_CONTEXT_1,output buffer 1 [soft slice 1] underflow" "0,1" newline rbitfld.long 0x0 0. "ENC_UNDERFLOW_CONTEXT_0,output buffer 0 [soft slice 0] underflow" "0,1" line.long 0x4 "V2A__CORE_VP__REGS_APB_ENC0_INT_CLR_p,Encoder Interrupt Clear. Setting any one of these bits. clears the corresponding ENC_INT_STAT bits. This register is self-clearing after 8 regs_pclk cycles." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x4 10. "OUT_BUFF_FULL_CONTEXT_1,Output buffer 1 [soft slice 1] became full" "0,1" newline bitfld.long 0x4 9. "OUT_BUFF_FULL_CONTEXT_0,Output buffer 0 [soft slice 0] became full" "0,1" newline bitfld.long 0x4 8. "OUT_BUFF_EMPTY_CONTEXT_1,Output buffer 1 [soft slice 1] became empty" "0,1" newline bitfld.long 0x4 7. "OUT_BUFF_EMPTY_CONTEXT_0,Output buffer 0 [soft slice 0] became empty" "0,1" newline bitfld.long 0x4 6. "FRAME_DONE,Encoder finished a frame" "0,1" newline bitfld.long 0x4 5. "FRAME_STARTED,Encoder is started to process a frame" "0,1" newline bitfld.long 0x4 4. "CE,Flow control internal clock enable" "0,1" newline bitfld.long 0x4 3. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1,rc model buffer 1 overflow" "0,1" newline bitfld.long 0x4 2. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0,rc model buffer 0 overflow" "0,1" newline bitfld.long 0x4 1. "ENC_UNDERFLOW_CONTEXT_1,output buffer 1 underflow" "0,1" newline bitfld.long 0x4 0. "ENC_UNDERFLOW_CONTEXT_0,output buffer 0 underflow" "0,1" line.long 0x8 "V2A__CORE_VP__REGS_APB_ENC0_INT_MASK_p,Encoder Interrupt Mask. Any bit set to 1'b1 is enabled to report an interrupt on the corresponding bit position" hexmask.long.tbyte 0x8 11.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x8 10. "OUT_BUFF_FULL_CONTEXT_1,Output buffer 1 [soft slice 1] became full" "0,1" newline bitfld.long 0x8 9. "OUT_BUFF_FULL_CONTEXT_0,Output buffer 0 [soft slice 0] became full" "0,1" newline bitfld.long 0x8 8. "OUT_BUFF_EMPTY_CONTEXT_1,Output buffer 1 [soft slice 1] became empty" "0,1" newline bitfld.long 0x8 7. "OUT_BUFF_EMPTY_CONTEXT_0,Output buffer 0 [soft slice 0] became empty" "0,1" newline bitfld.long 0x8 6. "FRAME_DONE,Encoder finished a frame" "0,1" newline bitfld.long 0x8 5. "FRAME_STARTED,Encoder is started to process a frame" "0,1" newline bitfld.long 0x8 4. "CE,Flow control internal clock enable" "0,1" newline bitfld.long 0x8 3. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1,rc model buffer 1 overflow" "0,1" newline bitfld.long 0x8 2. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0,rc model buffer 0 overflow" "0,1" newline bitfld.long 0x8 1. "ENC_UNDERFLOW_CONTEXT_1,enc underflow 1 underflow" "0,1" newline bitfld.long 0x8 0. "ENC_UNDERFLOW_CONTEXT_0,enc underflow 0 underflow" "0,1" line.long 0xC "V2A__CORE_VP__REGS_APB_ENC0_INT_TEST_p,Encoder Interrupt Test. Setting any one of these bits to 0x0 and then to 0x1 simulate a hardware event and generate an interrupt if the corresponding ENCx_INT_MASK bit is set." hexmask.long.tbyte 0xC 11.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0xC 10. "OUT_BUFF_FULL_CONTEXT_1,Output buffer 1 [soft slice 1] became full test" "0,1" newline bitfld.long 0xC 9. "OUT_BUFF_FULL_CONTEXT_0,Output buffer 0 [soft slice 0] became full test" "0,1" newline bitfld.long 0xC 8. "OUT_BUFF_EMPTY_CONTEXT_1,Output buffer 1 [soft slice 1] became empty test" "0,1" newline bitfld.long 0xC 7. "OUT_BUFF_EMPTY_CONTEXT_0,Output buffer 0 [soft slice 0] became empty test" "0,1" newline bitfld.long 0xC 6. "FRAME_DONE,Encoder finished a frame test" "0,1" newline bitfld.long 0xC 5. "FRAME_STARTED,Encoder is started to process a frame test" "0,1" newline bitfld.long 0xC 4. "CE,Flow control internal clock enable test" "0,1" newline bitfld.long 0xC 3. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1,rc model buffer 1 overflow test" "0,1" newline bitfld.long 0xC 2. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0,rc model buffer 0 overflow test" "0,1" newline bitfld.long 0xC 1. "ENC_UNDERFLOW_CONTEXT_1,enc underflow 1 underflow test" "0,1" newline bitfld.long 0xC 0. "ENC_UNDERFLOW_CONTEXT_0,enc underflow 0 underflow test" "0,1" rgroup.long 0x30E20++0x6B line.long 0x0 "V2A__CORE_VP__REGS_APB_ENC1_MAIN_CONF_p,Encoder Main Configuration values test" hexmask.long.byte 0x0 24.--31. 1. "INITIAL_LINES,Number of lines to wait before initiating transport in Command Mode." newline bitfld.long 0x0 21.--23. "RESERVED,Reserved. Writes are ignored. 0x0 when read" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ICH_RST_EOL,Forces the ICH to reset at EOL [when not in split mode]." "0,1" newline bitfld.long 0x0 19. "VIDEO_MODE,MIPI Video/Command mode: '0' Command mode '1' Video mode" "0,1" newline bitfld.long 0x0 18. "BLOCK_PRED_ENABLE,Active-High input Block Prediction Enable" "0,1" newline hexmask.long.word 0x0 8.--17. 1. "BITS_PER_PIXEL,Target bits per pixel. The value is in 6.4 format [4 LSBs for fractional part they should be 0000]" newline hexmask.long.byte 0x0 4.--7. 1. "LINEBUF_DEPTH,Depth of the line buffer used by the decoder [i.e. the number of bits stored for each component of the pixels on the previous line]" newline bitfld.long 0x0 3. "ENABLE_422,Active-High input to indicate the data_in pixels are 4:2:2 sub-sampled. This input is valid only when convert_rgb is low. NOT SUPPORTED MUST BE SET TO '0'" "0,1" newline bitfld.long 0x0 2. "CONVERT_RGB,Active-High input to indicate the data_in pixels are RGB. When set to low input it is YUV and does not require conversion." "0,1" newline bitfld.long 0x0 0.--1. "INPUT_BPC,Indicates the current input pixel stream bits per component: 00: input is 8 bits/component 01: input is 10 bits/component" "0: input is 8 bits/component,1: input is 10 bits/component,?,?" line.long 0x4 "V2A__CORE_VP__REGS_APB_ENC1_PICTURE_SIZE_p,Encoder Picture configuration" hexmask.long.word 0x4 16.--31. 1. "PICTURE_HEIGHT,Picture height" newline hexmask.long.word 0x4 0.--15. 1. "PICTURE_WIDTH,Picture width" line.long 0x8 "V2A__CORE_VP__REGS_APB_ENC1_SLICE_SIZE_p,Encoder Slice(s) configuration" hexmask.long.word 0x8 16.--31. 1. "SLICE_HEIGHT,Slice height" newline hexmask.long.word 0x8 0.--15. 1. "SLICE_WIDTH,Slice width" line.long 0xC "V2A__CORE_VP__REGS_APB_ENC1_MISC_SIZE_p,Encoder Group. Output Buffer(s). and Transport Chunk Size" hexmask.long.word 0xC 16.--31. 1. "CHUNK_SIZE,Chunk size in bytes" newline hexmask.long.word 0xC 2.--15. 1. "OB_MAX_ADDR,Output Buffer[s] max pointer address[es]" newline bitfld.long 0xC 0.--1. "SLICE_LAST_GROUP_SIZE,Size of last group of the slice line [0-based]: 0 = 1 pixel 1 = 2 pixels 2 = 3 pixels [slice_width + 2] % 3" "0: based]:,?,?,?" line.long 0x10 "V2A__CORE_VP__REGS_APB_ENC1_HRD_DELAYS_p,Hypothetical Reference Decoder delays" hexmask.long.word 0x10 16.--31. 1. "INITIAL_DEC_DELAY,Initial Decoder delay" newline hexmask.long.byte 0x10 10.--15. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.word 0x10 0.--9. 1. "INITIAL_XMIT_DELAY,Initial Decoder Transmit delay" line.long 0x14 "V2A__CORE_VP__REGS_APB_ENC1_RC_SCALE_p,RC Calculate Buffer Fullness and Offset. Scale value" hexmask.long 0x14 6.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x14 0.--5. 1. "INITIAL_SCALE_VALUE,Three fractional bits" line.long 0x18 "V2A__CORE_VP__REGS_APB_ENC1_RC_SCALE_INC_DEC_p,RC Calculate Buffer Fullness and Offset. Increment and Decrement Scale values" hexmask.long.byte 0x18 28.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.word 0x18 16.--27. 1. "SCALE_DECREMENT_INTERVAL,RC scale decrement value" newline hexmask.long.word 0x18 0.--15. 1. "SCALE_INCREMENT_INTERVAL,RC scale increment value" line.long 0x1C "V2A__CORE_VP__REGS_APB_ENC1_RC_OFFSETS_1_p,RC Calculate Buffer Fullness and Offset. Various Offset control values 1" hexmask.long 0x1C 5.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x1C 0.--4. 1. "FIRST_LINE_BPG_OFFSET,First Line" line.long 0x20 "V2A__CORE_VP__REGS_APB_ENC1_RC_OFFSETS_2_p,RC Calculate Buffer Fullness and Offset. Various Offset control values 2" hexmask.long.word 0x20 16.--31. 1. "SLICE_BPG_OFFSET,Extra budget per group [11 fractional bits]" newline hexmask.long.word 0x20 0.--15. 1. "NFL_BPG_OFFSET,Non First Line [11 fractional bits]" line.long 0x24 "V2A__CORE_VP__REGS_APB_ENC1_RC_OFFSETS_3_p,RC Calculate Buffer Fullness and Offset. Various Offset control values 3" hexmask.long.word 0x24 16.--31. 1. "FINAL_OFFSET,Final Offset" newline hexmask.long.word 0x24 0.--15. 1. "INITIAL_OFFSET,Initial Offset" line.long 0x28 "V2A__CORE_VP__REGS_APB_ENC1_FLATNESS_DETECTION_p,Flatness Signaling QP Override thresholds" hexmask.long.word 0x28 18.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x28 10.--17. 1. "FLATNESS_DET_THRESH,Flatness Detection Threshold as defined in PPS table of the DSC specification" newline hexmask.long.byte 0x28 5.--9. 1. "FLATNESS_MAX_QP,Maximum threshold" newline hexmask.long.byte 0x28 0.--4. 1. "FLATNESS_MIN_QP,Minimum threshold" line.long 0x2C "V2A__CORE_VP__REGS_APB_ENC1_RC_MODEL_SIZE_p,RC Model Size" hexmask.long.word 0x2C 16.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.word 0x2C 0.--15. 1. "RC_MODEL_SIZE,RC Model Size" line.long 0x30 "V2A__CORE_VP__REGS_APB_ENC1_RC_CONFIG_p,RC Model Various Config" hexmask.long.byte 0x30 28.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x30 24.--27. 1. "RC_TGT_OFFSET_LO,RC Target offset low" newline hexmask.long.byte 0x30 20.--23. 1. "RC_TGT_OFFSET_HI,RC Target offset high" newline bitfld.long 0x30 18.--19. "RESERVED,Reserved. Writes are ignored. 0x0 when read" "0,1,2,3" newline hexmask.long.byte 0x30 13.--17. 1. "RC_QUANT_INCR_LIMIT1,RC quantization increment limit 1" newline hexmask.long.byte 0x30 8.--12. 1. "RC_QUANT_INCR_LIMIT0,RC quantization increment limit 0" newline hexmask.long.byte 0x30 4.--7. 1. "RESERVED,RC Edge factor [1 fractional bit]" newline hexmask.long.byte 0x30 0.--3. 1. "RC_EDGE_FACTOR,Reserved. Writes are ignored. 0x0 when read" line.long 0x34 "V2A__CORE_VP__REGS_APB_ENC1_RC_BUF_THRESH_0_p,RC Model Buffer Thresholds 0" hexmask.long.byte 0x34 24.--31. 1. "RC_BUF_THRESH_3,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" newline hexmask.long.byte 0x34 16.--23. 1. "RC_BUF_THRESH_2,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" newline hexmask.long.byte 0x34 8.--15. 1. "RC_BUF_THRESH_1,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" newline hexmask.long.byte 0x34 0.--7. 1. "RC_BUF_THRESH_0,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" line.long 0x38 "V2A__CORE_VP__REGS_APB_ENC1_RC_BUF_THRESH_1_p,RC Model Buffer Thresholds 1" hexmask.long.byte 0x38 24.--31. 1. "RC_BUF_THRESH_7,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" newline hexmask.long.byte 0x38 16.--23. 1. "RC_BUF_THRESH_6,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" newline hexmask.long.byte 0x38 8.--15. 1. "RC_BUF_THRESH_5,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" newline hexmask.long.byte 0x38 0.--7. 1. "RC_BUF_THRESH_4,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" line.long 0x3C "V2A__CORE_VP__REGS_APB_ENC1_RC_BUF_THRESH_2_p,RC Model Buffer Thresholds 2" hexmask.long.byte 0x3C 24.--31. 1. "RC_BUF_THRESH_11,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" newline hexmask.long.byte 0x3C 16.--23. 1. "RC_BUF_THRESH_10,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" newline hexmask.long.byte 0x3C 8.--15. 1. "RC_BUF_THRESH_9,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" newline hexmask.long.byte 0x3C 0.--7. 1. "RC_BUF_THRESH_8,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" line.long 0x40 "V2A__CORE_VP__REGS_APB_ENC1_RC_BUF_THRESH_3_p,RC Model Buffer Thresholds 3" hexmask.long.word 0x40 16.--31. 1. "RESERVED,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" newline hexmask.long.byte 0x40 8.--15. 1. "RC_BUF_THRESH_13,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" newline hexmask.long.byte 0x40 0.--7. 1. "RC_BUF_THRESH_12,8 MSBs of the value. Values in configuration files are 14 bits but 6 LSBs are always 0" line.long 0x44 "V2A__CORE_VP__REGS_APB_ENC1_RC_MIN_QP_0_p,RC Min QP 0" hexmask.long.byte 0x44 25.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x44 20.--24. 1. "RANGE_MIN_QP_4,As per DSC specification" newline hexmask.long.byte 0x44 15.--19. 1. "RANGE_MIN_QP_3,As per DSC specification" newline hexmask.long.byte 0x44 10.--14. 1. "RANGE_MIN_QP_2,As per DSC specification" newline hexmask.long.byte 0x44 5.--9. 1. "RANGE_MIN_QP_1,As per DSC specification" newline hexmask.long.byte 0x44 0.--4. 1. "RANGE_MIN_QP_0,As per DSC specification" line.long 0x48 "V2A__CORE_VP__REGS_APB_ENC1_RC_MIN_QP_1_p,RC Min QP 1" hexmask.long.byte 0x48 25.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x48 20.--24. 1. "RANGE_MIN_QP_9,As per DSC specification" newline hexmask.long.byte 0x48 15.--19. 1. "RANGE_MIN_QP_8,As per DSC specification" newline hexmask.long.byte 0x48 10.--14. 1. "RANGE_MIN_QP_7,As per DSC specification" newline hexmask.long.byte 0x48 5.--9. 1. "RANGE_MIN_QP_6,As per DSC specification" newline hexmask.long.byte 0x48 0.--4. 1. "RANGE_MIN_QP_5,As per DSC specification" line.long 0x4C "V2A__CORE_VP__REGS_APB_ENC1_RC_MIN_QP_2_p,RC Min QP 2" hexmask.long.byte 0x4C 25.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x4C 20.--24. 1. "RANGE_MIN_QP_14,As per DSC specification" newline hexmask.long.byte 0x4C 15.--19. 1. "RANGE_MIN_QP_13,As per DSC specification" newline hexmask.long.byte 0x4C 10.--14. 1. "RANGE_MIN_QP_12,As per DSC specification" newline hexmask.long.byte 0x4C 5.--9. 1. "RANGE_MIN_QP_11,As per DSC specification" newline hexmask.long.byte 0x4C 0.--4. 1. "RANGE_MIN_QP_10,As per DSC specification" line.long 0x50 "V2A__CORE_VP__REGS_APB_ENC1_RC_MAX_QP_0_p,RC Max QP 0" hexmask.long.byte 0x50 25.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x50 20.--24. 1. "RANGE_MAX_QP_4,As per DSC specification" newline hexmask.long.byte 0x50 15.--19. 1. "RANGE_MAX_QP_3,As per DSC specification" newline hexmask.long.byte 0x50 10.--14. 1. "RANGE_MAX_QP_2,As per DSC specification" newline hexmask.long.byte 0x50 5.--9. 1. "RANGE_MAX_QP_1,As per DSC specification" newline hexmask.long.byte 0x50 0.--4. 1. "RANGE_MAX_QP_0,As per DSC specification" line.long 0x54 "V2A__CORE_VP__REGS_APB_ENC1_RC_MAX_QP_1_p,RC Max QP 1" hexmask.long.byte 0x54 25.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x54 20.--24. 1. "RANGE_MAX_QP_9,As per DSC specification" newline hexmask.long.byte 0x54 15.--19. 1. "RANGE_MAX_QP_8,As per DSC specification" newline hexmask.long.byte 0x54 10.--14. 1. "RANGE_MAX_QP_7,As per DSC specification" newline hexmask.long.byte 0x54 5.--9. 1. "RANGE_MAX_QP_6,As per DSC specification" newline hexmask.long.byte 0x54 0.--4. 1. "RANGE_MAX_QP_5,As per DSC specification" line.long 0x58 "V2A__CORE_VP__REGS_APB_ENC1_RC_MAX_QP_2_p,RC Max QP 2" hexmask.long.byte 0x58 25.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x58 20.--24. 1. "RANGE_MAX_QP_14,As per DSC specification" newline hexmask.long.byte 0x58 15.--19. 1. "RANGE_MAX_QP_13,As per DSC specification" newline hexmask.long.byte 0x58 10.--14. 1. "RANGE_MAX_QP_12,As per DSC specification" newline hexmask.long.byte 0x58 5.--9. 1. "RANGE_MAX_QP_11,As per DSC specification" newline hexmask.long.byte 0x58 0.--4. 1. "RANGE_MAX_QP_10,As per DSC specification" line.long 0x5C "V2A__CORE_VP__REGS_APB_ENC1_RC_RANGE_BPG_OFFSETS_0_p,RC Range bpg Offsets 0" bitfld.long 0x5C 30.--31. "RESERVED,Reserved. Writes are ignored. 0x0 when read" "0,1,2,3" newline hexmask.long.byte 0x5C 24.--29. 1. "RANGE_BPG_OFFSET_4,As per DSC specification" newline hexmask.long.byte 0x5C 18.--23. 1. "RANGE_BPG_OFFSET_3,As per DSC specification" newline hexmask.long.byte 0x5C 12.--17. 1. "RANGE_BPG_OFFSET_2,As per DSC specification" newline hexmask.long.byte 0x5C 6.--11. 1. "RANGE_BPG_OFFSET_1,As per DSC specification" newline hexmask.long.byte 0x5C 0.--5. 1. "RANGE_BPG_OFFSET_0,As per DSC specification" line.long 0x60 "V2A__CORE_VP__REGS_APB_ENC1_RC_RANGE_BPG_OFFSETS_1_p,RC Range bpg Offsets 1" bitfld.long 0x60 30.--31. "RESERVED,Reserved. Writes are ignored. 0x0 when read" "0,1,2,3" newline hexmask.long.byte 0x60 24.--29. 1. "RANGE_BPG_OFFSET_9,As per DSC specification" newline hexmask.long.byte 0x60 18.--23. 1. "RANGE_BPG_OFFSET_8,As per DSC specification" newline hexmask.long.byte 0x60 12.--17. 1. "RANGE_BPG_OFFSET_7,As per DSC specification" newline hexmask.long.byte 0x60 6.--11. 1. "RANGE_BPG_OFFSET_6,As per DSC specification" newline hexmask.long.byte 0x60 0.--5. 1. "RANGE_BPG_OFFSET_5,As per DSC specification" line.long 0x64 "V2A__CORE_VP__REGS_APB_ENC1_RC_RANGE_BPG_OFFSETS_2_p,RC Range bpg Offsets 2" bitfld.long 0x64 30.--31. "RESERVED,Reserved. Writes are ignored. 0x0 when read" "0,1,2,3" newline hexmask.long.byte 0x64 24.--29. 1. "RANGE_BPG_OFFSET_14,As per DSC specification" newline hexmask.long.byte 0x64 18.--23. 1. "RANGE_BPG_OFFSET_13,As per DSC specification" newline hexmask.long.byte 0x64 12.--17. 1. "RANGE_BPG_OFFSET_12,As per DSC specification" newline hexmask.long.byte 0x64 6.--11. 1. "RANGE_BPG_OFFSET_11,As per DSC specification" newline hexmask.long.byte 0x64 0.--5. 1. "RANGE_BPG_OFFSET_10,As per DSC specification" line.long 0x68 "V2A__CORE_VP__REGS_APB_ENC1_DPI_CTRL_OUT_DELAY_p,Delay applied to DPI input control signals to generate DPI output control signals" hexmask.long.word 0x68 16.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.word 0x68 0.--15. 1. "DPI_CTRL_OUT_DELAY,Delay in number of encx clock cycles. The delay should equal to InitialLines x Htotal[clk] where Htotal is the upstream source timing controller total line time [in clock cycles not in pixels] including the horizontal blanking.." rgroup.long 0x30EC0++0x3 line.long 0x0 "V2A__CORE_VP__REGS_APB_ENC1_GENERAL_STATUS_p,General Encoder Status" hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline rbitfld.long 0x0 6. "OUT_BUFF_FULL_CONTEXT_1,Output buffer 1 [soft slice 1] is full.For Debug purposes only." "0,1" newline rbitfld.long 0x0 5. "OUT_BUFF_FULL_CONTEXT_0,Output buffer 0 [soft slice 0] is full.For Debug purposes only." "0,1" newline rbitfld.long 0x0 4. "OUT_BUFF_EMPTY_CONTEXT_1,Output buffer 1 [soft slice 1] is empty.For Debug purposes only." "0,1" newline rbitfld.long 0x0 3. "OUT_BUFF_EMPTY_CONTEXT_0,Output buffer 0 [soft slice 0] is empty.For Debug purposes only." "0,1" newline rbitfld.long 0x0 2. "FRAME_DONE,Encoder finished a frame" "0,1" newline rbitfld.long 0x0 1. "FRAME_STARTED,Encoder is currently processing a frame" "0,1" newline rbitfld.long 0x0 0. "CE,Flow control internal clock enable status.For Debug purposes only." "0,1" rgroup.long 0x30EC4++0x7 line.long 0x0 "V2A__CORE_VP__REGS_APB_ENC1_HSLICE_STATUS_p,Hard Slice Encoded Status" hexmask.long.word 0x0 16.--31. 1. "SLICE_COUNT_ENCODED,Actual slice number of current frame being processed at VLC encoder.Not re-synchronized in register clock domain. For Debug purposes only." newline hexmask.long.word 0x0 0.--15. 1. "SLICE_LINE_COUNT_ENCODED,Actual line number of current slice being processed at VLC encoder.Not re-synchronized in register clock domain. For Debug purposes only." line.long 0x4 "V2A__CORE_VP__REGS_APB_ENC1_OUT_STATUS_p,Outputted Slice Status" hexmask.long.word 0x4 16.--31. 1. "SLICE_COUNT_OUT,Actual slice number of current frame being read at output interface.Not re-synchronized in register clock domain. For Debug purposes only." newline hexmask.long.word 0x4 0.--15. 1. "SLICE_LINE_COUNT_OUT,Actual line number of current slice being read at output interface.Not re-synchronized in register clock domain. For Debug purposes only." rgroup.long 0x30ECC++0xF line.long 0x0 "V2A__CORE_VP__REGS_APB_ENC1_INT_STAT_p,Encoder Interrupt Status" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline rbitfld.long 0x0 10. "OUT_BUFF_FULL_CONTEXT_1,Output buffer 1 [soft slice 1] became full" "0,1" newline rbitfld.long 0x0 9. "OUT_BUFF_FULL_CONTEXT_0,Output buffer 0 [soft slice 0] became full" "0,1" newline rbitfld.long 0x0 8. "OUT_BUFF_EMPTY_CONTEXT_1,Output buffer 1 [soft slice 1] became empty" "0,1" newline rbitfld.long 0x0 7. "OUT_BUFF_EMPTY_CONTEXT_0,Output buffer 0 [soft slice 0] became empty" "0,1" newline rbitfld.long 0x0 6. "FRAME_DONE,Encoder finished a frame" "0,1" newline rbitfld.long 0x0 5. "FRAME_STARTED,Encoder is started to process a frame" "0,1" newline rbitfld.long 0x0 4. "CE,Flow control internal clock enable becomes high" "0,1" newline rbitfld.long 0x0 3. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1,output buffer 1 [soft slice 1] underflow" "0,1" newline rbitfld.long 0x0 2. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0,output buffer 0 [soft slice 0] underflow" "0,1" newline rbitfld.long 0x0 1. "ENC_UNDERFLOW_CONTEXT_1,output buffer 1 [soft slice 1] underflow" "0,1" newline rbitfld.long 0x0 0. "ENC_UNDERFLOW_CONTEXT_0,output buffer 0 [soft slice 0] underflow" "0,1" line.long 0x4 "V2A__CORE_VP__REGS_APB_ENC1_INT_CLR_p,Encoder Interrupt Clear. Setting any one of these bits. clears the corresponding ENC_INT_STAT bits. This register is self-clearing after 8 regs_pclk cycles." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x4 10. "OUT_BUFF_FULL_CONTEXT_1,Output buffer 1 [soft slice 1] became full" "0,1" newline bitfld.long 0x4 9. "OUT_BUFF_FULL_CONTEXT_0,Output buffer 0 [soft slice 0] became full" "0,1" newline bitfld.long 0x4 8. "OUT_BUFF_EMPTY_CONTEXT_1,Output buffer 1 [soft slice 1] became empty" "0,1" newline bitfld.long 0x4 7. "OUT_BUFF_EMPTY_CONTEXT_0,Output buffer 0 [soft slice 0] became empty" "0,1" newline bitfld.long 0x4 6. "FRAME_DONE,Encoder finished a frame" "0,1" newline bitfld.long 0x4 5. "FRAME_STARTED,Encoder is started to process a frame" "0,1" newline bitfld.long 0x4 4. "CE,Flow control internal clock enable" "0,1" newline bitfld.long 0x4 3. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1,rc model buffer 1 overflow" "0,1" newline bitfld.long 0x4 2. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0,rc model buffer 0 overflow" "0,1" newline bitfld.long 0x4 1. "ENC_UNDERFLOW_CONTEXT_1,output buffer 1 underflow" "0,1" newline bitfld.long 0x4 0. "ENC_UNDERFLOW_CONTEXT_0,output buffer 0 underflow" "0,1" line.long 0x8 "V2A__CORE_VP__REGS_APB_ENC1_INT_MASK_p,Encoder Interrupt Mask. Any bit set to 1'b1 is enabled to report an interrupt on the corresponding bit position" hexmask.long.tbyte 0x8 11.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x8 10. "OUT_BUFF_FULL_CONTEXT_1,Output buffer 1 [soft slice 1] became full" "0,1" newline bitfld.long 0x8 9. "OUT_BUFF_FULL_CONTEXT_0,Output buffer 0 [soft slice 0] became full" "0,1" newline bitfld.long 0x8 8. "OUT_BUFF_EMPTY_CONTEXT_1,Output buffer 1 [soft slice 1] became empty" "0,1" newline bitfld.long 0x8 7. "OUT_BUFF_EMPTY_CONTEXT_0,Output buffer 0 [soft slice 0] became empty" "0,1" newline bitfld.long 0x8 6. "FRAME_DONE,Encoder finished a frame" "0,1" newline bitfld.long 0x8 5. "FRAME_STARTED,Encoder is started to process a frame" "0,1" newline bitfld.long 0x8 4. "CE,Flow control internal clock enable" "0,1" newline bitfld.long 0x8 3. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1,rc model buffer 1 overflow" "0,1" newline bitfld.long 0x8 2. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0,rc model buffer 0 overflow" "0,1" newline bitfld.long 0x8 1. "ENC_UNDERFLOW_CONTEXT_1,enc underflow 1 underflow" "0,1" newline bitfld.long 0x8 0. "ENC_UNDERFLOW_CONTEXT_0,enc underflow 0 underflow" "0,1" line.long 0xC "V2A__CORE_VP__REGS_APB_ENC1_INT_TEST_p,Encoder Interrupt Test. Setting any one of these bits to 0x0 and then to 0x1 simulate a hardware event and generate an interrupt if the corresponding ENCx_INT_MASK bit is set." hexmask.long.tbyte 0xC 11.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0xC 10. "OUT_BUFF_FULL_CONTEXT_1,Output buffer 1 [soft slice 1] became full test" "0,1" newline bitfld.long 0xC 9. "OUT_BUFF_FULL_CONTEXT_0,Output buffer 0 [soft slice 0] became full test" "0,1" newline bitfld.long 0xC 8. "OUT_BUFF_EMPTY_CONTEXT_1,Output buffer 1 [soft slice 1] became empty test" "0,1" newline bitfld.long 0xC 7. "OUT_BUFF_EMPTY_CONTEXT_0,Output buffer 0 [soft slice 0] became empty test" "0,1" newline bitfld.long 0xC 6. "FRAME_DONE,Encoder finished a frame test" "0,1" newline bitfld.long 0xC 5. "FRAME_STARTED,Encoder is started to process a frame test" "0,1" newline bitfld.long 0xC 4. "CE,Flow control internal clock enable test" "0,1" newline bitfld.long 0xC 3. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1,rc model buffer 1 overflow test" "0,1" newline bitfld.long 0xC 2. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0,rc model buffer 0 overflow test" "0,1" newline bitfld.long 0xC 1. "ENC_UNDERFLOW_CONTEXT_1,enc underflow 1 underflow test" "0,1" newline bitfld.long 0xC 0. "ENC_UNDERFLOW_CONTEXT_0,enc underflow 0 underflow test" "0,1" rgroup.long 0x30F00++0xF line.long 0x0 "V2A__CORE_VP__REGS_APB_ENC_ASF_INT_STAT_p,Encoder ASF Interrupt Status" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline rbitfld.long 0x0 8. "ASF_CSR_ERR,Configuration and status registers uncorrectable error interrupt" "0,1" newline rbitfld.long 0x0 7. "ENC1_SELF_CHK_ERR,Hard Slice 1 Encoder self-check uncorrectable error interrupt" "0,1" newline rbitfld.long 0x0 6. "ENC1_OUT_CHK_ERR,Hard Slice 1 Encoder output checker uncorrectable error interrupt" "0,1" newline rbitfld.long 0x0 5. "ENC1_ASF_SRAM_UNCORR_ERR,Hard Slice 1 SRAM uncorrectable error interrupt" "0,1" newline rbitfld.long 0x0 4. "ENC1_ASF_SRAM_CORR_ERR,Hard Slice 1 SRAM correctable error interrupt" "0,1" newline rbitfld.long 0x0 3. "ENC0_SELF_CHK_ERR,Hard Slice 0 Encoder self-check uncorrectable error interrupt" "0,1" newline rbitfld.long 0x0 2. "ENC0_OUT_CHK_ERR,Hard Slice 0 Encoder output checker uncorrectable error interrupt" "0,1" newline bitfld.long 0x0 1. "ENC0_ASF_SRAM_UNCORR_ERR,Hard Slice 0 SRAM uncorrectable error interrupt" "0,1" newline rbitfld.long 0x0 0. "ENC0_ASF_SRAM_CORR_ERR,Hard Slice 0 SRAM correctable error interrupt" "0,1" line.long 0x4 "V2A__CORE_VP__REGS_APB_ENC_ASF_INT_MASK_p,Encoder ASF Interrupt Mask. Any bit set to 1'b1 is enabled to report an interrupt on the corresponding bit position" hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x4 8. "ASF_CSR_ERR,Configuration and status registers uncorrectable error interrupt" "0,1" newline bitfld.long 0x4 7. "ENC1_SELF_CHK_ERR,Hard Slice 1 Encoder self-check uncorrectable error interrupt" "0,1" newline bitfld.long 0x4 6. "ENC1_OUT_CHK_ERR,Hard Slice 1 Encoder output checker uncorrectable error interrupt" "0,1" newline bitfld.long 0x4 5. "ENC1_ASF_SRAM_UNCORR_ERR,Hard Slice 1 SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x4 4. "ENC1_ASF_SRAM_CORR_ERR,Hard Slice 1 SRAM correctable error interrupt" "0,1" newline bitfld.long 0x4 3. "ENC0_SELF_CHK_ERR,Hard Slice 0 Encoder self-check uncorrectable error interrupt" "0,1" newline bitfld.long 0x4 2. "ENC0_OUT_CHK_ERR,Hard Slice 0 Encoder output checker uncorrectable error interrupt" "0,1" newline bitfld.long 0x4 1. "ENC0_ASF_SRAM_UNCORR_ERR,Hard Slice 0 SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x4 0. "ENC0_ASF_SRAM_CORR_ERR,Hard Slice 0 SRAM correctable error interrupt" "0,1" line.long 0x8 "V2A__CORE_VP__REGS_APB_ENC_ASF_INT_CLR_p,Encoder ASF Interrupt Clear. Setting any one of these bits. clears the corresponding ENC_ASF_INT_STAT bits" hexmask.long.tbyte 0x8 9.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x8 8. "ASF_CSR_ERR,Configuration and status registers uncorrectable error interrupt" "0,1" newline bitfld.long 0x8 7. "ENC1_SELF_CHK_ERR,Hard Slice 1 Encoder self-check uncorrectable error interrupt" "0,1" newline bitfld.long 0x8 6. "ENC1_OUT_CHK_ERR,Hard Slice 1 Encoder output checker uncorrectable error interrupt" "0,1" newline bitfld.long 0x8 5. "ENC1_ASF_SRAM_UNCORR_ERR,Hard Slice 1 SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x8 4. "ENC1_ASF_SRAM_CORR_ERR,Hard Slice 1 SRAM correctable error interrupt" "0,1" newline bitfld.long 0x8 3. "ENC0_SELF_CHK_ERR,Hard Slice 0 Encoder self-check uncorrectable error interrupt" "0,1" newline bitfld.long 0x8 2. "ENC0_OUT_CHK_ERR,Hard Slice 0 Encoder output checker uncorrectable error interrupt" "0,1" newline bitfld.long 0x8 1. "ENC0_ASF_SRAM_UNCORR_ERR,Hard Slice 0 SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x8 0. "ENC0_ASF_SRAM_CORR_ERR,Hard Slice 0 SRAM correctable error interrupt" "0,1" line.long 0xC "V2A__CORE_VP__REGS_APB_ENC_ASF_INT_TEST_p,Encoder ASF Interrupt Test. Setting any one of these bits to 0x0 and then to 0x1 simulate a hardware event and generate an interrupt if the corresponding ENC_ASF_INT_MASK bit is set" hexmask.long.tbyte 0xC 9.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0xC 8. "ASF_CSR_ERR,Configuration and status registers uncorrectable error interrupt test" "0,1" newline bitfld.long 0xC 7. "ENC1_SELF_CHK_ERR,Hard Slice 1 Encoder self-check uncorrectable error interrupt test" "0,1" newline bitfld.long 0xC 6. "ENC1_OUT_CHK_ERR,Hard Slice 1 Encoder output checker uncorrectable error interrupt test" "0,1" newline bitfld.long 0xC 5. "ENC1_ASF_SRAM_UNCORR_ERR,Hard Slice 1 SRAM uncorrectable error interrupt test" "0,1" newline bitfld.long 0xC 4. "ENC1_ASF_SRAM_CORR_ERR,Hard Slice 1 SRAM correctable error interrupt test" "0,1" newline bitfld.long 0xC 3. "ENC0_SELF_CHK_ERR,Hard Slice 0 Encoder self-check uncorrectable error interrupt test" "0,1" newline bitfld.long 0xC 2. "ENC0_OUT_CHK_ERR,Hard Slice 0 Encoder output checker uncorrectable error interrupt test" "0,1" newline bitfld.long 0xC 1. "ENC0_ASF_SRAM_UNCORR_ERR,Hard Slice 0 SRAM uncorrectable error interrupt test" "0,1" newline bitfld.long 0xC 0. "ENC0_ASF_SRAM_CORR_ERR,Hard Slice 0 SRAM correctable error interrupt test" "0,1" rgroup.long 0x30F20++0x27 line.long 0x0 "V2A__CORE_VP__REGS_APB_ENC0_ASF_SRAM_CORR_p,Hard Slice 0 Status register for SRAM uncorrectable fault" hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline rbitfld.long 0x0 24.--25. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault. In case of simultaneous faults priority is given to the highest number below. 3: SSM_S 2: SSM_D 1: Output Buffer 0: Line Buffer" "0: Line Buffer,1: Output Buffer,2: SSM_D,3: SSM_S" newline hexmask.long.tbyte 0x0 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault" line.long 0x4 "V2A__CORE_VP__REGS_APB_ENC0_ASF_SRAM_UNCORR_p,Hard Slice 0 Status register for SRAM uncorrectable fault" hexmask.long.byte 0x4 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline rbitfld.long 0x4 24.--25. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault. In case of simultaneous faults priority is given to the highest number below. 3: SSM_S 2: SSM_D 1: Output Buffer 0: Line Buffer" "0: Line Buffer,1: Output Buffer,2: SSM_D,3: SSM_S" newline hexmask.long.tbyte 0x4 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault" line.long 0x8 "V2A__CORE_VP__REGS_APB_ENC1_ASF_SRAM_CORR_p,Hard Slice 1 Status register for SRAM uncorrectable fault" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline rbitfld.long 0x8 24.--25. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault. In case of simultaneous faults priority is given to the highest number below. 3: SSM_S 2: SSM_D 1: Output Buffer 0: Line Buffer" "0: Line Buffer,1: Output Buffer,2: SSM_D,3: SSM_S" newline hexmask.long.tbyte 0x8 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault" line.long 0xC "V2A__CORE_VP__REGS_APB_ENC1_ASF_SRAM_UNCORR_p,Hard Slice 1 Status register for SRAM uncorrectable fault" hexmask.long.byte 0xC 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline rbitfld.long 0xC 24.--25. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault. In case of simultaneous faults priority is given to the highest number below. 3: SSM_S 2: SSM_D 1: Output Buffer 0: Line Buffer" "0: Line Buffer,1: Output Buffer,2: SSM_D,3: SSM_S" newline hexmask.long.tbyte 0xC 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault" line.long 0x10 "V2A__CORE_VP__REGS_APB_ENC0_ASF_CSR_CHK_TEST_p,Hard Slice 0 Test for CSR protection expected CRC" hexmask.long.word 0x10 16.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.word 0x10 0.--15. 1. "ENC0_ASF_CSR_CHK_TEST,Each bit of the expected CRC can be corrupted separately [one bit at a time] using this register." line.long 0x14 "V2A__CORE_VP__REGS_APB_ENC1_ASF_CSR_CHK_TEST_p,Hard Slice 1 Test for CSR protection expected CRC" hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.word 0x14 0.--15. 1. "ENC1_ASF_CSR_CHK_TEST,Each bit of the expected CRC can be corrupted separately [one bit at a time] using this register." line.long 0x18 "V2A__CORE_VP__REGS_APB_ENC0_ASF_SELF_CHK_TEST_p,Hard Slice 0 Test for Self Check expected CRC" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.word 0x18 0.--15. 1. "ENC0_ASF_SELF_CHK_TEST,Each bit of the expected CRC can be corrupted separately [one bit at a time] using this register." line.long 0x1C "V2A__CORE_VP__REGS_APB_ENC1_ASF_SELF_CHK_TEST_p,Hard Slice 1 Test for Self Check expected CRC" hexmask.long.word 0x1C 16.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.word 0x1C 0.--15. 1. "ENC1_ASF_SELF_CHK_TEST,Each bit of the expected CRC can be corrupted separately [one bit at a time] using this register." line.long 0x20 "V2A__CORE_VP__REGS_APB_ENC0_ASF_OUT_CHK_TEST_p,Hard Slice 0 Test for Output Checker. Each bit (one at a time) can used to corrupt various input/parameter values of the module." hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x20 9.--15. 1. "RESERVED,Reserved but this field is a R/W field that returns the same value that was written to it." newline bitfld.long 0x20 8. "END_FRAME_OUT_STUCK1_ERR," "0,1" newline bitfld.long 0x20 7. "END_LINE_OUT_STUCK1_ERR," "0,1" newline bitfld.long 0x20 6. "END_CHUNK_STUCK1_ERR," "0,1" newline bitfld.long 0x20 5. "VALID_OUT_STUCK1_ERR," "0,1" newline bitfld.long 0x20 4. "DATA_OUT_STUCK1_ERR," "0,1" newline bitfld.long 0x20 3. "VALID_STUCK0_ERR," "0,1" newline bitfld.long 0x20 2. "NVB_VALUE_ERR," "0,1" newline bitfld.long 0x20 1. "LINE_CNT_ERR," "0,1" newline bitfld.long 0x20 0. "BYTE_CNT_ERR," "0,1" line.long 0x24 "V2A__CORE_VP__REGS_APB_ENC1_ASF_OUT_CHK_TEST_p,Hard Slice 1 Test for Output Checker. Each bit (one at a time) can used to corrupt various input/parameter values of the module." hexmask.long.word 0x24 16.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x24 9.--15. 1. "RESERVED,Reserved but this field is a R/W field that returns the same value that was written to it." newline bitfld.long 0x24 8. "END_FRAME_OUT_STUCK1_ERR," "0,1" newline bitfld.long 0x24 7. "END_LINE_OUT_STUCK1_ERR," "0,1" newline bitfld.long 0x24 6. "END_CHUNK_STUCK1_ERR," "0,1" newline bitfld.long 0x24 5. "VALID_OUT_STUCK1_ERR," "0,1" newline bitfld.long 0x24 4. "DATA_OUT_STUCK1_ERR," "0,1" newline bitfld.long 0x24 3. "VALID_STUCK0_ERR," "0,1" newline bitfld.long 0x24 2. "NVB_VALUE_ERR," "0,1" newline bitfld.long 0x24 1. "LINE_CNT_ERR," "0,1" newline bitfld.long 0x24 0. "BYTE_CNT_ERR," "0,1" rgroup.long 0x0++0x3B line.long 0x0 "V2A__CORE_VP__REGS_APB_CM_CTRL_p,Clock Meter control" hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x0 4.--6. "I2S_MULT,Select the division of N value for different I2S TDM configuration" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "SEL_AUD_LANE_REF,When 1 Select Audio CLK as a reference [HDMI] When 0 Select LANE CLK as a reference [DP]" "0,1" newline bitfld.long 0x0 2. "I2S_SEL_EXTERNAL,When 1 Select external values of NMAUD [N/A] for I2S" "0,1" newline bitfld.long 0x0 1. "SPDIF_SEL_EXTERNAL,When 1 Select external values of NMAUD [N/A] for SPDIF" "0,1" newline bitfld.long 0x0 0. "NMVID_SEL_EXTERNAL,When 1 Select external values of NMVID [N/A]" "0,1" line.long 0x4 "V2A__CORE_VP__REGS_APB_CM_I2S_CTRL_p,I2S clock control" hexmask.long.byte 0x4 28.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.byte 0x4 24.--27. 1. "I2S_MEAS_TOLERANCE,Measurement tolerance of Audio clock to be stable in clocks" newline hexmask.long.tbyte 0x4 0.--23. 1. "I2S_REF_CYC,Reference cycles for I2S Audio meter" line.long 0x8 "V2A__CORE_VP__REGS_APB_CM_SPDIF_CTRL_p,SPDIF clock control" hexmask.long.byte 0x8 28.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.byte 0x8 24.--27. 1. "SPDIF_MEAS_TOLERANCE,SPDIF measurement tolerance to be stable in clocks" newline hexmask.long.tbyte 0x8 0.--23. 1. "SPDIF_REF_CYC,Reference cycles of SPDIF measurement" line.long 0xC "V2A__CORE_VP__REGS_APB_CM_VID_CTRL_p,Video clock control" hexmask.long.byte 0xC 28.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.byte 0xC 24.--27. 1. "NMVID_MEAS_TOLERANCE,Video measurement tolerance in pixel clock cycles" newline hexmask.long.tbyte 0xC 0.--23. 1. "NMVID_REF_CYC,Video Reference cycles" line.long 0x10 "V2A__CORE_VP__REGS_APB_CM_LANE_CTRL_p,Lane control" hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.tbyte 0x10 0.--23. 1. "LANE_REF_CYC,Reference cycles when using lane clock as Reference [DP]" line.long 0x14 "V2A__CORE_VP__REGS_APB_I2S_NM_STABLE_p,I2S clock stable. audio clock measured" hexmask.long 0x14 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline rbitfld.long 0x14 0. "I2S_MNAUD_STABLE,I2S NMAUD Mesurment stable" "0,1" line.long 0x18 "V2A__CORE_VP__REGS_APB_I2S_NCTS_STABLE_p,I2S clock stable. lane clock measured" hexmask.long 0x18 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline rbitfld.long 0x18 0. "I2S_NCTS_STABLE,i2s CTS measurement stable" "0,1" line.long 0x1C "V2A__CORE_VP__REGS_APB_SPDIF_NM_STABLE_p,SPDIF clock stable. audio clock measured" hexmask.long 0x1C 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline rbitfld.long 0x1C 0. "SPDIF_MNAUD_STABLE,SPDIF NMAUD measurement stable" "0,1" line.long 0x20 "V2A__CORE_VP__REGS_APB_SPDIF_NCTS_STABLE_p,SPDIF clock stable. lane clock measured" hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline rbitfld.long 0x20 0. "SPDIF_NCTS_STABLE,SPDIF CTS measurement stable" "0,1" line.long 0x24 "V2A__CORE_VP__REGS_APB_NMVID_MEAS_STABLE_p,Video clock stable" hexmask.long 0x24 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline rbitfld.long 0x24 0. "ST_NMVID_MEAS_STABLE,Pixel clock NMVID measurement stable" "0,1" line.long 0x28 "V2A__CORE_VP__REGS_APB_CM_VID_MEAS_p,Video cycles measure" hexmask.long.byte 0x28 25.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x28 24. "NMVID_MEAS_VALID_INDC,When Toggle Valid pulse is generated to sample MNVID fix value" "0,1" newline hexmask.long.tbyte 0x28 0.--23. 1. "NMVID_MEAS_CYC,Fixed Value for NVID The MVID is nmvid_ref_cyc[23:0]" line.long 0x2C "V2A__CORE_VP__REGS_APB_CM_AUD_MEAS_p,Audio cycles measure" hexmask.long.byte 0x2C 25.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x2C 24. "NMAUD_MEAS_VALID_INDC,When Toggle Valid pulse is generated to sample MNAUD fix value" "0,1" newline hexmask.long.tbyte 0x2C 0.--23. 1. "NMAUD_MEAS_CYC,Fixed Value for NAUD The MAUD is lane_ref_cyc[23:0]" line.long 0x30 "V2A__CORE_VP__REGS_APB_I2S_MEAS_p,I2S clock measurement HDMI" hexmask.long.byte 0x30 24.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.tbyte 0x30 0.--23. 1. "I2_MEAS,I2S measurement value" line.long 0x34 "V2A__CORE_VP__REGS_APB_SPDIF_MEAS_p,SPDIF clock measurement HDMI" hexmask.long.byte 0x34 24.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.tbyte 0x34 0.--23. 1. "SPDIF_MEAS,SPDIF Clock Meter measurement value [in DP]" line.long 0x38 "V2A__CORE_VP__REGS_APB_NMVID_MEAS_p,Video clock measurement" hexmask.long.byte 0x38 24.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.tbyte 0x38 0.--23. 1. "NMVID_MEAS,Video clock measurement value" rgroup.long 0x0++0x3 line.long 0x0 "V2A__CORE_VP__REGS_APB_CM_CTRL_p,Clock Meter control" hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x0 4.--6. "I2S_MULT,Select the division of N value for different I2S TDM configuration" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "SEL_AUD_LANE_REF,When 1 Select Audio CLK as a reference [HDMI] When 0 Select LANE CLK as a reference [DP]" "0,1" newline bitfld.long 0x0 2. "I2S_SEL_EXTERNAL,When 1 Select external values of NMAUD [N/A] for I2S" "0,1" newline bitfld.long 0x0 1. "SPDIF_SEL_EXTERNAL,When 1 Select external values of NMAUD [N/A] for SPDIF" "0,1" newline bitfld.long 0x0 0. "NMVID_SEL_EXTERNAL,When 1 Select external values of NMVID [N/A]" "0,1" rgroup.long 0xC++0x3 line.long 0x0 "V2A__CORE_VP__REGS_APB_CM_VID_CTRL_p,Video clock control" hexmask.long.byte 0x0 28.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.byte 0x0 24.--27. 1. "NMVID_MEAS_TOLERANCE,Video measurement tolerance in pixel clock cycles" newline hexmask.long.tbyte 0x0 0.--23. 1. "NMVID_REF_CYC,Video Reference cycles" rgroup.long 0x24++0x7 line.long 0x0 "V2A__CORE_VP__REGS_APB_NMVID_MEAS_STABLE_p,Video clock stable" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline rbitfld.long 0x0 0. "ST_NMVID_MEAS_STABLE,Pixel clock NMVID measurement stable" "0,1" line.long 0x4 "V2A__CORE_VP__REGS_APB_CM_VID_MEAS_p,Video cycles measure" hexmask.long.byte 0x4 25.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x4 24. "NMVID_MEAS_VALID_INDC,When Toggle Valid pulse is generated to sample MNVID fix value" "0,1" newline hexmask.long.tbyte 0x4 0.--23. 1. "NMVID_MEAS_CYC,Fixed Value for NVID The MVID is nmvid_ref_cyc[23:0]" rgroup.long 0x38++0x3 line.long 0x0 "V2A__CORE_VP__REGS_APB_NMVID_MEAS_p,Video clock measurement" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.tbyte 0x0 0.--23. 1. "NMVID_MEAS,Video clock measurement value" rgroup.long 0x0++0x17 line.long 0x0 "V2A__CORE_VP__REGS_APB_BND_HSYNC2VSYNC_p,Video Input Interface Setting Register" hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x0 14. "IP_VIF_ALIGNMENT,Alignment of the input pixel data at the pixel interface: 0-MSB alignment 1-LSB alignment." "0: MSB alignment 1-LSB alignment,?" newline bitfld.long 0x0 13. "IP_VIF_BYPASS,Bypass video interface." "0,1" newline bitfld.long 0x0 12. "IP_DET_EN,Enable detection of Interlace formats after decided if the polarity is Automatic or Manual detection." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "IP_DTCT_WIN,Bound for HSYNC to VSYNC for all fields." line.long 0x4 "V2A__CORE_VP__REGS_APB_HSYNC2VSYNC_F1_L1_p,Status of HSYNC to VSYNC Distance Counter 1." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.word 0x4 0.--15. 1. "IP_DTCT_HSYNC2VSYNC_F1,Value of HSYNC to VSYNC field 1." line.long 0x8 "V2A__CORE_VP__REGS_APB_HSYNC2VSYNC_F2_L1_p,Status of HSYNC to VSYNC Distance Counter 2" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.word 0x8 0.--15. 1. "IP_DTCT_HSYNC2VSYNC_F2,Value of HSYNC to VSYNC field 2." line.long 0xC "V2A__CORE_VP__REGS_APB_HSYNC2VSYNC_STATUS_p,Video Interface Status Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline rbitfld.long 0xC 3. "IP_DTCT_HJITTER,Asserted when jitter is observed on htotal i.e. HSYNC rising edge to next HSYNC rising edge delay count. Clear on Read." "0,1" newline rbitfld.long 0xC 2. "IP_DTCT_VJITTER,Asserted when jitter is observed on vtotal i.e. VSYNC rising edge to next VSYNC rising edge delay count. Clear on Read." "0,1" newline rbitfld.long 0xC 1. "IP_DCT_IP,When asserted interlaced format is detected else progressive format." "0,1" newline rbitfld.long 0xC 0. "IP_DTCT_ERR,Asserted when HSYNC to VSYNC bound is violated. Clear on Read." "0,1" line.long 0x10 "V2A__CORE_VP__REGS_APB_HSYNC2VSYNC_POL_CTRL_p,Setting Polarity of HSYNC and VSYNC" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x10 2. "VPOL,VSYNC polarity: 0-active HIGH 1-active LOW." "0: active HIGH 1-active LOW,?" newline bitfld.long 0x10 1. "HPOL,HSYNC polarity: 0-active HIGH 1-active LOW." "0: active HIGH 1-active LOW,?" newline bitfld.long 0x10 0. "VIF_AUTO_MODE,Automatic or Manual configuration of the polarity: 0-vpol and hpol settings are used 1-automatic detection of polarity of input VSYNC and HSYNC" "0: vpol and hpol settings are used 1-automatic..,?" line.long 0x14 "V2A__CORE_VP__REGS_APB_DSC_CTRL_p,DSC Setting Register" hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x14 2. "DSC_REG_UPDATE,DSC registers update: active HIGH." "0,1" newline bitfld.long 0x14 1. "DSC_SW_RST,DSC software reset: active HIGH." "0,1" newline bitfld.long 0x14 0. "DSC_EN,DSC enable bit: 1-DSC is enabled 0-DSC is disabled" "?,1: DSC is enabled 0-DSC is disabled" rgroup.long 0x0++0x3F line.long 0x0 "V2A__CORE_VP__REGS_APB_MSA_HORIZONTAL_0_p,MSA horizontal parameters. This settings define MSA content (not used for input video stream parameters). This field must be set prior video is enabled and must not be changed when video transmission is active." hexmask.long.word 0x0 16.--31. 1. "PCK_STUFF_HSTART,MSA Hstart value. Horizontal active start from leading edge of Hsync measured in pixel count." newline hexmask.long.word 0x0 0.--15. 1. "PCK_STUFF_HTOTAL,MSA HTotal value. Horizontal total of transmitted main video stream measured in pixel count." line.long 0x4 "V2A__CORE_VP__REGS_APB_MSA_HORIZONTAL_1_p,MSA horizontal parameters. This settings define MSA content (not used for input video stream parameters). This field must be set prior video is enabled and must not be changed when video transmission is active." hexmask.long.word 0x4 16.--31. 1. "PCK_STUFF_HWIDTH,MSA Hwidth parameter. Active video width measured in pixel count." newline bitfld.long 0x4 15. "PCK_STUFF_HSYNCPOLARITY,MSA HSync Polarity. 0 - Active high pulse. Synchronization signal is high for the sync pulse width. 1 - Active low pulse. Synchronization signal is low for the sync pulse width. This value may be different than actual polarity.." "0: Active high pulse,1: Active low pulse" newline hexmask.long.word 0x4 0.--14. 1. "PCK_STUFF_HSYNCWIDTH,MSA HSyncWidth parameter. Hsync width measured in pixel count." line.long 0x8 "V2A__CORE_VP__REGS_APB_MSA_VERTICAL_0_p,MSA vertical parameters. This settings define MSA content (not used for input video stream parameters). This field must be set prior video is enabled and must not be changed when video transmission is active." hexmask.long.word 0x8 16.--31. 1. "PCK_STUFF_VSTART,MSA Vstart parameter. Vertical active start from leading edge of Vsync measured in line count." newline hexmask.long.word 0x8 0.--15. 1. "PCK_STUFF_VTOTAL,MSA Vtotal parameter. Vertical total of transmitted main video stream measured in line count." line.long 0xC "V2A__CORE_VP__REGS_APB_MSA_VERTICAL_1_p,MSA vertical parameters. This settings define MSA content (not used for input video stream parameters). This field must be set prior video is enabled and must not be changed when video transmission is active." hexmask.long.word 0xC 16.--31. 1. "PCK_STUFF_VHEIGHT,MSA VHeigh parameter. Active video height measured in line count." newline bitfld.long 0xC 15. "PCK_STUFF_VSYNCPOLARITY,MSA VSyncPolarity. 0 - Active high pulse. Synchronization signal is high for the sync pulse width. 1 - Active low pulse. Synchronization signal is low for the sync pulse width. This value may be different than actual polarity.." "0: Active high pulse,1: Active low pulse" newline hexmask.long.word 0xC 0.--14. 1. "PCK_STUFF_VSYNCWIDTH,MSA VSyncWidth parameter. Vsync width measured in line count." line.long 0x10 "V2A__CORE_VP__REGS_APB_MSA_MISC_p,MSA MISC0 and MISC1 control register. This field must be set prior video is enabled and must not be changed when video transmission is active." hexmask.long.word 0x10 18.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x10 17. "MSA_IN_MID_INTERLACE_EN,MSA transmission control in interlaced mode. 0 - enable transmission of MSA on each field 1 - MSA transmitted on Top only" "0: enable transmission of MSA on each field,1: MSA transmitted on Top only" newline bitfld.long 0x10 16. "MSA_MISC1_INV,L/R toggle for interlaced and field sequential video. 0 - left 1 - right" "0: left 1,?" newline hexmask.long.byte 0x10 8.--15. 1. "MSA_MISC1,MAS Miscellaneous1 as described in DisplayPort specification." newline hexmask.long.byte 0x10 0.--7. 1. "MSA_MISC0,MSA Miscellaneous0 as described in DisplayPort specification." line.long 0x14 "V2A__CORE_VP__REGS_APB_STREAM_CONFIG_p,Stream configuration register. Used only in MST mode." hexmask.long 0x14 2.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x14 1. "NO_VIDEO,Stream no video mode. 0 - video mode 1 - no video mode" "0: video mode 1,?" newline bitfld.long 0x14 0. "STREAM_EN,Stream enable. 0 - stream disabled 1 - stream enabled" "0: stream disabled 1,?" line.long 0x18 "V2A__CORE_VP__REGS_APB_AUDIO_PACK_STATUS_p,Status signals for the audio pack." hexmask.long.word 0x18 22.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.byte 0x18 16.--21. 1. "AUDIO_TS_VERSION,Audio timestamp version. This field is transmitted in HB3[7:2] of a Audio_TimeStamp SDP Header." newline bitfld.long 0x18 13.--15. "RESERVED,Reserved. Writes are ignored. 0x0 when read." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 10.--12. "AP_PARITY_FSM_CURRENT_STATE,Audio pack parity calc fsm state. Used only for debug purposes." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 8.--9. "AP_FIFO_WR_FSM_CURR_ST,Audio pack FIFO write fsm state. Used only for debug purposes." "0,1,2,3" newline rbitfld.long 0x18 6.--7. "AP_FIFO_RD_FSM_CURR_ST,Audio pack FIFO read fsm state. Used only for debug purposes." "0,1,2,3" newline rbitfld.long 0x18 3.--5. "AP_SDP_TRANSFER_FSM_CURR_ST,Audio pack sdp transfer fsm state. Used only for debug purposes." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 2. "AP_AIF_FSM_CURR_ST,Audio pack aif fsm state. Used only for debug purposes." "0,1" newline rbitfld.long 0x18 1. "AP_FIFO_FULL,Audio Pack Sync FIFO full flag active high. Used only for debug purposes." "0,1" newline rbitfld.long 0x18 0. "AP_FIFO_EMPTY,Audio Pack Sync FIFO empty flag active high. Used only for debug purposes." "0,1" line.long 0x1C "V2A__CORE_VP__REGS_APB_VIF_STATUS_p,Status signals for the VIF module. Used only for debug purposes." hexmask.long.byte 0x1C 28.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.tbyte 0x1C 8.--27. 1. "VIF_RD_CTRL_STATE,VIF rd fsm current state." newline hexmask.long.byte 0x1C 2.--7. 1. "VIF_WR_CTRL_STATE,VIF wr fsm current state." newline rbitfld.long 0x1C 1. "VIF_FIFO_FULL,VIF ASync FIFO full flag active high." "0,1" newline rbitfld.long 0x1C 0. "VIF_FIFO_EMPTY,VIF ASync FIFO empty flag active high." "0,1" line.long 0x20 "V2A__CORE_VP__REGS_APB_PCK_STUFF_STATUS_0_p,Status of the the video stuff module (0). Used only for debug purposes." bitfld.long 0x20 31. "RESERVED,Reserved. Writes are ignored. 0x0 when read." "0,1" newline hexmask.long.byte 0x20 24.--30. 1. "MSA_GEN_STATE,Secondary Data generator FSM status." newline hexmask.long.byte 0x20 16.--23. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x20 15. "RESERVED,Reserved. Writes are ignored. 0x0 when read." "0,1" newline hexmask.long.byte 0x20 8.--14. 1. "SST_VIDEO_GEN_STATE,SST video generator FSM status." newline bitfld.long 0x20 5.--7. "RESERVED,Reserved. Writes are ignored. 0x0 when read." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x20 0.--4. 1. "NO_VIDEO_GEN_STATE,No video generator FSM status." line.long 0x24 "V2A__CORE_VP__REGS_APB_PCK_STUFF_STATUS_1_p,Status of the the video stuff module (1). Used only for debug purposes." hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x24 6.--7. "RESERVED,Reserved. Writes are ignored. 0x0 when read." "0,1,2,3" newline hexmask.long.byte 0x24 0.--5. 1. "SST_SS_GEN_STATE,MSA generator FSM status." line.long 0x28 "V2A__CORE_VP__REGS_APB_INFO_PACK_STATUS_p,Status signals for the info pack module. as well as final VB-ID value. Used only for debug purposes." hexmask.long.byte 0x28 24.--31. 1. "IN_VBID,Value of the sent VB-ID [vb_id_final]." newline hexmask.long.byte 0x28 16.--23. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.byte 0x28 12.--15. 1. "IP_SEND_DATA_FSM_CURRENT_STATE,State of the send_data FSM." newline hexmask.long.byte 0x28 8.--11. 1. "IP_FIFO_RD_FSM_CURRENT_STATE,State of the fifo_rd FSM." newline rbitfld.long 0x28 5.--7. "IP_FIFO_WR_FSM_CURRENT_STATE,State of the fifo_wr FSM." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x28 2.--4. "IP_PARITY_FSM_CURRENT_STATE,State of the parity FSM." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x28 1. "INFO_PACK_FIFO_EMPTY,Info_pack fifo empty flag active high." "0,1" newline rbitfld.long 0x28 0. "INFO_PACK_FIFO_FULL,Info_pack fifo full flag active high." "0,1" line.long 0x2C "V2A__CORE_VP__REGS_APB_STREAM_CONFIG_2_p,Additional video stream configuration. Used for debug purposes or for non-standard video formats." hexmask.long.byte 0x2C 25.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x2C 24. "CFG_EN_HSYNC_DELAY,Unused. Kept RW for software backward compatibility." "0,1" newline hexmask.long.byte 0x2C 16.--23. 1. "CFG_HSYNC_DELAY,Unused. Kept RW for software backward compatibility." newline hexmask.long.byte 0x2C 10.--15. 1. "MST_SF_EVAL_VAL_SYM,Number of valid symbols to output during stream fill evaluation period. This should be less than mst_sf_eval_period." newline bitfld.long 0x2C 8.--9. "CFG_TU_VS_DIFF,Unused. Kept RW for software backward compatibility." "0,1,2,3" newline bitfld.long 0x2C 7. "MST_SF_EVAL_OVR_EN,Enable override of mst_sf_eval_period mst_sf_eval_val_sym and cfg_tu_vs_diff when in MST mode." "0,1" newline hexmask.long.byte 0x2C 0.--6. 1. "MST_SF_EVAL_PERIOD,Stream fill evaluation period when in MST mode and mst_sf_eval_ovr_en bit is set." line.long 0x30 "V2A__CORE_VP__REGS_APB_DP_HORIZONTAL_p,Video Horizontal parameters. This register must be programmed prior enabling video and must not be changed while video is being transmitted." hexmask.long.word 0x30 16.--31. 1. "HWIDTH,Horizontal Active Video Width. Width of video active period [VACTIVE] expressed in number pixel clock cycles. It must be a multiply of 16." newline bitfld.long 0x30 15. "RESERVED,Reserved. Writes are ignored. 0x0 when read." "0,1" newline hexmask.long.word 0x30 0.--14. 1. "HSYNCWIDTH,Horizontal Sync Width. Width of horizontal synchronization pulse [HSYNC] expressed in number pixel clock cycles." line.long 0x34 "V2A__CORE_VP__REGS_APB_DP_VERTICAL_0_p,Video Vertical parameters. This register must be programmed prior enabling video and must not be changed while video is being transmitted." hexmask.long.word 0x34 16.--31. 1. "VSTART,Vertical Active Start [VSTART]. Index of the first active line in a video frame." newline hexmask.long.word 0x34 0.--15. 1. "VHEIGHT,Vertical Active High [VACTIVE]. Number of active lines in a video frame." line.long 0x38 "V2A__CORE_VP__REGS_APB_DP_VERTICAL_1_p,Video Vertical parameters. This register must be programmed prior enabling video and must not be changed while video is being transmitted." hexmask.long.word 0x38 17.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x38 16. "VTOTAL_EVEN,Indicate Vtotal is an even number as described in MISC1[0] in DisplayPort specification. Active high." "0,1" newline hexmask.long.word 0x38 0.--15. 1. "VTOTAL,Vertical Total Heigh [HTOTAL]. Total number of lines per frame." line.long 0x3C "V2A__CORE_VP__REGS_APB_DP_BLOCK_SDP_p,SDP scheduling control register. Allows for tuning when SDP can be sent during blanking periods. This register must be programmed prior enabling video and must not be changed while video is being transmitted." bitfld.long 0x3C 31. "BS_SDP_STOP_OVR_EN,Enable override settings. If this bit is not set the hardware will not automatically block SDP transmission during video lines this may result in shifting of video timing." "0,1" newline hexmask.long.word 0x3C 16.--30. 1. "BS_SDP_STOP_ACTIVE,Block SDP scheduling after specified cycles after BS during horizontal blank lines. Maximum is 32767. If set to 0 no SDPs will be transmitted during hblank. Only used when bs_sdp_stop_ovr_en is set to 1." newline hexmask.long.word 0x3C 0.--15. 1. "BS_SDP_STOP_BLANK,Block SDP scheduling after specified cycles after BS during vertical blank lines. Maximum is 65535. If set to 0 no SDPs will be transmitted during vblank. Only used when bs_sdp_stop_ovr_en is set to 1." rgroup.long 0x44++0x13 line.long 0x0 "V2A__CORE_VP__REGS_APB_DP_MST_SLOT_ALLOCATE_p,Stream slots allocation in MST mode. This register defines slots in the MTP assigned to a given stream. All slots between start and and are assigned to the stream. Assignement of noncontiguous slots to a.." hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.byte 0x0 8.--13. 1. "STREAM_END_SLOT,Stream end slot. This value determines last slot in MTP assigned to a given stream. Allowed values are stream_start_slot-63." newline bitfld.long 0x0 6.--7. "RESERVED,Reserved. Writes are ignored. 0x0 when read." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "STREAM_START_SLOT,Stream start slot. This value determines first slot in MTP assigned to a given stream. Allowed values are 1-63." line.long 0x4 "V2A__CORE_VP__REGS_APB_RATE_GOVERNING_CTRL_p,Control rate governing for stream in MST mode." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x4 10. "RATE_GOV_EN,Enable rate governing. When set to 0 this stream will only output VCPF" "0,1" newline hexmask.long.byte 0x4 4.--9. 1. "TARG_AV_SLOTS_X,Target average number of slots per MTP configuration" newline hexmask.long.byte 0x4 0.--3. 1. "TARG_AV_SLOTS_Y,Target average number of slots per MTP configuration. Fractional component" line.long 0x8 "V2A__CORE_VP__REGS_APB_DP_FRAMER_PXL_REPR_p,Video pixel format configuration. This register must be programmed prior enabling video and must not be changed while video is being transmitted." bitfld.long 0x8 31. "RESERVED,Reserved. Writes are ignored. 0x0 when read." "0,1" newline hexmask.long.byte 0x8 24.--30. 1. "DIFF,Difference between Denominator and Numerator of the ratio that describes valid symbols distribution. Example: If TU_VALID*=12.34 then DIFF=100-34=66. TU_VALID calculated according to DisplayPort specification. This setting apply only when.." newline bitfld.long 0x8 23. "RESERVED,Reserved. Writes are ignored. 0x0 when read." "0,1" newline hexmask.long.byte 0x8 16.--22. 1. "M,Numerator of the ratio that describes valid symbols distribution. Example: If TU_VALID=12.34 then M=34. TU_VALID calculated according to DisplayPort specification. This setting apply only when compressed [DSC] stream is being transmitted." newline bitfld.long 0x8 13.--15. "RESERVED,Reserved. Writes are ignored. 0x0 when read." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--12. 1. "PXL_ENC_FORMAT,Pixel encoding format: 1h - RGB 2h - YCbCr 4:4:4 4h - YCbCr 4:2:2 8h - Y CbCr 4:2:0 10h - Y-only All other values - RESERVED" newline bitfld.long 0x8 5.--7. "RESERVED,Reserved. Writes are ignored. 0x0 when read." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--4. 1. "COLOR_DEPTH,Color depth: 1h - 6 bpc 2h - 8 bpc 4h - 10 bpc 8h - 12 bpc 10h - 16 bpc All other values - RESERVED" line.long 0xC "V2A__CORE_VP__REGS_APB_DP_FRAMER_SP_p,Synchronization signals polarity and 3D control. This register must be programmed prior enabling video and must not be changed while video is being transmitted." hexmask.long 0xC 5.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0xC 4. "STACKED_3D_EN,Unused. Kept RW for software backward compatibility." "0,1" newline bitfld.long 0xC 3. "FRAMER_3D_EN,3D video enable active high. This bit must be set when 3D Field Sequencial Stereo Format is enabled. Other 3D formats do not require setting this bit." "0,1" newline bitfld.long 0xC 2. "INTERLACE_EN,Interlaced video enable. Active high." "0,1" newline bitfld.long 0xC 1. "HSP,Video interface HSYNC polarity: 0 - active high 1 - active low" "0: active high,1: active low" newline bitfld.long 0xC 0. "VSP,Video interface VSYNC polarity: 0 - active high 1 - active low" "0: active high,1: active low" line.long 0x10 "V2A__CORE_VP__REGS_APB_AUDIO_PACK_CONTROL_p,Audio packet configuration." hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline bitfld.long 0x10 9. "MONO,In case of 2-channel layout and one lane configuration SW decides whether it is a stereo or mono transfer. Relevant for SDP HB3[2:0] - ChannelCount field" "0,1" newline bitfld.long 0x10 8. "AUDIO_PACK_EN,Enables the Audio_Pack module active high" "0,1" newline hexmask.long.byte 0x10 0.--7. 1. "MST_SDP_ID,Secondary-Data Packet ID. This field is transmitted in HB0 of the Audio SDP [Audio_TimeStamp and Audio_Stream]." rgroup.long 0x64++0xB line.long 0x0 "V2A__CORE_VP__REGS_APB_LINE_THRESH_p,Video FIFO latency threshold" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.byte 0x0 0.--5. 1. "CFG_ACTIVE_LINE_TRESH,Video Fifo Latency threshold. Defines the number of FIFO rows before reading starts. This setting depends on the transmitted video format and link rate." line.long 0x4 "V2A__CORE_VP__REGS_APB_DP_VB_ID_p,Vertical blanking ID" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read." newline hexmask.long.byte 0x4 0.--7. 1. "VB_ID,VB-ID as described in the DisplayPort specification. Bits that are timing dependent [VerticalBlanking_Flag FieldID_Flag HDCP SYNC DETECT Compressed Stream_Flag] are overriden by hardware thus actual value written to the register is ignored." line.long 0x8 "V2A__CORE_VP__REGS_APB_DP_FIELDSEQ_3D_p,Supporting configuration to switch from top/bottom on the input to field sequential on the output" hexmask.long.word 0x8 16.--31. 1. "FIELD_SEQ_END,Number of line in the frame where the Vblank part in the field sequential format ends" newline hexmask.long.word 0x8 0.--15. 1. "FIELD_SEQ_START,Number of line in the frame where the Vblank part in the field sequential format starts" rgroup.long 0x78++0x7 line.long 0x0 "V2A__CORE_VP__REGS_APB_DP_FRONT_BACK_PORCH_p,Front and Back Porch configuration register." hexmask.long.word 0x0 16.--31. 1. "FRONT_PORCH,Value of the front porch" newline hexmask.long.word 0x0 0.--15. 1. "BACK_PORCH,Value of the back porch" line.long 0x4 "V2A__CORE_VP__REGS_APB_DP_BYTE_COUNT_p,Number of bytes per lane/chunk parameters" hexmask.long.word 0x4 16.--31. 1. "BYTES_IN_CHUNK,Number of bytes in chunk per lane including additional EOC symbol." newline hexmask.long.word 0x4 0.--15. 1. "BYTE_COUNT,Total number of bytes in a line in case of non-DSC video. When DSC is enabled should be total number of bytes in a line *per lane* including the additional EOC symbol[s]." rgroup.long 0x0++0x4F line.long 0x0 "V2A__CORE_VP__REGS_APB_AUDIO_SRC_CNTL_p,Audio source control" hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x0 6. "VALID_ALL,valid bit for all samples" "0,1" newline bitfld.long 0x0 5. "VALID_BITS_FORCE,Force valid bits of the channels" "0,1" newline bitfld.long 0x0 4. "I2S_TS_EN,Enable I2S Time Stamp when decoders are disabled" "0,1" newline bitfld.long 0x0 3. "SPDIF_TS_EN,Enable SPDIF Time Stamp when decoders are disabled" "0,1" newline bitfld.long 0x0 2. "I2S_BLOCK_START_FORCE,Force a Block Start in the audio stream" "0,1" newline bitfld.long 0x0 1. "I2S_DEC_START,When high Source Decoder starts." "0,1" newline bitfld.long 0x0 0. "SW_RST,Software reset. Active high." "0,1" line.long 0x4 "V2A__CORE_VP__REGS_APB_AUDIO_SRC_CNFG_p,Audio source configuration" hexmask.long.word 0x4 21.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x4 17.--20. 1. "I2S_DEC_PORT_EN,Enables the I2S Decoder ports. Allowed values are: 0001 - I2S port 0 is enabled. 0011 - I2S ports 0 1 are enabled. 1111 - I2S ports 0 1 2 3 are enabled. No other values are allowed." newline hexmask.long.byte 0x4 13.--16. 1. "AUDIO_CHANNEL_TYPE,Set the transmission type." newline bitfld.long 0x4 11.--12. "TRANS_SMPL_WIDTH,Decoder Word Select width: 00-16 bit 01-24 bit 10-32 bit" "0,1,2,3" newline bitfld.long 0x4 9.--10. "AUDIO_SAMPLE_WIDTH,Decoder sample width: 00-16 bit 01-24 bit 10-32 bit" "0,1,2,3" newline bitfld.long 0x4 7.--8. "AUDIO_SAMPLE_JUST,Data justification setting: 00 left-justified 01 right-justified" "0,1,2,3" newline hexmask.long.byte 0x4 2.--6. 1. "AUDIO_CH_NUM,Number of channels to decode" newline bitfld.long 0x4 1. "WS_POLARITY,Word Select Polarity. 0: No change 1: Inverted." "0: No change,1: Inverted" newline bitfld.long 0x4 0. "LOW_INDEX_MSB,When low MSB is transmitted first. When high LSB is transmitted first." "0,1" line.long 0x8 "V2A__CORE_VP__REGS_APB_COM_CH_STTS_BITS_p,Common channels configuration" hexmask.long.byte 0x8 28.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x8 24.--27. 1. "ORIGINAL_SAMP_FREQ,Original Sampling Freq. of transmitted channel. Same for all channels." newline hexmask.long.byte 0x8 20.--23. 1. "CLOCK_ACCURACY,Clock Accuracy of transmitted channel. Same for all channels." newline hexmask.long.byte 0x8 16.--19. 1. "SAMPLING_FREQ,Sampling Frequency of transmitted channel. Same for all channels." newline hexmask.long.byte 0x8 8.--15. 1. "CATEGORY_CODE,Category Code of transmitted channel. Same for all channels." newline hexmask.long.byte 0x8 0.--7. 1. "BYTE0,Byte 0 of transmitted channel. Same for all channels." line.long 0xC "V2A__CORE_VP__REGS_APB_STTS_BIT_CH01_p,Channels 0.1 configuration" hexmask.long.byte 0xC 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0xC 24.--25. "VALID_BITS1_0,Valid Bits for channel 1 and 0 if force is enabled" "0,1,2,3" newline hexmask.long.byte 0xC 20.--23. 1. "WORD_LENGTH_CH1,Channel 1 word length." newline hexmask.long.byte 0xC 16.--19. 1. "CHANNEL_NUM_CH1,Channel 1 channel number." newline hexmask.long.byte 0xC 12.--15. 1. "SOURCE_NUM_CH1,Channel 1 Source number." newline hexmask.long.byte 0xC 8.--11. 1. "WORD_LENGTH_CH0,Channel 0 word length." newline hexmask.long.byte 0xC 4.--7. 1. "CHANNEL_NUM_CH0,Channel 0 channel number." newline hexmask.long.byte 0xC 0.--3. 1. "SOURCE_NUM_CH0,Channel 0 Source number." line.long 0x10 "V2A__CORE_VP__REGS_APB_STTS_BIT_CH23_p,Channels 2.3 configuration" hexmask.long.byte 0x10 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x10 24.--25. "VALID_BITS3_2,Valid Bits for channel 3 and 2 if force is enabled" "0,1,2,3" newline hexmask.long.byte 0x10 20.--23. 1. "WORD_LENGTH_CH3,Channel 3 word length." newline hexmask.long.byte 0x10 16.--19. 1. "CHANNEL_NUM_CH3,Channel 3 channel number." newline hexmask.long.byte 0x10 12.--15. 1. "SOURCE_NUM_CH3,Channel 3 Source number." newline hexmask.long.byte 0x10 8.--11. 1. "WORD_LENGTH_CH2,Channel 2 word length." newline hexmask.long.byte 0x10 4.--7. 1. "CHANNEL_NUM_CH2,Channel 2 channel number." newline hexmask.long.byte 0x10 0.--3. 1. "SOURCE_NUM_CH2,Channel 2 Source number." line.long 0x14 "V2A__CORE_VP__REGS_APB_STTS_BIT_CH45_p,Channels 4.5 configuration" hexmask.long.byte 0x14 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x14 24.--25. "VALID_BITS5_4,Valid Bits for channel 5 and 4 if force is enabled" "0,1,2,3" newline hexmask.long.byte 0x14 20.--23. 1. "WORD_LENGTH_CH5,Channel 5 word length." newline hexmask.long.byte 0x14 16.--19. 1. "CHANNEL_NUM_CH5,Channel 5 channel number." newline hexmask.long.byte 0x14 12.--15. 1. "SOURCE_NUM_CH5,Channel 5 Source number." newline hexmask.long.byte 0x14 8.--11. 1. "WORD_LENGTH_CH4,Channel 4 word length." newline hexmask.long.byte 0x14 4.--7. 1. "CHANNEL_NUM_CH4,Channel 4 channel number." newline hexmask.long.byte 0x14 0.--3. 1. "SOURCE_NUM_CH4,Channel 4 Source number." line.long 0x18 "V2A__CORE_VP__REGS_APB_STTS_BIT_CH67_p,Channels 6.7 configuration" hexmask.long.byte 0x18 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x18 24.--25. "VALID_BITS7_6,Valid Bits for channel 7 and 6 if force is enabled" "0,1,2,3" newline hexmask.long.byte 0x18 20.--23. 1. "WORD_LENGTH_CH7,Channel 7 word length." newline hexmask.long.byte 0x18 16.--19. 1. "CHANNEL_NUM_CH7,Channel 7 channel number." newline hexmask.long.byte 0x18 12.--15. 1. "SOURCE_NUM_CH7,Channel 7 Source number." newline hexmask.long.byte 0x18 8.--11. 1. "WORD_LENGTH_CH6,Channel 6 word length." newline hexmask.long.byte 0x18 4.--7. 1. "CHANNEL_NUM_CH6,Channel 6 channel number." newline hexmask.long.byte 0x18 0.--3. 1. "SOURCE_NUM_CH6,Channel 6 Source number." line.long 0x1C "V2A__CORE_VP__REGS_APB_STTS_BIT_CH89_p,Channels 8.9 configuration" hexmask.long.byte 0x1C 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x1C 24.--25. "VALID_BITS9_8,Valid Bits for channel 9 and 8 if force is enabled" "0,1,2,3" newline hexmask.long.byte 0x1C 20.--23. 1. "WORD_LENGTH_CH9,Channel 9 word length." newline hexmask.long.byte 0x1C 16.--19. 1. "CHANNEL_NUM_CH9,Channel 9 channel number." newline hexmask.long.byte 0x1C 12.--15. 1. "SOURCE_NUM_CH9,Channel 9 Source number." newline hexmask.long.byte 0x1C 8.--11. 1. "WORD_LENGTH_CH8,Channel 8 word length." newline hexmask.long.byte 0x1C 4.--7. 1. "CHANNEL_NUM_CH8,Channel 8 channel number." newline hexmask.long.byte 0x1C 0.--3. 1. "SOURCE_NUM_CH8,Channel 8 Source number." line.long 0x20 "V2A__CORE_VP__REGS_APB_STTS_BIT_CH1011_p,Channels 10.11 configuration" hexmask.long.byte 0x20 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x20 24.--25. "VALID_BITS11_10,Valid Bits for channel 11 and 10 if force is enabled" "0,1,2,3" newline hexmask.long.byte 0x20 20.--23. 1. "WORD_LENGTH_CH11,Channel 11 word length." newline hexmask.long.byte 0x20 16.--19. 1. "CHANNEL_NUM_CH11,Channel 11 channel number." newline hexmask.long.byte 0x20 12.--15. 1. "SOURCE_NUM_CH11,Channel 11 Source number." newline hexmask.long.byte 0x20 8.--11. 1. "WORD_LENGTH_CH10,Channel 10 word length." newline hexmask.long.byte 0x20 4.--7. 1. "CHANNEL_NUM_CH10,Channel 10 channel number." newline hexmask.long.byte 0x20 0.--3. 1. "SOURCE_NUM_CH10,Channel 10 Source number." line.long 0x24 "V2A__CORE_VP__REGS_APB_STTS_BIT_CH1213_p,Channels 12.13 configuration" hexmask.long.byte 0x24 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x24 24.--25. "VALID_BITS13_12,Valid Bits for channel 13 and 12 if force is enabled" "0,1,2,3" newline hexmask.long.byte 0x24 20.--23. 1. "WORD_LENGTH_CH13,Channel 13 word length." newline hexmask.long.byte 0x24 16.--19. 1. "CHANNEL_NUM_CH13,Channel 13 channel number." newline hexmask.long.byte 0x24 12.--15. 1. "SOURCE_NUM_CH13,Channel 13 Source number." newline hexmask.long.byte 0x24 8.--11. 1. "WORD_LENGTH_CH12,Channel 12 word length." newline hexmask.long.byte 0x24 4.--7. 1. "CHANNEL_NUM_CH12,Channel 12 channel number." newline hexmask.long.byte 0x24 0.--3. 1. "SOURCE_NUM_CH12,Channel 12 Source number." line.long 0x28 "V2A__CORE_VP__REGS_APB_STTS_BIT_CH1415_p,Channels 14.15 configuration" hexmask.long.byte 0x28 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x28 24.--25. "VALID_BITS15_14,Valid Bits for channel 15 and 14 if force is enabled" "0,1,2,3" newline hexmask.long.byte 0x28 20.--23. 1. "WORD_LENGTH_CH15,Channel 15 word length." newline hexmask.long.byte 0x28 16.--19. 1. "CHANNEL_NUM_CH15,Channel 15 channel number." newline hexmask.long.byte 0x28 12.--15. 1. "SOURCE_NUM_CH15,Channel 15 Source number." newline hexmask.long.byte 0x28 8.--11. 1. "WORD_LENGTH_CH14,Channel 14 word length." newline hexmask.long.byte 0x28 4.--7. 1. "CHANNEL_NUM_CH14,Channel 14 channel number." newline hexmask.long.byte 0x28 0.--3. 1. "SOURCE_NUM_CH14,Channel 14 Source number." line.long 0x2C "V2A__CORE_VP__REGS_APB_STTS_BIT_CH1617_p,Channels 16.17 configuration" hexmask.long.byte 0x2C 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x2C 24.--25. "VALID_BITS17_16,Valid Bits for channel 17 and 16 if force is enabled" "0,1,2,3" newline hexmask.long.byte 0x2C 20.--23. 1. "WORD_LENGTH_CH17,Channel 17 word length." newline hexmask.long.byte 0x2C 16.--19. 1. "CHANNEL_NUM_CH17,Channel 17 channel number." newline hexmask.long.byte 0x2C 12.--15. 1. "SOURCE_NUM_CH17,Channel 17 Source number." newline hexmask.long.byte 0x2C 8.--11. 1. "WORD_LENGTH_CH16,Channel 16 word length." newline hexmask.long.byte 0x2C 4.--7. 1. "CHANNEL_NUM_CH16,Channel 16 channel number." newline hexmask.long.byte 0x2C 0.--3. 1. "SOURCE_NUM_CH16,Channel 16 Source number." line.long 0x30 "V2A__CORE_VP__REGS_APB_STTS_BIT_CH1819_p,Channels 18.19 configuration" hexmask.long.byte 0x30 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x30 24.--25. "VALID_BITS19_18,Valid Bits for channel 19 and 18 if force is enabled" "0,1,2,3" newline hexmask.long.byte 0x30 20.--23. 1. "WORD_LENGTH_CH19,Channel 19 word length." newline hexmask.long.byte 0x30 16.--19. 1. "CHANNEL_NUM_CH19,Channel 19 channel number." newline hexmask.long.byte 0x30 12.--15. 1. "SOURCE_NUM_CH19,Channel 19 Source number." newline hexmask.long.byte 0x30 8.--11. 1. "WORD_LENGTH_CH18,Channel 18 word length." newline hexmask.long.byte 0x30 4.--7. 1. "CHANNEL_NUM_CH18,Channel 18 channel number." newline hexmask.long.byte 0x30 0.--3. 1. "SOURCE_NUM_CH18,Channel 18 Source number." line.long 0x34 "V2A__CORE_VP__REGS_APB_STTS_BIT_CH2021_p,Channels 20.21 configuration" hexmask.long.byte 0x34 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x34 24.--25. "VALID_BITS21_20,Valid Bits for channel 21 and 20 if force is enabled" "0,1,2,3" newline hexmask.long.byte 0x34 20.--23. 1. "WORD_LENGTH_CH21,Channel 21 word length." newline hexmask.long.byte 0x34 16.--19. 1. "CHANNEL_NUM_CH21,Channel 21 channel number." newline hexmask.long.byte 0x34 12.--15. 1. "SOURCE_NUM_CH21,Channel 21 Source number." newline hexmask.long.byte 0x34 8.--11. 1. "WORD_LENGTH_CH20,Channel 20 word length." newline hexmask.long.byte 0x34 4.--7. 1. "CHANNEL_NUM_CH20,Channel 20 channel number." newline hexmask.long.byte 0x34 0.--3. 1. "SOURCE_NUM_CH20,Channel 20 Source number." line.long 0x38 "V2A__CORE_VP__REGS_APB_STTS_BIT_CH2223_p,Channels 22.23 configuration" hexmask.long.byte 0x38 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x38 24.--25. "VALID_BITS23_22,Valid Bits for channel 23 and 22 if force is enabled" "0,1,2,3" newline hexmask.long.byte 0x38 20.--23. 1. "WORD_LENGTH_CH23,Channel 23 word length." newline hexmask.long.byte 0x38 16.--19. 1. "CHANNEL_NUM_CH23,Channel 23 channel number." newline hexmask.long.byte 0x38 12.--15. 1. "SOURCE_NUM_CH23,Channel 23 Source number." newline hexmask.long.byte 0x38 8.--11. 1. "WORD_LENGTH_CH22,Channel 22 word length." newline hexmask.long.byte 0x38 4.--7. 1. "CHANNEL_NUM_CH22,Channel 22 channel number." newline hexmask.long.byte 0x38 0.--3. 1. "SOURCE_NUM_CH22,Channel 22 Source number." line.long 0x3C "V2A__CORE_VP__REGS_APB_STTS_BIT_CH2425_p,Channels 24.25 configuration" hexmask.long.byte 0x3C 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x3C 24.--25. "VALID_BITS25_24,Valid Bits for channel 25 and 24 if force is enabled" "0,1,2,3" newline hexmask.long.byte 0x3C 20.--23. 1. "WORD_LENGTH_CH25,Channel 25 word length." newline hexmask.long.byte 0x3C 16.--19. 1. "CHANNEL_NUM_CH25,Channel 25 channel number." newline hexmask.long.byte 0x3C 12.--15. 1. "SOURCE_NUM_CH25,Channel 25 Source number." newline hexmask.long.byte 0x3C 8.--11. 1. "WORD_LENGTH_CH24,Channel 24 word length." newline hexmask.long.byte 0x3C 4.--7. 1. "CHANNEL_NUM_CH24,Channel 24 channel number." newline hexmask.long.byte 0x3C 0.--3. 1. "SOURCE_NUM_CH24,Channel 24 Source number." line.long 0x40 "V2A__CORE_VP__REGS_APB_STTS_BIT_CH2627_p,Channels 26.27 configuration" hexmask.long.byte 0x40 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x40 24.--25. "VALID_BITS27_26,Valid Bits for channel 27 and 26 if force is enabled" "0,1,2,3" newline hexmask.long.byte 0x40 20.--23. 1. "WORD_LENGTH_CH27,Channel 27 word length." newline hexmask.long.byte 0x40 16.--19. 1. "CHANNEL_NUM_CH27,Channel 27 channel number." newline hexmask.long.byte 0x40 12.--15. 1. "SOURCE_NUM_CH27,Channel 27 Source number." newline hexmask.long.byte 0x40 8.--11. 1. "WORD_LENGTH_CH26,Channel 26 word length." newline hexmask.long.byte 0x40 4.--7. 1. "CHANNEL_NUM_CH26,Channel 26 channel number." newline hexmask.long.byte 0x40 0.--3. 1. "SOURCE_NUM_CH26,Channel 26 Source number." line.long 0x44 "V2A__CORE_VP__REGS_APB_STTS_BIT_CH2829_p,Channels 28.29 configuration" hexmask.long.byte 0x44 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x44 24.--25. "VALID_BITS29_28,Valid Bits for channel 29 and 28 if force is enabled" "0,1,2,3" newline hexmask.long.byte 0x44 20.--23. 1. "WORD_LENGTH_CH29,Channel 29 word length." newline hexmask.long.byte 0x44 16.--19. 1. "CHANNEL_NUM_CH29,Channel 29 channel number." newline hexmask.long.byte 0x44 12.--15. 1. "SOURCE_NUM_CH29,Channel 29 Source number." newline hexmask.long.byte 0x44 8.--11. 1. "WORD_LENGTH_CH28,Channel 28 word length." newline hexmask.long.byte 0x44 4.--7. 1. "CHANNEL_NUM_CH28,Channel 28 channel number." newline hexmask.long.byte 0x44 0.--3. 1. "SOURCE_NUM_CH28,Channel 28 Source number." line.long 0x48 "V2A__CORE_VP__REGS_APB_STTS_BIT_CH3031_p,Channels 30.31 configuration" hexmask.long.byte 0x48 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x48 24.--25. "VALID_BITS31_30,Valid Bits for channel 31 and 30 if force is enabled" "0,1,2,3" newline hexmask.long.byte 0x48 20.--23. 1. "WORD_LENGTH_CH31,Channel 31 word length." newline hexmask.long.byte 0x48 16.--19. 1. "CHANNEL_NUM_CH31,Channel 31 channel number." newline hexmask.long.byte 0x48 12.--15. 1. "SOURCE_NUM_CH31,Channel 31 Source number." newline hexmask.long.byte 0x48 8.--11. 1. "WORD_LENGTH_CH30,Channel 30 word length." newline hexmask.long.byte 0x48 4.--7. 1. "CHANNEL_NUM_CH30,Channel 30 channel number." newline hexmask.long.byte 0x48 0.--3. 1. "SOURCE_NUM_CH30,Channel 30 Source number." line.long 0x4C "V2A__CORE_VP__REGS_APB_SPDIF_CTRL_ADDR_p,SPDIF control" hexmask.long.byte 0x4C 26.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x4C 22.--25. 1. "SPDIF_JITTER_STATUS,SPDIF Jitter Status" newline bitfld.long 0x4C 21. "SPDIF_ENABLE,SPDIF Enable" "0,1" newline bitfld.long 0x4C 20. "SPDIF_AVG_SEL,SPDIF average Select" "0,1" newline bitfld.long 0x4C 19. "SPDIF_JITTER_BYPASS,SPDIF Jitter Bypass" "0,1" newline hexmask.long.byte 0x4C 11.--18. 1. "SPDIF_FIFO_MID_RANGE,SPDIF fifo mid range" newline hexmask.long.byte 0x4C 3.--10. 1. "SPDIF_JITTER_THRSH,SPDIF Jitter threshold" newline bitfld.long 0x4C 0.--2. "SPDIF_JITTER_AVG_WIN,Spdif Jitter AVG Window" "0,1,2,3,4,5,6,7" rgroup.long 0x50++0x2F line.long 0x0 "V2A__CORE_VP__REGS_APB_SPDIF_CH1_CS_3100_ADDR_p,SPDIF channel 1 status [31:00]" hexmask.long 0x0 0.--31. 1. "SPDIF_CH1_ST_STTS_BITS3100,SPDIF Channel 1 Status bits[31:0]" line.long 0x4 "V2A__CORE_VP__REGS_APB_SPDIF_CH1_CS_6332_ADDR_p,SPDIF channel 1 status [63:32]" hexmask.long 0x4 0.--31. 1. "SPDIF_CH1_ST_STTS_BITS6332,SPDIF Channel 1 Status bits[63:32]" line.long 0x8 "V2A__CORE_VP__REGS_APB_SPDIF_CH1_CS_9564_ADDR_p,SPDIF channel 1 status [95:64]" hexmask.long 0x8 0.--31. 1. "SPDIF_CH1_ST_STTS_BITS9564,SPDIF Channel 1 Status bits[95:64]" line.long 0xC "V2A__CORE_VP__REGS_APB_SPDIF_CH1_CS_12796_ADDR_p,SPDIF channel 1 status [127:96]" hexmask.long 0xC 0.--31. 1. "SPDIF_CH1_ST_STTS_BITS12796,SPDIF Channel 1 Status bits[127:96]" line.long 0x10 "V2A__CORE_VP__REGS_APB_SPDIF_CH1_CS_159128_ADDR_p,SPDIF channel 1 status [159:128]" hexmask.long 0x10 0.--31. 1. "SPDIF_CH1_ST_STTS_BITS159128,SPDIF Channel 1 Status bits[159:128]" line.long 0x14 "V2A__CORE_VP__REGS_APB_SPDIF_CH1_CS_191160_ADDR_p,SPDIF channel 1 status [191:160]" hexmask.long 0x14 0.--31. 1. "SPDIF_CH1_ST_STTS_BITS191160,SPDIF Channel 1 Status bits[191:160]" line.long 0x18 "V2A__CORE_VP__REGS_APB_SPDIF_CH2_CS_3100_ADDR_p,SPDIF channel 2 status [31:00]" hexmask.long 0x18 0.--31. 1. "SPDIF_CH2_ST_STTS_BITS3100,SPDIF Channel 2 Status bits[31:0]" line.long 0x1C "V2A__CORE_VP__REGS_APB_SPDIF_CH2_CS_6332_ADDR_p,SPDIF channel 2 status [63:32]" hexmask.long 0x1C 0.--31. 1. "SPDIF_CH2_ST_STTS_BITS6332,SPDIF Channel 2 Status bits[63:32]" line.long 0x20 "V2A__CORE_VP__REGS_APB_SPDIF_CH2_CS_9564_ADDR_p,SPDIF channel 2 status [95:64]" hexmask.long 0x20 0.--31. 1. "SPDIF_CH2_ST_STTS_BITS9564,SPDIF Channel 2 Status bits[95:64]" line.long 0x24 "V2A__CORE_VP__REGS_APB_SPDIF_CH2_CS_12796_ADDR_p,SPDIF channel 2 status [127:96]" hexmask.long 0x24 0.--31. 1. "SPDIF_CH2_ST_STTS_BITS12796,SPDIF Channel 2 Status bits[127:96]" line.long 0x28 "V2A__CORE_VP__REGS_APB_SPDIF_CH2_CS_159128_ADDR_p,SPDIF channel 2 status [159:128]" hexmask.long 0x28 0.--31. 1. "SPDIF_CH2_ST_STTS_BITS159128,SPDIF Channel 2 Status bits[159:128]" line.long 0x2C "V2A__CORE_VP__REGS_APB_SPDIF_CH2_CS_191160_ADDR_p,SPDIF channel 2 status [191:160]" hexmask.long 0x2C 0.--31. 1. "SPDIF_CH2_ST_STTS_BITS191160,SPDIF Channel 2 Status bits[191:160]" rgroup.long 0x80++0x13 line.long 0x0 "V2A__CORE_VP__REGS_APB_SMPL2PKT_CNTL_p,Sample 2 Packets Control Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x0 1. "SMPL2PKT_EN,When high Sample to Packets Block starts." "0,1" newline bitfld.long 0x0 0. "SW_RST,Software reset. Active high." "0,1" line.long 0x4 "V2A__CORE_VP__REGS_APB_SMPL2PKT_CNFG_p,Sample 2 Packets Config Register" hexmask.long.word 0x4 21.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x4 20. "CFG_SAMPLE_PRESENT_FORCE,Force sample present bits" "0,1" newline hexmask.long.byte 0x4 16.--19. 1. "CFG_SAMPLE_PRESENT,Sample present bits if force them is active" newline bitfld.long 0x4 15. "CFG_EN_AUTO_SUB_PCKT_NUM,Enable automatics sub packet number. When enabled number of sub-packts will be set according to MEM FIFO number of samples." "0,1" newline bitfld.long 0x4 14. "CFG_BLOCK_LPCM_FIRST_PKT,0 - All packets behave the same. 1- First lpcm audio packet is sent with 1 - SP." "0: All packets behave the same,1: First lpcm audio packet is sent with 1" newline bitfld.long 0x4 11.--13. "CFG_SUB_PCKT_NUM,Number of sub-packets in HDMI audio 2-ch packet. 00: 1-SP 01: 2-SP 10: 3-SP 11: 4-SP. 100-111: NA." "?,1: SP,2: SP,3: SP,4: SP,?,?,?" newline hexmask.long.byte 0x4 7.--10. 1. "AUDIO_TYPE,Audio Type setting. Packet is structured according to audio type." newline bitfld.long 0x4 5.--6. "NUM_OF_I2S_PORTS,Number ofactive I2S ports. 00- 1 port 01-2 ports 11- 4 ports 11 -NA." "0,1,2,3" newline hexmask.long.byte 0x4 0.--4. 1. "MAX_NUM_CH,Number of channels to decode. 0: 1 channel 31: 32 channels" line.long 0x8 "V2A__CORE_VP__REGS_APB_FIFO_CNTL_p,FIFO control register" hexmask.long 0x8 5.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x8 4. "CFG_DIS_PORT3,0 - Normal Operation. 1 - I2S port 3 is disabled [user should ignore its outputs]. This allows for 24-ch 12-ch 6-ch transfer." "0: Normal Operation,1: I2S port 3 is disabled [user should ignore its.." newline bitfld.long 0x8 3. "FIFO_EMPTY_CALC,0 - Empty is a function of read address. 1 - Empty is a function of BASE read address." "0: Empty is a function of read address,1: Empty is a function of BASE read address" newline bitfld.long 0x8 2. "FIFO_DIR,0 - smpl2pkt [inc_step=number of I2S ports] 1 - pkt2smpl [inc_step=num_ch_per_port]" "0: smpl2pkt [inc_step=number of I2S ports] 1,?" newline bitfld.long 0x8 1. "SYNC_WR_TO_CH_ZERO,When high the last channel index synchronizes the write addresses [to the next channel group]" "0,1" newline bitfld.long 0x8 0. "FIFO_SW_RST,Resets Fifo's write and read pointers. When FIFO configuration bits change this signal should be high [due to synchronization issues]." "0,1" line.long 0xC "V2A__CORE_VP__REGS_APB_FIFO_STTS_p,FIFO Status register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline rbitfld.long 0xC 3. "UNDERRUN,Indicates a FIFO underrun error has occured - FIFO read when it was empty. For debug purposes not synchronized." "0,1" newline rbitfld.long 0xC 2. "OVERRUN,Indicates a FIFO overrun error has occured - FIFO written to when it was full. For debug purposes not synchronized." "0,1" newline rbitfld.long 0xC 1. "REMPTY,Indicates FIFO Empty. For debug purposes not synchronized." "0,1" newline rbitfld.long 0xC 0. "WFULL,Indicates FIFO Full. For debug purposes not synchronized." "0,1" line.long 0x10 "V2A__CORE_VP__REGS_APB_SUB_PCKT_THRSH_p,SUB Packet Threshold register" hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x10 16.--23. 1. "CFG_MEM_FIFO_THRSH3,If number of samples in MEM FIFO is below Threshold 3: Each Packet will contain only 3 subpacket." newline hexmask.long.byte 0x10 8.--15. 1. "CFG_MEM_FIFO_THRSH2,If number of samples in MEM FIFO is below Threshold2: Each Packet will contain only 2 subpacket." newline hexmask.long.byte 0x10 0.--7. 1. "CFG_MEM_FIFO_THRSH1,If number of samples in MEM FIFO is below Threshold 1: Each Packet will contain only 1 subpacket." rgroup.long 0x0++0x13 line.long 0x0 "V2A__CORE_VP__REGS_APB_SOURCE_PIF_WR_ADDR_p,4 MSB of the packet memory address in which the data is written." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x0 0.--3. 1. "WR_ADDR,4 MSB of the packet memory address in which the data is written." line.long 0x4 "V2A__CORE_VP__REGS_APB_SOURCE_PIF_WR_REQ_p,Write request bit for the host write transaction." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x4 0. "HOST_WR,Write request bit for the host write transaction active high. Bit is automatically cleared when operation is completed." "0,1" line.long 0x8 "V2A__CORE_VP__REGS_APB_SOURCE_PIF_RD_ADDR_p,4 MSB of the packet memory address from which the data is read." hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x8 0.--3. 1. "RD_ADDR,4 MSB of the packet memory address from which the data is read." line.long 0xC "V2A__CORE_VP__REGS_APB_SOURCE_PIF_RD_REQ_p,Read request bit for the host read transaction." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0xC 0. "HOST_RD,Read request bit for the host read transaction active high. Bit is automatically cleared when operation is completed." "0,1" line.long 0x10 "V2A__CORE_VP__REGS_APB_SOURCE_PIF_DATA_WR_p,The 32 bits of the data to be written to the packet memory." hexmask.long 0x10 0.--31. 1. "DATA_WR,The 32 bits of the data to be written to the packet memory. When written to this register fifo1_wr_enable will automatically be asserted and the data is stored in FIFO." rgroup.long 0x14++0x3 line.long 0x0 "V2A__CORE_VP__REGS_APB_SOURCE_PIF_DATA_RD_p,The 32 bits of the data to be read from the packet memory." hexmask.long 0x0 0.--31. 1. "FIFO2_DATA_OUT,The 32 bits of the data to be read from the packet memory. When read from this register fifo2_rd_enable will automatically be asserted and the data is read from the FIFO." rgroup.long 0x18++0x27 line.long 0x0 "V2A__CORE_VP__REGS_APB_SOURCE_PIF_FIFO1_FLUSH_p,Fifo1 flush" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x0 0. "FIFO1_FLUSH,Fifo1 flush bit active high. Bit is automatically cleared when operation is completed." "0,1" line.long 0x4 "V2A__CORE_VP__REGS_APB_SOURCE_PIF_FIFO2_FLUSH_p,Fifo2 flush" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x4 0. "FIFO2_FLUSH,Fifo2 flush bit active high. Bit is automatically cleared when operation is completed." "0,1" line.long 0x8 "V2A__CORE_VP__REGS_APB_SOURCE_PIF_STATUS_p,Status bits for the PIF module" hexmask.long 0x8 5.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline rbitfld.long 0x8 4. "FIFO2_EMPTY,Fifo2 empty indication when high indicates that FIFO2 is empty" "0,1" newline rbitfld.long 0x8 3. "FIFO1_FULL,Fifo1 full indication when high indicates that FIFO1 is full" "0,1" newline rbitfld.long 0x8 0.--2. "SOURCE_PKT_MEM_CTRL_FSM_STATE,State of the FSM that controls packet memory transactions." "0,1,2,3,4,5,6,7" line.long 0xC "V2A__CORE_VP__REGS_APB_SOURCE_PIF_INTERRUPT_SOURCE_p,Interrupt sources of the PIF module. active high. Automatically cleared on read. If any of this interrupt is enabled and triggered bit apb_pif_intr_status in APB_INT_STATUS register is set." hexmask.long.tbyte 0xC 11.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline rbitfld.long 0xC 10. "PPS_SENT,PPS sent to framer indication. Active HIGH. Clear on read." "0,1" newline rbitfld.long 0xC 9. "FIFO2_UNDERFLOW,Fifo2 underflow indication. Indicates incorrect programming sequence. Active HIGH. Clear on read." "0,1" newline rbitfld.long 0xC 8. "FIFO2_OVERFLOW,Fifo2 overflow indication. Indicates incorrect programming sequence. Active HIGH. Clear on read." "0,1" newline rbitfld.long 0xC 7. "FIFO1_UNDERFLOW,Fifo1 underflow indication. Indicates incorrect programming sequence. Active HIGH. Clear on read." "0,1" newline rbitfld.long 0xC 6. "FIFO1_OVERFLOW,Fifo1 overflow indication. Indicates incorrect programming sequence. Active HIGH. Clear on read." "0,1" newline rbitfld.long 0xC 5. "ALLOC_WR_ERROR,Error happened invalid write to the allocation table. Indicates incorrect programming sequence. Active HIGH. Clear on read." "0,1" newline rbitfld.long 0xC 4. "ALLOC_WR_DONE,Successful write to the allocation table. Active HIGH. Clear on read." "0,1" newline bitfld.long 0xC 3. "RESERVED,Reserved field. 0x0 when read. Writes ignored." "0,1" newline rbitfld.long 0xC 2. "NONVALID_TYPE_REQUESTED_INT,Indication that nonvalid type of packet is requested by the packet interface. Indicates incorrect programming sequence. Active HIGH. Clear on read." "0,1" newline rbitfld.long 0xC 1. "HOST_RD_DONE_INT,Indication that the host read transaction finished. Active HIGH. Clear on read." "0,1" newline rbitfld.long 0xC 0. "HOST_WR_DONE_INT,Indication that the host write transaction finished. Active HIGH. Clear on read." "0,1" line.long 0x10 "V2A__CORE_VP__REGS_APB_SOURCE_PIF_INTERRUPT_MASK_p,Masks for the interrupt sources in the SOURCE_PIF_INTERRUPT_SOURCE register. when set high. these bits disable the corresponding interrupts" hexmask.long.tbyte 0x10 11.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x10 10. "PPS_SENT_MASK,Masks the pps_sent interrupt. 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0x10 9. "FIFO2_UNDERFLOW_MASK,Masks the fifo2_underflow interrupt. 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0x10 8. "FIFO2_OVERFLOW_MASK,Masks the fifo2_overflow interrupt. 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0x10 7. "FIFO1_UNDERFLOW_MASK,Masks the fifo1_underflow interrupt. 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0x10 6. "FIFO1_OVERFLOW_MASK,Masks the fifo1_overflow interrupt. 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0x10 5. "ALLOC_WR_ERROR_MASK,Masks the alloc_wr_error interrupt. 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0x10 4. "ALLOC_WR_DONE_MASK,Masks the alloc_wr_done interrupt. 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0x10 3. "RESERVED,Reserved field. 0x0 when read. Writes ignored." "0,1" newline bitfld.long 0x10 2. "NONVALID_TYPE_REQUESTED_INT_MASK,Masks the nonvalid_type_requested_int interrupt. 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0x10 1. "HOST_RD_DONE_INT_MASK,Masks the host_rd_done_int interrupt. 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0x10 0. "HOST_WR_DONE_INT_MASK,Masks the host_wr_done_int interrupt. 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" line.long 0x14 "V2A__CORE_VP__REGS_APB_SOURCE_PIF_PKT_ALLOC_REG_p,Packet configuration to be stored in the allocation table" hexmask.long.word 0x14 18.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x14 17. "ACTIVE_IDLE_TYPE,Indicates in which mode the SDP will be sent. 0- no_video mode 1- video mode" "0: no_video mode,1: video mode" newline bitfld.long 0x14 16. "TYPE_VALID,1 for valid 0 for nonvalid" "0,1" newline hexmask.long.byte 0x14 8.--15. 1. "PACKET_TYPE,8-bit value of the packet type" newline hexmask.long.byte 0x14 4.--7. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline hexmask.long.byte 0x14 0.--3. 1. "PKT_ALLOC_ADDRESS,Address of the register in the source allocation table" line.long 0x18 "V2A__CORE_VP__REGS_APB_SOURCE_PIF_PKT_ALLOC_WR_EN_p,Enable bit for writing to the allocation table" hexmask.long 0x18 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x18 0. "PKT_ALLOC_WR_EN,Enable bit for writing to the allocation table active high" "0,1" line.long 0x1C "V2A__CORE_VP__REGS_APB_SOURCE_PIF_SW_RESET_p,Software reset." hexmask.long 0x1C 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x1C 0. "SW_RST,Software reset active high. Bit is automatically cleared when operation is completed." "0,1" line.long 0x20 "V2A__CORE_VP__REGS_APB_SOURCE_PIF_PPS_HEADER_p,PPS header" hexmask.long 0x20 0.--31. 1. "PPS_HEADER,value of the PPS header as per DPv1.4" line.long 0x24 "V2A__CORE_VP__REGS_APB_SOURCE_PIF_PPS_p,PPS SDP indication" hexmask.long 0x24 1.--31. 1. "RESERVED,Reserved. Writes are ignored. 0x0 when read" newline bitfld.long 0x24 0. "PPS,PPS SDP indication active high. When set the SDP to be read/written from/to the memory by the host is in fact PPS. Bit is automatically cleared when operation is completed." "0,1" tree.end tree "DSS_EDP0_V2A_S_CORE_VP_REGS_SAPB (DSS_EDP0_V2A_S_CORE_VP_REGS_SAPB)" base ad:0x4F48000 rgroup.long 0x0++0x53 line.long 0x0 "V2A_S__CORE_VP__REGS_SAPB_APB_CTRL_s,APB control register (SAPB)" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline bitfld.long 0x0 3. "APB_XT_RUNSTALL,Not used" "0,1" newline bitfld.long 0x0 2. "APB_IRAM_PATH,Not used" "0,1" newline bitfld.long 0x0 1. "APB_DRAM_PATH,Not used" "0,1" newline bitfld.long 0x0 0. "APB_XT_RESET,Not used" "0,1" line.long 0x4 "V2A_S__CORE_VP__REGS_SAPB_xt_int_ctrl_s,Internal CPU Interrupt Polarity Control Register." hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline bitfld.long 0x4 0.--1. "XT_INT_POLARITY,Not used" "0,1,2,3" line.long 0x8 "V2A_S__CORE_VP__REGS_SAPB_MAILBOX_FULL_ADDR_s,Mailbox full indication status register. This register provides a status of the mailbox that is used to send messages from the Host processor to internal uCPU. Mailbox full flag can be a source of mailbox.." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline rbitfld.long 0x8 0. "MAILBOX_FULL,Mailbox full indication. 0x1-mailbox full. No more messages can be sent to mailbox 0x0-mailbox not-full. At least 1 write can be performed to mailbox" "0: mailbox not-full,1: mailbox full" line.long 0xC "V2A_S__CORE_VP__REGS_SAPB_MAILBOX_EMPTY_ADDR_s,Mailbox empty indication status register. This register provides a status of the mailbox that is used to send responses from the internal uCPU to host processor as a result of previously sent message." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline rbitfld.long 0xC 0. "MAILBOX_EMPTY,Mailbox Empty indication 0x1-mailbox empty. No response available 0x0-mailbox not-empty. There is at least 1 byte of a response in mailbox available to read by Host processor" "0: mailbox not-empty,1: mailbox empty" line.long 0x10 "V2A_S__CORE_VP__REGS_SAPB_mailbox0_wr_data_s,Mailbox write data register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x10 0.--7. 1. "MAILBOX0_WR_DATA,Mailbox write Data." line.long 0x14 "V2A_S__CORE_VP__REGS_SAPB_mailbox0_rd_data_s,Mailbox Read data register" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x14 0.--7. 1. "MAILBOX0_RD_DATA,Mailbox Read data" line.long 0x18 "V2A_S__CORE_VP__REGS_SAPB_KEEP_ALIVE_s,Software keep alive counter" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x18 0.--7. 1. "KEEP_ALIVE_CNT,Software keep alive counter. Counter is initialized to 0x0 after reset and incremented by 0x1 with every FW kernel loop. It can be used to determine if internal CPU started running correctly." line.long 0x1C "V2A_S__CORE_VP__REGS_SAPB_VER_L_s,Software Version Register." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x1C 0.--7. 1. "VER_LSB,Software Version lower byte. Loaded by Firmware at the beggining of firmware operation." line.long 0x20 "V2A_S__CORE_VP__REGS_SAPB_VER_H_s,Software Version Register." hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x20 0.--7. 1. "VER_MSB,Software Version higher byte. Loaded by Firmware at the beggining of firmware operation." line.long 0x24 "V2A_S__CORE_VP__REGS_SAPB_VER_LIB_L_ADDR_s,Software Library Version Register." hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x24 0.--7. 1. "SW_LIB_VER_L,Software Library Version lower byte. Loaded by Firmware at the beggining of firmware operation." line.long 0x28 "V2A_S__CORE_VP__REGS_SAPB_VER_LIB_H_ADDR_s,Software Library Version Register." hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x28 0.--7. 1. "SW_LIB_VER_H,Software Library Version higher byte. Loaded by Firmware at the beggining of firmware operation." line.long 0x2C "V2A_S__CORE_VP__REGS_SAPB_SW_DEBUG_L_s,Software/Firmware Debug Register." hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x2C 0.--7. 1. "SW_DEBUG_7_0,Register used for debug purposes [lower byte]. Can be written internally by firmware to allow Core Driver to read the internal status. Not used during normal operation since it requires a special version of firmware with a debug capabilities." line.long 0x30 "V2A_S__CORE_VP__REGS_SAPB_SW_DEBUG_H_s,Software/Firmware Debug Register." hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x30 0.--7. 1. "SW_DEBUG_15_8,Register used for debug purposes [higher byte]. Can be written internally by firmware to allow Core Driver to read the internal status. Not used during normal operation since it requires a special version of firmware with a debug.." line.long 0x34 "V2A_S__CORE_VP__REGS_SAPB_MAILBOX_INT_MASK_s,Mailbox Interrupt mask register" hexmask.long 0x34 2.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline bitfld.long 0x34 1. "MAILBOX_FULL_INT_MASK,Mailbox Full Interrupt mask 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" newline bitfld.long 0x34 0. "MAILBOX_EMPTY_INT_MASK,Mailbox Not-empty Interrupt mask 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" line.long 0x38 "V2A_S__CORE_VP__REGS_SAPB_MAILBOX_INT_STATUS_s,Mailbox Interrupt Status register" hexmask.long 0x38 2.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline rbitfld.long 0x38 1. "MAILBOX_FULL_INT_STATUS,Mailbox full interrupt. Active HIGH. Cleared on read. This interrupt is set when mailbox becomes full which means there is no more space for messages sent from Host processor to internal uCPU and when this interrupt is enabled.." "0,1" newline rbitfld.long 0x38 0. "MAILBOX_EMPTY_INT_STATUS,Mailbox not-empty interrupt. Active HIGH. Cleared on read. This interrupt is set when mailbox becomes not-empty which means there is a response in the mailbox available to read by the Host processer and when interrupt is.." "0,1" line.long 0x3C "V2A_S__CORE_VP__REGS_SAPB_SW_CLK_L_s,Core Clock frequency" hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x3C 0.--7. 1. "SW_CLOCK_VAL_L,Not used." line.long 0x40 "V2A_S__CORE_VP__REGS_SAPB_SW_CLK_H_s,Core Clock frequency" hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x40 0.--7. 1. "SW_CLOCK_VAL_H,Not used." line.long 0x44 "V2A_S__CORE_VP__REGS_SAPB_SW_EVENTS0_s,Not used. 0x0 when read." hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x44 0.--7. 1. "SW_EVENTS7_0,Not used. 0x0 when read." line.long 0x48 "V2A_S__CORE_VP__REGS_SAPB_SW_EVENTS1_s,Not used. 0x0 when read." hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x48 0.--7. 1. "SW_EVENTS15_8,Not used. 0x0 when read." line.long 0x4C "V2A_S__CORE_VP__REGS_SAPB_SW_EVENTS2_s,Not used. 0x0 when read." hexmask.long.tbyte 0x4C 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x4C 0.--7. 1. "SW_EVENTS23_16,Not used. 0x0 when read." line.long 0x50 "V2A_S__CORE_VP__REGS_SAPB_SW_EVENTS3_s,Not used. 0x0 when read." hexmask.long.tbyte 0x50 8.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline hexmask.long.byte 0x50 0.--7. 1. "SW_EVENTS31_24,Not used. 0x0 when read." rgroup.long 0x60++0x7 line.long 0x0 "V2A_S__CORE_VP__REGS_SAPB_XT_OCD_CTRL_s,Internal CPU - On Chip Debug (OCD) Ctrl Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline bitfld.long 0x0 1. "XT_OCDHALTONRESET,Not used" "0,1" newline bitfld.long 0x0 0. "XT_DRESET,Not used" "0,1" line.long 0x4 "V2A_S__CORE_VP__REGS_SAPB_XT_OCD_CTRL_RO_s,Internal CPU - OCD R0 mode configuration" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline rbitfld.long 0x4 0. "XT_XOCDMODE,Internal CPU - OCD mode configuration" "0,1" rgroup.long 0x6C++0x7 line.long 0x0 "V2A_S__CORE_VP__REGS_SAPB_APB_INT_MASK_s,APB Interrupt Mask Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline bitfld.long 0x0 1. "APB_SW_INTR_MASK,Not used." "0,1" newline bitfld.long 0x0 0. "APB_MAILBOX_INTR_MASK,Mailbox Interrupt mask 0x0-interrupt enabled 0x1-interrupt disabled" "0: interrupt enabled 0x1-interrupt disabled,?" line.long 0x4 "V2A_S__CORE_VP__REGS_SAPB_APB_STATUS_s,APB interrupt status register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved field. 0x0 when read. Writes ignored." newline rbitfld.long 0x4 1. "APB_SW_INTR_STATUS,Not used." "0,1" newline rbitfld.long 0x4 0. "APB_MAILBOX_INTR_STATUS,Mailbox Interrupt status. Active HIGH. If this bit is set further status should be read from MAILBOX_INT_STATUS register. This bit is cleared automatically on read from MAILBOX_INT_STATUS register." "0,1" tree.end tree.end tree.end tree.end tree "DSS0" base ad:0x0 tree "DSS0_DISPC_0_COMMON" tree "DSS0_DISPC_0_COMMON_M (DSS0_DISPC_0_COMMON_M)" base ad:0x4A00000 rgroup.long 0x4++0x3 line.long 0x0 "DISPC_0_COMMON_M_DSS_REVISION,This register contains the K3_DSS revision number" hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID Field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Revision" newline bitfld.long 0x0 8.--10. "REVMAJOR,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Revision" rgroup.long 0x8++0x3 line.long 0x0 "DISPC_0_COMMON_M_DSS_SYSCONFIG,This register controls various parameters related to software reset and IP idle" hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED4,Write 0's for future compatibility. Read returns 0" hexmask.long.byte 0x0 8.--13. 1. "RESERVED3,Write 0's for future compatibility. Read returns 0" newline rbitfld.long 0x0 6.--7. "RESERVED2,Write 0's for future compatibility. Read returns 0" "0,1,2,3" bitfld.long 0x0 5. "WARMRESET,Warm reset. Setting this bit to 1 triggers a module warm reset. The bit is automatically reset by the hardware. During read it always returns 0. The warm reset keeps the configuration registers unchanged" "0,1" newline bitfld.long 0x0 3.--4. "IDLEMODE,Deprecated" "0,1,2,3" rbitfld.long 0x0 2. "RESERVED1,Write 0's for future compatibility. Read returns 0" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Setting this bit to 1 triggers a module reset. The bit is automatically reset by the hardware. During read it always returns 0" "0,1" bitfld.long 0x0 0. "AUTOCLKGATING,Internal clock gating strategy" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "DISPC_0_COMMON_M_DSS_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x0 9. "DISPC_IDLE_STATUS,Idle status of DISPC" "0,1" hexmask.long.byte 0x0 1.--4. 1. "DISPC_VP_RESETDONE,Reset status of VP[3:0] pixel clock domain" newline bitfld.long 0x0 0. "DISPC_FUNC_RESETDONE,Reset status of DISPC Functional clock domain" "0,1" rgroup.long 0x28++0x57 line.long 0x0 "DISPC_0_COMMON_M_DISPC_IRQSTATUS_RAW,RAW Interrupt status. Raw status is set even if interrupt is not enabled. Write 1 to set the RAW status" bitfld.long 0x0 16. "DUMMY_IRQ,Dummy IRQ STATUS- Reserved for future use" "0,1" bitfld.long 0x0 15. "DUMMY1_IRQ,Dummy IRQ STATUS- Reserved for future use" "0,1" newline bitfld.long 0x0 14. "WB_IRQ,WB IRQ STATUS. Register indicates the WB pipeline interrupt events if WB pipeline is present" "0,1" hexmask.long.byte 0x0 4.--7. 1. "VID_IRQ,VID IRQ STATUS. Register indicates the Video pipeline[s] interrupt events. [0] -> VID1 [1] -> VIDL1 [2] -> VID2 [3] -> VIDL2" newline hexmask.long.byte 0x0 0.--3. 1. "VP_IRQ,VP[3:0] IRQ STATUS. Register indicates the Video Port[s] interrupt events" line.long 0x4 "DISPC_0_COMMON_M_DISPC_IRQSTATUS,Interrupt status. Enabled status. isn't set unless event is enabled. Write 1 to clear the status after interrupt has been serviced. RAW status also gets cleared. i.e. even if not enabled" bitfld.long 0x4 16. "DUMMY_IRQ,Dummy IRQ STATUS-Reserved for future use" "0,1" bitfld.long 0x4 15. "DUMMY1_IRQ,Dummy IRQ STATUS-Reserved for future use" "0,1" newline bitfld.long 0x4 14. "WB_IRQ,WB IRQ STATUS. Register indicates the WB pipeline interrupt events if WB pipeline is present" "0,1" hexmask.long.byte 0x4 4.--7. 1. "VID_IRQ,VID IRQ STATUS. Register indicates the Video pipeline[s] interrupt events.[0] -> VID1 [1] -> VIDL1 [2] -> VID2 [3] -> VIDL2" newline hexmask.long.byte 0x4 0.--3. 1. "VP_IRQ,VP[3:0] IRQ STATUS. Register indicates the Video Port[s] interrupt events" line.long 0x8 "DISPC_0_COMMON_M_DISPC_IRQENABLE_SET,SET Interrupt enable. Write 1 to set interrupt enable. Readout equal to corresponding _CLR register" bitfld.long 0x8 16. "SET_DUMMY_IRQ,Dummy IRQ" "0,1" bitfld.long 0x8 15. "SET_DUMMY1_IRQ,Dummy IRQ" "0,1" newline bitfld.long 0x8 14. "SET_WB_IRQ,WB IRQ if WB pipeline is present" "0,1" hexmask.long.byte 0x8 4.--7. 1. "SET_VID_IRQ,VID IRQ. [0] -> VID1 [1] -> VIDL1 [2] -> VID2 [3] -> VIDL2" newline hexmask.long.byte 0x8 0.--3. 1. "SET_VP_IRQ,VP[3:0] IRQ" line.long 0xC "DISPC_0_COMMON_M_DISPC_IRQENABLE_CLR,CLR Interrupt enable. Write 1 to clear interrupt enable" bitfld.long 0xC 16. "CLR_DUMMY_IRQ,Dummy IRQ" "0,1" bitfld.long 0xC 15. "CLR_DUMMY1_IRQ,Dummy IRQ" "0,1" newline bitfld.long 0xC 14. "CLR_WB_IRQ,WB IRQ if WB pipeline is present" "0,1" hexmask.long.byte 0xC 4.--7. 1. "CLR_VID_IRQ,VID IRQ.[0] -> VID1 [1] -> VIDL1 [2] -> VID2 [3] -> VIDL2" newline hexmask.long.byte 0xC 0.--3. 1. "CLR_VP_IRQ,VP[3:0] IRQ" line.long 0x10 "DISPC_0_COMMON_M_VID_IRQENABLE_0,This register allows to mask/unmask the VID internal sources of interrupt. on an event-by-event basis.[0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x10 4. "FBDC_ILLEGALTILEREQ_EN,FBDC IRQ Illegal tile req detected" "0,1" bitfld.long 0x10 3. "FBDC_CORRUPTTILE_EN,FBDC IRQ. Corrupt tile detected" "0,1" newline bitfld.long 0x10 2. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x10 1. "VIDENDWINDOW_EN,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" newline bitfld.long 0x10 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x14 "DISPC_0_COMMON_M_VID_IRQENABLE_1,This register allows to mask/unmask the VID internal sources of interrupt. on an event-by-event basis.[0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x14 4. "FBDC_ILLEGALTILEREQ_EN,FBDC IRQ Illegal tile req detected" "0,1" bitfld.long 0x14 3. "FBDC_CORRUPTTILE_EN,FBDC IRQ. Corrupt tile detected" "0,1" newline bitfld.long 0x14 2. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x14 1. "VIDENDWINDOW_EN,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" newline bitfld.long 0x14 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x18 "DISPC_0_COMMON_M_VID_IRQENABLE_2,This register allows to mask/unmask the VID internal sources of interrupt. on an event-by-event basis.[0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x18 4. "FBDC_ILLEGALTILEREQ_EN,FBDC IRQ Illegal tile req detected" "0,1" bitfld.long 0x18 3. "FBDC_CORRUPTTILE_EN,FBDC IRQ. Corrupt tile detected" "0,1" newline bitfld.long 0x18 2. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x18 1. "VIDENDWINDOW_EN,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" newline bitfld.long 0x18 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x1C "DISPC_0_COMMON_M_VID_IRQENABLE_3,This register allows to mask/unmask the VID internal sources of interrupt. on an event-by-event basis.[0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x1C 4. "FBDC_ILLEGALTILEREQ_EN,FBDC IRQ Illegal tile req detected" "0,1" bitfld.long 0x1C 3. "FBDC_CORRUPTTILE_EN,FBDC IRQ. Corrupt tile detected" "0,1" newline bitfld.long 0x1C 2. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x1C 1. "VIDENDWINDOW_EN,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" newline bitfld.long 0x1C 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x20 "DISPC_0_COMMON_M_VID_IRQSTATUS_0,This register groups all the status of the VID internal events that generate an interrupt. Write 1 to a clear a bit field.[0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x20 4. "FBDC_ILLEGALTILEREQ_IRQ,FBDC IRQ Illegal tile req detected" "0,1" bitfld.long 0x20 3. "FBDC_CORRUPTTILE_IRQ,FBDC IRQ. Corrupt tile detected" "0,1" newline bitfld.long 0x20 2. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x20 1. "VIDENDWINDOW_IRQ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" newline bitfld.long 0x20 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x24 "DISPC_0_COMMON_M_VID_IRQSTATUS_1,This register groups all the status of the VID internal events that generate an interrupt. Write 1 to a clear a bit field.[0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x24 4. "FBDC_ILLEGALTILEREQ_IRQ,FBDC IRQ Illegal tile req detected" "0,1" bitfld.long 0x24 3. "FBDC_CORRUPTTILE_IRQ,FBDC IRQ. Corrupt tile detected" "0,1" newline bitfld.long 0x24 2. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x24 1. "VIDENDWINDOW_IRQ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" newline bitfld.long 0x24 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x28 "DISPC_0_COMMON_M_VID_IRQSTATUS_2,This register groups all the status of the VID internal events that generate an interrupt. Write 1 to a clear a bit field.[0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x28 4. "FBDC_ILLEGALTILEREQ_IRQ,FBDC IRQ Illegal tile req detected" "0,1" bitfld.long 0x28 3. "FBDC_CORRUPTTILE_IRQ,FBDC IRQ. Corrupt tile detected" "0,1" newline bitfld.long 0x28 2. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x28 1. "VIDENDWINDOW_IRQ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" newline bitfld.long 0x28 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x2C "DISPC_0_COMMON_M_VID_IRQSTATUS_3,This register groups all the status of the VID internal events that generate an interrupt. Write 1 to a clear a bit field.[0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x2C 4. "FBDC_ILLEGALTILEREQ_IRQ,FBDC IRQ Illegal tile req detected" "0,1" bitfld.long 0x2C 3. "FBDC_CORRUPTTILE_IRQ,FBDC IRQ. Corrupt tile detected" "0,1" newline bitfld.long 0x2C 2. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x2C 1. "VIDENDWINDOW_IRQ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" newline bitfld.long 0x2C 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x30 "DISPC_0_COMMON_M_VP_IRQENABLE_0,This register allows to mask/unmask the VP_0 internal sources of interrupt. on an event-by-event basis" hexmask.long.byte 0x30 13.--16. 1. "SAFETYREGION1_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x30 12. "DUMMY_EN,Dummy IRQ for future use" "0,1" newline bitfld.long 0x30 11. "VPSYNC_EN,Go bit clear event" "0,1" bitfld.long 0x30 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID" "0,1" newline hexmask.long.byte 0x30 6.--9. 1. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x30 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x30 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1" bitfld.long 0x30 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" newline bitfld.long 0x30 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1" bitfld.long 0x30 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1" newline bitfld.long 0x30 0. "VPFRAMEDONE_EN,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent" "0,1" line.long 0x34 "DISPC_0_COMMON_M_VP_IRQENABLE_1,This register allows to mask/unmask the VP_1 internal sources of interrupt. on an event-by-event basis" hexmask.long.byte 0x34 13.--16. 1. "SAFETYREGION1_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x34 12. "DUMMY_EN,Dummy IRQ for future use" "0,1" newline bitfld.long 0x34 11. "VPSYNC_EN,Go bit clear event" "0,1" bitfld.long 0x34 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID" "0,1" newline hexmask.long.byte 0x34 6.--9. 1. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x34 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x34 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1" bitfld.long 0x34 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" newline bitfld.long 0x34 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1" bitfld.long 0x34 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1" newline bitfld.long 0x34 0. "VPFRAMEDONE_EN,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent" "0,1" line.long 0x38 "DISPC_0_COMMON_M_VP_IRQENABLE_2,This register allows to mask/unmask the VP_2 internal sources of interrupt. on an event-by-event basis" hexmask.long.byte 0x38 13.--16. 1. "SAFETYREGION1_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x38 12. "DUMMY_EN,Dummy IRQ for future use" "0,1" newline bitfld.long 0x38 11. "VPSYNC_EN,Go bit clear event" "0,1" bitfld.long 0x38 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID" "0,1" newline hexmask.long.byte 0x38 6.--9. 1. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x38 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x38 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1" bitfld.long 0x38 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" newline bitfld.long 0x38 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1" bitfld.long 0x38 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1" newline bitfld.long 0x38 0. "VPFRAMEDONE_EN,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent" "0,1" line.long 0x3C "DISPC_0_COMMON_M_VP_IRQENABLE_3,This register allows to mask/unmask the VP_3 internal sources of interrupt. on an event-by-event basis" hexmask.long.byte 0x3C 13.--16. 1. "SAFETYREGION1_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x3C 12. "DUMMY_EN,Dummy IRQ for future use" "0,1" newline bitfld.long 0x3C 11. "VPSYNC_EN,Go bit clear event" "0,1" bitfld.long 0x3C 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID" "0,1" newline hexmask.long.byte 0x3C 6.--9. 1. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x3C 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x3C 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1" bitfld.long 0x3C 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" newline bitfld.long 0x3C 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1" bitfld.long 0x3C 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1" newline bitfld.long 0x3C 0. "VPFRAMEDONE_EN,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent" "0,1" line.long 0x40 "DISPC_0_COMMON_M_VP_IRQSTATUS_0,This register groups all the status of the VP_0 internal events that generate an interrupt. Write 1 to a given bit resets this bit" hexmask.long.byte 0x40 13.--16. 1. "SAFETYREGION1_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x40 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1" newline bitfld.long 0x40 11. "VPSYNC_IRQ,Go bit clear event" "0,1" bitfld.long 0x40 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure OVR/VP connected to secure VID" "0,1" newline hexmask.long.byte 0x40 6.--9. 1. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x40 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x40 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with VP output" "0,1" bitfld.long 0x40 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" newline bitfld.long 0x40 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field. For interlace mode only" "0,1" bitfld.long 0x40 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output. It is used as VSYNC_EVEN in case of interlace mode" "0,1" newline bitfld.long 0x40 0. "VPFRAMEDONE_IRQ,Frame Done for VP. VP output has been disabled by user All the data have been sent" "0,1" line.long 0x44 "DISPC_0_COMMON_M_VP_IRQSTATUS_1,This register groups all the status of the VP_1 internal events that generate an interrupt. Write 1 to a given bit resets this bit" hexmask.long.byte 0x44 13.--16. 1. "SAFETYREGION1_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x44 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1" newline bitfld.long 0x44 11. "VPSYNC_IRQ,Go bit clear event" "0,1" bitfld.long 0x44 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure OVR/VP connected to secure VID" "0,1" newline hexmask.long.byte 0x44 6.--9. 1. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x44 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x44 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with VP output" "0,1" bitfld.long 0x44 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" newline bitfld.long 0x44 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field. For interlace mode only" "0,1" bitfld.long 0x44 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output. It is used as VSYNC_EVEN in case of interlace mode" "0,1" newline bitfld.long 0x44 0. "VPFRAMEDONE_IRQ,Frame Done for VP. VP output has been disabled by user All the data have been sent" "0,1" line.long 0x48 "DISPC_0_COMMON_M_VP_IRQSTATUS_2,This register groups all the status of the VP_2 internal events that generate an interrupt. Write 1 to a given bit resets this bit" hexmask.long.byte 0x48 13.--16. 1. "SAFETYREGION1_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x48 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1" newline bitfld.long 0x48 11. "VPSYNC_IRQ,Go bit clear event" "0,1" bitfld.long 0x48 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure OVR/VP connected to secure VID" "0,1" newline hexmask.long.byte 0x48 6.--9. 1. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x48 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x48 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with VP output" "0,1" bitfld.long 0x48 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" newline bitfld.long 0x48 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field. For interlace mode only" "0,1" bitfld.long 0x48 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output. It is used as VSYNC_EVEN in case of interlace mode" "0,1" newline bitfld.long 0x48 0. "VPFRAMEDONE_IRQ,Frame Done for VP. VP output has been disabled by user All the data have been sent" "0,1" line.long 0x4C "DISPC_0_COMMON_M_VP_IRQSTATUS_3,This register groups all the status of the VP_3 internal events that generate an interrupt. Write 1 to a given bit resets this bit" hexmask.long.byte 0x4C 13.--16. 1. "SAFETYREGION1_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x4C 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1" newline bitfld.long 0x4C 11. "VPSYNC_IRQ,Go bit clear event" "0,1" bitfld.long 0x4C 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure OVR/VP connected to secure VID" "0,1" newline hexmask.long.byte 0x4C 6.--9. 1. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x4C 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x4C 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with VP output" "0,1" bitfld.long 0x4C 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" newline bitfld.long 0x4C 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field. For interlace mode only" "0,1" bitfld.long 0x4C 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output. It is used as VSYNC_EVEN in case of interlace mode" "0,1" newline bitfld.long 0x4C 0. "VPFRAMEDONE_IRQ,Frame Done for VP. VP output has been disabled by user All the data have been sent" "0,1" line.long 0x50 "DISPC_0_COMMON_M_WB_IRQENABLE,This register allows to mask/unmask the WB internal sources of interrupt. if WB pipeline is present. on an event-by-event basis" bitfld.long 0x50 4. "WBSYNC_EN,Write-back sync IRQ. Configuration copied from shadow to work for WB for next frame" "0,1" bitfld.long 0x50 3. "SECURITYVIOLATION_EN,Security Violation IRQ. Non-secure WB connected to a secure VID/OVR" "0,1" newline bitfld.long 0x50 2. "WBFRAMEDONE_EN,Write-back Frame Done" "0,1" bitfld.long 0x50 1. "WBUNCOMPLETEERROR_EN,The write back buffer has been flushed before been fully drained. Can only occur in WB Capture Mode use-case" "0,1" newline bitfld.long 0x50 0. "WBBUFFEROVERFLOW_EN,Write-back DMA Buffer Overflow. Can only occur in WB Capture Mode use-case" "0,1" line.long 0x54 "DISPC_0_COMMON_M_WB_IRQSTATUS,This register groups all the status of the WB internal events that generate an interrupt. if WB pipeline is present. Write 1 to a given bit resets this bit" bitfld.long 0x54 4. "WBSYNC_IRQ,Write-back sync IRQ. Configuration copied from shadow to work for WB for next frame" "0,1" bitfld.long 0x54 3. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure WB connected to a secure VID/OVR" "0,1" newline bitfld.long 0x54 2. "WBFRAMEDONE_IRQ,Write-back Frame Done" "0,1" bitfld.long 0x54 1. "WBUNCOMPLETEERROR_IRQ,Write back DMA buffer is flushed before been completely drained. Can only occur in WB Capture Mode use-case" "0,1" newline bitfld.long 0x54 0. "WBBUFFEROVERFLOW_IRQ,Write-back DMA Buffer Overflow The DMA buffer is full" "0,1" rgroup.long 0x80++0xB line.long 0x0 "DISPC_0_COMMON_M_DISPC_IRQ_EOI_FUNC,End-Of-Interrupt register for FUNC interrupts. to be used if pulse interrupts are used" bitfld.long 0x0 0. "EOI,Write 1 to acknowledge a pulse IRQ" "0,1" line.long 0x4 "DISPC_0_COMMON_M_DISPC_IRQ_EOI_SAFETY,End-Of-Interrupt register for SAFETY interrupts. to be used if pulse interrupts are used" bitfld.long 0x4 0. "EOI,Write 1 to acknowledge a pulse IRQ" "0,1" line.long 0x8 "DISPC_0_COMMON_M_DISPC_IRQ_EOI_SECURITY,End-Of-Interrupt register for SECURITY interrupts. to be used if pulse interrupts are used" bitfld.long 0x8 0. "EOI,Write 1 to acknowledge a pulse IRQ" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "DISPC_0_COMMON_M_DISPC_SECURE_DISABLE,Disable security settings throughout DSS IP. COMMON_1.DISPC_SECURE bits are honoured only if COMMON.DISPC_SECURE_DISABLE =0" bitfld.long 0x0 0. "SECURE_DISABLE,Secure disable bit" "0,1" rgroup.long 0x98++0x13 line.long 0x0 "DISPC_0_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE,MFLAG control register" bitfld.long 0x0 6. "MFLAG_START,MFLAG_START for DMA master port" "0,1" bitfld.long 0x0 0.--1. "MFLAG_CTRL,MFLAG_CTRL for DMA master port" "0,1,2,3" line.long 0x4 "DISPC_0_COMMON_M_DISPC_GLOBAL_OUTPUT_ENABLE,DISPC global output enable register. The ENABLE or GO bit for a particular output port is set when either the corresponding bit in this register is set or the corresponding bit within the sub-module is set." hexmask.long.byte 0x4 16.--19. 1. "VP_GO,Global GO Command for the VP[3:0] output. It is used to synchronize the pipelines associated with the VP output. wr: immediate" hexmask.long.byte 0x4 0.--3. 1. "VP_ENABLE,Global VP[3:0] Enable" line.long 0x8 "DISPC_0_COMMON_M_DISPC_GLOBAL_BUFFER,The register configures the DMA buffers allocations to the pipelines for DMA" bitfld.long 0x8 31. "BUFFERFILLING,Controls if the DMA buffers are re-filled only when the LOW threshold is reached or if all DMA buffers are re-filled when at least one of them reaches the LOW threshold" "0,1" bitfld.long 0x8 30. "SHAREDBUFENABLE,Enable Shared DMA Buffer feature" "0,1" newline bitfld.long 0x8 29. "RESERVED1,Reserved1" "0,1" bitfld.long 0x8 12.--14. "WB_BUFFER,WB DMA buffer allocation to one of the pipelines if WB pipeline is present" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "VIDL2_BUFFER,VIDL2 DMA buffer allocation to one of the pipelines if VIDL2 is present" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "VID2_BUFFER,VID2 DMA buffer allocation to one of the pipelines if VID2 is present" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "VIDL1_BUFFER,VIDL1 DMA buffer allocation to one of the pipelines" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "VID1_BUFFER,VID1 DMA buffer allocation to one of the pipelines" "0,1,2,3,4,5,6,7" line.long 0xC "DISPC_0_COMMON_M_DSS_CBA_CFG,This register contains CBA specific config bits in DSS" bitfld.long 0xC 7.--8. "DMA_BACKLOGSTATUS_DISABLE_VAL,IP Internal - Tie-off value on DMA_BACKLOGSTATUS pins when DMA Backlog Status reporting is disabled" "0,1,2,3" bitfld.long 0xC 6. "DMA_BACKLOGSTATUS_DISABLE,IP Internal - Disable generation of DMA Backlog Status reporting to interconnect" "0,1" newline bitfld.long 0xC 3.--5. "PRI_HI,The value sent out on the PRI_HI bus from DSS to CBA Indicates the priority level for high-priority [MFLAG] transactions. Value of 0x0 indicates highest priority Value of 0x7 indicates lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "PRI_LO,The value sent out on the PRI_LO bus from DSS to CBA Indicates the priority level for normal [non-MFLAG] transactions. Value of 0x0 indicates highest priority Value of 0x7 indicates lowest priority" "0,1,2,3,4,5,6,7" line.long 0x10 "DISPC_0_COMMON_M_DISPC_DBG_CONTROL,DISPC debug status control register" hexmask.long.byte 0x10 1.--8. 1. "DBGMUXSEL,Mux select for the debug status" bitfld.long 0x10 0. "DBGEN,Enable debug ports" "0,1" rgroup.long 0xAC++0x3 line.long 0x0 "DISPC_0_COMMON_M_DISPC_DBG_STATUS,DISPC debug status register" hexmask.long 0x0 0.--31. 1. "DBGOUT,Debug status" rgroup.long 0xB0++0x3 line.long 0x0 "DISPC_0_COMMON_M_DISPC_CLKGATING_DISABLE,Register to control clock gating at DISPC sub-module level" hexmask.long.byte 0x0 18.--21. 1. "VP,Clock gating control for VP[3:0]" hexmask.long.byte 0x0 14.--17. 1. "OVR,Clock gating control for OVR[3:0]" newline bitfld.long 0x0 13. "WB,Clock gating control for WB if WB pipeline is present" "0,1" hexmask.long.byte 0x0 3.--6. 1. "VID,Clock gating control for VID. [0] -> VID1 [1] -> VIDL1 [2] -> VID2 [3] -> VIDL2" newline bitfld.long 0x0 0. "DMA,Clock gating control for DMA" "0,1" rgroup.long 0xB8++0x17 line.long 0x0 "DISPC_0_COMMON_M_FBDC_REVISION_1,This register contains the FBDC Product Code" hexmask.long.word 0x0 0.--15. 1. "PRODUCTCODE,FBDC Product Code" line.long 0x4 "DISPC_0_COMMON_M_FBDC_REVISION_2,This register contains the FBDC Branch Code" hexmask.long.word 0x4 0.--15. 1. "BRANCHCODE,FBDC Branch Code" line.long 0x8 "DISPC_0_COMMON_M_FBDC_REVISION_3,This register contains the FBDC Version Code" hexmask.long.word 0x8 0.--15. 1. "VERSIONCODE,FBDC Version Code" line.long 0xC "DISPC_0_COMMON_M_FBDC_REVISION_4,This register contains the FBDC Scalable Core Code" hexmask.long.word 0xC 0.--15. 1. "CORECODE,FBDC Scalable Core Code" line.long 0x10 "DISPC_0_COMMON_M_FBDC_REVISION_5,This register contains the FBDC Configuration Code" hexmask.long.word 0x10 0.--15. 1. "CONFIGCODE,FBDC Configuration Code" line.long 0x14 "DISPC_0_COMMON_M_FBDC_REVISION_6,This register contains the FBDC Changelist Code" hexmask.long 0x14 0.--31. 1. "CHANGELISTCODE,FBDC Changelist Code" rgroup.long 0xD0++0xB line.long 0x0 "DISPC_0_COMMON_M_FBDC_COMMON_CONTROL,This register contains the common control signals for FBDC" bitfld.long 0x0 2. "GPUTYPE,GPU Selection" "0,1" line.long 0x4 "DISPC_0_COMMON_M_FBDC_CONSTANT_COLOR_0,Defines the Constant Color-0 value to be used for the FBDC" hexmask.long 0x4 0.--31. 1. "CONSTCOLOR,Defines the Constant Color-0 value to be used for the FBDC" line.long 0x8 "DISPC_0_COMMON_M_FBDC_CONSTANT_COLOR_1,Defines the Constant Color-1 value to be used for the FBDC" hexmask.long 0x8 0.--31. 1. "CONSTCOLOR,Defines the Constant Color-1 value to be used for the FBDC" rgroup.long 0xE4++0xF line.long 0x0 "DISPC_0_COMMON_M_DISPC_CONNECTIONS,Connections of various sub-modules within DISPC. as well as some peripherals outside. One hot encoding" hexmask.long.byte 0x0 24.--27. 1. "VIRTUALVP_CONN,Defines the connection to VIRTUAL_VP output" hexmask.long.byte 0x0 16.--20. 1. "WB_CONN,Defines the connection to WB pipe" newline hexmask.long.byte 0x0 4.--7. 1. "DPI_1_CONN,Defines the connection to DPI-1 output. For J7 valid values are 0x0 0x2 and 0x8" hexmask.long.byte 0x0 0.--3. 1. "DPI_0_CONN,Defines the connection to DPI-0 output. For J7 valid values are 0x0 0x2 and 0x8" line.long 0x4 "DISPC_0_COMMON_M_DISPC_MSS_VP1,This register controls the Merge_Split_Sync operation for VP1" bitfld.long 0x4 3. "MSSFORMAT,Merge Split format" "0,1" bitfld.long 0x4 1.--2. "MSSTYPE,Merge-Split-Sync operation type" "0,1,2,3" newline bitfld.long 0x4 0. "MSSENABLE,Merge-Split-Sync operation Enable" "0,1" line.long 0x8 "DISPC_0_COMMON_M_DISPC_MSS_VP3,This register controls the Merge_Split_Sync operation for VP3" bitfld.long 0x8 3. "MSSFORMAT,Merge Split format" "0,1" bitfld.long 0x8 1.--2. "MSSTYPE,Merge-Split-Sync operation type" "0,1,2,3" newline bitfld.long 0x8 0. "MSSENABLE,Merge-Split-Sync operation Enable" "0,1" line.long 0xC "DISPC_0_COMMON_M_GLOBAL_DMA_THREADSIZE,This register configures the DMA buffer size allocated to the different threads - Shared memory feature" hexmask.long.byte 0xC 20.--24. 1. "WBTHREADSIZE,Total DMA buffer size for all the pipelines connected to WB THREAD4.If the value programmed is n then the allocated buffer size is 16KB*n. Default:0KB" hexmask.long.byte 0xC 15.--19. 1. "VP3THREADSIZE,Total DMA buffer size for all the pipelines connected to VP3 THREAD3.If the value programmed is n then the allocated buffer size is 16KB*n. Default:0KB" newline hexmask.long.byte 0xC 10.--14. 1. "VP2THREADSIZE,Total DMA buffer size for all the pipelines connected to VP2 THREAD2.If the value programmed is n then the allocated buffer size is 16KB*n. Default:0KB" hexmask.long.byte 0xC 5.--9. 1. "VP1THREADSIZE,Total DMA buffer size for all the pipelines connected to VP1 THREAD1.If the value programmed is n then the allocated buffer size is 16KB*n. Default:0KB" newline hexmask.long.byte 0xC 0.--4. 1. "VP0THREADSIZE,Total DMA buffer size for all the pipelines connected to VP0 THREAD0.If the value programmed is n then the allocated buffer size is 16KB*n. Default:256KB" rgroup.long 0xF4++0x3 line.long 0x0 "DISPC_0_COMMON_M_GLOBAL_DMA_THREADSIZESTATUS,This register read the synchronized value of DMA buffer size allocated to the different threads - Shared memory feature" hexmask.long.byte 0x0 20.--24. 1. "WBTHREADSIZE,Synchronized version of WB THREADSIZE. Value used by HW" hexmask.long.byte 0x0 15.--19. 1. "VP3THREADSIZE,Synchronized version of VP3 THREADSIZE. Value used by HW" newline hexmask.long.byte 0x0 10.--14. 1. "VP2THREADSIZE,Synchronized version of VP2 THREADSIZE. Value used by HW" hexmask.long.byte 0x0 5.--9. 1. "VP1THREADSIZE,Synchronized version of VP1 THREADSIZE. Value used by HW" newline hexmask.long.byte 0x0 0.--4. 1. "VP0THREADSIZE,Synchronized version of VP0 THREADSIZE. Value used by HW" rgroup.long 0xF8++0x3 line.long 0x0 "DISPC_0_COMMON_M_GLOBAL_GOBITMODE,GLOBAL_GOBITMODE settings" bitfld.long 0x0 0. "MODE,Go bit" "0,1" tree.end tree "DSS0_DISPC_0_COMMON_S0 (DSS0_DISPC_0_COMMON_S0)" base ad:0x4A10000 rgroup.long 0x28++0x57 line.long 0x0 "DISPC_0_COMMON_S0_DISPC_IRQSTATUS_RAW,RAW Interrupt status. Raw status is set even if interrupt is not enabled. Write 1 to set the RAW status" bitfld.long 0x0 16. "DUMMY_IRQ,Dummy IRQ STATUS- Reserved for future use" "0,1" bitfld.long 0x0 15. "DUMMY1_IRQ,Dummy IRQ STATUS- Reserved for future use" "0,1" bitfld.long 0x0 14. "WB_IRQ,WB IRQ STATUS. Register indicates the WB pipeline interrupt events if WB pipeline is present" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "VID_IRQ,VID IRQ STATUS. Register indicates the Video pipeline[s] interrupt events. [0] -> VID1 [1] -> VIDL1 [2] -> VID2 [3] -> VIDL2" hexmask.long.byte 0x0 0.--3. 1. "VP_IRQ,VP[3:0] IRQ STATUS. Register indicates the Video Port[s] interrupt events" line.long 0x4 "DISPC_0_COMMON_S0_DISPC_IRQSTATUS,Interrupt status. Enabled status. isn't set unless event is enabled. Write 1 to clear the status after interrupt has been serviced. RAW status also gets cleared. i.e. even if not enabled" bitfld.long 0x4 16. "DUMMY_IRQ,Dummy IRQ STATUS-Reserved for future use" "0,1" bitfld.long 0x4 15. "DUMMY1_IRQ,Dummy IRQ STATUS-Reserved for future use" "0,1" bitfld.long 0x4 14. "WB_IRQ,WB IRQ STATUS. Register indicates the WB pipeline interrupt events if WB pipeline is present" "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "VID_IRQ,VID IRQ STATUS. Register indicates the Video pipeline[s] interrupt events. [0] -> VID1 [1] -> VIDL1 [2] -> VID2 [3] -> VIDL2" hexmask.long.byte 0x4 0.--3. 1. "VP_IRQ,VP IRQ STATUS. Register indicates the Video Port[s] interrupt events" line.long 0x8 "DISPC_0_COMMON_S0_DISPC_IRQENABLE_SET,SET Interrupt enable. Write 1 to set interrupt enable. Readout equal to corresponding _CLR register" bitfld.long 0x8 16. "SET_DUMMY_IRQ,Dummy IRQ" "0,1" bitfld.long 0x8 15. "SET_DUMMY1_IRQ,Dummy IRQ" "0,1" bitfld.long 0x8 14. "SET_WB_IRQ,WB IRQ if WB pipeline is present" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "SET_VID_IRQ,VID IRQ. [0] -> VID1 [1] -> VIDL1 [2] -> VID2 [3] -> VIDL2" hexmask.long.byte 0x8 0.--3. 1. "SET_VP_IRQ,VP IRQ" line.long 0xC "DISPC_0_COMMON_S0_DISPC_IRQENABLE_CLR,CLR Interrupt enable. Write 1 to clear interrupt enable" bitfld.long 0xC 16. "CLR_DUMMY_IRQ,Dummy IRQ" "0,1" bitfld.long 0xC 15. "CLR_DUMMY1_IRQ,Dummy IRQ" "0,1" bitfld.long 0xC 14. "CLR_WB_IRQ,WB IRQ if WB pipeline is present" "0,1" newline hexmask.long.byte 0xC 4.--7. 1. "CLR_VID_IRQ,VID IRQ. [0] -> VID1 [1] -> VIDL1 [2] -> VID2 [3] -> VIDL2" hexmask.long.byte 0xC 0.--3. 1. "CLR_VP_IRQ,VP IRQ" line.long 0x10 "DISPC_0_COMMON_S0_VID_IRQENABLE_0,This register allows to mask/unmask the VID internal sources of interrupt. on an event-by-event basis. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x10 4. "FBDC_ILLEGALTILEREQ_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x10 3. "FBDC_CORRUPTTILE_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x10 2. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x10 1. "VIDENDWINDOW_EN,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x10 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x14 "DISPC_0_COMMON_S0_VID_IRQENABLE_1,This register allows to mask/unmask the VID internal sources of interrupt. on an event-by-event basis. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x14 4. "FBDC_ILLEGALTILEREQ_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x14 3. "FBDC_CORRUPTTILE_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x14 2. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x14 1. "VIDENDWINDOW_EN,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x14 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x18 "DISPC_0_COMMON_S0_VID_IRQENABLE_2,This register allows to mask/unmask the VID internal sources of interrupt. on an event-by-event basis. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x18 4. "FBDC_ILLEGALTILEREQ_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x18 3. "FBDC_CORRUPTTILE_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x18 2. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x18 1. "VIDENDWINDOW_EN,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x18 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x1C "DISPC_0_COMMON_S0_VID_IRQENABLE_3,This register allows to mask/unmask the VID internal sources of interrupt. on an event-by-event basis. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x1C 4. "FBDC_ILLEGALTILEREQ_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x1C 3. "FBDC_CORRUPTTILE_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x1C 2. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x1C 1. "VIDENDWINDOW_EN,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x1C 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x20 "DISPC_0_COMMON_S0_VID_IRQSTATUS_0,This register groups all the status of the VID internal events that generate an interrupt. Write 1 to a clear a bit field. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x20 4. "FBDC_ILLEGALTILEREQ_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x20 3. "FBDC_CORRUPTTILE_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x20 2. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x20 1. "VIDENDWINDOW_IRQ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x20 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x24 "DISPC_0_COMMON_S0_VID_IRQSTATUS_1,This register groups all the status of the VID internal events that generate an interrupt. Write 1 to a clear a bit field. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x24 4. "FBDC_ILLEGALTILEREQ_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x24 3. "FBDC_CORRUPTTILE_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x24 2. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x24 1. "VIDENDWINDOW_IRQ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x24 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x28 "DISPC_0_COMMON_S0_VID_IRQSTATUS_2,This register groups all the status of the VID internal events that generate an interrupt. Write 1 to a clear a bit field. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x28 4. "FBDC_ILLEGALTILEREQ_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x28 3. "FBDC_CORRUPTTILE_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x28 2. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x28 1. "VIDENDWINDOW_IRQ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x28 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x2C "DISPC_0_COMMON_S0_VID_IRQSTATUS_3,This register groups all the status of the VID internal events that generate an interrupt. Write 1 to a clear a bit field. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x2C 4. "FBDC_ILLEGALTILEREQ_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x2C 3. "FBDC_CORRUPTTILE_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x2C 2. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x2C 1. "VIDENDWINDOW_IRQ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x2C 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x30 "DISPC_0_COMMON_S0_VP_IRQENABLE_0,This register allows to mask/unmask the VP_0 internal sources of interrupt. on an event-by-event basis" hexmask.long.byte 0x30 13.--16. 1. "SAFETYREGION1_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x30 12. "DUMMY_EN,Dummy IRQ for future use" "0,1" bitfld.long 0x30 11. "VPSYNC_EN,Go bit clear event" "0,1" newline bitfld.long 0x30 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x30 6.--9. 1. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x30 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x30 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1" bitfld.long 0x30 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x30 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1" newline bitfld.long 0x30 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1" bitfld.long 0x30 0. "VPFRAMEDONE_EN,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent" "0,1" line.long 0x34 "DISPC_0_COMMON_S0_VP_IRQENABLE_1,This register allows to mask/unmask the VP_1 internal sources of interrupt. on an event-by-event basis" hexmask.long.byte 0x34 13.--16. 1. "SAFETYREGION1_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x34 12. "DUMMY_EN,Dummy IRQ for future use" "0,1" bitfld.long 0x34 11. "VPSYNC_EN,Go bit clear event" "0,1" newline bitfld.long 0x34 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x34 6.--9. 1. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x34 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x34 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1" bitfld.long 0x34 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x34 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1" newline bitfld.long 0x34 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1" bitfld.long 0x34 0. "VPFRAMEDONE_EN,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent" "0,1" line.long 0x38 "DISPC_0_COMMON_S0_VP_IRQENABLE_2,This register allows to mask/unmask the VP_2 internal sources of interrupt. on an event-by-event basis" hexmask.long.byte 0x38 13.--16. 1. "SAFETYREGION1_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x38 12. "DUMMY_EN,Dummy IRQ for future use" "0,1" bitfld.long 0x38 11. "VPSYNC_EN,Go bit clear event" "0,1" newline bitfld.long 0x38 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x38 6.--9. 1. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x38 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x38 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1" bitfld.long 0x38 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x38 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1" newline bitfld.long 0x38 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1" bitfld.long 0x38 0. "VPFRAMEDONE_EN,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent" "0,1" line.long 0x3C "DISPC_0_COMMON_S0_VP_IRQENABLE_3,This register allows to mask/unmask the VP_3 internal sources of interrupt. on an event-by-event basis" hexmask.long.byte 0x3C 13.--16. 1. "SAFETYREGION1_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x3C 12. "DUMMY_EN,Dummy IRQ for future use" "0,1" bitfld.long 0x3C 11. "VPSYNC_EN,Go bit clear event" "0,1" newline bitfld.long 0x3C 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x3C 6.--9. 1. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x3C 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x3C 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1" bitfld.long 0x3C 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x3C 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1" newline bitfld.long 0x3C 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1" bitfld.long 0x3C 0. "VPFRAMEDONE_EN,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent" "0,1" line.long 0x40 "DISPC_0_COMMON_S0_VP_IRQSTATUS_0,This register groups all the status of the VP_0 internal events that generate an interrupt. Write 1 to a given bit resets this bit" hexmask.long.byte 0x40 13.--16. 1. "SAFETYREGION1_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x40 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1" bitfld.long 0x40 11. "VPSYNC_IRQ,Go bit clear event" "0,1" newline bitfld.long 0x40 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x40 6.--9. 1. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x40 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x40 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with VP output" "0,1" bitfld.long 0x40 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x40 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field. For interlace mode only" "0,1" newline bitfld.long 0x40 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output. It is used as VSYNC_EVEN in case of interlace mode" "0,1" bitfld.long 0x40 0. "VPFRAMEDONE_IRQ,Frame Done for VP. VP output has been disabled by user All the data have been sent" "0,1" line.long 0x44 "DISPC_0_COMMON_S0_VP_IRQSTATUS_1,This register groups all the status of the VP_1 internal events that generate an interrupt. Write 1 to a given bit resets this bit" hexmask.long.byte 0x44 13.--16. 1. "SAFETYREGION1_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x44 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1" bitfld.long 0x44 11. "VPSYNC_IRQ,Go bit clear event" "0,1" newline bitfld.long 0x44 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x44 6.--9. 1. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x44 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x44 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with VP output" "0,1" bitfld.long 0x44 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x44 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field. For interlace mode only" "0,1" newline bitfld.long 0x44 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output. It is used as VSYNC_EVEN in case of interlace mode" "0,1" bitfld.long 0x44 0. "VPFRAMEDONE_IRQ,Frame Done for VP. VP output has been disabled by user All the data have been sent" "0,1" line.long 0x48 "DISPC_0_COMMON_S0_VP_IRQSTATUS_2,This register groups all the status of the VP_2 internal events that generate an interrupt. Write 1 to a given bit resets this bit" hexmask.long.byte 0x48 13.--16. 1. "SAFETYREGION1_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x48 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1" bitfld.long 0x48 11. "VPSYNC_IRQ,Go bit clear event" "0,1" newline bitfld.long 0x48 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x48 6.--9. 1. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x48 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x48 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with VP output" "0,1" bitfld.long 0x48 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x48 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field. For interlace mode only" "0,1" newline bitfld.long 0x48 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output. It is used as VSYNC_EVEN in case of interlace mode" "0,1" bitfld.long 0x48 0. "VPFRAMEDONE_IRQ,Frame Done for VP. VP output has been disabled by user All the data have been sent" "0,1" line.long 0x4C "DISPC_0_COMMON_S0_VP_IRQSTATUS_3,This register groups all the status of the VP_3 internal events that generate an interrupt. Write 1 to a given bit resets this bit" hexmask.long.byte 0x4C 13.--16. 1. "SAFETYREGION1_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x4C 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1" bitfld.long 0x4C 11. "VPSYNC_IRQ,Go bit clear event" "0,1" newline bitfld.long 0x4C 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x4C 6.--9. 1. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x4C 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x4C 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with VP output" "0,1" bitfld.long 0x4C 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x4C 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field. For interlace mode only" "0,1" newline bitfld.long 0x4C 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output. It is used as VSYNC_EVEN in case of interlace mode" "0,1" bitfld.long 0x4C 0. "VPFRAMEDONE_IRQ,Frame Done for VP. VP output has been disabled by user All the data have been sent" "0,1" line.long 0x50 "DISPC_0_COMMON_S0_WB_IRQENABLE,This register allows to mask/unmask the WB internal sources of interrupt. if WB pipeline is present. on an event-by-event basis" bitfld.long 0x50 4. "WBSYNC_EN,Write-back sync IRQ. Configuration copied from shadow to work for WB for next frame" "0,1" bitfld.long 0x50 3. "SECURITYVIOLATION_EN,Security Violation IRQ. Non-secure WB connected to a secure VID/OVR" "0,1" bitfld.long 0x50 2. "WBFRAMEDONE_EN,Write-back Frame Done" "0,1" newline bitfld.long 0x50 1. "WBUNCOMPLETEERROR_EN,The write back buffer has been flushed before been fully drained. Can only occur in WB Capture Mode use-case" "0,1" bitfld.long 0x50 0. "WBBUFFEROVERFLOW_EN,Write-back DMA Buffer Overflow. Can only occur in WB Capture Mode use-case" "0,1" line.long 0x54 "DISPC_0_COMMON_S0_WB_IRQSTATUS,This register groups all the status of the WB internal events that generate an interrupt. if WB pipeline is present. Write 1 to a given bit resets this bit" bitfld.long 0x54 4. "WBSYNC_IRQ,Write-back sync IRQ. Configuration copied from shadow to work for WB for next frame" "0,1" bitfld.long 0x54 3. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure WB connected to a secure VID/OVR" "0,1" bitfld.long 0x54 2. "WBFRAMEDONE_IRQ,Write-back Frame Done" "0,1" newline bitfld.long 0x54 1. "WBUNCOMPLETEERROR_IRQ,Write back DMA buffer is flushed before been completely drained. Can only occur in WB Capture Mode use-case" "0,1" bitfld.long 0x54 0. "WBBUFFEROVERFLOW_IRQ,Write-back DMA Buffer Overflow The DMA buffer is full" "0,1" rgroup.long 0x80++0xB line.long 0x0 "DISPC_0_COMMON_S0_DISPC_IRQ_EOI_FUNC,End-Of-Interrupt register for FUNC interrupts. to be used if pulse interrupts are used" bitfld.long 0x0 0. "EOI,Write 1 to acknowledge a pulse IRQ" "0,1" line.long 0x4 "DISPC_0_COMMON_S0_DISPC_IRQ_EOI_SAFETY,End-Of-Interrupt register for SAFETY interrupts. to be used if pulse interrupts are used" bitfld.long 0x4 0. "EOI,Write 1 to acknowledge a pulse IRQ" "0,1" line.long 0x8 "DISPC_0_COMMON_S0_DISPC_IRQ_EOI_SECURITY,End-Of-Interrupt register for SECURITY interrupts. to be used if pulse interrupts are used" bitfld.long 0x8 0. "EOI,Write 1 to acknowledge a pulse IRQ" "0,1" tree.end tree "DSS0_DISPC_0_COMMON_S1 (DSS0_DISPC_0_COMMON_S1)" base ad:0x4B00000 rgroup.long 0x28++0x57 line.long 0x0 "DISPC_0_COMMON_S1_DISPC_IRQSTATUS_RAW,RAW Interrupt status. Raw status is set even if interrupt is not enabled. Write 1 to set the RAW status" bitfld.long 0x0 16. "DUMMY_IRQ,Dummy IRQ STATUS- Reserved for future use" "0,1" bitfld.long 0x0 15. "DUMMY1_IRQ,Dummy IRQ STATUS- Reserved for future use" "0,1" bitfld.long 0x0 14. "WB_IRQ,WB IRQ STATUS. Register indicates the WB pipeline interrupt events if WB pipeline is present" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "VID_IRQ,VID IRQ STATUS. Register indicates the Video pipeline[s] interrupt events. [0] -> VID1 [1] -> VIDL1 [2] -> VID2 [3] -> VIDL2" hexmask.long.byte 0x0 0.--3. 1. "VP_IRQ,VP[3:0] IRQ STATUS. Register indicates the Video Port[s] interrupt events" line.long 0x4 "DISPC_0_COMMON_S1_DISPC_IRQSTATUS,Interrupt status. Enabled status. isn't set unless event is enabled. Write 1 to clear the status after interrupt has been serviced. RAW status also gets cleared. i.e. even if not enabled" bitfld.long 0x4 16. "DUMMY_IRQ,Dummy IRQ STATUS-Reserved for future use" "0,1" bitfld.long 0x4 15. "DUMMY1_IRQ,Dummy IRQ STATUS-Reserved for future use" "0,1" bitfld.long 0x4 14. "WB_IRQ,WB IRQ STATUS. Register indicates the WB pipeline interrupt events if WB pipeline is present" "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "VID_IRQ,VID IRQ STATUS. Register indicates the Video pipeline[s] interrupt events. [0] -> VID1 [1] -> VIDL1 [2] -> VID2 [3] -> VIDL2" hexmask.long.byte 0x4 0.--3. 1. "VP_IRQ,VP IRQ STATUS. Register indicates the Video Port[s] interrupt events" line.long 0x8 "DISPC_0_COMMON_S1_DISPC_IRQENABLE_SET,SET Interrupt enable. Write 1 to set interrupt enable. Readout equal to corresponding _CLR register" bitfld.long 0x8 16. "SET_DUMMY_IRQ,Dummy IRQ" "0,1" bitfld.long 0x8 15. "SET_DUMMY1_IRQ,Dummy IRQ" "0,1" bitfld.long 0x8 14. "SET_WB_IRQ,WB IRQ if WB pipeline is present" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "SET_VID_IRQ,VID IRQ. [0] -> VID1 [1] -> VIDL1 [2] -> VID2 [3] -> VIDL2" hexmask.long.byte 0x8 0.--3. 1. "SET_VP_IRQ,VP IRQ" line.long 0xC "DISPC_0_COMMON_S1_DISPC_IRQENABLE_CLR,CLR Interrupt enable. Write 1 to clear interrupt enable" bitfld.long 0xC 16. "CLR_DUMMY_IRQ,Dummy IRQ" "0,1" bitfld.long 0xC 15. "CLR_DUMMY1_IRQ,Dummy IRQ" "0,1" bitfld.long 0xC 14. "CLR_WB_IRQ,WB IRQ if WB pipeline is present" "0,1" newline hexmask.long.byte 0xC 4.--7. 1. "CLR_VID_IRQ,VID IRQ. [0] -> VID1 [1] -> VIDL1 [2] -> VID2 [3] -> VIDL2" hexmask.long.byte 0xC 0.--3. 1. "CLR_VP_IRQ,VP IRQ" line.long 0x10 "DISPC_0_COMMON_S1_VID_IRQENABLE_0,This register allows to mask/unmask the VID internal sources of interrupt. on an event-by-event basis. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x10 4. "FBDC_ILLEGALTILEREQ_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x10 3. "FBDC_CORRUPTTILE_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x10 2. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x10 1. "VIDENDWINDOW_EN,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x10 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x14 "DISPC_0_COMMON_S1_VID_IRQENABLE_1,This register allows to mask/unmask the VID internal sources of interrupt. on an event-by-event basis. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x14 4. "FBDC_ILLEGALTILEREQ_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x14 3. "FBDC_CORRUPTTILE_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x14 2. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x14 1. "VIDENDWINDOW_EN,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x14 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x18 "DISPC_0_COMMON_S1_VID_IRQENABLE_2,This register allows to mask/unmask the VID internal sources of interrupt. on an event-by-event basis. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x18 4. "FBDC_ILLEGALTILEREQ_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x18 3. "FBDC_CORRUPTTILE_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x18 2. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x18 1. "VIDENDWINDOW_EN,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x18 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x1C "DISPC_0_COMMON_S1_VID_IRQENABLE_3,This register allows to mask/unmask the VID internal sources of interrupt. on an event-by-event basis. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x1C 4. "FBDC_ILLEGALTILEREQ_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x1C 3. "FBDC_CORRUPTTILE_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x1C 2. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x1C 1. "VIDENDWINDOW_EN,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x1C 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x20 "DISPC_0_COMMON_S1_VID_IRQSTATUS_0,This register groups all the status of the VID internal events that generate an interrupt. Write 1 to a clear a bit field. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x20 4. "FBDC_ILLEGALTILEREQ_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x20 3. "FBDC_CORRUPTTILE_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x20 2. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x20 1. "VIDENDWINDOW_IRQ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x20 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x24 "DISPC_0_COMMON_S1_VID_IRQSTATUS_1,This register groups all the status of the VID internal events that generate an interrupt. Write 1 to a clear a bit field. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x24 4. "FBDC_ILLEGALTILEREQ_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x24 3. "FBDC_CORRUPTTILE_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x24 2. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x24 1. "VIDENDWINDOW_IRQ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x24 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x28 "DISPC_0_COMMON_S1_VID_IRQSTATUS_2,This register groups all the status of the VID internal events that generate an interrupt. Write 1 to a clear a bit field. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x28 4. "FBDC_ILLEGALTILEREQ_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x28 3. "FBDC_CORRUPTTILE_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x28 2. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x28 1. "VIDENDWINDOW_IRQ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x28 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x2C "DISPC_0_COMMON_S1_VID_IRQSTATUS_3,This register groups all the status of the VID internal events that generate an interrupt. Write 1 to a clear a bit field. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x2C 4. "FBDC_ILLEGALTILEREQ_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x2C 3. "FBDC_CORRUPTTILE_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x2C 2. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x2C 1. "VIDENDWINDOW_IRQ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x2C 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x30 "DISPC_0_COMMON_S1_VP_IRQENABLE_0,This register allows to mask/unmask the VP_0 internal sources of interrupt. on an event-by-event basis" hexmask.long.byte 0x30 13.--16. 1. "SAFETYREGION1_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x30 12. "DUMMY_EN,Dummy IRQ for future use" "0,1" bitfld.long 0x30 11. "VPSYNC_EN,Go bit clear event" "0,1" newline bitfld.long 0x30 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x30 6.--9. 1. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x30 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x30 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1" bitfld.long 0x30 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x30 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1" newline bitfld.long 0x30 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1" bitfld.long 0x30 0. "VPFRAMEDONE_EN,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent" "0,1" line.long 0x34 "DISPC_0_COMMON_S1_VP_IRQENABLE_1,This register allows to mask/unmask the VP_1 internal sources of interrupt. on an event-by-event basis" hexmask.long.byte 0x34 13.--16. 1. "SAFETYREGION1_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x34 12. "DUMMY_EN,Dummy IRQ for future use" "0,1" bitfld.long 0x34 11. "VPSYNC_EN,Go bit clear event" "0,1" newline bitfld.long 0x34 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x34 6.--9. 1. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x34 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x34 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1" bitfld.long 0x34 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x34 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1" newline bitfld.long 0x34 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1" bitfld.long 0x34 0. "VPFRAMEDONE_EN,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent" "0,1" line.long 0x38 "DISPC_0_COMMON_S1_VP_IRQENABLE_2,This register allows to mask/unmask the VP_2 internal sources of interrupt. on an event-by-event basis" hexmask.long.byte 0x38 13.--16. 1. "SAFETYREGION1_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x38 12. "DUMMY_EN,Dummy IRQ for future use" "0,1" bitfld.long 0x38 11. "VPSYNC_EN,Go bit clear event" "0,1" newline bitfld.long 0x38 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x38 6.--9. 1. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x38 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x38 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1" bitfld.long 0x38 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x38 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1" newline bitfld.long 0x38 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1" bitfld.long 0x38 0. "VPFRAMEDONE_EN,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent" "0,1" line.long 0x3C "DISPC_0_COMMON_S1_VP_IRQENABLE_3,This register allows to mask/unmask the VP_3 internal sources of interrupt. on an event-by-event basis" hexmask.long.byte 0x3C 13.--16. 1. "SAFETYREGION1_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x3C 12. "DUMMY_EN,Dummy IRQ for future use" "0,1" bitfld.long 0x3C 11. "VPSYNC_EN,Go bit clear event" "0,1" newline bitfld.long 0x3C 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x3C 6.--9. 1. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x3C 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x3C 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1" bitfld.long 0x3C 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x3C 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1" newline bitfld.long 0x3C 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1" bitfld.long 0x3C 0. "VPFRAMEDONE_EN,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent" "0,1" line.long 0x40 "DISPC_0_COMMON_S1_VP_IRQSTATUS_0,This register groups all the status of the VP_0 internal events that generate an interrupt. Write 1 to a given bit resets this bit" hexmask.long.byte 0x40 13.--16. 1. "SAFETYREGION1_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x40 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1" bitfld.long 0x40 11. "VPSYNC_IRQ,Go bit clear event" "0,1" newline bitfld.long 0x40 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x40 6.--9. 1. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x40 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x40 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with VP output" "0,1" bitfld.long 0x40 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x40 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field. For interlace mode only" "0,1" newline bitfld.long 0x40 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output. It is used as VSYNC_EVEN in case of interlace mode" "0,1" bitfld.long 0x40 0. "VPFRAMEDONE_IRQ,Frame Done for VP. VP output has been disabled by user All the data have been sent" "0,1" line.long 0x44 "DISPC_0_COMMON_S1_VP_IRQSTATUS_1,This register groups all the status of the VP_1 internal events that generate an interrupt. Write 1 to a given bit resets this bit" hexmask.long.byte 0x44 13.--16. 1. "SAFETYREGION1_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x44 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1" bitfld.long 0x44 11. "VPSYNC_IRQ,Go bit clear event" "0,1" newline bitfld.long 0x44 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x44 6.--9. 1. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x44 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x44 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with VP output" "0,1" bitfld.long 0x44 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x44 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field. For interlace mode only" "0,1" newline bitfld.long 0x44 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output. It is used as VSYNC_EVEN in case of interlace mode" "0,1" bitfld.long 0x44 0. "VPFRAMEDONE_IRQ,Frame Done for VP. VP output has been disabled by user All the data have been sent" "0,1" line.long 0x48 "DISPC_0_COMMON_S1_VP_IRQSTATUS_2,This register groups all the status of the VP_2 internal events that generate an interrupt. Write 1 to a given bit resets this bit" hexmask.long.byte 0x48 13.--16. 1. "SAFETYREGION1_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x48 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1" bitfld.long 0x48 11. "VPSYNC_IRQ,Go bit clear event" "0,1" newline bitfld.long 0x48 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x48 6.--9. 1. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x48 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x48 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with VP output" "0,1" bitfld.long 0x48 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x48 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field. For interlace mode only" "0,1" newline bitfld.long 0x48 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output. It is used as VSYNC_EVEN in case of interlace mode" "0,1" bitfld.long 0x48 0. "VPFRAMEDONE_IRQ,Frame Done for VP. VP output has been disabled by user All the data have been sent" "0,1" line.long 0x4C "DISPC_0_COMMON_S1_VP_IRQSTATUS_3,This register groups all the status of the VP_3 internal events that generate an interrupt. Write 1 to a given bit resets this bit" hexmask.long.byte 0x4C 13.--16. 1. "SAFETYREGION1_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x4C 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1" bitfld.long 0x4C 11. "VPSYNC_IRQ,Go bit clear event" "0,1" newline bitfld.long 0x4C 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x4C 6.--9. 1. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x4C 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x4C 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with VP output" "0,1" bitfld.long 0x4C 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x4C 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field. For interlace mode only" "0,1" newline bitfld.long 0x4C 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output. It is used as VSYNC_EVEN in case of interlace mode" "0,1" bitfld.long 0x4C 0. "VPFRAMEDONE_IRQ,Frame Done for VP. VP output has been disabled by user All the data have been sent" "0,1" line.long 0x50 "DISPC_0_COMMON_S1_WB_IRQENABLE,This register allows to mask/unmask the WB internal sources of interrupt. if WB pipeline is present. on an event-by-event basis" bitfld.long 0x50 4. "WBSYNC_EN,Write-back sync IRQ. Configuration copied from shadow to work for WB for next frame" "0,1" bitfld.long 0x50 3. "SECURITYVIOLATION_EN,Security Violation IRQ. Non-secure WB connected to a secure VID/OVR" "0,1" bitfld.long 0x50 2. "WBFRAMEDONE_EN,Write-back Frame Done" "0,1" newline bitfld.long 0x50 1. "WBUNCOMPLETEERROR_EN,The write back buffer has been flushed before been fully drained. Can only occur in WB Capture Mode use-case" "0,1" bitfld.long 0x50 0. "WBBUFFEROVERFLOW_EN,Write-back DMA Buffer Overflow. Can only occur in WB Capture Mode use-case" "0,1" line.long 0x54 "DISPC_0_COMMON_S1_WB_IRQSTATUS,This register groups all the status of the WB internal events that generate an interrupt. if WB pipeline is present. Write 1 to a given bit resets this bit" bitfld.long 0x54 4. "WBSYNC_IRQ,Write-back sync IRQ. Configuration copied from shadow to work for WB for next frame" "0,1" bitfld.long 0x54 3. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure WB connected to a secure VID/OVR" "0,1" bitfld.long 0x54 2. "WBFRAMEDONE_IRQ,Write-back Frame Done" "0,1" newline bitfld.long 0x54 1. "WBUNCOMPLETEERROR_IRQ,Write back DMA buffer is flushed before been completely drained. Can only occur in WB Capture Mode use-case" "0,1" bitfld.long 0x54 0. "WBBUFFEROVERFLOW_IRQ,Write-back DMA Buffer Overflow The DMA buffer is full" "0,1" rgroup.long 0x80++0xB line.long 0x0 "DISPC_0_COMMON_S1_DISPC_IRQ_EOI_FUNC,End-Of-Interrupt register for FUNC interrupts. to be used if pulse interrupts are used" bitfld.long 0x0 0. "EOI,Write 1 to acknowledge a pulse IRQ" "0,1" line.long 0x4 "DISPC_0_COMMON_S1_DISPC_IRQ_EOI_SAFETY,End-Of-Interrupt register for SAFETY interrupts. to be used if pulse interrupts are used" bitfld.long 0x4 0. "EOI,Write 1 to acknowledge a pulse IRQ" "0,1" line.long 0x8 "DISPC_0_COMMON_S1_DISPC_IRQ_EOI_SECURITY,End-Of-Interrupt register for SECURITY interrupts. to be used if pulse interrupts are used" bitfld.long 0x8 0. "EOI,Write 1 to acknowledge a pulse IRQ" "0,1" tree.end tree "DSS0_DISPC_0_COMMON_S2 (DSS0_DISPC_0_COMMON_S2)" base ad:0x4B10000 rgroup.long 0x28++0x57 line.long 0x0 "DISPC_0_COMMON_S2_DISPC_IRQSTATUS_RAW,RAW Interrupt status. Raw status is set even if interrupt is not enabled. Write 1 to set the RAW status" bitfld.long 0x0 16. "DUMMY_IRQ,Dummy IRQ STATUS- Reserved for future use" "0,1" bitfld.long 0x0 15. "DUMMY1_IRQ,Dummy IRQ STATUS- Reserved for future use" "0,1" bitfld.long 0x0 14. "WB_IRQ,WB IRQ STATUS. Register indicates the WB pipeline interrupt events if WB pipeline is present" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "VID_IRQ,VID IRQ STATUS. Register indicates the Video pipeline[s] interrupt events. [0] -> VID1 [1] -> VIDL1 [2] -> VID2 [3] -> VIDL2" hexmask.long.byte 0x0 0.--3. 1. "VP_IRQ,VP[3:0] IRQ STATUS. Register indicates the Video Port[s] interrupt events" line.long 0x4 "DISPC_0_COMMON_S2_DISPC_IRQSTATUS,Interrupt status. Enabled status. isn't set unless event is enabled. Write 1 to clear the status after interrupt has been serviced. RAW status also gets cleared. i.e. even if not enabled" bitfld.long 0x4 16. "DUMMY_IRQ,Dummy IRQ STATUS-Reserved for future use" "0,1" bitfld.long 0x4 15. "DUMMY1_IRQ,Dummy IRQ STATUS-Reserved for future use" "0,1" bitfld.long 0x4 14. "WB_IRQ,WB IRQ STATUS. Register indicates the WB pipeline interrupt events if WB pipeline is present" "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "VID_IRQ,VID IRQ STATUS. Register indicates the Video pipeline[s] interrupt events. [0] -> VID1 [1] -> VIDL1 [2] -> VID2 [3] -> VIDL2" hexmask.long.byte 0x4 0.--3. 1. "VP_IRQ,VP IRQ STATUS. Register indicates the Video Port[s] interrupt events" line.long 0x8 "DISPC_0_COMMON_S2_DISPC_IRQENABLE_SET,SET Interrupt enable. Write 1 to set interrupt enable. Readout equal to corresponding _CLR register" bitfld.long 0x8 16. "SET_DUMMY_IRQ,Dummy IRQ" "0,1" bitfld.long 0x8 15. "SET_DUMMY1_IRQ,Dummy IRQ" "0,1" bitfld.long 0x8 14. "SET_WB_IRQ,WB IRQ if WB pipeline is present" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "SET_VID_IRQ,VID IRQ. [0] -> VID1 [1] -> VIDL1 [2] -> VID2 [3] -> VIDL2" hexmask.long.byte 0x8 0.--3. 1. "SET_VP_IRQ,VP IRQ" line.long 0xC "DISPC_0_COMMON_S2_DISPC_IRQENABLE_CLR,CLR Interrupt enable. Write 1 to clear interrupt enable" bitfld.long 0xC 16. "CLR_DUMMY_IRQ,Dummy IRQ" "0,1" bitfld.long 0xC 15. "CLR_DUMMY1_IRQ,Dummy IRQ" "0,1" bitfld.long 0xC 14. "CLR_WB_IRQ,WB IRQ if WB pipeline is present" "0,1" newline hexmask.long.byte 0xC 4.--7. 1. "CLR_VID_IRQ,VID IRQ. [0] -> VID1 [1] -> VIDL1 [2] -> VID2 [3] -> VIDL2" hexmask.long.byte 0xC 0.--3. 1. "CLR_VP_IRQ,VP IRQ" line.long 0x10 "DISPC_0_COMMON_S2_VID_IRQENABLE_0,This register allows to mask/unmask the VID internal sources of interrupt. on an event-by-event basis. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x10 4. "FBDC_ILLEGALTILEREQ_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x10 3. "FBDC_CORRUPTTILE_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x10 2. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x10 1. "VIDENDWINDOW_EN,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x10 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x14 "DISPC_0_COMMON_S2_VID_IRQENABLE_1,This register allows to mask/unmask the VID internal sources of interrupt. on an event-by-event basis. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x14 4. "FBDC_ILLEGALTILEREQ_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x14 3. "FBDC_CORRUPTTILE_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x14 2. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x14 1. "VIDENDWINDOW_EN,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x14 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x18 "DISPC_0_COMMON_S2_VID_IRQENABLE_2,This register allows to mask/unmask the VID internal sources of interrupt. on an event-by-event basis. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x18 4. "FBDC_ILLEGALTILEREQ_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x18 3. "FBDC_CORRUPTTILE_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x18 2. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x18 1. "VIDENDWINDOW_EN,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x18 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x1C "DISPC_0_COMMON_S2_VID_IRQENABLE_3,This register allows to mask/unmask the VID internal sources of interrupt. on an event-by-event basis. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x1C 4. "FBDC_ILLEGALTILEREQ_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x1C 3. "FBDC_CORRUPTTILE_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x1C 2. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x1C 1. "VIDENDWINDOW_EN,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x1C 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x20 "DISPC_0_COMMON_S2_VID_IRQSTATUS_0,This register groups all the status of the VID internal events that generate an interrupt. Write 1 to a clear a bit field. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x20 4. "FBDC_ILLEGALTILEREQ_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x20 3. "FBDC_CORRUPTTILE_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x20 2. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x20 1. "VIDENDWINDOW_IRQ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x20 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x24 "DISPC_0_COMMON_S2_VID_IRQSTATUS_1,This register groups all the status of the VID internal events that generate an interrupt. Write 1 to a clear a bit field. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x24 4. "FBDC_ILLEGALTILEREQ_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x24 3. "FBDC_CORRUPTTILE_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x24 2. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x24 1. "VIDENDWINDOW_IRQ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x24 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x28 "DISPC_0_COMMON_S2_VID_IRQSTATUS_2,This register groups all the status of the VID internal events that generate an interrupt. Write 1 to a clear a bit field. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x28 4. "FBDC_ILLEGALTILEREQ_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x28 3. "FBDC_CORRUPTTILE_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x28 2. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x28 1. "VIDENDWINDOW_IRQ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x28 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x2C "DISPC_0_COMMON_S2_VID_IRQSTATUS_3,This register groups all the status of the VID internal events that generate an interrupt. Write 1 to a clear a bit field. [0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2" bitfld.long 0x2C 4. "FBDC_ILLEGALTILEREQ_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x2C 3. "FBDC_CORRUPTTILE_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x2C 2. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" newline bitfld.long 0x2C 1. "VIDENDWINDOW_IRQ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x2C 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x30 "DISPC_0_COMMON_S2_VP_IRQENABLE_0,This register allows to mask/unmask the VP_0 internal sources of interrupt. on an event-by-event basis" hexmask.long.byte 0x30 13.--16. 1. "SAFETYREGION1_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x30 12. "DUMMY_EN,Dummy IRQ for future use" "0,1" bitfld.long 0x30 11. "VPSYNC_EN,Go bit clear event" "0,1" newline bitfld.long 0x30 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x30 6.--9. 1. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x30 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x30 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1" bitfld.long 0x30 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x30 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1" newline bitfld.long 0x30 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1" bitfld.long 0x30 0. "VPFRAMEDONE_EN,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent" "0,1" line.long 0x34 "DISPC_0_COMMON_S2_VP_IRQENABLE_1,This register allows to mask/unmask the VP_1 internal sources of interrupt. on an event-by-event basis" hexmask.long.byte 0x34 13.--16. 1. "SAFETYREGION1_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x34 12. "DUMMY_EN,Dummy IRQ for future use" "0,1" bitfld.long 0x34 11. "VPSYNC_EN,Go bit clear event" "0,1" newline bitfld.long 0x34 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x34 6.--9. 1. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x34 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x34 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1" bitfld.long 0x34 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x34 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1" newline bitfld.long 0x34 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1" bitfld.long 0x34 0. "VPFRAMEDONE_EN,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent" "0,1" line.long 0x38 "DISPC_0_COMMON_S2_VP_IRQENABLE_2,This register allows to mask/unmask the VP_2 internal sources of interrupt. on an event-by-event basis" hexmask.long.byte 0x38 13.--16. 1. "SAFETYREGION1_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x38 12. "DUMMY_EN,Dummy IRQ for future use" "0,1" bitfld.long 0x38 11. "VPSYNC_EN,Go bit clear event" "0,1" newline bitfld.long 0x38 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x38 6.--9. 1. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x38 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x38 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1" bitfld.long 0x38 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x38 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1" newline bitfld.long 0x38 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1" bitfld.long 0x38 0. "VPFRAMEDONE_EN,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent" "0,1" line.long 0x3C "DISPC_0_COMMON_S2_VP_IRQENABLE_3,This register allows to mask/unmask the VP_3 internal sources of interrupt. on an event-by-event basis" hexmask.long.byte 0x3C 13.--16. 1. "SAFETYREGION1_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x3C 12. "DUMMY_EN,Dummy IRQ for future use" "0,1" bitfld.long 0x3C 11. "VPSYNC_EN,Go bit clear event" "0,1" newline bitfld.long 0x3C 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x3C 6.--9. 1. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x3C 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x3C 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1" bitfld.long 0x3C 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x3C 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1" newline bitfld.long 0x3C 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1" bitfld.long 0x3C 0. "VPFRAMEDONE_EN,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent" "0,1" line.long 0x40 "DISPC_0_COMMON_S2_VP_IRQSTATUS_0,This register groups all the status of the VP_0 internal events that generate an interrupt. Write 1 to a given bit resets this bit" hexmask.long.byte 0x40 13.--16. 1. "SAFETYREGION1_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x40 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1" bitfld.long 0x40 11. "VPSYNC_IRQ,Go bit clear event" "0,1" newline bitfld.long 0x40 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x40 6.--9. 1. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x40 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x40 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with VP output" "0,1" bitfld.long 0x40 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x40 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field. For interlace mode only" "0,1" newline bitfld.long 0x40 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output. It is used as VSYNC_EVEN in case of interlace mode" "0,1" bitfld.long 0x40 0. "VPFRAMEDONE_IRQ,Frame Done for VP. VP output has been disabled by user All the data have been sent" "0,1" line.long 0x44 "DISPC_0_COMMON_S2_VP_IRQSTATUS_1,This register groups all the status of the VP_1 internal events that generate an interrupt. Write 1 to a given bit resets this bit" hexmask.long.byte 0x44 13.--16. 1. "SAFETYREGION1_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x44 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1" bitfld.long 0x44 11. "VPSYNC_IRQ,Go bit clear event" "0,1" newline bitfld.long 0x44 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x44 6.--9. 1. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x44 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x44 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with VP output" "0,1" bitfld.long 0x44 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x44 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field. For interlace mode only" "0,1" newline bitfld.long 0x44 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output. It is used as VSYNC_EVEN in case of interlace mode" "0,1" bitfld.long 0x44 0. "VPFRAMEDONE_IRQ,Frame Done for VP. VP output has been disabled by user All the data have been sent" "0,1" line.long 0x48 "DISPC_0_COMMON_S2_VP_IRQSTATUS_2,This register groups all the status of the VP_2 internal events that generate an interrupt. Write 1 to a given bit resets this bit" hexmask.long.byte 0x48 13.--16. 1. "SAFETYREGION1_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x48 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1" bitfld.long 0x48 11. "VPSYNC_IRQ,Go bit clear event" "0,1" newline bitfld.long 0x48 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x48 6.--9. 1. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x48 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x48 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with VP output" "0,1" bitfld.long 0x48 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x48 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field. For interlace mode only" "0,1" newline bitfld.long 0x48 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output. It is used as VSYNC_EVEN in case of interlace mode" "0,1" bitfld.long 0x48 0. "VPFRAMEDONE_IRQ,Frame Done for VP. VP output has been disabled by user All the data have been sent" "0,1" line.long 0x4C "DISPC_0_COMMON_S2_VP_IRQSTATUS_3,This register groups all the status of the VP_3 internal events that generate an interrupt. Write 1 to a given bit resets this bit" hexmask.long.byte 0x4C 13.--16. 1. "SAFETYREGION1_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 4-7" bitfld.long 0x4C 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1" bitfld.long 0x4C 11. "VPSYNC_IRQ,Go bit clear event" "0,1" newline bitfld.long 0x4C 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x4C 6.--9. 1. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0-3" bitfld.long 0x4C 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1" newline bitfld.long 0x4C 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with VP output" "0,1" bitfld.long 0x4C 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x4C 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field. For interlace mode only" "0,1" newline bitfld.long 0x4C 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output. It is used as VSYNC_EVEN in case of interlace mode" "0,1" bitfld.long 0x4C 0. "VPFRAMEDONE_IRQ,Frame Done for VP. VP output has been disabled by user All the data have been sent" "0,1" line.long 0x50 "DISPC_0_COMMON_S2_WB_IRQENABLE,This register allows to mask/unmask the WB internal sources of interrupt. if WB pipeline is present. on an event-by-event basis" bitfld.long 0x50 4. "WBSYNC_EN,Write-back sync IRQ. Configuration copied from shadow to work for WB for next frame" "0,1" bitfld.long 0x50 3. "SECURITYVIOLATION_EN,Security Violation IRQ. Non-secure WB connected to a secure VID/OVR" "0,1" bitfld.long 0x50 2. "WBFRAMEDONE_EN,Write-back Frame Done" "0,1" newline bitfld.long 0x50 1. "WBUNCOMPLETEERROR_EN,The write back buffer has been flushed before been fully drained. Can only occur in WB Capture Mode use-case" "0,1" bitfld.long 0x50 0. "WBBUFFEROVERFLOW_EN,Write-back DMA Buffer Overflow. Can only occur in WB Capture Mode use-case" "0,1" line.long 0x54 "DISPC_0_COMMON_S2_WB_IRQSTATUS,This register groups all the status of the WB internal events that generate an interrupt. if WB pipeline is present. Write 1 to a given bit resets this bit" bitfld.long 0x54 4. "WBSYNC_IRQ,Write-back sync IRQ. Configuration copied from shadow to work for WB for next frame" "0,1" bitfld.long 0x54 3. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure WB connected to a secure VID/OVR" "0,1" bitfld.long 0x54 2. "WBFRAMEDONE_IRQ,Write-back Frame Done" "0,1" newline bitfld.long 0x54 1. "WBUNCOMPLETEERROR_IRQ,Write back DMA buffer is flushed before been completely drained. Can only occur in WB Capture Mode use-case" "0,1" bitfld.long 0x54 0. "WBBUFFEROVERFLOW_IRQ,Write-back DMA Buffer Overflow The DMA buffer is full" "0,1" rgroup.long 0x80++0xB line.long 0x0 "DISPC_0_COMMON_S2_DISPC_IRQ_EOI_FUNC,End-Of-Interrupt register for FUNC interrupts. to be used if pulse interrupts are used" bitfld.long 0x0 0. "EOI,Write 1 to acknowledge a pulse IRQ" "0,1" line.long 0x4 "DISPC_0_COMMON_S2_DISPC_IRQ_EOI_SAFETY,End-Of-Interrupt register for SAFETY interrupts. to be used if pulse interrupts are used" bitfld.long 0x4 0. "EOI,Write 1 to acknowledge a pulse IRQ" "0,1" line.long 0x8 "DISPC_0_COMMON_S2_DISPC_IRQ_EOI_SECURITY,End-Of-Interrupt register for SECURITY interrupts. to be used if pulse interrupts are used" bitfld.long 0x8 0. "EOI,Write 1 to acknowledge a pulse IRQ" "0,1" tree.end tree.end tree "DSS0_OVR1 (DSS0_OVR1)" base ad:0x4A70000 rgroup.long 0x0++0x4B line.long 0x0 "DISPC_0_OVR1_CONFIG,The control register configures the Display Controller module for the VP output. Shadow register" hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED1," rbitfld.long 0x0 13. "RESERVED3," "0,1" rbitfld.long 0x0 12. "RESERVED2," "0,1" bitfld.long 0x0 11. "TCKLCDSELECTION,Transparency Color Key Selection" "0,1" bitfld.long 0x0 10. "TCKLCDENABLE,Transparency Color Key Enable" "0,1" newline hexmask.long.byte 0x0 2.--9. 1. "RESERVED," bitfld.long 0x0 1. "COLORBAREN,Enable the Color-Bar" "0,1" rbitfld.long 0x0 0. "RESERVED6," "0,1" line.long 0x4 "DISPC_0_OVR1_VIRTUALVP,Configures the new VIRTUAL VP operation. Shadow register" bitfld.long 0x4 31. "ENABLE,Enable the Virtual VP Operation" "0,1" hexmask.long.word 0x4 16.--29. 1. "LPP,Lines per panel Encoded value [from 1 to 16384] to specify the number of lines on the Virtual VP [program to value minus 1]" hexmask.long.word 0x4 0.--13. 1. "PPL,Pixels per line Encoded value [from 1 to 16384] to specify the number of pixels contains within each line on the Virtual VP [program to value minus 1]" line.long 0x8 "DISPC_0_OVR1_DEFAULT_COLOR,The control register configures the default solid background color LSB[31:0]. Shadow register" hexmask.long 0x8 0.--31. 1. "DEFAULTCOLOR,32-bit LSB of ARGB background color" line.long 0xC "DISPC_0_OVR1_DEFAULT_COLOR2,The control register configures the default solid background color MSB[47:32]. Shadow register" hexmask.long.word 0xC 16.--31. 1. "RESERVED," hexmask.long.word 0xC 0.--15. 1. "DEFAULTCOLOR,16-bit MSB of ARGB background color" line.long 0x10 "DISPC_0_OVR1_TRANS_COLOR_MAX,The register sets the max transparency color value for the overlays. Shadow register" hexmask.long 0x10 0.--31. 1. "TRANSCOLORKEY,LSB[31:0]. Transparency Color Key Value in 36-bit RGB format" line.long 0x14 "DISPC_0_OVR1_TRANS_COLOR_MAX2,The register sets the max transparency color value for the overlays. Shadow register" hexmask.long 0x14 4.--31. 1. "RESERVED," hexmask.long.byte 0x14 0.--3. 1. "TRANSCOLORKEY,MSB[35:32]. Transparency Color Key Value in 36-bit RGB format" line.long 0x18 "DISPC_0_OVR1_TRANS_COLOR_MIN,The register sets the min transparency color value for the overlays. Shadow register" hexmask.long 0x18 0.--31. 1. "TRANSCOLORKEY,LSB[31:0]. Transparency Color Key Value in 36-bit RGB format" line.long 0x1C "DISPC_0_OVR1_TRANS_COLOR_MIN2,The register sets the min transparency color value for the overlays. Shadow register" hexmask.long 0x1C 4.--31. 1. "RESERVED," hexmask.long.byte 0x1C 0.--3. 1. "TRANSCOLORKEY,MSB[35:32]. Transparency Color Key Value in 36-bit RGB format" line.long 0x20 "DISPC_0_OVR1_ATTRIBUTES_0,The register configures the attributes of layer-0. ZORDER= 0. of the Overlay manager. Shadow register" hexmask.long.byte 0x20 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x20 0. "ENABLE,Layer Enable" "0,1" line.long 0x24 "DISPC_0_OVR1_ATTRIBUTES_1,The register configures the attributes of layer-1. ZORDER= 1. of the Overlay manager. Shadow register" hexmask.long.byte 0x24 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x24 0. "ENABLE,Layer Enable" "0,1" line.long 0x28 "DISPC_0_OVR1_ATTRIBUTES_2,The register configures the attributes of layer-2. ZORDER= 2. of the Overlay manager. Shadow register" hexmask.long.byte 0x28 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x28 0. "ENABLE,Layer Enable" "0,1" line.long 0x2C "DISPC_0_OVR1_ATTRIBUTES_3,The register configures the attributes of layer-3. ZORDER= 3. of the Overlay manager. Shadow register" hexmask.long.byte 0x2C 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x2C 0. "ENABLE,Layer Enable" "0,1" line.long 0x30 "DISPC_0_OVR1_ATTRIBUTES_4,The register configures the attributes of layer-4. ZORDER= 4. of the Overlay manager. Shadow register" hexmask.long.byte 0x30 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x30 0. "ENABLE,Layer Enable" "0,1" line.long 0x34 "DISPC_0_OVR1_ATTRIBUTES2_0,The register configures the additional attributes of layer-0. ZORDER= 0. of the Overlay manager. Shadow register" hexmask.long.word 0x34 16.--29. 1. "POSY,Y position of the layer. Encoded value [from 0 to 16383] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" hexmask.long.word 0x34 0.--13. 1. "POSX,X position of the layer. Encoded value [from 0 to 16383] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x38 "DISPC_0_OVR1_ATTRIBUTES2_1,The register configures the additional attributes of layer-1. ZORDER= 1. of the Overlay manager. Shadow register" hexmask.long.word 0x38 16.--29. 1. "POSY,Y position of the layer. Encoded value [from 0 to 16383] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" hexmask.long.word 0x38 0.--13. 1. "POSX,X position of the layer. Encoded value [from 0 to 16383] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x3C "DISPC_0_OVR1_ATTRIBUTES2_2,The register configures the additional attributes of layer-2. ZORDER= 2. of the Overlay manager. Shadow register" hexmask.long.word 0x3C 16.--29. 1. "POSY,Y position of the layer. Encoded value [from 0 to 16383] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" hexmask.long.word 0x3C 0.--13. 1. "POSX,X position of the layer. Encoded value [from 0 to 16383] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x40 "DISPC_0_OVR1_ATTRIBUTES2_3,The register configures the additional attributes of layer-3. ZORDER= 3. of the Overlay manager. Shadow register" hexmask.long.word 0x40 16.--29. 1. "POSY,Y position of the layer. Encoded value [from 0 to 16383] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" hexmask.long.word 0x40 0.--13. 1. "POSX,X position of the layer. Encoded value [from 0 to 16383] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x44 "DISPC_0_OVR1_ATTRIBUTES2_4,The register configures the additional attributes of layer-4. ZORDER= 4. of the Overlay manager. Shadow register" hexmask.long.word 0x44 16.--29. 1. "POSY,Y position of the layer. Encoded value [from 0 to 16383] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" hexmask.long.word 0x44 0.--13. 1. "POSX,X position of the layer. Encoded value [from 0 to 16383] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x48 "DISPC_0_OVR1_SECURE,Security bit settings for the sub-module" bitfld.long 0x48 0. "SECURE,Secure bit" "0,1" tree.end tree "DSS0_OVR2 (DSS0_OVR2)" base ad:0x4A90000 rgroup.long 0x0++0x4B line.long 0x0 "DISPC_0_OVR2_CONFIG,The control register configures the Display Controller module for the VP output. Shadow register" hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED1," rbitfld.long 0x0 13. "RESERVED3," "0,1" rbitfld.long 0x0 12. "RESERVED2," "0,1" bitfld.long 0x0 11. "TCKLCDSELECTION,Transparency Color Key Selection" "0,1" bitfld.long 0x0 10. "TCKLCDENABLE,Transparency Color Key Enable" "0,1" newline hexmask.long.byte 0x0 2.--9. 1. "RESERVED," bitfld.long 0x0 1. "COLORBAREN,Enable the Color-Bar" "0,1" rbitfld.long 0x0 0. "RESERVED6," "0,1" line.long 0x4 "DISPC_0_OVR2_VIRTUALVP,Configures the new VIRTUAL VP operation. Shadow register" bitfld.long 0x4 31. "ENABLE,Enable the Virtual VP Operation" "0,1" hexmask.long.word 0x4 16.--29. 1. "LPP,Lines per panel Encoded value [from 1 to 16384] to specify the number of lines on the Virtual VP [program to value minus 1]" hexmask.long.word 0x4 0.--13. 1. "PPL,Pixels per line Encoded value [from 1 to 16384] to specify the number of pixels contains within each line on the Virtual VP [program to value minus 1]" line.long 0x8 "DISPC_0_OVR2_DEFAULT_COLOR,The control register configures the default solid background color LSB[31:0]. Shadow register" hexmask.long 0x8 0.--31. 1. "DEFAULTCOLOR,32-bit LSB of ARGB background color" line.long 0xC "DISPC_0_OVR2_DEFAULT_COLOR2,The control register configures the default solid background color MSB[47:32]. Shadow register" hexmask.long.word 0xC 16.--31. 1. "RESERVED," hexmask.long.word 0xC 0.--15. 1. "DEFAULTCOLOR,16-bit MSB of ARGB background color" line.long 0x10 "DISPC_0_OVR2_TRANS_COLOR_MAX,The register sets the max transparency color value for the overlays. Shadow register" hexmask.long 0x10 0.--31. 1. "TRANSCOLORKEY,LSB[31:0]. Transparency Color Key Value in 36-bit RGB format" line.long 0x14 "DISPC_0_OVR2_TRANS_COLOR_MAX2,The register sets the max transparency color value for the overlays. Shadow register" hexmask.long 0x14 4.--31. 1. "RESERVED," hexmask.long.byte 0x14 0.--3. 1. "TRANSCOLORKEY,MSB[35:32]. Transparency Color Key Value in 36-bit RGB format" line.long 0x18 "DISPC_0_OVR2_TRANS_COLOR_MIN,The register sets the min transparency color value for the overlays. Shadow register" hexmask.long 0x18 0.--31. 1. "TRANSCOLORKEY,LSB[31:0]. Transparency Color Key Value in 36-bit RGB format" line.long 0x1C "DISPC_0_OVR2_TRANS_COLOR_MIN2,The register sets the min transparency color value for the overlays. Shadow register" hexmask.long 0x1C 4.--31. 1. "RESERVED," hexmask.long.byte 0x1C 0.--3. 1. "TRANSCOLORKEY,MSB[35:32]. Transparency Color Key Value in 36-bit RGB format" line.long 0x20 "DISPC_0_OVR2_ATTRIBUTES_0,The register configures the attributes of layer-0. ZORDER= 0. of the Overlay manager. Shadow register" hexmask.long.byte 0x20 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x20 0. "ENABLE,Layer Enable" "0,1" line.long 0x24 "DISPC_0_OVR2_ATTRIBUTES_1,The register configures the attributes of layer-1. ZORDER= 1. of the Overlay manager. Shadow register" hexmask.long.byte 0x24 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x24 0. "ENABLE,Layer Enable" "0,1" line.long 0x28 "DISPC_0_OVR2_ATTRIBUTES_2,The register configures the attributes of layer-2. ZORDER= 2. of the Overlay manager. Shadow register" hexmask.long.byte 0x28 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x28 0. "ENABLE,Layer Enable" "0,1" line.long 0x2C "DISPC_0_OVR2_ATTRIBUTES_3,The register configures the attributes of layer-3. ZORDER= 3. of the Overlay manager. Shadow register" hexmask.long.byte 0x2C 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x2C 0. "ENABLE,Layer Enable" "0,1" line.long 0x30 "DISPC_0_OVR2_ATTRIBUTES_4,The register configures the attributes of layer-4. ZORDER= 4. of the Overlay manager. Shadow register" hexmask.long.byte 0x30 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x30 0. "ENABLE,Layer Enable" "0,1" line.long 0x34 "DISPC_0_OVR2_ATTRIBUTES2_0,The register configures the additional attributes of layer-0. ZORDER= 0. of the Overlay manager. Shadow register" hexmask.long.word 0x34 16.--29. 1. "POSY,Y position of the layer. Encoded value [from 0 to 16383] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" hexmask.long.word 0x34 0.--13. 1. "POSX,X position of the layer. Encoded value [from 0 to 16383] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x38 "DISPC_0_OVR2_ATTRIBUTES2_1,The register configures the additional attributes of layer-1. ZORDER= 1. of the Overlay manager. Shadow register" hexmask.long.word 0x38 16.--29. 1. "POSY,Y position of the layer. Encoded value [from 0 to 16383] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" hexmask.long.word 0x38 0.--13. 1. "POSX,X position of the layer. Encoded value [from 0 to 16383] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x3C "DISPC_0_OVR2_ATTRIBUTES2_2,The register configures the additional attributes of layer-2. ZORDER= 2. of the Overlay manager. Shadow register" hexmask.long.word 0x3C 16.--29. 1. "POSY,Y position of the layer. Encoded value [from 0 to 16383] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" hexmask.long.word 0x3C 0.--13. 1. "POSX,X position of the layer. Encoded value [from 0 to 16383] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x40 "DISPC_0_OVR2_ATTRIBUTES2_3,The register configures the additional attributes of layer-3. ZORDER= 3. of the Overlay manager. Shadow register" hexmask.long.word 0x40 16.--29. 1. "POSY,Y position of the layer. Encoded value [from 0 to 16383] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" hexmask.long.word 0x40 0.--13. 1. "POSX,X position of the layer. Encoded value [from 0 to 16383] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x44 "DISPC_0_OVR2_ATTRIBUTES2_4,The register configures the additional attributes of layer-4. ZORDER= 4. of the Overlay manager. Shadow register" hexmask.long.word 0x44 16.--29. 1. "POSY,Y position of the layer. Encoded value [from 0 to 16383] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" hexmask.long.word 0x44 0.--13. 1. "POSX,X position of the layer. Encoded value [from 0 to 16383] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x48 "DISPC_0_OVR2_SECURE,Security bit settings for the sub-module" bitfld.long 0x48 0. "SECURE,Secure bit" "0,1" tree.end tree "DSS0_OVR3 (DSS0_OVR3)" base ad:0x4AB0000 rgroup.long 0x0++0x4B line.long 0x0 "DISPC_0_OVR3_CONFIG,The control register configures the Display Controller module for the VP output. Shadow register" hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED1," rbitfld.long 0x0 13. "RESERVED3," "0,1" rbitfld.long 0x0 12. "RESERVED2," "0,1" bitfld.long 0x0 11. "TCKLCDSELECTION,Transparency Color Key Selection" "0,1" bitfld.long 0x0 10. "TCKLCDENABLE,Transparency Color Key Enable" "0,1" newline hexmask.long.byte 0x0 2.--9. 1. "RESERVED," bitfld.long 0x0 1. "COLORBAREN,Enable the Color-Bar" "0,1" rbitfld.long 0x0 0. "RESERVED6," "0,1" line.long 0x4 "DISPC_0_OVR3_VIRTUALVP,Configures the new VIRTUAL VP operation. Shadow register" bitfld.long 0x4 31. "ENABLE,Enable the Virtual VP Operation" "0,1" hexmask.long.word 0x4 16.--29. 1. "LPP,Lines per panel Encoded value [from 1 to 16384] to specify the number of lines on the Virtual VP [program to value minus 1]" hexmask.long.word 0x4 0.--13. 1. "PPL,Pixels per line Encoded value [from 1 to 16384] to specify the number of pixels contains within each line on the Virtual VP [program to value minus 1]" line.long 0x8 "DISPC_0_OVR3_DEFAULT_COLOR,The control register configures the default solid background color LSB[31:0]. Shadow register" hexmask.long 0x8 0.--31. 1. "DEFAULTCOLOR,32-bit LSB of ARGB background color" line.long 0xC "DISPC_0_OVR3_DEFAULT_COLOR2,The control register configures the default solid background color MSB[47:32]. Shadow register" hexmask.long.word 0xC 16.--31. 1. "RESERVED," hexmask.long.word 0xC 0.--15. 1. "DEFAULTCOLOR,16-bit MSB of ARGB background color" line.long 0x10 "DISPC_0_OVR3_TRANS_COLOR_MAX,The register sets the max transparency color value for the overlays. Shadow register" hexmask.long 0x10 0.--31. 1. "TRANSCOLORKEY,LSB[31:0]. Transparency Color Key Value in 36-bit RGB format" line.long 0x14 "DISPC_0_OVR3_TRANS_COLOR_MAX2,The register sets the max transparency color value for the overlays. Shadow register" hexmask.long 0x14 4.--31. 1. "RESERVED," hexmask.long.byte 0x14 0.--3. 1. "TRANSCOLORKEY,MSB[35:32]. Transparency Color Key Value in 36-bit RGB format" line.long 0x18 "DISPC_0_OVR3_TRANS_COLOR_MIN,The register sets the min transparency color value for the overlays. Shadow register" hexmask.long 0x18 0.--31. 1. "TRANSCOLORKEY,LSB[31:0]. Transparency Color Key Value in 36-bit RGB format" line.long 0x1C "DISPC_0_OVR3_TRANS_COLOR_MIN2,The register sets the min transparency color value for the overlays. Shadow register" hexmask.long 0x1C 4.--31. 1. "RESERVED," hexmask.long.byte 0x1C 0.--3. 1. "TRANSCOLORKEY,MSB[35:32]. Transparency Color Key Value in 36-bit RGB format" line.long 0x20 "DISPC_0_OVR3_ATTRIBUTES_0,The register configures the attributes of layer-0. ZORDER= 0. of the Overlay manager. Shadow register" hexmask.long.byte 0x20 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x20 0. "ENABLE,Layer Enable" "0,1" line.long 0x24 "DISPC_0_OVR3_ATTRIBUTES_1,The register configures the attributes of layer-1. ZORDER= 1. of the Overlay manager. Shadow register" hexmask.long.byte 0x24 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x24 0. "ENABLE,Layer Enable" "0,1" line.long 0x28 "DISPC_0_OVR3_ATTRIBUTES_2,The register configures the attributes of layer-2. ZORDER= 2. of the Overlay manager. Shadow register" hexmask.long.byte 0x28 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x28 0. "ENABLE,Layer Enable" "0,1" line.long 0x2C "DISPC_0_OVR3_ATTRIBUTES_3,The register configures the attributes of layer-3. ZORDER= 3. of the Overlay manager. Shadow register" hexmask.long.byte 0x2C 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x2C 0. "ENABLE,Layer Enable" "0,1" line.long 0x30 "DISPC_0_OVR3_ATTRIBUTES_4,The register configures the attributes of layer-4. ZORDER= 4. of the Overlay manager. Shadow register" hexmask.long.byte 0x30 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x30 0. "ENABLE,Layer Enable" "0,1" line.long 0x34 "DISPC_0_OVR3_ATTRIBUTES2_0,The register configures the additional attributes of layer-0. ZORDER= 0. of the Overlay manager. Shadow register" hexmask.long.word 0x34 16.--29. 1. "POSY,Y position of the layer. Encoded value [from 0 to 16383] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" hexmask.long.word 0x34 0.--13. 1. "POSX,X position of the layer. Encoded value [from 0 to 16383] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x38 "DISPC_0_OVR3_ATTRIBUTES2_1,The register configures the additional attributes of layer-1. ZORDER= 1. of the Overlay manager. Shadow register" hexmask.long.word 0x38 16.--29. 1. "POSY,Y position of the layer. Encoded value [from 0 to 16383] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" hexmask.long.word 0x38 0.--13. 1. "POSX,X position of the layer. Encoded value [from 0 to 16383] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x3C "DISPC_0_OVR3_ATTRIBUTES2_2,The register configures the additional attributes of layer-2. ZORDER= 2. of the Overlay manager. Shadow register" hexmask.long.word 0x3C 16.--29. 1. "POSY,Y position of the layer. Encoded value [from 0 to 16383] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" hexmask.long.word 0x3C 0.--13. 1. "POSX,X position of the layer. Encoded value [from 0 to 16383] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x40 "DISPC_0_OVR3_ATTRIBUTES2_3,The register configures the additional attributes of layer-3. ZORDER= 3. of the Overlay manager. Shadow register" hexmask.long.word 0x40 16.--29. 1. "POSY,Y position of the layer. Encoded value [from 0 to 16383] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" hexmask.long.word 0x40 0.--13. 1. "POSX,X position of the layer. Encoded value [from 0 to 16383] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x44 "DISPC_0_OVR3_ATTRIBUTES2_4,The register configures the additional attributes of layer-4. ZORDER= 4. of the Overlay manager. Shadow register" hexmask.long.word 0x44 16.--29. 1. "POSY,Y position of the layer. Encoded value [from 0 to 16383] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" hexmask.long.word 0x44 0.--13. 1. "POSX,X position of the layer. Encoded value [from 0 to 16383] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x48 "DISPC_0_OVR3_SECURE,Security bit settings for the sub-module" bitfld.long 0x48 0. "SECURE,Secure bit" "0,1" tree.end tree "DSS0_OVR4 (DSS0_OVR4)" base ad:0x4AD0000 rgroup.long 0x0++0x4B line.long 0x0 "DISPC_0_OVR4_CONFIG,The control register configures the Display Controller module for the VP output. Shadow register" hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED1," rbitfld.long 0x0 13. "RESERVED3," "0,1" rbitfld.long 0x0 12. "RESERVED2," "0,1" bitfld.long 0x0 11. "TCKLCDSELECTION,Transparency Color Key Selection" "0,1" bitfld.long 0x0 10. "TCKLCDENABLE,Transparency Color Key Enable" "0,1" newline hexmask.long.byte 0x0 2.--9. 1. "RESERVED," bitfld.long 0x0 1. "COLORBAREN,Enable the Color-Bar" "0,1" rbitfld.long 0x0 0. "RESERVED6," "0,1" line.long 0x4 "DISPC_0_OVR4_VIRTUALVP,Configures the new VIRTUAL VP operation. Shadow register" bitfld.long 0x4 31. "ENABLE,Enable the Virtual VP Operation" "0,1" hexmask.long.word 0x4 16.--29. 1. "LPP,Lines per panel Encoded value [from 1 to 16384] to specify the number of lines on the Virtual VP [program to value minus 1]" hexmask.long.word 0x4 0.--13. 1. "PPL,Pixels per line Encoded value [from 1 to 16384] to specify the number of pixels contains within each line on the Virtual VP [program to value minus 1]" line.long 0x8 "DISPC_0_OVR4_DEFAULT_COLOR,The control register configures the default solid background color LSB[31:0]. Shadow register" hexmask.long 0x8 0.--31. 1. "DEFAULTCOLOR,32-bit LSB of ARGB background color" line.long 0xC "DISPC_0_OVR4_DEFAULT_COLOR2,The control register configures the default solid background color MSB[47:32]. Shadow register" hexmask.long.word 0xC 16.--31. 1. "RESERVED," hexmask.long.word 0xC 0.--15. 1. "DEFAULTCOLOR,16-bit MSB of ARGB background color" line.long 0x10 "DISPC_0_OVR4_TRANS_COLOR_MAX,The register sets the max transparency color value for the overlays. Shadow register" hexmask.long 0x10 0.--31. 1. "TRANSCOLORKEY,LSB[31:0]. Transparency Color Key Value in 36-bit RGB format" line.long 0x14 "DISPC_0_OVR4_TRANS_COLOR_MAX2,The register sets the max transparency color value for the overlays. Shadow register" hexmask.long 0x14 4.--31. 1. "RESERVED," hexmask.long.byte 0x14 0.--3. 1. "TRANSCOLORKEY,MSB[35:32]. Transparency Color Key Value in 36-bit RGB format" line.long 0x18 "DISPC_0_OVR4_TRANS_COLOR_MIN,The register sets the min transparency color value for the overlays. Shadow register" hexmask.long 0x18 0.--31. 1. "TRANSCOLORKEY,LSB[31:0]. Transparency Color Key Value in 36-bit RGB format" line.long 0x1C "DISPC_0_OVR4_TRANS_COLOR_MIN2,The register sets the min transparency color value for the overlays. Shadow register" hexmask.long 0x1C 4.--31. 1. "RESERVED," hexmask.long.byte 0x1C 0.--3. 1. "TRANSCOLORKEY,MSB[35:32]. Transparency Color Key Value in 36-bit RGB format" line.long 0x20 "DISPC_0_OVR4_ATTRIBUTES_0,The register configures the attributes of layer-0. ZORDER= 0. of the Overlay manager. Shadow register" hexmask.long.byte 0x20 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x20 0. "ENABLE,Layer Enable" "0,1" line.long 0x24 "DISPC_0_OVR4_ATTRIBUTES_1,The register configures the attributes of layer-1. ZORDER= 1. of the Overlay manager. Shadow register" hexmask.long.byte 0x24 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x24 0. "ENABLE,Layer Enable" "0,1" line.long 0x28 "DISPC_0_OVR4_ATTRIBUTES_2,The register configures the attributes of layer-2. ZORDER= 2. of the Overlay manager. Shadow register" hexmask.long.byte 0x28 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x28 0. "ENABLE,Layer Enable" "0,1" line.long 0x2C "DISPC_0_OVR4_ATTRIBUTES_3,The register configures the attributes of layer-3. ZORDER= 3. of the Overlay manager. Shadow register" hexmask.long.byte 0x2C 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x2C 0. "ENABLE,Layer Enable" "0,1" line.long 0x30 "DISPC_0_OVR4_ATTRIBUTES_4,The register configures the attributes of layer-4. ZORDER= 4. of the Overlay manager. Shadow register" hexmask.long.byte 0x30 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x30 0. "ENABLE,Layer Enable" "0,1" line.long 0x34 "DISPC_0_OVR4_ATTRIBUTES2_0,The register configures the additional attributes of layer-0. ZORDER= 0. of the Overlay manager. Shadow register" hexmask.long.word 0x34 16.--29. 1. "POSY,Y position of the layer. Encoded value [from 0 to 16383] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" hexmask.long.word 0x34 0.--13. 1. "POSX,X position of the layer. Encoded value [from 0 to 16383] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x38 "DISPC_0_OVR4_ATTRIBUTES2_1,The register configures the additional attributes of layer-1. ZORDER= 1. of the Overlay manager. Shadow register" hexmask.long.word 0x38 16.--29. 1. "POSY,Y position of the layer. Encoded value [from 0 to 16383] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" hexmask.long.word 0x38 0.--13. 1. "POSX,X position of the layer. Encoded value [from 0 to 16383] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x3C "DISPC_0_OVR4_ATTRIBUTES2_2,The register configures the additional attributes of layer-2. ZORDER= 2. of the Overlay manager. Shadow register" hexmask.long.word 0x3C 16.--29. 1. "POSY,Y position of the layer. Encoded value [from 0 to 16383] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" hexmask.long.word 0x3C 0.--13. 1. "POSX,X position of the layer. Encoded value [from 0 to 16383] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x40 "DISPC_0_OVR4_ATTRIBUTES2_3,The register configures the additional attributes of layer-3. ZORDER= 3. of the Overlay manager. Shadow register" hexmask.long.word 0x40 16.--29. 1. "POSY,Y position of the layer. Encoded value [from 0 to 16383] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" hexmask.long.word 0x40 0.--13. 1. "POSX,X position of the layer. Encoded value [from 0 to 16383] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x44 "DISPC_0_OVR4_ATTRIBUTES2_4,The register configures the additional attributes of layer-4. ZORDER= 4. of the Overlay manager. Shadow register" hexmask.long.word 0x44 16.--29. 1. "POSY,Y position of the layer. Encoded value [from 0 to 16383] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" hexmask.long.word 0x44 0.--13. 1. "POSX,X position of the layer. Encoded value [from 0 to 16383] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x48 "DISPC_0_OVR4_SECURE,Security bit settings for the sub-module" bitfld.long 0x48 0. "SECURE,Secure bit" "0,1" tree.end tree "DSS0_VID1 (DSS0_VID1)" base ad:0x4A50000 rgroup.long 0x0++0x37 line.long 0x0 "DISPC_0_VID1_ACCUH_0,The register configures the resize accumulator init values for horizontal up/down-sampling of the video window. DISPC_VIDx_ACCU__0 & DISPC_VIDx_ACCU__1 for ping-pong mechanism with external trigger. based on the field polarity. This.." hexmask.long.tbyte 0x0 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x4 "DISPC_0_VID1_ACCUH_1,The register configures the resize accumulator init values for horizontal up/down-sampling of the video window. DISPC_VIDx_ACCU__0 & DISPC_VIDx_ACCU__1 for ping-pong mechanism with external trigger. based on the field polarity. This.." hexmask.long.tbyte 0x4 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x8 "DISPC_0_VID1_ACCUH2_0,The register configures the resize accumulator init value for horizontal up/down-sampling of the video window. DISPC_VID n_ACCU2__0 & DISPC_VID n_ACCU2__1 for ping-pong mechanism with external trigger. based on the field polarity." hexmask.long.tbyte 0x8 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0xC "DISPC_0_VID1_ACCUH2_1,The register configures the resize accumulator init value for horizontal up/down-sampling of the video window. DISPC_VID n_ACCU2__0 & DISPC_VID n_ACCU2__1 for ping-pong mechanism with external trigger. based on the field polarity." hexmask.long.tbyte 0xC 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x10 "DISPC_0_VID1_ACCUV_0,The register configures the resize accumulator init values for horizontal and vertical up/down-sampling of the video window. DISPC_VIDx_ACCU__0 & DISPC_VIDx_ACCU__1 for ping-pong mechanism with external trigger. based on the field.." hexmask.long.tbyte 0x10 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x14 "DISPC_0_VID1_ACCUV_1,The register configures the resize accumulator init values for horizontal and vertical up/down-sampling of the video window. DISPC_VIDx_ACCU__0 & DISPC_VIDx_ACCU__1 for ping-pong mechanism with external trigger. based on the field.." hexmask.long.tbyte 0x14 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x18 "DISPC_0_VID1_ACCUV2_0,The register configures the resize accumulator init value for vertical up/down-sampling of the video window. ACCU2__0 & ACCU2__1 for ping-pong mechanism with external trigger. based on the field polarity. It is used for U/V.." hexmask.long.tbyte 0x18 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x1C "DISPC_0_VID1_ACCUV2_1,The register configures the resize accumulator init value for vertical up/down-sampling of the video window. ACCU2__0 & ACCU2__1 for ping-pong mechanism with external trigger. based on the field polarity. It is used for U/V.." hexmask.long.tbyte 0x1C 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x20 "DISPC_0_VID1_ATTRIBUTES,The register configures the attributes of the video window. Shadow register" bitfld.long 0x20 31. "LUMAKEYENABLE,Enable Luma Key transparency matching" "0,1" bitfld.long 0x20 30. "GAMMAINVERSION,Inverse Gamma support [using the CLUT table]" "0,1" newline bitfld.long 0x20 29. "GAMMAINVERSIONPOS,Position of Inverse Gamma operation" "0,1" bitfld.long 0x20 28. "PREMULTIPLYALPHA,The field configures the DISPC VID to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data" "0,1" newline bitfld.long 0x20 24. "SELFREFRESH,Enables the self refresh of the video window from its own DMA buffer only" "0,1" bitfld.long 0x20 23. "ARBITRATION,Determines the priority of the video pipeline. The video pipeline is one of the high priority pipelines. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there are only normal.." "0,1" newline bitfld.long 0x20 21. "VERTICALTAPS,Video Vertical Resize Tap Number. The vertical poly-phase filter can be configured in 3-tap or 5-tap configuration. According to the number of taps the maximum input picture width is double while using 3-tap compared to 5-tap" "0,1" bitfld.long 0x20 19. "BUFPRELOAD,Video Preload Value" "0,1" newline rbitfld.long 0x20 18. "RESERVED7,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x20 17. "SELFREFRESHAUTO,Automatic self refresh mode" "0,1" newline bitfld.long 0x20 13. "CROP,Enables cropping operation at the output of Video Pipeline" "0,1" bitfld.long 0x20 12. "FLIP,Describes the frame buffer flip operation" "0,1" newline bitfld.long 0x20 11. "FULLRANGE,Color Space Conversion full range setting" "0,1" bitfld.long 0x20 10. "NIBBLEMODE,Video Nibble mode [only for 1- 2- and 4-bpp]" "0,1" newline bitfld.long 0x20 9. "COLORCONVENABLE,Enable the color space conversion. The HW does not enable/disable the conversion based on the pixel format" "0,1" bitfld.long 0x20 7.--8. "RESIZEENABLE,Video Resize Enable" "0,1,2,3" newline hexmask.long.byte 0x20 1.--6. 1. "FORMAT,Video Format. It defines the pixel format when fetching the video frame buffer" bitfld.long 0x20 0. "ENABLE,Video pipeline Enable" "0,1" line.long 0x24 "DISPC_0_VID1_ATTRIBUTES2,The register configures the attributes of the video window. Shadow register" hexmask.long.byte 0x24 26.--30. 1. "TAGS,Number of OCP TAGS to be used for the pipeline [from 0x0 to 0xF]. A value of 0x0 means only a single tag will be used. A value of 0xF means all 16 tags can be used" bitfld.long 0x24 25. "MPORTSEL,Master-Port Selection. By default use primary master port only" "0,1" newline bitfld.long 0x24 10. "YUV_ALIGN,Alignment [MSB or LSB align] for unpacked 10b/12b YUV data" "0,1" bitfld.long 0x24 9. "YUV_MODE,Mode of packing for YUV data [only for 10b/12b formats]" "0,1" newline bitfld.long 0x24 7.--8. "YUV_SIZE,Size of YUV data 8b/10b/12b" "0,1,2,3" bitfld.long 0x24 4.--6. "VC1_RANGE_CBCR,Defines the VC1 range value for the CbCr component from 0 to 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 1.--3. "VC1_RANGE_Y,Defines the VC1 range value for the Y component from 0 to 7" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "VC1ENABLE,Enable/disable the VC1 range mapping processing. The bit-field is ignored if the format is not one of the supported YUV formats" "0,1" line.long 0x28 "DISPC_0_VID1_BA_0,The register configures the base address of the single video buffer. In case of single plane ARGB or YUV. this is the BA. In case of two plane YUV. this is the BA_Y. In case of two plane RGB565-A8. this is the BA_Alpha. BA__0 & BA__1.." hexmask.long 0x28 0.--31. 1. "BA,Video base address. Base address of the video buffer [Aligned on pixel size boundary except for the following. In case of RGB24 packed format 4-pixel alignment is required. In case of YUV422 2-pixel alignment is required. In case of YUV420 byte.." line.long 0x2C "DISPC_0_VID1_BA_1,The register configures the base address of the single video buffer. In case of single plane ARGB or YUV. this is the BA. In case of two plane YUV. this is the BA_Y. In case of two plane RGB565-A8. this is the BA_Alpha. BA__0 & BA__1.." hexmask.long 0x2C 0.--31. 1. "BA,Video base address. Base address of the video buffer [Aligned on pixel size boundary except for the following. In case of RGB24 packed format 4-pixel alignment is required. In case of YUV422 2-pixel alignment is required. In case of YUV420 byte.." line.long 0x30 "DISPC_0_VID1_BA_UV_0,The register configures the base address of the UV buffer for two plane YUV or RGB buffer for two plane RGB565-A8. for the video window. BA_UV__0 & BA_UV__1 for ping-pong mechanism with external trigger. based on the field polarity.." hexmask.long 0x30 0.--31. 1. "BA,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV420-NV12" line.long 0x34 "DISPC_0_VID1_BA_UV_1,The register configures the base address of the UV buffer for two plane YUV or RGB buffer for two plane RGB565-A8. for the video window. BA_UV__0 & BA_UV__1 for ping-pong mechanism with external trigger. based on the field polarity.." hexmask.long 0x34 0.--31. 1. "BA,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV420-NV12" rgroup.long 0x38++0x3 line.long 0x0 "DISPC_0_VID1_BUF_SIZE_STATUS,The register returns the Video buffer size for the video pipeline" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x0 0.--15. 1. "BUFSIZE,Video DMA buffer Size in number of 128-bits" rgroup.long 0x3C++0x1C3 line.long 0x0 "DISPC_0_VID1_BUF_THRESHOLD,The register configures the video buffer associated with the video pipeline. Shadow register" hexmask.long.word 0x0 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer High Threshold. Number of 128-bits defining the threshold value" hexmask.long.word 0x0 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer Low Threshold. Number of 128-bits defining the threshold value" line.long 0x4 "DISPC_0_VID1_CSC_COEF0,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x4 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x4 16.--26. 1. "C01,C01 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x4 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x4 0.--10. 1. "C00,C00 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x8 "DISPC_0_VID1_CSC_COEF1,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x8 16.--26. 1. "C10,C10 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x8 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x8 0.--10. 1. "C02,C02 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0xC "DISPC_0_VID1_CSC_COEF2,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0xC 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0xC 16.--26. 1. "C12,C12 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0xC 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0xC 0.--10. 1. "C11,C11 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x10 "DISPC_0_VID1_CSC_COEF3,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x10 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 16.--26. 1. "C21,C21 coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x10 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 0.--10. 1. "C20,C20 coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x14 "DISPC_0_VID1_CSC_COEF4,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.tbyte 0x14 11.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x14 0.--10. 1. "C22,C22 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x18 "DISPC_0_VID1_CSC_COEF5,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x18 19.--31. 1. "PREOFFSET2,Row-2 pre-offset. Encoded signed value [from -4096 to 4095]" hexmask.long.word 0x18 3.--15. 1. "PREOFFSET1,Row1 pre-offset. Encoded signed value [from -4096 to 4095]" line.long 0x1C "DISPC_0_VID1_CSC_COEF6,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x1C 19.--31. 1. "POSTOFFSET1,Row-1 post-offset. Encoded signed value [from -4096 to 4095]" hexmask.long.word 0x1C 3.--15. 1. "PREOFFSET3,Row-3 pre-offset. Encoded signed value [from -4096 to 4095]" line.long 0x20 "DISPC_0_VID1_FIRH,The register configures the resize factor for horizontal up/down-sampling of the video window. It is used for ARGB and Y setting. Shadow register" hexmask.long.tbyte 0x20 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter. The value 0 is invalid" line.long 0x24 "DISPC_0_VID1_FIRH2,The register configures the resize factor for horizontal up/down-sampling of the video window. It is used for U/V components for YUV 422 and 420 input formats. It is not used if input format is any RGB format. Shadow register" hexmask.long.tbyte 0x24 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter for Cb and Cr. The value 0 is invalid" line.long 0x28 "DISPC_0_VID1_FIRV,The register configures the resize factor for vertical up/down-sampling of the video window. It is used for ARGB and Y setting. Shadow register" hexmask.long.tbyte 0x28 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter. The value 0 is invalid" line.long 0x2C "DISPC_0_VID1_FIRV2,The register configures the resize factor for vertical up/down-sampling of the video window. It is used for U/V components for YUV420 input format. It is not used when the input format is any RGB format or YUV422 format. Shadow.." hexmask.long.tbyte 0x2C 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter for Cb and Cr. The value 0 is invalid" line.long 0x30 "DISPC_0_VID1_FIR_COEF_H0_0,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x30 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 0" line.long 0x34 "DISPC_0_VID1_FIR_COEF_H0_1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x34 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 1" line.long 0x38 "DISPC_0_VID1_FIR_COEF_H0_2,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x38 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 2" line.long 0x3C "DISPC_0_VID1_FIR_COEF_H0_3,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x3C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 3" line.long 0x40 "DISPC_0_VID1_FIR_COEF_H0_4,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x40 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 4" line.long 0x44 "DISPC_0_VID1_FIR_COEF_H0_5,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x44 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 5" line.long 0x48 "DISPC_0_VID1_FIR_COEF_H0_6,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x48 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 6" line.long 0x4C "DISPC_0_VID1_FIR_COEF_H0_7,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x4C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 7" line.long 0x50 "DISPC_0_VID1_FIR_COEF_H0_8,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x50 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 8" line.long 0x54 "DISPC_0_VID1_FIR_COEF_H0_C_0,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x54 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 0" line.long 0x58 "DISPC_0_VID1_FIR_COEF_H0_C_1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x58 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 1" line.long 0x5C "DISPC_0_VID1_FIR_COEF_H0_C_2,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x5C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 2" line.long 0x60 "DISPC_0_VID1_FIR_COEF_H0_C_3,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x60 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 3" line.long 0x64 "DISPC_0_VID1_FIR_COEF_H0_C_4,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x64 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 4" line.long 0x68 "DISPC_0_VID1_FIR_COEF_H0_C_5,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x68 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 5" line.long 0x6C "DISPC_0_VID1_FIR_COEF_H0_C_6,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x6C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 6" line.long 0x70 "DISPC_0_VID1_FIR_COEF_H0_C_7,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x70 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 7" line.long 0x74 "DISPC_0_VID1_FIR_COEF_H0_C_8,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x74 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 8" line.long 0x78 "DISPC_0_VID1_FIR_COEF_H12_0,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x78 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 0" hexmask.long.word 0x78 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 0" line.long 0x7C "DISPC_0_VID1_FIR_COEF_H12_1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x7C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 1" hexmask.long.word 0x7C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 1" line.long 0x80 "DISPC_0_VID1_FIR_COEF_H12_2,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x80 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 2" hexmask.long.word 0x80 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 2" line.long 0x84 "DISPC_0_VID1_FIR_COEF_H12_3,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x84 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 3" hexmask.long.word 0x84 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 3" line.long 0x88 "DISPC_0_VID1_FIR_COEF_H12_4,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x88 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 4" hexmask.long.word 0x88 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 4" line.long 0x8C "DISPC_0_VID1_FIR_COEF_H12_5,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x8C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 5" hexmask.long.word 0x8C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 5" line.long 0x90 "DISPC_0_VID1_FIR_COEF_H12_6,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x90 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 6" hexmask.long.word 0x90 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 6" line.long 0x94 "DISPC_0_VID1_FIR_COEF_H12_7,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x94 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 7" hexmask.long.word 0x94 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 7" line.long 0x98 "DISPC_0_VID1_FIR_COEF_H12_8,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x98 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 8" hexmask.long.word 0x98 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 8" line.long 0x9C "DISPC_0_VID1_FIR_COEF_H12_9,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x9C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 9" hexmask.long.word 0x9C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 9" line.long 0xA0 "DISPC_0_VID1_FIR_COEF_H12_10,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xA0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 10" hexmask.long.word 0xA0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 10" line.long 0xA4 "DISPC_0_VID1_FIR_COEF_H12_11,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xA4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 11" hexmask.long.word 0xA4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 11" line.long 0xA8 "DISPC_0_VID1_FIR_COEF_H12_12,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xA8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 12" hexmask.long.word 0xA8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 12" line.long 0xAC "DISPC_0_VID1_FIR_COEF_H12_13,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xAC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 13" hexmask.long.word 0xAC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 13" line.long 0xB0 "DISPC_0_VID1_FIR_COEF_H12_14,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xB0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 14" hexmask.long.word 0xB0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 14" line.long 0xB4 "DISPC_0_VID1_FIR_COEF_H12_15,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xB4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 15" hexmask.long.word 0xB4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 15" line.long 0xB8 "DISPC_0_VID1_FIR_COEF_H12_C_0,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xB8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 0" hexmask.long.word 0xB8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 0" line.long 0xBC "DISPC_0_VID1_FIR_COEF_H12_C_1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xBC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 1" hexmask.long.word 0xBC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 1" line.long 0xC0 "DISPC_0_VID1_FIR_COEF_H12_C_2,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xC0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 2" hexmask.long.word 0xC0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 2" line.long 0xC4 "DISPC_0_VID1_FIR_COEF_H12_C_3,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xC4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 3" hexmask.long.word 0xC4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 3" line.long 0xC8 "DISPC_0_VID1_FIR_COEF_H12_C_4,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xC8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 4" hexmask.long.word 0xC8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 4" line.long 0xCC "DISPC_0_VID1_FIR_COEF_H12_C_5,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xCC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 5" hexmask.long.word 0xCC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 5" line.long 0xD0 "DISPC_0_VID1_FIR_COEF_H12_C_6,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xD0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 6" hexmask.long.word 0xD0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 6" line.long 0xD4 "DISPC_0_VID1_FIR_COEF_H12_C_7,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xD4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 7" hexmask.long.word 0xD4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 7" line.long 0xD8 "DISPC_0_VID1_FIR_COEF_H12_C_8,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xD8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 8" hexmask.long.word 0xD8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 8" line.long 0xDC "DISPC_0_VID1_FIR_COEF_H12_C_9,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xDC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 9" hexmask.long.word 0xDC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 9" line.long 0xE0 "DISPC_0_VID1_FIR_COEF_H12_C_10,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xE0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 10" hexmask.long.word 0xE0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 10" line.long 0xE4 "DISPC_0_VID1_FIR_COEF_H12_C_11,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xE4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 11" hexmask.long.word 0xE4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 11" line.long 0xE8 "DISPC_0_VID1_FIR_COEF_H12_C_12,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xE8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 12" hexmask.long.word 0xE8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 12" line.long 0xEC "DISPC_0_VID1_FIR_COEF_H12_C_13,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xEC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 13" hexmask.long.word 0xEC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 13" line.long 0xF0 "DISPC_0_VID1_FIR_COEF_H12_C_14,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xF0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 14" hexmask.long.word 0xF0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 14" line.long 0xF4 "DISPC_0_VID1_FIR_COEF_H12_C_15,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xF4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 15" hexmask.long.word 0xF4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 15" line.long 0xF8 "DISPC_0_VID1_FIR_COEF_V0_0,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xF8 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 0" line.long 0xFC "DISPC_0_VID1_FIR_COEF_V0_1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xFC 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 1" line.long 0x100 "DISPC_0_VID1_FIR_COEF_V0_2,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x100 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 2" line.long 0x104 "DISPC_0_VID1_FIR_COEF_V0_3,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x104 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 3" line.long 0x108 "DISPC_0_VID1_FIR_COEF_V0_4,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x108 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 4" line.long 0x10C "DISPC_0_VID1_FIR_COEF_V0_5,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x10C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 5" line.long 0x110 "DISPC_0_VID1_FIR_COEF_V0_6,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x110 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 6" line.long 0x114 "DISPC_0_VID1_FIR_COEF_V0_7,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x114 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 7" line.long 0x118 "DISPC_0_VID1_FIR_COEF_V0_8,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x118 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 8" line.long 0x11C "DISPC_0_VID1_FIR_COEF_V0_C_0,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x11C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 0" line.long 0x120 "DISPC_0_VID1_FIR_COEF_V0_C_1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x120 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 1" line.long 0x124 "DISPC_0_VID1_FIR_COEF_V0_C_2,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x124 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 2" line.long 0x128 "DISPC_0_VID1_FIR_COEF_V0_C_3,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x128 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 3" line.long 0x12C "DISPC_0_VID1_FIR_COEF_V0_C_4,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x12C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 4" line.long 0x130 "DISPC_0_VID1_FIR_COEF_V0_C_5,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x130 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 5" line.long 0x134 "DISPC_0_VID1_FIR_COEF_V0_C_6,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x134 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 6" line.long 0x138 "DISPC_0_VID1_FIR_COEF_V0_C_7,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x138 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 7" line.long 0x13C "DISPC_0_VID1_FIR_COEF_V0_C_8,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x13C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 8" line.long 0x140 "DISPC_0_VID1_FIR_COEF_V12_0,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x140 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 0" hexmask.long.word 0x140 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 0" line.long 0x144 "DISPC_0_VID1_FIR_COEF_V12_1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x144 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 1" hexmask.long.word 0x144 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 1" line.long 0x148 "DISPC_0_VID1_FIR_COEF_V12_2,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x148 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 2" hexmask.long.word 0x148 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 2" line.long 0x14C "DISPC_0_VID1_FIR_COEF_V12_3,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x14C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 3" hexmask.long.word 0x14C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 3" line.long 0x150 "DISPC_0_VID1_FIR_COEF_V12_4,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x150 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 4" hexmask.long.word 0x150 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 4" line.long 0x154 "DISPC_0_VID1_FIR_COEF_V12_5,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x154 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 5" hexmask.long.word 0x154 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 5" line.long 0x158 "DISPC_0_VID1_FIR_COEF_V12_6,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x158 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 6" hexmask.long.word 0x158 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 6" line.long 0x15C "DISPC_0_VID1_FIR_COEF_V12_7,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x15C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 7" hexmask.long.word 0x15C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 7" line.long 0x160 "DISPC_0_VID1_FIR_COEF_V12_8,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x160 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 8" hexmask.long.word 0x160 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 8" line.long 0x164 "DISPC_0_VID1_FIR_COEF_V12_9,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x164 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 9" hexmask.long.word 0x164 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 9" line.long 0x168 "DISPC_0_VID1_FIR_COEF_V12_10,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x168 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 10" hexmask.long.word 0x168 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 10" line.long 0x16C "DISPC_0_VID1_FIR_COEF_V12_11,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x16C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 11" hexmask.long.word 0x16C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 11" line.long 0x170 "DISPC_0_VID1_FIR_COEF_V12_12,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x170 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 12" hexmask.long.word 0x170 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 12" line.long 0x174 "DISPC_0_VID1_FIR_COEF_V12_13,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x174 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 13" hexmask.long.word 0x174 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 13" line.long 0x178 "DISPC_0_VID1_FIR_COEF_V12_14,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x178 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 14" hexmask.long.word 0x178 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 14" line.long 0x17C "DISPC_0_VID1_FIR_COEF_V12_15,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x17C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 15" hexmask.long.word 0x17C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 15" line.long 0x180 "DISPC_0_VID1_FIR_COEF_V12_C_0,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x180 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 0" hexmask.long.word 0x180 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 0" line.long 0x184 "DISPC_0_VID1_FIR_COEF_V12_C_1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x184 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 1" hexmask.long.word 0x184 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 1" line.long 0x188 "DISPC_0_VID1_FIR_COEF_V12_C_2,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x188 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 2" hexmask.long.word 0x188 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 2" line.long 0x18C "DISPC_0_VID1_FIR_COEF_V12_C_3,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x18C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 3" hexmask.long.word 0x18C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 3" line.long 0x190 "DISPC_0_VID1_FIR_COEF_V12_C_4,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x190 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 4" hexmask.long.word 0x190 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 4" line.long 0x194 "DISPC_0_VID1_FIR_COEF_V12_C_5,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x194 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 5" hexmask.long.word 0x194 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 5" line.long 0x198 "DISPC_0_VID1_FIR_COEF_V12_C_6,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x198 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 6" hexmask.long.word 0x198 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 6" line.long 0x19C "DISPC_0_VID1_FIR_COEF_V12_C_7,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x19C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 7" hexmask.long.word 0x19C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 7" line.long 0x1A0 "DISPC_0_VID1_FIR_COEF_V12_C_8,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x1A0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 8" hexmask.long.word 0x1A0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 8" line.long 0x1A4 "DISPC_0_VID1_FIR_COEF_V12_C_9,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x1A4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 9" hexmask.long.word 0x1A4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 9" line.long 0x1A8 "DISPC_0_VID1_FIR_COEF_V12_C_10,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x1A8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 10" hexmask.long.word 0x1A8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 10" line.long 0x1AC "DISPC_0_VID1_FIR_COEF_V12_C_11,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x1AC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 11" hexmask.long.word 0x1AC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 11" line.long 0x1B0 "DISPC_0_VID1_FIR_COEF_V12_C_12,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x1B0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 12" hexmask.long.word 0x1B0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 12" line.long 0x1B4 "DISPC_0_VID1_FIR_COEF_V12_C_13,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x1B4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 13" hexmask.long.word 0x1B4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 13" line.long 0x1B8 "DISPC_0_VID1_FIR_COEF_V12_C_14,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x1B8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 14" hexmask.long.word 0x1B8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 14" line.long 0x1BC "DISPC_0_VID1_FIR_COEF_V12_C_15,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x1BC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 15" hexmask.long.word 0x1BC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 15" line.long 0x1C0 "DISPC_0_VID1_GLOBAL_ALPHA,The register defines the global alpha value for the video pipeline. Shadow register" hexmask.long.byte 0x1C0 0.--7. 1. "GLOBALALPHA,Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 corresponds to fully opaque" rgroup.long 0x208++0xB line.long 0x0 "DISPC_0_VID1_MFLAG_THRESHOLD,MFLAG_THRESHOLD Register" hexmask.long.word 0x0 16.--31. 1. "HT_MFLAG,MFlag High Threshold" hexmask.long.word 0x0 0.--15. 1. "LT_MFLAG,MFlag Low Threshold" line.long 0x4 "DISPC_0_VID1_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer before up/down-scaling. Shadow register" hexmask.long.word 0x4 16.--29. 1. "MEMSIZEY,Number of lines of the video picture Encoded value [from 1 to 16384] to specify the number of lines of the video picture in memory [program to value minus one] When predecimation is set the value represents the size of the image after.." hexmask.long.word 0x4 0.--13. 1. "MEMSIZEX,Number of pixels of the video picture Encoded value [from 1 to 16384] to specify the number of pixels of the video picture in memory [program to value minus one]. The size is limited to the size of the line buffer of the vertical sampling block.." line.long 0x8 "DISPC_0_VID1_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window. Shadow register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.byte 0x8 0.--7. 1. "PIXELINC,Number of bytes to increment between two pixels Encoded unsigned value [from 1 to 255] to specify the number of bytes between two pixels in the video buffer. The value 0 is invalid The value 1 means next pixel The value 1+n*bpp means increment.." rgroup.long 0x218++0xB line.long 0x0 "DISPC_0_VID1_PRELOAD,The register configures the DMA buffer of the video pipeline. Shadow register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x0 0.--11. 1. "PRELOAD,DMA buffer preload value Number of 128-bit words defining the preload value" line.long 0x4 "DISPC_0_VID1_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window. For YUV420 formats this corresponds to the Y Buffer. Shadow register" hexmask.long 0x4 0.--31. 1. "ROWINC,Number of bytes to increment at the end of the row Encoded signed value [from -2^31-1 to 2^31] to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value.." line.long 0x8 "DISPC_0_VID1_SIZE,The register configures the size of the video window. Shadow register" hexmask.long.word 0x8 16.--29. 1. "SIZEY,Number of lines of the video window Encoded value [from 1 to 16384] to specify the number of lines of the video window [program size -1]" hexmask.long.word 0x8 0.--13. 1. "SIZEX,Number of pixels of the video window Encoded value [from 1 to 16384] to specify the number of pixels of the video window [program size -1]" rgroup.long 0x22C++0x13 line.long 0x0 "DISPC_0_VID1_BA_EXT_0,The register configures the 16-bit base address extension. It is the base-address of the single video buffer for single plane ARGB or YUV. For the Y buffer for two plane YUV. For the Alpha buffer for two plane RGB565-A8. 0 & 1 : For.." hexmask.long.word 0x0 0.--15. 1. "BA_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0x4 "DISPC_0_VID1_BA_EXT_1,The register configures the 16-bit base address extension. It is the base-address of the single video buffer for single plane ARGB or YUV. For the Y buffer for two plane YUV. For the Alpha buffer for two plane RGB565-A8. 0 & 1 : For.." hexmask.long.word 0x4 0.--15. 1. "BA_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0x8 "DISPC_0_VID1_BA_UV_EXT_0,The register configures the 16-bit base address extension of the UV buffer for two plane YUV or the RGB buffer for two plane RGB565-A8. 0 & 1 : For ping-pong mechanism with external trigger. based on the field polarity. Shadow.." hexmask.long.word 0x8 0.--15. 1. "BA_UV_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0xC "DISPC_0_VID1_BA_UV_EXT_1,The register configures the 16-bit base address extension of the UV buffer for two plane YUV or the RGB buffer for two plane RGB565-A8. 0 & 1 : For ping-pong mechanism with external trigger. based on the field polarity. Shadow.." hexmask.long.word 0xC 0.--15. 1. "BA_UV_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0x10 "DISPC_0_VID1_CSC_COEF7,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x10 19.--31. 1. "POSTOFFSET3,Row-3 post-offset. Encoded signed value [from -4096 to 4095]" hexmask.long.word 0x10 3.--15. 1. "POSTOFFSET2,Row-2 post-offset. Encoded signed value [from -4096 to 4095]" rgroup.long 0x248++0x13 line.long 0x0 "DISPC_0_VID1_ROW_INC_UV,The register configures the number of bytes to increment at the end of the row for the UV buffer associated with the video window for YUV420 formats. For non-YUV420 formats this register is unused. Shadow register" hexmask.long 0x0 0.--31. 1. "ROWINC,Number of bytes to increment at the end of the row Encoded signed value [from -2^31-1 to 2^31] to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid The value 1 means next pixel. The value.." line.long 0x4 "DISPC_0_VID1_TILE,Defines the characteristics of the position of the first pixel inside the compressed frame buffer. In case of non-compressed frame buffer. the register is not used." hexmask.long.tbyte 0x4 0.--22. 1. "TILEINDEX,Defines the tile number for the first tile of the frame buffer: -0 means that the first tile is accessed otherwise some tiles are skipped to support cropping of the frame buffer" line.long 0x8 "DISPC_0_VID1_TILE2,Defines the number of tiles in the frame buffer. In case of non-compressed frame buffer. the register is not used." hexmask.long.tbyte 0x8 0.--22. 1. "NUM_TILES,Defines the total number of tiles in the compressed frame buffer" line.long 0xC "DISPC_0_VID1_FBDC_ATTRIBUTES,Defines the attributes for the compression engine -FBDC" bitfld.long 0xC 8.--9. "TILETYPE,FBDC tile-type" "0,1,2,3" hexmask.long.byte 0xC 1.--7. 1. "FORMAT,FBDC format" newline bitfld.long 0xC 0. "ENABLE,Frame Buffer Compression is Enabled. Transactions shall use secondary master port" "0,1" line.long 0x10 "DISPC_0_VID1_FBDC_CLEAR_COLOR,Defines the Clear Color value to be used for the channel in FBDC" hexmask.long 0x10 0.--31. 1. "CLEARCOLOR,Defines the Clear Color value to be used for the channel in FBDC" rgroup.long 0x260++0x3F line.long 0x0 "DISPC_0_VID1_CLUT_0,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x0 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x0 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x0 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x0 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x4 "DISPC_0_VID1_CLUT_1,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x4 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x4 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x4 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x4 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x8 "DISPC_0_VID1_CLUT_2,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x8 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x8 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x8 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x8 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0xC "DISPC_0_VID1_CLUT_3,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0xC 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0xC 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0xC 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0xC 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x10 "DISPC_0_VID1_CLUT_4,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x10 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x10 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x10 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x10 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x14 "DISPC_0_VID1_CLUT_5,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x14 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x14 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x14 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x14 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x18 "DISPC_0_VID1_CLUT_6,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x18 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x18 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x18 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x18 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x1C "DISPC_0_VID1_CLUT_7,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x1C 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x1C 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x1C 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x1C 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x20 "DISPC_0_VID1_CLUT_8,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x20 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x20 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x20 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x20 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x24 "DISPC_0_VID1_CLUT_9,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x24 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x24 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x24 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x24 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x28 "DISPC_0_VID1_CLUT_10,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x28 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x28 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x28 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x28 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x2C "DISPC_0_VID1_CLUT_11,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x2C 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x2C 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x2C 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x2C 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x30 "DISPC_0_VID1_CLUT_12,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x30 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x30 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x30 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x30 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x34 "DISPC_0_VID1_CLUT_13,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x34 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x34 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x34 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x34 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x38 "DISPC_0_VID1_CLUT_14,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x38 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x38 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x38 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x38 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x3C "DISPC_0_VID1_CLUT_15,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x3C 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x3C 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x3C 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x3C 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" rgroup.long 0x2A0++0x3 line.long 0x0 "DISPC_0_VID1_SAFETY_ATTRIBUTES,The register configures the safety sub-region. Shadow register" bitfld.long 0x0 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" hexmask.long.byte 0x0 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature. When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur. Note: The freeze frame counter is cleared on reset -OR- MISR.." newline bitfld.long 0x0 2. "SEEDSELECT,Initial seed selection control" "0,1" bitfld.long 0x0 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x0 0. "ENABLE,Safety check Enable for the region. Note: Transition from 0 to 1 clears the signature register" "0,1" rgroup.long 0x2A4++0x3 line.long 0x0 "DISPC_0_VID1_SAFETY_CAPT_SIGNATURE,The register captures the signature from the MISR of the safety sub-region. Shadow register" hexmask.long 0x0 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region. Shadow register" rgroup.long 0x2A8++0x23 line.long 0x0 "DISPC_0_VID1_SAFETY_POSITION,The register configures the position of the safety sub-region. Shadow register" hexmask.long.word 0x0 16.--29. 1. "POSY,Y position of the safety sub-region. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen. The first line on the top of the screen has the Y-position 0" hexmask.long.word 0x0 0.--13. 1. "POSX,X position of the safety sub-region. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x4 "DISPC_0_VID1_SAFETY_REF_SIGNATURE,The register configures the reference signature of the safety sub-region. Shadow register" hexmask.long 0x4 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region. Shadow register" line.long 0x8 "DISPC_0_VID1_SAFETY_SIZE,The register configures the size of the safety sub-region. Shadow register" hexmask.long.word 0x8 16.--29. 1. "SIZEY,Height of the safety sub-region. Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen. One line height region has value of 0" hexmask.long.word 0x8 0.--13. 1. "SIZEX,Width of the safety sub-region. Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen. One pixel wide region has value of 0" line.long 0xC "DISPC_0_VID1_SAFETY_LFSR_SEED,The register configures the seed [initial value] of the MISR. Otherwise. the MISR is initialized with 0xFFFF_FFFF. Shadow register" hexmask.long 0xC 0.--31. 1. "SEED,The register configures the seed [initial value] of the MISR. Otherwise the MISR is initialized with 0xFFFF_FFFF. Shadow register" line.long 0x10 "DISPC_0_VID1_LUMAKEY,The register configures the LUMA KEY transparency min and max values. Shadow register" hexmask.long.byte 0x10 28.--31. 1. "RESERVED1,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 16.--27. 1. "LUMAKEYMAX,12b luma_key_max value" newline hexmask.long.byte 0x10 12.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 0.--11. 1. "LUMAKEYMIN,12b luma_key_min value" line.long 0x14 "DISPC_0_VID1_DMA_BUFSIZE,The register configures the DMA buffer size allocated to the pipeline - New Shared memory feature" hexmask.long.byte 0x14 0.--4. 1. "BUFSIZE,DMA buffer size if VID pipe is enabled.If the value programmed is n then the allocated buffer size is 16KB*n. Default:64KB" line.long 0x18 "DISPC_0_VID1_CROP,Defines the attributes for the output cropping in Video Pipe" hexmask.long.byte 0x18 24.--28. 1. "CROPBOTTOM,Crop Bottom in Lines. Values from 0-31" hexmask.long.byte 0x18 16.--20. 1. "CROPTOP,Crop Top in Lines. Values from 0-31" newline hexmask.long.byte 0x18 8.--12. 1. "CROPRIGHT,Crop Right in Pixels. Values from 0-31" hexmask.long.byte 0x18 0.--4. 1. "CROPLEFT,Crop Left in Pixels. Values from 0-31" line.long 0x1C "DISPC_0_VID1_SECURE,Security bit settings for the sub-module" bitfld.long 0x1C 0. "SECURE,Secure bit" "0,1" line.long 0x20 "DISPC_0_VID1_PIPE_GO,PIPE GO bit settings" bitfld.long 0x20 0. "GOBIT,Go bit" "0,1" tree.end tree "DSS0_VID2 (DSS0_VID2)" base ad:0x4A60000 rgroup.long 0x0++0x37 line.long 0x0 "DISPC_0_VID2_ACCUH_0,The register configures the resize accumulator init values for horizontal up/down-sampling of the video window. DISPC_VIDx_ACCU__0 & DISPC_VIDx_ACCU__1 for ping-pong mechanism with external trigger. based on the field polarity. This.." hexmask.long.tbyte 0x0 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x4 "DISPC_0_VID2_ACCUH_1,The register configures the resize accumulator init values for horizontal up/down-sampling of the video window. DISPC_VIDx_ACCU__0 & DISPC_VIDx_ACCU__1 for ping-pong mechanism with external trigger. based on the field polarity. This.." hexmask.long.tbyte 0x4 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x8 "DISPC_0_VID2_ACCUH2_0,The register configures the resize accumulator init value for horizontal up/down-sampling of the video window. DISPC_VID n_ACCU2__0 & DISPC_VID n_ACCU2__1 for ping-pong mechanism with external trigger. based on the field polarity." hexmask.long.tbyte 0x8 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0xC "DISPC_0_VID2_ACCUH2_1,The register configures the resize accumulator init value for horizontal up/down-sampling of the video window. DISPC_VID n_ACCU2__0 & DISPC_VID n_ACCU2__1 for ping-pong mechanism with external trigger. based on the field polarity." hexmask.long.tbyte 0xC 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x10 "DISPC_0_VID2_ACCUV_0,The register configures the resize accumulator init values for horizontal and vertical up/down-sampling of the video window. DISPC_VIDx_ACCU__0 & DISPC_VIDx_ACCU__1 for ping-pong mechanism with external trigger. based on the field.." hexmask.long.tbyte 0x10 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x14 "DISPC_0_VID2_ACCUV_1,The register configures the resize accumulator init values for horizontal and vertical up/down-sampling of the video window. DISPC_VIDx_ACCU__0 & DISPC_VIDx_ACCU__1 for ping-pong mechanism with external trigger. based on the field.." hexmask.long.tbyte 0x14 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x18 "DISPC_0_VID2_ACCUV2_0,The register configures the resize accumulator init value for vertical up/down-sampling of the video window. ACCU2__0 & ACCU2__1 for ping-pong mechanism with external trigger. based on the field polarity. It is used for U/V.." hexmask.long.tbyte 0x18 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x1C "DISPC_0_VID2_ACCUV2_1,The register configures the resize accumulator init value for vertical up/down-sampling of the video window. ACCU2__0 & ACCU2__1 for ping-pong mechanism with external trigger. based on the field polarity. It is used for U/V.." hexmask.long.tbyte 0x1C 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x20 "DISPC_0_VID2_ATTRIBUTES,The register configures the attributes of the video window. Shadow register" bitfld.long 0x20 31. "LUMAKEYENABLE,Enable Luma Key transparency matching" "0,1" bitfld.long 0x20 30. "GAMMAINVERSION,Inverse Gamma support [using the CLUT table]" "0,1" newline bitfld.long 0x20 29. "GAMMAINVERSIONPOS,Position of Inverse Gamma operation" "0,1" bitfld.long 0x20 28. "PREMULTIPLYALPHA,The field configures the DISPC VID to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data" "0,1" newline bitfld.long 0x20 24. "SELFREFRESH,Enables the self refresh of the video window from its own DMA buffer only" "0,1" bitfld.long 0x20 23. "ARBITRATION,Determines the priority of the video pipeline. The video pipeline is one of the high priority pipelines. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there are only normal.." "0,1" newline bitfld.long 0x20 21. "VERTICALTAPS,Video Vertical Resize Tap Number. The vertical poly-phase filter can be configured in 3-tap or 5-tap configuration. According to the number of taps the maximum input picture width is double while using 3-tap compared to 5-tap" "0,1" bitfld.long 0x20 19. "BUFPRELOAD,Video Preload Value" "0,1" newline rbitfld.long 0x20 18. "RESERVED7,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x20 17. "SELFREFRESHAUTO,Automatic self refresh mode" "0,1" newline bitfld.long 0x20 13. "CROP,Enables cropping operation at the output of Video Pipeline" "0,1" bitfld.long 0x20 12. "FLIP,Describes the frame buffer flip operation" "0,1" newline bitfld.long 0x20 11. "FULLRANGE,Color Space Conversion full range setting" "0,1" bitfld.long 0x20 10. "NIBBLEMODE,Video Nibble mode [only for 1- 2- and 4-bpp]" "0,1" newline bitfld.long 0x20 9. "COLORCONVENABLE,Enable the color space conversion. The HW does not enable/disable the conversion based on the pixel format" "0,1" bitfld.long 0x20 7.--8. "RESIZEENABLE,Video Resize Enable" "0,1,2,3" newline hexmask.long.byte 0x20 1.--6. 1. "FORMAT,Video Format. It defines the pixel format when fetching the video frame buffer" bitfld.long 0x20 0. "ENABLE,Video pipeline Enable" "0,1" line.long 0x24 "DISPC_0_VID2_ATTRIBUTES2,The register configures the attributes of the video window. Shadow register" hexmask.long.byte 0x24 26.--30. 1. "TAGS,Number of OCP TAGS to be used for the pipeline [from 0x0 to 0xF]. A value of 0x0 means only a single tag will be used. A value of 0xF means all 16 tags can be used" bitfld.long 0x24 25. "MPORTSEL,Master-Port Selection. By default use primary master port only" "0,1" newline bitfld.long 0x24 10. "YUV_ALIGN,Alignment [MSB or LSB align] for unpacked 10b/12b YUV data" "0,1" bitfld.long 0x24 9. "YUV_MODE,Mode of packing for YUV data [only for 10b/12b formats]" "0,1" newline bitfld.long 0x24 7.--8. "YUV_SIZE,Size of YUV data 8b/10b/12b" "0,1,2,3" bitfld.long 0x24 4.--6. "VC1_RANGE_CBCR,Defines the VC1 range value for the CbCr component from 0 to 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 1.--3. "VC1_RANGE_Y,Defines the VC1 range value for the Y component from 0 to 7" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "VC1ENABLE,Enable/disable the VC1 range mapping processing. The bit-field is ignored if the format is not one of the supported YUV formats" "0,1" line.long 0x28 "DISPC_0_VID2_BA_0,The register configures the base address of the single video buffer. In case of single plane ARGB or YUV. this is the BA. In case of two plane YUV. this is the BA_Y. In case of two plane RGB565-A8. this is the BA_Alpha. BA__0 & BA__1.." hexmask.long 0x28 0.--31. 1. "BA,Video base address. Base address of the video buffer [Aligned on pixel size boundary except for the following. In case of RGB24 packed format 4-pixel alignment is required. In case of YUV422 2-pixel alignment is required. In case of YUV420 byte.." line.long 0x2C "DISPC_0_VID2_BA_1,The register configures the base address of the single video buffer. In case of single plane ARGB or YUV. this is the BA. In case of two plane YUV. this is the BA_Y. In case of two plane RGB565-A8. this is the BA_Alpha. BA__0 & BA__1.." hexmask.long 0x2C 0.--31. 1. "BA,Video base address. Base address of the video buffer [Aligned on pixel size boundary except for the following. In case of RGB24 packed format 4-pixel alignment is required. In case of YUV422 2-pixel alignment is required. In case of YUV420 byte.." line.long 0x30 "DISPC_0_VID2_BA_UV_0,The register configures the base address of the UV buffer for two plane YUV or RGB buffer for two plane RGB565-A8. for the video window. BA_UV__0 & BA_UV__1 for ping-pong mechanism with external trigger. based on the field polarity.." hexmask.long 0x30 0.--31. 1. "BA,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV420-NV12" line.long 0x34 "DISPC_0_VID2_BA_UV_1,The register configures the base address of the UV buffer for two plane YUV or RGB buffer for two plane RGB565-A8. for the video window. BA_UV__0 & BA_UV__1 for ping-pong mechanism with external trigger. based on the field polarity.." hexmask.long 0x34 0.--31. 1. "BA,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV420-NV12" rgroup.long 0x38++0x3 line.long 0x0 "DISPC_0_VID2_BUF_SIZE_STATUS,The register returns the Video buffer size for the video pipeline" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x0 0.--15. 1. "BUFSIZE,Video DMA buffer Size in number of 128-bits" rgroup.long 0x3C++0x1C3 line.long 0x0 "DISPC_0_VID2_BUF_THRESHOLD,The register configures the video buffer associated with the video pipeline. Shadow register" hexmask.long.word 0x0 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer High Threshold. Number of 128-bits defining the threshold value" hexmask.long.word 0x0 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer Low Threshold. Number of 128-bits defining the threshold value" line.long 0x4 "DISPC_0_VID2_CSC_COEF0,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x4 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x4 16.--26. 1. "C01,C01 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x4 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x4 0.--10. 1. "C00,C00 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x8 "DISPC_0_VID2_CSC_COEF1,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x8 16.--26. 1. "C10,C10 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x8 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x8 0.--10. 1. "C02,C02 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0xC "DISPC_0_VID2_CSC_COEF2,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0xC 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0xC 16.--26. 1. "C12,C12 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0xC 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0xC 0.--10. 1. "C11,C11 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x10 "DISPC_0_VID2_CSC_COEF3,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x10 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 16.--26. 1. "C21,C21 coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x10 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 0.--10. 1. "C20,C20 coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x14 "DISPC_0_VID2_CSC_COEF4,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.tbyte 0x14 11.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x14 0.--10. 1. "C22,C22 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x18 "DISPC_0_VID2_CSC_COEF5,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x18 19.--31. 1. "PREOFFSET2,Row-2 pre-offset. Encoded signed value [from -4096 to 4095]" hexmask.long.word 0x18 3.--15. 1. "PREOFFSET1,Row1 pre-offset. Encoded signed value [from -4096 to 4095]" line.long 0x1C "DISPC_0_VID2_CSC_COEF6,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x1C 19.--31. 1. "POSTOFFSET1,Row-1 post-offset. Encoded signed value [from -4096 to 4095]" hexmask.long.word 0x1C 3.--15. 1. "PREOFFSET3,Row-3 pre-offset. Encoded signed value [from -4096 to 4095]" line.long 0x20 "DISPC_0_VID2_FIRH,The register configures the resize factor for horizontal up/down-sampling of the video window. It is used for ARGB and Y setting. Shadow register" hexmask.long.tbyte 0x20 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter. The value 0 is invalid" line.long 0x24 "DISPC_0_VID2_FIRH2,The register configures the resize factor for horizontal up/down-sampling of the video window. It is used for U/V components for YUV 422 and 420 input formats. It is not used if input format is any RGB format. Shadow register" hexmask.long.tbyte 0x24 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter for Cb and Cr. The value 0 is invalid" line.long 0x28 "DISPC_0_VID2_FIRV,The register configures the resize factor for vertical up/down-sampling of the video window. It is used for ARGB and Y setting. Shadow register" hexmask.long.tbyte 0x28 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter. The value 0 is invalid" line.long 0x2C "DISPC_0_VID2_FIRV2,The register configures the resize factor for vertical up/down-sampling of the video window. It is used for U/V components for YUV420 input format. It is not used when the input format is any RGB format or YUV422 format. Shadow.." hexmask.long.tbyte 0x2C 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter for Cb and Cr. The value 0 is invalid" line.long 0x30 "DISPC_0_VID2_FIR_COEF_H0_0,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x30 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 0" line.long 0x34 "DISPC_0_VID2_FIR_COEF_H0_1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x34 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 1" line.long 0x38 "DISPC_0_VID2_FIR_COEF_H0_2,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x38 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 2" line.long 0x3C "DISPC_0_VID2_FIR_COEF_H0_3,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x3C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 3" line.long 0x40 "DISPC_0_VID2_FIR_COEF_H0_4,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x40 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 4" line.long 0x44 "DISPC_0_VID2_FIR_COEF_H0_5,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x44 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 5" line.long 0x48 "DISPC_0_VID2_FIR_COEF_H0_6,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x48 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 6" line.long 0x4C "DISPC_0_VID2_FIR_COEF_H0_7,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x4C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 7" line.long 0x50 "DISPC_0_VID2_FIR_COEF_H0_8,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x50 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 8" line.long 0x54 "DISPC_0_VID2_FIR_COEF_H0_C_0,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x54 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 0" line.long 0x58 "DISPC_0_VID2_FIR_COEF_H0_C_1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x58 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 1" line.long 0x5C "DISPC_0_VID2_FIR_COEF_H0_C_2,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x5C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 2" line.long 0x60 "DISPC_0_VID2_FIR_COEF_H0_C_3,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x60 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 3" line.long 0x64 "DISPC_0_VID2_FIR_COEF_H0_C_4,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x64 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 4" line.long 0x68 "DISPC_0_VID2_FIR_COEF_H0_C_5,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x68 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 5" line.long 0x6C "DISPC_0_VID2_FIR_COEF_H0_C_6,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x6C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 6" line.long 0x70 "DISPC_0_VID2_FIR_COEF_H0_C_7,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x70 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 7" line.long 0x74 "DISPC_0_VID2_FIR_COEF_H0_C_8,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x74 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 8" line.long 0x78 "DISPC_0_VID2_FIR_COEF_H12_0,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x78 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 0" hexmask.long.word 0x78 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 0" line.long 0x7C "DISPC_0_VID2_FIR_COEF_H12_1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x7C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 1" hexmask.long.word 0x7C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 1" line.long 0x80 "DISPC_0_VID2_FIR_COEF_H12_2,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x80 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 2" hexmask.long.word 0x80 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 2" line.long 0x84 "DISPC_0_VID2_FIR_COEF_H12_3,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x84 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 3" hexmask.long.word 0x84 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 3" line.long 0x88 "DISPC_0_VID2_FIR_COEF_H12_4,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x88 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 4" hexmask.long.word 0x88 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 4" line.long 0x8C "DISPC_0_VID2_FIR_COEF_H12_5,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x8C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 5" hexmask.long.word 0x8C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 5" line.long 0x90 "DISPC_0_VID2_FIR_COEF_H12_6,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x90 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 6" hexmask.long.word 0x90 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 6" line.long 0x94 "DISPC_0_VID2_FIR_COEF_H12_7,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x94 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 7" hexmask.long.word 0x94 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 7" line.long 0x98 "DISPC_0_VID2_FIR_COEF_H12_8,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x98 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 8" hexmask.long.word 0x98 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 8" line.long 0x9C "DISPC_0_VID2_FIR_COEF_H12_9,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x9C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 9" hexmask.long.word 0x9C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 9" line.long 0xA0 "DISPC_0_VID2_FIR_COEF_H12_10,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xA0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 10" hexmask.long.word 0xA0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 10" line.long 0xA4 "DISPC_0_VID2_FIR_COEF_H12_11,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xA4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 11" hexmask.long.word 0xA4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 11" line.long 0xA8 "DISPC_0_VID2_FIR_COEF_H12_12,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xA8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 12" hexmask.long.word 0xA8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 12" line.long 0xAC "DISPC_0_VID2_FIR_COEF_H12_13,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xAC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 13" hexmask.long.word 0xAC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 13" line.long 0xB0 "DISPC_0_VID2_FIR_COEF_H12_14,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xB0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 14" hexmask.long.word 0xB0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 14" line.long 0xB4 "DISPC_0_VID2_FIR_COEF_H12_15,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xB4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 15" hexmask.long.word 0xB4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 15" line.long 0xB8 "DISPC_0_VID2_FIR_COEF_H12_C_0,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xB8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 0" hexmask.long.word 0xB8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 0" line.long 0xBC "DISPC_0_VID2_FIR_COEF_H12_C_1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xBC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 1" hexmask.long.word 0xBC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 1" line.long 0xC0 "DISPC_0_VID2_FIR_COEF_H12_C_2,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xC0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 2" hexmask.long.word 0xC0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 2" line.long 0xC4 "DISPC_0_VID2_FIR_COEF_H12_C_3,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xC4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 3" hexmask.long.word 0xC4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 3" line.long 0xC8 "DISPC_0_VID2_FIR_COEF_H12_C_4,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xC8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 4" hexmask.long.word 0xC8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 4" line.long 0xCC "DISPC_0_VID2_FIR_COEF_H12_C_5,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xCC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 5" hexmask.long.word 0xCC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 5" line.long 0xD0 "DISPC_0_VID2_FIR_COEF_H12_C_6,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xD0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 6" hexmask.long.word 0xD0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 6" line.long 0xD4 "DISPC_0_VID2_FIR_COEF_H12_C_7,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xD4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 7" hexmask.long.word 0xD4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 7" line.long 0xD8 "DISPC_0_VID2_FIR_COEF_H12_C_8,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xD8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 8" hexmask.long.word 0xD8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 8" line.long 0xDC "DISPC_0_VID2_FIR_COEF_H12_C_9,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xDC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 9" hexmask.long.word 0xDC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 9" line.long 0xE0 "DISPC_0_VID2_FIR_COEF_H12_C_10,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xE0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 10" hexmask.long.word 0xE0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 10" line.long 0xE4 "DISPC_0_VID2_FIR_COEF_H12_C_11,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xE4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 11" hexmask.long.word 0xE4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 11" line.long 0xE8 "DISPC_0_VID2_FIR_COEF_H12_C_12,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xE8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 12" hexmask.long.word 0xE8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 12" line.long 0xEC "DISPC_0_VID2_FIR_COEF_H12_C_13,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xEC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 13" hexmask.long.word 0xEC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 13" line.long 0xF0 "DISPC_0_VID2_FIR_COEF_H12_C_14,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xF0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 14" hexmask.long.word 0xF0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 14" line.long 0xF4 "DISPC_0_VID2_FIR_COEF_H12_C_15,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used.." hexmask.long.word 0xF4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 15" hexmask.long.word 0xF4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 15" line.long 0xF8 "DISPC_0_VID2_FIR_COEF_V0_0,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xF8 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 0" line.long 0xFC "DISPC_0_VID2_FIR_COEF_V0_1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xFC 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 1" line.long 0x100 "DISPC_0_VID2_FIR_COEF_V0_2,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x100 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 2" line.long 0x104 "DISPC_0_VID2_FIR_COEF_V0_3,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x104 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 3" line.long 0x108 "DISPC_0_VID2_FIR_COEF_V0_4,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x108 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 4" line.long 0x10C "DISPC_0_VID2_FIR_COEF_V0_5,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x10C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 5" line.long 0x110 "DISPC_0_VID2_FIR_COEF_V0_6,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x110 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 6" line.long 0x114 "DISPC_0_VID2_FIR_COEF_V0_7,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x114 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 7" line.long 0x118 "DISPC_0_VID2_FIR_COEF_V0_8,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x118 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 8" line.long 0x11C "DISPC_0_VID2_FIR_COEF_V0_C_0,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x11C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 0" line.long 0x120 "DISPC_0_VID2_FIR_COEF_V0_C_1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x120 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 1" line.long 0x124 "DISPC_0_VID2_FIR_COEF_V0_C_2,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x124 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 2" line.long 0x128 "DISPC_0_VID2_FIR_COEF_V0_C_3,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x128 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 3" line.long 0x12C "DISPC_0_VID2_FIR_COEF_V0_C_4,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x12C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 4" line.long 0x130 "DISPC_0_VID2_FIR_COEF_V0_C_5,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x130 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 5" line.long 0x134 "DISPC_0_VID2_FIR_COEF_V0_C_6,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x134 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 6" line.long 0x138 "DISPC_0_VID2_FIR_COEF_V0_C_7,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x138 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 7" line.long 0x13C "DISPC_0_VID2_FIR_COEF_V0_C_8,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x13C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 8" line.long 0x140 "DISPC_0_VID2_FIR_COEF_V12_0,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x140 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 0" hexmask.long.word 0x140 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 0" line.long 0x144 "DISPC_0_VID2_FIR_COEF_V12_1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x144 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 1" hexmask.long.word 0x144 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 1" line.long 0x148 "DISPC_0_VID2_FIR_COEF_V12_2,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x148 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 2" hexmask.long.word 0x148 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 2" line.long 0x14C "DISPC_0_VID2_FIR_COEF_V12_3,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x14C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 3" hexmask.long.word 0x14C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 3" line.long 0x150 "DISPC_0_VID2_FIR_COEF_V12_4,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x150 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 4" hexmask.long.word 0x150 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 4" line.long 0x154 "DISPC_0_VID2_FIR_COEF_V12_5,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x154 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 5" hexmask.long.word 0x154 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 5" line.long 0x158 "DISPC_0_VID2_FIR_COEF_V12_6,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x158 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 6" hexmask.long.word 0x158 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 6" line.long 0x15C "DISPC_0_VID2_FIR_COEF_V12_7,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x15C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 7" hexmask.long.word 0x15C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 7" line.long 0x160 "DISPC_0_VID2_FIR_COEF_V12_8,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x160 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 8" hexmask.long.word 0x160 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 8" line.long 0x164 "DISPC_0_VID2_FIR_COEF_V12_9,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x164 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 9" hexmask.long.word 0x164 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 9" line.long 0x168 "DISPC_0_VID2_FIR_COEF_V12_10,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x168 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 10" hexmask.long.word 0x168 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 10" line.long 0x16C "DISPC_0_VID2_FIR_COEF_V12_11,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x16C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 11" hexmask.long.word 0x16C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 11" line.long 0x170 "DISPC_0_VID2_FIR_COEF_V12_12,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x170 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 12" hexmask.long.word 0x170 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 12" line.long 0x174 "DISPC_0_VID2_FIR_COEF_V12_13,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x174 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 13" hexmask.long.word 0x174 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 13" line.long 0x178 "DISPC_0_VID2_FIR_COEF_V12_14,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x178 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 14" hexmask.long.word 0x178 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 14" line.long 0x17C "DISPC_0_VID2_FIR_COEF_V12_15,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x17C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 15" hexmask.long.word 0x17C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 15" line.long 0x180 "DISPC_0_VID2_FIR_COEF_V12_C_0,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x180 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 0" hexmask.long.word 0x180 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 0" line.long 0x184 "DISPC_0_VID2_FIR_COEF_V12_C_1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x184 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 1" hexmask.long.word 0x184 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 1" line.long 0x188 "DISPC_0_VID2_FIR_COEF_V12_C_2,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x188 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 2" hexmask.long.word 0x188 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 2" line.long 0x18C "DISPC_0_VID2_FIR_COEF_V12_C_3,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x18C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 3" hexmask.long.word 0x18C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 3" line.long 0x190 "DISPC_0_VID2_FIR_COEF_V12_C_4,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x190 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 4" hexmask.long.word 0x190 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 4" line.long 0x194 "DISPC_0_VID2_FIR_COEF_V12_C_5,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x194 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 5" hexmask.long.word 0x194 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 5" line.long 0x198 "DISPC_0_VID2_FIR_COEF_V12_C_6,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x198 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 6" hexmask.long.word 0x198 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 6" line.long 0x19C "DISPC_0_VID2_FIR_COEF_V12_C_7,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x19C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 7" hexmask.long.word 0x19C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 7" line.long 0x1A0 "DISPC_0_VID2_FIR_COEF_V12_C_8,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x1A0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 8" hexmask.long.word 0x1A0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 8" line.long 0x1A4 "DISPC_0_VID2_FIR_COEF_V12_C_9,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x1A4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 9" hexmask.long.word 0x1A4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 9" line.long 0x1A8 "DISPC_0_VID2_FIR_COEF_V12_C_10,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x1A8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 10" hexmask.long.word 0x1A8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 10" line.long 0x1AC "DISPC_0_VID2_FIR_COEF_V12_C_11,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x1AC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 11" hexmask.long.word 0x1AC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 11" line.long 0x1B0 "DISPC_0_VID2_FIR_COEF_V12_C_12,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x1B0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 12" hexmask.long.word 0x1B0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 12" line.long 0x1B4 "DISPC_0_VID2_FIR_COEF_V12_C_13,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x1B4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 13" hexmask.long.word 0x1B4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 13" line.long 0x1B8 "DISPC_0_VID2_FIR_COEF_V12_C_14,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x1B8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 14" hexmask.long.word 0x1B8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 14" line.long 0x1BC "DISPC_0_VID2_FIR_COEF_V12_C_15,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only.." hexmask.long.word 0x1BC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 15" hexmask.long.word 0x1BC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 15" line.long 0x1C0 "DISPC_0_VID2_GLOBAL_ALPHA,The register defines the global alpha value for the video pipeline. Shadow register" hexmask.long.byte 0x1C0 0.--7. 1. "GLOBALALPHA,Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 corresponds to fully opaque" rgroup.long 0x208++0xB line.long 0x0 "DISPC_0_VID2_MFLAG_THRESHOLD,MFLAG_THRESHOLD Register" hexmask.long.word 0x0 16.--31. 1. "HT_MFLAG,MFlag High Threshold" hexmask.long.word 0x0 0.--15. 1. "LT_MFLAG,MFlag Low Threshold" line.long 0x4 "DISPC_0_VID2_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer before up/down-scaling. Shadow register" hexmask.long.word 0x4 16.--29. 1. "MEMSIZEY,Number of lines of the video picture Encoded value [from 1 to 16384] to specify the number of lines of the video picture in memory [program to value minus one] When predecimation is set the value represents the size of the image after.." hexmask.long.word 0x4 0.--13. 1. "MEMSIZEX,Number of pixels of the video picture Encoded value [from 1 to 16384] to specify the number of pixels of the video picture in memory [program to value minus one]. The size is limited to the size of the line buffer of the vertical sampling block.." line.long 0x8 "DISPC_0_VID2_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window. Shadow register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.byte 0x8 0.--7. 1. "PIXELINC,Number of bytes to increment between two pixels Encoded unsigned value [from 1 to 255] to specify the number of bytes between two pixels in the video buffer. The value 0 is invalid The value 1 means next pixel The value 1+n*bpp means increment.." rgroup.long 0x218++0xB line.long 0x0 "DISPC_0_VID2_PRELOAD,The register configures the DMA buffer of the video pipeline. Shadow register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x0 0.--11. 1. "PRELOAD,DMA buffer preload value Number of 128-bit words defining the preload value" line.long 0x4 "DISPC_0_VID2_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window. For YUV420 formats this corresponds to the Y Buffer. Shadow register" hexmask.long 0x4 0.--31. 1. "ROWINC,Number of bytes to increment at the end of the row Encoded signed value [from -2^31-1 to 2^31] to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value.." line.long 0x8 "DISPC_0_VID2_SIZE,The register configures the size of the video window. Shadow register" hexmask.long.word 0x8 16.--29. 1. "SIZEY,Number of lines of the video window Encoded value [from 1 to 16384] to specify the number of lines of the video window [program size -1]" hexmask.long.word 0x8 0.--13. 1. "SIZEX,Number of pixels of the video window Encoded value [from 1 to 16384] to specify the number of pixels of the video window [program size -1]" rgroup.long 0x22C++0x13 line.long 0x0 "DISPC_0_VID2_BA_EXT_0,The register configures the 16-bit base address extension. It is the base-address of the single video buffer for single plane ARGB or YUV. For the Y buffer for two plane YUV. For the Alpha buffer for two plane RGB565-A8. 0 & 1 : For.." hexmask.long.word 0x0 0.--15. 1. "BA_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0x4 "DISPC_0_VID2_BA_EXT_1,The register configures the 16-bit base address extension. It is the base-address of the single video buffer for single plane ARGB or YUV. For the Y buffer for two plane YUV. For the Alpha buffer for two plane RGB565-A8. 0 & 1 : For.." hexmask.long.word 0x4 0.--15. 1. "BA_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0x8 "DISPC_0_VID2_BA_UV_EXT_0,The register configures the 16-bit base address extension of the UV buffer for two plane YUV or the RGB buffer for two plane RGB565-A8. 0 & 1 : For ping-pong mechanism with external trigger. based on the field polarity. Shadow.." hexmask.long.word 0x8 0.--15. 1. "BA_UV_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0xC "DISPC_0_VID2_BA_UV_EXT_1,The register configures the 16-bit base address extension of the UV buffer for two plane YUV or the RGB buffer for two plane RGB565-A8. 0 & 1 : For ping-pong mechanism with external trigger. based on the field polarity. Shadow.." hexmask.long.word 0xC 0.--15. 1. "BA_UV_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0x10 "DISPC_0_VID2_CSC_COEF7,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x10 19.--31. 1. "POSTOFFSET3,Row-3 post-offset. Encoded signed value [from -4096 to 4095]" hexmask.long.word 0x10 3.--15. 1. "POSTOFFSET2,Row-2 post-offset. Encoded signed value [from -4096 to 4095]" rgroup.long 0x248++0x13 line.long 0x0 "DISPC_0_VID2_ROW_INC_UV,The register configures the number of bytes to increment at the end of the row for the UV buffer associated with the video window for YUV420 formats. For non-YUV420 formats this register is unused. Shadow register" hexmask.long 0x0 0.--31. 1. "ROWINC,Number of bytes to increment at the end of the row Encoded signed value [from -2^31-1 to 2^31] to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid The value 1 means next pixel. The value.." line.long 0x4 "DISPC_0_VID2_TILE,Defines the characteristics of the position of the first pixel inside the compressed frame buffer. In case of non-compressed frame buffer. the register is not used." hexmask.long.tbyte 0x4 0.--22. 1. "TILEINDEX,Defines the tile number for the first tile of the frame buffer: -0 means that the first tile is accessed otherwise some tiles are skipped to support cropping of the frame buffer" line.long 0x8 "DISPC_0_VID2_TILE2,Defines the number of tiles in the frame buffer. In case of non-compressed frame buffer. the register is not used." hexmask.long.tbyte 0x8 0.--22. 1. "NUM_TILES,Defines the total number of tiles in the compressed frame buffer" line.long 0xC "DISPC_0_VID2_FBDC_ATTRIBUTES,Defines the attributes for the compression engine -FBDC" bitfld.long 0xC 8.--9. "TILETYPE,FBDC tile-type" "0,1,2,3" hexmask.long.byte 0xC 1.--7. 1. "FORMAT,FBDC format" newline bitfld.long 0xC 0. "ENABLE,Frame Buffer Compression is Enabled. Transactions shall use secondary master port" "0,1" line.long 0x10 "DISPC_0_VID2_FBDC_CLEAR_COLOR,Defines the Clear Color value to be used for the channel in FBDC" hexmask.long 0x10 0.--31. 1. "CLEARCOLOR,Defines the Clear Color value to be used for the channel in FBDC" rgroup.long 0x260++0x3F line.long 0x0 "DISPC_0_VID2_CLUT_0,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x0 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x0 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x0 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x0 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x4 "DISPC_0_VID2_CLUT_1,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x4 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x4 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x4 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x4 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x8 "DISPC_0_VID2_CLUT_2,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x8 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x8 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x8 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x8 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0xC "DISPC_0_VID2_CLUT_3,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0xC 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0xC 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0xC 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0xC 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x10 "DISPC_0_VID2_CLUT_4,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x10 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x10 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x10 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x10 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x14 "DISPC_0_VID2_CLUT_5,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x14 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x14 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x14 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x14 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x18 "DISPC_0_VID2_CLUT_6,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x18 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x18 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x18 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x18 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x1C "DISPC_0_VID2_CLUT_7,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x1C 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x1C 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x1C 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x1C 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x20 "DISPC_0_VID2_CLUT_8,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x20 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x20 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x20 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x20 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x24 "DISPC_0_VID2_CLUT_9,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x24 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x24 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x24 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x24 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x28 "DISPC_0_VID2_CLUT_10,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x28 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x28 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x28 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x28 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x2C "DISPC_0_VID2_CLUT_11,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x2C 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x2C 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x2C 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x2C 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x30 "DISPC_0_VID2_CLUT_12,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x30 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x30 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x30 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x30 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x34 "DISPC_0_VID2_CLUT_13,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x34 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x34 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x34 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x34 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x38 "DISPC_0_VID2_CLUT_14,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x38 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x38 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x38 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x38 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x3C "DISPC_0_VID2_CLUT_15,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x3C 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x3C 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x3C 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x3C 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" rgroup.long 0x2A0++0x3 line.long 0x0 "DISPC_0_VID2_SAFETY_ATTRIBUTES,The register configures the safety sub-region. Shadow register" bitfld.long 0x0 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" hexmask.long.byte 0x0 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature. When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur. Note: The freeze frame counter is cleared on reset -OR- MISR.." newline bitfld.long 0x0 2. "SEEDSELECT,Initial seed selection control" "0,1" bitfld.long 0x0 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x0 0. "ENABLE,Safety check Enable for the region. Note: Transition from 0 to 1 clears the signature register" "0,1" rgroup.long 0x2A4++0x3 line.long 0x0 "DISPC_0_VID2_SAFETY_CAPT_SIGNATURE,The register captures the signature from the MISR of the safety sub-region. Shadow register" hexmask.long 0x0 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region. Shadow register" rgroup.long 0x2A8++0x23 line.long 0x0 "DISPC_0_VID2_SAFETY_POSITION,The register configures the position of the safety sub-region. Shadow register" hexmask.long.word 0x0 16.--29. 1. "POSY,Y position of the safety sub-region. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen. The first line on the top of the screen has the Y-position 0" hexmask.long.word 0x0 0.--13. 1. "POSX,X position of the safety sub-region. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x4 "DISPC_0_VID2_SAFETY_REF_SIGNATURE,The register configures the reference signature of the safety sub-region. Shadow register" hexmask.long 0x4 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region. Shadow register" line.long 0x8 "DISPC_0_VID2_SAFETY_SIZE,The register configures the size of the safety sub-region. Shadow register" hexmask.long.word 0x8 16.--29. 1. "SIZEY,Height of the safety sub-region. Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen. One line height region has value of 0" hexmask.long.word 0x8 0.--13. 1. "SIZEX,Width of the safety sub-region. Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen. One pixel wide region has value of 0" line.long 0xC "DISPC_0_VID2_SAFETY_LFSR_SEED,The register configures the seed [initial value] of the MISR. Otherwise. the MISR is initialized with 0xFFFF_FFFF. Shadow register" hexmask.long 0xC 0.--31. 1. "SEED,The register configures the seed [initial value] of the MISR. Otherwise the MISR is initialized with 0xFFFF_FFFF. Shadow register" line.long 0x10 "DISPC_0_VID2_LUMAKEY,The register configures the LUMA KEY transparency min and max values. Shadow register" hexmask.long.byte 0x10 28.--31. 1. "RESERVED1,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 16.--27. 1. "LUMAKEYMAX,12b luma_key_max value" newline hexmask.long.byte 0x10 12.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 0.--11. 1. "LUMAKEYMIN,12b luma_key_min value" line.long 0x14 "DISPC_0_VID2_DMA_BUFSIZE,The register configures the DMA buffer size allocated to the pipeline - New Shared memory feature" hexmask.long.byte 0x14 0.--4. 1. "BUFSIZE,DMA buffer size if VID pipe is enabled.If the value programmed is n then the allocated buffer size is 16KB*n. Default:64KB" line.long 0x18 "DISPC_0_VID2_CROP,Defines the attributes for the output cropping in Video Pipe" hexmask.long.byte 0x18 24.--28. 1. "CROPBOTTOM,Crop Bottom in Lines. Values from 0-31" hexmask.long.byte 0x18 16.--20. 1. "CROPTOP,Crop Top in Lines. Values from 0-31" newline hexmask.long.byte 0x18 8.--12. 1. "CROPRIGHT,Crop Right in Pixels. Values from 0-31" hexmask.long.byte 0x18 0.--4. 1. "CROPLEFT,Crop Left in Pixels. Values from 0-31" line.long 0x1C "DISPC_0_VID2_SECURE,Security bit settings for the sub-module" bitfld.long 0x1C 0. "SECURE,Secure bit" "0,1" line.long 0x20 "DISPC_0_VID2_PIPE_GO,PIPE GO bit settings" bitfld.long 0x20 0. "GOBIT,Go bit" "0,1" tree.end tree "DSS0_VIDL1 (DSS0_VIDL1)" base ad:0x4A20000 rgroup.long 0x20++0x17 line.long 0x0 "DISPC_0_VIDL1_ATTRIBUTES,The register configures the attributes of the video window. Shadow register" bitfld.long 0x0 31. "LUMAKEYENABLE,Enable Luma Key transparency matching" "0,1" bitfld.long 0x0 30. "GAMMAINVERSION,Inverse Gamma support [using the CLUT table]" "0,1" newline bitfld.long 0x0 29. "GAMMAINVERSIONPOS,Position of Inverse Gamma operation" "0,1" bitfld.long 0x0 28. "PREMULTIPLYALPHA,The field configures the DISPC VID to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data" "0,1" newline bitfld.long 0x0 24. "SELFREFRESH,Enables the self refresh of the video window from its own DMA buffer only" "0,1" bitfld.long 0x0 23. "ARBITRATION,Determines the priority of the video pipeline. The video pipeline is one of the high priority pipelines. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there are only normal.." "0,1" newline rbitfld.long 0x0 21. "RESERVED3,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 19. "BUFPRELOAD,Video Preload Value" "0,1" newline rbitfld.long 0x0 18. "RESERVED7,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 17. "SELFREFRESHAUTO,Automatic self refresh mode" "0,1" newline bitfld.long 0x0 13. "CROP,Enables cropping operation at the output of Video Pipeline" "0,1" bitfld.long 0x0 12. "FLIP,Describes the frame buffer flip operation" "0,1" newline bitfld.long 0x0 11. "FULLRANGE,Color Space Conversion full range setting" "0,1" bitfld.long 0x0 10. "NIBBLEMODE,Video Nibble mode [only for 1- 2- and 4-bpp]" "0,1" newline bitfld.long 0x0 9. "COLORCONVENABLE,Enable the color space conversion. The HW does not enable/disable the conversion based on the pixel format" "0,1" rbitfld.long 0x0 7.--8. "RESERVED8,Write 0's for future compatibility. Reads return 0" "0,1,2,3" newline hexmask.long.byte 0x0 1.--6. 1. "FORMAT,Video Format. It defines the pixel format when fetching the video frame buffer" bitfld.long 0x0 0. "ENABLE,Video pipeline Enable" "0,1" line.long 0x4 "DISPC_0_VIDL1_ATTRIBUTES2,The register configures the attributes of the video window. Shadow register" hexmask.long.byte 0x4 26.--30. 1. "TAGS,Number of OCP TAGS to be used for the pipeline [from 0x0 to 0xF]. A value of 0x0 means only a single tag will be used. A value of 0xF means all 16 tags can be used" bitfld.long 0x4 25. "MPORTSEL,Master-Port Selection. By default use primary master port only" "0,1" newline bitfld.long 0x4 10. "YUV_ALIGN,Alignment [MSB or LSB align] for unpacked 10b/12b YUV data" "0,1" bitfld.long 0x4 9. "YUV_MODE,Mode of packing for YUV data [only for 10b/12b formats]" "0,1" newline bitfld.long 0x4 7.--8. "YUV_SIZE,Size of YUV data 8b/10b/12b" "0,1,2,3" bitfld.long 0x4 4.--6. "VC1_RANGE_CBCR,Defines the VC1 range value for the CbCr component from 0 to 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 1.--3. "VC1_RANGE_Y,Defines the VC1 range value for the Y component from 0 to 7" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "VC1ENABLE,Enable/disable the VC1 range mapping processing. The bit-field is ignored if the format is not one of the supported YUV formats" "0,1" line.long 0x8 "DISPC_0_VIDL1_BA_0,The register configures the base address of the single video buffer. In case of single plane ARGB or YUV. this is the BA. In case of two plane YUV. this is the BA_Y. In case of two plane RGB565-A8. this is the BA_Alpha. BA__0 & BA__1.." hexmask.long 0x8 0.--31. 1. "BA,Video base address. Base address of the video buffer [Aligned on pixel size boundary except for the following. In case of RGB24 packed format 4-pixel alignment is required. In case of YUV422 2-pixel alignment is required. In case of YUV420 byte.." line.long 0xC "DISPC_0_VIDL1_BA_1,The register configures the base address of the single video buffer. In case of single plane ARGB or YUV. this is the BA. In case of two plane YUV. this is the BA_Y. In case of two plane RGB565-A8. this is the BA_Alpha. BA__0 & BA__1.." hexmask.long 0xC 0.--31. 1. "BA,Video base address. Base address of the video buffer [Aligned on pixel size boundary except for the following. In case of RGB24 packed format 4-pixel alignment is required. In case of YUV422 2-pixel alignment is required. In case of YUV420 byte.." line.long 0x10 "DISPC_0_VIDL1_BA_UV_0,The register configures the base address of the UV buffer for two plane YUV or RGB buffer for two plane RGB565-A8. for the video window. BA_UV__0 & BA_UV__1 for ping-pong mechanism with external trigger. based on the field polarity.." hexmask.long 0x10 0.--31. 1. "BA,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV420-NV12" line.long 0x14 "DISPC_0_VIDL1_BA_UV_1,The register configures the base address of the UV buffer for two plane YUV or RGB buffer for two plane RGB565-A8. for the video window. BA_UV__0 & BA_UV__1 for ping-pong mechanism with external trigger. based on the field polarity.." hexmask.long 0x14 0.--31. 1. "BA,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV420-NV12" rgroup.long 0x38++0x3 line.long 0x0 "DISPC_0_VIDL1_BUF_SIZE_STATUS,The register returns the Video buffer size for the video pipeline" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x0 0.--15. 1. "BUFSIZE,Video DMA buffer Size in number of 128-bits" rgroup.long 0x3C++0x1F line.long 0x0 "DISPC_0_VIDL1_BUF_THRESHOLD,The register configures the video buffer associated with the video pipeline. Shadow register" hexmask.long.word 0x0 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer High Threshold. Number of 128-bits defining the threshold value" hexmask.long.word 0x0 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer Low Threshold. Number of 128-bits defining the threshold value" line.long 0x4 "DISPC_0_VIDL1_CSC_COEF0,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x4 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x4 16.--26. 1. "C01,C01 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x4 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x4 0.--10. 1. "C00,C00 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x8 "DISPC_0_VIDL1_CSC_COEF1,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x8 16.--26. 1. "C10,C10 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x8 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x8 0.--10. 1. "C02,C02 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0xC "DISPC_0_VIDL1_CSC_COEF2,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0xC 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0xC 16.--26. 1. "C12,C12 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0xC 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0xC 0.--10. 1. "C11,C11 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x10 "DISPC_0_VIDL1_CSC_COEF3,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x10 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 16.--26. 1. "C21,C21 coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x10 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 0.--10. 1. "C20,C20 coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x14 "DISPC_0_VIDL1_CSC_COEF4,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.tbyte 0x14 11.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x14 0.--10. 1. "C22,C22 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x18 "DISPC_0_VIDL1_CSC_COEF5,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x18 19.--31. 1. "PREOFFSET2,Row-2 pre-offset. Encoded signed value [from -4096 to 4095]" hexmask.long.word 0x18 3.--15. 1. "PREOFFSET1,Row1 pre-offset. Encoded signed value [from -4096 to 4095]" line.long 0x1C "DISPC_0_VIDL1_CSC_COEF6,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x1C 19.--31. 1. "POSTOFFSET1,Row-1 post-offset. Encoded signed value [from -4096 to 4095]" hexmask.long.word 0x1C 3.--15. 1. "PREOFFSET3,Row-3 pre-offset. Encoded signed value [from -4096 to 4095]" rgroup.long 0x1FC++0x3 line.long 0x0 "DISPC_0_VIDL1_GLOBAL_ALPHA,The register defines the global alpha value for the video pipeline. Shadow register" hexmask.long.byte 0x0 0.--7. 1. "GLOBALALPHA,Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 corresponds to fully opaque" rgroup.long 0x208++0xB line.long 0x0 "DISPC_0_VIDL1_MFLAG_THRESHOLD,MFLAG_THRESHOLD Register" hexmask.long.word 0x0 16.--31. 1. "HT_MFLAG,MFLAG High Threshold" hexmask.long.word 0x0 0.--15. 1. "LT_MFLAG,MFLAG Low Threshold" line.long 0x4 "DISPC_0_VIDL1_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer before up/down-scaling. Shadow register" hexmask.long.word 0x4 16.--29. 1. "MEMSIZEY,Number of lines of the video picture Encoded value [from 1 to 16384] to specify the number of lines of the video picture in memory [program to value minus one] When predecimation is set the value represents the size of the image after.." hexmask.long.word 0x4 0.--13. 1. "MEMSIZEX,Number of pixels of the video picture Encoded value [from 1 to 16384] to specify the number of pixels of the video picture in memory [program to value minus one]. The size is limited to the size of the line buffer of the vertical sampling block.." line.long 0x8 "DISPC_0_VIDL1_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window. Shadow register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.byte 0x8 0.--7. 1. "PIXELINC,Number of bytes to increment between two pixels Encoded unsigned value [from 1 to 255] to specify the number of bytes between two pixels in the video buffer. The value 0 is invalid The value 1 means next pixel The value 1+n*bpp means increment.." rgroup.long 0x218++0x7 line.long 0x0 "DISPC_0_VIDL1_PRELOAD,The register configures the DMA buffer of the video pipeline. Shadow register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x0 0.--11. 1. "PRELOAD,DMA buffer preload value. Number of 128-bit words defining the preload value" line.long 0x4 "DISPC_0_VIDL1_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window. For YUV420 formats this corresponds to the Y Buffer. Shadow register" hexmask.long 0x4 0.--31. 1. "ROWINC,Number of bytes to increment at the end of the row Encoded signed value [from -2^31-1 to 2^31] to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value.." rgroup.long 0x22C++0x13 line.long 0x0 "DISPC_0_VIDL1_BA_EXT_0,The register configures the 16-bit base address extension. It is the base-address of the single video buffer for single plane ARGB or YUV. For the Y buffer for two plane YUV. For the Alpha buffer for two plane RGB565-A8. 0 & 1 :.." hexmask.long.word 0x0 0.--15. 1. "BA_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0x4 "DISPC_0_VIDL1_BA_EXT_1,The register configures the 16-bit base address extension. It is the base-address of the single video buffer for single plane ARGB or YUV. For the Y buffer for two plane YUV. For the Alpha buffer for two plane RGB565-A8. 0 & 1 :.." hexmask.long.word 0x4 0.--15. 1. "BA_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0x8 "DISPC_0_VIDL1_BA_UV_EXT_0,The register configures the 16-bit base address extension of the UV buffer for two plane YUV or the RGB buffer for two plane RGB565-A8. 0 & 1 : For ping-pong mechanism with external trigger. based on the field polarity. Shadow.." hexmask.long.word 0x8 0.--15. 1. "BA_UV_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0xC "DISPC_0_VIDL1_BA_UV_EXT_1,The register configures the 16-bit base address extension of the UV buffer for two plane YUV or the RGB buffer for two plane RGB565-A8. 0 & 1 : For ping-pong mechanism with external trigger. based on the field polarity. Shadow.." hexmask.long.word 0xC 0.--15. 1. "BA_UV_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0x10 "DISPC_0_VIDL1_CSC_COEF7,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x10 19.--31. 1. "POSTOFFSET3,Row-3 post-offset. Encoded signed value [from -4096 to 4095]" hexmask.long.word 0x10 3.--15. 1. "POSTOFFSET2,Row-2 post-offset. Encoded signed value [from -4096 to 4095]" rgroup.long 0x248++0x13 line.long 0x0 "DISPC_0_VIDL1_ROW_INC_UV,The register configures the number of bytes to increment at the end of the row for the UV buffer associated with the video window for YUV420 formats. For non-YUV420 formats this register is unused. Shadow register" hexmask.long 0x0 0.--31. 1. "ROWINC,Number of bytes to increment at the end of the row Encoded signed value [from -2^31-1 to 2^31] to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid The value 1 means next pixel. The value.." line.long 0x4 "DISPC_0_VIDL1_TILE,Defines the characteristics of the position of the first pixel inside the compressed frame buffer. In case of non-compressed frame buffer. the register is not used." hexmask.long.tbyte 0x4 0.--22. 1. "TILEINDEX,Defines the tile number for the first tile of the frame buffer: -0 means that the first tile is accessed otherwise some tiles are skipped to support cropping of the frame buffer" line.long 0x8 "DISPC_0_VIDL1_TILE2,Defines the number of tiles in the frame buffer. In case of non-compressed frame buffer. the register is not used." hexmask.long.tbyte 0x8 0.--22. 1. "NUM_TILES,Defines the total number of tiles in the compressed frame buffer" line.long 0xC "DISPC_0_VIDL1_FBDC_ATTRIBUTES,Defines the attributes for the compression engine -FBDC" bitfld.long 0xC 8.--9. "TILETYPE,FBDC tile-type" "0,1,2,3" hexmask.long.byte 0xC 1.--7. 1. "FORMAT,FBDC format" newline bitfld.long 0xC 0. "ENABLE,Frame Buffer Compression is Enabled. Transactions shall use secondary master port" "0,1" line.long 0x10 "DISPC_0_VIDL1_FBDC_CLEAR_COLOR,Defines the Clear Color value to be used for the channel in FBDC" hexmask.long 0x10 0.--31. 1. "CLEARCOLOR,Defines the Clear Color value to be used for the channel in FBDC" rgroup.long 0x260++0x3F line.long 0x0 "DISPC_0_VIDL1_CLUT_0,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x0 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x0 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x0 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x0 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x4 "DISPC_0_VIDL1_CLUT_1,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x4 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x4 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x4 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x4 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x8 "DISPC_0_VIDL1_CLUT_2,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x8 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x8 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x8 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x8 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0xC "DISPC_0_VIDL1_CLUT_3,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0xC 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0xC 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0xC 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0xC 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x10 "DISPC_0_VIDL1_CLUT_4,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x10 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x10 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x10 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x10 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x14 "DISPC_0_VIDL1_CLUT_5,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x14 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x14 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x14 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x14 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x18 "DISPC_0_VIDL1_CLUT_6,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x18 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x18 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x18 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x18 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x1C "DISPC_0_VIDL1_CLUT_7,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x1C 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x1C 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x1C 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x1C 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x20 "DISPC_0_VIDL1_CLUT_8,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x20 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x20 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x20 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x20 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x24 "DISPC_0_VIDL1_CLUT_9,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x24 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x24 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x24 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x24 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x28 "DISPC_0_VIDL1_CLUT_10,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x28 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x28 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x28 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x28 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x2C "DISPC_0_VIDL1_CLUT_11,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x2C 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x2C 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x2C 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x2C 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x30 "DISPC_0_VIDL1_CLUT_12,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x30 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x30 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x30 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x30 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x34 "DISPC_0_VIDL1_CLUT_13,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x34 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x34 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x34 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x34 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x38 "DISPC_0_VIDL1_CLUT_14,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x38 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x38 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x38 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x38 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x3C "DISPC_0_VIDL1_CLUT_15,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x3C 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x3C 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x3C 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x3C 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" rgroup.long 0x2A0++0x3 line.long 0x0 "DISPC_0_VIDL1_SAFETY_ATTRIBUTES,The register configures the safety sub-region. Shadow register" bitfld.long 0x0 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" hexmask.long.byte 0x0 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature. When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur. Note: The freeze frame counter is cleared on reset -OR- MISR.." newline bitfld.long 0x0 2. "SEEDSELECT,Initial seed selection control" "0,1" bitfld.long 0x0 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x0 0. "ENABLE,Safety check Enable for the region. Note: Transition from 0 to 1 clears the signature register" "0,1" rgroup.long 0x2A4++0x3 line.long 0x0 "DISPC_0_VIDL1_SAFETY_CAPT_SIGNATURE,The register captures the signature from the MISR of the safety sub-region. Shadow register" hexmask.long 0x0 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region. Shadow register" rgroup.long 0x2A8++0x23 line.long 0x0 "DISPC_0_VIDL1_SAFETY_POSITION,The register configures the position of the safety sub-region. Shadow register" hexmask.long.word 0x0 16.--29. 1. "POSY,Y position of the safety sub-region. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen. The first line on the top of the screen has the Y-position 0" hexmask.long.word 0x0 0.--13. 1. "POSX,X position of the safety sub-region. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x4 "DISPC_0_VIDL1_SAFETY_REF_SIGNATURE,The register configures the reference signature of the safety sub-region. Shadow register" hexmask.long 0x4 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region. Shadow register" line.long 0x8 "DISPC_0_VIDL1_SAFETY_SIZE,The register configures the size of the safety sub-region. Shadow register" hexmask.long.word 0x8 16.--29. 1. "SIZEY,Height of the safety sub-region. Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen. One line height region has value of 0" hexmask.long.word 0x8 0.--13. 1. "SIZEX,Width of the safety sub-region. Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen. One pixel wide region has value of 0" line.long 0xC "DISPC_0_VIDL1_SAFETY_LFSR_SEED,The register configures the seed [initial value] of the MISR. Otherwise. the MISR is initialized with 0xFFFF_FFFF. Shadow register" hexmask.long 0xC 0.--31. 1. "SEED,The register configures the seed [initial value] of the MISR. Otherwise the MISR is initialized with 0xFFFF_FFFF. Shadow register" line.long 0x10 "DISPC_0_VIDL1_LUMAKEY,The register configures the LUMA KEY transparency min and max values. Shadow register" hexmask.long.byte 0x10 28.--31. 1. "RESERVED1,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 16.--27. 1. "LUMAKEYMAX,12b luma_key_max value" newline hexmask.long.byte 0x10 12.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 0.--11. 1. "LUMAKEYMIN,12b luma_key_min value" line.long 0x14 "DISPC_0_VIDL1_DMA_BUFSIZE,The register configures the DMA buffer size allocated to the pipeline - New Shared memory feature" hexmask.long.byte 0x14 0.--4. 1. "BUFSIZE,DMA buffer size if VID pipe is enabled.If the value programmed is n then the allocated buffer size is 16KB*n. Default:64KB" line.long 0x18 "DISPC_0_VIDL1_CROP,Defines the attributes for the output cropping in Video Pipe" hexmask.long.byte 0x18 24.--28. 1. "CROPBOTTOM,Crop Bottom in Lines. Values from 0-31" hexmask.long.byte 0x18 16.--20. 1. "CROPTOP,Crop Top in Lines. Values from 0-31" newline hexmask.long.byte 0x18 8.--12. 1. "CROPRIGHT,Crop Right in Pixels. Values from 0-31" hexmask.long.byte 0x18 0.--4. 1. "CROPLEFT,Crop Left in Pixels. Values from 0-31" line.long 0x1C "DISPC_0_VIDL1_SECURE,Security bit settings for the sub-module" bitfld.long 0x1C 0. "SECURE,Secure bit" "0,1" line.long 0x20 "DISPC_0_VIDL1_PIPE_GO,PIPE GO bit settings" bitfld.long 0x20 0. "GOBIT,Go bit" "0,1" tree.end tree "DSS0_VIDL2 (DSS0_VIDL2)" base ad:0x4A30000 rgroup.long 0x20++0x17 line.long 0x0 "DISPC_0_VIDL2_ATTRIBUTES,The register configures the attributes of the video window. Shadow register" bitfld.long 0x0 31. "LUMAKEYENABLE,Enable Luma Key transparency matching" "0,1" bitfld.long 0x0 30. "GAMMAINVERSION,Inverse Gamma support [using the CLUT table]" "0,1" newline bitfld.long 0x0 29. "GAMMAINVERSIONPOS,Position of Inverse Gamma operation" "0,1" bitfld.long 0x0 28. "PREMULTIPLYALPHA,The field configures the DISPC VID to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data" "0,1" newline bitfld.long 0x0 24. "SELFREFRESH,Enables the self refresh of the video window from its own DMA buffer only" "0,1" bitfld.long 0x0 23. "ARBITRATION,Determines the priority of the video pipeline. The video pipeline is one of the high priority pipelines. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there are only normal.." "0,1" newline rbitfld.long 0x0 21. "RESERVED3,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 19. "BUFPRELOAD,Video Preload Value" "0,1" newline rbitfld.long 0x0 18. "RESERVED7,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 17. "SELFREFRESHAUTO,Automatic self refresh mode" "0,1" newline bitfld.long 0x0 13. "CROP,Enables cropping operation at the output of Video Pipeline" "0,1" bitfld.long 0x0 12. "FLIP,Describes the frame buffer flip operation" "0,1" newline bitfld.long 0x0 11. "FULLRANGE,Color Space Conversion full range setting" "0,1" bitfld.long 0x0 10. "NIBBLEMODE,Video Nibble mode [only for 1- 2- and 4-bpp]" "0,1" newline bitfld.long 0x0 9. "COLORCONVENABLE,Enable the color space conversion. The HW does not enable/disable the conversion based on the pixel format" "0,1" rbitfld.long 0x0 7.--8. "RESERVED8,Write 0's for future compatibility. Reads return 0" "0,1,2,3" newline hexmask.long.byte 0x0 1.--6. 1. "FORMAT,Video Format. It defines the pixel format when fetching the video frame buffer" bitfld.long 0x0 0. "ENABLE,Video pipeline Enable" "0,1" line.long 0x4 "DISPC_0_VIDL2_ATTRIBUTES2,The register configures the attributes of the video window. Shadow register" hexmask.long.byte 0x4 26.--30. 1. "TAGS,Number of OCP TAGS to be used for the pipeline [from 0x0 to 0xF]. A value of 0x0 means only a single tag will be used. A value of 0xF means all 16 tags can be used" bitfld.long 0x4 25. "MPORTSEL,Master-Port Selection. By default use primary master port only" "0,1" newline bitfld.long 0x4 10. "YUV_ALIGN,Alignment [MSB or LSB align] for unpacked 10b/12b YUV data" "0,1" bitfld.long 0x4 9. "YUV_MODE,Mode of packing for YUV data [only for 10b/12b formats]" "0,1" newline bitfld.long 0x4 7.--8. "YUV_SIZE,Size of YUV data 8b/10b/12b" "0,1,2,3" bitfld.long 0x4 4.--6. "VC1_RANGE_CBCR,Defines the VC1 range value for the CbCr component from 0 to 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 1.--3. "VC1_RANGE_Y,Defines the VC1 range value for the Y component from 0 to 7" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "VC1ENABLE,Enable/disable the VC1 range mapping processing. The bit-field is ignored if the format is not one of the supported YUV formats" "0,1" line.long 0x8 "DISPC_0_VIDL2_BA_0,The register configures the base address of the single video buffer. In case of single plane ARGB or YUV. this is the BA. In case of two plane YUV. this is the BA_Y. In case of two plane RGB565-A8. this is the BA_Alpha. BA__0 & BA__1.." hexmask.long 0x8 0.--31. 1. "BA,Video base address. Base address of the video buffer [Aligned on pixel size boundary except for the following. In case of RGB24 packed format 4-pixel alignment is required. In case of YUV422 2-pixel alignment is required. In case of YUV420 byte.." line.long 0xC "DISPC_0_VIDL2_BA_1,The register configures the base address of the single video buffer. In case of single plane ARGB or YUV. this is the BA. In case of two plane YUV. this is the BA_Y. In case of two plane RGB565-A8. this is the BA_Alpha. BA__0 & BA__1.." hexmask.long 0xC 0.--31. 1. "BA,Video base address. Base address of the video buffer [Aligned on pixel size boundary except for the following. In case of RGB24 packed format 4-pixel alignment is required. In case of YUV422 2-pixel alignment is required. In case of YUV420 byte.." line.long 0x10 "DISPC_0_VIDL2_BA_UV_0,The register configures the base address of the UV buffer for two plane YUV or RGB buffer for two plane RGB565-A8. for the video window. BA_UV__0 & BA_UV__1 for ping-pong mechanism with external trigger. based on the field polarity.." hexmask.long 0x10 0.--31. 1. "BA,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV420-NV12" line.long 0x14 "DISPC_0_VIDL2_BA_UV_1,The register configures the base address of the UV buffer for two plane YUV or RGB buffer for two plane RGB565-A8. for the video window. BA_UV__0 & BA_UV__1 for ping-pong mechanism with external trigger. based on the field polarity.." hexmask.long 0x14 0.--31. 1. "BA,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV420-NV12" rgroup.long 0x38++0x3 line.long 0x0 "DISPC_0_VIDL2_BUF_SIZE_STATUS,The register returns the Video buffer size for the video pipeline" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x0 0.--15. 1. "BUFSIZE,Video DMA buffer Size in number of 128-bits" rgroup.long 0x3C++0x1F line.long 0x0 "DISPC_0_VIDL2_BUF_THRESHOLD,The register configures the video buffer associated with the video pipeline. Shadow register" hexmask.long.word 0x0 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer High Threshold. Number of 128-bits defining the threshold value" hexmask.long.word 0x0 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer Low Threshold. Number of 128-bits defining the threshold value" line.long 0x4 "DISPC_0_VIDL2_CSC_COEF0,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x4 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x4 16.--26. 1. "C01,C01 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x4 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x4 0.--10. 1. "C00,C00 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x8 "DISPC_0_VIDL2_CSC_COEF1,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x8 16.--26. 1. "C10,C10 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x8 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x8 0.--10. 1. "C02,C02 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0xC "DISPC_0_VIDL2_CSC_COEF2,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0xC 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0xC 16.--26. 1. "C12,C12 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0xC 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0xC 0.--10. 1. "C11,C11 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x10 "DISPC_0_VIDL2_CSC_COEF3,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x10 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 16.--26. 1. "C21,C21 coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x10 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 0.--10. 1. "C20,C20 coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x14 "DISPC_0_VIDL2_CSC_COEF4,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.tbyte 0x14 11.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x14 0.--10. 1. "C22,C22 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x18 "DISPC_0_VIDL2_CSC_COEF5,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x18 19.--31. 1. "PREOFFSET2,Row-2 pre-offset. Encoded signed value [from -4096 to 4095]" hexmask.long.word 0x18 3.--15. 1. "PREOFFSET1,Row1 pre-offset. Encoded signed value [from -4096 to 4095]" line.long 0x1C "DISPC_0_VIDL2_CSC_COEF6,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x1C 19.--31. 1. "POSTOFFSET1,Row-1 post-offset. Encoded signed value [from -4096 to 4095]" hexmask.long.word 0x1C 3.--15. 1. "PREOFFSET3,Row-3 pre-offset. Encoded signed value [from -4096 to 4095]" rgroup.long 0x1FC++0x3 line.long 0x0 "DISPC_0_VIDL2_GLOBAL_ALPHA,The register defines the global alpha value for the video pipeline. Shadow register" hexmask.long.byte 0x0 0.--7. 1. "GLOBALALPHA,Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 corresponds to fully opaque" rgroup.long 0x208++0xB line.long 0x0 "DISPC_0_VIDL2_MFLAG_THRESHOLD,MFLAG_THRESHOLD Register" hexmask.long.word 0x0 16.--31. 1. "HT_MFLAG,MFLAG High Threshold" hexmask.long.word 0x0 0.--15. 1. "LT_MFLAG,MFLAG Low Threshold" line.long 0x4 "DISPC_0_VIDL2_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer before up/down-scaling. Shadow register" hexmask.long.word 0x4 16.--29. 1. "MEMSIZEY,Number of lines of the video picture Encoded value [from 1 to 16384] to specify the number of lines of the video picture in memory [program to value minus one] When predecimation is set the value represents the size of the image after.." hexmask.long.word 0x4 0.--13. 1. "MEMSIZEX,Number of pixels of the video picture Encoded value [from 1 to 16384] to specify the number of pixels of the video picture in memory [program to value minus one]. The size is limited to the size of the line buffer of the vertical sampling block.." line.long 0x8 "DISPC_0_VIDL2_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window. Shadow register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.byte 0x8 0.--7. 1. "PIXELINC,Number of bytes to increment between two pixels Encoded unsigned value [from 1 to 255] to specify the number of bytes between two pixels in the video buffer. The value 0 is invalid The value 1 means next pixel The value 1+n*bpp means increment.." rgroup.long 0x218++0x7 line.long 0x0 "DISPC_0_VIDL2_PRELOAD,The register configures the DMA buffer of the video pipeline. Shadow register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x0 0.--11. 1. "PRELOAD,DMA buffer preload value. Number of 128-bit words defining the preload value" line.long 0x4 "DISPC_0_VIDL2_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window. For YUV420 formats this corresponds to the Y Buffer. Shadow register" hexmask.long 0x4 0.--31. 1. "ROWINC,Number of bytes to increment at the end of the row Encoded signed value [from -2^31-1 to 2^31] to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value.." rgroup.long 0x22C++0x13 line.long 0x0 "DISPC_0_VIDL2_BA_EXT_0,The register configures the 16-bit base address extension. It is the base-address of the single video buffer for single plane ARGB or YUV. For the Y buffer for two plane YUV. For the Alpha buffer for two plane RGB565-A8. 0 & 1 :.." hexmask.long.word 0x0 0.--15. 1. "BA_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0x4 "DISPC_0_VIDL2_BA_EXT_1,The register configures the 16-bit base address extension. It is the base-address of the single video buffer for single plane ARGB or YUV. For the Y buffer for two plane YUV. For the Alpha buffer for two plane RGB565-A8. 0 & 1 :.." hexmask.long.word 0x4 0.--15. 1. "BA_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0x8 "DISPC_0_VIDL2_BA_UV_EXT_0,The register configures the 16-bit base address extension of the UV buffer for two plane YUV or the RGB buffer for two plane RGB565-A8. 0 & 1 : For ping-pong mechanism with external trigger. based on the field polarity. Shadow.." hexmask.long.word 0x8 0.--15. 1. "BA_UV_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0xC "DISPC_0_VIDL2_BA_UV_EXT_1,The register configures the 16-bit base address extension of the UV buffer for two plane YUV or the RGB buffer for two plane RGB565-A8. 0 & 1 : For ping-pong mechanism with external trigger. based on the field polarity. Shadow.." hexmask.long.word 0xC 0.--15. 1. "BA_UV_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0x10 "DISPC_0_VIDL2_CSC_COEF7,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x10 19.--31. 1. "POSTOFFSET3,Row-3 post-offset. Encoded signed value [from -4096 to 4095]" hexmask.long.word 0x10 3.--15. 1. "POSTOFFSET2,Row-2 post-offset. Encoded signed value [from -4096 to 4095]" rgroup.long 0x248++0x13 line.long 0x0 "DISPC_0_VIDL2_ROW_INC_UV,The register configures the number of bytes to increment at the end of the row for the UV buffer associated with the video window for YUV420 formats. For non-YUV420 formats this register is unused. Shadow register" hexmask.long 0x0 0.--31. 1. "ROWINC,Number of bytes to increment at the end of the row Encoded signed value [from -2^31-1 to 2^31] to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid The value 1 means next pixel. The value.." line.long 0x4 "DISPC_0_VIDL2_TILE,Defines the characteristics of the position of the first pixel inside the compressed frame buffer. In case of non-compressed frame buffer. the register is not used." hexmask.long.tbyte 0x4 0.--22. 1. "TILEINDEX,Defines the tile number for the first tile of the frame buffer: -0 means that the first tile is accessed otherwise some tiles are skipped to support cropping of the frame buffer" line.long 0x8 "DISPC_0_VIDL2_TILE2,Defines the number of tiles in the frame buffer. In case of non-compressed frame buffer. the register is not used." hexmask.long.tbyte 0x8 0.--22. 1. "NUM_TILES,Defines the total number of tiles in the compressed frame buffer" line.long 0xC "DISPC_0_VIDL2_FBDC_ATTRIBUTES,Defines the attributes for the compression engine -FBDC" bitfld.long 0xC 8.--9. "TILETYPE,FBDC tile-type" "0,1,2,3" hexmask.long.byte 0xC 1.--7. 1. "FORMAT,FBDC format" newline bitfld.long 0xC 0. "ENABLE,Frame Buffer Compression is Enabled. Transactions shall use secondary master port" "0,1" line.long 0x10 "DISPC_0_VIDL2_FBDC_CLEAR_COLOR,Defines the Clear Color value to be used for the channel in FBDC" hexmask.long 0x10 0.--31. 1. "CLEARCOLOR,Defines the Clear Color value to be used for the channel in FBDC" rgroup.long 0x260++0x3F line.long 0x0 "DISPC_0_VIDL2_CLUT_0,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x0 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x0 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x0 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x0 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x4 "DISPC_0_VIDL2_CLUT_1,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x4 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x4 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x4 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x4 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x8 "DISPC_0_VIDL2_CLUT_2,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x8 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x8 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x8 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x8 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0xC "DISPC_0_VIDL2_CLUT_3,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0xC 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0xC 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0xC 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0xC 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x10 "DISPC_0_VIDL2_CLUT_4,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x10 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x10 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x10 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x10 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x14 "DISPC_0_VIDL2_CLUT_5,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x14 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x14 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x14 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x14 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x18 "DISPC_0_VIDL2_CLUT_6,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x18 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x18 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x18 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x18 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x1C "DISPC_0_VIDL2_CLUT_7,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x1C 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x1C 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x1C 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x1C 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x20 "DISPC_0_VIDL2_CLUT_8,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x20 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x20 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x20 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x20 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x24 "DISPC_0_VIDL2_CLUT_9,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x24 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x24 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x24 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x24 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x28 "DISPC_0_VIDL2_CLUT_10,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x28 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x28 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x28 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x28 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x2C "DISPC_0_VIDL2_CLUT_11,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x2C 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x2C 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x2C 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x2C 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x30 "DISPC_0_VIDL2_CLUT_12,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x30 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x30 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x30 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x30 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x34 "DISPC_0_VIDL2_CLUT_13,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x34 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x34 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x34 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x34 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x38 "DISPC_0_VIDL2_CLUT_14,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x38 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x38 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x38 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x38 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" line.long 0x3C "DISPC_0_VIDL2_CLUT_15,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" bitfld.long 0x3C 31. "INDEX,Write 1 to reset the index" "0,1" hexmask.long.word 0x3C 20.--29. 1. "VALUE_R,10-bit R-value to store at the location in the table defined by the incrementing INDEX" newline hexmask.long.word 0x3C 10.--19. 1. "VALUE_G,10-bit G-value to store at the location in the table defined by the incrementing INDEX" hexmask.long.word 0x3C 0.--9. 1. "VALUE_B,10-bit B-value to store at the location in the table defined by the incrementing INDEX" rgroup.long 0x2A0++0x3 line.long 0x0 "DISPC_0_VIDL2_SAFETY_ATTRIBUTES,The register configures the safety sub-region. Shadow register" bitfld.long 0x0 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" hexmask.long.byte 0x0 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature. When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur. Note: The freeze frame counter is cleared on reset -OR- MISR.." newline bitfld.long 0x0 2. "SEEDSELECT,Initial seed selection control" "0,1" bitfld.long 0x0 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x0 0. "ENABLE,Safety check Enable for the region. Note: Transition from 0 to 1 clears the signature register" "0,1" rgroup.long 0x2A4++0x3 line.long 0x0 "DISPC_0_VIDL2_SAFETY_CAPT_SIGNATURE,The register captures the signature from the MISR of the safety sub-region. Shadow register" hexmask.long 0x0 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region. Shadow register" rgroup.long 0x2A8++0x23 line.long 0x0 "DISPC_0_VIDL2_SAFETY_POSITION,The register configures the position of the safety sub-region. Shadow register" hexmask.long.word 0x0 16.--29. 1. "POSY,Y position of the safety sub-region. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen. The first line on the top of the screen has the Y-position 0" hexmask.long.word 0x0 0.--13. 1. "POSX,X position of the safety sub-region. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x4 "DISPC_0_VIDL2_SAFETY_REF_SIGNATURE,The register configures the reference signature of the safety sub-region. Shadow register" hexmask.long 0x4 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region. Shadow register" line.long 0x8 "DISPC_0_VIDL2_SAFETY_SIZE,The register configures the size of the safety sub-region. Shadow register" hexmask.long.word 0x8 16.--29. 1. "SIZEY,Height of the safety sub-region. Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen. One line height region has value of 0" hexmask.long.word 0x8 0.--13. 1. "SIZEX,Width of the safety sub-region. Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen. One pixel wide region has value of 0" line.long 0xC "DISPC_0_VIDL2_SAFETY_LFSR_SEED,The register configures the seed [initial value] of the MISR. Otherwise. the MISR is initialized with 0xFFFF_FFFF. Shadow register" hexmask.long 0xC 0.--31. 1. "SEED,The register configures the seed [initial value] of the MISR. Otherwise the MISR is initialized with 0xFFFF_FFFF. Shadow register" line.long 0x10 "DISPC_0_VIDL2_LUMAKEY,The register configures the LUMA KEY transparency min and max values. Shadow register" hexmask.long.byte 0x10 28.--31. 1. "RESERVED1,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 16.--27. 1. "LUMAKEYMAX,12b luma_key_max value" newline hexmask.long.byte 0x10 12.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 0.--11. 1. "LUMAKEYMIN,12b luma_key_min value" line.long 0x14 "DISPC_0_VIDL2_DMA_BUFSIZE,The register configures the DMA buffer size allocated to the pipeline - New Shared memory feature" hexmask.long.byte 0x14 0.--4. 1. "BUFSIZE,DMA buffer size if VID pipe is enabled.If the value programmed is n then the allocated buffer size is 16KB*n. Default:64KB" line.long 0x18 "DISPC_0_VIDL2_CROP,Defines the attributes for the output cropping in Video Pipe" hexmask.long.byte 0x18 24.--28. 1. "CROPBOTTOM,Crop Bottom in Lines. Values from 0-31" hexmask.long.byte 0x18 16.--20. 1. "CROPTOP,Crop Top in Lines. Values from 0-31" newline hexmask.long.byte 0x18 8.--12. 1. "CROPRIGHT,Crop Right in Pixels. Values from 0-31" hexmask.long.byte 0x18 0.--4. 1. "CROPLEFT,Crop Left in Pixels. Values from 0-31" line.long 0x1C "DISPC_0_VIDL2_SECURE,Security bit settings for the sub-module" bitfld.long 0x1C 0. "SECURE,Secure bit" "0,1" line.long 0x20 "DISPC_0_VIDL2_PIPE_GO,PIPE GO bit settings" bitfld.long 0x20 0. "GOBIT,Go bit" "0,1" tree.end tree "DSS0_VP1 (DSS0_VP1)" base ad:0x4A80000 rgroup.long 0x0++0x1F line.long 0x0 "DISPC_0_VP1_CONFIG,The control register configures the Display Controller module for the VP output. Shadow register." hexmask.long.byte 0x0 27.--31. 1. "RESERVED3," newline bitfld.long 0x0 26. "COLORCONVPOS,Determines the position of the COLORCONV module" "0,1" newline bitfld.long 0x0 25. "FULLRANGE,Color Space Conversion full range setting" "0,1" newline bitfld.long 0x0 24. "COLORCONVENABLE,Enable the color space conversion. The coefficients and offsets used are all programmable and controlled by CPR_COEFF_* and CPR_OFFSET_* registers" "0,1" newline bitfld.long 0x0 23. "FIDFIRST,Selects the first field to output in case of interlace mode. In case of progressive mode the value is not used" "0,1" newline bitfld.long 0x0 22. "OUTPUTMODEENABLE,Selects between progressive and interlace mode for the VP output" "0,1" newline bitfld.long 0x0 21. "BT1120ENABLE,Selects BT-1120 format on the VP output. It is not possible to enable BT656 and BT1120 at the same time one the same LCD output" "0,1" newline bitfld.long 0x0 20. "BT656ENABLE,Selects BT-656 format on the VP output. It is not possible to enable BT656 and BT1120 at the same time one the same LCD output" "0,1" newline rbitfld.long 0x0 17.--19. "RESERVED2,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "BUFFERHANDSHAKE,Deprecated. Always write 0" "0,1" newline bitfld.long 0x0 15. "CPR,Deprecated. Always write 0" "0,1" newline hexmask.long.byte 0x0 9.--14. 1. "RESERVED1,Write 0's for future compatibility Reads return 0" newline bitfld.long 0x0 8. "EXTERNALSYNCEN,Deprecated. Always write 0" "0,1" newline bitfld.long 0x0 7. "VSYNCGATED,VSYNC Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 6. "HSYNCGATED,HSYNC Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 5. "PIXELCLOCKGATED,Pixel Clock Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 4. "PIXELDATAGATED,Pixel Data Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 3. "HDMIMODE,Deprecated. Always write 0" "0,1" newline bitfld.long 0x0 2. "GAMMAENABLE,Enable the gamma Shadow bit-field" "0,1" newline bitfld.long 0x0 1. "DATAENABLEGATED,DE Gated Enable Shadow bit-field" "0,1" newline bitfld.long 0x0 0. "PIXELGATED,Pixel Gated Enable. Shadow bit-field" "0,1" line.long 0x4 "DISPC_0_VP1_CONTROL,The control register configures the Display Controller module for the VP output" bitfld.long 0x4 30.--31. "SPATIALTEMPORALDITHERINGFRAMES,Spatial/Temporal dithering number of frames for the VP output Shadow bit-field" "0,1,2,3" newline rbitfld.long 0x4 27.--29. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 25.--26. "TDMUNUSEDBITS,State of unused bits [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3" newline bitfld.long 0x4 23.--24. "TDMCYCLEFORMAT,Cycle format [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3" newline bitfld.long 0x4 21.--22. "TDMPARALLELMODE,Output Interface width [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3" newline bitfld.long 0x4 20. "TDMENABLE,Enable the multiple cycle format for the VP output Shadow bit-field" "0,1" newline rbitfld.long 0x4 17.--19. "RESERVED1," "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 14.--16. "HT,Hold Time for output. Shadow bit-field. Encoded value [from 1 to 8] to specify the number of external digital clock periods to hold the data [programmed value = value minus one]" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 13. "RESERVED3," "0,1" newline bitfld.long 0x4 12. "STALLMODETYPE,The type of transfer in STALLMODE - If STALLMODE is enabled" "0,1" newline bitfld.long 0x4 11. "STALLMODE,Enable the STALLMODE on DPI output" "0,1" newline bitfld.long 0x4 8.--10. "DATALINES,Width of the data bus on VP output Shadow bit-field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "STDITHERENABLE,Spatial Temporal dithering enable for the VP output Shadow bit-field" "0,1" newline bitfld.long 0x4 6. "DPIENABLE,Enable the DPI output. wr:immediate" "0,1" newline bitfld.long 0x4 5. "GOBIT,GO Command for the VP output. It is used to synchronize the pipelines associated with the VP output wr:immediate" "0,1" newline bitfld.long 0x4 4. "M8B,Deprecated. Always write 0" "0,1" newline bitfld.long 0x4 3. "STN,Deprecated. Always write 0" "0,1" newline bitfld.long 0x4 2. "MONOCOLOR,Deprecated. Always write 0" "0,1" newline bitfld.long 0x4 1. "VPPROGLINENUMBERMODULO,Enable the modulo of the line number interrupt generation" "0,1" newline bitfld.long 0x4 0. "ENABLE,Enable the video port output. wr:immediate" "0,1" line.long 0x8 "DISPC_0_VP1_CSC_COEF0,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x8 16.--26. 1. "C01,C01 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x8 11.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x8 0.--10. 1. "C00,C00 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0xC "DISPC_0_VP1_CSC_COEF1,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0xC 27.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0xC 16.--26. 1. "C10,C10 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0xC 11.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0xC 0.--10. 1. "C02,C02 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x10 "DISPC_0_VP1_CSC_COEF2,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x10 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.word 0x10 16.--26. 1. "C12,C12 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x10 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.word 0x10 0.--10. 1. "C11,C11 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x14 "DISPC_0_VP1_DATA_CYCLE_0,The control register configures the output data format over up to 3 cycles. Shadow register" hexmask.long.byte 0x14 28.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.byte 0x14 24.--27. 1. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" newline rbitfld.long 0x14 21.--23. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 16.--20. 1. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" newline hexmask.long.byte 0x14 12.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.byte 0x14 8.--11. 1. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" newline rbitfld.long 0x14 5.--7. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--4. 1. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" line.long 0x18 "DISPC_0_VP1_DATA_CYCLE_1,The control register configures the output data format over up to 3 cycles. Shadow register" hexmask.long.byte 0x18 28.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.byte 0x18 24.--27. 1. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" newline rbitfld.long 0x18 21.--23. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 16.--20. 1. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" newline hexmask.long.byte 0x18 12.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.byte 0x18 8.--11. 1. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" newline rbitfld.long 0x18 5.--7. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--4. 1. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" line.long 0x1C "DISPC_0_VP1_DATA_CYCLE_2,The control register configures the output data format over up to 3 cycles. Shadow register" hexmask.long.byte 0x1C 28.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.byte 0x1C 24.--27. 1. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" newline rbitfld.long 0x1C 21.--23. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 16.--20. 1. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.byte 0x1C 8.--11. 1. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" newline rbitfld.long 0x1C 5.--7. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 0.--4. 1. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" rgroup.long 0x44++0x3 line.long 0x0 "DISPC_0_VP1_LINE_NUMBER,The control register indicates the panel display line number for the interrupt and the DMA request. Shadow register" hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--13. 1. "LINENUMBER,LCD panel line number programming LCD line number defines the line on which the programmable interrupt is generated and the DMA request occurs" rgroup.long 0x4C++0x43 line.long 0x0 "DISPC_0_VP1_POL_FREQ,The register configures the signal configuration. Shadow register" hexmask.long.word 0x0 19.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline bitfld.long 0x0 18. "ALIGN,Defines the alignment between HSYNC and VSYNC assertion" "0,1" newline bitfld.long 0x0 17. "ONOFF,HSYNC/VSYNC Pixel clock Control On/Off" "0,1" newline bitfld.long 0x0 16. "RF,Program HSYNC/VSYNC Rise or Fall" "0,1" newline bitfld.long 0x0 15. "IEO,Invert output enable" "0,1" newline bitfld.long 0x0 14. "IPC,Invert pixel clock" "0,1" newline bitfld.long 0x0 13. "IHS,Invert HSYNC" "0,1" newline bitfld.long 0x0 12. "IVS,Invert VSYNC" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "ACBI,AC Bias Pin transitions per interrupt Value [from 0 to 15] used to specify the number of AC Bias pin transitions" newline hexmask.long.byte 0x0 0.--7. 1. "ACB,AC Bias Pin Frequency Value [from 0 to 255] used to specify the number of line clocks to count before transitioning the AC Bias pin. This pin is used to periodically invert the polarity of the power supply to prevent DC charge build-up within the.." line.long 0x4 "DISPC_0_VP1_SIZE_SCREEN,The register configures the panel size horizontal and vertical. Shadow register. A delta value is used to indicate if the odd field has same vertical size as the even field or +/- one line." hexmask.long.word 0x4 16.--29. 1. "LPP,Lines per panel Encoded value [from 1 to 16384] to specify the number of lines per panel [program to value minus one]" newline bitfld.long 0x4 14.--15. "DELTA_LPP,Indicates the delta size value of the odd field compared to the even field" "0,1,2,3" newline hexmask.long.word 0x4 0.--13. 1. "PPL,Pixels per line Encoded value [from 1 to 16384] to specify the number of pixels contains within each line on the display [program to value minus one]. In STALL mode any value is valid In non-STALL mode only values multiple of 8 pixels are valid" line.long 0x8 "DISPC_0_VP1_TIMING_H,The register configures the timing logic for the HSYNC signal. Shadow register" hexmask.long.word 0x8 20.--31. 1. "HBP,Horizontal Back Porch Encoded value [from 1 to 4096] to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display [program to value minus one] When in BT mode and.." newline hexmask.long.word 0x8 8.--19. 1. "HFP,Horizontal front porch Encoded value [from 1 to 4096] to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted display [program to value minus one] When in BT mode and interlaced this field.." newline hexmask.long.byte 0x8 0.--7. 1. "HSW,Horizontal synchronization pulse width Encoded value [from 1 to 256] to specify the number of pixel clock periods to pulse the line clock at the end of each line display [program to value minus one] When in BT mode this field corresponds to the LSB.." line.long 0xC "DISPC_0_VP1_TIMING_V,The register configures the timing logic for the VSYNC signal. Shadow register" hexmask.long.word 0xC 20.--31. 1. "VBP,Vertical back porch Encoded value [from 0 to 4095] to specify the number of line clock periods to add to the beginning of a frame When in BT mode and interlaced this field corresponds to the vertical field blanking No 2 for Odd Field When in BT and.." newline hexmask.long.word 0xC 8.--19. 1. "VFP,Vertical front porch Encoded value [from 0 to 4095] to specify the number of line clock periods to add to the end of each frame When in BT mode and interlaced this field corresponds to the vertical field blanking No 1 for Odd Field When in BT and in.." newline hexmask.long.byte 0xC 0.--7. 1. "VSW,Vertical synchronization pulse width Encoded value [from 1 to 256] to specify the number of line clock periods to pulse the frame clock [VSYNC] pin at the end of each frame after the end of frame wait [VFP] period elapses Frame clock uses as VSYNC.." line.long 0x10 "DISPC_0_VP1_CSC_COEF3,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x10 27.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x10 16.--26. 1. "C21,C21 coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x10 11.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x10 0.--10. 1. "C20,C20 coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x14 "DISPC_0_VP1_CSC_COEF4,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.tbyte 0x14 11.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x14 0.--10. 1. "C22,C22 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x18 "DISPC_0_VP1_CSC_COEF5,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x18 19.--31. 1. "PREOFFSET2,Row-2 pre-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x18 16.--18. "RESERVED1," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x18 3.--15. 1. "PREOFFSET1,Row1 pre-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x18 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x1C "DISPC_0_VP1_CSC_COEF6,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x1C 19.--31. 1. "POSTOFFSET1,Row-1 post-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x1C 16.--18. "RESERVED1," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1C 3.--15. 1. "PREOFFSET3,Row-3 pre-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x1C 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x20 "DISPC_0_VP1_CSC_COEF7,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x20 19.--31. 1. "POSTOFFSET3,Row-3 post-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x20 16.--18. "RESERVED1," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x20 3.--15. 1. "POSTOFFSET2,Row-2 post-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x20 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x24 "DISPC_0_VP1_SAFETY_ATTRIBUTES_0,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x24 13.--31. 1. "RESERVED," newline bitfld.long 0x24 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x24 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x24 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x24 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x24 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x28 "DISPC_0_VP1_SAFETY_ATTRIBUTES_1,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x28 13.--31. 1. "RESERVED," newline bitfld.long 0x28 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x28 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x28 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x28 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x28 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x2C "DISPC_0_VP1_SAFETY_ATTRIBUTES_2,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x2C 13.--31. 1. "RESERVED," newline bitfld.long 0x2C 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x2C 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x2C 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x2C 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x2C 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x30 "DISPC_0_VP1_SAFETY_ATTRIBUTES_3,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x30 13.--31. 1. "RESERVED," newline bitfld.long 0x30 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x30 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x30 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x30 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x30 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x34 "DISPC_0_VP1_SAFETY_ATTRIBUTES_4,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x34 13.--31. 1. "RESERVED," newline bitfld.long 0x34 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x34 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x34 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x34 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x34 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x38 "DISPC_0_VP1_SAFETY_ATTRIBUTES_5,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x38 13.--31. 1. "RESERVED," newline bitfld.long 0x38 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x38 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x38 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x38 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x38 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x3C "DISPC_0_VP1_SAFETY_ATTRIBUTES_6,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x3C 13.--31. 1. "RESERVED," newline bitfld.long 0x3C 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x3C 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x3C 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x3C 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x3C 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x40 "DISPC_0_VP1_SAFETY_ATTRIBUTES_7,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x40 13.--31. 1. "RESERVED," newline bitfld.long 0x40 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x40 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x40 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x40 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x40 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" rgroup.long 0x90++0x1F line.long 0x0 "DISPC_0_VP1_SAFETY_CAPT_SIGNATURE_0,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x0 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x4 "DISPC_0_VP1_SAFETY_CAPT_SIGNATURE_1,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x4 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x8 "DISPC_0_VP1_SAFETY_CAPT_SIGNATURE_2,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x8 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0xC "DISPC_0_VP1_SAFETY_CAPT_SIGNATURE_3,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0xC 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x10 "DISPC_0_VP1_SAFETY_CAPT_SIGNATURE_4,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x10 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x14 "DISPC_0_VP1_SAFETY_CAPT_SIGNATURE_5,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x14 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x18 "DISPC_0_VP1_SAFETY_CAPT_SIGNATURE_6,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x18 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x1C "DISPC_0_VP1_SAFETY_CAPT_SIGNATURE_7,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x1C 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" rgroup.long 0xB0++0x63 line.long 0x0 "DISPC_0_VP1_SAFETY_POSITION_0,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x0 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x0 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x4 "DISPC_0_VP1_SAFETY_POSITION_1,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x4 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x4 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x8 "DISPC_0_VP1_SAFETY_POSITION_2,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x8 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x8 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0xC "DISPC_0_VP1_SAFETY_POSITION_3,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0xC 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0xC 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x10 "DISPC_0_VP1_SAFETY_POSITION_4,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x10 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x10 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x14 "DISPC_0_VP1_SAFETY_POSITION_5,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x14 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x14 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x18 "DISPC_0_VP1_SAFETY_POSITION_6,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x18 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x18 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x1C "DISPC_0_VP1_SAFETY_POSITION_7,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x1C 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x1C 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x20 "DISPC_0_VP1_SAFETY_REF_SIGNATURE_0,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x20 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x24 "DISPC_0_VP1_SAFETY_REF_SIGNATURE_1,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x24 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x28 "DISPC_0_VP1_SAFETY_REF_SIGNATURE_2,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x28 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x2C "DISPC_0_VP1_SAFETY_REF_SIGNATURE_3,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x2C 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x30 "DISPC_0_VP1_SAFETY_REF_SIGNATURE_4,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x30 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x34 "DISPC_0_VP1_SAFETY_REF_SIGNATURE_5,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x34 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x38 "DISPC_0_VP1_SAFETY_REF_SIGNATURE_6,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x38 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x3C "DISPC_0_VP1_SAFETY_REF_SIGNATURE_7,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x3C 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x40 "DISPC_0_VP1_SAFETY_SIZE_0,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x40 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x40 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x44 "DISPC_0_VP1_SAFETY_SIZE_1,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x44 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x44 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x48 "DISPC_0_VP1_SAFETY_SIZE_2,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x48 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x48 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x4C "DISPC_0_VP1_SAFETY_SIZE_3,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x4C 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x4C 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x50 "DISPC_0_VP1_SAFETY_SIZE_4,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x50 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x50 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x54 "DISPC_0_VP1_SAFETY_SIZE_5,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x54 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x54 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x58 "DISPC_0_VP1_SAFETY_SIZE_6,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x58 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x58 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x5C "DISPC_0_VP1_SAFETY_SIZE_7,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x5C 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x5C 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x60 "DISPC_0_VP1_SAFETY_LFSR_SEED,The register configures the seed initial signature value of MISRs that are to be initialized with a user programmed initial value. Otherwise. the MISR is initialized with 0xFFFF_FFFF. Shadow register." hexmask.long 0x60 0.--31. 1. "SEED,The register configures the seed [initial signature value] of MISRs that are to be initialized with a user programmed initial value Otherwise the MISR is initialized with 0xFFFF_FFFF Shadow register" rgroup.long 0x120++0x3F line.long 0x0 "DISPC_0_VP1_GAMMA_TABLE_0,The register configures the gamma table on VP output." bitfld.long 0x0 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x0 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x0 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x0 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x4 "DISPC_0_VP1_GAMMA_TABLE_1,The register configures the gamma table on VP output." bitfld.long 0x4 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x4 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x4 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x4 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x8 "DISPC_0_VP1_GAMMA_TABLE_2,The register configures the gamma table on VP output." bitfld.long 0x8 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x8 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x8 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x8 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0xC "DISPC_0_VP1_GAMMA_TABLE_3,The register configures the gamma table on VP output." bitfld.long 0xC 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0xC 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0xC 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0xC 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x10 "DISPC_0_VP1_GAMMA_TABLE_4,The register configures the gamma table on VP output." bitfld.long 0x10 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x10 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x10 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x10 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x14 "DISPC_0_VP1_GAMMA_TABLE_5,The register configures the gamma table on VP output." bitfld.long 0x14 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x14 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x14 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x14 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x18 "DISPC_0_VP1_GAMMA_TABLE_6,The register configures the gamma table on VP output." bitfld.long 0x18 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x18 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x18 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x18 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x1C "DISPC_0_VP1_GAMMA_TABLE_7,The register configures the gamma table on VP output." bitfld.long 0x1C 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x1C 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x1C 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x1C 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x20 "DISPC_0_VP1_GAMMA_TABLE_8,The register configures the gamma table on VP output." bitfld.long 0x20 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x20 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x20 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x20 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x24 "DISPC_0_VP1_GAMMA_TABLE_9,The register configures the gamma table on VP output." bitfld.long 0x24 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x24 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x24 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x24 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x28 "DISPC_0_VP1_GAMMA_TABLE_10,The register configures the gamma table on VP output." bitfld.long 0x28 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x28 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x28 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x28 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x2C "DISPC_0_VP1_GAMMA_TABLE_11,The register configures the gamma table on VP output." bitfld.long 0x2C 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x2C 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x2C 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x2C 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x30 "DISPC_0_VP1_GAMMA_TABLE_12,The register configures the gamma table on VP output." bitfld.long 0x30 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x30 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x30 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x30 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x34 "DISPC_0_VP1_GAMMA_TABLE_13,The register configures the gamma table on VP output." bitfld.long 0x34 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x34 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x34 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x34 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x38 "DISPC_0_VP1_GAMMA_TABLE_14,The register configures the gamma table on VP output." bitfld.long 0x38 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x38 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x38 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x38 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x3C "DISPC_0_VP1_GAMMA_TABLE_15,The register configures the gamma table on VP output." bitfld.long 0x3C 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x3C 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x3C 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x3C 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" rgroup.long 0x160++0xB line.long 0x0 "DISPC_0_VP1_DSS_OLDI_CFG,Reserved" line.long 0x4 "DISPC_0_VP1_DSS_OLDI_STATUS,Reserved" line.long 0x8 "DISPC_0_VP1_DSS_OLDI_LB,Reserved" rgroup.long 0x178++0x3 line.long 0x0 "DISPC_0_VP1_SECURE,Security bit settings for the sub-module" bitfld.long 0x0 0. "SECURE,Secure bit" "0,1" tree.end tree "DSS0_VP2 (DSS0_VP2)" base ad:0x4AA0000 rgroup.long 0x0++0x1F line.long 0x0 "DISPC_0_VP2_CONFIG,The control register configures the Display Controller module for the VP output. Shadow register." hexmask.long.byte 0x0 27.--31. 1. "RESERVED3," newline bitfld.long 0x0 26. "COLORCONVPOS,Determines the position of the COLORCONV module" "0,1" newline bitfld.long 0x0 25. "FULLRANGE,Color Space Conversion full range setting" "0,1" newline bitfld.long 0x0 24. "COLORCONVENABLE,Enable the color space conversion. The coefficients and offsets used are all programmable and controlled by CPR_COEFF_* and CPR_OFFSET_* registers" "0,1" newline bitfld.long 0x0 23. "FIDFIRST,Selects the first field to output in case of interlace mode. In case of progressive mode the value is not used" "0,1" newline bitfld.long 0x0 22. "OUTPUTMODEENABLE,Selects between progressive and interlace mode for the VP output" "0,1" newline bitfld.long 0x0 21. "BT1120ENABLE,Selects BT-1120 format on the VP output. It is not possible to enable BT656 and BT1120 at the same time one the same LCD output" "0,1" newline bitfld.long 0x0 20. "BT656ENABLE,Selects BT-656 format on the VP output. It is not possible to enable BT656 and BT1120 at the same time one the same LCD output" "0,1" newline rbitfld.long 0x0 17.--19. "RESERVED2,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "BUFFERHANDSHAKE,Deprecated. Always write 0" "0,1" newline bitfld.long 0x0 15. "CPR,Deprecated. Always write 0" "0,1" newline hexmask.long.byte 0x0 9.--14. 1. "RESERVED1,Write 0's for future compatibility Reads return 0" newline bitfld.long 0x0 8. "EXTERNALSYNCEN,Deprecated. Always write 0" "0,1" newline bitfld.long 0x0 7. "VSYNCGATED,VSYNC Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 6. "HSYNCGATED,HSYNC Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 5. "PIXELCLOCKGATED,Pixel Clock Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 4. "PIXELDATAGATED,Pixel Data Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 3. "HDMIMODE,Deprecated. Always write 0" "0,1" newline bitfld.long 0x0 2. "GAMMAENABLE,Enable the gamma Shadow bit-field" "0,1" newline bitfld.long 0x0 1. "DATAENABLEGATED,DE Gated Enable Shadow bit-field" "0,1" newline bitfld.long 0x0 0. "PIXELGATED,Pixel Gated Enable. Shadow bit-field" "0,1" line.long 0x4 "DISPC_0_VP2_CONTROL,The control register configures the Display Controller module for the VP output" bitfld.long 0x4 30.--31. "SPATIALTEMPORALDITHERINGFRAMES,Spatial/Temporal dithering number of frames for the VP output Shadow bit-field" "0,1,2,3" newline rbitfld.long 0x4 27.--29. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 25.--26. "TDMUNUSEDBITS,State of unused bits [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3" newline bitfld.long 0x4 23.--24. "TDMCYCLEFORMAT,Cycle format [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3" newline bitfld.long 0x4 21.--22. "TDMPARALLELMODE,Output Interface width [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3" newline bitfld.long 0x4 20. "TDMENABLE,Enable the multiple cycle format for the VP output Shadow bit-field" "0,1" newline rbitfld.long 0x4 17.--19. "RESERVED1," "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 14.--16. "HT,Hold Time for output. Shadow bit-field. Encoded value [from 1 to 8] to specify the number of external digital clock periods to hold the data [programmed value = value minus one]" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 13. "RESERVED3," "0,1" newline bitfld.long 0x4 12. "STALLMODETYPE,The type of transfer in STALLMODE - If STALLMODE is enabled" "0,1" newline bitfld.long 0x4 11. "STALLMODE,Enable the STALLMODE on DPI output" "0,1" newline bitfld.long 0x4 8.--10. "DATALINES,Width of the data bus on VP output Shadow bit-field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "STDITHERENABLE,Spatial Temporal dithering enable for the VP output Shadow bit-field" "0,1" newline bitfld.long 0x4 6. "DPIENABLE,Enable the DPI output. wr:immediate" "0,1" newline bitfld.long 0x4 5. "GOBIT,GO Command for the VP output. It is used to synchronize the pipelines associated with the VP output wr:immediate" "0,1" newline bitfld.long 0x4 4. "M8B,Deprecated. Always write 0" "0,1" newline bitfld.long 0x4 3. "STN,Deprecated. Always write 0" "0,1" newline bitfld.long 0x4 2. "MONOCOLOR,Deprecated. Always write 0" "0,1" newline bitfld.long 0x4 1. "VPPROGLINENUMBERMODULO,Enable the modulo of the line number interrupt generation" "0,1" newline bitfld.long 0x4 0. "ENABLE,Enable the video port output. wr:immediate" "0,1" line.long 0x8 "DISPC_0_VP2_CSC_COEF0,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x8 16.--26. 1. "C01,C01 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x8 11.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x8 0.--10. 1. "C00,C00 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0xC "DISPC_0_VP2_CSC_COEF1,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0xC 27.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0xC 16.--26. 1. "C10,C10 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0xC 11.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0xC 0.--10. 1. "C02,C02 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x10 "DISPC_0_VP2_CSC_COEF2,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x10 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.word 0x10 16.--26. 1. "C12,C12 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x10 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.word 0x10 0.--10. 1. "C11,C11 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x14 "DISPC_0_VP2_DATA_CYCLE_0,The control register configures the output data format over up to 3 cycles. Shadow register" hexmask.long.byte 0x14 28.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.byte 0x14 24.--27. 1. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" newline rbitfld.long 0x14 21.--23. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 16.--20. 1. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" newline hexmask.long.byte 0x14 12.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.byte 0x14 8.--11. 1. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" newline rbitfld.long 0x14 5.--7. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--4. 1. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" line.long 0x18 "DISPC_0_VP2_DATA_CYCLE_1,The control register configures the output data format over up to 3 cycles. Shadow register" hexmask.long.byte 0x18 28.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.byte 0x18 24.--27. 1. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" newline rbitfld.long 0x18 21.--23. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 16.--20. 1. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" newline hexmask.long.byte 0x18 12.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.byte 0x18 8.--11. 1. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" newline rbitfld.long 0x18 5.--7. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--4. 1. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" line.long 0x1C "DISPC_0_VP2_DATA_CYCLE_2,The control register configures the output data format over up to 3 cycles. Shadow register" hexmask.long.byte 0x1C 28.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.byte 0x1C 24.--27. 1. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" newline rbitfld.long 0x1C 21.--23. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 16.--20. 1. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.byte 0x1C 8.--11. 1. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" newline rbitfld.long 0x1C 5.--7. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 0.--4. 1. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" rgroup.long 0x44++0x3 line.long 0x0 "DISPC_0_VP2_LINE_NUMBER,The control register indicates the panel display line number for the interrupt and the DMA request. Shadow register" hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--13. 1. "LINENUMBER,LCD panel line number programming LCD line number defines the line on which the programmable interrupt is generated and the DMA request occurs" rgroup.long 0x4C++0x43 line.long 0x0 "DISPC_0_VP2_POL_FREQ,The register configures the signal configuration. Shadow register" hexmask.long.word 0x0 19.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline bitfld.long 0x0 18. "ALIGN,Defines the alignment between HSYNC and VSYNC assertion" "0,1" newline bitfld.long 0x0 17. "ONOFF,HSYNC/VSYNC Pixel clock Control On/Off" "0,1" newline bitfld.long 0x0 16. "RF,Program HSYNC/VSYNC Rise or Fall" "0,1" newline bitfld.long 0x0 15. "IEO,Invert output enable" "0,1" newline bitfld.long 0x0 14. "IPC,Invert pixel clock" "0,1" newline bitfld.long 0x0 13. "IHS,Invert HSYNC" "0,1" newline bitfld.long 0x0 12. "IVS,Invert VSYNC" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "ACBI,AC Bias Pin transitions per interrupt Value [from 0 to 15] used to specify the number of AC Bias pin transitions" newline hexmask.long.byte 0x0 0.--7. 1. "ACB,AC Bias Pin Frequency Value [from 0 to 255] used to specify the number of line clocks to count before transitioning the AC Bias pin. This pin is used to periodically invert the polarity of the power supply to prevent DC charge build-up within the.." line.long 0x4 "DISPC_0_VP2_SIZE_SCREEN,The register configures the panel size horizontal and vertical. Shadow register. A delta value is used to indicate if the odd field has same vertical size as the even field or +/- one line." hexmask.long.word 0x4 16.--29. 1. "LPP,Lines per panel Encoded value [from 1 to 16384] to specify the number of lines per panel [program to value minus one]" newline bitfld.long 0x4 14.--15. "DELTA_LPP,Indicates the delta size value of the odd field compared to the even field" "0,1,2,3" newline hexmask.long.word 0x4 0.--13. 1. "PPL,Pixels per line Encoded value [from 1 to 16384] to specify the number of pixels contains within each line on the display [program to value minus one]. In STALL mode any value is valid In non-STALL mode only values multiple of 8 pixels are valid" line.long 0x8 "DISPC_0_VP2_TIMING_H,The register configures the timing logic for the HSYNC signal. Shadow register" hexmask.long.word 0x8 20.--31. 1. "HBP,Horizontal Back Porch Encoded value [from 1 to 4096] to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display [program to value minus one] When in BT mode and.." newline hexmask.long.word 0x8 8.--19. 1. "HFP,Horizontal front porch Encoded value [from 1 to 4096] to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted display [program to value minus one] When in BT mode and interlaced this field.." newline hexmask.long.byte 0x8 0.--7. 1. "HSW,Horizontal synchronization pulse width Encoded value [from 1 to 256] to specify the number of pixel clock periods to pulse the line clock at the end of each line display [program to value minus one] When in BT mode this field corresponds to the LSB.." line.long 0xC "DISPC_0_VP2_TIMING_V,The register configures the timing logic for the VSYNC signal. Shadow register" hexmask.long.word 0xC 20.--31. 1. "VBP,Vertical back porch Encoded value [from 0 to 4095] to specify the number of line clock periods to add to the beginning of a frame When in BT mode and interlaced this field corresponds to the vertical field blanking No 2 for Odd Field When in BT and.." newline hexmask.long.word 0xC 8.--19. 1. "VFP,Vertical front porch Encoded value [from 0 to 4095] to specify the number of line clock periods to add to the end of each frame When in BT mode and interlaced this field corresponds to the vertical field blanking No 1 for Odd Field When in BT and in.." newline hexmask.long.byte 0xC 0.--7. 1. "VSW,Vertical synchronization pulse width Encoded value [from 1 to 256] to specify the number of line clock periods to pulse the frame clock [VSYNC] pin at the end of each frame after the end of frame wait [VFP] period elapses Frame clock uses as VSYNC.." line.long 0x10 "DISPC_0_VP2_CSC_COEF3,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x10 27.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x10 16.--26. 1. "C21,C21 coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x10 11.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x10 0.--10. 1. "C20,C20 coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x14 "DISPC_0_VP2_CSC_COEF4,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.tbyte 0x14 11.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x14 0.--10. 1. "C22,C22 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x18 "DISPC_0_VP2_CSC_COEF5,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x18 19.--31. 1. "PREOFFSET2,Row-2 pre-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x18 16.--18. "RESERVED1," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x18 3.--15. 1. "PREOFFSET1,Row1 pre-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x18 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x1C "DISPC_0_VP2_CSC_COEF6,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x1C 19.--31. 1. "POSTOFFSET1,Row-1 post-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x1C 16.--18. "RESERVED1," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1C 3.--15. 1. "PREOFFSET3,Row-3 pre-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x1C 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x20 "DISPC_0_VP2_CSC_COEF7,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x20 19.--31. 1. "POSTOFFSET3,Row-3 post-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x20 16.--18. "RESERVED1," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x20 3.--15. 1. "POSTOFFSET2,Row-2 post-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x20 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x24 "DISPC_0_VP2_SAFETY_ATTRIBUTES_0,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x24 13.--31. 1. "RESERVED," newline bitfld.long 0x24 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x24 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x24 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x24 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x24 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x28 "DISPC_0_VP2_SAFETY_ATTRIBUTES_1,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x28 13.--31. 1. "RESERVED," newline bitfld.long 0x28 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x28 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x28 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x28 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x28 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x2C "DISPC_0_VP2_SAFETY_ATTRIBUTES_2,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x2C 13.--31. 1. "RESERVED," newline bitfld.long 0x2C 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x2C 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x2C 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x2C 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x2C 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x30 "DISPC_0_VP2_SAFETY_ATTRIBUTES_3,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x30 13.--31. 1. "RESERVED," newline bitfld.long 0x30 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x30 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x30 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x30 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x30 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x34 "DISPC_0_VP2_SAFETY_ATTRIBUTES_4,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x34 13.--31. 1. "RESERVED," newline bitfld.long 0x34 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x34 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x34 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x34 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x34 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x38 "DISPC_0_VP2_SAFETY_ATTRIBUTES_5,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x38 13.--31. 1. "RESERVED," newline bitfld.long 0x38 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x38 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x38 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x38 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x38 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x3C "DISPC_0_VP2_SAFETY_ATTRIBUTES_6,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x3C 13.--31. 1. "RESERVED," newline bitfld.long 0x3C 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x3C 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x3C 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x3C 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x3C 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x40 "DISPC_0_VP2_SAFETY_ATTRIBUTES_7,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x40 13.--31. 1. "RESERVED," newline bitfld.long 0x40 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x40 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x40 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x40 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x40 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" rgroup.long 0x90++0x1F line.long 0x0 "DISPC_0_VP2_SAFETY_CAPT_SIGNATURE_0,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x0 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x4 "DISPC_0_VP2_SAFETY_CAPT_SIGNATURE_1,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x4 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x8 "DISPC_0_VP2_SAFETY_CAPT_SIGNATURE_2,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x8 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0xC "DISPC_0_VP2_SAFETY_CAPT_SIGNATURE_3,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0xC 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x10 "DISPC_0_VP2_SAFETY_CAPT_SIGNATURE_4,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x10 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x14 "DISPC_0_VP2_SAFETY_CAPT_SIGNATURE_5,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x14 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x18 "DISPC_0_VP2_SAFETY_CAPT_SIGNATURE_6,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x18 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x1C "DISPC_0_VP2_SAFETY_CAPT_SIGNATURE_7,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x1C 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" rgroup.long 0xB0++0x63 line.long 0x0 "DISPC_0_VP2_SAFETY_POSITION_0,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x0 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x0 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x4 "DISPC_0_VP2_SAFETY_POSITION_1,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x4 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x4 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x8 "DISPC_0_VP2_SAFETY_POSITION_2,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x8 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x8 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0xC "DISPC_0_VP2_SAFETY_POSITION_3,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0xC 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0xC 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x10 "DISPC_0_VP2_SAFETY_POSITION_4,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x10 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x10 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x14 "DISPC_0_VP2_SAFETY_POSITION_5,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x14 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x14 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x18 "DISPC_0_VP2_SAFETY_POSITION_6,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x18 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x18 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x1C "DISPC_0_VP2_SAFETY_POSITION_7,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x1C 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x1C 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x20 "DISPC_0_VP2_SAFETY_REF_SIGNATURE_0,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x20 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x24 "DISPC_0_VP2_SAFETY_REF_SIGNATURE_1,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x24 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x28 "DISPC_0_VP2_SAFETY_REF_SIGNATURE_2,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x28 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x2C "DISPC_0_VP2_SAFETY_REF_SIGNATURE_3,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x2C 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x30 "DISPC_0_VP2_SAFETY_REF_SIGNATURE_4,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x30 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x34 "DISPC_0_VP2_SAFETY_REF_SIGNATURE_5,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x34 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x38 "DISPC_0_VP2_SAFETY_REF_SIGNATURE_6,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x38 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x3C "DISPC_0_VP2_SAFETY_REF_SIGNATURE_7,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x3C 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x40 "DISPC_0_VP2_SAFETY_SIZE_0,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x40 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x40 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x44 "DISPC_0_VP2_SAFETY_SIZE_1,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x44 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x44 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x48 "DISPC_0_VP2_SAFETY_SIZE_2,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x48 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x48 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x4C "DISPC_0_VP2_SAFETY_SIZE_3,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x4C 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x4C 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x50 "DISPC_0_VP2_SAFETY_SIZE_4,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x50 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x50 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x54 "DISPC_0_VP2_SAFETY_SIZE_5,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x54 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x54 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x58 "DISPC_0_VP2_SAFETY_SIZE_6,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x58 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x58 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x5C "DISPC_0_VP2_SAFETY_SIZE_7,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x5C 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x5C 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x60 "DISPC_0_VP2_SAFETY_LFSR_SEED,The register configures the seed initial signature value of MISRs that are to be initialized with a user programmed initial value. Otherwise. the MISR is initialized with 0xFFFF_FFFF. Shadow register." hexmask.long 0x60 0.--31. 1. "SEED,The register configures the seed [initial signature value] of MISRs that are to be initialized with a user programmed initial value Otherwise the MISR is initialized with 0xFFFF_FFFF Shadow register" rgroup.long 0x120++0x3F line.long 0x0 "DISPC_0_VP2_GAMMA_TABLE_0,The register configures the gamma table on VP output." bitfld.long 0x0 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x0 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x0 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x0 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x4 "DISPC_0_VP2_GAMMA_TABLE_1,The register configures the gamma table on VP output." bitfld.long 0x4 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x4 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x4 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x4 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x8 "DISPC_0_VP2_GAMMA_TABLE_2,The register configures the gamma table on VP output." bitfld.long 0x8 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x8 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x8 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x8 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0xC "DISPC_0_VP2_GAMMA_TABLE_3,The register configures the gamma table on VP output." bitfld.long 0xC 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0xC 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0xC 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0xC 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x10 "DISPC_0_VP2_GAMMA_TABLE_4,The register configures the gamma table on VP output." bitfld.long 0x10 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x10 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x10 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x10 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x14 "DISPC_0_VP2_GAMMA_TABLE_5,The register configures the gamma table on VP output." bitfld.long 0x14 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x14 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x14 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x14 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x18 "DISPC_0_VP2_GAMMA_TABLE_6,The register configures the gamma table on VP output." bitfld.long 0x18 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x18 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x18 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x18 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x1C "DISPC_0_VP2_GAMMA_TABLE_7,The register configures the gamma table on VP output." bitfld.long 0x1C 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x1C 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x1C 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x1C 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x20 "DISPC_0_VP2_GAMMA_TABLE_8,The register configures the gamma table on VP output." bitfld.long 0x20 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x20 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x20 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x20 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x24 "DISPC_0_VP2_GAMMA_TABLE_9,The register configures the gamma table on VP output." bitfld.long 0x24 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x24 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x24 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x24 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x28 "DISPC_0_VP2_GAMMA_TABLE_10,The register configures the gamma table on VP output." bitfld.long 0x28 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x28 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x28 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x28 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x2C "DISPC_0_VP2_GAMMA_TABLE_11,The register configures the gamma table on VP output." bitfld.long 0x2C 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x2C 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x2C 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x2C 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x30 "DISPC_0_VP2_GAMMA_TABLE_12,The register configures the gamma table on VP output." bitfld.long 0x30 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x30 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x30 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x30 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x34 "DISPC_0_VP2_GAMMA_TABLE_13,The register configures the gamma table on VP output." bitfld.long 0x34 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x34 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x34 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x34 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x38 "DISPC_0_VP2_GAMMA_TABLE_14,The register configures the gamma table on VP output." bitfld.long 0x38 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x38 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x38 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x38 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x3C "DISPC_0_VP2_GAMMA_TABLE_15,The register configures the gamma table on VP output." bitfld.long 0x3C 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x3C 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x3C 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x3C 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" rgroup.long 0x160++0xB line.long 0x0 "DISPC_0_VP2_DSS_OLDI_CFG,Reserved" line.long 0x4 "DISPC_0_VP2_DSS_OLDI_STATUS,Reserved" line.long 0x8 "DISPC_0_VP2_DSS_OLDI_LB,Reserved" rgroup.long 0x178++0x3 line.long 0x0 "DISPC_0_VP2_SECURE,Security bit settings for the sub-module" bitfld.long 0x0 0. "SECURE,Secure bit" "0,1" tree.end tree "DSS0_VP3 (DSS0_VP3)" base ad:0x4AC0000 rgroup.long 0x0++0x1F line.long 0x0 "DISPC_0_VP3_CONFIG,The control register configures the Display Controller module for the VP output. Shadow register." hexmask.long.byte 0x0 27.--31. 1. "RESERVED3," newline bitfld.long 0x0 26. "COLORCONVPOS,Determines the position of the COLORCONV module" "0,1" newline bitfld.long 0x0 25. "FULLRANGE,Color Space Conversion full range setting" "0,1" newline bitfld.long 0x0 24. "COLORCONVENABLE,Enable the color space conversion. The coefficients and offsets used are all programmable and controlled by CPR_COEFF_* and CPR_OFFSET_* registers" "0,1" newline bitfld.long 0x0 23. "FIDFIRST,Selects the first field to output in case of interlace mode. In case of progressive mode the value is not used" "0,1" newline bitfld.long 0x0 22. "OUTPUTMODEENABLE,Selects between progressive and interlace mode for the VP output" "0,1" newline bitfld.long 0x0 21. "BT1120ENABLE,Selects BT-1120 format on the VP output. It is not possible to enable BT656 and BT1120 at the same time one the same LCD output" "0,1" newline bitfld.long 0x0 20. "BT656ENABLE,Selects BT-656 format on the VP output. It is not possible to enable BT656 and BT1120 at the same time one the same LCD output" "0,1" newline rbitfld.long 0x0 17.--19. "RESERVED2,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "BUFFERHANDSHAKE,Deprecated. Always write 0" "0,1" newline bitfld.long 0x0 15. "CPR,Deprecated. Always write 0" "0,1" newline hexmask.long.byte 0x0 9.--14. 1. "RESERVED1,Write 0's for future compatibility Reads return 0" newline bitfld.long 0x0 8. "EXTERNALSYNCEN,Deprecated. Always write 0" "0,1" newline bitfld.long 0x0 7. "VSYNCGATED,VSYNC Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 6. "HSYNCGATED,HSYNC Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 5. "PIXELCLOCKGATED,Pixel Clock Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 4. "PIXELDATAGATED,Pixel Data Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 3. "HDMIMODE,Deprecated. Always write 0" "0,1" newline bitfld.long 0x0 2. "GAMMAENABLE,Enable the gamma Shadow bit-field" "0,1" newline bitfld.long 0x0 1. "DATAENABLEGATED,DE Gated Enable Shadow bit-field" "0,1" newline bitfld.long 0x0 0. "PIXELGATED,Pixel Gated Enable. Shadow bit-field" "0,1" line.long 0x4 "DISPC_0_VP3_CONTROL,The control register configures the Display Controller module for the VP output" bitfld.long 0x4 30.--31. "SPATIALTEMPORALDITHERINGFRAMES,Spatial/Temporal dithering number of frames for the VP output Shadow bit-field" "0,1,2,3" newline rbitfld.long 0x4 27.--29. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 25.--26. "TDMUNUSEDBITS,State of unused bits [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3" newline bitfld.long 0x4 23.--24. "TDMCYCLEFORMAT,Cycle format [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3" newline bitfld.long 0x4 21.--22. "TDMPARALLELMODE,Output Interface width [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3" newline bitfld.long 0x4 20. "TDMENABLE,Enable the multiple cycle format for the VP output Shadow bit-field" "0,1" newline rbitfld.long 0x4 17.--19. "RESERVED1," "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 14.--16. "HT,Hold Time for output. Shadow bit-field. Encoded value [from 1 to 8] to specify the number of external digital clock periods to hold the data [programmed value = value minus one]" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 13. "RESERVED3," "0,1" newline bitfld.long 0x4 12. "STALLMODETYPE,The type of transfer in STALLMODE - If STALLMODE is enabled" "0,1" newline bitfld.long 0x4 11. "STALLMODE,Enable the STALLMODE on DPI output" "0,1" newline bitfld.long 0x4 8.--10. "DATALINES,Width of the data bus on VP output Shadow bit-field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "STDITHERENABLE,Spatial Temporal dithering enable for the VP output Shadow bit-field" "0,1" newline bitfld.long 0x4 6. "DPIENABLE,Enable the DPI output. wr:immediate" "0,1" newline bitfld.long 0x4 5. "GOBIT,GO Command for the VP output. It is used to synchronize the pipelines associated with the VP output wr:immediate" "0,1" newline bitfld.long 0x4 4. "M8B,Deprecated. Always write 0" "0,1" newline bitfld.long 0x4 3. "STN,Deprecated. Always write 0" "0,1" newline bitfld.long 0x4 2. "MONOCOLOR,Deprecated. Always write 0" "0,1" newline bitfld.long 0x4 1. "VPPROGLINENUMBERMODULO,Enable the modulo of the line number interrupt generation" "0,1" newline bitfld.long 0x4 0. "ENABLE,Enable the video port output. wr:immediate" "0,1" line.long 0x8 "DISPC_0_VP3_CSC_COEF0,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x8 16.--26. 1. "C01,C01 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x8 11.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x8 0.--10. 1. "C00,C00 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0xC "DISPC_0_VP3_CSC_COEF1,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0xC 27.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0xC 16.--26. 1. "C10,C10 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0xC 11.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0xC 0.--10. 1. "C02,C02 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x10 "DISPC_0_VP3_CSC_COEF2,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x10 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.word 0x10 16.--26. 1. "C12,C12 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x10 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.word 0x10 0.--10. 1. "C11,C11 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x14 "DISPC_0_VP3_DATA_CYCLE_0,The control register configures the output data format over up to 3 cycles. Shadow register" hexmask.long.byte 0x14 28.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.byte 0x14 24.--27. 1. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" newline rbitfld.long 0x14 21.--23. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 16.--20. 1. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" newline hexmask.long.byte 0x14 12.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.byte 0x14 8.--11. 1. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" newline rbitfld.long 0x14 5.--7. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--4. 1. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" line.long 0x18 "DISPC_0_VP3_DATA_CYCLE_1,The control register configures the output data format over up to 3 cycles. Shadow register" hexmask.long.byte 0x18 28.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.byte 0x18 24.--27. 1. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" newline rbitfld.long 0x18 21.--23. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 16.--20. 1. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" newline hexmask.long.byte 0x18 12.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.byte 0x18 8.--11. 1. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" newline rbitfld.long 0x18 5.--7. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--4. 1. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" line.long 0x1C "DISPC_0_VP3_DATA_CYCLE_2,The control register configures the output data format over up to 3 cycles. Shadow register" hexmask.long.byte 0x1C 28.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.byte 0x1C 24.--27. 1. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" newline rbitfld.long 0x1C 21.--23. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 16.--20. 1. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.byte 0x1C 8.--11. 1. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" newline rbitfld.long 0x1C 5.--7. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 0.--4. 1. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" rgroup.long 0x44++0x3 line.long 0x0 "DISPC_0_VP3_LINE_NUMBER,The control register indicates the panel display line number for the interrupt and the DMA request. Shadow register" hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--13. 1. "LINENUMBER,LCD panel line number programming LCD line number defines the line on which the programmable interrupt is generated and the DMA request occurs" rgroup.long 0x4C++0x43 line.long 0x0 "DISPC_0_VP3_POL_FREQ,The register configures the signal configuration. Shadow register" hexmask.long.word 0x0 19.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline bitfld.long 0x0 18. "ALIGN,Defines the alignment between HSYNC and VSYNC assertion" "0,1" newline bitfld.long 0x0 17. "ONOFF,HSYNC/VSYNC Pixel clock Control On/Off" "0,1" newline bitfld.long 0x0 16. "RF,Program HSYNC/VSYNC Rise or Fall" "0,1" newline bitfld.long 0x0 15. "IEO,Invert output enable" "0,1" newline bitfld.long 0x0 14. "IPC,Invert pixel clock" "0,1" newline bitfld.long 0x0 13. "IHS,Invert HSYNC" "0,1" newline bitfld.long 0x0 12. "IVS,Invert VSYNC" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "ACBI,AC Bias Pin transitions per interrupt Value [from 0 to 15] used to specify the number of AC Bias pin transitions" newline hexmask.long.byte 0x0 0.--7. 1. "ACB,AC Bias Pin Frequency Value [from 0 to 255] used to specify the number of line clocks to count before transitioning the AC Bias pin. This pin is used to periodically invert the polarity of the power supply to prevent DC charge build-up within the.." line.long 0x4 "DISPC_0_VP3_SIZE_SCREEN,The register configures the panel size horizontal and vertical. Shadow register. A delta value is used to indicate if the odd field has same vertical size as the even field or +/- one line." hexmask.long.word 0x4 16.--29. 1. "LPP,Lines per panel Encoded value [from 1 to 16384] to specify the number of lines per panel [program to value minus one]" newline bitfld.long 0x4 14.--15. "DELTA_LPP,Indicates the delta size value of the odd field compared to the even field" "0,1,2,3" newline hexmask.long.word 0x4 0.--13. 1. "PPL,Pixels per line Encoded value [from 1 to 16384] to specify the number of pixels contains within each line on the display [program to value minus one]. In STALL mode any value is valid In non-STALL mode only values multiple of 8 pixels are valid" line.long 0x8 "DISPC_0_VP3_TIMING_H,The register configures the timing logic for the HSYNC signal. Shadow register" hexmask.long.word 0x8 20.--31. 1. "HBP,Horizontal Back Porch Encoded value [from 1 to 4096] to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display [program to value minus one] When in BT mode and.." newline hexmask.long.word 0x8 8.--19. 1. "HFP,Horizontal front porch Encoded value [from 1 to 4096] to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted display [program to value minus one] When in BT mode and interlaced this field.." newline hexmask.long.byte 0x8 0.--7. 1. "HSW,Horizontal synchronization pulse width Encoded value [from 1 to 256] to specify the number of pixel clock periods to pulse the line clock at the end of each line display [program to value minus one] When in BT mode this field corresponds to the LSB.." line.long 0xC "DISPC_0_VP3_TIMING_V,The register configures the timing logic for the VSYNC signal. Shadow register" hexmask.long.word 0xC 20.--31. 1. "VBP,Vertical back porch Encoded value [from 0 to 4095] to specify the number of line clock periods to add to the beginning of a frame When in BT mode and interlaced this field corresponds to the vertical field blanking No 2 for Odd Field When in BT and.." newline hexmask.long.word 0xC 8.--19. 1. "VFP,Vertical front porch Encoded value [from 0 to 4095] to specify the number of line clock periods to add to the end of each frame When in BT mode and interlaced this field corresponds to the vertical field blanking No 1 for Odd Field When in BT and in.." newline hexmask.long.byte 0xC 0.--7. 1. "VSW,Vertical synchronization pulse width Encoded value [from 1 to 256] to specify the number of line clock periods to pulse the frame clock [VSYNC] pin at the end of each frame after the end of frame wait [VFP] period elapses Frame clock uses as VSYNC.." line.long 0x10 "DISPC_0_VP3_CSC_COEF3,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x10 27.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x10 16.--26. 1. "C21,C21 coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x10 11.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x10 0.--10. 1. "C20,C20 coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x14 "DISPC_0_VP3_CSC_COEF4,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.tbyte 0x14 11.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x14 0.--10. 1. "C22,C22 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x18 "DISPC_0_VP3_CSC_COEF5,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x18 19.--31. 1. "PREOFFSET2,Row-2 pre-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x18 16.--18. "RESERVED1," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x18 3.--15. 1. "PREOFFSET1,Row1 pre-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x18 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x1C "DISPC_0_VP3_CSC_COEF6,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x1C 19.--31. 1. "POSTOFFSET1,Row-1 post-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x1C 16.--18. "RESERVED1," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1C 3.--15. 1. "PREOFFSET3,Row-3 pre-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x1C 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x20 "DISPC_0_VP3_CSC_COEF7,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x20 19.--31. 1. "POSTOFFSET3,Row-3 post-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x20 16.--18. "RESERVED1," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x20 3.--15. 1. "POSTOFFSET2,Row-2 post-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x20 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x24 "DISPC_0_VP3_SAFETY_ATTRIBUTES_0,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x24 13.--31. 1. "RESERVED," newline bitfld.long 0x24 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x24 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x24 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x24 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x24 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x28 "DISPC_0_VP3_SAFETY_ATTRIBUTES_1,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x28 13.--31. 1. "RESERVED," newline bitfld.long 0x28 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x28 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x28 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x28 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x28 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x2C "DISPC_0_VP3_SAFETY_ATTRIBUTES_2,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x2C 13.--31. 1. "RESERVED," newline bitfld.long 0x2C 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x2C 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x2C 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x2C 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x2C 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x30 "DISPC_0_VP3_SAFETY_ATTRIBUTES_3,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x30 13.--31. 1. "RESERVED," newline bitfld.long 0x30 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x30 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x30 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x30 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x30 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x34 "DISPC_0_VP3_SAFETY_ATTRIBUTES_4,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x34 13.--31. 1. "RESERVED," newline bitfld.long 0x34 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x34 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x34 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x34 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x34 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x38 "DISPC_0_VP3_SAFETY_ATTRIBUTES_5,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x38 13.--31. 1. "RESERVED," newline bitfld.long 0x38 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x38 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x38 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x38 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x38 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x3C "DISPC_0_VP3_SAFETY_ATTRIBUTES_6,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x3C 13.--31. 1. "RESERVED," newline bitfld.long 0x3C 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x3C 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x3C 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x3C 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x3C 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x40 "DISPC_0_VP3_SAFETY_ATTRIBUTES_7,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x40 13.--31. 1. "RESERVED," newline bitfld.long 0x40 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x40 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x40 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x40 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x40 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" rgroup.long 0x90++0x1F line.long 0x0 "DISPC_0_VP3_SAFETY_CAPT_SIGNATURE_0,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x0 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x4 "DISPC_0_VP3_SAFETY_CAPT_SIGNATURE_1,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x4 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x8 "DISPC_0_VP3_SAFETY_CAPT_SIGNATURE_2,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x8 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0xC "DISPC_0_VP3_SAFETY_CAPT_SIGNATURE_3,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0xC 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x10 "DISPC_0_VP3_SAFETY_CAPT_SIGNATURE_4,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x10 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x14 "DISPC_0_VP3_SAFETY_CAPT_SIGNATURE_5,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x14 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x18 "DISPC_0_VP3_SAFETY_CAPT_SIGNATURE_6,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x18 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x1C "DISPC_0_VP3_SAFETY_CAPT_SIGNATURE_7,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x1C 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" rgroup.long 0xB0++0x63 line.long 0x0 "DISPC_0_VP3_SAFETY_POSITION_0,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x0 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x0 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x4 "DISPC_0_VP3_SAFETY_POSITION_1,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x4 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x4 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x8 "DISPC_0_VP3_SAFETY_POSITION_2,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x8 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x8 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0xC "DISPC_0_VP3_SAFETY_POSITION_3,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0xC 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0xC 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x10 "DISPC_0_VP3_SAFETY_POSITION_4,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x10 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x10 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x14 "DISPC_0_VP3_SAFETY_POSITION_5,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x14 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x14 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x18 "DISPC_0_VP3_SAFETY_POSITION_6,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x18 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x18 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x1C "DISPC_0_VP3_SAFETY_POSITION_7,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x1C 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x1C 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x20 "DISPC_0_VP3_SAFETY_REF_SIGNATURE_0,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x20 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x24 "DISPC_0_VP3_SAFETY_REF_SIGNATURE_1,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x24 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x28 "DISPC_0_VP3_SAFETY_REF_SIGNATURE_2,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x28 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x2C "DISPC_0_VP3_SAFETY_REF_SIGNATURE_3,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x2C 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x30 "DISPC_0_VP3_SAFETY_REF_SIGNATURE_4,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x30 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x34 "DISPC_0_VP3_SAFETY_REF_SIGNATURE_5,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x34 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x38 "DISPC_0_VP3_SAFETY_REF_SIGNATURE_6,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x38 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x3C "DISPC_0_VP3_SAFETY_REF_SIGNATURE_7,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x3C 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x40 "DISPC_0_VP3_SAFETY_SIZE_0,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x40 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x40 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x44 "DISPC_0_VP3_SAFETY_SIZE_1,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x44 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x44 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x48 "DISPC_0_VP3_SAFETY_SIZE_2,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x48 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x48 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x4C "DISPC_0_VP3_SAFETY_SIZE_3,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x4C 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x4C 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x50 "DISPC_0_VP3_SAFETY_SIZE_4,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x50 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x50 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x54 "DISPC_0_VP3_SAFETY_SIZE_5,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x54 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x54 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x58 "DISPC_0_VP3_SAFETY_SIZE_6,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x58 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x58 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x5C "DISPC_0_VP3_SAFETY_SIZE_7,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x5C 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x5C 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x60 "DISPC_0_VP3_SAFETY_LFSR_SEED,The register configures the seed initial signature value of MISRs that are to be initialized with a user programmed initial value. Otherwise. the MISR is initialized with 0xFFFF_FFFF. Shadow register." hexmask.long 0x60 0.--31. 1. "SEED,The register configures the seed [initial signature value] of MISRs that are to be initialized with a user programmed initial value Otherwise the MISR is initialized with 0xFFFF_FFFF Shadow register" rgroup.long 0x120++0x3F line.long 0x0 "DISPC_0_VP3_GAMMA_TABLE_0,The register configures the gamma table on VP output." bitfld.long 0x0 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x0 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x0 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x0 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x4 "DISPC_0_VP3_GAMMA_TABLE_1,The register configures the gamma table on VP output." bitfld.long 0x4 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x4 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x4 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x4 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x8 "DISPC_0_VP3_GAMMA_TABLE_2,The register configures the gamma table on VP output." bitfld.long 0x8 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x8 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x8 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x8 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0xC "DISPC_0_VP3_GAMMA_TABLE_3,The register configures the gamma table on VP output." bitfld.long 0xC 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0xC 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0xC 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0xC 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x10 "DISPC_0_VP3_GAMMA_TABLE_4,The register configures the gamma table on VP output." bitfld.long 0x10 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x10 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x10 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x10 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x14 "DISPC_0_VP3_GAMMA_TABLE_5,The register configures the gamma table on VP output." bitfld.long 0x14 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x14 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x14 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x14 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x18 "DISPC_0_VP3_GAMMA_TABLE_6,The register configures the gamma table on VP output." bitfld.long 0x18 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x18 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x18 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x18 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x1C "DISPC_0_VP3_GAMMA_TABLE_7,The register configures the gamma table on VP output." bitfld.long 0x1C 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x1C 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x1C 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x1C 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x20 "DISPC_0_VP3_GAMMA_TABLE_8,The register configures the gamma table on VP output." bitfld.long 0x20 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x20 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x20 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x20 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x24 "DISPC_0_VP3_GAMMA_TABLE_9,The register configures the gamma table on VP output." bitfld.long 0x24 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x24 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x24 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x24 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x28 "DISPC_0_VP3_GAMMA_TABLE_10,The register configures the gamma table on VP output." bitfld.long 0x28 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x28 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x28 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x28 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x2C "DISPC_0_VP3_GAMMA_TABLE_11,The register configures the gamma table on VP output." bitfld.long 0x2C 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x2C 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x2C 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x2C 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x30 "DISPC_0_VP3_GAMMA_TABLE_12,The register configures the gamma table on VP output." bitfld.long 0x30 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x30 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x30 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x30 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x34 "DISPC_0_VP3_GAMMA_TABLE_13,The register configures the gamma table on VP output." bitfld.long 0x34 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x34 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x34 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x34 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x38 "DISPC_0_VP3_GAMMA_TABLE_14,The register configures the gamma table on VP output." bitfld.long 0x38 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x38 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x38 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x38 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x3C "DISPC_0_VP3_GAMMA_TABLE_15,The register configures the gamma table on VP output." bitfld.long 0x3C 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x3C 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x3C 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x3C 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" rgroup.long 0x160++0xB line.long 0x0 "DISPC_0_VP3_DSS_OLDI_CFG,Reserved" line.long 0x4 "DISPC_0_VP3_DSS_OLDI_STATUS,Reserved" line.long 0x8 "DISPC_0_VP3_DSS_OLDI_LB,Reserved" rgroup.long 0x178++0x3 line.long 0x0 "DISPC_0_VP3_SECURE,Security bit settings for the sub-module" bitfld.long 0x0 0. "SECURE,Secure bit" "0,1" tree.end tree "DSS0_VP4 (DSS0_VP4)" base ad:0x4AE0000 rgroup.long 0x0++0x1F line.long 0x0 "DISPC_0_VP4_CONFIG,The control register configures the Display Controller module for the VP output. Shadow register." hexmask.long.byte 0x0 27.--31. 1. "RESERVED3," newline bitfld.long 0x0 26. "COLORCONVPOS,Determines the position of the COLORCONV module" "0,1" newline bitfld.long 0x0 25. "FULLRANGE,Color Space Conversion full range setting" "0,1" newline bitfld.long 0x0 24. "COLORCONVENABLE,Enable the color space conversion. The coefficients and offsets used are all programmable and controlled by CPR_COEFF_* and CPR_OFFSET_* registers" "0,1" newline bitfld.long 0x0 23. "FIDFIRST,Selects the first field to output in case of interlace mode. In case of progressive mode the value is not used" "0,1" newline bitfld.long 0x0 22. "OUTPUTMODEENABLE,Selects between progressive and interlace mode for the VP output" "0,1" newline bitfld.long 0x0 21. "BT1120ENABLE,Selects BT-1120 format on the VP output. It is not possible to enable BT656 and BT1120 at the same time one the same LCD output" "0,1" newline bitfld.long 0x0 20. "BT656ENABLE,Selects BT-656 format on the VP output. It is not possible to enable BT656 and BT1120 at the same time one the same LCD output" "0,1" newline rbitfld.long 0x0 17.--19. "RESERVED2,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "BUFFERHANDSHAKE,Deprecated. Always write 0" "0,1" newline bitfld.long 0x0 15. "CPR,Deprecated. Always write 0" "0,1" newline hexmask.long.byte 0x0 9.--14. 1. "RESERVED1,Write 0's for future compatibility Reads return 0" newline bitfld.long 0x0 8. "EXTERNALSYNCEN,Deprecated. Always write 0" "0,1" newline bitfld.long 0x0 7. "VSYNCGATED,VSYNC Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 6. "HSYNCGATED,HSYNC Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 5. "PIXELCLOCKGATED,Pixel Clock Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 4. "PIXELDATAGATED,Pixel Data Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 3. "HDMIMODE,Deprecated. Always write 0" "0,1" newline bitfld.long 0x0 2. "GAMMAENABLE,Enable the gamma Shadow bit-field" "0,1" newline bitfld.long 0x0 1. "DATAENABLEGATED,DE Gated Enable Shadow bit-field" "0,1" newline bitfld.long 0x0 0. "PIXELGATED,Pixel Gated Enable. Shadow bit-field" "0,1" line.long 0x4 "DISPC_0_VP4_CONTROL,The control register configures the Display Controller module for the VP output" bitfld.long 0x4 30.--31. "SPATIALTEMPORALDITHERINGFRAMES,Spatial/Temporal dithering number of frames for the VP output Shadow bit-field" "0,1,2,3" newline rbitfld.long 0x4 27.--29. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 25.--26. "TDMUNUSEDBITS,State of unused bits [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3" newline bitfld.long 0x4 23.--24. "TDMCYCLEFORMAT,Cycle format [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3" newline bitfld.long 0x4 21.--22. "TDMPARALLELMODE,Output Interface width [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3" newline bitfld.long 0x4 20. "TDMENABLE,Enable the multiple cycle format for the VP output Shadow bit-field" "0,1" newline rbitfld.long 0x4 17.--19. "RESERVED1," "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 14.--16. "HT,Hold Time for output. Shadow bit-field. Encoded value [from 1 to 8] to specify the number of external digital clock periods to hold the data [programmed value = value minus one]" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 13. "RESERVED3," "0,1" newline bitfld.long 0x4 12. "STALLMODETYPE,The type of transfer in STALLMODE - If STALLMODE is enabled" "0,1" newline bitfld.long 0x4 11. "STALLMODE,Enable the STALLMODE on DPI output" "0,1" newline bitfld.long 0x4 8.--10. "DATALINES,Width of the data bus on VP output Shadow bit-field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "STDITHERENABLE,Spatial Temporal dithering enable for the VP output Shadow bit-field" "0,1" newline bitfld.long 0x4 6. "DPIENABLE,Enable the DPI output. wr:immediate" "0,1" newline bitfld.long 0x4 5. "GOBIT,GO Command for the VP output. It is used to synchronize the pipelines associated with the VP output wr:immediate" "0,1" newline bitfld.long 0x4 4. "M8B,Deprecated. Always write 0" "0,1" newline bitfld.long 0x4 3. "STN,Deprecated. Always write 0" "0,1" newline bitfld.long 0x4 2. "MONOCOLOR,Deprecated. Always write 0" "0,1" newline bitfld.long 0x4 1. "VPPROGLINENUMBERMODULO,Enable the modulo of the line number interrupt generation" "0,1" newline bitfld.long 0x4 0. "ENABLE,Enable the video port output. wr:immediate" "0,1" line.long 0x8 "DISPC_0_VP4_CSC_COEF0,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x8 16.--26. 1. "C01,C01 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x8 11.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x8 0.--10. 1. "C00,C00 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0xC "DISPC_0_VP4_CSC_COEF1,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0xC 27.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0xC 16.--26. 1. "C10,C10 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0xC 11.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0xC 0.--10. 1. "C02,C02 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x10 "DISPC_0_VP4_CSC_COEF2,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x10 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.word 0x10 16.--26. 1. "C12,C12 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x10 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.word 0x10 0.--10. 1. "C11,C11 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x14 "DISPC_0_VP4_DATA_CYCLE_0,The control register configures the output data format over up to 3 cycles. Shadow register" hexmask.long.byte 0x14 28.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.byte 0x14 24.--27. 1. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" newline rbitfld.long 0x14 21.--23. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 16.--20. 1. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" newline hexmask.long.byte 0x14 12.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.byte 0x14 8.--11. 1. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" newline rbitfld.long 0x14 5.--7. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--4. 1. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" line.long 0x18 "DISPC_0_VP4_DATA_CYCLE_1,The control register configures the output data format over up to 3 cycles. Shadow register" hexmask.long.byte 0x18 28.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.byte 0x18 24.--27. 1. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" newline rbitfld.long 0x18 21.--23. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 16.--20. 1. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" newline hexmask.long.byte 0x18 12.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.byte 0x18 8.--11. 1. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" newline rbitfld.long 0x18 5.--7. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--4. 1. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" line.long 0x1C "DISPC_0_VP4_DATA_CYCLE_2,The control register configures the output data format over up to 3 cycles. Shadow register" hexmask.long.byte 0x1C 28.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.byte 0x1C 24.--27. 1. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" newline rbitfld.long 0x1C 21.--23. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 16.--20. 1. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.byte 0x1C 8.--11. 1. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" newline rbitfld.long 0x1C 5.--7. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 0.--4. 1. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" rgroup.long 0x44++0x3 line.long 0x0 "DISPC_0_VP4_LINE_NUMBER,The control register indicates the panel display line number for the interrupt and the DMA request. Shadow register" hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--13. 1. "LINENUMBER,LCD panel line number programming LCD line number defines the line on which the programmable interrupt is generated and the DMA request occurs" rgroup.long 0x4C++0x43 line.long 0x0 "DISPC_0_VP4_POL_FREQ,The register configures the signal configuration. Shadow register" hexmask.long.word 0x0 19.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline bitfld.long 0x0 18. "ALIGN,Defines the alignment between HSYNC and VSYNC assertion" "0,1" newline bitfld.long 0x0 17. "ONOFF,HSYNC/VSYNC Pixel clock Control On/Off" "0,1" newline bitfld.long 0x0 16. "RF,Program HSYNC/VSYNC Rise or Fall" "0,1" newline bitfld.long 0x0 15. "IEO,Invert output enable" "0,1" newline bitfld.long 0x0 14. "IPC,Invert pixel clock" "0,1" newline bitfld.long 0x0 13. "IHS,Invert HSYNC" "0,1" newline bitfld.long 0x0 12. "IVS,Invert VSYNC" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "ACBI,AC Bias Pin transitions per interrupt Value [from 0 to 15] used to specify the number of AC Bias pin transitions" newline hexmask.long.byte 0x0 0.--7. 1. "ACB,AC Bias Pin Frequency Value [from 0 to 255] used to specify the number of line clocks to count before transitioning the AC Bias pin. This pin is used to periodically invert the polarity of the power supply to prevent DC charge build-up within the.." line.long 0x4 "DISPC_0_VP4_SIZE_SCREEN,The register configures the panel size horizontal and vertical. Shadow register. A delta value is used to indicate if the odd field has same vertical size as the even field or +/- one line." hexmask.long.word 0x4 16.--29. 1. "LPP,Lines per panel Encoded value [from 1 to 16384] to specify the number of lines per panel [program to value minus one]" newline bitfld.long 0x4 14.--15. "DELTA_LPP,Indicates the delta size value of the odd field compared to the even field" "0,1,2,3" newline hexmask.long.word 0x4 0.--13. 1. "PPL,Pixels per line Encoded value [from 1 to 16384] to specify the number of pixels contains within each line on the display [program to value minus one]. In STALL mode any value is valid In non-STALL mode only values multiple of 8 pixels are valid" line.long 0x8 "DISPC_0_VP4_TIMING_H,The register configures the timing logic for the HSYNC signal. Shadow register" hexmask.long.word 0x8 20.--31. 1. "HBP,Horizontal Back Porch Encoded value [from 1 to 4096] to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display [program to value minus one] When in BT mode and.." newline hexmask.long.word 0x8 8.--19. 1. "HFP,Horizontal front porch Encoded value [from 1 to 4096] to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted display [program to value minus one] When in BT mode and interlaced this field.." newline hexmask.long.byte 0x8 0.--7. 1. "HSW,Horizontal synchronization pulse width Encoded value [from 1 to 256] to specify the number of pixel clock periods to pulse the line clock at the end of each line display [program to value minus one] When in BT mode this field corresponds to the LSB.." line.long 0xC "DISPC_0_VP4_TIMING_V,The register configures the timing logic for the VSYNC signal. Shadow register" hexmask.long.word 0xC 20.--31. 1. "VBP,Vertical back porch Encoded value [from 0 to 4095] to specify the number of line clock periods to add to the beginning of a frame When in BT mode and interlaced this field corresponds to the vertical field blanking No 2 for Odd Field When in BT and.." newline hexmask.long.word 0xC 8.--19. 1. "VFP,Vertical front porch Encoded value [from 0 to 4095] to specify the number of line clock periods to add to the end of each frame When in BT mode and interlaced this field corresponds to the vertical field blanking No 1 for Odd Field When in BT and in.." newline hexmask.long.byte 0xC 0.--7. 1. "VSW,Vertical synchronization pulse width Encoded value [from 1 to 256] to specify the number of line clock periods to pulse the frame clock [VSYNC] pin at the end of each frame after the end of frame wait [VFP] period elapses Frame clock uses as VSYNC.." line.long 0x10 "DISPC_0_VP4_CSC_COEF3,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x10 27.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x10 16.--26. 1. "C21,C21 coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x10 11.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x10 0.--10. 1. "C20,C20 coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x14 "DISPC_0_VP4_CSC_COEF4,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.tbyte 0x14 11.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x14 0.--10. 1. "C22,C22 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x18 "DISPC_0_VP4_CSC_COEF5,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x18 19.--31. 1. "PREOFFSET2,Row-2 pre-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x18 16.--18. "RESERVED1," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x18 3.--15. 1. "PREOFFSET1,Row1 pre-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x18 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x1C "DISPC_0_VP4_CSC_COEF6,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x1C 19.--31. 1. "POSTOFFSET1,Row-1 post-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x1C 16.--18. "RESERVED1," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1C 3.--15. 1. "PREOFFSET3,Row-3 pre-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x1C 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x20 "DISPC_0_VP4_CSC_COEF7,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x20 19.--31. 1. "POSTOFFSET3,Row-3 post-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x20 16.--18. "RESERVED1," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x20 3.--15. 1. "POSTOFFSET2,Row-2 post-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x20 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x24 "DISPC_0_VP4_SAFETY_ATTRIBUTES_0,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x24 13.--31. 1. "RESERVED," newline bitfld.long 0x24 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x24 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x24 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x24 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x24 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x28 "DISPC_0_VP4_SAFETY_ATTRIBUTES_1,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x28 13.--31. 1. "RESERVED," newline bitfld.long 0x28 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x28 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x28 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x28 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x28 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x2C "DISPC_0_VP4_SAFETY_ATTRIBUTES_2,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x2C 13.--31. 1. "RESERVED," newline bitfld.long 0x2C 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x2C 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x2C 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x2C 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x2C 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x30 "DISPC_0_VP4_SAFETY_ATTRIBUTES_3,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x30 13.--31. 1. "RESERVED," newline bitfld.long 0x30 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x30 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x30 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x30 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x30 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x34 "DISPC_0_VP4_SAFETY_ATTRIBUTES_4,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x34 13.--31. 1. "RESERVED," newline bitfld.long 0x34 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x34 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x34 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x34 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x34 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x38 "DISPC_0_VP4_SAFETY_ATTRIBUTES_5,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x38 13.--31. 1. "RESERVED," newline bitfld.long 0x38 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x38 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x38 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x38 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x38 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x3C "DISPC_0_VP4_SAFETY_ATTRIBUTES_6,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x3C 13.--31. 1. "RESERVED," newline bitfld.long 0x3C 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x3C 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x3C 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x3C 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x3C 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x40 "DISPC_0_VP4_SAFETY_ATTRIBUTES_7,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x40 13.--31. 1. "RESERVED," newline bitfld.long 0x40 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x40 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x40 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x40 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x40 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" rgroup.long 0x90++0x1F line.long 0x0 "DISPC_0_VP4_SAFETY_CAPT_SIGNATURE_0,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x0 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x4 "DISPC_0_VP4_SAFETY_CAPT_SIGNATURE_1,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x4 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x8 "DISPC_0_VP4_SAFETY_CAPT_SIGNATURE_2,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x8 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0xC "DISPC_0_VP4_SAFETY_CAPT_SIGNATURE_3,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0xC 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x10 "DISPC_0_VP4_SAFETY_CAPT_SIGNATURE_4,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x10 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x14 "DISPC_0_VP4_SAFETY_CAPT_SIGNATURE_5,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x14 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x18 "DISPC_0_VP4_SAFETY_CAPT_SIGNATURE_6,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x18 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x1C "DISPC_0_VP4_SAFETY_CAPT_SIGNATURE_7,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x1C 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" rgroup.long 0xB0++0x63 line.long 0x0 "DISPC_0_VP4_SAFETY_POSITION_0,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x0 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x0 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x4 "DISPC_0_VP4_SAFETY_POSITION_1,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x4 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x4 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x8 "DISPC_0_VP4_SAFETY_POSITION_2,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x8 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x8 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0xC "DISPC_0_VP4_SAFETY_POSITION_3,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0xC 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0xC 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x10 "DISPC_0_VP4_SAFETY_POSITION_4,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x10 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x10 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x14 "DISPC_0_VP4_SAFETY_POSITION_5,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x14 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x14 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x18 "DISPC_0_VP4_SAFETY_POSITION_6,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x18 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x18 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x1C "DISPC_0_VP4_SAFETY_POSITION_7,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.word 0x1C 16.--29. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.word 0x1C 0.--13. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 16383] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x20 "DISPC_0_VP4_SAFETY_REF_SIGNATURE_0,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x20 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x24 "DISPC_0_VP4_SAFETY_REF_SIGNATURE_1,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x24 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x28 "DISPC_0_VP4_SAFETY_REF_SIGNATURE_2,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x28 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x2C "DISPC_0_VP4_SAFETY_REF_SIGNATURE_3,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x2C 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x30 "DISPC_0_VP4_SAFETY_REF_SIGNATURE_4,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x30 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x34 "DISPC_0_VP4_SAFETY_REF_SIGNATURE_5,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x34 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x38 "DISPC_0_VP4_SAFETY_REF_SIGNATURE_6,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x38 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x3C "DISPC_0_VP4_SAFETY_REF_SIGNATURE_7,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x3C 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x40 "DISPC_0_VP4_SAFETY_SIZE_0,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x40 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x40 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x44 "DISPC_0_VP4_SAFETY_SIZE_1,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x44 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x44 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x48 "DISPC_0_VP4_SAFETY_SIZE_2,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x48 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x48 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x4C "DISPC_0_VP4_SAFETY_SIZE_3,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x4C 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x4C 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x50 "DISPC_0_VP4_SAFETY_SIZE_4,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x50 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x50 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x54 "DISPC_0_VP4_SAFETY_SIZE_5,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x54 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x54 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x58 "DISPC_0_VP4_SAFETY_SIZE_6,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x58 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x58 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x5C "DISPC_0_VP4_SAFETY_SIZE_7,The register configures the size of the safety sub-region n Shadow register." hexmask.long.word 0x5C 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.word 0x5C 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x60 "DISPC_0_VP4_SAFETY_LFSR_SEED,The register configures the seed initial signature value of MISRs that are to be initialized with a user programmed initial value. Otherwise. the MISR is initialized with 0xFFFF_FFFF. Shadow register." hexmask.long 0x60 0.--31. 1. "SEED,The register configures the seed [initial signature value] of MISRs that are to be initialized with a user programmed initial value Otherwise the MISR is initialized with 0xFFFF_FFFF Shadow register" rgroup.long 0x120++0x3F line.long 0x0 "DISPC_0_VP4_GAMMA_TABLE_0,The register configures the gamma table on VP output." bitfld.long 0x0 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x0 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x0 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x0 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x4 "DISPC_0_VP4_GAMMA_TABLE_1,The register configures the gamma table on VP output." bitfld.long 0x4 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x4 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x4 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x4 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x8 "DISPC_0_VP4_GAMMA_TABLE_2,The register configures the gamma table on VP output." bitfld.long 0x8 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x8 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x8 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x8 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0xC "DISPC_0_VP4_GAMMA_TABLE_3,The register configures the gamma table on VP output." bitfld.long 0xC 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0xC 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0xC 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0xC 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x10 "DISPC_0_VP4_GAMMA_TABLE_4,The register configures the gamma table on VP output." bitfld.long 0x10 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x10 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x10 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x10 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x14 "DISPC_0_VP4_GAMMA_TABLE_5,The register configures the gamma table on VP output." bitfld.long 0x14 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x14 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x14 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x14 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x18 "DISPC_0_VP4_GAMMA_TABLE_6,The register configures the gamma table on VP output." bitfld.long 0x18 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x18 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x18 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x18 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x1C "DISPC_0_VP4_GAMMA_TABLE_7,The register configures the gamma table on VP output." bitfld.long 0x1C 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x1C 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x1C 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x1C 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x20 "DISPC_0_VP4_GAMMA_TABLE_8,The register configures the gamma table on VP output." bitfld.long 0x20 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x20 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x20 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x20 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x24 "DISPC_0_VP4_GAMMA_TABLE_9,The register configures the gamma table on VP output." bitfld.long 0x24 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x24 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x24 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x24 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x28 "DISPC_0_VP4_GAMMA_TABLE_10,The register configures the gamma table on VP output." bitfld.long 0x28 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x28 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x28 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x28 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x2C "DISPC_0_VP4_GAMMA_TABLE_11,The register configures the gamma table on VP output." bitfld.long 0x2C 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x2C 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x2C 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x2C 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x30 "DISPC_0_VP4_GAMMA_TABLE_12,The register configures the gamma table on VP output." bitfld.long 0x30 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x30 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x30 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x30 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x34 "DISPC_0_VP4_GAMMA_TABLE_13,The register configures the gamma table on VP output." bitfld.long 0x34 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x34 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x34 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x34 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x38 "DISPC_0_VP4_GAMMA_TABLE_14,The register configures the gamma table on VP output." bitfld.long 0x38 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x38 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x38 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x38 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" line.long 0x3C "DISPC_0_VP4_GAMMA_TABLE_15,The register configures the gamma table on VP output." bitfld.long 0x3C 31. "INDEX,Write 1 to reset the index" "0,1" newline hexmask.long.word 0x3C 20.--29. 1. "VALUE_R,10-bit R value to be stored in the gamma table" newline hexmask.long.word 0x3C 10.--19. 1. "VALUE_G,10-bit G value to be stored in the gamma table" newline hexmask.long.word 0x3C 0.--9. 1. "VALUE_B,10-bit B value to be stored in the gamma table" rgroup.long 0x160++0xB line.long 0x0 "DISPC_0_VP4_DSS_OLDI_CFG,Reserved" line.long 0x4 "DISPC_0_VP4_DSS_OLDI_STATUS,Reserved" line.long 0x8 "DISPC_0_VP4_DSS_OLDI_LB,Reserved" rgroup.long 0x178++0x3 line.long 0x0 "DISPC_0_VP4_SECURE,Security bit settings for the sub-module" bitfld.long 0x0 0. "SECURE,Secure bit" "0,1" tree.end tree "DSS0_WB (DSS0_WB)" base ad:0x4AF0000 rgroup.long 0x0++0x37 line.long 0x0 "DISPC_0_WB_ACCUH_0,The register configures the resize accumulator init values for horizontal up/down-sampling of the write-back window. It is used for ARGB and Y setting. Shadow register" hexmask.long.tbyte 0x0 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x4 "DISPC_0_WB_ACCUH_1,The register configures the resize accumulator init values for horizontal up/down-sampling of the write-back window. It is used for ARGB and Y setting. Shadow register" hexmask.long.tbyte 0x4 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x8 "DISPC_0_WB_ACCUH2_0,The register configures the resize accumulator init value for horizontal up/down-sampling of the write-back window. It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV.." hexmask.long.tbyte 0x8 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0xC "DISPC_0_WB_ACCUH2_1,The register configures the resize accumulator init value for horizontal up/down-sampling of the write-back window. It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV.." hexmask.long.tbyte 0xC 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x10 "DISPC_0_WB_ACCUV_0,The register configures the resize accumulator init value for vertical up/down-sampling of the write-back window. It is used for ARGB and Y setting. Shadow register" hexmask.long.tbyte 0x10 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x14 "DISPC_0_WB_ACCUV_1,The register configures the resize accumulator init value for vertical up/down-sampling of the write-back window. It is used for ARGB and Y setting. Shadow register" hexmask.long.tbyte 0x14 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x18 "DISPC_0_WB_ACCUV2_0,The register configures the resize accumulator init value for vertical up/down-sampling of the write-back window. It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV.." hexmask.long.tbyte 0x18 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x1C "DISPC_0_WB_ACCUV2_1,The register configures the resize accumulator init value for vertical up/down-sampling of the write-back window. It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV.." hexmask.long.tbyte 0x1C 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x20 "DISPC_0_WB_ATTRIBUTES,The register configures the attributes of the write back pipeline. Shadow register" hexmask.long.byte 0x20 28.--31. 1. "IDLENUMBER,Determines the number of idles between requests on the L3 interconnect. It is only used when the write-back pipeline does data transfer from memory to memory. When the output of an overlay is stored in memory through the write-back pipeline in.." bitfld.long 0x20 27. "IDLESIZE,Determines if the IDLENUMBER corresponds to a number of bursts or singles" "0,1" bitfld.long 0x20 24.--26. "CAPTUREMODE,Defines the frame rate capture" "0,1,2,3,4,5,6,7" bitfld.long 0x20 23. "ARBITRATION,Determines the priority of the write-back pipeline. The write-back pipeline is one of the high priority pipelines. The arbitration gives always the priority first to the high priority pipelines using round-robin between them When there are.." "0,1" newline bitfld.long 0x20 21. "VERTICALTAPS,Video Vertical Resize Tap Number" "0,1" bitfld.long 0x20 20. "GOBIT,GO Command for the WB output. It is used to synchronize the pipelines associated with the WB output wr:immediate" "0,1" bitfld.long 0x20 19. "WRITEBACKMODE,When connected to the overlay output of a channel the write back can operate as a simple transfer from memory to memory [composition engine] or as a capture channel" "0,1" bitfld.long 0x20 12. "FULLRANGE,Color Space Conversion full range setting" "0,1" newline bitfld.long 0x20 11. "COLORCONVENABLE,Enable the color space conversion. The HW does not enable/disable the conversion based on the pixel format. The bit-field shall be reset when the format is not YUV" "0,1" bitfld.long 0x20 9. "ALPHAENABLE,Alpha enable on WB output" "0,1" bitfld.long 0x20 7.--8. "RESIZEENABLE,Resize Enable" "0,1,2,3" hexmask.long.byte 0x20 1.--6. 1. "FORMAT,Write-back Format. It defines the pixel format when storing the write-back picture into memory" newline bitfld.long 0x20 0. "ENABLE,Write-back Enable wr: immediate" "0,1" line.long 0x24 "DISPC_0_WB_ATTRIBUTES2,The register configures the attributes of the write back pipeline. Shadow register" hexmask.long.byte 0x24 26.--30. 1. "TAGS,Number of OCP TAGS to be used for the pipeline [0x0 to 0xF]. A value of '0' means a single tag will be used. A value of 'F' means all 16 tags can be used" bitfld.long 0x24 10. "YUV_ALIGN,Alignment [MSB or LSB align] for unpacked 10b/12b YUV data" "0,1" bitfld.long 0x24 9. "YUV_MODE,Mode of packing for YUV data [only for 10b/12b formats]" "0,1" bitfld.long 0x24 7.--8. "YUV_SIZE,Size of YUV data 8b/10b/12b" "0,1,2,3" line.long 0x28 "DISPC_0_WB_BA_0,The register configures the base address of the WB buffer. DISPC_WB_BA__0 & DISPC_WB_BA__1 for ping-pong mechanism with external trigger. based on the field polarity. otherwise only DISPC_WB_BA__0 is used. Shadow register" hexmask.long 0x28 0.--31. 1. "BA,Write-back base address Base address of the WB buffer [aligned on pixel size boundary except in case of RGB24 packed format where 4-pixel alignment is required. In case of YUV422 2-pixel alignment is required and YUV420 byte alignment is.." line.long 0x2C "DISPC_0_WB_BA_1,The register configures the base address of the WB buffer. DISPC_WB_BA__0 & DISPC_WB_BA__1 for ping-pong mechanism with external trigger. based on the field polarity. otherwise only DISPC_WB_BA__0 is used. Shadow register" hexmask.long 0x2C 0.--31. 1. "BA,Write-back base address Base address of the WB buffer [aligned on pixel size boundary except in case of RGB24 packed format where 4-pixel alignment is required. In case of YUV422 2-pixel alignment is required and YUV420 byte alignment is.." line.long 0x30 "DISPC_0_WB_BA_UV_0,The register configures the base address of the UV buffer for the write-back pipeline. DISPC_WB_BA_UV__0 & DISPC_WB_BA_UV__1 for ping-pong mechanism with external trigger. based on the field polarity. otherwise only DISPC_WB_BA_UV__0.." hexmask.long 0x30 0.--31. 1. "BA,WB base address aligned on 16-bit boundary. Base address of the UV WB buffer" line.long 0x34 "DISPC_0_WB_BA_UV_1,The register configures the base address of the UV buffer for the write-back pipeline. DISPC_WB_BA_UV__0 & DISPC_WB_BA_UV__1 for ping-pong mechanism with external trigger. based on the field polarity. otherwise only DISPC_WB_BA_UV__0.." hexmask.long 0x34 0.--31. 1. "BA,WB base address aligned on 16-bit boundary. Base address of the UV WB buffer" rgroup.long 0x38++0x3 line.long 0x0 "DISPC_0_WB_BUF_SIZE_STATUS,The register defines the DMA buffer size for the write back pipeline" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" hexmask.long.word 0x0 0.--15. 1. "BUFSIZE,DMA buffer Size in number of 128-bits" rgroup.long 0x3C++0x1BF line.long 0x0 "DISPC_0_WB_BUF_THRESHOLD,The register configures the DMA buffer associated with the write-back pipeline. Shadow register" hexmask.long.word 0x0 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer High Threshold Number of 128-bits defining the threshold value" hexmask.long.word 0x0 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer High Threshold Number of 128-bits defining the threshold value" line.long 0x4 "DISPC_0_WB_CSC_COEF0,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x4 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x4 16.--26. 1. "C01,C01 Coefficient. Encoded signed value [from -1024 to 1023]" hexmask.long.byte 0x4 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x4 0.--10. 1. "C00,C00 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x8 "DISPC_0_WB_CSC_COEF1,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x8 16.--26. 1. "C10,C10 Coefficient. Encoded signed value [from -1024 to 1023]" hexmask.long.byte 0x8 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x8 0.--10. 1. "C02,C02 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0xC "DISPC_0_WB_CSC_COEF2,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0xC 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0xC 16.--26. 1. "C12,C12 Coefficient. Encoded signed value [from -1024 to 1023]" hexmask.long.byte 0xC 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0xC 0.--10. 1. "C11,C11 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x10 "DISPC_0_WB_CSC_COEF3,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x10 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 16.--26. 1. "C21,C21 coefficient. Encoded signed value [from -1024 to 1023]" hexmask.long.byte 0x10 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 0.--10. 1. "C20,C20 coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x14 "DISPC_0_WB_CSC_COEF4,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.tbyte 0x14 11.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x14 0.--10. 1. "C22,C22 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x18 "DISPC_0_WB_CSC_COEF5,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x18 19.--31. 1. "PREOFFSET2,Row-2 pre-offset. Encoded signed value [from -4096 to 4095]" hexmask.long.word 0x18 3.--15. 1. "PREOFFSET1,Row1 pre-offset. Encoded signed value [from -4096 to 4095]" line.long 0x1C "DISPC_0_WB_CSC_COEF6,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x1C 19.--31. 1. "POSTOFFSET1,Row-1 post-offset. Encoded signed value [from -4096 to 4095]" hexmask.long.word 0x1C 3.--15. 1. "PREOFFSET3,Row-3 pre-offset. Encoded signed value [from -4096 to 4095]" line.long 0x20 "DISPC_0_WB_FIRH,The register configures the resize factor for horizontal up/down-sampling of the write-back window. It is used for ARGB and Y setting. Shadow register" hexmask.long.tbyte 0x20 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter. The value 0 is invalid" line.long 0x24 "DISPC_0_WB_FIRH2,The register configures the resize factor for horizontal up/down-sampling of the write-back window. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the.." hexmask.long.tbyte 0x24 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter for Cb and Cr. The value 0 is invalid" line.long 0x28 "DISPC_0_WB_FIRV,The register configures the resize factor for vertical up/down-sampling of the write-back window. It is used for ARGB and Y setting. Shadow register" hexmask.long.tbyte 0x28 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter. The value 0 is invalid" line.long 0x2C "DISPC_0_WB_FIRV2,The register configures the resize factor for vertical up/down-sampling of the write-back window. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the.." hexmask.long.tbyte 0x2C 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter for Cb and Cr. The value 0 is invalid" line.long 0x30 "DISPC_0_WB_FIR_COEF_H0_0,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x30 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x34 "DISPC_0_WB_FIR_COEF_H0_1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x34 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x38 "DISPC_0_WB_FIR_COEF_H0_2,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x38 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x3C "DISPC_0_WB_FIR_COEF_H0_3,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x3C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x40 "DISPC_0_WB_FIR_COEF_H0_4,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x40 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x44 "DISPC_0_WB_FIR_COEF_H0_5,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x44 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x48 "DISPC_0_WB_FIR_COEF_H0_6,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x48 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x4C "DISPC_0_WB_FIR_COEF_H0_7,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x4C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x50 "DISPC_0_WB_FIR_COEF_H0_8,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x50 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x54 "DISPC_0_WB_FIR_COEF_H0_C_0,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x54 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x58 "DISPC_0_WB_FIR_COEF_H0_C_1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x58 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x5C "DISPC_0_WB_FIR_COEF_H0_C_2,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x5C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x60 "DISPC_0_WB_FIR_COEF_H0_C_3,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x60 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x64 "DISPC_0_WB_FIR_COEF_H0_C_4,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x64 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x68 "DISPC_0_WB_FIR_COEF_H0_C_5,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x68 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x6C "DISPC_0_WB_FIR_COEF_H0_C_6,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x6C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x70 "DISPC_0_WB_FIR_COEF_H0_C_7,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x70 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x74 "DISPC_0_WB_FIR_COEF_H0_C_8,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x74 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x78 "DISPC_0_WB_FIR_COEF_H12_0,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x78 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x78 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0x7C "DISPC_0_WB_FIR_COEF_H12_1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x7C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x7C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0x80 "DISPC_0_WB_FIR_COEF_H12_2,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x80 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x80 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0x84 "DISPC_0_WB_FIR_COEF_H12_3,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x84 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x84 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0x88 "DISPC_0_WB_FIR_COEF_H12_4,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x88 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x88 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0x8C "DISPC_0_WB_FIR_COEF_H12_5,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x8C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x8C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0x90 "DISPC_0_WB_FIR_COEF_H12_6,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x90 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x90 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0x94 "DISPC_0_WB_FIR_COEF_H12_7,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x94 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x94 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0x98 "DISPC_0_WB_FIR_COEF_H12_8,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x98 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x98 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0x9C "DISPC_0_WB_FIR_COEF_H12_9,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x9C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x9C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0xA0 "DISPC_0_WB_FIR_COEF_H12_10,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0xA0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xA0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0xA4 "DISPC_0_WB_FIR_COEF_H12_11,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0xA4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xA4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0xA8 "DISPC_0_WB_FIR_COEF_H12_12,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0xA8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xA8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0xAC "DISPC_0_WB_FIR_COEF_H12_13,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0xAC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xAC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0xB0 "DISPC_0_WB_FIR_COEF_H12_14,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0xB0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xB0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0xB4 "DISPC_0_WB_FIR_COEF_H12_15,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0xB4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xB4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0xB8 "DISPC_0_WB_FIR_COEF_H12_C_0,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0xB8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xB8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0xBC "DISPC_0_WB_FIR_COEF_H12_C_1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0xBC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xBC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0xC0 "DISPC_0_WB_FIR_COEF_H12_C_2,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0xC0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xC0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0xC4 "DISPC_0_WB_FIR_COEF_H12_C_3,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0xC4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xC4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0xC8 "DISPC_0_WB_FIR_COEF_H12_C_4,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0xC8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xC8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0xCC "DISPC_0_WB_FIR_COEF_H12_C_5,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0xCC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xCC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0xD0 "DISPC_0_WB_FIR_COEF_H12_C_6,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0xD0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xD0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0xD4 "DISPC_0_WB_FIR_COEF_H12_C_7,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0xD4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xD4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0xD8 "DISPC_0_WB_FIR_COEF_H12_C_8,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0xD8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xD8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0xDC "DISPC_0_WB_FIR_COEF_H12_C_9,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0xDC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xDC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0xE0 "DISPC_0_WB_FIR_COEF_H12_C_10,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0xE0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xE0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0xE4 "DISPC_0_WB_FIR_COEF_H12_C_11,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0xE4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xE4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0xE8 "DISPC_0_WB_FIR_COEF_H12_C_12,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0xE8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xE8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0xEC "DISPC_0_WB_FIR_COEF_H12_C_13,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0xEC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xEC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0xF0 "DISPC_0_WB_FIR_COEF_H12_C_14,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0xF0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xF0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0xF4 "DISPC_0_WB_FIR_COEF_H12_C_15,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0xF4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xF4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" line.long 0xF8 "DISPC_0_WB_FIR_COEF_V0_0,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0xF8 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0xFC "DISPC_0_WB_FIR_COEF_V0_1,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0xFC 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x100 "DISPC_0_WB_FIR_COEF_V0_2,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x100 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x104 "DISPC_0_WB_FIR_COEF_V0_3,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x104 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x108 "DISPC_0_WB_FIR_COEF_V0_4,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x108 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x10C "DISPC_0_WB_FIR_COEF_V0_5,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x10C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x110 "DISPC_0_WB_FIR_COEF_V0_6,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x110 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x114 "DISPC_0_WB_FIR_COEF_V0_7,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x114 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x118 "DISPC_0_WB_FIR_COEF_V0_8,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x118 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x11C "DISPC_0_WB_FIR_COEF_V0_C_0,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x11C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x120 "DISPC_0_WB_FIR_COEF_V0_C_1,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x120 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x124 "DISPC_0_WB_FIR_COEF_V0_C_2,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x124 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x128 "DISPC_0_WB_FIR_COEF_V0_C_3,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x128 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x12C "DISPC_0_WB_FIR_COEF_V0_C_4,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x12C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x130 "DISPC_0_WB_FIR_COEF_V0_C_5,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x130 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x134 "DISPC_0_WB_FIR_COEF_V0_C_6,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x134 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x138 "DISPC_0_WB_FIR_COEF_V0_C_7,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x138 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x13C "DISPC_0_WB_FIR_COEF_V0_C_8,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x13C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x140 "DISPC_0_WB_FIR_COEF_V12_0,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x140 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x140 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x144 "DISPC_0_WB_FIR_COEF_V12_1,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x144 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x144 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x148 "DISPC_0_WB_FIR_COEF_V12_2,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x148 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x148 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x14C "DISPC_0_WB_FIR_COEF_V12_3,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x14C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x14C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x150 "DISPC_0_WB_FIR_COEF_V12_4,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x150 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x150 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x154 "DISPC_0_WB_FIR_COEF_V12_5,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x154 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x154 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x158 "DISPC_0_WB_FIR_COEF_V12_6,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x158 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x158 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x15C "DISPC_0_WB_FIR_COEF_V12_7,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x15C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x15C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x160 "DISPC_0_WB_FIR_COEF_V12_8,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x160 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x160 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x164 "DISPC_0_WB_FIR_COEF_V12_9,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x164 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x164 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x168 "DISPC_0_WB_FIR_COEF_V12_10,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x168 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x168 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x16C "DISPC_0_WB_FIR_COEF_V12_11,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x16C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x16C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x170 "DISPC_0_WB_FIR_COEF_V12_12,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x170 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x170 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x174 "DISPC_0_WB_FIR_COEF_V12_13,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x174 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x174 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x178 "DISPC_0_WB_FIR_COEF_V12_14,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x178 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x178 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x17C "DISPC_0_WB_FIR_COEF_V12_15,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for ARGB and Y setting. Shadow.." hexmask.long.word 0x17C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x17C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x180 "DISPC_0_WB_FIR_COEF_V12_C_0,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x180 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x180 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x184 "DISPC_0_WB_FIR_COEF_V12_C_1,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x184 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x184 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x188 "DISPC_0_WB_FIR_COEF_V12_C_2,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x188 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x188 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x18C "DISPC_0_WB_FIR_COEF_V12_C_3,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x18C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x18C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x190 "DISPC_0_WB_FIR_COEF_V12_C_4,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x190 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x190 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x194 "DISPC_0_WB_FIR_COEF_V12_C_5,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x194 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x194 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x198 "DISPC_0_WB_FIR_COEF_V12_C_6,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x198 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x198 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x19C "DISPC_0_WB_FIR_COEF_V12_C_7,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x19C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x19C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x1A0 "DISPC_0_WB_FIR_COEF_V12_C_8,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x1A0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1A0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x1A4 "DISPC_0_WB_FIR_COEF_V12_C_9,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It is.." hexmask.long.word 0x1A4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1A4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x1A8 "DISPC_0_WB_FIR_COEF_V12_C_10,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It.." hexmask.long.word 0x1A8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1A8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x1AC "DISPC_0_WB_FIR_COEF_V12_C_11,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It.." hexmask.long.word 0x1AC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1AC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x1B0 "DISPC_0_WB_FIR_COEF_V12_C_12,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It.." hexmask.long.word 0x1B0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1B0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x1B4 "DISPC_0_WB_FIR_COEF_V12_C_13,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It.." hexmask.long.word 0x1B4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1B4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x1B8 "DISPC_0_WB_FIR_COEF_V12_C_14,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It.." hexmask.long.word 0x1B8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1B8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" line.long 0x1BC "DISPC_0_WB_FIR_COEF_V12_C_15,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15. It is used for Crb and Cr setting. It.." hexmask.long.word 0x1BC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1BC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" rgroup.long 0x204++0x7 line.long 0x0 "DISPC_0_WB_MFLAG_THRESHOLD,MFLAG_THRESHOLD Register" hexmask.long.word 0x0 16.--31. 1. "HT_MFLAG,MFlag High Threshold" hexmask.long.word 0x0 0.--15. 1. "LT_MFLAG,MFlag Low Threshold" line.long 0x4 "DISPC_0_WB_PICTURE_SIZE,The register configures the size of the write-back picture associated with the write back pipeline after up/down-scaling size of the image stored in DDR memory. generated by WB pipe. Shadow register" hexmask.long.word 0x4 16.--29. 1. "MEMSIZEY,Number of lines of the wb picture in memory Encoded value [from 1 to 16384] to specify the number of lines of the picture store in memory [program to value minus one]" hexmask.long.word 0x4 0.--13. 1. "MEMSIZEX,Number of pixels of the wb picture in memory Encoded value [from 1 to 16384] to specify the number of pixels of the picture stored in memory [program to value minus one]" rgroup.long 0x210++0x7 line.long 0x0 "DISPC_0_WB_SIZE,The register configures the size of the output of overlay connected to the write-back pipeline when the overlay output is only used by the write-back pipeline. When the overlay is output on the primary LCD or secondary LCD or TV.." hexmask.long.word 0x0 16.--29. 1. "SIZEY,Number of lines of the Write-back picture Encoded value [from 1 to 16384] to specify the number of lines of the write-back picture from overlay or pipeline" hexmask.long.word 0x0 0.--13. 1. "SIZEX,Number of pixels of the Write-back picture Encoded value [from 1 to 16384] to specify the number of pixels of the write-back picture from overlay or pipeline" line.long 0x4 "DISPC_0_WB_POSITION,The register configures the start position of the window on overlay which wb will capture. Shadow register. Only applicable when WB is operating in capture_mode" hexmask.long.word 0x4 16.--29. 1. "POSY,Y position of the video window Encoded value [from 0 to 16384] to specify the Y position of the video window 1 The line at the top has the Y-position 0" hexmask.long.word 0x4 0.--13. 1. "POSX,X position of the video window Encoded value [from 0 to 16384] to specify the X position of the video window 1 The first pixel on the left of the display screen has the X-position 0" rgroup.long 0x21C++0x3 line.long 0x0 "DISPC_0_WB_CSC_COEF7,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x0 19.--31. 1. "POSTOFFSET3,Row-3 post-offset. Encoded signed value [from -4096 to 4095]" hexmask.long.word 0x0 3.--15. 1. "POSTOFFSET2,Row-2 post-offset. Encoded signed value [from -4096 to 4095]" rgroup.long 0x224++0x17 line.long 0x0 "DISPC_0_WB_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the WB window. For YUV420 formats this corresponds to the Y Buffer Shadow register." hexmask.long 0x0 0.--31. 1. "ROWINC,Number of bytes to increment at the end of the row Encoded signed value [from -2^31-1 to 2^31] to specify the number of bytes to increment at the end of the row in the video buffer The value 0 is invalid The value 1 means next pixel The value.." line.long 0x4 "DISPC_0_WB_ROW_INC_UV,The register configures the number of bytes to increment at the end of the row for the UV buffer associated with the WB window for YUV420 formats. For non-YUV420 formats this register is unused. Shadow register" hexmask.long 0x4 0.--31. 1. "ROWINC,Number of bytes to increment at the end of the row Encoded signed value [from -2^31-1 to 2^31] to specify the number of bytes to increment at the end of the row in the video buffer The value 0 is invalid The value 1 means next pixel The value.." line.long 0x8 "DISPC_0_WB_BA_EXT_0,The register configures the 16-bit base address extension. It is the base-address of the single video buffer for single plane ARGB or YUV. For the Y buffer for two plane YUV. For the Alpha buffer for two plane RGB565-A8. 0 & 1 : For.." hexmask.long.word 0x8 0.--15. 1. "BA_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0xC "DISPC_0_WB_BA_EXT_1,The register configures the 16-bit base address extension. It is the base-address of the single video buffer for single plane ARGB or YUV. For the Y buffer for two plane YUV. For the Alpha buffer for two plane RGB565-A8. 0 & 1 : For.." hexmask.long.word 0xC 0.--15. 1. "BA_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0x10 "DISPC_0_WB_BA_UV_EXT_0,The register configures the 16-bit base address extension of the UV buffer for two plane YUV or the RGB buffer for two plane RGB565-A8. 0 & 1 : For ping-pong mechanism with external trigger. based on the field polarity. Shadow.." hexmask.long.word 0x10 0.--15. 1. "BA_UV_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0x14 "DISPC_0_WB_BA_UV_EXT_1,The register configures the 16-bit base address extension of the UV buffer for two plane YUV or the RGB buffer for two plane RGB565-A8. 0 & 1 : For ping-pong mechanism with external trigger. based on the field polarity. Shadow.." hexmask.long.word 0x14 0.--15. 1. "BA_UV_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" rgroup.long 0x248++0x3 line.long 0x0 "DISPC_0_WB_SECURE,Security bit settings for the sub-module" bitfld.long 0x0 0. "SECURE,Secure bit" "0,1" tree.end tree.end tree "ECAP" base ad:0x0 tree "ECAP0_CTL_STS (ECAP0_CTL_STS)" base ad:0x3100000 rgroup.long 0x0++0x17 line.long 0x0 "CTL_STS_TSCNT," hexmask.long 0x0 0.--31. 1. "TSCNT,Active 32 bit Counter register which is used as the Capture time-base" line.long 0x4 "CTL_STS_CNTPHS," hexmask.long 0x4 0.--31. 1. "CNTPHS,Counter Phase value register that can be programmed for phase Lag/Lead. This register shadows TSCNT and is loaded into TSCNT upon either a SYNCI event or S/W force via a control bit. Used to achieve Phase control sync with respect to other ECAP.." line.long 0x8 "CTL_STS_CAP1," hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by : 1. Time-Stamp (i.e. counter value) during a Capture event 2. S/W - may be useful for test purposes / initialisation 3. APRD shadow register (i.e. CAP3) when used in APWM mode" line.long 0xC "CTL_STS_CAP2," hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by : 1. Time-Stamp (i.e. counter value) during a Capture event 2. S/W - may be useful for test purposes 3. ACMP shadow register (i.e. CAP4) when used in APWM mode" line.long 0x10 "CTL_STS_CAP3," hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register In APMW mode this is the Period Shadow (APER) register. User updates the PWM Period value via this register. In this mode CAP3 (APRD) shadows CAP1" line.long 0x14 "CTL_STS_CAP4," hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register In APMW mode this is the Compare Shadow (ACMP) register. User updates the PWM Compare value via this register. In this mode CAP4 (ACMP) shadows CAP2" rgroup.long 0x28++0xB line.long 0x0 "CTL_STS_ECCTL," hexmask.long.byte 0x0 27.--31. 1. "FILTER," bitfld.long 0x0 26. "APWMPOL,APWM output polarity select: 1'b0 Output is Active High (i.e. Compare value defines High time); 1'b1 Output is Active Low (i.e. Compare value defines Low time); Note: This is applicable only in APWM operating mode" "0,1" newline bitfld.long 0x0 25. "CAP_APWM,CAP/APWM operating mode select: 1'b0 ECAP module operates in Capture mode This mode forces the following configuration: 1- Inhibits TSCNT resets via PRD_eq event 2- Inhibits Shadow loads on CAP1 & 2 registers 3- Permits User to enable CAP1-4.." "?,1: Resets TSCNT on PRD_eq event" bitfld.long 0x0 24. "SWSYNC,Software forced Counter (TSCNT) sync'ing: 1'b0 Writing a Zero has no effect Reading will always return a zero; 1'b1 Writing a One will force a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits.." "0,1" newline bitfld.long 0x0 22.--23. "SYNCO_SEL,Sync-Out select: 2'b00 Select Sync-In event to be the Sync-Out signal (pass through); 2'b01 Select PRD_eq event to be the Sync-Out signal; 2'b10 DISABLE Sync Out Signal; 2'b11 DISABLE Sync Out Signal; Note: Selection PRD_eq is meaningful only.." "0,1,2,3" bitfld.long 0x0 21. "SYNCI_EN,Counter (TSCNT) Sync-In select mode: 1'b0 Disable Sync-In option 1'b1 Enable Counter (TSCNT) to be loaded from CNTPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.long 0x0 20. "TSCNTSTP,Counter Stop (freeze) Control: 1'b0 Counter Stopped; 1'b1 Counter Free Running" "0,1" bitfld.long 0x0 19. "REARM_RESET,One-Shot Re-arming i.e. Wait for stop Trigger: Writing a One Arms the One-Shot sequence i.e.: 1. Resets the Mod4 counter to zero 2. Un-freezes the Mod4 counter 3. Enables Capture Register Loads; Writing a zero has no effect. Reading always.." "0,1" newline bitfld.long 0x0 17.--18. "STOPVALUE,Stop value for One-Shot mode: This is the number (between 1-4) of Captures allowed to occur before the CAP(1-4) registers are frozen i.e.Capture sequence is stopped. 2'b00 Stop after Capture Event 1; 2'b01 Stop after Capture Event 2; 2'b10.." "?,1: Mod4 Counter is stopped,2: Capture Register Loads are inhibited [2] In one..,?" bitfld.long 0x0 16. "CONT_ONESHT,Continuous or Oneshot mode control: (applicable only in Capture mode) 1'b0 Operate in Continuous mode 1'b1 Operate in One-Shot mode" "0,1" newline bitfld.long 0x0 14.--15. "FREE_SOFT,Emulation Control 2'b00 TSCNT Counter stops immediately on emulation suspend; 2'b01 TSCNT Counter runs until = 0; 2'b1X TSCNT Counter is unaffected by emulation suspend (Run Free)" "0,1,2,3" hexmask.long.byte 0x0 9.--13. 1. "EVTFLTPS,Event Filter prescale select: 5'b00000 divide by 1 (i.e. no prescale by-pass the prescaler); 5'b00001 divide by 2; 5'b00010 divide by 4; 5'b00011 divide by 6; 5'b00100 divide by 8; 5'b00101 divide by 10; . . . . .; 5'b11110 divide by 60;.." newline bitfld.long 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a Capture Event: 1'b0 Disable CAP1-4 register loads at capture Event time; 1'b1 Enable CAP1-4 register loads at capture Event time" "0,1" bitfld.long 0x0 7. "CTRRST4,Counter Reset on Capture Event 4: 1'b0 Do Not reset Counter on Capture Event 4 (absolute time stamp); 1'b1 Reset Counter after Event 4 time-stamp has been captured (used in Difference mode operation)" "0,1" newline bitfld.long 0x0 6. "CAP4POL,Capture Event 4 Polarity select: 1'b0 Capture event 4 triggered on a Rising Edge (FE); 1'b1 Capture event 4 triggered on a Falling Edge (FE)" "0,1" bitfld.long 0x0 5. "CTRRST3,Counter Reset on Capture Event 3: 1'b0 Do Not reset Counter on Capture Event 3 (absolute time stamp); 1'b1 Reset Counter after Event 3 time-stamp has been captured (used in Difference mode operation)" "0,1" newline bitfld.long 0x0 4. "CAP3POL,Capture Event 3 Polarity select: 1'b0 Capture event 3 triggered on a Rising Edge (FE); 1'b1 Capture event 3 triggered on a Falling Edge (FE)" "0,1" bitfld.long 0x0 3. "CTRRST2,Counter Reset on Capture Event 2: 1'b0 Do Not reset Counter on Capture Event 2 (absolute time stamp); 1'b1 Reset Counter after Event 2 time-stamp has been captured (used in Difference mode operation)" "0,1" newline bitfld.long 0x0 2. "CAP2POL,Capture Event 2 Polarity select: 1'b0 Capture event 2 triggered on a Rising Edge (FE); 1'b1 Capture event 2 triggered on a Falling Edge (FE)" "0,1" bitfld.long 0x0 1. "CTRRST1,Counter Reset on Capture Event 1: 1'b0 Do Not reset Counter on Capture Event 1 (absolute time stamp); 1'b1 Reset Counter after Event 1 time-stamp has been captured (used in Difference mode operation)" "0,1" newline bitfld.long 0x0 0. "CAP1POL,Capture Event 1 Polarity select: 1'b0 Capture event 1 triggered on a Rising Edge (FE); 1'b1 Capture event 1 triggered on a Falling Edge (FE)" "0,1" line.long 0x4 "CTL_STS_ECINT_EN_FLG," rbitfld.long 0x4 23. "CMPEQ_FLG,Compare Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Compare register value (ACMP) Reading a 0 indicates no event occurred Note: This flag is only active in APWM mode." "0,1" rbitfld.long 0x4 22. "PRDEQ_FLG,Period Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Period register value (APER) and was reset. Reading a 0 indicates no event occurred Notes: This flag is only active in APWM mode." "0,1" newline rbitfld.long 0x4 21. "CNTOVF_FLG,Counter Overflow Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) has made the transition from 0xFFFFFFFF 0x00000000 Reading a 0 indicates no event occurred. Note: This flag is active in CAP & APWM mode." "0,1" rbitfld.long 0x4 20. "CEVT4_FLG,Capture Event 4 Status Flag: Reading a 1 on this bit indicates the fourth event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" newline rbitfld.long 0x4 19. "CEVT3_FLG,Capture Event 3 Status Flag: Reading a 1 on this bit indicates the third event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" rbitfld.long 0x4 18. "CEVT2_FLG,Capture Event 2 Status Flag: Reading a 1 on this bit indicates the second event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" newline rbitfld.long 0x4 17. "CEVT1_FLG,Capture Event 1 Status Flag: Reading a 1 on this bit indicates the first event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" rbitfld.long 0x4 16. "INT_FLG,Global Interrupt Status Flag: Reading a 1 on this bit indicates that an interrupt was generated from one of the following events. Reading a 0 indicates no interrupt generated." "0,1" newline bitfld.long 0x4 7. "CMPEQ_EN,Compare Equal Interrupt Enable: 1'b0 Disabled Compare Equal as an Interrupt source; 1'b1 Enable Compare Equal as an Interrupt source" "0,1" bitfld.long 0x4 6. "PRDEQ_EN,Period Equal Interrupt Enable: 1'b0 Disabled Period Equal as an Interrupt source; 1'b1 Enable Period Equal as an Interrupt source" "0,1" newline bitfld.long 0x4 5. "CNTOVF_EN,Counter Overflow Interrupt Enable: 1'b0 Disabled Counter Overflow as an Interrupt source; 1'b1 Enable Counter Overflow as an Interrupt source" "0,1" bitfld.long 0x4 4. "CEVT4_EN,Capture Event 4 Interrupt Enable: 1'b0 Disabled Capture Event 4 as an Interrupt source: 1'b1 Enable Capture Event 4 as an Interrupt source" "0,1" newline bitfld.long 0x4 3. "CEVT3_EN,Capture Event 3 Interrupt Enable: 1'b0 Disabled Capture Event 3 as an Interrupt source: 1'b1 Enable Capture Event 3 as an Interrupt source" "0,1" bitfld.long 0x4 2. "CEVT2_EN,Capture Event 2 Interrupt Enable: 1'b0 Disabled Capture Event 2 as an Interrupt source: 1'b1 Enable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.long 0x4 1. "CEVT1_EN,Capture Event 1 Interrupt Enable: 1'b0 Disabled Capture Event 1 as an Interrupt source: 1'b1 Enable Capture Event 1 as an Interrupt source" "0,1" line.long 0x8 "CTL_STS_ECINT_CLR_FRC," bitfld.long 0x8 23. "CMPEQ_FRC,Force Compare Equal: Writing a 1 to this bit will set the CMPEQ flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" bitfld.long 0x8 22. "PRDEQ_FRC,Force Period Equal: Writing a 1 to this bit will set the PRDEQ flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" newline bitfld.long 0x8 21. "CNTOVF_FRC,Force Counter Overflow: Writing a 1 to this bit will set the CNTOVF flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" bitfld.long 0x8 20. "CEVT4_FRC,Force Capture Event 4: Writing a 1 to this bit will set the CEVT4 flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" newline bitfld.long 0x8 19. "CEVT3_FRC,Force Capture Event 3: Writing a 1 to this bit will set the CEVT3 flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" bitfld.long 0x8 18. "CEVT2_FRC,Force Capture Event 2: Writing a 1 to this bit will set the CEVT2 flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" newline bitfld.long 0x8 17. "CEVT1_FRC,Force Capture Event 1: Writing a 1 to this bit will set the CEVT1 flag bit. Writing of 0 will be ignored. Always reads back a 0." "?,1: Writing a 1 to this bit will set the CEVT1 flag.." bitfld.long 0x8 7. "CMPEQ_CLR,Compare Equal Status Flag: Writing a 1 will clear the CMPEQ flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 6. "PRDEQ_CLR,Period Equal Status Flag: Writing a 1 will clear the PRDEQ flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" bitfld.long 0x8 5. "CNTOVF_CLR,Counter Overflow Status Flag: Writing a 1 will clear the CNTOVF flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 4. "CEVT4_CLR,Capture Event 4 Status Flag: Writing a 1 will clear the CEVT4 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" bitfld.long 0x8 3. "CEVT3_CLR,Capture Event 3 Status Flag: Writing a 1 will clear the CEVT3 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 2. "CEVT2_CLR,Capture Event 2 Status Flag: Writing a 1 will clear the CEVT2 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" bitfld.long 0x8 1. "CEVT1_CLR,Capture Event 1 Status Flag: Writing a 1 will clear the CEVT1 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 0. "INT_CLR,Global Interrupt Clear Flag: Writing a 1 will clear the INT flag and enable further interrupts to be generated if any of the event flags are set to 1. Writing a 0 will have no effect. Always reads back a 0." "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "CTL_STS_PID," bitfld.long 0x0 30.--31. "SCHEME," "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION," hexmask.long.byte 0x0 11.--15. 1. "RTL," newline bitfld.long 0x0 8.--10. "MAJOR," "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM," "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR," tree.end tree "ECAP1_CTL_STS (ECAP1_CTL_STS)" base ad:0x3110000 rgroup.long 0x0++0x17 line.long 0x0 "CTL_STS_TSCNT," hexmask.long 0x0 0.--31. 1. "TSCNT,Active 32 bit Counter register which is used as the Capture time-base" line.long 0x4 "CTL_STS_CNTPHS," hexmask.long 0x4 0.--31. 1. "CNTPHS,Counter Phase value register that can be programmed for phase Lag/Lead. This register shadows TSCNT and is loaded into TSCNT upon either a SYNCI event or S/W force via a control bit. Used to achieve Phase control sync with respect to other ECAP.." line.long 0x8 "CTL_STS_CAP1," hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by : 1. Time-Stamp (i.e. counter value) during a Capture event 2. S/W - may be useful for test purposes / initialisation 3. APRD shadow register (i.e. CAP3) when used in APWM mode" line.long 0xC "CTL_STS_CAP2," hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by : 1. Time-Stamp (i.e. counter value) during a Capture event 2. S/W - may be useful for test purposes 3. ACMP shadow register (i.e. CAP4) when used in APWM mode" line.long 0x10 "CTL_STS_CAP3," hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register In APMW mode this is the Period Shadow (APER) register. User updates the PWM Period value via this register. In this mode CAP3 (APRD) shadows CAP1" line.long 0x14 "CTL_STS_CAP4," hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register In APMW mode this is the Compare Shadow (ACMP) register. User updates the PWM Compare value via this register. In this mode CAP4 (ACMP) shadows CAP2" rgroup.long 0x28++0xB line.long 0x0 "CTL_STS_ECCTL," hexmask.long.byte 0x0 27.--31. 1. "FILTER," bitfld.long 0x0 26. "APWMPOL,APWM output polarity select: 1'b0 Output is Active High (i.e. Compare value defines High time); 1'b1 Output is Active Low (i.e. Compare value defines Low time); Note: This is applicable only in APWM operating mode" "0,1" newline bitfld.long 0x0 25. "CAP_APWM,CAP/APWM operating mode select: 1'b0 ECAP module operates in Capture mode This mode forces the following configuration: 1- Inhibits TSCNT resets via PRD_eq event 2- Inhibits Shadow loads on CAP1 & 2 registers 3- Permits User to enable CAP1-4.." "?,1: Resets TSCNT on PRD_eq event" bitfld.long 0x0 24. "SWSYNC,Software forced Counter (TSCNT) sync'ing: 1'b0 Writing a Zero has no effect Reading will always return a zero; 1'b1 Writing a One will force a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits.." "0,1" newline bitfld.long 0x0 22.--23. "SYNCO_SEL,Sync-Out select: 2'b00 Select Sync-In event to be the Sync-Out signal (pass through); 2'b01 Select PRD_eq event to be the Sync-Out signal; 2'b10 DISABLE Sync Out Signal; 2'b11 DISABLE Sync Out Signal; Note: Selection PRD_eq is meaningful only.." "0,1,2,3" bitfld.long 0x0 21. "SYNCI_EN,Counter (TSCNT) Sync-In select mode: 1'b0 Disable Sync-In option 1'b1 Enable Counter (TSCNT) to be loaded from CNTPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.long 0x0 20. "TSCNTSTP,Counter Stop (freeze) Control: 1'b0 Counter Stopped; 1'b1 Counter Free Running" "0,1" bitfld.long 0x0 19. "REARM_RESET,One-Shot Re-arming i.e. Wait for stop Trigger: Writing a One Arms the One-Shot sequence i.e.: 1. Resets the Mod4 counter to zero 2. Un-freezes the Mod4 counter 3. Enables Capture Register Loads; Writing a zero has no effect. Reading always.." "0,1" newline bitfld.long 0x0 17.--18. "STOPVALUE,Stop value for One-Shot mode: This is the number (between 1-4) of Captures allowed to occur before the CAP(1-4) registers are frozen i.e.Capture sequence is stopped. 2'b00 Stop after Capture Event 1; 2'b01 Stop after Capture Event 2; 2'b10.." "?,1: Mod4 Counter is stopped,2: Capture Register Loads are inhibited [2] In one..,?" bitfld.long 0x0 16. "CONT_ONESHT,Continuous or Oneshot mode control: (applicable only in Capture mode) 1'b0 Operate in Continuous mode 1'b1 Operate in One-Shot mode" "0,1" newline bitfld.long 0x0 14.--15. "FREE_SOFT,Emulation Control 2'b00 TSCNT Counter stops immediately on emulation suspend; 2'b01 TSCNT Counter runs until = 0; 2'b1X TSCNT Counter is unaffected by emulation suspend (Run Free)" "0,1,2,3" hexmask.long.byte 0x0 9.--13. 1. "EVTFLTPS,Event Filter prescale select: 5'b00000 divide by 1 (i.e. no prescale by-pass the prescaler); 5'b00001 divide by 2; 5'b00010 divide by 4; 5'b00011 divide by 6; 5'b00100 divide by 8; 5'b00101 divide by 10; . . . . .; 5'b11110 divide by 60;.." newline bitfld.long 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a Capture Event: 1'b0 Disable CAP1-4 register loads at capture Event time; 1'b1 Enable CAP1-4 register loads at capture Event time" "0,1" bitfld.long 0x0 7. "CTRRST4,Counter Reset on Capture Event 4: 1'b0 Do Not reset Counter on Capture Event 4 (absolute time stamp); 1'b1 Reset Counter after Event 4 time-stamp has been captured (used in Difference mode operation)" "0,1" newline bitfld.long 0x0 6. "CAP4POL,Capture Event 4 Polarity select: 1'b0 Capture event 4 triggered on a Rising Edge (FE); 1'b1 Capture event 4 triggered on a Falling Edge (FE)" "0,1" bitfld.long 0x0 5. "CTRRST3,Counter Reset on Capture Event 3: 1'b0 Do Not reset Counter on Capture Event 3 (absolute time stamp); 1'b1 Reset Counter after Event 3 time-stamp has been captured (used in Difference mode operation)" "0,1" newline bitfld.long 0x0 4. "CAP3POL,Capture Event 3 Polarity select: 1'b0 Capture event 3 triggered on a Rising Edge (FE); 1'b1 Capture event 3 triggered on a Falling Edge (FE)" "0,1" bitfld.long 0x0 3. "CTRRST2,Counter Reset on Capture Event 2: 1'b0 Do Not reset Counter on Capture Event 2 (absolute time stamp); 1'b1 Reset Counter after Event 2 time-stamp has been captured (used in Difference mode operation)" "0,1" newline bitfld.long 0x0 2. "CAP2POL,Capture Event 2 Polarity select: 1'b0 Capture event 2 triggered on a Rising Edge (FE); 1'b1 Capture event 2 triggered on a Falling Edge (FE)" "0,1" bitfld.long 0x0 1. "CTRRST1,Counter Reset on Capture Event 1: 1'b0 Do Not reset Counter on Capture Event 1 (absolute time stamp); 1'b1 Reset Counter after Event 1 time-stamp has been captured (used in Difference mode operation)" "0,1" newline bitfld.long 0x0 0. "CAP1POL,Capture Event 1 Polarity select: 1'b0 Capture event 1 triggered on a Rising Edge (FE); 1'b1 Capture event 1 triggered on a Falling Edge (FE)" "0,1" line.long 0x4 "CTL_STS_ECINT_EN_FLG," rbitfld.long 0x4 23. "CMPEQ_FLG,Compare Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Compare register value (ACMP) Reading a 0 indicates no event occurred Note: This flag is only active in APWM mode." "0,1" rbitfld.long 0x4 22. "PRDEQ_FLG,Period Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Period register value (APER) and was reset. Reading a 0 indicates no event occurred Notes: This flag is only active in APWM mode." "0,1" newline rbitfld.long 0x4 21. "CNTOVF_FLG,Counter Overflow Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) has made the transition from 0xFFFFFFFF 0x00000000 Reading a 0 indicates no event occurred. Note: This flag is active in CAP & APWM mode." "0,1" rbitfld.long 0x4 20. "CEVT4_FLG,Capture Event 4 Status Flag: Reading a 1 on this bit indicates the fourth event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" newline rbitfld.long 0x4 19. "CEVT3_FLG,Capture Event 3 Status Flag: Reading a 1 on this bit indicates the third event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" rbitfld.long 0x4 18. "CEVT2_FLG,Capture Event 2 Status Flag: Reading a 1 on this bit indicates the second event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" newline rbitfld.long 0x4 17. "CEVT1_FLG,Capture Event 1 Status Flag: Reading a 1 on this bit indicates the first event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" rbitfld.long 0x4 16. "INT_FLG,Global Interrupt Status Flag: Reading a 1 on this bit indicates that an interrupt was generated from one of the following events. Reading a 0 indicates no interrupt generated." "0,1" newline bitfld.long 0x4 7. "CMPEQ_EN,Compare Equal Interrupt Enable: 1'b0 Disabled Compare Equal as an Interrupt source; 1'b1 Enable Compare Equal as an Interrupt source" "0,1" bitfld.long 0x4 6. "PRDEQ_EN,Period Equal Interrupt Enable: 1'b0 Disabled Period Equal as an Interrupt source; 1'b1 Enable Period Equal as an Interrupt source" "0,1" newline bitfld.long 0x4 5. "CNTOVF_EN,Counter Overflow Interrupt Enable: 1'b0 Disabled Counter Overflow as an Interrupt source; 1'b1 Enable Counter Overflow as an Interrupt source" "0,1" bitfld.long 0x4 4. "CEVT4_EN,Capture Event 4 Interrupt Enable: 1'b0 Disabled Capture Event 4 as an Interrupt source: 1'b1 Enable Capture Event 4 as an Interrupt source" "0,1" newline bitfld.long 0x4 3. "CEVT3_EN,Capture Event 3 Interrupt Enable: 1'b0 Disabled Capture Event 3 as an Interrupt source: 1'b1 Enable Capture Event 3 as an Interrupt source" "0,1" bitfld.long 0x4 2. "CEVT2_EN,Capture Event 2 Interrupt Enable: 1'b0 Disabled Capture Event 2 as an Interrupt source: 1'b1 Enable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.long 0x4 1. "CEVT1_EN,Capture Event 1 Interrupt Enable: 1'b0 Disabled Capture Event 1 as an Interrupt source: 1'b1 Enable Capture Event 1 as an Interrupt source" "0,1" line.long 0x8 "CTL_STS_ECINT_CLR_FRC," bitfld.long 0x8 23. "CMPEQ_FRC,Force Compare Equal: Writing a 1 to this bit will set the CMPEQ flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" bitfld.long 0x8 22. "PRDEQ_FRC,Force Period Equal: Writing a 1 to this bit will set the PRDEQ flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" newline bitfld.long 0x8 21. "CNTOVF_FRC,Force Counter Overflow: Writing a 1 to this bit will set the CNTOVF flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" bitfld.long 0x8 20. "CEVT4_FRC,Force Capture Event 4: Writing a 1 to this bit will set the CEVT4 flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" newline bitfld.long 0x8 19. "CEVT3_FRC,Force Capture Event 3: Writing a 1 to this bit will set the CEVT3 flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" bitfld.long 0x8 18. "CEVT2_FRC,Force Capture Event 2: Writing a 1 to this bit will set the CEVT2 flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" newline bitfld.long 0x8 17. "CEVT1_FRC,Force Capture Event 1: Writing a 1 to this bit will set the CEVT1 flag bit. Writing of 0 will be ignored. Always reads back a 0." "?,1: Writing a 1 to this bit will set the CEVT1 flag.." bitfld.long 0x8 7. "CMPEQ_CLR,Compare Equal Status Flag: Writing a 1 will clear the CMPEQ flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 6. "PRDEQ_CLR,Period Equal Status Flag: Writing a 1 will clear the PRDEQ flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" bitfld.long 0x8 5. "CNTOVF_CLR,Counter Overflow Status Flag: Writing a 1 will clear the CNTOVF flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 4. "CEVT4_CLR,Capture Event 4 Status Flag: Writing a 1 will clear the CEVT4 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" bitfld.long 0x8 3. "CEVT3_CLR,Capture Event 3 Status Flag: Writing a 1 will clear the CEVT3 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 2. "CEVT2_CLR,Capture Event 2 Status Flag: Writing a 1 will clear the CEVT2 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" bitfld.long 0x8 1. "CEVT1_CLR,Capture Event 1 Status Flag: Writing a 1 will clear the CEVT1 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 0. "INT_CLR,Global Interrupt Clear Flag: Writing a 1 will clear the INT flag and enable further interrupts to be generated if any of the event flags are set to 1. Writing a 0 will have no effect. Always reads back a 0." "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "CTL_STS_PID," bitfld.long 0x0 30.--31. "SCHEME," "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION," hexmask.long.byte 0x0 11.--15. 1. "RTL," newline bitfld.long 0x0 8.--10. "MAJOR," "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM," "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR," tree.end tree "ECAP2_CTL_STS (ECAP2_CTL_STS)" base ad:0x3120000 rgroup.long 0x0++0x17 line.long 0x0 "CTL_STS_TSCNT," hexmask.long 0x0 0.--31. 1. "TSCNT,Active 32 bit Counter register which is used as the Capture time-base" line.long 0x4 "CTL_STS_CNTPHS," hexmask.long 0x4 0.--31. 1. "CNTPHS,Counter Phase value register that can be programmed for phase Lag/Lead. This register shadows TSCNT and is loaded into TSCNT upon either a SYNCI event or S/W force via a control bit. Used to achieve Phase control sync with respect to other ECAP.." line.long 0x8 "CTL_STS_CAP1," hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by : 1. Time-Stamp (i.e. counter value) during a Capture event 2. S/W - may be useful for test purposes / initialisation 3. APRD shadow register (i.e. CAP3) when used in APWM mode" line.long 0xC "CTL_STS_CAP2," hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by : 1. Time-Stamp (i.e. counter value) during a Capture event 2. S/W - may be useful for test purposes 3. ACMP shadow register (i.e. CAP4) when used in APWM mode" line.long 0x10 "CTL_STS_CAP3," hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register In APMW mode this is the Period Shadow (APER) register. User updates the PWM Period value via this register. In this mode CAP3 (APRD) shadows CAP1" line.long 0x14 "CTL_STS_CAP4," hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register In APMW mode this is the Compare Shadow (ACMP) register. User updates the PWM Compare value via this register. In this mode CAP4 (ACMP) shadows CAP2" rgroup.long 0x28++0xB line.long 0x0 "CTL_STS_ECCTL," hexmask.long.byte 0x0 27.--31. 1. "FILTER," bitfld.long 0x0 26. "APWMPOL,APWM output polarity select: 1'b0 Output is Active High (i.e. Compare value defines High time); 1'b1 Output is Active Low (i.e. Compare value defines Low time); Note: This is applicable only in APWM operating mode" "0,1" newline bitfld.long 0x0 25. "CAP_APWM,CAP/APWM operating mode select: 1'b0 ECAP module operates in Capture mode This mode forces the following configuration: 1- Inhibits TSCNT resets via PRD_eq event 2- Inhibits Shadow loads on CAP1 & 2 registers 3- Permits User to enable CAP1-4.." "?,1: Resets TSCNT on PRD_eq event" bitfld.long 0x0 24. "SWSYNC,Software forced Counter (TSCNT) sync'ing: 1'b0 Writing a Zero has no effect Reading will always return a zero; 1'b1 Writing a One will force a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits.." "0,1" newline bitfld.long 0x0 22.--23. "SYNCO_SEL,Sync-Out select: 2'b00 Select Sync-In event to be the Sync-Out signal (pass through); 2'b01 Select PRD_eq event to be the Sync-Out signal; 2'b10 DISABLE Sync Out Signal; 2'b11 DISABLE Sync Out Signal; Note: Selection PRD_eq is meaningful only.." "0,1,2,3" bitfld.long 0x0 21. "SYNCI_EN,Counter (TSCNT) Sync-In select mode: 1'b0 Disable Sync-In option 1'b1 Enable Counter (TSCNT) to be loaded from CNTPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.long 0x0 20. "TSCNTSTP,Counter Stop (freeze) Control: 1'b0 Counter Stopped; 1'b1 Counter Free Running" "0,1" bitfld.long 0x0 19. "REARM_RESET,One-Shot Re-arming i.e. Wait for stop Trigger: Writing a One Arms the One-Shot sequence i.e.: 1. Resets the Mod4 counter to zero 2. Un-freezes the Mod4 counter 3. Enables Capture Register Loads; Writing a zero has no effect. Reading always.." "0,1" newline bitfld.long 0x0 17.--18. "STOPVALUE,Stop value for One-Shot mode: This is the number (between 1-4) of Captures allowed to occur before the CAP(1-4) registers are frozen i.e.Capture sequence is stopped. 2'b00 Stop after Capture Event 1; 2'b01 Stop after Capture Event 2; 2'b10.." "?,1: Mod4 Counter is stopped,2: Capture Register Loads are inhibited [2] In one..,?" bitfld.long 0x0 16. "CONT_ONESHT,Continuous or Oneshot mode control: (applicable only in Capture mode) 1'b0 Operate in Continuous mode 1'b1 Operate in One-Shot mode" "0,1" newline bitfld.long 0x0 14.--15. "FREE_SOFT,Emulation Control 2'b00 TSCNT Counter stops immediately on emulation suspend; 2'b01 TSCNT Counter runs until = 0; 2'b1X TSCNT Counter is unaffected by emulation suspend (Run Free)" "0,1,2,3" hexmask.long.byte 0x0 9.--13. 1. "EVTFLTPS,Event Filter prescale select: 5'b00000 divide by 1 (i.e. no prescale by-pass the prescaler); 5'b00001 divide by 2; 5'b00010 divide by 4; 5'b00011 divide by 6; 5'b00100 divide by 8; 5'b00101 divide by 10; . . . . .; 5'b11110 divide by 60;.." newline bitfld.long 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a Capture Event: 1'b0 Disable CAP1-4 register loads at capture Event time; 1'b1 Enable CAP1-4 register loads at capture Event time" "0,1" bitfld.long 0x0 7. "CTRRST4,Counter Reset on Capture Event 4: 1'b0 Do Not reset Counter on Capture Event 4 (absolute time stamp); 1'b1 Reset Counter after Event 4 time-stamp has been captured (used in Difference mode operation)" "0,1" newline bitfld.long 0x0 6. "CAP4POL,Capture Event 4 Polarity select: 1'b0 Capture event 4 triggered on a Rising Edge (FE); 1'b1 Capture event 4 triggered on a Falling Edge (FE)" "0,1" bitfld.long 0x0 5. "CTRRST3,Counter Reset on Capture Event 3: 1'b0 Do Not reset Counter on Capture Event 3 (absolute time stamp); 1'b1 Reset Counter after Event 3 time-stamp has been captured (used in Difference mode operation)" "0,1" newline bitfld.long 0x0 4. "CAP3POL,Capture Event 3 Polarity select: 1'b0 Capture event 3 triggered on a Rising Edge (FE); 1'b1 Capture event 3 triggered on a Falling Edge (FE)" "0,1" bitfld.long 0x0 3. "CTRRST2,Counter Reset on Capture Event 2: 1'b0 Do Not reset Counter on Capture Event 2 (absolute time stamp); 1'b1 Reset Counter after Event 2 time-stamp has been captured (used in Difference mode operation)" "0,1" newline bitfld.long 0x0 2. "CAP2POL,Capture Event 2 Polarity select: 1'b0 Capture event 2 triggered on a Rising Edge (FE); 1'b1 Capture event 2 triggered on a Falling Edge (FE)" "0,1" bitfld.long 0x0 1. "CTRRST1,Counter Reset on Capture Event 1: 1'b0 Do Not reset Counter on Capture Event 1 (absolute time stamp); 1'b1 Reset Counter after Event 1 time-stamp has been captured (used in Difference mode operation)" "0,1" newline bitfld.long 0x0 0. "CAP1POL,Capture Event 1 Polarity select: 1'b0 Capture event 1 triggered on a Rising Edge (FE); 1'b1 Capture event 1 triggered on a Falling Edge (FE)" "0,1" line.long 0x4 "CTL_STS_ECINT_EN_FLG," rbitfld.long 0x4 23. "CMPEQ_FLG,Compare Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Compare register value (ACMP) Reading a 0 indicates no event occurred Note: This flag is only active in APWM mode." "0,1" rbitfld.long 0x4 22. "PRDEQ_FLG,Period Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Period register value (APER) and was reset. Reading a 0 indicates no event occurred Notes: This flag is only active in APWM mode." "0,1" newline rbitfld.long 0x4 21. "CNTOVF_FLG,Counter Overflow Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) has made the transition from 0xFFFFFFFF 0x00000000 Reading a 0 indicates no event occurred. Note: This flag is active in CAP & APWM mode." "0,1" rbitfld.long 0x4 20. "CEVT4_FLG,Capture Event 4 Status Flag: Reading a 1 on this bit indicates the fourth event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" newline rbitfld.long 0x4 19. "CEVT3_FLG,Capture Event 3 Status Flag: Reading a 1 on this bit indicates the third event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" rbitfld.long 0x4 18. "CEVT2_FLG,Capture Event 2 Status Flag: Reading a 1 on this bit indicates the second event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" newline rbitfld.long 0x4 17. "CEVT1_FLG,Capture Event 1 Status Flag: Reading a 1 on this bit indicates the first event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" rbitfld.long 0x4 16. "INT_FLG,Global Interrupt Status Flag: Reading a 1 on this bit indicates that an interrupt was generated from one of the following events. Reading a 0 indicates no interrupt generated." "0,1" newline bitfld.long 0x4 7. "CMPEQ_EN,Compare Equal Interrupt Enable: 1'b0 Disabled Compare Equal as an Interrupt source; 1'b1 Enable Compare Equal as an Interrupt source" "0,1" bitfld.long 0x4 6. "PRDEQ_EN,Period Equal Interrupt Enable: 1'b0 Disabled Period Equal as an Interrupt source; 1'b1 Enable Period Equal as an Interrupt source" "0,1" newline bitfld.long 0x4 5. "CNTOVF_EN,Counter Overflow Interrupt Enable: 1'b0 Disabled Counter Overflow as an Interrupt source; 1'b1 Enable Counter Overflow as an Interrupt source" "0,1" bitfld.long 0x4 4. "CEVT4_EN,Capture Event 4 Interrupt Enable: 1'b0 Disabled Capture Event 4 as an Interrupt source: 1'b1 Enable Capture Event 4 as an Interrupt source" "0,1" newline bitfld.long 0x4 3. "CEVT3_EN,Capture Event 3 Interrupt Enable: 1'b0 Disabled Capture Event 3 as an Interrupt source: 1'b1 Enable Capture Event 3 as an Interrupt source" "0,1" bitfld.long 0x4 2. "CEVT2_EN,Capture Event 2 Interrupt Enable: 1'b0 Disabled Capture Event 2 as an Interrupt source: 1'b1 Enable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.long 0x4 1. "CEVT1_EN,Capture Event 1 Interrupt Enable: 1'b0 Disabled Capture Event 1 as an Interrupt source: 1'b1 Enable Capture Event 1 as an Interrupt source" "0,1" line.long 0x8 "CTL_STS_ECINT_CLR_FRC," bitfld.long 0x8 23. "CMPEQ_FRC,Force Compare Equal: Writing a 1 to this bit will set the CMPEQ flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" bitfld.long 0x8 22. "PRDEQ_FRC,Force Period Equal: Writing a 1 to this bit will set the PRDEQ flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" newline bitfld.long 0x8 21. "CNTOVF_FRC,Force Counter Overflow: Writing a 1 to this bit will set the CNTOVF flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" bitfld.long 0x8 20. "CEVT4_FRC,Force Capture Event 4: Writing a 1 to this bit will set the CEVT4 flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" newline bitfld.long 0x8 19. "CEVT3_FRC,Force Capture Event 3: Writing a 1 to this bit will set the CEVT3 flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" bitfld.long 0x8 18. "CEVT2_FRC,Force Capture Event 2: Writing a 1 to this bit will set the CEVT2 flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" newline bitfld.long 0x8 17. "CEVT1_FRC,Force Capture Event 1: Writing a 1 to this bit will set the CEVT1 flag bit. Writing of 0 will be ignored. Always reads back a 0." "?,1: Writing a 1 to this bit will set the CEVT1 flag.." bitfld.long 0x8 7. "CMPEQ_CLR,Compare Equal Status Flag: Writing a 1 will clear the CMPEQ flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 6. "PRDEQ_CLR,Period Equal Status Flag: Writing a 1 will clear the PRDEQ flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" bitfld.long 0x8 5. "CNTOVF_CLR,Counter Overflow Status Flag: Writing a 1 will clear the CNTOVF flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 4. "CEVT4_CLR,Capture Event 4 Status Flag: Writing a 1 will clear the CEVT4 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" bitfld.long 0x8 3. "CEVT3_CLR,Capture Event 3 Status Flag: Writing a 1 will clear the CEVT3 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 2. "CEVT2_CLR,Capture Event 2 Status Flag: Writing a 1 will clear the CEVT2 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" bitfld.long 0x8 1. "CEVT1_CLR,Capture Event 1 Status Flag: Writing a 1 will clear the CEVT1 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 0. "INT_CLR,Global Interrupt Clear Flag: Writing a 1 will clear the INT flag and enable further interrupts to be generated if any of the event flags are set to 1. Writing a 0 will have no effect. Always reads back a 0." "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "CTL_STS_PID," bitfld.long 0x0 30.--31. "SCHEME," "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION," hexmask.long.byte 0x0 11.--15. 1. "RTL," newline bitfld.long 0x0 8.--10. "MAJOR," "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM," "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR," tree.end tree.end tree "ECC" base ad:0x0 tree "ECC_AGGR0_ECC_AGGR (ECC_AGGR0_ECC_AGGR)" base ad:0xC02000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 30. "IJ7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_STOG_9_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_main_infra_to_infra_cfg_vbusm_l0_stog_9_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 29. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_main_infra_cbass_main_0_j7am_main_infra_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 26. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for j7am_main_ctrl_mmr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 25. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_J7AM_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_SCRM_128B_CLK1_SCR_J7AM_PULSAR0_MEM_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "IJ7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_STOG_9_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_main_infra_to_infra_cfg_vbusm_l0_stog_9_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_OC_MSRAM00_M2M_BRIDGE_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_OC_MSRAM00_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for j7am_main_ctrl_mmr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 15. "IJ7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_STOG_9_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_main_infra_to_infra_cfg_vbusm_l0_stog_9_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 14. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_PEND,Interrupt Pending Status for j7am_main_ctrl_mmr_edc_ctrl_busecc_8_pend" "0,1" newline bitfld.long 0x4 13. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for j7am_main_ctrl_mmr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 12. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 10. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_SCRP_32B_CLK4_SCR_J7AM_MAIN_INFRA_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 9. "J7AM_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for j7am_main_pll_mmr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 8. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 7. "J7AM_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for j7am_main_pll_mmr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 6. "J7AM_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for j7am_main_pll_mmr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 5. "IJ7AM_MAIN_SEC_MMR_MAIN_0_J7AM_MAIN_SEC_MMR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_main_sec_mmr_main_0_j7am_main_sec_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 4. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7AM_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7AM_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_main_infra_cbass_main_0_j7am_main_infra_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 2. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_pulsar0_mem_cbass_0_j7am_pulsar0_mem_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 1. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7am_main_infra_cbass_main_fw_cbass_infra_cbass_dmsc_slv_p2p_bridge_infra_cbass_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 0. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_PULSAR00_M2M_BRIDGE_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_PULSAR00_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" line.long 0x8 "REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 26. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x8 25. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 24. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_PEND,Interrupt Pending Status for Ij7am_pulsar0_mem_cbass_0_j7am_pulsar0_mem_cbass_main_SYSCLK0_1_clk_edc_ctrl_cbass_int_main_SYSCLK0_1_busecc_pend" "0,1" newline bitfld.long 0x8 23. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7AM_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_PEND,Interrupt Pending Status for j7am_main_ctrl_mmr_edc_ctrl_busecc_5_pend" "0,1" newline bitfld.long 0x8 21. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_ERR_SCR_J7AM_PULSAR0_MEM_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_pulsar0_mem_cbass_0_j7am_pulsar0_mem_cbass_err_scr_j7am_pulsar0_mem_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 20. "EFUSE_PARITY_CHAIN1_BUSECC_PEND,Interrupt Pending Status for efuse_parity_chain1_busecc_pend" "0,1" newline bitfld.long 0x8 19. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 18. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for j7am_main_infra_cbass_main_fw_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x8 17. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_PEND,Interrupt Pending Status for j7am_main_ctrl_mmr_edc_ctrl_busecc_6_pend" "0,1" newline bitfld.long 0x8 16. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 15. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 14. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_J7AM_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 13. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_pulsar0_mem_cbass_0_j7am_pulsar0_mem_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 11. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_PEND,Interrupt Pending Status for j7am_main_ctrl_mmr_edc_ctrl_busecc_7_pend" "0,1" newline bitfld.long 0x8 8. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_PEND,Interrupt Pending Status for j7am_main_ctrl_mmr_edc_ctrl_busecc_9_pend" "0,1" newline bitfld.long 0x8 3. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_ERR_SCR_J7AM_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_main_infra_cbass_main_0_j7am_main_infra_cbass_err_scr_j7am_main_infra_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 2. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for j7am_main_ctrl_mmr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 0. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for j7am_main_ctrl_mmr_edc_ctrl_busecc_0_pend" "0,1" rgroup.long 0x80++0x7 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 30. "IJ7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_STOG_9_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_main_infra_to_infra_cfg_vbusm_l0_stog_9_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_main_infra_cbass_main_0_j7am_main_infra_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 26. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x0 25. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_J7AM_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_SCRM_128B_CLK1_SCR_J7AM_PULSAR0_MEM_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_STOG_9_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_main_infra_to_infra_cfg_vbusm_l0_stog_9_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_OC_MSRAM00_M2M_BRIDGE_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_OC_MSRAM00_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x0 15. "IJ7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_STOG_9_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_main_infra_to_infra_cfg_vbusm_l0_stog_9_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 14. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_ENABLE_SET,Interrupt Enable Set Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_8_pend" "0,1" newline bitfld.long 0x0 13. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x0 12. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 10. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_SCRP_32B_CLK4_SCR_J7AM_MAIN_INFRA_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 9. "J7AM_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for j7am_main_pll_mmr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x0 8. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 7. "J7AM_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for j7am_main_pll_mmr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x0 6. "J7AM_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for j7am_main_pll_mmr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x0 5. "IJ7AM_MAIN_SEC_MMR_MAIN_0_J7AM_MAIN_SEC_MMR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_main_sec_mmr_main_0_j7am_main_sec_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7AM_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7AM_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 3. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_main_infra_cbass_main_0_j7am_main_infra_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_pulsar0_mem_cbass_0_j7am_pulsar0_mem_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 1. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_main_infra_cbass_main_fw_cbass_infra_cbass_dmsc_slv_p2p_bridge_infra_cbass_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 0. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_PULSAR00_M2M_BRIDGE_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_PULSAR00_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" line.long 0x4 "REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 26. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x4 25. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 23. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7AM_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_ENABLE_SET,Interrupt Enable Set Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_5_pend" "0,1" newline bitfld.long 0x4 21. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_ERR_SCR_J7AM_PULSAR0_MEM_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "EFUSE_PARITY_CHAIN1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for efuse_parity_chain1_busecc_pend" "0,1" newline bitfld.long 0x4 19. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 18. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_main_infra_cbass_main_fw_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x4 17. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_ENABLE_SET,Interrupt Enable Set Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_6_pend" "0,1" newline bitfld.long 0x4 16. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 15. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 14. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_J7AM_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 13. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_pulsar0_mem_cbass_0_j7am_pulsar0_mem_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 11. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_ENABLE_SET,Interrupt Enable Set Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_7_pend" "0,1" newline bitfld.long 0x4 8. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_ENABLE_SET,Interrupt Enable Set Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_9_pend" "0,1" newline bitfld.long 0x4 3. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_ERR_SCR_J7AM_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 0. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_0_pend" "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 30. "IJ7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_STOG_9_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_main_infra_to_infra_cfg_vbusm_l0_stog_9_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_main_infra_cbass_main_0_j7am_main_infra_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 26. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x0 25. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_J7AM_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_SCRM_128B_CLK1_SCR_J7AM_PULSAR0_MEM_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_STOG_9_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_main_infra_to_infra_cfg_vbusm_l0_stog_9_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_OC_MSRAM00_M2M_BRIDGE_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_OC_MSRAM00_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x0 15. "IJ7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_STOG_9_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_main_infra_to_infra_cfg_vbusm_l0_stog_9_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 14. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_8_pend" "0,1" newline bitfld.long 0x0 13. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x0 12. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 10. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_SCRP_32B_CLK4_SCR_J7AM_MAIN_INFRA_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 9. "J7AM_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_pll_mmr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x0 8. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 7. "J7AM_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_pll_mmr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x0 6. "J7AM_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_pll_mmr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x0 5. "IJ7AM_MAIN_SEC_MMR_MAIN_0_J7AM_MAIN_SEC_MMR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_main_sec_mmr_main_0_j7am_main_sec_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7AM_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7AM_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 3. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_main_infra_cbass_main_0_j7am_main_infra_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_pulsar0_mem_cbass_0_j7am_pulsar0_mem_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 1. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 0. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_PULSAR00_M2M_BRIDGE_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_PULSAR00_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" line.long 0x4 "REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 26. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x4 25. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 23. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7AM_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_5_pend" "0,1" newline bitfld.long 0x4 21. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_ERR_SCR_J7AM_PULSAR0_MEM_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "EFUSE_PARITY_CHAIN1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for efuse_parity_chain1_busecc_pend" "0,1" newline bitfld.long 0x4 19. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 18. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_infra_cbass_main_fw_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x4 17. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_6_pend" "0,1" newline bitfld.long 0x4 16. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 15. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 14. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_J7AM_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 13. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_pulsar0_mem_cbass_0_j7am_pulsar0_mem_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 11. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_7_pend" "0,1" newline bitfld.long 0x4 8. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_9_pend" "0,1" newline bitfld.long 0x4 3. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_ERR_SCR_J7AM_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 0. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_0_pend" "0,1" rgroup.long 0x13C++0xB line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 30. "IJ7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_STOG_9_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_main_infra_to_infra_cfg_vbusm_l0_stog_9_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 29. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_main_infra_cbass_main_0_j7am_main_infra_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 26. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for j7am_main_ctrl_mmr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 25. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_J7AM_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_SCRM_128B_CLK1_SCR_J7AM_PULSAR0_MEM_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "IJ7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_STOG_9_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_main_infra_to_infra_cfg_vbusm_l0_stog_9_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_OC_MSRAM00_M2M_BRIDGE_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_OC_MSRAM00_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for j7am_main_ctrl_mmr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 15. "IJ7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_STOG_9_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_main_infra_to_infra_cfg_vbusm_l0_stog_9_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 14. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_PEND,Interrupt Pending Status for j7am_main_ctrl_mmr_edc_ctrl_busecc_8_pend" "0,1" newline bitfld.long 0x4 13. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for j7am_main_ctrl_mmr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 12. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 10. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_SCRP_32B_CLK4_SCR_J7AM_MAIN_INFRA_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 9. "J7AM_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for j7am_main_pll_mmr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 8. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 7. "J7AM_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for j7am_main_pll_mmr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 6. "J7AM_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for j7am_main_pll_mmr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 5. "IJ7AM_MAIN_SEC_MMR_MAIN_0_J7AM_MAIN_SEC_MMR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_main_sec_mmr_main_0_j7am_main_sec_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 4. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7AM_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7AM_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_main_infra_cbass_main_0_j7am_main_infra_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 2. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_pulsar0_mem_cbass_0_j7am_pulsar0_mem_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 1. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7am_main_infra_cbass_main_fw_cbass_infra_cbass_dmsc_slv_p2p_bridge_infra_cbass_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 0. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_PULSAR00_M2M_BRIDGE_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_PULSAR00_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" line.long 0x8 "REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 26. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x8 25. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 24. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_PEND,Interrupt Pending Status for Ij7am_pulsar0_mem_cbass_0_j7am_pulsar0_mem_cbass_main_SYSCLK0_1_clk_edc_ctrl_cbass_int_main_SYSCLK0_1_busecc_pend" "0,1" newline bitfld.long 0x8 23. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7AM_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_PEND,Interrupt Pending Status for j7am_main_ctrl_mmr_edc_ctrl_busecc_5_pend" "0,1" newline bitfld.long 0x8 21. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_ERR_SCR_J7AM_PULSAR0_MEM_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_pulsar0_mem_cbass_0_j7am_pulsar0_mem_cbass_err_scr_j7am_pulsar0_mem_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 20. "EFUSE_PARITY_CHAIN1_BUSECC_PEND,Interrupt Pending Status for efuse_parity_chain1_busecc_pend" "0,1" newline bitfld.long 0x8 19. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 18. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for j7am_main_infra_cbass_main_fw_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x8 17. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_PEND,Interrupt Pending Status for j7am_main_ctrl_mmr_edc_ctrl_busecc_6_pend" "0,1" newline bitfld.long 0x8 16. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 15. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 14. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_J7AM_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 13. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_pulsar0_mem_cbass_0_j7am_pulsar0_mem_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 11. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_PEND,Interrupt Pending Status for j7am_main_ctrl_mmr_edc_ctrl_busecc_7_pend" "0,1" newline bitfld.long 0x8 8. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_PEND,Interrupt Pending Status for j7am_main_ctrl_mmr_edc_ctrl_busecc_9_pend" "0,1" newline bitfld.long 0x8 3. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_ERR_SCR_J7AM_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_main_infra_cbass_main_0_j7am_main_infra_cbass_err_scr_j7am_main_infra_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 2. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for j7am_main_ctrl_mmr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 0. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for j7am_main_ctrl_mmr_edc_ctrl_busecc_0_pend" "0,1" rgroup.long 0x180++0x7 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 30. "IJ7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_STOG_9_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_main_infra_to_infra_cfg_vbusm_l0_stog_9_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_main_infra_cbass_main_0_j7am_main_infra_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 26. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x0 25. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_J7AM_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_SCRM_128B_CLK1_SCR_J7AM_PULSAR0_MEM_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_STOG_9_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_main_infra_to_infra_cfg_vbusm_l0_stog_9_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_OC_MSRAM00_M2M_BRIDGE_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_OC_MSRAM00_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x0 15. "IJ7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_STOG_9_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_main_infra_to_infra_cfg_vbusm_l0_stog_9_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 14. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_ENABLE_SET,Interrupt Enable Set Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_8_pend" "0,1" newline bitfld.long 0x0 13. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x0 12. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 10. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_SCRP_32B_CLK4_SCR_J7AM_MAIN_INFRA_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 9. "J7AM_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for j7am_main_pll_mmr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x0 8. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 7. "J7AM_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for j7am_main_pll_mmr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x0 6. "J7AM_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for j7am_main_pll_mmr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x0 5. "IJ7AM_MAIN_SEC_MMR_MAIN_0_J7AM_MAIN_SEC_MMR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_main_sec_mmr_main_0_j7am_main_sec_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7AM_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7AM_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 3. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_main_infra_cbass_main_0_j7am_main_infra_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_pulsar0_mem_cbass_0_j7am_pulsar0_mem_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 1. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_main_infra_cbass_main_fw_cbass_infra_cbass_dmsc_slv_p2p_bridge_infra_cbass_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 0. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_PULSAR00_M2M_BRIDGE_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_PULSAR00_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" line.long 0x4 "REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 26. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x4 25. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 23. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7AM_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_ENABLE_SET,Interrupt Enable Set Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_5_pend" "0,1" newline bitfld.long 0x4 21. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_ERR_SCR_J7AM_PULSAR0_MEM_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "EFUSE_PARITY_CHAIN1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for efuse_parity_chain1_busecc_pend" "0,1" newline bitfld.long 0x4 19. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 18. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_main_infra_cbass_main_fw_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x4 17. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_ENABLE_SET,Interrupt Enable Set Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_6_pend" "0,1" newline bitfld.long 0x4 16. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 15. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 14. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_J7AM_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 13. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_pulsar0_mem_cbass_0_j7am_pulsar0_mem_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 11. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_ENABLE_SET,Interrupt Enable Set Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_7_pend" "0,1" newline bitfld.long 0x4 8. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_ENABLE_SET,Interrupt Enable Set Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_9_pend" "0,1" newline bitfld.long 0x4 3. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_ERR_SCR_J7AM_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 0. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_0_pend" "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 30. "IJ7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_STOG_9_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_main_infra_to_infra_cfg_vbusm_l0_stog_9_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_main_infra_cbass_main_0_j7am_main_infra_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 26. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x0 25. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_J7AM_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_SCRM_128B_CLK1_SCR_J7AM_PULSAR0_MEM_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_STOG_9_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_main_infra_to_infra_cfg_vbusm_l0_stog_9_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_OC_MSRAM00_M2M_BRIDGE_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_OC_MSRAM00_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x0 15. "IJ7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_STOG_9_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_main_infra_to_infra_cfg_vbusm_l0_stog_9_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 14. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_8_pend" "0,1" newline bitfld.long 0x0 13. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x0 12. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 10. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_SCRP_32B_CLK4_SCR_J7AM_MAIN_INFRA_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 9. "J7AM_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_pll_mmr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x0 8. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7AM_MAIN_INFRA_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 7. "J7AM_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_pll_mmr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x0 6. "J7AM_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_pll_mmr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x0 5. "IJ7AM_MAIN_SEC_MMR_MAIN_0_J7AM_MAIN_SEC_MMR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_main_sec_mmr_main_0_j7am_main_sec_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7AM_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7AM_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 3. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_main_infra_cbass_main_0_j7am_main_infra_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_pulsar0_mem_cbass_0_j7am_pulsar0_mem_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 1. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 0. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_PULSAR00_M2M_BRIDGE_J7AM_PULSAR0_MEM_CBASS_INAVSS512J7AM_MAIN_0_PULSAR00_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" line.long 0x4 "REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 26. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x4 25. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_MAIN_INFRA_TO_INFRA_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 23. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7AM_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_5_pend" "0,1" newline bitfld.long 0x4 21. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_ERR_SCR_J7AM_PULSAR0_MEM_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "EFUSE_PARITY_CHAIN1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for efuse_parity_chain1_busecc_pend" "0,1" newline bitfld.long 0x4 19. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7AM_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 18. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_infra_cbass_main_fw_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x4 17. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_6_pend" "0,1" newline bitfld.long 0x4 16. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 15. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 14. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_J7AM_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 13. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_pulsar0_mem_cbass_0_j7am_pulsar0_mem_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 11. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_7_pend" "0,1" newline bitfld.long 0x4 8. "IJ7AM_PULSAR0_MEM_CBASS_0_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_J7AM_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "J7AM_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7AM_MAIN_INFRA_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_9_pend" "0,1" newline bitfld.long 0x4 3. "IJ7AM_MAIN_INFRA_CBASS_MAIN_0_J7AM_MAIN_INFRA_CBASS_ERR_SCR_J7AM_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "J7AM_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 0. "J7AM_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_ctrl_mmr_edc_ctrl_busecc_0_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "ECC_AGGR4_ECC_AGGR (ECC_AGGR4_ECC_AGGR)" base ad:0x2AF4000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x13 line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_CBASS_DEFAULT_MMRS_J7AM_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_cbass_default_mmrs_j7am_rc_cbass_cbass_default_mmrs_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 30. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_ERR_SCR_J7AM_PULSAR0_SLV_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_pulsar0_slv_cbass_0_j7am_pulsar0_slv_cbass_err_scr_j7am_pulsar0_slv_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 26. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_scrm_128b_clk1_scr_j7am_rc_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 25. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_P2M_BRIDGE_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_CFG_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_CFG_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_PEND,Interrupt Pending Status for Ij7am_pulsar0_slv_cbass_0_j7am_pulsar0_slv_cbass_main_SYSCLK0_2_clk_edc_ctrl_cbass_int_main_SYSCLK0_2_busecc_pend" "0,1" newline bitfld.long 0x4 19. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_J7AM_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "IJ7AM_RC_CFG_CBASS_J7AM_RC_CFG_CBASS_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_PEND,Interrupt Pending Status for Imcu_cor_fw_vbusp_32b_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 10. "IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_PEND,Interrupt Pending Status for Imcu_cor_fw_vbusp_32b_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 9. "IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_PEND,Interrupt Pending Status for Imcu_cor_data_vbusm_64b_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 8. "ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_PEND,Interrupt Pending Status for Icor_mcu_data_vbusm_64b_src_vbuss_pend" "0,1" newline bitfld.long 0x4 7. "IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_PEND,Interrupt Pending Status for Iwku_cor_data_vbusp_32b_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 6. "IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_PEND,Interrupt Pending Status for Iwku_cor_data_vbusp_32b_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 5. "IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_PEND,Interrupt Pending Status for Iwku_cor_data_vbusp_32b_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 4. "IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_PEND,Interrupt Pending Status for Imcu_cor_infra_vbusp_32b_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 3. "IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_PEND,Interrupt Pending Status for Imcu_cor_infra_vbusp_32b_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 2. "IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_PEND,Interrupt Pending Status for Imcu_cor_infra_vbusp_32b_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IMCU_COR_FW_VBUSP_32B_DST_M2P_BUSECC_PEND,Interrupt Pending Status for Imcu_cor_fw_vbusp_32b_dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x4 0. "IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_PEND,Interrupt Pending Status for Imcu_cor_data_vbusm_64b_m2m_vbuss_pend" "0,1" line.long 0x8 "REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 31. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST1_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 30. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_CFG_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_CFG_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 29. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_J7AM_TO_J7AM_RC_FW_CBASS_P2P_BRIDGE_J7AM_TO_J7AM_RC_FW_CBASS_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 28. "IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_MTOG_EDC_CTRL_PEND,Interrupt Pending Status for Iemmcsd4ss_main_0_emmcsdss_wr_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 27. "IJ7AM_RC_TO_RC_CFG_VBUSM_L0_STOG_6_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_rc_to_rc_cfg_vbusm_l0_stog_6_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 26. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_pulsar0_slv_cbass_0_j7am_pulsar0_slv_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 25. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 24. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 23. "IJ7AM_RC_CFG_CBASS_J7AM_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for Ij7am_rc_cfg_cbass_j7am_rc_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x8 22. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 21. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_scrm_64b_clk2_scr_j7am_rc_cbass_scrm_64b_clk2_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 19. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_rc_cbass_main_fw_cbass_rc_cbass_dmsc_slv_p2p_bridge_rc_cbass_dmsc_slv_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x8 18. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_pulsar0_slv_cbass_0_j7am_pulsar0_slv_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 17. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ERR_SCR_J7AM_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_err_scr_j7am_rc_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 16. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST0_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x8 14. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 13. "ICOMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_WR_VBUSM_MTOG_EDC_CTRL_PEND,Interrupt Pending Status for Icompute_cluster_j7ahp_main_0_gic_mem_wr_vbusm_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 12. "IJ7AM_RC_TO_RC_CFG_VBUSM_L0_STOG_6_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_rc_to_rc_cfg_vbusm_l0_stog_6_wr_ramecc_pend" "0,1" newline bitfld.long 0x8 11. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_scrm_128b_clk1_scr_j7am_rc_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 7. "ICOMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_RD_VBUSM_MTOG_EDC_CTRL_PEND,Interrupt Pending Status for Icompute_cluster_j7ahp_main_0_gic_mem_rd_vbusm_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 6. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_2_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_2_CPU1_CFG_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_CBASS_INT_DMSC_SCR_J7AM_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_cbass_int_dmsc_scr_j7am_rc_cbass_cbass_int_dmsc_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 1. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM0_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IIDOM0_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" line.long 0xC "REGS_sec_status_reg2,Interrupt Status Register 2" bitfld.long 0xC 31. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM1_ECC_AGGR_MAIN_RC_R5_2_1_CFG_P2P_BRIDGE_IIDOM1_ECC_AGGR_MAIN_RC_R5_2_1_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 30. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 29. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 28. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 27. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 26. "IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_MTOG_EDC_CTRL_PEND,Interrupt Pending Status for Iemmcsd4ss_main_0_emmcsdss_rd_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0xC 25. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 24. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0xC 23. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 22. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 21. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM0_ECC_AGGR_MAIN_RC_R5_2_0_CFG_P2P_BRIDGE_IIDOM0_ECC_AGGR_MAIN_RC_R5_2_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 20. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_1_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_1_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 19. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 18. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 17. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 16. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 14. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 13. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 12. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 11. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 10. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 9. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM1_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IIDOM1_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 8. "IJ7AM_RC_TO_RC_CFG_VBUSM_L0_STOG_6_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_rc_to_rc_cfg_vbusm_l0_stog_6_rd_ramecc_pend" "0,1" newline bitfld.long 0xC 7. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM0_ECC_AGGR_MAIN_RC_R5_1_0_CFG_P2P_BRIDGE_IIDOM0_ECC_AGGR_MAIN_RC_R5_1_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 6. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRP_32B_CLK4_CFG_SCR_J7AM_RC_CBASS_SCRP_32B_CLK4_CFG_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_scrp_32b_clk4_cfg_scr_j7am_rc_cbass_scrp_32b_clk4_cfg_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 5. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_CBASS_DEFAULT_ERR_J7AM_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_cbass_default_err_j7am_rc_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 4. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 3. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_rc_cbass_main_fw_cbass_rc_cbass_dmsc_slv_p2p_bridge_rc_cbass_dmsc_slv_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0xC 2. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 1. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_scrm_64b_clk2_scr_j7am_rc_cbass_scrm_64b_clk2_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0xC 0. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM1_ECC_AGGR_MAIN_RC_R5_0_1_CFG_P2P_BRIDGE_IIDOM1_ECC_AGGR_MAIN_RC_R5_0_1_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" line.long 0x10 "REGS_sec_status_reg3,Interrupt Status Register 3" bitfld.long 0x10 16. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x10 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ICOMPUTE_CLUSTER_J7AHP_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7AHP_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 14. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 13. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 12. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_J7AM_PULSAR0_SLV_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 11. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 10. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 9. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 8. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 7. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 6. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 5. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 4. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_rc_cbass_main_fw_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x10 3. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_2_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_2_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 2. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 1. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 0. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_main_SYSCLK0_2_clk_edc_ctrl_cbass_int_main_SYSCLK0_2_busecc_pend" "0,1" rgroup.long 0x80++0xF line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_CBASS_DEFAULT_MMRS_J7AM_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_cbass_default_mmrs_j7am_rc_cbass_cbass_default_mmrs_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 30. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_ERR_SCR_J7AM_PULSAR0_SLV_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_scrm_128b_clk1_scr_j7am_rc_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x0 25. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_P2M_BRIDGE_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_CFG_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_CFG_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_J7AM_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "IJ7AM_RC_CFG_CBASS_J7AM_RC_CFG_CBASS_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 13. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_fw_vbusp_32b_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 10. "IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_fw_vbusp_32b_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 9. "IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_data_vbusm_64b_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 8. "ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Icor_mcu_data_vbusm_64b_src_vbuss_pend" "0,1" newline bitfld.long 0x0 7. "IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Iwku_cor_data_vbusp_32b_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 6. "IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Iwku_cor_data_vbusp_32b_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 5. "IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Iwku_cor_data_vbusp_32b_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_infra_vbusp_32b_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 3. "IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_infra_vbusp_32b_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 2. "IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_infra_vbusp_32b_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IMCU_COR_FW_VBUSP_32B_DST_M2P_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_fw_vbusp_32b_dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 0. "IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_data_vbusm_64b_m2m_vbuss_pend" "0,1" line.long 0x4 "REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 31. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST1_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 30. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_CFG_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_CFG_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 29. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_J7AM_TO_J7AM_RC_FW_CBASS_P2P_BRIDGE_J7AM_TO_J7AM_RC_FW_CBASS_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 28. "IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_MTOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Iemmcsd4ss_main_0_emmcsdss_wr_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 27. "IJ7AM_RC_TO_RC_CFG_VBUSM_L0_STOG_6_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_to_rc_cfg_vbusm_l0_stog_6_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 26. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_pulsar0_slv_cbass_0_j7am_pulsar0_slv_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 25. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 23. "IJ7AM_RC_CFG_CBASS_J7AM_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cfg_cbass_j7am_rc_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x4 22. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 21. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_scrm_64b_clk2_scr_j7am_rc_cbass_scrm_64b_clk2_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 19. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 18. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_pulsar0_slv_cbass_0_j7am_pulsar0_slv_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 17. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ERR_SCR_J7AM_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_err_scr_j7am_rc_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 16. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST0_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x4 14. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 13. "ICOMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_WR_VBUSM_MTOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Icompute_cluster_j7ahp_main_0_gic_mem_wr_vbusm_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 12. "IJ7AM_RC_TO_RC_CFG_VBUSM_L0_STOG_6_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_to_rc_cfg_vbusm_l0_stog_6_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_scrm_128b_clk1_scr_j7am_rc_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 7. "ICOMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_RD_VBUSM_MTOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Icompute_cluster_j7ahp_main_0_gic_mem_rd_vbusm_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 6. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_2_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_2_CPU1_CFG_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_CBASS_INT_DMSC_SCR_J7AM_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_cbass_int_dmsc_scr_j7am_rc_cbass_cbass_int_dmsc_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM0_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IIDOM0_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" line.long 0x8 "REGS_sec_enable_set_reg2,Interrupt Enable Set Register 2" bitfld.long 0x8 31. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM1_ECC_AGGR_MAIN_RC_R5_2_1_CFG_P2P_BRIDGE_IIDOM1_ECC_AGGR_MAIN_RC_R5_2_1_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 30. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 29. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 28. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 27. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 26. "IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_MTOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Iemmcsd4ss_main_0_emmcsdss_rd_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 25. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 24. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 23. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 22. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 21. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM0_ECC_AGGR_MAIN_RC_R5_2_0_CFG_P2P_BRIDGE_IIDOM0_ECC_AGGR_MAIN_RC_R5_2_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 20. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_1_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_1_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 19. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 18. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 17. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 16. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 14. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 13. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 12. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 11. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 10. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 9. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM1_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IIDOM1_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 8. "IJ7AM_RC_TO_RC_CFG_VBUSM_L0_STOG_6_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_to_rc_cfg_vbusm_l0_stog_6_rd_ramecc_pend" "0,1" newline bitfld.long 0x8 7. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM0_ECC_AGGR_MAIN_RC_R5_1_0_CFG_P2P_BRIDGE_IIDOM0_ECC_AGGR_MAIN_RC_R5_1_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 6. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRP_32B_CLK4_CFG_SCR_J7AM_RC_CBASS_SCRP_32B_CLK4_CFG_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_scrp_32b_clk4_cfg_scr_j7am_rc_cbass_scrp_32b_clk4_cfg_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 5. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_CBASS_DEFAULT_ERR_J7AM_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_cbass_default_err_j7am_rc_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 4. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 3. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 2. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 1. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_scrm_64b_clk2_scr_j7am_rc_cbass_scrm_64b_clk2_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 0. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM1_ECC_AGGR_MAIN_RC_R5_0_1_CFG_P2P_BRIDGE_IIDOM1_ECC_AGGR_MAIN_RC_R5_0_1_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" line.long 0xC "REGS_sec_enable_set_reg3,Interrupt Enable Set Register 3" bitfld.long 0xC 16. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0xC 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ICOMPUTE_CLUSTER_J7AHP_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7AHP_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 14. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 13. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 12. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_J7AM_PULSAR0_SLV_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 11. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 10. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 9. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 8. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 7. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 6. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 5. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 4. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_rc_cbass_main_fw_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0xC 3. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_2_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_2_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 2. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 1. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 0. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_main_SYSCLK0_2_clk_edc_ctrl_cbass_int_main_SYSCLK0_2_busecc_pend" "0,1" rgroup.long 0xC0++0xF line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_CBASS_DEFAULT_MMRS_J7AM_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_cbass_default_mmrs_j7am_rc_cbass_cbass_default_mmrs_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 30. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_ERR_SCR_J7AM_PULSAR0_SLV_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_scrm_128b_clk1_scr_j7am_rc_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x0 25. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_P2M_BRIDGE_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_CFG_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_CFG_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_J7AM_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "IJ7AM_RC_CFG_CBASS_J7AM_RC_CFG_CBASS_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 13. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_fw_vbusp_32b_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 10. "IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_fw_vbusp_32b_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 9. "IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_data_vbusm_64b_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 8. "ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Icor_mcu_data_vbusm_64b_src_vbuss_pend" "0,1" newline bitfld.long 0x0 7. "IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Iwku_cor_data_vbusp_32b_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 6. "IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Iwku_cor_data_vbusp_32b_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 5. "IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Iwku_cor_data_vbusp_32b_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_infra_vbusp_32b_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 3. "IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_infra_vbusp_32b_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 2. "IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_infra_vbusp_32b_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IMCU_COR_FW_VBUSP_32B_DST_M2P_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_fw_vbusp_32b_dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 0. "IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_data_vbusm_64b_m2m_vbuss_pend" "0,1" line.long 0x4 "REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 31. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST1_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 30. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_CFG_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_CFG_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 29. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_J7AM_TO_J7AM_RC_FW_CBASS_P2P_BRIDGE_J7AM_TO_J7AM_RC_FW_CBASS_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 28. "IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_MTOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Iemmcsd4ss_main_0_emmcsdss_wr_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 27. "IJ7AM_RC_TO_RC_CFG_VBUSM_L0_STOG_6_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_to_rc_cfg_vbusm_l0_stog_6_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 26. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_pulsar0_slv_cbass_0_j7am_pulsar0_slv_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 25. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 23. "IJ7AM_RC_CFG_CBASS_J7AM_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cfg_cbass_j7am_rc_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x4 22. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 21. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_scrm_64b_clk2_scr_j7am_rc_cbass_scrm_64b_clk2_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 19. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 18. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_pulsar0_slv_cbass_0_j7am_pulsar0_slv_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 17. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ERR_SCR_J7AM_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_err_scr_j7am_rc_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 16. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST0_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x4 14. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 13. "ICOMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_WR_VBUSM_MTOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Icompute_cluster_j7ahp_main_0_gic_mem_wr_vbusm_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 12. "IJ7AM_RC_TO_RC_CFG_VBUSM_L0_STOG_6_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_to_rc_cfg_vbusm_l0_stog_6_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_scrm_128b_clk1_scr_j7am_rc_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 7. "ICOMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_RD_VBUSM_MTOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Icompute_cluster_j7ahp_main_0_gic_mem_rd_vbusm_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 6. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_2_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_2_CPU1_CFG_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_CBASS_INT_DMSC_SCR_J7AM_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_cbass_int_dmsc_scr_j7am_rc_cbass_cbass_int_dmsc_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM0_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IIDOM0_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" line.long 0x8 "REGS_sec_enable_clr_reg2,Interrupt Enable Clear Register 2" bitfld.long 0x8 31. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM1_ECC_AGGR_MAIN_RC_R5_2_1_CFG_P2P_BRIDGE_IIDOM1_ECC_AGGR_MAIN_RC_R5_2_1_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 30. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 29. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 28. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 27. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 26. "IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_MTOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Iemmcsd4ss_main_0_emmcsdss_rd_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 25. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 24. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 23. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 22. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 21. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM0_ECC_AGGR_MAIN_RC_R5_2_0_CFG_P2P_BRIDGE_IIDOM0_ECC_AGGR_MAIN_RC_R5_2_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 20. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_1_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_1_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 19. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 18. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 17. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 16. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 14. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 13. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 12. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 11. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 10. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 9. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM1_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IIDOM1_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 8. "IJ7AM_RC_TO_RC_CFG_VBUSM_L0_STOG_6_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_to_rc_cfg_vbusm_l0_stog_6_rd_ramecc_pend" "0,1" newline bitfld.long 0x8 7. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM0_ECC_AGGR_MAIN_RC_R5_1_0_CFG_P2P_BRIDGE_IIDOM0_ECC_AGGR_MAIN_RC_R5_1_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 6. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRP_32B_CLK4_CFG_SCR_J7AM_RC_CBASS_SCRP_32B_CLK4_CFG_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 5. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_CBASS_DEFAULT_ERR_J7AM_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_cbass_default_err_j7am_rc_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 4. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 3. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 2. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 1. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_scrm_64b_clk2_scr_j7am_rc_cbass_scrm_64b_clk2_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 0. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM1_ECC_AGGR_MAIN_RC_R5_0_1_CFG_P2P_BRIDGE_IIDOM1_ECC_AGGR_MAIN_RC_R5_0_1_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" line.long 0xC "REGS_sec_enable_clr_reg3,Interrupt Enable Clear Register 3" bitfld.long 0xC 16. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0xC 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ICOMPUTE_CLUSTER_J7AHP_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7AHP_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 14. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 13. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 12. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_J7AM_PULSAR0_SLV_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 11. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 10. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 9. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 8. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 7. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 6. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 5. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 4. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Irc_fw_cbass_j7am_rc_cbass_main_fw_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0xC 3. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_2_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_2_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 2. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 1. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 0. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_main_SYSCLK0_2_clk_edc_ctrl_cbass_int_main_SYSCLK0_2_busecc_pend" "0,1" rgroup.long 0x13C++0x13 line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_CBASS_DEFAULT_MMRS_J7AM_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_cbass_default_mmrs_j7am_rc_cbass_cbass_default_mmrs_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 30. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_ERR_SCR_J7AM_PULSAR0_SLV_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_pulsar0_slv_cbass_0_j7am_pulsar0_slv_cbass_err_scr_j7am_pulsar0_slv_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 26. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_scrm_128b_clk1_scr_j7am_rc_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 25. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_P2M_BRIDGE_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_CFG_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_CFG_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_PEND,Interrupt Pending Status for Ij7am_pulsar0_slv_cbass_0_j7am_pulsar0_slv_cbass_main_SYSCLK0_2_clk_edc_ctrl_cbass_int_main_SYSCLK0_2_busecc_pend" "0,1" newline bitfld.long 0x4 19. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_J7AM_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "IJ7AM_RC_CFG_CBASS_J7AM_RC_CFG_CBASS_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_PEND,Interrupt Pending Status for Imcu_cor_fw_vbusp_32b_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 10. "IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_PEND,Interrupt Pending Status for Imcu_cor_fw_vbusp_32b_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 9. "IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_PEND,Interrupt Pending Status for Imcu_cor_data_vbusm_64b_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 8. "ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_PEND,Interrupt Pending Status for Icor_mcu_data_vbusm_64b_src_vbuss_pend" "0,1" newline bitfld.long 0x4 7. "IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_PEND,Interrupt Pending Status for Iwku_cor_data_vbusp_32b_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 6. "IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_PEND,Interrupt Pending Status for Iwku_cor_data_vbusp_32b_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 5. "IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_PEND,Interrupt Pending Status for Iwku_cor_data_vbusp_32b_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 4. "IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_PEND,Interrupt Pending Status for Imcu_cor_infra_vbusp_32b_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 3. "IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_PEND,Interrupt Pending Status for Imcu_cor_infra_vbusp_32b_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 2. "IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_PEND,Interrupt Pending Status for Imcu_cor_infra_vbusp_32b_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IMCU_COR_FW_VBUSP_32B_DST_M2P_BUSECC_PEND,Interrupt Pending Status for Imcu_cor_fw_vbusp_32b_dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x4 0. "IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_PEND,Interrupt Pending Status for Imcu_cor_data_vbusm_64b_m2m_vbuss_pend" "0,1" line.long 0x8 "REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 31. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST1_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 30. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_CFG_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_CFG_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 29. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_J7AM_TO_J7AM_RC_FW_CBASS_P2P_BRIDGE_J7AM_TO_J7AM_RC_FW_CBASS_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 28. "IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_MTOG_EDC_CTRL_PEND,Interrupt Pending Status for Iemmcsd4ss_main_0_emmcsdss_wr_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 27. "IJ7AM_RC_TO_RC_CFG_VBUSM_L0_STOG_6_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_rc_to_rc_cfg_vbusm_l0_stog_6_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 26. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_pulsar0_slv_cbass_0_j7am_pulsar0_slv_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 25. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 24. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 23. "IJ7AM_RC_CFG_CBASS_J7AM_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for Ij7am_rc_cfg_cbass_j7am_rc_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x8 22. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 21. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_scrm_64b_clk2_scr_j7am_rc_cbass_scrm_64b_clk2_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 19. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_rc_cbass_main_fw_cbass_rc_cbass_dmsc_slv_p2p_bridge_rc_cbass_dmsc_slv_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x8 18. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_pulsar0_slv_cbass_0_j7am_pulsar0_slv_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 17. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ERR_SCR_J7AM_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_err_scr_j7am_rc_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 16. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST0_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x8 14. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 13. "ICOMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_WR_VBUSM_MTOG_EDC_CTRL_PEND,Interrupt Pending Status for Icompute_cluster_j7ahp_main_0_gic_mem_wr_vbusm_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 12. "IJ7AM_RC_TO_RC_CFG_VBUSM_L0_STOG_6_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_rc_to_rc_cfg_vbusm_l0_stog_6_wr_ramecc_pend" "0,1" newline bitfld.long 0x8 11. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_scrm_128b_clk1_scr_j7am_rc_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 7. "ICOMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_RD_VBUSM_MTOG_EDC_CTRL_PEND,Interrupt Pending Status for Icompute_cluster_j7ahp_main_0_gic_mem_rd_vbusm_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 6. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_2_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_2_CPU1_CFG_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_CBASS_INT_DMSC_SCR_J7AM_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_cbass_int_dmsc_scr_j7am_rc_cbass_cbass_int_dmsc_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 1. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM0_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IIDOM0_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" line.long 0xC "REGS_ded_status_reg2,Interrupt Status Register 2" bitfld.long 0xC 31. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM1_ECC_AGGR_MAIN_RC_R5_2_1_CFG_P2P_BRIDGE_IIDOM1_ECC_AGGR_MAIN_RC_R5_2_1_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 30. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 29. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 28. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 27. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 26. "IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_MTOG_EDC_CTRL_PEND,Interrupt Pending Status for Iemmcsd4ss_main_0_emmcsdss_rd_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0xC 25. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 24. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0xC 23. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 22. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 21. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM0_ECC_AGGR_MAIN_RC_R5_2_0_CFG_P2P_BRIDGE_IIDOM0_ECC_AGGR_MAIN_RC_R5_2_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 20. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_1_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_1_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 19. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 18. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 17. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 16. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 14. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 13. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 12. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 11. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 10. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 9. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM1_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IIDOM1_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 8. "IJ7AM_RC_TO_RC_CFG_VBUSM_L0_STOG_6_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_rc_to_rc_cfg_vbusm_l0_stog_6_rd_ramecc_pend" "0,1" newline bitfld.long 0xC 7. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM0_ECC_AGGR_MAIN_RC_R5_1_0_CFG_P2P_BRIDGE_IIDOM0_ECC_AGGR_MAIN_RC_R5_1_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 6. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRP_32B_CLK4_CFG_SCR_J7AM_RC_CBASS_SCRP_32B_CLK4_CFG_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_scrp_32b_clk4_cfg_scr_j7am_rc_cbass_scrp_32b_clk4_cfg_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 5. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_CBASS_DEFAULT_ERR_J7AM_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_cbass_default_err_j7am_rc_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 4. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 3. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_rc_cbass_main_fw_cbass_rc_cbass_dmsc_slv_p2p_bridge_rc_cbass_dmsc_slv_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0xC 2. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 1. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_scrm_64b_clk2_scr_j7am_rc_cbass_scrm_64b_clk2_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0xC 0. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM1_ECC_AGGR_MAIN_RC_R5_0_1_CFG_P2P_BRIDGE_IIDOM1_ECC_AGGR_MAIN_RC_R5_0_1_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" line.long 0x10 "REGS_ded_status_reg3,Interrupt Status Register 3" bitfld.long 0x10 16. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x10 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ICOMPUTE_CLUSTER_J7AHP_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7AHP_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 14. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 13. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 12. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_J7AM_PULSAR0_SLV_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 11. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 10. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 9. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 8. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 7. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 6. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 5. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 4. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_rc_cbass_main_fw_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x10 3. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_2_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_2_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 2. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 1. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 0. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_PEND,Interrupt Pending Status for Ij7am_rc_cbass_j7am_rc_cbass_main_SYSCLK0_2_clk_edc_ctrl_cbass_int_main_SYSCLK0_2_busecc_pend" "0,1" rgroup.long 0x180++0xF line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_CBASS_DEFAULT_MMRS_J7AM_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_cbass_default_mmrs_j7am_rc_cbass_cbass_default_mmrs_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 30. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_ERR_SCR_J7AM_PULSAR0_SLV_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_scrm_128b_clk1_scr_j7am_rc_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x0 25. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_P2M_BRIDGE_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_CFG_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_CFG_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_J7AM_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "IJ7AM_RC_CFG_CBASS_J7AM_RC_CFG_CBASS_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 13. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_fw_vbusp_32b_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 10. "IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_fw_vbusp_32b_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 9. "IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_data_vbusm_64b_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 8. "ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Icor_mcu_data_vbusm_64b_src_vbuss_pend" "0,1" newline bitfld.long 0x0 7. "IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Iwku_cor_data_vbusp_32b_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 6. "IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Iwku_cor_data_vbusp_32b_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 5. "IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Iwku_cor_data_vbusp_32b_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_infra_vbusp_32b_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 3. "IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_infra_vbusp_32b_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 2. "IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_infra_vbusp_32b_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IMCU_COR_FW_VBUSP_32B_DST_M2P_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_fw_vbusp_32b_dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 0. "IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_data_vbusm_64b_m2m_vbuss_pend" "0,1" line.long 0x4 "REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 31. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST1_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 30. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_CFG_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_CFG_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 29. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_J7AM_TO_J7AM_RC_FW_CBASS_P2P_BRIDGE_J7AM_TO_J7AM_RC_FW_CBASS_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 28. "IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_MTOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Iemmcsd4ss_main_0_emmcsdss_wr_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 27. "IJ7AM_RC_TO_RC_CFG_VBUSM_L0_STOG_6_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_to_rc_cfg_vbusm_l0_stog_6_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 26. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_pulsar0_slv_cbass_0_j7am_pulsar0_slv_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 25. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 23. "IJ7AM_RC_CFG_CBASS_J7AM_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cfg_cbass_j7am_rc_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x4 22. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 21. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_scrm_64b_clk2_scr_j7am_rc_cbass_scrm_64b_clk2_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 19. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 18. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_pulsar0_slv_cbass_0_j7am_pulsar0_slv_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 17. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ERR_SCR_J7AM_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_err_scr_j7am_rc_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 16. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST0_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x4 14. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 13. "ICOMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_WR_VBUSM_MTOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Icompute_cluster_j7ahp_main_0_gic_mem_wr_vbusm_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 12. "IJ7AM_RC_TO_RC_CFG_VBUSM_L0_STOG_6_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_to_rc_cfg_vbusm_l0_stog_6_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_scrm_128b_clk1_scr_j7am_rc_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 7. "ICOMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_RD_VBUSM_MTOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Icompute_cluster_j7ahp_main_0_gic_mem_rd_vbusm_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 6. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_2_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_2_CPU1_CFG_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_CBASS_INT_DMSC_SCR_J7AM_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_cbass_int_dmsc_scr_j7am_rc_cbass_cbass_int_dmsc_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM0_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IIDOM0_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" line.long 0x8 "REGS_ded_enable_set_reg2,Interrupt Enable Set Register 2" bitfld.long 0x8 31. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM1_ECC_AGGR_MAIN_RC_R5_2_1_CFG_P2P_BRIDGE_IIDOM1_ECC_AGGR_MAIN_RC_R5_2_1_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 30. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 29. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 28. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 27. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 26. "IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_MTOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Iemmcsd4ss_main_0_emmcsdss_rd_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 25. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 24. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 23. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 22. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 21. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM0_ECC_AGGR_MAIN_RC_R5_2_0_CFG_P2P_BRIDGE_IIDOM0_ECC_AGGR_MAIN_RC_R5_2_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 20. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_1_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_1_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 19. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 18. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 17. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 16. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 14. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 13. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 12. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 11. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 10. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 9. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM1_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IIDOM1_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 8. "IJ7AM_RC_TO_RC_CFG_VBUSM_L0_STOG_6_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_to_rc_cfg_vbusm_l0_stog_6_rd_ramecc_pend" "0,1" newline bitfld.long 0x8 7. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM0_ECC_AGGR_MAIN_RC_R5_1_0_CFG_P2P_BRIDGE_IIDOM0_ECC_AGGR_MAIN_RC_R5_1_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 6. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRP_32B_CLK4_CFG_SCR_J7AM_RC_CBASS_SCRP_32B_CLK4_CFG_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_scrp_32b_clk4_cfg_scr_j7am_rc_cbass_scrp_32b_clk4_cfg_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 5. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_CBASS_DEFAULT_ERR_J7AM_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_cbass_default_err_j7am_rc_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 4. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 3. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 2. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 1. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_scrm_64b_clk2_scr_j7am_rc_cbass_scrm_64b_clk2_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 0. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM1_ECC_AGGR_MAIN_RC_R5_0_1_CFG_P2P_BRIDGE_IIDOM1_ECC_AGGR_MAIN_RC_R5_0_1_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" line.long 0xC "REGS_ded_enable_set_reg3,Interrupt Enable Set Register 3" bitfld.long 0xC 16. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0xC 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ICOMPUTE_CLUSTER_J7AHP_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7AHP_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 14. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 13. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 12. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_J7AM_PULSAR0_SLV_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 11. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 10. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 9. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 8. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 7. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 6. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 5. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 4. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_rc_cbass_main_fw_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0xC 3. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_2_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_2_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 2. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 1. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 0. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_cbass_j7am_rc_cbass_main_SYSCLK0_2_clk_edc_ctrl_cbass_int_main_SYSCLK0_2_busecc_pend" "0,1" rgroup.long 0x1C0++0xF line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_CBASS_DEFAULT_MMRS_J7AM_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_cbass_default_mmrs_j7am_rc_cbass_cbass_default_mmrs_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 30. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_ERR_SCR_J7AM_PULSAR0_SLV_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_scrm_128b_clk1_scr_j7am_rc_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x0 25. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_P2M_BRIDGE_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_CFG_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_CFG_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_J7AM_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "IJ7AM_RC_CFG_CBASS_J7AM_RC_CFG_CBASS_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 13. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_fw_vbusp_32b_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 10. "IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_fw_vbusp_32b_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 9. "IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_data_vbusm_64b_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 8. "ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Icor_mcu_data_vbusm_64b_src_vbuss_pend" "0,1" newline bitfld.long 0x0 7. "IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Iwku_cor_data_vbusp_32b_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 6. "IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Iwku_cor_data_vbusp_32b_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 5. "IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Iwku_cor_data_vbusp_32b_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_infra_vbusp_32b_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 3. "IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_infra_vbusp_32b_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 2. "IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_infra_vbusp_32b_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IMCU_COR_FW_VBUSP_32B_DST_M2P_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_fw_vbusp_32b_dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 0. "IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_data_vbusm_64b_m2m_vbuss_pend" "0,1" line.long 0x4 "REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 31. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST1_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 30. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_CFG_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_CFG_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 29. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_J7AM_TO_J7AM_RC_FW_CBASS_P2P_BRIDGE_J7AM_TO_J7AM_RC_FW_CBASS_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 28. "IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_MTOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Iemmcsd4ss_main_0_emmcsdss_wr_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 27. "IJ7AM_RC_TO_RC_CFG_VBUSM_L0_STOG_6_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_to_rc_cfg_vbusm_l0_stog_6_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 26. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_pulsar0_slv_cbass_0_j7am_pulsar0_slv_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 25. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 23. "IJ7AM_RC_CFG_CBASS_J7AM_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cfg_cbass_j7am_rc_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x4 22. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 21. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_scrm_64b_clk2_scr_j7am_rc_cbass_scrm_64b_clk2_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 19. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 18. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_pulsar0_slv_cbass_0_j7am_pulsar0_slv_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 17. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ERR_SCR_J7AM_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_err_scr_j7am_rc_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 16. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST0_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x4 14. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 13. "ICOMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_WR_VBUSM_MTOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Icompute_cluster_j7ahp_main_0_gic_mem_wr_vbusm_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 12. "IJ7AM_RC_TO_RC_CFG_VBUSM_L0_STOG_6_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_to_rc_cfg_vbusm_l0_stog_6_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_128B_CLK1_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7AM_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_J7AM_RC_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_scrm_128b_clk1_scr_j7am_rc_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 7. "ICOMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_RD_VBUSM_MTOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Icompute_cluster_j7ahp_main_0_gic_mem_rd_vbusm_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 6. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_RC_TO_RC_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_2_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_2_CPU1_CFG_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_CBASS_INT_DMSC_SCR_J7AM_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_cbass_int_dmsc_scr_j7am_rc_cbass_cbass_int_dmsc_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM0_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IIDOM0_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" line.long 0x8 "REGS_ded_enable_clr_reg2,Interrupt Enable Clear Register 2" bitfld.long 0x8 31. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM1_ECC_AGGR_MAIN_RC_R5_2_1_CFG_P2P_BRIDGE_IIDOM1_ECC_AGGR_MAIN_RC_R5_2_1_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 30. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 29. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 28. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_J7AM_RC_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 27. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 26. "IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_MTOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Iemmcsd4ss_main_0_emmcsdss_rd_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 25. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 24. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 23. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 22. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 21. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM0_ECC_AGGR_MAIN_RC_R5_2_0_CFG_P2P_BRIDGE_IIDOM0_ECC_AGGR_MAIN_RC_R5_2_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 20. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_1_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_1_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 19. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 18. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_BR_BR_SCRM_64B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_64B_CLK2_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 17. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 16. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7AM_MAIN_RC_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 14. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 13. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 12. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 11. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_VIRTSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 10. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_J7AM_PULSAR0_SLV_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 9. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM1_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IIDOM1_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 8. "IJ7AM_RC_TO_RC_CFG_VBUSM_L0_STOG_6_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_to_rc_cfg_vbusm_l0_stog_6_rd_ramecc_pend" "0,1" newline bitfld.long 0x8 7. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM0_ECC_AGGR_MAIN_RC_R5_1_0_CFG_P2P_BRIDGE_IIDOM0_ECC_AGGR_MAIN_RC_R5_1_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 6. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRP_32B_CLK4_CFG_SCR_J7AM_RC_CBASS_SCRP_32B_CLK4_CFG_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 5. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_CBASS_DEFAULT_ERR_J7AM_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_cbass_default_err_j7am_rc_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 4. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 3. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 2. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7AM_NAVSS512_NBSS_PHYS_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 1. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_J7AM_RC_CBASS_SCRM_64B_CLK2_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_scrm_64b_clk2_scr_j7am_rc_cbass_scrm_64b_clk2_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 0. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IIDOM1_ECC_AGGR_MAIN_RC_R5_0_1_CFG_P2P_BRIDGE_IIDOM1_ECC_AGGR_MAIN_RC_R5_0_1_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" line.long 0xC "REGS_ded_enable_clr_reg3,Interrupt Enable Clear Register 3" bitfld.long 0xC 16. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0xC 15. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_ICOMPUTE_CLUSTER_J7AHP_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7AHP_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 14. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 13. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 12. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_J7AM_PULSAR0_SLV_CBASS_EXPORT_J7AM_RC_TO_PULSAR0_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 11. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 10. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 9. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 8. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 7. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_J7AM_RC_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 6. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 5. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7AM_RC_CBASS_INAVSS512J7AM_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 4. "IRC_FW_CBASS_J7AM_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Irc_fw_cbass_j7am_rc_cbass_main_fw_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0xC 3. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_2_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_2_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 2. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 1. "IJ7AM_PULSAR0_SLV_CBASS_0_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_J7AM_PULSAR0_SLV_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 0. "IJ7AM_RC_CBASS_J7AM_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_cbass_j7am_rc_cbass_main_SYSCLK0_2_clk_edc_ctrl_cbass_int_main_SYSCLK0_2_busecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "ECC_AGGR5_ECC_AGGR (ECC_AGGR5_ECC_AGGR)" base ad:0x2AF5000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "J7AM_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for j7am_hc_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x4 30. "J7AM_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7am_hc2_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 29. "J7AM_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for j7am_main_hc2_fw_cbass_hc2_cbass_dmsc_slv_p2p_bridge_hc2_cbass_dmsc_slv_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 28. "J7AM_HC2_CBASS_CBASS_DEFAULT_ERR_J7AM_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_hc2_cbass_cbass_default_err_j7am_hc2_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 27. "J7AM_HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_PEND,Interrupt Pending Status for j7am_hc2_cbass_main_SYSCLK0_1_clk_edc_ctrl_cbass_int_main_SYSCLK0_1_busecc_0_pend" "0,1" newline bitfld.long 0x4 26. "J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for j7am_hc2_cbass_scrm_128b_clk1_scr_j7am_hc2_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 25. "J7AM_HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_PEND,Interrupt Pending Status for j7am_hc2_cbass_main_SYSCLK0_1_clk_edc_ctrl_cbass_int_main_SYSCLK0_1_busecc_1_pend" "0,1" newline bitfld.long 0x4 24. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_rc_to_hc2_vbusm_l1_stog_4_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 23. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for Ij7am_rc_to_hc2_vbusm_l1_stog_4_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 22. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_rc_to_hc2_vbusm_l1_stog_4_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "J7AM_HC2_CBASS_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_rc_to_hc2_vbusm_l0_stog_3_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "J7AM_HC2_CBASS_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "J7AM_HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_PEND,Interrupt Pending Status for j7am_hc2_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_1_pend" "0,1" newline bitfld.long 0x4 16. "J7AM_HC2_CBASS_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "IJ7AM_HC2_TO_RC_VBUSM_L0_MTOG_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_hc2_to_rc_vbusm_l0_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 12. "J7AM_HC2_CBASS_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "J7AM_HC_CFG_CBASS_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 10. "J7AM_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7am_hc2_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 9. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for Ij7am_rc_to_hc2_vbusm_l1_stog_4_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 8. "J7AM_HC2_CBASS_SCRP_32B_CLK4_SCR_J7AM_HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_hc2_cbass_scrp_32b_clk4_scr_j7am_hc2_cbass_scrp_32b_clk4_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 7. "IJ7AM_HC2_TO_HC_CFG_VBUSM_L0_STOG_5_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_hc2_to_hc_cfg_vbusm_l0_stog_5_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "IJ7AM_HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_hc2_to_hc_cfg_vbusm_l0_stog_5_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 5. "J7AM_HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_PEND,Interrupt Pending Status for j7am_hc2_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_0_pend" "0,1" newline bitfld.long 0x4 4. "IJ7AM_HC2_TO_HC_CFG_VBUSM_L0_STOG_5_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_hc2_to_hc_cfg_vbusm_l0_stog_5_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_rc_to_hc2_vbusm_l0_stog_3_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "IJ7AM_HC2_TO_RC_VBUSM_L1_MTOG_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_hc2_to_rc_vbusm_l1_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 0. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" line.long 0x8 "REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x8 23. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 21. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for Ij7am_rc_to_hc2_vbusm_l0_stog_3_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 20. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for Ij7am_rc_to_hc2_vbusm_l0_stog_3_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 19. "J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for j7am_hc2_cbass_scrm_128b_clk1_scr_j7am_hc2_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 18. "J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7am_hc2_cbass_export_j7am_rc_to_hc2_vbusp_l0_p2p_bridge_export_j7am_rc_to_hc2_vbusp_l0_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 17. "J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 16. "J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 15. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 14. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 13. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 12. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 11. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 10. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 9. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 8. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 7. "J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for j7am_hc2_cbass_scrm_128b_clk1_scr_j7am_hc2_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 4. "J7AM_HC2_CBASS_ERR_SCR_J7AM_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_hc2_cbass_err_scr_j7am_hc2_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 3. "J7AM_HC2_CBASS_CBASS_DEFAULT_MMRS_J7AM_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_hc2_cbass_cbass_default_mmrs_j7am_hc2_cbass_cbass_default_mmrs_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 2. "IJ7AM_MAIN_HC2_FW_CBASS_0_J7AM_MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for Ij7am_main_hc2_fw_cbass_0_j7am_main_hc2_fw_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x8 1. "J7AM_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for j7am_main_hc2_fw_cbass_hc2_cbass_dmsc_slv_p2p_bridge_hc2_cbass_dmsc_slv_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x8 0. "J7AM_HC2_CBASS_CBASS_INT_DMSC_SCR_J7AM_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_hc2_cbass_cbass_int_dmsc_scr_j7am_hc2_cbass_cbass_int_dmsc_scr_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x80++0x7 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "J7AM_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_hc_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x0 30. "J7AM_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 29. "J7AM_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_main_hc2_fw_cbass_hc2_cbass_dmsc_slv_p2p_bridge_hc2_cbass_dmsc_slv_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 28. "J7AM_HC2_CBASS_CBASS_DEFAULT_ERR_J7AM_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_cbass_default_err_j7am_hc2_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 27. "J7AM_HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_main_SYSCLK0_1_clk_edc_ctrl_cbass_int_main_SYSCLK0_1_busecc_0_pend" "0,1" newline bitfld.long 0x0 26. "J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_scrm_128b_clk1_scr_j7am_hc2_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x0 25. "J7AM_HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_main_SYSCLK0_1_clk_edc_ctrl_cbass_int_main_SYSCLK0_1_busecc_1_pend" "0,1" newline bitfld.long 0x0 24. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_to_hc2_vbusm_l1_stog_4_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_to_hc2_vbusm_l1_stog_4_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x0 22. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_to_hc2_vbusm_l1_stog_4_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "J7AM_HC2_CBASS_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_to_hc2_vbusm_l0_stog_3_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "J7AM_HC2_CBASS_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "J7AM_HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_1_pend" "0,1" newline bitfld.long 0x0 16. "J7AM_HC2_CBASS_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "IJ7AM_HC2_TO_RC_VBUSM_L0_MTOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc2_to_rc_vbusm_l0_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 12. "J7AM_HC2_CBASS_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "J7AM_HC_CFG_CBASS_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 10. "J7AM_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_to_hc2_vbusm_l1_stog_4_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x0 8. "J7AM_HC2_CBASS_SCRP_32B_CLK4_SCR_J7AM_HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_scrp_32b_clk4_scr_j7am_hc2_cbass_scrp_32b_clk4_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IJ7AM_HC2_TO_HC_CFG_VBUSM_L0_STOG_5_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc2_to_hc_cfg_vbusm_l0_stog_5_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "IJ7AM_HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc2_to_hc_cfg_vbusm_l0_stog_5_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 5. "J7AM_HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_0_pend" "0,1" newline bitfld.long 0x0 4. "IJ7AM_HC2_TO_HC_CFG_VBUSM_L0_STOG_5_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc2_to_hc_cfg_vbusm_l0_stog_5_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 2. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_to_hc2_vbusm_l0_stog_3_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "IJ7AM_HC2_TO_RC_VBUSM_L1_MTOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc2_to_rc_vbusm_l1_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 0. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" line.long 0x4 "REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x4 23. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 21. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_to_hc2_vbusm_l0_stog_3_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 20. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_to_hc2_vbusm_l0_stog_3_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 19. "J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_scrm_128b_clk1_scr_j7am_hc2_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 18. "J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_export_j7am_rc_to_hc2_vbusp_l0_p2p_bridge_export_j7am_rc_to_hc2_vbusp_l0_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 17. "J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 16. "J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 15. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 14. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 13. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 11. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 9. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 8. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 7. "J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_scrm_128b_clk1_scr_j7am_hc2_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 4. "J7AM_HC2_CBASS_ERR_SCR_J7AM_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_err_scr_j7am_hc2_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "J7AM_HC2_CBASS_CBASS_DEFAULT_MMRS_J7AM_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_cbass_default_mmrs_j7am_hc2_cbass_cbass_default_mmrs_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 2. "IJ7AM_MAIN_HC2_FW_CBASS_0_J7AM_MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "J7AM_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_main_hc2_fw_cbass_hc2_cbass_dmsc_slv_p2p_bridge_hc2_cbass_dmsc_slv_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 0. "J7AM_HC2_CBASS_CBASS_INT_DMSC_SCR_J7AM_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_cbass_int_dmsc_scr_j7am_hc2_cbass_cbass_int_dmsc_scr_edc_ctrl_busecc_pend" "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "J7AM_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x0 30. "J7AM_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 29. "J7AM_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_hc2_fw_cbass_hc2_cbass_dmsc_slv_p2p_bridge_hc2_cbass_dmsc_slv_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 28. "J7AM_HC2_CBASS_CBASS_DEFAULT_ERR_J7AM_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_cbass_default_err_j7am_hc2_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 27. "J7AM_HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_main_SYSCLK0_1_clk_edc_ctrl_cbass_int_main_SYSCLK0_1_busecc_0_pend" "0,1" newline bitfld.long 0x0 26. "J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_scrm_128b_clk1_scr_j7am_hc2_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x0 25. "J7AM_HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_main_SYSCLK0_1_clk_edc_ctrl_cbass_int_main_SYSCLK0_1_busecc_1_pend" "0,1" newline bitfld.long 0x0 24. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_to_hc2_vbusm_l1_stog_4_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_to_hc2_vbusm_l1_stog_4_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x0 22. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_to_hc2_vbusm_l1_stog_4_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "J7AM_HC2_CBASS_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_to_hc2_vbusm_l0_stog_3_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "J7AM_HC2_CBASS_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "J7AM_HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_1_pend" "0,1" newline bitfld.long 0x0 16. "J7AM_HC2_CBASS_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "IJ7AM_HC2_TO_RC_VBUSM_L0_MTOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc2_to_rc_vbusm_l0_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 12. "J7AM_HC2_CBASS_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "J7AM_HC_CFG_CBASS_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 10. "J7AM_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_to_hc2_vbusm_l1_stog_4_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x0 8. "J7AM_HC2_CBASS_SCRP_32B_CLK4_SCR_J7AM_HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_scrp_32b_clk4_scr_j7am_hc2_cbass_scrp_32b_clk4_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IJ7AM_HC2_TO_HC_CFG_VBUSM_L0_STOG_5_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc2_to_hc_cfg_vbusm_l0_stog_5_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "IJ7AM_HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc2_to_hc_cfg_vbusm_l0_stog_5_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 5. "J7AM_HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_0_pend" "0,1" newline bitfld.long 0x0 4. "IJ7AM_HC2_TO_HC_CFG_VBUSM_L0_STOG_5_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc2_to_hc_cfg_vbusm_l0_stog_5_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 2. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_to_hc2_vbusm_l0_stog_3_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "IJ7AM_HC2_TO_RC_VBUSM_L1_MTOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc2_to_rc_vbusm_l1_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 0. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" line.long 0x4 "REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x4 23. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 21. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_to_hc2_vbusm_l0_stog_3_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 20. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_to_hc2_vbusm_l0_stog_3_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 19. "J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_scrm_128b_clk1_scr_j7am_hc2_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 18. "J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_export_j7am_rc_to_hc2_vbusp_l0_p2p_bridge_export_j7am_rc_to_hc2_vbusp_l0_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 17. "J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 16. "J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 15. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 14. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 13. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 11. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 9. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 8. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 7. "J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_scrm_128b_clk1_scr_j7am_hc2_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 4. "J7AM_HC2_CBASS_ERR_SCR_J7AM_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_err_scr_j7am_hc2_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "J7AM_HC2_CBASS_CBASS_DEFAULT_MMRS_J7AM_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_cbass_default_mmrs_j7am_hc2_cbass_cbass_default_mmrs_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 2. "IJ7AM_MAIN_HC2_FW_CBASS_0_J7AM_MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "J7AM_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_hc2_fw_cbass_hc2_cbass_dmsc_slv_p2p_bridge_hc2_cbass_dmsc_slv_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 0. "J7AM_HC2_CBASS_CBASS_INT_DMSC_SCR_J7AM_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_cbass_int_dmsc_scr_j7am_hc2_cbass_cbass_int_dmsc_scr_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x13C++0xB line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "J7AM_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for j7am_hc_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x4 30. "J7AM_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7am_hc2_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 29. "J7AM_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for j7am_main_hc2_fw_cbass_hc2_cbass_dmsc_slv_p2p_bridge_hc2_cbass_dmsc_slv_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 28. "J7AM_HC2_CBASS_CBASS_DEFAULT_ERR_J7AM_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_hc2_cbass_cbass_default_err_j7am_hc2_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 27. "J7AM_HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_PEND,Interrupt Pending Status for j7am_hc2_cbass_main_SYSCLK0_1_clk_edc_ctrl_cbass_int_main_SYSCLK0_1_busecc_0_pend" "0,1" newline bitfld.long 0x4 26. "J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for j7am_hc2_cbass_scrm_128b_clk1_scr_j7am_hc2_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 25. "J7AM_HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_PEND,Interrupt Pending Status for j7am_hc2_cbass_main_SYSCLK0_1_clk_edc_ctrl_cbass_int_main_SYSCLK0_1_busecc_1_pend" "0,1" newline bitfld.long 0x4 24. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_rc_to_hc2_vbusm_l1_stog_4_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 23. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for Ij7am_rc_to_hc2_vbusm_l1_stog_4_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 22. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_rc_to_hc2_vbusm_l1_stog_4_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "J7AM_HC2_CBASS_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_rc_to_hc2_vbusm_l0_stog_3_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "J7AM_HC2_CBASS_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "J7AM_HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_PEND,Interrupt Pending Status for j7am_hc2_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_1_pend" "0,1" newline bitfld.long 0x4 16. "J7AM_HC2_CBASS_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "IJ7AM_HC2_TO_RC_VBUSM_L0_MTOG_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_hc2_to_rc_vbusm_l0_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 12. "J7AM_HC2_CBASS_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "J7AM_HC_CFG_CBASS_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 10. "J7AM_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7am_hc2_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 9. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for Ij7am_rc_to_hc2_vbusm_l1_stog_4_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 8. "J7AM_HC2_CBASS_SCRP_32B_CLK4_SCR_J7AM_HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_hc2_cbass_scrp_32b_clk4_scr_j7am_hc2_cbass_scrp_32b_clk4_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 7. "IJ7AM_HC2_TO_HC_CFG_VBUSM_L0_STOG_5_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_hc2_to_hc_cfg_vbusm_l0_stog_5_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "IJ7AM_HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_hc2_to_hc_cfg_vbusm_l0_stog_5_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 5. "J7AM_HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_PEND,Interrupt Pending Status for j7am_hc2_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_0_pend" "0,1" newline bitfld.long 0x4 4. "IJ7AM_HC2_TO_HC_CFG_VBUSM_L0_STOG_5_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_hc2_to_hc_cfg_vbusm_l0_stog_5_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_rc_to_hc2_vbusm_l0_stog_3_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "IJ7AM_HC2_TO_RC_VBUSM_L1_MTOG_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_hc2_to_rc_vbusm_l1_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 0. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" line.long 0x8 "REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x8 23. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 21. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for Ij7am_rc_to_hc2_vbusm_l0_stog_3_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 20. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for Ij7am_rc_to_hc2_vbusm_l0_stog_3_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 19. "J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for j7am_hc2_cbass_scrm_128b_clk1_scr_j7am_hc2_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 18. "J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7am_hc2_cbass_export_j7am_rc_to_hc2_vbusp_l0_p2p_bridge_export_j7am_rc_to_hc2_vbusp_l0_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 17. "J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 16. "J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 15. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 14. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 13. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 12. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 11. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 10. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 9. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 8. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 7. "J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for j7am_hc2_cbass_scrm_128b_clk1_scr_j7am_hc2_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 4. "J7AM_HC2_CBASS_ERR_SCR_J7AM_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_hc2_cbass_err_scr_j7am_hc2_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 3. "J7AM_HC2_CBASS_CBASS_DEFAULT_MMRS_J7AM_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_hc2_cbass_cbass_default_mmrs_j7am_hc2_cbass_cbass_default_mmrs_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 2. "IJ7AM_MAIN_HC2_FW_CBASS_0_J7AM_MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for Ij7am_main_hc2_fw_cbass_0_j7am_main_hc2_fw_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x8 1. "J7AM_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for j7am_main_hc2_fw_cbass_hc2_cbass_dmsc_slv_p2p_bridge_hc2_cbass_dmsc_slv_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x8 0. "J7AM_HC2_CBASS_CBASS_INT_DMSC_SCR_J7AM_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_hc2_cbass_cbass_int_dmsc_scr_j7am_hc2_cbass_cbass_int_dmsc_scr_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x180++0x7 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "J7AM_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_hc_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x0 30. "J7AM_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 29. "J7AM_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_main_hc2_fw_cbass_hc2_cbass_dmsc_slv_p2p_bridge_hc2_cbass_dmsc_slv_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 28. "J7AM_HC2_CBASS_CBASS_DEFAULT_ERR_J7AM_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_cbass_default_err_j7am_hc2_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 27. "J7AM_HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_main_SYSCLK0_1_clk_edc_ctrl_cbass_int_main_SYSCLK0_1_busecc_0_pend" "0,1" newline bitfld.long 0x0 26. "J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_scrm_128b_clk1_scr_j7am_hc2_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x0 25. "J7AM_HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_main_SYSCLK0_1_clk_edc_ctrl_cbass_int_main_SYSCLK0_1_busecc_1_pend" "0,1" newline bitfld.long 0x0 24. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_to_hc2_vbusm_l1_stog_4_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_to_hc2_vbusm_l1_stog_4_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x0 22. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_to_hc2_vbusm_l1_stog_4_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "J7AM_HC2_CBASS_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_to_hc2_vbusm_l0_stog_3_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "J7AM_HC2_CBASS_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "J7AM_HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_1_pend" "0,1" newline bitfld.long 0x0 16. "J7AM_HC2_CBASS_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "IJ7AM_HC2_TO_RC_VBUSM_L0_MTOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc2_to_rc_vbusm_l0_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 12. "J7AM_HC2_CBASS_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "J7AM_HC_CFG_CBASS_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 10. "J7AM_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_to_hc2_vbusm_l1_stog_4_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x0 8. "J7AM_HC2_CBASS_SCRP_32B_CLK4_SCR_J7AM_HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_scrp_32b_clk4_scr_j7am_hc2_cbass_scrp_32b_clk4_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IJ7AM_HC2_TO_HC_CFG_VBUSM_L0_STOG_5_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc2_to_hc_cfg_vbusm_l0_stog_5_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "IJ7AM_HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc2_to_hc_cfg_vbusm_l0_stog_5_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 5. "J7AM_HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_0_pend" "0,1" newline bitfld.long 0x0 4. "IJ7AM_HC2_TO_HC_CFG_VBUSM_L0_STOG_5_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc2_to_hc_cfg_vbusm_l0_stog_5_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 2. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_to_hc2_vbusm_l0_stog_3_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "IJ7AM_HC2_TO_RC_VBUSM_L1_MTOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc2_to_rc_vbusm_l1_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 0. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" line.long 0x4 "REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x4 23. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 21. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_to_hc2_vbusm_l0_stog_3_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 20. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for Ij7am_rc_to_hc2_vbusm_l0_stog_3_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 19. "J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_scrm_128b_clk1_scr_j7am_hc2_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 18. "J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_export_j7am_rc_to_hc2_vbusp_l0_p2p_bridge_export_j7am_rc_to_hc2_vbusp_l0_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 17. "J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 16. "J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 15. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 14. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 13. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 11. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 9. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 8. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 7. "J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_scrm_128b_clk1_scr_j7am_hc2_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 4. "J7AM_HC2_CBASS_ERR_SCR_J7AM_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_err_scr_j7am_hc2_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "J7AM_HC2_CBASS_CBASS_DEFAULT_MMRS_J7AM_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_cbass_default_mmrs_j7am_hc2_cbass_cbass_default_mmrs_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 2. "IJ7AM_MAIN_HC2_FW_CBASS_0_J7AM_MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "J7AM_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_main_hc2_fw_cbass_hc2_cbass_dmsc_slv_p2p_bridge_hc2_cbass_dmsc_slv_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 0. "J7AM_HC2_CBASS_CBASS_INT_DMSC_SCR_J7AM_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_hc2_cbass_cbass_int_dmsc_scr_j7am_hc2_cbass_cbass_int_dmsc_scr_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "J7AM_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x0 30. "J7AM_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 29. "J7AM_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_hc2_fw_cbass_hc2_cbass_dmsc_slv_p2p_bridge_hc2_cbass_dmsc_slv_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 28. "J7AM_HC2_CBASS_CBASS_DEFAULT_ERR_J7AM_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_cbass_default_err_j7am_hc2_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 27. "J7AM_HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_main_SYSCLK0_1_clk_edc_ctrl_cbass_int_main_SYSCLK0_1_busecc_0_pend" "0,1" newline bitfld.long 0x0 26. "J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_scrm_128b_clk1_scr_j7am_hc2_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x0 25. "J7AM_HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_main_SYSCLK0_1_clk_edc_ctrl_cbass_int_main_SYSCLK0_1_busecc_1_pend" "0,1" newline bitfld.long 0x0 24. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_to_hc2_vbusm_l1_stog_4_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_to_hc2_vbusm_l1_stog_4_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x0 22. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_to_hc2_vbusm_l1_stog_4_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "J7AM_HC2_CBASS_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_to_hc2_vbusm_l0_stog_3_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "J7AM_HC2_CBASS_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "J7AM_HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_1_pend" "0,1" newline bitfld.long 0x0 16. "J7AM_HC2_CBASS_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7AM_MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "IJ7AM_HC2_TO_RC_VBUSM_L0_MTOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc2_to_rc_vbusm_l0_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 12. "J7AM_HC2_CBASS_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "J7AM_HC_CFG_CBASS_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 10. "J7AM_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IJ7AM_RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_to_hc2_vbusm_l1_stog_4_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x0 8. "J7AM_HC2_CBASS_SCRP_32B_CLK4_SCR_J7AM_HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_scrp_32b_clk4_scr_j7am_hc2_cbass_scrp_32b_clk4_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IJ7AM_HC2_TO_HC_CFG_VBUSM_L0_STOG_5_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc2_to_hc_cfg_vbusm_l0_stog_5_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "IJ7AM_HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc2_to_hc_cfg_vbusm_l0_stog_5_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 5. "J7AM_HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_0_pend" "0,1" newline bitfld.long 0x0 4. "IJ7AM_HC2_TO_HC_CFG_VBUSM_L0_STOG_5_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc2_to_hc_cfg_vbusm_l0_stog_5_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 2. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_to_hc2_vbusm_l0_stog_3_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "IJ7AM_HC2_TO_RC_VBUSM_L1_MTOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc2_to_rc_vbusm_l1_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 0. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" line.long 0x4 "REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x4 23. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "J7AM_HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 21. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_to_hc2_vbusm_l0_stog_3_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 20. "IJ7AM_RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_rc_to_hc2_vbusm_l0_stog_3_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 19. "J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_scrm_128b_clk1_scr_j7am_hc2_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 18. "J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_export_j7am_rc_to_hc2_vbusp_l0_p2p_bridge_export_j7am_rc_to_hc2_vbusp_l0_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 17. "J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 16. "J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 15. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 14. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 13. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 11. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 9. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 8. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 7. "J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_HC2_CBASS_EXPORT_J7AM_HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_J7AM_HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_scrm_128b_clk1_scr_j7am_hc2_cbass_scrm_128b_clk1_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 4. "J7AM_HC2_CBASS_ERR_SCR_J7AM_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_err_scr_j7am_hc2_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "J7AM_HC2_CBASS_CBASS_DEFAULT_MMRS_J7AM_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_cbass_default_mmrs_j7am_hc2_cbass_cbass_default_mmrs_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 2. "IJ7AM_MAIN_HC2_FW_CBASS_0_J7AM_MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "J7AM_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_main_hc2_fw_cbass_hc2_cbass_dmsc_slv_p2p_bridge_hc2_cbass_dmsc_slv_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 0. "J7AM_HC2_CBASS_CBASS_INT_DMSC_SCR_J7AM_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_hc2_cbass_cbass_int_dmsc_scr_j7am_hc2_cbass_cbass_int_dmsc_scr_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "ECC_AGGR6_ECC_AGGR (ECC_AGGR6_ECC_AGGR)" base ad:0x2AF7000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xF line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 30. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 29. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_non_safe_cbass_0_j7am_ac_non_safe_cbass_main_SYSCLK0_1_clk_edc_ctrl_cbass_int_main_SYSCLK0_1_busecc_pend" "0,1" newline bitfld.long 0x4 27. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_navss_to_ac_non_safe_stog_0_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 25. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_cbass_default_err_j7am_ac_cfg_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 22. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_2_clk_edc_ctrl_cbass_int_main_SYSCLK0_2_busecc_pend" "0,1" newline bitfld.long 0x4 21. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SCR_J7AM_AC_CFG_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_scr_j7am_ac_cfg_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 16. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 15. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 14. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_0_pend" "0,1" newline bitfld.long 0x4 13. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 9. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_merger_cbass_0_j7am_ac_merger_cbass_main_SYSCLK0_1_clk_edc_ctrl_cbass_int_main_SYSCLK0_1_busecc_pend" "0,1" newline bitfld.long 0x4 8. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 7. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 6. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_navss_to_ac_non_safe_stog_0_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_FW_TO_J7AM_FW_P2P_BRIDGE_FW_TO_J7AM_FW_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_navss_to_ac_non_safe_stog_0_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_1_pend" "0,1" newline bitfld.long 0x4 0. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_edc_ctrl_pend" "0,1" line.long 0x8 "REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 31. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 30. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 29. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 28. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 27. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x8 26. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 25. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 24. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 23. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 22. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 21. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 20. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 18. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 17. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 16. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x8 15. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 14. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 13. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 12. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 11. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" line.long 0xC "REGS_sec_status_reg2,Interrupt Status Register 2" bitfld.long 0xC 5. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0xC 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 3. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 2. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 1. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 0. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x80++0xB line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 30. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_navss_to_ac_non_safe_stog_0_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 25. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_2_clk_edc_ctrl_cbass_int_main_SYSCLK0_2_busecc_pend" "0,1" newline bitfld.long 0x0 21. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SCR_J7AM_AC_CFG_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_scr_j7am_ac_cfg_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 16. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 15. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 14. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_0_pend" "0,1" newline bitfld.long 0x0 13. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 9. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 8. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 7. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 6. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_navss_to_ac_non_safe_stog_0_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_FW_TO_J7AM_FW_P2P_BRIDGE_FW_TO_J7AM_FW_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 3. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 2. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_navss_to_ac_non_safe_stog_0_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_1_pend" "0,1" newline bitfld.long 0x0 0. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_edc_ctrl_pend" "0,1" line.long 0x4 "REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 31. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 30. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 29. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 28. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 27. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x4 26. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 25. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 23. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 22. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 21. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 20. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 18. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 17. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 16. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x4 15. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 14. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 13. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 12. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 11. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" line.long 0x8 "REGS_sec_enable_set_reg2,Interrupt Enable Set Register 2" bitfld.long 0x8 5. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x8 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 3. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 2. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 1. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 0. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0xC0++0xB line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 30. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_navss_to_ac_non_safe_stog_0_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 25. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_2_clk_edc_ctrl_cbass_int_main_SYSCLK0_2_busecc_pend" "0,1" newline bitfld.long 0x0 21. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SCR_J7AM_AC_CFG_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_scr_j7am_ac_cfg_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 16. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 15. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 14. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_0_pend" "0,1" newline bitfld.long 0x0 13. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 9. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 8. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 7. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 6. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_navss_to_ac_non_safe_stog_0_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_FW_TO_J7AM_FW_P2P_BRIDGE_FW_TO_J7AM_FW_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 3. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 2. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_navss_to_ac_non_safe_stog_0_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_1_pend" "0,1" newline bitfld.long 0x0 0. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_edc_ctrl_pend" "0,1" line.long 0x4 "REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 31. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 30. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 29. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 28. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 27. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x4 26. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 25. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 23. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 22. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 21. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 20. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 18. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 17. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 16. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x4 15. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 14. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 13. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 12. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 11. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" line.long 0x8 "REGS_sec_enable_clr_reg2,Interrupt Enable Clear Register 2" bitfld.long 0x8 5. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x8 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 3. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 2. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 1. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 0. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x13C++0xF line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 30. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 29. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_non_safe_cbass_0_j7am_ac_non_safe_cbass_main_SYSCLK0_1_clk_edc_ctrl_cbass_int_main_SYSCLK0_1_busecc_pend" "0,1" newline bitfld.long 0x4 27. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_navss_to_ac_non_safe_stog_0_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 25. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_cbass_default_err_j7am_ac_cfg_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 22. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_2_clk_edc_ctrl_cbass_int_main_SYSCLK0_2_busecc_pend" "0,1" newline bitfld.long 0x4 21. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SCR_J7AM_AC_CFG_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_scr_j7am_ac_cfg_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 16. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 15. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 14. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_0_pend" "0,1" newline bitfld.long 0x4 13. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 9. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_merger_cbass_0_j7am_ac_merger_cbass_main_SYSCLK0_1_clk_edc_ctrl_cbass_int_main_SYSCLK0_1_busecc_pend" "0,1" newline bitfld.long 0x4 8. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 7. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 6. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_navss_to_ac_non_safe_stog_0_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_FW_TO_J7AM_FW_P2P_BRIDGE_FW_TO_J7AM_FW_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_navss_to_ac_non_safe_stog_0_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_1_pend" "0,1" newline bitfld.long 0x4 0. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_edc_ctrl_pend" "0,1" line.long 0x8 "REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 31. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 30. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 29. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 28. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 27. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x8 26. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 25. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 24. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 23. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 22. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 21. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 20. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 18. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 17. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 16. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x8 15. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 14. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 13. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 12. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 11. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" line.long 0xC "REGS_ded_status_reg2,Interrupt Status Register 2" bitfld.long 0xC 5. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0xC 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 3. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 2. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 1. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 0. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x180++0xB line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 30. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_navss_to_ac_non_safe_stog_0_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 25. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_2_clk_edc_ctrl_cbass_int_main_SYSCLK0_2_busecc_pend" "0,1" newline bitfld.long 0x0 21. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SCR_J7AM_AC_CFG_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_scr_j7am_ac_cfg_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 16. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 15. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 14. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_0_pend" "0,1" newline bitfld.long 0x0 13. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 9. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 8. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 7. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 6. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_navss_to_ac_non_safe_stog_0_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_FW_TO_J7AM_FW_P2P_BRIDGE_FW_TO_J7AM_FW_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 3. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 2. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_navss_to_ac_non_safe_stog_0_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_1_pend" "0,1" newline bitfld.long 0x0 0. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_edc_ctrl_pend" "0,1" line.long 0x4 "REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 31. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 30. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 29. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 28. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 27. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x4 26. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 25. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 23. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 22. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 21. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 20. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 18. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 17. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 16. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x4 15. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 14. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 13. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 12. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 11. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" line.long 0x8 "REGS_ded_enable_set_reg2,Interrupt Enable Set Register 2" bitfld.long 0x8 5. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x8 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 3. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 2. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 1. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 0. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x1C0++0xB line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 30. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_navss_to_ac_non_safe_stog_0_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 25. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_2_clk_edc_ctrl_cbass_int_main_SYSCLK0_2_busecc_pend" "0,1" newline bitfld.long 0x0 21. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SCR_J7AM_AC_CFG_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_scr_j7am_ac_cfg_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 16. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 15. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 14. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_0_pend" "0,1" newline bitfld.long 0x0 13. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 9. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 8. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 7. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 6. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_navss_to_ac_non_safe_stog_0_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_FW_TO_J7AM_FW_P2P_BRIDGE_FW_TO_J7AM_FW_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 3. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 2. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_navss_to_ac_non_safe_stog_0_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_1_pend" "0,1" newline bitfld.long 0x0 0. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_edc_ctrl_pend" "0,1" line.long 0x4 "REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 31. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 30. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 29. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 28. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 27. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x4 26. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 25. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 23. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 22. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 21. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 20. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 18. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 17. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 16. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x4 15. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 14. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 13. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 12. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 11. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" line.long 0x8 "REGS_ded_enable_clr_reg2,Interrupt Enable Clear Register 2" bitfld.long 0x8 5. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x8 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 3. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 2. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 1. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 0. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "ECC_AGGR9_ECC_AGGR (ECC_AGGR9_ECC_AGGR)" base ad:0x2AF9000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xF line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 30. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 29. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_non_safe_cbass_0_j7am_ac_non_safe_cbass_main_SYSCLK0_1_clk_edc_ctrl_cbass_int_main_SYSCLK0_1_busecc_pend" "0,1" newline bitfld.long 0x4 27. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_navss_to_ac_non_safe_stog_0_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 25. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_cbass_default_err_j7am_ac_cfg_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 22. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_2_clk_edc_ctrl_cbass_int_main_SYSCLK0_2_busecc_pend" "0,1" newline bitfld.long 0x4 21. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SCR_J7AM_AC_CFG_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_scr_j7am_ac_cfg_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 16. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 15. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 14. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_0_pend" "0,1" newline bitfld.long 0x4 13. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 9. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_merger_cbass_0_j7am_ac_merger_cbass_main_SYSCLK0_1_clk_edc_ctrl_cbass_int_main_SYSCLK0_1_busecc_pend" "0,1" newline bitfld.long 0x4 8. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 7. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 6. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_navss_to_ac_non_safe_stog_0_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_FW_TO_J7AM_FW_P2P_BRIDGE_FW_TO_J7AM_FW_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_navss_to_ac_non_safe_stog_0_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_1_pend" "0,1" newline bitfld.long 0x4 0. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_edc_ctrl_pend" "0,1" line.long 0x8 "REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 31. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 30. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 29. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 28. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 27. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x8 26. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 25. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 24. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 23. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 22. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 21. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 20. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 18. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 17. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 16. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x8 15. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 14. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 13. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 12. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 11. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" line.long 0xC "REGS_sec_status_reg2,Interrupt Status Register 2" bitfld.long 0xC 5. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0xC 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 3. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 2. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 1. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 0. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x80++0xB line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 30. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_navss_to_ac_non_safe_stog_0_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 25. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_2_clk_edc_ctrl_cbass_int_main_SYSCLK0_2_busecc_pend" "0,1" newline bitfld.long 0x0 21. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SCR_J7AM_AC_CFG_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_scr_j7am_ac_cfg_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 16. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 15. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 14. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_0_pend" "0,1" newline bitfld.long 0x0 13. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 9. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 8. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 7. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 6. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_navss_to_ac_non_safe_stog_0_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_FW_TO_J7AM_FW_P2P_BRIDGE_FW_TO_J7AM_FW_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 3. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 2. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_navss_to_ac_non_safe_stog_0_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_1_pend" "0,1" newline bitfld.long 0x0 0. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_edc_ctrl_pend" "0,1" line.long 0x4 "REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 31. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 30. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 29. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 28. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 27. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x4 26. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 25. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 23. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 22. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 21. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 20. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 18. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 17. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 16. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x4 15. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 14. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 13. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 12. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 11. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" line.long 0x8 "REGS_sec_enable_set_reg2,Interrupt Enable Set Register 2" bitfld.long 0x8 5. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x8 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 3. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 2. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 1. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 0. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0xC0++0xB line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 30. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_navss_to_ac_non_safe_stog_0_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 25. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_2_clk_edc_ctrl_cbass_int_main_SYSCLK0_2_busecc_pend" "0,1" newline bitfld.long 0x0 21. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SCR_J7AM_AC_CFG_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_scr_j7am_ac_cfg_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 16. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 15. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 14. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_0_pend" "0,1" newline bitfld.long 0x0 13. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 9. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 8. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 7. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 6. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_navss_to_ac_non_safe_stog_0_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_FW_TO_J7AM_FW_P2P_BRIDGE_FW_TO_J7AM_FW_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 3. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 2. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_navss_to_ac_non_safe_stog_0_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_1_pend" "0,1" newline bitfld.long 0x0 0. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_edc_ctrl_pend" "0,1" line.long 0x4 "REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 31. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 30. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 29. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 28. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 27. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x4 26. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 25. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 23. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 22. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 21. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 20. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 18. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 17. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 16. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x4 15. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 14. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 13. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 12. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 11. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" line.long 0x8 "REGS_sec_enable_clr_reg2,Interrupt Enable Clear Register 2" bitfld.long 0x8 5. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x8 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 3. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 2. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 1. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 0. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x13C++0xF line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 30. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 29. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_non_safe_cbass_0_j7am_ac_non_safe_cbass_main_SYSCLK0_1_clk_edc_ctrl_cbass_int_main_SYSCLK0_1_busecc_pend" "0,1" newline bitfld.long 0x4 27. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_navss_to_ac_non_safe_stog_0_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 25. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_cbass_default_err_j7am_ac_cfg_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 22. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_2_clk_edc_ctrl_cbass_int_main_SYSCLK0_2_busecc_pend" "0,1" newline bitfld.long 0x4 21. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SCR_J7AM_AC_CFG_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_scr_j7am_ac_cfg_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 16. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 15. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 14. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_0_pend" "0,1" newline bitfld.long 0x4 13. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 9. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_PEND,Interrupt Pending Status for Ij7am_ac_merger_cbass_0_j7am_ac_merger_cbass_main_SYSCLK0_1_clk_edc_ctrl_cbass_int_main_SYSCLK0_1_busecc_pend" "0,1" newline bitfld.long 0x4 8. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 7. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 6. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_navss_to_ac_non_safe_stog_0_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_FW_TO_J7AM_FW_P2P_BRIDGE_FW_TO_J7AM_FW_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_navss_to_ac_non_safe_stog_0_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_PEND,Interrupt Pending Status for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_1_pend" "0,1" newline bitfld.long 0x4 0. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_edc_ctrl_pend" "0,1" line.long 0x8 "REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 31. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 30. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 29. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 28. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 27. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x8 26. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 25. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 24. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 23. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 22. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 21. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 20. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 18. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 17. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 16. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe2_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x8 15. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 14. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 13. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 12. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 11. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" line.long 0xC "REGS_ded_status_reg2,Interrupt Status Register 2" bitfld.long 0xC 5. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0xC 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 3. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 2. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 1. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 0. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x180++0xB line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 30. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_navss_to_ac_non_safe_stog_0_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 25. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_2_clk_edc_ctrl_cbass_int_main_SYSCLK0_2_busecc_pend" "0,1" newline bitfld.long 0x0 21. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SCR_J7AM_AC_CFG_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_scr_j7am_ac_cfg_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 16. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 15. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 14. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_0_pend" "0,1" newline bitfld.long 0x0 13. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 9. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 8. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 7. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 6. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_navss_to_ac_non_safe_stog_0_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_FW_TO_J7AM_FW_P2P_BRIDGE_FW_TO_J7AM_FW_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 3. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 2. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_navss_to_ac_non_safe_stog_0_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_1_pend" "0,1" newline bitfld.long 0x0 0. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_edc_ctrl_pend" "0,1" line.long 0x4 "REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 31. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 30. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 29. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 28. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 27. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x4 26. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 25. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 23. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 22. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 21. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 20. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 18. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 17. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 16. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe2_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x4 15. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 14. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 13. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 12. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 11. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" line.long 0x8 "REGS_ded_enable_set_reg2,Interrupt Enable Set Register 2" bitfld.long 0x8 5. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x8 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 3. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 2. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 1. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 0. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x1C0++0xB line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 30. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_navss_to_ac_non_safe_stog_0_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 25. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_J7AM_AC_CFG_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_2_clk_edc_ctrl_cbass_int_main_SYSCLK0_2_busecc_pend" "0,1" newline bitfld.long 0x0 21. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_AC_CFG_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "IJ7AM_AC_CFG_NON_SAFE_CBASS_0_J7AM_AC_CFG_NON_SAFE_CBASS_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_AC_CFG_TO_B_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SCR_J7AM_AC_CFG_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_scr_j7am_ac_cfg_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 16. "IJ7AM_AC_CFG_TO_QM_VBUSM_L0_STOG_2_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_qm_vbusm_l0_stog_2_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 15. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 14. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_0_pend" "0,1" newline bitfld.long 0x0 13. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_J7AM_AC_CFG_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 9. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 8. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 7. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 6. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_navss_to_ac_non_safe_stog_0_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_FW_TO_J7AM_FW_P2P_BRIDGE_FW_TO_J7AM_FW_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 3. "IJ7AM_AC_CBASS_MAIN_FW_CBASS_0_J7AM_AC_CBASS_MAIN_FW_CBASS_AC_CFG_CBASS_DMSC_SLV_P2P_BRIDGE_AC_CFG_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 2. "IJ7AM_NAVSS_TO_AC_NON_SAFE_STOG_0_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_navss_to_ac_non_safe_stog_0_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_cbass_0_j7am_ac_cfg_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_1_pend" "0,1" newline bitfld.long 0x0 0. "IJ7AM_AC_CFG_TO_B_VBUSM_L0_STOG_1_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ac_cfg_to_b_vbusm_l0_stog_1_edc_ctrl_pend" "0,1" line.long 0x4 "REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 31. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 30. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 29. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 28. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 27. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x4 26. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 25. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 23. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 22. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 21. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 20. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "IJ7AM_HC_PIPE2_PHYS__IHC2_TO_RC_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Ihc2_to_rc_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 18. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 17. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 16. "IJ7AM_HC_PIPE2_PHYS__IRC_TO_HC_CFG_P2P_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe2_phys__Irc_to_hc_cfg_p2p_busecc_pend" "0,1" newline bitfld.long 0x4 15. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 14. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 13. "IJ7AM_AC_NON_SAFE_CBASS_0_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_J7AM_AC_NON_SAFE_CBASS_INAVSS512J7AM_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 12. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 11. "IJ7AM_AC_MERGER_CBASS_0_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_J7AM_AC_MERGER_CBASS_INAVSS512J7AM_MAIN_0_AC_DDR2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_J7AM_AC_CFG_CBASS_EXPORT_J7AM_AC_CFG_TO_QM_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_BR_BR_SCRM_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRM_32B_CLK2_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_J7AM_AC_CFG_CBASS_SCRM_32B_CLK2_MAIN_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_1_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_NAVSS2AC_0_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_J7AM_AC_CFG_CBASS_SCRP_32B_CLK4_DIAG_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_P2P_BRIDGE_IJ7AM_MAIN_AC_ECC_AGGR_MAIN_AC_9_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" line.long 0x8 "REGS_ded_enable_clr_reg2,Interrupt Enable Clear Register 2" bitfld.long 0x8 5. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x8 4. "IJ7AM_AC_CFG_CBASS_0_J7AM_AC_CFG_CBASS_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_M2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_ACCFG2ACCFG_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 3. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 2. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 1. "IJ7AM_HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Ihc2_to_rc_vbusm_l0_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 0. "IJ7AM_HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_J7AM_128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_hc_pipe3_phys__Irc_to_hc2_vbusm_l1_j7am_128b_m2m_retime_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "ECC_AGGR10_ECC_AGGR (ECC_AGGR10_ECC_AGGR)" base ad:0x2AFA000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x4 30. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x4 29. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_ERR_SCR_J7AM_MVO_CC_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_err_scr_j7am_mvo_cc_fw_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 28. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 27. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_J7AM_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_cbass_default_err_j7am_mvo_cc_fw_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 26. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_J7AM_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_dmsc_fw_scr_scr_j7am_mvo_cc_fw_cbass_dmsc_fw_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 25. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_udmass_cbass_dmsc_slv_p2p_bridge_udmass_cbass_dmsc_slv_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 24. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_udmass_cbass_dmsc_slv_p2p_bridge_udmass_cbass_dmsc_slv_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 23. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_modss_dmsc_slv_p2p_bridge_modss_dmsc_slv_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 22. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_modss_dmsc_slv_p2p_bridge_modss_dmsc_slv_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 21. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_virtss_dmsc_slv_p2p_bridge_virtss_dmsc_slv_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 20. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_virtss_dmsc_slv_p2p_bridge_virtss_dmsc_slv_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 19. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_BCDMA0_CRED_DMSC_P2P_BRIDGE_BCDMA0_CRED_DMSC_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_bcdma0_cred_dmsc_p2p_bridge_bcdma0_cred_dmsc_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 18. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_BCDMA0_CRED_DMSC_P2P_BRIDGE_BCDMA0_CRED_DMSC_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_bcdma0_cred_dmsc_p2p_bridge_bcdma0_cred_dmsc_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 17. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_J7AM_FW_TO_FW_P2P_BRIDGE_J7AM_FW_TO_FW_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_j7am_fw_to_fw_p2p_bridge_j7am_fw_to_fw_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 16. "VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_PEND,Interrupt Pending Status for vdc_j7_nav_nb_ecc_aggr_src_nb_ecc_aggr_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x4 15. "VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_ecc_aggr_src_nb_ecc_aggr_cfg_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x4 14. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV4_SRC_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_src_nb_slv4_src_vbuss_pend" "0,1" newline bitfld.long 0x4 13. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_src_nb_slv3_src_vbuss_pend" "0,1" newline bitfld.long 0x4 12. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_src_nb_slv2_src_vbuss_pend" "0,1" newline bitfld.long 0x4 11. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_src_nb_slv1_src_vbuss_pend" "0,1" newline bitfld.long 0x4 10. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_src_nb_slv0_src_vbuss_pend" "0,1" newline bitfld.long 0x4 9. "VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_mst0_dst_nb_mst0_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 8. "VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_mst0_dst_nb_mst0_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 7. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_PEND,Interrupt Pending Status for vdc_data_vbusm_64b_dst_msmc_gic_mem_wr_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 6. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_PEND,Interrupt Pending Status for vdc_data_vbusm_64b_dst_msmc_gic_mem_wr_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 5. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_PEND,Interrupt Pending Status for vdc_data_vbusm_64b_dst_msmc_gic_mem_rd_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 4. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_PEND,Interrupt Pending Status for vdc_data_vbusm_64b_dst_msmc_gic_mem_rd_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 3. "VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_PEND,Interrupt Pending Status for vdc_cc_soc_dmsc_vbusp_32b_src_msmc_vbusp_dmsc_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x4 2. "VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_PEND,Interrupt Pending Status for vdc_cc_soc_dmsc_vbusp_32b_src_msmc_vbusp_dmsc_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x4 1. "VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_PEND,Interrupt Pending Status for vdc_cc_soc_cfg_vbusp_32b_src_msmc_vbusp_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x4 0. "VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_PEND,Interrupt Pending Status for vdc_cc_soc_cfg_vbusp_32b_src_msmc_vbusp_cfg_m2m_src_vbuss_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x0 30. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x0 29. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_ERR_SCR_J7AM_MVO_CC_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_err_scr_j7am_mvo_cc_fw_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 28. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 27. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_J7AM_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_J7AM_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_dmsc_fw_scr_scr_j7am_mvo_cc_fw_cbass_dmsc_fw_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 25. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_modss_dmsc_slv_p2p_bridge_modss_dmsc_slv_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 22. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_modss_dmsc_slv_p2p_bridge_modss_dmsc_slv_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 21. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_virtss_dmsc_slv_p2p_bridge_virtss_dmsc_slv_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 20. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_virtss_dmsc_slv_p2p_bridge_virtss_dmsc_slv_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 19. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_BCDMA0_CRED_DMSC_P2P_BRIDGE_BCDMA0_CRED_DMSC_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_bcdma0_cred_dmsc_p2p_bridge_bcdma0_cred_dmsc_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 18. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_BCDMA0_CRED_DMSC_P2P_BRIDGE_BCDMA0_CRED_DMSC_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_bcdma0_cred_dmsc_p2p_bridge_bcdma0_cred_dmsc_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 17. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_J7AM_FW_TO_FW_P2P_BRIDGE_J7AM_FW_TO_FW_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_j7am_fw_to_fw_p2p_bridge_j7am_fw_to_fw_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 16. "VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_ecc_aggr_src_nb_ecc_aggr_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 15. "VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_ecc_aggr_src_nb_ecc_aggr_cfg_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 14. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV4_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_src_nb_slv4_src_vbuss_pend" "0,1" newline bitfld.long 0x0 13. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_src_nb_slv3_src_vbuss_pend" "0,1" newline bitfld.long 0x0 12. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_src_nb_slv2_src_vbuss_pend" "0,1" newline bitfld.long 0x0 11. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_src_nb_slv1_src_vbuss_pend" "0,1" newline bitfld.long 0x0 10. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_src_nb_slv0_src_vbuss_pend" "0,1" newline bitfld.long 0x0 9. "VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_mst0_dst_nb_mst0_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 8. "VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_mst0_dst_nb_mst0_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 7. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_data_vbusm_64b_dst_msmc_gic_mem_wr_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 6. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_data_vbusm_64b_dst_msmc_gic_mem_wr_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 5. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_data_vbusm_64b_dst_msmc_gic_mem_rd_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 4. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_data_vbusm_64b_dst_msmc_gic_mem_rd_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 3. "VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vdc_cc_soc_dmsc_vbusp_32b_src_msmc_vbusp_dmsc_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 2. "VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_cc_soc_dmsc_vbusp_32b_src_msmc_vbusp_dmsc_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 1. "VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vdc_cc_soc_cfg_vbusp_32b_src_msmc_vbusp_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 0. "VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_cc_soc_cfg_vbusp_32b_src_msmc_vbusp_cfg_m2m_src_vbuss_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x0 30. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x0 29. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_ERR_SCR_J7AM_MVO_CC_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_err_scr_j7am_mvo_cc_fw_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 28. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 27. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_J7AM_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_J7AM_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_modss_dmsc_slv_p2p_bridge_modss_dmsc_slv_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 22. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_modss_dmsc_slv_p2p_bridge_modss_dmsc_slv_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 21. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_virtss_dmsc_slv_p2p_bridge_virtss_dmsc_slv_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 20. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_virtss_dmsc_slv_p2p_bridge_virtss_dmsc_slv_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 19. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_BCDMA0_CRED_DMSC_P2P_BRIDGE_BCDMA0_CRED_DMSC_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_bcdma0_cred_dmsc_p2p_bridge_bcdma0_cred_dmsc_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 18. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_BCDMA0_CRED_DMSC_P2P_BRIDGE_BCDMA0_CRED_DMSC_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_bcdma0_cred_dmsc_p2p_bridge_bcdma0_cred_dmsc_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 17. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_J7AM_FW_TO_FW_P2P_BRIDGE_J7AM_FW_TO_FW_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_j7am_fw_to_fw_p2p_bridge_j7am_fw_to_fw_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 16. "VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_ecc_aggr_src_nb_ecc_aggr_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 15. "VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_ecc_aggr_src_nb_ecc_aggr_cfg_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 14. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV4_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_src_nb_slv4_src_vbuss_pend" "0,1" newline bitfld.long 0x0 13. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_src_nb_slv3_src_vbuss_pend" "0,1" newline bitfld.long 0x0 12. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_src_nb_slv2_src_vbuss_pend" "0,1" newline bitfld.long 0x0 11. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_src_nb_slv1_src_vbuss_pend" "0,1" newline bitfld.long 0x0 10. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_src_nb_slv0_src_vbuss_pend" "0,1" newline bitfld.long 0x0 9. "VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_mst0_dst_nb_mst0_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 8. "VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_mst0_dst_nb_mst0_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 7. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_data_vbusm_64b_dst_msmc_gic_mem_wr_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 6. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_data_vbusm_64b_dst_msmc_gic_mem_wr_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 5. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_data_vbusm_64b_dst_msmc_gic_mem_rd_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 4. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_data_vbusm_64b_dst_msmc_gic_mem_rd_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 3. "VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vdc_cc_soc_dmsc_vbusp_32b_src_msmc_vbusp_dmsc_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 2. "VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_cc_soc_dmsc_vbusp_32b_src_msmc_vbusp_dmsc_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 1. "VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vdc_cc_soc_cfg_vbusp_32b_src_msmc_vbusp_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 0. "VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_cc_soc_cfg_vbusp_32b_src_msmc_vbusp_cfg_m2m_src_vbuss_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x4 30. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x4 29. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_ERR_SCR_J7AM_MVO_CC_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_err_scr_j7am_mvo_cc_fw_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 28. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 27. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_J7AM_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_cbass_default_err_j7am_mvo_cc_fw_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 26. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_J7AM_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_dmsc_fw_scr_scr_j7am_mvo_cc_fw_cbass_dmsc_fw_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 25. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_udmass_cbass_dmsc_slv_p2p_bridge_udmass_cbass_dmsc_slv_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 24. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_udmass_cbass_dmsc_slv_p2p_bridge_udmass_cbass_dmsc_slv_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 23. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_modss_dmsc_slv_p2p_bridge_modss_dmsc_slv_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 22. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_modss_dmsc_slv_p2p_bridge_modss_dmsc_slv_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 21. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_virtss_dmsc_slv_p2p_bridge_virtss_dmsc_slv_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 20. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_virtss_dmsc_slv_p2p_bridge_virtss_dmsc_slv_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 19. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_BCDMA0_CRED_DMSC_P2P_BRIDGE_BCDMA0_CRED_DMSC_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_bcdma0_cred_dmsc_p2p_bridge_bcdma0_cred_dmsc_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 18. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_BCDMA0_CRED_DMSC_P2P_BRIDGE_BCDMA0_CRED_DMSC_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_bcdma0_cred_dmsc_p2p_bridge_bcdma0_cred_dmsc_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 17. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_J7AM_FW_TO_FW_P2P_BRIDGE_J7AM_FW_TO_FW_BRIDGE_BUSECC_PEND,Interrupt Pending Status for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_j7am_fw_to_fw_p2p_bridge_j7am_fw_to_fw_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 16. "VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_PEND,Interrupt Pending Status for vdc_j7_nav_nb_ecc_aggr_src_nb_ecc_aggr_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x4 15. "VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_ecc_aggr_src_nb_ecc_aggr_cfg_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x4 14. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV4_SRC_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_src_nb_slv4_src_vbuss_pend" "0,1" newline bitfld.long 0x4 13. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_src_nb_slv3_src_vbuss_pend" "0,1" newline bitfld.long 0x4 12. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_src_nb_slv2_src_vbuss_pend" "0,1" newline bitfld.long 0x4 11. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_src_nb_slv1_src_vbuss_pend" "0,1" newline bitfld.long 0x4 10. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_src_nb_slv0_src_vbuss_pend" "0,1" newline bitfld.long 0x4 9. "VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_mst0_dst_nb_mst0_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 8. "VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_mst0_dst_nb_mst0_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 7. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_PEND,Interrupt Pending Status for vdc_data_vbusm_64b_dst_msmc_gic_mem_wr_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 6. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_PEND,Interrupt Pending Status for vdc_data_vbusm_64b_dst_msmc_gic_mem_wr_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 5. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_PEND,Interrupt Pending Status for vdc_data_vbusm_64b_dst_msmc_gic_mem_rd_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 4. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_PEND,Interrupt Pending Status for vdc_data_vbusm_64b_dst_msmc_gic_mem_rd_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 3. "VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_PEND,Interrupt Pending Status for vdc_cc_soc_dmsc_vbusp_32b_src_msmc_vbusp_dmsc_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x4 2. "VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_PEND,Interrupt Pending Status for vdc_cc_soc_dmsc_vbusp_32b_src_msmc_vbusp_dmsc_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x4 1. "VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_PEND,Interrupt Pending Status for vdc_cc_soc_cfg_vbusp_32b_src_msmc_vbusp_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x4 0. "VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_PEND,Interrupt Pending Status for vdc_cc_soc_cfg_vbusp_32b_src_msmc_vbusp_cfg_m2m_src_vbuss_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x0 30. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x0 29. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_ERR_SCR_J7AM_MVO_CC_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_err_scr_j7am_mvo_cc_fw_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 28. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 27. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_J7AM_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_J7AM_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_dmsc_fw_scr_scr_j7am_mvo_cc_fw_cbass_dmsc_fw_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 25. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_modss_dmsc_slv_p2p_bridge_modss_dmsc_slv_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 22. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_modss_dmsc_slv_p2p_bridge_modss_dmsc_slv_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 21. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_virtss_dmsc_slv_p2p_bridge_virtss_dmsc_slv_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 20. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_virtss_dmsc_slv_p2p_bridge_virtss_dmsc_slv_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 19. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_BCDMA0_CRED_DMSC_P2P_BRIDGE_BCDMA0_CRED_DMSC_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_bcdma0_cred_dmsc_p2p_bridge_bcdma0_cred_dmsc_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 18. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_BCDMA0_CRED_DMSC_P2P_BRIDGE_BCDMA0_CRED_DMSC_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_bcdma0_cred_dmsc_p2p_bridge_bcdma0_cred_dmsc_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 17. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_J7AM_FW_TO_FW_P2P_BRIDGE_J7AM_FW_TO_FW_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_j7am_fw_to_fw_p2p_bridge_j7am_fw_to_fw_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 16. "VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_ecc_aggr_src_nb_ecc_aggr_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 15. "VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_ecc_aggr_src_nb_ecc_aggr_cfg_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 14. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV4_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_src_nb_slv4_src_vbuss_pend" "0,1" newline bitfld.long 0x0 13. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_src_nb_slv3_src_vbuss_pend" "0,1" newline bitfld.long 0x0 12. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_src_nb_slv2_src_vbuss_pend" "0,1" newline bitfld.long 0x0 11. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_src_nb_slv1_src_vbuss_pend" "0,1" newline bitfld.long 0x0 10. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_src_nb_slv0_src_vbuss_pend" "0,1" newline bitfld.long 0x0 9. "VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_mst0_dst_nb_mst0_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 8. "VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_mst0_dst_nb_mst0_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 7. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_data_vbusm_64b_dst_msmc_gic_mem_wr_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 6. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_data_vbusm_64b_dst_msmc_gic_mem_wr_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 5. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_data_vbusm_64b_dst_msmc_gic_mem_rd_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 4. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_data_vbusm_64b_dst_msmc_gic_mem_rd_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 3. "VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vdc_cc_soc_dmsc_vbusp_32b_src_msmc_vbusp_dmsc_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 2. "VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_cc_soc_dmsc_vbusp_32b_src_msmc_vbusp_dmsc_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 1. "VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vdc_cc_soc_cfg_vbusp_32b_src_msmc_vbusp_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 0. "VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_cc_soc_cfg_vbusp_32b_src_msmc_vbusp_cfg_m2m_src_vbuss_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x0 30. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1" newline bitfld.long 0x0 29. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_ERR_SCR_J7AM_MVO_CC_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_err_scr_j7am_mvo_cc_fw_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 28. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 27. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_J7AM_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_J7AM_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_modss_dmsc_slv_p2p_bridge_modss_dmsc_slv_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 22. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_modss_dmsc_slv_p2p_bridge_modss_dmsc_slv_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 21. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_virtss_dmsc_slv_p2p_bridge_virtss_dmsc_slv_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 20. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_virtss_dmsc_slv_p2p_bridge_virtss_dmsc_slv_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 19. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_BCDMA0_CRED_DMSC_P2P_BRIDGE_BCDMA0_CRED_DMSC_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_bcdma0_cred_dmsc_p2p_bridge_bcdma0_cred_dmsc_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 18. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_BCDMA0_CRED_DMSC_P2P_BRIDGE_BCDMA0_CRED_DMSC_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_bcdma0_cred_dmsc_p2p_bridge_bcdma0_cred_dmsc_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 17. "IRC_FW_CBASS_J7AM_MVO_CC_FW_CBASS_J7AM_FW_TO_FW_P2P_BRIDGE_J7AM_FW_TO_FW_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Irc_fw_cbass_j7am_mvo_cc_fw_cbass_j7am_fw_to_fw_p2p_bridge_j7am_fw_to_fw_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 16. "VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_ecc_aggr_src_nb_ecc_aggr_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 15. "VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_ecc_aggr_src_nb_ecc_aggr_cfg_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 14. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV4_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_src_nb_slv4_src_vbuss_pend" "0,1" newline bitfld.long 0x0 13. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_src_nb_slv3_src_vbuss_pend" "0,1" newline bitfld.long 0x0 12. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_src_nb_slv2_src_vbuss_pend" "0,1" newline bitfld.long 0x0 11. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_src_nb_slv1_src_vbuss_pend" "0,1" newline bitfld.long 0x0 10. "VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_src_nb_slv0_src_vbuss_pend" "0,1" newline bitfld.long 0x0 9. "VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_mst0_dst_nb_mst0_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 8. "VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_mst0_dst_nb_mst0_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 7. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_data_vbusm_64b_dst_msmc_gic_mem_wr_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 6. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_data_vbusm_64b_dst_msmc_gic_mem_wr_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 5. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_data_vbusm_64b_dst_msmc_gic_mem_rd_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 4. "VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_data_vbusm_64b_dst_msmc_gic_mem_rd_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 3. "VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vdc_cc_soc_dmsc_vbusp_32b_src_msmc_vbusp_dmsc_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 2. "VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_cc_soc_dmsc_vbusp_32b_src_msmc_vbusp_dmsc_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 1. "VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vdc_cc_soc_cfg_vbusp_32b_src_msmc_vbusp_cfg_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 0. "VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_cc_soc_cfg_vbusp_32b_src_msmc_vbusp_cfg_m2m_src_vbuss_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "ECC_AGGR11_ECC_AGGR (ECC_AGGR11_ECC_AGGR)" base ad:0x2AFB000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 23. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x4 22. "J7AM_NAVSS512_NBSS_PSIL_RETIME_BR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_navss512_nbss_psil_retime_br_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 21. "VDC_J7_NAV_NB_SLV_DST_NB_SLV4_M2M_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_dst_nb_slv4_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 20. "VDC_J7_NAV_NB_SLV_DST_NB_SLV4_DST_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_dst_nb_slv4_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 19. "VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_PEND,Interrupt Pending Status for vdc_cc_soc_dmsc_vbusp_32b_dst_msmc_vbusp_dmsc_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 18. "VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_ecc_aggr_dst_nb_ecc_aggr_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 17. "VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_dst_nb_slv2_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 16. "VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_dst_nb_slv2_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 15. "VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_PEND,Interrupt Pending Status for vdc_j7_nav_nb_ecc_aggr_dst_nb_ecc_aggr_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 14. "VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_PEND,Interrupt Pending Status for vdc_cc_soc_cfg_vbusp_32b_dst_msmc_vbusp_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 13. "VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_dst_nb_slv3_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 12. "VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_dst_nb_slv0_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 11. "VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_ecc_aggr_dst_nb_ecc_aggr_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 10. "VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_PEND,Interrupt Pending Status for vdc_data_vbusm_64b_src_msmc_gic_mem_rd_src_vbuss_pend" "0,1" newline bitfld.long 0x4 9. "VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_mst0_src_nb_mst0_src_vbuss_pend" "0,1" newline bitfld.long 0x4 8. "VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_dst_nb_slv3_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 7. "VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_PEND,Interrupt Pending Status for vdc_cc_soc_dmsc_vbusp_32b_dst_msmc_vbusp_dmsc_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 6. "VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_PEND,Interrupt Pending Status for vdc_cc_soc_cfg_vbusp_32b_dst_msmc_vbusp_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 5. "VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_dst_nb_slv0_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 4. "VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_dst_nb_slv1_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 3. "VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_PEND,Interrupt Pending Status for vdc_cc_soc_dmsc_vbusp_32b_dst_msmc_vbusp_dmsc_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 2. "VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_dst_nb_slv1_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 1. "VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_PEND,Interrupt Pending Status for vdc_cc_soc_cfg_vbusp_32b_dst_msmc_vbusp_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 0. "VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_PEND,Interrupt Pending Status for vdc_data_vbusm_64b_src_msmc_gic_mem_wr_src_vbuss_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 23. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x0 22. "J7AM_NAVSS512_NBSS_PSIL_RETIME_BR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_navss512_nbss_psil_retime_br_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 21. "VDC_J7_NAV_NB_SLV_DST_NB_SLV4_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_dst_nb_slv4_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 20. "VDC_J7_NAV_NB_SLV_DST_NB_SLV4_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_dst_nb_slv4_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 19. "VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vdc_cc_soc_dmsc_vbusp_32b_dst_msmc_vbusp_dmsc_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 18. "VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_ecc_aggr_dst_nb_ecc_aggr_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 17. "VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_dst_nb_slv2_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 16. "VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_dst_nb_slv2_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 15. "VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_ecc_aggr_dst_nb_ecc_aggr_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 14. "VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_cc_soc_cfg_vbusp_32b_dst_msmc_vbusp_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 13. "VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_dst_nb_slv3_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 12. "VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_dst_nb_slv0_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 11. "VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_ecc_aggr_dst_nb_ecc_aggr_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 10. "VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_data_vbusm_64b_src_msmc_gic_mem_rd_src_vbuss_pend" "0,1" newline bitfld.long 0x0 9. "VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_mst0_src_nb_mst0_src_vbuss_pend" "0,1" newline bitfld.long 0x0 8. "VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_dst_nb_slv3_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 7. "VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_cc_soc_dmsc_vbusp_32b_dst_msmc_vbusp_dmsc_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 6. "VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vdc_cc_soc_cfg_vbusp_32b_dst_msmc_vbusp_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 5. "VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_dst_nb_slv0_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 4. "VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_dst_nb_slv1_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 3. "VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_cc_soc_dmsc_vbusp_32b_dst_msmc_vbusp_dmsc_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 2. "VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_dst_nb_slv1_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 1. "VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_cc_soc_cfg_vbusp_32b_dst_msmc_vbusp_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_data_vbusm_64b_src_msmc_gic_mem_wr_src_vbuss_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 23. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x0 22. "J7AM_NAVSS512_NBSS_PSIL_RETIME_BR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_navss512_nbss_psil_retime_br_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 21. "VDC_J7_NAV_NB_SLV_DST_NB_SLV4_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_dst_nb_slv4_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 20. "VDC_J7_NAV_NB_SLV_DST_NB_SLV4_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_dst_nb_slv4_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 19. "VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vdc_cc_soc_dmsc_vbusp_32b_dst_msmc_vbusp_dmsc_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 18. "VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_ecc_aggr_dst_nb_ecc_aggr_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 17. "VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_dst_nb_slv2_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 16. "VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_dst_nb_slv2_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 15. "VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_ecc_aggr_dst_nb_ecc_aggr_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 14. "VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_cc_soc_cfg_vbusp_32b_dst_msmc_vbusp_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 13. "VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_dst_nb_slv3_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 12. "VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_dst_nb_slv0_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 11. "VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_ecc_aggr_dst_nb_ecc_aggr_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 10. "VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_data_vbusm_64b_src_msmc_gic_mem_rd_src_vbuss_pend" "0,1" newline bitfld.long 0x0 9. "VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_mst0_src_nb_mst0_src_vbuss_pend" "0,1" newline bitfld.long 0x0 8. "VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_dst_nb_slv3_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 7. "VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_cc_soc_dmsc_vbusp_32b_dst_msmc_vbusp_dmsc_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 6. "VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vdc_cc_soc_cfg_vbusp_32b_dst_msmc_vbusp_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 5. "VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_dst_nb_slv0_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 4. "VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_dst_nb_slv1_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 3. "VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_cc_soc_dmsc_vbusp_32b_dst_msmc_vbusp_dmsc_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 2. "VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_dst_nb_slv1_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 1. "VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_cc_soc_cfg_vbusp_32b_dst_msmc_vbusp_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_data_vbusm_64b_src_msmc_gic_mem_wr_src_vbuss_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 23. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x4 22. "J7AM_NAVSS512_NBSS_PSIL_RETIME_BR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_navss512_nbss_psil_retime_br_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 21. "VDC_J7_NAV_NB_SLV_DST_NB_SLV4_M2M_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_dst_nb_slv4_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 20. "VDC_J7_NAV_NB_SLV_DST_NB_SLV4_DST_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_dst_nb_slv4_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 19. "VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_PEND,Interrupt Pending Status for vdc_cc_soc_dmsc_vbusp_32b_dst_msmc_vbusp_dmsc_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 18. "VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_ecc_aggr_dst_nb_ecc_aggr_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 17. "VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_dst_nb_slv2_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 16. "VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_dst_nb_slv2_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 15. "VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_PEND,Interrupt Pending Status for vdc_j7_nav_nb_ecc_aggr_dst_nb_ecc_aggr_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 14. "VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_PEND,Interrupt Pending Status for vdc_cc_soc_cfg_vbusp_32b_dst_msmc_vbusp_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 13. "VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_dst_nb_slv3_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 12. "VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_dst_nb_slv0_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 11. "VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_ecc_aggr_dst_nb_ecc_aggr_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 10. "VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_PEND,Interrupt Pending Status for vdc_data_vbusm_64b_src_msmc_gic_mem_rd_src_vbuss_pend" "0,1" newline bitfld.long 0x4 9. "VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_mst0_src_nb_mst0_src_vbuss_pend" "0,1" newline bitfld.long 0x4 8. "VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_dst_nb_slv3_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 7. "VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_PEND,Interrupt Pending Status for vdc_cc_soc_dmsc_vbusp_32b_dst_msmc_vbusp_dmsc_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 6. "VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_PEND,Interrupt Pending Status for vdc_cc_soc_cfg_vbusp_32b_dst_msmc_vbusp_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 5. "VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_dst_nb_slv0_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 4. "VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_dst_nb_slv1_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 3. "VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_PEND,Interrupt Pending Status for vdc_cc_soc_dmsc_vbusp_32b_dst_msmc_vbusp_dmsc_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 2. "VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_PEND,Interrupt Pending Status for vdc_j7_nav_nb_slv_dst_nb_slv1_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 1. "VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_PEND,Interrupt Pending Status for vdc_cc_soc_cfg_vbusp_32b_dst_msmc_vbusp_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 0. "VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_PEND,Interrupt Pending Status for vdc_data_vbusm_64b_src_msmc_gic_mem_wr_src_vbuss_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 23. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x0 22. "J7AM_NAVSS512_NBSS_PSIL_RETIME_BR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_navss512_nbss_psil_retime_br_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 21. "VDC_J7_NAV_NB_SLV_DST_NB_SLV4_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_dst_nb_slv4_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 20. "VDC_J7_NAV_NB_SLV_DST_NB_SLV4_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_dst_nb_slv4_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 19. "VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vdc_cc_soc_dmsc_vbusp_32b_dst_msmc_vbusp_dmsc_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 18. "VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_ecc_aggr_dst_nb_ecc_aggr_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 17. "VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_dst_nb_slv2_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 16. "VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_dst_nb_slv2_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 15. "VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_ecc_aggr_dst_nb_ecc_aggr_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 14. "VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_cc_soc_cfg_vbusp_32b_dst_msmc_vbusp_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 13. "VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_dst_nb_slv3_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 12. "VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_dst_nb_slv0_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 11. "VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_ecc_aggr_dst_nb_ecc_aggr_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 10. "VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_data_vbusm_64b_src_msmc_gic_mem_rd_src_vbuss_pend" "0,1" newline bitfld.long 0x0 9. "VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_mst0_src_nb_mst0_src_vbuss_pend" "0,1" newline bitfld.long 0x0 8. "VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_dst_nb_slv3_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 7. "VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_cc_soc_dmsc_vbusp_32b_dst_msmc_vbusp_dmsc_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 6. "VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vdc_cc_soc_cfg_vbusp_32b_dst_msmc_vbusp_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 5. "VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_dst_nb_slv0_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 4. "VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_dst_nb_slv1_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 3. "VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_cc_soc_dmsc_vbusp_32b_dst_msmc_vbusp_dmsc_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 2. "VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_j7_nav_nb_slv_dst_nb_slv1_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 1. "VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_cc_soc_cfg_vbusp_32b_dst_msmc_vbusp_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for vdc_data_vbusm_64b_src_msmc_gic_mem_wr_src_vbuss_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 23. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x0 22. "J7AM_NAVSS512_NBSS_PSIL_RETIME_BR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_navss512_nbss_psil_retime_br_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 21. "VDC_J7_NAV_NB_SLV_DST_NB_SLV4_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_dst_nb_slv4_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 20. "VDC_J7_NAV_NB_SLV_DST_NB_SLV4_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_dst_nb_slv4_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 19. "VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vdc_cc_soc_dmsc_vbusp_32b_dst_msmc_vbusp_dmsc_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 18. "VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_ecc_aggr_dst_nb_ecc_aggr_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 17. "VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_dst_nb_slv2_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 16. "VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_dst_nb_slv2_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 15. "VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_ecc_aggr_dst_nb_ecc_aggr_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 14. "VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_cc_soc_cfg_vbusp_32b_dst_msmc_vbusp_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 13. "VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_dst_nb_slv3_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 12. "VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_dst_nb_slv0_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 11. "VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_ecc_aggr_dst_nb_ecc_aggr_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 10. "VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_data_vbusm_64b_src_msmc_gic_mem_rd_src_vbuss_pend" "0,1" newline bitfld.long 0x0 9. "VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_mst0_src_nb_mst0_src_vbuss_pend" "0,1" newline bitfld.long 0x0 8. "VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_dst_nb_slv3_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 7. "VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_cc_soc_dmsc_vbusp_32b_dst_msmc_vbusp_dmsc_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 6. "VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vdc_cc_soc_cfg_vbusp_32b_dst_msmc_vbusp_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x0 5. "VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_dst_nb_slv0_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 4. "VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_dst_nb_slv1_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 3. "VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_cc_soc_dmsc_vbusp_32b_dst_msmc_vbusp_dmsc_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 2. "VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_j7_nav_nb_slv_dst_nb_slv1_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 1. "VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_cc_soc_cfg_vbusp_32b_dst_msmc_vbusp_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for vdc_data_vbusm_64b_src_msmc_gic_mem_wr_src_vbuss_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree.end tree "ELM0 (ELM0)" base ad:0x5380000 rgroup.long 0x0++0x3 line.long 0x0 "MEM_ELM_REVISION,This register contains the IP revision code." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_0,Read returns 0" newline hexmask.long.byte 0x0 0.--7. 1. "REV_NUMBER,IP revision number [RTL] [7:4] Major revision [3:0] Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "MEM_ELM_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x0 8. "CLOCKACTIVITYOCP,OCP Clock activity when module is in IDLE mode [during wake up mode period]" "0,1" newline bitfld.long 0x0 3.--4. "SIDLEMODE,Slave interface power management [IDLE req/ack control]" "0,1,2,3" newline bitfld.long 0x0 1. "SOFTRESET,Module Software Reset The bit is automatically reset by the hardware [During reads it always returns 0] It has same effect as the OCP Hardware reset" "0,1" newline bitfld.long 0x0 0. "AUTOGATING,Internal OCP clock gating strategy [no module visible impact other than saving power]" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_ELM_SYSSTATUS,Internal Reset monitoring (OCP domain)" bitfld.long 0x0 0. "RESETDONE,Internal Reset monitoring [OCP domain] Undefined since: on HW perspective reset state is 0 on SW user perspective when module is accessible is 1" "0,1" rgroup.long 0x18++0xB line.long 0x0 "MEM_ELM_IRQSTATUS,Interrupt status. This register doubles as a status register for the error location processes." bitfld.long 0x0 8. "PAGE_VALID,Error location status for a full page based on the mask definition Read 0x0: error locations invalid for all polynomials enabled in the ECC_INTERRUPT_MASK register Read 0x1: all error locations valid Write 0x0: no effect Write 0x1: clear.." "0: error locations invalid for all polynomials..,?" newline bitfld.long 0x0 7. "LOC_VALID_7,Error location status for syndrome polynomial 7 Read 0x0: no syndrome processed or process in progress Read 0x1: error location process completed Write 0x0: no effect Write 0x1: clear interrupt" "0: no syndrome processed or process in progress..,?" newline bitfld.long 0x0 6. "LOC_VALID_6,Error location status for syndrome polynomial 6" "0,1" newline bitfld.long 0x0 5. "LOC_VALID_5,Error location status for syndrome polynomial 5" "0,1" newline bitfld.long 0x0 4. "LOC_VALID_4,Error location status for syndrome polynomial 4" "0,1" newline bitfld.long 0x0 3. "LOC_VALID_3,Error location status for syndrome polynomial 3" "0,1" newline bitfld.long 0x0 2. "LOC_VALID_2,Error location status for syndrome polynomial 2" "0,1" newline bitfld.long 0x0 1. "LOC_VALID_1,Error location status for syndrome polynomial 1" "0,1" newline bitfld.long 0x0 0. "LOC_VALID_0,Error location status for syndrome polynomial 0" "0,1" line.long 0x4 "MEM_ELM_IRQENABLE,Interrupt enable" bitfld.long 0x4 8. "PAGE_MASK,Page interrupt mask bit 0: disable interrupt 1: enable interrupt" "0: disable interrupt,1: enable interrupt" newline bitfld.long 0x4 7. "LOCATION_MASK_7,Error location interrupt mask bit for syndrome polynomial 7" "0,1" newline bitfld.long 0x4 6. "LOCATION_MASK_6,Error location interrupt mask bit for syndrome polynomial 6" "0,1" newline bitfld.long 0x4 5. "LOCATION_MASK_5,Error location interrupt mask bit for syndrome polynomial 5" "0,1" newline bitfld.long 0x4 4. "LOCATION_MASK_4,Error location interrupt mask bit for syndrome polynomial 4" "0,1" newline bitfld.long 0x4 3. "LOCATION_MASK_3,Error location interrupt mask bit for syndrome polynomial 3" "0,1" newline bitfld.long 0x4 2. "LOCATION_MASK_2,Error location interrupt mask bit for syndrome polynomial 2" "0,1" newline bitfld.long 0x4 1. "LOCATION_MASK_1,Error location interrupt mask bit for syndrome polynomial 1" "0,1" newline bitfld.long 0x4 0. "LOCATION_MASK_0,Error location interrupt mask bit for syndrome polynomial 0 0: disable interrupt 1: enable interrupt" "0: disable interrupt,1: enable interrupt" line.long 0x8 "MEM_ELM_LOCATION_CONFIG,ECC algorithm parameters" hexmask.long.word 0x8 16.--26. 1. "ECC_SIZE,Maximum size of the buffers for which the error location engine is used in number of nibbles [4-bits entities]" newline bitfld.long 0x8 0.--1. "ECC_BCH_LEVEL,Error correction level 0x0: 4 bits 0x1: 8 bits 0x2: 16 bits 0x3: reserved" "?,?,?,3: reserved" rgroup.long 0x80++0x3 line.long 0x0 "MEM_ELM_PAGE_CTRL,Page definition" bitfld.long 0x0 7. "SECTOR_7,Set to 1 if syndrome polynomial 7 is part of the page in page mode Must be 0 in continuous mode" "0,1" newline bitfld.long 0x0 6. "SECTOR_6,Set to 1 if syndrome polynomial 6 is part of the page in page mode Must be 0 in continuous mode" "0,1" newline bitfld.long 0x0 5. "SECTOR_5,Set to 1 if syndrome polynomial 5 is part of the page in page mode Must be 0 in continuous mode" "0,1" newline bitfld.long 0x0 4. "SECTOR_4,Set to 1 if syndrome polynomial 4 is part of the page in page mode Must be 0 in continuous mode" "0,1" newline bitfld.long 0x0 3. "SECTOR_3,Set to 1 if syndrome polynomial 3 is part of the page in page mode Must be 0 in continuous mode" "0,1" newline bitfld.long 0x0 2. "SECTOR_2,Set to 1 if syndrome polynomial 2 is part of the page in page mode Must be 0 in continuous mode" "0,1" newline bitfld.long 0x0 1. "SECTOR_1,Set to 1 if syndrome polynomial 1 is part of the page in page mode Must be 0 in continuous mode" "0,1" newline bitfld.long 0x0 0. "SECTOR_0,Set to 1 if syndrome polynomial 0 is part of the page in page mode Must be 0 in continuous mode" "0,1" rgroup.long 0x400++0x1B line.long 0x0 "MEM_ELM_SYNDROME_FRAGMENT_0,Input syndrome polynomial bits 0 to 31." hexmask.long 0x0 0.--31. 1. "SYNDROME_0,Syndrome bits 0 to 31" line.long 0x4 "MEM_ELM_SYNDROME_FRAGMENT_1,Input syndrome polynomial bits 32 to 63." hexmask.long 0x4 0.--31. 1. "SYNDROME_1,Syndrome bits 32 to 63" line.long 0x8 "MEM_ELM_SYNDROME_FRAGMENT_2,Input syndrome polynomial bits 64 to 95." hexmask.long 0x8 0.--31. 1. "SYNDROME_2,Syndrome bits 64 to 95" line.long 0xC "MEM_ELM_SYNDROME_FRAGMENT_3,Input syndrome polynomial bits 96 to 127" hexmask.long 0xC 0.--31. 1. "SYNDROME_3,Syndrome bits 96 to 127" line.long 0x10 "MEM_ELM_SYNDROME_FRAGMENT_4,Input syndrome polynomial bits 128 to 159." hexmask.long 0x10 0.--31. 1. "SYNDROME_4,Syndrome bits 128 to 159" line.long 0x14 "MEM_ELM_SYNDROME_FRAGMENT_5,Input syndrome polynomial bits 160 to 191." hexmask.long 0x14 0.--31. 1. "SYNDROME_5,Syndrome bits 160 to 191" line.long 0x18 "MEM_ELM_SYNDROME_FRAGMENT_6,Input syndrome polynomial bits 192 to 207." bitfld.long 0x18 16. "SYNDROME_VALID,Syndrome valid bit 0x0: this syndrome polynomial should not be processed 0x1: this syndrome polynomial must be processed" "0: this syndrome polynomial should not be processed..,?" newline hexmask.long.word 0x18 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" rgroup.long 0x800++0x3 line.long 0x0 "MEM_ELM_LOCATION_STATUS,Exit status for the syndrome polynomial processing" bitfld.long 0x0 8. "ECC_CORRECTABLE,Error location process exit status 0x0: ECC error location process failed Number of errors and error locations are invalid 0x1: all errors were successfully located Number of errors and error locations are valid" "0: ECC error location process failed Number of..,?" newline hexmask.long.byte 0x0 0.--4. 1. "ECC_NB_ERRORS,Number of errors detected and located" rgroup.long 0x880++0x3F line.long 0x0 "MEM_ELM_ERROR_LOCATION_0,Error location register" hexmask.long.word 0x0 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x4 "MEM_ELM_ERROR_LOCATION_1,Error location register" hexmask.long.word 0x4 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x8 "MEM_ELM_ERROR_LOCATION_2,Error location register" hexmask.long.word 0x8 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0xC "MEM_ELM_ERROR_LOCATION_3,Error location register" hexmask.long.word 0xC 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x10 "MEM_ELM_ERROR_LOCATION_4,Error location register" hexmask.long.word 0x10 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x14 "MEM_ELM_ERROR_LOCATION_5,Error location register" hexmask.long.word 0x14 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x18 "MEM_ELM_ERROR_LOCATION_6,Error location register" hexmask.long.word 0x18 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x1C "MEM_ELM_ERROR_LOCATION_7,Error location register" hexmask.long.word 0x1C 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x20 "MEM_ELM_ERROR_LOCATION_8,Error location register" hexmask.long.word 0x20 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x24 "MEM_ELM_ERROR_LOCATION_9,Error location register" hexmask.long.word 0x24 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x28 "MEM_ELM_ERROR_LOCATION_10,Error location register" hexmask.long.word 0x28 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x2C "MEM_ELM_ERROR_LOCATION_11,Error location register" hexmask.long.word 0x2C 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x30 "MEM_ELM_ERROR_LOCATION_12,Error location register" hexmask.long.word 0x30 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x34 "MEM_ELM_ERROR_LOCATION_13,Error location register" hexmask.long.word 0x34 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x38 "MEM_ELM_ERROR_LOCATION_14,Error location register" hexmask.long.word 0x38 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x3C "MEM_ELM_ERROR_LOCATION_15,Error location register" hexmask.long.word 0x3C 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" tree.end tree "EPWM" base ad:0x0 tree "EPWM0_EPWM (EPWM0_EPWM)" base ad:0x3000000 rgroup.word 0x0++0xB line.word 0x0 "EPWM_REGS_TBCTL,Time-Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events:" "0,1,2,3" bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase value.." "0,1" bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7" bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1" bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3" bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1" bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1" bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3" line.word 0x2 "EPWM_REGS_TBSTS,Time-Base Status Register" bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1" bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1" rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset the counter is frozen therefore this bit has no meaning To make this bit meaningful you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1" line.word 0x4 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register" hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits" line.word 0x6 "EPWM_REGS_TBPHS,Time Base Phase Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved." hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal [a] If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base counter is not loaded with.." line.word 0x8 "EPWM_REGS_TBCNT,Time Base Counter Register" hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value Writing to these bits sets the current time-base counter value The update happens as soon as the write occurs The write is NOT synchronized to the time-base clock [TBCLK] and the register.." line.word 0xA "EPWM_REGS_TBPRD,Time Base Period Register" hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter This sets the PWM frequency Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit By default this register is shadowed [a] If TBCTL[PRDLD] = 0 then the shadow is enabled.." rgroup.word 0xE++0x17 line.word 0x0 "EPWM_REGS_CMPCTL,Counter Compare Control Register" rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1" rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self clears.." "0,1" bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1" bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1" bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3" bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3" line.word 0x2 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved." hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h" line.word 0x4 "EPWM_REGS_CMPA,Counter Compare A Register" hexmask.word 0x4 0.--15. 1. "CMPA,The value in the active CMPA register is continuously compared to the time-base counter [TBCNT] When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event This event is sent to the.." line.word 0x6 "EPWM_REGS_CMPB,Counter Compare B Register" hexmask.word 0x6 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter [TBCNT] When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event This event is sent to the.." line.word 0x8 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x8 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3" bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3" bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3" bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3" bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3" bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3" line.word 0xA "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3" bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3" bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3" bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3" bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3" bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3" line.word 0xC "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0xC 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3" bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1" bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3" bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1" bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3" line.word 0xE "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3" bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3" line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms the default is EPWMxA In is.." "0,1,2,3" bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3" bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3" line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register" hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter" line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter" line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register" hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low a one-shot trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the EPWMxA and.." hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low a cycle-by-cycle trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the.." rgroup.word 0x28++0x3 line.word 0x0 "EPWM_REGS_TZCTL,Trip Zone Control Register" bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3" bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3" line.word 0x2 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1" bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1" rgroup.word 0x2C++0x1 line.word 0x0 "EPWM_REGS_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1" bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1" bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag" "0,1" rgroup.word 0x2E++0x7 line.word 0x0 "EPWM_REGS_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1" bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1" bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1" line.word 0x2 "EPWM_REGS_TZFRC,Trip Zone Force Register" bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software" "0,1" bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1" line.word 0x4 "EPWM_REGS_ETSEL,Event Trigger Selection Register" bitfld.word 0x4 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1" bitfld.word 0x4 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7" line.word 0x6 "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x6 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled ETSEL[INT] = 0 or the.." "0,1,2,3" bitfld.word 0x6 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3" rgroup.word 0x36++0x5 line.word 0x0 "EPWM_REGS_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1" line.word 0x2 "EPWM_REGS_ETCLR,Event Trigger Clear Register" bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1" line.word 0x4 "EPWM_REGS_ETFRC,Event Trigger Force Register" bitfld.word 0x4 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1" rgroup.word 0x3C++0x1 line.word 0x0 "EPWM_REGS_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7" bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width" bitfld.word 0x0 0. "CHPEN,PWM-chopping Enable" "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "EPWM_REGS_PID,EHRPWM Peripheral ID Register. The IP revision register is used by software to track features. bugs. and compatibility." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,FUNC" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL version [R] maintained by IP design owner" bitfld.long 0x0 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,CUSTOM" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision [Y]" tree.end tree "EPWM1_EPWM (EPWM1_EPWM)" base ad:0x3010000 rgroup.word 0x0++0xB line.word 0x0 "EPWM_REGS_TBCTL,Time-Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events:" "0,1,2,3" bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase value.." "0,1" bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7" bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1" bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3" bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1" bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1" bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3" line.word 0x2 "EPWM_REGS_TBSTS,Time-Base Status Register" bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1" bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1" rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset the counter is frozen therefore this bit has no meaning To make this bit meaningful you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1" line.word 0x4 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register" hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits" line.word 0x6 "EPWM_REGS_TBPHS,Time Base Phase Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved." hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal [a] If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base counter is not loaded with.." line.word 0x8 "EPWM_REGS_TBCNT,Time Base Counter Register" hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value Writing to these bits sets the current time-base counter value The update happens as soon as the write occurs The write is NOT synchronized to the time-base clock [TBCLK] and the register.." line.word 0xA "EPWM_REGS_TBPRD,Time Base Period Register" hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter This sets the PWM frequency Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit By default this register is shadowed [a] If TBCTL[PRDLD] = 0 then the shadow is enabled.." rgroup.word 0xE++0x17 line.word 0x0 "EPWM_REGS_CMPCTL,Counter Compare Control Register" rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1" rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self clears.." "0,1" bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1" bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1" bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3" bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3" line.word 0x2 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved." hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h" line.word 0x4 "EPWM_REGS_CMPA,Counter Compare A Register" hexmask.word 0x4 0.--15. 1. "CMPA,The value in the active CMPA register is continuously compared to the time-base counter [TBCNT] When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event This event is sent to the.." line.word 0x6 "EPWM_REGS_CMPB,Counter Compare B Register" hexmask.word 0x6 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter [TBCNT] When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event This event is sent to the.." line.word 0x8 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x8 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3" bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3" bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3" bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3" bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3" bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3" line.word 0xA "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3" bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3" bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3" bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3" bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3" bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3" line.word 0xC "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0xC 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3" bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1" bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3" bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1" bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3" line.word 0xE "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3" bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3" line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms the default is EPWMxA In is.." "0,1,2,3" bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3" bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3" line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register" hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter" line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter" line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register" hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low a one-shot trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the EPWMxA and.." hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low a cycle-by-cycle trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the.." rgroup.word 0x28++0x3 line.word 0x0 "EPWM_REGS_TZCTL,Trip Zone Control Register" bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3" bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3" line.word 0x2 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1" bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1" rgroup.word 0x2C++0x1 line.word 0x0 "EPWM_REGS_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1" bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1" bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag" "0,1" rgroup.word 0x2E++0x7 line.word 0x0 "EPWM_REGS_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1" bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1" bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1" line.word 0x2 "EPWM_REGS_TZFRC,Trip Zone Force Register" bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software" "0,1" bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1" line.word 0x4 "EPWM_REGS_ETSEL,Event Trigger Selection Register" bitfld.word 0x4 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1" bitfld.word 0x4 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7" line.word 0x6 "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x6 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled ETSEL[INT] = 0 or the.." "0,1,2,3" bitfld.word 0x6 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3" rgroup.word 0x36++0x5 line.word 0x0 "EPWM_REGS_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1" line.word 0x2 "EPWM_REGS_ETCLR,Event Trigger Clear Register" bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1" line.word 0x4 "EPWM_REGS_ETFRC,Event Trigger Force Register" bitfld.word 0x4 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1" rgroup.word 0x3C++0x1 line.word 0x0 "EPWM_REGS_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7" bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width" bitfld.word 0x0 0. "CHPEN,PWM-chopping Enable" "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "EPWM_REGS_PID,EHRPWM Peripheral ID Register. The IP revision register is used by software to track features. bugs. and compatibility." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,FUNC" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL version [R] maintained by IP design owner" bitfld.long 0x0 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,CUSTOM" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision [Y]" tree.end tree "EPWM2_EPWM (EPWM2_EPWM)" base ad:0x3020000 rgroup.word 0x0++0xB line.word 0x0 "EPWM_REGS_TBCTL,Time-Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events:" "0,1,2,3" bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase value.." "0,1" bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7" bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1" bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3" bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1" bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1" bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3" line.word 0x2 "EPWM_REGS_TBSTS,Time-Base Status Register" bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1" bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1" rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset the counter is frozen therefore this bit has no meaning To make this bit meaningful you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1" line.word 0x4 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register" hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits" line.word 0x6 "EPWM_REGS_TBPHS,Time Base Phase Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved." hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal [a] If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base counter is not loaded with.." line.word 0x8 "EPWM_REGS_TBCNT,Time Base Counter Register" hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value Writing to these bits sets the current time-base counter value The update happens as soon as the write occurs The write is NOT synchronized to the time-base clock [TBCLK] and the register.." line.word 0xA "EPWM_REGS_TBPRD,Time Base Period Register" hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter This sets the PWM frequency Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit By default this register is shadowed [a] If TBCTL[PRDLD] = 0 then the shadow is enabled.." rgroup.word 0xE++0x17 line.word 0x0 "EPWM_REGS_CMPCTL,Counter Compare Control Register" rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1" rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self clears.." "0,1" bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1" bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1" bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3" bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3" line.word 0x2 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved." hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h" line.word 0x4 "EPWM_REGS_CMPA,Counter Compare A Register" hexmask.word 0x4 0.--15. 1. "CMPA,The value in the active CMPA register is continuously compared to the time-base counter [TBCNT] When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event This event is sent to the.." line.word 0x6 "EPWM_REGS_CMPB,Counter Compare B Register" hexmask.word 0x6 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter [TBCNT] When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event This event is sent to the.." line.word 0x8 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x8 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3" bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3" bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3" bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3" bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3" bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3" line.word 0xA "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3" bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3" bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3" bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3" bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3" bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3" line.word 0xC "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0xC 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3" bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1" bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3" bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1" bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3" line.word 0xE "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3" bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3" line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms the default is EPWMxA In is.." "0,1,2,3" bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3" bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3" line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register" hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter" line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter" line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register" hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low a one-shot trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the EPWMxA and.." hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low a cycle-by-cycle trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the.." rgroup.word 0x28++0x3 line.word 0x0 "EPWM_REGS_TZCTL,Trip Zone Control Register" bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3" bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3" line.word 0x2 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1" bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1" rgroup.word 0x2C++0x1 line.word 0x0 "EPWM_REGS_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1" bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1" bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag" "0,1" rgroup.word 0x2E++0x7 line.word 0x0 "EPWM_REGS_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1" bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1" bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1" line.word 0x2 "EPWM_REGS_TZFRC,Trip Zone Force Register" bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software" "0,1" bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1" line.word 0x4 "EPWM_REGS_ETSEL,Event Trigger Selection Register" bitfld.word 0x4 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1" bitfld.word 0x4 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7" line.word 0x6 "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x6 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled ETSEL[INT] = 0 or the.." "0,1,2,3" bitfld.word 0x6 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3" rgroup.word 0x36++0x5 line.word 0x0 "EPWM_REGS_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1" line.word 0x2 "EPWM_REGS_ETCLR,Event Trigger Clear Register" bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1" line.word 0x4 "EPWM_REGS_ETFRC,Event Trigger Force Register" bitfld.word 0x4 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1" rgroup.word 0x3C++0x1 line.word 0x0 "EPWM_REGS_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7" bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width" bitfld.word 0x0 0. "CHPEN,PWM-chopping Enable" "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "EPWM_REGS_PID,EHRPWM Peripheral ID Register. The IP revision register is used by software to track features. bugs. and compatibility." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,FUNC" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL version [R] maintained by IP design owner" bitfld.long 0x0 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,CUSTOM" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision [Y]" tree.end tree "EPWM3_EPWM (EPWM3_EPWM)" base ad:0x3030000 rgroup.word 0x0++0xB line.word 0x0 "EPWM_REGS_TBCTL,Time-Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events:" "0,1,2,3" bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase value.." "0,1" bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7" bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1" bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3" bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1" bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1" bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3" line.word 0x2 "EPWM_REGS_TBSTS,Time-Base Status Register" bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1" bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1" rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset the counter is frozen therefore this bit has no meaning To make this bit meaningful you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1" line.word 0x4 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register" hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits" line.word 0x6 "EPWM_REGS_TBPHS,Time Base Phase Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved." hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal [a] If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base counter is not loaded with.." line.word 0x8 "EPWM_REGS_TBCNT,Time Base Counter Register" hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value Writing to these bits sets the current time-base counter value The update happens as soon as the write occurs The write is NOT synchronized to the time-base clock [TBCLK] and the register.." line.word 0xA "EPWM_REGS_TBPRD,Time Base Period Register" hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter This sets the PWM frequency Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit By default this register is shadowed [a] If TBCTL[PRDLD] = 0 then the shadow is enabled.." rgroup.word 0xE++0x17 line.word 0x0 "EPWM_REGS_CMPCTL,Counter Compare Control Register" rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1" rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self clears.." "0,1" bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1" bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1" bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3" bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3" line.word 0x2 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved." hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h" line.word 0x4 "EPWM_REGS_CMPA,Counter Compare A Register" hexmask.word 0x4 0.--15. 1. "CMPA,The value in the active CMPA register is continuously compared to the time-base counter [TBCNT] When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event This event is sent to the.." line.word 0x6 "EPWM_REGS_CMPB,Counter Compare B Register" hexmask.word 0x6 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter [TBCNT] When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event This event is sent to the.." line.word 0x8 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x8 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3" bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3" bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3" bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3" bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3" bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3" line.word 0xA "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3" bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3" bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3" bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3" bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3" bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3" line.word 0xC "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0xC 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3" bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1" bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3" bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1" bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3" line.word 0xE "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3" bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3" line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms the default is EPWMxA In is.." "0,1,2,3" bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3" bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3" line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register" hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter" line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter" line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register" hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low a one-shot trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the EPWMxA and.." hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low a cycle-by-cycle trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the.." rgroup.word 0x28++0x3 line.word 0x0 "EPWM_REGS_TZCTL,Trip Zone Control Register" bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3" bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3" line.word 0x2 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1" bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1" rgroup.word 0x2C++0x1 line.word 0x0 "EPWM_REGS_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1" bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1" bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag" "0,1" rgroup.word 0x2E++0x7 line.word 0x0 "EPWM_REGS_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1" bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1" bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1" line.word 0x2 "EPWM_REGS_TZFRC,Trip Zone Force Register" bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software" "0,1" bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1" line.word 0x4 "EPWM_REGS_ETSEL,Event Trigger Selection Register" bitfld.word 0x4 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1" bitfld.word 0x4 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7" line.word 0x6 "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x6 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled ETSEL[INT] = 0 or the.." "0,1,2,3" bitfld.word 0x6 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3" rgroup.word 0x36++0x5 line.word 0x0 "EPWM_REGS_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1" line.word 0x2 "EPWM_REGS_ETCLR,Event Trigger Clear Register" bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1" line.word 0x4 "EPWM_REGS_ETFRC,Event Trigger Force Register" bitfld.word 0x4 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1" rgroup.word 0x3C++0x1 line.word 0x0 "EPWM_REGS_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7" bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width" bitfld.word 0x0 0. "CHPEN,PWM-chopping Enable" "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "EPWM_REGS_PID,EHRPWM Peripheral ID Register. The IP revision register is used by software to track features. bugs. and compatibility." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,FUNC" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL version [R] maintained by IP design owner" bitfld.long 0x0 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,CUSTOM" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision [Y]" tree.end tree "EPWM4_EPWM (EPWM4_EPWM)" base ad:0x3040000 rgroup.word 0x0++0xB line.word 0x0 "EPWM_REGS_TBCTL,Time-Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events:" "0,1,2,3" bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase value.." "0,1" bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7" bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1" bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3" bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1" bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1" bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3" line.word 0x2 "EPWM_REGS_TBSTS,Time-Base Status Register" bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1" bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1" rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset the counter is frozen therefore this bit has no meaning To make this bit meaningful you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1" line.word 0x4 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register" hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits" line.word 0x6 "EPWM_REGS_TBPHS,Time Base Phase Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved." hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal [a] If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base counter is not loaded with.." line.word 0x8 "EPWM_REGS_TBCNT,Time Base Counter Register" hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value Writing to these bits sets the current time-base counter value The update happens as soon as the write occurs The write is NOT synchronized to the time-base clock [TBCLK] and the register.." line.word 0xA "EPWM_REGS_TBPRD,Time Base Period Register" hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter This sets the PWM frequency Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit By default this register is shadowed [a] If TBCTL[PRDLD] = 0 then the shadow is enabled.." rgroup.word 0xE++0x17 line.word 0x0 "EPWM_REGS_CMPCTL,Counter Compare Control Register" rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1" rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self clears.." "0,1" bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1" bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1" bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3" bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3" line.word 0x2 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved." hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h" line.word 0x4 "EPWM_REGS_CMPA,Counter Compare A Register" hexmask.word 0x4 0.--15. 1. "CMPA,The value in the active CMPA register is continuously compared to the time-base counter [TBCNT] When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event This event is sent to the.." line.word 0x6 "EPWM_REGS_CMPB,Counter Compare B Register" hexmask.word 0x6 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter [TBCNT] When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event This event is sent to the.." line.word 0x8 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x8 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3" bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3" bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3" bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3" bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3" bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3" line.word 0xA "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3" bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3" bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3" bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3" bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3" bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3" line.word 0xC "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0xC 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3" bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1" bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3" bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1" bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3" line.word 0xE "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3" bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3" line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms the default is EPWMxA In is.." "0,1,2,3" bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3" bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3" line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register" hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter" line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter" line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register" hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low a one-shot trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the EPWMxA and.." hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low a cycle-by-cycle trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the.." rgroup.word 0x28++0x3 line.word 0x0 "EPWM_REGS_TZCTL,Trip Zone Control Register" bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3" bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3" line.word 0x2 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1" bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1" rgroup.word 0x2C++0x1 line.word 0x0 "EPWM_REGS_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1" bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1" bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag" "0,1" rgroup.word 0x2E++0x7 line.word 0x0 "EPWM_REGS_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1" bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1" bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1" line.word 0x2 "EPWM_REGS_TZFRC,Trip Zone Force Register" bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software" "0,1" bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1" line.word 0x4 "EPWM_REGS_ETSEL,Event Trigger Selection Register" bitfld.word 0x4 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1" bitfld.word 0x4 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7" line.word 0x6 "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x6 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled ETSEL[INT] = 0 or the.." "0,1,2,3" bitfld.word 0x6 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3" rgroup.word 0x36++0x5 line.word 0x0 "EPWM_REGS_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1" line.word 0x2 "EPWM_REGS_ETCLR,Event Trigger Clear Register" bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1" line.word 0x4 "EPWM_REGS_ETFRC,Event Trigger Force Register" bitfld.word 0x4 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1" rgroup.word 0x3C++0x1 line.word 0x0 "EPWM_REGS_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7" bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width" bitfld.word 0x0 0. "CHPEN,PWM-chopping Enable" "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "EPWM_REGS_PID,EHRPWM Peripheral ID Register. The IP revision register is used by software to track features. bugs. and compatibility." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,FUNC" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL version [R] maintained by IP design owner" bitfld.long 0x0 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,CUSTOM" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision [Y]" tree.end tree "EPWM5_EPWM (EPWM5_EPWM)" base ad:0x3050000 rgroup.word 0x0++0xB line.word 0x0 "EPWM_REGS_TBCTL,Time-Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events:" "0,1,2,3" bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase value.." "0,1" bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7" bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1" bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3" bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1" bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1" bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3" line.word 0x2 "EPWM_REGS_TBSTS,Time-Base Status Register" bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1" bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1" rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset the counter is frozen therefore this bit has no meaning To make this bit meaningful you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1" line.word 0x4 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register" hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits" line.word 0x6 "EPWM_REGS_TBPHS,Time Base Phase Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved." hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal [a] If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base counter is not loaded with.." line.word 0x8 "EPWM_REGS_TBCNT,Time Base Counter Register" hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value Writing to these bits sets the current time-base counter value The update happens as soon as the write occurs The write is NOT synchronized to the time-base clock [TBCLK] and the register.." line.word 0xA "EPWM_REGS_TBPRD,Time Base Period Register" hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter This sets the PWM frequency Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit By default this register is shadowed [a] If TBCTL[PRDLD] = 0 then the shadow is enabled.." rgroup.word 0xE++0x17 line.word 0x0 "EPWM_REGS_CMPCTL,Counter Compare Control Register" rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1" rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self clears.." "0,1" bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1" bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1" bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3" bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3" line.word 0x2 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved." hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h" line.word 0x4 "EPWM_REGS_CMPA,Counter Compare A Register" hexmask.word 0x4 0.--15. 1. "CMPA,The value in the active CMPA register is continuously compared to the time-base counter [TBCNT] When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event This event is sent to the.." line.word 0x6 "EPWM_REGS_CMPB,Counter Compare B Register" hexmask.word 0x6 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter [TBCNT] When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event This event is sent to the.." line.word 0x8 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x8 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3" bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3" bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3" bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3" bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3" bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3" line.word 0xA "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3" bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3" bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3" bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3" bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3" bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3" line.word 0xC "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0xC 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3" bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1" bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3" bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1" bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3" line.word 0xE "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3" bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3" line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms the default is EPWMxA In is.." "0,1,2,3" bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3" bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3" line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register" hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter" line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter" line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register" hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low a one-shot trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the EPWMxA and.." hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low a cycle-by-cycle trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the.." rgroup.word 0x28++0x3 line.word 0x0 "EPWM_REGS_TZCTL,Trip Zone Control Register" bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3" bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3" line.word 0x2 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1" bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1" rgroup.word 0x2C++0x1 line.word 0x0 "EPWM_REGS_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1" bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1" bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag" "0,1" rgroup.word 0x2E++0x7 line.word 0x0 "EPWM_REGS_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1" bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1" bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1" line.word 0x2 "EPWM_REGS_TZFRC,Trip Zone Force Register" bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software" "0,1" bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1" line.word 0x4 "EPWM_REGS_ETSEL,Event Trigger Selection Register" bitfld.word 0x4 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1" bitfld.word 0x4 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7" line.word 0x6 "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x6 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled ETSEL[INT] = 0 or the.." "0,1,2,3" bitfld.word 0x6 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3" rgroup.word 0x36++0x5 line.word 0x0 "EPWM_REGS_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1" line.word 0x2 "EPWM_REGS_ETCLR,Event Trigger Clear Register" bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1" line.word 0x4 "EPWM_REGS_ETFRC,Event Trigger Force Register" bitfld.word 0x4 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1" rgroup.word 0x3C++0x1 line.word 0x0 "EPWM_REGS_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7" bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width" bitfld.word 0x0 0. "CHPEN,PWM-chopping Enable" "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "EPWM_REGS_PID,EHRPWM Peripheral ID Register. The IP revision register is used by software to track features. bugs. and compatibility." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,FUNC" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL version [R] maintained by IP design owner" bitfld.long 0x0 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,CUSTOM" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision [Y]" tree.end tree.end tree "EQEP" base ad:0x0 tree "EQEP0_REG (EQEP0_REG)" base ad:0x3200000 rgroup.long 0x0++0xF line.long 0x0 "REG_QPOSCNT," hexmask.long 0x0 0.--31. 1. "POSCNT,This 32-bit position counter register counts up/down on every QEP pulse based on direction input. This counter acts as a position integrator whose count value is proportional to position from a give reference point." line.long 0x4 "REG_QPOSINIT," hexmask.long 0x4 0.--31. 1. "INITPOS,This register contains the position value to be used to initialize the position counter based on external strobe or Index event. Position counter can be initialized through software." line.long 0x8 "REG_QPOSMAX," hexmask.long 0x8 0.--31. 1. "MAXPOS,This register contains the maximum Position counter value for error checking in index reset mode or to reset the Position counter based on the maximum count value." line.long 0xC "REG_QPOSCMP," hexmask.long 0xC 0.--31. 1. "POSCMP,Position compare value in this register is compared with the position counter (POSCNT) to optionally generate interrupt on compare match." rgroup.long 0x10++0xB line.long 0x0 "REG_QPOSILAT," hexmask.long 0x0 0.--31. 1. "IPOSLAT,Position counter value can be latched into this register on index event." line.long 0x4 "REG_QPOSSLAT," hexmask.long 0x4 0.--31. 1. "SPOSLAT,Position counter value can be latched into this register on strobe event." line.long 0x8 "REG_QPOSLAT," hexmask.long 0x8 0.--31. 1. "POSLAT,Position counter value can be latched into this register on unit time out event." rgroup.long 0x1C++0x23 line.long 0x0 "REG_QUTMR," hexmask.long 0x0 0.--31. 1. "UNITTMR,This register acts as time base for unit time event generation. When this timer value matches with unit time period value unit time event is generated." line.long 0x4 "REG_QUPRD," hexmask.long 0x4 0.--31. 1. "UNITPRD,This register contains the period count for unit timer to generate periodic unit time events to latch the QEP position information at periodic interval & optionally to generate interrupt." line.long 0x8 "REG_QWD_TMR_PRD," hexmask.long.word 0x8 16.--31. 1. "QWDPRD,This field contains the time-out count for the QEP peripheral watch dog timer. When watch dog timer value matches with the watch dog period value status flag is set to indicate the stall." hexmask.long.word 0x8 0.--15. 1. "QWDTMR,This field acts as time base for watch dog to detect stalls. When this timer value matches with watch dog period value watch dog timeout event is generated. This register is reset upon edge transition in Quadrature clock indicating the motion." line.long 0xC "REG_QDEC_QEP_CTL," bitfld.long 0xC 30.--31. "FREE_SOFT,POSCNT Behavior: 00 Position Counter stops immediately on emulation suspend 01 Position Counter continues to count until the rollover 1x Position Counter is unaffected by emulation suspend QWDTMR Behavior: 02 Watchdog counter stops immediately.." "0,1,2,3" bitfld.long 0xC 28.--29. "PCRM,Position Counter Reset mode: 0 0 Index event resets the Position Counter for each revolution 0 1 Maximum position event resets the Position Counter. 1 0 RESET ONCE: First Index Event resets the Position Counter 1 1 Unit Time event resets the.." "0,1,2,3" bitfld.long 0xC 26.--27. "SEI,Strobe Event Initialization of Position Counter: 0 x Do nothing (action disabled) 1 0 Initialize Position Counter on rising edge of QEPS signal 1 1 Clockwise Direction: Initialize Position Counter on Rising edge of QEPS strobe Counter Clockwise.." "0,1,2,3" bitfld.long 0xC 24.--25. "IEI,Index Event Initialization of Position Counter: 0 x Do nothing (action disabled) 1 0 Initialize Position Counter on rising edge of index signal 1 1 Initialize Position Counter on falling edge of index signal" "0,1,2,3" bitfld.long 0xC 23. "SWI,Software Initialization of Position Counter: 0 Do nothing (action disabled) 1 Initialize Position Counter this bit is cleared automatically" "0,1" bitfld.long 0xC 22. "SEL,Strobe Event Latch of Position Counter: 0 Latch Position Counter on rising edge of strobe signal 1 Clockwise Direction: Position Counter is latched on Rising edge of QEPS strobe Counter Clockwise Direction: Position Counter is latched on Falling edge.." "0,1" bitfld.long 0xC 20.--21. "IEL,Index Event Latch of Position Counter (Software Index Marker): 0 0 Reserved 0 1 Latch Position Counter on Rising edge of index signal 1 0 Latch Position Counter on Falling edge of index signal 1 1 Software Index Marker Latch the Position Counter &.." "0,1,2,3" newline bitfld.long 0xC 19. "QPEN,Quadrature Position counter Enable/Software Reset: 0 Software Reset Initialize the internal operating Flag/read only registers to reset value* Following register are reset & QEP control registers retains the same value on the software reset be.." "0,1" bitfld.long 0xC 18. "QCLM,QEP Capture Latch mode: 0 Latch on Position Counter read by CPU: Capture Timer & Capture Period values are latched into QCTMRLAT & QCPRDLAT registers when CPU reads the POSCNT register. 1 Latch on Unit Time Out: Position Counter Capture Timer &.." "0,1" bitfld.long 0xC 17. "UTE,QEP Unit Timer Enable: 0 Disable QEP Unit Timer 1 Enable Unit Timer" "0,1" bitfld.long 0xC 16. "WDE,QEP Watchdog Enable: 0 Disable QEP watchdog 1 Enable QEP watchdog" "0,1" bitfld.long 0xC 14.--15. "QSRC,Position Counter Source selection: 00 Quadrature Count mode (QCLK=iCLK QDIR=iDIR) 01 Direction Count mode (QCLK=xCLK QDIR=xDIR) 10 UP Count mode for Frequency measurement (QCLK=xCLK QDIR=1) 11 DOWN Count mode for Frequency measurement (QCLK=xCLK .." "0,1,2,3" bitfld.long 0xC 13. "SOEN,Enable Position Compare Sync Output: 0 Disable Position Compare Sync Output 1 Enable Position Compare Sync Output" "0,1" bitfld.long 0xC 12. "SPSEL,Sync Output Pin Selection: 0 Index pin is used for Sync output (see Note below) 1 Strobe pin is used for Sync output (see Note below)" "0,1" newline bitfld.long 0xC 11. "XCR,External Clock Rate: 0 2x Resolution: Count the rising/falling edge 1 1x Resolution: Count the rising edge only" "0,1" bitfld.long 0xC 10. "SWAP,CLK/DIR signal source for Position Counter: 0 Quadrature clock inputs are not swapped 1 Quadrature clock inputs are swapped" "0,1" bitfld.long 0xC 9. "IGATE,Index Pulse Gating Option: 0 Disable gating of Index pulse 1 Gate the index pin with strobe" "0,1" bitfld.long 0xC 8. "QAP,QEPA input Polarity: 0 No effect 1 Negate QEPA input" "0,1" bitfld.long 0xC 7. "QBP,QEPB input Polarity: 0 No effect 1 Negate QEPB input" "0,1" bitfld.long 0xC 6. "QIP,QEPI input Polarity: 0 No effect 1 Negate QEPI input" "0,1" bitfld.long 0xC 5. "QSP,QEPS input Polarity: 0 No effect 1 Negate QEPS input" "0,1" line.long 0x10 "REG_QCAP_QPOS_CTL," bitfld.long 0x10 31. "PCSHDW,Position Compare Shadow Enable: 0 Shadow disabled load Immediate 1 Shadow Enabled." "0,1" bitfld.long 0x10 30. "PCLOAD,Position Compare Shadow Load Mode: 0 Load On POSCNT = 0 1 Load When POSCNT = POSCMP" "0,1" bitfld.long 0x10 29. "PCPOL,Polarity Of Sync Output: 0 Active HIGH pulse output 1 Active LOW pulse output" "0,1" bitfld.long 0x10 28. "PCE,Position Compare Enable/Disable: 0 Disable Mode (no inter or pulse) 1 Enable Mode" "0,1" hexmask.long.word 0x10 16.--27. 1. "PCSPW,Select pulse width period in SYSCLKOUT cycles: 0x000 1 * 4 * SYSCLKOUT cycles 0x001 2 * 4 * SYSCLKOUT cycles ... 0xFFF 4096 * 4 * SYSCLKOUT cycles" bitfld.long 0x10 15. "CEN,Enable QEP Capture: 0 QEP Capture unit is disabled 1 QEP Capture unit is enabled" "0,1" bitfld.long 0x10 4.--6. "CCPS,QEP Capture timer clock prescalar: 000 CAPCLK=SYSCLKOUT/1 001 CAPCLK=SYSCLKOUT/2 010 CAPCLK=SYSCLKOUT/4 011 CAPCLK=SYSCLKOUT/8 100 CAPCLK=SYSCLKOUT/16 101 CAPCLK=SYSCLKOUT/32 110 CAPCLK=SYSCLKOUT/64 111 CAPCLK=SYSCLKOUT/128" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--3. 1. "UPPS,Unit Position Event prescalar: 0000 UPEVNT = QCLK/1 0001 UPEVNT = QCLK/2 0010 UPEVNT = QCLK/4 0011 UPEVNT = QCLK/8 0100 UPEVNT = QCLK/16 0101 UPEVNT = QCLK/32 0110 UPEVNT = QCLK/64 0111 UPEVNT = QCLK/128 1000 UPEVNT = QCLK/256 1001 UPEVNT = QCLK/512.." line.long 0x14 "REG_QINT_EN_FLG," rbitfld.long 0x14 27. "UTOI_FLG,Unit Time Out Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 Set by QEP unit timer period match" "0,1" rbitfld.long 0x14 26. "IELI_FLG,Index Event Latch Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This bit is set after latching the POSCNT to IPOSLAT" "0,1" rbitfld.long 0x14 25. "SELI_FLG,Strobe Event Latch Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This bit is set after latching the POSCNT to SPOSLAT" "0,1" rbitfld.long 0x14 24. "PCMI_FLG,QEP Compare Match Event Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This bit is set on position compare match" "0,1" rbitfld.long 0x14 23. "PCRI_FLG,Position Compare Ready Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This bit is set on position compare FIFO level match" "0,1" rbitfld.long 0x14 22. "PCOI_FLG,Position Counter Overflow Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This bit is set during the POSCNT overflow" "0,1" rbitfld.long 0x14 21. "PCUI_FLG,Position Counter Underflow Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This bit is set during the POSCNT underflow" "0,1" newline rbitfld.long 0x14 20. "WTOI_FLG,Watchdog Timeout Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 Set by watch dog (monitoring QEPA & QEPB) timeout" "0,1" rbitfld.long 0x14 19. "QDCI_FLG,Quadrature Direction Change Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This bit is set during change of direction" "0,1" rbitfld.long 0x14 18. "QPEI_FLG,Quadrature Phase Error Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 Set on simultaneous transition of QEPA & QEPB" "0,1" rbitfld.long 0x14 17. "PCEI_FLG,Position Counter Error Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This is set during error in position count between index" "0,1" rbitfld.long 0x14 16. "INT_FLG,Global Interrupt Status Flag: Reading a 1 on this bit indicates that an interrupt was generated from one of the following events. Reading a 0 indicates no interrupt generated." "0,1" bitfld.long 0x14 11. "UTOI_EN,Unit Time Out Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 10. "IELI_EN,Index Event Latch Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" newline bitfld.long 0x14 9. "SELI_EN,Strobe Event Latch Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 8. "PCMI_EN,Position Compare Match Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 7. "PCRI_EN,Position Compare Ready Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 6. "PCOI_EN,Position Counter Overflow Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 5. "PCUI_EN,Position Counter Underflow Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 4. "WTOI_EN,Watchdog Time Out Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 3. "QDCI_EN,Quadrature Direction Change Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" newline bitfld.long 0x14 2. "QPEI_EN,Quadrature Phase Error Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 1. "PCEI_EN,Position Counter Error Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" line.long 0x18 "REG_QINT_CLR_FRC," bitfld.long 0x18 27. "UTOI_FRC,Unit Time Out Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 26. "IELI_FRC,Index Event Latch Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 25. "SELI_FRC,Strobe Event Latch Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 24. "PCMI_FRC,Position Compare Match Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 23. "PCRI_FRC,Position Compare Ready Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 22. "PCOI_FRC,Position Counter Overflow Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 21. "PCUI_FRC,Position Counter Underflow Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" newline bitfld.long 0x18 20. "WTOI_FRC,Watchdog Time Out Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 19. "QDCI_FRC,Quadrature Direction Change Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 18. "QPEI_FRC,Quadrature Phase Error Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 17. "PCEI_FRC,Position Counter Error Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 11. "UTOI_CLR,Clear Unit Time Out Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 10. "IELI_CLR,Clear Index Event Latch Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 9. "SELI_CLR,Clear Strobe Event Latch Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" newline bitfld.long 0x18 8. "PCMI_CLR,Clear QEP Compare Match Event Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 7. "PCRI_CLR,Clear Position Compare Ready Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 6. "PCOI_CLR,Clear Position Counter Overflow Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 5. "PCUI_CLR,Clear Position Counter Underflow Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 4. "WTOI_CLR,Clear Watchdog Timeout Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 3. "QDCI_CLR,Clear Quadrature Direction Change Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 2. "QPEI_CLR,Clear Quadrature Phase Error Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" newline bitfld.long 0x18 1. "PCEI_CLR,Clear Position Counter Error Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 0. "INT_CLR,Global Interrupt Clear Flag: Writing a 1 will clear the interrupt flag and enable further interrupts to be generated if any of the event flags are set to 1." "0,1" line.long 0x1C "REG_QEP_STS_CT," hexmask.long.word 0x1C 16.--31. 1. "QCTMR,This field provides time base for edge capture unit." rbitfld.long 0x1C 6. "FIDF,Direction on First Index Marker: Status of the direction is latched on first index event marker" "0,1" rbitfld.long 0x1C 5. "QDF,Quadrature Direction flag: 0 Anti-clockwise rotation or Reverse movement 1 Clockwise rotation or Forward movement" "0,1" rbitfld.long 0x1C 4. "QDLF,QEP Direction Latch Flag: Status of Direction is latched on every index event marker." "0,1" bitfld.long 0x1C 3. "COEF,Capture Overflow Error Flag: 0 Sticky bit cleared by writing 1 1 Overflow occurred in QEP Capture timer (QEPCTMR)" "0,1" bitfld.long 0x1C 2. "CDEF,Capture Direction Error Flag: 0 Sticky bit cleared by writing 1 1 Direction change occurred between the capture position event" "0,1" bitfld.long 0x1C 1. "FIMF,First Index Marker Flag: 0 Sticky bit cleared by writing 1 1 Set by first occurrence of index pulse" "0,1" newline rbitfld.long 0x1C 0. "PCEF,Position Counter Error Flag: (This bit is not sticky bit & it is updated for every index event) 0 No error occurred during the last index transition 1 Position counter error" "0,1" line.long 0x20 "REG_QC_PRD_TLAT," hexmask.long.word 0x20 16.--31. 1. "QCTMRLAT,QEP Capture timer value can be latched into this register on two events viz. Unit Timeout event Reading the QEP position counter." hexmask.long.word 0x20 0.--15. 1. "QCPRD,This field holds the period count value between the last successive QEP position events." rgroup.long 0x40++0x3 line.long 0x0 "REG_QCPRDLAT," hexmask.long.word 0x0 0.--15. 1. "QCPRDLAT,QEP Capture period value can be latched into this register on two events viz. Unit Timeout event Reading the QEP position counter." rgroup.long 0x5C++0x3 line.long 0x0 "REG_PID," bitfld.long 0x0 30.--31. "SCHEME," "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION," hexmask.long.byte 0x0 11.--15. 1. "RTL," bitfld.long 0x0 8.--10. "MAJOR," "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM," "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR," tree.end tree "EQEP1_REG (EQEP1_REG)" base ad:0x3210000 rgroup.long 0x0++0xF line.long 0x0 "REG_QPOSCNT," hexmask.long 0x0 0.--31. 1. "POSCNT,This 32-bit position counter register counts up/down on every QEP pulse based on direction input. This counter acts as a position integrator whose count value is proportional to position from a give reference point." line.long 0x4 "REG_QPOSINIT," hexmask.long 0x4 0.--31. 1. "INITPOS,This register contains the position value to be used to initialize the position counter based on external strobe or Index event. Position counter can be initialized through software." line.long 0x8 "REG_QPOSMAX," hexmask.long 0x8 0.--31. 1. "MAXPOS,This register contains the maximum Position counter value for error checking in index reset mode or to reset the Position counter based on the maximum count value." line.long 0xC "REG_QPOSCMP," hexmask.long 0xC 0.--31. 1. "POSCMP,Position compare value in this register is compared with the position counter (POSCNT) to optionally generate interrupt on compare match." rgroup.long 0x10++0xB line.long 0x0 "REG_QPOSILAT," hexmask.long 0x0 0.--31. 1. "IPOSLAT,Position counter value can be latched into this register on index event." line.long 0x4 "REG_QPOSSLAT," hexmask.long 0x4 0.--31. 1. "SPOSLAT,Position counter value can be latched into this register on strobe event." line.long 0x8 "REG_QPOSLAT," hexmask.long 0x8 0.--31. 1. "POSLAT,Position counter value can be latched into this register on unit time out event." rgroup.long 0x1C++0x23 line.long 0x0 "REG_QUTMR," hexmask.long 0x0 0.--31. 1. "UNITTMR,This register acts as time base for unit time event generation. When this timer value matches with unit time period value unit time event is generated." line.long 0x4 "REG_QUPRD," hexmask.long 0x4 0.--31. 1. "UNITPRD,This register contains the period count for unit timer to generate periodic unit time events to latch the QEP position information at periodic interval & optionally to generate interrupt." line.long 0x8 "REG_QWD_TMR_PRD," hexmask.long.word 0x8 16.--31. 1. "QWDPRD,This field contains the time-out count for the QEP peripheral watch dog timer. When watch dog timer value matches with the watch dog period value status flag is set to indicate the stall." hexmask.long.word 0x8 0.--15. 1. "QWDTMR,This field acts as time base for watch dog to detect stalls. When this timer value matches with watch dog period value watch dog timeout event is generated. This register is reset upon edge transition in Quadrature clock indicating the motion." line.long 0xC "REG_QDEC_QEP_CTL," bitfld.long 0xC 30.--31. "FREE_SOFT,POSCNT Behavior: 00 Position Counter stops immediately on emulation suspend 01 Position Counter continues to count until the rollover 1x Position Counter is unaffected by emulation suspend QWDTMR Behavior: 02 Watchdog counter stops immediately.." "0,1,2,3" bitfld.long 0xC 28.--29. "PCRM,Position Counter Reset mode: 0 0 Index event resets the Position Counter for each revolution 0 1 Maximum position event resets the Position Counter. 1 0 RESET ONCE: First Index Event resets the Position Counter 1 1 Unit Time event resets the.." "0,1,2,3" bitfld.long 0xC 26.--27. "SEI,Strobe Event Initialization of Position Counter: 0 x Do nothing (action disabled) 1 0 Initialize Position Counter on rising edge of QEPS signal 1 1 Clockwise Direction: Initialize Position Counter on Rising edge of QEPS strobe Counter Clockwise.." "0,1,2,3" bitfld.long 0xC 24.--25. "IEI,Index Event Initialization of Position Counter: 0 x Do nothing (action disabled) 1 0 Initialize Position Counter on rising edge of index signal 1 1 Initialize Position Counter on falling edge of index signal" "0,1,2,3" bitfld.long 0xC 23. "SWI,Software Initialization of Position Counter: 0 Do nothing (action disabled) 1 Initialize Position Counter this bit is cleared automatically" "0,1" bitfld.long 0xC 22. "SEL,Strobe Event Latch of Position Counter: 0 Latch Position Counter on rising edge of strobe signal 1 Clockwise Direction: Position Counter is latched on Rising edge of QEPS strobe Counter Clockwise Direction: Position Counter is latched on Falling edge.." "0,1" bitfld.long 0xC 20.--21. "IEL,Index Event Latch of Position Counter (Software Index Marker): 0 0 Reserved 0 1 Latch Position Counter on Rising edge of index signal 1 0 Latch Position Counter on Falling edge of index signal 1 1 Software Index Marker Latch the Position Counter &.." "0,1,2,3" newline bitfld.long 0xC 19. "QPEN,Quadrature Position counter Enable/Software Reset: 0 Software Reset Initialize the internal operating Flag/read only registers to reset value* Following register are reset & QEP control registers retains the same value on the software reset be.." "0,1" bitfld.long 0xC 18. "QCLM,QEP Capture Latch mode: 0 Latch on Position Counter read by CPU: Capture Timer & Capture Period values are latched into QCTMRLAT & QCPRDLAT registers when CPU reads the POSCNT register. 1 Latch on Unit Time Out: Position Counter Capture Timer &.." "0,1" bitfld.long 0xC 17. "UTE,QEP Unit Timer Enable: 0 Disable QEP Unit Timer 1 Enable Unit Timer" "0,1" bitfld.long 0xC 16. "WDE,QEP Watchdog Enable: 0 Disable QEP watchdog 1 Enable QEP watchdog" "0,1" bitfld.long 0xC 14.--15. "QSRC,Position Counter Source selection: 00 Quadrature Count mode (QCLK=iCLK QDIR=iDIR) 01 Direction Count mode (QCLK=xCLK QDIR=xDIR) 10 UP Count mode for Frequency measurement (QCLK=xCLK QDIR=1) 11 DOWN Count mode for Frequency measurement (QCLK=xCLK .." "0,1,2,3" bitfld.long 0xC 13. "SOEN,Enable Position Compare Sync Output: 0 Disable Position Compare Sync Output 1 Enable Position Compare Sync Output" "0,1" bitfld.long 0xC 12. "SPSEL,Sync Output Pin Selection: 0 Index pin is used for Sync output (see Note below) 1 Strobe pin is used for Sync output (see Note below)" "0,1" newline bitfld.long 0xC 11. "XCR,External Clock Rate: 0 2x Resolution: Count the rising/falling edge 1 1x Resolution: Count the rising edge only" "0,1" bitfld.long 0xC 10. "SWAP,CLK/DIR signal source for Position Counter: 0 Quadrature clock inputs are not swapped 1 Quadrature clock inputs are swapped" "0,1" bitfld.long 0xC 9. "IGATE,Index Pulse Gating Option: 0 Disable gating of Index pulse 1 Gate the index pin with strobe" "0,1" bitfld.long 0xC 8. "QAP,QEPA input Polarity: 0 No effect 1 Negate QEPA input" "0,1" bitfld.long 0xC 7. "QBP,QEPB input Polarity: 0 No effect 1 Negate QEPB input" "0,1" bitfld.long 0xC 6. "QIP,QEPI input Polarity: 0 No effect 1 Negate QEPI input" "0,1" bitfld.long 0xC 5. "QSP,QEPS input Polarity: 0 No effect 1 Negate QEPS input" "0,1" line.long 0x10 "REG_QCAP_QPOS_CTL," bitfld.long 0x10 31. "PCSHDW,Position Compare Shadow Enable: 0 Shadow disabled load Immediate 1 Shadow Enabled." "0,1" bitfld.long 0x10 30. "PCLOAD,Position Compare Shadow Load Mode: 0 Load On POSCNT = 0 1 Load When POSCNT = POSCMP" "0,1" bitfld.long 0x10 29. "PCPOL,Polarity Of Sync Output: 0 Active HIGH pulse output 1 Active LOW pulse output" "0,1" bitfld.long 0x10 28. "PCE,Position Compare Enable/Disable: 0 Disable Mode (no inter or pulse) 1 Enable Mode" "0,1" hexmask.long.word 0x10 16.--27. 1. "PCSPW,Select pulse width period in SYSCLKOUT cycles: 0x000 1 * 4 * SYSCLKOUT cycles 0x001 2 * 4 * SYSCLKOUT cycles ... 0xFFF 4096 * 4 * SYSCLKOUT cycles" bitfld.long 0x10 15. "CEN,Enable QEP Capture: 0 QEP Capture unit is disabled 1 QEP Capture unit is enabled" "0,1" bitfld.long 0x10 4.--6. "CCPS,QEP Capture timer clock prescalar: 000 CAPCLK=SYSCLKOUT/1 001 CAPCLK=SYSCLKOUT/2 010 CAPCLK=SYSCLKOUT/4 011 CAPCLK=SYSCLKOUT/8 100 CAPCLK=SYSCLKOUT/16 101 CAPCLK=SYSCLKOUT/32 110 CAPCLK=SYSCLKOUT/64 111 CAPCLK=SYSCLKOUT/128" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--3. 1. "UPPS,Unit Position Event prescalar: 0000 UPEVNT = QCLK/1 0001 UPEVNT = QCLK/2 0010 UPEVNT = QCLK/4 0011 UPEVNT = QCLK/8 0100 UPEVNT = QCLK/16 0101 UPEVNT = QCLK/32 0110 UPEVNT = QCLK/64 0111 UPEVNT = QCLK/128 1000 UPEVNT = QCLK/256 1001 UPEVNT = QCLK/512.." line.long 0x14 "REG_QINT_EN_FLG," rbitfld.long 0x14 27. "UTOI_FLG,Unit Time Out Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 Set by QEP unit timer period match" "0,1" rbitfld.long 0x14 26. "IELI_FLG,Index Event Latch Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This bit is set after latching the POSCNT to IPOSLAT" "0,1" rbitfld.long 0x14 25. "SELI_FLG,Strobe Event Latch Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This bit is set after latching the POSCNT to SPOSLAT" "0,1" rbitfld.long 0x14 24. "PCMI_FLG,QEP Compare Match Event Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This bit is set on position compare match" "0,1" rbitfld.long 0x14 23. "PCRI_FLG,Position Compare Ready Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This bit is set on position compare FIFO level match" "0,1" rbitfld.long 0x14 22. "PCOI_FLG,Position Counter Overflow Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This bit is set during the POSCNT overflow" "0,1" rbitfld.long 0x14 21. "PCUI_FLG,Position Counter Underflow Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This bit is set during the POSCNT underflow" "0,1" newline rbitfld.long 0x14 20. "WTOI_FLG,Watchdog Timeout Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 Set by watch dog (monitoring QEPA & QEPB) timeout" "0,1" rbitfld.long 0x14 19. "QDCI_FLG,Quadrature Direction Change Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This bit is set during change of direction" "0,1" rbitfld.long 0x14 18. "QPEI_FLG,Quadrature Phase Error Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 Set on simultaneous transition of QEPA & QEPB" "0,1" rbitfld.long 0x14 17. "PCEI_FLG,Position Counter Error Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This is set during error in position count between index" "0,1" rbitfld.long 0x14 16. "INT_FLG,Global Interrupt Status Flag: Reading a 1 on this bit indicates that an interrupt was generated from one of the following events. Reading a 0 indicates no interrupt generated." "0,1" bitfld.long 0x14 11. "UTOI_EN,Unit Time Out Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 10. "IELI_EN,Index Event Latch Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" newline bitfld.long 0x14 9. "SELI_EN,Strobe Event Latch Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 8. "PCMI_EN,Position Compare Match Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 7. "PCRI_EN,Position Compare Ready Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 6. "PCOI_EN,Position Counter Overflow Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 5. "PCUI_EN,Position Counter Underflow Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 4. "WTOI_EN,Watchdog Time Out Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 3. "QDCI_EN,Quadrature Direction Change Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" newline bitfld.long 0x14 2. "QPEI_EN,Quadrature Phase Error Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 1. "PCEI_EN,Position Counter Error Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" line.long 0x18 "REG_QINT_CLR_FRC," bitfld.long 0x18 27. "UTOI_FRC,Unit Time Out Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 26. "IELI_FRC,Index Event Latch Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 25. "SELI_FRC,Strobe Event Latch Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 24. "PCMI_FRC,Position Compare Match Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 23. "PCRI_FRC,Position Compare Ready Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 22. "PCOI_FRC,Position Counter Overflow Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 21. "PCUI_FRC,Position Counter Underflow Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" newline bitfld.long 0x18 20. "WTOI_FRC,Watchdog Time Out Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 19. "QDCI_FRC,Quadrature Direction Change Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 18. "QPEI_FRC,Quadrature Phase Error Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 17. "PCEI_FRC,Position Counter Error Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 11. "UTOI_CLR,Clear Unit Time Out Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 10. "IELI_CLR,Clear Index Event Latch Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 9. "SELI_CLR,Clear Strobe Event Latch Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" newline bitfld.long 0x18 8. "PCMI_CLR,Clear QEP Compare Match Event Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 7. "PCRI_CLR,Clear Position Compare Ready Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 6. "PCOI_CLR,Clear Position Counter Overflow Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 5. "PCUI_CLR,Clear Position Counter Underflow Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 4. "WTOI_CLR,Clear Watchdog Timeout Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 3. "QDCI_CLR,Clear Quadrature Direction Change Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 2. "QPEI_CLR,Clear Quadrature Phase Error Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" newline bitfld.long 0x18 1. "PCEI_CLR,Clear Position Counter Error Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 0. "INT_CLR,Global Interrupt Clear Flag: Writing a 1 will clear the interrupt flag and enable further interrupts to be generated if any of the event flags are set to 1." "0,1" line.long 0x1C "REG_QEP_STS_CT," hexmask.long.word 0x1C 16.--31. 1. "QCTMR,This field provides time base for edge capture unit." rbitfld.long 0x1C 6. "FIDF,Direction on First Index Marker: Status of the direction is latched on first index event marker" "0,1" rbitfld.long 0x1C 5. "QDF,Quadrature Direction flag: 0 Anti-clockwise rotation or Reverse movement 1 Clockwise rotation or Forward movement" "0,1" rbitfld.long 0x1C 4. "QDLF,QEP Direction Latch Flag: Status of Direction is latched on every index event marker." "0,1" bitfld.long 0x1C 3. "COEF,Capture Overflow Error Flag: 0 Sticky bit cleared by writing 1 1 Overflow occurred in QEP Capture timer (QEPCTMR)" "0,1" bitfld.long 0x1C 2. "CDEF,Capture Direction Error Flag: 0 Sticky bit cleared by writing 1 1 Direction change occurred between the capture position event" "0,1" bitfld.long 0x1C 1. "FIMF,First Index Marker Flag: 0 Sticky bit cleared by writing 1 1 Set by first occurrence of index pulse" "0,1" newline rbitfld.long 0x1C 0. "PCEF,Position Counter Error Flag: (This bit is not sticky bit & it is updated for every index event) 0 No error occurred during the last index transition 1 Position counter error" "0,1" line.long 0x20 "REG_QC_PRD_TLAT," hexmask.long.word 0x20 16.--31. 1. "QCTMRLAT,QEP Capture timer value can be latched into this register on two events viz. Unit Timeout event Reading the QEP position counter." hexmask.long.word 0x20 0.--15. 1. "QCPRD,This field holds the period count value between the last successive QEP position events." rgroup.long 0x40++0x3 line.long 0x0 "REG_QCPRDLAT," hexmask.long.word 0x0 0.--15. 1. "QCPRDLAT,QEP Capture period value can be latched into this register on two events viz. Unit Timeout event Reading the QEP position counter." rgroup.long 0x5C++0x3 line.long 0x0 "REG_PID," bitfld.long 0x0 30.--31. "SCHEME," "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION," hexmask.long.byte 0x0 11.--15. 1. "RTL," bitfld.long 0x0 8.--10. "MAJOR," "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM," "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR," tree.end tree "EQEP2_REG (EQEP2_REG)" base ad:0x3220000 rgroup.long 0x0++0xF line.long 0x0 "REG_QPOSCNT," hexmask.long 0x0 0.--31. 1. "POSCNT,This 32-bit position counter register counts up/down on every QEP pulse based on direction input. This counter acts as a position integrator whose count value is proportional to position from a give reference point." line.long 0x4 "REG_QPOSINIT," hexmask.long 0x4 0.--31. 1. "INITPOS,This register contains the position value to be used to initialize the position counter based on external strobe or Index event. Position counter can be initialized through software." line.long 0x8 "REG_QPOSMAX," hexmask.long 0x8 0.--31. 1. "MAXPOS,This register contains the maximum Position counter value for error checking in index reset mode or to reset the Position counter based on the maximum count value." line.long 0xC "REG_QPOSCMP," hexmask.long 0xC 0.--31. 1. "POSCMP,Position compare value in this register is compared with the position counter (POSCNT) to optionally generate interrupt on compare match." rgroup.long 0x10++0xB line.long 0x0 "REG_QPOSILAT," hexmask.long 0x0 0.--31. 1. "IPOSLAT,Position counter value can be latched into this register on index event." line.long 0x4 "REG_QPOSSLAT," hexmask.long 0x4 0.--31. 1. "SPOSLAT,Position counter value can be latched into this register on strobe event." line.long 0x8 "REG_QPOSLAT," hexmask.long 0x8 0.--31. 1. "POSLAT,Position counter value can be latched into this register on unit time out event." rgroup.long 0x1C++0x23 line.long 0x0 "REG_QUTMR," hexmask.long 0x0 0.--31. 1. "UNITTMR,This register acts as time base for unit time event generation. When this timer value matches with unit time period value unit time event is generated." line.long 0x4 "REG_QUPRD," hexmask.long 0x4 0.--31. 1. "UNITPRD,This register contains the period count for unit timer to generate periodic unit time events to latch the QEP position information at periodic interval & optionally to generate interrupt." line.long 0x8 "REG_QWD_TMR_PRD," hexmask.long.word 0x8 16.--31. 1. "QWDPRD,This field contains the time-out count for the QEP peripheral watch dog timer. When watch dog timer value matches with the watch dog period value status flag is set to indicate the stall." hexmask.long.word 0x8 0.--15. 1. "QWDTMR,This field acts as time base for watch dog to detect stalls. When this timer value matches with watch dog period value watch dog timeout event is generated. This register is reset upon edge transition in Quadrature clock indicating the motion." line.long 0xC "REG_QDEC_QEP_CTL," bitfld.long 0xC 30.--31. "FREE_SOFT,POSCNT Behavior: 00 Position Counter stops immediately on emulation suspend 01 Position Counter continues to count until the rollover 1x Position Counter is unaffected by emulation suspend QWDTMR Behavior: 02 Watchdog counter stops immediately.." "0,1,2,3" bitfld.long 0xC 28.--29. "PCRM,Position Counter Reset mode: 0 0 Index event resets the Position Counter for each revolution 0 1 Maximum position event resets the Position Counter. 1 0 RESET ONCE: First Index Event resets the Position Counter 1 1 Unit Time event resets the.." "0,1,2,3" bitfld.long 0xC 26.--27. "SEI,Strobe Event Initialization of Position Counter: 0 x Do nothing (action disabled) 1 0 Initialize Position Counter on rising edge of QEPS signal 1 1 Clockwise Direction: Initialize Position Counter on Rising edge of QEPS strobe Counter Clockwise.." "0,1,2,3" bitfld.long 0xC 24.--25. "IEI,Index Event Initialization of Position Counter: 0 x Do nothing (action disabled) 1 0 Initialize Position Counter on rising edge of index signal 1 1 Initialize Position Counter on falling edge of index signal" "0,1,2,3" bitfld.long 0xC 23. "SWI,Software Initialization of Position Counter: 0 Do nothing (action disabled) 1 Initialize Position Counter this bit is cleared automatically" "0,1" bitfld.long 0xC 22. "SEL,Strobe Event Latch of Position Counter: 0 Latch Position Counter on rising edge of strobe signal 1 Clockwise Direction: Position Counter is latched on Rising edge of QEPS strobe Counter Clockwise Direction: Position Counter is latched on Falling edge.." "0,1" bitfld.long 0xC 20.--21. "IEL,Index Event Latch of Position Counter (Software Index Marker): 0 0 Reserved 0 1 Latch Position Counter on Rising edge of index signal 1 0 Latch Position Counter on Falling edge of index signal 1 1 Software Index Marker Latch the Position Counter &.." "0,1,2,3" newline bitfld.long 0xC 19. "QPEN,Quadrature Position counter Enable/Software Reset: 0 Software Reset Initialize the internal operating Flag/read only registers to reset value* Following register are reset & QEP control registers retains the same value on the software reset be.." "0,1" bitfld.long 0xC 18. "QCLM,QEP Capture Latch mode: 0 Latch on Position Counter read by CPU: Capture Timer & Capture Period values are latched into QCTMRLAT & QCPRDLAT registers when CPU reads the POSCNT register. 1 Latch on Unit Time Out: Position Counter Capture Timer &.." "0,1" bitfld.long 0xC 17. "UTE,QEP Unit Timer Enable: 0 Disable QEP Unit Timer 1 Enable Unit Timer" "0,1" bitfld.long 0xC 16. "WDE,QEP Watchdog Enable: 0 Disable QEP watchdog 1 Enable QEP watchdog" "0,1" bitfld.long 0xC 14.--15. "QSRC,Position Counter Source selection: 00 Quadrature Count mode (QCLK=iCLK QDIR=iDIR) 01 Direction Count mode (QCLK=xCLK QDIR=xDIR) 10 UP Count mode for Frequency measurement (QCLK=xCLK QDIR=1) 11 DOWN Count mode for Frequency measurement (QCLK=xCLK .." "0,1,2,3" bitfld.long 0xC 13. "SOEN,Enable Position Compare Sync Output: 0 Disable Position Compare Sync Output 1 Enable Position Compare Sync Output" "0,1" bitfld.long 0xC 12. "SPSEL,Sync Output Pin Selection: 0 Index pin is used for Sync output (see Note below) 1 Strobe pin is used for Sync output (see Note below)" "0,1" newline bitfld.long 0xC 11. "XCR,External Clock Rate: 0 2x Resolution: Count the rising/falling edge 1 1x Resolution: Count the rising edge only" "0,1" bitfld.long 0xC 10. "SWAP,CLK/DIR signal source for Position Counter: 0 Quadrature clock inputs are not swapped 1 Quadrature clock inputs are swapped" "0,1" bitfld.long 0xC 9. "IGATE,Index Pulse Gating Option: 0 Disable gating of Index pulse 1 Gate the index pin with strobe" "0,1" bitfld.long 0xC 8. "QAP,QEPA input Polarity: 0 No effect 1 Negate QEPA input" "0,1" bitfld.long 0xC 7. "QBP,QEPB input Polarity: 0 No effect 1 Negate QEPB input" "0,1" bitfld.long 0xC 6. "QIP,QEPI input Polarity: 0 No effect 1 Negate QEPI input" "0,1" bitfld.long 0xC 5. "QSP,QEPS input Polarity: 0 No effect 1 Negate QEPS input" "0,1" line.long 0x10 "REG_QCAP_QPOS_CTL," bitfld.long 0x10 31. "PCSHDW,Position Compare Shadow Enable: 0 Shadow disabled load Immediate 1 Shadow Enabled." "0,1" bitfld.long 0x10 30. "PCLOAD,Position Compare Shadow Load Mode: 0 Load On POSCNT = 0 1 Load When POSCNT = POSCMP" "0,1" bitfld.long 0x10 29. "PCPOL,Polarity Of Sync Output: 0 Active HIGH pulse output 1 Active LOW pulse output" "0,1" bitfld.long 0x10 28. "PCE,Position Compare Enable/Disable: 0 Disable Mode (no inter or pulse) 1 Enable Mode" "0,1" hexmask.long.word 0x10 16.--27. 1. "PCSPW,Select pulse width period in SYSCLKOUT cycles: 0x000 1 * 4 * SYSCLKOUT cycles 0x001 2 * 4 * SYSCLKOUT cycles ... 0xFFF 4096 * 4 * SYSCLKOUT cycles" bitfld.long 0x10 15. "CEN,Enable QEP Capture: 0 QEP Capture unit is disabled 1 QEP Capture unit is enabled" "0,1" bitfld.long 0x10 4.--6. "CCPS,QEP Capture timer clock prescalar: 000 CAPCLK=SYSCLKOUT/1 001 CAPCLK=SYSCLKOUT/2 010 CAPCLK=SYSCLKOUT/4 011 CAPCLK=SYSCLKOUT/8 100 CAPCLK=SYSCLKOUT/16 101 CAPCLK=SYSCLKOUT/32 110 CAPCLK=SYSCLKOUT/64 111 CAPCLK=SYSCLKOUT/128" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--3. 1. "UPPS,Unit Position Event prescalar: 0000 UPEVNT = QCLK/1 0001 UPEVNT = QCLK/2 0010 UPEVNT = QCLK/4 0011 UPEVNT = QCLK/8 0100 UPEVNT = QCLK/16 0101 UPEVNT = QCLK/32 0110 UPEVNT = QCLK/64 0111 UPEVNT = QCLK/128 1000 UPEVNT = QCLK/256 1001 UPEVNT = QCLK/512.." line.long 0x14 "REG_QINT_EN_FLG," rbitfld.long 0x14 27. "UTOI_FLG,Unit Time Out Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 Set by QEP unit timer period match" "0,1" rbitfld.long 0x14 26. "IELI_FLG,Index Event Latch Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This bit is set after latching the POSCNT to IPOSLAT" "0,1" rbitfld.long 0x14 25. "SELI_FLG,Strobe Event Latch Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This bit is set after latching the POSCNT to SPOSLAT" "0,1" rbitfld.long 0x14 24. "PCMI_FLG,QEP Compare Match Event Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This bit is set on position compare match" "0,1" rbitfld.long 0x14 23. "PCRI_FLG,Position Compare Ready Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This bit is set on position compare FIFO level match" "0,1" rbitfld.long 0x14 22. "PCOI_FLG,Position Counter Overflow Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This bit is set during the POSCNT overflow" "0,1" rbitfld.long 0x14 21. "PCUI_FLG,Position Counter Underflow Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This bit is set during the POSCNT underflow" "0,1" newline rbitfld.long 0x14 20. "WTOI_FLG,Watchdog Timeout Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 Set by watch dog (monitoring QEPA & QEPB) timeout" "0,1" rbitfld.long 0x14 19. "QDCI_FLG,Quadrature Direction Change Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This bit is set during change of direction" "0,1" rbitfld.long 0x14 18. "QPEI_FLG,Quadrature Phase Error Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 Set on simultaneous transition of QEPA & QEPB" "0,1" rbitfld.long 0x14 17. "PCEI_FLG,Position Counter Error Interrupt Flag: 0 Reading a 0 indicates no interrupt generated 1 This is set during error in position count between index" "0,1" rbitfld.long 0x14 16. "INT_FLG,Global Interrupt Status Flag: Reading a 1 on this bit indicates that an interrupt was generated from one of the following events. Reading a 0 indicates no interrupt generated." "0,1" bitfld.long 0x14 11. "UTOI_EN,Unit Time Out Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 10. "IELI_EN,Index Event Latch Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" newline bitfld.long 0x14 9. "SELI_EN,Strobe Event Latch Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 8. "PCMI_EN,Position Compare Match Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 7. "PCRI_EN,Position Compare Ready Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 6. "PCOI_EN,Position Counter Overflow Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 5. "PCUI_EN,Position Counter Underflow Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 4. "WTOI_EN,Watchdog Time Out Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 3. "QDCI_EN,Quadrature Direction Change Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" newline bitfld.long 0x14 2. "QPEI_EN,Quadrature Phase Error Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" bitfld.long 0x14 1. "PCEI_EN,Position Counter Error Interrupt Enable: 0 Interrupt is disabled 1 Interrupt is enabled" "0,1" line.long 0x18 "REG_QINT_CLR_FRC," bitfld.long 0x18 27. "UTOI_FRC,Unit Time Out Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 26. "IELI_FRC,Index Event Latch Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 25. "SELI_FRC,Strobe Event Latch Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 24. "PCMI_FRC,Position Compare Match Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 23. "PCRI_FRC,Position Compare Ready Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 22. "PCOI_FRC,Position Counter Overflow Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 21. "PCUI_FRC,Position Counter Underflow Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" newline bitfld.long 0x18 20. "WTOI_FRC,Watchdog Time Out Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 19. "QDCI_FRC,Quadrature Direction Change Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 18. "QPEI_FRC,Quadrature Phase Error Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 17. "PCEI_FRC,Position Counter Error Interrupt Force: 0 No effect 1 Force the interrupt" "0,1" bitfld.long 0x18 11. "UTOI_CLR,Clear Unit Time Out Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 10. "IELI_CLR,Clear Index Event Latch Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 9. "SELI_CLR,Clear Strobe Event Latch Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" newline bitfld.long 0x18 8. "PCMI_CLR,Clear QEP Compare Match Event Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 7. "PCRI_CLR,Clear Position Compare Ready Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 6. "PCOI_CLR,Clear Position Counter Overflow Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 5. "PCUI_CLR,Clear Position Counter Underflow Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 4. "WTOI_CLR,Clear Watchdog Timeout Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 3. "QDCI_CLR,Clear Quadrature Direction Change Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 2. "QPEI_CLR,Clear Quadrature Phase Error Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" newline bitfld.long 0x18 1. "PCEI_CLR,Clear Position Counter Error Interrupt Flag: Writing 1 clears the interrupt flag" "0,1" bitfld.long 0x18 0. "INT_CLR,Global Interrupt Clear Flag: Writing a 1 will clear the interrupt flag and enable further interrupts to be generated if any of the event flags are set to 1." "0,1" line.long 0x1C "REG_QEP_STS_CT," hexmask.long.word 0x1C 16.--31. 1. "QCTMR,This field provides time base for edge capture unit." rbitfld.long 0x1C 6. "FIDF,Direction on First Index Marker: Status of the direction is latched on first index event marker" "0,1" rbitfld.long 0x1C 5. "QDF,Quadrature Direction flag: 0 Anti-clockwise rotation or Reverse movement 1 Clockwise rotation or Forward movement" "0,1" rbitfld.long 0x1C 4. "QDLF,QEP Direction Latch Flag: Status of Direction is latched on every index event marker." "0,1" bitfld.long 0x1C 3. "COEF,Capture Overflow Error Flag: 0 Sticky bit cleared by writing 1 1 Overflow occurred in QEP Capture timer (QEPCTMR)" "0,1" bitfld.long 0x1C 2. "CDEF,Capture Direction Error Flag: 0 Sticky bit cleared by writing 1 1 Direction change occurred between the capture position event" "0,1" bitfld.long 0x1C 1. "FIMF,First Index Marker Flag: 0 Sticky bit cleared by writing 1 1 Set by first occurrence of index pulse" "0,1" newline rbitfld.long 0x1C 0. "PCEF,Position Counter Error Flag: (This bit is not sticky bit & it is updated for every index event) 0 No error occurred during the last index transition 1 Position counter error" "0,1" line.long 0x20 "REG_QC_PRD_TLAT," hexmask.long.word 0x20 16.--31. 1. "QCTMRLAT,QEP Capture timer value can be latched into this register on two events viz. Unit Timeout event Reading the QEP position counter." hexmask.long.word 0x20 0.--15. 1. "QCPRD,This field holds the period count value between the last successive QEP position events." rgroup.long 0x40++0x3 line.long 0x0 "REG_QCPRDLAT," hexmask.long.word 0x0 0.--15. 1. "QCPRDLAT,QEP Capture period value can be latched into this register on two events viz. Unit Timeout event Reading the QEP position counter." rgroup.long 0x5C++0x3 line.long 0x0 "REG_PID," bitfld.long 0x0 30.--31. "SCHEME," "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION," hexmask.long.byte 0x0 11.--15. 1. "RTL," bitfld.long 0x0 8.--10. "MAJOR," "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM," "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR," tree.end tree.end tree "ESM0_CFG (ESM0_CFG)" base ad:0x700000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "CFG_INFO,The Info Register gives the configuration Inforrmation of this ESM." bitfld.long 0x4 31. "LAST_RESET,Indicates the Source of the last Reset" "0,1" hexmask.long.byte 0x4 8.--15. 1. "PULSE_GROUPS,Number of Pulse Error Groups" hexmask.long.byte 0x4 0.--7. 1. "GROUPS,Total number of Error Groups" rgroup.long 0x8++0x3 line.long 0x0 "CFG_EN,The Global Enable Register has the master interrupt mask" hexmask.long.byte 0x0 0.--3. 1. "KEY,Global Enable" rgroup.long 0xC++0x3 line.long 0x0 "CFG_SFT_RST,The Global Soft Reset Register controls the global clear for raw status and enables" hexmask.long.byte 0x0 0.--3. 1. "KEY,Global Soft Reset" rgroup.long 0x10++0xF line.long 0x0 "CFG_ERR_RAW,Raw Status/Set Register for Configuration Errors" hexmask.long.tbyte 0x0 0.--21. 1. "STS,This is the raw status for config errors" line.long 0x4 "CFG_ERR_STS,Config Error Enable and Clear Register" hexmask.long.tbyte 0x4 0.--21. 1. "MSK,This is the masked status/clear for config errors" line.long 0x8 "CFG_ERR_EN_SET,Config Error Enable Set Register" hexmask.long.tbyte 0x8 0.--21. 1. "MSK,This is the mask enable set for config errors" line.long 0xC "CFG_ERR_EN_CLR,Config Error Interrupt Enabled Clear register" hexmask.long.tbyte 0xC 0.--21. 1. "MSK,This is the mask enable clear for config errors" rgroup.long 0x20++0xF line.long 0x0 "CFG_LOW_PRI,Shows which is the highest priority outstanding low priority interrupt" hexmask.long.word 0x0 16.--31. 1. "PLS,This is the highest priority outstanding low priority pulse interrupt" hexmask.long.word 0x0 0.--15. 1. "LVL,This is the highest priority outstanding low priority level interrupt" line.long 0x4 "CFG_HI_PRI,Shows which is the highest priority outstanding high priority interrupt" hexmask.long.word 0x4 16.--31. 1. "PLS,This is the highest priority outstanding high priority pulse interrupt" hexmask.long.word 0x4 0.--15. 1. "LVL,This is the highest priority outstanding high priority level interrupt" line.long 0x8 "CFG_LOW,Shows which groups have oustanding low priority interrupts" hexmask.long 0x8 0.--31. 1. "STS,This is the raw status for config errors" line.long 0xC "CFG_HI,Shows which groups have oustanding high priority interrupts" hexmask.long 0xC 0.--31. 1. "STS,This is the raw status for config errors" rgroup.long 0x30++0x3 line.long 0x0 "CFG_EOI,End of Interrupt Register" hexmask.long.word 0x0 0.--10. 1. "KEY,This is the interrupt being serviced" rgroup.long 0x40++0x3 line.long 0x0 "CFG_PIN_CTRL,This register controls the error_pin_n output" hexmask.long.byte 0x0 4.--7. 1. "PWM_EN,PWM enable" hexmask.long.byte 0x0 0.--3. 1. "KEY,Pin Control Key" rgroup.long 0x44++0x7 line.long 0x0 "CFG_PIN_STS,This register reflects the status of the error_pin_n output" bitfld.long 0x0 0. "VAL,Value of the error_pin_n" "0,1" line.long 0x4 "CFG_PIN_CNTR,This register shows the current value of the error pin counter" hexmask.long.tbyte 0x4 0.--23. 1. "COUNT,Current Counter Value" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error Counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value" rgroup.long 0x50++0x3 line.long 0x0 "CFG_PWMH_PIN_CNTR,This register shows the current value of the error pin PWM high counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Current Counter Value" rgroup.long 0x54++0x3 line.long 0x0 "CFG_PWMH_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error PWM High Counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value" rgroup.long 0x58++0x3 line.long 0x0 "CFG_PWML_PIN_CNTR,This register shows the current value of the error pin PWM low counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Current Counter Value" rgroup.long 0x5C++0x3 line.long 0x0 "CFG_PWML_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error PWM Low Counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value" rgroup.long 0x400++0x1B line.long 0x0 "CFG_RAW,Raw Status/Set Register for Group A Errors" hexmask.long 0x0 0.--31. 1. "STS,This is the raw status/set for errors Group A" line.long 0x4 "CFG_STS,Error Enable and Clear Register" hexmask.long 0x4 0.--31. 1. "MSK,This is the masked status/clear for errors in Group A" line.long 0x8 "CFG_INTR_EN_SET,Level Error Enable Set Register" hexmask.long 0x8 0.--31. 1. "MSK,This is the mask enable set for errors in Group A" line.long 0xC "CFG_INTR_EN_CLR,Level Error Interrupt Enabled Clear register" hexmask.long 0xC 0.--31. 1. "MSK,This is the mask enable clear for errors in Group A" line.long 0x10 "CFG_INT_PRIO,Level Error Interrupt Enabled Clear register" hexmask.long 0x10 0.--31. 1. "MSK,This is interrupt priority for errors in Group A" line.long 0x14 "CFG_PIN_EN_SET,Level Error Interrupt Enabled Clear register" hexmask.long 0x14 0.--31. 1. "MSK,This is the error pin influence enable set for errors in Group A" line.long 0x18 "CFG_PIN_EN_CLR,Level Error Interrupt Enabled Clear register" hexmask.long 0x18 0.--31. 1. "MSK,This is the error pin influence enable clear for errors in Group A" tree.end tree "GPIO" base ad:0x0 tree "GPIO0 (GPIO0)" base ad:0x600000 rgroup.long 0x0++0x7 line.long 0x0 "MEM_pid,GPIO Periperal ID Register" bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code" bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code" line.long 0x4 "MEM_PCR,Peripheral Control Register" bitfld.long 0x4 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode." "0,1" bitfld.long 0x4 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_BINTEN,Bit Interrupt Enable Register" hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable. 0 = disable 1 = enable." rgroup.long 0x10++0xF line.long 0x0 "MEM_DIR01,Direction Register" hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits 0 = output 1 = input." hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits 0 = output 1 = input." line.long 0x4 "MEM_OUT_DATA01,Output Drive State Register" hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x8 "MEM_SET_DATA01,Set Output Drive State Register" hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits. Reading it returns the output drive state." hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits. Reading it returns the output drive state." line.long 0xC "MEM_CLR_DATA01,Clear Output Drive State Register" hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x20++0x3 line.long 0x0 "MEM_IN_DATA01,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits." rgroup.long 0x24++0x23 line.long 0x0 "MEM_SET_RIS_TRIG01,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits." line.long 0x4 "MEM_CLR_RIS_TRIG01,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits." line.long 0x8 "MEM_SET_FAL_TRIG01,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits." line.long 0xC "MEM_CLR_FAL_TRIG01,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits." line.long 0x10 "MEM_INTSTAT01,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR23,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA23,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA23,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA23,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x48++0x3 line.long 0x0 "MEM_IN_DATA23,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits." rgroup.long 0x4C++0x23 line.long 0x0 "MEM_SET_RIS_TRIG23,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits." line.long 0x4 "MEM_CLR_RIS_TRIG23,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits." line.long 0x8 "MEM_SET_FAL_TRIG23,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits." line.long 0xC "MEM_CLR_FAL_TRIG23,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits." line.long 0x10 "MEM_INTSTAT23,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR45,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA45,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA45,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA45,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x70++0x3 line.long 0x0 "MEM_IN_DATA45,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits." rgroup.long 0x74++0x23 line.long 0x0 "MEM_SET_RIS_TRIG45,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits." line.long 0x4 "MEM_CLR_RIS_TRIG45,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits." line.long 0x8 "MEM_SET_FAL_TRIG45,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits." line.long 0xC "MEM_CLR_FAL_TRIG45,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits." line.long 0x10 "MEM_INTSTAT45,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR67,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA67,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA67,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA67,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x98++0x3 line.long 0x0 "MEM_IN_DATA67,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits." rgroup.long 0x9C++0x23 line.long 0x0 "MEM_SET_RIS_TRIG67,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits." line.long 0x4 "MEM_CLR_RIS_TRIG67,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits." line.long 0x8 "MEM_SET_FAL_TRIG67,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits." line.long 0xC "MEM_CLR_FAL_TRIG67,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits." line.long 0x10 "MEM_INTSTAT67,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR8,Direction Register" hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA8,Output Drive State Register" hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA8,Set Output Drive State Register" hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA8,Clear Output Drive State Register" hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0xC0++0x3 line.long 0x0 "MEM_IN_DATA8,Bank Status Register" hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits." rgroup.long 0xC4++0x13 line.long 0x0 "MEM_SET_RIS_TRIG8,Set Rising Edge Detection Register" hexmask.long.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits." line.long 0x4 "MEM_CLR_RIS_TRIG8,Clear Rising Edge Detection Register" hexmask.long.word 0x4 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits." line.long 0x8 "MEM_SET_FAL_TRIG8,Set Falling Edge Detection Register" hexmask.long.word 0x8 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits." line.long 0xC "MEM_CLR_FAL_TRIG8,Clear Falling Edge Detection Register" hexmask.long.word 0xC 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits." line.long 0x10 "MEM_INTSTAT8,Bank Interrupt Status Register" hexmask.long.word 0x10 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." tree.end tree "GPIO2 (GPIO2)" base ad:0x610000 rgroup.long 0x0++0x7 line.long 0x0 "MEM_pid,GPIO Periperal ID Register" bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code" bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code" line.long 0x4 "MEM_PCR,Peripheral Control Register" bitfld.long 0x4 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode." "0,1" bitfld.long 0x4 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_BINTEN,Bit Interrupt Enable Register" hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable. 0 = disable 1 = enable." rgroup.long 0x10++0xF line.long 0x0 "MEM_DIR01,Direction Register" hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits 0 = output 1 = input." hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits 0 = output 1 = input." line.long 0x4 "MEM_OUT_DATA01,Output Drive State Register" hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x8 "MEM_SET_DATA01,Set Output Drive State Register" hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits. Reading it returns the output drive state." hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits. Reading it returns the output drive state." line.long 0xC "MEM_CLR_DATA01,Clear Output Drive State Register" hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x20++0x3 line.long 0x0 "MEM_IN_DATA01,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits." rgroup.long 0x24++0x23 line.long 0x0 "MEM_SET_RIS_TRIG01,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits." line.long 0x4 "MEM_CLR_RIS_TRIG01,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits." line.long 0x8 "MEM_SET_FAL_TRIG01,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits." line.long 0xC "MEM_CLR_FAL_TRIG01,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits." line.long 0x10 "MEM_INTSTAT01,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR23,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA23,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA23,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA23,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x48++0x3 line.long 0x0 "MEM_IN_DATA23,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits." rgroup.long 0x4C++0x23 line.long 0x0 "MEM_SET_RIS_TRIG23,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits." line.long 0x4 "MEM_CLR_RIS_TRIG23,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits." line.long 0x8 "MEM_SET_FAL_TRIG23,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits." line.long 0xC "MEM_CLR_FAL_TRIG23,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits." line.long 0x10 "MEM_INTSTAT23,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR45,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA45,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA45,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA45,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x70++0x3 line.long 0x0 "MEM_IN_DATA45,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits." rgroup.long 0x74++0x23 line.long 0x0 "MEM_SET_RIS_TRIG45,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits." line.long 0x4 "MEM_CLR_RIS_TRIG45,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits." line.long 0x8 "MEM_SET_FAL_TRIG45,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits." line.long 0xC "MEM_CLR_FAL_TRIG45,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits." line.long 0x10 "MEM_INTSTAT45,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR67,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA67,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA67,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA67,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x98++0x3 line.long 0x0 "MEM_IN_DATA67,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits." rgroup.long 0x9C++0x23 line.long 0x0 "MEM_SET_RIS_TRIG67,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits." line.long 0x4 "MEM_CLR_RIS_TRIG67,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits." line.long 0x8 "MEM_SET_FAL_TRIG67,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits." line.long 0xC "MEM_CLR_FAL_TRIG67,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits." line.long 0x10 "MEM_INTSTAT67,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR8,Direction Register" hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA8,Output Drive State Register" hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA8,Set Output Drive State Register" hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA8,Clear Output Drive State Register" hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0xC0++0x3 line.long 0x0 "MEM_IN_DATA8,Bank Status Register" hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits." rgroup.long 0xC4++0x13 line.long 0x0 "MEM_SET_RIS_TRIG8,Set Rising Edge Detection Register" hexmask.long.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits." line.long 0x4 "MEM_CLR_RIS_TRIG8,Clear Rising Edge Detection Register" hexmask.long.word 0x4 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits." line.long 0x8 "MEM_SET_FAL_TRIG8,Set Falling Edge Detection Register" hexmask.long.word 0x8 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits." line.long 0xC "MEM_CLR_FAL_TRIG8,Clear Falling Edge Detection Register" hexmask.long.word 0xC 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits." line.long 0x10 "MEM_INTSTAT8,Bank Interrupt Status Register" hexmask.long.word 0x10 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." tree.end tree "GPIO4 (GPIO4)" base ad:0x620000 rgroup.long 0x0++0x7 line.long 0x0 "MEM_pid,GPIO Periperal ID Register" bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code" bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code" line.long 0x4 "MEM_PCR,Peripheral Control Register" bitfld.long 0x4 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode." "0,1" bitfld.long 0x4 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_BINTEN,Bit Interrupt Enable Register" hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable. 0 = disable 1 = enable." rgroup.long 0x10++0xF line.long 0x0 "MEM_DIR01,Direction Register" hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits 0 = output 1 = input." hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits 0 = output 1 = input." line.long 0x4 "MEM_OUT_DATA01,Output Drive State Register" hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x8 "MEM_SET_DATA01,Set Output Drive State Register" hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits. Reading it returns the output drive state." hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits. Reading it returns the output drive state." line.long 0xC "MEM_CLR_DATA01,Clear Output Drive State Register" hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x20++0x3 line.long 0x0 "MEM_IN_DATA01,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits." rgroup.long 0x24++0x23 line.long 0x0 "MEM_SET_RIS_TRIG01,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits." line.long 0x4 "MEM_CLR_RIS_TRIG01,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits." line.long 0x8 "MEM_SET_FAL_TRIG01,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits." line.long 0xC "MEM_CLR_FAL_TRIG01,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits." line.long 0x10 "MEM_INTSTAT01,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR23,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA23,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA23,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA23,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x48++0x3 line.long 0x0 "MEM_IN_DATA23,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits." rgroup.long 0x4C++0x23 line.long 0x0 "MEM_SET_RIS_TRIG23,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits." line.long 0x4 "MEM_CLR_RIS_TRIG23,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits." line.long 0x8 "MEM_SET_FAL_TRIG23,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits." line.long 0xC "MEM_CLR_FAL_TRIG23,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits." line.long 0x10 "MEM_INTSTAT23,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR45,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA45,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA45,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA45,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x70++0x3 line.long 0x0 "MEM_IN_DATA45,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits." rgroup.long 0x74++0x23 line.long 0x0 "MEM_SET_RIS_TRIG45,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits." line.long 0x4 "MEM_CLR_RIS_TRIG45,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits." line.long 0x8 "MEM_SET_FAL_TRIG45,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits." line.long 0xC "MEM_CLR_FAL_TRIG45,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits." line.long 0x10 "MEM_INTSTAT45,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR67,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA67,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA67,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA67,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x98++0x3 line.long 0x0 "MEM_IN_DATA67,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits." rgroup.long 0x9C++0x23 line.long 0x0 "MEM_SET_RIS_TRIG67,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits." line.long 0x4 "MEM_CLR_RIS_TRIG67,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits." line.long 0x8 "MEM_SET_FAL_TRIG67,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits." line.long 0xC "MEM_CLR_FAL_TRIG67,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits." line.long 0x10 "MEM_INTSTAT67,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR8,Direction Register" hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA8,Output Drive State Register" hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA8,Set Output Drive State Register" hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA8,Clear Output Drive State Register" hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0xC0++0x3 line.long 0x0 "MEM_IN_DATA8,Bank Status Register" hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits." rgroup.long 0xC4++0x13 line.long 0x0 "MEM_SET_RIS_TRIG8,Set Rising Edge Detection Register" hexmask.long.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits." line.long 0x4 "MEM_CLR_RIS_TRIG8,Clear Rising Edge Detection Register" hexmask.long.word 0x4 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits." line.long 0x8 "MEM_SET_FAL_TRIG8,Set Falling Edge Detection Register" hexmask.long.word 0x8 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits." line.long 0xC "MEM_CLR_FAL_TRIG8,Clear Falling Edge Detection Register" hexmask.long.word 0xC 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits." line.long 0x10 "MEM_INTSTAT8,Bank Interrupt Status Register" hexmask.long.word 0x10 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." tree.end tree "GPIO6 (GPIO6)" base ad:0x630000 rgroup.long 0x0++0x7 line.long 0x0 "MEM_pid,GPIO Periperal ID Register" bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code" bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code" line.long 0x4 "MEM_PCR,Peripheral Control Register" bitfld.long 0x4 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode." "0,1" bitfld.long 0x4 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_BINTEN,Bit Interrupt Enable Register" hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable. 0 = disable 1 = enable." rgroup.long 0x10++0xF line.long 0x0 "MEM_DIR01,Direction Register" hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits 0 = output 1 = input." hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits 0 = output 1 = input." line.long 0x4 "MEM_OUT_DATA01,Output Drive State Register" hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x8 "MEM_SET_DATA01,Set Output Drive State Register" hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits. Reading it returns the output drive state." hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits. Reading it returns the output drive state." line.long 0xC "MEM_CLR_DATA01,Clear Output Drive State Register" hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x20++0x3 line.long 0x0 "MEM_IN_DATA01,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits." rgroup.long 0x24++0x23 line.long 0x0 "MEM_SET_RIS_TRIG01,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits." line.long 0x4 "MEM_CLR_RIS_TRIG01,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits." line.long 0x8 "MEM_SET_FAL_TRIG01,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits." line.long 0xC "MEM_CLR_FAL_TRIG01,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits." line.long 0x10 "MEM_INTSTAT01,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR23,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA23,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA23,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA23,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x48++0x3 line.long 0x0 "MEM_IN_DATA23,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits." rgroup.long 0x4C++0x23 line.long 0x0 "MEM_SET_RIS_TRIG23,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits." line.long 0x4 "MEM_CLR_RIS_TRIG23,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits." line.long 0x8 "MEM_SET_FAL_TRIG23,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits." line.long 0xC "MEM_CLR_FAL_TRIG23,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits." line.long 0x10 "MEM_INTSTAT23,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR45,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA45,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA45,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA45,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x70++0x3 line.long 0x0 "MEM_IN_DATA45,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits." rgroup.long 0x74++0x23 line.long 0x0 "MEM_SET_RIS_TRIG45,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits." line.long 0x4 "MEM_CLR_RIS_TRIG45,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits." line.long 0x8 "MEM_SET_FAL_TRIG45,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits." line.long 0xC "MEM_CLR_FAL_TRIG45,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits." line.long 0x10 "MEM_INTSTAT45,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR67,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA67,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA67,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA67,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x98++0x3 line.long 0x0 "MEM_IN_DATA67,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits." rgroup.long 0x9C++0x23 line.long 0x0 "MEM_SET_RIS_TRIG67,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits." line.long 0x4 "MEM_CLR_RIS_TRIG67,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits." line.long 0x8 "MEM_SET_FAL_TRIG67,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits." line.long 0xC "MEM_CLR_FAL_TRIG67,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits." line.long 0x10 "MEM_INTSTAT67,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR8,Direction Register" hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA8,Output Drive State Register" hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA8,Set Output Drive State Register" hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA8,Clear Output Drive State Register" hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0xC0++0x3 line.long 0x0 "MEM_IN_DATA8,Bank Status Register" hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits." rgroup.long 0xC4++0x13 line.long 0x0 "MEM_SET_RIS_TRIG8,Set Rising Edge Detection Register" hexmask.long.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits." line.long 0x4 "MEM_CLR_RIS_TRIG8,Clear Rising Edge Detection Register" hexmask.long.word 0x4 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits." line.long 0x8 "MEM_SET_FAL_TRIG8,Set Falling Edge Detection Register" hexmask.long.word 0x8 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits." line.long 0xC "MEM_CLR_FAL_TRIG8,Clear Falling Edge Detection Register" hexmask.long.word 0xC 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits." line.long 0x10 "MEM_INTSTAT8,Bank Interrupt Status Register" hexmask.long.word 0x10 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." tree.end tree.end tree "GPMC0_CFG (GPMC0_CFG)" base ad:0x5390000 group.long 0x0++0x3 line.long 0x0 "CFG_GPMC_REVISION,This register contains the IP revision code" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reads returns 0" newline hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0 0x21 for 2.1" group.long 0x10++0xF line.long 0x0 "CFG_GPMC_SYSCONFIG,This register controls the various parameters of the OCP interface" hexmask.long 0x0 5.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline bitfld.long 0x0 3.--4. "IDLEMODE," "0,1,2,3" newline bitfld.long 0x0 2. "RESERVED,Write 0 for future compatibility Reads returns 0" "0,1" newline bitfld.long 0x0 1. "RESERVED,This bit must be kept 0 for normal functioning of the IP. Do not set this bit to 1" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" line.long 0x4 "CFG_GPMC_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reads returns 0" newline hexmask.long.byte 0x4 1.--7. 1. "RESERVED,Reads returns 0 [reserved for OCP-socket status information]" newline rbitfld.long 0x4 0. "RESETDONE,Internal reset monitoring" "0,1" line.long 0x8 "CFG_GPMC_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline bitfld.long 0x8 11. "WAIT3EDGEDETECTIONSTATUS,Status of the Wait3 Edge Detection interrupt" "0,1" newline bitfld.long 0x8 10. "WAIT2EDGEDETECTIONSTATUS,Status of the Wait2 Edge Detection interrupt" "0,1" newline bitfld.long 0x8 9. "WAIT1EDGEDETECTIONSTATUS,Status of the Wait1 Edge Detection interrupt" "0,1" newline bitfld.long 0x8 8. "WAIT0EDGEDETECTIONSTATUS,Status of the Wait0 Edge Detection interrupt" "0,1" newline hexmask.long.byte 0x8 2.--7. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline bitfld.long 0x8 1. "TERMINALCOUNTSTATUS,Status of the TerminalCountEvent interrupt" "0,1" newline bitfld.long 0x8 0. "FIFOEVENTSTATUS,Status of the FIFOEvent interrupt" "0,1" line.long 0xC "CFG_GPMC_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis." hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline bitfld.long 0xC 11. "WAIT3EDGEDETECTIONENABLE,Enables the Wait3 Edge Detection interrupt" "0,1" newline bitfld.long 0xC 10. "WAIT2EDGEDETECTIONENABLE,Enables the Wait2 Edge Detection interrupt" "0,1" newline bitfld.long 0xC 9. "WAIT1EDGEDETECTIONENABLE,Enables the Wait1 Edge Detection interrupt" "0,1" newline bitfld.long 0xC 8. "WAIT0EDGEDETECTIONENABLE,Enables the Wait0 Edge Detection interrupt" "0,1" newline hexmask.long.byte 0xC 2.--7. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline bitfld.long 0xC 1. "TERMINALCOUNTEVENTENABLE,Enables TerminalCountEvent interrupt issuing in pre-fetch or write posting mode" "0,1" newline bitfld.long 0xC 0. "FIFOEVENTENABLE,Enables the FIFOEvent interrupt" "0,1" group.long 0x40++0xB line.long 0x0 "CFG_GPMC_TIMEOUT_CONTROL,The GPMC_TIMEOUT_CONTROL register allows the user to set the start value of the timeout counter" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline hexmask.long.word 0x0 4.--12. 1. "TIMEOUTSTARTVALUE,Start value of the time-out counter [0x000 corresponds to 0 GPMC.FCLK cycle 0x001 corresponds to 1 GmpcClk cycle & 0x1FF corresponds to 511 GPMC.FCLK cyles.]" newline bitfld.long 0x0 1.--3. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "TIMEOUTENABLE,Enable bit of the TimeOut feature" "0,1" line.long 0x4 "CFG_GPMC_ERR_ADDRESS,The GPMC_ERR_ADDRESS register stores the address of the illegal access when an error occurs" bitfld.long 0x4 31. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1" newline hexmask.long 0x4 0.--30. 1. "ILLEGALADD,Address of illegal access : A30[0 for memory region 1 for GPMC register region] and A29-A0[1 GBytes maximum]" line.long 0x8 "CFG_GPMC_ERR_TYPE,The GPMC_ERR_TYPE register stores the type of error when an error occurs" hexmask.long.tbyte 0x8 11.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline rbitfld.long 0x8 8.--10. "ILLEGALMCMD,System Command of the transaction that caused the error" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 5.--7. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 4. "ERRORNOTSUPPADD,Not supported Address error" "0,1" newline rbitfld.long 0x8 3. "ERRORNOTSUPPMCMD,Not supported Command error" "0,1" newline rbitfld.long 0x8 2. "ERRORTIMEOUT,Time-out error" "0,1" newline bitfld.long 0x8 1. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1" newline bitfld.long 0x8 0. "ERRORVALID,Error validity status - Must be explicitely cleared with a write 1 transaction" "0,1" group.long 0x50++0x7 line.long 0x0 "CFG_GPMC_CONFIG,The configuration register allows global configuration of the GPMC" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline bitfld.long 0x0 11. "WAIT3PINPOLARITY,Selects the polarity of input pin WAIT3" "0,1" newline bitfld.long 0x0 10. "WAIT2PINPOLARITY,Selects the polarity of input pin WAIT2" "0,1" newline bitfld.long 0x0 9. "WAIT1PINPOLARITY,Selects the polarity of input pin WAIT1" "0,1" newline bitfld.long 0x0 8. "WAIT0PINPOLARITY,Selects the polarity of input pin WAIT0" "0,1" newline bitfld.long 0x0 5.--7. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "WRITEPROTECT,Controls the WP output pin level" "0,1" newline bitfld.long 0x0 2.--3. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3" newline bitfld.long 0x0 1. "LIMITEDADDRESS,Limited Address device support" "0,1" newline bitfld.long 0x0 0. "NANDFORCEPOSTEDWRITE,Enables the Force Posted Write feature to NAND Cmd/Add/Data location" "0,1" line.long 0x4 "CFG_GPMC_STATUS,The status register provides global status bits of the GPMC" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline rbitfld.long 0x4 11. "WAIT3STATUS,Is a copy of input pin WAIT3. [Reset value is WAIT3 input pin sampled at IC reset]" "0,1" newline rbitfld.long 0x4 10. "WAIT2STATUS,Is a copy of input pin WAIT2. [Reset value is WAIT2 input pin sampled at IC reset]" "0,1" newline rbitfld.long 0x4 9. "WAIT1STATUS,Is a copy of input pin WAIT1. [Reset value is WAIT1 input pin sampled at IC reset]" "0,1" newline rbitfld.long 0x4 8. "WAIT0STATUS,Is a copy of input pin WAIT0. [Reset value is WAIT0 input pin sampled at IC reset]" "0,1" newline hexmask.long.byte 0x4 1.--7. 1. "RESERVED,Write 0's for future compatibility Reads returns 0" newline rbitfld.long 0x4 0. "EMPTYWRITEBUFFERSTATUS,Stores the empty status of the write buffer" "0,1" group.long 0x1E0++0x7 line.long 0x0 "CFG_GPMC_PREFETCH_CONFIG1,Prefetch engine configuration 1" bitfld.long 0x0 31. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1" newline bitfld.long 0x0 28.--30. "CYCLEOPTIMIZATION,Define the number of GPMC.FCLK cycles to be substracted from RdCycleTime WrCycleTime AccessTime CSRdOffTime CSWrOffTime ADVRdOffTime ADVWrOffTime OEOffTime WEOffTime [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 27. "ENABLEOPTIMIZEDACCESS,Enables access cycle optimization" "0,1" newline bitfld.long 0x0 24.--26. "ENGINECSSELECTOR,Selects the CS where Prefetch Postwrite engine is active [0x0 corresponds toCS0 0x1 corresponds to CS1 & 0x7 corresponds to CS7]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "PFPWENROUNDROBIN,Enables the PFPW RoundRobin arbitration" "0,1" newline bitfld.long 0x0 20.--22. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "PFPWWEIGHTEDPRIO,When an arbitration occurs between a direct memory access and a PFPW engine access the direct memory access is always serviced. If the PFPWEnRoundRobin is enabled 0x0 means : the next access is granted to the PFPW engine 0x1 means :.." newline bitfld.long 0x0 15. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "FIFOTHRESHOLD,Selects the maximum number of bytes read from the FIFO or written to the FIFO by the host on a DMA or interrupt request [0x00 corresponds to 0 byte 0x01 corresponds to 1 byte & 0x40 corresponds to 64 bytes]" newline bitfld.long 0x0 7. "ENABLEENGINE,Enables the Prefetch Postwite engine" "0,1" newline bitfld.long 0x0 6. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1" newline bitfld.long 0x0 4.--5. "WAITPINSELECTOR,Select which wait pin edge detector should start the engine in synchronized mode" "0,1,2,3" newline bitfld.long 0x0 3. "SYNCHROMODE,Selects when the engine starts the access to CS" "0,1" newline bitfld.long 0x0 2. "DMAMODE,Selects interrupt synchronization or DMA request synchronization" "0,1" newline bitfld.long 0x0 1. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1" newline bitfld.long 0x0 0. "ACCESSMODE,Selects pre-fetch read or write posting accesses" "0,1" line.long 0x4 "CFG_GPMC_PREFETCH_CONFIG2,Prefetch engine configuration 2" hexmask.long.tbyte 0x4 14.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline hexmask.long.word 0x4 0.--13. 1. "TRANSFERCOUNT,Selects the number of bytes to be read or written by the engine to the selected CS [0x0000 corresponds to 0 byte 0x0001 corresponds to 1 byte & 0x2000 corresponds to 8 Kbytes]" group.long 0x1EC++0x17 line.long 0x0 "CFG_GPMC_PREFETCH_CONTROL,Prefetch engine control" hexmask.long 0x0 1.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline bitfld.long 0x0 0. "STARTENGINE,Resets the FIFO pointer and starts the engine" "0,1" line.long 0x4 "CFG_GPMC_PREFETCH_STATUS,Prefetch engine status" bitfld.long 0x4 31. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1" newline hexmask.long.byte 0x4 24.--30. 1. "FIFOPOINTER,Number of available bytes to be read or number of free empty byte places to be written [0x00 corresponds to 0 byte available to be read or 0 free empty place to be written & 0x40 corresponds to 64 bytes available to be read or 64 empty.." newline hexmask.long.byte 0x4 17.--23. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline rbitfld.long 0x4 16. "FIFOTHRESHOLDSTATUS,Set when FIFOPointer exceeds FIFOThreshold value" "0,1" newline bitfld.long 0x4 14.--15. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3" newline hexmask.long.word 0x4 0.--13. 1. "COUNTVALUE,Number of remaining bytes to be read or to be written by the engine according to the TransferCount value [0x0000 corresponds to 0 byte remaining to be read or to be written 0x0001 corresponds to 1 byte remaining to be read or to be written .." line.long 0x8 "CFG_GPMC_ECC_CONFIG,ECC configuration" hexmask.long.word 0x8 17.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline bitfld.long 0x8 16. "ECCALGORITHM,ECC algorithm used 0x0: Hamming code 0x1: BCH code" "0: Hamming code 0x1: BCH code,?" newline bitfld.long 0x8 14.--15. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3" newline bitfld.long 0x8 12.--13. "ECCBCHTSEL,Error correction capability used for BCH 0x0: up to 4 bits error correction [t = 4] 0x1: up to 8 bits error correction [t=8] 0x2: up to 16 bits error correction [t=16] 0x3: reserved" "0: up to 4 bits error correction [t = 4] 0x1: up to..,?,?,?" newline hexmask.long.byte 0x8 8.--11. 1. "ECCWRAPMODE,Spare area organization definition for the BCH algorithm. See the BCH syndrome/parity calculator module functional specification for more details" newline bitfld.long 0x8 7. "ECC16B,Selects an ECC calculated on 16 columns" "0,1" newline bitfld.long 0x8 4.--6. "ECCTOPSECTOR,Number of sectors to process with the BCH algorithm 0x0: 1 sector [512kB page] 0x1: 2 sectors ... 0x3: 4 sectors [2kB page] ... 0x7: 8 sectors [4kB page]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 1.--3. "ECCCS,Selects the CS where ECC is computed" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "ECCENABLE,Enables the ECC feature" "0,1" line.long 0xC "CFG_GPMC_ECC_CONTROL,ECC control" hexmask.long.tbyte 0xC 9.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline bitfld.long 0xC 8. "ECCCLEAR,Clear all ECC result registers [Reads returns 0 - Writes 1 to this field clear all ECC result registers - Writes 0 are ignored]" "0: Writes 1 to this field clear all ECC result..,?" newline hexmask.long.byte 0xC 4.--7. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline hexmask.long.byte 0xC 0.--3. 1. "ECCPOINTER,Selects ECC result register [Reads to this field give the dynamic position of the ECC pointer - Writes to this field select the ECC result register where the first ECC computation will be stored]; Other enums: writing other values disables the.." line.long 0x10 "CFG_GPMC_ECC_SIZE_CONFIG,ECC size" bitfld.long 0x10 30.--31. "RESERVED,Write 0's for future compatibility. Read returns 3" "0,1,2,3" newline hexmask.long.byte 0x10 22.--29. 1. "ECCSIZE1,Defines ECC size 1 [0x00 corresponds to 2 Bytes 0x01 corresponds to 4 Bytes 0x02 corresponds to 6 Bytes 0x03 corresponds to 8 Bytes & 0xFF corresponds to 512 Bytes]" newline bitfld.long 0x10 20.--21. "RESERVED,Write 0's for future compatibility. Read returns 3" "0,1,2,3" newline hexmask.long.byte 0x10 12.--19. 1. "ECCSIZE0,Defines ECC size 0 [0x00 corresponds to 2 Bytes 0x01 corresponds to 4 Bytes 0x02 corresponds to 6 Bytes 0x03 corresponds to 8 Bytes & 0xFF corresponds to 512 Bytes]" newline bitfld.long 0x10 9.--11. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "ECC9RESULTSIZE,Selects ECC size for ECC 9 result register" "0,1" newline bitfld.long 0x10 7. "ECC8RESULTSIZE,Selects ECC size for ECC 8 result register" "0,1" newline bitfld.long 0x10 6. "ECC7RESULTSIZE,Selects ECC size for ECC 7 result register" "0,1" newline bitfld.long 0x10 5. "ECC6RESULTSIZE,Selects ECC size for ECC 6 result register" "0,1" newline bitfld.long 0x10 4. "ECC5RESULTSIZE,Selects ECC size for ECC 5 result register" "0,1" newline bitfld.long 0x10 3. "ECC4RESULTSIZE,Selects ECC size for ECC 4 result register" "0,1" newline bitfld.long 0x10 2. "ECC3RESULTSIZE,Selects ECC size for ECC 3 result register" "0,1" newline bitfld.long 0x10 1. "ECC2RESULTSIZE,Selects ECC size for ECC 2 result register" "0,1" newline bitfld.long 0x10 0. "ECC1RESULTSIZE,Selects ECC size for ECC 1 result register" "0,1" line.long 0x14 "CFG_GPMC_ECC_RESULT,ECC result register" hexmask.long.byte 0x14 28.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline rbitfld.long 0x14 27. "P2048O,Odd Row Parity bit 2048 only used for ECC computed on 512 Bytes" "0,1" newline rbitfld.long 0x14 26. "P1024O,Odd Row Parity bit 1024" "0,1" newline rbitfld.long 0x14 25. "P512O,Odd Row Parity bit 512" "0,1" newline rbitfld.long 0x14 24. "P256O,Odd Row Parity bit 256" "0,1" newline rbitfld.long 0x14 23. "P128O,Odd Row Parity bit 128" "0,1" newline rbitfld.long 0x14 22. "P64O,Odd Row Parity bit 64" "0,1" newline rbitfld.long 0x14 21. "P32O,Odd Row Parity bit 32" "0,1" newline rbitfld.long 0x14 20. "P16O,Odd Row Parity bit 16" "0,1" newline rbitfld.long 0x14 19. "P8O,Odd Row Parity bit 8" "0,1" newline rbitfld.long 0x14 18. "P4O,Odd Column Parity bit 4" "0,1" newline rbitfld.long 0x14 17. "P2O,Odd Column Parity bit 2" "0,1" newline rbitfld.long 0x14 16. "P1O,Odd Column Parity bit 1" "0,1" newline hexmask.long.byte 0x14 12.--15. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline rbitfld.long 0x14 11. "P2048E,Even Row Parity bit 2048 only used for ECC computed on 512 Bytes" "0,1" newline rbitfld.long 0x14 10. "P1024E,Even Row Parity bit 1024" "0,1" newline rbitfld.long 0x14 9. "P512E,Even Row Parity bit 512" "0,1" newline rbitfld.long 0x14 8. "P256E,Even Row Parity bit 256" "0,1" newline rbitfld.long 0x14 7. "P128E,Even Row Parity bit 128" "0,1" newline rbitfld.long 0x14 6. "P64E,Even Row Parity bit 64" "0,1" newline rbitfld.long 0x14 5. "P32E,Even Row Parity bit 32" "0,1" newline rbitfld.long 0x14 4. "P16E,Even Row Parity bit 16" "0,1" newline rbitfld.long 0x14 3. "P8E,Even Row Parity bit 8" "0,1" newline rbitfld.long 0x14 2. "P4E,Even Column Parity bit 4" "0,1" newline rbitfld.long 0x14 1. "P2E,Even Column Parity bit 2" "0,1" newline rbitfld.long 0x14 0. "P1E,Even Column Parity bit 1" "0,1" wgroup.long 0x2D0++0x3 line.long 0x0 "CFG_GPMC_BCH_SWDATA,This register is used to directly pass data to the BCH ECC calculator without accessing the actual NAND flash interface." hexmask.long.word 0x0 0.--15. 1. "BCH_DATA,Data to be included in the BCH calculation. Only bits 0 to 7 are taken into account if the calculator is configured to use 8 bits data [ECC16B = 0]" wgroup.long 0x60++0x1B line.long 0x0 "CFG_GPMC_CONFIG1,The configuration 1 register sets signal control parameters per chip select" bitfld.long 0x0 31. "WRAPBURST,Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst" "0,1" newline bitfld.long 0x0 30. "READMULTIPLE,Selects the read single or multiple access" "0,1" newline bitfld.long 0x0 29. "READTYPE,Selects the read mode operation" "0,1" newline bitfld.long 0x0 28. "WRITEMULTIPLE,Selects the write single or multiple access" "0,1" newline bitfld.long 0x0 27. "WRITETYPE,Selects the write mode operation" "0,1" newline bitfld.long 0x0 25.--26. "CLKACTIVATIONTIME,Output GPMC.CLK activation time" "0,1,2,3" newline bitfld.long 0x0 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page [burst] length" "0,1,2,3" newline bitfld.long 0x0 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses [Reset value is BOOTWAITEN input pin sampled at IC reset]" "0,1" newline bitfld.long 0x0 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "0,1" newline bitfld.long 0x0 20. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1" newline bitfld.long 0x0 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "0,1,2,3" newline bitfld.long 0x0 16.--17. "WAITPINSELECT,Selects the input WAIT pin for this chip select [Reset value is BOOTWAITSELECT input pin sampled at IC reset for CS0 and 0 for CS1-7]" "0,1,2,3" newline bitfld.long 0x0 14.--15. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3" newline bitfld.long 0x0 12.--13. "DEVICESIZE,Selects the device size attached [Reset value is BOOTDEVICESIZE input pin sampled at IC reset for CS0 and 01 for CS1-7]" "0,1,2,3" newline bitfld.long 0x0 10.--11. "DEVICETYPE,Selects the attached device type" "0,1,2,3" newline bitfld.long 0x0 8.--9. "MUXADDDATA,Enables the Address and data multiplexed protocol [Reset value is CS0MUXDEVICE input pin sampled at IC reset for CS0 and 0 for CS1-7]" "0,1,2,3" newline bitfld.long 0x0 5.--7. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor [Rd/WRCycleTime AccessTime PageBurstAccessTime CSOnTime CSRd/WrOffTime ADVOnTime ADVRd/WrOffTime OEOnTime OEOffTime WEOnTime WEOffTime Cycle2CycleDelay BusTurnAround TimeOutStartValue]" "0,1" newline bitfld.long 0x0 2.--3. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3" newline bitfld.long 0x0 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC.FCLK clock" "0,1,2,3" line.long 0x4 "CFG_GPMC_CONFIG2,Chip-select signal timing parameter configuration" hexmask.long.word 0x4 21.--31. 1. "RESERVED,Write 0's for future compatibility Reads returns 0" newline hexmask.long.byte 0x4 16.--20. 1. "CSWROFFTIME,CS# de-assertion time from start cycle time for write accesses [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" newline bitfld.long 0x4 13.--15. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--12. 1. "CSRDOFFTIME,CS# de-assertion time from start cycle time for read accesses [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" newline bitfld.long 0x4 7. "CSEXTRADELAY,CS# Add Extra Half GPMC.FCLK cycle" "0,1" newline bitfld.long 0x4 4.--6. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--3. 1. "CSONTIME,CS# assertion time from start cycle time [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1 GPMC.FCLK cycle & 0xF corresponds to 15 GPMC.FCLK cycles]" line.long 0x8 "CFG_GPMC_CONFIG3,ADV# signal timing parameter configuration" rbitfld.long 0x8 31. "RESERVED_1,Write 0's for future compatibility. Read returns 0" "0,1" newline bitfld.long 0x8 28.--30. "ADVAADMUXWROFFTIME,ADV# de-assertion for first address phase when using the AAD-Mux protocol" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 27. "RESERVED_0,Write 0's for future compatibility. Read returns 0" "0,1" newline bitfld.long 0x8 24.--26. "ADVAADMUXRDOFFTIME,ADV# assertion for first address phase when using the AAD-Mux protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 21.--23. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 16.--20. 1. "ADVWROFFTIME,ADV# de-assertion time from start cycle time for write accesses [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" newline bitfld.long 0x8 13.--15. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--12. 1. "ADVRDOFFTIME,ADV# de-assertion time from start cycle time for read accesses[0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" newline bitfld.long 0x8 7. "ADVEXTRADELAY,ADV# Add Extra Half GPMC.FCLK cycle" "0,1" newline bitfld.long 0x8 4.--6. "ADVAADMUXONTIME,ADV# assertion for first address phase when using the AAD-Mux protocol" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--3. 1. "ADVONTIME,ADV# assertion time from start cycle time [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1 GPMC.FCLK cycle & 0xF corresponds to 15 GPMC.FCLK cycles]" line.long 0xC "CFG_GPMC_CONFIG4,WE# and OE# signals timing parameter configuration" rbitfld.long 0xC 29.--31. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 24.--28. 1. "WEOFFTIME,WE# de-assertion time from start cycle time [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" newline bitfld.long 0xC 23. "WEEXTRADELAY,WE# Add Extra Half GPMC.FCLK cycle" "0,1" newline bitfld.long 0xC 20.--22. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--19. 1. "WEONTIME,WE# assertion time from start cycle time [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1 GPMC.FCLK cycle & 0xF corresponds to 15 GPMC.FCLK cycles]" newline bitfld.long 0xC 13.--15. "OEAADMUXOFFTIME,OE# de-assertion time for the first address phase in an AAD-Mux access" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--12. 1. "OEOFFTIME,OE# de-assertion time from start cycle time [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" newline bitfld.long 0xC 7. "OEEXTRADELAY,OE# Add Extra Half GPMC.FCLK cycle" "0,1" newline bitfld.long 0xC 4.--6. "OEAADMUXONTIME,OE# assertion time for the first address phase in an AAD-Mux access" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 0.--3. 1. "OEONTIME,OE# assertion time from start cycle time [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1 GPMC.FCLK cycle & 0xF corresponds to 15 GPMC.FCLK cycles]" line.long 0x10 "CFG_GPMC_CONFIG5,RdAccessTime and CycleTime timing parameters configuration" hexmask.long.byte 0x10 28.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline hexmask.long.byte 0x10 24.--27. 1. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1 GPMC.FCLK cycle & 0xF corresponds to 15 GPMC.FCLK cycles]" newline bitfld.long 0x10 21.--23. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 16.--20. 1. "RDACCESSTIME,Delay between start cycle time and first data valid [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" newline bitfld.long 0x10 13.--15. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 8.--12. 1. "WRCYCLETIME,Total write cycle time [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" newline bitfld.long 0x10 5.--7. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--4. 1. "RDCYCLETIME,Total read cycle time [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" line.long 0x14 "CFG_GPMC_CONFIG6,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x14 31. "RESERVED,TI Internal use - Do not modify" "0,1" newline bitfld.long 0x14 29.--30. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3" newline hexmask.long.byte 0x14 24.--28. 1. "WRACCESSTIME,Delay from StartAccessTime to the GPMC.FCLK rising edge corresponding the the GPMC.CLK rising edge used by the attached memory for the first data capture [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F.." newline hexmask.long.byte 0x14 20.--23. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline hexmask.long.byte 0x14 16.--19. 1. "WRDATAONADMUXBUS,Specifies on which GPMC.FCLK rising edge the first data of the synchronous burst write is driven in the add/data mux bus" newline hexmask.long.byte 0x14 12.--15. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline hexmask.long.byte 0x14 8.--11. 1. "CYCLE2CYCLEDELAY,Chip select high pulse delay between two successive accesses [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1 GPMC.FCLK cycle & 0xF corresponds to 15 GPMC.FCLK cycles]" newline bitfld.long 0x14 7. "CYCLE2CYCLESAMECSEN,Add Cycle2CycleDelay between two successive accesses to the same chip-select [any access type]" "0,1" newline bitfld.long 0x14 6. "CYCLE2CYCLEDIFFCSEN,Add Cycle2CycleDelay between two successive accesses to a different chip-select [any access type]" "0,1" newline bitfld.long 0x14 4.--5. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1,2,3" newline hexmask.long.byte 0x14 0.--3. 1. "BUSTURNAROUND,Bus turn around latency between two successive accesses to the same chip-select [rd to wr] or to a different chip-select [read to read and read to write] [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1 GPMC.FCLK cycle & 0xF.." line.long 0x18 "CFG_GPMC_CONFIG7,Chip-select address mapping configuration" hexmask.long.tbyte 0x18 12.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline hexmask.long.byte 0x18 8.--11. 1. "MASKADDRESS,Chip-select mask address" newline bitfld.long 0x18 7. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1" newline bitfld.long 0x18 6. "CSVALID,Chip-select enable [reset value is 1 for CS0 and 0 for CS1-7]" "0,1" newline hexmask.long.byte 0x18 0.--5. 1. "BASEADDRESS,Chip-select base address" wgroup.long 0x7C++0x7 line.long 0x0 "CFG_GPMC_NAND_COMMAND,This Register is not a true register. just a address location." hexmask.long 0x0 0.--31. 1. "GPMC_NAND_COMMAND_0," line.long 0x4 "CFG_GPMC_NAND_ADDRESS,This Register is not a true register. just a address location." hexmask.long 0x4 0.--31. 1. "GPMC_NAND_ADDRESS_0," wgroup.long 0x84++0x3 line.long 0x0 "CFG_GPMC_NAND_DATA,This Register is not a true register. just a address location." hexmask.long 0x0 0.--31. 1. "GPMC_NAND_DATA_0," rgroup.long 0x240++0xF line.long 0x0 "CFG_GPMC_BCH_RESULT_0,BCH ECC result. bits 0 to 31" hexmask.long 0x0 0.--31. 1. "BCH_RESULT_0,BCH ECC result bits 0 to 31" line.long 0x4 "CFG_GPMC_BCH_RESULT_1,BCH ECC result. bits 32 to 63" hexmask.long 0x4 0.--31. 1. "BCH_RESULT_1,BCH ECC result bits 32 to 63" line.long 0x8 "CFG_GPMC_BCH_RESULT_2,BCH ECC result. bits 64 to 95" hexmask.long 0x8 0.--31. 1. "BCH_RESULT_2,BCH ECC result bits 64 to 95" line.long 0xC "CFG_GPMC_BCH_RESULT_3,BCH ECC result. bits 96 to 127" hexmask.long 0xC 0.--31. 1. "BCH_RESULT_3,BCH ECC result bits 96 to 127" rgroup.long 0x300++0xB line.long 0x0 "CFG_GPMC_BCH_RESULT_4,BCH ECC result. bits 128 to 159" hexmask.long 0x0 0.--31. 1. "BCH_RESULT_4,BCH ECC result bits 128 to 159" line.long 0x4 "CFG_GPMC_BCH_RESULT_5,BCH ECC result. bits 160 to 191" hexmask.long 0x4 0.--31. 1. "BCH_RESULT_5,BCH ECC result bits 160 to 191" line.long 0x8 "CFG_GPMC_BCH_RESULT_6,BCH ECC result. bits 192 to 207" hexmask.long.word 0x8 0.--15. 1. "BCH_RESULT_6,BCH ECC result bits 192 to 207" tree.end tree "GTC0_GTC" base ad:0x0 tree "GTC0_GTC_CFG0 (GTC0_GTC_CFG0)" base ad:0xA80000 rgroup.long 0x0++0x7 line.long 0x0 "GTC_CFG0_PID," hexmask.long.word 0x0 16.--31. 1. "PID_MSB16," hexmask.long.byte 0x0 11.--15. 1. "PID_MISC," bitfld.long 0x0 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "PID_CUSTOM," "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR," line.long 0x4 "GTC_CFG0_GTC_PID," bitfld.long 0x4 30.--31. "GTC_PID_SCHEME,PID follows new scheme" "0,1,2,3" bitfld.long 0x4 28.--29. "GTC_PID_BU,Business unit - Processors" "0,1,2,3" hexmask.long.word 0x4 16.--27. 1. "GTC_PID_FUNC,Module functional identifier - GTC module" hexmask.long.byte 0x4 11.--15. 1. "GTC_PID_R_RTL,RTL revision number - actual value determined by RTL" bitfld.long 0x4 8.--10. "GTC_PID_X_MAJOR,Major revision number - actual value determined by RTL" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6.--7. "GTC_PID_CUSTOM,Custom revision number - actual value determined by RTL" "0,1,2,3" hexmask.long.byte 0x4 0.--5. 1. "GTC_PID_Y_MINOR,Minor revision number - actual value determined by RTL" rgroup.long 0x8++0x3 line.long 0x0 "GTC_CFG0_PUSHEVT," hexmask.long.byte 0x0 0.--5. 1. "PUSHEVT_EXPBIT_SEL,Selects which bit [63:0] of the System Counter value is exported on the push_evt output. This field controls the 64:1 mux that drives the push_evt output." tree.end tree "GTC0_GTC_CFG1 (GTC0_GTC_CFG1)" base ad:0xA90000 rgroup.long 0x0++0x3 line.long 0x0 "GTC_CFG1_CNTCR," hexmask.long.tbyte 0x0 8.--31. 1. "CNTCR_FCREQ,Frequency Change Request" bitfld.long 0x0 1. "CNTCR_HDBG,Halt on Debug" "0,1" bitfld.long 0x0 0. "CNTCR_EN,Enable System Counter" "0,1" rgroup.long 0x4++0xB line.long 0x0 "GTC_CFG1_CNTSR," hexmask.long.tbyte 0x0 8.--31. 1. "CNTSR_FCACK,Frequency Change Ackowledge" bitfld.long 0x0 1. "CNTSR_DBGH,Debug Halt" "0,1" line.long 0x4 "GTC_CFG1_CNTCV_LO," hexmask.long 0x4 0.--31. 1. "CNTCV_LO_COUNTVALUE,Indicates bits [31:0] of the System Counter value." line.long 0x8 "GTC_CFG1_CNTCV_HI," hexmask.long 0x8 0.--31. 1. "CNTCV_HI_COUNTVALUE,Indicates bits [63:32] of the System Counter value." rgroup.long 0x20++0x3 line.long 0x0 "GTC_CFG1_CNTFID0," hexmask.long 0x0 0.--31. 1. "CNTFID0_FREQVALUE,Indicates the base update frequency of the System Counter in Hz." rgroup.long 0x24++0x3 line.long 0x0 "GTC_CFG1_CNTFID1," hexmask.long 0x0 0.--31. 1. "CNTFID1_FREQVALUE,Frequency table end indicator" tree.end tree "GTC0_GTC_CFG2 (GTC0_GTC_CFG2)" base ad:0xAA0000 rgroup.long 0x0++0x7 line.long 0x0 "GTC_CFG2_CNTCVS_LO," hexmask.long 0x0 0.--31. 1. "CNTCVS_LO_COUNTVALUE,Indicates bits [31:0] of the System Counter value." line.long 0x4 "GTC_CFG2_CNTCVS_HI," hexmask.long 0x4 0.--31. 1. "CNTCVS_HI_COUNTVALUE,Indicates bits [63:32] of the System Counter value." tree.end tree "GTC0_GTC_CFG3 (GTC0_GTC_CFG3)" base ad:0xAB0000 rgroup.long 0x8++0x3 line.long 0x0 "GTC_CFG3_CNTTIDR," hexmask.long.byte 0x0 28.--31. 1. "CNTTIDR_FRAME7,Indicates the features of timer frame7. Each 4 bit field has the following meaning:" hexmask.long.byte 0x0 24.--27. 1. "CNTTIDR_FRAME6,Indicates the features of timer frame6. Each 4 bit field has the following meaning:" hexmask.long.byte 0x0 20.--23. 1. "CNTTIDR_FRAME5,Indicates the features of timer frame5. Each 4 bit field has the following meaning:" hexmask.long.byte 0x0 16.--19. 1. "CNTTIDR_FRAME4,Indicates the features of timer frame4. Each 4 bit field has the following meaning:" hexmask.long.byte 0x0 12.--15. 1. "CNTTIDR_FRAME3,Indicates the features of timer frame3. Each 4 bit field has the following meaning:" hexmask.long.byte 0x0 8.--11. 1. "CNTTIDR_FRAME2,Indicates the features of timer frame2. Each 4 bit field has the following meaning:" hexmask.long.byte 0x0 4.--7. 1. "CNTTIDR_FRAME1,Indicates the features of timer frame1. Each 4 bit field has the following meaning:" newline hexmask.long.byte 0x0 0.--3. 1. "CNTTIDR_FRAME0,Indicates the features of timer frame0. Each 4 bit field has the following meaning:" tree.end tree.end tree "I2C" base ad:0x0 tree "I2C0_CFG (I2C0_CFG)" base ad:0x2000000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "CFG_I2C_REVNB_HI,Revision Number register (High)" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" rgroup.long 0x10++0x3 line.long 0x0 "CFG_I2C_SYSC,System Configuration register" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" bitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" newline bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CFG_I2C_EOI,End Of Interrupt number specification" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" rgroup.long 0x24++0x2B line.long 0x0 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x0 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x0 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x0 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x0 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x0 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x0 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x0 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x0 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x4 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ enabled status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ enabled status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x8 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x8 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x8 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x8 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x8 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x8 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x8 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x8 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x8 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x8 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x8 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x8 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x8 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0xC "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0xC 11. "ROVR,Receive overrun enable clear" "0,1" newline bitfld.long 0xC 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x10 "CFG_I2C_WE,I2C wakeup enable vector (legacy)." bitfld.long 0x10 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x10 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x10 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x10 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x10 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x10 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x10 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x10 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x10 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x10 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x10 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x14 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.long 0x14 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x18 "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.long 0x18 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x1C "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.long 0x1C 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x20 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.long 0x20 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x24 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.long 0x24 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x24 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x24 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x24 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x24 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x24 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x24 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x24 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x24 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x24 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x24 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x24 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x28 "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" rgroup.long 0x84++0x7 line.long 0x0 "CFG_I2C_IE,I2C interrupt enable vector (legacy)." bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x4 "CFG_I2C_STAT,I2C interrupt status vector (legacy)." bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "CFG_I2C_SYSS,System Status register" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" rgroup.long 0x94++0xB line.long 0x0 "CFG_I2C_BUF,Buffer Configuration register" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "CFG_I2C_CNT,Data counter register" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "CFG_I2C_DATA,Data access register" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" rgroup.long 0xA4++0x1B line.long 0x0 "CFG_I2C_CON,I2C configuration register." bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" newline bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "CFG_I2C_OA,Own address register" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "CFG_I2C_SA,Slave address register" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "CFG_I2C_PSC,I2C Clock Prescaler Register" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 0xFF: Divide by 256" line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register." hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register." hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register." bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" newline bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "CFG_I2C_BUFSTAT,I2C Buffer Status Register." bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" rgroup.long 0xC4++0xB line.long 0x0 "CFG_I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "CFG_I2C_OA2,I2C Own Address 2" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "CFG_I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "CFG_I2C_ACTOA,I2C Active Own Address Register." bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" rgroup.long 0xD4++0x3 line.long 0x0 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree "I2C1_CFG (I2C1_CFG)" base ad:0x2010000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "CFG_I2C_REVNB_HI,Revision Number register (High)" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" rgroup.long 0x10++0x3 line.long 0x0 "CFG_I2C_SYSC,System Configuration register" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" bitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" newline bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CFG_I2C_EOI,End Of Interrupt number specification" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" rgroup.long 0x24++0x2B line.long 0x0 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x0 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x0 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x0 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x0 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x0 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x0 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x0 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x0 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x4 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ enabled status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ enabled status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x8 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x8 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x8 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x8 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x8 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x8 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x8 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x8 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x8 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x8 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x8 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x8 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x8 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0xC "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0xC 11. "ROVR,Receive overrun enable clear" "0,1" newline bitfld.long 0xC 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x10 "CFG_I2C_WE,I2C wakeup enable vector (legacy)." bitfld.long 0x10 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x10 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x10 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x10 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x10 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x10 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x10 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x10 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x10 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x10 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x10 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x14 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.long 0x14 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x18 "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.long 0x18 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x1C "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.long 0x1C 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x20 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.long 0x20 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x24 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.long 0x24 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x24 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x24 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x24 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x24 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x24 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x24 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x24 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x24 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x24 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x24 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x24 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x28 "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" rgroup.long 0x84++0x7 line.long 0x0 "CFG_I2C_IE,I2C interrupt enable vector (legacy)." bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x4 "CFG_I2C_STAT,I2C interrupt status vector (legacy)." bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "CFG_I2C_SYSS,System Status register" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" rgroup.long 0x94++0xB line.long 0x0 "CFG_I2C_BUF,Buffer Configuration register" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "CFG_I2C_CNT,Data counter register" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "CFG_I2C_DATA,Data access register" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" rgroup.long 0xA4++0x1B line.long 0x0 "CFG_I2C_CON,I2C configuration register." bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" newline bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "CFG_I2C_OA,Own address register" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "CFG_I2C_SA,Slave address register" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "CFG_I2C_PSC,I2C Clock Prescaler Register" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 0xFF: Divide by 256" line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register." hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register." hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register." bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" newline bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "CFG_I2C_BUFSTAT,I2C Buffer Status Register." bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" rgroup.long 0xC4++0xB line.long 0x0 "CFG_I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "CFG_I2C_OA2,I2C Own Address 2" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "CFG_I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "CFG_I2C_ACTOA,I2C Active Own Address Register." bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" rgroup.long 0xD4++0x3 line.long 0x0 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree "I2C2_CFG (I2C2_CFG)" base ad:0x2020000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "CFG_I2C_REVNB_HI,Revision Number register (High)" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" rgroup.long 0x10++0x3 line.long 0x0 "CFG_I2C_SYSC,System Configuration register" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" bitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" newline bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CFG_I2C_EOI,End Of Interrupt number specification" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" rgroup.long 0x24++0x2B line.long 0x0 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x0 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x0 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x0 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x0 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x0 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x0 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x0 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x0 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x4 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ enabled status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ enabled status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x8 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x8 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x8 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x8 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x8 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x8 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x8 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x8 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x8 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x8 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x8 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x8 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x8 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0xC "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0xC 11. "ROVR,Receive overrun enable clear" "0,1" newline bitfld.long 0xC 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x10 "CFG_I2C_WE,I2C wakeup enable vector (legacy)." bitfld.long 0x10 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x10 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x10 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x10 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x10 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x10 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x10 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x10 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x10 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x10 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x10 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x14 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.long 0x14 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x18 "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.long 0x18 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x1C "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.long 0x1C 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x20 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.long 0x20 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x24 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.long 0x24 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x24 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x24 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x24 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x24 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x24 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x24 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x24 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x24 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x24 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x24 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x24 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x28 "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" rgroup.long 0x84++0x7 line.long 0x0 "CFG_I2C_IE,I2C interrupt enable vector (legacy)." bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x4 "CFG_I2C_STAT,I2C interrupt status vector (legacy)." bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "CFG_I2C_SYSS,System Status register" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" rgroup.long 0x94++0xB line.long 0x0 "CFG_I2C_BUF,Buffer Configuration register" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "CFG_I2C_CNT,Data counter register" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "CFG_I2C_DATA,Data access register" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" rgroup.long 0xA4++0x1B line.long 0x0 "CFG_I2C_CON,I2C configuration register." bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" newline bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "CFG_I2C_OA,Own address register" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "CFG_I2C_SA,Slave address register" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "CFG_I2C_PSC,I2C Clock Prescaler Register" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 0xFF: Divide by 256" line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register." hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register." hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register." bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" newline bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "CFG_I2C_BUFSTAT,I2C Buffer Status Register." bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" rgroup.long 0xC4++0xB line.long 0x0 "CFG_I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "CFG_I2C_OA2,I2C Own Address 2" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "CFG_I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "CFG_I2C_ACTOA,I2C Active Own Address Register." bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" rgroup.long 0xD4++0x3 line.long 0x0 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree "I2C3_CFG (I2C3_CFG)" base ad:0x2030000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "CFG_I2C_REVNB_HI,Revision Number register (High)" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" rgroup.long 0x10++0x3 line.long 0x0 "CFG_I2C_SYSC,System Configuration register" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" bitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" newline bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CFG_I2C_EOI,End Of Interrupt number specification" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" rgroup.long 0x24++0x2B line.long 0x0 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x0 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x0 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x0 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x0 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x0 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x0 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x0 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x0 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x4 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ enabled status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ enabled status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x8 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x8 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x8 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x8 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x8 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x8 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x8 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x8 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x8 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x8 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x8 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x8 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x8 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0xC "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0xC 11. "ROVR,Receive overrun enable clear" "0,1" newline bitfld.long 0xC 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x10 "CFG_I2C_WE,I2C wakeup enable vector (legacy)." bitfld.long 0x10 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x10 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x10 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x10 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x10 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x10 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x10 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x10 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x10 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x10 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x10 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x14 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.long 0x14 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x18 "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.long 0x18 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x1C "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.long 0x1C 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x20 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.long 0x20 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x24 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.long 0x24 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x24 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x24 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x24 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x24 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x24 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x24 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x24 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x24 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x24 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x24 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x24 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x28 "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" rgroup.long 0x84++0x7 line.long 0x0 "CFG_I2C_IE,I2C interrupt enable vector (legacy)." bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x4 "CFG_I2C_STAT,I2C interrupt status vector (legacy)." bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "CFG_I2C_SYSS,System Status register" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" rgroup.long 0x94++0xB line.long 0x0 "CFG_I2C_BUF,Buffer Configuration register" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "CFG_I2C_CNT,Data counter register" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "CFG_I2C_DATA,Data access register" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" rgroup.long 0xA4++0x1B line.long 0x0 "CFG_I2C_CON,I2C configuration register." bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" newline bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "CFG_I2C_OA,Own address register" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "CFG_I2C_SA,Slave address register" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "CFG_I2C_PSC,I2C Clock Prescaler Register" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 0xFF: Divide by 256" line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register." hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register." hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register." bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" newline bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "CFG_I2C_BUFSTAT,I2C Buffer Status Register." bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" rgroup.long 0xC4++0xB line.long 0x0 "CFG_I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "CFG_I2C_OA2,I2C Own Address 2" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "CFG_I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "CFG_I2C_ACTOA,I2C Active Own Address Register." bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" rgroup.long 0xD4++0x3 line.long 0x0 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree "I2C4_CFG (I2C4_CFG)" base ad:0x2040000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "CFG_I2C_REVNB_HI,Revision Number register (High)" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" rgroup.long 0x10++0x3 line.long 0x0 "CFG_I2C_SYSC,System Configuration register" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" bitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" newline bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CFG_I2C_EOI,End Of Interrupt number specification" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" rgroup.long 0x24++0x2B line.long 0x0 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x0 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x0 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x0 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x0 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x0 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x0 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x0 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x0 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x4 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ enabled status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ enabled status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x8 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x8 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x8 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x8 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x8 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x8 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x8 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x8 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x8 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x8 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x8 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x8 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x8 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0xC "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0xC 11. "ROVR,Receive overrun enable clear" "0,1" newline bitfld.long 0xC 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x10 "CFG_I2C_WE,I2C wakeup enable vector (legacy)." bitfld.long 0x10 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x10 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x10 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x10 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x10 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x10 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x10 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x10 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x10 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x10 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x10 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x14 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.long 0x14 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x18 "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.long 0x18 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x1C "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.long 0x1C 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x20 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.long 0x20 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x24 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.long 0x24 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x24 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x24 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x24 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x24 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x24 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x24 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x24 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x24 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x24 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x24 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x24 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x28 "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" rgroup.long 0x84++0x7 line.long 0x0 "CFG_I2C_IE,I2C interrupt enable vector (legacy)." bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x4 "CFG_I2C_STAT,I2C interrupt status vector (legacy)." bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "CFG_I2C_SYSS,System Status register" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" rgroup.long 0x94++0xB line.long 0x0 "CFG_I2C_BUF,Buffer Configuration register" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "CFG_I2C_CNT,Data counter register" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "CFG_I2C_DATA,Data access register" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" rgroup.long 0xA4++0x1B line.long 0x0 "CFG_I2C_CON,I2C configuration register." bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" newline bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "CFG_I2C_OA,Own address register" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "CFG_I2C_SA,Slave address register" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "CFG_I2C_PSC,I2C Clock Prescaler Register" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 0xFF: Divide by 256" line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register." hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register." hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register." bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" newline bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "CFG_I2C_BUFSTAT,I2C Buffer Status Register." bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" rgroup.long 0xC4++0xB line.long 0x0 "CFG_I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "CFG_I2C_OA2,I2C Own Address 2" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "CFG_I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "CFG_I2C_ACTOA,I2C Active Own Address Register." bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" rgroup.long 0xD4++0x3 line.long 0x0 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree "I2C5_CFG (I2C5_CFG)" base ad:0x2050000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "CFG_I2C_REVNB_HI,Revision Number register (High)" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" rgroup.long 0x10++0x3 line.long 0x0 "CFG_I2C_SYSC,System Configuration register" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" bitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" newline bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CFG_I2C_EOI,End Of Interrupt number specification" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" rgroup.long 0x24++0x2B line.long 0x0 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x0 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x0 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x0 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x0 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x0 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x0 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x0 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x0 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x4 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ enabled status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ enabled status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x8 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x8 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x8 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x8 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x8 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x8 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x8 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x8 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x8 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x8 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x8 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x8 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x8 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0xC "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0xC 11. "ROVR,Receive overrun enable clear" "0,1" newline bitfld.long 0xC 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x10 "CFG_I2C_WE,I2C wakeup enable vector (legacy)." bitfld.long 0x10 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x10 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x10 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x10 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x10 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x10 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x10 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x10 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x10 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x10 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x10 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x14 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.long 0x14 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x18 "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.long 0x18 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x1C "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.long 0x1C 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x20 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.long 0x20 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x24 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.long 0x24 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x24 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x24 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x24 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x24 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x24 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x24 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x24 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x24 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x24 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x24 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x24 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x28 "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" rgroup.long 0x84++0x7 line.long 0x0 "CFG_I2C_IE,I2C interrupt enable vector (legacy)." bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x4 "CFG_I2C_STAT,I2C interrupt status vector (legacy)." bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "CFG_I2C_SYSS,System Status register" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" rgroup.long 0x94++0xB line.long 0x0 "CFG_I2C_BUF,Buffer Configuration register" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "CFG_I2C_CNT,Data counter register" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "CFG_I2C_DATA,Data access register" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" rgroup.long 0xA4++0x1B line.long 0x0 "CFG_I2C_CON,I2C configuration register." bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" newline bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "CFG_I2C_OA,Own address register" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "CFG_I2C_SA,Slave address register" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "CFG_I2C_PSC,I2C Clock Prescaler Register" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 0xFF: Divide by 256" line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register." hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register." hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register." bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" newline bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "CFG_I2C_BUFSTAT,I2C Buffer Status Register." bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" rgroup.long 0xC4++0xB line.long 0x0 "CFG_I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "CFG_I2C_OA2,I2C Own Address 2" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "CFG_I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "CFG_I2C_ACTOA,I2C Active Own Address Register." bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" rgroup.long 0xD4++0x3 line.long 0x0 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree "I2C6_CFG (I2C6_CFG)" base ad:0x2060000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "CFG_I2C_REVNB_HI,Revision Number register (High)" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" rgroup.long 0x10++0x3 line.long 0x0 "CFG_I2C_SYSC,System Configuration register" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" bitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" newline bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CFG_I2C_EOI,End Of Interrupt number specification" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" rgroup.long 0x24++0x2B line.long 0x0 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x0 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x0 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x0 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x0 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x0 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x0 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x0 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x0 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x4 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ enabled status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ enabled status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x8 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x8 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x8 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x8 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x8 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x8 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x8 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x8 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x8 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x8 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x8 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x8 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x8 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0xC "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0xC 11. "ROVR,Receive overrun enable clear" "0,1" newline bitfld.long 0xC 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x10 "CFG_I2C_WE,I2C wakeup enable vector (legacy)." bitfld.long 0x10 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x10 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x10 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x10 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x10 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x10 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x10 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x10 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x10 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x10 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x10 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x14 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.long 0x14 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x18 "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.long 0x18 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x1C "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.long 0x1C 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x20 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.long 0x20 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x24 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.long 0x24 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x24 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x24 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x24 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x24 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x24 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x24 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x24 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x24 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x24 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x24 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x24 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x28 "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" rgroup.long 0x84++0x7 line.long 0x0 "CFG_I2C_IE,I2C interrupt enable vector (legacy)." bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x4 "CFG_I2C_STAT,I2C interrupt status vector (legacy)." bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "CFG_I2C_SYSS,System Status register" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" rgroup.long 0x94++0xB line.long 0x0 "CFG_I2C_BUF,Buffer Configuration register" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "CFG_I2C_CNT,Data counter register" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "CFG_I2C_DATA,Data access register" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" rgroup.long 0xA4++0x1B line.long 0x0 "CFG_I2C_CON,I2C configuration register." bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" newline bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "CFG_I2C_OA,Own address register" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "CFG_I2C_SA,Slave address register" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "CFG_I2C_PSC,I2C Clock Prescaler Register" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 0xFF: Divide by 256" line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register." hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register." hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register." bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" newline bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "CFG_I2C_BUFSTAT,I2C Buffer Status Register." bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" rgroup.long 0xC4++0xB line.long 0x0 "CFG_I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "CFG_I2C_OA2,I2C Own Address 2" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "CFG_I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "CFG_I2C_ACTOA,I2C Active Own Address Register." bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" rgroup.long 0xD4++0x3 line.long 0x0 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree.end tree "Igpu_main_0_m0" base ad:0x0 tree "Igpu_main_0_m0_vbusm_r_async_bw_limiter0_REGS (Igpu_main_0_m0_vbusm_r_async_bw_limiter0_REGS)" base ad:0x48006000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_PID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,PID function identifier" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "REGS_CTRL,This register controls the overall behavior of the rate limiter module" bitfld.long 0x0 4. "REGION_FILTER_EN,Enable the region filter which will only apply the bandwith and transaction limits to the configured address regions" "0,1" bitfld.long 0x0 3. "WR_TXN_ENABLE,Enable limiting maximum outstanding write transactions" "0,1" bitfld.long 0x0 2. "RD_TXN_ENABLE,Enable limiting maximum outstanding read transactions" "0,1" bitfld.long 0x0 1. "WR_BW_ENABLE,Enable write bandwidth limiting" "0,1" bitfld.long 0x0 0. "RD_BW_ENABLE,Enable read bandwidth limiting" "0,1" rgroup.long 0x100++0xB line.long 0x0 "REGS_RD_BW_CIR,Read Bandwidth Committed Information Rate" hexmask.long 0x0 0.--31. 1. "CIR,Committed Information Rate" line.long 0x4 "REGS_RD_BW_PIR,Read Bandwidth Peak Information Rate" hexmask.long 0x4 0.--31. 1. "PIR,Peak Information Rate" line.long 0x8 "REGS_RD_BW_BURST_OFFSET,Read Bandwidth Burst Offset" hexmask.long.word 0x8 0.--15. 1. "OFFSET,Burst Offset - the number of bytes before the Committed Information Rate is applied at startup or after a period of inactivity. Peak Information Rate will still apply" rgroup.long 0x10C++0x3 line.long 0x0 "REGS_RD_BW_INFO,Read Bandwidth State machine information. Primarly for verification purposes" bitfld.long 0x0 0.--1. "COLOR,Read Bandwidth three-color marker output from rategen submodule" "0,1,2,3" rgroup.long 0x120++0x7 line.long 0x0 "REGS_RD_BW_STATS,Read Bandwidth Statistics Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable read bandwidth statistics" "0,1" line.long 0x4 "REGS_RD_BW_STATS_THRSHLD,A statistics threshold separate from the CIR and PIR" hexmask.long 0x4 0.--31. 1. "THRESHOLD,Read bandwidth stats threshold in bytes. Note that this is total bytes unlike CIR and PIR. CIR and PIR are based on a rolling window and the statistics threshold is based on a fixed window. This will still take into account DDR bytes used so.." rgroup.long 0x128++0x13 line.long 0x0 "REGS_RD_BW_WINDOWS_CNT,Read Bandwidth Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Read bandwidth window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_RD_BW_CIR_CNT,Read Bandwidth Statistics - CIR Count" hexmask.long 0x4 0.--31. 1. "VAL,The total number of statistics windows in which Read Commit Information Rate occurred. Note that if PIR is set to a lower value than CIR or if the burst offset feature is used this will also count times that PIR is reached." line.long 0x8 "REGS_RD_BW_PIR_CNT,Read Bandwidth Statistics - PIR Count" hexmask.long 0x8 0.--31. 1. "VAL,The total number of statistics windows in which Read Peak Information Rate occurred" line.long 0xC "REGS_RD_BW_THRSHLD_CNT,Read Bandwidth Statistics - Threshold Count" hexmask.long 0xC 0.--31. 1. "VAL,The total number of statistics windows in which Read bytes transferred exceeded the statistics threshold" line.long 0x10 "REGS_RD_BYTES_MAX,The maximum number of bytes seen in a single statitsics window. This can be compared with the window size to calculate the maximum bandwidth seen" hexmask.long 0x10 0.--31. 1. "VAL,Max number of bytes in a single window. This number accounts for DDR bandwidth consumed not simply the accumulation of the packet bytecnt values across a window. The max bandwidth calculation is the total bytes value in this MMR divided by the.." rgroup.long 0x300++0x3 line.long 0x0 "REGS_RD_TXN,The maximum number of outstanding read transactions the rate limiter will allow" hexmask.long.word 0x0 0.--15. 1. "LIMIT,The maximum number of outstanding read transactions allowed. NOTE: This cannot be programmed to a zero. If a zero is written it will default to the reset value of 16'd64 as a limit of zero outstanding transactions would hang the interface." rgroup.long 0x30C++0x3 line.long 0x0 "REGS_RD_TXN_INFO,Read Transaction State machine information. Primarly for verification purposes" hexmask.long.byte 0x0 0.--6. 1. "OCC,Read transaction scoreboard occupancy" rgroup.long 0x320++0x7 line.long 0x0 "REGS_RD_TXN_STATS,Read Transaction Stats Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable read transaction statistics" "0,1" line.long 0x4 "REGS_RD_TXN_STATS_THRSHLD,A statistics threshold separate from the read transaction limit" hexmask.long.word 0x4 0.--15. 1. "THRESHOLD,Read transaction statistics threshold. The threshold can be set to any value though it will saturate at the outstanding transaction limit if it is set to a value greater than the programmed outstanding read transaction limit" rgroup.long 0x328++0x17 line.long 0x0 "REGS_RD_TXN_WINDOWS_CNT,Read Transaction Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Read transaction window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_RD_TXN_LMT_CNT,Read Transaction Statistics - number of windows in which the outstanding transaction limit was reached" hexmask.long 0x4 0.--31. 1. "VAL,The number of statistics windows in which the outstanding read transaction limit was reached" line.long 0x8 "REGS_RD_TXN_THRSHLD_CNT,Read Transaction Statistics - number of windows in which the statistics threshold was reached" hexmask.long 0x8 0.--31. 1. "VAL,The number of statistics windows in which the number of outstanding read transactions was greater than or equal to the threshold in RD_TXN_STATS_THRSHLD" line.long 0xC "REGS_RD_TXN_LIMIT_TOTAL,Read Transaction Statistics - Cycles at Outstanding Read Transactions Limit" hexmask.long 0xC 0.--31. 1. "VAL,The total number of cycles with the read transactions outstanding at the programmed limit since statistics collection began" line.long 0x10 "REGS_RD_TXN_THRSHLD_TOTAL,Read Transaction Statistics - Cycles at the Statistics Threshold" hexmask.long 0x10 0.--31. 1. "VAL,The total number of cycles with read transactions outstanding greater than or equal to the statistics threshold in RD_TXN_STATS_THRSHLD since statistics collection began" line.long 0x14 "REGS_RD_TXN_MAX,Read Transaction Statistics - Max Observed Outstanding Read Transactions" hexmask.long.word 0x14 0.--15. 1. "VAL,The maximum outstanding read transactions at any point in time regardless of the programmed limit" tree.end tree "Igpu_main_0_m0_vbusm_w_async_bw_limiter0_REGS (Igpu_main_0_m0_vbusm_w_async_bw_limiter0_REGS)" base ad:0x48007000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_PID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,PID function identifier" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "REGS_CTRL,This register controls the overall behavior of the rate limiter module" bitfld.long 0x0 4. "REGION_FILTER_EN,Enable the region filter which will only apply the bandwith and transaction limits to the configured address regions" "0,1" bitfld.long 0x0 3. "WR_TXN_ENABLE,Enable limiting maximum outstanding write transactions" "0,1" bitfld.long 0x0 2. "RD_TXN_ENABLE,Enable limiting maximum outstanding read transactions" "0,1" bitfld.long 0x0 1. "WR_BW_ENABLE,Enable write bandwidth limiting" "0,1" bitfld.long 0x0 0. "RD_BW_ENABLE,Enable read bandwidth limiting" "0,1" rgroup.long 0x200++0xB line.long 0x0 "REGS_WR_BW_CIR,Write Bandwidth Committed Information Rate" hexmask.long 0x0 0.--31. 1. "CIR,Committed Information Rate" line.long 0x4 "REGS_WR_BW_PIR,Write Bandwidth Peak Information Rate" hexmask.long 0x4 0.--31. 1. "PIR,Peak Information Rate" line.long 0x8 "REGS_WR_BW_BURST_OFFSET,Write Bandwidth Burst Offset" hexmask.long.word 0x8 0.--15. 1. "OFFSET,Burst Offset - the number of bytes before the Committed Information Rate is applied at startup or after a period of inactivity. Peak Information Rate will still apply" rgroup.long 0x20C++0x3 line.long 0x0 "REGS_WR_BW_INFO,Write Bandwidth State machine information. Primarly for verification purposes" bitfld.long 0x0 0.--1. "COLOR,Write Bandwidth three-color marker output from rategen submodule" "0,1,2,3" rgroup.long 0x220++0x7 line.long 0x0 "REGS_WR_BW_STATS,Write Bandwidth Statistics Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable write bandwidth statistics" "0,1" line.long 0x4 "REGS_WR_BW_STATS_THRSHLD,A statistics threshold separate from the CIR and PIR" hexmask.long 0x4 0.--31. 1. "THRESHOLD,Write bandwidth stats threshold in bytes. Note that this is total bytes unlike CIR and PIR. CIR and PIR are based on a rolling window and the statistics threshold is based on a fixed window. This will still take into account DDR bytes used .." rgroup.long 0x228++0x13 line.long 0x0 "REGS_WR_BW_WINDOWS_CNT,Write Bandwidth Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Write bandwidth window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_WR_BW_CIR_CNT,Write Bandwidth Statistics - CIR Count" hexmask.long 0x4 0.--31. 1. "VAL,The total number of statistics windows in which Write Commit Information Rate occurred. Note that if PIR is set to a lower value than CIR or if the burst offset feature is used this will also count times that PIR is reached." line.long 0x8 "REGS_WR_BW_PIR_CNT,Write Bandwidth Statistics - PIR Count" hexmask.long 0x8 0.--31. 1. "VAL,The total number of statistics windows in which Write Peak Information Rate occurred" line.long 0xC "REGS_WR_BW_THRSHLD_CNT,Write Bandwidth Statistics - Threshold Count" hexmask.long 0xC 0.--31. 1. "VAL,The total number of statistics windows in which Write bytes transferred exceeded the statistics threshold" line.long 0x10 "REGS_WR_BYTES_MAX,The maximum number of bytes seen in a single statitsics window. This can be compared with the window size to calculate the maximum bandwidth seen" hexmask.long 0x10 0.--31. 1. "VAL,Max number of bytes in a single window. This number accounts for DDR bandwidth consumed not simply the accumulation of the packet bytecnt values across a window. The max bandwidth calculation is the total bytes value in this MMR divided by the.." rgroup.long 0x400++0x3 line.long 0x0 "REGS_WR_TXN,The maximum number of outstanding write transactions the rate limiter will allow" hexmask.long.word 0x0 0.--15. 1. "LIMIT,The maximum number of outstanding write transactions allowed. NOTE: This cannot be programmed to a zero. If a zero is written it will default to the reset value of 16'd64 as a limit of zero outstanding transactions would hang the interface." rgroup.long 0x40C++0x3 line.long 0x0 "REGS_WR_TXN_INFO,Write Transaction State machine information. Primarly for verification purposes" hexmask.long.byte 0x0 0.--6. 1. "OCC,Write transaction scoreboard occupancy" rgroup.long 0x420++0x7 line.long 0x0 "REGS_WR_TXN_STATS,Write Transaction Stats Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable write transaction statistics" "0,1" line.long 0x4 "REGS_WR_TXN_STATS_THRSHLD,A statistics threshold separate from the write transaction limit" hexmask.long.word 0x4 0.--15. 1. "THRESHOLD,Write transaction statistics threshold. The threshold can be set to any value though it will saturate at the outstanding transaction limit if it is set to a value greater than the programmed outstanding write transaction limit" rgroup.long 0x428++0x17 line.long 0x0 "REGS_WR_TXN_WINDOWS_CNT,Write Transaction Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Write transaction window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_WR_TXN_LMT_CNT,Write Transaction Statistics - number of windows in which the outstanding transaction limit was reached" hexmask.long 0x4 0.--31. 1. "VAL,The number of statistics windows in which the outstanding write transaction limit was reached" line.long 0x8 "REGS_WR_TXN_THRSHLD_CNT,Write Transaction Statistics - number of windows in which the statistics threshold was reached" hexmask.long 0x8 0.--31. 1. "VAL,The number of statistics windows in which the number of outstanding write transactions was greater than or equal to the threshold in WR_TXN_STATS_THRSHLD" line.long 0xC "REGS_WR_TXN_LIMIT_TOTAL,Write Transaction Statistics - Cycles at Outstanding Write Transactions Limit" hexmask.long 0xC 0.--31. 1. "VAL,The total number of cycles with the write transactions outstanding at the programmed limit since statistics collection began" line.long 0x10 "REGS_WR_TXN_THRSHLD_TOTAL,Write Transaction Statistics - Cycles at the Statistics Threshold" hexmask.long 0x10 0.--31. 1. "VAL,The total number of cycles with write transactions outstanding greater than or equal to the statistics threshold in WR_TXN_STATS_THRSHLD since statistics collection began" line.long 0x14 "REGS_WR_TXN_MAX,Write Transaction Statistics - Max Observed Outstanding Write Transactions" hexmask.long.word 0x14 0.--15. 1. "VAL,The maximum outstanding write transactions at any point in time regardless of the programmed limit" tree.end tree.end tree "Ij7am_cnm_wave521cl_main" base ad:0x0 tree "Ij7am_cnm_wave521cl_main_0_pri_m_vbusm_r_bw_limiter0_REGS (Ij7am_cnm_wave521cl_main_0_pri_m_vbusm_r_bw_limiter0_REGS)" base ad:0x48000000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_PID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,PID function identifier" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "REGS_CTRL,This register controls the overall behavior of the rate limiter module" bitfld.long 0x0 4. "REGION_FILTER_EN,Enable the region filter which will only apply the bandwith and transaction limits to the configured address regions" "0,1" bitfld.long 0x0 3. "WR_TXN_ENABLE,Enable limiting maximum outstanding write transactions" "0,1" bitfld.long 0x0 2. "RD_TXN_ENABLE,Enable limiting maximum outstanding read transactions" "0,1" bitfld.long 0x0 1. "WR_BW_ENABLE,Enable write bandwidth limiting" "0,1" bitfld.long 0x0 0. "RD_BW_ENABLE,Enable read bandwidth limiting" "0,1" rgroup.long 0x100++0xB line.long 0x0 "REGS_RD_BW_CIR,Read Bandwidth Committed Information Rate" hexmask.long 0x0 0.--31. 1. "CIR,Committed Information Rate" line.long 0x4 "REGS_RD_BW_PIR,Read Bandwidth Peak Information Rate" hexmask.long 0x4 0.--31. 1. "PIR,Peak Information Rate" line.long 0x8 "REGS_RD_BW_BURST_OFFSET,Read Bandwidth Burst Offset" hexmask.long.word 0x8 0.--15. 1. "OFFSET,Burst Offset - the number of bytes before the Committed Information Rate is applied at startup or after a period of inactivity. Peak Information Rate will still apply" rgroup.long 0x10C++0x3 line.long 0x0 "REGS_RD_BW_INFO,Read Bandwidth State machine information. Primarly for verification purposes" bitfld.long 0x0 0.--1. "COLOR,Read Bandwidth three-color marker output from rategen submodule" "0,1,2,3" rgroup.long 0x120++0x7 line.long 0x0 "REGS_RD_BW_STATS,Read Bandwidth Statistics Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable read bandwidth statistics" "0,1" line.long 0x4 "REGS_RD_BW_STATS_THRSHLD,A statistics threshold separate from the CIR and PIR" hexmask.long 0x4 0.--31. 1. "THRESHOLD,Read bandwidth stats threshold in bytes. Note that this is total bytes unlike CIR and PIR. CIR and PIR are based on a rolling window and the statistics threshold is based on a fixed window. This will still take into account DDR bytes used so.." rgroup.long 0x128++0x13 line.long 0x0 "REGS_RD_BW_WINDOWS_CNT,Read Bandwidth Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Read bandwidth window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_RD_BW_CIR_CNT,Read Bandwidth Statistics - CIR Count" hexmask.long 0x4 0.--31. 1. "VAL,The total number of statistics windows in which Read Commit Information Rate occurred. Note that if PIR is set to a lower value than CIR or if the burst offset feature is used this will also count times that PIR is reached." line.long 0x8 "REGS_RD_BW_PIR_CNT,Read Bandwidth Statistics - PIR Count" hexmask.long 0x8 0.--31. 1. "VAL,The total number of statistics windows in which Read Peak Information Rate occurred" line.long 0xC "REGS_RD_BW_THRSHLD_CNT,Read Bandwidth Statistics - Threshold Count" hexmask.long 0xC 0.--31. 1. "VAL,The total number of statistics windows in which Read bytes transferred exceeded the statistics threshold" line.long 0x10 "REGS_RD_BYTES_MAX,The maximum number of bytes seen in a single statitsics window. This can be compared with the window size to calculate the maximum bandwidth seen" hexmask.long 0x10 0.--31. 1. "VAL,Max number of bytes in a single window. This number accounts for DDR bandwidth consumed not simply the accumulation of the packet bytecnt values across a window. The max bandwidth calculation is the total bytes value in this MMR divided by the.." rgroup.long 0x300++0x3 line.long 0x0 "REGS_RD_TXN,The maximum number of outstanding read transactions the rate limiter will allow" hexmask.long.word 0x0 0.--15. 1. "LIMIT,The maximum number of outstanding read transactions allowed. NOTE: This cannot be programmed to a zero. If a zero is written it will default to the reset value of 16'd64 as a limit of zero outstanding transactions would hang the interface." rgroup.long 0x30C++0x3 line.long 0x0 "REGS_RD_TXN_INFO,Read Transaction State machine information. Primarly for verification purposes" hexmask.long.byte 0x0 0.--6. 1. "OCC,Read transaction scoreboard occupancy" rgroup.long 0x320++0x7 line.long 0x0 "REGS_RD_TXN_STATS,Read Transaction Stats Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable read transaction statistics" "0,1" line.long 0x4 "REGS_RD_TXN_STATS_THRSHLD,A statistics threshold separate from the read transaction limit" hexmask.long.word 0x4 0.--15. 1. "THRESHOLD,Read transaction statistics threshold. The threshold can be set to any value though it will saturate at the outstanding transaction limit if it is set to a value greater than the programmed outstanding read transaction limit" rgroup.long 0x328++0x17 line.long 0x0 "REGS_RD_TXN_WINDOWS_CNT,Read Transaction Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Read transaction window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_RD_TXN_LMT_CNT,Read Transaction Statistics - number of windows in which the outstanding transaction limit was reached" hexmask.long 0x4 0.--31. 1. "VAL,The number of statistics windows in which the outstanding read transaction limit was reached" line.long 0x8 "REGS_RD_TXN_THRSHLD_CNT,Read Transaction Statistics - number of windows in which the statistics threshold was reached" hexmask.long 0x8 0.--31. 1. "VAL,The number of statistics windows in which the number of outstanding read transactions was greater than or equal to the threshold in RD_TXN_STATS_THRSHLD" line.long 0xC "REGS_RD_TXN_LIMIT_TOTAL,Read Transaction Statistics - Cycles at Outstanding Read Transactions Limit" hexmask.long 0xC 0.--31. 1. "VAL,The total number of cycles with the read transactions outstanding at the programmed limit since statistics collection began" line.long 0x10 "REGS_RD_TXN_THRSHLD_TOTAL,Read Transaction Statistics - Cycles at the Statistics Threshold" hexmask.long 0x10 0.--31. 1. "VAL,The total number of cycles with read transactions outstanding greater than or equal to the statistics threshold in RD_TXN_STATS_THRSHLD since statistics collection began" line.long 0x14 "REGS_RD_TXN_MAX,Read Transaction Statistics - Max Observed Outstanding Read Transactions" hexmask.long.word 0x14 0.--15. 1. "VAL,The maximum outstanding read transactions at any point in time regardless of the programmed limit" tree.end tree "Ij7am_cnm_wave521cl_main_0_pri_m_vbusm_w_bw_limiter0_REGS (Ij7am_cnm_wave521cl_main_0_pri_m_vbusm_w_bw_limiter0_REGS)" base ad:0x48001000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_PID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,PID function identifier" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "REGS_CTRL,This register controls the overall behavior of the rate limiter module" bitfld.long 0x0 4. "REGION_FILTER_EN,Enable the region filter which will only apply the bandwith and transaction limits to the configured address regions" "0,1" bitfld.long 0x0 3. "WR_TXN_ENABLE,Enable limiting maximum outstanding write transactions" "0,1" bitfld.long 0x0 2. "RD_TXN_ENABLE,Enable limiting maximum outstanding read transactions" "0,1" bitfld.long 0x0 1. "WR_BW_ENABLE,Enable write bandwidth limiting" "0,1" bitfld.long 0x0 0. "RD_BW_ENABLE,Enable read bandwidth limiting" "0,1" rgroup.long 0x200++0xB line.long 0x0 "REGS_WR_BW_CIR,Write Bandwidth Committed Information Rate" hexmask.long 0x0 0.--31. 1. "CIR,Committed Information Rate" line.long 0x4 "REGS_WR_BW_PIR,Write Bandwidth Peak Information Rate" hexmask.long 0x4 0.--31. 1. "PIR,Peak Information Rate" line.long 0x8 "REGS_WR_BW_BURST_OFFSET,Write Bandwidth Burst Offset" hexmask.long.word 0x8 0.--15. 1. "OFFSET,Burst Offset - the number of bytes before the Committed Information Rate is applied at startup or after a period of inactivity. Peak Information Rate will still apply" rgroup.long 0x20C++0x3 line.long 0x0 "REGS_WR_BW_INFO,Write Bandwidth State machine information. Primarly for verification purposes" bitfld.long 0x0 0.--1. "COLOR,Write Bandwidth three-color marker output from rategen submodule" "0,1,2,3" rgroup.long 0x220++0x7 line.long 0x0 "REGS_WR_BW_STATS,Write Bandwidth Statistics Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable write bandwidth statistics" "0,1" line.long 0x4 "REGS_WR_BW_STATS_THRSHLD,A statistics threshold separate from the CIR and PIR" hexmask.long 0x4 0.--31. 1. "THRESHOLD,Write bandwidth stats threshold in bytes. Note that this is total bytes unlike CIR and PIR. CIR and PIR are based on a rolling window and the statistics threshold is based on a fixed window. This will still take into account DDR bytes used .." rgroup.long 0x228++0x13 line.long 0x0 "REGS_WR_BW_WINDOWS_CNT,Write Bandwidth Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Write bandwidth window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_WR_BW_CIR_CNT,Write Bandwidth Statistics - CIR Count" hexmask.long 0x4 0.--31. 1. "VAL,The total number of statistics windows in which Write Commit Information Rate occurred. Note that if PIR is set to a lower value than CIR or if the burst offset feature is used this will also count times that PIR is reached." line.long 0x8 "REGS_WR_BW_PIR_CNT,Write Bandwidth Statistics - PIR Count" hexmask.long 0x8 0.--31. 1. "VAL,The total number of statistics windows in which Write Peak Information Rate occurred" line.long 0xC "REGS_WR_BW_THRSHLD_CNT,Write Bandwidth Statistics - Threshold Count" hexmask.long 0xC 0.--31. 1. "VAL,The total number of statistics windows in which Write bytes transferred exceeded the statistics threshold" line.long 0x10 "REGS_WR_BYTES_MAX,The maximum number of bytes seen in a single statitsics window. This can be compared with the window size to calculate the maximum bandwidth seen" hexmask.long 0x10 0.--31. 1. "VAL,Max number of bytes in a single window. This number accounts for DDR bandwidth consumed not simply the accumulation of the packet bytecnt values across a window. The max bandwidth calculation is the total bytes value in this MMR divided by the.." rgroup.long 0x400++0x3 line.long 0x0 "REGS_WR_TXN,The maximum number of outstanding write transactions the rate limiter will allow" hexmask.long.word 0x0 0.--15. 1. "LIMIT,The maximum number of outstanding write transactions allowed. NOTE: This cannot be programmed to a zero. If a zero is written it will default to the reset value of 16'd64 as a limit of zero outstanding transactions would hang the interface." rgroup.long 0x40C++0x3 line.long 0x0 "REGS_WR_TXN_INFO,Write Transaction State machine information. Primarly for verification purposes" hexmask.long.byte 0x0 0.--6. 1. "OCC,Write transaction scoreboard occupancy" rgroup.long 0x420++0x7 line.long 0x0 "REGS_WR_TXN_STATS,Write Transaction Stats Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable write transaction statistics" "0,1" line.long 0x4 "REGS_WR_TXN_STATS_THRSHLD,A statistics threshold separate from the write transaction limit" hexmask.long.word 0x4 0.--15. 1. "THRESHOLD,Write transaction statistics threshold. The threshold can be set to any value though it will saturate at the outstanding transaction limit if it is set to a value greater than the programmed outstanding write transaction limit" rgroup.long 0x428++0x17 line.long 0x0 "REGS_WR_TXN_WINDOWS_CNT,Write Transaction Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Write transaction window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_WR_TXN_LMT_CNT,Write Transaction Statistics - number of windows in which the outstanding transaction limit was reached" hexmask.long 0x4 0.--31. 1. "VAL,The number of statistics windows in which the outstanding write transaction limit was reached" line.long 0x8 "REGS_WR_TXN_THRSHLD_CNT,Write Transaction Statistics - number of windows in which the statistics threshold was reached" hexmask.long 0x8 0.--31. 1. "VAL,The number of statistics windows in which the number of outstanding write transactions was greater than or equal to the threshold in WR_TXN_STATS_THRSHLD" line.long 0xC "REGS_WR_TXN_LIMIT_TOTAL,Write Transaction Statistics - Cycles at Outstanding Write Transactions Limit" hexmask.long 0xC 0.--31. 1. "VAL,The total number of cycles with the write transactions outstanding at the programmed limit since statistics collection began" line.long 0x10 "REGS_WR_TXN_THRSHLD_TOTAL,Write Transaction Statistics - Cycles at the Statistics Threshold" hexmask.long 0x10 0.--31. 1. "VAL,The total number of cycles with write transactions outstanding greater than or equal to the statistics threshold in WR_TXN_STATS_THRSHLD since statistics collection began" line.long 0x14 "REGS_WR_TXN_MAX,Write Transaction Statistics - Max Observed Outstanding Write Transactions" hexmask.long.word 0x14 0.--15. 1. "VAL,The maximum outstanding write transactions at any point in time regardless of the programmed limit" tree.end tree.end tree "Ij7vc" base ad:0x0 tree "Ij7vc_dom0_ecc" tree "Ij7vc_dom0_ecc_aggr16_REGS (Ij7vc_dom0_ecc_aggr16_REGS)" base ad:0x2AF0000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 13. "IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_wmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_rmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 11. "IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 9. "IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 8. "IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 7. "IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 6. "IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 5. "IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 4. "IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_p2p_cpu0_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 2. "IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_p2p_cpu0_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_cpu0_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 13. "IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_wmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_rmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_p2p_cpu0_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_p2p_cpu0_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_cpu0_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 13. "IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_wmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_rmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_p2p_cpu0_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_p2p_cpu0_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_cpu0_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 13. "IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_wmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_rmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 11. "IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 9. "IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 8. "IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 7. "IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 6. "IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 5. "IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 4. "IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_p2p_cpu0_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 2. "IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_p2p_cpu0_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_cpu0_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 13. "IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_wmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_rmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_p2p_cpu0_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_p2p_cpu0_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_cpu0_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 13. "IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_wmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_rmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_p2p_cpu0_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_p2p_cpu0_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_cpu0_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "Ij7vc_dom0_ecc_aggr18_REGS (Ij7vc_dom0_ecc_aggr18_REGS)" base ad:0x2AF2000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 13. "IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_wmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_rmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 11. "IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 9. "IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 8. "IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 7. "IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 6. "IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 5. "IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 4. "IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_p2p_cpu0_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 2. "IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_p2p_cpu0_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_cpu0_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 13. "IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_wmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_rmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_p2p_cpu0_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_p2p_cpu0_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_cpu0_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 13. "IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_wmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_rmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_p2p_cpu0_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_p2p_cpu0_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_cpu0_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 13. "IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_wmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_rmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 11. "IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 9. "IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 8. "IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 7. "IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 6. "IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 5. "IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 4. "IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_p2p_cpu0_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 2. "IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_p2p_cpu0_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_cpu0_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 13. "IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_wmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_rmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_p2p_cpu0_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_p2p_cpu0_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_cpu0_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 13. "IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_wmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_rmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_p2p_cpu0_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_p2p_cpu0_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_cpu0_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "Ij7vc_dom0_ecc_aggr20_REGS (Ij7vc_dom0_ecc_aggr20_REGS)" base ad:0x2AE0000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 13. "IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_wmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_rmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 11. "IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 9. "IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 8. "IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 7. "IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 6. "IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 5. "IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 4. "IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_p2p_cpu0_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 2. "IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_p2p_cpu0_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_cpu0_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 13. "IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_wmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_rmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_p2p_cpu0_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_p2p_cpu0_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_cpu0_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 13. "IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_wmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_rmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_p2p_cpu0_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_p2p_cpu0_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_cpu0_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 13. "IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_wmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_rmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 11. "IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 9. "IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 8. "IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_pbdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 7. "IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 6. "IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 5. "IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 4. "IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_membdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_p2p_cpu0_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 2. "IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_p2p_cpu0_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom0_m2m_cpu0_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 13. "IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_wmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_rmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_pbdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_membdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_p2p_cpu0_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_p2p_cpu0_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom0_m2m_cpu0_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 13. "IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_wmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_rmst0_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_pbdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_wmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_wmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_rmst0_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_membdg_rmst0_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_p2p_cpu0_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_p2p_cpu0_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom0_m2m_cpu0_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree.end tree "Ij7vc_dom1_ecc" tree "Ij7vc_dom1_ecc_aggr17_REGS (Ij7vc_dom1_ecc_aggr17_REGS)" base ad:0x2AF1000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 14. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x4 13. "IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_wmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_rmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 11. "IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 9. "IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 8. "IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 7. "IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 6. "IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 5. "IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 4. "IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_p2p_cpu1_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 2. "IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_p2p_cpu1_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_cpu1_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 0. "IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_cpu1_slv_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 14. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x0 13. "IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_wmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_rmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_p2p_cpu1_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_p2p_cpu1_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_cpu1_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_cpu1_slv_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 14. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x0 13. "IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_wmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_rmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_p2p_cpu1_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_p2p_cpu1_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_cpu1_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_cpu1_slv_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 14. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x4 13. "IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_wmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_rmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 11. "IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 9. "IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 8. "IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 7. "IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 6. "IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 5. "IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 4. "IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_p2p_cpu1_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 2. "IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_p2p_cpu1_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_cpu1_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 0. "IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_cpu1_slv_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 14. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x0 13. "IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_wmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_rmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_p2p_cpu1_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_p2p_cpu1_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_cpu1_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_cpu1_slv_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 14. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x0 13. "IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_wmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_rmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_p2p_cpu1_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_p2p_cpu1_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_cpu1_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_cpu1_slv_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "Ij7vc_dom1_ecc_aggr19_REGS (Ij7vc_dom1_ecc_aggr19_REGS)" base ad:0x2AF3000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 14. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x4 13. "IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_wmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_rmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 11. "IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 9. "IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 8. "IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 7. "IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 6. "IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 5. "IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 4. "IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_p2p_cpu1_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 2. "IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_p2p_cpu1_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_cpu1_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 0. "IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_cpu1_slv_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 14. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x0 13. "IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_wmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_rmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_p2p_cpu1_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_p2p_cpu1_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_cpu1_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_cpu1_slv_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 14. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x0 13. "IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_wmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_rmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_p2p_cpu1_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_p2p_cpu1_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_cpu1_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_cpu1_slv_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 14. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x4 13. "IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_wmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_rmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 11. "IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 9. "IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 8. "IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 7. "IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 6. "IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 5. "IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 4. "IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_p2p_cpu1_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 2. "IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_p2p_cpu1_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_cpu1_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 0. "IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_cpu1_slv_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 14. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x0 13. "IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_wmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_rmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_p2p_cpu1_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_p2p_cpu1_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_cpu1_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_cpu1_slv_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 14. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x0 13. "IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_wmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_rmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_p2p_cpu1_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_p2p_cpu1_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_cpu1_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_cpu1_slv_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "Ij7vc_dom1_ecc_aggr21_REGS (Ij7vc_dom1_ecc_aggr21_REGS)" base ad:0x2AE1000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 14. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x4 13. "IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_wmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_rmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 11. "IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 9. "IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 8. "IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 7. "IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 6. "IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 5. "IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 4. "IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_p2p_cpu1_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 2. "IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_p2p_cpu1_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_cpu1_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 0. "IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_cpu1_slv_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 14. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x0 13. "IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_wmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_rmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_p2p_cpu1_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_p2p_cpu1_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_cpu1_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_cpu1_slv_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 14. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x0 13. "IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_wmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_rmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_p2p_cpu1_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_p2p_cpu1_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_cpu1_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_cpu1_slv_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 14. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x4 13. "IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_wmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 12. "IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_rmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 11. "IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 9. "IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 8. "IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_pbdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 7. "IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 6. "IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 5. "IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 4. "IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_membdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_p2p_cpu1_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 2. "IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_p2p_cpu1_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_cpu1_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 0. "IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for Idom1_m2m_cpu1_slv_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 14. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x0 13. "IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_wmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_rmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_pbdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_membdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_p2p_cpu1_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_p2p_cpu1_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_cpu1_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Idom1_m2m_cpu1_slv_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 14. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x0 13. "IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_wmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 12. "IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_rmst1_mtog_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 9. "IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 8. "IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_pbdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 7. "IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_wmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 6. "IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_wmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 5. "IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_rmst1_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 4. "IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_membdg_rmst1_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_p2p_cpu1_pmst_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_p2p_cpu1_pmst_src_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_cpu1_slv_dst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Idom1_m2m_cpu1_slv_src_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree.end tree.end tree "j7aep" base ad:0x0 tree "j7aep_hc2_cbass0" tree "j7aep_hc2_cbass0_ERR (j7aep_hc2_cbass0_ERR)" base ad:0x2A83000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end tree "j7aep_hc2_cbass0_GLB (j7aep_hc2_cbass0_GLB)" base ad:0x45B22800 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x20++0x3 line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x40++0x7 line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree "j7aep_hc2_cbass0_ISC (j7aep_hc2_cbass0_ISC)" base ad:0x45898000 rgroup.long 0x400++0x3 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x410++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x430++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x450++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x470++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x490++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 4 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 4 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 4 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 4 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_5_control,The ISC Region 5 Control Register defines the control fields for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 5 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x4B0++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_5_start_address_l,The ISC Region 5 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 5 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_5_start_address_h,The ISC Region 5 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 5 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_5_end_address_l,The ISC Region 5 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 5 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_5_end_address_h,The ISC Region 5 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 5 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_6_control,The ISC Region 6 Control Register defines the control fields for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 6 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x4D0++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_6_start_address_l,The ISC Region 6 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 6 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_6_start_address_h,The ISC Region 6 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 6 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_6_end_address_l,The ISC Region 6 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 6 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_6_end_address_h,The ISC Region 6 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 6 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_7_control,The ISC Region 7 Control Register defines the control fields for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 7 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x4F0++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_7_start_address_l,The ISC Region 7 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 7 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_7_start_address_h,The ISC Region 7 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 7 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_7_end_address_l,The ISC Region 7 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 7 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_7_end_address_h,The ISC Region 7 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 7 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipcie_g3x4_128_main_0.pcie_mst_rd region 8 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC00++0x3 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC10++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC30++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC50++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC70++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC90++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 4 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 4 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 4 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 4 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_5_control,The ISC Region 5 Control Register defines the control fields for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 5 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xCB0++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_5_start_address_l,The ISC Region 5 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 5 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_5_start_address_h,The ISC Region 5 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 5 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_5_end_address_l,The ISC Region 5 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 5 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_5_end_address_h,The ISC Region 5 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 5 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_6_control,The ISC Region 6 Control Register defines the control fields for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 6 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xCD0++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_6_start_address_l,The ISC Region 6 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 6 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_6_start_address_h,The ISC Region 6 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 6 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_6_end_address_l,The ISC Region 6 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 6 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_6_end_address_h,The ISC Region 6 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 6 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_7_control,The ISC Region 7 Control Register defines the control fields for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 7 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xCF0++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_7_start_address_l,The ISC Region 7 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 7 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_7_start_address_h,The ISC Region 7 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 7 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_7_end_address_l,The ISC Region 7 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 7 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_7_end_address_h,The ISC Region 7 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 7 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipcie_g3x4_128_main_0.pcie_mst_wr region 8 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1400++0x3 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1410++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1430++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1450++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1470++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1490++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 4 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 4 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 4 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 4 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_5_control,The ISC Region 5 Control Register defines the control fields for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 5 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x14B0++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_5_start_address_l,The ISC Region 5 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 5 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_5_start_address_h,The ISC Region 5 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 5 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_5_end_address_l,The ISC Region 5 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 5 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_5_end_address_h,The ISC Region 5 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 5 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_6_control,The ISC Region 6 Control Register defines the control fields for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 6 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x14D0++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_6_start_address_l,The ISC Region 6 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 6 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_6_start_address_h,The ISC Region 6 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 6 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_6_end_address_l,The ISC Region 6 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 6 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_6_end_address_h,The ISC Region 6 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 6 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_7_control,The ISC Region 7 Control Register defines the control fields for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 7 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x14F0++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_7_start_address_l,The ISC Region 7 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 7 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_7_start_address_h,The ISC Region 7 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 7 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_7_end_address_l,The ISC Region 7 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 7 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_7_end_address_h,The ISC Region 7 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 7 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipcie_g3x4_128_main_1.pcie_mst_rd region 8 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1C00++0x3 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1C10++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1C30++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1C50++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1C70++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1C90++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 4 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 4 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 4 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 4 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_5_control,The ISC Region 5 Control Register defines the control fields for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 5 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1CB0++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_5_start_address_l,The ISC Region 5 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 5 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_5_start_address_h,The ISC Region 5 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 5 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_5_end_address_l,The ISC Region 5 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 5 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_5_end_address_h,The ISC Region 5 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 5 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_6_control,The ISC Region 6 Control Register defines the control fields for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 6 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1CD0++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_6_start_address_l,The ISC Region 6 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 6 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_6_start_address_h,The ISC Region 6 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 6 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_6_end_address_l,The ISC Region 6 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 6 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_6_end_address_h,The ISC Region 6 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 6 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_7_control,The ISC Region 7 Control Register defines the control fields for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 7 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1CF0++0x13 line.long 0x0 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_7_start_address_l,The ISC Region 7 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 7 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_7_start_address_h,The ISC Region 7 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 7 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_7_end_address_l,The ISC Region 7 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 7 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_7_end_address_h,The ISC Region 7 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 7 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipcie_g3x4_128_main_1.pcie_mst_wr region 8 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2000++0x3 line.long 0x0 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iusb3p0ss_16ffc_main_0.mstr0 region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2010++0x13 line.long 0x0 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Iusb3p0ss_16ffc_main_0.mstr0 region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2030++0x13 line.long 0x0 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Iusb3p0ss_16ffc_main_0.mstr0 region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2050++0x13 line.long 0x0 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Iusb3p0ss_16ffc_main_0.mstr0 region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2070++0x13 line.long 0x0 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Iusb3p0ss_16ffc_main_0.mstr0 region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2090++0x13 line.long 0x0 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 4 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 4 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 4 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 4 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_5_control,The ISC Region 5 Control Register defines the control fields for the master Iusb3p0ss_16ffc_main_0.mstr0 region 5 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x20B0++0x13 line.long 0x0 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_5_start_address_l,The ISC Region 5 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 5 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_5_start_address_h,The ISC Region 5 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 5 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_5_end_address_l,The ISC Region 5 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 5 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_5_end_address_h,The ISC Region 5 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 5 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_6_control,The ISC Region 6 Control Register defines the control fields for the master Iusb3p0ss_16ffc_main_0.mstr0 region 6 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x20D0++0x13 line.long 0x0 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_6_start_address_l,The ISC Region 6 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 6 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_6_start_address_h,The ISC Region 6 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 6 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_6_end_address_l,The ISC Region 6 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 6 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_6_end_address_h,The ISC Region 6 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 6 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_7_control,The ISC Region 7 Control Register defines the control fields for the master Iusb3p0ss_16ffc_main_0.mstr0 region 7 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x20F0++0x13 line.long 0x0 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_7_start_address_l,The ISC Region 7 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 7 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_7_start_address_h,The ISC Region 7 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 7 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_7_end_address_l,The ISC Region 7 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 7 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_7_end_address_h,The ISC Region 7 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstr0 region 7 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstr0_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iusb3p0ss_16ffc_main_0.mstr0 region 8 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2400++0x3 line.long 0x0 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iusb3p0ss_16ffc_main_0.mstw0 region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2410++0x13 line.long 0x0 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Iusb3p0ss_16ffc_main_0.mstw0 region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2430++0x13 line.long 0x0 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Iusb3p0ss_16ffc_main_0.mstw0 region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2450++0x13 line.long 0x0 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Iusb3p0ss_16ffc_main_0.mstw0 region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2470++0x13 line.long 0x0 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Iusb3p0ss_16ffc_main_0.mstw0 region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2490++0x13 line.long 0x0 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 4 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 4 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 4 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 4 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_5_control,The ISC Region 5 Control Register defines the control fields for the master Iusb3p0ss_16ffc_main_0.mstw0 region 5 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x24B0++0x13 line.long 0x0 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_5_start_address_l,The ISC Region 5 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 5 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_5_start_address_h,The ISC Region 5 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 5 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_5_end_address_l,The ISC Region 5 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 5 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_5_end_address_h,The ISC Region 5 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 5 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_6_control,The ISC Region 6 Control Register defines the control fields for the master Iusb3p0ss_16ffc_main_0.mstw0 region 6 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x24D0++0x13 line.long 0x0 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_6_start_address_l,The ISC Region 6 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 6 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_6_start_address_h,The ISC Region 6 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 6 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_6_end_address_l,The ISC Region 6 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 6 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_6_end_address_h,The ISC Region 6 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 6 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_7_control,The ISC Region 7 Control Register defines the control fields for the master Iusb3p0ss_16ffc_main_0.mstw0 region 7 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x24F0++0x13 line.long 0x0 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_7_start_address_l,The ISC Region 7 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 7 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_7_start_address_h,The ISC Region 7 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 7 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_7_end_address_l,The ISC Region 7 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 7 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_7_end_address_h,The ISC Region 7 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss_16ffc_main_0.mstw0 region 7 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iusb3p0ss_16ffc_main_0_mstw0_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iusb3p0ss_16ffc_main_0.mstw0 region 8 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2C00++0x3 line.long 0x0 "ISC_REGS_Iufshci2p1ss_16ffc_main_0_ufshci_vbm_mst_rd_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iufshci2p1ss_16ffc_main_0.ufshci_vbm_mst_rd region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x2C10++0x13 line.long 0x0 "ISC_REGS_Iufshci2p1ss_16ffc_main_0_ufshci_vbm_mst_rd_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iufshci2p1ss_16ffc_main_0.ufshci_vbm_mst_rd region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iufshci2p1ss_16ffc_main_0_ufshci_vbm_mst_rd_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iufshci2p1ss_16ffc_main_0.ufshci_vbm_mst_rd region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iufshci2p1ss_16ffc_main_0_ufshci_vbm_mst_rd_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iufshci2p1ss_16ffc_main_0.ufshci_vbm_mst_rd region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iufshci2p1ss_16ffc_main_0_ufshci_vbm_mst_rd_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iufshci2p1ss_16ffc_main_0.ufshci_vbm_mst_rd region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iufshci2p1ss_16ffc_main_0_ufshci_vbm_mst_rd_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iufshci2p1ss_16ffc_main_0.ufshci_vbm_mst_rd region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3000++0x3 line.long 0x0 "ISC_REGS_Iufshci2p1ss_16ffc_main_0_ufshci_vbm_mst_wr_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iufshci2p1ss_16ffc_main_0.ufshci_vbm_mst_wr region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3010++0x13 line.long 0x0 "ISC_REGS_Iufshci2p1ss_16ffc_main_0_ufshci_vbm_mst_wr_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iufshci2p1ss_16ffc_main_0.ufshci_vbm_mst_wr region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iufshci2p1ss_16ffc_main_0_ufshci_vbm_mst_wr_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iufshci2p1ss_16ffc_main_0.ufshci_vbm_mst_wr region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iufshci2p1ss_16ffc_main_0_ufshci_vbm_mst_wr_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iufshci2p1ss_16ffc_main_0.ufshci_vbm_mst_wr region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iufshci2p1ss_16ffc_main_0_ufshci_vbm_mst_wr_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iufshci2p1ss_16ffc_main_0.ufshci_vbm_mst_wr region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iufshci2p1ss_16ffc_main_0_ufshci_vbm_mst_wr_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iufshci2p1ss_16ffc_main_0.ufshci_vbm_mst_wr region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3400++0x3 line.long 0x0 "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_wr_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iemmc8ss_16ffc_main_0.emmcss_wr region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3410++0x13 line.long 0x0 "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_wr_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iemmc8ss_16ffc_main_0.emmcss_wr region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_wr_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iemmc8ss_16ffc_main_0.emmcss_wr region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_wr_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iemmc8ss_16ffc_main_0.emmcss_wr region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_wr_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iemmc8ss_16ffc_main_0.emmcss_wr region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_wr_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iemmc8ss_16ffc_main_0.emmcss_wr region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3800++0x3 line.long 0x0 "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_rd_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iemmc8ss_16ffc_main_0.emmcss_rd region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3810++0x13 line.long 0x0 "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_rd_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iemmc8ss_16ffc_main_0.emmcss_rd region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_rd_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iemmc8ss_16ffc_main_0.emmcss_rd region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_rd_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iemmc8ss_16ffc_main_0.emmcss_rd region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_rd_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iemmc8ss_16ffc_main_0.emmcss_rd region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_rd_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iemmc8ss_16ffc_main_0.emmcss_rd region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3C00++0x3 line.long 0x0 "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Isa2_ul_main_0.ctxcach_ext_dma region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3C10++0x13 line.long 0x0 "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Isa2_ul_main_0.ctxcach_ext_dma region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Isa2_ul_main_0.ctxcach_ext_dma region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Isa2_ul_main_0.ctxcach_ext_dma region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Isa2_ul_main_0.ctxcach_ext_dma region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Isa2_ul_main_0.ctxcach_ext_dma region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3C30++0x13 line.long 0x0 "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Isa2_ul_main_0.ctxcach_ext_dma region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Isa2_ul_main_0.ctxcach_ext_dma region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Isa2_ul_main_0.ctxcach_ext_dma region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Isa2_ul_main_0.ctxcach_ext_dma region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Isa2_ul_main_0.ctxcach_ext_dma region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3C50++0x13 line.long 0x0 "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Isa2_ul_main_0.ctxcach_ext_dma region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Isa2_ul_main_0.ctxcach_ext_dma region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Isa2_ul_main_0.ctxcach_ext_dma region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Isa2_ul_main_0.ctxcach_ext_dma region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Isa2_ul_main_0.ctxcach_ext_dma region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3C70++0x13 line.long 0x0 "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Isa2_ul_main_0.ctxcach_ext_dma region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Isa2_ul_main_0.ctxcach_ext_dma region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Isa2_ul_main_0.ctxcach_ext_dma region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Isa2_ul_main_0.ctxcach_ext_dma region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Isa2_ul_main_0.ctxcach_ext_dma region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." tree.end tree "j7aep_hc2_cbass0_QOS (j7aep_hc2_cbass0_QOS)" base ad:0x45D98000 rgroup.long 0x400++0x7 line.long 0x0 "QOS_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Ipcie_g3x4_128_main_0.pcie_mst_rd for group slv_linkgrp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Ipcie_g3x4_128_main_0.pcie_mst_rd for group slv_linkgrp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x500++0x1F line.long 0x0 "QOS_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_map0,The Map Register defines the fields for the master Ipcie_g3x4_128_main_0.pcie_mst_rd per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_map1,The Map Register defines the fields for the master Ipcie_g3x4_128_main_0.pcie_mst_rd per channel." bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x8 "QOS_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_map2,The Map Register defines the fields for the master Ipcie_g3x4_128_main_0.pcie_mst_rd per channel." bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC "QOS_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_map3,The Map Register defines the fields for the master Ipcie_g3x4_128_main_0.pcie_mst_rd per channel." bitfld.long 0xC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0xC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x10 "QOS_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_map4,The Map Register defines the fields for the master Ipcie_g3x4_128_main_0.pcie_mst_rd per channel." bitfld.long 0x10 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x10 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x10 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x14 "QOS_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_map5,The Map Register defines the fields for the master Ipcie_g3x4_128_main_0.pcie_mst_rd per channel." bitfld.long 0x14 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x14 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x14 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x18 "QOS_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_map6,The Map Register defines the fields for the master Ipcie_g3x4_128_main_0.pcie_mst_rd per channel." bitfld.long 0x18 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x18 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x18 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1C "QOS_REGS_Ipcie_g3x4_128_main_0_pcie_mst_rd_map7,The Map Register defines the fields for the master Ipcie_g3x4_128_main_0.pcie_mst_rd per channel." bitfld.long 0x1C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1C 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x1C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0xC00++0x7 line.long 0x0 "QOS_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Ipcie_g3x4_128_main_0.pcie_mst_wr for group slv_linkgrp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Ipcie_g3x4_128_main_0.pcie_mst_wr for group slv_linkgrp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0xD00++0x1F line.long 0x0 "QOS_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_map0,The Map Register defines the fields for the master Ipcie_g3x4_128_main_0.pcie_mst_wr per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_map1,The Map Register defines the fields for the master Ipcie_g3x4_128_main_0.pcie_mst_wr per channel." bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x8 "QOS_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_map2,The Map Register defines the fields for the master Ipcie_g3x4_128_main_0.pcie_mst_wr per channel." bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC "QOS_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_map3,The Map Register defines the fields for the master Ipcie_g3x4_128_main_0.pcie_mst_wr per channel." bitfld.long 0xC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0xC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x10 "QOS_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_map4,The Map Register defines the fields for the master Ipcie_g3x4_128_main_0.pcie_mst_wr per channel." bitfld.long 0x10 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x10 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x10 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x14 "QOS_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_map5,The Map Register defines the fields for the master Ipcie_g3x4_128_main_0.pcie_mst_wr per channel." bitfld.long 0x14 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x14 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x14 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x18 "QOS_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_map6,The Map Register defines the fields for the master Ipcie_g3x4_128_main_0.pcie_mst_wr per channel." bitfld.long 0x18 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x18 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x18 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1C "QOS_REGS_Ipcie_g3x4_128_main_0_pcie_mst_wr_map7,The Map Register defines the fields for the master Ipcie_g3x4_128_main_0.pcie_mst_wr per channel." bitfld.long 0x1C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1C 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x1C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x1400++0x7 line.long 0x0 "QOS_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Ipcie_g3x4_128_main_1.pcie_mst_rd for group slv_linkgrp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Ipcie_g3x4_128_main_1.pcie_mst_rd for group slv_linkgrp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x1500++0x1F line.long 0x0 "QOS_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_map0,The Map Register defines the fields for the master Ipcie_g3x4_128_main_1.pcie_mst_rd per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_map1,The Map Register defines the fields for the master Ipcie_g3x4_128_main_1.pcie_mst_rd per channel." bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x8 "QOS_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_map2,The Map Register defines the fields for the master Ipcie_g3x4_128_main_1.pcie_mst_rd per channel." bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC "QOS_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_map3,The Map Register defines the fields for the master Ipcie_g3x4_128_main_1.pcie_mst_rd per channel." bitfld.long 0xC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0xC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x10 "QOS_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_map4,The Map Register defines the fields for the master Ipcie_g3x4_128_main_1.pcie_mst_rd per channel." bitfld.long 0x10 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x10 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x10 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x14 "QOS_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_map5,The Map Register defines the fields for the master Ipcie_g3x4_128_main_1.pcie_mst_rd per channel." bitfld.long 0x14 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x14 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x14 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x18 "QOS_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_map6,The Map Register defines the fields for the master Ipcie_g3x4_128_main_1.pcie_mst_rd per channel." bitfld.long 0x18 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x18 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x18 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1C "QOS_REGS_Ipcie_g3x4_128_main_1_pcie_mst_rd_map7,The Map Register defines the fields for the master Ipcie_g3x4_128_main_1.pcie_mst_rd per channel." bitfld.long 0x1C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1C 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x1C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x1C00++0x7 line.long 0x0 "QOS_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Ipcie_g3x4_128_main_1.pcie_mst_wr for group slv_linkgrp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Ipcie_g3x4_128_main_1.pcie_mst_wr for group slv_linkgrp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x1D00++0x1F line.long 0x0 "QOS_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_map0,The Map Register defines the fields for the master Ipcie_g3x4_128_main_1.pcie_mst_wr per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_map1,The Map Register defines the fields for the master Ipcie_g3x4_128_main_1.pcie_mst_wr per channel." bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x8 "QOS_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_map2,The Map Register defines the fields for the master Ipcie_g3x4_128_main_1.pcie_mst_wr per channel." bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC "QOS_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_map3,The Map Register defines the fields for the master Ipcie_g3x4_128_main_1.pcie_mst_wr per channel." bitfld.long 0xC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0xC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x10 "QOS_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_map4,The Map Register defines the fields for the master Ipcie_g3x4_128_main_1.pcie_mst_wr per channel." bitfld.long 0x10 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x10 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x10 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x14 "QOS_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_map5,The Map Register defines the fields for the master Ipcie_g3x4_128_main_1.pcie_mst_wr per channel." bitfld.long 0x14 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x14 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x14 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x18 "QOS_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_map6,The Map Register defines the fields for the master Ipcie_g3x4_128_main_1.pcie_mst_wr per channel." bitfld.long 0x18 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x18 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x18 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1C "QOS_REGS_Ipcie_g3x4_128_main_1_pcie_mst_wr_map7,The Map Register defines the fields for the master Ipcie_g3x4_128_main_1.pcie_mst_wr per channel." bitfld.long 0x1C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1C 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x1C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x2000++0x7 line.long 0x0 "QOS_REGS_Iusb3p0ss_16ffc_main_0_mstr0_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Iusb3p0ss_16ffc_main_0.mstr0 for group slv_linkgrp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Iusb3p0ss_16ffc_main_0_mstr0_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Iusb3p0ss_16ffc_main_0.mstr0 for group slv_linkgrp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x2100++0x1F line.long 0x0 "QOS_REGS_Iusb3p0ss_16ffc_main_0_mstr0_map0,The Map Register defines the fields for the master Iusb3p0ss_16ffc_main_0.mstr0 per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Iusb3p0ss_16ffc_main_0_mstr0_map1,The Map Register defines the fields for the master Iusb3p0ss_16ffc_main_0.mstr0 per channel." bitfld.long 0x4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x8 "QOS_REGS_Iusb3p0ss_16ffc_main_0_mstr0_map2,The Map Register defines the fields for the master Iusb3p0ss_16ffc_main_0.mstr0 per channel." bitfld.long 0x8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC "QOS_REGS_Iusb3p0ss_16ffc_main_0_mstr0_map3,The Map Register defines the fields for the master Iusb3p0ss_16ffc_main_0.mstr0 per channel." bitfld.long 0xC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x10 "QOS_REGS_Iusb3p0ss_16ffc_main_0_mstr0_map4,The Map Register defines the fields for the master Iusb3p0ss_16ffc_main_0.mstr0 per channel." bitfld.long 0x10 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x10 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x10 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x10 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x10 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x14 "QOS_REGS_Iusb3p0ss_16ffc_main_0_mstr0_map5,The Map Register defines the fields for the master Iusb3p0ss_16ffc_main_0.mstr0 per channel." bitfld.long 0x14 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x14 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x14 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x14 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x14 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x18 "QOS_REGS_Iusb3p0ss_16ffc_main_0_mstr0_map6,The Map Register defines the fields for the master Iusb3p0ss_16ffc_main_0.mstr0 per channel." bitfld.long 0x18 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x18 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x18 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x18 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x18 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1C "QOS_REGS_Iusb3p0ss_16ffc_main_0_mstr0_map7,The Map Register defines the fields for the master Iusb3p0ss_16ffc_main_0.mstr0 per channel." bitfld.long 0x1C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x2400++0x7 line.long 0x0 "QOS_REGS_Iusb3p0ss_16ffc_main_0_mstw0_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Iusb3p0ss_16ffc_main_0.mstw0 for group slv_linkgrp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Iusb3p0ss_16ffc_main_0_mstw0_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Iusb3p0ss_16ffc_main_0.mstw0 for group slv_linkgrp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x2500++0x1F line.long 0x0 "QOS_REGS_Iusb3p0ss_16ffc_main_0_mstw0_map0,The Map Register defines the fields for the master Iusb3p0ss_16ffc_main_0.mstw0 per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Iusb3p0ss_16ffc_main_0_mstw0_map1,The Map Register defines the fields for the master Iusb3p0ss_16ffc_main_0.mstw0 per channel." bitfld.long 0x4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x8 "QOS_REGS_Iusb3p0ss_16ffc_main_0_mstw0_map2,The Map Register defines the fields for the master Iusb3p0ss_16ffc_main_0.mstw0 per channel." bitfld.long 0x8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC "QOS_REGS_Iusb3p0ss_16ffc_main_0_mstw0_map3,The Map Register defines the fields for the master Iusb3p0ss_16ffc_main_0.mstw0 per channel." bitfld.long 0xC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x10 "QOS_REGS_Iusb3p0ss_16ffc_main_0_mstw0_map4,The Map Register defines the fields for the master Iusb3p0ss_16ffc_main_0.mstw0 per channel." bitfld.long 0x10 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x10 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x10 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x10 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x10 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x14 "QOS_REGS_Iusb3p0ss_16ffc_main_0_mstw0_map5,The Map Register defines the fields for the master Iusb3p0ss_16ffc_main_0.mstw0 per channel." bitfld.long 0x14 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x14 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x14 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x14 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x14 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x18 "QOS_REGS_Iusb3p0ss_16ffc_main_0_mstw0_map6,The Map Register defines the fields for the master Iusb3p0ss_16ffc_main_0.mstw0 per channel." bitfld.long 0x18 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x18 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x18 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x18 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x18 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x1C "QOS_REGS_Iusb3p0ss_16ffc_main_0_mstw0_map7,The Map Register defines the fields for the master Iusb3p0ss_16ffc_main_0.mstw0 per channel." bitfld.long 0x1C 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x1C 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x1C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x1C 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x1C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x2C00++0x7 line.long 0x0 "QOS_REGS_Iufshci2p1ss_16ffc_main_0_ufshci_vbm_mst_rd_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Iufshci2p1ss_16ffc_main_0.ufshci_vbm_mst_rd for group slv_linkgrp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Iufshci2p1ss_16ffc_main_0_ufshci_vbm_mst_rd_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Iufshci2p1ss_16ffc_main_0.ufshci_vbm_mst_rd for group slv_linkgrp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x2D00++0x7 line.long 0x0 "QOS_REGS_Iufshci2p1ss_16ffc_main_0_ufshci_vbm_mst_rd_map0,The Map Register defines the fields for the master Iufshci2p1ss_16ffc_main_0.ufshci_vbm_mst_rd per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Iufshci2p1ss_16ffc_main_0_ufshci_vbm_mst_rd_map1,The Map Register defines the fields for the master Iufshci2p1ss_16ffc_main_0.ufshci_vbm_mst_rd per channel." bitfld.long 0x4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x3000++0x7 line.long 0x0 "QOS_REGS_Iufshci2p1ss_16ffc_main_0_ufshci_vbm_mst_wr_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Iufshci2p1ss_16ffc_main_0.ufshci_vbm_mst_wr for group slv_linkgrp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Iufshci2p1ss_16ffc_main_0_ufshci_vbm_mst_wr_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Iufshci2p1ss_16ffc_main_0.ufshci_vbm_mst_wr for group slv_linkgrp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x3100++0xF line.long 0x0 "QOS_REGS_Iufshci2p1ss_16ffc_main_0_ufshci_vbm_mst_wr_map0,The Map Register defines the fields for the master Iufshci2p1ss_16ffc_main_0.ufshci_vbm_mst_wr per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Iufshci2p1ss_16ffc_main_0_ufshci_vbm_mst_wr_map1,The Map Register defines the fields for the master Iufshci2p1ss_16ffc_main_0.ufshci_vbm_mst_wr per channel." bitfld.long 0x4 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x4 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x8 "QOS_REGS_Iufshci2p1ss_16ffc_main_0_ufshci_vbm_mst_wr_map2,The Map Register defines the fields for the master Iufshci2p1ss_16ffc_main_0.ufshci_vbm_mst_wr per channel." bitfld.long 0x8 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x8 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC "QOS_REGS_Iufshci2p1ss_16ffc_main_0_ufshci_vbm_mst_wr_map3,The Map Register defines the fields for the master Iufshci2p1ss_16ffc_main_0.ufshci_vbm_mst_wr per channel." bitfld.long 0xC 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0xC 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0xC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x3400++0x7 line.long 0x0 "QOS_REGS_Iemmc8ss_16ffc_main_0_emmcss_wr_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Iemmc8ss_16ffc_main_0.emmcss_wr for group slv_linkgrp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Iemmc8ss_16ffc_main_0_emmcss_wr_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Iemmc8ss_16ffc_main_0.emmcss_wr for group slv_linkgrp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x3500++0x3 line.long 0x0 "QOS_REGS_Iemmc8ss_16ffc_main_0_emmcss_wr_map0,The Map Register defines the fields for the master Iemmc8ss_16ffc_main_0.emmcss_wr per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x3800++0x7 line.long 0x0 "QOS_REGS_Iemmc8ss_16ffc_main_0_emmcss_rd_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Iemmc8ss_16ffc_main_0.emmcss_rd for group slv_linkgrp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Iemmc8ss_16ffc_main_0_emmcss_rd_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Iemmc8ss_16ffc_main_0.emmcss_rd for group slv_linkgrp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x3900++0x3 line.long 0x0 "QOS_REGS_Iemmc8ss_16ffc_main_0_emmcss_rd_map0,The Map Register defines the fields for the master Iemmc8ss_16ffc_main_0.emmcss_rd per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x3C00++0x7 line.long 0x0 "QOS_REGS_Isa2_ul_main_0_ctxcach_ext_dma_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Isa2_ul_main_0.ctxcach_ext_dma for group slv_linkgrp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Isa2_ul_main_0_ctxcach_ext_dma_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Isa2_ul_main_0.ctxcach_ext_dma for group slv_linkgrp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x3D00++0x3 line.long 0x0 "QOS_REGS_Isa2_ul_main_0_ctxcach_ext_dma_map0,The Map Register defines the fields for the master Isa2_ul_main_0.ctxcach_ext_dma per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x4000++0x7 line.long 0x0 "QOS_REGS_Ivusr_dual_main_0_v0_m_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Ivusr_dual_main_0.v0_m for group slv_linkgrp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ivusr_dual_main_0_v0_m_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Ivusr_dual_main_0.v0_m for group slv_linkgrp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x4100++0x3 line.long 0x0 "QOS_REGS_Ivusr_dual_main_0_v0_m_map0,The Map Register defines the fields for the master Ivusr_dual_main_0.v0_m per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x4400++0x7 line.long 0x0 "QOS_REGS_Ivusr_dual_main_0_v1_m_slv_linkgrp_0_grp_map1,The Group Map Register defines the final orderid for the master Ivusr_dual_main_0.v1_m for group slv_linkgrp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." newline hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ivusr_dual_main_0_v1_m_slv_linkgrp_0_grp_map2,The Group Map Register defines the final orderid for the master Ivusr_dual_main_0.v1_m for group slv_linkgrp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." newline hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." newline hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." rgroup.long 0x4500++0x3 line.long 0x0 "QOS_REGS_Ivusr_dual_main_0_v1_m_map0,The Map Register defines the fields for the master Ivusr_dual_main_0.v1_m per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." newline hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" tree.end tree.end tree "j7aep_hc_cfg_cbass0" tree "j7aep_hc_cfg_cbass0_ERR (j7aep_hc_cfg_cbass0_ERR)" base ad:0x2A89000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end tree "j7aep_hc_cfg_cbass0_GLB (j7aep_hc_cfg_cbass0_GLB)" base ad:0x45B21000 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x20++0x3 line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x40++0x7 line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree.end tree.end tree "J7AEP_GPU_BXS464_WRAP0_GPU_SS_0_CORE_MMRS (J7AEP_GPU_BXS464_WRAP0_GPU_SS_0_CORE_MMRS)" base ad:0x4E20000000 rgroup.quad 0x0++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_CLK_CTRL,Core Module Clock Control Modes." hexmask.quad.word 0x0 54.--63. 1. "RESERVED_54," newline bitfld.quad 0x0 52.--53. "USCS," "0,1,2,3" newline bitfld.quad 0x0 50.--51. "PBE," "0,1,2,3" newline bitfld.quad 0x0 48.--49. "MCU_L1," "0,1,2,3" newline bitfld.quad 0x0 46.--47. "CDM," "0,1,2,3" newline bitfld.quad 0x0 44.--45. "SIDEKICK," "0,1,2,3" newline bitfld.quad 0x0 42.--43. "BIF_SIDEKICK," "0,1,2,3" newline bitfld.quad 0x0 40.--41. "BIF," "0,1,2,3" newline hexmask.quad.word 0x0 30.--39. 1. "RESERVED_30," newline bitfld.quad 0x0 28.--29. "TPU_MCU_DEMUX," "0,1,2,3" newline bitfld.quad 0x0 26.--27. "MCU_L0," "0,1,2,3" newline bitfld.quad 0x0 24.--25. "TPU," "0,1,2,3" newline rbitfld.quad 0x0 22.--23. "RESERVED_22," "0,1,2,3" newline bitfld.quad 0x0 20.--21. "USC," "0,1,2,3" newline rbitfld.quad 0x0 18.--19. "RESERVED_18," "0,1,2,3" newline bitfld.quad 0x0 16.--17. "SLC," "0,1,2,3" newline bitfld.quad 0x0 14.--15. "UVS," "0,1,2,3" newline bitfld.quad 0x0 12.--13. "PDS," "0,1,2,3" newline bitfld.quad 0x0 10.--11. "VDM," "0,1,2,3" newline bitfld.quad 0x0 8.--9. "PM," "0,1,2,3" newline bitfld.quad 0x0 6.--7. "GPP," "0,1,2,3" newline bitfld.quad 0x0 4.--5. "TE," "0,1,2,3" newline bitfld.quad 0x0 2.--3. "TSP," "0,1,2,3" newline bitfld.quad 0x0 0.--1. "ISP," "0,1,2,3" rgroup.quad 0x8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_CLK_STATUS,Reports the current module clock status" hexmask.quad 0x0 27.--63. 1. "RESERVED_27," newline bitfld.quad 0x0 26. "USCS," "0,1" newline bitfld.quad 0x0 25. "PBE," "0,1" newline bitfld.quad 0x0 24. "MCU_L1," "0,1" newline bitfld.quad 0x0 23. "CDM," "0,1" newline bitfld.quad 0x0 22. "SIDEKICK," "0,1" newline bitfld.quad 0x0 21. "BIF_SIDEKICK," "0,1" newline bitfld.quad 0x0 20. "BIF," "0,1" newline hexmask.quad.byte 0x0 15.--19. 1. "RESERVED_15," newline bitfld.quad 0x0 14. "TPU_MCU_DEMUX," "0,1" newline bitfld.quad 0x0 13. "MCU_L0," "0,1" newline bitfld.quad 0x0 12. "TPU," "0,1" newline bitfld.quad 0x0 11. "RESERVED_11," "0,1" newline bitfld.quad 0x0 10. "USC," "0,1" newline bitfld.quad 0x0 9. "RESERVED_9," "0,1" newline bitfld.quad 0x0 8. "SLC," "0,1" newline bitfld.quad 0x0 7. "UVS," "0,1" newline bitfld.quad 0x0 6. "PDS," "0,1" newline bitfld.quad 0x0 5. "VDM," "0,1" newline bitfld.quad 0x0 4. "PM," "0,1" newline bitfld.quad 0x0 3. "GPP," "0,1" newline bitfld.quad 0x0 2. "TE," "0,1" newline bitfld.quad 0x0 1. "TSP," "0,1" newline bitfld.quad 0x0 0. "ISP," "0,1" rgroup.quad 0x18++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_PRODUCT_ID,Reports the product ID" hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.word 0x0 16.--31. 1. "IMG_PRODUCT_ID,IMG Product ID" newline hexmask.quad.word 0x0 0.--15. 1. "RESERVED_0," line.quad 0x8 "CORE_MMRS_RGX_CR_CORE_ID,Reports the product ID" hexmask.quad.word 0x8 48.--63. 1. "BRANCH_ID,B - Branch ID" newline hexmask.quad.word 0x8 32.--47. 1. "VERSION_ID,V - Version ID" newline hexmask.quad.word 0x8 16.--31. 1. "NUMBER_OF_SCALABLE_UNITS,N - Number of scalable Units" newline hexmask.quad.word 0x8 0.--15. 1. "CONFIG_ID,C - Config ID" line.quad 0x10 "CORE_MMRS_RGX_CR_CORE_IP_INTEGRATOR_ID,Reports the product ID" hexmask.quad.long 0x10 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x10 0.--31. 1. "VALUE,IP company ID/Designer" line.quad 0x18 "CORE_MMRS_RGX_CR_CORE_IP_CHANGELIST,Reports the version control ID" hexmask.quad.long 0x18 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x18 0.--31. 1. "VALUE,Version control ID" rgroup.quad 0x38++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_POWER_EVENT,Allows the firmware to request a power-up or power-down operation to an external (to Rogue) power-management controller" hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.byte 0x0 24.--31. 1. "GPU_MASK,One bit per GPU indicating which GPUs are considered for the power event." newline hexmask.quad.word 0x0 8.--23. 1. "DOMAIN,sets which power island is enabled for the current power event request; bit0:jones bit1-8:dusts bit9-12:blackpearls" newline hexmask.quad.byte 0x0 2.--7. 1. "RESERVED_2," newline bitfld.quad 0x0 1. "REQ,Set when a power event operation is requested" "0,1" newline bitfld.quad 0x0 0. "TYPE,The requested power event operation" "0,1" rgroup.quad 0x50++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_DUSTS_ENABLE,Controls how many Dual Unified Shading and Texturing Units (DUSTs) are enabled." hexmask.quad 0x0 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x0 0.--7. 1. "ENABLE,Dusts enabled" line.quad 0x8 "CORE_MMRS_RGX_CR_DUSTS_FUSE,Indicates how many of the available DUST modules are enabled on the Silicon." hexmask.quad 0x8 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x8 0.--7. 1. "ENABLE,Dusts enabled" rgroup.quad 0x80++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_CLK_XTPLUS_CTRL,Core Module Clock Control Modes." hexmask.quad.long 0x0 36.--63. 1. "RESERVED_36," newline bitfld.quad 0x0 34.--35. "ASTC," "0,1,2,3" newline hexmask.quad 0x0 0.--33. 1. "RESERVED_0," rgroup.quad 0x88++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_CLK_XTPLUS_STATUS,Reports the current module clock status" hexmask.quad 0x0 10.--63. 1. "RESERVED_10," newline bitfld.quad 0x0 9. "IPF," "0,1" newline bitfld.quad 0x0 8. "COMPUTE," "0,1" newline bitfld.quad 0x0 7. "ASTC," "0,1" newline bitfld.quad 0x0 6. "PIXEL," "0,1" newline bitfld.quad 0x0 5. "VERTEX," "0,1" newline bitfld.quad 0x0 4. "RESERVED_4," "0,1" newline bitfld.quad 0x0 3. "PDS_SHARED," "0,1" newline bitfld.quad 0x0 2. "BIF_BLACKPEARL," "0,1" newline bitfld.quad 0x0 1. "USC_SHARED," "0,1" newline bitfld.quad 0x0 0. "GEOMETRY," "0,1" rgroup.quad 0xE0++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_SOC_TIMER_GRAY,This register contains the value of a 64-bit external gray coded timer." hexmask.quad 0x0 0.--63. 1. "VALUE," line.quad 0x8 "CORE_MMRS_RGX_CR_SOC_TIMER_BINARY,This register contains the value of a 64-bit external binary coded timer." hexmask.quad 0x8 0.--63. 1. "VALUE," rgroup.quad 0x100++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_SOFT_RESET,Core soft reset control register." hexmask.quad.byte 0x0 60.--63. 1. "RESERVED_60," newline rbitfld.quad 0x0 59. "TILING_CORE," "0,1" newline rbitfld.quad 0x0 58. "TE3," "0,1" newline rbitfld.quad 0x0 57. "VCE," "0,1" newline rbitfld.quad 0x0 56. "VBS," "0,1" newline hexmask.quad.tbyte 0x0 35.--55. 1. "RESERVED_35," newline bitfld.quad 0x0 34. "MMU," "0,1" newline rbitfld.quad 0x0 33. "RESERVED_33," "0,1" newline bitfld.quad 0x0 32. "CPU,Includes MTS and META or MIPS" "0,1" newline bitfld.quad 0x0 31. "RASCAL_CORE,Note that the RASL_CORE bit affects logic related to the reading and writing of registers. This soft reset should therefore be used with caution. Upon power down events it is necessary.." "0,1" newline bitfld.quad 0x0 30. "DUST_B_CORE," "0,1" newline bitfld.quad 0x0 29. "DUST_A_CORE," "0,1" newline rbitfld.quad 0x0 28. "RESERVED_28," "0,1" newline bitfld.quad 0x0 27. "SLC," "0,1" newline rbitfld.quad 0x0 26. "RESERVED_26," "0,1" newline bitfld.quad 0x0 25. "UVS," "0,1" newline bitfld.quad 0x0 24. "TE," "0,1" newline bitfld.quad 0x0 23. "GPP," "0,1" newline rbitfld.quad 0x0 21.--22. "RESERVED_21," "0,1,2,3" newline bitfld.quad 0x0 20. "PM," "0,1" newline bitfld.quad 0x0 19. "PBE," "0,1" newline bitfld.quad 0x0 18. "USC_SHARED," "0,1" newline bitfld.quad 0x0 17. "MCU_L1," "0,1" newline bitfld.quad 0x0 16. "BIF,Bifpmcache BIF" "0,1" newline bitfld.quad 0x0 15. "CDM," "0,1" newline bitfld.quad 0x0 14. "VDM," "0,1" newline rbitfld.quad 0x0 13. "RESERVED_13," "0,1" newline bitfld.quad 0x0 12. "PDS," "0,1" newline bitfld.quad 0x0 11. "ISP," "0,1" newline bitfld.quad 0x0 10. "TSP," "0,1" newline hexmask.quad.byte 0x0 6.--9. 1. "RESERVED_6," newline bitfld.quad 0x0 5. "SYSARB," "0,1" newline bitfld.quad 0x0 4. "TPU_MCU_DEMUX," "0,1" newline bitfld.quad 0x0 3. "MCU_L0," "0,1" newline bitfld.quad 0x0 2. "TPU," "0,1" newline rbitfld.quad 0x0 1. "RESERVED_1," "0,1" newline bitfld.quad 0x0 0. "USC," "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_SOFT_RESET2,Core soft reset control register." hexmask.quad 0x8 11.--63. 1. "RESERVED_11," newline bitfld.quad 0x8 10. "ASTC," "0,1" newline rbitfld.quad 0x8 9. "BLACKPEARL," "0,1" newline rbitfld.quad 0x8 8. "RESERVED_8," "0,1" newline rbitfld.quad 0x8 7. "IPF," "0,1" newline rbitfld.quad 0x8 6. "GEOMETRY," "0,1" newline rbitfld.quad 0x8 5. "USC_SHARED," "0,1" newline rbitfld.quad 0x8 4. "PDS_SHARED," "0,1" newline rbitfld.quad 0x8 3. "BIF_BLACKPEARL," "0,1" newline rbitfld.quad 0x8 2. "PIXEL," "0,1" newline rbitfld.quad 0x8 1. "RESERVED_1," "0,1" newline rbitfld.quad 0x8 0. "VERTEX," "0,1" rgroup.quad 0x120++0x2F line.quad 0x0 "CORE_MMRS_RGX_CR_CONTEXT_SWITCH_ENABLE,The use of the this register has been deprecated." hexmask.quad 0x0 4.--63. 1. "RESERVED_4," newline bitfld.quad 0x0 3. "SOFT_RESET," "0,1" newline bitfld.quad 0x0 2. "IPF," "0,1" newline bitfld.quad 0x0 1. "VDM," "0,1" newline bitfld.quad 0x0 0. "CDM," "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_EVENT_ENABLE,This register is used to enable GPU interrupts directly to the host" hexmask.quad 0x8 21.--63. 1. "RESERVED_21," newline bitfld.quad 0x8 20. "SAFETY,Indicates an interrupt event from an active safety feature has been received" "0,1" newline bitfld.quad 0x8 19. "SLAVE_REQ,Indicates an interrupt event from a slave has been received." "0,1" newline rbitfld.quad 0x8 16.--18. "RESERVED_16," "0,1,2,3,4,5,6,7" newline bitfld.quad 0x8 15. "USC_TRIGGER,One or more USC has executed a nop.trigger instruction" "0,1" newline bitfld.quad 0x8 14. "ZLS_FINISHED,ZLS has finished all tiles in a Render" "0,1" newline bitfld.quad 0x8 13. "GPIO_ACK,General Purpose ouput acknowledgement" "0,1" newline bitfld.quad 0x8 12. "GPIO_REQ,General Purpose input request" "0,1" newline bitfld.quad 0x8 11. "POWER_ABORT,The requested power operation has been denied." "0,1" newline bitfld.quad 0x8 10. "POWER_COMPLETE,The requested power operation has completed" "0,1" newline bitfld.quad 0x8 9. "MMU_PAGE_FAULT,An MMU page fault has occurred" "0,1" newline bitfld.quad 0x8 8. "PM_3D_MEM_FREE,PM memory allocation completed for the current render" "0,1" newline bitfld.quad 0x8 7. "PM_OUT_OF_MEMORY,PM memory allocation failed for a macro-tile" "0,1" newline bitfld.quad 0x8 6. "TA_TERMINATE,The TE has aborted a macro tile after a failted PM allocation request" "0,1" newline bitfld.quad 0x8 5. "TA_FINISHED,The TA phase has completed" "0,1" newline bitfld.quad 0x8 4. "ISP_END_MACROTILE,ISP End-of-Macrotile" "0,1" newline bitfld.quad 0x8 3. "PIXELBE_END_RENDER,The 3D phase has completed" "0,1" newline bitfld.quad 0x8 2. "COMPUTE_FINISHED,The compute phase has completed" "0,1" newline bitfld.quad 0x8 1. "KERNEL_FINISHED,A compute kernel has completed and updated the associated event object in external memory" "0,1" newline rbitfld.quad 0x8 0. "RESERVED_0," "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_EVENT_STATUS,The event status register indicate the source of an interrupt generated by PowerVR RGX" hexmask.quad 0x10 21.--63. 1. "RESERVED_21," newline bitfld.quad 0x10 20. "SAFETY,Indicates an interrupt event from an active safety feature has been received" "0,1" newline bitfld.quad 0x10 19. "SLAVE_REQ,Indicates an interrupt event from a slave has been received." "0,1" newline rbitfld.quad 0x10 16.--18. "RESERVED_16," "0,1,2,3,4,5,6,7" newline bitfld.quad 0x10 15. "USC_TRIGGER,One or more USC has executed a nop.trigger instruction" "0,1" newline bitfld.quad 0x10 14. "ZLS_FINISHED,ZLS has finished all tiles in a Render" "0,1" newline bitfld.quad 0x10 13. "GPIO_ACK,General Purpose ouput acknowledgement" "0,1" newline bitfld.quad 0x10 12. "GPIO_REQ,General Purpose input request" "0,1" newline bitfld.quad 0x10 11. "POWER_ABORT,The requested power operation has been denied." "0,1" newline bitfld.quad 0x10 10. "POWER_COMPLETE,The requested power operation has completed" "0,1" newline bitfld.quad 0x10 9. "MMU_PAGE_FAULT,An MMU page fault has occurred" "0,1" newline bitfld.quad 0x10 8. "PM_3D_MEM_FREE,PM memory allocation completed for the current render" "0,1" newline bitfld.quad 0x10 7. "PM_OUT_OF_MEMORY,PM memory allocation failed for a macro-tile" "0,1" newline bitfld.quad 0x10 6. "TA_TERMINATE,The TE has aborted a macro tile after a failted PM allocation request" "0,1" newline bitfld.quad 0x10 5. "TA_FINISHED,The TA phase has completed" "0,1" newline bitfld.quad 0x10 4. "ISP_END_MACROTILE,ISP End-of-Macrotile" "0,1" newline bitfld.quad 0x10 3. "PIXELBE_END_RENDER,The 3D phase has completed" "0,1" newline bitfld.quad 0x10 2. "COMPUTE_FINISHED,The compute phase has completed" "0,1" newline bitfld.quad 0x10 1. "KERNEL_FINISHED,A compute kernel has completed and updated the associated event object in external memory" "0,1" newline rbitfld.quad 0x10 0. "RESERVED_0," "0,1" line.quad 0x18 "CORE_MMRS_RGX_CR_EVENT_CLEAR,This register is used to clear event interrupts." hexmask.quad 0x18 21.--63. 1. "RESERVED_21," newline bitfld.quad 0x18 20. "SAFETY,Indicates an interrupt event from an active safety feature has been received" "0,1" newline bitfld.quad 0x18 19. "SLAVE_REQ,Indicates an interrupt event from a slave has been received." "0,1" newline rbitfld.quad 0x18 16.--18. "RESERVED_16," "0,1,2,3,4,5,6,7" newline bitfld.quad 0x18 15. "USC_TRIGGER,One or more USC has executed a nop.trigger instruction" "0,1" newline bitfld.quad 0x18 14. "ZLS_FINISHED,ZLS has finished all tiles in a Render" "0,1" newline bitfld.quad 0x18 13. "GPIO_ACK,General Purpose ouput acknowledgement" "0,1" newline bitfld.quad 0x18 12. "GPIO_REQ,General Purpose input request" "0,1" newline bitfld.quad 0x18 11. "POWER_ABORT,The requested power operation has been denied." "0,1" newline bitfld.quad 0x18 10. "POWER_COMPLETE,The requested power operation has completed" "0,1" newline bitfld.quad 0x18 9. "MMU_PAGE_FAULT,An MMU page fault has occurred" "0,1" newline bitfld.quad 0x18 8. "PM_3D_MEM_FREE,PM memory allocation completed for the current render" "0,1" newline bitfld.quad 0x18 7. "PM_OUT_OF_MEMORY,PM memory allocation failed for a macro-tile" "0,1" newline bitfld.quad 0x18 6. "TA_TERMINATE,The TE has aborted a macro tile after a failted PM allocation request" "0,1" newline bitfld.quad 0x18 5. "TA_FINISHED,The TA phase has completed" "0,1" newline bitfld.quad 0x18 4. "ISP_END_MACROTILE,ISP End-of-Macrotile" "0,1" newline bitfld.quad 0x18 3. "PIXELBE_END_RENDER,The 3D phase has completed" "0,1" newline bitfld.quad 0x18 2. "COMPUTE_FINISHED,The compute phase has completed" "0,1" newline bitfld.quad 0x18 1. "KERNEL_FINISHED,A compute kernel has completed and updated the associated event object in external memory" "0,1" newline rbitfld.quad 0x18 0. "RESERVED_0," "0,1" line.quad 0x20 "CORE_MMRS_RGX_CR_GPIO_OUTPUT_DATA,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware" hexmask.quad 0x20 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x20 0.--7. 1. "DATA,The data the firmware wants to transfer" line.quad 0x28 "CORE_MMRS_RGX_CR_GPIO_OUTPUT_REQ,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware" hexmask.quad 0x28 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x28 0. "REQ,Set when the firmware wants to communicate with a external HW" "0,1" rgroup.quad 0x150++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_GPIO_INPUT_DATA,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware" hexmask.quad 0x0 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x0 0.--7. 1. "DATA,The incoming data from HW external to Rogue" rgroup.quad 0x158++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_GPIO_INPUT_ACK,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware" hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "ACK,Set by the firmware when it has acknowledged the incoming request" "0,1" rgroup.quad 0x160++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_TIMER,This register contains the value of a 48-bit internal timer." bitfld.quad 0x0 63. "BIT31," "0,1" newline hexmask.quad.word 0x0 48.--62. 1. "RESERVED_48," newline hexmask.quad 0x0 0.--47. 1. "VALUE," rgroup.quad 0x168++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_AXI_EXACCESS,AXI exclusive access enable register" hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "SOCIF_ENABLE,enable the exclusive access logic in the socif img_axi2img. vhd module" "0,1" rgroup.quad 0x190++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_TASK_MLIST_LOAD,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters)." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "PENDING,A write to this register will cause the MLIST pointer to be loaded from either PM_MLIST0_START_OF or PM_MLIST1_START_OF depending upon the Context ID contained in PM_CONTEXT_ID_MLS_LS." "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_PM_TASK_MLIST_CLEAR,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters)." hexmask.quad 0x8 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x8 0. "PENDING,A write to this register will cause the MLIST pointer to be reset to 0. A read to this register return '1' until this operation has completed." "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_PM_TA_MAX_RENDER_TARGET,This register is deprecated and has no function." hexmask.quad 0x10 11.--63. 1. "RESERVED_11," newline hexmask.quad.word 0x10 0.--10. 1. "ID,If used the software should program this with the maximum render target array index used within the Scene" rgroup.quad 0x1A8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_MTILE_ARRAY_REORDER_VALID_STATUS,This register is deprecated and has no function." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "OP," "0,1" rgroup.quad 0x1B0++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_PM_EMPTY_PAGE_FAST_FREEING,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters)." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "ID,When set enable freeing of unused pages during TA phase" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_PM_MMU_REMAP_PENDING,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters)." hexmask.quad 0x8 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x8 0. "OP,Pending status register corresponding to the MMU remapping operation it will become '1' when written and deassert when the operation complete." "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_PM_PBE_FORCE_FREEING,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters)." hexmask.quad 0x10 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x10 0. "ENABLE,When this bit is set PM will free all the 3D context Memory when a genuine pixelbe end of render is received." "0,1" line.quad 0x18 "CORE_MMRS_RGX_CR_PM_PDS_STARTOF_MTILEFREE," hexmask.quad 0x18 17.--63. 1. "RESERVED_17," newline hexmask.quad.tbyte 0x18 0.--16. 1. "OP,This startof register indicates the macrotile number of the PDSs current macrotile free request needs to be programmed by FW on a render start" rgroup.quad 0x200++0x27 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_TASK_3D_FREE_LOAD," hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "PENDING,A write into this register will cause the 3D free list context to be loaded from the relevant configuration registers" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_PM_TASK_TA_FREE_LOAD," hexmask.quad 0x8 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x8 0. "PENDING,A write into this register will cause the TA free list context to be loaded from the relevant configuration registers" "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_PM_TA_FSTACK_BASE,Effective on load TA context. this register defines the base address of the free list stack being referenced during TA processing." hexmask.quad.tbyte 0x10 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x10 4.--39. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for TA context page tables in the DPM module" newline hexmask.quad.byte 0x10 0.--3. 1. "RESERVED_0," line.quad 0x18 "CORE_MMRS_RGX_CR_PM_3D_FSTACK_BASE,Effective on load 3D context. this register defines the base address of the free list table being referenced in the process of de-allocating pages during a 3D render." hexmask.quad.tbyte 0x18 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x18 4.--39. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for 3D context page tables in the DPM module" newline hexmask.quad.byte 0x18 0.--3. 1. "RESERVED_0," line.quad 0x20 "CORE_MMRS_RGX_CR_PM_TA_FSTACK,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned" hexmask.quad.word 0x20 54.--63. 1. "RESERVED_54," newline hexmask.quad.tbyte 0x20 32.--53. 1. "STARTOF_TOP,This register defines the head pointer of the free list in terms of 4K free pages in the free list stack effective on a load TA context." newline hexmask.quad.word 0x20 22.--31. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x20 0.--21. 1. "SIZE,This register defines the number of 4K pages in the free list stack used for the TA page allocation effective on a load TA context." rgroup.quad 0x230++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_3D_FSTACK,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned" hexmask.quad.tbyte 0x0 44.--63. 1. "RESERVED_44," newline hexmask.quad.tbyte 0x0 22.--43. 1. "STARTOF_TOP,This register defines the head pointer of the free list in terms of 4K free pages in the free list stack effective on a load TA context." newline hexmask.quad.tbyte 0x0 0.--21. 1. "SIZE,This register defines the number of 4K pages in the free list stack used for the TA page allocation effective on a load TA context." rgroup.quad 0x240++0x2F line.quad 0x0 "CORE_MMRS_RGX_CR_PM_MTILE_ARRAY,Effective Immediately." hexmask.quad.tbyte 0x0 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x0 4.--39. 1. "BASE_ADDR,1TB Addressable 128 bits aligned Base Address for Mtile Array Base" newline hexmask.quad.byte 0x0 0.--3. 1. "RESERVED_0," line.quad 0x8 "CORE_MMRS_RGX_CR_PM_VHEAP_TABLE,Effective immediately. this register defines the base address of the virtual heap table information." hexmask.quad.tbyte 0x8 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x8 4.--39. 1. "BASE_ADDR,1TB Addressable 128 bits aligned Base Address for Virtual Heap Table" newline hexmask.quad.byte 0x8 0.--3. 1. "RESERVED_0," line.quad 0x10 "CORE_MMRS_RGX_CR_PM_TASK_VHEAP_LOAD," hexmask.quad 0x10 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x10 0. "PENDING,Causes the vheap to be loaded as specified by the relevant configuration registers when it is done the hw will clear this bit" "0,1" line.quad 0x18 "CORE_MMRS_RGX_CR_PM_TASK_VHEAP_CLEAR," hexmask.quad 0x18 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x18 0. "PENDING,Causes the vheap to be cleared as specified by the relevant configuration registers. When it is done the hw will clear this bit" "0,1" line.quad 0x20 "CORE_MMRS_RGX_CR_PM_TASK_VHEAP_STORE," hexmask.quad 0x20 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x20 0. "PENDING,Causes the vheap to be stored as specified by the relevant configuration registers. When it is done the hw will clear this bit" "0,1" line.quad 0x28 "CORE_MMRS_RGX_CR_PM_ALIST0_START_OF,start pointer of the allocation list tail.in size of 8 bytes" hexmask.quad.long 0x28 33.--63. 1. "RESERVED_33," newline hexmask.quad 0x28 0.--32. 1. "TAIL,allocation List 0 tail pointer" rgroup.quad 0x270++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_ALIST0_STATUS,pointer of current allocation list.in size of 8 bytes" hexmask.quad.long 0x0 33.--63. 1. "RESERVED_33," newline hexmask.quad 0x0 0.--32. 1. "TAIL,allocation List tail pointer" rgroup.quad 0x278++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_ALIST1_START_OF,start of the tail pointer of current allocation list.effecitve on an allocation_list_load" hexmask.quad.long 0x0 33.--63. 1. "RESERVED_33," newline hexmask.quad 0x0 0.--32. 1. "TAIL,start of the allocation list tail pointer" rgroup.quad 0x280++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_ALIST1_STATUS,pointer of current allocation list.in size of 8 bytes" hexmask.quad.long 0x0 33.--63. 1. "RESERVED_33," newline hexmask.quad 0x0 0.--32. 1. "TAIL,allocation List tail pointer" rgroup.quad 0x288++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_PM_TASK_ALIST_LOAD," hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "PENDING,the write to this register will cause allocation list to be loaded from the relevant configuration registers" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_PM_TASK_ALIST_CLEAR," hexmask.quad 0x8 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x8 0. "PENDING,the write to this register will causes the allocation list to be cleard from the relevant configuration registers" "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_PM_DEALLOCATION_STARTOF_MASK," hexmask.quad 0x10 16.--63. 1. "RESERVED_16," newline hexmask.quad.word 0x10 0.--15. 1. "OP,This is the start of the mask PM deallocation will be based on. Normally it is 0. However in ISP context resume or extra 3D timeout case the driver has to.." line.quad 0x18 "CORE_MMRS_RGX_CR_PM_PAGE_MANAGEOP," hexmask.quad 0x18 3.--63. 1. "RESERVED_3," newline bitfld.quad 0x18 2. "COMBINE_DALLOC,1 means the PM writes to the free stack will be burst combined" "0,1" newline bitfld.quad 0x18 1. "DISABLE_DALLOC,1 means the PM page management deallocation operation will be disabled" "0,1" newline bitfld.quad 0x18 0. "DISABLE_ALLOC,1 means the PM page management allocation operation will be disabled" "0,1" rgroup.quad 0x2A8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_PAGE_MANAGEOP_STATUS," hexmask.quad 0x0 2.--63. 1. "RESERVED_2," newline bitfld.quad 0x0 1. "DALLOC_DISABLED,1 means the PM page management operation has been disabled" "0,1" newline bitfld.quad 0x0 0. "ALLOC_DISABLED,1 means the PM page management operation has been disabled" "0,1" rgroup.quad 0x2B0++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_PM_CONTEXT_PB_BASE," hexmask.quad 0x0 3.--63. 1. "RESERVED_3," newline bitfld.quad 0x0 0.--2. "CMP,Defines whether the TA/3D/HOST contexts are using the same parameter buffer. Setting a bit to '1' indicates that the context is using a different parameter buffer." "0: MMU Free List 3D context Parameter buffer = MMU..,?,?,?,?,?,?,?" line.quad 0x8 "CORE_MMRS_RGX_CR_PM_MLIST0_START_OF,start value of the mlist tail @ the loading of the context." hexmask.quad 0x8 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x8 0.--21. 1. "TAIL,allocation List 0 tail pointer" rgroup.quad 0x2C0++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_MLIST0_STATUS,pointer of current mmu allocation list.in size of 4 bytes." hexmask.quad 0x0 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x0 0.--21. 1. "TAIL,allocation List 1 tail pointer" rgroup.quad 0x2C8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_MLIST1_START_OF,start of the tail pointer of mmu allocation list.effecitve on an allocation_list_load" hexmask.quad 0x0 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x0 0.--21. 1. "TAIL,start of the allocation list 1 tail pointer" rgroup.quad 0x2D0++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_MLIST1_STATUS,pointer of mmu allocation list1 pointer.in size of 4 bytes" hexmask.quad 0x0 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x0 0.--21. 1. "TAIL,mmu allocation List 1 tail pointer" rgroup.quad 0x2D8++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_PM_MLIST0_BASE,This register defines the base address of the mmu list 0 for the mmu pages." hexmask.quad.tbyte 0x0 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x0 4.--39. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for mmu list0 module Effective Immediately" newline hexmask.quad.byte 0x0 0.--3. 1. "RESERVED_0," line.quad 0x8 "CORE_MMRS_RGX_CR_PM_MLIST1_BASE,This register defines the base address of the mmu list 1 for the mmu pages." hexmask.quad.tbyte 0x8 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x8 4.--39. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for mmu list1 module Effective Immediately" newline hexmask.quad.byte 0x8 0.--3. 1. "RESERVED_0," rgroup.quad 0x2F8++0x27 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_VCE_VTOP_STATUS," hexmask.quad 0x0 21.--63. 1. "RESERVED_21," newline hexmask.quad.tbyte 0x0 0.--20. 1. "OP,Virtual Page Pointer for the VCE 8KB granularity" line.quad 0x8 "CORE_MMRS_RGX_CR_PM_TE_VTOP_STATUS," hexmask.quad 0x8 21.--63. 1. "RESERVED_21," newline hexmask.quad.tbyte 0x8 0.--20. 1. "OP,Virtual Page Pointer for the TE 8KB granularity" line.quad 0x10 "CORE_MMRS_RGX_CR_PM_OUTOF_MEM_SRC," hexmask.quad 0x10 3.--63. 1. "RESERVED_3," newline bitfld.quad 0x10 0.--2. "OP,one hot encoding indicating which part of resource runs out of memory bit 0: normal ta free list bit 1: unified ta free list bit 2: mmu free list" "0: normal ta free list,1: unified ta free list,2: mmu free list,?,?,?,?,?" line.quad 0x18 "CORE_MMRS_RGX_CR_PM_ALIST_VTOP_STATUS," hexmask.quad 0x18 21.--63. 1. "RESERVED_21," newline hexmask.quad.tbyte 0x18 0.--20. 1. "OP,Virtual Page Pointer for the allocation list 8KB granularity" line.quad 0x20 "CORE_MMRS_RGX_CR_PM_MMU_VTOP_STATUS," hexmask.quad 0x20 21.--63. 1. "RESERVED_21," newline hexmask.quad.tbyte 0x20 0.--20. 1. "OP,Virtual Page Pointer for the MMU 4KB granularity" rgroup.quad 0x320++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_PM_OUTOFMEM_ABORTALL," hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "OP,Instruct the PM to Deny the TE allocation outstanding on Out Of Memory" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_PM_OUTOFMEM_RESTART," hexmask.quad 0x8 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x8 0. "OP,Restart the PM after an Out of Memory and Abort sequence" "0,1" rgroup.quad 0x330++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_REQUESTING_SOURCE," hexmask.quad 0x0 2.--63. 1. "RESERVED_2," newline bitfld.quad 0x0 0.--1. "OP,Requesting source when out of memory. Bit 1 : VCE Bit 0 : TE" "0: TE,1: VCE,?,?" rgroup.quad 0x338++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_PM_PARTIAL_RENDER_ENABLE," hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "OP,Partial Render Enable Bit" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_PM_3D_DEALLOCATE_SCANMODE," hexmask.quad 0x8 5.--63. 1. "RESERVED_5," newline hexmask.quad.byte 0x8 0.--4. 1. "OP,This register defines the deallocation behaviour of the PM: value > 2 is only for debug on ZLS mode 0 it can only set less than 2 0: PM will free the macrotile memory as soon as it is possible.." rgroup.quad 0x348++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_PM_TA_FSTACK_STATUS,Note: this is the pointer pointing to the TA free stack top." hexmask.quad 0x0 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the ta context free list pointer status." line.quad 0x8 "CORE_MMRS_RGX_CR_PM_3D_FSTACK_STATUS,Note: this is the pointer pointing to the 3D free stack top." hexmask.quad 0x8 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x8 0.--21. 1. "TOP,This status register indicated the 3D context free list status" rgroup.quad 0x358++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_RESERVE_PAGES," hexmask.quad 0x0 16.--63. 1. "RESERVED_16," newline hexmask.quad.word 0x0 0.--15. 1. "OP,This register defines the guard page required for one VCE/TE allocation. The requirement is set by the number of ppages needed to create the ALIST nodes when a vpage is closed." rgroup.quad 0x360++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_DEALLOCATED_MASK_STATUS," hexmask.quad 0x0 16.--63. 1. "RESERVED_16," newline hexmask.quad.word 0x0 0.--15. 1. "TOP,This status register contains a bitmask of the macrotiles freed at this point in the render" line.quad 0x8 "CORE_MMRS_RGX_CR_PM_DEALLOCATING_MASK_STATUS," hexmask.quad 0x8 16.--63. 1. "RESERVED_16," newline hexmask.quad.word 0x8 0.--15. 1. "TOP,This status register indicates the mtile mask being freed at the current traverse" line.quad 0x10 "CORE_MMRS_RGX_CR_PM_PDS_MTILEFREE_STATUS," hexmask.quad 0x10 17.--63. 1. "RESERVED_17," newline hexmask.quad.tbyte 0x10 0.--16. 1. "OP,This status register indicates the macrotile number of the PDSs current macrotile free request" rgroup.quad 0x378++0x27 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_TA_FREE_CONTEXT," hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "PENDING,free the ta context register operation" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_PM_3D_TIMEOUT_NOW," hexmask.quad 0x8 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x8 0. "OP,free the 3D context" "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_PM_3D_DEALLOCATE_ENABLE," hexmask.quad 0x10 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x10 0. "OP,3D deallocate enable mode" "0,1" line.quad 0x18 "CORE_MMRS_RGX_CR_PM_START_OF_TACONTEXT," hexmask.quad.word 0x18 54.--63. 1. "RESERVED_54," newline hexmask.quad.tbyte 0x18 32.--53. 1. "ALLOCATED_MMUPAGE,Start of TA MMU pages[4KB] on loading of the TA context" newline hexmask.quad.word 0x18 22.--31. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x18 0.--21. 1. "ALLOCATED_PAGE,Start of TA pages[4KB] on loading of the TA context" line.quad 0x20 "CORE_MMRS_RGX_CR_PM_START_OF_3DCONTEXT," hexmask.quad.word 0x20 54.--63. 1. "RESERVED_54," newline hexmask.quad.tbyte 0x20 32.--53. 1. "ALLOCATED_MMUPAGE,Start of 3D MMU pages[4KB] on loading of the TA context" newline hexmask.quad.word 0x20 22.--31. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x20 0.--21. 1. "ALLOCATED_PAGE,Start of 3D pages[4KB] on loading of the TA context" rgroup.quad 0x3A0++0x2F line.quad 0x0 "CORE_MMRS_RGX_CR_PM_TA_PAGE_STATUS," hexmask.quad 0x0 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x0 0.--21. 1. "OP,The number of TA pages currently allocated" line.quad 0x8 "CORE_MMRS_RGX_CR_PM_3D_PAGE_STATUS," hexmask.quad 0x8 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x8 0.--21. 1. "OP,The number of 3D pages currently allocated" line.quad 0x10 "CORE_MMRS_RGX_CR_PM_VCE_INFLIGHT_STATUS," hexmask.quad 0x10 21.--63. 1. "RESERVED_21," newline hexmask.quad.tbyte 0x10 0.--20. 1. "OP,The Virtual Page Number in flight in the VCE Requestor" line.quad 0x18 "CORE_MMRS_RGX_CR_PM_TE_INFLIGHT_STATUS," hexmask.quad 0x18 21.--63. 1. "RESERVED_21," newline hexmask.quad.tbyte 0x18 0.--20. 1. "OP,The Virtual Page Number in flight in the TE Requestor" line.quad 0x20 "CORE_MMRS_RGX_CR_BIFPM_IDLE," hexmask.quad 0x20 7.--63. 1. "RESERVED_7," newline bitfld.quad 0x20 6. "MCU_L0_MEMIF,MCU L0 MEMIF Module IDLE" "0,1" newline bitfld.quad 0x20 5. "PBE,PBE Module IDLE" "0,1" newline bitfld.quad 0x20 4. "MCU_L0_PDSRW,MCU L0 PDSRW Module IDLE" "0,1" newline bitfld.quad 0x20 3. "MCU_L1,MCU L1 Module IDLE" "0,1" newline bitfld.quad 0x20 2. "USCS,USC Shared Module IDLE" "0,1" newline bitfld.quad 0x20 1. "PM,PM Module IDLE" "0,1" newline bitfld.quad 0x20 0. "BIF256,BIF256 Module IDLE" "0,1" line.quad 0x28 "CORE_MMRS_RGX_CR_SIDEKICK_IDLE," hexmask.quad 0x28 7.--63. 1. "RESERVED_7," newline bitfld.quad 0x28 6. "FB_CDC,FB CDC Module IDLE" "0,1" newline bitfld.quad 0x28 5. "MMU,MMU Module IDLE" "0,1" newline bitfld.quad 0x28 4. "BIF128,BIF128 Module IDLE" "0,1" newline bitfld.quad 0x28 3. "TLA,TLA Module IDLE" "0,1" newline bitfld.quad 0x28 2. "GARTEN,GARTEN Module IDLE" "0,1" newline bitfld.quad 0x28 1. "HOSTIF,HOSTIF Module IDLE" "0,1" newline bitfld.quad 0x28 0. "SOCIF,SOCIF Module IDLE" "0,1" rgroup.quad 0x3D0++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_CONTEXT_ID," hexmask.quad.tbyte 0x0 41.--63. 1. "RESERVED_41," newline bitfld.quad 0x0 40. "MLIS_LS,MMU page List [TE VCE aligned with this context ]Load Store Context ID" "0,1" newline hexmask.quad.byte 0x0 33.--39. 1. "RESERVED_33," newline bitfld.quad 0x0 32. "MLIS_DALLOC,MMU page List [TE VCE aligned with this context ]DeAllocation Context ID" "0,1" newline hexmask.quad.byte 0x0 25.--31. 1. "RESERVED_25," newline bitfld.quad 0x0 24. "MLIS_ALLOC,MMU page List [TE VCE aligned with this context ]Allocation Context ID" "0,1" newline hexmask.quad.byte 0x0 17.--23. 1. "RESERVED_17," newline bitfld.quad 0x0 16. "LS,Load Store Context ID for the allocation list" "0,1" newline hexmask.quad.byte 0x0 9.--15. 1. "RESERVED_9," newline bitfld.quad 0x0 8. "DALLOC,DeAllocation Context ID for the allocation list" "0,1" newline hexmask.quad.byte 0x0 1.--7. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "ALLOC,Allocation Context ID for the allocation list" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_PM_3D_RENDER_TARGET_INDEX," hexmask.quad 0x8 11.--63. 1. "RESERVED_11," newline hexmask.quad.word 0x8 0.--10. 1. "ID,Render Target ID which is being rendered" line.quad 0x10 "CORE_MMRS_RGX_CR_PM_3D_RENDER_TARGET_LAST," hexmask.quad 0x10 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x10 0. "ID,If this bit is set this means the render will be the last one in the whole render target array. If no multiple render target array is present this bit always needs set" "0,1" rgroup.quad 0x3E8++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_LOCK_STATUS," hexmask.quad 0x0 2.--63. 1. "RESERVED_2," newline bitfld.quad 0x0 1. "TD,Bit 1: 3D free list Lock Status. 0 idle/ 1 used" "0,1" newline bitfld.quad 0x0 0. "TA,Bit 0: TA free list Lock Status. 0 idle/ 1 used." "0: TA free list Lock Status,?" line.quad 0x8 "CORE_MMRS_RGX_CR_PM_LOCK_OWNER," hexmask.quad 0x8 2.--63. 1. "RESERVED_2," newline bitfld.quad 0x8 1. "TD,Bit 1 :3D free list Lock owner. 0 PMA / 1 PMD" "0,1" newline bitfld.quad 0x8 0. "TA,Bit 0: TA free list Lock Owner. 0 PMA / 1 PMD." "0: TA free list Lock Owner,?" line.quad 0x10 "CORE_MMRS_RGX_CR_PM_IDLE_STATUS," hexmask.quad 0x10 8.--63. 1. "RESERVED_8," newline bitfld.quad 0x10 7. "PMD_BIF,Idle Status Register of the PMD module bif state machine" "0,1" newline bitfld.quad 0x10 6. "PMD_FRE,Idle Status Register of the PMD module master state machine" "0,1" newline bitfld.quad 0x10 5. "BIF,Idle Status Register of the BIF Interface default" "0,1" newline bitfld.quad 0x10 4. "BARB,Idle Status Register of the BIF Arbiter state BAR" "0,1" newline bitfld.quad 0x10 3. "AMAN,Idle Status Register of the Alist state machine" "0,1" newline bitfld.quad 0x10 2. "STA,Idle Status Register of the Stack Manager Modul" "0,1" newline bitfld.quad 0x10 1. "PMD,Idle Status Register of the PMD module" "0,1" newline bitfld.quad 0x10 0. "PMA,Idle Status Register of the PMA module" "0,1" rgroup.quad 0x400++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_VDM_START,A write of '1' to this register starts the Vertex Data Master (TA) Reading the control stream pointed to by VDM_CTRL_STREAM_BASE" hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "PULSE,Start VDM" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_VDM_CTRL_STREAM_BASE,The base address of the Vertex Data Master's Input Parameter Control Stream in external memory" hexmask.quad.tbyte 0x8 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x8 2.--39. 1. "ADDR,1TB range 32-bit aligned base address" newline rbitfld.quad 0x8 0.--1. "RESERVED_0," "0,1,2,3" rgroup.quad 0x410++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_VDM_CTRL_STREAM_CURRENT,This status register reports the current position in the input parameter format of the data being processed." hexmask.quad.tbyte 0x0 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x0 2.--39. 1. "ADDR,1TB range 32-bit aligned address" newline bitfld.quad 0x0 0.--1. "RESERVED_0," "0,1,2,3" rgroup.quad 0x418++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_VDM_CALL_STACK_POINTER,The pointer to the control stream call stack." hexmask.quad.tbyte 0x0 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x0 3.--39. 1. "ADDR,1TB range 64-bit aligned base address" newline rbitfld.quad 0x0 0.--2. "RESERVED_0," "0,1,2,3,4,5,6,7" line.quad 0x8 "CORE_MMRS_RGX_CR_VDM_BATCH,The Batch number is a index list block (draw call) ID which is passed through the GPU pipeline." hexmask.quad 0x8 14.--63. 1. "RESERVED_14," newline hexmask.quad.word 0x8 0.--13. 1. "NUMBER," line.quad 0x10 "CORE_MMRS_RGX_CR_VDM_CONTEXT_STATE_BASE,The base address in external memory of the VDM's context state buffer." hexmask.quad.tbyte 0x10 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x10 4.--39. 1. "ADDR,1TB range 128-bit aligned base address" newline hexmask.quad.byte 0x10 0.--3. 1. "RESERVED_0," rgroup.quad 0x430++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_VDM_CONTEXT_STORE_STATUS,This register indicates the status of a VDM context switch operation." hexmask.quad 0x0 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x0 4.--7. 1. "LAST_PIPE,The TA pipe number to which the VDM last sent indices" newline bitfld.quad 0x0 2.--3. "RESERVED_2," "0,1,2,3" newline bitfld.quad 0x0 1. "NEED_RESUME,The VDM still has control stream left to process meaning this context must be resumed" "0,1" newline bitfld.quad 0x0 0. "COMPLETE,The VDM has completed the context store operation and fenced its state to external memory" "0,1" rgroup.quad 0x438++0x67 line.quad 0x0 "CORE_MMRS_RGX_CR_VDM_CONTEXT_STORE_TASK0,These words define the PDS State Update task which will be inserted into the VDM pipeline on a context store operation." hexmask.quad.long 0x0 32.--63. 1. "PDS_STATE1," newline hexmask.quad.long 0x0 0.--31. 1. "PDS_STATE0," line.quad 0x8 "CORE_MMRS_RGX_CR_VDM_CONTEXT_STORE_TASK1,This word defines the PDS State Update task which will be inserted into the VDM pipeline on a context store operation." hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "PDS_STATE2," line.quad 0x10 "CORE_MMRS_RGX_CR_VDM_CONTEXT_STORE_TASK2,These words defines the Stream Out Sync program which will be inserted into the VDM pipeline as a PPP State Update on a context store operation." hexmask.quad.long 0x10 32.--63. 1. "STREAM_OUT2," newline hexmask.quad.long 0x10 0.--31. 1. "STREAM_OUT1," line.quad 0x18 "CORE_MMRS_RGX_CR_VDM_CONTEXT_RESUME_TASK0,These words define the PDS State Update task which will be written by the VDM to its context resume control stream on a context store operation." hexmask.quad.long 0x18 32.--63. 1. "PDS_STATE1," newline hexmask.quad.long 0x18 0.--31. 1. "PDS_STATE0," line.quad 0x20 "CORE_MMRS_RGX_CR_VDM_CONTEXT_RESUME_TASK1,This word defines the PDS State Update task which will be written by the VDM to its context resume control stream on a context store operation." hexmask.quad.long 0x20 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x20 0.--31. 1. "PDS_STATE2," line.quad 0x28 "CORE_MMRS_RGX_CR_VDM_CONTEXT_RESUME_TASK2,These words defines the Stream Out Sync program which will be written." hexmask.quad.long 0x28 32.--63. 1. "STREAM_OUT2," newline hexmask.quad.long 0x28 0.--31. 1. "STREAM_OUT1," line.quad 0x30 "CORE_MMRS_RGX_CR_VDM_CONTEXT_STORE_START,Writing '1' to this register starts the VDM context store operation." hexmask.quad 0x30 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x30 0. "PULSE," "0,1" line.quad 0x38 "CORE_MMRS_RGX_CR_VDM_SYNC_PDS_DATA_BASE,The base address of the PDS data segment base for all TA state sync program" hexmask.quad.long 0x38 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x38 4.--31. 1. "ADDR," newline hexmask.quad.byte 0x38 0.--3. 1. "RESERVED_0," line.quad 0x40 "CORE_MMRS_RGX_CR_CDM_START,A write of '1' to this register starts the Compute Data Master reading it's control stream from memory." hexmask.quad 0x40 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x40 0. "PULSE,Start CDM" "0,1" line.quad 0x48 "CORE_MMRS_RGX_CR_CDM_CTRL_STREAM_BASE,The base address of the Compute Data Master's Input Parameter Control Stream in external memory" hexmask.quad.tbyte 0x48 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x48 2.--39. 1. "ADDR,1TB range 32-bit aligned base address" newline rbitfld.quad 0x48 0.--1. "RESERVED_0," "0,1,2,3" line.quad 0x50 "CORE_MMRS_RGX_CR_CDM_CONTEXT_STORE,Writing '1' to this register starts the CDM context store operation." hexmask.quad 0x50 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x50 0. "PULSE," "0,1" line.quad 0x58 "CORE_MMRS_RGX_CR_CDM_CONTEXT_LOAD,The firmware writes a '1' to this register starts the CDM context load operation." hexmask.quad 0x58 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x58 0. "PENDING," "0,1" line.quad 0x60 "CORE_MMRS_RGX_CR_CDM_CONTEXT_STATE_BASE,The base address in external memory of the CDM's context state buffer." hexmask.quad.tbyte 0x60 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x60 4.--39. 1. "ADDR,1TB range 128-bit aligned base address" newline hexmask.quad.byte 0x60 0.--3. 1. "RESERVED_0," rgroup.quad 0x4A0++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_CDM_CONTEXT_STORE_STATUS,This register indicates the status of a CDM context switch operation." hexmask.quad 0x0 2.--63. 1. "RESERVED_2," newline bitfld.quad 0x0 1. "NEED_RESUME,The CDM still has control stream left to process meaning this context must be resumed" "0,1" newline bitfld.quad 0x0 0. "COMPLETE,The CDM has completed the context store operation and fenced its state to external memory" "0,1" rgroup.quad 0x4A8++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_CDM_CONTEXT_PDS0,This register contains the PDS Code and Data Addresses for the Store/Load Program." hexmask.quad.long 0x0 36.--63. 1. "DATA_ADDR,PDS Data Address for Store/Load Program 128-bit aligned" newline hexmask.quad.byte 0x0 32.--35. 1. "RESERVED_32," newline hexmask.quad.long 0x0 4.--31. 1. "CODE_ADDR,PDS Code Address for Store/Load Program 128-bit aligned" newline hexmask.quad.byte 0x0 0.--3. 1. "RESERVED_0," line.quad 0x8 "CORE_MMRS_RGX_CR_CDM_CONTEXT_PDS1,This register contains the PDS Task Data necessary to produce the Store/Load PDS Program Task from CDM to PDS" hexmask.quad 0x8 30.--63. 1. "RESERVED_30," newline bitfld.quad 0x8 29. "PDS_SEQ_DEP,PDS Sequential Dependency" "0,1" newline bitfld.quad 0x8 28. "USC_SEQ_DEP,USC Sequential Dependency" "0,1" newline bitfld.quad 0x8 27. "TARGET,USC Target [0=All 1=Any]" "0: All,1: Any]" newline hexmask.quad.byte 0x8 21.--26. 1. "UNIFIED_SIZE,Unified Size" newline bitfld.quad 0x8 20. "COMMON_SHARED,PDS Common Store Allocation is Shared Registers" "0,1" newline hexmask.quad.word 0x8 11.--19. 1. "COMMON_SIZE,PDS Common Size" newline hexmask.quad.byte 0x8 7.--10. 1. "TEMP_SIZE,PDS Temp Size" newline hexmask.quad.byte 0x8 1.--6. 1. "DATA_SIZE,PDS Data Size" newline bitfld.quad 0x8 0. "FENCE,Fence the Task in the PDS/USC - Set on Store unset on Load" "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_CDM_TERMINATE_PDS,This register contains the PDS Code and Data Addresses for the Terminate Program." hexmask.quad.long 0x10 36.--63. 1. "DATA_ADDR,PDS Data Address for Terminate Program 128-bit aligned" newline hexmask.quad.byte 0x10 32.--35. 1. "RESERVED_32," newline hexmask.quad.long 0x10 4.--31. 1. "CODE_ADDR,PDS Code Address for Terminate Program 128-bit aligned" newline hexmask.quad.byte 0x10 0.--3. 1. "RESERVED_0," line.quad 0x18 "CORE_MMRS_RGX_CR_CDM_TERMINATE_PDS1,This register contains the PDS Task Data necessary to produce the Context Store Terminate PDS Program Task from CDM to PDS" hexmask.quad 0x18 30.--63. 1. "RESERVED_30," newline bitfld.quad 0x18 29. "PDS_SEQ_DEP,PDS Sequential Dependency" "0,1" newline bitfld.quad 0x18 28. "USC_SEQ_DEP,USC Sequential Dependency" "0,1" newline bitfld.quad 0x18 27. "TARGET,USC Target [0=All 1=Any]" "0: All,1: Any]" newline hexmask.quad.byte 0x18 21.--26. 1. "UNIFIED_SIZE,Unified Size" newline bitfld.quad 0x18 20. "COMMON_SHARED,PDS Common Store Allocation is Shared Registers" "0,1" newline hexmask.quad.word 0x18 11.--19. 1. "COMMON_SIZE,PDS Common Size" newline hexmask.quad.byte 0x18 7.--10. 1. "TEMP_SIZE,PDS Temp Size" newline hexmask.quad.byte 0x18 1.--6. 1. "DATA_SIZE,PDS Data Size" newline bitfld.quad 0x18 0. "FENCE,Fence the Task in the PDS/USC - Set on Store Terminate" "0,1" rgroup.quad 0x4D8++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_CDM_CONTEXT_LOAD_PDS0,This register contains the PDS Code and Data Addresses for the Store/Load Program." hexmask.quad.long 0x0 36.--63. 1. "DATA_ADDR,PDS Data Address for Store/Load Program 128-bit aligned" newline hexmask.quad.byte 0x0 32.--35. 1. "RESERVED_32," newline hexmask.quad.long 0x0 4.--31. 1. "CODE_ADDR,PDS Code Address for Store/Load Program 128-bit aligned" newline hexmask.quad.byte 0x0 0.--3. 1. "RESERVED_0," line.quad 0x8 "CORE_MMRS_RGX_CR_CDM_CONTEXT_LOAD_PDS1,This register contains the PDS Task Data necessary to produce the Store/Load PDS Program Task from CDM to PDS" hexmask.quad 0x8 30.--63. 1. "RESERVED_30," newline bitfld.quad 0x8 29. "PDS_SEQ_DEP,PDS Sequential Dependency" "0,1" newline bitfld.quad 0x8 28. "USC_SEQ_DEP,USC Sequential Dependency" "0,1" newline bitfld.quad 0x8 27. "TARGET,USC Target [0=All 1=Any]" "0: All,1: Any]" newline hexmask.quad.byte 0x8 21.--26. 1. "UNIFIED_SIZE,Unified Size" newline bitfld.quad 0x8 20. "COMMON_SHARED,PDS Common Store Allocation is Shared Registers" "0,1" newline hexmask.quad.word 0x8 11.--19. 1. "COMMON_SIZE,PDS Common Size" newline hexmask.quad.byte 0x8 7.--10. 1. "TEMP_SIZE,PDS Temp Size" newline hexmask.quad.byte 0x8 1.--6. 1. "DATA_SIZE,PDS Data Size" newline bitfld.quad 0x8 0. "FENCE,Fence the Task in the PDS/USC - Set on Store unset on Load" "0,1" rgroup.quad 0x600++0x67 line.quad 0x0 "CORE_MMRS_RGX_CR_PDS_CTRL,Controls the maximum number of tasks per data master (per USC)." hexmask.quad.byte 0x0 56.--63. 1. "RESERVED_56," newline bitfld.quad 0x0 55. "SM_OVERLAP_ENABLE,Enable per Data Master slot tracking within the PDS Slot Manager [SM] for improved performance while running overlapped" "0,1" newline hexmask.quad.tbyte 0x0 32.--54. 1. "RESERVED_32," newline hexmask.quad.byte 0x0 24.--31. 1. "MAX_NUM_CDM_TASKS,The maximum number of compute tasks allowed on each USC range 0 to 48" newline hexmask.quad.byte 0x0 16.--23. 1. "MAX_NUM_PDM_TASKS,The maximum number of pixel tasks allowed on each USC range 0 to 48" newline hexmask.quad.byte 0x0 8.--15. 1. "MAX_NUM_VDM_TASKS,The maximum number of vertex tasks [VS HS GS when Tess not enabled] allowed on each USC range 0 to 39 [Note reduced range to prevent Pixel/VDM system deadlock]" newline hexmask.quad.byte 0x0 0.--7. 1. "RESERVED_0," line.quad 0x8 "CORE_MMRS_RGX_CR_PDS_USC_COLLATOR,This register clear the internal resource tracking storage." hexmask.quad 0x8 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x8 0. "CLEAR,Clear PDS Unified Clusters Resource Collator" "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_PDS_EXEC_BASE,Base Address in memory where the PDS programs are located" hexmask.quad.tbyte 0x10 40.--63. 1. "RESERVED_40," newline hexmask.quad.tbyte 0x10 20.--39. 1. "ADDR,1TB addressable 1 MB aligned base address for PDS programs" newline hexmask.quad.tbyte 0x10 0.--19. 1. "RESERVED_0," line.quad 0x18 "CORE_MMRS_RGX_CR_EVENT_PIXEL_PDS_CODE," hexmask.quad.long 0x18 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x18 4.--31. 1. "ADDR,PDS Execution Address for pixel tasks [Positioned as a byte address 128 bit granularity] 4 GB Range" newline hexmask.quad.byte 0x18 0.--3. 1. "RESERVED_0," line.quad 0x20 "CORE_MMRS_RGX_CR_EVENT_PIXEL_PDS_DATA," hexmask.quad.long 0x20 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x20 4.--31. 1. "ADDR,PDS Execution Address for pixel tasks [Positioned as a byte address 128 bit granularity] 4 GB Range" newline hexmask.quad.byte 0x20 0.--3. 1. "RESERVED_0," line.quad 0x28 "CORE_MMRS_RGX_CR_EVENT_PIXEL_PDS_INFO," hexmask.quad 0x28 15.--63. 1. "RESERVED_15," newline hexmask.quad.byte 0x28 9.--14. 1. "USC_SR_SIZE,USC Shared Register Data Size in 4x128 bit words [0=0] for pixel event task if zero pixel event task is skipped" newline hexmask.quad.byte 0x28 5.--8. 1. "TEMP_STRIDE,PDS Temp Size in 128 bit words [0=0] for pixel event tasks" newline hexmask.quad.byte 0x28 0.--4. 1. "CONST_SIZE,PDS Data Size in 128 bit words [0=0] for pixel event tasks if zero pixel event task is skipped" line.quad 0x30 "CORE_MMRS_RGX_CR_PDS_CSRM,A write of '1' to this register clears the PDS Common Store Resource Manager Contents" hexmask.quad 0x30 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x30 0. "CLEAR,Clear PDS Common Store Resource Manager a write to this register results in a one cycle pulse" "0,1" line.quad 0x38 "CORE_MMRS_RGX_CR_PDS_MAX_CSRM_CHUNKS,Soft Limit Registers for Maximum Allocation Chunks in the Common Store on a Data Master basis." hexmask.quad 0x38 27.--63. 1. "RESERVED_27," newline hexmask.quad.word 0x38 18.--26. 1. "CDM,Max Number of Allocation Regions to Allocate to the Compute Data Master in Common Store" newline hexmask.quad.word 0x38 9.--17. 1. "PDM,Max Number of Allocation Regions to Allocate to the Pixel Data Master in Common Store" newline hexmask.quad.word 0x38 0.--8. 1. "VDM,Max Number of Allocation Regions to Allocate to the VDM Data Master in Common Store" line.quad 0x40 "CORE_MMRS_RGX_CR_PDS_CSRM_MAX_COEFF,The Common Store contains Coefficients and Shared Registers in a maximum of n Lines of 64 Allocation Chunks numbered 0-19." hexmask.quad 0x40 6.--63. 1. "RESERVED_6," newline hexmask.quad.byte 0x40 1.--5. 1. "LINE,Coefficients are allocated from Line 0 upwards this is the maximum Line to use for Coefficients before wrapping" newline bitfld.quad 0x40 0. "LINE_ENABLE,Enable Max Coefficient Line Limit" "0,1" line.quad 0x48 "CORE_MMRS_RGX_CR_PDS_USRM,A write of '1' to this register clears the PDS Unified Store Resource Manager Contents." hexmask.quad 0x48 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x48 0. "CLEAR,Clear PDS Unified Store Resource Manager a write to this register results in a one cycle pulse" "0,1" line.quad 0x50 "CORE_MMRS_RGX_CR_PDS_MAX_USRM_CHUNKS,Soft Limit Registers for Maximum Allocation Chunks in the Unified Store on a Data Master basis." hexmask.quad 0x50 18.--63. 1. "RESERVED_18," newline hexmask.quad.word 0x50 9.--17. 1. "CDM,Max Number of Allocation Regions to Allocate to the Compute Data Master in Unified Store" newline hexmask.quad.word 0x50 0.--8. 1. "VDM,Max Number of Allocation Regions to Allocate to the VDM Data Master in Unified Store" line.quad 0x58 "CORE_MMRS_RGX_CR_PDS_USRM_MAX_TEMP,The Unified Store contains Temporaries and Attributes in n Lines of 16 Allocation Chunks numbered 0- n-1." hexmask.quad 0x58 6.--63. 1. "RESERVED_6," newline hexmask.quad.byte 0x58 1.--5. 1. "LINE,Max Line for use as Temporaries" newline bitfld.quad 0x58 0. "LINE_ENABLE,Enable Max Temporaries Line Limit" "0,1" line.quad 0x60 "CORE_MMRS_RGX_CR_PDS_UVSRM,A write of '1' to this register clears the PDS Unified Vertex Store Resource Manager Contents" hexmask.quad 0x60 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x60 0. "CLEAR,Clear PDS Unified Vertex Store Resource Manager a write to this register results in a one cycle pulse" "0,1" rgroup.quad 0x670++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_PDS_STORERM,A write of '1' to this register clears the PDS Store Resource Manager Contents." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "CLEAR,Clear PDS Store Resource Manager a write to this register results in a one cycle pulse" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_PDS_MAX_STORERM_CHUNKS,Soft Limit Registers for Maximum Allocation Chunks in the PDS Store on a Data Master basis." hexmask.quad.long 0x8 36.--63. 1. "RESERVED_36," newline hexmask.quad.word 0x8 27.--35. 1. "STM,Max Number of Allocation Regions to Allocate to the Stream Out Data Master in PDS Store" newline hexmask.quad.word 0x8 18.--26. 1. "CDM,Max Number of Allocation Regions to Allocate to the Compute Data Master in PDS Store" newline hexmask.quad.word 0x8 9.--17. 1. "PDM,Max Number of Allocation Regions to Allocate to the Pixel Data Master in PDS Store" newline hexmask.quad.word 0x8 0.--8. 1. "VDM,Max Number of Allocation Regions to Allocate to the VDM Data Master in PDS Store" rgroup.quad 0x688++0x3F line.quad 0x0 "CORE_MMRS_RGX_CR_PDS_ICC_INVAL,A write of '1' any bit to this register clears the PDS Instruction Cache for the selected DM" hexmask.quad 0x0 3.--63. 1. "RESERVED_3," newline bitfld.quad 0x0 2. "COMPUTE_PENDING,PDS Instruction Cache Compute [DM 2] has been invalidated" "0,1" newline bitfld.quad 0x0 1. "PIXEL_PENDING,PDS Instruction Cache Pixel [DM 1] has been invalidated" "0,1" newline bitfld.quad 0x0 0. "VERTEX_PENDING,PDS Instruction Cache Vertex [DM 0] has been invalidated" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_PDS_MCU_REQ_CTRL,The PDS makes requests to the MCU to DMA to the PDS store and write data to memory." hexmask.quad 0x8 4.--63. 1. "RESERVED_4," newline bitfld.quad 0x8 2.--3. "SMODE,SLC cache policy to use for requests from the VDM/PDM/CDM/STM resource requestors inside the PDS" "0,1,2,3" newline bitfld.quad 0x8 0.--1. "CMODE,Cache Mode to use for requests from the VDM/PDM/CDM/STM resource requestors inside the PDS" "0,1,2,3" line.quad 0x10 "CORE_MMRS_RGX_CR_PDS_CSRM_MIN_SHARED,The Common Store contains Coefficients and Shared Registers in 14 Lines of 64 Allocation Chunks numbered 0-13." hexmask.quad 0x10 6.--63. 1. "RESERVED_6," newline hexmask.quad.byte 0x10 1.--5. 1. "LINE,Shared are allocated from top line downwards this is the minimum Line to use for Shared Registers before wrapping" newline bitfld.quad 0x10 0. "LINE_ENABLE,Enable Min Shared Register Line Limit" "0,1" line.quad 0x18 "CORE_MMRS_RGX_CR_PDS_BGRND0_BASE,PDS Background Setup Word 0" hexmask.quad.long 0x18 36.--63. 1. "TEXUNICODE_ADDR,This is the PDS Code Address used for 2 programs. The Program which issues the DMAs [DOUTD etc. ] for uniform data and/or texture state." newline hexmask.quad.byte 0x18 32.--35. 1. "RESERVED_32," newline hexmask.quad.long 0x18 4.--31. 1. "SHADER_ADDR,The pixel shader base is the base address of the PDS Data Segment. The code segment is address is PDS_PIXEL_SHADERBASE + PDS_PIXELSHADERSIZE. The pixel shader program issues the DOUTU.." newline hexmask.quad.byte 0x18 0.--3. 1. "RESERVED_0," line.quad 0x20 "CORE_MMRS_RGX_CR_PDS_BGRND1_BASE,PDS Background Setup Word 1" hexmask.quad.long 0x20 36.--63. 1. "TEXTUREDATA_ADDR,This points to the DMAs to load the Texture State [or contains the State with DOUTW commands]" newline hexmask.quad.byte 0x20 32.--35. 1. "RESERVED_32," newline hexmask.quad.long 0x20 4.--31. 1. "VARYING_ADDR,This is the base address of the PDS Data Segment. The code segment is address is PDS_VARYINGBASE + PDS_VARYINGSIZE [PDS_BGRND_SIZEINFO1]." newline hexmask.quad.byte 0x20 0.--3. 1. "RESERVED_0," line.quad 0x28 "CORE_MMRS_RGX_CR_PDS_BGRND2_BASE,PDS Background Setup Word 2" hexmask.quad.long 0x28 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x28 4.--31. 1. "UNIFORMDATA_ADDR,This points to the DMAs to load the Uniforms [or contains the Uniforms with DOUTW commands]" newline hexmask.quad.byte 0x28 0.--3. 1. "RESERVED_0," line.quad 0x30 "CORE_MMRS_RGX_CR_PDS_BGRND3_SIZEINFO,If any of the size fields are 0. then that program will not be run." hexmask.quad.word 0x30 55.--63. 1. "USC_SHAREDSIZE,The common store allocation size for the shared registers [texture and uniform data commbined]" newline hexmask.quad.word 0x30 46.--54. 1. "RESERVED_46," newline hexmask.quad.word 0x30 32.--45. 1. "PDS_BATCHNUM,The batch ID to be associated with the background" newline hexmask.quad.word 0x30 23.--31. 1. "PDS_UNIFORMSIZE,The size of the Uniform PDS Data Segment in 128 bit words" newline hexmask.quad.byte 0x30 16.--22. 1. "PDS_TEXTURESTATESIZE,The size of the Texture PDS Data Segment in 128 bit words" newline hexmask.quad.byte 0x30 10.--15. 1. "PDS_VARYINGSIZE,The size of the Varying/Coefficient PDS Data Segment in 128 bit words" newline hexmask.quad.byte 0x30 4.--9. 1. "USC_VARYINGSIZE,The size of the Varying/Coefficient USC Common Store Data in 4x128 bit words" newline hexmask.quad.byte 0x30 0.--3. 1. "PDS_TEMPSIZE,0 = 0 128 bit words 1 = 1 128 bit word this applies to coefficient uniform and varying state" line.quad 0x38 "CORE_MMRS_RGX_CR_PDS_USRM_MIN_ATTR,The Unified Store contains Temporaries and Attributes in n Lines of 16 Allocation Chunks numbered 0 - n-1." hexmask.quad 0x38 6.--63. 1. "RESERVED_6," newline hexmask.quad.byte 0x38 1.--5. 1. "LINE,Min Line for use for Attributes" newline bitfld.quad 0x38 0. "LINE_ENABLE,Enable Min Attributes Line Limit" "0,1" rgroup.quad 0x6D0++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_PDS_PIXELMERGE," hexmask.quad 0x0 7.--63. 1. "RESERVED_7," newline bitfld.quad 0x0 6. "TASK_DISABLE,Disable pixel merging within a whole pixel fragment task" "0,1" newline bitfld.quad 0x0 5. "DISABLE,Disable pixel merging within each 2x2 pixel block of a pixel fragment task" "0,1" newline hexmask.quad.byte 0x0 0.--4. 1. "GRADLIMIT,Gradient difference limit for PDS PP pixel merging" line.quad 0x8 "CORE_MMRS_RGX_CR_PDS_CSRM_USC_DEBUG,When written a non zero value. this register assigns an extra degree of space to be allocated in the Common Store via the PDS CSRM for USC debugging on Shared Allocations." hexmask.quad 0x8 5.--63. 1. "RESERVED_5," newline hexmask.quad.byte 0x8 0.--4. 1. "SIZE,Amount of Space [in 512-bit Allocation Regions] to allocate to USC Debug Space on a Shared Allocation." line.quad 0x10 "CORE_MMRS_RGX_CR_PDS_CSRM_DISABLE,When this register is set. the CSRM will be configured on PDS CSRM CLEAR to not reserve any space for Partitions (this is normally governed by the AA MODE and PIXEL OUTPUT CTRL WIDTH register settings)." hexmask.quad 0x10 3.--63. 1. "RESERVED_3," newline bitfld.quad 0x10 2. "COEFF_SLIDE,Disable Slide of Coeff Allocations on Failure" "0,1" newline bitfld.quad 0x10 1. "SHARED_SLIDE,Disable Slide of Shared Allocations on Failure" "0,1" newline rbitfld.quad 0x10 0. "RESERVED_0," "0,1" rgroup.quad 0x6E8++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_HUB_IDLE," hexmask.quad 0x0 3.--63. 1. "RESERVED_3," newline bitfld.quad 0x0 2. "CDM,CDM Module IDLE" "0,1" newline bitfld.quad 0x0 1. "VDM,VDM Module IDLE" "0,1" newline bitfld.quad 0x0 0. "PDS,PDS Module IDLE" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_HUB_PWR," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "NUM_PDS_INST,Number of PDS instructions" rgroup.quad 0x700++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_PDS_PASSGROUP," hexmask.quad 0x0 2.--63. 1. "RESERVED_2," newline bitfld.quad 0x0 1. "FORCE_PT,Force the use of Hard SDs between punchthrough or depth feedback type passes" "0,1" newline bitfld.quad 0x0 0. "ENABLE,Enable pass group optimisation within USC by replacing USC Hard SDs with USC Soft SDs for all pass groups in the PDS PP." "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_PDS_COMPUTE_THREAD_BARRIER," hexmask.quad 0x8 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x8 0. "ENABLE,Enable thread barrier support in the PDS CDM_RR." "0,1" rgroup.quad 0x720++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PDS_CSRM_SETUP,If the ENABLE field is set. then when the PDS CSRM is Cleared via the PDS_CSRM_CLEAR register." hexmask.quad 0x0 6.--63. 1. "RESERVED_6," newline bitfld.quad 0x0 5. "HALF,Top line is prefilled half full" "0,1" newline hexmask.quad.byte 0x0 1.--4. 1. "MAX_LINE,[Lower 4 bits of] Maximum Line within the CSRM that can be allocated to Shared Registers/Coefficients" newline bitfld.quad 0x0 0. "ENABLE,Enable use of this register to set the Maximum Line the CSRM can allocate on behalf of the USC Common Store" "0,1" rgroup.quad 0x738++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PDS_USRM_DISABLE,When this register is set. the USRM will be configured on PDS USRM CLEAR to disable the Temp/Attribute slide functionality which allows" hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "TEMP_SLIDE,Disable Slide of Temp Allocations on Failure" "0,1" rgroup.quad 0x788++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PDS_CSRM_PIXEL,The Common Store contains Coefficients and Shared Registers in a maximum of n Lines of 64 Allocation Chunks numbered 0-31." hexmask.quad 0x0 6.--63. 1. "RESERVED_6," newline hexmask.quad.byte 0x0 1.--5. 1. "MAX_LINE,Coefficients are allocated from Line 0 upwards this is the maximum Line to reserve for ONLY PDM Coefficients. The Max line of this region is set in the PDS_CSRM_MAX_COEFF register" newline bitfld.quad 0x0 0. "MODE_ENABLE,Enable PIXEL RESERVE MODE in the PDS CSRM" "0,1" rgroup.quad 0x890++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_XPU_BROADCAST,This register contains a bit for this. the primary XPU and for each secondary device connected to the primary." hexmask.quad 0x0 9.--63. 1. "RESERVED_9," newline hexmask.quad.word 0x0 0.--8. 1. "MASK,If bit N is set forward broadcast XPU register writes to this device." line.quad 0x8 "CORE_MMRS_RGX_CR_XPU_RW_ORDER," hexmask.quad 0x8 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x8 0. "FORCE,1 - Force reads and writes to complete in order with respect to each other on the XPU register AXI bus by stalling read requests if any writes are outstanding and vice versa. 0 - No ordering.." "0: No ordering is enforced between reads and writes,1: Force reads and writes to complete in order with.." rgroup.quad 0x8F0++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_SLAVE_EVENT,This register contains a bit for each slave connected to this." hexmask.quad 0x0 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x0 0.--7. 1. "STATUS,If bit N is set an interrupt from slave N is pending." line.quad 0x8 "CORE_MMRS_RGX_CR_MARS_IDLE," hexmask.quad 0x8 3.--63. 1. "RESERVED_3," newline bitfld.quad 0x8 2. "MH_SYSARB0,SYSARB0 Module IDLE" "0,1" newline bitfld.quad 0x8 1. "CPU,CPU Module IDLE" "0,1" newline bitfld.quad 0x8 0. "SOCIF,SOCIF Module IDLE" "0,1" rgroup.quad 0xB00++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_MTS_SCHEDULE,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.quad 0x0 9.--63. 1. "RESERVED_9," newline bitfld.quad 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.quad 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.quad 0x0 5. "CONTEXT," "0,1" newline bitfld.quad 0x0 4. "TASK," "0,1" newline hexmask.quad.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.quad 0x8 "CORE_MMRS_RGX_CR_MTS_PROC_COMPLETE,This register allows firmware tasks to signal process completion." hexmask.quad 0x8 2.--63. 1. "RESERVED_2," newline bitfld.quad 0x8 1. "CONTEXT," "0,1" newline rbitfld.quad 0x8 0. "RESERVED_0," "0,1" rgroup.quad 0xB10++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_MTS_BGCTX_SBDATA0,This register contains the sideband data for the process running on the background context of thread 0." hexmask.quad 0x0 9.--63. 1. "RESERVED_9," newline bitfld.quad 0x0 6.--8. "OS_ID,The OS_ID of the active thread" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x0 5. "THREAD_ACTIVE,Indicates the thread is active" "0,1" newline bitfld.quad 0x0 4. "TASK," "0,1" newline hexmask.quad.byte 0x0 0.--3. 1. "DM,DataMaster Type" rgroup.quad 0xB20++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_MTS_INTCTX_SBDATA0,This register contains the sideband data for the process running on the interrupt context of thread 0." hexmask.quad.tbyte 0x0 42.--63. 1. "RESERVED_42," newline bitfld.quad 0x0 39.--41. "OS_ID,The OS_ID of the active thread" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x0 38. "THREAD_ACTIVE,Indicates the thread is active" "0,1" newline hexmask.quad.long 0x0 6.--37. 1. "INT_STATUS,Interrupt Status for 32 event bus lines" newline hexmask.quad.byte 0x0 2.--5. 1. "DM,DataMaster Type" newline bitfld.quad 0x0 0.--1. "INT_TASK,Kick Request for timer/BG-request/host" "0,1,2,3" rgroup.quad 0xB30++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_MTS_BGCTX_THREAD0_DM_ASSOC,This register is the DataMaster assocation for the background context of thread 0." hexmask.quad 0x0 16.--63. 1. "RESERVED_16," newline hexmask.quad.word 0x0 0.--15. 1. "DM_ASSOC,DataMaster Association [Active High]" rgroup.quad 0xB40++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_MTS_INTCTX_THREAD0_DM_ASSOC,This register is the DataMaster assocation for the interrupt context of thread 0." hexmask.quad 0x0 16.--63. 1. "RESERVED_16," newline hexmask.quad.word 0x0 0.--15. 1. "DM_ASSOC,DataMaster Association [Active High]" rgroup.quad 0xB50++0x47 line.quad 0x0 "CORE_MMRS_RGX_CR_MTS_GARTEN_WRAPPER_CONFIG,This register contains the configuration options for the Garten wrapper." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "IDLE_CTRL," "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_MTS_DM0_INTERRUPT_ENABLE,Interrupt enable status register for DataMaster 0" hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "INT_ENABLE,Interrupt Enable" line.quad 0x10 "CORE_MMRS_RGX_CR_MTS_DM1_INTERRUPT_ENABLE,Interrupt enable status register for DataMaster 1" hexmask.quad.long 0x10 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x10 0.--31. 1. "INT_ENABLE,Interrupt Enable" line.quad 0x18 "CORE_MMRS_RGX_CR_MTS_DM2_INTERRUPT_ENABLE,Interrupt enable status register for DataMaster 2" hexmask.quad.long 0x18 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x18 0.--31. 1. "INT_ENABLE,Interrupt Enable" line.quad 0x20 "CORE_MMRS_RGX_CR_MTS_DM3_INTERRUPT_ENABLE,Interrupt enable status register for DataMaster 3" hexmask.quad.long 0x20 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x20 0.--31. 1. "INT_ENABLE,Interrupt Enable" line.quad 0x28 "CORE_MMRS_RGX_CR_MTS_DM4_INTERRUPT_ENABLE,Interrupt enable status register for DataMaster 4" hexmask.quad.long 0x28 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x28 0.--31. 1. "INT_ENABLE,Interrupt Enable" line.quad 0x30 "CORE_MMRS_RGX_CR_MTS_DM5_INTERRUPT_ENABLE,Interrupt enable status register for DataMaster 5" hexmask.quad.long 0x30 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x30 0.--31. 1. "INT_ENABLE,Interrupt Enable" line.quad 0x38 "CORE_MMRS_RGX_CR_MTS_EVENT_MASK,Mask interrupt events" hexmask.quad.long 0x38 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x38 0.--31. 1. "MASK,DESCRIPTION" line.quad 0x40 "CORE_MMRS_RGX_CR_MTS_EVENT_CLEAR,Clear internal interrupt registers" hexmask.quad.long 0x40 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x40 0.--31. 1. "CLEAR,DESCRIPTION" rgroup.quad 0xB98++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_MTS_INTCTX,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.quad 0x0 30.--63. 1. "RESERVED_30," newline hexmask.quad.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.quad.byte 0x0 16.--21. 1. "RESERVED_16," newline hexmask.quad.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.quad.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.quad 0x8 "CORE_MMRS_RGX_CR_MTS_BGCTX,This register contains the sideband data for the MTS internal background context registers" hexmask.quad 0x8 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.quad 0x10 "CORE_MMRS_RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE,This register contains the sideband data for the MTS internal counted background context counters" hexmask.quad.word 0x10 48.--63. 1. "RESERVED_48," newline hexmask.quad.byte 0x10 40.--47. 1. "DM5,A 8 bit counter for DM5" newline hexmask.quad.byte 0x10 32.--39. 1. "DM4,A 8 bit counter for DM4" newline hexmask.quad.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.quad.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.quad.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.quad.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.quad 0x18 "CORE_MMRS_RGX_CR_MTS_GPU_INT_STATUS,This register contains the sideband data for the MTS internal GPU interrupt status" hexmask.quad.long 0x18 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x18 0.--31. 1. "STATUS,A 32 bit register for recored GPU events" rgroup.quad 0xBC0++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_MTS_OS_PRIORITY,Operating System Priority" hexmask.quad 0x0 16.--63. 1. "RESERVED_16," newline bitfld.quad 0x0 14.--15. "ID7,Scheduling priority for operating system 7" "0,1,2,3" newline bitfld.quad 0x0 12.--13. "ID6,Scheduling priority for operating system 6" "0,1,2,3" newline bitfld.quad 0x0 10.--11. "ID5,Scheduling priority for operating system 5" "0,1,2,3" newline bitfld.quad 0x0 8.--9. "ID4,Scheduling priority for operating system 4" "0,1,2,3" newline bitfld.quad 0x0 6.--7. "ID3,Scheduling priority for operating system 3" "0,1,2,3" newline bitfld.quad 0x0 4.--5. "ID2,Scheduling priority for operating system 2" "0,1,2,3" newline bitfld.quad 0x0 2.--3. "ID1,Scheduling priority for operating system 1" "0,1,2,3" newline bitfld.quad 0x0 0.--1. "ID0,Scheduling priority for operating system 0" "0,1,2,3" line.quad 0x8 "CORE_MMRS_RGX_CR_MTS_SCHEDULE_ENABLE,This register is an active-high mask." hexmask.quad 0x8 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x8 0.--7. 1. "MASK," rgroup.quad 0xBD8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_IRQ_OS0_EVENT_STATUS,This register indicates the source of a per-OS host interrupt." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "SOURCE," "0,1" rgroup.quad 0xBE0++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_HOST_IRQ,This register triggers a per-OS host interrupt." hexmask.quad 0x0 3.--63. 1. "RESERVED_3," newline bitfld.quad 0x0 0.--2. "OSID,Indicates the Guest OS for the interrupt" "0,1,2,3,4,5,6,7" line.quad 0x8 "CORE_MMRS_RGX_CR_IRQ_OS0_EVENT_CLEAR,This register clears a per-OS host interrupt." hexmask.quad 0x8 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x8 0. "SOURCE," "0,1" rgroup.quad 0xBF8++0x5F line.quad 0x0 "CORE_MMRS_RGX_CR_META_BOOT," hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "MODE,0 = Don't boot 1 = Boot" "0: Don't boot,1: Boot" line.quad 0x8 "CORE_MMRS_RGX_CR_TE_AA,This register controls the anti-aliasing mode of the Tiling Co-Processor." hexmask.quad 0x8 4.--63. 1. "RESERVED_4," newline bitfld.quad 0x8 3. "Y2,Indicates 4xmsaa when X2 and Y2 are set to 1. This does not affect TE and is only used within TPW." "0,1" newline bitfld.quad 0x8 2. "Y,Anti-Aliasing in Y Plane Enabled" "0,1" newline bitfld.quad 0x8 1. "X,Anti-Aliasing in X Plane Enabled" "0,1" newline bitfld.quad 0x8 0. "X2,2x Anti-Aliasing Enabled affects PPP only" "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_TE_MTILE1,MacroTile Boundaries X Plane" hexmask.quad 0x10 27.--63. 1. "RESERVED_27," newline hexmask.quad.word 0x10 18.--26. 1. "X1,X1 MacroTile boundary left tile X for second column of macrotiles [16MT mode] - 32 pixels across tile" newline hexmask.quad.word 0x10 9.--17. 1. "X2,X2 MacroTile boundary left tile X for third[16MT] column of macrotiles - 32 pixels across tile" newline hexmask.quad.word 0x10 0.--8. 1. "X3,X3 MacroTile boundary left tile X for fourth column of macrotiles [16MT] - 32 pixels across tile" line.quad 0x18 "CORE_MMRS_RGX_CR_TE_MTILE2,MacroTile Boundaries Y Plane." hexmask.quad 0x18 27.--63. 1. "RESERVED_27," newline hexmask.quad.word 0x18 18.--26. 1. "Y1,X1 MacroTile boundary ltop tile Y for second column of macrotiles [16MT mode] - 32 pixels tile height" newline hexmask.quad.word 0x18 9.--17. 1. "Y2,X2 MacroTile boundary top tile Y for third[16MT] column of macrotiles - 32 pixels tile height" newline hexmask.quad.word 0x18 0.--8. 1. "Y3,X3 MacroTile boundary top tile Y for fourth column of macrotiles [16MT] - 32 pixels tile height" line.quad 0x20 "CORE_MMRS_RGX_CR_TE_SCREEN,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of tiles in X & Y axis." hexmask.quad 0x20 21.--63. 1. "RESERVED_21," newline hexmask.quad.word 0x20 12.--20. 1. "YMAX,Maximum Y tile address visible on screen 32 pixel tile height 16Kx16K max screen size" newline rbitfld.quad 0x20 9.--11. "RESERVED_9," "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x20 0.--8. 1. "XMAX,Maximum X tile address visible on screen 32 pixel tile width 16Kx16K max screen size" line.quad 0x28 "CORE_MMRS_RGX_CR_TE_MTILE,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of tiles in X & Y axis." hexmask.quad 0x28 19.--63. 1. "RESERVED_19," newline hexmask.quad.tbyte 0x28 0.--18. 1. "STRIDE,Number of tiles in a Macrotile. Stride = [XTile * YTiles] tiles 32 pixels across by 32 pixels" line.quad 0x30 "CORE_MMRS_RGX_CR_TE_PSG,This register defines the global control for the Parameter Stream Generator within the Tiling Co-Processor." hexmask.quad 0x30 23.--63. 1. "RESERVED_23," newline bitfld.quad 0x30 22. "FORCE_PROTECT,When set the TE shall force the PROTECT bit to 1 for all tiles" "0,1" newline bitfld.quad 0x30 21. "CS_SIZE,Size of control stream chunk. 0x0 512 bit 0x1 1024 bit" "0,1" newline bitfld.quad 0x30 20. "ENABLE_PWR_GATE_STATE,Enables TE PSG power gate state init. 0x0 Disable 0x1 Enable" "0,1" newline bitfld.quad 0x30 19. "ENABLE_CONTEXT_STATE_RESTORE,Enables sampling of Driver TE_STATE_ISP_STATE_ID and TE_ACTIVE_MTILE registers on context switch/restore when set when reset current local value is preserved." "0,1" newline bitfld.quad 0x30 18. "ZONLYRENDER,Don't invalidate Tail Pointer Cache entries on a Terminate command. Only effective when COMPLETEONTERMINATE is 0x0 0x0 Do Invalidate 0x1 Don't.." "0,1" newline bitfld.quad 0x30 17. "COMPLETEONTERMINATE,0x1 Write region headers terminate streams and invalidate tail pointer cache entries on terminate. 0x0 If ZONLYRENDER = 0x0 then force an Interrupt .." "0,1" newline rbitfld.quad 0x30 15.--16. "RESERVED_15," "0,1,2,3" newline bitfld.quad 0x30 14. "CACHE_BYPASS,when set PSG sets its write only cache to bypass mode effectively disabling the cache" "0,1" newline bitfld.quad 0x30 13. "FORCENEWSTATE,Always embed state information in control stream. Debug only." "0,1" newline rbitfld.quad 0x30 11.--12. "RESERVED_11," "0,1,2,3" newline hexmask.quad.word 0x30 0.--10. 1. "REGION_STRIDE,Number of 4kB Pages devoted to region headers for each Render Target - max needed = 0x500" line.quad 0x38 "CORE_MMRS_RGX_CR_TE_PSG_TERMINATE,This register can be written by the driver to define what the TA should terminate tile control streams with." hexmask.quad.tbyte 0x38 40.--63. 1. "RESERVED_40," newline hexmask.quad.byte 0x38 32.--39. 1. "BYTE,Byte to terminate all tile control streams with." newline hexmask.quad.long 0x38 0.--31. 1. "DWORD,Double-word to terminate all tile control streams with." line.quad 0x40 "CORE_MMRS_RGX_CR_TE_PSGREGION_ADDR,This register defines the base address in memory of the Region Header writes by the TA." hexmask.quad.tbyte 0x40 40.--63. 1. "RESERVED_40," newline hexmask.quad.byte 0x40 34.--39. 1. "HEAP,1TB Addressable 16GB aligned Heap Address for Region Header writes" newline hexmask.quad.long 0x40 6.--33. 1. "BASE,16GB Addressable 512-bit aligned Base Address for Region Header writes" newline hexmask.quad.byte 0x40 0.--5. 1. "RESERVED_0," line.quad 0x48 "CORE_MMRS_RGX_CR_TE_TPC_ADDR,This register defines the base address in memory of the Tail Pointer Cache." hexmask.quad.tbyte 0x48 40.--63. 1. "RESERVED_40," newline hexmask.quad.byte 0x48 34.--39. 1. "HEAP,1TB Addressable 16GB aligned Heap Address for Tail Pointer Cache." newline hexmask.quad.long 0x48 6.--33. 1. "BASE,16GB Addressable 512-bit aligned Base Address for Tail Pointer Cache entries. The tail pointer is the current last address written to for a control stream for a tile." newline hexmask.quad.byte 0x48 0.--5. 1. "RESERVED_0," line.quad 0x50 "CORE_MMRS_RGX_CR_TE_TPC,This register defines the TPC Memory footprint size per Render Target as a Stride of 4KB pages" hexmask.quad 0x50 12.--63. 1. "RESERVED_12," newline hexmask.quad.word 0x50 0.--11. 1. "STRIDE,Number of 4KB pages per Render Target in each TPC footprint - max = 2048" line.quad 0x58 "CORE_MMRS_RGX_CR_TE_TPC_CONTEXT,The Tail Pointer Cache is used to keep track of the last address written to for a particular tile." hexmask.quad.long 0x58 32.--63. 1. "RESERVED_32," newline bitfld.quad 0x58 31. "CLEAR_PENDING,Reset contents of Tail Pointer Cache" "0,1" newline bitfld.quad 0x58 30. "FLUSH_PENDING,Flush contents of Tail Pointer Cache to Memory" "0,1" newline hexmask.quad.long 0x58 0.--29. 1. "RESERVED_0," rgroup.quad 0xC58++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_TE_RGNBBOX_X,Reset or enabled by the PPP_RESETBBOX and PPP_UPDATEBBOX fields in the PPPControl word of the Input Parameter format." hexmask.quad 0x0 26.--63. 1. "RESERVED_26," newline hexmask.quad.word 0x0 16.--25. 1. "MAX,XMax value for maintained Region Generator Bounding Box tiles 32 pixels in width" newline hexmask.quad.byte 0x0 10.--15. 1. "RESERVED_10," newline hexmask.quad.word 0x0 0.--9. 1. "MIN,XMin value for maintained Region Generator Bounding Box tiles 32 pixels in width" line.quad 0x8 "CORE_MMRS_RGX_CR_TE_RGNBBOX_Y,Reset or enabled by the PPP_RESETBBOX and PPP_UPDATEBBOX fields in the PPP Control word of the Input Parameter format." hexmask.quad 0x8 26.--63. 1. "RESERVED_26," newline hexmask.quad.word 0x8 16.--25. 1. "MAX,YMax value for maintained Region Generator Bounding Box tiles 16 pixels in height" newline hexmask.quad.byte 0x8 10.--15. 1. "RESERVED_10," newline hexmask.quad.word 0x8 0.--9. 1. "MIN,YMin value for maintained Region Generator Bounding Box tiles 16 pixels in height" rgroup.quad 0xC68++0x5F line.quad 0x0 "CORE_MMRS_RGX_CR_TE_RGNHDR_INIT,A write of '1' to this register starts the TE Region Header Initialisation Sequence" hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "PENDING,Start TE Region Header Initialisation" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_TE_PSG_HAZARD,Control of hazard checking in SLC for TE PSG requesters" hexmask.quad 0x8 2.--63. 1. "RESERVED_2," newline bitfld.quad 0x8 1. "STREAM_CHECK_ENABLE,when set PSG will enable hazard checking in the SLC for control stream writes" "0,1" newline bitfld.quad 0x8 0. "REGION_CHECK_ENABLE,when set PSG will enable hazard checking in the SLC for region header writes" "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_PPP_GRIDOFFSET,Sample position grid offset for use when MSAA/ODAA is DISABLED" hexmask.quad 0x10 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x10 4.--7. 1. "GRID_Y,Unsigned sub-pixel offset" newline hexmask.quad.byte 0x10 0.--3. 1. "GRID_X,Unsigned sub-pixel offset" line.quad 0x18 "CORE_MMRS_RGX_CR_PPP_MULTISAMPLECTL,Sample position grid offset for use in 2x. 4x. 8xMSAA and ODAA modes." hexmask.quad.long 0x18 32.--63. 1. "RESERVED_32," newline hexmask.quad.byte 0x18 28.--31. 1. "MSAA_Y3,Unsigned sub-pixel offset for the 4th multisample Y position" newline hexmask.quad.byte 0x18 24.--27. 1. "MSAA_X3,Unsigned sub-pixel offset for the 4th multisample X position" newline hexmask.quad.byte 0x18 20.--23. 1. "MSAA_Y2,Unsigned sub-pixel offset for the 3rd multisample Y position" newline hexmask.quad.byte 0x18 16.--19. 1. "MSAA_X2,Unsigned sub-pixel offset for the 3rd multisample X position" newline hexmask.quad.byte 0x18 12.--15. 1. "MSAA_Y1,Unsigned sub-pixel offset for the 2nd multisample Y position" newline hexmask.quad.byte 0x18 8.--11. 1. "MSAA_X1,Unsigned sub-pixel offset for the 2nd multisample X position" newline hexmask.quad.byte 0x18 4.--7. 1. "MSAA_Y0,Unsigned sub-pixel offset for the 1st multisample Y position" newline hexmask.quad.byte 0x18 0.--3. 1. "MSAA_X0,Unsigned sub-pixel offset for the 1st multisample X position" line.quad 0x20 "CORE_MMRS_RGX_CR_PPP_CTRL,This register controls the global setup of the PPP." hexmask.quad 0x20 13.--63. 1. "RESERVED_13," newline bitfld.quad 0x20 12. "VPT_SCISSOR,When 0 the PPP will insert state updates on change of VPT ID When 1 this feature is disabled" "0,1" newline bitfld.quad 0x20 11. "FLUSH_MODE,when 0 PPP will supress end of draw call flushed from reaching the Clipper and TA pipeline This will break batch number funstionality but will give better primitive block utiliastion." "0,1" newline bitfld.quad 0x20 10. "BFCULL_RESTRICT_CLIP,When set clipped primitives are only back-face culled after the clipper. 0 Enable early back face cull for clipped primitives 1.." "0,1" newline bitfld.quad 0x20 9. "FIXED_POINT_FORMAT,When set the PPP will use a fixed point format of 16. 8 rather than 16.4. 0 16.4 fixed point format 1 16.8 fixed point format" "0,1" newline bitfld.quad 0x20 8. "DEFAULT_POINT_SIZE,When set the PPP will use the default point size rather than reading it from the vertex. 0 Point size read from vertex 1 Default point.." "0,1" newline bitfld.quad 0x20 7. "BFCULL1_DISABLE,Disable for fully clipped culling 0 First back face cull block enabled 1 First back face cull block disabled" "0,1" newline bitfld.quad 0x20 6. "BFCULL2_DISABLE,Disable for fully clipped culling 0 Second back face cull block enabled 1 Second back face cull block disabled" "0,1" newline bitfld.quad 0x20 5. "FCCULL_DISABLE,Disable for fully clipped culling 0 Fully clipped culling enabled 1 Fully clipped culling disabled" "0,1" newline bitfld.quad 0x20 4. "OSCULL_DISABLE,Disable for off screen culling 0 Off screen culling enabled 1 Off screen culling disabled" "0,1" newline bitfld.quad 0x20 3. "PSOCULL_DISABLE,Disable for perfect small object culling 0 Perfect small object culling enabled 1 Perfect small object culling disabled" "0,1" newline bitfld.quad 0x20 2. "SOCULL_DISABLE,Disable for small object culling 0 Small object culling enabled 1 Small object culling disabled" "0,1" newline bitfld.quad 0x20 1. "WCLAMPEN,Enable W clamping 0 W clamping disabled 1 W clamping enabled" "0,1" newline bitfld.quad 0x20 0. "OPENGL,Select OpenGL or D3D mode 0 D3D 1 OpenGL" "0,1" line.quad 0x28 "CORE_MMRS_RGX_CR_PPP_WCLAMP," hexmask.quad.long 0x28 32.--63. 1. "COMPARE_VALUE,Compare value for W clamping. See the Input parameter format viewport transform for details. Compare is applied post viewport transform. Note that this value cannot be negative." newline hexmask.quad.long 0x28 0.--31. 1. "CLAMP_VALUE,Clamp value for W clamping. See the Input parameter format viewport transform for details. Clamp is applied post viewport transform if the w value is less than the WCOMPARE value." line.quad 0x30 "CORE_MMRS_RGX_CR_PPP_SCREEN,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of pixels in X & Y axis since this may not be the same as the number of tiles defined in.." hexmask.quad 0x30 31.--63. 1. "RESERVED_31," newline hexmask.quad.word 0x30 16.--30. 1. "PIXYMAX,Screen height in pixels. [16K x 16K max screen size]" newline rbitfld.quad 0x30 15. "RESERVED_15," "0,1" newline hexmask.quad.word 0x30 0.--14. 1. "PIXXMAX,Screen width in pixels.[16K x 16K max screen size]" line.quad 0x38 "CORE_MMRS_RGX_CR_VCE_CTRL,This register controls the global setup of the VCE." hexmask.quad 0x38 5.--63. 1. "RESERVED_5," newline bitfld.quad 0x38 4. "HAZARD_CHECK_ENABLE,when set hazard checking will be enabled in SLC for parameter buffer writes" "0,1" newline bitfld.quad 0x38 3. "CACHE_BYPASS,when set VCE sets its write only cache to bypass mode effectively disabling the cache" "0,1" newline rbitfld.quad 0x38 2. "RESERVED_2," "0,1" newline bitfld.quad 0x38 1. "TWO_ORIGIN_DISABLE,When set raw mode is selected in place of 2-origin delta stream compression mode" "0,1" newline bitfld.quad 0x38 0. "COMPRESS_DISABLE,When set vertex compression is disabled. I.e. raw mode is forced for all vertices" "0,1" line.quad 0x40 "CORE_MMRS_RGX_CR_TE_CLEAR_LISTS_AFTER_ABORT,A write of '1' to this register tells the TE we are resuming after an Abort and Partial Render Sequence" hexmask.quad 0x40 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x40 0. "PULSE,TE Clears all references after Abort and Partial Render Sequence" "0,1" line.quad 0x48 "CORE_MMRS_RGX_CR_TA_RTC_ADDR,This register defines the base address in memory of the TA Render Target Caches." hexmask.quad.tbyte 0x48 40.--63. 1. "RESERVED_40," newline hexmask.quad.byte 0x48 34.--39. 1. "HEAP,1TB Addressable 16GB aligned Heap Address for TA Render Target Caches" newline hexmask.quad.long 0x48 6.--33. 1. "BASE,16GB Addressabreadonly le 512-bit aligned Base Address for TA Render Target Caches." newline hexmask.quad.byte 0x48 0.--5. 1. "RESERVED_0," line.quad 0x50 "CORE_MMRS_RGX_CR_TA_RTC_CTRL,A write of '1' to Bit 0 of this register Clears the RTC." hexmask.quad 0x50 2.--63. 1. "RESERVED_2," newline bitfld.quad 0x50 1. "STORE_PENDING,Store RTC" "0,1" newline bitfld.quad 0x50 0. "CLEAR_PENDING,Clear RTC" "0,1" line.quad 0x58 "CORE_MMRS_RGX_CR_TA_CONTEXT_STATE_BASE,The base address in external memory of the TA's context state buffer." hexmask.quad.tbyte 0x58 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x58 4.--39. 1. "ADDR,1TB range 128-bit aligned base address" newline hexmask.quad.byte 0x58 0.--3. 1. "RESERVED_0," rgroup.quad 0xCC8++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_PPP_DIAG_CULL,Diagnois register keeps a count of the number of primtives entering the PPP culling module" hexmask.quad.word 0x0 52.--63. 1. "RESERVED_52," newline hexmask.quad.long 0x0 26.--51. 1. "OP_COUNT,count of primitives exiting the cull block" newline hexmask.quad.long 0x0 0.--25. 1. "IP_COUNT,count of primitives entering the cull block" line.quad 0x8 "CORE_MMRS_RGX_CR_PPP,Checksum generated from the output of the PPP" hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "CHECKSUM,checksum generated from the output of the PPP" rgroup.quad 0xCD8++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_UVS_CLEAR,A write of '1' to this register starts the UVS Clear Operation" hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "PENDING,Start UVS Clear Operation a write to this register results in a one cycle pulse" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_TA_RTC_PRELOAD,When set. the RTC will be Preloaded with Zeros (or a nonRTA render target of 1) on a Clear Operation (used when Render Targets are not in use to remove the need for memory allocation)" hexmask.quad 0x8 2.--63. 1. "RESERVED_2," newline bitfld.quad 0x8 1. "ONE,Preload RTC with Render Target 0 set on a Clear. Used when resuming a TA phase after coarse grain context switch" "0,1" newline bitfld.quad 0x8 0. "ZEROS,Preload RTC with Zeros on a Clear" "0,1" rgroup.quad 0xCE8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_TE_STATE,This register should be Sampled by the Driver on Context Switch and Restored before the Resume of the TA Context" hexmask.quad 0x0 6.--63. 1. "RESERVED_6," newline hexmask.quad.byte 0x0 1.--5. 1. "ISP_STATE_ID,ISP State ID" newline bitfld.quad 0x0 0. "ABORTED,TA had been aborted in the past" "0,1" rgroup.quad 0xCF0++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_VCE_HALT,The MicroKernel must halt VCE processing (consumption of it's pages allocated by PM) before we can do a Partial Render in the Rogue Architecture." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "PENDING,VCE is Halting after Current Block" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_TE_RESUME_AFTER_ABORT,A write of '1' to this register tells the TE we are resuming after an Abort but that no Partial Render took place" hexmask.quad 0x8 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x8 0. "PULSE,TE is restarted and reattempts failing allocation after Out Of Memory event only" "0,1" rgroup.quad 0xD00++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_TA_IDLE," hexmask.quad 0x0 6.--63. 1. "RESERVED_6," newline bitfld.quad 0x0 5. "TE,TE Module IDLE" "0,1" newline bitfld.quad 0x0 4. "VCE,VCE Module IDLE" "0,1" newline bitfld.quad 0x0 3. "VBG,VBG Module IDLE" "0,1" newline bitfld.quad 0x0 2. "CLIP,CLIP Module IDLE" "0,1" newline bitfld.quad 0x0 1. "PPP,PPP Module IDLE" "0,1" newline bitfld.quad 0x0 0. "UVS,UVS Module IDLE" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_STAT_NEW_PRIM," hexmask.quad.long 0x8 32.--63. 1. "TE,Number of primitives into TE" newline hexmask.quad.long 0x8 0.--31. 1. "PPP,Number of primitives into PPP" line.quad 0x10 "CORE_MMRS_RGX_CR_STAT_NEW," hexmask.quad.long 0x10 32.--63. 1. "OBJECT_TE,Number of Control Stream Updates by TE" newline hexmask.quad.long 0x10 0.--31. 1. "VERTEX,Number of vertices" rgroup.quad 0xD20++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_TE_PSG_RTC,This register should be Sampled by the Driver on VDM Context Switch Terminate TA FINISHED event and Restored before the Resume of the TA Context" hexmask.quad 0x0 12.--63. 1. "RESERVED_12," newline hexmask.quad.word 0x0 0.--11. 1. "ACTIVE_RTS,RTAs active at the point of the VDM Context SWitch" line.quad 0x8 "CORE_MMRS_RGX_CR_VCE_CACHE_FLUSH,The MicroKernel can use this to flush the VCE write only cache at the end of TA phase render." hexmask.quad 0x8 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x8 0. "PENDING,VCE is Flushing its write only cache to memory" "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_TE_CACHE_FLUSH,The MicroKernel can use this to flush the TE write only cache at the end of TA phase render." hexmask.quad 0x10 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x10 0. "PENDING,TE is Flushing its write only cache to memory" "0,1" line.quad 0x18 "CORE_MMRS_RGX_CR_PM_CACHE_FLUSH,The MicroKernel can use this to flush the PM write only cache at the end of TA phase render." hexmask.quad 0x18 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x18 0. "PENDING,PM is Flushing its write only cache to memory" "0,1" rgroup.quad 0xF00++0x8F line.quad 0x0 "CORE_MMRS_RGX_CR_ISP_START_RENDER,Writing '1' to this register initiates a 3D render" hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "PULSE," "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_ISP_RENDER,Controls the render" hexmask.quad 0x8 9.--63. 1. "RESERVED_9," newline bitfld.quad 0x8 8. "FAST_RENDER_FORCE_PROTECT,When set all tiles to be rasterised are marked as protected" "0,1" newline bitfld.quad 0x8 7. "PROCESS_PROTECTED_TILES,When set protected tiles are processed" "0,1" newline bitfld.quad 0x8 6. "PROCESS_UNPROTECTED_TILES,When set unprotected tiles are processed" "0,1" newline bitfld.quad 0x8 5. "DISABLE_EOMT,Prevent End-of-Macro-Tile flags being sent to ISP" "0,1" newline bitfld.quad 0x8 4. "RESUME,Render resume" "0,1" newline bitfld.quad 0x8 2.--3. "DIR,Render direction" "0,1,2,3" newline bitfld.quad 0x8 0.--1. "MODE,Render type" "0,1,2,3" line.quad 0x10 "CORE_MMRS_RGX_CR_ISP_RENDER_ORIGIN,This register defines the top-left tile coordinate for the render." hexmask.quad 0x10 26.--63. 1. "RESERVED_26," newline hexmask.quad.word 0x10 16.--25. 1. "X,X coordinate in tiles" newline hexmask.quad.byte 0x10 10.--15. 1. "RESERVED_10," newline hexmask.quad.word 0x10 0.--9. 1. "Y,Y coordinate in tiles" line.quad 0x18 "CORE_MMRS_RGX_CR_ISP_MTILE_SIZE," hexmask.quad 0x18 26.--63. 1. "RESERVED_26," newline hexmask.quad.word 0x18 16.--25. 1. "X,Macrotile width in tiles. A value of zero corresponds to the maximum size" newline hexmask.quad.byte 0x18 10.--15. 1. "RESERVED_10," newline hexmask.quad.word 0x18 0.--9. 1. "Y,Macrotile height in tiles. A value of zero corresponds to the maximum size" line.quad 0x20 "CORE_MMRS_RGX_CR_ISP_MTILE_BASE," hexmask.quad.tbyte 0x20 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x20 2.--39. 1. "ADDR,1TB range 32-bit aligned base address" newline rbitfld.quad 0x20 0.--1. "RESERVED_0," "0,1,2,3" line.quad 0x28 "CORE_MMRS_RGX_CR_ISP_RGN,This register defines the sizes of the allocations of the simple internal parameter data." hexmask.quad 0x28 29.--63. 1. "RESERVED_29," newline hexmask.quad.byte 0x28 24.--28. 1. "CS_SIZE,Number of primitive headers in the control stream for a fast 2D render. If the number of primitive headers exceeds the maximum field size or the size of the control stream is unknown a.." newline hexmask.quad.tbyte 0x28 0.--23. 1. "SIZE,Number of Region Headers to fetch" line.quad 0x30 "CORE_MMRS_RGX_CR_ISP_AA,Controls whether anti-aliasing is enabled or disabled" hexmask.quad 0x30 2.--63. 1. "RESERVED_2," newline bitfld.quad 0x30 0.--1. "MODE," "0,1,2,3" line.quad 0x38 "CORE_MMRS_RGX_CR_ISP_CTL,ISP control register." hexmask.quad.long 0x38 32.--63. 1. "RESERVED_32," newline bitfld.quad 0x38 31. "SKIP_INIT_HDRS,Used to enable skipping of initial region headers based on gpu offset '0': reads all region headers and discards the ones not needed. '1': skip reading of.." "0,1" newline rbitfld.quad 0x38 29.--30. "RESERVED_29," "0,1,2,3" newline bitfld.quad 0x38 28. "PAIR_TILES_VERT,If set causes IPF to pair tiles vertically within its pipeline." "0,1" newline bitfld.quad 0x38 27. "PAIR_TILES,If set causes IPF to pair tiles within its pipeline." "0,1" newline hexmask.quad.byte 0x38 21.--26. 1. "RESERVED_21," newline bitfld.quad 0x38 20. "DBIAS_IS_INT,When set depth bias value is a signed integer" "0,1" newline bitfld.quad 0x38 19. "OVERLAP_CHECK_MODE,0 - different samples for the same pixel will be sent to different pass groups for translucent objects [pixel to pixel overlap test] 1 - different samples for the same pixel will be sent as the same pass.." "0: different samples for the same pixel will be..,?" newline bitfld.quad 0x38 18. "PT_UPFRONT_DEPTH_DISABLE,When set disable UPFRONT depth test in the Depthsorter" "0,1" newline bitfld.quad 0x38 17. "PROCESS_EMPTY_TILES,When set empty tiles are always processed rather than being suppressed" "0,1" newline bitfld.quad 0x38 16. "SAMPLE_POS,Specifies the sampling rule to be used when calculating the endpoint adjustment for thin lines" "0,1" newline hexmask.quad.byte 0x38 12.--15. 1. "PIPE_ENABLE,Tiles-in-flight" newline rbitfld.quad 0x38 10.--11. "RESERVED_10," "0,1,2,3" newline hexmask.quad.byte 0x38 4.--9. 1. "VALID_ID,Triangle validation value" newline hexmask.quad.byte 0x38 0.--3. 1. "UPASS_START,User pass start value" line.quad 0x40 "CORE_MMRS_RGX_CR_ISP_SPLIT_RENDER," hexmask.quad.long 0x40 33.--63. 1. "RESERVED_33," newline bitfld.quad 0x40 32. "ENABLE," "0,1" newline rbitfld.quad 0x40 30.--31. "RESERVED_30," "0,1,2,3" newline hexmask.quad.word 0x40 16.--29. 1. "MAX,Render up to and including this value" newline rbitfld.quad 0x40 14.--15. "RESERVED_14," "0,1,2,3" newline hexmask.quad.word 0x40 0.--13. 1. "MIN,Render up from and including this value" line.quad 0x48 "CORE_MMRS_RGX_CR_ISP_ZLSCTL,ISP Z Load/Store & format global control register" hexmask.quad.byte 0x48 58.--63. 1. "RESERVED_58," newline hexmask.quad.word 0x48 48.--57. 1. "ZLSEXTENT_Y_S,For stencil buffer the value calculation is the same as ZLSEXTENT_Y_Z" newline hexmask.quad.word 0x48 38.--47. 1. "ZLSEXTENT_X_S,For stencil buffer the value calculation is the same as ZLSEXTENT_X_Z" newline bitfld.quad 0x48 37. "STENCIL_EXTENT_ENABLE,When this bit is '1' stencil buffer will use zlsextent_x/y_s value to calculate zload/store address otherwise zlsextent_x/y_z value will be used." "0,1" newline hexmask.quad.word 0x48 27.--36. 1. "ZLSEXTENT_Y_Z,For Depth buffer Display width of Y in tiles minus one: 0x000 1 tile 0x001 2 tiles .. 0x2FF 1024 tiles zlsextent_y = total_samples_y / 32.." newline bitfld.quad 0x48 25.--26. "ZSTOREFORMAT," "0,1,2,3" newline bitfld.quad 0x48 23.--24. "ZLOADFORMAT," "0,1,2,3" newline bitfld.quad 0x48 22. "FB_STOREEN,when set frame buffer compression store is enabled" "0,1" newline bitfld.quad 0x48 21. "FB_LOADEN,when set frame buffer decompression load is enabled" "0,1" newline bitfld.quad 0x48 20. "MSTOREEN,When set and ZSTOREFORMAT = 0x0 mask plane is stored within msb of IEEE format when set and ZSTOREFORMAT = 0x3 mask plane is stored at bit position 31 of IEEE format .." "0,1" newline bitfld.quad 0x48 19. "ZSTOREEN,When set to 1 if the ZSTORE bit in the region header is also set then the depth buffer is stored to memory after each tile is processed" "0,1" newline bitfld.quad 0x48 18. "SSTOREEN,When set to 1 if the ZSTORE bit in the region header is also set then the stencil buffer is stored to memory after each tile is processed" "0,1" newline bitfld.quad 0x48 17. "STORETWIDDLED,When set to 1 depth and stencil data is written out in Twiddled order." "0,1" newline bitfld.quad 0x48 16. "MLOADEN,When set and ZLOADFORMAT = 0x0 mask plane is loaded from msb of IEEE format when set and ZLOADFORMAT = 0x3 mask plane is loaded from the bit position 31 of IEEE format .." "0,1" newline bitfld.quad 0x48 15. "ZLOADEN,When set to 1 if the ZLOAD bit in the region header is also set then the depth buffer is read from memory prior to tile processing" "0,1" newline bitfld.quad 0x48 14. "SLOADEN,When set to 1 if the ZLOAD bit in the region header is also set then the stencil buffer is read from memory prior to tile processing" "0,1" newline bitfld.quad 0x48 13. "LOADTWIDDLED,When set to 1 depth stencil data is loaded in Twiddled order" "0,1" newline hexmask.quad.word 0x48 3.--12. 1. "ZLSEXTENT_X_Z,For depth buffer Display width of X in tiles minus one: 0x000 1 tile 0x001 2 tiles .. 0x2FF 1024 tiles. For different msaa mode .." newline bitfld.quad 0x48 2. "FORCEZSTORE,If set to 1 the depth/stencil buffer is always stored at the end of each tile irrespective of the region header ZSTORE bit." "0,1" newline bitfld.quad 0x48 1. "FORCEZLOAD,If set to 1 the depth/stencil buffer is always loaded at the start of each tile irrespective of the region header ZLOAD bit." "0,1" newline bitfld.quad 0x48 0. "ZONLYRENDER,When set only the Z buffer is rendered. Opaque and translucent objects are stencil and depth tested as usual but no pixel spans are emitted to the PDS Pixel presenter. Pixels within punch through and depth.." "0,1" line.quad 0x50 "CORE_MMRS_RGX_CR_ISP_ZLOAD_BASE,Base address in memory of the Z Buffer base address to load into the ISP for non-compressed ZLS formats." hexmask.quad.tbyte 0x50 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x50 4.--39. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline hexmask.quad.byte 0x50 0.--3. 1. "RESERVED_0," line.quad 0x58 "CORE_MMRS_RGX_CR_ISP_ZSTORE_BASE,Base address in memory of the Z Buffer base address to store into the ISP for non-compressed ZLS formats." hexmask.quad.tbyte 0x58 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x58 4.--39. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Store base address" newline hexmask.quad.byte 0x58 0.--3. 1. "RESERVED_0," line.quad 0x60 "CORE_MMRS_RGX_CR_ISP_STENCIL_LOAD_BASE,Base address in memory of the Stencil Buffer base address to load into the ISP for non-compressed ZLS formats." hexmask.quad.tbyte 0x60 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x60 4.--39. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline rbitfld.quad 0x60 1.--3. "RESERVED_1," "0,1,2,3,4,5,6,7" newline bitfld.quad 0x60 0. "ENABLE,When set to 1 enables fetching of stencil from a separate base address" "0,1" line.quad 0x68 "CORE_MMRS_RGX_CR_ISP_STENCIL_STORE_BASE,Base address in memory of the Stencil Buffer base address to store into the ISP for non-compressed ZLS formats." hexmask.quad.tbyte 0x68 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x68 4.--39. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline rbitfld.quad 0x68 1.--3. "RESERVED_1," "0,1,2,3,4,5,6,7" newline bitfld.quad 0x68 0. "ENABLE,When set to 1 enables fetching of stencil from a separate base address" "0,1" line.quad 0x70 "CORE_MMRS_RGX_CR_ISP_MASK_LOAD_BASE,Base address in memory of the Mask Buffer base address to load into the ISP for non-compressed ZLS formats." hexmask.quad.tbyte 0x70 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x70 4.--39. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline rbitfld.quad 0x70 1.--3. "RESERVED_1," "0,1,2,3,4,5,6,7" newline bitfld.quad 0x70 0. "ENABLE,When set to 1 enables fetching of mask from a separate base address" "0,1" line.quad 0x78 "CORE_MMRS_RGX_CR_ISP_MASK_STORE_BASE,Base address in memory of the Mask Buffer base address to store into the ISP for non-compressed ZLS formats." hexmask.quad.tbyte 0x78 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x78 4.--39. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline rbitfld.quad 0x78 1.--3. "RESERVED_1," "0,1,2,3,4,5,6,7" newline bitfld.quad 0x78 0. "ENABLE,When set to 1 enables fetching of mask from a separate base address" "0,1" line.quad 0x80 "CORE_MMRS_RGX_CR_ISP_BGOBJDEPTH,The ISP operates by comparing depth values of incoming objects with the results of previous depth compares." hexmask.quad.long 0x80 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x80 0.--31. 1. "VALUE,Note the format in this register has to be consistent with the format defined by ZLS_STORE_FORMAT register. If depth buffer is F32 then the value here should be IEEE 754 single precisoin.." line.quad 0x88 "CORE_MMRS_RGX_CR_ISP_BGOBJVALS,This register provides enable. mask and stencil information for the hardware background object." hexmask.quad 0x88 10.--63. 1. "RESERVED_10," newline bitfld.quad 0x88 9. "ENABLEBGTAG,When set to 1 at the start of each tile the ISP tag buffer is initialised with the background object tag [default = 1]" "0,1" newline bitfld.quad 0x88 8. "MASK,Hardware background object mask plane" "0,1" newline hexmask.quad.byte 0x88 0.--7. 1. "STENCIL,Hardware background object stencil" rgroup.quad 0xFA0++0x3F line.quad 0x0 "CORE_MMRS_RGX_CR_ISP_GRIDOFFSET,Sample position grid offset for use when MSAA/ODAA is DISABLED" hexmask.quad 0x0 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x0 4.--7. 1. "GRID_Y,Unsigned sub-pixel offset" newline hexmask.quad.byte 0x0 0.--3. 1. "GRID_X,Unsigned sub-pixel offset" line.quad 0x8 "CORE_MMRS_RGX_CR_ISP_MULTISAMPLECTL,Sample position grid offset for use in 2x. 4x. 8xMSAA and ODAA modes." hexmask.quad.byte 0x8 60.--63. 1. "MSAA_Y7,Unsigned sub-pixel offset for the 8th multisample Y position" newline hexmask.quad.byte 0x8 56.--59. 1. "MSAA_X7,Unsigned sub-pixel offset for the 8th multisample X position" newline hexmask.quad.byte 0x8 52.--55. 1. "MSAA_Y6,Unsigned sub-pixel offset for the 7th multisample Y position" newline hexmask.quad.byte 0x8 48.--51. 1. "MSAA_X6,Unsigned sub-pixel offset for the 7th multisample X position" newline hexmask.quad.byte 0x8 44.--47. 1. "MSAA_Y5,Unsigned sub-pixel offset for the 6th multisample Y position" newline hexmask.quad.byte 0x8 40.--43. 1. "MSAA_X5,Unsigned sub-pixel offset for the 6th multisample X position" newline hexmask.quad.byte 0x8 36.--39. 1. "MSAA_Y4,Unsigned sub-pixel offset for the 5th multisample Y position" newline hexmask.quad.byte 0x8 32.--35. 1. "MSAA_X4,Unsigned sub-pixel offset for the 5th multisample X position" newline hexmask.quad.byte 0x8 28.--31. 1. "MSAA_Y3,Unsigned sub-pixel offset for the 4th multisample Y position" newline hexmask.quad.byte 0x8 24.--27. 1. "MSAA_X3,Unsigned sub-pixel offset for the 4th multisample X position" newline hexmask.quad.byte 0x8 20.--23. 1. "MSAA_Y2,Unsigned sub-pixel offset for the 3rd multisample Y position" newline hexmask.quad.byte 0x8 16.--19. 1. "MSAA_X2,Unsigned sub-pixel offset for the 3rd multisample X position" newline hexmask.quad.byte 0x8 12.--15. 1. "MSAA_Y1,Unsigned sub-pixel offset for the 2nd multisample Y position" newline hexmask.quad.byte 0x8 8.--11. 1. "MSAA_X1,Unsigned sub-pixel offset for the 2nd multisample X position" newline hexmask.quad.byte 0x8 4.--7. 1. "MSAA_Y0,Unsigned sub-pixel offset for the 1st multisample Y position" newline hexmask.quad.byte 0x8 0.--3. 1. "MSAA_X0,Unsigned sub-pixel offset for the 1st multisample X position" line.quad 0x10 "CORE_MMRS_RGX_CR_ISP_SCISSOR_BASE," hexmask.quad.tbyte 0x10 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x10 2.--39. 1. "ADDR,1TB range 32-bit aligned base address" newline rbitfld.quad 0x10 0.--1. "RESERVED_0," "0,1,2,3" line.quad 0x18 "CORE_MMRS_RGX_CR_ISP_DBIAS_BASE," hexmask.quad.tbyte 0x18 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x18 2.--39. 1. "ADDR,1TB range 32-bit aligned base address" newline rbitfld.quad 0x18 0.--1. "RESERVED_0," "0,1,2,3" line.quad 0x20 "CORE_MMRS_RGX_CR_ISP_OCLQRY_BASE,Base address for occlusion query counter values." hexmask.quad.tbyte 0x20 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x20 4.--39. 1. "ADDR,1TB range 128-bit aligned base address" newline hexmask.quad.byte 0x20 0.--3. 1. "RESERVED_0," line.quad 0x28 "CORE_MMRS_RGX_CR_ISP_PIXEL_BASE,Base address for control stream and primitive blocks." hexmask.quad.tbyte 0x28 40.--63. 1. "RESERVED_40," newline hexmask.quad.byte 0x28 34.--39. 1. "ADDR,1TB range 16GB granularity" newline hexmask.quad 0x28 0.--33. 1. "RESERVED_0," line.quad 0x30 "CORE_MMRS_RGX_CR_ISP_ZLS_PIXELS,screen size in pixel numbers for ZLS." hexmask.quad 0x30 30.--63. 1. "RESERVED_30," newline hexmask.quad.word 0x30 15.--29. 1. "Y,Display width of Y in pixels minus one. 0x000 1 pixel 0x001 2 pixels ... 0x7FFF 1024*32 pixels. Subtile only supports for non-msaa mode depth load/store .." newline hexmask.quad.word 0x30 0.--14. 1. "X,Display width of X in pixels minus one. 0x000 1 pixel 0x001 2 pixels ... 0x7FFF 1024*32 pixels. Subtile only supports for non-msaa mode depth load/store .." line.quad 0x38 "CORE_MMRS_RGX_CR_ISP_CTL2," hexmask.quad 0x38 5.--63. 1. "RESERVED_5," newline hexmask.quad.byte 0x38 0.--4. 1. "DEPTHBUFFERS_IN_USE,Specifies the number of depth buffers to use" rgroup.quad 0x1000++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_ISP_START_CONTEXT_STORE,Writing '1' to this register initiates a 3D context store" hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "PULSE," "0,1" rgroup.quad 0x1008++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_ISP_STORE0,ISP context store register" hexmask.quad 0x0 31.--63. 1. "RESERVED_31," newline bitfld.quad 0x0 30. "ACTIVE," "0,1" newline bitfld.quad 0x0 29. "EOR," "0,1" newline bitfld.quad 0x0 28. "TILE_LAST," "0,1" newline hexmask.quad.byte 0x0 24.--27. 1. "MT," newline bitfld.quad 0x0 22.--23. "RESERVED_22," "0,1,2,3" newline hexmask.quad.word 0x0 12.--21. 1. "TILE_X," newline bitfld.quad 0x0 10.--11. "RESERVED_10," "0,1,2,3" newline hexmask.quad.word 0x0 0.--9. 1. "TILE_Y," rgroup.quad 0x1020++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_ISP_RESUME0,ISP context resume register" hexmask.quad 0x0 22.--63. 1. "RESERVED_22," newline hexmask.quad.word 0x0 12.--21. 1. "TILE_X," newline rbitfld.quad 0x0 10.--11. "RESERVED_10," "0,1,2,3" newline hexmask.quad.word 0x0 0.--9. 1. "TILE_Y," rgroup.quad 0x1038++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_ISP_STATUS,ISP status registers" hexmask.quad 0x0 3.--63. 1. "RESERVED_3," newline bitfld.quad 0x0 2. "SPLIT_MAX,Split Render Maximum Threshold has been Exceeded" "0,1" newline bitfld.quad 0x0 1. "ACTIVE,ISP is Active first tile in the render has been assigned" "0,1" newline bitfld.quad 0x0 0. "EOR,ISP has assigned the last tile in the render" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_RAST_IDLE," hexmask.quad 0x8 5.--63. 1. "RESERVED_5," newline bitfld.quad 0x8 4. "TFPU,TFPU Module IDLE" "0,1" newline bitfld.quad 0x8 3. "TPF,TPF Module IDLE" "0,1" newline bitfld.quad 0x8 2. "IFPU,IFPU Module IDLE" "0,1" newline bitfld.quad 0x8 1. "ISP,ISP Module IDLE" "0,1" newline bitfld.quad 0x8 0. "IPF,IPF Module IDLE" "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_ISP_PWR_NUM," hexmask.quad.long 0x10 32.--63. 1. "VERTICES_PROCESS,Number of vertices processed" newline hexmask.quad.long 0x10 0.--31. 1. "PIXELS_PROCESS,Number of depth tested pixels[non-MSAA] or samples[MSAA] processed" rgroup.quad 0x1058++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_TFPU_PWR_NUM," hexmask.quad.long 0x0 32.--63. 1. "LAYERS_PROCESSED,Number of layers processed" newline hexmask.quad.long 0x0 0.--31. 1. "PRIMITIVES_PROCESSED,Number of primitives processed" rgroup.quad 0x11D0++0x87 line.quad 0x0 "CORE_MMRS_RGX_CR_ISP_MERGE_LOWER_X,Used by the IFPU to generate the angle vectors used for triangle merging" hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "VALUE,tan[15]/16k screen size" line.quad 0x8 "CORE_MMRS_RGX_CR_ISP_MERGE_LOWER_Y,Used by the IFPU to generate the angle vectors used for triangle merging" hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "VALUE,tan[15]/16k screen size" line.quad 0x10 "CORE_MMRS_RGX_CR_ISP_MERGE_UPPER_X," hexmask.quad.long 0x10 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x10 0.--31. 1. "VALUE,tan[60]/16k screen size" line.quad 0x18 "CORE_MMRS_RGX_CR_ISP_MERGE_UPPER_Y,Used by the IFPU to generate the angle vectors used for triangle merging" hexmask.quad.long 0x18 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x18 0.--31. 1. "VALUE,tan[60]/16k screen size" line.quad 0x20 "CORE_MMRS_RGX_CR_ISP_MERGE_SCALE_X," hexmask.quad.long 0x20 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x20 0.--31. 1. "VALUE,16 * default screen size of 16k" line.quad 0x28 "CORE_MMRS_RGX_CR_ISP_MERGE_SCALE_Y,Used by the IFPU to generate the angle vectors used for triangle merging" hexmask.quad.long 0x28 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x28 0.--31. 1. "VALUE,16 * default screen size of 16k" line.quad 0x30 "CORE_MMRS_RGX_CR_BIF_CAT_BASE0," hexmask.quad.tbyte 0x30 40.--63. 1. "RESERVED_40," newline hexmask.quad.long 0x30 12.--39. 1. "ADDR," newline hexmask.quad.word 0x30 0.--11. 1. "RESERVED_0," line.quad 0x38 "CORE_MMRS_RGX_CR_BIF_CAT_BASE1," hexmask.quad.tbyte 0x38 40.--63. 1. "RESERVED_40," newline hexmask.quad.long 0x38 12.--39. 1. "ADDR," newline hexmask.quad.word 0x38 0.--11. 1. "RESERVED_0," line.quad 0x40 "CORE_MMRS_RGX_CR_BIF_CAT_BASE2," hexmask.quad.tbyte 0x40 40.--63. 1. "RESERVED_40," newline hexmask.quad.long 0x40 12.--39. 1. "ADDR," newline hexmask.quad.word 0x40 0.--11. 1. "RESERVED_0," line.quad 0x48 "CORE_MMRS_RGX_CR_BIF_CAT_BASE3," hexmask.quad.tbyte 0x48 40.--63. 1. "RESERVED_40," newline hexmask.quad.long 0x48 12.--39. 1. "ADDR," newline hexmask.quad.word 0x48 0.--11. 1. "RESERVED_0," line.quad 0x50 "CORE_MMRS_RGX_CR_BIF_CAT_BASE4," hexmask.quad.tbyte 0x50 40.--63. 1. "RESERVED_40," newline hexmask.quad.long 0x50 12.--39. 1. "ADDR," newline hexmask.quad.word 0x50 0.--11. 1. "RESERVED_0," line.quad 0x58 "CORE_MMRS_RGX_CR_BIF_CAT_BASE5," hexmask.quad.tbyte 0x58 40.--63. 1. "RESERVED_40," newline hexmask.quad.long 0x58 12.--39. 1. "ADDR," newline hexmask.quad.word 0x58 0.--11. 1. "RESERVED_0," line.quad 0x60 "CORE_MMRS_RGX_CR_BIF_CAT_BASE6," hexmask.quad.tbyte 0x60 40.--63. 1. "RESERVED_40," newline hexmask.quad.long 0x60 12.--39. 1. "ADDR," newline hexmask.quad.word 0x60 0.--11. 1. "RESERVED_0," line.quad 0x68 "CORE_MMRS_RGX_CR_BIF_CAT_BASE7," hexmask.quad.tbyte 0x68 40.--63. 1. "RESERVED_40," newline hexmask.quad.long 0x68 12.--39. 1. "ADDR," newline hexmask.quad.word 0x68 0.--11. 1. "RESERVED_0," line.quad 0x70 "CORE_MMRS_RGX_CR_BIF_CAT_BASE_INDEX,Index registers per data master. Byte aligned fields to allow byte-masked access" hexmask.quad.long 0x70 35.--63. 1. "RESERVED_35," newline bitfld.quad 0x70 32.--34. "HOST,Catalogue Base number for HOST data master" "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x70 19.--31. 1. "RESERVED_19," newline bitfld.quad 0x70 16.--18. "CDM,Catalogue Base number for CDM data master" "0,1,2,3,4,5,6,7" newline hexmask.quad.byte 0x70 11.--15. 1. "RESERVED_11," newline bitfld.quad 0x70 8.--10. "PIXEL,Catalogue Base number for PIXEL data master" "0,1,2,3,4,5,6,7" newline hexmask.quad.byte 0x70 3.--7. 1. "RESERVED_3," newline bitfld.quad 0x70 0.--2. "TA,Catalogue Base number for TA data master" "0,1,2,3,4,5,6,7" line.quad 0x78 "CORE_MMRS_RGX_CR_BIF_PM_CAT_BASE_VCE0,PM catalogue base address for VCE context 0" hexmask.quad.byte 0x78 60.--63. 1. "RESERVED_60," newline hexmask.quad.tbyte 0x78 40.--59. 1. "INIT_PAGE," newline hexmask.quad.byte 0x78 36.--39. 1. "RESERVED_36," newline hexmask.quad.tbyte 0x78 12.--35. 1. "ADDR," newline hexmask.quad.word 0x78 2.--11. 1. "RESERVED_2," newline bitfld.quad 0x78 1. "WRAP,Indicates address space has been fully allocated" "0,1" newline bitfld.quad 0x78 0. "VALID," "0,1" line.quad 0x80 "CORE_MMRS_RGX_CR_BIF_PM_CAT_BASE_TE0,PM catalogue base address for TE context 0" hexmask.quad.byte 0x80 60.--63. 1. "RESERVED_60," newline hexmask.quad.tbyte 0x80 40.--59. 1. "INIT_PAGE," newline hexmask.quad.byte 0x80 36.--39. 1. "RESERVED_36," newline hexmask.quad.tbyte 0x80 12.--35. 1. "ADDR," newline hexmask.quad.word 0x80 2.--11. 1. "RESERVED_2," newline bitfld.quad 0x80 1. "WRAP," "0,1" newline bitfld.quad 0x80 0. "VALID," "0,1" rgroup.quad 0x1260++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_BIF_PM_CAT_BASE_ALIST0,PM catalogue base address for ALIST context 0" hexmask.quad.byte 0x0 60.--63. 1. "RESERVED_60," newline hexmask.quad.tbyte 0x0 40.--59. 1. "INIT_PAGE," newline hexmask.quad.byte 0x0 36.--39. 1. "RESERVED_36," newline hexmask.quad.tbyte 0x0 12.--35. 1. "ADDR," newline hexmask.quad.word 0x0 2.--11. 1. "RESERVED_2," newline bitfld.quad 0x0 1. "WRAP," "0,1" newline bitfld.quad 0x0 0. "VALID," "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_BIF_PM_CAT_BASE_VCE1,PM catalogue base address for VCE context 1" hexmask.quad.byte 0x8 60.--63. 1. "RESERVED_60," newline hexmask.quad.tbyte 0x8 40.--59. 1. "INIT_PAGE," newline hexmask.quad.byte 0x8 36.--39. 1. "RESERVED_36," newline hexmask.quad.tbyte 0x8 12.--35. 1. "ADDR," newline hexmask.quad.word 0x8 2.--11. 1. "RESERVED_2," newline bitfld.quad 0x8 1. "WRAP," "0,1" newline bitfld.quad 0x8 0. "VALID," "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_BIF_PM_CAT_BASE_TE1,PM catalogue base address for TE context 1" hexmask.quad.byte 0x10 60.--63. 1. "RESERVED_60," newline hexmask.quad.tbyte 0x10 40.--59. 1. "INIT_PAGE," newline hexmask.quad.byte 0x10 36.--39. 1. "RESERVED_36," newline hexmask.quad.tbyte 0x10 12.--35. 1. "ADDR," newline hexmask.quad.word 0x10 2.--11. 1. "RESERVED_2," newline bitfld.quad 0x10 1. "WRAP," "0,1" newline bitfld.quad 0x10 0. "VALID," "0,1" rgroup.quad 0x1280++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_BIF_PM_CAT_BASE_ALIST1,PM catalogue base address for ALIST context 1" hexmask.quad.byte 0x0 60.--63. 1. "RESERVED_60," newline hexmask.quad.tbyte 0x0 40.--59. 1. "INIT_PAGE," newline hexmask.quad.byte 0x0 36.--39. 1. "RESERVED_36," newline hexmask.quad.tbyte 0x0 12.--35. 1. "ADDR," newline hexmask.quad.word 0x0 2.--11. 1. "RESERVED_2," newline bitfld.quad 0x0 1. "WRAP," "0,1" newline bitfld.quad 0x0 0. "VALID," "0,1" rgroup.quad 0x12A0++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_BIF_CTRL_INVAL,Invalidation bits allowing BIF/MMU to clear when invalidation complete" hexmask.quad 0x0 4.--63. 1. "RESERVED_4," newline bitfld.quad 0x0 3. "TLB1," "0,1" newline bitfld.quad 0x0 2. "PC," "0,1" newline bitfld.quad 0x0 1. "PD," "0,1" newline bitfld.quad 0x0 0. "PT," "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_BIF_CTRL,Miscellaneous controls" hexmask.quad 0x8 10.--63. 1. "RESERVED_10," newline bitfld.quad 0x8 9. "PAUSE_MMU_CPU,Stalls input to CPU MMU" "0,1" newline hexmask.quad.byte 0x8 4.--8. 1. "RESERVED_4," newline bitfld.quad 0x8 3. "PAUSE_BIF1,Stalls BIF1 pipeline" "0,1" newline bitfld.quad 0x8 2. "PAUSE_MMU_PM,Stalls PM input to MMU" "0,1" newline rbitfld.quad 0x8 1. "RESERVED_1," "0,1" newline bitfld.quad 0x8 0. "PAUSE_MMU_BIF0,Stalls BIF0 input to MMU" "0,1" rgroup.quad 0x12B0++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_BIF_FAULT_BANK0_MMU_STATUS,Indicates a fault has occurred on bank 0 and provides details of fault" hexmask.quad 0x0 16.--63. 1. "RESERVED_16," newline hexmask.quad.byte 0x0 12.--15. 1. "CAT_BASE,Catalogue base address number" newline bitfld.quad 0x0 11. "RESERVED_11," "0,1" newline bitfld.quad 0x0 8.--10. "PAGE_SIZE,Page size" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x0 7. "RESERVED_7," "0,1" newline bitfld.quad 0x0 5.--6. "DATA_TYPE,MMU data type that was invalid [on valid fault]" "0,1,2,3" newline bitfld.quad 0x0 4. "FAULT_RO,Indicates read-only fault['1'] or valid fault['0']" "0,1" newline bitfld.quad 0x0 3. "RESERVED_3," "0,1" newline bitfld.quad 0x0 2. "FAULT_PM_META_RO,Indicates pm/meta protected region fault" "0,1" newline bitfld.quad 0x0 1. "RESERVED_1," "0,1" newline bitfld.quad 0x0 0. "FAULT,Indicates a fault has occured" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_BIF_FAULT_BANK0_REQ_STATUS,Provides details of the request that faulted on bank 0" hexmask.quad.word 0x8 53.--63. 1. "RESERVED_53," newline bitfld.quad 0x8 52. "RNW," "0,1" newline hexmask.quad.byte 0x8 46.--51. 1. "TAG_SB," newline hexmask.quad.byte 0x8 40.--45. 1. "TAG_ID," newline hexmask.quad 0x8 4.--39. 1. "ADDRESS," newline hexmask.quad.byte 0x8 0.--3. 1. "RESERVED_0," rgroup.quad 0x12D0++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_BIF_MMU_STATUS,General MMU status" hexmask.quad 0x0 29.--63. 1. "RESERVED_29," newline bitfld.quad 0x0 28. "PM_FAULT," "0,1" newline hexmask.quad.byte 0x0 20.--27. 1. "PC_DATA," newline hexmask.quad.byte 0x0 12.--19. 1. "PD_DATA," newline hexmask.quad.byte 0x0 4.--11. 1. "PT_DATA," newline bitfld.quad 0x0 3. "RESERVED_3," "0,1" newline bitfld.quad 0x0 2. "STALLED," "0,1" newline bitfld.quad 0x0 1. "PAUSED," "0,1" newline bitfld.quad 0x0 0. "BUSY," "0,1" rgroup.quad 0x1320++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_BIF_READS_EXT_STATUS,Outstanding read data external to BIF for BIF128 and MMU" hexmask.quad 0x0 28.--63. 1. "RESERVED_28," newline hexmask.quad.word 0x0 16.--27. 1. "MMU," newline hexmask.quad.word 0x0 0.--15. 1. "BANK1," line.quad 0x8 "CORE_MMRS_RGX_CR_BIF_READS_INT_STATUS,Outstanding 256-bit read data in return data FIFO for BIF128 and MMU" hexmask.quad 0x8 27.--63. 1. "RESERVED_27," newline hexmask.quad.word 0x8 16.--26. 1. "MMU," newline hexmask.quad.word 0x8 0.--15. 1. "BANK1," line.quad 0x10 "CORE_MMRS_RGX_CR_BIFPM_READS_INT_STATUS,Outstanding 256-bit read data in return data FIFO for BIF256" hexmask.quad 0x10 16.--63. 1. "RESERVED_16," newline hexmask.quad.word 0x10 0.--15. 1. "BANK0," line.quad 0x18 "CORE_MMRS_RGX_CR_BIFPM_READS_EXT_STATUS,Outstanding 256-bit read data external to BIF for BIF256" hexmask.quad 0x18 16.--63. 1. "RESERVED_16," newline hexmask.quad.word 0x18 0.--15. 1. "BANK0," rgroup.quad 0x1340++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_BIFPM_CTRL,Miscellaneous controls" hexmask.quad 0x0 2.--63. 1. "RESERVED_2," newline bitfld.quad 0x0 1. "ENABLE_SLC_STALLING,Enables BIF to stall returns from SLC so that requests can be made even when there is no space in the BIF return buffer [only when no chance of lockup]" "0,1" newline bitfld.quad 0x0 0. "PAUSE_BIF0,Stalls BIF0 pipeline" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_BIFPM_CTRL_INVAL,Invalidation bits allowing BIF to clear when invalidation complete" hexmask.quad 0x8 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x8 0. "TLB0," "0,1" rgroup.quad 0x1350++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_BIFPM_STATUS_MMU,Outstanding MMU requests from BIF0" hexmask.quad 0x0 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x0 0.--7. 1. "REQUESTS," line.quad 0x8 "CORE_MMRS_RGX_CR_BIF_STATUS_MMU,Outstanding MMU requests from BIF1" hexmask.quad 0x8 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x8 0.--7. 1. "REQUESTS," rgroup.quad 0x1370++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_BIF_BLACKPEARL_PWR,Power monitoring register" hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "NUM_256BIT_TRANS,Number of 256-bit transactions" line.quad 0x8 "CORE_MMRS_RGX_CR_BIF_JONES_PWR,Power monitoring register" hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "NUM_256BIT_TRANS,Number of 256-bit transactions" rgroup.quad 0x13E0++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_BIF_FAULT_READ,Specifies physical address to read from in the event of a faulting read request from BIF1" hexmask.quad.tbyte 0x0 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x0 4.--39. 1. "ADDRESS," newline hexmask.quad.byte 0x0 0.--3. 1. "RESERVED_0," rgroup.quad 0x13E8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_BIF_PWR,Power monitoring register" hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "NUM_256BIT_TRANS,Number of 256-bit transactions" rgroup.quad 0x13F8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_BIF_MCU_RESERVED,Allows driver to change the amount of space in the return data FIFO reserved for the MCU" hexmask.quad 0x0 5.--63. 1. "RESERVED_5," newline hexmask.quad.byte 0x0 0.--4. 1. "SPACE,Granularity of 8 spaces minimum legal value 0x1" rgroup.quad 0x1430++0x27 line.quad 0x0 "CORE_MMRS_RGX_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS,Indicates a fault has occurred on bank 0 and provides details of fault" hexmask.quad 0x0 16.--63. 1. "RESERVED_16," newline hexmask.quad.byte 0x0 12.--15. 1. "CAT_BASE,Catalogue base address number" newline bitfld.quad 0x0 11. "RESERVED_11," "0,1" newline bitfld.quad 0x0 8.--10. "PAGE_SIZE,Page size" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x0 7. "RESERVED_7," "0,1" newline bitfld.quad 0x0 5.--6. "DATA_TYPE,MMU data type that was invalid [on valid fault]" "0,1,2,3" newline bitfld.quad 0x0 4. "FAULT_RO,Indicates read-only fault['1'] or valid fault['0']" "0,1" newline bitfld.quad 0x0 3. "RESERVED_3," "0,1" newline bitfld.quad 0x0 2. "FAULT_PM_META_RO,Indicates pm/meta protected region fault" "0,1" newline bitfld.quad 0x0 1. "RESERVED_1," "0,1" newline bitfld.quad 0x0 0. "FAULT,Indicates a fault has occured" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS,Provides details of the request that faulted on bank 0" hexmask.quad.word 0x8 51.--63. 1. "RESERVED_51," newline bitfld.quad 0x8 50. "RNW," "0,1" newline hexmask.quad.byte 0x8 44.--49. 1. "TAG_SB," newline hexmask.quad.byte 0x8 40.--43. 1. "TAG_ID," newline hexmask.quad 0x8 4.--39. 1. "ADDRESS," newline hexmask.quad.byte 0x8 0.--3. 1. "RESERVED_0," line.quad 0x10 "CORE_MMRS_RGX_CR_TEXAS_BIFPM_READS_INT_STATUS,Outstanding 256-bit read data in return data FIFO for BIF256" hexmask.quad 0x10 16.--63. 1. "RESERVED_16," newline hexmask.quad.word 0x10 0.--15. 1. "BANK0," line.quad 0x18 "CORE_MMRS_RGX_CR_TEXAS_BIFPM_READS_EXT_STATUS,Outstanding 256-bit read data external to BIF for BIF256" hexmask.quad 0x18 16.--63. 1. "RESERVED_16," newline hexmask.quad.word 0x18 0.--15. 1. "BANK0," line.quad 0x20 "CORE_MMRS_RGX_CR_TEXAS_BIFPM_STATUS_MMU,Outstanding MMU requests from BIF0" hexmask.quad 0x20 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x20 0.--7. 1. "REQUESTS," rgroup.quad 0x1460++0x3F line.quad 0x0 "CORE_MMRS_RGX_CR_BIF_OSID0,Defines OSID for each CAT_BASE" hexmask.quad.byte 0x0 59.--63. 1. "RESERVED_59," newline bitfld.quad 0x0 56.--58. "CBASE7,OSID for CAT BASE 7" "0,1,2,3,4,5,6,7" newline hexmask.quad.byte 0x0 51.--55. 1. "RESERVED_51," newline bitfld.quad 0x0 48.--50. "CBASE6,OSID for CAT BASE 6" "0,1,2,3,4,5,6,7" newline hexmask.quad.byte 0x0 43.--47. 1. "RESERVED_43," newline bitfld.quad 0x0 40.--42. "CBASE5,OSID for CAT BASE 5" "0,1,2,3,4,5,6,7" newline hexmask.quad.byte 0x0 35.--39. 1. "RESERVED_35," newline bitfld.quad 0x0 32.--34. "CBASE4,OSID for CAT BASE 4" "0,1,2,3,4,5,6,7" newline hexmask.quad.byte 0x0 27.--31. 1. "RESERVED_27," newline bitfld.quad 0x0 24.--26. "CBASE3,OSID for CAT BASE 3" "0,1,2,3,4,5,6,7" newline hexmask.quad.byte 0x0 19.--23. 1. "RESERVED_19," newline bitfld.quad 0x0 16.--18. "CBASE2,OSID for CAT BASE 2" "0,1,2,3,4,5,6,7" newline hexmask.quad.byte 0x0 11.--15. 1. "RESERVED_11," newline bitfld.quad 0x0 8.--10. "CBASE1,OSID for CAT BASE 1" "0,1,2,3,4,5,6,7" newline hexmask.quad.byte 0x0 3.--7. 1. "RESERVED_3," newline bitfld.quad 0x0 0.--2. "CBASE0,OSID for CAT BASE 0" "0,1,2,3,4,5,6,7" line.quad 0x8 "CORE_MMRS_RGX_CR_BIF_OSID1,Defines OSID for each data master" hexmask.quad 0x8 11.--63. 1. "RESERVED_11," newline bitfld.quad 0x8 8.--10. "PM_CTX1,OSID for VCE1 TE1 and ALIST1" "0,1,2,3,4,5,6,7" newline hexmask.quad.byte 0x8 3.--7. 1. "RESERVED_3," newline bitfld.quad 0x8 0.--2. "PM_CTX0,OSID for VCE0 TE0 and ALIST0" "0,1,2,3,4,5,6,7" line.quad 0x10 "CORE_MMRS_RGX_CR_TFBC_ZLS_COMPRESSOR_CFI,ZLS TFBC compressor cache control flush" hexmask.quad 0x10 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x10 0. "PENDING,Write a one to this register to initiate a flush of the ZLS TFBC Compressor cache. This register can be read. If the value is one the this indicates a flush operation is underway." "0,1" line.quad 0x18 "CORE_MMRS_RGX_CR_TFBC_PBE_COMPRESSOR_CFI,PBE TFBC compressor cache control flush" hexmask.quad 0x18 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x18 0. "PENDING,Write a one to this register to initiate a flush of the PBE TFBC Compressor cache. This register can be read. If the value is one the this indicates a flush operation is underway." "0,1" line.quad 0x20 "CORE_MMRS_RGX_CR_TFBC_ZLS_DECOMPRESSOR_CFI,ZLS TFBC decompressor cache invalidation" hexmask.quad 0x20 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x20 0. "INVALIDATE,Informs the ZLS decompressor to invalidate its cache." "0,1" line.quad 0x28 "CORE_MMRS_RGX_CR_TFBC_TPU_DECOMPRESSOR_CFI,TPU TFBC decompressor cache invalidation" hexmask.quad 0x28 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x28 0. "INVALIDATE,Informs the TPU decompressor to invalidate its cache." "0,1" line.quad 0x30 "CORE_MMRS_RGX_CR_TFBC_CACHE_CTRL,TFBC compressor and decompressor cache control register" hexmask.quad 0x30 22.--63. 1. "RESERVED_22," newline bitfld.quad 0x30 21. "ZLS_DECOMPRESSOR_BYPASS,When set to 1 the ZLS decompressor cache is disabled." "0,1" newline bitfld.quad 0x30 20. "TPU_DECOMPRESSOR_BYPASS,When set to 1 the TPU decompressor cache is disabled." "0,1" newline bitfld.quad 0x30 19. "ZLS_COMPRESSOR_DELTA_NOHAZARD,When set to 1 the ZLS compressor no_hazard signal is set high to the SLC for delta writes. This will cause the TFBC to disable hazard checking in the SLC for delta writes." "0,1" newline bitfld.quad 0x30 18. "ZLS_COMPRESSOR_HEADER_NOHAZARD,When set to 1 the ZLS compressor no_hazard signal is set high to the SLC for header writes. This will cause the TFBC to disable hazard checking in the SLC for header writes." "0,1" newline bitfld.quad 0x30 17. "ZLS_COMPRESSOR_DELTA_NOLINEFILL,When set to 0 the ZLS compressor line fills data from memory before writing data back for deltas. When set to 1 the ZLS compressor does not line fill from memory for deltas." "0,1" newline bitfld.quad 0x30 16. "ZLS_COMPRESSOR_HEADER_NOLINEFILL,When set to 0 the ZLS compressor line fills data from memory before writing data back for headers. When set to 1 the ZLS compressor does not line fill from memory for headers." "0,1" newline bitfld.quad 0x30 15. "ZLS_COMPRESSOR_DELTA_POLICY_OVERRIDE,When set to 0 the ZLS compressor will use the SLC policy supplied by the ZLS for delta writes. When set to 1 the ZLS compressor will use the ZLS_COMPRESSOR_DELTA_POLICY for delta writes." "0,1" newline bitfld.quad 0x30 14. "ZLS_COMPRESSOR_HEADER_POLICY_OVERRIDE,When set to 0 the ZLS compressor will use the SLC policy supplied by the ZLS for header writes. When set to 1 the ZLS compressor will use the ZLS_COMPRESSOR_HEADER_POLICY for header.." "0,1" newline bitfld.quad 0x30 12.--13. "ZLS_COMPRESSOR_DELTA_POLICY,SLC cache policy applied to ZLS compressor delta writes when ZLS_COMPRESSOR_DELTA_POLICY_OVERRIDE is set to 1" "0,1,2,3" newline bitfld.quad 0x30 10.--11. "ZLS_COMPRESSOR_HEADER_POLICY,SLC cache policy applied to ZLS compressor header writes when ZLS_COMPRESSOR_HEADER_POLICY_OVERRIDE is set to 1" "0,1,2,3" newline bitfld.quad 0x30 9. "PBE_COMPRESSOR_DELTA_NOHAZARD,When set to 1 the PBE compressor no_hazard signal is set high to the SLC for delta writes. This will cause the TFBC to disable hazard checking in the SLC for delta writes." "0,1" newline bitfld.quad 0x30 8. "PBE_COMPRESSOR_HEADER_NOHAZARD,When set to 1 the PBE compressor no_hazard signal is set high to the SLC for header writes. This will cause the TFBC to disable hazard checking in the SLC for header writes." "0,1" newline bitfld.quad 0x30 7. "PBE_COMPRESSOR_DELTA_NOLINEFILL,When set to 0 the PBE compressor line fills data from memory before writing data back for deltas. When set to 1 the PBE compressor does not line fill from memory for deltas." "0,1" newline bitfld.quad 0x30 6. "PBE_COMPRESSOR_HEADER_NOLINEFILL,When set to 0 the PBE compressor line fills data from memory before writing data back for headers. When set to 1 the PBE compressor does not line fill from memory for headers." "0,1" newline bitfld.quad 0x30 5. "PBE_COMPRESSOR_DELTA_POLICY_OVERRIDE,When set to 0 the PBE compressor will use the SLC policy supplied by the PBE for delta writes. When set to 1 the PBE compressor will use the PBE_COMPRESSOR_DELTA_POLICY for delta writes." "0,1" newline bitfld.quad 0x30 4. "PBE_COMPRESSOR_HEADER_POLICY_OVERRIDE,When set to 0 the PBE compressor will use the SLC policy supplied by the PBE for header writes. When set to 1 the PBE compressor will use the PBE_COMPRESSOR_HEADER_POLICY for header.." "0,1" newline bitfld.quad 0x30 2.--3. "PBE_COMPRESSOR_DELTA_POLICY,SLC cache policy applied to PBE compressor delta writes when PBE_COMPRESSOR_DELTA_POLICY_OVERRIDE is set to 1" "0,1,2,3" newline bitfld.quad 0x30 0.--1. "PBE_COMPRESSOR_HEADER_POLICY,SLC cache policy applied to PBE compressor header writes when PBE_COMPRESSOR_HEADER_POLICY_OVERRIDE is set to 1" "0,1,2,3" line.quad 0x38 "CORE_MMRS_RGX_CR_TFBC_CTRL,General TFBC control register" hexmask.quad 0x38 2.--63. 1. "RESERVED_2," newline bitfld.quad 0x38 1. "ZLS_CRC_ENABLE,Enable the generation of CRCs for compression depth buffer writes." "0,1" newline bitfld.quad 0x38 0. "PBE_CRC_ENABLE,Enable the generation of CRCs for compressed frame buffer writes." "0,1" rgroup.quad 0x1500++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PBE,The PBE(Pixel back end) module scales and packs the pixel data before writing to memory." hexmask.quad 0x0 9.--63. 1. "RESERVED_9," newline bitfld.quad 0x0 8. "AA_EDGEOPT_OFF,Switches off the PBE-USE read optimisation during Anti aliasing mode. [This is typically for debug purposes only]" "0,1" newline hexmask.quad.byte 0x0 0.--7. 1. "ALPHATHRESHOLD,Alpha threshold used when encoding 1555 format. If the internal 8bit Alpha value exceeds this value then a 1 is written to the top bit of the output otherwise a 0 is written" rgroup.quad 0x1508++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PBE_EMIT_STATUS,This register indicates if the PixelBE would stall the USE if there were another emit." hexmask.quad 0x0 16.--63. 1. "RESERVED_16," newline bitfld.quad 0x0 15. "USC15,Pipe 15 status" "0,1" newline bitfld.quad 0x0 14. "USC14,Pipe 14 status" "0,1" newline bitfld.quad 0x0 13. "USC13,Pipe 13 status" "0,1" newline bitfld.quad 0x0 12. "USC12,Pipe 12 status" "0,1" newline bitfld.quad 0x0 11. "USC11,Pipe 11 status" "0,1" newline bitfld.quad 0x0 10. "USC10,Pipe 10 status" "0,1" newline bitfld.quad 0x0 9. "USC9,Pipe 9 status" "0,1" newline bitfld.quad 0x0 8. "USC8,Pipe 8 status" "0,1" newline bitfld.quad 0x0 7. "USC7,Pipe 7 status" "0,1" newline bitfld.quad 0x0 6. "USC6,Pipe 6 status" "0,1" newline bitfld.quad 0x0 5. "USC5,Pipe 5 status" "0,1" newline bitfld.quad 0x0 4. "USC4,Pipe 4 status" "0,1" newline bitfld.quad 0x0 3. "USC3,Pipe 3 status" "0,1" newline bitfld.quad 0x0 2. "USC2,Pipe 2 status" "0,1" newline bitfld.quad 0x0 1. "USC1,Pipe 1 status" "0,1" newline bitfld.quad 0x0 0. "USC0,Pipe 0 status" "0,1" rgroup.quad 0x1510++0x7F line.quad 0x0 "CORE_MMRS_RGX_CR_PBE_WORD0_MRT0,Pixel Back end State Word 0." bitfld.quad 0x0 62.--63. "TFBC_LOSSY,Sets the lossy bit for frame buffer compression" "0,1,2,3" newline bitfld.quad 0x0 61. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0.." "0,1" newline bitfld.quad 0x0 60. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline bitfld.quad 0x0 59. "X_RSRVD2,Not used" "0,1" newline bitfld.quad 0x0 58. "DITHER,Enable dither" "0,1" newline bitfld.quad 0x0 57. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.quad 0x0 56. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.quad.byte 0x0 52.--55. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.quad 0x0 50.--51. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.quad.word 0x0 34.--49. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.quad 0x0 32.--33. "MEMLAYOUT,Memory layout" "0,1,2,3" newline bitfld.quad 0x0 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x0 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x0 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x0 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x0 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.quad 0x0 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.quad 0x0 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.quad 0x0 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.quad 0x0 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8.." "0,1" newline bitfld.quad 0x0 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.quad 0x0 0. "Y_FLIP," "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_PBE_WORD0_MRT1,Pixel Back end State Word 0." bitfld.quad 0x8 62.--63. "TFBC_LOSSY,Sets the lossy bit for frame buffer compression" "0,1,2,3" newline bitfld.quad 0x8 61. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0.." "0,1" newline bitfld.quad 0x8 60. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline bitfld.quad 0x8 59. "X_RSRVD2,Not used" "0,1" newline bitfld.quad 0x8 58. "DITHER,Enable dither" "0,1" newline bitfld.quad 0x8 57. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.quad 0x8 56. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.quad.byte 0x8 52.--55. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.quad 0x8 50.--51. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.quad.word 0x8 34.--49. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.quad 0x8 32.--33. "MEMLAYOUT,Memory layout" "0,1,2,3" newline bitfld.quad 0x8 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x8 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x8 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x8 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x8 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.quad 0x8 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.quad 0x8 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.quad 0x8 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.quad 0x8 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8.." "0,1" newline bitfld.quad 0x8 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.quad 0x8 0. "Y_FLIP," "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_PBE_WORD0_MRT2,Pixel Back end State Word 0." bitfld.quad 0x10 62.--63. "TFBC_LOSSY,Sets the lossy bit for frame buffer compression" "0,1,2,3" newline bitfld.quad 0x10 61. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0.." "0,1" newline bitfld.quad 0x10 60. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline bitfld.quad 0x10 59. "X_RSRVD2,Not used" "0,1" newline bitfld.quad 0x10 58. "DITHER,Enable dither" "0,1" newline bitfld.quad 0x10 57. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.quad 0x10 56. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.quad.byte 0x10 52.--55. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.quad 0x10 50.--51. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.quad.word 0x10 34.--49. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.quad 0x10 32.--33. "MEMLAYOUT,Memory layout" "0,1,2,3" newline bitfld.quad 0x10 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x10 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x10 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x10 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x10 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.quad 0x10 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.quad 0x10 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.quad 0x10 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.quad 0x10 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8.." "0,1" newline bitfld.quad 0x10 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.quad 0x10 0. "Y_FLIP," "0,1" line.quad 0x18 "CORE_MMRS_RGX_CR_PBE_WORD0_MRT3,Pixel Back end State Word 0." bitfld.quad 0x18 62.--63. "TFBC_LOSSY,Sets the lossy bit for frame buffer compression" "0,1,2,3" newline bitfld.quad 0x18 61. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0.." "0,1" newline bitfld.quad 0x18 60. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline bitfld.quad 0x18 59. "X_RSRVD2,Not used" "0,1" newline bitfld.quad 0x18 58. "DITHER,Enable dither" "0,1" newline bitfld.quad 0x18 57. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.quad 0x18 56. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.quad.byte 0x18 52.--55. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.quad 0x18 50.--51. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.quad.word 0x18 34.--49. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.quad 0x18 32.--33. "MEMLAYOUT,Memory layout" "0,1,2,3" newline bitfld.quad 0x18 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x18 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x18 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x18 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x18 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.quad 0x18 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.quad 0x18 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.quad 0x18 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.quad 0x18 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8.." "0,1" newline bitfld.quad 0x18 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.quad 0x18 0. "Y_FLIP," "0,1" line.quad 0x20 "CORE_MMRS_RGX_CR_PBE_WORD0_MRT4,Pixel Back end State Word 0." bitfld.quad 0x20 62.--63. "TFBC_LOSSY,Sets the lossy bit for frame buffer compression" "0,1,2,3" newline bitfld.quad 0x20 61. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0.." "0,1" newline bitfld.quad 0x20 60. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline bitfld.quad 0x20 59. "X_RSRVD2,Not used" "0,1" newline bitfld.quad 0x20 58. "DITHER,Enable dither" "0,1" newline bitfld.quad 0x20 57. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.quad 0x20 56. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.quad.byte 0x20 52.--55. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.quad 0x20 50.--51. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.quad.word 0x20 34.--49. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.quad 0x20 32.--33. "MEMLAYOUT,Memory layout" "0,1,2,3" newline bitfld.quad 0x20 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x20 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x20 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x20 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x20 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.quad 0x20 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.quad 0x20 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.quad 0x20 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.quad 0x20 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8.." "0,1" newline bitfld.quad 0x20 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.quad 0x20 0. "Y_FLIP," "0,1" line.quad 0x28 "CORE_MMRS_RGX_CR_PBE_WORD0_MRT5,Pixel Back end State Word 0." bitfld.quad 0x28 62.--63. "TFBC_LOSSY,Sets the lossy bit for frame buffer compression" "0,1,2,3" newline bitfld.quad 0x28 61. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0.." "0,1" newline bitfld.quad 0x28 60. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline bitfld.quad 0x28 59. "X_RSRVD2,Not used" "0,1" newline bitfld.quad 0x28 58. "DITHER,Enable dither" "0,1" newline bitfld.quad 0x28 57. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.quad 0x28 56. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.quad.byte 0x28 52.--55. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.quad 0x28 50.--51. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.quad.word 0x28 34.--49. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.quad 0x28 32.--33. "MEMLAYOUT,Memory layout" "0,1,2,3" newline bitfld.quad 0x28 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x28 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x28 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x28 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x28 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.quad 0x28 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.quad 0x28 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.quad 0x28 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.quad 0x28 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8.." "0,1" newline bitfld.quad 0x28 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.quad 0x28 0. "Y_FLIP," "0,1" line.quad 0x30 "CORE_MMRS_RGX_CR_PBE_WORD0_MRT6,Pixel Back end State Word 0." bitfld.quad 0x30 62.--63. "TFBC_LOSSY,Sets the lossy bit for frame buffer compression" "0,1,2,3" newline bitfld.quad 0x30 61. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0.." "0,1" newline bitfld.quad 0x30 60. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline bitfld.quad 0x30 59. "X_RSRVD2,Not used" "0,1" newline bitfld.quad 0x30 58. "DITHER,Enable dither" "0,1" newline bitfld.quad 0x30 57. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.quad 0x30 56. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.quad.byte 0x30 52.--55. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.quad 0x30 50.--51. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.quad.word 0x30 34.--49. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.quad 0x30 32.--33. "MEMLAYOUT,Memory layout" "0,1,2,3" newline bitfld.quad 0x30 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x30 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x30 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x30 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x30 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.quad 0x30 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.quad 0x30 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.quad 0x30 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.quad 0x30 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8.." "0,1" newline bitfld.quad 0x30 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.quad 0x30 0. "Y_FLIP," "0,1" line.quad 0x38 "CORE_MMRS_RGX_CR_PBE_WORD0_MRT7,Pixel Back end State Word 0." bitfld.quad 0x38 62.--63. "TFBC_LOSSY,Sets the lossy bit for frame buffer compression" "0,1,2,3" newline bitfld.quad 0x38 61. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0.." "0,1" newline bitfld.quad 0x38 60. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline bitfld.quad 0x38 59. "X_RSRVD2,Not used" "0,1" newline bitfld.quad 0x38 58. "DITHER,Enable dither" "0,1" newline bitfld.quad 0x38 57. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.quad 0x38 56. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.quad.byte 0x38 52.--55. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.quad 0x38 50.--51. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.quad.word 0x38 34.--49. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.quad 0x38 32.--33. "MEMLAYOUT,Memory layout" "0,1,2,3" newline bitfld.quad 0x38 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x38 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x38 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x38 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x38 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.quad 0x38 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.quad 0x38 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.quad 0x38 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.quad 0x38 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8.." "0,1" newline bitfld.quad 0x38 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.quad 0x38 0. "Y_FLIP," "0,1" line.quad 0x40 "CORE_MMRS_RGX_CR_PBE_WORD1_MRT0,Pixel Back end State Word 1." hexmask.quad.byte 0x40 60.--63. 1. "SIZE_X,X Size in pixels [log 2]" newline hexmask.quad.word 0x40 46.--59. 1. "MINCLIP_Y,Min Y Clip" newline hexmask.quad.word 0x40 32.--45. 1. "MAXCLIP_X,Max X clip" newline hexmask.quad.byte 0x40 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.quad.word 0x40 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.quad.word 0x40 0.--13. 1. "MAXCLIP_Y,Max Y clip" line.quad 0x48 "CORE_MMRS_RGX_CR_PBE_WORD1_MRT1,Pixel Back end State Word 1." hexmask.quad.byte 0x48 60.--63. 1. "SIZE_X,X Size in pixels [log 2]" newline hexmask.quad.word 0x48 46.--59. 1. "MINCLIP_Y,Min Y Clip" newline hexmask.quad.word 0x48 32.--45. 1. "MAXCLIP_X,Max X clip" newline hexmask.quad.byte 0x48 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.quad.word 0x48 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.quad.word 0x48 0.--13. 1. "MAXCLIP_Y,Max Y clip" line.quad 0x50 "CORE_MMRS_RGX_CR_PBE_WORD1_MRT2,Pixel Back end State Word 1." hexmask.quad.byte 0x50 60.--63. 1. "SIZE_X,X Size in pixels [log 2]" newline hexmask.quad.word 0x50 46.--59. 1. "MINCLIP_Y,Min Y Clip" newline hexmask.quad.word 0x50 32.--45. 1. "MAXCLIP_X,Max X clip" newline hexmask.quad.byte 0x50 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.quad.word 0x50 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.quad.word 0x50 0.--13. 1. "MAXCLIP_Y,Max Y clip" line.quad 0x58 "CORE_MMRS_RGX_CR_PBE_WORD1_MRT3,Pixel Back end State Word 1." hexmask.quad.byte 0x58 60.--63. 1. "SIZE_X,X Size in pixels [log 2]" newline hexmask.quad.word 0x58 46.--59. 1. "MINCLIP_Y,Min Y Clip" newline hexmask.quad.word 0x58 32.--45. 1. "MAXCLIP_X,Max X clip" newline hexmask.quad.byte 0x58 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.quad.word 0x58 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.quad.word 0x58 0.--13. 1. "MAXCLIP_Y,Max Y clip" line.quad 0x60 "CORE_MMRS_RGX_CR_PBE_WORD1_MRT4,Pixel Back end State Word 1." hexmask.quad.byte 0x60 60.--63. 1. "SIZE_X,X Size in pixels [log 2]" newline hexmask.quad.word 0x60 46.--59. 1. "MINCLIP_Y,Min Y Clip" newline hexmask.quad.word 0x60 32.--45. 1. "MAXCLIP_X,Max X clip" newline hexmask.quad.byte 0x60 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.quad.word 0x60 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.quad.word 0x60 0.--13. 1. "MAXCLIP_Y,Max Y clip" line.quad 0x68 "CORE_MMRS_RGX_CR_PBE_WORD1_MRT5,Pixel Back end State Word 1." hexmask.quad.byte 0x68 60.--63. 1. "SIZE_X,X Size in pixels [log 2]" newline hexmask.quad.word 0x68 46.--59. 1. "MINCLIP_Y,Min Y Clip" newline hexmask.quad.word 0x68 32.--45. 1. "MAXCLIP_X,Max X clip" newline hexmask.quad.byte 0x68 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.quad.word 0x68 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.quad.word 0x68 0.--13. 1. "MAXCLIP_Y,Max Y clip" line.quad 0x70 "CORE_MMRS_RGX_CR_PBE_WORD1_MRT6,Pixel Back end State Word 1." hexmask.quad.byte 0x70 60.--63. 1. "SIZE_X,X Size in pixels [log 2]" newline hexmask.quad.word 0x70 46.--59. 1. "MINCLIP_Y,Min Y Clip" newline hexmask.quad.word 0x70 32.--45. 1. "MAXCLIP_X,Max X clip" newline hexmask.quad.byte 0x70 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.quad.word 0x70 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.quad.word 0x70 0.--13. 1. "MAXCLIP_Y,Max Y clip" line.quad 0x78 "CORE_MMRS_RGX_CR_PBE_WORD1_MRT7,Pixel Back end State Word 1." hexmask.quad.byte 0x78 60.--63. 1. "SIZE_X,X Size in pixels [log 2]" newline hexmask.quad.word 0x78 46.--59. 1. "MINCLIP_Y,Min Y Clip" newline hexmask.quad.word 0x78 32.--45. 1. "MAXCLIP_X,Max X clip" newline hexmask.quad.byte 0x78 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.quad.word 0x78 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.quad.word 0x78 0.--13. 1. "MAXCLIP_Y,Max Y clip" rgroup.quad 0x1590++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PBE_PWR,Power monitoring register" hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "NUM_PIXELS_PROCESSED,Number of on-edge/off-edge pixels per tile." rgroup.quad 0x1720++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_MCU_GLB_CFI,Global flush and invalidation control for all Texture and Data Cache." hexmask.quad 0x0 6.--63. 1. "RESERVED_6," newline bitfld.quad 0x0 5. "FENCE,When set additionally perform a fence to external memory before signalling that a flush is complete" "0,1" newline bitfld.quad 0x0 4. "DM_COMPUTE,When set perform operation on compute data master" "0,1" newline bitfld.quad 0x0 3. "DM_PIXEL,When set perform operation on pixel data master" "0,1" newline bitfld.quad 0x0 2. "DM_VERTEX,When set perform operation on vertex data master" "0,1" newline bitfld.quad 0x0 1. "FLUSH,When set will flush cache based on data master" "0,1" newline bitfld.quad 0x0 0. "INVALIDATE,When set will invalidate cache based on data master. This bit will also invalidate the L0 cache in the MADD and teh YUV cache in the TAG to reset the CSC coefficients." "0,1" rgroup.quad 0x1728++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_MCU_GLB_CFI_EVENT,Global flush and invalidation event for all Texture and Data Cache." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "PENDING,1 Indicate there is a pending global CFI operation on the MCU" "0,1" rgroup.quad 0x1730++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_MCU_LIMIT,Define the maximum number of cache lines allowed to be allocated to each Data Master within the SLC." hexmask.quad 0x0 24.--63. 1. "RESERVED_24," newline hexmask.quad.byte 0x0 16.--23. 1. "DM_COMPUTE,Maximum number of cachelines which can be used by the Compute data master" newline hexmask.quad.byte 0x0 8.--15. 1. "DM_PIXEL,Maximum number of cachelines which can be used by the Pixel data master" newline hexmask.quad.byte 0x0 0.--7. 1. "DM_VERTEX,Maximum number of cachelines which can be used by the Vertex data master" line.quad 0x8 "CORE_MMRS_RGX_CR_MCU_CTRL,MCU control registers" hexmask.quad 0x8 18.--63. 1. "RESERVED_18," newline bitfld.quad 0x8 17. "PDSRW_L0_OFF,Turn off MCU PDSRW L0 cache" "0,1" newline hexmask.quad.byte 0x8 9.--16. 1. "FBDC_REQ_THRESHOLD,Maximum number of outstanding requests each MCU group can have to the Framebuffer Decompression module" newline bitfld.quad 0x8 8. "RD_OVERTAKE_THRESH_ENABLE,Enables the use of the threshold to limit the amount of overtaking which is permitted" "0,1" newline hexmask.quad.byte 0x8 2.--7. 1. "RD_OVERTAKE_THRESHOLD,The number of read accesses which are permitted to overtake waiting Writebacks when enabled" newline bitfld.quad 0x8 1. "INSTANCE_MERGE_DISABLE,Turn off instance merging in the MCU L1" "0,1" newline bitfld.quad 0x8 0. "L1_OFF,Turn off MCU L1" "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_MCU_FENCE,Defines the Data Master and Addresses used when the MCU optionally issues a Fence as part of a Flush operation." hexmask.quad.tbyte 0x10 43.--63. 1. "RESERVED_43," newline bitfld.quad 0x10 40.--42. "DM,Data Master value to use when issuing a Fence" "0,1,2,3,4,5,6,7" newline hexmask.quad 0x10 5.--39. 1. "ADDR,Address value to use when issuing a Fence" newline hexmask.quad.byte 0x10 0.--4. 1. "RESERVED_0," rgroup.quad 0x1780++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_TPU,Global control to TPU_MCU_L0|tpu" hexmask.quad 0x0 9.--63. 1. "RESERVED_9," newline bitfld.quad 0x0 8. "MCU_PDS_L0_OFF,Turn off MCU PDSL0 cache" "0,1" newline bitfld.quad 0x0 7. "TAG_CEM_64_FACE_PACKING,Pixel data master. Enable 64-byte alignment between CEM faces when set to 1. It applies for both when mipmap is enabled or disabled" "0,1" newline bitfld.quad 0x0 6. "TAG_ENABLE_MMU_PREFETCH,Enables generation of prefetch requests to the MMU" "0,1" newline bitfld.quad 0x0 5. "TAG_CEM_4K_FACE_PACKING,Pixel data master. Enable 4K-byte alignment between CEM faces when set to 1. It applies for both when mipmap is enabled or disabled" "0,1" newline bitfld.quad 0x0 4. "MADD_CONFIG_L0OFF,When set this disables MADD P0 L0 cache" "0,1" newline bitfld.quad 0x0 3. "TAG_CEM_FACE_PACKING,Pixel data master. Enable dword alignment between CEM faces when set to 1" "0,1" newline bitfld.quad 0x0 2. "TAG_CEMEDGE_DONTFILTER,Pixel data master. Disable filtering over edges/corners for CEM. When set to 1 HW will be seemfull ie always stay in the current map always.." "0,1" newline bitfld.quad 0x0 1. "TAG_CEMGRAD_DONTNEGATE,Pixel data master. Disable negation for user supplied gradients for cem swap i. e. will only swap dudx etc not negate" "0,1" newline bitfld.quad 0x0 0. "MADD_CONFIG_DXT35_TRANSOVR,When set this disables alternative mode implied by colour0 > colour1 for DXT3 to DXT5" "0: colour1 for DXT3 to DXT5,?" line.quad 0x8 "CORE_MMRS_RGX_CR_TPU_YUV_CSC_COEFFICIENTS,Base address for the YUV CSC set of coefficients stored in memory for pixel data master" hexmask.quad.long 0x8 38.--63. 1. "RESERVED_38," newline hexmask.quad 0x8 0.--37. 1. "YUV_CSC_COEFFICIENTS_ADDRESS,Base address DWORD aligned for the location in memory of the CSC coefficients" line.quad 0x10 "CORE_MMRS_RGX_CR_TPU_BORDER_COLOUR_TABLE_PDM,Base address for the border colour table" hexmask.quad.long 0x10 38.--63. 1. "RESERVED_38," newline hexmask.quad 0x10 0.--37. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the PDM" rgroup.quad 0x1798++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_DUST_IDLE," hexmask.quad 0x0 7.--63. 1. "RESERVED_7," newline bitfld.quad 0x0 6. "MCU_L0_WRAP,MCU L0 WRAP Module IDLE" "0,1" newline bitfld.quad 0x0 5. "MCU_L0,MCU L0 Module IDLE" "0,1" newline bitfld.quad 0x0 4. "TF,TF Module IDLE" "0,1" newline bitfld.quad 0x0 3. "MADD,MADD Module IDLE" "0,1" newline bitfld.quad 0x0 2. "TAG,TAG Module IDLE" "0,1" newline bitfld.quad 0x0 1. "USC1,USC1 Module IDLE" "0,1" newline bitfld.quad 0x0 0. "USC0,USC0 Module IDLE" "0,1" rgroup.quad 0x17A0++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_TPU_BORDER_COLOUR_TABLE_VDM,Base address for the border colour table" hexmask.quad.long 0x0 38.--63. 1. "RESERVED_38," newline hexmask.quad 0x0 0.--37. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the VDM" line.quad 0x8 "CORE_MMRS_RGX_CR_TPU_BORDER_COLOUR_TABLE_CDM,Base address for the border colour table" hexmask.quad.long 0x8 38.--63. 1. "RESERVED_38," newline hexmask.quad 0x8 0.--37. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the CDM" rgroup.quad 0x17B0++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_TPU_PWR_NUMBER_OF_TEXELS,Peformance counter associated with Power Monitoring." hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "VALUE,Number of texels requested per clock" rgroup.quad 0x17B8++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_TPU_TAG_CTRL,Global control to TAG for the pixel data master" hexmask.quad 0x0 4.--63. 1. "RESERVED_4," newline bitfld.quad 0x0 3. "AF_RATIO_TRUNCATE_TO_INTEGER,0 current mode 1 clear the fractional part of the calculated AF ratio" "0,1" newline bitfld.quad 0x0 2. "AF_RATIO_TRUNCATE_TO_HALF,0 current mode 1 truncate the fractional part of the calculated AF ratio to 0. 5" "0,1" newline bitfld.quad 0x0 1. "AF_FILTERING_MODE,0 current mode 1 new mode." "0,1" newline bitfld.quad 0x0 0. "YUV_CAM_INVALIDATE,When set will invalidate YUV CSC CAM to reset the CSC coefficients. It should be set when the TPU is not performing CSC." "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_TPU_MADD_CTRL,Global control to MADD for pixel data master" hexmask.quad 0x8 2.--63. 1. "RESERVED_2," newline bitfld.quad 0x8 1. "ASTC_ODD_SCALING_ENABLE,When set ASTC encoded texels use the odd U16->F16 scaling in the TF. When zero the usual scaling will be used in TF." "0,1" newline bitfld.quad 0x8 0. "ASTC_MULTICYCLE_TF_FORCE_F16,When set ASTC encoded texels that are filtered over multiple cycles by the TF will be output from the MADD as F16." "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_TPU_MADD_VDM_CTRL,Global control to MADD for vertex data master" hexmask.quad 0x10 3.--63. 1. "RESERVED_3," newline bitfld.quad 0x10 2. "MADD_CONFIG_DXT35_TRANSOVR,When set this disables alternative mode implied by colour0 > colour1 for DXT3 to DXT5" "0: colour1 for DXT3 to DXT5,?" newline bitfld.quad 0x10 1. "ASTC_ODD_SCALING_ENABLE,When set ASTC encoded texels use the odd U16->F16 scaling in the TF. When zero the usual scaling will be used in TF." "0,1" newline bitfld.quad 0x10 0. "ASTC_MULTICYCLE_TF_FORCE_F16,When set ASTC encoded texels that are filtered over multiple cycles by the TF will be output from the MADD as F16." "0,1" line.quad 0x18 "CORE_MMRS_RGX_CR_TPU_MADD_CDM_CTRL,Global control to MADD for compute data master" hexmask.quad 0x18 3.--63. 1. "RESERVED_3," newline bitfld.quad 0x18 2. "MADD_CONFIG_DXT35_TRANSOVR,When set this disables alternative mode implied by colour0 > colour1 for DXT3 to DXT5" "0: colour1 for DXT3 to DXT5,?" newline bitfld.quad 0x18 1. "ASTC_ODD_SCALING_ENABLE,When set ASTC encoded texels use the odd U16->F16 scaling in the TF. When zero the usual scaling will be used in TF." "0,1" newline bitfld.quad 0x18 0. "ASTC_MULTICYCLE_TF_FORCE_F16,When set ASTC encoded texels that are filtered over multiple cycles by the TF will be output from the MADD as F16." "0,1" rgroup.quad 0x1800++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_TPU_CEM_VDM,Global control to CEM textures for vertex data master" hexmask.quad 0x0 8.--63. 1. "RESERVED_8," newline bitfld.quad 0x0 7. "TAG_CEM_64_FACE_PACKING,Vertex data master. Enable 64-byte alignment between CEM faces when set to 1. It applies for both when mipmap is enabled or disabled" "0,1" newline rbitfld.quad 0x0 6. "RESERVED_6," "0,1" newline bitfld.quad 0x0 5. "TAG_CEM_4K_FACE_PACKING,Vertex data master. Enable 4K-byte alignment between CEM faces when set to 1. It applies for both when mipmap is enabled or disabled" "0,1" newline rbitfld.quad 0x0 4. "RESERVED_4," "0,1" newline bitfld.quad 0x0 3. "TAG_CEM_FACE_PACKING,Vertex data master. Enable dword alignment between CEM faces when set to 1" "0,1" newline bitfld.quad 0x0 2. "TAG_CEMEDGE_DONTFILTER,Vertex data master. Disable filtering over edges/corners for CEM. When set to 1 HW will be seemfull ie always stay in the current map always.." "0,1" newline bitfld.quad 0x0 1. "TAG_CEMGRAD_DONTNEGATE,Vertex data master. Disable negation for user supplied gradients for cem swap i. e. will only swap dudx etc not negate" "0,1" newline rbitfld.quad 0x0 0. "RESERVED_0," "0,1" rgroup.quad 0x1810++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_TPU_CEM_CDM,Global control to CEM textures for compute data master" hexmask.quad 0x0 8.--63. 1. "RESERVED_8," newline bitfld.quad 0x0 7. "TAG_CEM_64_FACE_PACKING,Compute data master. Enable 64-byte alignment between CEM faces when set to 1. It applies for both when mipmap is enabled or disabled" "0,1" newline rbitfld.quad 0x0 6. "RESERVED_6," "0,1" newline bitfld.quad 0x0 5. "TAG_CEM_4K_FACE_PACKING,Compute data master. Enable 4K-byte alignment between CEM faces when set to 1. It applies for both when mipmap is enabled or disabled" "0,1" newline rbitfld.quad 0x0 4. "RESERVED_4," "0,1" newline bitfld.quad 0x0 3. "TAG_CEM_FACE_PACKING,Compute data master. Enable dword alignment between CEM faces when set to 1" "0,1" newline bitfld.quad 0x0 2. "TAG_CEMEDGE_DONTFILTER,Compute data master. Disable filtering over edges/corners for CEM. When set to 1 HW will be seemfull ie always stay in the current map always.." "0,1" newline bitfld.quad 0x0 1. "TAG_CEMGRAD_DONTNEGATE,Compute data master. Disable negation for user supplied gradients for cem swap i. e. will only swap dudx etc not negate" "0,1" newline rbitfld.quad 0x0 0. "RESERVED_0," "0,1" rgroup.quad 0x1850++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_TPU_TAG_VDM_CTRL,Global control to TAG for the vertex data master" hexmask.quad 0x0 4.--63. 1. "RESERVED_4," newline bitfld.quad 0x0 3. "AF_RATIO_TRUNCATE_TO_INTEGER,0 current mode 1 clear the fractional part of the calculated AF ratio" "0,1" newline bitfld.quad 0x0 2. "AF_RATIO_TRUNCATE_TO_HALF,0 current mode 1 truncate the fractional part of the calculated AF ratio to 0. 5" "0,1" newline bitfld.quad 0x0 1. "AF_FILTERING_MODE,0 current mode 1 new mode." "0,1" newline bitfld.quad 0x0 0. "YUV_CAM_INVALIDATE,When set will invalidate YUV CSC CAM to reset the CSC coefficients. It should be set when the TPU is not performing CSC." "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_TPU_TAG_CDM_CTRL,Global control to TAG for the compute data master" hexmask.quad 0x8 4.--63. 1. "RESERVED_4," newline bitfld.quad 0x8 3. "AF_RATIO_TRUNCATE_TO_INTEGER,0 current mode 1 clear the fractional part of the calculated AF ratio" "0,1" newline bitfld.quad 0x8 2. "AF_RATIO_TRUNCATE_TO_HALF,0 current mode 1 truncate the fractional part of the calculated AF ratio to 0. 5" "0,1" newline bitfld.quad 0x8 1. "AF_FILTERING_MODE,0 current mode 1 new mode." "0,1" newline bitfld.quad 0x8 0. "YUV_CAM_INVALIDATE,When set will invalidate YUV CSC CAM to reset the CSC coefficients. It should be set when the TPU is not performing CSC." "0,1" rgroup.quad 0x1870++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_TPU_VDM_YUV_CSC_COEFFICIENTS,Base address for the YUV CSC set of coefficients stored in memory for the compute data master" hexmask.quad.long 0x0 38.--63. 1. "RESERVED_38," newline hexmask.quad 0x0 0.--37. 1. "YUV_CSC_COEFFICIENTS_ADDRESS,Base address DWORD aligned for the location in memory of the CSC coefficients" line.quad 0x8 "CORE_MMRS_RGX_CR_TPU_CDM_YUV_CSC_COEFFICIENTS,Base address for the YUV CSC set of coefficients stored in memory for the compute data master" hexmask.quad.long 0x8 38.--63. 1. "RESERVED_38," newline hexmask.quad 0x8 0.--37. 1. "YUV_CSC_COEFFICIENTS_ADDRESS,Base address DWORD aligned for the location in memory of the CSC coefficients" rgroup.quad 0x18C0++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_PDM,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the pixel data master" hexmask.quad 0x0 23.--63. 1. "RESERVED_23," newline hexmask.quad.tbyte 0x0 0.--22. 1. "LODBIASREP_CMP_MANTISSA_MASK,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup" line.quad 0x8 "CORE_MMRS_RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_VDM,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the vertex data master" hexmask.quad 0x8 23.--63. 1. "RESERVED_23," newline hexmask.quad.tbyte 0x8 0.--22. 1. "LODBIASREP_CMP_MANTISSA_MASK,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup" line.quad 0x10 "CORE_MMRS_RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_CDM,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the compute data master" hexmask.quad 0x10 23.--63. 1. "RESERVED_23," newline hexmask.quad.tbyte 0x10 0.--22. 1. "LODBIASREP_CMP_MANTISSA_MASK,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup" rgroup.quad 0x18E8++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_TPU_TAG_LOD_TRI_FRAC_MASK,Mask to enable/disable and set accuracy of Trilinear performance optimisation." hexmask.quad 0x0 4.--63. 1. "RESERVED_4," newline hexmask.quad.byte 0x0 0.--3. 1. "TAG_LOD_TRI_FRAC_MASK,Mask to enable/disable and set accuracy of Trilinear performance optimisation. Mask bit 1 => corresponding trilinear fraction LSB rounding enabled 0 => disabled. Only 4 LSBs.." line.quad 0x8 "CORE_MMRS_RGX_CR_TPU_TAG_LOD_TRI_FRAC_MASK_VDM,Mask to enable/disable and set accuracy of Trilinear performance optimisation." hexmask.quad 0x8 4.--63. 1. "RESERVED_4," newline hexmask.quad.byte 0x8 0.--3. 1. "TAG_LOD_TRI_FRAC_MASK,Mask to enable/disable and set accuracy of Trilinear performance optimisation. Mask bit 1 => corresponding trilinear fraction LSB rounding enabled 0 => disabled. Only 4 LSBs.." line.quad 0x10 "CORE_MMRS_RGX_CR_TPU_TAG_LOD_TRI_FRAC_MASK_CDM,Mask to enable/disable and set accuracy of Trilinear performance optimisation." hexmask.quad 0x10 4.--63. 1. "RESERVED_4," newline hexmask.quad.byte 0x10 0.--3. 1. "TAG_LOD_TRI_FRAC_MASK,Mask to enable/disable and set accuracy of Trilinear performance optimisation. Mask bit 1 => corresponding trilinear fraction LSB rounding enabled 0 => disabled. Only 4 LSBs.." rgroup.quad 0x1A00++0x9F line.quad 0x0 "CORE_MMRS_RGX_CR_SCRATCH0,Internal 'scratch' register for debug use by the firmware." hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "DATA," line.quad 0x8 "CORE_MMRS_RGX_CR_SCRATCH1,Internal 'scratch' register for debug use by the firmware." hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "DATA," line.quad 0x10 "CORE_MMRS_RGX_CR_SCRATCH2,Internal 'scratch' register for debug use by the firmware." hexmask.quad.long 0x10 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x10 0.--31. 1. "DATA," line.quad 0x18 "CORE_MMRS_RGX_CR_SCRATCH3,Internal 'scratch' register for debug use by the firmware." hexmask.quad.long 0x18 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x18 0.--31. 1. "DATA," line.quad 0x20 "CORE_MMRS_RGX_CR_SCRATCH4,Internal 'scratch' register for debug use by the firmware." hexmask.quad.long 0x20 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x20 0.--31. 1. "DATA," line.quad 0x28 "CORE_MMRS_RGX_CR_SCRATCH5,Internal 'scratch' register for debug use by the firmware." hexmask.quad.long 0x28 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x28 0.--31. 1. "DATA," line.quad 0x30 "CORE_MMRS_RGX_CR_SCRATCH6,Internal 'scratch' register for debug use by the firmware." hexmask.quad.long 0x30 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x30 0.--31. 1. "DATA," line.quad 0x38 "CORE_MMRS_RGX_CR_SCRATCH7,Internal 'scratch' register for debug use by the firmware." hexmask.quad.long 0x38 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x38 0.--31. 1. "DATA," line.quad 0x40 "CORE_MMRS_RGX_CR_SCRATCH8,Internal 'scratch' register for debug use by the firmware." hexmask.quad.long 0x40 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x40 0.--31. 1. "DATA," line.quad 0x48 "CORE_MMRS_RGX_CR_SCRATCH9,Internal 'scratch' register for debug use by the firmware." hexmask.quad.long 0x48 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x48 0.--31. 1. "DATA," line.quad 0x50 "CORE_MMRS_RGX_CR_SCRATCH10,Internal 'scratch' register for debug use by the firmware." hexmask.quad.long 0x50 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x50 0.--31. 1. "DATA," line.quad 0x58 "CORE_MMRS_RGX_CR_SCRATCH11,Internal 'scratch' register for debug use by the firmware." hexmask.quad.long 0x58 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x58 0.--31. 1. "DATA," line.quad 0x60 "CORE_MMRS_RGX_CR_SCRATCH12,Internal 'scratch' register for debug use by the firmware." hexmask.quad.long 0x60 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x60 0.--31. 1. "DATA," line.quad 0x68 "CORE_MMRS_RGX_CR_SCRATCH13,Internal 'scratch' register for debug use by the firmware." hexmask.quad.long 0x68 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x68 0.--31. 1. "DATA," line.quad 0x70 "CORE_MMRS_RGX_CR_SCRATCH14,Internal 'scratch' register for debug use by the firmware." hexmask.quad.long 0x70 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x70 0.--31. 1. "DATA," line.quad 0x78 "CORE_MMRS_RGX_CR_SCRATCH15,Internal 'scratch' register for debug use by the firmware." hexmask.quad.long 0x78 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x78 0.--31. 1. "DATA," line.quad 0x80 "CORE_MMRS_RGX_CR_OS0_SCRATCH0," hexmask.quad.long 0x80 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x80 0.--31. 1. "DATA," line.quad 0x88 "CORE_MMRS_RGX_CR_OS0_SCRATCH1," hexmask.quad.long 0x88 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x88 0.--31. 1. "DATA," line.quad 0x90 "CORE_MMRS_RGX_CR_OS0_SCRATCH2," hexmask.quad 0x90 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x90 0.--7. 1. "DATA," line.quad 0x98 "CORE_MMRS_RGX_CR_OS0_SCRATCH3," hexmask.quad 0x98 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x98 0.--7. 1. "DATA," rgroup.quad 0x2000++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_PM_TA_MMUPAGE_STATUS," hexmask.quad 0x0 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x0 0.--21. 1. "OP,MMU pages[4KB] counter @ the TA context" line.quad 0x8 "CORE_MMRS_RGX_CR_PM_3D_MMUPAGE_STATUS," hexmask.quad 0x8 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x8 0.--21. 1. "OP,MMU pages[4KB] counter @ the 3D context" rgroup.quad 0x2010++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_PM_MMU_STACK_POLICY,This register enables the PM to drain pages for MMU from the dedicated mmu free list stack." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "OP,when this bit is '1' PM will try to drain pages from the dedicated mmu free list stack" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_PM_TA_MMU_FSTACK_BASE,Effective on loading of the MMU TA free list loading . this register defines the base address of the mmu free list stack being referenced during TA processing." hexmask.quad.tbyte 0x8 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x8 4.--39. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for MMU TA free list stack" newline hexmask.quad.byte 0x8 0.--3. 1. "RESERVED_0," rgroup.quad 0x2020++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_TA_MMU_FSTACK_STATUS,Note: this is the pointer pointing to the MMU TA free stack top." hexmask.quad 0x0 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the mmu ta context free list pointer status." rgroup.quad 0x2028++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_PM_TA_MMU_FSTACK,Defines the start of the stack pointer regarding to the MMU free list stack" hexmask.quad 0x0 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x0 0.--21. 1. "STARTOF_TOP,This register defines the head pointer of the mmu free list in terms of 4K free pages in the free list stack effective on a loading of the MMU TA free list" line.quad 0x8 "CORE_MMRS_RGX_CR_PM_START_OF_MMU_TACONTEXT," hexmask.quad 0x8 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x8 0.--21. 1. "ALLOCATED_MMUPAGE,Start of MMU Freelists TA pages[4KB] on loading of the MMU TA context" line.quad 0x10 "CORE_MMRS_RGX_CR_PM_TASK_TA_MMU_FSTACK_FREE_LOAD," hexmask.quad 0x10 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x10 0. "PENDING,A write into this register will cause the TA MMU free list context to be loaded from the relevant configuration registers" "0,1" line.quad 0x18 "CORE_MMRS_RGX_CR_PM_3D_MMU_FSTACK_BASE,Effective on loading of the MMU 3D free list loading . this register defines the base address of the mmu free list stack" hexmask.quad.tbyte 0x18 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x18 4.--39. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for MMU TA free list stack" newline hexmask.quad.byte 0x18 0.--3. 1. "RESERVED_0," rgroup.quad 0x2048++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_3D_MMU_FSTACK_STATUS,Note: this is the pointer pointing to the MMU TA free stack top." hexmask.quad 0x0 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the mmu ta context free list pointer status." rgroup.quad 0x2050++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_3D_MMU_FSTACK,Defines the start of the stack pointer regarding to the MMU free list stack" hexmask.quad 0x0 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x0 0.--21. 1. "STARTOF_TOP,This register defines the head pointer of the mmu free list in terms of 4K free pages in the free list stack effective on a loading of the MMU TA free list" line.quad 0x8 "CORE_MMRS_RGX_CR_PM_START_OF_MMU_3DCONTEXT,Effective on a 3D MMU fstack load" hexmask.quad 0x8 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x8 0.--21. 1. "ALLOCATED_MMUPAGE,Start of MMU Freelists 3D pages[4KB] on loading of the MMU TA context" line.quad 0x10 "CORE_MMRS_RGX_CR_PM_TASK_3D_MMU_FSTACK_FREE_LOAD," hexmask.quad 0x10 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x10 0. "PENDING,A write into this register will cause the 3D MMU free list context to be loaded from the relevant configuration registers" "0,1" rgroup.quad 0x2068++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_PM_MMUSTACK_LOCK_STATUS," hexmask.quad 0x0 2.--63. 1. "RESERVED_2," newline bitfld.quad 0x0 1. "TD,Bit 1: 3D MMU free list Lock Status. 0 idle/ 1 used" "0,1" newline bitfld.quad 0x0 0. "TA,Bit 0: TA MMU free list Lock Status. 0 idle/ 1 used." "0: TA MMU free list Lock Status,?" line.quad 0x8 "CORE_MMRS_RGX_CR_PM_MMUSTACK_LOCK_OWNER," hexmask.quad 0x8 2.--63. 1. "RESERVED_2," newline bitfld.quad 0x8 1. "TD,Bit 1 :3D free list Lock owner. 0 PMA / 1 PMD" "0,1" newline bitfld.quad 0x8 0. "TA,Bit 0: TA free list Lock Owner. 0 PMA / 1 PMD." "0: TA free list Lock Owner,?" rgroup.quad 0x2078++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_PM_3D_UFSTACK_BASE,Effective on load of the Unified Free List Stack. this register defines the base address of the unified free list stack being referenced." hexmask.quad.tbyte 0x0 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x0 4.--39. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for unified free list stack base address" newline hexmask.quad.byte 0x0 0.--3. 1. "RESERVED_0," line.quad 0x8 "CORE_MMRS_RGX_CR_PM_3D_UFSTACK,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned" hexmask.quad 0x8 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x8 0.--21. 1. "STARTOF_TOP,This register defines the unified free list stack pointer @ loading time. It is 4K page." rgroup.quad 0x2088++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_3D_UFSTACK_STATUS,Note: this is the pointer pointing to the ufstack top. (4KB page pointer)" hexmask.quad 0x0 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the unified free list stack pointer status." rgroup.quad 0x2090++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_START_OF_3D_UFSTACK,Effective on load of the Unified Free List Stack." hexmask.quad.word 0x0 54.--63. 1. "RESERVED_54," newline hexmask.quad.tbyte 0x0 32.--53. 1. "ALLOCATED_MMUPAGE,Start of MMU Pages allocated from the Unifed Free List Stack On Loading" newline hexmask.quad.word 0x0 22.--31. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x0 0.--21. 1. "ALLOCATED_PAGE,Start of TA pages[4KB] on loading of the Unified Free List Stack" rgroup.quad 0x2098++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_PM_3D_UFSTACK_PAGE_STATUS," hexmask.quad 0x0 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x0 0.--21. 1. "OP,The number of Unified Free list pages currently allocated for the TA" line.quad 0x8 "CORE_MMRS_RGX_CR_PM_3D_UFSTACK_MMUPAGE_STATUS," hexmask.quad 0x8 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x8 0.--21. 1. "OP,The number of Unified Free list pages currently allocated for the MMU" line.quad 0x10 "CORE_MMRS_RGX_CR_PM_TASK_3D_UFSTACK_LOAD," hexmask.quad 0x10 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x10 0. "PENDING,pending status register corresponding to the ustack loading operation it will become '1' when this pm_task_ufstack_load being written and deassert until the operation is done" "0,1" line.quad 0x18 "CORE_MMRS_RGX_CR_PM_TASK_TA_UFSTACK_LOAD," hexmask.quad 0x18 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x18 0. "PENDING,pending status register corresponding to the ustack loading operation it will become '1' when this pm_task_ufstack_load being written and deassert until the operation is done" "0,1" rgroup.quad 0x20B8++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_PM_TA_UFSTACK_BASE,Effective on load of the Unified Free List Stack. this register defines the base address of the unified free list stack being referenced." hexmask.quad.tbyte 0x0 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x0 4.--39. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for unified free list stack base address" newline hexmask.quad.byte 0x0 0.--3. 1. "RESERVED_0," line.quad 0x8 "CORE_MMRS_RGX_CR_PM_TA_UFSTACK,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned" hexmask.quad 0x8 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x8 0.--21. 1. "STARTOF_TOP,This register defines the unified free list stack pointer @ loading time. It is 4K page." rgroup.quad 0x20C8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_TA_UFSTACK_STATUS,Note: this is the pointer pointing to the ufstack top. (4KB page pointer)" hexmask.quad 0x0 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the unified free list stack pointer status." rgroup.quad 0x20D0++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PM_START_OF_TA_UFSTACK," hexmask.quad.word 0x0 54.--63. 1. "RESERVED_54," newline hexmask.quad.tbyte 0x0 32.--53. 1. "ALLOCATED_MMUPAGE,Start of MMU Pages allocated from the Unifed Free List Stack On Loading" newline hexmask.quad.word 0x0 22.--31. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x0 0.--21. 1. "ALLOCATED_PAGE,Start of TA pages[4KB] on loading of the Unified Free List Stack" rgroup.quad 0x20D8++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_PM_TA_UFSTACK_PAGE_STATUS," hexmask.quad 0x0 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x0 0.--21. 1. "OP,The number of Unified Free list pages currently allocated for the TA" line.quad 0x8 "CORE_MMRS_RGX_CR_PM_TA_UFSTACK_MMUPAGE_STATUS," hexmask.quad 0x8 22.--63. 1. "RESERVED_22," newline hexmask.quad.tbyte 0x8 0.--21. 1. "OP,The number of Unified Free list pages currently allocated for the MMU" line.quad 0x10 "CORE_MMRS_RGX_CR_PM_UFSTACK_LOCK_STATUS,In rogue architecture. there is a unified free list whereby shared across multiple context." hexmask.quad 0x10 2.--63. 1. "RESERVED_2," newline bitfld.quad 0x10 1. "PMD,Bit 1: Page DeAllocation Manger is grabing the lock. 0:idle/ 1 used." "0: idle/ 1 used,1: Page DeAllocation Manger is grabing the lock" newline bitfld.quad 0x10 0. "PMA,Bit 0: Page Allocation Manger is grabing the lock. 0:idle/ 1 used." "0: idle/ 1 used,?" line.quad 0x18 "CORE_MMRS_RGX_CR_PM_UFSTACK_LOCK_OWNER," hexmask.quad 0x18 2.--63. 1. "RESERVED_2," newline bitfld.quad 0x18 1. "TD,Bit 1 :3D free list Lock owner. 0 PMA / 1 PMD" "0,1" newline bitfld.quad 0x18 0. "TA,Bit 0: TA free list Lock Owner. 0 PMA / 1 PMD." "0: TA free list Lock Owner,?" rgroup.quad 0x20F8++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_PM_UFSTACK_POLICY,This register enables the PM to drain pages from the unified free list stack" hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "OP,when this bit is '1' PM will try to drain pages from the unified free list stack as long as the ta free list do not have enough pages for the allocation" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_PM_VFP_TRAN_EN,This register enables the PM to another level of transfrom which is from Virtial Page to VirtualPhysical Page number" hexmask.quad 0x8 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x8 0. "OP,when this bit is '1' PM will try to another level of lookup between virtual page and the virtual physical page" "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_PM_TA_VFP_TABLE_BASE,Effective on loading TA context. this register defines the base address of the virtual-physical page table during TA processing." hexmask.quad.tbyte 0x10 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x10 4.--39. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for TA context page tables in the DPM module" newline hexmask.quad.byte 0x10 0.--3. 1. "RESERVED_0," line.quad 0x18 "CORE_MMRS_RGX_CR_PM_3D_VFP_TABLE_BASE,Effective on loading 3D context. this register defines the base address of the virtual-physical page table during 3D processing." hexmask.quad.tbyte 0x18 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x18 4.--39. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for 3D context page tables in the DPM module" newline hexmask.quad.byte 0x18 0.--3. 1. "RESERVED_0," rgroup.quad 0x3000++0x7F line.quad 0x0 "CORE_MMRS_RGX_CR_FWCORE_ADDR_REMAP_CONFIG0,Override swerv memory access for this region" rbitfld.quad 0x0 63. "RESERVED_63," "0,1" newline bitfld.quad 0x0 62. "TRUSTED,Set whether accesses in the this region are trusted" "0,1" newline bitfld.quad 0x0 61. "LOAD_STORE_EN,Region enabled for loads/stores" "0,1" newline bitfld.quad 0x0 60. "FETCH_EN,Region enabled for instruction fetches" "0,1" newline hexmask.quad.word 0x0 44.--59. 1. "SIZE,Region mapped window size" newline rbitfld.quad 0x0 43. "RESERVED_43," "0,1" newline bitfld.quad 0x0 40.--42. "CBASE,MMU catalogue base index. Indices 0-7 are supported" "0,1,2,3,4,5,6,7" newline hexmask.quad.long 0x0 12.--39. 1. "DEVVADDR,Base output address [4k aligned]" newline hexmask.quad.word 0x0 0.--11. 1. "RESERVED_0," line.quad 0x8 "CORE_MMRS_RGX_CR_FWCORE_ADDR_REMAP_CONFIG1,Override swerv memory access for this region" rbitfld.quad 0x8 63. "RESERVED_63," "0,1" newline bitfld.quad 0x8 62. "TRUSTED,Set whether accesses in the this region are trusted" "0,1" newline bitfld.quad 0x8 61. "LOAD_STORE_EN,Region enabled for loads/stores" "0,1" newline bitfld.quad 0x8 60. "FETCH_EN,Region enabled for instruction fetches" "0,1" newline hexmask.quad.word 0x8 44.--59. 1. "SIZE,Region mapped window size" newline rbitfld.quad 0x8 43. "RESERVED_43," "0,1" newline bitfld.quad 0x8 40.--42. "CBASE,MMU catalogue base index. Indices 0-7 are supported" "0,1,2,3,4,5,6,7" newline hexmask.quad.long 0x8 12.--39. 1. "DEVVADDR,Base output address [4k aligned]" newline hexmask.quad.word 0x8 0.--11. 1. "RESERVED_0," line.quad 0x10 "CORE_MMRS_RGX_CR_FWCORE_ADDR_REMAP_CONFIG2,Override swerv memory access for this region" rbitfld.quad 0x10 63. "RESERVED_63," "0,1" newline bitfld.quad 0x10 62. "TRUSTED,Set whether accesses in the this region are trusted" "0,1" newline bitfld.quad 0x10 61. "LOAD_STORE_EN,Region enabled for loads/stores" "0,1" newline bitfld.quad 0x10 60. "FETCH_EN,Region enabled for instruction fetches" "0,1" newline hexmask.quad.word 0x10 44.--59. 1. "SIZE,Region mapped window size" newline rbitfld.quad 0x10 43. "RESERVED_43," "0,1" newline bitfld.quad 0x10 40.--42. "CBASE,MMU catalogue base index. Indices 0-7 are supported" "0,1,2,3,4,5,6,7" newline hexmask.quad.long 0x10 12.--39. 1. "DEVVADDR,Base output address [4k aligned]" newline hexmask.quad.word 0x10 0.--11. 1. "RESERVED_0," line.quad 0x18 "CORE_MMRS_RGX_CR_FWCORE_ADDR_REMAP_CONFIG3,Override swerv memory access for this region" rbitfld.quad 0x18 63. "RESERVED_63," "0,1" newline bitfld.quad 0x18 62. "TRUSTED,Set whether accesses in the this region are trusted" "0,1" newline bitfld.quad 0x18 61. "LOAD_STORE_EN,Region enabled for loads/stores" "0,1" newline bitfld.quad 0x18 60. "FETCH_EN,Region enabled for instruction fetches" "0,1" newline hexmask.quad.word 0x18 44.--59. 1. "SIZE,Region mapped window size" newline rbitfld.quad 0x18 43. "RESERVED_43," "0,1" newline bitfld.quad 0x18 40.--42. "CBASE,MMU catalogue base index. Indices 0-7 are supported" "0,1,2,3,4,5,6,7" newline hexmask.quad.long 0x18 12.--39. 1. "DEVVADDR,Base output address [4k aligned]" newline hexmask.quad.word 0x18 0.--11. 1. "RESERVED_0," line.quad 0x20 "CORE_MMRS_RGX_CR_FWCORE_ADDR_REMAP_CONFIG4,Override swerv memory access for this region" rbitfld.quad 0x20 63. "RESERVED_63," "0,1" newline bitfld.quad 0x20 62. "TRUSTED,Set whether accesses in the this region are trusted" "0,1" newline bitfld.quad 0x20 61. "LOAD_STORE_EN,Region enabled for loads/stores" "0,1" newline bitfld.quad 0x20 60. "FETCH_EN,Region enabled for instruction fetches" "0,1" newline hexmask.quad.word 0x20 44.--59. 1. "SIZE,Region mapped window size" newline rbitfld.quad 0x20 43. "RESERVED_43," "0,1" newline bitfld.quad 0x20 40.--42. "CBASE,MMU catalogue base index. Indices 0-7 are supported" "0,1,2,3,4,5,6,7" newline hexmask.quad.long 0x20 12.--39. 1. "DEVVADDR,Base output address [4k aligned]" newline hexmask.quad.word 0x20 0.--11. 1. "RESERVED_0," line.quad 0x28 "CORE_MMRS_RGX_CR_FWCORE_ADDR_REMAP_CONFIG5,Override swerv memory access for this region" rbitfld.quad 0x28 63. "RESERVED_63," "0,1" newline bitfld.quad 0x28 62. "TRUSTED,Set whether accesses in the this region are trusted" "0,1" newline bitfld.quad 0x28 61. "LOAD_STORE_EN,Region enabled for loads/stores" "0,1" newline bitfld.quad 0x28 60. "FETCH_EN,Region enabled for instruction fetches" "0,1" newline hexmask.quad.word 0x28 44.--59. 1. "SIZE,Region mapped window size" newline rbitfld.quad 0x28 43. "RESERVED_43," "0,1" newline bitfld.quad 0x28 40.--42. "CBASE,MMU catalogue base index. Indices 0-7 are supported" "0,1,2,3,4,5,6,7" newline hexmask.quad.long 0x28 12.--39. 1. "DEVVADDR,Base output address [4k aligned]" newline hexmask.quad.word 0x28 0.--11. 1. "RESERVED_0," line.quad 0x30 "CORE_MMRS_RGX_CR_FWCORE_ADDR_REMAP_CONFIG6,Override swerv memory access for this region" rbitfld.quad 0x30 63. "RESERVED_63," "0,1" newline bitfld.quad 0x30 62. "TRUSTED,Set whether accesses in the this region are trusted" "0,1" newline bitfld.quad 0x30 61. "LOAD_STORE_EN,Region enabled for loads/stores" "0,1" newline bitfld.quad 0x30 60. "FETCH_EN,Region enabled for instruction fetches" "0,1" newline hexmask.quad.word 0x30 44.--59. 1. "SIZE,Region mapped window size" newline rbitfld.quad 0x30 43. "RESERVED_43," "0,1" newline bitfld.quad 0x30 40.--42. "CBASE,MMU catalogue base index. Indices 0-7 are supported" "0,1,2,3,4,5,6,7" newline hexmask.quad.long 0x30 12.--39. 1. "DEVVADDR,Base output address [4k aligned]" newline hexmask.quad.word 0x30 0.--11. 1. "RESERVED_0," line.quad 0x38 "CORE_MMRS_RGX_CR_FWCORE_ADDR_REMAP_CONFIG7,Override swerv memory access for this region" rbitfld.quad 0x38 63. "RESERVED_63," "0,1" newline bitfld.quad 0x38 62. "TRUSTED,Set whether accesses in the this region are trusted" "0,1" newline bitfld.quad 0x38 61. "LOAD_STORE_EN,Region enabled for loads/stores" "0,1" newline bitfld.quad 0x38 60. "FETCH_EN,Region enabled for instruction fetches" "0,1" newline hexmask.quad.word 0x38 44.--59. 1. "SIZE,Region mapped window size" newline rbitfld.quad 0x38 43. "RESERVED_43," "0,1" newline bitfld.quad 0x38 40.--42. "CBASE,MMU catalogue base index. Indices 0-7 are supported" "0,1,2,3,4,5,6,7" newline hexmask.quad.long 0x38 12.--39. 1. "DEVVADDR,Base output address [4k aligned]" newline hexmask.quad.word 0x38 0.--11. 1. "RESERVED_0," line.quad 0x40 "CORE_MMRS_RGX_CR_FWCORE_ADDR_REMAP_CONFIG8,Override swerv memory access for this region" rbitfld.quad 0x40 63. "RESERVED_63," "0,1" newline bitfld.quad 0x40 62. "TRUSTED,Set whether accesses in the this region are trusted" "0,1" newline bitfld.quad 0x40 61. "LOAD_STORE_EN,Region enabled for loads/stores" "0,1" newline bitfld.quad 0x40 60. "FETCH_EN,Region enabled for instruction fetches" "0,1" newline hexmask.quad.word 0x40 44.--59. 1. "SIZE,Region mapped window size" newline rbitfld.quad 0x40 43. "RESERVED_43," "0,1" newline bitfld.quad 0x40 40.--42. "CBASE,MMU catalogue base index. Indices 0-7 are supported" "0,1,2,3,4,5,6,7" newline hexmask.quad.long 0x40 12.--39. 1. "DEVVADDR,Base output address [4k aligned]" newline hexmask.quad.word 0x40 0.--11. 1. "RESERVED_0," line.quad 0x48 "CORE_MMRS_RGX_CR_FWCORE_ADDR_REMAP_CONFIG9,Override swerv memory access for this region" rbitfld.quad 0x48 63. "RESERVED_63," "0,1" newline bitfld.quad 0x48 62. "TRUSTED,Set whether accesses in the this region are trusted" "0,1" newline bitfld.quad 0x48 61. "LOAD_STORE_EN,Region enabled for loads/stores" "0,1" newline bitfld.quad 0x48 60. "FETCH_EN,Region enabled for instruction fetches" "0,1" newline hexmask.quad.word 0x48 44.--59. 1. "SIZE,Region mapped window size" newline rbitfld.quad 0x48 43. "RESERVED_43," "0,1" newline bitfld.quad 0x48 40.--42. "CBASE,MMU catalogue base index. Indices 0-7 are supported" "0,1,2,3,4,5,6,7" newline hexmask.quad.long 0x48 12.--39. 1. "DEVVADDR,Base output address [4k aligned]" newline hexmask.quad.word 0x48 0.--11. 1. "RESERVED_0," line.quad 0x50 "CORE_MMRS_RGX_CR_FWCORE_ADDR_REMAP_CONFIG10,Override swerv memory access for this region" rbitfld.quad 0x50 63. "RESERVED_63," "0,1" newline bitfld.quad 0x50 62. "TRUSTED,Set whether accesses in the this region are trusted" "0,1" newline bitfld.quad 0x50 61. "LOAD_STORE_EN,Region enabled for loads/stores" "0,1" newline bitfld.quad 0x50 60. "FETCH_EN,Region enabled for instruction fetches" "0,1" newline hexmask.quad.word 0x50 44.--59. 1. "SIZE,Region mapped window size" newline rbitfld.quad 0x50 43. "RESERVED_43," "0,1" newline bitfld.quad 0x50 40.--42. "CBASE,MMU catalogue base index. Indices 0-7 are supported" "0,1,2,3,4,5,6,7" newline hexmask.quad.long 0x50 12.--39. 1. "DEVVADDR,Base output address [4k aligned]" newline hexmask.quad.word 0x50 0.--11. 1. "RESERVED_0," line.quad 0x58 "CORE_MMRS_RGX_CR_FWCORE_ADDR_REMAP_CONFIG11,Override swerv memory access for this region" rbitfld.quad 0x58 63. "RESERVED_63," "0,1" newline bitfld.quad 0x58 62. "TRUSTED,Set whether accesses in the this region are trusted" "0,1" newline bitfld.quad 0x58 61. "LOAD_STORE_EN,Region enabled for loads/stores" "0,1" newline bitfld.quad 0x58 60. "FETCH_EN,Region enabled for instruction fetches" "0,1" newline hexmask.quad.word 0x58 44.--59. 1. "SIZE,Region mapped window size" newline rbitfld.quad 0x58 43. "RESERVED_43," "0,1" newline bitfld.quad 0x58 40.--42. "CBASE,MMU catalogue base index. Indices 0-7 are supported" "0,1,2,3,4,5,6,7" newline hexmask.quad.long 0x58 12.--39. 1. "DEVVADDR,Base output address [4k aligned]" newline hexmask.quad.word 0x58 0.--11. 1. "RESERVED_0," line.quad 0x60 "CORE_MMRS_RGX_CR_FWCORE_ADDR_REMAP_CONFIG12,Override swerv memory access for this region" rbitfld.quad 0x60 63. "RESERVED_63," "0,1" newline bitfld.quad 0x60 62. "TRUSTED,Set whether accesses in the this region are trusted" "0,1" newline bitfld.quad 0x60 61. "LOAD_STORE_EN,Region enabled for loads/stores" "0,1" newline bitfld.quad 0x60 60. "FETCH_EN,Region enabled for instruction fetches" "0,1" newline hexmask.quad.word 0x60 44.--59. 1. "SIZE,Region mapped window size" newline rbitfld.quad 0x60 43. "RESERVED_43," "0,1" newline bitfld.quad 0x60 40.--42. "CBASE,MMU catalogue base index. Indices 0-7 are supported" "0,1,2,3,4,5,6,7" newline hexmask.quad.long 0x60 12.--39. 1. "DEVVADDR,Base output address [4k aligned]" newline hexmask.quad.word 0x60 0.--11. 1. "RESERVED_0," line.quad 0x68 "CORE_MMRS_RGX_CR_FWCORE_ADDR_REMAP_CONFIG13,Override swerv memory access for this region" rbitfld.quad 0x68 63. "RESERVED_63," "0,1" newline bitfld.quad 0x68 62. "TRUSTED,Set whether accesses in the this region are trusted" "0,1" newline bitfld.quad 0x68 61. "LOAD_STORE_EN,Region enabled for loads/stores" "0,1" newline bitfld.quad 0x68 60. "FETCH_EN,Region enabled for instruction fetches" "0,1" newline hexmask.quad.word 0x68 44.--59. 1. "SIZE,Region mapped window size" newline rbitfld.quad 0x68 43. "RESERVED_43," "0,1" newline bitfld.quad 0x68 40.--42. "CBASE,MMU catalogue base index. Indices 0-7 are supported" "0,1,2,3,4,5,6,7" newline hexmask.quad.long 0x68 12.--39. 1. "DEVVADDR,Base output address [4k aligned]" newline hexmask.quad.word 0x68 0.--11. 1. "RESERVED_0," line.quad 0x70 "CORE_MMRS_RGX_CR_FWCORE_ADDR_REMAP_CONFIG14,Override swerv memory access for this region" rbitfld.quad 0x70 63. "RESERVED_63," "0,1" newline bitfld.quad 0x70 62. "TRUSTED,Set whether accesses in the this region are trusted" "0,1" newline bitfld.quad 0x70 61. "LOAD_STORE_EN,Region enabled for loads/stores" "0,1" newline bitfld.quad 0x70 60. "FETCH_EN,Region enabled for instruction fetches" "0,1" newline hexmask.quad.word 0x70 44.--59. 1. "SIZE,Region mapped window size" newline rbitfld.quad 0x70 43. "RESERVED_43," "0,1" newline bitfld.quad 0x70 40.--42. "CBASE,MMU catalogue base index. Indices 0-7 are supported" "0,1,2,3,4,5,6,7" newline hexmask.quad.long 0x70 12.--39. 1. "DEVVADDR,Base output address [4k aligned]" newline hexmask.quad.word 0x70 0.--11. 1. "RESERVED_0," line.quad 0x78 "CORE_MMRS_RGX_CR_FWCORE_ADDR_REMAP_CONFIG15,Override swerv memory access for this region" rbitfld.quad 0x78 63. "RESERVED_63," "0,1" newline bitfld.quad 0x78 62. "TRUSTED,Set whether accesses in the this region are trusted" "0,1" newline bitfld.quad 0x78 61. "LOAD_STORE_EN,Region enabled for loads/stores" "0,1" newline bitfld.quad 0x78 60. "FETCH_EN,Region enabled for instruction fetches" "0,1" newline hexmask.quad.word 0x78 44.--59. 1. "SIZE,Region mapped window size" newline rbitfld.quad 0x78 43. "RESERVED_43," "0,1" newline bitfld.quad 0x78 40.--42. "CBASE,MMU catalogue base index. Indices 0-7 are supported" "0,1,2,3,4,5,6,7" newline hexmask.quad.long 0x78 12.--39. 1. "DEVVADDR,Base output address [4k aligned]" newline hexmask.quad.word 0x78 0.--11. 1. "RESERVED_0," rgroup.quad 0x3090++0x27 line.quad 0x0 "CORE_MMRS_RGX_CR_FWCORE_BOOT,Boot the RISCV CPU" hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "ENABLE,Boot the RISCV CPU" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_FWCORE_RESET_ADDR,Swerv reset address" hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 1.--31. 1. "ADDR,Reset address for the core" newline rbitfld.quad 0x8 0. "RESERVED_0," "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_FWCORE_WRAPPER_NMI_ADDR,Non-Maskable Interrupt address" hexmask.quad.long 0x10 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x10 1.--31. 1. "ADDR,Non-Maskable Interrupt address" newline rbitfld.quad 0x10 0. "RESERVED_0," "0,1" line.quad 0x18 "CORE_MMRS_RGX_CR_FWCORE_WRAPPER_NMI_EVENT,Issue a Non-Maskable Interrupt to RISCV" hexmask.quad 0x18 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x18 0. "TRIGGER_EN,Issue a Non-Maskable Interrupt to RISCV" "0,1" line.quad 0x20 "CORE_MMRS_RGX_CR_FWCORE_MEM_FAULT_MMU_STATUS,Indicates a fault has occurred on the CPU MMU and provides details of the fault." hexmask.quad 0x20 16.--63. 1. "RESERVED_16," newline hexmask.quad.byte 0x20 12.--15. 1. "CAT_BASE,Catalogue base address number" newline rbitfld.quad 0x20 11. "RESERVED_11," "0,1" newline bitfld.quad 0x20 8.--10. "PAGE_SIZE,Page size" "0,1,2,3,4,5,6,7" newline rbitfld.quad 0x20 7. "RESERVED_7," "0,1" newline bitfld.quad 0x20 5.--6. "DATA_TYPE,MMU data type that was invalid [on valid fault]" "0,1,2,3" newline bitfld.quad 0x20 4. "FAULT_RO,Indicates read-only fault['1'] or valid fault['0']" "0,1" newline rbitfld.quad 0x20 1.--3. "RESERVED_1," "0,1,2,3,4,5,6,7" newline bitfld.quad 0x20 0. "FAULT,Indicates a fault has occured" "0,1" rgroup.quad 0x30B8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_FWCORE_MEM_FAULT_REQ_STATUS,Provides details of the request that faulted on the CPU MMU" hexmask.quad.word 0x0 53.--63. 1. "RESERVED_53," newline bitfld.quad 0x0 52. "RNW," "0,1" newline hexmask.quad.byte 0x0 46.--51. 1. "TAG_SB," newline hexmask.quad.byte 0x0 40.--45. 1. "TAG_ID," newline hexmask.quad 0x0 4.--39. 1. "ADDRESS," newline hexmask.quad.byte 0x0 0.--3. 1. "RESERVED_0," rgroup.quad 0x30C0++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_FWCORE_MEM_CTRL_INVAL,Invalidation bits allowing CPU BIF/MMU to clear when invalidation complete" hexmask.quad 0x0 4.--63. 1. "RESERVED_4," newline bitfld.quad 0x0 3. "TLB," "0,1" newline bitfld.quad 0x0 2. "PC," "0,1" newline bitfld.quad 0x0 1. "PD," "0,1" newline bitfld.quad 0x0 0. "PT," "0,1" rgroup.quad 0x30C8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_FWCORE_MEM_MMU_STATUS,General CPU MMU status" hexmask.quad 0x0 28.--63. 1. "RESERVED_28," newline hexmask.quad.byte 0x0 20.--27. 1. "PC_DATA," newline hexmask.quad.byte 0x0 12.--19. 1. "PD_DATA," newline hexmask.quad.byte 0x0 4.--11. 1. "PT_DATA," newline bitfld.quad 0x0 3. "RESERVED_3," "0,1" newline bitfld.quad 0x0 2. "STALLED," "0,1" newline bitfld.quad 0x0 1. "PAUSED," "0,1" newline bitfld.quad 0x0 0. "BUSY," "0,1" rgroup.quad 0x30D8++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_FWCORE_MEM_READS_EXT_STATUS,Outstanding read data external to CPU MMU" hexmask.quad 0x0 12.--63. 1. "RESERVED_12," newline hexmask.quad.word 0x0 0.--11. 1. "MMU," line.quad 0x8 "CORE_MMRS_RGX_CR_FWCORE_MEM_READS_INT_STATUS,Outstanding 256-bit read data in return data FIFO for CPU MMU" hexmask.quad 0x8 11.--63. 1. "RESERVED_11," newline hexmask.quad.word 0x8 0.--10. 1. "MMU," rgroup.quad 0x30E8++0x57 line.quad 0x0 "CORE_MMRS_RGX_CR_FWCORE_WRAPPER_FENCE,Writing to this register offset will cause the CPU wrapper to emit a write fence to memory." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "ID," "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_FWCORE_MEM_CAT_BASE0," hexmask.quad.tbyte 0x8 40.--63. 1. "RESERVED_40," newline hexmask.quad.long 0x8 12.--39. 1. "ADDR," newline hexmask.quad.word 0x8 0.--11. 1. "RESERVED_0," line.quad 0x10 "CORE_MMRS_RGX_CR_FWCORE_MEM_CAT_BASE1," hexmask.quad.tbyte 0x10 40.--63. 1. "RESERVED_40," newline hexmask.quad.long 0x10 12.--39. 1. "ADDR," newline hexmask.quad.word 0x10 0.--11. 1. "RESERVED_0," line.quad 0x18 "CORE_MMRS_RGX_CR_FWCORE_MEM_CAT_BASE2," hexmask.quad.tbyte 0x18 40.--63. 1. "RESERVED_40," newline hexmask.quad.long 0x18 12.--39. 1. "ADDR," newline hexmask.quad.word 0x18 0.--11. 1. "RESERVED_0," line.quad 0x20 "CORE_MMRS_RGX_CR_FWCORE_MEM_CAT_BASE3," hexmask.quad.tbyte 0x20 40.--63. 1. "RESERVED_40," newline hexmask.quad.long 0x20 12.--39. 1. "ADDR," newline hexmask.quad.word 0x20 0.--11. 1. "RESERVED_0," line.quad 0x28 "CORE_MMRS_RGX_CR_FWCORE_MEM_CAT_BASE4," hexmask.quad.tbyte 0x28 40.--63. 1. "RESERVED_40," newline hexmask.quad.long 0x28 12.--39. 1. "ADDR," newline hexmask.quad.word 0x28 0.--11. 1. "RESERVED_0," line.quad 0x30 "CORE_MMRS_RGX_CR_FWCORE_MEM_CAT_BASE5," hexmask.quad.tbyte 0x30 40.--63. 1. "RESERVED_40," newline hexmask.quad.long 0x30 12.--39. 1. "ADDR," newline hexmask.quad.word 0x30 0.--11. 1. "RESERVED_0," line.quad 0x38 "CORE_MMRS_RGX_CR_FWCORE_MEM_CAT_BASE6," hexmask.quad.tbyte 0x38 40.--63. 1. "RESERVED_40," newline hexmask.quad.long 0x38 12.--39. 1. "ADDR," newline hexmask.quad.word 0x38 0.--11. 1. "RESERVED_0," line.quad 0x40 "CORE_MMRS_RGX_CR_FWCORE_MEM_CAT_BASE7," hexmask.quad.tbyte 0x40 40.--63. 1. "RESERVED_40," newline hexmask.quad.long 0x40 12.--39. 1. "ADDR," newline hexmask.quad.word 0x40 0.--11. 1. "RESERVED_0," line.quad 0x48 "CORE_MMRS_RGX_CR_FWCORE_WDT_RESET,A '1' may be written to this register to reset the watchdog timer count." hexmask.quad 0x48 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x48 0. "EN," "0,1" line.quad 0x50 "CORE_MMRS_RGX_CR_FWCORE_WDT_CTRL,Watchdog timer control register." hexmask.quad.long 0x50 32.--63. 1. "RESERVED_32," newline hexmask.quad.word 0x50 16.--31. 1. "PROT,Writes to this register must set these bits to 0xABCD for the writes to THRESHOLD and ENABLE to take effect. These bits are read as 0x0000" newline rbitfld.quad 0x50 13.--15. "RESERVED_13," "0,1,2,3,4,5,6,7" newline hexmask.quad.byte 0x50 8.--12. 1. "THRESHOLD,Logarithmic threshold. When the counter bit indexed by the value in this field transitions from 0 to 1 the WDT module output pulse is asserted and the count is reset to 0." newline hexmask.quad.byte 0x50 1.--7. 1. "RESERVED_1," newline bitfld.quad 0x50 0. "ENABLE,'1' - WDT enabled. '0' - WDT disabled." "0,1" rgroup.quad 0x3140++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_FWCORE_WDT_COUNT,Read only register returns the current value of the watchdog timer count." hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "VALUE," rgroup.quad 0x3148++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_RISCV_MTIME_SET,Writing to this register updates the Timer counter. On the following ticks the counter will be incremented based on the newly written value." hexmask.quad 0x0 0.--63. 1. "VALUE," line.quad 0x8 "CORE_MMRS_RGX_CR_RISCV_MTIME_CMP,Writing to this register updates the Timer compare value and at the same time clears the sticky bit of the timer interrupt output." hexmask.quad 0x8 0.--63. 1. "VALUE," rgroup.quad 0x3158++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_RISCV_MTIME_STAT,Shows the momentary value of the 64 bit Timer counter." hexmask.quad 0x0 0.--63. 1. "VALUE," rgroup.quad 0x3160++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_RISCV_MTIME_CTRL,Control register." hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline bitfld.quad 0x0 31. "SOFT_RESET,When high the counter the MTIME_SET & MTIME_CMP registers and the sticky interrupt are all forced to zero" "0,1" newline hexmask.quad.long 0x0 2.--30. 1. "RESERVED_2," newline bitfld.quad 0x0 1. "PAUSE,When high the timer is not being incremented by tick pulses but can still be written using the MTIME_SET registers." "0,1" newline bitfld.quad 0x0 0. "ENABLE,When high the timer interrupt output is enabled. The counter itself is not affected by this bit." "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_FWCORE_IDLE,Top-level idle control register" hexmask.quad 0x8 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x8 0. "ENABLE,Set to 0x0 overwrites the value of GPU_IDLE to 0x0 set to 0x1 makes GPU Idle dependent on top level idles" "0,1" rgroup.quad 0x3400++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED00,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x0 0.--63. 1. "RESERVED_0," line.quad 0x8 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED01,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x8 0.--63. 1. "RESERVED_0," line.quad 0x10 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED02,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x10 0.--63. 1. "RESERVED_0," line.quad 0x18 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED03,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x18 0.--63. 1. "RESERVED_0," rgroup.quad 0x3420++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_FWCORE_DMI_DATA0,RISC-V Debug Module Interface - Basic read/write register that may be read or changed by abstract commands." hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "VAL," line.quad 0x8 "CORE_MMRS_RGX_CR_FWCORE_DMI_DATA1,RISC-V Debug Module Interface - Basic read/write register that may be read or changed by abstract commands." hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "VAL," rgroup.quad 0x3430++0x4F line.quad 0x0 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED10,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x0 0.--63. 1. "RESERVED_0," line.quad 0x8 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED11,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x8 0.--63. 1. "RESERVED_0," line.quad 0x10 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED12,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x10 0.--63. 1. "RESERVED_0," line.quad 0x18 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED13,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x18 0.--63. 1. "RESERVED_0," line.quad 0x20 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED14,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x20 0.--63. 1. "RESERVED_0," line.quad 0x28 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED15,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x28 0.--63. 1. "RESERVED_0," line.quad 0x30 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED16,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x30 0.--63. 1. "RESERVED_0," line.quad 0x38 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED17,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x38 0.--63. 1. "RESERVED_0," line.quad 0x40 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED18,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x40 0.--63. 1. "RESERVED_0," line.quad 0x48 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED19,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x48 0.--63. 1. "RESERVED_0," rgroup.quad 0x3480++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_FWCORE_DMI_DMCONTROL,RISC-V Debug Module Interface - This register controls the overall Debug Module as well as the currently selected harts." hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline bitfld.quad 0x0 31. "HALTREQ," "0,1" newline bitfld.quad 0x0 30. "RESUMEREQ," "0,1" newline rbitfld.quad 0x0 29. "RESERVED_29," "0,1" newline bitfld.quad 0x0 28. "ACKHAVERESET," "0,1" newline hexmask.quad.long 0x0 2.--27. 1. "RESERVED_2," newline bitfld.quad 0x0 1. "NDMRESET," "0,1" newline bitfld.quad 0x0 0. "DMACTIVE," "0,1" rgroup.quad 0x3488++0x27 line.quad 0x0 "CORE_MMRS_RGX_CR_FWCORE_DMI_DMSTATUS,RISC-V Debug Module Interface - This register reports status for the overall Debug Module as well as the currently selected harts." hexmask.quad 0x0 23.--63. 1. "RESERVED_23," newline bitfld.quad 0x0 22. "IMPEBREAK," "0,1" newline bitfld.quad 0x0 20.--21. "RESERVED_20," "0,1,2,3" newline bitfld.quad 0x0 19. "ALLHAVERESET," "0,1" newline bitfld.quad 0x0 18. "ANYHAVERESET," "0,1" newline bitfld.quad 0x0 17. "ALLRESUMEACK," "0,1" newline bitfld.quad 0x0 16. "ANYRESUMEACK," "0,1" newline bitfld.quad 0x0 15. "ALLNONEXISTENT," "0,1" newline bitfld.quad 0x0 14. "ANYNONEXISTENT," "0,1" newline bitfld.quad 0x0 13. "ALLUNAVAIL," "0,1" newline bitfld.quad 0x0 12. "ANYUNAVAIL," "0,1" newline bitfld.quad 0x0 11. "ALLRUNNING," "0,1" newline bitfld.quad 0x0 10. "ANYRUNNING," "0,1" newline bitfld.quad 0x0 9. "ALLHALTED," "0,1" newline bitfld.quad 0x0 8. "ANYHALTED," "0,1" newline bitfld.quad 0x0 7. "AUTHENTICATED," "0,1" newline bitfld.quad 0x0 6. "AUTHBUSY," "0,1" newline bitfld.quad 0x0 5. "HASRESETHALTREQ," "0,1" newline bitfld.quad 0x0 4. "CONFSTRPTRVALID," "0,1" newline hexmask.quad.byte 0x0 0.--3. 1. "VERSION," line.quad 0x8 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED20,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x8 0.--63. 1. "RESERVED_0," line.quad 0x10 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED21,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x10 0.--63. 1. "RESERVED_0," line.quad 0x18 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED22,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x18 0.--63. 1. "RESERVED_0," line.quad 0x20 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED23,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x20 0.--63. 1. "RESERVED_0," rgroup.quad 0x34B0++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_FWCORE_DMI_ABSTRACTCS,RISC-V Debug Module Interface - Abstract Control and Status" hexmask.quad 0x0 29.--63. 1. "RESERVED_29," newline hexmask.quad.byte 0x0 24.--28. 1. "PROGBUFSIZE," newline hexmask.quad.word 0x0 13.--23. 1. "RESERVED_13," newline bitfld.quad 0x0 12. "BUSY," "0,1" newline rbitfld.quad 0x0 11. "RESERVED_11," "0,1" newline bitfld.quad 0x0 8.--10. "CMDERR," "0,1,2,3,4,5,6,7" newline hexmask.quad.byte 0x0 4.--7. 1. "RESERVED_4," newline hexmask.quad.byte 0x0 0.--3. 1. "DATACOUNT," line.quad 0x8 "CORE_MMRS_RGX_CR_FWCORE_DMI_COMMAND,RISC-V Debug Module Interface - Abstract Command" hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.byte 0x8 24.--31. 1. "CMDTYPE," newline hexmask.quad.tbyte 0x8 0.--23. 1. "CONTROL," rgroup.quad 0x34C0++0xFF line.quad 0x0 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED30,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x0 0.--63. 1. "RESERVED_0," line.quad 0x8 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED31,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x8 0.--63. 1. "RESERVED_0," line.quad 0x10 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED32,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x10 0.--63. 1. "RESERVED_0," line.quad 0x18 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED33,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x18 0.--63. 1. "RESERVED_0," line.quad 0x20 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED34,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x20 0.--63. 1. "RESERVED_0," line.quad 0x28 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED35,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x28 0.--63. 1. "RESERVED_0," line.quad 0x30 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED36,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x30 0.--63. 1. "RESERVED_0," line.quad 0x38 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED37,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x38 0.--63. 1. "RESERVED_0," line.quad 0x40 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED38,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x40 0.--63. 1. "RESERVED_0," line.quad 0x48 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED39,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x48 0.--63. 1. "RESERVED_0," line.quad 0x50 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED310,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x50 0.--63. 1. "RESERVED_0," line.quad 0x58 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED311,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x58 0.--63. 1. "RESERVED_0," line.quad 0x60 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED312,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x60 0.--63. 1. "RESERVED_0," line.quad 0x68 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED313,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x68 0.--63. 1. "RESERVED_0," line.quad 0x70 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED314,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x70 0.--63. 1. "RESERVED_0," line.quad 0x78 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED315,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x78 0.--63. 1. "RESERVED_0," line.quad 0x80 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED316,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x80 0.--63. 1. "RESERVED_0," line.quad 0x88 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED317,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x88 0.--63. 1. "RESERVED_0," line.quad 0x90 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED318,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x90 0.--63. 1. "RESERVED_0," line.quad 0x98 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED319,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x98 0.--63. 1. "RESERVED_0," line.quad 0xA0 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED320,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0xA0 0.--63. 1. "RESERVED_0," line.quad 0xA8 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED321,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0xA8 0.--63. 1. "RESERVED_0," line.quad 0xB0 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED322,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0xB0 0.--63. 1. "RESERVED_0," line.quad 0xB8 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED323,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0xB8 0.--63. 1. "RESERVED_0," line.quad 0xC0 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED324,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0xC0 0.--63. 1. "RESERVED_0," line.quad 0xC8 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED325,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0xC8 0.--63. 1. "RESERVED_0," line.quad 0xD0 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED326,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0xD0 0.--63. 1. "RESERVED_0," line.quad 0xD8 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED327,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0xD8 0.--63. 1. "RESERVED_0," line.quad 0xE0 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED328,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0xE0 0.--63. 1. "RESERVED_0," line.quad 0xE8 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED329,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0xE8 0.--63. 1. "RESERVED_0," line.quad 0xF0 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED330,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0xF0 0.--63. 1. "RESERVED_0," line.quad 0xF8 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED331,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0xF8 0.--63. 1. "RESERVED_0," rgroup.quad 0x35C0++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_FWCORE_DMI_SBCS,RISC-V Debug Module Interface - System Bus Access Control and Status" hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline bitfld.quad 0x0 29.--31. "SBVERSION," "0,1,2,3,4,5,6,7" newline hexmask.quad.byte 0x0 23.--28. 1. "RESERVED_23," newline bitfld.quad 0x0 22. "SBBUSYERROR," "0,1" newline bitfld.quad 0x0 21. "SBBUSY," "0,1" newline bitfld.quad 0x0 20. "SBREADONADDR," "0,1" newline bitfld.quad 0x0 17.--19. "SBACCESS," "0,1,2,3,4,5,6,7" newline bitfld.quad 0x0 16. "SBAUTOINCREMENT," "0,1" newline bitfld.quad 0x0 15. "SBREADONDATA," "0,1" newline bitfld.quad 0x0 12.--14. "SBERROR," "0,1,2,3,4,5,6,7" newline hexmask.quad.byte 0x0 5.--11. 1. "SBASIZE," newline bitfld.quad 0x0 4. "SBACCESS128," "0,1" newline bitfld.quad 0x0 3. "SBACCESS64," "0,1" newline bitfld.quad 0x0 2. "SBACCESS32," "0,1" newline bitfld.quad 0x0 1. "SBACCESS16," "0,1" newline bitfld.quad 0x0 0. "SBACCESS8," "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_FWCORE_DMI_SBADDRESS0,RISC-V Debug Module Interface - System Bus Address" hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "ADDRESS," rgroup.quad 0x35D0++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED40,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x0 0.--63. 1. "RESERVED_0," line.quad 0x8 "CORE_MMRS_RGX_CR_FWCORE_DMI_RESERVED41,This address is mapped to the FW CPU debug port. Do not use" hexmask.quad 0x8 0.--63. 1. "RESERVED_0," rgroup.quad 0x35E0++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_FWCORE_DMI_SBDATA0,RISC-V Debug Module Interface - System Bus Data Words" hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "DATA," line.quad 0x8 "CORE_MMRS_RGX_CR_FWCORE_DMI_SBDATA1,RISC-V Debug Module Interface - System Bus Data Words" hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "DATA," line.quad 0x10 "CORE_MMRS_RGX_CR_FWCORE_DMI_SBDATA2,RISC-V Debug Module Interface - System Bus Data Words" hexmask.quad.long 0x10 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x10 0.--31. 1. "DATA," line.quad 0x18 "CORE_MMRS_RGX_CR_FWCORE_DMI_SBDATA3,RISC-V Debug Module Interface - System Bus Data Words" hexmask.quad.long 0x18 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x18 0.--31. 1. "DATA," rgroup.quad 0x3600++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_FWCORE_DMI_HALTSUM0,RISC-V Debug Module Interface - Halt Summary 0" hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "VAL," rgroup.quad 0x3800++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_SLC_CTRL_MISC,SLC control registers" hexmask.quad.long 0x0 32.--63. 1. "SCRAMBLE_BITS,Pattern of bits used to determine the Cache Bank in Address Decode mode 0x21. The actual Cache Bank to use is determined by indexing into the 32 Scramble Bits using the 5 LSB's of the Hash result and then XORing.." newline hexmask.quad.byte 0x0 26.--31. 1. "RESERVED_26," newline bitfld.quad 0x0 25. "TAG_ID_LIMIT_CONTROL,Controls the number of external memory tag IDs available to SLC" "0,1" newline bitfld.quad 0x0 24. "LAZYWB_OVERRIDE,Override cache policy of requests with lazy write back to write back" "0,1" newline hexmask.quad.byte 0x0 16.--23. 1. "ADDR_DECODE_MODE,Address decoding used to determine cache bank from the address: 0x00 = Bit 6 = 64 byte 0x01 = Bit 7 = 128 byte 0x10 = Simple XOR based address hash 1 .." newline hexmask.quad.byte 0x0 9.--15. 1. "RESERVED_9," newline bitfld.quad 0x0 8. "PAUSE,Pause the SLC" "0,1" newline hexmask.quad.byte 0x0 4.--7. 1. "RESERVED_4," newline bitfld.quad 0x0 3. "RESP_PRIORITY,Priority setting between Hit and Miss on return response. Default is round robin and set to 1 if miss needs priority over hit" "0,1" newline bitfld.quad 0x0 2. "ENABLE_LINE_USE_LIMIT,Enable the use of cache line limits" "0,1" newline bitfld.quad 0x0 1. "ENABLE_PSG_HAZARD_CHECK,Enable the hazard checking of PSG writes only turn off if strict write ordering is guaranteed in the memory fabric" "0,1" newline bitfld.quad 0x0 0. "BYPASS_BURST_COMBINER,Disable the burst combiner on the external memory interface" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_SLC_CTRL_INVAL,SLC Invalidate control." hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline bitfld.quad 0x8 31. "LAZY,Advanced mode of operation whereby other requestors are not blocked whilst the Invalidate is in progress" "0,1" newline hexmask.quad.long 0x8 6.--30. 1. "RESERVED_6," newline bitfld.quad 0x8 5. "DM_HOST_META,When set invalidate all SLC entries referenced solely by the HOST or META" "0,1" newline bitfld.quad 0x8 4. "DM_MMU,When set invalidate all SLC entries referenced solely by the MMU" "0,1" newline bitfld.quad 0x8 3. "DM_COMPUTE,When set invalidate all SLC entries referenced solely by the COMPUTE data master" "0,1" newline bitfld.quad 0x8 2. "DM_PIXEL,When set invalidate all SLC entries referenced solely by the PIXEL data master" "0,1" newline bitfld.quad 0x8 1. "DM_TA,When set invalidate all SLC entries referenced solely by the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters" "0,1" newline bitfld.quad 0x8 0. "ALL,When set invalidate all SLC entries" "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_SLC_CTRL_FLUSH,SLC Flush control." hexmask.quad.long 0x10 32.--63. 1. "RESERVED_32," newline bitfld.quad 0x10 31. "LAZY,Advanced mode of operation whereby other requestors are not blocked whilst the Flush is in progress" "0,1" newline hexmask.quad.long 0x10 6.--30. 1. "RESERVED_6," newline bitfld.quad 0x10 5. "DM_HOST_META,When set flush all SLC entries made dirty by the HOST or META" "0,1" newline bitfld.quad 0x10 4. "DM_MMU,When set flush all SLC entries made dirty by the MMU" "0,1" newline bitfld.quad 0x10 3. "DM_COMPUTE,When set flush all SLC entries made dirty by the COMPUTE data master" "0,1" newline bitfld.quad 0x10 2. "DM_PIXEL,When set flush all SLC entries made dirty by the PIXEL data master" "0,1" newline bitfld.quad 0x10 1. "DM_TA,When set flush all SLC entries made dirty by the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters" "0,1" newline bitfld.quad 0x10 0. "ALL,When set flush all SLC entries" "0,1" line.quad 0x18 "CORE_MMRS_RGX_CR_SLC_CTRL_FLUSH_INVAL,SLC Flush & Invalidate control." hexmask.quad.long 0x18 32.--63. 1. "RESERVED_32," newline bitfld.quad 0x18 31. "LAZY,Advanced mode of operation whereby other requestors are not blocked whilst the Flush Invalidate is in progress" "0,1" newline hexmask.quad.long 0x18 6.--30. 1. "RESERVED_6," newline bitfld.quad 0x18 5. "DM_HOST_META,When set flush all SLC entries made dirty by the HOST or META then invalidate all SLC entries referenced solely by the HOST or META" "0,1" newline bitfld.quad 0x18 4. "DM_MMU,When set flush all SLC entries made dirty by the MMU then invalidate all SLC entries referenced solely by the MMU" "0,1" newline bitfld.quad 0x18 3. "DM_COMPUTE,When set flush all SLC entries made dirty by the COMPUTE data master then invalidate all SLC entries referenced solely by the COMPUTE data master" "0,1" newline bitfld.quad 0x18 2. "DM_PIXEL,When set flush all SLC entries made dirty by the PIXEL data master then invalidate all SLC entries referenced solely by the PIXEL data master" "0,1" newline bitfld.quad 0x18 1. "DM_TA,When set flush all SLC entries made dirty by the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters then invalidate all SLC entries referenced solely by the TA group which includes VERTEX .." "0,1" newline bitfld.quad 0x18 0. "ALL,When set flush all SLC entries then invalidate all SLC entries" "0,1" rgroup.quad 0x3820++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_SLC_STATUS0,Current status of Flush / Invalidate operations within the SLC" hexmask.quad 0x0 3.--63. 1. "RESERVED_3," newline bitfld.quad 0x0 2. "FLUSH_INVAL_PENDING,1 indicates there is a pending request to perform a combined Flush Invalidate on the SLC" "0,1" newline bitfld.quad 0x0 1. "INVAL_PENDING,1 indicates there is a pending request to Invalidate the SLC" "0,1" newline bitfld.quad 0x0 0. "FLUSH_PENDING,1 indicates there is a pending request to Flush the SLC" "0,1" rgroup.quad 0x3828++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_SLC_CTRL_BYPASS,SLC Bypass control" hexmask.quad.byte 0x0 60.--63. 1. "RESERVED_60," newline bitfld.quad 0x0 59. "REQ_TFBC_COMP_ZLS,Bypass SLC for TFBC_COMP ZLS requestor" "0,1" newline bitfld.quad 0x0 58. "REQ_TFBC_DECOMP_ZLS_HEADER,Bypass SLC for TFBC_DECOMP ZLS Header requestor" "0,1" newline bitfld.quad 0x0 57. "REQ_TFBC_DECOMP_TCU_HEADER,Bypass SLC for TFBC_DECOMP TCU Header requestor" "0,1" newline bitfld.quad 0x0 56. "REQ_TFBC_DECOMP_ZLS_DATA,Bypass SLC for TFBC_DECOMP ZLS Delta requestor" "0,1" newline bitfld.quad 0x0 55. "REQ_TFBC_DECOMP_TCU_DATA,Bypass SLC for TFBC_DECOMP TCU Delta requestor" "0,1" newline bitfld.quad 0x0 54. "REQ_TFBC_COMP_PBE,Bypass SLC for TFBC_COMP PBE requestor" "0,1" newline bitfld.quad 0x0 53. "REQ_TCU_DM_COMPUTE,Bypass SLC when DM is COMPUTE for TCU requests" "0,1" newline bitfld.quad 0x0 52. "PDSRW_NOLINEFILL,PDSRW nolinefill set" "0,1" newline bitfld.quad 0x0 51. "PBE_NOLINEFILL,PBE nolinefill set" "0,1" newline rbitfld.quad 0x0 50. "RESERVED_50," "0,1" newline bitfld.quad 0x0 49. "REQ_IPF_RREQ,Bypass SLC for IPF [RREQ] requestor" "0,1" newline bitfld.quad 0x0 48. "REQ_IPF_CREQ,Bypass SLC for IPF [CREQ] requestor" "0,1" newline bitfld.quad 0x0 47. "REQ_IPF_PREQ,Bypass SLC for IPF [PREQ] requestor" "0,1" newline bitfld.quad 0x0 46. "REQ_IPF_DBSC,Bypass SLC for IPF [DBSC] requestor" "0,1" newline bitfld.quad 0x0 45. "REQ_TCU,Bypass SLC for TCU requests" "0,1" newline bitfld.quad 0x0 44. "REQ_PBE,Bypass SLC for PBE requestor" "0,1" newline bitfld.quad 0x0 43. "REQ_ISP,Bypass SLC for the ISP requestor" "0,1" newline bitfld.quad 0x0 42. "REQ_PM,Bypass SLC for the PM requestor" "0,1" newline rbitfld.quad 0x0 41. "RESERVED_41," "0,1" newline bitfld.quad 0x0 40. "REQ_CDM,Bypass SLC for the CDM requestor" "0,1" newline bitfld.quad 0x0 39. "REQ_TSPF_PDS_STATE,Bypass SLC for the TSPF PDS STATE requestor" "0,1" newline bitfld.quad 0x0 38. "REQ_TSPF_DB,Bypass SLC for the TSPF DB requestor" "0,1" newline bitfld.quad 0x0 37. "REQ_TSPF_VTX_VAR,Bypass SLC for the TSPF VTX VAR requestor" "0,1" newline bitfld.quad 0x0 36. "REQ_VDM,Bypass SLC for VDM requestor" "0,1" newline bitfld.quad 0x0 35. "REQ_TA_PSG_STREAM,Bypass SLC for the TA [PSG Stream] requestor" "0,1" newline bitfld.quad 0x0 34. "REQ_TA_PSG_REGION,Bypass SLC for the TA [PSG Region] requestor" "0,1" newline bitfld.quad 0x0 33. "REQ_TA_VCE,Bypass SLC for the TA [VCE] requestor" "0,1" newline bitfld.quad 0x0 32. "REQ_TA_PPP,Bypass SLC for the TA [PPP] requestor" "0,1" newline rbitfld.quad 0x0 31. "RESERVED_31," "0,1" newline bitfld.quad 0x0 30. "DM_PM_ALIST,Bypass SLC for the PM_ALIST data master" "0,1" newline bitfld.quad 0x0 29. "DM_PB_TE,Bypass SLC for the PB_TE data master" "0,1" newline bitfld.quad 0x0 28. "DM_PB_VCE,Bypass SLC for the PB_VCE data master" "0,1" newline rbitfld.quad 0x0 26.--27. "RESERVED_26," "0,1,2,3" newline bitfld.quad 0x0 25. "REQ_IPF_CPF,Bypass SLC for IPF [CPF] requestor" "0,1" newline bitfld.quad 0x0 24. "REQ_TPU,Bypass SLC for TPU requests coming from the MCU requestor" "0,1" newline rbitfld.quad 0x0 22.--23. "RESERVED_22," "0,1,2,3" newline bitfld.quad 0x0 21. "BYP_CC_N,Bypass SLC when Cache Coherency bit is not set" "0,1" newline bitfld.quad 0x0 20. "BYP_CC,Bypass SLC when Cache Coherency bit is set" "0,1" newline bitfld.quad 0x0 19. "REQ_MCU,Bypass SLC for the MCU requestor" "0,1" newline bitfld.quad 0x0 18. "REQ_PDS,Bypass SLC for the PDS requestor" "0,1" newline bitfld.quad 0x0 17. "REQ_TPF,Bypass SLC for the TPF requestor" "0,1" newline bitfld.quad 0x0 16. "REQ_TA_TPC,Bypass SLC for the TA [Tail Pointer Cache data] requestor" "0,1" newline rbitfld.quad 0x0 15. "RESERVED_15," "0,1" newline bitfld.quad 0x0 14. "REQ_USC,Bypass SLC for the USC requestor" "0,1" newline bitfld.quad 0x0 13. "REQ_META,Bypass SLC for the META requestor" "0,1" newline bitfld.quad 0x0 12. "REQ_HOST,Bypass SLC for the Host requestor" "0,1" newline bitfld.quad 0x0 11. "REQ_MMU_PT,Bypass SLC for the MMU requestor [Page Table data]" "0,1" newline bitfld.quad 0x0 10. "REQ_MMU_PD,Bypass SLC for the MMU requestor [Page Directory data]" "0,1" newline bitfld.quad 0x0 9. "REQ_MMU_PC,Bypass SLC for the MMU requestor [Page Catalogue data]" "0,1" newline rbitfld.quad 0x0 6.--8. "RESERVED_6," "0,1,2,3,4,5,6,7" newline bitfld.quad 0x0 5. "DM_HOST_META,Bypass SLC the HOST/META data master" "0,1" newline bitfld.quad 0x0 4. "DM_MMU,Bypass SLC the MMU data master" "0,1" newline bitfld.quad 0x0 3. "DM_COMPUTE,Bypass SLC the COMPUTE data master" "0,1" newline bitfld.quad 0x0 2. "DM_PIXEL,Bypass SLC for the PIXEL data master" "0,1" newline bitfld.quad 0x0 1. "DM_TA,Bypass SLC for the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters" "0,1" newline bitfld.quad 0x0 0. "ALL,Bypass SLC for all requesters" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_SLC_LINE_USE_COUNT_LIMIT0,Define the maximum number of cache lines allowed to be allocated to each requester within the SLC." hexmask.quad.byte 0x8 56.--63. 1. "TPF,Maximum number of cachelines allocated to the TPF requestor" newline hexmask.quad.byte 0x8 48.--55. 1. "TA_TPC,Maximum number of cachelines allocated to the TA [Tail Pointer Cache data] requestor" newline hexmask.quad.byte 0x8 40.--47. 1. "IPF_OBJ,Maximum number of cachelines allocated to the IPF [Object data] requestor" newline hexmask.quad.byte 0x8 32.--39. 1. "USC,Maximum number of cachelines allocated to the USC requestor" newline hexmask.quad.byte 0x8 24.--31. 1. "TDM,Maximum number of cachelines allocated to the TDM requestor" newline hexmask.quad.byte 0x8 16.--23. 1. "HOST,Maximum number of cachelines allocated to the HOST requestor" newline hexmask.quad.byte 0x8 8.--15. 1. "TCU,Maximum number of cachelines allocated to the TCU requestor" newline hexmask.quad.byte 0x8 0.--7. 1. "MMU,Maximum number of cachelines allocated to the MMU requestor" line.quad 0x10 "CORE_MMRS_RGX_CR_SLC_LINE_USE_COUNT_LIMIT1,Define the maximum number of cache lines allowed to be allocated to each requester within the SLC." hexmask.quad 0x10 24.--63. 1. "RESERVED_24," newline hexmask.quad.byte 0x10 16.--23. 1. "FBDC,Maximum number of cachelines allocated to the FBDC requestor" newline hexmask.quad.byte 0x10 8.--15. 1. "MCU,Maximum number of cachelines allocated to the MCU requestor" newline hexmask.quad.byte 0x10 0.--7. 1. "PDS,Maximum number of cachelines allocated to the PDS requestor" rgroup.quad 0x3840++0x37 line.quad 0x0 "CORE_MMRS_RGX_CR_SLC_LINE_USE_COUNT_STATUS0,Number of cache lines currently allocated to each requester within the SLC." hexmask.quad.byte 0x0 60.--63. 1. "RESERVED_60," newline hexmask.quad.word 0x0 48.--59. 1. "BANK0_HOST,Number of cache lines in bank 0 currently allocated to the HOST" newline hexmask.quad.word 0x0 36.--47. 1. "BANK1_TDM,Number of cache lines in bank 1 currently allocated to the TDM" newline hexmask.quad.word 0x0 24.--35. 1. "BANK0_TDM,Number of cache lines in bank 0 currently allocated to the TDM" newline hexmask.quad.word 0x0 12.--23. 1. "BANK1_MMU,Number of cache lines in bank 1 currently allocated to the MMU" newline hexmask.quad.word 0x0 0.--11. 1. "BANK0_MMU,Number of cache lines in bank 0 currently allocated to the MMU" line.quad 0x8 "CORE_MMRS_RGX_CR_SLC_LINE_USE_COUNT_STATUS1,Number of cache lines currently allocated to each requester within the SLC." hexmask.quad.byte 0x8 60.--63. 1. "RESERVED_60," newline hexmask.quad.word 0x8 48.--59. 1. "BANK1_USC,Number of cache lines in bank 1 currently allocated to the USC" newline hexmask.quad.word 0x8 36.--47. 1. "BANK0_USC,Number of cache lines in bank 0 currently allocated to the USC" newline hexmask.quad.word 0x8 24.--35. 1. "BANK1_TCU,Number of cache lines in bank 1 currently allocated to the TCU" newline hexmask.quad.word 0x8 12.--23. 1. "BANK0_TCU,Number of cache lines in bank 0 currently allocated to the TCU" newline hexmask.quad.word 0x8 0.--11. 1. "BANK1_HOST,Number of cache lines in bank 1 currently allocated to the HOST" line.quad 0x10 "CORE_MMRS_RGX_CR_SLC_LINE_USE_COUNT_STATUS2,Number of cache lines currently allocated to each requester within the SLC." hexmask.quad.byte 0x10 60.--63. 1. "RESERVED_60," newline hexmask.quad.word 0x10 48.--59. 1. "BANK0_TPF,Number of cache lines in bank 0 currently allocated to the TPF" newline hexmask.quad.word 0x10 36.--47. 1. "BANK1_TA_TPC,Number of cache lines in bank 1 currently allocated to the TA [Tail Pointer Cache data]" newline hexmask.quad.word 0x10 24.--35. 1. "BANK0_TA_TPC,Number of cache lines in bank 0 currently allocated to the TA [Tail Pointer Cache data]" newline hexmask.quad.word 0x10 12.--23. 1. "BANK1_IPF_OBJ,Number of cache lines in bank 1 currently allocated to the IPF [Object data]" newline hexmask.quad.word 0x10 0.--11. 1. "BANK0_IPF_OBJ,Number of cache lines in bank 0 currently allocated to the IPF [Object data]" line.quad 0x18 "CORE_MMRS_RGX_CR_SLC_LINE_USE_COUNT_STATUS3,Number of cache lines currently allocated to each requester within the SLC." hexmask.quad.byte 0x18 60.--63. 1. "RESERVED_60," newline hexmask.quad.word 0x18 48.--59. 1. "BANK1_MCU,Number of cache lines in bank 1 currently allocated to the MCU" newline hexmask.quad.word 0x18 36.--47. 1. "BANK0_MCU,Number of cache lines in bank 0 currently allocated to the MCU" newline hexmask.quad.word 0x18 24.--35. 1. "BANK1_PDS,Number of cache lines in bank 1 currently allocated to the PDS" newline hexmask.quad.word 0x18 12.--23. 1. "BANK0_PDS,Number of cache lines in bank 0 currently allocated to the PDS" newline hexmask.quad.word 0x18 0.--11. 1. "BANK1_TPF,Number of cache lines in bank 1 currently allocated to the TPF" line.quad 0x20 "CORE_MMRS_RGX_CR_SLC_LINE_USE_COUNT_STATUS4,Number of cache lines currently allocated to each requester within the SLC." hexmask.quad 0x20 24.--63. 1. "RESERVED_24," newline hexmask.quad.word 0x20 12.--23. 1. "BANK1_FBDC,Number of cache lines in bank 1 currently allocated to the FBDC" newline hexmask.quad.word 0x20 0.--11. 1. "BANK0_FBDC,Number of cache lines in bank 0 currently allocated to the FBDC" line.quad 0x28 "CORE_MMRS_RGX_CR_SLC_LINE_USE_COUNT_STATUS5,Number of cache lines currently allocated to each requester within the SLC." hexmask.quad.byte 0x28 60.--63. 1. "RESERVED_60," newline hexmask.quad.word 0x28 48.--59. 1. "BANK1_PM,Number of cache lines in bank 1 currently allocated to the PM core" newline hexmask.quad.word 0x28 36.--47. 1. "BANK0_PM,Number of cache lines in bank 0 currently allocated to the PM core" newline hexmask.quad 0x28 0.--35. 1. "RESERVED_0," line.quad 0x30 "CORE_MMRS_RGX_CR_SLC_STATUS1,Current status of the SLC" bitfld.quad 0x30 63. "PAUSED,All cache banks are Paused" "0,1" newline hexmask.quad.tbyte 0x30 42.--62. 1. "RESERVED_42," newline hexmask.quad.word 0x30 32.--41. 1. "READS1,Number of items of read data SLC bank 1 has in internal pipeline FIFO's" newline hexmask.quad.byte 0x30 26.--31. 1. "RESERVED_26," newline hexmask.quad.word 0x30 16.--25. 1. "READS0,Number of items of read data SLC bank 0 has in internal pipeline FIFO's" newline hexmask.quad.byte 0x30 8.--15. 1. "READS1_EXT,Number of items of read data SLC bank 1 has outstanding from external memory" newline hexmask.quad.byte 0x30 0.--7. 1. "READS0_EXT,Number of items of read data SLC bank 0 has outstanding from external memory" rgroup.quad 0x3878++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_SLC_STATS0_CTRL,Configuration of the SLC Stats counters inside SLC bank 0." hexmask.quad 0x0 28.--63. 1. "RESERVED_28," newline bitfld.quad 0x0 27. "STOP,Pause counting whilst this bit is set" "0,1" newline bitfld.quad 0x0 26. "RESET,Reset counter" "0,1" newline bitfld.quad 0x0 25. "RNW,If constraint set 0x0 count only writes 0x1 count only reads" "0,1" newline bitfld.quad 0x0 24. "BYPASS,If constraint set 0x0 count cached requests 0x1 count bypassed requests" "0,1" newline bitfld.quad 0x0 21.--23. "DM,If constraint set count only requests for the specified Data Master" "0,1,2,3,4,5,6,7" newline hexmask.quad.byte 0x0 16.--20. 1. "TAG_ID,If constraint set count only requests with the specified Tag ID" newline hexmask.quad.byte 0x0 8.--15. 1. "TAG_SB,If constraint set count only requests with the specified sideband Tag" newline bitfld.quad 0x0 7. "SELECT_TAG_SB,Include Tag sideband in constraints" "0,1" newline bitfld.quad 0x0 6. "SELECT_TAG_ID,Include Tag ID in constraints" "0,1" newline bitfld.quad 0x0 5. "SELECT_DM,Include Data Master in constraints" "0,1" newline bitfld.quad 0x0 4. "SELECT_BYPASS,Include Bypass enable in constraints" "0,1" newline bitfld.quad 0x0 3. "SELECT_RNW,Include Wead/Write select in constraints" "0,1" newline bitfld.quad 0x0 2. "TYPE_FLUSH,Count number of cache lines flushed" "0,1" newline bitfld.quad 0x0 1. "TYPE_MISS,Count number of misses" "0,1" newline bitfld.quad 0x0 0. "TYPE_HIT,Count number of hits" "0,1" rgroup.quad 0x3880++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_SLC_STATS0_OUTPUT,Output of the SLC Stats counter inside SLC bank 0." hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "VALUE,Value of counter 0" rgroup.quad 0x3888++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_SLC_STATS1_CTRL,Configuration of the SLC Stats counters inside SLC bank 1." hexmask.quad 0x0 28.--63. 1. "RESERVED_28," newline bitfld.quad 0x0 27. "STOP,Pause counting whilst this bit is set" "0,1" newline bitfld.quad 0x0 26. "RESET,Reset counter" "0,1" newline bitfld.quad 0x0 25. "RNW,If constraint set 0x0 count only writes 0x1 count only reads" "0,1" newline bitfld.quad 0x0 24. "BYPASS,If constraint set 0x0 count cached requests 0x1 count bypassed requests" "0,1" newline bitfld.quad 0x0 21.--23. "DM,If constraint set count only requests for the specified Data Master" "0,1,2,3,4,5,6,7" newline hexmask.quad.byte 0x0 16.--20. 1. "TAG_ID,If constraint set count only requests with the specified Tag ID" newline hexmask.quad.byte 0x0 8.--15. 1. "TAG_SB,If constraint set count only requests with the specified sideband Tag" newline bitfld.quad 0x0 7. "SELECT_TAG_SB,Include Tag sideband in constraints" "0,1" newline bitfld.quad 0x0 6. "SELECT_TAG_ID,Include Tag ID in constraints" "0,1" newline bitfld.quad 0x0 5. "SELECT_DM,Include Data Master in constraints" "0,1" newline bitfld.quad 0x0 4. "SELECT_BYPASS,Include Bypass enable in constraints" "0,1" newline bitfld.quad 0x0 3. "SELECT_RNW,Include Wead/Write select in constraints" "0,1" newline bitfld.quad 0x0 2. "TYPE_FLUSH,Count number of cache lines flushed" "0,1" newline bitfld.quad 0x0 1. "TYPE_MISS,Count number of misses" "0,1" newline bitfld.quad 0x0 0. "TYPE_HIT,Count number of hits" "0,1" rgroup.quad 0x3890++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_SLC_STATS1_OUTPUT,Output of the SLC Stats counter inside SLC bank 1." hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "VALUE,Value of counter 1" line.quad 0x8 "CORE_MMRS_RGX_CR_SLC_IDLE," hexmask.quad 0x8 8.--63. 1. "RESERVED_8," newline bitfld.quad 0x8 7. "IMGBV4,IMG Bus v4 Module IDLE" "0,1" newline bitfld.quad 0x8 6. "CACHE_BANKS,Cache Bank IDLEs" "0,1" newline bitfld.quad 0x8 5. "RBOFIFO,Read Burst Order FIFO Module IDLE" "0,1" newline bitfld.quad 0x8 4. "FRC_CONV,FRC Module IDLE" "0,1" newline bitfld.quad 0x8 3. "VXE_CONV,Video Encode Converter Module IDLE" "0,1" newline bitfld.quad 0x8 2. "VXD_CONV,Video Decode Converter Module IDLE" "0,1" newline bitfld.quad 0x8 1. "BIF1_CONV,BIF128->256 Converter Module IDLE" "0,1" newline bitfld.quad 0x8 0. "CBAR,CrossBar Module IDLE" "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_MCU_PWR_NUM,Power Monitoring register" hexmask.quad.long 0x10 32.--63. 1. "L1_TO_SLC_ACCESS,Number of L1 to SLC accesses" newline hexmask.quad.long 0x10 0.--31. 1. "L0_TO_L1_ACCESS,Number of L0 to L1 accesses. Both L0s in a DUST added together" rgroup.quad 0x38A8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_SLC_LINE_USE_COUNT_LIMIT2,Define the maximum number of cache lines allowed to be allocated to each requester within the SLC." hexmask.quad.tbyte 0x0 40.--63. 1. "RESERVED_40," newline hexmask.quad.byte 0x0 32.--39. 1. "PM,Maximum number of cachelines allocated to the PM requestor" newline hexmask.quad.byte 0x0 24.--31. 1. "CDM,Maximum number of cachelines allocated to the CDM requestor" newline hexmask.quad.byte 0x0 16.--23. 1. "VDM,Maximum number of cachelines allocated to the VDM requestor" newline hexmask.quad.byte 0x0 8.--15. 1. "ISP,Maximum number of cachelines allocated to the ISP requestor" newline hexmask.quad.byte 0x0 0.--7. 1. "PBE,Maximum number of cachelines allocated to the PBE requestor" rgroup.quad 0x38B0++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_SLC_LINE_USE_COUNT_STATUS6,Number of cache lines currently allocated to each requester within the SLC." hexmask.quad.byte 0x0 60.--63. 1. "RESERVED_60," newline hexmask.quad.word 0x0 48.--59. 1. "BANK0_CDM,Number of cache lines in bank 1 currently allocated to the CDM core" newline hexmask.quad.word 0x0 36.--47. 1. "BANK1_ISP,Number of cache lines in bank 1 currently allocated to the ISP core" newline hexmask.quad.word 0x0 24.--35. 1. "BANK0_ISP,Number of cache lines in bank 0 currently allocated to the ISP core" newline hexmask.quad.word 0x0 12.--23. 1. "BANK1_PBE,Number of cache lines in bank 1 currently allocated to the PBE core" newline hexmask.quad.word 0x0 0.--11. 1. "BANK0_PBE,Number of cache lines in bank 0 currently allocated to the PBE core" line.quad 0x8 "CORE_MMRS_RGX_CR_SLC_LINE_USE_COUNT_STATUS7,Number of cache lines currently allocated to each requester within the SLC." hexmask.quad.long 0x8 36.--63. 1. "RESERVED_36," newline hexmask.quad.word 0x8 24.--35. 1. "BANK1_VDM,Number of cache lines in bank 1 currently allocated to the VDM core" newline hexmask.quad.word 0x8 12.--23. 1. "BANK0_VDM,Number of cache lines in bank 0 currently allocated to the VDM core" newline hexmask.quad.word 0x8 0.--11. 1. "BANK1_CDM,Number of cache lines in bank 1 currently allocated to the CDM core" rgroup.quad 0x38C0++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_AXI_ACE_LITE_CONFIGURATION,AXI ACE-LITE configuration registers" hexmask.quad.tbyte 0x0 46.--63. 1. "RESERVED_46," newline bitfld.quad 0x0 45. "ENABLE_FENCE_OUT,SET to 1 to enable fence output to AXI" "0,1" newline hexmask.quad.byte 0x0 37.--44. 1. "OSID_SECURITY,SET to 1 to disable secure reads/writes for each OSID" newline bitfld.quad 0x0 36. "DISABLE_COHERENT_WRITELINEUNIQUE,SET to 1 to disable coherent write line uniques" "0,1" newline bitfld.quad 0x0 35. "DISABLE_COHERENT_WRITE,SET to 1 to disable coherent writes" "0,1" newline bitfld.quad 0x0 34. "DISABLE_COHERENT_READ,SET to 1 to disable coherent reads" "0,1" newline hexmask.quad.byte 0x0 30.--33. 1. "ARCACHE_CACHE_MAINTENANCE,Read cache policy for cache maintenance transactions - bit[1] should be set to 1" newline hexmask.quad.byte 0x0 26.--29. 1. "ARCACHE_COHERENT,Read cache policy for coherent transactions - bit[1] should be set to 1" newline hexmask.quad.byte 0x0 22.--25. 1. "AWCACHE_COHERENT,Write cache policy for coherent transactions - bit[1] should be set to 1" newline bitfld.quad 0x0 20.--21. "ARDOMAIN_BARRIER,Read shareability domain for barrier transactions 00 = Non-Shareable 01 = Inner Shareable 10 = Outer Shareable 11 = System" "0: Non-Shareable,1: Inner Shareable,?,?" newline bitfld.quad 0x0 18.--19. "AWDOMAIN_BARRIER,Write shareability domain for barrier transactions 00 = Non-Shareable 01 = Inner Shareable 10 = Outer Shareable 11 = System" "0: Non-Shareable,1: Inner Shareable,?,?" newline bitfld.quad 0x0 16.--17. "ARDOMAIN_CACHE_MAINTENANCE,Read shareability domain for cache maintenance transactions 00 = Non-Shareable 01 = Inner Shareable 10 = Outer Shareable" "0: Non-Shareable,1: Inner Shareable,?,?" newline bitfld.quad 0x0 14.--15. "AWDOMAIN_COHERENT,Write shareability domain for coherant transactions 01 = Inner Shareable 10 = Outer Shareable" "?,1: Inner Shareable,?,?" newline bitfld.quad 0x0 12.--13. "ARDOMAIN_COHERENT,Read shareability domain for coherant transactions 01 = Inner Shareable 10 = Outer Shareable" "?,1: Inner Shareable,?,?" newline bitfld.quad 0x0 10.--11. "ARDOMAIN_NON_SNOOPING,Read shareability domain for non-snooping transactions 00 = Non-Shareable 11 = System" "0: Non-Shareable,?,?,?" newline bitfld.quad 0x0 8.--9. "AWDOMAIN_NON_SNOOPING,Write shareability domain for non-snooping transactions 00 = Non-Shareable 11 = System" "0: Non-Shareable,?,?,?" newline hexmask.quad.byte 0x0 4.--7. 1. "ARCACHE_NON_SNOOPING,Read cache policy for non-snooping transactions" newline hexmask.quad.byte 0x0 0.--3. 1. "AWCACHE_NON_SNOOPING,Write cache policy for non-snooping transactions" line.quad 0x8 "CORE_MMRS_RGX_CR_AXI_ACE_LITE_CACHE_MAINTENANCE_CONFIGURATION,AXI ACE-LITE Cache Maintenance configuration registers" hexmask.quad.tbyte 0x8 44.--63. 1. "RESERVED_44," newline hexmask.quad 0x8 4.--43. 1. "MAINTENANCE_ADDRESS,Address to perform cache maintenace address on" newline bitfld.quad 0x8 3. "MAINTENANCE_MAKEINVALID,Writing a 1 issues a makeinvalid operation" "0,1" newline bitfld.quad 0x8 2. "MAINTENANCE_CLEAN_INVALID,Writing a 1 issues a clean invalid operation" "0,1" newline bitfld.quad 0x8 1. "MAINTENANCE_CLEANSHARED,Writing a 1 issues a clean shared operation" "0,1" newline bitfld.quad 0x8 0. "ENABLE_MAINTENANCE,Writing a 1 enables cache maintenance operations" "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_AXI_ACE_LITE_CACHE_MAINTENANCE_STATUS,The hardware will set this to 1 once the cache maintenance operation has completed." hexmask.quad 0x10 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x10 0. "DONE," "0,1" rgroup.quad 0x3930++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_SLC_CTRL_MISC2,SLC control registers" hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "SCRAMBLE_BITS,Pattern of bits used to determine the MSB of the Cache Bank in 4 Bank configurations in Address Decode mode 0x21. The actual Cache Bank to use is determined by indexing into the 32 Scramble Bits using the 5.." line.quad 0x8 "CORE_MMRS_RGX_CR_SLC_CROSSBAR_LOAD_BALANCE,SLC control registers to bypass SLC crossbar load balancing" hexmask.quad 0x8 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x8 0. "BYPASS,control register bit to bypass load balancing in SLC crossbar. In this case the requests from img-memif0 will go directly to ocp-memif0 and so on" "0,1" rgroup.quad 0x3960++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_SLC_STATUS3,Current status of the SLC" hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.byte 0x0 24.--31. 1. "WRITES1_TRANSACTIONS_EXT,Number of outsanding write burst transactions in SLC bank 1" newline hexmask.quad.byte 0x0 16.--23. 1. "WRITES0_TRANSACTIONS_EXT,Number of outsanding write burst transactions in SLC bank 0" newline hexmask.quad.byte 0x0 8.--15. 1. "READS1_TRANSACTIONS_EXT,Number of outsanding read burst transactions in SLC bank 1" newline hexmask.quad.byte 0x0 0.--7. 1. "READS0_TRANSACTIONS_EXT,Number of outsanding read burst transactions in SLC bank 0" rgroup.quad 0x3970++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_SLC_SIZE_IN_KB,Configured SLC SIZE in KBytes" hexmask.quad 0x0 16.--63. 1. "RESERVED_16," newline hexmask.quad.word 0x0 0.--15. 1. "SIZE,The configured SLC SIZE in KBytes ie 0x0100 = 256 KB." rgroup.quad 0x39A0++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_TCU_PWR_NUM,Power Monitoring register" hexmask.quad.long 0x0 32.--63. 1. "TCU_TO_SLC_ACCESS,Number of TCU to SLC accesses" newline hexmask.quad.long 0x0 0.--31. 1. "L0_TO_TCU_ACCESS,Number of MADD-L0 to TCU accesses" rgroup.quad 0x39B0++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_TCU_CTRL,TCU control regiseters" hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "SLC_CP_LAZYWB_OVERRIDE,Override the TCU to SLC cache policy from lazy write back to write back" "0,1" rgroup.quad 0x3E40++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_FRAG_SCREEN,Define the screen size for fragment processing." hexmask.quad 0x0 31.--63. 1. "RESERVED_31," newline hexmask.quad.word 0x0 16.--30. 1. "YMAX,Maximum pixel number in y dimension on screen. Screen height in pixels is YMAX+1. 16K x 16K is the max screen size. I.e. 2^14 bit 15 is always written as 0." newline rbitfld.quad 0x0 15. "RESERVED_15," "0,1" newline hexmask.quad.word 0x0 0.--14. 1. "XMAX,Maximum pixel number in x dimension on screen. Screen width in pixels is XMAX+1. 16K x 16K is the max screen size. I.e. 2^14 bit 15 is always written as 0." rgroup.quad 0x4000++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_USC_INST_CACHE," hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "INVALIDATE,Any write to this location invalidates the L1 and L2 instruction caches automatically" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_USC_CODE_BASE_VERTEX," hexmask.quad.tbyte 0x8 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x8 6.--39. 1. "ADDR,Vertex Data Master Code Base Register bits" newline hexmask.quad.byte 0x8 0.--5. 1. "RESERVED_0," line.quad 0x10 "CORE_MMRS_RGX_CR_USC_CODE_BASE_PIXEL," hexmask.quad.tbyte 0x10 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x10 6.--39. 1. "ADDR,Pixel Data Master Code Base Register bits" newline hexmask.quad.byte 0x10 0.--5. 1. "RESERVED_0," rgroup.quad 0x4028++0x2F line.quad 0x0 "CORE_MMRS_RGX_CR_USC_CODE_BASE_COMPUTE," hexmask.quad.tbyte 0x0 40.--63. 1. "RESERVED_40," newline hexmask.quad 0x0 6.--39. 1. "ADDR,Compute Data Master Code Base Register bits" newline hexmask.quad.byte 0x0 0.--5. 1. "RESERVED_0," line.quad 0x8 "CORE_MMRS_RGX_CR_USC_BREAKPOINT," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 1.--31. 1. "ADDR,Breakpoint Address" newline rbitfld.quad 0x8 0. "RESERVED_0," "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_USC_BREAKPOINT_HANDLER," hexmask.quad.long 0x10 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x10 1.--31. 1. "ADDR,Breakpoint Handler Address" newline rbitfld.quad 0x10 0. "RESERVED_0," "0,1" line.quad 0x18 "CORE_MMRS_RGX_CR_USC_BREAKPOINT_CTRL," hexmask.quad 0x18 4.--63. 1. "RESERVED_4," newline bitfld.quad 0x18 3. "ENABLE,0 = Breakpoint disabled 1 = Breakpoint enabled" "0: Breakpoint disabled,1: Breakpoint enabled" newline bitfld.quad 0x18 0.--2. "DM,Data Master of Breakpoint" "0,1,2,3,4,5,6,7" line.quad 0x20 "CORE_MMRS_RGX_CR_USC_SMP_SWAP," hexmask.quad 0x20 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x20 0. "ENABLE,Deactivate after SMP instruction" "0,1" line.quad 0x28 "CORE_MMRS_RGX_CR_USC_OVERRIDE_CTRL," hexmask.quad 0x28 22.--63. 1. "RESERVED_22," newline bitfld.quad 0x28 21. "USCIS_LOCKING,0 = Default enable locking of USCIS when queue fills to maintain task ordering 1 = retry USCIS request" "0: Default,1: retry USCIS request" newline bitfld.quad 0x28 20. "PHASE_BOTH,0 = Default no extra pass groups when single phase followed by multi-phase 1 = generate pass group whenever phases per task changes" "0: Default,1: generate pass group whenever phases per task.." newline bitfld.quad 0x28 18.--19. "RESERVE_SLOTS,0 = Default allow all slots to be used for first phase tasks 1 = reserve 1 slot 2 = reserve 2 3 = reserve 4" "0: Default,1: reserve 1 slot,2: reserve 2,3: reserve 4" newline bitfld.quad 0x28 17. "NO_RESERVE,0 = Default reserve slots for second phases 1 = Do not reserve slots for second phase tasks" "0: Default,1: Do not reserve slots for second phase tasks" newline bitfld.quad 0x28 15.--16. "MAX_GROUP,0 = Default - 8 pass groups in flight 1 = 6 pass groups 2 = 4 pass groups 3 = 2 pass groups. To disable entirely see PDS" "0: Default,?,?,?" newline bitfld.quad 0x28 14. "WAKE_UP,0 = Default normal wake up 1 = force task wake up" "0: Default,1: force task wake up" newline bitfld.quad 0x28 13. "LATE_PARTN,0 = Default enable pixel data master tasks to start before a partition is allocated 1 = wait for partition" "0: Default,1: wait for partition" newline bitfld.quad 0x28 12. "DMA_LOCKING,0 = Default enable locking of DMA when queue fills to maintain task ordering 1 = retry DMA request" "0: Default,1: retry DMA request" newline bitfld.quad 0x28 11. "PRIORITY,0 = Default enable state loading and end of tile tasks to run with higher priority 1 = all tasks low priority" "0: Default,1: all tasks low priority" newline bitfld.quad 0x28 10. "PHASE_PASSES,0 = Default enable inferred pass groups when multiple phase tasks are encountered 1 = disable hard SDs must be used" "0: Default,1: disable" newline bitfld.quad 0x28 9. "OUTPUT_WRITES,0 = Default enable tracking of output buffer write completion for on-edge buffer validlity 1 = tracking invalid" "0: Default,1: tracking invalid" newline bitfld.quad 0x28 8. "SELECTIVE_RATE,0 = Default [core specific enable selective rate mode if functional] 1 = disable" "0: Default,1: disable" newline rbitfld.quad 0x28 6.--7. "RESERVED_6," "0,1,2,3" newline hexmask.quad.byte 0x28 0.--5. 1. "DEBUG_TEMPS,Number of temps to add to PDS allocation size for debugging. Units of 8" rgroup.quad 0x4068++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_USC_SHARED_GROUP_CLEAR," hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "PENDING,Any write to this location requests the USC Shared Group register file to be cleared" "0,1" rgroup.quad 0x4070++0x67 line.quad 0x0 "CORE_MMRS_RGX_CR_USC_PIXEL_OUTPUT_CTRL," hexmask.quad 0x0 21.--63. 1. "RESERVED_21," newline hexmask.quad.tbyte 0x0 3.--20. 1. "PARTITION_MASK,Partition Enable Mask for USC pixel task" newline bitfld.quad 0x0 2. "ENABLE_4TH_PARTITION,Enables 4th Partition" "0,1" newline bitfld.quad 0x0 0.--1. "WIDTH," "0,1,2,3" line.quad 0x8 "CORE_MMRS_RGX_CR_USC_CLEAR_REGISTER0," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "VAL,Clear Colour register 0" line.quad 0x10 "CORE_MMRS_RGX_CR_USC_CLEAR_REGISTER1," hexmask.quad.long 0x10 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x10 0.--31. 1. "VAL,Clear Colour register 1" line.quad 0x18 "CORE_MMRS_RGX_CR_USC_CLEAR_REGISTER2," hexmask.quad.long 0x18 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x18 0.--31. 1. "VAL,Clear Colour register 2" line.quad 0x20 "CORE_MMRS_RGX_CR_USC_CLEAR_REGISTER3," hexmask.quad.long 0x20 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x20 0.--31. 1. "VAL,Clear Colour register 3" line.quad 0x28 "CORE_MMRS_RGX_CR_USC_G0," hexmask.quad 0x28 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x28 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.quad 0x30 "CORE_MMRS_RGX_CR_USC_G1," hexmask.quad 0x30 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x30 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.quad 0x38 "CORE_MMRS_RGX_CR_USC_G2," hexmask.quad 0x38 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x38 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.quad 0x40 "CORE_MMRS_RGX_CR_USC_G3," hexmask.quad 0x40 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x40 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.quad 0x48 "CORE_MMRS_RGX_CR_USC_G4," hexmask.quad 0x48 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x48 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.quad 0x50 "CORE_MMRS_RGX_CR_USC_G5," hexmask.quad 0x50 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x50 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.quad 0x58 "CORE_MMRS_RGX_CR_USC_G6," hexmask.quad 0x58 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x58 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.quad 0x60 "CORE_MMRS_RGX_CR_USC_G7," hexmask.quad 0x60 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x60 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" rgroup.quad 0x40D8++0x47 line.quad 0x0 "CORE_MMRS_RGX_CR_USC_SERV_PIXEL," hexmask.quad 0x0 17.--63. 1. "RESERVED_17," newline bitfld.quad 0x0 16. "EMPTY,No Pixel Data Master tasks in USC0 queue" "0,1" newline hexmask.quad.word 0x0 0.--15. 1. "COUNT,Number of Pixel Data Master tasks serviced by USC0" line.quad 0x8 "CORE_MMRS_RGX_CR_USC_SERV_VERTEX," hexmask.quad 0x8 17.--63. 1. "RESERVED_17," newline bitfld.quad 0x8 16. "EMPTY,No Vertex Data Master tasks in USC0 queue" "0,1" newline hexmask.quad.word 0x8 0.--15. 1. "COUNT,Number of Vertex Data Master tasks serviced by USC0" line.quad 0x10 "CORE_MMRS_RGX_CR_USC_SERV_TESS_PIXEL," hexmask.quad 0x10 17.--63. 1. "RESERVED_17," newline bitfld.quad 0x10 16. "EMPTY,No Tessellator Pixel Data Master tasks in USC0 queue" "0,1" newline hexmask.quad.word 0x10 0.--15. 1. "COUNT,Number of Tessellator Pixel Data Master tasks serviced by USC0" line.quad 0x18 "CORE_MMRS_RGX_CR_USC_SERV_TESS_VERTEX," hexmask.quad 0x18 17.--63. 1. "RESERVED_17," newline bitfld.quad 0x18 16. "EMPTY,No Tessellator Vertex Data Master tasks in USC0 queue" "0,1" newline hexmask.quad.word 0x18 0.--15. 1. "COUNT,Number of Tessellator Vertex Data Master tasks serviced by USC0" line.quad 0x20 "CORE_MMRS_RGX_CR_USC_SERV_COMPUTE," hexmask.quad 0x20 17.--63. 1. "RESERVED_17," newline bitfld.quad 0x20 16. "EMPTY,No Compute Data Master tasks in USC0 queue" "0,1" newline hexmask.quad.word 0x20 0.--15. 1. "COUNT,Number of Compute Data Master tasks serviced by USC0" line.quad 0x28 "CORE_MMRS_RGX_CR_USC_PARTITION_STATUS," hexmask.quad.word 0x28 48.--63. 1. "RESERVED_48," newline hexmask.quad.word 0x28 32.--47. 1. "WRITES_PEND,Partition writes pending" newline hexmask.quad.word 0x28 16.--31. 1. "CLOSED,Partition closed - end of tile task started" newline hexmask.quad.word 0x28 0.--15. 1. "IN_USE,Partition in use" line.quad 0x30 "CORE_MMRS_RGX_CR_USC_OLDEST_TASK_STATUS," hexmask.quad 0x30 20.--63. 1. "RESERVED_20," newline hexmask.quad.byte 0x30 16.--19. 1. "PASS_NUM,The present pass group" newline bitfld.quad 0x30 13.--15. "DM,The task Data Master" "0,1,2,3,4,5,6,7" newline hexmask.quad.byte 0x30 9.--12. 1. "TILEQUAD,The stream of the task depends on Data Master Vertex: Indicates the patch of the task Pixel >= 4 cluster: The tile ID of the task Pixel 2 cluster: The tile ID.." newline bitfld.quad 0x30 7.--8. "STATE,Queue state for entry" "0,1,2,3" newline bitfld.quad 0x30 6. "NEW_SD,This task is at the start of a new SD group bit is cleared when the task is first run" "0,1" newline bitfld.quad 0x30 5. "TFPU_CS_ED,This task is waiting for a TFPU strobe which has not been satisfied" "0,1" newline bitfld.quad 0x30 4. "MCU_CS_ED,This task is waiting for an MCU CS strobe which has not been satisfied" "0,1" newline bitfld.quad 0x30 3. "MCU_US_ED,This task is waiting for an MCU US strobe which has not been satisfied" "0,1" newline bitfld.quad 0x30 2. "FRAG_TYPE,Is this task a work or state loading type. '1' indicates a Vertex/Fragment/Work type '0' indicates a Shared/ Coefficient/ Control type" "0,1" newline bitfld.quad 0x30 1. "PHAS_ISSUE,This task must issue a PHAS instruction which has not yet been seen" "0,1" newline bitfld.quad 0x30 0. "PASS_GROUP,Is the task the start of a new pass group" "0,1" line.quad 0x38 "CORE_MMRS_RGX_CR_USC_PARTITION_TILE_STATUS0," hexmask.quad.word 0x38 48.--63. 1. "RESERVED_48," newline hexmask.quad.byte 0x38 42.--47. 1. "TILE_ID7,Tile ID for partition 7" newline hexmask.quad.byte 0x38 36.--41. 1. "TILE_ID6,Tile ID for partition 6" newline hexmask.quad.byte 0x38 30.--35. 1. "TILE_ID5,Tile ID for partition 5" newline hexmask.quad.byte 0x38 24.--29. 1. "TILE_ID4,Tile ID for partition 4" newline hexmask.quad.byte 0x38 18.--23. 1. "TILE_ID3,Tile ID for partition 3" newline hexmask.quad.byte 0x38 12.--17. 1. "TILE_ID2,Tile ID for partition 2" newline hexmask.quad.byte 0x38 6.--11. 1. "TILE_ID1,Tile ID for partition 1" newline hexmask.quad.byte 0x38 0.--5. 1. "TILE_ID0,Tile ID for partition 0" line.quad 0x40 "CORE_MMRS_RGX_CR_USC_PARTITION_TILE_STATUS1," hexmask.quad.byte 0x40 60.--63. 1. "RESERVED_60," newline hexmask.quad.byte 0x40 54.--59. 1. "TILE_ID17,Tile ID for partition 17" newline hexmask.quad.byte 0x40 48.--53. 1. "TILE_ID16,Tile ID for partition 16" newline hexmask.quad.byte 0x40 42.--47. 1. "TILE_ID15,Tile ID for partition 15" newline hexmask.quad.byte 0x40 36.--41. 1. "TILE_ID14,Tile ID for partition 14" newline hexmask.quad.byte 0x40 30.--35. 1. "TILE_ID13,Tile ID for partition 13" newline hexmask.quad.byte 0x40 24.--29. 1. "TILE_ID12,Tile ID for partition 12" newline hexmask.quad.byte 0x40 18.--23. 1. "TILE_ID11,Tile ID for partition 11" newline hexmask.quad.byte 0x40 12.--17. 1. "TILE_ID10,Tile ID for partition 10" newline hexmask.quad.byte 0x40 6.--11. 1. "TILE_ID9,Tile ID for partition 9" newline hexmask.quad.byte 0x40 0.--5. 1. "TILE_ID8,Tile ID for partition 8" rgroup.quad 0x4178++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_USC_DM_SLOT0,Cluster Data Master in Slots" hexmask.quad.byte 0x0 60.--63. 1. "SLOT_15," newline hexmask.quad.byte 0x0 56.--59. 1. "SLOT_14," newline hexmask.quad.byte 0x0 52.--55. 1. "SLOT_13," newline hexmask.quad.byte 0x0 48.--51. 1. "SLOT_12," newline hexmask.quad.byte 0x0 44.--47. 1. "SLOT_11," newline hexmask.quad.byte 0x0 40.--43. 1. "SLOT_10," newline hexmask.quad.byte 0x0 36.--39. 1. "SLOT_9," newline hexmask.quad.byte 0x0 32.--35. 1. "SLOT_8," newline hexmask.quad.byte 0x0 28.--31. 1. "SLOT_7," newline hexmask.quad.byte 0x0 24.--27. 1. "SLOT_6," newline hexmask.quad.byte 0x0 20.--23. 1. "SLOT_5," newline hexmask.quad.byte 0x0 16.--19. 1. "SLOT_4," newline hexmask.quad.byte 0x0 12.--15. 1. "SLOT_3," newline hexmask.quad.byte 0x0 8.--11. 1. "SLOT_2," newline hexmask.quad.byte 0x0 4.--7. 1. "SLOT_1," newline hexmask.quad.byte 0x0 0.--3. 1. "SLOT_0," line.quad 0x8 "CORE_MMRS_RGX_CR_USC_DM_SLOT1,Cluster Data Master in Slots" hexmask.quad.byte 0x8 60.--63. 1. "SLOT_15," newline hexmask.quad.byte 0x8 56.--59. 1. "SLOT_14," newline hexmask.quad.byte 0x8 52.--55. 1. "SLOT_13," newline hexmask.quad.byte 0x8 48.--51. 1. "SLOT_12," newline hexmask.quad.byte 0x8 44.--47. 1. "SLOT_11," newline hexmask.quad.byte 0x8 40.--43. 1. "SLOT_10," newline hexmask.quad.byte 0x8 36.--39. 1. "SLOT_9," newline hexmask.quad.byte 0x8 32.--35. 1. "SLOT_8," newline hexmask.quad.byte 0x8 28.--31. 1. "SLOT_7," newline hexmask.quad.byte 0x8 24.--27. 1. "SLOT_6," newline hexmask.quad.byte 0x8 20.--23. 1. "SLOT_5," newline hexmask.quad.byte 0x8 16.--19. 1. "SLOT_4," newline hexmask.quad.byte 0x8 12.--15. 1. "SLOT_3," newline hexmask.quad.byte 0x8 8.--11. 1. "SLOT_2," newline hexmask.quad.byte 0x8 4.--7. 1. "SLOT_1," newline hexmask.quad.byte 0x8 0.--3. 1. "SLOT_0," line.quad 0x10 "CORE_MMRS_RGX_CR_USC_DM_SLOT2,Cluster Data Master in Slots" hexmask.quad.byte 0x10 60.--63. 1. "SLOT_15," newline hexmask.quad.byte 0x10 56.--59. 1. "SLOT_14," newline hexmask.quad.byte 0x10 52.--55. 1. "SLOT_13," newline hexmask.quad.byte 0x10 48.--51. 1. "SLOT_12," newline hexmask.quad.byte 0x10 44.--47. 1. "SLOT_11," newline hexmask.quad.byte 0x10 40.--43. 1. "SLOT_10," newline hexmask.quad.byte 0x10 36.--39. 1. "SLOT_9," newline hexmask.quad.byte 0x10 32.--35. 1. "SLOT_8," newline hexmask.quad.byte 0x10 28.--31. 1. "SLOT_7," newline hexmask.quad.byte 0x10 24.--27. 1. "SLOT_6," newline hexmask.quad.byte 0x10 20.--23. 1. "SLOT_5," newline hexmask.quad.byte 0x10 16.--19. 1. "SLOT_4," newline hexmask.quad.byte 0x10 12.--15. 1. "SLOT_3," newline hexmask.quad.byte 0x10 8.--11. 1. "SLOT_2," newline hexmask.quad.byte 0x10 4.--7. 1. "SLOT_1," newline hexmask.quad.byte 0x10 0.--3. 1. "SLOT_0," line.quad 0x18 "CORE_MMRS_RGX_CR_USC_DM_SLOT3,Cluster Data Master in Slots" hexmask.quad.byte 0x18 60.--63. 1. "SLOT_15," newline hexmask.quad.byte 0x18 56.--59. 1. "SLOT_14," newline hexmask.quad.byte 0x18 52.--55. 1. "SLOT_13," newline hexmask.quad.byte 0x18 48.--51. 1. "SLOT_12," newline hexmask.quad.byte 0x18 44.--47. 1. "SLOT_11," newline hexmask.quad.byte 0x18 40.--43. 1. "SLOT_10," newline hexmask.quad.byte 0x18 36.--39. 1. "SLOT_9," newline hexmask.quad.byte 0x18 32.--35. 1. "SLOT_8," newline hexmask.quad.byte 0x18 28.--31. 1. "SLOT_7," newline hexmask.quad.byte 0x18 24.--27. 1. "SLOT_6," newline hexmask.quad.byte 0x18 20.--23. 1. "SLOT_5," newline hexmask.quad.byte 0x18 16.--19. 1. "SLOT_4," newline hexmask.quad.byte 0x18 12.--15. 1. "SLOT_3," newline hexmask.quad.byte 0x18 8.--11. 1. "SLOT_2," newline hexmask.quad.byte 0x18 4.--7. 1. "SLOT_1," newline hexmask.quad.byte 0x18 0.--3. 1. "SLOT_0," rgroup.quad 0x41B8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_USC_EXCEPTION," hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.word 0x0 16.--31. 1. "CODE,Cluster exception code" newline hexmask.quad.word 0x0 1.--15. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "STATUS,1=Cluster has raised an exception" "?,1: Cluster has raised an exception" rgroup.quad 0x41D8++0xFF line.quad 0x0 "CORE_MMRS_RGX_CR_USC_SLOT0," hexmask.quad.long 0x0 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x0 32.--35. 1. "STATUS," newline hexmask.quad.long 0x0 1.--31. 1. "PC," newline bitfld.quad 0x0 0. "RESERVED_0," "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_USC_SLOT1," hexmask.quad.long 0x8 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x8 32.--35. 1. "STATUS," newline hexmask.quad.long 0x8 1.--31. 1. "PC," newline bitfld.quad 0x8 0. "RESERVED_0," "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_USC_SLOT2," hexmask.quad.long 0x10 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x10 32.--35. 1. "STATUS," newline hexmask.quad.long 0x10 1.--31. 1. "PC," newline bitfld.quad 0x10 0. "RESERVED_0," "0,1" line.quad 0x18 "CORE_MMRS_RGX_CR_USC_SLOT3," hexmask.quad.long 0x18 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x18 32.--35. 1. "STATUS," newline hexmask.quad.long 0x18 1.--31. 1. "PC," newline bitfld.quad 0x18 0. "RESERVED_0," "0,1" line.quad 0x20 "CORE_MMRS_RGX_CR_USC_SLOT4," hexmask.quad.long 0x20 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x20 32.--35. 1. "STATUS," newline hexmask.quad.long 0x20 1.--31. 1. "PC," newline bitfld.quad 0x20 0. "RESERVED_0," "0,1" line.quad 0x28 "CORE_MMRS_RGX_CR_USC_SLOT5," hexmask.quad.long 0x28 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x28 32.--35. 1. "STATUS," newline hexmask.quad.long 0x28 1.--31. 1. "PC," newline bitfld.quad 0x28 0. "RESERVED_0," "0,1" line.quad 0x30 "CORE_MMRS_RGX_CR_USC_SLOT6," hexmask.quad.long 0x30 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x30 32.--35. 1. "STATUS," newline hexmask.quad.long 0x30 1.--31. 1. "PC," newline bitfld.quad 0x30 0. "RESERVED_0," "0,1" line.quad 0x38 "CORE_MMRS_RGX_CR_USC_SLOT7," hexmask.quad.long 0x38 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x38 32.--35. 1. "STATUS," newline hexmask.quad.long 0x38 1.--31. 1. "PC," newline bitfld.quad 0x38 0. "RESERVED_0," "0,1" line.quad 0x40 "CORE_MMRS_RGX_CR_USC_SLOT8," hexmask.quad.long 0x40 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x40 32.--35. 1. "STATUS," newline hexmask.quad.long 0x40 1.--31. 1. "PC," newline bitfld.quad 0x40 0. "RESERVED_0," "0,1" line.quad 0x48 "CORE_MMRS_RGX_CR_USC_SLOT9," hexmask.quad.long 0x48 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x48 32.--35. 1. "STATUS," newline hexmask.quad.long 0x48 1.--31. 1. "PC," newline bitfld.quad 0x48 0. "RESERVED_0," "0,1" line.quad 0x50 "CORE_MMRS_RGX_CR_USC_SLOT10," hexmask.quad.long 0x50 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x50 32.--35. 1. "STATUS," newline hexmask.quad.long 0x50 1.--31. 1. "PC," newline bitfld.quad 0x50 0. "RESERVED_0," "0,1" line.quad 0x58 "CORE_MMRS_RGX_CR_USC_SLOT11," hexmask.quad.long 0x58 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x58 32.--35. 1. "STATUS," newline hexmask.quad.long 0x58 1.--31. 1. "PC," newline bitfld.quad 0x58 0. "RESERVED_0," "0,1" line.quad 0x60 "CORE_MMRS_RGX_CR_USC_SLOT12," hexmask.quad.long 0x60 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x60 32.--35. 1. "STATUS," newline hexmask.quad.long 0x60 1.--31. 1. "PC," newline bitfld.quad 0x60 0. "RESERVED_0," "0,1" line.quad 0x68 "CORE_MMRS_RGX_CR_USC_SLOT13," hexmask.quad.long 0x68 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x68 32.--35. 1. "STATUS," newline hexmask.quad.long 0x68 1.--31. 1. "PC," newline bitfld.quad 0x68 0. "RESERVED_0," "0,1" line.quad 0x70 "CORE_MMRS_RGX_CR_USC_SLOT14," hexmask.quad.long 0x70 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x70 32.--35. 1. "STATUS," newline hexmask.quad.long 0x70 1.--31. 1. "PC," newline bitfld.quad 0x70 0. "RESERVED_0," "0,1" line.quad 0x78 "CORE_MMRS_RGX_CR_USC_SLOT15," hexmask.quad.long 0x78 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x78 32.--35. 1. "STATUS," newline hexmask.quad.long 0x78 1.--31. 1. "PC," newline bitfld.quad 0x78 0. "RESERVED_0," "0,1" line.quad 0x80 "CORE_MMRS_RGX_CR_USC_SLOT16," hexmask.quad.long 0x80 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x80 32.--35. 1. "STATUS," newline hexmask.quad.long 0x80 1.--31. 1. "PC," newline bitfld.quad 0x80 0. "RESERVED_0," "0,1" line.quad 0x88 "CORE_MMRS_RGX_CR_USC_SLOT17," hexmask.quad.long 0x88 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x88 32.--35. 1. "STATUS," newline hexmask.quad.long 0x88 1.--31. 1. "PC," newline bitfld.quad 0x88 0. "RESERVED_0," "0,1" line.quad 0x90 "CORE_MMRS_RGX_CR_USC_SLOT18," hexmask.quad.long 0x90 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x90 32.--35. 1. "STATUS," newline hexmask.quad.long 0x90 1.--31. 1. "PC," newline bitfld.quad 0x90 0. "RESERVED_0," "0,1" line.quad 0x98 "CORE_MMRS_RGX_CR_USC_SLOT19," hexmask.quad.long 0x98 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x98 32.--35. 1. "STATUS," newline hexmask.quad.long 0x98 1.--31. 1. "PC," newline bitfld.quad 0x98 0. "RESERVED_0," "0,1" line.quad 0xA0 "CORE_MMRS_RGX_CR_USC_SLOT20," hexmask.quad.long 0xA0 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xA0 32.--35. 1. "STATUS," newline hexmask.quad.long 0xA0 1.--31. 1. "PC," newline bitfld.quad 0xA0 0. "RESERVED_0," "0,1" line.quad 0xA8 "CORE_MMRS_RGX_CR_USC_SLOT21," hexmask.quad.long 0xA8 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xA8 32.--35. 1. "STATUS," newline hexmask.quad.long 0xA8 1.--31. 1. "PC," newline bitfld.quad 0xA8 0. "RESERVED_0," "0,1" line.quad 0xB0 "CORE_MMRS_RGX_CR_USC_SLOT22," hexmask.quad.long 0xB0 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xB0 32.--35. 1. "STATUS," newline hexmask.quad.long 0xB0 1.--31. 1. "PC," newline bitfld.quad 0xB0 0. "RESERVED_0," "0,1" line.quad 0xB8 "CORE_MMRS_RGX_CR_USC_SLOT23," hexmask.quad.long 0xB8 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xB8 32.--35. 1. "STATUS," newline hexmask.quad.long 0xB8 1.--31. 1. "PC," newline bitfld.quad 0xB8 0. "RESERVED_0," "0,1" line.quad 0xC0 "CORE_MMRS_RGX_CR_USC_SLOT24," hexmask.quad.long 0xC0 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xC0 32.--35. 1. "STATUS," newline hexmask.quad.long 0xC0 1.--31. 1. "PC," newline bitfld.quad 0xC0 0. "RESERVED_0," "0,1" line.quad 0xC8 "CORE_MMRS_RGX_CR_USC_SLOT25," hexmask.quad.long 0xC8 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xC8 32.--35. 1. "STATUS," newline hexmask.quad.long 0xC8 1.--31. 1. "PC," newline bitfld.quad 0xC8 0. "RESERVED_0," "0,1" line.quad 0xD0 "CORE_MMRS_RGX_CR_USC_SLOT26," hexmask.quad.long 0xD0 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xD0 32.--35. 1. "STATUS," newline hexmask.quad.long 0xD0 1.--31. 1. "PC," newline bitfld.quad 0xD0 0. "RESERVED_0," "0,1" line.quad 0xD8 "CORE_MMRS_RGX_CR_USC_SLOT27," hexmask.quad.long 0xD8 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xD8 32.--35. 1. "STATUS," newline hexmask.quad.long 0xD8 1.--31. 1. "PC," newline bitfld.quad 0xD8 0. "RESERVED_0," "0,1" line.quad 0xE0 "CORE_MMRS_RGX_CR_USC_SLOT28," hexmask.quad.long 0xE0 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xE0 32.--35. 1. "STATUS," newline hexmask.quad.long 0xE0 1.--31. 1. "PC," newline bitfld.quad 0xE0 0. "RESERVED_0," "0,1" line.quad 0xE8 "CORE_MMRS_RGX_CR_USC_SLOT29," hexmask.quad.long 0xE8 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xE8 32.--35. 1. "STATUS," newline hexmask.quad.long 0xE8 1.--31. 1. "PC," newline bitfld.quad 0xE8 0. "RESERVED_0," "0,1" line.quad 0xF0 "CORE_MMRS_RGX_CR_USC_SLOT30," hexmask.quad.long 0xF0 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xF0 32.--35. 1. "STATUS," newline hexmask.quad.long 0xF0 1.--31. 1. "PC," newline bitfld.quad 0xF0 0. "RESERVED_0," "0,1" line.quad 0xF8 "CORE_MMRS_RGX_CR_USC_SLOT31," hexmask.quad.long 0xF8 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xF8 32.--35. 1. "STATUS," newline hexmask.quad.long 0xF8 1.--31. 1. "PC," newline bitfld.quad 0xF8 0. "RESERVED_0," "0,1" rgroup.quad 0x4300++0xFF line.quad 0x0 "CORE_MMRS_RGX_CR_USC_SLOT32," hexmask.quad.long 0x0 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x0 32.--35. 1. "STATUS," newline hexmask.quad.long 0x0 1.--31. 1. "PC," newline bitfld.quad 0x0 0. "RESERVED_0," "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_USC_SLOT33," hexmask.quad.long 0x8 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x8 32.--35. 1. "STATUS," newline hexmask.quad.long 0x8 1.--31. 1. "PC," newline bitfld.quad 0x8 0. "RESERVED_0," "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_USC_SLOT34," hexmask.quad.long 0x10 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x10 32.--35. 1. "STATUS," newline hexmask.quad.long 0x10 1.--31. 1. "PC," newline bitfld.quad 0x10 0. "RESERVED_0," "0,1" line.quad 0x18 "CORE_MMRS_RGX_CR_USC_SLOT35," hexmask.quad.long 0x18 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x18 32.--35. 1. "STATUS," newline hexmask.quad.long 0x18 1.--31. 1. "PC," newline bitfld.quad 0x18 0. "RESERVED_0," "0,1" line.quad 0x20 "CORE_MMRS_RGX_CR_USC_SLOT36," hexmask.quad.long 0x20 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x20 32.--35. 1. "STATUS," newline hexmask.quad.long 0x20 1.--31. 1. "PC," newline bitfld.quad 0x20 0. "RESERVED_0," "0,1" line.quad 0x28 "CORE_MMRS_RGX_CR_USC_SLOT37," hexmask.quad.long 0x28 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x28 32.--35. 1. "STATUS," newline hexmask.quad.long 0x28 1.--31. 1. "PC," newline bitfld.quad 0x28 0. "RESERVED_0," "0,1" line.quad 0x30 "CORE_MMRS_RGX_CR_USC_SLOT38," hexmask.quad.long 0x30 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x30 32.--35. 1. "STATUS," newline hexmask.quad.long 0x30 1.--31. 1. "PC," newline bitfld.quad 0x30 0. "RESERVED_0," "0,1" line.quad 0x38 "CORE_MMRS_RGX_CR_USC_SLOT39," hexmask.quad.long 0x38 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x38 32.--35. 1. "STATUS," newline hexmask.quad.long 0x38 1.--31. 1. "PC," newline bitfld.quad 0x38 0. "RESERVED_0," "0,1" line.quad 0x40 "CORE_MMRS_RGX_CR_USC_SLOT40," hexmask.quad.long 0x40 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x40 32.--35. 1. "STATUS," newline hexmask.quad.long 0x40 1.--31. 1. "PC," newline bitfld.quad 0x40 0. "RESERVED_0," "0,1" line.quad 0x48 "CORE_MMRS_RGX_CR_USC_SLOT41," hexmask.quad.long 0x48 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x48 32.--35. 1. "STATUS," newline hexmask.quad.long 0x48 1.--31. 1. "PC," newline bitfld.quad 0x48 0. "RESERVED_0," "0,1" line.quad 0x50 "CORE_MMRS_RGX_CR_USC_SLOT42," hexmask.quad.long 0x50 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x50 32.--35. 1. "STATUS," newline hexmask.quad.long 0x50 1.--31. 1. "PC," newline bitfld.quad 0x50 0. "RESERVED_0," "0,1" line.quad 0x58 "CORE_MMRS_RGX_CR_USC_SLOT43," hexmask.quad.long 0x58 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x58 32.--35. 1. "STATUS," newline hexmask.quad.long 0x58 1.--31. 1. "PC," newline bitfld.quad 0x58 0. "RESERVED_0," "0,1" line.quad 0x60 "CORE_MMRS_RGX_CR_USC_SLOT44," hexmask.quad.long 0x60 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x60 32.--35. 1. "STATUS," newline hexmask.quad.long 0x60 1.--31. 1. "PC," newline bitfld.quad 0x60 0. "RESERVED_0," "0,1" line.quad 0x68 "CORE_MMRS_RGX_CR_USC_SLOT45," hexmask.quad.long 0x68 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x68 32.--35. 1. "STATUS," newline hexmask.quad.long 0x68 1.--31. 1. "PC," newline bitfld.quad 0x68 0. "RESERVED_0," "0,1" line.quad 0x70 "CORE_MMRS_RGX_CR_USC_SLOT46," hexmask.quad.long 0x70 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x70 32.--35. 1. "STATUS," newline hexmask.quad.long 0x70 1.--31. 1. "PC," newline bitfld.quad 0x70 0. "RESERVED_0," "0,1" line.quad 0x78 "CORE_MMRS_RGX_CR_USC_SLOT47," hexmask.quad.long 0x78 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x78 32.--35. 1. "STATUS," newline hexmask.quad.long 0x78 1.--31. 1. "PC," newline bitfld.quad 0x78 0. "RESERVED_0," "0,1" line.quad 0x80 "CORE_MMRS_RGX_CR_USC_SLOT48," hexmask.quad.long 0x80 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x80 32.--35. 1. "STATUS," newline hexmask.quad.long 0x80 1.--31. 1. "PC," newline bitfld.quad 0x80 0. "RESERVED_0," "0,1" line.quad 0x88 "CORE_MMRS_RGX_CR_USC_SLOT49," hexmask.quad.long 0x88 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x88 32.--35. 1. "STATUS," newline hexmask.quad.long 0x88 1.--31. 1. "PC," newline bitfld.quad 0x88 0. "RESERVED_0," "0,1" line.quad 0x90 "CORE_MMRS_RGX_CR_USC_SLOT50," hexmask.quad.long 0x90 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x90 32.--35. 1. "STATUS," newline hexmask.quad.long 0x90 1.--31. 1. "PC," newline bitfld.quad 0x90 0. "RESERVED_0," "0,1" line.quad 0x98 "CORE_MMRS_RGX_CR_USC_SLOT51," hexmask.quad.long 0x98 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0x98 32.--35. 1. "STATUS," newline hexmask.quad.long 0x98 1.--31. 1. "PC," newline bitfld.quad 0x98 0. "RESERVED_0," "0,1" line.quad 0xA0 "CORE_MMRS_RGX_CR_USC_SLOT52," hexmask.quad.long 0xA0 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xA0 32.--35. 1. "STATUS," newline hexmask.quad.long 0xA0 1.--31. 1. "PC," newline bitfld.quad 0xA0 0. "RESERVED_0," "0,1" line.quad 0xA8 "CORE_MMRS_RGX_CR_USC_SLOT53," hexmask.quad.long 0xA8 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xA8 32.--35. 1. "STATUS," newline hexmask.quad.long 0xA8 1.--31. 1. "PC," newline bitfld.quad 0xA8 0. "RESERVED_0," "0,1" line.quad 0xB0 "CORE_MMRS_RGX_CR_USC_SLOT54," hexmask.quad.long 0xB0 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xB0 32.--35. 1. "STATUS," newline hexmask.quad.long 0xB0 1.--31. 1. "PC," newline bitfld.quad 0xB0 0. "RESERVED_0," "0,1" line.quad 0xB8 "CORE_MMRS_RGX_CR_USC_SLOT55," hexmask.quad.long 0xB8 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xB8 32.--35. 1. "STATUS," newline hexmask.quad.long 0xB8 1.--31. 1. "PC," newline bitfld.quad 0xB8 0. "RESERVED_0," "0,1" line.quad 0xC0 "CORE_MMRS_RGX_CR_USC_SLOT56," hexmask.quad.long 0xC0 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xC0 32.--35. 1. "STATUS," newline hexmask.quad.long 0xC0 1.--31. 1. "PC," newline bitfld.quad 0xC0 0. "RESERVED_0," "0,1" line.quad 0xC8 "CORE_MMRS_RGX_CR_USC_SLOT57," hexmask.quad.long 0xC8 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xC8 32.--35. 1. "STATUS," newline hexmask.quad.long 0xC8 1.--31. 1. "PC," newline bitfld.quad 0xC8 0. "RESERVED_0," "0,1" line.quad 0xD0 "CORE_MMRS_RGX_CR_USC_SLOT58," hexmask.quad.long 0xD0 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xD0 32.--35. 1. "STATUS," newline hexmask.quad.long 0xD0 1.--31. 1. "PC," newline bitfld.quad 0xD0 0. "RESERVED_0," "0,1" line.quad 0xD8 "CORE_MMRS_RGX_CR_USC_SLOT59," hexmask.quad.long 0xD8 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xD8 32.--35. 1. "STATUS," newline hexmask.quad.long 0xD8 1.--31. 1. "PC," newline bitfld.quad 0xD8 0. "RESERVED_0," "0,1" line.quad 0xE0 "CORE_MMRS_RGX_CR_USC_SLOT60," hexmask.quad.long 0xE0 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xE0 32.--35. 1. "STATUS," newline hexmask.quad.long 0xE0 1.--31. 1. "PC," newline bitfld.quad 0xE0 0. "RESERVED_0," "0,1" line.quad 0xE8 "CORE_MMRS_RGX_CR_USC_SLOT61," hexmask.quad.long 0xE8 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xE8 32.--35. 1. "STATUS," newline hexmask.quad.long 0xE8 1.--31. 1. "PC," newline bitfld.quad 0xE8 0. "RESERVED_0," "0,1" line.quad 0xF0 "CORE_MMRS_RGX_CR_USC_SLOT62," hexmask.quad.long 0xF0 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xF0 32.--35. 1. "STATUS," newline hexmask.quad.long 0xF0 1.--31. 1. "PC," newline bitfld.quad 0xF0 0. "RESERVED_0," "0,1" line.quad 0xF8 "CORE_MMRS_RGX_CR_USC_SLOT63," hexmask.quad.long 0xF8 36.--63. 1. "RESERVED_36," newline hexmask.quad.byte 0xF8 32.--35. 1. "STATUS," newline hexmask.quad.long 0xF8 1.--31. 1. "PC," newline bitfld.quad 0xF8 0. "RESERVED_0," "0,1" rgroup.quad 0x4500++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_USC_BREAKPOINT1," hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 1.--31. 1. "ADDR,Breakpoint Address" newline rbitfld.quad 0x0 0. "RESERVED_0," "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_USC_BREAKPOINT1_HANDLER," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 1.--31. 1. "ADDR,Breakpoint Handler Address" newline rbitfld.quad 0x8 0. "RESERVED_0," "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_USC_BREAKPOINT1_CTRL," hexmask.quad 0x10 4.--63. 1. "RESERVED_4," newline bitfld.quad 0x10 3. "ENABLE,0 = Breakpoint disabled 1 = Breakpoint enabled" "0: Breakpoint disabled,1: Breakpoint enabled" newline bitfld.quad 0x10 0.--2. "DM,Data Master of Breakpoint" "0,1,2,3,4,5,6,7" rgroup.quad 0x45D8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_USC_IDLE," hexmask.quad 0x0 10.--63. 1. "RESERVED_10," newline bitfld.quad 0x0 9. "USCITR,USCITR idle" "0,1" newline bitfld.quad 0x0 8. "USCDMA,USCDMA idle" "0,1" newline bitfld.quad 0x0 7. "USCFS,USCFS idle" "0,1" newline bitfld.quad 0x0 6. "USCCS,USCCS idle" "0,1" newline bitfld.quad 0x0 5. "USCPD3,USCPD idle" "0,1" newline bitfld.quad 0x0 4. "USCPD2,USCPD idle" "0,1" newline bitfld.quad 0x0 3. "USCPD1,USCPD idle" "0,1" newline bitfld.quad 0x0 2. "USCPD0,USCPD idle" "0,1" newline bitfld.quad 0x0 1. "USCPC,USCPC idle" "0,1" newline bitfld.quad 0x0 0. "USCC,USCC idle" "0,1" rgroup.quad 0x45E8++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_USC_ITRCOEFF_CACHE,USC Iterator Coefficient Cache Bypass bit" hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "BYPASS,Bypass bit of the coefficient cache" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_USC_ITRSMP_STATE_CACHE,USC ITRSMP State Cache Bypass bit" hexmask.quad 0x8 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x8 0. "BYPASS,Bypass bit of the state cache" "0,1" rgroup.quad 0x4600++0x77 line.quad 0x0 "CORE_MMRS_RGX_CR_USC_PWR_INSTR,Peformance counter associated with Power Monitoring" hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "EXEC,Number of instructions executed [max 1 per clock]" line.quad 0x8 "CORE_MMRS_RGX_CR_USC_PWR_CMMN_STR_ACCESS,Peformance counter associated with Power Monitoring" hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "COUNT,Number of Common Store accesses [max of 4 per lock]" line.quad 0x10 "CORE_MMRS_RGX_CR_USC_PWR_CMMN_STR,Peformance counter associated with Power Monitoring" hexmask.quad.long 0x10 32.--63. 1. "RD_BANK_CLASH,Common Store: Number of read/read bank clashes" newline hexmask.quad.long 0x10 0.--31. 1. "WR_BANK_CLASH,Common Store: Number of write/write bank clashes" line.quad 0x18 "CORE_MMRS_RGX_CR_USC_PWR_UNI_STR,Peformance counter associated with Power Monitoring" hexmask.quad.long 0x18 32.--63. 1. "RD_BANK_CLASH,Unified Store: Number of read/read bank clashes" newline hexmask.quad.long 0x18 0.--31. 1. "WR_BANK_CLASH,Unified Store: Number of write/write bank clashes" line.quad 0x20 "CORE_MMRS_RGX_CR_USC_PWR_NUM_FLOAT,Peformance counter associated with Power Monitoring" hexmask.quad.long 0x20 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x20 0.--31. 1. "OPS,Number of floating point ops; FAdd/Fmul=1 MAD=2; max 32x2=64 per clock" line.quad 0x28 "CORE_MMRS_RGX_CR_USC_PWR_NUM_INTEGER,Peformance counter associated with Power Monitoring" hexmask.quad.long 0x28 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x28 0.--31. 1. "OPS,Number of integer ops; Add/Mul=1 MAD=2 max 16*2=32 per clock" line.quad 0x30 "CORE_MMRS_RGX_CR_USC_PWR_NUM_COALU,Peformance counter associated with Power Monitoring" hexmask.quad.long 0x30 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x30 0.--31. 1. "OPS,Number of COALU ops; max of 16 per clock" line.quad 0x38 "CORE_MMRS_RGX_CR_USC_PWR_NUM,Peformance counter associated with Power Monitoring" hexmask.quad.long 0x38 32.--63. 1. "ITERATIONS,Number of iterates" newline hexmask.quad.long 0x38 0.--31. 1. "PENALTY_CYCLES,Penalty cycles for read/read and write/write clashes. For each instruction this is max[a b c d]" line.quad 0x40 "CORE_MMRS_RGX_CR_USC_PWR_AV_NUM_INST_VALID,Peformance counter associated with Power Monitoring" hexmask.quad.long 0x40 32.--63. 1. "PIXEL,Average number of instances valid out of 16 for pixel tasks" newline hexmask.quad.long 0x40 0.--31. 1. "VERT,Average number of instances valid out of 16 for vertex tasks" line.quad 0x48 "CORE_MMRS_RGX_CR_USC_PWR_NUM_ON_EDGE_PIXL,Peformance counter associated with Power Monitoring" hexmask.quad.long 0x48 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x48 0.--31. 1. "WRITE,Number of on-edge pixel output register writes" line.quad 0x50 "CORE_MMRS_RGX_CR_USC_PWR_NUM_OFF_EDGE_PIXL,Peformance counter associated with Power Monitoring" hexmask.quad.long 0x50 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x50 0.--31. 1. "WRITE,Number of off-edge pixel output register writes" line.quad 0x58 "CORE_MMRS_RGX_CR_USC_PWR_NUM_F16,Peformance counter associated with Power Monitoring" hexmask.quad.long 0x58 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x58 0.--31. 1. "OPS,Number of F16 operations. Max of 16" line.quad 0x60 "CORE_MMRS_RGX_CR_USC_PWR_USCPD_INSTR,Peformance counter associated with Power Monitoring" hexmask.quad.long 0x60 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x60 0.--31. 1. "COUNT,Number of instructions executed by USCPD" line.quad 0x68 "CORE_MMRS_RGX_CR_USC_PWR_INT_REG_ACCESS,Peformance counter associated with Power Monitoring" hexmask.quad.long 0x68 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x68 0.--31. 1. "COUNT,Number of internal register accesses. Max 128 per clock = 8 registers * 16 instances" line.quad 0x70 "CORE_MMRS_RGX_CR_USC_PWR_US_STR_ACCESS,Peformance counter associated with Power Monitoring" hexmask.quad.long 0x70 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x70 0.--31. 1. "COUNT,Number of unified sotre US bank accesses. Max of 32 per clock = 8 banks * 4 pipes" rgroup.quad 0x4678++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_USC_HQ_RESCH,Disable rescheduling of slots in USCPC HQ" hexmask.quad 0x0 2.--63. 1. "RESERVED_2," newline bitfld.quad 0x0 1. "DISABLE_FOR_BE,Disable rescheduling for BE instr in USCPC" "0,1" newline bitfld.quad 0x0 0. "DISABLE,Disable rescheduling in USCPC" "0,1" rgroup.quad 0x5000++0x8F line.quad 0x0 "CORE_MMRS_RGX_CR_USC_UVS0_CHECKSUM," hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC0" line.quad 0x8 "CORE_MMRS_RGX_CR_USC_UVS1_CHECKSUM," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC1" line.quad 0x10 "CORE_MMRS_RGX_CR_USC_UVS2_CHECKSUM," hexmask.quad.long 0x10 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x10 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC2" line.quad 0x18 "CORE_MMRS_RGX_CR_USC_UVS3_CHECKSUM," hexmask.quad.long 0x18 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x18 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC3" line.quad 0x20 "CORE_MMRS_RGX_CR_PPP_SIGNATURE," hexmask.quad.long 0x20 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x20 0.--31. 1. "VALUE,Signature of PPP to Clipper Interface" line.quad 0x28 "CORE_MMRS_RGX_CR_TE_SIGNATURE," hexmask.quad.long 0x28 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x28 0.--31. 1. "VALUE,Signature of TE control stream writes" line.quad 0x30 "CORE_MMRS_RGX_CR_VCE_CHECKSUM," hexmask.quad.long 0x30 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x30 0.--31. 1. "VALUE,Checksum of VCE memory writes" line.quad 0x38 "CORE_MMRS_RGX_CR_ISP_PDS_CHECKSUM," hexmask.quad.long 0x38 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x38 0.--31. 1. "VALUE,Checksum of ISP PDS Span Output" line.quad 0x40 "CORE_MMRS_RGX_CR_ISP_TPF_CHECKSUM," hexmask.quad.long 0x40 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x40 0.--31. 1. "VALUE,Checksum of ISP TPF Object Output" line.quad 0x48 "CORE_MMRS_RGX_CR_TFPU_PLANE0_CHECKSUM," hexmask.quad.long 0x48 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x48 0.--31. 1. "VALUE,Checksum of TFPU Plane0 Output" line.quad 0x50 "CORE_MMRS_RGX_CR_TFPU_PLANE1_CHECKSUM," hexmask.quad.long 0x50 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x50 0.--31. 1. "VALUE,Checksum of TFPU Plane1 Output" line.quad 0x58 "CORE_MMRS_RGX_CR_PBE_CHECKSUM," hexmask.quad.long 0x58 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x58 0.--31. 1. "VALUE,Checksum of PBE memory writes" line.quad 0x60 "CORE_MMRS_RGX_CR_PDS_DOUTM_STM_SIGNATURE," hexmask.quad.long 0x60 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x60 0.--31. 1. "VALUE,Signature of PDS DOUTM Stream Out MCU writes" line.quad 0x68 "CORE_MMRS_RGX_CR_IFPU_ISP_CHECKSUM," hexmask.quad.long 0x68 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x68 0.--31. 1. "VALUE,Checksum of IFPU Output" line.quad 0x70 "CORE_MMRS_RGX_CR_MCU_L0_TA_CHECKSUM," hexmask.quad.long 0x70 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x70 0.--31. 1. "VALUE,Checksum of the PDS->USC from MCU for TA data" line.quad 0x78 "CORE_MMRS_RGX_CR_MCU_L0_3D_CHECKSUM," hexmask.quad.long 0x78 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x78 0.--31. 1. "VALUE,Checksum of the PDS->USC from MCU for 3D data" line.quad 0x80 "CORE_MMRS_RGX_CR_MCU_L0_WRAP_TA_CHECKSUM," hexmask.quad.long 0x80 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x80 0.--31. 1. "VALUE,Checksum of the PDS->USC from MCU for TA data" line.quad 0x88 "CORE_MMRS_RGX_CR_MCU_L0_WRAP_3D_CHECKSUM," hexmask.quad.long 0x88 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x88 0.--31. 1. "VALUE,Checksum of the PDS->USC from MCU for 3D data" rgroup.quad 0x5100++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_USC_UVS4_CHECKSUM," hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC4" line.quad 0x8 "CORE_MMRS_RGX_CR_USC_UVS5_CHECKSUM," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC5" rgroup.quad 0x5160++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PBE_CHECKSUM_NO_ADDR," hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "VALUE,No address checksum of PBE memory writes" rgroup.quad 0x6000++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PERF_COUNTER," hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "RESET,A write of 1 to this register resets the Cycle Counters and holds them in Reset. A write of 0 enables them for Counting" "0,1" rgroup.quad 0x6008++0x6F line.quad 0x0 "CORE_MMRS_RGX_CR_PERF_TA_PHASE," hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "COUNT,The number of TA phases completed" line.quad 0x8 "CORE_MMRS_RGX_CR_PERF_3D_PHASE," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "COUNT,The number of 3D phases completed" line.quad 0x10 "CORE_MMRS_RGX_CR_PERF_COMPUTE_PHASE," hexmask.quad.long 0x10 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x10 0.--31. 1. "COUNT,The number of Compute phases completed" line.quad 0x18 "CORE_MMRS_RGX_CR_PERF_TA_CYCLE," hexmask.quad.long 0x18 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x18 0.--31. 1. "COUNT,The number of cycles spent in TA phases" line.quad 0x20 "CORE_MMRS_RGX_CR_PERF_3D_CYCLE," hexmask.quad.long 0x20 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x20 0.--31. 1. "COUNT,The number of cycles spent in 3D phases" line.quad 0x28 "CORE_MMRS_RGX_CR_PERF_COMPUTE_CYCLE," hexmask.quad.long 0x28 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x28 0.--31. 1. "COUNT,The number of cycles spent in Compute phases" line.quad 0x30 "CORE_MMRS_RGX_CR_PERF_TA_OR_3D_CYCLE," hexmask.quad.long 0x30 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x30 0.--31. 1. "COUNT,The number of cycles spent in TA phases or 3D phases" line.quad 0x38 "CORE_MMRS_RGX_CR_PERF_INITIAL_TA_CYCLE," hexmask.quad.long 0x38 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x38 0.--31. 1. "COUNT,The number of cycles spent in TA phases before the first 3D phase" line.quad 0x40 "CORE_MMRS_RGX_CR_PERF_FINAL_3D_CYCLE," hexmask.quad.long 0x40 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x40 0.--31. 1. "COUNT,The number of cycles spent in the last 3D phase" line.quad 0x48 "CORE_MMRS_RGX_CR_PERF_BIF0_READ," hexmask.quad.long 0x48 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x48 0.--31. 1. "COUNT,The number of BIF0-to-SLC reads" line.quad 0x50 "CORE_MMRS_RGX_CR_PERF_BIF0_WRITE," hexmask.quad.long 0x50 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x50 0.--31. 1. "COUNT,The number of BIF0-to-SLC writes" line.quad 0x58 "CORE_MMRS_RGX_CR_PERF_BIF0_BYTE_WRITE," hexmask.quad.long 0x58 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x58 0.--31. 1. "COUNT,The number of BIF0-to-SLC bytes written" line.quad 0x60 "CORE_MMRS_RGX_CR_PERF_BIF0_READ_STALL," hexmask.quad.long 0x60 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x60 0.--31. 1. "COUNT,The number of BIF0-to-SLC read stalls" line.quad 0x68 "CORE_MMRS_RGX_CR_PERF_BIF0_WRITE_STALL," hexmask.quad.long 0x68 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x68 0.--31. 1. "COUNT,The number of BIF0-to-SLC write stalls" rgroup.quad 0x60A0++0x27 line.quad 0x0 "CORE_MMRS_RGX_CR_PERF_SLC0_READ," hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 0 reads" line.quad 0x8 "CORE_MMRS_RGX_CR_PERF_SLC0_WRITE," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 0 writes" line.quad 0x10 "CORE_MMRS_RGX_CR_PERF_SLC0_BYTE_WRITE," hexmask.quad.long 0x10 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x10 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 0 bytes written" line.quad 0x18 "CORE_MMRS_RGX_CR_PERF_SLC0_READ_STALL," hexmask.quad.long 0x18 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x18 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 0 command stalls" line.quad 0x20 "CORE_MMRS_RGX_CR_PERF_SLC0_WRITE_STALL," hexmask.quad.long 0x20 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x20 0.--31. 1. "COUNT,The number of SLC-to-MEM insterface 0 write channel stalls" rgroup.quad 0x60F0++0x37 line.quad 0x0 "CORE_MMRS_RGX_CR_PERF_SLC_BURST_SIZE0_IN," hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "VALUE,The number of burstlength 0 accesses into the Burst Combiner" line.quad 0x8 "CORE_MMRS_RGX_CR_PERF_SLC_BURST_SIZE1_IN," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "VALUE,The number of burstlength 1 accesses into the Burst Combiner" line.quad 0x10 "CORE_MMRS_RGX_CR_PERF_SLC_BURST_SIZE0_OUT," hexmask.quad.long 0x10 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x10 0.--31. 1. "VALUE,The number of burstlength 0 accesses out of the Burst Combiner" line.quad 0x18 "CORE_MMRS_RGX_CR_PERF_SLC_BURST_SIZE1_OUT," hexmask.quad.long 0x18 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x18 0.--31. 1. "VALUE,The number of burstlength 1 accesses out of the Burst Combiner" line.quad 0x20 "CORE_MMRS_RGX_CR_PERF_SLC_BURST_SIZE2_OUT," hexmask.quad.long 0x20 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x20 0.--31. 1. "VALUE,The number of burstlength 2 accesses out of the Burst Combiner" line.quad 0x28 "CORE_MMRS_RGX_CR_PERF_SLC0_READ_ID_STALL," hexmask.quad.long 0x28 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x28 0.--31. 1. "COUNT,The number of cycles the SLC spends stalled because all Read IDs on memory interface 0 are currently in use" line.quad 0x30 "CORE_MMRS_RGX_CR_PERF_SLC0_WRITE_ID_STALL," hexmask.quad.long 0x30 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x30 0.--31. 1. "COUNT,The number of cycles the SLC spends stalled because all Write IDs on memory interface 0 are currently in use" rgroup.quad 0x6138++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PERF_SLC_BURST_SIZE3_OUT," hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "VALUE,The number of burstlength 3 accesses out of the Burst Combiner" rgroup.quad 0x6190++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_PERF_SLC_BURST_SIZE2_IN," hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "VALUE,The number of burstlength 2 accesses into the Burst Combiner" line.quad 0x8 "CORE_MMRS_RGX_CR_PERF_SLC_BURST_SIZE3_IN," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "VALUE,The number of burstlength 3 accesses into the Burst Combiner" rgroup.quad 0x6220++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PERF_3D_SPINUP," hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "CYCLES,The number of cycles it takes the 3D pipeline to spin-up" rgroup.quad 0x6300++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_POWER_ESTIMATE_REQ_RST,Power estimate Request/Reset - The generation of the power estimate will be initiated upon a write to the power" hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "VALUE," "0,1" rgroup.quad 0x6310++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_POWER_ESTIMATE_SAMPLE_COUNT,Power Estimate Sample Count - This defines the number of cycles over which power monitoring will occur." hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "VALUE," rgroup.quad 0x6318++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_POWER_ESTIMATE_READY,Power estimate Ready - A system event (portmap signal and maskable interrupt) is output when the power estimate has" hexmask.quad 0x0 15.--63. 1. "RESERVED_15," newline bitfld.quad 0x0 14. "SLC," "0,1" newline bitfld.quad 0x0 13. "TILING," "0,1" newline bitfld.quad 0x0 12. "JONES," "0,1" newline bitfld.quad 0x0 10.--11. "RESERVED_10," "0,1,2,3" newline bitfld.quad 0x0 9. "TA," "0,1" newline bitfld.quad 0x0 8. "RASTERISATION," "0,1" newline bitfld.quad 0x0 7. "HUB," "0,1" newline bitfld.quad 0x0 6. "BIFPMCACHE," "0,1" newline bitfld.quad 0x0 5. "RESERVED_5," "0,1" newline bitfld.quad 0x0 4. "TPU_MCU," "0,1" newline bitfld.quad 0x0 1.--3. "RESERVED_1," "0,1,2,3,4,5,6,7" newline bitfld.quad 0x0 0. "USC," "0,1" rgroup.quad 0x6320++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_POWER_ESTIMATE_GAIN_COEFF,Final Gain coefficient to apply to summation of all power monitoring quotients" hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "VALUE," line.quad 0x8 "CORE_MMRS_RGX_CR_POWER_ESTIMATE_RESULT,Power Estimate Result. This represents the estimation of the total system power usage." hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "VALUE," line.quad 0x10 "CORE_MMRS_RGX_CR_PERF_COUNT_MODE_ONLY,This register bit set means we need to do only perf-counter gathering and nothing to do with pwr-perf related counting" hexmask.quad 0x10 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x10 0. "VALUE," "0,1" rgroup.quad 0x6500++0x2F line.quad 0x0 "CORE_MMRS_RGX_CR_AVG_NON_CRITICAL_MEM0_LATENCY," hexmask.quad 0x0 12.--63. 1. "RESERVED_12," newline hexmask.quad.word 0x0 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for non critical tag" line.quad 0x8 "CORE_MMRS_RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY," hexmask.quad 0x8 12.--63. 1. "RESERVED_12," newline hexmask.quad.word 0x8 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for non critical tag" line.quad 0x10 "CORE_MMRS_RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY," hexmask.quad 0x10 12.--63. 1. "RESERVED_12," newline hexmask.quad.word 0x10 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for non critical tag" line.quad 0x18 "CORE_MMRS_RGX_CR_AVG_CRITICAL_MEM0_LATENCY," hexmask.quad 0x18 12.--63. 1. "RESERVED_12," newline hexmask.quad.word 0x18 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for critical tag" line.quad 0x20 "CORE_MMRS_RGX_CR_MIN_CRITICAL_MEM0_LATENCY," hexmask.quad 0x20 12.--63. 1. "RESERVED_12," newline hexmask.quad.word 0x20 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for critical tag" line.quad 0x28 "CORE_MMRS_RGX_CR_MAX_CRITICAL_MEM0_LATENCY," hexmask.quad 0x28 12.--63. 1. "RESERVED_12," newline hexmask.quad.word 0x28 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for critical tag" rgroup.quad 0x6530++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_USER_DEFINED_MEM0_MH_TAG,Writing '1' followed by mh_tag value at the lsb end of this register starts the user defined mh_tag value for latency calculation." hexmask.quad 0x0 7.--63. 1. "RESERVED_7," newline hexmask.quad.byte 0x0 0.--6. 1. "VALUE," rgroup.quad 0x6538++0x27 line.quad 0x0 "CORE_MMRS_RGX_CR_AVG_USER_MH_TAG_MEM0_LATENCY," hexmask.quad 0x0 12.--63. 1. "RESERVED_12," newline hexmask.quad.word 0x0 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for user_defined tag" line.quad 0x8 "CORE_MMRS_RGX_CR_MIN_USER_MH_TAG_MEM0_LATENCY," hexmask.quad 0x8 12.--63. 1. "RESERVED_12," newline hexmask.quad.word 0x8 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for user defined tag" line.quad 0x10 "CORE_MMRS_RGX_CR_MAX_USER_MH_TAG_MEM0_LATENCY," hexmask.quad 0x10 12.--63. 1. "RESERVED_12," newline hexmask.quad.word 0x10 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for user defined tag" line.quad 0x18 "CORE_MMRS_RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_MH_TAG," hexmask.quad 0x18 6.--63. 1. "RESERVED_6," newline hexmask.quad.byte 0x18 0.--5. 1. "VALUE,The mh_tag value of min read latency cycles for non critical tag" line.quad 0x20 "CORE_MMRS_RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_MH_TAG," hexmask.quad 0x20 6.--63. 1. "RESERVED_6," newline hexmask.quad.byte 0x20 0.--5. 1. "VALUE,The mh_tag value of max read latency cycles for non critical tag" rgroup.quad 0x7600++0x27 line.quad 0x0 "CORE_MMRS_RGX_CR_TA_PERF," hexmask.quad 0x0 5.--63. 1. "RESERVED_5," newline bitfld.quad 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.quad 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.quad 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.quad 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.quad 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_TA_PERF_SELECT0," hexmask.quad 0x8 22.--63. 1. "RESERVED_22," newline bitfld.quad 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.quad.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.quad 0x10 "CORE_MMRS_RGX_CR_TA_PERF_SELECT1," hexmask.quad 0x10 22.--63. 1. "RESERVED_22," newline bitfld.quad 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.quad.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.quad 0x18 "CORE_MMRS_RGX_CR_TA_PERF_SELECT2," hexmask.quad 0x18 22.--63. 1. "RESERVED_22," newline bitfld.quad 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.quad.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.quad 0x20 "CORE_MMRS_RGX_CR_TA_PERF_SELECT3," hexmask.quad 0x20 22.--63. 1. "RESERVED_22," newline bitfld.quad 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.quad.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" rgroup.quad 0x7648++0x27 line.quad 0x0 "CORE_MMRS_RGX_CR_TA_PERF_SELECTED_BITS," hexmask.quad.word 0x0 48.--63. 1. "REG3,present bus signals counter 3" newline hexmask.quad.word 0x0 32.--47. 1. "REG2,present bus signals counter 2" newline hexmask.quad.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.quad.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" line.quad 0x8 "CORE_MMRS_RGX_CR_TA_PERF_COUNTER_0," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "REG,counter a0" line.quad 0x10 "CORE_MMRS_RGX_CR_TA_PERF_COUNTER_1," hexmask.quad.long 0x10 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x10 0.--31. 1. "REG,counter a0" line.quad 0x18 "CORE_MMRS_RGX_CR_TA_PERF_COUNTER_2," hexmask.quad.long 0x18 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x18 0.--31. 1. "REG,counter a0" line.quad 0x20 "CORE_MMRS_RGX_CR_TA_PERF_COUNTER_3," hexmask.quad.long 0x20 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x20 0.--31. 1. "REG,counter a0" rgroup.quad 0x7700++0x27 line.quad 0x0 "CORE_MMRS_RGX_CR_RASTERISATION_PERF," hexmask.quad 0x0 5.--63. 1. "RESERVED_5," newline bitfld.quad 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.quad 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.quad 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.quad 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.quad 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_RASTERISATION_PERF_SELECT0," hexmask.quad 0x8 22.--63. 1. "RESERVED_22," newline bitfld.quad 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documenrasterisationtion for signals in each group" newline hexmask.quad.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.quad 0x10 "CORE_MMRS_RGX_CR_RASTERISATION_PERF_SELECT1," hexmask.quad 0x10 22.--63. 1. "RESERVED_22," newline bitfld.quad 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documenrasterisationtion for signals in each group" newline hexmask.quad.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.quad 0x18 "CORE_MMRS_RGX_CR_RASTERISATION_PERF_SELECT2," hexmask.quad 0x18 22.--63. 1. "RESERVED_22," newline bitfld.quad 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documenrasterisationtion for signals in each group" newline hexmask.quad.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.quad 0x20 "CORE_MMRS_RGX_CR_RASTERISATION_PERF_SELECT3," hexmask.quad 0x20 22.--63. 1. "RESERVED_22," newline bitfld.quad 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documenrasterisationtion for signals in each group" newline hexmask.quad.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" rgroup.quad 0x7748++0x27 line.quad 0x0 "CORE_MMRS_RGX_CR_RASTERISATION_PERF_SELECTED_BITS," hexmask.quad.word 0x0 48.--63. 1. "REG3,present bus signals counter 3" newline hexmask.quad.word 0x0 32.--47. 1. "REG2,present bus signals counter 2" newline hexmask.quad.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.quad.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" line.quad 0x8 "CORE_MMRS_RGX_CR_RASTERISATION_PERF_COUNTER_0," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "REG,counter a0" line.quad 0x10 "CORE_MMRS_RGX_CR_RASTERISATION_PERF_COUNTER_1," hexmask.quad.long 0x10 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x10 0.--31. 1. "REG,counter a0" line.quad 0x18 "CORE_MMRS_RGX_CR_RASTERISATION_PERF_COUNTER_2," hexmask.quad.long 0x18 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x18 0.--31. 1. "REG,counter a0" line.quad 0x20 "CORE_MMRS_RGX_CR_RASTERISATION_PERF_COUNTER_3," hexmask.quad.long 0x20 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x20 0.--31. 1. "REG,counter a0" rgroup.quad 0x7800++0x27 line.quad 0x0 "CORE_MMRS_RGX_CR_HUB_BIFPMCACHE_PERF," hexmask.quad 0x0 5.--63. 1. "RESERVED_5," newline bitfld.quad 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.quad 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.quad 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.quad 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.quad 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_HUB_BIFPMCACHE_PERF_SELECT0," hexmask.quad 0x8 22.--63. 1. "RESERVED_22," newline bitfld.quad 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documenhub_bifpmcachetion for signals in each group" newline hexmask.quad.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.quad 0x10 "CORE_MMRS_RGX_CR_HUB_BIFPMCACHE_PERF_SELECT1," hexmask.quad 0x10 22.--63. 1. "RESERVED_22," newline bitfld.quad 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documenhub_bifpmcachetion for signals in each group" newline hexmask.quad.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.quad 0x18 "CORE_MMRS_RGX_CR_HUB_BIFPMCACHE_PERF_SELECT2," hexmask.quad 0x18 22.--63. 1. "RESERVED_22," newline bitfld.quad 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documenhub_bifpmcachetion for signals in each group" newline hexmask.quad.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.quad 0x20 "CORE_MMRS_RGX_CR_HUB_BIFPMCACHE_PERF_SELECT3," hexmask.quad 0x20 22.--63. 1. "RESERVED_22," newline bitfld.quad 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documenhub_bifpmcachetion for signals in each group" newline hexmask.quad.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" rgroup.quad 0x7848++0x27 line.quad 0x0 "CORE_MMRS_RGX_CR_HUB_BIFPMCACHE_PERF_SELECTED_BITS," hexmask.quad.word 0x0 48.--63. 1. "REG3,present bus signals counter 3" newline hexmask.quad.word 0x0 32.--47. 1. "REG2,present bus signals counter 2" newline hexmask.quad.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.quad.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" line.quad 0x8 "CORE_MMRS_RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_0," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "REG,counter a0" line.quad 0x10 "CORE_MMRS_RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_1," hexmask.quad.long 0x10 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x10 0.--31. 1. "REG,counter a0" line.quad 0x18 "CORE_MMRS_RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_2," hexmask.quad.long 0x18 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x18 0.--31. 1. "REG,counter a0" line.quad 0x20 "CORE_MMRS_RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_3," hexmask.quad.long 0x20 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x20 0.--31. 1. "REG,counter a0" rgroup.quad 0x7900++0x27 line.quad 0x0 "CORE_MMRS_RGX_CR_TPU_MCU_L0_PERF," hexmask.quad 0x0 5.--63. 1. "RESERVED_5," newline bitfld.quad 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.quad 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.quad 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.quad 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.quad 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_TPU_MCU_L0_PERF_SELECT0," rbitfld.quad 0x8 62.--63. "RESERVED_62," "0,1,2,3" newline hexmask.quad.word 0x8 48.--61. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline rbitfld.quad 0x8 46.--47. "RESERVED_46," "0,1,2,3" newline hexmask.quad.word 0x8 32.--45. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" newline hexmask.quad.word 0x8 22.--31. 1. "RESERVED_22," newline bitfld.quad 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.quad.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.quad 0x10 "CORE_MMRS_RGX_CR_TPU_MCU_L0_PERF_SELECT1," rbitfld.quad 0x10 62.--63. "RESERVED_62," "0,1,2,3" newline hexmask.quad.word 0x10 48.--61. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline rbitfld.quad 0x10 46.--47. "RESERVED_46," "0,1,2,3" newline hexmask.quad.word 0x10 32.--45. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" newline hexmask.quad.word 0x10 22.--31. 1. "RESERVED_22," newline bitfld.quad 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.quad.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.quad 0x18 "CORE_MMRS_RGX_CR_TPU_MCU_L0_PERF_SELECT2," rbitfld.quad 0x18 62.--63. "RESERVED_62," "0,1,2,3" newline hexmask.quad.word 0x18 48.--61. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline rbitfld.quad 0x18 46.--47. "RESERVED_46," "0,1,2,3" newline hexmask.quad.word 0x18 32.--45. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" newline hexmask.quad.word 0x18 22.--31. 1. "RESERVED_22," newline bitfld.quad 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.quad.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.quad 0x20 "CORE_MMRS_RGX_CR_TPU_MCU_L0_PERF_SELECT3," rbitfld.quad 0x20 62.--63. "RESERVED_62," "0,1,2,3" newline hexmask.quad.word 0x20 48.--61. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline rbitfld.quad 0x20 46.--47. "RESERVED_46," "0,1,2,3" newline hexmask.quad.word 0x20 32.--45. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" newline hexmask.quad.word 0x20 22.--31. 1. "RESERVED_22," newline bitfld.quad 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.quad.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" rgroup.quad 0x7948++0x27 line.quad 0x0 "CORE_MMRS_RGX_CR_TPU_MCU_L0_PERF_SELECTED_BITS," hexmask.quad.word 0x0 48.--63. 1. "REG3,present bus signals counter 3" newline hexmask.quad.word 0x0 32.--47. 1. "REG2,present bus signals counter 2" newline hexmask.quad.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.quad.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" line.quad 0x8 "CORE_MMRS_RGX_CR_TPU_MCU_L0_PERF_COUNTER_0," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "REG,counter a0" line.quad 0x10 "CORE_MMRS_RGX_CR_TPU_MCU_L0_PERF_COUNTER_1," hexmask.quad.long 0x10 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x10 0.--31. 1. "REG,counter a0" line.quad 0x18 "CORE_MMRS_RGX_CR_TPU_MCU_L0_PERF_COUNTER_2," hexmask.quad.long 0x18 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x18 0.--31. 1. "REG,counter a0" line.quad 0x20 "CORE_MMRS_RGX_CR_TPU_MCU_L0_PERF_COUNTER_3," hexmask.quad.long 0x20 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x20 0.--31. 1. "REG,counter a0" rgroup.quad 0x8020++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_USC_TPU_LOW_PRECISION_ENABLE,Enable signal to use low precision across USC and TPU (TAG) in coordinates." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "VALUE," "0,1" rgroup.quad 0x8100++0x27 line.quad 0x0 "CORE_MMRS_RGX_CR_USC_PERF," hexmask.quad 0x0 5.--63. 1. "RESERVED_5," newline bitfld.quad 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.quad 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.quad 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.quad 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.quad 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_USC_PERF_SELECT0," rbitfld.quad 0x8 62.--63. "RESERVED_62," "0,1,2,3" newline hexmask.quad.word 0x8 48.--61. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline rbitfld.quad 0x8 46.--47. "RESERVED_46," "0,1,2,3" newline hexmask.quad.word 0x8 32.--45. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" newline hexmask.quad.word 0x8 22.--31. 1. "RESERVED_22," newline bitfld.quad 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documenusction for signals in each group" newline hexmask.quad.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.quad 0x10 "CORE_MMRS_RGX_CR_USC_PERF_SELECT1," rbitfld.quad 0x10 62.--63. "RESERVED_62," "0,1,2,3" newline hexmask.quad.word 0x10 48.--61. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline rbitfld.quad 0x10 46.--47. "RESERVED_46," "0,1,2,3" newline hexmask.quad.word 0x10 32.--45. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" newline hexmask.quad.word 0x10 22.--31. 1. "RESERVED_22," newline bitfld.quad 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documenusction for signals in each group" newline hexmask.quad.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.quad 0x18 "CORE_MMRS_RGX_CR_USC_PERF_SELECT2," rbitfld.quad 0x18 62.--63. "RESERVED_62," "0,1,2,3" newline hexmask.quad.word 0x18 48.--61. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline rbitfld.quad 0x18 46.--47. "RESERVED_46," "0,1,2,3" newline hexmask.quad.word 0x18 32.--45. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" newline hexmask.quad.word 0x18 22.--31. 1. "RESERVED_22," newline bitfld.quad 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documenusction for signals in each group" newline hexmask.quad.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.quad 0x20 "CORE_MMRS_RGX_CR_USC_PERF_SELECT3," rbitfld.quad 0x20 62.--63. "RESERVED_62," "0,1,2,3" newline hexmask.quad.word 0x20 48.--61. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline rbitfld.quad 0x20 46.--47. "RESERVED_46," "0,1,2,3" newline hexmask.quad.word 0x20 32.--45. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" newline hexmask.quad.word 0x20 22.--31. 1. "RESERVED_22," newline bitfld.quad 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documenusction for signals in each group" newline hexmask.quad.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" rgroup.quad 0x8148++0x27 line.quad 0x0 "CORE_MMRS_RGX_CR_USC_PERF_SELECTED_BITS," hexmask.quad.word 0x0 48.--63. 1. "REG3,present bus signals counter 3" newline hexmask.quad.word 0x0 32.--47. 1. "REG2,present bus signals counter 2" newline hexmask.quad.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.quad.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" line.quad 0x8 "CORE_MMRS_RGX_CR_USC_PERF_COUNTER_0," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "REG,counter a0" line.quad 0x10 "CORE_MMRS_RGX_CR_USC_PERF_COUNTER_1," hexmask.quad.long 0x10 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x10 0.--31. 1. "REG,counter a0" line.quad 0x18 "CORE_MMRS_RGX_CR_USC_PERF_COUNTER_2," hexmask.quad.long 0x18 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x18 0.--31. 1. "REG,counter a0" line.quad 0x20 "CORE_MMRS_RGX_CR_USC_PERF_COUNTER_3," hexmask.quad.long 0x20 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x20 0.--31. 1. "REG,counter a0" rgroup.quad 0x8478++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_PBE_PERF," hexmask.quad 0x0 5.--63. 1. "RESERVED_5," newline bitfld.quad 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.quad 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.quad 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.quad 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.quad 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_PBE_PERF_SELECT0," rbitfld.quad 0x8 62.--63. "RESERVED_62," "0,1,2,3" newline hexmask.quad.word 0x8 48.--61. 1. "BATCH_MAX,this is the max batch number which will be counted in this group" newline rbitfld.quad 0x8 46.--47. "RESERVED_46," "0,1,2,3" newline hexmask.quad.word 0x8 32.--45. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" newline hexmask.quad.word 0x8 22.--31. 1. "RESERVED_22," newline bitfld.quad 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.quad.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.quad 0x10 "CORE_MMRS_RGX_CR_PBE_PERF_SELECT1," rbitfld.quad 0x10 62.--63. "RESERVED_62," "0,1,2,3" newline hexmask.quad.word 0x10 48.--61. 1. "BATCH_MAX,this is the max batch number which will be counted in this group" newline rbitfld.quad 0x10 46.--47. "RESERVED_46," "0,1,2,3" newline hexmask.quad.word 0x10 32.--45. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" newline hexmask.quad.word 0x10 22.--31. 1. "RESERVED_22," newline bitfld.quad 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.quad.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.quad 0x18 "CORE_MMRS_RGX_CR_PBE_PERF_SELECT2," rbitfld.quad 0x18 62.--63. "RESERVED_62," "0,1,2,3" newline hexmask.quad.word 0x18 48.--61. 1. "BATCH_MAX,this is the max batch number which will be counted in this group" newline rbitfld.quad 0x18 46.--47. "RESERVED_46," "0,1,2,3" newline hexmask.quad.word 0x18 32.--45. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" newline hexmask.quad.word 0x18 22.--31. 1. "RESERVED_22," newline bitfld.quad 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.quad.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" rgroup.quad 0x84A0++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_PBE_PERF_SELECT3," rbitfld.quad 0x0 62.--63. "RESERVED_62," "0,1,2,3" newline hexmask.quad.word 0x0 48.--61. 1. "BATCH_MAX,this is the max batch number which will be counted in this group" newline rbitfld.quad 0x0 46.--47. "RESERVED_46," "0,1,2,3" newline hexmask.quad.word 0x0 32.--45. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" newline hexmask.quad.word 0x0 22.--31. 1. "RESERVED_22," newline bitfld.quad 0x0 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "0: bitwise increments,1: unsigned count increment" newline hexmask.quad.byte 0x0 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.quad.word 0x0 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" rgroup.quad 0x84A8++0x27 line.quad 0x0 "CORE_MMRS_RGX_CR_PBE_PERF_SELECTED_BITS," hexmask.quad.word 0x0 48.--63. 1. "REG3,present bus signals counter 3" newline hexmask.quad.word 0x0 32.--47. 1. "REG2,present bus signals counter 2" newline hexmask.quad.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.quad.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" line.quad 0x8 "CORE_MMRS_RGX_CR_PBE_PERF_COUNTER_0," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "REG,counter a0" line.quad 0x10 "CORE_MMRS_RGX_CR_PBE_PERF_COUNTER_1," hexmask.quad.long 0x10 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x10 0.--31. 1. "REG,counter a0" line.quad 0x18 "CORE_MMRS_RGX_CR_PBE_PERF_COUNTER_2," hexmask.quad.long 0x18 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x18 0.--31. 1. "REG,counter a0" line.quad 0x20 "CORE_MMRS_RGX_CR_PBE_PERF_COUNTER_3," hexmask.quad.long 0x20 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x20 0.--31. 1. "REG,counter a0" rgroup.quad 0x9100++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_TRP_CHECKSUM_PBE_3D," hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "VALUE," rgroup.quad 0x9110++0x27 line.quad 0x0 "CORE_MMRS_RGX_CR_TRP_CHECKSUM_ZLS_UNCOMPRESSED," hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "VALUE," line.quad 0x8 "CORE_MMRS_RGX_CR_TRP_CHECKSUM_ZLS_COMPRESSED," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "VALUE," line.quad 0x10 "CORE_MMRS_RGX_CR_TRP_CHECKSUM_TPW," hexmask.quad.long 0x10 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x10 0.--31. 1. "VALUE," line.quad 0x18 "CORE_MMRS_RGX_CR_TRP_CHECKSUM_TE_REGION," hexmask.quad.long 0x18 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x18 0.--31. 1. "VALUE," line.quad 0x20 "CORE_MMRS_RGX_CR_TRP_CHECKSUM_TE_CONTROL," hexmask.quad.long 0x20 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x20 0.--31. 1. "VALUE," rgroup.quad 0x9138++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_TRP_CLEAR,At the end of a processing phase where TRP is enabled. after having read the relevant status registers." hexmask.quad 0x0 2.--63. 1. "RESERVED_2," newline bitfld.quad 0x0 1. "FRAG_3D," "0,1" newline bitfld.quad 0x0 0. "GEOM," "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_TRP_FILTER,This register designates which TRP Filters shall discard the protected 'safety' transactions for the respective processing phase" hexmask.quad 0x8 2.--63. 1. "RESERVED_2," newline bitfld.quad 0x8 1. "FRAG_3D," "0,1" newline bitfld.quad 0x8 0. "GEOM," "0,1" rgroup.quad 0x9148++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_USC_DMA_CHECKSUM_DATA_COMP,Checksum of protected compute workloads on USC to TPU_MCU data path" hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "VALUE," rgroup.quad 0x9150++0x27 line.quad 0x0 "CORE_MMRS_RGX_CR_USC_DMA_CHECKSUM_OP_COMP,Writes to this register will clear compute checksums generated for USC to TPU_MCU datapath" hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "CLEAR," "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_USC_DMA_HEAP_COMP,Defines the address stride of the duplicate buffer for safe compute operations" hexmask.quad.tbyte 0x8 40.--63. 1. "RESERVED_40," newline hexmask.quad.long 0x8 12.--39. 1. "STRIDE," newline hexmask.quad.word 0x8 0.--11. 1. "RESERVED_0," line.quad 0x10 "CORE_MMRS_RGX_CR_TRP_DUMMY_PM,A write of '1' to this register resets the Dummy PM allocation counters to zero." hexmask.quad 0x10 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x10 0. "CLEAR,Clear Dummy PM allocations a write to this register results in a one cycle pulse" "0,1" line.quad 0x18 "CORE_MMRS_RGX_CR_TRP_DUMMY_PM_TE_PAGE,The reset value of the TE vpage for dummy PM. in 8KB granularity." hexmask.quad.long 0x18 34.--63. 1. "RESERVED_34," newline hexmask.quad.tbyte 0x18 13.--33. 1. "ADDR," newline hexmask.quad.word 0x18 0.--12. 1. "RESERVED_0," line.quad 0x20 "CORE_MMRS_RGX_CR_TRP_DUMMY_PM_TPW_PAGE,The reset value of the TPW vpage for dummy PM. in 8KB granularity." hexmask.quad.long 0x20 34.--63. 1. "RESERVED_34," newline hexmask.quad.tbyte 0x20 13.--33. 1. "ADDR," newline hexmask.quad.word 0x20 0.--12. 1. "RESERVED_0," rgroup.quad 0xA000++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_BIF_TRUST,Define Requestors/Data Masters which are Trusted/Untrusted and enable/disable the Memory Bus Security feature within the Core" hexmask.quad 0x0 17.--63. 1. "RESERVED_17," newline bitfld.quad 0x0 16. "ENABLE,Enable Security feature: 0x1 = Enabled 0x0 = Disabled" "0: Disabled,1: Enabled" newline hexmask.quad.byte 0x0 9.--15. 1. "DM_TRUSTED,Mask of bits which defines which of the remaining Data Masters are trusted: 0x1 = Trusted 0x0 = Untrusted" newline bitfld.quad 0x0 8. "OTHER_COMPUTE_DM_TRUSTED,Defines whether other accesses with the Compute DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "0: Untrusted,1: Trusted" newline bitfld.quad 0x0 7. "MCU_COMPUTE_DM_TRUSTED,Defines whether MCU accesses with the Compute DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "0: Untrusted,1: Trusted" newline bitfld.quad 0x0 6. "PBE_COMPUTE_DM_TRUSTED,Defines whether PBE accesses with the Compute DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "0: Untrusted,1: Trusted" newline bitfld.quad 0x0 5. "OTHER_PIXEL_DM_TRUSTED,Defines whether other accesses with the Pixel DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "0: Untrusted,1: Trusted" newline bitfld.quad 0x0 4. "MCU_PIXEL_DM_TRUSTED,Defines whether MCU accesses with the Pixel DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "0: Untrusted,1: Trusted" newline bitfld.quad 0x0 3. "PBE_PIXEL_DM_TRUSTED,Defines whether PBE accesses with the Pixel DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "0: Untrusted,1: Trusted" newline bitfld.quad 0x0 2. "OTHER_VERTEX_DM_TRUSTED,Defines whether other accesses with the Vertex DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "0: Untrusted,1: Trusted" newline bitfld.quad 0x0 1. "MCU_VERTEX_DM_TRUSTED,Defines whether MCU accesses with the Vertex DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "0: Untrusted,1: Trusted" newline bitfld.quad 0x0 0. "PBE_VERTEX_DM_TRUSTED,Defines whether PBE accesses with the Vertex DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "0: Untrusted,1: Trusted" rgroup.quad 0xA100++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_SYS_BUS_SECURE,Setting this register secures the IMG Configuration Registers from the System Bus." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "ENABLE,

0 = No System Bus Security

1 = System Bus Restricted

" "0: No System Bus Security

1 = System Bus..,?" rgroup.quad 0xB000++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_PIPELINE_STATS_ENABLE,This register globally enables per DM pipeline statistics counters." hexmask.quad 0x0 17.--63. 1. "RESERVED_17," newline bitfld.quad 0x0 16. "COMPUTE," "0,1" newline hexmask.quad.byte 0x0 9.--15. 1. "RESERVED_9," newline bitfld.quad 0x0 8. "_3D," "0,1" newline hexmask.quad.byte 0x0 1.--7. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "TA," "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_PIPELINE_STATS_CLEAR,Writing '1' to fields of this register resets the pipeline statistics counters per DM" hexmask.quad 0x8 17.--63. 1. "RESERVED_17," newline bitfld.quad 0x8 16. "COMPUTE," "0,1" newline hexmask.quad.byte 0x8 9.--15. 1. "RESERVED_9," newline bitfld.quad 0x8 8. "_3D," "0,1" newline hexmask.quad.byte 0x8 1.--7. 1. "RESERVED_1," newline bitfld.quad 0x8 0. "TA," "0,1" rgroup.quad 0xB010++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_PIPELINE_STATS_IA_VERTICES,Number of vertices the Input Assembly stage generated (not subtracting any caching)" hexmask.quad 0x0 0.--63. 1. "COUNT," line.quad 0x8 "CORE_MMRS_RGX_CR_PIPELINE_STATS_IA_PRIMITIVES,Number of primitives the Input Assembly stage generated" hexmask.quad 0x8 0.--63. 1. "COUNT," line.quad 0x10 "CORE_MMRS_RGX_CR_PIPELINE_STATS_VS_INVOCATIONS,Number of times the Vertex Shader is executed" hexmask.quad 0x10 0.--63. 1. "COUNT," rgroup.quad 0xB038++0x2F line.quad 0x0 "CORE_MMRS_RGX_CR_PIPELINE_STATS_GS_INVOCATIONS,Number of times the Geometry Shader is executed" hexmask.quad 0x0 0.--63. 1. "COUNT," line.quad 0x8 "CORE_MMRS_RGX_CR_PIPELINE_STATS_GS_PRIMITIVES,Number of primitives the Geometry Shader generated" hexmask.quad 0x8 0.--63. 1. "COUNT," line.quad 0x10 "CORE_MMRS_RGX_CR_PIPELINE_STATS_C_INVOCATIONS,Number of times the Clipper is executed" hexmask.quad 0x10 0.--63. 1. "COUNT," line.quad 0x18 "CORE_MMRS_RGX_CR_PIPELINE_STATS_C_PRIMITIVES,Number of primitives the Clipper generated" hexmask.quad 0x18 0.--63. 1. "COUNT," line.quad 0x20 "CORE_MMRS_RGX_CR_PIPELINE_STATS_PS_INVOCATIONS,Number of times the Pixel Shader is executed" hexmask.quad 0x20 0.--63. 1. "COUNT," line.quad 0x28 "CORE_MMRS_RGX_CR_PIPELINE_STATS_CS_INVOCATIONS,Number of times the Compute Shader is executed" hexmask.quad 0x28 0.--63. 1. "COUNT," rgroup.quad 0xE000++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_CACHE_CFI_EVENT,Global Flush and Invalidation Pending bits for all Texture and Data Caches in the design." hexmask.quad.tbyte 0x0 41.--63. 1. "RESERVED_41," newline bitfld.quad 0x0 40. "SLC_PENDING,1 Indicates there is a pending global CFI operation on the SLC cache" "0,1" newline hexmask.quad.byte 0x0 32.--39. 1. "MCU_L1_PENDING,1 Indicates there is a pending global CFI operation on the specified MCU L1 cache [there can be up to 8 MCU L1 caches depending on the number of clusters]" newline hexmask.quad.word 0x0 16.--31. 1. "MCU_L0_PENDING,1 Indicates there is a pending global CFI operation on the specified MCU L0 cache [there can be up to 16 MCU L0 caches depending on the number of clusters]" newline hexmask.quad.word 0x0 0.--15. 1. "MADD_PENDING,1 Indicates there is a pending global CFI operation on the specified MADD Texture cache [there can be up to 16 MADD caches depending on the number of clusters]" rgroup.quad 0xE138++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_MMU_CTRL_INVAL,MMU invalidation control registers" hexmask.quad 0x0 12.--63. 1. "RESERVED_12," newline bitfld.quad 0x0 11. "ALL_CONTEXTS,When ALL_CONTEXTS is set all context ids get invalidated [global invalidation]" "0,1" newline hexmask.quad.byte 0x0 3.--10. 1. "CONTEXT,When ALL_CONTEXTS is not set this field specifies the context id to be invalidated [per-context invalidation]" newline bitfld.quad 0x0 2. "PC,Invalidates PC PD & PT" "0,1" newline bitfld.quad 0x0 1. "PD,Invalidates PD & PT" "0,1" newline bitfld.quad 0x0 0. "PT,Invalidates PT" "0,1" rgroup.quad 0xF220++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_BIF_BLACKPEARL_RTN_FIFO_WORD_COUNT,Blackpearl BIF return FIFO word count" hexmask.quad 0x0 9.--63. 1. "RESERVED_9," newline hexmask.quad.word 0x0 0.--8. 1. "COUNTER," line.quad 0x8 "CORE_MMRS_RGX_CR_BIF_JONES_RTN_FIFO_WORD_COUNT,Jones BIF return FIFO word count" hexmask.quad 0x8 9.--63. 1. "RESERVED_9," newline hexmask.quad.word 0x8 0.--8. 1. "COUNTER," rgroup.quad 0xF300++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_MULTICORE_GPU," hexmask.quad 0x0 7.--63. 1. "RESERVED_7," newline bitfld.quad 0x0 6. "CAPABILITY_FRAGMENT,Whether or not this core has fragment capability. A value of 1 means it has the capability." "0,1" newline bitfld.quad 0x0 5. "CAPABILITY_GEOMETRY,Whether or not this core has geometry capability. A value of 1 means it has the capability." "0,1" newline bitfld.quad 0x0 4. "CAPABILITY_COMPUTE,Whether or not this core has compute capability. A value of 1 means it has the capability." "0,1" newline bitfld.quad 0x0 3. "CAPABILITY_PRIMARY,If this field is set to one then this core has job synchronisation capabilities [i. e. via its firmware scheduler] and can be used as a Primary core." "0,1" newline bitfld.quad 0x0 0.--2. "ID,The ID number of the GPU within the multicore system" "0,1,2,3,4,5,6,7" line.quad 0x8 "CORE_MMRS_RGX_CR_MULTICORE_SYSTEM,Multicore read-only count register." hexmask.quad 0x8 4.--63. 1. "RESERVED_4," newline hexmask.quad.byte 0x8 0.--3. 1. "GPU_COUNT,The number of physical cores in this Primary-Secondary group of a multicore system. A value of zero is meaningless. This register is set via a top level pin." rgroup.quad 0xF310++0xF line.quad 0x0 "CORE_MMRS_RGX_CR_MULTICORE_FRAGMENT_CTRL_COMMON,Multicore common fragment phase control register. This register must be the same across all instances in this Primary-Secondary group." hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline bitfld.quad 0x0 30.--31. "WORKLOAD_TYPE,Sets the type of workload to be executed. 0 = Execute count is per tile-group [2x2 group of 16x16 tiles] for standard 3D renders and per two-tiles for Fast/Scale renders. 1 = Execute count is per row. Where a.." "0: Execute count is per tile-group [2x2 group of..,1: Execute count is per row,2: Reserved,3: Reserved" newline hexmask.quad.tbyte 0x0 8.--29. 1. "WORKLOAD_EXECUTE_COUNT,The number of workloads to process in a run where a workload is as identified by the RGX_CR_MULTICORE_FRAGMENT_CTRL_COMMON_WORKLOAD_TYPE register. This register must be the same across all instances in.." newline hexmask.quad.byte 0x0 0.--7. 1. "GPU_ENABLE,An active high signal one bit per GPU indicating if the fragment phase is active. Each GPU uses its RGX_CR_MULTICORE_FRAGMENT_CTRL_GPU_OFFSET register value to index into this register." line.quad 0x8 "CORE_MMRS_RGX_CR_MULTICORE_FRAGMENT_CTRL,Multicore non-common fragment phase control register. This register can be different per Primary/Secondary instance within a group." hexmask.quad 0x8 3.--63. 1. "RESERVED_3," newline bitfld.quad 0x8 0.--2. "GPU_OFFSET,The index of the GPU used in the calculation of the fragment Workload Distribution. This register shall be different per Primary/Secondary instance within a group. See the Workload.." "0,1,2,3,4,5,6,7" rgroup.quad 0xF330++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_MULTICORE_COMPUTE_CTRL_COMMON,Multicore common compute phase control register. Should be same across all instances in this Primary-Secondary group." hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline bitfld.quad 0x0 30.--31. "WORKLOAD_TYPE,The type of workload per WORKLOAD_EXECUTE_COUNT. 0 = workgroup. 1 2 3 = reserved." "0: workgroup,?,?,3: reserved" newline hexmask.quad.tbyte 0x0 8.--29. 1. "WORKLOAD_EXECUTE_COUNT,The number of compute workloads to process in a run. This register must be the same across all instances in this Primary-Secondary group. Setting this register to zero means.." newline hexmask.quad.byte 0x0 0.--7. 1. "GPU_ENABLE,An active high signal one bit per GPU indicating if the compute phase is active. Each GPU uses its RGX_CR_MULTICORE_COMPUTE_CTRL_GPU_OFFSET register value to index into this register." line.quad 0x8 "CORE_MMRS_RGX_CR_MULTICORE_COMPUTE_CTRL,Multicore non-common compute phase control register. Can be different per Primary/Secondary instance within a group." hexmask.quad 0x8 3.--63. 1. "RESERVED_3," newline bitfld.quad 0x8 0.--2. "GPU_OFFSET,The index of the GPU used in the calculation of the compute Workload Distribution. This register shall be different per Primary/Secondary instance within a group. The offset must be.." "0,1,2,3,4,5,6,7" line.quad 0x10 "CORE_MMRS_RGX_CR_ECC_RAM_ERR_INJ,Core ECC RAM error injection control register." hexmask.quad 0x10 5.--63. 1. "RESERVED_5," newline bitfld.quad 0x10 4. "SLC_SIDEKICK,ECC_RAM error injection for ALL blocks within SLC_SIDEKICK" "0,1" newline bitfld.quad 0x10 3. "USC,ECC_RAM error injection for ALL blocks within USC" "0,1" newline bitfld.quad 0x10 2. "TPU_MCU_L0,ECC_RAM error injection for ALL blocks within TPU_MCU_L0" "0,1" newline bitfld.quad 0x10 1. "RASCAL,ECC_RAM error injection for ALL blocks within RASCAL" "0,1" newline rbitfld.quad 0x10 0. "RESERVED_0," "0,1" line.quad 0x18 "CORE_MMRS_RGX_CR_ECC_RAM_INIT_KICK,Core ECC RAM Initialisation control register." hexmask.quad 0x18 5.--63. 1. "RESERVED_5," newline bitfld.quad 0x18 4. "SLC_SIDEKICK,ECC_RAM Init kick for ALL blocks within SLC_SIDEKICK" "0,1" newline bitfld.quad 0x18 3. "USC,ECC_RAM Init kick for ALL blocks within USC" "0,1" newline bitfld.quad 0x18 2. "TPU_MCU_L0,ECC_RAM Init kick for ALL blocks within TPU_MCU_L0" "0,1" newline bitfld.quad 0x18 1. "RASCAL,ECC_RAM Init kick for ALL blocks within RASCAL" "0,1" newline rbitfld.quad 0x18 0. "RESERVED_0," "0,1" rgroup.quad 0xF350++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_ECC_RAM_INIT_DONE,Core ECC RAM initialisation status register." hexmask.quad 0x0 5.--63. 1. "RESERVED_5," newline bitfld.quad 0x0 4. "SLC_SIDEKICK,ECC_RAM Init kick for ALL blocks within SLC_SIDEKICK" "0,1" newline bitfld.quad 0x0 3. "USC,ECC_RAM Init kick for ALL blocks within USC" "0,1" newline bitfld.quad 0x0 2. "TPU_MCU_L0,ECC_RAM Init kick for ALL blocks within TPU_MCU_L0" "0,1" newline bitfld.quad 0x0 1. "RASCAL,ECC_RAM Init kick for ALL blocks within RASCAL" "0,1" newline bitfld.quad 0x0 0. "RESERVED_0," "0,1" rgroup.quad 0xF390++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_SAFETY_EVENT_ENABLE,This register is used to enable Safety mechanism interrupts directly to the host" hexmask.quad 0x0 8.--63. 1. "RESERVED_8," newline bitfld.quad 0x0 7. "GPU_LOCKUP,Set if GPU has locked up" "0,1" newline bitfld.quad 0x0 6. "CPU_PAGE_FAULT,Set if a CPU page fault has been detected." "0,1" newline bitfld.quad 0x0 5. "SAFE_COMPUTE_FAIL,Set if workgroup protection checksum comparison has failed" "0,1" newline bitfld.quad 0x0 4. "WATCHDOG_TIMEOUT,Set if HW watchdog timer has timed out" "0,1" newline bitfld.quad 0x0 3. "TRP_FAIL,Set if TRP checksum check has failed" "0,1" newline bitfld.quad 0x0 2. "FAULT_FW,Set if a parity failure has been detected in FW processor" "0,1" newline bitfld.quad 0x0 1. "FAULT_GPU,Set if a parity failure has been detected in GPU" "0,1" newline bitfld.quad 0x0 0. "GPU_PAGE_FAULT,Set if a GPU page fault has been detected." "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_SAFETY_EVENT_STATUS,The event status register indicate the source of an interrupt generated by the current active safety mechanisms" hexmask.quad 0x8 8.--63. 1. "RESERVED_8," newline bitfld.quad 0x8 7. "GPU_LOCKUP,Set if GPU has locked up" "0,1" newline bitfld.quad 0x8 6. "CPU_PAGE_FAULT,Set if a CPU page fault has been detected." "0,1" newline bitfld.quad 0x8 5. "SAFE_COMPUTE_FAIL,Set if workgroup protection checksum comparison has failed" "0,1" newline bitfld.quad 0x8 4. "WATCHDOG_TIMEOUT,Set if HW watchdog timer has timed out" "0,1" newline bitfld.quad 0x8 3. "TRP_FAIL,Set if TRP checksum check has failed" "0,1" newline bitfld.quad 0x8 2. "FAULT_FW,Set if a parity failure has been detected in FW processor" "0,1" newline bitfld.quad 0x8 1. "FAULT_GPU,Set if a parity failure has been detected in GPU" "0,1" newline bitfld.quad 0x8 0. "GPU_PAGE_FAULT,Set if a GPU page fault has been detected." "0,1" line.quad 0x10 "CORE_MMRS_RGX_CR_SAFETY_EVENT_CLEAR,This register is used to clear safety event interrupts." hexmask.quad 0x10 8.--63. 1. "RESERVED_8," newline bitfld.quad 0x10 7. "GPU_LOCKUP,Set if GPU has locked up" "0,1" newline bitfld.quad 0x10 6. "CPU_PAGE_FAULT,Set if a CPU page fault has been detected." "0,1" newline bitfld.quad 0x10 5. "SAFE_COMPUTE_FAIL,Set if workgroup protection checksum comparison has failed" "0,1" newline bitfld.quad 0x10 4. "WATCHDOG_TIMEOUT,Set if HW watchdog timer has timed out" "0,1" newline bitfld.quad 0x10 3. "TRP_FAIL,Set if TRP checksum check has failed" "0,1" newline bitfld.quad 0x10 2. "FAULT_FW,Set if a parity failure has been detected in FW processor" "0,1" newline bitfld.quad 0x10 1. "FAULT_GPU,Set if a parity failure has been detected in GPU" "0,1" newline bitfld.quad 0x10 0. "GPU_PAGE_FAULT,Set if a GPU page fault has been detected." "0,1" line.quad 0x18 "CORE_MMRS_RGX_CR_TRP_FAIL,Writing '1' to this register indicates a failure in TRP checksum comparison" hexmask.quad 0x18 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x18 0. "PULSE," "0,1" rgroup.quad 0xF3B0++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_FAULT_FW_STATUS,Status register to indicate memory fault that has been detected in the FW processor" hexmask.quad 0x0 17.--63. 1. "RESERVED_17," newline bitfld.quad 0x0 16. "CPU_CORRECT,Set if a fault affecting the FW processor has been corrected" "0,1" newline hexmask.quad.word 0x0 1.--15. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "CPU_DETECT,Set if a fault affecting the FW processor has been detected" "0,1" rgroup.quad 0xF3B8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_FAULT_FW_CLEAR,Individually clear FAULT_FW_STATUS fields" hexmask.quad 0x0 17.--63. 1. "RESERVED_17," newline bitfld.quad 0x0 16. "CPU_CORRECT,Set if a fault affecting the FW processor has been corrected" "0,1" newline hexmask.quad.word 0x0 1.--15. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "CPU_DETECT,Set if a fault affecting the FW processor has been detected" "0,1" rgroup.quad 0xF3C0++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_FAULT_GPU_STATUS,Status register to indicate the granularity of a memory fault that has been detected in the GPU" hexmask.quad 0x0 20.--63. 1. "RESERVED_20," newline bitfld.quad 0x0 19. "SLC_SIDEKICK_CORRECT,Set if a fault affecting any RAM in SLC_SIDEKICK layout block has been corrected." "0,1" newline bitfld.quad 0x0 18. "USC_CORRECT,Set if a fault affecting any RAM in USC layout block has been corrected." "0,1" newline bitfld.quad 0x0 17. "TPU_MCU_L0_CORRECT,Set if a fault affecting any RAM in TPU_MCU_L0 layout block has been corrected." "0,1" newline bitfld.quad 0x0 16. "RASCAL_CORRECT,Set if a fault affecting any RAM in RASCAL layout block has been corrected." "0,1" newline hexmask.quad.word 0x0 4.--15. 1. "RESERVED_4," newline bitfld.quad 0x0 3. "SLC_SIDEKICK_DETECT,Set if a fault affecting any RAM in SLC_SIDEKICK layout block has been detected." "0,1" newline bitfld.quad 0x0 2. "USC_DETECT,Set if a fault affecting any RAM in USC layout block has been detected." "0,1" newline bitfld.quad 0x0 1. "TPU_MCU_L0_DETECT,Set if a fault affecting any RAM in TPU_MCU_L0 layout block has been detected." "0,1" newline bitfld.quad 0x0 0. "RASCAL_DETECT,Set if a fault affecting any RAM in RASCAL layout block has been detected." "0,1" rgroup.quad 0xF3C8++0x27 line.quad 0x0 "CORE_MMRS_RGX_CR_FAULT_GPU_CLEAR,Individually clear RAM_FAULT_GPU_STATUS fields" hexmask.quad 0x0 20.--63. 1. "RESERVED_20," newline bitfld.quad 0x0 19. "SLC_SIDEKICK_CORRECT,Set if a fault affecting any RAM in SLC_SIDEKICK layout block has been corrected." "0,1" newline bitfld.quad 0x0 18. "USC_CORRECT,Set if a fault affecting any RAM in USC layout block has been corrected." "0,1" newline bitfld.quad 0x0 17. "TPU_MCU_L0_CORRECT,Set if a fault affecting any RAM in TPU_MCU_L0 layout block has been corrected." "0,1" newline bitfld.quad 0x0 16. "RASCAL_CORRECT,Set if a fault affecting any RAM in RASCAL layout block has been corrected." "0,1" newline hexmask.quad.word 0x0 4.--15. 1. "RESERVED_4," newline bitfld.quad 0x0 3. "SLC_SIDEKICK_DETECT,Set if a fault affecting any RAM in SLC_SIDEKICK layout block has been detected." "0,1" newline bitfld.quad 0x0 2. "USC_DETECT,Set if a fault affecting any RAM in USC layout block has been detected." "0,1" newline bitfld.quad 0x0 1. "TPU_MCU_L0_DETECT,Set if a fault affecting any RAM in TPU_MCU_L0 layout block has been detected." "0,1" newline bitfld.quad 0x0 0. "RASCAL_DETECT,Set if a fault affecting any RAM in RASCAL layout block has been detected." "0,1" line.quad 0x8 "CORE_MMRS_RGX_CR_FILTER_FAULT_CORRECTION,This register affects the category of faults that are signaled on the FAULT_GPU and FAULT_FW fields of the SAFETY_EVENT_STATUS register." hexmask.quad 0x8 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x8 0. "ENABLE,0 - Only faults that were detected but not corrected are signaled . 1 - Faults that are detected or corrected are signaled." "0: Only faults that were detected but not corrected..,1: Faults that are detected or corrected are signaled" line.quad 0x10 "CORE_MMRS_RGX_CR_MTS_SAFETY_EVENT_ENABLE,This register is used to enable safety mechanism interrupts directly to the MTS" hexmask.quad 0x10 8.--63. 1. "RESERVED_8," newline bitfld.quad 0x10 7. "GPU_LOCKUP,Set if GPU has locked up" "0,1" newline bitfld.quad 0x10 6. "CPU_PAGE_FAULT,Set if a CPU page fault has been detected." "0,1" newline bitfld.quad 0x10 5. "SAFE_COMPUTE_FAIL,Set if workgroup protection checksum comparison has failed" "0,1" newline bitfld.quad 0x10 4. "WATCHDOG_TIMEOUT,Set if HW watchdog timer has timed out" "0,1" newline bitfld.quad 0x10 3. "TRP_FAIL,Set if TRP checksum check has failed" "0,1" newline bitfld.quad 0x10 2. "FAULT_FW,Set if a parity failure has been detected in FW processor" "0,1" newline bitfld.quad 0x10 1. "FAULT_GPU,Set if a parity failure has been detected in GPU" "0,1" newline bitfld.quad 0x10 0. "GPU_PAGE_FAULT,Set if a GPU page fault has been detected." "0,1" line.quad 0x18 "CORE_MMRS_RGX_CR_SAFE_COMPUTE_FAIL,Writing '1' to this register indicates a failure in workgroup protection checksum comparison" hexmask.quad 0x18 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x18 0. "PULSE," "0,1" line.quad 0x20 "CORE_MMRS_RGX_CR_GPU_LOCKUP,Writing '1' to this register indicates failure of GPU to complete processing a workload" hexmask.quad 0x20 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x20 0. "PULSE," "0,1" rgroup.quad 0x10020++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_CORE_ID1,Reports the product ID" hexmask.quad.word 0x0 48.--63. 1. "BRANCH_ID,B - Branch ID" newline hexmask.quad.word 0x0 32.--47. 1. "VERSION_ID,V - Version ID" newline hexmask.quad.word 0x0 16.--31. 1. "NUMBER_OF_SCALABLE_UNITS,N - Number of scalable Units" newline hexmask.quad.word 0x0 0.--15. 1. "CONFIG_ID,C - Config ID" rgroup.quad 0x10B00++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_MTS_SCHEDULE1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.quad 0x0 9.--63. 1. "RESERVED_9," newline bitfld.quad 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.quad 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.quad 0x0 5. "CONTEXT," "0,1" newline bitfld.quad 0x0 4. "TASK," "0,1" newline hexmask.quad.byte 0x0 0.--3. 1. "DM,DataMaster Type" rgroup.quad 0x10B98++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_MTS_INTCTX1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.quad 0x0 30.--63. 1. "RESERVED_30," newline hexmask.quad.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.quad.byte 0x0 16.--21. 1. "RESERVED_16," newline hexmask.quad.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.quad.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.quad 0x8 "CORE_MMRS_RGX_CR_MTS_BGCTX1,This register contains the sideband data for the MTS internal background context registers" hexmask.quad 0x8 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.quad 0x10 "CORE_MMRS_RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.quad.word 0x10 48.--63. 1. "RESERVED_48," newline hexmask.quad.byte 0x10 40.--47. 1. "DM5,A 8 bit counter for DM5" newline hexmask.quad.byte 0x10 32.--39. 1. "DM4,A 8 bit counter for DM4" newline hexmask.quad.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.quad.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.quad.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.quad.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" rgroup.quad 0x10BD8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_IRQ_OS1_EVENT_STATUS,This register indicates the source of a per-OS host interrupt." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "SOURCE," "0,1" rgroup.quad 0x10BE8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_IRQ_OS1_EVENT_CLEAR,This register clears a per-OS host interrupt." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "SOURCE," "0,1" rgroup.quad 0x11A80++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_OS1_SCRATCH0," hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "DATA," line.quad 0x8 "CORE_MMRS_RGX_CR_OS1_SCRATCH1," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "DATA," line.quad 0x10 "CORE_MMRS_RGX_CR_OS1_SCRATCH2," hexmask.quad 0x10 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x10 0.--7. 1. "DATA," line.quad 0x18 "CORE_MMRS_RGX_CR_OS1_SCRATCH3," hexmask.quad 0x18 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x18 0.--7. 1. "DATA," rgroup.quad 0x20020++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_CORE_ID2,Reports the product ID" hexmask.quad.word 0x0 48.--63. 1. "BRANCH_ID,B - Branch ID" newline hexmask.quad.word 0x0 32.--47. 1. "VERSION_ID,V - Version ID" newline hexmask.quad.word 0x0 16.--31. 1. "NUMBER_OF_SCALABLE_UNITS,N - Number of scalable Units" newline hexmask.quad.word 0x0 0.--15. 1. "CONFIG_ID,C - Config ID" rgroup.quad 0x20B00++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_MTS_SCHEDULE2,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.quad 0x0 9.--63. 1. "RESERVED_9," newline bitfld.quad 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.quad 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.quad 0x0 5. "CONTEXT," "0,1" newline bitfld.quad 0x0 4. "TASK," "0,1" newline hexmask.quad.byte 0x0 0.--3. 1. "DM,DataMaster Type" rgroup.quad 0x20B98++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_MTS_INTCTX2,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.quad 0x0 30.--63. 1. "RESERVED_30," newline hexmask.quad.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.quad.byte 0x0 16.--21. 1. "RESERVED_16," newline hexmask.quad.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.quad.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.quad 0x8 "CORE_MMRS_RGX_CR_MTS_BGCTX2,This register contains the sideband data for the MTS internal background context registers" hexmask.quad 0x8 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.quad 0x10 "CORE_MMRS_RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE2,This register contains the sideband data for the MTS internal counted background context counters" hexmask.quad.word 0x10 48.--63. 1. "RESERVED_48," newline hexmask.quad.byte 0x10 40.--47. 1. "DM5,A 8 bit counter for DM5" newline hexmask.quad.byte 0x10 32.--39. 1. "DM4,A 8 bit counter for DM4" newline hexmask.quad.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.quad.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.quad.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.quad.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" rgroup.quad 0x20BD8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_IRQ_OS2_EVENT_STATUS,This register indicates the source of a per-OS host interrupt." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "SOURCE," "0,1" rgroup.quad 0x20BE8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_IRQ_OS2_EVENT_CLEAR,This register clears a per-OS host interrupt." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "SOURCE," "0,1" rgroup.quad 0x21A80++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_OS2_SCRATCH0," hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "DATA," line.quad 0x8 "CORE_MMRS_RGX_CR_OS2_SCRATCH1," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "DATA," line.quad 0x10 "CORE_MMRS_RGX_CR_OS2_SCRATCH2," hexmask.quad 0x10 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x10 0.--7. 1. "DATA," line.quad 0x18 "CORE_MMRS_RGX_CR_OS2_SCRATCH3," hexmask.quad 0x18 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x18 0.--7. 1. "DATA," rgroup.quad 0x30020++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_CORE_ID3,Reports the product ID" hexmask.quad.word 0x0 48.--63. 1. "BRANCH_ID,B - Branch ID" newline hexmask.quad.word 0x0 32.--47. 1. "VERSION_ID,V - Version ID" newline hexmask.quad.word 0x0 16.--31. 1. "NUMBER_OF_SCALABLE_UNITS,N - Number of scalable Units" newline hexmask.quad.word 0x0 0.--15. 1. "CONFIG_ID,C - Config ID" rgroup.quad 0x30B00++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_MTS_SCHEDULE3,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.quad 0x0 9.--63. 1. "RESERVED_9," newline bitfld.quad 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.quad 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.quad 0x0 5. "CONTEXT," "0,1" newline bitfld.quad 0x0 4. "TASK," "0,1" newline hexmask.quad.byte 0x0 0.--3. 1. "DM,DataMaster Type" rgroup.quad 0x30B98++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_MTS_INTCTX3,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.quad 0x0 30.--63. 1. "RESERVED_30," newline hexmask.quad.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.quad.byte 0x0 16.--21. 1. "RESERVED_16," newline hexmask.quad.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.quad.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.quad 0x8 "CORE_MMRS_RGX_CR_MTS_BGCTX3,This register contains the sideband data for the MTS internal background context registers" hexmask.quad 0x8 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.quad 0x10 "CORE_MMRS_RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE3,This register contains the sideband data for the MTS internal counted background context counters" hexmask.quad.word 0x10 48.--63. 1. "RESERVED_48," newline hexmask.quad.byte 0x10 40.--47. 1. "DM5,A 8 bit counter for DM5" newline hexmask.quad.byte 0x10 32.--39. 1. "DM4,A 8 bit counter for DM4" newline hexmask.quad.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.quad.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.quad.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.quad.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" rgroup.quad 0x30BD8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_IRQ_OS3_EVENT_STATUS,This register indicates the source of a per-OS host interrupt." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "SOURCE," "0,1" rgroup.quad 0x30BE8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_IRQ_OS3_EVENT_CLEAR,This register clears a per-OS host interrupt." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "SOURCE," "0,1" rgroup.quad 0x31A80++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_OS3_SCRATCH0," hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "DATA," line.quad 0x8 "CORE_MMRS_RGX_CR_OS3_SCRATCH1," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "DATA," line.quad 0x10 "CORE_MMRS_RGX_CR_OS3_SCRATCH2," hexmask.quad 0x10 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x10 0.--7. 1. "DATA," line.quad 0x18 "CORE_MMRS_RGX_CR_OS3_SCRATCH3," hexmask.quad 0x18 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x18 0.--7. 1. "DATA," rgroup.quad 0x40020++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_CORE_ID4,Reports the product ID" hexmask.quad.word 0x0 48.--63. 1. "BRANCH_ID,B - Branch ID" newline hexmask.quad.word 0x0 32.--47. 1. "VERSION_ID,V - Version ID" newline hexmask.quad.word 0x0 16.--31. 1. "NUMBER_OF_SCALABLE_UNITS,N - Number of scalable Units" newline hexmask.quad.word 0x0 0.--15. 1. "CONFIG_ID,C - Config ID" rgroup.quad 0x40B00++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_MTS_SCHEDULE4,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.quad 0x0 9.--63. 1. "RESERVED_9," newline bitfld.quad 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.quad 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.quad 0x0 5. "CONTEXT," "0,1" newline bitfld.quad 0x0 4. "TASK," "0,1" newline hexmask.quad.byte 0x0 0.--3. 1. "DM,DataMaster Type" rgroup.quad 0x40B98++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_MTS_INTCTX4,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.quad 0x0 30.--63. 1. "RESERVED_30," newline hexmask.quad.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.quad.byte 0x0 16.--21. 1. "RESERVED_16," newline hexmask.quad.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.quad.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.quad 0x8 "CORE_MMRS_RGX_CR_MTS_BGCTX4,This register contains the sideband data for the MTS internal background context registers" hexmask.quad 0x8 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.quad 0x10 "CORE_MMRS_RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE4,This register contains the sideband data for the MTS internal counted background context counters" hexmask.quad.word 0x10 48.--63. 1. "RESERVED_48," newline hexmask.quad.byte 0x10 40.--47. 1. "DM5,A 8 bit counter for DM5" newline hexmask.quad.byte 0x10 32.--39. 1. "DM4,A 8 bit counter for DM4" newline hexmask.quad.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.quad.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.quad.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.quad.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" rgroup.quad 0x40BD8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_IRQ_OS4_EVENT_STATUS,This register indicates the source of a per-OS host interrupt." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "SOURCE," "0,1" rgroup.quad 0x40BE8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_IRQ_OS4_EVENT_CLEAR,This register clears a per-OS host interrupt." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "SOURCE," "0,1" rgroup.quad 0x41A80++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_OS4_SCRATCH0," hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "DATA," line.quad 0x8 "CORE_MMRS_RGX_CR_OS4_SCRATCH1," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "DATA," line.quad 0x10 "CORE_MMRS_RGX_CR_OS4_SCRATCH2," hexmask.quad 0x10 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x10 0.--7. 1. "DATA," line.quad 0x18 "CORE_MMRS_RGX_CR_OS4_SCRATCH3," hexmask.quad 0x18 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x18 0.--7. 1. "DATA," rgroup.quad 0x50020++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_CORE_ID5,Reports the product ID" hexmask.quad.word 0x0 48.--63. 1. "BRANCH_ID,B - Branch ID" newline hexmask.quad.word 0x0 32.--47. 1. "VERSION_ID,V - Version ID" newline hexmask.quad.word 0x0 16.--31. 1. "NUMBER_OF_SCALABLE_UNITS,N - Number of scalable Units" newline hexmask.quad.word 0x0 0.--15. 1. "CONFIG_ID,C - Config ID" rgroup.quad 0x50B00++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_MTS_SCHEDULE5,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.quad 0x0 9.--63. 1. "RESERVED_9," newline bitfld.quad 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.quad 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.quad 0x0 5. "CONTEXT," "0,1" newline bitfld.quad 0x0 4. "TASK," "0,1" newline hexmask.quad.byte 0x0 0.--3. 1. "DM,DataMaster Type" rgroup.quad 0x50B98++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_MTS_INTCTX5,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.quad 0x0 30.--63. 1. "RESERVED_30," newline hexmask.quad.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.quad.byte 0x0 16.--21. 1. "RESERVED_16," newline hexmask.quad.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.quad.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.quad 0x8 "CORE_MMRS_RGX_CR_MTS_BGCTX5,This register contains the sideband data for the MTS internal background context registers" hexmask.quad 0x8 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.quad 0x10 "CORE_MMRS_RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE5,This register contains the sideband data for the MTS internal counted background context counters" hexmask.quad.word 0x10 48.--63. 1. "RESERVED_48," newline hexmask.quad.byte 0x10 40.--47. 1. "DM5,A 8 bit counter for DM5" newline hexmask.quad.byte 0x10 32.--39. 1. "DM4,A 8 bit counter for DM4" newline hexmask.quad.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.quad.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.quad.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.quad.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" rgroup.quad 0x50BD8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_IRQ_OS5_EVENT_STATUS,This register indicates the source of a per-OS host interrupt." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "SOURCE," "0,1" rgroup.quad 0x50BE8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_IRQ_OS5_EVENT_CLEAR,This register clears a per-OS host interrupt." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "SOURCE," "0,1" rgroup.quad 0x51A80++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_OS5_SCRATCH0," hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "DATA," line.quad 0x8 "CORE_MMRS_RGX_CR_OS5_SCRATCH1," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "DATA," line.quad 0x10 "CORE_MMRS_RGX_CR_OS5_SCRATCH2," hexmask.quad 0x10 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x10 0.--7. 1. "DATA," line.quad 0x18 "CORE_MMRS_RGX_CR_OS5_SCRATCH3," hexmask.quad 0x18 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x18 0.--7. 1. "DATA," rgroup.quad 0x60020++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_CORE_ID6,Reports the product ID" hexmask.quad.word 0x0 48.--63. 1. "BRANCH_ID,B - Branch ID" newline hexmask.quad.word 0x0 32.--47. 1. "VERSION_ID,V - Version ID" newline hexmask.quad.word 0x0 16.--31. 1. "NUMBER_OF_SCALABLE_UNITS,N - Number of scalable Units" newline hexmask.quad.word 0x0 0.--15. 1. "CONFIG_ID,C - Config ID" rgroup.quad 0x60B00++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_MTS_SCHEDULE6,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.quad 0x0 9.--63. 1. "RESERVED_9," newline bitfld.quad 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.quad 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.quad 0x0 5. "CONTEXT," "0,1" newline bitfld.quad 0x0 4. "TASK," "0,1" newline hexmask.quad.byte 0x0 0.--3. 1. "DM,DataMaster Type" rgroup.quad 0x60B98++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_MTS_INTCTX6,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.quad 0x0 30.--63. 1. "RESERVED_30," newline hexmask.quad.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.quad.byte 0x0 16.--21. 1. "RESERVED_16," newline hexmask.quad.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.quad.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.quad 0x8 "CORE_MMRS_RGX_CR_MTS_BGCTX6,This register contains the sideband data for the MTS internal background context registers" hexmask.quad 0x8 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.quad 0x10 "CORE_MMRS_RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE6,This register contains the sideband data for the MTS internal counted background context counters" hexmask.quad.word 0x10 48.--63. 1. "RESERVED_48," newline hexmask.quad.byte 0x10 40.--47. 1. "DM5,A 8 bit counter for DM5" newline hexmask.quad.byte 0x10 32.--39. 1. "DM4,A 8 bit counter for DM4" newline hexmask.quad.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.quad.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.quad.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.quad.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" rgroup.quad 0x60BD8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_IRQ_OS6_EVENT_STATUS,This register indicates the source of a per-OS host interrupt." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "SOURCE," "0,1" rgroup.quad 0x60BE8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_IRQ_OS6_EVENT_CLEAR,This register clears a per-OS host interrupt." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "SOURCE," "0,1" rgroup.quad 0x61A80++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_OS6_SCRATCH0," hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "DATA," line.quad 0x8 "CORE_MMRS_RGX_CR_OS6_SCRATCH1," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "DATA," line.quad 0x10 "CORE_MMRS_RGX_CR_OS6_SCRATCH2," hexmask.quad 0x10 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x10 0.--7. 1. "DATA," line.quad 0x18 "CORE_MMRS_RGX_CR_OS6_SCRATCH3," hexmask.quad 0x18 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x18 0.--7. 1. "DATA," rgroup.quad 0x70020++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_CORE_ID7,Reports the product ID" hexmask.quad.word 0x0 48.--63. 1. "BRANCH_ID,B - Branch ID" newline hexmask.quad.word 0x0 32.--47. 1. "VERSION_ID,V - Version ID" newline hexmask.quad.word 0x0 16.--31. 1. "NUMBER_OF_SCALABLE_UNITS,N - Number of scalable Units" newline hexmask.quad.word 0x0 0.--15. 1. "CONFIG_ID,C - Config ID" rgroup.quad 0x70B00++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_MTS_SCHEDULE7,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.quad 0x0 9.--63. 1. "RESERVED_9," newline bitfld.quad 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.quad 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.quad 0x0 5. "CONTEXT," "0,1" newline bitfld.quad 0x0 4. "TASK," "0,1" newline hexmask.quad.byte 0x0 0.--3. 1. "DM,DataMaster Type" rgroup.quad 0x70B98++0x17 line.quad 0x0 "CORE_MMRS_RGX_CR_MTS_INTCTX7,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.quad 0x0 30.--63. 1. "RESERVED_30," newline hexmask.quad.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.quad.byte 0x0 16.--21. 1. "RESERVED_16," newline hexmask.quad.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.quad.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.quad 0x8 "CORE_MMRS_RGX_CR_MTS_BGCTX7,This register contains the sideband data for the MTS internal background context registers" hexmask.quad 0x8 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.quad 0x10 "CORE_MMRS_RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE7,This register contains the sideband data for the MTS internal counted background context counters" hexmask.quad.word 0x10 48.--63. 1. "RESERVED_48," newline hexmask.quad.byte 0x10 40.--47. 1. "DM5,A 8 bit counter for DM5" newline hexmask.quad.byte 0x10 32.--39. 1. "DM4,A 8 bit counter for DM4" newline hexmask.quad.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.quad.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.quad.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.quad.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" rgroup.quad 0x70BD8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_IRQ_OS7_EVENT_STATUS,This register indicates the source of a per-OS host interrupt." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "SOURCE," "0,1" rgroup.quad 0x70BE8++0x7 line.quad 0x0 "CORE_MMRS_RGX_CR_IRQ_OS7_EVENT_CLEAR,This register clears a per-OS host interrupt." hexmask.quad 0x0 1.--63. 1. "RESERVED_1," newline bitfld.quad 0x0 0. "SOURCE," "0,1" rgroup.quad 0x71A80++0x1F line.quad 0x0 "CORE_MMRS_RGX_CR_OS7_SCRATCH0," hexmask.quad.long 0x0 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x0 0.--31. 1. "DATA," line.quad 0x8 "CORE_MMRS_RGX_CR_OS7_SCRATCH1," hexmask.quad.long 0x8 32.--63. 1. "RESERVED_32," newline hexmask.quad.long 0x8 0.--31. 1. "DATA," line.quad 0x10 "CORE_MMRS_RGX_CR_OS7_SCRATCH2," hexmask.quad 0x10 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x10 0.--7. 1. "DATA," line.quad 0x18 "CORE_MMRS_RGX_CR_OS7_SCRATCH3," hexmask.quad 0x18 8.--63. 1. "RESERVED_8," newline hexmask.quad.byte 0x18 0.--7. 1. "DATA," tree.end tree "j7am" base ad:0x0 tree "j7am_ac" tree "j7am_ac_cfg_to" tree "j7am_ac_cfg_to_ac_cfg_non_safe_stog2_CFG (j7am_ac_cfg_to_ac_cfg_non_safe_stog2_CFG)" base ad:0x2612000 rgroup.long 0x0++0xB line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end tree "j7am_ac_cfg_to_ac_cfg_non_safe_stog9_CFG (j7am_ac_cfg_to_ac_cfg_non_safe_stog9_CFG)" base ad:0x2614000 rgroup.long 0x0++0xB line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end tree.end tree "j7am_ac_merger_cbass0_ERR (j7am_ac_merger_cbass0_ERR)" base ad:0x2A98000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end tree.end tree "j7am_hc2_to_hc_cfg_stog5_CFG (j7am_hc2_to_hc_cfg_stog5_CFG)" base ad:0x2604000 rgroup.long 0x0++0xB line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end tree "j7am_ipphy_to" tree "j7am_ipphy_to_ipphy_stog1_CFG (j7am_ipphy_to_ipphy_stog1_CFG)" base ad:0x260A000 rgroup.long 0x0++0xB line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end tree "j7am_ipphy_to_rti_gpu_stog8_CFG (j7am_ipphy_to_rti_gpu_stog8_CFG)" base ad:0x2616000 rgroup.long 0x0++0xB line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end tree.end tree "j7am_main_infra_to_main_infra_stog0_CFG (j7am_main_infra_to_main_infra_stog0_CFG)" base ad:0x780000 rgroup.long 0x0++0xB line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end tree "j7am_navss_to_ac_non_safe_stog4_CFG (j7am_navss_to_ac_non_safe_stog4_CFG)" base ad:0x2610000 rgroup.long 0x0++0xB line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end tree "j7am_pulsar0" tree "j7am_pulsar0_mem_cbass0" tree "j7am_pulsar0_mem_cbass0_ERR (j7am_pulsar0_mem_cbass0_ERR)" base ad:0x2A90000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end tree "j7am_pulsar0_mem_cbass0_GLB (j7am_pulsar0_mem_cbass0_GLB)" base ad:0x45B23000 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x20++0x3 line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x40++0x7 line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree "j7am_pulsar0_mem_cbass0_ISC (j7am_pulsar0_mem_cbass0_ISC)" base ad:0x458C8000 rgroup.long 0x0++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_cpu0_rmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_0.cpu0_rmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x10++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_cpu0_rmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu0_rmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_cpu0_rmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu0_rmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_cpu0_rmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu0_rmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_cpu0_rmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu0_rmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_cpu0_rmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_0.cpu0_rmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x30++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_cpu0_rmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu0_rmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_cpu0_rmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu0_rmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_cpu0_rmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu0_rmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_cpu0_rmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu0_rmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_cpu0_rmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_0.cpu0_rmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x50++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_cpu0_rmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu0_rmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_cpu0_rmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu0_rmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_cpu0_rmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu0_rmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_cpu0_rmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu0_rmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_cpu0_rmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_0.cpu0_rmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x70++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_cpu0_rmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu0_rmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_cpu0_rmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu0_rmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_cpu0_rmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu0_rmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_cpu0_rmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu0_rmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_cpu0_rmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_0.cpu0_rmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x400++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_cpu0_wmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_0.cpu0_wmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x410++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_cpu0_wmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu0_wmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_cpu0_wmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu0_wmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_cpu0_wmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu0_wmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_cpu0_wmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu0_wmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_cpu0_wmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_0.cpu0_wmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x430++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_cpu0_wmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu0_wmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_cpu0_wmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu0_wmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_cpu0_wmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu0_wmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_cpu0_wmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu0_wmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_cpu0_wmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_0.cpu0_wmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x450++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_cpu0_wmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu0_wmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_cpu0_wmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu0_wmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_cpu0_wmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu0_wmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_cpu0_wmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu0_wmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_cpu0_wmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_0.cpu0_wmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x470++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_cpu0_wmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu0_wmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_cpu0_wmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu0_wmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_cpu0_wmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu0_wmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_cpu0_wmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu0_wmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_cpu0_wmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_0.cpu0_wmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x800++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_cpu1_rmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_0.cpu1_rmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x810++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_cpu1_rmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu1_rmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_cpu1_rmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu1_rmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_cpu1_rmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu1_rmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_cpu1_rmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu1_rmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_cpu1_rmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_0.cpu1_rmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x830++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_cpu1_rmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu1_rmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_cpu1_rmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu1_rmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_cpu1_rmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu1_rmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_cpu1_rmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu1_rmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_cpu1_rmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_0.cpu1_rmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x850++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_cpu1_rmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu1_rmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_cpu1_rmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu1_rmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_cpu1_rmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu1_rmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_cpu1_rmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu1_rmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_cpu1_rmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_0.cpu1_rmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x870++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_cpu1_rmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu1_rmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_cpu1_rmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu1_rmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_cpu1_rmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu1_rmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_cpu1_rmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu1_rmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_cpu1_rmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_0.cpu1_rmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC00++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_cpu1_wmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_0.cpu1_wmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC10++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_cpu1_wmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu1_wmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_cpu1_wmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu1_wmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_cpu1_wmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu1_wmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_cpu1_wmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu1_wmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_cpu1_wmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_0.cpu1_wmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC30++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_cpu1_wmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu1_wmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_cpu1_wmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu1_wmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_cpu1_wmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu1_wmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_cpu1_wmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu1_wmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_cpu1_wmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_0.cpu1_wmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC50++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_cpu1_wmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu1_wmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_cpu1_wmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu1_wmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_cpu1_wmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu1_wmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_cpu1_wmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu1_wmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_cpu1_wmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_0.cpu1_wmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC70++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_0_cpu1_wmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu1_wmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_0_cpu1_wmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu1_wmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_0_cpu1_wmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_0.cpu1_wmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_0_cpu1_wmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_0.cpu1_wmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_0_cpu1_wmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_0.cpu1_wmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." tree.end tree "j7am_pulsar0_mem_cbass0_QOS (j7am_pulsar0_mem_cbass0_QOS)" base ad:0x45DC8000 rgroup.long 0x100++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_0_cpu0_rmst_map0,The Map Register defines the fields for the master Ipulsar_sl_main_0.cpu0_rmst per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x500++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_0_cpu0_wmst_map0,The Map Register defines the fields for the master Ipulsar_sl_main_0.cpu0_wmst per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x900++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_0_cpu1_rmst_map0,The Map Register defines the fields for the master Ipulsar_sl_main_0.cpu1_rmst per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0xD00++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_0_cpu1_wmst_map0,The Map Register defines the fields for the master Ipulsar_sl_main_0.cpu1_wmst per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" tree.end tree.end tree "j7am_pulsar0_slv_cbass0" tree "j7am_pulsar0_slv_cbass0_ERR (j7am_pulsar0_slv_cbass0_ERR)" base ad:0x2A91000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end tree "j7am_pulsar0_slv_cbass0_GLB (j7am_pulsar0_slv_cbass0_GLB)" base ad:0x45B23400 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x20++0x3 line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x40++0x7 line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree.end tree.end tree "j7am_pulsar1" tree "j7am_pulsar1_mem_cbass0" tree "j7am_pulsar1_mem_cbass0_ERR (j7am_pulsar1_mem_cbass0_ERR)" base ad:0x2A92000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end tree "j7am_pulsar1_mem_cbass0_GLB (j7am_pulsar1_mem_cbass0_GLB)" base ad:0x45B23800 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x20++0x3 line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x40++0x7 line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree "j7am_pulsar1_mem_cbass0_ISC (j7am_pulsar1_mem_cbass0_ISC)" base ad:0x458D8000 rgroup.long 0x0++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_cpu0_rmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_1.cpu0_rmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x10++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_cpu0_rmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu0_rmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_cpu0_rmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu0_rmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_cpu0_rmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu0_rmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_cpu0_rmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu0_rmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_cpu0_rmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_1.cpu0_rmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x30++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_cpu0_rmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu0_rmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_cpu0_rmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu0_rmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_cpu0_rmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu0_rmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_cpu0_rmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu0_rmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_cpu0_rmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_1.cpu0_rmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x50++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_cpu0_rmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu0_rmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_cpu0_rmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu0_rmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_cpu0_rmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu0_rmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_cpu0_rmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu0_rmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_cpu0_rmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_1.cpu0_rmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x70++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_cpu0_rmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu0_rmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_cpu0_rmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu0_rmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_cpu0_rmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu0_rmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_cpu0_rmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu0_rmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_cpu0_rmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_1.cpu0_rmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x400++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_cpu0_wmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_1.cpu0_wmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x410++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_cpu0_wmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu0_wmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_cpu0_wmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu0_wmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_cpu0_wmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu0_wmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_cpu0_wmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu0_wmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_cpu0_wmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_1.cpu0_wmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x430++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_cpu0_wmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu0_wmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_cpu0_wmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu0_wmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_cpu0_wmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu0_wmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_cpu0_wmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu0_wmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_cpu0_wmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_1.cpu0_wmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x450++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_cpu0_wmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu0_wmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_cpu0_wmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu0_wmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_cpu0_wmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu0_wmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_cpu0_wmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu0_wmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_cpu0_wmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_1.cpu0_wmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x470++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_cpu0_wmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu0_wmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_cpu0_wmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu0_wmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_cpu0_wmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu0_wmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_cpu0_wmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu0_wmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_cpu0_wmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_1.cpu0_wmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x800++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_cpu1_rmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_1.cpu1_rmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x810++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_cpu1_rmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu1_rmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_cpu1_rmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu1_rmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_cpu1_rmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu1_rmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_cpu1_rmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu1_rmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_cpu1_rmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_1.cpu1_rmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x830++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_cpu1_rmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu1_rmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_cpu1_rmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu1_rmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_cpu1_rmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu1_rmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_cpu1_rmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu1_rmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_cpu1_rmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_1.cpu1_rmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x850++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_cpu1_rmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu1_rmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_cpu1_rmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu1_rmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_cpu1_rmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu1_rmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_cpu1_rmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu1_rmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_cpu1_rmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_1.cpu1_rmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x870++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_cpu1_rmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu1_rmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_cpu1_rmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu1_rmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_cpu1_rmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu1_rmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_cpu1_rmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu1_rmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_cpu1_rmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_1.cpu1_rmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC00++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_cpu1_wmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_1.cpu1_wmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC10++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_cpu1_wmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu1_wmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_cpu1_wmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu1_wmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_cpu1_wmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu1_wmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_cpu1_wmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu1_wmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_cpu1_wmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_1.cpu1_wmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC30++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_cpu1_wmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu1_wmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_cpu1_wmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu1_wmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_cpu1_wmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu1_wmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_cpu1_wmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu1_wmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_cpu1_wmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_1.cpu1_wmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC50++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_cpu1_wmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu1_wmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_cpu1_wmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu1_wmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_cpu1_wmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu1_wmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_cpu1_wmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu1_wmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_cpu1_wmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_1.cpu1_wmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC70++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_cpu1_wmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu1_wmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_cpu1_wmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu1_wmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_cpu1_wmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.cpu1_wmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_cpu1_wmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.cpu1_wmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_cpu1_wmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_1.cpu1_wmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1000++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_cpu0_rmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_2.cpu0_rmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1010++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_cpu0_rmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu0_rmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_cpu0_rmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu0_rmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_cpu0_rmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu0_rmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_cpu0_rmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu0_rmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_cpu0_rmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_2.cpu0_rmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1030++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_cpu0_rmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu0_rmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_cpu0_rmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu0_rmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_cpu0_rmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu0_rmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_cpu0_rmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu0_rmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_cpu0_rmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_2.cpu0_rmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1050++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_cpu0_rmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu0_rmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_cpu0_rmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu0_rmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_cpu0_rmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu0_rmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_cpu0_rmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu0_rmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_cpu0_rmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_2.cpu0_rmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1070++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_cpu0_rmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu0_rmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_cpu0_rmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu0_rmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_cpu0_rmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu0_rmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_cpu0_rmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu0_rmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_cpu0_rmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_2.cpu0_rmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1400++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_cpu0_wmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_2.cpu0_wmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1410++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_cpu0_wmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu0_wmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_cpu0_wmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu0_wmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_cpu0_wmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu0_wmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_cpu0_wmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu0_wmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_cpu0_wmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_2.cpu0_wmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1430++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_cpu0_wmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu0_wmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_cpu0_wmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu0_wmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_cpu0_wmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu0_wmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_cpu0_wmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu0_wmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_cpu0_wmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_2.cpu0_wmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1450++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_cpu0_wmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu0_wmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_cpu0_wmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu0_wmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_cpu0_wmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu0_wmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_cpu0_wmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu0_wmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_cpu0_wmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_2.cpu0_wmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1470++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_cpu0_wmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu0_wmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_cpu0_wmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu0_wmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_cpu0_wmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu0_wmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_cpu0_wmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu0_wmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_cpu0_wmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_2.cpu0_wmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1800++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_cpu1_rmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_2.cpu1_rmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1810++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_cpu1_rmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu1_rmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_cpu1_rmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu1_rmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_cpu1_rmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu1_rmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_cpu1_rmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu1_rmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_cpu1_rmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_2.cpu1_rmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1830++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_cpu1_rmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu1_rmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_cpu1_rmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu1_rmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_cpu1_rmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu1_rmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_cpu1_rmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu1_rmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_cpu1_rmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_2.cpu1_rmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1850++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_cpu1_rmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu1_rmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_cpu1_rmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu1_rmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_cpu1_rmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu1_rmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_cpu1_rmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu1_rmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_cpu1_rmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_2.cpu1_rmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1870++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_cpu1_rmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu1_rmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_cpu1_rmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu1_rmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_cpu1_rmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu1_rmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_cpu1_rmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu1_rmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_cpu1_rmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_2.cpu1_rmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1C00++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_cpu1_wmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_2.cpu1_wmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1C10++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_cpu1_wmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu1_wmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_cpu1_wmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu1_wmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_cpu1_wmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu1_wmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_cpu1_wmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu1_wmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_cpu1_wmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_2.cpu1_wmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1C30++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_cpu1_wmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu1_wmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_cpu1_wmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu1_wmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_cpu1_wmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu1_wmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_cpu1_wmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu1_wmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_cpu1_wmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_2.cpu1_wmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1C50++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_cpu1_wmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu1_wmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_cpu1_wmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu1_wmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_cpu1_wmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu1_wmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_cpu1_wmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu1_wmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_cpu1_wmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_2.cpu1_wmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1C70++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_cpu1_wmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu1_wmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_cpu1_wmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu1_wmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_cpu1_wmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.cpu1_wmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_cpu1_wmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.cpu1_wmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_cpu1_wmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_2.cpu1_wmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." tree.end tree "j7am_pulsar1_mem_cbass0_QOS (j7am_pulsar1_mem_cbass0_QOS)" base ad:0x45DA8000 rgroup.long 0x100++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_1_cpu0_rmst_map0,The Map Register defines the fields for the master Ipulsar_sl_main_1.cpu0_rmst per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x500++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_1_cpu0_wmst_map0,The Map Register defines the fields for the master Ipulsar_sl_main_1.cpu0_wmst per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x900++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_1_cpu1_rmst_map0,The Map Register defines the fields for the master Ipulsar_sl_main_1.cpu1_rmst per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0xD00++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_1_cpu1_wmst_map0,The Map Register defines the fields for the master Ipulsar_sl_main_1.cpu1_wmst per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x1100++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_2_cpu0_rmst_map0,The Map Register defines the fields for the master Ipulsar_sl_main_2.cpu0_rmst per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x1500++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_2_cpu0_wmst_map0,The Map Register defines the fields for the master Ipulsar_sl_main_2.cpu0_wmst per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x1900++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_2_cpu1_rmst_map0,The Map Register defines the fields for the master Ipulsar_sl_main_2.cpu1_rmst per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x1D00++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_2_cpu1_wmst_map0,The Map Register defines the fields for the master Ipulsar_sl_main_2.cpu1_wmst per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" tree.end tree.end tree "j7am_pulsar1_periph_switch" tree "j7am_pulsar1_periph_switch_cbass0_ERR (j7am_pulsar1_periph_switch_cbass0_ERR)" base ad:0x2A95000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end tree "j7am_pulsar1_periph_switch_cbass0_GLB (j7am_pulsar1_periph_switch_cbass0_GLB)" base ad:0x45B23C00 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end tree "j7am_pulsar1_periph_switch_cbass0_ISC (j7am_pulsar1_periph_switch_cbass0_ISC)" base ad:0x458CA000 rgroup.long 0x0++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst0_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_1.pbdg_rmst0 region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x10++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst0_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_rmst0 region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst0_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_rmst0 region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst0_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_rmst0 region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst0_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_rmst0 region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst0_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_1.pbdg_rmst0 region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x30++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst0_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_rmst0 region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst0_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_rmst0 region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst0_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_rmst0 region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst0_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_rmst0 region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst0_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_1.pbdg_rmst0 region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x50++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst0_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_rmst0 region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst0_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_rmst0 region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst0_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_rmst0 region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst0_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_rmst0 region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst0_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_1.pbdg_rmst0 region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x70++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst0_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_rmst0 region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst0_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_rmst0 region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst0_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_rmst0 region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst0_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_rmst0 region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst0_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_1.pbdg_rmst0 region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x400++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst0_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_1.pbdg_wmst0 region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x410++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst0_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_wmst0 region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst0_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_wmst0 region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst0_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_wmst0 region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst0_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_wmst0 region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst0_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_1.pbdg_wmst0 region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x430++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst0_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_wmst0 region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst0_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_wmst0 region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst0_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_wmst0 region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst0_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_wmst0 region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst0_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_1.pbdg_wmst0 region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x450++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst0_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_wmst0 region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst0_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_wmst0 region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst0_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_wmst0 region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst0_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_wmst0 region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst0_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_1.pbdg_wmst0 region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x470++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst0_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_wmst0 region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst0_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_wmst0 region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst0_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_wmst0 region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst0_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_wmst0 region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst0_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_1.pbdg_wmst0 region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x800++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst1_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_1.pbdg_rmst1 region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x810++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst1_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_rmst1 region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst1_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_rmst1 region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst1_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_rmst1 region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst1_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_rmst1 region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst1_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_1.pbdg_rmst1 region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x830++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst1_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_rmst1 region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst1_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_rmst1 region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst1_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_rmst1 region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst1_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_rmst1 region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst1_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_1.pbdg_rmst1 region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x850++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst1_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_rmst1 region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst1_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_rmst1 region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst1_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_rmst1 region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst1_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_rmst1 region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst1_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_1.pbdg_rmst1 region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x870++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst1_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_rmst1 region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst1_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_rmst1 region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst1_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_rmst1 region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst1_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_rmst1 region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_pbdg_rmst1_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_1.pbdg_rmst1 region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC00++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst1_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_1.pbdg_wmst1 region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC10++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst1_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_wmst1 region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst1_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_wmst1 region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst1_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_wmst1 region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst1_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_wmst1 region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst1_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_1.pbdg_wmst1 region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC30++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst1_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_wmst1 region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst1_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_wmst1 region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst1_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_wmst1 region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst1_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_wmst1 region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst1_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_1.pbdg_wmst1 region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC50++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst1_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_wmst1 region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst1_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_wmst1 region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst1_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_wmst1 region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst1_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_wmst1 region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst1_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_1.pbdg_wmst1 region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0xC70++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst1_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_wmst1 region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst1_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_wmst1 region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst1_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_1.pbdg_wmst1 region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst1_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_1.pbdg_wmst1 region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_1_pbdg_wmst1_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_1.pbdg_wmst1 region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1000++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst0_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_2.pbdg_rmst0 region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1010++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst0_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_rmst0 region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst0_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_rmst0 region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst0_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_rmst0 region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst0_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_rmst0 region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst0_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_2.pbdg_rmst0 region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1030++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst0_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_rmst0 region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst0_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_rmst0 region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst0_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_rmst0 region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst0_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_rmst0 region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst0_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_2.pbdg_rmst0 region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1050++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst0_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_rmst0 region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst0_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_rmst0 region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst0_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_rmst0 region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst0_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_rmst0 region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst0_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_2.pbdg_rmst0 region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1070++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst0_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_rmst0 region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst0_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_rmst0 region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst0_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_rmst0 region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst0_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_rmst0 region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst0_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_2.pbdg_rmst0 region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1400++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst0_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_2.pbdg_wmst0 region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1410++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst0_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_wmst0 region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst0_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_wmst0 region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst0_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_wmst0 region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst0_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_wmst0 region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst0_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_2.pbdg_wmst0 region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1430++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst0_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_wmst0 region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst0_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_wmst0 region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst0_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_wmst0 region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst0_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_wmst0 region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst0_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_2.pbdg_wmst0 region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1450++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst0_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_wmst0 region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst0_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_wmst0 region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst0_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_wmst0 region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst0_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_wmst0 region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst0_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_2.pbdg_wmst0 region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1470++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst0_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_wmst0 region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst0_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_wmst0 region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst0_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_wmst0 region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst0_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_wmst0 region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst0_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_2.pbdg_wmst0 region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1800++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst1_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_2.pbdg_rmst1 region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1810++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst1_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_rmst1 region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst1_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_rmst1 region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst1_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_rmst1 region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst1_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_rmst1 region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst1_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_2.pbdg_rmst1 region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1830++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst1_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_rmst1 region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst1_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_rmst1 region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst1_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_rmst1 region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst1_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_rmst1 region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst1_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_2.pbdg_rmst1 region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1850++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst1_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_rmst1 region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst1_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_rmst1 region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst1_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_rmst1 region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst1_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_rmst1 region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst1_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_2.pbdg_rmst1 region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1870++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst1_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_rmst1 region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst1_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_rmst1 region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst1_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_rmst1 region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst1_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_rmst1 region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_pbdg_rmst1_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_2.pbdg_rmst1 region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1C00++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst1_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_main_2.pbdg_wmst1 region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1C10++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst1_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_wmst1 region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst1_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_wmst1 region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst1_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_wmst1 region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst1_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_wmst1 region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst1_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_main_2.pbdg_wmst1 region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1C30++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst1_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_wmst1 region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst1_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_wmst1 region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst1_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_wmst1 region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst1_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_wmst1 region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst1_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_main_2.pbdg_wmst1 region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1C50++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst1_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_wmst1 region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst1_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_wmst1 region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst1_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_wmst1 region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst1_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_wmst1 region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst1_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_main_2.pbdg_wmst1 region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1C70++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst1_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_wmst1 region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst1_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_wmst1 region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst1_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_main_2.pbdg_wmst1 region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst1_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_main_2.pbdg_wmst1 region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_main_2_pbdg_wmst1_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_main_2.pbdg_wmst1 region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." tree.end tree "j7am_pulsar1_periph_switch_cbass0_QOS (j7am_pulsar1_periph_switch_cbass0_QOS)" base ad:0x45DCA000 rgroup.long 0x100++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_1_pbdg_rmst0_map0,The Map Register defines the fields for the master Ipulsar_sl_main_1.pbdg_rmst0 per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x500++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_1_pbdg_wmst0_map0,The Map Register defines the fields for the master Ipulsar_sl_main_1.pbdg_wmst0 per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x900++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_1_pbdg_rmst1_map0,The Map Register defines the fields for the master Ipulsar_sl_main_1.pbdg_rmst1 per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0xD00++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_1_pbdg_wmst1_map0,The Map Register defines the fields for the master Ipulsar_sl_main_1.pbdg_wmst1 per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x1100++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_2_pbdg_rmst0_map0,The Map Register defines the fields for the master Ipulsar_sl_main_2.pbdg_rmst0 per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x1500++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_2_pbdg_wmst0_map0,The Map Register defines the fields for the master Ipulsar_sl_main_2.pbdg_wmst0 per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x1900++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_2_pbdg_rmst1_map0,The Map Register defines the fields for the master Ipulsar_sl_main_2.pbdg_rmst1 per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x1D00++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_main_2_pbdg_wmst1_map0,The Map Register defines the fields for the master Ipulsar_sl_main_2.pbdg_wmst1 per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" tree.end tree.end tree.end tree "j7am_rc_to" tree "j7am_rc_to_hc2" tree "j7am_rc_to_hc2_stog6_CFG (j7am_rc_to_hc2_stog6_CFG)" base ad:0x260C000 rgroup.long 0x0++0xB line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end tree "j7am_rc_to_hc2_stog7_CFG (j7am_rc_to_hc2_stog7_CFG)" base ad:0x2606000 rgroup.long 0x0++0xB line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end tree.end tree "j7am_rc_to_rc_cfg_stog3_CFG (j7am_rc_to_rc_cfg_stog3_CFG)" base ad:0x2608000 rgroup.long 0x0++0xB line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end tree.end tree.end tree "MAIN" base ad:0x0 tree "MAIN2MCU" tree "MAIN2MCU_LVL_INTRTR0_CFG (MAIN2MCU_LVL_INTRTR0_CFG)" base ad:0xA10000 rgroup.long 0x0++0x3 line.long 0x0 "INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" rgroup.long 0x4++0x3 line.long 0x0 "INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.word 0x0 0.--8. 1. "MUX_CNTL,Mux control for interrupt N" tree.end tree "MAIN2MCU_PLS_INTRTR0_CFG (MAIN2MCU_PLS_INTRTR0_CFG)" base ad:0xA20000 rgroup.long 0x0++0x3 line.long 0x0 "INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" rgroup.long 0x4++0x3 line.long 0x0 "INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.byte 0x0 0.--6. 1. "MUX_CNTL,Mux control for interrupt N" tree.end tree.end tree "MAIN_CBASS0" tree "MAIN_CBASS0_ERR (MAIN_CBASS0_ERR)" base ad:0xB00000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end tree "MAIN_CBASS0_GLB (MAIN_CBASS0_GLB)" base ad:0x45B0C000 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x20++0x3 line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x40++0x7 line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree.end tree "MAIN_IP_ECC_AGGR0_ECC_AGGR (MAIN_IP_ECC_AGGR0_ECC_AGGR)" base ad:0x2AF6000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 30. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_5_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_IPPHY_VBUSM_L0_STOG_8_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_ipphy_vbusm_l0_stog_8_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_IPPHY_VBUSM_L0_STOG_8_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_ipphy_vbusm_l0_stog_8_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 23. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_BR_BR_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_RTI_CFG1_MAIN_GPU_SLV_STOG_7_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_rti_cfg1_main_gpu_slv_stog_7_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_6_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_RTI_CFG1_MAIN_GPU_SLV_STOG_7_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_rti_cfg1_main_gpu_slv_stog_7_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 10. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 9. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 8. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_7_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 7. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_RTI_CFG1_MAIN_GPU_SLV_STOG_7_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_rti_cfg1_main_gpu_slv_stog_7_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 6. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 5. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 4. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 1. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 0. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RTI_GPU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RTI_GPU_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" line.long 0x8 "REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x8 23. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_IPPHY_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_IPPHY_VBUSP_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 21. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 19. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 18. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 17. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 16. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 15. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 14. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 13. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_J7AM_FW_TO_FW_P2P_BRIDGE_J7AM_FW_TO_FW_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 12. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 11. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_IPPHY_VBUSM_L0_STOG_8_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_ipphy_vbusm_l0_stog_8_rd_ramecc_pend" "0,1" newline bitfld.long 0x8 10. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_J7AM_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRM_32B_CLK2_SCR_J7AM_IPPHY_SAFE_CBASS_SCRM_32B_CLK2_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_IPPHY_SAFE_DMSC_SLV_P2P_BRIDGE_IPPHY_SAFE_DMSC_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_IPPHY_SAFE_DMSC_SLV_P2P_BRIDGE_IPPHY_SAFE_DMSC_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ERR_SCR_J7AM_IPPHY_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_BR_BR_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x7 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 30. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_5_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_IPPHY_VBUSM_L0_STOG_8_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_ipphy_vbusm_l0_stog_8_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_IPPHY_VBUSM_L0_STOG_8_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_ipphy_vbusm_l0_stog_8_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 23. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_BR_BR_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_RTI_CFG1_MAIN_GPU_SLV_STOG_7_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_rti_cfg1_main_gpu_slv_stog_7_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_6_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_RTI_CFG1_MAIN_GPU_SLV_STOG_7_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_rti_cfg1_main_gpu_slv_stog_7_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 10. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 9. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 8. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_7_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 7. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_RTI_CFG1_MAIN_GPU_SLV_STOG_7_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_rti_cfg1_main_gpu_slv_stog_7_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 6. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 5. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 4. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 3. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 2. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 1. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 0. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RTI_GPU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RTI_GPU_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" line.long 0x4 "REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x4 23. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set.." "0,1" newline bitfld.long 0x4 22. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_IPPHY_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_IPPHY_VBUSP_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 21. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 19. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 18. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 17. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 16. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 15. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 14. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 13. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_J7AM_FW_TO_FW_P2P_BRIDGE_J7AM_FW_TO_FW_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 12. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 11. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_IPPHY_VBUSM_L0_STOG_8_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_ipphy_vbusm_l0_stog_8_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_J7AM_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRM_32B_CLK2_SCR_J7AM_IPPHY_SAFE_CBASS_SCRM_32B_CLK2_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_IPPHY_SAFE_DMSC_SLV_P2P_BRIDGE_IPPHY_SAFE_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_IPPHY_SAFE_DMSC_SLV_P2P_BRIDGE_IPPHY_SAFE_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ERR_SCR_J7AM_IPPHY_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_BR_BR_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 30. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_5_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_IPPHY_VBUSM_L0_STOG_8_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_ipphy_vbusm_l0_stog_8_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_IPPHY_VBUSM_L0_STOG_8_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_ipphy_vbusm_l0_stog_8_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 23. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_BR_BR_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_RTI_CFG1_MAIN_GPU_SLV_STOG_7_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_rti_cfg1_main_gpu_slv_stog_7_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_6_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_RTI_CFG1_MAIN_GPU_SLV_STOG_7_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_rti_cfg1_main_gpu_slv_stog_7_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 10. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 9. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 8. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_7_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 7. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_RTI_CFG1_MAIN_GPU_SLV_STOG_7_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_rti_cfg1_main_gpu_slv_stog_7_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 6. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 5. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 4. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 3. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 2. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 1. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 0. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RTI_GPU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RTI_GPU_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" line.long 0x4 "REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x4 23. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear.." "0,1" newline bitfld.long 0x4 22. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_IPPHY_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_IPPHY_VBUSP_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 21. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register.." "0,1" newline bitfld.long 0x4 19. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 18. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 17. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 16. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 15. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 14. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 13. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_J7AM_FW_TO_FW_P2P_BRIDGE_J7AM_FW_TO_FW_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 12. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 11. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_IPPHY_VBUSM_L0_STOG_8_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_ipphy_vbusm_l0_stog_8_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_J7AM_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRM_32B_CLK2_SCR_J7AM_IPPHY_SAFE_CBASS_SCRM_32B_CLK2_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_IPPHY_SAFE_DMSC_SLV_P2P_BRIDGE_IPPHY_SAFE_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_IPPHY_SAFE_DMSC_SLV_P2P_BRIDGE_IPPHY_SAFE_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ERR_SCR_J7AM_IPPHY_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_BR_BR_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0xB line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 30. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_5_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_IPPHY_VBUSM_L0_STOG_8_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_ipphy_vbusm_l0_stog_8_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_IPPHY_VBUSM_L0_STOG_8_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_ipphy_vbusm_l0_stog_8_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 23. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_BR_BR_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_RTI_CFG1_MAIN_GPU_SLV_STOG_7_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_rti_cfg1_main_gpu_slv_stog_7_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_6_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_RTI_CFG1_MAIN_GPU_SLV_STOG_7_WR_RAMECC_PEND,Interrupt Pending Status for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_rti_cfg1_main_gpu_slv_stog_7_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 10. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 9. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 8. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_7_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 7. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_RTI_CFG1_MAIN_GPU_SLV_STOG_7_EDC_CTRL_PEND,Interrupt Pending Status for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_rti_cfg1_main_gpu_slv_stog_7_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 6. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 5. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 4. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 1. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 0. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RTI_GPU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RTI_GPU_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" line.long 0x8 "REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x8 23. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_IPPHY_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_IPPHY_VBUSP_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 21. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 19. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 18. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 17. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 16. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 15. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 14. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 13. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_J7AM_FW_TO_FW_P2P_BRIDGE_J7AM_FW_TO_FW_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 12. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 11. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_IPPHY_VBUSM_L0_STOG_8_RD_RAMECC_PEND,Interrupt Pending Status for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_ipphy_vbusm_l0_stog_8_rd_ramecc_pend" "0,1" newline bitfld.long 0x8 10. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_J7AM_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRM_32B_CLK2_SCR_J7AM_IPPHY_SAFE_CBASS_SCRM_32B_CLK2_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_IPPHY_SAFE_DMSC_SLV_P2P_BRIDGE_IPPHY_SAFE_DMSC_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_IPPHY_SAFE_DMSC_SLV_P2P_BRIDGE_IPPHY_SAFE_DMSC_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ERR_SCR_J7AM_IPPHY_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_BR_BR_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x7 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 30. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_5_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_IPPHY_VBUSM_L0_STOG_8_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_ipphy_vbusm_l0_stog_8_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_IPPHY_VBUSM_L0_STOG_8_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_ipphy_vbusm_l0_stog_8_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 23. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_BR_BR_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_RTI_CFG1_MAIN_GPU_SLV_STOG_7_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_rti_cfg1_main_gpu_slv_stog_7_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_6_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_RTI_CFG1_MAIN_GPU_SLV_STOG_7_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_rti_cfg1_main_gpu_slv_stog_7_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 10. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 9. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 8. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_7_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 7. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_RTI_CFG1_MAIN_GPU_SLV_STOG_7_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_rti_cfg1_main_gpu_slv_stog_7_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 6. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 5. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 4. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 3. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 2. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 1. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 0. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RTI_GPU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RTI_GPU_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" line.long 0x4 "REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x4 23. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set.." "0,1" newline bitfld.long 0x4 22. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_IPPHY_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_IPPHY_VBUSP_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 21. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 19. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 18. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 17. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 16. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 15. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 14. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 13. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_J7AM_FW_TO_FW_P2P_BRIDGE_J7AM_FW_TO_FW_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 12. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 11. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_IPPHY_VBUSM_L0_STOG_8_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_ipphy_vbusm_l0_stog_8_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_J7AM_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRM_32B_CLK2_SCR_J7AM_IPPHY_SAFE_CBASS_SCRM_32B_CLK2_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_IPPHY_SAFE_DMSC_SLV_P2P_BRIDGE_IPPHY_SAFE_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_IPPHY_SAFE_DMSC_SLV_P2P_BRIDGE_IPPHY_SAFE_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ERR_SCR_J7AM_IPPHY_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_BR_BR_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 30. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_5_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_IPPHY_VBUSM_L0_STOG_8_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_ipphy_vbusm_l0_stog_8_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_IPPHY_VBUSM_L0_STOG_8_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_ipphy_vbusm_l0_stog_8_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 23. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_BR_BR_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_RTI_CFG1_MAIN_GPU_SLV_STOG_7_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_rti_cfg1_main_gpu_slv_stog_7_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_6_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_RTI_CFG1_MAIN_GPU_SLV_STOG_7_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_rti_cfg1_main_gpu_slv_stog_7_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 10. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 9. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 8. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_7_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 7. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_RTI_CFG1_MAIN_GPU_SLV_STOG_7_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_rti_cfg1_main_gpu_slv_stog_7_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 6. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 5. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_IPPHY_TO_IPPHY_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 4. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7AM_MAIN_IP_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 3. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_MCU_TO_IPPHY_VBUSP_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 2. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_IPPHY_TO_RC_VBUSP_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 1. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_0_J7AM_IPPHY_CBASS_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 0. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RTI_GPU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RTI_GPU_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" line.long 0x4 "REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x4 23. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_TO_IPPHY_SWITCH_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear.." "0,1" newline bitfld.long 0x4 22. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_IPPHY_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_PULSAR1_PERIPH_SWITCH_TO_IPPHY_VBUSP_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 21. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_RC_TO_IPPHY_VBUSP_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_EXPORT_J7AM_IPPHY_TO_AC_CFG_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register.." "0,1" newline bitfld.long 0x4 19. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 18. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 17. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 16. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 15. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_J7AM_IPPHY_SAFE_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 14. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 13. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_J7AM_FW_TO_FW_P2P_BRIDGE_J7AM_FW_TO_FW_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 12. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 11. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_TO_IPPHY_VBUSM_L0_STOG_8_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ij7am_ipphy_cbass_wrap_0_Ij7am_ipphy_to_ipphy_vbusm_l0_stog_8_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_J7AM_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_SCRM_32B_CLK2_SCR_J7AM_IPPHY_SAFE_CBASS_SCRM_32B_CLK2_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_IPPHY_SAFE_DMSC_SLV_P2P_BRIDGE_IPPHY_SAFE_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_CBASS_MAIN_FW_CBASS_0_J7AM_IPPHY_CBASS_MAIN_FW_CBASS_IPPHY_SAFE_DMSC_SLV_P2P_BRIDGE_IPPHY_SAFE_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ERR_SCR_J7AM_IPPHY_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_J7AM_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_BR_BR_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_BR_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "IJ7AM_IPPHY_CBASS_WRAP_0_IJ7AM_IPPHY_SAFE_CBASS_0_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7AM_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MAIN_USART_PSILSS0_MMRS (MAIN_USART_PSILSS0_MMRS)" base ad:0x3400000 rgroup.long 0x0++0x7 line.long 0x0 "MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." rgroup.long 0x10++0x3 line.long 0x0 "MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." rgroup.long 0x40++0x3 line.long 0x0 "MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end tree.end tree "MCAN" base ad:0x0 tree "MCAN0" tree "MCAN0_CFG (MCAN0_CFG)" base ad:0x2701000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" rgroup.long 0x8++0x37 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point" newline hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection" rbitfld.long 0x8 7. "RX,Receive Pin" "0,1" bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM" hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration" bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1" bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1" bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1" newline bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0x10 0. "INIT,Initialization" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing" hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter" hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter" hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x4B line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" newline bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable" bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)" bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field" line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address" line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field" line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" rgroup.long 0x98++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x0 31. "ND31,New Data" "0,1" bitfld.long 0x0 30. "ND30,New Data" "0,1" bitfld.long 0x0 29. "ND29,New Data" "0,1" newline bitfld.long 0x0 28. "ND28,New Data" "0,1" bitfld.long 0x0 27. "ND27,New Data" "0,1" bitfld.long 0x0 26. "ND26,New Data" "0,1" newline bitfld.long 0x0 25. "ND25,New Data" "0,1" bitfld.long 0x0 24. "ND24,New Data" "0,1" bitfld.long 0x0 23. "ND23,New Data" "0,1" newline bitfld.long 0x0 22. "ND22,New Data" "0,1" bitfld.long 0x0 21. "ND21,New Data" "0,1" bitfld.long 0x0 20. "ND20,New Data" "0,1" newline bitfld.long 0x0 19. "ND19,New Data" "0,1" bitfld.long 0x0 18. "ND18,New Data" "0,1" bitfld.long 0x0 17. "ND17,New Data" "0,1" newline bitfld.long 0x0 16. "ND16,New Data" "0,1" bitfld.long 0x0 15. "ND15,New Data" "0,1" bitfld.long 0x0 14. "ND14,New Data" "0,1" newline bitfld.long 0x0 13. "ND13,New Data" "0,1" bitfld.long 0x0 12. "ND12,New Data" "0,1" bitfld.long 0x0 11. "ND11,New Data" "0,1" newline bitfld.long 0x0 10. "ND10,New Data" "0,1" bitfld.long 0x0 9. "ND9,New Data" "0,1" bitfld.long 0x0 8. "ND8,New Data" "0,1" newline bitfld.long 0x0 7. "ND7,New Data" "0,1" bitfld.long 0x0 6. "ND6,New Data" "0,1" bitfld.long 0x0 5. "ND5,New Data" "0,1" newline bitfld.long 0x0 4. "ND4,New Data" "0,1" bitfld.long 0x0 3. "ND3,New Data" "0,1" bitfld.long 0x0 2. "ND2,New Data" "0,1" newline bitfld.long 0x0 1. "ND1,New Data" "0,1" bitfld.long 0x0 0. "ND0,New Data" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x4 31. "ND63,New Data" "0,1" bitfld.long 0x4 30. "ND62,New Data" "0,1" bitfld.long 0x4 29. "ND61,New Data" "0,1" newline bitfld.long 0x4 28. "ND60,New Data" "0,1" bitfld.long 0x4 27. "ND59,New Data" "0,1" bitfld.long 0x4 26. "ND58,New Data" "0,1" newline bitfld.long 0x4 25. "ND57,New Data" "0,1" bitfld.long 0x4 24. "ND56,New Data" "0,1" bitfld.long 0x4 23. "ND55,New Data" "0,1" newline bitfld.long 0x4 22. "ND54,New Data" "0,1" bitfld.long 0x4 21. "ND53,New Data" "0,1" bitfld.long 0x4 20. "ND52,New Data" "0,1" newline bitfld.long 0x4 19. "ND51,New Data" "0,1" bitfld.long 0x4 18. "ND50,New Data" "0,1" bitfld.long 0x4 17. "ND49,New Data" "0,1" newline bitfld.long 0x4 16. "ND48,New Data" "0,1" bitfld.long 0x4 15. "ND47,New Data" "0,1" bitfld.long 0x4 14. "ND46,New Data" "0,1" newline bitfld.long 0x4 13. "ND45,New Data" "0,1" bitfld.long 0x4 12. "ND44,New Data" "0,1" bitfld.long 0x4 11. "ND43,New Data" "0,1" newline bitfld.long 0x4 10. "ND42,New Data" "0,1" bitfld.long 0x4 9. "ND41,New Data" "0,1" bitfld.long 0x4 8. "ND40,New Data" "0,1" newline bitfld.long 0x4 7. "ND39,New Data" "0,1" bitfld.long 0x4 6. "ND38,New Data" "0,1" bitfld.long 0x4 5. "ND37,New Data" "0,1" newline bitfld.long 0x4 4. "ND36,New Data" "0,1" bitfld.long 0x4 3. "ND35,New Data" "0,1" bitfld.long 0x4 2. "ND34,New Data" "0,1" newline bitfld.long 0x4 1. "ND33,New Data" "0,1" bitfld.long 0x4 0. "ND32,New Data" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" rgroup.long 0xA8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" rgroup.long 0xB8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" rgroup.long 0xC8++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1" rgroup.long 0xD0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests" bitfld.long 0x0 31. "AR31,Add request" "0,1" bitfld.long 0x0 30. "AR30,Add request" "0,1" bitfld.long 0x0 29. "AR29,Add request" "0,1" newline bitfld.long 0x0 28. "AR28,Add request" "0,1" bitfld.long 0x0 27. "AR27,Add request" "0,1" bitfld.long 0x0 26. "AR26,Add request" "0,1" newline bitfld.long 0x0 25. "AR25,Add request" "0,1" bitfld.long 0x0 24. "AR24,Add request" "0,1" bitfld.long 0x0 23. "AR23,Add request" "0,1" newline bitfld.long 0x0 22. "AR22,Add request" "0,1" bitfld.long 0x0 21. "AR21,Add request" "0,1" bitfld.long 0x0 20. "AR20,Add request" "0,1" newline bitfld.long 0x0 19. "AR19,Add request" "0,1" bitfld.long 0x0 18. "AR18,Add request" "0,1" bitfld.long 0x0 17. "AR17,Add request" "0,1" newline bitfld.long 0x0 16. "AR16,Add request" "0,1" bitfld.long 0x0 15. "AR15,Add request" "0,1" bitfld.long 0x0 14. "AR14,Add request" "0,1" newline bitfld.long 0x0 13. "AR13,Add request" "0,1" bitfld.long 0x0 12. "AR12,Add request" "0,1" bitfld.long 0x0 11. "AR11,Add request" "0,1" newline bitfld.long 0x0 10. "AR10,Add request" "0,1" bitfld.long 0x0 9. "AR9,Add request" "0,1" bitfld.long 0x0 8. "AR8,Add request" "0,1" newline bitfld.long 0x0 7. "AR7,Add request" "0,1" bitfld.long 0x0 6. "AR6,Add request" "0,1" bitfld.long 0x0 5. "AR5,Add request" "0,1" newline bitfld.long 0x0 4. "AR4,Add request" "0,1" bitfld.long 0x0 3. "AR3,Add request" "0,1" bitfld.long 0x0 2. "AR2,Add request" "0,1" newline bitfld.long 0x0 1. "AR1,Add request" "0,1" bitfld.long 0x0 0. "AR0,Add request" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions" bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1" rgroup.long 0xE0++0x13 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" rgroup.long 0xF8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field" tree.end tree "MCAN0_ECC_AGGR (MCAN0_ECC_AGGR)" base ad:0x2A78000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCAN0_MSGMEM_RAM (MCAN0_MSGMEM_RAM)" base ad:0x2708000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCAN0_SS (MCAN0_SS)" base ad:0x2700000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0: Honor Debug Suspend,1: Disregard debug suspend" rgroup.long 0x8++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS" bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1" newline bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" rgroup.long 0xC++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1" rgroup.long 0x10++0xB line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits." bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1" line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1" line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" rgroup.long 0x24++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1" rgroup.long 0x28++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt" tree.end tree.end tree "MCAN1" tree "MCAN1_CFG (MCAN1_CFG)" base ad:0x2711000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" rgroup.long 0x8++0x37 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point" newline hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection" rbitfld.long 0x8 7. "RX,Receive Pin" "0,1" bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM" hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration" bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1" bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1" bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1" newline bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0x10 0. "INIT,Initialization" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing" hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter" hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter" hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x4B line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" newline bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable" bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)" bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field" line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address" line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field" line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" rgroup.long 0x98++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x0 31. "ND31,New Data" "0,1" bitfld.long 0x0 30. "ND30,New Data" "0,1" bitfld.long 0x0 29. "ND29,New Data" "0,1" newline bitfld.long 0x0 28. "ND28,New Data" "0,1" bitfld.long 0x0 27. "ND27,New Data" "0,1" bitfld.long 0x0 26. "ND26,New Data" "0,1" newline bitfld.long 0x0 25. "ND25,New Data" "0,1" bitfld.long 0x0 24. "ND24,New Data" "0,1" bitfld.long 0x0 23. "ND23,New Data" "0,1" newline bitfld.long 0x0 22. "ND22,New Data" "0,1" bitfld.long 0x0 21. "ND21,New Data" "0,1" bitfld.long 0x0 20. "ND20,New Data" "0,1" newline bitfld.long 0x0 19. "ND19,New Data" "0,1" bitfld.long 0x0 18. "ND18,New Data" "0,1" bitfld.long 0x0 17. "ND17,New Data" "0,1" newline bitfld.long 0x0 16. "ND16,New Data" "0,1" bitfld.long 0x0 15. "ND15,New Data" "0,1" bitfld.long 0x0 14. "ND14,New Data" "0,1" newline bitfld.long 0x0 13. "ND13,New Data" "0,1" bitfld.long 0x0 12. "ND12,New Data" "0,1" bitfld.long 0x0 11. "ND11,New Data" "0,1" newline bitfld.long 0x0 10. "ND10,New Data" "0,1" bitfld.long 0x0 9. "ND9,New Data" "0,1" bitfld.long 0x0 8. "ND8,New Data" "0,1" newline bitfld.long 0x0 7. "ND7,New Data" "0,1" bitfld.long 0x0 6. "ND6,New Data" "0,1" bitfld.long 0x0 5. "ND5,New Data" "0,1" newline bitfld.long 0x0 4. "ND4,New Data" "0,1" bitfld.long 0x0 3. "ND3,New Data" "0,1" bitfld.long 0x0 2. "ND2,New Data" "0,1" newline bitfld.long 0x0 1. "ND1,New Data" "0,1" bitfld.long 0x0 0. "ND0,New Data" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x4 31. "ND63,New Data" "0,1" bitfld.long 0x4 30. "ND62,New Data" "0,1" bitfld.long 0x4 29. "ND61,New Data" "0,1" newline bitfld.long 0x4 28. "ND60,New Data" "0,1" bitfld.long 0x4 27. "ND59,New Data" "0,1" bitfld.long 0x4 26. "ND58,New Data" "0,1" newline bitfld.long 0x4 25. "ND57,New Data" "0,1" bitfld.long 0x4 24. "ND56,New Data" "0,1" bitfld.long 0x4 23. "ND55,New Data" "0,1" newline bitfld.long 0x4 22. "ND54,New Data" "0,1" bitfld.long 0x4 21. "ND53,New Data" "0,1" bitfld.long 0x4 20. "ND52,New Data" "0,1" newline bitfld.long 0x4 19. "ND51,New Data" "0,1" bitfld.long 0x4 18. "ND50,New Data" "0,1" bitfld.long 0x4 17. "ND49,New Data" "0,1" newline bitfld.long 0x4 16. "ND48,New Data" "0,1" bitfld.long 0x4 15. "ND47,New Data" "0,1" bitfld.long 0x4 14. "ND46,New Data" "0,1" newline bitfld.long 0x4 13. "ND45,New Data" "0,1" bitfld.long 0x4 12. "ND44,New Data" "0,1" bitfld.long 0x4 11. "ND43,New Data" "0,1" newline bitfld.long 0x4 10. "ND42,New Data" "0,1" bitfld.long 0x4 9. "ND41,New Data" "0,1" bitfld.long 0x4 8. "ND40,New Data" "0,1" newline bitfld.long 0x4 7. "ND39,New Data" "0,1" bitfld.long 0x4 6. "ND38,New Data" "0,1" bitfld.long 0x4 5. "ND37,New Data" "0,1" newline bitfld.long 0x4 4. "ND36,New Data" "0,1" bitfld.long 0x4 3. "ND35,New Data" "0,1" bitfld.long 0x4 2. "ND34,New Data" "0,1" newline bitfld.long 0x4 1. "ND33,New Data" "0,1" bitfld.long 0x4 0. "ND32,New Data" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" rgroup.long 0xA8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" rgroup.long 0xB8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" rgroup.long 0xC8++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1" rgroup.long 0xD0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests" bitfld.long 0x0 31. "AR31,Add request" "0,1" bitfld.long 0x0 30. "AR30,Add request" "0,1" bitfld.long 0x0 29. "AR29,Add request" "0,1" newline bitfld.long 0x0 28. "AR28,Add request" "0,1" bitfld.long 0x0 27. "AR27,Add request" "0,1" bitfld.long 0x0 26. "AR26,Add request" "0,1" newline bitfld.long 0x0 25. "AR25,Add request" "0,1" bitfld.long 0x0 24. "AR24,Add request" "0,1" bitfld.long 0x0 23. "AR23,Add request" "0,1" newline bitfld.long 0x0 22. "AR22,Add request" "0,1" bitfld.long 0x0 21. "AR21,Add request" "0,1" bitfld.long 0x0 20. "AR20,Add request" "0,1" newline bitfld.long 0x0 19. "AR19,Add request" "0,1" bitfld.long 0x0 18. "AR18,Add request" "0,1" bitfld.long 0x0 17. "AR17,Add request" "0,1" newline bitfld.long 0x0 16. "AR16,Add request" "0,1" bitfld.long 0x0 15. "AR15,Add request" "0,1" bitfld.long 0x0 14. "AR14,Add request" "0,1" newline bitfld.long 0x0 13. "AR13,Add request" "0,1" bitfld.long 0x0 12. "AR12,Add request" "0,1" bitfld.long 0x0 11. "AR11,Add request" "0,1" newline bitfld.long 0x0 10. "AR10,Add request" "0,1" bitfld.long 0x0 9. "AR9,Add request" "0,1" bitfld.long 0x0 8. "AR8,Add request" "0,1" newline bitfld.long 0x0 7. "AR7,Add request" "0,1" bitfld.long 0x0 6. "AR6,Add request" "0,1" bitfld.long 0x0 5. "AR5,Add request" "0,1" newline bitfld.long 0x0 4. "AR4,Add request" "0,1" bitfld.long 0x0 3. "AR3,Add request" "0,1" bitfld.long 0x0 2. "AR2,Add request" "0,1" newline bitfld.long 0x0 1. "AR1,Add request" "0,1" bitfld.long 0x0 0. "AR0,Add request" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions" bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1" rgroup.long 0xE0++0x13 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" rgroup.long 0xF8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field" tree.end tree "MCAN1_ECC_AGGR (MCAN1_ECC_AGGR)" base ad:0x2A79000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCAN1_MSGMEM_RAM (MCAN1_MSGMEM_RAM)" base ad:0x2718000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCAN1_SS (MCAN1_SS)" base ad:0x2710000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0: Honor Debug Suspend,1: Disregard debug suspend" rgroup.long 0x8++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS" bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1" newline bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" rgroup.long 0xC++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1" rgroup.long 0x10++0xB line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits." bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1" line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1" line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" rgroup.long 0x24++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1" rgroup.long 0x28++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt" tree.end tree "MCAN10_CFG (MCAN10_CFG)" base ad:0x27A1000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" rgroup.long 0x8++0x37 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point" newline hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection" rbitfld.long 0x8 7. "RX,Receive Pin" "0,1" bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM" hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration" bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1" bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1" bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1" newline bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0x10 0. "INIT,Initialization" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing" hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter" hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter" hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x4B line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" newline bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable" bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)" bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field" line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address" line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field" line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" rgroup.long 0x98++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x0 31. "ND31,New Data" "0,1" bitfld.long 0x0 30. "ND30,New Data" "0,1" bitfld.long 0x0 29. "ND29,New Data" "0,1" newline bitfld.long 0x0 28. "ND28,New Data" "0,1" bitfld.long 0x0 27. "ND27,New Data" "0,1" bitfld.long 0x0 26. "ND26,New Data" "0,1" newline bitfld.long 0x0 25. "ND25,New Data" "0,1" bitfld.long 0x0 24. "ND24,New Data" "0,1" bitfld.long 0x0 23. "ND23,New Data" "0,1" newline bitfld.long 0x0 22. "ND22,New Data" "0,1" bitfld.long 0x0 21. "ND21,New Data" "0,1" bitfld.long 0x0 20. "ND20,New Data" "0,1" newline bitfld.long 0x0 19. "ND19,New Data" "0,1" bitfld.long 0x0 18. "ND18,New Data" "0,1" bitfld.long 0x0 17. "ND17,New Data" "0,1" newline bitfld.long 0x0 16. "ND16,New Data" "0,1" bitfld.long 0x0 15. "ND15,New Data" "0,1" bitfld.long 0x0 14. "ND14,New Data" "0,1" newline bitfld.long 0x0 13. "ND13,New Data" "0,1" bitfld.long 0x0 12. "ND12,New Data" "0,1" bitfld.long 0x0 11. "ND11,New Data" "0,1" newline bitfld.long 0x0 10. "ND10,New Data" "0,1" bitfld.long 0x0 9. "ND9,New Data" "0,1" bitfld.long 0x0 8. "ND8,New Data" "0,1" newline bitfld.long 0x0 7. "ND7,New Data" "0,1" bitfld.long 0x0 6. "ND6,New Data" "0,1" bitfld.long 0x0 5. "ND5,New Data" "0,1" newline bitfld.long 0x0 4. "ND4,New Data" "0,1" bitfld.long 0x0 3. "ND3,New Data" "0,1" bitfld.long 0x0 2. "ND2,New Data" "0,1" newline bitfld.long 0x0 1. "ND1,New Data" "0,1" bitfld.long 0x0 0. "ND0,New Data" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x4 31. "ND63,New Data" "0,1" bitfld.long 0x4 30. "ND62,New Data" "0,1" bitfld.long 0x4 29. "ND61,New Data" "0,1" newline bitfld.long 0x4 28. "ND60,New Data" "0,1" bitfld.long 0x4 27. "ND59,New Data" "0,1" bitfld.long 0x4 26. "ND58,New Data" "0,1" newline bitfld.long 0x4 25. "ND57,New Data" "0,1" bitfld.long 0x4 24. "ND56,New Data" "0,1" bitfld.long 0x4 23. "ND55,New Data" "0,1" newline bitfld.long 0x4 22. "ND54,New Data" "0,1" bitfld.long 0x4 21. "ND53,New Data" "0,1" bitfld.long 0x4 20. "ND52,New Data" "0,1" newline bitfld.long 0x4 19. "ND51,New Data" "0,1" bitfld.long 0x4 18. "ND50,New Data" "0,1" bitfld.long 0x4 17. "ND49,New Data" "0,1" newline bitfld.long 0x4 16. "ND48,New Data" "0,1" bitfld.long 0x4 15. "ND47,New Data" "0,1" bitfld.long 0x4 14. "ND46,New Data" "0,1" newline bitfld.long 0x4 13. "ND45,New Data" "0,1" bitfld.long 0x4 12. "ND44,New Data" "0,1" bitfld.long 0x4 11. "ND43,New Data" "0,1" newline bitfld.long 0x4 10. "ND42,New Data" "0,1" bitfld.long 0x4 9. "ND41,New Data" "0,1" bitfld.long 0x4 8. "ND40,New Data" "0,1" newline bitfld.long 0x4 7. "ND39,New Data" "0,1" bitfld.long 0x4 6. "ND38,New Data" "0,1" bitfld.long 0x4 5. "ND37,New Data" "0,1" newline bitfld.long 0x4 4. "ND36,New Data" "0,1" bitfld.long 0x4 3. "ND35,New Data" "0,1" bitfld.long 0x4 2. "ND34,New Data" "0,1" newline bitfld.long 0x4 1. "ND33,New Data" "0,1" bitfld.long 0x4 0. "ND32,New Data" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" rgroup.long 0xA8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" rgroup.long 0xB8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" rgroup.long 0xC8++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1" rgroup.long 0xD0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests" bitfld.long 0x0 31. "AR31,Add request" "0,1" bitfld.long 0x0 30. "AR30,Add request" "0,1" bitfld.long 0x0 29. "AR29,Add request" "0,1" newline bitfld.long 0x0 28. "AR28,Add request" "0,1" bitfld.long 0x0 27. "AR27,Add request" "0,1" bitfld.long 0x0 26. "AR26,Add request" "0,1" newline bitfld.long 0x0 25. "AR25,Add request" "0,1" bitfld.long 0x0 24. "AR24,Add request" "0,1" bitfld.long 0x0 23. "AR23,Add request" "0,1" newline bitfld.long 0x0 22. "AR22,Add request" "0,1" bitfld.long 0x0 21. "AR21,Add request" "0,1" bitfld.long 0x0 20. "AR20,Add request" "0,1" newline bitfld.long 0x0 19. "AR19,Add request" "0,1" bitfld.long 0x0 18. "AR18,Add request" "0,1" bitfld.long 0x0 17. "AR17,Add request" "0,1" newline bitfld.long 0x0 16. "AR16,Add request" "0,1" bitfld.long 0x0 15. "AR15,Add request" "0,1" bitfld.long 0x0 14. "AR14,Add request" "0,1" newline bitfld.long 0x0 13. "AR13,Add request" "0,1" bitfld.long 0x0 12. "AR12,Add request" "0,1" bitfld.long 0x0 11. "AR11,Add request" "0,1" newline bitfld.long 0x0 10. "AR10,Add request" "0,1" bitfld.long 0x0 9. "AR9,Add request" "0,1" bitfld.long 0x0 8. "AR8,Add request" "0,1" newline bitfld.long 0x0 7. "AR7,Add request" "0,1" bitfld.long 0x0 6. "AR6,Add request" "0,1" bitfld.long 0x0 5. "AR5,Add request" "0,1" newline bitfld.long 0x0 4. "AR4,Add request" "0,1" bitfld.long 0x0 3. "AR3,Add request" "0,1" bitfld.long 0x0 2. "AR2,Add request" "0,1" newline bitfld.long 0x0 1. "AR1,Add request" "0,1" bitfld.long 0x0 0. "AR0,Add request" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions" bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1" rgroup.long 0xE0++0x13 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" rgroup.long 0xF8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field" tree.end tree "MCAN10_ECC_AGGR (MCAN10_ECC_AGGR)" base ad:0x2A42000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCAN10_MSGMEM_RAM (MCAN10_MSGMEM_RAM)" base ad:0x27A8000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCAN10_SS (MCAN10_SS)" base ad:0x27A0000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0: Honor Debug Suspend,1: Disregard debug suspend" rgroup.long 0x8++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS" bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1" newline bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" rgroup.long 0xC++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1" rgroup.long 0x10++0xB line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits." bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1" line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1" line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" rgroup.long 0x24++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1" rgroup.long 0x28++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt" tree.end tree "MCAN11_CFG (MCAN11_CFG)" base ad:0x27B1000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" rgroup.long 0x8++0x37 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point" newline hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection" rbitfld.long 0x8 7. "RX,Receive Pin" "0,1" bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM" hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration" bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1" bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1" bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1" newline bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0x10 0. "INIT,Initialization" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing" hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter" hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter" hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x4B line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" newline bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable" bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)" bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field" line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address" line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field" line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" rgroup.long 0x98++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x0 31. "ND31,New Data" "0,1" bitfld.long 0x0 30. "ND30,New Data" "0,1" bitfld.long 0x0 29. "ND29,New Data" "0,1" newline bitfld.long 0x0 28. "ND28,New Data" "0,1" bitfld.long 0x0 27. "ND27,New Data" "0,1" bitfld.long 0x0 26. "ND26,New Data" "0,1" newline bitfld.long 0x0 25. "ND25,New Data" "0,1" bitfld.long 0x0 24. "ND24,New Data" "0,1" bitfld.long 0x0 23. "ND23,New Data" "0,1" newline bitfld.long 0x0 22. "ND22,New Data" "0,1" bitfld.long 0x0 21. "ND21,New Data" "0,1" bitfld.long 0x0 20. "ND20,New Data" "0,1" newline bitfld.long 0x0 19. "ND19,New Data" "0,1" bitfld.long 0x0 18. "ND18,New Data" "0,1" bitfld.long 0x0 17. "ND17,New Data" "0,1" newline bitfld.long 0x0 16. "ND16,New Data" "0,1" bitfld.long 0x0 15. "ND15,New Data" "0,1" bitfld.long 0x0 14. "ND14,New Data" "0,1" newline bitfld.long 0x0 13. "ND13,New Data" "0,1" bitfld.long 0x0 12. "ND12,New Data" "0,1" bitfld.long 0x0 11. "ND11,New Data" "0,1" newline bitfld.long 0x0 10. "ND10,New Data" "0,1" bitfld.long 0x0 9. "ND9,New Data" "0,1" bitfld.long 0x0 8. "ND8,New Data" "0,1" newline bitfld.long 0x0 7. "ND7,New Data" "0,1" bitfld.long 0x0 6. "ND6,New Data" "0,1" bitfld.long 0x0 5. "ND5,New Data" "0,1" newline bitfld.long 0x0 4. "ND4,New Data" "0,1" bitfld.long 0x0 3. "ND3,New Data" "0,1" bitfld.long 0x0 2. "ND2,New Data" "0,1" newline bitfld.long 0x0 1. "ND1,New Data" "0,1" bitfld.long 0x0 0. "ND0,New Data" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x4 31. "ND63,New Data" "0,1" bitfld.long 0x4 30. "ND62,New Data" "0,1" bitfld.long 0x4 29. "ND61,New Data" "0,1" newline bitfld.long 0x4 28. "ND60,New Data" "0,1" bitfld.long 0x4 27. "ND59,New Data" "0,1" bitfld.long 0x4 26. "ND58,New Data" "0,1" newline bitfld.long 0x4 25. "ND57,New Data" "0,1" bitfld.long 0x4 24. "ND56,New Data" "0,1" bitfld.long 0x4 23. "ND55,New Data" "0,1" newline bitfld.long 0x4 22. "ND54,New Data" "0,1" bitfld.long 0x4 21. "ND53,New Data" "0,1" bitfld.long 0x4 20. "ND52,New Data" "0,1" newline bitfld.long 0x4 19. "ND51,New Data" "0,1" bitfld.long 0x4 18. "ND50,New Data" "0,1" bitfld.long 0x4 17. "ND49,New Data" "0,1" newline bitfld.long 0x4 16. "ND48,New Data" "0,1" bitfld.long 0x4 15. "ND47,New Data" "0,1" bitfld.long 0x4 14. "ND46,New Data" "0,1" newline bitfld.long 0x4 13. "ND45,New Data" "0,1" bitfld.long 0x4 12. "ND44,New Data" "0,1" bitfld.long 0x4 11. "ND43,New Data" "0,1" newline bitfld.long 0x4 10. "ND42,New Data" "0,1" bitfld.long 0x4 9. "ND41,New Data" "0,1" bitfld.long 0x4 8. "ND40,New Data" "0,1" newline bitfld.long 0x4 7. "ND39,New Data" "0,1" bitfld.long 0x4 6. "ND38,New Data" "0,1" bitfld.long 0x4 5. "ND37,New Data" "0,1" newline bitfld.long 0x4 4. "ND36,New Data" "0,1" bitfld.long 0x4 3. "ND35,New Data" "0,1" bitfld.long 0x4 2. "ND34,New Data" "0,1" newline bitfld.long 0x4 1. "ND33,New Data" "0,1" bitfld.long 0x4 0. "ND32,New Data" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" rgroup.long 0xA8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" rgroup.long 0xB8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" rgroup.long 0xC8++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1" rgroup.long 0xD0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests" bitfld.long 0x0 31. "AR31,Add request" "0,1" bitfld.long 0x0 30. "AR30,Add request" "0,1" bitfld.long 0x0 29. "AR29,Add request" "0,1" newline bitfld.long 0x0 28. "AR28,Add request" "0,1" bitfld.long 0x0 27. "AR27,Add request" "0,1" bitfld.long 0x0 26. "AR26,Add request" "0,1" newline bitfld.long 0x0 25. "AR25,Add request" "0,1" bitfld.long 0x0 24. "AR24,Add request" "0,1" bitfld.long 0x0 23. "AR23,Add request" "0,1" newline bitfld.long 0x0 22. "AR22,Add request" "0,1" bitfld.long 0x0 21. "AR21,Add request" "0,1" bitfld.long 0x0 20. "AR20,Add request" "0,1" newline bitfld.long 0x0 19. "AR19,Add request" "0,1" bitfld.long 0x0 18. "AR18,Add request" "0,1" bitfld.long 0x0 17. "AR17,Add request" "0,1" newline bitfld.long 0x0 16. "AR16,Add request" "0,1" bitfld.long 0x0 15. "AR15,Add request" "0,1" bitfld.long 0x0 14. "AR14,Add request" "0,1" newline bitfld.long 0x0 13. "AR13,Add request" "0,1" bitfld.long 0x0 12. "AR12,Add request" "0,1" bitfld.long 0x0 11. "AR11,Add request" "0,1" newline bitfld.long 0x0 10. "AR10,Add request" "0,1" bitfld.long 0x0 9. "AR9,Add request" "0,1" bitfld.long 0x0 8. "AR8,Add request" "0,1" newline bitfld.long 0x0 7. "AR7,Add request" "0,1" bitfld.long 0x0 6. "AR6,Add request" "0,1" bitfld.long 0x0 5. "AR5,Add request" "0,1" newline bitfld.long 0x0 4. "AR4,Add request" "0,1" bitfld.long 0x0 3. "AR3,Add request" "0,1" bitfld.long 0x0 2. "AR2,Add request" "0,1" newline bitfld.long 0x0 1. "AR1,Add request" "0,1" bitfld.long 0x0 0. "AR0,Add request" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions" bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1" rgroup.long 0xE0++0x13 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" rgroup.long 0xF8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field" tree.end tree "MCAN11_ECC_AGGR (MCAN11_ECC_AGGR)" base ad:0x2A43000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCAN11_MSGMEM_RAM (MCAN11_MSGMEM_RAM)" base ad:0x27B8000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCAN11_SS (MCAN11_SS)" base ad:0x27B0000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0: Honor Debug Suspend,1: Disregard debug suspend" rgroup.long 0x8++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS" bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1" newline bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" rgroup.long 0xC++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1" rgroup.long 0x10++0xB line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits." bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1" line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1" line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" rgroup.long 0x24++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1" rgroup.long 0x28++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt" tree.end tree "MCAN12_CFG (MCAN12_CFG)" base ad:0x27C1000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" rgroup.long 0x8++0x37 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point" newline hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection" rbitfld.long 0x8 7. "RX,Receive Pin" "0,1" bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM" hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration" bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1" bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1" bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1" newline bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0x10 0. "INIT,Initialization" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing" hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter" hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter" hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x4B line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" newline bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable" bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)" bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field" line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address" line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field" line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" rgroup.long 0x98++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x0 31. "ND31,New Data" "0,1" bitfld.long 0x0 30. "ND30,New Data" "0,1" bitfld.long 0x0 29. "ND29,New Data" "0,1" newline bitfld.long 0x0 28. "ND28,New Data" "0,1" bitfld.long 0x0 27. "ND27,New Data" "0,1" bitfld.long 0x0 26. "ND26,New Data" "0,1" newline bitfld.long 0x0 25. "ND25,New Data" "0,1" bitfld.long 0x0 24. "ND24,New Data" "0,1" bitfld.long 0x0 23. "ND23,New Data" "0,1" newline bitfld.long 0x0 22. "ND22,New Data" "0,1" bitfld.long 0x0 21. "ND21,New Data" "0,1" bitfld.long 0x0 20. "ND20,New Data" "0,1" newline bitfld.long 0x0 19. "ND19,New Data" "0,1" bitfld.long 0x0 18. "ND18,New Data" "0,1" bitfld.long 0x0 17. "ND17,New Data" "0,1" newline bitfld.long 0x0 16. "ND16,New Data" "0,1" bitfld.long 0x0 15. "ND15,New Data" "0,1" bitfld.long 0x0 14. "ND14,New Data" "0,1" newline bitfld.long 0x0 13. "ND13,New Data" "0,1" bitfld.long 0x0 12. "ND12,New Data" "0,1" bitfld.long 0x0 11. "ND11,New Data" "0,1" newline bitfld.long 0x0 10. "ND10,New Data" "0,1" bitfld.long 0x0 9. "ND9,New Data" "0,1" bitfld.long 0x0 8. "ND8,New Data" "0,1" newline bitfld.long 0x0 7. "ND7,New Data" "0,1" bitfld.long 0x0 6. "ND6,New Data" "0,1" bitfld.long 0x0 5. "ND5,New Data" "0,1" newline bitfld.long 0x0 4. "ND4,New Data" "0,1" bitfld.long 0x0 3. "ND3,New Data" "0,1" bitfld.long 0x0 2. "ND2,New Data" "0,1" newline bitfld.long 0x0 1. "ND1,New Data" "0,1" bitfld.long 0x0 0. "ND0,New Data" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x4 31. "ND63,New Data" "0,1" bitfld.long 0x4 30. "ND62,New Data" "0,1" bitfld.long 0x4 29. "ND61,New Data" "0,1" newline bitfld.long 0x4 28. "ND60,New Data" "0,1" bitfld.long 0x4 27. "ND59,New Data" "0,1" bitfld.long 0x4 26. "ND58,New Data" "0,1" newline bitfld.long 0x4 25. "ND57,New Data" "0,1" bitfld.long 0x4 24. "ND56,New Data" "0,1" bitfld.long 0x4 23. "ND55,New Data" "0,1" newline bitfld.long 0x4 22. "ND54,New Data" "0,1" bitfld.long 0x4 21. "ND53,New Data" "0,1" bitfld.long 0x4 20. "ND52,New Data" "0,1" newline bitfld.long 0x4 19. "ND51,New Data" "0,1" bitfld.long 0x4 18. "ND50,New Data" "0,1" bitfld.long 0x4 17. "ND49,New Data" "0,1" newline bitfld.long 0x4 16. "ND48,New Data" "0,1" bitfld.long 0x4 15. "ND47,New Data" "0,1" bitfld.long 0x4 14. "ND46,New Data" "0,1" newline bitfld.long 0x4 13. "ND45,New Data" "0,1" bitfld.long 0x4 12. "ND44,New Data" "0,1" bitfld.long 0x4 11. "ND43,New Data" "0,1" newline bitfld.long 0x4 10. "ND42,New Data" "0,1" bitfld.long 0x4 9. "ND41,New Data" "0,1" bitfld.long 0x4 8. "ND40,New Data" "0,1" newline bitfld.long 0x4 7. "ND39,New Data" "0,1" bitfld.long 0x4 6. "ND38,New Data" "0,1" bitfld.long 0x4 5. "ND37,New Data" "0,1" newline bitfld.long 0x4 4. "ND36,New Data" "0,1" bitfld.long 0x4 3. "ND35,New Data" "0,1" bitfld.long 0x4 2. "ND34,New Data" "0,1" newline bitfld.long 0x4 1. "ND33,New Data" "0,1" bitfld.long 0x4 0. "ND32,New Data" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" rgroup.long 0xA8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" rgroup.long 0xB8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" rgroup.long 0xC8++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1" rgroup.long 0xD0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests" bitfld.long 0x0 31. "AR31,Add request" "0,1" bitfld.long 0x0 30. "AR30,Add request" "0,1" bitfld.long 0x0 29. "AR29,Add request" "0,1" newline bitfld.long 0x0 28. "AR28,Add request" "0,1" bitfld.long 0x0 27. "AR27,Add request" "0,1" bitfld.long 0x0 26. "AR26,Add request" "0,1" newline bitfld.long 0x0 25. "AR25,Add request" "0,1" bitfld.long 0x0 24. "AR24,Add request" "0,1" bitfld.long 0x0 23. "AR23,Add request" "0,1" newline bitfld.long 0x0 22. "AR22,Add request" "0,1" bitfld.long 0x0 21. "AR21,Add request" "0,1" bitfld.long 0x0 20. "AR20,Add request" "0,1" newline bitfld.long 0x0 19. "AR19,Add request" "0,1" bitfld.long 0x0 18. "AR18,Add request" "0,1" bitfld.long 0x0 17. "AR17,Add request" "0,1" newline bitfld.long 0x0 16. "AR16,Add request" "0,1" bitfld.long 0x0 15. "AR15,Add request" "0,1" bitfld.long 0x0 14. "AR14,Add request" "0,1" newline bitfld.long 0x0 13. "AR13,Add request" "0,1" bitfld.long 0x0 12. "AR12,Add request" "0,1" bitfld.long 0x0 11. "AR11,Add request" "0,1" newline bitfld.long 0x0 10. "AR10,Add request" "0,1" bitfld.long 0x0 9. "AR9,Add request" "0,1" bitfld.long 0x0 8. "AR8,Add request" "0,1" newline bitfld.long 0x0 7. "AR7,Add request" "0,1" bitfld.long 0x0 6. "AR6,Add request" "0,1" bitfld.long 0x0 5. "AR5,Add request" "0,1" newline bitfld.long 0x0 4. "AR4,Add request" "0,1" bitfld.long 0x0 3. "AR3,Add request" "0,1" bitfld.long 0x0 2. "AR2,Add request" "0,1" newline bitfld.long 0x0 1. "AR1,Add request" "0,1" bitfld.long 0x0 0. "AR0,Add request" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions" bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1" rgroup.long 0xE0++0x13 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" rgroup.long 0xF8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field" tree.end tree "MCAN12_ECC_AGGR (MCAN12_ECC_AGGR)" base ad:0x2A44000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCAN12_MSGMEM_RAM (MCAN12_MSGMEM_RAM)" base ad:0x27C8000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCAN12_SS (MCAN12_SS)" base ad:0x27C0000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0: Honor Debug Suspend,1: Disregard debug suspend" rgroup.long 0x8++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS" bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1" newline bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" rgroup.long 0xC++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1" rgroup.long 0x10++0xB line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits." bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1" line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1" line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" rgroup.long 0x24++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1" rgroup.long 0x28++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt" tree.end tree "MCAN13_CFG (MCAN13_CFG)" base ad:0x27D1000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" rgroup.long 0x8++0x37 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point" newline hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection" rbitfld.long 0x8 7. "RX,Receive Pin" "0,1" bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM" hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration" bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1" bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1" bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1" newline bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0x10 0. "INIT,Initialization" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing" hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter" hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter" hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x4B line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" newline bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable" bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)" bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field" line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address" line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field" line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" rgroup.long 0x98++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x0 31. "ND31,New Data" "0,1" bitfld.long 0x0 30. "ND30,New Data" "0,1" bitfld.long 0x0 29. "ND29,New Data" "0,1" newline bitfld.long 0x0 28. "ND28,New Data" "0,1" bitfld.long 0x0 27. "ND27,New Data" "0,1" bitfld.long 0x0 26. "ND26,New Data" "0,1" newline bitfld.long 0x0 25. "ND25,New Data" "0,1" bitfld.long 0x0 24. "ND24,New Data" "0,1" bitfld.long 0x0 23. "ND23,New Data" "0,1" newline bitfld.long 0x0 22. "ND22,New Data" "0,1" bitfld.long 0x0 21. "ND21,New Data" "0,1" bitfld.long 0x0 20. "ND20,New Data" "0,1" newline bitfld.long 0x0 19. "ND19,New Data" "0,1" bitfld.long 0x0 18. "ND18,New Data" "0,1" bitfld.long 0x0 17. "ND17,New Data" "0,1" newline bitfld.long 0x0 16. "ND16,New Data" "0,1" bitfld.long 0x0 15. "ND15,New Data" "0,1" bitfld.long 0x0 14. "ND14,New Data" "0,1" newline bitfld.long 0x0 13. "ND13,New Data" "0,1" bitfld.long 0x0 12. "ND12,New Data" "0,1" bitfld.long 0x0 11. "ND11,New Data" "0,1" newline bitfld.long 0x0 10. "ND10,New Data" "0,1" bitfld.long 0x0 9. "ND9,New Data" "0,1" bitfld.long 0x0 8. "ND8,New Data" "0,1" newline bitfld.long 0x0 7. "ND7,New Data" "0,1" bitfld.long 0x0 6. "ND6,New Data" "0,1" bitfld.long 0x0 5. "ND5,New Data" "0,1" newline bitfld.long 0x0 4. "ND4,New Data" "0,1" bitfld.long 0x0 3. "ND3,New Data" "0,1" bitfld.long 0x0 2. "ND2,New Data" "0,1" newline bitfld.long 0x0 1. "ND1,New Data" "0,1" bitfld.long 0x0 0. "ND0,New Data" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x4 31. "ND63,New Data" "0,1" bitfld.long 0x4 30. "ND62,New Data" "0,1" bitfld.long 0x4 29. "ND61,New Data" "0,1" newline bitfld.long 0x4 28. "ND60,New Data" "0,1" bitfld.long 0x4 27. "ND59,New Data" "0,1" bitfld.long 0x4 26. "ND58,New Data" "0,1" newline bitfld.long 0x4 25. "ND57,New Data" "0,1" bitfld.long 0x4 24. "ND56,New Data" "0,1" bitfld.long 0x4 23. "ND55,New Data" "0,1" newline bitfld.long 0x4 22. "ND54,New Data" "0,1" bitfld.long 0x4 21. "ND53,New Data" "0,1" bitfld.long 0x4 20. "ND52,New Data" "0,1" newline bitfld.long 0x4 19. "ND51,New Data" "0,1" bitfld.long 0x4 18. "ND50,New Data" "0,1" bitfld.long 0x4 17. "ND49,New Data" "0,1" newline bitfld.long 0x4 16. "ND48,New Data" "0,1" bitfld.long 0x4 15. "ND47,New Data" "0,1" bitfld.long 0x4 14. "ND46,New Data" "0,1" newline bitfld.long 0x4 13. "ND45,New Data" "0,1" bitfld.long 0x4 12. "ND44,New Data" "0,1" bitfld.long 0x4 11. "ND43,New Data" "0,1" newline bitfld.long 0x4 10. "ND42,New Data" "0,1" bitfld.long 0x4 9. "ND41,New Data" "0,1" bitfld.long 0x4 8. "ND40,New Data" "0,1" newline bitfld.long 0x4 7. "ND39,New Data" "0,1" bitfld.long 0x4 6. "ND38,New Data" "0,1" bitfld.long 0x4 5. "ND37,New Data" "0,1" newline bitfld.long 0x4 4. "ND36,New Data" "0,1" bitfld.long 0x4 3. "ND35,New Data" "0,1" bitfld.long 0x4 2. "ND34,New Data" "0,1" newline bitfld.long 0x4 1. "ND33,New Data" "0,1" bitfld.long 0x4 0. "ND32,New Data" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" rgroup.long 0xA8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" rgroup.long 0xB8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" rgroup.long 0xC8++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1" rgroup.long 0xD0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests" bitfld.long 0x0 31. "AR31,Add request" "0,1" bitfld.long 0x0 30. "AR30,Add request" "0,1" bitfld.long 0x0 29. "AR29,Add request" "0,1" newline bitfld.long 0x0 28. "AR28,Add request" "0,1" bitfld.long 0x0 27. "AR27,Add request" "0,1" bitfld.long 0x0 26. "AR26,Add request" "0,1" newline bitfld.long 0x0 25. "AR25,Add request" "0,1" bitfld.long 0x0 24. "AR24,Add request" "0,1" bitfld.long 0x0 23. "AR23,Add request" "0,1" newline bitfld.long 0x0 22. "AR22,Add request" "0,1" bitfld.long 0x0 21. "AR21,Add request" "0,1" bitfld.long 0x0 20. "AR20,Add request" "0,1" newline bitfld.long 0x0 19. "AR19,Add request" "0,1" bitfld.long 0x0 18. "AR18,Add request" "0,1" bitfld.long 0x0 17. "AR17,Add request" "0,1" newline bitfld.long 0x0 16. "AR16,Add request" "0,1" bitfld.long 0x0 15. "AR15,Add request" "0,1" bitfld.long 0x0 14. "AR14,Add request" "0,1" newline bitfld.long 0x0 13. "AR13,Add request" "0,1" bitfld.long 0x0 12. "AR12,Add request" "0,1" bitfld.long 0x0 11. "AR11,Add request" "0,1" newline bitfld.long 0x0 10. "AR10,Add request" "0,1" bitfld.long 0x0 9. "AR9,Add request" "0,1" bitfld.long 0x0 8. "AR8,Add request" "0,1" newline bitfld.long 0x0 7. "AR7,Add request" "0,1" bitfld.long 0x0 6. "AR6,Add request" "0,1" bitfld.long 0x0 5. "AR5,Add request" "0,1" newline bitfld.long 0x0 4. "AR4,Add request" "0,1" bitfld.long 0x0 3. "AR3,Add request" "0,1" bitfld.long 0x0 2. "AR2,Add request" "0,1" newline bitfld.long 0x0 1. "AR1,Add request" "0,1" bitfld.long 0x0 0. "AR0,Add request" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions" bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1" rgroup.long 0xE0++0x13 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" rgroup.long 0xF8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field" tree.end tree "MCAN13_ECC_AGGR (MCAN13_ECC_AGGR)" base ad:0x2A45000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCAN13_MSGMEM_RAM (MCAN13_MSGMEM_RAM)" base ad:0x27D8000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCAN13_SS (MCAN13_SS)" base ad:0x27D0000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0: Honor Debug Suspend,1: Disregard debug suspend" rgroup.long 0x8++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS" bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1" newline bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" rgroup.long 0xC++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1" rgroup.long 0x10++0xB line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits." bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1" line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1" line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" rgroup.long 0x24++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1" rgroup.long 0x28++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt" tree.end tree "MCAN14_CFG (MCAN14_CFG)" base ad:0x2681000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" rgroup.long 0x8++0x37 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point" newline hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection" rbitfld.long 0x8 7. "RX,Receive Pin" "0,1" bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM" hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration" bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1" bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1" bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1" newline bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0x10 0. "INIT,Initialization" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing" hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter" hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter" hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x4B line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" newline bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable" bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)" bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field" line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address" line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field" line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" rgroup.long 0x98++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x0 31. "ND31,New Data" "0,1" bitfld.long 0x0 30. "ND30,New Data" "0,1" bitfld.long 0x0 29. "ND29,New Data" "0,1" newline bitfld.long 0x0 28. "ND28,New Data" "0,1" bitfld.long 0x0 27. "ND27,New Data" "0,1" bitfld.long 0x0 26. "ND26,New Data" "0,1" newline bitfld.long 0x0 25. "ND25,New Data" "0,1" bitfld.long 0x0 24. "ND24,New Data" "0,1" bitfld.long 0x0 23. "ND23,New Data" "0,1" newline bitfld.long 0x0 22. "ND22,New Data" "0,1" bitfld.long 0x0 21. "ND21,New Data" "0,1" bitfld.long 0x0 20. "ND20,New Data" "0,1" newline bitfld.long 0x0 19. "ND19,New Data" "0,1" bitfld.long 0x0 18. "ND18,New Data" "0,1" bitfld.long 0x0 17. "ND17,New Data" "0,1" newline bitfld.long 0x0 16. "ND16,New Data" "0,1" bitfld.long 0x0 15. "ND15,New Data" "0,1" bitfld.long 0x0 14. "ND14,New Data" "0,1" newline bitfld.long 0x0 13. "ND13,New Data" "0,1" bitfld.long 0x0 12. "ND12,New Data" "0,1" bitfld.long 0x0 11. "ND11,New Data" "0,1" newline bitfld.long 0x0 10. "ND10,New Data" "0,1" bitfld.long 0x0 9. "ND9,New Data" "0,1" bitfld.long 0x0 8. "ND8,New Data" "0,1" newline bitfld.long 0x0 7. "ND7,New Data" "0,1" bitfld.long 0x0 6. "ND6,New Data" "0,1" bitfld.long 0x0 5. "ND5,New Data" "0,1" newline bitfld.long 0x0 4. "ND4,New Data" "0,1" bitfld.long 0x0 3. "ND3,New Data" "0,1" bitfld.long 0x0 2. "ND2,New Data" "0,1" newline bitfld.long 0x0 1. "ND1,New Data" "0,1" bitfld.long 0x0 0. "ND0,New Data" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x4 31. "ND63,New Data" "0,1" bitfld.long 0x4 30. "ND62,New Data" "0,1" bitfld.long 0x4 29. "ND61,New Data" "0,1" newline bitfld.long 0x4 28. "ND60,New Data" "0,1" bitfld.long 0x4 27. "ND59,New Data" "0,1" bitfld.long 0x4 26. "ND58,New Data" "0,1" newline bitfld.long 0x4 25. "ND57,New Data" "0,1" bitfld.long 0x4 24. "ND56,New Data" "0,1" bitfld.long 0x4 23. "ND55,New Data" "0,1" newline bitfld.long 0x4 22. "ND54,New Data" "0,1" bitfld.long 0x4 21. "ND53,New Data" "0,1" bitfld.long 0x4 20. "ND52,New Data" "0,1" newline bitfld.long 0x4 19. "ND51,New Data" "0,1" bitfld.long 0x4 18. "ND50,New Data" "0,1" bitfld.long 0x4 17. "ND49,New Data" "0,1" newline bitfld.long 0x4 16. "ND48,New Data" "0,1" bitfld.long 0x4 15. "ND47,New Data" "0,1" bitfld.long 0x4 14. "ND46,New Data" "0,1" newline bitfld.long 0x4 13. "ND45,New Data" "0,1" bitfld.long 0x4 12. "ND44,New Data" "0,1" bitfld.long 0x4 11. "ND43,New Data" "0,1" newline bitfld.long 0x4 10. "ND42,New Data" "0,1" bitfld.long 0x4 9. "ND41,New Data" "0,1" bitfld.long 0x4 8. "ND40,New Data" "0,1" newline bitfld.long 0x4 7. "ND39,New Data" "0,1" bitfld.long 0x4 6. "ND38,New Data" "0,1" bitfld.long 0x4 5. "ND37,New Data" "0,1" newline bitfld.long 0x4 4. "ND36,New Data" "0,1" bitfld.long 0x4 3. "ND35,New Data" "0,1" bitfld.long 0x4 2. "ND34,New Data" "0,1" newline bitfld.long 0x4 1. "ND33,New Data" "0,1" bitfld.long 0x4 0. "ND32,New Data" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" rgroup.long 0xA8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" rgroup.long 0xB8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" rgroup.long 0xC8++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1" rgroup.long 0xD0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests" bitfld.long 0x0 31. "AR31,Add request" "0,1" bitfld.long 0x0 30. "AR30,Add request" "0,1" bitfld.long 0x0 29. "AR29,Add request" "0,1" newline bitfld.long 0x0 28. "AR28,Add request" "0,1" bitfld.long 0x0 27. "AR27,Add request" "0,1" bitfld.long 0x0 26. "AR26,Add request" "0,1" newline bitfld.long 0x0 25. "AR25,Add request" "0,1" bitfld.long 0x0 24. "AR24,Add request" "0,1" bitfld.long 0x0 23. "AR23,Add request" "0,1" newline bitfld.long 0x0 22. "AR22,Add request" "0,1" bitfld.long 0x0 21. "AR21,Add request" "0,1" bitfld.long 0x0 20. "AR20,Add request" "0,1" newline bitfld.long 0x0 19. "AR19,Add request" "0,1" bitfld.long 0x0 18. "AR18,Add request" "0,1" bitfld.long 0x0 17. "AR17,Add request" "0,1" newline bitfld.long 0x0 16. "AR16,Add request" "0,1" bitfld.long 0x0 15. "AR15,Add request" "0,1" bitfld.long 0x0 14. "AR14,Add request" "0,1" newline bitfld.long 0x0 13. "AR13,Add request" "0,1" bitfld.long 0x0 12. "AR12,Add request" "0,1" bitfld.long 0x0 11. "AR11,Add request" "0,1" newline bitfld.long 0x0 10. "AR10,Add request" "0,1" bitfld.long 0x0 9. "AR9,Add request" "0,1" bitfld.long 0x0 8. "AR8,Add request" "0,1" newline bitfld.long 0x0 7. "AR7,Add request" "0,1" bitfld.long 0x0 6. "AR6,Add request" "0,1" bitfld.long 0x0 5. "AR5,Add request" "0,1" newline bitfld.long 0x0 4. "AR4,Add request" "0,1" bitfld.long 0x0 3. "AR3,Add request" "0,1" bitfld.long 0x0 2. "AR2,Add request" "0,1" newline bitfld.long 0x0 1. "AR1,Add request" "0,1" bitfld.long 0x0 0. "AR0,Add request" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions" bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1" rgroup.long 0xE0++0x13 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" rgroup.long 0xF8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field" tree.end tree "MCAN14_ECC_AGGR (MCAN14_ECC_AGGR)" base ad:0x2A46000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCAN14_MSGMEM_RAM (MCAN14_MSGMEM_RAM)" base ad:0x2688000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCAN14_SS (MCAN14_SS)" base ad:0x2680000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0: Honor Debug Suspend,1: Disregard debug suspend" rgroup.long 0x8++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS" bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1" newline bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" rgroup.long 0xC++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1" rgroup.long 0x10++0xB line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits." bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1" line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1" line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" rgroup.long 0x24++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1" rgroup.long 0x28++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt" tree.end tree "MCAN15_CFG (MCAN15_CFG)" base ad:0x2691000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" rgroup.long 0x8++0x37 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point" newline hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection" rbitfld.long 0x8 7. "RX,Receive Pin" "0,1" bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM" hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration" bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1" bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1" bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1" newline bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0x10 0. "INIT,Initialization" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing" hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter" hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter" hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x4B line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" newline bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable" bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)" bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field" line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address" line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field" line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" rgroup.long 0x98++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x0 31. "ND31,New Data" "0,1" bitfld.long 0x0 30. "ND30,New Data" "0,1" bitfld.long 0x0 29. "ND29,New Data" "0,1" newline bitfld.long 0x0 28. "ND28,New Data" "0,1" bitfld.long 0x0 27. "ND27,New Data" "0,1" bitfld.long 0x0 26. "ND26,New Data" "0,1" newline bitfld.long 0x0 25. "ND25,New Data" "0,1" bitfld.long 0x0 24. "ND24,New Data" "0,1" bitfld.long 0x0 23. "ND23,New Data" "0,1" newline bitfld.long 0x0 22. "ND22,New Data" "0,1" bitfld.long 0x0 21. "ND21,New Data" "0,1" bitfld.long 0x0 20. "ND20,New Data" "0,1" newline bitfld.long 0x0 19. "ND19,New Data" "0,1" bitfld.long 0x0 18. "ND18,New Data" "0,1" bitfld.long 0x0 17. "ND17,New Data" "0,1" newline bitfld.long 0x0 16. "ND16,New Data" "0,1" bitfld.long 0x0 15. "ND15,New Data" "0,1" bitfld.long 0x0 14. "ND14,New Data" "0,1" newline bitfld.long 0x0 13. "ND13,New Data" "0,1" bitfld.long 0x0 12. "ND12,New Data" "0,1" bitfld.long 0x0 11. "ND11,New Data" "0,1" newline bitfld.long 0x0 10. "ND10,New Data" "0,1" bitfld.long 0x0 9. "ND9,New Data" "0,1" bitfld.long 0x0 8. "ND8,New Data" "0,1" newline bitfld.long 0x0 7. "ND7,New Data" "0,1" bitfld.long 0x0 6. "ND6,New Data" "0,1" bitfld.long 0x0 5. "ND5,New Data" "0,1" newline bitfld.long 0x0 4. "ND4,New Data" "0,1" bitfld.long 0x0 3. "ND3,New Data" "0,1" bitfld.long 0x0 2. "ND2,New Data" "0,1" newline bitfld.long 0x0 1. "ND1,New Data" "0,1" bitfld.long 0x0 0. "ND0,New Data" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x4 31. "ND63,New Data" "0,1" bitfld.long 0x4 30. "ND62,New Data" "0,1" bitfld.long 0x4 29. "ND61,New Data" "0,1" newline bitfld.long 0x4 28. "ND60,New Data" "0,1" bitfld.long 0x4 27. "ND59,New Data" "0,1" bitfld.long 0x4 26. "ND58,New Data" "0,1" newline bitfld.long 0x4 25. "ND57,New Data" "0,1" bitfld.long 0x4 24. "ND56,New Data" "0,1" bitfld.long 0x4 23. "ND55,New Data" "0,1" newline bitfld.long 0x4 22. "ND54,New Data" "0,1" bitfld.long 0x4 21. "ND53,New Data" "0,1" bitfld.long 0x4 20. "ND52,New Data" "0,1" newline bitfld.long 0x4 19. "ND51,New Data" "0,1" bitfld.long 0x4 18. "ND50,New Data" "0,1" bitfld.long 0x4 17. "ND49,New Data" "0,1" newline bitfld.long 0x4 16. "ND48,New Data" "0,1" bitfld.long 0x4 15. "ND47,New Data" "0,1" bitfld.long 0x4 14. "ND46,New Data" "0,1" newline bitfld.long 0x4 13. "ND45,New Data" "0,1" bitfld.long 0x4 12. "ND44,New Data" "0,1" bitfld.long 0x4 11. "ND43,New Data" "0,1" newline bitfld.long 0x4 10. "ND42,New Data" "0,1" bitfld.long 0x4 9. "ND41,New Data" "0,1" bitfld.long 0x4 8. "ND40,New Data" "0,1" newline bitfld.long 0x4 7. "ND39,New Data" "0,1" bitfld.long 0x4 6. "ND38,New Data" "0,1" bitfld.long 0x4 5. "ND37,New Data" "0,1" newline bitfld.long 0x4 4. "ND36,New Data" "0,1" bitfld.long 0x4 3. "ND35,New Data" "0,1" bitfld.long 0x4 2. "ND34,New Data" "0,1" newline bitfld.long 0x4 1. "ND33,New Data" "0,1" bitfld.long 0x4 0. "ND32,New Data" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" rgroup.long 0xA8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" rgroup.long 0xB8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" rgroup.long 0xC8++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1" rgroup.long 0xD0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests" bitfld.long 0x0 31. "AR31,Add request" "0,1" bitfld.long 0x0 30. "AR30,Add request" "0,1" bitfld.long 0x0 29. "AR29,Add request" "0,1" newline bitfld.long 0x0 28. "AR28,Add request" "0,1" bitfld.long 0x0 27. "AR27,Add request" "0,1" bitfld.long 0x0 26. "AR26,Add request" "0,1" newline bitfld.long 0x0 25. "AR25,Add request" "0,1" bitfld.long 0x0 24. "AR24,Add request" "0,1" bitfld.long 0x0 23. "AR23,Add request" "0,1" newline bitfld.long 0x0 22. "AR22,Add request" "0,1" bitfld.long 0x0 21. "AR21,Add request" "0,1" bitfld.long 0x0 20. "AR20,Add request" "0,1" newline bitfld.long 0x0 19. "AR19,Add request" "0,1" bitfld.long 0x0 18. "AR18,Add request" "0,1" bitfld.long 0x0 17. "AR17,Add request" "0,1" newline bitfld.long 0x0 16. "AR16,Add request" "0,1" bitfld.long 0x0 15. "AR15,Add request" "0,1" bitfld.long 0x0 14. "AR14,Add request" "0,1" newline bitfld.long 0x0 13. "AR13,Add request" "0,1" bitfld.long 0x0 12. "AR12,Add request" "0,1" bitfld.long 0x0 11. "AR11,Add request" "0,1" newline bitfld.long 0x0 10. "AR10,Add request" "0,1" bitfld.long 0x0 9. "AR9,Add request" "0,1" bitfld.long 0x0 8. "AR8,Add request" "0,1" newline bitfld.long 0x0 7. "AR7,Add request" "0,1" bitfld.long 0x0 6. "AR6,Add request" "0,1" bitfld.long 0x0 5. "AR5,Add request" "0,1" newline bitfld.long 0x0 4. "AR4,Add request" "0,1" bitfld.long 0x0 3. "AR3,Add request" "0,1" bitfld.long 0x0 2. "AR2,Add request" "0,1" newline bitfld.long 0x0 1. "AR1,Add request" "0,1" bitfld.long 0x0 0. "AR0,Add request" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions" bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1" rgroup.long 0xE0++0x13 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" rgroup.long 0xF8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field" tree.end tree "MCAN15_ECC_AGGR (MCAN15_ECC_AGGR)" base ad:0x2A47000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCAN15_MSGMEM_RAM (MCAN15_MSGMEM_RAM)" base ad:0x2698000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCAN15_SS (MCAN15_SS)" base ad:0x2690000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0: Honor Debug Suspend,1: Disregard debug suspend" rgroup.long 0x8++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS" bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1" newline bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" rgroup.long 0xC++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1" rgroup.long 0x10++0xB line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits." bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1" line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1" line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" rgroup.long 0x24++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1" rgroup.long 0x28++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt" tree.end tree "MCAN16_CFG (MCAN16_CFG)" base ad:0x26A1000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" rgroup.long 0x8++0x37 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point" newline hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection" rbitfld.long 0x8 7. "RX,Receive Pin" "0,1" bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM" hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration" bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1" bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1" bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1" newline bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0x10 0. "INIT,Initialization" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing" hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter" hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter" hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x4B line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" newline bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable" bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)" bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field" line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address" line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field" line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" rgroup.long 0x98++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x0 31. "ND31,New Data" "0,1" bitfld.long 0x0 30. "ND30,New Data" "0,1" bitfld.long 0x0 29. "ND29,New Data" "0,1" newline bitfld.long 0x0 28. "ND28,New Data" "0,1" bitfld.long 0x0 27. "ND27,New Data" "0,1" bitfld.long 0x0 26. "ND26,New Data" "0,1" newline bitfld.long 0x0 25. "ND25,New Data" "0,1" bitfld.long 0x0 24. "ND24,New Data" "0,1" bitfld.long 0x0 23. "ND23,New Data" "0,1" newline bitfld.long 0x0 22. "ND22,New Data" "0,1" bitfld.long 0x0 21. "ND21,New Data" "0,1" bitfld.long 0x0 20. "ND20,New Data" "0,1" newline bitfld.long 0x0 19. "ND19,New Data" "0,1" bitfld.long 0x0 18. "ND18,New Data" "0,1" bitfld.long 0x0 17. "ND17,New Data" "0,1" newline bitfld.long 0x0 16. "ND16,New Data" "0,1" bitfld.long 0x0 15. "ND15,New Data" "0,1" bitfld.long 0x0 14. "ND14,New Data" "0,1" newline bitfld.long 0x0 13. "ND13,New Data" "0,1" bitfld.long 0x0 12. "ND12,New Data" "0,1" bitfld.long 0x0 11. "ND11,New Data" "0,1" newline bitfld.long 0x0 10. "ND10,New Data" "0,1" bitfld.long 0x0 9. "ND9,New Data" "0,1" bitfld.long 0x0 8. "ND8,New Data" "0,1" newline bitfld.long 0x0 7. "ND7,New Data" "0,1" bitfld.long 0x0 6. "ND6,New Data" "0,1" bitfld.long 0x0 5. "ND5,New Data" "0,1" newline bitfld.long 0x0 4. "ND4,New Data" "0,1" bitfld.long 0x0 3. "ND3,New Data" "0,1" bitfld.long 0x0 2. "ND2,New Data" "0,1" newline bitfld.long 0x0 1. "ND1,New Data" "0,1" bitfld.long 0x0 0. "ND0,New Data" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x4 31. "ND63,New Data" "0,1" bitfld.long 0x4 30. "ND62,New Data" "0,1" bitfld.long 0x4 29. "ND61,New Data" "0,1" newline bitfld.long 0x4 28. "ND60,New Data" "0,1" bitfld.long 0x4 27. "ND59,New Data" "0,1" bitfld.long 0x4 26. "ND58,New Data" "0,1" newline bitfld.long 0x4 25. "ND57,New Data" "0,1" bitfld.long 0x4 24. "ND56,New Data" "0,1" bitfld.long 0x4 23. "ND55,New Data" "0,1" newline bitfld.long 0x4 22. "ND54,New Data" "0,1" bitfld.long 0x4 21. "ND53,New Data" "0,1" bitfld.long 0x4 20. "ND52,New Data" "0,1" newline bitfld.long 0x4 19. "ND51,New Data" "0,1" bitfld.long 0x4 18. "ND50,New Data" "0,1" bitfld.long 0x4 17. "ND49,New Data" "0,1" newline bitfld.long 0x4 16. "ND48,New Data" "0,1" bitfld.long 0x4 15. "ND47,New Data" "0,1" bitfld.long 0x4 14. "ND46,New Data" "0,1" newline bitfld.long 0x4 13. "ND45,New Data" "0,1" bitfld.long 0x4 12. "ND44,New Data" "0,1" bitfld.long 0x4 11. "ND43,New Data" "0,1" newline bitfld.long 0x4 10. "ND42,New Data" "0,1" bitfld.long 0x4 9. "ND41,New Data" "0,1" bitfld.long 0x4 8. "ND40,New Data" "0,1" newline bitfld.long 0x4 7. "ND39,New Data" "0,1" bitfld.long 0x4 6. "ND38,New Data" "0,1" bitfld.long 0x4 5. "ND37,New Data" "0,1" newline bitfld.long 0x4 4. "ND36,New Data" "0,1" bitfld.long 0x4 3. "ND35,New Data" "0,1" bitfld.long 0x4 2. "ND34,New Data" "0,1" newline bitfld.long 0x4 1. "ND33,New Data" "0,1" bitfld.long 0x4 0. "ND32,New Data" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" rgroup.long 0xA8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" rgroup.long 0xB8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" rgroup.long 0xC8++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1" rgroup.long 0xD0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests" bitfld.long 0x0 31. "AR31,Add request" "0,1" bitfld.long 0x0 30. "AR30,Add request" "0,1" bitfld.long 0x0 29. "AR29,Add request" "0,1" newline bitfld.long 0x0 28. "AR28,Add request" "0,1" bitfld.long 0x0 27. "AR27,Add request" "0,1" bitfld.long 0x0 26. "AR26,Add request" "0,1" newline bitfld.long 0x0 25. "AR25,Add request" "0,1" bitfld.long 0x0 24. "AR24,Add request" "0,1" bitfld.long 0x0 23. "AR23,Add request" "0,1" newline bitfld.long 0x0 22. "AR22,Add request" "0,1" bitfld.long 0x0 21. "AR21,Add request" "0,1" bitfld.long 0x0 20. "AR20,Add request" "0,1" newline bitfld.long 0x0 19. "AR19,Add request" "0,1" bitfld.long 0x0 18. "AR18,Add request" "0,1" bitfld.long 0x0 17. "AR17,Add request" "0,1" newline bitfld.long 0x0 16. "AR16,Add request" "0,1" bitfld.long 0x0 15. "AR15,Add request" "0,1" bitfld.long 0x0 14. "AR14,Add request" "0,1" newline bitfld.long 0x0 13. "AR13,Add request" "0,1" bitfld.long 0x0 12. "AR12,Add request" "0,1" bitfld.long 0x0 11. "AR11,Add request" "0,1" newline bitfld.long 0x0 10. "AR10,Add request" "0,1" bitfld.long 0x0 9. "AR9,Add request" "0,1" bitfld.long 0x0 8. "AR8,Add request" "0,1" newline bitfld.long 0x0 7. "AR7,Add request" "0,1" bitfld.long 0x0 6. "AR6,Add request" "0,1" bitfld.long 0x0 5. "AR5,Add request" "0,1" newline bitfld.long 0x0 4. "AR4,Add request" "0,1" bitfld.long 0x0 3. "AR3,Add request" "0,1" bitfld.long 0x0 2. "AR2,Add request" "0,1" newline bitfld.long 0x0 1. "AR1,Add request" "0,1" bitfld.long 0x0 0. "AR0,Add request" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions" bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1" rgroup.long 0xE0++0x13 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" rgroup.long 0xF8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field" tree.end tree "MCAN16_ECC_AGGR (MCAN16_ECC_AGGR)" base ad:0x2A48000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCAN16_MSGMEM_RAM (MCAN16_MSGMEM_RAM)" base ad:0x26A8000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCAN16_SS (MCAN16_SS)" base ad:0x26A0000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0: Honor Debug Suspend,1: Disregard debug suspend" rgroup.long 0x8++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS" bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1" newline bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" rgroup.long 0xC++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1" rgroup.long 0x10++0xB line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits." bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1" line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1" line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" rgroup.long 0x24++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1" rgroup.long 0x28++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt" tree.end tree "MCAN17_CFG (MCAN17_CFG)" base ad:0x26B1000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" rgroup.long 0x8++0x37 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point" newline hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection" rbitfld.long 0x8 7. "RX,Receive Pin" "0,1" bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM" hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration" bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1" bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1" bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1" newline bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0x10 0. "INIT,Initialization" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing" hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter" hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter" hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x4B line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" newline bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable" bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)" bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field" line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address" line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field" line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" rgroup.long 0x98++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x0 31. "ND31,New Data" "0,1" bitfld.long 0x0 30. "ND30,New Data" "0,1" bitfld.long 0x0 29. "ND29,New Data" "0,1" newline bitfld.long 0x0 28. "ND28,New Data" "0,1" bitfld.long 0x0 27. "ND27,New Data" "0,1" bitfld.long 0x0 26. "ND26,New Data" "0,1" newline bitfld.long 0x0 25. "ND25,New Data" "0,1" bitfld.long 0x0 24. "ND24,New Data" "0,1" bitfld.long 0x0 23. "ND23,New Data" "0,1" newline bitfld.long 0x0 22. "ND22,New Data" "0,1" bitfld.long 0x0 21. "ND21,New Data" "0,1" bitfld.long 0x0 20. "ND20,New Data" "0,1" newline bitfld.long 0x0 19. "ND19,New Data" "0,1" bitfld.long 0x0 18. "ND18,New Data" "0,1" bitfld.long 0x0 17. "ND17,New Data" "0,1" newline bitfld.long 0x0 16. "ND16,New Data" "0,1" bitfld.long 0x0 15. "ND15,New Data" "0,1" bitfld.long 0x0 14. "ND14,New Data" "0,1" newline bitfld.long 0x0 13. "ND13,New Data" "0,1" bitfld.long 0x0 12. "ND12,New Data" "0,1" bitfld.long 0x0 11. "ND11,New Data" "0,1" newline bitfld.long 0x0 10. "ND10,New Data" "0,1" bitfld.long 0x0 9. "ND9,New Data" "0,1" bitfld.long 0x0 8. "ND8,New Data" "0,1" newline bitfld.long 0x0 7. "ND7,New Data" "0,1" bitfld.long 0x0 6. "ND6,New Data" "0,1" bitfld.long 0x0 5. "ND5,New Data" "0,1" newline bitfld.long 0x0 4. "ND4,New Data" "0,1" bitfld.long 0x0 3. "ND3,New Data" "0,1" bitfld.long 0x0 2. "ND2,New Data" "0,1" newline bitfld.long 0x0 1. "ND1,New Data" "0,1" bitfld.long 0x0 0. "ND0,New Data" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x4 31. "ND63,New Data" "0,1" bitfld.long 0x4 30. "ND62,New Data" "0,1" bitfld.long 0x4 29. "ND61,New Data" "0,1" newline bitfld.long 0x4 28. "ND60,New Data" "0,1" bitfld.long 0x4 27. "ND59,New Data" "0,1" bitfld.long 0x4 26. "ND58,New Data" "0,1" newline bitfld.long 0x4 25. "ND57,New Data" "0,1" bitfld.long 0x4 24. "ND56,New Data" "0,1" bitfld.long 0x4 23. "ND55,New Data" "0,1" newline bitfld.long 0x4 22. "ND54,New Data" "0,1" bitfld.long 0x4 21. "ND53,New Data" "0,1" bitfld.long 0x4 20. "ND52,New Data" "0,1" newline bitfld.long 0x4 19. "ND51,New Data" "0,1" bitfld.long 0x4 18. "ND50,New Data" "0,1" bitfld.long 0x4 17. "ND49,New Data" "0,1" newline bitfld.long 0x4 16. "ND48,New Data" "0,1" bitfld.long 0x4 15. "ND47,New Data" "0,1" bitfld.long 0x4 14. "ND46,New Data" "0,1" newline bitfld.long 0x4 13. "ND45,New Data" "0,1" bitfld.long 0x4 12. "ND44,New Data" "0,1" bitfld.long 0x4 11. "ND43,New Data" "0,1" newline bitfld.long 0x4 10. "ND42,New Data" "0,1" bitfld.long 0x4 9. "ND41,New Data" "0,1" bitfld.long 0x4 8. "ND40,New Data" "0,1" newline bitfld.long 0x4 7. "ND39,New Data" "0,1" bitfld.long 0x4 6. "ND38,New Data" "0,1" bitfld.long 0x4 5. "ND37,New Data" "0,1" newline bitfld.long 0x4 4. "ND36,New Data" "0,1" bitfld.long 0x4 3. "ND35,New Data" "0,1" bitfld.long 0x4 2. "ND34,New Data" "0,1" newline bitfld.long 0x4 1. "ND33,New Data" "0,1" bitfld.long 0x4 0. "ND32,New Data" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" rgroup.long 0xA8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" rgroup.long 0xB8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" rgroup.long 0xC8++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1" rgroup.long 0xD0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests" bitfld.long 0x0 31. "AR31,Add request" "0,1" bitfld.long 0x0 30. "AR30,Add request" "0,1" bitfld.long 0x0 29. "AR29,Add request" "0,1" newline bitfld.long 0x0 28. "AR28,Add request" "0,1" bitfld.long 0x0 27. "AR27,Add request" "0,1" bitfld.long 0x0 26. "AR26,Add request" "0,1" newline bitfld.long 0x0 25. "AR25,Add request" "0,1" bitfld.long 0x0 24. "AR24,Add request" "0,1" bitfld.long 0x0 23. "AR23,Add request" "0,1" newline bitfld.long 0x0 22. "AR22,Add request" "0,1" bitfld.long 0x0 21. "AR21,Add request" "0,1" bitfld.long 0x0 20. "AR20,Add request" "0,1" newline bitfld.long 0x0 19. "AR19,Add request" "0,1" bitfld.long 0x0 18. "AR18,Add request" "0,1" bitfld.long 0x0 17. "AR17,Add request" "0,1" newline bitfld.long 0x0 16. "AR16,Add request" "0,1" bitfld.long 0x0 15. "AR15,Add request" "0,1" bitfld.long 0x0 14. "AR14,Add request" "0,1" newline bitfld.long 0x0 13. "AR13,Add request" "0,1" bitfld.long 0x0 12. "AR12,Add request" "0,1" bitfld.long 0x0 11. "AR11,Add request" "0,1" newline bitfld.long 0x0 10. "AR10,Add request" "0,1" bitfld.long 0x0 9. "AR9,Add request" "0,1" bitfld.long 0x0 8. "AR8,Add request" "0,1" newline bitfld.long 0x0 7. "AR7,Add request" "0,1" bitfld.long 0x0 6. "AR6,Add request" "0,1" bitfld.long 0x0 5. "AR5,Add request" "0,1" newline bitfld.long 0x0 4. "AR4,Add request" "0,1" bitfld.long 0x0 3. "AR3,Add request" "0,1" bitfld.long 0x0 2. "AR2,Add request" "0,1" newline bitfld.long 0x0 1. "AR1,Add request" "0,1" bitfld.long 0x0 0. "AR0,Add request" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions" bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1" rgroup.long 0xE0++0x13 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" rgroup.long 0xF8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field" tree.end tree "MCAN17_ECC_AGGR (MCAN17_ECC_AGGR)" base ad:0x2A49000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCAN17_MSGMEM_RAM (MCAN17_MSGMEM_RAM)" base ad:0x26B8000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCAN17_SS (MCAN17_SS)" base ad:0x26B0000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0: Honor Debug Suspend,1: Disregard debug suspend" rgroup.long 0x8++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS" bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1" newline bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" rgroup.long 0xC++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1" rgroup.long 0x10++0xB line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits." bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1" line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1" line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" rgroup.long 0x24++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1" rgroup.long 0x28++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt" tree.end tree.end tree "MCAN2" tree "MCAN2_CFG (MCAN2_CFG)" base ad:0x2721000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" rgroup.long 0x8++0x37 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point" newline hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection" rbitfld.long 0x8 7. "RX,Receive Pin" "0,1" bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM" hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration" bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1" bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1" bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1" newline bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0x10 0. "INIT,Initialization" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing" hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter" hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter" hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x4B line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" newline bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable" bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)" bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field" line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address" line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field" line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" rgroup.long 0x98++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x0 31. "ND31,New Data" "0,1" bitfld.long 0x0 30. "ND30,New Data" "0,1" bitfld.long 0x0 29. "ND29,New Data" "0,1" newline bitfld.long 0x0 28. "ND28,New Data" "0,1" bitfld.long 0x0 27. "ND27,New Data" "0,1" bitfld.long 0x0 26. "ND26,New Data" "0,1" newline bitfld.long 0x0 25. "ND25,New Data" "0,1" bitfld.long 0x0 24. "ND24,New Data" "0,1" bitfld.long 0x0 23. "ND23,New Data" "0,1" newline bitfld.long 0x0 22. "ND22,New Data" "0,1" bitfld.long 0x0 21. "ND21,New Data" "0,1" bitfld.long 0x0 20. "ND20,New Data" "0,1" newline bitfld.long 0x0 19. "ND19,New Data" "0,1" bitfld.long 0x0 18. "ND18,New Data" "0,1" bitfld.long 0x0 17. "ND17,New Data" "0,1" newline bitfld.long 0x0 16. "ND16,New Data" "0,1" bitfld.long 0x0 15. "ND15,New Data" "0,1" bitfld.long 0x0 14. "ND14,New Data" "0,1" newline bitfld.long 0x0 13. "ND13,New Data" "0,1" bitfld.long 0x0 12. "ND12,New Data" "0,1" bitfld.long 0x0 11. "ND11,New Data" "0,1" newline bitfld.long 0x0 10. "ND10,New Data" "0,1" bitfld.long 0x0 9. "ND9,New Data" "0,1" bitfld.long 0x0 8. "ND8,New Data" "0,1" newline bitfld.long 0x0 7. "ND7,New Data" "0,1" bitfld.long 0x0 6. "ND6,New Data" "0,1" bitfld.long 0x0 5. "ND5,New Data" "0,1" newline bitfld.long 0x0 4. "ND4,New Data" "0,1" bitfld.long 0x0 3. "ND3,New Data" "0,1" bitfld.long 0x0 2. "ND2,New Data" "0,1" newline bitfld.long 0x0 1. "ND1,New Data" "0,1" bitfld.long 0x0 0. "ND0,New Data" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x4 31. "ND63,New Data" "0,1" bitfld.long 0x4 30. "ND62,New Data" "0,1" bitfld.long 0x4 29. "ND61,New Data" "0,1" newline bitfld.long 0x4 28. "ND60,New Data" "0,1" bitfld.long 0x4 27. "ND59,New Data" "0,1" bitfld.long 0x4 26. "ND58,New Data" "0,1" newline bitfld.long 0x4 25. "ND57,New Data" "0,1" bitfld.long 0x4 24. "ND56,New Data" "0,1" bitfld.long 0x4 23. "ND55,New Data" "0,1" newline bitfld.long 0x4 22. "ND54,New Data" "0,1" bitfld.long 0x4 21. "ND53,New Data" "0,1" bitfld.long 0x4 20. "ND52,New Data" "0,1" newline bitfld.long 0x4 19. "ND51,New Data" "0,1" bitfld.long 0x4 18. "ND50,New Data" "0,1" bitfld.long 0x4 17. "ND49,New Data" "0,1" newline bitfld.long 0x4 16. "ND48,New Data" "0,1" bitfld.long 0x4 15. "ND47,New Data" "0,1" bitfld.long 0x4 14. "ND46,New Data" "0,1" newline bitfld.long 0x4 13. "ND45,New Data" "0,1" bitfld.long 0x4 12. "ND44,New Data" "0,1" bitfld.long 0x4 11. "ND43,New Data" "0,1" newline bitfld.long 0x4 10. "ND42,New Data" "0,1" bitfld.long 0x4 9. "ND41,New Data" "0,1" bitfld.long 0x4 8. "ND40,New Data" "0,1" newline bitfld.long 0x4 7. "ND39,New Data" "0,1" bitfld.long 0x4 6. "ND38,New Data" "0,1" bitfld.long 0x4 5. "ND37,New Data" "0,1" newline bitfld.long 0x4 4. "ND36,New Data" "0,1" bitfld.long 0x4 3. "ND35,New Data" "0,1" bitfld.long 0x4 2. "ND34,New Data" "0,1" newline bitfld.long 0x4 1. "ND33,New Data" "0,1" bitfld.long 0x4 0. "ND32,New Data" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" rgroup.long 0xA8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" rgroup.long 0xB8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" rgroup.long 0xC8++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1" rgroup.long 0xD0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests" bitfld.long 0x0 31. "AR31,Add request" "0,1" bitfld.long 0x0 30. "AR30,Add request" "0,1" bitfld.long 0x0 29. "AR29,Add request" "0,1" newline bitfld.long 0x0 28. "AR28,Add request" "0,1" bitfld.long 0x0 27. "AR27,Add request" "0,1" bitfld.long 0x0 26. "AR26,Add request" "0,1" newline bitfld.long 0x0 25. "AR25,Add request" "0,1" bitfld.long 0x0 24. "AR24,Add request" "0,1" bitfld.long 0x0 23. "AR23,Add request" "0,1" newline bitfld.long 0x0 22. "AR22,Add request" "0,1" bitfld.long 0x0 21. "AR21,Add request" "0,1" bitfld.long 0x0 20. "AR20,Add request" "0,1" newline bitfld.long 0x0 19. "AR19,Add request" "0,1" bitfld.long 0x0 18. "AR18,Add request" "0,1" bitfld.long 0x0 17. "AR17,Add request" "0,1" newline bitfld.long 0x0 16. "AR16,Add request" "0,1" bitfld.long 0x0 15. "AR15,Add request" "0,1" bitfld.long 0x0 14. "AR14,Add request" "0,1" newline bitfld.long 0x0 13. "AR13,Add request" "0,1" bitfld.long 0x0 12. "AR12,Add request" "0,1" bitfld.long 0x0 11. "AR11,Add request" "0,1" newline bitfld.long 0x0 10. "AR10,Add request" "0,1" bitfld.long 0x0 9. "AR9,Add request" "0,1" bitfld.long 0x0 8. "AR8,Add request" "0,1" newline bitfld.long 0x0 7. "AR7,Add request" "0,1" bitfld.long 0x0 6. "AR6,Add request" "0,1" bitfld.long 0x0 5. "AR5,Add request" "0,1" newline bitfld.long 0x0 4. "AR4,Add request" "0,1" bitfld.long 0x0 3. "AR3,Add request" "0,1" bitfld.long 0x0 2. "AR2,Add request" "0,1" newline bitfld.long 0x0 1. "AR1,Add request" "0,1" bitfld.long 0x0 0. "AR0,Add request" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions" bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1" rgroup.long 0xE0++0x13 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" rgroup.long 0xF8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field" tree.end tree "MCAN2_ECC_AGGR (MCAN2_ECC_AGGR)" base ad:0x2A7A000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCAN2_MSGMEM_RAM (MCAN2_MSGMEM_RAM)" base ad:0x2728000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCAN2_SS (MCAN2_SS)" base ad:0x2720000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0: Honor Debug Suspend,1: Disregard debug suspend" rgroup.long 0x8++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS" bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1" newline bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" rgroup.long 0xC++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1" rgroup.long 0x10++0xB line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits." bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1" line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1" line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" rgroup.long 0x24++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1" rgroup.long 0x28++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt" tree.end tree.end tree "MCAN3" tree "MCAN3_CFG (MCAN3_CFG)" base ad:0x2731000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" rgroup.long 0x8++0x37 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point" newline hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection" rbitfld.long 0x8 7. "RX,Receive Pin" "0,1" bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM" hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration" bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1" bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1" bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1" newline bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0x10 0. "INIT,Initialization" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing" hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter" hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter" hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x4B line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" newline bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable" bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)" bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field" line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address" line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field" line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" rgroup.long 0x98++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x0 31. "ND31,New Data" "0,1" bitfld.long 0x0 30. "ND30,New Data" "0,1" bitfld.long 0x0 29. "ND29,New Data" "0,1" newline bitfld.long 0x0 28. "ND28,New Data" "0,1" bitfld.long 0x0 27. "ND27,New Data" "0,1" bitfld.long 0x0 26. "ND26,New Data" "0,1" newline bitfld.long 0x0 25. "ND25,New Data" "0,1" bitfld.long 0x0 24. "ND24,New Data" "0,1" bitfld.long 0x0 23. "ND23,New Data" "0,1" newline bitfld.long 0x0 22. "ND22,New Data" "0,1" bitfld.long 0x0 21. "ND21,New Data" "0,1" bitfld.long 0x0 20. "ND20,New Data" "0,1" newline bitfld.long 0x0 19. "ND19,New Data" "0,1" bitfld.long 0x0 18. "ND18,New Data" "0,1" bitfld.long 0x0 17. "ND17,New Data" "0,1" newline bitfld.long 0x0 16. "ND16,New Data" "0,1" bitfld.long 0x0 15. "ND15,New Data" "0,1" bitfld.long 0x0 14. "ND14,New Data" "0,1" newline bitfld.long 0x0 13. "ND13,New Data" "0,1" bitfld.long 0x0 12. "ND12,New Data" "0,1" bitfld.long 0x0 11. "ND11,New Data" "0,1" newline bitfld.long 0x0 10. "ND10,New Data" "0,1" bitfld.long 0x0 9. "ND9,New Data" "0,1" bitfld.long 0x0 8. "ND8,New Data" "0,1" newline bitfld.long 0x0 7. "ND7,New Data" "0,1" bitfld.long 0x0 6. "ND6,New Data" "0,1" bitfld.long 0x0 5. "ND5,New Data" "0,1" newline bitfld.long 0x0 4. "ND4,New Data" "0,1" bitfld.long 0x0 3. "ND3,New Data" "0,1" bitfld.long 0x0 2. "ND2,New Data" "0,1" newline bitfld.long 0x0 1. "ND1,New Data" "0,1" bitfld.long 0x0 0. "ND0,New Data" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x4 31. "ND63,New Data" "0,1" bitfld.long 0x4 30. "ND62,New Data" "0,1" bitfld.long 0x4 29. "ND61,New Data" "0,1" newline bitfld.long 0x4 28. "ND60,New Data" "0,1" bitfld.long 0x4 27. "ND59,New Data" "0,1" bitfld.long 0x4 26. "ND58,New Data" "0,1" newline bitfld.long 0x4 25. "ND57,New Data" "0,1" bitfld.long 0x4 24. "ND56,New Data" "0,1" bitfld.long 0x4 23. "ND55,New Data" "0,1" newline bitfld.long 0x4 22. "ND54,New Data" "0,1" bitfld.long 0x4 21. "ND53,New Data" "0,1" bitfld.long 0x4 20. "ND52,New Data" "0,1" newline bitfld.long 0x4 19. "ND51,New Data" "0,1" bitfld.long 0x4 18. "ND50,New Data" "0,1" bitfld.long 0x4 17. "ND49,New Data" "0,1" newline bitfld.long 0x4 16. "ND48,New Data" "0,1" bitfld.long 0x4 15. "ND47,New Data" "0,1" bitfld.long 0x4 14. "ND46,New Data" "0,1" newline bitfld.long 0x4 13. "ND45,New Data" "0,1" bitfld.long 0x4 12. "ND44,New Data" "0,1" bitfld.long 0x4 11. "ND43,New Data" "0,1" newline bitfld.long 0x4 10. "ND42,New Data" "0,1" bitfld.long 0x4 9. "ND41,New Data" "0,1" bitfld.long 0x4 8. "ND40,New Data" "0,1" newline bitfld.long 0x4 7. "ND39,New Data" "0,1" bitfld.long 0x4 6. "ND38,New Data" "0,1" bitfld.long 0x4 5. "ND37,New Data" "0,1" newline bitfld.long 0x4 4. "ND36,New Data" "0,1" bitfld.long 0x4 3. "ND35,New Data" "0,1" bitfld.long 0x4 2. "ND34,New Data" "0,1" newline bitfld.long 0x4 1. "ND33,New Data" "0,1" bitfld.long 0x4 0. "ND32,New Data" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" rgroup.long 0xA8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" rgroup.long 0xB8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" rgroup.long 0xC8++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1" rgroup.long 0xD0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests" bitfld.long 0x0 31. "AR31,Add request" "0,1" bitfld.long 0x0 30. "AR30,Add request" "0,1" bitfld.long 0x0 29. "AR29,Add request" "0,1" newline bitfld.long 0x0 28. "AR28,Add request" "0,1" bitfld.long 0x0 27. "AR27,Add request" "0,1" bitfld.long 0x0 26. "AR26,Add request" "0,1" newline bitfld.long 0x0 25. "AR25,Add request" "0,1" bitfld.long 0x0 24. "AR24,Add request" "0,1" bitfld.long 0x0 23. "AR23,Add request" "0,1" newline bitfld.long 0x0 22. "AR22,Add request" "0,1" bitfld.long 0x0 21. "AR21,Add request" "0,1" bitfld.long 0x0 20. "AR20,Add request" "0,1" newline bitfld.long 0x0 19. "AR19,Add request" "0,1" bitfld.long 0x0 18. "AR18,Add request" "0,1" bitfld.long 0x0 17. "AR17,Add request" "0,1" newline bitfld.long 0x0 16. "AR16,Add request" "0,1" bitfld.long 0x0 15. "AR15,Add request" "0,1" bitfld.long 0x0 14. "AR14,Add request" "0,1" newline bitfld.long 0x0 13. "AR13,Add request" "0,1" bitfld.long 0x0 12. "AR12,Add request" "0,1" bitfld.long 0x0 11. "AR11,Add request" "0,1" newline bitfld.long 0x0 10. "AR10,Add request" "0,1" bitfld.long 0x0 9. "AR9,Add request" "0,1" bitfld.long 0x0 8. "AR8,Add request" "0,1" newline bitfld.long 0x0 7. "AR7,Add request" "0,1" bitfld.long 0x0 6. "AR6,Add request" "0,1" bitfld.long 0x0 5. "AR5,Add request" "0,1" newline bitfld.long 0x0 4. "AR4,Add request" "0,1" bitfld.long 0x0 3. "AR3,Add request" "0,1" bitfld.long 0x0 2. "AR2,Add request" "0,1" newline bitfld.long 0x0 1. "AR1,Add request" "0,1" bitfld.long 0x0 0. "AR0,Add request" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions" bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1" rgroup.long 0xE0++0x13 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" rgroup.long 0xF8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field" tree.end tree "MCAN3_ECC_AGGR (MCAN3_ECC_AGGR)" base ad:0x2A7B000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCAN3_MSGMEM_RAM (MCAN3_MSGMEM_RAM)" base ad:0x2738000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCAN3_SS (MCAN3_SS)" base ad:0x2730000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0: Honor Debug Suspend,1: Disregard debug suspend" rgroup.long 0x8++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS" bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1" newline bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" rgroup.long 0xC++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1" rgroup.long 0x10++0xB line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits." bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1" line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1" line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" rgroup.long 0x24++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1" rgroup.long 0x28++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt" tree.end tree.end tree "MCAN4" tree "MCAN4_CFG (MCAN4_CFG)" base ad:0x2741000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" rgroup.long 0x8++0x37 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point" newline hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection" rbitfld.long 0x8 7. "RX,Receive Pin" "0,1" bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM" hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration" bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1" bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1" bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1" newline bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0x10 0. "INIT,Initialization" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing" hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter" hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter" hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x4B line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" newline bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable" bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)" bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field" line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address" line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field" line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" rgroup.long 0x98++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x0 31. "ND31,New Data" "0,1" bitfld.long 0x0 30. "ND30,New Data" "0,1" bitfld.long 0x0 29. "ND29,New Data" "0,1" newline bitfld.long 0x0 28. "ND28,New Data" "0,1" bitfld.long 0x0 27. "ND27,New Data" "0,1" bitfld.long 0x0 26. "ND26,New Data" "0,1" newline bitfld.long 0x0 25. "ND25,New Data" "0,1" bitfld.long 0x0 24. "ND24,New Data" "0,1" bitfld.long 0x0 23. "ND23,New Data" "0,1" newline bitfld.long 0x0 22. "ND22,New Data" "0,1" bitfld.long 0x0 21. "ND21,New Data" "0,1" bitfld.long 0x0 20. "ND20,New Data" "0,1" newline bitfld.long 0x0 19. "ND19,New Data" "0,1" bitfld.long 0x0 18. "ND18,New Data" "0,1" bitfld.long 0x0 17. "ND17,New Data" "0,1" newline bitfld.long 0x0 16. "ND16,New Data" "0,1" bitfld.long 0x0 15. "ND15,New Data" "0,1" bitfld.long 0x0 14. "ND14,New Data" "0,1" newline bitfld.long 0x0 13. "ND13,New Data" "0,1" bitfld.long 0x0 12. "ND12,New Data" "0,1" bitfld.long 0x0 11. "ND11,New Data" "0,1" newline bitfld.long 0x0 10. "ND10,New Data" "0,1" bitfld.long 0x0 9. "ND9,New Data" "0,1" bitfld.long 0x0 8. "ND8,New Data" "0,1" newline bitfld.long 0x0 7. "ND7,New Data" "0,1" bitfld.long 0x0 6. "ND6,New Data" "0,1" bitfld.long 0x0 5. "ND5,New Data" "0,1" newline bitfld.long 0x0 4. "ND4,New Data" "0,1" bitfld.long 0x0 3. "ND3,New Data" "0,1" bitfld.long 0x0 2. "ND2,New Data" "0,1" newline bitfld.long 0x0 1. "ND1,New Data" "0,1" bitfld.long 0x0 0. "ND0,New Data" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x4 31. "ND63,New Data" "0,1" bitfld.long 0x4 30. "ND62,New Data" "0,1" bitfld.long 0x4 29. "ND61,New Data" "0,1" newline bitfld.long 0x4 28. "ND60,New Data" "0,1" bitfld.long 0x4 27. "ND59,New Data" "0,1" bitfld.long 0x4 26. "ND58,New Data" "0,1" newline bitfld.long 0x4 25. "ND57,New Data" "0,1" bitfld.long 0x4 24. "ND56,New Data" "0,1" bitfld.long 0x4 23. "ND55,New Data" "0,1" newline bitfld.long 0x4 22. "ND54,New Data" "0,1" bitfld.long 0x4 21. "ND53,New Data" "0,1" bitfld.long 0x4 20. "ND52,New Data" "0,1" newline bitfld.long 0x4 19. "ND51,New Data" "0,1" bitfld.long 0x4 18. "ND50,New Data" "0,1" bitfld.long 0x4 17. "ND49,New Data" "0,1" newline bitfld.long 0x4 16. "ND48,New Data" "0,1" bitfld.long 0x4 15. "ND47,New Data" "0,1" bitfld.long 0x4 14. "ND46,New Data" "0,1" newline bitfld.long 0x4 13. "ND45,New Data" "0,1" bitfld.long 0x4 12. "ND44,New Data" "0,1" bitfld.long 0x4 11. "ND43,New Data" "0,1" newline bitfld.long 0x4 10. "ND42,New Data" "0,1" bitfld.long 0x4 9. "ND41,New Data" "0,1" bitfld.long 0x4 8. "ND40,New Data" "0,1" newline bitfld.long 0x4 7. "ND39,New Data" "0,1" bitfld.long 0x4 6. "ND38,New Data" "0,1" bitfld.long 0x4 5. "ND37,New Data" "0,1" newline bitfld.long 0x4 4. "ND36,New Data" "0,1" bitfld.long 0x4 3. "ND35,New Data" "0,1" bitfld.long 0x4 2. "ND34,New Data" "0,1" newline bitfld.long 0x4 1. "ND33,New Data" "0,1" bitfld.long 0x4 0. "ND32,New Data" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" rgroup.long 0xA8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" rgroup.long 0xB8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" rgroup.long 0xC8++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1" rgroup.long 0xD0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests" bitfld.long 0x0 31. "AR31,Add request" "0,1" bitfld.long 0x0 30. "AR30,Add request" "0,1" bitfld.long 0x0 29. "AR29,Add request" "0,1" newline bitfld.long 0x0 28. "AR28,Add request" "0,1" bitfld.long 0x0 27. "AR27,Add request" "0,1" bitfld.long 0x0 26. "AR26,Add request" "0,1" newline bitfld.long 0x0 25. "AR25,Add request" "0,1" bitfld.long 0x0 24. "AR24,Add request" "0,1" bitfld.long 0x0 23. "AR23,Add request" "0,1" newline bitfld.long 0x0 22. "AR22,Add request" "0,1" bitfld.long 0x0 21. "AR21,Add request" "0,1" bitfld.long 0x0 20. "AR20,Add request" "0,1" newline bitfld.long 0x0 19. "AR19,Add request" "0,1" bitfld.long 0x0 18. "AR18,Add request" "0,1" bitfld.long 0x0 17. "AR17,Add request" "0,1" newline bitfld.long 0x0 16. "AR16,Add request" "0,1" bitfld.long 0x0 15. "AR15,Add request" "0,1" bitfld.long 0x0 14. "AR14,Add request" "0,1" newline bitfld.long 0x0 13. "AR13,Add request" "0,1" bitfld.long 0x0 12. "AR12,Add request" "0,1" bitfld.long 0x0 11. "AR11,Add request" "0,1" newline bitfld.long 0x0 10. "AR10,Add request" "0,1" bitfld.long 0x0 9. "AR9,Add request" "0,1" bitfld.long 0x0 8. "AR8,Add request" "0,1" newline bitfld.long 0x0 7. "AR7,Add request" "0,1" bitfld.long 0x0 6. "AR6,Add request" "0,1" bitfld.long 0x0 5. "AR5,Add request" "0,1" newline bitfld.long 0x0 4. "AR4,Add request" "0,1" bitfld.long 0x0 3. "AR3,Add request" "0,1" bitfld.long 0x0 2. "AR2,Add request" "0,1" newline bitfld.long 0x0 1. "AR1,Add request" "0,1" bitfld.long 0x0 0. "AR0,Add request" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions" bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1" rgroup.long 0xE0++0x13 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" rgroup.long 0xF8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field" tree.end tree "MCAN4_ECC_AGGR (MCAN4_ECC_AGGR)" base ad:0x2A7C000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCAN4_MSGMEM_RAM (MCAN4_MSGMEM_RAM)" base ad:0x2748000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCAN4_SS (MCAN4_SS)" base ad:0x2740000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0: Honor Debug Suspend,1: Disregard debug suspend" rgroup.long 0x8++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS" bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1" newline bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" rgroup.long 0xC++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1" rgroup.long 0x10++0xB line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits." bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1" line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1" line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" rgroup.long 0x24++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1" rgroup.long 0x28++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt" tree.end tree.end tree "MCAN5" tree "MCAN5_CFG (MCAN5_CFG)" base ad:0x2751000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" rgroup.long 0x8++0x37 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point" newline hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection" rbitfld.long 0x8 7. "RX,Receive Pin" "0,1" bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM" hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration" bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1" bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1" bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1" newline bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0x10 0. "INIT,Initialization" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing" hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter" hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter" hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x4B line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" newline bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable" bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)" bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field" line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address" line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field" line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" rgroup.long 0x98++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x0 31. "ND31,New Data" "0,1" bitfld.long 0x0 30. "ND30,New Data" "0,1" bitfld.long 0x0 29. "ND29,New Data" "0,1" newline bitfld.long 0x0 28. "ND28,New Data" "0,1" bitfld.long 0x0 27. "ND27,New Data" "0,1" bitfld.long 0x0 26. "ND26,New Data" "0,1" newline bitfld.long 0x0 25. "ND25,New Data" "0,1" bitfld.long 0x0 24. "ND24,New Data" "0,1" bitfld.long 0x0 23. "ND23,New Data" "0,1" newline bitfld.long 0x0 22. "ND22,New Data" "0,1" bitfld.long 0x0 21. "ND21,New Data" "0,1" bitfld.long 0x0 20. "ND20,New Data" "0,1" newline bitfld.long 0x0 19. "ND19,New Data" "0,1" bitfld.long 0x0 18. "ND18,New Data" "0,1" bitfld.long 0x0 17. "ND17,New Data" "0,1" newline bitfld.long 0x0 16. "ND16,New Data" "0,1" bitfld.long 0x0 15. "ND15,New Data" "0,1" bitfld.long 0x0 14. "ND14,New Data" "0,1" newline bitfld.long 0x0 13. "ND13,New Data" "0,1" bitfld.long 0x0 12. "ND12,New Data" "0,1" bitfld.long 0x0 11. "ND11,New Data" "0,1" newline bitfld.long 0x0 10. "ND10,New Data" "0,1" bitfld.long 0x0 9. "ND9,New Data" "0,1" bitfld.long 0x0 8. "ND8,New Data" "0,1" newline bitfld.long 0x0 7. "ND7,New Data" "0,1" bitfld.long 0x0 6. "ND6,New Data" "0,1" bitfld.long 0x0 5. "ND5,New Data" "0,1" newline bitfld.long 0x0 4. "ND4,New Data" "0,1" bitfld.long 0x0 3. "ND3,New Data" "0,1" bitfld.long 0x0 2. "ND2,New Data" "0,1" newline bitfld.long 0x0 1. "ND1,New Data" "0,1" bitfld.long 0x0 0. "ND0,New Data" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x4 31. "ND63,New Data" "0,1" bitfld.long 0x4 30. "ND62,New Data" "0,1" bitfld.long 0x4 29. "ND61,New Data" "0,1" newline bitfld.long 0x4 28. "ND60,New Data" "0,1" bitfld.long 0x4 27. "ND59,New Data" "0,1" bitfld.long 0x4 26. "ND58,New Data" "0,1" newline bitfld.long 0x4 25. "ND57,New Data" "0,1" bitfld.long 0x4 24. "ND56,New Data" "0,1" bitfld.long 0x4 23. "ND55,New Data" "0,1" newline bitfld.long 0x4 22. "ND54,New Data" "0,1" bitfld.long 0x4 21. "ND53,New Data" "0,1" bitfld.long 0x4 20. "ND52,New Data" "0,1" newline bitfld.long 0x4 19. "ND51,New Data" "0,1" bitfld.long 0x4 18. "ND50,New Data" "0,1" bitfld.long 0x4 17. "ND49,New Data" "0,1" newline bitfld.long 0x4 16. "ND48,New Data" "0,1" bitfld.long 0x4 15. "ND47,New Data" "0,1" bitfld.long 0x4 14. "ND46,New Data" "0,1" newline bitfld.long 0x4 13. "ND45,New Data" "0,1" bitfld.long 0x4 12. "ND44,New Data" "0,1" bitfld.long 0x4 11. "ND43,New Data" "0,1" newline bitfld.long 0x4 10. "ND42,New Data" "0,1" bitfld.long 0x4 9. "ND41,New Data" "0,1" bitfld.long 0x4 8. "ND40,New Data" "0,1" newline bitfld.long 0x4 7. "ND39,New Data" "0,1" bitfld.long 0x4 6. "ND38,New Data" "0,1" bitfld.long 0x4 5. "ND37,New Data" "0,1" newline bitfld.long 0x4 4. "ND36,New Data" "0,1" bitfld.long 0x4 3. "ND35,New Data" "0,1" bitfld.long 0x4 2. "ND34,New Data" "0,1" newline bitfld.long 0x4 1. "ND33,New Data" "0,1" bitfld.long 0x4 0. "ND32,New Data" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" rgroup.long 0xA8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" rgroup.long 0xB8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" rgroup.long 0xC8++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1" rgroup.long 0xD0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests" bitfld.long 0x0 31. "AR31,Add request" "0,1" bitfld.long 0x0 30. "AR30,Add request" "0,1" bitfld.long 0x0 29. "AR29,Add request" "0,1" newline bitfld.long 0x0 28. "AR28,Add request" "0,1" bitfld.long 0x0 27. "AR27,Add request" "0,1" bitfld.long 0x0 26. "AR26,Add request" "0,1" newline bitfld.long 0x0 25. "AR25,Add request" "0,1" bitfld.long 0x0 24. "AR24,Add request" "0,1" bitfld.long 0x0 23. "AR23,Add request" "0,1" newline bitfld.long 0x0 22. "AR22,Add request" "0,1" bitfld.long 0x0 21. "AR21,Add request" "0,1" bitfld.long 0x0 20. "AR20,Add request" "0,1" newline bitfld.long 0x0 19. "AR19,Add request" "0,1" bitfld.long 0x0 18. "AR18,Add request" "0,1" bitfld.long 0x0 17. "AR17,Add request" "0,1" newline bitfld.long 0x0 16. "AR16,Add request" "0,1" bitfld.long 0x0 15. "AR15,Add request" "0,1" bitfld.long 0x0 14. "AR14,Add request" "0,1" newline bitfld.long 0x0 13. "AR13,Add request" "0,1" bitfld.long 0x0 12. "AR12,Add request" "0,1" bitfld.long 0x0 11. "AR11,Add request" "0,1" newline bitfld.long 0x0 10. "AR10,Add request" "0,1" bitfld.long 0x0 9. "AR9,Add request" "0,1" bitfld.long 0x0 8. "AR8,Add request" "0,1" newline bitfld.long 0x0 7. "AR7,Add request" "0,1" bitfld.long 0x0 6. "AR6,Add request" "0,1" bitfld.long 0x0 5. "AR5,Add request" "0,1" newline bitfld.long 0x0 4. "AR4,Add request" "0,1" bitfld.long 0x0 3. "AR3,Add request" "0,1" bitfld.long 0x0 2. "AR2,Add request" "0,1" newline bitfld.long 0x0 1. "AR1,Add request" "0,1" bitfld.long 0x0 0. "AR0,Add request" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions" bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1" rgroup.long 0xE0++0x13 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" rgroup.long 0xF8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field" tree.end tree "MCAN5_ECC_AGGR (MCAN5_ECC_AGGR)" base ad:0x2A7D000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCAN5_MSGMEM_RAM (MCAN5_MSGMEM_RAM)" base ad:0x2758000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCAN5_SS (MCAN5_SS)" base ad:0x2750000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0: Honor Debug Suspend,1: Disregard debug suspend" rgroup.long 0x8++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS" bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1" newline bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" rgroup.long 0xC++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1" rgroup.long 0x10++0xB line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits." bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1" line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1" line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" rgroup.long 0x24++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1" rgroup.long 0x28++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt" tree.end tree.end tree "MCAN6" tree "MCAN6_CFG (MCAN6_CFG)" base ad:0x2761000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" rgroup.long 0x8++0x37 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point" newline hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection" rbitfld.long 0x8 7. "RX,Receive Pin" "0,1" bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM" hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration" bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1" bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1" bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1" newline bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0x10 0. "INIT,Initialization" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing" hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter" hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter" hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x4B line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" newline bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable" bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)" bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field" line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address" line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field" line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" rgroup.long 0x98++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x0 31. "ND31,New Data" "0,1" bitfld.long 0x0 30. "ND30,New Data" "0,1" bitfld.long 0x0 29. "ND29,New Data" "0,1" newline bitfld.long 0x0 28. "ND28,New Data" "0,1" bitfld.long 0x0 27. "ND27,New Data" "0,1" bitfld.long 0x0 26. "ND26,New Data" "0,1" newline bitfld.long 0x0 25. "ND25,New Data" "0,1" bitfld.long 0x0 24. "ND24,New Data" "0,1" bitfld.long 0x0 23. "ND23,New Data" "0,1" newline bitfld.long 0x0 22. "ND22,New Data" "0,1" bitfld.long 0x0 21. "ND21,New Data" "0,1" bitfld.long 0x0 20. "ND20,New Data" "0,1" newline bitfld.long 0x0 19. "ND19,New Data" "0,1" bitfld.long 0x0 18. "ND18,New Data" "0,1" bitfld.long 0x0 17. "ND17,New Data" "0,1" newline bitfld.long 0x0 16. "ND16,New Data" "0,1" bitfld.long 0x0 15. "ND15,New Data" "0,1" bitfld.long 0x0 14. "ND14,New Data" "0,1" newline bitfld.long 0x0 13. "ND13,New Data" "0,1" bitfld.long 0x0 12. "ND12,New Data" "0,1" bitfld.long 0x0 11. "ND11,New Data" "0,1" newline bitfld.long 0x0 10. "ND10,New Data" "0,1" bitfld.long 0x0 9. "ND9,New Data" "0,1" bitfld.long 0x0 8. "ND8,New Data" "0,1" newline bitfld.long 0x0 7. "ND7,New Data" "0,1" bitfld.long 0x0 6. "ND6,New Data" "0,1" bitfld.long 0x0 5. "ND5,New Data" "0,1" newline bitfld.long 0x0 4. "ND4,New Data" "0,1" bitfld.long 0x0 3. "ND3,New Data" "0,1" bitfld.long 0x0 2. "ND2,New Data" "0,1" newline bitfld.long 0x0 1. "ND1,New Data" "0,1" bitfld.long 0x0 0. "ND0,New Data" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x4 31. "ND63,New Data" "0,1" bitfld.long 0x4 30. "ND62,New Data" "0,1" bitfld.long 0x4 29. "ND61,New Data" "0,1" newline bitfld.long 0x4 28. "ND60,New Data" "0,1" bitfld.long 0x4 27. "ND59,New Data" "0,1" bitfld.long 0x4 26. "ND58,New Data" "0,1" newline bitfld.long 0x4 25. "ND57,New Data" "0,1" bitfld.long 0x4 24. "ND56,New Data" "0,1" bitfld.long 0x4 23. "ND55,New Data" "0,1" newline bitfld.long 0x4 22. "ND54,New Data" "0,1" bitfld.long 0x4 21. "ND53,New Data" "0,1" bitfld.long 0x4 20. "ND52,New Data" "0,1" newline bitfld.long 0x4 19. "ND51,New Data" "0,1" bitfld.long 0x4 18. "ND50,New Data" "0,1" bitfld.long 0x4 17. "ND49,New Data" "0,1" newline bitfld.long 0x4 16. "ND48,New Data" "0,1" bitfld.long 0x4 15. "ND47,New Data" "0,1" bitfld.long 0x4 14. "ND46,New Data" "0,1" newline bitfld.long 0x4 13. "ND45,New Data" "0,1" bitfld.long 0x4 12. "ND44,New Data" "0,1" bitfld.long 0x4 11. "ND43,New Data" "0,1" newline bitfld.long 0x4 10. "ND42,New Data" "0,1" bitfld.long 0x4 9. "ND41,New Data" "0,1" bitfld.long 0x4 8. "ND40,New Data" "0,1" newline bitfld.long 0x4 7. "ND39,New Data" "0,1" bitfld.long 0x4 6. "ND38,New Data" "0,1" bitfld.long 0x4 5. "ND37,New Data" "0,1" newline bitfld.long 0x4 4. "ND36,New Data" "0,1" bitfld.long 0x4 3. "ND35,New Data" "0,1" bitfld.long 0x4 2. "ND34,New Data" "0,1" newline bitfld.long 0x4 1. "ND33,New Data" "0,1" bitfld.long 0x4 0. "ND32,New Data" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" rgroup.long 0xA8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" rgroup.long 0xB8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" rgroup.long 0xC8++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1" rgroup.long 0xD0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests" bitfld.long 0x0 31. "AR31,Add request" "0,1" bitfld.long 0x0 30. "AR30,Add request" "0,1" bitfld.long 0x0 29. "AR29,Add request" "0,1" newline bitfld.long 0x0 28. "AR28,Add request" "0,1" bitfld.long 0x0 27. "AR27,Add request" "0,1" bitfld.long 0x0 26. "AR26,Add request" "0,1" newline bitfld.long 0x0 25. "AR25,Add request" "0,1" bitfld.long 0x0 24. "AR24,Add request" "0,1" bitfld.long 0x0 23. "AR23,Add request" "0,1" newline bitfld.long 0x0 22. "AR22,Add request" "0,1" bitfld.long 0x0 21. "AR21,Add request" "0,1" bitfld.long 0x0 20. "AR20,Add request" "0,1" newline bitfld.long 0x0 19. "AR19,Add request" "0,1" bitfld.long 0x0 18. "AR18,Add request" "0,1" bitfld.long 0x0 17. "AR17,Add request" "0,1" newline bitfld.long 0x0 16. "AR16,Add request" "0,1" bitfld.long 0x0 15. "AR15,Add request" "0,1" bitfld.long 0x0 14. "AR14,Add request" "0,1" newline bitfld.long 0x0 13. "AR13,Add request" "0,1" bitfld.long 0x0 12. "AR12,Add request" "0,1" bitfld.long 0x0 11. "AR11,Add request" "0,1" newline bitfld.long 0x0 10. "AR10,Add request" "0,1" bitfld.long 0x0 9. "AR9,Add request" "0,1" bitfld.long 0x0 8. "AR8,Add request" "0,1" newline bitfld.long 0x0 7. "AR7,Add request" "0,1" bitfld.long 0x0 6. "AR6,Add request" "0,1" bitfld.long 0x0 5. "AR5,Add request" "0,1" newline bitfld.long 0x0 4. "AR4,Add request" "0,1" bitfld.long 0x0 3. "AR3,Add request" "0,1" bitfld.long 0x0 2. "AR2,Add request" "0,1" newline bitfld.long 0x0 1. "AR1,Add request" "0,1" bitfld.long 0x0 0. "AR0,Add request" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions" bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1" rgroup.long 0xE0++0x13 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" rgroup.long 0xF8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field" tree.end tree "MCAN6_ECC_AGGR (MCAN6_ECC_AGGR)" base ad:0x2A7E000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCAN6_MSGMEM_RAM (MCAN6_MSGMEM_RAM)" base ad:0x2768000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCAN6_SS (MCAN6_SS)" base ad:0x2760000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0: Honor Debug Suspend,1: Disregard debug suspend" rgroup.long 0x8++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS" bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1" newline bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" rgroup.long 0xC++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1" rgroup.long 0x10++0xB line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits." bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1" line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1" line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" rgroup.long 0x24++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1" rgroup.long 0x28++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt" tree.end tree.end tree "MCAN7" tree "MCAN7_CFG (MCAN7_CFG)" base ad:0x2771000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" rgroup.long 0x8++0x37 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point" newline hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection" rbitfld.long 0x8 7. "RX,Receive Pin" "0,1" bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM" hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration" bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1" bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1" bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1" newline bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0x10 0. "INIT,Initialization" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing" hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter" hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter" hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x4B line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" newline bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable" bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)" bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field" line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address" line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field" line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" rgroup.long 0x98++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x0 31. "ND31,New Data" "0,1" bitfld.long 0x0 30. "ND30,New Data" "0,1" bitfld.long 0x0 29. "ND29,New Data" "0,1" newline bitfld.long 0x0 28. "ND28,New Data" "0,1" bitfld.long 0x0 27. "ND27,New Data" "0,1" bitfld.long 0x0 26. "ND26,New Data" "0,1" newline bitfld.long 0x0 25. "ND25,New Data" "0,1" bitfld.long 0x0 24. "ND24,New Data" "0,1" bitfld.long 0x0 23. "ND23,New Data" "0,1" newline bitfld.long 0x0 22. "ND22,New Data" "0,1" bitfld.long 0x0 21. "ND21,New Data" "0,1" bitfld.long 0x0 20. "ND20,New Data" "0,1" newline bitfld.long 0x0 19. "ND19,New Data" "0,1" bitfld.long 0x0 18. "ND18,New Data" "0,1" bitfld.long 0x0 17. "ND17,New Data" "0,1" newline bitfld.long 0x0 16. "ND16,New Data" "0,1" bitfld.long 0x0 15. "ND15,New Data" "0,1" bitfld.long 0x0 14. "ND14,New Data" "0,1" newline bitfld.long 0x0 13. "ND13,New Data" "0,1" bitfld.long 0x0 12. "ND12,New Data" "0,1" bitfld.long 0x0 11. "ND11,New Data" "0,1" newline bitfld.long 0x0 10. "ND10,New Data" "0,1" bitfld.long 0x0 9. "ND9,New Data" "0,1" bitfld.long 0x0 8. "ND8,New Data" "0,1" newline bitfld.long 0x0 7. "ND7,New Data" "0,1" bitfld.long 0x0 6. "ND6,New Data" "0,1" bitfld.long 0x0 5. "ND5,New Data" "0,1" newline bitfld.long 0x0 4. "ND4,New Data" "0,1" bitfld.long 0x0 3. "ND3,New Data" "0,1" bitfld.long 0x0 2. "ND2,New Data" "0,1" newline bitfld.long 0x0 1. "ND1,New Data" "0,1" bitfld.long 0x0 0. "ND0,New Data" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x4 31. "ND63,New Data" "0,1" bitfld.long 0x4 30. "ND62,New Data" "0,1" bitfld.long 0x4 29. "ND61,New Data" "0,1" newline bitfld.long 0x4 28. "ND60,New Data" "0,1" bitfld.long 0x4 27. "ND59,New Data" "0,1" bitfld.long 0x4 26. "ND58,New Data" "0,1" newline bitfld.long 0x4 25. "ND57,New Data" "0,1" bitfld.long 0x4 24. "ND56,New Data" "0,1" bitfld.long 0x4 23. "ND55,New Data" "0,1" newline bitfld.long 0x4 22. "ND54,New Data" "0,1" bitfld.long 0x4 21. "ND53,New Data" "0,1" bitfld.long 0x4 20. "ND52,New Data" "0,1" newline bitfld.long 0x4 19. "ND51,New Data" "0,1" bitfld.long 0x4 18. "ND50,New Data" "0,1" bitfld.long 0x4 17. "ND49,New Data" "0,1" newline bitfld.long 0x4 16. "ND48,New Data" "0,1" bitfld.long 0x4 15. "ND47,New Data" "0,1" bitfld.long 0x4 14. "ND46,New Data" "0,1" newline bitfld.long 0x4 13. "ND45,New Data" "0,1" bitfld.long 0x4 12. "ND44,New Data" "0,1" bitfld.long 0x4 11. "ND43,New Data" "0,1" newline bitfld.long 0x4 10. "ND42,New Data" "0,1" bitfld.long 0x4 9. "ND41,New Data" "0,1" bitfld.long 0x4 8. "ND40,New Data" "0,1" newline bitfld.long 0x4 7. "ND39,New Data" "0,1" bitfld.long 0x4 6. "ND38,New Data" "0,1" bitfld.long 0x4 5. "ND37,New Data" "0,1" newline bitfld.long 0x4 4. "ND36,New Data" "0,1" bitfld.long 0x4 3. "ND35,New Data" "0,1" bitfld.long 0x4 2. "ND34,New Data" "0,1" newline bitfld.long 0x4 1. "ND33,New Data" "0,1" bitfld.long 0x4 0. "ND32,New Data" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" rgroup.long 0xA8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" rgroup.long 0xB8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" rgroup.long 0xC8++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1" rgroup.long 0xD0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests" bitfld.long 0x0 31. "AR31,Add request" "0,1" bitfld.long 0x0 30. "AR30,Add request" "0,1" bitfld.long 0x0 29. "AR29,Add request" "0,1" newline bitfld.long 0x0 28. "AR28,Add request" "0,1" bitfld.long 0x0 27. "AR27,Add request" "0,1" bitfld.long 0x0 26. "AR26,Add request" "0,1" newline bitfld.long 0x0 25. "AR25,Add request" "0,1" bitfld.long 0x0 24. "AR24,Add request" "0,1" bitfld.long 0x0 23. "AR23,Add request" "0,1" newline bitfld.long 0x0 22. "AR22,Add request" "0,1" bitfld.long 0x0 21. "AR21,Add request" "0,1" bitfld.long 0x0 20. "AR20,Add request" "0,1" newline bitfld.long 0x0 19. "AR19,Add request" "0,1" bitfld.long 0x0 18. "AR18,Add request" "0,1" bitfld.long 0x0 17. "AR17,Add request" "0,1" newline bitfld.long 0x0 16. "AR16,Add request" "0,1" bitfld.long 0x0 15. "AR15,Add request" "0,1" bitfld.long 0x0 14. "AR14,Add request" "0,1" newline bitfld.long 0x0 13. "AR13,Add request" "0,1" bitfld.long 0x0 12. "AR12,Add request" "0,1" bitfld.long 0x0 11. "AR11,Add request" "0,1" newline bitfld.long 0x0 10. "AR10,Add request" "0,1" bitfld.long 0x0 9. "AR9,Add request" "0,1" bitfld.long 0x0 8. "AR8,Add request" "0,1" newline bitfld.long 0x0 7. "AR7,Add request" "0,1" bitfld.long 0x0 6. "AR6,Add request" "0,1" bitfld.long 0x0 5. "AR5,Add request" "0,1" newline bitfld.long 0x0 4. "AR4,Add request" "0,1" bitfld.long 0x0 3. "AR3,Add request" "0,1" bitfld.long 0x0 2. "AR2,Add request" "0,1" newline bitfld.long 0x0 1. "AR1,Add request" "0,1" bitfld.long 0x0 0. "AR0,Add request" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions" bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1" rgroup.long 0xE0++0x13 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" rgroup.long 0xF8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field" tree.end tree "MCAN7_ECC_AGGR (MCAN7_ECC_AGGR)" base ad:0x2A7F000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCAN7_MSGMEM_RAM (MCAN7_MSGMEM_RAM)" base ad:0x2778000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCAN7_SS (MCAN7_SS)" base ad:0x2770000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0: Honor Debug Suspend,1: Disregard debug suspend" rgroup.long 0x8++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS" bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1" newline bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" rgroup.long 0xC++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1" rgroup.long 0x10++0xB line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits." bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1" line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1" line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" rgroup.long 0x24++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1" rgroup.long 0x28++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt" tree.end tree.end tree "MCAN8" tree "MCAN8_CFG (MCAN8_CFG)" base ad:0x2781000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" rgroup.long 0x8++0x37 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point" newline hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection" rbitfld.long 0x8 7. "RX,Receive Pin" "0,1" bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM" hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration" bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1" bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1" bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1" newline bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0x10 0. "INIT,Initialization" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing" hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter" hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter" hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x4B line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" newline bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable" bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)" bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field" line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address" line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field" line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" rgroup.long 0x98++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x0 31. "ND31,New Data" "0,1" bitfld.long 0x0 30. "ND30,New Data" "0,1" bitfld.long 0x0 29. "ND29,New Data" "0,1" newline bitfld.long 0x0 28. "ND28,New Data" "0,1" bitfld.long 0x0 27. "ND27,New Data" "0,1" bitfld.long 0x0 26. "ND26,New Data" "0,1" newline bitfld.long 0x0 25. "ND25,New Data" "0,1" bitfld.long 0x0 24. "ND24,New Data" "0,1" bitfld.long 0x0 23. "ND23,New Data" "0,1" newline bitfld.long 0x0 22. "ND22,New Data" "0,1" bitfld.long 0x0 21. "ND21,New Data" "0,1" bitfld.long 0x0 20. "ND20,New Data" "0,1" newline bitfld.long 0x0 19. "ND19,New Data" "0,1" bitfld.long 0x0 18. "ND18,New Data" "0,1" bitfld.long 0x0 17. "ND17,New Data" "0,1" newline bitfld.long 0x0 16. "ND16,New Data" "0,1" bitfld.long 0x0 15. "ND15,New Data" "0,1" bitfld.long 0x0 14. "ND14,New Data" "0,1" newline bitfld.long 0x0 13. "ND13,New Data" "0,1" bitfld.long 0x0 12. "ND12,New Data" "0,1" bitfld.long 0x0 11. "ND11,New Data" "0,1" newline bitfld.long 0x0 10. "ND10,New Data" "0,1" bitfld.long 0x0 9. "ND9,New Data" "0,1" bitfld.long 0x0 8. "ND8,New Data" "0,1" newline bitfld.long 0x0 7. "ND7,New Data" "0,1" bitfld.long 0x0 6. "ND6,New Data" "0,1" bitfld.long 0x0 5. "ND5,New Data" "0,1" newline bitfld.long 0x0 4. "ND4,New Data" "0,1" bitfld.long 0x0 3. "ND3,New Data" "0,1" bitfld.long 0x0 2. "ND2,New Data" "0,1" newline bitfld.long 0x0 1. "ND1,New Data" "0,1" bitfld.long 0x0 0. "ND0,New Data" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x4 31. "ND63,New Data" "0,1" bitfld.long 0x4 30. "ND62,New Data" "0,1" bitfld.long 0x4 29. "ND61,New Data" "0,1" newline bitfld.long 0x4 28. "ND60,New Data" "0,1" bitfld.long 0x4 27. "ND59,New Data" "0,1" bitfld.long 0x4 26. "ND58,New Data" "0,1" newline bitfld.long 0x4 25. "ND57,New Data" "0,1" bitfld.long 0x4 24. "ND56,New Data" "0,1" bitfld.long 0x4 23. "ND55,New Data" "0,1" newline bitfld.long 0x4 22. "ND54,New Data" "0,1" bitfld.long 0x4 21. "ND53,New Data" "0,1" bitfld.long 0x4 20. "ND52,New Data" "0,1" newline bitfld.long 0x4 19. "ND51,New Data" "0,1" bitfld.long 0x4 18. "ND50,New Data" "0,1" bitfld.long 0x4 17. "ND49,New Data" "0,1" newline bitfld.long 0x4 16. "ND48,New Data" "0,1" bitfld.long 0x4 15. "ND47,New Data" "0,1" bitfld.long 0x4 14. "ND46,New Data" "0,1" newline bitfld.long 0x4 13. "ND45,New Data" "0,1" bitfld.long 0x4 12. "ND44,New Data" "0,1" bitfld.long 0x4 11. "ND43,New Data" "0,1" newline bitfld.long 0x4 10. "ND42,New Data" "0,1" bitfld.long 0x4 9. "ND41,New Data" "0,1" bitfld.long 0x4 8. "ND40,New Data" "0,1" newline bitfld.long 0x4 7. "ND39,New Data" "0,1" bitfld.long 0x4 6. "ND38,New Data" "0,1" bitfld.long 0x4 5. "ND37,New Data" "0,1" newline bitfld.long 0x4 4. "ND36,New Data" "0,1" bitfld.long 0x4 3. "ND35,New Data" "0,1" bitfld.long 0x4 2. "ND34,New Data" "0,1" newline bitfld.long 0x4 1. "ND33,New Data" "0,1" bitfld.long 0x4 0. "ND32,New Data" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" rgroup.long 0xA8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" rgroup.long 0xB8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" rgroup.long 0xC8++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1" rgroup.long 0xD0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests" bitfld.long 0x0 31. "AR31,Add request" "0,1" bitfld.long 0x0 30. "AR30,Add request" "0,1" bitfld.long 0x0 29. "AR29,Add request" "0,1" newline bitfld.long 0x0 28. "AR28,Add request" "0,1" bitfld.long 0x0 27. "AR27,Add request" "0,1" bitfld.long 0x0 26. "AR26,Add request" "0,1" newline bitfld.long 0x0 25. "AR25,Add request" "0,1" bitfld.long 0x0 24. "AR24,Add request" "0,1" bitfld.long 0x0 23. "AR23,Add request" "0,1" newline bitfld.long 0x0 22. "AR22,Add request" "0,1" bitfld.long 0x0 21. "AR21,Add request" "0,1" bitfld.long 0x0 20. "AR20,Add request" "0,1" newline bitfld.long 0x0 19. "AR19,Add request" "0,1" bitfld.long 0x0 18. "AR18,Add request" "0,1" bitfld.long 0x0 17. "AR17,Add request" "0,1" newline bitfld.long 0x0 16. "AR16,Add request" "0,1" bitfld.long 0x0 15. "AR15,Add request" "0,1" bitfld.long 0x0 14. "AR14,Add request" "0,1" newline bitfld.long 0x0 13. "AR13,Add request" "0,1" bitfld.long 0x0 12. "AR12,Add request" "0,1" bitfld.long 0x0 11. "AR11,Add request" "0,1" newline bitfld.long 0x0 10. "AR10,Add request" "0,1" bitfld.long 0x0 9. "AR9,Add request" "0,1" bitfld.long 0x0 8. "AR8,Add request" "0,1" newline bitfld.long 0x0 7. "AR7,Add request" "0,1" bitfld.long 0x0 6. "AR6,Add request" "0,1" bitfld.long 0x0 5. "AR5,Add request" "0,1" newline bitfld.long 0x0 4. "AR4,Add request" "0,1" bitfld.long 0x0 3. "AR3,Add request" "0,1" bitfld.long 0x0 2. "AR2,Add request" "0,1" newline bitfld.long 0x0 1. "AR1,Add request" "0,1" bitfld.long 0x0 0. "AR0,Add request" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions" bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1" rgroup.long 0xE0++0x13 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" rgroup.long 0xF8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field" tree.end tree "MCAN8_ECC_AGGR (MCAN8_ECC_AGGR)" base ad:0x2A40000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCAN8_MSGMEM_RAM (MCAN8_MSGMEM_RAM)" base ad:0x2788000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCAN8_SS (MCAN8_SS)" base ad:0x2780000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0: Honor Debug Suspend,1: Disregard debug suspend" rgroup.long 0x8++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS" bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1" newline bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" rgroup.long 0xC++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1" rgroup.long 0x10++0xB line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits." bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1" line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1" line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" rgroup.long 0x24++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1" rgroup.long 0x28++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt" tree.end tree.end tree "MCAN9" tree "MCAN9_CFG (MCAN9_CFG)" base ad:0x2791000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" rgroup.long 0x8++0x37 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point" newline hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection" rbitfld.long 0x8 7. "RX,Receive Pin" "0,1" bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM" hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration" bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1" bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1" bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1" newline bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0x10 0. "INIT,Initialization" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing" hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter" hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter" hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x4B line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" newline bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable" bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)" bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field" line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address" line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field" line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" rgroup.long 0x98++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x0 31. "ND31,New Data" "0,1" bitfld.long 0x0 30. "ND30,New Data" "0,1" bitfld.long 0x0 29. "ND29,New Data" "0,1" newline bitfld.long 0x0 28. "ND28,New Data" "0,1" bitfld.long 0x0 27. "ND27,New Data" "0,1" bitfld.long 0x0 26. "ND26,New Data" "0,1" newline bitfld.long 0x0 25. "ND25,New Data" "0,1" bitfld.long 0x0 24. "ND24,New Data" "0,1" bitfld.long 0x0 23. "ND23,New Data" "0,1" newline bitfld.long 0x0 22. "ND22,New Data" "0,1" bitfld.long 0x0 21. "ND21,New Data" "0,1" bitfld.long 0x0 20. "ND20,New Data" "0,1" newline bitfld.long 0x0 19. "ND19,New Data" "0,1" bitfld.long 0x0 18. "ND18,New Data" "0,1" bitfld.long 0x0 17. "ND17,New Data" "0,1" newline bitfld.long 0x0 16. "ND16,New Data" "0,1" bitfld.long 0x0 15. "ND15,New Data" "0,1" bitfld.long 0x0 14. "ND14,New Data" "0,1" newline bitfld.long 0x0 13. "ND13,New Data" "0,1" bitfld.long 0x0 12. "ND12,New Data" "0,1" bitfld.long 0x0 11. "ND11,New Data" "0,1" newline bitfld.long 0x0 10. "ND10,New Data" "0,1" bitfld.long 0x0 9. "ND9,New Data" "0,1" bitfld.long 0x0 8. "ND8,New Data" "0,1" newline bitfld.long 0x0 7. "ND7,New Data" "0,1" bitfld.long 0x0 6. "ND6,New Data" "0,1" bitfld.long 0x0 5. "ND5,New Data" "0,1" newline bitfld.long 0x0 4. "ND4,New Data" "0,1" bitfld.long 0x0 3. "ND3,New Data" "0,1" bitfld.long 0x0 2. "ND2,New Data" "0,1" newline bitfld.long 0x0 1. "ND1,New Data" "0,1" bitfld.long 0x0 0. "ND0,New Data" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x4 31. "ND63,New Data" "0,1" bitfld.long 0x4 30. "ND62,New Data" "0,1" bitfld.long 0x4 29. "ND61,New Data" "0,1" newline bitfld.long 0x4 28. "ND60,New Data" "0,1" bitfld.long 0x4 27. "ND59,New Data" "0,1" bitfld.long 0x4 26. "ND58,New Data" "0,1" newline bitfld.long 0x4 25. "ND57,New Data" "0,1" bitfld.long 0x4 24. "ND56,New Data" "0,1" bitfld.long 0x4 23. "ND55,New Data" "0,1" newline bitfld.long 0x4 22. "ND54,New Data" "0,1" bitfld.long 0x4 21. "ND53,New Data" "0,1" bitfld.long 0x4 20. "ND52,New Data" "0,1" newline bitfld.long 0x4 19. "ND51,New Data" "0,1" bitfld.long 0x4 18. "ND50,New Data" "0,1" bitfld.long 0x4 17. "ND49,New Data" "0,1" newline bitfld.long 0x4 16. "ND48,New Data" "0,1" bitfld.long 0x4 15. "ND47,New Data" "0,1" bitfld.long 0x4 14. "ND46,New Data" "0,1" newline bitfld.long 0x4 13. "ND45,New Data" "0,1" bitfld.long 0x4 12. "ND44,New Data" "0,1" bitfld.long 0x4 11. "ND43,New Data" "0,1" newline bitfld.long 0x4 10. "ND42,New Data" "0,1" bitfld.long 0x4 9. "ND41,New Data" "0,1" bitfld.long 0x4 8. "ND40,New Data" "0,1" newline bitfld.long 0x4 7. "ND39,New Data" "0,1" bitfld.long 0x4 6. "ND38,New Data" "0,1" bitfld.long 0x4 5. "ND37,New Data" "0,1" newline bitfld.long 0x4 4. "ND36,New Data" "0,1" bitfld.long 0x4 3. "ND35,New Data" "0,1" bitfld.long 0x4 2. "ND34,New Data" "0,1" newline bitfld.long 0x4 1. "ND33,New Data" "0,1" bitfld.long 0x4 0. "ND32,New Data" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" rgroup.long 0xA8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" rgroup.long 0xB8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" rgroup.long 0xC8++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1" rgroup.long 0xD0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests" bitfld.long 0x0 31. "AR31,Add request" "0,1" bitfld.long 0x0 30. "AR30,Add request" "0,1" bitfld.long 0x0 29. "AR29,Add request" "0,1" newline bitfld.long 0x0 28. "AR28,Add request" "0,1" bitfld.long 0x0 27. "AR27,Add request" "0,1" bitfld.long 0x0 26. "AR26,Add request" "0,1" newline bitfld.long 0x0 25. "AR25,Add request" "0,1" bitfld.long 0x0 24. "AR24,Add request" "0,1" bitfld.long 0x0 23. "AR23,Add request" "0,1" newline bitfld.long 0x0 22. "AR22,Add request" "0,1" bitfld.long 0x0 21. "AR21,Add request" "0,1" bitfld.long 0x0 20. "AR20,Add request" "0,1" newline bitfld.long 0x0 19. "AR19,Add request" "0,1" bitfld.long 0x0 18. "AR18,Add request" "0,1" bitfld.long 0x0 17. "AR17,Add request" "0,1" newline bitfld.long 0x0 16. "AR16,Add request" "0,1" bitfld.long 0x0 15. "AR15,Add request" "0,1" bitfld.long 0x0 14. "AR14,Add request" "0,1" newline bitfld.long 0x0 13. "AR13,Add request" "0,1" bitfld.long 0x0 12. "AR12,Add request" "0,1" bitfld.long 0x0 11. "AR11,Add request" "0,1" newline bitfld.long 0x0 10. "AR10,Add request" "0,1" bitfld.long 0x0 9. "AR9,Add request" "0,1" bitfld.long 0x0 8. "AR8,Add request" "0,1" newline bitfld.long 0x0 7. "AR7,Add request" "0,1" bitfld.long 0x0 6. "AR6,Add request" "0,1" bitfld.long 0x0 5. "AR5,Add request" "0,1" newline bitfld.long 0x0 4. "AR4,Add request" "0,1" bitfld.long 0x0 3. "AR3,Add request" "0,1" bitfld.long 0x0 2. "AR2,Add request" "0,1" newline bitfld.long 0x0 1. "AR1,Add request" "0,1" bitfld.long 0x0 0. "AR0,Add request" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions" bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1" rgroup.long 0xE0++0x13 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" rgroup.long 0xF8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field" tree.end tree "MCAN9_ECC_AGGR (MCAN9_ECC_AGGR)" base ad:0x2A41000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCAN9_MSGMEM_RAM (MCAN9_MSGMEM_RAM)" base ad:0x2798000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCAN9_SS (MCAN9_SS)" base ad:0x2790000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0: Honor Debug Suspend,1: Disregard debug suspend" rgroup.long 0x8++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS" bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1" newline bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" rgroup.long 0xC++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1" rgroup.long 0x10++0xB line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits." bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1" line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1" line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" rgroup.long 0x24++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1" rgroup.long 0x28++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt" tree.end tree.end tree.end tree "MCASP" base ad:0x0 tree "MCASP0_CFG (MCASP0_CFG)" base ad:0x2B00000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_PID,The revision identification register (PID) contains identification data for the peripheral." hexmask.long 0x0 0.--31. 1. "REV,Identifies revision of peripheral." rgroup.long 0x4++0x3 line.long 0x0 "CFG_PWRIDLESYSCONFIG," hexmask.long 0x0 6.--31. 1. "RESERVED66," hexmask.long.byte 0x0 2.--5. 1. "OTHER,Reserved for future programming." bitfld.long 0x0 0.--1. "IDLEMODE,Power management Configuration of the local target state management mode. By definition target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" rgroup.long 0x10++0x13 line.long 0x0 "CFG_PFUNC,The pin function register (PFUNC) specifies the function of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either a McASP pin or a general-purpose input/output (GPIO) pin. CAUTION: Writing a value other than 0 to reserved bits in.." bitfld.long 0x0 31. "AFSR,Determines if AFSR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 30. "AHCLKR,Determines if AHCLKR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 29. "ACLKR,Determines if ACLKR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 28. "AFSX,Determines if AFSX pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 27. "AHCLKX,Determines if AHCLKX pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 26. "ACLKX,Determines if ACLKX pin functions as McASP or GPIO." "0,1" newline bitfld.long 0x0 25. "AMUTE,Determines if AMUTE pin functions as McASP or GPIO." "0,1" hexmask.long.tbyte 0x0 4.--24. 1. "RESERVED67," hexmask.long.byte 0x0 0.--3. 1. "AXR,Determines if AXRn pin functions as McASP or GPIO." line.long 0x4 "CFG_PDIR,The pin direction register (PDIR) specifies the direction of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either an input or an output pin. Regardless of the pin function register (PFUNC) setting. each PDIR bit must be set to 1 for.." bitfld.long 0x4 31. "AFSR,Determines if AFSR pin functions as an input or output." "0,1" bitfld.long 0x4 30. "AHCLKR,Determines if AHCLKR pin functions as an input or output." "0,1" bitfld.long 0x4 29. "ACLKR,Determines if ACLKR pin functions as an input or output." "0,1" bitfld.long 0x4 28. "AFSX,Determines if AFSX pin functions as an input or output." "0,1" bitfld.long 0x4 27. "AHCLKX,Determines if AHCLKX pin functions as an input or output." "0,1" bitfld.long 0x4 26. "ACLKX,Determines if ACLKX pin functions as an input or output." "0,1" newline bitfld.long 0x4 25. "AMUTE,Determines if AMUTE pin functions as an input or output." "0,1" hexmask.long.tbyte 0x4 4.--24. 1. "RESERVED68," hexmask.long.byte 0x4 0.--3. 1. "AXR,Determines if AXRn pin functions as an input or output." line.long 0x8 "CFG_PDOUT,The pin data output register (PDOUT) holds a value for data out at all times. and may be read back at all times. The value held by PDOUT is not affected by writing to PDIR and PFUNC. However. the data value in PDOUT is driven out onto the McASP.." bitfld.long 0x8 31. "AFSR,Determines drive on AFSR output pin when the corresponding PFUNC[31] and PDIR[31] bits are set to 1." "0,1" bitfld.long 0x8 30. "AHCLKR,Determines drive on AHCLKR output pin when the corresponding PFUNC[30] and PDIR[30] bits are set to 1." "0,1" bitfld.long 0x8 29. "ACLKR,Determines drive on ACLKR output pin when the corresponding PFUNC[29] and PDIR[29] bits are set to 1." "0,1" bitfld.long 0x8 28. "AFSX,Determines drive on AFSX output pin when the corresponding PFUNC[28] and PDIR[28] bits are set to 1." "0,1" bitfld.long 0x8 27. "AHCLKX,Determines drive on AHCLKX output pin when the corresponding PFUNC[27] and PDIR[27] bits are set to 1." "0,1" bitfld.long 0x8 26. "ACLKX,Determines drive on ACLKX output pin when the corresponding PFUNC[26] and PDIR[26] bits are set to 1." "0,1" newline bitfld.long 0x8 25. "AMUTE,Determines drive on AMUTE output pin when the corresponding PFUNC[25] and PDIR[25] bits are set to 1." "0,1" hexmask.long.tbyte 0x8 4.--24. 1. "RESERVED69," hexmask.long.byte 0x8 0.--3. 1. "AXR,Determines drive on AXR[n] output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1." line.long 0xC "CFG_PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins. PDIN allows the actual value of the pin to be read. regardless of the state of PFUNC and PDIR. The value after reset for registers 1 through 15 and 24 through.." bitfld.long 0xC 31. "AFSR,Logic level on AFSR pin." "0,1" bitfld.long 0xC 30. "AHCLKR,Logic level on AHCLKR pin." "0,1" bitfld.long 0xC 29. "ACLKR,Logic level on ACLKR pin." "0,1" bitfld.long 0xC 28. "AFSX,Logic level on AFSX pin." "0,1" bitfld.long 0xC 27. "AHCLKX,Logic level on AHCLKX pin." "0,1" bitfld.long 0xC 26. "ACLKX,Logic level on ACLKX pin." "0,1" newline bitfld.long 0xC 25. "AMUTE,Logic level on AMUTE pin." "0,1" hexmask.long.tbyte 0xC 4.--24. 1. "RESERVED70," hexmask.long.byte 0xC 0.--3. 1. "AXR,Logic level on AXR[n] pin." line.long 0x10 "CFG_PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDCLR bit clears the corresponding bit in PDOUT and. if PFUNC = 1 (GPIO function) and PDIR = 1 (output). drives a logic.." bitfld.long 0x10 31. "AFSR,Allows the corresponding AFSR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 30. "AHCLKR,Allows the corresponding AHCLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 29. "ACLKR,Allows the corresponding ACLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 28. "AFSX,Allows the corresponding AFSX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 27. "AHCLKX,Allows the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 26. "ACLKX,Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" newline bitfld.long 0x10 25. "AMUTE,Allows the corresponding AMUTE bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" hexmask.long.tbyte 0x10 4.--24. 1. "RESERVED71," hexmask.long.byte 0x10 0.--3. 1. "AXR,Allows the corresponding AXR[n] bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." rgroup.long 0x44++0xF line.long 0x0 "CFG_GBLCTL,The global control register (GBLCTL) provides initialization of the transmit and receive sections. The bit fields in GBLCTL are synchronized and latched by the corresponding clocks (ACLKX for bits 12-8 and ACLKR for bits 4-0). Before GBLCTL is.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED73," bitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit." "0,1" bitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit." "0,1" bitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. By clearing then setting this bit the transmit buffer is flushed to an empty state [XDATA = 1]. If XSMRST = 1 XSRCLR = 1 XDATA = 1 and XBUF is not loaded with new data before the start of the next active.." "0,1" bitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit." "0,1" bitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED72," "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit." "0,1" bitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit." "0,1" bitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. By clearing then setting this bit the receive buffer is flushed." "0,1" bitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit." "0,1" bitfld.long 0x0 0. "RCLKRST,Receive high-frequency clock divider reset enable bit." "0,1" line.long 0x4 "CFG_AMUTE,The audio mute control register (AMUTE) controls the McASP audio mute (AMUTE) output pin. The value after reset for register 4 depends on how the pins are being driven." hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED74," bitfld.long 0x4 12. "XDMAERR,If transmit DMA error [XDMAERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 11. "RDMAERR,If receive DMA error [RDMAERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 10. "XCKFAIL,If transmit clock failure [XCKFAIL] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 9. "RCKFAIL,If receive clock failure [RCKFAIL] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 8. "XSYNCERR,If unexpected transmit frame sync error [XSYNCERR] drive AMUTE active enable bit." "0,1" newline bitfld.long 0x4 7. "RSYNCERR,If unexpected receive frame sync error [RSYNCERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 6. "XUNDRN,If transmit underrun error [XUNDRN] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 5. "ROVRN,If receiver overrun error [ROVRN] drive AMUTE active enable bit." "0,1" rbitfld.long 0x4 4. "INSTAT,Determines drive on AXRn pin when PFUNC[n] and PDIR[n] bits are set to 1." "0,1" bitfld.long 0x4 3. "INEN,Drive AMUTE active when AMUTEIN error is active [INSTAT = 1]." "0,1" bitfld.long 0x4 2. "INPOL,Audio mute in [AMUTEIN] polarity select bit." "0,1" newline bitfld.long 0x4 0.--1. "MUTEN,AMUTE pin enable bit [unless overridden by GPIO registers]." "0,1,2,3" line.long 0x8 "CFG_DLBCTL,The digital loopback control register (DLBCTL) controls the internal loopback settings of the McASP in TDM mode." hexmask.long 0x8 4.--31. 1. "RESERVED75," bitfld.long 0x8 2.--3. "MODE,Loopback generator mode bits. Applies only when loopback mode is enabled [DLBEN = 1]." "0,1,2,3" bitfld.long 0x8 1. "ORD,Loopback order bit when loopback mode is enabled [DLBEN = 1]." "0,1" bitfld.long 0x8 0. "DLBEN,Loopback mode enable bit." "0,1" line.long 0xC "CFG_DITCTL,The DIT mode control register (DITCTL) controls DIT operations of the McASP." hexmask.long 0xC 4.--31. 1. "RESERVED77," bitfld.long 0xC 3. "VB,Valid bit for odd time slots [DIT right subframe]." "0,1" bitfld.long 0xC 2. "VA,Valid bit for even time slots [DIT left subframe]." "0,1" rbitfld.long 0xC 1. "RESERVED76," "0,1" bitfld.long 0xC 0. "DITEN,DIT mode enable bit. DITEN should only be changed while the XSMRST bit in GBLCTL is in reset [and for startup XSRCLR also in reset]. However it is not necessary to reset the XCLKRST or XHCLKRST bits in GBLCTL to change DITEN." "0,1" rgroup.long 0x60++0x23 line.long 0x0 "CFG_RGBLCTL,Alias of the global control register (GBLCTL). Writing to the receiver global control register (RGBLCTL) affects only the receive bits of GBLCTL (bits 4-0). Reads from RGBLCTL return the value of GBLCTL. RGBLCTL allows the receiver to be.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED79," rbitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit. A read of this bit returns the XFRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit. A read of this bit returns the XSMRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. A read of this bit returns the XSRCLR bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit. A read of this bit returns the XHCLKRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit. A read of this bit returns the XCLKRST bit value of GBLCTL. Writes have no effect." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED78," "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit. A write to this bit affects the RFRST bit of GBLCTL." "0,1" bitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit. A write to this bit affects the RSMRST bit of GBLCTL." "0,1" bitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. A write to this bit affects the RSRCLR bit of GBLCTL." "0,1" bitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit. A write to this bit affects the RHCLKRST bit of GBLCTL." "0,1" bitfld.long 0x0 0. "RCLKRST,Receive clock divider reset enable bit. A write to this bit affects the RCLKRST bit of GBLCTL." "0,1" line.long 0x4 "CFG_RMASK,The receive format unit bit mask register (RMASK) determines which bits of the received data are masked off and padded with a known value before being read by the CPU or DMA." hexmask.long 0x4 0.--31. 1. "RMASK,Receive data mask n enable bit." line.long 0x8 "CFG_RFMT,The receive bit stream format register (RFMT) configures the receive data format." hexmask.long.word 0x8 18.--31. 1. "RESERVED80," bitfld.long 0x8 16.--17. "RDATDLY,Receive bit delay." "0,1,2,3" bitfld.long 0x8 15. "RRVRS,Receive serial bitstream order." "0,1" bitfld.long 0x8 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word. This field only applies to bits when RMASK[n] = 0." "0,1,2,3" hexmask.long.byte 0x8 8.--12. 1. "RPBIT,RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits. This field only applies when RPAD = 2h." hexmask.long.byte 0x8 4.--7. 1. "RSSZ,Receive slot size." newline bitfld.long 0x8 3. "RBUSEL,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port." "0,1" bitfld.long 0x8 0.--2. "RROT,Right-rotation value for receive rotate right format unit." "0,1,2,3,4,5,6,7" line.long 0xC "CFG_AFSRCTL,The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR)." hexmask.long.word 0xC 16.--31. 1. "RESERVED83," hexmask.long.word 0xC 7.--15. 1. "RMOD,Receive frame sync mode select bits. 1FFh = Reserved from 181h to 1FFh." rbitfld.long 0xC 5.--6. "RESERVED82," "0,1,2,3" bitfld.long 0xC 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period." "0,1" rbitfld.long 0xC 2.--3. "RESERVED81," "0,1,2,3" bitfld.long 0xC 1. "FSRM,Receive frame sync generation select bit." "0,1" newline bitfld.long 0xC 0. "FSRP,Receive frame sync polarity select bit." "0,1" line.long 0x10 "CFG_ACLKRCTL,The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive clock generator." hexmask.long.word 0x10 21.--31. 1. "RESERVED86," bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress" "0,1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress" "0,1" bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "0,1,2,3" hexmask.long.byte 0x10 8.--15. 1. "RESERVED85," newline bitfld.long 0x10 7. "CLKRP,Receive bitstream clock polarity select bit." "0,1" rbitfld.long 0x10 6. "RESERVED84," "0,1" bitfld.long 0x10 5. "CLKRM,Receive bit clock source bit. Note that this bit does not have any effect if ACLKXCTL.ASYNC = 0." "0,1" hexmask.long.byte 0x10 0.--4. 1. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR. Note that this bit does not have any effect if ACLKXCTL.ASYNC = 0." line.long 0x14 "CFG_AHCLKRCTL,The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency master clock (AHCLKR) and the receive clock generator." hexmask.long.word 0x14 21.--31. 1. "RESERVED88," bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "0,1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "0,1" bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "0,1,2,3" bitfld.long 0x14 15. "HCLKRM,Receive high-frequency clock source bit." "0,1" newline bitfld.long 0x14 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit." "0,1" rbitfld.long 0x14 12.--13. "RESERVED87," "0,1,2,3" hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR." line.long 0x18 "CFG_RTDM,The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active." hexmask.long 0x18 0.--31. 1. "RTDMS,Receiver mode during TDM time slot n." line.long 0x1C "CFG_RINTCTL,The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT). When the register bit(s) is set to 1. the occurrence of the enabled McASP condition(s) generates RINT. See the RSTAT register for a.." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED90," bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit." "0,1" rbitfld.long 0x1C 6. "RESERVED89," "0,1" bitfld.long 0x1C 5. "RDATA,Receive data ready interrupt enable bit." "0,1" bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit." "0,1" bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit." "0,1" newline bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit." "0,1" bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame sync interrupt enable bit." "0,1" bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit." "0,1" line.long 0x20 "CFG_RSTAT,The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number. If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the McASP logic has priority.." hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED91," bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR. Allows a single bit to be checked to determine if a receiver error interrupt has occurred." "0,1" bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag. RDMAERR is set when the CPU or DMA reads more serializers through the data port in a given time slot than were programmed as receivers. Causes a receive interrupt [RINT] if this bit is set and RDMAERR in RINTCTL is set." "0,1" bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag. Causes a receive interrupt [RINT] if this bit is set and RSTAFRM in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x20 5. "RDATA,Receive data ready flag. Causes a receive interrupt [RINT] if this bit is set and RDATA in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x20 4. "RLAST,Receive last slot flag. RLAST is set along with RDATA if the current slot is the last slot in a frame. Causes a receive interrupt [RINT] if this bit is set and RLAST in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0.." "0,1" newline rbitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of RSLOT. Allows a single read of RSTAT to determine whether the current TDM time slot is even or odd." "0,1" bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag. RCKFAIL is set when the receive clock failure detection circuit reports an error. Causes a receive interrupt [RINT] if this bit is set and RCKFAIL in RINTCTL is set. This bit is cleared by writing a 1 to this bit." "0,1" bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag. RSYNCERR is set when a new receive frame sync [AFSR] occurs before it is expected. Causes a receive interrupt [RINT] if this bit is set and RSYNCERR in RINTCTL is set. This bit is cleared by writing a 1 to.." "0,1" bitfld.long 0x20 0. "ROVRN,Receiver overrun flag. ROVRN is set when the receive serializer is instructed to transfer data from XRSR to RBUF but the former data in RBUF has not yet been read by the CPU or DMA. Causes a receive interrupt [RINT] if this bit is set and ROVRN.." "0,1" rgroup.long 0x84++0x3 line.long 0x0 "CFG_RSLOT,The current receive TDM time slot register (RSLOT) indicates the current time slot for the receive data frame." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED92," hexmask.long.word 0x0 0.--8. 1. "RSLOTCNT,0-17Fh = Current receive time slot count. Legal values: 0 to 383 [17Fh]. TDM function is not supported for > 32 time slots. However TDM time slot counter may count to 383 when used to receive a DIR block [transferred over TDM format]." rgroup.long 0x88++0x7 line.long 0x0 "CFG_RCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit." hexmask.long.byte 0x0 24.--31. 1. "RCNT,Receive clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 receive high-frequency master clock [AHCLKR] signals and stores the count in RCNT until the next measurement is.." hexmask.long.byte 0x0 16.--23. 1. "RMAX,Receive clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 receive high-frequency master clock [AHCLKR] signals have been received. If the current counter value is greater than.." hexmask.long.byte 0x0 8.--15. 1. "RMIN,Receive clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 receive high-frequency master clock [AHCLKR] signals have been received. If RCNT is less than RMIN after counting 32.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED93," hexmask.long.byte 0x0 0.--3. 1. "RPS,Receive clock check prescaler value." line.long 0x4 "CFG_PIDTCTL,The receiver DMA event control register (PIDTCTL) contains a disable bit for the receiver DMA event. Note for device-specific registers: Accessing PIDTCTL not implemented on a specific device may cause improper operation." hexmask.long 0x4 1.--31. 1. "RESERVED94," bitfld.long 0x4 0. "RDATDMA,Receive data DMA request enable bit. If writing to this bit always write the default value of 0." "0,1" rgroup.long 0xA0++0x23 line.long 0x0 "CFG_XGBLCTL,Alias of the global control register (GBLCTL). Writing to the transmitter global control register (XGBLCTL) affects only the transmit bits of GBLCTL (bits 12-8). Reads from XGBLCTL return the value of GBLCTL. XGBLCTL allows the transmitter to.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED96," bitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit. A write to this bit affects the XFRST bit of GBLCTL." "0,1" bitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit. A write to this bit affects the XSMRST bit of GBLCTL." "0,1" bitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. A write to this bit affects the XSRCLR bit of GBLCTL." "0,1" bitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit. A write to this bit affects the XHCLKRST bit of GBLCTL." "0,1" bitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit. A write to this bit affects the XCLKRST bit of GBLCTL." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED95," "0,1,2,3,4,5,6,7" rbitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit. A read of this bit returns the RFRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit. A read of this bit returns the RSMRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. A read of this bit returns the RSRSCLR bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit. A read of this bit returns the RHCLKRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 0. "RCLKRST,Receive clock divider reset enable bit. A read of this bit returns the RCLKRST bit value of GBLCTL. Writes have no effect." "0,1" line.long 0x4 "CFG_XMASK,The transmit format unit bit mask register (XMASK) determines which bits of the transmitted data are masked off and padded with a known value before being shifted out the McASP." hexmask.long 0x4 0.--31. 1. "XMASK,Transmit data mask n enable bit." line.long 0x8 "CFG_XFMT,The transmit bit stream format register (XFMT) configures the transmit data format." hexmask.long.word 0x8 18.--31. 1. "RESERVED97," bitfld.long 0x8 16.--17. "XDATDLY,Transmit sync bit delay." "0,1,2,3" bitfld.long 0x8 15. "XRVRS,Transmit serial bitstream order." "0,1" bitfld.long 0x8 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK. This field only applies to bits when XMASK[n] = 0." "0,1,2,3" hexmask.long.byte 0x8 8.--12. 1. "XPBIT,XPBIT value determines which bit [as written by the CPU or DMA to XBUF[n]] is used to pad the extra bits before shifting. This field only applies when XPAD = 2h." hexmask.long.byte 0x8 4.--7. 1. "XSSZ,Transmit slot size." newline bitfld.long 0x8 3. "XBUSEL,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port." "0,1" bitfld.long 0x8 0.--2. "XROT,Right-rotation value for transmit rotate right format unit." "0,1,2,3,4,5,6,7" line.long 0xC "CFG_AFSXCTL,The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX)." hexmask.long.word 0xC 16.--31. 1. "RESERVED100," hexmask.long.word 0xC 7.--15. 1. "XMOD,Transmit frame sync mode select bits. 1FFh = Reserved from 181h to 1FFh." rbitfld.long 0xC 5.--6. "RESERVED99," "0,1,2,3" bitfld.long 0xC 4. "FXWID,Transmit frame sync width select bit indicates the width of the transmit frame sync [AFSX] during its active period." "0,1" rbitfld.long 0xC 2.--3. "RESERVED98," "0,1,2,3" bitfld.long 0xC 1. "FSXM,Transmit frame sync generation select bit." "0,1" newline bitfld.long 0xC 0. "FSXP,Transmit frame sync polarity select bit." "0,1" line.long 0x10 "CFG_ACLKXCTL,The transmit clock control register (ACLKXCTL) configures the transmit bit clock (ACLKX) and the transmit clock generator." hexmask.long.word 0x10 21.--31. 1. "RESERVED102," bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress" "0,1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress" "0,1" bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "0,1,2,3" hexmask.long.byte 0x10 8.--15. 1. "RESERVED101," newline bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit." "0,1" bitfld.long 0x10 6. "ASYNC,Transmit/receive operation asynchronous enable bit." "0,1" bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit." "0,1" hexmask.long.byte 0x10 0.--4. 1. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX." line.long 0x14 "CFG_AHCLKXCTL,The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator." hexmask.long.word 0x14 21.--31. 1. "RESERVED104," bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "0,1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "0,1" bitfld.long 0x14 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "0,1,2,3" bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit." "0,1" newline bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit." "0,1" rbitfld.long 0x14 12.--13. "RESERVED103," "0,1,2,3" hexmask.long.word 0x14 0.--11. 1. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX." line.long 0x18 "CFG_XTDM,The transmit TDM time slot register (XTDM) specifies in which TDM time slot the transmitter is active. TDM time slot counter range is extended to 384 slots (to support SPDIF blocks of 384 subframes). XTDM operates modulo 32. that is. XTDMS.." hexmask.long 0x18 0.--31. 1. "XTDMS,Transmitter mode during TDM time slot n." line.long 0x1C "CFG_XINTCTL,The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt (XINT). When the register bit(s) is set to 1. the occurrence of the enabled McASP condition(s) generates XINT. See the XSTAT register for.." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED106," bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit." "0,1" rbitfld.long 0x1C 6. "RESERVED105," "0,1" bitfld.long 0x1C 5. "XDATA,Transmit data ready interrupt enable bit." "0,1" bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit." "0,1" bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit." "0,1" newline bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit." "0,1" bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame sync interrupt enable bit." "0,1" bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit." "0,1" line.long 0x20 "CFG_XSTAT,The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot number. If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the McASP logic has.." hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED107," bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR. Allows a single bit to be checked to determine if a transmitter error interrupt has occurred." "0,1" bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag. XDMAERR is set when the CPU or DMA writes more serializers through the data port in a given time slot than were programmed as transmitters. Causes a transmit interrupt [XINT] if this bit is set and XDMAERR in XINTCTL is.." "0,1" bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag. Causes a transmit interrupt [XINT] if this bit is set and XSTAFRM in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect." "0,1" bitfld.long 0x20 5. "XDATA,Transmit data ready flag. Causes a transmit interrupt [XINT] if this bit is set and XDATA in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect." "0,1" bitfld.long 0x20 4. "XLAST,Transmit last slot flag. XLAST is set along with XDATA if the current slot is the last slot in a frame. Causes a transmit interrupt [XINT] if this bit is set and XLAST in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0.." "0,1" newline rbitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of XSLOT. Allows a single read of XSTAT to determine whether the current TDM time slot is even or odd." "0,1" bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag. XCKFAIL is set when the transmit clock failure detection circuit reports an error. Causes a transmit interrupt [XINT] if this bit is set and XCKFAIL in XINTCTL is set. This bit is cleared by writing a 1 to this bit." "0,1" bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame sync flag. XSYNCERR is set when a new transmit frame sync [AFSX] occurs before it is expected. Causes a transmit interrupt [XINT] if this bit is set and XSYNCERR in XINTCTL is set. This bit is cleared by writing a 1 to.." "0,1" bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from XBUF to XRSR but XBUF has not yet been serviced with new data since the last transfer. Causes a transmit interrupt [XINT] if this bit is.." "0,1" rgroup.long 0xC4++0x3 line.long 0x0 "CFG_XSLOT,The current transmit TDM time slot register (XSLOT) indicates the current time slot for the transmit data frame." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED108," hexmask.long.word 0x0 0.--9. 1. "XSLOTCNT,Current transmit time slot count. Legal values: 0 to 383 [17Fh]. During reset this counter value is 383 so the next count value which is used to encode the first DIT group of data will be 0 and encodes the B preamble. TDM function is not.." rgroup.long 0xC8++0x7 line.long 0x0 "CFG_XCLKCHK,The transmit clock check control register (XCLKCHK) configures the transmit clock failure detection circuit." hexmask.long.byte 0x0 24.--31. 1. "XCNT,Transmit clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 transmit high-frequency master clock [AHCLKX] signals and stores the count in XCNT until the next measurement is.." hexmask.long.byte 0x0 16.--23. 1. "XMAX,Transmit clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high-frequency master clock [AHCLKX] signals have been received. If the current counter value is greater than.." hexmask.long.byte 0x0 8.--15. 1. "XMIN,Transmit clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 transmit high-frequency master clock [AHCLKX] signals have been received. If XCNT is less than XMIN after counting 32.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED109," hexmask.long.byte 0x0 0.--3. 1. "XPS,Transmit clock check prescaler value. Fh = Reserved from 9h to Fh." line.long 0x4 "CFG_XEVTCTL,The transmitter DMA event control register (XEVTCTL) contains a disable bit for the transmit DMA event. Note for device-specific registers: Accessing XEVTCTL not implemented on a specific device may cause improper device operation." hexmask.long 0x4 1.--31. 1. "RESERVED110," bitfld.long 0x4 0. "XDATDMA,Transmit data DMA request enable bit. If writing to this bit always write the default value of 0." "0,1" rgroup.long 0x100++0x5F line.long 0x0 "CFG_DITCSRA0,The DIT left channel status registers (DITCSRA0) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x0 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x4 "CFG_DITCSRA1,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x4 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x8 "CFG_DITCSRA2,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x8 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0xC "CFG_DITCSRA3,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0xC 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x10 "CFG_DITCSRA4,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x10 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x14 "CFG_DITCSRA5,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x14 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x18 "CFG_DITCSRB0,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x18 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x1C "CFG_DITCSRB1,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x1C 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x20 "CFG_DITCSRB2,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x20 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x24 "CFG_DITCSRB3,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x24 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x28 "CFG_DITCSRB4,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x28 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x2C "CFG_DITCSRB5,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x2C 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x30 "CFG_DITUDRA0,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x30 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x34 "CFG_DITUDRA1,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x34 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x38 "CFG_DITUDRA2,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x38 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x3C "CFG_DITUDRA3,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x3C 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x40 "CFG_DITUDRA4,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x40 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x44 "CFG_DITUDRA5,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x44 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x48 "CFG_DITUDRB0,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x48 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x4C "CFG_DITUDRB1,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x4C 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x50 "CFG_DITUDRB2,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x50 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x54 "CFG_DITUDRB3,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x54 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x58 "CFG_DITUDRB4,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x58 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x5C "CFG_DITUDRB5,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x5C 0.--31. 1. "DITUDRB,DIT right channel user data registers." rgroup.long 0x180++0x3F line.long 0x0 "CFG_SRCTL0,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x0 6.--31. 1. "RESERVED111," rbitfld.long 0x0 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x0 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x0 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x0 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x4 "CFG_SRCTL1,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x4 6.--31. 1. "RESERVED112," rbitfld.long 0x4 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x4 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x4 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x4 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x8 "CFG_SRCTL2,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x8 6.--31. 1. "RESERVED113," rbitfld.long 0x8 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x8 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x8 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x8 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0xC "CFG_SRCTL3,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0xC 6.--31. 1. "RESERVED114," rbitfld.long 0xC 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0xC 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0xC 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0xC 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x10 "CFG_SRCTL4,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x10 6.--31. 1. "RESERVED115," rbitfld.long 0x10 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x10 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x10 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x10 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x14 "CFG_SRCTL5,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x14 6.--31. 1. "RESERVED116," rbitfld.long 0x14 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x14 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x14 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x14 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x18 "CFG_SRCTL6,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x18 6.--31. 1. "RESERVED117," rbitfld.long 0x18 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x18 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x18 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x18 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x1C "CFG_SRCTL7,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x1C 6.--31. 1. "RESERVED118," rbitfld.long 0x1C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x1C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x1C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x1C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x20 "CFG_SRCTL8,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x20 6.--31. 1. "RESERVED119," rbitfld.long 0x20 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x20 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x20 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x20 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x24 "CFG_SRCTL9,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x24 6.--31. 1. "RESERVED120," rbitfld.long 0x24 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x24 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x24 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x24 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x28 "CFG_SRCTL10,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x28 6.--31. 1. "RESERVED121," rbitfld.long 0x28 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x28 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x28 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x28 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x2C "CFG_SRCTL11,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x2C 6.--31. 1. "RESERVED122," rbitfld.long 0x2C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x2C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x2C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x2C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x30 "CFG_SRCTL12,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x30 6.--31. 1. "RESERVED123," rbitfld.long 0x30 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x30 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x30 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x30 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x34 "CFG_SRCTL13,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x34 6.--31. 1. "RESERVED124," rbitfld.long 0x34 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x34 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x34 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x34 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x38 "CFG_SRCTL14,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x38 6.--31. 1. "RESERVED125," rbitfld.long 0x38 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x38 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x38 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x38 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x3C "CFG_SRCTL15,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x3C 6.--31. 1. "RESERVED126," rbitfld.long 0x3C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x3C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x3C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x3C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" rgroup.long 0x200++0x3F line.long 0x0 "CFG_XBUF0,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x0 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x4 "CFG_XBUF1,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x4 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x8 "CFG_XBUF2,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x8 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0xC "CFG_XBUF3,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0xC 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x10 "CFG_XBUF4,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x10 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x14 "CFG_XBUF5,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x14 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x18 "CFG_XBUF6,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x18 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x1C "CFG_XBUF7,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x1C 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x20 "CFG_XBUF8,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x20 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x24 "CFG_XBUF9,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x24 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x28 "CFG_XBUF10,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x28 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x2C "CFG_XBUF11,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x2C 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x30 "CFG_XBUF12,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x30 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x34 "CFG_XBUF13,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x34 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x38 "CFG_XBUF14,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x38 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x3C "CFG_XBUF15,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x3C 0.--31. 1. "XBUF,Transmit buffers for serializers." rgroup.long 0x280++0x3F line.long 0x0 "CFG_RBUF0,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x0 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x4 "CFG_RBUF1,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x4 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x8 "CFG_RBUF2,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x8 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0xC "CFG_RBUF3,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0xC 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x10 "CFG_RBUF4,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x10 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x14 "CFG_RBUF5,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x14 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x18 "CFG_RBUF6,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x18 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x1C "CFG_RBUF7,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x1C 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x20 "CFG_RBUF8,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x20 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x24 "CFG_RBUF9,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x24 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x28 "CFG_RBUF10,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x28 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x2C "CFG_RBUF11,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x2C 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x30 "CFG_RBUF12,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x30 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x34 "CFG_RBUF13,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x34 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x38 "CFG_RBUF14,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x38 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x3C "CFG_RBUF15,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x3C 0.--31. 1. "RBUF,Receive buffers for serializers." rgroup.long 0x1000++0x3 line.long 0x0 "CFG_WFIFOCTL,The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO. If the Write FIFO is to be enabled. it must be enabled prior to taking the McASP out of reset" hexmask.long.word 0x0 17.--31. 1. "RESERVED127," bitfld.long 0x0 16. "WENA,Write FIFO enable bit." "0,1" hexmask.long.byte 0x0 8.--15. 1. "WNUMEVT,Write word count per DMA event [32 bit]. When the Write FIFO has space for at least WNUMEVT words of data then an AXEVT [transmit DMA event] is generated to the host/DMA controller. This value should be set to a non-zero integer multiple of the.." hexmask.long.byte 0x0 0.--7. 1. "WNUMDMA,Write word count per transfer [32 bit words]. Upon a transmit DMA event from the McASP WNUMDMA words are transferred from the Write FIFO to the McASP. This value must equal the number of McASP serializers used as transmitters. This value must be.." rgroup.long 0x1004++0x3 line.long 0x0 "CFG_WFIFOSTS," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED128," hexmask.long.byte 0x0 0.--7. 1. "WLVL,Write level [read-only]. Number of 32 bit words currently in the Write FIFO. 40h = 3 to 64 words currently in Write FIFO from 3h to 40h. FFh = Reserved from 41h to FFh." rgroup.long 0x1008++0x3 line.long 0x0 "CFG_RFIFOCTL,The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO. If the Read FIFO is to be enabled. it must be enabled prior to taking the McASP out of reset" hexmask.long.word 0x0 17.--31. 1. "RESERVED129," bitfld.long 0x0 16. "RENA,Read FIFO enable bit." "0,1" hexmask.long.byte 0x0 8.--15. 1. "RNUMEVT,Read word count per DMA event [32 bit]. When the Read FIFO contains at least RNUMEVT words of data then an AREVT [receive DMA event] is generated to the host/DMA controller. This value should be set to a non-zero integer multiple of the number.." hexmask.long.byte 0x0 0.--7. 1. "RNUMDMA,Read word count per transfer [32 bit words]. Upon a receive DMA event from the McASP the Read FIFO reads RNUMDMA words from the McASP. This value must equal the number of McASP serializers used as receivers. This value must be set prior to.." rgroup.long 0x100C++0x3 line.long 0x0 "CFG_RFIFOSTS," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED130," hexmask.long.byte 0x0 0.--7. 1. "RLVL,Read level [read-only]. Number of 32 bit words currently in the Read FIFO. 40h = 3 to 64 words currently in Read FIFO from 3h to 40h. FFh = Reserved from 41h to FFh." tree.end tree "MCASP1_CFG (MCASP1_CFG)" base ad:0x2B10000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_PID,The revision identification register (PID) contains identification data for the peripheral." hexmask.long 0x0 0.--31. 1. "REV,Identifies revision of peripheral." rgroup.long 0x4++0x3 line.long 0x0 "CFG_PWRIDLESYSCONFIG," hexmask.long 0x0 6.--31. 1. "RESERVED66," hexmask.long.byte 0x0 2.--5. 1. "OTHER,Reserved for future programming." bitfld.long 0x0 0.--1. "IDLEMODE,Power management Configuration of the local target state management mode. By definition target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" rgroup.long 0x10++0x13 line.long 0x0 "CFG_PFUNC,The pin function register (PFUNC) specifies the function of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either a McASP pin or a general-purpose input/output (GPIO) pin. CAUTION: Writing a value other than 0 to reserved bits in.." bitfld.long 0x0 31. "AFSR,Determines if AFSR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 30. "AHCLKR,Determines if AHCLKR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 29. "ACLKR,Determines if ACLKR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 28. "AFSX,Determines if AFSX pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 27. "AHCLKX,Determines if AHCLKX pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 26. "ACLKX,Determines if ACLKX pin functions as McASP or GPIO." "0,1" newline bitfld.long 0x0 25. "AMUTE,Determines if AMUTE pin functions as McASP or GPIO." "0,1" hexmask.long.tbyte 0x0 4.--24. 1. "RESERVED67," hexmask.long.byte 0x0 0.--3. 1. "AXR,Determines if AXRn pin functions as McASP or GPIO." line.long 0x4 "CFG_PDIR,The pin direction register (PDIR) specifies the direction of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either an input or an output pin. Regardless of the pin function register (PFUNC) setting. each PDIR bit must be set to 1 for.." bitfld.long 0x4 31. "AFSR,Determines if AFSR pin functions as an input or output." "0,1" bitfld.long 0x4 30. "AHCLKR,Determines if AHCLKR pin functions as an input or output." "0,1" bitfld.long 0x4 29. "ACLKR,Determines if ACLKR pin functions as an input or output." "0,1" bitfld.long 0x4 28. "AFSX,Determines if AFSX pin functions as an input or output." "0,1" bitfld.long 0x4 27. "AHCLKX,Determines if AHCLKX pin functions as an input or output." "0,1" bitfld.long 0x4 26. "ACLKX,Determines if ACLKX pin functions as an input or output." "0,1" newline bitfld.long 0x4 25. "AMUTE,Determines if AMUTE pin functions as an input or output." "0,1" hexmask.long.tbyte 0x4 4.--24. 1. "RESERVED68," hexmask.long.byte 0x4 0.--3. 1. "AXR,Determines if AXRn pin functions as an input or output." line.long 0x8 "CFG_PDOUT,The pin data output register (PDOUT) holds a value for data out at all times. and may be read back at all times. The value held by PDOUT is not affected by writing to PDIR and PFUNC. However. the data value in PDOUT is driven out onto the McASP.." bitfld.long 0x8 31. "AFSR,Determines drive on AFSR output pin when the corresponding PFUNC[31] and PDIR[31] bits are set to 1." "0,1" bitfld.long 0x8 30. "AHCLKR,Determines drive on AHCLKR output pin when the corresponding PFUNC[30] and PDIR[30] bits are set to 1." "0,1" bitfld.long 0x8 29. "ACLKR,Determines drive on ACLKR output pin when the corresponding PFUNC[29] and PDIR[29] bits are set to 1." "0,1" bitfld.long 0x8 28. "AFSX,Determines drive on AFSX output pin when the corresponding PFUNC[28] and PDIR[28] bits are set to 1." "0,1" bitfld.long 0x8 27. "AHCLKX,Determines drive on AHCLKX output pin when the corresponding PFUNC[27] and PDIR[27] bits are set to 1." "0,1" bitfld.long 0x8 26. "ACLKX,Determines drive on ACLKX output pin when the corresponding PFUNC[26] and PDIR[26] bits are set to 1." "0,1" newline bitfld.long 0x8 25. "AMUTE,Determines drive on AMUTE output pin when the corresponding PFUNC[25] and PDIR[25] bits are set to 1." "0,1" hexmask.long.tbyte 0x8 4.--24. 1. "RESERVED69," hexmask.long.byte 0x8 0.--3. 1. "AXR,Determines drive on AXR[n] output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1." line.long 0xC "CFG_PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins. PDIN allows the actual value of the pin to be read. regardless of the state of PFUNC and PDIR. The value after reset for registers 1 through 15 and 24 through.." bitfld.long 0xC 31. "AFSR,Logic level on AFSR pin." "0,1" bitfld.long 0xC 30. "AHCLKR,Logic level on AHCLKR pin." "0,1" bitfld.long 0xC 29. "ACLKR,Logic level on ACLKR pin." "0,1" bitfld.long 0xC 28. "AFSX,Logic level on AFSX pin." "0,1" bitfld.long 0xC 27. "AHCLKX,Logic level on AHCLKX pin." "0,1" bitfld.long 0xC 26. "ACLKX,Logic level on ACLKX pin." "0,1" newline bitfld.long 0xC 25. "AMUTE,Logic level on AMUTE pin." "0,1" hexmask.long.tbyte 0xC 4.--24. 1. "RESERVED70," hexmask.long.byte 0xC 0.--3. 1. "AXR,Logic level on AXR[n] pin." line.long 0x10 "CFG_PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDCLR bit clears the corresponding bit in PDOUT and. if PFUNC = 1 (GPIO function) and PDIR = 1 (output). drives a logic.." bitfld.long 0x10 31. "AFSR,Allows the corresponding AFSR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 30. "AHCLKR,Allows the corresponding AHCLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 29. "ACLKR,Allows the corresponding ACLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 28. "AFSX,Allows the corresponding AFSX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 27. "AHCLKX,Allows the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 26. "ACLKX,Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" newline bitfld.long 0x10 25. "AMUTE,Allows the corresponding AMUTE bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" hexmask.long.tbyte 0x10 4.--24. 1. "RESERVED71," hexmask.long.byte 0x10 0.--3. 1. "AXR,Allows the corresponding AXR[n] bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." rgroup.long 0x44++0xF line.long 0x0 "CFG_GBLCTL,The global control register (GBLCTL) provides initialization of the transmit and receive sections. The bit fields in GBLCTL are synchronized and latched by the corresponding clocks (ACLKX for bits 12-8 and ACLKR for bits 4-0). Before GBLCTL is.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED73," bitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit." "0,1" bitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit." "0,1" bitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. By clearing then setting this bit the transmit buffer is flushed to an empty state [XDATA = 1]. If XSMRST = 1 XSRCLR = 1 XDATA = 1 and XBUF is not loaded with new data before the start of the next active.." "0,1" bitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit." "0,1" bitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED72," "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit." "0,1" bitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit." "0,1" bitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. By clearing then setting this bit the receive buffer is flushed." "0,1" bitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit." "0,1" bitfld.long 0x0 0. "RCLKRST,Receive high-frequency clock divider reset enable bit." "0,1" line.long 0x4 "CFG_AMUTE,The audio mute control register (AMUTE) controls the McASP audio mute (AMUTE) output pin. The value after reset for register 4 depends on how the pins are being driven." hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED74," bitfld.long 0x4 12. "XDMAERR,If transmit DMA error [XDMAERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 11. "RDMAERR,If receive DMA error [RDMAERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 10. "XCKFAIL,If transmit clock failure [XCKFAIL] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 9. "RCKFAIL,If receive clock failure [RCKFAIL] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 8. "XSYNCERR,If unexpected transmit frame sync error [XSYNCERR] drive AMUTE active enable bit." "0,1" newline bitfld.long 0x4 7. "RSYNCERR,If unexpected receive frame sync error [RSYNCERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 6. "XUNDRN,If transmit underrun error [XUNDRN] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 5. "ROVRN,If receiver overrun error [ROVRN] drive AMUTE active enable bit." "0,1" rbitfld.long 0x4 4. "INSTAT,Determines drive on AXRn pin when PFUNC[n] and PDIR[n] bits are set to 1." "0,1" bitfld.long 0x4 3. "INEN,Drive AMUTE active when AMUTEIN error is active [INSTAT = 1]." "0,1" bitfld.long 0x4 2. "INPOL,Audio mute in [AMUTEIN] polarity select bit." "0,1" newline bitfld.long 0x4 0.--1. "MUTEN,AMUTE pin enable bit [unless overridden by GPIO registers]." "0,1,2,3" line.long 0x8 "CFG_DLBCTL,The digital loopback control register (DLBCTL) controls the internal loopback settings of the McASP in TDM mode." hexmask.long 0x8 4.--31. 1. "RESERVED75," bitfld.long 0x8 2.--3. "MODE,Loopback generator mode bits. Applies only when loopback mode is enabled [DLBEN = 1]." "0,1,2,3" bitfld.long 0x8 1. "ORD,Loopback order bit when loopback mode is enabled [DLBEN = 1]." "0,1" bitfld.long 0x8 0. "DLBEN,Loopback mode enable bit." "0,1" line.long 0xC "CFG_DITCTL,The DIT mode control register (DITCTL) controls DIT operations of the McASP." hexmask.long 0xC 4.--31. 1. "RESERVED77," bitfld.long 0xC 3. "VB,Valid bit for odd time slots [DIT right subframe]." "0,1" bitfld.long 0xC 2. "VA,Valid bit for even time slots [DIT left subframe]." "0,1" rbitfld.long 0xC 1. "RESERVED76," "0,1" bitfld.long 0xC 0. "DITEN,DIT mode enable bit. DITEN should only be changed while the XSMRST bit in GBLCTL is in reset [and for startup XSRCLR also in reset]. However it is not necessary to reset the XCLKRST or XHCLKRST bits in GBLCTL to change DITEN." "0,1" rgroup.long 0x60++0x23 line.long 0x0 "CFG_RGBLCTL,Alias of the global control register (GBLCTL). Writing to the receiver global control register (RGBLCTL) affects only the receive bits of GBLCTL (bits 4-0). Reads from RGBLCTL return the value of GBLCTL. RGBLCTL allows the receiver to be.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED79," rbitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit. A read of this bit returns the XFRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit. A read of this bit returns the XSMRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. A read of this bit returns the XSRCLR bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit. A read of this bit returns the XHCLKRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit. A read of this bit returns the XCLKRST bit value of GBLCTL. Writes have no effect." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED78," "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit. A write to this bit affects the RFRST bit of GBLCTL." "0,1" bitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit. A write to this bit affects the RSMRST bit of GBLCTL." "0,1" bitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. A write to this bit affects the RSRCLR bit of GBLCTL." "0,1" bitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit. A write to this bit affects the RHCLKRST bit of GBLCTL." "0,1" bitfld.long 0x0 0. "RCLKRST,Receive clock divider reset enable bit. A write to this bit affects the RCLKRST bit of GBLCTL." "0,1" line.long 0x4 "CFG_RMASK,The receive format unit bit mask register (RMASK) determines which bits of the received data are masked off and padded with a known value before being read by the CPU or DMA." hexmask.long 0x4 0.--31. 1. "RMASK,Receive data mask n enable bit." line.long 0x8 "CFG_RFMT,The receive bit stream format register (RFMT) configures the receive data format." hexmask.long.word 0x8 18.--31. 1. "RESERVED80," bitfld.long 0x8 16.--17. "RDATDLY,Receive bit delay." "0,1,2,3" bitfld.long 0x8 15. "RRVRS,Receive serial bitstream order." "0,1" bitfld.long 0x8 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word. This field only applies to bits when RMASK[n] = 0." "0,1,2,3" hexmask.long.byte 0x8 8.--12. 1. "RPBIT,RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits. This field only applies when RPAD = 2h." hexmask.long.byte 0x8 4.--7. 1. "RSSZ,Receive slot size." newline bitfld.long 0x8 3. "RBUSEL,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port." "0,1" bitfld.long 0x8 0.--2. "RROT,Right-rotation value for receive rotate right format unit." "0,1,2,3,4,5,6,7" line.long 0xC "CFG_AFSRCTL,The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR)." hexmask.long.word 0xC 16.--31. 1. "RESERVED83," hexmask.long.word 0xC 7.--15. 1. "RMOD,Receive frame sync mode select bits. 1FFh = Reserved from 181h to 1FFh." rbitfld.long 0xC 5.--6. "RESERVED82," "0,1,2,3" bitfld.long 0xC 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period." "0,1" rbitfld.long 0xC 2.--3. "RESERVED81," "0,1,2,3" bitfld.long 0xC 1. "FSRM,Receive frame sync generation select bit." "0,1" newline bitfld.long 0xC 0. "FSRP,Receive frame sync polarity select bit." "0,1" line.long 0x10 "CFG_ACLKRCTL,The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive clock generator." hexmask.long.word 0x10 21.--31. 1. "RESERVED86," bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress" "0,1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress" "0,1" bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "0,1,2,3" hexmask.long.byte 0x10 8.--15. 1. "RESERVED85," newline bitfld.long 0x10 7. "CLKRP,Receive bitstream clock polarity select bit." "0,1" rbitfld.long 0x10 6. "RESERVED84," "0,1" bitfld.long 0x10 5. "CLKRM,Receive bit clock source bit. Note that this bit does not have any effect if ACLKXCTL.ASYNC = 0." "0,1" hexmask.long.byte 0x10 0.--4. 1. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR. Note that this bit does not have any effect if ACLKXCTL.ASYNC = 0." line.long 0x14 "CFG_AHCLKRCTL,The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency master clock (AHCLKR) and the receive clock generator." hexmask.long.word 0x14 21.--31. 1. "RESERVED88," bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "0,1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "0,1" bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "0,1,2,3" bitfld.long 0x14 15. "HCLKRM,Receive high-frequency clock source bit." "0,1" newline bitfld.long 0x14 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit." "0,1" rbitfld.long 0x14 12.--13. "RESERVED87," "0,1,2,3" hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR." line.long 0x18 "CFG_RTDM,The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active." hexmask.long 0x18 0.--31. 1. "RTDMS,Receiver mode during TDM time slot n." line.long 0x1C "CFG_RINTCTL,The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT). When the register bit(s) is set to 1. the occurrence of the enabled McASP condition(s) generates RINT. See the RSTAT register for a.." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED90," bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit." "0,1" rbitfld.long 0x1C 6. "RESERVED89," "0,1" bitfld.long 0x1C 5. "RDATA,Receive data ready interrupt enable bit." "0,1" bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit." "0,1" bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit." "0,1" newline bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit." "0,1" bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame sync interrupt enable bit." "0,1" bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit." "0,1" line.long 0x20 "CFG_RSTAT,The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number. If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the McASP logic has priority.." hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED91," bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR. Allows a single bit to be checked to determine if a receiver error interrupt has occurred." "0,1" bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag. RDMAERR is set when the CPU or DMA reads more serializers through the data port in a given time slot than were programmed as receivers. Causes a receive interrupt [RINT] if this bit is set and RDMAERR in RINTCTL is set." "0,1" bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag. Causes a receive interrupt [RINT] if this bit is set and RSTAFRM in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x20 5. "RDATA,Receive data ready flag. Causes a receive interrupt [RINT] if this bit is set and RDATA in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x20 4. "RLAST,Receive last slot flag. RLAST is set along with RDATA if the current slot is the last slot in a frame. Causes a receive interrupt [RINT] if this bit is set and RLAST in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0.." "0,1" newline rbitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of RSLOT. Allows a single read of RSTAT to determine whether the current TDM time slot is even or odd." "0,1" bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag. RCKFAIL is set when the receive clock failure detection circuit reports an error. Causes a receive interrupt [RINT] if this bit is set and RCKFAIL in RINTCTL is set. This bit is cleared by writing a 1 to this bit." "0,1" bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag. RSYNCERR is set when a new receive frame sync [AFSR] occurs before it is expected. Causes a receive interrupt [RINT] if this bit is set and RSYNCERR in RINTCTL is set. This bit is cleared by writing a 1 to.." "0,1" bitfld.long 0x20 0. "ROVRN,Receiver overrun flag. ROVRN is set when the receive serializer is instructed to transfer data from XRSR to RBUF but the former data in RBUF has not yet been read by the CPU or DMA. Causes a receive interrupt [RINT] if this bit is set and ROVRN.." "0,1" rgroup.long 0x84++0x3 line.long 0x0 "CFG_RSLOT,The current receive TDM time slot register (RSLOT) indicates the current time slot for the receive data frame." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED92," hexmask.long.word 0x0 0.--8. 1. "RSLOTCNT,0-17Fh = Current receive time slot count. Legal values: 0 to 383 [17Fh]. TDM function is not supported for > 32 time slots. However TDM time slot counter may count to 383 when used to receive a DIR block [transferred over TDM format]." rgroup.long 0x88++0x7 line.long 0x0 "CFG_RCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit." hexmask.long.byte 0x0 24.--31. 1. "RCNT,Receive clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 receive high-frequency master clock [AHCLKR] signals and stores the count in RCNT until the next measurement is.." hexmask.long.byte 0x0 16.--23. 1. "RMAX,Receive clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 receive high-frequency master clock [AHCLKR] signals have been received. If the current counter value is greater than.." hexmask.long.byte 0x0 8.--15. 1. "RMIN,Receive clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 receive high-frequency master clock [AHCLKR] signals have been received. If RCNT is less than RMIN after counting 32.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED93," hexmask.long.byte 0x0 0.--3. 1. "RPS,Receive clock check prescaler value." line.long 0x4 "CFG_PIDTCTL,The receiver DMA event control register (PIDTCTL) contains a disable bit for the receiver DMA event. Note for device-specific registers: Accessing PIDTCTL not implemented on a specific device may cause improper operation." hexmask.long 0x4 1.--31. 1. "RESERVED94," bitfld.long 0x4 0. "RDATDMA,Receive data DMA request enable bit. If writing to this bit always write the default value of 0." "0,1" rgroup.long 0xA0++0x23 line.long 0x0 "CFG_XGBLCTL,Alias of the global control register (GBLCTL). Writing to the transmitter global control register (XGBLCTL) affects only the transmit bits of GBLCTL (bits 12-8). Reads from XGBLCTL return the value of GBLCTL. XGBLCTL allows the transmitter to.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED96," bitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit. A write to this bit affects the XFRST bit of GBLCTL." "0,1" bitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit. A write to this bit affects the XSMRST bit of GBLCTL." "0,1" bitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. A write to this bit affects the XSRCLR bit of GBLCTL." "0,1" bitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit. A write to this bit affects the XHCLKRST bit of GBLCTL." "0,1" bitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit. A write to this bit affects the XCLKRST bit of GBLCTL." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED95," "0,1,2,3,4,5,6,7" rbitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit. A read of this bit returns the RFRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit. A read of this bit returns the RSMRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. A read of this bit returns the RSRSCLR bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit. A read of this bit returns the RHCLKRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 0. "RCLKRST,Receive clock divider reset enable bit. A read of this bit returns the RCLKRST bit value of GBLCTL. Writes have no effect." "0,1" line.long 0x4 "CFG_XMASK,The transmit format unit bit mask register (XMASK) determines which bits of the transmitted data are masked off and padded with a known value before being shifted out the McASP." hexmask.long 0x4 0.--31. 1. "XMASK,Transmit data mask n enable bit." line.long 0x8 "CFG_XFMT,The transmit bit stream format register (XFMT) configures the transmit data format." hexmask.long.word 0x8 18.--31. 1. "RESERVED97," bitfld.long 0x8 16.--17. "XDATDLY,Transmit sync bit delay." "0,1,2,3" bitfld.long 0x8 15. "XRVRS,Transmit serial bitstream order." "0,1" bitfld.long 0x8 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK. This field only applies to bits when XMASK[n] = 0." "0,1,2,3" hexmask.long.byte 0x8 8.--12. 1. "XPBIT,XPBIT value determines which bit [as written by the CPU or DMA to XBUF[n]] is used to pad the extra bits before shifting. This field only applies when XPAD = 2h." hexmask.long.byte 0x8 4.--7. 1. "XSSZ,Transmit slot size." newline bitfld.long 0x8 3. "XBUSEL,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port." "0,1" bitfld.long 0x8 0.--2. "XROT,Right-rotation value for transmit rotate right format unit." "0,1,2,3,4,5,6,7" line.long 0xC "CFG_AFSXCTL,The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX)." hexmask.long.word 0xC 16.--31. 1. "RESERVED100," hexmask.long.word 0xC 7.--15. 1. "XMOD,Transmit frame sync mode select bits. 1FFh = Reserved from 181h to 1FFh." rbitfld.long 0xC 5.--6. "RESERVED99," "0,1,2,3" bitfld.long 0xC 4. "FXWID,Transmit frame sync width select bit indicates the width of the transmit frame sync [AFSX] during its active period." "0,1" rbitfld.long 0xC 2.--3. "RESERVED98," "0,1,2,3" bitfld.long 0xC 1. "FSXM,Transmit frame sync generation select bit." "0,1" newline bitfld.long 0xC 0. "FSXP,Transmit frame sync polarity select bit." "0,1" line.long 0x10 "CFG_ACLKXCTL,The transmit clock control register (ACLKXCTL) configures the transmit bit clock (ACLKX) and the transmit clock generator." hexmask.long.word 0x10 21.--31. 1. "RESERVED102," bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress" "0,1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress" "0,1" bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "0,1,2,3" hexmask.long.byte 0x10 8.--15. 1. "RESERVED101," newline bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit." "0,1" bitfld.long 0x10 6. "ASYNC,Transmit/receive operation asynchronous enable bit." "0,1" bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit." "0,1" hexmask.long.byte 0x10 0.--4. 1. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX." line.long 0x14 "CFG_AHCLKXCTL,The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator." hexmask.long.word 0x14 21.--31. 1. "RESERVED104," bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "0,1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "0,1" bitfld.long 0x14 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "0,1,2,3" bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit." "0,1" newline bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit." "0,1" rbitfld.long 0x14 12.--13. "RESERVED103," "0,1,2,3" hexmask.long.word 0x14 0.--11. 1. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX." line.long 0x18 "CFG_XTDM,The transmit TDM time slot register (XTDM) specifies in which TDM time slot the transmitter is active. TDM time slot counter range is extended to 384 slots (to support SPDIF blocks of 384 subframes). XTDM operates modulo 32. that is. XTDMS.." hexmask.long 0x18 0.--31. 1. "XTDMS,Transmitter mode during TDM time slot n." line.long 0x1C "CFG_XINTCTL,The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt (XINT). When the register bit(s) is set to 1. the occurrence of the enabled McASP condition(s) generates XINT. See the XSTAT register for.." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED106," bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit." "0,1" rbitfld.long 0x1C 6. "RESERVED105," "0,1" bitfld.long 0x1C 5. "XDATA,Transmit data ready interrupt enable bit." "0,1" bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit." "0,1" bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit." "0,1" newline bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit." "0,1" bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame sync interrupt enable bit." "0,1" bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit." "0,1" line.long 0x20 "CFG_XSTAT,The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot number. If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the McASP logic has.." hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED107," bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR. Allows a single bit to be checked to determine if a transmitter error interrupt has occurred." "0,1" bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag. XDMAERR is set when the CPU or DMA writes more serializers through the data port in a given time slot than were programmed as transmitters. Causes a transmit interrupt [XINT] if this bit is set and XDMAERR in XINTCTL is.." "0,1" bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag. Causes a transmit interrupt [XINT] if this bit is set and XSTAFRM in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect." "0,1" bitfld.long 0x20 5. "XDATA,Transmit data ready flag. Causes a transmit interrupt [XINT] if this bit is set and XDATA in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect." "0,1" bitfld.long 0x20 4. "XLAST,Transmit last slot flag. XLAST is set along with XDATA if the current slot is the last slot in a frame. Causes a transmit interrupt [XINT] if this bit is set and XLAST in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0.." "0,1" newline rbitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of XSLOT. Allows a single read of XSTAT to determine whether the current TDM time slot is even or odd." "0,1" bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag. XCKFAIL is set when the transmit clock failure detection circuit reports an error. Causes a transmit interrupt [XINT] if this bit is set and XCKFAIL in XINTCTL is set. This bit is cleared by writing a 1 to this bit." "0,1" bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame sync flag. XSYNCERR is set when a new transmit frame sync [AFSX] occurs before it is expected. Causes a transmit interrupt [XINT] if this bit is set and XSYNCERR in XINTCTL is set. This bit is cleared by writing a 1 to.." "0,1" bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from XBUF to XRSR but XBUF has not yet been serviced with new data since the last transfer. Causes a transmit interrupt [XINT] if this bit is.." "0,1" rgroup.long 0xC4++0x3 line.long 0x0 "CFG_XSLOT,The current transmit TDM time slot register (XSLOT) indicates the current time slot for the transmit data frame." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED108," hexmask.long.word 0x0 0.--9. 1. "XSLOTCNT,Current transmit time slot count. Legal values: 0 to 383 [17Fh]. During reset this counter value is 383 so the next count value which is used to encode the first DIT group of data will be 0 and encodes the B preamble. TDM function is not.." rgroup.long 0xC8++0x7 line.long 0x0 "CFG_XCLKCHK,The transmit clock check control register (XCLKCHK) configures the transmit clock failure detection circuit." hexmask.long.byte 0x0 24.--31. 1. "XCNT,Transmit clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 transmit high-frequency master clock [AHCLKX] signals and stores the count in XCNT until the next measurement is.." hexmask.long.byte 0x0 16.--23. 1. "XMAX,Transmit clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high-frequency master clock [AHCLKX] signals have been received. If the current counter value is greater than.." hexmask.long.byte 0x0 8.--15. 1. "XMIN,Transmit clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 transmit high-frequency master clock [AHCLKX] signals have been received. If XCNT is less than XMIN after counting 32.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED109," hexmask.long.byte 0x0 0.--3. 1. "XPS,Transmit clock check prescaler value. Fh = Reserved from 9h to Fh." line.long 0x4 "CFG_XEVTCTL,The transmitter DMA event control register (XEVTCTL) contains a disable bit for the transmit DMA event. Note for device-specific registers: Accessing XEVTCTL not implemented on a specific device may cause improper device operation." hexmask.long 0x4 1.--31. 1. "RESERVED110," bitfld.long 0x4 0. "XDATDMA,Transmit data DMA request enable bit. If writing to this bit always write the default value of 0." "0,1" rgroup.long 0x100++0x5F line.long 0x0 "CFG_DITCSRA0,The DIT left channel status registers (DITCSRA0) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x0 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x4 "CFG_DITCSRA1,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x4 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x8 "CFG_DITCSRA2,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x8 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0xC "CFG_DITCSRA3,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0xC 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x10 "CFG_DITCSRA4,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x10 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x14 "CFG_DITCSRA5,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x14 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x18 "CFG_DITCSRB0,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x18 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x1C "CFG_DITCSRB1,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x1C 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x20 "CFG_DITCSRB2,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x20 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x24 "CFG_DITCSRB3,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x24 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x28 "CFG_DITCSRB4,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x28 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x2C "CFG_DITCSRB5,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x2C 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x30 "CFG_DITUDRA0,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x30 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x34 "CFG_DITUDRA1,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x34 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x38 "CFG_DITUDRA2,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x38 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x3C "CFG_DITUDRA3,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x3C 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x40 "CFG_DITUDRA4,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x40 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x44 "CFG_DITUDRA5,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x44 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x48 "CFG_DITUDRB0,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x48 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x4C "CFG_DITUDRB1,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x4C 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x50 "CFG_DITUDRB2,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x50 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x54 "CFG_DITUDRB3,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x54 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x58 "CFG_DITUDRB4,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x58 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x5C "CFG_DITUDRB5,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x5C 0.--31. 1. "DITUDRB,DIT right channel user data registers." rgroup.long 0x180++0x3F line.long 0x0 "CFG_SRCTL0,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x0 6.--31. 1. "RESERVED111," rbitfld.long 0x0 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x0 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x0 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x0 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x4 "CFG_SRCTL1,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x4 6.--31. 1. "RESERVED112," rbitfld.long 0x4 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x4 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x4 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x4 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x8 "CFG_SRCTL2,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x8 6.--31. 1. "RESERVED113," rbitfld.long 0x8 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x8 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x8 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x8 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0xC "CFG_SRCTL3,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0xC 6.--31. 1. "RESERVED114," rbitfld.long 0xC 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0xC 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0xC 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0xC 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x10 "CFG_SRCTL4,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x10 6.--31. 1. "RESERVED115," rbitfld.long 0x10 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x10 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x10 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x10 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x14 "CFG_SRCTL5,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x14 6.--31. 1. "RESERVED116," rbitfld.long 0x14 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x14 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x14 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x14 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x18 "CFG_SRCTL6,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x18 6.--31. 1. "RESERVED117," rbitfld.long 0x18 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x18 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x18 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x18 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x1C "CFG_SRCTL7,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x1C 6.--31. 1. "RESERVED118," rbitfld.long 0x1C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x1C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x1C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x1C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x20 "CFG_SRCTL8,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x20 6.--31. 1. "RESERVED119," rbitfld.long 0x20 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x20 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x20 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x20 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x24 "CFG_SRCTL9,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x24 6.--31. 1. "RESERVED120," rbitfld.long 0x24 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x24 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x24 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x24 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x28 "CFG_SRCTL10,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x28 6.--31. 1. "RESERVED121," rbitfld.long 0x28 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x28 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x28 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x28 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x2C "CFG_SRCTL11,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x2C 6.--31. 1. "RESERVED122," rbitfld.long 0x2C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x2C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x2C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x2C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x30 "CFG_SRCTL12,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x30 6.--31. 1. "RESERVED123," rbitfld.long 0x30 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x30 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x30 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x30 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x34 "CFG_SRCTL13,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x34 6.--31. 1. "RESERVED124," rbitfld.long 0x34 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x34 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x34 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x34 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x38 "CFG_SRCTL14,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x38 6.--31. 1. "RESERVED125," rbitfld.long 0x38 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x38 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x38 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x38 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x3C "CFG_SRCTL15,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x3C 6.--31. 1. "RESERVED126," rbitfld.long 0x3C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x3C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x3C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x3C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" rgroup.long 0x200++0x3F line.long 0x0 "CFG_XBUF0,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x0 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x4 "CFG_XBUF1,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x4 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x8 "CFG_XBUF2,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x8 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0xC "CFG_XBUF3,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0xC 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x10 "CFG_XBUF4,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x10 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x14 "CFG_XBUF5,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x14 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x18 "CFG_XBUF6,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x18 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x1C "CFG_XBUF7,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x1C 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x20 "CFG_XBUF8,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x20 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x24 "CFG_XBUF9,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x24 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x28 "CFG_XBUF10,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x28 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x2C "CFG_XBUF11,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x2C 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x30 "CFG_XBUF12,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x30 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x34 "CFG_XBUF13,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x34 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x38 "CFG_XBUF14,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x38 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x3C "CFG_XBUF15,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x3C 0.--31. 1. "XBUF,Transmit buffers for serializers." rgroup.long 0x280++0x3F line.long 0x0 "CFG_RBUF0,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x0 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x4 "CFG_RBUF1,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x4 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x8 "CFG_RBUF2,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x8 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0xC "CFG_RBUF3,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0xC 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x10 "CFG_RBUF4,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x10 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x14 "CFG_RBUF5,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x14 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x18 "CFG_RBUF6,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x18 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x1C "CFG_RBUF7,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x1C 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x20 "CFG_RBUF8,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x20 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x24 "CFG_RBUF9,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x24 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x28 "CFG_RBUF10,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x28 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x2C "CFG_RBUF11,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x2C 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x30 "CFG_RBUF12,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x30 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x34 "CFG_RBUF13,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x34 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x38 "CFG_RBUF14,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x38 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x3C "CFG_RBUF15,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x3C 0.--31. 1. "RBUF,Receive buffers for serializers." rgroup.long 0x1000++0x3 line.long 0x0 "CFG_WFIFOCTL,The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO. If the Write FIFO is to be enabled. it must be enabled prior to taking the McASP out of reset" hexmask.long.word 0x0 17.--31. 1. "RESERVED127," bitfld.long 0x0 16. "WENA,Write FIFO enable bit." "0,1" hexmask.long.byte 0x0 8.--15. 1. "WNUMEVT,Write word count per DMA event [32 bit]. When the Write FIFO has space for at least WNUMEVT words of data then an AXEVT [transmit DMA event] is generated to the host/DMA controller. This value should be set to a non-zero integer multiple of the.." hexmask.long.byte 0x0 0.--7. 1. "WNUMDMA,Write word count per transfer [32 bit words]. Upon a transmit DMA event from the McASP WNUMDMA words are transferred from the Write FIFO to the McASP. This value must equal the number of McASP serializers used as transmitters. This value must be.." rgroup.long 0x1004++0x3 line.long 0x0 "CFG_WFIFOSTS," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED128," hexmask.long.byte 0x0 0.--7. 1. "WLVL,Write level [read-only]. Number of 32 bit words currently in the Write FIFO. 40h = 3 to 64 words currently in Write FIFO from 3h to 40h. FFh = Reserved from 41h to FFh." rgroup.long 0x1008++0x3 line.long 0x0 "CFG_RFIFOCTL,The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO. If the Read FIFO is to be enabled. it must be enabled prior to taking the McASP out of reset" hexmask.long.word 0x0 17.--31. 1. "RESERVED129," bitfld.long 0x0 16. "RENA,Read FIFO enable bit." "0,1" hexmask.long.byte 0x0 8.--15. 1. "RNUMEVT,Read word count per DMA event [32 bit]. When the Read FIFO contains at least RNUMEVT words of data then an AREVT [receive DMA event] is generated to the host/DMA controller. This value should be set to a non-zero integer multiple of the number.." hexmask.long.byte 0x0 0.--7. 1. "RNUMDMA,Read word count per transfer [32 bit words]. Upon a receive DMA event from the McASP the Read FIFO reads RNUMDMA words from the McASP. This value must equal the number of McASP serializers used as receivers. This value must be set prior to.." rgroup.long 0x100C++0x3 line.long 0x0 "CFG_RFIFOSTS," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED130," hexmask.long.byte 0x0 0.--7. 1. "RLVL,Read level [read-only]. Number of 32 bit words currently in the Read FIFO. 40h = 3 to 64 words currently in Read FIFO from 3h to 40h. FFh = Reserved from 41h to FFh." tree.end tree "MCASP2_CFG (MCASP2_CFG)" base ad:0x2B20000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_PID,The revision identification register (PID) contains identification data for the peripheral." hexmask.long 0x0 0.--31. 1. "REV,Identifies revision of peripheral." rgroup.long 0x4++0x3 line.long 0x0 "CFG_PWRIDLESYSCONFIG," hexmask.long 0x0 6.--31. 1. "RESERVED66," hexmask.long.byte 0x0 2.--5. 1. "OTHER,Reserved for future programming." bitfld.long 0x0 0.--1. "IDLEMODE,Power management Configuration of the local target state management mode. By definition target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" rgroup.long 0x10++0x13 line.long 0x0 "CFG_PFUNC,The pin function register (PFUNC) specifies the function of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either a McASP pin or a general-purpose input/output (GPIO) pin. CAUTION: Writing a value other than 0 to reserved bits in.." bitfld.long 0x0 31. "AFSR,Determines if AFSR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 30. "AHCLKR,Determines if AHCLKR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 29. "ACLKR,Determines if ACLKR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 28. "AFSX,Determines if AFSX pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 27. "AHCLKX,Determines if AHCLKX pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 26. "ACLKX,Determines if ACLKX pin functions as McASP or GPIO." "0,1" newline bitfld.long 0x0 25. "AMUTE,Determines if AMUTE pin functions as McASP or GPIO." "0,1" hexmask.long.tbyte 0x0 4.--24. 1. "RESERVED67," hexmask.long.byte 0x0 0.--3. 1. "AXR,Determines if AXRn pin functions as McASP or GPIO." line.long 0x4 "CFG_PDIR,The pin direction register (PDIR) specifies the direction of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either an input or an output pin. Regardless of the pin function register (PFUNC) setting. each PDIR bit must be set to 1 for.." bitfld.long 0x4 31. "AFSR,Determines if AFSR pin functions as an input or output." "0,1" bitfld.long 0x4 30. "AHCLKR,Determines if AHCLKR pin functions as an input or output." "0,1" bitfld.long 0x4 29. "ACLKR,Determines if ACLKR pin functions as an input or output." "0,1" bitfld.long 0x4 28. "AFSX,Determines if AFSX pin functions as an input or output." "0,1" bitfld.long 0x4 27. "AHCLKX,Determines if AHCLKX pin functions as an input or output." "0,1" bitfld.long 0x4 26. "ACLKX,Determines if ACLKX pin functions as an input or output." "0,1" newline bitfld.long 0x4 25. "AMUTE,Determines if AMUTE pin functions as an input or output." "0,1" hexmask.long.tbyte 0x4 4.--24. 1. "RESERVED68," hexmask.long.byte 0x4 0.--3. 1. "AXR,Determines if AXRn pin functions as an input or output." line.long 0x8 "CFG_PDOUT,The pin data output register (PDOUT) holds a value for data out at all times. and may be read back at all times. The value held by PDOUT is not affected by writing to PDIR and PFUNC. However. the data value in PDOUT is driven out onto the McASP.." bitfld.long 0x8 31. "AFSR,Determines drive on AFSR output pin when the corresponding PFUNC[31] and PDIR[31] bits are set to 1." "0,1" bitfld.long 0x8 30. "AHCLKR,Determines drive on AHCLKR output pin when the corresponding PFUNC[30] and PDIR[30] bits are set to 1." "0,1" bitfld.long 0x8 29. "ACLKR,Determines drive on ACLKR output pin when the corresponding PFUNC[29] and PDIR[29] bits are set to 1." "0,1" bitfld.long 0x8 28. "AFSX,Determines drive on AFSX output pin when the corresponding PFUNC[28] and PDIR[28] bits are set to 1." "0,1" bitfld.long 0x8 27. "AHCLKX,Determines drive on AHCLKX output pin when the corresponding PFUNC[27] and PDIR[27] bits are set to 1." "0,1" bitfld.long 0x8 26. "ACLKX,Determines drive on ACLKX output pin when the corresponding PFUNC[26] and PDIR[26] bits are set to 1." "0,1" newline bitfld.long 0x8 25. "AMUTE,Determines drive on AMUTE output pin when the corresponding PFUNC[25] and PDIR[25] bits are set to 1." "0,1" hexmask.long.tbyte 0x8 4.--24. 1. "RESERVED69," hexmask.long.byte 0x8 0.--3. 1. "AXR,Determines drive on AXR[n] output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1." line.long 0xC "CFG_PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins. PDIN allows the actual value of the pin to be read. regardless of the state of PFUNC and PDIR. The value after reset for registers 1 through 15 and 24 through.." bitfld.long 0xC 31. "AFSR,Logic level on AFSR pin." "0,1" bitfld.long 0xC 30. "AHCLKR,Logic level on AHCLKR pin." "0,1" bitfld.long 0xC 29. "ACLKR,Logic level on ACLKR pin." "0,1" bitfld.long 0xC 28. "AFSX,Logic level on AFSX pin." "0,1" bitfld.long 0xC 27. "AHCLKX,Logic level on AHCLKX pin." "0,1" bitfld.long 0xC 26. "ACLKX,Logic level on ACLKX pin." "0,1" newline bitfld.long 0xC 25. "AMUTE,Logic level on AMUTE pin." "0,1" hexmask.long.tbyte 0xC 4.--24. 1. "RESERVED70," hexmask.long.byte 0xC 0.--3. 1. "AXR,Logic level on AXR[n] pin." line.long 0x10 "CFG_PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDCLR bit clears the corresponding bit in PDOUT and. if PFUNC = 1 (GPIO function) and PDIR = 1 (output). drives a logic.." bitfld.long 0x10 31. "AFSR,Allows the corresponding AFSR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 30. "AHCLKR,Allows the corresponding AHCLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 29. "ACLKR,Allows the corresponding ACLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 28. "AFSX,Allows the corresponding AFSX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 27. "AHCLKX,Allows the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 26. "ACLKX,Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" newline bitfld.long 0x10 25. "AMUTE,Allows the corresponding AMUTE bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" hexmask.long.tbyte 0x10 4.--24. 1. "RESERVED71," hexmask.long.byte 0x10 0.--3. 1. "AXR,Allows the corresponding AXR[n] bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." rgroup.long 0x44++0xF line.long 0x0 "CFG_GBLCTL,The global control register (GBLCTL) provides initialization of the transmit and receive sections. The bit fields in GBLCTL are synchronized and latched by the corresponding clocks (ACLKX for bits 12-8 and ACLKR for bits 4-0). Before GBLCTL is.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED73," bitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit." "0,1" bitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit." "0,1" bitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. By clearing then setting this bit the transmit buffer is flushed to an empty state [XDATA = 1]. If XSMRST = 1 XSRCLR = 1 XDATA = 1 and XBUF is not loaded with new data before the start of the next active.." "0,1" bitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit." "0,1" bitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED72," "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit." "0,1" bitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit." "0,1" bitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. By clearing then setting this bit the receive buffer is flushed." "0,1" bitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit." "0,1" bitfld.long 0x0 0. "RCLKRST,Receive high-frequency clock divider reset enable bit." "0,1" line.long 0x4 "CFG_AMUTE,The audio mute control register (AMUTE) controls the McASP audio mute (AMUTE) output pin. The value after reset for register 4 depends on how the pins are being driven." hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED74," bitfld.long 0x4 12. "XDMAERR,If transmit DMA error [XDMAERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 11. "RDMAERR,If receive DMA error [RDMAERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 10. "XCKFAIL,If transmit clock failure [XCKFAIL] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 9. "RCKFAIL,If receive clock failure [RCKFAIL] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 8. "XSYNCERR,If unexpected transmit frame sync error [XSYNCERR] drive AMUTE active enable bit." "0,1" newline bitfld.long 0x4 7. "RSYNCERR,If unexpected receive frame sync error [RSYNCERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 6. "XUNDRN,If transmit underrun error [XUNDRN] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 5. "ROVRN,If receiver overrun error [ROVRN] drive AMUTE active enable bit." "0,1" rbitfld.long 0x4 4. "INSTAT,Determines drive on AXRn pin when PFUNC[n] and PDIR[n] bits are set to 1." "0,1" bitfld.long 0x4 3. "INEN,Drive AMUTE active when AMUTEIN error is active [INSTAT = 1]." "0,1" bitfld.long 0x4 2. "INPOL,Audio mute in [AMUTEIN] polarity select bit." "0,1" newline bitfld.long 0x4 0.--1. "MUTEN,AMUTE pin enable bit [unless overridden by GPIO registers]." "0,1,2,3" line.long 0x8 "CFG_DLBCTL,The digital loopback control register (DLBCTL) controls the internal loopback settings of the McASP in TDM mode." hexmask.long 0x8 4.--31. 1. "RESERVED75," bitfld.long 0x8 2.--3. "MODE,Loopback generator mode bits. Applies only when loopback mode is enabled [DLBEN = 1]." "0,1,2,3" bitfld.long 0x8 1. "ORD,Loopback order bit when loopback mode is enabled [DLBEN = 1]." "0,1" bitfld.long 0x8 0. "DLBEN,Loopback mode enable bit." "0,1" line.long 0xC "CFG_DITCTL,The DIT mode control register (DITCTL) controls DIT operations of the McASP." hexmask.long 0xC 4.--31. 1. "RESERVED77," bitfld.long 0xC 3. "VB,Valid bit for odd time slots [DIT right subframe]." "0,1" bitfld.long 0xC 2. "VA,Valid bit for even time slots [DIT left subframe]." "0,1" rbitfld.long 0xC 1. "RESERVED76," "0,1" bitfld.long 0xC 0. "DITEN,DIT mode enable bit. DITEN should only be changed while the XSMRST bit in GBLCTL is in reset [and for startup XSRCLR also in reset]. However it is not necessary to reset the XCLKRST or XHCLKRST bits in GBLCTL to change DITEN." "0,1" rgroup.long 0x60++0x23 line.long 0x0 "CFG_RGBLCTL,Alias of the global control register (GBLCTL). Writing to the receiver global control register (RGBLCTL) affects only the receive bits of GBLCTL (bits 4-0). Reads from RGBLCTL return the value of GBLCTL. RGBLCTL allows the receiver to be.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED79," rbitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit. A read of this bit returns the XFRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit. A read of this bit returns the XSMRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. A read of this bit returns the XSRCLR bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit. A read of this bit returns the XHCLKRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit. A read of this bit returns the XCLKRST bit value of GBLCTL. Writes have no effect." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED78," "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit. A write to this bit affects the RFRST bit of GBLCTL." "0,1" bitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit. A write to this bit affects the RSMRST bit of GBLCTL." "0,1" bitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. A write to this bit affects the RSRCLR bit of GBLCTL." "0,1" bitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit. A write to this bit affects the RHCLKRST bit of GBLCTL." "0,1" bitfld.long 0x0 0. "RCLKRST,Receive clock divider reset enable bit. A write to this bit affects the RCLKRST bit of GBLCTL." "0,1" line.long 0x4 "CFG_RMASK,The receive format unit bit mask register (RMASK) determines which bits of the received data are masked off and padded with a known value before being read by the CPU or DMA." hexmask.long 0x4 0.--31. 1. "RMASK,Receive data mask n enable bit." line.long 0x8 "CFG_RFMT,The receive bit stream format register (RFMT) configures the receive data format." hexmask.long.word 0x8 18.--31. 1. "RESERVED80," bitfld.long 0x8 16.--17. "RDATDLY,Receive bit delay." "0,1,2,3" bitfld.long 0x8 15. "RRVRS,Receive serial bitstream order." "0,1" bitfld.long 0x8 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word. This field only applies to bits when RMASK[n] = 0." "0,1,2,3" hexmask.long.byte 0x8 8.--12. 1. "RPBIT,RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits. This field only applies when RPAD = 2h." hexmask.long.byte 0x8 4.--7. 1. "RSSZ,Receive slot size." newline bitfld.long 0x8 3. "RBUSEL,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port." "0,1" bitfld.long 0x8 0.--2. "RROT,Right-rotation value for receive rotate right format unit." "0,1,2,3,4,5,6,7" line.long 0xC "CFG_AFSRCTL,The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR)." hexmask.long.word 0xC 16.--31. 1. "RESERVED83," hexmask.long.word 0xC 7.--15. 1. "RMOD,Receive frame sync mode select bits. 1FFh = Reserved from 181h to 1FFh." rbitfld.long 0xC 5.--6. "RESERVED82," "0,1,2,3" bitfld.long 0xC 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period." "0,1" rbitfld.long 0xC 2.--3. "RESERVED81," "0,1,2,3" bitfld.long 0xC 1. "FSRM,Receive frame sync generation select bit." "0,1" newline bitfld.long 0xC 0. "FSRP,Receive frame sync polarity select bit." "0,1" line.long 0x10 "CFG_ACLKRCTL,The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive clock generator." hexmask.long.word 0x10 21.--31. 1. "RESERVED86," bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress" "0,1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress" "0,1" bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "0,1,2,3" hexmask.long.byte 0x10 8.--15. 1. "RESERVED85," newline bitfld.long 0x10 7. "CLKRP,Receive bitstream clock polarity select bit." "0,1" rbitfld.long 0x10 6. "RESERVED84," "0,1" bitfld.long 0x10 5. "CLKRM,Receive bit clock source bit. Note that this bit does not have any effect if ACLKXCTL.ASYNC = 0." "0,1" hexmask.long.byte 0x10 0.--4. 1. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR. Note that this bit does not have any effect if ACLKXCTL.ASYNC = 0." line.long 0x14 "CFG_AHCLKRCTL,The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency master clock (AHCLKR) and the receive clock generator." hexmask.long.word 0x14 21.--31. 1. "RESERVED88," bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "0,1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "0,1" bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "0,1,2,3" bitfld.long 0x14 15. "HCLKRM,Receive high-frequency clock source bit." "0,1" newline bitfld.long 0x14 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit." "0,1" rbitfld.long 0x14 12.--13. "RESERVED87," "0,1,2,3" hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR." line.long 0x18 "CFG_RTDM,The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active." hexmask.long 0x18 0.--31. 1. "RTDMS,Receiver mode during TDM time slot n." line.long 0x1C "CFG_RINTCTL,The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT). When the register bit(s) is set to 1. the occurrence of the enabled McASP condition(s) generates RINT. See the RSTAT register for a.." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED90," bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit." "0,1" rbitfld.long 0x1C 6. "RESERVED89," "0,1" bitfld.long 0x1C 5. "RDATA,Receive data ready interrupt enable bit." "0,1" bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit." "0,1" bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit." "0,1" newline bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit." "0,1" bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame sync interrupt enable bit." "0,1" bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit." "0,1" line.long 0x20 "CFG_RSTAT,The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number. If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the McASP logic has priority.." hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED91," bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR. Allows a single bit to be checked to determine if a receiver error interrupt has occurred." "0,1" bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag. RDMAERR is set when the CPU or DMA reads more serializers through the data port in a given time slot than were programmed as receivers. Causes a receive interrupt [RINT] if this bit is set and RDMAERR in RINTCTL is set." "0,1" bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag. Causes a receive interrupt [RINT] if this bit is set and RSTAFRM in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x20 5. "RDATA,Receive data ready flag. Causes a receive interrupt [RINT] if this bit is set and RDATA in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x20 4. "RLAST,Receive last slot flag. RLAST is set along with RDATA if the current slot is the last slot in a frame. Causes a receive interrupt [RINT] if this bit is set and RLAST in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0.." "0,1" newline rbitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of RSLOT. Allows a single read of RSTAT to determine whether the current TDM time slot is even or odd." "0,1" bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag. RCKFAIL is set when the receive clock failure detection circuit reports an error. Causes a receive interrupt [RINT] if this bit is set and RCKFAIL in RINTCTL is set. This bit is cleared by writing a 1 to this bit." "0,1" bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag. RSYNCERR is set when a new receive frame sync [AFSR] occurs before it is expected. Causes a receive interrupt [RINT] if this bit is set and RSYNCERR in RINTCTL is set. This bit is cleared by writing a 1 to.." "0,1" bitfld.long 0x20 0. "ROVRN,Receiver overrun flag. ROVRN is set when the receive serializer is instructed to transfer data from XRSR to RBUF but the former data in RBUF has not yet been read by the CPU or DMA. Causes a receive interrupt [RINT] if this bit is set and ROVRN.." "0,1" rgroup.long 0x84++0x3 line.long 0x0 "CFG_RSLOT,The current receive TDM time slot register (RSLOT) indicates the current time slot for the receive data frame." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED92," hexmask.long.word 0x0 0.--8. 1. "RSLOTCNT,0-17Fh = Current receive time slot count. Legal values: 0 to 383 [17Fh]. TDM function is not supported for > 32 time slots. However TDM time slot counter may count to 383 when used to receive a DIR block [transferred over TDM format]." rgroup.long 0x88++0x7 line.long 0x0 "CFG_RCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit." hexmask.long.byte 0x0 24.--31. 1. "RCNT,Receive clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 receive high-frequency master clock [AHCLKR] signals and stores the count in RCNT until the next measurement is.." hexmask.long.byte 0x0 16.--23. 1. "RMAX,Receive clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 receive high-frequency master clock [AHCLKR] signals have been received. If the current counter value is greater than.." hexmask.long.byte 0x0 8.--15. 1. "RMIN,Receive clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 receive high-frequency master clock [AHCLKR] signals have been received. If RCNT is less than RMIN after counting 32.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED93," hexmask.long.byte 0x0 0.--3. 1. "RPS,Receive clock check prescaler value." line.long 0x4 "CFG_PIDTCTL,The receiver DMA event control register (PIDTCTL) contains a disable bit for the receiver DMA event. Note for device-specific registers: Accessing PIDTCTL not implemented on a specific device may cause improper operation." hexmask.long 0x4 1.--31. 1. "RESERVED94," bitfld.long 0x4 0. "RDATDMA,Receive data DMA request enable bit. If writing to this bit always write the default value of 0." "0,1" rgroup.long 0xA0++0x23 line.long 0x0 "CFG_XGBLCTL,Alias of the global control register (GBLCTL). Writing to the transmitter global control register (XGBLCTL) affects only the transmit bits of GBLCTL (bits 12-8). Reads from XGBLCTL return the value of GBLCTL. XGBLCTL allows the transmitter to.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED96," bitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit. A write to this bit affects the XFRST bit of GBLCTL." "0,1" bitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit. A write to this bit affects the XSMRST bit of GBLCTL." "0,1" bitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. A write to this bit affects the XSRCLR bit of GBLCTL." "0,1" bitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit. A write to this bit affects the XHCLKRST bit of GBLCTL." "0,1" bitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit. A write to this bit affects the XCLKRST bit of GBLCTL." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED95," "0,1,2,3,4,5,6,7" rbitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit. A read of this bit returns the RFRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit. A read of this bit returns the RSMRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. A read of this bit returns the RSRSCLR bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit. A read of this bit returns the RHCLKRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 0. "RCLKRST,Receive clock divider reset enable bit. A read of this bit returns the RCLKRST bit value of GBLCTL. Writes have no effect." "0,1" line.long 0x4 "CFG_XMASK,The transmit format unit bit mask register (XMASK) determines which bits of the transmitted data are masked off and padded with a known value before being shifted out the McASP." hexmask.long 0x4 0.--31. 1. "XMASK,Transmit data mask n enable bit." line.long 0x8 "CFG_XFMT,The transmit bit stream format register (XFMT) configures the transmit data format." hexmask.long.word 0x8 18.--31. 1. "RESERVED97," bitfld.long 0x8 16.--17. "XDATDLY,Transmit sync bit delay." "0,1,2,3" bitfld.long 0x8 15. "XRVRS,Transmit serial bitstream order." "0,1" bitfld.long 0x8 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK. This field only applies to bits when XMASK[n] = 0." "0,1,2,3" hexmask.long.byte 0x8 8.--12. 1. "XPBIT,XPBIT value determines which bit [as written by the CPU or DMA to XBUF[n]] is used to pad the extra bits before shifting. This field only applies when XPAD = 2h." hexmask.long.byte 0x8 4.--7. 1. "XSSZ,Transmit slot size." newline bitfld.long 0x8 3. "XBUSEL,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port." "0,1" bitfld.long 0x8 0.--2. "XROT,Right-rotation value for transmit rotate right format unit." "0,1,2,3,4,5,6,7" line.long 0xC "CFG_AFSXCTL,The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX)." hexmask.long.word 0xC 16.--31. 1. "RESERVED100," hexmask.long.word 0xC 7.--15. 1. "XMOD,Transmit frame sync mode select bits. 1FFh = Reserved from 181h to 1FFh." rbitfld.long 0xC 5.--6. "RESERVED99," "0,1,2,3" bitfld.long 0xC 4. "FXWID,Transmit frame sync width select bit indicates the width of the transmit frame sync [AFSX] during its active period." "0,1" rbitfld.long 0xC 2.--3. "RESERVED98," "0,1,2,3" bitfld.long 0xC 1. "FSXM,Transmit frame sync generation select bit." "0,1" newline bitfld.long 0xC 0. "FSXP,Transmit frame sync polarity select bit." "0,1" line.long 0x10 "CFG_ACLKXCTL,The transmit clock control register (ACLKXCTL) configures the transmit bit clock (ACLKX) and the transmit clock generator." hexmask.long.word 0x10 21.--31. 1. "RESERVED102," bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress" "0,1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress" "0,1" bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "0,1,2,3" hexmask.long.byte 0x10 8.--15. 1. "RESERVED101," newline bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit." "0,1" bitfld.long 0x10 6. "ASYNC,Transmit/receive operation asynchronous enable bit." "0,1" bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit." "0,1" hexmask.long.byte 0x10 0.--4. 1. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX." line.long 0x14 "CFG_AHCLKXCTL,The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator." hexmask.long.word 0x14 21.--31. 1. "RESERVED104," bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "0,1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "0,1" bitfld.long 0x14 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "0,1,2,3" bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit." "0,1" newline bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit." "0,1" rbitfld.long 0x14 12.--13. "RESERVED103," "0,1,2,3" hexmask.long.word 0x14 0.--11. 1. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX." line.long 0x18 "CFG_XTDM,The transmit TDM time slot register (XTDM) specifies in which TDM time slot the transmitter is active. TDM time slot counter range is extended to 384 slots (to support SPDIF blocks of 384 subframes). XTDM operates modulo 32. that is. XTDMS.." hexmask.long 0x18 0.--31. 1. "XTDMS,Transmitter mode during TDM time slot n." line.long 0x1C "CFG_XINTCTL,The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt (XINT). When the register bit(s) is set to 1. the occurrence of the enabled McASP condition(s) generates XINT. See the XSTAT register for.." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED106," bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit." "0,1" rbitfld.long 0x1C 6. "RESERVED105," "0,1" bitfld.long 0x1C 5. "XDATA,Transmit data ready interrupt enable bit." "0,1" bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit." "0,1" bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit." "0,1" newline bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit." "0,1" bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame sync interrupt enable bit." "0,1" bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit." "0,1" line.long 0x20 "CFG_XSTAT,The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot number. If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the McASP logic has.." hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED107," bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR. Allows a single bit to be checked to determine if a transmitter error interrupt has occurred." "0,1" bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag. XDMAERR is set when the CPU or DMA writes more serializers through the data port in a given time slot than were programmed as transmitters. Causes a transmit interrupt [XINT] if this bit is set and XDMAERR in XINTCTL is.." "0,1" bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag. Causes a transmit interrupt [XINT] if this bit is set and XSTAFRM in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect." "0,1" bitfld.long 0x20 5. "XDATA,Transmit data ready flag. Causes a transmit interrupt [XINT] if this bit is set and XDATA in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect." "0,1" bitfld.long 0x20 4. "XLAST,Transmit last slot flag. XLAST is set along with XDATA if the current slot is the last slot in a frame. Causes a transmit interrupt [XINT] if this bit is set and XLAST in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0.." "0,1" newline rbitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of XSLOT. Allows a single read of XSTAT to determine whether the current TDM time slot is even or odd." "0,1" bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag. XCKFAIL is set when the transmit clock failure detection circuit reports an error. Causes a transmit interrupt [XINT] if this bit is set and XCKFAIL in XINTCTL is set. This bit is cleared by writing a 1 to this bit." "0,1" bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame sync flag. XSYNCERR is set when a new transmit frame sync [AFSX] occurs before it is expected. Causes a transmit interrupt [XINT] if this bit is set and XSYNCERR in XINTCTL is set. This bit is cleared by writing a 1 to.." "0,1" bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from XBUF to XRSR but XBUF has not yet been serviced with new data since the last transfer. Causes a transmit interrupt [XINT] if this bit is.." "0,1" rgroup.long 0xC4++0x3 line.long 0x0 "CFG_XSLOT,The current transmit TDM time slot register (XSLOT) indicates the current time slot for the transmit data frame." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED108," hexmask.long.word 0x0 0.--9. 1. "XSLOTCNT,Current transmit time slot count. Legal values: 0 to 383 [17Fh]. During reset this counter value is 383 so the next count value which is used to encode the first DIT group of data will be 0 and encodes the B preamble. TDM function is not.." rgroup.long 0xC8++0x7 line.long 0x0 "CFG_XCLKCHK,The transmit clock check control register (XCLKCHK) configures the transmit clock failure detection circuit." hexmask.long.byte 0x0 24.--31. 1. "XCNT,Transmit clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 transmit high-frequency master clock [AHCLKX] signals and stores the count in XCNT until the next measurement is.." hexmask.long.byte 0x0 16.--23. 1. "XMAX,Transmit clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high-frequency master clock [AHCLKX] signals have been received. If the current counter value is greater than.." hexmask.long.byte 0x0 8.--15. 1. "XMIN,Transmit clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 transmit high-frequency master clock [AHCLKX] signals have been received. If XCNT is less than XMIN after counting 32.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED109," hexmask.long.byte 0x0 0.--3. 1. "XPS,Transmit clock check prescaler value. Fh = Reserved from 9h to Fh." line.long 0x4 "CFG_XEVTCTL,The transmitter DMA event control register (XEVTCTL) contains a disable bit for the transmit DMA event. Note for device-specific registers: Accessing XEVTCTL not implemented on a specific device may cause improper device operation." hexmask.long 0x4 1.--31. 1. "RESERVED110," bitfld.long 0x4 0. "XDATDMA,Transmit data DMA request enable bit. If writing to this bit always write the default value of 0." "0,1" rgroup.long 0x100++0x5F line.long 0x0 "CFG_DITCSRA0,The DIT left channel status registers (DITCSRA0) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x0 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x4 "CFG_DITCSRA1,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x4 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x8 "CFG_DITCSRA2,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x8 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0xC "CFG_DITCSRA3,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0xC 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x10 "CFG_DITCSRA4,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x10 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x14 "CFG_DITCSRA5,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x14 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x18 "CFG_DITCSRB0,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x18 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x1C "CFG_DITCSRB1,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x1C 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x20 "CFG_DITCSRB2,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x20 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x24 "CFG_DITCSRB3,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x24 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x28 "CFG_DITCSRB4,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x28 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x2C "CFG_DITCSRB5,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x2C 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x30 "CFG_DITUDRA0,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x30 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x34 "CFG_DITUDRA1,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x34 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x38 "CFG_DITUDRA2,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x38 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x3C "CFG_DITUDRA3,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x3C 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x40 "CFG_DITUDRA4,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x40 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x44 "CFG_DITUDRA5,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x44 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x48 "CFG_DITUDRB0,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x48 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x4C "CFG_DITUDRB1,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x4C 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x50 "CFG_DITUDRB2,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x50 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x54 "CFG_DITUDRB3,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x54 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x58 "CFG_DITUDRB4,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x58 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x5C "CFG_DITUDRB5,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x5C 0.--31. 1. "DITUDRB,DIT right channel user data registers." rgroup.long 0x180++0x3F line.long 0x0 "CFG_SRCTL0,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x0 6.--31. 1. "RESERVED111," rbitfld.long 0x0 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x0 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x0 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x0 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x4 "CFG_SRCTL1,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x4 6.--31. 1. "RESERVED112," rbitfld.long 0x4 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x4 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x4 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x4 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x8 "CFG_SRCTL2,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x8 6.--31. 1. "RESERVED113," rbitfld.long 0x8 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x8 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x8 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x8 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0xC "CFG_SRCTL3,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0xC 6.--31. 1. "RESERVED114," rbitfld.long 0xC 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0xC 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0xC 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0xC 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x10 "CFG_SRCTL4,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x10 6.--31. 1. "RESERVED115," rbitfld.long 0x10 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x10 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x10 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x10 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x14 "CFG_SRCTL5,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x14 6.--31. 1. "RESERVED116," rbitfld.long 0x14 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x14 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x14 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x14 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x18 "CFG_SRCTL6,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x18 6.--31. 1. "RESERVED117," rbitfld.long 0x18 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x18 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x18 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x18 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x1C "CFG_SRCTL7,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x1C 6.--31. 1. "RESERVED118," rbitfld.long 0x1C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x1C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x1C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x1C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x20 "CFG_SRCTL8,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x20 6.--31. 1. "RESERVED119," rbitfld.long 0x20 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x20 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x20 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x20 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x24 "CFG_SRCTL9,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x24 6.--31. 1. "RESERVED120," rbitfld.long 0x24 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x24 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x24 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x24 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x28 "CFG_SRCTL10,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x28 6.--31. 1. "RESERVED121," rbitfld.long 0x28 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x28 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x28 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x28 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x2C "CFG_SRCTL11,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x2C 6.--31. 1. "RESERVED122," rbitfld.long 0x2C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x2C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x2C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x2C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x30 "CFG_SRCTL12,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x30 6.--31. 1. "RESERVED123," rbitfld.long 0x30 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x30 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x30 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x30 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x34 "CFG_SRCTL13,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x34 6.--31. 1. "RESERVED124," rbitfld.long 0x34 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x34 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x34 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x34 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x38 "CFG_SRCTL14,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x38 6.--31. 1. "RESERVED125," rbitfld.long 0x38 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x38 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x38 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x38 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x3C "CFG_SRCTL15,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x3C 6.--31. 1. "RESERVED126," rbitfld.long 0x3C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x3C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x3C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x3C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" rgroup.long 0x200++0x3F line.long 0x0 "CFG_XBUF0,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x0 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x4 "CFG_XBUF1,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x4 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x8 "CFG_XBUF2,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x8 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0xC "CFG_XBUF3,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0xC 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x10 "CFG_XBUF4,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x10 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x14 "CFG_XBUF5,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x14 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x18 "CFG_XBUF6,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x18 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x1C "CFG_XBUF7,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x1C 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x20 "CFG_XBUF8,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x20 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x24 "CFG_XBUF9,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x24 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x28 "CFG_XBUF10,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x28 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x2C "CFG_XBUF11,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x2C 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x30 "CFG_XBUF12,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x30 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x34 "CFG_XBUF13,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x34 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x38 "CFG_XBUF14,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x38 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x3C "CFG_XBUF15,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x3C 0.--31. 1. "XBUF,Transmit buffers for serializers." rgroup.long 0x280++0x3F line.long 0x0 "CFG_RBUF0,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x0 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x4 "CFG_RBUF1,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x4 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x8 "CFG_RBUF2,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x8 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0xC "CFG_RBUF3,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0xC 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x10 "CFG_RBUF4,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x10 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x14 "CFG_RBUF5,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x14 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x18 "CFG_RBUF6,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x18 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x1C "CFG_RBUF7,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x1C 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x20 "CFG_RBUF8,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x20 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x24 "CFG_RBUF9,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x24 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x28 "CFG_RBUF10,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x28 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x2C "CFG_RBUF11,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x2C 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x30 "CFG_RBUF12,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x30 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x34 "CFG_RBUF13,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x34 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x38 "CFG_RBUF14,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x38 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x3C "CFG_RBUF15,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x3C 0.--31. 1. "RBUF,Receive buffers for serializers." rgroup.long 0x1000++0x3 line.long 0x0 "CFG_WFIFOCTL,The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO. If the Write FIFO is to be enabled. it must be enabled prior to taking the McASP out of reset" hexmask.long.word 0x0 17.--31. 1. "RESERVED127," bitfld.long 0x0 16. "WENA,Write FIFO enable bit." "0,1" hexmask.long.byte 0x0 8.--15. 1. "WNUMEVT,Write word count per DMA event [32 bit]. When the Write FIFO has space for at least WNUMEVT words of data then an AXEVT [transmit DMA event] is generated to the host/DMA controller. This value should be set to a non-zero integer multiple of the.." hexmask.long.byte 0x0 0.--7. 1. "WNUMDMA,Write word count per transfer [32 bit words]. Upon a transmit DMA event from the McASP WNUMDMA words are transferred from the Write FIFO to the McASP. This value must equal the number of McASP serializers used as transmitters. This value must be.." rgroup.long 0x1004++0x3 line.long 0x0 "CFG_WFIFOSTS," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED128," hexmask.long.byte 0x0 0.--7. 1. "WLVL,Write level [read-only]. Number of 32 bit words currently in the Write FIFO. 40h = 3 to 64 words currently in Write FIFO from 3h to 40h. FFh = Reserved from 41h to FFh." rgroup.long 0x1008++0x3 line.long 0x0 "CFG_RFIFOCTL,The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO. If the Read FIFO is to be enabled. it must be enabled prior to taking the McASP out of reset" hexmask.long.word 0x0 17.--31. 1. "RESERVED129," bitfld.long 0x0 16. "RENA,Read FIFO enable bit." "0,1" hexmask.long.byte 0x0 8.--15. 1. "RNUMEVT,Read word count per DMA event [32 bit]. When the Read FIFO contains at least RNUMEVT words of data then an AREVT [receive DMA event] is generated to the host/DMA controller. This value should be set to a non-zero integer multiple of the number.." hexmask.long.byte 0x0 0.--7. 1. "RNUMDMA,Read word count per transfer [32 bit words]. Upon a receive DMA event from the McASP the Read FIFO reads RNUMDMA words from the McASP. This value must equal the number of McASP serializers used as receivers. This value must be set prior to.." rgroup.long 0x100C++0x3 line.long 0x0 "CFG_RFIFOSTS," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED130," hexmask.long.byte 0x0 0.--7. 1. "RLVL,Read level [read-only]. Number of 32 bit words currently in the Read FIFO. 40h = 3 to 64 words currently in Read FIFO from 3h to 40h. FFh = Reserved from 41h to FFh." tree.end tree "MCASP3_CFG (MCASP3_CFG)" base ad:0x2B30000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_PID,The revision identification register (PID) contains identification data for the peripheral." hexmask.long 0x0 0.--31. 1. "REV,Identifies revision of peripheral." rgroup.long 0x4++0x3 line.long 0x0 "CFG_PWRIDLESYSCONFIG," hexmask.long 0x0 6.--31. 1. "RESERVED66," hexmask.long.byte 0x0 2.--5. 1. "OTHER,Reserved for future programming." bitfld.long 0x0 0.--1. "IDLEMODE,Power management Configuration of the local target state management mode. By definition target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" rgroup.long 0x10++0x13 line.long 0x0 "CFG_PFUNC,The pin function register (PFUNC) specifies the function of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either a McASP pin or a general-purpose input/output (GPIO) pin. CAUTION: Writing a value other than 0 to reserved bits in.." bitfld.long 0x0 31. "AFSR,Determines if AFSR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 30. "AHCLKR,Determines if AHCLKR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 29. "ACLKR,Determines if ACLKR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 28. "AFSX,Determines if AFSX pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 27. "AHCLKX,Determines if AHCLKX pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 26. "ACLKX,Determines if ACLKX pin functions as McASP or GPIO." "0,1" newline bitfld.long 0x0 25. "AMUTE,Determines if AMUTE pin functions as McASP or GPIO." "0,1" hexmask.long.tbyte 0x0 4.--24. 1. "RESERVED67," hexmask.long.byte 0x0 0.--3. 1. "AXR,Determines if AXRn pin functions as McASP or GPIO." line.long 0x4 "CFG_PDIR,The pin direction register (PDIR) specifies the direction of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either an input or an output pin. Regardless of the pin function register (PFUNC) setting. each PDIR bit must be set to 1 for.." bitfld.long 0x4 31. "AFSR,Determines if AFSR pin functions as an input or output." "0,1" bitfld.long 0x4 30. "AHCLKR,Determines if AHCLKR pin functions as an input or output." "0,1" bitfld.long 0x4 29. "ACLKR,Determines if ACLKR pin functions as an input or output." "0,1" bitfld.long 0x4 28. "AFSX,Determines if AFSX pin functions as an input or output." "0,1" bitfld.long 0x4 27. "AHCLKX,Determines if AHCLKX pin functions as an input or output." "0,1" bitfld.long 0x4 26. "ACLKX,Determines if ACLKX pin functions as an input or output." "0,1" newline bitfld.long 0x4 25. "AMUTE,Determines if AMUTE pin functions as an input or output." "0,1" hexmask.long.tbyte 0x4 4.--24. 1. "RESERVED68," hexmask.long.byte 0x4 0.--3. 1. "AXR,Determines if AXRn pin functions as an input or output." line.long 0x8 "CFG_PDOUT,The pin data output register (PDOUT) holds a value for data out at all times. and may be read back at all times. The value held by PDOUT is not affected by writing to PDIR and PFUNC. However. the data value in PDOUT is driven out onto the McASP.." bitfld.long 0x8 31. "AFSR,Determines drive on AFSR output pin when the corresponding PFUNC[31] and PDIR[31] bits are set to 1." "0,1" bitfld.long 0x8 30. "AHCLKR,Determines drive on AHCLKR output pin when the corresponding PFUNC[30] and PDIR[30] bits are set to 1." "0,1" bitfld.long 0x8 29. "ACLKR,Determines drive on ACLKR output pin when the corresponding PFUNC[29] and PDIR[29] bits are set to 1." "0,1" bitfld.long 0x8 28. "AFSX,Determines drive on AFSX output pin when the corresponding PFUNC[28] and PDIR[28] bits are set to 1." "0,1" bitfld.long 0x8 27. "AHCLKX,Determines drive on AHCLKX output pin when the corresponding PFUNC[27] and PDIR[27] bits are set to 1." "0,1" bitfld.long 0x8 26. "ACLKX,Determines drive on ACLKX output pin when the corresponding PFUNC[26] and PDIR[26] bits are set to 1." "0,1" newline bitfld.long 0x8 25. "AMUTE,Determines drive on AMUTE output pin when the corresponding PFUNC[25] and PDIR[25] bits are set to 1." "0,1" hexmask.long.tbyte 0x8 4.--24. 1. "RESERVED69," hexmask.long.byte 0x8 0.--3. 1. "AXR,Determines drive on AXR[n] output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1." line.long 0xC "CFG_PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins. PDIN allows the actual value of the pin to be read. regardless of the state of PFUNC and PDIR. The value after reset for registers 1 through 15 and 24 through.." bitfld.long 0xC 31. "AFSR,Logic level on AFSR pin." "0,1" bitfld.long 0xC 30. "AHCLKR,Logic level on AHCLKR pin." "0,1" bitfld.long 0xC 29. "ACLKR,Logic level on ACLKR pin." "0,1" bitfld.long 0xC 28. "AFSX,Logic level on AFSX pin." "0,1" bitfld.long 0xC 27. "AHCLKX,Logic level on AHCLKX pin." "0,1" bitfld.long 0xC 26. "ACLKX,Logic level on ACLKX pin." "0,1" newline bitfld.long 0xC 25. "AMUTE,Logic level on AMUTE pin." "0,1" hexmask.long.tbyte 0xC 4.--24. 1. "RESERVED70," hexmask.long.byte 0xC 0.--3. 1. "AXR,Logic level on AXR[n] pin." line.long 0x10 "CFG_PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDCLR bit clears the corresponding bit in PDOUT and. if PFUNC = 1 (GPIO function) and PDIR = 1 (output). drives a logic.." bitfld.long 0x10 31. "AFSR,Allows the corresponding AFSR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 30. "AHCLKR,Allows the corresponding AHCLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 29. "ACLKR,Allows the corresponding ACLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 28. "AFSX,Allows the corresponding AFSX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 27. "AHCLKX,Allows the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 26. "ACLKX,Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" newline bitfld.long 0x10 25. "AMUTE,Allows the corresponding AMUTE bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" hexmask.long.tbyte 0x10 4.--24. 1. "RESERVED71," hexmask.long.byte 0x10 0.--3. 1. "AXR,Allows the corresponding AXR[n] bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." rgroup.long 0x44++0xF line.long 0x0 "CFG_GBLCTL,The global control register (GBLCTL) provides initialization of the transmit and receive sections. The bit fields in GBLCTL are synchronized and latched by the corresponding clocks (ACLKX for bits 12-8 and ACLKR for bits 4-0). Before GBLCTL is.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED73," bitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit." "0,1" bitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit." "0,1" bitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. By clearing then setting this bit the transmit buffer is flushed to an empty state [XDATA = 1]. If XSMRST = 1 XSRCLR = 1 XDATA = 1 and XBUF is not loaded with new data before the start of the next active.." "0,1" bitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit." "0,1" bitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED72," "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit." "0,1" bitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit." "0,1" bitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. By clearing then setting this bit the receive buffer is flushed." "0,1" bitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit." "0,1" bitfld.long 0x0 0. "RCLKRST,Receive high-frequency clock divider reset enable bit." "0,1" line.long 0x4 "CFG_AMUTE,The audio mute control register (AMUTE) controls the McASP audio mute (AMUTE) output pin. The value after reset for register 4 depends on how the pins are being driven." hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED74," bitfld.long 0x4 12. "XDMAERR,If transmit DMA error [XDMAERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 11. "RDMAERR,If receive DMA error [RDMAERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 10. "XCKFAIL,If transmit clock failure [XCKFAIL] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 9. "RCKFAIL,If receive clock failure [RCKFAIL] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 8. "XSYNCERR,If unexpected transmit frame sync error [XSYNCERR] drive AMUTE active enable bit." "0,1" newline bitfld.long 0x4 7. "RSYNCERR,If unexpected receive frame sync error [RSYNCERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 6. "XUNDRN,If transmit underrun error [XUNDRN] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 5. "ROVRN,If receiver overrun error [ROVRN] drive AMUTE active enable bit." "0,1" rbitfld.long 0x4 4. "INSTAT,Determines drive on AXRn pin when PFUNC[n] and PDIR[n] bits are set to 1." "0,1" bitfld.long 0x4 3. "INEN,Drive AMUTE active when AMUTEIN error is active [INSTAT = 1]." "0,1" bitfld.long 0x4 2. "INPOL,Audio mute in [AMUTEIN] polarity select bit." "0,1" newline bitfld.long 0x4 0.--1. "MUTEN,AMUTE pin enable bit [unless overridden by GPIO registers]." "0,1,2,3" line.long 0x8 "CFG_DLBCTL,The digital loopback control register (DLBCTL) controls the internal loopback settings of the McASP in TDM mode." hexmask.long 0x8 4.--31. 1. "RESERVED75," bitfld.long 0x8 2.--3. "MODE,Loopback generator mode bits. Applies only when loopback mode is enabled [DLBEN = 1]." "0,1,2,3" bitfld.long 0x8 1. "ORD,Loopback order bit when loopback mode is enabled [DLBEN = 1]." "0,1" bitfld.long 0x8 0. "DLBEN,Loopback mode enable bit." "0,1" line.long 0xC "CFG_DITCTL,The DIT mode control register (DITCTL) controls DIT operations of the McASP." hexmask.long 0xC 4.--31. 1. "RESERVED77," bitfld.long 0xC 3. "VB,Valid bit for odd time slots [DIT right subframe]." "0,1" bitfld.long 0xC 2. "VA,Valid bit for even time slots [DIT left subframe]." "0,1" rbitfld.long 0xC 1. "RESERVED76," "0,1" bitfld.long 0xC 0. "DITEN,DIT mode enable bit. DITEN should only be changed while the XSMRST bit in GBLCTL is in reset [and for startup XSRCLR also in reset]. However it is not necessary to reset the XCLKRST or XHCLKRST bits in GBLCTL to change DITEN." "0,1" rgroup.long 0x60++0x23 line.long 0x0 "CFG_RGBLCTL,Alias of the global control register (GBLCTL). Writing to the receiver global control register (RGBLCTL) affects only the receive bits of GBLCTL (bits 4-0). Reads from RGBLCTL return the value of GBLCTL. RGBLCTL allows the receiver to be.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED79," rbitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit. A read of this bit returns the XFRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit. A read of this bit returns the XSMRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. A read of this bit returns the XSRCLR bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit. A read of this bit returns the XHCLKRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit. A read of this bit returns the XCLKRST bit value of GBLCTL. Writes have no effect." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED78," "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit. A write to this bit affects the RFRST bit of GBLCTL." "0,1" bitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit. A write to this bit affects the RSMRST bit of GBLCTL." "0,1" bitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. A write to this bit affects the RSRCLR bit of GBLCTL." "0,1" bitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit. A write to this bit affects the RHCLKRST bit of GBLCTL." "0,1" bitfld.long 0x0 0. "RCLKRST,Receive clock divider reset enable bit. A write to this bit affects the RCLKRST bit of GBLCTL." "0,1" line.long 0x4 "CFG_RMASK,The receive format unit bit mask register (RMASK) determines which bits of the received data are masked off and padded with a known value before being read by the CPU or DMA." hexmask.long 0x4 0.--31. 1. "RMASK,Receive data mask n enable bit." line.long 0x8 "CFG_RFMT,The receive bit stream format register (RFMT) configures the receive data format." hexmask.long.word 0x8 18.--31. 1. "RESERVED80," bitfld.long 0x8 16.--17. "RDATDLY,Receive bit delay." "0,1,2,3" bitfld.long 0x8 15. "RRVRS,Receive serial bitstream order." "0,1" bitfld.long 0x8 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word. This field only applies to bits when RMASK[n] = 0." "0,1,2,3" hexmask.long.byte 0x8 8.--12. 1. "RPBIT,RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits. This field only applies when RPAD = 2h." hexmask.long.byte 0x8 4.--7. 1. "RSSZ,Receive slot size." newline bitfld.long 0x8 3. "RBUSEL,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port." "0,1" bitfld.long 0x8 0.--2. "RROT,Right-rotation value for receive rotate right format unit." "0,1,2,3,4,5,6,7" line.long 0xC "CFG_AFSRCTL,The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR)." hexmask.long.word 0xC 16.--31. 1. "RESERVED83," hexmask.long.word 0xC 7.--15. 1. "RMOD,Receive frame sync mode select bits. 1FFh = Reserved from 181h to 1FFh." rbitfld.long 0xC 5.--6. "RESERVED82," "0,1,2,3" bitfld.long 0xC 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period." "0,1" rbitfld.long 0xC 2.--3. "RESERVED81," "0,1,2,3" bitfld.long 0xC 1. "FSRM,Receive frame sync generation select bit." "0,1" newline bitfld.long 0xC 0. "FSRP,Receive frame sync polarity select bit." "0,1" line.long 0x10 "CFG_ACLKRCTL,The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive clock generator." hexmask.long.word 0x10 21.--31. 1. "RESERVED86," bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress" "0,1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress" "0,1" bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "0,1,2,3" hexmask.long.byte 0x10 8.--15. 1. "RESERVED85," newline bitfld.long 0x10 7. "CLKRP,Receive bitstream clock polarity select bit." "0,1" rbitfld.long 0x10 6. "RESERVED84," "0,1" bitfld.long 0x10 5. "CLKRM,Receive bit clock source bit. Note that this bit does not have any effect if ACLKXCTL.ASYNC = 0." "0,1" hexmask.long.byte 0x10 0.--4. 1. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR. Note that this bit does not have any effect if ACLKXCTL.ASYNC = 0." line.long 0x14 "CFG_AHCLKRCTL,The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency master clock (AHCLKR) and the receive clock generator." hexmask.long.word 0x14 21.--31. 1. "RESERVED88," bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "0,1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "0,1" bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "0,1,2,3" bitfld.long 0x14 15. "HCLKRM,Receive high-frequency clock source bit." "0,1" newline bitfld.long 0x14 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit." "0,1" rbitfld.long 0x14 12.--13. "RESERVED87," "0,1,2,3" hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR." line.long 0x18 "CFG_RTDM,The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active." hexmask.long 0x18 0.--31. 1. "RTDMS,Receiver mode during TDM time slot n." line.long 0x1C "CFG_RINTCTL,The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT). When the register bit(s) is set to 1. the occurrence of the enabled McASP condition(s) generates RINT. See the RSTAT register for a.." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED90," bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit." "0,1" rbitfld.long 0x1C 6. "RESERVED89," "0,1" bitfld.long 0x1C 5. "RDATA,Receive data ready interrupt enable bit." "0,1" bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit." "0,1" bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit." "0,1" newline bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit." "0,1" bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame sync interrupt enable bit." "0,1" bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit." "0,1" line.long 0x20 "CFG_RSTAT,The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number. If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the McASP logic has priority.." hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED91," bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR. Allows a single bit to be checked to determine if a receiver error interrupt has occurred." "0,1" bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag. RDMAERR is set when the CPU or DMA reads more serializers through the data port in a given time slot than were programmed as receivers. Causes a receive interrupt [RINT] if this bit is set and RDMAERR in RINTCTL is set." "0,1" bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag. Causes a receive interrupt [RINT] if this bit is set and RSTAFRM in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x20 5. "RDATA,Receive data ready flag. Causes a receive interrupt [RINT] if this bit is set and RDATA in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x20 4. "RLAST,Receive last slot flag. RLAST is set along with RDATA if the current slot is the last slot in a frame. Causes a receive interrupt [RINT] if this bit is set and RLAST in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0.." "0,1" newline rbitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of RSLOT. Allows a single read of RSTAT to determine whether the current TDM time slot is even or odd." "0,1" bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag. RCKFAIL is set when the receive clock failure detection circuit reports an error. Causes a receive interrupt [RINT] if this bit is set and RCKFAIL in RINTCTL is set. This bit is cleared by writing a 1 to this bit." "0,1" bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag. RSYNCERR is set when a new receive frame sync [AFSR] occurs before it is expected. Causes a receive interrupt [RINT] if this bit is set and RSYNCERR in RINTCTL is set. This bit is cleared by writing a 1 to.." "0,1" bitfld.long 0x20 0. "ROVRN,Receiver overrun flag. ROVRN is set when the receive serializer is instructed to transfer data from XRSR to RBUF but the former data in RBUF has not yet been read by the CPU or DMA. Causes a receive interrupt [RINT] if this bit is set and ROVRN.." "0,1" rgroup.long 0x84++0x3 line.long 0x0 "CFG_RSLOT,The current receive TDM time slot register (RSLOT) indicates the current time slot for the receive data frame." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED92," hexmask.long.word 0x0 0.--8. 1. "RSLOTCNT,0-17Fh = Current receive time slot count. Legal values: 0 to 383 [17Fh]. TDM function is not supported for > 32 time slots. However TDM time slot counter may count to 383 when used to receive a DIR block [transferred over TDM format]." rgroup.long 0x88++0x7 line.long 0x0 "CFG_RCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit." hexmask.long.byte 0x0 24.--31. 1. "RCNT,Receive clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 receive high-frequency master clock [AHCLKR] signals and stores the count in RCNT until the next measurement is.." hexmask.long.byte 0x0 16.--23. 1. "RMAX,Receive clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 receive high-frequency master clock [AHCLKR] signals have been received. If the current counter value is greater than.." hexmask.long.byte 0x0 8.--15. 1. "RMIN,Receive clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 receive high-frequency master clock [AHCLKR] signals have been received. If RCNT is less than RMIN after counting 32.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED93," hexmask.long.byte 0x0 0.--3. 1. "RPS,Receive clock check prescaler value." line.long 0x4 "CFG_PIDTCTL,The receiver DMA event control register (PIDTCTL) contains a disable bit for the receiver DMA event. Note for device-specific registers: Accessing PIDTCTL not implemented on a specific device may cause improper operation." hexmask.long 0x4 1.--31. 1. "RESERVED94," bitfld.long 0x4 0. "RDATDMA,Receive data DMA request enable bit. If writing to this bit always write the default value of 0." "0,1" rgroup.long 0xA0++0x23 line.long 0x0 "CFG_XGBLCTL,Alias of the global control register (GBLCTL). Writing to the transmitter global control register (XGBLCTL) affects only the transmit bits of GBLCTL (bits 12-8). Reads from XGBLCTL return the value of GBLCTL. XGBLCTL allows the transmitter to.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED96," bitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit. A write to this bit affects the XFRST bit of GBLCTL." "0,1" bitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit. A write to this bit affects the XSMRST bit of GBLCTL." "0,1" bitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. A write to this bit affects the XSRCLR bit of GBLCTL." "0,1" bitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit. A write to this bit affects the XHCLKRST bit of GBLCTL." "0,1" bitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit. A write to this bit affects the XCLKRST bit of GBLCTL." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED95," "0,1,2,3,4,5,6,7" rbitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit. A read of this bit returns the RFRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit. A read of this bit returns the RSMRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. A read of this bit returns the RSRSCLR bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit. A read of this bit returns the RHCLKRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 0. "RCLKRST,Receive clock divider reset enable bit. A read of this bit returns the RCLKRST bit value of GBLCTL. Writes have no effect." "0,1" line.long 0x4 "CFG_XMASK,The transmit format unit bit mask register (XMASK) determines which bits of the transmitted data are masked off and padded with a known value before being shifted out the McASP." hexmask.long 0x4 0.--31. 1. "XMASK,Transmit data mask n enable bit." line.long 0x8 "CFG_XFMT,The transmit bit stream format register (XFMT) configures the transmit data format." hexmask.long.word 0x8 18.--31. 1. "RESERVED97," bitfld.long 0x8 16.--17. "XDATDLY,Transmit sync bit delay." "0,1,2,3" bitfld.long 0x8 15. "XRVRS,Transmit serial bitstream order." "0,1" bitfld.long 0x8 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK. This field only applies to bits when XMASK[n] = 0." "0,1,2,3" hexmask.long.byte 0x8 8.--12. 1. "XPBIT,XPBIT value determines which bit [as written by the CPU or DMA to XBUF[n]] is used to pad the extra bits before shifting. This field only applies when XPAD = 2h." hexmask.long.byte 0x8 4.--7. 1. "XSSZ,Transmit slot size." newline bitfld.long 0x8 3. "XBUSEL,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port." "0,1" bitfld.long 0x8 0.--2. "XROT,Right-rotation value for transmit rotate right format unit." "0,1,2,3,4,5,6,7" line.long 0xC "CFG_AFSXCTL,The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX)." hexmask.long.word 0xC 16.--31. 1. "RESERVED100," hexmask.long.word 0xC 7.--15. 1. "XMOD,Transmit frame sync mode select bits. 1FFh = Reserved from 181h to 1FFh." rbitfld.long 0xC 5.--6. "RESERVED99," "0,1,2,3" bitfld.long 0xC 4. "FXWID,Transmit frame sync width select bit indicates the width of the transmit frame sync [AFSX] during its active period." "0,1" rbitfld.long 0xC 2.--3. "RESERVED98," "0,1,2,3" bitfld.long 0xC 1. "FSXM,Transmit frame sync generation select bit." "0,1" newline bitfld.long 0xC 0. "FSXP,Transmit frame sync polarity select bit." "0,1" line.long 0x10 "CFG_ACLKXCTL,The transmit clock control register (ACLKXCTL) configures the transmit bit clock (ACLKX) and the transmit clock generator." hexmask.long.word 0x10 21.--31. 1. "RESERVED102," bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress" "0,1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress" "0,1" bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "0,1,2,3" hexmask.long.byte 0x10 8.--15. 1. "RESERVED101," newline bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit." "0,1" bitfld.long 0x10 6. "ASYNC,Transmit/receive operation asynchronous enable bit." "0,1" bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit." "0,1" hexmask.long.byte 0x10 0.--4. 1. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX." line.long 0x14 "CFG_AHCLKXCTL,The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator." hexmask.long.word 0x14 21.--31. 1. "RESERVED104," bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "0,1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "0,1" bitfld.long 0x14 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "0,1,2,3" bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit." "0,1" newline bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit." "0,1" rbitfld.long 0x14 12.--13. "RESERVED103," "0,1,2,3" hexmask.long.word 0x14 0.--11. 1. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX." line.long 0x18 "CFG_XTDM,The transmit TDM time slot register (XTDM) specifies in which TDM time slot the transmitter is active. TDM time slot counter range is extended to 384 slots (to support SPDIF blocks of 384 subframes). XTDM operates modulo 32. that is. XTDMS.." hexmask.long 0x18 0.--31. 1. "XTDMS,Transmitter mode during TDM time slot n." line.long 0x1C "CFG_XINTCTL,The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt (XINT). When the register bit(s) is set to 1. the occurrence of the enabled McASP condition(s) generates XINT. See the XSTAT register for.." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED106," bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit." "0,1" rbitfld.long 0x1C 6. "RESERVED105," "0,1" bitfld.long 0x1C 5. "XDATA,Transmit data ready interrupt enable bit." "0,1" bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit." "0,1" bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit." "0,1" newline bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit." "0,1" bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame sync interrupt enable bit." "0,1" bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit." "0,1" line.long 0x20 "CFG_XSTAT,The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot number. If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the McASP logic has.." hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED107," bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR. Allows a single bit to be checked to determine if a transmitter error interrupt has occurred." "0,1" bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag. XDMAERR is set when the CPU or DMA writes more serializers through the data port in a given time slot than were programmed as transmitters. Causes a transmit interrupt [XINT] if this bit is set and XDMAERR in XINTCTL is.." "0,1" bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag. Causes a transmit interrupt [XINT] if this bit is set and XSTAFRM in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect." "0,1" bitfld.long 0x20 5. "XDATA,Transmit data ready flag. Causes a transmit interrupt [XINT] if this bit is set and XDATA in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect." "0,1" bitfld.long 0x20 4. "XLAST,Transmit last slot flag. XLAST is set along with XDATA if the current slot is the last slot in a frame. Causes a transmit interrupt [XINT] if this bit is set and XLAST in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0.." "0,1" newline rbitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of XSLOT. Allows a single read of XSTAT to determine whether the current TDM time slot is even or odd." "0,1" bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag. XCKFAIL is set when the transmit clock failure detection circuit reports an error. Causes a transmit interrupt [XINT] if this bit is set and XCKFAIL in XINTCTL is set. This bit is cleared by writing a 1 to this bit." "0,1" bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame sync flag. XSYNCERR is set when a new transmit frame sync [AFSX] occurs before it is expected. Causes a transmit interrupt [XINT] if this bit is set and XSYNCERR in XINTCTL is set. This bit is cleared by writing a 1 to.." "0,1" bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from XBUF to XRSR but XBUF has not yet been serviced with new data since the last transfer. Causes a transmit interrupt [XINT] if this bit is.." "0,1" rgroup.long 0xC4++0x3 line.long 0x0 "CFG_XSLOT,The current transmit TDM time slot register (XSLOT) indicates the current time slot for the transmit data frame." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED108," hexmask.long.word 0x0 0.--9. 1. "XSLOTCNT,Current transmit time slot count. Legal values: 0 to 383 [17Fh]. During reset this counter value is 383 so the next count value which is used to encode the first DIT group of data will be 0 and encodes the B preamble. TDM function is not.." rgroup.long 0xC8++0x7 line.long 0x0 "CFG_XCLKCHK,The transmit clock check control register (XCLKCHK) configures the transmit clock failure detection circuit." hexmask.long.byte 0x0 24.--31. 1. "XCNT,Transmit clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 transmit high-frequency master clock [AHCLKX] signals and stores the count in XCNT until the next measurement is.." hexmask.long.byte 0x0 16.--23. 1. "XMAX,Transmit clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high-frequency master clock [AHCLKX] signals have been received. If the current counter value is greater than.." hexmask.long.byte 0x0 8.--15. 1. "XMIN,Transmit clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 transmit high-frequency master clock [AHCLKX] signals have been received. If XCNT is less than XMIN after counting 32.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED109," hexmask.long.byte 0x0 0.--3. 1. "XPS,Transmit clock check prescaler value. Fh = Reserved from 9h to Fh." line.long 0x4 "CFG_XEVTCTL,The transmitter DMA event control register (XEVTCTL) contains a disable bit for the transmit DMA event. Note for device-specific registers: Accessing XEVTCTL not implemented on a specific device may cause improper device operation." hexmask.long 0x4 1.--31. 1. "RESERVED110," bitfld.long 0x4 0. "XDATDMA,Transmit data DMA request enable bit. If writing to this bit always write the default value of 0." "0,1" rgroup.long 0x100++0x5F line.long 0x0 "CFG_DITCSRA0,The DIT left channel status registers (DITCSRA0) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x0 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x4 "CFG_DITCSRA1,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x4 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x8 "CFG_DITCSRA2,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x8 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0xC "CFG_DITCSRA3,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0xC 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x10 "CFG_DITCSRA4,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x10 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x14 "CFG_DITCSRA5,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x14 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x18 "CFG_DITCSRB0,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x18 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x1C "CFG_DITCSRB1,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x1C 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x20 "CFG_DITCSRB2,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x20 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x24 "CFG_DITCSRB3,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x24 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x28 "CFG_DITCSRB4,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x28 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x2C "CFG_DITCSRB5,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x2C 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x30 "CFG_DITUDRA0,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x30 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x34 "CFG_DITUDRA1,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x34 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x38 "CFG_DITUDRA2,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x38 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x3C "CFG_DITUDRA3,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x3C 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x40 "CFG_DITUDRA4,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x40 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x44 "CFG_DITUDRA5,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x44 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x48 "CFG_DITUDRB0,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x48 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x4C "CFG_DITUDRB1,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x4C 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x50 "CFG_DITUDRB2,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x50 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x54 "CFG_DITUDRB3,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x54 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x58 "CFG_DITUDRB4,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x58 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x5C "CFG_DITUDRB5,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x5C 0.--31. 1. "DITUDRB,DIT right channel user data registers." rgroup.long 0x180++0x3F line.long 0x0 "CFG_SRCTL0,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x0 6.--31. 1. "RESERVED111," rbitfld.long 0x0 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x0 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x0 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x0 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x4 "CFG_SRCTL1,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x4 6.--31. 1. "RESERVED112," rbitfld.long 0x4 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x4 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x4 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x4 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x8 "CFG_SRCTL2,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x8 6.--31. 1. "RESERVED113," rbitfld.long 0x8 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x8 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x8 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x8 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0xC "CFG_SRCTL3,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0xC 6.--31. 1. "RESERVED114," rbitfld.long 0xC 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0xC 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0xC 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0xC 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x10 "CFG_SRCTL4,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x10 6.--31. 1. "RESERVED115," rbitfld.long 0x10 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x10 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x10 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x10 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x14 "CFG_SRCTL5,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x14 6.--31. 1. "RESERVED116," rbitfld.long 0x14 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x14 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x14 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x14 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x18 "CFG_SRCTL6,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x18 6.--31. 1. "RESERVED117," rbitfld.long 0x18 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x18 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x18 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x18 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x1C "CFG_SRCTL7,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x1C 6.--31. 1. "RESERVED118," rbitfld.long 0x1C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x1C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x1C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x1C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x20 "CFG_SRCTL8,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x20 6.--31. 1. "RESERVED119," rbitfld.long 0x20 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x20 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x20 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x20 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x24 "CFG_SRCTL9,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x24 6.--31. 1. "RESERVED120," rbitfld.long 0x24 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x24 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x24 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x24 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x28 "CFG_SRCTL10,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x28 6.--31. 1. "RESERVED121," rbitfld.long 0x28 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x28 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x28 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x28 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x2C "CFG_SRCTL11,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x2C 6.--31. 1. "RESERVED122," rbitfld.long 0x2C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x2C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x2C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x2C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x30 "CFG_SRCTL12,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x30 6.--31. 1. "RESERVED123," rbitfld.long 0x30 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x30 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x30 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x30 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x34 "CFG_SRCTL13,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x34 6.--31. 1. "RESERVED124," rbitfld.long 0x34 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x34 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x34 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x34 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x38 "CFG_SRCTL14,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x38 6.--31. 1. "RESERVED125," rbitfld.long 0x38 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x38 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x38 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x38 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x3C "CFG_SRCTL15,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x3C 6.--31. 1. "RESERVED126," rbitfld.long 0x3C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x3C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x3C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x3C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" rgroup.long 0x200++0x3F line.long 0x0 "CFG_XBUF0,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x0 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x4 "CFG_XBUF1,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x4 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x8 "CFG_XBUF2,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x8 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0xC "CFG_XBUF3,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0xC 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x10 "CFG_XBUF4,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x10 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x14 "CFG_XBUF5,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x14 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x18 "CFG_XBUF6,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x18 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x1C "CFG_XBUF7,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x1C 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x20 "CFG_XBUF8,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x20 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x24 "CFG_XBUF9,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x24 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x28 "CFG_XBUF10,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x28 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x2C "CFG_XBUF11,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x2C 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x30 "CFG_XBUF12,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x30 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x34 "CFG_XBUF13,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x34 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x38 "CFG_XBUF14,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x38 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x3C "CFG_XBUF15,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x3C 0.--31. 1. "XBUF,Transmit buffers for serializers." rgroup.long 0x280++0x3F line.long 0x0 "CFG_RBUF0,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x0 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x4 "CFG_RBUF1,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x4 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x8 "CFG_RBUF2,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x8 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0xC "CFG_RBUF3,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0xC 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x10 "CFG_RBUF4,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x10 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x14 "CFG_RBUF5,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x14 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x18 "CFG_RBUF6,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x18 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x1C "CFG_RBUF7,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x1C 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x20 "CFG_RBUF8,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x20 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x24 "CFG_RBUF9,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x24 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x28 "CFG_RBUF10,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x28 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x2C "CFG_RBUF11,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x2C 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x30 "CFG_RBUF12,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x30 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x34 "CFG_RBUF13,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x34 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x38 "CFG_RBUF14,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x38 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x3C "CFG_RBUF15,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x3C 0.--31. 1. "RBUF,Receive buffers for serializers." rgroup.long 0x1000++0x3 line.long 0x0 "CFG_WFIFOCTL,The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO. If the Write FIFO is to be enabled. it must be enabled prior to taking the McASP out of reset" hexmask.long.word 0x0 17.--31. 1. "RESERVED127," bitfld.long 0x0 16. "WENA,Write FIFO enable bit." "0,1" hexmask.long.byte 0x0 8.--15. 1. "WNUMEVT,Write word count per DMA event [32 bit]. When the Write FIFO has space for at least WNUMEVT words of data then an AXEVT [transmit DMA event] is generated to the host/DMA controller. This value should be set to a non-zero integer multiple of the.." hexmask.long.byte 0x0 0.--7. 1. "WNUMDMA,Write word count per transfer [32 bit words]. Upon a transmit DMA event from the McASP WNUMDMA words are transferred from the Write FIFO to the McASP. This value must equal the number of McASP serializers used as transmitters. This value must be.." rgroup.long 0x1004++0x3 line.long 0x0 "CFG_WFIFOSTS," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED128," hexmask.long.byte 0x0 0.--7. 1. "WLVL,Write level [read-only]. Number of 32 bit words currently in the Write FIFO. 40h = 3 to 64 words currently in Write FIFO from 3h to 40h. FFh = Reserved from 41h to FFh." rgroup.long 0x1008++0x3 line.long 0x0 "CFG_RFIFOCTL,The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO. If the Read FIFO is to be enabled. it must be enabled prior to taking the McASP out of reset" hexmask.long.word 0x0 17.--31. 1. "RESERVED129," bitfld.long 0x0 16. "RENA,Read FIFO enable bit." "0,1" hexmask.long.byte 0x0 8.--15. 1. "RNUMEVT,Read word count per DMA event [32 bit]. When the Read FIFO contains at least RNUMEVT words of data then an AREVT [receive DMA event] is generated to the host/DMA controller. This value should be set to a non-zero integer multiple of the number.." hexmask.long.byte 0x0 0.--7. 1. "RNUMDMA,Read word count per transfer [32 bit words]. Upon a receive DMA event from the McASP the Read FIFO reads RNUMDMA words from the McASP. This value must equal the number of McASP serializers used as receivers. This value must be set prior to.." rgroup.long 0x100C++0x3 line.long 0x0 "CFG_RFIFOSTS," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED130," hexmask.long.byte 0x0 0.--7. 1. "RLVL,Read level [read-only]. Number of 32 bit words currently in the Read FIFO. 40h = 3 to 64 words currently in Read FIFO from 3h to 40h. FFh = Reserved from 41h to FFh." tree.end tree "MCASP4_CFG (MCASP4_CFG)" base ad:0x2B40000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_PID,The revision identification register (PID) contains identification data for the peripheral." hexmask.long 0x0 0.--31. 1. "REV,Identifies revision of peripheral." rgroup.long 0x4++0x3 line.long 0x0 "CFG_PWRIDLESYSCONFIG," hexmask.long 0x0 6.--31. 1. "RESERVED66," hexmask.long.byte 0x0 2.--5. 1. "OTHER,Reserved for future programming." bitfld.long 0x0 0.--1. "IDLEMODE,Power management Configuration of the local target state management mode. By definition target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" rgroup.long 0x10++0x13 line.long 0x0 "CFG_PFUNC,The pin function register (PFUNC) specifies the function of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either a McASP pin or a general-purpose input/output (GPIO) pin. CAUTION: Writing a value other than 0 to reserved bits in.." bitfld.long 0x0 31. "AFSR,Determines if AFSR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 30. "AHCLKR,Determines if AHCLKR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 29. "ACLKR,Determines if ACLKR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 28. "AFSX,Determines if AFSX pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 27. "AHCLKX,Determines if AHCLKX pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 26. "ACLKX,Determines if ACLKX pin functions as McASP or GPIO." "0,1" newline bitfld.long 0x0 25. "AMUTE,Determines if AMUTE pin functions as McASP or GPIO." "0,1" hexmask.long.tbyte 0x0 4.--24. 1. "RESERVED67," hexmask.long.byte 0x0 0.--3. 1. "AXR,Determines if AXRn pin functions as McASP or GPIO." line.long 0x4 "CFG_PDIR,The pin direction register (PDIR) specifies the direction of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either an input or an output pin. Regardless of the pin function register (PFUNC) setting. each PDIR bit must be set to 1 for.." bitfld.long 0x4 31. "AFSR,Determines if AFSR pin functions as an input or output." "0,1" bitfld.long 0x4 30. "AHCLKR,Determines if AHCLKR pin functions as an input or output." "0,1" bitfld.long 0x4 29. "ACLKR,Determines if ACLKR pin functions as an input or output." "0,1" bitfld.long 0x4 28. "AFSX,Determines if AFSX pin functions as an input or output." "0,1" bitfld.long 0x4 27. "AHCLKX,Determines if AHCLKX pin functions as an input or output." "0,1" bitfld.long 0x4 26. "ACLKX,Determines if ACLKX pin functions as an input or output." "0,1" newline bitfld.long 0x4 25. "AMUTE,Determines if AMUTE pin functions as an input or output." "0,1" hexmask.long.tbyte 0x4 4.--24. 1. "RESERVED68," hexmask.long.byte 0x4 0.--3. 1. "AXR,Determines if AXRn pin functions as an input or output." line.long 0x8 "CFG_PDOUT,The pin data output register (PDOUT) holds a value for data out at all times. and may be read back at all times. The value held by PDOUT is not affected by writing to PDIR and PFUNC. However. the data value in PDOUT is driven out onto the McASP.." bitfld.long 0x8 31. "AFSR,Determines drive on AFSR output pin when the corresponding PFUNC[31] and PDIR[31] bits are set to 1." "0,1" bitfld.long 0x8 30. "AHCLKR,Determines drive on AHCLKR output pin when the corresponding PFUNC[30] and PDIR[30] bits are set to 1." "0,1" bitfld.long 0x8 29. "ACLKR,Determines drive on ACLKR output pin when the corresponding PFUNC[29] and PDIR[29] bits are set to 1." "0,1" bitfld.long 0x8 28. "AFSX,Determines drive on AFSX output pin when the corresponding PFUNC[28] and PDIR[28] bits are set to 1." "0,1" bitfld.long 0x8 27. "AHCLKX,Determines drive on AHCLKX output pin when the corresponding PFUNC[27] and PDIR[27] bits are set to 1." "0,1" bitfld.long 0x8 26. "ACLKX,Determines drive on ACLKX output pin when the corresponding PFUNC[26] and PDIR[26] bits are set to 1." "0,1" newline bitfld.long 0x8 25. "AMUTE,Determines drive on AMUTE output pin when the corresponding PFUNC[25] and PDIR[25] bits are set to 1." "0,1" hexmask.long.tbyte 0x8 4.--24. 1. "RESERVED69," hexmask.long.byte 0x8 0.--3. 1. "AXR,Determines drive on AXR[n] output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1." line.long 0xC "CFG_PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins. PDIN allows the actual value of the pin to be read. regardless of the state of PFUNC and PDIR. The value after reset for registers 1 through 15 and 24 through.." bitfld.long 0xC 31. "AFSR,Logic level on AFSR pin." "0,1" bitfld.long 0xC 30. "AHCLKR,Logic level on AHCLKR pin." "0,1" bitfld.long 0xC 29. "ACLKR,Logic level on ACLKR pin." "0,1" bitfld.long 0xC 28. "AFSX,Logic level on AFSX pin." "0,1" bitfld.long 0xC 27. "AHCLKX,Logic level on AHCLKX pin." "0,1" bitfld.long 0xC 26. "ACLKX,Logic level on ACLKX pin." "0,1" newline bitfld.long 0xC 25. "AMUTE,Logic level on AMUTE pin." "0,1" hexmask.long.tbyte 0xC 4.--24. 1. "RESERVED70," hexmask.long.byte 0xC 0.--3. 1. "AXR,Logic level on AXR[n] pin." line.long 0x10 "CFG_PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDCLR bit clears the corresponding bit in PDOUT and. if PFUNC = 1 (GPIO function) and PDIR = 1 (output). drives a logic.." bitfld.long 0x10 31. "AFSR,Allows the corresponding AFSR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 30. "AHCLKR,Allows the corresponding AHCLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 29. "ACLKR,Allows the corresponding ACLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 28. "AFSX,Allows the corresponding AFSX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 27. "AHCLKX,Allows the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 26. "ACLKX,Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" newline bitfld.long 0x10 25. "AMUTE,Allows the corresponding AMUTE bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" hexmask.long.tbyte 0x10 4.--24. 1. "RESERVED71," hexmask.long.byte 0x10 0.--3. 1. "AXR,Allows the corresponding AXR[n] bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." rgroup.long 0x44++0xF line.long 0x0 "CFG_GBLCTL,The global control register (GBLCTL) provides initialization of the transmit and receive sections. The bit fields in GBLCTL are synchronized and latched by the corresponding clocks (ACLKX for bits 12-8 and ACLKR for bits 4-0). Before GBLCTL is.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED73," bitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit." "0,1" bitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit." "0,1" bitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. By clearing then setting this bit the transmit buffer is flushed to an empty state [XDATA = 1]. If XSMRST = 1 XSRCLR = 1 XDATA = 1 and XBUF is not loaded with new data before the start of the next active.." "0,1" bitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit." "0,1" bitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED72," "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit." "0,1" bitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit." "0,1" bitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. By clearing then setting this bit the receive buffer is flushed." "0,1" bitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit." "0,1" bitfld.long 0x0 0. "RCLKRST,Receive high-frequency clock divider reset enable bit." "0,1" line.long 0x4 "CFG_AMUTE,The audio mute control register (AMUTE) controls the McASP audio mute (AMUTE) output pin. The value after reset for register 4 depends on how the pins are being driven." hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED74," bitfld.long 0x4 12. "XDMAERR,If transmit DMA error [XDMAERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 11. "RDMAERR,If receive DMA error [RDMAERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 10. "XCKFAIL,If transmit clock failure [XCKFAIL] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 9. "RCKFAIL,If receive clock failure [RCKFAIL] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 8. "XSYNCERR,If unexpected transmit frame sync error [XSYNCERR] drive AMUTE active enable bit." "0,1" newline bitfld.long 0x4 7. "RSYNCERR,If unexpected receive frame sync error [RSYNCERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 6. "XUNDRN,If transmit underrun error [XUNDRN] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 5. "ROVRN,If receiver overrun error [ROVRN] drive AMUTE active enable bit." "0,1" rbitfld.long 0x4 4. "INSTAT,Determines drive on AXRn pin when PFUNC[n] and PDIR[n] bits are set to 1." "0,1" bitfld.long 0x4 3. "INEN,Drive AMUTE active when AMUTEIN error is active [INSTAT = 1]." "0,1" bitfld.long 0x4 2. "INPOL,Audio mute in [AMUTEIN] polarity select bit." "0,1" newline bitfld.long 0x4 0.--1. "MUTEN,AMUTE pin enable bit [unless overridden by GPIO registers]." "0,1,2,3" line.long 0x8 "CFG_DLBCTL,The digital loopback control register (DLBCTL) controls the internal loopback settings of the McASP in TDM mode." hexmask.long 0x8 4.--31. 1. "RESERVED75," bitfld.long 0x8 2.--3. "MODE,Loopback generator mode bits. Applies only when loopback mode is enabled [DLBEN = 1]." "0,1,2,3" bitfld.long 0x8 1. "ORD,Loopback order bit when loopback mode is enabled [DLBEN = 1]." "0,1" bitfld.long 0x8 0. "DLBEN,Loopback mode enable bit." "0,1" line.long 0xC "CFG_DITCTL,The DIT mode control register (DITCTL) controls DIT operations of the McASP." hexmask.long 0xC 4.--31. 1. "RESERVED77," bitfld.long 0xC 3. "VB,Valid bit for odd time slots [DIT right subframe]." "0,1" bitfld.long 0xC 2. "VA,Valid bit for even time slots [DIT left subframe]." "0,1" rbitfld.long 0xC 1. "RESERVED76," "0,1" bitfld.long 0xC 0. "DITEN,DIT mode enable bit. DITEN should only be changed while the XSMRST bit in GBLCTL is in reset [and for startup XSRCLR also in reset]. However it is not necessary to reset the XCLKRST or XHCLKRST bits in GBLCTL to change DITEN." "0,1" rgroup.long 0x60++0x23 line.long 0x0 "CFG_RGBLCTL,Alias of the global control register (GBLCTL). Writing to the receiver global control register (RGBLCTL) affects only the receive bits of GBLCTL (bits 4-0). Reads from RGBLCTL return the value of GBLCTL. RGBLCTL allows the receiver to be.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED79," rbitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit. A read of this bit returns the XFRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit. A read of this bit returns the XSMRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. A read of this bit returns the XSRCLR bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit. A read of this bit returns the XHCLKRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit. A read of this bit returns the XCLKRST bit value of GBLCTL. Writes have no effect." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED78," "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit. A write to this bit affects the RFRST bit of GBLCTL." "0,1" bitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit. A write to this bit affects the RSMRST bit of GBLCTL." "0,1" bitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. A write to this bit affects the RSRCLR bit of GBLCTL." "0,1" bitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit. A write to this bit affects the RHCLKRST bit of GBLCTL." "0,1" bitfld.long 0x0 0. "RCLKRST,Receive clock divider reset enable bit. A write to this bit affects the RCLKRST bit of GBLCTL." "0,1" line.long 0x4 "CFG_RMASK,The receive format unit bit mask register (RMASK) determines which bits of the received data are masked off and padded with a known value before being read by the CPU or DMA." hexmask.long 0x4 0.--31. 1. "RMASK,Receive data mask n enable bit." line.long 0x8 "CFG_RFMT,The receive bit stream format register (RFMT) configures the receive data format." hexmask.long.word 0x8 18.--31. 1. "RESERVED80," bitfld.long 0x8 16.--17. "RDATDLY,Receive bit delay." "0,1,2,3" bitfld.long 0x8 15. "RRVRS,Receive serial bitstream order." "0,1" bitfld.long 0x8 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word. This field only applies to bits when RMASK[n] = 0." "0,1,2,3" hexmask.long.byte 0x8 8.--12. 1. "RPBIT,RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits. This field only applies when RPAD = 2h." hexmask.long.byte 0x8 4.--7. 1. "RSSZ,Receive slot size." newline bitfld.long 0x8 3. "RBUSEL,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port." "0,1" bitfld.long 0x8 0.--2. "RROT,Right-rotation value for receive rotate right format unit." "0,1,2,3,4,5,6,7" line.long 0xC "CFG_AFSRCTL,The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR)." hexmask.long.word 0xC 16.--31. 1. "RESERVED83," hexmask.long.word 0xC 7.--15. 1. "RMOD,Receive frame sync mode select bits. 1FFh = Reserved from 181h to 1FFh." rbitfld.long 0xC 5.--6. "RESERVED82," "0,1,2,3" bitfld.long 0xC 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period." "0,1" rbitfld.long 0xC 2.--3. "RESERVED81," "0,1,2,3" bitfld.long 0xC 1. "FSRM,Receive frame sync generation select bit." "0,1" newline bitfld.long 0xC 0. "FSRP,Receive frame sync polarity select bit." "0,1" line.long 0x10 "CFG_ACLKRCTL,The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive clock generator." hexmask.long.word 0x10 21.--31. 1. "RESERVED86," bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress" "0,1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress" "0,1" bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "0,1,2,3" hexmask.long.byte 0x10 8.--15. 1. "RESERVED85," newline bitfld.long 0x10 7. "CLKRP,Receive bitstream clock polarity select bit." "0,1" rbitfld.long 0x10 6. "RESERVED84," "0,1" bitfld.long 0x10 5. "CLKRM,Receive bit clock source bit. Note that this bit does not have any effect if ACLKXCTL.ASYNC = 0." "0,1" hexmask.long.byte 0x10 0.--4. 1. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR. Note that this bit does not have any effect if ACLKXCTL.ASYNC = 0." line.long 0x14 "CFG_AHCLKRCTL,The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency master clock (AHCLKR) and the receive clock generator." hexmask.long.word 0x14 21.--31. 1. "RESERVED88," bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "0,1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "0,1" bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "0,1,2,3" bitfld.long 0x14 15. "HCLKRM,Receive high-frequency clock source bit." "0,1" newline bitfld.long 0x14 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit." "0,1" rbitfld.long 0x14 12.--13. "RESERVED87," "0,1,2,3" hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR." line.long 0x18 "CFG_RTDM,The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active." hexmask.long 0x18 0.--31. 1. "RTDMS,Receiver mode during TDM time slot n." line.long 0x1C "CFG_RINTCTL,The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT). When the register bit(s) is set to 1. the occurrence of the enabled McASP condition(s) generates RINT. See the RSTAT register for a.." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED90," bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit." "0,1" rbitfld.long 0x1C 6. "RESERVED89," "0,1" bitfld.long 0x1C 5. "RDATA,Receive data ready interrupt enable bit." "0,1" bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit." "0,1" bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit." "0,1" newline bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit." "0,1" bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame sync interrupt enable bit." "0,1" bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit." "0,1" line.long 0x20 "CFG_RSTAT,The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number. If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the McASP logic has priority.." hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED91," bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR. Allows a single bit to be checked to determine if a receiver error interrupt has occurred." "0,1" bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag. RDMAERR is set when the CPU or DMA reads more serializers through the data port in a given time slot than were programmed as receivers. Causes a receive interrupt [RINT] if this bit is set and RDMAERR in RINTCTL is set." "0,1" bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag. Causes a receive interrupt [RINT] if this bit is set and RSTAFRM in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x20 5. "RDATA,Receive data ready flag. Causes a receive interrupt [RINT] if this bit is set and RDATA in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x20 4. "RLAST,Receive last slot flag. RLAST is set along with RDATA if the current slot is the last slot in a frame. Causes a receive interrupt [RINT] if this bit is set and RLAST in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0.." "0,1" newline rbitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of RSLOT. Allows a single read of RSTAT to determine whether the current TDM time slot is even or odd." "0,1" bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag. RCKFAIL is set when the receive clock failure detection circuit reports an error. Causes a receive interrupt [RINT] if this bit is set and RCKFAIL in RINTCTL is set. This bit is cleared by writing a 1 to this bit." "0,1" bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag. RSYNCERR is set when a new receive frame sync [AFSR] occurs before it is expected. Causes a receive interrupt [RINT] if this bit is set and RSYNCERR in RINTCTL is set. This bit is cleared by writing a 1 to.." "0,1" bitfld.long 0x20 0. "ROVRN,Receiver overrun flag. ROVRN is set when the receive serializer is instructed to transfer data from XRSR to RBUF but the former data in RBUF has not yet been read by the CPU or DMA. Causes a receive interrupt [RINT] if this bit is set and ROVRN.." "0,1" rgroup.long 0x84++0x3 line.long 0x0 "CFG_RSLOT,The current receive TDM time slot register (RSLOT) indicates the current time slot for the receive data frame." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED92," hexmask.long.word 0x0 0.--8. 1. "RSLOTCNT,0-17Fh = Current receive time slot count. Legal values: 0 to 383 [17Fh]. TDM function is not supported for > 32 time slots. However TDM time slot counter may count to 383 when used to receive a DIR block [transferred over TDM format]." rgroup.long 0x88++0x7 line.long 0x0 "CFG_RCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit." hexmask.long.byte 0x0 24.--31. 1. "RCNT,Receive clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 receive high-frequency master clock [AHCLKR] signals and stores the count in RCNT until the next measurement is.." hexmask.long.byte 0x0 16.--23. 1. "RMAX,Receive clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 receive high-frequency master clock [AHCLKR] signals have been received. If the current counter value is greater than.." hexmask.long.byte 0x0 8.--15. 1. "RMIN,Receive clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 receive high-frequency master clock [AHCLKR] signals have been received. If RCNT is less than RMIN after counting 32.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED93," hexmask.long.byte 0x0 0.--3. 1. "RPS,Receive clock check prescaler value." line.long 0x4 "CFG_PIDTCTL,The receiver DMA event control register (PIDTCTL) contains a disable bit for the receiver DMA event. Note for device-specific registers: Accessing PIDTCTL not implemented on a specific device may cause improper operation." hexmask.long 0x4 1.--31. 1. "RESERVED94," bitfld.long 0x4 0. "RDATDMA,Receive data DMA request enable bit. If writing to this bit always write the default value of 0." "0,1" rgroup.long 0xA0++0x23 line.long 0x0 "CFG_XGBLCTL,Alias of the global control register (GBLCTL). Writing to the transmitter global control register (XGBLCTL) affects only the transmit bits of GBLCTL (bits 12-8). Reads from XGBLCTL return the value of GBLCTL. XGBLCTL allows the transmitter to.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED96," bitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit. A write to this bit affects the XFRST bit of GBLCTL." "0,1" bitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit. A write to this bit affects the XSMRST bit of GBLCTL." "0,1" bitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. A write to this bit affects the XSRCLR bit of GBLCTL." "0,1" bitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit. A write to this bit affects the XHCLKRST bit of GBLCTL." "0,1" bitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit. A write to this bit affects the XCLKRST bit of GBLCTL." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED95," "0,1,2,3,4,5,6,7" rbitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit. A read of this bit returns the RFRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit. A read of this bit returns the RSMRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. A read of this bit returns the RSRSCLR bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit. A read of this bit returns the RHCLKRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 0. "RCLKRST,Receive clock divider reset enable bit. A read of this bit returns the RCLKRST bit value of GBLCTL. Writes have no effect." "0,1" line.long 0x4 "CFG_XMASK,The transmit format unit bit mask register (XMASK) determines which bits of the transmitted data are masked off and padded with a known value before being shifted out the McASP." hexmask.long 0x4 0.--31. 1. "XMASK,Transmit data mask n enable bit." line.long 0x8 "CFG_XFMT,The transmit bit stream format register (XFMT) configures the transmit data format." hexmask.long.word 0x8 18.--31. 1. "RESERVED97," bitfld.long 0x8 16.--17. "XDATDLY,Transmit sync bit delay." "0,1,2,3" bitfld.long 0x8 15. "XRVRS,Transmit serial bitstream order." "0,1" bitfld.long 0x8 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK. This field only applies to bits when XMASK[n] = 0." "0,1,2,3" hexmask.long.byte 0x8 8.--12. 1. "XPBIT,XPBIT value determines which bit [as written by the CPU or DMA to XBUF[n]] is used to pad the extra bits before shifting. This field only applies when XPAD = 2h." hexmask.long.byte 0x8 4.--7. 1. "XSSZ,Transmit slot size." newline bitfld.long 0x8 3. "XBUSEL,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port." "0,1" bitfld.long 0x8 0.--2. "XROT,Right-rotation value for transmit rotate right format unit." "0,1,2,3,4,5,6,7" line.long 0xC "CFG_AFSXCTL,The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX)." hexmask.long.word 0xC 16.--31. 1. "RESERVED100," hexmask.long.word 0xC 7.--15. 1. "XMOD,Transmit frame sync mode select bits. 1FFh = Reserved from 181h to 1FFh." rbitfld.long 0xC 5.--6. "RESERVED99," "0,1,2,3" bitfld.long 0xC 4. "FXWID,Transmit frame sync width select bit indicates the width of the transmit frame sync [AFSX] during its active period." "0,1" rbitfld.long 0xC 2.--3. "RESERVED98," "0,1,2,3" bitfld.long 0xC 1. "FSXM,Transmit frame sync generation select bit." "0,1" newline bitfld.long 0xC 0. "FSXP,Transmit frame sync polarity select bit." "0,1" line.long 0x10 "CFG_ACLKXCTL,The transmit clock control register (ACLKXCTL) configures the transmit bit clock (ACLKX) and the transmit clock generator." hexmask.long.word 0x10 21.--31. 1. "RESERVED102," bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress" "0,1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress" "0,1" bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "0,1,2,3" hexmask.long.byte 0x10 8.--15. 1. "RESERVED101," newline bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit." "0,1" bitfld.long 0x10 6. "ASYNC,Transmit/receive operation asynchronous enable bit." "0,1" bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit." "0,1" hexmask.long.byte 0x10 0.--4. 1. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX." line.long 0x14 "CFG_AHCLKXCTL,The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator." hexmask.long.word 0x14 21.--31. 1. "RESERVED104," bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "0,1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "0,1" bitfld.long 0x14 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "0,1,2,3" bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit." "0,1" newline bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit." "0,1" rbitfld.long 0x14 12.--13. "RESERVED103," "0,1,2,3" hexmask.long.word 0x14 0.--11. 1. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX." line.long 0x18 "CFG_XTDM,The transmit TDM time slot register (XTDM) specifies in which TDM time slot the transmitter is active. TDM time slot counter range is extended to 384 slots (to support SPDIF blocks of 384 subframes). XTDM operates modulo 32. that is. XTDMS.." hexmask.long 0x18 0.--31. 1. "XTDMS,Transmitter mode during TDM time slot n." line.long 0x1C "CFG_XINTCTL,The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt (XINT). When the register bit(s) is set to 1. the occurrence of the enabled McASP condition(s) generates XINT. See the XSTAT register for.." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED106," bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit." "0,1" rbitfld.long 0x1C 6. "RESERVED105," "0,1" bitfld.long 0x1C 5. "XDATA,Transmit data ready interrupt enable bit." "0,1" bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit." "0,1" bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit." "0,1" newline bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit." "0,1" bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame sync interrupt enable bit." "0,1" bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit." "0,1" line.long 0x20 "CFG_XSTAT,The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot number. If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the McASP logic has.." hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED107," bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR. Allows a single bit to be checked to determine if a transmitter error interrupt has occurred." "0,1" bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag. XDMAERR is set when the CPU or DMA writes more serializers through the data port in a given time slot than were programmed as transmitters. Causes a transmit interrupt [XINT] if this bit is set and XDMAERR in XINTCTL is.." "0,1" bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag. Causes a transmit interrupt [XINT] if this bit is set and XSTAFRM in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect." "0,1" bitfld.long 0x20 5. "XDATA,Transmit data ready flag. Causes a transmit interrupt [XINT] if this bit is set and XDATA in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect." "0,1" bitfld.long 0x20 4. "XLAST,Transmit last slot flag. XLAST is set along with XDATA if the current slot is the last slot in a frame. Causes a transmit interrupt [XINT] if this bit is set and XLAST in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0.." "0,1" newline rbitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of XSLOT. Allows a single read of XSTAT to determine whether the current TDM time slot is even or odd." "0,1" bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag. XCKFAIL is set when the transmit clock failure detection circuit reports an error. Causes a transmit interrupt [XINT] if this bit is set and XCKFAIL in XINTCTL is set. This bit is cleared by writing a 1 to this bit." "0,1" bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame sync flag. XSYNCERR is set when a new transmit frame sync [AFSX] occurs before it is expected. Causes a transmit interrupt [XINT] if this bit is set and XSYNCERR in XINTCTL is set. This bit is cleared by writing a 1 to.." "0,1" bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from XBUF to XRSR but XBUF has not yet been serviced with new data since the last transfer. Causes a transmit interrupt [XINT] if this bit is.." "0,1" rgroup.long 0xC4++0x3 line.long 0x0 "CFG_XSLOT,The current transmit TDM time slot register (XSLOT) indicates the current time slot for the transmit data frame." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED108," hexmask.long.word 0x0 0.--9. 1. "XSLOTCNT,Current transmit time slot count. Legal values: 0 to 383 [17Fh]. During reset this counter value is 383 so the next count value which is used to encode the first DIT group of data will be 0 and encodes the B preamble. TDM function is not.." rgroup.long 0xC8++0x7 line.long 0x0 "CFG_XCLKCHK,The transmit clock check control register (XCLKCHK) configures the transmit clock failure detection circuit." hexmask.long.byte 0x0 24.--31. 1. "XCNT,Transmit clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 transmit high-frequency master clock [AHCLKX] signals and stores the count in XCNT until the next measurement is.." hexmask.long.byte 0x0 16.--23. 1. "XMAX,Transmit clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high-frequency master clock [AHCLKX] signals have been received. If the current counter value is greater than.." hexmask.long.byte 0x0 8.--15. 1. "XMIN,Transmit clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 transmit high-frequency master clock [AHCLKX] signals have been received. If XCNT is less than XMIN after counting 32.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED109," hexmask.long.byte 0x0 0.--3. 1. "XPS,Transmit clock check prescaler value. Fh = Reserved from 9h to Fh." line.long 0x4 "CFG_XEVTCTL,The transmitter DMA event control register (XEVTCTL) contains a disable bit for the transmit DMA event. Note for device-specific registers: Accessing XEVTCTL not implemented on a specific device may cause improper device operation." hexmask.long 0x4 1.--31. 1. "RESERVED110," bitfld.long 0x4 0. "XDATDMA,Transmit data DMA request enable bit. If writing to this bit always write the default value of 0." "0,1" rgroup.long 0x100++0x5F line.long 0x0 "CFG_DITCSRA0,The DIT left channel status registers (DITCSRA0) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x0 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x4 "CFG_DITCSRA1,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x4 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x8 "CFG_DITCSRA2,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x8 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0xC "CFG_DITCSRA3,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0xC 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x10 "CFG_DITCSRA4,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x10 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x14 "CFG_DITCSRA5,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x14 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x18 "CFG_DITCSRB0,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x18 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x1C "CFG_DITCSRB1,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x1C 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x20 "CFG_DITCSRB2,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x20 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x24 "CFG_DITCSRB3,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x24 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x28 "CFG_DITCSRB4,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x28 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x2C "CFG_DITCSRB5,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x2C 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x30 "CFG_DITUDRA0,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x30 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x34 "CFG_DITUDRA1,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x34 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x38 "CFG_DITUDRA2,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x38 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x3C "CFG_DITUDRA3,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x3C 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x40 "CFG_DITUDRA4,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x40 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x44 "CFG_DITUDRA5,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x44 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x48 "CFG_DITUDRB0,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x48 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x4C "CFG_DITUDRB1,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x4C 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x50 "CFG_DITUDRB2,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x50 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x54 "CFG_DITUDRB3,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x54 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x58 "CFG_DITUDRB4,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x58 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x5C "CFG_DITUDRB5,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x5C 0.--31. 1. "DITUDRB,DIT right channel user data registers." rgroup.long 0x180++0x3F line.long 0x0 "CFG_SRCTL0,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x0 6.--31. 1. "RESERVED111," rbitfld.long 0x0 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x0 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x0 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x0 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x4 "CFG_SRCTL1,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x4 6.--31. 1. "RESERVED112," rbitfld.long 0x4 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x4 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x4 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x4 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x8 "CFG_SRCTL2,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x8 6.--31. 1. "RESERVED113," rbitfld.long 0x8 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x8 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x8 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x8 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0xC "CFG_SRCTL3,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0xC 6.--31. 1. "RESERVED114," rbitfld.long 0xC 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0xC 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0xC 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0xC 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x10 "CFG_SRCTL4,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x10 6.--31. 1. "RESERVED115," rbitfld.long 0x10 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x10 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x10 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x10 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x14 "CFG_SRCTL5,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x14 6.--31. 1. "RESERVED116," rbitfld.long 0x14 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x14 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x14 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x14 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x18 "CFG_SRCTL6,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x18 6.--31. 1. "RESERVED117," rbitfld.long 0x18 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x18 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x18 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x18 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x1C "CFG_SRCTL7,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x1C 6.--31. 1. "RESERVED118," rbitfld.long 0x1C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x1C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x1C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x1C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x20 "CFG_SRCTL8,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x20 6.--31. 1. "RESERVED119," rbitfld.long 0x20 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x20 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x20 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x20 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x24 "CFG_SRCTL9,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x24 6.--31. 1. "RESERVED120," rbitfld.long 0x24 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x24 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x24 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x24 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x28 "CFG_SRCTL10,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x28 6.--31. 1. "RESERVED121," rbitfld.long 0x28 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x28 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x28 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x28 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x2C "CFG_SRCTL11,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x2C 6.--31. 1. "RESERVED122," rbitfld.long 0x2C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x2C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x2C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x2C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x30 "CFG_SRCTL12,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x30 6.--31. 1. "RESERVED123," rbitfld.long 0x30 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x30 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x30 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x30 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x34 "CFG_SRCTL13,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x34 6.--31. 1. "RESERVED124," rbitfld.long 0x34 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x34 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x34 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x34 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x38 "CFG_SRCTL14,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x38 6.--31. 1. "RESERVED125," rbitfld.long 0x38 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x38 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x38 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x38 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x3C "CFG_SRCTL15,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x3C 6.--31. 1. "RESERVED126," rbitfld.long 0x3C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x3C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x3C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x3C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" rgroup.long 0x200++0x3F line.long 0x0 "CFG_XBUF0,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x0 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x4 "CFG_XBUF1,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x4 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x8 "CFG_XBUF2,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x8 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0xC "CFG_XBUF3,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0xC 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x10 "CFG_XBUF4,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x10 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x14 "CFG_XBUF5,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x14 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x18 "CFG_XBUF6,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x18 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x1C "CFG_XBUF7,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x1C 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x20 "CFG_XBUF8,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x20 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x24 "CFG_XBUF9,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x24 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x28 "CFG_XBUF10,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x28 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x2C "CFG_XBUF11,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x2C 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x30 "CFG_XBUF12,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x30 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x34 "CFG_XBUF13,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x34 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x38 "CFG_XBUF14,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x38 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x3C "CFG_XBUF15,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x3C 0.--31. 1. "XBUF,Transmit buffers for serializers." rgroup.long 0x280++0x3F line.long 0x0 "CFG_RBUF0,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x0 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x4 "CFG_RBUF1,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x4 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x8 "CFG_RBUF2,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x8 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0xC "CFG_RBUF3,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0xC 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x10 "CFG_RBUF4,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x10 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x14 "CFG_RBUF5,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x14 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x18 "CFG_RBUF6,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x18 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x1C "CFG_RBUF7,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x1C 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x20 "CFG_RBUF8,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x20 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x24 "CFG_RBUF9,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x24 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x28 "CFG_RBUF10,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x28 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x2C "CFG_RBUF11,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x2C 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x30 "CFG_RBUF12,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x30 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x34 "CFG_RBUF13,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x34 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x38 "CFG_RBUF14,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x38 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x3C "CFG_RBUF15,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x3C 0.--31. 1. "RBUF,Receive buffers for serializers." rgroup.long 0x1000++0x3 line.long 0x0 "CFG_WFIFOCTL,The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO. If the Write FIFO is to be enabled. it must be enabled prior to taking the McASP out of reset" hexmask.long.word 0x0 17.--31. 1. "RESERVED127," bitfld.long 0x0 16. "WENA,Write FIFO enable bit." "0,1" hexmask.long.byte 0x0 8.--15. 1. "WNUMEVT,Write word count per DMA event [32 bit]. When the Write FIFO has space for at least WNUMEVT words of data then an AXEVT [transmit DMA event] is generated to the host/DMA controller. This value should be set to a non-zero integer multiple of the.." hexmask.long.byte 0x0 0.--7. 1. "WNUMDMA,Write word count per transfer [32 bit words]. Upon a transmit DMA event from the McASP WNUMDMA words are transferred from the Write FIFO to the McASP. This value must equal the number of McASP serializers used as transmitters. This value must be.." rgroup.long 0x1004++0x3 line.long 0x0 "CFG_WFIFOSTS," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED128," hexmask.long.byte 0x0 0.--7. 1. "WLVL,Write level [read-only]. Number of 32 bit words currently in the Write FIFO. 40h = 3 to 64 words currently in Write FIFO from 3h to 40h. FFh = Reserved from 41h to FFh." rgroup.long 0x1008++0x3 line.long 0x0 "CFG_RFIFOCTL,The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO. If the Read FIFO is to be enabled. it must be enabled prior to taking the McASP out of reset" hexmask.long.word 0x0 17.--31. 1. "RESERVED129," bitfld.long 0x0 16. "RENA,Read FIFO enable bit." "0,1" hexmask.long.byte 0x0 8.--15. 1. "RNUMEVT,Read word count per DMA event [32 bit]. When the Read FIFO contains at least RNUMEVT words of data then an AREVT [receive DMA event] is generated to the host/DMA controller. This value should be set to a non-zero integer multiple of the number.." hexmask.long.byte 0x0 0.--7. 1. "RNUMDMA,Read word count per transfer [32 bit words]. Upon a receive DMA event from the McASP the Read FIFO reads RNUMDMA words from the McASP. This value must equal the number of McASP serializers used as receivers. This value must be set prior to.." rgroup.long 0x100C++0x3 line.long 0x0 "CFG_RFIFOSTS," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED130," hexmask.long.byte 0x0 0.--7. 1. "RLVL,Read level [read-only]. Number of 32 bit words currently in the Read FIFO. 40h = 3 to 64 words currently in Read FIFO from 3h to 40h. FFh = Reserved from 41h to FFh." tree.end tree.end tree "MCSPI" base ad:0x0 tree "MCSPI0_CFG (MCSPI0_CFG)" base ad:0x2100000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_HL_REV,IP Revision Identifier (X.Y.R)" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" newline hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any)." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" newline bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "CFG_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "CFG_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" rgroup.long 0x110++0x2B line.long 0x0 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1" bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1" line.long 0x4 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0" rbitfld.long 0x4 0. "RESETDONE,Internal Reset Monitoring" "0,1" line.long 0x8 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x8 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1" bitfld.long 0x8 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" newline bitfld.long 0x8 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1" bitfld.long 0x8 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" newline bitfld.long 0x8 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1" bitfld.long 0x8 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1" newline bitfld.long 0x8 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1" bitfld.long 0x8 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1" bitfld.long 0x8 7. "RESERVED,Reads returns 0" "0,1" newline bitfld.long 0x8 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1" bitfld.long 0x8 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1" bitfld.long 0x8 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1" newline bitfld.long 0x8 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1" bitfld.long 0x8 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1" bitfld.long 0x8 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1" newline bitfld.long 0x8 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1" line.long 0xC "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0xC 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0xC 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1" bitfld.long 0xC 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" newline bitfld.long 0xC 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0xC 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1" bitfld.long 0xC 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1" newline bitfld.long 0xC 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1" bitfld.long 0xC 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0xC 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1" newline bitfld.long 0xC 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 7. "RESERVED,Reads return 0" "0,1" newline bitfld.long 0xC 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1" newline bitfld.long 0xC 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1" newline bitfld.long 0xC 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1" line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x14 11. "SSB,Set status bit" "0,1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1" newline bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1" bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1" bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1" newline bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" newline bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1" newline bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1" bitfld.long 0x18 2. "MS,Master/ Slave" "0,1" newline bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1" bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1" line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3" bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x1C 18. "IS,Input Select" "0,1" bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x1C 7.--11. 1. "WL,SPI word length" bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x1C 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1" line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x24 0. "EN,Channel Enable" "0,1" line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x28 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" rgroup.long 0x140++0xF line.long 0x0 "CFG_CH1CONF,This register is dedicated to the configuration of the channel." bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" rgroup.long 0x154++0xF line.long 0x0 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" rgroup.long 0x168++0xF line.long 0x0 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" rgroup.long 0x17C++0x7 line.long 0x0 "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." rgroup.long 0x1A0++0x3 line.long 0x0 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." tree.end tree "MCSPI1_CFG (MCSPI1_CFG)" base ad:0x2110000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_HL_REV,IP Revision Identifier (X.Y.R)" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" newline hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any)." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" newline bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "CFG_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "CFG_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" rgroup.long 0x110++0x2B line.long 0x0 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1" bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1" line.long 0x4 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0" rbitfld.long 0x4 0. "RESETDONE,Internal Reset Monitoring" "0,1" line.long 0x8 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x8 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1" bitfld.long 0x8 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" newline bitfld.long 0x8 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1" bitfld.long 0x8 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" newline bitfld.long 0x8 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1" bitfld.long 0x8 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1" newline bitfld.long 0x8 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1" bitfld.long 0x8 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1" bitfld.long 0x8 7. "RESERVED,Reads returns 0" "0,1" newline bitfld.long 0x8 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1" bitfld.long 0x8 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1" bitfld.long 0x8 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1" newline bitfld.long 0x8 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1" bitfld.long 0x8 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1" bitfld.long 0x8 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1" newline bitfld.long 0x8 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1" line.long 0xC "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0xC 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0xC 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1" bitfld.long 0xC 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" newline bitfld.long 0xC 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0xC 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1" bitfld.long 0xC 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1" newline bitfld.long 0xC 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1" bitfld.long 0xC 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0xC 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1" newline bitfld.long 0xC 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 7. "RESERVED,Reads return 0" "0,1" newline bitfld.long 0xC 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1" newline bitfld.long 0xC 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1" newline bitfld.long 0xC 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1" line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x14 11. "SSB,Set status bit" "0,1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1" newline bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1" bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1" bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1" newline bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" newline bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1" newline bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1" bitfld.long 0x18 2. "MS,Master/ Slave" "0,1" newline bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1" bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1" line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3" bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x1C 18. "IS,Input Select" "0,1" bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x1C 7.--11. 1. "WL,SPI word length" bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x1C 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1" line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x24 0. "EN,Channel Enable" "0,1" line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x28 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" rgroup.long 0x140++0xF line.long 0x0 "CFG_CH1CONF,This register is dedicated to the configuration of the channel." bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" rgroup.long 0x154++0xF line.long 0x0 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" rgroup.long 0x168++0xF line.long 0x0 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" rgroup.long 0x17C++0x7 line.long 0x0 "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." rgroup.long 0x1A0++0x3 line.long 0x0 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." tree.end tree "MCSPI2_CFG (MCSPI2_CFG)" base ad:0x2120000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_HL_REV,IP Revision Identifier (X.Y.R)" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" newline hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any)." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" newline bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "CFG_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "CFG_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" rgroup.long 0x110++0x2B line.long 0x0 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1" bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1" line.long 0x4 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0" rbitfld.long 0x4 0. "RESETDONE,Internal Reset Monitoring" "0,1" line.long 0x8 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x8 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1" bitfld.long 0x8 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" newline bitfld.long 0x8 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1" bitfld.long 0x8 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" newline bitfld.long 0x8 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1" bitfld.long 0x8 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1" newline bitfld.long 0x8 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1" bitfld.long 0x8 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1" bitfld.long 0x8 7. "RESERVED,Reads returns 0" "0,1" newline bitfld.long 0x8 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1" bitfld.long 0x8 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1" bitfld.long 0x8 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1" newline bitfld.long 0x8 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1" bitfld.long 0x8 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1" bitfld.long 0x8 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1" newline bitfld.long 0x8 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1" line.long 0xC "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0xC 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0xC 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1" bitfld.long 0xC 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" newline bitfld.long 0xC 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0xC 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1" bitfld.long 0xC 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1" newline bitfld.long 0xC 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1" bitfld.long 0xC 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0xC 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1" newline bitfld.long 0xC 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 7. "RESERVED,Reads return 0" "0,1" newline bitfld.long 0xC 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1" newline bitfld.long 0xC 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1" newline bitfld.long 0xC 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1" line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x14 11. "SSB,Set status bit" "0,1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1" newline bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1" bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1" bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1" newline bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" newline bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1" newline bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1" bitfld.long 0x18 2. "MS,Master/ Slave" "0,1" newline bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1" bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1" line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3" bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x1C 18. "IS,Input Select" "0,1" bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x1C 7.--11. 1. "WL,SPI word length" bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x1C 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1" line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x24 0. "EN,Channel Enable" "0,1" line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x28 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" rgroup.long 0x140++0xF line.long 0x0 "CFG_CH1CONF,This register is dedicated to the configuration of the channel." bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" rgroup.long 0x154++0xF line.long 0x0 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" rgroup.long 0x168++0xF line.long 0x0 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" rgroup.long 0x17C++0x7 line.long 0x0 "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." rgroup.long 0x1A0++0x3 line.long 0x0 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." tree.end tree "MCSPI3_CFG (MCSPI3_CFG)" base ad:0x2130000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_HL_REV,IP Revision Identifier (X.Y.R)" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" newline hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any)." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" newline bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "CFG_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "CFG_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" rgroup.long 0x110++0x2B line.long 0x0 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1" bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1" line.long 0x4 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0" rbitfld.long 0x4 0. "RESETDONE,Internal Reset Monitoring" "0,1" line.long 0x8 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x8 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1" bitfld.long 0x8 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" newline bitfld.long 0x8 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1" bitfld.long 0x8 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" newline bitfld.long 0x8 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1" bitfld.long 0x8 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1" newline bitfld.long 0x8 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1" bitfld.long 0x8 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1" bitfld.long 0x8 7. "RESERVED,Reads returns 0" "0,1" newline bitfld.long 0x8 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1" bitfld.long 0x8 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1" bitfld.long 0x8 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1" newline bitfld.long 0x8 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1" bitfld.long 0x8 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1" bitfld.long 0x8 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1" newline bitfld.long 0x8 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1" line.long 0xC "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0xC 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0xC 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1" bitfld.long 0xC 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" newline bitfld.long 0xC 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0xC 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1" bitfld.long 0xC 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1" newline bitfld.long 0xC 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1" bitfld.long 0xC 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0xC 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1" newline bitfld.long 0xC 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 7. "RESERVED,Reads return 0" "0,1" newline bitfld.long 0xC 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1" newline bitfld.long 0xC 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1" newline bitfld.long 0xC 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1" line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x14 11. "SSB,Set status bit" "0,1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1" newline bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1" bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1" bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1" newline bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" newline bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1" newline bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1" bitfld.long 0x18 2. "MS,Master/ Slave" "0,1" newline bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1" bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1" line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3" bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x1C 18. "IS,Input Select" "0,1" bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x1C 7.--11. 1. "WL,SPI word length" bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x1C 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1" line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x24 0. "EN,Channel Enable" "0,1" line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x28 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" rgroup.long 0x140++0xF line.long 0x0 "CFG_CH1CONF,This register is dedicated to the configuration of the channel." bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" rgroup.long 0x154++0xF line.long 0x0 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" rgroup.long 0x168++0xF line.long 0x0 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" rgroup.long 0x17C++0x7 line.long 0x0 "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." rgroup.long 0x1A0++0x3 line.long 0x0 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." tree.end tree "MCSPI4_CFG (MCSPI4_CFG)" base ad:0x2140000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_HL_REV,IP Revision Identifier (X.Y.R)" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" newline hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any)." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" newline bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "CFG_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "CFG_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" rgroup.long 0x110++0x2B line.long 0x0 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1" bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1" line.long 0x4 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0" rbitfld.long 0x4 0. "RESETDONE,Internal Reset Monitoring" "0,1" line.long 0x8 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x8 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1" bitfld.long 0x8 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" newline bitfld.long 0x8 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1" bitfld.long 0x8 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" newline bitfld.long 0x8 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1" bitfld.long 0x8 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1" newline bitfld.long 0x8 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1" bitfld.long 0x8 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1" bitfld.long 0x8 7. "RESERVED,Reads returns 0" "0,1" newline bitfld.long 0x8 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1" bitfld.long 0x8 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1" bitfld.long 0x8 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1" newline bitfld.long 0x8 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1" bitfld.long 0x8 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1" bitfld.long 0x8 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1" newline bitfld.long 0x8 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1" line.long 0xC "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0xC 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0xC 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1" bitfld.long 0xC 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" newline bitfld.long 0xC 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0xC 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1" bitfld.long 0xC 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1" newline bitfld.long 0xC 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1" bitfld.long 0xC 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0xC 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1" newline bitfld.long 0xC 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 7. "RESERVED,Reads return 0" "0,1" newline bitfld.long 0xC 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1" newline bitfld.long 0xC 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1" newline bitfld.long 0xC 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1" line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x14 11. "SSB,Set status bit" "0,1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1" newline bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1" bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1" bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1" newline bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" newline bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1" newline bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1" bitfld.long 0x18 2. "MS,Master/ Slave" "0,1" newline bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1" bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1" line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3" bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x1C 18. "IS,Input Select" "0,1" bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x1C 7.--11. 1. "WL,SPI word length" bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x1C 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1" line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x24 0. "EN,Channel Enable" "0,1" line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x28 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" rgroup.long 0x140++0xF line.long 0x0 "CFG_CH1CONF,This register is dedicated to the configuration of the channel." bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" rgroup.long 0x154++0xF line.long 0x0 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" rgroup.long 0x168++0xF line.long 0x0 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" rgroup.long 0x17C++0x7 line.long 0x0 "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." rgroup.long 0x1A0++0x3 line.long 0x0 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." tree.end tree "MCSPI5_CFG (MCSPI5_CFG)" base ad:0x2150000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_HL_REV,IP Revision Identifier (X.Y.R)" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" newline hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any)." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" newline bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "CFG_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "CFG_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" rgroup.long 0x110++0x2B line.long 0x0 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1" bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1" line.long 0x4 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0" rbitfld.long 0x4 0. "RESETDONE,Internal Reset Monitoring" "0,1" line.long 0x8 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x8 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1" bitfld.long 0x8 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" newline bitfld.long 0x8 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1" bitfld.long 0x8 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" newline bitfld.long 0x8 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1" bitfld.long 0x8 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1" newline bitfld.long 0x8 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1" bitfld.long 0x8 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1" bitfld.long 0x8 7. "RESERVED,Reads returns 0" "0,1" newline bitfld.long 0x8 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1" bitfld.long 0x8 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1" bitfld.long 0x8 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1" newline bitfld.long 0x8 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1" bitfld.long 0x8 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1" bitfld.long 0x8 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1" newline bitfld.long 0x8 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1" line.long 0xC "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0xC 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0xC 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1" bitfld.long 0xC 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" newline bitfld.long 0xC 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0xC 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1" bitfld.long 0xC 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1" newline bitfld.long 0xC 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1" bitfld.long 0xC 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0xC 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1" newline bitfld.long 0xC 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 7. "RESERVED,Reads return 0" "0,1" newline bitfld.long 0xC 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1" newline bitfld.long 0xC 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1" newline bitfld.long 0xC 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1" line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x14 11. "SSB,Set status bit" "0,1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1" newline bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1" bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1" bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1" newline bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" newline bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1" newline bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1" bitfld.long 0x18 2. "MS,Master/ Slave" "0,1" newline bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1" bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1" line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3" bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x1C 18. "IS,Input Select" "0,1" bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x1C 7.--11. 1. "WL,SPI word length" bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x1C 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1" line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x24 0. "EN,Channel Enable" "0,1" line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x28 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" rgroup.long 0x140++0xF line.long 0x0 "CFG_CH1CONF,This register is dedicated to the configuration of the channel." bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" rgroup.long 0x154++0xF line.long 0x0 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" rgroup.long 0x168++0xF line.long 0x0 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" rgroup.long 0x17C++0x7 line.long 0x0 "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." rgroup.long 0x1A0++0x3 line.long 0x0 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." tree.end tree "MCSPI6_CFG (MCSPI6_CFG)" base ad:0x2160000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_HL_REV,IP Revision Identifier (X.Y.R)" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" newline hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any)." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" newline bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "CFG_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "CFG_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" rgroup.long 0x110++0x2B line.long 0x0 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1" bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1" line.long 0x4 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0" rbitfld.long 0x4 0. "RESETDONE,Internal Reset Monitoring" "0,1" line.long 0x8 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x8 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1" bitfld.long 0x8 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" newline bitfld.long 0x8 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1" bitfld.long 0x8 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" newline bitfld.long 0x8 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1" bitfld.long 0x8 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1" newline bitfld.long 0x8 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1" bitfld.long 0x8 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1" bitfld.long 0x8 7. "RESERVED,Reads returns 0" "0,1" newline bitfld.long 0x8 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1" bitfld.long 0x8 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1" bitfld.long 0x8 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1" newline bitfld.long 0x8 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1" bitfld.long 0x8 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1" bitfld.long 0x8 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1" newline bitfld.long 0x8 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1" line.long 0xC "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0xC 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0xC 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1" bitfld.long 0xC 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" newline bitfld.long 0xC 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0xC 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1" bitfld.long 0xC 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1" newline bitfld.long 0xC 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1" bitfld.long 0xC 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0xC 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1" newline bitfld.long 0xC 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 7. "RESERVED,Reads return 0" "0,1" newline bitfld.long 0xC 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1" newline bitfld.long 0xC 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1" newline bitfld.long 0xC 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1" line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x14 11. "SSB,Set status bit" "0,1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1" newline bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1" bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1" bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1" newline bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" newline bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1" newline bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1" bitfld.long 0x18 2. "MS,Master/ Slave" "0,1" newline bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1" bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1" line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3" bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x1C 18. "IS,Input Select" "0,1" bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x1C 7.--11. 1. "WL,SPI word length" bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x1C 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1" line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x24 0. "EN,Channel Enable" "0,1" line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x28 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" rgroup.long 0x140++0xF line.long 0x0 "CFG_CH1CONF,This register is dedicated to the configuration of the channel." bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" rgroup.long 0x154++0xF line.long 0x0 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" rgroup.long 0x168++0xF line.long 0x0 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" rgroup.long 0x17C++0x7 line.long 0x0 "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." rgroup.long 0x1A0++0x3 line.long 0x0 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." tree.end tree "MCSPI7_CFG (MCSPI7_CFG)" base ad:0x2170000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_HL_REV,IP Revision Identifier (X.Y.R)" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" newline hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any)." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" newline bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "CFG_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "CFG_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" rgroup.long 0x110++0x2B line.long 0x0 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1" bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1" line.long 0x4 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0" rbitfld.long 0x4 0. "RESETDONE,Internal Reset Monitoring" "0,1" line.long 0x8 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x8 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1" bitfld.long 0x8 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" newline bitfld.long 0x8 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1" bitfld.long 0x8 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" newline bitfld.long 0x8 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1" bitfld.long 0x8 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1" newline bitfld.long 0x8 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1" bitfld.long 0x8 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1" bitfld.long 0x8 7. "RESERVED,Reads returns 0" "0,1" newline bitfld.long 0x8 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1" bitfld.long 0x8 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1" bitfld.long 0x8 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1" newline bitfld.long 0x8 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1" bitfld.long 0x8 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1" bitfld.long 0x8 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1" newline bitfld.long 0x8 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1" line.long 0xC "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0xC 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0xC 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1" bitfld.long 0xC 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" newline bitfld.long 0xC 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0xC 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1" bitfld.long 0xC 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1" newline bitfld.long 0xC 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1" bitfld.long 0xC 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0xC 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1" newline bitfld.long 0xC 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 7. "RESERVED,Reads return 0" "0,1" newline bitfld.long 0xC 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1" newline bitfld.long 0xC 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1" newline bitfld.long 0xC 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1" line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x14 11. "SSB,Set status bit" "0,1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1" newline bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1" bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1" bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1" newline bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" newline bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1" newline bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1" bitfld.long 0x18 2. "MS,Master/ Slave" "0,1" newline bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1" bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1" line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3" bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x1C 18. "IS,Input Select" "0,1" bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x1C 7.--11. 1. "WL,SPI word length" bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x1C 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1" line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x24 0. "EN,Channel Enable" "0,1" line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x28 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" rgroup.long 0x140++0xF line.long 0x0 "CFG_CH1CONF,This register is dedicated to the configuration of the channel." bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" rgroup.long 0x154++0xF line.long 0x0 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" rgroup.long 0x168++0xF line.long 0x0 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" rgroup.long 0x17C++0x7 line.long 0x0 "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." rgroup.long 0x1A0++0x3 line.long 0x0 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." tree.end tree.end tree "MCU" base ad:0x0 tree "MCU_adc12fc" tree "MCU_adc12fc_16ffc0" tree "MCU_adc12fc_16ffc0_ADC (MCU_adc12fc_16ffc0_ADC)" base ad:0x40200000 rgroup.long 0x0++0x3 line.long 0x0 "ADCREGS_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x38++0xB line.long 0x0 "ADCREGS_DMAENABLE_SET,The DMAENABLE_SET register allows the enabling of DMA requests" bitfld.long 0x0 1. "ENABLE1,enable DMA reguest FIFO1" "0,1" bitfld.long 0x0 0. "ENABLE0,enable DMA reguest FIFO0" "0,1" line.long 0x4 "ADCREGS_DMAENABLE_CLR,The DMAENABLE_CLR register allows the disabling of DMA requests" bitfld.long 0x4 1. "ENABLE1,clears the enable of the DMA reguest FIFO1. Disables DMA request when writing 1" "0,1" bitfld.long 0x4 0. "ENABLE0,clears the enable of the DMA reguest FIFO0. Disables DMA request when writing 1" "0,1" line.long 0x8 "ADCREGS_CONTROL,Controls various parameters of the cotroller state." bitfld.long 0x8 11. "HI_MID_SEL,Functional safety debug mode. =1 choose ADCREFP =0 VMID reference input to ADC" "0,1" bitfld.long 0x8 10. "HI_MID_EN,Functional safety debug mode. enable fixed reference to ADC for testing" "0,1" newline bitfld.long 0x8 9. "HW_PREEMPT,1 steps are preempted" "0,1" bitfld.long 0x8 8. "HW_MAP,1 = hw events enabled" "?,1: hw events enabled" newline bitfld.long 0x8 4. "PD,AFE powered down" "0,1" bitfld.long 0x8 3. "BIAS_SEL,AFE select bias control" "0,1" newline bitfld.long 0x8 1. "STEP_ID_EN,writing 1 will store the stepid number with the captured adc data in the fifo" "0,1" bitfld.long 0x8 0. "MODULE_ENABLE,ADC12_SS module enable bit. After programming all the configuration and step enable registers write a 1 to this bit to start conversion. Writing a 0 will disable the module after the current conversion. Before turning on again the.." "0,1" rgroup.long 0x44++0x3 line.long 0x0 "ADCREGS_SEQUENCER_STAT,SW can read this register to find out the currently" bitfld.long 0x0 8. "GPADC_BUSY,Monitor the AFE internal calibration busy bit" "0,1" bitfld.long 0x0 6. "MEM_INIT_DONE,status of ram initialization 1= ram initialization to 0 after reset is done." "?,1: ram initialization to 0 after reset is done" newline bitfld.long 0x0 5. "FSM_BUSY,status of fsm 1= conversion in progress" "?,1: conversion in progress" hexmask.long.byte 0x0 0.--4. 1. "STEP_IDLE,10000 = idle 000000 -> 01111 corresponds to step 1 -> step 16" rgroup.long 0x48++0x3 line.long 0x0 "ADCREGS_RANGE,This feature requires the range check interrupt bit to be enabled first." hexmask.long.word 0x0 16.--27. 1. "HIRANGE,If the sampled data is > value then interrupt is generated" hexmask.long.word 0x0 0.--11. 1. "LOWRANGE,If the sampled data is < value then interrupt is generated" rgroup.long 0x50++0x7 line.long 0x0 "ADCREGS_MISC,Spare inputs of the AFE are driven by this register. spare outputs from the AFE are read." hexmask.long.byte 0x0 8.--11. 1. "AFE_SPARE_OUT,Spare outputs from AFE" hexmask.long.byte 0x0 0.--3. 1. "AFE_SPARE_IN,Spare inputs to AFE" line.long 0x4 "ADCREGS_STEPENABLE,Contains the enable bit for each step in the sequencer." bitfld.long 0x4 16. "STEP16,Enable step" "0,1" bitfld.long 0x4 15. "STEP15,Enable step" "0,1" newline bitfld.long 0x4 14. "STEP14,Enable step" "0,1" bitfld.long 0x4 13. "STEP13,Enable step" "0,1" newline bitfld.long 0x4 12. "STEP12,Enable step" "0,1" bitfld.long 0x4 11. "STEP11,Enable step" "0,1" newline bitfld.long 0x4 10. "STEP10,Enable step" "0,1" bitfld.long 0x4 9. "STEP9,Enable step" "0,1" newline bitfld.long 0x4 8. "STEP8,Enable step" "0,1" bitfld.long 0x4 7. "STEP7,Enable step" "0,1" newline bitfld.long 0x4 6. "STEP6,Enable step" "0,1" bitfld.long 0x4 5. "STEP5,Enable step" "0,1" newline bitfld.long 0x4 4. "STEP4,Enable step" "0,1" bitfld.long 0x4 3. "STEP3,Enable step" "0,1" newline bitfld.long 0x4 2. "STEP2,Enable step" "0,1" bitfld.long 0x4 1. "STEP1,Enable step" "0,1" rgroup.long 0xE4++0x3 line.long 0x0 "ADCREGS_FIFO0WC,FIFO word count status" hexmask.long.word 0x0 0.--8. 1. "NUMWDS,number of words in the FIFO" rgroup.long 0xE8++0x7 line.long 0x0 "ADCREGS_FIFO0THRESHOLD,FIFO threshold" hexmask.long.byte 0x0 0.--7. 1. "THRESHOLD,Program the desired FIFO0 data sample level minus 1 to reach before generating interrupt to CPU" line.long 0x4 "ADCREGS_FIFO0DMAREQ,dma request." hexmask.long.byte 0x4 0.--7. 1. "DMAREQLEVEL,Number of words minus 1 in FIFO0 before generating a DMA request" rgroup.long 0xF0++0x3 line.long 0x0 "ADCREGS_FIFO1WC,FIFO word count status" hexmask.long.word 0x0 0.--8. 1. "NUMWDS,number of words in the FIFO" rgroup.long 0xF4++0x7 line.long 0x0 "ADCREGS_FIFO1THRESHOLD,FIFO threshold" hexmask.long.byte 0x0 0.--7. 1. "THRESHOLD,Program the desired FIFO1 data sample level minus 1 to reach before generating interrupt to CPU" line.long 0x4 "ADCREGS_FIFO1DMAREQ,dma request." hexmask.long.byte 0x4 0.--7. 1. "DMAREQLEVEL,Number of words minus 1 in FIFO1 before generating a DMA request" rgroup.long 0x100++0x3 line.long 0x0 "ADCREGS_FIFO0DATA,A read from this register will auto increment the FIFO read pointer." hexmask.long.byte 0x0 16.--19. 1. "ADCCHANLID,Optional ID tag of channel that captured the data. If tag option is disabled these bits will be 0" hexmask.long.word 0x0 0.--11. 1. "ADCDATA,sampled ADC converted data value stored in FIFO" rgroup.long 0x200++0x3 line.long 0x0 "ADCREGS_FIFO1DATA,A read from this register will auto increment the FIFO read pointer." hexmask.long.byte 0x0 16.--19. 1. "ADCCHANLID,Optional ID tag of channel that captured the data. If tag option is disabled these bits will be 0" hexmask.long.word 0x0 0.--11. 1. "ADCDATA,sampled ADC converted data value stored in FIFO" rgroup.long 0x20++0x3 line.long 0x0 "ADCREGS_EOI,The End of Interrupt (EOI) MISC Register allows the CPU to acknowledge completion of an interrupt by writing to the EOI for MISC interrupt sources. An eoi_write signal will be generated and another interrupt will be triggered if interrupt.." bitfld.long 0x0 0. "LINENUMEOI,Write 0 to flag End Of Interrupt." "0,1" rgroup.long 0x24++0xF line.long 0x0 "ADCREGS_STATUS_RAW,The IRQ_STATUS_RAW register allows the adc12 interrupt sources to be manually set when writing a 1 to a specific bit. Write 0: No action Write 1: Set event Read 0: No event pending Read 1: Event pending" bitfld.long 0x0 8. "OUTOFRANGE,sample out of range" "0,1" bitfld.long 0x0 7. "FIFO1UNFL,fifo under flow" "0,1" newline bitfld.long 0x0 6. "FIFO1OVFL,fifo over flow" "0,1" bitfld.long 0x0 5. "FIFO1THRS,fifo thresholds met" "0,1" newline bitfld.long 0x0 4. "FIFO0UNFL,fifo under flow" "0,1" bitfld.long 0x0 3. "FIFO0OVFL,fifo over flow" "0,1" newline bitfld.long 0x0 2. "FIFO0THRS,fifo thresholds met" "0,1" bitfld.long 0x0 1. "ENDOFEQUENCE,end of sequence" "0,1" newline bitfld.long 0x0 0. "AFE_EOC_MISSING,eoc from the analog front end missing at expected time after soc" "0,1" line.long 0x4 "ADCREGS_STATUS,The IRQ_STATUS register allows the adc12 interrupt sources to be manually cleared when writing a 1 to a specific bit. Write 0: No action Write 1: Clear event Read 0: No event pending Read 1: Event pending" bitfld.long 0x4 8. "OUTOFRANGE,sample out of range" "0,1" bitfld.long 0x4 7. "FIFO1UNFL,fifo under flow" "0,1" newline bitfld.long 0x4 6. "FIFO1OVFL,fifo over flow" "0,1" bitfld.long 0x4 5. "FIFO1THRS,fifo thresholds met" "0,1" newline bitfld.long 0x4 4. "FIFO0UNFL,fifo under flow" "0,1" bitfld.long 0x4 3. "FIFO0OVFL,fifo over flow" "0,1" newline bitfld.long 0x4 2. "FIFO0THRS,fifo thresholds met" "0,1" bitfld.long 0x4 1. "ENDOFEQUENCE,end of sequence" "0,1" newline bitfld.long 0x4 0. "AFE_EOC_MISSING,eoc from the analog front end missing at expected time after soc" "0,1" line.long 0x8 "ADCREGS_ENABLE_SET,The IRQ_ENABLE_SET register allows the adc12 interrupt sources to be manually enabled when writing a 1 to a specific bit. Write 0: No action Write 1: Enable event Read 0: Event is disabled Read 1: Event is enabled" bitfld.long 0x8 8. "OUTOFRANGE,sample out of range" "0,1" bitfld.long 0x8 7. "FIFO1UNFL,fifo under flow" "0,1" newline bitfld.long 0x8 6. "FIFO1OVFL,fifo over flow" "0,1" bitfld.long 0x8 5. "FIFO1THRS,fifo thresholds met" "0,1" newline bitfld.long 0x8 4. "FIFO0UNFL,fifo under flow" "0,1" bitfld.long 0x8 3. "FIFO0OVFL,fifo over flow" "0,1" newline bitfld.long 0x8 2. "FIFO0THRS,fifo thresholds met" "0,1" bitfld.long 0x8 1. "ENDOFEQUENCE,end of sequence" "0,1" newline bitfld.long 0x8 0. "AFE_EOC_MISSING,eoc from the analog front end missing at expected time after soc" "0,1" line.long 0xC "ADCREGS_ENABLE_CLR,The IRQ_ENABLE_CLR register allows the adc12 interrupt sources to be manually disabled when writing a 1 to a specific bit. Write 0: No action Write 1: Disable event Read 0: Event is disabled Read 1: Event is enabled" bitfld.long 0xC 8. "OUTOFRANGE,sample out of range" "0,1" bitfld.long 0xC 7. "FIFO1UNFL,fifo under flow" "0,1" newline bitfld.long 0xC 6. "FIFO1OVFL,fifo over flow" "0,1" bitfld.long 0xC 5. "FIFO1THRS,fifo thresholds met" "0,1" newline bitfld.long 0xC 4. "FIFO0UNFL,fifo under flow" "0,1" bitfld.long 0xC 3. "FIFO0OVFL,fifo over flow" "0,1" newline bitfld.long 0xC 2. "FIFO0THRS,fifo thresholds met" "0,1" bitfld.long 0xC 1. "ENDOFEQUENCE,end of sequence" "0,1" newline bitfld.long 0xC 0. "AFE_EOC_MISSING,eoc from the analog front end missing at expected time after soc" "0,1" rgroup.long 0x64++0x7 line.long 0x0 "ADCREGS_STEPCONFIG,The user should write to this register the values" bitfld.long 0x0 27. "RANGECHECK,0 = no range sel 1 = compare ADC data with range" "0: no range sel,1: compare ADC data with range" bitfld.long 0x0 26. "FIFOSEL,Sampled data will be stored in FIFO0 when = 0 FIFO1 when = 1" "0,1" newline bitfld.long 0x0 25. "DIFF_CNTRL,Differential control. Single ended when = 0 differential input when = 1" "0,1" hexmask.long.byte 0x0 19.--22. 1. "SEL_INP_SWC,SEL_INP pins SW configuration" newline hexmask.long.byte 0x0 15.--18. 1. "SEL_INM_SWM,SEL_INM pins negative differential" bitfld.long 0x0 2.--4. "AVERAGING,000 -> no average 001 -> 2 samples average 010 -> 4 samples average 011 -> 8 samples average 100 -> 16 samples average" "0: no average 001,?,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "MODE,00 SW enabled one shot 01 SW enabled continuous 10 HW synchronized one-shot 11 HW synchronized continuous" "0,1,2,3" line.long 0x4 "ADCREGS_STEPDELAY,Controls number of clock periods to sample and delay" hexmask.long.byte 0x4 24.--31. 1. "SAMPLEDELAY,number of ADC clock cycles to sample. Any value programmed here will be added to the minimum requirement of 1 clock cycle." hexmask.long.tbyte 0x4 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion" tree.end tree "MCU_adc12fc_16ffc0_ADC12_FIFO_DMA (MCU_adc12fc_16ffc0_ADC12_FIFO_DMA)" base ad:0x40208000 rgroup.long 0x100++0x3 line.long 0x0 "ADC12_FIFO_DMA_FIFO0DMADATA,DMA sample FIFO" hexmask.long.byte 0x0 16.--19. 1. "ADCCHANLID,Optional ID tag of channel that captured the data. If tag option is disabled these bits will be 0" hexmask.long.word 0x0 0.--11. 1. "ADCDATA,sampled ADC converted data value stored in FIFO" rgroup.long 0x200++0x3 line.long 0x0 "ADC12_FIFO_DMA_FIFO1DMADATA,DMA sample FIFO" hexmask.long.byte 0x0 16.--19. 1. "ADCCHANLID,Optional ID tag of channel that captured the data. If tag option is disabled these bits will be 0" hexmask.long.word 0x0 0.--11. 1. "ADCDATA,sampled ADC converted data value stored in FIFO" tree.end tree "MCU_adc12fc_16ffc0_ECC (MCU_adc12fc_16ffc0_ECC)" base ad:0x40707000 rgroup.long 0x0++0x3 line.long 0x0 "ECCREGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "ECCREGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECCREGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x3C++0x7 line.long 0x0 "ECCREGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECCREGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "RAM1_PEND,Interrupt Pending Status for ram1_pend" "0,1" bitfld.long 0x4 0. "RAM0_PEND,Interrupt Pending Status for ram0_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "ECCREGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "RAM1_ENABLE_SET,Interrupt Enable Set Register for ram1_pend" "0,1" bitfld.long 0x0 0. "RAM0_ENABLE_SET,Interrupt Enable Set Register for ram0_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ECCREGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "RAM1_ENABLE_CLR,Interrupt Enable Clear Register for ram1_pend" "0,1" bitfld.long 0x0 0. "RAM0_ENABLE_CLR,Interrupt Enable Clear Register for ram0_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "ECCREGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECCREGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "RAM1_PEND,Interrupt Pending Status for ram1_pend" "0,1" bitfld.long 0x4 0. "RAM0_PEND,Interrupt Pending Status for ram0_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "ECCREGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "RAM1_ENABLE_SET,Interrupt Enable Set Register for ram1_pend" "0,1" bitfld.long 0x0 0. "RAM0_ENABLE_SET,Interrupt Enable Set Register for ram0_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "ECCREGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "RAM1_ENABLE_CLR,Interrupt Enable Clear Register for ram1_pend" "0,1" bitfld.long 0x0 0. "RAM0_ENABLE_CLR,Interrupt Enable Clear Register for ram0_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "ECCREGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECCREGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECCREGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECCREGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree.end tree "MCU_adc12fc_16ffc1" tree "MCU_adc12fc_16ffc1_ADC (MCU_adc12fc_16ffc1_ADC)" base ad:0x40210000 rgroup.long 0x0++0x3 line.long 0x0 "ADCREGS_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x38++0xB line.long 0x0 "ADCREGS_DMAENABLE_SET,The DMAENABLE_SET register allows the enabling of DMA requests" bitfld.long 0x0 1. "ENABLE1,enable DMA reguest FIFO1" "0,1" bitfld.long 0x0 0. "ENABLE0,enable DMA reguest FIFO0" "0,1" line.long 0x4 "ADCREGS_DMAENABLE_CLR,The DMAENABLE_CLR register allows the disabling of DMA requests" bitfld.long 0x4 1. "ENABLE1,clears the enable of the DMA reguest FIFO1. Disables DMA request when writing 1" "0,1" bitfld.long 0x4 0. "ENABLE0,clears the enable of the DMA reguest FIFO0. Disables DMA request when writing 1" "0,1" line.long 0x8 "ADCREGS_CONTROL,Controls various parameters of the cotroller state." bitfld.long 0x8 11. "HI_MID_SEL,Functional safety debug mode. =1 choose ADCREFP =0 VMID reference input to ADC" "0,1" bitfld.long 0x8 10. "HI_MID_EN,Functional safety debug mode. enable fixed reference to ADC for testing" "0,1" newline bitfld.long 0x8 9. "HW_PREEMPT,1 steps are preempted" "0,1" bitfld.long 0x8 8. "HW_MAP,1 = hw events enabled" "?,1: hw events enabled" newline bitfld.long 0x8 4. "PD,AFE powered down" "0,1" bitfld.long 0x8 3. "BIAS_SEL,AFE select bias control" "0,1" newline bitfld.long 0x8 1. "STEP_ID_EN,writing 1 will store the stepid number with the captured adc data in the fifo" "0,1" bitfld.long 0x8 0. "MODULE_ENABLE,ADC12_SS module enable bit. After programming all the configuration and step enable registers write a 1 to this bit to start conversion. Writing a 0 will disable the module after the current conversion. Before turning on again the.." "0,1" rgroup.long 0x44++0x3 line.long 0x0 "ADCREGS_SEQUENCER_STAT,SW can read this register to find out the currently" bitfld.long 0x0 8. "GPADC_BUSY,Monitor the AFE internal calibration busy bit" "0,1" bitfld.long 0x0 6. "MEM_INIT_DONE,status of ram initialization 1= ram initialization to 0 after reset is done." "?,1: ram initialization to 0 after reset is done" newline bitfld.long 0x0 5. "FSM_BUSY,status of fsm 1= conversion in progress" "?,1: conversion in progress" hexmask.long.byte 0x0 0.--4. 1. "STEP_IDLE,10000 = idle 000000 -> 01111 corresponds to step 1 -> step 16" rgroup.long 0x48++0x3 line.long 0x0 "ADCREGS_RANGE,This feature requires the range check interrupt bit to be enabled first." hexmask.long.word 0x0 16.--27. 1. "HIRANGE,If the sampled data is > value then interrupt is generated" hexmask.long.word 0x0 0.--11. 1. "LOWRANGE,If the sampled data is < value then interrupt is generated" rgroup.long 0x50++0x7 line.long 0x0 "ADCREGS_MISC,Spare inputs of the AFE are driven by this register. spare outputs from the AFE are read." hexmask.long.byte 0x0 8.--11. 1. "AFE_SPARE_OUT,Spare outputs from AFE" hexmask.long.byte 0x0 0.--3. 1. "AFE_SPARE_IN,Spare inputs to AFE" line.long 0x4 "ADCREGS_STEPENABLE,Contains the enable bit for each step in the sequencer." bitfld.long 0x4 16. "STEP16,Enable step" "0,1" bitfld.long 0x4 15. "STEP15,Enable step" "0,1" newline bitfld.long 0x4 14. "STEP14,Enable step" "0,1" bitfld.long 0x4 13. "STEP13,Enable step" "0,1" newline bitfld.long 0x4 12. "STEP12,Enable step" "0,1" bitfld.long 0x4 11. "STEP11,Enable step" "0,1" newline bitfld.long 0x4 10. "STEP10,Enable step" "0,1" bitfld.long 0x4 9. "STEP9,Enable step" "0,1" newline bitfld.long 0x4 8. "STEP8,Enable step" "0,1" bitfld.long 0x4 7. "STEP7,Enable step" "0,1" newline bitfld.long 0x4 6. "STEP6,Enable step" "0,1" bitfld.long 0x4 5. "STEP5,Enable step" "0,1" newline bitfld.long 0x4 4. "STEP4,Enable step" "0,1" bitfld.long 0x4 3. "STEP3,Enable step" "0,1" newline bitfld.long 0x4 2. "STEP2,Enable step" "0,1" bitfld.long 0x4 1. "STEP1,Enable step" "0,1" rgroup.long 0xE4++0x3 line.long 0x0 "ADCREGS_FIFO0WC,FIFO word count status" hexmask.long.word 0x0 0.--8. 1. "NUMWDS,number of words in the FIFO" rgroup.long 0xE8++0x7 line.long 0x0 "ADCREGS_FIFO0THRESHOLD,FIFO threshold" hexmask.long.byte 0x0 0.--7. 1. "THRESHOLD,Program the desired FIFO0 data sample level minus 1 to reach before generating interrupt to CPU" line.long 0x4 "ADCREGS_FIFO0DMAREQ,dma request." hexmask.long.byte 0x4 0.--7. 1. "DMAREQLEVEL,Number of words minus 1 in FIFO0 before generating a DMA request" rgroup.long 0xF0++0x3 line.long 0x0 "ADCREGS_FIFO1WC,FIFO word count status" hexmask.long.word 0x0 0.--8. 1. "NUMWDS,number of words in the FIFO" rgroup.long 0xF4++0x7 line.long 0x0 "ADCREGS_FIFO1THRESHOLD,FIFO threshold" hexmask.long.byte 0x0 0.--7. 1. "THRESHOLD,Program the desired FIFO1 data sample level minus 1 to reach before generating interrupt to CPU" line.long 0x4 "ADCREGS_FIFO1DMAREQ,dma request." hexmask.long.byte 0x4 0.--7. 1. "DMAREQLEVEL,Number of words minus 1 in FIFO1 before generating a DMA request" rgroup.long 0x100++0x3 line.long 0x0 "ADCREGS_FIFO0DATA,A read from this register will auto increment the FIFO read pointer." hexmask.long.byte 0x0 16.--19. 1. "ADCCHANLID,Optional ID tag of channel that captured the data. If tag option is disabled these bits will be 0" hexmask.long.word 0x0 0.--11. 1. "ADCDATA,sampled ADC converted data value stored in FIFO" rgroup.long 0x200++0x3 line.long 0x0 "ADCREGS_FIFO1DATA,A read from this register will auto increment the FIFO read pointer." hexmask.long.byte 0x0 16.--19. 1. "ADCCHANLID,Optional ID tag of channel that captured the data. If tag option is disabled these bits will be 0" hexmask.long.word 0x0 0.--11. 1. "ADCDATA,sampled ADC converted data value stored in FIFO" tree.end tree "MCU_adc12fc_16ffc1_ADC12_FIFO_DMA (MCU_adc12fc_16ffc1_ADC12_FIFO_DMA)" base ad:0x40218000 rgroup.long 0x100++0x3 line.long 0x0 "ADC12_FIFO_DMA_FIFO0DMADATA,DMA sample FIFO" hexmask.long.byte 0x0 16.--19. 1. "ADCCHANLID,Optional ID tag of channel that captured the data. If tag option is disabled these bits will be 0" hexmask.long.word 0x0 0.--11. 1. "ADCDATA,sampled ADC converted data value stored in FIFO" rgroup.long 0x200++0x3 line.long 0x0 "ADC12_FIFO_DMA_FIFO1DMADATA,DMA sample FIFO" hexmask.long.byte 0x0 16.--19. 1. "ADCCHANLID,Optional ID tag of channel that captured the data. If tag option is disabled these bits will be 0" hexmask.long.word 0x0 0.--11. 1. "ADCDATA,sampled ADC converted data value stored in FIFO" tree.end tree "MCU_adc12fc_16ffc1_ECC (MCU_adc12fc_16ffc1_ECC)" base ad:0x40708000 rgroup.long 0x0++0x3 line.long 0x0 "ECCREGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "ECCREGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECCREGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x3C++0x7 line.long 0x0 "ECCREGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECCREGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "RAM1_PEND,Interrupt Pending Status for ram1_pend" "0,1" bitfld.long 0x4 0. "RAM0_PEND,Interrupt Pending Status for ram0_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "ECCREGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "RAM1_ENABLE_SET,Interrupt Enable Set Register for ram1_pend" "0,1" bitfld.long 0x0 0. "RAM0_ENABLE_SET,Interrupt Enable Set Register for ram0_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ECCREGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "RAM1_ENABLE_CLR,Interrupt Enable Clear Register for ram1_pend" "0,1" bitfld.long 0x0 0. "RAM0_ENABLE_CLR,Interrupt Enable Clear Register for ram0_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "ECCREGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECCREGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "RAM1_PEND,Interrupt Pending Status for ram1_pend" "0,1" bitfld.long 0x4 0. "RAM0_PEND,Interrupt Pending Status for ram0_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "ECCREGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "RAM1_ENABLE_SET,Interrupt Enable Set Register for ram1_pend" "0,1" bitfld.long 0x0 0. "RAM0_ENABLE_SET,Interrupt Enable Set Register for ram0_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "ECCREGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "RAM1_ENABLE_CLR,Interrupt Enable Clear Register for ram1_pend" "0,1" bitfld.long 0x0 0. "RAM0_ENABLE_CLR,Interrupt Enable Clear Register for ram0_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "ECCREGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECCREGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECCREGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECCREGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree.end tree.end tree "MCU_CPSW0_NUSS (MCU_CPSW0_NUSS)" base ad:0x46000000 rgroup.long 0x0++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_CPSW_NUSS_IDVER_REG,CPSW_NUSS ID Version Register" hexmask.long.word 0x0 16.--31. 1. "IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" rgroup.long 0x4++0xF line.long 0x0 "CPSW_NUSS_VBUSP_SYNCE_COUNT_REG,CPSW_NUSS SYNCE Count Register" hexmask.long 0x0 0.--31. 1. "SYNCE_CNT,Sync E Count Value" line.long 0x4 "CPSW_NUSS_VBUSP_SYNCE_MUX_REG,CPSW_NUSS Synce Mux Register" hexmask.long.byte 0x4 0.--5. 1. "SYNCE_SEL,Sync E Select Value" line.long 0x8 "CPSW_NUSS_VBUSP_CONTROL_REG,CPSW_NUSS Control Register" bitfld.long 0x8 1. "EEE_PHY_ONLY,Energy Efficient Enable Phy Only Mode: 0=The low power indicate state includes gating off the CPPI_GCLK to the CPSW 1=The low power indicate state does not gate the clock to the CPSW" "0: The low power indicate state includes gating off..,1: The low power indicate state does not gate the.." bitfld.long 0x8 0. "EEE_EN,Energy Efficient Ethernet Enable: 0=EEE is disabled 1=EEE is enabled" "0: EEE is disabled,1: EEE is enabled" line.long 0xC "CPSW_NUSS_VBUSP_SGMII_MODE_REG,CPSW_NUSS SyncE Mux Register" bitfld.long 0xC 0. "SYNCE_SEL,SGMII_MODE Input" "0,1" rgroup.long 0x18++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_RGMII_STATUS_REG,CPSW_NUSS RGMII Status Register" bitfld.long 0x0 3. "FULLDUPLEX,Rgmii full dulex: 0=Half-duplex 1=Full-duplex" "0: Half-duplex,1: Full-duplex" bitfld.long 0x0 1.--2. "SPEED,Rgmii speed: 00=10Mbps 01=100Mbps 10=1000Mbps 11=reserved" "0,1,2,3" newline bitfld.long 0x0 0. "LINK,Rgmii link indicator: 0=Link is down 1=Link is up" "0: Link is down,1: Link is up" line.long 0x4 "CPSW_NUSS_VBUSP_SUBSSYSTEM_STATUS_REG,CPSW_NUSS Status Register" bitfld.long 0x4 0. "EEE_CLKSTOP_ACK,Energy Efficient Ethernet clockstop acknowledge from CPSW" "0,1" tree.end tree "MCU_CTRL_MMR0_CFG0 (MCU_CTRL_MMR0_CFG0)" base ad:0x40F00000 rgroup.long 0x0++0xB line.long 0x0 "CFG0_PID," hexmask.long.word 0x0 16.--31. 1. "PID_MSB16," newline hexmask.long.byte 0x0 11.--15. 1. "PID_MISC," newline bitfld.long 0x0 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "PID_CUSTOM," "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR," line.long 0x4 "CFG0_MMR_CFG0," hexmask.long.word 0x4 16.--31. 1. "MMR_CFG0_CFG_REV,Major configuration release" newline hexmask.long.word 0x4 0.--15. 1. "MMR_CFG0_SPEC_REV,Minor spec-only revision. Doesn't change with RTL release so RTL will always read as 16'h0000" line.long 0x8 "CFG0_MMR_CFG1," bitfld.long 0x8 31. "MMR_CFG1_PROXY_EN,Proxy addressing enabled" "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "MMR_CFG1_PARTITIONS,Indicates present partitions" rgroup.long 0x100++0x7 line.long 0x0 "CFG0_IPC_SET0," hexmask.long 0x0 4.--31. 1. "IPC_SET0_IPC_SRC_SET,Read returns current value Write: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0x0 0. "IPC_SET0_IPC_SET,Read returns 0 Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0: No effect 1,?" line.long 0x4 "CFG0_IPC_SET1," hexmask.long 0x4 4.--31. 1. "IPC_SET1_IPC_SRC_SET,Read returns current value Write: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0x4 0. "IPC_SET1_IPC_SET,Read returns 0 Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0: No effect 1,?" rgroup.long 0x120++0x3 line.long 0x0 "CFG0_IPC_SET8," hexmask.long 0x0 4.--31. 1. "IPC_SET8_IPC_SRC_SET,Read returns current value Write: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0x0 0. "IPC_SET8_IPC_SET,Read returns 0 Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0: No effect 1,?" rgroup.long 0x180++0x7 line.long 0x0 "CFG0_IPC_CLR0," hexmask.long 0x0 4.--31. 1. "IPC_CLR0_IPC_SRC_CLR,Read returns current value Write: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0x0 0. "IPC_CLR0_IPC_CLR,Read returns current value Write: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0: No effect 1,?" line.long 0x4 "CFG0_IPC_CLR1," hexmask.long 0x4 4.--31. 1. "IPC_CLR1_IPC_SRC_CLR,Read returns current value Write: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0x4 0. "IPC_CLR1_IPC_CLR,Read returns current value Write: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0: No effect 1,?" rgroup.long 0x1A0++0x3 line.long 0x0 "CFG0_IPC_CLR8," hexmask.long 0x0 4.--31. 1. "IPC_CLR8_IPC_SRC_CLR,Read returns current value Write: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0x0 0. "IPC_CLR8_IPC_CLR,Read returns current value Write: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0: No effect 1,?" rgroup.long 0x200++0x7 line.long 0x0 "CFG0_MAC_ID0," hexmask.long 0x0 0.--31. 1. "MAC_ID0_MACID_LO,32 lsbs of MAC address This bitfield may be written only once after each module reset ." line.long 0x4 "CFG0_MAC_ID1," hexmask.long.word 0x4 0.--15. 1. "MAC_ID1_MACID_HI,16 msbs of MAC address This bitfield may be written only once after each module reset ." rgroup.long 0x208++0x3 line.long 0x0 "CFG0_MAC_ID_COUNT," hexmask.long.byte 0x0 0.--3. 1. "MAC_ID_COUNT_COUNT,Indicates the number of MAC addresses to be assigned" rgroup.long 0x1008++0x1B line.long 0x0 "CFG0_LOCK0_KICK0," hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK0_KICK1," hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1,- KICK1 component" line.long 0x8 "CFG0_intr_raw_status," bitfld.long 0x8 3. "PROXY_ERR,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 2. "KICK_ERR,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 1. "ADDR_ERR,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0xC "CFG0_intr_enabled_status_clear," bitfld.long 0xC 3. "ENABLED_PROXY_ERR,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 2. "ENABLED_KICK_ERR,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x10 "CFG0_intr_enable," bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0x14 "CFG0_intr_enable_clear," bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x18 "CFG0_eoi," hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x1024++0xB line.long 0x0 "CFG0_fault_address," hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault Address." line.long 0x4 "CFG0_fault_type_status," bitfld.long 0x4 6. "FAULT_NS,Non-secure access." "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir.." line.long 0x8 "CFG0_fault_attr_status," hexmask.long.word 0x8 20.--31. 1. "FAULT_XID,XID." newline hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID,Route ID." newline hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID,Privilege ID." rgroup.long 0x1030++0x3 line.long 0x0 "CFG0_fault_clear," bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" rgroup.long 0x1100++0x13 line.long 0x0 "CFG0_CLAIMREG_P0_R0_READONLY," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P0_R0_READONLY,Claim bits for Partition 0" line.long 0x4 "CFG0_CLAIMREG_P0_R1_READONLY," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P0_R1_READONLY,Claim bits for Partition 0" line.long 0x8 "CFG0_CLAIMREG_P0_R2_READONLY," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P0_R2_READONLY,Claim bits for Partition 0" line.long 0xC "CFG0_CLAIMREG_P0_R3_READONLY," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P0_R3_READONLY,Claim bits for Partition 0" line.long 0x10 "CFG0_CLAIMREG_P0_R4_READONLY," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P0_R4_READONLY,Claim bits for Partition 0" rgroup.long 0x2000++0xB line.long 0x0 "CFG0_PID_PROXY," hexmask.long.word 0x0 16.--31. 1. "PID_MSB16_PROXY," newline hexmask.long.byte 0x0 11.--15. 1. "PID_MISC_PROXY," newline bitfld.long 0x0 8.--10. "PID_MAJOR_PROXY," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "PID_CUSTOM_PROXY," "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR_PROXY," line.long 0x4 "CFG0_MMR_CFG0_PROXY," hexmask.long.word 0x4 16.--31. 1. "MMR_CFG0_CFG_REV_PROXY,Major configuration release" newline hexmask.long.word 0x4 0.--15. 1. "MMR_CFG0_SPEC_REV_PROXY,Minor spec-only revision. Doesn't change with RTL release so RTL will always read as 16'h0000" line.long 0x8 "CFG0_MMR_CFG1_PROXY," bitfld.long 0x8 31. "MMR_CFG1_PROXY_EN_PROXY,Proxy addressing enabled" "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "MMR_CFG1_PARTITIONS_PROXY,Indicates present partitions" rgroup.long 0x2100++0x7 line.long 0x0 "CFG0_IPC_SET0_PROXY," hexmask.long 0x0 4.--31. 1. "IPC_SET0_IPC_SRC_SET_PROXY,Read returns current value Write: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0x0 0. "IPC_SET0_IPC_SET_PROXY,Read returns 0 Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0: No effect 1,?" line.long 0x4 "CFG0_IPC_SET1_PROXY," hexmask.long 0x4 4.--31. 1. "IPC_SET1_IPC_SRC_SET_PROXY,Read returns current value Write: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0x4 0. "IPC_SET1_IPC_SET_PROXY,Read returns 0 Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0: No effect 1,?" rgroup.long 0x2120++0x3 line.long 0x0 "CFG0_IPC_SET8_PROXY," hexmask.long 0x0 4.--31. 1. "IPC_SET8_IPC_SRC_SET_PROXY,Read returns current value Write: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0x0 0. "IPC_SET8_IPC_SET_PROXY,Read returns 0 Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0: No effect 1,?" rgroup.long 0x2180++0x7 line.long 0x0 "CFG0_IPC_CLR0_PROXY," hexmask.long 0x0 4.--31. 1. "IPC_CLR0_IPC_SRC_CLR_PROXY,Read returns current value Write: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0x0 0. "IPC_CLR0_IPC_CLR_PROXY,Read returns current value Write: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0: No effect 1,?" line.long 0x4 "CFG0_IPC_CLR1_PROXY," hexmask.long 0x4 4.--31. 1. "IPC_CLR1_IPC_SRC_CLR_PROXY,Read returns current value Write: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0x4 0. "IPC_CLR1_IPC_CLR_PROXY,Read returns current value Write: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0: No effect 1,?" rgroup.long 0x21A0++0x3 line.long 0x0 "CFG0_IPC_CLR8_PROXY," hexmask.long 0x0 4.--31. 1. "IPC_CLR8_IPC_SRC_CLR_PROXY,Read returns current value Write: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0x0 0. "IPC_CLR8_IPC_CLR_PROXY,Read returns current value Write: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0: No effect 1,?" rgroup.long 0x2200++0x7 line.long 0x0 "CFG0_MAC_ID0_PROXY," hexmask.long 0x0 0.--31. 1. "MAC_ID0_MACID_LO_PROXY,32 lsbs of MAC address This bitfield may be written only once after each module reset ." line.long 0x4 "CFG0_MAC_ID1_PROXY," hexmask.long.word 0x4 0.--15. 1. "MAC_ID1_MACID_HI_PROXY,16 msbs of MAC address This bitfield may be written only once after each module reset ." rgroup.long 0x2208++0x3 line.long 0x0 "CFG0_MAC_ID_COUNT_PROXY," hexmask.long.byte 0x0 0.--3. 1. "MAC_ID_COUNT_COUNT_PROXY,Indicates the number of MAC addresses to be assigned" rgroup.long 0x3008++0x1B line.long 0x0 "CFG0_LOCK0_KICK0_PROXY," hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK0_KICK1_PROXY," hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1_PROXY,- KICK1 component" line.long 0x8 "CFG0_intr_raw_status_PROXY," bitfld.long 0x8 3. "PROXY_ERR_PROXY,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 2. "KICK_ERR_PROXY,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 1. "ADDR_ERR_PROXY,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 0. "PROT_ERR_PROXY,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0xC "CFG0_intr_enabled_status_clear_PROXY," bitfld.long 0xC 3. "ENABLED_PROXY_ERR_PROXY,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 2. "ENABLED_KICK_ERR_PROXY,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 1. "ENABLED_ADDR_ERR_PROXY,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 0. "ENABLED_PROT_ERR_PROXY,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x10 "CFG0_intr_enable_PROXY," bitfld.long 0x10 3. "PROXY_ERR_EN_PROXY,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 2. "KICK_ERR_EN_PROXY,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 1. "ADDR_ERR_EN_PROXY,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 0. "PROT_ERR_EN_PROXY,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0x14 "CFG0_intr_enable_clear_PROXY," bitfld.long 0x14 3. "PROXY_ERR_EN_CLR_PROXY,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 2. "KICK_ERR_EN_CLR_PROXY,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 1. "ADDR_ERR_EN_CLR_PROXY,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 0. "PROT_ERR_EN_CLR_PROXY,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x18 "CFG0_eoi_PROXY," hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR_PROXY,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x3024++0xB line.long 0x0 "CFG0_fault_address_PROXY," hexmask.long 0x0 0.--31. 1. "FAULT_ADDR_PROXY,Fault Address." line.long 0x4 "CFG0_fault_type_status_PROXY," bitfld.long 0x4 6. "FAULT_NS_PROXY,Non-secure access." "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE_PROXY,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv =.." line.long 0x8 "CFG0_fault_attr_status_PROXY," hexmask.long.word 0x8 20.--31. 1. "FAULT_XID_PROXY,XID." newline hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID_PROXY,Route ID." newline hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID_PROXY,Privilege ID." rgroup.long 0x3030++0x3 line.long 0x0 "CFG0_fault_clear_PROXY," bitfld.long 0x0 0. "FAULT_CLR_PROXY,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" rgroup.long 0x3100++0x13 line.long 0x0 "CFG0_CLAIMREG_P0_R0," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P0_R0,Claim bits for Partition 0" line.long 0x4 "CFG0_CLAIMREG_P0_R1," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P0_R1,Claim bits for Partition 0" line.long 0x8 "CFG0_CLAIMREG_P0_R2," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P0_R2,Claim bits for Partition 0" line.long 0xC "CFG0_CLAIMREG_P0_R3," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P0_R3,Claim bits for Partition 0" line.long 0x10 "CFG0_CLAIMREG_P0_R4," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P0_R4,Claim bits for Partition 0" rgroup.long 0x4030++0x3 line.long 0x0 "CFG0_MSMC_CFG," hexmask.long.byte 0x0 8.--11. 1. "MSMC_CFG_MEM_SIZE,Indicates the size of MSMC shared SRAM/Cache Field values (others are reserved): undefined - undefined undefined - undefined undefined - undefined undefined - undefined undefined - undefined undefined - undefined undefined - undefined.." newline bitfld.long 0x0 4. "MSMC_CFG_MEM_INIT_DIS,Disables MSMC SRAM initialization (Data Cache Tags and Snoop Filters). This is required for proper initial ECC initialization. 1'b0 - Perform memory initialization 1'b1 - Disable memory initialization" "0: Perform memory initialization 1'b1,?" rgroup.long 0x4040++0x3 line.long 0x0 "CFG0_MCU_ENET_CTRL," bitfld.long 0x0 4. "MCU_ENET_CTRL_RGMII_ID_MODE,Port1 RGMII internal transmit delay selection 0 - Internal transmit delay 1 - No internal transmit delay" "0: Internal transmit delay 1,?" newline bitfld.long 0x0 0.--1. "MCU_ENET_CTRL_MODE_SEL,Selects Ethernet switch Port1 interface Field values (others are reserved): 2'b00 - GMII/MII (not supported) 2'b01 - RMII 2'b10 - RGMII 2'b11 - SGMII (not supported)" "0: GMII/MII,1: RMII 2'b10,?,3: SGMII" rgroup.long 0x4060++0x3 line.long 0x0 "CFG0_MCU_SPI1_CTRL," bitfld.long 0x0 0. "MCU_SPI1_CTRL_SPI1_LINKDIS,Disables direct connection of MCU_SPI1 to SPI3 Field values (others are reserved): 1'b0 - MCU_SPI1 is tied as a slave to SPI3. MCU_SPI1 CLK DATA1 and CS0 are driven from SPI3 DATA OUT drives SPI3 DATA0 1'b1 - MCU_SPI1 is.." "0: MCU_SPI1 is tied as a slave to SPI3,1: MCU_SPI1 is NOT tied as a slave to SPI3" rgroup.long 0x4070++0x17 line.long 0x0 "CFG0_MCU_I3C0_CTRL0," hexmask.long.word 0x0 16.--30. 1. "MCU_I3C0_CTRL0_PID_MFR_ID,Manufacturer ID This input corresponds to bits[47:33] of the Provisional ID to identify the manufacturer. Defaults to TI value." newline bitfld.long 0x0 8. "MCU_I3C0_CTRL0_ROLE,Master Role 0 - Main master 1 - Secondary master" "0: Main master 1,?" newline hexmask.long.byte 0x0 0.--3. 1. "MCU_I3C0_CTRL0_PID_INSTANCE,Provisional ID Instance. This input corresponds to bits[15:12] of the Provisional ID. It is intended to provide a way of differentiating several I3C devices if there would be no other way to have each manufactured device.." line.long 0x4 "CFG0_MCU_I3C0_CTRL1," hexmask.long.byte 0x4 24.--31. 1. "MCU_I3C0_CTRL1_BUS_AVAIL_TIME,Indicates the number of pclk cycles in the Bus Available condition" newline hexmask.long.tbyte 0x4 0.--17. 1. "MCU_I3C0_CTRL1_BUS_IDLE_TIME,Indicates the number of pclk cycles in the Bus Idle condition" line.long 0x8 "CFG0_MCU_I3C1_CTRL0," hexmask.long.word 0x8 16.--30. 1. "MCU_I3C1_CTRL0_PID_MFR_ID,Manufacturer ID This input corresponds to bits[47:33] of the Provisional ID to identify the manufacturer. Defaults to TI value." newline bitfld.long 0x8 8. "MCU_I3C1_CTRL0_ROLE,Master Role 0 - Main master 1 - Secondary master" "0: Main master 1,?" newline hexmask.long.byte 0x8 0.--3. 1. "MCU_I3C1_CTRL0_PID_INSTANCE,Provisional ID Instance. This input corresponds to bits[15:12] of the Provisional ID. It is intended to provide a way of differentiating several I3C devices if there would be no other way to have each manufactured device.." line.long 0xC "CFG0_MCU_I3C1_CTRL1," hexmask.long.byte 0xC 24.--31. 1. "MCU_I3C1_CTRL1_BUS_AVAIL_TIME,Indicates the number of pclk cycles in the Bus Available condition" newline hexmask.long.tbyte 0xC 0.--17. 1. "MCU_I3C1_CTRL1_BUS_IDLE_TIME,Indicates the number of pclk cycles in the Bus Idle condition" line.long 0x10 "CFG0_MCU_I2C0_CTRL," bitfld.long 0x10 0. "MCU_I2C0_CTRL_HS_MCS_EN,HS Mode master current source enable. When set enables the current-source pull-up on the SCL output. Only one master on the I2C bus should enable SCL current sourcing." "0,1" line.long 0x14 "CFG0_MCU_I2C1_CTRL," bitfld.long 0x14 0. "MCU_I2C1_CTRL_HS_MCS_EN,HS Mode master current source enable. When set enables the current-source pull-up on the SCL output. Only one master on the I2C bus should enable SCL current sourcing." "0,1" rgroup.long 0x40A0++0x3 line.long 0x0 "CFG0_MCU_FSS_CTRL," bitfld.long 0x0 24. "MCU_FSS_CTRL_S1_BOOT_SIZE,Selects the size of the boot block to be used for the S1 (OSPI1) flash interface 0 - S1 boot size is 64 MB 1 - S1 boot size is 128 MB" "0: S1 boot size is 64 MB 1,?" newline hexmask.long.byte 0x0 16.--21. 1. "MCU_FSS_CTRL_S1_BOOT_SEG,Selects the boot block to be used for the S1 (OSPI1) flash interface. If the s1_boot_size is 128 MB then only bits [4:0] of this field are used. Care must be taken to account for the address translation as to not fall off or.." newline bitfld.long 0x0 8. "MCU_FSS_CTRL_S0_BOOT_SIZE,Selects the size of the boot block to be used for the S0 (OSPI0 or Hyperbus) flash interface 0 - S0 boot size is 64 MB 1 - S0 boot size is 128 MB" "0: S0 boot size is 64 MB 1,?" newline hexmask.long.byte 0x0 0.--5. 1. "MCU_FSS_CTRL_S0_BOOT_SEG,Selects the boot block to be used for the S0 (OSPI0 or Hyperbus) flash interface. If the s0_boot_size is 128 MB then only bits [4:0] of this field are used. Care must be taken to account for the address translation as to not.." rgroup.long 0x40B0++0x7 line.long 0x0 "CFG0_MCU_ADC0_CTRL," bitfld.long 0x0 16. "MCU_ADC0_CTRL_GPI_MODE_EN,Enables MCU_ADC0 data pins to be used as general purpose inputs when set. This signal is tied to the en_dig_test input of MCU_ADC0" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "MCU_ADC0_CTRL_TRIG_SEL,Selects the source of the ADC hardware event trigger Field values (others are reserved): 5'b00000 - MCU_ADC_EXT_TRIGGER0 pin 5'b00001 - MCU_ADC_EXT_TRIGGER1 pin 5'b00010 - eHRPWM SOCA event 5'b00011 - eHRPWM SOCB event 5'b00100 -.." line.long 0x4 "CFG0_MCU_ADC1_CTRL," bitfld.long 0x4 16. "MCU_ADC1_CTRL_GPI_MODE_EN,Enables MCU_ADC1 data pins to be used as general purpose inputs when set. This signal is tied to the en_dig_test input of MCU_ADC1" "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "MCU_ADC1_CTRL_TRIG_SEL,Selects the source of the ADC hardware event trigger Field values (others are reserved): 5'b00000 - MCU_ADC_EXT_TRIGGER0 pin 5'b00001 - MCU_ADC_EXT_TRIGGER1 pin 5'b00010 - eHRPWM SOCA event 5'b00011 - eHRPWM SOCB event 5'b00100 -.." rgroup.long 0x40C0++0x7 line.long 0x0 "CFG0_MCU_ADC0_TRIM," bitfld.long 0x0 24.--26. "MCU_ADC0_TRIM_TRIM5,Trim value for C5 0.37 fF to 3.2fF in ~0.37fF increments" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21.--23. "MCU_ADC0_TRIM_TRIM4,Trim value for C4 0.37 fF to 3.2fF in ~0.37fF increments" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "MCU_ADC0_TRIM_TRIM3,Trim value for C3 0.37 fF to 3.2fF in ~0.37fF increments" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 14.--17. 1. "MCU_ADC0_TRIM_TRIM2,Trim value for C2 0.37 fF to 6.4fF in ~0.37fF increments" newline hexmask.long.byte 0x0 10.--13. 1. "MCU_ADC0_TRIM_TRIM1,Trim value for C1 0.37 fF to 6.4fF in ~0.37fF increments" newline hexmask.long.byte 0x0 5.--9. 1. "MCU_ADC0_TRIM_ENABLE_CALB,Reserved. This bitfield no longer used" newline hexmask.long.byte 0x0 0.--4. 1. "MCU_ADC0_TRIM_ENABLE_CAL,Reserved. This bitfield no longer used" line.long 0x4 "CFG0_MCU_ADC1_TRIM," bitfld.long 0x4 24.--26. "MCU_ADC1_TRIM_TRIM5,Trim value for C5 0.37 fF to 3.2fF in ~0.37fF increments" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 21.--23. "MCU_ADC1_TRIM_TRIM4,Trim value for C4 0.37 fF to 3.2fF in ~0.37fF increments" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "MCU_ADC1_TRIM_TRIM3,Trim value for C3 0.37 fF to 3.2fF in ~0.37fF increments" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 14.--17. 1. "MCU_ADC1_TRIM_TRIM2,Trim value for C2 0.37 fF to 6.4fF in ~0.37fF increments" newline hexmask.long.byte 0x4 10.--13. 1. "MCU_ADC1_TRIM_TRIM1,Trim value for C1 0.37 fF to 6.4fF in ~0.37fF increments" newline hexmask.long.byte 0x4 5.--9. 1. "MCU_ADC1_TRIM_ENABLE_CALB,Reserved. This bitfield no longer used" newline hexmask.long.byte 0x4 0.--4. 1. "MCU_ADC1_TRIM_ENABLE_CAL,Reserved. This bitfield no longer used" rgroup.long 0x40D0++0x7 line.long 0x0 "CFG0_MCU_ADC0_CAL," bitfld.long 0x0 15. "MCU_ADC0_CAL_CAL_EN,Enable single-ended calibration Set to 1 to begin single-ended calibration" "0,1" newline bitfld.long 0x0 14. "MCU_ADC0_CAL_DIFF_CAL_EN,Enable differential calibration Set to 1 to begin differential calibration" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "MCU_ADC0_CAL_CAL_CAP_SEL,Select capacitor for calibration Bits correspond to C5:C1 Field values (others are reserved): 5'b00000 - None 5'b00001 - Select C1 5'b00010 - Select C2 5'b00100 - Select C3 5'b01000 - Select C4 5'b10000 - Select C5" line.long 0x4 "CFG0_MCU_ADC1_CAL," bitfld.long 0x4 15. "MCU_ADC1_CAL_CAL_EN,Enable single-ended calibration Set to 1 to begin single-ended calibration" "0,1" newline bitfld.long 0x4 14. "MCU_ADC1_CAL_DIFF_CAL_EN,Enable differential calibration Set to 1 to begin differential calibration" "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "MCU_ADC1_CAL_CAL_CAP_SEL,Select capacitor for calibration Bits correspond to C5:C1 Field values (others are reserved): 5'b00000 - None 5'b00001 - Select C1 5'b00010 - Select C2 5'b00100 - Select C3 5'b01000 - Select C4 5'b10000 - Select C5" rgroup.long 0x4200++0x27 line.long 0x0 "CFG0_MCU_TIMER0_CTRL," hexmask.long.byte 0x0 0.--3. 1. "MCU_TIMER0_CTRL_CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER0 is configured for capture operation. Field values (others are reserved): 4'b0000 - Use MCU_TIMER_IO0 pin 4'b0001 - Use.." line.long 0x4 "CFG0_MCU_TIMER1_CTRL," bitfld.long 0x4 8. "MCU_TIMER1_CTRL_CASCADE_EN,When set enables cascading of MCU_TIMER1 to MCU_TIMER0" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "MCU_TIMER1_CTRL_CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER1 is configured for capture operation. Field values (others are reserved): 4'b0000 - Use MCU_TIMER_IO0 pin 4'b0001 - Use.." line.long 0x8 "CFG0_MCU_TIMER2_CTRL," hexmask.long.byte 0x8 0.--3. 1. "MCU_TIMER2_CTRL_CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER2 is configured for capture operation. Field values (others are reserved): 4'b0000 - Use MCU_TIMER_IO0 pin 4'b0001 - Use.." line.long 0xC "CFG0_MCU_TIMER3_CTRL," bitfld.long 0xC 8. "MCU_TIMER3_CTRL_CASCADE_EN,When set enables cascading of MCU_TIMER3 to MCU_TIMER2" "0,1" newline hexmask.long.byte 0xC 0.--3. 1. "MCU_TIMER3_CTRL_CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER3 is configured for capture operation. Field values (others are reserved): 4'b0000 - Use MCU_TIMER_IO0 pin 4'b0001 - Use.." line.long 0x10 "CFG0_MCU_TIMER4_CTRL," hexmask.long.byte 0x10 0.--3. 1. "MCU_TIMER4_CTRL_CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER4 is configured for capture operation. Field values (others are reserved): 4'b0000 - Use MCU_TIMER_IO0 pin 4'b0001 - Use.." line.long 0x14 "CFG0_MCU_TIMER5_CTRL," bitfld.long 0x14 8. "MCU_TIMER5_CTRL_CASCADE_EN,When set enables cascading of MCU_TIMER5 to MCU_TIMER4" "0,1" newline hexmask.long.byte 0x14 0.--3. 1. "MCU_TIMER5_CTRL_CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER5 is configured for capture operation. Field values (others are reserved): 4'b0000 - Use MCU_TIMER_IO0 pin 4'b0001 - Use.." line.long 0x18 "CFG0_MCU_TIMER6_CTRL," hexmask.long.byte 0x18 0.--3. 1. "MCU_TIMER6_CTRL_CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER6 is configured for capture operation. Field values (others are reserved): 4'b0000 - Use MCU_TIMER_IO0 pin 4'b0001 - Use.." line.long 0x1C "CFG0_MCU_TIMER7_CTRL," bitfld.long 0x1C 8. "MCU_TIMER7_CTRL_CASCADE_EN,When set enables cascading of MCU_TIMER7 to MCU_TIMER6" "0,1" newline hexmask.long.byte 0x1C 0.--3. 1. "MCU_TIMER7_CTRL_CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER7 is configured for capture operation. Field values (others are reserved): 4'b0000 - Use MCU_TIMER_IO0 pin 4'b0001 - Use.." line.long 0x20 "CFG0_MCU_TIMER8_CTRL," hexmask.long.byte 0x20 0.--3. 1. "MCU_TIMER8_CTRL_CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER8 is configured for capture operation. Field values (others are reserved): 4'b0000 - Use MCU_TIMER_IO0 pin 4'b0001 - Use.." line.long 0x24 "CFG0_MCU_TIMER9_CTRL," bitfld.long 0x24 8. "MCU_TIMER9_CTRL_CASCADE_EN,When set enables cascading of MCU_TIMER9 to MCU_TIMER8" "0,1" newline hexmask.long.byte 0x24 0.--3. 1. "MCU_TIMER9_CTRL_CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER9 is configured for capture operation. Field values (others are reserved): 4'b0000 - Use MCU_TIMER_IO0 pin 4'b0001 - Use.." rgroup.long 0x4280++0x27 line.long 0x0 "CFG0_MCU_TIMERIO0_CTRL," hexmask.long.byte 0x0 0.--3. 1. "MCU_TIMERIO0_CTRL_OUT_SEL,Selects the source of the MCU_TIMERIO0 output Field values (others are reserved): 4'b0000 - MCU_TIMERIO0 is driven by MCU_TIMER0 output 4'b0001 - MCU_TIMERIO0 is driven by MCU_TIMER1 output 4'b0010 - MCU_TIMERIO0 is driven by.." line.long 0x4 "CFG0_MCU_TIMERIO1_CTRL," hexmask.long.byte 0x4 0.--3. 1. "MCU_TIMERIO1_CTRL_OUT_SEL,Selects the source of the MCU_TIMERIO1 output Field values (others are reserved): 4'b0000 - MCU_TIMERIO1 is driven by MCU_TIMER0 output 4'b0001 - MCU_TIMERIO1 is driven by MCU_TIMER1 output 4'b0010 - MCU_TIMERIO1 is driven by.." line.long 0x8 "CFG0_MCU_TIMERIO2_CTRL," hexmask.long.byte 0x8 0.--3. 1. "MCU_TIMERIO2_CTRL_OUT_SEL,Selects the source of the MCU_TIMERIO2 output Field values (others are reserved): 4'b0000 - MCU_TIMERIO2 is driven by MCU_TIMER0 output 4'b0001 - MCU_TIMERIO2 is driven by MCU_TIMER1 output 4'b0010 - MCU_TIMERIO2 is driven by.." line.long 0xC "CFG0_MCU_TIMERIO3_CTRL," hexmask.long.byte 0xC 0.--3. 1. "MCU_TIMERIO3_CTRL_OUT_SEL,Selects the source of the MCU_TIMERIO3 output Field values (others are reserved): 4'b0000 - MCU_TIMERIO3 is driven by MCU_TIMER0 output 4'b0001 - MCU_TIMERIO3 is driven by MCU_TIMER1 output 4'b0010 - MCU_TIMERIO3 is driven by.." line.long 0x10 "CFG0_MCU_TIMERIO4_CTRL," hexmask.long.byte 0x10 0.--3. 1. "MCU_TIMERIO4_CTRL_OUT_SEL,Selects the source of the MCU_TIMERIO4 output Field values (others are reserved): 4'b0000 - MCU_TIMERIO4 is driven by MCU_TIMER0 output 4'b0001 - MCU_TIMERIO4 is driven by MCU_TIMER1 output 4'b0010 - MCU_TIMERIO4 is driven by.." line.long 0x14 "CFG0_MCU_TIMERIO5_CTRL," hexmask.long.byte 0x14 0.--3. 1. "MCU_TIMERIO5_CTRL_OUT_SEL,Selects the source of the MCU_TIMERIO5 output Field values (others are reserved): 4'b0000 - MCU_TIMERIO5 is driven by MCU_TIMER0 output 4'b0001 - MCU_TIMERIO5 is driven by MCU_TIMER1 output 4'b0010 - MCU_TIMERIO5 is driven by.." line.long 0x18 "CFG0_MCU_TIMERIO6_CTRL," hexmask.long.byte 0x18 0.--3. 1. "MCU_TIMERIO6_CTRL_OUT_SEL,Selects the source of the MCU_TIMERIO6 output Field values (others are reserved): 4'b0000 - MCU_TIMERIO6 is driven by MCU_TIMER0 output 4'b0001 - MCU_TIMERIO6 is driven by MCU_TIMER1 output 4'b0010 - MCU_TIMERIO6 is driven by.." line.long 0x1C "CFG0_MCU_TIMERIO7_CTRL," hexmask.long.byte 0x1C 0.--3. 1. "MCU_TIMERIO7_CTRL_OUT_SEL,Selects the source of the MCU_TIMERIO7 output Field values (others are reserved): 4'b0000 - MCU_TIMERIO7 is driven by MCU_TIMER0 output 4'b0001 - MCU_TIMERIO7 is driven by MCU_TIMER1 output 4'b0010 - MCU_TIMERIO7 is driven by.." line.long 0x20 "CFG0_MCU_TIMERIO8_CTRL," hexmask.long.byte 0x20 0.--3. 1. "MCU_TIMERIO8_CTRL_OUT_SEL,Selects the source of the MCU_TIMERIO8 output Field values (others are reserved): 4'b0000 - MCU_TIMERIO8 is driven by MCU_TIMER0 output 4'b0001 - MCU_TIMERIO8 is driven by MCU_TIMER1 output 4'b0010 - MCU_TIMERIO8 is driven by.." line.long 0x24 "CFG0_MCU_TIMERIO9_CTRL," hexmask.long.byte 0x24 0.--3. 1. "MCU_TIMERIO9_CTRL_OUT_SEL,Selects the source of the MCU_TIMERIO9 output Field values (others are reserved): 4'b0000 - MCU_TIMERIO9 is driven by MCU_TIMER0 output 4'b0001 - MCU_TIMERIO9 is driven by MCU_TIMER1 output 4'b0010 - MCU_TIMERIO9 is driven by.." rgroup.long 0x4300++0x3 line.long 0x0 "CFG0_MCU_MTOG0_CTRL," rbitfld.long 0x0 31. "MCU_MTOG0_CTRL_IDLE_STAT,Idle status When high indicates MTOG0 is idle." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "MCU_MTOG0_CTRL_FORCE_TIMEOUT,Force Timeout Forces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be cleared to.." newline bitfld.long 0x0 15. "MCU_MTOG0_CTRL_TIMEOUT_EN,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x0 0.--2. "MCU_MTOG0_CTRL_TIMEOUT_VAL,Gasket Timeout Value Selects the number of clock cycles before the interface is considered to have timed out Field values (others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 - 16 384 clock cycles.." "0,1,2,3,4,5,6,7" rgroup.long 0x5008++0x7 line.long 0x0 "CFG0_LOCK1_KICK0," hexmask.long 0x0 0.--31. 1. "LOCK1_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK1_KICK1," hexmask.long 0x4 0.--31. 1. "LOCK1_KICK1,- KICK1 component" rgroup.long 0x5100++0x1B line.long 0x0 "CFG0_CLAIMREG_P1_R0_READONLY," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P1_R0_READONLY,Claim bits for Partition 1" line.long 0x4 "CFG0_CLAIMREG_P1_R1_READONLY," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P1_R1_READONLY,Claim bits for Partition 1" line.long 0x8 "CFG0_CLAIMREG_P1_R2_READONLY," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P1_R2_READONLY,Claim bits for Partition 1" line.long 0xC "CFG0_CLAIMREG_P1_R3_READONLY," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P1_R3_READONLY,Claim bits for Partition 1" line.long 0x10 "CFG0_CLAIMREG_P1_R4_READONLY," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P1_R4_READONLY,Claim bits for Partition 1" line.long 0x14 "CFG0_CLAIMREG_P1_R5_READONLY," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P1_R5_READONLY,Claim bits for Partition 1" line.long 0x18 "CFG0_CLAIMREG_P1_R6_READONLY," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P1_R6_READONLY,Claim bits for Partition 1" rgroup.long 0x6030++0x3 line.long 0x0 "CFG0_MSMC_CFG_PROXY," hexmask.long.byte 0x0 8.--11. 1. "MSMC_CFG_MEM_SIZE_PROXY,Indicates the size of MSMC shared SRAM/Cache Field values (others are reserved): undefined - undefined undefined - undefined undefined - undefined undefined - undefined undefined - undefined undefined - undefined undefined -.." newline bitfld.long 0x0 4. "MSMC_CFG_MEM_INIT_DIS_PROXY,Disables MSMC SRAM initialization (Data Cache Tags and Snoop Filters). This is required for proper initial ECC initialization. 1'b0 - Perform memory initialization 1'b1 - Disable memory initialization" "0: Perform memory initialization 1'b1,?" rgroup.long 0x6040++0x3 line.long 0x0 "CFG0_MCU_ENET_CTRL_PROXY," bitfld.long 0x0 4. "MCU_ENET_CTRL_RGMII_ID_MODE_PROXY,Port1 RGMII internal transmit delay selection 0 - Internal transmit delay 1 - No internal transmit delay" "0: Internal transmit delay 1,?" newline bitfld.long 0x0 0.--1. "MCU_ENET_CTRL_MODE_SEL_PROXY,Selects Ethernet switch Port1 interface Field values (others are reserved): 2'b00 - GMII/MII (not supported) 2'b01 - RMII 2'b10 - RGMII 2'b11 - SGMII (not supported)" "0: GMII/MII,1: RMII 2'b10,?,3: SGMII" rgroup.long 0x6060++0x3 line.long 0x0 "CFG0_MCU_SPI1_CTRL_PROXY," bitfld.long 0x0 0. "MCU_SPI1_CTRL_SPI1_LINKDIS_PROXY,Disables direct connection of MCU_SPI1 to SPI3 Field values (others are reserved): 1'b0 - MCU_SPI1 is tied as a slave to SPI3. MCU_SPI1 CLK DATA1 and CS0 are driven from SPI3 DATA OUT drives SPI3 DATA0 1'b1 - MCU_SPI1.." "0: MCU_SPI1 is tied as a slave to SPI3,1: MCU_SPI1 is NOT tied as a slave to SPI3" rgroup.long 0x6070++0x17 line.long 0x0 "CFG0_MCU_I3C0_CTRL0_PROXY," hexmask.long.word 0x0 16.--30. 1. "MCU_I3C0_CTRL0_PID_MFR_ID_PROXY,Manufacturer ID This input corresponds to bits[47:33] of the Provisional ID to identify the manufacturer. Defaults to TI value." newline bitfld.long 0x0 8. "MCU_I3C0_CTRL0_ROLE_PROXY,Master Role 0 - Main master 1 - Secondary master" "0: Main master 1,?" newline hexmask.long.byte 0x0 0.--3. 1. "MCU_I3C0_CTRL0_PID_INSTANCE_PROXY,Provisional ID Instance. This input corresponds to bits[15:12] of the Provisional ID. It is intended to provide a way of differentiating several I3C devices if there would be no other way to have each manufactured.." line.long 0x4 "CFG0_MCU_I3C0_CTRL1_PROXY," hexmask.long.byte 0x4 24.--31. 1. "MCU_I3C0_CTRL1_BUS_AVAIL_TIME_PROXY,Indicates the number of pclk cycles in the Bus Available condition" newline hexmask.long.tbyte 0x4 0.--17. 1. "MCU_I3C0_CTRL1_BUS_IDLE_TIME_PROXY,Indicates the number of pclk cycles in the Bus Idle condition" line.long 0x8 "CFG0_MCU_I3C1_CTRL0_PROXY," hexmask.long.word 0x8 16.--30. 1. "MCU_I3C1_CTRL0_PID_MFR_ID_PROXY,Manufacturer ID This input corresponds to bits[47:33] of the Provisional ID to identify the manufacturer. Defaults to TI value." newline bitfld.long 0x8 8. "MCU_I3C1_CTRL0_ROLE_PROXY,Master Role 0 - Main master 1 - Secondary master" "0: Main master 1,?" newline hexmask.long.byte 0x8 0.--3. 1. "MCU_I3C1_CTRL0_PID_INSTANCE_PROXY,Provisional ID Instance. This input corresponds to bits[15:12] of the Provisional ID. It is intended to provide a way of differentiating several I3C devices if there would be no other way to have each manufactured.." line.long 0xC "CFG0_MCU_I3C1_CTRL1_PROXY," hexmask.long.byte 0xC 24.--31. 1. "MCU_I3C1_CTRL1_BUS_AVAIL_TIME_PROXY,Indicates the number of pclk cycles in the Bus Available condition" newline hexmask.long.tbyte 0xC 0.--17. 1. "MCU_I3C1_CTRL1_BUS_IDLE_TIME_PROXY,Indicates the number of pclk cycles in the Bus Idle condition" line.long 0x10 "CFG0_MCU_I2C0_CTRL_PROXY," bitfld.long 0x10 0. "MCU_I2C0_CTRL_HS_MCS_EN_PROXY,HS Mode master current source enable. When set enables the current-source pull-up on the SCL output. Only one master on the I2C bus should enable SCL current sourcing." "0,1" line.long 0x14 "CFG0_MCU_I2C1_CTRL_PROXY," bitfld.long 0x14 0. "MCU_I2C1_CTRL_HS_MCS_EN_PROXY,HS Mode master current source enable. When set enables the current-source pull-up on the SCL output. Only one master on the I2C bus should enable SCL current sourcing." "0,1" rgroup.long 0x60A0++0x3 line.long 0x0 "CFG0_MCU_FSS_CTRL_PROXY," bitfld.long 0x0 24. "MCU_FSS_CTRL_S1_BOOT_SIZE_PROXY,Selects the size of the boot block to be used for the S1 (OSPI1) flash interface 0 - S1 boot size is 64 MB 1 - S1 boot size is 128 MB" "0: S1 boot size is 64 MB 1,?" newline hexmask.long.byte 0x0 16.--21. 1. "MCU_FSS_CTRL_S1_BOOT_SEG_PROXY,Selects the boot block to be used for the S1 (OSPI1) flash interface. If the s1_boot_size is 128 MB then only bits [4:0] of this field are used. Care must be taken to account for the address translation as to not fall off.." newline bitfld.long 0x0 8. "MCU_FSS_CTRL_S0_BOOT_SIZE_PROXY,Selects the size of the boot block to be used for the S0 (OSPI0 or Hyperbus) flash interface 0 - S0 boot size is 64 MB 1 - S0 boot size is 128 MB" "0: S0 boot size is 64 MB 1,?" newline hexmask.long.byte 0x0 0.--5. 1. "MCU_FSS_CTRL_S0_BOOT_SEG_PROXY,Selects the boot block to be used for the S0 (OSPI0 or Hyperbus) flash interface. If the s0_boot_size is 128 MB then only bits [4:0] of this field are used. Care must be taken to account for the address translation as to.." rgroup.long 0x60B0++0x7 line.long 0x0 "CFG0_MCU_ADC0_CTRL_PROXY," bitfld.long 0x0 16. "MCU_ADC0_CTRL_GPI_MODE_EN_PROXY,Enables MCU_ADC0 data pins to be used as general purpose inputs when set. This signal is tied to the en_dig_test input of MCU_ADC0" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "MCU_ADC0_CTRL_TRIG_SEL_PROXY,Selects the source of the ADC hardware event trigger Field values (others are reserved): 5'b00000 - MCU_ADC_EXT_TRIGGER0 pin 5'b00001 - MCU_ADC_EXT_TRIGGER1 pin 5'b00010 - eHRPWM SOCA event 5'b00011 - eHRPWM SOCB event.." line.long 0x4 "CFG0_MCU_ADC1_CTRL_PROXY," bitfld.long 0x4 16. "MCU_ADC1_CTRL_GPI_MODE_EN_PROXY,Enables MCU_ADC1 data pins to be used as general purpose inputs when set. This signal is tied to the en_dig_test input of MCU_ADC1" "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "MCU_ADC1_CTRL_TRIG_SEL_PROXY,Selects the source of the ADC hardware event trigger Field values (others are reserved): 5'b00000 - MCU_ADC_EXT_TRIGGER0 pin 5'b00001 - MCU_ADC_EXT_TRIGGER1 pin 5'b00010 - eHRPWM SOCA event 5'b00011 - eHRPWM SOCB event.." rgroup.long 0x60C0++0x7 line.long 0x0 "CFG0_MCU_ADC0_TRIM_PROXY," bitfld.long 0x0 24.--26. "MCU_ADC0_TRIM_TRIM5_PROXY,Trim value for C5 0.37 fF to 3.2fF in ~0.37fF increments" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21.--23. "MCU_ADC0_TRIM_TRIM4_PROXY,Trim value for C4 0.37 fF to 3.2fF in ~0.37fF increments" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "MCU_ADC0_TRIM_TRIM3_PROXY,Trim value for C3 0.37 fF to 3.2fF in ~0.37fF increments" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 14.--17. 1. "MCU_ADC0_TRIM_TRIM2_PROXY,Trim value for C2 0.37 fF to 6.4fF in ~0.37fF increments" newline hexmask.long.byte 0x0 10.--13. 1. "MCU_ADC0_TRIM_TRIM1_PROXY,Trim value for C1 0.37 fF to 6.4fF in ~0.37fF increments" newline hexmask.long.byte 0x0 5.--9. 1. "MCU_ADC0_TRIM_ENABLE_CALB_PROXY,Reserved. This bitfield no longer used" newline hexmask.long.byte 0x0 0.--4. 1. "MCU_ADC0_TRIM_ENABLE_CAL_PROXY,Reserved. This bitfield no longer used" line.long 0x4 "CFG0_MCU_ADC1_TRIM_PROXY," bitfld.long 0x4 24.--26. "MCU_ADC1_TRIM_TRIM5_PROXY,Trim value for C5 0.37 fF to 3.2fF in ~0.37fF increments" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 21.--23. "MCU_ADC1_TRIM_TRIM4_PROXY,Trim value for C4 0.37 fF to 3.2fF in ~0.37fF increments" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "MCU_ADC1_TRIM_TRIM3_PROXY,Trim value for C3 0.37 fF to 3.2fF in ~0.37fF increments" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 14.--17. 1. "MCU_ADC1_TRIM_TRIM2_PROXY,Trim value for C2 0.37 fF to 6.4fF in ~0.37fF increments" newline hexmask.long.byte 0x4 10.--13. 1. "MCU_ADC1_TRIM_TRIM1_PROXY,Trim value for C1 0.37 fF to 6.4fF in ~0.37fF increments" newline hexmask.long.byte 0x4 5.--9. 1. "MCU_ADC1_TRIM_ENABLE_CALB_PROXY,Reserved. This bitfield no longer used" newline hexmask.long.byte 0x4 0.--4. 1. "MCU_ADC1_TRIM_ENABLE_CAL_PROXY,Reserved. This bitfield no longer used" rgroup.long 0x60D0++0x7 line.long 0x0 "CFG0_MCU_ADC0_CAL_PROXY," bitfld.long 0x0 15. "MCU_ADC0_CAL_CAL_EN_PROXY,Enable single-ended calibration Set to 1 to begin single-ended calibration" "0,1" newline bitfld.long 0x0 14. "MCU_ADC0_CAL_DIFF_CAL_EN_PROXY,Enable differential calibration Set to 1 to begin differential calibration" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "MCU_ADC0_CAL_CAL_CAP_SEL_PROXY,Select capacitor for calibration Bits correspond to C5:C1 Field values (others are reserved): 5'b00000 - None 5'b00001 - Select C1 5'b00010 - Select C2 5'b00100 - Select C3 5'b01000 - Select C4 5'b10000 - Select C5" line.long 0x4 "CFG0_MCU_ADC1_CAL_PROXY," bitfld.long 0x4 15. "MCU_ADC1_CAL_CAL_EN_PROXY,Enable single-ended calibration Set to 1 to begin single-ended calibration" "0,1" newline bitfld.long 0x4 14. "MCU_ADC1_CAL_DIFF_CAL_EN_PROXY,Enable differential calibration Set to 1 to begin differential calibration" "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "MCU_ADC1_CAL_CAL_CAP_SEL_PROXY,Select capacitor for calibration Bits correspond to C5:C1 Field values (others are reserved): 5'b00000 - None 5'b00001 - Select C1 5'b00010 - Select C2 5'b00100 - Select C3 5'b01000 - Select C4 5'b10000 - Select C5" rgroup.long 0x6200++0x27 line.long 0x0 "CFG0_MCU_TIMER0_CTRL_PROXY," hexmask.long.byte 0x0 0.--3. 1. "MCU_TIMER0_CTRL_CAP_SEL_PROXY,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER0 is configured for capture operation. Field values (others are reserved): 4'b0000 - Use MCU_TIMER_IO0 pin 4'b0001 - Use.." line.long 0x4 "CFG0_MCU_TIMER1_CTRL_PROXY," bitfld.long 0x4 8. "MCU_TIMER1_CTRL_CASCADE_EN_PROXY,When set enables cascading of MCU_TIMER1 to MCU_TIMER0" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "MCU_TIMER1_CTRL_CAP_SEL_PROXY,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER1 is configured for capture operation. Field values (others are reserved): 4'b0000 - Use MCU_TIMER_IO0 pin 4'b0001 - Use.." line.long 0x8 "CFG0_MCU_TIMER2_CTRL_PROXY," hexmask.long.byte 0x8 0.--3. 1. "MCU_TIMER2_CTRL_CAP_SEL_PROXY,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER2 is configured for capture operation. Field values (others are reserved): 4'b0000 - Use MCU_TIMER_IO0 pin 4'b0001 - Use.." line.long 0xC "CFG0_MCU_TIMER3_CTRL_PROXY," bitfld.long 0xC 8. "MCU_TIMER3_CTRL_CASCADE_EN_PROXY,When set enables cascading of MCU_TIMER3 to MCU_TIMER2" "0,1" newline hexmask.long.byte 0xC 0.--3. 1. "MCU_TIMER3_CTRL_CAP_SEL_PROXY,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER3 is configured for capture operation. Field values (others are reserved): 4'b0000 - Use MCU_TIMER_IO0 pin 4'b0001 - Use.." line.long 0x10 "CFG0_MCU_TIMER4_CTRL_PROXY," hexmask.long.byte 0x10 0.--3. 1. "MCU_TIMER4_CTRL_CAP_SEL_PROXY,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER4 is configured for capture operation. Field values (others are reserved): 4'b0000 - Use MCU_TIMER_IO0 pin 4'b0001 - Use.." line.long 0x14 "CFG0_MCU_TIMER5_CTRL_PROXY," bitfld.long 0x14 8. "MCU_TIMER5_CTRL_CASCADE_EN_PROXY,When set enables cascading of MCU_TIMER5 to MCU_TIMER4" "0,1" newline hexmask.long.byte 0x14 0.--3. 1. "MCU_TIMER5_CTRL_CAP_SEL_PROXY,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER5 is configured for capture operation. Field values (others are reserved): 4'b0000 - Use MCU_TIMER_IO0 pin 4'b0001 - Use.." line.long 0x18 "CFG0_MCU_TIMER6_CTRL_PROXY," hexmask.long.byte 0x18 0.--3. 1. "MCU_TIMER6_CTRL_CAP_SEL_PROXY,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER6 is configured for capture operation. Field values (others are reserved): 4'b0000 - Use MCU_TIMER_IO0 pin 4'b0001 - Use.." line.long 0x1C "CFG0_MCU_TIMER7_CTRL_PROXY," bitfld.long 0x1C 8. "MCU_TIMER7_CTRL_CASCADE_EN_PROXY,When set enables cascading of MCU_TIMER7 to MCU_TIMER6" "0,1" newline hexmask.long.byte 0x1C 0.--3. 1. "MCU_TIMER7_CTRL_CAP_SEL_PROXY,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER7 is configured for capture operation. Field values (others are reserved): 4'b0000 - Use MCU_TIMER_IO0 pin 4'b0001 - Use.." line.long 0x20 "CFG0_MCU_TIMER8_CTRL_PROXY," hexmask.long.byte 0x20 0.--3. 1. "MCU_TIMER8_CTRL_CAP_SEL_PROXY,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER8 is configured for capture operation. Field values (others are reserved): 4'b0000 - Use MCU_TIMER_IO0 pin 4'b0001 - Use.." line.long 0x24 "CFG0_MCU_TIMER9_CTRL_PROXY," bitfld.long 0x24 8. "MCU_TIMER9_CTRL_CASCADE_EN_PROXY,When set enables cascading of MCU_TIMER9 to MCU_TIMER8" "0,1" newline hexmask.long.byte 0x24 0.--3. 1. "MCU_TIMER9_CTRL_CAP_SEL_PROXY,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER9 is configured for capture operation. Field values (others are reserved): 4'b0000 - Use MCU_TIMER_IO0 pin 4'b0001 - Use.." rgroup.long 0x6280++0x27 line.long 0x0 "CFG0_MCU_TIMERIO0_CTRL_PROXY," hexmask.long.byte 0x0 0.--3. 1. "MCU_TIMERIO0_CTRL_OUT_SEL_PROXY,Selects the source of the MCU_TIMERIO0 output Field values (others are reserved): 4'b0000 - MCU_TIMERIO0 is driven by MCU_TIMER0 output 4'b0001 - MCU_TIMERIO0 is driven by MCU_TIMER1 output 4'b0010 - MCU_TIMERIO0 is driven.." line.long 0x4 "CFG0_MCU_TIMERIO1_CTRL_PROXY," hexmask.long.byte 0x4 0.--3. 1. "MCU_TIMERIO1_CTRL_OUT_SEL_PROXY,Selects the source of the MCU_TIMERIO1 output Field values (others are reserved): 4'b0000 - MCU_TIMERIO1 is driven by MCU_TIMER0 output 4'b0001 - MCU_TIMERIO1 is driven by MCU_TIMER1 output 4'b0010 - MCU_TIMERIO1 is driven.." line.long 0x8 "CFG0_MCU_TIMERIO2_CTRL_PROXY," hexmask.long.byte 0x8 0.--3. 1. "MCU_TIMERIO2_CTRL_OUT_SEL_PROXY,Selects the source of the MCU_TIMERIO2 output Field values (others are reserved): 4'b0000 - MCU_TIMERIO2 is driven by MCU_TIMER0 output 4'b0001 - MCU_TIMERIO2 is driven by MCU_TIMER1 output 4'b0010 - MCU_TIMERIO2 is driven.." line.long 0xC "CFG0_MCU_TIMERIO3_CTRL_PROXY," hexmask.long.byte 0xC 0.--3. 1. "MCU_TIMERIO3_CTRL_OUT_SEL_PROXY,Selects the source of the MCU_TIMERIO3 output Field values (others are reserved): 4'b0000 - MCU_TIMERIO3 is driven by MCU_TIMER0 output 4'b0001 - MCU_TIMERIO3 is driven by MCU_TIMER1 output 4'b0010 - MCU_TIMERIO3 is driven.." line.long 0x10 "CFG0_MCU_TIMERIO4_CTRL_PROXY," hexmask.long.byte 0x10 0.--3. 1. "MCU_TIMERIO4_CTRL_OUT_SEL_PROXY,Selects the source of the MCU_TIMERIO4 output Field values (others are reserved): 4'b0000 - MCU_TIMERIO4 is driven by MCU_TIMER0 output 4'b0001 - MCU_TIMERIO4 is driven by MCU_TIMER1 output 4'b0010 - MCU_TIMERIO4 is driven.." line.long 0x14 "CFG0_MCU_TIMERIO5_CTRL_PROXY," hexmask.long.byte 0x14 0.--3. 1. "MCU_TIMERIO5_CTRL_OUT_SEL_PROXY,Selects the source of the MCU_TIMERIO5 output Field values (others are reserved): 4'b0000 - MCU_TIMERIO5 is driven by MCU_TIMER0 output 4'b0001 - MCU_TIMERIO5 is driven by MCU_TIMER1 output 4'b0010 - MCU_TIMERIO5 is driven.." line.long 0x18 "CFG0_MCU_TIMERIO6_CTRL_PROXY," hexmask.long.byte 0x18 0.--3. 1. "MCU_TIMERIO6_CTRL_OUT_SEL_PROXY,Selects the source of the MCU_TIMERIO6 output Field values (others are reserved): 4'b0000 - MCU_TIMERIO6 is driven by MCU_TIMER0 output 4'b0001 - MCU_TIMERIO6 is driven by MCU_TIMER1 output 4'b0010 - MCU_TIMERIO6 is driven.." line.long 0x1C "CFG0_MCU_TIMERIO7_CTRL_PROXY," hexmask.long.byte 0x1C 0.--3. 1. "MCU_TIMERIO7_CTRL_OUT_SEL_PROXY,Selects the source of the MCU_TIMERIO7 output Field values (others are reserved): 4'b0000 - MCU_TIMERIO7 is driven by MCU_TIMER0 output 4'b0001 - MCU_TIMERIO7 is driven by MCU_TIMER1 output 4'b0010 - MCU_TIMERIO7 is driven.." line.long 0x20 "CFG0_MCU_TIMERIO8_CTRL_PROXY," hexmask.long.byte 0x20 0.--3. 1. "MCU_TIMERIO8_CTRL_OUT_SEL_PROXY,Selects the source of the MCU_TIMERIO8 output Field values (others are reserved): 4'b0000 - MCU_TIMERIO8 is driven by MCU_TIMER0 output 4'b0001 - MCU_TIMERIO8 is driven by MCU_TIMER1 output 4'b0010 - MCU_TIMERIO8 is driven.." line.long 0x24 "CFG0_MCU_TIMERIO9_CTRL_PROXY," hexmask.long.byte 0x24 0.--3. 1. "MCU_TIMERIO9_CTRL_OUT_SEL_PROXY,Selects the source of the MCU_TIMERIO9 output Field values (others are reserved): 4'b0000 - MCU_TIMERIO9 is driven by MCU_TIMER0 output 4'b0001 - MCU_TIMERIO9 is driven by MCU_TIMER1 output 4'b0010 - MCU_TIMERIO9 is driven.." rgroup.long 0x6300++0x3 line.long 0x0 "CFG0_MCU_MTOG0_CTRL_PROXY," rbitfld.long 0x0 31. "MCU_MTOG0_CTRL_IDLE_STAT_PROXY,Idle status When high indicates MTOG0 is idle." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "MCU_MTOG0_CTRL_FORCE_TIMEOUT_PROXY,Force Timeout Forces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and timeout_en bitfields must be.." newline bitfld.long 0x0 15. "MCU_MTOG0_CTRL_TIMEOUT_EN_PROXY,Timeout Enable 1'b0 - Disable the gasket. Clear the interrupt and reset the counter 1'b1 - Enable the timeout gasket functions" "0: Disable the gasket,1: Enable the timeout gasket functions" newline bitfld.long 0x0 0.--2. "MCU_MTOG0_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout Value Selects the number of clock cycles before the interface is considered to have timed out Field values (others are reserved): 3'b000 - 1024 clock cycles 3'b001 - 4096 clock cycles 3'b010 - 16 384 clock.." "0,1,2,3,4,5,6,7" rgroup.long 0x7008++0x7 line.long 0x0 "CFG0_LOCK1_KICK0_PROXY," hexmask.long 0x0 0.--31. 1. "LOCK1_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK1_KICK1_PROXY," hexmask.long 0x4 0.--31. 1. "LOCK1_KICK1_PROXY,- KICK1 component" rgroup.long 0x7100++0x1B line.long 0x0 "CFG0_CLAIMREG_P1_R0," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P1_R0,Claim bits for Partition 1" line.long 0x4 "CFG0_CLAIMREG_P1_R1," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P1_R1,Claim bits for Partition 1" line.long 0x8 "CFG0_CLAIMREG_P1_R2," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P1_R2,Claim bits for Partition 1" line.long 0xC "CFG0_CLAIMREG_P1_R3," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P1_R3,Claim bits for Partition 1" line.long 0x10 "CFG0_CLAIMREG_P1_R4," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P1_R4,Claim bits for Partition 1" line.long 0x14 "CFG0_CLAIMREG_P1_R5," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P1_R5,Claim bits for Partition 1" line.long 0x18 "CFG0_CLAIMREG_P1_R6," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P1_R6,Claim bits for Partition 1" rgroup.long 0x8010++0x3 line.long 0x0 "CFG0_MCU_CLKOUT0_CTRL," bitfld.long 0x0 4. "MCU_CLKOUT0_CTRL_CLK_EN,When set enables MCU_CLKOUT0 output" "0,1" newline bitfld.long 0x0 0. "MCU_CLKOUT0_CTRL_CLK_SEL,Selects MCU_CLKOUT0 clock source 1'b0 - RGMII_MHZ_50_CLK (50 MHz) 1'b1 -RGMII_MHZ_50_CLK / 2 (25 MHz)" "0: RGMII_MHZ_50_CLK,1: RGMII_MHZ_50_CLK / 2" rgroup.long 0x8018++0x3 line.long 0x0 "CFG0_MCU_EFUSE_CLKSEL," bitfld.long 0x0 0. "MCU_EFUSE_CLKSEL_CLK_SEL,Selects the clock source Field values (others are reserved): 1'b0 - EFUSE_CLK (HFOSC0_CLKOUT or CLK_12M_RC) 1'b1 - MCU_SYSCLK0 / 8" "0: EFUSE_CLK,1: MCU_SYSCLK0 / 8" rgroup.long 0x8020++0x7 line.long 0x0 "CFG0_MCU_MCAN0_CLKSEL," bitfld.long 0x0 0.--1. "MCU_MCAN0_CLKSEL_CLK_SEL,MCU_MCAN MCAN_CLK selection 2'b00 - MCU_PLL2_HSDIV3_CLKOUT 2'b01 - MCU_EXT_REFCLK0 2'b10 - MCU_PLL1_HSDIV2_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MCU_PLL2_HSDIV3_CLKOUT 2'b01,?,2: MCU_PLL1_HSDIV2_CLKOUT 2'b11,?" line.long 0x4 "CFG0_MCU_MCAN1_CLKSEL," bitfld.long 0x4 0.--1. "MCU_MCAN1_CLKSEL_CLK_SEL,MCU_MCAN MCAN_CLK selection 2'b00 - MCU_PLL2_HSDIV3_CLKOUT 2'b01 - MCU_EXT_REFCLK0 2'b10 - MCU_PLL1_HSDIV2_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MCU_PLL2_HSDIV3_CLKOUT 2'b01,?,2: MCU_PLL1_HSDIV2_CLKOUT 2'b11,?" rgroup.long 0x8030++0x7 line.long 0x0 "CFG0_MCU_OSPI0_CLKSEL," bitfld.long 0x0 4. "MCU_OSPI0_CLKSEL_LOOPCLK_SEL,OBSPI0 Loopback clock source 1'b0 - OSPI_DQS external pin (external) 1'b1 - OSPI_LBCLKO output (internal)" "0: OSPI_DQS external pin,1: OSPI_LBCLKO output" newline bitfld.long 0x0 0. "MCU_OSPI0_CLKSEL_CLK_SEL,OSPI0 reference clock selection 1'b0 - MCU_PLL1_HSDIV4_CLKOUT 1'b1 - MCU_PLL2_HSDIV4_CLKOUT" "0: MCU_PLL1_HSDIV4_CLKOUT 1'b1,?" line.long 0x4 "CFG0_MCU_OSPI1_CLKSEL," bitfld.long 0x4 4. "MCU_OSPI1_CLKSEL_LOOPCLK_SEL,OBSPI1 Loopback clock source 1'b0 - OSPI_DQS external pin (external) 1'b1 - OSPI_LBCLKO output (internal)" "0: OSPI_DQS external pin,1: OSPI_LBCLKO output" newline bitfld.long 0x4 0. "MCU_OSPI1_CLKSEL_CLK_SEL,OSPI1 reference clock selection 1'b0 - MCU_PLL1_HSDIV4_CLKOUT 1'b1 - MCU_PLL2_HSDIV4_CLKOUT" "0: MCU_PLL1_HSDIV4_CLKOUT 1'b1,?" rgroup.long 0x8040++0x7 line.long 0x0 "CFG0_MCU_ADC0_CLKSEL," bitfld.long 0x0 0.--1. "MCU_ADC0_CLKSEL_CLK_SEL,Selects the sampling clock source for ADC0 Field values (others are reserved): 2'b00 - HFOSC0_CLKOUT 2'b01 - MCU_PLL1_HSDIV1_CLKOUT1 2'b10 - MCU_PLL0_HSDIV1_CLKOUT1 2'b11 - MCU_EXT_REFCLK0" "0: HFOSC0_CLKOUT 2'b01,?,2: MCU_PLL0_HSDIV1_CLKOUT1 2'b11,?" line.long 0x4 "CFG0_MCU_ADC1_CLKSEL," bitfld.long 0x4 0.--1. "MCU_ADC1_CLKSEL_CLK_SEL,Selects the sampling clock source for ADC1 Field values (others are reserved): 2'b00 - HFOSC0_CLKOUT 2'b01 - MCU_PLL1_HSDIV1_CLKOUT1 2'b10 - MCU_PLL0_HSDIV1_CLKOUT1 2'b11 - MCU_EXT_REFCLK0" "0: HFOSC0_CLKOUT 2'b01,?,2: MCU_PLL0_HSDIV1_CLKOUT1 2'b11,?" rgroup.long 0x8050++0x3 line.long 0x0 "CFG0_MCU_ENET_CLKSEL," hexmask.long.byte 0x0 8.--11. 1. "MCU_ENET_CLKSEL_CPTS_CLKSEL,Selects the clock source for the CPSW2x Ethernet switch Common Platform Time Stamp module Field values (others are reserved): 4'b0000 - MAIN_PLL3_HSDIV1_CLKOUT 4'b0001 - MAIN_PLL0_HSDIV6_CLKOUT 4'b0010 - MCU_CPTS_REF_CLK (pin).." newline bitfld.long 0x0 0. "MCU_ENET_CLKSEL_RMII_CLK_SEL,Selects the rmii clock (rmii_mhz_50_clk) source. This defaults to the internal 50 MHz clock source for proper clockstop operation 1'b0 - MCU_PLL2_HSDIV0_CLKOUT / 5 1'b1 - MCU_RMII_REFCLK (pin)" "0: MCU_PLL2_HSDIV0_CLKOUT / 5 1'b1,?" rgroup.long 0x8080++0x7 line.long 0x0 "CFG0_MCU_R5_CORE0_CLKSEL," bitfld.long 0x0 0. "MCU_R5_CORE0_CLKSEL_CLK_SEL,Selects the Core 0 functional clock and mcu/interface clock ratio. Note this value must only be changed when the MCU R5 is powered off or in WFI 1'b0 - Use MCU_SYSCLK0. MCU/interface is 3:1 clock ratio 1'b1 - Use.." "0: Use MCU_SYSCLK0,1: Use MCU_SYSCLK0/3" line.long 0x4 "CFG0_MCU_R5_CORE1_CLKSEL," bitfld.long 0x4 0. "MCU_R5_CORE1_CLKSEL_CLK_SEL,Selects the Core 1 functional clock and mcu/interface clock ratio. Note this value must only be changed when the MCU R5 is powered off or in WFI 1'b0 - Use MCU_SYSCLK0. MCU/interface is 3:1 clock ratio 1'b1 - Use.." "0: Use MCU_SYSCLK0,1: Use MCU_SYSCLK0/3" rgroup.long 0x8100++0x27 line.long 0x0 "CFG0_MCU_TIMER0_CLKSEL," bitfld.long 0x0 0.--2. "MCU_TIMER0_CLKSEL_CLK_SEL,Timer functional clock input select mux control Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 4 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL2_HSDIV2_CLKOUT 3'b100 - MCU_EXT_REFCLK0 3'b101 -.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: MCU_EXT_REFCLK0 3'b101,?,6: CPSW_GENF0 3'b111,?" line.long 0x4 "CFG0_MCU_TIMER1_CLKSEL," bitfld.long 0x4 0.--2. "MCU_TIMER1_CLKSEL_CLK_SEL,Timer functional clock input select mux control Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 4 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL2_HSDIV2_CLKOUT 3'b100 - MCU_EXT_REFCLK0 3'b101 -.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: MCU_EXT_REFCLK0 3'b101,?,6: CPSW_GENF0 3'b111,?" line.long 0x8 "CFG0_MCU_TIMER2_CLKSEL," bitfld.long 0x8 0.--2. "MCU_TIMER2_CLKSEL_CLK_SEL,Timer functional clock input select mux control Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 4 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL2_HSDIV2_CLKOUT 3'b100 - MCU_EXT_REFCLK0 3'b101 -.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: MCU_EXT_REFCLK0 3'b101,?,6: CPSW_GENF0 3'b111,?" line.long 0xC "CFG0_MCU_TIMER3_CLKSEL," bitfld.long 0xC 0.--2. "MCU_TIMER3_CLKSEL_CLK_SEL,Timer functional clock input select mux control Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 4 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL2_HSDIV2_CLKOUT 3'b100 - MCU_EXT_REFCLK0 3'b101 -.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: MCU_EXT_REFCLK0 3'b101,?,6: CPSW_GENF0 3'b111,?" line.long 0x10 "CFG0_MCU_TIMER4_CLKSEL," bitfld.long 0x10 0.--2. "MCU_TIMER4_CLKSEL_CLK_SEL,Timer functional clock input select mux control Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 4 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL2_HSDIV2_CLKOUT 3'b100 - MCU_EXT_REFCLK0 3'b101 -.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: MCU_EXT_REFCLK0 3'b101,?,6: CPSW_GENF0 3'b111,?" line.long 0x14 "CFG0_MCU_TIMER5_CLKSEL," bitfld.long 0x14 0.--2. "MCU_TIMER5_CLKSEL_CLK_SEL,Timer functional clock input select mux control Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 4 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL2_HSDIV2_CLKOUT 3'b100 - MCU_EXT_REFCLK0 3'b101 -.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: MCU_EXT_REFCLK0 3'b101,?,6: CPSW_GENF0 3'b111,?" line.long 0x18 "CFG0_MCU_TIMER6_CLKSEL," bitfld.long 0x18 0.--2. "MCU_TIMER6_CLKSEL_CLK_SEL,Timer functional clock input select mux control Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 4 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL2_HSDIV2_CLKOUT 3'b100 - MCU_EXT_REFCLK0 3'b101 -.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: MCU_EXT_REFCLK0 3'b101,?,6: CPSW_GENF0 3'b111,?" line.long 0x1C "CFG0_MCU_TIMER7_CLKSEL," bitfld.long 0x1C 0.--2. "MCU_TIMER7_CLKSEL_CLK_SEL,Timer functional clock input select mux control Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 4 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL2_HSDIV2_CLKOUT 3'b100 - MCU_EXT_REFCLK0 3'b101 -.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: MCU_EXT_REFCLK0 3'b101,?,6: CPSW_GENF0 3'b111,?" line.long 0x20 "CFG0_MCU_TIMER8_CLKSEL," bitfld.long 0x20 0.--2. "MCU_TIMER8_CLKSEL_CLK_SEL,Timer functional clock input select mux control Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 4 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL2_HSDIV2_CLKOUT 3'b100 - MCU_EXT_REFCLK0 3'b101 -.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: MCU_EXT_REFCLK0 3'b101,?,6: CPSW_GENF0 3'b111,?" line.long 0x24 "CFG0_MCU_TIMER9_CLKSEL," bitfld.long 0x24 0.--2. "MCU_TIMER9_CLKSEL_CLK_SEL,Timer functional clock input select mux control Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 4 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL2_HSDIV2_CLKOUT 3'b100 - MCU_EXT_REFCLK0 3'b101 -.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: MCU_EXT_REFCLK0 3'b101,?,6: CPSW_GENF0 3'b111,?" rgroup.long 0x8180++0x7 line.long 0x0 "CFG0_MCU_RTI0_CLKSEL," bitfld.long 0x0 31. "MCU_RTI0_CLKSEL_WRTLOCK,When set locks further writes to MCU_RTI0_CLKSEL until the next module reset" "0,1" newline bitfld.long 0x0 0.--2. "MCU_RTI0_CLKSEL_CLK_SEL,RTI functional clock input select mux control Field values (others are reserved): 2'b00 - HFOSC0_CLKOUT 2'b01 - LFXOSC_CLKOUT 2'b10 - CLK_12M_RC 2'b11 - CLK_32K" "0: HFOSC0_CLKOUT 2'b01,?,2: CLK_12M_RC 2'b11,?,?,?,?,?" line.long 0x4 "CFG0_MCU_RTI1_CLKSEL," bitfld.long 0x4 31. "MCU_RTI1_CLKSEL_WRTLOCK,When set locks further writes to MCU_RTI1_CLKSEL until the next module reset" "0,1" newline bitfld.long 0x4 0.--2. "MCU_RTI1_CLKSEL_CLK_SEL,RTI functional clock input select mux control Field values (others are reserved): 2'b00 - HFOSC0_CLKOUT 2'b01 - LFXOSC_CLKOUT 2'b10 - CLK_12M_RC 2'b11 - CLK_32K" "0: HFOSC0_CLKOUT 2'b01,?,2: CLK_12M_RC 2'b11,?,?,?,?,?" rgroup.long 0x81C0++0x3 line.long 0x0 "CFG0_MCU_USART_CLKSEL," bitfld.long 0x0 0. "MCU_USART_CLKSEL_CLK_SEL,MCU_USART0 FCLK selection 1'b0 - MCU_PLL1_HSDIV3_CLKOUT 1'b1 - MAIN_PLL1_HSDIV5_CLKOUT" "0: MCU_PLL1_HSDIV3_CLKOUT 1'b1,?" rgroup.long 0x9008++0x7 line.long 0x0 "CFG0_LOCK2_KICK0," hexmask.long 0x0 0.--31. 1. "LOCK2_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK2_KICK1," hexmask.long 0x4 0.--31. 1. "LOCK2_KICK1,- KICK1 component" rgroup.long 0x9100++0xF line.long 0x0 "CFG0_CLAIMREG_P2_R0_READONLY," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P2_R0_READONLY,Claim bits for Partition 2" line.long 0x4 "CFG0_CLAIMREG_P2_R1_READONLY," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P2_R1_READONLY,Claim bits for Partition 2" line.long 0x8 "CFG0_CLAIMREG_P2_R2_READONLY," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P2_R2_READONLY,Claim bits for Partition 2" line.long 0xC "CFG0_CLAIMREG_P2_R3_READONLY," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P2_R3_READONLY,Claim bits for Partition 2" rgroup.long 0xA010++0x3 line.long 0x0 "CFG0_MCU_CLKOUT0_CTRL_PROXY," bitfld.long 0x0 4. "MCU_CLKOUT0_CTRL_CLK_EN_PROXY,When set enables MCU_CLKOUT0 output" "0,1" newline bitfld.long 0x0 0. "MCU_CLKOUT0_CTRL_CLK_SEL_PROXY,Selects MCU_CLKOUT0 clock source 1'b0 - RGMII_MHZ_50_CLK (50 MHz) 1'b1 -RGMII_MHZ_50_CLK / 2 (25 MHz)" "0: RGMII_MHZ_50_CLK,1: RGMII_MHZ_50_CLK / 2" rgroup.long 0xA018++0x3 line.long 0x0 "CFG0_MCU_EFUSE_CLKSEL_PROXY," bitfld.long 0x0 0. "MCU_EFUSE_CLKSEL_CLK_SEL_PROXY,Selects the clock source Field values (others are reserved): 1'b0 - EFUSE_CLK (HFOSC0_CLKOUT or CLK_12M_RC) 1'b1 - MCU_SYSCLK0 / 8" "0: EFUSE_CLK,1: MCU_SYSCLK0 / 8" rgroup.long 0xA020++0x7 line.long 0x0 "CFG0_MCU_MCAN0_CLKSEL_PROXY," bitfld.long 0x0 0.--1. "MCU_MCAN0_CLKSEL_CLK_SEL_PROXY,MCU_MCAN MCAN_CLK selection 2'b00 - MCU_PLL2_HSDIV3_CLKOUT 2'b01 - MCU_EXT_REFCLK0 2'b10 - MCU_PLL1_HSDIV2_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MCU_PLL2_HSDIV3_CLKOUT 2'b01,?,2: MCU_PLL1_HSDIV2_CLKOUT 2'b11,?" line.long 0x4 "CFG0_MCU_MCAN1_CLKSEL_PROXY," bitfld.long 0x4 0.--1. "MCU_MCAN1_CLKSEL_CLK_SEL_PROXY,MCU_MCAN MCAN_CLK selection 2'b00 - MCU_PLL2_HSDIV3_CLKOUT 2'b01 - MCU_EXT_REFCLK0 2'b10 - MCU_PLL1_HSDIV2_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0: MCU_PLL2_HSDIV3_CLKOUT 2'b01,?,2: MCU_PLL1_HSDIV2_CLKOUT 2'b11,?" rgroup.long 0xA030++0x7 line.long 0x0 "CFG0_MCU_OSPI0_CLKSEL_PROXY," bitfld.long 0x0 4. "MCU_OSPI0_CLKSEL_LOOPCLK_SEL_PROXY,OBSPI0 Loopback clock source 1'b0 - OSPI_DQS external pin (external) 1'b1 - OSPI_LBCLKO output (internal)" "0: OSPI_DQS external pin,1: OSPI_LBCLKO output" newline bitfld.long 0x0 0. "MCU_OSPI0_CLKSEL_CLK_SEL_PROXY,OSPI0 reference clock selection 1'b0 - MCU_PLL1_HSDIV4_CLKOUT 1'b1 - MCU_PLL2_HSDIV4_CLKOUT" "0: MCU_PLL1_HSDIV4_CLKOUT 1'b1,?" line.long 0x4 "CFG0_MCU_OSPI1_CLKSEL_PROXY," bitfld.long 0x4 4. "MCU_OSPI1_CLKSEL_LOOPCLK_SEL_PROXY,OBSPI1 Loopback clock source 1'b0 - OSPI_DQS external pin (external) 1'b1 - OSPI_LBCLKO output (internal)" "0: OSPI_DQS external pin,1: OSPI_LBCLKO output" newline bitfld.long 0x4 0. "MCU_OSPI1_CLKSEL_CLK_SEL_PROXY,OSPI1 reference clock selection 1'b0 - MCU_PLL1_HSDIV4_CLKOUT 1'b1 - MCU_PLL2_HSDIV4_CLKOUT" "0: MCU_PLL1_HSDIV4_CLKOUT 1'b1,?" rgroup.long 0xA040++0x7 line.long 0x0 "CFG0_MCU_ADC0_CLKSEL_PROXY," bitfld.long 0x0 0.--1. "MCU_ADC0_CLKSEL_CLK_SEL_PROXY,Selects the sampling clock source for ADC0 Field values (others are reserved): 2'b00 - HFOSC0_CLKOUT 2'b01 - MCU_PLL1_HSDIV1_CLKOUT1 2'b10 - MCU_PLL0_HSDIV1_CLKOUT1 2'b11 - MCU_EXT_REFCLK0" "0: HFOSC0_CLKOUT 2'b01,?,2: MCU_PLL0_HSDIV1_CLKOUT1 2'b11,?" line.long 0x4 "CFG0_MCU_ADC1_CLKSEL_PROXY," bitfld.long 0x4 0.--1. "MCU_ADC1_CLKSEL_CLK_SEL_PROXY,Selects the sampling clock source for ADC1 Field values (others are reserved): 2'b00 - HFOSC0_CLKOUT 2'b01 - MCU_PLL1_HSDIV1_CLKOUT1 2'b10 - MCU_PLL0_HSDIV1_CLKOUT1 2'b11 - MCU_EXT_REFCLK0" "0: HFOSC0_CLKOUT 2'b01,?,2: MCU_PLL0_HSDIV1_CLKOUT1 2'b11,?" rgroup.long 0xA050++0x3 line.long 0x0 "CFG0_MCU_ENET_CLKSEL_PROXY," hexmask.long.byte 0x0 8.--11. 1. "MCU_ENET_CLKSEL_CPTS_CLKSEL_PROXY,Selects the clock source for the CPSW2x Ethernet switch Common Platform Time Stamp module Field values (others are reserved): 4'b0000 - MAIN_PLL3_HSDIV1_CLKOUT 4'b0001 - MAIN_PLL0_HSDIV6_CLKOUT 4'b0010 - MCU_CPTS_REF_CLK.." newline bitfld.long 0x0 0. "MCU_ENET_CLKSEL_RMII_CLK_SEL_PROXY,Selects the rmii clock (rmii_mhz_50_clk) source. This defaults to the internal 50 MHz clock source for proper clockstop operation 1'b0 - MCU_PLL2_HSDIV0_CLKOUT / 5 1'b1 - MCU_RMII_REFCLK (pin)" "0: MCU_PLL2_HSDIV0_CLKOUT / 5 1'b1,?" rgroup.long 0xA080++0x7 line.long 0x0 "CFG0_MCU_R5_CORE0_CLKSEL_PROXY," bitfld.long 0x0 0. "MCU_R5_CORE0_CLKSEL_CLK_SEL_PROXY,Selects the Core 0 functional clock and mcu/interface clock ratio. Note this value must only be changed when the MCU R5 is powered off or in WFI 1'b0 - Use MCU_SYSCLK0. MCU/interface is 3:1 clock ratio 1'b1 - Use.." "0: Use MCU_SYSCLK0,1: Use MCU_SYSCLK0/3" line.long 0x4 "CFG0_MCU_R5_CORE1_CLKSEL_PROXY," bitfld.long 0x4 0. "MCU_R5_CORE1_CLKSEL_CLK_SEL_PROXY,Selects the Core 1 functional clock and mcu/interface clock ratio. Note this value must only be changed when the MCU R5 is powered off or in WFI 1'b0 - Use MCU_SYSCLK0. MCU/interface is 3:1 clock ratio 1'b1 - Use.." "0: Use MCU_SYSCLK0,1: Use MCU_SYSCLK0/3" rgroup.long 0xA100++0x27 line.long 0x0 "CFG0_MCU_TIMER0_CLKSEL_PROXY," bitfld.long 0x0 0.--2. "MCU_TIMER0_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 4 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL2_HSDIV2_CLKOUT 3'b100 - MCU_EXT_REFCLK0 3'b101 -.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: MCU_EXT_REFCLK0 3'b101,?,6: CPSW_GENF0 3'b111,?" line.long 0x4 "CFG0_MCU_TIMER1_CLKSEL_PROXY," bitfld.long 0x4 0.--2. "MCU_TIMER1_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 4 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL2_HSDIV2_CLKOUT 3'b100 - MCU_EXT_REFCLK0 3'b101 -.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: MCU_EXT_REFCLK0 3'b101,?,6: CPSW_GENF0 3'b111,?" line.long 0x8 "CFG0_MCU_TIMER2_CLKSEL_PROXY," bitfld.long 0x8 0.--2. "MCU_TIMER2_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 4 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL2_HSDIV2_CLKOUT 3'b100 - MCU_EXT_REFCLK0 3'b101 -.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: MCU_EXT_REFCLK0 3'b101,?,6: CPSW_GENF0 3'b111,?" line.long 0xC "CFG0_MCU_TIMER3_CLKSEL_PROXY," bitfld.long 0xC 0.--2. "MCU_TIMER3_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 4 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL2_HSDIV2_CLKOUT 3'b100 - MCU_EXT_REFCLK0 3'b101 -.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: MCU_EXT_REFCLK0 3'b101,?,6: CPSW_GENF0 3'b111,?" line.long 0x10 "CFG0_MCU_TIMER4_CLKSEL_PROXY," bitfld.long 0x10 0.--2. "MCU_TIMER4_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 4 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL2_HSDIV2_CLKOUT 3'b100 - MCU_EXT_REFCLK0 3'b101 -.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: MCU_EXT_REFCLK0 3'b101,?,6: CPSW_GENF0 3'b111,?" line.long 0x14 "CFG0_MCU_TIMER5_CLKSEL_PROXY," bitfld.long 0x14 0.--2. "MCU_TIMER5_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 4 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL2_HSDIV2_CLKOUT 3'b100 - MCU_EXT_REFCLK0 3'b101 -.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: MCU_EXT_REFCLK0 3'b101,?,6: CPSW_GENF0 3'b111,?" line.long 0x18 "CFG0_MCU_TIMER6_CLKSEL_PROXY," bitfld.long 0x18 0.--2. "MCU_TIMER6_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 4 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL2_HSDIV2_CLKOUT 3'b100 - MCU_EXT_REFCLK0 3'b101 -.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: MCU_EXT_REFCLK0 3'b101,?,6: CPSW_GENF0 3'b111,?" line.long 0x1C "CFG0_MCU_TIMER7_CLKSEL_PROXY," bitfld.long 0x1C 0.--2. "MCU_TIMER7_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 4 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL2_HSDIV2_CLKOUT 3'b100 - MCU_EXT_REFCLK0 3'b101 -.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: MCU_EXT_REFCLK0 3'b101,?,6: CPSW_GENF0 3'b111,?" line.long 0x20 "CFG0_MCU_TIMER8_CLKSEL_PROXY," bitfld.long 0x20 0.--2. "MCU_TIMER8_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 4 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL2_HSDIV2_CLKOUT 3'b100 - MCU_EXT_REFCLK0 3'b101 -.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: MCU_EXT_REFCLK0 3'b101,?,6: CPSW_GENF0 3'b111,?" line.long 0x24 "CFG0_MCU_TIMER9_CLKSEL_PROXY," bitfld.long 0x24 0.--2. "MCU_TIMER9_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 4 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL2_HSDIV2_CLKOUT 3'b100 - MCU_EXT_REFCLK0 3'b101 -.." "0: HFOSC0_CLKOUT 3'b001,?,2: CLK_12M_RC 3'b011,?,4: MCU_EXT_REFCLK0 3'b101,?,6: CPSW_GENF0 3'b111,?" rgroup.long 0xA180++0x7 line.long 0x0 "CFG0_MCU_RTI0_CLKSEL_PROXY," bitfld.long 0x0 31. "MCU_RTI0_CLKSEL_WRTLOCK_PROXY,When set locks further writes to MCU_RTI0_CLKSEL until the next module reset" "0,1" newline bitfld.long 0x0 0.--2. "MCU_RTI0_CLKSEL_CLK_SEL_PROXY,RTI functional clock input select mux control Field values (others are reserved): 2'b00 - HFOSC0_CLKOUT 2'b01 - LFXOSC_CLKOUT 2'b10 - CLK_12M_RC 2'b11 - CLK_32K" "0: HFOSC0_CLKOUT 2'b01,?,2: CLK_12M_RC 2'b11,?,?,?,?,?" line.long 0x4 "CFG0_MCU_RTI1_CLKSEL_PROXY," bitfld.long 0x4 31. "MCU_RTI1_CLKSEL_WRTLOCK_PROXY,When set locks further writes to MCU_RTI1_CLKSEL until the next module reset" "0,1" newline bitfld.long 0x4 0.--2. "MCU_RTI1_CLKSEL_CLK_SEL_PROXY,RTI functional clock input select mux control Field values (others are reserved): 2'b00 - HFOSC0_CLKOUT 2'b01 - LFXOSC_CLKOUT 2'b10 - CLK_12M_RC 2'b11 - CLK_32K" "0: HFOSC0_CLKOUT 2'b01,?,2: CLK_12M_RC 2'b11,?,?,?,?,?" rgroup.long 0xA1C0++0x3 line.long 0x0 "CFG0_MCU_USART_CLKSEL_PROXY," bitfld.long 0x0 0. "MCU_USART_CLKSEL_CLK_SEL_PROXY,MCU_USART0 FCLK selection 1'b0 - MCU_PLL1_HSDIV3_CLKOUT 1'b1 - MAIN_PLL1_HSDIV5_CLKOUT" "0: MCU_PLL1_HSDIV3_CLKOUT 1'b1,?" rgroup.long 0xB008++0x7 line.long 0x0 "CFG0_LOCK2_KICK0_PROXY," hexmask.long 0x0 0.--31. 1. "LOCK2_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK2_KICK1_PROXY," hexmask.long 0x4 0.--31. 1. "LOCK2_KICK1_PROXY,- KICK1 component" rgroup.long 0xB100++0xF line.long 0x0 "CFG0_CLAIMREG_P2_R0," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P2_R0,Claim bits for Partition 2" line.long 0x4 "CFG0_CLAIMREG_P2_R1," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P2_R1,Claim bits for Partition 2" line.long 0x8 "CFG0_CLAIMREG_P2_R2," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P2_R2,Claim bits for Partition 2" line.long 0xC "CFG0_CLAIMREG_P2_R3," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P2_R3,Claim bits for Partition 2" rgroup.long 0xC000++0x1B line.long 0x0 "CFG0_MCU_LBIST_CTRL," bitfld.long 0x0 31. "MCU_LBIST_CTRL_BIST_RESET,Reset LBIST macro (active low)" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "MCU_LBIST_CTRL_BIST_RUN,Starts LBIST if all bits are 1" newline hexmask.long.byte 0x0 12.--15. 1. "MCU_LBIST_CTRL_RUNBIST_MODE,Runbist mode enable if all bits are 1" newline bitfld.long 0x0 8.--9. "MCU_LBIST_CTRL_DC_DEF,Clock delay after scan_enable switching" "0,1,2,3" newline bitfld.long 0x0 7. "MCU_LBIST_CTRL_LOAD_DIV,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "MCU_LBIST_CTRL_DIVIDE_RATIO,LBIST clock divide ratio" line.long 0x4 "CFG0_MCU_LBIST_PATCOUNT," hexmask.long.word 0x4 16.--29. 1. "MCU_LBIST_PATCOUNT_STATIC_PC_DEF,Number of stuck-at patterns to run" newline hexmask.long.byte 0x4 8.--11. 1. "MCU_LBIST_PATCOUNT_SET_PC_DEF,Number of set patterns to run" newline hexmask.long.byte 0x4 4.--7. 1. "MCU_LBIST_PATCOUNT_RESET_PC_DEF,Number of reset patterns to run" newline hexmask.long.byte 0x4 0.--3. 1. "MCU_LBIST_PATCOUNT_SCAN_PC_DEF,Number of chain test patterns to run" line.long 0x8 "CFG0_MCU_LBIST_SEED0," hexmask.long 0x8 0.--31. 1. "MCU_LBIST_SEED0_PRPG_DEF,Initial seed for PRPG (bits 31:0)" line.long 0xC "CFG0_MCU_LBIST_SEED1," hexmask.long.tbyte 0xC 0.--20. 1. "MCU_LBIST_SEED1_PRPG_DEF,Initial seed for PRPG (bits 52:32)" line.long 0x10 "CFG0_MCU_LBIST_SPARE0," hexmask.long 0x10 2.--31. 1. "MCU_LBIST_SPARE0_SPARE0,LBIST spare bits" newline bitfld.long 0x10 1. "MCU_LBIST_SPARE0_PBIST_SELFTEST_EN,PBIST isolation control" "0,1" newline bitfld.long 0x10 0. "MCU_LBIST_SPARE0_LBIST_SELFTEST_EN,LBIST isolation control" "0,1" line.long 0x14 "CFG0_MCU_LBIST_SPARE1," hexmask.long 0x14 0.--31. 1. "MCU_LBIST_SPARE1_SPARE1,LBIST spare bits" line.long 0x18 "CFG0_MCU_LBIST_STAT," rbitfld.long 0x18 31. "MCU_LBIST_STAT_BIST_DONE,LBIST is done" "0,1" newline rbitfld.long 0x18 15. "MCU_LBIST_STAT_BIST_RUNNING,LBIST is running" "0,1" newline bitfld.long 0x18 8.--9. "MCU_LBIST_STAT_OUT_MUX_CTL,Selects source of LBIST output 00 - LBIST IP PID value 01 - LBIST CTRL ID value 1x - MISR value" "0: LBIST IP PID value 01,?,?,?" newline hexmask.long.byte 0x18 0.--7. 1. "MCU_LBIST_STAT_MISR_MUX_CTL,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR." rgroup.long 0xC01C++0x3 line.long 0x0 "CFG0_MCU_LBIST_MISR," hexmask.long 0x0 0.--31. 1. "MCU_LBIST_MISR_MISR_RESULT,32-bits of MISR value selected by misr_mux_ctl" rgroup.long 0xC280++0x3 line.long 0x0 "CFG0_MCU_LBIST_SIG," hexmask.long 0x0 0.--31. 1. "MCU_LBIST_SIG_MISR_SIG,MISR signature" rgroup.long 0xD008++0x7 line.long 0x0 "CFG0_LOCK3_KICK0," hexmask.long 0x0 0.--31. 1. "LOCK3_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK3_KICK1," hexmask.long 0x4 0.--31. 1. "LOCK3_KICK1,- KICK1 component" rgroup.long 0xD100++0x17 line.long 0x0 "CFG0_CLAIMREG_P3_R0_READONLY," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P3_R0_READONLY,Claim bits for Partition 3" line.long 0x4 "CFG0_CLAIMREG_P3_R1_READONLY," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P3_R1_READONLY,Claim bits for Partition 3" line.long 0x8 "CFG0_CLAIMREG_P3_R2_READONLY," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P3_R2_READONLY,Claim bits for Partition 3" line.long 0xC "CFG0_CLAIMREG_P3_R3_READONLY," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P3_R3_READONLY,Claim bits for Partition 3" line.long 0x10 "CFG0_CLAIMREG_P3_R4_READONLY," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P3_R4_READONLY,Claim bits for Partition 3" line.long 0x14 "CFG0_CLAIMREG_P3_R5_READONLY," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P3_R5_READONLY,Claim bits for Partition 3" rgroup.long 0xE000++0x1B line.long 0x0 "CFG0_MCU_LBIST_CTRL_PROXY," bitfld.long 0x0 31. "MCU_LBIST_CTRL_BIST_RESET_PROXY,Reset LBIST macro (active low)" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "MCU_LBIST_CTRL_BIST_RUN_PROXY,Starts LBIST if all bits are 1" newline hexmask.long.byte 0x0 12.--15. 1. "MCU_LBIST_CTRL_RUNBIST_MODE_PROXY,Runbist mode enable if all bits are 1" newline bitfld.long 0x0 8.--9. "MCU_LBIST_CTRL_DC_DEF_PROXY,Clock delay after scan_enable switching" "0,1,2,3" newline bitfld.long 0x0 7. "MCU_LBIST_CTRL_LOAD_DIV_PROXY,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "MCU_LBIST_CTRL_DIVIDE_RATIO_PROXY,LBIST clock divide ratio" line.long 0x4 "CFG0_MCU_LBIST_PATCOUNT_PROXY," hexmask.long.word 0x4 16.--29. 1. "MCU_LBIST_PATCOUNT_STATIC_PC_DEF_PROXY,Number of stuck-at patterns to run" newline hexmask.long.byte 0x4 8.--11. 1. "MCU_LBIST_PATCOUNT_SET_PC_DEF_PROXY,Number of set patterns to run" newline hexmask.long.byte 0x4 4.--7. 1. "MCU_LBIST_PATCOUNT_RESET_PC_DEF_PROXY,Number of reset patterns to run" newline hexmask.long.byte 0x4 0.--3. 1. "MCU_LBIST_PATCOUNT_SCAN_PC_DEF_PROXY,Number of chain test patterns to run" line.long 0x8 "CFG0_MCU_LBIST_SEED0_PROXY," hexmask.long 0x8 0.--31. 1. "MCU_LBIST_SEED0_PRPG_DEF_PROXY,Initial seed for PRPG (bits 31:0)" line.long 0xC "CFG0_MCU_LBIST_SEED1_PROXY," hexmask.long.tbyte 0xC 0.--20. 1. "MCU_LBIST_SEED1_PRPG_DEF_PROXY,Initial seed for PRPG (bits 52:32)" line.long 0x10 "CFG0_MCU_LBIST_SPARE0_PROXY," hexmask.long 0x10 2.--31. 1. "MCU_LBIST_SPARE0_SPARE0_PROXY,LBIST spare bits" newline bitfld.long 0x10 1. "MCU_LBIST_SPARE0_PBIST_SELFTEST_EN_PROXY,PBIST isolation control" "0,1" newline bitfld.long 0x10 0. "MCU_LBIST_SPARE0_LBIST_SELFTEST_EN_PROXY,LBIST isolation control" "0,1" line.long 0x14 "CFG0_MCU_LBIST_SPARE1_PROXY," hexmask.long 0x14 0.--31. 1. "MCU_LBIST_SPARE1_SPARE1_PROXY,LBIST spare bits" line.long 0x18 "CFG0_MCU_LBIST_STAT_PROXY," rbitfld.long 0x18 31. "MCU_LBIST_STAT_BIST_DONE_PROXY,LBIST is done" "0,1" newline rbitfld.long 0x18 15. "MCU_LBIST_STAT_BIST_RUNNING_PROXY,LBIST is running" "0,1" newline bitfld.long 0x18 8.--9. "MCU_LBIST_STAT_OUT_MUX_CTL_PROXY,Selects source of LBIST output 00 - LBIST IP PID value 01 - LBIST CTRL ID value 1x - MISR value" "0: LBIST IP PID value 01,?,?,?" newline hexmask.long.byte 0x18 0.--7. 1. "MCU_LBIST_STAT_MISR_MUX_CTL_PROXY,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR." rgroup.long 0xE01C++0x3 line.long 0x0 "CFG0_MCU_LBIST_MISR_PROXY," hexmask.long 0x0 0.--31. 1. "MCU_LBIST_MISR_MISR_RESULT_PROXY,32-bits of MISR value selected by misr_mux_ctl" rgroup.long 0xE280++0x3 line.long 0x0 "CFG0_MCU_LBIST_SIG_PROXY," hexmask.long 0x0 0.--31. 1. "MCU_LBIST_SIG_MISR_SIG_PROXY,MISR signature" rgroup.long 0xF008++0x7 line.long 0x0 "CFG0_LOCK3_KICK0_PROXY," hexmask.long 0x0 0.--31. 1. "LOCK3_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK3_KICK1_PROXY," hexmask.long 0x4 0.--31. 1. "LOCK3_KICK1_PROXY,- KICK1 component" rgroup.long 0xF100++0x17 line.long 0x0 "CFG0_CLAIMREG_P3_R0," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P3_R0,Claim bits for Partition 3" line.long 0x4 "CFG0_CLAIMREG_P3_R1," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P3_R1,Claim bits for Partition 3" line.long 0x8 "CFG0_CLAIMREG_P3_R2," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P3_R2,Claim bits for Partition 3" line.long 0xC "CFG0_CLAIMREG_P3_R3," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P3_R3,Claim bits for Partition 3" line.long 0x10 "CFG0_CLAIMREG_P3_R4," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P3_R4,Claim bits for Partition 3" line.long 0x14 "CFG0_CLAIMREG_P3_R5," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P3_R5,Claim bits for Partition 3" rgroup.long 0x10000++0x1F line.long 0x0 "CFG0_DV_REG0," hexmask.long 0x0 0.--31. 1. "DV_REG0_BIT,Defined by DV usage" line.long 0x4 "CFG0_DV_REG1," hexmask.long 0x4 0.--31. 1. "DV_REG1_BIT,Defined by DV usage" line.long 0x8 "CFG0_DV_REG2," hexmask.long 0x8 0.--31. 1. "DV_REG2_BIT,Defined by DV usage" line.long 0xC "CFG0_DV_REG3," hexmask.long 0xC 0.--31. 1. "DV_REG3_BIT,Defined by DV usage" line.long 0x10 "CFG0_DV_REG4," hexmask.long 0x10 0.--31. 1. "DV_REG4_BIT,Defined by DV usage" line.long 0x14 "CFG0_DV_REG5," hexmask.long 0x14 0.--31. 1. "DV_REG5_BIT,Defined by DV usage" line.long 0x18 "CFG0_DV_REG6," hexmask.long 0x18 0.--31. 1. "DV_REG6_BIT,Defined by DV usage" line.long 0x1C "CFG0_DV_REG7," hexmask.long 0x1C 0.--31. 1. "DV_REG7_BIT,Defined by DV usage" rgroup.long 0x10200++0xF line.long 0x0 "CFG0_DV_REG0_SET," hexmask.long 0x0 0.--31. 1. "DV_REG0_SET_BIT,Defined by DV usage" line.long 0x4 "CFG0_DV_REG1_SET," hexmask.long 0x4 0.--31. 1. "DV_REG1_SET_BIT,Defined by DV usage" line.long 0x8 "CFG0_DV_REG2_SET," hexmask.long 0x8 0.--31. 1. "DV_REG2_SET_BIT,Defined by DV usage" line.long 0xC "CFG0_DV_REG3_SET," hexmask.long 0xC 0.--31. 1. "DV_REG3_SET_BIT,Defined by DV usage" rgroup.long 0x10300++0xF line.long 0x0 "CFG0_DV_REG0_CLR," hexmask.long 0x0 0.--31. 1. "DV_REG0_CLR_BIT,Defined by DV usage" line.long 0x4 "CFG0_DV_REG1_CLR," hexmask.long 0x4 0.--31. 1. "DV_REG1_CLR_BIT,Defined by DV usage" line.long 0x8 "CFG0_DV_REG2_CLR," hexmask.long 0x8 0.--31. 1. "DV_REG2_CLR_BIT,Defined by DV usage" line.long 0xC "CFG0_DV_REG3_CLR," hexmask.long 0xC 0.--31. 1. "DV_REG3_CLR_BIT,Defined by DV usage" rgroup.long 0x11008++0x7 line.long 0x0 "CFG0_LOCK4_KICK0," hexmask.long 0x0 0.--31. 1. "LOCK4_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK4_KICK1," hexmask.long 0x4 0.--31. 1. "LOCK4_KICK1,- KICK1 component" rgroup.long 0x11100++0x1B line.long 0x0 "CFG0_CLAIMREG_P4_R0_READONLY," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P4_R0_READONLY,Claim bits for Partition 4" line.long 0x4 "CFG0_CLAIMREG_P4_R1_READONLY," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P4_R1_READONLY,Claim bits for Partition 4" line.long 0x8 "CFG0_CLAIMREG_P4_R2_READONLY," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P4_R2_READONLY,Claim bits for Partition 4" line.long 0xC "CFG0_CLAIMREG_P4_R3_READONLY," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P4_R3_READONLY,Claim bits for Partition 4" line.long 0x10 "CFG0_CLAIMREG_P4_R4_READONLY," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P4_R4_READONLY,Claim bits for Partition 4" line.long 0x14 "CFG0_CLAIMREG_P4_R5_READONLY," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P4_R5_READONLY,Claim bits for Partition 4" line.long 0x18 "CFG0_CLAIMREG_P4_R6_READONLY," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P4_R6_READONLY,Claim bits for Partition 4" rgroup.long 0x12000++0x1F line.long 0x0 "CFG0_DV_REG0_PROXY," hexmask.long 0x0 0.--31. 1. "DV_REG0_BIT_PROXY,Defined by DV usage" line.long 0x4 "CFG0_DV_REG1_PROXY," hexmask.long 0x4 0.--31. 1. "DV_REG1_BIT_PROXY,Defined by DV usage" line.long 0x8 "CFG0_DV_REG2_PROXY," hexmask.long 0x8 0.--31. 1. "DV_REG2_BIT_PROXY,Defined by DV usage" line.long 0xC "CFG0_DV_REG3_PROXY," hexmask.long 0xC 0.--31. 1. "DV_REG3_BIT_PROXY,Defined by DV usage" line.long 0x10 "CFG0_DV_REG4_PROXY," hexmask.long 0x10 0.--31. 1. "DV_REG4_BIT_PROXY,Defined by DV usage" line.long 0x14 "CFG0_DV_REG5_PROXY," hexmask.long 0x14 0.--31. 1. "DV_REG5_BIT_PROXY,Defined by DV usage" line.long 0x18 "CFG0_DV_REG6_PROXY," hexmask.long 0x18 0.--31. 1. "DV_REG6_BIT_PROXY,Defined by DV usage" line.long 0x1C "CFG0_DV_REG7_PROXY," hexmask.long 0x1C 0.--31. 1. "DV_REG7_BIT_PROXY,Defined by DV usage" rgroup.long 0x12200++0xF line.long 0x0 "CFG0_DV_REG0_SET_PROXY," hexmask.long 0x0 0.--31. 1. "DV_REG0_SET_BIT_PROXY,Defined by DV usage" line.long 0x4 "CFG0_DV_REG1_SET_PROXY," hexmask.long 0x4 0.--31. 1. "DV_REG1_SET_BIT_PROXY,Defined by DV usage" line.long 0x8 "CFG0_DV_REG2_SET_PROXY," hexmask.long 0x8 0.--31. 1. "DV_REG2_SET_BIT_PROXY,Defined by DV usage" line.long 0xC "CFG0_DV_REG3_SET_PROXY," hexmask.long 0xC 0.--31. 1. "DV_REG3_SET_BIT_PROXY,Defined by DV usage" rgroup.long 0x12300++0xF line.long 0x0 "CFG0_DV_REG0_CLR_PROXY," hexmask.long 0x0 0.--31. 1. "DV_REG0_CLR_BIT_PROXY,Defined by DV usage" line.long 0x4 "CFG0_DV_REG1_CLR_PROXY," hexmask.long 0x4 0.--31. 1. "DV_REG1_CLR_BIT_PROXY,Defined by DV usage" line.long 0x8 "CFG0_DV_REG2_CLR_PROXY," hexmask.long 0x8 0.--31. 1. "DV_REG2_CLR_BIT_PROXY,Defined by DV usage" line.long 0xC "CFG0_DV_REG3_CLR_PROXY," hexmask.long 0xC 0.--31. 1. "DV_REG3_CLR_BIT_PROXY,Defined by DV usage" rgroup.long 0x13008++0x7 line.long 0x0 "CFG0_LOCK4_KICK0_PROXY," hexmask.long 0x0 0.--31. 1. "LOCK4_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK4_KICK1_PROXY," hexmask.long 0x4 0.--31. 1. "LOCK4_KICK1_PROXY,- KICK1 component" rgroup.long 0x13100++0x1B line.long 0x0 "CFG0_CLAIMREG_P4_R0," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P4_R0,Claim bits for Partition 4" line.long 0x4 "CFG0_CLAIMREG_P4_R1," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P4_R1,Claim bits for Partition 4" line.long 0x8 "CFG0_CLAIMREG_P4_R2," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P4_R2,Claim bits for Partition 4" line.long 0xC "CFG0_CLAIMREG_P4_R3," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P4_R3,Claim bits for Partition 4" line.long 0x10 "CFG0_CLAIMREG_P4_R4," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P4_R4,Claim bits for Partition 4" line.long 0x14 "CFG0_CLAIMREG_P4_R5," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P4_R5,Claim bits for Partition 4" line.long 0x18 "CFG0_CLAIMREG_P4_R6," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P4_R6,Claim bits for Partition 4" tree.end tree "MCU_DCC0 (MCU_DCC0)" base ad:0x40100000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register. User privilege and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User privilege and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User privilege and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.." rgroup.long 0x4++0x3 line.long 0x0 "CFG_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained. User privilege and debug mode (read): 0x0 Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User privilege and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User privilege and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect." rgroup.long 0x8++0xF line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User privilege and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.." line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User privilege and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.." line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User privilege and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.." line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag" bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag" rgroup.long 0x18++0xB line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User privilege and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect." line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User privilege and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect." line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User privilege and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect." rgroup.long 0x24++0xB line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature. User privilege and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC." line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User privilege and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0." line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.." rgroup.long 0x30++0x3 line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User privilege and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User privilege and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User privilege and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User privilege and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User privilege and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User privilege and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty" rgroup.long 0x34++0x3 line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree "MCU_DCC1 (MCU_DCC1)" base ad:0x40110000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register. User privilege and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User privilege and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User privilege and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.." rgroup.long 0x4++0x3 line.long 0x0 "CFG_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained. User privilege and debug mode (read): 0x0 Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User privilege and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User privilege and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect." rgroup.long 0x8++0xF line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User privilege and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.." line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User privilege and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.." line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User privilege and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.." line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag" bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag" rgroup.long 0x18++0xB line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User privilege and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect." line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User privilege and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect." line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User privilege and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect." rgroup.long 0x24++0xB line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature. User privilege and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC." line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User privilege and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0." line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.." rgroup.long 0x30++0x3 line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User privilege and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User privilege and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User privilege and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User privilege and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User privilege and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User privilege and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty" rgroup.long 0x34++0x3 line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree "MCU_DCC2 (MCU_DCC2)" base ad:0x40120000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register. User privilege and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User privilege and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User privilege and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.." rgroup.long 0x4++0x3 line.long 0x0 "CFG_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained. User privilege and debug mode (read): 0x0 Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User privilege and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User privilege and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect." rgroup.long 0x8++0xF line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User privilege and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.." line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User privilege and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.." line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User privilege and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.." line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag" bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag" rgroup.long 0x18++0xB line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User privilege and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect." line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User privilege and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect." line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User privilege and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect." rgroup.long 0x24++0xB line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature. User privilege and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC." line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User privilege and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0." line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.." rgroup.long 0x30++0x3 line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User privilege and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User privilege and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User privilege and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User privilege and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User privilege and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User privilege and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty" rgroup.long 0x34++0x3 line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree "MCU_ESM0_CFG (MCU_ESM0_CFG)" base ad:0x40800000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "CFG_INFO,The Info Register gives the configuration Inforrmation of this ESM." bitfld.long 0x4 31. "LAST_RESET,Indicates the Source of the last Reset" "0,1" hexmask.long.byte 0x4 8.--15. 1. "PULSE_GROUPS,Number of Pulse Error Groups" hexmask.long.byte 0x4 0.--7. 1. "GROUPS,Total number of Error Groups" rgroup.long 0x8++0x3 line.long 0x0 "CFG_EN,The Global Enable Register has the master interrupt mask" hexmask.long.byte 0x0 0.--3. 1. "KEY,Global Enable" rgroup.long 0xC++0x3 line.long 0x0 "CFG_SFT_RST,The Global Soft Reset Register controls the global clear for raw status and enables" hexmask.long.byte 0x0 0.--3. 1. "KEY,Global Soft Reset" rgroup.long 0x10++0xF line.long 0x0 "CFG_ERR_RAW,Raw Status/Set Register for Configuration Errors" hexmask.long.byte 0x0 0.--3. 1. "STS,This is the raw status for config errors" line.long 0x4 "CFG_ERR_STS,Config Error Enable and Clear Register" hexmask.long.byte 0x4 0.--3. 1. "MSK,This is the masked status/clear for config errors" line.long 0x8 "CFG_ERR_EN_SET,Config Error Enable Set Register" hexmask.long.byte 0x8 0.--3. 1. "MSK,This is the mask enable set for config errors" line.long 0xC "CFG_ERR_EN_CLR,Config Error Interrupt Enabled Clear register" hexmask.long.byte 0xC 0.--3. 1. "MSK,This is the mask enable clear for config errors" rgroup.long 0x20++0xF line.long 0x0 "CFG_LOW_PRI,Shows which is the highest priority outstanding low priority interrupt" hexmask.long.word 0x0 16.--31. 1. "PLS,This is the highest priority outstanding low priority pulse interrupt" hexmask.long.word 0x0 0.--15. 1. "LVL,This is the highest priority outstanding low priority level interrupt" line.long 0x4 "CFG_HI_PRI,Shows which is the highest priority outstanding high priority interrupt" hexmask.long.word 0x4 16.--31. 1. "PLS,This is the highest priority outstanding high priority pulse interrupt" hexmask.long.word 0x4 0.--15. 1. "LVL,This is the highest priority outstanding high priority level interrupt" line.long 0x8 "CFG_LOW,Shows which groups have oustanding low priority interrupts" hexmask.long 0x8 0.--31. 1. "STS,This is the raw status for config errors" line.long 0xC "CFG_HI,Shows which groups have oustanding high priority interrupts" hexmask.long 0xC 0.--31. 1. "STS,This is the raw status for config errors" rgroup.long 0x30++0x3 line.long 0x0 "CFG_EOI,End of Interrupt Register" hexmask.long.word 0x0 0.--10. 1. "KEY,This is the interrupt being serviced" rgroup.long 0x40++0x3 line.long 0x0 "CFG_PIN_CTRL,This register controls the error_pin_n output" hexmask.long.byte 0x0 0.--3. 1. "KEY,Pin Control Key" rgroup.long 0x44++0x7 line.long 0x0 "CFG_PIN_STS,This register reflects the status of the error_pin_n output" bitfld.long 0x0 0. "VAL,Value of the error_pin_n" "0,1" line.long 0x4 "CFG_PIN_CNTR,This register shows the current value of the error pin counter" hexmask.long.tbyte 0x4 0.--23. 1. "COUNT,Current Counter Value" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error Counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value" tree.end tree "MCU_I2C0_CFG (MCU_I2C0_CFG)" base ad:0x40B00000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "CFG_I2C_REVNB_HI,Revision Number register (High)" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" rgroup.long 0x10++0x3 line.long 0x0 "CFG_I2C_SYSC,System Configuration register" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" bitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" newline bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CFG_I2C_EOI,End Of Interrupt number specification" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" rgroup.long 0x24++0x2B line.long 0x0 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x0 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x0 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x0 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x0 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x0 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x0 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x0 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x0 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x4 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ enabled status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ enabled status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x8 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x8 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x8 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x8 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x8 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x8 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x8 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x8 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x8 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x8 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x8 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x8 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x8 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0xC "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0xC 11. "ROVR,Receive overrun enable clear" "0,1" newline bitfld.long 0xC 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x10 "CFG_I2C_WE,I2C wakeup enable vector (legacy)." bitfld.long 0x10 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x10 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x10 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x10 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x10 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x10 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x10 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x10 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x10 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x10 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x10 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x14 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.long 0x14 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x18 "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.long 0x18 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x1C "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.long 0x1C 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x20 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.long 0x20 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x24 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.long 0x24 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x24 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x24 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x24 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x24 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x24 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x24 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x24 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x24 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x24 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x24 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x24 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x28 "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" rgroup.long 0x84++0x7 line.long 0x0 "CFG_I2C_IE,I2C interrupt enable vector (legacy)." bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x4 "CFG_I2C_STAT,I2C interrupt status vector (legacy)." bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "CFG_I2C_SYSS,System Status register" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" rgroup.long 0x94++0xB line.long 0x0 "CFG_I2C_BUF,Buffer Configuration register" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "CFG_I2C_CNT,Data counter register" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "CFG_I2C_DATA,Data access register" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" rgroup.long 0xA4++0x1B line.long 0x0 "CFG_I2C_CON,I2C configuration register." bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" newline bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "CFG_I2C_OA,Own address register" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "CFG_I2C_SA,Slave address register" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "CFG_I2C_PSC,I2C Clock Prescaler Register" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 0xFF: Divide by 256" line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register." hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register." hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register." bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" newline bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "CFG_I2C_BUFSTAT,I2C Buffer Status Register." bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" rgroup.long 0xC4++0xB line.long 0x0 "CFG_I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "CFG_I2C_OA2,I2C Own Address 2" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "CFG_I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "CFG_I2C_ACTOA,I2C Active Own Address Register." bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" rgroup.long 0xD4++0x3 line.long 0x0 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree "MCU_I2C1_CFG (MCU_I2C1_CFG)" base ad:0x40B10000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "CFG_I2C_REVNB_HI,Revision Number register (High)" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" rgroup.long 0x10++0x3 line.long 0x0 "CFG_I2C_SYSC,System Configuration register" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" bitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" newline bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CFG_I2C_EOI,End Of Interrupt number specification" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" rgroup.long 0x24++0x2B line.long 0x0 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x0 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x0 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x0 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x0 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x0 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x0 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x0 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x0 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x4 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ enabled status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ enabled status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x8 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x8 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x8 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x8 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x8 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x8 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x8 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x8 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x8 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x8 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x8 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x8 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x8 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0xC "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0xC 11. "ROVR,Receive overrun enable clear" "0,1" newline bitfld.long 0xC 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x10 "CFG_I2C_WE,I2C wakeup enable vector (legacy)." bitfld.long 0x10 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x10 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x10 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x10 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x10 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x10 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x10 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x10 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x10 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x10 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x10 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x14 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.long 0x14 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x18 "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.long 0x18 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x1C "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.long 0x1C 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x20 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.long 0x20 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x24 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.long 0x24 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x24 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x24 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x24 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x24 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x24 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x24 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x24 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x24 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x24 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x24 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x24 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x28 "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" rgroup.long 0x84++0x7 line.long 0x0 "CFG_I2C_IE,I2C interrupt enable vector (legacy)." bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x4 "CFG_I2C_STAT,I2C interrupt status vector (legacy)." bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "CFG_I2C_SYSS,System Status register" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" rgroup.long 0x94++0xB line.long 0x0 "CFG_I2C_BUF,Buffer Configuration register" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "CFG_I2C_CNT,Data counter register" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "CFG_I2C_DATA,Data access register" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" rgroup.long 0xA4++0x1B line.long 0x0 "CFG_I2C_CON,I2C configuration register." bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" newline bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "CFG_I2C_OA,Own address register" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "CFG_I2C_SA,Slave address register" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "CFG_I2C_PSC,I2C Clock Prescaler Register" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 0xFF: Divide by 256" line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register." hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register." hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register." bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" newline bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "CFG_I2C_BUFSTAT,I2C Buffer Status Register." bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" rgroup.long 0xC4++0xB line.long 0x0 "CFG_I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "CFG_I2C_OA2,I2C Own Address 2" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "CFG_I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "CFG_I2C_ACTOA,I2C Active Own Address Register." bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" rgroup.long 0xD4++0x3 line.long 0x0 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree "MCU_j7am_mcu_ecc_aggr0_REGS (MCU_j7am_mcu_ecc_aggr0_REGS)" base ad:0x47200000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xF line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_ERR_SCR_J7AM_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_fw_cbass_mcu_0_j7am_mcu_fw_cbass_err_scr_j7am_mcu_fw_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 30. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_fw_cbass_mcu_0_j7am_mcu_fw_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 29. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_CBASS_DEFAULT_ERR_J7AM_MCU_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7AM_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_IJ7AM_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7AM_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "IJ7VCL_IEXPORT_VBUSM_64B_MST_MCU_0_MST_MTOG_EDC_CTRL_PEND,Interrupt Pending Status for Ij7vcl_Iexport_vbusm_64b_mst_mcu_0_mst_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 24. "J7AM_MCU_CTRL_MMR_MCU_0_J7AM_MCU_CTRL_MMR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_ctrl_mmr_mcu_0_j7am_mcu_ctrl_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 23. "J7VC_MCU_SEC_MMR_MCU_0_J7VC_MCU_SEC_MMR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7vc_mcu_sec_mmr_mcu_0_j7vc_mcu_sec_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 22. "J7VC_MCU_PLL_MMR_MCU_0_J7VC_MCU_PLL_MMR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7vc_mcu_pll_mmr_mcu_0_j7vc_mcu_pll_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 21. "I7_MCU_VBUSM_FSS1_SAFETY_GASKET_WR_RAMECC_PEND,Interrupt Pending Status for I7_mcu_vbusm_fss1_safety_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "I7_MCU_VBUSM_FSS1_SAFETY_GASKET_RD_RAMECC_PEND,Interrupt Pending Status for I7_mcu_vbusm_fss1_safety_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "I7_MCU_VBUSM_FSS1_SAFETY_GASKET_EDC_CTRL_PEND,Interrupt Pending Status for I7_mcu_vbusm_fss1_safety_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 18. "I7_MCU_VBUSM_FSS0_SAFETY_GASKET_WR_RAMECC_PEND,Interrupt Pending Status for I7_mcu_vbusm_fss0_safety_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "I7_MCU_VBUSM_FSS0_SAFETY_GASKET_RD_RAMECC_PEND,Interrupt Pending Status for I7_mcu_vbusm_fss0_safety_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "I7_MCU_VBUSM_FSS0_SAFETY_GASKET_EDC_CTRL_PEND,Interrupt Pending Status for I7_mcu_vbusm_fss0_safety_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 15. "IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_PEND,Interrupt Pending Status for Ivdc_data_safeg_vbusm_64b_ref_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 14. "IVDC_DATA_SAFEG_VBUSM_64B_REF_RD_RAMECC_PEND,Interrupt Pending Status for Ivdc_data_safeg_vbusm_64b_ref_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "IVDC_DATA_SAFEG_VBUSM_64B_REF_WR_RAMECC_PEND,Interrupt Pending Status for Ivdc_data_safeg_vbusm_64b_ref_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_PEND,Interrupt Pending Status for Imcu_cor_infra_vbusp_32b_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x4 11. "IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_PEND,Interrupt Pending Status for Imcu_cor_infra_vbusp_32b_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x4 10. "IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_PEND,Interrupt Pending Status for Imcu_cor_infra_vbusp_32b_infra_safeg_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 9. "IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_PEND,Interrupt Pending Status for Imcu_cor_infra_vbusp_32b_infra_safeg_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 8. "IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_PEND,Interrupt Pending Status for Imcu_cor_infra_vbusp_32b_infra_safeg_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 7. "IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_PEND,Interrupt Pending Status for Imcu_cor_data_vbusm_64b_src_vbuss_pend" "0,1" newline bitfld.long 0x4 6. "ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_PEND,Interrupt Pending Status for Icor_mcu_data_vbusm_64b_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 5. "ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_PEND,Interrupt Pending Status for Icor_mcu_data_vbusm_64b_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 4. "IMCU_COR_FW_VBUSP_32B_SRC_P2M_BUSECC_PEND,Interrupt Pending Status for Imcu_cor_fw_vbusp_32b_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x4 3. "IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_PEND,Interrupt Pending Status for Imcu_cor_fw_vbusp_32b_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x4 2. "IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_PEND,Interrupt Pending Status for Imcu_cor_fw_vbusp_32b_soc_fw_safeg_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 1. "IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_PEND,Interrupt Pending Status for Imcu_cor_fw_vbusp_32b_soc_fw_safeg_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_PEND,Interrupt Pending Status for Imcu_cor_fw_vbusp_32b_soc_fw_safeg_wr_ramecc_pend" "0,1" line.long 0x8 "REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 31. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_SCRP_32_PCLK6_scr_j7am_mcu_cbass_SCRP_32_PCLK6_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 30. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_SCRP_32_PCLK6_scr_j7am_mcu_cbass_SCRP_32_PCLK6_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 29. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_SCRP_32_PCLK6_scr_j7am_mcu_cbass_SCRP_32_PCLK6_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 28. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_SCRP_32_PCLK6_scr_j7am_mcu_cbass_SCRP_32_PCLK6_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 27. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_SCRP_32_PCLK6_scr_j7am_mcu_cbass_SCRP_32_PCLK6_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 26. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_MAIN_INFRA_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_MCU_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 25. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 24. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7AM_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 23. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7AM_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_1_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_1_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 21. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 19. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 18. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 17. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 16. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7AM_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7AM_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 15. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 14. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 13. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 12. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 11. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_ISA3SS_AM62_MCU_0_PKTDMA_MEM_M2M_BRIDGE_J7AM_MCU_CBASS_ISA3SS_AM62_MCU_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_fw_cbass_mcu_0_j7am_mcu_fw_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_pend" "0,1" line.long 0xC "REGS_sec_status_reg2,Interrupt Status Register 2" bitfld.long 0xC 24. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0xC 23. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 22. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 21. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_3_pend" "0,1" newline bitfld.long 0xC 20. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_2_pend" "0,1" newline bitfld.long 0xC 19. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_1_pend" "0,1" newline bitfld.long 0xC 18. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_0_pend" "0,1" newline bitfld.long 0xC 17. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_2_pend" "0,1" newline bitfld.long 0xC 16. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_1_pend" "0,1" newline bitfld.long 0xC 15. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_0_pend" "0,1" newline bitfld.long 0xC 14. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_12_clk_edc_ctrl_cbass_int_mcu_sysclk0_12_busecc_pend" "0,1" newline bitfld.long 0xC 13. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_ERR_SCR_J7AM_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_err_scr_j7am_mcu_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 12. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0xC 11. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_CBASS_DEFAULT_ERR_J7AM_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_cbass_default_err_j7am_mcu_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 10. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_CBASS_INT_DMSC_SCR_J7AM_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_cbass_int_dmsc_scr_j7am_mcu_cbass_cbass_int_dmsc_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 9. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0xC 8. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_CBASS_DEFAULT_MMRS_J7AM_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_cbass_default_mmrs_j7am_mcu_cbass_cbass_default_mmrs_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 7. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK12_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_SCRP_32_PCLK12_scr_j7am_mcu_cbass_SCRP_32_PCLK12_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 6. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 5. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 4. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 3. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 2. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_SCRP_32b_PCLK3_scr_j7am_mcu_cbass_SCRP_32b_PCLK3_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0xC 1. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_SCRP_32b_PCLK3_scr_j7am_mcu_cbass_SCRP_32b_PCLK3_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0xC 0. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_SCRP_32b_PCLK3_scr_j7am_mcu_cbass_SCRP_32b_PCLK3_scr_edc_ctrl_busecc_0_pend" "0,1" rgroup.long 0x80++0xB line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_ERR_SCR_J7AM_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_fw_cbass_mcu_0_j7am_mcu_fw_cbass_err_scr_j7am_mcu_fw_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 30. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_fw_cbass_mcu_0_j7am_mcu_fw_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 29. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_CBASS_DEFAULT_ERR_J7AM_MCU_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7AM_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_IJ7AM_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7AM_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "IJ7VCL_IEXPORT_VBUSM_64B_MST_MCU_0_MST_MTOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7vcl_Iexport_vbusm_64b_mst_mcu_0_mst_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 24. "J7AM_MCU_CTRL_MMR_MCU_0_J7AM_MCU_CTRL_MMR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_ctrl_mmr_mcu_0_j7am_mcu_ctrl_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 23. "J7VC_MCU_SEC_MMR_MCU_0_J7VC_MCU_SEC_MMR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7vc_mcu_sec_mmr_mcu_0_j7vc_mcu_sec_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 22. "J7VC_MCU_PLL_MMR_MCU_0_J7VC_MCU_PLL_MMR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7vc_mcu_pll_mmr_mcu_0_j7vc_mcu_pll_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 21. "I7_MCU_VBUSM_FSS1_SAFETY_GASKET_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for I7_mcu_vbusm_fss1_safety_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "I7_MCU_VBUSM_FSS1_SAFETY_GASKET_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for I7_mcu_vbusm_fss1_safety_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 19. "I7_MCU_VBUSM_FSS1_SAFETY_GASKET_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for I7_mcu_vbusm_fss1_safety_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 18. "I7_MCU_VBUSM_FSS0_SAFETY_GASKET_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for I7_mcu_vbusm_fss0_safety_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "I7_MCU_VBUSM_FSS0_SAFETY_GASKET_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for I7_mcu_vbusm_fss0_safety_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 16. "I7_MCU_VBUSM_FSS0_SAFETY_GASKET_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for I7_mcu_vbusm_fss0_safety_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 15. "IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ivdc_data_safeg_vbusm_64b_ref_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 14. "IVDC_DATA_SAFEG_VBUSM_64B_REF_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ivdc_data_safeg_vbusm_64b_ref_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "IVDC_DATA_SAFEG_VBUSM_64B_REF_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ivdc_data_safeg_vbusm_64b_ref_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 12. "IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_infra_vbusp_32b_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_infra_vbusp_32b_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 10. "IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_infra_vbusp_32b_infra_safeg_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 9. "IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_infra_vbusp_32b_infra_safeg_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_infra_vbusp_32b_infra_safeg_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_data_vbusm_64b_src_vbuss_pend" "0,1" newline bitfld.long 0x0 6. "ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Icor_mcu_data_vbusm_64b_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 5. "ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Icor_mcu_data_vbusm_64b_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 4. "IMCU_COR_FW_VBUSP_32B_SRC_P2M_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_fw_vbusp_32b_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_fw_vbusp_32b_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 2. "IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_fw_vbusp_32b_soc_fw_safeg_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 1. "IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_fw_vbusp_32b_soc_fw_safeg_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_fw_vbusp_32b_soc_fw_safeg_wr_ramecc_pend" "0,1" line.long 0x4 "REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 31. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 30. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 29. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 28. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 27. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 26. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_MAIN_INFRA_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_MCU_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 25. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 24. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7AM_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 23. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7AM_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_1_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_1_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 21. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 19. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 18. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 17. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 16. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7AM_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7AM_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 15. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 14. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 13. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 12. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 11. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_ISA3SS_AM62_MCU_0_PKTDMA_MEM_M2M_BRIDGE_J7AM_MCU_CBASS_ISA3SS_AM62_MCU_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_fw_cbass_mcu_0_j7am_mcu_fw_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_pend" "0,1" line.long 0x8 "REGS_sec_enable_set_reg2,Interrupt Enable Set Register 2" bitfld.long 0x8 24. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x8 23. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 22. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 21. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_3_pend" "0,1" newline bitfld.long 0x8 20. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_2_pend" "0,1" newline bitfld.long 0x8 19. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_1_pend" "0,1" newline bitfld.long 0x8 18. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_0_pend" "0,1" newline bitfld.long 0x8 17. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_12_clk_edc_ctrl_cbass_int_mcu_sysclk0_12_busecc_pend" "0,1" newline bitfld.long 0x8 13. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_ERR_SCR_J7AM_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_err_scr_j7am_mcu_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 12. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_CBASS_DEFAULT_ERR_J7AM_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_cbass_default_err_j7am_mcu_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 10. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_CBASS_INT_DMSC_SCR_J7AM_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 9. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 8. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_CBASS_DEFAULT_MMRS_J7AM_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 7. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK12_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 6. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 5. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 4. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 3. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 2. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 1. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 0. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0xB line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_ERR_SCR_J7AM_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_fw_cbass_mcu_0_j7am_mcu_fw_cbass_err_scr_j7am_mcu_fw_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 30. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_fw_cbass_mcu_0_j7am_mcu_fw_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 29. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_CBASS_DEFAULT_ERR_J7AM_MCU_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7AM_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_IJ7AM_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7AM_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "IJ7VCL_IEXPORT_VBUSM_64B_MST_MCU_0_MST_MTOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7vcl_Iexport_vbusm_64b_mst_mcu_0_mst_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 24. "J7AM_MCU_CTRL_MMR_MCU_0_J7AM_MCU_CTRL_MMR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_ctrl_mmr_mcu_0_j7am_mcu_ctrl_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 23. "J7VC_MCU_SEC_MMR_MCU_0_J7VC_MCU_SEC_MMR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7vc_mcu_sec_mmr_mcu_0_j7vc_mcu_sec_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 22. "J7VC_MCU_PLL_MMR_MCU_0_J7VC_MCU_PLL_MMR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7vc_mcu_pll_mmr_mcu_0_j7vc_mcu_pll_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 21. "I7_MCU_VBUSM_FSS1_SAFETY_GASKET_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for I7_mcu_vbusm_fss1_safety_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "I7_MCU_VBUSM_FSS1_SAFETY_GASKET_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for I7_mcu_vbusm_fss1_safety_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 19. "I7_MCU_VBUSM_FSS1_SAFETY_GASKET_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for I7_mcu_vbusm_fss1_safety_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 18. "I7_MCU_VBUSM_FSS0_SAFETY_GASKET_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for I7_mcu_vbusm_fss0_safety_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "I7_MCU_VBUSM_FSS0_SAFETY_GASKET_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for I7_mcu_vbusm_fss0_safety_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 16. "I7_MCU_VBUSM_FSS0_SAFETY_GASKET_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for I7_mcu_vbusm_fss0_safety_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 15. "IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ivdc_data_safeg_vbusm_64b_ref_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 14. "IVDC_DATA_SAFEG_VBUSM_64B_REF_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ivdc_data_safeg_vbusm_64b_ref_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "IVDC_DATA_SAFEG_VBUSM_64B_REF_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ivdc_data_safeg_vbusm_64b_ref_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 12. "IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_infra_vbusp_32b_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_infra_vbusp_32b_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 10. "IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_infra_vbusp_32b_infra_safeg_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 9. "IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_infra_vbusp_32b_infra_safeg_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_infra_vbusp_32b_infra_safeg_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_data_vbusm_64b_src_vbuss_pend" "0,1" newline bitfld.long 0x0 6. "ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Icor_mcu_data_vbusm_64b_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 5. "ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Icor_mcu_data_vbusm_64b_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 4. "IMCU_COR_FW_VBUSP_32B_SRC_P2M_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_fw_vbusp_32b_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_fw_vbusp_32b_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 2. "IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_fw_vbusp_32b_soc_fw_safeg_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 1. "IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_fw_vbusp_32b_soc_fw_safeg_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_fw_vbusp_32b_soc_fw_safeg_wr_ramecc_pend" "0,1" line.long 0x4 "REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 31. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 30. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 29. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 28. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 27. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 26. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_MAIN_INFRA_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_MCU_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 25. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 24. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7AM_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 23. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7AM_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_1_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_1_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 21. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 19. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 18. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 17. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 16. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7AM_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7AM_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 15. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 14. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 13. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 12. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 11. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_ISA3SS_AM62_MCU_0_PKTDMA_MEM_M2M_BRIDGE_J7AM_MCU_CBASS_ISA3SS_AM62_MCU_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_fw_cbass_mcu_0_j7am_mcu_fw_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_pend" "0,1" line.long 0x8 "REGS_sec_enable_clr_reg2,Interrupt Enable Clear Register 2" bitfld.long 0x8 24. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x8 23. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 22. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 21. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_3_pend" "0,1" newline bitfld.long 0x8 20. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_2_pend" "0,1" newline bitfld.long 0x8 19. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_1_pend" "0,1" newline bitfld.long 0x8 18. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_0_pend" "0,1" newline bitfld.long 0x8 17. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_12_clk_edc_ctrl_cbass_int_mcu_sysclk0_12_busecc_pend" "0,1" newline bitfld.long 0x8 13. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_ERR_SCR_J7AM_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_err_scr_j7am_mcu_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 12. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_CBASS_DEFAULT_ERR_J7AM_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 10. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_CBASS_INT_DMSC_SCR_J7AM_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 9. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 8. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_CBASS_DEFAULT_MMRS_J7AM_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 7. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK12_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 6. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 5. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 4. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 3. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 2. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 1. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 0. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0xF line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_ERR_SCR_J7AM_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_fw_cbass_mcu_0_j7am_mcu_fw_cbass_err_scr_j7am_mcu_fw_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 30. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_fw_cbass_mcu_0_j7am_mcu_fw_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 29. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_CBASS_DEFAULT_ERR_J7AM_MCU_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7AM_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_IJ7AM_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7AM_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "IJ7VCL_IEXPORT_VBUSM_64B_MST_MCU_0_MST_MTOG_EDC_CTRL_PEND,Interrupt Pending Status for Ij7vcl_Iexport_vbusm_64b_mst_mcu_0_mst_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 24. "J7AM_MCU_CTRL_MMR_MCU_0_J7AM_MCU_CTRL_MMR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_ctrl_mmr_mcu_0_j7am_mcu_ctrl_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 23. "J7VC_MCU_SEC_MMR_MCU_0_J7VC_MCU_SEC_MMR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7vc_mcu_sec_mmr_mcu_0_j7vc_mcu_sec_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 22. "J7VC_MCU_PLL_MMR_MCU_0_J7VC_MCU_PLL_MMR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7vc_mcu_pll_mmr_mcu_0_j7vc_mcu_pll_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 21. "I7_MCU_VBUSM_FSS1_SAFETY_GASKET_WR_RAMECC_PEND,Interrupt Pending Status for I7_mcu_vbusm_fss1_safety_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "I7_MCU_VBUSM_FSS1_SAFETY_GASKET_RD_RAMECC_PEND,Interrupt Pending Status for I7_mcu_vbusm_fss1_safety_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "I7_MCU_VBUSM_FSS1_SAFETY_GASKET_EDC_CTRL_PEND,Interrupt Pending Status for I7_mcu_vbusm_fss1_safety_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 18. "I7_MCU_VBUSM_FSS0_SAFETY_GASKET_WR_RAMECC_PEND,Interrupt Pending Status for I7_mcu_vbusm_fss0_safety_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "I7_MCU_VBUSM_FSS0_SAFETY_GASKET_RD_RAMECC_PEND,Interrupt Pending Status for I7_mcu_vbusm_fss0_safety_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "I7_MCU_VBUSM_FSS0_SAFETY_GASKET_EDC_CTRL_PEND,Interrupt Pending Status for I7_mcu_vbusm_fss0_safety_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 15. "IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_PEND,Interrupt Pending Status for Ivdc_data_safeg_vbusm_64b_ref_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 14. "IVDC_DATA_SAFEG_VBUSM_64B_REF_RD_RAMECC_PEND,Interrupt Pending Status for Ivdc_data_safeg_vbusm_64b_ref_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "IVDC_DATA_SAFEG_VBUSM_64B_REF_WR_RAMECC_PEND,Interrupt Pending Status for Ivdc_data_safeg_vbusm_64b_ref_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_PEND,Interrupt Pending Status for Imcu_cor_infra_vbusp_32b_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x4 11. "IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_PEND,Interrupt Pending Status for Imcu_cor_infra_vbusp_32b_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x4 10. "IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_PEND,Interrupt Pending Status for Imcu_cor_infra_vbusp_32b_infra_safeg_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 9. "IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_PEND,Interrupt Pending Status for Imcu_cor_infra_vbusp_32b_infra_safeg_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 8. "IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_PEND,Interrupt Pending Status for Imcu_cor_infra_vbusp_32b_infra_safeg_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 7. "IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_PEND,Interrupt Pending Status for Imcu_cor_data_vbusm_64b_src_vbuss_pend" "0,1" newline bitfld.long 0x4 6. "ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_PEND,Interrupt Pending Status for Icor_mcu_data_vbusm_64b_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 5. "ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_PEND,Interrupt Pending Status for Icor_mcu_data_vbusm_64b_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 4. "IMCU_COR_FW_VBUSP_32B_SRC_P2M_BUSECC_PEND,Interrupt Pending Status for Imcu_cor_fw_vbusp_32b_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x4 3. "IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_PEND,Interrupt Pending Status for Imcu_cor_fw_vbusp_32b_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x4 2. "IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_PEND,Interrupt Pending Status for Imcu_cor_fw_vbusp_32b_soc_fw_safeg_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 1. "IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_PEND,Interrupt Pending Status for Imcu_cor_fw_vbusp_32b_soc_fw_safeg_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_PEND,Interrupt Pending Status for Imcu_cor_fw_vbusp_32b_soc_fw_safeg_wr_ramecc_pend" "0,1" line.long 0x8 "REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 31. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_SCRP_32_PCLK6_scr_j7am_mcu_cbass_SCRP_32_PCLK6_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 30. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_SCRP_32_PCLK6_scr_j7am_mcu_cbass_SCRP_32_PCLK6_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 29. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_SCRP_32_PCLK6_scr_j7am_mcu_cbass_SCRP_32_PCLK6_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 28. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_SCRP_32_PCLK6_scr_j7am_mcu_cbass_SCRP_32_PCLK6_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 27. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_SCRP_32_PCLK6_scr_j7am_mcu_cbass_SCRP_32_PCLK6_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 26. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_MAIN_INFRA_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_MCU_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 25. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 24. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7AM_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 23. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7AM_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_1_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_1_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 21. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 19. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 18. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 17. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 16. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7AM_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7AM_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 15. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 14. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 13. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 12. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 11. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_ISA3SS_AM62_MCU_0_PKTDMA_MEM_M2M_BRIDGE_J7AM_MCU_CBASS_ISA3SS_AM62_MCU_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_fw_cbass_mcu_0_j7am_mcu_fw_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_pend" "0,1" line.long 0xC "REGS_ded_status_reg2,Interrupt Status Register 2" bitfld.long 0xC 24. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0xC 23. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 22. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 21. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_3_pend" "0,1" newline bitfld.long 0xC 20. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_2_pend" "0,1" newline bitfld.long 0xC 19. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_1_pend" "0,1" newline bitfld.long 0xC 18. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_0_pend" "0,1" newline bitfld.long 0xC 17. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_2_pend" "0,1" newline bitfld.long 0xC 16. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_1_pend" "0,1" newline bitfld.long 0xC 15. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_0_pend" "0,1" newline bitfld.long 0xC 14. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_12_clk_edc_ctrl_cbass_int_mcu_sysclk0_12_busecc_pend" "0,1" newline bitfld.long 0xC 13. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_ERR_SCR_J7AM_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_err_scr_j7am_mcu_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 12. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0xC 11. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_CBASS_DEFAULT_ERR_J7AM_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_cbass_default_err_j7am_mcu_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 10. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_CBASS_INT_DMSC_SCR_J7AM_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_cbass_int_dmsc_scr_j7am_mcu_cbass_cbass_int_dmsc_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 9. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0xC 8. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_CBASS_DEFAULT_MMRS_J7AM_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_cbass_default_mmrs_j7am_mcu_cbass_cbass_default_mmrs_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 7. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK12_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_SCRP_32_PCLK12_scr_j7am_mcu_cbass_SCRP_32_PCLK12_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 6. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 5. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 4. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 3. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 2. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_SCRP_32b_PCLK3_scr_j7am_mcu_cbass_SCRP_32b_PCLK3_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0xC 1. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_SCRP_32b_PCLK3_scr_j7am_mcu_cbass_SCRP_32b_PCLK3_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0xC 0. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_SCRP_32b_PCLK3_scr_j7am_mcu_cbass_SCRP_32b_PCLK3_scr_edc_ctrl_busecc_0_pend" "0,1" rgroup.long 0x180++0xB line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_ERR_SCR_J7AM_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_fw_cbass_mcu_0_j7am_mcu_fw_cbass_err_scr_j7am_mcu_fw_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 30. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_fw_cbass_mcu_0_j7am_mcu_fw_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 29. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_CBASS_DEFAULT_ERR_J7AM_MCU_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7AM_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_IJ7AM_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7AM_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "IJ7VCL_IEXPORT_VBUSM_64B_MST_MCU_0_MST_MTOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ij7vcl_Iexport_vbusm_64b_mst_mcu_0_mst_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 24. "J7AM_MCU_CTRL_MMR_MCU_0_J7AM_MCU_CTRL_MMR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_ctrl_mmr_mcu_0_j7am_mcu_ctrl_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 23. "J7VC_MCU_SEC_MMR_MCU_0_J7VC_MCU_SEC_MMR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7vc_mcu_sec_mmr_mcu_0_j7vc_mcu_sec_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 22. "J7VC_MCU_PLL_MMR_MCU_0_J7VC_MCU_PLL_MMR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7vc_mcu_pll_mmr_mcu_0_j7vc_mcu_pll_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 21. "I7_MCU_VBUSM_FSS1_SAFETY_GASKET_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for I7_mcu_vbusm_fss1_safety_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "I7_MCU_VBUSM_FSS1_SAFETY_GASKET_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for I7_mcu_vbusm_fss1_safety_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 19. "I7_MCU_VBUSM_FSS1_SAFETY_GASKET_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for I7_mcu_vbusm_fss1_safety_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 18. "I7_MCU_VBUSM_FSS0_SAFETY_GASKET_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for I7_mcu_vbusm_fss0_safety_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "I7_MCU_VBUSM_FSS0_SAFETY_GASKET_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for I7_mcu_vbusm_fss0_safety_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 16. "I7_MCU_VBUSM_FSS0_SAFETY_GASKET_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for I7_mcu_vbusm_fss0_safety_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 15. "IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Ivdc_data_safeg_vbusm_64b_ref_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 14. "IVDC_DATA_SAFEG_VBUSM_64B_REF_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ivdc_data_safeg_vbusm_64b_ref_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "IVDC_DATA_SAFEG_VBUSM_64B_REF_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Ivdc_data_safeg_vbusm_64b_ref_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 12. "IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_infra_vbusp_32b_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_infra_vbusp_32b_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 10. "IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_infra_vbusp_32b_infra_safeg_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 9. "IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_infra_vbusp_32b_infra_safeg_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_infra_vbusp_32b_infra_safeg_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_data_vbusm_64b_src_vbuss_pend" "0,1" newline bitfld.long 0x0 6. "ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Icor_mcu_data_vbusm_64b_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 5. "ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Icor_mcu_data_vbusm_64b_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 4. "IMCU_COR_FW_VBUSP_32B_SRC_P2M_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_fw_vbusp_32b_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_fw_vbusp_32b_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 2. "IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_fw_vbusp_32b_soc_fw_safeg_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 1. "IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_fw_vbusp_32b_soc_fw_safeg_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Imcu_cor_fw_vbusp_32b_soc_fw_safeg_wr_ramecc_pend" "0,1" line.long 0x4 "REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 31. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 30. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 29. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 28. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 27. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 26. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_MAIN_INFRA_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_MCU_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 25. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 24. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7AM_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 23. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7AM_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_1_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_1_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 21. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 19. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 18. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 17. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 16. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7AM_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7AM_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 15. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 14. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 13. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 12. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 11. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_ISA3SS_AM62_MCU_0_PKTDMA_MEM_M2M_BRIDGE_J7AM_MCU_CBASS_ISA3SS_AM62_MCU_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_fw_cbass_mcu_0_j7am_mcu_fw_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_pend" "0,1" line.long 0x8 "REGS_ded_enable_set_reg2,Interrupt Enable Set Register 2" bitfld.long 0x8 24. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x8 23. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 22. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 21. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_3_pend" "0,1" newline bitfld.long 0x8 20. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_2_pend" "0,1" newline bitfld.long 0x8 19. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_1_pend" "0,1" newline bitfld.long 0x8 18. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_0_pend" "0,1" newline bitfld.long 0x8 17. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_12_clk_edc_ctrl_cbass_int_mcu_sysclk0_12_busecc_pend" "0,1" newline bitfld.long 0x8 13. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_ERR_SCR_J7AM_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_err_scr_j7am_mcu_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 12. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_CBASS_DEFAULT_ERR_J7AM_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_cbass_default_err_j7am_mcu_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 10. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_CBASS_INT_DMSC_SCR_J7AM_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 9. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 8. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_CBASS_DEFAULT_MMRS_J7AM_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 7. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK12_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 6. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 5. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 4. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 3. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 2. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 1. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 0. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0xB line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_ERR_SCR_J7AM_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_fw_cbass_mcu_0_j7am_mcu_fw_cbass_err_scr_j7am_mcu_fw_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 30. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_fw_cbass_mcu_0_j7am_mcu_fw_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 29. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_CBASS_DEFAULT_ERR_J7AM_MCU_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7AM_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_IJ7AM_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7AM_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "IJ7VCL_IEXPORT_VBUSM_64B_MST_MCU_0_MST_MTOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ij7vcl_Iexport_vbusm_64b_mst_mcu_0_mst_mtog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 24. "J7AM_MCU_CTRL_MMR_MCU_0_J7AM_MCU_CTRL_MMR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_ctrl_mmr_mcu_0_j7am_mcu_ctrl_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 23. "J7VC_MCU_SEC_MMR_MCU_0_J7VC_MCU_SEC_MMR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7vc_mcu_sec_mmr_mcu_0_j7vc_mcu_sec_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 22. "J7VC_MCU_PLL_MMR_MCU_0_J7VC_MCU_PLL_MMR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7vc_mcu_pll_mmr_mcu_0_j7vc_mcu_pll_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 21. "I7_MCU_VBUSM_FSS1_SAFETY_GASKET_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for I7_mcu_vbusm_fss1_safety_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "I7_MCU_VBUSM_FSS1_SAFETY_GASKET_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for I7_mcu_vbusm_fss1_safety_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 19. "I7_MCU_VBUSM_FSS1_SAFETY_GASKET_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for I7_mcu_vbusm_fss1_safety_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 18. "I7_MCU_VBUSM_FSS0_SAFETY_GASKET_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for I7_mcu_vbusm_fss0_safety_gasket_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "I7_MCU_VBUSM_FSS0_SAFETY_GASKET_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for I7_mcu_vbusm_fss0_safety_gasket_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 16. "I7_MCU_VBUSM_FSS0_SAFETY_GASKET_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for I7_mcu_vbusm_fss0_safety_gasket_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 15. "IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Ivdc_data_safeg_vbusm_64b_ref_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 14. "IVDC_DATA_SAFEG_VBUSM_64B_REF_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ivdc_data_safeg_vbusm_64b_ref_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "IVDC_DATA_SAFEG_VBUSM_64B_REF_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Ivdc_data_safeg_vbusm_64b_ref_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 12. "IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_infra_vbusp_32b_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 11. "IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_infra_vbusp_32b_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 10. "IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_infra_vbusp_32b_infra_safeg_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 9. "IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_infra_vbusp_32b_infra_safeg_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_infra_vbusp_32b_infra_safeg_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_data_vbusm_64b_src_vbuss_pend" "0,1" newline bitfld.long 0x0 6. "ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Icor_mcu_data_vbusm_64b_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 5. "ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Icor_mcu_data_vbusm_64b_dst_vbuss_pend" "0,1" newline bitfld.long 0x0 4. "IMCU_COR_FW_VBUSP_32B_SRC_P2M_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_fw_vbusp_32b_src_p2m_busecc_pend" "0,1" newline bitfld.long 0x0 3. "IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_fw_vbusp_32b_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 2. "IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_fw_vbusp_32b_soc_fw_safeg_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 1. "IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_fw_vbusp_32b_soc_fw_safeg_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Imcu_cor_fw_vbusp_32b_soc_fw_safeg_wr_ramecc_pend" "0,1" line.long 0x4 "REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 31. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 30. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 29. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 28. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 27. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 26. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_MAIN_INFRA_VBUSP_L0_M2P_BRIDGE_EXPORT_J7AM_MCU_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 25. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 24. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7AM_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 23. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7AM_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_1_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_1_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 21. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU_FSS_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 19. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 18. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 17. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 16. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IJ7AM_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7AM_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 15. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 14. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 13. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 12. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 11. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_ISA3SS_AM62_MCU_0_PKTDMA_MEM_M2M_BRIDGE_J7AM_MCU_CBASS_ISA3SS_AM62_MCU_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "J7AM_MCU_FW_CBASS_MCU_0_J7AM_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_fw_cbass_mcu_0_j7am_mcu_fw_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_pend" "0,1" line.long 0x8 "REGS_ded_enable_clr_reg2,Interrupt Enable Clear Register 2" bitfld.long 0x8 24. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x8 23. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_MCU_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 22. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_J7AM_MCU_CBASS_EXPORT_J7AM_RC_TO_MCU_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 21. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_3_pend" "0,1" newline bitfld.long 0x8 20. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_2_pend" "0,1" newline bitfld.long 0x8 19. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_1_pend" "0,1" newline bitfld.long 0x8 18. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_mcu_sysclk0_6_busecc_0_pend" "0,1" newline bitfld.long 0x8 17. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_mcu_sysclk0_3_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_mcu_sysclk0_12_clk_edc_ctrl_cbass_int_mcu_sysclk0_12_busecc_pend" "0,1" newline bitfld.long 0x8 13. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_ERR_SCR_J7AM_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_err_scr_j7am_mcu_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 12. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_CBASS_DEFAULT_ERR_J7AM_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 10. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_CBASS_INT_DMSC_SCR_J7AM_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 9. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_mcu_cbass_mcu_0_j7am_mcu_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 8. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_CBASS_DEFAULT_MMRS_J7AM_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 7. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32_PCLK12_SCR_J7AM_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 6. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 5. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 4. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 3. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7AM_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 2. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 1. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 0. "J7AM_MCU_CBASS_MCU_0_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7AM_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCU_MCSPI0_CFG (MCU_MCSPI0_CFG)" base ad:0x40300000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_HL_REV,IP Revision Identifier (X.Y.R)" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" newline hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any)." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" newline bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "CFG_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "CFG_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" rgroup.long 0x110++0x2B line.long 0x0 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1" bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1" line.long 0x4 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0" rbitfld.long 0x4 0. "RESETDONE,Internal Reset Monitoring" "0,1" line.long 0x8 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x8 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1" bitfld.long 0x8 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" newline bitfld.long 0x8 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1" bitfld.long 0x8 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" newline bitfld.long 0x8 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1" bitfld.long 0x8 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1" newline bitfld.long 0x8 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1" bitfld.long 0x8 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1" bitfld.long 0x8 7. "RESERVED,Reads returns 0" "0,1" newline bitfld.long 0x8 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1" bitfld.long 0x8 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1" bitfld.long 0x8 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1" newline bitfld.long 0x8 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1" bitfld.long 0x8 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1" bitfld.long 0x8 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1" newline bitfld.long 0x8 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1" line.long 0xC "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0xC 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0xC 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1" bitfld.long 0xC 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" newline bitfld.long 0xC 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0xC 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1" bitfld.long 0xC 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1" newline bitfld.long 0xC 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1" bitfld.long 0xC 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0xC 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1" newline bitfld.long 0xC 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 7. "RESERVED,Reads return 0" "0,1" newline bitfld.long 0xC 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1" newline bitfld.long 0xC 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1" newline bitfld.long 0xC 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1" line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x14 11. "SSB,Set status bit" "0,1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1" newline bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1" bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1" bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1" newline bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" newline bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1" newline bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1" bitfld.long 0x18 2. "MS,Master/ Slave" "0,1" newline bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1" bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1" line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3" bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x1C 18. "IS,Input Select" "0,1" bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x1C 7.--11. 1. "WL,SPI word length" bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x1C 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1" line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x24 0. "EN,Channel Enable" "0,1" line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x28 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" rgroup.long 0x140++0xF line.long 0x0 "CFG_CH1CONF,This register is dedicated to the configuration of the channel." bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" rgroup.long 0x154++0xF line.long 0x0 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" rgroup.long 0x168++0xF line.long 0x0 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" rgroup.long 0x17C++0x7 line.long 0x0 "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." rgroup.long 0x1A0++0x3 line.long 0x0 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." tree.end tree "MCU_MCSPI1_CFG (MCU_MCSPI1_CFG)" base ad:0x40310000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_HL_REV,IP Revision Identifier (X.Y.R)" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" newline hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any)." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" newline bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "CFG_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "CFG_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" rgroup.long 0x110++0x2B line.long 0x0 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1" bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1" line.long 0x4 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0" rbitfld.long 0x4 0. "RESETDONE,Internal Reset Monitoring" "0,1" line.long 0x8 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x8 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1" bitfld.long 0x8 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" newline bitfld.long 0x8 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1" bitfld.long 0x8 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" newline bitfld.long 0x8 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1" bitfld.long 0x8 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1" newline bitfld.long 0x8 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1" bitfld.long 0x8 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1" bitfld.long 0x8 7. "RESERVED,Reads returns 0" "0,1" newline bitfld.long 0x8 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1" bitfld.long 0x8 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1" bitfld.long 0x8 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1" newline bitfld.long 0x8 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1" bitfld.long 0x8 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1" bitfld.long 0x8 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1" newline bitfld.long 0x8 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1" line.long 0xC "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0xC 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0xC 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1" bitfld.long 0xC 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" newline bitfld.long 0xC 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0xC 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1" bitfld.long 0xC 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1" newline bitfld.long 0xC 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1" bitfld.long 0xC 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0xC 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1" newline bitfld.long 0xC 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 7. "RESERVED,Reads return 0" "0,1" newline bitfld.long 0xC 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1" newline bitfld.long 0xC 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1" newline bitfld.long 0xC 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1" line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x14 11. "SSB,Set status bit" "0,1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1" newline bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1" bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1" bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1" newline bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" newline bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1" newline bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1" bitfld.long 0x18 2. "MS,Master/ Slave" "0,1" newline bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1" bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1" line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3" bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x1C 18. "IS,Input Select" "0,1" bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x1C 7.--11. 1. "WL,SPI word length" bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x1C 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1" line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x24 0. "EN,Channel Enable" "0,1" line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x28 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" rgroup.long 0x140++0xF line.long 0x0 "CFG_CH1CONF,This register is dedicated to the configuration of the channel." bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" rgroup.long 0x154++0xF line.long 0x0 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" rgroup.long 0x168++0xF line.long 0x0 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" rgroup.long 0x17C++0x7 line.long 0x0 "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." rgroup.long 0x1A0++0x3 line.long 0x0 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." tree.end tree "MCU_MCSPI2_CFG (MCU_MCSPI2_CFG)" base ad:0x40320000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_HL_REV,IP Revision Identifier (X.Y.R)" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" newline hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any)." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" newline bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "CFG_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "CFG_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" rgroup.long 0x110++0x2B line.long 0x0 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1" bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1" line.long 0x4 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0" rbitfld.long 0x4 0. "RESETDONE,Internal Reset Monitoring" "0,1" line.long 0x8 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x8 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1" bitfld.long 0x8 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" newline bitfld.long 0x8 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1" bitfld.long 0x8 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" newline bitfld.long 0x8 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1" bitfld.long 0x8 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1" newline bitfld.long 0x8 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1" bitfld.long 0x8 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1" bitfld.long 0x8 7. "RESERVED,Reads returns 0" "0,1" newline bitfld.long 0x8 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1" bitfld.long 0x8 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1" bitfld.long 0x8 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1" newline bitfld.long 0x8 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1" bitfld.long 0x8 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1" bitfld.long 0x8 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1" newline bitfld.long 0x8 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1" line.long 0xC "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0xC 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0xC 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1" bitfld.long 0xC 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" newline bitfld.long 0xC 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0xC 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1" bitfld.long 0xC 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1" newline bitfld.long 0xC 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1" bitfld.long 0xC 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0xC 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1" newline bitfld.long 0xC 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 7. "RESERVED,Reads return 0" "0,1" newline bitfld.long 0xC 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1" newline bitfld.long 0xC 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1" newline bitfld.long 0xC 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1" line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x14 11. "SSB,Set status bit" "0,1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1" newline bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1" bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1" bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1" newline bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" newline bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1" newline bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1" bitfld.long 0x18 2. "MS,Master/ Slave" "0,1" newline bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1" bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1" line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3" bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x1C 18. "IS,Input Select" "0,1" bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x1C 7.--11. 1. "WL,SPI word length" bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x1C 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1" line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x24 0. "EN,Channel Enable" "0,1" line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x28 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" rgroup.long 0x140++0xF line.long 0x0 "CFG_CH1CONF,This register is dedicated to the configuration of the channel." bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" rgroup.long 0x154++0xF line.long 0x0 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" rgroup.long 0x168++0xF line.long 0x0 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" newline bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "?,?,2: bits field defines the number of interface clock..,?" bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" newline bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" newline bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" newline bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" newline rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" newline rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" rgroup.long 0x17C++0x7 line.long 0x0 "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." rgroup.long 0x1A0++0x3 line.long 0x0 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." tree.end tree "MCU_NAVSS0" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "MCU_NAVSS0_PSILCFG_0_UDMASS_PSILSS_CFG0_PROXY (MCU_NAVSS0_PSILCFG_0_UDMASS_PSILSS_CFG0_PROXY)" base ad:0x2A268000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_UDMASS__PSILCFG0_CFG__PROXY_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "PAR_UDMASS__PSILCFG0_CFG__PROXY_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access. Once set this bit is persistent until manually cleared" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x100++0xB line.long 0x0 "PAR_UDMASS__PSILCFG0_CFG__PROXY_PSIL_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction." bitfld.long 0x0 31. "PROXY_BUSY,Indication that a configuration read or write is in progress" "0,1" bitfld.long 0x0 30. "PROXY_DIR,Direction of configuration transaction" "0,1" bitfld.long 0x0 29. "PROXY_TOUT,Indication that a timeout occurred. This bit should be written to 0 on each new transaction." "0,1" hexmask.long.word 0x0 0.--15. 1. "PROXY_THREAD_ID,Thread ID to which configuration read or write is being sent" line.long 0x4 "PAR_UDMASS__PSILCFG0_CFG__PROXY_PSIL_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction." hexmask.long.byte 0x4 28.--31. 1. "PROXY_BYTEN,Byte enables to use for configuration read or write" hexmask.long.word 0x4 0.--15. 1. "PROXY_ADDRESS,Word (32-bit) address within thread configuration space for transaction" line.long 0x8 "PAR_UDMASS__PSILCFG0_CFG__PROXY_PSIL_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction." hexmask.long 0x8 0.--31. 1. "PROXY_WDATA,Configuration data word to be written" rgroup.long 0x140++0x3 line.long 0x0 "PAR_UDMASS__PSILCFG0_CFG__PROXY_PSIL_RDATA,The Read Data Register contains the data which which was read back during the configuration transaction." hexmask.long 0x0 0.--31. 1. "PROXY_RDATA,Configuration data word that was read" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "MCU_NAVSS0_PSILSS_0_UDMASS_PSILSS0_CFG_MMRS (MCU_NAVSS0_PSILSS_0_UDMASS_PSILSS0_CFG_MMRS)" base ad:0x285E0000 rgroup.long 0x0++0x7 line.long 0x0 "PAR_UDMASS__PSILSS0_CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "PAR_UDMASS__PSILSS0_CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." rgroup.long 0x10++0x3 line.long 0x0 "PAR_UDMASS__PSILSS0_CFG__MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "PAR_UDMASS__PSILSS0_CFG__MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." rgroup.long 0x40++0x3 line.long 0x0 "PAR_UDMASS__PSILSS0_CFG__MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "MCU_NAVSS0_UDMAP_0_UDMASS_UDMAP0_CFG_GCFG (MCU_NAVSS0_UDMAP_0_UDMASS_UDMAP0_CFG_GCFG)" base ad:0x285C0000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_UDMASS__UDMAP0_CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "PAR_UDMASS__UDMAP0_CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the UDMA-P in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This field sets the timeout duration in clock cycles. This field controls the minimum amount of time that an Rx channel will be required to wait when it encounters a buffer starvation condition and the Rx error handling bit is set to 1.." line.long 0x4 "PAR_UDMASS__UDMAP0_CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "PAR_UDMASS__UDMAP0_CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x1C++0x3 line.long 0x0 "PAR_UDMASS__UDMAP0_CFG__GCFG_UTC_CTRL,The external UTC control register provides a mapping of logical to physical thread IDs ." hexmask.long.word 0x0 0.--15. 1. "UTC_CHAN_START,This field specifies the starting PSI-L thread number for the external UTC" rgroup.long 0x20++0xF line.long 0x0 "PAR_UDMASS__UDMAP0_CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this UDMA-P instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "PAR_UDMASS__UDMAP0_CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this UDMA-P instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "PAR_UDMASS__UDMAP0_CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx internal channel count" hexmask.long.word 0x8 9.--17. 1. "ECHAN_CNT,Tx external channel count" hexmask.long.word 0x8 0.--8. 1. "TCHAN_CNT,Tx internal channel count" line.long 0xC "PAR_UDMASS__UDMAP0_CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,Tx ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,Tx high capacity internal channel count" hexmask.long.word 0xC 0.--13. 1. "RFLOW_CNT,Rx flow table entry count" rgroup.long 0x40++0xF line.long 0x0 "PAR_UDMASS__UDMAP0_CFG__GCFG_PERF0,This register provides thresholds for outstanding virtualized read/write commands from interface mem0" hexmask.long.byte 0x0 16.--23. 1. "VRD_THRESH0,Virt read command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x0 0.--7. 1. "VWR_THRESH0,Virt write command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x4 "PAR_UDMASS__UDMAP0_CFG__GCFG_PERF1,This register provides thresholds for outstanding virtualized read/write commands from interface mem1" hexmask.long.byte 0x4 16.--23. 1. "VRD_THRESH1,Virt read command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x4 0.--7. 1. "VWR_THRESH1,Virt write command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x8 "PAR_UDMASS__UDMAP0_CFG__GCFG_PERF2,This register provides thresholds for outstanding virtualized read commands from interface memr" hexmask.long.byte 0x8 16.--23. 1. "VRD_THRESH2,Virt read command throttling threshold for memr. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." line.long 0xC "PAR_UDMASS__UDMAP0_CFG__GCFG_PERF3,This register provides thresholds for outstanding virtualized write commands from interface memw" hexmask.long.byte 0xC 0.--7. 1. "VWR_THRESH3,Virt write command throttling threshold for memw. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." rgroup.long 0x60++0x7 line.long 0x0 "PAR_UDMASS__UDMAP0_CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x0 0.--31. 1. "NOGATE_LO,When set inhibits automatic gating of clock." line.long 0x4 "PAR_UDMASS__UDMAP0_CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x4 0.--31. 1. "NOGATE_HI,When set inhibits automatic gating of clock." rgroup.long 0x78++0xB line.long 0x0 "PAR_UDMASS__UDMAP0_CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "PAR_UDMASS__UDMAP0_CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" line.long 0x8 "PAR_UDMASS__UDMAP0_CFG__GCFG_RFLOWFWOES,The Rx Flow FW OES Register specifies a destination event number to which an event should be sent if an out of range flow ID is received on a packet." hexmask.long.word 0x8 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x88++0x3 line.long 0x0 "PAR_UDMASS__UDMAP0_CFG__GCFG_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check. Values in this register will remain persistent once an exception has been detected.." bitfld.long 0x0 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet. Once this bit is set the remaining fields in this register will not be modified. SW is required to write this bit to 0 to allow another.." "0,1" hexmask.long.word 0x0 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet" hexmask.long.word 0x0 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received" tree.end endif tree "MCU_NAVSS0_INTR_ROUTER_0_INTR0_CFG (MCU_NAVSS0_INTR_ROUTER_0_INTR0_CFG)" base ad:0x28540000 rgroup.long 0x0++0x3 line.long 0x0 "INTR0__CFG__INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" rgroup.long 0x4++0x3 line.long 0x0 "INTR0__CFG__INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.word 0x0 0.--8. 1. "MUX_CNTL,Mux control for interrupt N" tree.end tree "MCU_NAVSS0_MODSS_CFG (MCU_NAVSS0_MODSS_CFG)" base ad:0x28520000 rgroup.long 0x0++0x3 line.long 0x0 "REGS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end tree "MCU_NAVSS0_PROXY0" tree "MCU_NAVSS0_PROXY0_PROXY" tree "MCU_NAVSS0_PROXY0_PROXY0" tree "MCU_NAVSS0_PROXY0_PROXY0_BUF_CFG (MCU_NAVSS0_PROXY0_PROXY0_BUF_CFG)" base ad:0x2A580000 group.long 0x0++0x3 line.long 0x0 "PROXY0__CFG__BUF__CFG__CFG_EVT_REG,The Proxy Event for the proxy" hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Proxy Error Event" tree.end tree "MCU_NAVSS0_PROXY0_PROXY0_TARGET0_DATA (MCU_NAVSS0_PROXY0_PROXY0_TARGET0_DATA)" base ad:0x2A500000 group.long 0x0++0x7 line.long 0x0 "PROXY0__SRC__TARGET0_DATA_CTL_REG,The Proxy Control for the proxy" bitfld.long 0x0 24.--26. "ELSIZE,Queue element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = 512 bytes" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--17. "MODE,Proxy Queue Mode that determines how to access the queue." "0,1,2,3" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Proxy Queue" line.long 0x4 "PROXY0__SRC__TARGET0_DATA_ST_REG,The Proxy Status for the proxy" bitfld.long 0x4 31. "ERROR,Proxy Error status" "0,1" group.long 0x200++0x3 line.long 0x0 "PROXY0__SRC__TARGET0_DATA_DATA_REG,The Proxy Data for the proxy. target and channel" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Data" tree.end tree.end tree "MCU_NAVSS0_PROXY0_PROXY_CFG_BUF (MCU_NAVSS0_PROXY0_PROXY_CFG_BUF)" base ad:0x285A0000 rgroup.long 0x0++0x3 line.long 0x0 "PROXY0__CFG__BUF__BUFRAM_SLV__RAM_DATA_REG,The Proxy Buffer for the proxy" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Buffer Data" tree.end tree "MCU_NAVSS0_PROXY0_PROXY_CFG_GCFG (MCU_NAVSS0_PROXY0_PROXY_CFG_GCFG)" base ad:0x28590000 rgroup.long 0x0++0x7 line.long 0x0 "PROXY0__CFG__BUF__CFG__GCFG_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "PROXY0__CFG__BUF__CFG__GCFG_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "PROXY0__CFG__BUF__CFG__GCFG_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end tree.end tree.end tree "MCU_NAVSS0_RINGACC0_UDMASS" tree "MCU_NAVSS0_RINGACC0_UDMASS_RINGACC0_CFG (MCU_NAVSS0_RINGACC0_UDMASS_RINGACC0_CFG)" base ad:0x28440000 rgroup.long 0x40++0x13 line.long 0x0 "PAR_UDMASS__RINGACC0_CFG__CFG_BA_LO,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Tx Ring base address (LSBs)" line.long 0x4 "PAR_UDMASS__RINGACC0_CFG__CFG_BA_HI,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of.." hexmask.long.word 0x4 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)" line.long 0x8 "PAR_UDMASS__RINGACC0_CFG__CFG_SIZE,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear.." bitfld.long 0x8 30.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3" bitfld.long 0x8 24.--26. "ELSIZE,Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED" "?,?,?,?,?,?,?,7: RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number." line.long 0xC "PAR_UDMASS__RINGACC0_CFG__CFG_EVT,The Ring Event Register contains the event number for the ring for when it is active or empty." hexmask.long.word 0xC 0.--15. 1. "EVT,Defines the event for this ring or queue." line.long 0x10 "PAR_UDMASS__RINGACC0_CFG__CFG_ORDERID,The Ring OrderID Register contains the bus orderid value for the ring memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for this ring or queue." tree.end tree "MCU_NAVSS0_RINGACC0_UDMASS_RINGACC0_CFG_GCFG (MCU_NAVSS0_RINGACC0_UDMASS_RINGACC0_CFG_GCFG)" base ad:0x285D0000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_UDMASS__RINGACC0_CFG__GCFG_revision,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "PAR_UDMASS__RINGACC0_CFG__GCFG_trace_ctl,Trace Control Register" bitfld.long 0x0 31. "EN,Trace enable 0 = disable 1 = enable." "0: disable,1: enable" bitfld.long 0x0 30. "ALL_QUEUES,Trace everything 0 = only the selected queue 1 = every queue." "0: only the selected queue,1: every queue" bitfld.long 0x0 29. "MSG,Trace message data 0 = include only the operation 1 = include message data." "0: include only the operation,1: include message data" newline hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number when tracing a single queue." rgroup.long 0x20++0x3 line.long 0x0 "PAR_UDMASS__RINGACC0_CFG__GCFG_overflow,Overflow Queue Register" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue to send overflow messages. A value of 0xffff will disable the overflow function." rgroup.long 0x40++0x3 line.long 0x0 "PAR_UDMASS__RINGACC0_CFG__GCFG_error_evt,Error Event Register" hexmask.long.word 0x0 0.--15. 1. "EVT,Event to send when detecting a bus error." rgroup.long 0x44++0x3 line.long 0x0 "PAR_UDMASS__RINGACC0_CFG__GCFG_error_log,Error Log Register. A read of this register will clear the pending error log event and allow a new error to be captured. It does not clear the contents of this register which are only valid while the error event.." bitfld.long 0x0 31. "PUSH,Bus error was caused by a push. 0 = pop. 1 = push." "0: pop,1: push" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue that received the bus error." tree.end tree "MCU_NAVSS0_RINGACC0_UDMASS_RINGACC0_CFG_MON (MCU_NAVSS0_RINGACC0_UDMASS_RINGACC0_CFG_MON)" base ad:0x2A280000 rgroup.long 0x0++0xF line.long 0x0 "PAR_UDMASS__RINGACC0_CFG__MON_control,Monitor Control Register" hexmask.long.word 0x0 16.--31. 1. "EVT,Event to produce." hexmask.long.byte 0x0 8.--11. 1. "SOURCE,Monitor source selection. 0 = element count. 1 = reserved. 2 = reserved." bitfld.long 0x0 0.--2. "MODE,Monitor Mode. 0 = disabled. 1 = push/pop statistics capture. 2 = low/high threshold checks. 3 = low/high watermarking. 4 = starvation counting." "0: disabled,1: push/pop statistics capture,2: low/high threshold checks,3: low/high watermarking,4: starvation counting,?,?,?" line.long 0x4 "PAR_UDMASS__RINGACC0_CFG__MON_queue,Monitor Queue Register" hexmask.long.word 0x4 0.--15. 1. "QUEUE,Queue to monitor." line.long 0x8 "PAR_UDMASS__RINGACC0_CFG__MON_data0,Monitor Data Register" hexmask.long 0x8 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pushes. For mode 2 this is read-write and the low threshold value. For mode 3 this is read only and the low watermark. For mode 4 this is read only and the starvation count." line.long 0xC "PAR_UDMASS__RINGACC0_CFG__MON_data1,Monitor Data Register" hexmask.long 0xC 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pops. For mode 2 this is read-write and the high threshold value. For mode 3 this is read only and the high watermark. For mode 4 this is not used." tree.end tree "MCU_NAVSS0_RINGACC0_UDMASS_RINGACC0_CFG_RT (MCU_NAVSS0_RINGACC0_UDMASS_RINGACC0_CFG_RT)" base ad:0x2B800000 rgroup.long 0x10++0x3 line.long 0x0 "PAR_UDMASS__RINGACC0_CFG__RT_RT_DB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write operation." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0xF line.long 0x0 "PAR_UDMASS__RINGACC0_CFG__RT_RT_OCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring.." hexmask.long.tbyte 0x0 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0x4 "PAR_UDMASS__RINGACC0_CFG__RT_RT_INDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel." hexmask.long.tbyte 0x4 0.--19. 1. "INDX,Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." line.long 0x8 "PAR_UDMASS__RINGACC0_CFG__RT_RT_HWOCC,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a.." hexmask.long.tbyte 0x8 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0xC "PAR_UDMASS__RINGACC0_CFG__RT_RT_HWINDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel." hexmask.long.tbyte 0xC 0.--19. 1. "INDX,Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." tree.end tree "MCU_NAVSS0_RINGACC0_UDMASS_RINGACC0_FIFOS (MCU_NAVSS0_RINGACC0_UDMASS_RINGACC0_FIFOS)" base ad:0x2B000000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_UDMASS__RINGACC0_SRC__FIFOS_RING_HEAD_DATA,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x200++0x3 line.long 0x0 "PAR_UDMASS__RINGACC0_SRC__FIFOS_RING_TAIL_DATA,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x400++0x3 line.long 0x0 "PAR_UDMASS__RINGACC0_SRC__FIFOS_PEEK_HEAD_DATA,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element. These registers are virtual and non-static (i.e. they are just address locations.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." rgroup.long 0x600++0x3 line.long 0x0 "PAR_UDMASS__RINGACC0_SRC__FIFOS_PEEK_TAIL_DATA,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element. These registers are virtual and non-static (i.e. they are just address locations.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." tree.end tree "MCU_NAVSS0_RINGACC0_UDMASS_RINGACC0_ISC (MCU_NAVSS0_RINGACC0_UDMASS_RINGACC0_ISC)" base ad:0x45820000 rgroup.long 0x0++0x7 line.long 0x0 "UDMASS_RINGACC0_ISC_ISC_control,The ISC a Region b Control Register defines the control fields for the ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared. Has precedence over priv set bits." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure. Has precedence over secure enable bits." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "UDMASS_RINGACC0_ISC_ISC_control2,The ISC a Region b Control Register 2 defines the control fields for the ISC." bitfld.long 0x4 31. "PASS_V,No virtID replacement pass through value." "0,1" bitfld.long 0x4 28.--29. "ATYPE,Defines the output address type. 0 = physical no memory attributes. 1 = intermediate. 2 = virtual. 3 = physical with memory attributes." "0: physical no memory attributes,1: intermediate,2: virtual,3: physical with memory attributes" hexmask.long.word 0x4 16.--27. 1. "VIRTID,Virt ID." tree.end tree.end tree "MCU_NAVSS0_SEC_PROXY0" tree "MCU_NAVSS0_SEC_PROXY0_SEC_PROXY0_CFG (MCU_NAVSS0_SEC_PROXY0_SEC_PROXY0_CFG)" base ad:0x285B0000 rgroup.long 0x0++0x7 line.long 0x0 "SEC_PROXY0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "SEC_PROXY0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 16.--31. 1. "MSG_SIZE,Supported message size in bytes." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "SEC_PROXY0__CFG__MMRS_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end tree "MCU_NAVSS0_SEC_PROXY0_SEC_PROXY0_CFG_RT (MCU_NAVSS0_SEC_PROXY0_SEC_PROXY0_CFG_RT)" base ad:0x2A380000 rgroup.long 0x0++0x7 line.long 0x0 "SEC_PROXY0__CFG__RT_status,The Status Register gives status for proxy thread a." bitfld.long 0x0 31. "ERROR,Error detected on proxy thread. The error will also use the err_evt field to generate an error event which can generate an interrupt. While in error a proxy thread will not process any operations. Write a 0 to clear the error and reset the proxy.." "0,1" rbitfld.long 0x0 30. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread." hexmask.long.byte 0x0 0.--7. 1. "CUR_CNT,Current message count for the proxy thread. For an inbound proxy this is the number of available messages. For an outbound proxy this is the number of free messages that can be written. This value will initialize itself to 0 if the THREAD[a]_CTL.." line.long 0x4 "SEC_PROXY0__CFG__RT_thr,The Threshold Register controls the threshold for proxy thread a events." hexmask.long.byte 0x4 0.--7. 1. "THR_CNT,Threshold count that causes proxy thread events. For an outbound proxy this will be the number of free messages to cause an event. For an inbound proxy this will be the number of available messages to cause an event." tree.end tree "MCU_NAVSS0_SEC_PROXY0_SEC_PROXY0_CFG_SCFG (MCU_NAVSS0_SEC_PROXY0_SEC_PROXY0_CFG_SCFG)" base ad:0x2A400000 rgroup.long 0x0++0x13 line.long 0x0 "SEC_PROXY0__CFG__SCFG_buffer_l,The Buffer Register defines the pointer for the external buffer." hexmask.long 0x0 0.--31. 1. "BASE_L,The base address for the external buffer lower 32 bits." line.long 0x4 "SEC_PROXY0__CFG__SCFG_buffer_h,The Buffer Register defines the pointer for the external buffer." hexmask.long.word 0x4 0.--15. 1. "BASE_H,The base address for the external buffer upper 16 bits." line.long 0x8 "SEC_PROXY0__CFG__SCFG_target_l,The Target Register defines the pointer for the external target." hexmask.long 0x8 0.--31. 1. "BASE_L,The base address for the external target lower 32 bits." line.long 0xC "SEC_PROXY0__CFG__SCFG_target_h,The Target Register defines the pointer for the external target." hexmask.long.word 0xC 0.--15. 1. "BASE_H,The base address for the external target upper 16 bits." line.long 0x10 "SEC_PROXY0__CFG__SCFG_ORDERID,The Buffer OrderID Register contains the bus orderid value for the buffer memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for the buffer access with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for the buffer access." rgroup.long 0x1000++0xB line.long 0x0 "SEC_PROXY0__CFG__SCFG_ctl,The Control Register defines controls for proxy thread a." bitfld.long 0x0 31. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread. Is not used otherwise." hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number in the target to use for the proxy thread. If the target base does not start at queue 0 then this is the relative queue number from that base queue." line.long 0x4 "SEC_PROXY0__CFG__SCFG_evt_map,The Event Map Register defines the event numbers for proxy thread a." hexmask.long.word 0x4 16.--31. 1. "ERR_EVT,Event number for an error from the proxy thread." hexmask.long.word 0x4 0.--15. 1. "THR_EVT,Event number for a threshold event from the proxy thread." line.long 0x8 "SEC_PROXY0__CFG__SCFG_dst,The Destination Register defines the destination proxy thread for outbound proxy thread a." hexmask.long.word 0x8 0.--15. 1. "THREAD,The proxy thread that is the destination of messages from this outbound proxy thread based on the queue numbers. This is ignored for inbound proxy threads." tree.end tree "MCU_NAVSS0_SEC_PROXY0_SEC_PROXY0_TARGET_DATA (MCU_NAVSS0_SEC_PROXY0_SEC_PROXY0_TARGET_DATA)" base ad:0x2A480000 rgroup.long 0x0++0x3 line.long 0x0 "SEC_PROXY0__SRC__TARGET_DATA_private,The Proxy Private register contains private information for the proxy thread a and should not be written. writes are ignored. Reads are allowed to know the source thread of the message." hexmask.long.word 0x0 0.--9. 1. "SRC_THR,Proxy source thread of message." rgroup.long 0x4++0x3 line.long 0x0 "SEC_PROXY0__SRC__TARGET_DATA_message,The Message Data for proxy thread a. The word with index b = 14 contains the completion final byte." hexmask.long 0x0 0.--31. 1. "DATA,Proxy Message Data" tree.end tree.end tree "MCU_NAVSS0_UDMASS" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "MCU_NAVSS0_UDMASS_INTA_0_UDMASS_INTA0_CFG (MCU_NAVSS0_UDMASS_INTA_0_UDMASS_INTA0_CFG)" base ad:0x283C0000 rgroup.quad 0x0++0x17 line.quad 0x0 "PAR_UDMASS__UDMASS_INTA0_CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "PAR_UDMASS__UDMASS_INTA0_CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "PAR_UDMASS__UDMASS_INTA0_CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif tree "MCU_NAVSS0_UDMASS_ECC_AGGR0_UDMASS_ECCAGGR0 (MCU_NAVSS0_UDMASS_ECC_AGGR0_UDMASS_ECCAGGR0)" base ad:0x28381000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x13 line.long 0x0 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "UDMAP0_RPCF1_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 30. "UDMAP0_RPCF0_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x4 29. "UDMAP0_RFFW_RAMECC_PEND,Interrupt Pending Status for udmap0_rffw_ramecc_pend" "0,1" newline bitfld.long 0x4 28. "UDMAP0_TPCF4_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcf4_ramecc_pend" "0,1" newline bitfld.long 0x4 27. "UDMAP0_TPCF1_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "UDMAP0_TPCF0_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x4 25. "UDMAP0_TSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_tstate_ramecc_pend" "0,1" newline bitfld.long 0x4 24. "UDMAP0_RPCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x4 23. "UDMAP0_RPCU_SB1_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcu_sb1_ramecc_pend" "0,1" newline bitfld.long 0x4 22. "UDMAP0_RPCU_SB0_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcu_sb0_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "UDMAP0_RPTRCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "UDMAP0_RPTRSB2_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "UDMAP0_RPTRSB1_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "UDMAP0_RPTRSB0_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "UDMAP0_TPTRCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "UDMAP0_TPTRSB2_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "UDMAP0_TPTRSB1_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "UDMAP0_TPTRSB0_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "UDMAP0_RPBUF_PF_RAMECC_PEND,Interrupt Pending Status for udmap0_rpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "UDMAP0_RPBUF_DF_RAMECC_PEND,Interrupt Pending Status for udmap0_rpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "UDMAP0_RPBUF_CF_RAMECC_PEND,Interrupt Pending Status for udmap0_rpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "UDMAP0_RPRQ_RAMECC_PEND,Interrupt Pending Status for udmap0_rprq_ramecc_pend" "0,1" newline bitfld.long 0x4 9. "UDMAP0_RPCFG_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcfg_ramecc_pend" "0,1" newline bitfld.long 0x4 8. "UDMAP0_RPSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_rpstate_ramecc_pend" "0,1" newline bitfld.long 0x4 7. "UDMAP0_TPCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "UDMAP0_TPCU_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcu_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "UDMAP0_TPBUF_PF_RAMECC_PEND,Interrupt Pending Status for udmap0_tpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "UDMAP0_TPBUF_DF_RAMECC_PEND,Interrupt Pending Status for udmap0_tpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "UDMAP0_TPBUF_CF_RAMECC_PEND,Interrupt Pending Status for udmap0_tpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "UDMAP0_TPCFG_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcfg_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "UDMAP0_TPSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_tpstate_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 31. "UDMASS_INTA0_MC_ECC_PEND,Interrupt Pending Status for udmass_inta0_mc_ecc_pend" "0,1" newline bitfld.long 0x8 30. "UDMASS_INTA0_SR_ECC_PEND,Interrupt Pending Status for udmass_inta0_sr_ecc_pend" "0,1" newline bitfld.long 0x8 29. "UDMASS_INTA0_IM_ECC_PEND,Interrupt Pending Status for udmass_inta0_im_ecc_pend" "0,1" newline bitfld.long 0x8 28. "NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_udmass_inta0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 27. "RINGACC0_ECC_PEND,Interrupt Pending Status for ringacc0_ecc_pend" "0,1" newline bitfld.long 0x8 26. "NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_ringacc0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 25. "NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_ringacc0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 24. "NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_udmap0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_udmap0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 22. "UDMAP0_RRNGOCC_RAMECC_PEND,Interrupt Pending Status for udmap0_rrngocc_ramecc_pend" "0,1" newline bitfld.long 0x8 21. "UDMAP0_TRNGOCC_RAMECC_PEND,Interrupt Pending Status for udmap0_trngocc_ramecc_pend" "0,1" newline bitfld.long 0x8 20. "UDMAP0_PSILTID_RAMECC_PEND,Interrupt Pending Status for udmap0_psiltid_ramecc_pend" "0,1" newline bitfld.long 0x8 19. "UDMAP0_PSILR_RAMECC_PEND,Interrupt Pending Status for udmap0_psilr_ramecc_pend" "0,1" newline bitfld.long 0x8 18. "UDMAP0_SDEC3_RAMECC_PEND,Interrupt Pending Status for udmap0_sdec3_ramecc_pend" "0,1" newline bitfld.long 0x8 17. "UDMAP0_SDEC0_RAMECC_PEND,Interrupt Pending Status for udmap0_sdec0_ramecc_pend" "0,1" newline bitfld.long 0x8 16. "UDMAP0_RDEC2_RAMECC_PEND,Interrupt Pending Status for udmap0_rdec2_ramecc_pend" "0,1" newline bitfld.long 0x8 15. "UDMAP0_RDEC1_RAMECC_PEND,Interrupt Pending Status for udmap0_rdec1_ramecc_pend" "0,1" newline bitfld.long 0x8 14. "UDMAP0_RDEC0_RAMECC_PEND,Interrupt Pending Status for udmap0_rdec0_ramecc_pend" "0,1" newline bitfld.long 0x8 13. "UDMAP0_REVTCNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_revtcntr_ramecc_pend" "0,1" newline bitfld.long 0x8 12. "UDMAP0_TEVTCNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_tevtcntr_ramecc_pend" "0,1" newline bitfld.long 0x8 11. "UDMAP0_STS_RAMECC3_PEND,Interrupt Pending Status for udmap0_sts_ramecc3_pend" "0,1" newline bitfld.long 0x8 10. "UDMAP0_STS_RAMECC2_PEND,Interrupt Pending Status for udmap0_sts_ramecc2_pend" "0,1" newline bitfld.long 0x8 9. "UDMAP0_STS_RAMECC1_PEND,Interrupt Pending Status for udmap0_sts_ramecc1_pend" "0,1" newline bitfld.long 0x8 8. "UDMAP0_STS_RAMECC0_PEND,Interrupt Pending Status for udmap0_sts_ramecc0_pend" "0,1" newline bitfld.long 0x8 7. "UDMAP0_EH_RAMECC_PEND,Interrupt Pending Status for udmap0_eh_ramecc_pend" "0,1" newline bitfld.long 0x8 6. "UDMAP0_PROXY_RAMECC_PEND,Interrupt Pending Status for udmap0_proxy_ramecc_pend" "0,1" newline bitfld.long 0x8 5. "UDMAP0_RSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_rstate_ramecc_pend" "0,1" newline bitfld.long 0x8 4. "UDMAP0_RFLOW1_RAMECC_PEND,Interrupt Pending Status for udmap0_rflow1_ramecc_pend" "0,1" newline bitfld.long 0x8 3. "UDMAP0_RFLOW0_RAMECC_PEND,Interrupt Pending Status for udmap0_rflow0_ramecc_pend" "0,1" newline bitfld.long 0x8 2. "UDMAP0_RPCF4_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf4_ramecc_pend" "0,1" newline bitfld.long 0x8 1. "UDMAP0_RPCF3_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf3_ramecc_pend" "0,1" newline bitfld.long 0x8 0. "UDMAP0_RPCF2_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf2_ramecc_pend" "0,1" line.long 0xC "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_sec_status_reg2,Interrupt Status Register 2" bitfld.long 0xC 31. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 30. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 29. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 28. "NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_psilss0_cfg_navss_mcu_j7_udmass_psilss0_cfg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 27. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 26. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 25. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 24. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 23. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 22. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_psilss0_l2p_dmsc_evt_navss_mcu_j7_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 21. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_psilss0_l2p_udmap0_strm_navss_mcu_j7_udmass_psilss0_l2p_udmap0_strm_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 20. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_psilss0_l2p_saul0_psil_navss_mcu_j7_udmass_psilss0_l2p_saul0_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 19. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_psilss0_l2p_pdma_adc_psil_navss_mcu_j7_udmass_psilss0_l2p_pdma_adc_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 18. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 17. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 16. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 15. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_j7_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 14. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_psilss0_l2p_navss_psil_navss_mcu_j7_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 13. "NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 12. "NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 11. "NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 10. "NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 9. "NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_psilss0_udmap0_strm_safeg_navss_mcu_j7_udmass_psilss0_udmap0_strm_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 8. "NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_psilss0_saul0_psil_safeg_navss_mcu_j7_udmass_psilss0_saul0_psil_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 7. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 6. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 5. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 4. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 3. "NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_psilss0_cpsw0_psil_safeg_navss_mcu_j7_udmass_psilss0_cpsw0_psil_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 2. "NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_SCR_E_GCLK_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 1. "NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_E_GCLK_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 0. "UDMASS_INTA0_GC_ECC_PEND,Interrupt Pending Status for udmass_inta0_gc_ecc_pend" "0,1" line.long 0x10 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_sec_status_reg3,Interrupt Status Register 3" bitfld.long 0x10 1. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_CBASS_INT_VD2GBUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 0. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0xF line.long 0x0 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "UDMAP0_RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "UDMAP0_RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "UDMAP0_RFFW_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rffw_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "UDMAP0_TPCF4_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcf4_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "UDMAP0_TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "UDMAP0_TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "UDMAP0_TSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tstate_ramecc_pend" "0,1" newline bitfld.long 0x0 24. "UDMAP0_RPCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "UDMAP0_RPCU_SB1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcu_sb1_ramecc_pend" "0,1" newline bitfld.long 0x0 22. "UDMAP0_RPCU_SB0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcu_sb0_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "UDMAP0_RPTRCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "UDMAP0_RPTRSB2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x0 19. "UDMAP0_RPTRSB1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "UDMAP0_RPTRSB0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "UDMAP0_TPTRCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 16. "UDMAP0_TPTRSB2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "UDMAP0_TPTRSB1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x0 14. "UDMAP0_TPTRSB0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "UDMAP0_RPBUF_PF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x0 12. "UDMAP0_RPBUF_DF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x0 11. "UDMAP0_RPBUF_CF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "UDMAP0_RPRQ_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rprq_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "UDMAP0_RPCFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcfg_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "UDMAP0_RPSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpstate_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "UDMAP0_TPCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "UDMAP0_TPCU_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcu_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "UDMAP0_TPBUF_PF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "UDMAP0_TPBUF_DF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "UDMAP0_TPBUF_CF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "UDMAP0_TPCFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcfg_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "UDMAP0_TPSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpstate_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 31. "UDMASS_INTA0_MC_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_mc_ecc_pend" "0,1" newline bitfld.long 0x4 30. "UDMASS_INTA0_SR_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_sr_ecc_pend" "0,1" newline bitfld.long 0x4 29. "UDMASS_INTA0_IM_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_im_ecc_pend" "0,1" newline bitfld.long 0x4 28. "NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_j7_udmass_udmass_inta0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 27. "RINGACC0_ECC_ENABLE_SET,Interrupt Enable Set Register for ringacc0_ecc_pend" "0,1" newline bitfld.long 0x4 26. "NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_j7_udmass_ringacc0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 25. "NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_j7_udmass_ringacc0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 24. "NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_j7_udmass_udmap0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_j7_udmass_udmap0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 22. "UDMAP0_RRNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rrngocc_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "UDMAP0_TRNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_trngocc_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "UDMAP0_PSILTID_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_psiltid_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "UDMAP0_PSILR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_psilr_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "UDMAP0_SDEC3_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_sdec3_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "UDMAP0_SDEC0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_sdec0_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "UDMAP0_RDEC2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rdec2_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "UDMAP0_RDEC1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rdec1_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "UDMAP0_RDEC0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rdec0_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "UDMAP0_REVTCNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_revtcntr_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "UDMAP0_TEVTCNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tevtcntr_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "UDMAP0_STS_RAMECC3_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc3_pend" "0,1" newline bitfld.long 0x4 10. "UDMAP0_STS_RAMECC2_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc2_pend" "0,1" newline bitfld.long 0x4 9. "UDMAP0_STS_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc1_pend" "0,1" newline bitfld.long 0x4 8. "UDMAP0_STS_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc0_pend" "0,1" newline bitfld.long 0x4 7. "UDMAP0_EH_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_eh_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "UDMAP0_PROXY_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_proxy_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "UDMAP0_RSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rstate_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "UDMAP0_RFLOW1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rflow1_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "UDMAP0_RFLOW0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rflow0_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "UDMAP0_RPCF4_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf4_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "UDMAP0_RPCF3_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf3_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "UDMAP0_RPCF2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf2_ramecc_pend" "0,1" line.long 0x8 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_sec_enable_set_reg2,Interrupt Enable Set Register 2" bitfld.long 0x8 31. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 30. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 29. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 28. "NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_j7_udmass_psilss0_cfg_navss_mcu_j7_udmass_psilss0_cfg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 27. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 26. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 25. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 24. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 23. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 22. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_j7_udmass_psilss0_l2p_dmsc_evt_navss_mcu_j7_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 20. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_j7_udmass_psilss0_l2p_saul0_psil_navss_mcu_j7_udmass_psilss0_l2p_saul0_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 18. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 17. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 16. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 15. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_j7_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_j7_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_j7_udmass_psilss0_l2p_navss_psil_navss_mcu_j7_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 12. "NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 11. "NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 10. "NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 9. "NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 8. "NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 7. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 6. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 5. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 4. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 3. "NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 2. "NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_SCR_E_GCLK_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 1. "NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_E_GCLK_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 0. "UDMASS_INTA0_GC_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_gc_ecc_pend" "0,1" line.long 0xC "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_sec_enable_set_reg3,Interrupt Enable Set Register 3" bitfld.long 0xC 1. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_CBASS_INT_VD2GBUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 0. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0xF line.long 0x0 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "UDMAP0_RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "UDMAP0_RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "UDMAP0_RFFW_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rffw_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "UDMAP0_TPCF4_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcf4_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "UDMAP0_TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "UDMAP0_TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "UDMAP0_TSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tstate_ramecc_pend" "0,1" newline bitfld.long 0x0 24. "UDMAP0_RPCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "UDMAP0_RPCU_SB1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcu_sb1_ramecc_pend" "0,1" newline bitfld.long 0x0 22. "UDMAP0_RPCU_SB0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcu_sb0_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "UDMAP0_RPTRCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "UDMAP0_RPTRSB2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x0 19. "UDMAP0_RPTRSB1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "UDMAP0_RPTRSB0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "UDMAP0_TPTRCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 16. "UDMAP0_TPTRSB2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "UDMAP0_TPTRSB1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x0 14. "UDMAP0_TPTRSB0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "UDMAP0_RPBUF_PF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x0 12. "UDMAP0_RPBUF_DF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x0 11. "UDMAP0_RPBUF_CF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "UDMAP0_RPRQ_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rprq_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "UDMAP0_RPCFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcfg_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "UDMAP0_RPSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpstate_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "UDMAP0_TPCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "UDMAP0_TPCU_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcu_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "UDMAP0_TPBUF_PF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "UDMAP0_TPBUF_DF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "UDMAP0_TPBUF_CF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "UDMAP0_TPCFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcfg_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "UDMAP0_TPSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpstate_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 31. "UDMASS_INTA0_MC_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_mc_ecc_pend" "0,1" newline bitfld.long 0x4 30. "UDMASS_INTA0_SR_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_sr_ecc_pend" "0,1" newline bitfld.long 0x4 29. "UDMASS_INTA0_IM_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_im_ecc_pend" "0,1" newline bitfld.long 0x4 28. "NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_j7_udmass_udmass_inta0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 27. "RINGACC0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for ringacc0_ecc_pend" "0,1" newline bitfld.long 0x4 26. "NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_j7_udmass_ringacc0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 25. "NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_j7_udmass_ringacc0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 24. "NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_j7_udmass_udmap0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_j7_udmass_udmap0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 22. "UDMAP0_RRNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rrngocc_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "UDMAP0_TRNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_trngocc_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "UDMAP0_PSILTID_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_psiltid_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "UDMAP0_PSILR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_psilr_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "UDMAP0_SDEC3_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sdec3_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "UDMAP0_SDEC0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sdec0_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "UDMAP0_RDEC2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rdec2_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "UDMAP0_RDEC1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rdec1_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "UDMAP0_RDEC0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rdec0_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "UDMAP0_REVTCNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_revtcntr_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "UDMAP0_TEVTCNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tevtcntr_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "UDMAP0_STS_RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc3_pend" "0,1" newline bitfld.long 0x4 10. "UDMAP0_STS_RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc2_pend" "0,1" newline bitfld.long 0x4 9. "UDMAP0_STS_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc1_pend" "0,1" newline bitfld.long 0x4 8. "UDMAP0_STS_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc0_pend" "0,1" newline bitfld.long 0x4 7. "UDMAP0_EH_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_eh_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "UDMAP0_PROXY_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_proxy_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "UDMAP0_RSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rstate_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "UDMAP0_RFLOW1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rflow1_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "UDMAP0_RFLOW0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rflow0_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "UDMAP0_RPCF4_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf4_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "UDMAP0_RPCF3_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf3_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "UDMAP0_RPCF2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf2_ramecc_pend" "0,1" line.long 0x8 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_sec_enable_clr_reg2,Interrupt Enable Clear Register 2" bitfld.long 0x8 31. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 30. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 29. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 28. "NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_j7_udmass_psilss0_cfg_navss_mcu_j7_udmass_psilss0_cfg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 27. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 26. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 25. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 24. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 23. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 22. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_j7_udmass_psilss0_l2p_dmsc_evt_navss_mcu_j7_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 20. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_j7_udmass_psilss0_l2p_saul0_psil_navss_mcu_j7_udmass_psilss0_l2p_saul0_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 18. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 17. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 16. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 15. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_j7_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_j7_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_j7_udmass_psilss0_l2p_navss_psil_navss_mcu_j7_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 12. "NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 11. "NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 10. "NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 9. "NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 8. "NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 7. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 6. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 5. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 4. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 3. "NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 2. "NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_SCR_E_GCLK_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 1. "NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_E_GCLK_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 0. "UDMASS_INTA0_GC_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_gc_ecc_pend" "0,1" line.long 0xC "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_sec_enable_clr_reg3,Interrupt Enable Clear Register 3" bitfld.long 0xC 1. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_CBASS_INT_VD2GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 0. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0x13 line.long 0x0 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "UDMAP0_RPCF1_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 30. "UDMAP0_RPCF0_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x4 29. "UDMAP0_RFFW_RAMECC_PEND,Interrupt Pending Status for udmap0_rffw_ramecc_pend" "0,1" newline bitfld.long 0x4 28. "UDMAP0_TPCF4_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcf4_ramecc_pend" "0,1" newline bitfld.long 0x4 27. "UDMAP0_TPCF1_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "UDMAP0_TPCF0_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x4 25. "UDMAP0_TSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_tstate_ramecc_pend" "0,1" newline bitfld.long 0x4 24. "UDMAP0_RPCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x4 23. "UDMAP0_RPCU_SB1_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcu_sb1_ramecc_pend" "0,1" newline bitfld.long 0x4 22. "UDMAP0_RPCU_SB0_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcu_sb0_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "UDMAP0_RPTRCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "UDMAP0_RPTRSB2_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "UDMAP0_RPTRSB1_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "UDMAP0_RPTRSB0_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "UDMAP0_TPTRCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "UDMAP0_TPTRSB2_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "UDMAP0_TPTRSB1_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "UDMAP0_TPTRSB0_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "UDMAP0_RPBUF_PF_RAMECC_PEND,Interrupt Pending Status for udmap0_rpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "UDMAP0_RPBUF_DF_RAMECC_PEND,Interrupt Pending Status for udmap0_rpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "UDMAP0_RPBUF_CF_RAMECC_PEND,Interrupt Pending Status for udmap0_rpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "UDMAP0_RPRQ_RAMECC_PEND,Interrupt Pending Status for udmap0_rprq_ramecc_pend" "0,1" newline bitfld.long 0x4 9. "UDMAP0_RPCFG_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcfg_ramecc_pend" "0,1" newline bitfld.long 0x4 8. "UDMAP0_RPSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_rpstate_ramecc_pend" "0,1" newline bitfld.long 0x4 7. "UDMAP0_TPCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "UDMAP0_TPCU_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcu_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "UDMAP0_TPBUF_PF_RAMECC_PEND,Interrupt Pending Status for udmap0_tpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "UDMAP0_TPBUF_DF_RAMECC_PEND,Interrupt Pending Status for udmap0_tpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "UDMAP0_TPBUF_CF_RAMECC_PEND,Interrupt Pending Status for udmap0_tpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "UDMAP0_TPCFG_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcfg_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "UDMAP0_TPSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_tpstate_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 31. "UDMASS_INTA0_MC_ECC_PEND,Interrupt Pending Status for udmass_inta0_mc_ecc_pend" "0,1" newline bitfld.long 0x8 30. "UDMASS_INTA0_SR_ECC_PEND,Interrupt Pending Status for udmass_inta0_sr_ecc_pend" "0,1" newline bitfld.long 0x8 29. "UDMASS_INTA0_IM_ECC_PEND,Interrupt Pending Status for udmass_inta0_im_ecc_pend" "0,1" newline bitfld.long 0x8 28. "NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_udmass_inta0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 27. "RINGACC0_ECC_PEND,Interrupt Pending Status for ringacc0_ecc_pend" "0,1" newline bitfld.long 0x8 26. "NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_ringacc0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 25. "NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_ringacc0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 24. "NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_udmap0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_udmap0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 22. "UDMAP0_RRNGOCC_RAMECC_PEND,Interrupt Pending Status for udmap0_rrngocc_ramecc_pend" "0,1" newline bitfld.long 0x8 21. "UDMAP0_TRNGOCC_RAMECC_PEND,Interrupt Pending Status for udmap0_trngocc_ramecc_pend" "0,1" newline bitfld.long 0x8 20. "UDMAP0_PSILTID_RAMECC_PEND,Interrupt Pending Status for udmap0_psiltid_ramecc_pend" "0,1" newline bitfld.long 0x8 19. "UDMAP0_PSILR_RAMECC_PEND,Interrupt Pending Status for udmap0_psilr_ramecc_pend" "0,1" newline bitfld.long 0x8 18. "UDMAP0_SDEC3_RAMECC_PEND,Interrupt Pending Status for udmap0_sdec3_ramecc_pend" "0,1" newline bitfld.long 0x8 17. "UDMAP0_SDEC0_RAMECC_PEND,Interrupt Pending Status for udmap0_sdec0_ramecc_pend" "0,1" newline bitfld.long 0x8 16. "UDMAP0_RDEC2_RAMECC_PEND,Interrupt Pending Status for udmap0_rdec2_ramecc_pend" "0,1" newline bitfld.long 0x8 15. "UDMAP0_RDEC1_RAMECC_PEND,Interrupt Pending Status for udmap0_rdec1_ramecc_pend" "0,1" newline bitfld.long 0x8 14. "UDMAP0_RDEC0_RAMECC_PEND,Interrupt Pending Status for udmap0_rdec0_ramecc_pend" "0,1" newline bitfld.long 0x8 13. "UDMAP0_REVTCNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_revtcntr_ramecc_pend" "0,1" newline bitfld.long 0x8 12. "UDMAP0_TEVTCNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_tevtcntr_ramecc_pend" "0,1" newline bitfld.long 0x8 11. "UDMAP0_STS_RAMECC3_PEND,Interrupt Pending Status for udmap0_sts_ramecc3_pend" "0,1" newline bitfld.long 0x8 10. "UDMAP0_STS_RAMECC2_PEND,Interrupt Pending Status for udmap0_sts_ramecc2_pend" "0,1" newline bitfld.long 0x8 9. "UDMAP0_STS_RAMECC1_PEND,Interrupt Pending Status for udmap0_sts_ramecc1_pend" "0,1" newline bitfld.long 0x8 8. "UDMAP0_STS_RAMECC0_PEND,Interrupt Pending Status for udmap0_sts_ramecc0_pend" "0,1" newline bitfld.long 0x8 7. "UDMAP0_EH_RAMECC_PEND,Interrupt Pending Status for udmap0_eh_ramecc_pend" "0,1" newline bitfld.long 0x8 6. "UDMAP0_PROXY_RAMECC_PEND,Interrupt Pending Status for udmap0_proxy_ramecc_pend" "0,1" newline bitfld.long 0x8 5. "UDMAP0_RSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_rstate_ramecc_pend" "0,1" newline bitfld.long 0x8 4. "UDMAP0_RFLOW1_RAMECC_PEND,Interrupt Pending Status for udmap0_rflow1_ramecc_pend" "0,1" newline bitfld.long 0x8 3. "UDMAP0_RFLOW0_RAMECC_PEND,Interrupt Pending Status for udmap0_rflow0_ramecc_pend" "0,1" newline bitfld.long 0x8 2. "UDMAP0_RPCF4_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf4_ramecc_pend" "0,1" newline bitfld.long 0x8 1. "UDMAP0_RPCF3_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf3_ramecc_pend" "0,1" newline bitfld.long 0x8 0. "UDMAP0_RPCF2_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf2_ramecc_pend" "0,1" line.long 0xC "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_ded_status_reg2,Interrupt Status Register 2" bitfld.long 0xC 31. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 30. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 29. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 28. "NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_psilss0_cfg_navss_mcu_j7_udmass_psilss0_cfg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 27. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 26. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 25. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 24. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 23. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 22. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_psilss0_l2p_dmsc_evt_navss_mcu_j7_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 21. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_psilss0_l2p_udmap0_strm_navss_mcu_j7_udmass_psilss0_l2p_udmap0_strm_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 20. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_psilss0_l2p_saul0_psil_navss_mcu_j7_udmass_psilss0_l2p_saul0_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 19. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_psilss0_l2p_pdma_adc_psil_navss_mcu_j7_udmass_psilss0_l2p_pdma_adc_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 18. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 17. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 16. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 15. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_j7_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 14. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_psilss0_l2p_navss_psil_navss_mcu_j7_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 13. "NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 12. "NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 11. "NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 10. "NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 9. "NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_psilss0_udmap0_strm_safeg_navss_mcu_j7_udmass_psilss0_udmap0_strm_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 8. "NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_psilss0_saul0_psil_safeg_navss_mcu_j7_udmass_psilss0_saul0_psil_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 7. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 6. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 5. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 4. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 3. "NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_j7_udmass_psilss0_cpsw0_psil_safeg_navss_mcu_j7_udmass_psilss0_cpsw0_psil_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 2. "NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_SCR_E_GCLK_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 1. "NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_E_GCLK_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 0. "UDMASS_INTA0_GC_ECC_PEND,Interrupt Pending Status for udmass_inta0_gc_ecc_pend" "0,1" line.long 0x10 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_ded_status_reg3,Interrupt Status Register 3" bitfld.long 0x10 1. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_CBASS_INT_VD2GBUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 0. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0xF line.long 0x0 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "UDMAP0_RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "UDMAP0_RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "UDMAP0_RFFW_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rffw_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "UDMAP0_TPCF4_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcf4_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "UDMAP0_TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "UDMAP0_TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "UDMAP0_TSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tstate_ramecc_pend" "0,1" newline bitfld.long 0x0 24. "UDMAP0_RPCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "UDMAP0_RPCU_SB1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcu_sb1_ramecc_pend" "0,1" newline bitfld.long 0x0 22. "UDMAP0_RPCU_SB0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcu_sb0_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "UDMAP0_RPTRCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "UDMAP0_RPTRSB2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x0 19. "UDMAP0_RPTRSB1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "UDMAP0_RPTRSB0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "UDMAP0_TPTRCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 16. "UDMAP0_TPTRSB2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "UDMAP0_TPTRSB1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x0 14. "UDMAP0_TPTRSB0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "UDMAP0_RPBUF_PF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x0 12. "UDMAP0_RPBUF_DF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x0 11. "UDMAP0_RPBUF_CF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "UDMAP0_RPRQ_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rprq_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "UDMAP0_RPCFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcfg_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "UDMAP0_RPSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpstate_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "UDMAP0_TPCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "UDMAP0_TPCU_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcu_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "UDMAP0_TPBUF_PF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "UDMAP0_TPBUF_DF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "UDMAP0_TPBUF_CF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "UDMAP0_TPCFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcfg_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "UDMAP0_TPSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpstate_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 31. "UDMASS_INTA0_MC_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_mc_ecc_pend" "0,1" newline bitfld.long 0x4 30. "UDMASS_INTA0_SR_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_sr_ecc_pend" "0,1" newline bitfld.long 0x4 29. "UDMASS_INTA0_IM_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_im_ecc_pend" "0,1" newline bitfld.long 0x4 28. "NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_j7_udmass_udmass_inta0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 27. "RINGACC0_ECC_ENABLE_SET,Interrupt Enable Set Register for ringacc0_ecc_pend" "0,1" newline bitfld.long 0x4 26. "NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_j7_udmass_ringacc0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 25. "NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_j7_udmass_ringacc0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 24. "NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_j7_udmass_udmap0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_j7_udmass_udmap0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 22. "UDMAP0_RRNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rrngocc_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "UDMAP0_TRNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_trngocc_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "UDMAP0_PSILTID_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_psiltid_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "UDMAP0_PSILR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_psilr_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "UDMAP0_SDEC3_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_sdec3_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "UDMAP0_SDEC0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_sdec0_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "UDMAP0_RDEC2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rdec2_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "UDMAP0_RDEC1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rdec1_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "UDMAP0_RDEC0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rdec0_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "UDMAP0_REVTCNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_revtcntr_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "UDMAP0_TEVTCNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tevtcntr_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "UDMAP0_STS_RAMECC3_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc3_pend" "0,1" newline bitfld.long 0x4 10. "UDMAP0_STS_RAMECC2_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc2_pend" "0,1" newline bitfld.long 0x4 9. "UDMAP0_STS_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc1_pend" "0,1" newline bitfld.long 0x4 8. "UDMAP0_STS_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc0_pend" "0,1" newline bitfld.long 0x4 7. "UDMAP0_EH_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_eh_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "UDMAP0_PROXY_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_proxy_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "UDMAP0_RSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rstate_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "UDMAP0_RFLOW1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rflow1_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "UDMAP0_RFLOW0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rflow0_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "UDMAP0_RPCF4_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf4_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "UDMAP0_RPCF3_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf3_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "UDMAP0_RPCF2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf2_ramecc_pend" "0,1" line.long 0x8 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_ded_enable_set_reg2,Interrupt Enable Set Register 2" bitfld.long 0x8 31. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 30. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 29. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 28. "NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_j7_udmass_psilss0_cfg_navss_mcu_j7_udmass_psilss0_cfg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 27. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 26. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 25. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 24. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 23. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 22. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_j7_udmass_psilss0_l2p_dmsc_evt_navss_mcu_j7_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 20. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_j7_udmass_psilss0_l2p_saul0_psil_navss_mcu_j7_udmass_psilss0_l2p_saul0_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 18. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 17. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 16. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 15. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_j7_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_j7_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_j7_udmass_psilss0_l2p_navss_psil_navss_mcu_j7_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 12. "NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 11. "NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 10. "NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 9. "NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 8. "NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 7. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 6. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 5. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 4. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 3. "NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 2. "NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_SCR_E_GCLK_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 1. "NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_E_GCLK_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 0. "UDMASS_INTA0_GC_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_gc_ecc_pend" "0,1" line.long 0xC "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_ded_enable_set_reg3,Interrupt Enable Set Register 3" bitfld.long 0xC 1. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_CBASS_INT_VD2GBUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 0. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0xF line.long 0x0 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "UDMAP0_RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "UDMAP0_RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "UDMAP0_RFFW_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rffw_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "UDMAP0_TPCF4_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcf4_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "UDMAP0_TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "UDMAP0_TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "UDMAP0_TSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tstate_ramecc_pend" "0,1" newline bitfld.long 0x0 24. "UDMAP0_RPCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "UDMAP0_RPCU_SB1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcu_sb1_ramecc_pend" "0,1" newline bitfld.long 0x0 22. "UDMAP0_RPCU_SB0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcu_sb0_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "UDMAP0_RPTRCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "UDMAP0_RPTRSB2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x0 19. "UDMAP0_RPTRSB1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "UDMAP0_RPTRSB0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "UDMAP0_TPTRCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 16. "UDMAP0_TPTRSB2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "UDMAP0_TPTRSB1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x0 14. "UDMAP0_TPTRSB0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "UDMAP0_RPBUF_PF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x0 12. "UDMAP0_RPBUF_DF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x0 11. "UDMAP0_RPBUF_CF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "UDMAP0_RPRQ_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rprq_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "UDMAP0_RPCFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcfg_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "UDMAP0_RPSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpstate_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "UDMAP0_TPCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "UDMAP0_TPCU_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcu_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "UDMAP0_TPBUF_PF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "UDMAP0_TPBUF_DF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "UDMAP0_TPBUF_CF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "UDMAP0_TPCFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcfg_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "UDMAP0_TPSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpstate_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 31. "UDMASS_INTA0_MC_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_mc_ecc_pend" "0,1" newline bitfld.long 0x4 30. "UDMASS_INTA0_SR_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_sr_ecc_pend" "0,1" newline bitfld.long 0x4 29. "UDMASS_INTA0_IM_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_im_ecc_pend" "0,1" newline bitfld.long 0x4 28. "NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_j7_udmass_udmass_inta0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 27. "RINGACC0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for ringacc0_ecc_pend" "0,1" newline bitfld.long 0x4 26. "NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_j7_udmass_ringacc0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 25. "NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_j7_udmass_ringacc0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 24. "NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_j7_udmass_udmap0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_j7_udmass_udmap0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 22. "UDMAP0_RRNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rrngocc_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "UDMAP0_TRNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_trngocc_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "UDMAP0_PSILTID_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_psiltid_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "UDMAP0_PSILR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_psilr_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "UDMAP0_SDEC3_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sdec3_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "UDMAP0_SDEC0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sdec0_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "UDMAP0_RDEC2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rdec2_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "UDMAP0_RDEC1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rdec1_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "UDMAP0_RDEC0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rdec0_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "UDMAP0_REVTCNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_revtcntr_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "UDMAP0_TEVTCNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tevtcntr_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "UDMAP0_STS_RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc3_pend" "0,1" newline bitfld.long 0x4 10. "UDMAP0_STS_RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc2_pend" "0,1" newline bitfld.long 0x4 9. "UDMAP0_STS_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc1_pend" "0,1" newline bitfld.long 0x4 8. "UDMAP0_STS_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc0_pend" "0,1" newline bitfld.long 0x4 7. "UDMAP0_EH_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_eh_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "UDMAP0_PROXY_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_proxy_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "UDMAP0_RSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rstate_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "UDMAP0_RFLOW1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rflow1_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "UDMAP0_RFLOW0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rflow0_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "UDMAP0_RPCF4_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf4_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "UDMAP0_RPCF3_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf3_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "UDMAP0_RPCF2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf2_ramecc_pend" "0,1" line.long 0x8 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_ded_enable_clr_reg2,Interrupt Enable Clear Register 2" bitfld.long 0x8 31. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 30. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 29. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 28. "NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_j7_udmass_psilss0_cfg_navss_mcu_j7_udmass_psilss0_cfg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 27. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 26. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 25. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 24. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 23. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 22. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_j7_udmass_psilss0_l2p_dmsc_evt_navss_mcu_j7_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 20. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_j7_udmass_psilss0_l2p_saul0_psil_navss_mcu_j7_udmass_psilss0_l2p_saul0_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 18. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 17. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 16. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 15. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_j7_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_j7_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_j7_udmass_psilss0_l2p_navss_psil_navss_mcu_j7_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 12. "NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 11. "NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 10. "NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 9. "NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 8. "NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 7. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 6. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 5. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 4. "NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 3. "NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 2. "NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_SCR_E_GCLK_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 1. "NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_E_GCLK_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 0. "UDMASS_INTA0_GC_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_gc_ecc_pend" "0,1" line.long 0xC "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_ded_enable_clr_reg3,Interrupt Enable Clear Register 3" bitfld.long 0xC 1. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_CBASS_INT_VD2GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 0. "NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "PAR_UDMASS__UDMASS_ECCAGGR0_CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree.end tree.end tree "MCU_PBIST0 (MCU_PBIST0)" base ad:0x40E00000 rgroup.long 0x0++0x7F line.long 0x0 "MEM_RF0L," hexmask.long 0x0 0.--31. 1. "RF0L,Register Files / Instruction Registers RF0 lower (RF0L)" line.long 0x4 "MEM_RF1L," hexmask.long 0x4 0.--31. 1. "RF1L,Register Files / Instruction Registers RF1 lower (RF1L)" line.long 0x8 "MEM_RF2L," hexmask.long 0x8 0.--31. 1. "RF2L,Register Files / Instruction Registers RF2 lower (RF2L)" line.long 0xC "MEM_RF3L," hexmask.long 0xC 0.--31. 1. "RF3L,Register Files / Instruction Registers RF3 lower (RF3L)" line.long 0x10 "MEM_RF4L," hexmask.long 0x10 0.--31. 1. "RF4L,Register Files / Instruction Registers RF4 lower (RF4L)" line.long 0x14 "MEM_RF5L," hexmask.long 0x14 0.--31. 1. "RF5L,Register Files / Instruction Registers RF5 lower (RF5L)" line.long 0x18 "MEM_RF6L," hexmask.long 0x18 0.--31. 1. "RF6L,Register Files / Instruction Registers RF6 lower (RF6L)" line.long 0x1C "MEM_RF7L," hexmask.long 0x1C 0.--31. 1. "RF7L,Register Files / Instruction Registers RF7 lower (RF7L)" line.long 0x20 "MEM_RF8L," hexmask.long 0x20 0.--31. 1. "RF8L,Register Files / Instruction Registers RF8 lower (RF8L)" line.long 0x24 "MEM_RF9L," hexmask.long 0x24 0.--31. 1. "RF9L,Register Files / Instruction Registers RF9 lower (RF9L)" line.long 0x28 "MEM_RF10L," hexmask.long 0x28 0.--31. 1. "RF10L,Register Files / Instruction Registers RF10 lower (RF10L)" line.long 0x2C "MEM_RF11L," hexmask.long 0x2C 0.--31. 1. "RF11L,Register Files / Instruction Registers RF11 lower (RF11L)" line.long 0x30 "MEM_RF12L," hexmask.long 0x30 0.--31. 1. "RF12L,Register Files / Instruction Registers RF12 lower (RF12L)" line.long 0x34 "MEM_RF13L," hexmask.long 0x34 0.--31. 1. "RF13L,Register Files / Instruction Registers RF13 lower (RF13L)" line.long 0x38 "MEM_RF14L," hexmask.long 0x38 0.--31. 1. "RF14L,Register Files / Instruction Registers RF14 lower (RF14L)" line.long 0x3C "MEM_RF15L," hexmask.long 0x3C 0.--31. 1. "RF15L,Register Files / Instruction Registers RF15 lower (RF15L)" line.long 0x40 "MEM_RF0U," hexmask.long 0x40 0.--31. 1. "RF0U,Register Files / Instruction Registers RF0 upper (RF0U)" line.long 0x44 "MEM_RF1U," hexmask.long 0x44 0.--31. 1. "RF1U,Register Files / Instruction Registers RF1 upper (RF1U)" line.long 0x48 "MEM_RF2U," hexmask.long 0x48 0.--31. 1. "RF2U,Register Files / Instruction Registers RF2 upper (RF2U)" line.long 0x4C "MEM_RF3U," hexmask.long 0x4C 0.--31. 1. "RF3U,Register Files / Instruction Registers RF3 upper (RF3U)" line.long 0x50 "MEM_RF4U," hexmask.long 0x50 0.--31. 1. "RF4U,Register Files / Instruction Registers RF4 upper (RF4U)" line.long 0x54 "MEM_RF5U," hexmask.long 0x54 0.--31. 1. "RF5U,Register Files / Instruction Registers RF5 upper (RF5U)" line.long 0x58 "MEM_RF6U," hexmask.long 0x58 0.--31. 1. "RF6U,Register Files / Instruction Registers RF6 upper (RF6U)" line.long 0x5C "MEM_RF7U," hexmask.long 0x5C 0.--31. 1. "RF7U,Register Files / Instruction Registers RF7 upper (RF7U)" line.long 0x60 "MEM_RF8U," hexmask.long 0x60 0.--31. 1. "RF8U,Register Files / Instruction Registers RF8 upper (RF8U)" line.long 0x64 "MEM_RF9U," hexmask.long 0x64 0.--31. 1. "RF9U,Register Files / Instruction Registers RF9 upper (RF9U)" line.long 0x68 "MEM_RF10U," hexmask.long 0x68 0.--31. 1. "RF10U,Register Files / Instruction Registers RF10 upper (RF10U)" line.long 0x6C "MEM_RF11U," hexmask.long 0x6C 0.--31. 1. "RF11U,Register Files / Instruction Registers RF11 upper (RF11U)" line.long 0x70 "MEM_RF12U," hexmask.long 0x70 0.--31. 1. "RF12U,Register Files / Instruction Registers RF12 upper (RF12U)" line.long 0x74 "MEM_RF13U," hexmask.long 0x74 0.--31. 1. "RF13U,Register Files / Instruction Registers RF13 upper (RF13U)" line.long 0x78 "MEM_RF14U," hexmask.long 0x78 0.--31. 1. "RF14U,Register Files / Instruction Registers RF14 upper (RF14U)" line.long 0x7C "MEM_RF15U," hexmask.long 0x7C 0.--31. 1. "RF15U,Register Files / Instruction Registers RF15 upper (RF15U)" rgroup.long 0x100++0x27 line.long 0x0 "MEM_A0," hexmask.long.word 0x0 0.--15. 1. "A0,Variable Address Register 0 (A0)" line.long 0x4 "MEM_A1," hexmask.long.word 0x4 0.--15. 1. "A1,Variable Address Register 1 (A1)" line.long 0x8 "MEM_A2," hexmask.long.word 0x8 0.--15. 1. "A2,Variable Address Register 2 (A2)" line.long 0xC "MEM_A3," hexmask.long.word 0xC 0.--15. 1. "A3,Variable Address Register 3 (A3)" line.long 0x10 "MEM_L0," hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 (L0)" line.long 0x14 "MEM_L1," hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 (L1)" line.long 0x18 "MEM_L2," hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 (L2)" line.long 0x1C "MEM_L3," hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 (L3)" line.long 0x20 "MEM_D," hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 (D1)" hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 (D0)" line.long 0x24 "MEM_E," hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 (E1)" hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 (E0)" rgroup.long 0x130++0x3F line.long 0x0 "MEM_CA0," hexmask.long.word 0x0 0.--15. 1. "CA0,Constant Address Register 0 (CA0)" line.long 0x4 "MEM_CA1," hexmask.long.word 0x4 0.--15. 1. "CA1,Constant Address Register 1 (CA1)" line.long 0x8 "MEM_CA2," hexmask.long.word 0x8 0.--15. 1. "CA2,Constant Address Register 2 (CA2)" line.long 0xC "MEM_CA3," hexmask.long.word 0xC 0.--15. 1. "CA3,Constant Address Register 3 (CA3)" line.long 0x10 "MEM_CL0," hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 (CL0)" line.long 0x14 "MEM_CL1," hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 (CL1)" line.long 0x18 "MEM_CL2," hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 (CL2)" line.long 0x1C "MEM_CL3," hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 (CL3)" line.long 0x20 "MEM_I0," hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 (I0)" line.long 0x24 "MEM_I1," hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 (I1)" line.long 0x28 "MEM_I2," hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 (I2)" line.long 0x2C "MEM_I3," hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 (I3)" line.long 0x30 "MEM_RAMT," hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS" hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS" hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR" hexmask.long.byte 0x30 2.--5. 1. "PLS,Pipeline Latency Select" bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3" line.long 0x34 "MEM_DLR," hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 (BRP)" bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1" bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1" bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode (mainly for ROM testing)" "0,1" bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1" newline bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1" bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1" bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1" bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1" bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1" newline bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1" bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1" line.long 0x38 "MEM_CMS," hexmask.long.byte 0x38 0.--3. 1. "CMS,Clock Mux Select (CMS)" line.long 0x3C "MEM_STR," bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1" bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1" bitfld.long 0x3C 2. "STOP,Stop" "0,1" bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1" bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1" rgroup.quad 0x170++0x7 line.quad 0x0 "MEM_SCR," hexmask.quad.byte 0x0 56.--63. 1. "SCR7,Address Scrambling Register 7" hexmask.quad.byte 0x0 48.--55. 1. "SCR6,Address Scrambling Register 6" hexmask.quad.byte 0x0 40.--47. 1. "SCR5,Address Scrambling Register 5" hexmask.quad.byte 0x0 32.--39. 1. "SCR4,Address Scrambling Register 4" hexmask.quad.byte 0x0 24.--31. 1. "SCR3,Address Scrambling Register 3" newline hexmask.quad.byte 0x0 16.--23. 1. "SCR2,Address Scrambling Register 2" hexmask.quad.byte 0x0 8.--15. 1. "SCR1,Address Scrambling Register 1" hexmask.quad.byte 0x0 0.--7. 1. "SCR0,Address Scrambling Register 0" rgroup.long 0x178++0x13 line.long 0x0 "MEM_CSR," hexmask.long.byte 0x0 24.--31. 1. "CSR3,Chip Select 3 (CSR3)" hexmask.long.byte 0x0 16.--23. 1. "CSR2,Chip Select 2 (CSR2)" hexmask.long.byte 0x0 8.--15. 1. "CSR1,Chip Select 1(CSR1)" hexmask.long.byte 0x0 0.--7. 1. "CSR0,Chip Select 0 (CSR0)" line.long 0x4 "MEM_FDLY," hexmask.long.byte 0x4 0.--7. 1. "FDLY,Fail Delay (FDLY)" line.long 0x8 "MEM_PACT," bitfld.long 0x8 0. "PACT,PBIST Activate (PACT)" "0,1" line.long 0xC "MEM_PID," hexmask.long.byte 0xC 0.--4. 1. "PID,PBIST ID" line.long 0x10 "MEM_OVER," bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1" bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1" bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1" bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1" rgroup.quad 0x190++0x17 line.quad 0x0 "MEM_FSRF," bitfld.quad 0x0 32. "FRSF1,Fail Status Fail - Port 1 (FSRF1)" "0,1" bitfld.quad 0x0 0. "FRSF0,Fail Status Fail - Port 0 (FSRF0)" "0,1" line.quad 0x8 "MEM_FSRC," hexmask.quad.byte 0x8 32.--35. 1. "FSRC1,Fail Status Count - Port 1 (FSRC1)" hexmask.quad.byte 0x8 0.--3. 1. "FSRC0,Fail Status Count - Port 0 (FSRC0)" line.quad 0x10 "MEM_FSRA," hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 (FSRA1)" hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 (FSRA0)" rgroup.long 0x1A8++0x3 line.long 0x0 "MEM_FSRDL0," hexmask.long 0x0 0.--31. 1. "FSRDL0,Fail Status Data - Port 0 (FSRDL0)" rgroup.long 0x1B0++0xF line.long 0x0 "MEM_FSRDL1," hexmask.long 0x0 0.--31. 1. "FSRDL1,Fail Status Data - Port 1 (FSRDL1)" line.long 0x4 "MEM_MARGIN_MODE," bitfld.long 0x4 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3" bitfld.long 0x4 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3" line.long 0x8 "MEM_WRENZ," bitfld.long 0x8 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3" line.long 0xC "MEM_PAGE_PGS," bitfld.long 0xC 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3" rgroup.long 0x1C0++0x7 line.long 0x0 "MEM_ROM," bitfld.long 0x0 0.--1. "ROM,ROM Mask (ROM)" "0,1,2,3" line.long 0x4 "MEM_ALGO," hexmask.long.byte 0x4 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 (ALGO 3)" hexmask.long.byte 0x4 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 (ALGO 2)" hexmask.long.byte 0x4 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 (ALGO 1)" hexmask.long.byte 0x4 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 (ALGO 0)" rgroup.quad 0x1C8++0x7 line.quad 0x0 "MEM_RINFO," hexmask.quad.byte 0x0 56.--63. 1. "U3,RAM Info Mask Upper 3 (RINFOU3)" hexmask.quad.byte 0x0 48.--55. 1. "U2,RAM Info Mask Upper 2 (RINFOU2)" hexmask.quad.byte 0x0 40.--47. 1. "U1,RAM Info Mask Upper 1 (RINFOU1)" hexmask.quad.byte 0x0 32.--39. 1. "U0,RAM Info Mask Upper 0 (RINFOU0)" hexmask.quad.byte 0x0 24.--31. 1. "L3,RAM Info Mask Lower 3 (RINFOL3)" newline hexmask.quad.byte 0x0 16.--23. 1. "L2,RAM Info Mask Lower 2 (RINFOL2)" hexmask.quad.byte 0x0 8.--15. 1. "L1,RAM Info Mask Lower 1 (RINFOL1)" hexmask.quad.byte 0x0 0.--7. 1. "L0,RAM Info Mask Lower 0 (RINFOL0)" tree.end tree "MCU_PBIST1 (MCU_PBIST1)" base ad:0x40E20000 rgroup.long 0x0++0x7F line.long 0x0 "MEM_RF0L," hexmask.long 0x0 0.--31. 1. "RF0L,Register Files / Instruction Registers RF0 lower (RF0L)" line.long 0x4 "MEM_RF1L," hexmask.long 0x4 0.--31. 1. "RF1L,Register Files / Instruction Registers RF1 lower (RF1L)" line.long 0x8 "MEM_RF2L," hexmask.long 0x8 0.--31. 1. "RF2L,Register Files / Instruction Registers RF2 lower (RF2L)" line.long 0xC "MEM_RF3L," hexmask.long 0xC 0.--31. 1. "RF3L,Register Files / Instruction Registers RF3 lower (RF3L)" line.long 0x10 "MEM_RF4L," hexmask.long 0x10 0.--31. 1. "RF4L,Register Files / Instruction Registers RF4 lower (RF4L)" line.long 0x14 "MEM_RF5L," hexmask.long 0x14 0.--31. 1. "RF5L,Register Files / Instruction Registers RF5 lower (RF5L)" line.long 0x18 "MEM_RF6L," hexmask.long 0x18 0.--31. 1. "RF6L,Register Files / Instruction Registers RF6 lower (RF6L)" line.long 0x1C "MEM_RF7L," hexmask.long 0x1C 0.--31. 1. "RF7L,Register Files / Instruction Registers RF7 lower (RF7L)" line.long 0x20 "MEM_RF8L," hexmask.long 0x20 0.--31. 1. "RF8L,Register Files / Instruction Registers RF8 lower (RF8L)" line.long 0x24 "MEM_RF9L," hexmask.long 0x24 0.--31. 1. "RF9L,Register Files / Instruction Registers RF9 lower (RF9L)" line.long 0x28 "MEM_RF10L," hexmask.long 0x28 0.--31. 1. "RF10L,Register Files / Instruction Registers RF10 lower (RF10L)" line.long 0x2C "MEM_RF11L," hexmask.long 0x2C 0.--31. 1. "RF11L,Register Files / Instruction Registers RF11 lower (RF11L)" line.long 0x30 "MEM_RF12L," hexmask.long 0x30 0.--31. 1. "RF12L,Register Files / Instruction Registers RF12 lower (RF12L)" line.long 0x34 "MEM_RF13L," hexmask.long 0x34 0.--31. 1. "RF13L,Register Files / Instruction Registers RF13 lower (RF13L)" line.long 0x38 "MEM_RF14L," hexmask.long 0x38 0.--31. 1. "RF14L,Register Files / Instruction Registers RF14 lower (RF14L)" line.long 0x3C "MEM_RF15L," hexmask.long 0x3C 0.--31. 1. "RF15L,Register Files / Instruction Registers RF15 lower (RF15L)" line.long 0x40 "MEM_RF0U," hexmask.long 0x40 0.--31. 1. "RF0U,Register Files / Instruction Registers RF0 upper (RF0U)" line.long 0x44 "MEM_RF1U," hexmask.long 0x44 0.--31. 1. "RF1U,Register Files / Instruction Registers RF1 upper (RF1U)" line.long 0x48 "MEM_RF2U," hexmask.long 0x48 0.--31. 1. "RF2U,Register Files / Instruction Registers RF2 upper (RF2U)" line.long 0x4C "MEM_RF3U," hexmask.long 0x4C 0.--31. 1. "RF3U,Register Files / Instruction Registers RF3 upper (RF3U)" line.long 0x50 "MEM_RF4U," hexmask.long 0x50 0.--31. 1. "RF4U,Register Files / Instruction Registers RF4 upper (RF4U)" line.long 0x54 "MEM_RF5U," hexmask.long 0x54 0.--31. 1. "RF5U,Register Files / Instruction Registers RF5 upper (RF5U)" line.long 0x58 "MEM_RF6U," hexmask.long 0x58 0.--31. 1. "RF6U,Register Files / Instruction Registers RF6 upper (RF6U)" line.long 0x5C "MEM_RF7U," hexmask.long 0x5C 0.--31. 1. "RF7U,Register Files / Instruction Registers RF7 upper (RF7U)" line.long 0x60 "MEM_RF8U," hexmask.long 0x60 0.--31. 1. "RF8U,Register Files / Instruction Registers RF8 upper (RF8U)" line.long 0x64 "MEM_RF9U," hexmask.long 0x64 0.--31. 1. "RF9U,Register Files / Instruction Registers RF9 upper (RF9U)" line.long 0x68 "MEM_RF10U," hexmask.long 0x68 0.--31. 1. "RF10U,Register Files / Instruction Registers RF10 upper (RF10U)" line.long 0x6C "MEM_RF11U," hexmask.long 0x6C 0.--31. 1. "RF11U,Register Files / Instruction Registers RF11 upper (RF11U)" line.long 0x70 "MEM_RF12U," hexmask.long 0x70 0.--31. 1. "RF12U,Register Files / Instruction Registers RF12 upper (RF12U)" line.long 0x74 "MEM_RF13U," hexmask.long 0x74 0.--31. 1. "RF13U,Register Files / Instruction Registers RF13 upper (RF13U)" line.long 0x78 "MEM_RF14U," hexmask.long 0x78 0.--31. 1. "RF14U,Register Files / Instruction Registers RF14 upper (RF14U)" line.long 0x7C "MEM_RF15U," hexmask.long 0x7C 0.--31. 1. "RF15U,Register Files / Instruction Registers RF15 upper (RF15U)" rgroup.long 0x100++0x27 line.long 0x0 "MEM_A0," hexmask.long.word 0x0 0.--15. 1. "A0,Variable Address Register 0 (A0)" line.long 0x4 "MEM_A1," hexmask.long.word 0x4 0.--15. 1. "A1,Variable Address Register 1 (A1)" line.long 0x8 "MEM_A2," hexmask.long.word 0x8 0.--15. 1. "A2,Variable Address Register 2 (A2)" line.long 0xC "MEM_A3," hexmask.long.word 0xC 0.--15. 1. "A3,Variable Address Register 3 (A3)" line.long 0x10 "MEM_L0," hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 (L0)" line.long 0x14 "MEM_L1," hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 (L1)" line.long 0x18 "MEM_L2," hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 (L2)" line.long 0x1C "MEM_L3," hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 (L3)" line.long 0x20 "MEM_D," hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 (D1)" hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 (D0)" line.long 0x24 "MEM_E," hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 (E1)" hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 (E0)" rgroup.long 0x130++0x3F line.long 0x0 "MEM_CA0," hexmask.long.word 0x0 0.--15. 1. "CA0,Constant Address Register 0 (CA0)" line.long 0x4 "MEM_CA1," hexmask.long.word 0x4 0.--15. 1. "CA1,Constant Address Register 1 (CA1)" line.long 0x8 "MEM_CA2," hexmask.long.word 0x8 0.--15. 1. "CA2,Constant Address Register 2 (CA2)" line.long 0xC "MEM_CA3," hexmask.long.word 0xC 0.--15. 1. "CA3,Constant Address Register 3 (CA3)" line.long 0x10 "MEM_CL0," hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 (CL0)" line.long 0x14 "MEM_CL1," hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 (CL1)" line.long 0x18 "MEM_CL2," hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 (CL2)" line.long 0x1C "MEM_CL3," hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 (CL3)" line.long 0x20 "MEM_I0," hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 (I0)" line.long 0x24 "MEM_I1," hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 (I1)" line.long 0x28 "MEM_I2," hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 (I2)" line.long 0x2C "MEM_I3," hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 (I3)" line.long 0x30 "MEM_RAMT," hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS" hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS" hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR" hexmask.long.byte 0x30 2.--5. 1. "PLS,Pipeline Latency Select" bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3" line.long 0x34 "MEM_DLR," hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 (BRP)" bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1" bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1" bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode (mainly for ROM testing)" "0,1" bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1" newline bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1" bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1" bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1" bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1" bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1" newline bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1" bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1" line.long 0x38 "MEM_CMS," hexmask.long.byte 0x38 0.--3. 1. "CMS,Clock Mux Select (CMS)" line.long 0x3C "MEM_STR," bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1" bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1" bitfld.long 0x3C 2. "STOP,Stop" "0,1" bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1" bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1" rgroup.quad 0x170++0x7 line.quad 0x0 "MEM_SCR," hexmask.quad.byte 0x0 56.--63. 1. "SCR7,Address Scrambling Register 7" hexmask.quad.byte 0x0 48.--55. 1. "SCR6,Address Scrambling Register 6" hexmask.quad.byte 0x0 40.--47. 1. "SCR5,Address Scrambling Register 5" hexmask.quad.byte 0x0 32.--39. 1. "SCR4,Address Scrambling Register 4" hexmask.quad.byte 0x0 24.--31. 1. "SCR3,Address Scrambling Register 3" newline hexmask.quad.byte 0x0 16.--23. 1. "SCR2,Address Scrambling Register 2" hexmask.quad.byte 0x0 8.--15. 1. "SCR1,Address Scrambling Register 1" hexmask.quad.byte 0x0 0.--7. 1. "SCR0,Address Scrambling Register 0" rgroup.long 0x178++0x13 line.long 0x0 "MEM_CSR," hexmask.long.byte 0x0 24.--31. 1. "CSR3,Chip Select 3 (CSR3)" hexmask.long.byte 0x0 16.--23. 1. "CSR2,Chip Select 2 (CSR2)" hexmask.long.byte 0x0 8.--15. 1. "CSR1,Chip Select 1(CSR1)" hexmask.long.byte 0x0 0.--7. 1. "CSR0,Chip Select 0 (CSR0)" line.long 0x4 "MEM_FDLY," hexmask.long.byte 0x4 0.--7. 1. "FDLY,Fail Delay (FDLY)" line.long 0x8 "MEM_PACT," bitfld.long 0x8 0. "PACT,PBIST Activate (PACT)" "0,1" line.long 0xC "MEM_PID," hexmask.long.byte 0xC 0.--4. 1. "PID,PBIST ID" line.long 0x10 "MEM_OVER," bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1" bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1" bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1" bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1" rgroup.quad 0x190++0x17 line.quad 0x0 "MEM_FSRF," bitfld.quad 0x0 32. "FRSF1,Fail Status Fail - Port 1 (FSRF1)" "0,1" bitfld.quad 0x0 0. "FRSF0,Fail Status Fail - Port 0 (FSRF0)" "0,1" line.quad 0x8 "MEM_FSRC," hexmask.quad.byte 0x8 32.--35. 1. "FSRC1,Fail Status Count - Port 1 (FSRC1)" hexmask.quad.byte 0x8 0.--3. 1. "FSRC0,Fail Status Count - Port 0 (FSRC0)" line.quad 0x10 "MEM_FSRA," hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 (FSRA1)" hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 (FSRA0)" rgroup.long 0x1A8++0x3 line.long 0x0 "MEM_FSRDL0," hexmask.long 0x0 0.--31. 1. "FSRDL0,Fail Status Data - Port 0 (FSRDL0)" rgroup.long 0x1B0++0xF line.long 0x0 "MEM_FSRDL1," hexmask.long 0x0 0.--31. 1. "FSRDL1,Fail Status Data - Port 1 (FSRDL1)" line.long 0x4 "MEM_MARGIN_MODE," bitfld.long 0x4 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3" bitfld.long 0x4 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3" line.long 0x8 "MEM_WRENZ," bitfld.long 0x8 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3" line.long 0xC "MEM_PAGE_PGS," bitfld.long 0xC 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3" rgroup.long 0x1C0++0x7 line.long 0x0 "MEM_ROM," bitfld.long 0x0 0.--1. "ROM,ROM Mask (ROM)" "0,1,2,3" line.long 0x4 "MEM_ALGO," hexmask.long.byte 0x4 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 (ALGO 3)" hexmask.long.byte 0x4 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 (ALGO 2)" hexmask.long.byte 0x4 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 (ALGO 1)" hexmask.long.byte 0x4 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 (ALGO 0)" rgroup.quad 0x1C8++0x7 line.quad 0x0 "MEM_RINFO," hexmask.quad.byte 0x0 56.--63. 1. "U3,RAM Info Mask Upper 3 (RINFOU3)" hexmask.quad.byte 0x0 48.--55. 1. "U2,RAM Info Mask Upper 2 (RINFOU2)" hexmask.quad.byte 0x0 40.--47. 1. "U1,RAM Info Mask Upper 1 (RINFOU1)" hexmask.quad.byte 0x0 32.--39. 1. "U0,RAM Info Mask Upper 0 (RINFOU0)" hexmask.quad.byte 0x0 24.--31. 1. "L3,RAM Info Mask Lower 3 (RINFOL3)" newline hexmask.quad.byte 0x0 16.--23. 1. "L2,RAM Info Mask Lower 2 (RINFOL2)" hexmask.quad.byte 0x0 8.--15. 1. "L1,RAM Info Mask Lower 1 (RINFOL1)" hexmask.quad.byte 0x0 0.--7. 1. "L0,RAM Info Mask Lower 0 (RINFOL0)" tree.end tree "MCU_PBIST2 (MCU_PBIST2)" base ad:0x40E10000 rgroup.long 0x0++0x7F line.long 0x0 "MEM_RF0L," hexmask.long 0x0 0.--31. 1. "RF0L,Register Files / Instruction Registers RF0 lower (RF0L)" line.long 0x4 "MEM_RF1L," hexmask.long 0x4 0.--31. 1. "RF1L,Register Files / Instruction Registers RF1 lower (RF1L)" line.long 0x8 "MEM_RF2L," hexmask.long 0x8 0.--31. 1. "RF2L,Register Files / Instruction Registers RF2 lower (RF2L)" line.long 0xC "MEM_RF3L," hexmask.long 0xC 0.--31. 1. "RF3L,Register Files / Instruction Registers RF3 lower (RF3L)" line.long 0x10 "MEM_RF4L," hexmask.long 0x10 0.--31. 1. "RF4L,Register Files / Instruction Registers RF4 lower (RF4L)" line.long 0x14 "MEM_RF5L," hexmask.long 0x14 0.--31. 1. "RF5L,Register Files / Instruction Registers RF5 lower (RF5L)" line.long 0x18 "MEM_RF6L," hexmask.long 0x18 0.--31. 1. "RF6L,Register Files / Instruction Registers RF6 lower (RF6L)" line.long 0x1C "MEM_RF7L," hexmask.long 0x1C 0.--31. 1. "RF7L,Register Files / Instruction Registers RF7 lower (RF7L)" line.long 0x20 "MEM_RF8L," hexmask.long 0x20 0.--31. 1. "RF8L,Register Files / Instruction Registers RF8 lower (RF8L)" line.long 0x24 "MEM_RF9L," hexmask.long 0x24 0.--31. 1. "RF9L,Register Files / Instruction Registers RF9 lower (RF9L)" line.long 0x28 "MEM_RF10L," hexmask.long 0x28 0.--31. 1. "RF10L,Register Files / Instruction Registers RF10 lower (RF10L)" line.long 0x2C "MEM_RF11L," hexmask.long 0x2C 0.--31. 1. "RF11L,Register Files / Instruction Registers RF11 lower (RF11L)" line.long 0x30 "MEM_RF12L," hexmask.long 0x30 0.--31. 1. "RF12L,Register Files / Instruction Registers RF12 lower (RF12L)" line.long 0x34 "MEM_RF13L," hexmask.long 0x34 0.--31. 1. "RF13L,Register Files / Instruction Registers RF13 lower (RF13L)" line.long 0x38 "MEM_RF14L," hexmask.long 0x38 0.--31. 1. "RF14L,Register Files / Instruction Registers RF14 lower (RF14L)" line.long 0x3C "MEM_RF15L," hexmask.long 0x3C 0.--31. 1. "RF15L,Register Files / Instruction Registers RF15 lower (RF15L)" line.long 0x40 "MEM_RF0U," hexmask.long 0x40 0.--31. 1. "RF0U,Register Files / Instruction Registers RF0 upper (RF0U)" line.long 0x44 "MEM_RF1U," hexmask.long 0x44 0.--31. 1. "RF1U,Register Files / Instruction Registers RF1 upper (RF1U)" line.long 0x48 "MEM_RF2U," hexmask.long 0x48 0.--31. 1. "RF2U,Register Files / Instruction Registers RF2 upper (RF2U)" line.long 0x4C "MEM_RF3U," hexmask.long 0x4C 0.--31. 1. "RF3U,Register Files / Instruction Registers RF3 upper (RF3U)" line.long 0x50 "MEM_RF4U," hexmask.long 0x50 0.--31. 1. "RF4U,Register Files / Instruction Registers RF4 upper (RF4U)" line.long 0x54 "MEM_RF5U," hexmask.long 0x54 0.--31. 1. "RF5U,Register Files / Instruction Registers RF5 upper (RF5U)" line.long 0x58 "MEM_RF6U," hexmask.long 0x58 0.--31. 1. "RF6U,Register Files / Instruction Registers RF6 upper (RF6U)" line.long 0x5C "MEM_RF7U," hexmask.long 0x5C 0.--31. 1. "RF7U,Register Files / Instruction Registers RF7 upper (RF7U)" line.long 0x60 "MEM_RF8U," hexmask.long 0x60 0.--31. 1. "RF8U,Register Files / Instruction Registers RF8 upper (RF8U)" line.long 0x64 "MEM_RF9U," hexmask.long 0x64 0.--31. 1. "RF9U,Register Files / Instruction Registers RF9 upper (RF9U)" line.long 0x68 "MEM_RF10U," hexmask.long 0x68 0.--31. 1. "RF10U,Register Files / Instruction Registers RF10 upper (RF10U)" line.long 0x6C "MEM_RF11U," hexmask.long 0x6C 0.--31. 1. "RF11U,Register Files / Instruction Registers RF11 upper (RF11U)" line.long 0x70 "MEM_RF12U," hexmask.long 0x70 0.--31. 1. "RF12U,Register Files / Instruction Registers RF12 upper (RF12U)" line.long 0x74 "MEM_RF13U," hexmask.long 0x74 0.--31. 1. "RF13U,Register Files / Instruction Registers RF13 upper (RF13U)" line.long 0x78 "MEM_RF14U," hexmask.long 0x78 0.--31. 1. "RF14U,Register Files / Instruction Registers RF14 upper (RF14U)" line.long 0x7C "MEM_RF15U," hexmask.long 0x7C 0.--31. 1. "RF15U,Register Files / Instruction Registers RF15 upper (RF15U)" rgroup.long 0x100++0x27 line.long 0x0 "MEM_A0," hexmask.long.word 0x0 0.--15. 1. "A0,Variable Address Register 0 (A0)" line.long 0x4 "MEM_A1," hexmask.long.word 0x4 0.--15. 1. "A1,Variable Address Register 1 (A1)" line.long 0x8 "MEM_A2," hexmask.long.word 0x8 0.--15. 1. "A2,Variable Address Register 2 (A2)" line.long 0xC "MEM_A3," hexmask.long.word 0xC 0.--15. 1. "A3,Variable Address Register 3 (A3)" line.long 0x10 "MEM_L0," hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 (L0)" line.long 0x14 "MEM_L1," hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 (L1)" line.long 0x18 "MEM_L2," hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 (L2)" line.long 0x1C "MEM_L3," hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 (L3)" line.long 0x20 "MEM_D," hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 (D1)" hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 (D0)" line.long 0x24 "MEM_E," hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 (E1)" hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 (E0)" rgroup.long 0x130++0x3F line.long 0x0 "MEM_CA0," hexmask.long.word 0x0 0.--15. 1. "CA0,Constant Address Register 0 (CA0)" line.long 0x4 "MEM_CA1," hexmask.long.word 0x4 0.--15. 1. "CA1,Constant Address Register 1 (CA1)" line.long 0x8 "MEM_CA2," hexmask.long.word 0x8 0.--15. 1. "CA2,Constant Address Register 2 (CA2)" line.long 0xC "MEM_CA3," hexmask.long.word 0xC 0.--15. 1. "CA3,Constant Address Register 3 (CA3)" line.long 0x10 "MEM_CL0," hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 (CL0)" line.long 0x14 "MEM_CL1," hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 (CL1)" line.long 0x18 "MEM_CL2," hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 (CL2)" line.long 0x1C "MEM_CL3," hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 (CL3)" line.long 0x20 "MEM_I0," hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 (I0)" line.long 0x24 "MEM_I1," hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 (I1)" line.long 0x28 "MEM_I2," hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 (I2)" line.long 0x2C "MEM_I3," hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 (I3)" line.long 0x30 "MEM_RAMT," hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS" hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS" hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR" hexmask.long.byte 0x30 2.--5. 1. "PLS,Pipeline Latency Select" bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3" line.long 0x34 "MEM_DLR," hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 (BRP)" bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1" bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1" bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode (mainly for ROM testing)" "0,1" bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1" newline bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1" bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1" bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1" bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1" bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1" newline bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1" bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1" line.long 0x38 "MEM_CMS," hexmask.long.byte 0x38 0.--3. 1. "CMS,Clock Mux Select (CMS)" line.long 0x3C "MEM_STR," bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1" bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1" bitfld.long 0x3C 2. "STOP,Stop" "0,1" bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1" bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1" rgroup.quad 0x170++0x7 line.quad 0x0 "MEM_SCR," hexmask.quad.byte 0x0 56.--63. 1. "SCR7,Address Scrambling Register 7" hexmask.quad.byte 0x0 48.--55. 1. "SCR6,Address Scrambling Register 6" hexmask.quad.byte 0x0 40.--47. 1. "SCR5,Address Scrambling Register 5" hexmask.quad.byte 0x0 32.--39. 1. "SCR4,Address Scrambling Register 4" hexmask.quad.byte 0x0 24.--31. 1. "SCR3,Address Scrambling Register 3" newline hexmask.quad.byte 0x0 16.--23. 1. "SCR2,Address Scrambling Register 2" hexmask.quad.byte 0x0 8.--15. 1. "SCR1,Address Scrambling Register 1" hexmask.quad.byte 0x0 0.--7. 1. "SCR0,Address Scrambling Register 0" rgroup.long 0x178++0x13 line.long 0x0 "MEM_CSR," hexmask.long.byte 0x0 24.--31. 1. "CSR3,Chip Select 3 (CSR3)" hexmask.long.byte 0x0 16.--23. 1. "CSR2,Chip Select 2 (CSR2)" hexmask.long.byte 0x0 8.--15. 1. "CSR1,Chip Select 1(CSR1)" hexmask.long.byte 0x0 0.--7. 1. "CSR0,Chip Select 0 (CSR0)" line.long 0x4 "MEM_FDLY," hexmask.long.byte 0x4 0.--7. 1. "FDLY,Fail Delay (FDLY)" line.long 0x8 "MEM_PACT," bitfld.long 0x8 0. "PACT,PBIST Activate (PACT)" "0,1" line.long 0xC "MEM_PID," hexmask.long.byte 0xC 0.--4. 1. "PID,PBIST ID" line.long 0x10 "MEM_OVER," bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1" bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1" bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1" bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1" rgroup.quad 0x190++0x17 line.quad 0x0 "MEM_FSRF," bitfld.quad 0x0 32. "FRSF1,Fail Status Fail - Port 1 (FSRF1)" "0,1" bitfld.quad 0x0 0. "FRSF0,Fail Status Fail - Port 0 (FSRF0)" "0,1" line.quad 0x8 "MEM_FSRC," hexmask.quad.byte 0x8 32.--35. 1. "FSRC1,Fail Status Count - Port 1 (FSRC1)" hexmask.quad.byte 0x8 0.--3. 1. "FSRC0,Fail Status Count - Port 0 (FSRC0)" line.quad 0x10 "MEM_FSRA," hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 (FSRA1)" hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 (FSRA0)" rgroup.long 0x1A8++0x3 line.long 0x0 "MEM_FSRDL0," hexmask.long 0x0 0.--31. 1. "FSRDL0,Fail Status Data - Port 0 (FSRDL0)" rgroup.long 0x1B0++0xF line.long 0x0 "MEM_FSRDL1," hexmask.long 0x0 0.--31. 1. "FSRDL1,Fail Status Data - Port 1 (FSRDL1)" line.long 0x4 "MEM_MARGIN_MODE," bitfld.long 0x4 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3" bitfld.long 0x4 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3" line.long 0x8 "MEM_WRENZ," bitfld.long 0x8 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3" line.long 0xC "MEM_PAGE_PGS," bitfld.long 0xC 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3" rgroup.long 0x1C0++0x7 line.long 0x0 "MEM_ROM," bitfld.long 0x0 0.--1. "ROM,ROM Mask (ROM)" "0,1,2,3" line.long 0x4 "MEM_ALGO," hexmask.long.byte 0x4 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 (ALGO 3)" hexmask.long.byte 0x4 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 (ALGO 2)" hexmask.long.byte 0x4 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 (ALGO 1)" hexmask.long.byte 0x4 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 (ALGO 0)" rgroup.quad 0x1C8++0x7 line.quad 0x0 "MEM_RINFO," hexmask.quad.byte 0x0 56.--63. 1. "U3,RAM Info Mask Upper 3 (RINFOU3)" hexmask.quad.byte 0x0 48.--55. 1. "U2,RAM Info Mask Upper 2 (RINFOU2)" hexmask.quad.byte 0x0 40.--47. 1. "U1,RAM Info Mask Upper 1 (RINFOU1)" hexmask.quad.byte 0x0 32.--39. 1. "U0,RAM Info Mask Upper 0 (RINFOU0)" hexmask.quad.byte 0x0 24.--31. 1. "L3,RAM Info Mask Lower 3 (RINFOL3)" newline hexmask.quad.byte 0x0 16.--23. 1. "L2,RAM Info Mask Lower 2 (RINFOL2)" hexmask.quad.byte 0x0 8.--15. 1. "L1,RAM Info Mask Lower 1 (RINFOL1)" hexmask.quad.byte 0x0 0.--7. 1. "L0,RAM Info Mask Lower 0 (RINFOL0)" tree.end tree "MCU_PLL0_CFG (MCU_PLL0_CFG)" base ad:0x40D00000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_pll0_PID," bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" newline hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x8++0x3 line.long 0x0 "CFG_pll0_CFG," hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" newline bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0: SSM is not present 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0: SSM Wave table is not present 1'b1,?" newline bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0: Fractional PLL 2'b01,?,2: De-Skew PLL,?" rgroup.long 0x10++0x7 line.long 0x0 "CFG_pll0_LOCKKEY0," hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers" newline rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll0_LOCKKEY1," hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers" rgroup.long 0x20++0x3 line.long 0x0 "CFG_pll0_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0: Synchronously select PLL and associated HSDIV..,?" newline bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0: Do not automatically switch to ref clock source..,?" newline bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0: PLL is disabled 1'b1,?" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0: Output clocks are derived from the VCO clock 1'b1,?" newline bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0: Post divide powered down,?" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0: Delta-Sigma modulator is disabled,1: Delta-Sigma modulator is enabled" newline bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0: Fractional NC DAC is disabled,1: Fractional NC DAC is enabled" rgroup.long 0x24++0x3 line.long 0x0 "CFG_pll0_STAT," bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0: PLL is not locked 1'b1,?" rgroup.long 0x30++0xB line.long 0x0 "CFG_pll0_FREQ_CTRL0," hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll0_FREQ_CTRL1," hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll0_DIV_CTRL," bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0: Reserved,1: Divide by 1 3'b010,?,3: Divide by 3 3'b100,?,5: Divide by 5 3'b110,?,7: Divide by 7" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" rgroup.long 0x40++0x7 line.long 0x0 "CFG_pll0_SS_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0: Spread spectrum modulation is enabled 1'b1,?" newline hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" newline bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" newline bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0: Center spread 1'b1,?" newline bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0: Use 128 point triangle wave table 1'b1,?" line.long 0x4 "CFG_pll0_SS_SPREAD," hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" newline hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" rgroup.long 0x60++0x3 line.long 0x0 "CFG_pll0_CAL_CTRL," bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0: Normal operation 1'b1,?" newline bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0: Use the calibration output to set the phase..,?" newline hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x64++0x3 line.long 0x0 "CFG_pll0_CAL_STAT," bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" newline hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" rgroup.long 0x80++0x7 line.long 0x0 "CFG_pll0_HSDIV_CTRL0," bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "CFG_pll0_HSDIV_CTRL1," bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x1000++0x3 line.long 0x0 "CFG_pll1_PID," bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" newline hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x1008++0x3 line.long 0x0 "CFG_pll1_CFG," hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" newline bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0: SSM is not present 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0: SSM Wave table is not present 1'b1,?" newline bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0: Fractional PLL 2'b01,?,2: De-Skew PLL,?" rgroup.long 0x1010++0x7 line.long 0x0 "CFG_pll1_LOCKKEY0," hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers" newline rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll1_LOCKKEY1," hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition1 registers" rgroup.long 0x1020++0x3 line.long 0x0 "CFG_pll1_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0: Synchronously select PLL and associated HSDIV..,?" newline bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0: Do not automatically switch to ref clock source..,?" newline bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0: PLL is disabled 1'b1,?" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0: Output clocks are derived from the VCO clock 1'b1,?" newline bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0: Post divide powered down,?" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0: Delta-Sigma modulator is disabled,1: Delta-Sigma modulator is enabled" newline bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0: Fractional NC DAC is disabled,1: Fractional NC DAC is enabled" rgroup.long 0x1024++0x3 line.long 0x0 "CFG_pll1_STAT," bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0: PLL is not locked 1'b1,?" rgroup.long 0x1030++0xB line.long 0x0 "CFG_pll1_FREQ_CTRL0," hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll1_FREQ_CTRL1," hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll1_DIV_CTRL," bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0: Reserved,1: Divide by 1 3'b010,?,3: Divide by 3 3'b100,?,5: Divide by 5 3'b110,?,7: Divide by 7" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" rgroup.long 0x1040++0x7 line.long 0x0 "CFG_pll1_SS_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0: Spread spectrum modulation is enabled 1'b1,?" newline hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" newline bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" newline bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0: Center spread 1'b1,?" newline bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0: Use 128 point triangle wave table 1'b1,?" line.long 0x4 "CFG_pll1_SS_SPREAD," hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" newline hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" rgroup.long 0x1060++0x3 line.long 0x0 "CFG_pll1_CAL_CTRL," bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0: Normal operation 1'b1,?" newline bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0: Use the calibration output to set the phase..,?" newline hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x1064++0x3 line.long 0x0 "CFG_pll1_CAL_STAT," bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" newline hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" rgroup.long 0x1080++0x13 line.long 0x0 "CFG_pll1_HSDIV_CTRL0," bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "CFG_pll1_HSDIV_CTRL1," bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x8 "CFG_pll1_HSDIV_CTRL2," bitfld.long 0x8 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0xC "CFG_pll1_HSDIV_CTRL3," bitfld.long 0xC 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0xC 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0xC 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0xC 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x10 "CFG_pll1_HSDIV_CTRL4," bitfld.long 0x10 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x2000++0x3 line.long 0x0 "CFG_pll2_PID," bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" newline hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x2008++0x3 line.long 0x0 "CFG_pll2_CFG," hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" newline bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0: SSM is not present 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0: SSM Wave table is not present 1'b1,?" newline bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0: Fractional PLL 2'b01,?,2: De-Skew PLL,?" rgroup.long 0x2010++0x7 line.long 0x0 "CFG_pll2_LOCKKEY0," hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers" newline rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll2_LOCKKEY1," hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition2 registers" rgroup.long 0x2020++0x3 line.long 0x0 "CFG_pll2_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0: Synchronously select PLL and associated HSDIV..,?" newline bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0: Do not automatically switch to ref clock source..,?" newline bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0: PLL is disabled 1'b1,?" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0: Output clocks are derived from the VCO clock 1'b1,?" newline bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0: Post divide powered down,?" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0: Delta-Sigma modulator is disabled,1: Delta-Sigma modulator is enabled" newline bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0: Fractional NC DAC is disabled,1: Fractional NC DAC is enabled" rgroup.long 0x2024++0x3 line.long 0x0 "CFG_pll2_STAT," bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0: PLL is not locked 1'b1,?" rgroup.long 0x2030++0xB line.long 0x0 "CFG_pll2_FREQ_CTRL0," hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll2_FREQ_CTRL1," hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll2_DIV_CTRL," bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0: Reserved,1: Divide by 1 3'b010,?,3: Divide by 3 3'b100,?,5: Divide by 5 3'b110,?,7: Divide by 7" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" rgroup.long 0x2040++0x7 line.long 0x0 "CFG_pll2_SS_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0: Spread spectrum modulation is enabled 1'b1,?" newline hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" newline bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" newline bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0: Center spread 1'b1,?" newline bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0: Use 128 point triangle wave table 1'b1,?" line.long 0x4 "CFG_pll2_SS_SPREAD," hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" newline hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" rgroup.long 0x2060++0x3 line.long 0x0 "CFG_pll2_CAL_CTRL," bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0: Normal operation 1'b1,?" newline bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0: Use the calibration output to set the phase..,?" newline hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x2064++0x3 line.long 0x0 "CFG_pll2_CAL_STAT," bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" newline hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" rgroup.long 0x2080++0x13 line.long 0x0 "CFG_pll2_HSDIV_CTRL0," bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "CFG_pll2_HSDIV_CTRL1," bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x8 "CFG_pll2_HSDIV_CTRL2," bitfld.long 0x8 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0xC "CFG_pll2_HSDIV_CTRL3," bitfld.long 0xC 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0xC 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0xC 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0xC 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x10 "CFG_pll2_HSDIV_CTRL4," bitfld.long 0x10 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" tree.end tree "MCU_PSRAM0_RAM (MCU_PSRAM0_RAM)" base ad:0x40280000 rgroup.long 0x0++0x3 line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCU_ROM0 (MCU_ROM0)" base ad:0x41800000 rgroup.long 0x0++0x3 line.long 0x0 "ROM_ROM_REG,The ROM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCU_RTI0_CFG (MCU_RTI0_CFG)" base ad:0x40600000 rgroup.long 0x0++0x1B line.long 0x0 "CFG_GCTRL," hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.." bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode" newline bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" line.long 0x4 "CFG_TBCTRL," bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme" line.long 0x8 "CFG_CAPCTRL," bitfld.long 0x8 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." bitfld.long 0x8 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "CFG_COMPCTRL," bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" newline bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" line.long 0x10 "CFG_FRC0," hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register." line.long 0x14 "CFG_UC0," hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x18 "CFG_CPUC0," hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." rgroup.long 0x20++0x7 line.long 0x0 "CFG_CAFRC0," hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event" line.long 0x4 "CFG_CAUC0," hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.." rgroup.long 0x30++0xB line.long 0x0 "CFG_FRC1," hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register." line.long 0x4 "CFG_UC1," hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x8 "CFG_CPUC1," hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." rgroup.long 0x40++0x7 line.long 0x0 "CFG_CAFRC1," hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event" line.long 0x4 "CFG_CAUC1," hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.." rgroup.long 0x50++0x27 line.long 0x0 "CFG_COMP0," hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x4 "CFG_UDCP0," hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x8 "CFG_COMP1," hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0xC "CFG_UDCP1," hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x10 "CFG_COMP2," hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x14 "CFG_UDCP2," hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x18 "CFG_COMP3," hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x1C "CFG_UDCP3," hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x20 "CFG_TBLCOMP," hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.." line.long 0x24 "CFG_TBHCOMP," hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.." rgroup.long 0x80++0xB line.long 0x0 "CFG_SETINT," bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" line.long 0x4 "CFG_CLEARINT," bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" line.long 0x8 "CFG_INTFLAG," bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" rgroup.long 0x90++0xF line.long 0x0 "CFG_DWDCTRL," hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.." line.long 0x4 "CFG_DWDPRLD," hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.." line.long 0x8 "CFG_WDSTATUS," bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0" line.long 0xC "CFG_WDKEY," hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.." rgroup.long 0xA0++0x3 line.long 0x0 "CFG_DWDCNTR," hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be generated in 1 second. User and.." rgroup.long 0xA4++0x1B line.long 0x0 "CFG_WWDRXNCTRL," hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration or if the watchdog is not.." line.long 0x4 "CFG_WWDSIZECTRL," hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read) privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).." line.long 0x8 "CFG_INTCLRENABLE," hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.." newline hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.." line.long 0xC "CFG_COMP0CLR," hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared. User and privilege.." line.long 0x10 "CFG_COMP1CLR," hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared. User and privilege.." line.long 0x14 "CFG_COMP2CLR," hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared. User and privilege.." line.long 0x18 "CFG_COMP3CLR," hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared. User and privilege.." tree.end tree "MCU_RTI1_CFG (MCU_RTI1_CFG)" base ad:0x40610000 rgroup.long 0x0++0x1B line.long 0x0 "CFG_GCTRL," hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.." bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode" newline bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" line.long 0x4 "CFG_TBCTRL," bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme" line.long 0x8 "CFG_CAPCTRL," bitfld.long 0x8 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." bitfld.long 0x8 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "CFG_COMPCTRL," bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" newline bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" line.long 0x10 "CFG_FRC0," hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register." line.long 0x14 "CFG_UC0," hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x18 "CFG_CPUC0," hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." rgroup.long 0x20++0x7 line.long 0x0 "CFG_CAFRC0," hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event" line.long 0x4 "CFG_CAUC0," hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.." rgroup.long 0x30++0xB line.long 0x0 "CFG_FRC1," hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register." line.long 0x4 "CFG_UC1," hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x8 "CFG_CPUC1," hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." rgroup.long 0x40++0x7 line.long 0x0 "CFG_CAFRC1," hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event" line.long 0x4 "CFG_CAUC1," hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.." rgroup.long 0x50++0x27 line.long 0x0 "CFG_COMP0," hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x4 "CFG_UDCP0," hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x8 "CFG_COMP1," hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0xC "CFG_UDCP1," hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x10 "CFG_COMP2," hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x14 "CFG_UDCP2," hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x18 "CFG_COMP3," hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x1C "CFG_UDCP3," hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x20 "CFG_TBLCOMP," hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.." line.long 0x24 "CFG_TBHCOMP," hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.." rgroup.long 0x80++0xB line.long 0x0 "CFG_SETINT," bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" line.long 0x4 "CFG_CLEARINT," bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" line.long 0x8 "CFG_INTFLAG," bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" rgroup.long 0x90++0xF line.long 0x0 "CFG_DWDCTRL," hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.." line.long 0x4 "CFG_DWDPRLD," hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.." line.long 0x8 "CFG_WDSTATUS," bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0" line.long 0xC "CFG_WDKEY," hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.." rgroup.long 0xA0++0x3 line.long 0x0 "CFG_DWDCNTR," hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be generated in 1 second. User and.." rgroup.long 0xA4++0x1B line.long 0x0 "CFG_WWDRXNCTRL," hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration or if the watchdog is not.." line.long 0x4 "CFG_WWDSIZECTRL," hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read) privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).." line.long 0x8 "CFG_INTCLRENABLE," hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.." newline hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.." line.long 0xC "CFG_COMP0CLR," hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared. User and privilege.." line.long 0x10 "CFG_COMP1CLR," hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared. User and privilege.." line.long 0x14 "CFG_COMP2CLR," hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared. User and privilege.." line.long 0x18 "CFG_COMP3CLR," hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared. User and privilege.." tree.end tree "MCU_TIMER0_CFG (MCU_TIMER0_CFG)" base ad:0x40400000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "MCU_TIMER1_CFG (MCU_TIMER1_CFG)" base ad:0x40410000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "MCU_TIMER2_CFG (MCU_TIMER2_CFG)" base ad:0x40420000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "MCU_TIMER3_CFG (MCU_TIMER3_CFG)" base ad:0x40430000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "MCU_TIMER4_CFG (MCU_TIMER4_CFG)" base ad:0x40440000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "MCU_TIMER5_CFG (MCU_TIMER5_CFG)" base ad:0x40450000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "MCU_TIMER6_CFG (MCU_TIMER6_CFG)" base ad:0x40460000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "MCU_TIMER7_CFG (MCU_TIMER7_CFG)" base ad:0x40470000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "MCU_TIMER8_CFG (MCU_TIMER8_CFG)" base ad:0x40480000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "MCU_TIMER9_CFG (MCU_TIMER9_CFG)" base ad:0x40490000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "MCU_UART0 (MCU_UART0)" base ad:0x40A00000 rgroup.long 0x0++0x3 line.long 0x0 "MEM_DLL,Divisor Latches Low Register" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" rgroup.long 0x0++0x7 line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" line.long 0x4 "MEM_DLH,Divisor Latches High Register" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.." bitfld.long 0x0 6.--7. "NOT_USED2," "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "NOT_USED1," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x7 line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "CTS_IT," "0,1" newline bitfld.long 0x0 6. "RTS_IT," "0,1" newline bitfld.long 0x0 5. "XOFF_IT," "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE," "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT," "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" line.long 0x4 "MEM_EFR,Enhanced Feature Register" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" rgroup.long 0x8++0x3 line.long 0x0 "MEM_FCR,Notes:" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered. If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of.." "0,1,2,3" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 0. "FIFO_EN," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE," newline bitfld.long 0x0 0. "IT_PENDING," "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "DIV_EN," "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1," "0,1" newline bitfld.long 0x0 3. "PARITY_EN," "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3" line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline rbitfld.long 0x4 7. "RESERVED," "0,1" newline bitfld.long 0x4 6. "TCR_TLR," "0,1" newline bitfld.long 0x4 5. "XON_EN," "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN," "0,1" newline bitfld.long 0x4 3. "CD_STS_CH," "0,1" newline bitfld.long 0x4 2. "RI_STS_CH," "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1" newline bitfld.long 0x4 0. "DTR," "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_CIR," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "RESERVED," "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_IRDA," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL," "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE," "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG," "0,1" newline bitfld.long 0x0 3. "ABORT," "0,1" newline bitfld.long 0x0 2. "CRC," "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_UART," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "RX_FIFO_STS," "0,1" newline bitfld.long 0x0 6. "TX_SR_E," "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E," "0,1" newline bitfld.long 0x0 4. "RX_BI," "0,1" newline bitfld.long 0x0 3. "RX_FE," "0,1" newline bitfld.long 0x0 2. "RX_PE," "0,1" newline bitfld.long 0x0 1. "RX_OE," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS," "0,1" newline bitfld.long 0x0 0. "CTS_STS," "0,1" rgroup.long 0x18++0x3 line.long 0x0 "MEM_TCR,Transmission Control Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" rgroup.long 0x18++0x7 line.long 0x0 "MEM_XOFF1,XOFF1 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" rgroup.long 0x1C++0x3 line.long 0x0 "MEM_TLR,Trigger Level Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" rgroup.long 0x1C++0xB line.long 0x0 "MEM_XOFF2,XOFF2 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP," "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7" line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is :" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_SFLSR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR," "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR," "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT," "0,1" newline bitfld.long 0x0 1. "CRC_ERROR," "0,1" newline bitfld.long 0x0 0. "RESERVED0," "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_TXFLL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" rgroup.long 0x2C++0x7 line.long 0x0 "MEM_TXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "MEM_RXFLL,IrDA modes only." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "MEM_SFREGL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" rgroup.long 0x34++0x3 line.long 0x0 "MEM_RXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "MEM_SFREGH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" rgroup.long 0x38++0x3 line.long 0x0 "MEM_BLR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED," rgroup.long 0x38++0x3 line.long 0x0 "MEM_UASR,UART Autobauding Status Register" bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." rgroup.long 0x3C++0xF line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX," "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "RX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 5. "DSR_IT," "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT," "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL," "0,1" line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x8 3.--7. 1. "RESERVED," newline bitfld.long 0x8 2. "DMA_COUNTER_RST," "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL," "0,1" line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED," newline hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." rgroup.long 0x54++0x3 line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "MEM_SYSS," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED," newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" rgroup.long 0x5C++0x7 line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN," "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT," "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY," "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY," "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY," "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY," "0,1" line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.." rgroup.long 0x64++0x7 line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL," line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL," rgroup.long 0x6C++0xB line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED," newline bitfld.long 0x0 2. "RHR_IT_DIS," "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED," newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1" line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED," line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED," rgroup.long 0x80++0x23 line.long 0x0 "MEM_MDR3,Mode definition register 3." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2," newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1" line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "MEM_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1," newline rbitfld.long 0x8 7. "RESERVED," "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7" line.long 0xC "MEM_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1," newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "MEM_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1," newline rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "MEM_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1," newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "MEM_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" rgroup.long 0xA4++0xF line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" line.long 0x4 "MEM_MAR,Multidrop Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "MEM_MMR,Multidrop Mask Register" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end sif (cpuis("AM68Ax-CR5-MCU")||cpuis("TDA4AL88-CR5-MCU")||cpuis("TDA4VE88-CR5-MCU")) tree "MCU_ARMSS" base ad:0x0 tree "MCU_ARMSS_RAT_CFG" base ad:0x40F90000 rgroup.long 0x0++0x7 line.long 0x0 "RAT_PID,This register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." line.long 0x4 "RAT_CONFIG,This register contains the configuration values for the module." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved." hexmask.long.byte 0x4 16.--23. 1. "ADDR_WIDTH,Number of address bits." hexmask.long.byte 0x4 8.--15. 1. "ADDRS,Number of addresses." hexmask.long.byte 0x4 0.--7. 1. "REGIONS,Number of regions." rgroup.long 0x20++0xF line.long 0x0 "RAT_CTRL_j,This region controls the size and the enable for a region. Offset = 20h + (j * 10h); where j = 0h to Fh." bitfld.long 0x0 31. "EN,Enable for the region." "0,1" hexmask.long 0x0 6.--30. 1. "RESERVED,Reserved." hexmask.long.byte 0x0 0.--5. 1. "SIZE,Size of the region in address bits." line.long 0x4 "RAT_BASE_j,This register is used for the base address for a region. This is the source address for matching to a region. Offset = 24h + (j * 10h); where j = 0h to Fh." hexmask.long 0x4 0.--31. 1. "BASE,Base address for the region. It must be aligned to the programmed size." line.long 0x8 "RAT_TRANS_L_j,This register contains the translated lower address bits for a region. Offset = 28h + (j * 10h); where j = 0h to Fh." hexmask.long 0x8 0.--31. 1. "LOWER,Translated lower address bits for the region. It must be aligned to the programmed size." line.long 0xC "RAT_TRANS_U_j,This register contains the translated upper address bits for a region. Offset = 2Ch + (j * 10h); where j = 0h to Fh" hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved." hexmask.long.word 0xC 0.--15. 1. "UPPER,Translated upper address bits for the region." rgroup.long 0x804++0x3 line.long 0x0 "RAT_DESTINATION_ID,This register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." rgroup.long 0x820++0x3 line.long 0x0 "RAT_EXCEPTION_LOGGING_CONTROL,This register controls the exception logging." hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x824++0x17 line.long 0x0 "RAT_EXCEPTION_LOGGING_HEADER0,This register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "RAT_EXCEPTION_LOGGING_HEADER1,This register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED,Reserved." line.long 0x8 "RAT_EXCEPTION_LOGGING_DATA0,This register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "RAT_EXCEPTION_LOGGING_DATA1,This register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 12 bits." line.long 0x10 "RAT_EXCEPTION_LOGGING_DATA2,This register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED,Reserved." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED,Reserved." "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "RAT_EXCEPTION_LOGGING_DATA3,This register contains the fourth word of the data. Reading this register will clear the error pending bit." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED,Reserved." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x840++0x13 line.long 0x0 "RAT_EXCEPTION_PEND_SET,This register allows to set the exception pending signal." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pending signal." "0,1" line.long 0x4 "RAT_EXCEPTION_PEND_CLEAR,This register allows to clear the pend signal." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pending signal." "0,1" line.long 0x8 "RAT_EXCEPTION_ENABLE_SET,This register allows to set the interrupt enable signal." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "RAT_EXCEPTION_ENABLE_CLEAR,This register allows to clear the interrupt enable signal." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "RAT_EOI_REG,EOI Register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt.." hexmask.long.word 0x10 16.--31. 1. "RESERVED,Reserved." hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI value." tree.end tree "MCU_ARMSS_VIC_CFG" base ad:0x40F80000 rgroup.long 0x0++0x27 line.long 0x0 "VIM_PID,This register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." line.long 0x4 "VIM_INFO,This contains information about the configuration of the VIM." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.word 0x4 0.--10. 1. "INTERRUPTS,Indicates the number of interrupts supported by the VIM." line.long 0x8 "VIM_PRIIRQ,This register contains the number of the highest priority pending IRQ." bitfld.long 0x8 31. "VALID,This field indicates if the NUM field of this register is valid." "0,1" hexmask.long.word 0x8 20.--30. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0x8 16.--19. 1. "PRI,This field indicates the priority of the pending IRQ interrupt." hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.word 0x8 0.--9. 1. "NUM,This field indicates the interrupt number of the pending IRQ interrupt with the highest priority." line.long 0xC "VIM_PRIFIQ,This register contains the number of the highest priority pending FIQ." bitfld.long 0xC 31. "VALID,This field indicates if the NUM field of this register is valid." "0,1" hexmask.long.word 0xC 20.--30. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0xC 16.--19. 1. "PRI,This field indicates the priority of the pending FIQ interrupt." hexmask.long.byte 0xC 10.--15. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.word 0xC 0.--9. 1. "NUM,This field indicates the interrupt number of the pending FIQ interrupt with the highest priority." line.long 0x10 "VIM_IRQGSTS,This register indicates which groups of interrupts have pending. unmasked IRQ interrupts." hexmask.long 0x10 0.--31. 1. "STS,This field indicates that one or more interrupts in group M are mapped to IRQ unmasked and pending. Bit 0 corresponds to group 0 bit 1 corresponds to group 1 etc. The interrupts associated with each group are [(M*32)+31:M*32]" line.long 0x14 "VIM_FIQGSTS,This register indicates which groups of interrupts have pending. unmasked FIQ interrupts." hexmask.long 0x14 0.--31. 1. "STS,This field indicates that one or more interrupts in group M are mapped to FIQ unmasked and pending. Bit 0 corresponds to group 0 bit 1 corresponds to group 1 etc. The interrupts associated with each group are [(M*32)+31:M*32]" line.long 0x18 "VIM_IRQVEC,This register contains the 32-bit interrupt vector address of the currently pending IRQ." hexmask.long 0x18 2.--31. 1. "ADDR,This field contains the upper 30 bits of the 32-bit interrupt vector address (addresses must be 32-bit aligned) of the currently pending highest priority IRQ (as indicated by the" bitfld.long 0x18 0.--1. "RESERVED,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.)" "0,1,2,3" line.long 0x1C "VIM_FIQVEC,This register contains the 32-bit interrupt vector address of the currently pending FIQ." hexmask.long 0x1C 2.--31. 1. "ADDR,This field contains the upper 30 bits of the 32-bit interrupt vector address (addresses must be 32-bit aligned) of the currently pending highest priority FIQ (as indicated by the" bitfld.long 0x1C 0.--1. "RESERVED,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.)" "0,1,2,3" line.long 0x20 "VIM_ACTIRQ,This register contains the number of the active IRQ." bitfld.long 0x20 31. "VALID,This field indicates if the NUM field of this register is valid." "0,1" hexmask.long.word 0x20 20.--30. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0x20 16.--19. 1. "PRI,This field indicates the priority of the active IRQ interrupt." hexmask.long.byte 0x20 10.--15. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.word 0x20 0.--9. 1. "NUM,This field indicates the interrupt number of the active IRQ interrupt." line.long 0x24 "VIM_ACTFIQ,This register contains the number of the active FIQ." bitfld.long 0x24 31. "VALID,This field indicates if the NUM field of this register is valid." "0,1" hexmask.long.word 0x24 20.--30. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0x24 16.--19. 1. "PRI,This field indicates the priority of the active FIQ interrupt." hexmask.long.byte 0x24 10.--15. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.word 0x24 0.--9. 1. "NUM,This field indicates the interrupt number of the active FIQ interrupt." rgroup.long 0x30++0x3 line.long 0x0 "VIM_DEDVEC,This register contains the 32-bit interrupt vector address to be used as a default in case of a DED error in any of the vectors." hexmask.long 0x0 2.--31. 1. "ADDR,This field contains the upper 30 bits of the 32-bit interrupt vector address (the address must be 32-bit aligned) of an interrupt to be used if an uncorrectable double-bit error (DED) is detected in any of the interrupt vector addresses." rbitfld.long 0x0 0.--1. "RESERVED,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.)" "0,1,2,3" rgroup.long 0x400++0x1F line.long 0x0 "VIM_RAW_j,This register indicates the raw status of the events in group M. Offset = 400h + (j * 20h); where j = 0h to Fh." hexmask.long 0x0 0.--31. 1. "STS,This is the raw status of the events in group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x4 "VIM_STS_j,This register indicates the masked status of the events in group M. Offset = 404h + (j * 20h); where j = 0h to Fh." hexmask.long 0x4 0.--31. 1. "MSK,This is the masked status of the events in group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x8 "VIM_INTR_EN_SET_j,This register is used to enable the mask for the events in group M. Offset = 408h + (j * 20h); where j = 0h to Fh." hexmask.long 0x8 0.--31. 1. "MSK,This field is used to enable the mask of events in group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0xC "VIM_INTR_EN_CLR_j,This register is used to disable the mask for the events in group M. Offset = 40Ch + (j * 20h); where j = 0h to Fh." hexmask.long 0xC 0.--31. 1. "MSK,This field is used to disable the mask of events in group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x10 "VIM_IRQSTS_j,This register indicates the masked status of the events in Group M that are also mapped as IRQs. Offset = 410h + (j * 20h); where j = 0h to Fh." hexmask.long 0x10 0.--31. 1. "MSK,This is the masked status of the events in group M that are mapped to IRQ. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x14 "VIM_FIQSTS_j,This register indicates the masked status of the events in group M that are also mapped as FIQs. Offset = 414h + (j * 20h); where j = 0h to Fh." hexmask.long 0x14 0.--31. 1. "MSK,This is the masked status of the events in group M that are mapped to FIQ. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x18 "VIM_INTMAP_j,This register is used to map interrupts as IRQ or FIQ. Offset = 418h + (j * 20h); where j = 0h to Fh." hexmask.long 0x18 0.--31. 1. "MSK,This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x1C "VIM_INTTYPE_j,This register indicates whether an interrupt is a pulse or level source. Offset = 41Ch + (j * 20h); where j = 0h to Fh." hexmask.long 0x1C 0.--31. 1. "MSK,This field is used to indicate whether the source of an interrupt is a level (default) or a pulse for event group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." rgroup.long 0x1000++0x3 line.long 0x0 "VIM_PRI_INT_j,This register is used to set the priority of interrupt Q. Offset = 1000h + (j * 4h); where j = 0h to 1FFh." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0x0 0.--3. 1. "VAL,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration." rgroup.long 0x2000++0x3 line.long 0x0 "VIM_VEC_INT_j,This register contains the vector address associated with interrupt Q. Offset = 2000h + (j * 4h); where j = 0h to 1FFh." hexmask.long 0x0 2.--31. 1. "VAL,These are the upper 30 bits of the 32-bit vector address associated with interrupt Q. It is the address that will be reflected in the" rbitfld.long 0x0 0.--1. "RESERVED,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.)" "0,1,2,3" tree.end tree.end endif tree "MCU_CBASS0" tree "MCU_CBASS0_ERR (MCU_CBASS0_ERR)" base ad:0x47100000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end tree "MCU_CBASS0_GLB (MCU_CBASS0_GLB)" base ad:0x45B06000 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x20++0x3 line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x40++0x7 line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree "MCU_CBASS0_ISC (MCU_CBASS0_ISC)" base ad:0x45810000 rgroup.long 0x0++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_rmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu0_rmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x10++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_rmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_rmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_rmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_rmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_rmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_rmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_rmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_rmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_rmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu0_rmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x30++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_rmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_rmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_rmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_rmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_rmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_rmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_rmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_rmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_rmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu0_rmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x50++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_rmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_rmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_rmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_rmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_rmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_rmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_rmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_rmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_rmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu0_rmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x70++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_rmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_rmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_rmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_rmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_rmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_rmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_rmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_rmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_rmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu0_rmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x400++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_wmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu0_wmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x410++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_wmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_wmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_wmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_wmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_wmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_wmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_wmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_wmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_wmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu0_wmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x430++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_wmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_wmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_wmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_wmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_wmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_wmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_wmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_wmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_wmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu0_wmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x450++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_wmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_wmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_wmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_wmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_wmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_wmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_wmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_wmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_wmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu0_wmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x470++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_wmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_wmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_wmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_wmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_wmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_wmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_wmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_wmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_wmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu0_wmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x800++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_pmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu0_pmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x810++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_pmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_pmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_pmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_pmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_pmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_pmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_pmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_pmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_pmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu0_pmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x830++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_pmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_pmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_pmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_pmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_pmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_pmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_pmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_pmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_pmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu0_pmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x850++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_pmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_pmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_pmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_pmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_pmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_pmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_pmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_pmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_pmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu0_pmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x870++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_pmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_pmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_pmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_pmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_pmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu0_pmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_pmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu0_pmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu0_pmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu0_pmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1000++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_rmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu1_rmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1010++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_rmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_rmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_rmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_rmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_rmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_rmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_rmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_rmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_rmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu1_rmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1030++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_rmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_rmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_rmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_rmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_rmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_rmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_rmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_rmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_rmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu1_rmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1050++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_rmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_rmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_rmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_rmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_rmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_rmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_rmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_rmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_rmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu1_rmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1070++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_rmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_rmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_rmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_rmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_rmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_rmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_rmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_rmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_rmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu1_rmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1400++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_wmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu1_wmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1410++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_wmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_wmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_wmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_wmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_wmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_wmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_wmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_wmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_wmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu1_wmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1430++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_wmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_wmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_wmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_wmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_wmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_wmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_wmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_wmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_wmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu1_wmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1450++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_wmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_wmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_wmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_wmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_wmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_wmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_wmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_wmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_wmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu1_wmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1470++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_wmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_wmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_wmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_wmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_wmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_wmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_wmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_wmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_wmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu1_wmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1800++0x3 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_pmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu1_pmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1810++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_pmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_pmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_pmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_pmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_pmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_pmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_pmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_pmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_pmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu1_pmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1830++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_pmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_pmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_pmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_pmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_pmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_pmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_pmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_pmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_pmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu1_pmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1850++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_pmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_pmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_pmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_pmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_pmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_pmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_pmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_pmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_pmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu1_pmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x1870++0x13 line.long 0x0 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_pmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_pmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_pmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_pmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_pmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_sl_mcu_0.cpu1_pmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_pmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_sl_mcu_0.cpu1_pmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_sl_mcu_0_cpu1_pmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_sl_mcu_0.cpu1_pmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3000++0x3 line.long 0x0 "ISC_REGS_Isa3ss_am62_mcu_0_ctxcach_ext_dma_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Isa3ss_am62_mcu_0.ctxcach_ext_dma region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3010++0x13 line.long 0x0 "ISC_REGS_Isa3ss_am62_mcu_0_ctxcach_ext_dma_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Isa3ss_am62_mcu_0.ctxcach_ext_dma region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Isa3ss_am62_mcu_0_ctxcach_ext_dma_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Isa3ss_am62_mcu_0.ctxcach_ext_dma region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Isa3ss_am62_mcu_0_ctxcach_ext_dma_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Isa3ss_am62_mcu_0.ctxcach_ext_dma region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Isa3ss_am62_mcu_0_ctxcach_ext_dma_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Isa3ss_am62_mcu_0.ctxcach_ext_dma region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Isa3ss_am62_mcu_0_ctxcach_ext_dma_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Isa3ss_am62_mcu_0.ctxcach_ext_dma region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3030++0x13 line.long 0x0 "ISC_REGS_Isa3ss_am62_mcu_0_ctxcach_ext_dma_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Isa3ss_am62_mcu_0.ctxcach_ext_dma region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Isa3ss_am62_mcu_0_ctxcach_ext_dma_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Isa3ss_am62_mcu_0.ctxcach_ext_dma region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Isa3ss_am62_mcu_0_ctxcach_ext_dma_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Isa3ss_am62_mcu_0.ctxcach_ext_dma region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Isa3ss_am62_mcu_0_ctxcach_ext_dma_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Isa3ss_am62_mcu_0.ctxcach_ext_dma region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Isa3ss_am62_mcu_0_ctxcach_ext_dma_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Isa3ss_am62_mcu_0.ctxcach_ext_dma region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3050++0x13 line.long 0x0 "ISC_REGS_Isa3ss_am62_mcu_0_ctxcach_ext_dma_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Isa3ss_am62_mcu_0.ctxcach_ext_dma region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Isa3ss_am62_mcu_0_ctxcach_ext_dma_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Isa3ss_am62_mcu_0.ctxcach_ext_dma region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Isa3ss_am62_mcu_0_ctxcach_ext_dma_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Isa3ss_am62_mcu_0.ctxcach_ext_dma region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Isa3ss_am62_mcu_0_ctxcach_ext_dma_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Isa3ss_am62_mcu_0.ctxcach_ext_dma region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Isa3ss_am62_mcu_0_ctxcach_ext_dma_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Isa3ss_am62_mcu_0.ctxcach_ext_dma region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." rgroup.long 0x3070++0x13 line.long 0x0 "ISC_REGS_Isa3ss_am62_mcu_0_ctxcach_ext_dma_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Isa3ss_am62_mcu_0.ctxcach_ext_dma region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Isa3ss_am62_mcu_0_ctxcach_ext_dma_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Isa3ss_am62_mcu_0.ctxcach_ext_dma region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Isa3ss_am62_mcu_0_ctxcach_ext_dma_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Isa3ss_am62_mcu_0.ctxcach_ext_dma region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Isa3ss_am62_mcu_0_ctxcach_ext_dma_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Isa3ss_am62_mcu_0.ctxcach_ext_dma region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Isa3ss_am62_mcu_0_ctxcach_ext_dma_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Isa3ss_am62_mcu_0.ctxcach_ext_dma region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." tree.end tree "MCU_CBASS0_QOS (MCU_CBASS0_QOS)" base ad:0x45D10000 rgroup.long 0x100++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_mcu_0_cpu0_rmst_map0,The Map Register defines the fields for the master Ipulsar_sl_mcu_0.cpu0_rmst per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x500++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_mcu_0_cpu0_wmst_map0,The Map Register defines the fields for the master Ipulsar_sl_mcu_0.cpu0_wmst per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x900++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_mcu_0_cpu0_pmst_map0,The Map Register defines the fields for the master Ipulsar_sl_mcu_0.cpu0_pmst per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x1100++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_mcu_0_cpu1_rmst_map0,The Map Register defines the fields for the master Ipulsar_sl_mcu_0.cpu1_rmst per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x1500++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_mcu_0_cpu1_wmst_map0,The Map Register defines the fields for the master Ipulsar_sl_mcu_0.cpu1_wmst per channel." bitfld.long 0x0 28.--29. "ATYPE,epriority signal for channel N. 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence." "0: physical,1: intermediate,2: virtual,3: physical with coherence" hexmask.long.word 0x0 16.--27. 1. "VIRTID,virtid signal for channel N." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." newline bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x1900++0x3 line.long 0x0 "QOS_REGS_Ipulsar_sl_mcu_0_cpu1_pmst_map0,The Map Register defines the fields for the master Ipulsar_sl_mcu_0.cpu1_pmst per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x3100++0x3 line.long 0x0 "QOS_REGS_Isa3ss_am62_mcu_0_ctxcach_ext_dma_map0,The Map Register defines the fields for the master Isa3ss_am62_mcu_0.ctxcach_ext_dma per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" tree.end tree.end tree "MCU_FSS0" tree "MCU_FSS0_CFG (MCU_FSS0_CFG)" base ad:0x47000000 rgroup.long 0x0++0x3 line.long 0x0 "FSS_MMR__FSS_MMR_CFG__FSS_GENREGS_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "FSS_MMR__FSS_MMR_CFG__FSS_GENREGS_SYSCONFIG,Controls various parameters of the cotroller state." bitfld.long 0x0 8. "OSPI_32B_DISABLE_MODE,0 OSPI 32bit mode enabled. 1 OSPI 32bit mode disabled" "0,1" bitfld.long 0x0 7. "DISXIP,0 XIP Prefetch Enabled. 1 XIP prefetch disabled" "0,1" bitfld.long 0x0 6. "OSPI_DDR_DISABLE_MODE,0 OSPI DDR mode enabled. 1 OSPI DDR mode disabled" "0,1" newline bitfld.long 0x0 3. "ECC_DISABLE_ADR,0 Block address within ECC calculation 1 Block address not within ECC calculation" "0,1" rbitfld.long 0x0 2. "FSS_AES_EN_IPCFG,1 select security 0 disable security" "0,1" bitfld.long 0x0 1. "HB_OSPI,1 select hb path. 0 select ospi path" "0,1" newline bitfld.long 0x0 0. "ECC_EN,0 ECC disabled. 1 ECC enabled" "0,1" rgroup.long 0x10++0x13 line.long 0x0 "FSS_MMR__FSS_MMR_CFG__FSS_GENREGS_EOI,The End of Interrupt (EOI) MISC Register allows the CPU to acknowledge completion of an interrupt by writing to the EOI for MISC interrupt sources. An eoi_write signal will be generated and another interrupt will be.." bitfld.long 0x0 0. "EOI_VECTOR,Write with bit position of targeted interrupt. (E.g. Ext FSS ECC is bit 0). Upon write level interrupt will clear and if un-serviced will issue another pulse interrupt" "0,1" line.long 0x4 "FSS_MMR__FSS_MMR_CFG__FSS_GENREGS_STATUS_RAW,The IRQ_STATUS_RAW register allows the interrupt sources to be manually set when writing a 1 to a specific bit. Write 0: No action Write 1: Set event Read 0: No event pending Read 1: Event pending" bitfld.long 0x4 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1" bitfld.long 0x4 1. "ECC_ERROR_2BIT,ECC error on 2 bits. Not correctable" "0,1" bitfld.long 0x4 0. "ECC_ERROR_1BIT,ECC error on 1 bits. correctable" "0,1" line.long 0x8 "FSS_MMR__FSS_MMR_CFG__FSS_GENREGS_STATUS,The IRQ_STATUS register allows the interrupt sources to be manually cleared when writing a 1 to a specific bit. Write 0: No action Write 1: Clear event Read 0: No event pending Read 1: Event pending" bitfld.long 0x8 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1" bitfld.long 0x8 1. "ECC_ERROR_2BIT,ECC error on 2 bits. Not correctable" "0,1" bitfld.long 0x8 0. "ECC_ERROR_1BIT,ECC error on 1 bits. correctable" "0,1" line.long 0xC "FSS_MMR__FSS_MMR_CFG__FSS_GENREGS_ENABLE_SET,The IRQ_ENABLE_SET register allows the interrupt sources to be manually enabled when writing a 1 to a specific bit. Write 0: No action Write 1: Enable event Read 0: Event is disabled Read 1: Event is enabled" bitfld.long 0xC 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1" bitfld.long 0xC 1. "ECC_ERROR_2BIT,ECC error on 2 bits. Not correctable" "0,1" bitfld.long 0xC 0. "ECC_ERROR_1BIT,ECC error on 1 bits. correctable" "0,1" line.long 0x10 "FSS_MMR__FSS_MMR_CFG__FSS_GENREGS_ENABLE_CLR,The IRQ_ENABLE_CLR register allows the interrupt sources to be manually disabled when writing a 1 to a specific bit. Write 0: No action Write 1: Disable event Read 0: Event is disabled Read 1: Event is enabled" bitfld.long 0x10 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1" bitfld.long 0x10 1. "ECC_ERROR_2BIT,ECC error on 2 bits. Not correctable" "0,1" bitfld.long 0x10 0. "ECC_ERROR_1BIT,ECC error on 1 bits. correctable" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "FSS_MMR__FSS_MMR_CFG__FSS_GENREGS_ECC_RGSTRT,This defines the start of the ECC region in 4KBytes steps." hexmask.long.tbyte 0x0 0.--19. 1. "R_START,This defines the start of the ECC region in 4KBytes steps. Address start = {start[19:0] 0x000} 0x0 means the start is 0x0000_0000 0x1 means the start is 0x0000_1000 0xA means the start is 0x0000_A000 Note the offset + size should be <=.." line.long 0x4 "FSS_MMR__FSS_MMR_CFG__FSS_GENREGS_ECC_RGSIZ,This defines the size of the ECC region in 4KBytes steps." hexmask.long.tbyte 0x4 0.--19. 1. "R_SIZE,This defines the size of the ECC region in 4KBytes steps 0x0 means the size is zero and disabled 0x1 means the size is 4KBytes 0xA means the size is 40KBytes 0xF_FFFF means the size is 4GBytes Note the offset + size should be <= 4GBytes wrap.." rgroup.long 0x70++0x3 line.long 0x0 "FSS_MMR__FSS_MMR_CFG__FSS_GENREGS_ECC_BLOCK_ADR,The ERR_ECC_BLOCK_ADR register holds the current top of stack ECC error block address. this is only valid when the ecc_err_valid is set" hexmask.long 0x0 5.--31. 1. "ECC_ERROR_BLOCK_ADDR,ECC 32 byte aligned block address" rgroup.long 0x74++0x7 line.long 0x0 "FSS_MMR__FSS_MMR_CFG__FSS_GENREGS_ECC_TYPE,The ERR_ECC_TYPE register holds the current top of stack ECC error info. this is only valid when the ecc_err_valid is set" bitfld.long 0x0 31. "ECC_ERR_VALID,When set indicates that there is valid ECC error information available Writing a one to this register will pop the top of the stack" "0,1" rbitfld.long 0x0 5. "ECC_ERR_ADR,When set indicates that there was a single error detected within the address field" "0,1" rbitfld.long 0x0 4. "ECC_ERR_MAC,When set indicates that there was a single error detected within the MAC field" "0,1" newline rbitfld.long 0x0 3. "ECC_ERR_DA1,When set indicates that there was a single error detected within the High Data word" "0,1" rbitfld.long 0x0 2. "ECC_ERR_DA0,When set indicates that there was a single error detected within the Low Data word" "0,1" rbitfld.long 0x0 1. "ECC_ERR_DED,When set indicates that there was a double error detected for the block" "0,1" newline rbitfld.long 0x0 0. "ECC_ERR_SEC,hen set indicates that there was a single error detected for the block" "0,1" line.long 0x4 "FSS_MMR__FSS_MMR_CFG__FSS_GENREGS_WRT_TYPE,The ERR_WRT_TYPE register holds the current top of stack write error info. this is only valid when the wrt_err_valid is set" bitfld.long 0x4 31. "WRT_ERR_VALID,When set indicates that there is valid write error information available Writing a one to this register will pop the top of the stack" "0,1" rbitfld.long 0x4 13. "WRT_ERR_BEN,When set indicates that there was a write error due to a non-contiguous byte enables" "0,1" rbitfld.long 0x4 12. "WRT_ERR_ADR,When set indicates that there was a write error due to a non-aligned address" "0,1" newline hexmask.long.word 0x4 0.--11. 1. "WRT_ERR_ROUTEID,Indicates the Route ID for the Master that caused the write error" tree.end tree "MCU_FSS0_FSAS_0" tree "MCU_FSS0_FSAS_0_DAT_REG0 (MCU_FSS0_FSAS_0_DAT_REG0)" base ad:0x400000000 rgroup.long 0x0++0x3 line.long 0x0 "DAT_REG0_hpb_data_mem,FSAS data region0" hexmask.long 0x0 0.--31. 1. "HPB_DATA,FSAS data region0" tree.end tree "MCU_FSS0_FSAS_0_DAT_REG1 (MCU_FSS0_FSAS_0_DAT_REG1)" base ad:0x50000000 rgroup.long 0x0++0x3 line.long 0x0 "DAT_REG1_hpb_data_mem,FSAS boot data region1" hexmask.long 0x0 0.--31. 1. "HPB_DATA,FSAS data region1" tree.end tree "MCU_FSS0_FSAS_0_DAT_REG3 (MCU_FSS0_FSAS_0_DAT_REG3)" base ad:0x500000000 rgroup.long 0x0++0x3 line.long 0x0 "DAT_REG3_hpb_data_mem,FSAS bypass data region3" hexmask.long 0x0 0.--31. 1. "HPB_DATA,FSAS data region1" tree.end tree "MCU_FSS0_FSAS_0_FSAS_CFG (MCU_FSS0_FSAS_0_FSAS_CFG)" base ad:0x47010000 rgroup.long 0x4++0x1F line.long 0x0 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_SYSCONFIG,Controls various parameters of the cotroller state." bitfld.long 0x0 8. "OSPI_32B_DISABLE_MODE,0 OSPI 32bit mode enabled. 1 OSPI 32bit mode disabled" "0,1" bitfld.long 0x0 7. "DISXIP,0 XIP Prefetch Enabled. 1 XIP prefetch disabled" "0,1" bitfld.long 0x0 6. "OSPI_DDR_DISABLE_MODE,0 OSPI DDR mode enabled. 1 OSPI DDR mode disabled" "0,1" newline bitfld.long 0x0 3. "ECC_DISABLE_ADR,0 Block address within ECC calculation 1 Block address not within ECC calculation" "0,1" rbitfld.long 0x0 2. "FSS_AES_EN_IPCFG,1 select security 0 disable security" "0,1" bitfld.long 0x0 0. "ECC_EN,0 ECC disabled. 1 ECC enabled" "0,1" line.long 0x4 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_FRAG_ADR,This FRAG_ADR is the address of a request that frag_hi or frag_lo boundary occurs" hexmask.long 0x4 0.--31. 1. "FRAG_ADDR,This address is used to determine the boundary of frag_hi and flag_lo" line.long 0x8 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_FRAG_CTL,The FRAG_CTL determins which frag region is fragmented" bitfld.long 0x8 1. "FRAG_HI,When set any address greater than or equal to frag_addr will be fragmented to 16 bits" "0,1" bitfld.long 0x8 0. "FRAG_LO,When set any address less than frag_addr will be fragmented to 16 bits" "0,1" line.long 0xC "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_EOI,The End of Interrupt (EOI) MISC Register allows the CPU to acknowledge completion of an interrupt by writing to the EOI for MISC interrupt sources. An eoi_write signal will be generated and another interrupt will be.." bitfld.long 0xC 0. "EOI_VECTOR,Write with bit position of targeted interrupt. (E.g. Ext FSS ECC is bit 0). Upon write level interrupt will clear and if un-serviced will issue another pulse interrupt" "0,1" line.long 0x10 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_STATUS_RAW,The IRQ_STATUS_RAW register allows the interrupt sources to be manually set when writing a 1 to a specific bit. Write 0: No action Write 1: Set event Read 0: No event pending Read 1: Event pending" bitfld.long 0x10 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1" bitfld.long 0x10 1. "ECC_ERROR_2BIT,ECC error on 2 bits. Not correctable" "0,1" bitfld.long 0x10 0. "ECC_ERROR_1BIT,ECC error on 1 bits. correctable" "0,1" line.long 0x14 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_STATUS,The IRQ_STATUS register allows the interrupt sources to be manually cleared when writing a 1 to a specific bit. Write 0: No action Write 1: Clear event Read 0: No event pending Read 1: Event pending" bitfld.long 0x14 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1" bitfld.long 0x14 1. "ECC_ERROR_2BIT,ECC error on 2 bits. Not correctable" "0,1" bitfld.long 0x14 0. "ECC_ERROR_1BIT,ECC error on 1 bits. correctable" "0,1" line.long 0x18 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ENABLE_SET,The IRQ_ENABLE_SET register allows the interrupt sources to be manually enabled when writing a 1 to a specific bit. Write 0: No action Write 1: Enable event Read 0: Event is disabled Read 1: Event is enabled" bitfld.long 0x18 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1" bitfld.long 0x18 1. "ECC_ERROR_2BIT,ECC error on 2 bits. Not correctable" "0,1" bitfld.long 0x18 0. "ECC_ERROR_1BIT,ECC error on 1 bits. correctable" "0,1" line.long 0x1C "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ENABLE_CLR,The IRQ_ENABLE_CLR register allows the interrupt sources to be manually disabled when writing a 1 to a specific bit. Write 0: No action Write 1: Disable event Read 0: Event is disabled Read 1: Event is enabled" bitfld.long 0x1C 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1" bitfld.long 0x1C 1. "ECC_ERROR_2BIT,ECC error on 2 bits. Not correctable" "0,1" bitfld.long 0x1C 0. "ECC_ERROR_1BIT,ECC error on 1 bits. correctable" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ECC_RGSTRT,This defines the start of the ECC region in 4KBytes steps." hexmask.long.tbyte 0x0 0.--19. 1. "R_START,This defines the start of the ECC region in 4KBytes steps. Address start = {start[19:0] 0x000} 0x0 means the start is 0x0000_0000 0x1 means the start is 0x0000_1000 0xA means the start is 0x0000_A000 Note the offset + size should be <=.." line.long 0x4 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ECC_RGSIZ,This defines the size of the ECC region in 4KBytes steps." hexmask.long.tbyte 0x4 0.--19. 1. "R_SIZE,This defines the size of the ECC region in 4KBytes steps 0x0 means the size is zero and disabled 0x1 means the size is 4KBytes 0xA means the size is 40KBytes 0xF_FFFF means the size is 4GBytes Note the offset + size should be <= 4GBytes wrap.." rgroup.long 0x70++0x3 line.long 0x0 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ECC_BLOCK_ADR,The ERR_ECC_BLOCK_ADR register holds the current top of stack ECC error block address. this is only valid when the ecc_err_valid is set" hexmask.long 0x0 5.--31. 1. "ECC_ERROR_BLOCK_ADDR,ECC 32 byte aligned block address" rgroup.long 0x74++0x7 line.long 0x0 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ECC_TYPE,The ERR_ECC_TYPE register holds the current top of stack ECC error info. this is only valid when the ecc_err_valid is set" bitfld.long 0x0 31. "ECC_ERR_VALID,When set indicates that there is valid ECC error information available Writing a one to this register will pop the top of the stack" "0,1" rbitfld.long 0x0 5. "ECC_ERR_ADR,When set indicates that there was a single error detected within the address field" "0,1" rbitfld.long 0x0 4. "ECC_ERR_MAC,When set indicates that there was a single error detected within the MAC field" "0,1" newline rbitfld.long 0x0 3. "ECC_ERR_DA1,When set indicates that there was a single error detected within the High Data word" "0,1" rbitfld.long 0x0 2. "ECC_ERR_DA0,When set indicates that there was a single error detected within the Low Data word" "0,1" rbitfld.long 0x0 1. "ECC_ERR_DED,When set indicates that there was a double error detected for the block" "0,1" newline rbitfld.long 0x0 0. "ECC_ERR_SEC,hen set indicates that there was a single error detected for the block" "0,1" line.long 0x4 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_WRT_TYPE,The ERR_WRT_TYPE register holds the current top of stack write error info. this is only valid when the wrt_err_valid is set" bitfld.long 0x4 31. "WRT_ERR_VALID,When set indicates that there is valid write error information available Writing a one to this register will pop the top of the stack" "0,1" rbitfld.long 0x4 13. "WRT_ERR_BEN,When set indicates that there was a write error due to a non-contiguous byte enables" "0,1" rbitfld.long 0x4 12. "WRT_ERR_ADR,When set indicates that there was a write error due to a non-aligned address" "0,1" newline hexmask.long.word 0x4 0.--11. 1. "WRT_ERR_ROUTEID,Indicates the Route ID for the Master that caused the write error" tree.end tree "MCU_FSS0_FSAS_0_OTFA_CFG (MCU_FSS0_FSAS_0_OTFA_CFG)" base ad:0x47020000 rgroup.long 0x0++0x3 line.long 0x0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_revid," hexmask.long 0x0 0.--31. 1. "REVID,REVID" rgroup.long 0x4++0x21B line.long 0x0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_scfg," bitfld.long 0x0 0.--1. "IDLE_MODE,IDLE MODE" "0,1,2,3" line.long 0x4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_isr," hexmask.long.byte 0x4 12.--15. 1. "MAC_ERR,MAC error" hexmask.long.byte 0x4 8.--11. 1. "WRT_ERR,Write error" hexmask.long.byte 0x4 4.--7. 1. "REGION_BV,Region overflow boundary event caused by a burst transaction crossed a start or end of a region" newline hexmask.long.byte 0x4 0.--3. 1. "CTR_WKV,AES mode 0 enabled region violated Wrt Once Per Wrt Key rule" line.long 0x8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_is," hexmask.long.byte 0x8 12.--15. 1. "MAC_ERR,MAC error" hexmask.long.byte 0x8 8.--11. 1. "WRT_ERR,Write error" hexmask.long.byte 0x8 4.--7. 1. "REGION_BV,Region overflow boundary event caused by a burst transaction crossed a start or end of a region" newline hexmask.long.byte 0x8 0.--3. 1. "CTR_WKV,AES mode 0 enabled region violated Wrt Once Per Wrt Key rule" line.long 0xC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_ies," hexmask.long.byte 0xC 12.--15. 1. "MAC_ERR,MAC error" hexmask.long.byte 0xC 8.--11. 1. "WRT_ERR,Write error" hexmask.long.byte 0xC 4.--7. 1. "REGION_BV,Region overflow boundary event caused by a burst transaction crossed a start or end of a region" newline hexmask.long.byte 0xC 0.--3. 1. "CTR_WKV,AES mode 0 enabled region violated Wrt Once Per Wrt Key rule" line.long 0x10 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_iec," hexmask.long.byte 0x10 12.--15. 1. "MAC_ERR,MAC error" hexmask.long.byte 0x10 8.--11. 1. "WRT_ERR,Write error" hexmask.long.byte 0x10 4.--7. 1. "REGION_BV,Region overflow boundary event caused by a burst transaction crossed a start or end of a region" newline hexmask.long.byte 0x10 0.--3. 1. "CTR_WKV,AES mode 0 enabled region violated Wrt Once Per Wrt Key rule" line.long 0x14 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_ccfg," bitfld.long 0x14 31. "MASTER_EN_RD,This register controls the enabling the functionality of this IP Disabled and Bypass mode active" "0,1" bitfld.long 0x14 9. "ERROR_RESP_EN,This register controls the enabling the the ocp error response for mac errors" "0,1" bitfld.long 0x14 8. "OTFA_WAIT,This register allows the ability to stop accepting any new transactions from getting accepted and allow the current transactions to complete" "0,1" newline bitfld.long 0x14 6. "CACHE_ENABLE,MAC cache enable" "0,1" bitfld.long 0x14 5. "CACHE_EVICT_MODE,cache evict mode" "0,1" bitfld.long 0x14 4. "KEY_SIZE,Key Size 0 128 Bit 1 256 Bit" "0,1" newline hexmask.long.byte 0x14 0.--3. 1. "RD_WRT_OPT,This register defines the static allocation of the AES cores to read transactions. The remainder will be allocated to write transactions" line.long 0x18 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_cstatus," rbitfld.long 0x18 31. "BUSY,0 No transactions are active crypto or none crypto 1 One or more transactions are active crypto or none crypto" "0,1" rbitfld.long 0x18 30. "CRYPTO_BUSY,0 No transactions are active crypto or none crypto 1 One or more transactions are active crypto or none crypto" "0,1" hexmask.long.word 0x18 16.--29. 1. "RD_STALL_EVENT_CNT,rd stall event do to lack of eng" newline hexmask.long.word 0x18 0.--13. 1. "WRT_STALL_EVENT_CNT,wrt stall event do to lack of eng" line.long 0x1C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgcfg0," bitfld.long 0x1C 4. "WRT_PROTECT0,WRT protect" "0,1" bitfld.long 0x1C 2.--3. "MAC_MODE0,MAC mode" "0,1,2,3" bitfld.long 0x1C 0.--1. "AES_MODE0,AES mode" "0,1,2,3" line.long 0x20 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgmacst0," hexmask.long.tbyte 0x20 0.--19. 1. "M_START0,This defines the start of the mac buffer in 4KBytes steps" line.long 0x24 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgst0," hexmask.long.tbyte 0x24 0.--19. 1. "R_START0,This defines the start of the crypto region in 4KBytes steps" line.long 0x28 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgsi0," hexmask.long.tbyte 0x28 0.--19. 1. "R_SIZE0,This defines the size of the crypto region in 4KBytes steps" line.long 0x2C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye00," hexmask.long 0x2C 0.--31. 1. "R_KEY_E00,Key E" line.long 0x30 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye01," hexmask.long 0x30 0.--31. 1. "R_KEY_E01,Key E" line.long 0x34 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye02," hexmask.long 0x34 0.--31. 1. "R_KEY_E02,Key E" line.long 0x38 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye03," hexmask.long 0x38 0.--31. 1. "R_KEY_E03,Key E" line.long 0x3C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye04," hexmask.long 0x3C 0.--31. 1. "R_KEY_E04,Key E" line.long 0x40 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye05," hexmask.long 0x40 0.--31. 1. "R_KEY_E05,Key E" line.long 0x44 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye06," hexmask.long 0x44 0.--31. 1. "R_KEY_E06,Key E" line.long 0x48 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye07," hexmask.long 0x48 0.--31. 1. "R_KEY_E07,Key E" line.long 0x4C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep00," hexmask.long 0x4C 0.--31. 1. "R_KEY_EP00,Key EP" line.long 0x50 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep01," hexmask.long 0x50 0.--31. 1. "R_KEY_EP01,Key EP" line.long 0x54 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep02," hexmask.long 0x54 0.--31. 1. "R_KEY_EP02,Key EP" line.long 0x58 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep03," hexmask.long 0x58 0.--31. 1. "R_KEY_EP03,Key EP" line.long 0x5C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep04," hexmask.long 0x5C 0.--31. 1. "R_KEY_EP04,Key EP" line.long 0x60 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep05," hexmask.long 0x60 0.--31. 1. "R_KEY_EP05,Key EP" line.long 0x64 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep06," hexmask.long 0x64 0.--31. 1. "R_KEY_EP06,Key EP" line.long 0x68 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep07," hexmask.long 0x68 0.--31. 1. "R_KEY_EP07,Key EP" line.long 0x6C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya00," hexmask.long 0x6C 0.--31. 1. "R_KEY_A00,Key A" line.long 0x70 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya01," hexmask.long 0x70 0.--31. 1. "R_KEY_A01,Key A" line.long 0x74 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya02," hexmask.long 0x74 0.--31. 1. "R_KEY_A02,Key A" line.long 0x78 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya03," hexmask.long 0x78 0.--31. 1. "R_KEY_A03,Key A" line.long 0x7C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap00," hexmask.long 0x7C 0.--31. 1. "R_KEY_AP00,Key AP" line.long 0x80 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap01," hexmask.long 0x80 0.--31. 1. "R_KEY_AP01,Key AP" line.long 0x84 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap02," hexmask.long 0x84 0.--31. 1. "R_KEY_AP02,Key AP" line.long 0x88 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap03," hexmask.long 0x88 0.--31. 1. "R_KEY_AP03,Key AP" line.long 0x8C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv00," hexmask.long 0x8C 0.--31. 1. "R_IV00,IV" line.long 0x90 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv01," hexmask.long 0x90 0.--31. 1. "R_IV01,IV" line.long 0x94 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv02," hexmask.long 0x94 0.--31. 1. "R_IV02,IV" line.long 0x98 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv03," hexmask.long 0x98 0.--31. 1. "R_IV03,IV" line.long 0x9C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgcfg1," bitfld.long 0x9C 4. "WRT_PROTECT1,WRT protect" "0,1" bitfld.long 0x9C 2.--3. "MAC_MODE1,MAC mode" "0,1,2,3" bitfld.long 0x9C 0.--1. "AES_MODE1,AES mode" "0,1,2,3" line.long 0xA0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgmacst1," hexmask.long.tbyte 0xA0 0.--19. 1. "M_START1,This defines the start of the mac buffer in 4KBytes steps" line.long 0xA4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgst1," hexmask.long.tbyte 0xA4 0.--19. 1. "R_START1,This defines the start of the crypto region in 4KBytes steps" line.long 0xA8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgsi1," hexmask.long.tbyte 0xA8 0.--19. 1. "R_SIZE1,This defines the size of the crypto region in 4KBytes steps" line.long 0xAC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye10," hexmask.long 0xAC 0.--31. 1. "R_KEY_E10,Key E" line.long 0xB0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye11," hexmask.long 0xB0 0.--31. 1. "R_KEY_E11,Key E" line.long 0xB4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye12," hexmask.long 0xB4 0.--31. 1. "R_KEY_E12,Key E" line.long 0xB8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye13," hexmask.long 0xB8 0.--31. 1. "R_KEY_E13,Key E" line.long 0xBC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye14," hexmask.long 0xBC 0.--31. 1. "R_KEY_E14,Key E" line.long 0xC0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye15," hexmask.long 0xC0 0.--31. 1. "R_KEY_E15,Key E" line.long 0xC4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye16," hexmask.long 0xC4 0.--31. 1. "R_KEY_E16,Key E" line.long 0xC8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye17," hexmask.long 0xC8 0.--31. 1. "R_KEY_E17,Key E" line.long 0xCC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep10," hexmask.long 0xCC 0.--31. 1. "R_KEY_EP10,Key EP" line.long 0xD0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep11," hexmask.long 0xD0 0.--31. 1. "R_KEY_EP11,Key EP" line.long 0xD4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep12," hexmask.long 0xD4 0.--31. 1. "R_KEY_EP12,Key EP" line.long 0xD8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep13," hexmask.long 0xD8 0.--31. 1. "R_KEY_EP13,Key EP" line.long 0xDC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep14," hexmask.long 0xDC 0.--31. 1. "R_KEY_EP14,Key EP" line.long 0xE0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep15," hexmask.long 0xE0 0.--31. 1. "R_KEY_EP15,Key EP" line.long 0xE4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep16," hexmask.long 0xE4 0.--31. 1. "R_KEY_EP16,Key EP" line.long 0xE8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep17," hexmask.long 0xE8 0.--31. 1. "R_KEY_EP17,Key EP" line.long 0xEC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya10," hexmask.long 0xEC 0.--31. 1. "R_KEY_A10,Key A" line.long 0xF0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya11," hexmask.long 0xF0 0.--31. 1. "R_KEY_A11,Key A" line.long 0xF4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya12," hexmask.long 0xF4 0.--31. 1. "R_KEY_A12,Key A" line.long 0xF8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya13," hexmask.long 0xF8 0.--31. 1. "R_KEY_A13,Key A" line.long 0xFC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap10," hexmask.long 0xFC 0.--31. 1. "R_KEY_AP10,Key AP" line.long 0x100 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap11," hexmask.long 0x100 0.--31. 1. "R_KEY_AP11,Key AP" line.long 0x104 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap12," hexmask.long 0x104 0.--31. 1. "R_KEY_AP12,Key AP" line.long 0x108 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap13," hexmask.long 0x108 0.--31. 1. "R_KEY_AP13,Key AP" line.long 0x10C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv10," hexmask.long 0x10C 0.--31. 1. "R_IV10,IV" line.long 0x110 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv11," hexmask.long 0x110 0.--31. 1. "R_IV11,IV" line.long 0x114 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv12," hexmask.long 0x114 0.--31. 1. "R_IV12,IV" line.long 0x118 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv13," hexmask.long 0x118 0.--31. 1. "R_IV13,IV" line.long 0x11C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgcfg2," bitfld.long 0x11C 4. "WRT_PROTECT2,WRT protect" "0,1" bitfld.long 0x11C 2.--3. "MAC_MODE2,MAC mode" "0,1,2,3" bitfld.long 0x11C 0.--1. "AES_MODE2,AES mode" "0,1,2,3" line.long 0x120 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgmacst2," hexmask.long.tbyte 0x120 0.--19. 1. "M_START2,This defines the start of the mac buffer in 4KBytes steps" line.long 0x124 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgst2," hexmask.long.tbyte 0x124 0.--19. 1. "R_START2,This defines the start of the crypto region in 4KBytes steps" line.long 0x128 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgsi2," hexmask.long.tbyte 0x128 0.--19. 1. "R_SIZE2,This defines the size of the crypto region in 4KBytes steps" line.long 0x12C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye20," hexmask.long 0x12C 0.--31. 1. "R_KEY_E20,Key E" line.long 0x130 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye21," hexmask.long 0x130 0.--31. 1. "R_KEY_E21,Key E" line.long 0x134 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye22," hexmask.long 0x134 0.--31. 1. "R_KEY_E22,Key E" line.long 0x138 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye23," hexmask.long 0x138 0.--31. 1. "R_KEY_E23,Key E" line.long 0x13C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye24," hexmask.long 0x13C 0.--31. 1. "R_KEY_E24,Key E" line.long 0x140 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye25," hexmask.long 0x140 0.--31. 1. "R_KEY_E25,Key E" line.long 0x144 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye26," hexmask.long 0x144 0.--31. 1. "R_KEY_E26,Key E" line.long 0x148 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye27," hexmask.long 0x148 0.--31. 1. "R_KEY_E27,Key E" line.long 0x14C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep20," hexmask.long 0x14C 0.--31. 1. "R_KEY_EP20,Key EP" line.long 0x150 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep21," hexmask.long 0x150 0.--31. 1. "R_KEY_EP21,Key EP" line.long 0x154 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep22," hexmask.long 0x154 0.--31. 1. "R_KEY_EP22,Key EP" line.long 0x158 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep23," hexmask.long 0x158 0.--31. 1. "R_KEY_EP23,Key EP" line.long 0x15C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep24," hexmask.long 0x15C 0.--31. 1. "R_KEY_EP24,Key EP" line.long 0x160 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep25," hexmask.long 0x160 0.--31. 1. "R_KEY_EP25,Key EP" line.long 0x164 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep26," hexmask.long 0x164 0.--31. 1. "R_KEY_EP26,Key EP" line.long 0x168 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep27," hexmask.long 0x168 0.--31. 1. "R_KEY_EP27,Key EP" line.long 0x16C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya20," hexmask.long 0x16C 0.--31. 1. "R_KEY_A20,Key A" line.long 0x170 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya21," hexmask.long 0x170 0.--31. 1. "R_KEY_A21,Key A" line.long 0x174 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya22," hexmask.long 0x174 0.--31. 1. "R_KEY_A22,Key A" line.long 0x178 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya23," hexmask.long 0x178 0.--31. 1. "R_KEY_A23,Key A" line.long 0x17C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap20," hexmask.long 0x17C 0.--31. 1. "R_KEY_AP20,Key AP" line.long 0x180 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap21," hexmask.long 0x180 0.--31. 1. "R_KEY_AP21,Key AP" line.long 0x184 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap22," hexmask.long 0x184 0.--31. 1. "R_KEY_AP22,Key AP" line.long 0x188 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap23," hexmask.long 0x188 0.--31. 1. "R_KEY_AP23,Key AP" line.long 0x18C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv20," hexmask.long 0x18C 0.--31. 1. "R_IV20,IV" line.long 0x190 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv21," hexmask.long 0x190 0.--31. 1. "R_IV21,IV" line.long 0x194 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv22," hexmask.long 0x194 0.--31. 1. "R_IV22,IV" line.long 0x198 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv23," hexmask.long 0x198 0.--31. 1. "R_IV23,IV" line.long 0x19C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgcfg3," bitfld.long 0x19C 4. "WRT_PROTECT3,WRT protect" "0,1" bitfld.long 0x19C 2.--3. "MAC_MODE3,MAC mode" "0,1,2,3" bitfld.long 0x19C 0.--1. "AES_MODE3,AES mode" "0,1,2,3" line.long 0x1A0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgmacst3," hexmask.long.tbyte 0x1A0 0.--19. 1. "M_START3,This defines the start of the mac buffer in 4KBytes steps" line.long 0x1A4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgst3," hexmask.long.tbyte 0x1A4 0.--19. 1. "R_START3,This defines the start of the crypto region in 4KBytes steps" line.long 0x1A8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgsi3," hexmask.long.tbyte 0x1A8 0.--19. 1. "R_SIZE3,This defines the size of the crypto region in 4KBytes steps" line.long 0x1AC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye30," hexmask.long 0x1AC 0.--31. 1. "R_KEY_E30,Key E" line.long 0x1B0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye31," hexmask.long 0x1B0 0.--31. 1. "R_KEY_E31,Key E" line.long 0x1B4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye32," hexmask.long 0x1B4 0.--31. 1. "R_KEY_E32,Key E" line.long 0x1B8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye33," hexmask.long 0x1B8 0.--31. 1. "R_KEY_E33,Key E" line.long 0x1BC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye34," hexmask.long 0x1BC 0.--31. 1. "R_KEY_E34,Key E" line.long 0x1C0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye35," hexmask.long 0x1C0 0.--31. 1. "R_KEY_E35,Key E" line.long 0x1C4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye36," hexmask.long 0x1C4 0.--31. 1. "R_KEY_E36,Key E" line.long 0x1C8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye37," hexmask.long 0x1C8 0.--31. 1. "R_KEY_E37,Key E" line.long 0x1CC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep30," hexmask.long 0x1CC 0.--31. 1. "R_KEY_EP30,Key EP" line.long 0x1D0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep31," hexmask.long 0x1D0 0.--31. 1. "R_KEY_EP31,Key EP" line.long 0x1D4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep32," hexmask.long 0x1D4 0.--31. 1. "R_KEY_EP32,Key EP" line.long 0x1D8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep33," hexmask.long 0x1D8 0.--31. 1. "R_KEY_EP33,Key EP" line.long 0x1DC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep34," hexmask.long 0x1DC 0.--31. 1. "R_KEY_EP34,Key EP" line.long 0x1E0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep35," hexmask.long 0x1E0 0.--31. 1. "R_KEY_EP35,Key EP" line.long 0x1E4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep36," hexmask.long 0x1E4 0.--31. 1. "R_KEY_EP36,Key EP" line.long 0x1E8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep37," hexmask.long 0x1E8 0.--31. 1. "R_KEY_EP37,Key EP" line.long 0x1EC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya30," hexmask.long 0x1EC 0.--31. 1. "R_KEY_A30,Key A" line.long 0x1F0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya31," hexmask.long 0x1F0 0.--31. 1. "R_KEY_A31,Key A" line.long 0x1F4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya32," hexmask.long 0x1F4 0.--31. 1. "R_KEY_A32,Key A" line.long 0x1F8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya33," hexmask.long 0x1F8 0.--31. 1. "R_KEY_A33,Key A" line.long 0x1FC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap30," hexmask.long 0x1FC 0.--31. 1. "R_KEY_AP30,Key AP" line.long 0x200 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap31," hexmask.long 0x200 0.--31. 1. "R_KEY_AP31,Key AP" line.long 0x204 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap32," hexmask.long 0x204 0.--31. 1. "R_KEY_AP32,Key AP" line.long 0x208 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap33," hexmask.long 0x208 0.--31. 1. "R_KEY_AP33,Key AP" line.long 0x20C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv30," hexmask.long 0x20C 0.--31. 1. "R_IV30,IV" line.long 0x210 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv31," hexmask.long 0x210 0.--31. 1. "R_IV31,IV" line.long 0x214 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv32," hexmask.long 0x214 0.--31. 1. "R_IV32,IV" line.long 0x218 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv33," hexmask.long 0x218 0.--31. 1. "R_IV33,IV" rgroup.long 0x220++0xF line.long 0x0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_irqaddinfo0," hexmask.long 0x0 0.--31. 1. "IRQ_MADDR,Master Address which caused the event" line.long 0x4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_irqaddinfo1," hexmask.long.byte 0x4 14.--17. 1. "IRQ_MLEN,Master LENGTH which caused the event" bitfld.long 0x4 11.--13. "IRQ_MSEQ,Master SEQ which caused the event" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "IRQ_MCMD,Master CMD which caused the event" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--7. 1. "IRQ_MID,Master TAG ID which caused the event" line.long 0x8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_maccacheinfo," hexmask.long.word 0x8 0.--15. 1. "CACHE_MISS_EVENT_CNT,MAC Cache Miss event cnt" line.long 0xC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rmwrmcnt," hexmask.long.word 0xC 16.--31. 1. "RM_EVENT_CNT,RM event cnt" hexmask.long.word 0xC 0.--15. 1. "RMW_EVENT_CNT,RMW event cnt" tree.end tree.end tree "MCU_FSS0_HYPERBUS1P0_0" tree "MCU_FSS0_HYPERBUS1P0_0_HPB_CTRL (MCU_FSS0_HYPERBUS1P0_0_HPB_CTRL)" base ad:0x47034000 rgroup.long 0x0++0x3 line.long 0x0 "HB__HPB_CFG__WRAP__CORE_CFG__CORE_CFG_REG_CSR,Controller Status Register to access the internal status of HyperBus Memory Controller IP" hexmask.long.byte 0x0 27.--31. 1. "RFU3,This field is reserved for future use" newline bitfld.long 0x0 26. "WRSTOERR,Write RSTO error. This bit indicates whether HyperBus memory is under reset state in the latest write operation.When this bit is set HyperBus Memory Controller IP responds by AXI SLVERR.0-Normal operation 1- HyperBus memory is under reset" "0: Normal operation,1: HyperBus memory is under reset" newline bitfld.long 0x0 25. "WTRSERR,Write Transaction Error. This bit indicates whether AXI protocol is acceptable by HyperBus Memory Controller IP in the latest write transaction.When this bit is set HyperBus Memory Controller IP responds by AXI SLVERR.0-Normal operation 1- This.." "0: Normal operation,1: This protocol is not supported" newline bitfld.long 0x0 24. "WDECERR,Write Decode Error. This bit indicates whether access address is acceptable in the latest write transaction.When this bit is set HyperBus Memory Controller IP responds by AXI DECERR.0-Normal operation. 1- Access address is not reachable" "0: Normal operation,1: Access address is not reachable" newline hexmask.long.byte 0x0 17.--23. 1. "RFU2,This field is reserved for future use" newline bitfld.long 0x0 16. "WACT,Write is Active. This bit indicates whether write transaction is in progress or not.0- Write is idle 1 - Write is active.When receiving write request on write address channel this bit becomes 1. When retrieving response signaling on write response.." "0: Write is idle,1: Write is active" newline hexmask.long.byte 0x0 12.--15. 1. "RFU1,This field is reserved for future use" newline bitfld.long 0x0 11. "RDSSTALL,RDS Stall. This bit indicates whether read data transfer from HyperBus memory is stalled [RDS remains LOW] in the latest read transaction.When this bit is set HyperBus Memory Controller IP responds by AXI SLVERR." "0,1" newline bitfld.long 0x0 10. "RRSTOERR,Read RSTO error. This bit indicates whether HyperBus memory is under reset state in the latest read operation.When this bit is set HyperBus Memory Controller IP responds by AXI SLVERR.0 -Normal operation 1 -HyperBus memory is under reset" "0: Normal operation,1: HyperBus memory is under reset" newline bitfld.long 0x0 9. "RTRSERR,Read Transaction Error. This bit indicates whether AXI protocol is acceptable by HyperBus Memory Controller IP in the latest read transaction.When this bit is set HyperBus Memory Controller IP responds by AXI SLVERR.0- Normal operation 1- This.." "0: Normal operation,1: This protocol is not supported" newline bitfld.long 0x0 8. "RDECERR,Read Decode Error. This bit indicates whether access address is acceptable in the latest read transaction.When this bit is set HyperBus Memory Controller IP responds by AXI DECERR.0 -Normal operation 1- Access address is not reachable" "0: Normal operation,1: Access address is not reachable" newline hexmask.long.byte 0x0 1.--7. 1. "RFU0,This field is reserved for future use" newline bitfld.long 0x0 0. "RACT,Read is Active. This bit indicates whether read transaction is in progress or not. 0 - Read is idle 1-Read is active. When receiving read request on read address channel this bit becomes 1. When retrieving all requested data on read data channel .." "0: Read is idle,1: Read is active" rgroup.long 0x4++0x3 line.long 0x0 "HB__HPB_CFG__WRAP__CORE_CFG__CORE_CFG_REG_IER,HyperBus Memory Controller IP outputs optional interrupt signal by condition enabled by this register" bitfld.long 0x0 31. "INTP,Interrupt Polarity Control. This bit is used to choose the polarity of optional interrupt signal [IENOn].0 -IENOn signal is active low.1 -IENOn signal is active high. [Reversed mode.]" "0: IENOn signal is active low,1: IENOn signal is active high" newline hexmask.long 0x0 1.--30. 1. "RFU4,This field is reserved for future use" newline bitfld.long 0x0 0. "RPCINTE,HyperBus Memory Interrupt Enable.0 - Disable interrupt.1 - Enable interrupt by INT# signal of HyperBus memory." "0: Disable interrupt,1: Enable interrupt by INT# signal of HyperBus memory" rgroup.long 0x8++0x3 line.long 0x0 "HB__HPB_CFG__WRAP__CORE_CFG__CORE_CFG_REG_ISR,Interrupt status register" hexmask.long 0x0 1.--31. 1. "RFU5,This field is reserved for future use" newline bitfld.long 0x0 0. "RPCINTS,HyperBus Memory Interrupt.0 -No interrupt.1 - This bit displays interrupt from INT# signal of HyperBus memory." "0: No interrupt,1: This bit displays interrupt from INT# signal of.." rgroup.long 0x10++0x3 line.long 0x0 "HB__HPB_CFG__WRAP__CORE_CFG__CORE_CFG_REG_MBAR,Memory Base Address Register for device connected to CS#" hexmask.long.byte 0x0 24.--31. 1. "A_MSB,MSB 8 bit of the base address of addressable region to HyperBus memory" newline hexmask.long.tbyte 0x0 0.--23. 1. "A_LSB,Since register can be set in 16M bytes boundary lower 24 bit is fixed to 0 if read this field will always return 0" rgroup.long 0x20++0x3 line.long 0x0 "HB__HPB_CFG__WRAP__CORE_CFG__CORE_CFG_REG_MCR,Memory configuration register for CS#" bitfld.long 0x0 31. "MAXEN,Maximum length Enable 0: No configurable CS# low time 1: Configurable CS# low time When this bit 1 CS# low time can be configurable by MAXLEN bit." "0: No configurable CS# low time,1: Configurable CS# low time When this bit 1" newline hexmask.long.byte 0x0 27.--30. 1. "RFU8,This field is reserved for future use" newline hexmask.long.word 0x0 18.--26. 1. "MAXLEN,Maximum Length This bit indicates maximum read/write transaction length to memory. This bit is ignored when MAXEN bit is 0. 000000000: 2 Byte [1 HyperBus CK] 000000001: 4 Byte [2 HyperBus CK] 000000010: 6 Byte [3 HyperBus CK] 111111111: 1024 Byte.." newline bitfld.long 0x0 17. "TCMO,True Continuous Merge Option. 0 : No merging WRAP and INCR. 1 : Merging WRAP and INCR. Note that this function can be used with the HyperFlash with specific function. Please confirm whether it is corresponding HyperFlash before enabling this.." "0: No merging WRAP and INCR,1: Merging WRAP and INCR" newline bitfld.long 0x0 16. "ACS,Asymmetry Cache Support. 0 : No asymmetry cache system support. 1 : Asymmetry cache system support. This function should be disabled if the HyperBus memory itself supports the asymmetry cache system." "0: No asymmetry cache system support,1: Asymmetry cache system support" newline hexmask.long.word 0x0 6.--15. 1. "RFU7,This field is reserved for future use" newline bitfld.long 0x0 5. "CRT,Configuration Register Target. 0: Memory space 1: CR space . This bit indicates whether the read or write operation accesses the memory or CR space. This bit is mapped to CA-46 bit in HyperRAM. When using HyperFlash " "0: Memory space,1: CR space" newline bitfld.long 0x0 4. "DEVTYPE,Device Type. 0: HyperFlash 1: HyperRAM. Device type for control target" "0: HyperFlash,1: HyperRAM" newline rbitfld.long 0x0 2.--3. "RFU6,This field is reserved for future use" "0,1,2,3" newline bitfld.long 0x0 0.--1. "WRAPSIZE,Wrap Size.The wrap burst length of HyperBus memory. This bit is ignored when the asymmetry cache support bit is 0. When the asymmetry cache support is 1 this bit should be set the same as wrap size of configuration register in HyperBus memory." "0: Reserved,?,?,?" rgroup.long 0x30++0x3 line.long 0x0 "HB__HPB_CFG__WRAP__CORE_CFG__CORE_CFG_REG_MTR,CS# Memory Timing Register" hexmask.long.byte 0x0 28.--31. 1. "RCSHI,Read Chip Select High Between Operations. This bit indicates CS# high time for read between operations. 0x0 corresponds to 1.5 clock cycle 0xF corresponds to 16.5 clock cycle." newline hexmask.long.byte 0x0 24.--27. 1. "WCSHI,Write Chip Select High Between Operations. This bit indicates CS# high time for write between operations. 0x0 corresponds to 1.5 clock cycle 0xF corresponds to 16.5 clock cycle." newline hexmask.long.byte 0x0 20.--23. 1. "RCSS,Read Chip Select Setup to next CK rising edge. This bit indicates CS# setup time for read from CS# assertion. 0x0 corresponds to 1 clock cycle 0xF corresponds to 16 clock cycle." newline hexmask.long.byte 0x0 16.--19. 1. "WCSS,Write Chip Select Setup to next CK rising edge. This bit indicates CS# setup time for write from CS# assertion. 0x0 corresponds to 1 clock cycle 0xF corresponds to 16 clock cycle" newline hexmask.long.byte 0x0 12.--15. 1. "RCSH,Read Chip Select Hold after CK falling edge. This bit indicates CS# hold time for read to CS# de-assertion. 0x0 corresponds to 1 clock cycle 0xF corresponds to 16 clock cycle." newline hexmask.long.byte 0x0 8.--11. 1. "WCSH,Write Chip Select Hold after CK falling edge. This bit indicates CS# hold time for write to CS# de-assertion. 0x0 corresponds to 1 clock cycle 0xF corresponding to 16 clock cycle" newline hexmask.long.byte 0x0 4.--7. 1. "RFU12,This field is reserved for future use" newline hexmask.long.byte 0x0 0.--3. 1. "LTCY,Latency Cycle. Only uses in HyperRAM. This bit indicates initial latency code for read/write access. This bit is ignored when MCRX.DEVTYPE is 0 [HyperFlash]. 0000 - 5 clock latency 0001 - 6 clock latency 0010 - Reserved 1101 - Reserved 1110 - 3.." rgroup.long 0x40++0xB line.long 0x0 "HB__HPB_CFG__WRAP__CORE_CFG__CORE_CFG_REG_GPOR,General Purpose Output Register" hexmask.long 0x0 2.--31. 1. "RFU14,This field is reserved for future use" newline bitfld.long 0x0 0.--1. "GPO,General Purpose Output interface. 0: Output signal polarity is LOW. 1: Output signal polarity is HIGH." "0: Output signal polarity is LOW,1: Output signal polarity is HIGH,?,?" line.long 0x4 "HB__HPB_CFG__WRAP__CORE_CFG__CORE_CFG_REG_WPR,Write Protection Register" hexmask.long 0x4 1.--31. 1. "RFU15,This field is reserved for future use" newline bitfld.long 0x4 0. "WP,Write Protection Control. 0 : Not Protected. WP# signal is HIGH. 1 : Protected. WP# signal is LOW." "0: Not Protected,1: Protected" line.long 0x8 "HB__HPB_CFG__WRAP__CORE_CFG__CORE_CFG_REG_LBR,Loop Back Register" hexmask.long 0x8 1.--31. 1. "RFU16,This field is reserved for future use" newline bitfld.long 0x8 0. "LOOPBACK,The write transaction data written on AXI bus is looped back as the read data from RPC bus. The loop-back is performed between W DAT FIFO and R DAT FIFO in AXI interface controller. 0 :Disable loopback. 1 :Enable loopback." "0: Disable loopback,1: Enable loopback" tree.end tree "MCU_FSS0_HYPERBUS1P0_0_HPB_ECC_AGGR (MCU_FSS0_HYPERBUS1P0_0_HPB_ECC_AGGR)" base ad:0x47060000 rgroup.long 0x0++0x3 line.long 0x0 "HB__HPB_CFG__WRAP__ECC_AGGR_CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "HB__HPB_CFG__WRAP__ECC_AGGR_CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "HB__HPB_CFG__WRAP__ECC_AGGR_CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "HB__HPB_CFG__WRAP__ECC_AGGR_CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "HB__HPB_CFG__WRAP__ECC_AGGR_CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "HB__HPB_CFG__WRAP__ECC_AGGR_CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 14. "MEM_ARID_FIFO_PEND,Interrupt Pending Status for mem_arid_fifo_pend" "0,1" bitfld.long 0x4 13. "MEM_AR_FIFO_PEND,Interrupt Pending Status for mem_ar_fifo_pend" "0,1" newline bitfld.long 0x4 12. "MEM_AWID1_FIFO_PEND,Interrupt Pending Status for mem_awid1_fifo_pend" "0,1" bitfld.long 0x4 11. "MEM_WID1_FIFO_PEND,Interrupt Pending Status for mem_wid1_fifo_pend" "0,1" newline bitfld.long 0x4 10. "MEM_AW1_FIFO_PEND,Interrupt Pending Status for mem_aw1_fifo_pend" "0,1" bitfld.long 0x4 9. "MEM_AWID0_FIFO_PEND,Interrupt Pending Status for mem_awid0_fifo_pend" "0,1" newline bitfld.long 0x4 8. "MEM_WID0_FIFO_PEND,Interrupt Pending Status for mem_wid0_fifo_pend" "0,1" bitfld.long 0x4 7. "MEM_AW0_FIFO_PEND,Interrupt Pending Status for mem_aw0_fifo_pend" "0,1" newline bitfld.long 0x4 6. "MEM_RX_FIFO_PEND,Interrupt Pending Status for mem_rx_fifo_pend" "0,1" bitfld.long 0x4 5. "MEM_RDAT_FIFO_PEND,Interrupt Pending Status for mem_rdat_fifo_pend" "0,1" newline bitfld.long 0x4 4. "MEM_BDAT1_FIFO_PEND,Interrupt Pending Status for mem_bdat1_fifo_pend" "0,1" bitfld.long 0x4 3. "MEM_BDAT0_FIFO_PEND,Interrupt Pending Status for mem_bdat0_fifo_pend" "0,1" newline bitfld.long 0x4 2. "MEM_WDAT1_FIFO_PEND,Interrupt Pending Status for mem_wdat1_fifo_pend" "0,1" bitfld.long 0x4 1. "MEM_WDAT0_FIFO_PEND,Interrupt Pending Status for mem_wdat0_fifo_pend" "0,1" newline bitfld.long 0x4 0. "MEM_ADR_FIFO_PEND,Interrupt Pending Status for mem_adr_fifo_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "HB__HPB_CFG__WRAP__ECC_AGGR_CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 14. "MEM_ARID_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_arid_fifo_pend" "0,1" bitfld.long 0x0 13. "MEM_AR_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_ar_fifo_pend" "0,1" newline bitfld.long 0x0 12. "MEM_AWID1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_awid1_fifo_pend" "0,1" bitfld.long 0x0 11. "MEM_WID1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wid1_fifo_pend" "0,1" newline bitfld.long 0x0 10. "MEM_AW1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_aw1_fifo_pend" "0,1" bitfld.long 0x0 9. "MEM_AWID0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_awid0_fifo_pend" "0,1" newline bitfld.long 0x0 8. "MEM_WID0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wid0_fifo_pend" "0,1" bitfld.long 0x0 7. "MEM_AW0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_aw0_fifo_pend" "0,1" newline bitfld.long 0x0 6. "MEM_RX_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_rx_fifo_pend" "0,1" bitfld.long 0x0 5. "MEM_RDAT_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_rdat_fifo_pend" "0,1" newline bitfld.long 0x0 4. "MEM_BDAT1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_bdat1_fifo_pend" "0,1" bitfld.long 0x0 3. "MEM_BDAT0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_bdat0_fifo_pend" "0,1" newline bitfld.long 0x0 2. "MEM_WDAT1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wdat1_fifo_pend" "0,1" bitfld.long 0x0 1. "MEM_WDAT0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wdat0_fifo_pend" "0,1" newline bitfld.long 0x0 0. "MEM_ADR_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_adr_fifo_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "HB__HPB_CFG__WRAP__ECC_AGGR_CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 14. "MEM_ARID_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_arid_fifo_pend" "0,1" bitfld.long 0x0 13. "MEM_AR_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_ar_fifo_pend" "0,1" newline bitfld.long 0x0 12. "MEM_AWID1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_awid1_fifo_pend" "0,1" bitfld.long 0x0 11. "MEM_WID1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wid1_fifo_pend" "0,1" newline bitfld.long 0x0 10. "MEM_AW1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_aw1_fifo_pend" "0,1" bitfld.long 0x0 9. "MEM_AWID0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_awid0_fifo_pend" "0,1" newline bitfld.long 0x0 8. "MEM_WID0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wid0_fifo_pend" "0,1" bitfld.long 0x0 7. "MEM_AW0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_aw0_fifo_pend" "0,1" newline bitfld.long 0x0 6. "MEM_RX_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_rx_fifo_pend" "0,1" bitfld.long 0x0 5. "MEM_RDAT_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_rdat_fifo_pend" "0,1" newline bitfld.long 0x0 4. "MEM_BDAT1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_bdat1_fifo_pend" "0,1" bitfld.long 0x0 3. "MEM_BDAT0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_bdat0_fifo_pend" "0,1" newline bitfld.long 0x0 2. "MEM_WDAT1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wdat1_fifo_pend" "0,1" bitfld.long 0x0 1. "MEM_WDAT0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wdat0_fifo_pend" "0,1" newline bitfld.long 0x0 0. "MEM_ADR_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_adr_fifo_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "HB__HPB_CFG__WRAP__ECC_AGGR_CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "HB__HPB_CFG__WRAP__ECC_AGGR_CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 14. "MEM_ARID_FIFO_PEND,Interrupt Pending Status for mem_arid_fifo_pend" "0,1" bitfld.long 0x4 13. "MEM_AR_FIFO_PEND,Interrupt Pending Status for mem_ar_fifo_pend" "0,1" newline bitfld.long 0x4 12. "MEM_AWID1_FIFO_PEND,Interrupt Pending Status for mem_awid1_fifo_pend" "0,1" bitfld.long 0x4 11. "MEM_WID1_FIFO_PEND,Interrupt Pending Status for mem_wid1_fifo_pend" "0,1" newline bitfld.long 0x4 10. "MEM_AW1_FIFO_PEND,Interrupt Pending Status for mem_aw1_fifo_pend" "0,1" bitfld.long 0x4 9. "MEM_AWID0_FIFO_PEND,Interrupt Pending Status for mem_awid0_fifo_pend" "0,1" newline bitfld.long 0x4 8. "MEM_WID0_FIFO_PEND,Interrupt Pending Status for mem_wid0_fifo_pend" "0,1" bitfld.long 0x4 7. "MEM_AW0_FIFO_PEND,Interrupt Pending Status for mem_aw0_fifo_pend" "0,1" newline bitfld.long 0x4 6. "MEM_RX_FIFO_PEND,Interrupt Pending Status for mem_rx_fifo_pend" "0,1" bitfld.long 0x4 5. "MEM_RDAT_FIFO_PEND,Interrupt Pending Status for mem_rdat_fifo_pend" "0,1" newline bitfld.long 0x4 4. "MEM_BDAT1_FIFO_PEND,Interrupt Pending Status for mem_bdat1_fifo_pend" "0,1" bitfld.long 0x4 3. "MEM_BDAT0_FIFO_PEND,Interrupt Pending Status for mem_bdat0_fifo_pend" "0,1" newline bitfld.long 0x4 2. "MEM_WDAT1_FIFO_PEND,Interrupt Pending Status for mem_wdat1_fifo_pend" "0,1" bitfld.long 0x4 1. "MEM_WDAT0_FIFO_PEND,Interrupt Pending Status for mem_wdat0_fifo_pend" "0,1" newline bitfld.long 0x4 0. "MEM_ADR_FIFO_PEND,Interrupt Pending Status for mem_adr_fifo_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "HB__HPB_CFG__WRAP__ECC_AGGR_CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 14. "MEM_ARID_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_arid_fifo_pend" "0,1" bitfld.long 0x0 13. "MEM_AR_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_ar_fifo_pend" "0,1" newline bitfld.long 0x0 12. "MEM_AWID1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_awid1_fifo_pend" "0,1" bitfld.long 0x0 11. "MEM_WID1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wid1_fifo_pend" "0,1" newline bitfld.long 0x0 10. "MEM_AW1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_aw1_fifo_pend" "0,1" bitfld.long 0x0 9. "MEM_AWID0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_awid0_fifo_pend" "0,1" newline bitfld.long 0x0 8. "MEM_WID0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wid0_fifo_pend" "0,1" bitfld.long 0x0 7. "MEM_AW0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_aw0_fifo_pend" "0,1" newline bitfld.long 0x0 6. "MEM_RX_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_rx_fifo_pend" "0,1" bitfld.long 0x0 5. "MEM_RDAT_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_rdat_fifo_pend" "0,1" newline bitfld.long 0x0 4. "MEM_BDAT1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_bdat1_fifo_pend" "0,1" bitfld.long 0x0 3. "MEM_BDAT0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_bdat0_fifo_pend" "0,1" newline bitfld.long 0x0 2. "MEM_WDAT1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wdat1_fifo_pend" "0,1" bitfld.long 0x0 1. "MEM_WDAT0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wdat0_fifo_pend" "0,1" newline bitfld.long 0x0 0. "MEM_ADR_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_adr_fifo_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "HB__HPB_CFG__WRAP__ECC_AGGR_CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 14. "MEM_ARID_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_arid_fifo_pend" "0,1" bitfld.long 0x0 13. "MEM_AR_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_ar_fifo_pend" "0,1" newline bitfld.long 0x0 12. "MEM_AWID1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_awid1_fifo_pend" "0,1" bitfld.long 0x0 11. "MEM_WID1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wid1_fifo_pend" "0,1" newline bitfld.long 0x0 10. "MEM_AW1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_aw1_fifo_pend" "0,1" bitfld.long 0x0 9. "MEM_AWID0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_awid0_fifo_pend" "0,1" newline bitfld.long 0x0 8. "MEM_WID0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wid0_fifo_pend" "0,1" bitfld.long 0x0 7. "MEM_AW0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_aw0_fifo_pend" "0,1" newline bitfld.long 0x0 6. "MEM_RX_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_rx_fifo_pend" "0,1" bitfld.long 0x0 5. "MEM_RDAT_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_rdat_fifo_pend" "0,1" newline bitfld.long 0x0 4. "MEM_BDAT1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_bdat1_fifo_pend" "0,1" bitfld.long 0x0 3. "MEM_BDAT0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_bdat0_fifo_pend" "0,1" newline bitfld.long 0x0 2. "MEM_WDAT1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wdat1_fifo_pend" "0,1" bitfld.long 0x0 1. "MEM_WDAT0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wdat0_fifo_pend" "0,1" newline bitfld.long 0x0 0. "MEM_ADR_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_adr_fifo_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "HB__HPB_CFG__WRAP__ECC_AGGR_CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "HB__HPB_CFG__WRAP__ECC_AGGR_CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "HB__HPB_CFG__WRAP__ECC_AGGR_CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "HB__HPB_CFG__WRAP__ECC_AGGR_CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCU_FSS0_HYPERBUS1P0_0_HPB_SS_CFG (MCU_FSS0_HYPERBUS1P0_0_HPB_SS_CFG)" base ad:0x47030000 rgroup.long 0x0++0xB line.long 0x0 "HB__HPB_CFG__SYS__SS_CFG__SS_CFG_REG_REVISION_REG,The Revision Register contains the major and minor revisions for the module" hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release" bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.long 0x4 "HB__HPB_CFG__SYS__SS_CFG__SS_CFG_REG_DLL_STAT_REG,DLL status register" hexmask.long.word 0x4 2.--10. 1. "MDLL_CODE,MDLL code. The slave delay line length that is currently enabled is determined by the MDLL code value" bitfld.long 0x4 1. "SDL_LOCK,SDL lock. When this bit is set it indicates that the slave delay line in the MDLL is locked." "0,1" bitfld.long 0x4 0. "MDLL_LOCK,MDLL lock. When this bit is set it indicates that the master delay line in the MDLL is locked." "0,1" line.long 0x8 "HB__HPB_CFG__SYS__SS_CFG__SS_CFG_REG_RAM_STAT_REG,RAM status register" bitfld.long 0x8 0. "INIT_DONE,FIFO RAM initialization done. When this bit is set t indicates that all the FIFO RAM auto initialization is complete. Software should check that this bit is set before initiating transactions to the external memory" "0,1" tree.end tree.end tree "MCU_FSS0_OSPI" tree "MCU_FSS0_OSPI_0" tree "MCU_FSS0_OSPI_0_OSPI0_CTRL (MCU_FSS0_OSPI_0_OSPI0_CTRL)" base ad:0x47040000 rgroup.long 0x0++0x2B line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_config_reg,Octal-SPI Configuration Register" rbitfld.long 0x0 31. "IDLE_FLD,Serial interface and low level SPI pipeline is IDLE: This is a STATUS read-only bit. Note this is a retimed signal so there will be some inherent delay on the generation of this status signal." "0,1" newline bitfld.long 0x0 30. "DUAL_BYTE_OPCODE_EN_FLD,Dual-byte Opcode Mode enable bit This bit is to be set in case the target Flash Device supports dual byte opcode [i.e. Macronix MX25]. It is applicable for Octal I/O Mode or Protocol only so should be set back to low if the device.." "0,1" newline bitfld.long 0x0 29. "CRC_ENABLE_FLD,CRC enable bit This bit is to be set in case the target Flash Device supports CRC [Macronix MX25]. It is applicable for Octal DDR Protocol only so should be set back to low if the device is configured to work in another SPI Mode." "0,1" newline bitfld.long 0x0 25. "PIPELINE_PHY_FLD,Pipeline PHY Mode enable: This bit is relevant only for configuration with PHY Module. It should be asserted to 1 between consecutive PHY pipeline reads transfers and de-asserted to 0 otherwise." "0,1" newline bitfld.long 0x0 24. "ENABLE_DTR_PROTOCOL_FLD,Enable DTR Protocol: This bit should be set if device is configured to work in DTR protocol." "0,1" newline bitfld.long 0x0 23. "ENABLE_AHB_DECODER_FLD,Enable AHB Decoder: Value=0 : Active slave is selected based on Peripheral Chip Select Lines [bits [13:10]]. Value=1 Active slave is selected based on actual AHB address [the partition for each device is calculated with respect to.." "0: Active slave is selected based on Peripheral..,?" newline hexmask.long.byte 0x0 19.--22. 1. "MSTR_BAUD_DIV_FLD,Master Mode Baud Rate Divisor: SPI baud rate = [master reference clock] baud_rate_divisor" newline bitfld.long 0x0 18. "ENTER_XIP_MODE_IMM_FLD,Enter XIP Mode immediately: Value=0 : If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : Operate the device in XIP mode immediately Use this register when the.." "0: If XIP is enabled,1: Operate the device in XIP mode immediately Use.." newline bitfld.long 0x0 17. "ENTER_XIP_MODE_FLD,Enter XIP Mode on next READ: Value=0 : If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : If XIP is disabled then setting to ?1? will inform the controller that the.." "0: If XIP is enabled,1: If XIP is disabled" newline bitfld.long 0x0 16. "ENB_AHB_ADDR_REMAP_FLD,Enable AHB Address Re-mapping: [Direct Access Mode Only] When set to 1 the incoming AHB address will be adapted and sent to the FLASH device as [address + N] where N is the value stored in the remap address register." "0,1" newline bitfld.long 0x0 15. "ENB_DMA_IF_FLD,Enable DMA Peripheral Interface: Set to 1 to enable the DMA handshaking logic. When enabled the controller will trigger DMA transfer requests via the DMA peripheral interface. Set to 0 to disable" "0,1" newline bitfld.long 0x0 14. "WR_PROT_FLASH_FLD,Write Protect Flash Pin: Set to drive the Write Protect pin of the FLASH device. This is resynchronized to the generated memory clock as necessary." "0,1" newline hexmask.long.byte 0x0 10.--13. 1. "PERIPH_CS_LINES_FLD,Peripheral Chip Select Lines: Peripheral chip select lines If pdec = 0 ss[3:0] are output thus: ss[3:0] n_ss_out[3:0] xxx0 1110 xx01 1101 x011 1011 0111 0111 1111 1111 [no peripheral selected] else ss[3:0] directly drives n_ss_out[3:0]" newline bitfld.long 0x0 9. "PERIPH_SEL_DEC_FLD,Peripheral select decode: 0 : only 1 of 4 selects n_ss_out[3:0] is active 1 : allow external 4-to-16 decode [n_ss_out = ss]" "0: only 1 of 4 selects n_ss_out[3:0] is active,1: allow external 4-to-16 decode [n_ss_out = ss]" newline bitfld.long 0x0 8. "ENB_LEGACY_IP_MODE_FLD,Legacy IP Mode Enable: 0 : Use Direct Access Controller/Indirect Access Controller 1 : legacy Mode is enabled. In this mode any write to the controller via the AHB interface is serialized and sent to the FLASH device. Any valid.." "0: Use Direct Access Controller/Indirect Access..,1: legacy Mode is enabled" newline bitfld.long 0x0 7. "ENB_DIR_ACC_CTLR_FLD,Enable Direct Access Controller: 0 : disable the Direct Access Controller once current transfer of the data word [FF_W] is complete. 1 : enable the Direct Access Controller When the Direct Access Controller and Indirect Access.." "0: disable the Direct Access Controller once..,1: enable the Direct Access Controller When the.." newline bitfld.long 0x0 6. "RESET_CFG_FLD,RESET pin configuration: 0 = RESET feature on DQ3 pin of the device 1 = RESET feature on dedicated pin of the device [controlling of 5th bit influences on reset_out output]" "0: RESET feature on DQ3 pin of the device,1: RESET feature on dedicated pin of the device.." newline bitfld.long 0x0 5. "RESET_PIN_FLD,Set to drive the RESET pin of the FLASH device and reset for de-activation of the RESET pin feature" "0,1" newline bitfld.long 0x0 4. "HOLD_PIN_FLD,Set to drive the HOLD pin of the FLASH device and reset for de-activation of the HOLD pin feature" "0,1" newline bitfld.long 0x0 3. "PHY_MODE_ENABLE_FLD,PHY mode enable: When enabled the controller is informed that PHY Module is to be used for handling SPI transfers. This bit is relevant only for configuration with PHY Module." "0,1" newline bitfld.long 0x0 2. "SEL_CLK_PHASE_FLD,Select Clock Phase: Selects whether the clock is in an active or inactive phase outside the SPI word. 0 : the SPI clock is active outside the word 1 : the SPI clock is inactive outside the word" "0: the SPI clock is active outside the word,1: the SPI clock is inactive outside the word" newline bitfld.long 0x0 1. "SEL_CLK_POL_FLD,Clock polarity outside SPI word: 0 : the SPI clock is quiescent low 1 : the SPI clock is quiescent high" "0: the SPI clock is quiescent low,1: the SPI clock is quiescent high" newline bitfld.long 0x0 0. "ENB_SPI_FLD,Octal-SPI Enable: 0 : disable the Octal-SPI once current transfer of the data word [FF_W] is complete. 1 : enable the Octal-SPI when spi_enable = 0 all output enables are inactive and all pins are set to input mode." "0: disable the Octal-SPI,1: enable the Octal-SPI" line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_instr_rd_config_reg,Device Read Instruction Configuration Register" hexmask.long.byte 0x4 24.--28. 1. "DUMMY_RD_CLK_CYCLES_FLD,Dummy Read Clock Cycles: Number of dummy clock cycles required by device for read instruction." newline bitfld.long 0x4 20. "MODE_BIT_ENABLE_FLD,Mode Bit Enable: Set this field to 1 to ensure that the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes." "0,1" newline bitfld.long 0x4 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers DQ0 and DQ1 are used as both.." "0: SIO mode data is shifted to the device on DQ0..,1: Used for Dual Input/Output instructions,2: Used for Quad Input/Output instructions,3: Used for Quad Input/Output instructions" newline bitfld.long 0x4 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0 DQ1 DQ2.." "0: Addresses can be shifted to the device on DQ0 only,1: Addresses can be shifted to the device on DQ0..,2: Addresses can be shifted to the device on DQ0,3: Addresses can be shifted to the device on DQ[7:0]" newline bitfld.long 0x4 10. "DDR_EN_FLD,DDR Enable: This is to inform that opcode from rd_opcode_non_xip_fld is compliant with one of the DDR READ Commands" "0,1" newline bitfld.long 0x4 8.--9. "INSTR_TYPE_FLD,Instruction Type: 0 : Use Standard SPI mode [instruction always shifted into the device on DQ0 only] 1 : Use DIO-SPI mode [Instructions Address and Data always sent on DQ0 and DQ1] 2 : Use QIO-SPI mode [Instructions Address and Data.." "0: Use Standard SPI mode [instruction always..,1: Use DIO-SPI mode [Instructions,2: Use QIO-SPI mode [Instructions,3: Use Octal-IO-SPI mode [Instructions" newline hexmask.long.byte 0x4 0.--7. 1. "RD_OPCODE_NON_XIP_FLD,Read Opcode in non-XIP mode: Read Opcode to use when not in XIP mode" line.long 0x8 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_instr_wr_config_reg,Device Write Instruction Configuration Register" hexmask.long.byte 0x8 24.--28. 1. "DUMMY_WR_CLK_CYCLES_FLD,Dummy Write Clock Cycles: Number of dummy clock cycles required by device for write instruction." newline bitfld.long 0x8 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers DQ0 and DQ1 are used as both.." "0: SIO mode data is shifted to the device on DQ0..,1: Used for Dual Input/Output instructions,2: Used for Quad Input/Output instructions,3: Used for Quad Input/Output instructions" newline bitfld.long 0x8 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0 DQ1 DQ2.." "0: Addresses can be shifted to the device on DQ0 only,1: Addresses can be shifted to the device on DQ0..,2: Addresses can be shifted to the device on DQ0,3: Addresses can be shifted to the device on DQ[7:0]" newline bitfld.long 0x8 8. "WEL_DIS_FLD,WEL Disable: This is to turn off automatic issuing of WEL Command before write operation for DAC or INDAC" "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "WR_OPCODE_FLD,Write Opcode" line.long 0xC "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_delay_reg,Octal-SPI Device Delay Register: This register is used to introduce relative delays into the generation of the master output signals. All timings are defined in cycles.." hexmask.long.byte 0xC 24.--31. 1. "D_NSS_FLD,Clock Delay for Chip Select Deassert: Delay in master reference clocks for the length that the master mode chip select outputs are de-asserted between transactions. The minimum delay is always SCLK period to ensure the chip select is never.." newline hexmask.long.byte 0xC 16.--23. 1. "D_BTWN_FLD,Clock Delay for Chip Select Deactivation: Delay in master reference clocks between one chip select being de-activated and the activation of another. This is used to ensure a quiet period between the selection of two different slaves and.." newline hexmask.long.byte 0xC 8.--15. 1. "D_AFTER_FLD,Clock Delay for Last Transaction Bit: Delay in master reference clocks between last bit of current transaction and deasserting the device chip select [n_ss_out]. By default the chip select will be deasserted on the cycle following the.." newline hexmask.long.byte 0xC 0.--7. 1. "D_INIT_FLD,Clock Delay with n_ss_out: Delay in master reference clocks between setting n_ss_out low and first bit transfer." line.long 0x10 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_rd_data_capture_reg,Read Data Capture Register" hexmask.long.byte 0x10 16.--19. 1. "DDR_READ_DELAY_FLD,DDR read delay: Delay the transmitted data by the programmed number of ref_clk cycles.This field is only relevant when DDR Read Command is executed. Otherwise can be ignored." newline bitfld.long 0x10 8. "DQS_ENABLE_FLD,DQS enable bit: If enabled signal from DQS input is driven into RX DLL and is used for data capturing in PHY Mode rather than internally generated gated ref_clk.." "0,1" newline bitfld.long 0x10 5. "SAMPLE_EDGE_SEL_FLD,Sample edge selection: Choose edge on which data outputs from flash memory will be sampled" "0,1" newline hexmask.long.byte 0x10 1.--4. 1. "DELAY_FLD,Read Delay: Delay the read data capturing logic by the programmed number of ref_clk cycles" newline bitfld.long 0x10 0. "BYPASS_FLD,Bypass the adapted loopback clock circuit" "0,1" line.long 0x14 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_size_config_reg,Device Size Configuration Register" bitfld.long 0x14 27.--28. "MEM_SIZE_ON_CS3_FLD,Size of Flash Device connected to CS[3] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "0: size of 512Mb,1: size of 1Gb,?,?" newline bitfld.long 0x14 25.--26. "MEM_SIZE_ON_CS2_FLD,Size of Flash Device connected to CS[2] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "0: size of 512Mb,1: size of 1Gb,?,?" newline bitfld.long 0x14 23.--24. "MEM_SIZE_ON_CS1_FLD,Size of Flash Device connected to CS[1] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "0: size of 512Mb,1: size of 1Gb,?,?" newline bitfld.long 0x14 21.--22. "MEM_SIZE_ON_CS0_FLD,Size of Flash Device connected to CS[0] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "0: size of 512Mb,1: size of 1Gb,?,?" newline hexmask.long.byte 0x14 16.--20. 1. "BYTES_PER_SUBSECTOR_FLD,Number of bytes per Block. This is required by the controller for performing the write protection logic. The number of bytes per block must be a power of 2 number." newline hexmask.long.word 0x14 4.--15. 1. "BYTES_PER_DEVICE_PAGE_FLD,Number of bytes per device page. This is required by the controller for performing FLASH writes up to and across page boundaries." newline hexmask.long.byte 0x14 0.--3. 1. "NUM_ADDR_BYTES_FLD,Number of address bytes. A value of 0 indicates 1 byte." line.long 0x18 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_sram_partition_cfg_reg,SRAM Partition Configuration Register" hexmask.long.byte 0x18 0.--7. 1. "ADDR_FLD,Indirect Read Partition Size: Defines the size of the indirect read partition in the SRAM in units of SRAM locations. By default half of the SRAM is reserved for indirect read operation and half for indirect write. The size of this register.." line.long 0x1C "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_ind_AHB_addr_trigger_reg,Indirect AHB Address Trigger Register" hexmask.long 0x1C 0.--31. 1. "ADDR_FLD,This is the base address that will be used by the AHB controller. When the incoming AHB read access address matches a range of addresses from this trigger address to the trigger address + 15 then the AHB request will be completed by fetching.." line.long 0x20 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dma_periph_config_reg,DMA Peripheral Configuration Register" hexmask.long.byte 0x20 8.--11. 1. "NUM_BURST_REQ_BYTES_FLD,Number of Burst Bytes: Number of bytes in a burst type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The actual.." newline hexmask.long.byte 0x20 0.--3. 1. "NUM_SINGLE_REQ_BYTES_FLD,Number of Single Bytes: Number of bytes in a single type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The.." line.long 0x24 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_remap_addr_reg,Remap Address Register" hexmask.long 0x24 0.--31. 1. "VALUE_FLD,This register is used to remap an incoming AHB address to a different address used by the FLASH device." line.long 0x28 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_mode_bit_config_reg,Mode Bit Configuration Register" hexmask.long.byte 0x28 24.--31. 1. "RX_CRC_DATA_LOW_FLD,RX CRC data [lower] The first CRC byte returned after RX data chunk." newline hexmask.long.byte 0x28 16.--23. 1. "RX_CRC_DATA_UP_FLD,RX CRC data [upper] The second CRC byte returned after RX data chunk." newline bitfld.long 0x28 15. "CRC_OUT_ENABLE_FLD,CRC# output enable bit When enabled the controller expects the Flash Device to toggle CRC data on both SPI clock edges in CRC->CRC# sequence and calculates CRC compliance accordingly." "0,1" newline bitfld.long 0x28 8.--10. "CHUNK_SIZE_FLD,It defines size of chunk after which CRC data is expected to show up on the SPI interface for write and read data transfers." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x28 0.--7. 1. "MODE_FLD,These are the 8 mode bits that are sent to the device following the address bytes if mode bit transmission has been enabled." rgroup.long 0x2C++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_sram_fill_reg,SRAM Fill Register" hexmask.long.word 0x0 16.--31. 1. "SRAM_FILL_INDAC_WRITE_FLD,SRAM Fill Level [Indirect Write Partition]: Identifies the current fill level of the SRAM Indirect Write partition" newline hexmask.long.word 0x0 0.--15. 1. "SRAM_FILL_INDAC_READ_FLD,SRAM Fill Level [Indirect Read Partition]: Identifies the current fill level of the SRAM Indirect Read partition" rgroup.long 0x30++0x17 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_tx_thresh_reg,TX Threshold Register" hexmask.long.byte 0x0 0.--4. 1. "LEVEL_FLD,Defines the level at which the small TX FIFO not full interrupt is generated" line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_rx_thresh_reg,RX Threshold Register" hexmask.long.byte 0x4 0.--4. 1. "LEVEL_FLD,Defines the level at which the small RX FIFO not empty interrupt is generated" line.long 0x8 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_write_completion_ctrl_reg,Write Completion Control Register: This register defines how the controller will poll the device following a write transfer" hexmask.long.byte 0x8 24.--31. 1. "POLL_REP_DELAY_FLD,Defines additional delay for maintain Chip Select de-asserted during auto-polling phase" newline hexmask.long.byte 0x8 16.--23. 1. "POLL_COUNT_FLD,Defines the number of times the controller should expect to see a true result from the polling in successive reads of the device register." newline bitfld.long 0x8 15. "ENABLE_POLLING_EXP_FLD,Set to '1' for enabling auto-polling expiration." "0,1" newline bitfld.long 0x8 14. "DISABLE_POLLING_FLD,This switches off the automatic polling function" "0,1" newline bitfld.long 0x8 13. "POLLING_POLARITY_FLD,Defines the polling polarity. If '1' then the write transfer to the device will be complete if the polled bit is equal to '1'. If '0' then the write transfer to the device will be complete if the polled bit is equal to '0'." "0,1" newline bitfld.long 0x8 8.--10. "POLLING_BIT_INDEX_FLD,Defines the bit index that should be polled. A value of 010 means that bit 2 of the returned data will be polled for.A value of 111 means that bit 7 of the returned data will be polled for." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "OPCODE_FLD,Defines the opcode that should be issued by the controller when it is automatically polling for device program completion. This command is issued followed all device write operations. By default this will poll the standard device STATUS.." line.long 0xC "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_no_of_polls_bef_exp_reg,Polling Expiration Register" hexmask.long 0xC 0.--31. 1. "NO_OF_POLLS_BEF_EXP_FLD,Number of polls cycles before expiration" line.long 0x10 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_irq_status_reg,Interrupt Status Register: The status fields in this register are set when the described event occurs and the interrupt is enabled in the mask register. When any of.." bitfld.long 0x10 19. "ECC_FAIL_FLD,ECC failure This interrupt informs the system that Flash Device reported ECC error." "0,1" newline bitfld.long 0x10 18. "TX_CRC_CHUNK_BRK_FLD,TX CRC chunk was broken This interrupt informs the system that program page SPI transfer was discontinued somewhere inside the chunk." "0,1" newline bitfld.long 0x10 17. "RX_CRC_DATA_VAL_FLD,RX CRC data valid New RX CRC data was captured from Flash Device" "0,1" newline bitfld.long 0x10 16. "RX_CRC_DATA_ERR_FLD,RX CRC data error CRC data from Flash Device does not correspond to the one dynamically calculated by the controller." "0,1" newline bitfld.long 0x10 14. "STIG_REQ_INT_FLD,The controller is ready for getting another STIG request." "0,1" newline bitfld.long 0x10 13. "POLL_EXP_INT_FLD,The maximum number of programmed polls cycles is expired" "0,1" newline bitfld.long 0x10 12. "INDRD_SRAM_FULL_FLD,Indirect Read Partition overflow: Indirect Read Partition of SRAM is full and unable to immediately complete indirect operation" "0,1" newline bitfld.long 0x10 11. "RX_FIFO_FULL_FLD,Small RX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full 1 : FIFO is full" "0: FIFO is not full,1: FIFO is full" newline bitfld.long 0x10 10. "RX_FIFO_NOT_EMPTY_FLD,Small RX FIFO not empty: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has less than RX THRESHOLD entries 1 : FIFO has >= THRESHOLD entries" "0: FIFO has less than RX THRESHOLD entries,1: FIFO has >= THRESHOLD entries" newline bitfld.long 0x10 9. "TX_FIFO_FULL_FLD,Small TX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full 1 : FIFO is full" "0: FIFO is not full,1: FIFO is full" newline bitfld.long 0x10 8. "TX_FIFO_NOT_FULL_FLD,Small TX FIFO not full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has >= THRESHOLD entries 1 : FIFO has less than THRESHOLD entries" "0: FIFO has >= THRESHOLD entries,1: FIFO has less than THRESHOLD entries" newline bitfld.long 0x10 7. "RECV_OVERFLOW_FLD,Receive Overflow: This should only occur in Legacy SPI mode. Set if an attempt is made to push the RX FIFO when it is full. This bit is reset only by a system reset and cleared only when this register is read. If a new push to the RX.." "0: no overflow has been detected,1: an overflow has occurred" newline bitfld.long 0x10 6. "INDIRECT_XFER_LEVEL_BREACH_FLD,Indirect Transfer Watermark Level Breached" "0,1" newline bitfld.long 0x10 5. "ILLEGAL_ACCESS_DET_FLD,Illegal AHB access has been detected. AHB wrapping bursts and the use of SPLIT/RETRY accesses will cause this error interrupt to trigger." "0,1" newline bitfld.long 0x10 4. "PROT_WR_ATTEMPT_FLD,Write to protected area was attempted and rejected." "0,1" newline bitfld.long 0x10 3. "INDIRECT_READ_REJECT_FLD,Indirect operation was requested but could not be accepted. Two indirect operations already in storage." "0,1" newline bitfld.long 0x10 2. "INDIRECT_OP_DONE_FLD,Indirect Operation Complete: Controller has completed last triggered indirect operation" "0,1" newline bitfld.long 0x10 1. "UNDERFLOW_DET_FLD,Underflow Detected: 0 : no underflow has been detected 1 : underflow is detected and an attempt to transfer data is made when the small TX FIFO is empty. This may occur when AHB write data is being supplied too slowly to keep up with.." "0: no underflow has been detected,1: underflow is detected and an attempt to transfer.." newline bitfld.long 0x10 0. "MODE_M_FAIL_FLD,Mode M Failure: Mode M failure indicates the voltage on pin n_ss_in is inconsistent with the SPI mode. Set =1 if n_ss_in is low in master mode [multi-master contention]. These conditions will clear the spi_enable bit and disable the SPI." "0: no mode fault has been detected,1: a mode fault has occurred" line.long 0x14 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_irq_mask_reg,Interrupt Mask: 0 : the interrupt for the corresponding interrupt status register bit is disabled." bitfld.long 0x14 19. "ECC_FAIL_MASK_FLD,ECC failure Mask" "0,1" newline bitfld.long 0x14 18. "TX_CRC_CHUNK_BRK_MASK_FLD,TX CRC chunk was broken Mask" "0,1" newline bitfld.long 0x14 17. "RX_CRC_DATA_VAL_MASK_FLD,RX CRC data valid Mask" "0,1" newline bitfld.long 0x14 16. "RX_CRC_DATA_ERR_MASK_FLD,RX CRC data error Mask" "0,1" newline bitfld.long 0x14 14. "STIG_REQ_MASK_FLD,STIG request completion Mask" "0,1" newline bitfld.long 0x14 13. "POLL_EXP_INT_MASK_FLD,Polling expiration detected Mask" "0,1" newline bitfld.long 0x14 12. "INDRD_SRAM_FULL_MASK_FLD,Indirect Read Partition overflow mask" "0,1" newline bitfld.long 0x14 11. "RX_FIFO_FULL_MASK_FLD,Small RX FIFO full Mask" "0,1" newline bitfld.long 0x14 10. "RX_FIFO_NOT_EMPTY_MASK_FLD,Small RX FIFO not empty Mask" "0,1" newline bitfld.long 0x14 9. "TX_FIFO_FULL_MASK_FLD,Small TX FIFO full Mask" "0,1" newline bitfld.long 0x14 8. "TX_FIFO_NOT_FULL_MASK_FLD,Small TX FIFO not full Mask" "0,1" newline bitfld.long 0x14 7. "RECV_OVERFLOW_MASK_FLD,Receive Overflow Mask" "0,1" newline bitfld.long 0x14 6. "INDIRECT_XFER_LEVEL_BREACH_MASK_FLD,Transfer Watermark Breach Mask" "0,1" newline bitfld.long 0x14 5. "ILLEGAL_ACCESS_DET_MASK_FLD,Illegal Access Detected Mask" "0,1" newline bitfld.long 0x14 4. "PROT_WR_ATTEMPT_MASK_FLD,Protected Area Write Attempt Mask" "0,1" newline bitfld.long 0x14 3. "INDIRECT_READ_REJECT_MASK_FLD,Indirect Read Reject Mask" "0,1" newline bitfld.long 0x14 2. "INDIRECT_OP_DONE_MASK_FLD,Indirect Complete Mask" "0,1" newline bitfld.long 0x14 1. "UNDERFLOW_DET_MASK_FLD,Underflow Detected Mask" "0,1" newline bitfld.long 0x14 0. "MODE_M_FAIL_MASK_FLD,Mode M Failure Mask" "0,1" rgroup.long 0x50++0xB line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_lower_wr_prot_reg,Lower Write Protection Register" hexmask.long 0x0 0.--31. 1. "SUBSECTOR_FLD,The block number that defines the lower block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register." line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_upper_wr_prot_reg,Upper Write Protection Register" hexmask.long 0x4 0.--31. 1. "SUBSECTOR_FLD,The block number that defines the upper block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register." line.long 0x8 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_wr_prot_ctrl_reg,Write Protection Control Register" bitfld.long 0x8 1. "ENB_FLD,Write Protection Enable Bit: When set to 1 any AHB write access with an address within the protection region defined in the lower and upper write protection registers is rejected. An AHB error response is generated and an interrupt source.." "0,1" newline bitfld.long 0x8 0. "INV_FLD,Write Protection Inversion Bit: When set to 1 the protection region defined in the lower and upper write protection registers is inverted meaning it is the region that the system is permitted to write to. When set to 0 the protection region.." "0,1" rgroup.long 0x60++0x23 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_ctrl_reg,Indirect Read Transfer Control Register" rbitfld.long 0x0 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field [bit 5]. It is incremented by hardware when an indirect operation has completed." "0,1,2,3" newline bitfld.long 0x0 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it." "0,1" newline rbitfld.long 0x0 4. "RD_QUEUED_FLD,Two indirect read operations have been queued" "0,1" newline bitfld.long 0x0 3. "SRAM_FULL_FLD,SRAM Full: SRAM full and unable to immediately complete an indirect operation. Write a 1 to this field to clear it.; indirect operation [status]" "0,1" newline rbitfld.long 0x0 2. "RD_STATUS_FLD,Indirect Read Status: Indirect read operation in progress [status]" "0,1" newline bitfld.long 0x0 1. "CANCEL_FLD,Cancel Indirect Read: Writing a 1 to this bit will cancel all ongoing indirect read operations." "0,1" newline bitfld.long 0x0 0. "START_FLD,Start Indirect Read: Writing a 1 to this bit will trigger an indirect read operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect read operation." "0,1" line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_watermark_reg,Indirect Read Transfer Watermark Register" hexmask.long 0x4 0.--31. 1. "LEVEL_FLD,Watermark Value: This represents the minimum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level passes the watermark an interrupt is also generated. This field can be disabled by writing a value of all.." line.long 0x8 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_start_reg,Indirect Read Transfer Start Address Register" hexmask.long 0x8 0.--31. 1. "ADDR_FLD,This is the start address from which the indirect access will commence its READ operation." line.long 0xC "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_num_bytes_reg,Indirect Read Transfer Number Bytes Register" hexmask.long 0xC 0.--31. 1. "VALUE_FLD,This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM." line.long 0x10 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_ctrl_reg,Indirect Write Transfer Control Register" rbitfld.long 0x10 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field [bit 5]. It is incremented by hardware when an indirect operation has completed." "0,1,2,3" newline bitfld.long 0x10 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it." "0,1" newline rbitfld.long 0x10 4. "WR_QUEUED_FLD,Two indirect write operations have been queued" "0,1" newline rbitfld.long 0x10 2. "WR_STATUS_FLD,Indirect Write Status: Indirect write operation in progress [status]" "0,1" newline bitfld.long 0x10 1. "CANCEL_FLD,Cancel Indirect Write: Writing a 1 to this bit will cancel all ongoing indirect write operations." "0,1" newline bitfld.long 0x10 0. "START_FLD,Start Indirect Write: Writing a 1 to this bit will trigger an indirect write operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect write operation." "0,1" line.long 0x14 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_watermark_reg,Indirect Write Transfer Watermark Register" hexmask.long 0x14 0.--31. 1. "LEVEL_FLD,Watermark Value: This represents the maximum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level falls below the watermark an interrupt is also generated. This field can be disabled by writing a value.." line.long 0x18 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_start_reg,Indirect Write Transfer Start Address Register" hexmask.long 0x18 0.--31. 1. "ADDR_FLD,Start of Indirect Access: This is the start address from which the indirect access will commence its READ operation." line.long 0x1C "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_num_bytes_reg,Indirect Write Transfer Number Bytes Register" hexmask.long 0x1C 0.--31. 1. "VALUE_FLD,Indirect Number of Bytes: This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM." line.long 0x20 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_trigger_addr_range_reg,Indirect Trigger Address Range Register" hexmask.long.byte 0x20 0.--3. 1. "IND_RANGE_WIDTH_FLD,This is the address offset of Indirect Trigger Address Register." rgroup.long 0x8C++0xB line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_command_ctrl_mem_reg,Flash Command Control Memory Register" hexmask.long.word 0x0 20.--28. 1. "MEM_BANK_ADDR_FLD,The address of the Memory Bank which data will be read from." newline bitfld.long 0x0 16.--18. "NB_OF_STIG_READ_BYTES_FLD,It defines the number of read bytes for the extended STIG." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "MEM_BANK_READ_DATA_FLD,Last requested data from the STIG Memory Bank." newline rbitfld.long 0x0 1. "MEM_BANK_REQ_IN_PROGRESS_FLD,Memory Bank data request in progress." "0,1" newline bitfld.long 0x0 0. "TRIGGER_MEM_BANK_REQ_FLD,Trigger the Memory Bank data request." "0,1" line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_cmd_ctrl_reg,Flash Command Control Register" hexmask.long.byte 0x4 24.--31. 1. "CMD_OPCODE_FLD,Command Opcode: The command opcode field should be setup before triggering the command. For example 0x20 maps to SubSector Erase. Writing to the execute field [bit 0] of this register launches the command. NOTE : Using this approach to.." newline bitfld.long 0x4 23. "ENB_READ_DATA_FLD,Read Data Enable: Set to 1 if the command specified in the command opcode field [bits 31:24] requires read data bytes to be received from the device." "0,1" newline bitfld.long 0x4 20.--22. "NUM_RD_DATA_BYTES_FLD,Number of Read Data Bytes: Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for 8 bytes." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "ENB_COMD_ADDR_FLD,Command Address Enable: Set to 1 if the command specified in bits 31:24 requires an address. This should be setup before triggering the command via writing a 1 to the execute field." "0,1" newline bitfld.long 0x4 18. "ENB_MODE_BIT_FLD,Mode Bit Enable: Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes." "0,1" newline bitfld.long 0x4 16.--17. "NUM_ADDR_BYTES_FLD,Number of Address Bytes: Set to the number of address bytes required [the address itself is programmed in the FLASH COMMAND ADDRESS REGISTERS]. This should be setup before triggering the command via bit 0 of this register. 2'b00 : 1.." "0,1,2,3" newline bitfld.long 0x4 15. "ENB_WRITE_DATA_FLD,Write Data Enable: Set to 1 if the command specified in the command opcode field requires write data bytes to be sent to the device." "0,1" newline bitfld.long 0x4 12.--14. "NUM_WR_DATA_BYTES_FLD,Number of Write Data Bytes: Up to 8 Data bytes may be written using this command Set to 0 for 1 byte 7 for 8 bytes." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 7.--11. 1. "NUM_DUMMY_CYCLES_FLD,Number of Dummy cycles: Set to the number of dummy cycles required. This should be setup before triggering the command via the execute field of this register." newline bitfld.long 0x4 2. "STIG_MEM_BANK_EN_FLD,STIG Memory Bank enable bit." "0,1" newline rbitfld.long 0x4 1. "CMD_EXEC_STATUS_FLD,Command execution in progress." "0,1" newline bitfld.long 0x4 0. "CMD_EXEC_FLD,Execute the command." "0,1" line.long 0x8 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_cmd_addr_reg,Flash Command Address Register" hexmask.long 0x8 0.--31. 1. "ADDR_FLD,Command Address: This should be setup before triggering the command with execute field [bit 0] of the Flash Command Control register. It is the address used by the command specified in the opcode field [bits 31:24] of the Flash Command Control.." rgroup.long 0xA0++0x7 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_rd_data_lower_reg,Flash Command Read Data Register (Lower)" hexmask.long 0x0 0.--31. 1. "DATA_FLD,This is the data that is returned by the flash device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low." line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_rd_data_upper_reg,Flash Command Read Data Register (Upper)" hexmask.long 0x4 0.--31. 1. "DATA_FLD,This is the data that is returned by the FLASH device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low." rgroup.long 0xA8++0x13 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_wr_data_lower_reg,Flash Command Write Data Register (Lower)" hexmask.long 0x0 0.--31. 1. "DATA_FLD,Command Write Data Lower Byte: This is the command write data lower byte. This should be setup before triggering the command with execute field [bit 0] of the Flash Command Control register. It is the data that is to be written to the flash for.." line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_wr_data_upper_reg,Flash Command Write Data Register (Upper)" hexmask.long 0x4 0.--31. 1. "DATA_FLD,Command Write Data Upper Byte: This is the command write data upper byte. This should be setup before triggering the command with execute field [bit 0] of the Flash Command Control register. It is the data that is to be written to the flash for.." line.long 0x8 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_polling_flash_status_reg,Polling Flash Status Register" hexmask.long.byte 0x8 16.--19. 1. "DEVICE_STATUS_NB_DUMMY,Number of dummy cycles for auto-polling" newline rbitfld.long 0x8 8. "DEVICE_STATUS_VALID_FLD,Device Status Valid: This should be set when value in bits from 7 to 0 is valid." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "DEVICE_STATUS_FLD,Defines actual Status Register of Device" line.long 0xC "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_phy_configuration_reg,PHY Configuration Register" bitfld.long 0xC 31. "PHY_CONFIG_RESYNC_FLD,This bit is used for re-synchronisation delay lines to update them with values from TX DLL Delay and RX DLL Delay fields." "0,1" newline bitfld.long 0xC 30. "PHY_CONFIG_RESET_FLD,DLL Reset bit: This bit is used for reset of Delay Lines by software." "0,1" newline bitfld.long 0xC 29. "PHY_CONFIG_RX_DLL_BYPASS_FLD,RX DLL Bypass: This field determines id RX DLL is bypassed." "0,1" newline hexmask.long.byte 0xC 16.--22. 1. "PHY_CONFIG_TX_DLL_DELAY_FLD,TX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and spi_clk." newline hexmask.long.byte 0xC 0.--6. 1. "PHY_CONFIG_RX_DLL_DELAY_FLD,RX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and rx_dll_clk." line.long 0x10 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_phy_master_control_reg,PHY DLL Master Control Register" bitfld.long 0x10 24. "PHY_MASTER_LOCK_MODE_FLD,Determines if the master delay line locks on a full cycle or half cycle of delay." "0,1" newline bitfld.long 0x10 23. "PHY_MASTER_BYPASS_MODE_FLD,Controls the bypass mode of the master and slave DLLs." "0,1" newline bitfld.long 0x10 20.--22. "PHY_MASTER_PHASE_DETECT_SELECTOR_FLD,Selects the number of delay elements to be inserted between the phase detect flip-flops." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 16.--18. "PHY_MASTER_NB_INDICATIONS_FLD,Holds the number of consecutive increment or decrement indications." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--6. 1. "PHY_MASTER_INITIAL_DELAY_FLD,This value is the initial delay value for the DLL." rgroup.long 0xBC++0x7 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dll_observable_lower_reg,DLL Observable Register Lower" hexmask.long.byte 0x0 24.--31. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD,Holds the state of the cumulative dll_lock_inc register." newline hexmask.long.byte 0x0 16.--23. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD,Holds the state of the cumulative dll_lock_dec register." newline bitfld.long 0x0 15. "DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD,This bit indicates that lock of loopback is done." "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD,Reports the DLL encoder value from the master DLL to the slave DLLs." newline hexmask.long.byte 0x0 3.--7. 1. "DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD,Reports the number of increments or decrements required for the master DLL to complete the locking process." newline bitfld.long 0x0 1.--2. "DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD,Defines the mode in which the DLL has achieved the lock." "0,1,2,3" newline bitfld.long 0x0 0. "DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD,Indicates status of DLL." "0,1" line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dll_observable_upper_reg,DLL Observable Register Upper" hexmask.long.byte 0x4 16.--22. 1. "DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD,Holds the encoded value for the TX delay line for this slice." newline hexmask.long.byte 0x4 0.--6. 1. "DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD,Holds the encoded value for the RX delay line for this slice." rgroup.long 0xE0++0x7 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_opcode_ext_lower_reg,Opcode Extension Register (Lower)" hexmask.long.byte 0x0 24.--31. 1. "EXT_READ_OPCODE_FLD,Supplement byte of any Read Opcode" newline hexmask.long.byte 0x0 16.--23. 1. "EXT_WRITE_OPCODE_FLD,Supplement byte of any Write Opcode" newline hexmask.long.byte 0x0 8.--15. 1. "EXT_POLL_OPCODE_FLD,Supplement byte of any Polling Opcode" newline hexmask.long.byte 0x0 0.--7. 1. "EXT_STIG_OPCODE_FLD,Supplement byte of any STIG Opcode" line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_opcode_ext_upper_reg,Opcode Extension Register (Upper)" hexmask.long.byte 0x4 24.--31. 1. "WEL_OPCODE_FLD,First byte of any WEL Opcode" newline hexmask.long.byte 0x4 16.--23. 1. "EXT_WEL_OPCODE_FLD,Supplement byte of any WEL Opcode" rgroup.long 0xFC++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_module_id_reg,Module ID Register" hexmask.long.byte 0x0 24.--31. 1. "FIX_PATCH_FLD,Fix/path number related to revision described by 3 LSBs of this register" newline hexmask.long.word 0x0 8.--23. 1. "MODULE_ID_FLD,Module/Revision ID number" newline bitfld.long 0x0 0.--1. "CONF_FLD,Configuration ID number: 0 : OCTAL + PHY Configuration 1 : OCTAL Configuration 2 : QUAD + PHY Configuration 3 : QUAD Configuration" "0: OCTAL + PHY Configuration,1: OCTAL Configuration,2: QUAD + PHY Configuration,3: QUAD Configuration" tree.end tree "MCU_FSS0_OSPI_0_OSPI0_ECC_AGGR (MCU_FSS0_OSPI_0_OSPI0_ECC_AGGR)" base ad:0x47068000 rgroup.long 0x0++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCU_FSS0_OSPI_0_OSPI0_SS_CFG (MCU_FSS0_OSPI_0_OSPI0_SS_CFG)" base ad:0x47044000 rgroup.long 0x0++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_CTRL,The Control Register contains general control bits for the ospi" bitfld.long 0x0 3. "PIPELINE_MODE_FLUSH,1 - Flush Cadence Flash Controller FIFO by forcin gAHB SEL low. 0 - AHB Sel to Cadence Controller is 1" "0: AHB Sel to Cadence Controller is 1,1: Flush Cadence Flash Controller FIFO by forcin.." rgroup.long 0x8++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_STAT,The Status register provide general status bits for the ospi" bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" rgroup.long 0x20++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targetted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" tree.end tree.end tree "MCU_FSS0_OSPI_1" tree "MCU_FSS0_OSPI_1_OSPI1_CTRL (MCU_FSS0_OSPI_1_OSPI1_CTRL)" base ad:0x47050000 rgroup.long 0x0++0x2B line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_config_reg,Octal-SPI Configuration Register" rbitfld.long 0x0 31. "IDLE_FLD,Serial interface and low level SPI pipeline is IDLE: This is a STATUS read-only bit. Note this is a retimed signal so there will be some inherent delay on the generation of this status signal." "0,1" newline bitfld.long 0x0 30. "DUAL_BYTE_OPCODE_EN_FLD,Dual-byte Opcode Mode enable bit This bit is to be set in case the target Flash Device supports dual byte opcode [i.e. Macronix MX25]. It is applicable for Octal I/O Mode or Protocol only so should be set back to low if the device.." "0,1" newline bitfld.long 0x0 29. "CRC_ENABLE_FLD,CRC enable bit This bit is to be set in case the target Flash Device supports CRC [Macronix MX25]. It is applicable for Octal DDR Protocol only so should be set back to low if the device is configured to work in another SPI Mode." "0,1" newline bitfld.long 0x0 25. "PIPELINE_PHY_FLD,Pipeline PHY Mode enable: This bit is relevant only for configuration with PHY Module. It should be asserted to 1 between consecutive PHY pipeline reads transfers and de-asserted to 0 otherwise." "0,1" newline bitfld.long 0x0 24. "ENABLE_DTR_PROTOCOL_FLD,Enable DTR Protocol: This bit should be set if device is configured to work in DTR protocol." "0,1" newline bitfld.long 0x0 23. "ENABLE_AHB_DECODER_FLD,Enable AHB Decoder: Value=0 : Active slave is selected based on Peripheral Chip Select Lines [bits [13:10]]. Value=1 Active slave is selected based on actual AHB address [the partition for each device is calculated with respect to.." "0: Active slave is selected based on Peripheral..,?" newline hexmask.long.byte 0x0 19.--22. 1. "MSTR_BAUD_DIV_FLD,Master Mode Baud Rate Divisor: SPI baud rate = [master reference clock] baud_rate_divisor" newline bitfld.long 0x0 18. "ENTER_XIP_MODE_IMM_FLD,Enter XIP Mode immediately: Value=0 : If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : Operate the device in XIP mode immediately Use this register when the.." "0: If XIP is enabled,1: Operate the device in XIP mode immediately Use.." newline bitfld.long 0x0 17. "ENTER_XIP_MODE_FLD,Enter XIP Mode on next READ: Value=0 : If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : If XIP is disabled then setting to ?1? will inform the controller that the.." "0: If XIP is enabled,1: If XIP is disabled" newline bitfld.long 0x0 16. "ENB_AHB_ADDR_REMAP_FLD,Enable AHB Address Re-mapping: [Direct Access Mode Only] When set to 1 the incoming AHB address will be adapted and sent to the FLASH device as [address + N] where N is the value stored in the remap address register." "0,1" newline bitfld.long 0x0 15. "ENB_DMA_IF_FLD,Enable DMA Peripheral Interface: Set to 1 to enable the DMA handshaking logic. When enabled the controller will trigger DMA transfer requests via the DMA peripheral interface. Set to 0 to disable" "0,1" newline bitfld.long 0x0 14. "WR_PROT_FLASH_FLD,Write Protect Flash Pin: Set to drive the Write Protect pin of the FLASH device. This is resynchronized to the generated memory clock as necessary." "0,1" newline hexmask.long.byte 0x0 10.--13. 1. "PERIPH_CS_LINES_FLD,Peripheral Chip Select Lines: Peripheral chip select lines If pdec = 0 ss[3:0] are output thus: ss[3:0] n_ss_out[3:0] xxx0 1110 xx01 1101 x011 1011 0111 0111 1111 1111 [no peripheral selected] else ss[3:0] directly drives n_ss_out[3:0]" newline bitfld.long 0x0 9. "PERIPH_SEL_DEC_FLD,Peripheral select decode: 0 : only 1 of 4 selects n_ss_out[3:0] is active 1 : allow external 4-to-16 decode [n_ss_out = ss]" "0: only 1 of 4 selects n_ss_out[3:0] is active,1: allow external 4-to-16 decode [n_ss_out = ss]" newline bitfld.long 0x0 8. "ENB_LEGACY_IP_MODE_FLD,Legacy IP Mode Enable: 0 : Use Direct Access Controller/Indirect Access Controller 1 : legacy Mode is enabled. In this mode any write to the controller via the AHB interface is serialized and sent to the FLASH device. Any valid.." "0: Use Direct Access Controller/Indirect Access..,1: legacy Mode is enabled" newline bitfld.long 0x0 7. "ENB_DIR_ACC_CTLR_FLD,Enable Direct Access Controller: 0 : disable the Direct Access Controller once current transfer of the data word [FF_W] is complete. 1 : enable the Direct Access Controller When the Direct Access Controller and Indirect Access.." "0: disable the Direct Access Controller once..,1: enable the Direct Access Controller When the.." newline bitfld.long 0x0 6. "RESET_CFG_FLD,RESET pin configuration: 0 = RESET feature on DQ3 pin of the device 1 = RESET feature on dedicated pin of the device [controlling of 5th bit influences on reset_out output]" "0: RESET feature on DQ3 pin of the device,1: RESET feature on dedicated pin of the device.." newline bitfld.long 0x0 5. "RESET_PIN_FLD,Set to drive the RESET pin of the FLASH device and reset for de-activation of the RESET pin feature" "0,1" newline bitfld.long 0x0 4. "HOLD_PIN_FLD,Set to drive the HOLD pin of the FLASH device and reset for de-activation of the HOLD pin feature" "0,1" newline bitfld.long 0x0 3. "PHY_MODE_ENABLE_FLD,PHY mode enable: When enabled the controller is informed that PHY Module is to be used for handling SPI transfers. This bit is relevant only for configuration with PHY Module." "0,1" newline bitfld.long 0x0 2. "SEL_CLK_PHASE_FLD,Select Clock Phase: Selects whether the clock is in an active or inactive phase outside the SPI word. 0 : the SPI clock is active outside the word 1 : the SPI clock is inactive outside the word" "0: the SPI clock is active outside the word,1: the SPI clock is inactive outside the word" newline bitfld.long 0x0 1. "SEL_CLK_POL_FLD,Clock polarity outside SPI word: 0 : the SPI clock is quiescent low 1 : the SPI clock is quiescent high" "0: the SPI clock is quiescent low,1: the SPI clock is quiescent high" newline bitfld.long 0x0 0. "ENB_SPI_FLD,Octal-SPI Enable: 0 : disable the Octal-SPI once current transfer of the data word [FF_W] is complete. 1 : enable the Octal-SPI when spi_enable = 0 all output enables are inactive and all pins are set to input mode." "0: disable the Octal-SPI,1: enable the Octal-SPI" line.long 0x4 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_instr_rd_config_reg,Device Read Instruction Configuration Register" hexmask.long.byte 0x4 24.--28. 1. "DUMMY_RD_CLK_CYCLES_FLD,Dummy Read Clock Cycles: Number of dummy clock cycles required by device for read instruction." newline bitfld.long 0x4 20. "MODE_BIT_ENABLE_FLD,Mode Bit Enable: Set this field to 1 to ensure that the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes." "0,1" newline bitfld.long 0x4 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers DQ0 and DQ1 are used as both.." "0: SIO mode data is shifted to the device on DQ0..,1: Used for Dual Input/Output instructions,2: Used for Quad Input/Output instructions,3: Used for Quad Input/Output instructions" newline bitfld.long 0x4 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0 DQ1 DQ2.." "0: Addresses can be shifted to the device on DQ0 only,1: Addresses can be shifted to the device on DQ0..,2: Addresses can be shifted to the device on DQ0,3: Addresses can be shifted to the device on DQ[7:0]" newline bitfld.long 0x4 10. "DDR_EN_FLD,DDR Enable: This is to inform that opcode from rd_opcode_non_xip_fld is compliant with one of the DDR READ Commands" "0,1" newline bitfld.long 0x4 8.--9. "INSTR_TYPE_FLD,Instruction Type: 0 : Use Standard SPI mode [instruction always shifted into the device on DQ0 only] 1 : Use DIO-SPI mode [Instructions Address and Data always sent on DQ0 and DQ1] 2 : Use QIO-SPI mode [Instructions Address and Data.." "0: Use Standard SPI mode [instruction always..,1: Use DIO-SPI mode [Instructions,2: Use QIO-SPI mode [Instructions,3: Use Octal-IO-SPI mode [Instructions" newline hexmask.long.byte 0x4 0.--7. 1. "RD_OPCODE_NON_XIP_FLD,Read Opcode in non-XIP mode: Read Opcode to use when not in XIP mode" line.long 0x8 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_instr_wr_config_reg,Device Write Instruction Configuration Register" hexmask.long.byte 0x8 24.--28. 1. "DUMMY_WR_CLK_CYCLES_FLD,Dummy Write Clock Cycles: Number of dummy clock cycles required by device for write instruction." newline bitfld.long 0x8 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers DQ0 and DQ1 are used as both.." "0: SIO mode data is shifted to the device on DQ0..,1: Used for Dual Input/Output instructions,2: Used for Quad Input/Output instructions,3: Used for Quad Input/Output instructions" newline bitfld.long 0x8 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0 DQ1 DQ2.." "0: Addresses can be shifted to the device on DQ0 only,1: Addresses can be shifted to the device on DQ0..,2: Addresses can be shifted to the device on DQ0,3: Addresses can be shifted to the device on DQ[7:0]" newline bitfld.long 0x8 8. "WEL_DIS_FLD,WEL Disable: This is to turn off automatic issuing of WEL Command before write operation for DAC or INDAC" "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "WR_OPCODE_FLD,Write Opcode" line.long 0xC "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_delay_reg,Octal-SPI Device Delay Register: This register is used to introduce relative delays into the generation of the master output signals. All timings are defined in cycles.." hexmask.long.byte 0xC 24.--31. 1. "D_NSS_FLD,Clock Delay for Chip Select Deassert: Delay in master reference clocks for the length that the master mode chip select outputs are de-asserted between transactions. The minimum delay is always SCLK period to ensure the chip select is never.." newline hexmask.long.byte 0xC 16.--23. 1. "D_BTWN_FLD,Clock Delay for Chip Select Deactivation: Delay in master reference clocks between one chip select being de-activated and the activation of another. This is used to ensure a quiet period between the selection of two different slaves and.." newline hexmask.long.byte 0xC 8.--15. 1. "D_AFTER_FLD,Clock Delay for Last Transaction Bit: Delay in master reference clocks between last bit of current transaction and deasserting the device chip select [n_ss_out]. By default the chip select will be deasserted on the cycle following the.." newline hexmask.long.byte 0xC 0.--7. 1. "D_INIT_FLD,Clock Delay with n_ss_out: Delay in master reference clocks between setting n_ss_out low and first bit transfer." line.long 0x10 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_rd_data_capture_reg,Read Data Capture Register" hexmask.long.byte 0x10 16.--19. 1. "DDR_READ_DELAY_FLD,DDR read delay: Delay the transmitted data by the programmed number of ref_clk cycles.This field is only relevant when DDR Read Command is executed. Otherwise can be ignored." newline bitfld.long 0x10 8. "DQS_ENABLE_FLD,DQS enable bit: If enabled signal from DQS input is driven into RX DLL and is used for data capturing in PHY Mode rather than internally generated gated ref_clk.." "0,1" newline bitfld.long 0x10 5. "SAMPLE_EDGE_SEL_FLD,Sample edge selection: Choose edge on which data outputs from flash memory will be sampled" "0,1" newline hexmask.long.byte 0x10 1.--4. 1. "DELAY_FLD,Read Delay: Delay the read data capturing logic by the programmed number of ref_clk cycles" newline bitfld.long 0x10 0. "BYPASS_FLD,Bypass the adapted loopback clock circuit" "0,1" line.long 0x14 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_size_config_reg,Device Size Configuration Register" bitfld.long 0x14 27.--28. "MEM_SIZE_ON_CS3_FLD,Size of Flash Device connected to CS[3] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "0: size of 512Mb,1: size of 1Gb,?,?" newline bitfld.long 0x14 25.--26. "MEM_SIZE_ON_CS2_FLD,Size of Flash Device connected to CS[2] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "0: size of 512Mb,1: size of 1Gb,?,?" newline bitfld.long 0x14 23.--24. "MEM_SIZE_ON_CS1_FLD,Size of Flash Device connected to CS[1] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "0: size of 512Mb,1: size of 1Gb,?,?" newline bitfld.long 0x14 21.--22. "MEM_SIZE_ON_CS0_FLD,Size of Flash Device connected to CS[0] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "0: size of 512Mb,1: size of 1Gb,?,?" newline hexmask.long.byte 0x14 16.--20. 1. "BYTES_PER_SUBSECTOR_FLD,Number of bytes per Block. This is required by the controller for performing the write protection logic. The number of bytes per block must be a power of 2 number." newline hexmask.long.word 0x14 4.--15. 1. "BYTES_PER_DEVICE_PAGE_FLD,Number of bytes per device page. This is required by the controller for performing FLASH writes up to and across page boundaries." newline hexmask.long.byte 0x14 0.--3. 1. "NUM_ADDR_BYTES_FLD,Number of address bytes. A value of 0 indicates 1 byte." line.long 0x18 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_sram_partition_cfg_reg,SRAM Partition Configuration Register" hexmask.long.byte 0x18 0.--7. 1. "ADDR_FLD,Indirect Read Partition Size: Defines the size of the indirect read partition in the SRAM in units of SRAM locations. By default half of the SRAM is reserved for indirect read operation and half for indirect write. The size of this register.." line.long 0x1C "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_ind_AHB_addr_trigger_reg,Indirect AHB Address Trigger Register" hexmask.long 0x1C 0.--31. 1. "ADDR_FLD,This is the base address that will be used by the AHB controller. When the incoming AHB read access address matches a range of addresses from this trigger address to the trigger address + 15 then the AHB request will be completed by fetching.." line.long 0x20 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dma_periph_config_reg,DMA Peripheral Configuration Register" hexmask.long.byte 0x20 8.--11. 1. "NUM_BURST_REQ_BYTES_FLD,Number of Burst Bytes: Number of bytes in a burst type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The actual.." newline hexmask.long.byte 0x20 0.--3. 1. "NUM_SINGLE_REQ_BYTES_FLD,Number of Single Bytes: Number of bytes in a single type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The.." line.long 0x24 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_remap_addr_reg,Remap Address Register" hexmask.long 0x24 0.--31. 1. "VALUE_FLD,This register is used to remap an incoming AHB address to a different address used by the FLASH device." line.long 0x28 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_mode_bit_config_reg,Mode Bit Configuration Register" hexmask.long.byte 0x28 24.--31. 1. "RX_CRC_DATA_LOW_FLD,RX CRC data [lower] The first CRC byte returned after RX data chunk." newline hexmask.long.byte 0x28 16.--23. 1. "RX_CRC_DATA_UP_FLD,RX CRC data [upper] The second CRC byte returned after RX data chunk." newline bitfld.long 0x28 15. "CRC_OUT_ENABLE_FLD,CRC# output enable bit When enabled the controller expects the Flash Device to toggle CRC data on both SPI clock edges in CRC->CRC# sequence and calculates CRC compliance accordingly." "0,1" newline bitfld.long 0x28 8.--10. "CHUNK_SIZE_FLD,It defines size of chunk after which CRC data is expected to show up on the SPI interface for write and read data transfers." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x28 0.--7. 1. "MODE_FLD,These are the 8 mode bits that are sent to the device following the address bytes if mode bit transmission has been enabled." rgroup.long 0x2C++0x3 line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_sram_fill_reg,SRAM Fill Register" hexmask.long.word 0x0 16.--31. 1. "SRAM_FILL_INDAC_WRITE_FLD,SRAM Fill Level [Indirect Write Partition]: Identifies the current fill level of the SRAM Indirect Write partition" newline hexmask.long.word 0x0 0.--15. 1. "SRAM_FILL_INDAC_READ_FLD,SRAM Fill Level [Indirect Read Partition]: Identifies the current fill level of the SRAM Indirect Read partition" rgroup.long 0x30++0x17 line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_tx_thresh_reg,TX Threshold Register" hexmask.long.byte 0x0 0.--4. 1. "LEVEL_FLD,Defines the level at which the small TX FIFO not full interrupt is generated" line.long 0x4 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_rx_thresh_reg,RX Threshold Register" hexmask.long.byte 0x4 0.--4. 1. "LEVEL_FLD,Defines the level at which the small RX FIFO not empty interrupt is generated" line.long 0x8 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_write_completion_ctrl_reg,Write Completion Control Register: This register defines how the controller will poll the device following a write transfer" hexmask.long.byte 0x8 24.--31. 1. "POLL_REP_DELAY_FLD,Defines additional delay for maintain Chip Select de-asserted during auto-polling phase" newline hexmask.long.byte 0x8 16.--23. 1. "POLL_COUNT_FLD,Defines the number of times the controller should expect to see a true result from the polling in successive reads of the device register." newline bitfld.long 0x8 15. "ENABLE_POLLING_EXP_FLD,Set to '1' for enabling auto-polling expiration." "0,1" newline bitfld.long 0x8 14. "DISABLE_POLLING_FLD,This switches off the automatic polling function" "0,1" newline bitfld.long 0x8 13. "POLLING_POLARITY_FLD,Defines the polling polarity. If '1' then the write transfer to the device will be complete if the polled bit is equal to '1'. If '0' then the write transfer to the device will be complete if the polled bit is equal to '0'." "0,1" newline bitfld.long 0x8 8.--10. "POLLING_BIT_INDEX_FLD,Defines the bit index that should be polled. A value of 010 means that bit 2 of the returned data will be polled for.A value of 111 means that bit 7 of the returned data will be polled for." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "OPCODE_FLD,Defines the opcode that should be issued by the controller when it is automatically polling for device program completion. This command is issued followed all device write operations. By default this will poll the standard device STATUS.." line.long 0xC "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_no_of_polls_bef_exp_reg,Polling Expiration Register" hexmask.long 0xC 0.--31. 1. "NO_OF_POLLS_BEF_EXP_FLD,Number of polls cycles before expiration" line.long 0x10 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_irq_status_reg,Interrupt Status Register: The status fields in this register are set when the described event occurs and the interrupt is enabled in the mask register. When any of.." bitfld.long 0x10 19. "ECC_FAIL_FLD,ECC failure This interrupt informs the system that Flash Device reported ECC error." "0,1" newline bitfld.long 0x10 18. "TX_CRC_CHUNK_BRK_FLD,TX CRC chunk was broken This interrupt informs the system that program page SPI transfer was discontinued somewhere inside the chunk." "0,1" newline bitfld.long 0x10 17. "RX_CRC_DATA_VAL_FLD,RX CRC data valid New RX CRC data was captured from Flash Device" "0,1" newline bitfld.long 0x10 16. "RX_CRC_DATA_ERR_FLD,RX CRC data error CRC data from Flash Device does not correspond to the one dynamically calculated by the controller." "0,1" newline bitfld.long 0x10 14. "STIG_REQ_INT_FLD,The controller is ready for getting another STIG request." "0,1" newline bitfld.long 0x10 13. "POLL_EXP_INT_FLD,The maximum number of programmed polls cycles is expired" "0,1" newline bitfld.long 0x10 12. "INDRD_SRAM_FULL_FLD,Indirect Read Partition overflow: Indirect Read Partition of SRAM is full and unable to immediately complete indirect operation" "0,1" newline bitfld.long 0x10 11. "RX_FIFO_FULL_FLD,Small RX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full 1 : FIFO is full" "0: FIFO is not full,1: FIFO is full" newline bitfld.long 0x10 10. "RX_FIFO_NOT_EMPTY_FLD,Small RX FIFO not empty: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has less than RX THRESHOLD entries 1 : FIFO has >= THRESHOLD entries" "0: FIFO has less than RX THRESHOLD entries,1: FIFO has >= THRESHOLD entries" newline bitfld.long 0x10 9. "TX_FIFO_FULL_FLD,Small TX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full 1 : FIFO is full" "0: FIFO is not full,1: FIFO is full" newline bitfld.long 0x10 8. "TX_FIFO_NOT_FULL_FLD,Small TX FIFO not full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has >= THRESHOLD entries 1 : FIFO has less than THRESHOLD entries" "0: FIFO has >= THRESHOLD entries,1: FIFO has less than THRESHOLD entries" newline bitfld.long 0x10 7. "RECV_OVERFLOW_FLD,Receive Overflow: This should only occur in Legacy SPI mode. Set if an attempt is made to push the RX FIFO when it is full. This bit is reset only by a system reset and cleared only when this register is read. If a new push to the RX.." "0: no overflow has been detected,1: an overflow has occurred" newline bitfld.long 0x10 6. "INDIRECT_XFER_LEVEL_BREACH_FLD,Indirect Transfer Watermark Level Breached" "0,1" newline bitfld.long 0x10 5. "ILLEGAL_ACCESS_DET_FLD,Illegal AHB access has been detected. AHB wrapping bursts and the use of SPLIT/RETRY accesses will cause this error interrupt to trigger." "0,1" newline bitfld.long 0x10 4. "PROT_WR_ATTEMPT_FLD,Write to protected area was attempted and rejected." "0,1" newline bitfld.long 0x10 3. "INDIRECT_READ_REJECT_FLD,Indirect operation was requested but could not be accepted. Two indirect operations already in storage." "0,1" newline bitfld.long 0x10 2. "INDIRECT_OP_DONE_FLD,Indirect Operation Complete: Controller has completed last triggered indirect operation" "0,1" newline bitfld.long 0x10 1. "UNDERFLOW_DET_FLD,Underflow Detected: 0 : no underflow has been detected 1 : underflow is detected and an attempt to transfer data is made when the small TX FIFO is empty. This may occur when AHB write data is being supplied too slowly to keep up with.." "0: no underflow has been detected,1: underflow is detected and an attempt to transfer.." newline bitfld.long 0x10 0. "MODE_M_FAIL_FLD,Mode M Failure: Mode M failure indicates the voltage on pin n_ss_in is inconsistent with the SPI mode. Set =1 if n_ss_in is low in master mode [multi-master contention]. These conditions will clear the spi_enable bit and disable the SPI." "0: no mode fault has been detected,1: a mode fault has occurred" line.long 0x14 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_irq_mask_reg,Interrupt Mask: 0 : the interrupt for the corresponding interrupt status register bit is disabled." bitfld.long 0x14 19. "ECC_FAIL_MASK_FLD,ECC failure Mask" "0,1" newline bitfld.long 0x14 18. "TX_CRC_CHUNK_BRK_MASK_FLD,TX CRC chunk was broken Mask" "0,1" newline bitfld.long 0x14 17. "RX_CRC_DATA_VAL_MASK_FLD,RX CRC data valid Mask" "0,1" newline bitfld.long 0x14 16. "RX_CRC_DATA_ERR_MASK_FLD,RX CRC data error Mask" "0,1" newline bitfld.long 0x14 14. "STIG_REQ_MASK_FLD,STIG request completion Mask" "0,1" newline bitfld.long 0x14 13. "POLL_EXP_INT_MASK_FLD,Polling expiration detected Mask" "0,1" newline bitfld.long 0x14 12. "INDRD_SRAM_FULL_MASK_FLD,Indirect Read Partition overflow mask" "0,1" newline bitfld.long 0x14 11. "RX_FIFO_FULL_MASK_FLD,Small RX FIFO full Mask" "0,1" newline bitfld.long 0x14 10. "RX_FIFO_NOT_EMPTY_MASK_FLD,Small RX FIFO not empty Mask" "0,1" newline bitfld.long 0x14 9. "TX_FIFO_FULL_MASK_FLD,Small TX FIFO full Mask" "0,1" newline bitfld.long 0x14 8. "TX_FIFO_NOT_FULL_MASK_FLD,Small TX FIFO not full Mask" "0,1" newline bitfld.long 0x14 7. "RECV_OVERFLOW_MASK_FLD,Receive Overflow Mask" "0,1" newline bitfld.long 0x14 6. "INDIRECT_XFER_LEVEL_BREACH_MASK_FLD,Transfer Watermark Breach Mask" "0,1" newline bitfld.long 0x14 5. "ILLEGAL_ACCESS_DET_MASK_FLD,Illegal Access Detected Mask" "0,1" newline bitfld.long 0x14 4. "PROT_WR_ATTEMPT_MASK_FLD,Protected Area Write Attempt Mask" "0,1" newline bitfld.long 0x14 3. "INDIRECT_READ_REJECT_MASK_FLD,Indirect Read Reject Mask" "0,1" newline bitfld.long 0x14 2. "INDIRECT_OP_DONE_MASK_FLD,Indirect Complete Mask" "0,1" newline bitfld.long 0x14 1. "UNDERFLOW_DET_MASK_FLD,Underflow Detected Mask" "0,1" newline bitfld.long 0x14 0. "MODE_M_FAIL_MASK_FLD,Mode M Failure Mask" "0,1" rgroup.long 0x50++0xB line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_lower_wr_prot_reg,Lower Write Protection Register" hexmask.long 0x0 0.--31. 1. "SUBSECTOR_FLD,The block number that defines the lower block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register." line.long 0x4 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_upper_wr_prot_reg,Upper Write Protection Register" hexmask.long 0x4 0.--31. 1. "SUBSECTOR_FLD,The block number that defines the upper block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register." line.long 0x8 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_wr_prot_ctrl_reg,Write Protection Control Register" bitfld.long 0x8 1. "ENB_FLD,Write Protection Enable Bit: When set to 1 any AHB write access with an address within the protection region defined in the lower and upper write protection registers is rejected. An AHB error response is generated and an interrupt source.." "0,1" newline bitfld.long 0x8 0. "INV_FLD,Write Protection Inversion Bit: When set to 1 the protection region defined in the lower and upper write protection registers is inverted meaning it is the region that the system is permitted to write to. When set to 0 the protection region.." "0,1" rgroup.long 0x60++0x23 line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_ctrl_reg,Indirect Read Transfer Control Register" rbitfld.long 0x0 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field [bit 5]. It is incremented by hardware when an indirect operation has completed." "0,1,2,3" newline bitfld.long 0x0 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it." "0,1" newline rbitfld.long 0x0 4. "RD_QUEUED_FLD,Two indirect read operations have been queued" "0,1" newline bitfld.long 0x0 3. "SRAM_FULL_FLD,SRAM Full: SRAM full and unable to immediately complete an indirect operation. Write a 1 to this field to clear it.; indirect operation [status]" "0,1" newline rbitfld.long 0x0 2. "RD_STATUS_FLD,Indirect Read Status: Indirect read operation in progress [status]" "0,1" newline bitfld.long 0x0 1. "CANCEL_FLD,Cancel Indirect Read: Writing a 1 to this bit will cancel all ongoing indirect read operations." "0,1" newline bitfld.long 0x0 0. "START_FLD,Start Indirect Read: Writing a 1 to this bit will trigger an indirect read operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect read operation." "0,1" line.long 0x4 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_watermark_reg,Indirect Read Transfer Watermark Register" hexmask.long 0x4 0.--31. 1. "LEVEL_FLD,Watermark Value: This represents the minimum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level passes the watermark an interrupt is also generated. This field can be disabled by writing a value of all.." line.long 0x8 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_start_reg,Indirect Read Transfer Start Address Register" hexmask.long 0x8 0.--31. 1. "ADDR_FLD,This is the start address from which the indirect access will commence its READ operation." line.long 0xC "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_num_bytes_reg,Indirect Read Transfer Number Bytes Register" hexmask.long 0xC 0.--31. 1. "VALUE_FLD,This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM." line.long 0x10 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_ctrl_reg,Indirect Write Transfer Control Register" rbitfld.long 0x10 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field [bit 5]. It is incremented by hardware when an indirect operation has completed." "0,1,2,3" newline bitfld.long 0x10 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it." "0,1" newline rbitfld.long 0x10 4. "WR_QUEUED_FLD,Two indirect write operations have been queued" "0,1" newline rbitfld.long 0x10 2. "WR_STATUS_FLD,Indirect Write Status: Indirect write operation in progress [status]" "0,1" newline bitfld.long 0x10 1. "CANCEL_FLD,Cancel Indirect Write: Writing a 1 to this bit will cancel all ongoing indirect write operations." "0,1" newline bitfld.long 0x10 0. "START_FLD,Start Indirect Write: Writing a 1 to this bit will trigger an indirect write operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect write operation." "0,1" line.long 0x14 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_watermark_reg,Indirect Write Transfer Watermark Register" hexmask.long 0x14 0.--31. 1. "LEVEL_FLD,Watermark Value: This represents the maximum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level falls below the watermark an interrupt is also generated. This field can be disabled by writing a value.." line.long 0x18 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_start_reg,Indirect Write Transfer Start Address Register" hexmask.long 0x18 0.--31. 1. "ADDR_FLD,Start of Indirect Access: This is the start address from which the indirect access will commence its READ operation." line.long 0x1C "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_num_bytes_reg,Indirect Write Transfer Number Bytes Register" hexmask.long 0x1C 0.--31. 1. "VALUE_FLD,Indirect Number of Bytes: This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM." line.long 0x20 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_trigger_addr_range_reg,Indirect Trigger Address Range Register" hexmask.long.byte 0x20 0.--3. 1. "IND_RANGE_WIDTH_FLD,This is the address offset of Indirect Trigger Address Register." rgroup.long 0x8C++0xB line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_command_ctrl_mem_reg,Flash Command Control Memory Register" hexmask.long.word 0x0 20.--28. 1. "MEM_BANK_ADDR_FLD,The address of the Memory Bank which data will be read from." newline bitfld.long 0x0 16.--18. "NB_OF_STIG_READ_BYTES_FLD,It defines the number of read bytes for the extended STIG." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "MEM_BANK_READ_DATA_FLD,Last requested data from the STIG Memory Bank." newline rbitfld.long 0x0 1. "MEM_BANK_REQ_IN_PROGRESS_FLD,Memory Bank data request in progress." "0,1" newline bitfld.long 0x0 0. "TRIGGER_MEM_BANK_REQ_FLD,Trigger the Memory Bank data request." "0,1" line.long 0x4 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_cmd_ctrl_reg,Flash Command Control Register" hexmask.long.byte 0x4 24.--31. 1. "CMD_OPCODE_FLD,Command Opcode: The command opcode field should be setup before triggering the command. For example 0x20 maps to SubSector Erase. Writing to the execute field [bit 0] of this register launches the command. NOTE : Using this approach to.." newline bitfld.long 0x4 23. "ENB_READ_DATA_FLD,Read Data Enable: Set to 1 if the command specified in the command opcode field [bits 31:24] requires read data bytes to be received from the device." "0,1" newline bitfld.long 0x4 20.--22. "NUM_RD_DATA_BYTES_FLD,Number of Read Data Bytes: Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for 8 bytes." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "ENB_COMD_ADDR_FLD,Command Address Enable: Set to 1 if the command specified in bits 31:24 requires an address. This should be setup before triggering the command via writing a 1 to the execute field." "0,1" newline bitfld.long 0x4 18. "ENB_MODE_BIT_FLD,Mode Bit Enable: Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes." "0,1" newline bitfld.long 0x4 16.--17. "NUM_ADDR_BYTES_FLD,Number of Address Bytes: Set to the number of address bytes required [the address itself is programmed in the FLASH COMMAND ADDRESS REGISTERS]. This should be setup before triggering the command via bit 0 of this register. 2'b00 : 1.." "0,1,2,3" newline bitfld.long 0x4 15. "ENB_WRITE_DATA_FLD,Write Data Enable: Set to 1 if the command specified in the command opcode field requires write data bytes to be sent to the device." "0,1" newline bitfld.long 0x4 12.--14. "NUM_WR_DATA_BYTES_FLD,Number of Write Data Bytes: Up to 8 Data bytes may be written using this command Set to 0 for 1 byte 7 for 8 bytes." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 7.--11. 1. "NUM_DUMMY_CYCLES_FLD,Number of Dummy cycles: Set to the number of dummy cycles required. This should be setup before triggering the command via the execute field of this register." newline bitfld.long 0x4 2. "STIG_MEM_BANK_EN_FLD,STIG Memory Bank enable bit." "0,1" newline rbitfld.long 0x4 1. "CMD_EXEC_STATUS_FLD,Command execution in progress." "0,1" newline bitfld.long 0x4 0. "CMD_EXEC_FLD,Execute the command." "0,1" line.long 0x8 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_cmd_addr_reg,Flash Command Address Register" hexmask.long 0x8 0.--31. 1. "ADDR_FLD,Command Address: This should be setup before triggering the command with execute field [bit 0] of the Flash Command Control register. It is the address used by the command specified in the opcode field [bits 31:24] of the Flash Command Control.." rgroup.long 0xA0++0x7 line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_rd_data_lower_reg,Flash Command Read Data Register (Lower)" hexmask.long 0x0 0.--31. 1. "DATA_FLD,This is the data that is returned by the flash device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low." line.long 0x4 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_rd_data_upper_reg,Flash Command Read Data Register (Upper)" hexmask.long 0x4 0.--31. 1. "DATA_FLD,This is the data that is returned by the FLASH device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low." rgroup.long 0xA8++0x13 line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_wr_data_lower_reg,Flash Command Write Data Register (Lower)" hexmask.long 0x0 0.--31. 1. "DATA_FLD,Command Write Data Lower Byte: This is the command write data lower byte. This should be setup before triggering the command with execute field [bit 0] of the Flash Command Control register. It is the data that is to be written to the flash for.." line.long 0x4 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_wr_data_upper_reg,Flash Command Write Data Register (Upper)" hexmask.long 0x4 0.--31. 1. "DATA_FLD,Command Write Data Upper Byte: This is the command write data upper byte. This should be setup before triggering the command with execute field [bit 0] of the Flash Command Control register. It is the data that is to be written to the flash for.." line.long 0x8 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_polling_flash_status_reg,Polling Flash Status Register" hexmask.long.byte 0x8 16.--19. 1. "DEVICE_STATUS_NB_DUMMY,Number of dummy cycles for auto-polling" newline rbitfld.long 0x8 8. "DEVICE_STATUS_VALID_FLD,Device Status Valid: This should be set when value in bits from 7 to 0 is valid." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "DEVICE_STATUS_FLD,Defines actual Status Register of Device" line.long 0xC "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_phy_configuration_reg,PHY Configuration Register" bitfld.long 0xC 31. "PHY_CONFIG_RESYNC_FLD,This bit is used for re-synchronisation delay lines to update them with values from TX DLL Delay and RX DLL Delay fields." "0,1" newline bitfld.long 0xC 30. "PHY_CONFIG_RESET_FLD,DLL Reset bit: This bit is used for reset of Delay Lines by software." "0,1" newline bitfld.long 0xC 29. "PHY_CONFIG_RX_DLL_BYPASS_FLD,RX DLL Bypass: This field determines id RX DLL is bypassed." "0,1" newline hexmask.long.byte 0xC 16.--22. 1. "PHY_CONFIG_TX_DLL_DELAY_FLD,TX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and spi_clk." newline hexmask.long.byte 0xC 0.--6. 1. "PHY_CONFIG_RX_DLL_DELAY_FLD,RX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and rx_dll_clk." line.long 0x10 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_phy_master_control_reg,PHY DLL Master Control Register" bitfld.long 0x10 24. "PHY_MASTER_LOCK_MODE_FLD,Determines if the master delay line locks on a full cycle or half cycle of delay." "0,1" newline bitfld.long 0x10 23. "PHY_MASTER_BYPASS_MODE_FLD,Controls the bypass mode of the master and slave DLLs." "0,1" newline bitfld.long 0x10 20.--22. "PHY_MASTER_PHASE_DETECT_SELECTOR_FLD,Selects the number of delay elements to be inserted between the phase detect flip-flops." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 16.--18. "PHY_MASTER_NB_INDICATIONS_FLD,Holds the number of consecutive increment or decrement indications." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--6. 1. "PHY_MASTER_INITIAL_DELAY_FLD,This value is the initial delay value for the DLL." rgroup.long 0xBC++0x7 line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dll_observable_lower_reg,DLL Observable Register Lower" hexmask.long.byte 0x0 24.--31. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD,Holds the state of the cumulative dll_lock_inc register." newline hexmask.long.byte 0x0 16.--23. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD,Holds the state of the cumulative dll_lock_dec register." newline bitfld.long 0x0 15. "DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD,This bit indicates that lock of loopback is done." "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD,Reports the DLL encoder value from the master DLL to the slave DLLs." newline hexmask.long.byte 0x0 3.--7. 1. "DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD,Reports the number of increments or decrements required for the master DLL to complete the locking process." newline bitfld.long 0x0 1.--2. "DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD,Defines the mode in which the DLL has achieved the lock." "0,1,2,3" newline bitfld.long 0x0 0. "DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD,Indicates status of DLL." "0,1" line.long 0x4 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dll_observable_upper_reg,DLL Observable Register Upper" hexmask.long.byte 0x4 16.--22. 1. "DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD,Holds the encoded value for the TX delay line for this slice." newline hexmask.long.byte 0x4 0.--6. 1. "DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD,Holds the encoded value for the RX delay line for this slice." rgroup.long 0xE0++0x7 line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_opcode_ext_lower_reg,Opcode Extension Register (Lower)" hexmask.long.byte 0x0 24.--31. 1. "EXT_READ_OPCODE_FLD,Supplement byte of any Read Opcode" newline hexmask.long.byte 0x0 16.--23. 1. "EXT_WRITE_OPCODE_FLD,Supplement byte of any Write Opcode" newline hexmask.long.byte 0x0 8.--15. 1. "EXT_POLL_OPCODE_FLD,Supplement byte of any Polling Opcode" newline hexmask.long.byte 0x0 0.--7. 1. "EXT_STIG_OPCODE_FLD,Supplement byte of any STIG Opcode" line.long 0x4 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_opcode_ext_upper_reg,Opcode Extension Register (Upper)" hexmask.long.byte 0x4 24.--31. 1. "WEL_OPCODE_FLD,First byte of any WEL Opcode" newline hexmask.long.byte 0x4 16.--23. 1. "EXT_WEL_OPCODE_FLD,Supplement byte of any WEL Opcode" rgroup.long 0xFC++0x3 line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_module_id_reg,Module ID Register" hexmask.long.byte 0x0 24.--31. 1. "FIX_PATCH_FLD,Fix/path number related to revision described by 3 LSBs of this register" newline hexmask.long.word 0x0 8.--23. 1. "MODULE_ID_FLD,Module/Revision ID number" newline bitfld.long 0x0 0.--1. "CONF_FLD,Configuration ID number: 0 : OCTAL + PHY Configuration 1 : OCTAL Configuration 2 : QUAD + PHY Configuration 3 : QUAD Configuration" "0: OCTAL + PHY Configuration,1: OCTAL Configuration,2: QUAD + PHY Configuration,3: QUAD Configuration" tree.end tree "MCU_FSS0_OSPI_1_OSPI1_ECC_AGGR (MCU_FSS0_OSPI_1_OSPI1_ECC_AGGR)" base ad:0x47064000 rgroup.long 0x0++0x3 line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "OSPI1__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "OSPI1__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "OSPI1__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "OSPI1__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "OSPI1__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCU_FSS0_OSPI_1_OSPI1_R0 (MCU_FSS0_OSPI_1_OSPI1_R0)" base ad:0x600000000 rgroup.long 0x0++0x3 line.long 0x0 "OSPI1_OSPI_DATA_VBP_R0_MAP_ospi_core_mem,OSPI Core memory mapped with Region 0" hexmask.long 0x0 0.--31. 1. "OSPI_MEM,OSPI Core Mem" tree.end tree "MCU_FSS0_OSPI_1_OSPI1_R1 (MCU_FSS0_OSPI_1_OSPI1_R1)" base ad:0x58000000 rgroup.long 0x0++0x3 line.long 0x0 "OSPI1_OSPI_DATA_VBP_R1_MAP_ospi_core_mem,OSPI Core boot memory mapped with Region 1" hexmask.long 0x0 0.--31. 1. "OSPI_MEM,OSPI Core Mem" tree.end tree "MCU_FSS0_OSPI_1_OSPI1_R3 (MCU_FSS0_OSPI_1_OSPI1_R3)" base ad:0x700000000 rgroup.long 0x0++0x3 line.long 0x0 "OSPI1_OSPI_DATA_VBP_R3_MAP_ospi_core_mem,OSPI Core bypass memory mapped with Region 3" hexmask.long 0x0 0.--31. 1. "OSPI_MEM,OSPI Core Mem" tree.end tree "MCU_FSS0_OSPI_1_OSPI1_SS_CFG (MCU_FSS0_OSPI_1_OSPI1_SS_CFG)" base ad:0x47054000 rgroup.long 0x0++0x3 line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_CTRL,The Control Register contains general control bits for the ospi" bitfld.long 0x0 3. "PIPELINE_MODE_FLUSH,1 - Flush Cadence Flash Controller FIFO by forcin gAHB SEL low. 0 - AHB Sel to Cadence Controller is 1" "0: AHB Sel to Cadence Controller is 1,1: Flush Cadence Flash Controller FIFO by forcin.." rgroup.long 0x8++0x3 line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_STAT,The Status register provide general status bits for the ospi" bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" rgroup.long 0x20++0x3 line.long 0x0 "OSPI1__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targetted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" tree.end tree.end tree.end tree.end tree "MCU_I3C0" tree "MCU_I3C0_MMR_MMRVBP (MCU_I3C0_MMR_MMRVBP)" base ad:0x40B80000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__REGS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end tree "MCU_I3C0_P_ECC_AGGR_CFG (MCU_I3C0_P_ECC_AGGR_CFG)" base ad:0x40720000 rgroup.long 0x0++0x3 line.long 0x0 "P_ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "P_ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "P_ECC_AGGR__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "P_ECC_AGGR__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "P_ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "P_ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "P_ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "P_ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "P_ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "P_ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "P_ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "P_ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "P_ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "P_ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "P_ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "P_ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCU_I3C0_S_ECC_AGGR_CFG (MCU_I3C0_S_ECC_AGGR_CFG)" base ad:0x40721000 rgroup.long 0x0++0x3 line.long 0x0 "S_ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "S_ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "S_ECC_AGGR__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "S_ECC_AGGR__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "S_ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "S_ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 8. "RX_DATA_PEND,Interrupt Pending Status for rx_data_pend" "0,1" bitfld.long 0x4 7. "CMD_WRD0_PEND,Interrupt Pending Status for cmd_wrd0_pend" "0,1" bitfld.long 0x4 6. "TX_DATA_PEND,Interrupt Pending Status for tx_data_pend" "0,1" newline bitfld.long 0x4 5. "CMD_WRD1_PEND,Interrupt Pending Status for cmd_wrd1_pend" "0,1" bitfld.long 0x4 4. "IBI_PEND,Interrupt Pending Status for ibi_pend" "0,1" bitfld.long 0x4 3. "SLV_DDR_TX_PEND,Interrupt Pending Status for slv_ddr_tx_pend" "0,1" newline bitfld.long 0x4 2. "CMDR_QUEUE_PEND,Interrupt Pending Status for cmdr_queue_pend" "0,1" bitfld.long 0x4 1. "SLV_DDR_RX_PEND,Interrupt Pending Status for slv_ddr_rx_pend" "0,1" bitfld.long 0x4 0. "IBIR_QUEUE_PEND,Interrupt Pending Status for ibir_queue_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "S_ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 8. "RX_DATA_ENABLE_SET,Interrupt Enable Set Register for rx_data_pend" "0,1" bitfld.long 0x0 7. "CMD_WRD0_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd0_pend" "0,1" bitfld.long 0x0 6. "TX_DATA_ENABLE_SET,Interrupt Enable Set Register for tx_data_pend" "0,1" newline bitfld.long 0x0 5. "CMD_WRD1_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd1_pend" "0,1" bitfld.long 0x0 4. "IBI_ENABLE_SET,Interrupt Enable Set Register for ibi_pend" "0,1" bitfld.long 0x0 3. "SLV_DDR_TX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_tx_pend" "0,1" newline bitfld.long 0x0 2. "CMDR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for cmdr_queue_pend" "0,1" bitfld.long 0x0 1. "SLV_DDR_RX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_rx_pend" "0,1" bitfld.long 0x0 0. "IBIR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for ibir_queue_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "S_ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 8. "RX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for rx_data_pend" "0,1" bitfld.long 0x0 7. "CMD_WRD0_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd0_pend" "0,1" bitfld.long 0x0 6. "TX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for tx_data_pend" "0,1" newline bitfld.long 0x0 5. "CMD_WRD1_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd1_pend" "0,1" bitfld.long 0x0 4. "IBI_ENABLE_CLR,Interrupt Enable Clear Register for ibi_pend" "0,1" bitfld.long 0x0 3. "SLV_DDR_TX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_tx_pend" "0,1" newline bitfld.long 0x0 2. "CMDR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for cmdr_queue_pend" "0,1" bitfld.long 0x0 1. "SLV_DDR_RX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_rx_pend" "0,1" bitfld.long 0x0 0. "IBIR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for ibir_queue_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "S_ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "S_ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 8. "RX_DATA_PEND,Interrupt Pending Status for rx_data_pend" "0,1" bitfld.long 0x4 7. "CMD_WRD0_PEND,Interrupt Pending Status for cmd_wrd0_pend" "0,1" bitfld.long 0x4 6. "TX_DATA_PEND,Interrupt Pending Status for tx_data_pend" "0,1" newline bitfld.long 0x4 5. "CMD_WRD1_PEND,Interrupt Pending Status for cmd_wrd1_pend" "0,1" bitfld.long 0x4 4. "IBI_PEND,Interrupt Pending Status for ibi_pend" "0,1" bitfld.long 0x4 3. "SLV_DDR_TX_PEND,Interrupt Pending Status for slv_ddr_tx_pend" "0,1" newline bitfld.long 0x4 2. "CMDR_QUEUE_PEND,Interrupt Pending Status for cmdr_queue_pend" "0,1" bitfld.long 0x4 1. "SLV_DDR_RX_PEND,Interrupt Pending Status for slv_ddr_rx_pend" "0,1" bitfld.long 0x4 0. "IBIR_QUEUE_PEND,Interrupt Pending Status for ibir_queue_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "S_ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 8. "RX_DATA_ENABLE_SET,Interrupt Enable Set Register for rx_data_pend" "0,1" bitfld.long 0x0 7. "CMD_WRD0_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd0_pend" "0,1" bitfld.long 0x0 6. "TX_DATA_ENABLE_SET,Interrupt Enable Set Register for tx_data_pend" "0,1" newline bitfld.long 0x0 5. "CMD_WRD1_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd1_pend" "0,1" bitfld.long 0x0 4. "IBI_ENABLE_SET,Interrupt Enable Set Register for ibi_pend" "0,1" bitfld.long 0x0 3. "SLV_DDR_TX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_tx_pend" "0,1" newline bitfld.long 0x0 2. "CMDR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for cmdr_queue_pend" "0,1" bitfld.long 0x0 1. "SLV_DDR_RX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_rx_pend" "0,1" bitfld.long 0x0 0. "IBIR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for ibir_queue_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "S_ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 8. "RX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for rx_data_pend" "0,1" bitfld.long 0x0 7. "CMD_WRD0_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd0_pend" "0,1" bitfld.long 0x0 6. "TX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for tx_data_pend" "0,1" newline bitfld.long 0x0 5. "CMD_WRD1_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd1_pend" "0,1" bitfld.long 0x0 4. "IBI_ENABLE_CLR,Interrupt Enable Clear Register for ibi_pend" "0,1" bitfld.long 0x0 3. "SLV_DDR_TX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_tx_pend" "0,1" newline bitfld.long 0x0 2. "CMDR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for cmdr_queue_pend" "0,1" bitfld.long 0x0 1. "SLV_DDR_RX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_rx_pend" "0,1" bitfld.long 0x0 0. "IBIR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for ibir_queue_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "S_ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "S_ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "S_ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "S_ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCU_I3C0_VBP2APB_WRAP_CORE_VBP_MIPI_I3C_MST (MCU_I3C0_VBP2APB_WRAP_CORE_VBP_MIPI_I3C_MST)" base ad:0x40B88000 rgroup.long 0x0++0xF line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID,ID Register for Cadence I3C Master IP - Read Only register that provides identification information for the controller." hexmask.long.word 0x0 16.--31. 1. "RSVD0,Reserved." newline hexmask.long.word 0x0 0.--15. 1. "DEV_ID,Device ID: Unique IP identifier within Cadence IP portfolio [reset = 0x5034]." line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_CONF_STATUS0,The read-only Configuration Status Register 0 indicates the hardware configuration options chosen for implementation of I3C-Master." bitfld.long 0x4 29.--31. "CMDR_MEM_DEPTH,Indicates depth of Command Response Queue: 000 - Memory has depth of 4 001 - Memory has depth of 8 010 - Memory has depth of 16 011 - Memory has depth of 32 100 - Memory.." "0: Memory has depth of 4 001,?,?,?,?,?,?,?" newline hexmask.long.byte 0x4 24.--28. 1. "ASF,Indicates supported ASF checks: asf[4] - ECC Check enabled asf[3] - Integrity Check enabled asf[2] - CSR/DAP Check enabled asf[1] - Trans. Timeout Check enabled asf[0] - Protocol.." newline hexmask.long.byte 0x4 16.--23. 1. "GPO_NUM,Returns the value of User GPO [1-126]." newline hexmask.long.byte 0x4 8.--15. 1. "GPI_NUM,Returns the value of User GPI [1-126]." newline bitfld.long 0x4 6.--7. "IBIR_MEM_DEPTH,Indicates depth of IBI Response Queue: 00 - Memory has depth of 4 01 - Memory has depth of 8 10 - Memory has depth of 16 11 - Memory has depth of 32 Note: 2^[2 +.." "0: Memory has depth of 4 01,?,?,?" newline bitfld.long 0x4 5. "DDR,Indicates if DDR is supported." "0,1" newline bitfld.long 0x4 4. "DEV_ROLE,Returns status of Device Role [MM/SM]: 0 - Main Master 1 - Secondary Master" "0: Main Master 1,?" newline hexmask.long.byte 0x4 0.--3. 1. "DEVS_NUM,Returns the number of retaining registers for I3C Slave devices [Addresses and Characteristics] the max value is 11." line.long 0x8 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_CONF_STATUS1,The read-only Configuration Status Register 1 indicates the hardware configuration options chosen for implementation of I3C-Master." hexmask.long.byte 0x8 28.--31. 1. "IBI_HW_RES,Indicates HW resources for IBI capable devices: 0000 - SIR map for 1 Slave device 0001 - SIR map for 2 Slave devices ... 1010 - SIR map for 11 Slave devices 1101 - 1111 -.." newline bitfld.long 0x8 26.--27. "CMD_MEM_DEPTH,Indicates depth of Command Memories [0 and 1]: 00 - Memory has depth of 4 01 - Memory has depth of 8 10 - Memory has depth of 16 11 - Memory has depth of 32 Note: 2^[2 +.." "0: Memory has depth of 4 01,?,?,?" newline hexmask.long.byte 0x8 21.--25. 1. "SLV_DDR_RX_MEM_DEPTH,Indicates depth of Slave DDR Rx Memory: 00000 - Memory has depth of 8 00001 - Memory has depth of 16 ... 01101 - Memory has depth of 65536 01110 - 11111 - N/A.." newline hexmask.long.byte 0x8 16.--20. 1. "SLV_DDR_TX_MEM_DEPTH,Indicates depth of Slave DDR Tx Memory: 00000 - Memory has depth of 8 00001 - Memory has depth of 16 ... 01101 - Memory has depth of 65536 01110 - 11111 - N/A.." newline bitfld.long 0x8 13.--15. "RSVD0,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 10.--12. "IBI_MEM_DEPTH,Indicates depth of In-Band Interrupt Memory: 000 - Memory has depth of 2 001 - Memory has depth of 4 ... 101 - Memory has depth of 64 110 - 111 - N/A Note:.." "0: Memory has depth of 2 001,?,?,?,?,?,?,?" newline hexmask.long.byte 0x8 5.--9. 1. "RX_MEM_DEPTH,Indicates depth of Rx Data Memory: 00000 - Memory has depth of 8 00001 - Memory has depth of 16 ... 01101 - Memory has depth of 65536 01110 - 11111 - N/A.." newline hexmask.long.byte 0x8 0.--4. 1. "TX_MEM_DEPTH,Indicates depth of Tx Data Memory: 00000 - Memory has depth of 8 00001 - Memory has depth of 16 ... 01101 - Memory has depth of 65536 01110 - 11111 - N/A.." line.long 0xC "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_REV_ID,This register gives an information about particular version of the IP." hexmask.long.word 0xC 20.--31. 1. "VID,VENDOR_ID: IP vendor ID affected to Cadence I3C Master controller [reset = 0xCAD]." newline hexmask.long.word 0xC 8.--19. 1. "PID,PRODUCT_ID: unique IP identifier within CDNS IP portfolio [reset = 0x13C]." newline bitfld.long 0xC 5.--7. "REV_MAJOR,X: Major revision value [1]. rXYYv1p0 - current version r105v1p0" "0: current version r105v1p0,?,?,?,?,?,?,?" newline hexmask.long.byte 0xC 0.--4. 1. "REV_MINOR,Y: Minor revision value [05]. rXYYv1p0 - current version r105v1p0" rgroup.long 0x10++0xB line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_CTRL,Control Register for Cadence I3C Master IP - register that provides main control and configuration options for the controller." bitfld.long 0x0 31. "DEV_EN,When set HIGH the I3C-Master is enabled and it can initiates the I3C/I2C transactions. Also write access to the following fields of various registers is forbidden : CTRL.bus_mode CTRL.ahdr_opt.." "0,1" newline bitfld.long 0x0 30. "HALT_EN,Enable[1]/Disable[0] Halt on Abort function." "0,1" newline bitfld.long 0x0 29. "MCS,Manual Command Start writing 1 starts execution of the commands currently in CMD Memories. Self-cleared bit. Relevant only if MCS_EN bit [CTRL.mcs_en] set to 1 disregarded otherwise." "0,1" newline bitfld.long 0x0 28. "MCS_EN,Manual Command Start Enable if set 1 the IP will wait with starting of command execution until MCS but [CTRL.mcs] would be set 1. If set to 0 the IP will start execute commands automatically as soon as at lease one is present in the.." "0,1" newline rbitfld.long 0x0 27. "RSVD2,Reserved." "0,1" newline bitfld.long 0x0 26. "I3C_11_SUPP,Enables support for timing parameter that has been changed in v1.1 i.e. tCASr_min. If: - 1'b0 - then tCASr_min = tCAS_min [as per MIPI spec v1.0] - 1'b1 - then tCASr_min = tCAS_min/2 [as per draft version of MIPI.." "0: then tCASr_min = tCAS_min [as per MIPI spec v1,1: then tCASr_min = tCAS_min/2 [as per draft.." newline bitfld.long 0x0 24.--25. "THD_DEL,Data Hold Time Delay field that provides option to add data hold delay with respect to the SCL clock on which data on SDA is launched [applied only during actual Data transfer]: 00 - adds delay of 3x sys_clk clock.." "0: adds delay of 3x sys_clk clock cycles 01,?,?,?" newline hexmask.long.word 0x0 9.--23. 1. "RSVD1,Reserved." newline bitfld.long 0x0 8. "HJ_DISEC,This bit controls the HW response for ACK'ed HJ request. When set HIGH then the DISEC CCC is used. Otherwise if set LOW the ENTDAA CCC is used. This control bit is meaningful if hj_ack=1 and controller operates in Main Master.." "0,1" newline bitfld.long 0x0 7. "MST_ACK,Specifies ACK response type for GETACCMST CCC it can be either ACK response type [mst_ack = 1] or NACK response type [mst_ack = 0]. This control bit is meaningful in Slave Mode only." "0,1" newline bitfld.long 0x0 6. "HJ_ACK,Specifies ACK response type for HJ request it can be either ACK response type [hj_ack = 1] or NACK response type [hj_ack = 0]. For Secondary Master configuration this bit tied off to 0." "0,1" newline bitfld.long 0x0 5. "HJ_INIT,Initiate HJ request - applicable only for Secondary master in slave mode. Self-cleared bit." "0,1" newline bitfld.long 0x0 4. "MST_INIT,Initiate Mastership request - applicable only in slave mode. When set in master mode this bit has no effect. Self-cleared bit." "0,1" newline bitfld.long 0x0 3. "AHDR_OPT,Enable[1]/Disable[0] the Address Header optimization. If enabled FW needs to restrict DAs to 0x03 - 0x3F range." "0,1" newline bitfld.long 0x0 0.--1. "BUS_MODE,Bus Mode 00 : Pure Bus Mode 01 : Invalid Config 10 : Mixed Fast Bus Mode 11 : Mixed Slow/Limited Bus Mode" "0: Pure Bus Mode,1: Invalid Config,?,?" line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_PRESCL_CTRL0,Prescale settings for SDR/I2C modes" hexmask.long.word 0x4 16.--31. 1. "I2C,Prescaler value for I2C SCL clock generation. It should be generated based on sys clock freq and should be 5x w.r.t. to the slowest I2C device's SCL speed: presc_ctl_i2c[15:0] = sys_clk_freq / [i2c_freq * 5] - 1'b1.." newline hexmask.long.word 0x4 0.--9. 1. "I3C,Prescaler value for I3C Push-Pull SDR Mode SCL clock generation. When the bus is configured in mixed fast mode the resulting SCL frequency must be faster than 11MHz. It should be generated based on sys clock freq and.." line.long 0x8 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_PRESCL_CTRL1,Prescale settings related to Open Drain / Push Pull I3C timings" hexmask.long.byte 0x8 8.--15. 1. "PP_LOW,Counter for low period of SCL clock for Push Pull in I3C. When particular I3C device does not support Max SCL speed low period stretching is required for PP as well. Controller will determine that by inspecting BCR[0].." newline hexmask.long.byte 0x8 0.--7. 1. "OD_LOW,Counter for low period of SCL clock for Open Drain in I3C. SCL waveform will have constant asymmetric ratio in OD as it will be calculated by 1/4 SCL * [od_low + 2]. The resolution used is 1/4 SDR SCL clock. FW need to.." rgroup.long 0x20++0x7 line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_MST_IER,The write only Interrupt Enable Register is used to enable interrupts by setting bits in the read only Interrupt Mask Register - Master Mode (MST_IMR)." hexmask.long.word 0x0 19.--31. 1. "RSVD1,Reserved." newline bitfld.long 0x0 18. "HALTED,Controller in halted state." "0,1" newline bitfld.long 0x0 17. "MR_DONE,Mastership handoff done Enable." "0,1" newline bitfld.long 0x0 16. "IMM_COMP,Immediate Commmand Completed Enable" "0,1" newline bitfld.long 0x0 15. "TX_THR,Tx Data Threshold Enable." "0,1" newline bitfld.long 0x0 14. "TX_OVF,Tx Data MEM Underflow Enable" "0,1" newline bitfld.long 0x0 13. "RSVD0,Reserved." "0,1" newline bitfld.long 0x0 12. "IBID_THR,IBI Data MEM threshold Enable." "0,1" newline bitfld.long 0x0 11. "IBID_UNF,IBI Data MEM underflow Enable." "0,1" newline bitfld.long 0x0 10. "IBIR_THR,IBI Response Queue threshold Enable" "0,1" newline bitfld.long 0x0 9. "IBIR_UNF,IBI Response Queue underflow Enable" "0,1" newline bitfld.long 0x0 8. "IBIR_OVF,IBI Response Queue onverflow Enable." "0,1" newline bitfld.long 0x0 7. "RX_THR,Rx Data MEM threshold Enable." "0,1" newline bitfld.long 0x0 6. "RX_UNF,Rx Data MEM underflow Enable." "0,1" newline bitfld.long 0x0 5. "CMDD_EMP,Command Request Queue Empty Enable." "0,1" newline bitfld.long 0x0 4. "CMDD_THR,Command Request Queue Threshold Enable." "0,1" newline bitfld.long 0x0 3. "CMDD_OVF,Command Request Queue Overflow Enable." "0,1" newline bitfld.long 0x0 2. "CMDR_THR,Command Response Queue Threshold Enable." "0,1" newline bitfld.long 0x0 1. "CMDR_UNF,Command Response Queue Underflow Enable." "0,1" newline bitfld.long 0x0 0. "CMDR_OVF,Command Response Queue Overflow Enable." "0,1" line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_MST_IDR,The write only Interrupt Disable Register is used to disable interrupts by clearing the bits in the read only Interrupt Mask Register - Master Mode (MST_IMR)." hexmask.long.word 0x4 19.--31. 1. "RSVD1,Reserved." newline bitfld.long 0x4 18. "HALTED,Controller in halted state." "0,1" newline bitfld.long 0x4 17. "MR_DONE,Mastership handoff done Disable." "0,1" newline bitfld.long 0x4 16. "IMM_COMP,Immediate Commmand Completed Disable" "0,1" newline bitfld.long 0x4 15. "TX_THR,Tx Data Threshold Disable." "0,1" newline bitfld.long 0x4 14. "TX_OVF,Tx Data MEM Underflow Disable" "0,1" newline bitfld.long 0x4 13. "RSVD0,Reserved." "0,1" newline bitfld.long 0x4 12. "IBID_THR,IBI Data MEM threshold Disable." "0,1" newline bitfld.long 0x4 11. "IBID_UNF,IBI Data MEM underflow Disable." "0,1" newline bitfld.long 0x4 10. "IBIR_THR,IBI Response Queue threshold Disable" "0,1" newline bitfld.long 0x4 9. "IBIR_UNF,IBI Response Queue underflow Disable" "0,1" newline bitfld.long 0x4 8. "IBIR_OVF,IBI Response Queue onverflow Disable." "0,1" newline bitfld.long 0x4 7. "RX_THR,Rx Data MEM threshold Disable." "0,1" newline bitfld.long 0x4 6. "RX_UNF,Rx Data MEM underflow Disable." "0,1" newline bitfld.long 0x4 5. "CMDD_EMP,Command Request Queue Empty Disable." "0,1" newline bitfld.long 0x4 4. "CMDD_THR,Command Request Queue Threshold Disable." "0,1" newline bitfld.long 0x4 3. "CMDD_OVF,Command Request Queue Overflow Disable." "0,1" newline bitfld.long 0x4 2. "CMDR_THR,Command Response Queue Threshold Disable." "0,1" newline bitfld.long 0x4 1. "CMDR_UNF,Command Response Queue Underflow Disable." "0,1" newline bitfld.long 0x4 0. "CMDR_OVF,Command Response Queue Overflow Disable." "0,1" rgroup.long 0x28++0x3 line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_MST_IMR,This read only register. indicates the current state of the interrupts mask." hexmask.long.word 0x0 19.--31. 1. "RSVD1,Reserved." newline bitfld.long 0x0 18. "HALTED,Controller in halted state." "0,1" newline bitfld.long 0x0 17. "MR_DONE,Mastership handoff done Mask." "0,1" newline bitfld.long 0x0 16. "IMM_COMP,Immediate Commmand Completed Mask" "0,1" newline bitfld.long 0x0 15. "TX_THR,Tx Data Threshold Mask." "0,1" newline bitfld.long 0x0 14. "TX_OVF,Tx Data MEM Underflow Mask" "0,1" newline bitfld.long 0x0 13. "RSVD0,Reserved." "0,1" newline bitfld.long 0x0 12. "IBID_THR,IBI Data MEM threshold Mask." "0,1" newline bitfld.long 0x0 11. "IBID_UNF,IBI Data MEM underflow Mask." "0,1" newline bitfld.long 0x0 10. "IBIR_THR,IBI Response Queue threshold Mask" "0,1" newline bitfld.long 0x0 9. "IBIR_UNF,IBI Response Queue underflow Mask" "0,1" newline bitfld.long 0x0 8. "IBIR_OVF,IBI Response Queue onverflow Mask." "0,1" newline bitfld.long 0x0 7. "RX_THR,Rx Data MEM threshold Mask." "0,1" newline bitfld.long 0x0 6. "RX_UNF,Rx Data MEM underflow Mask." "0,1" newline bitfld.long 0x0 5. "CMDD_EMP,Command Request Queue Empty Mask." "0,1" newline bitfld.long 0x0 4. "CMDD_THR,Command Request Queue Threshold Mask." "0,1" newline bitfld.long 0x0 3. "CMDD_OVF,Command Request Queue Overflow Mask." "0,1" newline bitfld.long 0x0 2. "CMDR_THR,Command Response Queue Threshold Mask." "0,1" newline bitfld.long 0x0 1. "CMDR_UNF,Command Response Queue Underflow Mask." "0,1" newline bitfld.long 0x0 0. "CMDR_OVF,Command Response Queue Overflow Mask." "0,1" rgroup.long 0x2C++0x3 line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_MST_ICR,Interrupt Clear Register for Master Mode of the cdnsi3c_master controller. Write 1 to clear (change from 1 to 0) corresponding bit in MST_ISR. Writing 0 has no effect" hexmask.long.word 0x0 19.--31. 1. "RSVD1,Reserved." newline bitfld.long 0x0 18. "HALTED,Controller is in halted state." "0,1" newline bitfld.long 0x0 17. "MR_DONE,Mastership handoff done Mask." "0,1" newline bitfld.long 0x0 16. "IMM_COMP,Immediate Commmand Completed Mask" "0,1" newline bitfld.long 0x0 15. "TX_THR,Tx Data Threshold Mask." "0,1" newline bitfld.long 0x0 14. "TX_OVF,Tx Data MEM Underflow Mask" "0,1" newline bitfld.long 0x0 13. "RSVD0,Reserved." "0,1" newline bitfld.long 0x0 12. "IBID_THR,IBI Data MEM threshold Mask." "0,1" newline bitfld.long 0x0 11. "IBID_UNF,IBI Data MEM underflow Mask." "0,1" newline bitfld.long 0x0 10. "IBIR_THR,IBI Response Queue threshold Mask" "0,1" newline bitfld.long 0x0 9. "IBIR_UNF,IBI Response Queue underflow Mask" "0,1" newline bitfld.long 0x0 8. "IBIR_OVF,IBI Response Queue onverflow Mask." "0,1" newline bitfld.long 0x0 7. "RX_THR,Rx Data MEM threshold Mask." "0,1" newline bitfld.long 0x0 6. "RX_UNF,Rx Data MEM underflow Mask." "0,1" newline bitfld.long 0x0 5. "CMDD_EMP,Command Request Queue Empty Mask." "0,1" newline bitfld.long 0x0 4. "CMDD_THR,Command Request Queue Threshold Mask." "0,1" newline bitfld.long 0x0 3. "CMDD_OVF,Command Request Queue Overflow Mask." "0,1" newline bitfld.long 0x0 2. "CMDR_THR,Command Response Queue Threshold Mask." "0,1" newline bitfld.long 0x0 1. "CMDR_UNF,Command Response Queue Underflow Mask." "0,1" newline bitfld.long 0x0 0. "CMDR_OVF,Command Response Queue Overflow Mask." "0,1" rgroup.long 0x30++0x3 line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_MST_ISR,Interrupt Status Register for Master Mode of the cdnsi3c_master controller" hexmask.long.word 0x0 19.--31. 1. "RSVD1,Reserved." newline bitfld.long 0x0 18. "HALTED,Controller in Halted state. This event is asserted on the second abort has occured during Read operation [if CTRL.halt_en=1] or in case of Rx DATA Buffer is full [regardless of CTRL.halt_en state]." "0,1" newline bitfld.long 0x0 17. "MR_DONE,Mastership handoff Done. This event is triggered whenever Mastership Request procedure is completed." "0,1" newline bitfld.long 0x0 16. "IMM_COMP,Immediate Commmand Completed. Is asserted when immediate command is completed." "0,1" newline bitfld.long 0x0 15. "TX_THR,Tx DATA Buffer Threshold. It is set when number of bytes in the Tx DATA Buffer reaches value programmed in the TX_RX_THR_CTRL.tx_thr field." "0,1" newline bitfld.long 0x0 14. "TX_OVF,Tx DATA Buffer Overflow. Set if host attempts to write to Tx DATA Buffer which is already full" "0,1" newline bitfld.long 0x0 13. "RSVD0,Reserved." "0,1" newline bitfld.long 0x0 12. "IBID_THR,IBI DATA Buffer Threshold. It is set when number of butes in the IBI DATA Buffer reaches value programmed in the CMD_IBI_THR_CTRL.ibid_thr field." "0,1" newline bitfld.long 0x0 11. "IBID_UNF,IBI DATA Buffer Underflow. It is set when FW attempts to read from empty IBI DATA Buffer." "0,1" newline bitfld.long 0x0 10. "IBIR_THR,IBI Response Buffer Threshold. It is set when number of butes in the IBI Response Buffer reaches value programmed in the CMD_IBI_THR_CTRL.ibir_thr field." "0,1" newline bitfld.long 0x0 9. "IBIR_UNF,IBI Response Buffer Underflow. It is set when FW attempts to read from empty IBI Response Buffer." "0,1" newline bitfld.long 0x0 8. "IBIR_OVF,IBI Response Buffer Overflow. Set if the new slave-initiated request is received while IBI Response Buffer is already full." "0,1" newline bitfld.long 0x0 7. "RX_THR,Rx Data Buffer Threshold. It is set when number of bytes in the Rx DATA Buffer reaches value programmed in the TX_RX_THR_CTRL.rx_thr field." "0,1" newline bitfld.long 0x0 6. "RX_UNF,Rx Data Buffer Underflow. Set if the host attempts to read from the empty Rx DATA Buffer." "0,1" newline bitfld.long 0x0 5. "CMDD_EMP,Command Request Queue Empty. It is set as soon as the last command in the Command Queue is completed [simultaneously with comp flag]." "0,1" newline bitfld.long 0x0 4. "CMDD_THR,Command Request Queue Threshold. It is set when number of bytes in the Command Buffer reaches value programmed in the CMD_IBI_THR_CTRL.cmdd_thr field." "0,1" newline bitfld.long 0x0 3. "CMDD_OVF,Command Request Queue Overflow. It is set whenever Command Buffer is full and a new command is received from the host. In this case contents of the Command Buffer remains unchanged." "0,1" newline bitfld.long 0x0 2. "CMDR_THR,Command Response Queue Threshold. It is set when number of bytes in the Command Response Buffer reaches value programmed in the CMD_IBI_THR_CTRL.cmdr_thr field." "0,1" newline bitfld.long 0x0 1. "CMDR_UNF,Command Response Queue Underflow. It is set when FW attempts to read from empty Command Response Buffer." "0,1" newline bitfld.long 0x0 0. "CMDR_OVF,Command Response Queue Overflow. It is set whenever Command Response Buffer is full and a new response is received. In this case contents of the Command Response Buffer remains unchanged." "0,1" rgroup.long 0x34++0x3 line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_MST_STATUS0,Status Register for Cadence I3C Master IP. meaningful only when controller operates in Master mode." rbitfld.long 0x0 18. "IDLE,Indicates when the core is IDLE and ready to accept new commands. When CTRL.dev_en is deasserted FW should poll this reg in order to ensure that core completed its last command. It is advisable to use this bit in order to ensure that currently the.." "0,1" newline bitfld.long 0x0 17. "HALTED,Core Halted. This status bit will be asserted on the second abort has occurred during Read operation [if CTRL.halt_en=1] or in case of Rx DATA FIFO is full [regardless of CTRL.halt_en state]. Writing 1 will unhalt the controllers operation." "0,1" newline rbitfld.long 0x0 16. "OP_MODE,Indicates current mode of the controller: 0 - Slave mode; 1 - Master mode. For Main Master configuration the reset value is 1 For Secondary Master configuration the reset value is 0.." "0: Slave mode; 1,?" newline rbitfld.long 0x0 14.--15. "RSVD1,Reserved." "0,1,2,3" newline rbitfld.long 0x0 13. "TX_FULL,Tx DATA Memory is Full." "0,1" newline rbitfld.long 0x0 12. "IBID_FULL,IBI DATA Memory is Full." "0,1" newline rbitfld.long 0x0 11. "IBIR_FULL,IBI Response Queue is Full." "0,1" newline rbitfld.long 0x0 10. "RX_FULL,Rx DATA Memory is Full." "0,1" newline rbitfld.long 0x0 9. "CMDD_FULL,CMD DATA Queue is Full." "0,1" newline rbitfld.long 0x0 8. "CMDR_FULL,CMD Response Queue is Full." "0,1" newline rbitfld.long 0x0 6.--7. "RSVD0,Reserved." "0,1,2,3" newline rbitfld.long 0x0 5. "TX_EMP,TX DATA Memory is Empty." "0,1" newline rbitfld.long 0x0 4. "IBID_EMP,IBI DATA Memory is Empty." "0,1" newline rbitfld.long 0x0 3. "IBIR_EMP,IBI Response Queue is Empty." "0,1" newline rbitfld.long 0x0 2. "RX_EMP,RX DATA Memory is Empty." "0,1" newline rbitfld.long 0x0 1. "CMDD_EMP,CMD Descriptor Queue is Empty." "0,1" newline rbitfld.long 0x0 0. "CMDR_EMP,CMD Response Queue is Empty." "0,1" rgroup.long 0x38++0x7 line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_CMDR,Command Response Queue - stores status on completion of each command. works on FIFO-basis." hexmask.long.byte 0x0 28.--31. 1. "RSVD1,Reserved." newline hexmask.long.byte 0x0 24.--27. 1. "ERROR,Error Code - contains the code of an error that has occured during command execution: - 4'h0: No Error - 4'h1: DDR Preamble Error - 4'h2: DDR Parity Error - 4'h3: DDR Rx FIFO Overflow .." newline hexmask.long.byte 0x0 20.--23. 1. "RSVD0,Reserved." newline hexmask.long.word 0x0 8.--19. 1. "XFER_BYTES,The number of transferred bytes [SDR] or transferred words [DDR] during command execution. Will be set correctly for CCC commands as well even for those without payload [to zero value]." newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ID,Command Identifier - equals to the value of CMD_ID field of Command Descriptor for given command. There are following exceptions in a form of HW-initiated commands: - DAA after HJ-ACK response - ID field is returned as 8'hFF.." line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_IBIR,Stores status of SIR on its completion. works on FIFO-basis." bitfld.long 0x4 12. "RESP,Master response. If set HIGH then IBI has been ACKed NACK response otherwise." "0,1" newline hexmask.long.byte 0x4 8.--11. 1. "SLV_ID,ID of slave that issued the request as stored in retaining registers." newline bitfld.long 0x4 7. "ERROR,Error. Set HIGH if IBI DATA Buffer overflow has occured during the transaction." "0,1" newline hexmask.long.byte 0x4 2.--6. 1. "XFER_BYTES,Number of received DATA bytes." newline bitfld.long 0x4 0.--1. "IBI_TYPE,Type of IBI Request. This field contains the type of serviced IBI message. Type codes: - 2'h0: In-Band Interrupt - 2'h1: Hot-Join Request - 2'h2: Masterhip Takeover Request." "0: In-Band Interrupt,1: Hot-Join Request,2: Masterhip Takeover Request,?" rgroup.long 0x40++0x7 line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_SLV_IER,The write only Interrupt Enable Register is used to enable interrupts by setting bits in the read only Interrupt Mask Register - Slave Mode (SLV_IMR)." bitfld.long 0x0 21. "DEFSLVS,DEFSLVS interrupt Enable." "0,1" newline bitfld.long 0x0 20. "TM,TM interrupt Enable." "0,1" newline bitfld.long 0x0 19. "ERROR,ERROR interrupt Enable." "0,1" newline bitfld.long 0x0 18. "EVENT_UP,EVENT_UP interrupt Enable." "0,1" newline bitfld.long 0x0 17. "HJ_DONE,HJ_DONE interrupt Enable." "0,1" newline bitfld.long 0x0 16. "MR_DONE,MR_DONE interrupt Enable." "0,1" newline bitfld.long 0x0 15. "DA_UPDATE,DA_UPDATE interrupt Enable" "0,1" newline bitfld.long 0x0 14. "SDR_FAIL,SDR_FAIL interrupt Enable" "0,1" newline bitfld.long 0x0 13. "DDR_FAIL,DDR_FAIL interrupt Enable" "0,1" newline bitfld.long 0x0 12. "M_RD_ABORT,M_RD_ABORT interrupt Enable." "0,1" newline bitfld.long 0x0 11. "DDR_RX_THR,DDR_RX_THR interrupt Enable." "0,1" newline bitfld.long 0x0 10. "DDR_TX_THR,DDR_TX_THR interrupt Enable." "0,1" newline bitfld.long 0x0 9. "SDR_RX_THR,SDR_RX_THR interrupt Enable." "0,1" newline bitfld.long 0x0 8. "SDR_TX_THR,SLV_SDR_TX_THR interrupt Enable." "0,1" newline bitfld.long 0x0 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Enable." "0,1" newline bitfld.long 0x0 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Enable." "0,1" newline bitfld.long 0x0 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Enable." "0,1" newline bitfld.long 0x0 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Enable." "0,1" newline bitfld.long 0x0 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Enable." "0,1" newline bitfld.long 0x0 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Enable." "0,1" newline bitfld.long 0x0 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Enable." "0,1" newline bitfld.long 0x0 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Enable." "0,1" line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_SLV_IDR,The write only Interrupt Disable Register is used to disable interrupts by clearing the bits in the read only Interrupt Mask Register - Slave Mode (SLV_IMR)." bitfld.long 0x4 21. "DEFSLVS,DEFSLVS interrupt Disable." "0,1" newline bitfld.long 0x4 20. "TM,TM interrupt Disable." "0,1" newline bitfld.long 0x4 19. "ERROR,ERROR interrupt Disable." "0,1" newline bitfld.long 0x4 18. "EVENT_UP,EVENT_UP interrupt Disable." "0,1" newline bitfld.long 0x4 17. "HJ_DONE,HJ_DONE interrupt Disable." "0,1" newline bitfld.long 0x4 16. "MR_DONE,MR_DONE interrupt Disable." "0,1" newline bitfld.long 0x4 15. "DA_UPDATE,DA_UPDATE interrupt Disable." "0,1" newline bitfld.long 0x4 14. "SDR_FAIL,SDR_FAIL interrupt Disable" "0,1" newline bitfld.long 0x4 13. "DDR_FAIL,DDR_FAIL interrupt Disable" "0,1" newline bitfld.long 0x4 12. "M_RD_ABORT,M_RD_ABORT interrupt Disable." "0,1" newline bitfld.long 0x4 11. "DDR_RX_THR,DDR_RX_THR interrupt Disable." "0,1" newline bitfld.long 0x4 10. "DDR_TX_THR,DDR_TX_THR interrupt Disable." "0,1" newline bitfld.long 0x4 9. "SDR_RX_THR,SDR_RX_THR interrupt Disable." "0,1" newline bitfld.long 0x4 8. "SDR_TX_THR,SDR_TX_THR interrupt Disable." "0,1" newline bitfld.long 0x4 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Disable." "0,1" newline bitfld.long 0x4 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Disable." "0,1" newline bitfld.long 0x4 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Disable." "0,1" newline bitfld.long 0x4 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Disable." "0,1" newline bitfld.long 0x4 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Disable." "0,1" newline bitfld.long 0x4 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Disable." "0,1" newline bitfld.long 0x4 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Disable." "0,1" newline bitfld.long 0x4 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Disable." "0,1" rgroup.long 0x48++0x3 line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_SLV_IMR,This read only register. indicates the current state of the interrupts mask." bitfld.long 0x0 21. "DEFSLVS,DEFSLVS interrupt Mask." "0,1" newline bitfld.long 0x0 20. "TM,TM interrupt Mask." "0,1" newline bitfld.long 0x0 19. "ERROR,ERROR interrupt Mask." "0,1" newline bitfld.long 0x0 18. "EVENT_UP,EVENT_UP interrupt Mask." "0,1" newline bitfld.long 0x0 17. "HJ_DONE,HJ_DONE interrupt Mask." "0,1" newline bitfld.long 0x0 16. "MR_DONE,MR_DONE interrupt Mask." "0,1" newline bitfld.long 0x0 15. "DA_UPDATE,DA_UPDATE interrupt Mask." "0,1" newline bitfld.long 0x0 14. "SDR_FAIL,SDR_FAIL interrupt Mask" "0,1" newline bitfld.long 0x0 13. "DDR_FAIL,DDR_FAIL interrupt Mask" "0,1" newline bitfld.long 0x0 12. "M_RD_ABORT,M_RD_ABORT interrupt Mask." "0,1" newline bitfld.long 0x0 11. "DDR_RX_THR,DDR_RX_THR interrupt Mask." "0,1" newline bitfld.long 0x0 10. "DDR_TX_THR,DDR_TX_THR interrupt Mask." "0,1" newline bitfld.long 0x0 9. "SDR_RX_THR,SDR_RX_THR interrupt Mask." "0,1" newline bitfld.long 0x0 8. "SDR_TX_THR,SDR_TX_THR interrupt Mask." "0,1" newline bitfld.long 0x0 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Mask." "0,1" newline bitfld.long 0x0 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Mask." "0,1" newline bitfld.long 0x0 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Mask." "0,1" newline bitfld.long 0x0 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Mask." "0,1" newline bitfld.long 0x0 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Mask." "0,1" newline bitfld.long 0x0 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Mask." "0,1" newline bitfld.long 0x0 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Mask." "0,1" newline bitfld.long 0x0 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Mask." "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_SLV_ICR,Interrupt Clear Register for Slave Mode of the cdnsi3c_master controller. Write 1 to clear (change from 1 to 0) corresponding bit in SLV_ISR. Writing 0 has no effect" bitfld.long 0x0 21. "DEFSLVS,DEFSLVS interrupt Clear." "0,1" newline bitfld.long 0x0 20. "TM,TM interrupt Clear." "0,1" newline bitfld.long 0x0 19. "ERROR,ERROR interrupt Clear." "0,1" newline bitfld.long 0x0 18. "EVENT_UP,EVENT_UP interrupt Clear." "0,1" newline bitfld.long 0x0 17. "HJ_DONE,HJ_DONE interrupt Clear." "0,1" newline bitfld.long 0x0 16. "MR_DONE,MR_DONE interrupt Clear." "0,1" newline bitfld.long 0x0 15. "DA_UPDATE,DA_UPDATE interrupt Clear." "0,1" newline bitfld.long 0x0 14. "SDR_FAIL,SDR_FAIL interrupt Clear." "0,1" newline bitfld.long 0x0 13. "DDR_FAIL,DDR_FAIL interrupt Clear." "0,1" newline bitfld.long 0x0 12. "M_RD_ABORT,M_RD_ABORT interrupt Clear." "0,1" newline bitfld.long 0x0 11. "DDR_RX_THR,DDR_RX_THR interrupt Clear." "0,1" newline bitfld.long 0x0 10. "DDR_TX_THR,DDR_TX_THR interrupt Clear." "0,1" newline bitfld.long 0x0 9. "SDR_RX_THR,SDR_RX_THR interrupt Clear." "0,1" newline bitfld.long 0x0 8. "SDR_TX_THR,SDR_TX_THR interrupt Clear." "0,1" newline bitfld.long 0x0 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Clear." "0,1" newline bitfld.long 0x0 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Clear." "0,1" newline bitfld.long 0x0 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Clear." "0,1" newline bitfld.long 0x0 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Clear." "0,1" newline bitfld.long 0x0 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Clear." "0,1" newline bitfld.long 0x0 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Clear." "0,1" newline bitfld.long 0x0 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Clear." "0,1" newline bitfld.long 0x0 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Clear." "0,1" rgroup.long 0x50++0xB line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_SLV_ISR,Interrupt Status Register for Slave Mode operation" bitfld.long 0x0 21. "DEFSLVS,This interrupt is triggered whenever I3C-Slave DEFSLVS CCC command is received." "0,1" newline bitfld.long 0x0 20. "TM,This interrupt is triggered whenever I3C-Slave is not in Test Mode and ENTTM CCC requests to enter general Test Mode." "0,1" newline bitfld.long 0x0 19. "ERROR,This event is triggered whenever SDR Error is detected - applicable for S0 S1 S2 S4 and S5 Errors from MIPI spec." "0,1" newline bitfld.long 0x0 18. "EVENT_UP,This event is triggered whenever DISEC CCC or ENEC CCC is received." "0,1" newline bitfld.long 0x0 17. "HJ_DONE,This event is triggered whenever Hot-Join request is completed." "0,1" newline bitfld.long 0x0 16. "MR_DONE,This event is triggered whenever Mastership Request is completed." "0,1" newline bitfld.long 0x0 15. "DA_UPDATE,This event is triggered whenever Dynamic Address of the device has been updated." "0,1" newline bitfld.long 0x0 14. "SDR_FAIL,This event is triggered whenever fail event during SDR transfer is detected [applicable for Private Write transfers only]." "0,1" newline bitfld.long 0x0 13. "DDR_FAIL,This event is triggered whenever fail event during DDR transfer is detected." "0,1" newline bitfld.long 0x0 12. "M_RD_ABORT,Read Transfer Aborted by Master." "0,1" newline bitfld.long 0x0 11. "DDR_RX_THR,Slave DDR Rx DATA Buffer Threshold. It is set when the number of words in the Slave DDR Rx DATA Buffer reaches value programmed in SLV_DDR_TX_RX_THR_CTRL.slv_ddr_rx_thr field." "0,1" newline bitfld.long 0x0 10. "DDR_TX_THR,Slave DDR Tx DATA Buffer Threshold. It is set when the number of words in the Slave DDR Tx DATA Buffer reaches value programmed in SLV_DDR_TX_RX_THR_CTRL.slv_ddr_tx_thr field." "0,1" newline bitfld.long 0x0 9. "SDR_RX_THR,Rx DATA Buffer Threshold. It is set when the number of bytes in the Rx DATA Buffer reaches value programmed in TX_RX_THR_CTRL.rx_thr field." "0,1" newline bitfld.long 0x0 8. "SDR_TX_THR,Tx DATA Buffer Threshold. It is set when the number of bytes in the Tx DATA Buffer reaches value programmed in TX_RX_THR_CTRL.tx_thr field." "0,1" newline bitfld.long 0x0 7. "DDR_RX_UNF,Slave DDR Rx DATA Buffer Underflow. Set if host attempts to read from the empty Slave Rx DATA Buffer." "0,1" newline bitfld.long 0x0 6. "DDR_TX_OVF,Slave DDR Tx DATA Buffer Overflow. Set if host attepmts to write to Slvave DDR Tx DATA Buffer which is already full." "0,1" newline bitfld.long 0x0 5. "SDR_RX_UNF,Rx DATA Buffer Underflow. Set if host attempts to read from the empty Rx DATA Buffer." "0,1" newline bitfld.long 0x0 4. "SDR_TX_OVF,Tx DATA Buffer Overflow. Set if host attempts to write to Tx DATA Buffer which is already full." "0,1" newline bitfld.long 0x0 3. "DDR_RD_COMP,This bit is set whenever the Slave terminates the DDR Read transfer." "0,1" newline bitfld.long 0x0 2. "DDR_WR_COMP,This bit is set whenever the Master terminates the DDR Write transfer." "0,1" newline bitfld.long 0x0 1. "SDR_RD_COMP,This bit is set whenever the Slave terminates the SDR Private Read transfer." "0,1" newline bitfld.long 0x0 0. "SDR_WR_COMP,This bit is set whenever the Master terminates the SDR Private Write transfer." "0,1" line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_SLV_STATUS0,The read only Status 0 register (SLV_STATUS0) is provided to enable the continuous monitoring of the raw unmasked status information of the I3C-Master operating in Slave mode." hexmask.long.byte 0x4 16.--23. 1. "REG_ADDR,Private Read/Write Address." newline hexmask.long.word 0x4 0.--15. 1. "XFERRED_BYTES,Number of transferred bytes in SDR transactions." line.long 0x8 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_SLV_STATUS1,The read only Status 1 register (SLV_STATUS1) is provided to enable the continuous monitoring of the raw unmasked status information of the I3C-Master operating in Slave mode." bitfld.long 0x8 20.--21. "ENTAS,Bits that indicate current Activity State. It is updated based on ENTASx CCC [broadcast or direct] by default is set to 2'b00." "0,1,2,3" newline bitfld.long 0x8 19. "VEN_TM,Vendor Test Mode. This bit is set whenever ENTTM CCC requests to enter general Test Mode. It remains HIGH until reception of another ENTTM CCC with different value." "0,1" newline bitfld.long 0x8 18. "HJ_DIS,Hot-Join Request is Disabled. This bit is set whenever HJ request is disabled by Current I3C-Master using DISEC CCC." "0,1" newline bitfld.long 0x8 17. "MR_DIS,Mastership Request is Disabled. This bit is set whenever MR request is disabled by Current I3C-Master using DISEC CCC." "0,1" newline bitfld.long 0x8 16. "PROT_ERROR,Protocol Error Condition Indicator. This bit is set whenever SDR error condition is detected by I3C-Master operating in Slave mode. It remains High until detection of recovery pattern." "0,1" newline hexmask.long.byte 0x8 9.--15. 1. "DA,Current Slave Dynamic Address. Irrelevant if SLV_STATUS1.has_da bit is Low." newline bitfld.long 0x8 8. "HAS_DA,This bit is set whenever Slave has Dynamic Address assigned. Tied HIGH when controller operates as Main Master device class." "0,1" newline bitfld.long 0x8 7. "DDRRX_FULL,This bit is set whenever Slave DDR Rx DATA Buffer is full." "0,1" newline bitfld.long 0x8 6. "DDRTX_FULL,This bit is set whenever Slave DDR Tx DATA Buffer is full." "0,1" newline bitfld.long 0x8 5. "DDRRX_EMPTY,This bit is set whenever Slave DDR Rx DATA Buffer is empty." "0,1" newline bitfld.long 0x8 4. "DDRTX_EMPTY,This bit is set whenever Slave DDR Tx DATA Buffer is empty." "0,1" newline bitfld.long 0x8 3. "SDRRX_FULL,This bit is set whenever Rx DATA Buffer is full." "0,1" newline bitfld.long 0x8 2. "SDRTX_FULL,This bit is set whenever Tx DATA Buffer is full." "0,1" newline bitfld.long 0x8 1. "SDRRX_EMPTY,This bit is set whenever Rx DATA Buffer is empty." "0,1" newline bitfld.long 0x8 0. "SDRTX_EMPTY,This bit is set whenever Tx DATA Buffer is empty." "0,1" rgroup.long 0x60++0xB line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_CMD0_FIFO,Command Word 0 - commands are executed sequentially in order of arrival from the host." bitfld.long 0x0 31. "IS_DDR,IS_DDR - DDR command. Enables DDR mode of transfer. 0 - SDR mode 1 - DDR mode note that ENTHDR-DDR CCC should precede any commands with DDR mode enabled." "0: SDR mode 1,?" newline bitfld.long 0x0 30. "IS_CCC,IsCCC. Denotes whether it is a CCC or generic command. 0 - generic command 1 - CCC command" "0: generic command 1,?" newline bitfld.long 0x0 29. "BCH,BCH - Broadcast Header. Defines whether command will includes broadcast address header [0x7E] or not. Implicitly set for CCC commands. 0 - broadcast header disabled 1 - broadcast header enabled" "0: broadcast header disabled 1,?" newline bitfld.long 0x0 27.--28. "XMIT_MODE,Defines transfer modes for I3C SDR private read/write commands [not CCC] the following options are available: 00 - burst [byte-by-byte] transfer with static register sub-address. Send static sub-address followed by.." "0: burst [byte-by-byte] transfer with static..,1: single data byte transfers with auto incremented..,?,?" newline bitfld.long 0x0 26. "SBCA,SBCA - Sixteen Bits CSR Addressing. Defines the CSR addressing mode for I3C private commands only. 0 - normal CSR addressing mode [8-bit] - ADDR0_7 - ADDR0_0 1 - extended CSR addressing mode [16-bit] - ADDR0_7 -.." "0: normal CSR addressing mode [8-bit],?" newline bitfld.long 0x0 25. "RSBC,RSBC - Repeated Start Between Commands. When this bit is set then between commands he repeated start condition is issued instead stop condition. It is only applicable when there is more than one command is in the command queue and next command is.." "0,1" newline bitfld.long 0x0 24. "IS10B,Is10B - Normal/Extended Address. Defines the addressing mode applicable only for legacy I2C messaging. 0 - normal addressing mode [7-bit] - ID6-ID0 1 - extended addressing mode [10-bit] - ID10B2-ID10B0 and ID6-ID0" "0: normal addressing mode [7-bit],?" newline hexmask.long.word 0x0 12.--23. 1. "PL_LEN,PL_LEN - Payload Length defines number of bytes to be sent for particular CCC or generic R/Q command. Supports up to 4095 bytes." newline bitfld.long 0x0 8.--10. "DEV_ADDR_MSB,DEV_ADDR_MSB - legacy I2C Extended Address. The 3 MSB bits of legacy I2C 10-bit address. Applicable only if Is_10B is set for I2C legacy transfers." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 1.--7. 1. "DEV_ADDR,DEV_ADDR - Static/Dynamic slave Address. Correspond to a given slave Dynamic Address and Static Address. For CCC is applicable only when it is direct CCC command. For broadcast CCC this field is ignored." newline bitfld.long 0x0 0. "RNW,RnW - Read no Write. Defines the direction of transfer for broadcast CCC this field is ignored. 0 - Write Transfer 1 - Read Transfer" "0: Write Transfer 1,?" line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_CMD1_FIFO,Command Word 1 - commands are executed sequentially in order of arrival from host." hexmask.long.byte 0x4 24.--31. 1. "CMD_ID,CMD_ID - command identifier." newline hexmask.long.byte 0x4 8.--15. 1. "CSRADDR1,CSR ADDR1 - second byte of the CSR address in 16-bit addressing mode. Applicable only when 16-bit addressing mode is used and for private commands [non CCC commands]." newline hexmask.long.byte 0x4 0.--7. 1. "CCC_CSRADDR0,CCC/CSR ADDR0 - CCC or CSR Address. Meaning of this field depends on bit 30 [IsCCC] of Command Word0. - When is_ccc is set to '0' then this field holds address of slave CSR. When 16-bit addressing is used then it is the first.." line.long 0x8 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_TX_FIFO,Tx DATA Buffer that stores payload to be send with associated Tx command descriptor (from regular Command Queue)." hexmask.long 0x8 0.--31. 1. "DATA,Tx DATA payload." rgroup.long 0x70++0x7 line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_IMD_CMD0,Immediate Command Word 0 - High priority command register. If host submits immediate command when controller is during execution of regular command. the core will run regular command to completion and.." bitfld.long 0x0 12.--14. "PL_LEN,PL_LEN - Payload Length defines number of bytes to be send for particular CCC or generic R/W command. Supports up to 4 bytes." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 1.--7. 1. "DEV_ADDR,DEV_ADDR - Static/Dynamic slave Address. Correspond to a given slave Dynamic Address and Static Address. For CCC is applicable only when it is direct CCC command. For broadcast CCC this field is ignored." newline bitfld.long 0x0 0. "RNW,RnW - Read not Write. Defines the direction of transfer for broadcast CCC this field is ignored. 0 - Write Transfer 1 - Read Transfer" "0: Write Transfer 1,?" line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_IMD_CMD1,Immediate Command Word 1 - High priority command register. If host submits immediate command when controller is during execution of regular command. the core will run regular command to completion and.." hexmask.long.byte 0x4 24.--31. 1. "CMD_ID,CMD_ID - command identifier." newline hexmask.long.byte 0x4 0.--7. 1. "CCC,CCC Code - field holds code of CCC message." rgroup.long 0x78++0x3 line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_IMD_DATA,Tx DATA Register that stores payload to be send with associated command descriptor (from Immediate Command Register)." hexmask.long 0x0 0.--31. 1. "DATA,Tx DATA payload [it's not a FIFO supports up to 4 bytes only]." rgroup.long 0x80++0x7 line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_RX_FIFO,Rx DATA Buffer that stores payload received as a part of Rx command execution (from regular Command Queue)." hexmask.long 0x0 0.--31. 1. "DATA,Rx DATA payload." line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_IBI_DATA_FIFO,IBI Data Buffer that stores payload received as apart of IBI reuqest service." hexmask.long 0x4 0.--31. 1. "DATA,IBI DATA payload." rgroup.long 0x88++0x3 line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_SLV_DDR_TX_FIFO,Slave DDR Tx DATA Buffer that stores payload to be send upon reception of DDR read request from Current Master." hexmask.long.tbyte 0x0 0.--19. 1. "DDR_SLAVE_TX_DATA_FIFO,DDR Tx DATA payload [with meta-data e.g. preamble/parity]." rgroup.long 0x8C++0x3 line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_SLV_DDR_RX_FIFO,Slave DDR Rx DATA Buffer that stores payload received during reception of DDR write request from Current Master." hexmask.long.tbyte 0x0 0.--19. 1. "DDR_SLAVE_RX_DATA_FIFO,DDR Rx DATA payload [with meta-data e.g. preamble/parity]." rgroup.long 0x90++0xB line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_CMD_IBI_THR_CTRL,Control register for threshold generation - associated with Command and In-Band Interrupt memory blocks." hexmask.long.byte 0x0 24.--29. 1. "IBIR_THR,Threshold configuration value for IBI Response Queue." newline hexmask.long.byte 0x0 16.--20. 1. "CMDR_THR,Threshold configuration value for Command Response Queue." newline hexmask.long.byte 0x0 8.--13. 1. "IBID_THR,Threshold configuration value for IBI DATA Buffer." newline hexmask.long.byte 0x0 0.--4. 1. "CMDD_THR,Threshold configuration value for Command Queue." line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_TX_RX_THR_CTRL,Control register for threshold generation - associated with Tx and Rx DATA memory blocks." hexmask.long.word 0x4 16.--31. 1. "RX_THR,Threshold configuration value for Rx Data memory block" newline hexmask.long.word 0x4 0.--15. 1. "TX_THR,Threshold configuration value for Tx Data memory block" line.long 0x8 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_SLV_DDR_TX_RX_THR_CTRL,Control register for threshold generation - associated with Slave Mode DDR Tx and Rx DATA memory blocks." hexmask.long.word 0x8 16.--31. 1. "SLV_DDR_RX_THR,Threshold configuration value for Slave DDR Rx DATA buffer." newline hexmask.long.word 0x8 0.--15. 1. "SLV_DDR_TX_THR,Threshold configuration value for Slave DDR Tx DATA buffer." rgroup.long 0x9C++0x3 line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_FLUSH_CTRL,Soft flush control for memory blocks." bitfld.long 0x0 24. "IBI_RESP_FLUSH,When asserted while controller is disabled the IBI Response Queue read/write pointers will be set to 0 effectively makes the buffer empty. Self-cleared control bit." "0,1" newline bitfld.long 0x0 23. "CMD_RESP_FLUSH,When asserted while controller is disabled the Command Response Queue read/write pointers will be set to 0 effectively makes the buffer empty. Self-cleared control bit." "0,1" newline bitfld.long 0x0 22. "SLV_DDR_RX_FLUSH,When asserted while controller is disabled the Slave DDR Rx DATA Buffer read/write pointers will be set to 0 effectively makes the buffer empty. Self-cleared control bit." "0,1" newline bitfld.long 0x0 21. "SLV_DDR_TX_FLUSH,When asserted while controller is disabled the Slave DDR Tx DATA Buffer read/write pointers will be set to 0 effectively makes the buffer empty. Self-cleared control bit." "0,1" newline bitfld.long 0x0 20. "IMM_CMD_FLUSH,When asserted while controller is disabled the Immediate Commadn/DATA registers will be cleared and their empty flag will be asserted. Self-cleared control bit." "0,1" newline bitfld.long 0x0 19. "IBI_FLUSH,When asserted while controller is disabled the IBI DATA Buffer read/write pointers will be set to 0 effectively makes the buffer empty. Self-cleared control bit." "0,1" newline bitfld.long 0x0 18. "RX_FLUSH,When asserted while controller is disabled the Rx DATA Buffer read/write pointers will be set to 0 effectively makes the buffer empty. Self-cleared control bit.. Self-cleared control bit." "0,1" newline bitfld.long 0x0 17. "TX_FLUSH,When asserted while controller is disabled the Tx DATA Buffer read/write pointers will be set to 0 effectively makes the buffer empty. Self-cleared control bit." "0,1" newline bitfld.long 0x0 16. "CMD_FLUSH,When asserted while controller is disabled the Command Buffer read/write pointers will be set to 0 effectively makes the buffer empty. Self-cleared control bit." "0,1" rgroup.long 0xB0++0xB line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_TTO_PRESCL_CTRL0,Prescale settings for First SCL high timeout detection." hexmask.long.word 0x0 16.--25. 1. "DIV_B,Divider B" newline hexmask.long.word 0x0 0.--10. 1. "DIV_A,Divider A" line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_TTO_PRESCL_CTRL1,Prescale settings for SCL high and low timeout detection." hexmask.long.word 0x4 16.--25. 1. "DIV_B,Divider B" newline hexmask.long.byte 0x4 0.--7. 1. "DIV_A,Divider A" line.long 0x8 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEVS_CTRL,Device control register." hexmask.long.byte 0x8 28.--31. 1. "RSVD1,Reserved." newline bitfld.long 0x8 27. "DEV11_CLR,Clear contents of DevID11 retaining registers. Self-cleared bit." "0,1" newline bitfld.long 0x8 26. "DEV10_CLR,Clear contents of DevID10 retaining registers. Self-cleared bit." "0,1" newline bitfld.long 0x8 25. "DEV9_CLR,Clear contents of DevID9 retaining registers. Self-cleared bit." "0,1" newline bitfld.long 0x8 24. "DEV8_CLR,Clear contents of DevID8 retaining registers. Self-cleared bit." "0,1" newline bitfld.long 0x8 23. "DEV7_CLR,Clear contents of DevID7 retaining registers. Self-cleared bit." "0,1" newline bitfld.long 0x8 22. "DEV6_CLR,Clear contents of DevID6 retaining registers. Self-cleared bit." "0,1" newline bitfld.long 0x8 21. "DEV5_CLR,Clear contents of DevID5 retaining registers. Self-cleared bit." "0,1" newline bitfld.long 0x8 20. "DEV4_CLR,Clear contents of DevID4 retaining registers. Self-cleared bit." "0,1" newline bitfld.long 0x8 19. "DEV3_CLR,Clear contents of DevID3 retaining registers. Self-cleared bit." "0,1" newline bitfld.long 0x8 18. "DEV2_CLR,Clear contents of DevID2 retaining registers. Self-cleared bit." "0,1" newline bitfld.long 0x8 17. "DEV1_CLR,Clear contents of DevID1 retaining registers. Self-cleared bit." "0,1" newline hexmask.long.byte 0x8 12.--16. 1. "RSVD0,Reserved." newline bitfld.long 0x8 11. "DEV11_ACTIVE,DevID11 is active - has either valid DA or SA." "0,1" newline bitfld.long 0x8 10. "DEV10_ACTIVE,DevID10 is active - has either valid DA or SA." "0,1" newline bitfld.long 0x8 9. "DEV9_ACTIVE,DevID9 is active - has either valid DA or SA." "0,1" newline bitfld.long 0x8 8. "DEV8_ACTIVE,DevID8 is active - has either valid DA or SA." "0,1" newline bitfld.long 0x8 7. "DEV7_ACTIVE,DevID7 is active - has either valid DA or SA." "0,1" newline bitfld.long 0x8 6. "DEV6_ACTIVE,DevID6 is active - has either valid DA or SA." "0,1" newline bitfld.long 0x8 5. "DEV5_ACTIVE,DevID5 is active - has either valid DA or SA." "0,1" newline bitfld.long 0x8 4. "DEV4_ACTIVE,DevID4 is active - has either valid DA or SA." "0,1" newline bitfld.long 0x8 3. "DEV3_ACTIVE,DevID3 is active - has either valid DA or SA." "0,1" newline bitfld.long 0x8 2. "DEV2_ACTIVE,DevID2 is active - has either valid DA or SA." "0,1" newline bitfld.long 0x8 1. "DEV1_ACTIVE,DevID1 is active - has either valid DA or SA." "0,1" newline rbitfld.long 0x8 0. "DEV0_ACTIVE,DevID0 is active - has either valid DA or SA." "0,1" rgroup.long 0xC0++0xB line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID0_RR0,Device ID 0 Retaining Register 0 : Configuration Register" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with 10-bit addressing." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 0 Address mode used: 0 - 7-bit addressing - applicable for I3C and I2C devices. 1 - 10-bit addressing - applicable only for I2C devices with 10-bit extended address. NOTE: Invalid setting when.." "0,1" newline rbitfld.long 0x0 9. "IS_I3C,Device 0 I3C mode Operation 1 Yes 0 No" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 0 Slave Dynamic [Static/Legacy] Address bits 7:1 bit 0 - parity XOR check -> ~XOR[dev_addr[7:1]]." line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID0_RR1,Device ID 0 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 0 48 to 16 Dev ID bits" line.long 0x8 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID0_RR2,Device ID 0 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 0 15 to 0 Dev ID bits" newline hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 0 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 0 DCR [if I3C device] or LVR [if I2C device] register Decoding if used as DCR: Bits[7:0]: 255 available codes for describing the type of sensor or Device; Decoding if used as LVR:.." rgroup.long 0xD0++0xB line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID1_RR0,Device ID 1 Retaining Register 0 : Configuration Register" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with 10-bit addressing." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 1 Address mode used: 0 - 7-bit addressing - applicable for I3C and I2C devices. 1 - 10-bit addressing - applicable only for I2C devices with 10-bit extended address. NOTE: Invalid setting when.." "0,1" newline bitfld.long 0x0 9. "IS_I3C,Device 1 I3C mode Operation 1 Yes 0 No" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 1 Slave Dynamic [Static/Legacy] Address bits 7:1 bit 0 - parity XOR check -> ~XOR[dev_addr[7:1]]." line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID1_RR1,Device ID 1 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 1 48 to 16 Dev ID bits" line.long 0x8 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID1_RR2,Device ID 1 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 1 15 to 0 Dev ID bits" newline hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 1 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 1 DCR [if I3C device] or LVR [if I2C device] register Decoding if used as DCR: Bits[7:0]: 255 available codes for describing the type of sensor or Device; Decoding if used as LVR:.." rgroup.long 0xE0++0xB line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID2_RR0,Device ID 2 Retaining Register 0 : Configuration Register" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with 10-bit addressing." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 2 Address mode used: 0 - 7-bit addressing - applicable for I3C and I2C devices. 1 - 10-bit addressing - applicable only for I2C devices with 10-bit extended address. NOTE: Invalid setting when.." "0,1" newline bitfld.long 0x0 9. "IS_I3C,Device 2 I3C mode Operation 1 Yes 0 No" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 2 Slave Dynamic [Static/Legacy] Address bits 7:1 bit 0 - parity XOR check -> ~XOR[dev_addr[7:1]]." line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID2_RR1,Device ID 2 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 2 48 to 16 Dev ID bits" line.long 0x8 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID2_RR2,Device ID 2 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 2 15 to 0 Dev ID bits" newline hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 2 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 2 DCR [if I3C device] or LVR [if I2C device] register Decoding if used as DCR: Bits[7:0]: 255 available codes for describing the type of sensor or Device; Decoding if used as LVR:.." rgroup.long 0xF0++0xB line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID3_RR0,Device ID 3 Retaining Register 0 : Configuration Register" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with 10-bit addressing." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 3 Address mode used: 0 - 7-bit addressing - applicable for I3C and I2C devices. 1 - 10-bit addressing - applicable only for I2C devices with 10-bit extended address. NOTE: Invalid setting when.." "0,1" newline bitfld.long 0x0 9. "IS_I3C,Device 3 I3C mode Operation 1 Yes 0 No" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 3 Slave Dynamic [Static/Legacy] Address bits 7:1 bit 0 - parity XOR check -> ~XOR[dev_addr[7:1]]." line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID3_RR1,Device ID 3 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 3 48 to 16 Dev ID bits" line.long 0x8 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID3_RR2,Device ID 3 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 3 15 to 0 Dev ID bits" newline hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 3 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 3 DCR [if I3C device] or LVR [if I2C device] register Decoding if used as DCR: Bits[7:0]: 255 available codes for describing the type of sensor or Device; Decoding if used as LVR:.." rgroup.long 0x100++0xB line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID4_RR0,Device ID 4 Retaining Register 0 : Configuration Register" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with 10-bit addressing." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 4 Address mode used: 0 - 7-bit addressing - applicable for I3C and I2C devices. 1 - 10-bit addressing - applicable only for I2C devices with 10-bit extended address. NOTE: Invalid setting when.." "0,1" newline bitfld.long 0x0 9. "IS_I3C,Device 4 I3C mode Operation 1 Yes 0 No" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 4 Slave Dynamic [Static/Legacy] Address bits 7:1 bit 0 - parity XOR check -> ~XOR[dev_addr[7:1]]." line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID4_RR1,Device ID 4 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 4 48 to 16 Dev ID bits" line.long 0x8 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID4_RR2,Device ID 4 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 4 15 to 0 Dev ID bits" newline hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 4 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 4 DCR [if I3C device] or LVR [if I2C device] register Decoding if used as DCR: Bits[7:0]: 255 available codes for describing the type of sensor or Device; Decoding if used as LVR:.." rgroup.long 0x110++0xB line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID5_RR0,Device ID 5 Retaining Register 0 : Configuration Register" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with 10-bit addressing." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 5 Address mode used: 0 - 7-bit addressing - applicable for I3C and I2C devices. 1 - 10-bit addressing - applicable only for I2C devices with 10-bit extended address. NOTE: Invalid setting when.." "0,1" newline bitfld.long 0x0 9. "IS_I3C,Device 5 I3C mode Operation 1 Yes 0 No" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 5 Slave Dynamic [Static/Legacy] Address bits 7:1 bit 0 - parity XOR check -> ~XOR[dev_addr[7:1]]." line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID5_RR1,Device ID 5 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 5 48 to 16 Dev ID bits" line.long 0x8 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID5_RR2,Device ID 5 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 5 15 to 0 Dev ID bits" newline hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 5 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 5 DCR [if I3C device] or LVR [if I2C device] register Decoding if used as DCR: Bits[7:0]: 255 available codes for describing the type of sensor or Device; Decoding if used as LVR:.." rgroup.long 0x120++0xB line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID6_RR0,Device ID 6 Retaining Register 0 : Configuration Register" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with 10-bit addressing." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 6 Address mode used: 0 - 7-bit addressing - applicable for I3C and I2C devices. 1 - 10-bit addressing - applicable only for I2C devices with 10-bit extended address. NOTE: Invalid setting when.." "0,1" newline bitfld.long 0x0 9. "IS_I3C,Device 6 I3C mode Operation 1 Yes 0 No" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 6 Slave Dynamic [Static/Legacy] Address bits 7:1 bit 0 - parity XOR check -> ~XOR[dev_addr[7:1]]." line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID6_RR1,Device ID 6 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 6 48 to 16 Dev ID bits" line.long 0x8 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID6_RR2,Device ID 6 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 6 15 to 0 Dev ID bits" newline hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 6 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 6 DCR [if I3C device] or LVR [if I2C device] register Decoding if used as DCR: Bits[7:0]: 255 available codes for describing the type of sensor or Device; Decoding if used as LVR:.." rgroup.long 0x130++0xB line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID7_RR0,Device ID 7 Retaining Register 0 : Configuration Register" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with 10-bit addressing." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 7 Address mode used: 0 - 7-bit addressing - applicable for I3C and I2C devices. 1 - 10-bit addressing - applicable only for I2C devices with 10-bit extended address. NOTE: Invalid setting when.." "0,1" newline bitfld.long 0x0 9. "IS_I3C,Device 7 I3C mode Operation 1 Yes 0 No" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 7 Slave Dynamic [Static/Legacy] Address bits 7:1 bit 0 - parity XOR check -> ~XOR[dev_addr[7:1]]." line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID7_RR1,Device ID 7 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 7 48 to 16 Dev ID bits" line.long 0x8 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID7_RR2,Device ID 7 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 7 15 to 0 Dev ID bits" newline hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 7 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 7 DCR [if I3C device] or LVR [if I2C device] register Decoding if used as DCR: Bits[7:0]: 255 available codes for describing the type of sensor or Device; Decoding if used as LVR:.." rgroup.long 0x140++0xB line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID8_RR0,Device ID 8 Retaining Register 0 : Configuration Register" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with 10-bit addressing." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 8 Address mode used: 0 - 7-bit addressing - applicable for I3C and I2C devices. 1 - 10-bit addressing - applicable only for I2C devices with 10-bit extended address. NOTE: Invalid setting when.." "0,1" newline bitfld.long 0x0 9. "IS_I3C,Device 8 I3C mode Operation 1 Yes 0 No" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 8 Slave Dynamic [Static/Legacy] Address bits 7:1 bit 0 - parity XOR check -> ~XOR[dev_addr[7:1]]." line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID8_RR1,Device ID 8 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 8 48 to 16 Dev ID bits" line.long 0x8 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID8_RR2,Device ID 8 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 8 15 to 0 Dev ID bits" newline hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 8 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 8 DCR [if I3C device] or LVR [if I2C device] register Decoding if used as DCR: Bits[7:0]: 255 available codes for describing the type of sensor or Device; Decoding if used as LVR:.." rgroup.long 0x150++0xB line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID9_RR0,Device ID 9 Retaining Register 0 : Configuration Register" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with 10-bit addressing." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 9 Address mode used: 0 - 7-bit addressing - applicable for I3C and I2C devices. 1 - 10-bit addressing - applicable only for I2C devices with 10-bit extended address. NOTE: Invalid setting when.." "0,1" newline bitfld.long 0x0 9. "IS_I3C,Device 9 I3C mode Operation 1 Yes 0 No" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 9 Slave Dynamic [Static/Legacy] Address bits 7:1 bit 0 - parity XOR check -> ~XOR[dev_addr[7:1]]." line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID9_RR1,Device ID 9 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 9 48 to 16 Dev ID bits" line.long 0x8 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID9_RR2,Device ID 9 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 9 15 to 0 Dev ID bits" newline hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 9 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 9 DCR [if I3C device] or LVR [if I2C device] register Decoding if used as DCR: Bits[7:0]: 255 available codes for describing the type of sensor or Device; Decoding if used as LVR:.." rgroup.long 0x160++0xB line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID10_RR0,Device ID 10 Retaining Register 0 : Configuration Register" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with 10-bit addressing." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 10 Address mode used: 0 - 7-bit addressing - applicable for I3C and I2C devices. 1 - 10-bit addressing - applicable only for I2C devices with 10-bit extended address. NOTE: Invalid setting when.." "0,1" newline bitfld.long 0x0 9. "IS_I3C,Device 10 I3C mode Operation 1 Yes 0 No" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 10 Slave Dynamic [Static/Legacy] Address bits 7:1 bit 0 - parity XOR check -> ~XOR[dev_addr[7:1]]." line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID10_RR1,Device ID 10 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 10 48 to 16 Dev ID bits" line.long 0x8 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID10_RR2,Device ID 10 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 10 15 to 0 Dev ID bits" newline hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 10 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 10 DCR [if I3C device] or LVR [if I2C device] register Decoding if used as DCR: Bits[7:0]: 255 available codes for describing the type of sensor or Device; Decoding if used as LVR:.." rgroup.long 0x170++0xB line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID11_RR0,Device ID 11 Retaining Register 0 : Configuration Register" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with 10-bit addressing." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 11 Address mode used: 0 - 7-bit addressing - applicable for I3C and I2C devices. 1 - 10-bit addressing - applicable only for I2C devices with 10-bit extended address. NOTE: Invalid setting when.." "0,1" newline bitfld.long 0x0 9. "IS_I3C,Device 11 I3C mode Operation 1 Yes 0 No" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 11 Slave Dynamic [Static/Legacy] Address bits 7:1 bit 0 - parity XOR check -> ~XOR[dev_addr[7:1]]." line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID11_RR1,Device ID 11 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 11 48 to 16 Dev ID bits" line.long 0x8 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_DEV_ID11_RR2,Device ID 11 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 11 15 to 0 Dev ID bits" newline hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 11 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 11 DCR [if I3C device] or LVR [if I2C device] register Decoding if used as DCR: Bits[7:0]: 255 available codes for describing the type of sensor or Device; Decoding if used as LVR:.." rgroup.long 0x180++0x17 line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_SIR_MAP0,Slave-initiated request Device ID Detection register0" bitfld.long 0x0 30.--31. "DEVID1_ROLE,Slave-initiated request Device ID0 BCR role 2'b00 - Slave 2'b01 - Master/Secondary Master 2'b10 - Reserved 2'b11 - Reserved" "0: Slave 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 29. "DEVID1_SLOW,Slave-initiated request Device ID0 Max Data Speed Limitation 0 - No limitation 1 - Limitation" "0: No limitation 1,?" newline hexmask.long.byte 0x0 24.--28. 1. "DEVID1_PL,Slave-initiated request Device ID0 payload length" newline hexmask.long.byte 0x0 17.--23. 1. "DEVID1_DA,Slave-initiated request Device ID0 DA" newline bitfld.long 0x0 16. "DEVID1_RESP,Slave-initiated request Device ID0 Ack/Nack response 0 - NACK each request from this device. 1 - ACK each request from this device." "0: NACK each request from this device,1: ACK each request from this device" newline bitfld.long 0x0 14.--15. "DEVID0_ROLE,Slave-initiated request Device ID0 BCR role 2'b00 - Slave 2'b01 - Master/Secondary Master 2'b10 - Reserved 2'b11 - Reserved" "0: Slave 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 13. "DEVID0_SLOW,Slave-initiated request Device ID0 Max Data Speed Limitation 0 - No limitation 1 - Limitation" "0: No limitation 1,?" newline hexmask.long.byte 0x0 8.--12. 1. "DEVID0_PL,Slave-initiated request Device ID0 payload length" newline hexmask.long.byte 0x0 1.--7. 1. "DEVID0_DA,Slave-initiated request Device ID0 DA" newline bitfld.long 0x0 0. "DEVID0_RESP,Slave-initiated request Device ID0 Ack/Nack response 0 - NACK each request from this device. 1 - ACK each request from this device." "0: NACK each request from this device,1: ACK each request from this device" line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_SIR_MAP1,Slave-initiated request Device ID Detection register1" bitfld.long 0x4 30.--31. "DEVID3_ROLE,Slave-initiated request Device ID2 BCR role 2'b00 - Slave 2'b01 - Master/Secondary Master 2'b10 - Reserved 2'b11 - Reserved" "0: Slave 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x4 29. "DEVID3_SLOW,Slave-initiated request Device ID2 Max Data Speed Limitation 0 - No limitation 1 - Limitation" "0: No limitation 1,?" newline hexmask.long.byte 0x4 24.--28. 1. "DEVID3_PL,Slave-initiated request Device ID2 payload length" newline hexmask.long.byte 0x4 17.--23. 1. "DEVID3_DA,Slave-initiated request Device ID2 DA" newline bitfld.long 0x4 16. "DEVID3_RESP,Slave-initiated request Device ID2 Ack/Nack response 0 - NACK each request from this device. 1 - ACK each request from this device." "0: NACK each request from this device,1: ACK each request from this device" newline bitfld.long 0x4 14.--15. "DEVID2_ROLE,Slave-initiated request Device ID2 BCR role 2'b00 - Slave 2'b01 - Master/Secondary Master 2'b10 - Reserved 2'b11 - Reserved" "0: Slave 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x4 13. "DEVID2_SLOW,Slave-initiated request Device ID2 Max Data Speed Limitation 0 - No limitation 1 - Limitation" "0: No limitation 1,?" newline hexmask.long.byte 0x4 8.--12. 1. "DEVID2_PL,Slave-initiated request Device ID2 payload length" newline hexmask.long.byte 0x4 1.--7. 1. "DEVID2_DA,Slave-initiated request Device ID2 DA" newline bitfld.long 0x4 0. "DEVID2_RESP,Slave-initiated request Device ID2 Ack/Nack response 0 - NACK each request from this device. 1 - ACK each request from this device." "0: NACK each request from this device,1: ACK each request from this device" line.long 0x8 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_SIR_MAP2,Slave-initiated request Device ID Detection register2" bitfld.long 0x8 30.--31. "DEVID5_ROLE,Slave-initiated request Device ID4 BCR role 2'b00 - Slave 2'b01 - Master/Secondary Master 2'b10 - Reserved 2'b11 - Reserved" "0: Slave 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x8 29. "DEVID5_SLOW,Slave-initiated request Device ID4 Max Data Speed Limitation 0 - No limitation 1 - Limitation" "0: No limitation 1,?" newline hexmask.long.byte 0x8 24.--28. 1. "DEVID5_PL,Slave-initiated request Device ID4 payload length" newline hexmask.long.byte 0x8 17.--23. 1. "DEVID5_DA,Slave-initiated request Device ID4 DA" newline bitfld.long 0x8 16. "DEVID5_RESP,Slave-initiated request Device ID4 Ack/Nack response 0 - NACK each request from this device. 1 - ACK each request from this device." "0: NACK each request from this device,1: ACK each request from this device" newline bitfld.long 0x8 14.--15. "DEVID4_ROLE,Slave-initiated request Device ID4 BCR role 2'b00 - Slave 2'b01 - Master/Secondary Master 2'b10 - Reserved 2'b11 - Reserved" "0: Slave 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x8 13. "DEVID4_SLOW,Slave-initiated request Device ID4 Max Data Speed Limitation 0 - No limitation 1 - Limitation" "0: No limitation 1,?" newline hexmask.long.byte 0x8 8.--12. 1. "DEVID4_PL,Slave-initiated request Device ID4 payload length" newline hexmask.long.byte 0x8 1.--7. 1. "DEVID4_DA,Slave-initiated request Device ID4 DA" newline bitfld.long 0x8 0. "DEVID4_RESP,Slave-initiated request Device ID4 Ack/Nack response 0 - NACK each request from this device. 1 - ACK each request from this device." "0: NACK each request from this device,1: ACK each request from this device" line.long 0xC "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_SIR_MAP3,Slave-initiated request Device ID Detection register3" bitfld.long 0xC 30.--31. "DEVID7_ROLE,Slave-initiated request Device ID6 BCR role 2'b00 - Slave 2'b01 - Master/Secondary Master 2'b10 - Reserved 2'b11 - Reserved" "0: Slave 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0xC 29. "DEVID7_SLOW,Slave-initiated request Device ID6 Max Data Speed Limitation 0 - No limitation 1 - Limitation" "0: No limitation 1,?" newline hexmask.long.byte 0xC 24.--28. 1. "DEVID7_PL,Slave-initiated request Device ID6 payload length" newline hexmask.long.byte 0xC 17.--23. 1. "DEVID7_DA,Slave-initiated request Device ID6 DA" newline bitfld.long 0xC 16. "DEVID7_RESP,Slave-initiated request Device ID6 Ack/Nack response 0 - NACK each request from this device. 1 - ACK each request from this device." "0: NACK each request from this device,1: ACK each request from this device" newline bitfld.long 0xC 14.--15. "DEVID6_ROLE,Slave-initiated request Device ID6 BCR role 2'b00 - Slave 2'b01 - Master/Secondary Master 2'b10 - Reserved 2'b11 - Reserved" "0: Slave 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0xC 13. "DEVID6_SLOW,Slave-initiated request Device ID6 Max Data Speed Limitation 0 - No limitation 1 - Limitation" "0: No limitation 1,?" newline hexmask.long.byte 0xC 8.--12. 1. "DEVID6_PL,Slave-initiated request Device ID6 payload length" newline hexmask.long.byte 0xC 1.--7. 1. "DEVID6_DA,Slave-initiated request Device ID6 DA" newline bitfld.long 0xC 0. "DEVID6_RESP,Slave-initiated request Device ID6 Ack/Nack response 0 - NACK each request from this device. 1 - ACK each request from this device." "0: NACK each request from this device,1: ACK each request from this device" line.long 0x10 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_SIR_MAP4,Slave-initiated request Device ID Detection register4" bitfld.long 0x10 30.--31. "DEVID9_ROLE,Slave-initiated request Device ID8 BCR role 2'b00 - Slave 2'b01 - Master/Secondary Master 2'b10 - Reserved 2'b11 - Reserved" "0: Slave 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x10 29. "DEVID9_SLOW,Slave-initiated request Device ID8 Max Data Speed Limitation 0 - No limitation 1 - Limitation" "0: No limitation 1,?" newline hexmask.long.byte 0x10 24.--28. 1. "DEVID9_PL,Slave-initiated request Device ID8 payload length" newline hexmask.long.byte 0x10 17.--23. 1. "DEVID9_DA,Slave-initiated request Device ID8 DA" newline bitfld.long 0x10 16. "DEVID9_RESP,Slave-initiated request Device ID8 Ack/Nack response 0 - NACK each request from this device. 1 - ACK each request from this device." "0: NACK each request from this device,1: ACK each request from this device" newline bitfld.long 0x10 14.--15. "DEVID8_ROLE,Slave-initiated request Device ID8 BCR role 2'b00 - Slave 2'b01 - Master/Secondary Master 2'b10 - Reserved 2'b11 - Reserved" "0: Slave 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x10 13. "DEVID8_SLOW,Slave-initiated request Device ID8 Max Data Speed Limitation 0 - No limitation 1 - Limitation" "0: No limitation 1,?" newline hexmask.long.byte 0x10 8.--12. 1. "DEVID8_PL,Slave-initiated request Device ID8 payload length" newline hexmask.long.byte 0x10 1.--7. 1. "DEVID8_DA,Slave-initiated request Device ID8 DA" newline bitfld.long 0x10 0. "DEVID8_RESP,Slave-initiated request Device ID8 Ack/Nack response 0 - NACK each request from this device. 1 - ACK each request from this device." "0: NACK each request from this device,1: ACK each request from this device" line.long 0x14 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_SIR_MAP5,Slave-initiated request Device ID Detection register5" bitfld.long 0x14 14.--15. "DEVID10_ROLE,Slave-initiated request Device ID10 BCR role 2'b00 - Slave 2'b01 - Master/Secondary Master 2'b10 - Reserved 2'b11 - Reserved" "0: Slave 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x14 13. "DEVID10_SLOW,Slave-initiated request Device ID10 Max Data Speed Limitation 0 - No limitation 1 - Limitation" "0: No limitation 1,?" newline hexmask.long.byte 0x14 8.--12. 1. "DEVID10_PL,Slave-initiated request Device ID10 payload length" newline hexmask.long.byte 0x14 1.--7. 1. "DEVID10_DA,Slave-initiated request Device ID10 DA" newline bitfld.long 0x14 0. "DEVID10_RESP,Slave-initiated request Device ID10 Ack/Nack response 0 - NACK each request from this device. 1 - ACK each request from this device." "0: NACK each request from this device,1: ACK each request from this device" rgroup.long 0x1A0++0x3 line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_GPIR_WORD0,User Defined GPI Word 0: four 8-bits GPI Registers" hexmask.long.byte 0x0 0.--7. 1. "GPI0,User Defined GPI Register 0" rgroup.long 0x220++0x3 line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_GPOR_WORD0,User Defined GPO Word 0: four 8-bits GPO Registers" hexmask.long.byte 0x0 0.--7. 1. "GPO0,User Defined GPO Register 0" rgroup.long 0x300++0x13 line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_asf_int_status,ASF Interrupt Status Register. This register indicates the source of ASF interrupts. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register.." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x0 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1" newline bitfld.long 0x0 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1" newline bitfld.long 0x0 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1" newline bitfld.long 0x0 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x0 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1" newline bitfld.long 0x0 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x0 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1" line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_asf_int_raw_status,ASF Interrupt Raw Status Register. A bit set in this raw register indicates a source of ASF fault in the corresponding feature. Writing to either raw or masked status registers. clear both.." hexmask.long 0x4 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x4 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1" newline bitfld.long 0x4 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1" newline bitfld.long 0x4 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1" newline bitfld.long 0x4 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x4 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1" newline bitfld.long 0x4 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x4 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1" line.long 0x8 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_asf_int_mask,The ASF interrupt mask register indicating which interrupt bits in the ASF interrupt status register are masked. All bits are set at reset. Clear the individual bit to enable the corresponding.." hexmask.long 0x8 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x8 6. "ASF_INTEGRITY_ERR_MASK,Mask bit for integrity error interrupt" "0,1" newline bitfld.long 0x8 5. "ASF_PROTOCOL_ERR_MASK,Mask bit for protocol error interrupt." "0,1" newline bitfld.long 0x8 4. "ASF_TRANS_TO_ERR_MASK,Mask bit for transaction timeouts error interrupt." "0,1" newline bitfld.long 0x8 3. "ASF_CSR_ERR_MASK,Mask bit for configuration and status registers error interrupt." "0,1" newline bitfld.long 0x8 2. "ASF_DAP_ERR_MASK,Mask bit for data and address paths parity error interrupt." "0,1" newline bitfld.long 0x8 1. "ASF_SRAM_UNCORR_ERR_MASK,Mask bit for SRAM uncorrectable error interrupt." "0,1" newline bitfld.long 0x8 0. "ASF_SRAM_CORR_ERR_MASK,Mask bit for SRAM correctable error interrupt." "0,1" line.long 0xC "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_asf_int_test,The ASF interrupt test register emulate hardware even. Write one to individual bit to trigger single event in (masked and raw) status registers according to mask and will generate interrupt.." hexmask.long 0xC 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0xC 6. "ASF_INTEGRITY_ERR_TEST,Test bit for integrity error interrupt" "0,1" newline bitfld.long 0xC 5. "ASF_PROTOCOL_ERR_TEST,Test bit for protocol error interrupt." "0,1" newline bitfld.long 0xC 4. "ASF_TRANS_TO_ERR_TEST,Test bit for transaction timeouts error interrupt." "0,1" newline bitfld.long 0xC 3. "ASF_CSR_ERR_TEST,Test bit for configuration and status registers error interrupt." "0,1" newline bitfld.long 0xC 2. "ASF_DAP_ERR_TEST,Test bit for data and address paths parity error interrupt." "0,1" newline bitfld.long 0xC 1. "ASF_SRAM_UNCORR_ERR_TEST,Test bit for SRAM uncorrectable error interrupt." "0,1" newline bitfld.long 0xC 0. "ASF_SRAM_CORR_ERR_TEST,Test bit for SRAM correctable error interrupt." "0,1" line.long 0x10 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_asf_fatal_nonfatal_select,The fatal or non-fatal interrupt register selects whether a fatal (asf_int_fatal) or non-fatal (asf_int_nonfatal) interrupt is triggered. If the bit of the event will be set to one then.." hexmask.long 0x10 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x10 6. "ASF_INTEGRITY_ERR,Enable integrity error interrupt as fatal" "0,1" newline bitfld.long 0x10 5. "ASF_PROTOCOL_ERR,Enable protocol error interrupt as fatal." "0,1" newline bitfld.long 0x10 4. "ASF_TRANS_TO_ERR,Enable transaction timeouts error interrupt as fatal." "0,1" newline bitfld.long 0x10 3. "ASF_CSR_ERR,Enable configuration and status registers error interrupt as fatal." "0,1" newline bitfld.long 0x10 2. "ASF_DAP_ERR,Enable data and address paths parity error interrupt as fatal." "0,1" newline bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR,Enable SRAM uncorrectable error interrupt as fatal." "0,1" newline bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR,Enable SRAM correctable error interrupt as fatal." "0,1" rgroup.long 0x320++0x7 line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_asf_sram_corr_fault_status,Status register for SRAM correctable fault. These fields are updated whenever asf_sram_corr_fault input is active." hexmask.long.byte 0x0 24.--31. 1. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault." newline hexmask.long.tbyte 0x0 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault." line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_asf_sram_uncorr_fault_status,Status register for SRAM uncorrectable fault. These fields are updated whenever asf_sram_uncorr_fault input is active." hexmask.long.byte 0x4 24.--31. 1. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault." newline hexmask.long.tbyte 0x4 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault." rgroup.long 0x328++0x3 line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_asf_sram_fault_stats,Statistics register for SRAM faults. Note that this register clears when software writes to any field." hexmask.long.word 0x0 16.--31. 1. "ASF_SRAM_FAULT_UNCORR_STATS,Count of number of uncorrectable errors if implemented. Count value will saturate at 0xffff." newline hexmask.long.word 0x0 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS,Count of number of correctable errors if implemented. Count value will saturate at 0xffff." rgroup.long 0x330++0xB line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_asf_trans_to_ctrl,Control register to configure the ASF transaction timeout monitors." bitfld.long 0x0 31. "ASF_TRANS_TO_EN,Enable transaction timeout monitoring." "0,1" newline hexmask.long.word 0x0 16.--30. 1. "RESERVED,Reserved read as 0 ignored on write." newline hexmask.long.word 0x0 0.--15. 1. "ASF_TRANS_TO_CTRL,Timer value to use for transaction timeout monitor." line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_asf_trans_to_fault_mask,Control register to mask out ASF transaction timeout faults from triggering interrupts. On reset. all bits are set to mask out all sources. Clear the corresponding bit to enable the.." hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x4 3. "ASF_TRANS_TO_FAULT_3_MASK,Mask bit for apb transaction timeout fault." "0,1" newline bitfld.long 0x4 2. "ASF_TRANS_TO_FAULT_2_MASK,Mask bit for I3C transaction SCL low timeout fault." "0,1" newline bitfld.long 0x4 1. "ASF_TRANS_TO_FAULT_1_MASK,Mask bit for I3C transaction SCL high timeout fault." "0,1" newline bitfld.long 0x4 0. "ASF_TRANS_TO_FAULT_0_MASK,Mask bit for I3C transaction first SCL high timeout fault." "0,1" line.long 0x8 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_asf_trans_to_fault_status,Status register for transaction timeouts fault. If a fault occurs the relevant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit." hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x8 3. "ASF_TRANS_TO_FAULT_3_STATUS,Status bits for apb transaction timeout fault." "0,1" newline bitfld.long 0x8 2. "ASF_TRANS_TO_FAULT_2_STATUS,Status bits for I3C transaction SCL low timeout fault." "0,1" newline bitfld.long 0x8 1. "ASF_TRANS_TO_FAULT_1_STATUS,Status bits for I3C transaction SCL high timeout fault." "0,1" newline bitfld.long 0x8 0. "ASF_TRANS_TO_FAULT_0_STATUS,Status bits for I3C transaction first SCL high timeout fault." "0,1" rgroup.long 0x340++0x7 line.long 0x0 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_asf_protocol_fault_mask,Control register to mask out ASF Protocol faults from triggering interrupts. On reset. all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt source." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x0 12. "ASF_PROTOCOL_FAULT_SLV_SDR_RD_ABORT_MASK,Mask bit for slv_sdr_rd_abort protocol fault source." "0,1" newline bitfld.long 0x0 11. "ASF_PROTOCOL_FAULT_SLV_DDR_FAIL_MASK,Mask bit for slv_ddr_fail protocol fault source." "0,1" newline bitfld.long 0x0 10. "ASF_PROTOCOL_FAULT_S5_MASK,Mask bit for s5 protocol fault source." "0,1" newline bitfld.long 0x0 9. "ASF_PROTOCOL_FAULT_S4_MASK,Mask bit for s4 protocol fault source." "0,1" newline bitfld.long 0x0 8. "ASF_PROTOCOL_FAULT_S3_MASK,Mask bit for s3 protocol fault source." "0,1" newline bitfld.long 0x0 7. "ASF_PROTOCOL_FAULT_S2_MASK,Mask bit for s2 protocol fault source." "0,1" newline bitfld.long 0x0 6. "ASF_PROTOCOL_FAULT_S1_MASK,Mask bit for s1 protocol fault source." "0,1" newline bitfld.long 0x0 5. "ASF_PROTOCOL_FAULT_S0_MASK,Mask bit for s0 protocol fault source." "0,1" newline bitfld.long 0x0 4. "ASF_PROTOCOL_FAULT_MST_SDR_RD_ABORT_MASK,Mask bit for mst_sdr_rd_abort protocol fault source." "0,1" newline bitfld.long 0x0 3. "ASF_PROTOCOL_FAULT_MST_DDR_FAIL_MASK,Mask bit for mst_ddr_fail protocol fault source." "0,1" newline bitfld.long 0x0 2. "ASF_PROTOCOL_FAULT_M2_MASK,Mask bit for m2 protocol fault source." "0,1" newline bitfld.long 0x0 1. "ASF_PROTOCOL_FAULT_M1_MASK,Mask bit for m1 protocol fault source." "0,1" newline bitfld.long 0x0 0. "ASF_PROTOCOL_FAULT_M0_MASK,Mask bit for m0 protocol fault source." "0,1" line.long 0x4 "VBP2APB_WRAP__CORE_VBP__MIPI_I3C_MST_REGS_asf_protocol_fault_status,Status register for protocol faults. If a fault occurs the relevant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit" hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x4 12. "ASF_PROTOCOL_FAULT_SLV_SDR_RD_ABORT_STATUS,Status bit for slv_sdr_rd_abort protocol fault." "0,1" newline bitfld.long 0x4 11. "ASF_PROTOCOL_FAULT_SLV_DDR_FAIL_STATUS,Status bit for slv_ddr_fail protocol fault." "0,1" newline bitfld.long 0x4 10. "ASF_PROTOCOL_FAULT_S5_STATUS,Status bit for s5 protocol fault." "0,1" newline bitfld.long 0x4 9. "ASF_PROTOCOL_FAULT_S4_STATUS,Status bit for s4 protocol fault." "0,1" newline bitfld.long 0x4 8. "ASF_PROTOCOL_FAULT_S3_STATUS,Status bit for s3 protocol fault." "0,1" newline bitfld.long 0x4 7. "ASF_PROTOCOL_FAULT_S2_STATUS,Status bit for s2 protocol fault." "0,1" newline bitfld.long 0x4 6. "ASF_PROTOCOL_FAULT_S1_STATUS,Status bit for s1 protocol fault." "0,1" newline bitfld.long 0x4 5. "ASF_PROTOCOL_FAULT_S0_STATUS,Status bit for s0 protocol fault." "0,1" newline bitfld.long 0x4 4. "ASF_PROTOCOL_FAULT_MST_SDR_RD_ABORT_STATUS,Status bit for mst_sdr_rd_abort protocol fault." "0,1" newline bitfld.long 0x4 3. "ASF_PROTOCOL_FAULT_MST_DDR_FAIL_STATUS,Status bit for mst_ddr_fail protocol fault." "0,1" newline bitfld.long 0x4 2. "ASF_PROTOCOL_FAULT_M2_STATUS,Status bit for m2 protocol fault." "0,1" newline bitfld.long 0x4 1. "ASF_PROTOCOL_FAULT_M1_STATUS,Status bit for m1 protocol fault." "0,1" newline bitfld.long 0x4 0. "ASF_PROTOCOL_FAULT_M0_STATUS,Status bit for m0 protocol fault." "0,1" tree.end tree.end tree "MCU_I3C1" tree "MCU_I3C1_MMR_MMRVBP (MCU_I3C1_MMR_MMRVBP)" base ad:0x40B90000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__REGS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end tree "MCU_I3C1_P_ECC_AGGR_CFG (MCU_I3C1_P_ECC_AGGR_CFG)" base ad:0x40722000 rgroup.long 0x0++0x3 line.long 0x0 "P_ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "P_ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "P_ECC_AGGR__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "P_ECC_AGGR__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "P_ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "P_ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "P_ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "P_ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "P_ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "P_ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "P_ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "P_ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "P_ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "P_ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "P_ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "P_ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCU_I3C1_S_ECC_AGGR_CFG (MCU_I3C1_S_ECC_AGGR_CFG)" base ad:0x40723000 rgroup.long 0x0++0x3 line.long 0x0 "S_ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "S_ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "S_ECC_AGGR__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "S_ECC_AGGR__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "S_ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "S_ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 8. "RX_DATA_PEND,Interrupt Pending Status for rx_data_pend" "0,1" bitfld.long 0x4 7. "CMD_WRD0_PEND,Interrupt Pending Status for cmd_wrd0_pend" "0,1" bitfld.long 0x4 6. "TX_DATA_PEND,Interrupt Pending Status for tx_data_pend" "0,1" newline bitfld.long 0x4 5. "CMD_WRD1_PEND,Interrupt Pending Status for cmd_wrd1_pend" "0,1" bitfld.long 0x4 4. "IBI_PEND,Interrupt Pending Status for ibi_pend" "0,1" bitfld.long 0x4 3. "SLV_DDR_TX_PEND,Interrupt Pending Status for slv_ddr_tx_pend" "0,1" newline bitfld.long 0x4 2. "CMDR_QUEUE_PEND,Interrupt Pending Status for cmdr_queue_pend" "0,1" bitfld.long 0x4 1. "SLV_DDR_RX_PEND,Interrupt Pending Status for slv_ddr_rx_pend" "0,1" bitfld.long 0x4 0. "IBIR_QUEUE_PEND,Interrupt Pending Status for ibir_queue_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "S_ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 8. "RX_DATA_ENABLE_SET,Interrupt Enable Set Register for rx_data_pend" "0,1" bitfld.long 0x0 7. "CMD_WRD0_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd0_pend" "0,1" bitfld.long 0x0 6. "TX_DATA_ENABLE_SET,Interrupt Enable Set Register for tx_data_pend" "0,1" newline bitfld.long 0x0 5. "CMD_WRD1_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd1_pend" "0,1" bitfld.long 0x0 4. "IBI_ENABLE_SET,Interrupt Enable Set Register for ibi_pend" "0,1" bitfld.long 0x0 3. "SLV_DDR_TX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_tx_pend" "0,1" newline bitfld.long 0x0 2. "CMDR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for cmdr_queue_pend" "0,1" bitfld.long 0x0 1. "SLV_DDR_RX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_rx_pend" "0,1" bitfld.long 0x0 0. "IBIR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for ibir_queue_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "S_ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 8. "RX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for rx_data_pend" "0,1" bitfld.long 0x0 7. "CMD_WRD0_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd0_pend" "0,1" bitfld.long 0x0 6. "TX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for tx_data_pend" "0,1" newline bitfld.long 0x0 5. "CMD_WRD1_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd1_pend" "0,1" bitfld.long 0x0 4. "IBI_ENABLE_CLR,Interrupt Enable Clear Register for ibi_pend" "0,1" bitfld.long 0x0 3. "SLV_DDR_TX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_tx_pend" "0,1" newline bitfld.long 0x0 2. "CMDR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for cmdr_queue_pend" "0,1" bitfld.long 0x0 1. "SLV_DDR_RX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_rx_pend" "0,1" bitfld.long 0x0 0. "IBIR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for ibir_queue_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "S_ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "S_ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 8. "RX_DATA_PEND,Interrupt Pending Status for rx_data_pend" "0,1" bitfld.long 0x4 7. "CMD_WRD0_PEND,Interrupt Pending Status for cmd_wrd0_pend" "0,1" bitfld.long 0x4 6. "TX_DATA_PEND,Interrupt Pending Status for tx_data_pend" "0,1" newline bitfld.long 0x4 5. "CMD_WRD1_PEND,Interrupt Pending Status for cmd_wrd1_pend" "0,1" bitfld.long 0x4 4. "IBI_PEND,Interrupt Pending Status for ibi_pend" "0,1" bitfld.long 0x4 3. "SLV_DDR_TX_PEND,Interrupt Pending Status for slv_ddr_tx_pend" "0,1" newline bitfld.long 0x4 2. "CMDR_QUEUE_PEND,Interrupt Pending Status for cmdr_queue_pend" "0,1" bitfld.long 0x4 1. "SLV_DDR_RX_PEND,Interrupt Pending Status for slv_ddr_rx_pend" "0,1" bitfld.long 0x4 0. "IBIR_QUEUE_PEND,Interrupt Pending Status for ibir_queue_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "S_ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 8. "RX_DATA_ENABLE_SET,Interrupt Enable Set Register for rx_data_pend" "0,1" bitfld.long 0x0 7. "CMD_WRD0_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd0_pend" "0,1" bitfld.long 0x0 6. "TX_DATA_ENABLE_SET,Interrupt Enable Set Register for tx_data_pend" "0,1" newline bitfld.long 0x0 5. "CMD_WRD1_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd1_pend" "0,1" bitfld.long 0x0 4. "IBI_ENABLE_SET,Interrupt Enable Set Register for ibi_pend" "0,1" bitfld.long 0x0 3. "SLV_DDR_TX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_tx_pend" "0,1" newline bitfld.long 0x0 2. "CMDR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for cmdr_queue_pend" "0,1" bitfld.long 0x0 1. "SLV_DDR_RX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_rx_pend" "0,1" bitfld.long 0x0 0. "IBIR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for ibir_queue_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "S_ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 8. "RX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for rx_data_pend" "0,1" bitfld.long 0x0 7. "CMD_WRD0_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd0_pend" "0,1" bitfld.long 0x0 6. "TX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for tx_data_pend" "0,1" newline bitfld.long 0x0 5. "CMD_WRD1_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd1_pend" "0,1" bitfld.long 0x0 4. "IBI_ENABLE_CLR,Interrupt Enable Clear Register for ibi_pend" "0,1" bitfld.long 0x0 3. "SLV_DDR_TX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_tx_pend" "0,1" newline bitfld.long 0x0 2. "CMDR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for cmdr_queue_pend" "0,1" bitfld.long 0x0 1. "SLV_DDR_RX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_rx_pend" "0,1" bitfld.long 0x0 0. "IBIR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for ibir_queue_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "S_ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "S_ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "S_ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "S_ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree.end tree "MCU_MCAN0" tree "MCU_MCAN0_CFG (MCU_MCAN0_CFG)" base ad:0x40528000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" rgroup.long 0x8++0x37 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point" newline hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection" rbitfld.long 0x8 7. "RX,Receive Pin" "0,1" bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM" hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration" bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1" bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1" bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1" newline bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0x10 0. "INIT,Initialization" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing" hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter" hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter" hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x4B line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" newline bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable" bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)" bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field" line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address" line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field" line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" rgroup.long 0x98++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x0 31. "ND31,New Data" "0,1" bitfld.long 0x0 30. "ND30,New Data" "0,1" bitfld.long 0x0 29. "ND29,New Data" "0,1" newline bitfld.long 0x0 28. "ND28,New Data" "0,1" bitfld.long 0x0 27. "ND27,New Data" "0,1" bitfld.long 0x0 26. "ND26,New Data" "0,1" newline bitfld.long 0x0 25. "ND25,New Data" "0,1" bitfld.long 0x0 24. "ND24,New Data" "0,1" bitfld.long 0x0 23. "ND23,New Data" "0,1" newline bitfld.long 0x0 22. "ND22,New Data" "0,1" bitfld.long 0x0 21. "ND21,New Data" "0,1" bitfld.long 0x0 20. "ND20,New Data" "0,1" newline bitfld.long 0x0 19. "ND19,New Data" "0,1" bitfld.long 0x0 18. "ND18,New Data" "0,1" bitfld.long 0x0 17. "ND17,New Data" "0,1" newline bitfld.long 0x0 16. "ND16,New Data" "0,1" bitfld.long 0x0 15. "ND15,New Data" "0,1" bitfld.long 0x0 14. "ND14,New Data" "0,1" newline bitfld.long 0x0 13. "ND13,New Data" "0,1" bitfld.long 0x0 12. "ND12,New Data" "0,1" bitfld.long 0x0 11. "ND11,New Data" "0,1" newline bitfld.long 0x0 10. "ND10,New Data" "0,1" bitfld.long 0x0 9. "ND9,New Data" "0,1" bitfld.long 0x0 8. "ND8,New Data" "0,1" newline bitfld.long 0x0 7. "ND7,New Data" "0,1" bitfld.long 0x0 6. "ND6,New Data" "0,1" bitfld.long 0x0 5. "ND5,New Data" "0,1" newline bitfld.long 0x0 4. "ND4,New Data" "0,1" bitfld.long 0x0 3. "ND3,New Data" "0,1" bitfld.long 0x0 2. "ND2,New Data" "0,1" newline bitfld.long 0x0 1. "ND1,New Data" "0,1" bitfld.long 0x0 0. "ND0,New Data" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x4 31. "ND63,New Data" "0,1" bitfld.long 0x4 30. "ND62,New Data" "0,1" bitfld.long 0x4 29. "ND61,New Data" "0,1" newline bitfld.long 0x4 28. "ND60,New Data" "0,1" bitfld.long 0x4 27. "ND59,New Data" "0,1" bitfld.long 0x4 26. "ND58,New Data" "0,1" newline bitfld.long 0x4 25. "ND57,New Data" "0,1" bitfld.long 0x4 24. "ND56,New Data" "0,1" bitfld.long 0x4 23. "ND55,New Data" "0,1" newline bitfld.long 0x4 22. "ND54,New Data" "0,1" bitfld.long 0x4 21. "ND53,New Data" "0,1" bitfld.long 0x4 20. "ND52,New Data" "0,1" newline bitfld.long 0x4 19. "ND51,New Data" "0,1" bitfld.long 0x4 18. "ND50,New Data" "0,1" bitfld.long 0x4 17. "ND49,New Data" "0,1" newline bitfld.long 0x4 16. "ND48,New Data" "0,1" bitfld.long 0x4 15. "ND47,New Data" "0,1" bitfld.long 0x4 14. "ND46,New Data" "0,1" newline bitfld.long 0x4 13. "ND45,New Data" "0,1" bitfld.long 0x4 12. "ND44,New Data" "0,1" bitfld.long 0x4 11. "ND43,New Data" "0,1" newline bitfld.long 0x4 10. "ND42,New Data" "0,1" bitfld.long 0x4 9. "ND41,New Data" "0,1" bitfld.long 0x4 8. "ND40,New Data" "0,1" newline bitfld.long 0x4 7. "ND39,New Data" "0,1" bitfld.long 0x4 6. "ND38,New Data" "0,1" bitfld.long 0x4 5. "ND37,New Data" "0,1" newline bitfld.long 0x4 4. "ND36,New Data" "0,1" bitfld.long 0x4 3. "ND35,New Data" "0,1" bitfld.long 0x4 2. "ND34,New Data" "0,1" newline bitfld.long 0x4 1. "ND33,New Data" "0,1" bitfld.long 0x4 0. "ND32,New Data" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" rgroup.long 0xA8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" rgroup.long 0xB8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" rgroup.long 0xC8++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1" rgroup.long 0xD0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests" bitfld.long 0x0 31. "AR31,Add request" "0,1" bitfld.long 0x0 30. "AR30,Add request" "0,1" bitfld.long 0x0 29. "AR29,Add request" "0,1" newline bitfld.long 0x0 28. "AR28,Add request" "0,1" bitfld.long 0x0 27. "AR27,Add request" "0,1" bitfld.long 0x0 26. "AR26,Add request" "0,1" newline bitfld.long 0x0 25. "AR25,Add request" "0,1" bitfld.long 0x0 24. "AR24,Add request" "0,1" bitfld.long 0x0 23. "AR23,Add request" "0,1" newline bitfld.long 0x0 22. "AR22,Add request" "0,1" bitfld.long 0x0 21. "AR21,Add request" "0,1" bitfld.long 0x0 20. "AR20,Add request" "0,1" newline bitfld.long 0x0 19. "AR19,Add request" "0,1" bitfld.long 0x0 18. "AR18,Add request" "0,1" bitfld.long 0x0 17. "AR17,Add request" "0,1" newline bitfld.long 0x0 16. "AR16,Add request" "0,1" bitfld.long 0x0 15. "AR15,Add request" "0,1" bitfld.long 0x0 14. "AR14,Add request" "0,1" newline bitfld.long 0x0 13. "AR13,Add request" "0,1" bitfld.long 0x0 12. "AR12,Add request" "0,1" bitfld.long 0x0 11. "AR11,Add request" "0,1" newline bitfld.long 0x0 10. "AR10,Add request" "0,1" bitfld.long 0x0 9. "AR9,Add request" "0,1" bitfld.long 0x0 8. "AR8,Add request" "0,1" newline bitfld.long 0x0 7. "AR7,Add request" "0,1" bitfld.long 0x0 6. "AR6,Add request" "0,1" bitfld.long 0x0 5. "AR5,Add request" "0,1" newline bitfld.long 0x0 4. "AR4,Add request" "0,1" bitfld.long 0x0 3. "AR3,Add request" "0,1" bitfld.long 0x0 2. "AR2,Add request" "0,1" newline bitfld.long 0x0 1. "AR1,Add request" "0,1" bitfld.long 0x0 0. "AR0,Add request" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions" bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1" rgroup.long 0xE0++0x13 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" rgroup.long 0xF8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field" tree.end tree "MCU_MCAN0_ECC_AGGR (MCU_MCAN0_ECC_AGGR)" base ad:0x40700000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCU_MCAN0_MSGMEM_RAM (MCU_MCAN0_MSGMEM_RAM)" base ad:0x40500000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCU_MCAN0_SS (MCU_MCAN0_SS)" base ad:0x40520000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0: Honor Debug Suspend,1: Disregard debug suspend" rgroup.long 0x8++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS" bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1" newline bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" rgroup.long 0xC++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1" rgroup.long 0x10++0xB line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits." bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1" line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1" line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" rgroup.long 0x24++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1" rgroup.long 0x28++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt" tree.end tree.end tree "MCU_MCAN1" tree "MCU_MCAN1_CFG (MCU_MCAN1_CFG)" base ad:0x40568000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" rgroup.long 0x8++0x37 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point" newline hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection" rbitfld.long 0x8 7. "RX,Receive Pin" "0,1" bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM" hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration" bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1" bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1" bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1" newline bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0x10 0. "INIT,Initialization" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing" hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter" hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter" hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x4B line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" newline bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable" bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)" bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field" line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address" line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field" line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" rgroup.long 0x98++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x0 31. "ND31,New Data" "0,1" bitfld.long 0x0 30. "ND30,New Data" "0,1" bitfld.long 0x0 29. "ND29,New Data" "0,1" newline bitfld.long 0x0 28. "ND28,New Data" "0,1" bitfld.long 0x0 27. "ND27,New Data" "0,1" bitfld.long 0x0 26. "ND26,New Data" "0,1" newline bitfld.long 0x0 25. "ND25,New Data" "0,1" bitfld.long 0x0 24. "ND24,New Data" "0,1" bitfld.long 0x0 23. "ND23,New Data" "0,1" newline bitfld.long 0x0 22. "ND22,New Data" "0,1" bitfld.long 0x0 21. "ND21,New Data" "0,1" bitfld.long 0x0 20. "ND20,New Data" "0,1" newline bitfld.long 0x0 19. "ND19,New Data" "0,1" bitfld.long 0x0 18. "ND18,New Data" "0,1" bitfld.long 0x0 17. "ND17,New Data" "0,1" newline bitfld.long 0x0 16. "ND16,New Data" "0,1" bitfld.long 0x0 15. "ND15,New Data" "0,1" bitfld.long 0x0 14. "ND14,New Data" "0,1" newline bitfld.long 0x0 13. "ND13,New Data" "0,1" bitfld.long 0x0 12. "ND12,New Data" "0,1" bitfld.long 0x0 11. "ND11,New Data" "0,1" newline bitfld.long 0x0 10. "ND10,New Data" "0,1" bitfld.long 0x0 9. "ND9,New Data" "0,1" bitfld.long 0x0 8. "ND8,New Data" "0,1" newline bitfld.long 0x0 7. "ND7,New Data" "0,1" bitfld.long 0x0 6. "ND6,New Data" "0,1" bitfld.long 0x0 5. "ND5,New Data" "0,1" newline bitfld.long 0x0 4. "ND4,New Data" "0,1" bitfld.long 0x0 3. "ND3,New Data" "0,1" bitfld.long 0x0 2. "ND2,New Data" "0,1" newline bitfld.long 0x0 1. "ND1,New Data" "0,1" bitfld.long 0x0 0. "ND0,New Data" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x4 31. "ND63,New Data" "0,1" bitfld.long 0x4 30. "ND62,New Data" "0,1" bitfld.long 0x4 29. "ND61,New Data" "0,1" newline bitfld.long 0x4 28. "ND60,New Data" "0,1" bitfld.long 0x4 27. "ND59,New Data" "0,1" bitfld.long 0x4 26. "ND58,New Data" "0,1" newline bitfld.long 0x4 25. "ND57,New Data" "0,1" bitfld.long 0x4 24. "ND56,New Data" "0,1" bitfld.long 0x4 23. "ND55,New Data" "0,1" newline bitfld.long 0x4 22. "ND54,New Data" "0,1" bitfld.long 0x4 21. "ND53,New Data" "0,1" bitfld.long 0x4 20. "ND52,New Data" "0,1" newline bitfld.long 0x4 19. "ND51,New Data" "0,1" bitfld.long 0x4 18. "ND50,New Data" "0,1" bitfld.long 0x4 17. "ND49,New Data" "0,1" newline bitfld.long 0x4 16. "ND48,New Data" "0,1" bitfld.long 0x4 15. "ND47,New Data" "0,1" bitfld.long 0x4 14. "ND46,New Data" "0,1" newline bitfld.long 0x4 13. "ND45,New Data" "0,1" bitfld.long 0x4 12. "ND44,New Data" "0,1" bitfld.long 0x4 11. "ND43,New Data" "0,1" newline bitfld.long 0x4 10. "ND42,New Data" "0,1" bitfld.long 0x4 9. "ND41,New Data" "0,1" bitfld.long 0x4 8. "ND40,New Data" "0,1" newline bitfld.long 0x4 7. "ND39,New Data" "0,1" bitfld.long 0x4 6. "ND38,New Data" "0,1" bitfld.long 0x4 5. "ND37,New Data" "0,1" newline bitfld.long 0x4 4. "ND36,New Data" "0,1" bitfld.long 0x4 3. "ND35,New Data" "0,1" bitfld.long 0x4 2. "ND34,New Data" "0,1" newline bitfld.long 0x4 1. "ND33,New Data" "0,1" bitfld.long 0x4 0. "ND32,New Data" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" rgroup.long 0xA8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" rgroup.long 0xB8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" rgroup.long 0xC8++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1" rgroup.long 0xD0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests" bitfld.long 0x0 31. "AR31,Add request" "0,1" bitfld.long 0x0 30. "AR30,Add request" "0,1" bitfld.long 0x0 29. "AR29,Add request" "0,1" newline bitfld.long 0x0 28. "AR28,Add request" "0,1" bitfld.long 0x0 27. "AR27,Add request" "0,1" bitfld.long 0x0 26. "AR26,Add request" "0,1" newline bitfld.long 0x0 25. "AR25,Add request" "0,1" bitfld.long 0x0 24. "AR24,Add request" "0,1" bitfld.long 0x0 23. "AR23,Add request" "0,1" newline bitfld.long 0x0 22. "AR22,Add request" "0,1" bitfld.long 0x0 21. "AR21,Add request" "0,1" bitfld.long 0x0 20. "AR20,Add request" "0,1" newline bitfld.long 0x0 19. "AR19,Add request" "0,1" bitfld.long 0x0 18. "AR18,Add request" "0,1" bitfld.long 0x0 17. "AR17,Add request" "0,1" newline bitfld.long 0x0 16. "AR16,Add request" "0,1" bitfld.long 0x0 15. "AR15,Add request" "0,1" bitfld.long 0x0 14. "AR14,Add request" "0,1" newline bitfld.long 0x0 13. "AR13,Add request" "0,1" bitfld.long 0x0 12. "AR12,Add request" "0,1" bitfld.long 0x0 11. "AR11,Add request" "0,1" newline bitfld.long 0x0 10. "AR10,Add request" "0,1" bitfld.long 0x0 9. "AR9,Add request" "0,1" bitfld.long 0x0 8. "AR8,Add request" "0,1" newline bitfld.long 0x0 7. "AR7,Add request" "0,1" bitfld.long 0x0 6. "AR6,Add request" "0,1" bitfld.long 0x0 5. "AR5,Add request" "0,1" newline bitfld.long 0x0 4. "AR4,Add request" "0,1" bitfld.long 0x0 3. "AR3,Add request" "0,1" bitfld.long 0x0 2. "AR2,Add request" "0,1" newline bitfld.long 0x0 1. "AR1,Add request" "0,1" bitfld.long 0x0 0. "AR0,Add request" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions" bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1" rgroup.long 0xE0++0x13 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" rgroup.long 0xF8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field" tree.end tree "MCU_MCAN1_ECC_AGGR (MCU_MCAN1_ECC_AGGR)" base ad:0x40701000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCU_MCAN1_MSGMEM_RAM (MCU_MCAN1_MSGMEM_RAM)" base ad:0x40540000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCU_MCAN1_SS (MCU_MCAN1_SS)" base ad:0x40560000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0: Honor Debug Suspend,1: Disregard debug suspend" rgroup.long 0x8++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS" bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1" newline bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" rgroup.long 0xC++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1" rgroup.long 0x10++0xB line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits." bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1" line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1" line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" rgroup.long 0x24++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1" rgroup.long 0x28++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt" tree.end tree.end tree "MCU_MSRAM_1MB0" tree "MCU_MSRAM_1MB0_ECC_AGGR_REGS (MCU_MSRAM_1MB0_ECC_AGGR_REGS)" base ad:0x4070B000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_REGSREGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_REGSREGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" bitfld.long 0x4 1. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" bitfld.long 0x0 1. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" bitfld.long 0x0 1. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_REGSREGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_REGSREGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" bitfld.long 0x4 1. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" bitfld.long 0x0 1. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" bitfld.long 0x0 1. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "ECC_AGGR_REGSREGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_REGSREGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_REGSREGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_REGSREGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCU_MSRAM_1MB0_RAM (MCU_MSRAM_1MB0_RAM)" base ad:0x41C00000 rgroup.long 0x0++0x3 line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree.end tree "MCU_R5FSS0" tree "MCU_R5FSS0_COMMON0" tree "MCU_R5FSS0_COMMON0_COMPARE_CFG (MCU_R5FSS0_COMMON0_COMPARE_CFG)" base ad:0x400F0000 rgroup.long 0x0++0x7 line.long 0x0 "PULSAR_SL_COMPARE_WRAPPER__CFG__MMRS_CCMSR1,Shows the Error and Self test Status of the CPU CPU Compare block." hexmask.long.word 0x0 17.--31. 1. "RESERVED2,This is the Reserved field" bitfld.long 0x0 16. "CMPE1,This is the CMPE1 field" "0,1" hexmask.long.byte 0x0 9.--15. 1. "RESERVED1,This is the Reserved field" rbitfld.long 0x0 8. "STC1,This is the STC1 field" "0,1" hexmask.long.byte 0x0 2.--7. 1. "RESERVED0,This is the Reserved field" rbitfld.long 0x0 1. "STET1,This is the STET1 field" "0,1" newline rbitfld.long 0x0 0. "STE1,This is the STE1 field" "0,1" line.long 0x4 "PULSAR_SL_COMPARE_WRAPPER__CFG__MMRS_CCMKEYR1,Selects Operating mode of CPU Compare block." hexmask.long 0x4 4.--31. 1. "RESERVED,This is the Reserved field" hexmask.long.byte 0x4 0.--3. 1. "MKEY1,This is the MKEY1 field" rgroup.long 0x10++0xB line.long 0x0 "PULSAR_SL_COMPARE_WRAPPER__CFG__MMRS_CCMSR3,Shows the Error and Self test Status of the CPU CPU Compare block." hexmask.long.word 0x0 17.--31. 1. "RESERVED2,This is the Reserved field" bitfld.long 0x0 16. "CMPE3,This is the CMPE3 field" "0,1" hexmask.long.byte 0x0 9.--15. 1. "RESERVED1,This is the Reserved field" rbitfld.long 0x0 8. "STC3,This is the STC3 field" "0,1" hexmask.long.byte 0x0 2.--7. 1. "RESERVED0,This is the Reserved field" rbitfld.long 0x0 1. "STET3,This is the STET3 field" "0,1" newline rbitfld.long 0x0 0. "STE3,This is the STE3 field" "0,1" line.long 0x4 "PULSAR_SL_COMPARE_WRAPPER__CFG__MMRS_CCMKEYR3,Selects Operating mode of CPU Compare block." hexmask.long 0x4 4.--31. 1. "RESERVED,This is the Reserved field" hexmask.long.byte 0x4 0.--3. 1. "MKEY3,This is the MKEY3 field" line.long 0x8 "PULSAR_SL_COMPARE_WRAPPER__CFG__MMRS_CCMPOLCNTRL,Selects Operating mode of CPU Compare block." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,This is the Reserved field" hexmask.long.byte 0x8 0.--7. 1. "POL_INV,This is the Polarity Inversion field" tree.end tree "MCU_R5FSS0_COMMON0_EVNT_BUS_VBUSP_MMRS (MCU_R5FSS0_COMMON0_EVNT_BUS_VBUSP_MMRS)" base ad:0x4072F000 rgroup.long 0x0++0x3 line.long 0x0 "EVNT_BUS__VBUSP__MMRS_DISABLE_CR,This register contains config bits to enable or disable change requests added to the IP" bitfld.long 0x0 0. "COMBINE_TCM_LOCKSTEP_MODE,this bit disables the CR logic to combine TCM in lockstep mode" "0,1" rgroup.long 0x4++0x13 line.long 0x0 "EVNT_BUS__VBUSP__MMRS_PULSAR_CPU0_EVNT_BUS_SB_ERR_CNT_STATUS,Status bits showing the PULSAR CPU0 EVNT_BUS single bit error counters" bitfld.long 0x0 16.--17. "EVNT_BUS8,Status bits showing the PULSAR CPU0 EVNT 8 single bit error counter." "0,1,2,3" bitfld.long 0x0 14.--15. "EVNT_BUS7,Status bits showing the PULSAR CPU0 EVNT 7 single bit error counter." "0,1,2,3" newline bitfld.long 0x0 12.--13. "EVNT_BUS6,Status bits showing the PULSAR CPU0 EVNT 6 single bit error counter." "0,1,2,3" bitfld.long 0x0 10.--11. "EVNT_BUS5,Status bits showing the PULSAR CPU0 EVNT 5 single bit error counter." "0,1,2,3" newline bitfld.long 0x0 8.--9. "EVNT_BUS4,Status bits showing the PULSAR CPU0 EVNT 4 single bit error counter." "0,1,2,3" bitfld.long 0x0 6.--7. "EVNT_BUS3,Status bits showing the PULSAR CPU0 EVNT 3 single bit error counter." "0,1,2,3" newline bitfld.long 0x0 4.--5. "EVNT_BUS2,Status bits showing the PULSAR CPU0 EVNT 2 single bit error counter." "0,1,2,3" bitfld.long 0x0 2.--3. "EVNT_BUS1,Status bits showing the PULSAR CPU0 EVNT 1 single bit error counter." "0,1,2,3" newline bitfld.long 0x0 0.--1. "EVNT_BUS0,Status bits showing the PULSAR CPU0 EVNT 0 single bit error counter." "0,1,2,3" line.long 0x4 "EVNT_BUS__VBUSP__MMRS_PULSAR_CPU1_EVNT_BUS_SB_ERR_CNT_STATUS,Status bits showing the PULSAR CPU1 EVNT_BUS single bit error counters" bitfld.long 0x4 16.--17. "EVNT_BUS8,Status bits showing the PULSAR CPU1 EVNT 8 single bit error counter." "0,1,2,3" bitfld.long 0x4 14.--15. "EVNT_BUS7,Status bits showing the PULSAR CPU1 EVNT 7 single bit error counter." "0,1,2,3" newline bitfld.long 0x4 12.--13. "EVNT_BUS6,Status bits showing the PULSAR CPU1 EVNT 6 single bit error counter." "0,1,2,3" bitfld.long 0x4 10.--11. "EVNT_BUS5,Status bits showing the PULSAR CPU1 EVNT 5 single bit error counter." "0,1,2,3" newline bitfld.long 0x4 8.--9. "EVNT_BUS4,Status bits showing the PULSAR CPU1 EVNT 4 single bit error counter." "0,1,2,3" bitfld.long 0x4 6.--7. "EVNT_BUS3,Status bits showing the PULSAR CPU1 EVNT 3 single bit error counter." "0,1,2,3" newline bitfld.long 0x4 4.--5. "EVNT_BUS2,Status bits showing the PULSAR CPU1 EVNT 2 single bit error counter." "0,1,2,3" bitfld.long 0x4 2.--3. "EVNT_BUS1,Status bits showing the PULSAR CPU1 EVNT 1 single bit error counter." "0,1,2,3" newline bitfld.long 0x4 0.--1. "EVNT_BUS0,Status bits showing the PULSAR CPU1 EVNT 0 single bit error counter." "0,1,2,3" line.long 0x8 "EVNT_BUS__VBUSP__MMRS_PULSAR_CPU0_EVNT_BUS_MB_ERR_CNT_STATUS,Status bits showing the PULSAR CPU0 EVNT_BUS multi bit error counters" bitfld.long 0x8 12.--13. "EVNT_BUS6,Status bits showing the PULSAR CPU0 EVNT 6 multi bit error counter." "0,1,2,3" bitfld.long 0x8 10.--11. "EVNT_BUS5,Status bits showing the PULSAR CPU0 EVNT 5 multi bit error counter." "0,1,2,3" newline bitfld.long 0x8 8.--9. "EVNT_BUS4,Status bits showing the PULSAR CPU0 EVNT 4 multi bit error counter." "0,1,2,3" bitfld.long 0x8 6.--7. "EVNT_BUS3,Status bits showing the PULSAR CPU0 EVNT 3 multi bit error counter." "0,1,2,3" newline bitfld.long 0x8 4.--5. "EVNT_BUS2,Status bits showing the PULSAR CPU0 EVNT 2 multi bit error counter." "0,1,2,3" bitfld.long 0x8 2.--3. "EVNT_BUS1,Status bits showing the PULSAR CPU0 EVNT 1 multi bit error counter." "0,1,2,3" newline bitfld.long 0x8 0.--1. "EVNT_BUS0,Status bits showing the PULSAR CPU0 EVNT 0 multi bit error counter." "0,1,2,3" line.long 0xC "EVNT_BUS__VBUSP__MMRS_PULSAR_CPU1_EVNT_BUS_MB_ERR_CNT_STATUS,Status bits showing the PULSAR CPU1 EVNT_BUS multi bit error counters" bitfld.long 0xC 12.--13. "EVNT_BUS6,Status bits showing the PULSAR CPU1 EVNT 6 multi bit error counter." "0,1,2,3" bitfld.long 0xC 10.--11. "EVNT_BUS5,Status bits showing the PULSAR CPU1 EVNT 5 multi bit error counter." "0,1,2,3" newline bitfld.long 0xC 8.--9. "EVNT_BUS4,Status bits showing the PULSAR CPU1 EVNT 4 multi bit error counter." "0,1,2,3" bitfld.long 0xC 6.--7. "EVNT_BUS3,Status bits showing the PULSAR CPU1 EVNT 3 multi bit error counter." "0,1,2,3" newline bitfld.long 0xC 4.--5. "EVNT_BUS2,Status bits showing the PULSAR CPU1 EVNT 2 multi bit error counter." "0,1,2,3" bitfld.long 0xC 2.--3. "EVNT_BUS1,Status bits showing the PULSAR CPU1 EVNT 1 multi bit error counter." "0,1,2,3" newline bitfld.long 0xC 0.--1. "EVNT_BUS0,Status bits showing the PULSAR CPU1 EVNT 0 multi bit error counter." "0,1,2,3" line.long 0x10 "EVNT_BUS__VBUSP__MMRS_PULSAR_EVNT_BUS_ESM_STATUS,ESM status bits for the PULSAR EVNT BUS" bitfld.long 0x10 3. "CPU1_MULTIPLE_BIT_ERROR,ESM status of CPU1 multiple bit errors on EVNT BUS" "0,1" bitfld.long 0x10 2. "CPU1_SINGLE_BIT_ERROR,ESM status of CPU1 single bit errors on EVNT BUS" "0,1" newline bitfld.long 0x10 1. "CPU0_MULTIPLE_BIT_ERROR,ESM status of CPU0 multiple bit errors on EVNT BUS" "0,1" bitfld.long 0x10 0. "CPU0_SINGLE_BIT_ERROR,ESM status of CPU0 single bit errors on EVNT BUS" "0,1" rgroup.long 0x18++0xF line.long 0x0 "EVNT_BUS__VBUSP__MMRS_PULSAR_EVNT_BUS_ESM_SET,SET the PULSAR EVNT BUS ESM events" bitfld.long 0x0 3. "CPU1_MULTIPLE_BIT_ERROR,SET CPU1 multiple bit errors ESM event" "0,1" bitfld.long 0x0 2. "CPU1_SINGLE_BIT_ERROR,SET CPU1 single bit errors ESM event" "0,1" newline bitfld.long 0x0 1. "CPU0_MULTIPLE_BIT_ERROR,SET CPU0 multiple bit error ESM event" "0,1" bitfld.long 0x0 0. "CPU0_SINGLE_BIT_ERROR,SET CPU0 single bit error ESM event" "0,1" line.long 0x4 "EVNT_BUS__VBUSP__MMRS_PULSAR_EVNT_BUS_ESM_CLR,RESET the PULSAR EVNT BUS ESM events" bitfld.long 0x4 31. "CPU1_EB6_MULTIPLE_BIT_ERROR,Decrement CPU1 Event Bus 31 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 30. "CPU1_EB5_MULTIPLE_BIT_ERROR,Decrement CPU1 Event Bus 30 MULTIPLE BIT Error Counter" "0,1" newline bitfld.long 0x4 29. "CPU1_EB4_MULTIPLE_BIT_ERROR,Decrement CPU1 Event Bus 29 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 28. "CPU1_EB3_MULTIPLE_BIT_ERROR,Decrement CPU1 Event Bus 28 MULTIPLE BIT Error Counter" "0,1" newline bitfld.long 0x4 27. "CPU1_EB2_MULTIPLE_BIT_ERROR,Decrement CPU1 Event Bus 27 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 26. "CPU1_EB1_MULTIPLE_BIT_ERROR,Decrement CPU1 Event Bus 26 MULTIPLE BIT Error Counter" "0,1" newline bitfld.long 0x4 25. "CPU1_EB0_MULTIPLE_BIT_ERROR,Decrement CPU1 Event Bus 25 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 24. "CPU1_EB8_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 24 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 23. "CPU1_EB7_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 23 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 22. "CPU1_EB6_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 22 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 21. "CPU1_EB5_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 21 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 20. "CPU1_EB4_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 20 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 19. "CPU1_EB3_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 19 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 18. "CPU1_EB2_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 18 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 17. "CPU1_EB1_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 17 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 16. "CPU1_EB0_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 16 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 15. "CPU0_EB6_MULTIPLE_BIT_ERROR,Decrement CPU0 Event Bus 15 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 14. "CPU0_EB5_MULTIPLE_BIT_ERROR,Decrement CPU0 Event Bus 14 MULTIPLE BIT Error Counter" "0,1" newline bitfld.long 0x4 13. "CPU0_EB4_MULTIPLE_BIT_ERROR,Decrement CPU0 Event Bus 13 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 12. "CPU0_EB3_MULTIPLE_BIT_ERROR,Decrement CPU0 Event Bus 12 MULTIPLE BIT Error Counter" "0,1" newline bitfld.long 0x4 11. "CPU0_EB2_MULTIPLE_BIT_ERROR,Decrement CPU0 Event Bus 11 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 10. "CPU0_EB1_MULTIPLE_BIT_ERROR,Decrement CPU0 Event Bus 10 MULTIPLE BIT Error Counter" "0,1" newline bitfld.long 0x4 9. "CPU0_EB0_MULTIPLE_BIT_ERROR,Decrement CPU0 Event Bus 9 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 8. "CPU0_EB8_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 8 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 7. "CPU0_EB7_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 7 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 6. "CPU0_EB6_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 6 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 5. "CPU0_EB5_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 5 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 4. "CPU0_EB4_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 4 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 3. "CPU0_EB3_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 3 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 2. "CPU0_EB2_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 2 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 1. "CPU0_EB1_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 1 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 0. "CPU0_EB0_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 0 SINGLE BIT Error Counter" "0,1" line.long 0x8 "EVNT_BUS__VBUSP__MMRS_PULSAR_EVNT_BUS_MASK_ESM_SET,MASK the PULSAR EVNT BUS ESM events" bitfld.long 0x8 3. "CPU1_MULTIPLE_BIT_ERROR,MASK CPU1 multiple bit errors ESM event" "0,1" bitfld.long 0x8 2. "CPU1_SINGLE_BIT_ERROR,MASK CPU1 single bit errors ESM event" "0,1" newline bitfld.long 0x8 1. "CPU0_MULTIPLE_BIT_ERROR,MASK CPU0 multiple bit error ESM event" "0,1" bitfld.long 0x8 0. "CPU0_SINGLE_BIT_ERROR,MASK CPU0 single bit error ESM event" "0,1" line.long 0xC "EVNT_BUS__VBUSP__MMRS_PULSAR_EVNT_BUS_MASK_ESM_CLR,UNMASK the PULSAR EVNT BUS ESM events" bitfld.long 0xC 3. "CPU1_MULTIPLE_BIT_ERROR,UNMASK CPU1 multiple bit errors ESM event" "0,1" bitfld.long 0xC 2. "CPU1_SINGLE_BIT_ERROR,UNMASK CPU1 single bit errors ESM event" "0,1" newline bitfld.long 0xC 1. "CPU0_MULTIPLE_BIT_ERROR,UNMASK CPU0 multiple bit error ESM event" "0,1" bitfld.long 0xC 0. "CPU0_SINGLE_BIT_ERROR,UNMASK CPU0 single bit error ESM event" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "EVNT_BUS__VBUSP__MMRS_PULSAR_EVT_BUS_REVID,Module ID register" hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release" newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" tree.end tree.end tree "MCU_R5FSS0_CORE0_ECC_AGGR_CORE0_ECC_AGGR (MCU_R5FSS0_CORE0_ECC_AGGR_CORE0_ECC_AGGR)" base ad:0x40080000 rgroup.long 0x0++0x3 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "CPU0_ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_periph_mst_ramecc_pend" "0,1" newline bitfld.long 0x4 30. "CPU0_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 29. "CPU0_AXI2VBUSM_MEM_MST_RAMECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_mem_mst_ramecc_pend" "0,1" newline bitfld.long 0x4 28. "CPU0_VBUSM2AXI_EDC_PEND,Interrupt Pending Status for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x4 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "B1TCM0_BANK1_PEND,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM0_BANK0_PEND,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x4 24. "B0TCM0_BANK1_PEND,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM0_BANK0_PEND,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x4 22. "ATCM0_BANK1_PEND,Interrupt Pending Status for atcm0_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM0_BANK0_PEND,Interrupt Pending Status for atcm0_bank0_pend" "0,1" newline bitfld.long 0x4 20. "CPU0_DDATA_RAM7_PEND,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_DDATA_RAM6_PEND,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x4 18. "CPU0_DDATA_RAM5_PEND,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_DDATA_RAM4_PEND,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x4 16. "CPU0_DDATA_RAM3_PEND,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_DDATA_RAM2_PEND,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x4 14. "CPU0_DDATA_RAM1_PEND,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_DDATA_RAM0_PEND,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x4 12. "CPU0_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_DTAG_RAM3_PEND,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x4 10. "CPU0_DTAG_RAM2_PEND,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_DTAG_RAM1_PEND,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x4 8. "CPU0_DTAG_RAM0_PEND,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_IDATA_BANK3_PEND,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x4 6. "CPU0_IDATA_BANK2_PEND,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_IDATA_BANK1_PEND,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x4 4. "CPU0_IDATA_BANK0_PEND,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_ITAG_RAM3_PEND,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x4 2. "CPU0_ITAG_RAM2_PEND,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_ITAG_RAM1_PEND,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_ITAG_RAM0_PEND,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1" line.long 0x8 "CPU0_ECC_AGGR__CFG__REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 3. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x8 2. "SCRP_EDC_PEND,Interrupt Pending Status for scrp_edc_pend" "0,1" newline bitfld.long 0x8 1. "CPU0_AHB2VBUSP_EDC_PEND,Interrupt Pending Status for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x8 0. "CPU0_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x80++0x7 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_periph_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "CPU0_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU0_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_mem_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "CPU0_VBUSM2AXI_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1" line.long 0x4 "CPU0_ECC_AGGR__CFG__REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 3. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x4 2. "SCRP_EDC_ENABLE_SET,Interrupt Enable Set Register for scrp_edc_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_AHB2VBUSP_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_periph_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "CPU0_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU0_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_mem_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "CPU0_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram0_pend" "0,1" line.long 0x4 "CPU0_ECC_AGGR__CFG__REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 3. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x4 2. "SCRP_EDC_ENABLE_CLR,Interrupt Enable Clear Register for scrp_edc_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x13C++0xB line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "CPU0_ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_periph_mst_ramecc_pend" "0,1" newline bitfld.long 0x4 30. "CPU0_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 29. "CPU0_AXI2VBUSM_MEM_MST_RAMECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_mem_mst_ramecc_pend" "0,1" newline bitfld.long 0x4 28. "CPU0_VBUSM2AXI_EDC_PEND,Interrupt Pending Status for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x4 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "B1TCM0_BANK1_PEND,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM0_BANK0_PEND,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x4 24. "B0TCM0_BANK1_PEND,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM0_BANK0_PEND,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x4 22. "ATCM0_BANK1_PEND,Interrupt Pending Status for atcm0_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM0_BANK0_PEND,Interrupt Pending Status for atcm0_bank0_pend" "0,1" newline bitfld.long 0x4 20. "CPU0_DDATA_RAM7_PEND,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_DDATA_RAM6_PEND,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x4 18. "CPU0_DDATA_RAM5_PEND,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_DDATA_RAM4_PEND,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x4 16. "CPU0_DDATA_RAM3_PEND,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_DDATA_RAM2_PEND,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x4 14. "CPU0_DDATA_RAM1_PEND,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_DDATA_RAM0_PEND,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x4 12. "CPU0_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_DTAG_RAM3_PEND,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x4 10. "CPU0_DTAG_RAM2_PEND,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_DTAG_RAM1_PEND,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x4 8. "CPU0_DTAG_RAM0_PEND,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_IDATA_BANK3_PEND,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x4 6. "CPU0_IDATA_BANK2_PEND,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_IDATA_BANK1_PEND,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x4 4. "CPU0_IDATA_BANK0_PEND,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_ITAG_RAM3_PEND,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x4 2. "CPU0_ITAG_RAM2_PEND,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_ITAG_RAM1_PEND,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_ITAG_RAM0_PEND,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1" line.long 0x8 "CPU0_ECC_AGGR__CFG__REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 3. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x8 2. "SCRP_EDC_PEND,Interrupt Pending Status for scrp_edc_pend" "0,1" newline bitfld.long 0x8 1. "CPU0_AHB2VBUSP_EDC_PEND,Interrupt Pending Status for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x8 0. "CPU0_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x180++0x7 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_periph_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "CPU0_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU0_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_mem_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "CPU0_VBUSM2AXI_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1" line.long 0x4 "CPU0_ECC_AGGR__CFG__REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 3. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x4 2. "SCRP_EDC_ENABLE_SET,Interrupt Enable Set Register for scrp_edc_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_AHB2VBUSP_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_periph_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "CPU0_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU0_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_mem_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "CPU0_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram0_pend" "0,1" line.long 0x4 "CPU0_ECC_AGGR__CFG__REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 3. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x4 2. "SCRP_EDC_ENABLE_CLR,Interrupt Enable Clear Register for scrp_edc_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "CPU0_ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "CPU0_ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "CPU0_ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCU_R5FSS0_CORE1_ECC_AGGR_CORE1_ECC_AGGR (MCU_R5FSS0_CORE1_ECC_AGGR_CORE1_ECC_AGGR)" base ad:0x400C0000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_periph_mst_ramecc_pend" "0,1" bitfld.long 0x4 30. "CPU1_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 29. "CPU1_AXI2VBUSM_MEM_MST_RAMECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_mem_mst_ramecc_pend" "0,1" bitfld.long 0x4 28. "CPU1_VBUSM2AXI_EDC_PEND,Interrupt Pending Status for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x4 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x4 26. "B1TCM1_BANK1_PEND,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM1_BANK0_PEND,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1" bitfld.long 0x4 24. "B0TCM1_BANK1_PEND,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM1_BANK0_PEND,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1" bitfld.long 0x4 22. "ATCM1_BANK1_PEND,Interrupt Pending Status for atcm1_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM1_BANK0_PEND,Interrupt Pending Status for atcm1_bank0_pend" "0,1" bitfld.long 0x4 20. "CPU1_DDATA_RAM7_PEND,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_DDATA_RAM6_PEND,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x4 18. "CPU1_DDATA_RAM5_PEND,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_DDATA_RAM4_PEND,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x4 16. "CPU1_DDATA_RAM3_PEND,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_DDATA_RAM2_PEND,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x4 14. "CPU1_DDATA_RAM1_PEND,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_DDATA_RAM0_PEND,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x4 12. "CPU1_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_DTAG_RAM3_PEND,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x4 10. "CPU1_DTAG_RAM2_PEND,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_DTAG_RAM1_PEND,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x4 8. "CPU1_DTAG_RAM0_PEND,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_IDATA_BANK3_PEND,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x4 6. "CPU1_IDATA_BANK2_PEND,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_IDATA_BANK1_PEND,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x4 4. "CPU1_IDATA_BANK0_PEND,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_ITAG_RAM3_PEND,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x4 2. "CPU1_ITAG_RAM2_PEND,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_ITAG_RAM1_PEND,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x4 0. "CPU1_ITAG_RAM0_PEND,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1" line.long 0x8 "REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 2. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" bitfld.long 0x8 1. "CPU1_AHB2VBUSP_EDC_PEND,Interrupt Pending Status for cpu1_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x8 0. "CPU1_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x80++0x7 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_periph_mst_ramecc_pend" "0,1" bitfld.long 0x0 30. "CPU1_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU1_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_mem_mst_ramecc_pend" "0,1" bitfld.long 0x0 28. "CPU1_VBUSM2AXI_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1" line.long 0x4 "REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 2. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" bitfld.long 0x4 1. "CPU1_AHB2VBUSP_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU1_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_periph_mst_ramecc_pend" "0,1" bitfld.long 0x0 30. "CPU1_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU1_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_mem_mst_ramecc_pend" "0,1" bitfld.long 0x0 28. "CPU1_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram0_pend" "0,1" line.long 0x4 "REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 2. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" bitfld.long 0x4 1. "CPU1_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU1_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x13C++0xB line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_periph_mst_ramecc_pend" "0,1" bitfld.long 0x4 30. "CPU1_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 29. "CPU1_AXI2VBUSM_MEM_MST_RAMECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_mem_mst_ramecc_pend" "0,1" bitfld.long 0x4 28. "CPU1_VBUSM2AXI_EDC_PEND,Interrupt Pending Status for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x4 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x4 26. "B1TCM1_BANK1_PEND,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM1_BANK0_PEND,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1" bitfld.long 0x4 24. "B0TCM1_BANK1_PEND,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM1_BANK0_PEND,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1" bitfld.long 0x4 22. "ATCM1_BANK1_PEND,Interrupt Pending Status for atcm1_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM1_BANK0_PEND,Interrupt Pending Status for atcm1_bank0_pend" "0,1" bitfld.long 0x4 20. "CPU1_DDATA_RAM7_PEND,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_DDATA_RAM6_PEND,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x4 18. "CPU1_DDATA_RAM5_PEND,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_DDATA_RAM4_PEND,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x4 16. "CPU1_DDATA_RAM3_PEND,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_DDATA_RAM2_PEND,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x4 14. "CPU1_DDATA_RAM1_PEND,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_DDATA_RAM0_PEND,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x4 12. "CPU1_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_DTAG_RAM3_PEND,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x4 10. "CPU1_DTAG_RAM2_PEND,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_DTAG_RAM1_PEND,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x4 8. "CPU1_DTAG_RAM0_PEND,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_IDATA_BANK3_PEND,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x4 6. "CPU1_IDATA_BANK2_PEND,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_IDATA_BANK1_PEND,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x4 4. "CPU1_IDATA_BANK0_PEND,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_ITAG_RAM3_PEND,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x4 2. "CPU1_ITAG_RAM2_PEND,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_ITAG_RAM1_PEND,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x4 0. "CPU1_ITAG_RAM0_PEND,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1" line.long 0x8 "REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 2. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" bitfld.long 0x8 1. "CPU1_AHB2VBUSP_EDC_PEND,Interrupt Pending Status for cpu1_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x8 0. "CPU1_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x180++0x7 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_periph_mst_ramecc_pend" "0,1" bitfld.long 0x0 30. "CPU1_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU1_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_mem_mst_ramecc_pend" "0,1" bitfld.long 0x0 28. "CPU1_VBUSM2AXI_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1" line.long 0x4 "REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 2. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" bitfld.long 0x4 1. "CPU1_AHB2VBUSP_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU1_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_periph_mst_ramecc_pend" "0,1" bitfld.long 0x0 30. "CPU1_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU1_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_mem_mst_ramecc_pend" "0,1" bitfld.long 0x0 28. "CPU1_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram0_pend" "0,1" line.long 0x4 "REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 2. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" bitfld.long 0x4 1. "CPU1_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU1_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree.end tree "MCU_SEC_MMR0" tree "MCU_SEC_MMR0_CFG0 (MCU_SEC_MMR0_CFG0)" base ad:0x45A50000 rgroup.long 0x0++0x3 line.long 0x0 "CFG0_PID," hexmask.long.word 0x0 16.--31. 1. "PID_MSB16," hexmask.long.byte 0x0 11.--15. 1. "PID_MISC," newline bitfld.long 0x0 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "PID_CUSTOM," "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR," rgroup.long 0x20++0x3 line.long 0x0 "CFG0_CLSTR0_DEF," bitfld.long 0x0 16.--18. "CLSTR0_DEF_CORE_NUM,Number of cores in cluster" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--15. 1. "CLSTR0_DEF_DSP_CORE_TYPE,DSP core type configuration" newline hexmask.long.byte 0x0 0.--7. 1. "CLSTR0_DEF_ARM_CORE_TYPE,ARM core type configuration" rgroup.long 0x40++0x3 line.long 0x0 "CFG0_CLSTR0_CFG," hexmask.long 0x0 5.--31. 1. "CLSTR0_CFG_CLSTR_CFG_RSVD,Reserved for future use. Write '0' to ensure compatibility with future devices." bitfld.long 0x0 4. "CLSTR0_CFG_MEM_INIT_DIS,Disables SRAM initialization (TCM etc) at reset " "0,1" newline rbitfld.long 0x0 3. "CLSTR0_CFG_LOCKSTEP_EN,Lockstep enable. Indicates if R5 lockstep operation is supported on the device" "0,1" bitfld.long 0x0 2. "CLSTR0_CFG_DBG_NO_CLKSTOP,CPU clockstop behavior" "0,1" newline bitfld.long 0x0 1. "CLSTR0_CFG_TEINIT,Exception handling state at reset:" "0,1" bitfld.long 0x0 0. "CLSTR0_CFG_LOCKSTEP,When set Core0 and Core1 operate in lockstep mode. Can only be changed if lockstep operation is supported as indicated by CLSTR0_CFG_lockstep_en = 1. If CLSTR0_CFG_lockstep_en = 0 lockstep is not supported this bit will be read.." "0,1" rgroup.long 0x80++0x3 line.long 0x0 "CFG0_CLSTR0_PMCTRL," hexmask.long 0x0 0.--31. 1. "RESERVED,Not used for Pulsar" rgroup.long 0x90++0x3 line.long 0x0 "CFG0_CLSTR0_PMSTAT," hexmask.long 0x0 0.--31. 1. "RESERVED,Not used for Pulsar" rgroup.long 0x100++0x3 line.long 0x0 "CFG0_CLSTR0_CORE0_CFG," bitfld.long 0x0 15. "CLSTR0_CORE0_CFG_NMFI_EN,Enable Core0 Non-Maskable Fast Interrupts" "0,1" bitfld.long 0x0 11. "CLSTR0_CORE0_CFG_TCM_RSTBASE,Core0 A/BTCM Reset Base Address Indicator" "0,1" newline bitfld.long 0x0 7. "CLSTR0_CORE0_CFG_BTCM_EN,Enable Core0 BTCM RAM at reset" "0,1" bitfld.long 0x0 3. "CLSTR0_CORE0_CFG_ATCM_EN,Enable Core0 ATCM RAM at reset" "0,1" rgroup.long 0x110++0x7 line.long 0x0 "CFG0_CLSTR0_CORE0_BOOTVECT_LO," hexmask.long 0x0 7.--31. 1. "CLSTR0_CORE0_BOOTVECT_LO_VECT_ADDR,Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]. Note bits 6:0 of the Vector Table address are always 0." line.long 0x4 "CFG0_CLSTR0_CORE0_BOOTVECT_HI," hexmask.long.word 0x4 0.--15. 1. "CLSTR0_CORE0_BOOTVECT_HI_VECT_ADDR,Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]." rgroup.long 0x120++0x3 line.long 0x0 "CFG0_CLSTR0_CORE0_PMCTRL," bitfld.long 0x0 0. "CLSTR0_CORE0_PMCTRL_CORE_HALT,Halt Core0" "0,1" rgroup.long 0x130++0x3 line.long 0x0 "CFG0_CLSTR0_CORE0_PMSTAT," bitfld.long 0x0 3. "CLSTR0_CORE0_PMSTAT_CLK_GATE,Core0 Clocked stopped due to WFI or WFE state" "0,1" bitfld.long 0x0 1. "CLSTR0_CORE0_PMSTAT_WFE,Core0 WFE" "0,1" newline bitfld.long 0x0 0. "CLSTR0_CORE0_PMSTAT_WFI,Core0 WFI" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "CFG0_CLSTR0_CORE1_CFG," bitfld.long 0x0 15. "CLSTR0_CORE1_CFG_NMFI_EN,Enable Core1 Non-Maskable Fast Interrupts" "0,1" bitfld.long 0x0 11. "CLSTR0_CORE1_CFG_TCM_RSTBASE,Core1 A/BTCM Reset Base Address Indicator" "0,1" newline bitfld.long 0x0 7. "CLSTR0_CORE1_CFG_BTCM_EN,Enable Core1 BTCM RAM at reset" "0,1" bitfld.long 0x0 3. "CLSTR0_CORE1_CFG_ATCM_EN,Enable Core1 ATCM RAM at reset" "0,1" rgroup.long 0x190++0x7 line.long 0x0 "CFG0_CLSTR0_CORE1_BOOTVECT_LO," hexmask.long 0x0 7.--31. 1. "CLSTR0_CORE1_BOOTVECT_LO_VECT_ADDR,Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]. Note bits 6:0 of the Vector Table address are always 0." line.long 0x4 "CFG0_CLSTR0_CORE1_BOOTVECT_HI," hexmask.long.word 0x4 0.--15. 1. "CLSTR0_CORE1_BOOTVECT_HI_VECT_ADDR,Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]." rgroup.long 0x1A0++0x3 line.long 0x0 "CFG0_CLSTR0_CORE1_PMCTRL," bitfld.long 0x0 0. "CLSTR0_CORE1_PMCTRL_CORE_HALT,Halt Core1" "0,1" rgroup.long 0x1B0++0x3 line.long 0x0 "CFG0_CLSTR0_CORE1_PMSTAT," bitfld.long 0x0 3. "CLSTR0_CORE1_PMSTAT_CLK_GATE,Core1 Clocked stopped due to WFI or WFE state" "0,1" bitfld.long 0x0 1. "CLSTR0_CORE1_PMSTAT_WFE,Core1 WFE" "0,1" newline bitfld.long 0x0 0. "CLSTR0_CORE1_PMSTAT_WFI,Core1 WFI" "0,1" tree.end tree "MCU_SEC_MMR0_DBG_CTRL (MCU_SEC_MMR0_DBG_CTRL)" base ad:0x45950000 rgroup.long 0x0++0x3 line.long 0x0 "CFG2_CLSTR0_CORE0_DBG_CFG," hexmask.long.byte 0x0 12.--15. 1. "CLSTR0_CORE0_DBG_CFG_DBGEN,Core0 Invasive debug enable." hexmask.long.byte 0x0 8.--11. 1. "CLSTR0_CORE0_DBG_CFG_NIDEN,Core0 Non-invasive debug enable." rgroup.long 0x40++0x3 line.long 0x0 "CFG2_CLSTR0_CORE1_DBG_CFG," hexmask.long.byte 0x0 12.--15. 1. "CLSTR0_CORE1_DBG_CFG_DBGEN,Core1 Invasive debug enable." hexmask.long.byte 0x0 8.--11. 1. "CLSTR0_CORE1_DBG_CFG_NIDEN,Core1 Non-invasive debug enable." tree.end tree.end tree "MCU_TIMEOUT" tree "MCU_TIMEOUT_64B2_CFG (MCU_TIMEOUT_64B2_CFG)" base ad:0x40730000 rgroup.long 0x0++0xB line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end tree "MCU_TIMEOUT_64B3_CFG (MCU_TIMEOUT_64B3_CFG)" base ad:0x40736000 rgroup.long 0x0++0xB line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end tree "MCU_TIMEOUT_64B4_CFG (MCU_TIMEOUT_64B4_CFG)" base ad:0x40737000 rgroup.long 0x0++0xB line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end tree.end tree "MCU_vdc" tree "MCU_vdc_infra_vbusp_32b_src_safeg0_CFG (MCU_vdc_infra_vbusp_32b_src_safeg0_CFG)" base ad:0x40731000 rgroup.long 0x0++0xB line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end tree "MCU_vdc_soc_fw_vbusp_32b_src_safeg1_CFG (MCU_vdc_soc_fw_vbusp_32b_src_safeg1_CFG)" base ad:0x40732000 rgroup.long 0x0++0xB line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end tree.end tree.end tree "MMCSD0" base ad:0x0 tree "MMCSD0_CTL_CFG (MMCSD0_CTL_CFG)" base ad:0x4F80000 rgroup.word 0x0++0xF line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_sdma_sys_addr_lo,This register contains the Lower 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10." hexmask.word 0x0 0.--15. 1. "SDMA_ADDRESS,When Host Version 4 Enable is set to 0 in the Host Control 2 register DMA uses this register as system address in only 32-bit addressing mode. Auto CMD23 cannot be used with SDMA. When Host Version 4 Enable is set to 1 SDMA uses ADMA System.." line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_sdma_sys_addr_hi,This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10." hexmask.word 0x2 0.--15. 1. "SDMA_ADDRESS,This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10." line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_block_size,This register is used to configure the number of bytes in a data block" bitfld.word 0x4 12.--14. "SDMA_BUF_SIZE,To perform long DMA transfer System Address register shall be updated at every system boundary during DMA transfer. These bits specify the size of contiguous buffer in the system memory. The DMA transfer shall wait at the every boundary.." "0,1,2,3,4,5,6,7" newline hexmask.word 0x4 0.--11. 1. "XFER_BLK_SIZE,This field specifies the block size for block data transfers for CMD17 CMD18 CMD24 CMD25 and CMD53. It can be accessed only if no transaction is executing [i.e after a transaction has stopped]. Read operations during transfer return an.." line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_block_count,This register is used to configure the number of data blocks" hexmask.word 0x6 0.--15. 1. "XFER_BLK_CNT,Host Controller Version 4.10 extends block count to 32-bit [Refer to Section 1.15].Selection of either 16-bit Block Count register or 32-bit Block Count register is defined as follows: [1] If Host Version 4 Enable in the Host Control 2.." line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_argument1_lo,This register contains Lower bits of SD Command Argument" hexmask.word 0x8 0.--15. 1. "CMD_ARG1,The SD Command Argument is specified as bit23-8 of Command-Format." line.word 0xA "SDHC_WRAP__CTL_CFG__CTLCFG_argument1_hi,This register contains higher bits of SD Command Argument" hexmask.word 0xA 0.--15. 1. "CMD_ARG1,The SD Command Argument is specified as bit39-24 of Command-Format." line.word 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_transfer_mode,This register is used to control the operations of data transfers" bitfld.word 0xC 8. "RESP_INTR_DIS,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error sets this bit to 0 and waits Command Complete.." "0,1" newline bitfld.word 0xC 7. "RESP_ERR_CHK_ENA,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked.If Host Driver checks response error this bit is set to 0 and Response Interrupt.." "0,1" newline bitfld.word 0xC 6. "RESP_TYPE,When response error check is enabled this bit selects either R1 or R5 response types. Two types of response checks are supported: R1 for memory and R5 for SDIO." "0,1" newline bitfld.word 0xC 5. "MULTI_BLK_SEL,This bit enables multiple block data transfers." "0,1" newline bitfld.word 0xC 4. "DATA_XFER_DIR,This bit defines the direction of data transfers." "0,1" newline bitfld.word 0xC 2.--3. "AUTO_CMD_ENA,There are three methods to stop Multiple-block read and write operation. [1] Auto CMD12 Enable: Multiple-block read and write commands for memory require CMD12 to stop the operation. When this field is set to 01b the Host.." "0,1,2,3" newline bitfld.word 0xC 1. "BLK_CNT_ENA,This bit is used to enable the Block count register which is only relevant for multiple block transfers. When this bit is 0 the Block Count register is disabled which is useful in executing an infinite transfer." "0,1" newline bitfld.word 0xC 0. "DMA_ENA,DMA can be enabled only if DMA Support bit in the Capabilities register is set. If this bit is set to 1 a DMA operation shall begin when the HD writes to the upper byte of Command register [00Fh]." "0,1" line.word 0xE "SDHC_WRAP__CTL_CFG__CTLCFG_command,This register is used to program the Command for host controller" hexmask.word.byte 0xE 8.--13. 1. "CMD_INDEX,This bit shall be set to the command number [CMD0-63 ACMD0-63]." newline bitfld.word 0xE 6.--7. "CMD_TYPE,There are three types of special commands. Suspend Resume andAbort. These bits shall bet set to 00b for all other commands. Suspend Command: If the Suspend command succeeds the HC shall assume the SD Bus has been released and that it is.." "0,1,2,3" newline bitfld.word 0xE 5. "DATA_PRESENT,This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. If is set to 0 for the following: 1. Commands using only CMD line [ex. CMD52]. 2. Commands with no data transferbut using busy.." "0,1" newline bitfld.word 0xE 4. "CMD_INDEX_CHK_ENA,If this bit is set to 1 the HC shall check the index field in the response to see if it has the same value as the command index. If it is not it is reported as a Command Index Error. If this bit is set to 0 the Index field is not.." "0,1" newline bitfld.word 0xE 3. "CMD_CRC_CHK_ENA,If this bit is set to 1 the HC shall check the CRC field in the response. If an error is detected it is reported as a Command CRC Error. If this bit is set to 0 the CRC field is not checked." "0,1" newline bitfld.word 0xE 2. "SUB_CMD,This bit is added from Version 4.10 to distinguish a main command or sub command [Refer to Section 1.17]. When issuing a main com-mand this bit is set to 0 and when issuing a sub command this bit is set to 1. Setting of this bit is checked.." "0,1" newline bitfld.word 0xE 0.--1. "RESP_TYPE_SEL,Response Type Select." "0,1,2,3" rgroup.word 0x10++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_response,This register is used to store responses from SD Cards" hexmask.word 0x0 0.--15. 1. "CMD_RESP,R[] refers to a bit range within the response data as transmitted on the SD Bus REP[] refers to a bit range within the Response register." rgroup.long 0x20++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_data_port,This register is used to access internal buffer" hexmask.long 0x0 0.--31. 1. "BUF_RD_DATA,The Host Controller Buffer can be accessed through this 32-bit Data Port Register." rgroup.long 0x24++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_presentstate,The Host Driver can get status of the Host Controller from this 32-bit read-only register" bitfld.long 0x0 31. "UHS2_IF_DETECTION,This status indicates whether a card supports UHS-II IF. This status is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 regis-ter. UHS-II interface initialization is activated by setting SD Clock Enable in the.." "0,1" newline bitfld.long 0x0 30. "UHS2_IF_LANE_SYNC,This status indicates whether lane is synchronized in UHS-II mode. This status is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 register. On detecting UHS-II Interface [D31=1] Host Controller provides SYN.." "0,1" newline bitfld.long 0x0 29. "UHS2_DORMANT,This status indicates whether UHS-II Ianes enterDormant state. This function is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 register. On issuing GO_DORMAT_STATE com-mand Go Dormant Command [111b]; is set to Command.." "0,1" newline bitfld.long 0x0 28. "SUB_COMMAND_STS,The Command register and Response register are commonly used for main command and sub command. This status is used to distinguish which response error statuses main command or sub command indicated in the Error Interrupt Status.." "?,1: Sub Command Status 0" newline bitfld.long 0x0 27. "CMD_NOT_ISS_BY_ERR,Setting of this status indicates that a command cannot be issued due to an error except Auto CMD12 error. [Equivalent error status by Auto CMD12 error is defined as Command Not Issued By Auto CMD12 Error in the Auto CMD Error.." "?,1: Command cannot be issued 0" newline bitfld.long 0x0 24. "SDIF_CMDIN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 23. "SDIF_DAT3IN,This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[3]." "0,1" newline bitfld.long 0x0 22. "SDIF_DAT2IN,This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[2]." "0,1" newline bitfld.long 0x0 21. "SDIF_DAT1IN,This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[1]." "0,1" newline bitfld.long 0x0 20. "SDIF_DAT0IN,This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[0]." "0,1" newline bitfld.long 0x0 19. "WRITE_PROTECT,The Write Protect Switch is supported for memory and combo cards.This bit reflects the SDWP# pin." "0,1" newline bitfld.long 0x0 18. "CARD_DETECT,This bit reflects the inverse value of the SDCD# pin. '0' No Card present [SDCD# = 1] '1' Card present [SDCD# = 0]" "0,1" newline bitfld.long 0x0 17. "CARD_STATE_STABLE,This bit is used for testing. If it is 0 the Card Detect Pin Level is not stable. If this bit is set to 1 it means the Card Detect Pin Level is stable. The Software Reset For All in the Software Reset Register shall not affect this.." "0,1" newline bitfld.long 0x0 16. "CARD_INSERTED,This bit indicates whether a card has been inserted. Changing from 0 to 1 generates a Card Insertion interrupt in the Normal Interrupt Status register and changing from 1 to 0 generates a Card Removal Interrupt in the Normal Interrupt.." "0,1" newline bitfld.long 0x0 11. "BUF_RD_ENA,This status is used for non-DMA read transfers.This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1 readable data exists in the buffer. A change of this bit from 1 to 0 occurs when all the.." "0,1" newline bitfld.long 0x0 10. "BUF_WR_ENA,This status is used for non-DMA write transfers.This read only flag indicates if space is available for write data. If this bit is 1 data can be written to the buffer. A change of this bit from 1 to 0 occurs when all the block data is written.." "0,1" newline bitfld.long 0x0 9. "RD_XFER_ACTIVE,This status is used for detecting completion of a read transfer. This bit is set to 1 for either of the following conditions: After the end bit of the read command. When writing a 1 to continue Request in the Block.." "0,1" newline bitfld.long 0x0 8. "WR_XFER_ACTIVE,This status indicates a write transfer is active. If this bit is 0 it means no valid write data exists in the HC. This bit is set in either of the following cases: After the end bit of the write command. When writing a.." "0,1" newline bitfld.long 0x0 7. "SDIF_DAT7IN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 6. "SDIF_DAT6IN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 5. "SDIF_DAT5IN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 4. "SDIF_DAT4IN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 3. "RETUNING_REQ,Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data. This bit is.." "0,1" newline bitfld.long 0x0 2. "DATA_LINE_ACTIVE,This bit indicates whether one of the DAT line on SD bus is in use." "0,1" newline bitfld.long 0x0 1. "INHIBIT_DAT,This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1. If this bit is 0 it indicates the HC can issue the next SD command. Commands with busy signal belong to Command Inhibit [DAT] [ex. R1b R5b.." "0,1" newline bitfld.long 0x0 0. "INHIBIT_CMD,SD Mode If this bit is 0 it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line. This bit is set immediately after the Command register [00Fh] is written. This bit is cleared when the command response is.." "?,1: Host Controller is not ready to issue a com-mand.." rgroup.byte 0x28++0x3 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_host_control1,This register is used to program DMA modes. LED Control. Data Transfer Width. High Speed Enable. Card detect test level and signal selection" bitfld.byte 0x0 7. "CD_SIG_SEL,This bit selects source for card detection. '0' SDCD# is selected [for normal use] '1' The card detect test level is selected" "0,1" newline bitfld.byte 0x0 6. "CD_TEST_LEVEL,This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. Generates [card ins or card removal] interrupt when the normal int sts enable bit is set. '0' No Card '1' Card Inserted" "0,1" newline bitfld.byte 0x0 5. "EXT_DATA_WIDTH,This bit controls 8-bit bus width mode for embedded device. Support of this function is indicated in 8-bit Support for Embedded Device in the Capabilities register. If a device supports 8-bit bus mode this bit may be set to 1. If this bit.." "0,1" newline bitfld.byte 0x0 3.--4. "DMA_SELECT,This field is used to select DMA type. The Host Driver shall check support of DMA modes by referring the Capabilities register. Selected DMA is enabled by DMA Enable of the Transfer Mode register in SD mode and DMA Enable of UHS-II Transfer.." "0: SDMA is selected 01,?,?,?" newline bitfld.byte 0x0 2. "HIGH_SPEED_ENA,This bit is optional. Before setting this bit the HD shall check the High Speed Support in the capabilities register. If this bit is set to 0 [default] the HC outputs CMD line and DAT lines at the falling edge of the SD clock [up to.." "0,1" newline bitfld.byte 0x0 1. "DATA_WIDTH,This bit selects the data width of the HC. The HD shall select it to match the data width of the SD card. This bit is not effective in UHS-II mode." "0,1" newline bitfld.byte 0x0 0. "LED_CONTROL,This bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue multiple SD commands this bit can be set during all transactions. It is not necessary to change for each.." "0,1" line.byte 0x1 "SDHC_WRAP__CTL_CFG__CTLCFG_power_control,This register is used to program the SD Bus power and voltage level" bitfld.byte 0x1 5.--7. "UHS2_VOLTAGE,This field determines supply voltage range to VDD2. This field can be set to 101b if 1.8V VDD2 Support in the Capabilities register is set to 1. '000' VDD2 Not supported '001'- '011' Reserved '100' Reserved for 1.2V.." "0,1,2,3,4,5,6,7" newline bitfld.byte 0x1 4. "UHS2_POWER,Setting this bit enables providing VDD2. '0' Power Off '1' Power On" "0,1" newline bitfld.byte 0x1 1.--3. "SD_BUS_VOLTAGE,By setting these bits the HD selects the voltage level for the SD card. Before setting this register the HD shall check the voltage support bits in the capabilities register. If an unsupported voltage is selected the Host System shall.." "0,1,2,3,4,5,6,7" newline bitfld.byte 0x1 0. "SD_BUS_POWER,Before setting this bit the SD host driver shall set SD Bus Voltage Select. If the HC detects the No Card State this bit shall be cleared. If this bit is cleared the Host Control-ler should immediately stop driving CMD and DAT[3:0].." "0,1" line.byte 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_block_gap_control,This register is used to program the block gap request. read wait control and interrupt at block gap" bitfld.byte 0x2 7. "BOOT_ACK_ENA,To check for the boot acknowledge in boot operation." "0,1" newline bitfld.byte 0x2 6. "ALT_BOOT_MODE,To start boot code access in alternative mode." "0,1" newline bitfld.byte 0x2 5. "BOOT_ENABLE,To start boot code access." "0,1" newline bitfld.byte 0x2 4. "SPI_MODE,SPI mode enable bit." "0,1" newline bitfld.byte 0x2 3. "INTRPT_AT_BLK_GAP,This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. If the SD card cannot signal an interrupt.." "0,1" newline bitfld.byte 0x2 2. "RDWAIT_CTRL,The read wait function is optional for SDIO cards. If the card supports read wait set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise the HC has to stop the SD clock to hold read data which.." "0,1" newline bitfld.byte 0x2 1. "CONTINUE,This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request. To cancel stop at the block gap set Stop At block Gap Request to 0 and set this bit to restart the transfer. The Host Controller automatically.." "0,1" newline bitfld.byte 0x2 0. "STOP_AT_BLK_GAP,This bit is used to stop executing a transaction at the next block gap for non- DMA SDMA and ADMA transfers. Until the transfer complete is set to 1 indicating a transfer completion the HD shall leave this bit set to 1. Clearing both the.." "0,1" line.byte 0x3 "SDHC_WRAP__CTL_CFG__CTLCFG_wakeup_control,This register is used to program the wakeup functionality" bitfld.byte 0x3 2. "CARD_REMOVAL,This bit enables wakeup event via Card removal assertion in the Normal Interrupt Status register.FN_WUS [Wake up Support] in CIS does not affect this bit." "0,1" newline bitfld.byte 0x3 1. "CARD_INSERTION,This bit enables wakeup event via Card Insertion assertion in the Normal Interrupt Status register.FN_WUS [Wake up Support] in CIS does not affect this bit." "0,1" newline bitfld.byte 0x3 0. "CARD_INTERRUPT,This bit enables wakeup event via Card Interrupt assertion in the Normal Interrupt Status register.This bit can be set to 1 if FN_WUS [Wake Up Support] in CIS is set to 1." "0,1" rgroup.word 0x2C++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_clock_control,This register is used to program the Clock frequency select. generator select. Clock enable. Internal Clock state fields" hexmask.word.byte 0x0 8.--15. 1. "SDCLK_FRQSEL,This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly; rather this register holds the divisor of the Base Clock Frequency For SD clock in the capabilities register. Only the following.." newline bitfld.word 0x0 6.--7. "SDCLK_FRQSEL_UPBITS,Bit 07-06 is assigned to bit 09-08 of clock divider in SDCLK Frequency Select." "0,1,2,3" newline bitfld.word 0x0 5. "CLKGEN_SEL,This bit is used to select the clock generator mode in SDCLK Frequency Select. If the Programmable Clock Mode is supported [non-zero value is set to Clock Multiplier in the Capabilities register] this bit attribute is RW and if not.." "0,1" newline bitfld.word 0x0 3. "PLL_ENA,This bit is added from Version 4.10 for Host Controller using PLL. This feature allows Host Controller to initialize clock generator in two steps: by Internal Clock Enable and PLL Enable and to minimize output latency [ex. SDCLK/RCLK D0lane].." "0,1" newline bitfld.word 0x0 2. "SD_CLK_ENA,The HC shall stop SDCLK when writing this bit to 0. SDCLK frequency Select can be changed when this bit is 0. Then the HC shall maintain the same clock frequency until SDCLK is stopped [Stop at SDCLK = 0]. If the HC detects the No Card state .." "0,1" newline rbitfld.word 0x0 1. "INT_CLK_STABLE,This bit is set to 1 when SD clock is stable after writing to Internal Clock Enable in this register to 1. The SD Host Driver shall wait to set SD Clock Enable until this bit is set to 1. Note: This is useful when using PLL for a clock.." "0,1" newline bitfld.word 0x0 0. "INT_CLK_ENA,This bit is set to 0 when the HD is not using the HC or the HC awaits a wakeup event. The HC should stop its internal clock to go very low power state. Still registers shall be able to be read and written. Clock starts to oscillate when this.." "0,1" rgroup.byte 0x2E++0x1 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_timeout_control,The register sets the Data Timeout counter value" hexmask.byte 0x0 0.--3. 1. "COUNTER_VALUE,This value determines the interval by which DAT line time-outs are detected. Refer to the Data Time-out Error in the Error Interrupt Status register for information on factors that dictate time-out generation. Time-out clock frequency will.." line.byte 0x1 "SDHC_WRAP__CTL_CFG__CTLCFG_software_reset,This register is used to program the software reset for data. command and for all" bitfld.byte 0x1 2. "SWRST_FOR_DAT,Only part of data circuit is reset. The following registers and bits are cleared by this bit: Buffer Data Port Register: Buffer is cleared and Initialized. Present State register: Buffer read Enable Buffer write.." "0,1" newline bitfld.byte 0x1 1. "SWRST_FOR_CMD,Software Reset For CMD Line Only part of command circuit is reset to be able to issue a command. From Version 4.10 this bit is also used to initialize UHS-II command circuit. This reset is effective only command issuing circuit [including.." "0,1" newline bitfld.byte 0x1 0. "SWRST_FOR_ALL,This reset affects the entire HC except for the card detection circuit. Register bits of type ROC RW RW1C RWAC are cleared to 0. During its initialization the HD shall set this bit to 1 to reset the HC. The HC shall reset this bit to 0.." "0,1" rgroup.word 0x30++0xB line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sts,This register gives the status of all the interrupts" rbitfld.word 0x0 15. "ERROR_INTR,If any of the bits in the Error Interrupt Status Register are set then this bit is set. Therefore the HD can test for an error by checking this bit first. In UHS-II mode is enabled if any of the bits in the UHS-II Error.." "0,1" newline bitfld.word 0x0 14. "BOOT_COMPLETE,This status is set if the boot operation gets terminated. '0' Boot operation is not terminated '1' Boot operation is terminated" "0,1" newline bitfld.word 0x0 13. "RCV_BOOT_ACK,This status is set if the boot acknowledge is received from device. '0' Boot ack not recieved '1' Boot ack is recieved" "0,1" newline rbitfld.word 0x0 12. "RETUNING_EVENT,This status is set if Re-Tuning Request in the Present State register changes from 0 to 1. Host Controller requests Host Driver to perform re-tuning for next data transfer. Current data transfer [not large block count] can be completed.." "0,1" newline rbitfld.word 0x0 11. "INTC,This status is set if INT_C is enabled and INT_C# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_C interrupt factor." "0,1" newline rbitfld.word 0x0 10. "INTB,This status is set if INT_B is enabled and INT_B# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_B interrupt factor." "0,1" newline rbitfld.word 0x0 9. "INTA,This status is set if INT_A is enabled and INT_A# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_A interrupt factor. NOTE : INT_A INT_B and INT_C are to be implemented based on the.." "0,1" newline rbitfld.word 0x0 8. "CARD_INTR,When this status has been set and the Host Driver needs to start this interrupt service Card Interrupt Status Enable in the Normal Interrupt Status Enable register may be set to 0 in order to clear the card interrupt status latched in the Host.." "?,1: bit mode" newline bitfld.word 0x0 7. "CARD_REM,This status is set if the Card Inserted in the Present State register changes from 1 to 0. When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the card.." "0,1" newline bitfld.word 0x0 6. "CARD_INS,This status is set if the Card Inserted in the Present State register changes from 0 to 1.When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the card.." "0,1" newline bitfld.word 0x0 5. "BUF_RD_READY,This status is set if the Buffer Read Enable changes from 0 to 1. Buffer Read Ready is set to 1 for every CMD19 execution in tuning procedure.In UHS-II mode this bit is set at FC [Flow Control] unit basis. '0' Not ready to.." "0,1" newline bitfld.word 0x0 4. "BUF_WR_READY,This status is set if the Buffer Write Enable changes from 0 to 1.In UHS-II mode this bit is set at FC [Flow Control] unit basis. '0' Not ready to write to buffer '1' Ready to write to buffer" "0,1" newline bitfld.word 0x0 3. "DMA_INTERRUPT,This status is set if the HC detects the Host DMA Buffer Boundary in the Block Size regiser. '0' No DMA Interrupt '1' DMA Interrupt is generated" "0,1" newline bitfld.word 0x0 2. "BLK_GAP_EVENT,If the Stop At Block Gap Request in the BlockGap Control Register is set this bit is set. Read Transaction: This bit is set at the falling edge of the DAT Line Active Status [When the transaction is stopped at SD Bus timing. The Read.." "0,1" newline bitfld.word 0x0 1. "XFER_COMPLETE,This bit is set when a read / write transaction is completed. SD Mode Read Transaction: This bit is set at the falling edge of Read Transfer Active Status. There are two cases in which the Interrupt is generated. The first is.." "?,1: Command execution is completed 0" newline bitfld.word 0x0 0. "CMD_COMPLETE,SD Mode This bit is set when we get the end bit of the command response [Except Auto CMD12 and Auto CMD23] Note: Command Time-out Error has higher priority than Command Complete. If both are set to 1 it can be considered that the.." "0,1" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sts,This register gives the status of the error interrupts" bitfld.word 0x2 12. "HOST,Occurs when detecting ERROR in m_hresp[dma transaction]" "0,1" newline bitfld.word 0x2 11. "RESP,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to 1 in the Transfer Mode register Host Controller Checks R1 or.." "0,1" newline bitfld.word 0x2 10. "TUNING,This bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure [Occurrence of an error during tuning procedure is indicated by Sampling Select]. By detecting Tuning Error Host Driver needs to abort a.." "0,1" newline bitfld.word 0x2 9. "ADMA,This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register." "0,1" newline bitfld.word 0x2 8. "AUTO_CMD,Auto CMD12 and Auto CMD23 use this error status.This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. D07 is effective in case of Auto CMD12. Auto CMD Error Status register is.." "0,1" newline bitfld.word 0x2 7. "CURR_LIMIT,By setting the SD Bus Power bit in the Power Control Register the HC is requested to supply power for the SD Bus. If the HC supports the Current Limit Function it can be protected from an Illegal card by stopping power supply to the card in.." "0,1" newline bitfld.word 0x2 6. "DATA_ENDBIT,Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status." "0,1" newline bitfld.word 0x2 5. "DATA_CRC,Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than 010." "0,1" newline bitfld.word 0x2 4. "DATA_TIMEOUT,Occurs when detecting one of following timeout conditions: 1. Busy Timeout for R1b R5b type. 2. Busy Timeout after Write CRC status 3. Write CRC status Timeout 4. Read Data Timeout." "0,1" newline bitfld.word 0x2 3. "CMD_INDEX,Occurs if a Command Index error occurs in the Command Response." "0,1" newline bitfld.word 0x2 2. "CMD_ENDBIT,Occurs when detecting that the end bit of a command response is 0." "0,1" newline bitfld.word 0x2 1. "CMD_CRC,Command CRC Error is generated in two cases. 1. If a response is returned and the Command Time-out Error is set to 0 this bit is set to 1 when detecting a CRT error in the command response 2. The HC detects a CMD line conflict by.." "0,1" newline bitfld.word 0x2 0. "CMD_TIMEOUT,Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command. If the HC detects a CMD line conflict in which case Command CRC Error shall also be set. This bit shall be set without waiting for 64 SDCLK.." "0,1" line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sts_ena,This register is used to enable the normal interrupt status register fields" rbitfld.word 0x4 15. "BIT15_FIXED0,The HC shall control error Interrupts using the Error Interrupt Status Enable register." "0,1" newline bitfld.word 0x4 14. "BOOT_COMPLETE,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 13. "RCV_BOOT_ACK,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 12. "RETUNING_EVENT,0 - Masked 1 - Enabled" "0: Masked 1,?" newline bitfld.word 0x4 11. "INTC,If this bit is set to 0 the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to INT_C pin are cleared to prevent.." "0,1" newline bitfld.word 0x4 10. "INTB,If this bit is set to 0 the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to INT_B pin are cleared to prevent.." "0,1" newline bitfld.word 0x4 9. "INTA,If this bit is set to 0 the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to INT_A pin are cleared to prevent.." "0,1" newline bitfld.word 0x4 8. "CARD_INTERRUPT,If this bit is set to 0 the HC shall clear Interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. The HD may clear the Card Interrupt Status Enable before.." "0,1" newline bitfld.word 0x4 7. "CARD_REMOVAL,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 6. "CARD_INSERTION,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 5. "BUF_RD_READY,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 4. "BUF_WR_READY,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 3. "DMA_INTERRUPT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 2. "BLK_GAP_EVENT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 1. "XFER_COMPLETE,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 0. "CMD_COMPLETE,'0' Masked '1' Enabled" "0,1" line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sts_ena,This register is used to enable the Error Interrupt Status register fields" bitfld.word 0x6 13.--14. "VENDOR_SPECIFIC,N/A" "0,1,2,3" newline bitfld.word 0x6 12. "HOST,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 11. "RESP,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 10. "TUNING,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 9. "ADMA,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 8. "AUTO_CMD,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 7. "CURR_LIMIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 6. "DATA_ENDBIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 5. "DATA_CRC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 4. "DATA_TIMEOUT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 3. "CMD_INDEX,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 2. "CMD_ENDBIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 1. "CMD_CRC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 0. "CMD_TIMEOUT,'0' Masked '1' Enabled" "0,1" line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sig_ena,This register is used to enable the Normal Interrupt Signal register" rbitfld.word 0x8 15. "BIT15_FIXED0,The HD shall control error Interrupts using the Error Interrupt Signal Enable register." "0,1" newline bitfld.word 0x8 14. "BOOT_COMPLETE,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 13. "RCV_BOOT_ACK,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 12. "RETUNING_EVENT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 11. "INTC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 10. "INTB,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 9. "INTA,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 8. "CARD_INTERRUPT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 7. "CARD_REMOVAL,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 6. "CARD_INSERTION,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 5. "BUF_RD_READY,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 4. "BUF_WR_READY,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 3. "DMA_INTERRUPT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 2. "BLK_GAP_EVENT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 1. "XFER_COMPLETE,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 0. "CMD_COMPLETE,'0' Masked '1' Enabled" "0,1" line.word 0xA "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sig_ena,This register is used to enable Error Interrupt Signal register" bitfld.word 0xA 13.--14. "VENDOR_SPECIFIC,N/A" "0,1,2,3" newline bitfld.word 0xA 12. "HOST,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 11. "RESP,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 10. "TUNING,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 9. "ADMA,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 8. "AUTO_CMD,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 7. "CURR_LIMIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 6. "DATA_ENDBIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 5. "DATA_CRC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 4. "DATA_TIMEOUT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 3. "CMD_INDEX,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 2. "CMD_ENDBIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 1. "CMD_CRC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 0. "CMD_TIMEOUT,'0' Masked '1' Enabled" "0,1" rgroup.word 0x3C++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_autocmd_err_sts,This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD 23" bitfld.word 0x0 7. "CMD_NOT_ISSUED,Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 error [D04- D01] in this register. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23." "0,1" newline bitfld.word 0x0 5. "RESP,This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or Auto CMD23. This status should be ignored if any bit of D00 to D04 is set to 1." "0,1" newline bitfld.word 0x0 4. "INDEX,Occurs if the Command Index error occurs in response to a command." "0,1" newline bitfld.word 0x0 3. "ENDBIT,Occurs when detecting that the end bit of command response is 0." "0,1" newline bitfld.word 0x0 2. "CRC,Occurs when detecting a CRC error in the command response." "0,1" newline bitfld.word 0x0 1. "TIMEOUT,Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command.If this bit is set to 1 the other error status bits [D04 - D02] are meaningless." "0,1" newline bitfld.word 0x0 0. "ACMD12_NOT_EXEC,If memory multiple block data transfer is not started due to command error this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the HC cannot issue Auto CMD12 to stop memory multiple block.." "0,1" rgroup.word 0x3E++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_host_control2,This register is used to program UHS Select Mode.UHS Select Mode.Driver Strength Select.Execute Tuning.Sampling Clock Select.Asynchronous Interrupt Enable and Preset value enable" bitfld.word 0x0 15. "PRESET_VALUE_ENA,Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation it is difficult to determine these parameters in the Standard Host Driver. When Preset.." "0,1" newline bitfld.word 0x0 14. "ASYNCH_INTR_ENA,This bit can be set to 1 if a card support asynchronous interrupt and Asynchronous Interrupt Support is set to 1 in the Capabilities register. Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode [and zero is.." "0,1" newline bitfld.word 0x0 13. "BIT64_ADDRESSING,This field is effective when Host Version 4.00 Enable is set to 1. Host Controller selects either of 32-bit or 64-bit addressing modes to access system memory. Whether 32-bit or 64-bit is determined by OS installed in a host.." "0,1" newline bitfld.word 0x0 12. "HOST_VER40_ENA,This bit selects either Version 3.00 compatible mode or Ver4.mode. In Version 4.00 support of 64-bit System Addressing is modified. All DMAs support 64-bit System Addressing. UHS-II supported Host Driver shall enable this bit. In Version.." "0,1" newline bitfld.word 0x0 11. "CMD23_ENA,In memory card initialization Host Driver Version 4.10 checks whether card supports CMD23 by checking a bit SCR[33]. If the card supports CMD23 [SCR[33]=1] this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3.." "0,1" newline bitfld.word 0x0 10. "ADMA2_LEN_MODE,This bit selects one of ADMA2 Length Modes either 16-bit or 26-bit." "0,1" newline bitfld.word 0x0 9. "DRIVER_STRENGTH2,This is the programmed Drive STrength output and Bit[2] of the sdhccore_drivestrength value." "0,1" newline bitfld.word 0x0 8. "UHS2_INTF_ENABLE,This bit is used to enable UHS-II Interface. Before trying to start UHS-II initialization this bit shall be set to 1. Before trying to start SD mode initialization this bit shall be set to 0. This bit is used to enable UHS-II IF.." "0,1" newline bitfld.word 0x0 7. "SAMPLING_CLK_SELECT,This bit is set by tuning procedure when Execute Tuning is cleared. Writing 1 to this bit is meaningless and ignored. Setting 1 means that tuning is completed successfully and setting 0 means that tuning is failed. Host Controller.." "0,1" newline bitfld.word 0x0 6. "EXECUTE_TUNING,This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to Sampling Clock Select. Tuning procedure is aborted by writing 0 for more detail about tuning.." "0,1" newline bitfld.word 0x0 4.--5. "DRIVER_STRENGTH1,Host Controller output driver in 1.8V signaling is selected by this bit. In 3.3V signaling this field is not effective. This field can be set depends on Driver Type A C and D support bits in the Capabilities register. This bit depends.." "0,1,2,3" newline bitfld.word 0x0 3. "V1P8_SIGNAL_ENA,This bit controls voltage regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V. 1.8V regulator output shall be stable within.." "?,1: SDR50" newline bitfld.word 0x0 0.--2. "UHS_MODE_SELECT,This field is used to select one of UHS-I modes or UHS-II mode.In case of UHS-I mode this field is effective when 1.8V Signal-ing Enable is set to 1. In case of UHS-II mode 1.8V Signaling Enable shall be set to 0. Setting of this field.." "0,1,2,3,4,5,6,7" rgroup.quad 0x40++0xF line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_capabilities,This register provides the HD with information specific to the HC implementation. The HC may implement these values as fixed or loaded from flash memory during power on initializa-tion." bitfld.quad 0x0 63. "HS400_SUPPORT,1 HS400 is Supported 0 HS400 is Not Supported" "0,1" newline bitfld.quad 0x0 60. "VDD2_1P8_SUPPORT,This field indicates that support of VDD2 on Host system." "0,1" newline bitfld.quad 0x0 59. "ADMA3_SUPPORT,This field indicates that support of ADMA3 on Host Controller." "0,1" newline bitfld.quad 0x0 57. "SPI_BLK_MODE,This field indicates whether SPI Block Mode is supported or not." "0,1" newline bitfld.quad 0x0 56. "SPI_SUPPORT,This field indicates whether SPI Mode is supported or not." "0,1" newline hexmask.quad.byte 0x0 48.--55. 1. "CLOCK_MULTIPLIER,This field indicates clock multiplier value of programmable clock generator. Refer to Clock Control register. Setting 00h means that Host Controller does not support programmable clock generator. 'FF' Clock Multiplier M = 256.." newline bitfld.quad 0x0 46.--47. "RETUNING_MODES,This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver. '00' Mode 1 '01' Mode 2 '10' Mode 3 '11' Reserved. There are two.." "0,1,2,3" newline bitfld.quad 0x0 45. "TUNING_FOR_SDR50,If this bit is set to 1 this Host Controller requires tuning to operate SDR50. [Tuning is always required to operate SDR104]. '0' '1'" "0,1" newline hexmask.quad.byte 0x0 40.--43. 1. "RETUNING_TIMER_CNT,This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. 0h - Get information via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds ------.." newline bitfld.quad 0x0 38. "DRIVERD_SUPPORT,This bit indicates support of Driver Type D for 1.8 Signaling. '0' Driver Type D is Not supported '1' Driver Type D is supported" "0,1" newline bitfld.quad 0x0 37. "DRIVERC_SUPPORT,This bit indicates support of Driver Type C for 1.8 Signaling. '0' Driver Type C is Not supported '1' Driver Type C is supported" "0,1" newline bitfld.quad 0x0 36. "DRIVERA_SUPPORT,This bit indicates support of Driver Type A for 1.8 Signaling. '0' Driver Type A is Not supported '1' Driver Type A is supported" "0,1" newline bitfld.quad 0x0 35. "UHS2_SUPPORT,This bit indicates whether Host controller supports UHS-II. If this bit is set to 1 1.8V VDD2 Support shall be set to 1 [Host Sys- tem shall support VDD2 power supply]. 1 UHS-II is Supported 0 UHS-II is Not Supported" "0,1" newline bitfld.quad 0x0 34. "DDR50_SUPPORT,This bit indicates whether DDR50 is supported or not." "0,1" newline bitfld.quad 0x0 33. "SDR104_SUPPORT,This bit indicates whether SDR104 is supported or not.SDR104 requires tuning." "0,1" newline bitfld.quad 0x0 32. "SDR50_SUPPORT,If SDR104 is supported this bit shall be set to 1. Bit 40 indicates whether SDR50 requires tuning or not." "0,1" newline bitfld.quad 0x0 30.--31. "SLOT_TYPE,This field indicates usage of a slot by a specific Host System. [A host controller register set is defined perslot.] Embedded slot for one device [01b] means that only one non-removable device is connected to a SD bus slot. Shared Bus Slot.." "0,1,2,3" newline bitfld.quad 0x0 29. "ASYNCH_INTR_SUPPORT,Refer to SDIO Specification Version 3.00 about asynchronous interrupt." "0,1" newline bitfld.quad 0x0 28. "ADDR_64BIT_SUPPORT_V3,IMeaning of this bit is different depends on Versions [Refer to Table 2-35 for more details]. Host Controller Version 3.00 and Ver4.10 use this bit as 64-bit System Address support for V3 mode. Host Con- troller Version 4.00 uses.." "0,1" newline bitfld.quad 0x0 27. "ADDR_64BIT_SUPPORT_V4,This bit is added from Version 4.10. Set-ting 1 to this bit indicates that the Host Controller supports 64-bit System Addressing of Version 4 mode [Refer to Table 2-35 for the summary of 64-bit sys-tem address support].. When.." "0,1" newline bitfld.quad 0x0 26. "VOLT_1P8_SUPPORT,This bit indicates whether the HC supports 1.8V." "0,1" newline bitfld.quad 0x0 25. "VOLT_3P0_SUPPORT,This bit indicates whether the HC supports 3.0V." "0,1" newline bitfld.quad 0x0 24. "VOLT_3P3_SUPPORT,This bit indicates whether the HC supports 3.3V." "0,1" newline bitfld.quad 0x0 23. "SUSP_RES_SUPPORT,This bit indicates whether the HC supports Suspend / Resume functionality. If this bit is 0 the Suspend and Resume mechanism are not supported and the HD shall not issue either Suspend / Resume commands." "0,1" newline bitfld.quad 0x0 22. "SDMA_SUPPORT,This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly.Version 4.10 Host Controller shall support SDMA if ADMA2 is supported." "0,1" newline bitfld.quad 0x0 21. "HIGH_SPEED_SUPPORT,This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25Mhz to 50 Mhz [for SD]/ 20MHz to 52MHz [for MMC]." "0,1" newline bitfld.quad 0x0 19. "ADMA2_SUPPORT,'0' ADMA2 Not Supported '1' ADMA2 Supported" "0,1" newline bitfld.quad 0x0 18. "BUS_8BIT_SUPPORT,This bit indicates whether the Host Controller is capable of using 8-bit bus width mode. This bit is not effective when Slot Type is set to 10b. In this case refer to Bus Width Preset in the Shared Bus resister." "0,1" newline bitfld.quad 0x0 16.--17. "MAX_BLK_LENGTH,This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall transfer this block size without wait cycles. Three sizes can be defined as indicated below." "0,1,2,3" newline hexmask.quad.byte 0x0 8.--15. 1. "BASE_CLK_FREQ,[1]6-bit Base Clock Frequency: This mode is supported by the Host Controller Version 1.00 and 2.00. Upper 2-bit is not effective and always 0. Unit values are 1MHz. The supported clock range is 10MHz to 63MHz. '11xx xxxxb' Not.." newline bitfld.quad 0x0 7. "TIMEOUT_CLK_UNIT,This bit shows the unit of base clock frequency used to detect Data Timeout Error." "0,1" newline hexmask.quad.byte 0x0 0.--5. 1. "TIMEOUT_CLK_FREQ,This bit shows the base clock frequency used to detect Data Timeout Error. '000000' Get Information via another method 'not 0' 1KHz to 63KHz/1MHz to 63MHz" line.quad 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_max_current_cap,This register indicates maximum current capability for each voltage" hexmask.quad.byte 0x8 32.--39. 1. "VDD2_1P8V,Maximum Current for 1.8V VDD2" newline hexmask.quad.byte 0x8 16.--23. 1. "VDD1_1P8V,Maximum Current for 1.8V VDD1" newline hexmask.quad.byte 0x8 8.--15. 1. "VDD1_3P0V,Maximum Current for 3.0V VDD1" newline hexmask.quad.byte 0x8 0.--7. 1. "VDD1_3P3V,Maximum Current for 3.3V VDD1" rgroup.word 0x50++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_force_evnt_ACMD_Err_Sts,This register is not physically implemented. rather it is an address where Auto CMD Error Status register can be written." bitfld.word 0x0 7. "CMD_NOT_ISS,Force Event for Command Not Issued by AUTO CMD12 Error." "0,1" newline bitfld.word 0x0 5. "RESP,Force Event for AUTO CMD Response Error.." "0,1" newline bitfld.word 0x0 4. "INDEX,Force Event for AUTO CMD Index Error.." "0,1" newline bitfld.word 0x0 3. "ENDBIT,Force Event for AUTO CMD End Bit Error." "0,1" newline bitfld.word 0x0 2. "CRC,Force Event for AUTO CMD Timeout Error." "0,1" newline bitfld.word 0x0 1. "TIMEOUT,Force Event for AUTO CMD Timeout Error." "0,1" newline bitfld.word 0x0 0. "ACMD_NOT_EXEC,Force Event for AUTO CMD12 Not Executed." "0,1" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_force_evnt_Err_Int_Sts,This register is not physically implemented. rather it is an address where Error Interrupt Status register can be written." bitfld.word 0x2 12. "HOST,Force Event for Host Error" "0,1" newline bitfld.word 0x2 11. "RESP,Force Event for Response Error" "0,1" newline bitfld.word 0x2 10. "TUNING,Force Event for Tuning Error." "0,1" newline bitfld.word 0x2 9. "ADMA,Force Event for ADMA Error." "0,1" newline bitfld.word 0x2 8. "AUTO_CMD,Force Event for Auto CMD Error." "0,1" newline bitfld.word 0x2 7. "CURR_LIM,Force Event for Current Limit Error." "0,1" newline bitfld.word 0x2 6. "DAT_ENDBIT,Force Event for Data End Bit Error." "0,1" newline bitfld.word 0x2 5. "DAT_CRC,Force Event for Data CRC Error." "0,1" newline bitfld.word 0x2 4. "DAT_TIMEOUT,Force Event for Data Timeout Error." "0,1" newline bitfld.word 0x2 3. "CMD_INDEX,Force Event for Command Index Error" "0,1" newline bitfld.word 0x2 2. "CMD_ENDBIT,Force Event for Command End Bit Error." "0,1" newline bitfld.word 0x2 1. "CMD_CRC,Force Event for Command CRC Error." "0,1" newline bitfld.word 0x2 0. "CMD_TIMEOUT,Force Event for CMD Timeout Error." "0,1" rgroup.byte 0x54++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_adma_err_status,When the ADMA Error interrupt occur. this register holds the ADMA State in ADMA Error States field and ADMA System Address holds address around the error descriptor" bitfld.byte 0x0 2. "ADMA_LENGTH_ERR,This error occurs in the following 2 cases. While Block Count Enable being set the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length. Total data length can not be.." "0,1" newline bitfld.byte 0x0 0.--1. "ADMA_ERR_STATE,This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates 10 because ADMA never stops in this state. D01 D00 : ADMA Error State when error occurred Contents of SYS_SDR.." "0: ADMA Error State when error occurred Contents of..,?,?,?" rgroup.quad 0x58++0x7 line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_adma_sys_address,This register contains the physical address used for ADMA data transfer" hexmask.quad 0x0 0.--63. 1. "ADMA_ADDR,The 32-bit addressing Host Driver uses lower 32-bit of this register [upper 32-bit should be set to 0] and shall program Descriptor Table on 32-bit boundary andset 32-bit boundary address to this register. DMA2/3 ignores lower 2-bit of this.." rgroup.word 0x60++0xF line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value0,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x0 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x0 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x0 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value1,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x2 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x2 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x2 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value2,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x4 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x4 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x4 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value3,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x6 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x6 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x6 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value4,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x8 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x8 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x8 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0xA "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value5,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0xA 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0xA 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0xA 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value6,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0xC 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0xC 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0xC 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0xE "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value7,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0xE 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0xE 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0xE 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." rgroup.word 0x72++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value8,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x0 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x0 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x0 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value10,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x2 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x2 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x2 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." rgroup.quad 0x78++0x7 line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_adma3_desc_address,The start address of Integrated DMA Descriptor is set to this register." hexmask.quad 0x0 0.--63. 1. "INTG_DESC_ADDR,The start address of Integrated DMA Descriptor is set to this register. Writing to a specific address starts ADMA3 depends on 32-bit/64-bit address-ing. The ADMA3 fetches one Descriptor Address and increments this field to indicate the.." rgroup.word 0x80++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_block_size,This register is used to configure the number of bytes in a data block" bitfld.word 0x0 12.--14. "SDMA_BUF_BOUNDARY,When system memory is managed by paging SDMA data transfer is performed in unit of paging. A page size of sys-tem memory management is set to this field. Host Controller generates the DMA Interrupt at the page boundary and.." "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--11. 1. "XFER_BLK_SIZE,This register specifies the block size of data packet. SD Memory Card uses a fixed block size of 512 bytes. Vari-able block size may be used for SDIO. The maximum value is 2048 Bytes because CRC16 covers up to 2048 bytes. This register is.." rgroup.long 0x84++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_block_count,This register is used to configure the number of data blocks" hexmask.long 0x0 0.--31. 1. "XFER_BLK_COUNT,This register is effective when Data Present is set to 1 in UHS-II Command register and is enabled when Block Count Enable is set to 1 and Block / Byte Mode is set to 0 in the UHS-II Transfer Mode register. Data transfer stops when the.." rgroup.byte 0x88++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_command_pkt,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes. The command length varies depends on a Command Packet type. The length is specified by the UHS-II Command register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,UHS-II Command Packet image is set to this register.The command length varies depends on a Command Packet type." rgroup.word 0x9C++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_xfer_mode,This register is used to control the operations of data transfers" bitfld.word 0x0 15. "DUPLEX_SELECT,Use of 2 lane half duplex mode is determined by Host Driver." "0,1" newline bitfld.word 0x0 14. "EBSY_WAIT,This bit is set when issuing a command which is accompanied by EBSY packet to indicate end of command execution. Busy is expected for CCMD with R1b/R5b type and DCMD with data transfer.If this bit is set to 1 Host Controller waits receiving of.." "0,1" newline bitfld.word 0x0 8. "RESP_INTR_DIS,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error sets this bit to 0 and waits Command.." "0,1" newline bitfld.word 0x0 7. "RESP_ERR_CHK_ENA,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver.Only R1 or R5 can be checked. If Host Driver checks response error this bit is set to 0 and Response.." "0,1" newline bitfld.word 0x0 6. "RESP_TYPE,When response error check is enabled this bit selects either R1 or R5 response types. Two types of response checks are supported: R1 for memory and R5 for SDIO. Error Statuses Checked in R1 Bit31 OUT_OF_RANGE.." "0,1" newline bitfld.word 0x0 5. "BYTE_MODE,This bit specifies whether data transfer is in byte mode or block mode when Data Present is set to 1. This bit is effective to a command with data trans-fer." "0,1" newline bitfld.word 0x0 4. "DATA_XFER_DIR,This bit specifies direction of data trans-fer when Data Present is set to 1. This bit is effective to a command with data transfer. 0 - Read [Card to Host] 1 - Write [Host to Card]" "0: Read [Card to Host] 1,?" newline bitfld.word 0x0 1. "BLK_CNT_ENA,This bit specifies whether data transfer usesUHS-II Block Count register. If this bit is set to 1 data transfer is terminated by Block Count. Setting to UHS-II Block Count register shall be equivalent to TLEN in UHS-II Command Packet.." "0,1" newline bitfld.word 0x0 0. "DMA_ENA,This bit selects whether DMA is used or not and is effective to a command with data transfer. One of DMA types is selected by DMA Select in the Host Control 1 register." "0,1" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_command,This register is used to program the Command for host controller" hexmask.word.byte 0x2 8.--12. 1. "PKT_LENGTH,A command packet length which is set in the UHS-II Command Packet register is set to this register. 00011b - 00000b - 3-0 Bytes [Not used] 00100b - 4 Bytes .......... ...... 10100b - 20 Bytes.." newline bitfld.word 0x2 6.--7. "CMD_TYPE,This field is used to distinguish a spe-cific command like abort command. If this field is set to 00b the UHS-II RES Packet is stored in UHS-II Response register [0B3h-0A0h]. To avoid overwrit-ing the UHS-II Response register when this filed.." "0,1,2,3" newline bitfld.word 0x2 5. "DATA_PRESENT,This bit specifies whether the command is accompanied by data packet." "0,1" newline bitfld.word 0x2 2. "SUB_COMMAND,This bit is added from Version 4.10 to distinguish a main command or sub command [Refer to Section 1.17].When issuing a main command this bit is set to 0 and when issuing a sub com-mand this bit is set to 1. Setting of this bit is checked.." "0,1" rgroup.byte 0xA0++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_response,This register is used to store received UHS-II RES Packet image" hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." rgroup.byte 0xB4++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_message_select,This register is used to access internal buffer" bitfld.byte 0x0 0.--1. "MSG_SEL,Host Controller holds 4 MSG packets in FIFO buffer.One of 4 MSGs can be read from the UHS-II MSG register [0BB-0B8h] by setting this register.[Assumed for debug usage.] '00' The latest MSG '01' One MSG before '10' Two MSGs.." "0,1,2,3" rgroup.long 0xB8++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_message,This register is used to access internal buffer" hexmask.long.byte 0x0 24.--31. 1. "MSG_BYTE3,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.." newline hexmask.long.byte 0x0 16.--23. 1. "MSG_BYTE2,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.." newline hexmask.long.byte 0x0 8.--15. 1. "MSG_BYTE1,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.." newline hexmask.long.byte 0x0 0.--7. 1. "MSG_BYTE0,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.." rgroup.word 0xBC++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_intr_status,This register shows receipt of INT MSG from which device" hexmask.word 0x0 0.--15. 1. "DEV_INT_STS,This register shows receipt of INT MSG from which device and is effective when INT MSG Enable is set to 1 in the UHS- II Device Select register. On receiving INT MSG from a device Host Controller saves the INT MSG to UHS-II Device Interrupt.." rgroup.byte 0xBE++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_select,UHS-II Device Select Register" bitfld.byte 0x0 7. "INT_MSG_ENA,This bit enables receipt of INT MSG. If this bit is set to 1 receipt of INT MSG is informed by Card Interrupt in the Nor-mal Interrupt Status register. If this bit is set to 0 Host Con-troller ignores receipt of INT MSG and may not set the.." "0,1" newline hexmask.byte 0x0 0.--3. 1. "DEV_SEL,Host Controller holds an INT MSG packet per device. One of INT MSGs [up to 15] can be selected by this field and read from the UHS-II Device Interrupt Code Register [0BFh]. This field is effective when INT MSG Enable is set to 1. The.." rgroup.byte 0xBF++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_int_code,This register is effective when INT MSG Enable is set to 1 in the UHS-II Device Select register." hexmask.byte 0x0 0.--7. 1. "DEV_INTR,This register is effective when INT MSG Enable is set to 1 in the UHS-II Device Select register. Host Controller holds an INT MSG packet per device. One of INT MSGs [Code length is 1 byte] up to 15 can be read from this register by.." rgroup.word 0xC0++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_software_reset,UHS-II Software Reset Register" bitfld.word 0x0 1. "HOST_SDTRAN_RESET,Host Driver set this bit to 1 to reset SD-TRAN layer when CMD0 is issued to Device or data transfer error occurs. This bit is cleared automatically at completionof SD-TRAN reset. If CMD0 is issued SD-TRAN Initial- ization sequence from.." "0,1" newline bitfld.word 0x0 0. "HOST_FULL_RESET,On issuing FULL_RESET CCMD Host Driver set this bit to 1 to reset Host Controller. This bit is cleared auto-matically at completion of Host Controller reset. Initial- ization sequence from PHY Initialization is required to use UHS-II.." "0,1" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_timer_control,UHS-II Timeout Control Register" hexmask.word.byte 0x2 4.--7. 1. "DEADLOCK_TIMEOUT_CTR,This value determines the deadlock period while host expecting to receive a packet [1 second]. Tim-eout clock frequency will be generated by dividing the base clock TMCLK value by this value. When setting this register prevent.." newline hexmask.word.byte 0x2 0.--3. 1. "CMDRESP_TIMEOUT_CTR,This value determines the interval between com-mand packet and response packet [5ms]. Timeout clock frequency will be generated by dividing the base clock TMCLK value by this value. When set-ting this register prevent inadvertent.." rgroup.long 0xC4++0xB line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sts,This register gives the status of all UHS-II interrupts" hexmask.long.byte 0x0 27.--31. 1. "VENDOR_SPECFIC_ERR,Vendor may use this field for vendor specific error status. '0' Interrupt is not generated '1' Vendor Specific Error" newline bitfld.long 0x0 17. "DEADLOCK_TIMEOUT,Setting of this bit means that deadlock timeout occurs. Host expects to receive a packet but not received in a specified timeout [1 second]. Timeout value is determined by the setting of Timeout Counter Value for Deadlock in UHS-II Timer.." "0,1" newline bitfld.long 0x0 16. "CMD_RESP_TIMEOUT,Setting of this bit means that RES Packet timeout occurs. Host expects to receive RES packet but not received in a specified timeout [5ms]. Timeout value is determined by the setting of Timeout Counter Value for CMD_RES in UHS-II Timer.." "0,1" newline bitfld.long 0x0 15. "ADMA2_ADMA3,Setting of this bit means that ADMA2/3 Error occurs in UHS-II mode. ADMA2/3 Error Status is indicated to the ADMA Error Status [054h] which is defined in the Host spec 3.00." "0,1" newline bitfld.long 0x0 8. "EBSY,On receiving EBSY packet if the packet indicates an error this bit is set to 1. Setting of this bit also sets Error Interrupt and Transfer Completer together in the Normal Interrupt Status register. This error check is effective for a command with.." "0,1" newline bitfld.long 0x0 7. "UNRECOVERABLE,Setting of this bit means that Unrecoverable Error is set in a packet from a device." "0,1" newline bitfld.long 0x0 5. "TID,Setting of this bit means that TID Error occurs." "0,1" newline bitfld.long 0x0 4. "FRAMING,Setting of this bit means that Framing Error occurs during a packet receiving." "0,1" newline bitfld.long 0x0 3. "CRC,Setting of this bit means that CRC Error occurs during a packet receiving." "0,1" newline bitfld.long 0x0 2. "RETRY_EXPIRED,Setting of this bit means that Retry Counter Expired Error occurs during data transfer.If this bit is set either Framing Error or CRC Error in this register shall be set." "0,1" newline bitfld.long 0x0 1. "RESP_PKT,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to1 in the UHS- II Transfer Mode register Host Controller.." "0,1" newline bitfld.long 0x0 0. "HEADER,Setting of this bit means that Header Error occurs in a received packet." "0,1" line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sts_ena,This register is used to enable the UHS-II Error Interrupt Status register fields" hexmask.long.byte 0x4 27.--31. 1. "VENDOR_SPECFIC,Setting this bit to 1 enables setting of Vendor Specific Error bit in the UHS-II Error Interrupt Status register. 0h - Status is Disabled 1h - Status is Enabled" newline bitfld.long 0x4 17. "DEADLOCK_TIMEOUT,Setting this bit to 1 enables setting of Timeout for Dead lock bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 16. "CMD_RESP_TIMEOUT,Setting this bit to 1 enables setting of Timeout for CMD_RES bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 15. "ADMA2_ADMA3,Setting this bit to 1 enables setting of ADMA2/3 Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 8. "EBSY,Setting this bit to 1 enables setting of EBSY Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 7. "UNRECOVERABLE,Setting this bit to 1 enables setting of Unrecoverable Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 5. "TID,Setting this bit to 1 enables setting of TID Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 4. "FRAMING,Setting this bit to 1 enables setting of Framing Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 3. "CRC,Setting this bit to 1 enables setting of CRC Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 2. "RETRY_EXPIRED,Setting this bit to 1 enables setting of Retry Expired bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 1. "RESP_PKT,Setting this bit to 1 enables setting of RES Packet Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 0. "HEADER,Setting this bit to 1 enables setting of Header Error bit in the UHS-II Error Interrupt Status Register." "0,1" line.long 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sig_ena,This register is used to generate UHS-II Interrupt signals" hexmask.long.byte 0x8 27.--31. 1. "VENDOR_SPECFIC,Setting of a bit to 1 in this field enables generating interrupt signal when corre-spondent bit of Vendor Specific Error is set in the UHS-II Error Interrupt Status Register. 0h - Interrupt Signal is Disabled 1h -.." newline bitfld.long 0x8 17. "DEADLOCK_TIMEOUT,Setting this bit to 1 enables generating interrupt signal when Timeout for Dead lock bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 16. "CMD_RESP_TIMEOUT,Setting this bit to 1 enables generating interrupt signal when Timeout for CMD_RES bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 15. "ADMA2_ADMA3,Setting this bit to 1 enables generating interrupt signal when ADMA2/3 Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 8. "EBSY,Setting this bit to 1 enables generating interrupt signal when EBSY Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 7. "UNRECOVERABLE,Setting this bit to 1 enables generating interrupt signal when Unrecoverable Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 5. "TID,Setting this bit to 1 enables generating interrupt signal when TID Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 4. "FRAMING,Setting this bit to 1 enables generating interrupt signal when Framing Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 3. "CRC,Setting this bit to 1 enables generating interrupt signal when CRC Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 2. "RETRY_EXPIRED_SIG_ENA,Setting this bit to 1 enables generating interrupt signal when Retry Expired bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 1. "RESP_PKT,Setting this bit to 1 enables generating interrupt signal when RES Packet Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 0. "HEADER,Setting this bit to 1 enables generating interrupt signal when Header Error bit is set in the UHS-II Error Interrupt Status Register." "0,1" rgroup.word 0xE0++0x9 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_settings_ptr,This register is pointer for UHS-II settings." hexmask.word 0x0 0.--15. 1. "UHS2_SETTINGS_PTR,Pointer for UHS-II Settings Register" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_capabilities_ptr,This register is pointer for UHS-II Capabilities Register." hexmask.word 0x2 0.--15. 1. "UHS2_CAPABILITIES_PTR,Pointer for UHS-II Capabilities Register" line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_test_ptr,This register is pointer for UHS-II Test Register." hexmask.word 0x4 0.--15. 1. "UHS2_TEST_PTR,Pointer for UHS-II Test Register" line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_shared_bus_ctrl_ptr,This register is pointer for UHS-II Shared Bus Control Register." hexmask.word 0x6 0.--15. 1. "SHARED_BUS_CTRL_PTR,Pointer for Shared Bus Control Register" line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_vendor_specfic_ptr,This register is pointer for UHS-II Vendor Specific Pointer Register." hexmask.word 0x8 0.--15. 1. "VENDOR_SPECFIC_PTR,Pointer for Vendor Specific Area" rgroup.long 0xF4++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_boot_timeout_control,This is used to program the boot timeout value counter" hexmask.long 0x0 0.--31. 1. "DATA_TIMEOUT_CNT,This value determines the interval by which DAT line time-outs are detected during boot operation for eMMC4.4 card.The value is in number of sd clock." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_vendor_register,Vendor register added for autogate sdclk. cmd11 power down timer. enhancedstrobe and eMMC hardware reset" bitfld.long 0x4 16. "AUTOGATE_SDCLK,If this bit is set SD CLK will be gated automatically when there is no transfer. This is applicable only for Embedded Device" "0,1" newline hexmask.long.word 0x4 2.--15. 1. "CMD11_PD_TIMER,cmd11 power-down timer value" newline bitfld.long 0x4 1. "EMMC_HW_RESET,Hardware reset signal is generared for eMMC card when this bit is set" "0,1" newline bitfld.long 0x4 0. "ENHANCED_STROBE,This bit enables the enhanced strobe logic of the Host Controller" "0,1" rgroup.word 0xFC++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_slot_int_sts,This register is used to read the interrupt signal for each slot." hexmask.word.byte 0x0 0.--7. 1. "INTR_SIG,These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot." line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_host_controller_ver,This register is used to read the vendor version number and specification version number" hexmask.word.byte 0x2 8.--15. 1. "VEN_VER_NUM,The Vendor Version Number is set to 0x10 [1.0]" newline hexmask.word.byte 0x2 0.--7. 1. "SPEC_VER_NUM,This status indicates the Host Controller Spec. Version. The upper and lower 4-bits indicate the version. 00h - SD Host Controller Specification Version 1.00 01h - SD Host Controller Specification Version 2.00 Including the.." rgroup.long 0x100++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_gen_settings,Start Address of General settings is pointed by Pointer for UHS-II Setting Register." hexmask.long.byte 0x0 8.--13. 1. "NUMLANES,The lane configuration of a Host System is set to this field depends on the capability among Host Controller and connected devices. 2 Lanes FD mode is mandatory and the others modes are optional. 0000b - 2 Lanes FD or 2L-HD 0001b -.." newline bitfld.long 0x0 0. "POWER_MODE,This field determines either Fast mode or Low Power mode.Host and all devices connected to the host shall be set to the same mode." "0,1" line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_phy_settings,Start Address of PHY settings is pointed by Pointer for UHS-II Setting Register." hexmask.long.byte 0x4 20.--23. 1. "N_LSS_DIR,The largest value of N_LSS_DIR capabilities among the Host Controller and Connected Devices is set to this field. 0h - 8 x16 LSS 1h - 8 x 1 LSS 2h - 8 x 2 LSS 3h - 8 x 3 LSS ...... ......" newline hexmask.long.byte 0x4 16.--19. 1. "N_LSS_SYN,The largest value of N_LSS_SYN capabilities among the Host Controller and Connected Devices is set to this field. 0h - 4 x16 LSS 1h - 4 x 1 LSS 2h - 4 x 2 LSS 3h - 4 x 3 LSS ...... ......" newline bitfld.long 0x4 15. "HIBERNATE_ENA,After checking card capability of Hibernate mode if all devices support Hibernate mode this bit may be set. This bit determines whether Host remains in Dormant state or goes to Hibernate state. In Hibernate mode VDD1 Power may be off." "0,1" newline bitfld.long 0x4 6.--7. "SPEED_RANGE,PLL multiplier is selected by this field.Change of PLL Multiplier is not effective immediately and is applied from exiting Dormant State. '00' Range A [Default] '01' Range B '10' Reserved '11' Reserved" "0,1,2,3" rgroup.quad 0x108++0x7 line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_lnk_trn_settings,Start Address of LINK/TRAN settings is pointed by Pointer for UHS-II Setting Register." hexmask.quad.byte 0x0 32.--39. 1. "N_DATA_GAP,The largest value of N_DATA_GAP capabilities among the Host Controller and Connected Devices is set to this field. 00h - No Gap 01h - 1 LSS 02h - 2 LSS 03h - 3 LSS ...... ...... FFh - 255.." newline bitfld.quad 0x0 16.--17. "RETRY_COUNT,Data Burst retry count is set to this field. '00' Retry Disabled '01' 1 time '10' 2 times '11' 3 times" "0,1,2,3" newline hexmask.quad.byte 0x0 8.--15. 1. "HOST_NFCU,Host Driver sets the number of blocks in Data Burst [Flow Control] to this field.The value shall be smaller than or equal to N_FCU capabilities among the Host Controller and connected card and devices. Setting 1 to 4 blocks is recommended.." rgroup.long 0x110++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_gen_cap,Start Address of General Capabilities is pointed by Pointer for UHS-II Host Capabilities Register." bitfld.long 0x0 22.--23. "CORECFG_UHS2_BUS_TOPLOGY,This field indicates one of bus topologies configured by a Host system. '00' P2P Connection '01' Ring Connection '10' HUB Connection '11' HUB is connected in Ring" "0,1,2,3" newline hexmask.long.byte 0x0 18.--21. 1. "CORECFG_UHS2_MAX_DEVICES,This field indicates the maximum number of devices supported by the Host Controller. 0h - Not used 1h - 1 Devices 2h - 2 Devices ..... ....... Fh - 15 Devices" newline bitfld.long 0x0 16.--17. "DEVICE_TYPE,This field indicates device type configured by a Host system. '00' Removable Card[P2P] '01' Embedded Devices '10' Embedded Devices+Removable Card '11' Reserved" "0,1,2,3" newline bitfld.long 0x0 14. "CFG_64BIT_ADDRESSING,This field indicates support of 64-bit addressing by the Host Controller. '0' 32-bit Addressing is supported '1' 32-bit and 64-bit Addressing is supported" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "NUM_LANES,This field indicates support of lanes by the Host Controller.0 mean not supported and 1 means supported. D08 - 2L-HD D09 - 2D1U-FD D10 - 1D2U-FD D11 - 2D2U-FD D12 - Reserved D13 - Reserved" newline hexmask.long.byte 0x0 4.--7. 1. "GAP,This field indicates the maximum capability of host power supply for a group configured by a Host system.This field is used to set the argument of DEVICE_INIT CCMD 0h -Not used 1h - 360 mW 2h - 720 mW ....." newline hexmask.long.byte 0x0 0.--3. 1. "DAP,This field indicates the maximum capability of host power supply for a device configured by a Host system.This field is used to set the argument of DEVICE_INIT CCMD 0h -360 mW [Default] 1h - 360 mW 2h - 720 mW.." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_phy_cap,Start Address of PHY Capabilities is pointed by Pointer for UHS-II Host Capabilities Register." hexmask.long.byte 0x4 20.--23. 1. "N_LSS_DIR,This field indicates the minimum N_LSS_DIR required by the Host Controller. 0h - 4 x16 LSS 1h - 4 x 1 LSS 2h - 4 x 2 LSS 3h - 4 x 3 LSS ...... ...... Fh - 4 x 15 LSS" newline hexmask.long.byte 0x4 16.--19. 1. "N_LSS_SYN,This field indicates the minimum N_LSS_SYN required by the Host Controller. 0h - 4 x16 LSS 1h - 4 x 1 LSS 2h - 4 x 2 LSS 3h - 4 x 3 LSS ...... ...... Fh - 4 x 15 LSS" newline bitfld.long 0x4 6.--7. "SPEED_RANGE,This field indicates supported Speed Range by the Host Controller '00' Range A [Default] '01' Range A and Range B '10' Reserved '11' Reserved" "0,1,2,3" rgroup.quad 0x118++0x7 line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_lnk_trn_cap,Start Address of LINK/TRAN settings is pointed by Pointer for UHS-II Capabilities Register." hexmask.quad.byte 0x0 32.--39. 1. "N_DATA_GAP,This field indicates the minimum number of data gap[DIDL] supported by the Host Controller. 00h - No Gap 01h - 1 LSS 02h - 2 LSS 03h - 3 LSS ...... ...... FFh - 255 LSS" newline hexmask.quad.word 0x0 20.--31. 1. "MAX_BLK_LENGTH,This field indicates maximum block length by the Host Controller. 000h - Not Used 001h - 1 byte 002h - 2 bytes ...... ...... 200h - 512 bytes ...... ......" newline hexmask.quad.byte 0x0 8.--15. 1. "N_FCU,This field indicates maximum the number of blocks in a Flow Control unit by the Host Controller.This value is determined by supported buffer size. 00h - 256 Blocks 01h - 1 Block 02h - 2 Block 03h - 3 Block.." rgroup.long 0x120++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_force_UHSII_Err_Int_Sts,This register is not physically implemented. rather it is an address where UHS-II Error Interrupt Status register can be written." hexmask.long.byte 0x0 27.--31. 1. "VENDOR_SPECIFIC,Force Event for Vendor Specific Error 0h - Not Affected 1h - Vendor Specific Error Status is set" newline bitfld.long 0x0 17. "TIMEOUT_DEADLOCK,Setting this bit forces the Host Controller to set Timeout for Deadlock in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 16. "TIMEOUT_CMD_RES,Setting this bit forces the Host Controller to set Timeout for CMD_RES in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 15. "ADMA,Setting this bit forces the Host Controller to set ADMA Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 8. "EBSY,Setting this bit forces the Host Controller to set EBSY Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 7. "UNRECOVERABLE,Setting this bit forces the Host Controller to set Unrecover-able Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 5. "TID,Setting this bit forces the Host Controller to set TID Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 4. "FRAMING,Setting this bit forces the Host Controller to set Framing Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 3. "CRC,Setting this bit forces the Host Controller to set CRC Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 2. "RETRY_EXPIRED,Setting this bit forces the Host Controller to set Retry Expired in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 1. "RES_PKT,Setting this bit forces the Host Controller to set RES Packet Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 0. "HEADER,Setting this bit forces the Host Controller to set Header Error in the UHS-II Error Interrupt Status register." "0,1" rgroup.long 0x200++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_version,This register provides information about the version of the eMMC CQ standard which is 285 implemented by the CQE. in BCD format. The current version is rev 5.1" hexmask.long.byte 0x0 8.--11. 1. "EMMC_MAJOR_VER_NUM,eMMC Major Version Number [digit left of decimal point] in BCD format" newline hexmask.long.byte 0x0 4.--7. 1. "EMMC_MINOR_VER_NUM,eMMC Minor Version Number [digit right of decimal point] in BCD format" newline hexmask.long.byte 0x0 0.--3. 1. "EMMC_VERSION_SUFFIX,eMMC Version Suffix [2nd digit right of decimal point] in BCD format" line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_capabilities,This register is reserved for capability indication." hexmask.long.byte 0x4 12.--15. 1. "CF_MUL,Internal Timer Clock Frequency Multiplier [ITCFMUL] ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for deter-mining the SQS polling period. See ITCFVAL definition for details." newline hexmask.long.word 0x4 0.--9. 1. "CF_VAL,Internal Timer Clock Frequency Value [ITCFVAL] TCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for deter-mining the polling period when using periodic SEND_QUEUE_ STATUS [CMD13] polling." rgroup.long 0x208++0x27 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_config,This register controls CQE behavior affecting the general operation of command queueing 290 module or operation of multiple tasks in the same time." bitfld.long 0x0 12. "DCMD_ENA,Direct Command [DCMD] Enable This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a Data Transfer Task Descriptor or a Direct Command Task Descriptor. CQE uses this bit when a task is issued in slot.." "0: Task descriptor in slot #31 is a Data Transfer..,1: Task descriptor in slot #31 is a DCMD Task.." newline bitfld.long 0x0 8. "TASK_DESC_SIZE,Task Descriptor Size This bit indicates whether the task descriptor size is 128 bits or 64 bits as detailed in Data Structures section. This bit can only be configured when Command Queueing Enable bit is 0 [command queueing is.." "0: Task descriptor size is 64 bits,1: Task descriptor size is 128 bits" newline bitfld.long 0x0 0. "CQ_ENABLE,Command Queueing Enable Software shall write 1 this bit when in order to enable command queueing mode [i.e. enable CQE]. When this bit is 0 CQE is disabled and software controls the eMMC bus using the legacy eMMC host controller." "0,1" line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_control,This register controls CQE behavior affecting the general operation of command queueing 293 module or operation of multiple tasks in the same time." bitfld.long 0x4 8. "CLEAR_ALL_TASKS,Clear All Tasks Software shall write 1 this bit when it wants to clear all the tasks sent to the device. This bit can only be written when CQE is in halt state [i.e.Halt bit is 1]. When software writes 1 the value of the.." "0,1" newline bitfld.long 0x4 0. "HALT_BIT,Halt Host software shall write 1 to the bit when it wants to acquire software control over the eMMC bus and disable CQE from issuing commands on the bus. For example issuing a Discard Task command [CMDQ_TASK_MGMT] When software writes 1 .." "0,1" line.long 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sts,This register indicates pending interrupts that require service. Each bit in this registers is asserted 296 in response a specific event. only if the respective bit is set in CQ ISTE register." bitfld.long 0x8 4. "TASK_ERROR,Task Error Interrupt [TERR] This bit is asserted when task error is detected due to invalid task descriptor" "0,1" newline bitfld.long 0x8 3. "TASK_CLEARED,Task Cleared [TCL] This status bit is asserted [if CQISTE.TCL=1] when a task clear operation is completed by CQE. The com-pleted task clear operation is either an individual task clear [CQTCLR] or clearing of all tasks [CQCTL]." "0,1" newline bitfld.long 0x8 2. "RESP_ERR_DET,Response Error Detected Interrupt [RED] This status bit is asserted [if CQISTE.RED=1] when a response is received with an error bit set in the device status field. The contents of the device status field are listed in Section.." "0,1" newline bitfld.long 0x8 1. "TASK_COMPLETE,Task Complete Interrupt [TCC] This status bit is asserted [if CQISTE.TCC=1] when atleast one of the following two conditions are met: [1] A task is completed and the INT bit is set in its Task Descriptor [2] Interrupt caused by.." "0,1" newline bitfld.long 0x8 0. "HALT_COMPLETE,Halt Complete Interrupt [HAC] This status bit is asserted [if CQISTE.HAC=1] when halt bit in CQCTL register transitions from 0 to 1 indicating that host controller has completed its current ongoing task and has entered halt state." "0,1" line.long 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sts_ena,This register enables and disables the reporting of the corresponding interrupt to host soft-ware in 299 CQIS register. When a bit is set ( 1 ) and the corresponding interrupt c -ondition is active. then.." bitfld.long 0xC 4. "TASK_ERROR,Task Error Interrupt Status Enable 1 = CQIS.TERR will be set when its interrupt condition is active 0 = CQIS.TERR is disabled" "0: CQIS,1: CQIS" newline bitfld.long 0xC 3. "TASK_CLEARED,Task Cleared Status Enable [TCL] 1 = CQIS.TCL will be set when its interrupt condition is active 0 = CQIS.TCL is disabled" "0: CQIS,1: CQIS" newline bitfld.long 0xC 2. "RESP_ERR_DET,Response Error Detected Status Enable [RED] 1 = CQIS.RED will be set when its interrupt condition is active 0 = CQIS.RED is disabled" "0: CQIS,1: CQIS" newline bitfld.long 0xC 1. "TASK_COMPLETE,Task Complete Status Enable [TCC] 1 = CQIS.TCC will be set when its interrupt condition is active 0 = CQIS.TCC is disabled" "0: CQIS,1: CQIS" newline bitfld.long 0xC 0. "HALT_COMPLETE,Halt Complete Status Enable [HAC] 1 = CQIS.HAC will be set when its interrupt condition is active 0 = CQIS.HAC is disabled" "0: CQIS,1: CQIS" line.long 0x10 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sig_ena,This register enables and disables the generation of interrupts to host software. When a bit is set 304 ( 1 ) and the corresponding bit in CQIS is set. then an interrupt is gene -rated. Interrupt sources.." bitfld.long 0x10 4. "TASK_ERROR,Task Error Interrupt Signal Enable [TERR] When set and CQIS.TERR is asserted the CQE shall generate an interrupt" "0,1" newline bitfld.long 0x10 3. "TASK_CLEARED,Task Cleared Signal Enable [TCL] When set and CQIS.TCL is asserted the CQE shall generate an interrupt" "0,1" newline bitfld.long 0x10 2. "RESP_ERR_DET,Response Error Detected Signal Enable [TCC] When set and CQIS.RED is asserted the CQE shall generate an interrupt" "0,1" newline bitfld.long 0x10 1. "TASK_COMPLETE,Task Complete Signal Enable [TCC] When set and CQIS.TCC is asserted the CQE shall generate an interrupt" "0,1" newline bitfld.long 0x10 0. "HALT_COMPLETE,Halt Complete Signal Enable [HAC] When set and CQIS.HAC is asserted the CQE shall generate an interrupt" "0,1" line.long 0x14 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_coalescing,This register controls the interrupt coalescing feature." bitfld.long 0x14 31. "CQINTCOALESC_ENABLE,When set to 0 by software command responses are neither counted nor timed. Interrupts are still triggered by completion of tasks with INT=1 in the Task Descriptor. When set to 1 the interrupt coalescing mechanism is enabled.." "0,1" newline rbitfld.long 0x14 20. "IC_STATUS,This bit indicates to software whether any tasks [with INT=0] have completed and counted towards interrupt coalescing [i.e. ICSB is set if and only if IC counter > 0]. Bit Value Description 1 = At least one task completion has been.." "0: No task completions have occurred since last..,1: At least one task completion has been counted.." newline hexmask.long.byte 0x14 8.--12. 1. "CTR_THRESHOLD,Interrupt Coalescing Counter Threshold [ICCTH]: Software uses this field to configure the number of task completions [only tasks with INT=0 in the Task Descriptor] which are required in order to generate an interrupt. Counter.." newline hexmask.long.byte 0x14 0.--6. 1. "TIMEOUT_VAL,Interrupt Coalescing Timeout Value [ICTOVAL]: Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. Timer Operation: The timer is reset by.." line.long 0x18 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_tdl_base_addr,This register is used for configuring the lower 32 bits of the byte address of the head of the Task 312 Descriptor List in the host memory." hexmask.long 0x18 0.--31. 1. "CQTDLBA_LO,Task Descriptor List Base Address [TDLBA] This register stores the LSB bits [bits 31:0] of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 * [Task Descrip-tor.." line.long 0x1C "SDHC_WRAP__CTL_CFG__CTLCFG_cq_tdl_base_addr_upbits,This register is used for configuring the upper 32 bits of the byte address of the head of the Task 316 Descriptor List in the host memory." hexmask.long 0x1C 0.--31. 1. "CQTDLBA_HI,Task Descriptor List Base Address [TDLBA] This register stores the MSB bits [bits 63:32] of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 * [Task Descrip-tor.." line.long 0x20 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_door_bell,Using this register. software triggers CQE to process a new task." hexmask.long 0x20 0.--31. 1. "CQTDB_VAL,Command Queueing Task Doorbell Software shall configure TDLBA and TDLBAU and enable CQE in CQCFG before using this register. Writing 1 to bit n of this register triggers CQE to start pro-cessing the task encoded in slot n of the TDL." line.long 0x24 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_comp_notif,This register is used by CQE to notify software about completed tasks." hexmask.long 0x24 0.--31. 1. "CQTCN_VAL,CQE shall set bit n of this register [at the same time it clears bit n of CQTDBR] when a task execution is com-pleted [with success or error]. When receiving interrupt for task completion software may read this register to know which tasks.." rgroup.long 0x230++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dev_queue_status,This register stores the most recent value of the device s queue status." hexmask.long 0x0 0.--31. 1. "CQDQ_STS,Every time the Host controller receives a queue status register [QSR] from the device it updates this register with the response of status command i.e. the devices queue status." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dev_pending_tasks,This register indicates to software which tasks are queued in the device. awaiting execution." hexmask.long 0x4 0.--31. 1. "CQDP_TSKS,Bit n of this register is set if and only if QUEUED_TASK_PARAMS [CMD44] and QUEUED_TASK_ADDRESS [CMD45] were sent for this specific task and if this task hasnt been executed yet.CQE shall set this bit after receiving a successful response for.." rgroup.long 0x238++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_clear,This register is used for removing an outstanding task in the CQE. 327. The register should be used only when CQE is in Halt state." hexmask.long 0x0 0.--31. 1. "CQTCLR,Writing 1 to bit n of this register orders CQE to clear a task which software has previously issued.This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit.When software writes 1 to a bit in this.." rgroup.long 0x240++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_send_sts_config1,The register controls the when SEND_QUEUE_STATUS commands are sent." hexmask.long.byte 0x0 16.--19. 1. "CMD_BLK_CNTR,This field indicates to CQE when to send SEND_QUEUE_STATUS [CMD13] command to inquire the status of the devices task queue.A value of n means CQE shall send status command on the CMD line during the transfer of data block BLOCK_CNT-n on.." newline hexmask.long.word 0x0 0.--15. 1. "CMD_IDLE_TIMER,This field indicates to CQE the polling period to use when using periodic SEND_QUEUE_STATUS [CMD13] polling.Periodic polling is used when tasks are pending in the device but no data transfer is in progress. When a SEND_QUEUE_STATUS.." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_send_sts_config2,This register is used for 333 configuring RCA field in SEND_QUEUE_STATUS command argu-ment." hexmask.long.word 0x4 0.--15. 1. "QUEUE_RCA,This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_ STATUS [CMD13] com-mand. argument. CQE shall copy this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS [CMD13] command." rgroup.long 0x248++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dcmd_response,This register is used for passing the response of a DCMD task to software." hexmask.long 0x0 0.--31. 1. "LAST_RESP,This register contains the response of the command generated by the last direct-command [DCMD] task which was sent.CQE shall update this register when it receives the response for a DCMD task. This register is considered valid only after bit 31.." rgroup.long 0x250++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_resp_err_mask,This register controls the generation of Response Error Detection (RED) interrupt." hexmask.long 0x0 0.--31. 1. "CQRMEM,This bit is used as in interrupt mask on the device status filed which is received in R1/R1b responses.Bit Value Description [for any bit i]:1 = When a R1/R1b response is received with bit i in the device status set a RED interrupt is generated.." rgroup.long 0x254++0xF line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_err_info,This register is updated by CQE when an error occurs on data or command related to a task activity." bitfld.long 0x0 31. "DATERR_VALID,Data Transfer Error Fields Valid This bit is updated when an error is detected by CQE or indicated by eMMC controller. If a data transfer is in progress when the error is detected/indicated the bit is set to 1. If a no.." "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "DATERR_TASK_ID,Data Transfer Error Task ID This field indicates the ID of the task which was executed on the data lines when an error occurred. The field is updated if a data transfer is in progress when an error is detected by CQE or.." newline hexmask.long.byte 0x0 16.--21. 1. "DATERR_CMD_INDEX,Data Transfer Error Command Index This field indicates the index of the command which was executed on the data lines when an error occurred. The index shall be set to EXECUTE_READ_TASK[CMD46] or EXECUTE_WRITE_TASK [CMD47].." newline bitfld.long 0x0 15. "RESP_MODE_VALID,Response Mode Error Fields Valid This bit is updated when an error is detected by CQE or indicated by eMMC controller. If a command transaction is in progress when the error is detected/indicated the bit is set to 1." "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "RESP_MODE_TASK_ID,Response Mode Error Task ID This field indicates the ID of the task which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is detected by.." newline hexmask.long.byte 0x0 0.--5. 1. "RESP_MODE_CMD_INDEX,Response Mode Error Command Index This field indicates the index of the command which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is.." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_cmd_resp_index,This register stores the index of the last received command response." hexmask.long.byte 0x4 0.--5. 1. "LAST_CRI,This field stores the index of the last received command response. CQE shall update the value every time a com-mand response is received." line.long 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_cmd_resp_arg,This register stores the index of the last received command response." hexmask.long 0x8 0.--31. 1. "LAST_CRA,This field stores the argument of the last received com-mand. CQE shall update the value every time a com-mand response is received." line.long 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_cq_error_task_id,CQ Error Task ID Register" hexmask.long.byte 0xC 0.--4. 1. "TERR_ID,Task Error ID" tree.end tree "MMCSD0_ECC_AGGR" tree "MMCSD0_ECC_AGGR_RXMEM (MMCSD0_ECC_AGGR_RXMEM)" base ad:0x2A24000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_RXMEM__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "RXMEM_ENABLE_SET,Interrupt Enable Set Register for rxmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear Register for rxmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_RXMEM__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "RXMEM_ENABLE_SET,Interrupt Enable Set Register for rxmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear Register for rxmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_RXMEM__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_RXMEM__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_RXMEM__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MMCSD0_ECC_AGGR_TXMEM (MMCSD0_ECC_AGGR_TXMEM)" base ad:0x2A25000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_TXMEM__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "TXMEM_ENABLE_SET,Interrupt Enable Set Register for txmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear Register for txmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_TXMEM__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "TXMEM_ENABLE_SET,Interrupt Enable Set Register for txmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear Register for txmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_TXMEM__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_TXMEM__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_TXMEM__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree.end tree "MMCSD0_SS_CFG (MMCSD0_SS_CFG)" base ad:0x4F88000 rgroup.long 0x0++0x3 line.long 0x0 "REGS__SS_CFG__SSCFG_SS_ID_REV_REG,The Subsystem ID and Revision Register contains the module ID. major. and minor revisions for the subsystem" hexmask.long.word 0x0 16.--31. 1. "MOD_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version" newline bitfld.long 0x0 8.--10. "MAJ_REV,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MIN_REV,Minor revision" rgroup.long 0x10++0x37 line.long 0x0 "REGS__SS_CFG__SSCFG_CTL_CFG_1_REG,The Controller Config 1 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.byte 0x0 24.--29. 1. "TUNINGCOUNT,Configures the Number of Taps (Phases) of the RX clock that is supported. The Tuning State machine uses this information to select one of the Taps (Phases) of the RX clock during the Tuning Procedure." bitfld.long 0x0 20. "ASYNCWKUPENA,Determines the Wakeup Signal Generation Mode. 0: Synchronous Wakeup Mode: The xin_clk has to be running for this mode. The Card Insertion/Removal/Interrupt events are detected synchronously on the xin_clk and the Wakeup Event is generated." "0: Synchronous Wakeup Mode: The xin_clk has to be..,1: Asyncrhonous Wakeup Mode: The xin_clk and the.." newline hexmask.long.byte 0x0 12.--15. 1. "CQFMUL,FMUL for the CQ Internal Timer Clock Frequency" hexmask.long.word 0x0 0.--9. 1. "CQFVAL,FVAL for the CQ Internal Timer Clock Frequency" line.long 0x4 "REGS__SS_CFG__SSCFG_CTL_CFG_2_REG,The Controller Config 2 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." bitfld.long 0x4 30.--31. "SLOTTYPE,Slot Type. Should be set based on the final product usage. 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved." "0: Removable SCard Slot,1: Embedded Slot for One Device,?,?" bitfld.long 0x4 29. "ASYNCHINTRSUPPORT,Asynchronous Interrupt Support. Suggested Value is 1'b1 (The Core supports monitoring of Asynchronous Interrupt)." "0,1" newline bitfld.long 0x4 26. "SUPPORT1P8VOLT,1.8V Support. Suggested Value is 1'b1 (The 1.8 Volt Switching is supported by Core). Optionally can be set to 1'b0 if the application doesn't want 1.8V switching (SD3.0)." "0,1" bitfld.long 0x4 25. "SUPPORT3P0VOLT,3.0V Support. Should be set based on whether 3.0V is supported on the SD Interface." "0,1" newline bitfld.long 0x4 24. "SUPPORT3P3VOLT,3.3V Support. Suggested Value is 1'b1 as the 3.3 V is the default voltage on the SD Interface." "0,1" bitfld.long 0x4 23. "SUSPRESSUPPORT,Suspend/Resume Support. Suggested Value is 1'b1 (The Suspend/Resume is supported by Core). Optionally can be set to 1'b0 if the application doesn't want to support Suspend/Resume Mode." "0,1" newline bitfld.long 0x4 22. "SDMASUPPORT,SDMA Support. Suggested Value is 1'b1 (The SDMA is supported by Core). Optionally can be set to 1'b0 if the application doesn't want to support SDMA Mode." "0,1" bitfld.long 0x4 21. "HIGHSPEEDSUPPORT,High Speed Support. Suggested Value is 1'b1 (The High Speed mode is supported by Core)." "0,1" newline bitfld.long 0x4 19. "ADMA2SUPPORT,ADMA2 Support. Suggested Value is 1'b1 (The ADMA2 is supported by Core). Optionally can be set to 1'b0 if the application doesn't want to support ADMA2 Mode." "0,1" bitfld.long 0x4 18. "SUPPORT8BIT,8-bit Support for Embedded Device. Suggested Value is 1'b1 (The Core supports 8-bit Interface). Optionally an be set to 1'b0 if the Application supports only 4-bit SD Interface." "0,1" newline bitfld.long 0x4 16.--17. "MAXBLKLENGTH,Max Block Length. Maximum Block Length supported by the Core/Device. 00: 512 (Bytes) 01: 1024 10: 2048 11: Reserved." "0,1,2,3" hexmask.long.byte 0x4 8.--15. 1. "BASECLKFREQ,Base Clock Frequency for SD Clock. This is the frequency of the xin_clk." newline bitfld.long 0x4 7. "TIMEOUTCLKUNIT,Timeout Clock Unit. Suggested Value is 1'b0 (KHz)." "0,1" hexmask.long.byte 0x4 0.--5. 1. "TIMEOUTCLKFREQ,Timeout Clock Frequency. Suggested Value is 1 KHz. Internally the 1msec Timer is used for Timeout Detection. The 1msec Timer is generated from the xin_clk." line.long 0x8 "REGS__SS_CFG__SSCFG_CTL_CFG_3_REG,The Controller Config 3 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." bitfld.long 0x8 31. "HS400SUPPORT,HS400 Support. Suggested Value is 1'b1 (The Core supports HS400 Mode). This applies only to eMMC5.0 mode. This should be set to 1'b0 for SD3.0 mode Optionally can be set to 1'b0 if the application doesn't want to support HS400." "0,1" bitfld.long 0x8 28. "SUPPORT1P8VDD2,1.8V VDD2 Support." "0,1" newline bitfld.long 0x8 27. "ADMA3SUPPORT,ADMA3 Support." "0,1" hexmask.long.byte 0x8 16.--23. 1. "CLOCKMULTIPLIER,Clock Multiplier. This field indicates clock multiplier value of programmable clock generator. Refer to Clock Control register. Setting 00h means that Host Controller does not support programmable clock generator. FFh Clock Multiplier M =.." newline bitfld.long 0x8 14.--15. "RETUNINGMODES,Re-Tuning Modes. Should be set to 2'b00 as the Core supports only the Software Timer based Re-Tuning." "0,1,2,3" bitfld.long 0x8 13. "TUNINGFORSDR50,Use Tuning for SDR50. This bit should be set if the Application wants Tuning be used for SDR50 Modes. The Core operates with or with out tuning for SDR50 mode as long as the Clock can be manually tuned using tap delay." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "RETUNINGTIMERCNT,Timer Count for Re-Tuning. This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer." bitfld.long 0x8 7. "TYPE4SUPPORT,Driver Type 4 Support. This bit should be set based on whether Driver Type 4 for 1.8 Signalling is supported or not." "0,1" newline bitfld.long 0x8 6. "DDRIVERSUPPORT,Driver Type D Support. This bit should be set based on whether Driver Type D for 1.8 Signalling is supported or not." "0,1" bitfld.long 0x8 5. "CDRIVERSUPPORT,Driver Type C Support. This bit should be set based on whether Driver Type C for 1.8 Signalling is supported or not." "0,1" newline bitfld.long 0x8 4. "ADRIVERSUPPORT,Driver Type A Support. This bit should be set based on whether Driver Type A for 1.8 Signalling is supported or not." "0,1" bitfld.long 0x8 2. "DDR50SUPPORT,DDR50 Support. Suggested Value is 1'b1 (The Core supports DDR50 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support DDR50." "0,1" newline bitfld.long 0x8 1. "SDR104SUPPORT,SDR104 Support. Suggested Value is 1'b1 (The Core supports SDR104 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support SDR104." "0,1" bitfld.long 0x8 0. "SDR50SUPPORT,SDR50 Support. Suggested Value is 1'b1 (The Core supports SDR50 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support SDR50." "0,1" line.long 0xC "REGS__SS_CFG__SSCFG_CTL_CFG_4_REG,The Controller Config 4 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.byte 0xC 16.--23. 1. "MAXCURRENT1P8V,Maximum Current for 1.8V." hexmask.long.byte 0xC 8.--15. 1. "MAXCURRENT3P0V,Maximum Current for 3.0V." newline hexmask.long.byte 0xC 0.--7. 1. "MAXCURRENT3P3V,Maximum Current for 3.3V." line.long 0x10 "REGS__SS_CFG__SSCFG_CTL_CFG_5_REG,The Controller Config 5 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.byte 0x10 0.--7. 1. "MAXCURRENTVDD2,Maximum Current for 1.8 V (VDD2)." line.long 0x14 "REGS__SS_CFG__SSCFG_CTL_CFG_6_REG,The Controller Config 6 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x14 0.--12. 1. "INITPRESETVAL,Preset Value for Initialization." line.long 0x18 "REGS__SS_CFG__SSCFG_CTL_CFG_7_REG,The Controller Config 7 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x18 0.--12. 1. "DSPDPRESETVAL,Preset Value for Default Speed." line.long 0x1C "REGS__SS_CFG__SSCFG_CTL_CFG_8_REG,The Controller Config 8 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x1C 0.--12. 1. "HSPDPRESETVAL,Preset Value for High Speed." line.long 0x20 "REGS__SS_CFG__SSCFG_CTL_CFG_9_REG,The Controller Config 9 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x20 0.--12. 1. "SDR12PRESETVAL,Preset Value for SDR12." line.long 0x24 "REGS__SS_CFG__SSCFG_CTL_CFG_10_REG,The Controller Config 10 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x24 0.--12. 1. "SDR25PRESETVAL,Preset Value for SDR25." line.long 0x28 "REGS__SS_CFG__SSCFG_CTL_CFG_11_REG,The Controller Config 11 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x28 0.--12. 1. "SDR50PRESETVAL,Preset Value for SDR50." line.long 0x2C "REGS__SS_CFG__SSCFG_CTL_CFG_12_REG,The Controller Config 12 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x2C 0.--12. 1. "SDR104PRESETVAL,Preset Value for SDR104." line.long 0x30 "REGS__SS_CFG__SSCFG_CTL_CFG_13_REG,The Controller Config 13 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x30 0.--12. 1. "DDR50PRESETVAL,Preset Value for DDR50." line.long 0x34 "REGS__SS_CFG__SSCFG_CTL_CFG_14_REG,The Controller Config 14 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x34 0.--12. 1. "HS400PRESETVAL,Preset Value for HS400." rgroup.long 0x60++0x17 line.long 0x0 "REGS__SS_CFG__SSCFG_CTL_STAT_1_REG,The Controller Status 1 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." bitfld.long 0x0 31. "SDHC_CMDIDLE,Idle signal to enable S/W to gate off the clocks." "0,1" hexmask.long.word 0x0 0.--15. 1. "DMADEBUGBUS,DMA_CTRL Debug Bus." line.long 0x4 "REGS__SS_CFG__SSCFG_CTL_STAT_2_REG,The Controller Status 2 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0x4 0.--15. 1. "CMDDEBUGBUS,CMD_CTRL Debug Bus." line.long 0x8 "REGS__SS_CFG__SSCFG_CTL_STAT_3_REG,The Controller Status 3 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0x8 0.--15. 1. "TXDDEBUGBUS,TXD_CTRL Debug Bus." line.long 0xC "REGS__SS_CFG__SSCFG_CTL_STAT_4_REG,The Controller Status 4 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0xC 0.--15. 1. "RXDDEBUGBUS0,RXD_CTRL Debug Bus (SD CLK)." line.long 0x10 "REGS__SS_CFG__SSCFG_CTL_STAT_5_REG,The Controller Status 5 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0x10 0.--15. 1. "RXDDEBUGBUS1,RXD_CTRL Debug Bus (RX CLK)." line.long 0x14 "REGS__SS_CFG__SSCFG_CTL_STAT_6_REG,The Controller Status 6 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0x14 0.--15. 1. "TUNDEBUGBUS,TUN_CTRL Debug Bus." rgroup.long 0x100++0x17 line.long 0x0 "REGS__SS_CFG__SSCFG_PHY_CTRL_1_REG,The PHY Control 1 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." bitfld.long 0x0 20.--22. "DR_TY,Drive Source/Sink impedance programming. 0 => 50 Ohms 1 => 33 Ohms 2 => 66 Ohms 3 => 100 Ohms 4 => 40 Ohms." "0,1,2,3,4,5,6,7" bitfld.long 0x0 17. "RETRIM,Start IO calibration cycle. A positive edge initiates the IO calibration cycle using CALIO." "0,1" newline bitfld.long 0x0 16. "EN_RTRIM,Enables CALIO. When enabled CALIO will start IO calibration cycle on the positive edge of pdb." "0,1" hexmask.long.byte 0x0 4.--7. 1. "DLL_TRM_ICP,Analog DLL's Charge Pump Current Trim. Programs the analog DLL loop gain." newline bitfld.long 0x0 1. "ENDLL,Enable DLL. Enables the analog DLL circuits." "0,1" bitfld.long 0x0 0. "PDB,Active low power down for CALIO. Software must write a 1 to power-up CALIO during power-up sequence." "0,1" line.long 0x4 "REGS__SS_CFG__SSCFG_PHY_CTRL_2_REG,The PHY Control 2 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." bitfld.long 0x4 29. "OD_RELEASE_STRB,Disable an internal 4.7K pull up resistor on STRB line in open drain mode." "0,1" bitfld.long 0x4 28. "OD_RELEASE_CMD,Disable an internal 4.7K pull up resistor on CMD line in open drain mode." "0,1" newline hexmask.long.byte 0x4 16.--23. 1. "OD_RELEASE_DAT,Disable an internal 4.7K pull up resistor on data lines in open drain mode." bitfld.long 0x4 13. "ODEN_STRB,Open Drain Enable on STRB line." "0,1" newline bitfld.long 0x4 12. "ODEN_CMD,Open Drain Enable on CMD line." "0,1" hexmask.long.byte 0x4 0.--7. 1. "ODEN_DAT,Open Drain Enable on DAT lines." line.long 0x8 "REGS__SS_CFG__SSCFG_PHY_CTRL_3_REG,The PHY Control 3 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." bitfld.long 0x8 29. "PU_STRB,Internal pull select for STRB line. 0=pull-down 1=pull-up." "0: pull-down,1: pull-up" bitfld.long 0x8 28. "PU_CMD,Internal pull select for CMD line. 0=pull-down 1=pull-up." "0: pull-down,1: pull-up" newline hexmask.long.byte 0x8 16.--23. 1. "PU_DAT,Internal pull select for DAT lines. 0=pull-down 1=pull-up." bitfld.long 0x8 13. "REN_STRB,Enable internal pull-up/down resistor on the STRB line. 0=internal pull disable 1=internal pull enabled." "0: internal pull disable,1: internal pull enabled" newline bitfld.long 0x8 12. "REN_CMD,Enable internal pull-up/down resistor on the CMD line. 0=internal pull disable 1=internal pull enabled." "0: internal pull disable,1: internal pull enabled" hexmask.long.byte 0x8 0.--7. 1. "REN_DAT,Enable internal pull-up/down resistor on the DAT lines. 0=internal pull disable 1=internal pull enabled." line.long 0xC "REGS__SS_CFG__SSCFG_PHY_CTRL_4_REG,The PHY Control 4 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." hexmask.long.byte 0xC 24.--31. 1. "STRBSEL,Select the Four Taps for each of STRB_90 and STRB_180 Outputs. strbsel[3:2] selects one of the four for STRB_180 and strbsel[1:0] selects the four taps for STRB_90." bitfld.long 0xC 20. "OTAPDLYENA,Output Tap Delay Enable. Enables manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface." "0,1" newline hexmask.long.byte 0xC 12.--15. 1. "OTAPDLYSEL,Output Tap Delay Select. Manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface." bitfld.long 0xC 9. "ITAPCHGWIN,Input Tap Change Window. It gets asserted by the controller while changing the itapdlysel. Used to gate of the RX clock during switching the clock source while tap is changing to avoid clock glitches." "0,1" newline bitfld.long 0xC 8. "ITAPDLYENA,Input Tap Delay Enable. This is used for the manual control of the RX clock Tap Delay in non HS200/HS400 modes." "0,1" hexmask.long.byte 0xC 0.--4. 1. "ITAPDLYSEL,Input Tap Delay Select. Manual control of the RX clock Tap Delay in the non HS200/HS400 modes." line.long 0x10 "REGS__SS_CFG__SSCFG_PHY_CTRL_5_REG,The PHY Control 5 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." bitfld.long 0x10 17. "SELDLYTXCLK,Select the Delay chain based txclk. Enables the TX clock based delay chain rather than analog DLL based delay chain." "0,1" bitfld.long 0x10 16. "SELDLYRXCLK,Select the Delay chain based rxclk. Enables the RX clock based delay chain rather than analog DLL based delay chain." "0,1" newline bitfld.long 0x10 8.--10. "FRQSEL,Select the frequency range of DLL operation: 0 => 200MHz to 170 MHz 1 => 170MHz to 140 MHz 2 => 140MHz to 110 MHz 3 => 110MHz to 80MHz 4 => 80MHz to 50 MHz 5 => 275Mhz to 250MHz 6 => 250MHz to 225MHz 7 => 225MHz to 200MHz." "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "CLKBUFSEL,Clock Delay Buffer Select. Selects one of the eight taps in the CLK Delay Buffer based on PVT variation." "0,1,2,3,4,5,6,7" line.long 0x14 "REGS__SS_CFG__SSCFG_PHY_CTRL_6_REG,The PHY Control 6 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." bitfld.long 0x14 31. "BISTENABLE,Internal BIST operation enable. Enables the embedded BIST." "0,1" bitfld.long 0x14 30. "BISTSTART,Internal BIST start. Starts the embedded BIST operation." "0,1" newline hexmask.long.byte 0x14 24.--27. 1. "BISTMODE,Internal BIST mode Select. Select the embedded BIST mode of operation." hexmask.long.byte 0x14 0.--7. 1. "TESTCTRL,PHY test control: 8'b00010000 => Test EMMC IOs sink impedance 8'b00010001 => Test EMMC IOs source impedance 8'b00100000 => Test RX clock phases on data lines 8'b00110000 => Test TX clock phases on data lines 8'b01000000 => Test STRB clock.." rgroup.long 0x130++0x7 line.long 0x0 "REGS__SS_CFG__SSCFG_PHY_STAT_1_REG,The PHY Status 1 Register contains various fields to reflect the status of the Arasan eMMC/SD PHY ports. For detailed functionality of the Arasan eMMC/SD PHY status ports please refer to its specification listed in.." hexmask.long.byte 0x0 4.--7. 1. "RTRIM,CALIO Calibration Result. Holds the content of CALIO Impedance Calibration Result." bitfld.long 0x0 3. "BISTDONE,Internal BIST completed test cycle. Indicates that the embedded BIST has completed the test cycle." "0,1" newline bitfld.long 0x0 2. "EXR_NINST,External Resistor on CALIO absent. Indicates trim cycle started and external resistor is absent." "0,1" bitfld.long 0x0 1. "CALDONE,STATUS indicate that CALIO Calibration is completed successfully." "0,1" newline bitfld.long 0x0 0. "DLLRDY,DLL ready. Indicates that DLL loop is locked." "0,1" line.long 0x4 "REGS__SS_CFG__SSCFG_PHY_STAT_2_REG,The PHY Status 2 Register contains various fields to reflect the status of the Arasan eMMC/SD PHY ports. For detailed functionality of the Arasan eMMC/SD PHY status ports please refer to its specification listed in.." hexmask.long 0x4 0.--31. 1. "BISTSTATUS,Internal BIST data compare results. BIST cycle data comparison results." tree.end tree.end tree "MMCSD1" base ad:0x0 tree "MMCSD1_CTL_CFG (MMCSD1_CTL_CFG)" base ad:0x4FB0000 rgroup.word 0x0++0xF line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_sdma_sys_addr_lo,This register contains the Lower 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10." hexmask.word 0x0 0.--15. 1. "SDMA_ADDRESS,When Host Version 4 Enable is set to 0 in the Host Control 2 register DMA uses this register as system address in only 32-bit addressing mode. Auto CMD23 cannot be used with SDMA. When Host Version 4 Enable is set to 1 SDMA uses ADMA System.." line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_sdma_sys_addr_hi,This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10." hexmask.word 0x2 0.--15. 1. "SDMA_ADDRESS,This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10." line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_block_size,This register is used to configure the number of bytes in a data block" bitfld.word 0x4 12.--14. "SDMA_BUF_SIZE,To perform long DMA transfer System Address register shall be updated at every system boundary during DMA transfer. These bits specify the size of contiguous buffer in the system memory. The DMA transfer shall wait at the every boundary.." "0,1,2,3,4,5,6,7" newline hexmask.word 0x4 0.--11. 1. "XFER_BLK_SIZE,This field specifies the block size for block data transfers for CMD17 CMD18 CMD24 CMD25 and CMD53. It can be accessed only if no transaction is executing [i.e after a transaction has stopped]. Read operations during transfer return an.." line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_block_count,This register is used to configure the number of data blocks" hexmask.word 0x6 0.--15. 1. "XFER_BLK_CNT,Host Controller Version 4.10 extends block count to 32-bit [Refer to Section 1.15].Selection of either 16-bit Block Count register or 32-bit Block Count register is defined as follows: [1] If Host Version 4 Enable in the Host Control 2.." line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_argument1_lo,This register contains Lower bits of SD Command Argument" hexmask.word 0x8 0.--15. 1. "CMD_ARG1,The SD Command Argument is specified as bit23-8 of Command-Format." line.word 0xA "SDHC_WRAP__CTL_CFG__CTLCFG_argument1_hi,This register contains higher bits of SD Command Argument" hexmask.word 0xA 0.--15. 1. "CMD_ARG1,The SD Command Argument is specified as bit39-24 of Command-Format." line.word 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_transfer_mode,This register is used to control the operations of data transfers" bitfld.word 0xC 8. "RESP_INTR_DIS,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error sets this bit to 0 and waits Command Complete.." "0,1" newline bitfld.word 0xC 7. "RESP_ERR_CHK_ENA,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked.If Host Driver checks response error this bit is set to 0 and Response Interrupt.." "0,1" newline bitfld.word 0xC 6. "RESP_TYPE,When response error check is enabled this bit selects either R1 or R5 response types. Two types of response checks are supported: R1 for memory and R5 for SDIO." "0,1" newline bitfld.word 0xC 5. "MULTI_BLK_SEL,This bit enables multiple block data transfers." "0,1" newline bitfld.word 0xC 4. "DATA_XFER_DIR,This bit defines the direction of data transfers." "0,1" newline bitfld.word 0xC 2.--3. "AUTO_CMD_ENA,There are three methods to stop Multiple-block read and write operation. [1] Auto CMD12 Enable: Multiple-block read and write commands for memory require CMD12 to stop the operation. When this field is set to 01b the Host.." "0,1,2,3" newline bitfld.word 0xC 1. "BLK_CNT_ENA,This bit is used to enable the Block count register which is only relevant for multiple block transfers. When this bit is 0 the Block Count register is disabled which is useful in executing an infinite transfer." "0,1" newline bitfld.word 0xC 0. "DMA_ENA,DMA can be enabled only if DMA Support bit in the Capabilities register is set. If this bit is set to 1 a DMA operation shall begin when the HD writes to the upper byte of Command register [00Fh]." "0,1" line.word 0xE "SDHC_WRAP__CTL_CFG__CTLCFG_command,This register is used to program the Command for host controller" hexmask.word.byte 0xE 8.--13. 1. "CMD_INDEX,This bit shall be set to the command number [CMD0-63 ACMD0-63]." newline bitfld.word 0xE 6.--7. "CMD_TYPE,There are three types of special commands. Suspend Resume andAbort. These bits shall bet set to 00b for all other commands. Suspend Command: If the Suspend command succeeds the HC shall assume the SD Bus has been released and that it is.." "0,1,2,3" newline bitfld.word 0xE 5. "DATA_PRESENT,This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. If is set to 0 for the following: 1. Commands using only CMD line [ex. CMD52]. 2. Commands with no data transferbut using busy.." "0,1" newline bitfld.word 0xE 4. "CMD_INDEX_CHK_ENA,If this bit is set to 1 the HC shall check the index field in the response to see if it has the same value as the command index. If it is not it is reported as a Command Index Error. If this bit is set to 0 the Index field is not.." "0,1" newline bitfld.word 0xE 3. "CMD_CRC_CHK_ENA,If this bit is set to 1 the HC shall check the CRC field in the response. If an error is detected it is reported as a Command CRC Error. If this bit is set to 0 the CRC field is not checked." "0,1" newline bitfld.word 0xE 2. "SUB_CMD,This bit is added from Version 4.10 to distinguish a main command or sub command [Refer to Section 1.17]. When issuing a main com-mand this bit is set to 0 and when issuing a sub command this bit is set to 1. Setting of this bit is checked.." "0,1" newline bitfld.word 0xE 0.--1. "RESP_TYPE_SEL,Response Type Select." "0,1,2,3" rgroup.word 0x10++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_response,This register is used to store responses from SD Cards" hexmask.word 0x0 0.--15. 1. "CMD_RESP,R[] refers to a bit range within the response data as transmitted on the SD Bus REP[] refers to a bit range within the Response register." rgroup.long 0x20++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_data_port,This register is used to access internal buffer" hexmask.long 0x0 0.--31. 1. "BUF_RD_DATA,The Host Controller Buffer can be accessed through this 32-bit Data Port Register." rgroup.long 0x24++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_presentstate,The Host Driver can get status of the Host Controller from this 32-bit read-only register" bitfld.long 0x0 31. "UHS2_IF_DETECTION,This status indicates whether a card supports UHS-II IF. This status is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 regis-ter. UHS-II interface initialization is activated by setting SD Clock Enable in the.." "0,1" newline bitfld.long 0x0 30. "UHS2_IF_LANE_SYNC,This status indicates whether lane is synchronized in UHS-II mode. This status is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 register. On detecting UHS-II Interface [D31=1] Host Controller provides SYN.." "0,1" newline bitfld.long 0x0 29. "UHS2_DORMANT,This status indicates whether UHS-II Ianes enterDormant state. This function is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 register. On issuing GO_DORMAT_STATE com-mand Go Dormant Command [111b]; is set to Command.." "0,1" newline bitfld.long 0x0 28. "SUB_COMMAND_STS,The Command register and Response register are commonly used for main command and sub command. This status is used to distinguish which response error statuses main command or sub command indicated in the Error Interrupt Status.." "?,1: Sub Command Status 0" newline bitfld.long 0x0 27. "CMD_NOT_ISS_BY_ERR,Setting of this status indicates that a command cannot be issued due to an error except Auto CMD12 error. [Equivalent error status by Auto CMD12 error is defined as Command Not Issued By Auto CMD12 Error in the Auto CMD Error.." "?,1: Command cannot be issued 0" newline bitfld.long 0x0 24. "SDIF_CMDIN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 23. "SDIF_DAT3IN,This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[3]." "0,1" newline bitfld.long 0x0 22. "SDIF_DAT2IN,This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[2]." "0,1" newline bitfld.long 0x0 21. "SDIF_DAT1IN,This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[1]." "0,1" newline bitfld.long 0x0 20. "SDIF_DAT0IN,This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[0]." "0,1" newline bitfld.long 0x0 19. "WRITE_PROTECT,The Write Protect Switch is supported for memory and combo cards.This bit reflects the SDWP# pin." "0,1" newline bitfld.long 0x0 18. "CARD_DETECT,This bit reflects the inverse value of the SDCD# pin. '0' No Card present [SDCD# = 1] '1' Card present [SDCD# = 0]" "0,1" newline bitfld.long 0x0 17. "CARD_STATE_STABLE,This bit is used for testing. If it is 0 the Card Detect Pin Level is not stable. If this bit is set to 1 it means the Card Detect Pin Level is stable. The Software Reset For All in the Software Reset Register shall not affect this.." "0,1" newline bitfld.long 0x0 16. "CARD_INSERTED,This bit indicates whether a card has been inserted. Changing from 0 to 1 generates a Card Insertion interrupt in the Normal Interrupt Status register and changing from 1 to 0 generates a Card Removal Interrupt in the Normal Interrupt.." "0,1" newline bitfld.long 0x0 11. "BUF_RD_ENA,This status is used for non-DMA read transfers.This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1 readable data exists in the buffer. A change of this bit from 1 to 0 occurs when all the.." "0,1" newline bitfld.long 0x0 10. "BUF_WR_ENA,This status is used for non-DMA write transfers.This read only flag indicates if space is available for write data. If this bit is 1 data can be written to the buffer. A change of this bit from 1 to 0 occurs when all the block data is written.." "0,1" newline bitfld.long 0x0 9. "RD_XFER_ACTIVE,This status is used for detecting completion of a read transfer. This bit is set to 1 for either of the following conditions: After the end bit of the read command. When writing a 1 to continue Request in the Block.." "0,1" newline bitfld.long 0x0 8. "WR_XFER_ACTIVE,This status indicates a write transfer is active. If this bit is 0 it means no valid write data exists in the HC. This bit is set in either of the following cases: After the end bit of the write command. When writing a.." "0,1" newline bitfld.long 0x0 7. "SDIF_DAT7IN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 6. "SDIF_DAT6IN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 5. "SDIF_DAT5IN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 4. "SDIF_DAT4IN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 3. "RETUNING_REQ,Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data. This bit is.." "0,1" newline bitfld.long 0x0 2. "DATA_LINE_ACTIVE,This bit indicates whether one of the DAT line on SD bus is in use." "0,1" newline bitfld.long 0x0 1. "INHIBIT_DAT,This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1. If this bit is 0 it indicates the HC can issue the next SD command. Commands with busy signal belong to Command Inhibit [DAT] [ex. R1b R5b.." "0,1" newline bitfld.long 0x0 0. "INHIBIT_CMD,SD Mode If this bit is 0 it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line. This bit is set immediately after the Command register [00Fh] is written. This bit is cleared when the command response is.." "?,1: Host Controller is not ready to issue a com-mand.." rgroup.byte 0x28++0x3 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_host_control1,This register is used to program DMA modes. LED Control. Data Transfer Width. High Speed Enable. Card detect test level and signal selection" bitfld.byte 0x0 7. "CD_SIG_SEL,This bit selects source for card detection. '0' SDCD# is selected [for normal use] '1' The card detect test level is selected" "0,1" newline bitfld.byte 0x0 6. "CD_TEST_LEVEL,This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. Generates [card ins or card removal] interrupt when the normal int sts enable bit is set. '0' No Card '1' Card Inserted" "0,1" newline bitfld.byte 0x0 5. "EXT_DATA_WIDTH,This bit controls 8-bit bus width mode for embedded device. Support of this function is indicated in 8-bit Support for Embedded Device in the Capabilities register. If a device supports 8-bit bus mode this bit may be set to 1. If this bit.." "0,1" newline bitfld.byte 0x0 3.--4. "DMA_SELECT,This field is used to select DMA type. The Host Driver shall check support of DMA modes by referring the Capabilities register. Selected DMA is enabled by DMA Enable of the Transfer Mode register in SD mode and DMA Enable of UHS-II Transfer.." "0: SDMA is selected 01,?,?,?" newline bitfld.byte 0x0 2. "HIGH_SPEED_ENA,This bit is optional. Before setting this bit the HD shall check the High Speed Support in the capabilities register. If this bit is set to 0 [default] the HC outputs CMD line and DAT lines at the falling edge of the SD clock [up to.." "0,1" newline bitfld.byte 0x0 1. "DATA_WIDTH,This bit selects the data width of the HC. The HD shall select it to match the data width of the SD card. This bit is not effective in UHS-II mode." "0,1" newline bitfld.byte 0x0 0. "LED_CONTROL,This bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue multiple SD commands this bit can be set during all transactions. It is not necessary to change for each.." "0,1" line.byte 0x1 "SDHC_WRAP__CTL_CFG__CTLCFG_power_control,This register is used to program the SD Bus power and voltage level" bitfld.byte 0x1 5.--7. "UHS2_VOLTAGE,This field determines supply voltage range to VDD2. This field can be set to 101b if 1.8V VDD2 Support in the Capabilities register is set to 1. '000' VDD2 Not supported '001'- '011' Reserved '100' Reserved for 1.2V.." "0,1,2,3,4,5,6,7" newline bitfld.byte 0x1 4. "UHS2_POWER,Setting this bit enables providing VDD2. '0' Power Off '1' Power On" "0,1" newline bitfld.byte 0x1 1.--3. "SD_BUS_VOLTAGE,By setting these bits the HD selects the voltage level for the SD card. Before setting this register the HD shall check the voltage support bits in the capabilities register. If an unsupported voltage is selected the Host System shall.." "0,1,2,3,4,5,6,7" newline bitfld.byte 0x1 0. "SD_BUS_POWER,Before setting this bit the SD host driver shall set SD Bus Voltage Select. If the HC detects the No Card State this bit shall be cleared. If this bit is cleared the Host Control-ler should immediately stop driving CMD and DAT[3:0].." "0,1" line.byte 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_block_gap_control,This register is used to program the block gap request. read wait control and interrupt at block gap" bitfld.byte 0x2 7. "BOOT_ACK_ENA,To check for the boot acknowledge in boot operation." "0,1" newline bitfld.byte 0x2 6. "ALT_BOOT_MODE,To start boot code access in alternative mode." "0,1" newline bitfld.byte 0x2 5. "BOOT_ENABLE,To start boot code access." "0,1" newline bitfld.byte 0x2 4. "SPI_MODE,SPI mode enable bit." "0,1" newline bitfld.byte 0x2 3. "INTRPT_AT_BLK_GAP,This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. If the SD card cannot signal an interrupt.." "0,1" newline bitfld.byte 0x2 2. "RDWAIT_CTRL,The read wait function is optional for SDIO cards. If the card supports read wait set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise the HC has to stop the SD clock to hold read data which.." "0,1" newline bitfld.byte 0x2 1. "CONTINUE,This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request. To cancel stop at the block gap set Stop At block Gap Request to 0 and set this bit to restart the transfer. The Host Controller automatically.." "0,1" newline bitfld.byte 0x2 0. "STOP_AT_BLK_GAP,This bit is used to stop executing a transaction at the next block gap for non- DMA SDMA and ADMA transfers. Until the transfer complete is set to 1 indicating a transfer completion the HD shall leave this bit set to 1. Clearing both the.." "0,1" line.byte 0x3 "SDHC_WRAP__CTL_CFG__CTLCFG_wakeup_control,This register is used to program the wakeup functionality" bitfld.byte 0x3 2. "CARD_REMOVAL,This bit enables wakeup event via Card removal assertion in the Normal Interrupt Status register.FN_WUS [Wake up Support] in CIS does not affect this bit." "0,1" newline bitfld.byte 0x3 1. "CARD_INSERTION,This bit enables wakeup event via Card Insertion assertion in the Normal Interrupt Status register.FN_WUS [Wake up Support] in CIS does not affect this bit." "0,1" newline bitfld.byte 0x3 0. "CARD_INTERRUPT,This bit enables wakeup event via Card Interrupt assertion in the Normal Interrupt Status register.This bit can be set to 1 if FN_WUS [Wake Up Support] in CIS is set to 1." "0,1" rgroup.word 0x2C++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_clock_control,This register is used to program the Clock frequency select. generator select. Clock enable. Internal Clock state fields" hexmask.word.byte 0x0 8.--15. 1. "SDCLK_FRQSEL,This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly; rather this register holds the divisor of the Base Clock Frequency For SD clock in the capabilities register. Only the following.." newline bitfld.word 0x0 6.--7. "SDCLK_FRQSEL_UPBITS,Bit 07-06 is assigned to bit 09-08 of clock divider in SDCLK Frequency Select." "0,1,2,3" newline bitfld.word 0x0 5. "CLKGEN_SEL,This bit is used to select the clock generator mode in SDCLK Frequency Select. If the Programmable Clock Mode is supported [non-zero value is set to Clock Multiplier in the Capabilities register] this bit attribute is RW and if not.." "0,1" newline bitfld.word 0x0 3. "PLL_ENA,This bit is added from Version 4.10 for Host Controller using PLL. This feature allows Host Controller to initialize clock generator in two steps: by Internal Clock Enable and PLL Enable and to minimize output latency [ex. SDCLK/RCLK D0lane].." "0,1" newline bitfld.word 0x0 2. "SD_CLK_ENA,The HC shall stop SDCLK when writing this bit to 0. SDCLK frequency Select can be changed when this bit is 0. Then the HC shall maintain the same clock frequency until SDCLK is stopped [Stop at SDCLK = 0]. If the HC detects the No Card state .." "0,1" newline rbitfld.word 0x0 1. "INT_CLK_STABLE,This bit is set to 1 when SD clock is stable after writing to Internal Clock Enable in this register to 1. The SD Host Driver shall wait to set SD Clock Enable until this bit is set to 1. Note: This is useful when using PLL for a clock.." "0,1" newline bitfld.word 0x0 0. "INT_CLK_ENA,This bit is set to 0 when the HD is not using the HC or the HC awaits a wakeup event. The HC should stop its internal clock to go very low power state. Still registers shall be able to be read and written. Clock starts to oscillate when this.." "0,1" rgroup.byte 0x2E++0x1 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_timeout_control,The register sets the Data Timeout counter value" hexmask.byte 0x0 0.--3. 1. "COUNTER_VALUE,This value determines the interval by which DAT line time-outs are detected. Refer to the Data Time-out Error in the Error Interrupt Status register for information on factors that dictate time-out generation. Time-out clock frequency will.." line.byte 0x1 "SDHC_WRAP__CTL_CFG__CTLCFG_software_reset,This register is used to program the software reset for data. command and for all" bitfld.byte 0x1 2. "SWRST_FOR_DAT,Only part of data circuit is reset. The following registers and bits are cleared by this bit: Buffer Data Port Register: Buffer is cleared and Initialized. Present State register: Buffer read Enable Buffer write.." "0,1" newline bitfld.byte 0x1 1. "SWRST_FOR_CMD,Software Reset For CMD Line Only part of command circuit is reset to be able to issue a command. From Version 4.10 this bit is also used to initialize UHS-II command circuit. This reset is effective only command issuing circuit [including.." "0,1" newline bitfld.byte 0x1 0. "SWRST_FOR_ALL,This reset affects the entire HC except for the card detection circuit. Register bits of type ROC RW RW1C RWAC are cleared to 0. During its initialization the HD shall set this bit to 1 to reset the HC. The HC shall reset this bit to 0.." "0,1" rgroup.word 0x30++0xB line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sts,This register gives the status of all the interrupts" rbitfld.word 0x0 15. "ERROR_INTR,If any of the bits in the Error Interrupt Status Register are set then this bit is set. Therefore the HD can test for an error by checking this bit first. In UHS-II mode is enabled if any of the bits in the UHS-II Error.." "0,1" newline bitfld.word 0x0 14. "BOOT_COMPLETE,This status is set if the boot operation gets terminated. '0' Boot operation is not terminated '1' Boot operation is terminated" "0,1" newline bitfld.word 0x0 13. "RCV_BOOT_ACK,This status is set if the boot acknowledge is received from device. '0' Boot ack not recieved '1' Boot ack is recieved" "0,1" newline rbitfld.word 0x0 12. "RETUNING_EVENT,This status is set if Re-Tuning Request in the Present State register changes from 0 to 1. Host Controller requests Host Driver to perform re-tuning for next data transfer. Current data transfer [not large block count] can be completed.." "0,1" newline rbitfld.word 0x0 11. "INTC,This status is set if INT_C is enabled and INT_C# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_C interrupt factor." "0,1" newline rbitfld.word 0x0 10. "INTB,This status is set if INT_B is enabled and INT_B# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_B interrupt factor." "0,1" newline rbitfld.word 0x0 9. "INTA,This status is set if INT_A is enabled and INT_A# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_A interrupt factor. NOTE : INT_A INT_B and INT_C are to be implemented based on the.." "0,1" newline rbitfld.word 0x0 8. "CARD_INTR,When this status has been set and the Host Driver needs to start this interrupt service Card Interrupt Status Enable in the Normal Interrupt Status Enable register may be set to 0 in order to clear the card interrupt status latched in the Host.." "?,1: bit mode" newline bitfld.word 0x0 7. "CARD_REM,This status is set if the Card Inserted in the Present State register changes from 1 to 0. When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the card.." "0,1" newline bitfld.word 0x0 6. "CARD_INS,This status is set if the Card Inserted in the Present State register changes from 0 to 1.When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the card.." "0,1" newline bitfld.word 0x0 5. "BUF_RD_READY,This status is set if the Buffer Read Enable changes from 0 to 1. Buffer Read Ready is set to 1 for every CMD19 execution in tuning procedure.In UHS-II mode this bit is set at FC [Flow Control] unit basis. '0' Not ready to.." "0,1" newline bitfld.word 0x0 4. "BUF_WR_READY,This status is set if the Buffer Write Enable changes from 0 to 1.In UHS-II mode this bit is set at FC [Flow Control] unit basis. '0' Not ready to write to buffer '1' Ready to write to buffer" "0,1" newline bitfld.word 0x0 3. "DMA_INTERRUPT,This status is set if the HC detects the Host DMA Buffer Boundary in the Block Size regiser. '0' No DMA Interrupt '1' DMA Interrupt is generated" "0,1" newline bitfld.word 0x0 2. "BLK_GAP_EVENT,If the Stop At Block Gap Request in the BlockGap Control Register is set this bit is set. Read Transaction: This bit is set at the falling edge of the DAT Line Active Status [When the transaction is stopped at SD Bus timing. The Read.." "0,1" newline bitfld.word 0x0 1. "XFER_COMPLETE,This bit is set when a read / write transaction is completed. SD Mode Read Transaction: This bit is set at the falling edge of Read Transfer Active Status. There are two cases in which the Interrupt is generated. The first is.." "?,1: Command execution is completed 0" newline bitfld.word 0x0 0. "CMD_COMPLETE,SD Mode This bit is set when we get the end bit of the command response [Except Auto CMD12 and Auto CMD23] Note: Command Time-out Error has higher priority than Command Complete. If both are set to 1 it can be considered that the.." "0,1" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sts,This register gives the status of the error interrupts" bitfld.word 0x2 12. "HOST,Occurs when detecting ERROR in m_hresp[dma transaction]" "0,1" newline bitfld.word 0x2 11. "RESP,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to 1 in the Transfer Mode register Host Controller Checks R1 or.." "0,1" newline bitfld.word 0x2 10. "TUNING,This bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure [Occurrence of an error during tuning procedure is indicated by Sampling Select]. By detecting Tuning Error Host Driver needs to abort a.." "0,1" newline bitfld.word 0x2 9. "ADMA,This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register." "0,1" newline bitfld.word 0x2 8. "AUTO_CMD,Auto CMD12 and Auto CMD23 use this error status.This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. D07 is effective in case of Auto CMD12. Auto CMD Error Status register is.." "0,1" newline bitfld.word 0x2 7. "CURR_LIMIT,By setting the SD Bus Power bit in the Power Control Register the HC is requested to supply power for the SD Bus. If the HC supports the Current Limit Function it can be protected from an Illegal card by stopping power supply to the card in.." "0,1" newline bitfld.word 0x2 6. "DATA_ENDBIT,Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status." "0,1" newline bitfld.word 0x2 5. "DATA_CRC,Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than 010." "0,1" newline bitfld.word 0x2 4. "DATA_TIMEOUT,Occurs when detecting one of following timeout conditions: 1. Busy Timeout for R1b R5b type. 2. Busy Timeout after Write CRC status 3. Write CRC status Timeout 4. Read Data Timeout." "0,1" newline bitfld.word 0x2 3. "CMD_INDEX,Occurs if a Command Index error occurs in the Command Response." "0,1" newline bitfld.word 0x2 2. "CMD_ENDBIT,Occurs when detecting that the end bit of a command response is 0." "0,1" newline bitfld.word 0x2 1. "CMD_CRC,Command CRC Error is generated in two cases. 1. If a response is returned and the Command Time-out Error is set to 0 this bit is set to 1 when detecting a CRT error in the command response 2. The HC detects a CMD line conflict by.." "0,1" newline bitfld.word 0x2 0. "CMD_TIMEOUT,Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command. If the HC detects a CMD line conflict in which case Command CRC Error shall also be set. This bit shall be set without waiting for 64 SDCLK.." "0,1" line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sts_ena,This register is used to enable the normal interrupt status register fields" rbitfld.word 0x4 15. "BIT15_FIXED0,The HC shall control error Interrupts using the Error Interrupt Status Enable register." "0,1" newline bitfld.word 0x4 14. "BOOT_COMPLETE,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 13. "RCV_BOOT_ACK,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 12. "RETUNING_EVENT,0 - Masked 1 - Enabled" "0: Masked 1,?" newline bitfld.word 0x4 11. "INTC,If this bit is set to 0 the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to INT_C pin are cleared to prevent.." "0,1" newline bitfld.word 0x4 10. "INTB,If this bit is set to 0 the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to INT_B pin are cleared to prevent.." "0,1" newline bitfld.word 0x4 9. "INTA,If this bit is set to 0 the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to INT_A pin are cleared to prevent.." "0,1" newline bitfld.word 0x4 8. "CARD_INTERRUPT,If this bit is set to 0 the HC shall clear Interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. The HD may clear the Card Interrupt Status Enable before.." "0,1" newline bitfld.word 0x4 7. "CARD_REMOVAL,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 6. "CARD_INSERTION,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 5. "BUF_RD_READY,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 4. "BUF_WR_READY,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 3. "DMA_INTERRUPT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 2. "BLK_GAP_EVENT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 1. "XFER_COMPLETE,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 0. "CMD_COMPLETE,'0' Masked '1' Enabled" "0,1" line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sts_ena,This register is used to enable the Error Interrupt Status register fields" bitfld.word 0x6 13.--14. "VENDOR_SPECIFIC,N/A" "0,1,2,3" newline bitfld.word 0x6 12. "HOST,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 11. "RESP,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 10. "TUNING,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 9. "ADMA,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 8. "AUTO_CMD,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 7. "CURR_LIMIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 6. "DATA_ENDBIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 5. "DATA_CRC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 4. "DATA_TIMEOUT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 3. "CMD_INDEX,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 2. "CMD_ENDBIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 1. "CMD_CRC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 0. "CMD_TIMEOUT,'0' Masked '1' Enabled" "0,1" line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sig_ena,This register is used to enable the Normal Interrupt Signal register" rbitfld.word 0x8 15. "BIT15_FIXED0,The HD shall control error Interrupts using the Error Interrupt Signal Enable register." "0,1" newline bitfld.word 0x8 14. "BOOT_COMPLETE,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 13. "RCV_BOOT_ACK,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 12. "RETUNING_EVENT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 11. "INTC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 10. "INTB,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 9. "INTA,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 8. "CARD_INTERRUPT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 7. "CARD_REMOVAL,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 6. "CARD_INSERTION,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 5. "BUF_RD_READY,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 4. "BUF_WR_READY,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 3. "DMA_INTERRUPT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 2. "BLK_GAP_EVENT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 1. "XFER_COMPLETE,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 0. "CMD_COMPLETE,'0' Masked '1' Enabled" "0,1" line.word 0xA "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sig_ena,This register is used to enable Error Interrupt Signal register" bitfld.word 0xA 13.--14. "VENDOR_SPECIFIC,N/A" "0,1,2,3" newline bitfld.word 0xA 12. "HOST,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 11. "RESP,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 10. "TUNING,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 9. "ADMA,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 8. "AUTO_CMD,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 7. "CURR_LIMIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 6. "DATA_ENDBIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 5. "DATA_CRC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 4. "DATA_TIMEOUT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 3. "CMD_INDEX,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 2. "CMD_ENDBIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 1. "CMD_CRC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 0. "CMD_TIMEOUT,'0' Masked '1' Enabled" "0,1" rgroup.word 0x3C++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_autocmd_err_sts,This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD 23" bitfld.word 0x0 7. "CMD_NOT_ISSUED,Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 error [D04- D01] in this register. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23." "0,1" newline bitfld.word 0x0 5. "RESP,This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or Auto CMD23. This status should be ignored if any bit of D00 to D04 is set to 1." "0,1" newline bitfld.word 0x0 4. "INDEX,Occurs if the Command Index error occurs in response to a command." "0,1" newline bitfld.word 0x0 3. "ENDBIT,Occurs when detecting that the end bit of command response is 0." "0,1" newline bitfld.word 0x0 2. "CRC,Occurs when detecting a CRC error in the command response." "0,1" newline bitfld.word 0x0 1. "TIMEOUT,Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command.If this bit is set to 1 the other error status bits [D04 - D02] are meaningless." "0,1" newline bitfld.word 0x0 0. "ACMD12_NOT_EXEC,If memory multiple block data transfer is not started due to command error this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the HC cannot issue Auto CMD12 to stop memory multiple block.." "0,1" rgroup.word 0x3E++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_host_control2,This register is used to program UHS Select Mode.UHS Select Mode.Driver Strength Select.Execute Tuning.Sampling Clock Select.Asynchronous Interrupt Enable and Preset value enable" bitfld.word 0x0 15. "PRESET_VALUE_ENA,Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation it is difficult to determine these parameters in the Standard Host Driver. When Preset.." "0,1" newline bitfld.word 0x0 14. "ASYNCH_INTR_ENA,This bit can be set to 1 if a card support asynchronous interrupt and Asynchronous Interrupt Support is set to 1 in the Capabilities register. Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode [and zero is.." "0,1" newline bitfld.word 0x0 13. "BIT64_ADDRESSING,This field is effective when Host Version 4.00 Enable is set to 1. Host Controller selects either of 32-bit or 64-bit addressing modes to access system memory. Whether 32-bit or 64-bit is determined by OS installed in a host.." "0,1" newline bitfld.word 0x0 12. "HOST_VER40_ENA,This bit selects either Version 3.00 compatible mode or Ver4.mode. In Version 4.00 support of 64-bit System Addressing is modified. All DMAs support 64-bit System Addressing. UHS-II supported Host Driver shall enable this bit. In Version.." "0,1" newline bitfld.word 0x0 11. "CMD23_ENA,In memory card initialization Host Driver Version 4.10 checks whether card supports CMD23 by checking a bit SCR[33]. If the card supports CMD23 [SCR[33]=1] this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3.." "0,1" newline bitfld.word 0x0 10. "ADMA2_LEN_MODE,This bit selects one of ADMA2 Length Modes either 16-bit or 26-bit." "0,1" newline bitfld.word 0x0 9. "DRIVER_STRENGTH2,This is the programmed Drive STrength output and Bit[2] of the sdhccore_drivestrength value." "0,1" newline bitfld.word 0x0 8. "UHS2_INTF_ENABLE,This bit is used to enable UHS-II Interface. Before trying to start UHS-II initialization this bit shall be set to 1. Before trying to start SD mode initialization this bit shall be set to 0. This bit is used to enable UHS-II IF.." "0,1" newline bitfld.word 0x0 7. "SAMPLING_CLK_SELECT,This bit is set by tuning procedure when Execute Tuning is cleared. Writing 1 to this bit is meaningless and ignored. Setting 1 means that tuning is completed successfully and setting 0 means that tuning is failed. Host Controller.." "0,1" newline bitfld.word 0x0 6. "EXECUTE_TUNING,This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to Sampling Clock Select. Tuning procedure is aborted by writing 0 for more detail about tuning.." "0,1" newline bitfld.word 0x0 4.--5. "DRIVER_STRENGTH1,Host Controller output driver in 1.8V signaling is selected by this bit. In 3.3V signaling this field is not effective. This field can be set depends on Driver Type A C and D support bits in the Capabilities register. This bit depends.." "0,1,2,3" newline bitfld.word 0x0 3. "V1P8_SIGNAL_ENA,This bit controls voltage regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V. 1.8V regulator output shall be stable within.." "?,1: SDR50" newline bitfld.word 0x0 0.--2. "UHS_MODE_SELECT,This field is used to select one of UHS-I modes or UHS-II mode.In case of UHS-I mode this field is effective when 1.8V Signal-ing Enable is set to 1. In case of UHS-II mode 1.8V Signaling Enable shall be set to 0. Setting of this field.." "0,1,2,3,4,5,6,7" rgroup.quad 0x40++0xF line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_capabilities,This register provides the HD with information specific to the HC implementation. The HC may implement these values as fixed or loaded from flash memory during power on initializa-tion." bitfld.quad 0x0 63. "HS400_SUPPORT,1 HS400 is Supported 0 HS400 is Not Supported" "0,1" newline bitfld.quad 0x0 60. "VDD2_1P8_SUPPORT,This field indicates that support of VDD2 on Host system." "0,1" newline bitfld.quad 0x0 59. "ADMA3_SUPPORT,This field indicates that support of ADMA3 on Host Controller." "0,1" newline bitfld.quad 0x0 57. "SPI_BLK_MODE,This field indicates whether SPI Block Mode is supported or not." "0,1" newline bitfld.quad 0x0 56. "SPI_SUPPORT,This field indicates whether SPI Mode is supported or not." "0,1" newline hexmask.quad.byte 0x0 48.--55. 1. "CLOCK_MULTIPLIER,This field indicates clock multiplier value of programmable clock generator. Refer to Clock Control register. Setting 00h means that Host Controller does not support programmable clock generator. 'FF' Clock Multiplier M = 256.." newline bitfld.quad 0x0 46.--47. "RETUNING_MODES,This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver. '00' Mode 1 '01' Mode 2 '10' Mode 3 '11' Reserved. There are two.." "0,1,2,3" newline bitfld.quad 0x0 45. "TUNING_FOR_SDR50,If this bit is set to 1 this Host Controller requires tuning to operate SDR50. [Tuning is always required to operate SDR104]. '0' '1'" "0,1" newline hexmask.quad.byte 0x0 40.--43. 1. "RETUNING_TIMER_CNT,This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. 0h - Get information via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds ------.." newline bitfld.quad 0x0 38. "DRIVERD_SUPPORT,This bit indicates support of Driver Type D for 1.8 Signaling. '0' Driver Type D is Not supported '1' Driver Type D is supported" "0,1" newline bitfld.quad 0x0 37. "DRIVERC_SUPPORT,This bit indicates support of Driver Type C for 1.8 Signaling. '0' Driver Type C is Not supported '1' Driver Type C is supported" "0,1" newline bitfld.quad 0x0 36. "DRIVERA_SUPPORT,This bit indicates support of Driver Type A for 1.8 Signaling. '0' Driver Type A is Not supported '1' Driver Type A is supported" "0,1" newline bitfld.quad 0x0 35. "UHS2_SUPPORT,This bit indicates whether Host controller supports UHS-II. If this bit is set to 1 1.8V VDD2 Support shall be set to 1 [Host Sys- tem shall support VDD2 power supply]. 1 UHS-II is Supported 0 UHS-II is Not Supported" "0,1" newline bitfld.quad 0x0 34. "DDR50_SUPPORT,This bit indicates whether DDR50 is supported or not." "0,1" newline bitfld.quad 0x0 33. "SDR104_SUPPORT,This bit indicates whether SDR104 is supported or not.SDR104 requires tuning." "0,1" newline bitfld.quad 0x0 32. "SDR50_SUPPORT,If SDR104 is supported this bit shall be set to 1. Bit 40 indicates whether SDR50 requires tuning or not." "0,1" newline bitfld.quad 0x0 30.--31. "SLOT_TYPE,This field indicates usage of a slot by a specific Host System. [A host controller register set is defined perslot.] Embedded slot for one device [01b] means that only one non-removable device is connected to a SD bus slot. Shared Bus Slot.." "0,1,2,3" newline bitfld.quad 0x0 29. "ASYNCH_INTR_SUPPORT,Refer to SDIO Specification Version 3.00 about asynchronous interrupt." "0,1" newline bitfld.quad 0x0 28. "ADDR_64BIT_SUPPORT_V3,IMeaning of this bit is different depends on Versions [Refer to Table 2-35 for more details]. Host Controller Version 3.00 and Ver4.10 use this bit as 64-bit System Address support for V3 mode. Host Con- troller Version 4.00 uses.." "0,1" newline bitfld.quad 0x0 27. "ADDR_64BIT_SUPPORT_V4,This bit is added from Version 4.10. Set-ting 1 to this bit indicates that the Host Controller supports 64-bit System Addressing of Version 4 mode [Refer to Table 2-35 for the summary of 64-bit sys-tem address support].. When.." "0,1" newline bitfld.quad 0x0 26. "VOLT_1P8_SUPPORT,This bit indicates whether the HC supports 1.8V." "0,1" newline bitfld.quad 0x0 25. "VOLT_3P0_SUPPORT,This bit indicates whether the HC supports 3.0V." "0,1" newline bitfld.quad 0x0 24. "VOLT_3P3_SUPPORT,This bit indicates whether the HC supports 3.3V." "0,1" newline bitfld.quad 0x0 23. "SUSP_RES_SUPPORT,This bit indicates whether the HC supports Suspend / Resume functionality. If this bit is 0 the Suspend and Resume mechanism are not supported and the HD shall not issue either Suspend / Resume commands." "0,1" newline bitfld.quad 0x0 22. "SDMA_SUPPORT,This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly.Version 4.10 Host Controller shall support SDMA if ADMA2 is supported." "0,1" newline bitfld.quad 0x0 21. "HIGH_SPEED_SUPPORT,This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25Mhz to 50 Mhz [for SD]/ 20MHz to 52MHz [for MMC]." "0,1" newline bitfld.quad 0x0 19. "ADMA2_SUPPORT,'0' ADMA2 Not Supported '1' ADMA2 Supported" "0,1" newline bitfld.quad 0x0 18. "BUS_8BIT_SUPPORT,This bit indicates whether the Host Controller is capable of using 8-bit bus width mode. This bit is not effective when Slot Type is set to 10b. In this case refer to Bus Width Preset in the Shared Bus resister." "0,1" newline bitfld.quad 0x0 16.--17. "MAX_BLK_LENGTH,This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall transfer this block size without wait cycles. Three sizes can be defined as indicated below." "0,1,2,3" newline hexmask.quad.byte 0x0 8.--15. 1. "BASE_CLK_FREQ,[1]6-bit Base Clock Frequency: This mode is supported by the Host Controller Version 1.00 and 2.00. Upper 2-bit is not effective and always 0. Unit values are 1MHz. The supported clock range is 10MHz to 63MHz. '11xx xxxxb' Not.." newline bitfld.quad 0x0 7. "TIMEOUT_CLK_UNIT,This bit shows the unit of base clock frequency used to detect Data Timeout Error." "0,1" newline hexmask.quad.byte 0x0 0.--5. 1. "TIMEOUT_CLK_FREQ,This bit shows the base clock frequency used to detect Data Timeout Error. '000000' Get Information via another method 'not 0' 1KHz to 63KHz/1MHz to 63MHz" line.quad 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_max_current_cap,This register indicates maximum current capability for each voltage" hexmask.quad.byte 0x8 32.--39. 1. "VDD2_1P8V,Maximum Current for 1.8V VDD2" newline hexmask.quad.byte 0x8 16.--23. 1. "VDD1_1P8V,Maximum Current for 1.8V VDD1" newline hexmask.quad.byte 0x8 8.--15. 1. "VDD1_3P0V,Maximum Current for 3.0V VDD1" newline hexmask.quad.byte 0x8 0.--7. 1. "VDD1_3P3V,Maximum Current for 3.3V VDD1" rgroup.word 0x50++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_force_evnt_ACMD_Err_Sts,This register is not physically implemented. rather it is an address where Auto CMD Error Status register can be written." bitfld.word 0x0 7. "CMD_NOT_ISS,Force Event for Command Not Issued by AUTO CMD12 Error." "0,1" newline bitfld.word 0x0 5. "RESP,Force Event for AUTO CMD Response Error.." "0,1" newline bitfld.word 0x0 4. "INDEX,Force Event for AUTO CMD Index Error.." "0,1" newline bitfld.word 0x0 3. "ENDBIT,Force Event for AUTO CMD End Bit Error." "0,1" newline bitfld.word 0x0 2. "CRC,Force Event for AUTO CMD Timeout Error." "0,1" newline bitfld.word 0x0 1. "TIMEOUT,Force Event for AUTO CMD Timeout Error." "0,1" newline bitfld.word 0x0 0. "ACMD_NOT_EXEC,Force Event for AUTO CMD12 Not Executed." "0,1" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_force_evnt_Err_Int_Sts,This register is not physically implemented. rather it is an address where Error Interrupt Status register can be written." bitfld.word 0x2 12. "HOST,Force Event for Host Error" "0,1" newline bitfld.word 0x2 11. "RESP,Force Event for Response Error" "0,1" newline bitfld.word 0x2 10. "TUNING,Force Event for Tuning Error." "0,1" newline bitfld.word 0x2 9. "ADMA,Force Event for ADMA Error." "0,1" newline bitfld.word 0x2 8. "AUTO_CMD,Force Event for Auto CMD Error." "0,1" newline bitfld.word 0x2 7. "CURR_LIM,Force Event for Current Limit Error." "0,1" newline bitfld.word 0x2 6. "DAT_ENDBIT,Force Event for Data End Bit Error." "0,1" newline bitfld.word 0x2 5. "DAT_CRC,Force Event for Data CRC Error." "0,1" newline bitfld.word 0x2 4. "DAT_TIMEOUT,Force Event for Data Timeout Error." "0,1" newline bitfld.word 0x2 3. "CMD_INDEX,Force Event for Command Index Error" "0,1" newline bitfld.word 0x2 2. "CMD_ENDBIT,Force Event for Command End Bit Error." "0,1" newline bitfld.word 0x2 1. "CMD_CRC,Force Event for Command CRC Error." "0,1" newline bitfld.word 0x2 0. "CMD_TIMEOUT,Force Event for CMD Timeout Error." "0,1" rgroup.byte 0x54++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_adma_err_status,When the ADMA Error interrupt occur. this register holds the ADMA State in ADMA Error States field and ADMA System Address holds address around the error descriptor" bitfld.byte 0x0 2. "ADMA_LENGTH_ERR,This error occurs in the following 2 cases. While Block Count Enable being set the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length. Total data length can not be.." "0,1" newline bitfld.byte 0x0 0.--1. "ADMA_ERR_STATE,This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates 10 because ADMA never stops in this state. D01 D00 : ADMA Error State when error occurred Contents of SYS_SDR.." "0: ADMA Error State when error occurred Contents of..,?,?,?" rgroup.quad 0x58++0x7 line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_adma_sys_address,This register contains the physical address used for ADMA data transfer" hexmask.quad 0x0 0.--63. 1. "ADMA_ADDR,The 32-bit addressing Host Driver uses lower 32-bit of this register [upper 32-bit should be set to 0] and shall program Descriptor Table on 32-bit boundary andset 32-bit boundary address to this register. DMA2/3 ignores lower 2-bit of this.." rgroup.word 0x60++0xF line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value0,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x0 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x0 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x0 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value1,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x2 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x2 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x2 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value2,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x4 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x4 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x4 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value3,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x6 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x6 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x6 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value4,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x8 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x8 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x8 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0xA "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value5,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0xA 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0xA 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0xA 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value6,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0xC 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0xC 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0xC 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0xE "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value7,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0xE 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0xE 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0xE 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." rgroup.word 0x72++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value8,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x0 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x0 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x0 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value10,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x2 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x2 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x2 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." rgroup.quad 0x78++0x7 line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_adma3_desc_address,The start address of Integrated DMA Descriptor is set to this register." hexmask.quad 0x0 0.--63. 1. "INTG_DESC_ADDR,The start address of Integrated DMA Descriptor is set to this register. Writing to a specific address starts ADMA3 depends on 32-bit/64-bit address-ing. The ADMA3 fetches one Descriptor Address and increments this field to indicate the.." rgroup.word 0x80++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_block_size,This register is used to configure the number of bytes in a data block" bitfld.word 0x0 12.--14. "SDMA_BUF_BOUNDARY,When system memory is managed by paging SDMA data transfer is performed in unit of paging. A page size of sys-tem memory management is set to this field. Host Controller generates the DMA Interrupt at the page boundary and.." "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--11. 1. "XFER_BLK_SIZE,This register specifies the block size of data packet. SD Memory Card uses a fixed block size of 512 bytes. Vari-able block size may be used for SDIO. The maximum value is 2048 Bytes because CRC16 covers up to 2048 bytes. This register is.." rgroup.long 0x84++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_block_count,This register is used to configure the number of data blocks" hexmask.long 0x0 0.--31. 1. "XFER_BLK_COUNT,This register is effective when Data Present is set to 1 in UHS-II Command register and is enabled when Block Count Enable is set to 1 and Block / Byte Mode is set to 0 in the UHS-II Transfer Mode register. Data transfer stops when the.." rgroup.byte 0x88++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_command_pkt,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes. The command length varies depends on a Command Packet type. The length is specified by the UHS-II Command register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,UHS-II Command Packet image is set to this register.The command length varies depends on a Command Packet type." rgroup.word 0x9C++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_xfer_mode,This register is used to control the operations of data transfers" bitfld.word 0x0 15. "DUPLEX_SELECT,Use of 2 lane half duplex mode is determined by Host Driver." "0,1" newline bitfld.word 0x0 14. "EBSY_WAIT,This bit is set when issuing a command which is accompanied by EBSY packet to indicate end of command execution. Busy is expected for CCMD with R1b/R5b type and DCMD with data transfer.If this bit is set to 1 Host Controller waits receiving of.." "0,1" newline bitfld.word 0x0 8. "RESP_INTR_DIS,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error sets this bit to 0 and waits Command.." "0,1" newline bitfld.word 0x0 7. "RESP_ERR_CHK_ENA,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver.Only R1 or R5 can be checked. If Host Driver checks response error this bit is set to 0 and Response.." "0,1" newline bitfld.word 0x0 6. "RESP_TYPE,When response error check is enabled this bit selects either R1 or R5 response types. Two types of response checks are supported: R1 for memory and R5 for SDIO. Error Statuses Checked in R1 Bit31 OUT_OF_RANGE.." "0,1" newline bitfld.word 0x0 5. "BYTE_MODE,This bit specifies whether data transfer is in byte mode or block mode when Data Present is set to 1. This bit is effective to a command with data trans-fer." "0,1" newline bitfld.word 0x0 4. "DATA_XFER_DIR,This bit specifies direction of data trans-fer when Data Present is set to 1. This bit is effective to a command with data transfer. 0 - Read [Card to Host] 1 - Write [Host to Card]" "0: Read [Card to Host] 1,?" newline bitfld.word 0x0 1. "BLK_CNT_ENA,This bit specifies whether data transfer usesUHS-II Block Count register. If this bit is set to 1 data transfer is terminated by Block Count. Setting to UHS-II Block Count register shall be equivalent to TLEN in UHS-II Command Packet.." "0,1" newline bitfld.word 0x0 0. "DMA_ENA,This bit selects whether DMA is used or not and is effective to a command with data transfer. One of DMA types is selected by DMA Select in the Host Control 1 register." "0,1" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_command,This register is used to program the Command for host controller" hexmask.word.byte 0x2 8.--12. 1. "PKT_LENGTH,A command packet length which is set in the UHS-II Command Packet register is set to this register. 00011b - 00000b - 3-0 Bytes [Not used] 00100b - 4 Bytes .......... ...... 10100b - 20 Bytes.." newline bitfld.word 0x2 6.--7. "CMD_TYPE,This field is used to distinguish a spe-cific command like abort command. If this field is set to 00b the UHS-II RES Packet is stored in UHS-II Response register [0B3h-0A0h]. To avoid overwrit-ing the UHS-II Response register when this filed.." "0,1,2,3" newline bitfld.word 0x2 5. "DATA_PRESENT,This bit specifies whether the command is accompanied by data packet." "0,1" newline bitfld.word 0x2 2. "SUB_COMMAND,This bit is added from Version 4.10 to distinguish a main command or sub command [Refer to Section 1.17].When issuing a main command this bit is set to 0 and when issuing a sub com-mand this bit is set to 1. Setting of this bit is checked.." "0,1" rgroup.byte 0xA0++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_response,This register is used to store received UHS-II RES Packet image" hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." rgroup.byte 0xB4++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_message_select,This register is used to access internal buffer" bitfld.byte 0x0 0.--1. "MSG_SEL,Host Controller holds 4 MSG packets in FIFO buffer.One of 4 MSGs can be read from the UHS-II MSG register [0BB-0B8h] by setting this register.[Assumed for debug usage.] '00' The latest MSG '01' One MSG before '10' Two MSGs.." "0,1,2,3" rgroup.long 0xB8++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_message,This register is used to access internal buffer" hexmask.long.byte 0x0 24.--31. 1. "MSG_BYTE3,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.." newline hexmask.long.byte 0x0 16.--23. 1. "MSG_BYTE2,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.." newline hexmask.long.byte 0x0 8.--15. 1. "MSG_BYTE1,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.." newline hexmask.long.byte 0x0 0.--7. 1. "MSG_BYTE0,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.." rgroup.word 0xBC++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_intr_status,This register shows receipt of INT MSG from which device" hexmask.word 0x0 0.--15. 1. "DEV_INT_STS,This register shows receipt of INT MSG from which device and is effective when INT MSG Enable is set to 1 in the UHS- II Device Select register. On receiving INT MSG from a device Host Controller saves the INT MSG to UHS-II Device Interrupt.." rgroup.byte 0xBE++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_select,UHS-II Device Select Register" bitfld.byte 0x0 7. "INT_MSG_ENA,This bit enables receipt of INT MSG. If this bit is set to 1 receipt of INT MSG is informed by Card Interrupt in the Nor-mal Interrupt Status register. If this bit is set to 0 Host Con-troller ignores receipt of INT MSG and may not set the.." "0,1" newline hexmask.byte 0x0 0.--3. 1. "DEV_SEL,Host Controller holds an INT MSG packet per device. One of INT MSGs [up to 15] can be selected by this field and read from the UHS-II Device Interrupt Code Register [0BFh]. This field is effective when INT MSG Enable is set to 1. The.." rgroup.byte 0xBF++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_int_code,This register is effective when INT MSG Enable is set to 1 in the UHS-II Device Select register." hexmask.byte 0x0 0.--7. 1. "DEV_INTR,This register is effective when INT MSG Enable is set to 1 in the UHS-II Device Select register. Host Controller holds an INT MSG packet per device. One of INT MSGs [Code length is 1 byte] up to 15 can be read from this register by.." rgroup.word 0xC0++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_software_reset,UHS-II Software Reset Register" bitfld.word 0x0 1. "HOST_SDTRAN_RESET,Host Driver set this bit to 1 to reset SD-TRAN layer when CMD0 is issued to Device or data transfer error occurs. This bit is cleared automatically at completionof SD-TRAN reset. If CMD0 is issued SD-TRAN Initial- ization sequence from.." "0,1" newline bitfld.word 0x0 0. "HOST_FULL_RESET,On issuing FULL_RESET CCMD Host Driver set this bit to 1 to reset Host Controller. This bit is cleared auto-matically at completion of Host Controller reset. Initial- ization sequence from PHY Initialization is required to use UHS-II.." "0,1" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_timer_control,UHS-II Timeout Control Register" hexmask.word.byte 0x2 4.--7. 1. "DEADLOCK_TIMEOUT_CTR,This value determines the deadlock period while host expecting to receive a packet [1 second]. Tim-eout clock frequency will be generated by dividing the base clock TMCLK value by this value. When setting this register prevent.." newline hexmask.word.byte 0x2 0.--3. 1. "CMDRESP_TIMEOUT_CTR,This value determines the interval between com-mand packet and response packet [5ms]. Timeout clock frequency will be generated by dividing the base clock TMCLK value by this value. When set-ting this register prevent inadvertent.." rgroup.long 0xC4++0xB line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sts,This register gives the status of all UHS-II interrupts" hexmask.long.byte 0x0 27.--31. 1. "VENDOR_SPECFIC_ERR,Vendor may use this field for vendor specific error status. '0' Interrupt is not generated '1' Vendor Specific Error" newline bitfld.long 0x0 17. "DEADLOCK_TIMEOUT,Setting of this bit means that deadlock timeout occurs. Host expects to receive a packet but not received in a specified timeout [1 second]. Timeout value is determined by the setting of Timeout Counter Value for Deadlock in UHS-II Timer.." "0,1" newline bitfld.long 0x0 16. "CMD_RESP_TIMEOUT,Setting of this bit means that RES Packet timeout occurs. Host expects to receive RES packet but not received in a specified timeout [5ms]. Timeout value is determined by the setting of Timeout Counter Value for CMD_RES in UHS-II Timer.." "0,1" newline bitfld.long 0x0 15. "ADMA2_ADMA3,Setting of this bit means that ADMA2/3 Error occurs in UHS-II mode. ADMA2/3 Error Status is indicated to the ADMA Error Status [054h] which is defined in the Host spec 3.00." "0,1" newline bitfld.long 0x0 8. "EBSY,On receiving EBSY packet if the packet indicates an error this bit is set to 1. Setting of this bit also sets Error Interrupt and Transfer Completer together in the Normal Interrupt Status register. This error check is effective for a command with.." "0,1" newline bitfld.long 0x0 7. "UNRECOVERABLE,Setting of this bit means that Unrecoverable Error is set in a packet from a device." "0,1" newline bitfld.long 0x0 5. "TID,Setting of this bit means that TID Error occurs." "0,1" newline bitfld.long 0x0 4. "FRAMING,Setting of this bit means that Framing Error occurs during a packet receiving." "0,1" newline bitfld.long 0x0 3. "CRC,Setting of this bit means that CRC Error occurs during a packet receiving." "0,1" newline bitfld.long 0x0 2. "RETRY_EXPIRED,Setting of this bit means that Retry Counter Expired Error occurs during data transfer.If this bit is set either Framing Error or CRC Error in this register shall be set." "0,1" newline bitfld.long 0x0 1. "RESP_PKT,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to1 in the UHS- II Transfer Mode register Host Controller.." "0,1" newline bitfld.long 0x0 0. "HEADER,Setting of this bit means that Header Error occurs in a received packet." "0,1" line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sts_ena,This register is used to enable the UHS-II Error Interrupt Status register fields" hexmask.long.byte 0x4 27.--31. 1. "VENDOR_SPECFIC,Setting this bit to 1 enables setting of Vendor Specific Error bit in the UHS-II Error Interrupt Status register. 0h - Status is Disabled 1h - Status is Enabled" newline bitfld.long 0x4 17. "DEADLOCK_TIMEOUT,Setting this bit to 1 enables setting of Timeout for Dead lock bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 16. "CMD_RESP_TIMEOUT,Setting this bit to 1 enables setting of Timeout for CMD_RES bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 15. "ADMA2_ADMA3,Setting this bit to 1 enables setting of ADMA2/3 Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 8. "EBSY,Setting this bit to 1 enables setting of EBSY Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 7. "UNRECOVERABLE,Setting this bit to 1 enables setting of Unrecoverable Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 5. "TID,Setting this bit to 1 enables setting of TID Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 4. "FRAMING,Setting this bit to 1 enables setting of Framing Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 3. "CRC,Setting this bit to 1 enables setting of CRC Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 2. "RETRY_EXPIRED,Setting this bit to 1 enables setting of Retry Expired bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 1. "RESP_PKT,Setting this bit to 1 enables setting of RES Packet Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 0. "HEADER,Setting this bit to 1 enables setting of Header Error bit in the UHS-II Error Interrupt Status Register." "0,1" line.long 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sig_ena,This register is used to generate UHS-II Interrupt signals" hexmask.long.byte 0x8 27.--31. 1. "VENDOR_SPECFIC,Setting of a bit to 1 in this field enables generating interrupt signal when corre-spondent bit of Vendor Specific Error is set in the UHS-II Error Interrupt Status Register. 0h - Interrupt Signal is Disabled 1h -.." newline bitfld.long 0x8 17. "DEADLOCK_TIMEOUT,Setting this bit to 1 enables generating interrupt signal when Timeout for Dead lock bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 16. "CMD_RESP_TIMEOUT,Setting this bit to 1 enables generating interrupt signal when Timeout for CMD_RES bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 15. "ADMA2_ADMA3,Setting this bit to 1 enables generating interrupt signal when ADMA2/3 Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 8. "EBSY,Setting this bit to 1 enables generating interrupt signal when EBSY Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 7. "UNRECOVERABLE,Setting this bit to 1 enables generating interrupt signal when Unrecoverable Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 5. "TID,Setting this bit to 1 enables generating interrupt signal when TID Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 4. "FRAMING,Setting this bit to 1 enables generating interrupt signal when Framing Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 3. "CRC,Setting this bit to 1 enables generating interrupt signal when CRC Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 2. "RETRY_EXPIRED_SIG_ENA,Setting this bit to 1 enables generating interrupt signal when Retry Expired bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 1. "RESP_PKT,Setting this bit to 1 enables generating interrupt signal when RES Packet Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 0. "HEADER,Setting this bit to 1 enables generating interrupt signal when Header Error bit is set in the UHS-II Error Interrupt Status Register." "0,1" rgroup.word 0xE0++0x9 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_settings_ptr,This register is pointer for UHS-II settings." hexmask.word 0x0 0.--15. 1. "UHS2_SETTINGS_PTR,Pointer for UHS-II Settings Register" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_capabilities_ptr,This register is pointer for UHS-II Capabilities Register." hexmask.word 0x2 0.--15. 1. "UHS2_CAPABILITIES_PTR,Pointer for UHS-II Capabilities Register" line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_test_ptr,This register is pointer for UHS-II Test Register." hexmask.word 0x4 0.--15. 1. "UHS2_TEST_PTR,Pointer for UHS-II Test Register" line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_shared_bus_ctrl_ptr,This register is pointer for UHS-II Shared Bus Control Register." hexmask.word 0x6 0.--15. 1. "SHARED_BUS_CTRL_PTR,Pointer for Shared Bus Control Register" line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_vendor_specfic_ptr,This register is pointer for UHS-II Vendor Specific Pointer Register." hexmask.word 0x8 0.--15. 1. "VENDOR_SPECFIC_PTR,Pointer for Vendor Specific Area" rgroup.long 0xF4++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_boot_timeout_control,This is used to program the boot timeout value counter" hexmask.long 0x0 0.--31. 1. "DATA_TIMEOUT_CNT,This value determines the interval by which DAT line time-outs are detected during boot operation for eMMC4.4 card.The value is in number of sd clock." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_vendor_register,Vendor register added for autogate sdclk. cmd11 power down timer. enhancedstrobe and eMMC hardware reset" bitfld.long 0x4 16. "AUTOGATE_SDCLK,If this bit is set SD CLK will be gated automatically when there is no transfer. This is applicable only for Embedded Device" "0,1" newline hexmask.long.word 0x4 2.--15. 1. "CMD11_PD_TIMER,cmd11 power-down timer value" newline bitfld.long 0x4 1. "EMMC_HW_RESET,Hardware reset signal is generared for eMMC card when this bit is set" "0,1" newline bitfld.long 0x4 0. "ENHANCED_STROBE,This bit enables the enhanced strobe logic of the Host Controller" "0,1" rgroup.word 0xFC++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_slot_int_sts,This register is used to read the interrupt signal for each slot." hexmask.word.byte 0x0 0.--7. 1. "INTR_SIG,These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot." line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_host_controller_ver,This register is used to read the vendor version number and specification version number" hexmask.word.byte 0x2 8.--15. 1. "VEN_VER_NUM,The Vendor Version Number is set to 0x10 [1.0]" newline hexmask.word.byte 0x2 0.--7. 1. "SPEC_VER_NUM,This status indicates the Host Controller Spec. Version. The upper and lower 4-bits indicate the version. 00h - SD Host Controller Specification Version 1.00 01h - SD Host Controller Specification Version 2.00 Including the.." rgroup.long 0x100++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_gen_settings,Start Address of General settings is pointed by Pointer for UHS-II Setting Register." hexmask.long.byte 0x0 8.--13. 1. "NUMLANES,The lane configuration of a Host System is set to this field depends on the capability among Host Controller and connected devices. 2 Lanes FD mode is mandatory and the others modes are optional. 0000b - 2 Lanes FD or 2L-HD 0001b -.." newline bitfld.long 0x0 0. "POWER_MODE,This field determines either Fast mode or Low Power mode.Host and all devices connected to the host shall be set to the same mode." "0,1" line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_phy_settings,Start Address of PHY settings is pointed by Pointer for UHS-II Setting Register." hexmask.long.byte 0x4 20.--23. 1. "N_LSS_DIR,The largest value of N_LSS_DIR capabilities among the Host Controller and Connected Devices is set to this field. 0h - 8 x16 LSS 1h - 8 x 1 LSS 2h - 8 x 2 LSS 3h - 8 x 3 LSS ...... ......" newline hexmask.long.byte 0x4 16.--19. 1. "N_LSS_SYN,The largest value of N_LSS_SYN capabilities among the Host Controller and Connected Devices is set to this field. 0h - 4 x16 LSS 1h - 4 x 1 LSS 2h - 4 x 2 LSS 3h - 4 x 3 LSS ...... ......" newline bitfld.long 0x4 15. "HIBERNATE_ENA,After checking card capability of Hibernate mode if all devices support Hibernate mode this bit may be set. This bit determines whether Host remains in Dormant state or goes to Hibernate state. In Hibernate mode VDD1 Power may be off." "0,1" newline bitfld.long 0x4 6.--7. "SPEED_RANGE,PLL multiplier is selected by this field.Change of PLL Multiplier is not effective immediately and is applied from exiting Dormant State. '00' Range A [Default] '01' Range B '10' Reserved '11' Reserved" "0,1,2,3" rgroup.quad 0x108++0x7 line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_lnk_trn_settings,Start Address of LINK/TRAN settings is pointed by Pointer for UHS-II Setting Register." hexmask.quad.byte 0x0 32.--39. 1. "N_DATA_GAP,The largest value of N_DATA_GAP capabilities among the Host Controller and Connected Devices is set to this field. 00h - No Gap 01h - 1 LSS 02h - 2 LSS 03h - 3 LSS ...... ...... FFh - 255.." newline bitfld.quad 0x0 16.--17. "RETRY_COUNT,Data Burst retry count is set to this field. '00' Retry Disabled '01' 1 time '10' 2 times '11' 3 times" "0,1,2,3" newline hexmask.quad.byte 0x0 8.--15. 1. "HOST_NFCU,Host Driver sets the number of blocks in Data Burst [Flow Control] to this field.The value shall be smaller than or equal to N_FCU capabilities among the Host Controller and connected card and devices. Setting 1 to 4 blocks is recommended.." rgroup.long 0x110++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_gen_cap,Start Address of General Capabilities is pointed by Pointer for UHS-II Host Capabilities Register." bitfld.long 0x0 22.--23. "CORECFG_UHS2_BUS_TOPLOGY,This field indicates one of bus topologies configured by a Host system. '00' P2P Connection '01' Ring Connection '10' HUB Connection '11' HUB is connected in Ring" "0,1,2,3" newline hexmask.long.byte 0x0 18.--21. 1. "CORECFG_UHS2_MAX_DEVICES,This field indicates the maximum number of devices supported by the Host Controller. 0h - Not used 1h - 1 Devices 2h - 2 Devices ..... ....... Fh - 15 Devices" newline bitfld.long 0x0 16.--17. "DEVICE_TYPE,This field indicates device type configured by a Host system. '00' Removable Card[P2P] '01' Embedded Devices '10' Embedded Devices+Removable Card '11' Reserved" "0,1,2,3" newline bitfld.long 0x0 14. "CFG_64BIT_ADDRESSING,This field indicates support of 64-bit addressing by the Host Controller. '0' 32-bit Addressing is supported '1' 32-bit and 64-bit Addressing is supported" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "NUM_LANES,This field indicates support of lanes by the Host Controller.0 mean not supported and 1 means supported. D08 - 2L-HD D09 - 2D1U-FD D10 - 1D2U-FD D11 - 2D2U-FD D12 - Reserved D13 - Reserved" newline hexmask.long.byte 0x0 4.--7. 1. "GAP,This field indicates the maximum capability of host power supply for a group configured by a Host system.This field is used to set the argument of DEVICE_INIT CCMD 0h -Not used 1h - 360 mW 2h - 720 mW ....." newline hexmask.long.byte 0x0 0.--3. 1. "DAP,This field indicates the maximum capability of host power supply for a device configured by a Host system.This field is used to set the argument of DEVICE_INIT CCMD 0h -360 mW [Default] 1h - 360 mW 2h - 720 mW.." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_phy_cap,Start Address of PHY Capabilities is pointed by Pointer for UHS-II Host Capabilities Register." hexmask.long.byte 0x4 20.--23. 1. "N_LSS_DIR,This field indicates the minimum N_LSS_DIR required by the Host Controller. 0h - 4 x16 LSS 1h - 4 x 1 LSS 2h - 4 x 2 LSS 3h - 4 x 3 LSS ...... ...... Fh - 4 x 15 LSS" newline hexmask.long.byte 0x4 16.--19. 1. "N_LSS_SYN,This field indicates the minimum N_LSS_SYN required by the Host Controller. 0h - 4 x16 LSS 1h - 4 x 1 LSS 2h - 4 x 2 LSS 3h - 4 x 3 LSS ...... ...... Fh - 4 x 15 LSS" newline bitfld.long 0x4 6.--7. "SPEED_RANGE,This field indicates supported Speed Range by the Host Controller '00' Range A [Default] '01' Range A and Range B '10' Reserved '11' Reserved" "0,1,2,3" rgroup.quad 0x118++0x7 line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_lnk_trn_cap,Start Address of LINK/TRAN settings is pointed by Pointer for UHS-II Capabilities Register." hexmask.quad.byte 0x0 32.--39. 1. "N_DATA_GAP,This field indicates the minimum number of data gap[DIDL] supported by the Host Controller. 00h - No Gap 01h - 1 LSS 02h - 2 LSS 03h - 3 LSS ...... ...... FFh - 255 LSS" newline hexmask.quad.word 0x0 20.--31. 1. "MAX_BLK_LENGTH,This field indicates maximum block length by the Host Controller. 000h - Not Used 001h - 1 byte 002h - 2 bytes ...... ...... 200h - 512 bytes ...... ......" newline hexmask.quad.byte 0x0 8.--15. 1. "N_FCU,This field indicates maximum the number of blocks in a Flow Control unit by the Host Controller.This value is determined by supported buffer size. 00h - 256 Blocks 01h - 1 Block 02h - 2 Block 03h - 3 Block.." rgroup.long 0x120++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_force_UHSII_Err_Int_Sts,This register is not physically implemented. rather it is an address where UHS-II Error Interrupt Status register can be written." hexmask.long.byte 0x0 27.--31. 1. "VENDOR_SPECIFIC,Force Event for Vendor Specific Error 0h - Not Affected 1h - Vendor Specific Error Status is set" newline bitfld.long 0x0 17. "TIMEOUT_DEADLOCK,Setting this bit forces the Host Controller to set Timeout for Deadlock in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 16. "TIMEOUT_CMD_RES,Setting this bit forces the Host Controller to set Timeout for CMD_RES in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 15. "ADMA,Setting this bit forces the Host Controller to set ADMA Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 8. "EBSY,Setting this bit forces the Host Controller to set EBSY Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 7. "UNRECOVERABLE,Setting this bit forces the Host Controller to set Unrecover-able Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 5. "TID,Setting this bit forces the Host Controller to set TID Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 4. "FRAMING,Setting this bit forces the Host Controller to set Framing Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 3. "CRC,Setting this bit forces the Host Controller to set CRC Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 2. "RETRY_EXPIRED,Setting this bit forces the Host Controller to set Retry Expired in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 1. "RES_PKT,Setting this bit forces the Host Controller to set RES Packet Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 0. "HEADER,Setting this bit forces the Host Controller to set Header Error in the UHS-II Error Interrupt Status register." "0,1" rgroup.long 0x200++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_version,This register provides information about the version of the eMMC CQ standard which is 285 implemented by the CQE. in BCD format. The current version is rev 5.1" hexmask.long.byte 0x0 8.--11. 1. "EMMC_MAJOR_VER_NUM,eMMC Major Version Number [digit left of decimal point] in BCD format" newline hexmask.long.byte 0x0 4.--7. 1. "EMMC_MINOR_VER_NUM,eMMC Minor Version Number [digit right of decimal point] in BCD format" newline hexmask.long.byte 0x0 0.--3. 1. "EMMC_VERSION_SUFFIX,eMMC Version Suffix [2nd digit right of decimal point] in BCD format" line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_capabilities,This register is reserved for capability indication." hexmask.long.byte 0x4 12.--15. 1. "CF_MUL,Internal Timer Clock Frequency Multiplier [ITCFMUL] ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for deter-mining the SQS polling period. See ITCFVAL definition for details." newline hexmask.long.word 0x4 0.--9. 1. "CF_VAL,Internal Timer Clock Frequency Value [ITCFVAL] TCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for deter-mining the polling period when using periodic SEND_QUEUE_ STATUS [CMD13] polling." rgroup.long 0x208++0x27 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_config,This register controls CQE behavior affecting the general operation of command queueing 290 module or operation of multiple tasks in the same time." bitfld.long 0x0 12. "DCMD_ENA,Direct Command [DCMD] Enable This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a Data Transfer Task Descriptor or a Direct Command Task Descriptor. CQE uses this bit when a task is issued in slot.." "0: Task descriptor in slot #31 is a Data Transfer..,1: Task descriptor in slot #31 is a DCMD Task.." newline bitfld.long 0x0 8. "TASK_DESC_SIZE,Task Descriptor Size This bit indicates whether the task descriptor size is 128 bits or 64 bits as detailed in Data Structures section. This bit can only be configured when Command Queueing Enable bit is 0 [command queueing is.." "0: Task descriptor size is 64 bits,1: Task descriptor size is 128 bits" newline bitfld.long 0x0 0. "CQ_ENABLE,Command Queueing Enable Software shall write 1 this bit when in order to enable command queueing mode [i.e. enable CQE]. When this bit is 0 CQE is disabled and software controls the eMMC bus using the legacy eMMC host controller." "0,1" line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_control,This register controls CQE behavior affecting the general operation of command queueing 293 module or operation of multiple tasks in the same time." bitfld.long 0x4 8. "CLEAR_ALL_TASKS,Clear All Tasks Software shall write 1 this bit when it wants to clear all the tasks sent to the device. This bit can only be written when CQE is in halt state [i.e.Halt bit is 1]. When software writes 1 the value of the.." "0,1" newline bitfld.long 0x4 0. "HALT_BIT,Halt Host software shall write 1 to the bit when it wants to acquire software control over the eMMC bus and disable CQE from issuing commands on the bus. For example issuing a Discard Task command [CMDQ_TASK_MGMT] When software writes 1 .." "0,1" line.long 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sts,This register indicates pending interrupts that require service. Each bit in this registers is asserted 296 in response a specific event. only if the respective bit is set in CQ ISTE register." bitfld.long 0x8 4. "TASK_ERROR,Task Error Interrupt [TERR] This bit is asserted when task error is detected due to invalid task descriptor" "0,1" newline bitfld.long 0x8 3. "TASK_CLEARED,Task Cleared [TCL] This status bit is asserted [if CQISTE.TCL=1] when a task clear operation is completed by CQE. The com-pleted task clear operation is either an individual task clear [CQTCLR] or clearing of all tasks [CQCTL]." "0,1" newline bitfld.long 0x8 2. "RESP_ERR_DET,Response Error Detected Interrupt [RED] This status bit is asserted [if CQISTE.RED=1] when a response is received with an error bit set in the device status field. The contents of the device status field are listed in Section.." "0,1" newline bitfld.long 0x8 1. "TASK_COMPLETE,Task Complete Interrupt [TCC] This status bit is asserted [if CQISTE.TCC=1] when atleast one of the following two conditions are met: [1] A task is completed and the INT bit is set in its Task Descriptor [2] Interrupt caused by.." "0,1" newline bitfld.long 0x8 0. "HALT_COMPLETE,Halt Complete Interrupt [HAC] This status bit is asserted [if CQISTE.HAC=1] when halt bit in CQCTL register transitions from 0 to 1 indicating that host controller has completed its current ongoing task and has entered halt state." "0,1" line.long 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sts_ena,This register enables and disables the reporting of the corresponding interrupt to host soft-ware in 299 CQIS register. When a bit is set ( 1 ) and the corresponding interrupt c -ondition is active. then.." bitfld.long 0xC 4. "TASK_ERROR,Task Error Interrupt Status Enable 1 = CQIS.TERR will be set when its interrupt condition is active 0 = CQIS.TERR is disabled" "0: CQIS,1: CQIS" newline bitfld.long 0xC 3. "TASK_CLEARED,Task Cleared Status Enable [TCL] 1 = CQIS.TCL will be set when its interrupt condition is active 0 = CQIS.TCL is disabled" "0: CQIS,1: CQIS" newline bitfld.long 0xC 2. "RESP_ERR_DET,Response Error Detected Status Enable [RED] 1 = CQIS.RED will be set when its interrupt condition is active 0 = CQIS.RED is disabled" "0: CQIS,1: CQIS" newline bitfld.long 0xC 1. "TASK_COMPLETE,Task Complete Status Enable [TCC] 1 = CQIS.TCC will be set when its interrupt condition is active 0 = CQIS.TCC is disabled" "0: CQIS,1: CQIS" newline bitfld.long 0xC 0. "HALT_COMPLETE,Halt Complete Status Enable [HAC] 1 = CQIS.HAC will be set when its interrupt condition is active 0 = CQIS.HAC is disabled" "0: CQIS,1: CQIS" line.long 0x10 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sig_ena,This register enables and disables the generation of interrupts to host software. When a bit is set 304 ( 1 ) and the corresponding bit in CQIS is set. then an interrupt is gene -rated. Interrupt sources.." bitfld.long 0x10 4. "TASK_ERROR,Task Error Interrupt Signal Enable [TERR] When set and CQIS.TERR is asserted the CQE shall generate an interrupt" "0,1" newline bitfld.long 0x10 3. "TASK_CLEARED,Task Cleared Signal Enable [TCL] When set and CQIS.TCL is asserted the CQE shall generate an interrupt" "0,1" newline bitfld.long 0x10 2. "RESP_ERR_DET,Response Error Detected Signal Enable [TCC] When set and CQIS.RED is asserted the CQE shall generate an interrupt" "0,1" newline bitfld.long 0x10 1. "TASK_COMPLETE,Task Complete Signal Enable [TCC] When set and CQIS.TCC is asserted the CQE shall generate an interrupt" "0,1" newline bitfld.long 0x10 0. "HALT_COMPLETE,Halt Complete Signal Enable [HAC] When set and CQIS.HAC is asserted the CQE shall generate an interrupt" "0,1" line.long 0x14 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_coalescing,This register controls the interrupt coalescing feature." bitfld.long 0x14 31. "CQINTCOALESC_ENABLE,When set to 0 by software command responses are neither counted nor timed. Interrupts are still triggered by completion of tasks with INT=1 in the Task Descriptor. When set to 1 the interrupt coalescing mechanism is enabled.." "0,1" newline rbitfld.long 0x14 20. "IC_STATUS,This bit indicates to software whether any tasks [with INT=0] have completed and counted towards interrupt coalescing [i.e. ICSB is set if and only if IC counter > 0]. Bit Value Description 1 = At least one task completion has been.." "0: No task completions have occurred since last..,1: At least one task completion has been counted.." newline hexmask.long.byte 0x14 8.--12. 1. "CTR_THRESHOLD,Interrupt Coalescing Counter Threshold [ICCTH]: Software uses this field to configure the number of task completions [only tasks with INT=0 in the Task Descriptor] which are required in order to generate an interrupt. Counter.." newline hexmask.long.byte 0x14 0.--6. 1. "TIMEOUT_VAL,Interrupt Coalescing Timeout Value [ICTOVAL]: Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. Timer Operation: The timer is reset by.." line.long 0x18 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_tdl_base_addr,This register is used for configuring the lower 32 bits of the byte address of the head of the Task 312 Descriptor List in the host memory." hexmask.long 0x18 0.--31. 1. "CQTDLBA_LO,Task Descriptor List Base Address [TDLBA] This register stores the LSB bits [bits 31:0] of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 * [Task Descrip-tor.." line.long 0x1C "SDHC_WRAP__CTL_CFG__CTLCFG_cq_tdl_base_addr_upbits,This register is used for configuring the upper 32 bits of the byte address of the head of the Task 316 Descriptor List in the host memory." hexmask.long 0x1C 0.--31. 1. "CQTDLBA_HI,Task Descriptor List Base Address [TDLBA] This register stores the MSB bits [bits 63:32] of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 * [Task Descrip-tor.." line.long 0x20 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_door_bell,Using this register. software triggers CQE to process a new task." hexmask.long 0x20 0.--31. 1. "CQTDB_VAL,Command Queueing Task Doorbell Software shall configure TDLBA and TDLBAU and enable CQE in CQCFG before using this register. Writing 1 to bit n of this register triggers CQE to start pro-cessing the task encoded in slot n of the TDL." line.long 0x24 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_comp_notif,This register is used by CQE to notify software about completed tasks." hexmask.long 0x24 0.--31. 1. "CQTCN_VAL,CQE shall set bit n of this register [at the same time it clears bit n of CQTDBR] when a task execution is com-pleted [with success or error]. When receiving interrupt for task completion software may read this register to know which tasks.." rgroup.long 0x230++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dev_queue_status,This register stores the most recent value of the device s queue status." hexmask.long 0x0 0.--31. 1. "CQDQ_STS,Every time the Host controller receives a queue status register [QSR] from the device it updates this register with the response of status command i.e. the devices queue status." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dev_pending_tasks,This register indicates to software which tasks are queued in the device. awaiting execution." hexmask.long 0x4 0.--31. 1. "CQDP_TSKS,Bit n of this register is set if and only if QUEUED_TASK_PARAMS [CMD44] and QUEUED_TASK_ADDRESS [CMD45] were sent for this specific task and if this task hasnt been executed yet.CQE shall set this bit after receiving a successful response for.." rgroup.long 0x238++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_clear,This register is used for removing an outstanding task in the CQE. 327. The register should be used only when CQE is in Halt state." hexmask.long 0x0 0.--31. 1. "CQTCLR,Writing 1 to bit n of this register orders CQE to clear a task which software has previously issued.This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit.When software writes 1 to a bit in this.." rgroup.long 0x240++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_send_sts_config1,The register controls the when SEND_QUEUE_STATUS commands are sent." hexmask.long.byte 0x0 16.--19. 1. "CMD_BLK_CNTR,This field indicates to CQE when to send SEND_QUEUE_STATUS [CMD13] command to inquire the status of the devices task queue.A value of n means CQE shall send status command on the CMD line during the transfer of data block BLOCK_CNT-n on.." newline hexmask.long.word 0x0 0.--15. 1. "CMD_IDLE_TIMER,This field indicates to CQE the polling period to use when using periodic SEND_QUEUE_STATUS [CMD13] polling.Periodic polling is used when tasks are pending in the device but no data transfer is in progress. When a SEND_QUEUE_STATUS.." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_send_sts_config2,This register is used for 333 configuring RCA field in SEND_QUEUE_STATUS command argu-ment." hexmask.long.word 0x4 0.--15. 1. "QUEUE_RCA,This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_ STATUS [CMD13] com-mand. argument. CQE shall copy this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS [CMD13] command." rgroup.long 0x248++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dcmd_response,This register is used for passing the response of a DCMD task to software." hexmask.long 0x0 0.--31. 1. "LAST_RESP,This register contains the response of the command generated by the last direct-command [DCMD] task which was sent.CQE shall update this register when it receives the response for a DCMD task. This register is considered valid only after bit 31.." rgroup.long 0x250++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_resp_err_mask,This register controls the generation of Response Error Detection (RED) interrupt." hexmask.long 0x0 0.--31. 1. "CQRMEM,This bit is used as in interrupt mask on the device status filed which is received in R1/R1b responses.Bit Value Description [for any bit i]:1 = When a R1/R1b response is received with bit i in the device status set a RED interrupt is generated.." rgroup.long 0x254++0xF line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_err_info,This register is updated by CQE when an error occurs on data or command related to a task activity." bitfld.long 0x0 31. "DATERR_VALID,Data Transfer Error Fields Valid This bit is updated when an error is detected by CQE or indicated by eMMC controller. If a data transfer is in progress when the error is detected/indicated the bit is set to 1. If a no.." "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "DATERR_TASK_ID,Data Transfer Error Task ID This field indicates the ID of the task which was executed on the data lines when an error occurred. The field is updated if a data transfer is in progress when an error is detected by CQE or.." newline hexmask.long.byte 0x0 16.--21. 1. "DATERR_CMD_INDEX,Data Transfer Error Command Index This field indicates the index of the command which was executed on the data lines when an error occurred. The index shall be set to EXECUTE_READ_TASK[CMD46] or EXECUTE_WRITE_TASK [CMD47].." newline bitfld.long 0x0 15. "RESP_MODE_VALID,Response Mode Error Fields Valid This bit is updated when an error is detected by CQE or indicated by eMMC controller. If a command transaction is in progress when the error is detected/indicated the bit is set to 1." "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "RESP_MODE_TASK_ID,Response Mode Error Task ID This field indicates the ID of the task which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is detected by.." newline hexmask.long.byte 0x0 0.--5. 1. "RESP_MODE_CMD_INDEX,Response Mode Error Command Index This field indicates the index of the command which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is.." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_cmd_resp_index,This register stores the index of the last received command response." hexmask.long.byte 0x4 0.--5. 1. "LAST_CRI,This field stores the index of the last received command response. CQE shall update the value every time a com-mand response is received." line.long 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_cmd_resp_arg,This register stores the index of the last received command response." hexmask.long 0x8 0.--31. 1. "LAST_CRA,This field stores the argument of the last received com-mand. CQE shall update the value every time a com-mand response is received." line.long 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_cq_error_task_id,CQ Error Task ID Register" hexmask.long.byte 0xC 0.--4. 1. "TERR_ID,Task Error ID" tree.end tree "MMCSD1_ECC_AGGR" tree "MMCSD1_ECC_AGGR_RXMEM (MMCSD1_ECC_AGGR_RXMEM)" base ad:0x2A26000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_RXMEM__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "RXMEM_ENABLE_SET,Interrupt Enable Set Register for rxmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear Register for rxmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_RXMEM__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "RXMEM_ENABLE_SET,Interrupt Enable Set Register for rxmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear Register for rxmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_RXMEM__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_RXMEM__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_RXMEM__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MMCSD1_ECC_AGGR_TXMEM (MMCSD1_ECC_AGGR_TXMEM)" base ad:0x2A27000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_TXMEM__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "TXMEM_ENABLE_SET,Interrupt Enable Set Register for txmem_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear Register for txmem_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_TXMEM__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "TXMEM_ENABLE_SET,Interrupt Enable Set Register for txmem_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear Register for txmem_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_TXMEM__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_TXMEM__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_TXMEM__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree.end tree "MMCSD1_SS_CFG (MMCSD1_SS_CFG)" base ad:0x4FB8000 rgroup.long 0x0++0x3 line.long 0x0 "REGS__SS_CFG__SSCFG_SS_ID_REV_REG,The Subsystem ID and Revision Register contains the module ID. major. and minor revisions for the subsystem" hexmask.long.word 0x0 16.--31. 1. "MOD_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version" newline bitfld.long 0x0 8.--10. "MAJ_REV,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MIN_REV,Minor revision" rgroup.long 0x10++0x37 line.long 0x0 "REGS__SS_CFG__SSCFG_CTL_CFG_1_REG,The Controller Config 1 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.byte 0x0 24.--29. 1. "TUNINGCOUNT,Configures the Number of Taps (Phases) of the RX clock that is supported. The Tuning State machine uses this information to select one of the Taps (Phases) of the RX clock during the Tuning Procedure." bitfld.long 0x0 20. "ASYNCWKUPENA,Determines the Wakeup Signal Generation Mode. 0: Synchronous Wakeup Mode: The xin_clk has to be running for this mode. The Card Insertion/Removal/Interrupt events are detected synchronously on the xin_clk and the Wakeup Event is generated." "0: Synchronous Wakeup Mode: The xin_clk has to be..,1: Asyncrhonous Wakeup Mode: The xin_clk and the.." newline hexmask.long.byte 0x0 12.--15. 1. "CQFMUL,FMUL for the CQ Internal Timer Clock Frequency" hexmask.long.word 0x0 0.--9. 1. "CQFVAL,FVAL for the CQ Internal Timer Clock Frequency" line.long 0x4 "REGS__SS_CFG__SSCFG_CTL_CFG_2_REG,The Controller Config 2 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." bitfld.long 0x4 30.--31. "SLOTTYPE,Slot Type. Should be set based on the final product usage. 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved." "0: Removable SCard Slot,1: Embedded Slot for One Device,?,?" bitfld.long 0x4 29. "ASYNCHINTRSUPPORT,Asynchronous Interrupt Support. Suggested Value is 1'b1 (The Core supports monitoring of Asynchronous Interrupt)." "0,1" newline bitfld.long 0x4 26. "SUPPORT1P8VOLT,1.8V Support. Suggested Value is 1'b1 (The 1.8 Volt Switching is supported by Core). Optionally can be set to 1'b0 if the application doesn't want 1.8V switching (SD3.0)." "0,1" bitfld.long 0x4 25. "SUPPORT3P0VOLT,3.0V Support. Should be set based on whether 3.0V is supported on the SD Interface." "0,1" newline bitfld.long 0x4 24. "SUPPORT3P3VOLT,3.3V Support. Suggested Value is 1'b1 as the 3.3 V is the default voltage on the SD Interface." "0,1" bitfld.long 0x4 23. "SUSPRESSUPPORT,Suspend/Resume Support. Suggested Value is 1'b1 (The Suspend/Resume is supported by Core). Optionally can be set to 1'b0 if the application doesn't want to support Suspend/Resume Mode." "0,1" newline bitfld.long 0x4 22. "SDMASUPPORT,SDMA Support. Suggested Value is 1'b1 (The SDMA is supported by Core). Optionally can be set to 1'b0 if the application doesn't want to support SDMA Mode." "0,1" bitfld.long 0x4 21. "HIGHSPEEDSUPPORT,High Speed Support. Suggested Value is 1'b1 (The High Speed mode is supported by Core)." "0,1" newline bitfld.long 0x4 19. "ADMA2SUPPORT,ADMA2 Support. Suggested Value is 1'b1 (The ADMA2 is supported by Core). Optionally can be set to 1'b0 if the application doesn't want to support ADMA2 Mode." "0,1" bitfld.long 0x4 18. "SUPPORT8BIT,8-bit Support for Embedded Device. Suggested Value is 1'b1 (The Core supports 8-bit Interface). Optionally an be set to 1'b0 if the Application supports only 4-bit SD Interface." "0,1" newline bitfld.long 0x4 16.--17. "MAXBLKLENGTH,Max Block Length. Maximum Block Length supported by the Core/Device. 00: 512 (Bytes) 01: 1024 10: 2048 11: Reserved." "0,1,2,3" hexmask.long.byte 0x4 8.--15. 1. "BASECLKFREQ,Base Clock Frequency for SD Clock. This is the frequency of the xin_clk." newline bitfld.long 0x4 7. "TIMEOUTCLKUNIT,Timeout Clock Unit. Suggested Value is 1'b0 (KHz)." "0,1" hexmask.long.byte 0x4 0.--5. 1. "TIMEOUTCLKFREQ,Timeout Clock Frequency. Suggested Value is 1 KHz. Internally the 1msec Timer is used for Timeout Detection. The 1msec Timer is generated from the xin_clk." line.long 0x8 "REGS__SS_CFG__SSCFG_CTL_CFG_3_REG,The Controller Config 3 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." bitfld.long 0x8 28. "SUPPORT1P8VDD2,1.8V VDD2 Support." "0,1" bitfld.long 0x8 27. "ADMA3SUPPORT,ADMA3 Support." "0,1" newline hexmask.long.byte 0x8 16.--23. 1. "CLOCKMULTIPLIER,Clock Multiplier. This field indicates clock multiplier value of programmable clock generator. Refer to Clock Control register. Setting 00h means that Host Controller does not support programmable clock generator. FFh Clock Multiplier M =.." bitfld.long 0x8 14.--15. "RETUNINGMODES,Re-Tuning Modes. Should be set to 2'b00 as the Core supports only the Software Timer based Re-Tuning." "0,1,2,3" newline bitfld.long 0x8 13. "TUNINGFORSDR50,Use Tuning for SDR50. This bit should be set if the Application wants Tuning be used for SDR50 Modes. The Core operates with or with out tuning for SDR50 mode as long as the Clock can be manually tuned using tap delay." "0,1" hexmask.long.byte 0x8 8.--11. 1. "RETUNINGTIMERCNT,Timer Count for Re-Tuning. This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer." newline bitfld.long 0x8 7. "TYPE4SUPPORT,Driver Type 4 Support. This bit should be set based on whether Driver Type 4 for 1.8 Signalling is supported or not." "0,1" bitfld.long 0x8 6. "DDRIVERSUPPORT,Driver Type D Support. This bit should be set based on whether Driver Type D for 1.8 Signalling is supported or not." "0,1" newline bitfld.long 0x8 5. "CDRIVERSUPPORT,Driver Type C Support. This bit should be set based on whether Driver Type C for 1.8 Signalling is supported or not." "0,1" bitfld.long 0x8 4. "ADRIVERSUPPORT,Driver Type A Support. This bit should be set based on whether Driver Type A for 1.8 Signalling is supported or not." "0,1" newline bitfld.long 0x8 2. "DDR50SUPPORT,DDR50 Support. Suggested Value is 1'b1 (The Core supports DDR50 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support DDR50." "0,1" bitfld.long 0x8 1. "SDR104SUPPORT,SDR104 Support. Suggested Value is 1'b1 (The Core supports SDR104 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support SDR104." "0,1" newline bitfld.long 0x8 0. "SDR50SUPPORT,SDR50 Support. Suggested Value is 1'b1 (The Core supports SDR50 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support SDR50." "0,1" line.long 0xC "REGS__SS_CFG__SSCFG_CTL_CFG_4_REG,The Controller Config 4 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.byte 0xC 16.--23. 1. "MAXCURRENT1P8V,Maximum Current for 1.8V." hexmask.long.byte 0xC 8.--15. 1. "MAXCURRENT3P0V,Maximum Current for 3.0V." newline hexmask.long.byte 0xC 0.--7. 1. "MAXCURRENT3P3V,Maximum Current for 3.3V." line.long 0x10 "REGS__SS_CFG__SSCFG_CTL_CFG_5_REG,The Controller Config 5 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.byte 0x10 0.--7. 1. "MAXCURRENTVDD2,Maximum Current for 1.8 V (VDD2)." line.long 0x14 "REGS__SS_CFG__SSCFG_CTL_CFG_6_REG,The Controller Config 6 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x14 0.--12. 1. "INITPRESETVAL,Preset Value for Initialization." line.long 0x18 "REGS__SS_CFG__SSCFG_CTL_CFG_7_REG,The Controller Config 7 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x18 0.--12. 1. "DSPDPRESETVAL,Preset Value for Default Speed." line.long 0x1C "REGS__SS_CFG__SSCFG_CTL_CFG_8_REG,The Controller Config 8 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x1C 0.--12. 1. "HSPDPRESETVAL,Preset Value for High Speed." line.long 0x20 "REGS__SS_CFG__SSCFG_CTL_CFG_9_REG,The Controller Config 9 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x20 0.--12. 1. "SDR12PRESETVAL,Preset Value for SDR12." line.long 0x24 "REGS__SS_CFG__SSCFG_CTL_CFG_10_REG,The Controller Config 10 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x24 0.--12. 1. "SDR25PRESETVAL,Preset Value for SDR25." line.long 0x28 "REGS__SS_CFG__SSCFG_CTL_CFG_11_REG,The Controller Config 11 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x28 0.--12. 1. "SDR50PRESETVAL,Preset Value for SDR50." line.long 0x2C "REGS__SS_CFG__SSCFG_CTL_CFG_12_REG,The Controller Config 12 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x2C 0.--12. 1. "SDR104PRESETVAL,Preset Value for SDR104." line.long 0x30 "REGS__SS_CFG__SSCFG_CTL_CFG_13_REG,The Controller Config 13 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x30 0.--12. 1. "DDR50PRESETVAL,Preset Value for DDR50." line.long 0x34 "REGS__SS_CFG__SSCFG_CTL_CFG_14_REG,The Controller Config 14 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." rgroup.long 0x60++0x17 line.long 0x0 "REGS__SS_CFG__SSCFG_CTL_STAT_1_REG,The Controller Status 1 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." bitfld.long 0x0 31. "SDHC_CMDIDLE,Idle signal to enable S/W to gate off the clocks." "0,1" hexmask.long.word 0x0 0.--15. 1. "DMADEBUGBUS,DMA_CTRL Debug Bus." line.long 0x4 "REGS__SS_CFG__SSCFG_CTL_STAT_2_REG,The Controller Status 2 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0x4 0.--15. 1. "CMDDEBUGBUS,CMD_CTRL Debug Bus." line.long 0x8 "REGS__SS_CFG__SSCFG_CTL_STAT_3_REG,The Controller Status 3 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0x8 0.--15. 1. "TXDDEBUGBUS,TXD_CTRL Debug Bus." line.long 0xC "REGS__SS_CFG__SSCFG_CTL_STAT_4_REG,The Controller Status 4 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0xC 0.--15. 1. "RXDDEBUGBUS0,RXD_CTRL Debug Bus (SD CLK)." line.long 0x10 "REGS__SS_CFG__SSCFG_CTL_STAT_5_REG,The Controller Status 5 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0x10 0.--15. 1. "RXDDEBUGBUS1,RXD_CTRL Debug Bus (RX CLK)." line.long 0x14 "REGS__SS_CFG__SSCFG_CTL_STAT_6_REG,The Controller Status 6 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0x14 0.--15. 1. "TUNDEBUGBUS,TUN_CTRL Debug Bus." rgroup.long 0x100++0x17 line.long 0x0 "REGS__SS_CFG__SSCFG_PHY_CTRL_1_REG,The PHY Control 1 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." bitfld.long 0x0 31. "IOMUX_ENABLE,IO mux enable. Set 1 for GPIO. Set 0 for eMMC/SD" "0,1" line.long 0x4 "REGS__SS_CFG__SSCFG_PHY_CTRL_2_REG,The PHY Control 2 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." line.long 0x8 "REGS__SS_CFG__SSCFG_PHY_CTRL_3_REG,The PHY Control 3 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." line.long 0xC "REGS__SS_CFG__SSCFG_PHY_CTRL_4_REG,The PHY Control 4 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." bitfld.long 0xC 20. "OTAPDLYENA,Output Tap Delay Enable. Enables manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface." "0,1" hexmask.long.byte 0xC 12.--15. 1. "OTAPDLYSEL,Output Tap Delay Select. Manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface." newline bitfld.long 0xC 9. "ITAPCHGWIN,Input Tap Change Window. It gets asserted by the controller while changing the itapdlysel. Used to gate of the RX clock during switching the clock source while tap is changing to avoid clock glitches." "0,1" bitfld.long 0xC 8. "ITAPDLYENA,Input Tap Delay Enable. This is used for the manual control of the RX clock Tap Delay in non HS200/HS400 modes." "0,1" newline hexmask.long.byte 0xC 0.--4. 1. "ITAPDLYSEL,Input Tap Delay Select. Manual control of the RX clock Tap Delay in the non HS200/HS400 modes." line.long 0x10 "REGS__SS_CFG__SSCFG_PHY_CTRL_5_REG,The PHY Control 5 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." bitfld.long 0x10 0.--2. "CLKBUFSEL,Clock Delay Buffer Select. Selects one of the eight taps in the CLK Delay Buffer based on PVT variation." "0,1,2,3,4,5,6,7" line.long 0x14 "REGS__SS_CFG__SSCFG_PHY_CTRL_6_REG,The PHY Control 6 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." rgroup.long 0x130++0x7 line.long 0x0 "REGS__SS_CFG__SSCFG_PHY_STAT_1_REG,The PHY Status 1 Register contains various fields to reflect the status of the Arasan eMMC/SD PHY ports. For detailed functionality of the Arasan eMMC/SD PHY status ports please refer to its specification listed in.." line.long 0x4 "REGS__SS_CFG__SSCFG_PHY_STAT_2_REG,The PHY Status 2 Register contains various fields to reflect the status of the Arasan eMMC/SD PHY ports. For detailed functionality of the Arasan eMMC/SD PHY status ports please refer to its specification listed in.." tree.end tree.end sif (cpuis("AM68Ax")||cpuis("TDA4AL88")||cpuis("TDA4VE88")) tree "MSRAM" base ad:0x0 tree "MSRAM_512K0" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "MSRAM_512K0_ECC_AGGR_REGS (MSRAM_512K0_ECC_AGGR_REGS)" base ad:0x2A2F000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_REGSREGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_REGSREGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" bitfld.long 0x4 1. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" bitfld.long 0x0 1. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" bitfld.long 0x0 1. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_REGSREGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_REGSREGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" bitfld.long 0x4 1. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" bitfld.long 0x0 1. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" bitfld.long 0x0 1. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "ECC_AGGR_REGSREGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_REGSREGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_REGSREGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_REGSREGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "MSRAM_512K0_RAM (MSRAM_512K0_RAM)" base ad:0x4F02000000 rgroup.long 0x0++0x3 line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end endif tree.end tree "MSRAM_512K1" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "MSRAM_512K1_ECC_AGGR_REGS (MSRAM_512K1_ECC_AGGR_REGS)" base ad:0x2AFC000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_REGSREGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_REGSREGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" bitfld.long 0x4 1. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" bitfld.long 0x0 1. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" bitfld.long 0x0 1. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_REGSREGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_REGSREGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" bitfld.long 0x4 1. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" bitfld.long 0x0 1. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" bitfld.long 0x0 1. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "ECC_AGGR_REGSREGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_REGSREGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_REGSREGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_REGSREGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "MSRAM_512K1_RAM (MSRAM_512K1_RAM)" base ad:0x4F02080000 rgroup.long 0x0++0x3 line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end endif tree.end tree.end endif sif (cpuis("AM68Ax")||cpuis("TDA4AL88")||cpuis("TDA4VE88")) tree "NAVSS0" base ad:0x0 sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MSRAM0_SLV_RAM (NAVSS0_MSRAM0_SLV_RAM)" base ad:0x30000000 rgroup.long 0x0++0x3 line.long 0x0 "MSRAM0__SLV__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MSRAM_0_MSRAM0_SLV_RAM (NAVSS0_MSRAM_0_MSRAM0_SLV_RAM)" base ad:0x30000000 rgroup.long 0x0++0x3 line.long 0x0 "MSRAM0__SLV__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end endif tree "NAVSS0_BCDMA_0" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_CRED (NAVSS0_BCDMA_0_CRED)" base ad:0x458E8000 rgroup.long 0x0++0x7 line.long 0x0 "CRED_CRED,The Credentials Register provides credentials to be used when performing memory accesses using this flow." bitfld.long 0x0 26. "SECURE,Secure attribute" "0,1" bitfld.long 0x0 24.--25. "PRIV,Privelege attribute" "0,1,2,3" hexmask.long.byte 0x0 16.--23. 1. "PRIVID,Privelege ID attribute" line.long 0x4 "CRED_CRED_VIRT,The Credentials Virtual Register provides virtual credentials to be used when performing memory accesses using this flow to the ring or descriptors." bitfld.long 0x4 24.--25. "ATYPE,This field controls how pointers will be interpreted for Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate to.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" hexmask.long.word 0x4 0.--11. 1. "VIRTID," tree.end endif tree "NAVSS0_BCDMA_0_ALIAS64K" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_ALIAS64K_BCDMA0_CFG_TCHAN (NAVSS0_BCDMA_0_ALIAS64K_BCDMA0_CFG_TCHAN)" base ad:0x4A58400000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_BCDMA0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" rgroup.long 0x64++0xF line.long 0x0 "ALIAS64K_BCDMA0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "ALIAS64K_BCDMA0__CFG__TCHAN_TTHRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "ALIAS64K_BCDMA0__CFG__TCHAN_TVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," line.long 0xC "ALIAS64K_BCDMA0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0xC 0.--9. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_BCDMA0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s). The.." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_ALIAS64K_BCDMA0_CFG_RCHAN (NAVSS0_BCDMA_0_ALIAS64K_BCDMA0_CFG_RCHAN)" base ad:0x4A58800000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_BCDMA0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 =.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" rgroup.long 0x64++0xB line.long 0x0 "ALIAS64K_BCDMA0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "ALIAS64K_BCDMA0__CFG__RCHAN_RTHRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "ALIAS64K_BCDMA0__CFG__RCHAN_RVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_BCDMA0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s). The.." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_ALIAS64K_BCDMA0_CFG_RING (NAVSS0_BCDMA_0_ALIAS64K_BCDMA0_CFG_RING)" base ad:0x4A59000000 rgroup.long 0x40++0xB line.long 0x0 "ALIAS64K_BCDMA0__CFG__RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Ring base address (LSBs)" line.long 0x4 "ALIAS64K_BCDMA0__CFG__RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long.byte 0x4 16.--19. 1. "ASEL,Ring base address select" hexmask.long.byte 0x4 0.--3. 1. "ADDR_HI,Ring base address (MSBs)" line.long 0x8 "ALIAS64K_BCDMA0__CFG__RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and.." bitfld.long 0x8 29.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "RING_ELSIZE," "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 0.--15. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_ALIAS64K_BCDMA0_CFG_TCHANRT (NAVSS0_BCDMA_0_ALIAS64K_BCDMA0_CFG_TCHANRT)" base ad:0x4A5C000000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA channel." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1" bitfld.long 0x4 8. "TDNULL,The channel has met the conditions to do teardown" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to schedule work" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has outstanding work to do" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "ALIAS64K_BCDMA0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_ALIAS64K_BCDMA0_CFG_RCHANRT (NAVSS0_BCDMA_0_ALIAS64K_BCDMA0_CFG_RCHANRT)" base ad:0x4A5D000000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 1. "RX_STARVATION,Rx starvation. This bit is set if the port receives a packet and the ring is empty. The bit clears when the doorbell is written with a positive value." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA channel." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "RRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "RXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1" bitfld.long 0x4 24. "FIFO_BUSY,The fifo has data" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to send data" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has active transactions" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "ALIAS64K_BCDMA0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_ALIAS64K_BCDMA0_CFG_RINGRT (NAVSS0_BCDMA_0_ALIAS64K_BCDMA0_CFG_RINGRT)" base ad:0x4A5E000000 rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_BCDMA0__CFG__RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0x3 line.long 0x0 "ALIAS64K_BCDMA0__CFG__RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring.." hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." rgroup.long 0x1010++0x3 line.long 0x0 "ALIAS64K_BCDMA0__CFG__RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." bitfld.long 0x0 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register. this bit is only valid on the reverse rings (rings consumed by the Host SW)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x1018++0x3 line.long 0x0 "ALIAS64K_BCDMA0__CFG__RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring.." bitfld.long 0x0 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel. This bit is cleared anytime the tdown_ack bit is written as a 1 in the corresponding Ring N Doorbell Register. This bit is only valid on the reverse rings (rings.." "0,1" hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." tree.end endif tree.end tree "NAVSS0_BCDMA_0_BCDMA0" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_BCDMA0_CFG_GCFG (NAVSS0_BCDMA_0_BCDMA0_CFG_GCFG)" base ad:0x311A0000 rgroup.long 0x0++0x3 line.long 0x0 "BCDMA0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "BCDMA0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the BCDMA in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported." line.long 0x4 "BCDMA0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "BCDMA0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x20++0x13 line.long 0x0 "BCDMA0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this BCDMA instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" newline bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" newline bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" newline bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "BCDMA0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this BCDMA instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "BCDMA0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this BCDMA instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx split channel count" hexmask.long.word 0x8 9.--17. 1. "TCHAN_CNT,Tx split channel count" hexmask.long.word 0x8 0.--8. 1. "CHAN_CNT,BC channel count" line.long 0xC "BCDMA0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this BCDMA instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,BC ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,BC high capacity internal channel count" line.long 0x10 "BCDMA0__CFG__GCFG_CAP4,The Capabilities Register 4 specifies how many resources this BCDMA instance supports." hexmask.long.byte 0x10 24.--31. 1. "TUCHAN_CNT,TX ultra high capacity internal channel count" hexmask.long.byte 0x10 16.--23. 1. "THCHAN_CNT,TX high capacity internal channel count" hexmask.long.byte 0x10 8.--15. 1. "RUCHAN_CNT,RX ultra high capacity internal channel count" hexmask.long.byte 0x10 0.--7. 1. "RHCHAN_CNT,RX high capacity internal channel count" rgroup.long 0x60++0x7 line.long 0x0 "BCDMA0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long.tbyte 0x0 15.--31. 1. "NOGATE_RSVD4,Reserved PM signals." bitfld.long 0x0 14. "NOGATE_RDEC2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 12.--13. "NOGATE_RSVD3,Reserved PM signals." "0,1,2,3" bitfld.long 0x0 11. "NOGATE_SDEC3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 8.--10. "NOGATE_RSVD2,Reserved PM signals." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "NOGATE_WARB3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 4.--6. "NOGATE_RSVD1,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "NOGATE_CARB3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 2. "NOGATE_CARB2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 0.--1. "NOGATE_RSVD0,Reserved PM signals." "0,1,2,3" line.long 0x4 "BCDMA0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" bitfld.long 0x4 31. "NOGATE_EDC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 30. "NOGATE_STATS,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 29. "NOGATE_PROXY,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 28. "NOGATE_PSILIF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 27. "NOGATE_P2P,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 26. "NOGATE_RSVD8,Reserved PM signals." "0,1" bitfld.long 0x4 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 23. "NOGATE_RPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 22. "NOGATE_TPCF,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 21. "NOGATE_PCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 19.--20. "NOGATE_RSVD7,Reserved PM signals." "0,1,2,3" bitfld.long 0x4 18. "NOGATE_CFG,When set inhibits automatic gating of clock." "0,1" hexmask.long.byte 0x4 11.--17. 1. "NOGATE_RSVD6,Reserved PM signals." bitfld.long 0x4 10. "NOGATE_TRCU,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 9. "NOGATE_RSVD5,Reserved PM signals." "0,1" bitfld.long 0x4 8. "NOGATE_EVTCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 7. "NOGATE_RWU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 6. "NOGATE_RWU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 5. "NOGATE_RWU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 4. "NOGATE_RWU0,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 3. "NOGATE_TRU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 2. "NOGATE_TRU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 1. "NOGATE_TRU1,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 0. "NOGATE_TRU0,When set inhibits automatic gating of clock." "0,1" rgroup.long 0x78++0x7 line.long 0x0 "BCDMA0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "BCDMA0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_BCDMA0_CFG_TCHAN (NAVSS0_BCDMA_0_BCDMA0_CFG_TCHAN)" base ad:0x35840000 rgroup.long 0x0++0x3 line.long 0x0 "BCDMA0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" rgroup.long 0x64++0xF line.long 0x0 "BCDMA0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "BCDMA0__CFG__TCHAN_TTHRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from this register." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "BCDMA0__CFG__TCHAN_TVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," line.long 0xC "BCDMA0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be artificially.." hexmask.long.word 0xC 0.--9. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "BCDMA0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s). The fields in.." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_BCDMA0_CFG_RCHAN (NAVSS0_BCDMA_0_BCDMA0_CFG_RCHAN)" base ad:0x35880000 rgroup.long 0x0++0x3 line.long 0x0 "BCDMA0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 =.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" rgroup.long 0x64++0xB line.long 0x0 "BCDMA0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "BCDMA0__CFG__RCHAN_RTHRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from this register." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "BCDMA0__CFG__RCHAN_RVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," rgroup.long 0x80++0x3 line.long 0x0 "BCDMA0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s). The fields in.." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_BCDMA0_CFG_RING (NAVSS0_BCDMA_0_BCDMA0_CFG_RING)" base ad:0x35900000 rgroup.long 0x40++0xB line.long 0x0 "BCDMA0__CFG__RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this register will.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Ring base address (LSBs)" line.long 0x4 "BCDMA0__CFG__RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this register will.." hexmask.long.byte 0x4 16.--19. 1. "ASEL,Ring base address select" hexmask.long.byte 0x4 0.--3. 1. "ADDR_HI,Ring base address (MSBs)" line.long 0x8 "BCDMA0__CFG__RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and reset the.." bitfld.long 0x8 29.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "RING_ELSIZE," "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 0.--15. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_BCDMA0_CFG_TCHANRT (NAVSS0_BCDMA_0_BCDMA0_CFG_TCHANRT)" base ad:0x35C00000 rgroup.long 0x0++0x3 line.long 0x0 "BCDMA0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "BCDMA0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA channel. This.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "BCDMA0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "BCDMA0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1" bitfld.long 0x4 8. "TDNULL,The channel has met the conditions to do teardown" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to schedule work" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has outstanding work to do" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "BCDMA0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was reported by the.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "BCDMA0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "BCDMA0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "BCDMA0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "BCDMA0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "BCDMA0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "BCDMA0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "BCDMA0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "BCDMA0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "BCDMA0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "BCDMA0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "BCDMA0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "BCDMA0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "BCDMA0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "BCDMA0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "BCDMA0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "BCDMA0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "BCDMA0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "BCDMA0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "BCDMA0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_BCDMA0_CFG_RCHANRT (NAVSS0_BCDMA_0_BCDMA0_CFG_RCHANRT)" base ad:0x35D00000 rgroup.long 0x0++0x3 line.long 0x0 "BCDMA0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 1. "RX_STARVATION,Rx starvation. This bit is set if the port receives a packet and the ring is empty. The bit clears when the doorbell is written with a positive value." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "BCDMA0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA channel. This.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "BCDMA0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "RRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "RXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "BCDMA0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1" bitfld.long 0x4 24. "FIFO_BUSY,The fifo has data" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to send data" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has active transactions" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "BCDMA0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was reported by the.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "BCDMA0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "BCDMA0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "BCDMA0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "BCDMA0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "BCDMA0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "BCDMA0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "BCDMA0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "BCDMA0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "BCDMA0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "BCDMA0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "BCDMA0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "BCDMA0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "BCDMA0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "BCDMA0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "BCDMA0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "BCDMA0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "BCDMA0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "BCDMA0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "BCDMA0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_BCDMA0_CFG_RINGRT (NAVSS0_BCDMA_0_BCDMA0_CFG_RINGRT)" base ad:0x35E00000 rgroup.long 0x10++0x3 line.long 0x0 "BCDMA0__CFG__RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write operation." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0x3 line.long 0x0 "BCDMA0__CFG__RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring which can.." hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." rgroup.long 0x1010++0x3 line.long 0x0 "BCDMA0__CFG__RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write operation." bitfld.long 0x0 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register. this bit is only valid on the reverse rings (rings consumed by the Host SW)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x1018++0x3 line.long 0x0 "BCDMA0__CFG__RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring which can.." bitfld.long 0x0 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel. This bit is cleared anytime the tdown_ack bit is written as a 1 in the corresponding Ring N Doorbell Register. This bit is only valid on the reverse rings (rings.." "0,1" hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." tree.end endif tree.end tree "NAVSS0_BCDMA_0_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_0_BCDMA0_CFG_GCFG (NAVSS0_BCDMA_0_VIRT_ALIAS_0_BCDMA0_CFG_GCFG)" base ad:0x4B011A0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the BCDMA in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported." line.long 0x4 "VIRT_ALIAS_0_BCDMA0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x20++0x13 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this BCDMA instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_0_BCDMA0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this BCDMA instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_0_BCDMA0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this BCDMA instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx split channel count" hexmask.long.word 0x8 9.--17. 1. "TCHAN_CNT,Tx split channel count" hexmask.long.word 0x8 0.--8. 1. "CHAN_CNT,BC channel count" line.long 0xC "VIRT_ALIAS_0_BCDMA0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this BCDMA instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,BC ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,BC high capacity internal channel count" line.long 0x10 "VIRT_ALIAS_0_BCDMA0__CFG__GCFG_CAP4,The Capabilities Register 4 specifies how many resources this BCDMA instance supports." hexmask.long.byte 0x10 24.--31. 1. "TUCHAN_CNT,TX ultra high capacity internal channel count" hexmask.long.byte 0x10 16.--23. 1. "THCHAN_CNT,TX high capacity internal channel count" hexmask.long.byte 0x10 8.--15. 1. "RUCHAN_CNT,RX ultra high capacity internal channel count" hexmask.long.byte 0x10 0.--7. 1. "RHCHAN_CNT,RX high capacity internal channel count" rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long.tbyte 0x0 15.--31. 1. "NOGATE_RSVD4,Reserved PM signals." bitfld.long 0x0 14. "NOGATE_RDEC2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 12.--13. "NOGATE_RSVD3,Reserved PM signals." "0,1,2,3" bitfld.long 0x0 11. "NOGATE_SDEC3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 8.--10. "NOGATE_RSVD2,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "NOGATE_WARB3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 4.--6. "NOGATE_RSVD1,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "NOGATE_CARB3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 2. "NOGATE_CARB2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 0.--1. "NOGATE_RSVD0,Reserved PM signals." "0,1,2,3" line.long 0x4 "VIRT_ALIAS_0_BCDMA0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" bitfld.long 0x4 31. "NOGATE_EDC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 30. "NOGATE_STATS,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 29. "NOGATE_PROXY,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 28. "NOGATE_PSILIF,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 27. "NOGATE_P2P,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 26. "NOGATE_RSVD8,Reserved PM signals." "0,1" bitfld.long 0x4 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 23. "NOGATE_RPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 22. "NOGATE_TPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 21. "NOGATE_PCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 19.--20. "NOGATE_RSVD7,Reserved PM signals." "0,1,2,3" newline bitfld.long 0x4 18. "NOGATE_CFG,When set inhibits automatic gating of clock." "0,1" hexmask.long.byte 0x4 11.--17. 1. "NOGATE_RSVD6,Reserved PM signals." bitfld.long 0x4 10. "NOGATE_TRCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 9. "NOGATE_RSVD5,Reserved PM signals." "0,1" newline bitfld.long 0x4 8. "NOGATE_EVTCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 7. "NOGATE_RWU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 6. "NOGATE_RWU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 5. "NOGATE_RWU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 4. "NOGATE_RWU0,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 3. "NOGATE_TRU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 2. "NOGATE_TRU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 1. "NOGATE_TRU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 0. "NOGATE_TRU0,When set inhibits automatic gating of clock." "0,1" rgroup.long 0x78++0x7 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_0_BCDMA0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_0_BCDMA0_CFG_TCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_0_BCDMA0_CFG_TCHAN)" base ad:0x4B05840000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" rgroup.long 0x64++0xF line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_0_BCDMA0__CFG__TCHAN_TTHRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_0_BCDMA0__CFG__TCHAN_TVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," line.long 0xC "VIRT_ALIAS_0_BCDMA0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0xC 0.--9. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_0_BCDMA0_CFG_RCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_0_BCDMA0_CFG_RCHAN)" base ad:0x4B05880000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 =.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" rgroup.long 0x64++0xB line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_0_BCDMA0__CFG__RCHAN_RTHRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_0_BCDMA0__CFG__RCHAN_RVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_0_BCDMA0_CFG_RING (NAVSS0_BCDMA_0_VIRT_ALIAS_0_BCDMA0_CFG_RING)" base ad:0x4B05900000 rgroup.long 0x40++0xB line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_0_BCDMA0__CFG__RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long.byte 0x4 16.--19. 1. "ASEL,Ring base address select" hexmask.long.byte 0x4 0.--3. 1. "ADDR_HI,Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_0_BCDMA0__CFG__RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and.." bitfld.long 0x8 29.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "RING_ELSIZE," "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 0.--15. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_0_BCDMA0_CFG_TCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_0_BCDMA0_CFG_TCHANRT)" base ad:0x4B05C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1" bitfld.long 0x4 8. "TDNULL,The channel has met the conditions to do teardown" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to schedule work" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has outstanding work to do" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_0_BCDMA0_CFG_RCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_0_BCDMA0_CFG_RCHANRT)" base ad:0x4B05D00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 1. "RX_STARVATION,Rx starvation. This bit is set if the port receives a packet and the ring is empty. The bit clears when the doorbell is written with a positive value." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "RRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "RXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1" bitfld.long 0x4 24. "FIFO_BUSY,The fifo has data" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to send data" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has active transactions" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_0_BCDMA0_CFG_RINGRT (NAVSS0_BCDMA_0_VIRT_ALIAS_0_BCDMA0_CFG_RINGRT)" base ad:0x4B05E00000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." rgroup.long 0x1010++0x3 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." bitfld.long 0x0 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register. this bit is only valid on the reverse rings (rings consumed by the Host SW)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x1018++0x3 line.long 0x0 "VIRT_ALIAS_0_BCDMA0__CFG__RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." bitfld.long 0x0 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel. This bit is cleared anytime the tdown_ack bit is written as a 1 in the corresponding Ring N Doorbell Register. This bit is only valid on the reverse rings (rings.." "0,1" hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_1_BCDMA0_CFG_GCFG (NAVSS0_BCDMA_0_VIRT_ALIAS_1_BCDMA0_CFG_GCFG)" base ad:0x4B111A0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the BCDMA in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported." line.long 0x4 "VIRT_ALIAS_1_BCDMA0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x20++0x13 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this BCDMA instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_1_BCDMA0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this BCDMA instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_1_BCDMA0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this BCDMA instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx split channel count" hexmask.long.word 0x8 9.--17. 1. "TCHAN_CNT,Tx split channel count" hexmask.long.word 0x8 0.--8. 1. "CHAN_CNT,BC channel count" line.long 0xC "VIRT_ALIAS_1_BCDMA0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this BCDMA instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,BC ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,BC high capacity internal channel count" line.long 0x10 "VIRT_ALIAS_1_BCDMA0__CFG__GCFG_CAP4,The Capabilities Register 4 specifies how many resources this BCDMA instance supports." hexmask.long.byte 0x10 24.--31. 1. "TUCHAN_CNT,TX ultra high capacity internal channel count" hexmask.long.byte 0x10 16.--23. 1. "THCHAN_CNT,TX high capacity internal channel count" hexmask.long.byte 0x10 8.--15. 1. "RUCHAN_CNT,RX ultra high capacity internal channel count" hexmask.long.byte 0x10 0.--7. 1. "RHCHAN_CNT,RX high capacity internal channel count" rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long.tbyte 0x0 15.--31. 1. "NOGATE_RSVD4,Reserved PM signals." bitfld.long 0x0 14. "NOGATE_RDEC2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 12.--13. "NOGATE_RSVD3,Reserved PM signals." "0,1,2,3" bitfld.long 0x0 11. "NOGATE_SDEC3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 8.--10. "NOGATE_RSVD2,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "NOGATE_WARB3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 4.--6. "NOGATE_RSVD1,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "NOGATE_CARB3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 2. "NOGATE_CARB2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 0.--1. "NOGATE_RSVD0,Reserved PM signals." "0,1,2,3" line.long 0x4 "VIRT_ALIAS_1_BCDMA0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" bitfld.long 0x4 31. "NOGATE_EDC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 30. "NOGATE_STATS,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 29. "NOGATE_PROXY,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 28. "NOGATE_PSILIF,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 27. "NOGATE_P2P,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 26. "NOGATE_RSVD8,Reserved PM signals." "0,1" bitfld.long 0x4 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 23. "NOGATE_RPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 22. "NOGATE_TPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 21. "NOGATE_PCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 19.--20. "NOGATE_RSVD7,Reserved PM signals." "0,1,2,3" newline bitfld.long 0x4 18. "NOGATE_CFG,When set inhibits automatic gating of clock." "0,1" hexmask.long.byte 0x4 11.--17. 1. "NOGATE_RSVD6,Reserved PM signals." bitfld.long 0x4 10. "NOGATE_TRCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 9. "NOGATE_RSVD5,Reserved PM signals." "0,1" newline bitfld.long 0x4 8. "NOGATE_EVTCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 7. "NOGATE_RWU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 6. "NOGATE_RWU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 5. "NOGATE_RWU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 4. "NOGATE_RWU0,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 3. "NOGATE_TRU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 2. "NOGATE_TRU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 1. "NOGATE_TRU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 0. "NOGATE_TRU0,When set inhibits automatic gating of clock." "0,1" rgroup.long 0x78++0x7 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_1_BCDMA0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_1_BCDMA0_CFG_TCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_1_BCDMA0_CFG_TCHAN)" base ad:0x4B15840000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" rgroup.long 0x64++0xF line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_1_BCDMA0__CFG__TCHAN_TTHRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_1_BCDMA0__CFG__TCHAN_TVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," line.long 0xC "VIRT_ALIAS_1_BCDMA0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0xC 0.--9. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_1_BCDMA0_CFG_RCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_1_BCDMA0_CFG_RCHAN)" base ad:0x4B15880000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 =.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" rgroup.long 0x64++0xB line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_1_BCDMA0__CFG__RCHAN_RTHRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_1_BCDMA0__CFG__RCHAN_RVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_1_BCDMA0_CFG_RING (NAVSS0_BCDMA_0_VIRT_ALIAS_1_BCDMA0_CFG_RING)" base ad:0x4B15900000 rgroup.long 0x40++0xB line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_1_BCDMA0__CFG__RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long.byte 0x4 16.--19. 1. "ASEL,Ring base address select" hexmask.long.byte 0x4 0.--3. 1. "ADDR_HI,Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_1_BCDMA0__CFG__RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and.." bitfld.long 0x8 29.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "RING_ELSIZE," "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 0.--15. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_1_BCDMA0_CFG_TCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_1_BCDMA0_CFG_TCHANRT)" base ad:0x4B15C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1" bitfld.long 0x4 8. "TDNULL,The channel has met the conditions to do teardown" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to schedule work" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has outstanding work to do" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_1_BCDMA0_CFG_RCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_1_BCDMA0_CFG_RCHANRT)" base ad:0x4B15D00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 1. "RX_STARVATION,Rx starvation. This bit is set if the port receives a packet and the ring is empty. The bit clears when the doorbell is written with a positive value." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "RRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "RXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1" bitfld.long 0x4 24. "FIFO_BUSY,The fifo has data" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to send data" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has active transactions" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_1_BCDMA0_CFG_RINGRT (NAVSS0_BCDMA_0_VIRT_ALIAS_1_BCDMA0_CFG_RINGRT)" base ad:0x4B15E00000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." rgroup.long 0x1010++0x3 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." bitfld.long 0x0 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register. this bit is only valid on the reverse rings (rings consumed by the Host SW)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x1018++0x3 line.long 0x0 "VIRT_ALIAS_1_BCDMA0__CFG__RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." bitfld.long 0x0 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel. This bit is cleared anytime the tdown_ack bit is written as a 1 in the corresponding Ring N Doorbell Register. This bit is only valid on the reverse rings (rings.." "0,1" hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_2_BCDMA0_CFG_GCFG (NAVSS0_BCDMA_0_VIRT_ALIAS_2_BCDMA0_CFG_GCFG)" base ad:0x4B211A0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the BCDMA in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported." line.long 0x4 "VIRT_ALIAS_2_BCDMA0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x20++0x13 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this BCDMA instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_2_BCDMA0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this BCDMA instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_2_BCDMA0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this BCDMA instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx split channel count" hexmask.long.word 0x8 9.--17. 1. "TCHAN_CNT,Tx split channel count" hexmask.long.word 0x8 0.--8. 1. "CHAN_CNT,BC channel count" line.long 0xC "VIRT_ALIAS_2_BCDMA0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this BCDMA instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,BC ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,BC high capacity internal channel count" line.long 0x10 "VIRT_ALIAS_2_BCDMA0__CFG__GCFG_CAP4,The Capabilities Register 4 specifies how many resources this BCDMA instance supports." hexmask.long.byte 0x10 24.--31. 1. "TUCHAN_CNT,TX ultra high capacity internal channel count" hexmask.long.byte 0x10 16.--23. 1. "THCHAN_CNT,TX high capacity internal channel count" hexmask.long.byte 0x10 8.--15. 1. "RUCHAN_CNT,RX ultra high capacity internal channel count" hexmask.long.byte 0x10 0.--7. 1. "RHCHAN_CNT,RX high capacity internal channel count" rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long.tbyte 0x0 15.--31. 1. "NOGATE_RSVD4,Reserved PM signals." bitfld.long 0x0 14. "NOGATE_RDEC2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 12.--13. "NOGATE_RSVD3,Reserved PM signals." "0,1,2,3" bitfld.long 0x0 11. "NOGATE_SDEC3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 8.--10. "NOGATE_RSVD2,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "NOGATE_WARB3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 4.--6. "NOGATE_RSVD1,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "NOGATE_CARB3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 2. "NOGATE_CARB2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 0.--1. "NOGATE_RSVD0,Reserved PM signals." "0,1,2,3" line.long 0x4 "VIRT_ALIAS_2_BCDMA0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" bitfld.long 0x4 31. "NOGATE_EDC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 30. "NOGATE_STATS,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 29. "NOGATE_PROXY,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 28. "NOGATE_PSILIF,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 27. "NOGATE_P2P,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 26. "NOGATE_RSVD8,Reserved PM signals." "0,1" bitfld.long 0x4 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 23. "NOGATE_RPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 22. "NOGATE_TPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 21. "NOGATE_PCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 19.--20. "NOGATE_RSVD7,Reserved PM signals." "0,1,2,3" newline bitfld.long 0x4 18. "NOGATE_CFG,When set inhibits automatic gating of clock." "0,1" hexmask.long.byte 0x4 11.--17. 1. "NOGATE_RSVD6,Reserved PM signals." bitfld.long 0x4 10. "NOGATE_TRCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 9. "NOGATE_RSVD5,Reserved PM signals." "0,1" newline bitfld.long 0x4 8. "NOGATE_EVTCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 7. "NOGATE_RWU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 6. "NOGATE_RWU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 5. "NOGATE_RWU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 4. "NOGATE_RWU0,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 3. "NOGATE_TRU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 2. "NOGATE_TRU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 1. "NOGATE_TRU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 0. "NOGATE_TRU0,When set inhibits automatic gating of clock." "0,1" rgroup.long 0x78++0x7 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_2_BCDMA0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_2_BCDMA0_CFG_TCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_2_BCDMA0_CFG_TCHAN)" base ad:0x4B25840000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" rgroup.long 0x64++0xF line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_2_BCDMA0__CFG__TCHAN_TTHRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_2_BCDMA0__CFG__TCHAN_TVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," line.long 0xC "VIRT_ALIAS_2_BCDMA0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0xC 0.--9. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_2_BCDMA0_CFG_RCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_2_BCDMA0_CFG_RCHAN)" base ad:0x4B25880000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 =.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" rgroup.long 0x64++0xB line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_2_BCDMA0__CFG__RCHAN_RTHRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_2_BCDMA0__CFG__RCHAN_RVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_2_BCDMA0_CFG_RING (NAVSS0_BCDMA_0_VIRT_ALIAS_2_BCDMA0_CFG_RING)" base ad:0x4B25900000 rgroup.long 0x40++0xB line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_2_BCDMA0__CFG__RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long.byte 0x4 16.--19. 1. "ASEL,Ring base address select" hexmask.long.byte 0x4 0.--3. 1. "ADDR_HI,Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_2_BCDMA0__CFG__RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and.." bitfld.long 0x8 29.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "RING_ELSIZE," "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 0.--15. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_2_BCDMA0_CFG_TCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_2_BCDMA0_CFG_TCHANRT)" base ad:0x4B25C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1" bitfld.long 0x4 8. "TDNULL,The channel has met the conditions to do teardown" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to schedule work" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has outstanding work to do" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_2_BCDMA0_CFG_RCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_2_BCDMA0_CFG_RCHANRT)" base ad:0x4B25D00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 1. "RX_STARVATION,Rx starvation. This bit is set if the port receives a packet and the ring is empty. The bit clears when the doorbell is written with a positive value." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "RRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "RXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1" bitfld.long 0x4 24. "FIFO_BUSY,The fifo has data" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to send data" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has active transactions" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_2_BCDMA0_CFG_RINGRT (NAVSS0_BCDMA_0_VIRT_ALIAS_2_BCDMA0_CFG_RINGRT)" base ad:0x4B25E00000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." rgroup.long 0x1010++0x3 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." bitfld.long 0x0 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register. this bit is only valid on the reverse rings (rings consumed by the Host SW)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x1018++0x3 line.long 0x0 "VIRT_ALIAS_2_BCDMA0__CFG__RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." bitfld.long 0x0 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel. This bit is cleared anytime the tdown_ack bit is written as a 1 in the corresponding Ring N Doorbell Register. This bit is only valid on the reverse rings (rings.." "0,1" hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_3_BCDMA0_CFG_GCFG (NAVSS0_BCDMA_0_VIRT_ALIAS_3_BCDMA0_CFG_GCFG)" base ad:0x4B311A0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the BCDMA in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported." line.long 0x4 "VIRT_ALIAS_3_BCDMA0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x20++0x13 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this BCDMA instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_3_BCDMA0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this BCDMA instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_3_BCDMA0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this BCDMA instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx split channel count" hexmask.long.word 0x8 9.--17. 1. "TCHAN_CNT,Tx split channel count" hexmask.long.word 0x8 0.--8. 1. "CHAN_CNT,BC channel count" line.long 0xC "VIRT_ALIAS_3_BCDMA0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this BCDMA instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,BC ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,BC high capacity internal channel count" line.long 0x10 "VIRT_ALIAS_3_BCDMA0__CFG__GCFG_CAP4,The Capabilities Register 4 specifies how many resources this BCDMA instance supports." hexmask.long.byte 0x10 24.--31. 1. "TUCHAN_CNT,TX ultra high capacity internal channel count" hexmask.long.byte 0x10 16.--23. 1. "THCHAN_CNT,TX high capacity internal channel count" hexmask.long.byte 0x10 8.--15. 1. "RUCHAN_CNT,RX ultra high capacity internal channel count" hexmask.long.byte 0x10 0.--7. 1. "RHCHAN_CNT,RX high capacity internal channel count" rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long.tbyte 0x0 15.--31. 1. "NOGATE_RSVD4,Reserved PM signals." bitfld.long 0x0 14. "NOGATE_RDEC2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 12.--13. "NOGATE_RSVD3,Reserved PM signals." "0,1,2,3" bitfld.long 0x0 11. "NOGATE_SDEC3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 8.--10. "NOGATE_RSVD2,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "NOGATE_WARB3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 4.--6. "NOGATE_RSVD1,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "NOGATE_CARB3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 2. "NOGATE_CARB2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 0.--1. "NOGATE_RSVD0,Reserved PM signals." "0,1,2,3" line.long 0x4 "VIRT_ALIAS_3_BCDMA0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" bitfld.long 0x4 31. "NOGATE_EDC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 30. "NOGATE_STATS,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 29. "NOGATE_PROXY,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 28. "NOGATE_PSILIF,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 27. "NOGATE_P2P,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 26. "NOGATE_RSVD8,Reserved PM signals." "0,1" bitfld.long 0x4 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 23. "NOGATE_RPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 22. "NOGATE_TPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 21. "NOGATE_PCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 19.--20. "NOGATE_RSVD7,Reserved PM signals." "0,1,2,3" newline bitfld.long 0x4 18. "NOGATE_CFG,When set inhibits automatic gating of clock." "0,1" hexmask.long.byte 0x4 11.--17. 1. "NOGATE_RSVD6,Reserved PM signals." bitfld.long 0x4 10. "NOGATE_TRCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 9. "NOGATE_RSVD5,Reserved PM signals." "0,1" newline bitfld.long 0x4 8. "NOGATE_EVTCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 7. "NOGATE_RWU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 6. "NOGATE_RWU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 5. "NOGATE_RWU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 4. "NOGATE_RWU0,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 3. "NOGATE_TRU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 2. "NOGATE_TRU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 1. "NOGATE_TRU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 0. "NOGATE_TRU0,When set inhibits automatic gating of clock." "0,1" rgroup.long 0x78++0x7 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_3_BCDMA0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_3_BCDMA0_CFG_TCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_3_BCDMA0_CFG_TCHAN)" base ad:0x4B35840000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" rgroup.long 0x64++0xF line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_3_BCDMA0__CFG__TCHAN_TTHRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_3_BCDMA0__CFG__TCHAN_TVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," line.long 0xC "VIRT_ALIAS_3_BCDMA0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0xC 0.--9. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_3_BCDMA0_CFG_RCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_3_BCDMA0_CFG_RCHAN)" base ad:0x4B35880000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 =.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" rgroup.long 0x64++0xB line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_3_BCDMA0__CFG__RCHAN_RTHRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_3_BCDMA0__CFG__RCHAN_RVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_3_BCDMA0_CFG_RING (NAVSS0_BCDMA_0_VIRT_ALIAS_3_BCDMA0_CFG_RING)" base ad:0x4B35900000 rgroup.long 0x40++0xB line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_3_BCDMA0__CFG__RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long.byte 0x4 16.--19. 1. "ASEL,Ring base address select" hexmask.long.byte 0x4 0.--3. 1. "ADDR_HI,Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_3_BCDMA0__CFG__RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and.." bitfld.long 0x8 29.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "RING_ELSIZE," "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 0.--15. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_3_BCDMA0_CFG_TCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_3_BCDMA0_CFG_TCHANRT)" base ad:0x4B35C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1" bitfld.long 0x4 8. "TDNULL,The channel has met the conditions to do teardown" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to schedule work" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has outstanding work to do" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_3_BCDMA0_CFG_RCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_3_BCDMA0_CFG_RCHANRT)" base ad:0x4B35D00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 1. "RX_STARVATION,Rx starvation. This bit is set if the port receives a packet and the ring is empty. The bit clears when the doorbell is written with a positive value." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "RRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "RXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1" bitfld.long 0x4 24. "FIFO_BUSY,The fifo has data" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to send data" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has active transactions" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_3_BCDMA0_CFG_RINGRT (NAVSS0_BCDMA_0_VIRT_ALIAS_3_BCDMA0_CFG_RINGRT)" base ad:0x4B35E00000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." rgroup.long 0x1010++0x3 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." bitfld.long 0x0 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register. this bit is only valid on the reverse rings (rings consumed by the Host SW)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x1018++0x3 line.long 0x0 "VIRT_ALIAS_3_BCDMA0__CFG__RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." bitfld.long 0x0 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel. This bit is cleared anytime the tdown_ack bit is written as a 1 in the corresponding Ring N Doorbell Register. This bit is only valid on the reverse rings (rings.." "0,1" hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_4_BCDMA0_CFG_GCFG (NAVSS0_BCDMA_0_VIRT_ALIAS_4_BCDMA0_CFG_GCFG)" base ad:0x4B411A0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the BCDMA in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported." line.long 0x4 "VIRT_ALIAS_4_BCDMA0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x20++0x13 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this BCDMA instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_4_BCDMA0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this BCDMA instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_4_BCDMA0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this BCDMA instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx split channel count" hexmask.long.word 0x8 9.--17. 1. "TCHAN_CNT,Tx split channel count" hexmask.long.word 0x8 0.--8. 1. "CHAN_CNT,BC channel count" line.long 0xC "VIRT_ALIAS_4_BCDMA0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this BCDMA instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,BC ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,BC high capacity internal channel count" line.long 0x10 "VIRT_ALIAS_4_BCDMA0__CFG__GCFG_CAP4,The Capabilities Register 4 specifies how many resources this BCDMA instance supports." hexmask.long.byte 0x10 24.--31. 1. "TUCHAN_CNT,TX ultra high capacity internal channel count" hexmask.long.byte 0x10 16.--23. 1. "THCHAN_CNT,TX high capacity internal channel count" hexmask.long.byte 0x10 8.--15. 1. "RUCHAN_CNT,RX ultra high capacity internal channel count" hexmask.long.byte 0x10 0.--7. 1. "RHCHAN_CNT,RX high capacity internal channel count" rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long.tbyte 0x0 15.--31. 1. "NOGATE_RSVD4,Reserved PM signals." bitfld.long 0x0 14. "NOGATE_RDEC2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 12.--13. "NOGATE_RSVD3,Reserved PM signals." "0,1,2,3" bitfld.long 0x0 11. "NOGATE_SDEC3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 8.--10. "NOGATE_RSVD2,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "NOGATE_WARB3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 4.--6. "NOGATE_RSVD1,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "NOGATE_CARB3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 2. "NOGATE_CARB2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 0.--1. "NOGATE_RSVD0,Reserved PM signals." "0,1,2,3" line.long 0x4 "VIRT_ALIAS_4_BCDMA0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" bitfld.long 0x4 31. "NOGATE_EDC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 30. "NOGATE_STATS,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 29. "NOGATE_PROXY,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 28. "NOGATE_PSILIF,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 27. "NOGATE_P2P,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 26. "NOGATE_RSVD8,Reserved PM signals." "0,1" bitfld.long 0x4 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 23. "NOGATE_RPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 22. "NOGATE_TPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 21. "NOGATE_PCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 19.--20. "NOGATE_RSVD7,Reserved PM signals." "0,1,2,3" newline bitfld.long 0x4 18. "NOGATE_CFG,When set inhibits automatic gating of clock." "0,1" hexmask.long.byte 0x4 11.--17. 1. "NOGATE_RSVD6,Reserved PM signals." bitfld.long 0x4 10. "NOGATE_TRCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 9. "NOGATE_RSVD5,Reserved PM signals." "0,1" newline bitfld.long 0x4 8. "NOGATE_EVTCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 7. "NOGATE_RWU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 6. "NOGATE_RWU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 5. "NOGATE_RWU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 4. "NOGATE_RWU0,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 3. "NOGATE_TRU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 2. "NOGATE_TRU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 1. "NOGATE_TRU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 0. "NOGATE_TRU0,When set inhibits automatic gating of clock." "0,1" rgroup.long 0x78++0x7 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_4_BCDMA0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_4_BCDMA0_CFG_TCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_4_BCDMA0_CFG_TCHAN)" base ad:0x4B45840000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" rgroup.long 0x64++0xF line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_4_BCDMA0__CFG__TCHAN_TTHRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_4_BCDMA0__CFG__TCHAN_TVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," line.long 0xC "VIRT_ALIAS_4_BCDMA0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0xC 0.--9. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_4_BCDMA0_CFG_RCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_4_BCDMA0_CFG_RCHAN)" base ad:0x4B45880000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 =.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" rgroup.long 0x64++0xB line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_4_BCDMA0__CFG__RCHAN_RTHRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_4_BCDMA0__CFG__RCHAN_RVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_4_BCDMA0_CFG_RING (NAVSS0_BCDMA_0_VIRT_ALIAS_4_BCDMA0_CFG_RING)" base ad:0x4B45900000 rgroup.long 0x40++0xB line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_4_BCDMA0__CFG__RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long.byte 0x4 16.--19. 1. "ASEL,Ring base address select" hexmask.long.byte 0x4 0.--3. 1. "ADDR_HI,Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_4_BCDMA0__CFG__RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and.." bitfld.long 0x8 29.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "RING_ELSIZE," "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 0.--15. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_4_BCDMA0_CFG_TCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_4_BCDMA0_CFG_TCHANRT)" base ad:0x4B45C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1" bitfld.long 0x4 8. "TDNULL,The channel has met the conditions to do teardown" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to schedule work" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has outstanding work to do" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_4_BCDMA0_CFG_RCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_4_BCDMA0_CFG_RCHANRT)" base ad:0x4B45D00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 1. "RX_STARVATION,Rx starvation. This bit is set if the port receives a packet and the ring is empty. The bit clears when the doorbell is written with a positive value." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "RRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "RXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1" bitfld.long 0x4 24. "FIFO_BUSY,The fifo has data" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to send data" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has active transactions" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_4_BCDMA0_CFG_RINGRT (NAVSS0_BCDMA_0_VIRT_ALIAS_4_BCDMA0_CFG_RINGRT)" base ad:0x4B45E00000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." rgroup.long 0x1010++0x3 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." bitfld.long 0x0 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register. this bit is only valid on the reverse rings (rings consumed by the Host SW)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x1018++0x3 line.long 0x0 "VIRT_ALIAS_4_BCDMA0__CFG__RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." bitfld.long 0x0 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel. This bit is cleared anytime the tdown_ack bit is written as a 1 in the corresponding Ring N Doorbell Register. This bit is only valid on the reverse rings (rings.." "0,1" hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_5_BCDMA0_CFG_GCFG (NAVSS0_BCDMA_0_VIRT_ALIAS_5_BCDMA0_CFG_GCFG)" base ad:0x4B511A0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the BCDMA in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported." line.long 0x4 "VIRT_ALIAS_5_BCDMA0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x20++0x13 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this BCDMA instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_5_BCDMA0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this BCDMA instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_5_BCDMA0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this BCDMA instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx split channel count" hexmask.long.word 0x8 9.--17. 1. "TCHAN_CNT,Tx split channel count" hexmask.long.word 0x8 0.--8. 1. "CHAN_CNT,BC channel count" line.long 0xC "VIRT_ALIAS_5_BCDMA0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this BCDMA instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,BC ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,BC high capacity internal channel count" line.long 0x10 "VIRT_ALIAS_5_BCDMA0__CFG__GCFG_CAP4,The Capabilities Register 4 specifies how many resources this BCDMA instance supports." hexmask.long.byte 0x10 24.--31. 1. "TUCHAN_CNT,TX ultra high capacity internal channel count" hexmask.long.byte 0x10 16.--23. 1. "THCHAN_CNT,TX high capacity internal channel count" hexmask.long.byte 0x10 8.--15. 1. "RUCHAN_CNT,RX ultra high capacity internal channel count" hexmask.long.byte 0x10 0.--7. 1. "RHCHAN_CNT,RX high capacity internal channel count" rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long.tbyte 0x0 15.--31. 1. "NOGATE_RSVD4,Reserved PM signals." bitfld.long 0x0 14. "NOGATE_RDEC2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 12.--13. "NOGATE_RSVD3,Reserved PM signals." "0,1,2,3" bitfld.long 0x0 11. "NOGATE_SDEC3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 8.--10. "NOGATE_RSVD2,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "NOGATE_WARB3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 4.--6. "NOGATE_RSVD1,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "NOGATE_CARB3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 2. "NOGATE_CARB2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 0.--1. "NOGATE_RSVD0,Reserved PM signals." "0,1,2,3" line.long 0x4 "VIRT_ALIAS_5_BCDMA0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" bitfld.long 0x4 31. "NOGATE_EDC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 30. "NOGATE_STATS,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 29. "NOGATE_PROXY,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 28. "NOGATE_PSILIF,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 27. "NOGATE_P2P,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 26. "NOGATE_RSVD8,Reserved PM signals." "0,1" bitfld.long 0x4 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 23. "NOGATE_RPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 22. "NOGATE_TPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 21. "NOGATE_PCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 19.--20. "NOGATE_RSVD7,Reserved PM signals." "0,1,2,3" newline bitfld.long 0x4 18. "NOGATE_CFG,When set inhibits automatic gating of clock." "0,1" hexmask.long.byte 0x4 11.--17. 1. "NOGATE_RSVD6,Reserved PM signals." bitfld.long 0x4 10. "NOGATE_TRCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 9. "NOGATE_RSVD5,Reserved PM signals." "0,1" newline bitfld.long 0x4 8. "NOGATE_EVTCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 7. "NOGATE_RWU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 6. "NOGATE_RWU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 5. "NOGATE_RWU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 4. "NOGATE_RWU0,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 3. "NOGATE_TRU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 2. "NOGATE_TRU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 1. "NOGATE_TRU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 0. "NOGATE_TRU0,When set inhibits automatic gating of clock." "0,1" rgroup.long 0x78++0x7 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_5_BCDMA0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_5_BCDMA0_CFG_TCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_5_BCDMA0_CFG_TCHAN)" base ad:0x4B55840000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" rgroup.long 0x64++0xF line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_5_BCDMA0__CFG__TCHAN_TTHRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_5_BCDMA0__CFG__TCHAN_TVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," line.long 0xC "VIRT_ALIAS_5_BCDMA0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0xC 0.--9. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_5_BCDMA0_CFG_RCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_5_BCDMA0_CFG_RCHAN)" base ad:0x4B55880000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 =.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" rgroup.long 0x64++0xB line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_5_BCDMA0__CFG__RCHAN_RTHRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_5_BCDMA0__CFG__RCHAN_RVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_5_BCDMA0_CFG_RING (NAVSS0_BCDMA_0_VIRT_ALIAS_5_BCDMA0_CFG_RING)" base ad:0x4B55900000 rgroup.long 0x40++0xB line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_5_BCDMA0__CFG__RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long.byte 0x4 16.--19. 1. "ASEL,Ring base address select" hexmask.long.byte 0x4 0.--3. 1. "ADDR_HI,Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_5_BCDMA0__CFG__RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and.." bitfld.long 0x8 29.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "RING_ELSIZE," "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 0.--15. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_5_BCDMA0_CFG_TCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_5_BCDMA0_CFG_TCHANRT)" base ad:0x4B55C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1" bitfld.long 0x4 8. "TDNULL,The channel has met the conditions to do teardown" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to schedule work" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has outstanding work to do" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_5_BCDMA0_CFG_RCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_5_BCDMA0_CFG_RCHANRT)" base ad:0x4B55D00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 1. "RX_STARVATION,Rx starvation. This bit is set if the port receives a packet and the ring is empty. The bit clears when the doorbell is written with a positive value." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "RRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "RXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1" bitfld.long 0x4 24. "FIFO_BUSY,The fifo has data" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to send data" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has active transactions" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_5_BCDMA0_CFG_RINGRT (NAVSS0_BCDMA_0_VIRT_ALIAS_5_BCDMA0_CFG_RINGRT)" base ad:0x4B55E00000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." rgroup.long 0x1010++0x3 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." bitfld.long 0x0 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register. this bit is only valid on the reverse rings (rings consumed by the Host SW)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x1018++0x3 line.long 0x0 "VIRT_ALIAS_5_BCDMA0__CFG__RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." bitfld.long 0x0 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel. This bit is cleared anytime the tdown_ack bit is written as a 1 in the corresponding Ring N Doorbell Register. This bit is only valid on the reverse rings (rings.." "0,1" hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_6_BCDMA0_CFG_GCFG (NAVSS0_BCDMA_0_VIRT_ALIAS_6_BCDMA0_CFG_GCFG)" base ad:0x4B611A0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the BCDMA in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported." line.long 0x4 "VIRT_ALIAS_6_BCDMA0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x20++0x13 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this BCDMA instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_6_BCDMA0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this BCDMA instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_6_BCDMA0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this BCDMA instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx split channel count" hexmask.long.word 0x8 9.--17. 1. "TCHAN_CNT,Tx split channel count" hexmask.long.word 0x8 0.--8. 1. "CHAN_CNT,BC channel count" line.long 0xC "VIRT_ALIAS_6_BCDMA0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this BCDMA instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,BC ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,BC high capacity internal channel count" line.long 0x10 "VIRT_ALIAS_6_BCDMA0__CFG__GCFG_CAP4,The Capabilities Register 4 specifies how many resources this BCDMA instance supports." hexmask.long.byte 0x10 24.--31. 1. "TUCHAN_CNT,TX ultra high capacity internal channel count" hexmask.long.byte 0x10 16.--23. 1. "THCHAN_CNT,TX high capacity internal channel count" hexmask.long.byte 0x10 8.--15. 1. "RUCHAN_CNT,RX ultra high capacity internal channel count" hexmask.long.byte 0x10 0.--7. 1. "RHCHAN_CNT,RX high capacity internal channel count" rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long.tbyte 0x0 15.--31. 1. "NOGATE_RSVD4,Reserved PM signals." bitfld.long 0x0 14. "NOGATE_RDEC2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 12.--13. "NOGATE_RSVD3,Reserved PM signals." "0,1,2,3" bitfld.long 0x0 11. "NOGATE_SDEC3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 8.--10. "NOGATE_RSVD2,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "NOGATE_WARB3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 4.--6. "NOGATE_RSVD1,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "NOGATE_CARB3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 2. "NOGATE_CARB2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 0.--1. "NOGATE_RSVD0,Reserved PM signals." "0,1,2,3" line.long 0x4 "VIRT_ALIAS_6_BCDMA0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" bitfld.long 0x4 31. "NOGATE_EDC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 30. "NOGATE_STATS,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 29. "NOGATE_PROXY,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 28. "NOGATE_PSILIF,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 27. "NOGATE_P2P,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 26. "NOGATE_RSVD8,Reserved PM signals." "0,1" bitfld.long 0x4 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 23. "NOGATE_RPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 22. "NOGATE_TPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 21. "NOGATE_PCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 19.--20. "NOGATE_RSVD7,Reserved PM signals." "0,1,2,3" newline bitfld.long 0x4 18. "NOGATE_CFG,When set inhibits automatic gating of clock." "0,1" hexmask.long.byte 0x4 11.--17. 1. "NOGATE_RSVD6,Reserved PM signals." bitfld.long 0x4 10. "NOGATE_TRCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 9. "NOGATE_RSVD5,Reserved PM signals." "0,1" newline bitfld.long 0x4 8. "NOGATE_EVTCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 7. "NOGATE_RWU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 6. "NOGATE_RWU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 5. "NOGATE_RWU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 4. "NOGATE_RWU0,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 3. "NOGATE_TRU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 2. "NOGATE_TRU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 1. "NOGATE_TRU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 0. "NOGATE_TRU0,When set inhibits automatic gating of clock." "0,1" rgroup.long 0x78++0x7 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_6_BCDMA0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_6_BCDMA0_CFG_TCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_6_BCDMA0_CFG_TCHAN)" base ad:0x4B65840000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" rgroup.long 0x64++0xF line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_6_BCDMA0__CFG__TCHAN_TTHRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_6_BCDMA0__CFG__TCHAN_TVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," line.long 0xC "VIRT_ALIAS_6_BCDMA0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0xC 0.--9. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_6_BCDMA0_CFG_RCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_6_BCDMA0_CFG_RCHAN)" base ad:0x4B65880000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 =.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" rgroup.long 0x64++0xB line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_6_BCDMA0__CFG__RCHAN_RTHRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_6_BCDMA0__CFG__RCHAN_RVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_6_BCDMA0_CFG_RING (NAVSS0_BCDMA_0_VIRT_ALIAS_6_BCDMA0_CFG_RING)" base ad:0x4B65900000 rgroup.long 0x40++0xB line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_6_BCDMA0__CFG__RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long.byte 0x4 16.--19. 1. "ASEL,Ring base address select" hexmask.long.byte 0x4 0.--3. 1. "ADDR_HI,Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_6_BCDMA0__CFG__RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and.." bitfld.long 0x8 29.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "RING_ELSIZE," "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 0.--15. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_6_BCDMA0_CFG_TCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_6_BCDMA0_CFG_TCHANRT)" base ad:0x4B65C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1" bitfld.long 0x4 8. "TDNULL,The channel has met the conditions to do teardown" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to schedule work" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has outstanding work to do" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_6_BCDMA0_CFG_RCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_6_BCDMA0_CFG_RCHANRT)" base ad:0x4B65D00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 1. "RX_STARVATION,Rx starvation. This bit is set if the port receives a packet and the ring is empty. The bit clears when the doorbell is written with a positive value." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "RRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "RXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1" bitfld.long 0x4 24. "FIFO_BUSY,The fifo has data" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to send data" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has active transactions" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_6_BCDMA0_CFG_RINGRT (NAVSS0_BCDMA_0_VIRT_ALIAS_6_BCDMA0_CFG_RINGRT)" base ad:0x4B65E00000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." rgroup.long 0x1010++0x3 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." bitfld.long 0x0 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register. this bit is only valid on the reverse rings (rings consumed by the Host SW)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x1018++0x3 line.long 0x0 "VIRT_ALIAS_6_BCDMA0__CFG__RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." bitfld.long 0x0 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel. This bit is cleared anytime the tdown_ack bit is written as a 1 in the corresponding Ring N Doorbell Register. This bit is only valid on the reverse rings (rings.." "0,1" hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_7_BCDMA0_CFG_GCFG (NAVSS0_BCDMA_0_VIRT_ALIAS_7_BCDMA0_CFG_GCFG)" base ad:0x4B711A0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the BCDMA in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported." line.long 0x4 "VIRT_ALIAS_7_BCDMA0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x20++0x13 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this BCDMA instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_7_BCDMA0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this BCDMA instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_7_BCDMA0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this BCDMA instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx split channel count" hexmask.long.word 0x8 9.--17. 1. "TCHAN_CNT,Tx split channel count" hexmask.long.word 0x8 0.--8. 1. "CHAN_CNT,BC channel count" line.long 0xC "VIRT_ALIAS_7_BCDMA0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this BCDMA instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,BC ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,BC high capacity internal channel count" line.long 0x10 "VIRT_ALIAS_7_BCDMA0__CFG__GCFG_CAP4,The Capabilities Register 4 specifies how many resources this BCDMA instance supports." hexmask.long.byte 0x10 24.--31. 1. "TUCHAN_CNT,TX ultra high capacity internal channel count" hexmask.long.byte 0x10 16.--23. 1. "THCHAN_CNT,TX high capacity internal channel count" hexmask.long.byte 0x10 8.--15. 1. "RUCHAN_CNT,RX ultra high capacity internal channel count" hexmask.long.byte 0x10 0.--7. 1. "RHCHAN_CNT,RX high capacity internal channel count" rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long.tbyte 0x0 15.--31. 1. "NOGATE_RSVD4,Reserved PM signals." bitfld.long 0x0 14. "NOGATE_RDEC2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 12.--13. "NOGATE_RSVD3,Reserved PM signals." "0,1,2,3" bitfld.long 0x0 11. "NOGATE_SDEC3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 8.--10. "NOGATE_RSVD2,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "NOGATE_WARB3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 4.--6. "NOGATE_RSVD1,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "NOGATE_CARB3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 2. "NOGATE_CARB2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 0.--1. "NOGATE_RSVD0,Reserved PM signals." "0,1,2,3" line.long 0x4 "VIRT_ALIAS_7_BCDMA0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" bitfld.long 0x4 31. "NOGATE_EDC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 30. "NOGATE_STATS,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 29. "NOGATE_PROXY,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 28. "NOGATE_PSILIF,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 27. "NOGATE_P2P,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 26. "NOGATE_RSVD8,Reserved PM signals." "0,1" bitfld.long 0x4 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 23. "NOGATE_RPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 22. "NOGATE_TPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 21. "NOGATE_PCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 19.--20. "NOGATE_RSVD7,Reserved PM signals." "0,1,2,3" newline bitfld.long 0x4 18. "NOGATE_CFG,When set inhibits automatic gating of clock." "0,1" hexmask.long.byte 0x4 11.--17. 1. "NOGATE_RSVD6,Reserved PM signals." bitfld.long 0x4 10. "NOGATE_TRCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 9. "NOGATE_RSVD5,Reserved PM signals." "0,1" newline bitfld.long 0x4 8. "NOGATE_EVTCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 7. "NOGATE_RWU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 6. "NOGATE_RWU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 5. "NOGATE_RWU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 4. "NOGATE_RWU0,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 3. "NOGATE_TRU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 2. "NOGATE_TRU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 1. "NOGATE_TRU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 0. "NOGATE_TRU0,When set inhibits automatic gating of clock." "0,1" rgroup.long 0x78++0x7 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_7_BCDMA0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_7_BCDMA0_CFG_TCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_7_BCDMA0_CFG_TCHAN)" base ad:0x4B75840000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" rgroup.long 0x64++0xF line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_7_BCDMA0__CFG__TCHAN_TTHRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_7_BCDMA0__CFG__TCHAN_TVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," line.long 0xC "VIRT_ALIAS_7_BCDMA0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0xC 0.--9. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_7_BCDMA0_CFG_RCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_7_BCDMA0_CFG_RCHAN)" base ad:0x4B75880000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 =.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" rgroup.long 0x64++0xB line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_7_BCDMA0__CFG__RCHAN_RTHRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_7_BCDMA0__CFG__RCHAN_RVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_7_BCDMA0_CFG_RING (NAVSS0_BCDMA_0_VIRT_ALIAS_7_BCDMA0_CFG_RING)" base ad:0x4B75900000 rgroup.long 0x40++0xB line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_7_BCDMA0__CFG__RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long.byte 0x4 16.--19. 1. "ASEL,Ring base address select" hexmask.long.byte 0x4 0.--3. 1. "ADDR_HI,Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_7_BCDMA0__CFG__RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and.." bitfld.long 0x8 29.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "RING_ELSIZE," "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 0.--15. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_7_BCDMA0_CFG_TCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_7_BCDMA0_CFG_TCHANRT)" base ad:0x4B75C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1" bitfld.long 0x4 8. "TDNULL,The channel has met the conditions to do teardown" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to schedule work" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has outstanding work to do" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_7_BCDMA0_CFG_RCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_7_BCDMA0_CFG_RCHANRT)" base ad:0x4B75D00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 1. "RX_STARVATION,Rx starvation. This bit is set if the port receives a packet and the ring is empty. The bit clears when the doorbell is written with a positive value." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "RRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "RXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1" bitfld.long 0x4 24. "FIFO_BUSY,The fifo has data" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to send data" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has active transactions" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_7_BCDMA0_CFG_RINGRT (NAVSS0_BCDMA_0_VIRT_ALIAS_7_BCDMA0_CFG_RINGRT)" base ad:0x4B75E00000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." rgroup.long 0x1010++0x3 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." bitfld.long 0x0 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register. this bit is only valid on the reverse rings (rings consumed by the Host SW)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x1018++0x3 line.long 0x0 "VIRT_ALIAS_7_BCDMA0__CFG__RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." bitfld.long 0x0 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel. This bit is cleared anytime the tdown_ack bit is written as a 1 in the corresponding Ring N Doorbell Register. This bit is only valid on the reverse rings (rings.." "0,1" hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_8_BCDMA0_CFG_GCFG (NAVSS0_BCDMA_0_VIRT_ALIAS_8_BCDMA0_CFG_GCFG)" base ad:0x4B811A0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the BCDMA in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported." line.long 0x4 "VIRT_ALIAS_8_BCDMA0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x20++0x13 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this BCDMA instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_8_BCDMA0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this BCDMA instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_8_BCDMA0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this BCDMA instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx split channel count" hexmask.long.word 0x8 9.--17. 1. "TCHAN_CNT,Tx split channel count" hexmask.long.word 0x8 0.--8. 1. "CHAN_CNT,BC channel count" line.long 0xC "VIRT_ALIAS_8_BCDMA0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this BCDMA instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,BC ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,BC high capacity internal channel count" line.long 0x10 "VIRT_ALIAS_8_BCDMA0__CFG__GCFG_CAP4,The Capabilities Register 4 specifies how many resources this BCDMA instance supports." hexmask.long.byte 0x10 24.--31. 1. "TUCHAN_CNT,TX ultra high capacity internal channel count" hexmask.long.byte 0x10 16.--23. 1. "THCHAN_CNT,TX high capacity internal channel count" hexmask.long.byte 0x10 8.--15. 1. "RUCHAN_CNT,RX ultra high capacity internal channel count" hexmask.long.byte 0x10 0.--7. 1. "RHCHAN_CNT,RX high capacity internal channel count" rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long.tbyte 0x0 15.--31. 1. "NOGATE_RSVD4,Reserved PM signals." bitfld.long 0x0 14. "NOGATE_RDEC2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 12.--13. "NOGATE_RSVD3,Reserved PM signals." "0,1,2,3" bitfld.long 0x0 11. "NOGATE_SDEC3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 8.--10. "NOGATE_RSVD2,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "NOGATE_WARB3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 4.--6. "NOGATE_RSVD1,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "NOGATE_CARB3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 2. "NOGATE_CARB2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 0.--1. "NOGATE_RSVD0,Reserved PM signals." "0,1,2,3" line.long 0x4 "VIRT_ALIAS_8_BCDMA0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" bitfld.long 0x4 31. "NOGATE_EDC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 30. "NOGATE_STATS,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 29. "NOGATE_PROXY,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 28. "NOGATE_PSILIF,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 27. "NOGATE_P2P,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 26. "NOGATE_RSVD8,Reserved PM signals." "0,1" bitfld.long 0x4 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 23. "NOGATE_RPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 22. "NOGATE_TPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 21. "NOGATE_PCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 19.--20. "NOGATE_RSVD7,Reserved PM signals." "0,1,2,3" newline bitfld.long 0x4 18. "NOGATE_CFG,When set inhibits automatic gating of clock." "0,1" hexmask.long.byte 0x4 11.--17. 1. "NOGATE_RSVD6,Reserved PM signals." bitfld.long 0x4 10. "NOGATE_TRCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 9. "NOGATE_RSVD5,Reserved PM signals." "0,1" newline bitfld.long 0x4 8. "NOGATE_EVTCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 7. "NOGATE_RWU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 6. "NOGATE_RWU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 5. "NOGATE_RWU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 4. "NOGATE_RWU0,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 3. "NOGATE_TRU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 2. "NOGATE_TRU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 1. "NOGATE_TRU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 0. "NOGATE_TRU0,When set inhibits automatic gating of clock." "0,1" rgroup.long 0x78++0x7 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_8_BCDMA0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_8_BCDMA0_CFG_TCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_8_BCDMA0_CFG_TCHAN)" base ad:0x4B85840000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" rgroup.long 0x64++0xF line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_8_BCDMA0__CFG__TCHAN_TTHRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_8_BCDMA0__CFG__TCHAN_TVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," line.long 0xC "VIRT_ALIAS_8_BCDMA0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0xC 0.--9. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_8_BCDMA0_CFG_RCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_8_BCDMA0_CFG_RCHAN)" base ad:0x4B85880000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 =.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" rgroup.long 0x64++0xB line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_8_BCDMA0__CFG__RCHAN_RTHRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_8_BCDMA0__CFG__RCHAN_RVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_8_BCDMA0_CFG_RING (NAVSS0_BCDMA_0_VIRT_ALIAS_8_BCDMA0_CFG_RING)" base ad:0x4B85900000 rgroup.long 0x40++0xB line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_8_BCDMA0__CFG__RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long.byte 0x4 16.--19. 1. "ASEL,Ring base address select" hexmask.long.byte 0x4 0.--3. 1. "ADDR_HI,Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_8_BCDMA0__CFG__RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and.." bitfld.long 0x8 29.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "RING_ELSIZE," "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 0.--15. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_8_BCDMA0_CFG_TCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_8_BCDMA0_CFG_TCHANRT)" base ad:0x4B85C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1" bitfld.long 0x4 8. "TDNULL,The channel has met the conditions to do teardown" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to schedule work" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has outstanding work to do" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_8_BCDMA0_CFG_RCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_8_BCDMA0_CFG_RCHANRT)" base ad:0x4B85D00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 1. "RX_STARVATION,Rx starvation. This bit is set if the port receives a packet and the ring is empty. The bit clears when the doorbell is written with a positive value." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "RRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "RXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1" bitfld.long 0x4 24. "FIFO_BUSY,The fifo has data" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to send data" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has active transactions" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_8_BCDMA0_CFG_RINGRT (NAVSS0_BCDMA_0_VIRT_ALIAS_8_BCDMA0_CFG_RINGRT)" base ad:0x4B85E00000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." rgroup.long 0x1010++0x3 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." bitfld.long 0x0 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register. this bit is only valid on the reverse rings (rings consumed by the Host SW)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x1018++0x3 line.long 0x0 "VIRT_ALIAS_8_BCDMA0__CFG__RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." bitfld.long 0x0 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel. This bit is cleared anytime the tdown_ack bit is written as a 1 in the corresponding Ring N Doorbell Register. This bit is only valid on the reverse rings (rings.." "0,1" hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_9_BCDMA0_CFG_GCFG (NAVSS0_BCDMA_0_VIRT_ALIAS_9_BCDMA0_CFG_GCFG)" base ad:0x4B911A0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the BCDMA in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported." line.long 0x4 "VIRT_ALIAS_9_BCDMA0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x20++0x13 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this BCDMA instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_9_BCDMA0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this BCDMA instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_9_BCDMA0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this BCDMA instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx split channel count" hexmask.long.word 0x8 9.--17. 1. "TCHAN_CNT,Tx split channel count" hexmask.long.word 0x8 0.--8. 1. "CHAN_CNT,BC channel count" line.long 0xC "VIRT_ALIAS_9_BCDMA0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this BCDMA instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,BC ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,BC high capacity internal channel count" line.long 0x10 "VIRT_ALIAS_9_BCDMA0__CFG__GCFG_CAP4,The Capabilities Register 4 specifies how many resources this BCDMA instance supports." hexmask.long.byte 0x10 24.--31. 1. "TUCHAN_CNT,TX ultra high capacity internal channel count" hexmask.long.byte 0x10 16.--23. 1. "THCHAN_CNT,TX high capacity internal channel count" hexmask.long.byte 0x10 8.--15. 1. "RUCHAN_CNT,RX ultra high capacity internal channel count" hexmask.long.byte 0x10 0.--7. 1. "RHCHAN_CNT,RX high capacity internal channel count" rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long.tbyte 0x0 15.--31. 1. "NOGATE_RSVD4,Reserved PM signals." bitfld.long 0x0 14. "NOGATE_RDEC2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 12.--13. "NOGATE_RSVD3,Reserved PM signals." "0,1,2,3" bitfld.long 0x0 11. "NOGATE_SDEC3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 8.--10. "NOGATE_RSVD2,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "NOGATE_WARB3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 4.--6. "NOGATE_RSVD1,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "NOGATE_CARB3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 2. "NOGATE_CARB2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 0.--1. "NOGATE_RSVD0,Reserved PM signals." "0,1,2,3" line.long 0x4 "VIRT_ALIAS_9_BCDMA0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" bitfld.long 0x4 31. "NOGATE_EDC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 30. "NOGATE_STATS,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 29. "NOGATE_PROXY,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 28. "NOGATE_PSILIF,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 27. "NOGATE_P2P,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 26. "NOGATE_RSVD8,Reserved PM signals." "0,1" bitfld.long 0x4 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 23. "NOGATE_RPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 22. "NOGATE_TPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 21. "NOGATE_PCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 19.--20. "NOGATE_RSVD7,Reserved PM signals." "0,1,2,3" newline bitfld.long 0x4 18. "NOGATE_CFG,When set inhibits automatic gating of clock." "0,1" hexmask.long.byte 0x4 11.--17. 1. "NOGATE_RSVD6,Reserved PM signals." bitfld.long 0x4 10. "NOGATE_TRCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 9. "NOGATE_RSVD5,Reserved PM signals." "0,1" newline bitfld.long 0x4 8. "NOGATE_EVTCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 7. "NOGATE_RWU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 6. "NOGATE_RWU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 5. "NOGATE_RWU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 4. "NOGATE_RWU0,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 3. "NOGATE_TRU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 2. "NOGATE_TRU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 1. "NOGATE_TRU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 0. "NOGATE_TRU0,When set inhibits automatic gating of clock." "0,1" rgroup.long 0x78++0x7 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_9_BCDMA0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_9_BCDMA0_CFG_TCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_9_BCDMA0_CFG_TCHAN)" base ad:0x4B95840000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" rgroup.long 0x64++0xF line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_9_BCDMA0__CFG__TCHAN_TTHRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_9_BCDMA0__CFG__TCHAN_TVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," line.long 0xC "VIRT_ALIAS_9_BCDMA0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0xC 0.--9. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_9_BCDMA0_CFG_RCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_9_BCDMA0_CFG_RCHAN)" base ad:0x4B95880000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 =.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" rgroup.long 0x64++0xB line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_9_BCDMA0__CFG__RCHAN_RTHRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_9_BCDMA0__CFG__RCHAN_RVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_9_BCDMA0_CFG_RING (NAVSS0_BCDMA_0_VIRT_ALIAS_9_BCDMA0_CFG_RING)" base ad:0x4B95900000 rgroup.long 0x40++0xB line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_9_BCDMA0__CFG__RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long.byte 0x4 16.--19. 1. "ASEL,Ring base address select" hexmask.long.byte 0x4 0.--3. 1. "ADDR_HI,Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_9_BCDMA0__CFG__RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and.." bitfld.long 0x8 29.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "RING_ELSIZE," "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 0.--15. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_9_BCDMA0_CFG_TCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_9_BCDMA0_CFG_TCHANRT)" base ad:0x4B95C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1" bitfld.long 0x4 8. "TDNULL,The channel has met the conditions to do teardown" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to schedule work" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has outstanding work to do" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_9_BCDMA0_CFG_RCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_9_BCDMA0_CFG_RCHANRT)" base ad:0x4B95D00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 1. "RX_STARVATION,Rx starvation. This bit is set if the port receives a packet and the ring is empty. The bit clears when the doorbell is written with a positive value." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "RRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "RXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1" bitfld.long 0x4 24. "FIFO_BUSY,The fifo has data" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to send data" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has active transactions" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_9_BCDMA0_CFG_RINGRT (NAVSS0_BCDMA_0_VIRT_ALIAS_9_BCDMA0_CFG_RINGRT)" base ad:0x4B95E00000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." rgroup.long 0x1010++0x3 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." bitfld.long 0x0 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register. this bit is only valid on the reverse rings (rings consumed by the Host SW)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x1018++0x3 line.long 0x0 "VIRT_ALIAS_9_BCDMA0__CFG__RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." bitfld.long 0x0 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel. This bit is cleared anytime the tdown_ack bit is written as a 1 in the corresponding Ring N Doorbell Register. This bit is only valid on the reverse rings (rings.." "0,1" hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_10_BCDMA0_CFG_GCFG (NAVSS0_BCDMA_0_VIRT_ALIAS_10_BCDMA0_CFG_GCFG)" base ad:0x4BA11A0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the BCDMA in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported." line.long 0x4 "VIRT_ALIAS_10_BCDMA0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x20++0x13 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this BCDMA instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_10_BCDMA0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this BCDMA instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_10_BCDMA0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this BCDMA instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx split channel count" hexmask.long.word 0x8 9.--17. 1. "TCHAN_CNT,Tx split channel count" hexmask.long.word 0x8 0.--8. 1. "CHAN_CNT,BC channel count" line.long 0xC "VIRT_ALIAS_10_BCDMA0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this BCDMA instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,BC ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,BC high capacity internal channel count" line.long 0x10 "VIRT_ALIAS_10_BCDMA0__CFG__GCFG_CAP4,The Capabilities Register 4 specifies how many resources this BCDMA instance supports." hexmask.long.byte 0x10 24.--31. 1. "TUCHAN_CNT,TX ultra high capacity internal channel count" hexmask.long.byte 0x10 16.--23. 1. "THCHAN_CNT,TX high capacity internal channel count" hexmask.long.byte 0x10 8.--15. 1. "RUCHAN_CNT,RX ultra high capacity internal channel count" hexmask.long.byte 0x10 0.--7. 1. "RHCHAN_CNT,RX high capacity internal channel count" rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long.tbyte 0x0 15.--31. 1. "NOGATE_RSVD4,Reserved PM signals." bitfld.long 0x0 14. "NOGATE_RDEC2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 12.--13. "NOGATE_RSVD3,Reserved PM signals." "0,1,2,3" bitfld.long 0x0 11. "NOGATE_SDEC3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 8.--10. "NOGATE_RSVD2,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "NOGATE_WARB3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 4.--6. "NOGATE_RSVD1,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "NOGATE_CARB3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 2. "NOGATE_CARB2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 0.--1. "NOGATE_RSVD0,Reserved PM signals." "0,1,2,3" line.long 0x4 "VIRT_ALIAS_10_BCDMA0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" bitfld.long 0x4 31. "NOGATE_EDC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 30. "NOGATE_STATS,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 29. "NOGATE_PROXY,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 28. "NOGATE_PSILIF,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 27. "NOGATE_P2P,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 26. "NOGATE_RSVD8,Reserved PM signals." "0,1" bitfld.long 0x4 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 23. "NOGATE_RPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 22. "NOGATE_TPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 21. "NOGATE_PCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 19.--20. "NOGATE_RSVD7,Reserved PM signals." "0,1,2,3" newline bitfld.long 0x4 18. "NOGATE_CFG,When set inhibits automatic gating of clock." "0,1" hexmask.long.byte 0x4 11.--17. 1. "NOGATE_RSVD6,Reserved PM signals." bitfld.long 0x4 10. "NOGATE_TRCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 9. "NOGATE_RSVD5,Reserved PM signals." "0,1" newline bitfld.long 0x4 8. "NOGATE_EVTCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 7. "NOGATE_RWU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 6. "NOGATE_RWU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 5. "NOGATE_RWU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 4. "NOGATE_RWU0,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 3. "NOGATE_TRU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 2. "NOGATE_TRU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 1. "NOGATE_TRU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 0. "NOGATE_TRU0,When set inhibits automatic gating of clock." "0,1" rgroup.long 0x78++0x7 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_10_BCDMA0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_10_BCDMA0_CFG_TCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_10_BCDMA0_CFG_TCHAN)" base ad:0x4BA5840000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" rgroup.long 0x64++0xF line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_10_BCDMA0__CFG__TCHAN_TTHRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_10_BCDMA0__CFG__TCHAN_TVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," line.long 0xC "VIRT_ALIAS_10_BCDMA0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0xC 0.--9. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_10_BCDMA0_CFG_RCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_10_BCDMA0_CFG_RCHAN)" base ad:0x4BA5880000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 =.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" rgroup.long 0x64++0xB line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_10_BCDMA0__CFG__RCHAN_RTHRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_10_BCDMA0__CFG__RCHAN_RVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_10_BCDMA0_CFG_RING (NAVSS0_BCDMA_0_VIRT_ALIAS_10_BCDMA0_CFG_RING)" base ad:0x4BA5900000 rgroup.long 0x40++0xB line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_10_BCDMA0__CFG__RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long.byte 0x4 16.--19. 1. "ASEL,Ring base address select" hexmask.long.byte 0x4 0.--3. 1. "ADDR_HI,Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_10_BCDMA0__CFG__RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and.." bitfld.long 0x8 29.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "RING_ELSIZE," "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 0.--15. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_10_BCDMA0_CFG_TCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_10_BCDMA0_CFG_TCHANRT)" base ad:0x4BA5C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1" newline bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" newline bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" newline bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" newline bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1" newline bitfld.long 0x4 8. "TDNULL,The channel has met the conditions to do teardown" "0,1" bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to schedule work" "0,1" newline bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has outstanding work to do" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_10_BCDMA0_CFG_RCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_10_BCDMA0_CFG_RCHANRT)" base ad:0x4BA5D00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 1. "RX_STARVATION,Rx starvation. This bit is set if the port receives a packet and the ring is empty. The bit clears when the doorbell is written with a positive value." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "RRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "RXQ_PEND,The channel fifo is available" "0,1" newline bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" newline bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" newline bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" newline bitfld.long 0x0 17. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1" newline bitfld.long 0x4 24. "FIFO_BUSY,The fifo has data" "0,1" bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to send data" "0,1" newline bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has active transactions" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_10_BCDMA0_CFG_RINGRT (NAVSS0_BCDMA_0_VIRT_ALIAS_10_BCDMA0_CFG_RINGRT)" base ad:0x4BA5E00000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." rgroup.long 0x1010++0x3 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." bitfld.long 0x0 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register. this bit is only valid on the reverse rings (rings consumed by the Host SW)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x1018++0x3 line.long 0x0 "VIRT_ALIAS_10_BCDMA0__CFG__RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." bitfld.long 0x0 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel. This bit is cleared anytime the tdown_ack bit is written as a 1 in the corresponding Ring N Doorbell Register. This bit is only valid on the reverse rings (rings.." "0,1" hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_11_BCDMA0_CFG_GCFG (NAVSS0_BCDMA_0_VIRT_ALIAS_11_BCDMA0_CFG_GCFG)" base ad:0x4BB11A0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the BCDMA in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported." line.long 0x4 "VIRT_ALIAS_11_BCDMA0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x20++0x13 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this BCDMA instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_11_BCDMA0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this BCDMA instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_11_BCDMA0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this BCDMA instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx split channel count" hexmask.long.word 0x8 9.--17. 1. "TCHAN_CNT,Tx split channel count" hexmask.long.word 0x8 0.--8. 1. "CHAN_CNT,BC channel count" line.long 0xC "VIRT_ALIAS_11_BCDMA0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this BCDMA instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,BC ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,BC high capacity internal channel count" line.long 0x10 "VIRT_ALIAS_11_BCDMA0__CFG__GCFG_CAP4,The Capabilities Register 4 specifies how many resources this BCDMA instance supports." hexmask.long.byte 0x10 24.--31. 1. "TUCHAN_CNT,TX ultra high capacity internal channel count" hexmask.long.byte 0x10 16.--23. 1. "THCHAN_CNT,TX high capacity internal channel count" hexmask.long.byte 0x10 8.--15. 1. "RUCHAN_CNT,RX ultra high capacity internal channel count" hexmask.long.byte 0x10 0.--7. 1. "RHCHAN_CNT,RX high capacity internal channel count" rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long.tbyte 0x0 15.--31. 1. "NOGATE_RSVD4,Reserved PM signals." bitfld.long 0x0 14. "NOGATE_RDEC2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 12.--13. "NOGATE_RSVD3,Reserved PM signals." "0,1,2,3" bitfld.long 0x0 11. "NOGATE_SDEC3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 8.--10. "NOGATE_RSVD2,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "NOGATE_WARB3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 4.--6. "NOGATE_RSVD1,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "NOGATE_CARB3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 2. "NOGATE_CARB2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 0.--1. "NOGATE_RSVD0,Reserved PM signals." "0,1,2,3" line.long 0x4 "VIRT_ALIAS_11_BCDMA0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" bitfld.long 0x4 31. "NOGATE_EDC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 30. "NOGATE_STATS,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 29. "NOGATE_PROXY,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 28. "NOGATE_PSILIF,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 27. "NOGATE_P2P,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 26. "NOGATE_RSVD8,Reserved PM signals." "0,1" bitfld.long 0x4 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 23. "NOGATE_RPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 22. "NOGATE_TPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 21. "NOGATE_PCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 19.--20. "NOGATE_RSVD7,Reserved PM signals." "0,1,2,3" newline bitfld.long 0x4 18. "NOGATE_CFG,When set inhibits automatic gating of clock." "0,1" hexmask.long.byte 0x4 11.--17. 1. "NOGATE_RSVD6,Reserved PM signals." bitfld.long 0x4 10. "NOGATE_TRCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 9. "NOGATE_RSVD5,Reserved PM signals." "0,1" newline bitfld.long 0x4 8. "NOGATE_EVTCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 7. "NOGATE_RWU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 6. "NOGATE_RWU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 5. "NOGATE_RWU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 4. "NOGATE_RWU0,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 3. "NOGATE_TRU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 2. "NOGATE_TRU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 1. "NOGATE_TRU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 0. "NOGATE_TRU0,When set inhibits automatic gating of clock." "0,1" rgroup.long 0x78++0x7 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_11_BCDMA0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_11_BCDMA0_CFG_TCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_11_BCDMA0_CFG_TCHAN)" base ad:0x4BB5840000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" rgroup.long 0x64++0xF line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_11_BCDMA0__CFG__TCHAN_TTHRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_11_BCDMA0__CFG__TCHAN_TVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," line.long 0xC "VIRT_ALIAS_11_BCDMA0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0xC 0.--9. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_11_BCDMA0_CFG_RCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_11_BCDMA0_CFG_RCHAN)" base ad:0x4BB5880000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 =.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" rgroup.long 0x64++0xB line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_11_BCDMA0__CFG__RCHAN_RTHRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_11_BCDMA0__CFG__RCHAN_RVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_11_BCDMA0_CFG_RING (NAVSS0_BCDMA_0_VIRT_ALIAS_11_BCDMA0_CFG_RING)" base ad:0x4BB5900000 rgroup.long 0x40++0xB line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_11_BCDMA0__CFG__RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long.byte 0x4 16.--19. 1. "ASEL,Ring base address select" hexmask.long.byte 0x4 0.--3. 1. "ADDR_HI,Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_11_BCDMA0__CFG__RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and.." bitfld.long 0x8 29.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "RING_ELSIZE," "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 0.--15. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_11_BCDMA0_CFG_TCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_11_BCDMA0_CFG_TCHANRT)" base ad:0x4BB5C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1" newline bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" newline bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" newline bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" newline bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1" newline bitfld.long 0x4 8. "TDNULL,The channel has met the conditions to do teardown" "0,1" bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to schedule work" "0,1" newline bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has outstanding work to do" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_11_BCDMA0_CFG_RCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_11_BCDMA0_CFG_RCHANRT)" base ad:0x4BB5D00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 1. "RX_STARVATION,Rx starvation. This bit is set if the port receives a packet and the ring is empty. The bit clears when the doorbell is written with a positive value." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "RRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "RXQ_PEND,The channel fifo is available" "0,1" newline bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" newline bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" newline bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" newline bitfld.long 0x0 17. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1" newline bitfld.long 0x4 24. "FIFO_BUSY,The fifo has data" "0,1" bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to send data" "0,1" newline bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has active transactions" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_11_BCDMA0_CFG_RINGRT (NAVSS0_BCDMA_0_VIRT_ALIAS_11_BCDMA0_CFG_RINGRT)" base ad:0x4BB5E00000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." rgroup.long 0x1010++0x3 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." bitfld.long 0x0 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register. this bit is only valid on the reverse rings (rings consumed by the Host SW)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x1018++0x3 line.long 0x0 "VIRT_ALIAS_11_BCDMA0__CFG__RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." bitfld.long 0x0 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel. This bit is cleared anytime the tdown_ack bit is written as a 1 in the corresponding Ring N Doorbell Register. This bit is only valid on the reverse rings (rings.." "0,1" hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_12_BCDMA0_CFG_GCFG (NAVSS0_BCDMA_0_VIRT_ALIAS_12_BCDMA0_CFG_GCFG)" base ad:0x4BC11A0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the BCDMA in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported." line.long 0x4 "VIRT_ALIAS_12_BCDMA0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x20++0x13 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this BCDMA instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_12_BCDMA0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this BCDMA instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_12_BCDMA0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this BCDMA instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx split channel count" hexmask.long.word 0x8 9.--17. 1. "TCHAN_CNT,Tx split channel count" hexmask.long.word 0x8 0.--8. 1. "CHAN_CNT,BC channel count" line.long 0xC "VIRT_ALIAS_12_BCDMA0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this BCDMA instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,BC ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,BC high capacity internal channel count" line.long 0x10 "VIRT_ALIAS_12_BCDMA0__CFG__GCFG_CAP4,The Capabilities Register 4 specifies how many resources this BCDMA instance supports." hexmask.long.byte 0x10 24.--31. 1. "TUCHAN_CNT,TX ultra high capacity internal channel count" hexmask.long.byte 0x10 16.--23. 1. "THCHAN_CNT,TX high capacity internal channel count" hexmask.long.byte 0x10 8.--15. 1. "RUCHAN_CNT,RX ultra high capacity internal channel count" hexmask.long.byte 0x10 0.--7. 1. "RHCHAN_CNT,RX high capacity internal channel count" rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long.tbyte 0x0 15.--31. 1. "NOGATE_RSVD4,Reserved PM signals." bitfld.long 0x0 14. "NOGATE_RDEC2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 12.--13. "NOGATE_RSVD3,Reserved PM signals." "0,1,2,3" bitfld.long 0x0 11. "NOGATE_SDEC3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 8.--10. "NOGATE_RSVD2,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "NOGATE_WARB3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 4.--6. "NOGATE_RSVD1,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "NOGATE_CARB3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 2. "NOGATE_CARB2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 0.--1. "NOGATE_RSVD0,Reserved PM signals." "0,1,2,3" line.long 0x4 "VIRT_ALIAS_12_BCDMA0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" bitfld.long 0x4 31. "NOGATE_EDC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 30. "NOGATE_STATS,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 29. "NOGATE_PROXY,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 28. "NOGATE_PSILIF,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 27. "NOGATE_P2P,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 26. "NOGATE_RSVD8,Reserved PM signals." "0,1" bitfld.long 0x4 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 23. "NOGATE_RPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 22. "NOGATE_TPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 21. "NOGATE_PCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 19.--20. "NOGATE_RSVD7,Reserved PM signals." "0,1,2,3" newline bitfld.long 0x4 18. "NOGATE_CFG,When set inhibits automatic gating of clock." "0,1" hexmask.long.byte 0x4 11.--17. 1. "NOGATE_RSVD6,Reserved PM signals." bitfld.long 0x4 10. "NOGATE_TRCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 9. "NOGATE_RSVD5,Reserved PM signals." "0,1" newline bitfld.long 0x4 8. "NOGATE_EVTCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 7. "NOGATE_RWU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 6. "NOGATE_RWU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 5. "NOGATE_RWU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 4. "NOGATE_RWU0,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 3. "NOGATE_TRU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 2. "NOGATE_TRU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 1. "NOGATE_TRU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 0. "NOGATE_TRU0,When set inhibits automatic gating of clock." "0,1" rgroup.long 0x78++0x7 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_12_BCDMA0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_12_BCDMA0_CFG_TCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_12_BCDMA0_CFG_TCHAN)" base ad:0x4BC5840000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" rgroup.long 0x64++0xF line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_12_BCDMA0__CFG__TCHAN_TTHRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_12_BCDMA0__CFG__TCHAN_TVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," line.long 0xC "VIRT_ALIAS_12_BCDMA0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0xC 0.--9. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_12_BCDMA0_CFG_RCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_12_BCDMA0_CFG_RCHAN)" base ad:0x4BC5880000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 =.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" rgroup.long 0x64++0xB line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_12_BCDMA0__CFG__RCHAN_RTHRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_12_BCDMA0__CFG__RCHAN_RVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_12_BCDMA0_CFG_RING (NAVSS0_BCDMA_0_VIRT_ALIAS_12_BCDMA0_CFG_RING)" base ad:0x4BC5900000 rgroup.long 0x40++0xB line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_12_BCDMA0__CFG__RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long.byte 0x4 16.--19. 1. "ASEL,Ring base address select" hexmask.long.byte 0x4 0.--3. 1. "ADDR_HI,Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_12_BCDMA0__CFG__RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and.." bitfld.long 0x8 29.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "RING_ELSIZE," "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 0.--15. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_12_BCDMA0_CFG_TCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_12_BCDMA0_CFG_TCHANRT)" base ad:0x4BC5C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1" newline bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" newline bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" newline bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" newline bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1" newline bitfld.long 0x4 8. "TDNULL,The channel has met the conditions to do teardown" "0,1" bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to schedule work" "0,1" newline bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has outstanding work to do" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_12_BCDMA0_CFG_RCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_12_BCDMA0_CFG_RCHANRT)" base ad:0x4BC5D00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 1. "RX_STARVATION,Rx starvation. This bit is set if the port receives a packet and the ring is empty. The bit clears when the doorbell is written with a positive value." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "RRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "RXQ_PEND,The channel fifo is available" "0,1" newline bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" newline bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" newline bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" newline bitfld.long 0x0 17. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1" newline bitfld.long 0x4 24. "FIFO_BUSY,The fifo has data" "0,1" bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to send data" "0,1" newline bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has active transactions" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_12_BCDMA0_CFG_RINGRT (NAVSS0_BCDMA_0_VIRT_ALIAS_12_BCDMA0_CFG_RINGRT)" base ad:0x4BC5E00000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." rgroup.long 0x1010++0x3 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." bitfld.long 0x0 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register. this bit is only valid on the reverse rings (rings consumed by the Host SW)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x1018++0x3 line.long 0x0 "VIRT_ALIAS_12_BCDMA0__CFG__RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." bitfld.long 0x0 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel. This bit is cleared anytime the tdown_ack bit is written as a 1 in the corresponding Ring N Doorbell Register. This bit is only valid on the reverse rings (rings.." "0,1" hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_13_BCDMA0_CFG_GCFG (NAVSS0_BCDMA_0_VIRT_ALIAS_13_BCDMA0_CFG_GCFG)" base ad:0x4BD11A0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the BCDMA in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported." line.long 0x4 "VIRT_ALIAS_13_BCDMA0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x20++0x13 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this BCDMA instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_13_BCDMA0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this BCDMA instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_13_BCDMA0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this BCDMA instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx split channel count" hexmask.long.word 0x8 9.--17. 1. "TCHAN_CNT,Tx split channel count" hexmask.long.word 0x8 0.--8. 1. "CHAN_CNT,BC channel count" line.long 0xC "VIRT_ALIAS_13_BCDMA0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this BCDMA instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,BC ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,BC high capacity internal channel count" line.long 0x10 "VIRT_ALIAS_13_BCDMA0__CFG__GCFG_CAP4,The Capabilities Register 4 specifies how many resources this BCDMA instance supports." hexmask.long.byte 0x10 24.--31. 1. "TUCHAN_CNT,TX ultra high capacity internal channel count" hexmask.long.byte 0x10 16.--23. 1. "THCHAN_CNT,TX high capacity internal channel count" hexmask.long.byte 0x10 8.--15. 1. "RUCHAN_CNT,RX ultra high capacity internal channel count" hexmask.long.byte 0x10 0.--7. 1. "RHCHAN_CNT,RX high capacity internal channel count" rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long.tbyte 0x0 15.--31. 1. "NOGATE_RSVD4,Reserved PM signals." bitfld.long 0x0 14. "NOGATE_RDEC2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 12.--13. "NOGATE_RSVD3,Reserved PM signals." "0,1,2,3" bitfld.long 0x0 11. "NOGATE_SDEC3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 8.--10. "NOGATE_RSVD2,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "NOGATE_WARB3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 4.--6. "NOGATE_RSVD1,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "NOGATE_CARB3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 2. "NOGATE_CARB2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 0.--1. "NOGATE_RSVD0,Reserved PM signals." "0,1,2,3" line.long 0x4 "VIRT_ALIAS_13_BCDMA0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" bitfld.long 0x4 31. "NOGATE_EDC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 30. "NOGATE_STATS,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 29. "NOGATE_PROXY,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 28. "NOGATE_PSILIF,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 27. "NOGATE_P2P,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 26. "NOGATE_RSVD8,Reserved PM signals." "0,1" bitfld.long 0x4 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 23. "NOGATE_RPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 22. "NOGATE_TPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 21. "NOGATE_PCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 19.--20. "NOGATE_RSVD7,Reserved PM signals." "0,1,2,3" newline bitfld.long 0x4 18. "NOGATE_CFG,When set inhibits automatic gating of clock." "0,1" hexmask.long.byte 0x4 11.--17. 1. "NOGATE_RSVD6,Reserved PM signals." bitfld.long 0x4 10. "NOGATE_TRCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 9. "NOGATE_RSVD5,Reserved PM signals." "0,1" newline bitfld.long 0x4 8. "NOGATE_EVTCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 7. "NOGATE_RWU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 6. "NOGATE_RWU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 5. "NOGATE_RWU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 4. "NOGATE_RWU0,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 3. "NOGATE_TRU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 2. "NOGATE_TRU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 1. "NOGATE_TRU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 0. "NOGATE_TRU0,When set inhibits automatic gating of clock." "0,1" rgroup.long 0x78++0x7 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_13_BCDMA0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_13_BCDMA0_CFG_TCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_13_BCDMA0_CFG_TCHAN)" base ad:0x4BD5840000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" rgroup.long 0x64++0xF line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_13_BCDMA0__CFG__TCHAN_TTHRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_13_BCDMA0__CFG__TCHAN_TVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," line.long 0xC "VIRT_ALIAS_13_BCDMA0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0xC 0.--9. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_13_BCDMA0_CFG_RCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_13_BCDMA0_CFG_RCHAN)" base ad:0x4BD5880000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 =.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" rgroup.long 0x64++0xB line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_13_BCDMA0__CFG__RCHAN_RTHRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_13_BCDMA0__CFG__RCHAN_RVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_13_BCDMA0_CFG_RING (NAVSS0_BCDMA_0_VIRT_ALIAS_13_BCDMA0_CFG_RING)" base ad:0x4BD5900000 rgroup.long 0x40++0xB line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_13_BCDMA0__CFG__RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long.byte 0x4 16.--19. 1. "ASEL,Ring base address select" hexmask.long.byte 0x4 0.--3. 1. "ADDR_HI,Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_13_BCDMA0__CFG__RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and.." bitfld.long 0x8 29.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "RING_ELSIZE," "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 0.--15. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_13_BCDMA0_CFG_TCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_13_BCDMA0_CFG_TCHANRT)" base ad:0x4BD5C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1" newline bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" newline bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" newline bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" newline bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1" newline bitfld.long 0x4 8. "TDNULL,The channel has met the conditions to do teardown" "0,1" bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to schedule work" "0,1" newline bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has outstanding work to do" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_13_BCDMA0_CFG_RCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_13_BCDMA0_CFG_RCHANRT)" base ad:0x4BD5D00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 1. "RX_STARVATION,Rx starvation. This bit is set if the port receives a packet and the ring is empty. The bit clears when the doorbell is written with a positive value." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "RRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "RXQ_PEND,The channel fifo is available" "0,1" newline bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" newline bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" newline bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" newline bitfld.long 0x0 17. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1" newline bitfld.long 0x4 24. "FIFO_BUSY,The fifo has data" "0,1" bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to send data" "0,1" newline bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has active transactions" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_13_BCDMA0_CFG_RINGRT (NAVSS0_BCDMA_0_VIRT_ALIAS_13_BCDMA0_CFG_RINGRT)" base ad:0x4BD5E00000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." rgroup.long 0x1010++0x3 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." bitfld.long 0x0 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register. this bit is only valid on the reverse rings (rings consumed by the Host SW)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x1018++0x3 line.long 0x0 "VIRT_ALIAS_13_BCDMA0__CFG__RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." bitfld.long 0x0 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel. This bit is cleared anytime the tdown_ack bit is written as a 1 in the corresponding Ring N Doorbell Register. This bit is only valid on the reverse rings (rings.." "0,1" hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_14_BCDMA0_CFG_GCFG (NAVSS0_BCDMA_0_VIRT_ALIAS_14_BCDMA0_CFG_GCFG)" base ad:0x4BE11A0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the BCDMA in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported." line.long 0x4 "VIRT_ALIAS_14_BCDMA0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x20++0x13 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this BCDMA instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_14_BCDMA0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this BCDMA instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_14_BCDMA0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this BCDMA instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx split channel count" hexmask.long.word 0x8 9.--17. 1. "TCHAN_CNT,Tx split channel count" hexmask.long.word 0x8 0.--8. 1. "CHAN_CNT,BC channel count" line.long 0xC "VIRT_ALIAS_14_BCDMA0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this BCDMA instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,BC ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,BC high capacity internal channel count" line.long 0x10 "VIRT_ALIAS_14_BCDMA0__CFG__GCFG_CAP4,The Capabilities Register 4 specifies how many resources this BCDMA instance supports." hexmask.long.byte 0x10 24.--31. 1. "TUCHAN_CNT,TX ultra high capacity internal channel count" hexmask.long.byte 0x10 16.--23. 1. "THCHAN_CNT,TX high capacity internal channel count" hexmask.long.byte 0x10 8.--15. 1. "RUCHAN_CNT,RX ultra high capacity internal channel count" hexmask.long.byte 0x10 0.--7. 1. "RHCHAN_CNT,RX high capacity internal channel count" rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long.tbyte 0x0 15.--31. 1. "NOGATE_RSVD4,Reserved PM signals." bitfld.long 0x0 14. "NOGATE_RDEC2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 12.--13. "NOGATE_RSVD3,Reserved PM signals." "0,1,2,3" bitfld.long 0x0 11. "NOGATE_SDEC3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 8.--10. "NOGATE_RSVD2,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "NOGATE_WARB3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 4.--6. "NOGATE_RSVD1,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "NOGATE_CARB3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 2. "NOGATE_CARB2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 0.--1. "NOGATE_RSVD0,Reserved PM signals." "0,1,2,3" line.long 0x4 "VIRT_ALIAS_14_BCDMA0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" bitfld.long 0x4 31. "NOGATE_EDC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 30. "NOGATE_STATS,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 29. "NOGATE_PROXY,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 28. "NOGATE_PSILIF,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 27. "NOGATE_P2P,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 26. "NOGATE_RSVD8,Reserved PM signals." "0,1" bitfld.long 0x4 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 23. "NOGATE_RPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 22. "NOGATE_TPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 21. "NOGATE_PCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 19.--20. "NOGATE_RSVD7,Reserved PM signals." "0,1,2,3" newline bitfld.long 0x4 18. "NOGATE_CFG,When set inhibits automatic gating of clock." "0,1" hexmask.long.byte 0x4 11.--17. 1. "NOGATE_RSVD6,Reserved PM signals." bitfld.long 0x4 10. "NOGATE_TRCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 9. "NOGATE_RSVD5,Reserved PM signals." "0,1" newline bitfld.long 0x4 8. "NOGATE_EVTCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 7. "NOGATE_RWU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 6. "NOGATE_RWU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 5. "NOGATE_RWU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 4. "NOGATE_RWU0,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 3. "NOGATE_TRU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 2. "NOGATE_TRU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 1. "NOGATE_TRU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 0. "NOGATE_TRU0,When set inhibits automatic gating of clock." "0,1" rgroup.long 0x78++0x7 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_14_BCDMA0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_14_BCDMA0_CFG_TCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_14_BCDMA0_CFG_TCHAN)" base ad:0x4BE5840000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" rgroup.long 0x64++0xF line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_14_BCDMA0__CFG__TCHAN_TTHRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_14_BCDMA0__CFG__TCHAN_TVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," line.long 0xC "VIRT_ALIAS_14_BCDMA0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0xC 0.--9. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_14_BCDMA0_CFG_RCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_14_BCDMA0_CFG_RCHAN)" base ad:0x4BE5880000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 =.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" rgroup.long 0x64++0xB line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_14_BCDMA0__CFG__RCHAN_RTHRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_14_BCDMA0__CFG__RCHAN_RVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_14_BCDMA0_CFG_RING (NAVSS0_BCDMA_0_VIRT_ALIAS_14_BCDMA0_CFG_RING)" base ad:0x4BE5900000 rgroup.long 0x40++0xB line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_14_BCDMA0__CFG__RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long.byte 0x4 16.--19. 1. "ASEL,Ring base address select" hexmask.long.byte 0x4 0.--3. 1. "ADDR_HI,Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_14_BCDMA0__CFG__RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and.." bitfld.long 0x8 29.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "RING_ELSIZE," "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 0.--15. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_14_BCDMA0_CFG_TCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_14_BCDMA0_CFG_TCHANRT)" base ad:0x4BE5C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1" newline bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" newline bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" newline bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" newline bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1" newline bitfld.long 0x4 8. "TDNULL,The channel has met the conditions to do teardown" "0,1" bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to schedule work" "0,1" newline bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has outstanding work to do" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_14_BCDMA0_CFG_RCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_14_BCDMA0_CFG_RCHANRT)" base ad:0x4BE5D00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 1. "RX_STARVATION,Rx starvation. This bit is set if the port receives a packet and the ring is empty. The bit clears when the doorbell is written with a positive value." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "RRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "RXQ_PEND,The channel fifo is available" "0,1" newline bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" newline bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" newline bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" newline bitfld.long 0x0 17. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1" newline bitfld.long 0x4 24. "FIFO_BUSY,The fifo has data" "0,1" bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to send data" "0,1" newline bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has active transactions" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_14_BCDMA0_CFG_RINGRT (NAVSS0_BCDMA_0_VIRT_ALIAS_14_BCDMA0_CFG_RINGRT)" base ad:0x4BE5E00000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." rgroup.long 0x1010++0x3 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." bitfld.long 0x0 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register. this bit is only valid on the reverse rings (rings consumed by the Host SW)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x1018++0x3 line.long 0x0 "VIRT_ALIAS_14_BCDMA0__CFG__RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." bitfld.long 0x0 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel. This bit is cleared anytime the tdown_ack bit is written as a 1 in the corresponding Ring N Doorbell Register. This bit is only valid on the reverse rings (rings.." "0,1" hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_15_BCDMA0_CFG_GCFG (NAVSS0_BCDMA_0_VIRT_ALIAS_15_BCDMA0_CFG_GCFG)" base ad:0x4BF11A0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the BCDMA in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported." line.long 0x4 "VIRT_ALIAS_15_BCDMA0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x20++0x13 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this BCDMA instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_15_BCDMA0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this BCDMA instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_15_BCDMA0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this BCDMA instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx split channel count" hexmask.long.word 0x8 9.--17. 1. "TCHAN_CNT,Tx split channel count" hexmask.long.word 0x8 0.--8. 1. "CHAN_CNT,BC channel count" line.long 0xC "VIRT_ALIAS_15_BCDMA0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this BCDMA instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,BC ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,BC high capacity internal channel count" line.long 0x10 "VIRT_ALIAS_15_BCDMA0__CFG__GCFG_CAP4,The Capabilities Register 4 specifies how many resources this BCDMA instance supports." hexmask.long.byte 0x10 24.--31. 1. "TUCHAN_CNT,TX ultra high capacity internal channel count" hexmask.long.byte 0x10 16.--23. 1. "THCHAN_CNT,TX high capacity internal channel count" hexmask.long.byte 0x10 8.--15. 1. "RUCHAN_CNT,RX ultra high capacity internal channel count" hexmask.long.byte 0x10 0.--7. 1. "RHCHAN_CNT,RX high capacity internal channel count" rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long.tbyte 0x0 15.--31. 1. "NOGATE_RSVD4,Reserved PM signals." bitfld.long 0x0 14. "NOGATE_RDEC2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 12.--13. "NOGATE_RSVD3,Reserved PM signals." "0,1,2,3" bitfld.long 0x0 11. "NOGATE_SDEC3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 8.--10. "NOGATE_RSVD2,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "NOGATE_WARB3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 4.--6. "NOGATE_RSVD1,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "NOGATE_CARB3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 2. "NOGATE_CARB2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 0.--1. "NOGATE_RSVD0,Reserved PM signals." "0,1,2,3" line.long 0x4 "VIRT_ALIAS_15_BCDMA0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" bitfld.long 0x4 31. "NOGATE_EDC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 30. "NOGATE_STATS,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 29. "NOGATE_PROXY,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 28. "NOGATE_PSILIF,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 27. "NOGATE_P2P,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 26. "NOGATE_RSVD8,Reserved PM signals." "0,1" bitfld.long 0x4 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 23. "NOGATE_RPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 22. "NOGATE_TPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 21. "NOGATE_PCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 19.--20. "NOGATE_RSVD7,Reserved PM signals." "0,1,2,3" newline bitfld.long 0x4 18. "NOGATE_CFG,When set inhibits automatic gating of clock." "0,1" hexmask.long.byte 0x4 11.--17. 1. "NOGATE_RSVD6,Reserved PM signals." bitfld.long 0x4 10. "NOGATE_TRCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 9. "NOGATE_RSVD5,Reserved PM signals." "0,1" newline bitfld.long 0x4 8. "NOGATE_EVTCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 7. "NOGATE_RWU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 6. "NOGATE_RWU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 5. "NOGATE_RWU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 4. "NOGATE_RWU0,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 3. "NOGATE_TRU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 2. "NOGATE_TRU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 1. "NOGATE_TRU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 0. "NOGATE_TRU0,When set inhibits automatic gating of clock." "0,1" rgroup.long 0x78++0x7 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_15_BCDMA0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_15_BCDMA0_CFG_TCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_15_BCDMA0_CFG_TCHAN)" base ad:0x4BF5840000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" rgroup.long 0x64++0xF line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_15_BCDMA0__CFG__TCHAN_TTHRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_15_BCDMA0__CFG__TCHAN_TVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," line.long 0xC "VIRT_ALIAS_15_BCDMA0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0xC 0.--9. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_15_BCDMA0_CFG_RCHAN (NAVSS0_BCDMA_0_VIRT_ALIAS_15_BCDMA0_CFG_RCHAN)" base ad:0x4BF5880000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 =.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes 2 = 128 Bytes 3 = 256 bytes The optimal burst size setting is 256 Bytes to maximize utilization of the channel FIFOs." "0,1,2,3" rgroup.long 0x64++0xB line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "VIRT_ALIAS_15_BCDMA0__CFG__RCHAN_RTHRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value.." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_15_BCDMA0__CFG__RCHAN_RVIRT_CTRL,The Virtual ID register is used to set the virtual id to use for any transaction that uses non-Physical addresses." hexmask.long.word 0x8 0.--11. 1. "VIRTID," rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_15_BCDMA0_CFG_RING (NAVSS0_BCDMA_0_VIRT_ALIAS_15_BCDMA0_CFG_RING)" base ad:0x4BF5900000 rgroup.long 0x40++0xB line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_15_BCDMA0__CFG__RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this.." hexmask.long.byte 0x4 16.--19. 1. "ASEL,Ring base address select" hexmask.long.byte 0x4 0.--3. 1. "ADDR_HI,Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_15_BCDMA0__CFG__RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and.." bitfld.long 0x8 29.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "RING_ELSIZE," "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 0.--15. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_15_BCDMA0_CFG_TCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_15_BCDMA0_CFG_TCHANRT)" base ad:0x4BF5C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1" newline bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" newline bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" newline bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" newline bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1" newline bitfld.long 0x4 8. "TDNULL,The channel has met the conditions to do teardown" "0,1" bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to schedule work" "0,1" newline bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has outstanding work to do" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_15_BCDMA0_CFG_RCHANRT (NAVSS0_BCDMA_0_VIRT_ALIAS_15_BCDMA0_CFG_RCHANRT)" base ad:0x4BF5D00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 1. "RX_STARVATION,Rx starvation. This bit is set if the port receives a packet and the ring is empty. The bit clears when the doorbell is written with a positive value." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "RRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "RXQ_PEND,The channel fifo is available" "0,1" newline bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" newline bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" newline bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" newline bitfld.long 0x0 17. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1" newline bitfld.long 0x4 24. "FIFO_BUSY,The fifo has data" "0,1" bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to send data" "0,1" newline bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has active transactions" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_BCDMA_0_VIRT_ALIAS_15_BCDMA0_CFG_RINGRT (NAVSS0_BCDMA_0_VIRT_ALIAS_15_BCDMA0_CFG_RINGRT)" base ad:0x4BF5E00000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." rgroup.long 0x1010++0x3 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." bitfld.long 0x0 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register. this bit is only valid on the reverse rings (rings consumed by the Host SW)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x1018++0x3 line.long 0x0 "VIRT_ALIAS_15_BCDMA0__CFG__RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." bitfld.long 0x0 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel. This bit is cleared anytime the tdown_ack bit is written as a 1 in the corresponding Ring N Doorbell Register. This bit is only valid on the reverse rings (rings.." "0,1" hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." tree.end endif tree.end tree.end tree "NAVSS0_CPTS_0" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_CPTS_0_CPTS (NAVSS0_CPTS_0_CPTS)" base ad:0x310D0000 rgroup.long 0x0++0x3 line.long 0x0 "CPTS0__S_VBUSP__CPTS_VBUSP_CPTS_IDVER_REG,Identification and Version Register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" rgroup.long 0x4++0x7 line.long 0x0 "CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Sync Control Register" hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" bitfld.long 0x0 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1" newline bitfld.long 0x0 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1" bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1" newline bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1" bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1" newline bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1" bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" newline bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" newline bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" bitfld.long 0x0 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1" newline bitfld.long 0x0 6. "TS_COMP_TOG,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode 1=TS_COMP is in toggle mode" "0: TS_COMP is in non-toggle mode,1: TS_COMP is in toggle mode" bitfld.long 0x0 5. "MODE,Timestamp mode" "0,1" newline bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable" "0,1" bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1" newline bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1" bitfld.long 0x0 1. "INT_TEST,Interrupt test" "0,1" newline bitfld.long 0x0 0. "CPTS_EN,Time sync enable" "0,1" line.long 0x4 "CPTS0__S_VBUSP__CPTS_VBUSP_RFTCLK_SEL_REG,RFTCLK Select Register" hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select" rgroup.long 0xC++0x3 line.long 0x0 "CPTS0__S_VBUSP__CPTS_VBUSP_TS_PUSH_REG,Time Stamp Event Push Register" bitfld.long 0x0 0. "TS_PUSH,Time stamp event push" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_LOW_VAL_REG,Time Stamp Load Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value" rgroup.long 0x14++0x3 line.long 0x0 "CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_EN_REG,Time Stamp Load Enable Register" bitfld.long 0x0 0. "TS_LOAD_EN,Time stamp load enable" "0,1" rgroup.long 0x18++0xB line.long 0x0 "CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LOW_VAL_REG,Time Stamp Comparison Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time stamp comparison low value" line.long 0x4 "CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LEN_REG,Time Stamp Comparison Length Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time stamp comparison length" line.long 0x8 "CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_RAW_REG,Interrupt Status Register Raw" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_MASKED_REG,Interrupt Status Register Masked" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" rgroup.long 0x28++0x7 line.long 0x0 "CPTS0__S_VBUSP__CPTS_VBUSP_INT_ENABLE_REG,Interrupt Enable Register" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" line.long 0x4 "CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount" rgroup.long 0x30++0x3 line.long 0x0 "CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_POP_REG,Event Pop Register" bitfld.long 0x0 0. "EVENT_POP,Event pop" "0,1" rgroup.long 0x34++0xF line.long 0x0 "CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_0_REG,Event 0 Register" hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp" line.long 0x4 "CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_1_REG,Event 1 Register" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1" hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port number" newline hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Event type" hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type" newline hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID" line.long 0x8 "CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_2_REG,Event 2 Register" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain" line.long 0xC "CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_3_REG,Event 3 Register" hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp" rgroup.long 0x44++0x17 line.long 0x0 "CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load high value" line.long 0x4 "CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time stamp comparison high value" line.long 0x8 "CPTS0__S_VBUSP__CPTS_VBUSP_TS_ADD_VAL_REG,TS Add Value Register" bitfld.long 0x8 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7" line.long 0xC "CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register" hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time stamp PPM Low value" line.long 0x10 "CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value" line.long 0x14 "CPTS0__S_VBUSP__CPTS_VBUSP_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value" rgroup.long 0xD0++0x3 line.long 0x0 "CPTS0__S_VBUSP__CPTS_VBUSP_TS_CONFIG,Time Stamp Configuration Read" hexmask.long.byte 0x0 8.--15. 1. "EVNT_FIFO_DEPTH,The Event FIFO Depth" hexmask.long.byte 0x0 0.--7. 1. "NUM_GENF,The number of CPTS GENF outputs" rgroup.long 0xE0++0x1B line.long 0x0 "CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value" line.long 0x4 "CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value" line.long 0x8 "CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1" line.long 0xC "CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value" line.long 0x10 "CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value" line.long 0x14 "CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value" line.long 0x18 "CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value" rgroup.long 0x200++0x1B line.long 0x0 "CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp ESTF Generate Function Comparison Low Value" line.long 0x4 "CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp ESTF Generate Function Comparison High Value" line.long 0x8 "CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp ESTF Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1" line.long 0xC "CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp ESTF Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp ESTF Generate Function Length Value" line.long 0x10 "CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp ESTF Generate Function PPM Low Value" line.long 0x14 "CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value" line.long 0x18 "CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value" tree.end endif tree "NAVSS0_CPTS_0_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_CPTS_0_VIRT_ALIAS_0_CPTS0_S_VBUSP_CPTS_VBUSP (NAVSS0_CPTS_0_VIRT_ALIAS_0_CPTS0_S_VBUSP_CPTS_VBUSP)" base ad:0x4B010D0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_CPTS_IDVER_REG,Identification and Version Register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Sync Control Register" hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" bitfld.long 0x0 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1" newline bitfld.long 0x0 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1" bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1" newline bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1" bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1" newline bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1" bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" newline bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" newline bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" bitfld.long 0x0 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1" newline bitfld.long 0x0 6. "TS_COMP_TOG,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode 1=TS_COMP is in toggle mode" "0: TS_COMP is in non-toggle mode,1: TS_COMP is in toggle mode" bitfld.long 0x0 5. "MODE,Timestamp mode" "0,1" newline bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable" "0,1" bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1" newline bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1" bitfld.long 0x0 1. "INT_TEST,Interrupt test" "0,1" newline bitfld.long 0x0 0. "CPTS_EN,Time sync enable" "0,1" line.long 0x4 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_RFTCLK_SEL_REG,RFTCLK Select Register" hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PUSH_REG,Time Stamp Event Push Register" bitfld.long 0x0 0. "TS_PUSH,Time stamp event push" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_LOW_VAL_REG,Time Stamp Load Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_EN_REG,Time Stamp Load Enable Register" bitfld.long 0x0 0. "TS_LOAD_EN,Time stamp load enable" "0,1" rgroup.long 0x18++0xB line.long 0x0 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LOW_VAL_REG,Time Stamp Comparison Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time stamp comparison low value" line.long 0x4 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LEN_REG,Time Stamp Comparison Length Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time stamp comparison length" line.long 0x8 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_RAW_REG,Interrupt Status Register Raw" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_MASKED_REG,Interrupt Status Register Masked" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" rgroup.long 0x28++0x7 line.long 0x0 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_INT_ENABLE_REG,Interrupt Enable Register" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" line.long 0x4 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount" rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_POP_REG,Event Pop Register" bitfld.long 0x0 0. "EVENT_POP,Event pop" "0,1" rgroup.long 0x34++0xF line.long 0x0 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_0_REG,Event 0 Register" hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp" line.long 0x4 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_1_REG,Event 1 Register" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1" hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port number" newline hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Event type" hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type" newline hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID" line.long 0x8 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_2_REG,Event 2 Register" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain" line.long 0xC "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_3_REG,Event 3 Register" hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp" rgroup.long 0x44++0x17 line.long 0x0 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load high value" line.long 0x4 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time stamp comparison high value" line.long 0x8 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_TS_ADD_VAL_REG,TS Add Value Register" bitfld.long 0x8 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7" line.long 0xC "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register" hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time stamp PPM Low value" line.long 0x10 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value" line.long 0x14 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value" rgroup.long 0xD0++0x3 line.long 0x0 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_TS_CONFIG,Time Stamp Configuration Read" hexmask.long.byte 0x0 8.--15. 1. "EVNT_FIFO_DEPTH,The Event FIFO Depth" hexmask.long.byte 0x0 0.--7. 1. "NUM_GENF,The number of CPTS GENF outputs" rgroup.long 0xE0++0x1B line.long 0x0 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value" rgroup.long 0x200++0x1B line.long 0x0 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp ESTF Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp ESTF Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp ESTF Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp ESTF Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp ESTF Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp ESTF Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_0_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_CPTS_0_VIRT_ALIAS_1_CPTS0_S_VBUSP_CPTS_VBUSP (NAVSS0_CPTS_0_VIRT_ALIAS_1_CPTS0_S_VBUSP_CPTS_VBUSP)" base ad:0x4B110D0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_CPTS_IDVER_REG,Identification and Version Register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Sync Control Register" hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" bitfld.long 0x0 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1" newline bitfld.long 0x0 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1" bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1" newline bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1" bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1" newline bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1" bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" newline bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" newline bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" bitfld.long 0x0 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1" newline bitfld.long 0x0 6. "TS_COMP_TOG,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode 1=TS_COMP is in toggle mode" "0: TS_COMP is in non-toggle mode,1: TS_COMP is in toggle mode" bitfld.long 0x0 5. "MODE,Timestamp mode" "0,1" newline bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable" "0,1" bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1" newline bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1" bitfld.long 0x0 1. "INT_TEST,Interrupt test" "0,1" newline bitfld.long 0x0 0. "CPTS_EN,Time sync enable" "0,1" line.long 0x4 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_RFTCLK_SEL_REG,RFTCLK Select Register" hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PUSH_REG,Time Stamp Event Push Register" bitfld.long 0x0 0. "TS_PUSH,Time stamp event push" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_LOW_VAL_REG,Time Stamp Load Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_EN_REG,Time Stamp Load Enable Register" bitfld.long 0x0 0. "TS_LOAD_EN,Time stamp load enable" "0,1" rgroup.long 0x18++0xB line.long 0x0 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LOW_VAL_REG,Time Stamp Comparison Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time stamp comparison low value" line.long 0x4 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LEN_REG,Time Stamp Comparison Length Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time stamp comparison length" line.long 0x8 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_RAW_REG,Interrupt Status Register Raw" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_MASKED_REG,Interrupt Status Register Masked" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" rgroup.long 0x28++0x7 line.long 0x0 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_INT_ENABLE_REG,Interrupt Enable Register" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" line.long 0x4 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount" rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_POP_REG,Event Pop Register" bitfld.long 0x0 0. "EVENT_POP,Event pop" "0,1" rgroup.long 0x34++0xF line.long 0x0 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_0_REG,Event 0 Register" hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp" line.long 0x4 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_1_REG,Event 1 Register" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1" hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port number" newline hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Event type" hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type" newline hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID" line.long 0x8 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_2_REG,Event 2 Register" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain" line.long 0xC "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_3_REG,Event 3 Register" hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp" rgroup.long 0x44++0x17 line.long 0x0 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load high value" line.long 0x4 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time stamp comparison high value" line.long 0x8 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_TS_ADD_VAL_REG,TS Add Value Register" bitfld.long 0x8 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7" line.long 0xC "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register" hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time stamp PPM Low value" line.long 0x10 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value" line.long 0x14 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value" rgroup.long 0xD0++0x3 line.long 0x0 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_TS_CONFIG,Time Stamp Configuration Read" hexmask.long.byte 0x0 8.--15. 1. "EVNT_FIFO_DEPTH,The Event FIFO Depth" hexmask.long.byte 0x0 0.--7. 1. "NUM_GENF,The number of CPTS GENF outputs" rgroup.long 0xE0++0x1B line.long 0x0 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value" rgroup.long 0x200++0x1B line.long 0x0 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp ESTF Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp ESTF Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp ESTF Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp ESTF Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp ESTF Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp ESTF Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_1_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_CPTS_0_VIRT_ALIAS_2_CPTS0_S_VBUSP_CPTS_VBUSP (NAVSS0_CPTS_0_VIRT_ALIAS_2_CPTS0_S_VBUSP_CPTS_VBUSP)" base ad:0x4B210D0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_CPTS_IDVER_REG,Identification and Version Register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Sync Control Register" hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" bitfld.long 0x0 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1" newline bitfld.long 0x0 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1" bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1" newline bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1" bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1" newline bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1" bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" newline bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" newline bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" bitfld.long 0x0 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1" newline bitfld.long 0x0 6. "TS_COMP_TOG,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode 1=TS_COMP is in toggle mode" "0: TS_COMP is in non-toggle mode,1: TS_COMP is in toggle mode" bitfld.long 0x0 5. "MODE,Timestamp mode" "0,1" newline bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable" "0,1" bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1" newline bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1" bitfld.long 0x0 1. "INT_TEST,Interrupt test" "0,1" newline bitfld.long 0x0 0. "CPTS_EN,Time sync enable" "0,1" line.long 0x4 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_RFTCLK_SEL_REG,RFTCLK Select Register" hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PUSH_REG,Time Stamp Event Push Register" bitfld.long 0x0 0. "TS_PUSH,Time stamp event push" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_LOW_VAL_REG,Time Stamp Load Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_EN_REG,Time Stamp Load Enable Register" bitfld.long 0x0 0. "TS_LOAD_EN,Time stamp load enable" "0,1" rgroup.long 0x18++0xB line.long 0x0 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LOW_VAL_REG,Time Stamp Comparison Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time stamp comparison low value" line.long 0x4 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LEN_REG,Time Stamp Comparison Length Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time stamp comparison length" line.long 0x8 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_RAW_REG,Interrupt Status Register Raw" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_MASKED_REG,Interrupt Status Register Masked" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" rgroup.long 0x28++0x7 line.long 0x0 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_INT_ENABLE_REG,Interrupt Enable Register" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" line.long 0x4 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount" rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_POP_REG,Event Pop Register" bitfld.long 0x0 0. "EVENT_POP,Event pop" "0,1" rgroup.long 0x34++0xF line.long 0x0 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_0_REG,Event 0 Register" hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp" line.long 0x4 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_1_REG,Event 1 Register" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1" hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port number" newline hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Event type" hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type" newline hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID" line.long 0x8 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_2_REG,Event 2 Register" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain" line.long 0xC "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_3_REG,Event 3 Register" hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp" rgroup.long 0x44++0x17 line.long 0x0 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load high value" line.long 0x4 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time stamp comparison high value" line.long 0x8 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_TS_ADD_VAL_REG,TS Add Value Register" bitfld.long 0x8 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7" line.long 0xC "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register" hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time stamp PPM Low value" line.long 0x10 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value" line.long 0x14 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value" rgroup.long 0xD0++0x3 line.long 0x0 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_TS_CONFIG,Time Stamp Configuration Read" hexmask.long.byte 0x0 8.--15. 1. "EVNT_FIFO_DEPTH,The Event FIFO Depth" hexmask.long.byte 0x0 0.--7. 1. "NUM_GENF,The number of CPTS GENF outputs" rgroup.long 0xE0++0x1B line.long 0x0 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value" rgroup.long 0x200++0x1B line.long 0x0 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp ESTF Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp ESTF Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp ESTF Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp ESTF Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp ESTF Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp ESTF Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_2_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_CPTS_0_VIRT_ALIAS_3_CPTS0_S_VBUSP_CPTS_VBUSP (NAVSS0_CPTS_0_VIRT_ALIAS_3_CPTS0_S_VBUSP_CPTS_VBUSP)" base ad:0x4B310D0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_CPTS_IDVER_REG,Identification and Version Register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Sync Control Register" hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" bitfld.long 0x0 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1" newline bitfld.long 0x0 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1" bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1" newline bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1" bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1" newline bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1" bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" newline bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" newline bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" bitfld.long 0x0 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1" newline bitfld.long 0x0 6. "TS_COMP_TOG,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode 1=TS_COMP is in toggle mode" "0: TS_COMP is in non-toggle mode,1: TS_COMP is in toggle mode" bitfld.long 0x0 5. "MODE,Timestamp mode" "0,1" newline bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable" "0,1" bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1" newline bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1" bitfld.long 0x0 1. "INT_TEST,Interrupt test" "0,1" newline bitfld.long 0x0 0. "CPTS_EN,Time sync enable" "0,1" line.long 0x4 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_RFTCLK_SEL_REG,RFTCLK Select Register" hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PUSH_REG,Time Stamp Event Push Register" bitfld.long 0x0 0. "TS_PUSH,Time stamp event push" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_LOW_VAL_REG,Time Stamp Load Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_EN_REG,Time Stamp Load Enable Register" bitfld.long 0x0 0. "TS_LOAD_EN,Time stamp load enable" "0,1" rgroup.long 0x18++0xB line.long 0x0 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LOW_VAL_REG,Time Stamp Comparison Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time stamp comparison low value" line.long 0x4 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LEN_REG,Time Stamp Comparison Length Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time stamp comparison length" line.long 0x8 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_RAW_REG,Interrupt Status Register Raw" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_MASKED_REG,Interrupt Status Register Masked" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" rgroup.long 0x28++0x7 line.long 0x0 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_INT_ENABLE_REG,Interrupt Enable Register" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" line.long 0x4 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount" rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_POP_REG,Event Pop Register" bitfld.long 0x0 0. "EVENT_POP,Event pop" "0,1" rgroup.long 0x34++0xF line.long 0x0 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_0_REG,Event 0 Register" hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp" line.long 0x4 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_1_REG,Event 1 Register" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1" hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port number" newline hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Event type" hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type" newline hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID" line.long 0x8 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_2_REG,Event 2 Register" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain" line.long 0xC "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_3_REG,Event 3 Register" hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp" rgroup.long 0x44++0x17 line.long 0x0 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load high value" line.long 0x4 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time stamp comparison high value" line.long 0x8 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_TS_ADD_VAL_REG,TS Add Value Register" bitfld.long 0x8 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7" line.long 0xC "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register" hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time stamp PPM Low value" line.long 0x10 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value" line.long 0x14 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value" rgroup.long 0xD0++0x3 line.long 0x0 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_TS_CONFIG,Time Stamp Configuration Read" hexmask.long.byte 0x0 8.--15. 1. "EVNT_FIFO_DEPTH,The Event FIFO Depth" hexmask.long.byte 0x0 0.--7. 1. "NUM_GENF,The number of CPTS GENF outputs" rgroup.long 0xE0++0x1B line.long 0x0 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value" rgroup.long 0x200++0x1B line.long 0x0 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp ESTF Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp ESTF Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp ESTF Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp ESTF Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp ESTF Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp ESTF Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_3_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_CPTS_0_VIRT_ALIAS_4_CPTS0_S_VBUSP_CPTS_VBUSP (NAVSS0_CPTS_0_VIRT_ALIAS_4_CPTS0_S_VBUSP_CPTS_VBUSP)" base ad:0x4B410D0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_CPTS_IDVER_REG,Identification and Version Register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Sync Control Register" hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" bitfld.long 0x0 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1" newline bitfld.long 0x0 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1" bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1" newline bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1" bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1" newline bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1" bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" newline bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" newline bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" bitfld.long 0x0 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1" newline bitfld.long 0x0 6. "TS_COMP_TOG,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode 1=TS_COMP is in toggle mode" "0: TS_COMP is in non-toggle mode,1: TS_COMP is in toggle mode" bitfld.long 0x0 5. "MODE,Timestamp mode" "0,1" newline bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable" "0,1" bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1" newline bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1" bitfld.long 0x0 1. "INT_TEST,Interrupt test" "0,1" newline bitfld.long 0x0 0. "CPTS_EN,Time sync enable" "0,1" line.long 0x4 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_RFTCLK_SEL_REG,RFTCLK Select Register" hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PUSH_REG,Time Stamp Event Push Register" bitfld.long 0x0 0. "TS_PUSH,Time stamp event push" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_LOW_VAL_REG,Time Stamp Load Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_EN_REG,Time Stamp Load Enable Register" bitfld.long 0x0 0. "TS_LOAD_EN,Time stamp load enable" "0,1" rgroup.long 0x18++0xB line.long 0x0 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LOW_VAL_REG,Time Stamp Comparison Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time stamp comparison low value" line.long 0x4 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LEN_REG,Time Stamp Comparison Length Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time stamp comparison length" line.long 0x8 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_RAW_REG,Interrupt Status Register Raw" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_MASKED_REG,Interrupt Status Register Masked" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" rgroup.long 0x28++0x7 line.long 0x0 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_INT_ENABLE_REG,Interrupt Enable Register" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" line.long 0x4 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount" rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_POP_REG,Event Pop Register" bitfld.long 0x0 0. "EVENT_POP,Event pop" "0,1" rgroup.long 0x34++0xF line.long 0x0 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_0_REG,Event 0 Register" hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp" line.long 0x4 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_1_REG,Event 1 Register" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1" hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port number" newline hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Event type" hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type" newline hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID" line.long 0x8 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_2_REG,Event 2 Register" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain" line.long 0xC "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_3_REG,Event 3 Register" hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp" rgroup.long 0x44++0x17 line.long 0x0 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load high value" line.long 0x4 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time stamp comparison high value" line.long 0x8 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_TS_ADD_VAL_REG,TS Add Value Register" bitfld.long 0x8 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7" line.long 0xC "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register" hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time stamp PPM Low value" line.long 0x10 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value" line.long 0x14 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value" rgroup.long 0xD0++0x3 line.long 0x0 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_TS_CONFIG,Time Stamp Configuration Read" hexmask.long.byte 0x0 8.--15. 1. "EVNT_FIFO_DEPTH,The Event FIFO Depth" hexmask.long.byte 0x0 0.--7. 1. "NUM_GENF,The number of CPTS GENF outputs" rgroup.long 0xE0++0x1B line.long 0x0 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value" rgroup.long 0x200++0x1B line.long 0x0 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp ESTF Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp ESTF Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp ESTF Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp ESTF Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp ESTF Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp ESTF Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_4_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_CPTS_0_VIRT_ALIAS_5_CPTS0_S_VBUSP_CPTS_VBUSP (NAVSS0_CPTS_0_VIRT_ALIAS_5_CPTS0_S_VBUSP_CPTS_VBUSP)" base ad:0x4B510D0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_CPTS_IDVER_REG,Identification and Version Register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Sync Control Register" hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" bitfld.long 0x0 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1" newline bitfld.long 0x0 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1" bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1" newline bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1" bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1" newline bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1" bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" newline bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" newline bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" bitfld.long 0x0 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1" newline bitfld.long 0x0 6. "TS_COMP_TOG,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode 1=TS_COMP is in toggle mode" "0: TS_COMP is in non-toggle mode,1: TS_COMP is in toggle mode" bitfld.long 0x0 5. "MODE,Timestamp mode" "0,1" newline bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable" "0,1" bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1" newline bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1" bitfld.long 0x0 1. "INT_TEST,Interrupt test" "0,1" newline bitfld.long 0x0 0. "CPTS_EN,Time sync enable" "0,1" line.long 0x4 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_RFTCLK_SEL_REG,RFTCLK Select Register" hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PUSH_REG,Time Stamp Event Push Register" bitfld.long 0x0 0. "TS_PUSH,Time stamp event push" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_LOW_VAL_REG,Time Stamp Load Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_EN_REG,Time Stamp Load Enable Register" bitfld.long 0x0 0. "TS_LOAD_EN,Time stamp load enable" "0,1" rgroup.long 0x18++0xB line.long 0x0 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LOW_VAL_REG,Time Stamp Comparison Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time stamp comparison low value" line.long 0x4 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LEN_REG,Time Stamp Comparison Length Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time stamp comparison length" line.long 0x8 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_RAW_REG,Interrupt Status Register Raw" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_MASKED_REG,Interrupt Status Register Masked" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" rgroup.long 0x28++0x7 line.long 0x0 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_INT_ENABLE_REG,Interrupt Enable Register" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" line.long 0x4 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount" rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_POP_REG,Event Pop Register" bitfld.long 0x0 0. "EVENT_POP,Event pop" "0,1" rgroup.long 0x34++0xF line.long 0x0 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_0_REG,Event 0 Register" hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp" line.long 0x4 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_1_REG,Event 1 Register" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1" hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port number" newline hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Event type" hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type" newline hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID" line.long 0x8 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_2_REG,Event 2 Register" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain" line.long 0xC "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_3_REG,Event 3 Register" hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp" rgroup.long 0x44++0x17 line.long 0x0 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load high value" line.long 0x4 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time stamp comparison high value" line.long 0x8 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_TS_ADD_VAL_REG,TS Add Value Register" bitfld.long 0x8 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7" line.long 0xC "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register" hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time stamp PPM Low value" line.long 0x10 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value" line.long 0x14 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value" rgroup.long 0xD0++0x3 line.long 0x0 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_TS_CONFIG,Time Stamp Configuration Read" hexmask.long.byte 0x0 8.--15. 1. "EVNT_FIFO_DEPTH,The Event FIFO Depth" hexmask.long.byte 0x0 0.--7. 1. "NUM_GENF,The number of CPTS GENF outputs" rgroup.long 0xE0++0x1B line.long 0x0 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value" rgroup.long 0x200++0x1B line.long 0x0 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp ESTF Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp ESTF Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp ESTF Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp ESTF Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp ESTF Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp ESTF Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_5_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_CPTS_0_VIRT_ALIAS_6_CPTS0_S_VBUSP_CPTS_VBUSP (NAVSS0_CPTS_0_VIRT_ALIAS_6_CPTS0_S_VBUSP_CPTS_VBUSP)" base ad:0x4B610D0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_CPTS_IDVER_REG,Identification and Version Register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Sync Control Register" hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" bitfld.long 0x0 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1" newline bitfld.long 0x0 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1" bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1" newline bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1" bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1" newline bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1" bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" newline bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" newline bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" bitfld.long 0x0 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1" newline bitfld.long 0x0 6. "TS_COMP_TOG,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode 1=TS_COMP is in toggle mode" "0: TS_COMP is in non-toggle mode,1: TS_COMP is in toggle mode" bitfld.long 0x0 5. "MODE,Timestamp mode" "0,1" newline bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable" "0,1" bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1" newline bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1" bitfld.long 0x0 1. "INT_TEST,Interrupt test" "0,1" newline bitfld.long 0x0 0. "CPTS_EN,Time sync enable" "0,1" line.long 0x4 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_RFTCLK_SEL_REG,RFTCLK Select Register" hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PUSH_REG,Time Stamp Event Push Register" bitfld.long 0x0 0. "TS_PUSH,Time stamp event push" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_LOW_VAL_REG,Time Stamp Load Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_EN_REG,Time Stamp Load Enable Register" bitfld.long 0x0 0. "TS_LOAD_EN,Time stamp load enable" "0,1" rgroup.long 0x18++0xB line.long 0x0 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LOW_VAL_REG,Time Stamp Comparison Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time stamp comparison low value" line.long 0x4 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LEN_REG,Time Stamp Comparison Length Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time stamp comparison length" line.long 0x8 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_RAW_REG,Interrupt Status Register Raw" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_MASKED_REG,Interrupt Status Register Masked" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" rgroup.long 0x28++0x7 line.long 0x0 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_INT_ENABLE_REG,Interrupt Enable Register" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" line.long 0x4 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount" rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_POP_REG,Event Pop Register" bitfld.long 0x0 0. "EVENT_POP,Event pop" "0,1" rgroup.long 0x34++0xF line.long 0x0 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_0_REG,Event 0 Register" hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp" line.long 0x4 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_1_REG,Event 1 Register" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1" hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port number" newline hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Event type" hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type" newline hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID" line.long 0x8 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_2_REG,Event 2 Register" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain" line.long 0xC "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_3_REG,Event 3 Register" hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp" rgroup.long 0x44++0x17 line.long 0x0 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load high value" line.long 0x4 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time stamp comparison high value" line.long 0x8 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_TS_ADD_VAL_REG,TS Add Value Register" bitfld.long 0x8 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7" line.long 0xC "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register" hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time stamp PPM Low value" line.long 0x10 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value" line.long 0x14 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value" rgroup.long 0xD0++0x3 line.long 0x0 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_TS_CONFIG,Time Stamp Configuration Read" hexmask.long.byte 0x0 8.--15. 1. "EVNT_FIFO_DEPTH,The Event FIFO Depth" hexmask.long.byte 0x0 0.--7. 1. "NUM_GENF,The number of CPTS GENF outputs" rgroup.long 0xE0++0x1B line.long 0x0 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value" rgroup.long 0x200++0x1B line.long 0x0 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp ESTF Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp ESTF Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp ESTF Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp ESTF Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp ESTF Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp ESTF Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_6_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_CPTS_0_VIRT_ALIAS_7_CPTS0_S_VBUSP_CPTS_VBUSP (NAVSS0_CPTS_0_VIRT_ALIAS_7_CPTS0_S_VBUSP_CPTS_VBUSP)" base ad:0x4B710D0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_CPTS_IDVER_REG,Identification and Version Register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Sync Control Register" hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" bitfld.long 0x0 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1" newline bitfld.long 0x0 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1" bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1" newline bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1" bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1" newline bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1" bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" newline bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" newline bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" bitfld.long 0x0 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1" newline bitfld.long 0x0 6. "TS_COMP_TOG,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode 1=TS_COMP is in toggle mode" "0: TS_COMP is in non-toggle mode,1: TS_COMP is in toggle mode" bitfld.long 0x0 5. "MODE,Timestamp mode" "0,1" newline bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable" "0,1" bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1" newline bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1" bitfld.long 0x0 1. "INT_TEST,Interrupt test" "0,1" newline bitfld.long 0x0 0. "CPTS_EN,Time sync enable" "0,1" line.long 0x4 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_RFTCLK_SEL_REG,RFTCLK Select Register" hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PUSH_REG,Time Stamp Event Push Register" bitfld.long 0x0 0. "TS_PUSH,Time stamp event push" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_LOW_VAL_REG,Time Stamp Load Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_EN_REG,Time Stamp Load Enable Register" bitfld.long 0x0 0. "TS_LOAD_EN,Time stamp load enable" "0,1" rgroup.long 0x18++0xB line.long 0x0 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LOW_VAL_REG,Time Stamp Comparison Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time stamp comparison low value" line.long 0x4 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LEN_REG,Time Stamp Comparison Length Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time stamp comparison length" line.long 0x8 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_RAW_REG,Interrupt Status Register Raw" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_MASKED_REG,Interrupt Status Register Masked" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" rgroup.long 0x28++0x7 line.long 0x0 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_INT_ENABLE_REG,Interrupt Enable Register" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" line.long 0x4 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount" rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_POP_REG,Event Pop Register" bitfld.long 0x0 0. "EVENT_POP,Event pop" "0,1" rgroup.long 0x34++0xF line.long 0x0 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_0_REG,Event 0 Register" hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp" line.long 0x4 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_1_REG,Event 1 Register" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1" hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port number" newline hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Event type" hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type" newline hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID" line.long 0x8 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_2_REG,Event 2 Register" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain" line.long 0xC "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_3_REG,Event 3 Register" hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp" rgroup.long 0x44++0x17 line.long 0x0 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load high value" line.long 0x4 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time stamp comparison high value" line.long 0x8 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_TS_ADD_VAL_REG,TS Add Value Register" bitfld.long 0x8 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7" line.long 0xC "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register" hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time stamp PPM Low value" line.long 0x10 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value" line.long 0x14 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value" rgroup.long 0xD0++0x3 line.long 0x0 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_TS_CONFIG,Time Stamp Configuration Read" hexmask.long.byte 0x0 8.--15. 1. "EVNT_FIFO_DEPTH,The Event FIFO Depth" hexmask.long.byte 0x0 0.--7. 1. "NUM_GENF,The number of CPTS GENF outputs" rgroup.long 0xE0++0x1B line.long 0x0 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value" rgroup.long 0x200++0x1B line.long 0x0 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp ESTF Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp ESTF Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp ESTF Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp ESTF Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp ESTF Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp ESTF Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_7_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_CPTS_0_VIRT_ALIAS_8_CPTS0_S_VBUSP_CPTS_VBUSP (NAVSS0_CPTS_0_VIRT_ALIAS_8_CPTS0_S_VBUSP_CPTS_VBUSP)" base ad:0x4B810D0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_CPTS_IDVER_REG,Identification and Version Register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Sync Control Register" hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" bitfld.long 0x0 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1" newline bitfld.long 0x0 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1" bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1" newline bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1" bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1" newline bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1" bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" newline bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" newline bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" bitfld.long 0x0 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1" newline bitfld.long 0x0 6. "TS_COMP_TOG,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode 1=TS_COMP is in toggle mode" "0: TS_COMP is in non-toggle mode,1: TS_COMP is in toggle mode" bitfld.long 0x0 5. "MODE,Timestamp mode" "0,1" newline bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable" "0,1" bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1" newline bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1" bitfld.long 0x0 1. "INT_TEST,Interrupt test" "0,1" newline bitfld.long 0x0 0. "CPTS_EN,Time sync enable" "0,1" line.long 0x4 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_RFTCLK_SEL_REG,RFTCLK Select Register" hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PUSH_REG,Time Stamp Event Push Register" bitfld.long 0x0 0. "TS_PUSH,Time stamp event push" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_LOW_VAL_REG,Time Stamp Load Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_EN_REG,Time Stamp Load Enable Register" bitfld.long 0x0 0. "TS_LOAD_EN,Time stamp load enable" "0,1" rgroup.long 0x18++0xB line.long 0x0 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LOW_VAL_REG,Time Stamp Comparison Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time stamp comparison low value" line.long 0x4 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LEN_REG,Time Stamp Comparison Length Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time stamp comparison length" line.long 0x8 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_RAW_REG,Interrupt Status Register Raw" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_MASKED_REG,Interrupt Status Register Masked" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" rgroup.long 0x28++0x7 line.long 0x0 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_INT_ENABLE_REG,Interrupt Enable Register" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" line.long 0x4 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount" rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_POP_REG,Event Pop Register" bitfld.long 0x0 0. "EVENT_POP,Event pop" "0,1" rgroup.long 0x34++0xF line.long 0x0 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_0_REG,Event 0 Register" hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp" line.long 0x4 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_1_REG,Event 1 Register" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1" hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port number" newline hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Event type" hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type" newline hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID" line.long 0x8 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_2_REG,Event 2 Register" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain" line.long 0xC "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_3_REG,Event 3 Register" hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp" rgroup.long 0x44++0x17 line.long 0x0 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load high value" line.long 0x4 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time stamp comparison high value" line.long 0x8 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_TS_ADD_VAL_REG,TS Add Value Register" bitfld.long 0x8 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7" line.long 0xC "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register" hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time stamp PPM Low value" line.long 0x10 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value" line.long 0x14 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value" rgroup.long 0xD0++0x3 line.long 0x0 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_TS_CONFIG,Time Stamp Configuration Read" hexmask.long.byte 0x0 8.--15. 1. "EVNT_FIFO_DEPTH,The Event FIFO Depth" hexmask.long.byte 0x0 0.--7. 1. "NUM_GENF,The number of CPTS GENF outputs" rgroup.long 0xE0++0x1B line.long 0x0 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value" rgroup.long 0x200++0x1B line.long 0x0 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp ESTF Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp ESTF Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp ESTF Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp ESTF Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp ESTF Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp ESTF Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_8_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_CPTS_0_VIRT_ALIAS_9_CPTS0_S_VBUSP_CPTS_VBUSP (NAVSS0_CPTS_0_VIRT_ALIAS_9_CPTS0_S_VBUSP_CPTS_VBUSP)" base ad:0x4B910D0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_CPTS_IDVER_REG,Identification and Version Register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Sync Control Register" hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" bitfld.long 0x0 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1" newline bitfld.long 0x0 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1" bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1" newline bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1" bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1" newline bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1" bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" newline bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" newline bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" bitfld.long 0x0 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1" newline bitfld.long 0x0 6. "TS_COMP_TOG,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode 1=TS_COMP is in toggle mode" "0: TS_COMP is in non-toggle mode,1: TS_COMP is in toggle mode" bitfld.long 0x0 5. "MODE,Timestamp mode" "0,1" newline bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable" "0,1" bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1" newline bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1" bitfld.long 0x0 1. "INT_TEST,Interrupt test" "0,1" newline bitfld.long 0x0 0. "CPTS_EN,Time sync enable" "0,1" line.long 0x4 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_RFTCLK_SEL_REG,RFTCLK Select Register" hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PUSH_REG,Time Stamp Event Push Register" bitfld.long 0x0 0. "TS_PUSH,Time stamp event push" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_LOW_VAL_REG,Time Stamp Load Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_EN_REG,Time Stamp Load Enable Register" bitfld.long 0x0 0. "TS_LOAD_EN,Time stamp load enable" "0,1" rgroup.long 0x18++0xB line.long 0x0 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LOW_VAL_REG,Time Stamp Comparison Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time stamp comparison low value" line.long 0x4 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LEN_REG,Time Stamp Comparison Length Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time stamp comparison length" line.long 0x8 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_RAW_REG,Interrupt Status Register Raw" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_MASKED_REG,Interrupt Status Register Masked" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" rgroup.long 0x28++0x7 line.long 0x0 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_INT_ENABLE_REG,Interrupt Enable Register" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" line.long 0x4 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount" rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_POP_REG,Event Pop Register" bitfld.long 0x0 0. "EVENT_POP,Event pop" "0,1" rgroup.long 0x34++0xF line.long 0x0 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_0_REG,Event 0 Register" hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp" line.long 0x4 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_1_REG,Event 1 Register" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1" hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port number" newline hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Event type" hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type" newline hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID" line.long 0x8 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_2_REG,Event 2 Register" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain" line.long 0xC "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_3_REG,Event 3 Register" hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp" rgroup.long 0x44++0x17 line.long 0x0 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load high value" line.long 0x4 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time stamp comparison high value" line.long 0x8 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_TS_ADD_VAL_REG,TS Add Value Register" bitfld.long 0x8 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7" line.long 0xC "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register" hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time stamp PPM Low value" line.long 0x10 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value" line.long 0x14 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value" rgroup.long 0xD0++0x3 line.long 0x0 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_TS_CONFIG,Time Stamp Configuration Read" hexmask.long.byte 0x0 8.--15. 1. "EVNT_FIFO_DEPTH,The Event FIFO Depth" hexmask.long.byte 0x0 0.--7. 1. "NUM_GENF,The number of CPTS GENF outputs" rgroup.long 0xE0++0x1B line.long 0x0 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value" rgroup.long 0x200++0x1B line.long 0x0 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp ESTF Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp ESTF Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp ESTF Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp ESTF Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp ESTF Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp ESTF Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_9_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_CPTS_0_VIRT_ALIAS_10_CPTS0_S_VBUSP_CPTS_VBUSP (NAVSS0_CPTS_0_VIRT_ALIAS_10_CPTS0_S_VBUSP_CPTS_VBUSP)" base ad:0x4BA10D0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_CPTS_IDVER_REG,Identification and Version Register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Sync Control Register" hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" bitfld.long 0x0 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1" newline bitfld.long 0x0 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1" bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1" newline bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1" bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1" newline bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1" bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" newline bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" newline bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" bitfld.long 0x0 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1" newline bitfld.long 0x0 6. "TS_COMP_TOG,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode 1=TS_COMP is in toggle mode" "0: TS_COMP is in non-toggle mode,1: TS_COMP is in toggle mode" bitfld.long 0x0 5. "MODE,Timestamp mode" "0,1" newline bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable" "0,1" bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1" newline bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1" bitfld.long 0x0 1. "INT_TEST,Interrupt test" "0,1" newline bitfld.long 0x0 0. "CPTS_EN,Time sync enable" "0,1" line.long 0x4 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_RFTCLK_SEL_REG,RFTCLK Select Register" hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PUSH_REG,Time Stamp Event Push Register" bitfld.long 0x0 0. "TS_PUSH,Time stamp event push" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_LOW_VAL_REG,Time Stamp Load Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_EN_REG,Time Stamp Load Enable Register" bitfld.long 0x0 0. "TS_LOAD_EN,Time stamp load enable" "0,1" rgroup.long 0x18++0xB line.long 0x0 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LOW_VAL_REG,Time Stamp Comparison Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time stamp comparison low value" line.long 0x4 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LEN_REG,Time Stamp Comparison Length Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time stamp comparison length" line.long 0x8 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_RAW_REG,Interrupt Status Register Raw" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_MASKED_REG,Interrupt Status Register Masked" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" rgroup.long 0x28++0x7 line.long 0x0 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_INT_ENABLE_REG,Interrupt Enable Register" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" line.long 0x4 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount" rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_POP_REG,Event Pop Register" bitfld.long 0x0 0. "EVENT_POP,Event pop" "0,1" rgroup.long 0x34++0xF line.long 0x0 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_0_REG,Event 0 Register" hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp" line.long 0x4 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_1_REG,Event 1 Register" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1" hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port number" newline hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Event type" hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type" newline hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID" line.long 0x8 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_2_REG,Event 2 Register" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain" line.long 0xC "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_3_REG,Event 3 Register" hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp" rgroup.long 0x44++0x17 line.long 0x0 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load high value" line.long 0x4 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time stamp comparison high value" line.long 0x8 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_TS_ADD_VAL_REG,TS Add Value Register" bitfld.long 0x8 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7" line.long 0xC "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register" hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time stamp PPM Low value" line.long 0x10 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value" line.long 0x14 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value" rgroup.long 0xD0++0x3 line.long 0x0 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_TS_CONFIG,Time Stamp Configuration Read" hexmask.long.byte 0x0 8.--15. 1. "EVNT_FIFO_DEPTH,The Event FIFO Depth" hexmask.long.byte 0x0 0.--7. 1. "NUM_GENF,The number of CPTS GENF outputs" rgroup.long 0xE0++0x1B line.long 0x0 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value" rgroup.long 0x200++0x1B line.long 0x0 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp ESTF Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp ESTF Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp ESTF Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp ESTF Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp ESTF Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp ESTF Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_10_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_CPTS_0_VIRT_ALIAS_11_CPTS0_S_VBUSP_CPTS_VBUSP (NAVSS0_CPTS_0_VIRT_ALIAS_11_CPTS0_S_VBUSP_CPTS_VBUSP)" base ad:0x4BB10D0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_CPTS_IDVER_REG,Identification and Version Register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Sync Control Register" hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" bitfld.long 0x0 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1" newline bitfld.long 0x0 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1" bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1" newline bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1" bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1" newline bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1" bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" newline bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" newline bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" bitfld.long 0x0 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1" newline bitfld.long 0x0 6. "TS_COMP_TOG,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode 1=TS_COMP is in toggle mode" "0: TS_COMP is in non-toggle mode,1: TS_COMP is in toggle mode" bitfld.long 0x0 5. "MODE,Timestamp mode" "0,1" newline bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable" "0,1" bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1" newline bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1" bitfld.long 0x0 1. "INT_TEST,Interrupt test" "0,1" newline bitfld.long 0x0 0. "CPTS_EN,Time sync enable" "0,1" line.long 0x4 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_RFTCLK_SEL_REG,RFTCLK Select Register" hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PUSH_REG,Time Stamp Event Push Register" bitfld.long 0x0 0. "TS_PUSH,Time stamp event push" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_LOW_VAL_REG,Time Stamp Load Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_EN_REG,Time Stamp Load Enable Register" bitfld.long 0x0 0. "TS_LOAD_EN,Time stamp load enable" "0,1" rgroup.long 0x18++0xB line.long 0x0 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LOW_VAL_REG,Time Stamp Comparison Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time stamp comparison low value" line.long 0x4 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LEN_REG,Time Stamp Comparison Length Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time stamp comparison length" line.long 0x8 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_RAW_REG,Interrupt Status Register Raw" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_MASKED_REG,Interrupt Status Register Masked" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" rgroup.long 0x28++0x7 line.long 0x0 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_INT_ENABLE_REG,Interrupt Enable Register" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" line.long 0x4 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount" rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_POP_REG,Event Pop Register" bitfld.long 0x0 0. "EVENT_POP,Event pop" "0,1" rgroup.long 0x34++0xF line.long 0x0 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_0_REG,Event 0 Register" hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp" line.long 0x4 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_1_REG,Event 1 Register" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1" hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port number" newline hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Event type" hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type" newline hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID" line.long 0x8 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_2_REG,Event 2 Register" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain" line.long 0xC "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_3_REG,Event 3 Register" hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp" rgroup.long 0x44++0x17 line.long 0x0 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load high value" line.long 0x4 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time stamp comparison high value" line.long 0x8 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_TS_ADD_VAL_REG,TS Add Value Register" bitfld.long 0x8 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7" line.long 0xC "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register" hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time stamp PPM Low value" line.long 0x10 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value" line.long 0x14 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value" rgroup.long 0xD0++0x3 line.long 0x0 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_TS_CONFIG,Time Stamp Configuration Read" hexmask.long.byte 0x0 8.--15. 1. "EVNT_FIFO_DEPTH,The Event FIFO Depth" hexmask.long.byte 0x0 0.--7. 1. "NUM_GENF,The number of CPTS GENF outputs" rgroup.long 0xE0++0x1B line.long 0x0 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value" rgroup.long 0x200++0x1B line.long 0x0 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp ESTF Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp ESTF Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp ESTF Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp ESTF Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp ESTF Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp ESTF Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_11_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_CPTS_0_VIRT_ALIAS_12_CPTS0_S_VBUSP_CPTS_VBUSP (NAVSS0_CPTS_0_VIRT_ALIAS_12_CPTS0_S_VBUSP_CPTS_VBUSP)" base ad:0x4BC10D0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_CPTS_IDVER_REG,Identification and Version Register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Sync Control Register" hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" bitfld.long 0x0 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1" newline bitfld.long 0x0 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1" bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1" newline bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1" bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1" newline bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1" bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" newline bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" newline bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" bitfld.long 0x0 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1" newline bitfld.long 0x0 6. "TS_COMP_TOG,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode 1=TS_COMP is in toggle mode" "0: TS_COMP is in non-toggle mode,1: TS_COMP is in toggle mode" bitfld.long 0x0 5. "MODE,Timestamp mode" "0,1" newline bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable" "0,1" bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1" newline bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1" bitfld.long 0x0 1. "INT_TEST,Interrupt test" "0,1" newline bitfld.long 0x0 0. "CPTS_EN,Time sync enable" "0,1" line.long 0x4 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_RFTCLK_SEL_REG,RFTCLK Select Register" hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PUSH_REG,Time Stamp Event Push Register" bitfld.long 0x0 0. "TS_PUSH,Time stamp event push" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_LOW_VAL_REG,Time Stamp Load Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_EN_REG,Time Stamp Load Enable Register" bitfld.long 0x0 0. "TS_LOAD_EN,Time stamp load enable" "0,1" rgroup.long 0x18++0xB line.long 0x0 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LOW_VAL_REG,Time Stamp Comparison Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time stamp comparison low value" line.long 0x4 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LEN_REG,Time Stamp Comparison Length Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time stamp comparison length" line.long 0x8 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_RAW_REG,Interrupt Status Register Raw" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_MASKED_REG,Interrupt Status Register Masked" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" rgroup.long 0x28++0x7 line.long 0x0 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_INT_ENABLE_REG,Interrupt Enable Register" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" line.long 0x4 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount" rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_POP_REG,Event Pop Register" bitfld.long 0x0 0. "EVENT_POP,Event pop" "0,1" rgroup.long 0x34++0xF line.long 0x0 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_0_REG,Event 0 Register" hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp" line.long 0x4 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_1_REG,Event 1 Register" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1" hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port number" newline hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Event type" hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type" newline hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID" line.long 0x8 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_2_REG,Event 2 Register" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain" line.long 0xC "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_3_REG,Event 3 Register" hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp" rgroup.long 0x44++0x17 line.long 0x0 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load high value" line.long 0x4 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time stamp comparison high value" line.long 0x8 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_TS_ADD_VAL_REG,TS Add Value Register" bitfld.long 0x8 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7" line.long 0xC "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register" hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time stamp PPM Low value" line.long 0x10 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value" line.long 0x14 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value" rgroup.long 0xD0++0x3 line.long 0x0 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_TS_CONFIG,Time Stamp Configuration Read" hexmask.long.byte 0x0 8.--15. 1. "EVNT_FIFO_DEPTH,The Event FIFO Depth" hexmask.long.byte 0x0 0.--7. 1. "NUM_GENF,The number of CPTS GENF outputs" rgroup.long 0xE0++0x1B line.long 0x0 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value" rgroup.long 0x200++0x1B line.long 0x0 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp ESTF Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp ESTF Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp ESTF Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp ESTF Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp ESTF Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp ESTF Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_12_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_CPTS_0_VIRT_ALIAS_13_CPTS0_S_VBUSP_CPTS_VBUSP (NAVSS0_CPTS_0_VIRT_ALIAS_13_CPTS0_S_VBUSP_CPTS_VBUSP)" base ad:0x4BD10D0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_CPTS_IDVER_REG,Identification and Version Register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Sync Control Register" hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" bitfld.long 0x0 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1" newline bitfld.long 0x0 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1" bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1" newline bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1" bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1" newline bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1" bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" newline bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" newline bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" bitfld.long 0x0 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1" newline bitfld.long 0x0 6. "TS_COMP_TOG,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode 1=TS_COMP is in toggle mode" "0: TS_COMP is in non-toggle mode,1: TS_COMP is in toggle mode" bitfld.long 0x0 5. "MODE,Timestamp mode" "0,1" newline bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable" "0,1" bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1" newline bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1" bitfld.long 0x0 1. "INT_TEST,Interrupt test" "0,1" newline bitfld.long 0x0 0. "CPTS_EN,Time sync enable" "0,1" line.long 0x4 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_RFTCLK_SEL_REG,RFTCLK Select Register" hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PUSH_REG,Time Stamp Event Push Register" bitfld.long 0x0 0. "TS_PUSH,Time stamp event push" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_LOW_VAL_REG,Time Stamp Load Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_EN_REG,Time Stamp Load Enable Register" bitfld.long 0x0 0. "TS_LOAD_EN,Time stamp load enable" "0,1" rgroup.long 0x18++0xB line.long 0x0 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LOW_VAL_REG,Time Stamp Comparison Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time stamp comparison low value" line.long 0x4 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LEN_REG,Time Stamp Comparison Length Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time stamp comparison length" line.long 0x8 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_RAW_REG,Interrupt Status Register Raw" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_MASKED_REG,Interrupt Status Register Masked" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" rgroup.long 0x28++0x7 line.long 0x0 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_INT_ENABLE_REG,Interrupt Enable Register" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" line.long 0x4 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount" rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_POP_REG,Event Pop Register" bitfld.long 0x0 0. "EVENT_POP,Event pop" "0,1" rgroup.long 0x34++0xF line.long 0x0 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_0_REG,Event 0 Register" hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp" line.long 0x4 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_1_REG,Event 1 Register" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1" hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port number" newline hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Event type" hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type" newline hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID" line.long 0x8 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_2_REG,Event 2 Register" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain" line.long 0xC "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_3_REG,Event 3 Register" hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp" rgroup.long 0x44++0x17 line.long 0x0 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load high value" line.long 0x4 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time stamp comparison high value" line.long 0x8 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_TS_ADD_VAL_REG,TS Add Value Register" bitfld.long 0x8 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7" line.long 0xC "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register" hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time stamp PPM Low value" line.long 0x10 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value" line.long 0x14 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value" rgroup.long 0xD0++0x3 line.long 0x0 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_TS_CONFIG,Time Stamp Configuration Read" hexmask.long.byte 0x0 8.--15. 1. "EVNT_FIFO_DEPTH,The Event FIFO Depth" hexmask.long.byte 0x0 0.--7. 1. "NUM_GENF,The number of CPTS GENF outputs" rgroup.long 0xE0++0x1B line.long 0x0 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value" rgroup.long 0x200++0x1B line.long 0x0 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp ESTF Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp ESTF Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp ESTF Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp ESTF Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp ESTF Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp ESTF Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_13_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_CPTS_0_VIRT_ALIAS_14_CPTS0_S_VBUSP_CPTS_VBUSP (NAVSS0_CPTS_0_VIRT_ALIAS_14_CPTS0_S_VBUSP_CPTS_VBUSP)" base ad:0x4BE10D0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_CPTS_IDVER_REG,Identification and Version Register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Sync Control Register" hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" bitfld.long 0x0 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1" newline bitfld.long 0x0 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1" bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1" newline bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1" bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1" newline bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1" bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" newline bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" newline bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" bitfld.long 0x0 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1" newline bitfld.long 0x0 6. "TS_COMP_TOG,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode 1=TS_COMP is in toggle mode" "0: TS_COMP is in non-toggle mode,1: TS_COMP is in toggle mode" bitfld.long 0x0 5. "MODE,Timestamp mode" "0,1" newline bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable" "0,1" bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1" newline bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1" bitfld.long 0x0 1. "INT_TEST,Interrupt test" "0,1" newline bitfld.long 0x0 0. "CPTS_EN,Time sync enable" "0,1" line.long 0x4 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_RFTCLK_SEL_REG,RFTCLK Select Register" hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PUSH_REG,Time Stamp Event Push Register" bitfld.long 0x0 0. "TS_PUSH,Time stamp event push" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_LOW_VAL_REG,Time Stamp Load Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_EN_REG,Time Stamp Load Enable Register" bitfld.long 0x0 0. "TS_LOAD_EN,Time stamp load enable" "0,1" rgroup.long 0x18++0xB line.long 0x0 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LOW_VAL_REG,Time Stamp Comparison Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time stamp comparison low value" line.long 0x4 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LEN_REG,Time Stamp Comparison Length Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time stamp comparison length" line.long 0x8 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_RAW_REG,Interrupt Status Register Raw" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_MASKED_REG,Interrupt Status Register Masked" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" rgroup.long 0x28++0x7 line.long 0x0 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_INT_ENABLE_REG,Interrupt Enable Register" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" line.long 0x4 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount" rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_POP_REG,Event Pop Register" bitfld.long 0x0 0. "EVENT_POP,Event pop" "0,1" rgroup.long 0x34++0xF line.long 0x0 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_0_REG,Event 0 Register" hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp" line.long 0x4 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_1_REG,Event 1 Register" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1" hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port number" newline hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Event type" hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type" newline hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID" line.long 0x8 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_2_REG,Event 2 Register" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain" line.long 0xC "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_3_REG,Event 3 Register" hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp" rgroup.long 0x44++0x17 line.long 0x0 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load high value" line.long 0x4 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time stamp comparison high value" line.long 0x8 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_TS_ADD_VAL_REG,TS Add Value Register" bitfld.long 0x8 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7" line.long 0xC "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register" hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time stamp PPM Low value" line.long 0x10 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value" line.long 0x14 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value" rgroup.long 0xD0++0x3 line.long 0x0 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_TS_CONFIG,Time Stamp Configuration Read" hexmask.long.byte 0x0 8.--15. 1. "EVNT_FIFO_DEPTH,The Event FIFO Depth" hexmask.long.byte 0x0 0.--7. 1. "NUM_GENF,The number of CPTS GENF outputs" rgroup.long 0xE0++0x1B line.long 0x0 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value" rgroup.long 0x200++0x1B line.long 0x0 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp ESTF Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp ESTF Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp ESTF Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp ESTF Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp ESTF Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp ESTF Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_14_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_CPTS_0_VIRT_ALIAS_15_CPTS0_S_VBUSP_CPTS_VBUSP (NAVSS0_CPTS_0_VIRT_ALIAS_15_CPTS0_S_VBUSP_CPTS_VBUSP)" base ad:0x4BF10D0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_CPTS_IDVER_REG,Identification and Version Register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Sync Control Register" hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" bitfld.long 0x0 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1" newline bitfld.long 0x0 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1" bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1" newline bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1" bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1" newline bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1" bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" newline bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" newline bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" bitfld.long 0x0 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1" newline bitfld.long 0x0 6. "TS_COMP_TOG,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode 1=TS_COMP is in toggle mode" "0: TS_COMP is in non-toggle mode,1: TS_COMP is in toggle mode" bitfld.long 0x0 5. "MODE,Timestamp mode" "0,1" newline bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable" "0,1" bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1" newline bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1" bitfld.long 0x0 1. "INT_TEST,Interrupt test" "0,1" newline bitfld.long 0x0 0. "CPTS_EN,Time sync enable" "0,1" line.long 0x4 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_RFTCLK_SEL_REG,RFTCLK Select Register" hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PUSH_REG,Time Stamp Event Push Register" bitfld.long 0x0 0. "TS_PUSH,Time stamp event push" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_LOW_VAL_REG,Time Stamp Load Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_EN_REG,Time Stamp Load Enable Register" bitfld.long 0x0 0. "TS_LOAD_EN,Time stamp load enable" "0,1" rgroup.long 0x18++0xB line.long 0x0 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LOW_VAL_REG,Time Stamp Comparison Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time stamp comparison low value" line.long 0x4 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_LEN_REG,Time Stamp Comparison Length Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time stamp comparison length" line.long 0x8 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_RAW_REG,Interrupt Status Register Raw" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_INTSTAT_MASKED_REG,Interrupt Status Register Masked" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" rgroup.long 0x28++0x7 line.long 0x0 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_INT_ENABLE_REG,Interrupt Enable Register" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" line.long 0x4 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount" rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_POP_REG,Event Pop Register" bitfld.long 0x0 0. "EVENT_POP,Event pop" "0,1" rgroup.long 0x34++0xF line.long 0x0 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_0_REG,Event 0 Register" hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp" line.long 0x4 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_1_REG,Event 1 Register" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1" hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port number" newline hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Event type" hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type" newline hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID" line.long 0x8 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_2_REG,Event 2 Register" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain" line.long 0xC "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_EVENT_3_REG,Event 3 Register" hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp" rgroup.long 0x44++0x17 line.long 0x0 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load high value" line.long 0x4 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time stamp comparison high value" line.long 0x8 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_TS_ADD_VAL_REG,TS Add Value Register" bitfld.long 0x8 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7" line.long 0xC "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register" hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time stamp PPM Low value" line.long 0x10 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value" line.long 0x14 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value" rgroup.long 0xD0++0x3 line.long 0x0 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_TS_CONFIG,Time Stamp Configuration Read" hexmask.long.byte 0x0 8.--15. 1. "EVNT_FIFO_DEPTH,The Event FIFO Depth" hexmask.long.byte 0x0 0.--7. 1. "NUM_GENF,The number of CPTS GENF outputs" rgroup.long 0xE0++0x1B line.long 0x0 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value" rgroup.long 0x200++0x1B line.long 0x0 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp ESTF Generate Function Comparison Low Value" line.long 0x4 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp ESTF Generate Function Comparison High Value" line.long 0x8 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_CONTROL_REG,Time Stamp ESTF Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1" line.long 0xC "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_LENGTH_REG,Time Stamp ESTF Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp ESTF Generate Function Length Value" line.long 0x10 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp ESTF Generate Function PPM Low Value" line.long 0x14 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value" line.long 0x18 "VIRT_ALIAS_15_CPTS0__S_VBUSP__CPTS_VBUSP_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value" tree.end endif tree.end tree.end tree "NAVSS0_DMA_VIRTID" tree "NAVSS0_DMA_VIRTID_0" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_0_NAV_DDR0_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_0_NAV_DDR0_VIRTID_CFG_MMRS)" base ad:0x30A02000 rgroup.long 0x0++0x3 line.long 0x0 "NAV_DDR0_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "NAV_DDR0_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_0_NAV_DDR0_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_0_NAV_DDR0_VIRTID_CFG_MMRS)" base ad:0x4B00A02000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_NAV_DDR0_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_NAV_DDR0_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_1_NAV_DDR0_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_1_NAV_DDR0_VIRTID_CFG_MMRS)" base ad:0x4B10A02000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_NAV_DDR0_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_NAV_DDR0_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_2_NAV_DDR0_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_2_NAV_DDR0_VIRTID_CFG_MMRS)" base ad:0x4B20A02000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_NAV_DDR0_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_NAV_DDR0_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_3_NAV_DDR0_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_3_NAV_DDR0_VIRTID_CFG_MMRS)" base ad:0x4B30A02000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_NAV_DDR0_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_NAV_DDR0_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_4_NAV_DDR0_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_4_NAV_DDR0_VIRTID_CFG_MMRS)" base ad:0x4B40A02000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_NAV_DDR0_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_NAV_DDR0_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_5_NAV_DDR0_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_5_NAV_DDR0_VIRTID_CFG_MMRS)" base ad:0x4B50A02000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_NAV_DDR0_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_NAV_DDR0_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_6_NAV_DDR0_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_6_NAV_DDR0_VIRTID_CFG_MMRS)" base ad:0x4B60A02000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_NAV_DDR0_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_NAV_DDR0_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_7_NAV_DDR0_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_7_NAV_DDR0_VIRTID_CFG_MMRS)" base ad:0x4B70A02000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_NAV_DDR0_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_NAV_DDR0_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_8_NAV_DDR0_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_8_NAV_DDR0_VIRTID_CFG_MMRS)" base ad:0x4B80A02000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_NAV_DDR0_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_NAV_DDR0_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_9_NAV_DDR0_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_9_NAV_DDR0_VIRTID_CFG_MMRS)" base ad:0x4B90A02000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_NAV_DDR0_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_NAV_DDR0_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_10_NAV_DDR0_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_10_NAV_DDR0_VIRTID_CFG_MMRS)" base ad:0x4BA0A02000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_NAV_DDR0_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_NAV_DDR0_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_11_NAV_DDR0_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_11_NAV_DDR0_VIRTID_CFG_MMRS)" base ad:0x4BB0A02000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_NAV_DDR0_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_NAV_DDR0_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_12_NAV_DDR0_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_12_NAV_DDR0_VIRTID_CFG_MMRS)" base ad:0x4BC0A02000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_NAV_DDR0_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_NAV_DDR0_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_13_NAV_DDR0_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_13_NAV_DDR0_VIRTID_CFG_MMRS)" base ad:0x4BD0A02000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_NAV_DDR0_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_NAV_DDR0_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_14_NAV_DDR0_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_14_NAV_DDR0_VIRTID_CFG_MMRS)" base ad:0x4BE0A02000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_NAV_DDR0_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_NAV_DDR0_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_15_NAV_DDR0_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_0_VIRT_ALIAS_15_NAV_DDR0_VIRTID_CFG_MMRS)" base ad:0x4BF0A02000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_NAV_DDR0_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_NAV_DDR0_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif tree.end tree "NAVSS0_DMA_VIRTID_1" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_1_NAV_DDR1_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_1_NAV_DDR1_VIRTID_CFG_MMRS)" base ad:0x30A03000 rgroup.long 0x0++0x3 line.long 0x0 "NAV_DDR1_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "NAV_DDR1_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_0_NAV_DDR1_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_0_NAV_DDR1_VIRTID_CFG_MMRS)" base ad:0x4B00A03000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_NAV_DDR1_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_NAV_DDR1_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_1_NAV_DDR1_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_1_NAV_DDR1_VIRTID_CFG_MMRS)" base ad:0x4B10A03000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_NAV_DDR1_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_NAV_DDR1_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_2_NAV_DDR1_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_2_NAV_DDR1_VIRTID_CFG_MMRS)" base ad:0x4B20A03000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_NAV_DDR1_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_NAV_DDR1_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_3_NAV_DDR1_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_3_NAV_DDR1_VIRTID_CFG_MMRS)" base ad:0x4B30A03000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_NAV_DDR1_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_NAV_DDR1_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_4_NAV_DDR1_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_4_NAV_DDR1_VIRTID_CFG_MMRS)" base ad:0x4B40A03000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_NAV_DDR1_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_NAV_DDR1_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_5_NAV_DDR1_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_5_NAV_DDR1_VIRTID_CFG_MMRS)" base ad:0x4B50A03000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_NAV_DDR1_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_NAV_DDR1_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_6_NAV_DDR1_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_6_NAV_DDR1_VIRTID_CFG_MMRS)" base ad:0x4B60A03000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_NAV_DDR1_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_NAV_DDR1_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_7_NAV_DDR1_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_7_NAV_DDR1_VIRTID_CFG_MMRS)" base ad:0x4B70A03000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_NAV_DDR1_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_NAV_DDR1_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_8_NAV_DDR1_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_8_NAV_DDR1_VIRTID_CFG_MMRS)" base ad:0x4B80A03000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_NAV_DDR1_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_NAV_DDR1_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_9_NAV_DDR1_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_9_NAV_DDR1_VIRTID_CFG_MMRS)" base ad:0x4B90A03000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_NAV_DDR1_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_NAV_DDR1_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_10_NAV_DDR1_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_10_NAV_DDR1_VIRTID_CFG_MMRS)" base ad:0x4BA0A03000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_NAV_DDR1_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_NAV_DDR1_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_11_NAV_DDR1_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_11_NAV_DDR1_VIRTID_CFG_MMRS)" base ad:0x4BB0A03000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_NAV_DDR1_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_NAV_DDR1_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_12_NAV_DDR1_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_12_NAV_DDR1_VIRTID_CFG_MMRS)" base ad:0x4BC0A03000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_NAV_DDR1_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_NAV_DDR1_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_13_NAV_DDR1_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_13_NAV_DDR1_VIRTID_CFG_MMRS)" base ad:0x4BD0A03000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_NAV_DDR1_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_NAV_DDR1_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_14_NAV_DDR1_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_14_NAV_DDR1_VIRTID_CFG_MMRS)" base ad:0x4BE0A03000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_NAV_DDR1_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_NAV_DDR1_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_15_NAV_DDR1_VIRTID_CFG_MMRS (NAVSS0_DMA_VIRTID_1_VIRT_ALIAS_15_NAV_DDR1_VIRTID_CFG_MMRS)" base ad:0x4BF0A03000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_NAV_DDR1_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_NAV_DDR1_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif tree.end tree.end tree "NAVSS0_INTR_0" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_INTR_0_INTR0_INTR_ROUTER_CFG (NAVSS0_INTR_0_INTR0_INTR_ROUTER_CFG)" base ad:0x310E0000 rgroup.long 0x0++0x3 line.long 0x0 "INTR0__CFG__INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" rgroup.long 0x4++0x3 line.long 0x0 "INTR0__CFG__INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.word 0x0 0.--8. 1. "MUX_CNTL,Mux control for interrupt N" tree.end endif tree "NAVSS0_INTR_0_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_INTR_0_VIRT_ALIAS_0_INTR0_CFG_INTR_ROUTER_CFG (NAVSS0_INTR_0_VIRT_ALIAS_0_INTR0_CFG_INTR_ROUTER_CFG)" base ad:0x4B010E0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_INTR0__CFG__INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_0_INTR0__CFG__INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.word 0x0 0.--8. 1. "MUX_CNTL,Mux control for interrupt N" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_INTR_0_VIRT_ALIAS_1_INTR0_CFG_INTR_ROUTER_CFG (NAVSS0_INTR_0_VIRT_ALIAS_1_INTR0_CFG_INTR_ROUTER_CFG)" base ad:0x4B110E0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_INTR0__CFG__INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_1_INTR0__CFG__INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.word 0x0 0.--8. 1. "MUX_CNTL,Mux control for interrupt N" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_INTR_0_VIRT_ALIAS_2_INTR0_CFG_INTR_ROUTER_CFG (NAVSS0_INTR_0_VIRT_ALIAS_2_INTR0_CFG_INTR_ROUTER_CFG)" base ad:0x4B210E0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_INTR0__CFG__INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_2_INTR0__CFG__INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.word 0x0 0.--8. 1. "MUX_CNTL,Mux control for interrupt N" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_INTR_0_VIRT_ALIAS_3_INTR0_CFG_INTR_ROUTER_CFG (NAVSS0_INTR_0_VIRT_ALIAS_3_INTR0_CFG_INTR_ROUTER_CFG)" base ad:0x4B310E0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_INTR0__CFG__INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_3_INTR0__CFG__INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.word 0x0 0.--8. 1. "MUX_CNTL,Mux control for interrupt N" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_INTR_0_VIRT_ALIAS_4_INTR0_CFG_INTR_ROUTER_CFG (NAVSS0_INTR_0_VIRT_ALIAS_4_INTR0_CFG_INTR_ROUTER_CFG)" base ad:0x4B410E0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_INTR0__CFG__INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_4_INTR0__CFG__INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.word 0x0 0.--8. 1. "MUX_CNTL,Mux control for interrupt N" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_INTR_0_VIRT_ALIAS_5_INTR0_CFG_INTR_ROUTER_CFG (NAVSS0_INTR_0_VIRT_ALIAS_5_INTR0_CFG_INTR_ROUTER_CFG)" base ad:0x4B510E0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_INTR0__CFG__INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_5_INTR0__CFG__INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.word 0x0 0.--8. 1. "MUX_CNTL,Mux control for interrupt N" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_INTR_0_VIRT_ALIAS_6_INTR0_CFG_INTR_ROUTER_CFG (NAVSS0_INTR_0_VIRT_ALIAS_6_INTR0_CFG_INTR_ROUTER_CFG)" base ad:0x4B610E0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_INTR0__CFG__INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_6_INTR0__CFG__INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.word 0x0 0.--8. 1. "MUX_CNTL,Mux control for interrupt N" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_INTR_0_VIRT_ALIAS_7_INTR0_CFG_INTR_ROUTER_CFG (NAVSS0_INTR_0_VIRT_ALIAS_7_INTR0_CFG_INTR_ROUTER_CFG)" base ad:0x4B710E0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_INTR0__CFG__INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_7_INTR0__CFG__INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.word 0x0 0.--8. 1. "MUX_CNTL,Mux control for interrupt N" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_INTR_0_VIRT_ALIAS_8_INTR0_CFG_INTR_ROUTER_CFG (NAVSS0_INTR_0_VIRT_ALIAS_8_INTR0_CFG_INTR_ROUTER_CFG)" base ad:0x4B810E0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_INTR0__CFG__INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_8_INTR0__CFG__INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.word 0x0 0.--8. 1. "MUX_CNTL,Mux control for interrupt N" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_INTR_0_VIRT_ALIAS_9_INTR0_CFG_INTR_ROUTER_CFG (NAVSS0_INTR_0_VIRT_ALIAS_9_INTR0_CFG_INTR_ROUTER_CFG)" base ad:0x4B910E0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_INTR0__CFG__INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_9_INTR0__CFG__INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.word 0x0 0.--8. 1. "MUX_CNTL,Mux control for interrupt N" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_INTR_0_VIRT_ALIAS_10_INTR0_CFG_INTR_ROUTER_CFG (NAVSS0_INTR_0_VIRT_ALIAS_10_INTR0_CFG_INTR_ROUTER_CFG)" base ad:0x4BA10E0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_INTR0__CFG__INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_10_INTR0__CFG__INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.word 0x0 0.--8. 1. "MUX_CNTL,Mux control for interrupt N" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_INTR_0_VIRT_ALIAS_11_INTR0_CFG_INTR_ROUTER_CFG (NAVSS0_INTR_0_VIRT_ALIAS_11_INTR0_CFG_INTR_ROUTER_CFG)" base ad:0x4BB10E0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_INTR0__CFG__INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_11_INTR0__CFG__INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.word 0x0 0.--8. 1. "MUX_CNTL,Mux control for interrupt N" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_INTR_0_VIRT_ALIAS_12_INTR0_CFG_INTR_ROUTER_CFG (NAVSS0_INTR_0_VIRT_ALIAS_12_INTR0_CFG_INTR_ROUTER_CFG)" base ad:0x4BC10E0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_INTR0__CFG__INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_12_INTR0__CFG__INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.word 0x0 0.--8. 1. "MUX_CNTL,Mux control for interrupt N" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_INTR_0_VIRT_ALIAS_13_INTR0_CFG_INTR_ROUTER_CFG (NAVSS0_INTR_0_VIRT_ALIAS_13_INTR0_CFG_INTR_ROUTER_CFG)" base ad:0x4BD10E0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_INTR0__CFG__INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_13_INTR0__CFG__INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.word 0x0 0.--8. 1. "MUX_CNTL,Mux control for interrupt N" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_INTR_0_VIRT_ALIAS_14_INTR0_CFG_INTR_ROUTER_CFG (NAVSS0_INTR_0_VIRT_ALIAS_14_INTR0_CFG_INTR_ROUTER_CFG)" base ad:0x4BE10E0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_INTR0__CFG__INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_14_INTR0__CFG__INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.word 0x0 0.--8. 1. "MUX_CNTL,Mux control for interrupt N" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_INTR_0_VIRT_ALIAS_15_INTR0_CFG_INTR_ROUTER_CFG (NAVSS0_INTR_0_VIRT_ALIAS_15_INTR0_CFG_INTR_ROUTER_CFG)" base ad:0x4BF10E0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_INTR0__CFG__INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_15_INTR0__CFG__INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.word 0x0 0.--8. 1. "MUX_CNTL,Mux control for interrupt N" tree.end endif tree.end tree.end tree "NAVSS0_MAILBOX" tree "NAVSS0_MAILBOX_0" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_0_MAILBOX_REGS0 (NAVSS0_MAILBOX_0_MAILBOX_REGS0)" base ad:0x31F80000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX0__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX0__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX0__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX0__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_0_ALIAS64K_MAILBOX0_CFG_REGS0 (NAVSS0_MAILBOX_0_ALIAS64K_MAILBOX0_CFG_REGS0)" base ad:0x4A1F800000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX_0_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_0_VIRT_ALIAS_0_MAILBOX0_CFG_REGS0 (NAVSS0_MAILBOX_0_VIRT_ALIAS_0_MAILBOX0_CFG_REGS0)" base ad:0x4B01F80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_0_VIRT_ALIAS_1_MAILBOX0_CFG_REGS0 (NAVSS0_MAILBOX_0_VIRT_ALIAS_1_MAILBOX0_CFG_REGS0)" base ad:0x4B11F80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_0_VIRT_ALIAS_2_MAILBOX0_CFG_REGS0 (NAVSS0_MAILBOX_0_VIRT_ALIAS_2_MAILBOX0_CFG_REGS0)" base ad:0x4B21F80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_0_VIRT_ALIAS_3_MAILBOX0_CFG_REGS0 (NAVSS0_MAILBOX_0_VIRT_ALIAS_3_MAILBOX0_CFG_REGS0)" base ad:0x4B31F80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_0_VIRT_ALIAS_4_MAILBOX0_CFG_REGS0 (NAVSS0_MAILBOX_0_VIRT_ALIAS_4_MAILBOX0_CFG_REGS0)" base ad:0x4B41F80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_0_VIRT_ALIAS_5_MAILBOX0_CFG_REGS0 (NAVSS0_MAILBOX_0_VIRT_ALIAS_5_MAILBOX0_CFG_REGS0)" base ad:0x4B51F80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_0_VIRT_ALIAS_6_MAILBOX0_CFG_REGS0 (NAVSS0_MAILBOX_0_VIRT_ALIAS_6_MAILBOX0_CFG_REGS0)" base ad:0x4B61F80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_0_VIRT_ALIAS_7_MAILBOX0_CFG_REGS0 (NAVSS0_MAILBOX_0_VIRT_ALIAS_7_MAILBOX0_CFG_REGS0)" base ad:0x4B71F80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_0_VIRT_ALIAS_8_MAILBOX0_CFG_REGS0 (NAVSS0_MAILBOX_0_VIRT_ALIAS_8_MAILBOX0_CFG_REGS0)" base ad:0x4B81F80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_0_VIRT_ALIAS_9_MAILBOX0_CFG_REGS0 (NAVSS0_MAILBOX_0_VIRT_ALIAS_9_MAILBOX0_CFG_REGS0)" base ad:0x4B91F80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_0_VIRT_ALIAS_10_MAILBOX0_CFG_REGS0 (NAVSS0_MAILBOX_0_VIRT_ALIAS_10_MAILBOX0_CFG_REGS0)" base ad:0x4BA1F80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_0_VIRT_ALIAS_11_MAILBOX0_CFG_REGS0 (NAVSS0_MAILBOX_0_VIRT_ALIAS_11_MAILBOX0_CFG_REGS0)" base ad:0x4BB1F80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_0_VIRT_ALIAS_12_MAILBOX0_CFG_REGS0 (NAVSS0_MAILBOX_0_VIRT_ALIAS_12_MAILBOX0_CFG_REGS0)" base ad:0x4BC1F80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_0_VIRT_ALIAS_13_MAILBOX0_CFG_REGS0 (NAVSS0_MAILBOX_0_VIRT_ALIAS_13_MAILBOX0_CFG_REGS0)" base ad:0x4BD1F80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_0_VIRT_ALIAS_14_MAILBOX0_CFG_REGS0 (NAVSS0_MAILBOX_0_VIRT_ALIAS_14_MAILBOX0_CFG_REGS0)" base ad:0x4BE1F80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_0_VIRT_ALIAS_15_MAILBOX0_CFG_REGS0 (NAVSS0_MAILBOX_0_VIRT_ALIAS_15_MAILBOX0_CFG_REGS0)" base ad:0x4BF1F80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX0__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree "NAVSS0_MAILBOX_1" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_1_MAILBOX_REGS1 (NAVSS0_MAILBOX_1_MAILBOX_REGS1)" base ad:0x31F81000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX0__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX0__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX0__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX0__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_1_ALIAS64K_MAILBOX0_CFG_REGS1 (NAVSS0_MAILBOX_1_ALIAS64K_MAILBOX0_CFG_REGS1)" base ad:0x4A1F810000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX_1_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_1_VIRT_ALIAS_0_MAILBOX0_CFG_REGS1 (NAVSS0_MAILBOX_1_VIRT_ALIAS_0_MAILBOX0_CFG_REGS1)" base ad:0x4B01F81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_1_VIRT_ALIAS_1_MAILBOX0_CFG_REGS1 (NAVSS0_MAILBOX_1_VIRT_ALIAS_1_MAILBOX0_CFG_REGS1)" base ad:0x4B11F81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_1_VIRT_ALIAS_2_MAILBOX0_CFG_REGS1 (NAVSS0_MAILBOX_1_VIRT_ALIAS_2_MAILBOX0_CFG_REGS1)" base ad:0x4B21F81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_1_VIRT_ALIAS_3_MAILBOX0_CFG_REGS1 (NAVSS0_MAILBOX_1_VIRT_ALIAS_3_MAILBOX0_CFG_REGS1)" base ad:0x4B31F81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_1_VIRT_ALIAS_4_MAILBOX0_CFG_REGS1 (NAVSS0_MAILBOX_1_VIRT_ALIAS_4_MAILBOX0_CFG_REGS1)" base ad:0x4B41F81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_1_VIRT_ALIAS_5_MAILBOX0_CFG_REGS1 (NAVSS0_MAILBOX_1_VIRT_ALIAS_5_MAILBOX0_CFG_REGS1)" base ad:0x4B51F81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_1_VIRT_ALIAS_6_MAILBOX0_CFG_REGS1 (NAVSS0_MAILBOX_1_VIRT_ALIAS_6_MAILBOX0_CFG_REGS1)" base ad:0x4B61F81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_1_VIRT_ALIAS_7_MAILBOX0_CFG_REGS1 (NAVSS0_MAILBOX_1_VIRT_ALIAS_7_MAILBOX0_CFG_REGS1)" base ad:0x4B71F81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_1_VIRT_ALIAS_8_MAILBOX0_CFG_REGS1 (NAVSS0_MAILBOX_1_VIRT_ALIAS_8_MAILBOX0_CFG_REGS1)" base ad:0x4B81F81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_1_VIRT_ALIAS_9_MAILBOX0_CFG_REGS1 (NAVSS0_MAILBOX_1_VIRT_ALIAS_9_MAILBOX0_CFG_REGS1)" base ad:0x4B91F81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_1_VIRT_ALIAS_10_MAILBOX0_CFG_REGS1 (NAVSS0_MAILBOX_1_VIRT_ALIAS_10_MAILBOX0_CFG_REGS1)" base ad:0x4BA1F81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_1_VIRT_ALIAS_11_MAILBOX0_CFG_REGS1 (NAVSS0_MAILBOX_1_VIRT_ALIAS_11_MAILBOX0_CFG_REGS1)" base ad:0x4BB1F81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_1_VIRT_ALIAS_12_MAILBOX0_CFG_REGS1 (NAVSS0_MAILBOX_1_VIRT_ALIAS_12_MAILBOX0_CFG_REGS1)" base ad:0x4BC1F81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_1_VIRT_ALIAS_13_MAILBOX0_CFG_REGS1 (NAVSS0_MAILBOX_1_VIRT_ALIAS_13_MAILBOX0_CFG_REGS1)" base ad:0x4BD1F81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_1_VIRT_ALIAS_14_MAILBOX0_CFG_REGS1 (NAVSS0_MAILBOX_1_VIRT_ALIAS_14_MAILBOX0_CFG_REGS1)" base ad:0x4BE1F81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_1_VIRT_ALIAS_15_MAILBOX0_CFG_REGS1 (NAVSS0_MAILBOX_1_VIRT_ALIAS_15_MAILBOX0_CFG_REGS1)" base ad:0x4BF1F81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX0__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree "NAVSS0_MAILBOX_2" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_2_MAILBOX_REGS2 (NAVSS0_MAILBOX_2_MAILBOX_REGS2)" base ad:0x31F82000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX0__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX0__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX0__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX0__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_2_ALIAS64K_MAILBOX0_CFG_REGS2 (NAVSS0_MAILBOX_2_ALIAS64K_MAILBOX0_CFG_REGS2)" base ad:0x4A1F820000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX_2_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_2_VIRT_ALIAS_0_MAILBOX0_CFG_REGS2 (NAVSS0_MAILBOX_2_VIRT_ALIAS_0_MAILBOX0_CFG_REGS2)" base ad:0x4B01F82000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_2_VIRT_ALIAS_1_MAILBOX0_CFG_REGS2 (NAVSS0_MAILBOX_2_VIRT_ALIAS_1_MAILBOX0_CFG_REGS2)" base ad:0x4B11F82000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_2_VIRT_ALIAS_2_MAILBOX0_CFG_REGS2 (NAVSS0_MAILBOX_2_VIRT_ALIAS_2_MAILBOX0_CFG_REGS2)" base ad:0x4B21F82000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_2_VIRT_ALIAS_3_MAILBOX0_CFG_REGS2 (NAVSS0_MAILBOX_2_VIRT_ALIAS_3_MAILBOX0_CFG_REGS2)" base ad:0x4B31F82000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_2_VIRT_ALIAS_4_MAILBOX0_CFG_REGS2 (NAVSS0_MAILBOX_2_VIRT_ALIAS_4_MAILBOX0_CFG_REGS2)" base ad:0x4B41F82000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_2_VIRT_ALIAS_5_MAILBOX0_CFG_REGS2 (NAVSS0_MAILBOX_2_VIRT_ALIAS_5_MAILBOX0_CFG_REGS2)" base ad:0x4B51F82000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_2_VIRT_ALIAS_6_MAILBOX0_CFG_REGS2 (NAVSS0_MAILBOX_2_VIRT_ALIAS_6_MAILBOX0_CFG_REGS2)" base ad:0x4B61F82000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_2_VIRT_ALIAS_7_MAILBOX0_CFG_REGS2 (NAVSS0_MAILBOX_2_VIRT_ALIAS_7_MAILBOX0_CFG_REGS2)" base ad:0x4B71F82000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_2_VIRT_ALIAS_8_MAILBOX0_CFG_REGS2 (NAVSS0_MAILBOX_2_VIRT_ALIAS_8_MAILBOX0_CFG_REGS2)" base ad:0x4B81F82000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_2_VIRT_ALIAS_9_MAILBOX0_CFG_REGS2 (NAVSS0_MAILBOX_2_VIRT_ALIAS_9_MAILBOX0_CFG_REGS2)" base ad:0x4B91F82000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_2_VIRT_ALIAS_10_MAILBOX0_CFG_REGS2 (NAVSS0_MAILBOX_2_VIRT_ALIAS_10_MAILBOX0_CFG_REGS2)" base ad:0x4BA1F82000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_2_VIRT_ALIAS_11_MAILBOX0_CFG_REGS2 (NAVSS0_MAILBOX_2_VIRT_ALIAS_11_MAILBOX0_CFG_REGS2)" base ad:0x4BB1F82000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_2_VIRT_ALIAS_12_MAILBOX0_CFG_REGS2 (NAVSS0_MAILBOX_2_VIRT_ALIAS_12_MAILBOX0_CFG_REGS2)" base ad:0x4BC1F82000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_2_VIRT_ALIAS_13_MAILBOX0_CFG_REGS2 (NAVSS0_MAILBOX_2_VIRT_ALIAS_13_MAILBOX0_CFG_REGS2)" base ad:0x4BD1F82000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_2_VIRT_ALIAS_14_MAILBOX0_CFG_REGS2 (NAVSS0_MAILBOX_2_VIRT_ALIAS_14_MAILBOX0_CFG_REGS2)" base ad:0x4BE1F82000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_2_VIRT_ALIAS_15_MAILBOX0_CFG_REGS2 (NAVSS0_MAILBOX_2_VIRT_ALIAS_15_MAILBOX0_CFG_REGS2)" base ad:0x4BF1F82000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX0__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree "NAVSS0_MAILBOX_3" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_3_MAILBOX_REGS3 (NAVSS0_MAILBOX_3_MAILBOX_REGS3)" base ad:0x31F83000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX0__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX0__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX0__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX0__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_3_ALIAS64K_MAILBOX0_CFG_REGS3 (NAVSS0_MAILBOX_3_ALIAS64K_MAILBOX0_CFG_REGS3)" base ad:0x4A1F830000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX_3_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_3_VIRT_ALIAS_0_MAILBOX0_CFG_REGS3 (NAVSS0_MAILBOX_3_VIRT_ALIAS_0_MAILBOX0_CFG_REGS3)" base ad:0x4B01F83000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_3_VIRT_ALIAS_1_MAILBOX0_CFG_REGS3 (NAVSS0_MAILBOX_3_VIRT_ALIAS_1_MAILBOX0_CFG_REGS3)" base ad:0x4B11F83000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_3_VIRT_ALIAS_2_MAILBOX0_CFG_REGS3 (NAVSS0_MAILBOX_3_VIRT_ALIAS_2_MAILBOX0_CFG_REGS3)" base ad:0x4B21F83000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_3_VIRT_ALIAS_3_MAILBOX0_CFG_REGS3 (NAVSS0_MAILBOX_3_VIRT_ALIAS_3_MAILBOX0_CFG_REGS3)" base ad:0x4B31F83000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_3_VIRT_ALIAS_4_MAILBOX0_CFG_REGS3 (NAVSS0_MAILBOX_3_VIRT_ALIAS_4_MAILBOX0_CFG_REGS3)" base ad:0x4B41F83000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_3_VIRT_ALIAS_5_MAILBOX0_CFG_REGS3 (NAVSS0_MAILBOX_3_VIRT_ALIAS_5_MAILBOX0_CFG_REGS3)" base ad:0x4B51F83000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_3_VIRT_ALIAS_6_MAILBOX0_CFG_REGS3 (NAVSS0_MAILBOX_3_VIRT_ALIAS_6_MAILBOX0_CFG_REGS3)" base ad:0x4B61F83000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_3_VIRT_ALIAS_7_MAILBOX0_CFG_REGS3 (NAVSS0_MAILBOX_3_VIRT_ALIAS_7_MAILBOX0_CFG_REGS3)" base ad:0x4B71F83000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_3_VIRT_ALIAS_8_MAILBOX0_CFG_REGS3 (NAVSS0_MAILBOX_3_VIRT_ALIAS_8_MAILBOX0_CFG_REGS3)" base ad:0x4B81F83000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_3_VIRT_ALIAS_9_MAILBOX0_CFG_REGS3 (NAVSS0_MAILBOX_3_VIRT_ALIAS_9_MAILBOX0_CFG_REGS3)" base ad:0x4B91F83000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_3_VIRT_ALIAS_10_MAILBOX0_CFG_REGS3 (NAVSS0_MAILBOX_3_VIRT_ALIAS_10_MAILBOX0_CFG_REGS3)" base ad:0x4BA1F83000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_3_VIRT_ALIAS_11_MAILBOX0_CFG_REGS3 (NAVSS0_MAILBOX_3_VIRT_ALIAS_11_MAILBOX0_CFG_REGS3)" base ad:0x4BB1F83000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_3_VIRT_ALIAS_12_MAILBOX0_CFG_REGS3 (NAVSS0_MAILBOX_3_VIRT_ALIAS_12_MAILBOX0_CFG_REGS3)" base ad:0x4BC1F83000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_3_VIRT_ALIAS_13_MAILBOX0_CFG_REGS3 (NAVSS0_MAILBOX_3_VIRT_ALIAS_13_MAILBOX0_CFG_REGS3)" base ad:0x4BD1F83000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_3_VIRT_ALIAS_14_MAILBOX0_CFG_REGS3 (NAVSS0_MAILBOX_3_VIRT_ALIAS_14_MAILBOX0_CFG_REGS3)" base ad:0x4BE1F83000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_3_VIRT_ALIAS_15_MAILBOX0_CFG_REGS3 (NAVSS0_MAILBOX_3_VIRT_ALIAS_15_MAILBOX0_CFG_REGS3)" base ad:0x4BF1F83000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX0__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree "NAVSS0_MAILBOX_4" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_4_MAILBOX_REGS4 (NAVSS0_MAILBOX_4_MAILBOX_REGS4)" base ad:0x31F84000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX0__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX0__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX0__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX0__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_4_ALIAS64K_MAILBOX0_CFG_REGS4 (NAVSS0_MAILBOX_4_ALIAS64K_MAILBOX0_CFG_REGS4)" base ad:0x4A1F840000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX_4_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_4_VIRT_ALIAS_0_MAILBOX0_CFG_REGS4 (NAVSS0_MAILBOX_4_VIRT_ALIAS_0_MAILBOX0_CFG_REGS4)" base ad:0x4B01F84000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_4_VIRT_ALIAS_1_MAILBOX0_CFG_REGS4 (NAVSS0_MAILBOX_4_VIRT_ALIAS_1_MAILBOX0_CFG_REGS4)" base ad:0x4B11F84000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_4_VIRT_ALIAS_2_MAILBOX0_CFG_REGS4 (NAVSS0_MAILBOX_4_VIRT_ALIAS_2_MAILBOX0_CFG_REGS4)" base ad:0x4B21F84000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_4_VIRT_ALIAS_3_MAILBOX0_CFG_REGS4 (NAVSS0_MAILBOX_4_VIRT_ALIAS_3_MAILBOX0_CFG_REGS4)" base ad:0x4B31F84000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_4_VIRT_ALIAS_4_MAILBOX0_CFG_REGS4 (NAVSS0_MAILBOX_4_VIRT_ALIAS_4_MAILBOX0_CFG_REGS4)" base ad:0x4B41F84000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_4_VIRT_ALIAS_5_MAILBOX0_CFG_REGS4 (NAVSS0_MAILBOX_4_VIRT_ALIAS_5_MAILBOX0_CFG_REGS4)" base ad:0x4B51F84000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_4_VIRT_ALIAS_6_MAILBOX0_CFG_REGS4 (NAVSS0_MAILBOX_4_VIRT_ALIAS_6_MAILBOX0_CFG_REGS4)" base ad:0x4B61F84000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_4_VIRT_ALIAS_7_MAILBOX0_CFG_REGS4 (NAVSS0_MAILBOX_4_VIRT_ALIAS_7_MAILBOX0_CFG_REGS4)" base ad:0x4B71F84000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_4_VIRT_ALIAS_8_MAILBOX0_CFG_REGS4 (NAVSS0_MAILBOX_4_VIRT_ALIAS_8_MAILBOX0_CFG_REGS4)" base ad:0x4B81F84000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_4_VIRT_ALIAS_9_MAILBOX0_CFG_REGS4 (NAVSS0_MAILBOX_4_VIRT_ALIAS_9_MAILBOX0_CFG_REGS4)" base ad:0x4B91F84000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_4_VIRT_ALIAS_10_MAILBOX0_CFG_REGS4 (NAVSS0_MAILBOX_4_VIRT_ALIAS_10_MAILBOX0_CFG_REGS4)" base ad:0x4BA1F84000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_4_VIRT_ALIAS_11_MAILBOX0_CFG_REGS4 (NAVSS0_MAILBOX_4_VIRT_ALIAS_11_MAILBOX0_CFG_REGS4)" base ad:0x4BB1F84000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_4_VIRT_ALIAS_12_MAILBOX0_CFG_REGS4 (NAVSS0_MAILBOX_4_VIRT_ALIAS_12_MAILBOX0_CFG_REGS4)" base ad:0x4BC1F84000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_4_VIRT_ALIAS_13_MAILBOX0_CFG_REGS4 (NAVSS0_MAILBOX_4_VIRT_ALIAS_13_MAILBOX0_CFG_REGS4)" base ad:0x4BD1F84000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_4_VIRT_ALIAS_14_MAILBOX0_CFG_REGS4 (NAVSS0_MAILBOX_4_VIRT_ALIAS_14_MAILBOX0_CFG_REGS4)" base ad:0x4BE1F84000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_4_VIRT_ALIAS_15_MAILBOX0_CFG_REGS4 (NAVSS0_MAILBOX_4_VIRT_ALIAS_15_MAILBOX0_CFG_REGS4)" base ad:0x4BF1F84000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX0__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree "NAVSS0_MAILBOX_5" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_5_MAILBOX_REGS5 (NAVSS0_MAILBOX_5_MAILBOX_REGS5)" base ad:0x31F85000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX0__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX0__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX0__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX0__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_5_ALIAS64K_MAILBOX0_CFG_REGS5 (NAVSS0_MAILBOX_5_ALIAS64K_MAILBOX0_CFG_REGS5)" base ad:0x4A1F850000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX_5_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_5_VIRT_ALIAS_0_MAILBOX0_CFG_REGS5 (NAVSS0_MAILBOX_5_VIRT_ALIAS_0_MAILBOX0_CFG_REGS5)" base ad:0x4B01F85000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_5_VIRT_ALIAS_1_MAILBOX0_CFG_REGS5 (NAVSS0_MAILBOX_5_VIRT_ALIAS_1_MAILBOX0_CFG_REGS5)" base ad:0x4B11F85000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_5_VIRT_ALIAS_2_MAILBOX0_CFG_REGS5 (NAVSS0_MAILBOX_5_VIRT_ALIAS_2_MAILBOX0_CFG_REGS5)" base ad:0x4B21F85000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_5_VIRT_ALIAS_3_MAILBOX0_CFG_REGS5 (NAVSS0_MAILBOX_5_VIRT_ALIAS_3_MAILBOX0_CFG_REGS5)" base ad:0x4B31F85000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_5_VIRT_ALIAS_4_MAILBOX0_CFG_REGS5 (NAVSS0_MAILBOX_5_VIRT_ALIAS_4_MAILBOX0_CFG_REGS5)" base ad:0x4B41F85000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_5_VIRT_ALIAS_5_MAILBOX0_CFG_REGS5 (NAVSS0_MAILBOX_5_VIRT_ALIAS_5_MAILBOX0_CFG_REGS5)" base ad:0x4B51F85000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_5_VIRT_ALIAS_6_MAILBOX0_CFG_REGS5 (NAVSS0_MAILBOX_5_VIRT_ALIAS_6_MAILBOX0_CFG_REGS5)" base ad:0x4B61F85000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_5_VIRT_ALIAS_7_MAILBOX0_CFG_REGS5 (NAVSS0_MAILBOX_5_VIRT_ALIAS_7_MAILBOX0_CFG_REGS5)" base ad:0x4B71F85000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_5_VIRT_ALIAS_8_MAILBOX0_CFG_REGS5 (NAVSS0_MAILBOX_5_VIRT_ALIAS_8_MAILBOX0_CFG_REGS5)" base ad:0x4B81F85000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_5_VIRT_ALIAS_9_MAILBOX0_CFG_REGS5 (NAVSS0_MAILBOX_5_VIRT_ALIAS_9_MAILBOX0_CFG_REGS5)" base ad:0x4B91F85000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_5_VIRT_ALIAS_10_MAILBOX0_CFG_REGS5 (NAVSS0_MAILBOX_5_VIRT_ALIAS_10_MAILBOX0_CFG_REGS5)" base ad:0x4BA1F85000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_5_VIRT_ALIAS_11_MAILBOX0_CFG_REGS5 (NAVSS0_MAILBOX_5_VIRT_ALIAS_11_MAILBOX0_CFG_REGS5)" base ad:0x4BB1F85000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_5_VIRT_ALIAS_12_MAILBOX0_CFG_REGS5 (NAVSS0_MAILBOX_5_VIRT_ALIAS_12_MAILBOX0_CFG_REGS5)" base ad:0x4BC1F85000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_5_VIRT_ALIAS_13_MAILBOX0_CFG_REGS5 (NAVSS0_MAILBOX_5_VIRT_ALIAS_13_MAILBOX0_CFG_REGS5)" base ad:0x4BD1F85000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_5_VIRT_ALIAS_14_MAILBOX0_CFG_REGS5 (NAVSS0_MAILBOX_5_VIRT_ALIAS_14_MAILBOX0_CFG_REGS5)" base ad:0x4BE1F85000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_5_VIRT_ALIAS_15_MAILBOX0_CFG_REGS5 (NAVSS0_MAILBOX_5_VIRT_ALIAS_15_MAILBOX0_CFG_REGS5)" base ad:0x4BF1F85000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX0__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree "NAVSS0_MAILBOX_6" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_6_MAILBOX_REGS6 (NAVSS0_MAILBOX_6_MAILBOX_REGS6)" base ad:0x31F86000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX0__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX0__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX0__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX0__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_6_ALIAS64K_MAILBOX0_CFG_REGS6 (NAVSS0_MAILBOX_6_ALIAS64K_MAILBOX0_CFG_REGS6)" base ad:0x4A1F860000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX_6_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_6_VIRT_ALIAS_0_MAILBOX0_CFG_REGS6 (NAVSS0_MAILBOX_6_VIRT_ALIAS_0_MAILBOX0_CFG_REGS6)" base ad:0x4B01F86000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_6_VIRT_ALIAS_1_MAILBOX0_CFG_REGS6 (NAVSS0_MAILBOX_6_VIRT_ALIAS_1_MAILBOX0_CFG_REGS6)" base ad:0x4B11F86000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_6_VIRT_ALIAS_2_MAILBOX0_CFG_REGS6 (NAVSS0_MAILBOX_6_VIRT_ALIAS_2_MAILBOX0_CFG_REGS6)" base ad:0x4B21F86000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_6_VIRT_ALIAS_3_MAILBOX0_CFG_REGS6 (NAVSS0_MAILBOX_6_VIRT_ALIAS_3_MAILBOX0_CFG_REGS6)" base ad:0x4B31F86000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_6_VIRT_ALIAS_4_MAILBOX0_CFG_REGS6 (NAVSS0_MAILBOX_6_VIRT_ALIAS_4_MAILBOX0_CFG_REGS6)" base ad:0x4B41F86000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_6_VIRT_ALIAS_5_MAILBOX0_CFG_REGS6 (NAVSS0_MAILBOX_6_VIRT_ALIAS_5_MAILBOX0_CFG_REGS6)" base ad:0x4B51F86000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_6_VIRT_ALIAS_6_MAILBOX0_CFG_REGS6 (NAVSS0_MAILBOX_6_VIRT_ALIAS_6_MAILBOX0_CFG_REGS6)" base ad:0x4B61F86000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_6_VIRT_ALIAS_7_MAILBOX0_CFG_REGS6 (NAVSS0_MAILBOX_6_VIRT_ALIAS_7_MAILBOX0_CFG_REGS6)" base ad:0x4B71F86000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_6_VIRT_ALIAS_8_MAILBOX0_CFG_REGS6 (NAVSS0_MAILBOX_6_VIRT_ALIAS_8_MAILBOX0_CFG_REGS6)" base ad:0x4B81F86000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_6_VIRT_ALIAS_9_MAILBOX0_CFG_REGS6 (NAVSS0_MAILBOX_6_VIRT_ALIAS_9_MAILBOX0_CFG_REGS6)" base ad:0x4B91F86000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_6_VIRT_ALIAS_10_MAILBOX0_CFG_REGS6 (NAVSS0_MAILBOX_6_VIRT_ALIAS_10_MAILBOX0_CFG_REGS6)" base ad:0x4BA1F86000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_6_VIRT_ALIAS_11_MAILBOX0_CFG_REGS6 (NAVSS0_MAILBOX_6_VIRT_ALIAS_11_MAILBOX0_CFG_REGS6)" base ad:0x4BB1F86000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_6_VIRT_ALIAS_12_MAILBOX0_CFG_REGS6 (NAVSS0_MAILBOX_6_VIRT_ALIAS_12_MAILBOX0_CFG_REGS6)" base ad:0x4BC1F86000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_6_VIRT_ALIAS_13_MAILBOX0_CFG_REGS6 (NAVSS0_MAILBOX_6_VIRT_ALIAS_13_MAILBOX0_CFG_REGS6)" base ad:0x4BD1F86000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_6_VIRT_ALIAS_14_MAILBOX0_CFG_REGS6 (NAVSS0_MAILBOX_6_VIRT_ALIAS_14_MAILBOX0_CFG_REGS6)" base ad:0x4BE1F86000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_6_VIRT_ALIAS_15_MAILBOX0_CFG_REGS6 (NAVSS0_MAILBOX_6_VIRT_ALIAS_15_MAILBOX0_CFG_REGS6)" base ad:0x4BF1F86000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX0__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree "NAVSS0_MAILBOX_7" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_7_MAILBOX_REGS7 (NAVSS0_MAILBOX_7_MAILBOX_REGS7)" base ad:0x31F87000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX0__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX0__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX0__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX0__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_7_ALIAS64K_MAILBOX0_CFG_REGS7 (NAVSS0_MAILBOX_7_ALIAS64K_MAILBOX0_CFG_REGS7)" base ad:0x4A1F870000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX_7_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_7_VIRT_ALIAS_0_MAILBOX0_CFG_REGS7 (NAVSS0_MAILBOX_7_VIRT_ALIAS_0_MAILBOX0_CFG_REGS7)" base ad:0x4B01F87000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_7_VIRT_ALIAS_1_MAILBOX0_CFG_REGS7 (NAVSS0_MAILBOX_7_VIRT_ALIAS_1_MAILBOX0_CFG_REGS7)" base ad:0x4B11F87000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_7_VIRT_ALIAS_2_MAILBOX0_CFG_REGS7 (NAVSS0_MAILBOX_7_VIRT_ALIAS_2_MAILBOX0_CFG_REGS7)" base ad:0x4B21F87000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_7_VIRT_ALIAS_3_MAILBOX0_CFG_REGS7 (NAVSS0_MAILBOX_7_VIRT_ALIAS_3_MAILBOX0_CFG_REGS7)" base ad:0x4B31F87000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_7_VIRT_ALIAS_4_MAILBOX0_CFG_REGS7 (NAVSS0_MAILBOX_7_VIRT_ALIAS_4_MAILBOX0_CFG_REGS7)" base ad:0x4B41F87000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_7_VIRT_ALIAS_5_MAILBOX0_CFG_REGS7 (NAVSS0_MAILBOX_7_VIRT_ALIAS_5_MAILBOX0_CFG_REGS7)" base ad:0x4B51F87000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_7_VIRT_ALIAS_6_MAILBOX0_CFG_REGS7 (NAVSS0_MAILBOX_7_VIRT_ALIAS_6_MAILBOX0_CFG_REGS7)" base ad:0x4B61F87000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_7_VIRT_ALIAS_7_MAILBOX0_CFG_REGS7 (NAVSS0_MAILBOX_7_VIRT_ALIAS_7_MAILBOX0_CFG_REGS7)" base ad:0x4B71F87000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_7_VIRT_ALIAS_8_MAILBOX0_CFG_REGS7 (NAVSS0_MAILBOX_7_VIRT_ALIAS_8_MAILBOX0_CFG_REGS7)" base ad:0x4B81F87000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_7_VIRT_ALIAS_9_MAILBOX0_CFG_REGS7 (NAVSS0_MAILBOX_7_VIRT_ALIAS_9_MAILBOX0_CFG_REGS7)" base ad:0x4B91F87000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_7_VIRT_ALIAS_10_MAILBOX0_CFG_REGS7 (NAVSS0_MAILBOX_7_VIRT_ALIAS_10_MAILBOX0_CFG_REGS7)" base ad:0x4BA1F87000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_7_VIRT_ALIAS_11_MAILBOX0_CFG_REGS7 (NAVSS0_MAILBOX_7_VIRT_ALIAS_11_MAILBOX0_CFG_REGS7)" base ad:0x4BB1F87000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_7_VIRT_ALIAS_12_MAILBOX0_CFG_REGS7 (NAVSS0_MAILBOX_7_VIRT_ALIAS_12_MAILBOX0_CFG_REGS7)" base ad:0x4BC1F87000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_7_VIRT_ALIAS_13_MAILBOX0_CFG_REGS7 (NAVSS0_MAILBOX_7_VIRT_ALIAS_13_MAILBOX0_CFG_REGS7)" base ad:0x4BD1F87000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_7_VIRT_ALIAS_14_MAILBOX0_CFG_REGS7 (NAVSS0_MAILBOX_7_VIRT_ALIAS_14_MAILBOX0_CFG_REGS7)" base ad:0x4BE1F87000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_7_VIRT_ALIAS_15_MAILBOX0_CFG_REGS7 (NAVSS0_MAILBOX_7_VIRT_ALIAS_15_MAILBOX0_CFG_REGS7)" base ad:0x4BF1F87000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX0__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree "NAVSS0_MAILBOX_8" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_8_MAILBOX_REGS8 (NAVSS0_MAILBOX_8_MAILBOX_REGS8)" base ad:0x31F88000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX0__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX0__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX0__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX0__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_8_ALIAS64K_MAILBOX0_CFG_REGS8 (NAVSS0_MAILBOX_8_ALIAS64K_MAILBOX0_CFG_REGS8)" base ad:0x4A1F880000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX_8_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_8_VIRT_ALIAS_0_MAILBOX0_CFG_REGS8 (NAVSS0_MAILBOX_8_VIRT_ALIAS_0_MAILBOX0_CFG_REGS8)" base ad:0x4B01F88000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_8_VIRT_ALIAS_1_MAILBOX0_CFG_REGS8 (NAVSS0_MAILBOX_8_VIRT_ALIAS_1_MAILBOX0_CFG_REGS8)" base ad:0x4B11F88000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_8_VIRT_ALIAS_2_MAILBOX0_CFG_REGS8 (NAVSS0_MAILBOX_8_VIRT_ALIAS_2_MAILBOX0_CFG_REGS8)" base ad:0x4B21F88000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_8_VIRT_ALIAS_3_MAILBOX0_CFG_REGS8 (NAVSS0_MAILBOX_8_VIRT_ALIAS_3_MAILBOX0_CFG_REGS8)" base ad:0x4B31F88000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_8_VIRT_ALIAS_4_MAILBOX0_CFG_REGS8 (NAVSS0_MAILBOX_8_VIRT_ALIAS_4_MAILBOX0_CFG_REGS8)" base ad:0x4B41F88000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_8_VIRT_ALIAS_5_MAILBOX0_CFG_REGS8 (NAVSS0_MAILBOX_8_VIRT_ALIAS_5_MAILBOX0_CFG_REGS8)" base ad:0x4B51F88000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_8_VIRT_ALIAS_6_MAILBOX0_CFG_REGS8 (NAVSS0_MAILBOX_8_VIRT_ALIAS_6_MAILBOX0_CFG_REGS8)" base ad:0x4B61F88000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_8_VIRT_ALIAS_7_MAILBOX0_CFG_REGS8 (NAVSS0_MAILBOX_8_VIRT_ALIAS_7_MAILBOX0_CFG_REGS8)" base ad:0x4B71F88000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_8_VIRT_ALIAS_8_MAILBOX0_CFG_REGS8 (NAVSS0_MAILBOX_8_VIRT_ALIAS_8_MAILBOX0_CFG_REGS8)" base ad:0x4B81F88000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_8_VIRT_ALIAS_9_MAILBOX0_CFG_REGS8 (NAVSS0_MAILBOX_8_VIRT_ALIAS_9_MAILBOX0_CFG_REGS8)" base ad:0x4B91F88000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_8_VIRT_ALIAS_10_MAILBOX0_CFG_REGS8 (NAVSS0_MAILBOX_8_VIRT_ALIAS_10_MAILBOX0_CFG_REGS8)" base ad:0x4BA1F88000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_8_VIRT_ALIAS_11_MAILBOX0_CFG_REGS8 (NAVSS0_MAILBOX_8_VIRT_ALIAS_11_MAILBOX0_CFG_REGS8)" base ad:0x4BB1F88000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_8_VIRT_ALIAS_12_MAILBOX0_CFG_REGS8 (NAVSS0_MAILBOX_8_VIRT_ALIAS_12_MAILBOX0_CFG_REGS8)" base ad:0x4BC1F88000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_8_VIRT_ALIAS_13_MAILBOX0_CFG_REGS8 (NAVSS0_MAILBOX_8_VIRT_ALIAS_13_MAILBOX0_CFG_REGS8)" base ad:0x4BD1F88000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_8_VIRT_ALIAS_14_MAILBOX0_CFG_REGS8 (NAVSS0_MAILBOX_8_VIRT_ALIAS_14_MAILBOX0_CFG_REGS8)" base ad:0x4BE1F88000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_8_VIRT_ALIAS_15_MAILBOX0_CFG_REGS8 (NAVSS0_MAILBOX_8_VIRT_ALIAS_15_MAILBOX0_CFG_REGS8)" base ad:0x4BF1F88000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX0__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree "NAVSS0_MAILBOX_9" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_9_MAILBOX_REGS9 (NAVSS0_MAILBOX_9_MAILBOX_REGS9)" base ad:0x31F89000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX0__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX0__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX0__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX0__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_9_ALIAS64K_MAILBOX0_CFG_REGS9 (NAVSS0_MAILBOX_9_ALIAS64K_MAILBOX0_CFG_REGS9)" base ad:0x4A1F890000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX_9_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_9_VIRT_ALIAS_0_MAILBOX0_CFG_REGS9 (NAVSS0_MAILBOX_9_VIRT_ALIAS_0_MAILBOX0_CFG_REGS9)" base ad:0x4B01F89000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_9_VIRT_ALIAS_1_MAILBOX0_CFG_REGS9 (NAVSS0_MAILBOX_9_VIRT_ALIAS_1_MAILBOX0_CFG_REGS9)" base ad:0x4B11F89000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_9_VIRT_ALIAS_2_MAILBOX0_CFG_REGS9 (NAVSS0_MAILBOX_9_VIRT_ALIAS_2_MAILBOX0_CFG_REGS9)" base ad:0x4B21F89000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_9_VIRT_ALIAS_3_MAILBOX0_CFG_REGS9 (NAVSS0_MAILBOX_9_VIRT_ALIAS_3_MAILBOX0_CFG_REGS9)" base ad:0x4B31F89000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_9_VIRT_ALIAS_4_MAILBOX0_CFG_REGS9 (NAVSS0_MAILBOX_9_VIRT_ALIAS_4_MAILBOX0_CFG_REGS9)" base ad:0x4B41F89000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_9_VIRT_ALIAS_5_MAILBOX0_CFG_REGS9 (NAVSS0_MAILBOX_9_VIRT_ALIAS_5_MAILBOX0_CFG_REGS9)" base ad:0x4B51F89000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_9_VIRT_ALIAS_6_MAILBOX0_CFG_REGS9 (NAVSS0_MAILBOX_9_VIRT_ALIAS_6_MAILBOX0_CFG_REGS9)" base ad:0x4B61F89000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_9_VIRT_ALIAS_7_MAILBOX0_CFG_REGS9 (NAVSS0_MAILBOX_9_VIRT_ALIAS_7_MAILBOX0_CFG_REGS9)" base ad:0x4B71F89000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_9_VIRT_ALIAS_8_MAILBOX0_CFG_REGS9 (NAVSS0_MAILBOX_9_VIRT_ALIAS_8_MAILBOX0_CFG_REGS9)" base ad:0x4B81F89000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_9_VIRT_ALIAS_9_MAILBOX0_CFG_REGS9 (NAVSS0_MAILBOX_9_VIRT_ALIAS_9_MAILBOX0_CFG_REGS9)" base ad:0x4B91F89000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_9_VIRT_ALIAS_10_MAILBOX0_CFG_REGS9 (NAVSS0_MAILBOX_9_VIRT_ALIAS_10_MAILBOX0_CFG_REGS9)" base ad:0x4BA1F89000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_9_VIRT_ALIAS_11_MAILBOX0_CFG_REGS9 (NAVSS0_MAILBOX_9_VIRT_ALIAS_11_MAILBOX0_CFG_REGS9)" base ad:0x4BB1F89000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_9_VIRT_ALIAS_12_MAILBOX0_CFG_REGS9 (NAVSS0_MAILBOX_9_VIRT_ALIAS_12_MAILBOX0_CFG_REGS9)" base ad:0x4BC1F89000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_9_VIRT_ALIAS_13_MAILBOX0_CFG_REGS9 (NAVSS0_MAILBOX_9_VIRT_ALIAS_13_MAILBOX0_CFG_REGS9)" base ad:0x4BD1F89000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_9_VIRT_ALIAS_14_MAILBOX0_CFG_REGS9 (NAVSS0_MAILBOX_9_VIRT_ALIAS_14_MAILBOX0_CFG_REGS9)" base ad:0x4BE1F89000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_9_VIRT_ALIAS_15_MAILBOX0_CFG_REGS9 (NAVSS0_MAILBOX_9_VIRT_ALIAS_15_MAILBOX0_CFG_REGS9)" base ad:0x4BF1F89000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX0__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree "NAVSS0_MAILBOX_10" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_10_MAILBOX_REGS10 (NAVSS0_MAILBOX_10_MAILBOX_REGS10)" base ad:0x31F8A000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX0__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX0__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX0__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX0__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_10_ALIAS64K_MAILBOX0_CFG_REGS10 (NAVSS0_MAILBOX_10_ALIAS64K_MAILBOX0_CFG_REGS10)" base ad:0x4A1F8A0000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX_10_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_10_VIRT_ALIAS_0_MAILBOX0_CFG_REGS10 (NAVSS0_MAILBOX_10_VIRT_ALIAS_0_MAILBOX0_CFG_REGS10)" base ad:0x4B01F8A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_10_VIRT_ALIAS_1_MAILBOX0_CFG_REGS10 (NAVSS0_MAILBOX_10_VIRT_ALIAS_1_MAILBOX0_CFG_REGS10)" base ad:0x4B11F8A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_10_VIRT_ALIAS_2_MAILBOX0_CFG_REGS10 (NAVSS0_MAILBOX_10_VIRT_ALIAS_2_MAILBOX0_CFG_REGS10)" base ad:0x4B21F8A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_10_VIRT_ALIAS_3_MAILBOX0_CFG_REGS10 (NAVSS0_MAILBOX_10_VIRT_ALIAS_3_MAILBOX0_CFG_REGS10)" base ad:0x4B31F8A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_10_VIRT_ALIAS_4_MAILBOX0_CFG_REGS10 (NAVSS0_MAILBOX_10_VIRT_ALIAS_4_MAILBOX0_CFG_REGS10)" base ad:0x4B41F8A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_10_VIRT_ALIAS_5_MAILBOX0_CFG_REGS10 (NAVSS0_MAILBOX_10_VIRT_ALIAS_5_MAILBOX0_CFG_REGS10)" base ad:0x4B51F8A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_10_VIRT_ALIAS_6_MAILBOX0_CFG_REGS10 (NAVSS0_MAILBOX_10_VIRT_ALIAS_6_MAILBOX0_CFG_REGS10)" base ad:0x4B61F8A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_10_VIRT_ALIAS_7_MAILBOX0_CFG_REGS10 (NAVSS0_MAILBOX_10_VIRT_ALIAS_7_MAILBOX0_CFG_REGS10)" base ad:0x4B71F8A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_10_VIRT_ALIAS_8_MAILBOX0_CFG_REGS10 (NAVSS0_MAILBOX_10_VIRT_ALIAS_8_MAILBOX0_CFG_REGS10)" base ad:0x4B81F8A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_10_VIRT_ALIAS_9_MAILBOX0_CFG_REGS10 (NAVSS0_MAILBOX_10_VIRT_ALIAS_9_MAILBOX0_CFG_REGS10)" base ad:0x4B91F8A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_10_VIRT_ALIAS_10_MAILBOX0_CFG_REGS10 (NAVSS0_MAILBOX_10_VIRT_ALIAS_10_MAILBOX0_CFG_REGS10)" base ad:0x4BA1F8A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_10_VIRT_ALIAS_11_MAILBOX0_CFG_REGS10 (NAVSS0_MAILBOX_10_VIRT_ALIAS_11_MAILBOX0_CFG_REGS10)" base ad:0x4BB1F8A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_10_VIRT_ALIAS_12_MAILBOX0_CFG_REGS10 (NAVSS0_MAILBOX_10_VIRT_ALIAS_12_MAILBOX0_CFG_REGS10)" base ad:0x4BC1F8A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_10_VIRT_ALIAS_13_MAILBOX0_CFG_REGS10 (NAVSS0_MAILBOX_10_VIRT_ALIAS_13_MAILBOX0_CFG_REGS10)" base ad:0x4BD1F8A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_10_VIRT_ALIAS_14_MAILBOX0_CFG_REGS10 (NAVSS0_MAILBOX_10_VIRT_ALIAS_14_MAILBOX0_CFG_REGS10)" base ad:0x4BE1F8A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_10_VIRT_ALIAS_15_MAILBOX0_CFG_REGS10 (NAVSS0_MAILBOX_10_VIRT_ALIAS_15_MAILBOX0_CFG_REGS10)" base ad:0x4BF1F8A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX0__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree "NAVSS0_MAILBOX_11" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_11_MAILBOX_REGS11 (NAVSS0_MAILBOX_11_MAILBOX_REGS11)" base ad:0x31F8B000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX0__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX0__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX0__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX0__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX0__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_11_ALIAS64K_MAILBOX0_CFG_REGS11 (NAVSS0_MAILBOX_11_ALIAS64K_MAILBOX0_CFG_REGS11)" base ad:0x4A1F8B0000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX_11_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_11_VIRT_ALIAS_0_MAILBOX0_CFG_REGS11 (NAVSS0_MAILBOX_11_VIRT_ALIAS_0_MAILBOX0_CFG_REGS11)" base ad:0x4B01F8B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_11_VIRT_ALIAS_1_MAILBOX0_CFG_REGS11 (NAVSS0_MAILBOX_11_VIRT_ALIAS_1_MAILBOX0_CFG_REGS11)" base ad:0x4B11F8B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_11_VIRT_ALIAS_2_MAILBOX0_CFG_REGS11 (NAVSS0_MAILBOX_11_VIRT_ALIAS_2_MAILBOX0_CFG_REGS11)" base ad:0x4B21F8B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_11_VIRT_ALIAS_3_MAILBOX0_CFG_REGS11 (NAVSS0_MAILBOX_11_VIRT_ALIAS_3_MAILBOX0_CFG_REGS11)" base ad:0x4B31F8B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_11_VIRT_ALIAS_4_MAILBOX0_CFG_REGS11 (NAVSS0_MAILBOX_11_VIRT_ALIAS_4_MAILBOX0_CFG_REGS11)" base ad:0x4B41F8B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_11_VIRT_ALIAS_5_MAILBOX0_CFG_REGS11 (NAVSS0_MAILBOX_11_VIRT_ALIAS_5_MAILBOX0_CFG_REGS11)" base ad:0x4B51F8B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_11_VIRT_ALIAS_6_MAILBOX0_CFG_REGS11 (NAVSS0_MAILBOX_11_VIRT_ALIAS_6_MAILBOX0_CFG_REGS11)" base ad:0x4B61F8B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_11_VIRT_ALIAS_7_MAILBOX0_CFG_REGS11 (NAVSS0_MAILBOX_11_VIRT_ALIAS_7_MAILBOX0_CFG_REGS11)" base ad:0x4B71F8B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_11_VIRT_ALIAS_8_MAILBOX0_CFG_REGS11 (NAVSS0_MAILBOX_11_VIRT_ALIAS_8_MAILBOX0_CFG_REGS11)" base ad:0x4B81F8B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_11_VIRT_ALIAS_9_MAILBOX0_CFG_REGS11 (NAVSS0_MAILBOX_11_VIRT_ALIAS_9_MAILBOX0_CFG_REGS11)" base ad:0x4B91F8B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_11_VIRT_ALIAS_10_MAILBOX0_CFG_REGS11 (NAVSS0_MAILBOX_11_VIRT_ALIAS_10_MAILBOX0_CFG_REGS11)" base ad:0x4BA1F8B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_11_VIRT_ALIAS_11_MAILBOX0_CFG_REGS11 (NAVSS0_MAILBOX_11_VIRT_ALIAS_11_MAILBOX0_CFG_REGS11)" base ad:0x4BB1F8B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_11_VIRT_ALIAS_12_MAILBOX0_CFG_REGS11 (NAVSS0_MAILBOX_11_VIRT_ALIAS_12_MAILBOX0_CFG_REGS11)" base ad:0x4BC1F8B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_11_VIRT_ALIAS_13_MAILBOX0_CFG_REGS11 (NAVSS0_MAILBOX_11_VIRT_ALIAS_13_MAILBOX0_CFG_REGS11)" base ad:0x4BD1F8B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_11_VIRT_ALIAS_14_MAILBOX0_CFG_REGS11 (NAVSS0_MAILBOX_11_VIRT_ALIAS_14_MAILBOX0_CFG_REGS11)" base ad:0x4BE1F8B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX_11_VIRT_ALIAS_15_MAILBOX0_CFG_REGS11 (NAVSS0_MAILBOX_11_VIRT_ALIAS_15_MAILBOX0_CFG_REGS11)" base ad:0x4BF1F8B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX0__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree.end tree "NAVSS0_MAILBOX1" tree "NAVSS0_MAILBOX1_0" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_0_MAILBOX1_REGS0 (NAVSS0_MAILBOX1_0_MAILBOX1_REGS0)" base ad:0x31F90000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX1__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX1__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX1__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX1__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_0_ALIAS64K_MAILBOX1_CFG_REGS0 (NAVSS0_MAILBOX1_0_ALIAS64K_MAILBOX1_CFG_REGS0)" base ad:0x4A1F900000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX1_0_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_0_VIRT_ALIAS_0_MAILBOX1_CFG_REGS0 (NAVSS0_MAILBOX1_0_VIRT_ALIAS_0_MAILBOX1_CFG_REGS0)" base ad:0x4B01F90000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_0_VIRT_ALIAS_1_MAILBOX1_CFG_REGS0 (NAVSS0_MAILBOX1_0_VIRT_ALIAS_1_MAILBOX1_CFG_REGS0)" base ad:0x4B11F90000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_0_VIRT_ALIAS_2_MAILBOX1_CFG_REGS0 (NAVSS0_MAILBOX1_0_VIRT_ALIAS_2_MAILBOX1_CFG_REGS0)" base ad:0x4B21F90000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_0_VIRT_ALIAS_3_MAILBOX1_CFG_REGS0 (NAVSS0_MAILBOX1_0_VIRT_ALIAS_3_MAILBOX1_CFG_REGS0)" base ad:0x4B31F90000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_0_VIRT_ALIAS_4_MAILBOX1_CFG_REGS0 (NAVSS0_MAILBOX1_0_VIRT_ALIAS_4_MAILBOX1_CFG_REGS0)" base ad:0x4B41F90000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_0_VIRT_ALIAS_5_MAILBOX1_CFG_REGS0 (NAVSS0_MAILBOX1_0_VIRT_ALIAS_5_MAILBOX1_CFG_REGS0)" base ad:0x4B51F90000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_0_VIRT_ALIAS_6_MAILBOX1_CFG_REGS0 (NAVSS0_MAILBOX1_0_VIRT_ALIAS_6_MAILBOX1_CFG_REGS0)" base ad:0x4B61F90000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_0_VIRT_ALIAS_7_MAILBOX1_CFG_REGS0 (NAVSS0_MAILBOX1_0_VIRT_ALIAS_7_MAILBOX1_CFG_REGS0)" base ad:0x4B71F90000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_0_VIRT_ALIAS_8_MAILBOX1_CFG_REGS0 (NAVSS0_MAILBOX1_0_VIRT_ALIAS_8_MAILBOX1_CFG_REGS0)" base ad:0x4B81F90000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_0_VIRT_ALIAS_9_MAILBOX1_CFG_REGS0 (NAVSS0_MAILBOX1_0_VIRT_ALIAS_9_MAILBOX1_CFG_REGS0)" base ad:0x4B91F90000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_0_VIRT_ALIAS_10_MAILBOX1_CFG_REGS0 (NAVSS0_MAILBOX1_0_VIRT_ALIAS_10_MAILBOX1_CFG_REGS0)" base ad:0x4BA1F90000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_0_VIRT_ALIAS_11_MAILBOX1_CFG_REGS0 (NAVSS0_MAILBOX1_0_VIRT_ALIAS_11_MAILBOX1_CFG_REGS0)" base ad:0x4BB1F90000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_0_VIRT_ALIAS_12_MAILBOX1_CFG_REGS0 (NAVSS0_MAILBOX1_0_VIRT_ALIAS_12_MAILBOX1_CFG_REGS0)" base ad:0x4BC1F90000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_0_VIRT_ALIAS_13_MAILBOX1_CFG_REGS0 (NAVSS0_MAILBOX1_0_VIRT_ALIAS_13_MAILBOX1_CFG_REGS0)" base ad:0x4BD1F90000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_0_VIRT_ALIAS_14_MAILBOX1_CFG_REGS0 (NAVSS0_MAILBOX1_0_VIRT_ALIAS_14_MAILBOX1_CFG_REGS0)" base ad:0x4BE1F90000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_0_VIRT_ALIAS_15_MAILBOX1_CFG_REGS0 (NAVSS0_MAILBOX1_0_VIRT_ALIAS_15_MAILBOX1_CFG_REGS0)" base ad:0x4BF1F90000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX1__CFG__REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree "NAVSS0_MAILBOX1_1" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_1_MAILBOX1_REGS1 (NAVSS0_MAILBOX1_1_MAILBOX1_REGS1)" base ad:0x31F91000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX1__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX1__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX1__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX1__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_1_ALIAS64K_MAILBOX1_CFG_REGS1 (NAVSS0_MAILBOX1_1_ALIAS64K_MAILBOX1_CFG_REGS1)" base ad:0x4A1F910000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX1_1_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_1_VIRT_ALIAS_0_MAILBOX1_CFG_REGS1 (NAVSS0_MAILBOX1_1_VIRT_ALIAS_0_MAILBOX1_CFG_REGS1)" base ad:0x4B01F91000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_1_VIRT_ALIAS_1_MAILBOX1_CFG_REGS1 (NAVSS0_MAILBOX1_1_VIRT_ALIAS_1_MAILBOX1_CFG_REGS1)" base ad:0x4B11F91000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_1_VIRT_ALIAS_2_MAILBOX1_CFG_REGS1 (NAVSS0_MAILBOX1_1_VIRT_ALIAS_2_MAILBOX1_CFG_REGS1)" base ad:0x4B21F91000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_1_VIRT_ALIAS_3_MAILBOX1_CFG_REGS1 (NAVSS0_MAILBOX1_1_VIRT_ALIAS_3_MAILBOX1_CFG_REGS1)" base ad:0x4B31F91000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_1_VIRT_ALIAS_4_MAILBOX1_CFG_REGS1 (NAVSS0_MAILBOX1_1_VIRT_ALIAS_4_MAILBOX1_CFG_REGS1)" base ad:0x4B41F91000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_1_VIRT_ALIAS_5_MAILBOX1_CFG_REGS1 (NAVSS0_MAILBOX1_1_VIRT_ALIAS_5_MAILBOX1_CFG_REGS1)" base ad:0x4B51F91000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_1_VIRT_ALIAS_6_MAILBOX1_CFG_REGS1 (NAVSS0_MAILBOX1_1_VIRT_ALIAS_6_MAILBOX1_CFG_REGS1)" base ad:0x4B61F91000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_1_VIRT_ALIAS_7_MAILBOX1_CFG_REGS1 (NAVSS0_MAILBOX1_1_VIRT_ALIAS_7_MAILBOX1_CFG_REGS1)" base ad:0x4B71F91000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_1_VIRT_ALIAS_8_MAILBOX1_CFG_REGS1 (NAVSS0_MAILBOX1_1_VIRT_ALIAS_8_MAILBOX1_CFG_REGS1)" base ad:0x4B81F91000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_1_VIRT_ALIAS_9_MAILBOX1_CFG_REGS1 (NAVSS0_MAILBOX1_1_VIRT_ALIAS_9_MAILBOX1_CFG_REGS1)" base ad:0x4B91F91000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_1_VIRT_ALIAS_10_MAILBOX1_CFG_REGS1 (NAVSS0_MAILBOX1_1_VIRT_ALIAS_10_MAILBOX1_CFG_REGS1)" base ad:0x4BA1F91000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_1_VIRT_ALIAS_11_MAILBOX1_CFG_REGS1 (NAVSS0_MAILBOX1_1_VIRT_ALIAS_11_MAILBOX1_CFG_REGS1)" base ad:0x4BB1F91000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_1_VIRT_ALIAS_12_MAILBOX1_CFG_REGS1 (NAVSS0_MAILBOX1_1_VIRT_ALIAS_12_MAILBOX1_CFG_REGS1)" base ad:0x4BC1F91000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_1_VIRT_ALIAS_13_MAILBOX1_CFG_REGS1 (NAVSS0_MAILBOX1_1_VIRT_ALIAS_13_MAILBOX1_CFG_REGS1)" base ad:0x4BD1F91000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_1_VIRT_ALIAS_14_MAILBOX1_CFG_REGS1 (NAVSS0_MAILBOX1_1_VIRT_ALIAS_14_MAILBOX1_CFG_REGS1)" base ad:0x4BE1F91000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_1_VIRT_ALIAS_15_MAILBOX1_CFG_REGS1 (NAVSS0_MAILBOX1_1_VIRT_ALIAS_15_MAILBOX1_CFG_REGS1)" base ad:0x4BF1F91000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX1__CFG__REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree "NAVSS0_MAILBOX1_2" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_2_MAILBOX1_REGS2 (NAVSS0_MAILBOX1_2_MAILBOX1_REGS2)" base ad:0x31F92000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX1__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX1__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX1__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX1__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_2_ALIAS64K_MAILBOX1_CFG_REGS2 (NAVSS0_MAILBOX1_2_ALIAS64K_MAILBOX1_CFG_REGS2)" base ad:0x4A1F920000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX1_2_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_2_VIRT_ALIAS_0_MAILBOX1_CFG_REGS2 (NAVSS0_MAILBOX1_2_VIRT_ALIAS_0_MAILBOX1_CFG_REGS2)" base ad:0x4B01F92000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_2_VIRT_ALIAS_1_MAILBOX1_CFG_REGS2 (NAVSS0_MAILBOX1_2_VIRT_ALIAS_1_MAILBOX1_CFG_REGS2)" base ad:0x4B11F92000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_2_VIRT_ALIAS_2_MAILBOX1_CFG_REGS2 (NAVSS0_MAILBOX1_2_VIRT_ALIAS_2_MAILBOX1_CFG_REGS2)" base ad:0x4B21F92000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_2_VIRT_ALIAS_3_MAILBOX1_CFG_REGS2 (NAVSS0_MAILBOX1_2_VIRT_ALIAS_3_MAILBOX1_CFG_REGS2)" base ad:0x4B31F92000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_2_VIRT_ALIAS_4_MAILBOX1_CFG_REGS2 (NAVSS0_MAILBOX1_2_VIRT_ALIAS_4_MAILBOX1_CFG_REGS2)" base ad:0x4B41F92000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_2_VIRT_ALIAS_5_MAILBOX1_CFG_REGS2 (NAVSS0_MAILBOX1_2_VIRT_ALIAS_5_MAILBOX1_CFG_REGS2)" base ad:0x4B51F92000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_2_VIRT_ALIAS_6_MAILBOX1_CFG_REGS2 (NAVSS0_MAILBOX1_2_VIRT_ALIAS_6_MAILBOX1_CFG_REGS2)" base ad:0x4B61F92000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_2_VIRT_ALIAS_7_MAILBOX1_CFG_REGS2 (NAVSS0_MAILBOX1_2_VIRT_ALIAS_7_MAILBOX1_CFG_REGS2)" base ad:0x4B71F92000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_2_VIRT_ALIAS_8_MAILBOX1_CFG_REGS2 (NAVSS0_MAILBOX1_2_VIRT_ALIAS_8_MAILBOX1_CFG_REGS2)" base ad:0x4B81F92000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_2_VIRT_ALIAS_9_MAILBOX1_CFG_REGS2 (NAVSS0_MAILBOX1_2_VIRT_ALIAS_9_MAILBOX1_CFG_REGS2)" base ad:0x4B91F92000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_2_VIRT_ALIAS_10_MAILBOX1_CFG_REGS2 (NAVSS0_MAILBOX1_2_VIRT_ALIAS_10_MAILBOX1_CFG_REGS2)" base ad:0x4BA1F92000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_2_VIRT_ALIAS_11_MAILBOX1_CFG_REGS2 (NAVSS0_MAILBOX1_2_VIRT_ALIAS_11_MAILBOX1_CFG_REGS2)" base ad:0x4BB1F92000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_2_VIRT_ALIAS_12_MAILBOX1_CFG_REGS2 (NAVSS0_MAILBOX1_2_VIRT_ALIAS_12_MAILBOX1_CFG_REGS2)" base ad:0x4BC1F92000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_2_VIRT_ALIAS_13_MAILBOX1_CFG_REGS2 (NAVSS0_MAILBOX1_2_VIRT_ALIAS_13_MAILBOX1_CFG_REGS2)" base ad:0x4BD1F92000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_2_VIRT_ALIAS_14_MAILBOX1_CFG_REGS2 (NAVSS0_MAILBOX1_2_VIRT_ALIAS_14_MAILBOX1_CFG_REGS2)" base ad:0x4BE1F92000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_2_VIRT_ALIAS_15_MAILBOX1_CFG_REGS2 (NAVSS0_MAILBOX1_2_VIRT_ALIAS_15_MAILBOX1_CFG_REGS2)" base ad:0x4BF1F92000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX1__CFG__REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree "NAVSS0_MAILBOX1_3" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_3_MAILBOX1_REGS3 (NAVSS0_MAILBOX1_3_MAILBOX1_REGS3)" base ad:0x31F93000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX1__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX1__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX1__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX1__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_3_ALIAS64K_MAILBOX1_CFG_REGS3 (NAVSS0_MAILBOX1_3_ALIAS64K_MAILBOX1_CFG_REGS3)" base ad:0x4A1F930000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX1_3_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_3_VIRT_ALIAS_0_MAILBOX1_CFG_REGS3 (NAVSS0_MAILBOX1_3_VIRT_ALIAS_0_MAILBOX1_CFG_REGS3)" base ad:0x4B01F93000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_3_VIRT_ALIAS_1_MAILBOX1_CFG_REGS3 (NAVSS0_MAILBOX1_3_VIRT_ALIAS_1_MAILBOX1_CFG_REGS3)" base ad:0x4B11F93000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_3_VIRT_ALIAS_2_MAILBOX1_CFG_REGS3 (NAVSS0_MAILBOX1_3_VIRT_ALIAS_2_MAILBOX1_CFG_REGS3)" base ad:0x4B21F93000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_3_VIRT_ALIAS_3_MAILBOX1_CFG_REGS3 (NAVSS0_MAILBOX1_3_VIRT_ALIAS_3_MAILBOX1_CFG_REGS3)" base ad:0x4B31F93000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_3_VIRT_ALIAS_4_MAILBOX1_CFG_REGS3 (NAVSS0_MAILBOX1_3_VIRT_ALIAS_4_MAILBOX1_CFG_REGS3)" base ad:0x4B41F93000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_3_VIRT_ALIAS_5_MAILBOX1_CFG_REGS3 (NAVSS0_MAILBOX1_3_VIRT_ALIAS_5_MAILBOX1_CFG_REGS3)" base ad:0x4B51F93000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_3_VIRT_ALIAS_6_MAILBOX1_CFG_REGS3 (NAVSS0_MAILBOX1_3_VIRT_ALIAS_6_MAILBOX1_CFG_REGS3)" base ad:0x4B61F93000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_3_VIRT_ALIAS_7_MAILBOX1_CFG_REGS3 (NAVSS0_MAILBOX1_3_VIRT_ALIAS_7_MAILBOX1_CFG_REGS3)" base ad:0x4B71F93000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_3_VIRT_ALIAS_8_MAILBOX1_CFG_REGS3 (NAVSS0_MAILBOX1_3_VIRT_ALIAS_8_MAILBOX1_CFG_REGS3)" base ad:0x4B81F93000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_3_VIRT_ALIAS_9_MAILBOX1_CFG_REGS3 (NAVSS0_MAILBOX1_3_VIRT_ALIAS_9_MAILBOX1_CFG_REGS3)" base ad:0x4B91F93000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_3_VIRT_ALIAS_10_MAILBOX1_CFG_REGS3 (NAVSS0_MAILBOX1_3_VIRT_ALIAS_10_MAILBOX1_CFG_REGS3)" base ad:0x4BA1F93000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_3_VIRT_ALIAS_11_MAILBOX1_CFG_REGS3 (NAVSS0_MAILBOX1_3_VIRT_ALIAS_11_MAILBOX1_CFG_REGS3)" base ad:0x4BB1F93000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_3_VIRT_ALIAS_12_MAILBOX1_CFG_REGS3 (NAVSS0_MAILBOX1_3_VIRT_ALIAS_12_MAILBOX1_CFG_REGS3)" base ad:0x4BC1F93000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_3_VIRT_ALIAS_13_MAILBOX1_CFG_REGS3 (NAVSS0_MAILBOX1_3_VIRT_ALIAS_13_MAILBOX1_CFG_REGS3)" base ad:0x4BD1F93000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_3_VIRT_ALIAS_14_MAILBOX1_CFG_REGS3 (NAVSS0_MAILBOX1_3_VIRT_ALIAS_14_MAILBOX1_CFG_REGS3)" base ad:0x4BE1F93000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_3_VIRT_ALIAS_15_MAILBOX1_CFG_REGS3 (NAVSS0_MAILBOX1_3_VIRT_ALIAS_15_MAILBOX1_CFG_REGS3)" base ad:0x4BF1F93000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX1__CFG__REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree "NAVSS0_MAILBOX1_4" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_4_MAILBOX1_REGS4 (NAVSS0_MAILBOX1_4_MAILBOX1_REGS4)" base ad:0x31F94000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX1__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX1__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX1__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX1__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_4_ALIAS64K_MAILBOX1_CFG_REGS4 (NAVSS0_MAILBOX1_4_ALIAS64K_MAILBOX1_CFG_REGS4)" base ad:0x4A1F940000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX1_4_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_4_VIRT_ALIAS_0_MAILBOX1_CFG_REGS4 (NAVSS0_MAILBOX1_4_VIRT_ALIAS_0_MAILBOX1_CFG_REGS4)" base ad:0x4B01F94000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_4_VIRT_ALIAS_1_MAILBOX1_CFG_REGS4 (NAVSS0_MAILBOX1_4_VIRT_ALIAS_1_MAILBOX1_CFG_REGS4)" base ad:0x4B11F94000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_4_VIRT_ALIAS_2_MAILBOX1_CFG_REGS4 (NAVSS0_MAILBOX1_4_VIRT_ALIAS_2_MAILBOX1_CFG_REGS4)" base ad:0x4B21F94000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_4_VIRT_ALIAS_3_MAILBOX1_CFG_REGS4 (NAVSS0_MAILBOX1_4_VIRT_ALIAS_3_MAILBOX1_CFG_REGS4)" base ad:0x4B31F94000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_4_VIRT_ALIAS_4_MAILBOX1_CFG_REGS4 (NAVSS0_MAILBOX1_4_VIRT_ALIAS_4_MAILBOX1_CFG_REGS4)" base ad:0x4B41F94000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_4_VIRT_ALIAS_5_MAILBOX1_CFG_REGS4 (NAVSS0_MAILBOX1_4_VIRT_ALIAS_5_MAILBOX1_CFG_REGS4)" base ad:0x4B51F94000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_4_VIRT_ALIAS_6_MAILBOX1_CFG_REGS4 (NAVSS0_MAILBOX1_4_VIRT_ALIAS_6_MAILBOX1_CFG_REGS4)" base ad:0x4B61F94000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_4_VIRT_ALIAS_7_MAILBOX1_CFG_REGS4 (NAVSS0_MAILBOX1_4_VIRT_ALIAS_7_MAILBOX1_CFG_REGS4)" base ad:0x4B71F94000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_4_VIRT_ALIAS_8_MAILBOX1_CFG_REGS4 (NAVSS0_MAILBOX1_4_VIRT_ALIAS_8_MAILBOX1_CFG_REGS4)" base ad:0x4B81F94000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_4_VIRT_ALIAS_9_MAILBOX1_CFG_REGS4 (NAVSS0_MAILBOX1_4_VIRT_ALIAS_9_MAILBOX1_CFG_REGS4)" base ad:0x4B91F94000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_4_VIRT_ALIAS_10_MAILBOX1_CFG_REGS4 (NAVSS0_MAILBOX1_4_VIRT_ALIAS_10_MAILBOX1_CFG_REGS4)" base ad:0x4BA1F94000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_4_VIRT_ALIAS_11_MAILBOX1_CFG_REGS4 (NAVSS0_MAILBOX1_4_VIRT_ALIAS_11_MAILBOX1_CFG_REGS4)" base ad:0x4BB1F94000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_4_VIRT_ALIAS_12_MAILBOX1_CFG_REGS4 (NAVSS0_MAILBOX1_4_VIRT_ALIAS_12_MAILBOX1_CFG_REGS4)" base ad:0x4BC1F94000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_4_VIRT_ALIAS_13_MAILBOX1_CFG_REGS4 (NAVSS0_MAILBOX1_4_VIRT_ALIAS_13_MAILBOX1_CFG_REGS4)" base ad:0x4BD1F94000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_4_VIRT_ALIAS_14_MAILBOX1_CFG_REGS4 (NAVSS0_MAILBOX1_4_VIRT_ALIAS_14_MAILBOX1_CFG_REGS4)" base ad:0x4BE1F94000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_4_VIRT_ALIAS_15_MAILBOX1_CFG_REGS4 (NAVSS0_MAILBOX1_4_VIRT_ALIAS_15_MAILBOX1_CFG_REGS4)" base ad:0x4BF1F94000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX1__CFG__REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree "NAVSS0_MAILBOX1_5" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_5_MAILBOX1_REGS5 (NAVSS0_MAILBOX1_5_MAILBOX1_REGS5)" base ad:0x31F95000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX1__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX1__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX1__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX1__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_5_ALIAS64K_MAILBOX1_CFG_REGS5 (NAVSS0_MAILBOX1_5_ALIAS64K_MAILBOX1_CFG_REGS5)" base ad:0x4A1F950000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX1_5_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_5_VIRT_ALIAS_0_MAILBOX1_CFG_REGS5 (NAVSS0_MAILBOX1_5_VIRT_ALIAS_0_MAILBOX1_CFG_REGS5)" base ad:0x4B01F95000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_5_VIRT_ALIAS_1_MAILBOX1_CFG_REGS5 (NAVSS0_MAILBOX1_5_VIRT_ALIAS_1_MAILBOX1_CFG_REGS5)" base ad:0x4B11F95000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_5_VIRT_ALIAS_2_MAILBOX1_CFG_REGS5 (NAVSS0_MAILBOX1_5_VIRT_ALIAS_2_MAILBOX1_CFG_REGS5)" base ad:0x4B21F95000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_5_VIRT_ALIAS_3_MAILBOX1_CFG_REGS5 (NAVSS0_MAILBOX1_5_VIRT_ALIAS_3_MAILBOX1_CFG_REGS5)" base ad:0x4B31F95000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_5_VIRT_ALIAS_4_MAILBOX1_CFG_REGS5 (NAVSS0_MAILBOX1_5_VIRT_ALIAS_4_MAILBOX1_CFG_REGS5)" base ad:0x4B41F95000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_5_VIRT_ALIAS_5_MAILBOX1_CFG_REGS5 (NAVSS0_MAILBOX1_5_VIRT_ALIAS_5_MAILBOX1_CFG_REGS5)" base ad:0x4B51F95000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_5_VIRT_ALIAS_6_MAILBOX1_CFG_REGS5 (NAVSS0_MAILBOX1_5_VIRT_ALIAS_6_MAILBOX1_CFG_REGS5)" base ad:0x4B61F95000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_5_VIRT_ALIAS_7_MAILBOX1_CFG_REGS5 (NAVSS0_MAILBOX1_5_VIRT_ALIAS_7_MAILBOX1_CFG_REGS5)" base ad:0x4B71F95000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_5_VIRT_ALIAS_8_MAILBOX1_CFG_REGS5 (NAVSS0_MAILBOX1_5_VIRT_ALIAS_8_MAILBOX1_CFG_REGS5)" base ad:0x4B81F95000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_5_VIRT_ALIAS_9_MAILBOX1_CFG_REGS5 (NAVSS0_MAILBOX1_5_VIRT_ALIAS_9_MAILBOX1_CFG_REGS5)" base ad:0x4B91F95000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_5_VIRT_ALIAS_10_MAILBOX1_CFG_REGS5 (NAVSS0_MAILBOX1_5_VIRT_ALIAS_10_MAILBOX1_CFG_REGS5)" base ad:0x4BA1F95000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_5_VIRT_ALIAS_11_MAILBOX1_CFG_REGS5 (NAVSS0_MAILBOX1_5_VIRT_ALIAS_11_MAILBOX1_CFG_REGS5)" base ad:0x4BB1F95000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_5_VIRT_ALIAS_12_MAILBOX1_CFG_REGS5 (NAVSS0_MAILBOX1_5_VIRT_ALIAS_12_MAILBOX1_CFG_REGS5)" base ad:0x4BC1F95000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_5_VIRT_ALIAS_13_MAILBOX1_CFG_REGS5 (NAVSS0_MAILBOX1_5_VIRT_ALIAS_13_MAILBOX1_CFG_REGS5)" base ad:0x4BD1F95000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_5_VIRT_ALIAS_14_MAILBOX1_CFG_REGS5 (NAVSS0_MAILBOX1_5_VIRT_ALIAS_14_MAILBOX1_CFG_REGS5)" base ad:0x4BE1F95000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_5_VIRT_ALIAS_15_MAILBOX1_CFG_REGS5 (NAVSS0_MAILBOX1_5_VIRT_ALIAS_15_MAILBOX1_CFG_REGS5)" base ad:0x4BF1F95000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX1__CFG__REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree "NAVSS0_MAILBOX1_6" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_6_MAILBOX1_REGS6 (NAVSS0_MAILBOX1_6_MAILBOX1_REGS6)" base ad:0x31F96000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX1__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX1__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX1__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX1__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_6_ALIAS64K_MAILBOX1_CFG_REGS6 (NAVSS0_MAILBOX1_6_ALIAS64K_MAILBOX1_CFG_REGS6)" base ad:0x4A1F960000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX1_6_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_6_VIRT_ALIAS_0_MAILBOX1_CFG_REGS6 (NAVSS0_MAILBOX1_6_VIRT_ALIAS_0_MAILBOX1_CFG_REGS6)" base ad:0x4B01F96000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_6_VIRT_ALIAS_1_MAILBOX1_CFG_REGS6 (NAVSS0_MAILBOX1_6_VIRT_ALIAS_1_MAILBOX1_CFG_REGS6)" base ad:0x4B11F96000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_6_VIRT_ALIAS_2_MAILBOX1_CFG_REGS6 (NAVSS0_MAILBOX1_6_VIRT_ALIAS_2_MAILBOX1_CFG_REGS6)" base ad:0x4B21F96000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_6_VIRT_ALIAS_3_MAILBOX1_CFG_REGS6 (NAVSS0_MAILBOX1_6_VIRT_ALIAS_3_MAILBOX1_CFG_REGS6)" base ad:0x4B31F96000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_6_VIRT_ALIAS_4_MAILBOX1_CFG_REGS6 (NAVSS0_MAILBOX1_6_VIRT_ALIAS_4_MAILBOX1_CFG_REGS6)" base ad:0x4B41F96000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_6_VIRT_ALIAS_5_MAILBOX1_CFG_REGS6 (NAVSS0_MAILBOX1_6_VIRT_ALIAS_5_MAILBOX1_CFG_REGS6)" base ad:0x4B51F96000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_6_VIRT_ALIAS_6_MAILBOX1_CFG_REGS6 (NAVSS0_MAILBOX1_6_VIRT_ALIAS_6_MAILBOX1_CFG_REGS6)" base ad:0x4B61F96000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_6_VIRT_ALIAS_7_MAILBOX1_CFG_REGS6 (NAVSS0_MAILBOX1_6_VIRT_ALIAS_7_MAILBOX1_CFG_REGS6)" base ad:0x4B71F96000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_6_VIRT_ALIAS_8_MAILBOX1_CFG_REGS6 (NAVSS0_MAILBOX1_6_VIRT_ALIAS_8_MAILBOX1_CFG_REGS6)" base ad:0x4B81F96000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_6_VIRT_ALIAS_9_MAILBOX1_CFG_REGS6 (NAVSS0_MAILBOX1_6_VIRT_ALIAS_9_MAILBOX1_CFG_REGS6)" base ad:0x4B91F96000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_6_VIRT_ALIAS_10_MAILBOX1_CFG_REGS6 (NAVSS0_MAILBOX1_6_VIRT_ALIAS_10_MAILBOX1_CFG_REGS6)" base ad:0x4BA1F96000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_6_VIRT_ALIAS_11_MAILBOX1_CFG_REGS6 (NAVSS0_MAILBOX1_6_VIRT_ALIAS_11_MAILBOX1_CFG_REGS6)" base ad:0x4BB1F96000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_6_VIRT_ALIAS_12_MAILBOX1_CFG_REGS6 (NAVSS0_MAILBOX1_6_VIRT_ALIAS_12_MAILBOX1_CFG_REGS6)" base ad:0x4BC1F96000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_6_VIRT_ALIAS_13_MAILBOX1_CFG_REGS6 (NAVSS0_MAILBOX1_6_VIRT_ALIAS_13_MAILBOX1_CFG_REGS6)" base ad:0x4BD1F96000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_6_VIRT_ALIAS_14_MAILBOX1_CFG_REGS6 (NAVSS0_MAILBOX1_6_VIRT_ALIAS_14_MAILBOX1_CFG_REGS6)" base ad:0x4BE1F96000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_6_VIRT_ALIAS_15_MAILBOX1_CFG_REGS6 (NAVSS0_MAILBOX1_6_VIRT_ALIAS_15_MAILBOX1_CFG_REGS6)" base ad:0x4BF1F96000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX1__CFG__REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree "NAVSS0_MAILBOX1_7" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_7_MAILBOX1_REGS7 (NAVSS0_MAILBOX1_7_MAILBOX1_REGS7)" base ad:0x31F97000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX1__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX1__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX1__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX1__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_7_ALIAS64K_MAILBOX1_CFG_REGS7 (NAVSS0_MAILBOX1_7_ALIAS64K_MAILBOX1_CFG_REGS7)" base ad:0x4A1F970000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX1_7_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_7_VIRT_ALIAS_0_MAILBOX1_CFG_REGS7 (NAVSS0_MAILBOX1_7_VIRT_ALIAS_0_MAILBOX1_CFG_REGS7)" base ad:0x4B01F97000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_7_VIRT_ALIAS_1_MAILBOX1_CFG_REGS7 (NAVSS0_MAILBOX1_7_VIRT_ALIAS_1_MAILBOX1_CFG_REGS7)" base ad:0x4B11F97000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_7_VIRT_ALIAS_2_MAILBOX1_CFG_REGS7 (NAVSS0_MAILBOX1_7_VIRT_ALIAS_2_MAILBOX1_CFG_REGS7)" base ad:0x4B21F97000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_7_VIRT_ALIAS_3_MAILBOX1_CFG_REGS7 (NAVSS0_MAILBOX1_7_VIRT_ALIAS_3_MAILBOX1_CFG_REGS7)" base ad:0x4B31F97000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_7_VIRT_ALIAS_4_MAILBOX1_CFG_REGS7 (NAVSS0_MAILBOX1_7_VIRT_ALIAS_4_MAILBOX1_CFG_REGS7)" base ad:0x4B41F97000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_7_VIRT_ALIAS_5_MAILBOX1_CFG_REGS7 (NAVSS0_MAILBOX1_7_VIRT_ALIAS_5_MAILBOX1_CFG_REGS7)" base ad:0x4B51F97000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_7_VIRT_ALIAS_6_MAILBOX1_CFG_REGS7 (NAVSS0_MAILBOX1_7_VIRT_ALIAS_6_MAILBOX1_CFG_REGS7)" base ad:0x4B61F97000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_7_VIRT_ALIAS_7_MAILBOX1_CFG_REGS7 (NAVSS0_MAILBOX1_7_VIRT_ALIAS_7_MAILBOX1_CFG_REGS7)" base ad:0x4B71F97000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_7_VIRT_ALIAS_8_MAILBOX1_CFG_REGS7 (NAVSS0_MAILBOX1_7_VIRT_ALIAS_8_MAILBOX1_CFG_REGS7)" base ad:0x4B81F97000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_7_VIRT_ALIAS_9_MAILBOX1_CFG_REGS7 (NAVSS0_MAILBOX1_7_VIRT_ALIAS_9_MAILBOX1_CFG_REGS7)" base ad:0x4B91F97000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_7_VIRT_ALIAS_10_MAILBOX1_CFG_REGS7 (NAVSS0_MAILBOX1_7_VIRT_ALIAS_10_MAILBOX1_CFG_REGS7)" base ad:0x4BA1F97000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_7_VIRT_ALIAS_11_MAILBOX1_CFG_REGS7 (NAVSS0_MAILBOX1_7_VIRT_ALIAS_11_MAILBOX1_CFG_REGS7)" base ad:0x4BB1F97000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_7_VIRT_ALIAS_12_MAILBOX1_CFG_REGS7 (NAVSS0_MAILBOX1_7_VIRT_ALIAS_12_MAILBOX1_CFG_REGS7)" base ad:0x4BC1F97000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_7_VIRT_ALIAS_13_MAILBOX1_CFG_REGS7 (NAVSS0_MAILBOX1_7_VIRT_ALIAS_13_MAILBOX1_CFG_REGS7)" base ad:0x4BD1F97000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_7_VIRT_ALIAS_14_MAILBOX1_CFG_REGS7 (NAVSS0_MAILBOX1_7_VIRT_ALIAS_14_MAILBOX1_CFG_REGS7)" base ad:0x4BE1F97000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_7_VIRT_ALIAS_15_MAILBOX1_CFG_REGS7 (NAVSS0_MAILBOX1_7_VIRT_ALIAS_15_MAILBOX1_CFG_REGS7)" base ad:0x4BF1F97000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX1__CFG__REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree "NAVSS0_MAILBOX1_8" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_8_MAILBOX1_REGS8 (NAVSS0_MAILBOX1_8_MAILBOX1_REGS8)" base ad:0x31F98000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX1__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX1__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX1__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX1__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_8_ALIAS64K_MAILBOX1_CFG_REGS8 (NAVSS0_MAILBOX1_8_ALIAS64K_MAILBOX1_CFG_REGS8)" base ad:0x4A1F980000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX1_8_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_8_VIRT_ALIAS_0_MAILBOX1_CFG_REGS8 (NAVSS0_MAILBOX1_8_VIRT_ALIAS_0_MAILBOX1_CFG_REGS8)" base ad:0x4B01F98000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_8_VIRT_ALIAS_1_MAILBOX1_CFG_REGS8 (NAVSS0_MAILBOX1_8_VIRT_ALIAS_1_MAILBOX1_CFG_REGS8)" base ad:0x4B11F98000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_8_VIRT_ALIAS_2_MAILBOX1_CFG_REGS8 (NAVSS0_MAILBOX1_8_VIRT_ALIAS_2_MAILBOX1_CFG_REGS8)" base ad:0x4B21F98000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_8_VIRT_ALIAS_3_MAILBOX1_CFG_REGS8 (NAVSS0_MAILBOX1_8_VIRT_ALIAS_3_MAILBOX1_CFG_REGS8)" base ad:0x4B31F98000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_8_VIRT_ALIAS_4_MAILBOX1_CFG_REGS8 (NAVSS0_MAILBOX1_8_VIRT_ALIAS_4_MAILBOX1_CFG_REGS8)" base ad:0x4B41F98000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_8_VIRT_ALIAS_5_MAILBOX1_CFG_REGS8 (NAVSS0_MAILBOX1_8_VIRT_ALIAS_5_MAILBOX1_CFG_REGS8)" base ad:0x4B51F98000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_8_VIRT_ALIAS_6_MAILBOX1_CFG_REGS8 (NAVSS0_MAILBOX1_8_VIRT_ALIAS_6_MAILBOX1_CFG_REGS8)" base ad:0x4B61F98000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_8_VIRT_ALIAS_7_MAILBOX1_CFG_REGS8 (NAVSS0_MAILBOX1_8_VIRT_ALIAS_7_MAILBOX1_CFG_REGS8)" base ad:0x4B71F98000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_8_VIRT_ALIAS_8_MAILBOX1_CFG_REGS8 (NAVSS0_MAILBOX1_8_VIRT_ALIAS_8_MAILBOX1_CFG_REGS8)" base ad:0x4B81F98000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_8_VIRT_ALIAS_9_MAILBOX1_CFG_REGS8 (NAVSS0_MAILBOX1_8_VIRT_ALIAS_9_MAILBOX1_CFG_REGS8)" base ad:0x4B91F98000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_8_VIRT_ALIAS_10_MAILBOX1_CFG_REGS8 (NAVSS0_MAILBOX1_8_VIRT_ALIAS_10_MAILBOX1_CFG_REGS8)" base ad:0x4BA1F98000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_8_VIRT_ALIAS_11_MAILBOX1_CFG_REGS8 (NAVSS0_MAILBOX1_8_VIRT_ALIAS_11_MAILBOX1_CFG_REGS8)" base ad:0x4BB1F98000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_8_VIRT_ALIAS_12_MAILBOX1_CFG_REGS8 (NAVSS0_MAILBOX1_8_VIRT_ALIAS_12_MAILBOX1_CFG_REGS8)" base ad:0x4BC1F98000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_8_VIRT_ALIAS_13_MAILBOX1_CFG_REGS8 (NAVSS0_MAILBOX1_8_VIRT_ALIAS_13_MAILBOX1_CFG_REGS8)" base ad:0x4BD1F98000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_8_VIRT_ALIAS_14_MAILBOX1_CFG_REGS8 (NAVSS0_MAILBOX1_8_VIRT_ALIAS_14_MAILBOX1_CFG_REGS8)" base ad:0x4BE1F98000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_8_VIRT_ALIAS_15_MAILBOX1_CFG_REGS8 (NAVSS0_MAILBOX1_8_VIRT_ALIAS_15_MAILBOX1_CFG_REGS8)" base ad:0x4BF1F98000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS8_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS8_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS8_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS8_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS8_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX1__CFG__REGS8_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree "NAVSS0_MAILBOX1_9" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_9_MAILBOX1_REGS9 (NAVSS0_MAILBOX1_9_MAILBOX1_REGS9)" base ad:0x31F99000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX1__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX1__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX1__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX1__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_9_ALIAS64K_MAILBOX1_CFG_REGS9 (NAVSS0_MAILBOX1_9_ALIAS64K_MAILBOX1_CFG_REGS9)" base ad:0x4A1F990000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX1_9_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_9_VIRT_ALIAS_0_MAILBOX1_CFG_REGS9 (NAVSS0_MAILBOX1_9_VIRT_ALIAS_0_MAILBOX1_CFG_REGS9)" base ad:0x4B01F99000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_9_VIRT_ALIAS_1_MAILBOX1_CFG_REGS9 (NAVSS0_MAILBOX1_9_VIRT_ALIAS_1_MAILBOX1_CFG_REGS9)" base ad:0x4B11F99000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_9_VIRT_ALIAS_2_MAILBOX1_CFG_REGS9 (NAVSS0_MAILBOX1_9_VIRT_ALIAS_2_MAILBOX1_CFG_REGS9)" base ad:0x4B21F99000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_9_VIRT_ALIAS_3_MAILBOX1_CFG_REGS9 (NAVSS0_MAILBOX1_9_VIRT_ALIAS_3_MAILBOX1_CFG_REGS9)" base ad:0x4B31F99000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_9_VIRT_ALIAS_4_MAILBOX1_CFG_REGS9 (NAVSS0_MAILBOX1_9_VIRT_ALIAS_4_MAILBOX1_CFG_REGS9)" base ad:0x4B41F99000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_9_VIRT_ALIAS_5_MAILBOX1_CFG_REGS9 (NAVSS0_MAILBOX1_9_VIRT_ALIAS_5_MAILBOX1_CFG_REGS9)" base ad:0x4B51F99000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_9_VIRT_ALIAS_6_MAILBOX1_CFG_REGS9 (NAVSS0_MAILBOX1_9_VIRT_ALIAS_6_MAILBOX1_CFG_REGS9)" base ad:0x4B61F99000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_9_VIRT_ALIAS_7_MAILBOX1_CFG_REGS9 (NAVSS0_MAILBOX1_9_VIRT_ALIAS_7_MAILBOX1_CFG_REGS9)" base ad:0x4B71F99000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_9_VIRT_ALIAS_8_MAILBOX1_CFG_REGS9 (NAVSS0_MAILBOX1_9_VIRT_ALIAS_8_MAILBOX1_CFG_REGS9)" base ad:0x4B81F99000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_9_VIRT_ALIAS_9_MAILBOX1_CFG_REGS9 (NAVSS0_MAILBOX1_9_VIRT_ALIAS_9_MAILBOX1_CFG_REGS9)" base ad:0x4B91F99000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_9_VIRT_ALIAS_10_MAILBOX1_CFG_REGS9 (NAVSS0_MAILBOX1_9_VIRT_ALIAS_10_MAILBOX1_CFG_REGS9)" base ad:0x4BA1F99000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_9_VIRT_ALIAS_11_MAILBOX1_CFG_REGS9 (NAVSS0_MAILBOX1_9_VIRT_ALIAS_11_MAILBOX1_CFG_REGS9)" base ad:0x4BB1F99000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_9_VIRT_ALIAS_12_MAILBOX1_CFG_REGS9 (NAVSS0_MAILBOX1_9_VIRT_ALIAS_12_MAILBOX1_CFG_REGS9)" base ad:0x4BC1F99000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_9_VIRT_ALIAS_13_MAILBOX1_CFG_REGS9 (NAVSS0_MAILBOX1_9_VIRT_ALIAS_13_MAILBOX1_CFG_REGS9)" base ad:0x4BD1F99000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_9_VIRT_ALIAS_14_MAILBOX1_CFG_REGS9 (NAVSS0_MAILBOX1_9_VIRT_ALIAS_14_MAILBOX1_CFG_REGS9)" base ad:0x4BE1F99000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_9_VIRT_ALIAS_15_MAILBOX1_CFG_REGS9 (NAVSS0_MAILBOX1_9_VIRT_ALIAS_15_MAILBOX1_CFG_REGS9)" base ad:0x4BF1F99000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS9_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS9_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS9_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS9_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS9_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX1__CFG__REGS9_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree "NAVSS0_MAILBOX1_10" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_10_MAILBOX1_REGS10 (NAVSS0_MAILBOX1_10_MAILBOX1_REGS10)" base ad:0x31F9A000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX1__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX1__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX1__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX1__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_10_ALIAS64K_MAILBOX1_CFG_REGS10 (NAVSS0_MAILBOX1_10_ALIAS64K_MAILBOX1_CFG_REGS10)" base ad:0x4A1F9A0000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX1_10_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_10_VIRT_ALIAS_0_MAILBOX1_CFG_REGS10 (NAVSS0_MAILBOX1_10_VIRT_ALIAS_0_MAILBOX1_CFG_REGS10)" base ad:0x4B01F9A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_10_VIRT_ALIAS_1_MAILBOX1_CFG_REGS10 (NAVSS0_MAILBOX1_10_VIRT_ALIAS_1_MAILBOX1_CFG_REGS10)" base ad:0x4B11F9A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_10_VIRT_ALIAS_2_MAILBOX1_CFG_REGS10 (NAVSS0_MAILBOX1_10_VIRT_ALIAS_2_MAILBOX1_CFG_REGS10)" base ad:0x4B21F9A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_10_VIRT_ALIAS_3_MAILBOX1_CFG_REGS10 (NAVSS0_MAILBOX1_10_VIRT_ALIAS_3_MAILBOX1_CFG_REGS10)" base ad:0x4B31F9A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_10_VIRT_ALIAS_4_MAILBOX1_CFG_REGS10 (NAVSS0_MAILBOX1_10_VIRT_ALIAS_4_MAILBOX1_CFG_REGS10)" base ad:0x4B41F9A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_10_VIRT_ALIAS_5_MAILBOX1_CFG_REGS10 (NAVSS0_MAILBOX1_10_VIRT_ALIAS_5_MAILBOX1_CFG_REGS10)" base ad:0x4B51F9A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_10_VIRT_ALIAS_6_MAILBOX1_CFG_REGS10 (NAVSS0_MAILBOX1_10_VIRT_ALIAS_6_MAILBOX1_CFG_REGS10)" base ad:0x4B61F9A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_10_VIRT_ALIAS_7_MAILBOX1_CFG_REGS10 (NAVSS0_MAILBOX1_10_VIRT_ALIAS_7_MAILBOX1_CFG_REGS10)" base ad:0x4B71F9A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_10_VIRT_ALIAS_8_MAILBOX1_CFG_REGS10 (NAVSS0_MAILBOX1_10_VIRT_ALIAS_8_MAILBOX1_CFG_REGS10)" base ad:0x4B81F9A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_10_VIRT_ALIAS_9_MAILBOX1_CFG_REGS10 (NAVSS0_MAILBOX1_10_VIRT_ALIAS_9_MAILBOX1_CFG_REGS10)" base ad:0x4B91F9A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_10_VIRT_ALIAS_10_MAILBOX1_CFG_REGS10 (NAVSS0_MAILBOX1_10_VIRT_ALIAS_10_MAILBOX1_CFG_REGS10)" base ad:0x4BA1F9A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_10_VIRT_ALIAS_11_MAILBOX1_CFG_REGS10 (NAVSS0_MAILBOX1_10_VIRT_ALIAS_11_MAILBOX1_CFG_REGS10)" base ad:0x4BB1F9A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_10_VIRT_ALIAS_12_MAILBOX1_CFG_REGS10 (NAVSS0_MAILBOX1_10_VIRT_ALIAS_12_MAILBOX1_CFG_REGS10)" base ad:0x4BC1F9A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_10_VIRT_ALIAS_13_MAILBOX1_CFG_REGS10 (NAVSS0_MAILBOX1_10_VIRT_ALIAS_13_MAILBOX1_CFG_REGS10)" base ad:0x4BD1F9A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_10_VIRT_ALIAS_14_MAILBOX1_CFG_REGS10 (NAVSS0_MAILBOX1_10_VIRT_ALIAS_14_MAILBOX1_CFG_REGS10)" base ad:0x4BE1F9A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_10_VIRT_ALIAS_15_MAILBOX1_CFG_REGS10 (NAVSS0_MAILBOX1_10_VIRT_ALIAS_15_MAILBOX1_CFG_REGS10)" base ad:0x4BF1F9A000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS10_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS10_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS10_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS10_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS10_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX1__CFG__REGS10_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree "NAVSS0_MAILBOX1_11" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_11_MAILBOX1_REGS11 (NAVSS0_MAILBOX1_11_MAILBOX1_REGS11)" base ad:0x31F9B000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "MAILBOX1__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MAILBOX1__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX1__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX1__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "MAILBOX1__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_11_ALIAS64K_MAILBOX1_CFG_REGS11 (NAVSS0_MAILBOX1_11_ALIAS64K_MAILBOX1_CFG_REGS11)" base ad:0x4A1F9B0000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "ALIAS64K_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "ALIAS64K_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "ALIAS64K_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "ALIAS64K_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree "NAVSS0_MAILBOX1_11_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_11_VIRT_ALIAS_0_MAILBOX1_CFG_REGS11 (NAVSS0_MAILBOX1_11_VIRT_ALIAS_0_MAILBOX1_CFG_REGS11)" base ad:0x4B01F9B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_0_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_0_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_11_VIRT_ALIAS_1_MAILBOX1_CFG_REGS11 (NAVSS0_MAILBOX1_11_VIRT_ALIAS_1_MAILBOX1_CFG_REGS11)" base ad:0x4B11F9B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_1_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_1_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_11_VIRT_ALIAS_2_MAILBOX1_CFG_REGS11 (NAVSS0_MAILBOX1_11_VIRT_ALIAS_2_MAILBOX1_CFG_REGS11)" base ad:0x4B21F9B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_2_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_2_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_11_VIRT_ALIAS_3_MAILBOX1_CFG_REGS11 (NAVSS0_MAILBOX1_11_VIRT_ALIAS_3_MAILBOX1_CFG_REGS11)" base ad:0x4B31F9B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_3_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_3_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_11_VIRT_ALIAS_4_MAILBOX1_CFG_REGS11 (NAVSS0_MAILBOX1_11_VIRT_ALIAS_4_MAILBOX1_CFG_REGS11)" base ad:0x4B41F9B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_4_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_4_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_11_VIRT_ALIAS_5_MAILBOX1_CFG_REGS11 (NAVSS0_MAILBOX1_11_VIRT_ALIAS_5_MAILBOX1_CFG_REGS11)" base ad:0x4B51F9B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_5_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_5_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_11_VIRT_ALIAS_6_MAILBOX1_CFG_REGS11 (NAVSS0_MAILBOX1_11_VIRT_ALIAS_6_MAILBOX1_CFG_REGS11)" base ad:0x4B61F9B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_6_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_6_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_11_VIRT_ALIAS_7_MAILBOX1_CFG_REGS11 (NAVSS0_MAILBOX1_11_VIRT_ALIAS_7_MAILBOX1_CFG_REGS11)" base ad:0x4B71F9B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_7_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_7_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_11_VIRT_ALIAS_8_MAILBOX1_CFG_REGS11 (NAVSS0_MAILBOX1_11_VIRT_ALIAS_8_MAILBOX1_CFG_REGS11)" base ad:0x4B81F9B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_8_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_8_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_11_VIRT_ALIAS_9_MAILBOX1_CFG_REGS11 (NAVSS0_MAILBOX1_11_VIRT_ALIAS_9_MAILBOX1_CFG_REGS11)" base ad:0x4B91F9B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_9_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_9_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_11_VIRT_ALIAS_10_MAILBOX1_CFG_REGS11 (NAVSS0_MAILBOX1_11_VIRT_ALIAS_10_MAILBOX1_CFG_REGS11)" base ad:0x4BA1F9B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_10_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_10_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_11_VIRT_ALIAS_11_MAILBOX1_CFG_REGS11 (NAVSS0_MAILBOX1_11_VIRT_ALIAS_11_MAILBOX1_CFG_REGS11)" base ad:0x4BB1F9B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_11_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_11_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_11_VIRT_ALIAS_12_MAILBOX1_CFG_REGS11 (NAVSS0_MAILBOX1_11_VIRT_ALIAS_12_MAILBOX1_CFG_REGS11)" base ad:0x4BC1F9B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_12_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_12_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_11_VIRT_ALIAS_13_MAILBOX1_CFG_REGS11 (NAVSS0_MAILBOX1_11_VIRT_ALIAS_13_MAILBOX1_CFG_REGS11)" base ad:0x4BD1F9B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_13_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_13_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_11_VIRT_ALIAS_14_MAILBOX1_CFG_REGS11 (NAVSS0_MAILBOX1_11_VIRT_ALIAS_14_MAILBOX1_CFG_REGS11)" base ad:0x4BE1F9B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_14_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_14_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MAILBOX1_11_VIRT_ALIAS_15_MAILBOX1_CFG_REGS11 (NAVSS0_MAILBOX1_11_VIRT_ALIAS_15_MAILBOX1_CFG_REGS11)" base ad:0x4BF1F9B000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS11_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS11_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS11_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS11_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS11_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" newline bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" rgroup.long 0x100++0xF line.long 0x0 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" newline bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" newline bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" newline bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" newline bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" newline bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" newline bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "VIRT_ALIAS_15_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "VIRT_ALIAS_15_MAILBOX1__CFG__REGS11_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end endif tree.end tree.end tree.end tree "NAVSS0_MCRC_0" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MCRC_0_MCRC (NAVSS0_MCRC_0_MCRC)" base ad:0x31F70000 rgroup.long 0x0++0x3 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL0,CRC Global Control Register 0" bitfld.long 0x0 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" rgroup.long 0x8++0x3 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL1,CRC Global Control Register 1" bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode. 1 = MCRC is in power down mode." "0: MCRC is not in power down mode,1: MCRC is in power down mode" rgroup.long 0x10++0x3 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1. The seed value can be planted in PSA Signature Register during data capture mode by writing a seed.." bitfld.long 0x0 24.--25. "CH4_MODE,Channel 4 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 16.--17. "CH3_MODE,Channel 3 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable" newline bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" rgroup.long 0x18++0x3 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_CRC_INTS,CRC Interrupt Enable Set Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENS_,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENS_,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENS_,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" rgroup.long 0x20++0x3 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_CRC_INTR,CRC Interrupt Enable Reset Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENR_,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENR_,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENR_,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" rgroup.long 0x28++0x3 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_CRC_STATUS,CRC Interrupt Status Register" bitfld.long 0x0 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." rgroup.long 0x30++0x3 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_CRC_INT_OFFSET_REG,CRC Interrupt Offset" hexmask.long.byte 0x0 0.--7. 1. "CRC,Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register automatically clears the respective interrupt flag." rgroup.long 0x38++0x3 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_CRC_BUSY,CRC Busy Register" bitfld.long 0x0 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" rgroup.long 0x40++0x7 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x48++0x3 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG1,CRC Current Sector Register 1" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x4C++0x7 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x60++0xF line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL1,Channel 1 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG1,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register." line.long 0x4 "MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH1,Channel 1 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register." line.long 0x8 "MCRC0__S_CFG__MCRC64_REGS_CRC_REGL1,Channel 1 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC1,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register." line.long 0xC "MCRC0__S_CFG__MCRC64_REGS_CRC_REGH1,Channel 1 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC1_47_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] register." rgroup.long 0x70++0xF line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG1,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register." line.long 0x4 "MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register." line.long 0x8 "MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL1,Channel 1 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA1,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH1,Channel 1 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA1_47_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x80++0x7 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x88++0x3 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG2,CRC Current Sector Register 2" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x8C++0x7 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xA0++0xF line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL2,Channel 2 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG2,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register." line.long 0x4 "MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH2,Channel 2 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register." line.long 0x8 "MCRC0__S_CFG__MCRC64_REGS_CRC_REGL2,Channel 2 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC2,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register." line.long 0xC "MCRC0__S_CFG__MCRC64_REGS_CRC_REGH2,Channel 2 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register." rgroup.long 0xB0++0xF line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG2,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL2,Channel 2 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA2,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH2,Channel 2 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0xC0++0x7 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0xC8++0x3 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG3,CRC Current Sector Register 3" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0xCC++0x7 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xE0++0xF line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL3,Channel 3 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG3,Channel 3 PSA Signature Low Register. This register contains the value stored at PSASIG3[31:0] register." line.long 0x4 "MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH3,Channel 3 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG3_63_32,Channel 3 PSA Signature High Register. This register contains the value stored at PSASIG3[63:32] register." line.long 0x8 "MCRC0__S_CFG__MCRC64_REGS_CRC_REGL3,Channel 3 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC3,Channel 3 CRC Value Low Register. This register contains the current known good signature value stored at CRC3[31:0] register." line.long 0xC "MCRC0__S_CFG__MCRC64_REGS_CRC_REGH3,Channel 3 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC3_63_32,Channel 3 CRC Value High Register. This register contains the current known good signature value stored at CRC3[63:32] register." rgroup.long 0xF0++0xF line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG3,Channel 3 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG3[31:0] register." line.long 0x4 "MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG3_63_32,Channel 3 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG3[63:32] register." line.long 0x8 "MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL3,Channel 3 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA3,Channel 3 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH3,Channel 3 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA3_63_32,Channel 3 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x100++0x7 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x108++0x3 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG4,CRC Current Sector Register 4" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number is logged into current sector ID.." rgroup.long 0x10C++0x7 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x120++0xF line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL4,Channel 4 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register." line.long 0x4 "MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH4,Channel 4 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG4_63_32,This register contains the value stored at PSASIG4[63:32] register." line.long 0x8 "MCRC0__S_CFG__MCRC64_REGS_CRC_REGL4,Channel 4 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC4,Channel 4 CRC Value Low Register." line.long 0xC "MCRC0__S_CFG__MCRC64_REGS_CRC_REGH4,Channel 4 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC4_63_32,Channel 4 CRC Value High Register." rgroup.long 0x130++0xF line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG4,Channel 4 PSA Sector Signature Low Register." line.long 0x4 "MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG4_63_32,Channel 4 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG4[63:32] register." line.long 0x8 "MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL4,Channel 4 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA4,Channel 4 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH4,Channel 4 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA4_63_32,Channel 4 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x140++0x3 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_MCRC_BUS_SEL,Data bus tracing selection" bitfld.long 0x0 2. "MEN,Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x0 1. "DTC_MEN,Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.." newline bitfld.long 0x0 0. "ITC_MEN,Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses." "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled Please.." rgroup.long 0x200++0x3 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG1_CPY,Region for Channel 1 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG1_CPY0,This register is a 128 byte block copy of the PSASIG1 register for DMA destination it is write only the result can be found in the PSASIG1 register." rgroup.long 0x280++0x3 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG2_CPY,Region for Channel 2 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG2_CPY0,This register is a 128 byte block copy of the PSASIG2 register for DMA destination it is write only the result can be found in the PSASIG2 register." rgroup.long 0x300++0x3 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG3_CPY,Region for Channel 3 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG3_CPY0,This register is a 128 byte block copy of the PSASIG3 register for DMA destination it is write only the result can be found in the PSASIG3 register." rgroup.long 0x380++0x3 line.long 0x0 "MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG4_CPY,Region for Channel 4 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG4_CPY0,This register is a 128 byte block copy of the PSASIG4 register for DMA destination it is write only the result can be found in the PSASIG4 register." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MCRC_0_ALIAS64K_MCRC0_S_CFG_MCRC64 (NAVSS0_MCRC_0_ALIAS64K_MCRC0_S_CFG_MCRC64)" base ad:0x4A1F700000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL0,CRC Global Control Register 0" bitfld.long 0x0 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" rgroup.long 0x8++0x3 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL1,CRC Global Control Register 1" bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode. 1 = MCRC is in power down mode." "0: MCRC is not in power down mode,1: MCRC is in power down mode" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1. The seed value can be planted in PSA Signature Register during data capture mode by writing a.." bitfld.long 0x0 24.--25. "CH4_MODE,Channel 4 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 16.--17. "CH3_MODE,Channel 3 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable" newline bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" rgroup.long 0x18++0x3 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_INTS,CRC Interrupt Enable Set Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENS_,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENS_,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENS_,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" rgroup.long 0x20++0x3 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_INTR,CRC Interrupt Enable Reset Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENR_,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENR_,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENR_,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" rgroup.long 0x28++0x3 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_STATUS,CRC Interrupt Status Register" bitfld.long 0x0 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." rgroup.long 0x30++0x3 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_INT_OFFSET_REG,CRC Interrupt Offset" hexmask.long.byte 0x0 0.--7. 1. "CRC,Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register automatically clears the respective interrupt flag." rgroup.long 0x38++0x3 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_BUSY,CRC Busy Register" bitfld.long 0x0 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" rgroup.long 0x40++0x7 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x48++0x3 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG1,CRC Current Sector Register 1" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x4C++0x7 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x60++0xF line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL1,Channel 1 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG1,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register." line.long 0x4 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH1,Channel 1 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register." line.long 0x8 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL1,Channel 1 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC1,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register." line.long 0xC "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH1,Channel 1 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC1_47_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] register." rgroup.long 0x70++0xF line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG1,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register." line.long 0x4 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register." line.long 0x8 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL1,Channel 1 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA1,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH1,Channel 1 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA1_47_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x80++0x7 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x88++0x3 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG2,CRC Current Sector Register 2" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x8C++0x7 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xA0++0xF line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL2,Channel 2 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG2,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register." line.long 0x4 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH2,Channel 2 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register." line.long 0x8 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL2,Channel 2 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC2,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register." line.long 0xC "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH2,Channel 2 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register." rgroup.long 0xB0++0xF line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG2,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL2,Channel 2 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA2,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH2,Channel 2 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0xC0++0x7 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0xC8++0x3 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG3,CRC Current Sector Register 3" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0xCC++0x7 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xE0++0xF line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL3,Channel 3 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG3,Channel 3 PSA Signature Low Register. This register contains the value stored at PSASIG3[31:0] register." line.long 0x4 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH3,Channel 3 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG3_63_32,Channel 3 PSA Signature High Register. This register contains the value stored at PSASIG3[63:32] register." line.long 0x8 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL3,Channel 3 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC3,Channel 3 CRC Value Low Register. This register contains the current known good signature value stored at CRC3[31:0] register." line.long 0xC "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH3,Channel 3 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC3_63_32,Channel 3 CRC Value High Register. This register contains the current known good signature value stored at CRC3[63:32] register." rgroup.long 0xF0++0xF line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG3,Channel 3 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG3[31:0] register." line.long 0x4 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG3_63_32,Channel 3 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG3[63:32] register." line.long 0x8 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL3,Channel 3 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA3,Channel 3 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH3,Channel 3 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA3_63_32,Channel 3 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x100++0x7 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x108++0x3 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG4,CRC Current Sector Register 4" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number is logged into current sector ID.." rgroup.long 0x10C++0x7 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x120++0xF line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL4,Channel 4 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register." line.long 0x4 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH4,Channel 4 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG4_63_32,This register contains the value stored at PSASIG4[63:32] register." line.long 0x8 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL4,Channel 4 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC4,Channel 4 CRC Value Low Register." line.long 0xC "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH4,Channel 4 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC4_63_32,Channel 4 CRC Value High Register." rgroup.long 0x130++0xF line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG4,Channel 4 PSA Sector Signature Low Register." line.long 0x4 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG4_63_32,Channel 4 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG4[63:32] register." line.long 0x8 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL4,Channel 4 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA4,Channel 4 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH4,Channel 4 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA4_63_32,Channel 4 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_MCRC_BUS_SEL,Data bus tracing selection" bitfld.long 0x0 2. "MEN,Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x0 1. "DTC_MEN,Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.." newline bitfld.long 0x0 0. "ITC_MEN,Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses." "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled Please.." rgroup.long 0x200++0x3 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG1_CPY,Region for Channel 1 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG1_CPY0,This register is a 128 byte block copy of the PSASIG1 register for DMA destination it is write only the result can be found in the PSASIG1 register." rgroup.long 0x280++0x3 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG2_CPY,Region for Channel 2 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG2_CPY0,This register is a 128 byte block copy of the PSASIG2 register for DMA destination it is write only the result can be found in the PSASIG2 register." rgroup.long 0x300++0x3 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG3_CPY,Region for Channel 3 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG3_CPY0,This register is a 128 byte block copy of the PSASIG3 register for DMA destination it is write only the result can be found in the PSASIG3 register." rgroup.long 0x380++0x3 line.long 0x0 "ALIAS64K_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG4_CPY,Region for Channel 4 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG4_CPY0,This register is a 128 byte block copy of the PSASIG4 register for DMA destination it is write only the result can be found in the PSASIG4 register." tree.end endif tree "NAVSS0_MCRC_0_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MCRC_0_VIRT_ALIAS_0_MCRC0_S_CFG_MCRC64 (NAVSS0_MCRC_0_VIRT_ALIAS_0_MCRC0_S_CFG_MCRC64)" base ad:0x4B01F70000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL0,CRC Global Control Register 0" bitfld.long 0x0 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL1,CRC Global Control Register 1" bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode. 1 = MCRC is in power down mode." "0: MCRC is not in power down mode,1: MCRC is in power down mode" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1. The seed value can be planted in PSA Signature Register during data capture mode by.." bitfld.long 0x0 24.--25. "CH4_MODE,Channel 4 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 16.--17. "CH3_MODE,Channel 3 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable" newline bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_INTS,CRC Interrupt Enable Set Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENS_,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENS_,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENS_,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_INTR,CRC Interrupt Enable Reset Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENR_,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENR_,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENR_,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" rgroup.long 0x28++0x3 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_STATUS,CRC Interrupt Status Register" bitfld.long 0x0 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_INT_OFFSET_REG,CRC Interrupt Offset" hexmask.long.byte 0x0 0.--7. 1. "CRC,Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register automatically clears the respective interrupt flag." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_BUSY,CRC Busy Register" bitfld.long 0x0 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x48++0x3 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG1,CRC Current Sector Register 1" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x4C++0x7 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x60++0xF line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL1,Channel 1 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG1,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH1,Channel 1 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL1,Channel 1 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC1,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register." line.long 0xC "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH1,Channel 1 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC1_47_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] register." rgroup.long 0x70++0xF line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG1,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL1,Channel 1 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA1,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH1,Channel 1 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA1_47_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG2,CRC Current Sector Register 2" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x8C++0x7 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xA0++0xF line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL2,Channel 2 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG2,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH2,Channel 2 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL2,Channel 2 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC2,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register." line.long 0xC "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH2,Channel 2 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register." rgroup.long 0xB0++0xF line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG2,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL2,Channel 2 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA2,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH2,Channel 2 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0xC8++0x3 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG3,CRC Current Sector Register 3" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0xCC++0x7 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xE0++0xF line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL3,Channel 3 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG3,Channel 3 PSA Signature Low Register. This register contains the value stored at PSASIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH3,Channel 3 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG3_63_32,Channel 3 PSA Signature High Register. This register contains the value stored at PSASIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL3,Channel 3 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC3,Channel 3 CRC Value Low Register. This register contains the current known good signature value stored at CRC3[31:0] register." line.long 0xC "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH3,Channel 3 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC3_63_32,Channel 3 CRC Value High Register. This register contains the current known good signature value stored at CRC3[63:32] register." rgroup.long 0xF0++0xF line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG3,Channel 3 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG3_63_32,Channel 3 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL3,Channel 3 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA3,Channel 3 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH3,Channel 3 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA3_63_32,Channel 3 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x100++0x7 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x108++0x3 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG4,CRC Current Sector Register 4" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number is logged into current sector ID.." rgroup.long 0x10C++0x7 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x120++0xF line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL4,Channel 4 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register." line.long 0x4 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH4,Channel 4 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG4_63_32,This register contains the value stored at PSASIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL4,Channel 4 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC4,Channel 4 CRC Value Low Register." line.long 0xC "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH4,Channel 4 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC4_63_32,Channel 4 CRC Value High Register." rgroup.long 0x130++0xF line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG4,Channel 4 PSA Sector Signature Low Register." line.long 0x4 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG4_63_32,Channel 4 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL4,Channel 4 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA4,Channel 4 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH4,Channel 4 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA4_63_32,Channel 4 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_MCRC_BUS_SEL,Data bus tracing selection" bitfld.long 0x0 2. "MEN,Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x0 1. "DTC_MEN,Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.." newline bitfld.long 0x0 0. "ITC_MEN,Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses." "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled Please.." rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG1_CPY,Region for Channel 1 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG1_CPY0,This register is a 128 byte block copy of the PSASIG1 register for DMA destination it is write only the result can be found in the PSASIG1 register." rgroup.long 0x280++0x3 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG2_CPY,Region for Channel 2 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG2_CPY0,This register is a 128 byte block copy of the PSASIG2 register for DMA destination it is write only the result can be found in the PSASIG2 register." rgroup.long 0x300++0x3 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG3_CPY,Region for Channel 3 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG3_CPY0,This register is a 128 byte block copy of the PSASIG3 register for DMA destination it is write only the result can be found in the PSASIG3 register." rgroup.long 0x380++0x3 line.long 0x0 "VIRT_ALIAS_0_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG4_CPY,Region for Channel 4 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG4_CPY0,This register is a 128 byte block copy of the PSASIG4 register for DMA destination it is write only the result can be found in the PSASIG4 register." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MCRC_0_VIRT_ALIAS_1_MCRC0_S_CFG_MCRC64 (NAVSS0_MCRC_0_VIRT_ALIAS_1_MCRC0_S_CFG_MCRC64)" base ad:0x4B11F70000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL0,CRC Global Control Register 0" bitfld.long 0x0 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL1,CRC Global Control Register 1" bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode. 1 = MCRC is in power down mode." "0: MCRC is not in power down mode,1: MCRC is in power down mode" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1. The seed value can be planted in PSA Signature Register during data capture mode by.." bitfld.long 0x0 24.--25. "CH4_MODE,Channel 4 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 16.--17. "CH3_MODE,Channel 3 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable" newline bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_INTS,CRC Interrupt Enable Set Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENS_,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENS_,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENS_,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_INTR,CRC Interrupt Enable Reset Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENR_,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENR_,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENR_,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" rgroup.long 0x28++0x3 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_STATUS,CRC Interrupt Status Register" bitfld.long 0x0 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_INT_OFFSET_REG,CRC Interrupt Offset" hexmask.long.byte 0x0 0.--7. 1. "CRC,Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register automatically clears the respective interrupt flag." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_BUSY,CRC Busy Register" bitfld.long 0x0 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x48++0x3 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG1,CRC Current Sector Register 1" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x4C++0x7 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x60++0xF line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL1,Channel 1 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG1,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH1,Channel 1 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL1,Channel 1 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC1,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register." line.long 0xC "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH1,Channel 1 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC1_47_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] register." rgroup.long 0x70++0xF line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG1,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL1,Channel 1 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA1,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH1,Channel 1 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA1_47_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG2,CRC Current Sector Register 2" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x8C++0x7 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xA0++0xF line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL2,Channel 2 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG2,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH2,Channel 2 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL2,Channel 2 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC2,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register." line.long 0xC "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH2,Channel 2 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register." rgroup.long 0xB0++0xF line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG2,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL2,Channel 2 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA2,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH2,Channel 2 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0xC8++0x3 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG3,CRC Current Sector Register 3" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0xCC++0x7 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xE0++0xF line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL3,Channel 3 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG3,Channel 3 PSA Signature Low Register. This register contains the value stored at PSASIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH3,Channel 3 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG3_63_32,Channel 3 PSA Signature High Register. This register contains the value stored at PSASIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL3,Channel 3 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC3,Channel 3 CRC Value Low Register. This register contains the current known good signature value stored at CRC3[31:0] register." line.long 0xC "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH3,Channel 3 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC3_63_32,Channel 3 CRC Value High Register. This register contains the current known good signature value stored at CRC3[63:32] register." rgroup.long 0xF0++0xF line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG3,Channel 3 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG3_63_32,Channel 3 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL3,Channel 3 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA3,Channel 3 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH3,Channel 3 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA3_63_32,Channel 3 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x100++0x7 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x108++0x3 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG4,CRC Current Sector Register 4" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number is logged into current sector ID.." rgroup.long 0x10C++0x7 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x120++0xF line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL4,Channel 4 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register." line.long 0x4 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH4,Channel 4 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG4_63_32,This register contains the value stored at PSASIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL4,Channel 4 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC4,Channel 4 CRC Value Low Register." line.long 0xC "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH4,Channel 4 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC4_63_32,Channel 4 CRC Value High Register." rgroup.long 0x130++0xF line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG4,Channel 4 PSA Sector Signature Low Register." line.long 0x4 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG4_63_32,Channel 4 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL4,Channel 4 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA4,Channel 4 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH4,Channel 4 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA4_63_32,Channel 4 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_MCRC_BUS_SEL,Data bus tracing selection" bitfld.long 0x0 2. "MEN,Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x0 1. "DTC_MEN,Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.." newline bitfld.long 0x0 0. "ITC_MEN,Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses." "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled Please.." rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG1_CPY,Region for Channel 1 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG1_CPY0,This register is a 128 byte block copy of the PSASIG1 register for DMA destination it is write only the result can be found in the PSASIG1 register." rgroup.long 0x280++0x3 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG2_CPY,Region for Channel 2 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG2_CPY0,This register is a 128 byte block copy of the PSASIG2 register for DMA destination it is write only the result can be found in the PSASIG2 register." rgroup.long 0x300++0x3 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG3_CPY,Region for Channel 3 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG3_CPY0,This register is a 128 byte block copy of the PSASIG3 register for DMA destination it is write only the result can be found in the PSASIG3 register." rgroup.long 0x380++0x3 line.long 0x0 "VIRT_ALIAS_1_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG4_CPY,Region for Channel 4 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG4_CPY0,This register is a 128 byte block copy of the PSASIG4 register for DMA destination it is write only the result can be found in the PSASIG4 register." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MCRC_0_VIRT_ALIAS_2_MCRC0_S_CFG_MCRC64 (NAVSS0_MCRC_0_VIRT_ALIAS_2_MCRC0_S_CFG_MCRC64)" base ad:0x4B21F70000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL0,CRC Global Control Register 0" bitfld.long 0x0 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL1,CRC Global Control Register 1" bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode. 1 = MCRC is in power down mode." "0: MCRC is not in power down mode,1: MCRC is in power down mode" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1. The seed value can be planted in PSA Signature Register during data capture mode by.." bitfld.long 0x0 24.--25. "CH4_MODE,Channel 4 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 16.--17. "CH3_MODE,Channel 3 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable" newline bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_INTS,CRC Interrupt Enable Set Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENS_,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENS_,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENS_,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_INTR,CRC Interrupt Enable Reset Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENR_,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENR_,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENR_,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" rgroup.long 0x28++0x3 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_STATUS,CRC Interrupt Status Register" bitfld.long 0x0 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_INT_OFFSET_REG,CRC Interrupt Offset" hexmask.long.byte 0x0 0.--7. 1. "CRC,Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register automatically clears the respective interrupt flag." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_BUSY,CRC Busy Register" bitfld.long 0x0 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x48++0x3 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG1,CRC Current Sector Register 1" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x4C++0x7 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x60++0xF line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL1,Channel 1 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG1,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH1,Channel 1 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL1,Channel 1 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC1,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register." line.long 0xC "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH1,Channel 1 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC1_47_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] register." rgroup.long 0x70++0xF line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG1,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL1,Channel 1 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA1,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH1,Channel 1 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA1_47_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG2,CRC Current Sector Register 2" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x8C++0x7 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xA0++0xF line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL2,Channel 2 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG2,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH2,Channel 2 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL2,Channel 2 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC2,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register." line.long 0xC "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH2,Channel 2 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register." rgroup.long 0xB0++0xF line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG2,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL2,Channel 2 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA2,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH2,Channel 2 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0xC8++0x3 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG3,CRC Current Sector Register 3" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0xCC++0x7 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xE0++0xF line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL3,Channel 3 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG3,Channel 3 PSA Signature Low Register. This register contains the value stored at PSASIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH3,Channel 3 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG3_63_32,Channel 3 PSA Signature High Register. This register contains the value stored at PSASIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL3,Channel 3 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC3,Channel 3 CRC Value Low Register. This register contains the current known good signature value stored at CRC3[31:0] register." line.long 0xC "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH3,Channel 3 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC3_63_32,Channel 3 CRC Value High Register. This register contains the current known good signature value stored at CRC3[63:32] register." rgroup.long 0xF0++0xF line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG3,Channel 3 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG3_63_32,Channel 3 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL3,Channel 3 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA3,Channel 3 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH3,Channel 3 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA3_63_32,Channel 3 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x100++0x7 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x108++0x3 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG4,CRC Current Sector Register 4" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number is logged into current sector ID.." rgroup.long 0x10C++0x7 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x120++0xF line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL4,Channel 4 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register." line.long 0x4 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH4,Channel 4 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG4_63_32,This register contains the value stored at PSASIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL4,Channel 4 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC4,Channel 4 CRC Value Low Register." line.long 0xC "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH4,Channel 4 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC4_63_32,Channel 4 CRC Value High Register." rgroup.long 0x130++0xF line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG4,Channel 4 PSA Sector Signature Low Register." line.long 0x4 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG4_63_32,Channel 4 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL4,Channel 4 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA4,Channel 4 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH4,Channel 4 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA4_63_32,Channel 4 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_MCRC_BUS_SEL,Data bus tracing selection" bitfld.long 0x0 2. "MEN,Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x0 1. "DTC_MEN,Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.." newline bitfld.long 0x0 0. "ITC_MEN,Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses." "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled Please.." rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG1_CPY,Region for Channel 1 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG1_CPY0,This register is a 128 byte block copy of the PSASIG1 register for DMA destination it is write only the result can be found in the PSASIG1 register." rgroup.long 0x280++0x3 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG2_CPY,Region for Channel 2 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG2_CPY0,This register is a 128 byte block copy of the PSASIG2 register for DMA destination it is write only the result can be found in the PSASIG2 register." rgroup.long 0x300++0x3 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG3_CPY,Region for Channel 3 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG3_CPY0,This register is a 128 byte block copy of the PSASIG3 register for DMA destination it is write only the result can be found in the PSASIG3 register." rgroup.long 0x380++0x3 line.long 0x0 "VIRT_ALIAS_2_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG4_CPY,Region for Channel 4 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG4_CPY0,This register is a 128 byte block copy of the PSASIG4 register for DMA destination it is write only the result can be found in the PSASIG4 register." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MCRC_0_VIRT_ALIAS_3_MCRC0_S_CFG_MCRC64 (NAVSS0_MCRC_0_VIRT_ALIAS_3_MCRC0_S_CFG_MCRC64)" base ad:0x4B31F70000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL0,CRC Global Control Register 0" bitfld.long 0x0 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL1,CRC Global Control Register 1" bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode. 1 = MCRC is in power down mode." "0: MCRC is not in power down mode,1: MCRC is in power down mode" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1. The seed value can be planted in PSA Signature Register during data capture mode by.." bitfld.long 0x0 24.--25. "CH4_MODE,Channel 4 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 16.--17. "CH3_MODE,Channel 3 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable" newline bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_INTS,CRC Interrupt Enable Set Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENS_,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENS_,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENS_,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_INTR,CRC Interrupt Enable Reset Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENR_,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENR_,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENR_,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" rgroup.long 0x28++0x3 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_STATUS,CRC Interrupt Status Register" bitfld.long 0x0 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_INT_OFFSET_REG,CRC Interrupt Offset" hexmask.long.byte 0x0 0.--7. 1. "CRC,Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register automatically clears the respective interrupt flag." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_BUSY,CRC Busy Register" bitfld.long 0x0 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x48++0x3 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG1,CRC Current Sector Register 1" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x4C++0x7 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x60++0xF line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL1,Channel 1 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG1,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH1,Channel 1 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL1,Channel 1 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC1,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register." line.long 0xC "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH1,Channel 1 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC1_47_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] register." rgroup.long 0x70++0xF line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG1,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL1,Channel 1 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA1,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH1,Channel 1 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA1_47_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG2,CRC Current Sector Register 2" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x8C++0x7 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xA0++0xF line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL2,Channel 2 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG2,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH2,Channel 2 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL2,Channel 2 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC2,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register." line.long 0xC "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH2,Channel 2 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register." rgroup.long 0xB0++0xF line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG2,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL2,Channel 2 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA2,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH2,Channel 2 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0xC8++0x3 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG3,CRC Current Sector Register 3" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0xCC++0x7 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xE0++0xF line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL3,Channel 3 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG3,Channel 3 PSA Signature Low Register. This register contains the value stored at PSASIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH3,Channel 3 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG3_63_32,Channel 3 PSA Signature High Register. This register contains the value stored at PSASIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL3,Channel 3 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC3,Channel 3 CRC Value Low Register. This register contains the current known good signature value stored at CRC3[31:0] register." line.long 0xC "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH3,Channel 3 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC3_63_32,Channel 3 CRC Value High Register. This register contains the current known good signature value stored at CRC3[63:32] register." rgroup.long 0xF0++0xF line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG3,Channel 3 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG3_63_32,Channel 3 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL3,Channel 3 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA3,Channel 3 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH3,Channel 3 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA3_63_32,Channel 3 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x100++0x7 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x108++0x3 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG4,CRC Current Sector Register 4" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number is logged into current sector ID.." rgroup.long 0x10C++0x7 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x120++0xF line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL4,Channel 4 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register." line.long 0x4 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH4,Channel 4 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG4_63_32,This register contains the value stored at PSASIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL4,Channel 4 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC4,Channel 4 CRC Value Low Register." line.long 0xC "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH4,Channel 4 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC4_63_32,Channel 4 CRC Value High Register." rgroup.long 0x130++0xF line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG4,Channel 4 PSA Sector Signature Low Register." line.long 0x4 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG4_63_32,Channel 4 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL4,Channel 4 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA4,Channel 4 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH4,Channel 4 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA4_63_32,Channel 4 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_MCRC_BUS_SEL,Data bus tracing selection" bitfld.long 0x0 2. "MEN,Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x0 1. "DTC_MEN,Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.." newline bitfld.long 0x0 0. "ITC_MEN,Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses." "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled Please.." rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG1_CPY,Region for Channel 1 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG1_CPY0,This register is a 128 byte block copy of the PSASIG1 register for DMA destination it is write only the result can be found in the PSASIG1 register." rgroup.long 0x280++0x3 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG2_CPY,Region for Channel 2 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG2_CPY0,This register is a 128 byte block copy of the PSASIG2 register for DMA destination it is write only the result can be found in the PSASIG2 register." rgroup.long 0x300++0x3 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG3_CPY,Region for Channel 3 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG3_CPY0,This register is a 128 byte block copy of the PSASIG3 register for DMA destination it is write only the result can be found in the PSASIG3 register." rgroup.long 0x380++0x3 line.long 0x0 "VIRT_ALIAS_3_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG4_CPY,Region for Channel 4 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG4_CPY0,This register is a 128 byte block copy of the PSASIG4 register for DMA destination it is write only the result can be found in the PSASIG4 register." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MCRC_0_VIRT_ALIAS_4_MCRC0_S_CFG_MCRC64 (NAVSS0_MCRC_0_VIRT_ALIAS_4_MCRC0_S_CFG_MCRC64)" base ad:0x4B41F70000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL0,CRC Global Control Register 0" bitfld.long 0x0 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL1,CRC Global Control Register 1" bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode. 1 = MCRC is in power down mode." "0: MCRC is not in power down mode,1: MCRC is in power down mode" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1. The seed value can be planted in PSA Signature Register during data capture mode by.." bitfld.long 0x0 24.--25. "CH4_MODE,Channel 4 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 16.--17. "CH3_MODE,Channel 3 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable" newline bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_INTS,CRC Interrupt Enable Set Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENS_,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENS_,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENS_,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_INTR,CRC Interrupt Enable Reset Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENR_,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENR_,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENR_,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" rgroup.long 0x28++0x3 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_STATUS,CRC Interrupt Status Register" bitfld.long 0x0 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_INT_OFFSET_REG,CRC Interrupt Offset" hexmask.long.byte 0x0 0.--7. 1. "CRC,Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register automatically clears the respective interrupt flag." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_BUSY,CRC Busy Register" bitfld.long 0x0 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x48++0x3 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG1,CRC Current Sector Register 1" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x4C++0x7 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x60++0xF line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL1,Channel 1 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG1,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH1,Channel 1 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL1,Channel 1 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC1,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register." line.long 0xC "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH1,Channel 1 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC1_47_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] register." rgroup.long 0x70++0xF line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG1,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL1,Channel 1 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA1,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH1,Channel 1 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA1_47_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG2,CRC Current Sector Register 2" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x8C++0x7 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xA0++0xF line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL2,Channel 2 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG2,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH2,Channel 2 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL2,Channel 2 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC2,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register." line.long 0xC "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH2,Channel 2 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register." rgroup.long 0xB0++0xF line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG2,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL2,Channel 2 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA2,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH2,Channel 2 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0xC8++0x3 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG3,CRC Current Sector Register 3" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0xCC++0x7 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xE0++0xF line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL3,Channel 3 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG3,Channel 3 PSA Signature Low Register. This register contains the value stored at PSASIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH3,Channel 3 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG3_63_32,Channel 3 PSA Signature High Register. This register contains the value stored at PSASIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL3,Channel 3 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC3,Channel 3 CRC Value Low Register. This register contains the current known good signature value stored at CRC3[31:0] register." line.long 0xC "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH3,Channel 3 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC3_63_32,Channel 3 CRC Value High Register. This register contains the current known good signature value stored at CRC3[63:32] register." rgroup.long 0xF0++0xF line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG3,Channel 3 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG3_63_32,Channel 3 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL3,Channel 3 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA3,Channel 3 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH3,Channel 3 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA3_63_32,Channel 3 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x100++0x7 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x108++0x3 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG4,CRC Current Sector Register 4" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number is logged into current sector ID.." rgroup.long 0x10C++0x7 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x120++0xF line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL4,Channel 4 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register." line.long 0x4 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH4,Channel 4 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG4_63_32,This register contains the value stored at PSASIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL4,Channel 4 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC4,Channel 4 CRC Value Low Register." line.long 0xC "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH4,Channel 4 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC4_63_32,Channel 4 CRC Value High Register." rgroup.long 0x130++0xF line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG4,Channel 4 PSA Sector Signature Low Register." line.long 0x4 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG4_63_32,Channel 4 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL4,Channel 4 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA4,Channel 4 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH4,Channel 4 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA4_63_32,Channel 4 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_MCRC_BUS_SEL,Data bus tracing selection" bitfld.long 0x0 2. "MEN,Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x0 1. "DTC_MEN,Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.." newline bitfld.long 0x0 0. "ITC_MEN,Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses." "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled Please.." rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG1_CPY,Region for Channel 1 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG1_CPY0,This register is a 128 byte block copy of the PSASIG1 register for DMA destination it is write only the result can be found in the PSASIG1 register." rgroup.long 0x280++0x3 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG2_CPY,Region for Channel 2 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG2_CPY0,This register is a 128 byte block copy of the PSASIG2 register for DMA destination it is write only the result can be found in the PSASIG2 register." rgroup.long 0x300++0x3 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG3_CPY,Region for Channel 3 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG3_CPY0,This register is a 128 byte block copy of the PSASIG3 register for DMA destination it is write only the result can be found in the PSASIG3 register." rgroup.long 0x380++0x3 line.long 0x0 "VIRT_ALIAS_4_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG4_CPY,Region for Channel 4 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG4_CPY0,This register is a 128 byte block copy of the PSASIG4 register for DMA destination it is write only the result can be found in the PSASIG4 register." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MCRC_0_VIRT_ALIAS_5_MCRC0_S_CFG_MCRC64 (NAVSS0_MCRC_0_VIRT_ALIAS_5_MCRC0_S_CFG_MCRC64)" base ad:0x4B51F70000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL0,CRC Global Control Register 0" bitfld.long 0x0 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL1,CRC Global Control Register 1" bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode. 1 = MCRC is in power down mode." "0: MCRC is not in power down mode,1: MCRC is in power down mode" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1. The seed value can be planted in PSA Signature Register during data capture mode by.." bitfld.long 0x0 24.--25. "CH4_MODE,Channel 4 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 16.--17. "CH3_MODE,Channel 3 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable" newline bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_INTS,CRC Interrupt Enable Set Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENS_,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENS_,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENS_,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_INTR,CRC Interrupt Enable Reset Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENR_,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENR_,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENR_,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" rgroup.long 0x28++0x3 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_STATUS,CRC Interrupt Status Register" bitfld.long 0x0 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_INT_OFFSET_REG,CRC Interrupt Offset" hexmask.long.byte 0x0 0.--7. 1. "CRC,Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register automatically clears the respective interrupt flag." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_BUSY,CRC Busy Register" bitfld.long 0x0 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x48++0x3 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG1,CRC Current Sector Register 1" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x4C++0x7 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x60++0xF line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL1,Channel 1 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG1,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH1,Channel 1 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL1,Channel 1 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC1,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register." line.long 0xC "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH1,Channel 1 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC1_47_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] register." rgroup.long 0x70++0xF line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG1,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL1,Channel 1 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA1,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH1,Channel 1 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA1_47_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG2,CRC Current Sector Register 2" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x8C++0x7 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xA0++0xF line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL2,Channel 2 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG2,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH2,Channel 2 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL2,Channel 2 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC2,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register." line.long 0xC "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH2,Channel 2 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register." rgroup.long 0xB0++0xF line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG2,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL2,Channel 2 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA2,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH2,Channel 2 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0xC8++0x3 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG3,CRC Current Sector Register 3" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0xCC++0x7 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xE0++0xF line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL3,Channel 3 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG3,Channel 3 PSA Signature Low Register. This register contains the value stored at PSASIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH3,Channel 3 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG3_63_32,Channel 3 PSA Signature High Register. This register contains the value stored at PSASIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL3,Channel 3 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC3,Channel 3 CRC Value Low Register. This register contains the current known good signature value stored at CRC3[31:0] register." line.long 0xC "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH3,Channel 3 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC3_63_32,Channel 3 CRC Value High Register. This register contains the current known good signature value stored at CRC3[63:32] register." rgroup.long 0xF0++0xF line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG3,Channel 3 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG3_63_32,Channel 3 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL3,Channel 3 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA3,Channel 3 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH3,Channel 3 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA3_63_32,Channel 3 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x100++0x7 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x108++0x3 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG4,CRC Current Sector Register 4" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number is logged into current sector ID.." rgroup.long 0x10C++0x7 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x120++0xF line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL4,Channel 4 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register." line.long 0x4 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH4,Channel 4 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG4_63_32,This register contains the value stored at PSASIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL4,Channel 4 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC4,Channel 4 CRC Value Low Register." line.long 0xC "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH4,Channel 4 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC4_63_32,Channel 4 CRC Value High Register." rgroup.long 0x130++0xF line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG4,Channel 4 PSA Sector Signature Low Register." line.long 0x4 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG4_63_32,Channel 4 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL4,Channel 4 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA4,Channel 4 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH4,Channel 4 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA4_63_32,Channel 4 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_MCRC_BUS_SEL,Data bus tracing selection" bitfld.long 0x0 2. "MEN,Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x0 1. "DTC_MEN,Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.." newline bitfld.long 0x0 0. "ITC_MEN,Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses." "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled Please.." rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG1_CPY,Region for Channel 1 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG1_CPY0,This register is a 128 byte block copy of the PSASIG1 register for DMA destination it is write only the result can be found in the PSASIG1 register." rgroup.long 0x280++0x3 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG2_CPY,Region for Channel 2 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG2_CPY0,This register is a 128 byte block copy of the PSASIG2 register for DMA destination it is write only the result can be found in the PSASIG2 register." rgroup.long 0x300++0x3 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG3_CPY,Region for Channel 3 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG3_CPY0,This register is a 128 byte block copy of the PSASIG3 register for DMA destination it is write only the result can be found in the PSASIG3 register." rgroup.long 0x380++0x3 line.long 0x0 "VIRT_ALIAS_5_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG4_CPY,Region for Channel 4 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG4_CPY0,This register is a 128 byte block copy of the PSASIG4 register for DMA destination it is write only the result can be found in the PSASIG4 register." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MCRC_0_VIRT_ALIAS_6_MCRC0_S_CFG_MCRC64 (NAVSS0_MCRC_0_VIRT_ALIAS_6_MCRC0_S_CFG_MCRC64)" base ad:0x4B61F70000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL0,CRC Global Control Register 0" bitfld.long 0x0 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL1,CRC Global Control Register 1" bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode. 1 = MCRC is in power down mode." "0: MCRC is not in power down mode,1: MCRC is in power down mode" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1. The seed value can be planted in PSA Signature Register during data capture mode by.." bitfld.long 0x0 24.--25. "CH4_MODE,Channel 4 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 16.--17. "CH3_MODE,Channel 3 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable" newline bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_INTS,CRC Interrupt Enable Set Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENS_,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENS_,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENS_,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_INTR,CRC Interrupt Enable Reset Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENR_,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENR_,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENR_,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" rgroup.long 0x28++0x3 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_STATUS,CRC Interrupt Status Register" bitfld.long 0x0 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_INT_OFFSET_REG,CRC Interrupt Offset" hexmask.long.byte 0x0 0.--7. 1. "CRC,Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register automatically clears the respective interrupt flag." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_BUSY,CRC Busy Register" bitfld.long 0x0 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x48++0x3 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG1,CRC Current Sector Register 1" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x4C++0x7 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x60++0xF line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL1,Channel 1 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG1,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH1,Channel 1 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL1,Channel 1 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC1,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register." line.long 0xC "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH1,Channel 1 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC1_47_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] register." rgroup.long 0x70++0xF line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG1,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL1,Channel 1 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA1,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH1,Channel 1 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA1_47_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG2,CRC Current Sector Register 2" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x8C++0x7 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xA0++0xF line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL2,Channel 2 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG2,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH2,Channel 2 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL2,Channel 2 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC2,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register." line.long 0xC "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH2,Channel 2 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register." rgroup.long 0xB0++0xF line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG2,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL2,Channel 2 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA2,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH2,Channel 2 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0xC8++0x3 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG3,CRC Current Sector Register 3" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0xCC++0x7 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xE0++0xF line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL3,Channel 3 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG3,Channel 3 PSA Signature Low Register. This register contains the value stored at PSASIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH3,Channel 3 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG3_63_32,Channel 3 PSA Signature High Register. This register contains the value stored at PSASIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL3,Channel 3 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC3,Channel 3 CRC Value Low Register. This register contains the current known good signature value stored at CRC3[31:0] register." line.long 0xC "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH3,Channel 3 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC3_63_32,Channel 3 CRC Value High Register. This register contains the current known good signature value stored at CRC3[63:32] register." rgroup.long 0xF0++0xF line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG3,Channel 3 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG3_63_32,Channel 3 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL3,Channel 3 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA3,Channel 3 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH3,Channel 3 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA3_63_32,Channel 3 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x100++0x7 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x108++0x3 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG4,CRC Current Sector Register 4" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number is logged into current sector ID.." rgroup.long 0x10C++0x7 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x120++0xF line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL4,Channel 4 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register." line.long 0x4 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH4,Channel 4 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG4_63_32,This register contains the value stored at PSASIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL4,Channel 4 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC4,Channel 4 CRC Value Low Register." line.long 0xC "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH4,Channel 4 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC4_63_32,Channel 4 CRC Value High Register." rgroup.long 0x130++0xF line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG4,Channel 4 PSA Sector Signature Low Register." line.long 0x4 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG4_63_32,Channel 4 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL4,Channel 4 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA4,Channel 4 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH4,Channel 4 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA4_63_32,Channel 4 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_MCRC_BUS_SEL,Data bus tracing selection" bitfld.long 0x0 2. "MEN,Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x0 1. "DTC_MEN,Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.." newline bitfld.long 0x0 0. "ITC_MEN,Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses." "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled Please.." rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG1_CPY,Region for Channel 1 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG1_CPY0,This register is a 128 byte block copy of the PSASIG1 register for DMA destination it is write only the result can be found in the PSASIG1 register." rgroup.long 0x280++0x3 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG2_CPY,Region for Channel 2 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG2_CPY0,This register is a 128 byte block copy of the PSASIG2 register for DMA destination it is write only the result can be found in the PSASIG2 register." rgroup.long 0x300++0x3 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG3_CPY,Region for Channel 3 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG3_CPY0,This register is a 128 byte block copy of the PSASIG3 register for DMA destination it is write only the result can be found in the PSASIG3 register." rgroup.long 0x380++0x3 line.long 0x0 "VIRT_ALIAS_6_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG4_CPY,Region for Channel 4 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG4_CPY0,This register is a 128 byte block copy of the PSASIG4 register for DMA destination it is write only the result can be found in the PSASIG4 register." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MCRC_0_VIRT_ALIAS_7_MCRC0_S_CFG_MCRC64 (NAVSS0_MCRC_0_VIRT_ALIAS_7_MCRC0_S_CFG_MCRC64)" base ad:0x4B71F70000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL0,CRC Global Control Register 0" bitfld.long 0x0 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL1,CRC Global Control Register 1" bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode. 1 = MCRC is in power down mode." "0: MCRC is not in power down mode,1: MCRC is in power down mode" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1. The seed value can be planted in PSA Signature Register during data capture mode by.." bitfld.long 0x0 24.--25. "CH4_MODE,Channel 4 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 16.--17. "CH3_MODE,Channel 3 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable" newline bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_INTS,CRC Interrupt Enable Set Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENS_,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENS_,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENS_,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_INTR,CRC Interrupt Enable Reset Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENR_,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENR_,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENR_,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" rgroup.long 0x28++0x3 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_STATUS,CRC Interrupt Status Register" bitfld.long 0x0 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_INT_OFFSET_REG,CRC Interrupt Offset" hexmask.long.byte 0x0 0.--7. 1. "CRC,Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register automatically clears the respective interrupt flag." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_BUSY,CRC Busy Register" bitfld.long 0x0 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x48++0x3 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG1,CRC Current Sector Register 1" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x4C++0x7 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x60++0xF line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL1,Channel 1 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG1,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH1,Channel 1 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL1,Channel 1 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC1,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register." line.long 0xC "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH1,Channel 1 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC1_47_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] register." rgroup.long 0x70++0xF line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG1,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL1,Channel 1 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA1,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH1,Channel 1 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA1_47_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG2,CRC Current Sector Register 2" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x8C++0x7 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xA0++0xF line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL2,Channel 2 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG2,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH2,Channel 2 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL2,Channel 2 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC2,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register." line.long 0xC "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH2,Channel 2 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register." rgroup.long 0xB0++0xF line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG2,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL2,Channel 2 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA2,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH2,Channel 2 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0xC8++0x3 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG3,CRC Current Sector Register 3" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0xCC++0x7 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xE0++0xF line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL3,Channel 3 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG3,Channel 3 PSA Signature Low Register. This register contains the value stored at PSASIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH3,Channel 3 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG3_63_32,Channel 3 PSA Signature High Register. This register contains the value stored at PSASIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL3,Channel 3 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC3,Channel 3 CRC Value Low Register. This register contains the current known good signature value stored at CRC3[31:0] register." line.long 0xC "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH3,Channel 3 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC3_63_32,Channel 3 CRC Value High Register. This register contains the current known good signature value stored at CRC3[63:32] register." rgroup.long 0xF0++0xF line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG3,Channel 3 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG3_63_32,Channel 3 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL3,Channel 3 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA3,Channel 3 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH3,Channel 3 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA3_63_32,Channel 3 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x100++0x7 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x108++0x3 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG4,CRC Current Sector Register 4" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number is logged into current sector ID.." rgroup.long 0x10C++0x7 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x120++0xF line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL4,Channel 4 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register." line.long 0x4 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH4,Channel 4 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG4_63_32,This register contains the value stored at PSASIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL4,Channel 4 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC4,Channel 4 CRC Value Low Register." line.long 0xC "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH4,Channel 4 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC4_63_32,Channel 4 CRC Value High Register." rgroup.long 0x130++0xF line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG4,Channel 4 PSA Sector Signature Low Register." line.long 0x4 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG4_63_32,Channel 4 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL4,Channel 4 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA4,Channel 4 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH4,Channel 4 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA4_63_32,Channel 4 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_MCRC_BUS_SEL,Data bus tracing selection" bitfld.long 0x0 2. "MEN,Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x0 1. "DTC_MEN,Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.." newline bitfld.long 0x0 0. "ITC_MEN,Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses." "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled Please.." rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG1_CPY,Region for Channel 1 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG1_CPY0,This register is a 128 byte block copy of the PSASIG1 register for DMA destination it is write only the result can be found in the PSASIG1 register." rgroup.long 0x280++0x3 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG2_CPY,Region for Channel 2 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG2_CPY0,This register is a 128 byte block copy of the PSASIG2 register for DMA destination it is write only the result can be found in the PSASIG2 register." rgroup.long 0x300++0x3 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG3_CPY,Region for Channel 3 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG3_CPY0,This register is a 128 byte block copy of the PSASIG3 register for DMA destination it is write only the result can be found in the PSASIG3 register." rgroup.long 0x380++0x3 line.long 0x0 "VIRT_ALIAS_7_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG4_CPY,Region for Channel 4 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG4_CPY0,This register is a 128 byte block copy of the PSASIG4 register for DMA destination it is write only the result can be found in the PSASIG4 register." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MCRC_0_VIRT_ALIAS_8_MCRC0_S_CFG_MCRC64 (NAVSS0_MCRC_0_VIRT_ALIAS_8_MCRC0_S_CFG_MCRC64)" base ad:0x4B81F70000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL0,CRC Global Control Register 0" bitfld.long 0x0 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL1,CRC Global Control Register 1" bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode. 1 = MCRC is in power down mode." "0: MCRC is not in power down mode,1: MCRC is in power down mode" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1. The seed value can be planted in PSA Signature Register during data capture mode by.." bitfld.long 0x0 24.--25. "CH4_MODE,Channel 4 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 16.--17. "CH3_MODE,Channel 3 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable" newline bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_INTS,CRC Interrupt Enable Set Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENS_,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENS_,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENS_,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_INTR,CRC Interrupt Enable Reset Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENR_,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENR_,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENR_,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" rgroup.long 0x28++0x3 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_STATUS,CRC Interrupt Status Register" bitfld.long 0x0 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_INT_OFFSET_REG,CRC Interrupt Offset" hexmask.long.byte 0x0 0.--7. 1. "CRC,Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register automatically clears the respective interrupt flag." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_BUSY,CRC Busy Register" bitfld.long 0x0 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x48++0x3 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG1,CRC Current Sector Register 1" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x4C++0x7 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x60++0xF line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL1,Channel 1 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG1,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH1,Channel 1 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL1,Channel 1 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC1,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register." line.long 0xC "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH1,Channel 1 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC1_47_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] register." rgroup.long 0x70++0xF line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG1,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL1,Channel 1 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA1,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH1,Channel 1 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA1_47_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG2,CRC Current Sector Register 2" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x8C++0x7 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xA0++0xF line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL2,Channel 2 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG2,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH2,Channel 2 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL2,Channel 2 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC2,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register." line.long 0xC "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH2,Channel 2 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register." rgroup.long 0xB0++0xF line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG2,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL2,Channel 2 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA2,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH2,Channel 2 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0xC8++0x3 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG3,CRC Current Sector Register 3" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0xCC++0x7 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xE0++0xF line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL3,Channel 3 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG3,Channel 3 PSA Signature Low Register. This register contains the value stored at PSASIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH3,Channel 3 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG3_63_32,Channel 3 PSA Signature High Register. This register contains the value stored at PSASIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL3,Channel 3 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC3,Channel 3 CRC Value Low Register. This register contains the current known good signature value stored at CRC3[31:0] register." line.long 0xC "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH3,Channel 3 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC3_63_32,Channel 3 CRC Value High Register. This register contains the current known good signature value stored at CRC3[63:32] register." rgroup.long 0xF0++0xF line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG3,Channel 3 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG3_63_32,Channel 3 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL3,Channel 3 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA3,Channel 3 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH3,Channel 3 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA3_63_32,Channel 3 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x100++0x7 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x108++0x3 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG4,CRC Current Sector Register 4" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number is logged into current sector ID.." rgroup.long 0x10C++0x7 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x120++0xF line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL4,Channel 4 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register." line.long 0x4 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH4,Channel 4 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG4_63_32,This register contains the value stored at PSASIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL4,Channel 4 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC4,Channel 4 CRC Value Low Register." line.long 0xC "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH4,Channel 4 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC4_63_32,Channel 4 CRC Value High Register." rgroup.long 0x130++0xF line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG4,Channel 4 PSA Sector Signature Low Register." line.long 0x4 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG4_63_32,Channel 4 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL4,Channel 4 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA4,Channel 4 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH4,Channel 4 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA4_63_32,Channel 4 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_MCRC_BUS_SEL,Data bus tracing selection" bitfld.long 0x0 2. "MEN,Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x0 1. "DTC_MEN,Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.." newline bitfld.long 0x0 0. "ITC_MEN,Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses." "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled Please.." rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG1_CPY,Region for Channel 1 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG1_CPY0,This register is a 128 byte block copy of the PSASIG1 register for DMA destination it is write only the result can be found in the PSASIG1 register." rgroup.long 0x280++0x3 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG2_CPY,Region for Channel 2 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG2_CPY0,This register is a 128 byte block copy of the PSASIG2 register for DMA destination it is write only the result can be found in the PSASIG2 register." rgroup.long 0x300++0x3 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG3_CPY,Region for Channel 3 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG3_CPY0,This register is a 128 byte block copy of the PSASIG3 register for DMA destination it is write only the result can be found in the PSASIG3 register." rgroup.long 0x380++0x3 line.long 0x0 "VIRT_ALIAS_8_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG4_CPY,Region for Channel 4 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG4_CPY0,This register is a 128 byte block copy of the PSASIG4 register for DMA destination it is write only the result can be found in the PSASIG4 register." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MCRC_0_VIRT_ALIAS_9_MCRC0_S_CFG_MCRC64 (NAVSS0_MCRC_0_VIRT_ALIAS_9_MCRC0_S_CFG_MCRC64)" base ad:0x4B91F70000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL0,CRC Global Control Register 0" bitfld.long 0x0 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL1,CRC Global Control Register 1" bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode. 1 = MCRC is in power down mode." "0: MCRC is not in power down mode,1: MCRC is in power down mode" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1. The seed value can be planted in PSA Signature Register during data capture mode by.." bitfld.long 0x0 24.--25. "CH4_MODE,Channel 4 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 16.--17. "CH3_MODE,Channel 3 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable" newline bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_INTS,CRC Interrupt Enable Set Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENS_,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENS_,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENS_,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_INTR,CRC Interrupt Enable Reset Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENR_,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENR_,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENR_,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" rgroup.long 0x28++0x3 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_STATUS,CRC Interrupt Status Register" bitfld.long 0x0 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_INT_OFFSET_REG,CRC Interrupt Offset" hexmask.long.byte 0x0 0.--7. 1. "CRC,Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register automatically clears the respective interrupt flag." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_BUSY,CRC Busy Register" bitfld.long 0x0 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x48++0x3 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG1,CRC Current Sector Register 1" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x4C++0x7 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x60++0xF line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL1,Channel 1 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG1,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH1,Channel 1 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL1,Channel 1 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC1,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register." line.long 0xC "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH1,Channel 1 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC1_47_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] register." rgroup.long 0x70++0xF line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG1,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL1,Channel 1 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA1,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH1,Channel 1 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA1_47_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG2,CRC Current Sector Register 2" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x8C++0x7 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xA0++0xF line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL2,Channel 2 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG2,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH2,Channel 2 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL2,Channel 2 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC2,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register." line.long 0xC "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH2,Channel 2 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register." rgroup.long 0xB0++0xF line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG2,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL2,Channel 2 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA2,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH2,Channel 2 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0xC8++0x3 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG3,CRC Current Sector Register 3" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0xCC++0x7 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xE0++0xF line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL3,Channel 3 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG3,Channel 3 PSA Signature Low Register. This register contains the value stored at PSASIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH3,Channel 3 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG3_63_32,Channel 3 PSA Signature High Register. This register contains the value stored at PSASIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL3,Channel 3 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC3,Channel 3 CRC Value Low Register. This register contains the current known good signature value stored at CRC3[31:0] register." line.long 0xC "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH3,Channel 3 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC3_63_32,Channel 3 CRC Value High Register. This register contains the current known good signature value stored at CRC3[63:32] register." rgroup.long 0xF0++0xF line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG3,Channel 3 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG3_63_32,Channel 3 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL3,Channel 3 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA3,Channel 3 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH3,Channel 3 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA3_63_32,Channel 3 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x100++0x7 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x108++0x3 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG4,CRC Current Sector Register 4" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number is logged into current sector ID.." rgroup.long 0x10C++0x7 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x120++0xF line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL4,Channel 4 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register." line.long 0x4 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH4,Channel 4 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG4_63_32,This register contains the value stored at PSASIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL4,Channel 4 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC4,Channel 4 CRC Value Low Register." line.long 0xC "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH4,Channel 4 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC4_63_32,Channel 4 CRC Value High Register." rgroup.long 0x130++0xF line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG4,Channel 4 PSA Sector Signature Low Register." line.long 0x4 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG4_63_32,Channel 4 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL4,Channel 4 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA4,Channel 4 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH4,Channel 4 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA4_63_32,Channel 4 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_MCRC_BUS_SEL,Data bus tracing selection" bitfld.long 0x0 2. "MEN,Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x0 1. "DTC_MEN,Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.." newline bitfld.long 0x0 0. "ITC_MEN,Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses." "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled Please.." rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG1_CPY,Region for Channel 1 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG1_CPY0,This register is a 128 byte block copy of the PSASIG1 register for DMA destination it is write only the result can be found in the PSASIG1 register." rgroup.long 0x280++0x3 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG2_CPY,Region for Channel 2 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG2_CPY0,This register is a 128 byte block copy of the PSASIG2 register for DMA destination it is write only the result can be found in the PSASIG2 register." rgroup.long 0x300++0x3 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG3_CPY,Region for Channel 3 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG3_CPY0,This register is a 128 byte block copy of the PSASIG3 register for DMA destination it is write only the result can be found in the PSASIG3 register." rgroup.long 0x380++0x3 line.long 0x0 "VIRT_ALIAS_9_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG4_CPY,Region for Channel 4 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG4_CPY0,This register is a 128 byte block copy of the PSASIG4 register for DMA destination it is write only the result can be found in the PSASIG4 register." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MCRC_0_VIRT_ALIAS_10_MCRC0_S_CFG_MCRC64 (NAVSS0_MCRC_0_VIRT_ALIAS_10_MCRC0_S_CFG_MCRC64)" base ad:0x4BA1F70000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL0,CRC Global Control Register 0" bitfld.long 0x0 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL1,CRC Global Control Register 1" bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode. 1 = MCRC is in power down mode." "0: MCRC is not in power down mode,1: MCRC is in power down mode" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1. The seed value can be planted in PSA Signature Register during data capture mode by.." bitfld.long 0x0 24.--25. "CH4_MODE,Channel 4 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 16.--17. "CH3_MODE,Channel 3 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable" newline bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_INTS,CRC Interrupt Enable Set Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENS_,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENS_,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENS_,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_INTR,CRC Interrupt Enable Reset Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENR_,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENR_,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENR_,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" rgroup.long 0x28++0x3 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_STATUS,CRC Interrupt Status Register" bitfld.long 0x0 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_INT_OFFSET_REG,CRC Interrupt Offset" hexmask.long.byte 0x0 0.--7. 1. "CRC,Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register automatically clears the respective interrupt flag." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_BUSY,CRC Busy Register" bitfld.long 0x0 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x48++0x3 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG1,CRC Current Sector Register 1" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x4C++0x7 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x60++0xF line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL1,Channel 1 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG1,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH1,Channel 1 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL1,Channel 1 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC1,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register." line.long 0xC "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH1,Channel 1 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC1_47_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] register." rgroup.long 0x70++0xF line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG1,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL1,Channel 1 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA1,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH1,Channel 1 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA1_47_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG2,CRC Current Sector Register 2" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x8C++0x7 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xA0++0xF line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL2,Channel 2 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG2,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH2,Channel 2 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL2,Channel 2 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC2,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register." line.long 0xC "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH2,Channel 2 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register." rgroup.long 0xB0++0xF line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG2,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL2,Channel 2 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA2,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH2,Channel 2 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0xC8++0x3 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG3,CRC Current Sector Register 3" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0xCC++0x7 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xE0++0xF line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL3,Channel 3 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG3,Channel 3 PSA Signature Low Register. This register contains the value stored at PSASIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH3,Channel 3 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG3_63_32,Channel 3 PSA Signature High Register. This register contains the value stored at PSASIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL3,Channel 3 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC3,Channel 3 CRC Value Low Register. This register contains the current known good signature value stored at CRC3[31:0] register." line.long 0xC "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH3,Channel 3 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC3_63_32,Channel 3 CRC Value High Register. This register contains the current known good signature value stored at CRC3[63:32] register." rgroup.long 0xF0++0xF line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG3,Channel 3 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG3_63_32,Channel 3 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL3,Channel 3 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA3,Channel 3 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH3,Channel 3 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA3_63_32,Channel 3 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x100++0x7 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x108++0x3 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG4,CRC Current Sector Register 4" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number is logged into current sector ID.." rgroup.long 0x10C++0x7 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x120++0xF line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL4,Channel 4 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register." line.long 0x4 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH4,Channel 4 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG4_63_32,This register contains the value stored at PSASIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL4,Channel 4 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC4,Channel 4 CRC Value Low Register." line.long 0xC "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH4,Channel 4 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC4_63_32,Channel 4 CRC Value High Register." rgroup.long 0x130++0xF line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG4,Channel 4 PSA Sector Signature Low Register." line.long 0x4 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG4_63_32,Channel 4 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL4,Channel 4 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA4,Channel 4 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH4,Channel 4 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA4_63_32,Channel 4 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_MCRC_BUS_SEL,Data bus tracing selection" bitfld.long 0x0 2. "MEN,Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x0 1. "DTC_MEN,Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.." newline bitfld.long 0x0 0. "ITC_MEN,Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses." "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled Please.." rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG1_CPY,Region for Channel 1 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG1_CPY0,This register is a 128 byte block copy of the PSASIG1 register for DMA destination it is write only the result can be found in the PSASIG1 register." rgroup.long 0x280++0x3 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG2_CPY,Region for Channel 2 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG2_CPY0,This register is a 128 byte block copy of the PSASIG2 register for DMA destination it is write only the result can be found in the PSASIG2 register." rgroup.long 0x300++0x3 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG3_CPY,Region for Channel 3 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG3_CPY0,This register is a 128 byte block copy of the PSASIG3 register for DMA destination it is write only the result can be found in the PSASIG3 register." rgroup.long 0x380++0x3 line.long 0x0 "VIRT_ALIAS_10_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG4_CPY,Region for Channel 4 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG4_CPY0,This register is a 128 byte block copy of the PSASIG4 register for DMA destination it is write only the result can be found in the PSASIG4 register." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MCRC_0_VIRT_ALIAS_11_MCRC0_S_CFG_MCRC64 (NAVSS0_MCRC_0_VIRT_ALIAS_11_MCRC0_S_CFG_MCRC64)" base ad:0x4BB1F70000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL0,CRC Global Control Register 0" bitfld.long 0x0 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL1,CRC Global Control Register 1" bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode. 1 = MCRC is in power down mode." "0: MCRC is not in power down mode,1: MCRC is in power down mode" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1. The seed value can be planted in PSA Signature Register during data capture mode by.." bitfld.long 0x0 24.--25. "CH4_MODE,Channel 4 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 16.--17. "CH3_MODE,Channel 3 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable" newline bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_INTS,CRC Interrupt Enable Set Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENS_,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENS_,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENS_,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_INTR,CRC Interrupt Enable Reset Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENR_,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENR_,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENR_,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" rgroup.long 0x28++0x3 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_STATUS,CRC Interrupt Status Register" bitfld.long 0x0 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_INT_OFFSET_REG,CRC Interrupt Offset" hexmask.long.byte 0x0 0.--7. 1. "CRC,Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register automatically clears the respective interrupt flag." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_BUSY,CRC Busy Register" bitfld.long 0x0 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x48++0x3 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG1,CRC Current Sector Register 1" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x4C++0x7 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x60++0xF line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL1,Channel 1 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG1,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH1,Channel 1 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL1,Channel 1 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC1,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register." line.long 0xC "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH1,Channel 1 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC1_47_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] register." rgroup.long 0x70++0xF line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG1,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL1,Channel 1 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA1,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH1,Channel 1 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA1_47_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG2,CRC Current Sector Register 2" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x8C++0x7 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xA0++0xF line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL2,Channel 2 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG2,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH2,Channel 2 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL2,Channel 2 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC2,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register." line.long 0xC "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH2,Channel 2 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register." rgroup.long 0xB0++0xF line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG2,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL2,Channel 2 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA2,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH2,Channel 2 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0xC8++0x3 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG3,CRC Current Sector Register 3" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0xCC++0x7 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xE0++0xF line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL3,Channel 3 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG3,Channel 3 PSA Signature Low Register. This register contains the value stored at PSASIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH3,Channel 3 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG3_63_32,Channel 3 PSA Signature High Register. This register contains the value stored at PSASIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL3,Channel 3 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC3,Channel 3 CRC Value Low Register. This register contains the current known good signature value stored at CRC3[31:0] register." line.long 0xC "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH3,Channel 3 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC3_63_32,Channel 3 CRC Value High Register. This register contains the current known good signature value stored at CRC3[63:32] register." rgroup.long 0xF0++0xF line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG3,Channel 3 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG3_63_32,Channel 3 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL3,Channel 3 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA3,Channel 3 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH3,Channel 3 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA3_63_32,Channel 3 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x100++0x7 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x108++0x3 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG4,CRC Current Sector Register 4" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number is logged into current sector ID.." rgroup.long 0x10C++0x7 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x120++0xF line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL4,Channel 4 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register." line.long 0x4 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH4,Channel 4 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG4_63_32,This register contains the value stored at PSASIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL4,Channel 4 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC4,Channel 4 CRC Value Low Register." line.long 0xC "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH4,Channel 4 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC4_63_32,Channel 4 CRC Value High Register." rgroup.long 0x130++0xF line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG4,Channel 4 PSA Sector Signature Low Register." line.long 0x4 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG4_63_32,Channel 4 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL4,Channel 4 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA4,Channel 4 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH4,Channel 4 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA4_63_32,Channel 4 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_MCRC_BUS_SEL,Data bus tracing selection" bitfld.long 0x0 2. "MEN,Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x0 1. "DTC_MEN,Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.." newline bitfld.long 0x0 0. "ITC_MEN,Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses." "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled Please.." rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG1_CPY,Region for Channel 1 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG1_CPY0,This register is a 128 byte block copy of the PSASIG1 register for DMA destination it is write only the result can be found in the PSASIG1 register." rgroup.long 0x280++0x3 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG2_CPY,Region for Channel 2 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG2_CPY0,This register is a 128 byte block copy of the PSASIG2 register for DMA destination it is write only the result can be found in the PSASIG2 register." rgroup.long 0x300++0x3 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG3_CPY,Region for Channel 3 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG3_CPY0,This register is a 128 byte block copy of the PSASIG3 register for DMA destination it is write only the result can be found in the PSASIG3 register." rgroup.long 0x380++0x3 line.long 0x0 "VIRT_ALIAS_11_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG4_CPY,Region for Channel 4 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG4_CPY0,This register is a 128 byte block copy of the PSASIG4 register for DMA destination it is write only the result can be found in the PSASIG4 register." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MCRC_0_VIRT_ALIAS_12_MCRC0_S_CFG_MCRC64 (NAVSS0_MCRC_0_VIRT_ALIAS_12_MCRC0_S_CFG_MCRC64)" base ad:0x4BC1F70000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL0,CRC Global Control Register 0" bitfld.long 0x0 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL1,CRC Global Control Register 1" bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode. 1 = MCRC is in power down mode." "0: MCRC is not in power down mode,1: MCRC is in power down mode" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1. The seed value can be planted in PSA Signature Register during data capture mode by.." bitfld.long 0x0 24.--25. "CH4_MODE,Channel 4 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 16.--17. "CH3_MODE,Channel 3 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable" newline bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_INTS,CRC Interrupt Enable Set Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENS_,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENS_,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENS_,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_INTR,CRC Interrupt Enable Reset Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENR_,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENR_,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENR_,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" rgroup.long 0x28++0x3 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_STATUS,CRC Interrupt Status Register" bitfld.long 0x0 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_INT_OFFSET_REG,CRC Interrupt Offset" hexmask.long.byte 0x0 0.--7. 1. "CRC,Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register automatically clears the respective interrupt flag." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_BUSY,CRC Busy Register" bitfld.long 0x0 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x48++0x3 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG1,CRC Current Sector Register 1" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x4C++0x7 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x60++0xF line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL1,Channel 1 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG1,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH1,Channel 1 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL1,Channel 1 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC1,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register." line.long 0xC "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH1,Channel 1 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC1_47_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] register." rgroup.long 0x70++0xF line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG1,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL1,Channel 1 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA1,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH1,Channel 1 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA1_47_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG2,CRC Current Sector Register 2" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x8C++0x7 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xA0++0xF line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL2,Channel 2 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG2,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH2,Channel 2 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL2,Channel 2 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC2,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register." line.long 0xC "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH2,Channel 2 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register." rgroup.long 0xB0++0xF line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG2,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL2,Channel 2 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA2,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH2,Channel 2 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0xC8++0x3 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG3,CRC Current Sector Register 3" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0xCC++0x7 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xE0++0xF line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL3,Channel 3 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG3,Channel 3 PSA Signature Low Register. This register contains the value stored at PSASIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH3,Channel 3 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG3_63_32,Channel 3 PSA Signature High Register. This register contains the value stored at PSASIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL3,Channel 3 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC3,Channel 3 CRC Value Low Register. This register contains the current known good signature value stored at CRC3[31:0] register." line.long 0xC "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH3,Channel 3 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC3_63_32,Channel 3 CRC Value High Register. This register contains the current known good signature value stored at CRC3[63:32] register." rgroup.long 0xF0++0xF line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG3,Channel 3 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG3_63_32,Channel 3 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL3,Channel 3 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA3,Channel 3 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH3,Channel 3 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA3_63_32,Channel 3 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x100++0x7 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x108++0x3 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG4,CRC Current Sector Register 4" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number is logged into current sector ID.." rgroup.long 0x10C++0x7 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x120++0xF line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL4,Channel 4 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register." line.long 0x4 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH4,Channel 4 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG4_63_32,This register contains the value stored at PSASIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL4,Channel 4 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC4,Channel 4 CRC Value Low Register." line.long 0xC "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH4,Channel 4 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC4_63_32,Channel 4 CRC Value High Register." rgroup.long 0x130++0xF line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG4,Channel 4 PSA Sector Signature Low Register." line.long 0x4 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG4_63_32,Channel 4 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL4,Channel 4 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA4,Channel 4 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH4,Channel 4 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA4_63_32,Channel 4 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_MCRC_BUS_SEL,Data bus tracing selection" bitfld.long 0x0 2. "MEN,Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x0 1. "DTC_MEN,Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.." newline bitfld.long 0x0 0. "ITC_MEN,Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses." "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled Please.." rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG1_CPY,Region for Channel 1 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG1_CPY0,This register is a 128 byte block copy of the PSASIG1 register for DMA destination it is write only the result can be found in the PSASIG1 register." rgroup.long 0x280++0x3 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG2_CPY,Region for Channel 2 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG2_CPY0,This register is a 128 byte block copy of the PSASIG2 register for DMA destination it is write only the result can be found in the PSASIG2 register." rgroup.long 0x300++0x3 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG3_CPY,Region for Channel 3 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG3_CPY0,This register is a 128 byte block copy of the PSASIG3 register for DMA destination it is write only the result can be found in the PSASIG3 register." rgroup.long 0x380++0x3 line.long 0x0 "VIRT_ALIAS_12_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG4_CPY,Region for Channel 4 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG4_CPY0,This register is a 128 byte block copy of the PSASIG4 register for DMA destination it is write only the result can be found in the PSASIG4 register." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MCRC_0_VIRT_ALIAS_13_MCRC0_S_CFG_MCRC64 (NAVSS0_MCRC_0_VIRT_ALIAS_13_MCRC0_S_CFG_MCRC64)" base ad:0x4BD1F70000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL0,CRC Global Control Register 0" bitfld.long 0x0 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL1,CRC Global Control Register 1" bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode. 1 = MCRC is in power down mode." "0: MCRC is not in power down mode,1: MCRC is in power down mode" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1. The seed value can be planted in PSA Signature Register during data capture mode by.." bitfld.long 0x0 24.--25. "CH4_MODE,Channel 4 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 16.--17. "CH3_MODE,Channel 3 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable" newline bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_INTS,CRC Interrupt Enable Set Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENS_,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENS_,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENS_,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_INTR,CRC Interrupt Enable Reset Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENR_,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENR_,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENR_,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" rgroup.long 0x28++0x3 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_STATUS,CRC Interrupt Status Register" bitfld.long 0x0 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_INT_OFFSET_REG,CRC Interrupt Offset" hexmask.long.byte 0x0 0.--7. 1. "CRC,Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register automatically clears the respective interrupt flag." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_BUSY,CRC Busy Register" bitfld.long 0x0 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x48++0x3 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG1,CRC Current Sector Register 1" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x4C++0x7 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x60++0xF line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL1,Channel 1 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG1,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH1,Channel 1 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL1,Channel 1 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC1,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register." line.long 0xC "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH1,Channel 1 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC1_47_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] register." rgroup.long 0x70++0xF line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG1,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL1,Channel 1 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA1,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH1,Channel 1 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA1_47_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG2,CRC Current Sector Register 2" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x8C++0x7 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xA0++0xF line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL2,Channel 2 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG2,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH2,Channel 2 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL2,Channel 2 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC2,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register." line.long 0xC "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH2,Channel 2 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register." rgroup.long 0xB0++0xF line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG2,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL2,Channel 2 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA2,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH2,Channel 2 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0xC8++0x3 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG3,CRC Current Sector Register 3" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0xCC++0x7 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xE0++0xF line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL3,Channel 3 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG3,Channel 3 PSA Signature Low Register. This register contains the value stored at PSASIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH3,Channel 3 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG3_63_32,Channel 3 PSA Signature High Register. This register contains the value stored at PSASIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL3,Channel 3 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC3,Channel 3 CRC Value Low Register. This register contains the current known good signature value stored at CRC3[31:0] register." line.long 0xC "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH3,Channel 3 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC3_63_32,Channel 3 CRC Value High Register. This register contains the current known good signature value stored at CRC3[63:32] register." rgroup.long 0xF0++0xF line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG3,Channel 3 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG3_63_32,Channel 3 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL3,Channel 3 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA3,Channel 3 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH3,Channel 3 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA3_63_32,Channel 3 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x100++0x7 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x108++0x3 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG4,CRC Current Sector Register 4" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number is logged into current sector ID.." rgroup.long 0x10C++0x7 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x120++0xF line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL4,Channel 4 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register." line.long 0x4 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH4,Channel 4 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG4_63_32,This register contains the value stored at PSASIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL4,Channel 4 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC4,Channel 4 CRC Value Low Register." line.long 0xC "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH4,Channel 4 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC4_63_32,Channel 4 CRC Value High Register." rgroup.long 0x130++0xF line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG4,Channel 4 PSA Sector Signature Low Register." line.long 0x4 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG4_63_32,Channel 4 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL4,Channel 4 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA4,Channel 4 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH4,Channel 4 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA4_63_32,Channel 4 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_MCRC_BUS_SEL,Data bus tracing selection" bitfld.long 0x0 2. "MEN,Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x0 1. "DTC_MEN,Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.." newline bitfld.long 0x0 0. "ITC_MEN,Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses." "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled Please.." rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG1_CPY,Region for Channel 1 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG1_CPY0,This register is a 128 byte block copy of the PSASIG1 register for DMA destination it is write only the result can be found in the PSASIG1 register." rgroup.long 0x280++0x3 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG2_CPY,Region for Channel 2 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG2_CPY0,This register is a 128 byte block copy of the PSASIG2 register for DMA destination it is write only the result can be found in the PSASIG2 register." rgroup.long 0x300++0x3 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG3_CPY,Region for Channel 3 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG3_CPY0,This register is a 128 byte block copy of the PSASIG3 register for DMA destination it is write only the result can be found in the PSASIG3 register." rgroup.long 0x380++0x3 line.long 0x0 "VIRT_ALIAS_13_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG4_CPY,Region for Channel 4 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG4_CPY0,This register is a 128 byte block copy of the PSASIG4 register for DMA destination it is write only the result can be found in the PSASIG4 register." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MCRC_0_VIRT_ALIAS_14_MCRC0_S_CFG_MCRC64 (NAVSS0_MCRC_0_VIRT_ALIAS_14_MCRC0_S_CFG_MCRC64)" base ad:0x4BE1F70000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL0,CRC Global Control Register 0" bitfld.long 0x0 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL1,CRC Global Control Register 1" bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode. 1 = MCRC is in power down mode." "0: MCRC is not in power down mode,1: MCRC is in power down mode" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1. The seed value can be planted in PSA Signature Register during data capture mode by.." bitfld.long 0x0 24.--25. "CH4_MODE,Channel 4 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 16.--17. "CH3_MODE,Channel 3 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable" newline bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_INTS,CRC Interrupt Enable Set Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENS_,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENS_,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENS_,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_INTR,CRC Interrupt Enable Reset Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENR_,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENR_,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENR_,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" rgroup.long 0x28++0x3 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_STATUS,CRC Interrupt Status Register" bitfld.long 0x0 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_INT_OFFSET_REG,CRC Interrupt Offset" hexmask.long.byte 0x0 0.--7. 1. "CRC,Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register automatically clears the respective interrupt flag." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_BUSY,CRC Busy Register" bitfld.long 0x0 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x48++0x3 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG1,CRC Current Sector Register 1" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x4C++0x7 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x60++0xF line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL1,Channel 1 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG1,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH1,Channel 1 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL1,Channel 1 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC1,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register." line.long 0xC "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH1,Channel 1 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC1_47_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] register." rgroup.long 0x70++0xF line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG1,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL1,Channel 1 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA1,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH1,Channel 1 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA1_47_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG2,CRC Current Sector Register 2" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x8C++0x7 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xA0++0xF line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL2,Channel 2 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG2,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH2,Channel 2 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL2,Channel 2 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC2,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register." line.long 0xC "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH2,Channel 2 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register." rgroup.long 0xB0++0xF line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG2,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL2,Channel 2 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA2,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH2,Channel 2 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0xC8++0x3 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG3,CRC Current Sector Register 3" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0xCC++0x7 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xE0++0xF line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL3,Channel 3 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG3,Channel 3 PSA Signature Low Register. This register contains the value stored at PSASIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH3,Channel 3 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG3_63_32,Channel 3 PSA Signature High Register. This register contains the value stored at PSASIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL3,Channel 3 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC3,Channel 3 CRC Value Low Register. This register contains the current known good signature value stored at CRC3[31:0] register." line.long 0xC "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH3,Channel 3 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC3_63_32,Channel 3 CRC Value High Register. This register contains the current known good signature value stored at CRC3[63:32] register." rgroup.long 0xF0++0xF line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG3,Channel 3 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG3_63_32,Channel 3 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL3,Channel 3 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA3,Channel 3 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH3,Channel 3 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA3_63_32,Channel 3 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x100++0x7 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x108++0x3 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG4,CRC Current Sector Register 4" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number is logged into current sector ID.." rgroup.long 0x10C++0x7 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x120++0xF line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL4,Channel 4 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register." line.long 0x4 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH4,Channel 4 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG4_63_32,This register contains the value stored at PSASIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL4,Channel 4 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC4,Channel 4 CRC Value Low Register." line.long 0xC "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH4,Channel 4 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC4_63_32,Channel 4 CRC Value High Register." rgroup.long 0x130++0xF line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG4,Channel 4 PSA Sector Signature Low Register." line.long 0x4 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG4_63_32,Channel 4 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL4,Channel 4 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA4,Channel 4 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH4,Channel 4 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA4_63_32,Channel 4 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_MCRC_BUS_SEL,Data bus tracing selection" bitfld.long 0x0 2. "MEN,Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x0 1. "DTC_MEN,Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.." newline bitfld.long 0x0 0. "ITC_MEN,Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses." "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled Please.." rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG1_CPY,Region for Channel 1 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG1_CPY0,This register is a 128 byte block copy of the PSASIG1 register for DMA destination it is write only the result can be found in the PSASIG1 register." rgroup.long 0x280++0x3 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG2_CPY,Region for Channel 2 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG2_CPY0,This register is a 128 byte block copy of the PSASIG2 register for DMA destination it is write only the result can be found in the PSASIG2 register." rgroup.long 0x300++0x3 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG3_CPY,Region for Channel 3 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG3_CPY0,This register is a 128 byte block copy of the PSASIG3 register for DMA destination it is write only the result can be found in the PSASIG3 register." rgroup.long 0x380++0x3 line.long 0x0 "VIRT_ALIAS_14_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG4_CPY,Region for Channel 4 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG4_CPY0,This register is a 128 byte block copy of the PSASIG4 register for DMA destination it is write only the result can be found in the PSASIG4 register." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MCRC_0_VIRT_ALIAS_15_MCRC0_S_CFG_MCRC64 (NAVSS0_MCRC_0_VIRT_ALIAS_15_MCRC0_S_CFG_MCRC64)" base ad:0x4BF1F70000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL0,CRC Global Control Register 0" bitfld.long 0x0 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL1,CRC Global Control Register 1" bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode. 1 = MCRC is in power down mode." "0: MCRC is not in power down mode,1: MCRC is in power down mode" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1. The seed value can be planted in PSA Signature Register during data capture mode by.." bitfld.long 0x0 24.--25. "CH4_MODE,Channel 4 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 16.--17. "CH3_MODE,Channel 3 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable" newline bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" rgroup.long 0x18++0x3 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_INTS,CRC Interrupt Enable Set Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENS_,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENS_,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENS_,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_INTR,CRC Interrupt Enable Reset Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENR_,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENR_,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENR_,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" rgroup.long 0x28++0x3 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_STATUS,CRC Interrupt Status Register" bitfld.long 0x0 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_INT_OFFSET_REG,CRC Interrupt Offset" hexmask.long.byte 0x0 0.--7. 1. "CRC,Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register automatically clears the respective interrupt flag." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_BUSY,CRC Busy Register" bitfld.long 0x0 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x48++0x3 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG1,CRC Current Sector Register 1" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x4C++0x7 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x60++0xF line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL1,Channel 1 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG1,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH1,Channel 1 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL1,Channel 1 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC1,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register." line.long 0xC "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH1,Channel 1 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC1_47_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] register." rgroup.long 0x70++0xF line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG1,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register." line.long 0x4 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register." line.long 0x8 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL1,Channel 1 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA1,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH1,Channel 1 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA1_47_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG2,CRC Current Sector Register 2" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0x8C++0x7 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xA0++0xF line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL2,Channel 2 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG2,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH2,Channel 2 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL2,Channel 2 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC2,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register." line.long 0xC "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH2,Channel 2 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register." rgroup.long 0xB0++0xF line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG2,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL2,Channel 2 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA2,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH2,Channel 2 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0xC8++0x3 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG3,CRC Current Sector Register 3" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." rgroup.long 0xCC++0x7 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0xE0++0xF line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL3,Channel 3 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG3,Channel 3 PSA Signature Low Register. This register contains the value stored at PSASIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH3,Channel 3 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG3_63_32,Channel 3 PSA Signature High Register. This register contains the value stored at PSASIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL3,Channel 3 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC3,Channel 3 CRC Value Low Register. This register contains the current known good signature value stored at CRC3[31:0] register." line.long 0xC "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH3,Channel 3 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC3_63_32,Channel 3 CRC Value High Register. This register contains the current known good signature value stored at CRC3[63:32] register." rgroup.long 0xF0++0xF line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG3,Channel 3 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG3[31:0] register." line.long 0x4 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG3_63_32,Channel 3 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG3[63:32] register." line.long 0x8 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL3,Channel 3 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA3,Channel 3 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH3,Channel 3 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA3_63_32,Channel 3 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x100++0x7 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x108++0x3 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_CURSEC_REG4,CRC Current Sector Register 4" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number is logged into current sector ID.." rgroup.long 0x10C++0x7 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." rgroup.long 0x120++0xF line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGL4,Channel 4 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register." line.long 0x4 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_PSA_SIGREGH4,Channel 4 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG4_63_32,This register contains the value stored at PSASIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_REGL4,Channel 4 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC4,Channel 4 CRC Value Low Register." line.long 0xC "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_CRC_REGH4,Channel 4 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC4_63_32,Channel 4 CRC Value High Register." rgroup.long 0x130++0xF line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG4,Channel 4 PSA Sector Signature Low Register." line.long 0x4 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG4_63_32,Channel 4 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG4[63:32] register." line.long 0x8 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGL4,Channel 4 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA4,Channel 4 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_RAW_DATAREGH4,Channel 4 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA4_63_32,Channel 4 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_MCRC_BUS_SEL,Data bus tracing selection" bitfld.long 0x0 2. "MEN,Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x0 1. "DTC_MEN,Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.." newline bitfld.long 0x0 0. "ITC_MEN,Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses." "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled Please.." rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG1_CPY,Region for Channel 1 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG1_CPY0,This register is a 128 byte block copy of the PSASIG1 register for DMA destination it is write only the result can be found in the PSASIG1 register." rgroup.long 0x280++0x3 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG2_CPY,Region for Channel 2 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG2_CPY0,This register is a 128 byte block copy of the PSASIG2 register for DMA destination it is write only the result can be found in the PSASIG2 register." rgroup.long 0x300++0x3 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG3_CPY,Region for Channel 3 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG3_CPY0,This register is a 128 byte block copy of the PSASIG3 register for DMA destination it is write only the result can be found in the PSASIG3 register." rgroup.long 0x380++0x3 line.long 0x0 "VIRT_ALIAS_15_MCRC0__S_CFG__MCRC64_REGS_I0_PSA_SIGREG4_CPY,Region for Channel 4 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG4_CPY0,This register is a 128 byte block copy of the PSASIG4 register for DMA destination it is write only the result can be found in the PSASIG4 register." tree.end endif tree.end tree.end tree "NAVSS0_MODSS" tree "NAVSS0_MODSS_CFG_0" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_CFG_0_CFG (NAVSS0_MODSS_CFG_0_CFG)" base ad:0x310C0000 rgroup.long 0x0++0x3 line.long 0x0 "REGS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_CFG_0_VIRT_ALIAS_0_REGS0_CFG_MMRS (NAVSS0_MODSS_CFG_0_VIRT_ALIAS_0_REGS0_CFG_MMRS)" base ad:0x4B010C0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_REGS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_CFG_0_VIRT_ALIAS_1_REGS0_CFG_MMRS (NAVSS0_MODSS_CFG_0_VIRT_ALIAS_1_REGS0_CFG_MMRS)" base ad:0x4B110C0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_REGS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_CFG_0_VIRT_ALIAS_2_REGS0_CFG_MMRS (NAVSS0_MODSS_CFG_0_VIRT_ALIAS_2_REGS0_CFG_MMRS)" base ad:0x4B210C0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_REGS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_CFG_0_VIRT_ALIAS_3_REGS0_CFG_MMRS (NAVSS0_MODSS_CFG_0_VIRT_ALIAS_3_REGS0_CFG_MMRS)" base ad:0x4B310C0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_REGS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_CFG_0_VIRT_ALIAS_4_REGS0_CFG_MMRS (NAVSS0_MODSS_CFG_0_VIRT_ALIAS_4_REGS0_CFG_MMRS)" base ad:0x4B410C0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_REGS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_CFG_0_VIRT_ALIAS_5_REGS0_CFG_MMRS (NAVSS0_MODSS_CFG_0_VIRT_ALIAS_5_REGS0_CFG_MMRS)" base ad:0x4B510C0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_REGS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_CFG_0_VIRT_ALIAS_6_REGS0_CFG_MMRS (NAVSS0_MODSS_CFG_0_VIRT_ALIAS_6_REGS0_CFG_MMRS)" base ad:0x4B610C0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_REGS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_CFG_0_VIRT_ALIAS_7_REGS0_CFG_MMRS (NAVSS0_MODSS_CFG_0_VIRT_ALIAS_7_REGS0_CFG_MMRS)" base ad:0x4B710C0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_REGS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_CFG_0_VIRT_ALIAS_8_REGS0_CFG_MMRS (NAVSS0_MODSS_CFG_0_VIRT_ALIAS_8_REGS0_CFG_MMRS)" base ad:0x4B810C0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_REGS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_CFG_0_VIRT_ALIAS_9_REGS0_CFG_MMRS (NAVSS0_MODSS_CFG_0_VIRT_ALIAS_9_REGS0_CFG_MMRS)" base ad:0x4B910C0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_REGS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_CFG_0_VIRT_ALIAS_10_REGS0_CFG_MMRS (NAVSS0_MODSS_CFG_0_VIRT_ALIAS_10_REGS0_CFG_MMRS)" base ad:0x4BA10C0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_REGS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_CFG_0_VIRT_ALIAS_11_REGS0_CFG_MMRS (NAVSS0_MODSS_CFG_0_VIRT_ALIAS_11_REGS0_CFG_MMRS)" base ad:0x4BB10C0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_REGS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_CFG_0_VIRT_ALIAS_12_REGS0_CFG_MMRS (NAVSS0_MODSS_CFG_0_VIRT_ALIAS_12_REGS0_CFG_MMRS)" base ad:0x4BC10C0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_REGS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_CFG_0_VIRT_ALIAS_13_REGS0_CFG_MMRS (NAVSS0_MODSS_CFG_0_VIRT_ALIAS_13_REGS0_CFG_MMRS)" base ad:0x4BD10C0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_REGS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_CFG_0_VIRT_ALIAS_14_REGS0_CFG_MMRS (NAVSS0_MODSS_CFG_0_VIRT_ALIAS_14_REGS0_CFG_MMRS)" base ad:0x4BE10C0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_REGS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_CFG_0_VIRT_ALIAS_15_REGS0_CFG_MMRS (NAVSS0_MODSS_CFG_0_VIRT_ALIAS_15_REGS0_CFG_MMRS)" base ad:0x4BF10C0000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_REGS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end endif tree.end tree "NAVSS0_MODSS_INTA" tree "NAVSS0_MODSS_INTA_0" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_MODSS_INTA0_CFG (NAVSS0_MODSS_INTA_0_MODSS_INTA0_CFG)" base ad:0x30800000 rgroup.quad 0x0++0x17 line.quad 0x0 "MODSS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "MODSS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "MODSS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_MODSS_INTA0_CFG_IMAP (NAVSS0_MODSS_INTA_0_MODSS_INTA0_CFG_IMAP)" base ad:0x30900000 rgroup.quad 0x0++0x7 line.quad 0x0 "MODSS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_MODSS_INTA0_CFG_INTR (NAVSS0_MODSS_INTA_0_MODSS_INTA0_CFG_INTR)" base ad:0x33C00000 rgroup.quad 0x0++0x27 line.quad 0x0 "MODSS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual interrupt.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "MODSS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "MODSS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "MODSS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "MODSS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_ALIAS64K_MODSS_INTA0_CFG_INTR (NAVSS0_MODSS_INTA_0_ALIAS64K_MODSS_INTA0_CFG_INTR)" base ad:0x4A3C000000 rgroup.quad 0x0++0x27 line.quad 0x0 "ALIAS64K_MODSS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "ALIAS64K_MODSS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "ALIAS64K_MODSS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "ALIAS64K_MODSS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "ALIAS64K_MODSS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_0_MODSS_INTA0_CFG (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_0_MODSS_INTA0_CFG)" base ad:0x4B00800000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_0_MODSS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_0_MODSS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_0_MODSS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_0_MODSS_INTA0_CFG_IMAP (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_0_MODSS_INTA0_CFG_IMAP)" base ad:0x4B00900000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_0_MODSS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_0_MODSS_INTA0_CFG_INTR (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_0_MODSS_INTA0_CFG_INTR)" base ad:0x4B03C00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_0_MODSS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_0_MODSS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_0_MODSS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_0_MODSS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_0_MODSS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_1_MODSS_INTA0_CFG (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_1_MODSS_INTA0_CFG)" base ad:0x4B10800000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_1_MODSS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_1_MODSS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_1_MODSS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_1_MODSS_INTA0_CFG_IMAP (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_1_MODSS_INTA0_CFG_IMAP)" base ad:0x4B10900000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_1_MODSS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_1_MODSS_INTA0_CFG_INTR (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_1_MODSS_INTA0_CFG_INTR)" base ad:0x4B13C00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_1_MODSS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_1_MODSS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_1_MODSS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_1_MODSS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_1_MODSS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_2_MODSS_INTA0_CFG (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_2_MODSS_INTA0_CFG)" base ad:0x4B20800000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_2_MODSS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_2_MODSS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_2_MODSS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_2_MODSS_INTA0_CFG_IMAP (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_2_MODSS_INTA0_CFG_IMAP)" base ad:0x4B20900000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_2_MODSS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_2_MODSS_INTA0_CFG_INTR (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_2_MODSS_INTA0_CFG_INTR)" base ad:0x4B23C00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_2_MODSS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_2_MODSS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_2_MODSS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_2_MODSS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_2_MODSS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_3_MODSS_INTA0_CFG (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_3_MODSS_INTA0_CFG)" base ad:0x4B30800000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_3_MODSS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_3_MODSS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_3_MODSS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_3_MODSS_INTA0_CFG_IMAP (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_3_MODSS_INTA0_CFG_IMAP)" base ad:0x4B30900000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_3_MODSS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_3_MODSS_INTA0_CFG_INTR (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_3_MODSS_INTA0_CFG_INTR)" base ad:0x4B33C00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_3_MODSS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_3_MODSS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_3_MODSS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_3_MODSS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_3_MODSS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_4_MODSS_INTA0_CFG (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_4_MODSS_INTA0_CFG)" base ad:0x4B40800000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_4_MODSS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_4_MODSS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_4_MODSS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_4_MODSS_INTA0_CFG_IMAP (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_4_MODSS_INTA0_CFG_IMAP)" base ad:0x4B40900000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_4_MODSS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_4_MODSS_INTA0_CFG_INTR (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_4_MODSS_INTA0_CFG_INTR)" base ad:0x4B43C00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_4_MODSS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_4_MODSS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_4_MODSS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_4_MODSS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_4_MODSS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_5_MODSS_INTA0_CFG (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_5_MODSS_INTA0_CFG)" base ad:0x4B50800000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_5_MODSS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_5_MODSS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_5_MODSS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_5_MODSS_INTA0_CFG_IMAP (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_5_MODSS_INTA0_CFG_IMAP)" base ad:0x4B50900000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_5_MODSS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_5_MODSS_INTA0_CFG_INTR (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_5_MODSS_INTA0_CFG_INTR)" base ad:0x4B53C00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_5_MODSS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_5_MODSS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_5_MODSS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_5_MODSS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_5_MODSS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_6_MODSS_INTA0_CFG (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_6_MODSS_INTA0_CFG)" base ad:0x4B60800000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_6_MODSS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_6_MODSS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_6_MODSS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_6_MODSS_INTA0_CFG_IMAP (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_6_MODSS_INTA0_CFG_IMAP)" base ad:0x4B60900000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_6_MODSS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_6_MODSS_INTA0_CFG_INTR (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_6_MODSS_INTA0_CFG_INTR)" base ad:0x4B63C00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_6_MODSS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_6_MODSS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_6_MODSS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_6_MODSS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_6_MODSS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_7_MODSS_INTA0_CFG (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_7_MODSS_INTA0_CFG)" base ad:0x4B70800000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_7_MODSS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_7_MODSS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_7_MODSS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_7_MODSS_INTA0_CFG_IMAP (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_7_MODSS_INTA0_CFG_IMAP)" base ad:0x4B70900000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_7_MODSS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_7_MODSS_INTA0_CFG_INTR (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_7_MODSS_INTA0_CFG_INTR)" base ad:0x4B73C00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_7_MODSS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_7_MODSS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_7_MODSS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_7_MODSS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_7_MODSS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_8_MODSS_INTA0_CFG (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_8_MODSS_INTA0_CFG)" base ad:0x4B80800000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_8_MODSS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_8_MODSS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_8_MODSS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_8_MODSS_INTA0_CFG_IMAP (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_8_MODSS_INTA0_CFG_IMAP)" base ad:0x4B80900000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_8_MODSS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_8_MODSS_INTA0_CFG_INTR (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_8_MODSS_INTA0_CFG_INTR)" base ad:0x4B83C00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_8_MODSS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_8_MODSS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_8_MODSS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_8_MODSS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_8_MODSS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_9_MODSS_INTA0_CFG (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_9_MODSS_INTA0_CFG)" base ad:0x4B90800000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_9_MODSS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_9_MODSS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_9_MODSS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_9_MODSS_INTA0_CFG_IMAP (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_9_MODSS_INTA0_CFG_IMAP)" base ad:0x4B90900000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_9_MODSS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_9_MODSS_INTA0_CFG_INTR (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_9_MODSS_INTA0_CFG_INTR)" base ad:0x4B93C00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_9_MODSS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_9_MODSS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_9_MODSS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_9_MODSS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_9_MODSS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_10_MODSS_INTA0_CFG (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_10_MODSS_INTA0_CFG)" base ad:0x4BA0800000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_10_MODSS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_10_MODSS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_10_MODSS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_10_MODSS_INTA0_CFG_IMAP (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_10_MODSS_INTA0_CFG_IMAP)" base ad:0x4BA0900000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_10_MODSS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_10_MODSS_INTA0_CFG_INTR (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_10_MODSS_INTA0_CFG_INTR)" base ad:0x4BA3C00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_10_MODSS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_10_MODSS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_10_MODSS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_10_MODSS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_10_MODSS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_11_MODSS_INTA0_CFG (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_11_MODSS_INTA0_CFG)" base ad:0x4BB0800000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_11_MODSS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_11_MODSS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_11_MODSS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_11_MODSS_INTA0_CFG_IMAP (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_11_MODSS_INTA0_CFG_IMAP)" base ad:0x4BB0900000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_11_MODSS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_11_MODSS_INTA0_CFG_INTR (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_11_MODSS_INTA0_CFG_INTR)" base ad:0x4BB3C00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_11_MODSS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_11_MODSS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_11_MODSS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_11_MODSS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_11_MODSS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_12_MODSS_INTA0_CFG (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_12_MODSS_INTA0_CFG)" base ad:0x4BC0800000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_12_MODSS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_12_MODSS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_12_MODSS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_12_MODSS_INTA0_CFG_IMAP (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_12_MODSS_INTA0_CFG_IMAP)" base ad:0x4BC0900000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_12_MODSS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_12_MODSS_INTA0_CFG_INTR (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_12_MODSS_INTA0_CFG_INTR)" base ad:0x4BC3C00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_12_MODSS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_12_MODSS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_12_MODSS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_12_MODSS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_12_MODSS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_13_MODSS_INTA0_CFG (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_13_MODSS_INTA0_CFG)" base ad:0x4BD0800000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_13_MODSS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_13_MODSS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_13_MODSS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_13_MODSS_INTA0_CFG_IMAP (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_13_MODSS_INTA0_CFG_IMAP)" base ad:0x4BD0900000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_13_MODSS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_13_MODSS_INTA0_CFG_INTR (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_13_MODSS_INTA0_CFG_INTR)" base ad:0x4BD3C00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_13_MODSS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_13_MODSS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_13_MODSS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_13_MODSS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_13_MODSS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_14_MODSS_INTA0_CFG (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_14_MODSS_INTA0_CFG)" base ad:0x4BE0800000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_14_MODSS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_14_MODSS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_14_MODSS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_14_MODSS_INTA0_CFG_IMAP (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_14_MODSS_INTA0_CFG_IMAP)" base ad:0x4BE0900000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_14_MODSS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_14_MODSS_INTA0_CFG_INTR (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_14_MODSS_INTA0_CFG_INTR)" base ad:0x4BE3C00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_14_MODSS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_14_MODSS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_14_MODSS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_14_MODSS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_14_MODSS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_15_MODSS_INTA0_CFG (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_15_MODSS_INTA0_CFG)" base ad:0x4BF0800000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_15_MODSS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_15_MODSS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_15_MODSS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_15_MODSS_INTA0_CFG_IMAP (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_15_MODSS_INTA0_CFG_IMAP)" base ad:0x4BF0900000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_15_MODSS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_0_VIRT_ALIAS_15_MODSS_INTA0_CFG_INTR (NAVSS0_MODSS_INTA_0_VIRT_ALIAS_15_MODSS_INTA0_CFG_INTR)" base ad:0x4BF3C00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_15_MODSS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_15_MODSS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_15_MODSS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_15_MODSS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_15_MODSS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif tree.end tree "NAVSS0_MODSS_INTA_1" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_MODSS_INTA1_CFG (NAVSS0_MODSS_INTA_1_MODSS_INTA1_CFG)" base ad:0x30801000 rgroup.quad 0x0++0x17 line.quad 0x0 "MODSS_INTA1__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "MODSS_INTA1__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "MODSS_INTA1__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_MODSS_INTA1_CFG_IMAP (NAVSS0_MODSS_INTA_1_MODSS_INTA1_CFG_IMAP)" base ad:0x30908000 rgroup.quad 0x0++0x7 line.quad 0x0 "MODSS_INTA1__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_MODSS_INTA1_CFG_INTR (NAVSS0_MODSS_INTA_1_MODSS_INTA1_CFG_INTR)" base ad:0x33C40000 rgroup.quad 0x0++0x27 line.quad 0x0 "MODSS_INTA1__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual interrupt.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "MODSS_INTA1__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "MODSS_INTA1__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "MODSS_INTA1__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "MODSS_INTA1__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_ALIAS64K_MODSS_INTA1_CFG_INTR (NAVSS0_MODSS_INTA_1_ALIAS64K_MODSS_INTA1_CFG_INTR)" base ad:0x4A3C400000 rgroup.quad 0x0++0x27 line.quad 0x0 "ALIAS64K_MODSS_INTA1__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "ALIAS64K_MODSS_INTA1__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "ALIAS64K_MODSS_INTA1__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "ALIAS64K_MODSS_INTA1__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "ALIAS64K_MODSS_INTA1__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_0_MODSS_INTA1_CFG (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_0_MODSS_INTA1_CFG)" base ad:0x4B00801000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_0_MODSS_INTA1__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_0_MODSS_INTA1__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_0_MODSS_INTA1__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_0_MODSS_INTA1_CFG_IMAP (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_0_MODSS_INTA1_CFG_IMAP)" base ad:0x4B00908000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_0_MODSS_INTA1__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_0_MODSS_INTA1_CFG_INTR (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_0_MODSS_INTA1_CFG_INTR)" base ad:0x4B03C40000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_0_MODSS_INTA1__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_0_MODSS_INTA1__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_0_MODSS_INTA1__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_0_MODSS_INTA1__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_0_MODSS_INTA1__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_1_MODSS_INTA1_CFG (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_1_MODSS_INTA1_CFG)" base ad:0x4B10801000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_1_MODSS_INTA1__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_1_MODSS_INTA1__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_1_MODSS_INTA1__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_1_MODSS_INTA1_CFG_IMAP (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_1_MODSS_INTA1_CFG_IMAP)" base ad:0x4B10908000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_1_MODSS_INTA1__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_1_MODSS_INTA1_CFG_INTR (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_1_MODSS_INTA1_CFG_INTR)" base ad:0x4B13C40000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_1_MODSS_INTA1__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_1_MODSS_INTA1__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_1_MODSS_INTA1__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_1_MODSS_INTA1__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_1_MODSS_INTA1__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_2_MODSS_INTA1_CFG (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_2_MODSS_INTA1_CFG)" base ad:0x4B20801000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_2_MODSS_INTA1__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_2_MODSS_INTA1__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_2_MODSS_INTA1__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_2_MODSS_INTA1_CFG_IMAP (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_2_MODSS_INTA1_CFG_IMAP)" base ad:0x4B20908000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_2_MODSS_INTA1__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_2_MODSS_INTA1_CFG_INTR (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_2_MODSS_INTA1_CFG_INTR)" base ad:0x4B23C40000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_2_MODSS_INTA1__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_2_MODSS_INTA1__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_2_MODSS_INTA1__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_2_MODSS_INTA1__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_2_MODSS_INTA1__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_3_MODSS_INTA1_CFG (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_3_MODSS_INTA1_CFG)" base ad:0x4B30801000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_3_MODSS_INTA1__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_3_MODSS_INTA1__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_3_MODSS_INTA1__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_3_MODSS_INTA1_CFG_IMAP (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_3_MODSS_INTA1_CFG_IMAP)" base ad:0x4B30908000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_3_MODSS_INTA1__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_3_MODSS_INTA1_CFG_INTR (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_3_MODSS_INTA1_CFG_INTR)" base ad:0x4B33C40000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_3_MODSS_INTA1__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_3_MODSS_INTA1__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_3_MODSS_INTA1__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_3_MODSS_INTA1__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_3_MODSS_INTA1__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_4_MODSS_INTA1_CFG (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_4_MODSS_INTA1_CFG)" base ad:0x4B40801000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_4_MODSS_INTA1__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_4_MODSS_INTA1__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_4_MODSS_INTA1__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_4_MODSS_INTA1_CFG_IMAP (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_4_MODSS_INTA1_CFG_IMAP)" base ad:0x4B40908000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_4_MODSS_INTA1__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_4_MODSS_INTA1_CFG_INTR (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_4_MODSS_INTA1_CFG_INTR)" base ad:0x4B43C40000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_4_MODSS_INTA1__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_4_MODSS_INTA1__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_4_MODSS_INTA1__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_4_MODSS_INTA1__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_4_MODSS_INTA1__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_5_MODSS_INTA1_CFG (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_5_MODSS_INTA1_CFG)" base ad:0x4B50801000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_5_MODSS_INTA1__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_5_MODSS_INTA1__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_5_MODSS_INTA1__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_5_MODSS_INTA1_CFG_IMAP (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_5_MODSS_INTA1_CFG_IMAP)" base ad:0x4B50908000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_5_MODSS_INTA1__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_5_MODSS_INTA1_CFG_INTR (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_5_MODSS_INTA1_CFG_INTR)" base ad:0x4B53C40000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_5_MODSS_INTA1__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_5_MODSS_INTA1__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_5_MODSS_INTA1__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_5_MODSS_INTA1__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_5_MODSS_INTA1__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_6_MODSS_INTA1_CFG (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_6_MODSS_INTA1_CFG)" base ad:0x4B60801000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_6_MODSS_INTA1__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_6_MODSS_INTA1__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_6_MODSS_INTA1__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_6_MODSS_INTA1_CFG_IMAP (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_6_MODSS_INTA1_CFG_IMAP)" base ad:0x4B60908000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_6_MODSS_INTA1__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_6_MODSS_INTA1_CFG_INTR (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_6_MODSS_INTA1_CFG_INTR)" base ad:0x4B63C40000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_6_MODSS_INTA1__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_6_MODSS_INTA1__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_6_MODSS_INTA1__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_6_MODSS_INTA1__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_6_MODSS_INTA1__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_7_MODSS_INTA1_CFG (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_7_MODSS_INTA1_CFG)" base ad:0x4B70801000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_7_MODSS_INTA1__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_7_MODSS_INTA1__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_7_MODSS_INTA1__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_7_MODSS_INTA1_CFG_IMAP (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_7_MODSS_INTA1_CFG_IMAP)" base ad:0x4B70908000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_7_MODSS_INTA1__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_7_MODSS_INTA1_CFG_INTR (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_7_MODSS_INTA1_CFG_INTR)" base ad:0x4B73C40000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_7_MODSS_INTA1__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_7_MODSS_INTA1__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_7_MODSS_INTA1__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_7_MODSS_INTA1__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_7_MODSS_INTA1__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_8_MODSS_INTA1_CFG (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_8_MODSS_INTA1_CFG)" base ad:0x4B80801000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_8_MODSS_INTA1__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_8_MODSS_INTA1__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_8_MODSS_INTA1__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_8_MODSS_INTA1_CFG_IMAP (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_8_MODSS_INTA1_CFG_IMAP)" base ad:0x4B80908000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_8_MODSS_INTA1__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_8_MODSS_INTA1_CFG_INTR (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_8_MODSS_INTA1_CFG_INTR)" base ad:0x4B83C40000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_8_MODSS_INTA1__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_8_MODSS_INTA1__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_8_MODSS_INTA1__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_8_MODSS_INTA1__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_8_MODSS_INTA1__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_9_MODSS_INTA1_CFG (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_9_MODSS_INTA1_CFG)" base ad:0x4B90801000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_9_MODSS_INTA1__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_9_MODSS_INTA1__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_9_MODSS_INTA1__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_9_MODSS_INTA1_CFG_IMAP (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_9_MODSS_INTA1_CFG_IMAP)" base ad:0x4B90908000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_9_MODSS_INTA1__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_9_MODSS_INTA1_CFG_INTR (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_9_MODSS_INTA1_CFG_INTR)" base ad:0x4B93C40000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_9_MODSS_INTA1__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_9_MODSS_INTA1__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_9_MODSS_INTA1__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_9_MODSS_INTA1__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_9_MODSS_INTA1__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_10_MODSS_INTA1_CFG (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_10_MODSS_INTA1_CFG)" base ad:0x4BA0801000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_10_MODSS_INTA1__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_10_MODSS_INTA1__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_10_MODSS_INTA1__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_10_MODSS_INTA1_CFG_IMAP (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_10_MODSS_INTA1_CFG_IMAP)" base ad:0x4BA0908000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_10_MODSS_INTA1__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_10_MODSS_INTA1_CFG_INTR (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_10_MODSS_INTA1_CFG_INTR)" base ad:0x4BA3C40000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_10_MODSS_INTA1__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_10_MODSS_INTA1__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_10_MODSS_INTA1__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_10_MODSS_INTA1__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_10_MODSS_INTA1__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_11_MODSS_INTA1_CFG (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_11_MODSS_INTA1_CFG)" base ad:0x4BB0801000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_11_MODSS_INTA1__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_11_MODSS_INTA1__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_11_MODSS_INTA1__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_11_MODSS_INTA1_CFG_IMAP (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_11_MODSS_INTA1_CFG_IMAP)" base ad:0x4BB0908000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_11_MODSS_INTA1__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_11_MODSS_INTA1_CFG_INTR (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_11_MODSS_INTA1_CFG_INTR)" base ad:0x4BB3C40000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_11_MODSS_INTA1__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_11_MODSS_INTA1__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_11_MODSS_INTA1__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_11_MODSS_INTA1__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_11_MODSS_INTA1__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_12_MODSS_INTA1_CFG (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_12_MODSS_INTA1_CFG)" base ad:0x4BC0801000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_12_MODSS_INTA1__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_12_MODSS_INTA1__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_12_MODSS_INTA1__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_12_MODSS_INTA1_CFG_IMAP (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_12_MODSS_INTA1_CFG_IMAP)" base ad:0x4BC0908000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_12_MODSS_INTA1__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_12_MODSS_INTA1_CFG_INTR (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_12_MODSS_INTA1_CFG_INTR)" base ad:0x4BC3C40000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_12_MODSS_INTA1__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_12_MODSS_INTA1__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_12_MODSS_INTA1__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_12_MODSS_INTA1__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_12_MODSS_INTA1__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_13_MODSS_INTA1_CFG (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_13_MODSS_INTA1_CFG)" base ad:0x4BD0801000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_13_MODSS_INTA1__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_13_MODSS_INTA1__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_13_MODSS_INTA1__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_13_MODSS_INTA1_CFG_IMAP (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_13_MODSS_INTA1_CFG_IMAP)" base ad:0x4BD0908000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_13_MODSS_INTA1__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_13_MODSS_INTA1_CFG_INTR (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_13_MODSS_INTA1_CFG_INTR)" base ad:0x4BD3C40000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_13_MODSS_INTA1__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_13_MODSS_INTA1__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_13_MODSS_INTA1__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_13_MODSS_INTA1__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_13_MODSS_INTA1__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_14_MODSS_INTA1_CFG (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_14_MODSS_INTA1_CFG)" base ad:0x4BE0801000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_14_MODSS_INTA1__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_14_MODSS_INTA1__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_14_MODSS_INTA1__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_14_MODSS_INTA1_CFG_IMAP (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_14_MODSS_INTA1_CFG_IMAP)" base ad:0x4BE0908000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_14_MODSS_INTA1__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_14_MODSS_INTA1_CFG_INTR (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_14_MODSS_INTA1_CFG_INTR)" base ad:0x4BE3C40000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_14_MODSS_INTA1__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_14_MODSS_INTA1__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_14_MODSS_INTA1__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_14_MODSS_INTA1__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_14_MODSS_INTA1__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_15_MODSS_INTA1_CFG (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_15_MODSS_INTA1_CFG)" base ad:0x4BF0801000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_15_MODSS_INTA1__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_15_MODSS_INTA1__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_15_MODSS_INTA1__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_15_MODSS_INTA1_CFG_IMAP (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_15_MODSS_INTA1_CFG_IMAP)" base ad:0x4BF0908000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_15_MODSS_INTA1__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_MODSS_INTA_1_VIRT_ALIAS_15_MODSS_INTA1_CFG_INTR (NAVSS0_MODSS_INTA_1_VIRT_ALIAS_15_MODSS_INTA1_CFG_INTR)" base ad:0x4BF3C40000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_15_MODSS_INTA1__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_15_MODSS_INTA1__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_15_MODSS_INTA1__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_15_MODSS_INTA1__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_15_MODSS_INTA1__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif tree.end tree.end tree.end tree "NAVSS0_NBSS_0_NBSS" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_NBSS_0_NBSS_CFG_REGS0_MMRS (NAVSS0_NBSS_0_NBSS_CFG_REGS0_MMRS)" base ad:0x3700000 rgroup.long 0x0++0x3 line.long 0x0 "NBSS_CFG_REGS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_NBSS_0_NBSS_CFG_MSMC0_SLV_VIRTID_CFG_MMRS (NAVSS0_NBSS_0_NBSS_CFG_MSMC0_SLV_VIRTID_CFG_MMRS)" base ad:0x3710000 rgroup.long 0x0++0x3 line.long 0x0 "NBSS_CFG_MSMC0_SLV_VIRTID__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "NBSS_CFG_MSMC0_SLV_VIRTID__CFG__MMRS_window,The VirtID for window a." hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window a." tree.end endif tree.end tree "NAVSS0_NORTH" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_NORTH_0_NBSS_NB0_CFG_MMRS (NAVSS0_NORTH_0_NBSS_NB0_CFG_MMRS)" base ad:0x3702000 rgroup.long 0x0++0x3 line.long 0x0 "NBSS_CFG_NB0__CFG__CFG__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "NBSS_CFG_NB0__CFG__CFG__CFG__MMRS_threadmap,The Thread Map Register defines the vbusmc thread for each vbusm source." bitfld.long 0x0 0.--1. "THREADMAP,Thread map each bit is for each vbusm source. A bit of 0 maps to vbusmc thread 0 a bit of 1 maps to vbusmc thread 2." "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_NORTH_1_NBSS_NB1_CFG_MMRS (NAVSS0_NORTH_1_NBSS_NB1_CFG_MMRS)" base ad:0x3703000 rgroup.long 0x0++0x3 line.long 0x0 "NBSS_CFG_NB1__CFG__CFG__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "NBSS_CFG_NB1__CFG__CFG__CFG__MMRS_threadmap,The Thread Map Register defines the vbusmc thread for each vbusm source." bitfld.long 0x0 0.--2. "THREADMAP,Thread map each bit is for each vbusm source. A bit of 0 maps to vbusmc thread 0 a bit of 1 maps to vbusmc thread 2." "0,1,2,3,4,5,6,7" tree.end endif tree.end tree "NAVSS0_PROXY_0" tree "NAVSS0_PROXY_0_ALIAS64K" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_ALIAS64K_PROXY0_SRC_TARGET0_DATA (NAVSS0_PROXY_0_ALIAS64K_PROXY0_SRC_TARGET0_DATA)" base ad:0x4A30000000 rgroup.long 0x0++0x7 line.long 0x0 "ALIAS64K_PROXY0__SRC__TARGET0_DATA_CTL_REG,The Proxy Control for the proxy" bitfld.long 0x0 24.--26. "ELSIZE,Queue element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = 512 bytes" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--17. "MODE,Proxy Queue Mode that determines how to access the queue." "0,1,2,3" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Proxy Queue" line.long 0x4 "ALIAS64K_PROXY0__SRC__TARGET0_DATA_ST_REG,The Proxy Status for the proxy" bitfld.long 0x4 31. "ERROR,Proxy Error status" "0,1" rgroup.long 0x200++0x3 line.long 0x0 "ALIAS64K_PROXY0__SRC__TARGET0_DATA_DATA_REG,The Proxy Data for the proxy. target and channel" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_ALIAS64K_PROXY0_CFG_BUF_CFG (NAVSS0_PROXY_0_ALIAS64K_PROXY0_CFG_BUF_CFG)" base ad:0x4A34000000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_PROXY0__CFG__BUF__CFG__CFG_EVT_REG,The Proxy Event for the proxy" hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Proxy Error Event" tree.end endif tree.end tree "NAVSS0_PROXY_0_PROXY" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_PROXY_BUF (NAVSS0_PROXY_0_PROXY_BUF)" base ad:0x31130000 rgroup.long 0x0++0x3 line.long 0x0 "PROXY0__CFG__BUF__BUFRAM_SLV__RAM_DATA_REG,The Proxy Buffer for the proxy" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Buffer Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_PROXY_TARGET0_DATA (NAVSS0_PROXY_0_PROXY_TARGET0_DATA)" base ad:0x33000000 rgroup.long 0x0++0x7 line.long 0x0 "PROXY0__SRC__TARGET0_DATA_CTL_REG,The Proxy Control for the proxy" bitfld.long 0x0 24.--26. "ELSIZE,Queue element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = 512 bytes" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--17. "MODE,Proxy Queue Mode that determines how to access the queue." "0,1,2,3" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Proxy Queue" line.long 0x4 "PROXY0__SRC__TARGET0_DATA_ST_REG,The Proxy Status for the proxy" bitfld.long 0x4 31. "ERROR,Proxy Error status" "0,1" rgroup.long 0x200++0x3 line.long 0x0 "PROXY0__SRC__TARGET0_DATA_DATA_REG,The Proxy Data for the proxy. target and channel" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Data" tree.end endif tree "NAVSS0_PROXY_0_PROXY0" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_PROXY0_CFG_BUF_CFG (NAVSS0_PROXY_0_PROXY0_CFG_BUF_CFG)" base ad:0x31120000 rgroup.long 0x0++0x7 line.long 0x0 "PROXY0__CFG__BUF__CFG__GCFG_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "PROXY0__CFG__BUF__CFG__GCFG_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "PROXY0__CFG__BUF__CFG__GCFG_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_PROXY0_BUF_CFG (NAVSS0_PROXY_0_PROXY0_BUF_CFG)" base ad:0x33400000 rgroup.long 0x0++0x3 line.long 0x0 "PROXY0__CFG__BUF__CFG__CFG_EVT_REG,The Proxy Event for the proxy" hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Proxy Error Event" tree.end endif tree.end tree.end tree "NAVSS0_PROXY_0_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_0_PROXY0_CFG_BUF_CFG_GCFG (NAVSS0_PROXY_0_VIRT_ALIAS_0_PROXY0_CFG_BUF_CFG_GCFG)" base ad:0x4B01120000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_0_PROXY0__CFG__BUF__CFG__GCFG_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_0_PROXY0__CFG__BUF__CFG__GCFG_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_0_PROXY0__CFG__BUF__CFG__GCFG_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_0_PROXY0_CFG_BUFRAM_SLV_RAM (NAVSS0_PROXY_0_VIRT_ALIAS_0_PROXY0_CFG_BUFRAM_SLV_RAM)" base ad:0x4B01130000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_PROXY0__CFG__BUF__BUFRAM_SLV__RAM_DATA_REG,The Proxy Buffer for the proxy" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Buffer Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_0_PROXY0_SRC_TARGET0_DATA (NAVSS0_PROXY_0_VIRT_ALIAS_0_PROXY0_SRC_TARGET0_DATA)" base ad:0x4B03000000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_0_PROXY0__SRC__TARGET0_DATA_CTL_REG,The Proxy Control for the proxy" bitfld.long 0x0 24.--26. "ELSIZE,Queue element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = 512 bytes" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--17. "MODE,Proxy Queue Mode that determines how to access the queue." "0,1,2,3" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Proxy Queue" line.long 0x4 "VIRT_ALIAS_0_PROXY0__SRC__TARGET0_DATA_ST_REG,The Proxy Status for the proxy" bitfld.long 0x4 31. "ERROR,Proxy Error status" "0,1" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_0_PROXY0__SRC__TARGET0_DATA_DATA_REG,The Proxy Data for the proxy. target and channel" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_0_PROXY0_CFG_BUF_CFG (NAVSS0_PROXY_0_VIRT_ALIAS_0_PROXY0_CFG_BUF_CFG)" base ad:0x4B03400000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_PROXY0__CFG__BUF__CFG__CFG_EVT_REG,The Proxy Event for the proxy" hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Proxy Error Event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_1_PROXY0_CFG_BUF_CFG_GCFG (NAVSS0_PROXY_0_VIRT_ALIAS_1_PROXY0_CFG_BUF_CFG_GCFG)" base ad:0x4B11120000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_1_PROXY0__CFG__BUF__CFG__GCFG_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_1_PROXY0__CFG__BUF__CFG__GCFG_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_1_PROXY0__CFG__BUF__CFG__GCFG_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_1_PROXY0_CFG_BUFRAM_SLV_RAM (NAVSS0_PROXY_0_VIRT_ALIAS_1_PROXY0_CFG_BUFRAM_SLV_RAM)" base ad:0x4B11130000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_PROXY0__CFG__BUF__BUFRAM_SLV__RAM_DATA_REG,The Proxy Buffer for the proxy" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Buffer Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_1_PROXY0_SRC_TARGET0_DATA (NAVSS0_PROXY_0_VIRT_ALIAS_1_PROXY0_SRC_TARGET0_DATA)" base ad:0x4B13000000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_1_PROXY0__SRC__TARGET0_DATA_CTL_REG,The Proxy Control for the proxy" bitfld.long 0x0 24.--26. "ELSIZE,Queue element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = 512 bytes" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--17. "MODE,Proxy Queue Mode that determines how to access the queue." "0,1,2,3" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Proxy Queue" line.long 0x4 "VIRT_ALIAS_1_PROXY0__SRC__TARGET0_DATA_ST_REG,The Proxy Status for the proxy" bitfld.long 0x4 31. "ERROR,Proxy Error status" "0,1" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_1_PROXY0__SRC__TARGET0_DATA_DATA_REG,The Proxy Data for the proxy. target and channel" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_1_PROXY0_CFG_BUF_CFG (NAVSS0_PROXY_0_VIRT_ALIAS_1_PROXY0_CFG_BUF_CFG)" base ad:0x4B13400000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_PROXY0__CFG__BUF__CFG__CFG_EVT_REG,The Proxy Event for the proxy" hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Proxy Error Event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_2_PROXY0_CFG_BUF_CFG_GCFG (NAVSS0_PROXY_0_VIRT_ALIAS_2_PROXY0_CFG_BUF_CFG_GCFG)" base ad:0x4B21120000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_2_PROXY0__CFG__BUF__CFG__GCFG_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_2_PROXY0__CFG__BUF__CFG__GCFG_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_2_PROXY0__CFG__BUF__CFG__GCFG_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_2_PROXY0_CFG_BUFRAM_SLV_RAM (NAVSS0_PROXY_0_VIRT_ALIAS_2_PROXY0_CFG_BUFRAM_SLV_RAM)" base ad:0x4B21130000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_PROXY0__CFG__BUF__BUFRAM_SLV__RAM_DATA_REG,The Proxy Buffer for the proxy" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Buffer Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_2_PROXY0_SRC_TARGET0_DATA (NAVSS0_PROXY_0_VIRT_ALIAS_2_PROXY0_SRC_TARGET0_DATA)" base ad:0x4B23000000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_2_PROXY0__SRC__TARGET0_DATA_CTL_REG,The Proxy Control for the proxy" bitfld.long 0x0 24.--26. "ELSIZE,Queue element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = 512 bytes" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--17. "MODE,Proxy Queue Mode that determines how to access the queue." "0,1,2,3" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Proxy Queue" line.long 0x4 "VIRT_ALIAS_2_PROXY0__SRC__TARGET0_DATA_ST_REG,The Proxy Status for the proxy" bitfld.long 0x4 31. "ERROR,Proxy Error status" "0,1" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_2_PROXY0__SRC__TARGET0_DATA_DATA_REG,The Proxy Data for the proxy. target and channel" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_2_PROXY0_CFG_BUF_CFG (NAVSS0_PROXY_0_VIRT_ALIAS_2_PROXY0_CFG_BUF_CFG)" base ad:0x4B23400000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_PROXY0__CFG__BUF__CFG__CFG_EVT_REG,The Proxy Event for the proxy" hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Proxy Error Event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_3_PROXY0_CFG_BUF_CFG_GCFG (NAVSS0_PROXY_0_VIRT_ALIAS_3_PROXY0_CFG_BUF_CFG_GCFG)" base ad:0x4B31120000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_3_PROXY0__CFG__BUF__CFG__GCFG_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_3_PROXY0__CFG__BUF__CFG__GCFG_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_3_PROXY0__CFG__BUF__CFG__GCFG_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_3_PROXY0_CFG_BUFRAM_SLV_RAM (NAVSS0_PROXY_0_VIRT_ALIAS_3_PROXY0_CFG_BUFRAM_SLV_RAM)" base ad:0x4B31130000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_PROXY0__CFG__BUF__BUFRAM_SLV__RAM_DATA_REG,The Proxy Buffer for the proxy" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Buffer Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_3_PROXY0_SRC_TARGET0_DATA (NAVSS0_PROXY_0_VIRT_ALIAS_3_PROXY0_SRC_TARGET0_DATA)" base ad:0x4B33000000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_3_PROXY0__SRC__TARGET0_DATA_CTL_REG,The Proxy Control for the proxy" bitfld.long 0x0 24.--26. "ELSIZE,Queue element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = 512 bytes" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--17. "MODE,Proxy Queue Mode that determines how to access the queue." "0,1,2,3" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Proxy Queue" line.long 0x4 "VIRT_ALIAS_3_PROXY0__SRC__TARGET0_DATA_ST_REG,The Proxy Status for the proxy" bitfld.long 0x4 31. "ERROR,Proxy Error status" "0,1" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_3_PROXY0__SRC__TARGET0_DATA_DATA_REG,The Proxy Data for the proxy. target and channel" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_3_PROXY0_CFG_BUF_CFG (NAVSS0_PROXY_0_VIRT_ALIAS_3_PROXY0_CFG_BUF_CFG)" base ad:0x4B33400000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_PROXY0__CFG__BUF__CFG__CFG_EVT_REG,The Proxy Event for the proxy" hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Proxy Error Event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_4_PROXY0_CFG_BUF_CFG_GCFG (NAVSS0_PROXY_0_VIRT_ALIAS_4_PROXY0_CFG_BUF_CFG_GCFG)" base ad:0x4B41120000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_4_PROXY0__CFG__BUF__CFG__GCFG_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_4_PROXY0__CFG__BUF__CFG__GCFG_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_4_PROXY0__CFG__BUF__CFG__GCFG_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_4_PROXY0_CFG_BUFRAM_SLV_RAM (NAVSS0_PROXY_0_VIRT_ALIAS_4_PROXY0_CFG_BUFRAM_SLV_RAM)" base ad:0x4B41130000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_PROXY0__CFG__BUF__BUFRAM_SLV__RAM_DATA_REG,The Proxy Buffer for the proxy" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Buffer Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_4_PROXY0_SRC_TARGET0_DATA (NAVSS0_PROXY_0_VIRT_ALIAS_4_PROXY0_SRC_TARGET0_DATA)" base ad:0x4B43000000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_4_PROXY0__SRC__TARGET0_DATA_CTL_REG,The Proxy Control for the proxy" bitfld.long 0x0 24.--26. "ELSIZE,Queue element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = 512 bytes" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--17. "MODE,Proxy Queue Mode that determines how to access the queue." "0,1,2,3" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Proxy Queue" line.long 0x4 "VIRT_ALIAS_4_PROXY0__SRC__TARGET0_DATA_ST_REG,The Proxy Status for the proxy" bitfld.long 0x4 31. "ERROR,Proxy Error status" "0,1" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_4_PROXY0__SRC__TARGET0_DATA_DATA_REG,The Proxy Data for the proxy. target and channel" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_4_PROXY0_CFG_BUF_CFG (NAVSS0_PROXY_0_VIRT_ALIAS_4_PROXY0_CFG_BUF_CFG)" base ad:0x4B43400000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_PROXY0__CFG__BUF__CFG__CFG_EVT_REG,The Proxy Event for the proxy" hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Proxy Error Event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_5_PROXY0_CFG_BUF_CFG_GCFG (NAVSS0_PROXY_0_VIRT_ALIAS_5_PROXY0_CFG_BUF_CFG_GCFG)" base ad:0x4B51120000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_5_PROXY0__CFG__BUF__CFG__GCFG_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_5_PROXY0__CFG__BUF__CFG__GCFG_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_5_PROXY0__CFG__BUF__CFG__GCFG_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_5_PROXY0_CFG_BUFRAM_SLV_RAM (NAVSS0_PROXY_0_VIRT_ALIAS_5_PROXY0_CFG_BUFRAM_SLV_RAM)" base ad:0x4B51130000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_PROXY0__CFG__BUF__BUFRAM_SLV__RAM_DATA_REG,The Proxy Buffer for the proxy" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Buffer Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_5_PROXY0_SRC_TARGET0_DATA (NAVSS0_PROXY_0_VIRT_ALIAS_5_PROXY0_SRC_TARGET0_DATA)" base ad:0x4B53000000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_5_PROXY0__SRC__TARGET0_DATA_CTL_REG,The Proxy Control for the proxy" bitfld.long 0x0 24.--26. "ELSIZE,Queue element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = 512 bytes" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--17. "MODE,Proxy Queue Mode that determines how to access the queue." "0,1,2,3" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Proxy Queue" line.long 0x4 "VIRT_ALIAS_5_PROXY0__SRC__TARGET0_DATA_ST_REG,The Proxy Status for the proxy" bitfld.long 0x4 31. "ERROR,Proxy Error status" "0,1" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_5_PROXY0__SRC__TARGET0_DATA_DATA_REG,The Proxy Data for the proxy. target and channel" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_5_PROXY0_CFG_BUF_CFG (NAVSS0_PROXY_0_VIRT_ALIAS_5_PROXY0_CFG_BUF_CFG)" base ad:0x4B53400000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_PROXY0__CFG__BUF__CFG__CFG_EVT_REG,The Proxy Event for the proxy" hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Proxy Error Event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_6_PROXY0_CFG_BUF_CFG_GCFG (NAVSS0_PROXY_0_VIRT_ALIAS_6_PROXY0_CFG_BUF_CFG_GCFG)" base ad:0x4B61120000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_6_PROXY0__CFG__BUF__CFG__GCFG_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_6_PROXY0__CFG__BUF__CFG__GCFG_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_6_PROXY0__CFG__BUF__CFG__GCFG_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_6_PROXY0_CFG_BUFRAM_SLV_RAM (NAVSS0_PROXY_0_VIRT_ALIAS_6_PROXY0_CFG_BUFRAM_SLV_RAM)" base ad:0x4B61130000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_PROXY0__CFG__BUF__BUFRAM_SLV__RAM_DATA_REG,The Proxy Buffer for the proxy" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Buffer Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_6_PROXY0_SRC_TARGET0_DATA (NAVSS0_PROXY_0_VIRT_ALIAS_6_PROXY0_SRC_TARGET0_DATA)" base ad:0x4B63000000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_6_PROXY0__SRC__TARGET0_DATA_CTL_REG,The Proxy Control for the proxy" bitfld.long 0x0 24.--26. "ELSIZE,Queue element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = 512 bytes" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--17. "MODE,Proxy Queue Mode that determines how to access the queue." "0,1,2,3" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Proxy Queue" line.long 0x4 "VIRT_ALIAS_6_PROXY0__SRC__TARGET0_DATA_ST_REG,The Proxy Status for the proxy" bitfld.long 0x4 31. "ERROR,Proxy Error status" "0,1" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_6_PROXY0__SRC__TARGET0_DATA_DATA_REG,The Proxy Data for the proxy. target and channel" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_6_PROXY0_CFG_BUF_CFG (NAVSS0_PROXY_0_VIRT_ALIAS_6_PROXY0_CFG_BUF_CFG)" base ad:0x4B63400000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_PROXY0__CFG__BUF__CFG__CFG_EVT_REG,The Proxy Event for the proxy" hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Proxy Error Event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_7_PROXY0_CFG_BUF_CFG_GCFG (NAVSS0_PROXY_0_VIRT_ALIAS_7_PROXY0_CFG_BUF_CFG_GCFG)" base ad:0x4B71120000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_7_PROXY0__CFG__BUF__CFG__GCFG_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_7_PROXY0__CFG__BUF__CFG__GCFG_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_7_PROXY0__CFG__BUF__CFG__GCFG_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_7_PROXY0_CFG_BUFRAM_SLV_RAM (NAVSS0_PROXY_0_VIRT_ALIAS_7_PROXY0_CFG_BUFRAM_SLV_RAM)" base ad:0x4B71130000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_PROXY0__CFG__BUF__BUFRAM_SLV__RAM_DATA_REG,The Proxy Buffer for the proxy" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Buffer Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_7_PROXY0_SRC_TARGET0_DATA (NAVSS0_PROXY_0_VIRT_ALIAS_7_PROXY0_SRC_TARGET0_DATA)" base ad:0x4B73000000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_7_PROXY0__SRC__TARGET0_DATA_CTL_REG,The Proxy Control for the proxy" bitfld.long 0x0 24.--26. "ELSIZE,Queue element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = 512 bytes" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--17. "MODE,Proxy Queue Mode that determines how to access the queue." "0,1,2,3" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Proxy Queue" line.long 0x4 "VIRT_ALIAS_7_PROXY0__SRC__TARGET0_DATA_ST_REG,The Proxy Status for the proxy" bitfld.long 0x4 31. "ERROR,Proxy Error status" "0,1" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_7_PROXY0__SRC__TARGET0_DATA_DATA_REG,The Proxy Data for the proxy. target and channel" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_7_PROXY0_CFG_BUF_CFG (NAVSS0_PROXY_0_VIRT_ALIAS_7_PROXY0_CFG_BUF_CFG)" base ad:0x4B73400000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_PROXY0__CFG__BUF__CFG__CFG_EVT_REG,The Proxy Event for the proxy" hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Proxy Error Event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_8_PROXY0_CFG_BUF_CFG_GCFG (NAVSS0_PROXY_0_VIRT_ALIAS_8_PROXY0_CFG_BUF_CFG_GCFG)" base ad:0x4B81120000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_8_PROXY0__CFG__BUF__CFG__GCFG_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_8_PROXY0__CFG__BUF__CFG__GCFG_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_8_PROXY0__CFG__BUF__CFG__GCFG_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_8_PROXY0_CFG_BUFRAM_SLV_RAM (NAVSS0_PROXY_0_VIRT_ALIAS_8_PROXY0_CFG_BUFRAM_SLV_RAM)" base ad:0x4B81130000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_PROXY0__CFG__BUF__BUFRAM_SLV__RAM_DATA_REG,The Proxy Buffer for the proxy" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Buffer Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_8_PROXY0_SRC_TARGET0_DATA (NAVSS0_PROXY_0_VIRT_ALIAS_8_PROXY0_SRC_TARGET0_DATA)" base ad:0x4B83000000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_8_PROXY0__SRC__TARGET0_DATA_CTL_REG,The Proxy Control for the proxy" bitfld.long 0x0 24.--26. "ELSIZE,Queue element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = 512 bytes" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--17. "MODE,Proxy Queue Mode that determines how to access the queue." "0,1,2,3" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Proxy Queue" line.long 0x4 "VIRT_ALIAS_8_PROXY0__SRC__TARGET0_DATA_ST_REG,The Proxy Status for the proxy" bitfld.long 0x4 31. "ERROR,Proxy Error status" "0,1" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_8_PROXY0__SRC__TARGET0_DATA_DATA_REG,The Proxy Data for the proxy. target and channel" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_8_PROXY0_CFG_BUF_CFG (NAVSS0_PROXY_0_VIRT_ALIAS_8_PROXY0_CFG_BUF_CFG)" base ad:0x4B83400000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_PROXY0__CFG__BUF__CFG__CFG_EVT_REG,The Proxy Event for the proxy" hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Proxy Error Event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_9_PROXY0_CFG_BUF_CFG_GCFG (NAVSS0_PROXY_0_VIRT_ALIAS_9_PROXY0_CFG_BUF_CFG_GCFG)" base ad:0x4B91120000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_9_PROXY0__CFG__BUF__CFG__GCFG_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_9_PROXY0__CFG__BUF__CFG__GCFG_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_9_PROXY0__CFG__BUF__CFG__GCFG_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_9_PROXY0_CFG_BUFRAM_SLV_RAM (NAVSS0_PROXY_0_VIRT_ALIAS_9_PROXY0_CFG_BUFRAM_SLV_RAM)" base ad:0x4B91130000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_PROXY0__CFG__BUF__BUFRAM_SLV__RAM_DATA_REG,The Proxy Buffer for the proxy" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Buffer Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_9_PROXY0_SRC_TARGET0_DATA (NAVSS0_PROXY_0_VIRT_ALIAS_9_PROXY0_SRC_TARGET0_DATA)" base ad:0x4B93000000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_9_PROXY0__SRC__TARGET0_DATA_CTL_REG,The Proxy Control for the proxy" bitfld.long 0x0 24.--26. "ELSIZE,Queue element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = 512 bytes" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--17. "MODE,Proxy Queue Mode that determines how to access the queue." "0,1,2,3" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Proxy Queue" line.long 0x4 "VIRT_ALIAS_9_PROXY0__SRC__TARGET0_DATA_ST_REG,The Proxy Status for the proxy" bitfld.long 0x4 31. "ERROR,Proxy Error status" "0,1" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_9_PROXY0__SRC__TARGET0_DATA_DATA_REG,The Proxy Data for the proxy. target and channel" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_9_PROXY0_CFG_BUF_CFG (NAVSS0_PROXY_0_VIRT_ALIAS_9_PROXY0_CFG_BUF_CFG)" base ad:0x4B93400000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_PROXY0__CFG__BUF__CFG__CFG_EVT_REG,The Proxy Event for the proxy" hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Proxy Error Event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_10_PROXY0_CFG_BUF_CFG_GCFG (NAVSS0_PROXY_0_VIRT_ALIAS_10_PROXY0_CFG_BUF_CFG_GCFG)" base ad:0x4BA1120000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_10_PROXY0__CFG__BUF__CFG__GCFG_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_10_PROXY0__CFG__BUF__CFG__GCFG_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_10_PROXY0__CFG__BUF__CFG__GCFG_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_10_PROXY0_CFG_BUFRAM_SLV_RAM (NAVSS0_PROXY_0_VIRT_ALIAS_10_PROXY0_CFG_BUFRAM_SLV_RAM)" base ad:0x4BA1130000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_PROXY0__CFG__BUF__BUFRAM_SLV__RAM_DATA_REG,The Proxy Buffer for the proxy" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Buffer Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_10_PROXY0_SRC_TARGET0_DATA (NAVSS0_PROXY_0_VIRT_ALIAS_10_PROXY0_SRC_TARGET0_DATA)" base ad:0x4BA3000000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_10_PROXY0__SRC__TARGET0_DATA_CTL_REG,The Proxy Control for the proxy" bitfld.long 0x0 24.--26. "ELSIZE,Queue element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = 512 bytes" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--17. "MODE,Proxy Queue Mode that determines how to access the queue." "0,1,2,3" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Proxy Queue" line.long 0x4 "VIRT_ALIAS_10_PROXY0__SRC__TARGET0_DATA_ST_REG,The Proxy Status for the proxy" bitfld.long 0x4 31. "ERROR,Proxy Error status" "0,1" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_10_PROXY0__SRC__TARGET0_DATA_DATA_REG,The Proxy Data for the proxy. target and channel" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_10_PROXY0_CFG_BUF_CFG (NAVSS0_PROXY_0_VIRT_ALIAS_10_PROXY0_CFG_BUF_CFG)" base ad:0x4BA3400000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_PROXY0__CFG__BUF__CFG__CFG_EVT_REG,The Proxy Event for the proxy" hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Proxy Error Event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_11_PROXY0_CFG_BUF_CFG_GCFG (NAVSS0_PROXY_0_VIRT_ALIAS_11_PROXY0_CFG_BUF_CFG_GCFG)" base ad:0x4BB1120000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_11_PROXY0__CFG__BUF__CFG__GCFG_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_11_PROXY0__CFG__BUF__CFG__GCFG_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_11_PROXY0__CFG__BUF__CFG__GCFG_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_11_PROXY0_CFG_BUFRAM_SLV_RAM (NAVSS0_PROXY_0_VIRT_ALIAS_11_PROXY0_CFG_BUFRAM_SLV_RAM)" base ad:0x4BB1130000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_PROXY0__CFG__BUF__BUFRAM_SLV__RAM_DATA_REG,The Proxy Buffer for the proxy" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Buffer Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_11_PROXY0_SRC_TARGET0_DATA (NAVSS0_PROXY_0_VIRT_ALIAS_11_PROXY0_SRC_TARGET0_DATA)" base ad:0x4BB3000000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_11_PROXY0__SRC__TARGET0_DATA_CTL_REG,The Proxy Control for the proxy" bitfld.long 0x0 24.--26. "ELSIZE,Queue element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = 512 bytes" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--17. "MODE,Proxy Queue Mode that determines how to access the queue." "0,1,2,3" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Proxy Queue" line.long 0x4 "VIRT_ALIAS_11_PROXY0__SRC__TARGET0_DATA_ST_REG,The Proxy Status for the proxy" bitfld.long 0x4 31. "ERROR,Proxy Error status" "0,1" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_11_PROXY0__SRC__TARGET0_DATA_DATA_REG,The Proxy Data for the proxy. target and channel" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_11_PROXY0_CFG_BUF_CFG (NAVSS0_PROXY_0_VIRT_ALIAS_11_PROXY0_CFG_BUF_CFG)" base ad:0x4BB3400000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_PROXY0__CFG__BUF__CFG__CFG_EVT_REG,The Proxy Event for the proxy" hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Proxy Error Event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_12_PROXY0_CFG_BUF_CFG_GCFG (NAVSS0_PROXY_0_VIRT_ALIAS_12_PROXY0_CFG_BUF_CFG_GCFG)" base ad:0x4BC1120000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_12_PROXY0__CFG__BUF__CFG__GCFG_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_12_PROXY0__CFG__BUF__CFG__GCFG_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_12_PROXY0__CFG__BUF__CFG__GCFG_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_12_PROXY0_CFG_BUFRAM_SLV_RAM (NAVSS0_PROXY_0_VIRT_ALIAS_12_PROXY0_CFG_BUFRAM_SLV_RAM)" base ad:0x4BC1130000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_PROXY0__CFG__BUF__BUFRAM_SLV__RAM_DATA_REG,The Proxy Buffer for the proxy" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Buffer Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_12_PROXY0_SRC_TARGET0_DATA (NAVSS0_PROXY_0_VIRT_ALIAS_12_PROXY0_SRC_TARGET0_DATA)" base ad:0x4BC3000000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_12_PROXY0__SRC__TARGET0_DATA_CTL_REG,The Proxy Control for the proxy" bitfld.long 0x0 24.--26. "ELSIZE,Queue element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = 512 bytes" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--17. "MODE,Proxy Queue Mode that determines how to access the queue." "0,1,2,3" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Proxy Queue" line.long 0x4 "VIRT_ALIAS_12_PROXY0__SRC__TARGET0_DATA_ST_REG,The Proxy Status for the proxy" bitfld.long 0x4 31. "ERROR,Proxy Error status" "0,1" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_12_PROXY0__SRC__TARGET0_DATA_DATA_REG,The Proxy Data for the proxy. target and channel" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_12_PROXY0_CFG_BUF_CFG (NAVSS0_PROXY_0_VIRT_ALIAS_12_PROXY0_CFG_BUF_CFG)" base ad:0x4BC3400000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_PROXY0__CFG__BUF__CFG__CFG_EVT_REG,The Proxy Event for the proxy" hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Proxy Error Event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_13_PROXY0_CFG_BUF_CFG_GCFG (NAVSS0_PROXY_0_VIRT_ALIAS_13_PROXY0_CFG_BUF_CFG_GCFG)" base ad:0x4BD1120000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_13_PROXY0__CFG__BUF__CFG__GCFG_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_13_PROXY0__CFG__BUF__CFG__GCFG_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_13_PROXY0__CFG__BUF__CFG__GCFG_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_13_PROXY0_CFG_BUFRAM_SLV_RAM (NAVSS0_PROXY_0_VIRT_ALIAS_13_PROXY0_CFG_BUFRAM_SLV_RAM)" base ad:0x4BD1130000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_PROXY0__CFG__BUF__BUFRAM_SLV__RAM_DATA_REG,The Proxy Buffer for the proxy" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Buffer Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_13_PROXY0_SRC_TARGET0_DATA (NAVSS0_PROXY_0_VIRT_ALIAS_13_PROXY0_SRC_TARGET0_DATA)" base ad:0x4BD3000000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_13_PROXY0__SRC__TARGET0_DATA_CTL_REG,The Proxy Control for the proxy" bitfld.long 0x0 24.--26. "ELSIZE,Queue element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = 512 bytes" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--17. "MODE,Proxy Queue Mode that determines how to access the queue." "0,1,2,3" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Proxy Queue" line.long 0x4 "VIRT_ALIAS_13_PROXY0__SRC__TARGET0_DATA_ST_REG,The Proxy Status for the proxy" bitfld.long 0x4 31. "ERROR,Proxy Error status" "0,1" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_13_PROXY0__SRC__TARGET0_DATA_DATA_REG,The Proxy Data for the proxy. target and channel" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_13_PROXY0_CFG_BUF_CFG (NAVSS0_PROXY_0_VIRT_ALIAS_13_PROXY0_CFG_BUF_CFG)" base ad:0x4BD3400000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_PROXY0__CFG__BUF__CFG__CFG_EVT_REG,The Proxy Event for the proxy" hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Proxy Error Event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_14_PROXY0_CFG_BUF_CFG_GCFG (NAVSS0_PROXY_0_VIRT_ALIAS_14_PROXY0_CFG_BUF_CFG_GCFG)" base ad:0x4BE1120000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_14_PROXY0__CFG__BUF__CFG__GCFG_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_14_PROXY0__CFG__BUF__CFG__GCFG_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_14_PROXY0__CFG__BUF__CFG__GCFG_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_14_PROXY0_CFG_BUFRAM_SLV_RAM (NAVSS0_PROXY_0_VIRT_ALIAS_14_PROXY0_CFG_BUFRAM_SLV_RAM)" base ad:0x4BE1130000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_PROXY0__CFG__BUF__BUFRAM_SLV__RAM_DATA_REG,The Proxy Buffer for the proxy" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Buffer Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_14_PROXY0_SRC_TARGET0_DATA (NAVSS0_PROXY_0_VIRT_ALIAS_14_PROXY0_SRC_TARGET0_DATA)" base ad:0x4BE3000000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_14_PROXY0__SRC__TARGET0_DATA_CTL_REG,The Proxy Control for the proxy" bitfld.long 0x0 24.--26. "ELSIZE,Queue element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = 512 bytes" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--17. "MODE,Proxy Queue Mode that determines how to access the queue." "0,1,2,3" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Proxy Queue" line.long 0x4 "VIRT_ALIAS_14_PROXY0__SRC__TARGET0_DATA_ST_REG,The Proxy Status for the proxy" bitfld.long 0x4 31. "ERROR,Proxy Error status" "0,1" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_14_PROXY0__SRC__TARGET0_DATA_DATA_REG,The Proxy Data for the proxy. target and channel" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_14_PROXY0_CFG_BUF_CFG (NAVSS0_PROXY_0_VIRT_ALIAS_14_PROXY0_CFG_BUF_CFG)" base ad:0x4BE3400000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_PROXY0__CFG__BUF__CFG__CFG_EVT_REG,The Proxy Event for the proxy" hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Proxy Error Event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_15_PROXY0_CFG_BUF_CFG_GCFG (NAVSS0_PROXY_0_VIRT_ALIAS_15_PROXY0_CFG_BUF_CFG_GCFG)" base ad:0x4BF1120000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_15_PROXY0__CFG__BUF__CFG__GCFG_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_15_PROXY0__CFG__BUF__CFG__GCFG_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_15_PROXY0__CFG__BUF__CFG__GCFG_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_15_PROXY0_CFG_BUFRAM_SLV_RAM (NAVSS0_PROXY_0_VIRT_ALIAS_15_PROXY0_CFG_BUFRAM_SLV_RAM)" base ad:0x4BF1130000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_PROXY0__CFG__BUF__BUFRAM_SLV__RAM_DATA_REG,The Proxy Buffer for the proxy" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Buffer Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_15_PROXY0_SRC_TARGET0_DATA (NAVSS0_PROXY_0_VIRT_ALIAS_15_PROXY0_SRC_TARGET0_DATA)" base ad:0x4BF3000000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_15_PROXY0__SRC__TARGET0_DATA_CTL_REG,The Proxy Control for the proxy" bitfld.long 0x0 24.--26. "ELSIZE,Queue element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = 512 bytes" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--17. "MODE,Proxy Queue Mode that determines how to access the queue." "0,1,2,3" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Proxy Queue" line.long 0x4 "VIRT_ALIAS_15_PROXY0__SRC__TARGET0_DATA_ST_REG,The Proxy Status for the proxy" bitfld.long 0x4 31. "ERROR,Proxy Error status" "0,1" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_15_PROXY0__SRC__TARGET0_DATA_DATA_REG,The Proxy Data for the proxy. target and channel" hexmask.long 0x0 0.--31. 1. "DATA,Proxy Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PROXY_0_VIRT_ALIAS_15_PROXY0_CFG_BUF_CFG (NAVSS0_PROXY_0_VIRT_ALIAS_15_PROXY0_CFG_BUF_CFG)" base ad:0x4BF3400000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_PROXY0__CFG__BUF__CFG__CFG_EVT_REG,The Proxy Event for the proxy" hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Proxy Error Event" tree.end endif tree.end tree.end tree "NAVSS0_PSILCFG_0" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILCFG_0_UDMASS_PSILCFG0_CFG_PROXY (NAVSS0_PSILCFG_0_UDMASS_PSILCFG0_CFG_PROXY)" base ad:0x31F78000 rgroup.long 0x0++0x3 line.long 0x0 "PSILCFG0__CFG__PROXY_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "PSILCFG0__CFG__PROXY_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access. Once set this bit is persistent until manually cleared" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x100++0xB line.long 0x0 "PSILCFG0__CFG__PROXY_PSIL_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction." bitfld.long 0x0 31. "PROXY_BUSY,Indication that a configuration read or write is in progress" "0,1" bitfld.long 0x0 30. "PROXY_DIR,Direction of configuration transaction" "0,1" bitfld.long 0x0 29. "PROXY_TOUT,Indication that a timeout occurred. This bit should be written to 0 on each new transaction." "0,1" hexmask.long.word 0x0 0.--15. 1. "PROXY_THREAD_ID,Thread ID to which configuration read or write is being sent" line.long 0x4 "PSILCFG0__CFG__PROXY_PSIL_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction." hexmask.long.byte 0x4 28.--31. 1. "PROXY_BYTEN,Byte enables to use for configuration read or write" hexmask.long.word 0x4 0.--15. 1. "PROXY_ADDRESS,Word (32-bit) address within thread configuration space for transaction" line.long 0x8 "PSILCFG0__CFG__PROXY_PSIL_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction." hexmask.long 0x8 0.--31. 1. "PROXY_WDATA,Configuration data word to be written" rgroup.long 0x140++0x3 line.long 0x0 "PSILCFG0__CFG__PROXY_PSIL_RDATA,The Read Data Register contains the data which which was read back during the configuration transaction." hexmask.long 0x0 0.--31. 1. "PROXY_RDATA,Configuration data word that was read" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILCFG_0_ALIAS64K_PSILCFG0_CFG_PROXY (NAVSS0_PSILCFG_0_ALIAS64K_PSILCFG0_CFG_PROXY)" base ad:0x4A1F780000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_PSILCFG0__CFG__PROXY_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_PSILCFG0__CFG__PROXY_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access. Once set this bit is persistent until manually cleared" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x100++0xB line.long 0x0 "ALIAS64K_PSILCFG0__CFG__PROXY_PSIL_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction." bitfld.long 0x0 31. "PROXY_BUSY,Indication that a configuration read or write is in progress" "0,1" bitfld.long 0x0 30. "PROXY_DIR,Direction of configuration transaction" "0,1" bitfld.long 0x0 29. "PROXY_TOUT,Indication that a timeout occurred. This bit should be written to 0 on each new transaction." "0,1" hexmask.long.word 0x0 0.--15. 1. "PROXY_THREAD_ID,Thread ID to which configuration read or write is being sent" line.long 0x4 "ALIAS64K_PSILCFG0__CFG__PROXY_PSIL_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction." hexmask.long.byte 0x4 28.--31. 1. "PROXY_BYTEN,Byte enables to use for configuration read or write" hexmask.long.word 0x4 0.--15. 1. "PROXY_ADDRESS,Word (32-bit) address within thread configuration space for transaction" line.long 0x8 "ALIAS64K_PSILCFG0__CFG__PROXY_PSIL_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction." hexmask.long 0x8 0.--31. 1. "PROXY_WDATA,Configuration data word to be written" rgroup.long 0x140++0x3 line.long 0x0 "ALIAS64K_PSILCFG0__CFG__PROXY_PSIL_RDATA,The Read Data Register contains the data which which was read back during the configuration transaction." hexmask.long 0x0 0.--31. 1. "PROXY_RDATA,Configuration data word that was read" tree.end endif tree "NAVSS0_PSILCFG_0_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILCFG_0_VIRT_ALIAS_0_PSILCFG0_CFG_PROXY (NAVSS0_PSILCFG_0_VIRT_ALIAS_0_PSILCFG0_CFG_PROXY)" base ad:0x4B01F78000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_PSILCFG0__CFG__PROXY_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_PSILCFG0__CFG__PROXY_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access. Once set this bit is persistent until manually cleared" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x100++0xB line.long 0x0 "VIRT_ALIAS_0_PSILCFG0__CFG__PROXY_PSIL_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction." bitfld.long 0x0 31. "PROXY_BUSY,Indication that a configuration read or write is in progress" "0,1" bitfld.long 0x0 30. "PROXY_DIR,Direction of configuration transaction" "0,1" bitfld.long 0x0 29. "PROXY_TOUT,Indication that a timeout occurred. This bit should be written to 0 on each new transaction." "0,1" hexmask.long.word 0x0 0.--15. 1. "PROXY_THREAD_ID,Thread ID to which configuration read or write is being sent" line.long 0x4 "VIRT_ALIAS_0_PSILCFG0__CFG__PROXY_PSIL_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction." hexmask.long.byte 0x4 28.--31. 1. "PROXY_BYTEN,Byte enables to use for configuration read or write" hexmask.long.word 0x4 0.--15. 1. "PROXY_ADDRESS,Word (32-bit) address within thread configuration space for transaction" line.long 0x8 "VIRT_ALIAS_0_PSILCFG0__CFG__PROXY_PSIL_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction." hexmask.long 0x8 0.--31. 1. "PROXY_WDATA,Configuration data word to be written" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_0_PSILCFG0__CFG__PROXY_PSIL_RDATA,The Read Data Register contains the data which which was read back during the configuration transaction." hexmask.long 0x0 0.--31. 1. "PROXY_RDATA,Configuration data word that was read" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILCFG_0_VIRT_ALIAS_1_PSILCFG0_CFG_PROXY (NAVSS0_PSILCFG_0_VIRT_ALIAS_1_PSILCFG0_CFG_PROXY)" base ad:0x4B11F78000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_PSILCFG0__CFG__PROXY_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_PSILCFG0__CFG__PROXY_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access. Once set this bit is persistent until manually cleared" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x100++0xB line.long 0x0 "VIRT_ALIAS_1_PSILCFG0__CFG__PROXY_PSIL_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction." bitfld.long 0x0 31. "PROXY_BUSY,Indication that a configuration read or write is in progress" "0,1" bitfld.long 0x0 30. "PROXY_DIR,Direction of configuration transaction" "0,1" bitfld.long 0x0 29. "PROXY_TOUT,Indication that a timeout occurred. This bit should be written to 0 on each new transaction." "0,1" hexmask.long.word 0x0 0.--15. 1. "PROXY_THREAD_ID,Thread ID to which configuration read or write is being sent" line.long 0x4 "VIRT_ALIAS_1_PSILCFG0__CFG__PROXY_PSIL_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction." hexmask.long.byte 0x4 28.--31. 1. "PROXY_BYTEN,Byte enables to use for configuration read or write" hexmask.long.word 0x4 0.--15. 1. "PROXY_ADDRESS,Word (32-bit) address within thread configuration space for transaction" line.long 0x8 "VIRT_ALIAS_1_PSILCFG0__CFG__PROXY_PSIL_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction." hexmask.long 0x8 0.--31. 1. "PROXY_WDATA,Configuration data word to be written" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_1_PSILCFG0__CFG__PROXY_PSIL_RDATA,The Read Data Register contains the data which which was read back during the configuration transaction." hexmask.long 0x0 0.--31. 1. "PROXY_RDATA,Configuration data word that was read" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILCFG_0_VIRT_ALIAS_2_PSILCFG0_CFG_PROXY (NAVSS0_PSILCFG_0_VIRT_ALIAS_2_PSILCFG0_CFG_PROXY)" base ad:0x4B21F78000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_PSILCFG0__CFG__PROXY_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_PSILCFG0__CFG__PROXY_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access. Once set this bit is persistent until manually cleared" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x100++0xB line.long 0x0 "VIRT_ALIAS_2_PSILCFG0__CFG__PROXY_PSIL_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction." bitfld.long 0x0 31. "PROXY_BUSY,Indication that a configuration read or write is in progress" "0,1" bitfld.long 0x0 30. "PROXY_DIR,Direction of configuration transaction" "0,1" bitfld.long 0x0 29. "PROXY_TOUT,Indication that a timeout occurred. This bit should be written to 0 on each new transaction." "0,1" hexmask.long.word 0x0 0.--15. 1. "PROXY_THREAD_ID,Thread ID to which configuration read or write is being sent" line.long 0x4 "VIRT_ALIAS_2_PSILCFG0__CFG__PROXY_PSIL_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction." hexmask.long.byte 0x4 28.--31. 1. "PROXY_BYTEN,Byte enables to use for configuration read or write" hexmask.long.word 0x4 0.--15. 1. "PROXY_ADDRESS,Word (32-bit) address within thread configuration space for transaction" line.long 0x8 "VIRT_ALIAS_2_PSILCFG0__CFG__PROXY_PSIL_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction." hexmask.long 0x8 0.--31. 1. "PROXY_WDATA,Configuration data word to be written" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_2_PSILCFG0__CFG__PROXY_PSIL_RDATA,The Read Data Register contains the data which which was read back during the configuration transaction." hexmask.long 0x0 0.--31. 1. "PROXY_RDATA,Configuration data word that was read" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILCFG_0_VIRT_ALIAS_3_PSILCFG0_CFG_PROXY (NAVSS0_PSILCFG_0_VIRT_ALIAS_3_PSILCFG0_CFG_PROXY)" base ad:0x4B31F78000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_PSILCFG0__CFG__PROXY_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_PSILCFG0__CFG__PROXY_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access. Once set this bit is persistent until manually cleared" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x100++0xB line.long 0x0 "VIRT_ALIAS_3_PSILCFG0__CFG__PROXY_PSIL_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction." bitfld.long 0x0 31. "PROXY_BUSY,Indication that a configuration read or write is in progress" "0,1" bitfld.long 0x0 30. "PROXY_DIR,Direction of configuration transaction" "0,1" bitfld.long 0x0 29. "PROXY_TOUT,Indication that a timeout occurred. This bit should be written to 0 on each new transaction." "0,1" hexmask.long.word 0x0 0.--15. 1. "PROXY_THREAD_ID,Thread ID to which configuration read or write is being sent" line.long 0x4 "VIRT_ALIAS_3_PSILCFG0__CFG__PROXY_PSIL_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction." hexmask.long.byte 0x4 28.--31. 1. "PROXY_BYTEN,Byte enables to use for configuration read or write" hexmask.long.word 0x4 0.--15. 1. "PROXY_ADDRESS,Word (32-bit) address within thread configuration space for transaction" line.long 0x8 "VIRT_ALIAS_3_PSILCFG0__CFG__PROXY_PSIL_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction." hexmask.long 0x8 0.--31. 1. "PROXY_WDATA,Configuration data word to be written" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_3_PSILCFG0__CFG__PROXY_PSIL_RDATA,The Read Data Register contains the data which which was read back during the configuration transaction." hexmask.long 0x0 0.--31. 1. "PROXY_RDATA,Configuration data word that was read" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILCFG_0_VIRT_ALIAS_4_PSILCFG0_CFG_PROXY (NAVSS0_PSILCFG_0_VIRT_ALIAS_4_PSILCFG0_CFG_PROXY)" base ad:0x4B41F78000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_PSILCFG0__CFG__PROXY_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_PSILCFG0__CFG__PROXY_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access. Once set this bit is persistent until manually cleared" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x100++0xB line.long 0x0 "VIRT_ALIAS_4_PSILCFG0__CFG__PROXY_PSIL_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction." bitfld.long 0x0 31. "PROXY_BUSY,Indication that a configuration read or write is in progress" "0,1" bitfld.long 0x0 30. "PROXY_DIR,Direction of configuration transaction" "0,1" bitfld.long 0x0 29. "PROXY_TOUT,Indication that a timeout occurred. This bit should be written to 0 on each new transaction." "0,1" hexmask.long.word 0x0 0.--15. 1. "PROXY_THREAD_ID,Thread ID to which configuration read or write is being sent" line.long 0x4 "VIRT_ALIAS_4_PSILCFG0__CFG__PROXY_PSIL_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction." hexmask.long.byte 0x4 28.--31. 1. "PROXY_BYTEN,Byte enables to use for configuration read or write" hexmask.long.word 0x4 0.--15. 1. "PROXY_ADDRESS,Word (32-bit) address within thread configuration space for transaction" line.long 0x8 "VIRT_ALIAS_4_PSILCFG0__CFG__PROXY_PSIL_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction." hexmask.long 0x8 0.--31. 1. "PROXY_WDATA,Configuration data word to be written" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_4_PSILCFG0__CFG__PROXY_PSIL_RDATA,The Read Data Register contains the data which which was read back during the configuration transaction." hexmask.long 0x0 0.--31. 1. "PROXY_RDATA,Configuration data word that was read" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILCFG_0_VIRT_ALIAS_5_PSILCFG0_CFG_PROXY (NAVSS0_PSILCFG_0_VIRT_ALIAS_5_PSILCFG0_CFG_PROXY)" base ad:0x4B51F78000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_PSILCFG0__CFG__PROXY_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_PSILCFG0__CFG__PROXY_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access. Once set this bit is persistent until manually cleared" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x100++0xB line.long 0x0 "VIRT_ALIAS_5_PSILCFG0__CFG__PROXY_PSIL_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction." bitfld.long 0x0 31. "PROXY_BUSY,Indication that a configuration read or write is in progress" "0,1" bitfld.long 0x0 30. "PROXY_DIR,Direction of configuration transaction" "0,1" bitfld.long 0x0 29. "PROXY_TOUT,Indication that a timeout occurred. This bit should be written to 0 on each new transaction." "0,1" hexmask.long.word 0x0 0.--15. 1. "PROXY_THREAD_ID,Thread ID to which configuration read or write is being sent" line.long 0x4 "VIRT_ALIAS_5_PSILCFG0__CFG__PROXY_PSIL_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction." hexmask.long.byte 0x4 28.--31. 1. "PROXY_BYTEN,Byte enables to use for configuration read or write" hexmask.long.word 0x4 0.--15. 1. "PROXY_ADDRESS,Word (32-bit) address within thread configuration space for transaction" line.long 0x8 "VIRT_ALIAS_5_PSILCFG0__CFG__PROXY_PSIL_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction." hexmask.long 0x8 0.--31. 1. "PROXY_WDATA,Configuration data word to be written" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_5_PSILCFG0__CFG__PROXY_PSIL_RDATA,The Read Data Register contains the data which which was read back during the configuration transaction." hexmask.long 0x0 0.--31. 1. "PROXY_RDATA,Configuration data word that was read" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILCFG_0_VIRT_ALIAS_6_PSILCFG0_CFG_PROXY (NAVSS0_PSILCFG_0_VIRT_ALIAS_6_PSILCFG0_CFG_PROXY)" base ad:0x4B61F78000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_PSILCFG0__CFG__PROXY_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_PSILCFG0__CFG__PROXY_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access. Once set this bit is persistent until manually cleared" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x100++0xB line.long 0x0 "VIRT_ALIAS_6_PSILCFG0__CFG__PROXY_PSIL_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction." bitfld.long 0x0 31. "PROXY_BUSY,Indication that a configuration read or write is in progress" "0,1" bitfld.long 0x0 30. "PROXY_DIR,Direction of configuration transaction" "0,1" bitfld.long 0x0 29. "PROXY_TOUT,Indication that a timeout occurred. This bit should be written to 0 on each new transaction." "0,1" hexmask.long.word 0x0 0.--15. 1. "PROXY_THREAD_ID,Thread ID to which configuration read or write is being sent" line.long 0x4 "VIRT_ALIAS_6_PSILCFG0__CFG__PROXY_PSIL_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction." hexmask.long.byte 0x4 28.--31. 1. "PROXY_BYTEN,Byte enables to use for configuration read or write" hexmask.long.word 0x4 0.--15. 1. "PROXY_ADDRESS,Word (32-bit) address within thread configuration space for transaction" line.long 0x8 "VIRT_ALIAS_6_PSILCFG0__CFG__PROXY_PSIL_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction." hexmask.long 0x8 0.--31. 1. "PROXY_WDATA,Configuration data word to be written" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_6_PSILCFG0__CFG__PROXY_PSIL_RDATA,The Read Data Register contains the data which which was read back during the configuration transaction." hexmask.long 0x0 0.--31. 1. "PROXY_RDATA,Configuration data word that was read" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILCFG_0_VIRT_ALIAS_7_PSILCFG0_CFG_PROXY (NAVSS0_PSILCFG_0_VIRT_ALIAS_7_PSILCFG0_CFG_PROXY)" base ad:0x4B71F78000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_PSILCFG0__CFG__PROXY_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_PSILCFG0__CFG__PROXY_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access. Once set this bit is persistent until manually cleared" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x100++0xB line.long 0x0 "VIRT_ALIAS_7_PSILCFG0__CFG__PROXY_PSIL_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction." bitfld.long 0x0 31. "PROXY_BUSY,Indication that a configuration read or write is in progress" "0,1" bitfld.long 0x0 30. "PROXY_DIR,Direction of configuration transaction" "0,1" bitfld.long 0x0 29. "PROXY_TOUT,Indication that a timeout occurred. This bit should be written to 0 on each new transaction." "0,1" hexmask.long.word 0x0 0.--15. 1. "PROXY_THREAD_ID,Thread ID to which configuration read or write is being sent" line.long 0x4 "VIRT_ALIAS_7_PSILCFG0__CFG__PROXY_PSIL_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction." hexmask.long.byte 0x4 28.--31. 1. "PROXY_BYTEN,Byte enables to use for configuration read or write" hexmask.long.word 0x4 0.--15. 1. "PROXY_ADDRESS,Word (32-bit) address within thread configuration space for transaction" line.long 0x8 "VIRT_ALIAS_7_PSILCFG0__CFG__PROXY_PSIL_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction." hexmask.long 0x8 0.--31. 1. "PROXY_WDATA,Configuration data word to be written" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_7_PSILCFG0__CFG__PROXY_PSIL_RDATA,The Read Data Register contains the data which which was read back during the configuration transaction." hexmask.long 0x0 0.--31. 1. "PROXY_RDATA,Configuration data word that was read" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILCFG_0_VIRT_ALIAS_8_PSILCFG0_CFG_PROXY (NAVSS0_PSILCFG_0_VIRT_ALIAS_8_PSILCFG0_CFG_PROXY)" base ad:0x4B81F78000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_PSILCFG0__CFG__PROXY_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_PSILCFG0__CFG__PROXY_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access. Once set this bit is persistent until manually cleared" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x100++0xB line.long 0x0 "VIRT_ALIAS_8_PSILCFG0__CFG__PROXY_PSIL_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction." bitfld.long 0x0 31. "PROXY_BUSY,Indication that a configuration read or write is in progress" "0,1" bitfld.long 0x0 30. "PROXY_DIR,Direction of configuration transaction" "0,1" bitfld.long 0x0 29. "PROXY_TOUT,Indication that a timeout occurred. This bit should be written to 0 on each new transaction." "0,1" hexmask.long.word 0x0 0.--15. 1. "PROXY_THREAD_ID,Thread ID to which configuration read or write is being sent" line.long 0x4 "VIRT_ALIAS_8_PSILCFG0__CFG__PROXY_PSIL_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction." hexmask.long.byte 0x4 28.--31. 1. "PROXY_BYTEN,Byte enables to use for configuration read or write" hexmask.long.word 0x4 0.--15. 1. "PROXY_ADDRESS,Word (32-bit) address within thread configuration space for transaction" line.long 0x8 "VIRT_ALIAS_8_PSILCFG0__CFG__PROXY_PSIL_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction." hexmask.long 0x8 0.--31. 1. "PROXY_WDATA,Configuration data word to be written" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_8_PSILCFG0__CFG__PROXY_PSIL_RDATA,The Read Data Register contains the data which which was read back during the configuration transaction." hexmask.long 0x0 0.--31. 1. "PROXY_RDATA,Configuration data word that was read" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILCFG_0_VIRT_ALIAS_9_PSILCFG0_CFG_PROXY (NAVSS0_PSILCFG_0_VIRT_ALIAS_9_PSILCFG0_CFG_PROXY)" base ad:0x4B91F78000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_PSILCFG0__CFG__PROXY_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_PSILCFG0__CFG__PROXY_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access. Once set this bit is persistent until manually cleared" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x100++0xB line.long 0x0 "VIRT_ALIAS_9_PSILCFG0__CFG__PROXY_PSIL_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction." bitfld.long 0x0 31. "PROXY_BUSY,Indication that a configuration read or write is in progress" "0,1" bitfld.long 0x0 30. "PROXY_DIR,Direction of configuration transaction" "0,1" bitfld.long 0x0 29. "PROXY_TOUT,Indication that a timeout occurred. This bit should be written to 0 on each new transaction." "0,1" hexmask.long.word 0x0 0.--15. 1. "PROXY_THREAD_ID,Thread ID to which configuration read or write is being sent" line.long 0x4 "VIRT_ALIAS_9_PSILCFG0__CFG__PROXY_PSIL_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction." hexmask.long.byte 0x4 28.--31. 1. "PROXY_BYTEN,Byte enables to use for configuration read or write" hexmask.long.word 0x4 0.--15. 1. "PROXY_ADDRESS,Word (32-bit) address within thread configuration space for transaction" line.long 0x8 "VIRT_ALIAS_9_PSILCFG0__CFG__PROXY_PSIL_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction." hexmask.long 0x8 0.--31. 1. "PROXY_WDATA,Configuration data word to be written" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_9_PSILCFG0__CFG__PROXY_PSIL_RDATA,The Read Data Register contains the data which which was read back during the configuration transaction." hexmask.long 0x0 0.--31. 1. "PROXY_RDATA,Configuration data word that was read" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILCFG_0_VIRT_ALIAS_10_PSILCFG0_CFG_PROXY (NAVSS0_PSILCFG_0_VIRT_ALIAS_10_PSILCFG0_CFG_PROXY)" base ad:0x4BA1F78000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_PSILCFG0__CFG__PROXY_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_PSILCFG0__CFG__PROXY_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access. Once set this bit is persistent until manually cleared" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x100++0xB line.long 0x0 "VIRT_ALIAS_10_PSILCFG0__CFG__PROXY_PSIL_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction." bitfld.long 0x0 31. "PROXY_BUSY,Indication that a configuration read or write is in progress" "0,1" bitfld.long 0x0 30. "PROXY_DIR,Direction of configuration transaction" "0,1" bitfld.long 0x0 29. "PROXY_TOUT,Indication that a timeout occurred. This bit should be written to 0 on each new transaction." "0,1" hexmask.long.word 0x0 0.--15. 1. "PROXY_THREAD_ID,Thread ID to which configuration read or write is being sent" line.long 0x4 "VIRT_ALIAS_10_PSILCFG0__CFG__PROXY_PSIL_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction." hexmask.long.byte 0x4 28.--31. 1. "PROXY_BYTEN,Byte enables to use for configuration read or write" hexmask.long.word 0x4 0.--15. 1. "PROXY_ADDRESS,Word (32-bit) address within thread configuration space for transaction" line.long 0x8 "VIRT_ALIAS_10_PSILCFG0__CFG__PROXY_PSIL_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction." hexmask.long 0x8 0.--31. 1. "PROXY_WDATA,Configuration data word to be written" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_10_PSILCFG0__CFG__PROXY_PSIL_RDATA,The Read Data Register contains the data which which was read back during the configuration transaction." hexmask.long 0x0 0.--31. 1. "PROXY_RDATA,Configuration data word that was read" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILCFG_0_VIRT_ALIAS_11_PSILCFG0_CFG_PROXY (NAVSS0_PSILCFG_0_VIRT_ALIAS_11_PSILCFG0_CFG_PROXY)" base ad:0x4BB1F78000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_PSILCFG0__CFG__PROXY_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_PSILCFG0__CFG__PROXY_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access. Once set this bit is persistent until manually cleared" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x100++0xB line.long 0x0 "VIRT_ALIAS_11_PSILCFG0__CFG__PROXY_PSIL_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction." bitfld.long 0x0 31. "PROXY_BUSY,Indication that a configuration read or write is in progress" "0,1" bitfld.long 0x0 30. "PROXY_DIR,Direction of configuration transaction" "0,1" bitfld.long 0x0 29. "PROXY_TOUT,Indication that a timeout occurred. This bit should be written to 0 on each new transaction." "0,1" hexmask.long.word 0x0 0.--15. 1. "PROXY_THREAD_ID,Thread ID to which configuration read or write is being sent" line.long 0x4 "VIRT_ALIAS_11_PSILCFG0__CFG__PROXY_PSIL_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction." hexmask.long.byte 0x4 28.--31. 1. "PROXY_BYTEN,Byte enables to use for configuration read or write" hexmask.long.word 0x4 0.--15. 1. "PROXY_ADDRESS,Word (32-bit) address within thread configuration space for transaction" line.long 0x8 "VIRT_ALIAS_11_PSILCFG0__CFG__PROXY_PSIL_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction." hexmask.long 0x8 0.--31. 1. "PROXY_WDATA,Configuration data word to be written" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_11_PSILCFG0__CFG__PROXY_PSIL_RDATA,The Read Data Register contains the data which which was read back during the configuration transaction." hexmask.long 0x0 0.--31. 1. "PROXY_RDATA,Configuration data word that was read" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILCFG_0_VIRT_ALIAS_12_PSILCFG0_CFG_PROXY (NAVSS0_PSILCFG_0_VIRT_ALIAS_12_PSILCFG0_CFG_PROXY)" base ad:0x4BC1F78000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_PSILCFG0__CFG__PROXY_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_PSILCFG0__CFG__PROXY_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access. Once set this bit is persistent until manually cleared" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x100++0xB line.long 0x0 "VIRT_ALIAS_12_PSILCFG0__CFG__PROXY_PSIL_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction." bitfld.long 0x0 31. "PROXY_BUSY,Indication that a configuration read or write is in progress" "0,1" bitfld.long 0x0 30. "PROXY_DIR,Direction of configuration transaction" "0,1" bitfld.long 0x0 29. "PROXY_TOUT,Indication that a timeout occurred. This bit should be written to 0 on each new transaction." "0,1" hexmask.long.word 0x0 0.--15. 1. "PROXY_THREAD_ID,Thread ID to which configuration read or write is being sent" line.long 0x4 "VIRT_ALIAS_12_PSILCFG0__CFG__PROXY_PSIL_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction." hexmask.long.byte 0x4 28.--31. 1. "PROXY_BYTEN,Byte enables to use for configuration read or write" hexmask.long.word 0x4 0.--15. 1. "PROXY_ADDRESS,Word (32-bit) address within thread configuration space for transaction" line.long 0x8 "VIRT_ALIAS_12_PSILCFG0__CFG__PROXY_PSIL_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction." hexmask.long 0x8 0.--31. 1. "PROXY_WDATA,Configuration data word to be written" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_12_PSILCFG0__CFG__PROXY_PSIL_RDATA,The Read Data Register contains the data which which was read back during the configuration transaction." hexmask.long 0x0 0.--31. 1. "PROXY_RDATA,Configuration data word that was read" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILCFG_0_VIRT_ALIAS_13_PSILCFG0_CFG_PROXY (NAVSS0_PSILCFG_0_VIRT_ALIAS_13_PSILCFG0_CFG_PROXY)" base ad:0x4BD1F78000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_PSILCFG0__CFG__PROXY_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_PSILCFG0__CFG__PROXY_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access. Once set this bit is persistent until manually cleared" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x100++0xB line.long 0x0 "VIRT_ALIAS_13_PSILCFG0__CFG__PROXY_PSIL_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction." bitfld.long 0x0 31. "PROXY_BUSY,Indication that a configuration read or write is in progress" "0,1" bitfld.long 0x0 30. "PROXY_DIR,Direction of configuration transaction" "0,1" bitfld.long 0x0 29. "PROXY_TOUT,Indication that a timeout occurred. This bit should be written to 0 on each new transaction." "0,1" hexmask.long.word 0x0 0.--15. 1. "PROXY_THREAD_ID,Thread ID to which configuration read or write is being sent" line.long 0x4 "VIRT_ALIAS_13_PSILCFG0__CFG__PROXY_PSIL_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction." hexmask.long.byte 0x4 28.--31. 1. "PROXY_BYTEN,Byte enables to use for configuration read or write" hexmask.long.word 0x4 0.--15. 1. "PROXY_ADDRESS,Word (32-bit) address within thread configuration space for transaction" line.long 0x8 "VIRT_ALIAS_13_PSILCFG0__CFG__PROXY_PSIL_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction." hexmask.long 0x8 0.--31. 1. "PROXY_WDATA,Configuration data word to be written" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_13_PSILCFG0__CFG__PROXY_PSIL_RDATA,The Read Data Register contains the data which which was read back during the configuration transaction." hexmask.long 0x0 0.--31. 1. "PROXY_RDATA,Configuration data word that was read" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILCFG_0_VIRT_ALIAS_14_PSILCFG0_CFG_PROXY (NAVSS0_PSILCFG_0_VIRT_ALIAS_14_PSILCFG0_CFG_PROXY)" base ad:0x4BE1F78000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_PSILCFG0__CFG__PROXY_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_PSILCFG0__CFG__PROXY_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access. Once set this bit is persistent until manually cleared" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x100++0xB line.long 0x0 "VIRT_ALIAS_14_PSILCFG0__CFG__PROXY_PSIL_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction." bitfld.long 0x0 31. "PROXY_BUSY,Indication that a configuration read or write is in progress" "0,1" bitfld.long 0x0 30. "PROXY_DIR,Direction of configuration transaction" "0,1" bitfld.long 0x0 29. "PROXY_TOUT,Indication that a timeout occurred. This bit should be written to 0 on each new transaction." "0,1" hexmask.long.word 0x0 0.--15. 1. "PROXY_THREAD_ID,Thread ID to which configuration read or write is being sent" line.long 0x4 "VIRT_ALIAS_14_PSILCFG0__CFG__PROXY_PSIL_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction." hexmask.long.byte 0x4 28.--31. 1. "PROXY_BYTEN,Byte enables to use for configuration read or write" hexmask.long.word 0x4 0.--15. 1. "PROXY_ADDRESS,Word (32-bit) address within thread configuration space for transaction" line.long 0x8 "VIRT_ALIAS_14_PSILCFG0__CFG__PROXY_PSIL_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction." hexmask.long 0x8 0.--31. 1. "PROXY_WDATA,Configuration data word to be written" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_14_PSILCFG0__CFG__PROXY_PSIL_RDATA,The Read Data Register contains the data which which was read back during the configuration transaction." hexmask.long 0x0 0.--31. 1. "PROXY_RDATA,Configuration data word that was read" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILCFG_0_VIRT_ALIAS_15_PSILCFG0_CFG_PROXY (NAVSS0_PSILCFG_0_VIRT_ALIAS_15_PSILCFG0_CFG_PROXY)" base ad:0x4BF1F78000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_PSILCFG0__CFG__PROXY_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_PSILCFG0__CFG__PROXY_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access. Once set this bit is persistent until manually cleared" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x100++0xB line.long 0x0 "VIRT_ALIAS_15_PSILCFG0__CFG__PROXY_PSIL_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction." bitfld.long 0x0 31. "PROXY_BUSY,Indication that a configuration read or write is in progress" "0,1" bitfld.long 0x0 30. "PROXY_DIR,Direction of configuration transaction" "0,1" bitfld.long 0x0 29. "PROXY_TOUT,Indication that a timeout occurred. This bit should be written to 0 on each new transaction." "0,1" hexmask.long.word 0x0 0.--15. 1. "PROXY_THREAD_ID,Thread ID to which configuration read or write is being sent" line.long 0x4 "VIRT_ALIAS_15_PSILCFG0__CFG__PROXY_PSIL_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction." hexmask.long.byte 0x4 28.--31. 1. "PROXY_BYTEN,Byte enables to use for configuration read or write" hexmask.long.word 0x4 0.--15. 1. "PROXY_ADDRESS,Word (32-bit) address within thread configuration space for transaction" line.long 0x8 "VIRT_ALIAS_15_PSILCFG0__CFG__PROXY_PSIL_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction." hexmask.long 0x8 0.--31. 1. "PROXY_WDATA,Configuration data word to be written" rgroup.long 0x140++0x3 line.long 0x0 "VIRT_ALIAS_15_PSILCFG0__CFG__PROXY_PSIL_RDATA,The Read Data Register contains the data which which was read back during the configuration transaction." hexmask.long 0x0 0.--31. 1. "PROXY_RDATA,Configuration data word that was read" tree.end endif tree.end tree.end tree "NAVSS0_PSILSS_0" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILSS_0_PSILSS0_CFG_MMRS (NAVSS0_PSILSS_0_PSILSS0_CFG_MMRS)" base ad:0x31170000 rgroup.long 0x0++0x7 line.long 0x0 "PSILSS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "PSILSS0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." rgroup.long 0x10++0x3 line.long 0x0 "PSILSS0__CFG__MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "PSILSS0__CFG__MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." rgroup.long 0x40++0x3 line.long 0x0 "PSILSS0__CFG__MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end endif tree "NAVSS0_PSILSS_0_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILSS_0_VIRT_ALIAS_0_PSILSS0_CFG_MMRS (NAVSS0_PSILSS_0_VIRT_ALIAS_0_PSILSS0_CFG_MMRS)" base ad:0x4B01170000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_0_PSILSS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_0_PSILSS0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_PSILSS0__CFG__MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_0_PSILSS0__CFG__MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_PSILSS0__CFG__MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILSS_0_VIRT_ALIAS_1_PSILSS0_CFG_MMRS (NAVSS0_PSILSS_0_VIRT_ALIAS_1_PSILSS0_CFG_MMRS)" base ad:0x4B11170000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_1_PSILSS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_1_PSILSS0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_PSILSS0__CFG__MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_1_PSILSS0__CFG__MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_PSILSS0__CFG__MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILSS_0_VIRT_ALIAS_2_PSILSS0_CFG_MMRS (NAVSS0_PSILSS_0_VIRT_ALIAS_2_PSILSS0_CFG_MMRS)" base ad:0x4B21170000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_2_PSILSS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_2_PSILSS0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_PSILSS0__CFG__MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_2_PSILSS0__CFG__MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_PSILSS0__CFG__MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILSS_0_VIRT_ALIAS_3_PSILSS0_CFG_MMRS (NAVSS0_PSILSS_0_VIRT_ALIAS_3_PSILSS0_CFG_MMRS)" base ad:0x4B31170000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_3_PSILSS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_3_PSILSS0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_PSILSS0__CFG__MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_3_PSILSS0__CFG__MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_PSILSS0__CFG__MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILSS_0_VIRT_ALIAS_4_PSILSS0_CFG_MMRS (NAVSS0_PSILSS_0_VIRT_ALIAS_4_PSILSS0_CFG_MMRS)" base ad:0x4B41170000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_4_PSILSS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_4_PSILSS0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_PSILSS0__CFG__MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_4_PSILSS0__CFG__MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_PSILSS0__CFG__MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILSS_0_VIRT_ALIAS_5_PSILSS0_CFG_MMRS (NAVSS0_PSILSS_0_VIRT_ALIAS_5_PSILSS0_CFG_MMRS)" base ad:0x4B51170000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_5_PSILSS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_5_PSILSS0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_PSILSS0__CFG__MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_5_PSILSS0__CFG__MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_PSILSS0__CFG__MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILSS_0_VIRT_ALIAS_6_PSILSS0_CFG_MMRS (NAVSS0_PSILSS_0_VIRT_ALIAS_6_PSILSS0_CFG_MMRS)" base ad:0x4B61170000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_6_PSILSS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_6_PSILSS0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_PSILSS0__CFG__MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_6_PSILSS0__CFG__MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_PSILSS0__CFG__MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILSS_0_VIRT_ALIAS_7_PSILSS0_CFG_MMRS (NAVSS0_PSILSS_0_VIRT_ALIAS_7_PSILSS0_CFG_MMRS)" base ad:0x4B71170000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_7_PSILSS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_7_PSILSS0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_PSILSS0__CFG__MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_7_PSILSS0__CFG__MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_PSILSS0__CFG__MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILSS_0_VIRT_ALIAS_8_PSILSS0_CFG_MMRS (NAVSS0_PSILSS_0_VIRT_ALIAS_8_PSILSS0_CFG_MMRS)" base ad:0x4B81170000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_8_PSILSS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_8_PSILSS0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_PSILSS0__CFG__MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_8_PSILSS0__CFG__MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_PSILSS0__CFG__MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILSS_0_VIRT_ALIAS_9_PSILSS0_CFG_MMRS (NAVSS0_PSILSS_0_VIRT_ALIAS_9_PSILSS0_CFG_MMRS)" base ad:0x4B91170000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_9_PSILSS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_9_PSILSS0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_PSILSS0__CFG__MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_9_PSILSS0__CFG__MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_PSILSS0__CFG__MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILSS_0_VIRT_ALIAS_10_PSILSS0_CFG_MMRS (NAVSS0_PSILSS_0_VIRT_ALIAS_10_PSILSS0_CFG_MMRS)" base ad:0x4BA1170000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_10_PSILSS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_10_PSILSS0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_PSILSS0__CFG__MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_10_PSILSS0__CFG__MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_PSILSS0__CFG__MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILSS_0_VIRT_ALIAS_11_PSILSS0_CFG_MMRS (NAVSS0_PSILSS_0_VIRT_ALIAS_11_PSILSS0_CFG_MMRS)" base ad:0x4BB1170000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_11_PSILSS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_11_PSILSS0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_PSILSS0__CFG__MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_11_PSILSS0__CFG__MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_PSILSS0__CFG__MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILSS_0_VIRT_ALIAS_12_PSILSS0_CFG_MMRS (NAVSS0_PSILSS_0_VIRT_ALIAS_12_PSILSS0_CFG_MMRS)" base ad:0x4BC1170000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_12_PSILSS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_12_PSILSS0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_PSILSS0__CFG__MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_12_PSILSS0__CFG__MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_PSILSS0__CFG__MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILSS_0_VIRT_ALIAS_13_PSILSS0_CFG_MMRS (NAVSS0_PSILSS_0_VIRT_ALIAS_13_PSILSS0_CFG_MMRS)" base ad:0x4BD1170000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_13_PSILSS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_13_PSILSS0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_PSILSS0__CFG__MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_13_PSILSS0__CFG__MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_PSILSS0__CFG__MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILSS_0_VIRT_ALIAS_14_PSILSS0_CFG_MMRS (NAVSS0_PSILSS_0_VIRT_ALIAS_14_PSILSS0_CFG_MMRS)" base ad:0x4BE1170000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_14_PSILSS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_14_PSILSS0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_PSILSS0__CFG__MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_14_PSILSS0__CFG__MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_PSILSS0__CFG__MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PSILSS_0_VIRT_ALIAS_15_PSILSS0_CFG_MMRS (NAVSS0_PSILSS_0_VIRT_ALIAS_15_PSILSS0_CFG_MMRS)" base ad:0x4BF1170000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_15_PSILSS0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_15_PSILSS0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_PSILSS0__CFG__MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_15_PSILSS0__CFG__MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_PSILSS0__CFG__MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end endif tree.end tree.end tree "NAVSS0_PVU" tree "NAVSS0_PVU_0" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_ALIAS64K_IO_PVU0_CFG_TLBIF_TLB (NAVSS0_PVU_0_ALIAS64K_IO_PVU0_CFG_TLBIF_TLB)" base ad:0x4A60000000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_IO_PVU0_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "ALIAS64K_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "ALIAS64K_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "ALIAS64K_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "ALIAS64K_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "ALIAS64K_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "ALIAS64K_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif tree "NAVSS0_PVU_0_IO" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_IO_PVU0_CFG_MMRS (NAVSS0_PVU_0_IO_PVU0_CFG_MMRS)" base ad:0x30F80000 rgroup.long 0x0++0x7 line.long 0x0 "IO_PVU0_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "IO_PVU0_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "IO_PVU0_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "IO_PVU0_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "IO_PVU0_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "IO_PVU0_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "IO_PVU0_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "IO_PVU0_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "IO_PVU0_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "IO_PVU0_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "IO_PVU0_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "IO_PVU0_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "IO_PVU0_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "IO_PVU0_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "IO_PVU0_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "IO_PVU0_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "IO_PVU0_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "IO_PVU0_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "IO_PVU0_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_IO_PVU0_CFG_TLBIF_TLB (NAVSS0_PVU_0_IO_PVU0_CFG_TLBIF_TLB)" base ad:0x36000000 rgroup.long 0x0++0x3 line.long 0x0 "IO_PVU0_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif tree.end tree "NAVSS0_PVU_0_PVU0" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_PVU0_SRC_TOG_CFG (NAVSS0_PVU_0_PVU0_SRC_TOG_CFG)" base ad:0x30F90000 rgroup.long 0x0++0xB line.long 0x0 "PVU0_SRC_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "PVU0_SRC_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "PVU0_SRC_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "PVU0_SRC_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "PVU0_SRC_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "PVU0_SRC_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "PVU0_SRC_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "PVU0_SRC_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "PVU0_SRC_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "PVU0_SRC_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "PVU0_SRC_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "PVU0_SRC_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "PVU0_SRC_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "PVU0_SRC_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "PVU0_SRC_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "PVU0_SRC_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "PVU0_SRC_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "PVU0_SRC_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_PVU0_CFG_TOG_CFG (NAVSS0_PVU_0_PVU0_CFG_TOG_CFG)" base ad:0x30F91000 rgroup.long 0x0++0xB line.long 0x0 "PVU0_CFG_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "PVU0_CFG_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "PVU0_CFG_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "PVU0_CFG_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "PVU0_CFG_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "PVU0_CFG_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "PVU0_CFG_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "PVU0_CFG_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "PVU0_CFG_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "PVU0_CFG_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "PVU0_CFG_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "PVU0_CFG_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "PVU0_CFG_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "PVU0_CFG_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "PVU0_CFG_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "PVU0_CFG_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "PVU0_CFG_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "PVU0_CFG_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif tree.end tree "NAVSS0_PVU_0_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_0_IO_PVU0_CFG_MMRS (NAVSS0_PVU_0_VIRT_ALIAS_0_IO_PVU0_CFG_MMRS)" base ad:0x4B00F80000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_0_IO_PVU0_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_0_IO_PVU0_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_0_IO_PVU0_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_0_IO_PVU0_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_0_IO_PVU0_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_0_IO_PVU0_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_0_IO_PVU0_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_0_IO_PVU0_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_0_IO_PVU0_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_0_IO_PVU0_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_0_IO_PVU0_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_0_IO_PVU0_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_0_IO_PVU0_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_0_IO_PVU0_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_0_IO_PVU0_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_0_IO_PVU0_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_0_IO_PVU0_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_0_IO_PVU0_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_0_IO_PVU0_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_0_PVU0_SRC_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_0_PVU0_SRC_TOG_CFG)" base ad:0x4B00F90000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_0_PVU0_SRC_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_0_PVU0_SRC_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_0_PVU0_SRC_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_0_PVU0_SRC_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_0_PVU0_SRC_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_0_PVU0_SRC_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_0_PVU0_SRC_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_0_PVU0_SRC_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_0_PVU0_SRC_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_0_PVU0_SRC_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_0_PVU0_SRC_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_0_PVU0_SRC_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_0_PVU0_SRC_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_0_PVU0_SRC_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_0_PVU0_SRC_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_0_PVU0_SRC_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_0_PVU0_SRC_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_0_PVU0_SRC_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_0_PVU0_CFG_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_0_PVU0_CFG_TOG_CFG)" base ad:0x4B00F91000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_0_PVU0_CFG_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_0_PVU0_CFG_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_0_PVU0_CFG_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_0_PVU0_CFG_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_0_PVU0_CFG_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_0_PVU0_CFG_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_0_PVU0_CFG_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_0_PVU0_CFG_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_0_PVU0_CFG_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_0_PVU0_CFG_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_0_PVU0_CFG_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_0_PVU0_CFG_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_0_PVU0_CFG_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_0_PVU0_CFG_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_0_PVU0_CFG_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_0_PVU0_CFG_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_0_PVU0_CFG_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_0_PVU0_CFG_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_0_IO_PVU0_CFG_TLBIF_TLB (NAVSS0_PVU_0_VIRT_ALIAS_0_IO_PVU0_CFG_TLBIF_TLB)" base ad:0x4B06000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_IO_PVU0_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_0_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_0_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_0_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_0_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_0_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_0_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_1_IO_PVU0_CFG_MMRS (NAVSS0_PVU_0_VIRT_ALIAS_1_IO_PVU0_CFG_MMRS)" base ad:0x4B10F80000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_1_IO_PVU0_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_1_IO_PVU0_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_1_IO_PVU0_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_1_IO_PVU0_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_1_IO_PVU0_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_1_IO_PVU0_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_1_IO_PVU0_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_1_IO_PVU0_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_1_IO_PVU0_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_1_IO_PVU0_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_1_IO_PVU0_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_1_IO_PVU0_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_1_IO_PVU0_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_1_IO_PVU0_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_1_IO_PVU0_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_1_IO_PVU0_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_1_IO_PVU0_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_1_IO_PVU0_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_1_IO_PVU0_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_1_PVU0_SRC_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_1_PVU0_SRC_TOG_CFG)" base ad:0x4B10F90000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_1_PVU0_SRC_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_1_PVU0_SRC_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_1_PVU0_SRC_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_1_PVU0_SRC_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_1_PVU0_SRC_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_1_PVU0_SRC_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_1_PVU0_SRC_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_1_PVU0_SRC_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_1_PVU0_SRC_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_1_PVU0_SRC_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_1_PVU0_SRC_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_1_PVU0_SRC_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_1_PVU0_SRC_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_1_PVU0_SRC_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_1_PVU0_SRC_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_1_PVU0_SRC_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_1_PVU0_SRC_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_1_PVU0_SRC_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_1_PVU0_CFG_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_1_PVU0_CFG_TOG_CFG)" base ad:0x4B10F91000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_1_PVU0_CFG_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_1_PVU0_CFG_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_1_PVU0_CFG_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_1_PVU0_CFG_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_1_PVU0_CFG_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_1_PVU0_CFG_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_1_PVU0_CFG_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_1_PVU0_CFG_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_1_PVU0_CFG_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_1_PVU0_CFG_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_1_PVU0_CFG_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_1_PVU0_CFG_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_1_PVU0_CFG_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_1_PVU0_CFG_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_1_PVU0_CFG_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_1_PVU0_CFG_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_1_PVU0_CFG_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_1_PVU0_CFG_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_1_IO_PVU0_CFG_TLBIF_TLB (NAVSS0_PVU_0_VIRT_ALIAS_1_IO_PVU0_CFG_TLBIF_TLB)" base ad:0x4B16000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_IO_PVU0_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_1_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_1_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_1_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_1_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_1_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_1_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_2_IO_PVU0_CFG_MMRS (NAVSS0_PVU_0_VIRT_ALIAS_2_IO_PVU0_CFG_MMRS)" base ad:0x4B20F80000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_2_IO_PVU0_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_2_IO_PVU0_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_2_IO_PVU0_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_2_IO_PVU0_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_2_IO_PVU0_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_2_IO_PVU0_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_2_IO_PVU0_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_2_IO_PVU0_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_2_IO_PVU0_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_2_IO_PVU0_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_2_IO_PVU0_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_2_IO_PVU0_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_2_IO_PVU0_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_2_IO_PVU0_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_2_IO_PVU0_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_2_IO_PVU0_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_2_IO_PVU0_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_2_IO_PVU0_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_2_IO_PVU0_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_2_PVU0_SRC_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_2_PVU0_SRC_TOG_CFG)" base ad:0x4B20F90000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_2_PVU0_SRC_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_2_PVU0_SRC_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_2_PVU0_SRC_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_2_PVU0_SRC_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_2_PVU0_SRC_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_2_PVU0_SRC_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_2_PVU0_SRC_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_2_PVU0_SRC_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_2_PVU0_SRC_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_2_PVU0_SRC_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_2_PVU0_SRC_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_2_PVU0_SRC_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_2_PVU0_SRC_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_2_PVU0_SRC_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_2_PVU0_SRC_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_2_PVU0_SRC_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_2_PVU0_SRC_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_2_PVU0_SRC_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_2_PVU0_CFG_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_2_PVU0_CFG_TOG_CFG)" base ad:0x4B20F91000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_2_PVU0_CFG_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_2_PVU0_CFG_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_2_PVU0_CFG_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_2_PVU0_CFG_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_2_PVU0_CFG_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_2_PVU0_CFG_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_2_PVU0_CFG_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_2_PVU0_CFG_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_2_PVU0_CFG_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_2_PVU0_CFG_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_2_PVU0_CFG_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_2_PVU0_CFG_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_2_PVU0_CFG_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_2_PVU0_CFG_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_2_PVU0_CFG_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_2_PVU0_CFG_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_2_PVU0_CFG_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_2_PVU0_CFG_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_2_IO_PVU0_CFG_TLBIF_TLB (NAVSS0_PVU_0_VIRT_ALIAS_2_IO_PVU0_CFG_TLBIF_TLB)" base ad:0x4B26000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_IO_PVU0_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_2_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_2_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_2_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_2_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_2_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_2_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_3_IO_PVU0_CFG_MMRS (NAVSS0_PVU_0_VIRT_ALIAS_3_IO_PVU0_CFG_MMRS)" base ad:0x4B30F80000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_3_IO_PVU0_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_3_IO_PVU0_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_3_IO_PVU0_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_3_IO_PVU0_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_3_IO_PVU0_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_3_IO_PVU0_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_3_IO_PVU0_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_3_IO_PVU0_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_3_IO_PVU0_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_3_IO_PVU0_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_3_IO_PVU0_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_3_IO_PVU0_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_3_IO_PVU0_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_3_IO_PVU0_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_3_IO_PVU0_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_3_IO_PVU0_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_3_IO_PVU0_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_3_IO_PVU0_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_3_IO_PVU0_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_3_PVU0_SRC_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_3_PVU0_SRC_TOG_CFG)" base ad:0x4B30F90000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_3_PVU0_SRC_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_3_PVU0_SRC_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_3_PVU0_SRC_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_3_PVU0_SRC_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_3_PVU0_SRC_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_3_PVU0_SRC_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_3_PVU0_SRC_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_3_PVU0_SRC_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_3_PVU0_SRC_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_3_PVU0_SRC_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_3_PVU0_SRC_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_3_PVU0_SRC_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_3_PVU0_SRC_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_3_PVU0_SRC_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_3_PVU0_SRC_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_3_PVU0_SRC_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_3_PVU0_SRC_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_3_PVU0_SRC_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_3_PVU0_CFG_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_3_PVU0_CFG_TOG_CFG)" base ad:0x4B30F91000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_3_PVU0_CFG_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_3_PVU0_CFG_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_3_PVU0_CFG_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_3_PVU0_CFG_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_3_PVU0_CFG_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_3_PVU0_CFG_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_3_PVU0_CFG_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_3_PVU0_CFG_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_3_PVU0_CFG_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_3_PVU0_CFG_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_3_PVU0_CFG_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_3_PVU0_CFG_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_3_PVU0_CFG_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_3_PVU0_CFG_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_3_PVU0_CFG_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_3_PVU0_CFG_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_3_PVU0_CFG_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_3_PVU0_CFG_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_3_IO_PVU0_CFG_TLBIF_TLB (NAVSS0_PVU_0_VIRT_ALIAS_3_IO_PVU0_CFG_TLBIF_TLB)" base ad:0x4B36000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_IO_PVU0_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_3_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_3_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_3_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_3_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_3_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_3_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_4_IO_PVU0_CFG_MMRS (NAVSS0_PVU_0_VIRT_ALIAS_4_IO_PVU0_CFG_MMRS)" base ad:0x4B40F80000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_4_IO_PVU0_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_4_IO_PVU0_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_4_IO_PVU0_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_4_IO_PVU0_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_4_IO_PVU0_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_4_IO_PVU0_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_4_IO_PVU0_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_4_IO_PVU0_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_4_IO_PVU0_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_4_IO_PVU0_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_4_IO_PVU0_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_4_IO_PVU0_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_4_IO_PVU0_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_4_IO_PVU0_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_4_IO_PVU0_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_4_IO_PVU0_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_4_IO_PVU0_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_4_IO_PVU0_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_4_IO_PVU0_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_4_PVU0_SRC_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_4_PVU0_SRC_TOG_CFG)" base ad:0x4B40F90000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_4_PVU0_SRC_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_4_PVU0_SRC_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_4_PVU0_SRC_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_4_PVU0_SRC_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_4_PVU0_SRC_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_4_PVU0_SRC_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_4_PVU0_SRC_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_4_PVU0_SRC_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_4_PVU0_SRC_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_4_PVU0_SRC_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_4_PVU0_SRC_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_4_PVU0_SRC_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_4_PVU0_SRC_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_4_PVU0_SRC_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_4_PVU0_SRC_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_4_PVU0_SRC_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_4_PVU0_SRC_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_4_PVU0_SRC_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_4_PVU0_CFG_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_4_PVU0_CFG_TOG_CFG)" base ad:0x4B40F91000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_4_PVU0_CFG_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_4_PVU0_CFG_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_4_PVU0_CFG_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_4_PVU0_CFG_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_4_PVU0_CFG_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_4_PVU0_CFG_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_4_PVU0_CFG_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_4_PVU0_CFG_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_4_PVU0_CFG_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_4_PVU0_CFG_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_4_PVU0_CFG_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_4_PVU0_CFG_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_4_PVU0_CFG_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_4_PVU0_CFG_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_4_PVU0_CFG_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_4_PVU0_CFG_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_4_PVU0_CFG_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_4_PVU0_CFG_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_4_IO_PVU0_CFG_TLBIF_TLB (NAVSS0_PVU_0_VIRT_ALIAS_4_IO_PVU0_CFG_TLBIF_TLB)" base ad:0x4B46000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_IO_PVU0_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_4_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_4_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_4_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_4_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_4_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_4_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_5_IO_PVU0_CFG_MMRS (NAVSS0_PVU_0_VIRT_ALIAS_5_IO_PVU0_CFG_MMRS)" base ad:0x4B50F80000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_5_IO_PVU0_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_5_IO_PVU0_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_5_IO_PVU0_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_5_IO_PVU0_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_5_IO_PVU0_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_5_IO_PVU0_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_5_IO_PVU0_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_5_IO_PVU0_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_5_IO_PVU0_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_5_IO_PVU0_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_5_IO_PVU0_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_5_IO_PVU0_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_5_IO_PVU0_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_5_IO_PVU0_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_5_IO_PVU0_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_5_IO_PVU0_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_5_IO_PVU0_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_5_IO_PVU0_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_5_IO_PVU0_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_5_PVU0_SRC_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_5_PVU0_SRC_TOG_CFG)" base ad:0x4B50F90000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_5_PVU0_SRC_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_5_PVU0_SRC_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_5_PVU0_SRC_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_5_PVU0_SRC_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_5_PVU0_SRC_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_5_PVU0_SRC_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_5_PVU0_SRC_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_5_PVU0_SRC_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_5_PVU0_SRC_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_5_PVU0_SRC_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_5_PVU0_SRC_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_5_PVU0_SRC_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_5_PVU0_SRC_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_5_PVU0_SRC_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_5_PVU0_SRC_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_5_PVU0_SRC_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_5_PVU0_SRC_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_5_PVU0_SRC_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_5_PVU0_CFG_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_5_PVU0_CFG_TOG_CFG)" base ad:0x4B50F91000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_5_PVU0_CFG_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_5_PVU0_CFG_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_5_PVU0_CFG_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_5_PVU0_CFG_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_5_PVU0_CFG_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_5_PVU0_CFG_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_5_PVU0_CFG_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_5_PVU0_CFG_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_5_PVU0_CFG_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_5_PVU0_CFG_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_5_PVU0_CFG_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_5_PVU0_CFG_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_5_PVU0_CFG_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_5_PVU0_CFG_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_5_PVU0_CFG_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_5_PVU0_CFG_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_5_PVU0_CFG_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_5_PVU0_CFG_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_5_IO_PVU0_CFG_TLBIF_TLB (NAVSS0_PVU_0_VIRT_ALIAS_5_IO_PVU0_CFG_TLBIF_TLB)" base ad:0x4B56000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_IO_PVU0_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_5_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_5_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_5_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_5_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_5_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_5_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_6_IO_PVU0_CFG_MMRS (NAVSS0_PVU_0_VIRT_ALIAS_6_IO_PVU0_CFG_MMRS)" base ad:0x4B60F80000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_6_IO_PVU0_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_6_IO_PVU0_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_6_IO_PVU0_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_6_IO_PVU0_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_6_IO_PVU0_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_6_IO_PVU0_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_6_IO_PVU0_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_6_IO_PVU0_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_6_IO_PVU0_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_6_IO_PVU0_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_6_IO_PVU0_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_6_IO_PVU0_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_6_IO_PVU0_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_6_IO_PVU0_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_6_IO_PVU0_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_6_IO_PVU0_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_6_IO_PVU0_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_6_IO_PVU0_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_6_IO_PVU0_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_6_PVU0_SRC_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_6_PVU0_SRC_TOG_CFG)" base ad:0x4B60F90000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_6_PVU0_SRC_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_6_PVU0_SRC_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_6_PVU0_SRC_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_6_PVU0_SRC_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_6_PVU0_SRC_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_6_PVU0_SRC_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_6_PVU0_SRC_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_6_PVU0_SRC_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_6_PVU0_SRC_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_6_PVU0_SRC_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_6_PVU0_SRC_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_6_PVU0_SRC_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_6_PVU0_SRC_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_6_PVU0_SRC_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_6_PVU0_SRC_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_6_PVU0_SRC_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_6_PVU0_SRC_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_6_PVU0_SRC_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_6_PVU0_CFG_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_6_PVU0_CFG_TOG_CFG)" base ad:0x4B60F91000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_6_PVU0_CFG_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_6_PVU0_CFG_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_6_PVU0_CFG_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_6_PVU0_CFG_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_6_PVU0_CFG_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_6_PVU0_CFG_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_6_PVU0_CFG_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_6_PVU0_CFG_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_6_PVU0_CFG_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_6_PVU0_CFG_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_6_PVU0_CFG_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_6_PVU0_CFG_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_6_PVU0_CFG_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_6_PVU0_CFG_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_6_PVU0_CFG_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_6_PVU0_CFG_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_6_PVU0_CFG_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_6_PVU0_CFG_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_6_IO_PVU0_CFG_TLBIF_TLB (NAVSS0_PVU_0_VIRT_ALIAS_6_IO_PVU0_CFG_TLBIF_TLB)" base ad:0x4B66000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_IO_PVU0_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_6_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_6_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_6_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_6_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_6_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_6_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_7_IO_PVU0_CFG_MMRS (NAVSS0_PVU_0_VIRT_ALIAS_7_IO_PVU0_CFG_MMRS)" base ad:0x4B70F80000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_7_IO_PVU0_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_7_IO_PVU0_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_7_IO_PVU0_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_7_IO_PVU0_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_7_IO_PVU0_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_7_IO_PVU0_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_7_IO_PVU0_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_7_IO_PVU0_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_7_IO_PVU0_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_7_IO_PVU0_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_7_IO_PVU0_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_7_IO_PVU0_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_7_IO_PVU0_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_7_IO_PVU0_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_7_IO_PVU0_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_7_IO_PVU0_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_7_IO_PVU0_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_7_IO_PVU0_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_7_IO_PVU0_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_7_PVU0_SRC_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_7_PVU0_SRC_TOG_CFG)" base ad:0x4B70F90000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_7_PVU0_SRC_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_7_PVU0_SRC_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_7_PVU0_SRC_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_7_PVU0_SRC_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_7_PVU0_SRC_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_7_PVU0_SRC_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_7_PVU0_SRC_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_7_PVU0_SRC_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_7_PVU0_SRC_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_7_PVU0_SRC_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_7_PVU0_SRC_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_7_PVU0_SRC_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_7_PVU0_SRC_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_7_PVU0_SRC_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_7_PVU0_SRC_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_7_PVU0_SRC_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_7_PVU0_SRC_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_7_PVU0_SRC_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_7_PVU0_CFG_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_7_PVU0_CFG_TOG_CFG)" base ad:0x4B70F91000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_7_PVU0_CFG_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_7_PVU0_CFG_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_7_PVU0_CFG_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_7_PVU0_CFG_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_7_PVU0_CFG_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_7_PVU0_CFG_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_7_PVU0_CFG_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_7_PVU0_CFG_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_7_PVU0_CFG_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_7_PVU0_CFG_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_7_PVU0_CFG_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_7_PVU0_CFG_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_7_PVU0_CFG_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_7_PVU0_CFG_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_7_PVU0_CFG_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_7_PVU0_CFG_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_7_PVU0_CFG_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_7_PVU0_CFG_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_7_IO_PVU0_CFG_TLBIF_TLB (NAVSS0_PVU_0_VIRT_ALIAS_7_IO_PVU0_CFG_TLBIF_TLB)" base ad:0x4B76000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_IO_PVU0_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_7_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_7_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_7_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_7_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_7_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_7_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_8_IO_PVU0_CFG_MMRS (NAVSS0_PVU_0_VIRT_ALIAS_8_IO_PVU0_CFG_MMRS)" base ad:0x4B80F80000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_8_IO_PVU0_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_8_IO_PVU0_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_8_IO_PVU0_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_8_IO_PVU0_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_8_IO_PVU0_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_8_IO_PVU0_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_8_IO_PVU0_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_8_IO_PVU0_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_8_IO_PVU0_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_8_IO_PVU0_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_8_IO_PVU0_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_8_IO_PVU0_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_8_IO_PVU0_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_8_IO_PVU0_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_8_IO_PVU0_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_8_IO_PVU0_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_8_IO_PVU0_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_8_IO_PVU0_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_8_IO_PVU0_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_8_PVU0_SRC_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_8_PVU0_SRC_TOG_CFG)" base ad:0x4B80F90000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_8_PVU0_SRC_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_8_PVU0_SRC_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_8_PVU0_SRC_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_8_PVU0_SRC_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_8_PVU0_SRC_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_8_PVU0_SRC_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_8_PVU0_SRC_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_8_PVU0_SRC_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_8_PVU0_SRC_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_8_PVU0_SRC_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_8_PVU0_SRC_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_8_PVU0_SRC_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_8_PVU0_SRC_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_8_PVU0_SRC_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_8_PVU0_SRC_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_8_PVU0_SRC_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_8_PVU0_SRC_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_8_PVU0_SRC_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_8_PVU0_CFG_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_8_PVU0_CFG_TOG_CFG)" base ad:0x4B80F91000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_8_PVU0_CFG_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_8_PVU0_CFG_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_8_PVU0_CFG_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_8_PVU0_CFG_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_8_PVU0_CFG_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_8_PVU0_CFG_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_8_PVU0_CFG_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_8_PVU0_CFG_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_8_PVU0_CFG_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_8_PVU0_CFG_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_8_PVU0_CFG_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_8_PVU0_CFG_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_8_PVU0_CFG_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_8_PVU0_CFG_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_8_PVU0_CFG_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_8_PVU0_CFG_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_8_PVU0_CFG_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_8_PVU0_CFG_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_8_IO_PVU0_CFG_TLBIF_TLB (NAVSS0_PVU_0_VIRT_ALIAS_8_IO_PVU0_CFG_TLBIF_TLB)" base ad:0x4B86000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_IO_PVU0_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_8_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_8_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_8_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_8_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_8_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_8_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_9_IO_PVU0_CFG_MMRS (NAVSS0_PVU_0_VIRT_ALIAS_9_IO_PVU0_CFG_MMRS)" base ad:0x4B90F80000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_9_IO_PVU0_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_9_IO_PVU0_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_9_IO_PVU0_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_9_IO_PVU0_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_9_IO_PVU0_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_9_IO_PVU0_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_9_IO_PVU0_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_9_IO_PVU0_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_9_IO_PVU0_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_9_IO_PVU0_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_9_IO_PVU0_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_9_IO_PVU0_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_9_IO_PVU0_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_9_IO_PVU0_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_9_IO_PVU0_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_9_IO_PVU0_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_9_IO_PVU0_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_9_IO_PVU0_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_9_IO_PVU0_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_9_PVU0_SRC_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_9_PVU0_SRC_TOG_CFG)" base ad:0x4B90F90000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_9_PVU0_SRC_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_9_PVU0_SRC_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_9_PVU0_SRC_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_9_PVU0_SRC_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_9_PVU0_SRC_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_9_PVU0_SRC_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_9_PVU0_SRC_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_9_PVU0_SRC_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_9_PVU0_SRC_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_9_PVU0_SRC_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_9_PVU0_SRC_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_9_PVU0_SRC_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_9_PVU0_SRC_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_9_PVU0_SRC_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_9_PVU0_SRC_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_9_PVU0_SRC_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_9_PVU0_SRC_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_9_PVU0_SRC_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_9_PVU0_CFG_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_9_PVU0_CFG_TOG_CFG)" base ad:0x4B90F91000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_9_PVU0_CFG_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_9_PVU0_CFG_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_9_PVU0_CFG_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_9_PVU0_CFG_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_9_PVU0_CFG_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_9_PVU0_CFG_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_9_PVU0_CFG_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_9_PVU0_CFG_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_9_PVU0_CFG_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_9_PVU0_CFG_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_9_PVU0_CFG_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_9_PVU0_CFG_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_9_PVU0_CFG_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_9_PVU0_CFG_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_9_PVU0_CFG_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_9_PVU0_CFG_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_9_PVU0_CFG_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_9_PVU0_CFG_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_9_IO_PVU0_CFG_TLBIF_TLB (NAVSS0_PVU_0_VIRT_ALIAS_9_IO_PVU0_CFG_TLBIF_TLB)" base ad:0x4B96000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_IO_PVU0_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_9_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_9_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_9_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_9_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_9_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_9_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_10_IO_PVU0_CFG_MMRS (NAVSS0_PVU_0_VIRT_ALIAS_10_IO_PVU0_CFG_MMRS)" base ad:0x4BA0F80000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_10_IO_PVU0_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_10_IO_PVU0_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_10_IO_PVU0_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_10_IO_PVU0_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_10_IO_PVU0_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_10_IO_PVU0_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_10_IO_PVU0_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_10_IO_PVU0_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_10_IO_PVU0_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_10_IO_PVU0_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_10_IO_PVU0_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_10_IO_PVU0_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_10_IO_PVU0_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_10_IO_PVU0_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_10_IO_PVU0_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_10_IO_PVU0_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_10_IO_PVU0_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_10_IO_PVU0_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_10_IO_PVU0_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_10_PVU0_SRC_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_10_PVU0_SRC_TOG_CFG)" base ad:0x4BA0F90000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_10_PVU0_SRC_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_10_PVU0_SRC_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_10_PVU0_SRC_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_10_PVU0_SRC_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_10_PVU0_SRC_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_10_PVU0_SRC_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_10_PVU0_SRC_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_10_PVU0_SRC_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_10_PVU0_SRC_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_10_PVU0_SRC_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_10_PVU0_SRC_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_10_PVU0_SRC_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_10_PVU0_SRC_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_10_PVU0_SRC_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_10_PVU0_SRC_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_10_PVU0_SRC_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_10_PVU0_SRC_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_10_PVU0_SRC_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_10_PVU0_CFG_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_10_PVU0_CFG_TOG_CFG)" base ad:0x4BA0F91000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_10_PVU0_CFG_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_10_PVU0_CFG_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_10_PVU0_CFG_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_10_PVU0_CFG_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_10_PVU0_CFG_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_10_PVU0_CFG_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_10_PVU0_CFG_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_10_PVU0_CFG_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_10_PVU0_CFG_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_10_PVU0_CFG_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_10_PVU0_CFG_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_10_PVU0_CFG_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_10_PVU0_CFG_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_10_PVU0_CFG_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_10_PVU0_CFG_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_10_PVU0_CFG_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_10_PVU0_CFG_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_10_PVU0_CFG_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_10_IO_PVU0_CFG_TLBIF_TLB (NAVSS0_PVU_0_VIRT_ALIAS_10_IO_PVU0_CFG_TLBIF_TLB)" base ad:0x4BA6000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_IO_PVU0_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_10_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_10_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_10_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_10_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_10_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_10_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_11_IO_PVU0_CFG_MMRS (NAVSS0_PVU_0_VIRT_ALIAS_11_IO_PVU0_CFG_MMRS)" base ad:0x4BB0F80000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_11_IO_PVU0_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_11_IO_PVU0_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_11_IO_PVU0_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_11_IO_PVU0_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_11_IO_PVU0_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_11_IO_PVU0_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_11_IO_PVU0_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_11_IO_PVU0_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_11_IO_PVU0_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_11_IO_PVU0_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_11_IO_PVU0_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_11_IO_PVU0_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_11_IO_PVU0_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_11_IO_PVU0_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_11_IO_PVU0_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_11_IO_PVU0_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_11_IO_PVU0_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_11_IO_PVU0_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_11_IO_PVU0_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_11_PVU0_SRC_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_11_PVU0_SRC_TOG_CFG)" base ad:0x4BB0F90000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_11_PVU0_SRC_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_11_PVU0_SRC_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_11_PVU0_SRC_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_11_PVU0_SRC_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_11_PVU0_SRC_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_11_PVU0_SRC_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_11_PVU0_SRC_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_11_PVU0_SRC_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_11_PVU0_SRC_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_11_PVU0_SRC_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_11_PVU0_SRC_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_11_PVU0_SRC_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_11_PVU0_SRC_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_11_PVU0_SRC_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_11_PVU0_SRC_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_11_PVU0_SRC_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_11_PVU0_SRC_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_11_PVU0_SRC_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_11_PVU0_CFG_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_11_PVU0_CFG_TOG_CFG)" base ad:0x4BB0F91000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_11_PVU0_CFG_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_11_PVU0_CFG_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_11_PVU0_CFG_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_11_PVU0_CFG_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_11_PVU0_CFG_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_11_PVU0_CFG_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_11_PVU0_CFG_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_11_PVU0_CFG_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_11_PVU0_CFG_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_11_PVU0_CFG_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_11_PVU0_CFG_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_11_PVU0_CFG_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_11_PVU0_CFG_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_11_PVU0_CFG_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_11_PVU0_CFG_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_11_PVU0_CFG_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_11_PVU0_CFG_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_11_PVU0_CFG_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_11_IO_PVU0_CFG_TLBIF_TLB (NAVSS0_PVU_0_VIRT_ALIAS_11_IO_PVU0_CFG_TLBIF_TLB)" base ad:0x4BB6000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_IO_PVU0_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_11_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_11_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_11_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_11_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_11_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_11_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_12_IO_PVU0_CFG_MMRS (NAVSS0_PVU_0_VIRT_ALIAS_12_IO_PVU0_CFG_MMRS)" base ad:0x4BC0F80000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_12_IO_PVU0_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_12_IO_PVU0_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_12_IO_PVU0_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_12_IO_PVU0_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_12_IO_PVU0_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_12_IO_PVU0_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_12_IO_PVU0_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_12_IO_PVU0_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_12_IO_PVU0_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_12_IO_PVU0_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_12_IO_PVU0_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_12_IO_PVU0_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_12_IO_PVU0_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_12_IO_PVU0_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_12_IO_PVU0_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_12_IO_PVU0_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_12_IO_PVU0_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_12_IO_PVU0_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_12_IO_PVU0_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_12_PVU0_SRC_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_12_PVU0_SRC_TOG_CFG)" base ad:0x4BC0F90000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_12_PVU0_SRC_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_12_PVU0_SRC_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_12_PVU0_SRC_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_12_PVU0_SRC_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_12_PVU0_SRC_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_12_PVU0_SRC_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_12_PVU0_SRC_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_12_PVU0_SRC_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_12_PVU0_SRC_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_12_PVU0_SRC_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_12_PVU0_SRC_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_12_PVU0_SRC_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_12_PVU0_SRC_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_12_PVU0_SRC_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_12_PVU0_SRC_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_12_PVU0_SRC_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_12_PVU0_SRC_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_12_PVU0_SRC_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_12_PVU0_CFG_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_12_PVU0_CFG_TOG_CFG)" base ad:0x4BC0F91000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_12_PVU0_CFG_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_12_PVU0_CFG_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_12_PVU0_CFG_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_12_PVU0_CFG_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_12_PVU0_CFG_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_12_PVU0_CFG_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_12_PVU0_CFG_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_12_PVU0_CFG_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_12_PVU0_CFG_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_12_PVU0_CFG_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_12_PVU0_CFG_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_12_PVU0_CFG_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_12_PVU0_CFG_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_12_PVU0_CFG_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_12_PVU0_CFG_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_12_PVU0_CFG_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_12_PVU0_CFG_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_12_PVU0_CFG_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_12_IO_PVU0_CFG_TLBIF_TLB (NAVSS0_PVU_0_VIRT_ALIAS_12_IO_PVU0_CFG_TLBIF_TLB)" base ad:0x4BC6000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_IO_PVU0_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_12_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_12_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_12_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_12_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_12_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_12_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_13_IO_PVU0_CFG_MMRS (NAVSS0_PVU_0_VIRT_ALIAS_13_IO_PVU0_CFG_MMRS)" base ad:0x4BD0F80000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_13_IO_PVU0_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_13_IO_PVU0_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_13_IO_PVU0_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_13_IO_PVU0_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_13_IO_PVU0_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_13_IO_PVU0_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_13_IO_PVU0_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_13_IO_PVU0_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_13_IO_PVU0_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_13_IO_PVU0_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_13_IO_PVU0_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_13_IO_PVU0_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_13_IO_PVU0_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_13_IO_PVU0_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_13_IO_PVU0_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_13_IO_PVU0_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_13_IO_PVU0_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_13_IO_PVU0_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_13_IO_PVU0_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_13_PVU0_SRC_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_13_PVU0_SRC_TOG_CFG)" base ad:0x4BD0F90000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_13_PVU0_SRC_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_13_PVU0_SRC_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_13_PVU0_SRC_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_13_PVU0_SRC_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_13_PVU0_SRC_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_13_PVU0_SRC_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_13_PVU0_SRC_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_13_PVU0_SRC_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_13_PVU0_SRC_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_13_PVU0_SRC_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_13_PVU0_SRC_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_13_PVU0_SRC_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_13_PVU0_SRC_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_13_PVU0_SRC_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_13_PVU0_SRC_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_13_PVU0_SRC_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_13_PVU0_SRC_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_13_PVU0_SRC_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_13_PVU0_CFG_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_13_PVU0_CFG_TOG_CFG)" base ad:0x4BD0F91000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_13_PVU0_CFG_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_13_PVU0_CFG_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_13_PVU0_CFG_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_13_PVU0_CFG_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_13_PVU0_CFG_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_13_PVU0_CFG_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_13_PVU0_CFG_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_13_PVU0_CFG_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_13_PVU0_CFG_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_13_PVU0_CFG_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_13_PVU0_CFG_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_13_PVU0_CFG_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_13_PVU0_CFG_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_13_PVU0_CFG_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_13_PVU0_CFG_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_13_PVU0_CFG_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_13_PVU0_CFG_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_13_PVU0_CFG_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_13_IO_PVU0_CFG_TLBIF_TLB (NAVSS0_PVU_0_VIRT_ALIAS_13_IO_PVU0_CFG_TLBIF_TLB)" base ad:0x4BD6000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_IO_PVU0_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_13_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_13_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_13_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_13_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_13_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_13_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_14_IO_PVU0_CFG_MMRS (NAVSS0_PVU_0_VIRT_ALIAS_14_IO_PVU0_CFG_MMRS)" base ad:0x4BE0F80000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_14_IO_PVU0_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_14_IO_PVU0_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_14_IO_PVU0_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_14_IO_PVU0_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_14_IO_PVU0_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_14_IO_PVU0_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_14_IO_PVU0_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_14_IO_PVU0_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_14_IO_PVU0_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_14_IO_PVU0_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_14_IO_PVU0_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_14_IO_PVU0_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_14_IO_PVU0_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_14_IO_PVU0_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_14_IO_PVU0_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_14_IO_PVU0_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_14_IO_PVU0_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_14_IO_PVU0_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_14_IO_PVU0_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_14_PVU0_SRC_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_14_PVU0_SRC_TOG_CFG)" base ad:0x4BE0F90000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_14_PVU0_SRC_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_14_PVU0_SRC_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_14_PVU0_SRC_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_14_PVU0_SRC_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_14_PVU0_SRC_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_14_PVU0_SRC_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_14_PVU0_SRC_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_14_PVU0_SRC_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_14_PVU0_SRC_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_14_PVU0_SRC_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_14_PVU0_SRC_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_14_PVU0_SRC_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_14_PVU0_SRC_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_14_PVU0_SRC_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_14_PVU0_SRC_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_14_PVU0_SRC_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_14_PVU0_SRC_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_14_PVU0_SRC_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_14_PVU0_CFG_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_14_PVU0_CFG_TOG_CFG)" base ad:0x4BE0F91000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_14_PVU0_CFG_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_14_PVU0_CFG_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_14_PVU0_CFG_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_14_PVU0_CFG_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_14_PVU0_CFG_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_14_PVU0_CFG_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_14_PVU0_CFG_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_14_PVU0_CFG_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_14_PVU0_CFG_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_14_PVU0_CFG_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_14_PVU0_CFG_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_14_PVU0_CFG_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_14_PVU0_CFG_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_14_PVU0_CFG_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_14_PVU0_CFG_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_14_PVU0_CFG_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_14_PVU0_CFG_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_14_PVU0_CFG_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_14_IO_PVU0_CFG_TLBIF_TLB (NAVSS0_PVU_0_VIRT_ALIAS_14_IO_PVU0_CFG_TLBIF_TLB)" base ad:0x4BE6000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_IO_PVU0_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_14_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_14_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_14_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_14_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_14_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_14_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_15_IO_PVU0_CFG_MMRS (NAVSS0_PVU_0_VIRT_ALIAS_15_IO_PVU0_CFG_MMRS)" base ad:0x4BF0F80000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_15_IO_PVU0_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_15_IO_PVU0_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_15_IO_PVU0_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_15_IO_PVU0_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_15_IO_PVU0_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_15_IO_PVU0_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_15_IO_PVU0_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_15_IO_PVU0_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_15_IO_PVU0_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_15_IO_PVU0_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_15_IO_PVU0_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_15_IO_PVU0_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_15_IO_PVU0_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_15_IO_PVU0_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_15_IO_PVU0_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_15_IO_PVU0_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_15_IO_PVU0_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_15_IO_PVU0_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_15_IO_PVU0_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_15_PVU0_SRC_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_15_PVU0_SRC_TOG_CFG)" base ad:0x4BF0F90000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_15_PVU0_SRC_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_15_PVU0_SRC_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_15_PVU0_SRC_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_15_PVU0_SRC_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_15_PVU0_SRC_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_15_PVU0_SRC_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_15_PVU0_SRC_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_15_PVU0_SRC_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_15_PVU0_SRC_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_15_PVU0_SRC_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_15_PVU0_SRC_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_15_PVU0_SRC_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_15_PVU0_SRC_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_15_PVU0_SRC_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_15_PVU0_SRC_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_15_PVU0_SRC_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_15_PVU0_SRC_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_15_PVU0_SRC_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_15_PVU0_CFG_TOG_CFG (NAVSS0_PVU_0_VIRT_ALIAS_15_PVU0_CFG_TOG_CFG)" base ad:0x4BF0F91000 rgroup.long 0x0++0xB line.long 0x0 "VIRT_ALIAS_15_PVU0_CFG_TOG_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_15_PVU0_CFG_TOG_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "VIRT_ALIAS_15_PVU0_CFG_TOG_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "VIRT_ALIAS_15_PVU0_CFG_TOG_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "VIRT_ALIAS_15_PVU0_CFG_TOG_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "VIRT_ALIAS_15_PVU0_CFG_TOG_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "VIRT_ALIAS_15_PVU0_CFG_TOG_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "VIRT_ALIAS_15_PVU0_CFG_TOG_CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "VIRT_ALIAS_15_PVU0_CFG_TOG_CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "VIRT_ALIAS_15_PVU0_CFG_TOG_CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "VIRT_ALIAS_15_PVU0_CFG_TOG_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "VIRT_ALIAS_15_PVU0_CFG_TOG_CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "VIRT_ALIAS_15_PVU0_CFG_TOG_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "VIRT_ALIAS_15_PVU0_CFG_TOG_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "VIRT_ALIAS_15_PVU0_CFG_TOG_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "VIRT_ALIAS_15_PVU0_CFG_TOG_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "VIRT_ALIAS_15_PVU0_CFG_TOG_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "VIRT_ALIAS_15_PVU0_CFG_TOG_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_0_VIRT_ALIAS_15_IO_PVU0_CFG_TLBIF_TLB (NAVSS0_PVU_0_VIRT_ALIAS_15_IO_PVU0_CFG_TLBIF_TLB)" base ad:0x4BF6000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_IO_PVU0_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_15_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_15_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_15_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_15_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_15_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_15_IO_PVU0_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif tree.end tree.end tree "NAVSS0_PVU_1" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_ALIAS64K_IO_PVU1_CFG_TLBIF_TLB (NAVSS0_PVU_1_ALIAS64K_IO_PVU1_CFG_TLBIF_TLB)" base ad:0x4A60400000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_IO_PVU1_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "ALIAS64K_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "ALIAS64K_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "ALIAS64K_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "ALIAS64K_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "ALIAS64K_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "ALIAS64K_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif tree "NAVSS0_PVU_1_IO" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_IO_PVU1_CFG_MMRS (NAVSS0_PVU_1_IO_PVU1_CFG_MMRS)" base ad:0x30F81000 rgroup.long 0x0++0x7 line.long 0x0 "IO_PVU1_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "IO_PVU1_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "IO_PVU1_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "IO_PVU1_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "IO_PVU1_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "IO_PVU1_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "IO_PVU1_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "IO_PVU1_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "IO_PVU1_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "IO_PVU1_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "IO_PVU1_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "IO_PVU1_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "IO_PVU1_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "IO_PVU1_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "IO_PVU1_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "IO_PVU1_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "IO_PVU1_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "IO_PVU1_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "IO_PVU1_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_IO_PVU1_CFG_TLBIF_TLB (NAVSS0_PVU_1_IO_PVU1_CFG_TLBIF_TLB)" base ad:0x36040000 rgroup.long 0x0++0x3 line.long 0x0 "IO_PVU1_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif tree.end tree "NAVSS0_PVU_1_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_0_IO_PVU1_CFG_MMRS (NAVSS0_PVU_1_VIRT_ALIAS_0_IO_PVU1_CFG_MMRS)" base ad:0x4B00F81000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_0_IO_PVU1_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_0_IO_PVU1_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_0_IO_PVU1_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_0_IO_PVU1_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_0_IO_PVU1_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_0_IO_PVU1_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_0_IO_PVU1_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_0_IO_PVU1_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_0_IO_PVU1_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_0_IO_PVU1_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_0_IO_PVU1_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_0_IO_PVU1_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_0_IO_PVU1_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_0_IO_PVU1_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_0_IO_PVU1_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_0_IO_PVU1_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_0_IO_PVU1_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_0_IO_PVU1_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_0_IO_PVU1_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_0_IO_PVU1_CFG_TLBIF_TLB (NAVSS0_PVU_1_VIRT_ALIAS_0_IO_PVU1_CFG_TLBIF_TLB)" base ad:0x4B06040000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_IO_PVU1_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_0_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_0_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_0_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_0_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_0_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_0_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_1_IO_PVU1_CFG_MMRS (NAVSS0_PVU_1_VIRT_ALIAS_1_IO_PVU1_CFG_MMRS)" base ad:0x4B10F81000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_1_IO_PVU1_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_1_IO_PVU1_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_1_IO_PVU1_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_1_IO_PVU1_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_1_IO_PVU1_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_1_IO_PVU1_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_1_IO_PVU1_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_1_IO_PVU1_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_1_IO_PVU1_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_1_IO_PVU1_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_1_IO_PVU1_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_1_IO_PVU1_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_1_IO_PVU1_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_1_IO_PVU1_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_1_IO_PVU1_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_1_IO_PVU1_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_1_IO_PVU1_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_1_IO_PVU1_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_1_IO_PVU1_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_1_IO_PVU1_CFG_TLBIF_TLB (NAVSS0_PVU_1_VIRT_ALIAS_1_IO_PVU1_CFG_TLBIF_TLB)" base ad:0x4B16040000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_IO_PVU1_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_1_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_1_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_1_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_1_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_1_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_1_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_2_IO_PVU1_CFG_MMRS (NAVSS0_PVU_1_VIRT_ALIAS_2_IO_PVU1_CFG_MMRS)" base ad:0x4B20F81000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_2_IO_PVU1_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_2_IO_PVU1_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_2_IO_PVU1_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_2_IO_PVU1_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_2_IO_PVU1_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_2_IO_PVU1_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_2_IO_PVU1_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_2_IO_PVU1_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_2_IO_PVU1_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_2_IO_PVU1_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_2_IO_PVU1_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_2_IO_PVU1_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_2_IO_PVU1_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_2_IO_PVU1_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_2_IO_PVU1_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_2_IO_PVU1_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_2_IO_PVU1_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_2_IO_PVU1_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_2_IO_PVU1_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_2_IO_PVU1_CFG_TLBIF_TLB (NAVSS0_PVU_1_VIRT_ALIAS_2_IO_PVU1_CFG_TLBIF_TLB)" base ad:0x4B26040000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_IO_PVU1_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_2_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_2_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_2_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_2_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_2_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_2_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_3_IO_PVU1_CFG_MMRS (NAVSS0_PVU_1_VIRT_ALIAS_3_IO_PVU1_CFG_MMRS)" base ad:0x4B30F81000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_3_IO_PVU1_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_3_IO_PVU1_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_3_IO_PVU1_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_3_IO_PVU1_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_3_IO_PVU1_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_3_IO_PVU1_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_3_IO_PVU1_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_3_IO_PVU1_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_3_IO_PVU1_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_3_IO_PVU1_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_3_IO_PVU1_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_3_IO_PVU1_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_3_IO_PVU1_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_3_IO_PVU1_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_3_IO_PVU1_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_3_IO_PVU1_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_3_IO_PVU1_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_3_IO_PVU1_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_3_IO_PVU1_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_3_IO_PVU1_CFG_TLBIF_TLB (NAVSS0_PVU_1_VIRT_ALIAS_3_IO_PVU1_CFG_TLBIF_TLB)" base ad:0x4B36040000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_IO_PVU1_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_3_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_3_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_3_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_3_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_3_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_3_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_4_IO_PVU1_CFG_MMRS (NAVSS0_PVU_1_VIRT_ALIAS_4_IO_PVU1_CFG_MMRS)" base ad:0x4B40F81000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_4_IO_PVU1_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_4_IO_PVU1_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_4_IO_PVU1_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_4_IO_PVU1_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_4_IO_PVU1_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_4_IO_PVU1_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_4_IO_PVU1_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_4_IO_PVU1_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_4_IO_PVU1_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_4_IO_PVU1_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_4_IO_PVU1_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_4_IO_PVU1_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_4_IO_PVU1_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_4_IO_PVU1_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_4_IO_PVU1_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_4_IO_PVU1_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_4_IO_PVU1_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_4_IO_PVU1_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_4_IO_PVU1_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_4_IO_PVU1_CFG_TLBIF_TLB (NAVSS0_PVU_1_VIRT_ALIAS_4_IO_PVU1_CFG_TLBIF_TLB)" base ad:0x4B46040000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_IO_PVU1_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_4_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_4_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_4_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_4_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_4_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_4_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_5_IO_PVU1_CFG_MMRS (NAVSS0_PVU_1_VIRT_ALIAS_5_IO_PVU1_CFG_MMRS)" base ad:0x4B50F81000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_5_IO_PVU1_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_5_IO_PVU1_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_5_IO_PVU1_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_5_IO_PVU1_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_5_IO_PVU1_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_5_IO_PVU1_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_5_IO_PVU1_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_5_IO_PVU1_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_5_IO_PVU1_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_5_IO_PVU1_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_5_IO_PVU1_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_5_IO_PVU1_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_5_IO_PVU1_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_5_IO_PVU1_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_5_IO_PVU1_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_5_IO_PVU1_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_5_IO_PVU1_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_5_IO_PVU1_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_5_IO_PVU1_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_5_IO_PVU1_CFG_TLBIF_TLB (NAVSS0_PVU_1_VIRT_ALIAS_5_IO_PVU1_CFG_TLBIF_TLB)" base ad:0x4B56040000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_IO_PVU1_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_5_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_5_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_5_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_5_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_5_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_5_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_6_IO_PVU1_CFG_MMRS (NAVSS0_PVU_1_VIRT_ALIAS_6_IO_PVU1_CFG_MMRS)" base ad:0x4B60F81000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_6_IO_PVU1_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_6_IO_PVU1_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_6_IO_PVU1_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_6_IO_PVU1_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_6_IO_PVU1_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_6_IO_PVU1_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_6_IO_PVU1_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_6_IO_PVU1_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_6_IO_PVU1_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_6_IO_PVU1_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_6_IO_PVU1_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_6_IO_PVU1_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_6_IO_PVU1_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_6_IO_PVU1_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_6_IO_PVU1_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_6_IO_PVU1_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_6_IO_PVU1_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_6_IO_PVU1_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_6_IO_PVU1_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_6_IO_PVU1_CFG_TLBIF_TLB (NAVSS0_PVU_1_VIRT_ALIAS_6_IO_PVU1_CFG_TLBIF_TLB)" base ad:0x4B66040000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_IO_PVU1_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_6_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_6_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_6_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_6_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_6_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_6_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_7_IO_PVU1_CFG_MMRS (NAVSS0_PVU_1_VIRT_ALIAS_7_IO_PVU1_CFG_MMRS)" base ad:0x4B70F81000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_7_IO_PVU1_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_7_IO_PVU1_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_7_IO_PVU1_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_7_IO_PVU1_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_7_IO_PVU1_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_7_IO_PVU1_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_7_IO_PVU1_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_7_IO_PVU1_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_7_IO_PVU1_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_7_IO_PVU1_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_7_IO_PVU1_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_7_IO_PVU1_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_7_IO_PVU1_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_7_IO_PVU1_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_7_IO_PVU1_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_7_IO_PVU1_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_7_IO_PVU1_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_7_IO_PVU1_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_7_IO_PVU1_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_7_IO_PVU1_CFG_TLBIF_TLB (NAVSS0_PVU_1_VIRT_ALIAS_7_IO_PVU1_CFG_TLBIF_TLB)" base ad:0x4B76040000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_IO_PVU1_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_7_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_7_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_7_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_7_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_7_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_7_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_8_IO_PVU1_CFG_MMRS (NAVSS0_PVU_1_VIRT_ALIAS_8_IO_PVU1_CFG_MMRS)" base ad:0x4B80F81000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_8_IO_PVU1_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_8_IO_PVU1_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_8_IO_PVU1_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_8_IO_PVU1_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_8_IO_PVU1_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_8_IO_PVU1_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_8_IO_PVU1_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_8_IO_PVU1_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_8_IO_PVU1_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_8_IO_PVU1_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_8_IO_PVU1_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_8_IO_PVU1_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_8_IO_PVU1_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_8_IO_PVU1_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_8_IO_PVU1_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_8_IO_PVU1_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_8_IO_PVU1_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_8_IO_PVU1_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_8_IO_PVU1_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_8_IO_PVU1_CFG_TLBIF_TLB (NAVSS0_PVU_1_VIRT_ALIAS_8_IO_PVU1_CFG_TLBIF_TLB)" base ad:0x4B86040000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_IO_PVU1_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_8_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_8_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_8_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_8_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_8_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_8_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_9_IO_PVU1_CFG_MMRS (NAVSS0_PVU_1_VIRT_ALIAS_9_IO_PVU1_CFG_MMRS)" base ad:0x4B90F81000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_9_IO_PVU1_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_9_IO_PVU1_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_9_IO_PVU1_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_9_IO_PVU1_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_9_IO_PVU1_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_9_IO_PVU1_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_9_IO_PVU1_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_9_IO_PVU1_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_9_IO_PVU1_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_9_IO_PVU1_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_9_IO_PVU1_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_9_IO_PVU1_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_9_IO_PVU1_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_9_IO_PVU1_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_9_IO_PVU1_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_9_IO_PVU1_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_9_IO_PVU1_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_9_IO_PVU1_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_9_IO_PVU1_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_9_IO_PVU1_CFG_TLBIF_TLB (NAVSS0_PVU_1_VIRT_ALIAS_9_IO_PVU1_CFG_TLBIF_TLB)" base ad:0x4B96040000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_IO_PVU1_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_9_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_9_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_9_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_9_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_9_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_9_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_10_IO_PVU1_CFG_MMRS (NAVSS0_PVU_1_VIRT_ALIAS_10_IO_PVU1_CFG_MMRS)" base ad:0x4BA0F81000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_10_IO_PVU1_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_10_IO_PVU1_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_10_IO_PVU1_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_10_IO_PVU1_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_10_IO_PVU1_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_10_IO_PVU1_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_10_IO_PVU1_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_10_IO_PVU1_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_10_IO_PVU1_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_10_IO_PVU1_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_10_IO_PVU1_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_10_IO_PVU1_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_10_IO_PVU1_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_10_IO_PVU1_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_10_IO_PVU1_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_10_IO_PVU1_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_10_IO_PVU1_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_10_IO_PVU1_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_10_IO_PVU1_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_10_IO_PVU1_CFG_TLBIF_TLB (NAVSS0_PVU_1_VIRT_ALIAS_10_IO_PVU1_CFG_TLBIF_TLB)" base ad:0x4BA6040000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_IO_PVU1_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_10_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_10_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_10_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_10_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_10_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_10_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_11_IO_PVU1_CFG_MMRS (NAVSS0_PVU_1_VIRT_ALIAS_11_IO_PVU1_CFG_MMRS)" base ad:0x4BB0F81000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_11_IO_PVU1_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_11_IO_PVU1_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_11_IO_PVU1_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_11_IO_PVU1_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_11_IO_PVU1_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_11_IO_PVU1_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_11_IO_PVU1_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_11_IO_PVU1_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_11_IO_PVU1_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_11_IO_PVU1_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_11_IO_PVU1_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_11_IO_PVU1_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_11_IO_PVU1_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_11_IO_PVU1_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_11_IO_PVU1_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_11_IO_PVU1_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_11_IO_PVU1_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_11_IO_PVU1_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_11_IO_PVU1_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_11_IO_PVU1_CFG_TLBIF_TLB (NAVSS0_PVU_1_VIRT_ALIAS_11_IO_PVU1_CFG_TLBIF_TLB)" base ad:0x4BB6040000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_IO_PVU1_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_11_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_11_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_11_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_11_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_11_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_11_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_12_IO_PVU1_CFG_MMRS (NAVSS0_PVU_1_VIRT_ALIAS_12_IO_PVU1_CFG_MMRS)" base ad:0x4BC0F81000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_12_IO_PVU1_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_12_IO_PVU1_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_12_IO_PVU1_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_12_IO_PVU1_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_12_IO_PVU1_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_12_IO_PVU1_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_12_IO_PVU1_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_12_IO_PVU1_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_12_IO_PVU1_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_12_IO_PVU1_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_12_IO_PVU1_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_12_IO_PVU1_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_12_IO_PVU1_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_12_IO_PVU1_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_12_IO_PVU1_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_12_IO_PVU1_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_12_IO_PVU1_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_12_IO_PVU1_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_12_IO_PVU1_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_12_IO_PVU1_CFG_TLBIF_TLB (NAVSS0_PVU_1_VIRT_ALIAS_12_IO_PVU1_CFG_TLBIF_TLB)" base ad:0x4BC6040000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_IO_PVU1_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_12_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_12_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_12_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_12_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_12_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_12_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_13_IO_PVU1_CFG_MMRS (NAVSS0_PVU_1_VIRT_ALIAS_13_IO_PVU1_CFG_MMRS)" base ad:0x4BD0F81000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_13_IO_PVU1_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_13_IO_PVU1_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_13_IO_PVU1_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_13_IO_PVU1_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_13_IO_PVU1_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_13_IO_PVU1_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_13_IO_PVU1_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_13_IO_PVU1_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_13_IO_PVU1_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_13_IO_PVU1_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_13_IO_PVU1_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_13_IO_PVU1_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_13_IO_PVU1_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_13_IO_PVU1_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_13_IO_PVU1_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_13_IO_PVU1_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_13_IO_PVU1_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_13_IO_PVU1_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_13_IO_PVU1_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_13_IO_PVU1_CFG_TLBIF_TLB (NAVSS0_PVU_1_VIRT_ALIAS_13_IO_PVU1_CFG_TLBIF_TLB)" base ad:0x4BD6040000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_IO_PVU1_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_13_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_13_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_13_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_13_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_13_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_13_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_14_IO_PVU1_CFG_MMRS (NAVSS0_PVU_1_VIRT_ALIAS_14_IO_PVU1_CFG_MMRS)" base ad:0x4BE0F81000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_14_IO_PVU1_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_14_IO_PVU1_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_14_IO_PVU1_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_14_IO_PVU1_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_14_IO_PVU1_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_14_IO_PVU1_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_14_IO_PVU1_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_14_IO_PVU1_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_14_IO_PVU1_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_14_IO_PVU1_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_14_IO_PVU1_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_14_IO_PVU1_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_14_IO_PVU1_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_14_IO_PVU1_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_14_IO_PVU1_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_14_IO_PVU1_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_14_IO_PVU1_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_14_IO_PVU1_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_14_IO_PVU1_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_14_IO_PVU1_CFG_TLBIF_TLB (NAVSS0_PVU_1_VIRT_ALIAS_14_IO_PVU1_CFG_TLBIF_TLB)" base ad:0x4BE6040000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_IO_PVU1_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_14_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_14_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_14_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_14_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_14_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_14_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_15_IO_PVU1_CFG_MMRS (NAVSS0_PVU_1_VIRT_ALIAS_15_IO_PVU1_CFG_MMRS)" base ad:0x4BF0F81000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_15_IO_PVU1_CFG_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_15_IO_PVU1_CFG_MMRS_config,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs" rgroup.long 0x10++0xB line.long 0x0 "VIRT_ALIAS_15_IO_PVU1_CFG_MMRS_enable,The Enable Register enables the pvu." bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = disabled. 1 = enabled" "0: disabled,1: enabled" line.long 0x4 "VIRT_ALIAS_15_IO_PVU1_CFG_MMRS_virtid_map1,The Map Register 1 defines the virtid mapping for the pvu." bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "VIRT_ALIAS_15_IO_PVU1_CFG_MMRS_virtid_map2,The Map Register 2 defines the virtid mapping for the pvu." hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." rgroup.long 0x30++0x3 line.long 0x0 "VIRT_ALIAS_15_IO_PVU1_CFG_MMRS_exception_logging_disable,The Exception Logging Disable Register defines which types of faults are disabled for logging." bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" newline bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" newline bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" rgroup.long 0x104++0x3 line.long 0x0 "VIRT_ALIAS_15_IO_PVU1_CFG_MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x120++0x3 line.long 0x0 "VIRT_ALIAS_15_IO_PVU1_CFG_MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "VIRT_ALIAS_15_IO_PVU1_CFG_MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "VIRT_ALIAS_15_IO_PVU1_CFG_MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." line.long 0x8 "VIRT_ALIAS_15_IO_PVU1_CFG_MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "VIRT_ALIAS_15_IO_PVU1_CFG_MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "VIRT_ALIAS_15_IO_PVU1_CFG_MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "VIRT_ALIAS_15_IO_PVU1_CFG_MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x140++0x13 line.long 0x0 "VIRT_ALIAS_15_IO_PVU1_CFG_MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "VIRT_ALIAS_15_IO_PVU1_CFG_MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "VIRT_ALIAS_15_IO_PVU1_CFG_MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "VIRT_ALIAS_15_IO_PVU1_CFG_MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "VIRT_ALIAS_15_IO_PVU1_CFG_MMRS_eoi_reg,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_PVU_1_VIRT_ALIAS_15_IO_PVU1_CFG_TLBIF_TLB (NAVSS0_PVU_1_VIRT_ALIAS_15_IO_PVU1_CFG_TLBIF_TLB)" base ad:0x4BF6040000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_IO_PVU1_CFG_TLBIF_TLB_glb,The TLB chain points to another TLB. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" newline bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. 1+ = chain to that TLB number." rgroup.long 0x20++0xB line.long 0x0 "VIRT_ALIAS_15_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG0,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_15_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG1,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32. The address must be aligned to the page size." line.long 0x8 "VIRT_ALIAS_15_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG2,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" newline bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit0 = enable user read access UR. Bit1 = enable user write access UW. Bit2 = enable user execute access UX. Bit3 = enable supervisor read access SR. Bit4 = enable supervisor write access SW. Bit5 = enable.." newline bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" newline bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" newline bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" rgroup.long 0x30++0x7 line.long 0x0 "VIRT_ALIAS_15_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG4,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0. The address must be aligned to the page size." line.long 0x4 "VIRT_ALIAS_15_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG5,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB. The address must be aligned to the page size." hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32. The address must be aligned to the page size." rgroup.long 0x38++0x3 line.long 0x0 "VIRT_ALIAS_15_IO_PVU1_CFG_TLBIF_TLB_ENTRY_REG6,The TLB Entry. The a is the TLB number. and the b is the entry number within a TLB." bitfld.long 0x0 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end endif tree.end tree.end tree.end tree "NAVSS0_RINGACC_0" tree "NAVSS0_RINGACC_0_ALIAS64K" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_ALIAS64K_RINGACC0_CFG_MON (NAVSS0_RINGACC_0_ALIAS64K_RINGACC0_CFG_MON)" base ad:0x4A20000000 rgroup.long 0x0++0xF line.long 0x0 "ALIAS64K_RINGACC0__CFG__MON_control,Monitor Control Register" hexmask.long.word 0x0 16.--31. 1. "EVT,Event to produce." hexmask.long.byte 0x0 8.--11. 1. "SOURCE,Monitor source selection. 0 = element count. 1 = reserved. 2 = reserved." bitfld.long 0x0 0.--2. "MODE,Monitor Mode. 0 = disabled. 1 = push/pop statistics capture. 2 = low/high threshold checks. 3 = low/high watermarking. 4 = starvation counting." "0: disabled,1: push/pop statistics capture,2: low/high threshold checks,3: low/high watermarking,4: starvation counting,?,?,?" line.long 0x4 "ALIAS64K_RINGACC0__CFG__MON_queue,Monitor Queue Register" hexmask.long.word 0x4 0.--15. 1. "QUEUE,Queue to monitor." line.long 0x8 "ALIAS64K_RINGACC0__CFG__MON_data0,Monitor Data Register" hexmask.long 0x8 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pushes. For mode 2 this is read-write and the low threshold value. For mode 3 this is read only and the low watermark. For mode 4 this is read only and the starvation count." line.long 0xC "ALIAS64K_RINGACC0__CFG__MON_data1,Monitor Data Register" hexmask.long 0xC 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pops. For mode 2 this is read-write and the high threshold value. For mode 3 this is read only and the high watermark. For mode 4 this is not used." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_ALIAS64K_RINGACC0_SRC_FIFOS (NAVSS0_RINGACC_0_ALIAS64K_RINGACC0_SRC_FIFOS)" base ad:0x4A80000000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_RINGACC0__SRC__FIFOS_RING_HEAD_DATA,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head. These registers are virtual and non-static (i.e. they are just address locations that are used.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x200++0x3 line.long 0x0 "ALIAS64K_RINGACC0__SRC__FIFOS_RING_TAIL_DATA,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail. These registers are virtual and non-static (i.e. they are just address locations that are used.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x400++0x3 line.long 0x0 "ALIAS64K_RINGACC0__SRC__FIFOS_PEEK_HEAD_DATA,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element. These registers are virtual and non-static (i.e. they are just address locations.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." rgroup.long 0x600++0x3 line.long 0x0 "ALIAS64K_RINGACC0__SRC__FIFOS_PEEK_TAIL_DATA,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element. These registers are virtual and non-static (i.e. they are just address locations.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_ALIAS64K_RINGACC0_CFG_RT (NAVSS0_RINGACC_0_ALIAS64K_RINGACC0_CFG_RT)" base ad:0x4AC0000000 rgroup.long 0x10++0x3 line.long 0x0 "ALIAS64K_RINGACC0__CFG__RT_RT_DB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write operation." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0xF line.long 0x0 "ALIAS64K_RINGACC0__CFG__RT_RT_OCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring.." hexmask.long.tbyte 0x0 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0x4 "ALIAS64K_RINGACC0__CFG__RT_RT_INDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel." hexmask.long.tbyte 0x4 0.--19. 1. "INDX,Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." line.long 0x8 "ALIAS64K_RINGACC0__CFG__RT_RT_HWOCC,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a.." hexmask.long.tbyte 0x8 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0xC "ALIAS64K_RINGACC0__CFG__RT_RT_HWINDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel." hexmask.long.tbyte 0xC 0.--19. 1. "INDX,Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." tree.end endif tree.end tree "NAVSS0_RINGACC_0_UDMASS" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_UDMASS_RINGACC0_CFG (NAVSS0_RINGACC_0_UDMASS_RINGACC0_CFG)" base ad:0x31080000 rgroup.long 0x40++0x13 line.long 0x0 "RINGACC0__CFG__CFG_BA_LO,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of the ring. or.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Tx Ring base address (LSBs)" line.long 0x4 "RINGACC0__CFG__CFG_BA_HI,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of the ring. or.." hexmask.long.word 0x4 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)" line.long 0x8 "RINGACC0__CFG__CFG_SIZE,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the.." bitfld.long 0x8 30.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3" bitfld.long 0x8 24.--26. "ELSIZE,Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED" "?,?,?,?,?,?,?,7: RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number." line.long 0xC "RINGACC0__CFG__CFG_EVT,The Ring Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote the occurrence of an up event [empty to not-empty] or a down event [non-empty to empty] for this ring." hexmask.long.word 0xC 0.--15. 1. "EVT,Defines the event for this ring or queue." line.long 0x10 "RINGACC0__CFG__CFG_ORDERID,The Ring OrderID Register contains the bus orderid value for the ring memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for this ring or queue." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_UDMASS_RINGACC0_GCFG (NAVSS0_RINGACC_0_UDMASS_RINGACC0_GCFG)" base ad:0x31160000 rgroup.long 0x0++0x3 line.long 0x0 "RINGACC0__CFG__GCFG_revision,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "RINGACC0__CFG__GCFG_trace_ctl,Trace Control Register" bitfld.long 0x0 31. "EN,Trace enable 0 = disable 1 = enable." "0: disable,1: enable" bitfld.long 0x0 30. "ALL_QUEUES,Trace everything 0 = only the selected queue 1 = every queue." "0: only the selected queue,1: every queue" bitfld.long 0x0 29. "MSG,Trace message data 0 = include only the operation 1 = include message data." "0: include only the operation,1: include message data" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number when tracing a single queue." rgroup.long 0x20++0x3 line.long 0x0 "RINGACC0__CFG__GCFG_overflow,Overflow Queue Register" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue to send overflow messages. A value of 0xffff will disable the overflow function." rgroup.long 0x40++0x3 line.long 0x0 "RINGACC0__CFG__GCFG_error_evt,The Error Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote detection of a ring memory transaction bus error." hexmask.long.word 0x0 0.--15. 1. "EVT,Event to send when detecting a bus error." rgroup.long 0x44++0x3 line.long 0x0 "RINGACC0__CFG__GCFG_error_log,Error Log Register. A read of this register will clear the pending error log event and allow a new error to be captured. It does not clear the contents of this register which are only valid while the error event is pending." bitfld.long 0x0 31. "PUSH,Bus error was caused by a push. 0 = pop. 1 = push." "0: pop,1: push" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue that received the bus error." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_UDMASS_RINGACC0_CFG_MON (NAVSS0_RINGACC_0_UDMASS_RINGACC0_CFG_MON)" base ad:0x32000000 rgroup.long 0x0++0xF line.long 0x0 "RINGACC0__CFG__MON_control,Monitor Control Register" hexmask.long.word 0x0 16.--31. 1. "EVT,Event to produce." hexmask.long.byte 0x0 8.--11. 1. "SOURCE,Monitor source selection. 0 = element count. 1 = reserved. 2 = reserved." bitfld.long 0x0 0.--2. "MODE,Monitor Mode. 0 = disabled. 1 = push/pop statistics capture. 2 = low/high threshold checks. 3 = low/high watermarking. 4 = starvation counting." "0: disabled,1: push/pop statistics capture,2: low/high threshold checks,3: low/high watermarking,4: starvation counting,?,?,?" line.long 0x4 "RINGACC0__CFG__MON_queue,Monitor Queue Register" hexmask.long.word 0x4 0.--15. 1. "QUEUE,Queue to monitor." line.long 0x8 "RINGACC0__CFG__MON_data0,Monitor Data Register" hexmask.long 0x8 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pushes. For mode 2 this is read-write and the low threshold value. For mode 3 this is read only and the low watermark. For mode 4 this is read only and the starvation count." line.long 0xC "RINGACC0__CFG__MON_data1,Monitor Data Register" hexmask.long 0xC 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pops. For mode 2 this is read-write and the high threshold value. For mode 3 this is read only and the high watermark. For mode 4 this is not used." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_UDMASS_RINGACC0_SRC_FIFOS (NAVSS0_RINGACC_0_UDMASS_RINGACC0_SRC_FIFOS)" base ad:0x38000000 rgroup.long 0x0++0x3 line.long 0x0 "RINGACC0__SRC__FIFOS_RING_HEAD_DATA,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head. These registers are virtual and non-static (i.e. they are just address locations that are used to access.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x200++0x3 line.long 0x0 "RINGACC0__SRC__FIFOS_RING_TAIL_DATA,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail. These registers are virtual and non-static (i.e. they are just address locations that are used to access.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x400++0x3 line.long 0x0 "RINGACC0__SRC__FIFOS_PEEK_HEAD_DATA,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." rgroup.long 0x600++0x3 line.long 0x0 "RINGACC0__SRC__FIFOS_PEEK_TAIL_DATA,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_UDMASS_RINGACC0_CFG_RT (NAVSS0_RINGACC_0_UDMASS_RINGACC0_CFG_RT)" base ad:0x3C000000 rgroup.long 0x10++0x3 line.long 0x0 "RINGACC0__CFG__RT_RT_DB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write operation." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0xF line.long 0x0 "RINGACC0__CFG__RT_RT_OCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring which can be.." hexmask.long.tbyte 0x0 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0x4 "RINGACC0__CFG__RT_RT_INDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel." hexmask.long.tbyte 0x4 0.--19. 1. "INDX,Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." line.long 0x8 "RINGACC0__CFG__RT_RT_HWOCC,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending.." hexmask.long.tbyte 0x8 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0xC "RINGACC0__CFG__RT_RT_HWINDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel." hexmask.long.tbyte 0xC 0.--19. 1. "INDX,Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_UDMASS_RINGACC0_ISC (NAVSS0_RINGACC_0_UDMASS_RINGACC0_ISC)" base ad:0x45870000 rgroup.long 0x0++0x7 line.long 0x0 "UDMASS_RINGACC0_ISC_ISC_control,The ISC a Region b Control Register defines the control fields for the ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared. Has precedence over priv set bits." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure. Has precedence over secure enable bits." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "UDMASS_RINGACC0_ISC_ISC_control2,The ISC a Region b Control Register 2 defines the control fields for the ISC." bitfld.long 0x4 31. "PASS_V,No virtID replacement pass through value." "0,1" bitfld.long 0x4 28.--29. "ATYPE,Defines the output address type. 0 = physical no memory attributes. 1 = intermediate. 2 = virtual. 3 = physical with memory attributes." "0: physical no memory attributes,1: intermediate,2: virtual,3: physical with memory attributes" hexmask.long.word 0x4 16.--27. 1. "VIRTID,Virt ID." tree.end endif tree.end tree "NAVSS0_RINGACC_0_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_0_RINGACC0_CFG (NAVSS0_RINGACC_0_VIRT_ALIAS_0_RINGACC0_CFG)" base ad:0x4B01080000 rgroup.long 0x40++0x13 line.long 0x0 "VIRT_ALIAS_0_RINGACC0__CFG__CFG_BA_LO,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Tx Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_0_RINGACC0__CFG__CFG_BA_HI,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of.." hexmask.long.word 0x4 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_0_RINGACC0__CFG__CFG_SIZE,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to.." bitfld.long 0x8 30.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3" bitfld.long 0x8 24.--26. "ELSIZE,Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED" "?,?,?,?,?,?,?,7: RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number." line.long 0xC "VIRT_ALIAS_0_RINGACC0__CFG__CFG_EVT,The Ring Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote the occurrence of an up event [empty to not-empty] or a down event [non-empty to empty] for this ring." hexmask.long.word 0xC 0.--15. 1. "EVT,Defines the event for this ring or queue." line.long 0x10 "VIRT_ALIAS_0_RINGACC0__CFG__CFG_ORDERID,The Ring OrderID Register contains the bus orderid value for the ring memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for this ring or queue." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_0_RINGACC0_CFG_GCFG (NAVSS0_RINGACC_0_VIRT_ALIAS_0_RINGACC0_CFG_GCFG)" base ad:0x4B01160000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_RINGACC0__CFG__GCFG_revision,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_RINGACC0__CFG__GCFG_trace_ctl,Trace Control Register" bitfld.long 0x0 31. "EN,Trace enable 0 = disable 1 = enable." "0: disable,1: enable" bitfld.long 0x0 30. "ALL_QUEUES,Trace everything 0 = only the selected queue 1 = every queue." "0: only the selected queue,1: every queue" bitfld.long 0x0 29. "MSG,Trace message data 0 = include only the operation 1 = include message data." "0: include only the operation,1: include message data" newline hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number when tracing a single queue." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_0_RINGACC0__CFG__GCFG_overflow,Overflow Queue Register" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue to send overflow messages. A value of 0xffff will disable the overflow function." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_0_RINGACC0__CFG__GCFG_error_evt,The Error Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote detection of a ring memory transaction bus error." hexmask.long.word 0x0 0.--15. 1. "EVT,Event to send when detecting a bus error." rgroup.long 0x44++0x3 line.long 0x0 "VIRT_ALIAS_0_RINGACC0__CFG__GCFG_error_log,Error Log Register. A read of this register will clear the pending error log event and allow a new error to be captured. It does not clear the contents of this register which are only valid while the error event.." bitfld.long 0x0 31. "PUSH,Bus error was caused by a push. 0 = pop. 1 = push." "0: pop,1: push" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue that received the bus error." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_0_RINGACC0_CFG_MON (NAVSS0_RINGACC_0_VIRT_ALIAS_0_RINGACC0_CFG_MON)" base ad:0x4B02000000 rgroup.long 0x0++0xF line.long 0x0 "VIRT_ALIAS_0_RINGACC0__CFG__MON_control,Monitor Control Register" hexmask.long.word 0x0 16.--31. 1. "EVT,Event to produce." hexmask.long.byte 0x0 8.--11. 1. "SOURCE,Monitor source selection. 0 = element count. 1 = reserved. 2 = reserved." bitfld.long 0x0 0.--2. "MODE,Monitor Mode. 0 = disabled. 1 = push/pop statistics capture. 2 = low/high threshold checks. 3 = low/high watermarking. 4 = starvation counting." "0: disabled,1: push/pop statistics capture,2: low/high threshold checks,3: low/high watermarking,4: starvation counting,?,?,?" line.long 0x4 "VIRT_ALIAS_0_RINGACC0__CFG__MON_queue,Monitor Queue Register" hexmask.long.word 0x4 0.--15. 1. "QUEUE,Queue to monitor." line.long 0x8 "VIRT_ALIAS_0_RINGACC0__CFG__MON_data0,Monitor Data Register" hexmask.long 0x8 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pushes. For mode 2 this is read-write and the low threshold value. For mode 3 this is read only and the low watermark. For mode 4 this is read only and the starvation count." line.long 0xC "VIRT_ALIAS_0_RINGACC0__CFG__MON_data1,Monitor Data Register" hexmask.long 0xC 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pops. For mode 2 this is read-write and the high threshold value. For mode 3 this is read only and the high watermark. For mode 4 this is not used." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_0_RINGACC0_SRC_FIFOS (NAVSS0_RINGACC_0_VIRT_ALIAS_0_RINGACC0_SRC_FIFOS)" base ad:0x4B08000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_RINGACC0__SRC__FIFOS_RING_HEAD_DATA,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_0_RINGACC0__SRC__FIFOS_RING_TAIL_DATA,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_0_RINGACC0__SRC__FIFOS_PEEK_HEAD_DATA,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." rgroup.long 0x600++0x3 line.long 0x0 "VIRT_ALIAS_0_RINGACC0__SRC__FIFOS_PEEK_TAIL_DATA,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_0_RINGACC0_CFG_RT (NAVSS0_RINGACC_0_VIRT_ALIAS_0_RINGACC0_CFG_RT)" base ad:0x4B0C000000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_RINGACC0__CFG__RT_RT_DB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0xF line.long 0x0 "VIRT_ALIAS_0_RINGACC0__CFG__RT_RT_OCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring.." hexmask.long.tbyte 0x0 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0x4 "VIRT_ALIAS_0_RINGACC0__CFG__RT_RT_INDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel." hexmask.long.tbyte 0x4 0.--19. 1. "INDX,Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." line.long 0x8 "VIRT_ALIAS_0_RINGACC0__CFG__RT_RT_HWOCC,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a.." hexmask.long.tbyte 0x8 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0xC "VIRT_ALIAS_0_RINGACC0__CFG__RT_RT_HWINDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel." hexmask.long.tbyte 0xC 0.--19. 1. "INDX,Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_1_RINGACC0_CFG (NAVSS0_RINGACC_0_VIRT_ALIAS_1_RINGACC0_CFG)" base ad:0x4B11080000 rgroup.long 0x40++0x13 line.long 0x0 "VIRT_ALIAS_1_RINGACC0__CFG__CFG_BA_LO,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Tx Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_1_RINGACC0__CFG__CFG_BA_HI,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of.." hexmask.long.word 0x4 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_1_RINGACC0__CFG__CFG_SIZE,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to.." bitfld.long 0x8 30.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3" bitfld.long 0x8 24.--26. "ELSIZE,Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED" "?,?,?,?,?,?,?,7: RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number." line.long 0xC "VIRT_ALIAS_1_RINGACC0__CFG__CFG_EVT,The Ring Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote the occurrence of an up event [empty to not-empty] or a down event [non-empty to empty] for this ring." hexmask.long.word 0xC 0.--15. 1. "EVT,Defines the event for this ring or queue." line.long 0x10 "VIRT_ALIAS_1_RINGACC0__CFG__CFG_ORDERID,The Ring OrderID Register contains the bus orderid value for the ring memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for this ring or queue." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_1_RINGACC0_CFG_GCFG (NAVSS0_RINGACC_0_VIRT_ALIAS_1_RINGACC0_CFG_GCFG)" base ad:0x4B11160000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_RINGACC0__CFG__GCFG_revision,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_RINGACC0__CFG__GCFG_trace_ctl,Trace Control Register" bitfld.long 0x0 31. "EN,Trace enable 0 = disable 1 = enable." "0: disable,1: enable" bitfld.long 0x0 30. "ALL_QUEUES,Trace everything 0 = only the selected queue 1 = every queue." "0: only the selected queue,1: every queue" bitfld.long 0x0 29. "MSG,Trace message data 0 = include only the operation 1 = include message data." "0: include only the operation,1: include message data" newline hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number when tracing a single queue." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_1_RINGACC0__CFG__GCFG_overflow,Overflow Queue Register" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue to send overflow messages. A value of 0xffff will disable the overflow function." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_1_RINGACC0__CFG__GCFG_error_evt,The Error Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote detection of a ring memory transaction bus error." hexmask.long.word 0x0 0.--15. 1. "EVT,Event to send when detecting a bus error." rgroup.long 0x44++0x3 line.long 0x0 "VIRT_ALIAS_1_RINGACC0__CFG__GCFG_error_log,Error Log Register. A read of this register will clear the pending error log event and allow a new error to be captured. It does not clear the contents of this register which are only valid while the error event.." bitfld.long 0x0 31. "PUSH,Bus error was caused by a push. 0 = pop. 1 = push." "0: pop,1: push" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue that received the bus error." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_1_RINGACC0_CFG_MON (NAVSS0_RINGACC_0_VIRT_ALIAS_1_RINGACC0_CFG_MON)" base ad:0x4B12000000 rgroup.long 0x0++0xF line.long 0x0 "VIRT_ALIAS_1_RINGACC0__CFG__MON_control,Monitor Control Register" hexmask.long.word 0x0 16.--31. 1. "EVT,Event to produce." hexmask.long.byte 0x0 8.--11. 1. "SOURCE,Monitor source selection. 0 = element count. 1 = reserved. 2 = reserved." bitfld.long 0x0 0.--2. "MODE,Monitor Mode. 0 = disabled. 1 = push/pop statistics capture. 2 = low/high threshold checks. 3 = low/high watermarking. 4 = starvation counting." "0: disabled,1: push/pop statistics capture,2: low/high threshold checks,3: low/high watermarking,4: starvation counting,?,?,?" line.long 0x4 "VIRT_ALIAS_1_RINGACC0__CFG__MON_queue,Monitor Queue Register" hexmask.long.word 0x4 0.--15. 1. "QUEUE,Queue to monitor." line.long 0x8 "VIRT_ALIAS_1_RINGACC0__CFG__MON_data0,Monitor Data Register" hexmask.long 0x8 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pushes. For mode 2 this is read-write and the low threshold value. For mode 3 this is read only and the low watermark. For mode 4 this is read only and the starvation count." line.long 0xC "VIRT_ALIAS_1_RINGACC0__CFG__MON_data1,Monitor Data Register" hexmask.long 0xC 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pops. For mode 2 this is read-write and the high threshold value. For mode 3 this is read only and the high watermark. For mode 4 this is not used." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_1_RINGACC0_SRC_FIFOS (NAVSS0_RINGACC_0_VIRT_ALIAS_1_RINGACC0_SRC_FIFOS)" base ad:0x4B18000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_RINGACC0__SRC__FIFOS_RING_HEAD_DATA,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_1_RINGACC0__SRC__FIFOS_RING_TAIL_DATA,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_1_RINGACC0__SRC__FIFOS_PEEK_HEAD_DATA,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." rgroup.long 0x600++0x3 line.long 0x0 "VIRT_ALIAS_1_RINGACC0__SRC__FIFOS_PEEK_TAIL_DATA,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_1_RINGACC0_CFG_RT (NAVSS0_RINGACC_0_VIRT_ALIAS_1_RINGACC0_CFG_RT)" base ad:0x4B1C000000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_RINGACC0__CFG__RT_RT_DB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0xF line.long 0x0 "VIRT_ALIAS_1_RINGACC0__CFG__RT_RT_OCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring.." hexmask.long.tbyte 0x0 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0x4 "VIRT_ALIAS_1_RINGACC0__CFG__RT_RT_INDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel." hexmask.long.tbyte 0x4 0.--19. 1. "INDX,Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." line.long 0x8 "VIRT_ALIAS_1_RINGACC0__CFG__RT_RT_HWOCC,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a.." hexmask.long.tbyte 0x8 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0xC "VIRT_ALIAS_1_RINGACC0__CFG__RT_RT_HWINDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel." hexmask.long.tbyte 0xC 0.--19. 1. "INDX,Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_2_RINGACC0_CFG (NAVSS0_RINGACC_0_VIRT_ALIAS_2_RINGACC0_CFG)" base ad:0x4B21080000 rgroup.long 0x40++0x13 line.long 0x0 "VIRT_ALIAS_2_RINGACC0__CFG__CFG_BA_LO,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Tx Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_2_RINGACC0__CFG__CFG_BA_HI,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of.." hexmask.long.word 0x4 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_2_RINGACC0__CFG__CFG_SIZE,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to.." bitfld.long 0x8 30.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3" bitfld.long 0x8 24.--26. "ELSIZE,Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED" "?,?,?,?,?,?,?,7: RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number." line.long 0xC "VIRT_ALIAS_2_RINGACC0__CFG__CFG_EVT,The Ring Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote the occurrence of an up event [empty to not-empty] or a down event [non-empty to empty] for this ring." hexmask.long.word 0xC 0.--15. 1. "EVT,Defines the event for this ring or queue." line.long 0x10 "VIRT_ALIAS_2_RINGACC0__CFG__CFG_ORDERID,The Ring OrderID Register contains the bus orderid value for the ring memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for this ring or queue." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_2_RINGACC0_CFG_GCFG (NAVSS0_RINGACC_0_VIRT_ALIAS_2_RINGACC0_CFG_GCFG)" base ad:0x4B21160000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_RINGACC0__CFG__GCFG_revision,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_RINGACC0__CFG__GCFG_trace_ctl,Trace Control Register" bitfld.long 0x0 31. "EN,Trace enable 0 = disable 1 = enable." "0: disable,1: enable" bitfld.long 0x0 30. "ALL_QUEUES,Trace everything 0 = only the selected queue 1 = every queue." "0: only the selected queue,1: every queue" bitfld.long 0x0 29. "MSG,Trace message data 0 = include only the operation 1 = include message data." "0: include only the operation,1: include message data" newline hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number when tracing a single queue." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_2_RINGACC0__CFG__GCFG_overflow,Overflow Queue Register" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue to send overflow messages. A value of 0xffff will disable the overflow function." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_2_RINGACC0__CFG__GCFG_error_evt,The Error Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote detection of a ring memory transaction bus error." hexmask.long.word 0x0 0.--15. 1. "EVT,Event to send when detecting a bus error." rgroup.long 0x44++0x3 line.long 0x0 "VIRT_ALIAS_2_RINGACC0__CFG__GCFG_error_log,Error Log Register. A read of this register will clear the pending error log event and allow a new error to be captured. It does not clear the contents of this register which are only valid while the error event.." bitfld.long 0x0 31. "PUSH,Bus error was caused by a push. 0 = pop. 1 = push." "0: pop,1: push" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue that received the bus error." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_2_RINGACC0_CFG_MON (NAVSS0_RINGACC_0_VIRT_ALIAS_2_RINGACC0_CFG_MON)" base ad:0x4B22000000 rgroup.long 0x0++0xF line.long 0x0 "VIRT_ALIAS_2_RINGACC0__CFG__MON_control,Monitor Control Register" hexmask.long.word 0x0 16.--31. 1. "EVT,Event to produce." hexmask.long.byte 0x0 8.--11. 1. "SOURCE,Monitor source selection. 0 = element count. 1 = reserved. 2 = reserved." bitfld.long 0x0 0.--2. "MODE,Monitor Mode. 0 = disabled. 1 = push/pop statistics capture. 2 = low/high threshold checks. 3 = low/high watermarking. 4 = starvation counting." "0: disabled,1: push/pop statistics capture,2: low/high threshold checks,3: low/high watermarking,4: starvation counting,?,?,?" line.long 0x4 "VIRT_ALIAS_2_RINGACC0__CFG__MON_queue,Monitor Queue Register" hexmask.long.word 0x4 0.--15. 1. "QUEUE,Queue to monitor." line.long 0x8 "VIRT_ALIAS_2_RINGACC0__CFG__MON_data0,Monitor Data Register" hexmask.long 0x8 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pushes. For mode 2 this is read-write and the low threshold value. For mode 3 this is read only and the low watermark. For mode 4 this is read only and the starvation count." line.long 0xC "VIRT_ALIAS_2_RINGACC0__CFG__MON_data1,Monitor Data Register" hexmask.long 0xC 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pops. For mode 2 this is read-write and the high threshold value. For mode 3 this is read only and the high watermark. For mode 4 this is not used." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_2_RINGACC0_SRC_FIFOS (NAVSS0_RINGACC_0_VIRT_ALIAS_2_RINGACC0_SRC_FIFOS)" base ad:0x4B28000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_RINGACC0__SRC__FIFOS_RING_HEAD_DATA,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_2_RINGACC0__SRC__FIFOS_RING_TAIL_DATA,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_2_RINGACC0__SRC__FIFOS_PEEK_HEAD_DATA,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." rgroup.long 0x600++0x3 line.long 0x0 "VIRT_ALIAS_2_RINGACC0__SRC__FIFOS_PEEK_TAIL_DATA,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_2_RINGACC0_CFG_RT (NAVSS0_RINGACC_0_VIRT_ALIAS_2_RINGACC0_CFG_RT)" base ad:0x4B2C000000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_RINGACC0__CFG__RT_RT_DB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0xF line.long 0x0 "VIRT_ALIAS_2_RINGACC0__CFG__RT_RT_OCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring.." hexmask.long.tbyte 0x0 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0x4 "VIRT_ALIAS_2_RINGACC0__CFG__RT_RT_INDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel." hexmask.long.tbyte 0x4 0.--19. 1. "INDX,Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." line.long 0x8 "VIRT_ALIAS_2_RINGACC0__CFG__RT_RT_HWOCC,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a.." hexmask.long.tbyte 0x8 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0xC "VIRT_ALIAS_2_RINGACC0__CFG__RT_RT_HWINDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel." hexmask.long.tbyte 0xC 0.--19. 1. "INDX,Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_3_RINGACC0_CFG (NAVSS0_RINGACC_0_VIRT_ALIAS_3_RINGACC0_CFG)" base ad:0x4B31080000 rgroup.long 0x40++0x13 line.long 0x0 "VIRT_ALIAS_3_RINGACC0__CFG__CFG_BA_LO,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Tx Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_3_RINGACC0__CFG__CFG_BA_HI,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of.." hexmask.long.word 0x4 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_3_RINGACC0__CFG__CFG_SIZE,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to.." bitfld.long 0x8 30.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3" bitfld.long 0x8 24.--26. "ELSIZE,Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED" "?,?,?,?,?,?,?,7: RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number." line.long 0xC "VIRT_ALIAS_3_RINGACC0__CFG__CFG_EVT,The Ring Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote the occurrence of an up event [empty to not-empty] or a down event [non-empty to empty] for this ring." hexmask.long.word 0xC 0.--15. 1. "EVT,Defines the event for this ring or queue." line.long 0x10 "VIRT_ALIAS_3_RINGACC0__CFG__CFG_ORDERID,The Ring OrderID Register contains the bus orderid value for the ring memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for this ring or queue." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_3_RINGACC0_CFG_GCFG (NAVSS0_RINGACC_0_VIRT_ALIAS_3_RINGACC0_CFG_GCFG)" base ad:0x4B31160000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_RINGACC0__CFG__GCFG_revision,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_RINGACC0__CFG__GCFG_trace_ctl,Trace Control Register" bitfld.long 0x0 31. "EN,Trace enable 0 = disable 1 = enable." "0: disable,1: enable" bitfld.long 0x0 30. "ALL_QUEUES,Trace everything 0 = only the selected queue 1 = every queue." "0: only the selected queue,1: every queue" bitfld.long 0x0 29. "MSG,Trace message data 0 = include only the operation 1 = include message data." "0: include only the operation,1: include message data" newline hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number when tracing a single queue." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_3_RINGACC0__CFG__GCFG_overflow,Overflow Queue Register" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue to send overflow messages. A value of 0xffff will disable the overflow function." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_3_RINGACC0__CFG__GCFG_error_evt,The Error Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote detection of a ring memory transaction bus error." hexmask.long.word 0x0 0.--15. 1. "EVT,Event to send when detecting a bus error." rgroup.long 0x44++0x3 line.long 0x0 "VIRT_ALIAS_3_RINGACC0__CFG__GCFG_error_log,Error Log Register. A read of this register will clear the pending error log event and allow a new error to be captured. It does not clear the contents of this register which are only valid while the error event.." bitfld.long 0x0 31. "PUSH,Bus error was caused by a push. 0 = pop. 1 = push." "0: pop,1: push" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue that received the bus error." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_3_RINGACC0_CFG_MON (NAVSS0_RINGACC_0_VIRT_ALIAS_3_RINGACC0_CFG_MON)" base ad:0x4B32000000 rgroup.long 0x0++0xF line.long 0x0 "VIRT_ALIAS_3_RINGACC0__CFG__MON_control,Monitor Control Register" hexmask.long.word 0x0 16.--31. 1. "EVT,Event to produce." hexmask.long.byte 0x0 8.--11. 1. "SOURCE,Monitor source selection. 0 = element count. 1 = reserved. 2 = reserved." bitfld.long 0x0 0.--2. "MODE,Monitor Mode. 0 = disabled. 1 = push/pop statistics capture. 2 = low/high threshold checks. 3 = low/high watermarking. 4 = starvation counting." "0: disabled,1: push/pop statistics capture,2: low/high threshold checks,3: low/high watermarking,4: starvation counting,?,?,?" line.long 0x4 "VIRT_ALIAS_3_RINGACC0__CFG__MON_queue,Monitor Queue Register" hexmask.long.word 0x4 0.--15. 1. "QUEUE,Queue to monitor." line.long 0x8 "VIRT_ALIAS_3_RINGACC0__CFG__MON_data0,Monitor Data Register" hexmask.long 0x8 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pushes. For mode 2 this is read-write and the low threshold value. For mode 3 this is read only and the low watermark. For mode 4 this is read only and the starvation count." line.long 0xC "VIRT_ALIAS_3_RINGACC0__CFG__MON_data1,Monitor Data Register" hexmask.long 0xC 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pops. For mode 2 this is read-write and the high threshold value. For mode 3 this is read only and the high watermark. For mode 4 this is not used." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_3_RINGACC0_SRC_FIFOS (NAVSS0_RINGACC_0_VIRT_ALIAS_3_RINGACC0_SRC_FIFOS)" base ad:0x4B38000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_RINGACC0__SRC__FIFOS_RING_HEAD_DATA,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_3_RINGACC0__SRC__FIFOS_RING_TAIL_DATA,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_3_RINGACC0__SRC__FIFOS_PEEK_HEAD_DATA,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." rgroup.long 0x600++0x3 line.long 0x0 "VIRT_ALIAS_3_RINGACC0__SRC__FIFOS_PEEK_TAIL_DATA,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_3_RINGACC0_CFG_RT (NAVSS0_RINGACC_0_VIRT_ALIAS_3_RINGACC0_CFG_RT)" base ad:0x4B3C000000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_RINGACC0__CFG__RT_RT_DB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0xF line.long 0x0 "VIRT_ALIAS_3_RINGACC0__CFG__RT_RT_OCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring.." hexmask.long.tbyte 0x0 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0x4 "VIRT_ALIAS_3_RINGACC0__CFG__RT_RT_INDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel." hexmask.long.tbyte 0x4 0.--19. 1. "INDX,Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." line.long 0x8 "VIRT_ALIAS_3_RINGACC0__CFG__RT_RT_HWOCC,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a.." hexmask.long.tbyte 0x8 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0xC "VIRT_ALIAS_3_RINGACC0__CFG__RT_RT_HWINDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel." hexmask.long.tbyte 0xC 0.--19. 1. "INDX,Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_4_RINGACC0_CFG (NAVSS0_RINGACC_0_VIRT_ALIAS_4_RINGACC0_CFG)" base ad:0x4B41080000 rgroup.long 0x40++0x13 line.long 0x0 "VIRT_ALIAS_4_RINGACC0__CFG__CFG_BA_LO,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Tx Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_4_RINGACC0__CFG__CFG_BA_HI,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of.." hexmask.long.word 0x4 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_4_RINGACC0__CFG__CFG_SIZE,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to.." bitfld.long 0x8 30.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3" bitfld.long 0x8 24.--26. "ELSIZE,Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED" "?,?,?,?,?,?,?,7: RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number." line.long 0xC "VIRT_ALIAS_4_RINGACC0__CFG__CFG_EVT,The Ring Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote the occurrence of an up event [empty to not-empty] or a down event [non-empty to empty] for this ring." hexmask.long.word 0xC 0.--15. 1. "EVT,Defines the event for this ring or queue." line.long 0x10 "VIRT_ALIAS_4_RINGACC0__CFG__CFG_ORDERID,The Ring OrderID Register contains the bus orderid value for the ring memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for this ring or queue." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_4_RINGACC0_CFG_GCFG (NAVSS0_RINGACC_0_VIRT_ALIAS_4_RINGACC0_CFG_GCFG)" base ad:0x4B41160000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_RINGACC0__CFG__GCFG_revision,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_RINGACC0__CFG__GCFG_trace_ctl,Trace Control Register" bitfld.long 0x0 31. "EN,Trace enable 0 = disable 1 = enable." "0: disable,1: enable" bitfld.long 0x0 30. "ALL_QUEUES,Trace everything 0 = only the selected queue 1 = every queue." "0: only the selected queue,1: every queue" bitfld.long 0x0 29. "MSG,Trace message data 0 = include only the operation 1 = include message data." "0: include only the operation,1: include message data" newline hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number when tracing a single queue." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_4_RINGACC0__CFG__GCFG_overflow,Overflow Queue Register" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue to send overflow messages. A value of 0xffff will disable the overflow function." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_4_RINGACC0__CFG__GCFG_error_evt,The Error Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote detection of a ring memory transaction bus error." hexmask.long.word 0x0 0.--15. 1. "EVT,Event to send when detecting a bus error." rgroup.long 0x44++0x3 line.long 0x0 "VIRT_ALIAS_4_RINGACC0__CFG__GCFG_error_log,Error Log Register. A read of this register will clear the pending error log event and allow a new error to be captured. It does not clear the contents of this register which are only valid while the error event.." bitfld.long 0x0 31. "PUSH,Bus error was caused by a push. 0 = pop. 1 = push." "0: pop,1: push" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue that received the bus error." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_4_RINGACC0_CFG_MON (NAVSS0_RINGACC_0_VIRT_ALIAS_4_RINGACC0_CFG_MON)" base ad:0x4B42000000 rgroup.long 0x0++0xF line.long 0x0 "VIRT_ALIAS_4_RINGACC0__CFG__MON_control,Monitor Control Register" hexmask.long.word 0x0 16.--31. 1. "EVT,Event to produce." hexmask.long.byte 0x0 8.--11. 1. "SOURCE,Monitor source selection. 0 = element count. 1 = reserved. 2 = reserved." bitfld.long 0x0 0.--2. "MODE,Monitor Mode. 0 = disabled. 1 = push/pop statistics capture. 2 = low/high threshold checks. 3 = low/high watermarking. 4 = starvation counting." "0: disabled,1: push/pop statistics capture,2: low/high threshold checks,3: low/high watermarking,4: starvation counting,?,?,?" line.long 0x4 "VIRT_ALIAS_4_RINGACC0__CFG__MON_queue,Monitor Queue Register" hexmask.long.word 0x4 0.--15. 1. "QUEUE,Queue to monitor." line.long 0x8 "VIRT_ALIAS_4_RINGACC0__CFG__MON_data0,Monitor Data Register" hexmask.long 0x8 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pushes. For mode 2 this is read-write and the low threshold value. For mode 3 this is read only and the low watermark. For mode 4 this is read only and the starvation count." line.long 0xC "VIRT_ALIAS_4_RINGACC0__CFG__MON_data1,Monitor Data Register" hexmask.long 0xC 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pops. For mode 2 this is read-write and the high threshold value. For mode 3 this is read only and the high watermark. For mode 4 this is not used." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_4_RINGACC0_SRC_FIFOS (NAVSS0_RINGACC_0_VIRT_ALIAS_4_RINGACC0_SRC_FIFOS)" base ad:0x4B48000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_RINGACC0__SRC__FIFOS_RING_HEAD_DATA,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_4_RINGACC0__SRC__FIFOS_RING_TAIL_DATA,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_4_RINGACC0__SRC__FIFOS_PEEK_HEAD_DATA,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." rgroup.long 0x600++0x3 line.long 0x0 "VIRT_ALIAS_4_RINGACC0__SRC__FIFOS_PEEK_TAIL_DATA,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_4_RINGACC0_CFG_RT (NAVSS0_RINGACC_0_VIRT_ALIAS_4_RINGACC0_CFG_RT)" base ad:0x4B4C000000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_RINGACC0__CFG__RT_RT_DB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0xF line.long 0x0 "VIRT_ALIAS_4_RINGACC0__CFG__RT_RT_OCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring.." hexmask.long.tbyte 0x0 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0x4 "VIRT_ALIAS_4_RINGACC0__CFG__RT_RT_INDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel." hexmask.long.tbyte 0x4 0.--19. 1. "INDX,Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." line.long 0x8 "VIRT_ALIAS_4_RINGACC0__CFG__RT_RT_HWOCC,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a.." hexmask.long.tbyte 0x8 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0xC "VIRT_ALIAS_4_RINGACC0__CFG__RT_RT_HWINDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel." hexmask.long.tbyte 0xC 0.--19. 1. "INDX,Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_5_RINGACC0_CFG (NAVSS0_RINGACC_0_VIRT_ALIAS_5_RINGACC0_CFG)" base ad:0x4B51080000 rgroup.long 0x40++0x13 line.long 0x0 "VIRT_ALIAS_5_RINGACC0__CFG__CFG_BA_LO,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Tx Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_5_RINGACC0__CFG__CFG_BA_HI,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of.." hexmask.long.word 0x4 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_5_RINGACC0__CFG__CFG_SIZE,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to.." bitfld.long 0x8 30.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3" bitfld.long 0x8 24.--26. "ELSIZE,Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED" "?,?,?,?,?,?,?,7: RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number." line.long 0xC "VIRT_ALIAS_5_RINGACC0__CFG__CFG_EVT,The Ring Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote the occurrence of an up event [empty to not-empty] or a down event [non-empty to empty] for this ring." hexmask.long.word 0xC 0.--15. 1. "EVT,Defines the event for this ring or queue." line.long 0x10 "VIRT_ALIAS_5_RINGACC0__CFG__CFG_ORDERID,The Ring OrderID Register contains the bus orderid value for the ring memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for this ring or queue." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_5_RINGACC0_CFG_GCFG (NAVSS0_RINGACC_0_VIRT_ALIAS_5_RINGACC0_CFG_GCFG)" base ad:0x4B51160000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_RINGACC0__CFG__GCFG_revision,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_RINGACC0__CFG__GCFG_trace_ctl,Trace Control Register" bitfld.long 0x0 31. "EN,Trace enable 0 = disable 1 = enable." "0: disable,1: enable" bitfld.long 0x0 30. "ALL_QUEUES,Trace everything 0 = only the selected queue 1 = every queue." "0: only the selected queue,1: every queue" bitfld.long 0x0 29. "MSG,Trace message data 0 = include only the operation 1 = include message data." "0: include only the operation,1: include message data" newline hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number when tracing a single queue." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_5_RINGACC0__CFG__GCFG_overflow,Overflow Queue Register" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue to send overflow messages. A value of 0xffff will disable the overflow function." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_5_RINGACC0__CFG__GCFG_error_evt,The Error Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote detection of a ring memory transaction bus error." hexmask.long.word 0x0 0.--15. 1. "EVT,Event to send when detecting a bus error." rgroup.long 0x44++0x3 line.long 0x0 "VIRT_ALIAS_5_RINGACC0__CFG__GCFG_error_log,Error Log Register. A read of this register will clear the pending error log event and allow a new error to be captured. It does not clear the contents of this register which are only valid while the error event.." bitfld.long 0x0 31. "PUSH,Bus error was caused by a push. 0 = pop. 1 = push." "0: pop,1: push" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue that received the bus error." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_5_RINGACC0_CFG_MON (NAVSS0_RINGACC_0_VIRT_ALIAS_5_RINGACC0_CFG_MON)" base ad:0x4B52000000 rgroup.long 0x0++0xF line.long 0x0 "VIRT_ALIAS_5_RINGACC0__CFG__MON_control,Monitor Control Register" hexmask.long.word 0x0 16.--31. 1. "EVT,Event to produce." hexmask.long.byte 0x0 8.--11. 1. "SOURCE,Monitor source selection. 0 = element count. 1 = reserved. 2 = reserved." bitfld.long 0x0 0.--2. "MODE,Monitor Mode. 0 = disabled. 1 = push/pop statistics capture. 2 = low/high threshold checks. 3 = low/high watermarking. 4 = starvation counting." "0: disabled,1: push/pop statistics capture,2: low/high threshold checks,3: low/high watermarking,4: starvation counting,?,?,?" line.long 0x4 "VIRT_ALIAS_5_RINGACC0__CFG__MON_queue,Monitor Queue Register" hexmask.long.word 0x4 0.--15. 1. "QUEUE,Queue to monitor." line.long 0x8 "VIRT_ALIAS_5_RINGACC0__CFG__MON_data0,Monitor Data Register" hexmask.long 0x8 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pushes. For mode 2 this is read-write and the low threshold value. For mode 3 this is read only and the low watermark. For mode 4 this is read only and the starvation count." line.long 0xC "VIRT_ALIAS_5_RINGACC0__CFG__MON_data1,Monitor Data Register" hexmask.long 0xC 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pops. For mode 2 this is read-write and the high threshold value. For mode 3 this is read only and the high watermark. For mode 4 this is not used." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_5_RINGACC0_SRC_FIFOS (NAVSS0_RINGACC_0_VIRT_ALIAS_5_RINGACC0_SRC_FIFOS)" base ad:0x4B58000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_RINGACC0__SRC__FIFOS_RING_HEAD_DATA,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_5_RINGACC0__SRC__FIFOS_RING_TAIL_DATA,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_5_RINGACC0__SRC__FIFOS_PEEK_HEAD_DATA,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." rgroup.long 0x600++0x3 line.long 0x0 "VIRT_ALIAS_5_RINGACC0__SRC__FIFOS_PEEK_TAIL_DATA,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_5_RINGACC0_CFG_RT (NAVSS0_RINGACC_0_VIRT_ALIAS_5_RINGACC0_CFG_RT)" base ad:0x4B5C000000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_RINGACC0__CFG__RT_RT_DB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0xF line.long 0x0 "VIRT_ALIAS_5_RINGACC0__CFG__RT_RT_OCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring.." hexmask.long.tbyte 0x0 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0x4 "VIRT_ALIAS_5_RINGACC0__CFG__RT_RT_INDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel." hexmask.long.tbyte 0x4 0.--19. 1. "INDX,Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." line.long 0x8 "VIRT_ALIAS_5_RINGACC0__CFG__RT_RT_HWOCC,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a.." hexmask.long.tbyte 0x8 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0xC "VIRT_ALIAS_5_RINGACC0__CFG__RT_RT_HWINDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel." hexmask.long.tbyte 0xC 0.--19. 1. "INDX,Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_6_RINGACC0_CFG (NAVSS0_RINGACC_0_VIRT_ALIAS_6_RINGACC0_CFG)" base ad:0x4B61080000 rgroup.long 0x40++0x13 line.long 0x0 "VIRT_ALIAS_6_RINGACC0__CFG__CFG_BA_LO,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Tx Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_6_RINGACC0__CFG__CFG_BA_HI,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of.." hexmask.long.word 0x4 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_6_RINGACC0__CFG__CFG_SIZE,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to.." bitfld.long 0x8 30.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3" bitfld.long 0x8 24.--26. "ELSIZE,Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED" "?,?,?,?,?,?,?,7: RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number." line.long 0xC "VIRT_ALIAS_6_RINGACC0__CFG__CFG_EVT,The Ring Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote the occurrence of an up event [empty to not-empty] or a down event [non-empty to empty] for this ring." hexmask.long.word 0xC 0.--15. 1. "EVT,Defines the event for this ring or queue." line.long 0x10 "VIRT_ALIAS_6_RINGACC0__CFG__CFG_ORDERID,The Ring OrderID Register contains the bus orderid value for the ring memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for this ring or queue." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_6_RINGACC0_CFG_GCFG (NAVSS0_RINGACC_0_VIRT_ALIAS_6_RINGACC0_CFG_GCFG)" base ad:0x4B61160000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_RINGACC0__CFG__GCFG_revision,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_RINGACC0__CFG__GCFG_trace_ctl,Trace Control Register" bitfld.long 0x0 31. "EN,Trace enable 0 = disable 1 = enable." "0: disable,1: enable" bitfld.long 0x0 30. "ALL_QUEUES,Trace everything 0 = only the selected queue 1 = every queue." "0: only the selected queue,1: every queue" bitfld.long 0x0 29. "MSG,Trace message data 0 = include only the operation 1 = include message data." "0: include only the operation,1: include message data" newline hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number when tracing a single queue." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_6_RINGACC0__CFG__GCFG_overflow,Overflow Queue Register" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue to send overflow messages. A value of 0xffff will disable the overflow function." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_6_RINGACC0__CFG__GCFG_error_evt,The Error Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote detection of a ring memory transaction bus error." hexmask.long.word 0x0 0.--15. 1. "EVT,Event to send when detecting a bus error." rgroup.long 0x44++0x3 line.long 0x0 "VIRT_ALIAS_6_RINGACC0__CFG__GCFG_error_log,Error Log Register. A read of this register will clear the pending error log event and allow a new error to be captured. It does not clear the contents of this register which are only valid while the error event.." bitfld.long 0x0 31. "PUSH,Bus error was caused by a push. 0 = pop. 1 = push." "0: pop,1: push" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue that received the bus error." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_6_RINGACC0_CFG_MON (NAVSS0_RINGACC_0_VIRT_ALIAS_6_RINGACC0_CFG_MON)" base ad:0x4B62000000 rgroup.long 0x0++0xF line.long 0x0 "VIRT_ALIAS_6_RINGACC0__CFG__MON_control,Monitor Control Register" hexmask.long.word 0x0 16.--31. 1. "EVT,Event to produce." hexmask.long.byte 0x0 8.--11. 1. "SOURCE,Monitor source selection. 0 = element count. 1 = reserved. 2 = reserved." bitfld.long 0x0 0.--2. "MODE,Monitor Mode. 0 = disabled. 1 = push/pop statistics capture. 2 = low/high threshold checks. 3 = low/high watermarking. 4 = starvation counting." "0: disabled,1: push/pop statistics capture,2: low/high threshold checks,3: low/high watermarking,4: starvation counting,?,?,?" line.long 0x4 "VIRT_ALIAS_6_RINGACC0__CFG__MON_queue,Monitor Queue Register" hexmask.long.word 0x4 0.--15. 1. "QUEUE,Queue to monitor." line.long 0x8 "VIRT_ALIAS_6_RINGACC0__CFG__MON_data0,Monitor Data Register" hexmask.long 0x8 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pushes. For mode 2 this is read-write and the low threshold value. For mode 3 this is read only and the low watermark. For mode 4 this is read only and the starvation count." line.long 0xC "VIRT_ALIAS_6_RINGACC0__CFG__MON_data1,Monitor Data Register" hexmask.long 0xC 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pops. For mode 2 this is read-write and the high threshold value. For mode 3 this is read only and the high watermark. For mode 4 this is not used." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_6_RINGACC0_SRC_FIFOS (NAVSS0_RINGACC_0_VIRT_ALIAS_6_RINGACC0_SRC_FIFOS)" base ad:0x4B68000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_RINGACC0__SRC__FIFOS_RING_HEAD_DATA,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_6_RINGACC0__SRC__FIFOS_RING_TAIL_DATA,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_6_RINGACC0__SRC__FIFOS_PEEK_HEAD_DATA,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." rgroup.long 0x600++0x3 line.long 0x0 "VIRT_ALIAS_6_RINGACC0__SRC__FIFOS_PEEK_TAIL_DATA,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_6_RINGACC0_CFG_RT (NAVSS0_RINGACC_0_VIRT_ALIAS_6_RINGACC0_CFG_RT)" base ad:0x4B6C000000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_RINGACC0__CFG__RT_RT_DB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0xF line.long 0x0 "VIRT_ALIAS_6_RINGACC0__CFG__RT_RT_OCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring.." hexmask.long.tbyte 0x0 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0x4 "VIRT_ALIAS_6_RINGACC0__CFG__RT_RT_INDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel." hexmask.long.tbyte 0x4 0.--19. 1. "INDX,Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." line.long 0x8 "VIRT_ALIAS_6_RINGACC0__CFG__RT_RT_HWOCC,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a.." hexmask.long.tbyte 0x8 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0xC "VIRT_ALIAS_6_RINGACC0__CFG__RT_RT_HWINDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel." hexmask.long.tbyte 0xC 0.--19. 1. "INDX,Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_7_RINGACC0_CFG (NAVSS0_RINGACC_0_VIRT_ALIAS_7_RINGACC0_CFG)" base ad:0x4B71080000 rgroup.long 0x40++0x13 line.long 0x0 "VIRT_ALIAS_7_RINGACC0__CFG__CFG_BA_LO,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Tx Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_7_RINGACC0__CFG__CFG_BA_HI,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of.." hexmask.long.word 0x4 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_7_RINGACC0__CFG__CFG_SIZE,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to.." bitfld.long 0x8 30.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3" bitfld.long 0x8 24.--26. "ELSIZE,Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED" "?,?,?,?,?,?,?,7: RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number." line.long 0xC "VIRT_ALIAS_7_RINGACC0__CFG__CFG_EVT,The Ring Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote the occurrence of an up event [empty to not-empty] or a down event [non-empty to empty] for this ring." hexmask.long.word 0xC 0.--15. 1. "EVT,Defines the event for this ring or queue." line.long 0x10 "VIRT_ALIAS_7_RINGACC0__CFG__CFG_ORDERID,The Ring OrderID Register contains the bus orderid value for the ring memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for this ring or queue." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_7_RINGACC0_CFG_GCFG (NAVSS0_RINGACC_0_VIRT_ALIAS_7_RINGACC0_CFG_GCFG)" base ad:0x4B71160000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_RINGACC0__CFG__GCFG_revision,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_RINGACC0__CFG__GCFG_trace_ctl,Trace Control Register" bitfld.long 0x0 31. "EN,Trace enable 0 = disable 1 = enable." "0: disable,1: enable" bitfld.long 0x0 30. "ALL_QUEUES,Trace everything 0 = only the selected queue 1 = every queue." "0: only the selected queue,1: every queue" bitfld.long 0x0 29. "MSG,Trace message data 0 = include only the operation 1 = include message data." "0: include only the operation,1: include message data" newline hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number when tracing a single queue." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_7_RINGACC0__CFG__GCFG_overflow,Overflow Queue Register" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue to send overflow messages. A value of 0xffff will disable the overflow function." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_7_RINGACC0__CFG__GCFG_error_evt,The Error Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote detection of a ring memory transaction bus error." hexmask.long.word 0x0 0.--15. 1. "EVT,Event to send when detecting a bus error." rgroup.long 0x44++0x3 line.long 0x0 "VIRT_ALIAS_7_RINGACC0__CFG__GCFG_error_log,Error Log Register. A read of this register will clear the pending error log event and allow a new error to be captured. It does not clear the contents of this register which are only valid while the error event.." bitfld.long 0x0 31. "PUSH,Bus error was caused by a push. 0 = pop. 1 = push." "0: pop,1: push" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue that received the bus error." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_7_RINGACC0_CFG_MON (NAVSS0_RINGACC_0_VIRT_ALIAS_7_RINGACC0_CFG_MON)" base ad:0x4B72000000 rgroup.long 0x0++0xF line.long 0x0 "VIRT_ALIAS_7_RINGACC0__CFG__MON_control,Monitor Control Register" hexmask.long.word 0x0 16.--31. 1. "EVT,Event to produce." hexmask.long.byte 0x0 8.--11. 1. "SOURCE,Monitor source selection. 0 = element count. 1 = reserved. 2 = reserved." bitfld.long 0x0 0.--2. "MODE,Monitor Mode. 0 = disabled. 1 = push/pop statistics capture. 2 = low/high threshold checks. 3 = low/high watermarking. 4 = starvation counting." "0: disabled,1: push/pop statistics capture,2: low/high threshold checks,3: low/high watermarking,4: starvation counting,?,?,?" line.long 0x4 "VIRT_ALIAS_7_RINGACC0__CFG__MON_queue,Monitor Queue Register" hexmask.long.word 0x4 0.--15. 1. "QUEUE,Queue to monitor." line.long 0x8 "VIRT_ALIAS_7_RINGACC0__CFG__MON_data0,Monitor Data Register" hexmask.long 0x8 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pushes. For mode 2 this is read-write and the low threshold value. For mode 3 this is read only and the low watermark. For mode 4 this is read only and the starvation count." line.long 0xC "VIRT_ALIAS_7_RINGACC0__CFG__MON_data1,Monitor Data Register" hexmask.long 0xC 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pops. For mode 2 this is read-write and the high threshold value. For mode 3 this is read only and the high watermark. For mode 4 this is not used." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_7_RINGACC0_SRC_FIFOS (NAVSS0_RINGACC_0_VIRT_ALIAS_7_RINGACC0_SRC_FIFOS)" base ad:0x4B78000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_RINGACC0__SRC__FIFOS_RING_HEAD_DATA,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_7_RINGACC0__SRC__FIFOS_RING_TAIL_DATA,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_7_RINGACC0__SRC__FIFOS_PEEK_HEAD_DATA,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." rgroup.long 0x600++0x3 line.long 0x0 "VIRT_ALIAS_7_RINGACC0__SRC__FIFOS_PEEK_TAIL_DATA,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_7_RINGACC0_CFG_RT (NAVSS0_RINGACC_0_VIRT_ALIAS_7_RINGACC0_CFG_RT)" base ad:0x4B7C000000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_RINGACC0__CFG__RT_RT_DB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0xF line.long 0x0 "VIRT_ALIAS_7_RINGACC0__CFG__RT_RT_OCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring.." hexmask.long.tbyte 0x0 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0x4 "VIRT_ALIAS_7_RINGACC0__CFG__RT_RT_INDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel." hexmask.long.tbyte 0x4 0.--19. 1. "INDX,Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." line.long 0x8 "VIRT_ALIAS_7_RINGACC0__CFG__RT_RT_HWOCC,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a.." hexmask.long.tbyte 0x8 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0xC "VIRT_ALIAS_7_RINGACC0__CFG__RT_RT_HWINDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel." hexmask.long.tbyte 0xC 0.--19. 1. "INDX,Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_8_RINGACC0_CFG (NAVSS0_RINGACC_0_VIRT_ALIAS_8_RINGACC0_CFG)" base ad:0x4B81080000 rgroup.long 0x40++0x13 line.long 0x0 "VIRT_ALIAS_8_RINGACC0__CFG__CFG_BA_LO,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Tx Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_8_RINGACC0__CFG__CFG_BA_HI,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of.." hexmask.long.word 0x4 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_8_RINGACC0__CFG__CFG_SIZE,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to.." bitfld.long 0x8 30.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3" bitfld.long 0x8 24.--26. "ELSIZE,Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED" "?,?,?,?,?,?,?,7: RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number." line.long 0xC "VIRT_ALIAS_8_RINGACC0__CFG__CFG_EVT,The Ring Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote the occurrence of an up event [empty to not-empty] or a down event [non-empty to empty] for this ring." hexmask.long.word 0xC 0.--15. 1. "EVT,Defines the event for this ring or queue." line.long 0x10 "VIRT_ALIAS_8_RINGACC0__CFG__CFG_ORDERID,The Ring OrderID Register contains the bus orderid value for the ring memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for this ring or queue." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_8_RINGACC0_CFG_GCFG (NAVSS0_RINGACC_0_VIRT_ALIAS_8_RINGACC0_CFG_GCFG)" base ad:0x4B81160000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_RINGACC0__CFG__GCFG_revision,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_RINGACC0__CFG__GCFG_trace_ctl,Trace Control Register" bitfld.long 0x0 31. "EN,Trace enable 0 = disable 1 = enable." "0: disable,1: enable" bitfld.long 0x0 30. "ALL_QUEUES,Trace everything 0 = only the selected queue 1 = every queue." "0: only the selected queue,1: every queue" bitfld.long 0x0 29. "MSG,Trace message data 0 = include only the operation 1 = include message data." "0: include only the operation,1: include message data" newline hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number when tracing a single queue." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_8_RINGACC0__CFG__GCFG_overflow,Overflow Queue Register" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue to send overflow messages. A value of 0xffff will disable the overflow function." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_8_RINGACC0__CFG__GCFG_error_evt,The Error Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote detection of a ring memory transaction bus error." hexmask.long.word 0x0 0.--15. 1. "EVT,Event to send when detecting a bus error." rgroup.long 0x44++0x3 line.long 0x0 "VIRT_ALIAS_8_RINGACC0__CFG__GCFG_error_log,Error Log Register. A read of this register will clear the pending error log event and allow a new error to be captured. It does not clear the contents of this register which are only valid while the error event.." bitfld.long 0x0 31. "PUSH,Bus error was caused by a push. 0 = pop. 1 = push." "0: pop,1: push" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue that received the bus error." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_8_RINGACC0_CFG_MON (NAVSS0_RINGACC_0_VIRT_ALIAS_8_RINGACC0_CFG_MON)" base ad:0x4B82000000 rgroup.long 0x0++0xF line.long 0x0 "VIRT_ALIAS_8_RINGACC0__CFG__MON_control,Monitor Control Register" hexmask.long.word 0x0 16.--31. 1. "EVT,Event to produce." hexmask.long.byte 0x0 8.--11. 1. "SOURCE,Monitor source selection. 0 = element count. 1 = reserved. 2 = reserved." bitfld.long 0x0 0.--2. "MODE,Monitor Mode. 0 = disabled. 1 = push/pop statistics capture. 2 = low/high threshold checks. 3 = low/high watermarking. 4 = starvation counting." "0: disabled,1: push/pop statistics capture,2: low/high threshold checks,3: low/high watermarking,4: starvation counting,?,?,?" line.long 0x4 "VIRT_ALIAS_8_RINGACC0__CFG__MON_queue,Monitor Queue Register" hexmask.long.word 0x4 0.--15. 1. "QUEUE,Queue to monitor." line.long 0x8 "VIRT_ALIAS_8_RINGACC0__CFG__MON_data0,Monitor Data Register" hexmask.long 0x8 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pushes. For mode 2 this is read-write and the low threshold value. For mode 3 this is read only and the low watermark. For mode 4 this is read only and the starvation count." line.long 0xC "VIRT_ALIAS_8_RINGACC0__CFG__MON_data1,Monitor Data Register" hexmask.long 0xC 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pops. For mode 2 this is read-write and the high threshold value. For mode 3 this is read only and the high watermark. For mode 4 this is not used." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_8_RINGACC0_SRC_FIFOS (NAVSS0_RINGACC_0_VIRT_ALIAS_8_RINGACC0_SRC_FIFOS)" base ad:0x4B88000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_RINGACC0__SRC__FIFOS_RING_HEAD_DATA,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_8_RINGACC0__SRC__FIFOS_RING_TAIL_DATA,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_8_RINGACC0__SRC__FIFOS_PEEK_HEAD_DATA,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." rgroup.long 0x600++0x3 line.long 0x0 "VIRT_ALIAS_8_RINGACC0__SRC__FIFOS_PEEK_TAIL_DATA,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_8_RINGACC0_CFG_RT (NAVSS0_RINGACC_0_VIRT_ALIAS_8_RINGACC0_CFG_RT)" base ad:0x4B8C000000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_RINGACC0__CFG__RT_RT_DB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0xF line.long 0x0 "VIRT_ALIAS_8_RINGACC0__CFG__RT_RT_OCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring.." hexmask.long.tbyte 0x0 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0x4 "VIRT_ALIAS_8_RINGACC0__CFG__RT_RT_INDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel." hexmask.long.tbyte 0x4 0.--19. 1. "INDX,Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." line.long 0x8 "VIRT_ALIAS_8_RINGACC0__CFG__RT_RT_HWOCC,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a.." hexmask.long.tbyte 0x8 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0xC "VIRT_ALIAS_8_RINGACC0__CFG__RT_RT_HWINDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel." hexmask.long.tbyte 0xC 0.--19. 1. "INDX,Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_9_RINGACC0_CFG (NAVSS0_RINGACC_0_VIRT_ALIAS_9_RINGACC0_CFG)" base ad:0x4B91080000 rgroup.long 0x40++0x13 line.long 0x0 "VIRT_ALIAS_9_RINGACC0__CFG__CFG_BA_LO,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Tx Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_9_RINGACC0__CFG__CFG_BA_HI,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of.." hexmask.long.word 0x4 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_9_RINGACC0__CFG__CFG_SIZE,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to.." bitfld.long 0x8 30.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3" bitfld.long 0x8 24.--26. "ELSIZE,Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED" "?,?,?,?,?,?,?,7: RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number." line.long 0xC "VIRT_ALIAS_9_RINGACC0__CFG__CFG_EVT,The Ring Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote the occurrence of an up event [empty to not-empty] or a down event [non-empty to empty] for this ring." hexmask.long.word 0xC 0.--15. 1. "EVT,Defines the event for this ring or queue." line.long 0x10 "VIRT_ALIAS_9_RINGACC0__CFG__CFG_ORDERID,The Ring OrderID Register contains the bus orderid value for the ring memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for this ring or queue." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_9_RINGACC0_CFG_GCFG (NAVSS0_RINGACC_0_VIRT_ALIAS_9_RINGACC0_CFG_GCFG)" base ad:0x4B91160000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_RINGACC0__CFG__GCFG_revision,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_RINGACC0__CFG__GCFG_trace_ctl,Trace Control Register" bitfld.long 0x0 31. "EN,Trace enable 0 = disable 1 = enable." "0: disable,1: enable" bitfld.long 0x0 30. "ALL_QUEUES,Trace everything 0 = only the selected queue 1 = every queue." "0: only the selected queue,1: every queue" bitfld.long 0x0 29. "MSG,Trace message data 0 = include only the operation 1 = include message data." "0: include only the operation,1: include message data" newline hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number when tracing a single queue." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_9_RINGACC0__CFG__GCFG_overflow,Overflow Queue Register" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue to send overflow messages. A value of 0xffff will disable the overflow function." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_9_RINGACC0__CFG__GCFG_error_evt,The Error Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote detection of a ring memory transaction bus error." hexmask.long.word 0x0 0.--15. 1. "EVT,Event to send when detecting a bus error." rgroup.long 0x44++0x3 line.long 0x0 "VIRT_ALIAS_9_RINGACC0__CFG__GCFG_error_log,Error Log Register. A read of this register will clear the pending error log event and allow a new error to be captured. It does not clear the contents of this register which are only valid while the error event.." bitfld.long 0x0 31. "PUSH,Bus error was caused by a push. 0 = pop. 1 = push." "0: pop,1: push" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue that received the bus error." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_9_RINGACC0_CFG_MON (NAVSS0_RINGACC_0_VIRT_ALIAS_9_RINGACC0_CFG_MON)" base ad:0x4B92000000 rgroup.long 0x0++0xF line.long 0x0 "VIRT_ALIAS_9_RINGACC0__CFG__MON_control,Monitor Control Register" hexmask.long.word 0x0 16.--31. 1. "EVT,Event to produce." hexmask.long.byte 0x0 8.--11. 1. "SOURCE,Monitor source selection. 0 = element count. 1 = reserved. 2 = reserved." bitfld.long 0x0 0.--2. "MODE,Monitor Mode. 0 = disabled. 1 = push/pop statistics capture. 2 = low/high threshold checks. 3 = low/high watermarking. 4 = starvation counting." "0: disabled,1: push/pop statistics capture,2: low/high threshold checks,3: low/high watermarking,4: starvation counting,?,?,?" line.long 0x4 "VIRT_ALIAS_9_RINGACC0__CFG__MON_queue,Monitor Queue Register" hexmask.long.word 0x4 0.--15. 1. "QUEUE,Queue to monitor." line.long 0x8 "VIRT_ALIAS_9_RINGACC0__CFG__MON_data0,Monitor Data Register" hexmask.long 0x8 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pushes. For mode 2 this is read-write and the low threshold value. For mode 3 this is read only and the low watermark. For mode 4 this is read only and the starvation count." line.long 0xC "VIRT_ALIAS_9_RINGACC0__CFG__MON_data1,Monitor Data Register" hexmask.long 0xC 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pops. For mode 2 this is read-write and the high threshold value. For mode 3 this is read only and the high watermark. For mode 4 this is not used." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_9_RINGACC0_SRC_FIFOS (NAVSS0_RINGACC_0_VIRT_ALIAS_9_RINGACC0_SRC_FIFOS)" base ad:0x4B98000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_RINGACC0__SRC__FIFOS_RING_HEAD_DATA,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_9_RINGACC0__SRC__FIFOS_RING_TAIL_DATA,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_9_RINGACC0__SRC__FIFOS_PEEK_HEAD_DATA,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." rgroup.long 0x600++0x3 line.long 0x0 "VIRT_ALIAS_9_RINGACC0__SRC__FIFOS_PEEK_TAIL_DATA,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_9_RINGACC0_CFG_RT (NAVSS0_RINGACC_0_VIRT_ALIAS_9_RINGACC0_CFG_RT)" base ad:0x4B9C000000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_RINGACC0__CFG__RT_RT_DB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0xF line.long 0x0 "VIRT_ALIAS_9_RINGACC0__CFG__RT_RT_OCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring.." hexmask.long.tbyte 0x0 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0x4 "VIRT_ALIAS_9_RINGACC0__CFG__RT_RT_INDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel." hexmask.long.tbyte 0x4 0.--19. 1. "INDX,Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." line.long 0x8 "VIRT_ALIAS_9_RINGACC0__CFG__RT_RT_HWOCC,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a.." hexmask.long.tbyte 0x8 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0xC "VIRT_ALIAS_9_RINGACC0__CFG__RT_RT_HWINDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel." hexmask.long.tbyte 0xC 0.--19. 1. "INDX,Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_10_RINGACC0_CFG (NAVSS0_RINGACC_0_VIRT_ALIAS_10_RINGACC0_CFG)" base ad:0x4BA1080000 rgroup.long 0x40++0x13 line.long 0x0 "VIRT_ALIAS_10_RINGACC0__CFG__CFG_BA_LO,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Tx Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_10_RINGACC0__CFG__CFG_BA_HI,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size.." hexmask.long.word 0x4 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_10_RINGACC0__CFG__CFG_SIZE,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to.." bitfld.long 0x8 30.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3" bitfld.long 0x8 24.--26. "ELSIZE,Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED" "?,?,?,?,?,?,?,7: RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number." line.long 0xC "VIRT_ALIAS_10_RINGACC0__CFG__CFG_EVT,The Ring Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote the occurrence of an up event [empty to not-empty] or a down event [non-empty to empty] for this ring." hexmask.long.word 0xC 0.--15. 1. "EVT,Defines the event for this ring or queue." line.long 0x10 "VIRT_ALIAS_10_RINGACC0__CFG__CFG_ORDERID,The Ring OrderID Register contains the bus orderid value for the ring memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for this ring or queue." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_10_RINGACC0_CFG_GCFG (NAVSS0_RINGACC_0_VIRT_ALIAS_10_RINGACC0_CFG_GCFG)" base ad:0x4BA1160000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_RINGACC0__CFG__GCFG_revision,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_RINGACC0__CFG__GCFG_trace_ctl,Trace Control Register" bitfld.long 0x0 31. "EN,Trace enable 0 = disable 1 = enable." "0: disable,1: enable" bitfld.long 0x0 30. "ALL_QUEUES,Trace everything 0 = only the selected queue 1 = every queue." "0: only the selected queue,1: every queue" bitfld.long 0x0 29. "MSG,Trace message data 0 = include only the operation 1 = include message data." "0: include only the operation,1: include message data" newline hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number when tracing a single queue." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_10_RINGACC0__CFG__GCFG_overflow,Overflow Queue Register" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue to send overflow messages. A value of 0xffff will disable the overflow function." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_10_RINGACC0__CFG__GCFG_error_evt,The Error Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote detection of a ring memory transaction bus error." hexmask.long.word 0x0 0.--15. 1. "EVT,Event to send when detecting a bus error." rgroup.long 0x44++0x3 line.long 0x0 "VIRT_ALIAS_10_RINGACC0__CFG__GCFG_error_log,Error Log Register. A read of this register will clear the pending error log event and allow a new error to be captured. It does not clear the contents of this register which are only valid while the error.." bitfld.long 0x0 31. "PUSH,Bus error was caused by a push. 0 = pop. 1 = push." "0: pop,1: push" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue that received the bus error." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_10_RINGACC0_CFG_MON (NAVSS0_RINGACC_0_VIRT_ALIAS_10_RINGACC0_CFG_MON)" base ad:0x4BA2000000 rgroup.long 0x0++0xF line.long 0x0 "VIRT_ALIAS_10_RINGACC0__CFG__MON_control,Monitor Control Register" hexmask.long.word 0x0 16.--31. 1. "EVT,Event to produce." hexmask.long.byte 0x0 8.--11. 1. "SOURCE,Monitor source selection. 0 = element count. 1 = reserved. 2 = reserved." bitfld.long 0x0 0.--2. "MODE,Monitor Mode. 0 = disabled. 1 = push/pop statistics capture. 2 = low/high threshold checks. 3 = low/high watermarking. 4 = starvation counting." "0: disabled,1: push/pop statistics capture,2: low/high threshold checks,3: low/high watermarking,4: starvation counting,?,?,?" line.long 0x4 "VIRT_ALIAS_10_RINGACC0__CFG__MON_queue,Monitor Queue Register" hexmask.long.word 0x4 0.--15. 1. "QUEUE,Queue to monitor." line.long 0x8 "VIRT_ALIAS_10_RINGACC0__CFG__MON_data0,Monitor Data Register" hexmask.long 0x8 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pushes. For mode 2 this is read-write and the low threshold value. For mode 3 this is read only and the low watermark. For mode 4 this is read only and the starvation count." line.long 0xC "VIRT_ALIAS_10_RINGACC0__CFG__MON_data1,Monitor Data Register" hexmask.long 0xC 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pops. For mode 2 this is read-write and the high threshold value. For mode 3 this is read only and the high watermark. For mode 4 this is not used." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_10_RINGACC0_SRC_FIFOS (NAVSS0_RINGACC_0_VIRT_ALIAS_10_RINGACC0_SRC_FIFOS)" base ad:0x4BA8000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_RINGACC0__SRC__FIFOS_RING_HEAD_DATA,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_10_RINGACC0__SRC__FIFOS_RING_TAIL_DATA,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_10_RINGACC0__SRC__FIFOS_PEEK_HEAD_DATA,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." rgroup.long 0x600++0x3 line.long 0x0 "VIRT_ALIAS_10_RINGACC0__SRC__FIFOS_PEEK_TAIL_DATA,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_10_RINGACC0_CFG_RT (NAVSS0_RINGACC_0_VIRT_ALIAS_10_RINGACC0_CFG_RT)" base ad:0x4BAC000000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_RINGACC0__CFG__RT_RT_DB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0xF line.long 0x0 "VIRT_ALIAS_10_RINGACC0__CFG__RT_RT_OCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.tbyte 0x0 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0x4 "VIRT_ALIAS_10_RINGACC0__CFG__RT_RT_INDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel." hexmask.long.tbyte 0x4 0.--19. 1. "INDX,Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." line.long 0x8 "VIRT_ALIAS_10_RINGACC0__CFG__RT_RT_HWOCC,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create.." hexmask.long.tbyte 0x8 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0xC "VIRT_ALIAS_10_RINGACC0__CFG__RT_RT_HWINDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel." hexmask.long.tbyte 0xC 0.--19. 1. "INDX,Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_11_RINGACC0_CFG (NAVSS0_RINGACC_0_VIRT_ALIAS_11_RINGACC0_CFG)" base ad:0x4BB1080000 rgroup.long 0x40++0x13 line.long 0x0 "VIRT_ALIAS_11_RINGACC0__CFG__CFG_BA_LO,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Tx Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_11_RINGACC0__CFG__CFG_BA_HI,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size.." hexmask.long.word 0x4 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_11_RINGACC0__CFG__CFG_SIZE,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to.." bitfld.long 0x8 30.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3" bitfld.long 0x8 24.--26. "ELSIZE,Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED" "?,?,?,?,?,?,?,7: RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number." line.long 0xC "VIRT_ALIAS_11_RINGACC0__CFG__CFG_EVT,The Ring Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote the occurrence of an up event [empty to not-empty] or a down event [non-empty to empty] for this ring." hexmask.long.word 0xC 0.--15. 1. "EVT,Defines the event for this ring or queue." line.long 0x10 "VIRT_ALIAS_11_RINGACC0__CFG__CFG_ORDERID,The Ring OrderID Register contains the bus orderid value for the ring memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for this ring or queue." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_11_RINGACC0_CFG_GCFG (NAVSS0_RINGACC_0_VIRT_ALIAS_11_RINGACC0_CFG_GCFG)" base ad:0x4BB1160000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_RINGACC0__CFG__GCFG_revision,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_RINGACC0__CFG__GCFG_trace_ctl,Trace Control Register" bitfld.long 0x0 31. "EN,Trace enable 0 = disable 1 = enable." "0: disable,1: enable" bitfld.long 0x0 30. "ALL_QUEUES,Trace everything 0 = only the selected queue 1 = every queue." "0: only the selected queue,1: every queue" bitfld.long 0x0 29. "MSG,Trace message data 0 = include only the operation 1 = include message data." "0: include only the operation,1: include message data" newline hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number when tracing a single queue." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_11_RINGACC0__CFG__GCFG_overflow,Overflow Queue Register" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue to send overflow messages. A value of 0xffff will disable the overflow function." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_11_RINGACC0__CFG__GCFG_error_evt,The Error Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote detection of a ring memory transaction bus error." hexmask.long.word 0x0 0.--15. 1. "EVT,Event to send when detecting a bus error." rgroup.long 0x44++0x3 line.long 0x0 "VIRT_ALIAS_11_RINGACC0__CFG__GCFG_error_log,Error Log Register. A read of this register will clear the pending error log event and allow a new error to be captured. It does not clear the contents of this register which are only valid while the error.." bitfld.long 0x0 31. "PUSH,Bus error was caused by a push. 0 = pop. 1 = push." "0: pop,1: push" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue that received the bus error." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_11_RINGACC0_CFG_MON (NAVSS0_RINGACC_0_VIRT_ALIAS_11_RINGACC0_CFG_MON)" base ad:0x4BB2000000 rgroup.long 0x0++0xF line.long 0x0 "VIRT_ALIAS_11_RINGACC0__CFG__MON_control,Monitor Control Register" hexmask.long.word 0x0 16.--31. 1. "EVT,Event to produce." hexmask.long.byte 0x0 8.--11. 1. "SOURCE,Monitor source selection. 0 = element count. 1 = reserved. 2 = reserved." bitfld.long 0x0 0.--2. "MODE,Monitor Mode. 0 = disabled. 1 = push/pop statistics capture. 2 = low/high threshold checks. 3 = low/high watermarking. 4 = starvation counting." "0: disabled,1: push/pop statistics capture,2: low/high threshold checks,3: low/high watermarking,4: starvation counting,?,?,?" line.long 0x4 "VIRT_ALIAS_11_RINGACC0__CFG__MON_queue,Monitor Queue Register" hexmask.long.word 0x4 0.--15. 1. "QUEUE,Queue to monitor." line.long 0x8 "VIRT_ALIAS_11_RINGACC0__CFG__MON_data0,Monitor Data Register" hexmask.long 0x8 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pushes. For mode 2 this is read-write and the low threshold value. For mode 3 this is read only and the low watermark. For mode 4 this is read only and the starvation count." line.long 0xC "VIRT_ALIAS_11_RINGACC0__CFG__MON_data1,Monitor Data Register" hexmask.long 0xC 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pops. For mode 2 this is read-write and the high threshold value. For mode 3 this is read only and the high watermark. For mode 4 this is not used." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_11_RINGACC0_SRC_FIFOS (NAVSS0_RINGACC_0_VIRT_ALIAS_11_RINGACC0_SRC_FIFOS)" base ad:0x4BB8000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_RINGACC0__SRC__FIFOS_RING_HEAD_DATA,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_11_RINGACC0__SRC__FIFOS_RING_TAIL_DATA,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_11_RINGACC0__SRC__FIFOS_PEEK_HEAD_DATA,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." rgroup.long 0x600++0x3 line.long 0x0 "VIRT_ALIAS_11_RINGACC0__SRC__FIFOS_PEEK_TAIL_DATA,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_11_RINGACC0_CFG_RT (NAVSS0_RINGACC_0_VIRT_ALIAS_11_RINGACC0_CFG_RT)" base ad:0x4BBC000000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_RINGACC0__CFG__RT_RT_DB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0xF line.long 0x0 "VIRT_ALIAS_11_RINGACC0__CFG__RT_RT_OCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.tbyte 0x0 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0x4 "VIRT_ALIAS_11_RINGACC0__CFG__RT_RT_INDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel." hexmask.long.tbyte 0x4 0.--19. 1. "INDX,Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." line.long 0x8 "VIRT_ALIAS_11_RINGACC0__CFG__RT_RT_HWOCC,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create.." hexmask.long.tbyte 0x8 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0xC "VIRT_ALIAS_11_RINGACC0__CFG__RT_RT_HWINDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel." hexmask.long.tbyte 0xC 0.--19. 1. "INDX,Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_12_RINGACC0_CFG (NAVSS0_RINGACC_0_VIRT_ALIAS_12_RINGACC0_CFG)" base ad:0x4BC1080000 rgroup.long 0x40++0x13 line.long 0x0 "VIRT_ALIAS_12_RINGACC0__CFG__CFG_BA_LO,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Tx Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_12_RINGACC0__CFG__CFG_BA_HI,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size.." hexmask.long.word 0x4 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_12_RINGACC0__CFG__CFG_SIZE,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to.." bitfld.long 0x8 30.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3" bitfld.long 0x8 24.--26. "ELSIZE,Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED" "?,?,?,?,?,?,?,7: RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number." line.long 0xC "VIRT_ALIAS_12_RINGACC0__CFG__CFG_EVT,The Ring Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote the occurrence of an up event [empty to not-empty] or a down event [non-empty to empty] for this ring." hexmask.long.word 0xC 0.--15. 1. "EVT,Defines the event for this ring or queue." line.long 0x10 "VIRT_ALIAS_12_RINGACC0__CFG__CFG_ORDERID,The Ring OrderID Register contains the bus orderid value for the ring memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for this ring or queue." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_12_RINGACC0_CFG_GCFG (NAVSS0_RINGACC_0_VIRT_ALIAS_12_RINGACC0_CFG_GCFG)" base ad:0x4BC1160000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_RINGACC0__CFG__GCFG_revision,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_RINGACC0__CFG__GCFG_trace_ctl,Trace Control Register" bitfld.long 0x0 31. "EN,Trace enable 0 = disable 1 = enable." "0: disable,1: enable" bitfld.long 0x0 30. "ALL_QUEUES,Trace everything 0 = only the selected queue 1 = every queue." "0: only the selected queue,1: every queue" bitfld.long 0x0 29. "MSG,Trace message data 0 = include only the operation 1 = include message data." "0: include only the operation,1: include message data" newline hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number when tracing a single queue." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_12_RINGACC0__CFG__GCFG_overflow,Overflow Queue Register" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue to send overflow messages. A value of 0xffff will disable the overflow function." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_12_RINGACC0__CFG__GCFG_error_evt,The Error Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote detection of a ring memory transaction bus error." hexmask.long.word 0x0 0.--15. 1. "EVT,Event to send when detecting a bus error." rgroup.long 0x44++0x3 line.long 0x0 "VIRT_ALIAS_12_RINGACC0__CFG__GCFG_error_log,Error Log Register. A read of this register will clear the pending error log event and allow a new error to be captured. It does not clear the contents of this register which are only valid while the error.." bitfld.long 0x0 31. "PUSH,Bus error was caused by a push. 0 = pop. 1 = push." "0: pop,1: push" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue that received the bus error." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_12_RINGACC0_CFG_MON (NAVSS0_RINGACC_0_VIRT_ALIAS_12_RINGACC0_CFG_MON)" base ad:0x4BC2000000 rgroup.long 0x0++0xF line.long 0x0 "VIRT_ALIAS_12_RINGACC0__CFG__MON_control,Monitor Control Register" hexmask.long.word 0x0 16.--31. 1. "EVT,Event to produce." hexmask.long.byte 0x0 8.--11. 1. "SOURCE,Monitor source selection. 0 = element count. 1 = reserved. 2 = reserved." bitfld.long 0x0 0.--2. "MODE,Monitor Mode. 0 = disabled. 1 = push/pop statistics capture. 2 = low/high threshold checks. 3 = low/high watermarking. 4 = starvation counting." "0: disabled,1: push/pop statistics capture,2: low/high threshold checks,3: low/high watermarking,4: starvation counting,?,?,?" line.long 0x4 "VIRT_ALIAS_12_RINGACC0__CFG__MON_queue,Monitor Queue Register" hexmask.long.word 0x4 0.--15. 1. "QUEUE,Queue to monitor." line.long 0x8 "VIRT_ALIAS_12_RINGACC0__CFG__MON_data0,Monitor Data Register" hexmask.long 0x8 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pushes. For mode 2 this is read-write and the low threshold value. For mode 3 this is read only and the low watermark. For mode 4 this is read only and the starvation count." line.long 0xC "VIRT_ALIAS_12_RINGACC0__CFG__MON_data1,Monitor Data Register" hexmask.long 0xC 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pops. For mode 2 this is read-write and the high threshold value. For mode 3 this is read only and the high watermark. For mode 4 this is not used." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_12_RINGACC0_SRC_FIFOS (NAVSS0_RINGACC_0_VIRT_ALIAS_12_RINGACC0_SRC_FIFOS)" base ad:0x4BC8000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_RINGACC0__SRC__FIFOS_RING_HEAD_DATA,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_12_RINGACC0__SRC__FIFOS_RING_TAIL_DATA,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_12_RINGACC0__SRC__FIFOS_PEEK_HEAD_DATA,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." rgroup.long 0x600++0x3 line.long 0x0 "VIRT_ALIAS_12_RINGACC0__SRC__FIFOS_PEEK_TAIL_DATA,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_12_RINGACC0_CFG_RT (NAVSS0_RINGACC_0_VIRT_ALIAS_12_RINGACC0_CFG_RT)" base ad:0x4BCC000000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_RINGACC0__CFG__RT_RT_DB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0xF line.long 0x0 "VIRT_ALIAS_12_RINGACC0__CFG__RT_RT_OCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.tbyte 0x0 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0x4 "VIRT_ALIAS_12_RINGACC0__CFG__RT_RT_INDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel." hexmask.long.tbyte 0x4 0.--19. 1. "INDX,Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." line.long 0x8 "VIRT_ALIAS_12_RINGACC0__CFG__RT_RT_HWOCC,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create.." hexmask.long.tbyte 0x8 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0xC "VIRT_ALIAS_12_RINGACC0__CFG__RT_RT_HWINDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel." hexmask.long.tbyte 0xC 0.--19. 1. "INDX,Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_13_RINGACC0_CFG (NAVSS0_RINGACC_0_VIRT_ALIAS_13_RINGACC0_CFG)" base ad:0x4BD1080000 rgroup.long 0x40++0x13 line.long 0x0 "VIRT_ALIAS_13_RINGACC0__CFG__CFG_BA_LO,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Tx Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_13_RINGACC0__CFG__CFG_BA_HI,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size.." hexmask.long.word 0x4 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_13_RINGACC0__CFG__CFG_SIZE,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to.." bitfld.long 0x8 30.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3" bitfld.long 0x8 24.--26. "ELSIZE,Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED" "?,?,?,?,?,?,?,7: RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number." line.long 0xC "VIRT_ALIAS_13_RINGACC0__CFG__CFG_EVT,The Ring Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote the occurrence of an up event [empty to not-empty] or a down event [non-empty to empty] for this ring." hexmask.long.word 0xC 0.--15. 1. "EVT,Defines the event for this ring or queue." line.long 0x10 "VIRT_ALIAS_13_RINGACC0__CFG__CFG_ORDERID,The Ring OrderID Register contains the bus orderid value for the ring memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for this ring or queue." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_13_RINGACC0_CFG_GCFG (NAVSS0_RINGACC_0_VIRT_ALIAS_13_RINGACC0_CFG_GCFG)" base ad:0x4BD1160000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_RINGACC0__CFG__GCFG_revision,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_RINGACC0__CFG__GCFG_trace_ctl,Trace Control Register" bitfld.long 0x0 31. "EN,Trace enable 0 = disable 1 = enable." "0: disable,1: enable" bitfld.long 0x0 30. "ALL_QUEUES,Trace everything 0 = only the selected queue 1 = every queue." "0: only the selected queue,1: every queue" bitfld.long 0x0 29. "MSG,Trace message data 0 = include only the operation 1 = include message data." "0: include only the operation,1: include message data" newline hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number when tracing a single queue." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_13_RINGACC0__CFG__GCFG_overflow,Overflow Queue Register" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue to send overflow messages. A value of 0xffff will disable the overflow function." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_13_RINGACC0__CFG__GCFG_error_evt,The Error Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote detection of a ring memory transaction bus error." hexmask.long.word 0x0 0.--15. 1. "EVT,Event to send when detecting a bus error." rgroup.long 0x44++0x3 line.long 0x0 "VIRT_ALIAS_13_RINGACC0__CFG__GCFG_error_log,Error Log Register. A read of this register will clear the pending error log event and allow a new error to be captured. It does not clear the contents of this register which are only valid while the error.." bitfld.long 0x0 31. "PUSH,Bus error was caused by a push. 0 = pop. 1 = push." "0: pop,1: push" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue that received the bus error." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_13_RINGACC0_CFG_MON (NAVSS0_RINGACC_0_VIRT_ALIAS_13_RINGACC0_CFG_MON)" base ad:0x4BD2000000 rgroup.long 0x0++0xF line.long 0x0 "VIRT_ALIAS_13_RINGACC0__CFG__MON_control,Monitor Control Register" hexmask.long.word 0x0 16.--31. 1. "EVT,Event to produce." hexmask.long.byte 0x0 8.--11. 1. "SOURCE,Monitor source selection. 0 = element count. 1 = reserved. 2 = reserved." bitfld.long 0x0 0.--2. "MODE,Monitor Mode. 0 = disabled. 1 = push/pop statistics capture. 2 = low/high threshold checks. 3 = low/high watermarking. 4 = starvation counting." "0: disabled,1: push/pop statistics capture,2: low/high threshold checks,3: low/high watermarking,4: starvation counting,?,?,?" line.long 0x4 "VIRT_ALIAS_13_RINGACC0__CFG__MON_queue,Monitor Queue Register" hexmask.long.word 0x4 0.--15. 1. "QUEUE,Queue to monitor." line.long 0x8 "VIRT_ALIAS_13_RINGACC0__CFG__MON_data0,Monitor Data Register" hexmask.long 0x8 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pushes. For mode 2 this is read-write and the low threshold value. For mode 3 this is read only and the low watermark. For mode 4 this is read only and the starvation count." line.long 0xC "VIRT_ALIAS_13_RINGACC0__CFG__MON_data1,Monitor Data Register" hexmask.long 0xC 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pops. For mode 2 this is read-write and the high threshold value. For mode 3 this is read only and the high watermark. For mode 4 this is not used." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_13_RINGACC0_SRC_FIFOS (NAVSS0_RINGACC_0_VIRT_ALIAS_13_RINGACC0_SRC_FIFOS)" base ad:0x4BD8000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_RINGACC0__SRC__FIFOS_RING_HEAD_DATA,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_13_RINGACC0__SRC__FIFOS_RING_TAIL_DATA,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_13_RINGACC0__SRC__FIFOS_PEEK_HEAD_DATA,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." rgroup.long 0x600++0x3 line.long 0x0 "VIRT_ALIAS_13_RINGACC0__SRC__FIFOS_PEEK_TAIL_DATA,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_13_RINGACC0_CFG_RT (NAVSS0_RINGACC_0_VIRT_ALIAS_13_RINGACC0_CFG_RT)" base ad:0x4BDC000000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_RINGACC0__CFG__RT_RT_DB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0xF line.long 0x0 "VIRT_ALIAS_13_RINGACC0__CFG__RT_RT_OCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.tbyte 0x0 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0x4 "VIRT_ALIAS_13_RINGACC0__CFG__RT_RT_INDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel." hexmask.long.tbyte 0x4 0.--19. 1. "INDX,Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." line.long 0x8 "VIRT_ALIAS_13_RINGACC0__CFG__RT_RT_HWOCC,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create.." hexmask.long.tbyte 0x8 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0xC "VIRT_ALIAS_13_RINGACC0__CFG__RT_RT_HWINDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel." hexmask.long.tbyte 0xC 0.--19. 1. "INDX,Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_14_RINGACC0_CFG (NAVSS0_RINGACC_0_VIRT_ALIAS_14_RINGACC0_CFG)" base ad:0x4BE1080000 rgroup.long 0x40++0x13 line.long 0x0 "VIRT_ALIAS_14_RINGACC0__CFG__CFG_BA_LO,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Tx Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_14_RINGACC0__CFG__CFG_BA_HI,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size.." hexmask.long.word 0x4 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_14_RINGACC0__CFG__CFG_SIZE,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to.." bitfld.long 0x8 30.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3" bitfld.long 0x8 24.--26. "ELSIZE,Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED" "?,?,?,?,?,?,?,7: RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number." line.long 0xC "VIRT_ALIAS_14_RINGACC0__CFG__CFG_EVT,The Ring Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote the occurrence of an up event [empty to not-empty] or a down event [non-empty to empty] for this ring." hexmask.long.word 0xC 0.--15. 1. "EVT,Defines the event for this ring or queue." line.long 0x10 "VIRT_ALIAS_14_RINGACC0__CFG__CFG_ORDERID,The Ring OrderID Register contains the bus orderid value for the ring memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for this ring or queue." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_14_RINGACC0_CFG_GCFG (NAVSS0_RINGACC_0_VIRT_ALIAS_14_RINGACC0_CFG_GCFG)" base ad:0x4BE1160000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_RINGACC0__CFG__GCFG_revision,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_RINGACC0__CFG__GCFG_trace_ctl,Trace Control Register" bitfld.long 0x0 31. "EN,Trace enable 0 = disable 1 = enable." "0: disable,1: enable" bitfld.long 0x0 30. "ALL_QUEUES,Trace everything 0 = only the selected queue 1 = every queue." "0: only the selected queue,1: every queue" bitfld.long 0x0 29. "MSG,Trace message data 0 = include only the operation 1 = include message data." "0: include only the operation,1: include message data" newline hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number when tracing a single queue." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_14_RINGACC0__CFG__GCFG_overflow,Overflow Queue Register" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue to send overflow messages. A value of 0xffff will disable the overflow function." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_14_RINGACC0__CFG__GCFG_error_evt,The Error Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote detection of a ring memory transaction bus error." hexmask.long.word 0x0 0.--15. 1. "EVT,Event to send when detecting a bus error." rgroup.long 0x44++0x3 line.long 0x0 "VIRT_ALIAS_14_RINGACC0__CFG__GCFG_error_log,Error Log Register. A read of this register will clear the pending error log event and allow a new error to be captured. It does not clear the contents of this register which are only valid while the error.." bitfld.long 0x0 31. "PUSH,Bus error was caused by a push. 0 = pop. 1 = push." "0: pop,1: push" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue that received the bus error." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_14_RINGACC0_CFG_MON (NAVSS0_RINGACC_0_VIRT_ALIAS_14_RINGACC0_CFG_MON)" base ad:0x4BE2000000 rgroup.long 0x0++0xF line.long 0x0 "VIRT_ALIAS_14_RINGACC0__CFG__MON_control,Monitor Control Register" hexmask.long.word 0x0 16.--31. 1. "EVT,Event to produce." hexmask.long.byte 0x0 8.--11. 1. "SOURCE,Monitor source selection. 0 = element count. 1 = reserved. 2 = reserved." bitfld.long 0x0 0.--2. "MODE,Monitor Mode. 0 = disabled. 1 = push/pop statistics capture. 2 = low/high threshold checks. 3 = low/high watermarking. 4 = starvation counting." "0: disabled,1: push/pop statistics capture,2: low/high threshold checks,3: low/high watermarking,4: starvation counting,?,?,?" line.long 0x4 "VIRT_ALIAS_14_RINGACC0__CFG__MON_queue,Monitor Queue Register" hexmask.long.word 0x4 0.--15. 1. "QUEUE,Queue to monitor." line.long 0x8 "VIRT_ALIAS_14_RINGACC0__CFG__MON_data0,Monitor Data Register" hexmask.long 0x8 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pushes. For mode 2 this is read-write and the low threshold value. For mode 3 this is read only and the low watermark. For mode 4 this is read only and the starvation count." line.long 0xC "VIRT_ALIAS_14_RINGACC0__CFG__MON_data1,Monitor Data Register" hexmask.long 0xC 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pops. For mode 2 this is read-write and the high threshold value. For mode 3 this is read only and the high watermark. For mode 4 this is not used." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_14_RINGACC0_SRC_FIFOS (NAVSS0_RINGACC_0_VIRT_ALIAS_14_RINGACC0_SRC_FIFOS)" base ad:0x4BE8000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_RINGACC0__SRC__FIFOS_RING_HEAD_DATA,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_14_RINGACC0__SRC__FIFOS_RING_TAIL_DATA,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_14_RINGACC0__SRC__FIFOS_PEEK_HEAD_DATA,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." rgroup.long 0x600++0x3 line.long 0x0 "VIRT_ALIAS_14_RINGACC0__SRC__FIFOS_PEEK_TAIL_DATA,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_14_RINGACC0_CFG_RT (NAVSS0_RINGACC_0_VIRT_ALIAS_14_RINGACC0_CFG_RT)" base ad:0x4BEC000000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_RINGACC0__CFG__RT_RT_DB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0xF line.long 0x0 "VIRT_ALIAS_14_RINGACC0__CFG__RT_RT_OCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.tbyte 0x0 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0x4 "VIRT_ALIAS_14_RINGACC0__CFG__RT_RT_INDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel." hexmask.long.tbyte 0x4 0.--19. 1. "INDX,Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." line.long 0x8 "VIRT_ALIAS_14_RINGACC0__CFG__RT_RT_HWOCC,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create.." hexmask.long.tbyte 0x8 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0xC "VIRT_ALIAS_14_RINGACC0__CFG__RT_RT_HWINDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel." hexmask.long.tbyte 0xC 0.--19. 1. "INDX,Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_15_RINGACC0_CFG (NAVSS0_RINGACC_0_VIRT_ALIAS_15_RINGACC0_CFG)" base ad:0x4BF1080000 rgroup.long 0x40++0x13 line.long 0x0 "VIRT_ALIAS_15_RINGACC0__CFG__CFG_BA_LO,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Tx Ring base address (LSBs)" line.long 0x4 "VIRT_ALIAS_15_RINGACC0__CFG__CFG_BA_HI,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size.." hexmask.long.word 0x4 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)" line.long 0x8 "VIRT_ALIAS_15_RINGACC0__CFG__CFG_SIZE,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to.." bitfld.long 0x8 30.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3" bitfld.long 0x8 24.--26. "ELSIZE,Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED" "?,?,?,?,?,?,?,7: RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number." line.long 0xC "VIRT_ALIAS_15_RINGACC0__CFG__CFG_EVT,The Ring Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote the occurrence of an up event [empty to not-empty] or a down event [non-empty to empty] for this ring." hexmask.long.word 0xC 0.--15. 1. "EVT,Defines the event for this ring or queue." line.long 0x10 "VIRT_ALIAS_15_RINGACC0__CFG__CFG_ORDERID,The Ring OrderID Register contains the bus orderid value for the ring memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for this ring or queue." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_15_RINGACC0_CFG_GCFG (NAVSS0_RINGACC_0_VIRT_ALIAS_15_RINGACC0_CFG_GCFG)" base ad:0x4BF1160000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_RINGACC0__CFG__GCFG_revision,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_RINGACC0__CFG__GCFG_trace_ctl,Trace Control Register" bitfld.long 0x0 31. "EN,Trace enable 0 = disable 1 = enable." "0: disable,1: enable" bitfld.long 0x0 30. "ALL_QUEUES,Trace everything 0 = only the selected queue 1 = every queue." "0: only the selected queue,1: every queue" bitfld.long 0x0 29. "MSG,Trace message data 0 = include only the operation 1 = include message data." "0: include only the operation,1: include message data" newline hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number when tracing a single queue." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_15_RINGACC0__CFG__GCFG_overflow,Overflow Queue Register" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue to send overflow messages. A value of 0xffff will disable the overflow function." rgroup.long 0x40++0x3 line.long 0x0 "VIRT_ALIAS_15_RINGACC0__CFG__GCFG_error_evt,The Error Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote detection of a ring memory transaction bus error." hexmask.long.word 0x0 0.--15. 1. "EVT,Event to send when detecting a bus error." rgroup.long 0x44++0x3 line.long 0x0 "VIRT_ALIAS_15_RINGACC0__CFG__GCFG_error_log,Error Log Register. A read of this register will clear the pending error log event and allow a new error to be captured. It does not clear the contents of this register which are only valid while the error.." bitfld.long 0x0 31. "PUSH,Bus error was caused by a push. 0 = pop. 1 = push." "0: pop,1: push" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue that received the bus error." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_15_RINGACC0_CFG_MON (NAVSS0_RINGACC_0_VIRT_ALIAS_15_RINGACC0_CFG_MON)" base ad:0x4BF2000000 rgroup.long 0x0++0xF line.long 0x0 "VIRT_ALIAS_15_RINGACC0__CFG__MON_control,Monitor Control Register" hexmask.long.word 0x0 16.--31. 1. "EVT,Event to produce." hexmask.long.byte 0x0 8.--11. 1. "SOURCE,Monitor source selection. 0 = element count. 1 = reserved. 2 = reserved." bitfld.long 0x0 0.--2. "MODE,Monitor Mode. 0 = disabled. 1 = push/pop statistics capture. 2 = low/high threshold checks. 3 = low/high watermarking. 4 = starvation counting." "0: disabled,1: push/pop statistics capture,2: low/high threshold checks,3: low/high watermarking,4: starvation counting,?,?,?" line.long 0x4 "VIRT_ALIAS_15_RINGACC0__CFG__MON_queue,Monitor Queue Register" hexmask.long.word 0x4 0.--15. 1. "QUEUE,Queue to monitor." line.long 0x8 "VIRT_ALIAS_15_RINGACC0__CFG__MON_data0,Monitor Data Register" hexmask.long 0x8 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pushes. For mode 2 this is read-write and the low threshold value. For mode 3 this is read only and the low watermark. For mode 4 this is read only and the starvation count." line.long 0xC "VIRT_ALIAS_15_RINGACC0__CFG__MON_data1,Monitor Data Register" hexmask.long 0xC 0.--31. 1. "DATA,Monitor Data. For mode 1 this is read-only and number of pops. For mode 2 this is read-write and the high threshold value. For mode 3 this is read only and the high watermark. For mode 4 this is not used." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_15_RINGACC0_SRC_FIFOS (NAVSS0_RINGACC_0_VIRT_ALIAS_15_RINGACC0_SRC_FIFOS)" base ad:0x4BF8000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_RINGACC0__SRC__FIFOS_RING_HEAD_DATA,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x200++0x3 line.long 0x0 "VIRT_ALIAS_15_RINGACC0__SRC__FIFOS_RING_TAIL_DATA,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail. These registers are virtual and non-static (i.e. they are just address locations that are.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data" rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_15_RINGACC0__SRC__FIFOS_PEEK_HEAD_DATA,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." rgroup.long 0x600++0x3 line.long 0x0 "VIRT_ALIAS_15_RINGACC0__SRC__FIFOS_PEEK_TAIL_DATA,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element. These registers are virtual and non-static (i.e. they are just address.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_RINGACC_0_VIRT_ALIAS_15_RINGACC0_CFG_RT (NAVSS0_RINGACC_0_VIRT_ALIAS_15_RINGACC0_CFG_RT)" base ad:0x4BFC000000 rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_RINGACC0__CFG__RT_RT_DB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write.." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.long 0x18++0xF line.long 0x0 "VIRT_ALIAS_15_RINGACC0__CFG__RT_RT_OCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.tbyte 0x0 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0x4 "VIRT_ALIAS_15_RINGACC0__CFG__RT_RT_INDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel." hexmask.long.tbyte 0x4 0.--19. 1. "INDX,Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." line.long 0x8 "VIRT_ALIAS_15_RINGACC0__CFG__RT_RT_HWOCC,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create.." hexmask.long.tbyte 0x8 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0xC "VIRT_ALIAS_15_RINGACC0__CFG__RT_RT_HWINDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel." hexmask.long.tbyte 0xC 0.--19. 1. "INDX,Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." tree.end endif tree.end tree.end tree "NAVSS0_SEC_PROXY_0" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_SEC_PROXY0_CFG_MMRS (NAVSS0_SEC_PROXY_0_SEC_PROXY0_CFG_MMRS)" base ad:0x31140000 rgroup.long 0x0++0x7 line.long 0x0 "SEC_PROXY0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "SEC_PROXY0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 16.--31. 1. "MSG_SIZE,Supported message size in bytes." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "SEC_PROXY0__CFG__MMRS_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_SEC_PROXY0_CFG_RT (NAVSS0_SEC_PROXY_0_SEC_PROXY0_CFG_RT)" base ad:0x32400000 rgroup.long 0x0++0x7 line.long 0x0 "SEC_PROXY0__CFG__RT_status,The Status Register gives status for proxy thread a." bitfld.long 0x0 31. "ERROR,Error detected on proxy thread. The error will also use the err_evt field to generate an error event which can generate an interrupt. While in error a proxy thread will not process any operations. Write a 0 to clear the error and reset the proxy.." "0,1" rbitfld.long 0x0 30. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread." hexmask.long.byte 0x0 0.--7. 1. "CUR_CNT,Current message count for the proxy thread. For an inbound proxy this is the number of available messages. For an outbound proxy this is the number of free messages that can be written. This value will initialize itself to 0 if the THREAD[a]_CTL.." line.long 0x4 "SEC_PROXY0__CFG__RT_thr,The Threshold Register controls the threshold for proxy thread a events." hexmask.long.byte 0x4 0.--7. 1. "THR_CNT,Threshold count that causes proxy thread events. For an outbound proxy this will be the number of free messages to cause an event. For an inbound proxy this will be the number of available messages to cause an event." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_SEC_PROXY0_CFG_SCFG (NAVSS0_SEC_PROXY_0_SEC_PROXY0_CFG_SCFG)" base ad:0x32800000 rgroup.long 0x0++0x13 line.long 0x0 "SEC_PROXY0__CFG__SCFG_buffer_l,The Buffer Register defines the pointer for the external buffer." hexmask.long 0x0 0.--31. 1. "BASE_L,The base address for the external buffer lower 32 bits." line.long 0x4 "SEC_PROXY0__CFG__SCFG_buffer_h,The Buffer Register defines the pointer for the external buffer." hexmask.long.word 0x4 0.--15. 1. "BASE_H,The base address for the external buffer upper 16 bits." line.long 0x8 "SEC_PROXY0__CFG__SCFG_target_l,The Target Register defines the pointer for the external target." hexmask.long 0x8 0.--31. 1. "BASE_L,The base address for the external target lower 32 bits." line.long 0xC "SEC_PROXY0__CFG__SCFG_target_h,The Target Register defines the pointer for the external target." hexmask.long.word 0xC 0.--15. 1. "BASE_H,The base address for the external target upper 16 bits." line.long 0x10 "SEC_PROXY0__CFG__SCFG_ORDERID,The Buffer OrderID Register contains the bus orderid value for the buffer memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for the buffer access with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for the buffer access." rgroup.long 0x1000++0xB line.long 0x0 "SEC_PROXY0__CFG__SCFG_ctl,The Control Register defines controls for proxy thread a." bitfld.long 0x0 31. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread. Is not used otherwise." hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number in the target to use for the proxy thread. If the target base does not start at queue 0 then this is the relative queue number from that base queue." line.long 0x4 "SEC_PROXY0__CFG__SCFG_evt_map,The Event Map Register defines the event numbers for proxy thread a." hexmask.long.word 0x4 16.--31. 1. "ERR_EVT,Event number for an error from the proxy thread." hexmask.long.word 0x4 0.--15. 1. "THR_EVT,Event number for a threshold event from the proxy thread." line.long 0x8 "SEC_PROXY0__CFG__SCFG_dst,The Destination Register defines the destination proxy thread for outbound proxy thread a." hexmask.long.word 0x8 0.--15. 1. "THREAD,The proxy thread that is the destination of messages from this outbound proxy thread based on the queue numbers. This is ignored for inbound proxy threads." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_SEC_PROXY0_SRC_TARGET_DATA (NAVSS0_SEC_PROXY_0_SEC_PROXY0_SRC_TARGET_DATA)" base ad:0x32C00000 rgroup.long 0x0++0x3 line.long 0x0 "SEC_PROXY0__SRC__TARGET_DATA_private,The Proxy Private register contains private information for the proxy thread a and should not be written. writes are ignored. Reads are allowed to know the source thread of the message." hexmask.long.word 0x0 0.--9. 1. "SRC_THR,Proxy source thread of message." rgroup.long 0x4++0x3 line.long 0x0 "SEC_PROXY0__SRC__TARGET_DATA_message,The Message Data for proxy thread a. The word with index b = 14 contains the completion final byte." hexmask.long 0x0 0.--31. 1. "DATA,Proxy Message Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_ALIAS64K_SEC_PROXY0_CFG_RT (NAVSS0_SEC_PROXY_0_ALIAS64K_SEC_PROXY0_CFG_RT)" base ad:0x4A24000000 rgroup.long 0x0++0x7 line.long 0x0 "ALIAS64K_SEC_PROXY0__CFG__RT_status,The Status Register gives status for proxy thread a." bitfld.long 0x0 31. "ERROR,Error detected on proxy thread. The error will also use the err_evt field to generate an error event which can generate an interrupt. While in error a proxy thread will not process any operations. Write a 0 to clear the error and reset the proxy.." "0,1" rbitfld.long 0x0 30. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread." hexmask.long.byte 0x0 0.--7. 1. "CUR_CNT,Current message count for the proxy thread. For an inbound proxy this is the number of available messages. For an outbound proxy this is the number of free messages that can be written. This value will initialize itself to 0 if the THREAD[a]_CTL.." line.long 0x4 "ALIAS64K_SEC_PROXY0__CFG__RT_thr,The Threshold Register controls the threshold for proxy thread a events." hexmask.long.byte 0x4 0.--7. 1. "THR_CNT,Threshold count that causes proxy thread events. For an outbound proxy this will be the number of free messages to cause an event. For an inbound proxy this will be the number of available messages to cause an event." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_ALIAS64K_SEC_PROXY0_CFG_SCFG (NAVSS0_SEC_PROXY_0_ALIAS64K_SEC_PROXY0_CFG_SCFG)" base ad:0x4A28000000 rgroup.long 0x0++0x13 line.long 0x0 "ALIAS64K_SEC_PROXY0__CFG__SCFG_buffer_l,The Buffer Register defines the pointer for the external buffer." hexmask.long 0x0 0.--31. 1. "BASE_L,The base address for the external buffer lower 32 bits." line.long 0x4 "ALIAS64K_SEC_PROXY0__CFG__SCFG_buffer_h,The Buffer Register defines the pointer for the external buffer." hexmask.long.word 0x4 0.--15. 1. "BASE_H,The base address for the external buffer upper 16 bits." line.long 0x8 "ALIAS64K_SEC_PROXY0__CFG__SCFG_target_l,The Target Register defines the pointer for the external target." hexmask.long 0x8 0.--31. 1. "BASE_L,The base address for the external target lower 32 bits." line.long 0xC "ALIAS64K_SEC_PROXY0__CFG__SCFG_target_h,The Target Register defines the pointer for the external target." hexmask.long.word 0xC 0.--15. 1. "BASE_H,The base address for the external target upper 16 bits." line.long 0x10 "ALIAS64K_SEC_PROXY0__CFG__SCFG_ORDERID,The Buffer OrderID Register contains the bus orderid value for the buffer memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for the buffer access with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for the buffer access." rgroup.long 0x1000++0xB line.long 0x0 "ALIAS64K_SEC_PROXY0__CFG__SCFG_ctl,The Control Register defines controls for proxy thread a." bitfld.long 0x0 31. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread. Is not used otherwise." hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number in the target to use for the proxy thread. If the target base does not start at queue 0 then this is the relative queue number from that base queue." line.long 0x4 "ALIAS64K_SEC_PROXY0__CFG__SCFG_evt_map,The Event Map Register defines the event numbers for proxy thread a." hexmask.long.word 0x4 16.--31. 1. "ERR_EVT,Event number for an error from the proxy thread." hexmask.long.word 0x4 0.--15. 1. "THR_EVT,Event number for a threshold event from the proxy thread." line.long 0x8 "ALIAS64K_SEC_PROXY0__CFG__SCFG_dst,The Destination Register defines the destination proxy thread for outbound proxy thread a." hexmask.long.word 0x8 0.--15. 1. "THREAD,The proxy thread that is the destination of messages from this outbound proxy thread based on the queue numbers. This is ignored for inbound proxy threads." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_ALIAS64K_SEC_PROXY0_SRC_TARGET_DATA (NAVSS0_SEC_PROXY_0_ALIAS64K_SEC_PROXY0_SRC_TARGET_DATA)" base ad:0x4A2C000000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_SEC_PROXY0__SRC__TARGET_DATA_private,The Proxy Private register contains private information for the proxy thread a and should not be written. writes are ignored. Reads are allowed to know the source thread of the message." hexmask.long.word 0x0 0.--9. 1. "SRC_THR,Proxy source thread of message." rgroup.long 0x4++0x3 line.long 0x0 "ALIAS64K_SEC_PROXY0__SRC__TARGET_DATA_message,The Message Data for proxy thread a. The word with index b = 14 contains the completion final byte." hexmask.long 0x0 0.--31. 1. "DATA,Proxy Message Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_0_SEC_PROXY0_CFG_MMRS (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_0_SEC_PROXY0_CFG_MMRS)" base ad:0x4B01140000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_0_SEC_PROXY0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_0_SEC_PROXY0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 16.--31. 1. "MSG_SIZE,Supported message size in bytes." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_0_SEC_PROXY0__CFG__MMRS_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_0_SEC_PROXY0_CFG_RT (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_0_SEC_PROXY0_CFG_RT)" base ad:0x4B02400000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_0_SEC_PROXY0__CFG__RT_status,The Status Register gives status for proxy thread a." bitfld.long 0x0 31. "ERROR,Error detected on proxy thread. The error will also use the err_evt field to generate an error event which can generate an interrupt. While in error a proxy thread will not process any operations. Write a 0 to clear the error and reset the proxy.." "0,1" rbitfld.long 0x0 30. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread." hexmask.long.byte 0x0 0.--7. 1. "CUR_CNT,Current message count for the proxy thread. For an inbound proxy this is the number of available messages. For an outbound proxy this is the number of free messages that can be written. This value will initialize itself to 0 if the THREAD[a]_CTL.." line.long 0x4 "VIRT_ALIAS_0_SEC_PROXY0__CFG__RT_thr,The Threshold Register controls the threshold for proxy thread a events." hexmask.long.byte 0x4 0.--7. 1. "THR_CNT,Threshold count that causes proxy thread events. For an outbound proxy this will be the number of free messages to cause an event. For an inbound proxy this will be the number of available messages to cause an event." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_0_SEC_PROXY0_CFG_SCFG (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_0_SEC_PROXY0_CFG_SCFG)" base ad:0x4B02800000 rgroup.long 0x0++0x13 line.long 0x0 "VIRT_ALIAS_0_SEC_PROXY0__CFG__SCFG_buffer_l,The Buffer Register defines the pointer for the external buffer." hexmask.long 0x0 0.--31. 1. "BASE_L,The base address for the external buffer lower 32 bits." line.long 0x4 "VIRT_ALIAS_0_SEC_PROXY0__CFG__SCFG_buffer_h,The Buffer Register defines the pointer for the external buffer." hexmask.long.word 0x4 0.--15. 1. "BASE_H,The base address for the external buffer upper 16 bits." line.long 0x8 "VIRT_ALIAS_0_SEC_PROXY0__CFG__SCFG_target_l,The Target Register defines the pointer for the external target." hexmask.long 0x8 0.--31. 1. "BASE_L,The base address for the external target lower 32 bits." line.long 0xC "VIRT_ALIAS_0_SEC_PROXY0__CFG__SCFG_target_h,The Target Register defines the pointer for the external target." hexmask.long.word 0xC 0.--15. 1. "BASE_H,The base address for the external target upper 16 bits." line.long 0x10 "VIRT_ALIAS_0_SEC_PROXY0__CFG__SCFG_ORDERID,The Buffer OrderID Register contains the bus orderid value for the buffer memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for the buffer access with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for the buffer access." rgroup.long 0x1000++0xB line.long 0x0 "VIRT_ALIAS_0_SEC_PROXY0__CFG__SCFG_ctl,The Control Register defines controls for proxy thread a." bitfld.long 0x0 31. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread. Is not used otherwise." hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number in the target to use for the proxy thread. If the target base does not start at queue 0 then this is the relative queue number from that base queue." line.long 0x4 "VIRT_ALIAS_0_SEC_PROXY0__CFG__SCFG_evt_map,The Event Map Register defines the event numbers for proxy thread a." hexmask.long.word 0x4 16.--31. 1. "ERR_EVT,Event number for an error from the proxy thread." hexmask.long.word 0x4 0.--15. 1. "THR_EVT,Event number for a threshold event from the proxy thread." line.long 0x8 "VIRT_ALIAS_0_SEC_PROXY0__CFG__SCFG_dst,The Destination Register defines the destination proxy thread for outbound proxy thread a." hexmask.long.word 0x8 0.--15. 1. "THREAD,The proxy thread that is the destination of messages from this outbound proxy thread based on the queue numbers. This is ignored for inbound proxy threads." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_0_SEC_PROXY0_SRC_TARGET_DATA (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_0_SEC_PROXY0_SRC_TARGET_DATA)" base ad:0x4B02C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_SEC_PROXY0__SRC__TARGET_DATA_private,The Proxy Private register contains private information for the proxy thread a and should not be written. writes are ignored. Reads are allowed to know the source thread of the message." hexmask.long.word 0x0 0.--9. 1. "SRC_THR,Proxy source thread of message." rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_0_SEC_PROXY0__SRC__TARGET_DATA_message,The Message Data for proxy thread a. The word with index b = 14 contains the completion final byte." hexmask.long 0x0 0.--31. 1. "DATA,Proxy Message Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_1_SEC_PROXY0_CFG_MMRS (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_1_SEC_PROXY0_CFG_MMRS)" base ad:0x4B11140000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_1_SEC_PROXY0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_1_SEC_PROXY0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 16.--31. 1. "MSG_SIZE,Supported message size in bytes." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_1_SEC_PROXY0__CFG__MMRS_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_1_SEC_PROXY0_CFG_RT (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_1_SEC_PROXY0_CFG_RT)" base ad:0x4B12400000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_1_SEC_PROXY0__CFG__RT_status,The Status Register gives status for proxy thread a." bitfld.long 0x0 31. "ERROR,Error detected on proxy thread. The error will also use the err_evt field to generate an error event which can generate an interrupt. While in error a proxy thread will not process any operations. Write a 0 to clear the error and reset the proxy.." "0,1" rbitfld.long 0x0 30. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread." hexmask.long.byte 0x0 0.--7. 1. "CUR_CNT,Current message count for the proxy thread. For an inbound proxy this is the number of available messages. For an outbound proxy this is the number of free messages that can be written. This value will initialize itself to 0 if the THREAD[a]_CTL.." line.long 0x4 "VIRT_ALIAS_1_SEC_PROXY0__CFG__RT_thr,The Threshold Register controls the threshold for proxy thread a events." hexmask.long.byte 0x4 0.--7. 1. "THR_CNT,Threshold count that causes proxy thread events. For an outbound proxy this will be the number of free messages to cause an event. For an inbound proxy this will be the number of available messages to cause an event." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_1_SEC_PROXY0_CFG_SCFG (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_1_SEC_PROXY0_CFG_SCFG)" base ad:0x4B12800000 rgroup.long 0x0++0x13 line.long 0x0 "VIRT_ALIAS_1_SEC_PROXY0__CFG__SCFG_buffer_l,The Buffer Register defines the pointer for the external buffer." hexmask.long 0x0 0.--31. 1. "BASE_L,The base address for the external buffer lower 32 bits." line.long 0x4 "VIRT_ALIAS_1_SEC_PROXY0__CFG__SCFG_buffer_h,The Buffer Register defines the pointer for the external buffer." hexmask.long.word 0x4 0.--15. 1. "BASE_H,The base address for the external buffer upper 16 bits." line.long 0x8 "VIRT_ALIAS_1_SEC_PROXY0__CFG__SCFG_target_l,The Target Register defines the pointer for the external target." hexmask.long 0x8 0.--31. 1. "BASE_L,The base address for the external target lower 32 bits." line.long 0xC "VIRT_ALIAS_1_SEC_PROXY0__CFG__SCFG_target_h,The Target Register defines the pointer for the external target." hexmask.long.word 0xC 0.--15. 1. "BASE_H,The base address for the external target upper 16 bits." line.long 0x10 "VIRT_ALIAS_1_SEC_PROXY0__CFG__SCFG_ORDERID,The Buffer OrderID Register contains the bus orderid value for the buffer memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for the buffer access with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for the buffer access." rgroup.long 0x1000++0xB line.long 0x0 "VIRT_ALIAS_1_SEC_PROXY0__CFG__SCFG_ctl,The Control Register defines controls for proxy thread a." bitfld.long 0x0 31. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread. Is not used otherwise." hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number in the target to use for the proxy thread. If the target base does not start at queue 0 then this is the relative queue number from that base queue." line.long 0x4 "VIRT_ALIAS_1_SEC_PROXY0__CFG__SCFG_evt_map,The Event Map Register defines the event numbers for proxy thread a." hexmask.long.word 0x4 16.--31. 1. "ERR_EVT,Event number for an error from the proxy thread." hexmask.long.word 0x4 0.--15. 1. "THR_EVT,Event number for a threshold event from the proxy thread." line.long 0x8 "VIRT_ALIAS_1_SEC_PROXY0__CFG__SCFG_dst,The Destination Register defines the destination proxy thread for outbound proxy thread a." hexmask.long.word 0x8 0.--15. 1. "THREAD,The proxy thread that is the destination of messages from this outbound proxy thread based on the queue numbers. This is ignored for inbound proxy threads." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_1_SEC_PROXY0_SRC_TARGET_DATA (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_1_SEC_PROXY0_SRC_TARGET_DATA)" base ad:0x4B12C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_SEC_PROXY0__SRC__TARGET_DATA_private,The Proxy Private register contains private information for the proxy thread a and should not be written. writes are ignored. Reads are allowed to know the source thread of the message." hexmask.long.word 0x0 0.--9. 1. "SRC_THR,Proxy source thread of message." rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_1_SEC_PROXY0__SRC__TARGET_DATA_message,The Message Data for proxy thread a. The word with index b = 14 contains the completion final byte." hexmask.long 0x0 0.--31. 1. "DATA,Proxy Message Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_2_SEC_PROXY0_CFG_MMRS (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_2_SEC_PROXY0_CFG_MMRS)" base ad:0x4B21140000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_2_SEC_PROXY0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_2_SEC_PROXY0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 16.--31. 1. "MSG_SIZE,Supported message size in bytes." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_2_SEC_PROXY0__CFG__MMRS_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_2_SEC_PROXY0_CFG_RT (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_2_SEC_PROXY0_CFG_RT)" base ad:0x4B22400000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_2_SEC_PROXY0__CFG__RT_status,The Status Register gives status for proxy thread a." bitfld.long 0x0 31. "ERROR,Error detected on proxy thread. The error will also use the err_evt field to generate an error event which can generate an interrupt. While in error a proxy thread will not process any operations. Write a 0 to clear the error and reset the proxy.." "0,1" rbitfld.long 0x0 30. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread." hexmask.long.byte 0x0 0.--7. 1. "CUR_CNT,Current message count for the proxy thread. For an inbound proxy this is the number of available messages. For an outbound proxy this is the number of free messages that can be written. This value will initialize itself to 0 if the THREAD[a]_CTL.." line.long 0x4 "VIRT_ALIAS_2_SEC_PROXY0__CFG__RT_thr,The Threshold Register controls the threshold for proxy thread a events." hexmask.long.byte 0x4 0.--7. 1. "THR_CNT,Threshold count that causes proxy thread events. For an outbound proxy this will be the number of free messages to cause an event. For an inbound proxy this will be the number of available messages to cause an event." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_2_SEC_PROXY0_CFG_SCFG (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_2_SEC_PROXY0_CFG_SCFG)" base ad:0x4B22800000 rgroup.long 0x0++0x13 line.long 0x0 "VIRT_ALIAS_2_SEC_PROXY0__CFG__SCFG_buffer_l,The Buffer Register defines the pointer for the external buffer." hexmask.long 0x0 0.--31. 1. "BASE_L,The base address for the external buffer lower 32 bits." line.long 0x4 "VIRT_ALIAS_2_SEC_PROXY0__CFG__SCFG_buffer_h,The Buffer Register defines the pointer for the external buffer." hexmask.long.word 0x4 0.--15. 1. "BASE_H,The base address for the external buffer upper 16 bits." line.long 0x8 "VIRT_ALIAS_2_SEC_PROXY0__CFG__SCFG_target_l,The Target Register defines the pointer for the external target." hexmask.long 0x8 0.--31. 1. "BASE_L,The base address for the external target lower 32 bits." line.long 0xC "VIRT_ALIAS_2_SEC_PROXY0__CFG__SCFG_target_h,The Target Register defines the pointer for the external target." hexmask.long.word 0xC 0.--15. 1. "BASE_H,The base address for the external target upper 16 bits." line.long 0x10 "VIRT_ALIAS_2_SEC_PROXY0__CFG__SCFG_ORDERID,The Buffer OrderID Register contains the bus orderid value for the buffer memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for the buffer access with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for the buffer access." rgroup.long 0x1000++0xB line.long 0x0 "VIRT_ALIAS_2_SEC_PROXY0__CFG__SCFG_ctl,The Control Register defines controls for proxy thread a." bitfld.long 0x0 31. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread. Is not used otherwise." hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number in the target to use for the proxy thread. If the target base does not start at queue 0 then this is the relative queue number from that base queue." line.long 0x4 "VIRT_ALIAS_2_SEC_PROXY0__CFG__SCFG_evt_map,The Event Map Register defines the event numbers for proxy thread a." hexmask.long.word 0x4 16.--31. 1. "ERR_EVT,Event number for an error from the proxy thread." hexmask.long.word 0x4 0.--15. 1. "THR_EVT,Event number for a threshold event from the proxy thread." line.long 0x8 "VIRT_ALIAS_2_SEC_PROXY0__CFG__SCFG_dst,The Destination Register defines the destination proxy thread for outbound proxy thread a." hexmask.long.word 0x8 0.--15. 1. "THREAD,The proxy thread that is the destination of messages from this outbound proxy thread based on the queue numbers. This is ignored for inbound proxy threads." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_2_SEC_PROXY0_SRC_TARGET_DATA (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_2_SEC_PROXY0_SRC_TARGET_DATA)" base ad:0x4B22C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_SEC_PROXY0__SRC__TARGET_DATA_private,The Proxy Private register contains private information for the proxy thread a and should not be written. writes are ignored. Reads are allowed to know the source thread of the message." hexmask.long.word 0x0 0.--9. 1. "SRC_THR,Proxy source thread of message." rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_2_SEC_PROXY0__SRC__TARGET_DATA_message,The Message Data for proxy thread a. The word with index b = 14 contains the completion final byte." hexmask.long 0x0 0.--31. 1. "DATA,Proxy Message Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_3_SEC_PROXY0_CFG_MMRS (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_3_SEC_PROXY0_CFG_MMRS)" base ad:0x4B31140000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_3_SEC_PROXY0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_3_SEC_PROXY0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 16.--31. 1. "MSG_SIZE,Supported message size in bytes." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_3_SEC_PROXY0__CFG__MMRS_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_3_SEC_PROXY0_CFG_RT (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_3_SEC_PROXY0_CFG_RT)" base ad:0x4B32400000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_3_SEC_PROXY0__CFG__RT_status,The Status Register gives status for proxy thread a." bitfld.long 0x0 31. "ERROR,Error detected on proxy thread. The error will also use the err_evt field to generate an error event which can generate an interrupt. While in error a proxy thread will not process any operations. Write a 0 to clear the error and reset the proxy.." "0,1" rbitfld.long 0x0 30. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread." hexmask.long.byte 0x0 0.--7. 1. "CUR_CNT,Current message count for the proxy thread. For an inbound proxy this is the number of available messages. For an outbound proxy this is the number of free messages that can be written. This value will initialize itself to 0 if the THREAD[a]_CTL.." line.long 0x4 "VIRT_ALIAS_3_SEC_PROXY0__CFG__RT_thr,The Threshold Register controls the threshold for proxy thread a events." hexmask.long.byte 0x4 0.--7. 1. "THR_CNT,Threshold count that causes proxy thread events. For an outbound proxy this will be the number of free messages to cause an event. For an inbound proxy this will be the number of available messages to cause an event." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_3_SEC_PROXY0_CFG_SCFG (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_3_SEC_PROXY0_CFG_SCFG)" base ad:0x4B32800000 rgroup.long 0x0++0x13 line.long 0x0 "VIRT_ALIAS_3_SEC_PROXY0__CFG__SCFG_buffer_l,The Buffer Register defines the pointer for the external buffer." hexmask.long 0x0 0.--31. 1. "BASE_L,The base address for the external buffer lower 32 bits." line.long 0x4 "VIRT_ALIAS_3_SEC_PROXY0__CFG__SCFG_buffer_h,The Buffer Register defines the pointer for the external buffer." hexmask.long.word 0x4 0.--15. 1. "BASE_H,The base address for the external buffer upper 16 bits." line.long 0x8 "VIRT_ALIAS_3_SEC_PROXY0__CFG__SCFG_target_l,The Target Register defines the pointer for the external target." hexmask.long 0x8 0.--31. 1. "BASE_L,The base address for the external target lower 32 bits." line.long 0xC "VIRT_ALIAS_3_SEC_PROXY0__CFG__SCFG_target_h,The Target Register defines the pointer for the external target." hexmask.long.word 0xC 0.--15. 1. "BASE_H,The base address for the external target upper 16 bits." line.long 0x10 "VIRT_ALIAS_3_SEC_PROXY0__CFG__SCFG_ORDERID,The Buffer OrderID Register contains the bus orderid value for the buffer memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for the buffer access with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for the buffer access." rgroup.long 0x1000++0xB line.long 0x0 "VIRT_ALIAS_3_SEC_PROXY0__CFG__SCFG_ctl,The Control Register defines controls for proxy thread a." bitfld.long 0x0 31. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread. Is not used otherwise." hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number in the target to use for the proxy thread. If the target base does not start at queue 0 then this is the relative queue number from that base queue." line.long 0x4 "VIRT_ALIAS_3_SEC_PROXY0__CFG__SCFG_evt_map,The Event Map Register defines the event numbers for proxy thread a." hexmask.long.word 0x4 16.--31. 1. "ERR_EVT,Event number for an error from the proxy thread." hexmask.long.word 0x4 0.--15. 1. "THR_EVT,Event number for a threshold event from the proxy thread." line.long 0x8 "VIRT_ALIAS_3_SEC_PROXY0__CFG__SCFG_dst,The Destination Register defines the destination proxy thread for outbound proxy thread a." hexmask.long.word 0x8 0.--15. 1. "THREAD,The proxy thread that is the destination of messages from this outbound proxy thread based on the queue numbers. This is ignored for inbound proxy threads." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_3_SEC_PROXY0_SRC_TARGET_DATA (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_3_SEC_PROXY0_SRC_TARGET_DATA)" base ad:0x4B32C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_SEC_PROXY0__SRC__TARGET_DATA_private,The Proxy Private register contains private information for the proxy thread a and should not be written. writes are ignored. Reads are allowed to know the source thread of the message." hexmask.long.word 0x0 0.--9. 1. "SRC_THR,Proxy source thread of message." rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_3_SEC_PROXY0__SRC__TARGET_DATA_message,The Message Data for proxy thread a. The word with index b = 14 contains the completion final byte." hexmask.long 0x0 0.--31. 1. "DATA,Proxy Message Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_4_SEC_PROXY0_CFG_MMRS (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_4_SEC_PROXY0_CFG_MMRS)" base ad:0x4B41140000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_4_SEC_PROXY0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_4_SEC_PROXY0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 16.--31. 1. "MSG_SIZE,Supported message size in bytes." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_4_SEC_PROXY0__CFG__MMRS_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_4_SEC_PROXY0_CFG_RT (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_4_SEC_PROXY0_CFG_RT)" base ad:0x4B42400000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_4_SEC_PROXY0__CFG__RT_status,The Status Register gives status for proxy thread a." bitfld.long 0x0 31. "ERROR,Error detected on proxy thread. The error will also use the err_evt field to generate an error event which can generate an interrupt. While in error a proxy thread will not process any operations. Write a 0 to clear the error and reset the proxy.." "0,1" rbitfld.long 0x0 30. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread." hexmask.long.byte 0x0 0.--7. 1. "CUR_CNT,Current message count for the proxy thread. For an inbound proxy this is the number of available messages. For an outbound proxy this is the number of free messages that can be written. This value will initialize itself to 0 if the THREAD[a]_CTL.." line.long 0x4 "VIRT_ALIAS_4_SEC_PROXY0__CFG__RT_thr,The Threshold Register controls the threshold for proxy thread a events." hexmask.long.byte 0x4 0.--7. 1. "THR_CNT,Threshold count that causes proxy thread events. For an outbound proxy this will be the number of free messages to cause an event. For an inbound proxy this will be the number of available messages to cause an event." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_4_SEC_PROXY0_CFG_SCFG (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_4_SEC_PROXY0_CFG_SCFG)" base ad:0x4B42800000 rgroup.long 0x0++0x13 line.long 0x0 "VIRT_ALIAS_4_SEC_PROXY0__CFG__SCFG_buffer_l,The Buffer Register defines the pointer for the external buffer." hexmask.long 0x0 0.--31. 1. "BASE_L,The base address for the external buffer lower 32 bits." line.long 0x4 "VIRT_ALIAS_4_SEC_PROXY0__CFG__SCFG_buffer_h,The Buffer Register defines the pointer for the external buffer." hexmask.long.word 0x4 0.--15. 1. "BASE_H,The base address for the external buffer upper 16 bits." line.long 0x8 "VIRT_ALIAS_4_SEC_PROXY0__CFG__SCFG_target_l,The Target Register defines the pointer for the external target." hexmask.long 0x8 0.--31. 1. "BASE_L,The base address for the external target lower 32 bits." line.long 0xC "VIRT_ALIAS_4_SEC_PROXY0__CFG__SCFG_target_h,The Target Register defines the pointer for the external target." hexmask.long.word 0xC 0.--15. 1. "BASE_H,The base address for the external target upper 16 bits." line.long 0x10 "VIRT_ALIAS_4_SEC_PROXY0__CFG__SCFG_ORDERID,The Buffer OrderID Register contains the bus orderid value for the buffer memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for the buffer access with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for the buffer access." rgroup.long 0x1000++0xB line.long 0x0 "VIRT_ALIAS_4_SEC_PROXY0__CFG__SCFG_ctl,The Control Register defines controls for proxy thread a." bitfld.long 0x0 31. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread. Is not used otherwise." hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number in the target to use for the proxy thread. If the target base does not start at queue 0 then this is the relative queue number from that base queue." line.long 0x4 "VIRT_ALIAS_4_SEC_PROXY0__CFG__SCFG_evt_map,The Event Map Register defines the event numbers for proxy thread a." hexmask.long.word 0x4 16.--31. 1. "ERR_EVT,Event number for an error from the proxy thread." hexmask.long.word 0x4 0.--15. 1. "THR_EVT,Event number for a threshold event from the proxy thread." line.long 0x8 "VIRT_ALIAS_4_SEC_PROXY0__CFG__SCFG_dst,The Destination Register defines the destination proxy thread for outbound proxy thread a." hexmask.long.word 0x8 0.--15. 1. "THREAD,The proxy thread that is the destination of messages from this outbound proxy thread based on the queue numbers. This is ignored for inbound proxy threads." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_4_SEC_PROXY0_SRC_TARGET_DATA (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_4_SEC_PROXY0_SRC_TARGET_DATA)" base ad:0x4B42C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_SEC_PROXY0__SRC__TARGET_DATA_private,The Proxy Private register contains private information for the proxy thread a and should not be written. writes are ignored. Reads are allowed to know the source thread of the message." hexmask.long.word 0x0 0.--9. 1. "SRC_THR,Proxy source thread of message." rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_4_SEC_PROXY0__SRC__TARGET_DATA_message,The Message Data for proxy thread a. The word with index b = 14 contains the completion final byte." hexmask.long 0x0 0.--31. 1. "DATA,Proxy Message Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_5_SEC_PROXY0_CFG_MMRS (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_5_SEC_PROXY0_CFG_MMRS)" base ad:0x4B51140000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_5_SEC_PROXY0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_5_SEC_PROXY0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 16.--31. 1. "MSG_SIZE,Supported message size in bytes." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_5_SEC_PROXY0__CFG__MMRS_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_5_SEC_PROXY0_CFG_RT (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_5_SEC_PROXY0_CFG_RT)" base ad:0x4B52400000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_5_SEC_PROXY0__CFG__RT_status,The Status Register gives status for proxy thread a." bitfld.long 0x0 31. "ERROR,Error detected on proxy thread. The error will also use the err_evt field to generate an error event which can generate an interrupt. While in error a proxy thread will not process any operations. Write a 0 to clear the error and reset the proxy.." "0,1" rbitfld.long 0x0 30. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread." hexmask.long.byte 0x0 0.--7. 1. "CUR_CNT,Current message count for the proxy thread. For an inbound proxy this is the number of available messages. For an outbound proxy this is the number of free messages that can be written. This value will initialize itself to 0 if the THREAD[a]_CTL.." line.long 0x4 "VIRT_ALIAS_5_SEC_PROXY0__CFG__RT_thr,The Threshold Register controls the threshold for proxy thread a events." hexmask.long.byte 0x4 0.--7. 1. "THR_CNT,Threshold count that causes proxy thread events. For an outbound proxy this will be the number of free messages to cause an event. For an inbound proxy this will be the number of available messages to cause an event." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_5_SEC_PROXY0_CFG_SCFG (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_5_SEC_PROXY0_CFG_SCFG)" base ad:0x4B52800000 rgroup.long 0x0++0x13 line.long 0x0 "VIRT_ALIAS_5_SEC_PROXY0__CFG__SCFG_buffer_l,The Buffer Register defines the pointer for the external buffer." hexmask.long 0x0 0.--31. 1. "BASE_L,The base address for the external buffer lower 32 bits." line.long 0x4 "VIRT_ALIAS_5_SEC_PROXY0__CFG__SCFG_buffer_h,The Buffer Register defines the pointer for the external buffer." hexmask.long.word 0x4 0.--15. 1. "BASE_H,The base address for the external buffer upper 16 bits." line.long 0x8 "VIRT_ALIAS_5_SEC_PROXY0__CFG__SCFG_target_l,The Target Register defines the pointer for the external target." hexmask.long 0x8 0.--31. 1. "BASE_L,The base address for the external target lower 32 bits." line.long 0xC "VIRT_ALIAS_5_SEC_PROXY0__CFG__SCFG_target_h,The Target Register defines the pointer for the external target." hexmask.long.word 0xC 0.--15. 1. "BASE_H,The base address for the external target upper 16 bits." line.long 0x10 "VIRT_ALIAS_5_SEC_PROXY0__CFG__SCFG_ORDERID,The Buffer OrderID Register contains the bus orderid value for the buffer memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for the buffer access with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for the buffer access." rgroup.long 0x1000++0xB line.long 0x0 "VIRT_ALIAS_5_SEC_PROXY0__CFG__SCFG_ctl,The Control Register defines controls for proxy thread a." bitfld.long 0x0 31. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread. Is not used otherwise." hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number in the target to use for the proxy thread. If the target base does not start at queue 0 then this is the relative queue number from that base queue." line.long 0x4 "VIRT_ALIAS_5_SEC_PROXY0__CFG__SCFG_evt_map,The Event Map Register defines the event numbers for proxy thread a." hexmask.long.word 0x4 16.--31. 1. "ERR_EVT,Event number for an error from the proxy thread." hexmask.long.word 0x4 0.--15. 1. "THR_EVT,Event number for a threshold event from the proxy thread." line.long 0x8 "VIRT_ALIAS_5_SEC_PROXY0__CFG__SCFG_dst,The Destination Register defines the destination proxy thread for outbound proxy thread a." hexmask.long.word 0x8 0.--15. 1. "THREAD,The proxy thread that is the destination of messages from this outbound proxy thread based on the queue numbers. This is ignored for inbound proxy threads." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_5_SEC_PROXY0_SRC_TARGET_DATA (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_5_SEC_PROXY0_SRC_TARGET_DATA)" base ad:0x4B52C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_SEC_PROXY0__SRC__TARGET_DATA_private,The Proxy Private register contains private information for the proxy thread a and should not be written. writes are ignored. Reads are allowed to know the source thread of the message." hexmask.long.word 0x0 0.--9. 1. "SRC_THR,Proxy source thread of message." rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_5_SEC_PROXY0__SRC__TARGET_DATA_message,The Message Data for proxy thread a. The word with index b = 14 contains the completion final byte." hexmask.long 0x0 0.--31. 1. "DATA,Proxy Message Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_6_SEC_PROXY0_CFG_MMRS (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_6_SEC_PROXY0_CFG_MMRS)" base ad:0x4B61140000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_6_SEC_PROXY0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_6_SEC_PROXY0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 16.--31. 1. "MSG_SIZE,Supported message size in bytes." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_6_SEC_PROXY0__CFG__MMRS_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_6_SEC_PROXY0_CFG_RT (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_6_SEC_PROXY0_CFG_RT)" base ad:0x4B62400000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_6_SEC_PROXY0__CFG__RT_status,The Status Register gives status for proxy thread a." bitfld.long 0x0 31. "ERROR,Error detected on proxy thread. The error will also use the err_evt field to generate an error event which can generate an interrupt. While in error a proxy thread will not process any operations. Write a 0 to clear the error and reset the proxy.." "0,1" rbitfld.long 0x0 30. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread." hexmask.long.byte 0x0 0.--7. 1. "CUR_CNT,Current message count for the proxy thread. For an inbound proxy this is the number of available messages. For an outbound proxy this is the number of free messages that can be written. This value will initialize itself to 0 if the THREAD[a]_CTL.." line.long 0x4 "VIRT_ALIAS_6_SEC_PROXY0__CFG__RT_thr,The Threshold Register controls the threshold for proxy thread a events." hexmask.long.byte 0x4 0.--7. 1. "THR_CNT,Threshold count that causes proxy thread events. For an outbound proxy this will be the number of free messages to cause an event. For an inbound proxy this will be the number of available messages to cause an event." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_6_SEC_PROXY0_CFG_SCFG (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_6_SEC_PROXY0_CFG_SCFG)" base ad:0x4B62800000 rgroup.long 0x0++0x13 line.long 0x0 "VIRT_ALIAS_6_SEC_PROXY0__CFG__SCFG_buffer_l,The Buffer Register defines the pointer for the external buffer." hexmask.long 0x0 0.--31. 1. "BASE_L,The base address for the external buffer lower 32 bits." line.long 0x4 "VIRT_ALIAS_6_SEC_PROXY0__CFG__SCFG_buffer_h,The Buffer Register defines the pointer for the external buffer." hexmask.long.word 0x4 0.--15. 1. "BASE_H,The base address for the external buffer upper 16 bits." line.long 0x8 "VIRT_ALIAS_6_SEC_PROXY0__CFG__SCFG_target_l,The Target Register defines the pointer for the external target." hexmask.long 0x8 0.--31. 1. "BASE_L,The base address for the external target lower 32 bits." line.long 0xC "VIRT_ALIAS_6_SEC_PROXY0__CFG__SCFG_target_h,The Target Register defines the pointer for the external target." hexmask.long.word 0xC 0.--15. 1. "BASE_H,The base address for the external target upper 16 bits." line.long 0x10 "VIRT_ALIAS_6_SEC_PROXY0__CFG__SCFG_ORDERID,The Buffer OrderID Register contains the bus orderid value for the buffer memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for the buffer access with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for the buffer access." rgroup.long 0x1000++0xB line.long 0x0 "VIRT_ALIAS_6_SEC_PROXY0__CFG__SCFG_ctl,The Control Register defines controls for proxy thread a." bitfld.long 0x0 31. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread. Is not used otherwise." hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number in the target to use for the proxy thread. If the target base does not start at queue 0 then this is the relative queue number from that base queue." line.long 0x4 "VIRT_ALIAS_6_SEC_PROXY0__CFG__SCFG_evt_map,The Event Map Register defines the event numbers for proxy thread a." hexmask.long.word 0x4 16.--31. 1. "ERR_EVT,Event number for an error from the proxy thread." hexmask.long.word 0x4 0.--15. 1. "THR_EVT,Event number for a threshold event from the proxy thread." line.long 0x8 "VIRT_ALIAS_6_SEC_PROXY0__CFG__SCFG_dst,The Destination Register defines the destination proxy thread for outbound proxy thread a." hexmask.long.word 0x8 0.--15. 1. "THREAD,The proxy thread that is the destination of messages from this outbound proxy thread based on the queue numbers. This is ignored for inbound proxy threads." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_6_SEC_PROXY0_SRC_TARGET_DATA (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_6_SEC_PROXY0_SRC_TARGET_DATA)" base ad:0x4B62C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_SEC_PROXY0__SRC__TARGET_DATA_private,The Proxy Private register contains private information for the proxy thread a and should not be written. writes are ignored. Reads are allowed to know the source thread of the message." hexmask.long.word 0x0 0.--9. 1. "SRC_THR,Proxy source thread of message." rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_6_SEC_PROXY0__SRC__TARGET_DATA_message,The Message Data for proxy thread a. The word with index b = 14 contains the completion final byte." hexmask.long 0x0 0.--31. 1. "DATA,Proxy Message Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_7_SEC_PROXY0_CFG_MMRS (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_7_SEC_PROXY0_CFG_MMRS)" base ad:0x4B71140000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_7_SEC_PROXY0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_7_SEC_PROXY0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 16.--31. 1. "MSG_SIZE,Supported message size in bytes." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_7_SEC_PROXY0__CFG__MMRS_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_7_SEC_PROXY0_CFG_RT (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_7_SEC_PROXY0_CFG_RT)" base ad:0x4B72400000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_7_SEC_PROXY0__CFG__RT_status,The Status Register gives status for proxy thread a." bitfld.long 0x0 31. "ERROR,Error detected on proxy thread. The error will also use the err_evt field to generate an error event which can generate an interrupt. While in error a proxy thread will not process any operations. Write a 0 to clear the error and reset the proxy.." "0,1" rbitfld.long 0x0 30. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread." hexmask.long.byte 0x0 0.--7. 1. "CUR_CNT,Current message count for the proxy thread. For an inbound proxy this is the number of available messages. For an outbound proxy this is the number of free messages that can be written. This value will initialize itself to 0 if the THREAD[a]_CTL.." line.long 0x4 "VIRT_ALIAS_7_SEC_PROXY0__CFG__RT_thr,The Threshold Register controls the threshold for proxy thread a events." hexmask.long.byte 0x4 0.--7. 1. "THR_CNT,Threshold count that causes proxy thread events. For an outbound proxy this will be the number of free messages to cause an event. For an inbound proxy this will be the number of available messages to cause an event." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_7_SEC_PROXY0_CFG_SCFG (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_7_SEC_PROXY0_CFG_SCFG)" base ad:0x4B72800000 rgroup.long 0x0++0x13 line.long 0x0 "VIRT_ALIAS_7_SEC_PROXY0__CFG__SCFG_buffer_l,The Buffer Register defines the pointer for the external buffer." hexmask.long 0x0 0.--31. 1. "BASE_L,The base address for the external buffer lower 32 bits." line.long 0x4 "VIRT_ALIAS_7_SEC_PROXY0__CFG__SCFG_buffer_h,The Buffer Register defines the pointer for the external buffer." hexmask.long.word 0x4 0.--15. 1. "BASE_H,The base address for the external buffer upper 16 bits." line.long 0x8 "VIRT_ALIAS_7_SEC_PROXY0__CFG__SCFG_target_l,The Target Register defines the pointer for the external target." hexmask.long 0x8 0.--31. 1. "BASE_L,The base address for the external target lower 32 bits." line.long 0xC "VIRT_ALIAS_7_SEC_PROXY0__CFG__SCFG_target_h,The Target Register defines the pointer for the external target." hexmask.long.word 0xC 0.--15. 1. "BASE_H,The base address for the external target upper 16 bits." line.long 0x10 "VIRT_ALIAS_7_SEC_PROXY0__CFG__SCFG_ORDERID,The Buffer OrderID Register contains the bus orderid value for the buffer memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for the buffer access with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for the buffer access." rgroup.long 0x1000++0xB line.long 0x0 "VIRT_ALIAS_7_SEC_PROXY0__CFG__SCFG_ctl,The Control Register defines controls for proxy thread a." bitfld.long 0x0 31. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread. Is not used otherwise." hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number in the target to use for the proxy thread. If the target base does not start at queue 0 then this is the relative queue number from that base queue." line.long 0x4 "VIRT_ALIAS_7_SEC_PROXY0__CFG__SCFG_evt_map,The Event Map Register defines the event numbers for proxy thread a." hexmask.long.word 0x4 16.--31. 1. "ERR_EVT,Event number for an error from the proxy thread." hexmask.long.word 0x4 0.--15. 1. "THR_EVT,Event number for a threshold event from the proxy thread." line.long 0x8 "VIRT_ALIAS_7_SEC_PROXY0__CFG__SCFG_dst,The Destination Register defines the destination proxy thread for outbound proxy thread a." hexmask.long.word 0x8 0.--15. 1. "THREAD,The proxy thread that is the destination of messages from this outbound proxy thread based on the queue numbers. This is ignored for inbound proxy threads." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_7_SEC_PROXY0_SRC_TARGET_DATA (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_7_SEC_PROXY0_SRC_TARGET_DATA)" base ad:0x4B72C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_SEC_PROXY0__SRC__TARGET_DATA_private,The Proxy Private register contains private information for the proxy thread a and should not be written. writes are ignored. Reads are allowed to know the source thread of the message." hexmask.long.word 0x0 0.--9. 1. "SRC_THR,Proxy source thread of message." rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_7_SEC_PROXY0__SRC__TARGET_DATA_message,The Message Data for proxy thread a. The word with index b = 14 contains the completion final byte." hexmask.long 0x0 0.--31. 1. "DATA,Proxy Message Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_8_SEC_PROXY0_CFG_MMRS (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_8_SEC_PROXY0_CFG_MMRS)" base ad:0x4B81140000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_8_SEC_PROXY0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_8_SEC_PROXY0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 16.--31. 1. "MSG_SIZE,Supported message size in bytes." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_8_SEC_PROXY0__CFG__MMRS_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_8_SEC_PROXY0_CFG_RT (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_8_SEC_PROXY0_CFG_RT)" base ad:0x4B82400000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_8_SEC_PROXY0__CFG__RT_status,The Status Register gives status for proxy thread a." bitfld.long 0x0 31. "ERROR,Error detected on proxy thread. The error will also use the err_evt field to generate an error event which can generate an interrupt. While in error a proxy thread will not process any operations. Write a 0 to clear the error and reset the proxy.." "0,1" rbitfld.long 0x0 30. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread." hexmask.long.byte 0x0 0.--7. 1. "CUR_CNT,Current message count for the proxy thread. For an inbound proxy this is the number of available messages. For an outbound proxy this is the number of free messages that can be written. This value will initialize itself to 0 if the THREAD[a]_CTL.." line.long 0x4 "VIRT_ALIAS_8_SEC_PROXY0__CFG__RT_thr,The Threshold Register controls the threshold for proxy thread a events." hexmask.long.byte 0x4 0.--7. 1. "THR_CNT,Threshold count that causes proxy thread events. For an outbound proxy this will be the number of free messages to cause an event. For an inbound proxy this will be the number of available messages to cause an event." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_8_SEC_PROXY0_CFG_SCFG (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_8_SEC_PROXY0_CFG_SCFG)" base ad:0x4B82800000 rgroup.long 0x0++0x13 line.long 0x0 "VIRT_ALIAS_8_SEC_PROXY0__CFG__SCFG_buffer_l,The Buffer Register defines the pointer for the external buffer." hexmask.long 0x0 0.--31. 1. "BASE_L,The base address for the external buffer lower 32 bits." line.long 0x4 "VIRT_ALIAS_8_SEC_PROXY0__CFG__SCFG_buffer_h,The Buffer Register defines the pointer for the external buffer." hexmask.long.word 0x4 0.--15. 1. "BASE_H,The base address for the external buffer upper 16 bits." line.long 0x8 "VIRT_ALIAS_8_SEC_PROXY0__CFG__SCFG_target_l,The Target Register defines the pointer for the external target." hexmask.long 0x8 0.--31. 1. "BASE_L,The base address for the external target lower 32 bits." line.long 0xC "VIRT_ALIAS_8_SEC_PROXY0__CFG__SCFG_target_h,The Target Register defines the pointer for the external target." hexmask.long.word 0xC 0.--15. 1. "BASE_H,The base address for the external target upper 16 bits." line.long 0x10 "VIRT_ALIAS_8_SEC_PROXY0__CFG__SCFG_ORDERID,The Buffer OrderID Register contains the bus orderid value for the buffer memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for the buffer access with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for the buffer access." rgroup.long 0x1000++0xB line.long 0x0 "VIRT_ALIAS_8_SEC_PROXY0__CFG__SCFG_ctl,The Control Register defines controls for proxy thread a." bitfld.long 0x0 31. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread. Is not used otherwise." hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number in the target to use for the proxy thread. If the target base does not start at queue 0 then this is the relative queue number from that base queue." line.long 0x4 "VIRT_ALIAS_8_SEC_PROXY0__CFG__SCFG_evt_map,The Event Map Register defines the event numbers for proxy thread a." hexmask.long.word 0x4 16.--31. 1. "ERR_EVT,Event number for an error from the proxy thread." hexmask.long.word 0x4 0.--15. 1. "THR_EVT,Event number for a threshold event from the proxy thread." line.long 0x8 "VIRT_ALIAS_8_SEC_PROXY0__CFG__SCFG_dst,The Destination Register defines the destination proxy thread for outbound proxy thread a." hexmask.long.word 0x8 0.--15. 1. "THREAD,The proxy thread that is the destination of messages from this outbound proxy thread based on the queue numbers. This is ignored for inbound proxy threads." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_8_SEC_PROXY0_SRC_TARGET_DATA (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_8_SEC_PROXY0_SRC_TARGET_DATA)" base ad:0x4B82C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_SEC_PROXY0__SRC__TARGET_DATA_private,The Proxy Private register contains private information for the proxy thread a and should not be written. writes are ignored. Reads are allowed to know the source thread of the message." hexmask.long.word 0x0 0.--9. 1. "SRC_THR,Proxy source thread of message." rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_8_SEC_PROXY0__SRC__TARGET_DATA_message,The Message Data for proxy thread a. The word with index b = 14 contains the completion final byte." hexmask.long 0x0 0.--31. 1. "DATA,Proxy Message Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_9_SEC_PROXY0_CFG_MMRS (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_9_SEC_PROXY0_CFG_MMRS)" base ad:0x4B91140000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_9_SEC_PROXY0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_9_SEC_PROXY0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 16.--31. 1. "MSG_SIZE,Supported message size in bytes." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_9_SEC_PROXY0__CFG__MMRS_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_9_SEC_PROXY0_CFG_RT (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_9_SEC_PROXY0_CFG_RT)" base ad:0x4B92400000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_9_SEC_PROXY0__CFG__RT_status,The Status Register gives status for proxy thread a." bitfld.long 0x0 31. "ERROR,Error detected on proxy thread. The error will also use the err_evt field to generate an error event which can generate an interrupt. While in error a proxy thread will not process any operations. Write a 0 to clear the error and reset the proxy.." "0,1" rbitfld.long 0x0 30. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread." hexmask.long.byte 0x0 0.--7. 1. "CUR_CNT,Current message count for the proxy thread. For an inbound proxy this is the number of available messages. For an outbound proxy this is the number of free messages that can be written. This value will initialize itself to 0 if the THREAD[a]_CTL.." line.long 0x4 "VIRT_ALIAS_9_SEC_PROXY0__CFG__RT_thr,The Threshold Register controls the threshold for proxy thread a events." hexmask.long.byte 0x4 0.--7. 1. "THR_CNT,Threshold count that causes proxy thread events. For an outbound proxy this will be the number of free messages to cause an event. For an inbound proxy this will be the number of available messages to cause an event." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_9_SEC_PROXY0_CFG_SCFG (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_9_SEC_PROXY0_CFG_SCFG)" base ad:0x4B92800000 rgroup.long 0x0++0x13 line.long 0x0 "VIRT_ALIAS_9_SEC_PROXY0__CFG__SCFG_buffer_l,The Buffer Register defines the pointer for the external buffer." hexmask.long 0x0 0.--31. 1. "BASE_L,The base address for the external buffer lower 32 bits." line.long 0x4 "VIRT_ALIAS_9_SEC_PROXY0__CFG__SCFG_buffer_h,The Buffer Register defines the pointer for the external buffer." hexmask.long.word 0x4 0.--15. 1. "BASE_H,The base address for the external buffer upper 16 bits." line.long 0x8 "VIRT_ALIAS_9_SEC_PROXY0__CFG__SCFG_target_l,The Target Register defines the pointer for the external target." hexmask.long 0x8 0.--31. 1. "BASE_L,The base address for the external target lower 32 bits." line.long 0xC "VIRT_ALIAS_9_SEC_PROXY0__CFG__SCFG_target_h,The Target Register defines the pointer for the external target." hexmask.long.word 0xC 0.--15. 1. "BASE_H,The base address for the external target upper 16 bits." line.long 0x10 "VIRT_ALIAS_9_SEC_PROXY0__CFG__SCFG_ORDERID,The Buffer OrderID Register contains the bus orderid value for the buffer memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for the buffer access with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for the buffer access." rgroup.long 0x1000++0xB line.long 0x0 "VIRT_ALIAS_9_SEC_PROXY0__CFG__SCFG_ctl,The Control Register defines controls for proxy thread a." bitfld.long 0x0 31. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread. Is not used otherwise." hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number in the target to use for the proxy thread. If the target base does not start at queue 0 then this is the relative queue number from that base queue." line.long 0x4 "VIRT_ALIAS_9_SEC_PROXY0__CFG__SCFG_evt_map,The Event Map Register defines the event numbers for proxy thread a." hexmask.long.word 0x4 16.--31. 1. "ERR_EVT,Event number for an error from the proxy thread." hexmask.long.word 0x4 0.--15. 1. "THR_EVT,Event number for a threshold event from the proxy thread." line.long 0x8 "VIRT_ALIAS_9_SEC_PROXY0__CFG__SCFG_dst,The Destination Register defines the destination proxy thread for outbound proxy thread a." hexmask.long.word 0x8 0.--15. 1. "THREAD,The proxy thread that is the destination of messages from this outbound proxy thread based on the queue numbers. This is ignored for inbound proxy threads." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_9_SEC_PROXY0_SRC_TARGET_DATA (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_9_SEC_PROXY0_SRC_TARGET_DATA)" base ad:0x4B92C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_SEC_PROXY0__SRC__TARGET_DATA_private,The Proxy Private register contains private information for the proxy thread a and should not be written. writes are ignored. Reads are allowed to know the source thread of the message." hexmask.long.word 0x0 0.--9. 1. "SRC_THR,Proxy source thread of message." rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_9_SEC_PROXY0__SRC__TARGET_DATA_message,The Message Data for proxy thread a. The word with index b = 14 contains the completion final byte." hexmask.long 0x0 0.--31. 1. "DATA,Proxy Message Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_10_SEC_PROXY0_CFG_MMRS (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_10_SEC_PROXY0_CFG_MMRS)" base ad:0x4BA1140000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_10_SEC_PROXY0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_10_SEC_PROXY0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 16.--31. 1. "MSG_SIZE,Supported message size in bytes." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_10_SEC_PROXY0__CFG__MMRS_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_10_SEC_PROXY0_CFG_RT (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_10_SEC_PROXY0_CFG_RT)" base ad:0x4BA2400000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_10_SEC_PROXY0__CFG__RT_status,The Status Register gives status for proxy thread a." bitfld.long 0x0 31. "ERROR,Error detected on proxy thread. The error will also use the err_evt field to generate an error event which can generate an interrupt. While in error a proxy thread will not process any operations. Write a 0 to clear the error and reset the proxy.." "0,1" rbitfld.long 0x0 30. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread." hexmask.long.byte 0x0 0.--7. 1. "CUR_CNT,Current message count for the proxy thread. For an inbound proxy this is the number of available messages. For an outbound proxy this is the number of free messages that can be written. This value will initialize itself to 0 if the THREAD[a]_CTL.." line.long 0x4 "VIRT_ALIAS_10_SEC_PROXY0__CFG__RT_thr,The Threshold Register controls the threshold for proxy thread a events." hexmask.long.byte 0x4 0.--7. 1. "THR_CNT,Threshold count that causes proxy thread events. For an outbound proxy this will be the number of free messages to cause an event. For an inbound proxy this will be the number of available messages to cause an event." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_10_SEC_PROXY0_CFG_SCFG (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_10_SEC_PROXY0_CFG_SCFG)" base ad:0x4BA2800000 rgroup.long 0x0++0x13 line.long 0x0 "VIRT_ALIAS_10_SEC_PROXY0__CFG__SCFG_buffer_l,The Buffer Register defines the pointer for the external buffer." hexmask.long 0x0 0.--31. 1. "BASE_L,The base address for the external buffer lower 32 bits." line.long 0x4 "VIRT_ALIAS_10_SEC_PROXY0__CFG__SCFG_buffer_h,The Buffer Register defines the pointer for the external buffer." hexmask.long.word 0x4 0.--15. 1. "BASE_H,The base address for the external buffer upper 16 bits." line.long 0x8 "VIRT_ALIAS_10_SEC_PROXY0__CFG__SCFG_target_l,The Target Register defines the pointer for the external target." hexmask.long 0x8 0.--31. 1. "BASE_L,The base address for the external target lower 32 bits." line.long 0xC "VIRT_ALIAS_10_SEC_PROXY0__CFG__SCFG_target_h,The Target Register defines the pointer for the external target." hexmask.long.word 0xC 0.--15. 1. "BASE_H,The base address for the external target upper 16 bits." line.long 0x10 "VIRT_ALIAS_10_SEC_PROXY0__CFG__SCFG_ORDERID,The Buffer OrderID Register contains the bus orderid value for the buffer memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for the buffer access with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for the buffer access." rgroup.long 0x1000++0xB line.long 0x0 "VIRT_ALIAS_10_SEC_PROXY0__CFG__SCFG_ctl,The Control Register defines controls for proxy thread a." bitfld.long 0x0 31. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread. Is not used otherwise." hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number in the target to use for the proxy thread. If the target base does not start at queue 0 then this is the relative queue number from that base queue." line.long 0x4 "VIRT_ALIAS_10_SEC_PROXY0__CFG__SCFG_evt_map,The Event Map Register defines the event numbers for proxy thread a." hexmask.long.word 0x4 16.--31. 1. "ERR_EVT,Event number for an error from the proxy thread." hexmask.long.word 0x4 0.--15. 1. "THR_EVT,Event number for a threshold event from the proxy thread." line.long 0x8 "VIRT_ALIAS_10_SEC_PROXY0__CFG__SCFG_dst,The Destination Register defines the destination proxy thread for outbound proxy thread a." hexmask.long.word 0x8 0.--15. 1. "THREAD,The proxy thread that is the destination of messages from this outbound proxy thread based on the queue numbers. This is ignored for inbound proxy threads." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_10_SEC_PROXY0_SRC_TARGET_DATA (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_10_SEC_PROXY0_SRC_TARGET_DATA)" base ad:0x4BA2C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_SEC_PROXY0__SRC__TARGET_DATA_private,The Proxy Private register contains private information for the proxy thread a and should not be written. writes are ignored. Reads are allowed to know the source thread of the message." hexmask.long.word 0x0 0.--9. 1. "SRC_THR,Proxy source thread of message." rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_10_SEC_PROXY0__SRC__TARGET_DATA_message,The Message Data for proxy thread a. The word with index b = 14 contains the completion final byte." hexmask.long 0x0 0.--31. 1. "DATA,Proxy Message Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_11_SEC_PROXY0_CFG_MMRS (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_11_SEC_PROXY0_CFG_MMRS)" base ad:0x4BB1140000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_11_SEC_PROXY0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_11_SEC_PROXY0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 16.--31. 1. "MSG_SIZE,Supported message size in bytes." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_11_SEC_PROXY0__CFG__MMRS_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_11_SEC_PROXY0_CFG_RT (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_11_SEC_PROXY0_CFG_RT)" base ad:0x4BB2400000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_11_SEC_PROXY0__CFG__RT_status,The Status Register gives status for proxy thread a." bitfld.long 0x0 31. "ERROR,Error detected on proxy thread. The error will also use the err_evt field to generate an error event which can generate an interrupt. While in error a proxy thread will not process any operations. Write a 0 to clear the error and reset the proxy.." "0,1" rbitfld.long 0x0 30. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread." hexmask.long.byte 0x0 0.--7. 1. "CUR_CNT,Current message count for the proxy thread. For an inbound proxy this is the number of available messages. For an outbound proxy this is the number of free messages that can be written. This value will initialize itself to 0 if the THREAD[a]_CTL.." line.long 0x4 "VIRT_ALIAS_11_SEC_PROXY0__CFG__RT_thr,The Threshold Register controls the threshold for proxy thread a events." hexmask.long.byte 0x4 0.--7. 1. "THR_CNT,Threshold count that causes proxy thread events. For an outbound proxy this will be the number of free messages to cause an event. For an inbound proxy this will be the number of available messages to cause an event." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_11_SEC_PROXY0_CFG_SCFG (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_11_SEC_PROXY0_CFG_SCFG)" base ad:0x4BB2800000 rgroup.long 0x0++0x13 line.long 0x0 "VIRT_ALIAS_11_SEC_PROXY0__CFG__SCFG_buffer_l,The Buffer Register defines the pointer for the external buffer." hexmask.long 0x0 0.--31. 1. "BASE_L,The base address for the external buffer lower 32 bits." line.long 0x4 "VIRT_ALIAS_11_SEC_PROXY0__CFG__SCFG_buffer_h,The Buffer Register defines the pointer for the external buffer." hexmask.long.word 0x4 0.--15. 1. "BASE_H,The base address for the external buffer upper 16 bits." line.long 0x8 "VIRT_ALIAS_11_SEC_PROXY0__CFG__SCFG_target_l,The Target Register defines the pointer for the external target." hexmask.long 0x8 0.--31. 1. "BASE_L,The base address for the external target lower 32 bits." line.long 0xC "VIRT_ALIAS_11_SEC_PROXY0__CFG__SCFG_target_h,The Target Register defines the pointer for the external target." hexmask.long.word 0xC 0.--15. 1. "BASE_H,The base address for the external target upper 16 bits." line.long 0x10 "VIRT_ALIAS_11_SEC_PROXY0__CFG__SCFG_ORDERID,The Buffer OrderID Register contains the bus orderid value for the buffer memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for the buffer access with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for the buffer access." rgroup.long 0x1000++0xB line.long 0x0 "VIRT_ALIAS_11_SEC_PROXY0__CFG__SCFG_ctl,The Control Register defines controls for proxy thread a." bitfld.long 0x0 31. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread. Is not used otherwise." hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number in the target to use for the proxy thread. If the target base does not start at queue 0 then this is the relative queue number from that base queue." line.long 0x4 "VIRT_ALIAS_11_SEC_PROXY0__CFG__SCFG_evt_map,The Event Map Register defines the event numbers for proxy thread a." hexmask.long.word 0x4 16.--31. 1. "ERR_EVT,Event number for an error from the proxy thread." hexmask.long.word 0x4 0.--15. 1. "THR_EVT,Event number for a threshold event from the proxy thread." line.long 0x8 "VIRT_ALIAS_11_SEC_PROXY0__CFG__SCFG_dst,The Destination Register defines the destination proxy thread for outbound proxy thread a." hexmask.long.word 0x8 0.--15. 1. "THREAD,The proxy thread that is the destination of messages from this outbound proxy thread based on the queue numbers. This is ignored for inbound proxy threads." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_11_SEC_PROXY0_SRC_TARGET_DATA (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_11_SEC_PROXY0_SRC_TARGET_DATA)" base ad:0x4BB2C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_SEC_PROXY0__SRC__TARGET_DATA_private,The Proxy Private register contains private information for the proxy thread a and should not be written. writes are ignored. Reads are allowed to know the source thread of the message." hexmask.long.word 0x0 0.--9. 1. "SRC_THR,Proxy source thread of message." rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_11_SEC_PROXY0__SRC__TARGET_DATA_message,The Message Data for proxy thread a. The word with index b = 14 contains the completion final byte." hexmask.long 0x0 0.--31. 1. "DATA,Proxy Message Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_12_SEC_PROXY0_CFG_MMRS (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_12_SEC_PROXY0_CFG_MMRS)" base ad:0x4BC1140000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_12_SEC_PROXY0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_12_SEC_PROXY0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 16.--31. 1. "MSG_SIZE,Supported message size in bytes." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_12_SEC_PROXY0__CFG__MMRS_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_12_SEC_PROXY0_CFG_RT (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_12_SEC_PROXY0_CFG_RT)" base ad:0x4BC2400000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_12_SEC_PROXY0__CFG__RT_status,The Status Register gives status for proxy thread a." bitfld.long 0x0 31. "ERROR,Error detected on proxy thread. The error will also use the err_evt field to generate an error event which can generate an interrupt. While in error a proxy thread will not process any operations. Write a 0 to clear the error and reset the proxy.." "0,1" rbitfld.long 0x0 30. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread." hexmask.long.byte 0x0 0.--7. 1. "CUR_CNT,Current message count for the proxy thread. For an inbound proxy this is the number of available messages. For an outbound proxy this is the number of free messages that can be written. This value will initialize itself to 0 if the THREAD[a]_CTL.." line.long 0x4 "VIRT_ALIAS_12_SEC_PROXY0__CFG__RT_thr,The Threshold Register controls the threshold for proxy thread a events." hexmask.long.byte 0x4 0.--7. 1. "THR_CNT,Threshold count that causes proxy thread events. For an outbound proxy this will be the number of free messages to cause an event. For an inbound proxy this will be the number of available messages to cause an event." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_12_SEC_PROXY0_CFG_SCFG (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_12_SEC_PROXY0_CFG_SCFG)" base ad:0x4BC2800000 rgroup.long 0x0++0x13 line.long 0x0 "VIRT_ALIAS_12_SEC_PROXY0__CFG__SCFG_buffer_l,The Buffer Register defines the pointer for the external buffer." hexmask.long 0x0 0.--31. 1. "BASE_L,The base address for the external buffer lower 32 bits." line.long 0x4 "VIRT_ALIAS_12_SEC_PROXY0__CFG__SCFG_buffer_h,The Buffer Register defines the pointer for the external buffer." hexmask.long.word 0x4 0.--15. 1. "BASE_H,The base address for the external buffer upper 16 bits." line.long 0x8 "VIRT_ALIAS_12_SEC_PROXY0__CFG__SCFG_target_l,The Target Register defines the pointer for the external target." hexmask.long 0x8 0.--31. 1. "BASE_L,The base address for the external target lower 32 bits." line.long 0xC "VIRT_ALIAS_12_SEC_PROXY0__CFG__SCFG_target_h,The Target Register defines the pointer for the external target." hexmask.long.word 0xC 0.--15. 1. "BASE_H,The base address for the external target upper 16 bits." line.long 0x10 "VIRT_ALIAS_12_SEC_PROXY0__CFG__SCFG_ORDERID,The Buffer OrderID Register contains the bus orderid value for the buffer memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for the buffer access with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for the buffer access." rgroup.long 0x1000++0xB line.long 0x0 "VIRT_ALIAS_12_SEC_PROXY0__CFG__SCFG_ctl,The Control Register defines controls for proxy thread a." bitfld.long 0x0 31. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread. Is not used otherwise." hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number in the target to use for the proxy thread. If the target base does not start at queue 0 then this is the relative queue number from that base queue." line.long 0x4 "VIRT_ALIAS_12_SEC_PROXY0__CFG__SCFG_evt_map,The Event Map Register defines the event numbers for proxy thread a." hexmask.long.word 0x4 16.--31. 1. "ERR_EVT,Event number for an error from the proxy thread." hexmask.long.word 0x4 0.--15. 1. "THR_EVT,Event number for a threshold event from the proxy thread." line.long 0x8 "VIRT_ALIAS_12_SEC_PROXY0__CFG__SCFG_dst,The Destination Register defines the destination proxy thread for outbound proxy thread a." hexmask.long.word 0x8 0.--15. 1. "THREAD,The proxy thread that is the destination of messages from this outbound proxy thread based on the queue numbers. This is ignored for inbound proxy threads." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_12_SEC_PROXY0_SRC_TARGET_DATA (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_12_SEC_PROXY0_SRC_TARGET_DATA)" base ad:0x4BC2C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_SEC_PROXY0__SRC__TARGET_DATA_private,The Proxy Private register contains private information for the proxy thread a and should not be written. writes are ignored. Reads are allowed to know the source thread of the message." hexmask.long.word 0x0 0.--9. 1. "SRC_THR,Proxy source thread of message." rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_12_SEC_PROXY0__SRC__TARGET_DATA_message,The Message Data for proxy thread a. The word with index b = 14 contains the completion final byte." hexmask.long 0x0 0.--31. 1. "DATA,Proxy Message Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_13_SEC_PROXY0_CFG_MMRS (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_13_SEC_PROXY0_CFG_MMRS)" base ad:0x4BD1140000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_13_SEC_PROXY0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_13_SEC_PROXY0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 16.--31. 1. "MSG_SIZE,Supported message size in bytes." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_13_SEC_PROXY0__CFG__MMRS_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_13_SEC_PROXY0_CFG_RT (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_13_SEC_PROXY0_CFG_RT)" base ad:0x4BD2400000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_13_SEC_PROXY0__CFG__RT_status,The Status Register gives status for proxy thread a." bitfld.long 0x0 31. "ERROR,Error detected on proxy thread. The error will also use the err_evt field to generate an error event which can generate an interrupt. While in error a proxy thread will not process any operations. Write a 0 to clear the error and reset the proxy.." "0,1" rbitfld.long 0x0 30. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread." hexmask.long.byte 0x0 0.--7. 1. "CUR_CNT,Current message count for the proxy thread. For an inbound proxy this is the number of available messages. For an outbound proxy this is the number of free messages that can be written. This value will initialize itself to 0 if the THREAD[a]_CTL.." line.long 0x4 "VIRT_ALIAS_13_SEC_PROXY0__CFG__RT_thr,The Threshold Register controls the threshold for proxy thread a events." hexmask.long.byte 0x4 0.--7. 1. "THR_CNT,Threshold count that causes proxy thread events. For an outbound proxy this will be the number of free messages to cause an event. For an inbound proxy this will be the number of available messages to cause an event." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_13_SEC_PROXY0_CFG_SCFG (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_13_SEC_PROXY0_CFG_SCFG)" base ad:0x4BD2800000 rgroup.long 0x0++0x13 line.long 0x0 "VIRT_ALIAS_13_SEC_PROXY0__CFG__SCFG_buffer_l,The Buffer Register defines the pointer for the external buffer." hexmask.long 0x0 0.--31. 1. "BASE_L,The base address for the external buffer lower 32 bits." line.long 0x4 "VIRT_ALIAS_13_SEC_PROXY0__CFG__SCFG_buffer_h,The Buffer Register defines the pointer for the external buffer." hexmask.long.word 0x4 0.--15. 1. "BASE_H,The base address for the external buffer upper 16 bits." line.long 0x8 "VIRT_ALIAS_13_SEC_PROXY0__CFG__SCFG_target_l,The Target Register defines the pointer for the external target." hexmask.long 0x8 0.--31. 1. "BASE_L,The base address for the external target lower 32 bits." line.long 0xC "VIRT_ALIAS_13_SEC_PROXY0__CFG__SCFG_target_h,The Target Register defines the pointer for the external target." hexmask.long.word 0xC 0.--15. 1. "BASE_H,The base address for the external target upper 16 bits." line.long 0x10 "VIRT_ALIAS_13_SEC_PROXY0__CFG__SCFG_ORDERID,The Buffer OrderID Register contains the bus orderid value for the buffer memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for the buffer access with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for the buffer access." rgroup.long 0x1000++0xB line.long 0x0 "VIRT_ALIAS_13_SEC_PROXY0__CFG__SCFG_ctl,The Control Register defines controls for proxy thread a." bitfld.long 0x0 31. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread. Is not used otherwise." hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number in the target to use for the proxy thread. If the target base does not start at queue 0 then this is the relative queue number from that base queue." line.long 0x4 "VIRT_ALIAS_13_SEC_PROXY0__CFG__SCFG_evt_map,The Event Map Register defines the event numbers for proxy thread a." hexmask.long.word 0x4 16.--31. 1. "ERR_EVT,Event number for an error from the proxy thread." hexmask.long.word 0x4 0.--15. 1. "THR_EVT,Event number for a threshold event from the proxy thread." line.long 0x8 "VIRT_ALIAS_13_SEC_PROXY0__CFG__SCFG_dst,The Destination Register defines the destination proxy thread for outbound proxy thread a." hexmask.long.word 0x8 0.--15. 1. "THREAD,The proxy thread that is the destination of messages from this outbound proxy thread based on the queue numbers. This is ignored for inbound proxy threads." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_13_SEC_PROXY0_SRC_TARGET_DATA (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_13_SEC_PROXY0_SRC_TARGET_DATA)" base ad:0x4BD2C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_SEC_PROXY0__SRC__TARGET_DATA_private,The Proxy Private register contains private information for the proxy thread a and should not be written. writes are ignored. Reads are allowed to know the source thread of the message." hexmask.long.word 0x0 0.--9. 1. "SRC_THR,Proxy source thread of message." rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_13_SEC_PROXY0__SRC__TARGET_DATA_message,The Message Data for proxy thread a. The word with index b = 14 contains the completion final byte." hexmask.long 0x0 0.--31. 1. "DATA,Proxy Message Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_14_SEC_PROXY0_CFG_MMRS (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_14_SEC_PROXY0_CFG_MMRS)" base ad:0x4BE1140000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_14_SEC_PROXY0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_14_SEC_PROXY0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 16.--31. 1. "MSG_SIZE,Supported message size in bytes." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_14_SEC_PROXY0__CFG__MMRS_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_14_SEC_PROXY0_CFG_RT (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_14_SEC_PROXY0_CFG_RT)" base ad:0x4BE2400000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_14_SEC_PROXY0__CFG__RT_status,The Status Register gives status for proxy thread a." bitfld.long 0x0 31. "ERROR,Error detected on proxy thread. The error will also use the err_evt field to generate an error event which can generate an interrupt. While in error a proxy thread will not process any operations. Write a 0 to clear the error and reset the proxy.." "0,1" rbitfld.long 0x0 30. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread." hexmask.long.byte 0x0 0.--7. 1. "CUR_CNT,Current message count for the proxy thread. For an inbound proxy this is the number of available messages. For an outbound proxy this is the number of free messages that can be written. This value will initialize itself to 0 if the THREAD[a]_CTL.." line.long 0x4 "VIRT_ALIAS_14_SEC_PROXY0__CFG__RT_thr,The Threshold Register controls the threshold for proxy thread a events." hexmask.long.byte 0x4 0.--7. 1. "THR_CNT,Threshold count that causes proxy thread events. For an outbound proxy this will be the number of free messages to cause an event. For an inbound proxy this will be the number of available messages to cause an event." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_14_SEC_PROXY0_CFG_SCFG (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_14_SEC_PROXY0_CFG_SCFG)" base ad:0x4BE2800000 rgroup.long 0x0++0x13 line.long 0x0 "VIRT_ALIAS_14_SEC_PROXY0__CFG__SCFG_buffer_l,The Buffer Register defines the pointer for the external buffer." hexmask.long 0x0 0.--31. 1. "BASE_L,The base address for the external buffer lower 32 bits." line.long 0x4 "VIRT_ALIAS_14_SEC_PROXY0__CFG__SCFG_buffer_h,The Buffer Register defines the pointer for the external buffer." hexmask.long.word 0x4 0.--15. 1. "BASE_H,The base address for the external buffer upper 16 bits." line.long 0x8 "VIRT_ALIAS_14_SEC_PROXY0__CFG__SCFG_target_l,The Target Register defines the pointer for the external target." hexmask.long 0x8 0.--31. 1. "BASE_L,The base address for the external target lower 32 bits." line.long 0xC "VIRT_ALIAS_14_SEC_PROXY0__CFG__SCFG_target_h,The Target Register defines the pointer for the external target." hexmask.long.word 0xC 0.--15. 1. "BASE_H,The base address for the external target upper 16 bits." line.long 0x10 "VIRT_ALIAS_14_SEC_PROXY0__CFG__SCFG_ORDERID,The Buffer OrderID Register contains the bus orderid value for the buffer memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for the buffer access with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for the buffer access." rgroup.long 0x1000++0xB line.long 0x0 "VIRT_ALIAS_14_SEC_PROXY0__CFG__SCFG_ctl,The Control Register defines controls for proxy thread a." bitfld.long 0x0 31. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread. Is not used otherwise." hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number in the target to use for the proxy thread. If the target base does not start at queue 0 then this is the relative queue number from that base queue." line.long 0x4 "VIRT_ALIAS_14_SEC_PROXY0__CFG__SCFG_evt_map,The Event Map Register defines the event numbers for proxy thread a." hexmask.long.word 0x4 16.--31. 1. "ERR_EVT,Event number for an error from the proxy thread." hexmask.long.word 0x4 0.--15. 1. "THR_EVT,Event number for a threshold event from the proxy thread." line.long 0x8 "VIRT_ALIAS_14_SEC_PROXY0__CFG__SCFG_dst,The Destination Register defines the destination proxy thread for outbound proxy thread a." hexmask.long.word 0x8 0.--15. 1. "THREAD,The proxy thread that is the destination of messages from this outbound proxy thread based on the queue numbers. This is ignored for inbound proxy threads." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_14_SEC_PROXY0_SRC_TARGET_DATA (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_14_SEC_PROXY0_SRC_TARGET_DATA)" base ad:0x4BE2C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_SEC_PROXY0__SRC__TARGET_DATA_private,The Proxy Private register contains private information for the proxy thread a and should not be written. writes are ignored. Reads are allowed to know the source thread of the message." hexmask.long.word 0x0 0.--9. 1. "SRC_THR,Proxy source thread of message." rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_14_SEC_PROXY0__SRC__TARGET_DATA_message,The Message Data for proxy thread a. The word with index b = 14 contains the completion final byte." hexmask.long 0x0 0.--31. 1. "DATA,Proxy Message Data" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_15_SEC_PROXY0_CFG_MMRS (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_15_SEC_PROXY0_CFG_MMRS)" base ad:0x4BF1140000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_15_SEC_PROXY0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIRT_ALIAS_15_SEC_PROXY0__CFG__MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 16.--31. 1. "MSG_SIZE,Supported message size in bytes." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_15_SEC_PROXY0__CFG__MMRS_glb_evt,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_15_SEC_PROXY0_CFG_RT (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_15_SEC_PROXY0_CFG_RT)" base ad:0x4BF2400000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_15_SEC_PROXY0__CFG__RT_status,The Status Register gives status for proxy thread a." bitfld.long 0x0 31. "ERROR,Error detected on proxy thread. The error will also use the err_evt field to generate an error event which can generate an interrupt. While in error a proxy thread will not process any operations. Write a 0 to clear the error and reset the proxy.." "0,1" rbitfld.long 0x0 30. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread." hexmask.long.byte 0x0 0.--7. 1. "CUR_CNT,Current message count for the proxy thread. For an inbound proxy this is the number of available messages. For an outbound proxy this is the number of free messages that can be written. This value will initialize itself to 0 if the THREAD[a]_CTL.." line.long 0x4 "VIRT_ALIAS_15_SEC_PROXY0__CFG__RT_thr,The Threshold Register controls the threshold for proxy thread a events." hexmask.long.byte 0x4 0.--7. 1. "THR_CNT,Threshold count that causes proxy thread events. For an outbound proxy this will be the number of free messages to cause an event. For an inbound proxy this will be the number of available messages to cause an event." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_15_SEC_PROXY0_CFG_SCFG (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_15_SEC_PROXY0_CFG_SCFG)" base ad:0x4BF2800000 rgroup.long 0x0++0x13 line.long 0x0 "VIRT_ALIAS_15_SEC_PROXY0__CFG__SCFG_buffer_l,The Buffer Register defines the pointer for the external buffer." hexmask.long 0x0 0.--31. 1. "BASE_L,The base address for the external buffer lower 32 bits." line.long 0x4 "VIRT_ALIAS_15_SEC_PROXY0__CFG__SCFG_buffer_h,The Buffer Register defines the pointer for the external buffer." hexmask.long.word 0x4 0.--15. 1. "BASE_H,The base address for the external buffer upper 16 bits." line.long 0x8 "VIRT_ALIAS_15_SEC_PROXY0__CFG__SCFG_target_l,The Target Register defines the pointer for the external target." hexmask.long 0x8 0.--31. 1. "BASE_L,The base address for the external target lower 32 bits." line.long 0xC "VIRT_ALIAS_15_SEC_PROXY0__CFG__SCFG_target_h,The Target Register defines the pointer for the external target." hexmask.long.word 0xC 0.--15. 1. "BASE_H,The base address for the external target upper 16 bits." line.long 0x10 "VIRT_ALIAS_15_SEC_PROXY0__CFG__SCFG_ORDERID,The Buffer OrderID Register contains the bus orderid value for the buffer memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for the buffer access with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for the buffer access." rgroup.long 0x1000++0xB line.long 0x0 "VIRT_ALIAS_15_SEC_PROXY0__CFG__SCFG_ctl,The Control Register defines controls for proxy thread a." bitfld.long 0x0 31. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread. Is not used otherwise." hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number in the target to use for the proxy thread. If the target base does not start at queue 0 then this is the relative queue number from that base queue." line.long 0x4 "VIRT_ALIAS_15_SEC_PROXY0__CFG__SCFG_evt_map,The Event Map Register defines the event numbers for proxy thread a." hexmask.long.word 0x4 16.--31. 1. "ERR_EVT,Event number for an error from the proxy thread." hexmask.long.word 0x4 0.--15. 1. "THR_EVT,Event number for a threshold event from the proxy thread." line.long 0x8 "VIRT_ALIAS_15_SEC_PROXY0__CFG__SCFG_dst,The Destination Register defines the destination proxy thread for outbound proxy thread a." hexmask.long.word 0x8 0.--15. 1. "THREAD,The proxy thread that is the destination of messages from this outbound proxy thread based on the queue numbers. This is ignored for inbound proxy threads." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SEC_PROXY_0_VIRT_ALIAS_15_SEC_PROXY0_SRC_TARGET_DATA (NAVSS0_SEC_PROXY_0_VIRT_ALIAS_15_SEC_PROXY0_SRC_TARGET_DATA)" base ad:0x4BF2C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_SEC_PROXY0__SRC__TARGET_DATA_private,The Proxy Private register contains private information for the proxy thread a and should not be written. writes are ignored. Reads are allowed to know the source thread of the message." hexmask.long.word 0x0 0.--9. 1. "SRC_THR,Proxy source thread of message." rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_15_SEC_PROXY0__SRC__TARGET_DATA_message,The Message Data for proxy thread a. The word with index b = 14 contains the completion final byte." hexmask.long 0x0 0.--31. 1. "DATA,Proxy Message Data" tree.end endif tree.end tree "NAVSS0_SPINLOCK_0" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SPINLOCK_0_SPINLOCK (NAVSS0_SPINLOCK_0_SPINLOCK)" base ad:0x30E00000 rgroup.long 0x0++0x3 line.long 0x0 "SPINLOCK0__CFG__REGS_SPLOCK_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "SPINLOCK0__CFG__REGS_SPLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock" bitfld.long 0x0 1. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0 It has the same effect as the hardware reset Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and free all of the.." "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SPINLOCK0__CFG__REGS_SPLOCK_SYSTATUS,Provides information about the Spinlock module" hexmask.long.byte 0x0 24.--31. 1. "NUM_LOCKS,Module configuration parameter n the total number of spinlocks divided by 32. e.g. For 256 spin locks this will return the number 0x08" bitfld.long 0x0 7. "IN_USE7,In-Use flag 7 covering lock registers 224 - 255. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 224 - 255 are in the Not Taken state Read 1 : At least one of the lock registers 224.." "0: All lock registers 224,1: At least one of the lock registers 224" newline bitfld.long 0x0 6. "IN_USE6,In-Use flag 6 covering lock registers 192 - 223. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 192 - 223 are in the Not Taken state Read 1 : At least one of the lock registers 192.." "0: All lock registers 192,1: At least one of the lock registers 192" bitfld.long 0x0 5. "IN_USE5,In-Use flag 5 covering lock registers 160 - 191. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 160 - 191 are in the Not Taken state Read 1 : At least one of the lock registers 160.." "0: All lock registers 160,1: At least one of the lock registers 160" newline bitfld.long 0x0 4. "IN_USE4,In-Use flag 4 covering lock registers 128 - 159. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 128 - 159 are in the Not Taken state Read 1 : At least one of the lock registers 128.." "0: All lock registers 128,1: At least one of the lock registers 128" bitfld.long 0x0 3. "IN_USE3,In-Use flag 3 covering lock registers 96 - 127. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 96 - 127 are in the Not Taken state Read 1 : At least one of the lock registers 96 -.." "0: All lock registers 96,1: At least one of the lock registers 96" newline bitfld.long 0x0 2. "IN_USE2,In-Use flag 2 covering lock registers 64 - 95. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 64 - 95 are in the Not Taken state Read 1 : At least one of the lock registers 64 - 95.." "0: All lock registers 64,1: At least one of the lock registers 64" bitfld.long 0x0 1. "IN_USE1,In-Use flag 1 covering lock registers 32 - 63. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 32 - 63 are in the Not Taken state Read 1 : At least one of the lock registers 32 - 63.." "0: All lock registers 32,1: At least one of the lock registers 32" newline bitfld.long 0x0 0. "IN_USE0,In-Use flag 0 covering lock registers 0 - 31. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 0 - 31 are in the Not Taken state Read 1 : At least one of the lock registers 0 - 31.." "0: All lock registers 0,1: At least one of the lock registers 0" rgroup.long 0x800++0x3 line.long 0x0 "SPINLOCK0__CFG__REGS_LOCK,The Lock[a] register is read and written to perform lock and unlock operations on lock 'a'" bitfld.long 0x0 0. "TAKEN,Lock Status Read 0 : Lock was previously free. The reader now has been granted the lock. Read 1 : Lock was previously taken. The reader has not been granted the lock and must retry. Write 0 : Free the lock by setting TAKEN to zero. Write 1 : No.." "0: Free the lock by setting TAKEN to zero,1: No effect" tree.end endif tree "NAVSS0_SPINLOCK_0_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SPINLOCK_0_VIRT_ALIAS_0_SPINLOCK0_CFG (NAVSS0_SPINLOCK_0_VIRT_ALIAS_0_SPINLOCK0_CFG)" base ad:0x4B00E00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_SPINLOCK0__CFG__REGS_SPLOCK_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_SPINLOCK0__CFG__REGS_SPLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock" bitfld.long 0x0 1. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0 It has the same effect as the hardware reset Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and free all of the.." "0,1" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_0_SPINLOCK0__CFG__REGS_SPLOCK_SYSTATUS,Provides information about the Spinlock module" hexmask.long.byte 0x0 24.--31. 1. "NUM_LOCKS,Module configuration parameter n the total number of spinlocks divided by 32. e.g. For 256 spin locks this will return the number 0x08" newline bitfld.long 0x0 7. "IN_USE7,In-Use flag 7 covering lock registers 224 - 255. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 224 - 255 are in the Not Taken state Read 1 : At least one of the lock registers 224.." "0: All lock registers 224,1: At least one of the lock registers 224" newline bitfld.long 0x0 6. "IN_USE6,In-Use flag 6 covering lock registers 192 - 223. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 192 - 223 are in the Not Taken state Read 1 : At least one of the lock registers 192.." "0: All lock registers 192,1: At least one of the lock registers 192" newline bitfld.long 0x0 5. "IN_USE5,In-Use flag 5 covering lock registers 160 - 191. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 160 - 191 are in the Not Taken state Read 1 : At least one of the lock registers 160.." "0: All lock registers 160,1: At least one of the lock registers 160" newline bitfld.long 0x0 4. "IN_USE4,In-Use flag 4 covering lock registers 128 - 159. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 128 - 159 are in the Not Taken state Read 1 : At least one of the lock registers 128.." "0: All lock registers 128,1: At least one of the lock registers 128" newline bitfld.long 0x0 3. "IN_USE3,In-Use flag 3 covering lock registers 96 - 127. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 96 - 127 are in the Not Taken state Read 1 : At least one of the lock registers 96 -.." "0: All lock registers 96,1: At least one of the lock registers 96" newline bitfld.long 0x0 2. "IN_USE2,In-Use flag 2 covering lock registers 64 - 95. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 64 - 95 are in the Not Taken state Read 1 : At least one of the lock registers 64 - 95.." "0: All lock registers 64,1: At least one of the lock registers 64" newline bitfld.long 0x0 1. "IN_USE1,In-Use flag 1 covering lock registers 32 - 63. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 32 - 63 are in the Not Taken state Read 1 : At least one of the lock registers 32 - 63.." "0: All lock registers 32,1: At least one of the lock registers 32" newline bitfld.long 0x0 0. "IN_USE0,In-Use flag 0 covering lock registers 0 - 31. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 0 - 31 are in the Not Taken state Read 1 : At least one of the lock registers 0 - 31.." "0: All lock registers 0,1: At least one of the lock registers 0" rgroup.long 0x800++0x3 line.long 0x0 "VIRT_ALIAS_0_SPINLOCK0__CFG__REGS_LOCK,The Lock[a] register is read and written to perform lock and unlock operations on lock 'a'" bitfld.long 0x0 0. "TAKEN,Lock Status Read 0 : Lock was previously free. The reader now has been granted the lock. Read 1 : Lock was previously taken. The reader has not been granted the lock and must retry. Write 0 : Free the lock by setting TAKEN to zero. Write 1 : No.." "0: Free the lock by setting TAKEN to zero,1: No effect" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SPINLOCK_0_VIRT_ALIAS_1_SPINLOCK0_CFG (NAVSS0_SPINLOCK_0_VIRT_ALIAS_1_SPINLOCK0_CFG)" base ad:0x4B10E00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_SPINLOCK0__CFG__REGS_SPLOCK_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_SPINLOCK0__CFG__REGS_SPLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock" bitfld.long 0x0 1. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0 It has the same effect as the hardware reset Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and free all of the.." "0,1" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_1_SPINLOCK0__CFG__REGS_SPLOCK_SYSTATUS,Provides information about the Spinlock module" hexmask.long.byte 0x0 24.--31. 1. "NUM_LOCKS,Module configuration parameter n the total number of spinlocks divided by 32. e.g. For 256 spin locks this will return the number 0x08" newline bitfld.long 0x0 7. "IN_USE7,In-Use flag 7 covering lock registers 224 - 255. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 224 - 255 are in the Not Taken state Read 1 : At least one of the lock registers 224.." "0: All lock registers 224,1: At least one of the lock registers 224" newline bitfld.long 0x0 6. "IN_USE6,In-Use flag 6 covering lock registers 192 - 223. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 192 - 223 are in the Not Taken state Read 1 : At least one of the lock registers 192.." "0: All lock registers 192,1: At least one of the lock registers 192" newline bitfld.long 0x0 5. "IN_USE5,In-Use flag 5 covering lock registers 160 - 191. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 160 - 191 are in the Not Taken state Read 1 : At least one of the lock registers 160.." "0: All lock registers 160,1: At least one of the lock registers 160" newline bitfld.long 0x0 4. "IN_USE4,In-Use flag 4 covering lock registers 128 - 159. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 128 - 159 are in the Not Taken state Read 1 : At least one of the lock registers 128.." "0: All lock registers 128,1: At least one of the lock registers 128" newline bitfld.long 0x0 3. "IN_USE3,In-Use flag 3 covering lock registers 96 - 127. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 96 - 127 are in the Not Taken state Read 1 : At least one of the lock registers 96 -.." "0: All lock registers 96,1: At least one of the lock registers 96" newline bitfld.long 0x0 2. "IN_USE2,In-Use flag 2 covering lock registers 64 - 95. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 64 - 95 are in the Not Taken state Read 1 : At least one of the lock registers 64 - 95.." "0: All lock registers 64,1: At least one of the lock registers 64" newline bitfld.long 0x0 1. "IN_USE1,In-Use flag 1 covering lock registers 32 - 63. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 32 - 63 are in the Not Taken state Read 1 : At least one of the lock registers 32 - 63.." "0: All lock registers 32,1: At least one of the lock registers 32" newline bitfld.long 0x0 0. "IN_USE0,In-Use flag 0 covering lock registers 0 - 31. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 0 - 31 are in the Not Taken state Read 1 : At least one of the lock registers 0 - 31.." "0: All lock registers 0,1: At least one of the lock registers 0" rgroup.long 0x800++0x3 line.long 0x0 "VIRT_ALIAS_1_SPINLOCK0__CFG__REGS_LOCK,The Lock[a] register is read and written to perform lock and unlock operations on lock 'a'" bitfld.long 0x0 0. "TAKEN,Lock Status Read 0 : Lock was previously free. The reader now has been granted the lock. Read 1 : Lock was previously taken. The reader has not been granted the lock and must retry. Write 0 : Free the lock by setting TAKEN to zero. Write 1 : No.." "0: Free the lock by setting TAKEN to zero,1: No effect" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SPINLOCK_0_VIRT_ALIAS_2_SPINLOCK0_CFG (NAVSS0_SPINLOCK_0_VIRT_ALIAS_2_SPINLOCK0_CFG)" base ad:0x4B20E00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_SPINLOCK0__CFG__REGS_SPLOCK_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_SPINLOCK0__CFG__REGS_SPLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock" bitfld.long 0x0 1. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0 It has the same effect as the hardware reset Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and free all of the.." "0,1" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_2_SPINLOCK0__CFG__REGS_SPLOCK_SYSTATUS,Provides information about the Spinlock module" hexmask.long.byte 0x0 24.--31. 1. "NUM_LOCKS,Module configuration parameter n the total number of spinlocks divided by 32. e.g. For 256 spin locks this will return the number 0x08" newline bitfld.long 0x0 7. "IN_USE7,In-Use flag 7 covering lock registers 224 - 255. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 224 - 255 are in the Not Taken state Read 1 : At least one of the lock registers 224.." "0: All lock registers 224,1: At least one of the lock registers 224" newline bitfld.long 0x0 6. "IN_USE6,In-Use flag 6 covering lock registers 192 - 223. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 192 - 223 are in the Not Taken state Read 1 : At least one of the lock registers 192.." "0: All lock registers 192,1: At least one of the lock registers 192" newline bitfld.long 0x0 5. "IN_USE5,In-Use flag 5 covering lock registers 160 - 191. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 160 - 191 are in the Not Taken state Read 1 : At least one of the lock registers 160.." "0: All lock registers 160,1: At least one of the lock registers 160" newline bitfld.long 0x0 4. "IN_USE4,In-Use flag 4 covering lock registers 128 - 159. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 128 - 159 are in the Not Taken state Read 1 : At least one of the lock registers 128.." "0: All lock registers 128,1: At least one of the lock registers 128" newline bitfld.long 0x0 3. "IN_USE3,In-Use flag 3 covering lock registers 96 - 127. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 96 - 127 are in the Not Taken state Read 1 : At least one of the lock registers 96 -.." "0: All lock registers 96,1: At least one of the lock registers 96" newline bitfld.long 0x0 2. "IN_USE2,In-Use flag 2 covering lock registers 64 - 95. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 64 - 95 are in the Not Taken state Read 1 : At least one of the lock registers 64 - 95.." "0: All lock registers 64,1: At least one of the lock registers 64" newline bitfld.long 0x0 1. "IN_USE1,In-Use flag 1 covering lock registers 32 - 63. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 32 - 63 are in the Not Taken state Read 1 : At least one of the lock registers 32 - 63.." "0: All lock registers 32,1: At least one of the lock registers 32" newline bitfld.long 0x0 0. "IN_USE0,In-Use flag 0 covering lock registers 0 - 31. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 0 - 31 are in the Not Taken state Read 1 : At least one of the lock registers 0 - 31.." "0: All lock registers 0,1: At least one of the lock registers 0" rgroup.long 0x800++0x3 line.long 0x0 "VIRT_ALIAS_2_SPINLOCK0__CFG__REGS_LOCK,The Lock[a] register is read and written to perform lock and unlock operations on lock 'a'" bitfld.long 0x0 0. "TAKEN,Lock Status Read 0 : Lock was previously free. The reader now has been granted the lock. Read 1 : Lock was previously taken. The reader has not been granted the lock and must retry. Write 0 : Free the lock by setting TAKEN to zero. Write 1 : No.." "0: Free the lock by setting TAKEN to zero,1: No effect" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SPINLOCK_0_VIRT_ALIAS_3_SPINLOCK0_CFG (NAVSS0_SPINLOCK_0_VIRT_ALIAS_3_SPINLOCK0_CFG)" base ad:0x4B30E00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_SPINLOCK0__CFG__REGS_SPLOCK_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_SPINLOCK0__CFG__REGS_SPLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock" bitfld.long 0x0 1. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0 It has the same effect as the hardware reset Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and free all of the.." "0,1" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_3_SPINLOCK0__CFG__REGS_SPLOCK_SYSTATUS,Provides information about the Spinlock module" hexmask.long.byte 0x0 24.--31. 1. "NUM_LOCKS,Module configuration parameter n the total number of spinlocks divided by 32. e.g. For 256 spin locks this will return the number 0x08" newline bitfld.long 0x0 7. "IN_USE7,In-Use flag 7 covering lock registers 224 - 255. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 224 - 255 are in the Not Taken state Read 1 : At least one of the lock registers 224.." "0: All lock registers 224,1: At least one of the lock registers 224" newline bitfld.long 0x0 6. "IN_USE6,In-Use flag 6 covering lock registers 192 - 223. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 192 - 223 are in the Not Taken state Read 1 : At least one of the lock registers 192.." "0: All lock registers 192,1: At least one of the lock registers 192" newline bitfld.long 0x0 5. "IN_USE5,In-Use flag 5 covering lock registers 160 - 191. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 160 - 191 are in the Not Taken state Read 1 : At least one of the lock registers 160.." "0: All lock registers 160,1: At least one of the lock registers 160" newline bitfld.long 0x0 4. "IN_USE4,In-Use flag 4 covering lock registers 128 - 159. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 128 - 159 are in the Not Taken state Read 1 : At least one of the lock registers 128.." "0: All lock registers 128,1: At least one of the lock registers 128" newline bitfld.long 0x0 3. "IN_USE3,In-Use flag 3 covering lock registers 96 - 127. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 96 - 127 are in the Not Taken state Read 1 : At least one of the lock registers 96 -.." "0: All lock registers 96,1: At least one of the lock registers 96" newline bitfld.long 0x0 2. "IN_USE2,In-Use flag 2 covering lock registers 64 - 95. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 64 - 95 are in the Not Taken state Read 1 : At least one of the lock registers 64 - 95.." "0: All lock registers 64,1: At least one of the lock registers 64" newline bitfld.long 0x0 1. "IN_USE1,In-Use flag 1 covering lock registers 32 - 63. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 32 - 63 are in the Not Taken state Read 1 : At least one of the lock registers 32 - 63.." "0: All lock registers 32,1: At least one of the lock registers 32" newline bitfld.long 0x0 0. "IN_USE0,In-Use flag 0 covering lock registers 0 - 31. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 0 - 31 are in the Not Taken state Read 1 : At least one of the lock registers 0 - 31.." "0: All lock registers 0,1: At least one of the lock registers 0" rgroup.long 0x800++0x3 line.long 0x0 "VIRT_ALIAS_3_SPINLOCK0__CFG__REGS_LOCK,The Lock[a] register is read and written to perform lock and unlock operations on lock 'a'" bitfld.long 0x0 0. "TAKEN,Lock Status Read 0 : Lock was previously free. The reader now has been granted the lock. Read 1 : Lock was previously taken. The reader has not been granted the lock and must retry. Write 0 : Free the lock by setting TAKEN to zero. Write 1 : No.." "0: Free the lock by setting TAKEN to zero,1: No effect" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SPINLOCK_0_VIRT_ALIAS_4_SPINLOCK0_CFG (NAVSS0_SPINLOCK_0_VIRT_ALIAS_4_SPINLOCK0_CFG)" base ad:0x4B40E00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_SPINLOCK0__CFG__REGS_SPLOCK_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_SPINLOCK0__CFG__REGS_SPLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock" bitfld.long 0x0 1. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0 It has the same effect as the hardware reset Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and free all of the.." "0,1" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_4_SPINLOCK0__CFG__REGS_SPLOCK_SYSTATUS,Provides information about the Spinlock module" hexmask.long.byte 0x0 24.--31. 1. "NUM_LOCKS,Module configuration parameter n the total number of spinlocks divided by 32. e.g. For 256 spin locks this will return the number 0x08" newline bitfld.long 0x0 7. "IN_USE7,In-Use flag 7 covering lock registers 224 - 255. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 224 - 255 are in the Not Taken state Read 1 : At least one of the lock registers 224.." "0: All lock registers 224,1: At least one of the lock registers 224" newline bitfld.long 0x0 6. "IN_USE6,In-Use flag 6 covering lock registers 192 - 223. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 192 - 223 are in the Not Taken state Read 1 : At least one of the lock registers 192.." "0: All lock registers 192,1: At least one of the lock registers 192" newline bitfld.long 0x0 5. "IN_USE5,In-Use flag 5 covering lock registers 160 - 191. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 160 - 191 are in the Not Taken state Read 1 : At least one of the lock registers 160.." "0: All lock registers 160,1: At least one of the lock registers 160" newline bitfld.long 0x0 4. "IN_USE4,In-Use flag 4 covering lock registers 128 - 159. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 128 - 159 are in the Not Taken state Read 1 : At least one of the lock registers 128.." "0: All lock registers 128,1: At least one of the lock registers 128" newline bitfld.long 0x0 3. "IN_USE3,In-Use flag 3 covering lock registers 96 - 127. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 96 - 127 are in the Not Taken state Read 1 : At least one of the lock registers 96 -.." "0: All lock registers 96,1: At least one of the lock registers 96" newline bitfld.long 0x0 2. "IN_USE2,In-Use flag 2 covering lock registers 64 - 95. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 64 - 95 are in the Not Taken state Read 1 : At least one of the lock registers 64 - 95.." "0: All lock registers 64,1: At least one of the lock registers 64" newline bitfld.long 0x0 1. "IN_USE1,In-Use flag 1 covering lock registers 32 - 63. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 32 - 63 are in the Not Taken state Read 1 : At least one of the lock registers 32 - 63.." "0: All lock registers 32,1: At least one of the lock registers 32" newline bitfld.long 0x0 0. "IN_USE0,In-Use flag 0 covering lock registers 0 - 31. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 0 - 31 are in the Not Taken state Read 1 : At least one of the lock registers 0 - 31.." "0: All lock registers 0,1: At least one of the lock registers 0" rgroup.long 0x800++0x3 line.long 0x0 "VIRT_ALIAS_4_SPINLOCK0__CFG__REGS_LOCK,The Lock[a] register is read and written to perform lock and unlock operations on lock 'a'" bitfld.long 0x0 0. "TAKEN,Lock Status Read 0 : Lock was previously free. The reader now has been granted the lock. Read 1 : Lock was previously taken. The reader has not been granted the lock and must retry. Write 0 : Free the lock by setting TAKEN to zero. Write 1 : No.." "0: Free the lock by setting TAKEN to zero,1: No effect" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SPINLOCK_0_VIRT_ALIAS_5_SPINLOCK0_CFG (NAVSS0_SPINLOCK_0_VIRT_ALIAS_5_SPINLOCK0_CFG)" base ad:0x4B50E00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_SPINLOCK0__CFG__REGS_SPLOCK_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_SPINLOCK0__CFG__REGS_SPLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock" bitfld.long 0x0 1. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0 It has the same effect as the hardware reset Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and free all of the.." "0,1" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_5_SPINLOCK0__CFG__REGS_SPLOCK_SYSTATUS,Provides information about the Spinlock module" hexmask.long.byte 0x0 24.--31. 1. "NUM_LOCKS,Module configuration parameter n the total number of spinlocks divided by 32. e.g. For 256 spin locks this will return the number 0x08" newline bitfld.long 0x0 7. "IN_USE7,In-Use flag 7 covering lock registers 224 - 255. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 224 - 255 are in the Not Taken state Read 1 : At least one of the lock registers 224.." "0: All lock registers 224,1: At least one of the lock registers 224" newline bitfld.long 0x0 6. "IN_USE6,In-Use flag 6 covering lock registers 192 - 223. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 192 - 223 are in the Not Taken state Read 1 : At least one of the lock registers 192.." "0: All lock registers 192,1: At least one of the lock registers 192" newline bitfld.long 0x0 5. "IN_USE5,In-Use flag 5 covering lock registers 160 - 191. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 160 - 191 are in the Not Taken state Read 1 : At least one of the lock registers 160.." "0: All lock registers 160,1: At least one of the lock registers 160" newline bitfld.long 0x0 4. "IN_USE4,In-Use flag 4 covering lock registers 128 - 159. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 128 - 159 are in the Not Taken state Read 1 : At least one of the lock registers 128.." "0: All lock registers 128,1: At least one of the lock registers 128" newline bitfld.long 0x0 3. "IN_USE3,In-Use flag 3 covering lock registers 96 - 127. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 96 - 127 are in the Not Taken state Read 1 : At least one of the lock registers 96 -.." "0: All lock registers 96,1: At least one of the lock registers 96" newline bitfld.long 0x0 2. "IN_USE2,In-Use flag 2 covering lock registers 64 - 95. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 64 - 95 are in the Not Taken state Read 1 : At least one of the lock registers 64 - 95.." "0: All lock registers 64,1: At least one of the lock registers 64" newline bitfld.long 0x0 1. "IN_USE1,In-Use flag 1 covering lock registers 32 - 63. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 32 - 63 are in the Not Taken state Read 1 : At least one of the lock registers 32 - 63.." "0: All lock registers 32,1: At least one of the lock registers 32" newline bitfld.long 0x0 0. "IN_USE0,In-Use flag 0 covering lock registers 0 - 31. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 0 - 31 are in the Not Taken state Read 1 : At least one of the lock registers 0 - 31.." "0: All lock registers 0,1: At least one of the lock registers 0" rgroup.long 0x800++0x3 line.long 0x0 "VIRT_ALIAS_5_SPINLOCK0__CFG__REGS_LOCK,The Lock[a] register is read and written to perform lock and unlock operations on lock 'a'" bitfld.long 0x0 0. "TAKEN,Lock Status Read 0 : Lock was previously free. The reader now has been granted the lock. Read 1 : Lock was previously taken. The reader has not been granted the lock and must retry. Write 0 : Free the lock by setting TAKEN to zero. Write 1 : No.." "0: Free the lock by setting TAKEN to zero,1: No effect" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SPINLOCK_0_VIRT_ALIAS_6_SPINLOCK0_CFG (NAVSS0_SPINLOCK_0_VIRT_ALIAS_6_SPINLOCK0_CFG)" base ad:0x4B60E00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_SPINLOCK0__CFG__REGS_SPLOCK_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_SPINLOCK0__CFG__REGS_SPLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock" bitfld.long 0x0 1. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0 It has the same effect as the hardware reset Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and free all of the.." "0,1" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_6_SPINLOCK0__CFG__REGS_SPLOCK_SYSTATUS,Provides information about the Spinlock module" hexmask.long.byte 0x0 24.--31. 1. "NUM_LOCKS,Module configuration parameter n the total number of spinlocks divided by 32. e.g. For 256 spin locks this will return the number 0x08" newline bitfld.long 0x0 7. "IN_USE7,In-Use flag 7 covering lock registers 224 - 255. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 224 - 255 are in the Not Taken state Read 1 : At least one of the lock registers 224.." "0: All lock registers 224,1: At least one of the lock registers 224" newline bitfld.long 0x0 6. "IN_USE6,In-Use flag 6 covering lock registers 192 - 223. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 192 - 223 are in the Not Taken state Read 1 : At least one of the lock registers 192.." "0: All lock registers 192,1: At least one of the lock registers 192" newline bitfld.long 0x0 5. "IN_USE5,In-Use flag 5 covering lock registers 160 - 191. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 160 - 191 are in the Not Taken state Read 1 : At least one of the lock registers 160.." "0: All lock registers 160,1: At least one of the lock registers 160" newline bitfld.long 0x0 4. "IN_USE4,In-Use flag 4 covering lock registers 128 - 159. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 128 - 159 are in the Not Taken state Read 1 : At least one of the lock registers 128.." "0: All lock registers 128,1: At least one of the lock registers 128" newline bitfld.long 0x0 3. "IN_USE3,In-Use flag 3 covering lock registers 96 - 127. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 96 - 127 are in the Not Taken state Read 1 : At least one of the lock registers 96 -.." "0: All lock registers 96,1: At least one of the lock registers 96" newline bitfld.long 0x0 2. "IN_USE2,In-Use flag 2 covering lock registers 64 - 95. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 64 - 95 are in the Not Taken state Read 1 : At least one of the lock registers 64 - 95.." "0: All lock registers 64,1: At least one of the lock registers 64" newline bitfld.long 0x0 1. "IN_USE1,In-Use flag 1 covering lock registers 32 - 63. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 32 - 63 are in the Not Taken state Read 1 : At least one of the lock registers 32 - 63.." "0: All lock registers 32,1: At least one of the lock registers 32" newline bitfld.long 0x0 0. "IN_USE0,In-Use flag 0 covering lock registers 0 - 31. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 0 - 31 are in the Not Taken state Read 1 : At least one of the lock registers 0 - 31.." "0: All lock registers 0,1: At least one of the lock registers 0" rgroup.long 0x800++0x3 line.long 0x0 "VIRT_ALIAS_6_SPINLOCK0__CFG__REGS_LOCK,The Lock[a] register is read and written to perform lock and unlock operations on lock 'a'" bitfld.long 0x0 0. "TAKEN,Lock Status Read 0 : Lock was previously free. The reader now has been granted the lock. Read 1 : Lock was previously taken. The reader has not been granted the lock and must retry. Write 0 : Free the lock by setting TAKEN to zero. Write 1 : No.." "0: Free the lock by setting TAKEN to zero,1: No effect" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SPINLOCK_0_VIRT_ALIAS_7_SPINLOCK0_CFG (NAVSS0_SPINLOCK_0_VIRT_ALIAS_7_SPINLOCK0_CFG)" base ad:0x4B70E00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_SPINLOCK0__CFG__REGS_SPLOCK_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_SPINLOCK0__CFG__REGS_SPLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock" bitfld.long 0x0 1. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0 It has the same effect as the hardware reset Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and free all of the.." "0,1" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_7_SPINLOCK0__CFG__REGS_SPLOCK_SYSTATUS,Provides information about the Spinlock module" hexmask.long.byte 0x0 24.--31. 1. "NUM_LOCKS,Module configuration parameter n the total number of spinlocks divided by 32. e.g. For 256 spin locks this will return the number 0x08" newline bitfld.long 0x0 7. "IN_USE7,In-Use flag 7 covering lock registers 224 - 255. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 224 - 255 are in the Not Taken state Read 1 : At least one of the lock registers 224.." "0: All lock registers 224,1: At least one of the lock registers 224" newline bitfld.long 0x0 6. "IN_USE6,In-Use flag 6 covering lock registers 192 - 223. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 192 - 223 are in the Not Taken state Read 1 : At least one of the lock registers 192.." "0: All lock registers 192,1: At least one of the lock registers 192" newline bitfld.long 0x0 5. "IN_USE5,In-Use flag 5 covering lock registers 160 - 191. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 160 - 191 are in the Not Taken state Read 1 : At least one of the lock registers 160.." "0: All lock registers 160,1: At least one of the lock registers 160" newline bitfld.long 0x0 4. "IN_USE4,In-Use flag 4 covering lock registers 128 - 159. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 128 - 159 are in the Not Taken state Read 1 : At least one of the lock registers 128.." "0: All lock registers 128,1: At least one of the lock registers 128" newline bitfld.long 0x0 3. "IN_USE3,In-Use flag 3 covering lock registers 96 - 127. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 96 - 127 are in the Not Taken state Read 1 : At least one of the lock registers 96 -.." "0: All lock registers 96,1: At least one of the lock registers 96" newline bitfld.long 0x0 2. "IN_USE2,In-Use flag 2 covering lock registers 64 - 95. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 64 - 95 are in the Not Taken state Read 1 : At least one of the lock registers 64 - 95.." "0: All lock registers 64,1: At least one of the lock registers 64" newline bitfld.long 0x0 1. "IN_USE1,In-Use flag 1 covering lock registers 32 - 63. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 32 - 63 are in the Not Taken state Read 1 : At least one of the lock registers 32 - 63.." "0: All lock registers 32,1: At least one of the lock registers 32" newline bitfld.long 0x0 0. "IN_USE0,In-Use flag 0 covering lock registers 0 - 31. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 0 - 31 are in the Not Taken state Read 1 : At least one of the lock registers 0 - 31.." "0: All lock registers 0,1: At least one of the lock registers 0" rgroup.long 0x800++0x3 line.long 0x0 "VIRT_ALIAS_7_SPINLOCK0__CFG__REGS_LOCK,The Lock[a] register is read and written to perform lock and unlock operations on lock 'a'" bitfld.long 0x0 0. "TAKEN,Lock Status Read 0 : Lock was previously free. The reader now has been granted the lock. Read 1 : Lock was previously taken. The reader has not been granted the lock and must retry. Write 0 : Free the lock by setting TAKEN to zero. Write 1 : No.." "0: Free the lock by setting TAKEN to zero,1: No effect" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SPINLOCK_0_VIRT_ALIAS_8_SPINLOCK0_CFG (NAVSS0_SPINLOCK_0_VIRT_ALIAS_8_SPINLOCK0_CFG)" base ad:0x4B80E00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_SPINLOCK0__CFG__REGS_SPLOCK_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_SPINLOCK0__CFG__REGS_SPLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock" bitfld.long 0x0 1. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0 It has the same effect as the hardware reset Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and free all of the.." "0,1" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_8_SPINLOCK0__CFG__REGS_SPLOCK_SYSTATUS,Provides information about the Spinlock module" hexmask.long.byte 0x0 24.--31. 1. "NUM_LOCKS,Module configuration parameter n the total number of spinlocks divided by 32. e.g. For 256 spin locks this will return the number 0x08" newline bitfld.long 0x0 7. "IN_USE7,In-Use flag 7 covering lock registers 224 - 255. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 224 - 255 are in the Not Taken state Read 1 : At least one of the lock registers 224.." "0: All lock registers 224,1: At least one of the lock registers 224" newline bitfld.long 0x0 6. "IN_USE6,In-Use flag 6 covering lock registers 192 - 223. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 192 - 223 are in the Not Taken state Read 1 : At least one of the lock registers 192.." "0: All lock registers 192,1: At least one of the lock registers 192" newline bitfld.long 0x0 5. "IN_USE5,In-Use flag 5 covering lock registers 160 - 191. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 160 - 191 are in the Not Taken state Read 1 : At least one of the lock registers 160.." "0: All lock registers 160,1: At least one of the lock registers 160" newline bitfld.long 0x0 4. "IN_USE4,In-Use flag 4 covering lock registers 128 - 159. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 128 - 159 are in the Not Taken state Read 1 : At least one of the lock registers 128.." "0: All lock registers 128,1: At least one of the lock registers 128" newline bitfld.long 0x0 3. "IN_USE3,In-Use flag 3 covering lock registers 96 - 127. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 96 - 127 are in the Not Taken state Read 1 : At least one of the lock registers 96 -.." "0: All lock registers 96,1: At least one of the lock registers 96" newline bitfld.long 0x0 2. "IN_USE2,In-Use flag 2 covering lock registers 64 - 95. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 64 - 95 are in the Not Taken state Read 1 : At least one of the lock registers 64 - 95.." "0: All lock registers 64,1: At least one of the lock registers 64" newline bitfld.long 0x0 1. "IN_USE1,In-Use flag 1 covering lock registers 32 - 63. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 32 - 63 are in the Not Taken state Read 1 : At least one of the lock registers 32 - 63.." "0: All lock registers 32,1: At least one of the lock registers 32" newline bitfld.long 0x0 0. "IN_USE0,In-Use flag 0 covering lock registers 0 - 31. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 0 - 31 are in the Not Taken state Read 1 : At least one of the lock registers 0 - 31.." "0: All lock registers 0,1: At least one of the lock registers 0" rgroup.long 0x800++0x3 line.long 0x0 "VIRT_ALIAS_8_SPINLOCK0__CFG__REGS_LOCK,The Lock[a] register is read and written to perform lock and unlock operations on lock 'a'" bitfld.long 0x0 0. "TAKEN,Lock Status Read 0 : Lock was previously free. The reader now has been granted the lock. Read 1 : Lock was previously taken. The reader has not been granted the lock and must retry. Write 0 : Free the lock by setting TAKEN to zero. Write 1 : No.." "0: Free the lock by setting TAKEN to zero,1: No effect" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SPINLOCK_0_VIRT_ALIAS_9_SPINLOCK0_CFG (NAVSS0_SPINLOCK_0_VIRT_ALIAS_9_SPINLOCK0_CFG)" base ad:0x4B90E00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_SPINLOCK0__CFG__REGS_SPLOCK_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_SPINLOCK0__CFG__REGS_SPLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock" bitfld.long 0x0 1. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0 It has the same effect as the hardware reset Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and free all of the.." "0,1" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_9_SPINLOCK0__CFG__REGS_SPLOCK_SYSTATUS,Provides information about the Spinlock module" hexmask.long.byte 0x0 24.--31. 1. "NUM_LOCKS,Module configuration parameter n the total number of spinlocks divided by 32. e.g. For 256 spin locks this will return the number 0x08" newline bitfld.long 0x0 7. "IN_USE7,In-Use flag 7 covering lock registers 224 - 255. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 224 - 255 are in the Not Taken state Read 1 : At least one of the lock registers 224.." "0: All lock registers 224,1: At least one of the lock registers 224" newline bitfld.long 0x0 6. "IN_USE6,In-Use flag 6 covering lock registers 192 - 223. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 192 - 223 are in the Not Taken state Read 1 : At least one of the lock registers 192.." "0: All lock registers 192,1: At least one of the lock registers 192" newline bitfld.long 0x0 5. "IN_USE5,In-Use flag 5 covering lock registers 160 - 191. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 160 - 191 are in the Not Taken state Read 1 : At least one of the lock registers 160.." "0: All lock registers 160,1: At least one of the lock registers 160" newline bitfld.long 0x0 4. "IN_USE4,In-Use flag 4 covering lock registers 128 - 159. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 128 - 159 are in the Not Taken state Read 1 : At least one of the lock registers 128.." "0: All lock registers 128,1: At least one of the lock registers 128" newline bitfld.long 0x0 3. "IN_USE3,In-Use flag 3 covering lock registers 96 - 127. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 96 - 127 are in the Not Taken state Read 1 : At least one of the lock registers 96 -.." "0: All lock registers 96,1: At least one of the lock registers 96" newline bitfld.long 0x0 2. "IN_USE2,In-Use flag 2 covering lock registers 64 - 95. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 64 - 95 are in the Not Taken state Read 1 : At least one of the lock registers 64 - 95.." "0: All lock registers 64,1: At least one of the lock registers 64" newline bitfld.long 0x0 1. "IN_USE1,In-Use flag 1 covering lock registers 32 - 63. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 32 - 63 are in the Not Taken state Read 1 : At least one of the lock registers 32 - 63.." "0: All lock registers 32,1: At least one of the lock registers 32" newline bitfld.long 0x0 0. "IN_USE0,In-Use flag 0 covering lock registers 0 - 31. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 0 - 31 are in the Not Taken state Read 1 : At least one of the lock registers 0 - 31.." "0: All lock registers 0,1: At least one of the lock registers 0" rgroup.long 0x800++0x3 line.long 0x0 "VIRT_ALIAS_9_SPINLOCK0__CFG__REGS_LOCK,The Lock[a] register is read and written to perform lock and unlock operations on lock 'a'" bitfld.long 0x0 0. "TAKEN,Lock Status Read 0 : Lock was previously free. The reader now has been granted the lock. Read 1 : Lock was previously taken. The reader has not been granted the lock and must retry. Write 0 : Free the lock by setting TAKEN to zero. Write 1 : No.." "0: Free the lock by setting TAKEN to zero,1: No effect" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SPINLOCK_0_VIRT_ALIAS_10_SPINLOCK0_CFG (NAVSS0_SPINLOCK_0_VIRT_ALIAS_10_SPINLOCK0_CFG)" base ad:0x4BA0E00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_SPINLOCK0__CFG__REGS_SPLOCK_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_SPINLOCK0__CFG__REGS_SPLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock" bitfld.long 0x0 1. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0 It has the same effect as the hardware reset Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and free all of the.." "0,1" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_10_SPINLOCK0__CFG__REGS_SPLOCK_SYSTATUS,Provides information about the Spinlock module" hexmask.long.byte 0x0 24.--31. 1. "NUM_LOCKS,Module configuration parameter n the total number of spinlocks divided by 32. e.g. For 256 spin locks this will return the number 0x08" newline bitfld.long 0x0 7. "IN_USE7,In-Use flag 7 covering lock registers 224 - 255. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 224 - 255 are in the Not Taken state Read 1 : At least one of the lock registers 224.." "0: All lock registers 224,1: At least one of the lock registers 224" newline bitfld.long 0x0 6. "IN_USE6,In-Use flag 6 covering lock registers 192 - 223. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 192 - 223 are in the Not Taken state Read 1 : At least one of the lock registers 192.." "0: All lock registers 192,1: At least one of the lock registers 192" newline bitfld.long 0x0 5. "IN_USE5,In-Use flag 5 covering lock registers 160 - 191. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 160 - 191 are in the Not Taken state Read 1 : At least one of the lock registers 160.." "0: All lock registers 160,1: At least one of the lock registers 160" newline bitfld.long 0x0 4. "IN_USE4,In-Use flag 4 covering lock registers 128 - 159. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 128 - 159 are in the Not Taken state Read 1 : At least one of the lock registers 128.." "0: All lock registers 128,1: At least one of the lock registers 128" newline bitfld.long 0x0 3. "IN_USE3,In-Use flag 3 covering lock registers 96 - 127. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 96 - 127 are in the Not Taken state Read 1 : At least one of the lock registers 96 -.." "0: All lock registers 96,1: At least one of the lock registers 96" newline bitfld.long 0x0 2. "IN_USE2,In-Use flag 2 covering lock registers 64 - 95. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 64 - 95 are in the Not Taken state Read 1 : At least one of the lock registers 64 - 95.." "0: All lock registers 64,1: At least one of the lock registers 64" newline bitfld.long 0x0 1. "IN_USE1,In-Use flag 1 covering lock registers 32 - 63. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 32 - 63 are in the Not Taken state Read 1 : At least one of the lock registers 32 - 63.." "0: All lock registers 32,1: At least one of the lock registers 32" newline bitfld.long 0x0 0. "IN_USE0,In-Use flag 0 covering lock registers 0 - 31. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 0 - 31 are in the Not Taken state Read 1 : At least one of the lock registers 0 - 31.." "0: All lock registers 0,1: At least one of the lock registers 0" rgroup.long 0x800++0x3 line.long 0x0 "VIRT_ALIAS_10_SPINLOCK0__CFG__REGS_LOCK,The Lock[a] register is read and written to perform lock and unlock operations on lock 'a'" bitfld.long 0x0 0. "TAKEN,Lock Status Read 0 : Lock was previously free. The reader now has been granted the lock. Read 1 : Lock was previously taken. The reader has not been granted the lock and must retry. Write 0 : Free the lock by setting TAKEN to zero. Write 1 : No.." "0: Free the lock by setting TAKEN to zero,1: No effect" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SPINLOCK_0_VIRT_ALIAS_11_SPINLOCK0_CFG (NAVSS0_SPINLOCK_0_VIRT_ALIAS_11_SPINLOCK0_CFG)" base ad:0x4BB0E00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_SPINLOCK0__CFG__REGS_SPLOCK_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_SPINLOCK0__CFG__REGS_SPLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock" bitfld.long 0x0 1. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0 It has the same effect as the hardware reset Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and free all of the.." "0,1" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_11_SPINLOCK0__CFG__REGS_SPLOCK_SYSTATUS,Provides information about the Spinlock module" hexmask.long.byte 0x0 24.--31. 1. "NUM_LOCKS,Module configuration parameter n the total number of spinlocks divided by 32. e.g. For 256 spin locks this will return the number 0x08" newline bitfld.long 0x0 7. "IN_USE7,In-Use flag 7 covering lock registers 224 - 255. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 224 - 255 are in the Not Taken state Read 1 : At least one of the lock registers 224.." "0: All lock registers 224,1: At least one of the lock registers 224" newline bitfld.long 0x0 6. "IN_USE6,In-Use flag 6 covering lock registers 192 - 223. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 192 - 223 are in the Not Taken state Read 1 : At least one of the lock registers 192.." "0: All lock registers 192,1: At least one of the lock registers 192" newline bitfld.long 0x0 5. "IN_USE5,In-Use flag 5 covering lock registers 160 - 191. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 160 - 191 are in the Not Taken state Read 1 : At least one of the lock registers 160.." "0: All lock registers 160,1: At least one of the lock registers 160" newline bitfld.long 0x0 4. "IN_USE4,In-Use flag 4 covering lock registers 128 - 159. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 128 - 159 are in the Not Taken state Read 1 : At least one of the lock registers 128.." "0: All lock registers 128,1: At least one of the lock registers 128" newline bitfld.long 0x0 3. "IN_USE3,In-Use flag 3 covering lock registers 96 - 127. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 96 - 127 are in the Not Taken state Read 1 : At least one of the lock registers 96 -.." "0: All lock registers 96,1: At least one of the lock registers 96" newline bitfld.long 0x0 2. "IN_USE2,In-Use flag 2 covering lock registers 64 - 95. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 64 - 95 are in the Not Taken state Read 1 : At least one of the lock registers 64 - 95.." "0: All lock registers 64,1: At least one of the lock registers 64" newline bitfld.long 0x0 1. "IN_USE1,In-Use flag 1 covering lock registers 32 - 63. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 32 - 63 are in the Not Taken state Read 1 : At least one of the lock registers 32 - 63.." "0: All lock registers 32,1: At least one of the lock registers 32" newline bitfld.long 0x0 0. "IN_USE0,In-Use flag 0 covering lock registers 0 - 31. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 0 - 31 are in the Not Taken state Read 1 : At least one of the lock registers 0 - 31.." "0: All lock registers 0,1: At least one of the lock registers 0" rgroup.long 0x800++0x3 line.long 0x0 "VIRT_ALIAS_11_SPINLOCK0__CFG__REGS_LOCK,The Lock[a] register is read and written to perform lock and unlock operations on lock 'a'" bitfld.long 0x0 0. "TAKEN,Lock Status Read 0 : Lock was previously free. The reader now has been granted the lock. Read 1 : Lock was previously taken. The reader has not been granted the lock and must retry. Write 0 : Free the lock by setting TAKEN to zero. Write 1 : No.." "0: Free the lock by setting TAKEN to zero,1: No effect" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SPINLOCK_0_VIRT_ALIAS_12_SPINLOCK0_CFG (NAVSS0_SPINLOCK_0_VIRT_ALIAS_12_SPINLOCK0_CFG)" base ad:0x4BC0E00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_SPINLOCK0__CFG__REGS_SPLOCK_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_SPINLOCK0__CFG__REGS_SPLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock" bitfld.long 0x0 1. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0 It has the same effect as the hardware reset Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and free all of the.." "0,1" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_12_SPINLOCK0__CFG__REGS_SPLOCK_SYSTATUS,Provides information about the Spinlock module" hexmask.long.byte 0x0 24.--31. 1. "NUM_LOCKS,Module configuration parameter n the total number of spinlocks divided by 32. e.g. For 256 spin locks this will return the number 0x08" newline bitfld.long 0x0 7. "IN_USE7,In-Use flag 7 covering lock registers 224 - 255. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 224 - 255 are in the Not Taken state Read 1 : At least one of the lock registers 224.." "0: All lock registers 224,1: At least one of the lock registers 224" newline bitfld.long 0x0 6. "IN_USE6,In-Use flag 6 covering lock registers 192 - 223. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 192 - 223 are in the Not Taken state Read 1 : At least one of the lock registers 192.." "0: All lock registers 192,1: At least one of the lock registers 192" newline bitfld.long 0x0 5. "IN_USE5,In-Use flag 5 covering lock registers 160 - 191. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 160 - 191 are in the Not Taken state Read 1 : At least one of the lock registers 160.." "0: All lock registers 160,1: At least one of the lock registers 160" newline bitfld.long 0x0 4. "IN_USE4,In-Use flag 4 covering lock registers 128 - 159. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 128 - 159 are in the Not Taken state Read 1 : At least one of the lock registers 128.." "0: All lock registers 128,1: At least one of the lock registers 128" newline bitfld.long 0x0 3. "IN_USE3,In-Use flag 3 covering lock registers 96 - 127. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 96 - 127 are in the Not Taken state Read 1 : At least one of the lock registers 96 -.." "0: All lock registers 96,1: At least one of the lock registers 96" newline bitfld.long 0x0 2. "IN_USE2,In-Use flag 2 covering lock registers 64 - 95. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 64 - 95 are in the Not Taken state Read 1 : At least one of the lock registers 64 - 95.." "0: All lock registers 64,1: At least one of the lock registers 64" newline bitfld.long 0x0 1. "IN_USE1,In-Use flag 1 covering lock registers 32 - 63. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 32 - 63 are in the Not Taken state Read 1 : At least one of the lock registers 32 - 63.." "0: All lock registers 32,1: At least one of the lock registers 32" newline bitfld.long 0x0 0. "IN_USE0,In-Use flag 0 covering lock registers 0 - 31. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 0 - 31 are in the Not Taken state Read 1 : At least one of the lock registers 0 - 31.." "0: All lock registers 0,1: At least one of the lock registers 0" rgroup.long 0x800++0x3 line.long 0x0 "VIRT_ALIAS_12_SPINLOCK0__CFG__REGS_LOCK,The Lock[a] register is read and written to perform lock and unlock operations on lock 'a'" bitfld.long 0x0 0. "TAKEN,Lock Status Read 0 : Lock was previously free. The reader now has been granted the lock. Read 1 : Lock was previously taken. The reader has not been granted the lock and must retry. Write 0 : Free the lock by setting TAKEN to zero. Write 1 : No.." "0: Free the lock by setting TAKEN to zero,1: No effect" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SPINLOCK_0_VIRT_ALIAS_13_SPINLOCK0_CFG (NAVSS0_SPINLOCK_0_VIRT_ALIAS_13_SPINLOCK0_CFG)" base ad:0x4BD0E00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_SPINLOCK0__CFG__REGS_SPLOCK_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_SPINLOCK0__CFG__REGS_SPLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock" bitfld.long 0x0 1. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0 It has the same effect as the hardware reset Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and free all of the.." "0,1" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_13_SPINLOCK0__CFG__REGS_SPLOCK_SYSTATUS,Provides information about the Spinlock module" hexmask.long.byte 0x0 24.--31. 1. "NUM_LOCKS,Module configuration parameter n the total number of spinlocks divided by 32. e.g. For 256 spin locks this will return the number 0x08" newline bitfld.long 0x0 7. "IN_USE7,In-Use flag 7 covering lock registers 224 - 255. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 224 - 255 are in the Not Taken state Read 1 : At least one of the lock registers 224.." "0: All lock registers 224,1: At least one of the lock registers 224" newline bitfld.long 0x0 6. "IN_USE6,In-Use flag 6 covering lock registers 192 - 223. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 192 - 223 are in the Not Taken state Read 1 : At least one of the lock registers 192.." "0: All lock registers 192,1: At least one of the lock registers 192" newline bitfld.long 0x0 5. "IN_USE5,In-Use flag 5 covering lock registers 160 - 191. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 160 - 191 are in the Not Taken state Read 1 : At least one of the lock registers 160.." "0: All lock registers 160,1: At least one of the lock registers 160" newline bitfld.long 0x0 4. "IN_USE4,In-Use flag 4 covering lock registers 128 - 159. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 128 - 159 are in the Not Taken state Read 1 : At least one of the lock registers 128.." "0: All lock registers 128,1: At least one of the lock registers 128" newline bitfld.long 0x0 3. "IN_USE3,In-Use flag 3 covering lock registers 96 - 127. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 96 - 127 are in the Not Taken state Read 1 : At least one of the lock registers 96 -.." "0: All lock registers 96,1: At least one of the lock registers 96" newline bitfld.long 0x0 2. "IN_USE2,In-Use flag 2 covering lock registers 64 - 95. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 64 - 95 are in the Not Taken state Read 1 : At least one of the lock registers 64 - 95.." "0: All lock registers 64,1: At least one of the lock registers 64" newline bitfld.long 0x0 1. "IN_USE1,In-Use flag 1 covering lock registers 32 - 63. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 32 - 63 are in the Not Taken state Read 1 : At least one of the lock registers 32 - 63.." "0: All lock registers 32,1: At least one of the lock registers 32" newline bitfld.long 0x0 0. "IN_USE0,In-Use flag 0 covering lock registers 0 - 31. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 0 - 31 are in the Not Taken state Read 1 : At least one of the lock registers 0 - 31.." "0: All lock registers 0,1: At least one of the lock registers 0" rgroup.long 0x800++0x3 line.long 0x0 "VIRT_ALIAS_13_SPINLOCK0__CFG__REGS_LOCK,The Lock[a] register is read and written to perform lock and unlock operations on lock 'a'" bitfld.long 0x0 0. "TAKEN,Lock Status Read 0 : Lock was previously free. The reader now has been granted the lock. Read 1 : Lock was previously taken. The reader has not been granted the lock and must retry. Write 0 : Free the lock by setting TAKEN to zero. Write 1 : No.." "0: Free the lock by setting TAKEN to zero,1: No effect" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SPINLOCK_0_VIRT_ALIAS_14_SPINLOCK0_CFG (NAVSS0_SPINLOCK_0_VIRT_ALIAS_14_SPINLOCK0_CFG)" base ad:0x4BE0E00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_SPINLOCK0__CFG__REGS_SPLOCK_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_SPINLOCK0__CFG__REGS_SPLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock" bitfld.long 0x0 1. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0 It has the same effect as the hardware reset Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and free all of the.." "0,1" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_14_SPINLOCK0__CFG__REGS_SPLOCK_SYSTATUS,Provides information about the Spinlock module" hexmask.long.byte 0x0 24.--31. 1. "NUM_LOCKS,Module configuration parameter n the total number of spinlocks divided by 32. e.g. For 256 spin locks this will return the number 0x08" newline bitfld.long 0x0 7. "IN_USE7,In-Use flag 7 covering lock registers 224 - 255. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 224 - 255 are in the Not Taken state Read 1 : At least one of the lock registers 224.." "0: All lock registers 224,1: At least one of the lock registers 224" newline bitfld.long 0x0 6. "IN_USE6,In-Use flag 6 covering lock registers 192 - 223. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 192 - 223 are in the Not Taken state Read 1 : At least one of the lock registers 192.." "0: All lock registers 192,1: At least one of the lock registers 192" newline bitfld.long 0x0 5. "IN_USE5,In-Use flag 5 covering lock registers 160 - 191. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 160 - 191 are in the Not Taken state Read 1 : At least one of the lock registers 160.." "0: All lock registers 160,1: At least one of the lock registers 160" newline bitfld.long 0x0 4. "IN_USE4,In-Use flag 4 covering lock registers 128 - 159. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 128 - 159 are in the Not Taken state Read 1 : At least one of the lock registers 128.." "0: All lock registers 128,1: At least one of the lock registers 128" newline bitfld.long 0x0 3. "IN_USE3,In-Use flag 3 covering lock registers 96 - 127. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 96 - 127 are in the Not Taken state Read 1 : At least one of the lock registers 96 -.." "0: All lock registers 96,1: At least one of the lock registers 96" newline bitfld.long 0x0 2. "IN_USE2,In-Use flag 2 covering lock registers 64 - 95. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 64 - 95 are in the Not Taken state Read 1 : At least one of the lock registers 64 - 95.." "0: All lock registers 64,1: At least one of the lock registers 64" newline bitfld.long 0x0 1. "IN_USE1,In-Use flag 1 covering lock registers 32 - 63. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 32 - 63 are in the Not Taken state Read 1 : At least one of the lock registers 32 - 63.." "0: All lock registers 32,1: At least one of the lock registers 32" newline bitfld.long 0x0 0. "IN_USE0,In-Use flag 0 covering lock registers 0 - 31. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 0 - 31 are in the Not Taken state Read 1 : At least one of the lock registers 0 - 31.." "0: All lock registers 0,1: At least one of the lock registers 0" rgroup.long 0x800++0x3 line.long 0x0 "VIRT_ALIAS_14_SPINLOCK0__CFG__REGS_LOCK,The Lock[a] register is read and written to perform lock and unlock operations on lock 'a'" bitfld.long 0x0 0. "TAKEN,Lock Status Read 0 : Lock was previously free. The reader now has been granted the lock. Read 1 : Lock was previously taken. The reader has not been granted the lock and must retry. Write 0 : Free the lock by setting TAKEN to zero. Write 1 : No.." "0: Free the lock by setting TAKEN to zero,1: No effect" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_SPINLOCK_0_VIRT_ALIAS_15_SPINLOCK0_CFG (NAVSS0_SPINLOCK_0_VIRT_ALIAS_15_SPINLOCK0_CFG)" base ad:0x4BF0E00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_SPINLOCK0__CFG__REGS_SPLOCK_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_SPINLOCK0__CFG__REGS_SPLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock" bitfld.long 0x0 1. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0 It has the same effect as the hardware reset Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and free all of the.." "0,1" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_15_SPINLOCK0__CFG__REGS_SPLOCK_SYSTATUS,Provides information about the Spinlock module" hexmask.long.byte 0x0 24.--31. 1. "NUM_LOCKS,Module configuration parameter n the total number of spinlocks divided by 32. e.g. For 256 spin locks this will return the number 0x08" newline bitfld.long 0x0 7. "IN_USE7,In-Use flag 7 covering lock registers 224 - 255. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 224 - 255 are in the Not Taken state Read 1 : At least one of the lock registers 224.." "0: All lock registers 224,1: At least one of the lock registers 224" newline bitfld.long 0x0 6. "IN_USE6,In-Use flag 6 covering lock registers 192 - 223. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 192 - 223 are in the Not Taken state Read 1 : At least one of the lock registers 192.." "0: All lock registers 192,1: At least one of the lock registers 192" newline bitfld.long 0x0 5. "IN_USE5,In-Use flag 5 covering lock registers 160 - 191. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 160 - 191 are in the Not Taken state Read 1 : At least one of the lock registers 160.." "0: All lock registers 160,1: At least one of the lock registers 160" newline bitfld.long 0x0 4. "IN_USE4,In-Use flag 4 covering lock registers 128 - 159. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 128 - 159 are in the Not Taken state Read 1 : At least one of the lock registers 128.." "0: All lock registers 128,1: At least one of the lock registers 128" newline bitfld.long 0x0 3. "IN_USE3,In-Use flag 3 covering lock registers 96 - 127. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 96 - 127 are in the Not Taken state Read 1 : At least one of the lock registers 96 -.." "0: All lock registers 96,1: At least one of the lock registers 96" newline bitfld.long 0x0 2. "IN_USE2,In-Use flag 2 covering lock registers 64 - 95. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 64 - 95 are in the Not Taken state Read 1 : At least one of the lock registers 64 - 95.." "0: All lock registers 64,1: At least one of the lock registers 64" newline bitfld.long 0x0 1. "IN_USE1,In-Use flag 1 covering lock registers 32 - 63. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 32 - 63 are in the Not Taken state Read 1 : At least one of the lock registers 32 - 63.." "0: All lock registers 32,1: At least one of the lock registers 32" newline bitfld.long 0x0 0. "IN_USE0,In-Use flag 0 covering lock registers 0 - 31. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 0 - 31 are in the Not Taken state Read 1 : At least one of the lock registers 0 - 31.." "0: All lock registers 0,1: At least one of the lock registers 0" rgroup.long 0x800++0x3 line.long 0x0 "VIRT_ALIAS_15_SPINLOCK0__CFG__REGS_LOCK,The Lock[a] register is read and written to perform lock and unlock operations on lock 'a'" bitfld.long 0x0 0. "TAKEN,Lock Status Read 0 : Lock was previously free. The reader now has been granted the lock. Read 1 : Lock was previously taken. The reader has not been granted the lock and must retry. Write 0 : Free the lock by setting TAKEN to zero. Write 1 : No.." "0: Free the lock by setting TAKEN to zero,1: No effect" tree.end endif tree.end tree.end tree "NAVSS0_TIMERMGR" tree "NAVSS0_TIMERMGR_0" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_ALIAS64K_TIMERMGR0_CFG_TIMERS (NAVSS0_TIMERMGR_0_ALIAS64K_TIMERMGR0_CFG_TIMERS)" base ad:0x4A22000000 rgroup.long 0x0++0x7 line.long 0x0 "ALIAS64K_TIMERMGR0__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via TM_CTRL.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "ALIAS64K_TIMERMGR0__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif tree "NAVSS0_TIMERMGR_0_TIMERMGR0" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_TIMERMGR0_CFG_CONFIG (NAVSS0_TIMERMGR_0_TIMERMGR0_CFG_CONFIG)" base ad:0x30E80000 rgroup.long 0x0++0x3 line.long 0x0 "TIMERMGR0__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" newline bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "TIMERMGR0__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "TIMERMGR0__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is the only MMR.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all 1024 timers." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which banks contain.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "TIMERMGR0__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_TIMERMGR0_CFG_OES (NAVSS0_TIMERMGR_0_TIMERMGR0_CFG_OES)" base ad:0x30F00000 rgroup.long 0x0++0x3 line.long 0x0 "TIMERMGR0__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_TIMERMGR0_CFG_TIMERS (NAVSS0_TIMERMGR_0_TIMERMGR0_CFG_TIMERS)" base ad:0x32200000 rgroup.long 0x0++0x7 line.long 0x0 "TIMERMGR0__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via TM_CTRL and.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "TIMERMGR0__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif tree.end tree "NAVSS0_TIMERMGR_0_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_0_TIMERMGR0_CFG_CONFIG (NAVSS0_TIMERMGR_0_VIRT_ALIAS_0_TIMERMGR0_CFG_CONFIG)" base ad:0x4B00E80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_TIMERMGR0__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_0_TIMERMGR0__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_0_TIMERMGR0__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_0_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_0_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_0_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_0_TIMERMGR0__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_0_TIMERMGR0_CFG_OES (NAVSS0_TIMERMGR_0_VIRT_ALIAS_0_TIMERMGR0_CFG_OES)" base ad:0x4B00F00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_TIMERMGR0__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_0_TIMERMGR0_CFG_TIMERS (NAVSS0_TIMERMGR_0_VIRT_ALIAS_0_TIMERMGR0_CFG_TIMERS)" base ad:0x4B02200000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_0_TIMERMGR0__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_0_TIMERMGR0__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_1_TIMERMGR0_CFG_CONFIG (NAVSS0_TIMERMGR_0_VIRT_ALIAS_1_TIMERMGR0_CFG_CONFIG)" base ad:0x4B10E80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_TIMERMGR0__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_1_TIMERMGR0__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_1_TIMERMGR0__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_1_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_1_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_1_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_1_TIMERMGR0__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_1_TIMERMGR0_CFG_OES (NAVSS0_TIMERMGR_0_VIRT_ALIAS_1_TIMERMGR0_CFG_OES)" base ad:0x4B10F00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_TIMERMGR0__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_1_TIMERMGR0_CFG_TIMERS (NAVSS0_TIMERMGR_0_VIRT_ALIAS_1_TIMERMGR0_CFG_TIMERS)" base ad:0x4B12200000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_1_TIMERMGR0__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_1_TIMERMGR0__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_2_TIMERMGR0_CFG_CONFIG (NAVSS0_TIMERMGR_0_VIRT_ALIAS_2_TIMERMGR0_CFG_CONFIG)" base ad:0x4B20E80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_TIMERMGR0__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_2_TIMERMGR0__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_2_TIMERMGR0__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_2_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_2_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_2_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_2_TIMERMGR0__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_2_TIMERMGR0_CFG_OES (NAVSS0_TIMERMGR_0_VIRT_ALIAS_2_TIMERMGR0_CFG_OES)" base ad:0x4B20F00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_TIMERMGR0__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_2_TIMERMGR0_CFG_TIMERS (NAVSS0_TIMERMGR_0_VIRT_ALIAS_2_TIMERMGR0_CFG_TIMERS)" base ad:0x4B22200000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_2_TIMERMGR0__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_2_TIMERMGR0__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_3_TIMERMGR0_CFG_CONFIG (NAVSS0_TIMERMGR_0_VIRT_ALIAS_3_TIMERMGR0_CFG_CONFIG)" base ad:0x4B30E80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_TIMERMGR0__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_3_TIMERMGR0__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_3_TIMERMGR0__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_3_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_3_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_3_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_3_TIMERMGR0__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_3_TIMERMGR0_CFG_OES (NAVSS0_TIMERMGR_0_VIRT_ALIAS_3_TIMERMGR0_CFG_OES)" base ad:0x4B30F00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_TIMERMGR0__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_3_TIMERMGR0_CFG_TIMERS (NAVSS0_TIMERMGR_0_VIRT_ALIAS_3_TIMERMGR0_CFG_TIMERS)" base ad:0x4B32200000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_3_TIMERMGR0__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_3_TIMERMGR0__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_4_TIMERMGR0_CFG_CONFIG (NAVSS0_TIMERMGR_0_VIRT_ALIAS_4_TIMERMGR0_CFG_CONFIG)" base ad:0x4B40E80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_TIMERMGR0__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_4_TIMERMGR0__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_4_TIMERMGR0__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_4_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_4_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_4_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_4_TIMERMGR0__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_4_TIMERMGR0_CFG_OES (NAVSS0_TIMERMGR_0_VIRT_ALIAS_4_TIMERMGR0_CFG_OES)" base ad:0x4B40F00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_TIMERMGR0__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_4_TIMERMGR0_CFG_TIMERS (NAVSS0_TIMERMGR_0_VIRT_ALIAS_4_TIMERMGR0_CFG_TIMERS)" base ad:0x4B42200000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_4_TIMERMGR0__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_4_TIMERMGR0__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_5_TIMERMGR0_CFG_CONFIG (NAVSS0_TIMERMGR_0_VIRT_ALIAS_5_TIMERMGR0_CFG_CONFIG)" base ad:0x4B50E80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_TIMERMGR0__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_5_TIMERMGR0__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_5_TIMERMGR0__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_5_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_5_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_5_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_5_TIMERMGR0__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_5_TIMERMGR0_CFG_OES (NAVSS0_TIMERMGR_0_VIRT_ALIAS_5_TIMERMGR0_CFG_OES)" base ad:0x4B50F00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_TIMERMGR0__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_5_TIMERMGR0_CFG_TIMERS (NAVSS0_TIMERMGR_0_VIRT_ALIAS_5_TIMERMGR0_CFG_TIMERS)" base ad:0x4B52200000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_5_TIMERMGR0__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_5_TIMERMGR0__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_6_TIMERMGR0_CFG_CONFIG (NAVSS0_TIMERMGR_0_VIRT_ALIAS_6_TIMERMGR0_CFG_CONFIG)" base ad:0x4B60E80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_TIMERMGR0__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_6_TIMERMGR0__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_6_TIMERMGR0__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_6_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_6_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_6_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_6_TIMERMGR0__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_6_TIMERMGR0_CFG_OES (NAVSS0_TIMERMGR_0_VIRT_ALIAS_6_TIMERMGR0_CFG_OES)" base ad:0x4B60F00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_TIMERMGR0__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_6_TIMERMGR0_CFG_TIMERS (NAVSS0_TIMERMGR_0_VIRT_ALIAS_6_TIMERMGR0_CFG_TIMERS)" base ad:0x4B62200000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_6_TIMERMGR0__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_6_TIMERMGR0__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_7_TIMERMGR0_CFG_CONFIG (NAVSS0_TIMERMGR_0_VIRT_ALIAS_7_TIMERMGR0_CFG_CONFIG)" base ad:0x4B70E80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_TIMERMGR0__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_7_TIMERMGR0__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_7_TIMERMGR0__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_7_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_7_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_7_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_7_TIMERMGR0__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_7_TIMERMGR0_CFG_OES (NAVSS0_TIMERMGR_0_VIRT_ALIAS_7_TIMERMGR0_CFG_OES)" base ad:0x4B70F00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_TIMERMGR0__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_7_TIMERMGR0_CFG_TIMERS (NAVSS0_TIMERMGR_0_VIRT_ALIAS_7_TIMERMGR0_CFG_TIMERS)" base ad:0x4B72200000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_7_TIMERMGR0__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_7_TIMERMGR0__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_8_TIMERMGR0_CFG_CONFIG (NAVSS0_TIMERMGR_0_VIRT_ALIAS_8_TIMERMGR0_CFG_CONFIG)" base ad:0x4B80E80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_TIMERMGR0__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_8_TIMERMGR0__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_8_TIMERMGR0__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_8_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_8_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_8_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_8_TIMERMGR0__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_8_TIMERMGR0_CFG_OES (NAVSS0_TIMERMGR_0_VIRT_ALIAS_8_TIMERMGR0_CFG_OES)" base ad:0x4B80F00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_TIMERMGR0__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_8_TIMERMGR0_CFG_TIMERS (NAVSS0_TIMERMGR_0_VIRT_ALIAS_8_TIMERMGR0_CFG_TIMERS)" base ad:0x4B82200000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_8_TIMERMGR0__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_8_TIMERMGR0__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_9_TIMERMGR0_CFG_CONFIG (NAVSS0_TIMERMGR_0_VIRT_ALIAS_9_TIMERMGR0_CFG_CONFIG)" base ad:0x4B90E80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_TIMERMGR0__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_9_TIMERMGR0__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_9_TIMERMGR0__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_9_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_9_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_9_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_9_TIMERMGR0__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_9_TIMERMGR0_CFG_OES (NAVSS0_TIMERMGR_0_VIRT_ALIAS_9_TIMERMGR0_CFG_OES)" base ad:0x4B90F00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_TIMERMGR0__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_9_TIMERMGR0_CFG_TIMERS (NAVSS0_TIMERMGR_0_VIRT_ALIAS_9_TIMERMGR0_CFG_TIMERS)" base ad:0x4B92200000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_9_TIMERMGR0__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_9_TIMERMGR0__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_10_TIMERMGR0_CFG_CONFIG (NAVSS0_TIMERMGR_0_VIRT_ALIAS_10_TIMERMGR0_CFG_CONFIG)" base ad:0x4BA0E80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_TIMERMGR0__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_10_TIMERMGR0__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_10_TIMERMGR0__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_10_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_10_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_10_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_10_TIMERMGR0__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_10_TIMERMGR0_CFG_OES (NAVSS0_TIMERMGR_0_VIRT_ALIAS_10_TIMERMGR0_CFG_OES)" base ad:0x4BA0F00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_TIMERMGR0__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_10_TIMERMGR0_CFG_TIMERS (NAVSS0_TIMERMGR_0_VIRT_ALIAS_10_TIMERMGR0_CFG_TIMERS)" base ad:0x4BA2200000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_10_TIMERMGR0__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_10_TIMERMGR0__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_11_TIMERMGR0_CFG_CONFIG (NAVSS0_TIMERMGR_0_VIRT_ALIAS_11_TIMERMGR0_CFG_CONFIG)" base ad:0x4BB0E80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_TIMERMGR0__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_11_TIMERMGR0__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_11_TIMERMGR0__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_11_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_11_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_11_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_11_TIMERMGR0__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_11_TIMERMGR0_CFG_OES (NAVSS0_TIMERMGR_0_VIRT_ALIAS_11_TIMERMGR0_CFG_OES)" base ad:0x4BB0F00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_TIMERMGR0__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_11_TIMERMGR0_CFG_TIMERS (NAVSS0_TIMERMGR_0_VIRT_ALIAS_11_TIMERMGR0_CFG_TIMERS)" base ad:0x4BB2200000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_11_TIMERMGR0__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_11_TIMERMGR0__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_12_TIMERMGR0_CFG_CONFIG (NAVSS0_TIMERMGR_0_VIRT_ALIAS_12_TIMERMGR0_CFG_CONFIG)" base ad:0x4BC0E80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_TIMERMGR0__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_12_TIMERMGR0__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_12_TIMERMGR0__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_12_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_12_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_12_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_12_TIMERMGR0__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_12_TIMERMGR0_CFG_OES (NAVSS0_TIMERMGR_0_VIRT_ALIAS_12_TIMERMGR0_CFG_OES)" base ad:0x4BC0F00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_TIMERMGR0__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_12_TIMERMGR0_CFG_TIMERS (NAVSS0_TIMERMGR_0_VIRT_ALIAS_12_TIMERMGR0_CFG_TIMERS)" base ad:0x4BC2200000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_12_TIMERMGR0__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_12_TIMERMGR0__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_13_TIMERMGR0_CFG_CONFIG (NAVSS0_TIMERMGR_0_VIRT_ALIAS_13_TIMERMGR0_CFG_CONFIG)" base ad:0x4BD0E80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_TIMERMGR0__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_13_TIMERMGR0__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_13_TIMERMGR0__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_13_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_13_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_13_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_13_TIMERMGR0__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_13_TIMERMGR0_CFG_OES (NAVSS0_TIMERMGR_0_VIRT_ALIAS_13_TIMERMGR0_CFG_OES)" base ad:0x4BD0F00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_TIMERMGR0__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_13_TIMERMGR0_CFG_TIMERS (NAVSS0_TIMERMGR_0_VIRT_ALIAS_13_TIMERMGR0_CFG_TIMERS)" base ad:0x4BD2200000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_13_TIMERMGR0__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_13_TIMERMGR0__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_14_TIMERMGR0_CFG_CONFIG (NAVSS0_TIMERMGR_0_VIRT_ALIAS_14_TIMERMGR0_CFG_CONFIG)" base ad:0x4BE0E80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_TIMERMGR0__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_14_TIMERMGR0__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_14_TIMERMGR0__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_14_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_14_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_14_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_14_TIMERMGR0__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_14_TIMERMGR0_CFG_OES (NAVSS0_TIMERMGR_0_VIRT_ALIAS_14_TIMERMGR0_CFG_OES)" base ad:0x4BE0F00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_TIMERMGR0__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_14_TIMERMGR0_CFG_TIMERS (NAVSS0_TIMERMGR_0_VIRT_ALIAS_14_TIMERMGR0_CFG_TIMERS)" base ad:0x4BE2200000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_14_TIMERMGR0__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_14_TIMERMGR0__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_15_TIMERMGR0_CFG_CONFIG (NAVSS0_TIMERMGR_0_VIRT_ALIAS_15_TIMERMGR0_CFG_CONFIG)" base ad:0x4BF0E80000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_TIMERMGR0__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_15_TIMERMGR0__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_15_TIMERMGR0__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_15_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_15_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_15_TIMERMGR0__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_15_TIMERMGR0__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_15_TIMERMGR0_CFG_OES (NAVSS0_TIMERMGR_0_VIRT_ALIAS_15_TIMERMGR0_CFG_OES)" base ad:0x4BF0F00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_TIMERMGR0__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_0_VIRT_ALIAS_15_TIMERMGR0_CFG_TIMERS (NAVSS0_TIMERMGR_0_VIRT_ALIAS_15_TIMERMGR0_CFG_TIMERS)" base ad:0x4BF2200000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_15_TIMERMGR0__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_15_TIMERMGR0__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif tree.end tree.end tree "NAVSS0_TIMERMGR_1" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_ALIAS64K_TIMERMGR1_CFG_TIMERS (NAVSS0_TIMERMGR_1_ALIAS64K_TIMERMGR1_CFG_TIMERS)" base ad:0x4A22400000 rgroup.long 0x0++0x7 line.long 0x0 "ALIAS64K_TIMERMGR1__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via TM_CTRL.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "ALIAS64K_TIMERMGR1__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif tree "NAVSS0_TIMERMGR_1_TIMERMGR1" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_TIMERMGR1_CFG_CONFIG (NAVSS0_TIMERMGR_1_TIMERMGR1_CFG_CONFIG)" base ad:0x30E81000 rgroup.long 0x0++0x3 line.long 0x0 "TIMERMGR1__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" newline bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "TIMERMGR1__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "TIMERMGR1__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is the only MMR.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all 1024 timers." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which banks contain.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "TIMERMGR1__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_TIMERMGR1_CFG_OES (NAVSS0_TIMERMGR_1_TIMERMGR1_CFG_OES)" base ad:0x30F01000 rgroup.long 0x0++0x3 line.long 0x0 "TIMERMGR1__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_TIMERMGR1_CFG_TIMERS (NAVSS0_TIMERMGR_1_TIMERMGR1_CFG_TIMERS)" base ad:0x32240000 rgroup.long 0x0++0x7 line.long 0x0 "TIMERMGR1__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via TM_CTRL and.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "TIMERMGR1__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif tree.end tree "NAVSS0_TIMERMGR_1_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_0_TIMERMGR1_CFG_CONFIG (NAVSS0_TIMERMGR_1_VIRT_ALIAS_0_TIMERMGR1_CFG_CONFIG)" base ad:0x4B00E81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_TIMERMGR1__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_0_TIMERMGR1__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_0_TIMERMGR1__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_0_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_0_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_0_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_0_TIMERMGR1__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_0_TIMERMGR1_CFG_OES (NAVSS0_TIMERMGR_1_VIRT_ALIAS_0_TIMERMGR1_CFG_OES)" base ad:0x4B00F01000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_TIMERMGR1__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_0_TIMERMGR1_CFG_TIMERS (NAVSS0_TIMERMGR_1_VIRT_ALIAS_0_TIMERMGR1_CFG_TIMERS)" base ad:0x4B02240000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_0_TIMERMGR1__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_0_TIMERMGR1__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_1_TIMERMGR1_CFG_CONFIG (NAVSS0_TIMERMGR_1_VIRT_ALIAS_1_TIMERMGR1_CFG_CONFIG)" base ad:0x4B10E81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_TIMERMGR1__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_1_TIMERMGR1__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_1_TIMERMGR1__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_1_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_1_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_1_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_1_TIMERMGR1__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_1_TIMERMGR1_CFG_OES (NAVSS0_TIMERMGR_1_VIRT_ALIAS_1_TIMERMGR1_CFG_OES)" base ad:0x4B10F01000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_TIMERMGR1__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_1_TIMERMGR1_CFG_TIMERS (NAVSS0_TIMERMGR_1_VIRT_ALIAS_1_TIMERMGR1_CFG_TIMERS)" base ad:0x4B12240000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_1_TIMERMGR1__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_1_TIMERMGR1__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_2_TIMERMGR1_CFG_CONFIG (NAVSS0_TIMERMGR_1_VIRT_ALIAS_2_TIMERMGR1_CFG_CONFIG)" base ad:0x4B20E81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_TIMERMGR1__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_2_TIMERMGR1__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_2_TIMERMGR1__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_2_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_2_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_2_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_2_TIMERMGR1__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_2_TIMERMGR1_CFG_OES (NAVSS0_TIMERMGR_1_VIRT_ALIAS_2_TIMERMGR1_CFG_OES)" base ad:0x4B20F01000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_TIMERMGR1__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_2_TIMERMGR1_CFG_TIMERS (NAVSS0_TIMERMGR_1_VIRT_ALIAS_2_TIMERMGR1_CFG_TIMERS)" base ad:0x4B22240000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_2_TIMERMGR1__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_2_TIMERMGR1__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_3_TIMERMGR1_CFG_CONFIG (NAVSS0_TIMERMGR_1_VIRT_ALIAS_3_TIMERMGR1_CFG_CONFIG)" base ad:0x4B30E81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_TIMERMGR1__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_3_TIMERMGR1__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_3_TIMERMGR1__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_3_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_3_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_3_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_3_TIMERMGR1__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_3_TIMERMGR1_CFG_OES (NAVSS0_TIMERMGR_1_VIRT_ALIAS_3_TIMERMGR1_CFG_OES)" base ad:0x4B30F01000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_TIMERMGR1__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_3_TIMERMGR1_CFG_TIMERS (NAVSS0_TIMERMGR_1_VIRT_ALIAS_3_TIMERMGR1_CFG_TIMERS)" base ad:0x4B32240000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_3_TIMERMGR1__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_3_TIMERMGR1__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_4_TIMERMGR1_CFG_CONFIG (NAVSS0_TIMERMGR_1_VIRT_ALIAS_4_TIMERMGR1_CFG_CONFIG)" base ad:0x4B40E81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_TIMERMGR1__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_4_TIMERMGR1__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_4_TIMERMGR1__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_4_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_4_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_4_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_4_TIMERMGR1__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_4_TIMERMGR1_CFG_OES (NAVSS0_TIMERMGR_1_VIRT_ALIAS_4_TIMERMGR1_CFG_OES)" base ad:0x4B40F01000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_TIMERMGR1__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_4_TIMERMGR1_CFG_TIMERS (NAVSS0_TIMERMGR_1_VIRT_ALIAS_4_TIMERMGR1_CFG_TIMERS)" base ad:0x4B42240000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_4_TIMERMGR1__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_4_TIMERMGR1__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_5_TIMERMGR1_CFG_CONFIG (NAVSS0_TIMERMGR_1_VIRT_ALIAS_5_TIMERMGR1_CFG_CONFIG)" base ad:0x4B50E81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_TIMERMGR1__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_5_TIMERMGR1__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_5_TIMERMGR1__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_5_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_5_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_5_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_5_TIMERMGR1__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_5_TIMERMGR1_CFG_OES (NAVSS0_TIMERMGR_1_VIRT_ALIAS_5_TIMERMGR1_CFG_OES)" base ad:0x4B50F01000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_TIMERMGR1__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_5_TIMERMGR1_CFG_TIMERS (NAVSS0_TIMERMGR_1_VIRT_ALIAS_5_TIMERMGR1_CFG_TIMERS)" base ad:0x4B52240000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_5_TIMERMGR1__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_5_TIMERMGR1__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_6_TIMERMGR1_CFG_CONFIG (NAVSS0_TIMERMGR_1_VIRT_ALIAS_6_TIMERMGR1_CFG_CONFIG)" base ad:0x4B60E81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_TIMERMGR1__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_6_TIMERMGR1__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_6_TIMERMGR1__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_6_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_6_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_6_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_6_TIMERMGR1__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_6_TIMERMGR1_CFG_OES (NAVSS0_TIMERMGR_1_VIRT_ALIAS_6_TIMERMGR1_CFG_OES)" base ad:0x4B60F01000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_TIMERMGR1__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_6_TIMERMGR1_CFG_TIMERS (NAVSS0_TIMERMGR_1_VIRT_ALIAS_6_TIMERMGR1_CFG_TIMERS)" base ad:0x4B62240000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_6_TIMERMGR1__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_6_TIMERMGR1__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_7_TIMERMGR1_CFG_CONFIG (NAVSS0_TIMERMGR_1_VIRT_ALIAS_7_TIMERMGR1_CFG_CONFIG)" base ad:0x4B70E81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_TIMERMGR1__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_7_TIMERMGR1__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_7_TIMERMGR1__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_7_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_7_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_7_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_7_TIMERMGR1__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_7_TIMERMGR1_CFG_OES (NAVSS0_TIMERMGR_1_VIRT_ALIAS_7_TIMERMGR1_CFG_OES)" base ad:0x4B70F01000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_TIMERMGR1__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_7_TIMERMGR1_CFG_TIMERS (NAVSS0_TIMERMGR_1_VIRT_ALIAS_7_TIMERMGR1_CFG_TIMERS)" base ad:0x4B72240000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_7_TIMERMGR1__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_7_TIMERMGR1__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_8_TIMERMGR1_CFG_CONFIG (NAVSS0_TIMERMGR_1_VIRT_ALIAS_8_TIMERMGR1_CFG_CONFIG)" base ad:0x4B80E81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_TIMERMGR1__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_8_TIMERMGR1__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_8_TIMERMGR1__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_8_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_8_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_8_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_8_TIMERMGR1__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_8_TIMERMGR1_CFG_OES (NAVSS0_TIMERMGR_1_VIRT_ALIAS_8_TIMERMGR1_CFG_OES)" base ad:0x4B80F01000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_TIMERMGR1__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_8_TIMERMGR1_CFG_TIMERS (NAVSS0_TIMERMGR_1_VIRT_ALIAS_8_TIMERMGR1_CFG_TIMERS)" base ad:0x4B82240000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_8_TIMERMGR1__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_8_TIMERMGR1__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_9_TIMERMGR1_CFG_CONFIG (NAVSS0_TIMERMGR_1_VIRT_ALIAS_9_TIMERMGR1_CFG_CONFIG)" base ad:0x4B90E81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_TIMERMGR1__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_9_TIMERMGR1__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_9_TIMERMGR1__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_9_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_9_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_9_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_9_TIMERMGR1__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_9_TIMERMGR1_CFG_OES (NAVSS0_TIMERMGR_1_VIRT_ALIAS_9_TIMERMGR1_CFG_OES)" base ad:0x4B90F01000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_TIMERMGR1__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_9_TIMERMGR1_CFG_TIMERS (NAVSS0_TIMERMGR_1_VIRT_ALIAS_9_TIMERMGR1_CFG_TIMERS)" base ad:0x4B92240000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_9_TIMERMGR1__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_9_TIMERMGR1__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_10_TIMERMGR1_CFG_CONFIG (NAVSS0_TIMERMGR_1_VIRT_ALIAS_10_TIMERMGR1_CFG_CONFIG)" base ad:0x4BA0E81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_TIMERMGR1__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_10_TIMERMGR1__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_10_TIMERMGR1__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_10_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_10_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_10_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_10_TIMERMGR1__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_10_TIMERMGR1_CFG_OES (NAVSS0_TIMERMGR_1_VIRT_ALIAS_10_TIMERMGR1_CFG_OES)" base ad:0x4BA0F01000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_TIMERMGR1__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_10_TIMERMGR1_CFG_TIMERS (NAVSS0_TIMERMGR_1_VIRT_ALIAS_10_TIMERMGR1_CFG_TIMERS)" base ad:0x4BA2240000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_10_TIMERMGR1__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_10_TIMERMGR1__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_11_TIMERMGR1_CFG_CONFIG (NAVSS0_TIMERMGR_1_VIRT_ALIAS_11_TIMERMGR1_CFG_CONFIG)" base ad:0x4BB0E81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_TIMERMGR1__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_11_TIMERMGR1__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_11_TIMERMGR1__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_11_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_11_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_11_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_11_TIMERMGR1__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_11_TIMERMGR1_CFG_OES (NAVSS0_TIMERMGR_1_VIRT_ALIAS_11_TIMERMGR1_CFG_OES)" base ad:0x4BB0F01000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_TIMERMGR1__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_11_TIMERMGR1_CFG_TIMERS (NAVSS0_TIMERMGR_1_VIRT_ALIAS_11_TIMERMGR1_CFG_TIMERS)" base ad:0x4BB2240000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_11_TIMERMGR1__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_11_TIMERMGR1__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_12_TIMERMGR1_CFG_CONFIG (NAVSS0_TIMERMGR_1_VIRT_ALIAS_12_TIMERMGR1_CFG_CONFIG)" base ad:0x4BC0E81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_TIMERMGR1__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_12_TIMERMGR1__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_12_TIMERMGR1__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_12_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_12_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_12_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_12_TIMERMGR1__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_12_TIMERMGR1_CFG_OES (NAVSS0_TIMERMGR_1_VIRT_ALIAS_12_TIMERMGR1_CFG_OES)" base ad:0x4BC0F01000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_TIMERMGR1__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_12_TIMERMGR1_CFG_TIMERS (NAVSS0_TIMERMGR_1_VIRT_ALIAS_12_TIMERMGR1_CFG_TIMERS)" base ad:0x4BC2240000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_12_TIMERMGR1__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_12_TIMERMGR1__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_13_TIMERMGR1_CFG_CONFIG (NAVSS0_TIMERMGR_1_VIRT_ALIAS_13_TIMERMGR1_CFG_CONFIG)" base ad:0x4BD0E81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_TIMERMGR1__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_13_TIMERMGR1__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_13_TIMERMGR1__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_13_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_13_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_13_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_13_TIMERMGR1__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_13_TIMERMGR1_CFG_OES (NAVSS0_TIMERMGR_1_VIRT_ALIAS_13_TIMERMGR1_CFG_OES)" base ad:0x4BD0F01000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_TIMERMGR1__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_13_TIMERMGR1_CFG_TIMERS (NAVSS0_TIMERMGR_1_VIRT_ALIAS_13_TIMERMGR1_CFG_TIMERS)" base ad:0x4BD2240000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_13_TIMERMGR1__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_13_TIMERMGR1__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_14_TIMERMGR1_CFG_CONFIG (NAVSS0_TIMERMGR_1_VIRT_ALIAS_14_TIMERMGR1_CFG_CONFIG)" base ad:0x4BE0E81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_TIMERMGR1__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_14_TIMERMGR1__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_14_TIMERMGR1__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_14_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_14_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_14_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_14_TIMERMGR1__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_14_TIMERMGR1_CFG_OES (NAVSS0_TIMERMGR_1_VIRT_ALIAS_14_TIMERMGR1_CFG_OES)" base ad:0x4BE0F01000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_TIMERMGR1__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_14_TIMERMGR1_CFG_TIMERS (NAVSS0_TIMERMGR_1_VIRT_ALIAS_14_TIMERMGR1_CFG_TIMERS)" base ad:0x4BE2240000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_14_TIMERMGR1__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_14_TIMERMGR1__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_15_TIMERMGR1_CFG_CONFIG (NAVSS0_TIMERMGR_1_VIRT_ALIAS_15_TIMERMGR1_CFG_CONFIG)" base ad:0x4BF0E81000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_TIMERMGR1__CFG__CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" rgroup.long 0x4++0x3 line.long 0x0 "VIRT_ALIAS_15_TIMERMGR1__CFG__CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_15_TIMERMGR1__CFG__CONFIG_TIMER_COUNTER,This register contains the current counter value" hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "VIRT_ALIAS_15_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is.." bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "VIRT_ALIAS_15_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all.." bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "VIRT_ALIAS_15_TIMERMGR1__CFG__CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which.." hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "VIRT_ALIAS_15_TIMERMGR1__CFG__CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out" hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_15_TIMERMGR1_CFG_OES (NAVSS0_TIMERMGR_1_VIRT_ALIAS_15_TIMERMGR1_CFG_OES)" base ad:0x4BF0F01000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_TIMERMGR1__CFG__OES_TIMER_EVENT_INDEX,This programs the event index for a given timer" hexmask.long.word 0x0 0.--15. 1. "OES,The event index for a given timer to be used on the output event interface" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_TIMERMGR_1_VIRT_ALIAS_15_TIMERMGR1_CFG_TIMERS (NAVSS0_TIMERMGR_1_VIRT_ALIAS_15_TIMERMGR1_CFG_TIMERS)" base ad:0x4BF2240000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_15_TIMERMGR1__CFG__TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "VIRT_ALIAS_15_TIMERMGR1__CFG__TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below" bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1" bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable 0 to disable the timer." "0,1" tree.end endif tree.end tree.end tree.end tree "NAVSS0_UDMAP_0" tree "NAVSS0_UDMAP_0_ALIAS64K" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_ALIAS64K_UDMAP0_CFG_RCHANRT (NAVSS0_UDMAP_0_ALIAS64K_UDMAP0_CFG_RCHANRT)" base ad:0x4A40000000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the rx_chan_type is configured as a Third Party DMA channel." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "ALIAS64K_UDMAP0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_ALIAS64K_UDMAP0_CFG_TCHANRT (NAVSS0_UDMAP_0_ALIAS64K_UDMAP0_CFG_TCHANRT)" base ad:0x4A50000000 rgroup.long 0x0++0x3 line.long 0x0 "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA channel." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "ALIAS64K_UDMAP0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif tree.end tree "NAVSS0_UDMAP_0_UDMASS" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_UDMASS_UDMAP0_CFG_TCHAN (NAVSS0_UDMAP_0_UDMASS_UDMAP0_CFG_TCHAN)" base ad:0x30B00000 rgroup.long 0x0++0x7 line.long 0x0 "UDMAP0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 30. "TX_FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass extended.." "0: DMA controller will pass extended packet info..,?" newline bitfld.long 0x0 29. "TX_FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass PS words if present in.." "0: DMA controller will pass PS words if present in..,?" newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" newline hexmask.long.byte 0x0 0.--6. 1. "TX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." line.long 0x4 "UDMAP0__CFG__TCHAN_TCREDIT,The Transfer Request Credit Register indicates how many TR sized buffer slots exist in the associated UTC channel to which this channel is associated. This register only exists for external UTC channels. This field should not.." bitfld.long 0x4 0.--2. "COUNT,Transfer Request Credit Count: this field specifies how many credits for complete TRs are available. This field should be initialized before the channel is enabled and will then increment/decrement as TRs are submitted and responses are received." "0,1,2,3,4,5,6,7" rgroup.long 0x14++0x3 line.long 0x0 "UDMAP0__CFG__TCHAN_TCQ,The Tx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value channel mode. This register may only be written when the channel is disabled.." hexmask.long.word 0x0 0.--15. 1. "TXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "UDMAP0__CFG__TCHAN_TOES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "UDMAP0__CFG__TCHAN_TEOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the corresponding.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "UDMAP0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Tx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "UDMAP0__CFG__TCHAN_THRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from this register." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x70++0x3 line.long 0x0 "UDMAP0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be artificially.." hexmask.long.word 0x0 0.--12. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "UDMAP0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s). The fields in.." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_UDMASS_UDMAP0_CFG_RCHAN (NAVSS0_UDMAP_0_UDMASS_UDMAP0_CFG_RCHAN)" base ad:0x30C00000 rgroup.long 0x0++0x3 line.long 0x0 "UDMAP0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 15. "RX_IGNORE_SHORT,This field controls whether or not short packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Short packets are treated.." "0: Short packets are treated as exceptions and..,1: Short packets are ignored and the TR will.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline hexmask.long.byte 0x0 0.--6. 1. "RX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." rgroup.long 0x14++0x3 line.long 0x0 "UDMAP0__CFG__RCHAN_RCQ,The Rx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value TR based channel mode. This register may only be written when the channel is.." hexmask.long.word 0x0 0.--15. 1. "RXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "UDMAP0__CFG__RCHAN_ROES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "UDMAP0__CFG__RCHAN_REOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the corresponding.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "UDMAP0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Rx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "UDMAP0__CFG__RCHAN_THRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from this register." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x80++0x3 line.long 0x0 "UDMAP0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s). The fields in.." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." rgroup.long 0xF0++0x3 line.long 0x0 "UDMAP0__CFG__RCHAN_RFLOW_RNG,The flow range register is used to control which flows other than the default flow (0x3FFF / channel_number) are allowed to be used with this DMA channel." hexmask.long.word 0x0 16.--30. 1. "FLOWID_CNT,Rx Flow ID Count: This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for this channel. A value of 0 indicates that no flow IDs other than the default are allowed for the channel.." newline hexmask.long.word 0x0 0.--13. 1. "FLOWID_START,Rx Starting Flow ID: Beyond the default flow ID each channel can also make use of a single contiguous range of flow IDs and this field specifies the starting index for that range.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_UDMASS_UDMAP0_CFG_RFLOW (NAVSS0_UDMAP_0_UDMASS_UDMAP0_CFG_RFLOW)" base ad:0x30D00000 rgroup.long 0x0++0x1F line.long 0x0 "UDMAP0__CFG__RFLOW_RFA,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. The fields.." bitfld.long 0x0 30. "RX_EINFO_PRESENT,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will clear the Extended Packet Info Present bit in.." "0,1" newline bitfld.long 0x0 29. "RX_PSINFO_PRESENT,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will set the PS word count to 0 in the PD and will drop any PS words.." "0,1" newline bitfld.long 0x0 28. "RX_ERROR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor or buffer starvation occurs): 0 = Starvation errors result in dropping packet and reclaiming any used.." "0: Starvation errors result in dropping packet and..,1: Starvation errors result in subsequent re-try of.." newline bitfld.long 0x0 26.--27. "RX_DESC_TYPE,Rx Descriptor Type: This field indicates the descriptor type to use: 0 = Host 1 = RESERVED 2 = Monolithic 3 = RESERVED" "0: Host,1: RESERVED,2: Monolithic,3: RESERVED" newline bitfld.long 0x0 25. "RX_PS_LOCATION,Rx Protocol Specific Location: This bit controls where the Protocol Specific words will be placed in the Host Mode data structure. If this bit is cleared the DMA will clear the Protocol Specific Region Location bit in the PD and will.." "0,1" newline hexmask.long.word 0x0 16.--24. 1. "RX_SOP_OFFSET,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer). This value must be less than the.." newline hexmask.long.word 0x0 0.--15. 1. "RX_DEST_QNUM,Rx Destination Queue: This field indicates the default receive queue that packets on this flow should be placed onto." line.long 0x4 "UDMAP0__CFG__RFLOW_RFB,The Rx Flow N Configuration Register B contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. The fields.." hexmask.long.byte 0x4 24.--31. 1. "RX_SRC_TAG_HI,Rx Source Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 16.--23. 1. "RX_SRC_TAG_LO,Rx Source Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1." newline hexmask.long.byte 0x4 8.--15. 1. "RX_DEST_TAG_HI,Rx Destination Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 0.--7. 1. "RX_DEST_TAG_LO,Rx Destination Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1." line.long 0x8 "UDMAP0__CFG__RFLOW_RFC,The Rx Flow N Configuration Register C contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. The fields.." bitfld.long 0x8 28.--30. "RX_SRC_TAG_HI_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 24.--26. "RX_SRC_TAG_LO_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 20.--22. "RX_DEST_TAG_HI_SEL,Rx Destination Tag High Byte Selector: This field specifies the source for bits 15:8 of the destination tag field in the word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 16.--18. "RX_DEST_TAG_LO_SEL,Rx Destination Tag Low Byte Selector: This field specifies the source for bits 7:0 of the destination tag field in word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 0.--2. "RX_SIZE_THRESH_EN,Rx Packet Sized Based Free Buffer Queue Enables: These bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_threshN fields to determine which FDQ to allocate the.." "0: Do not use the threshold,1: Use the thresholds to select between the 4..,?,?,?,?,?,?" line.long 0xC "UDMAP0__CFG__RFLOW_RFD,The Rx Flow N Configuration Register D contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. The fields.." hexmask.long.word 0xC 16.--31. 1. "RX_FDQ0_SZ0_QNUM,Rx Free Descriptor 0 Queue Index - Size 0: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value." newline hexmask.long.word 0xC 0.--15. 1. "RX_FDQ1_QNUM,Rx Free Descriptor 1 Queue Index: This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet" line.long 0x10 "UDMAP0__CFG__RFLOW_RFE,The Rx Flow N Configuration Register E contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. The fields.." hexmask.long.word 0x10 16.--31. 1. "RX_FDQ2_QNUM,Rx Free Descriptor 2 Queue Index: This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet" newline hexmask.long.word 0x10 0.--15. 1. "RX_FDQ3_QNUM,Rx Free Descriptor 3 Queue Index: This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet" line.long 0x14 "UDMAP0__CFG__RFLOW_RFF,The Rx Flow N Configuration Register F contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. This.." hexmask.long.word 0x14 16.--31. 1. "RX_SIZE_THRESH0,Rx Packet Size Threshold 0: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x14 0.--15. 1. "RX_SIZE_THRESH1,Rx Packet Size Threshold 1: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is greater than the.." line.long 0x18 "UDMAP0__CFG__RFLOW_RFG,The Rx Flow N Configuration Register G contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. This.." hexmask.long.word 0x18 16.--31. 1. "RX_SIZE_THRESH2,Rx Packet Size Threshold 2: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x18 0.--15. 1. "RX_FDQ0_SZ1_QNUM,Rx Free Descriptor 0 Queue Index - Size 1: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value. This field is optional." line.long 0x1C "UDMAP0__CFG__RFLOW_RFH,The Rx Flow N Configuration Register H contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. This.." hexmask.long.word 0x1C 16.--31. 1. "RX_FDQ0_SZ2_QNUM,Rx Free Descriptor 0 Queue Index - Size 2: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size1 value. This field is optional." newline hexmask.long.word 0x1C 0.--15. 1. "RX_FDQ0_SZ3_QNUM,Rx Free Descriptor 0 Queue Index - Size 3: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size2 value. This field is optional." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_UDMASS_UDMAP0_CFG (NAVSS0_UDMAP_0_UDMASS_UDMAP0_CFG)" base ad:0x31150000 rgroup.long 0x0++0x3 line.long 0x0 "UDMAP0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "UDMAP0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the UDMA-P in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This field sets the timeout duration in clock cycles. This field controls the minimum amount of time that an Rx channel will be required to wait when it encounters a buffer starvation condition and the Rx error handling bit is set to 1.." line.long 0x4 "UDMAP0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "UDMAP0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x1C++0x3 line.long 0x0 "UDMAP0__CFG__GCFG_UTC_CTRL,The external UTC control register provides a mapping of logical to physical thread IDs ." hexmask.long.word 0x0 0.--15. 1. "UTC_CHAN_START,This field specifies the starting PSI-L thread number for the external UTC" rgroup.long 0x20++0xF line.long 0x0 "UDMAP0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this UDMA-P instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" newline bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" newline bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" newline bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "UDMAP0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this UDMA-P instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "UDMAP0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx internal channel count" hexmask.long.word 0x8 9.--17. 1. "ECHAN_CNT,Tx external channel count" hexmask.long.word 0x8 0.--8. 1. "TCHAN_CNT,Tx internal channel count" line.long 0xC "UDMAP0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,Tx ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,Tx high capacity internal channel count" hexmask.long.word 0xC 0.--13. 1. "RFLOW_CNT,Rx flow table entry count" rgroup.long 0x40++0xF line.long 0x0 "UDMAP0__CFG__GCFG_PERF0,This register provides thresholds for outstanding virtualized read/write commands from interface mem0" hexmask.long.byte 0x0 16.--23. 1. "VRD_THRESH0,Virt read command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x0 0.--7. 1. "VWR_THRESH0,Virt write command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x4 "UDMAP0__CFG__GCFG_PERF1,This register provides thresholds for outstanding virtualized read/write commands from interface mem1" hexmask.long.byte 0x4 16.--23. 1. "VRD_THRESH1,Virt read command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x4 0.--7. 1. "VWR_THRESH1,Virt write command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x8 "UDMAP0__CFG__GCFG_PERF2,This register provides thresholds for outstanding virtualized read commands from interface memr" hexmask.long.byte 0x8 16.--23. 1. "VRD_THRESH2,Virt read command throttling threshold for memr. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." line.long 0xC "UDMAP0__CFG__GCFG_PERF3,This register provides thresholds for outstanding virtualized write commands from interface memw" hexmask.long.byte 0xC 0.--7. 1. "VWR_THRESH3,Virt write command throttling threshold for memw. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." rgroup.long 0x60++0x7 line.long 0x0 "UDMAP0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x0 0.--31. 1. "NOGATE_LO,When set inhibits automatic gating of clock." line.long 0x4 "UDMAP0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x4 0.--31. 1. "NOGATE_HI,When set inhibits automatic gating of clock." rgroup.long 0x78++0xB line.long 0x0 "UDMAP0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "UDMAP0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" line.long 0x8 "UDMAP0__CFG__GCFG_RFLOWFWOES,The Rx Flow FW OES Register specifies a destination event number to which an event should be sent if an out of range flow ID is received on a packet." hexmask.long.word 0x8 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x88++0x3 line.long 0x0 "UDMAP0__CFG__GCFG_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check. Values in this register will remain persistent once an exception has been detected until the.." bitfld.long 0x0 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet. Once this bit is set the remaining fields in this register will not be modified. SW is required to write this bit to 0 to allow another.." "0,1" hexmask.long.word 0x0 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet" hexmask.long.word 0x0 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_UDMASS_UDMAP0_CFG_RCHANRT (NAVSS0_UDMAP_0_UDMASS_UDMAP0_CFG_RCHANRT)" base ad:0x34000000 rgroup.long 0x0++0x3 line.long 0x0 "UDMAP0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UDMAP0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the rx_chan_type is configured as a Third Party DMA channel. This.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "UDMAP0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "UDMAP0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "UDMAP0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was reported by the.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "UDMAP0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "UDMAP0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "UDMAP0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "UDMAP0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "UDMAP0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "UDMAP0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "UDMAP0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "UDMAP0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "UDMAP0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "UDMAP0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "UDMAP0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "UDMAP0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "UDMAP0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "UDMAP0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "UDMAP0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "UDMAP0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "UDMAP0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "UDMAP0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "UDMAP0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_UDMASS_UDMAP0_CFG_TCHANRT (NAVSS0_UDMAP_0_UDMASS_UDMAP0_CFG_TCHANRT)" base ad:0x35000000 rgroup.long 0x0++0x3 line.long 0x0 "UDMAP0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UDMAP0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA channel. This.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "UDMAP0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "UDMAP0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "UDMAP0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was reported by the.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "UDMAP0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "UDMAP0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "UDMAP0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "UDMAP0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "UDMAP0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "UDMAP0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "UDMAP0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "UDMAP0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "UDMAP0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "UDMAP0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "UDMAP0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "UDMAP0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "UDMAP0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "UDMAP0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "UDMAP0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "UDMAP0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "UDMAP0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "UDMAP0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "UDMAP0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif tree.end tree "NAVSS0_UDMAP_0_VIRT" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_0_UDMAP0_CFG_TCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_0_UDMAP0_CFG_TCHAN)" base ad:0x4B00B00000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 30. "TX_FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass extended.." "0: DMA controller will pass extended packet info..,?" newline bitfld.long 0x0 29. "TX_FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass PS words if present in.." "0: DMA controller will pass PS words if present in..,?" newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" newline hexmask.long.byte 0x0 0.--6. 1. "TX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." line.long 0x4 "VIRT_ALIAS_0_UDMAP0__CFG__TCHAN_TCREDIT,The Transfer Request Credit Register indicates how many TR sized buffer slots exist in the associated UTC channel to which this channel is associated. This register only exists for external UTC channels. This.." bitfld.long 0x4 0.--2. "COUNT,Transfer Request Credit Count: this field specifies how many credits for complete TRs are available. This field should be initialized before the channel is enabled and will then increment/decrement as TRs are submitted and responses are received." "0,1,2,3,4,5,6,7" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__TCHAN_TCQ,The Tx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value channel mode. This register may only be written when the channel.." hexmask.long.word 0x0 0.--15. 1. "TXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__TCHAN_TOES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__TCHAN_TEOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_0_UDMAP0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Tx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_0_UDMAP0__CFG__TCHAN_THRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x70++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0x0 0.--12. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_0_UDMAP0_CFG_RCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_0_UDMAP0_CFG_RCHAN)" base ad:0x4B00C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 15. "RX_IGNORE_SHORT,This field controls whether or not short packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Short packets are treated.." "0: Short packets are treated as exceptions and..,1: Short packets are ignored and the TR will.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline hexmask.long.byte 0x0 0.--6. 1. "RX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__RCHAN_RCQ,The Rx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value TR based channel mode. This register may only be written when the.." hexmask.long.word 0x0 0.--15. 1. "RXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__RCHAN_ROES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__RCHAN_REOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_0_UDMAP0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Rx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_0_UDMAP0__CFG__RCHAN_THRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." rgroup.long 0xF0++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__RCHAN_RFLOW_RNG,The flow range register is used to control which flows other than the default flow (0x3FFF / channel_number) are allowed to be used with this DMA channel." hexmask.long.word 0x0 16.--30. 1. "FLOWID_CNT,Rx Flow ID Count: This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for this channel. A value of 0 indicates that no flow IDs other than the default are allowed for the channel.." newline hexmask.long.word 0x0 0.--13. 1. "FLOWID_START,Rx Starting Flow ID: Beyond the default flow ID each channel can also make use of a single contiguous range of flow IDs and this field specifies the starting index for that range.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_0_UDMAP0_CFG_RFLOW (NAVSS0_UDMAP_0_VIRT_ALIAS_0_UDMAP0_CFG_RFLOW)" base ad:0x4B00D00000 rgroup.long 0x0++0x1F line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__RFLOW_RFA,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." bitfld.long 0x0 30. "RX_EINFO_PRESENT,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will clear the Extended Packet Info Present bit in.." "0,1" newline bitfld.long 0x0 29. "RX_PSINFO_PRESENT,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will set the PS word count to 0 in the PD and will drop any PS words.." "0,1" newline bitfld.long 0x0 28. "RX_ERROR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor or buffer starvation occurs): 0 = Starvation errors result in dropping packet and reclaiming any used.." "0: Starvation errors result in dropping packet and..,1: Starvation errors result in subsequent re-try of.." newline bitfld.long 0x0 26.--27. "RX_DESC_TYPE,Rx Descriptor Type: This field indicates the descriptor type to use: 0 = Host 1 = RESERVED 2 = Monolithic 3 = RESERVED" "0: Host,1: RESERVED,2: Monolithic,3: RESERVED" newline bitfld.long 0x0 25. "RX_PS_LOCATION,Rx Protocol Specific Location: This bit controls where the Protocol Specific words will be placed in the Host Mode data structure. If this bit is cleared the DMA will clear the Protocol Specific Region Location bit in the PD and will.." "0,1" newline hexmask.long.word 0x0 16.--24. 1. "RX_SOP_OFFSET,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer). This value must be less than the.." newline hexmask.long.word 0x0 0.--15. 1. "RX_DEST_QNUM,Rx Destination Queue: This field indicates the default receive queue that packets on this flow should be placed onto." line.long 0x4 "VIRT_ALIAS_0_UDMAP0__CFG__RFLOW_RFB,The Rx Flow N Configuration Register B contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.byte 0x4 24.--31. 1. "RX_SRC_TAG_HI,Rx Source Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 16.--23. 1. "RX_SRC_TAG_LO,Rx Source Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1." newline hexmask.long.byte 0x4 8.--15. 1. "RX_DEST_TAG_HI,Rx Destination Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 0.--7. 1. "RX_DEST_TAG_LO,Rx Destination Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1." line.long 0x8 "VIRT_ALIAS_0_UDMAP0__CFG__RFLOW_RFC,The Rx Flow N Configuration Register C contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." bitfld.long 0x8 28.--30. "RX_SRC_TAG_HI_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 24.--26. "RX_SRC_TAG_LO_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 20.--22. "RX_DEST_TAG_HI_SEL,Rx Destination Tag High Byte Selector: This field specifies the source for bits 15:8 of the destination tag field in the word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 16.--18. "RX_DEST_TAG_LO_SEL,Rx Destination Tag Low Byte Selector: This field specifies the source for bits 7:0 of the destination tag field in word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 0.--2. "RX_SIZE_THRESH_EN,Rx Packet Sized Based Free Buffer Queue Enables: These bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_threshN fields to determine which FDQ to allocate the.." "0: Do not use the threshold,1: Use the thresholds to select between the 4..,?,?,?,?,?,?" line.long 0xC "VIRT_ALIAS_0_UDMAP0__CFG__RFLOW_RFD,The Rx Flow N Configuration Register D contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0xC 16.--31. 1. "RX_FDQ0_SZ0_QNUM,Rx Free Descriptor 0 Queue Index - Size 0: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value." newline hexmask.long.word 0xC 0.--15. 1. "RX_FDQ1_QNUM,Rx Free Descriptor 1 Queue Index: This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet" line.long 0x10 "VIRT_ALIAS_0_UDMAP0__CFG__RFLOW_RFE,The Rx Flow N Configuration Register E contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x10 16.--31. 1. "RX_FDQ2_QNUM,Rx Free Descriptor 2 Queue Index: This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet" newline hexmask.long.word 0x10 0.--15. 1. "RX_FDQ3_QNUM,Rx Free Descriptor 3 Queue Index: This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet" line.long 0x14 "VIRT_ALIAS_0_UDMAP0__CFG__RFLOW_RFF,The Rx Flow N Configuration Register F contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x14 16.--31. 1. "RX_SIZE_THRESH0,Rx Packet Size Threshold 0: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x14 0.--15. 1. "RX_SIZE_THRESH1,Rx Packet Size Threshold 1: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is greater than the.." line.long 0x18 "VIRT_ALIAS_0_UDMAP0__CFG__RFLOW_RFG,The Rx Flow N Configuration Register G contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x18 16.--31. 1. "RX_SIZE_THRESH2,Rx Packet Size Threshold 2: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x18 0.--15. 1. "RX_FDQ0_SZ1_QNUM,Rx Free Descriptor 0 Queue Index - Size 1: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value. This field is optional." line.long 0x1C "VIRT_ALIAS_0_UDMAP0__CFG__RFLOW_RFH,The Rx Flow N Configuration Register H contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x1C 16.--31. 1. "RX_FDQ0_SZ2_QNUM,Rx Free Descriptor 0 Queue Index - Size 2: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size1 value. This field is optional." newline hexmask.long.word 0x1C 0.--15. 1. "RX_FDQ0_SZ3_QNUM,Rx Free Descriptor 0 Queue Index - Size 3: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size2 value. This field is optional." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_0_UDMAP0_CFG_GCFG (NAVSS0_UDMAP_0_VIRT_ALIAS_0_UDMAP0_CFG_GCFG)" base ad:0x4B01150000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the UDMA-P in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This field sets the timeout duration in clock cycles. This field controls the minimum amount of time that an Rx channel will be required to wait when it encounters a buffer starvation condition and the Rx error handling bit is set to 1.." line.long 0x4 "VIRT_ALIAS_0_UDMAP0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x1C++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__GCFG_UTC_CTRL,The external UTC control register provides a mapping of logical to physical thread IDs ." hexmask.long.word 0x0 0.--15. 1. "UTC_CHAN_START,This field specifies the starting PSI-L thread number for the external UTC" rgroup.long 0x20++0xF line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this UDMA-P instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_0_UDMAP0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this UDMA-P instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_0_UDMAP0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx internal channel count" hexmask.long.word 0x8 9.--17. 1. "ECHAN_CNT,Tx external channel count" hexmask.long.word 0x8 0.--8. 1. "TCHAN_CNT,Tx internal channel count" line.long 0xC "VIRT_ALIAS_0_UDMAP0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,Tx ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,Tx high capacity internal channel count" hexmask.long.word 0xC 0.--13. 1. "RFLOW_CNT,Rx flow table entry count" rgroup.long 0x40++0xF line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__GCFG_PERF0,This register provides thresholds for outstanding virtualized read/write commands from interface mem0" hexmask.long.byte 0x0 16.--23. 1. "VRD_THRESH0,Virt read command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x0 0.--7. 1. "VWR_THRESH0,Virt write command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x4 "VIRT_ALIAS_0_UDMAP0__CFG__GCFG_PERF1,This register provides thresholds for outstanding virtualized read/write commands from interface mem1" hexmask.long.byte 0x4 16.--23. 1. "VRD_THRESH1,Virt read command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x4 0.--7. 1. "VWR_THRESH1,Virt write command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x8 "VIRT_ALIAS_0_UDMAP0__CFG__GCFG_PERF2,This register provides thresholds for outstanding virtualized read commands from interface memr" hexmask.long.byte 0x8 16.--23. 1. "VRD_THRESH2,Virt read command throttling threshold for memr. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." line.long 0xC "VIRT_ALIAS_0_UDMAP0__CFG__GCFG_PERF3,This register provides thresholds for outstanding virtualized write commands from interface memw" hexmask.long.byte 0xC 0.--7. 1. "VWR_THRESH3,Virt write command throttling threshold for memw. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x0 0.--31. 1. "NOGATE_LO,When set inhibits automatic gating of clock." line.long 0x4 "VIRT_ALIAS_0_UDMAP0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x4 0.--31. 1. "NOGATE_HI,When set inhibits automatic gating of clock." rgroup.long 0x78++0xB line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_0_UDMAP0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" line.long 0x8 "VIRT_ALIAS_0_UDMAP0__CFG__GCFG_RFLOWFWOES,The Rx Flow FW OES Register specifies a destination event number to which an event should be sent if an out of range flow ID is received on a packet." hexmask.long.word 0x8 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__GCFG_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check. Values in this register will remain persistent once an exception has been detected.." bitfld.long 0x0 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet. Once this bit is set the remaining fields in this register will not be modified. SW is required to write this bit to 0 to allow another.." "0,1" hexmask.long.word 0x0 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet" hexmask.long.word 0x0 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_0_UDMAP0_CFG_RCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_0_UDMAP0_CFG_RCHANRT)" base ad:0x4B04000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the rx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_0_UDMAP0_CFG_TCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_0_UDMAP0_CFG_TCHANRT)" base ad:0x4B05000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_0_UDMAP0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_1_UDMAP0_CFG_TCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_1_UDMAP0_CFG_TCHAN)" base ad:0x4B10B00000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 30. "TX_FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass extended.." "0: DMA controller will pass extended packet info..,?" newline bitfld.long 0x0 29. "TX_FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass PS words if present in.." "0: DMA controller will pass PS words if present in..,?" newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" newline hexmask.long.byte 0x0 0.--6. 1. "TX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." line.long 0x4 "VIRT_ALIAS_1_UDMAP0__CFG__TCHAN_TCREDIT,The Transfer Request Credit Register indicates how many TR sized buffer slots exist in the associated UTC channel to which this channel is associated. This register only exists for external UTC channels. This.." bitfld.long 0x4 0.--2. "COUNT,Transfer Request Credit Count: this field specifies how many credits for complete TRs are available. This field should be initialized before the channel is enabled and will then increment/decrement as TRs are submitted and responses are received." "0,1,2,3,4,5,6,7" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__TCHAN_TCQ,The Tx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value channel mode. This register may only be written when the channel.." hexmask.long.word 0x0 0.--15. 1. "TXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__TCHAN_TOES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__TCHAN_TEOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_1_UDMAP0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Tx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_1_UDMAP0__CFG__TCHAN_THRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x70++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0x0 0.--12. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_1_UDMAP0_CFG_RCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_1_UDMAP0_CFG_RCHAN)" base ad:0x4B10C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 15. "RX_IGNORE_SHORT,This field controls whether or not short packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Short packets are treated.." "0: Short packets are treated as exceptions and..,1: Short packets are ignored and the TR will.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline hexmask.long.byte 0x0 0.--6. 1. "RX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__RCHAN_RCQ,The Rx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value TR based channel mode. This register may only be written when the.." hexmask.long.word 0x0 0.--15. 1. "RXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__RCHAN_ROES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__RCHAN_REOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_1_UDMAP0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Rx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_1_UDMAP0__CFG__RCHAN_THRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." rgroup.long 0xF0++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__RCHAN_RFLOW_RNG,The flow range register is used to control which flows other than the default flow (0x3FFF / channel_number) are allowed to be used with this DMA channel." hexmask.long.word 0x0 16.--30. 1. "FLOWID_CNT,Rx Flow ID Count: This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for this channel. A value of 0 indicates that no flow IDs other than the default are allowed for the channel.." newline hexmask.long.word 0x0 0.--13. 1. "FLOWID_START,Rx Starting Flow ID: Beyond the default flow ID each channel can also make use of a single contiguous range of flow IDs and this field specifies the starting index for that range.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_1_UDMAP0_CFG_RFLOW (NAVSS0_UDMAP_0_VIRT_ALIAS_1_UDMAP0_CFG_RFLOW)" base ad:0x4B10D00000 rgroup.long 0x0++0x1F line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__RFLOW_RFA,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." bitfld.long 0x0 30. "RX_EINFO_PRESENT,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will clear the Extended Packet Info Present bit in.." "0,1" newline bitfld.long 0x0 29. "RX_PSINFO_PRESENT,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will set the PS word count to 0 in the PD and will drop any PS words.." "0,1" newline bitfld.long 0x0 28. "RX_ERROR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor or buffer starvation occurs): 0 = Starvation errors result in dropping packet and reclaiming any used.." "0: Starvation errors result in dropping packet and..,1: Starvation errors result in subsequent re-try of.." newline bitfld.long 0x0 26.--27. "RX_DESC_TYPE,Rx Descriptor Type: This field indicates the descriptor type to use: 0 = Host 1 = RESERVED 2 = Monolithic 3 = RESERVED" "0: Host,1: RESERVED,2: Monolithic,3: RESERVED" newline bitfld.long 0x0 25. "RX_PS_LOCATION,Rx Protocol Specific Location: This bit controls where the Protocol Specific words will be placed in the Host Mode data structure. If this bit is cleared the DMA will clear the Protocol Specific Region Location bit in the PD and will.." "0,1" newline hexmask.long.word 0x0 16.--24. 1. "RX_SOP_OFFSET,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer). This value must be less than the.." newline hexmask.long.word 0x0 0.--15. 1. "RX_DEST_QNUM,Rx Destination Queue: This field indicates the default receive queue that packets on this flow should be placed onto." line.long 0x4 "VIRT_ALIAS_1_UDMAP0__CFG__RFLOW_RFB,The Rx Flow N Configuration Register B contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.byte 0x4 24.--31. 1. "RX_SRC_TAG_HI,Rx Source Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 16.--23. 1. "RX_SRC_TAG_LO,Rx Source Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1." newline hexmask.long.byte 0x4 8.--15. 1. "RX_DEST_TAG_HI,Rx Destination Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 0.--7. 1. "RX_DEST_TAG_LO,Rx Destination Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1." line.long 0x8 "VIRT_ALIAS_1_UDMAP0__CFG__RFLOW_RFC,The Rx Flow N Configuration Register C contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." bitfld.long 0x8 28.--30. "RX_SRC_TAG_HI_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 24.--26. "RX_SRC_TAG_LO_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 20.--22. "RX_DEST_TAG_HI_SEL,Rx Destination Tag High Byte Selector: This field specifies the source for bits 15:8 of the destination tag field in the word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 16.--18. "RX_DEST_TAG_LO_SEL,Rx Destination Tag Low Byte Selector: This field specifies the source for bits 7:0 of the destination tag field in word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 0.--2. "RX_SIZE_THRESH_EN,Rx Packet Sized Based Free Buffer Queue Enables: These bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_threshN fields to determine which FDQ to allocate the.." "0: Do not use the threshold,1: Use the thresholds to select between the 4..,?,?,?,?,?,?" line.long 0xC "VIRT_ALIAS_1_UDMAP0__CFG__RFLOW_RFD,The Rx Flow N Configuration Register D contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0xC 16.--31. 1. "RX_FDQ0_SZ0_QNUM,Rx Free Descriptor 0 Queue Index - Size 0: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value." newline hexmask.long.word 0xC 0.--15. 1. "RX_FDQ1_QNUM,Rx Free Descriptor 1 Queue Index: This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet" line.long 0x10 "VIRT_ALIAS_1_UDMAP0__CFG__RFLOW_RFE,The Rx Flow N Configuration Register E contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x10 16.--31. 1. "RX_FDQ2_QNUM,Rx Free Descriptor 2 Queue Index: This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet" newline hexmask.long.word 0x10 0.--15. 1. "RX_FDQ3_QNUM,Rx Free Descriptor 3 Queue Index: This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet" line.long 0x14 "VIRT_ALIAS_1_UDMAP0__CFG__RFLOW_RFF,The Rx Flow N Configuration Register F contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x14 16.--31. 1. "RX_SIZE_THRESH0,Rx Packet Size Threshold 0: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x14 0.--15. 1. "RX_SIZE_THRESH1,Rx Packet Size Threshold 1: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is greater than the.." line.long 0x18 "VIRT_ALIAS_1_UDMAP0__CFG__RFLOW_RFG,The Rx Flow N Configuration Register G contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x18 16.--31. 1. "RX_SIZE_THRESH2,Rx Packet Size Threshold 2: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x18 0.--15. 1. "RX_FDQ0_SZ1_QNUM,Rx Free Descriptor 0 Queue Index - Size 1: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value. This field is optional." line.long 0x1C "VIRT_ALIAS_1_UDMAP0__CFG__RFLOW_RFH,The Rx Flow N Configuration Register H contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x1C 16.--31. 1. "RX_FDQ0_SZ2_QNUM,Rx Free Descriptor 0 Queue Index - Size 2: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size1 value. This field is optional." newline hexmask.long.word 0x1C 0.--15. 1. "RX_FDQ0_SZ3_QNUM,Rx Free Descriptor 0 Queue Index - Size 3: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size2 value. This field is optional." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_1_UDMAP0_CFG_GCFG (NAVSS0_UDMAP_0_VIRT_ALIAS_1_UDMAP0_CFG_GCFG)" base ad:0x4B11150000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the UDMA-P in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This field sets the timeout duration in clock cycles. This field controls the minimum amount of time that an Rx channel will be required to wait when it encounters a buffer starvation condition and the Rx error handling bit is set to 1.." line.long 0x4 "VIRT_ALIAS_1_UDMAP0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x1C++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__GCFG_UTC_CTRL,The external UTC control register provides a mapping of logical to physical thread IDs ." hexmask.long.word 0x0 0.--15. 1. "UTC_CHAN_START,This field specifies the starting PSI-L thread number for the external UTC" rgroup.long 0x20++0xF line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this UDMA-P instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_1_UDMAP0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this UDMA-P instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_1_UDMAP0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx internal channel count" hexmask.long.word 0x8 9.--17. 1. "ECHAN_CNT,Tx external channel count" hexmask.long.word 0x8 0.--8. 1. "TCHAN_CNT,Tx internal channel count" line.long 0xC "VIRT_ALIAS_1_UDMAP0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,Tx ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,Tx high capacity internal channel count" hexmask.long.word 0xC 0.--13. 1. "RFLOW_CNT,Rx flow table entry count" rgroup.long 0x40++0xF line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__GCFG_PERF0,This register provides thresholds for outstanding virtualized read/write commands from interface mem0" hexmask.long.byte 0x0 16.--23. 1. "VRD_THRESH0,Virt read command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x0 0.--7. 1. "VWR_THRESH0,Virt write command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x4 "VIRT_ALIAS_1_UDMAP0__CFG__GCFG_PERF1,This register provides thresholds for outstanding virtualized read/write commands from interface mem1" hexmask.long.byte 0x4 16.--23. 1. "VRD_THRESH1,Virt read command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x4 0.--7. 1. "VWR_THRESH1,Virt write command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x8 "VIRT_ALIAS_1_UDMAP0__CFG__GCFG_PERF2,This register provides thresholds for outstanding virtualized read commands from interface memr" hexmask.long.byte 0x8 16.--23. 1. "VRD_THRESH2,Virt read command throttling threshold for memr. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." line.long 0xC "VIRT_ALIAS_1_UDMAP0__CFG__GCFG_PERF3,This register provides thresholds for outstanding virtualized write commands from interface memw" hexmask.long.byte 0xC 0.--7. 1. "VWR_THRESH3,Virt write command throttling threshold for memw. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x0 0.--31. 1. "NOGATE_LO,When set inhibits automatic gating of clock." line.long 0x4 "VIRT_ALIAS_1_UDMAP0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x4 0.--31. 1. "NOGATE_HI,When set inhibits automatic gating of clock." rgroup.long 0x78++0xB line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_1_UDMAP0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" line.long 0x8 "VIRT_ALIAS_1_UDMAP0__CFG__GCFG_RFLOWFWOES,The Rx Flow FW OES Register specifies a destination event number to which an event should be sent if an out of range flow ID is received on a packet." hexmask.long.word 0x8 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__GCFG_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check. Values in this register will remain persistent once an exception has been detected.." bitfld.long 0x0 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet. Once this bit is set the remaining fields in this register will not be modified. SW is required to write this bit to 0 to allow another.." "0,1" hexmask.long.word 0x0 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet" hexmask.long.word 0x0 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_1_UDMAP0_CFG_RCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_1_UDMAP0_CFG_RCHANRT)" base ad:0x4B14000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the rx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_1_UDMAP0_CFG_TCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_1_UDMAP0_CFG_TCHANRT)" base ad:0x4B15000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_1_UDMAP0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_2_UDMAP0_CFG_TCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_2_UDMAP0_CFG_TCHAN)" base ad:0x4B20B00000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 30. "TX_FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass extended.." "0: DMA controller will pass extended packet info..,?" newline bitfld.long 0x0 29. "TX_FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass PS words if present in.." "0: DMA controller will pass PS words if present in..,?" newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" newline hexmask.long.byte 0x0 0.--6. 1. "TX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." line.long 0x4 "VIRT_ALIAS_2_UDMAP0__CFG__TCHAN_TCREDIT,The Transfer Request Credit Register indicates how many TR sized buffer slots exist in the associated UTC channel to which this channel is associated. This register only exists for external UTC channels. This.." bitfld.long 0x4 0.--2. "COUNT,Transfer Request Credit Count: this field specifies how many credits for complete TRs are available. This field should be initialized before the channel is enabled and will then increment/decrement as TRs are submitted and responses are received." "0,1,2,3,4,5,6,7" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__TCHAN_TCQ,The Tx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value channel mode. This register may only be written when the channel.." hexmask.long.word 0x0 0.--15. 1. "TXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__TCHAN_TOES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__TCHAN_TEOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_2_UDMAP0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Tx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_2_UDMAP0__CFG__TCHAN_THRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x70++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0x0 0.--12. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_2_UDMAP0_CFG_RCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_2_UDMAP0_CFG_RCHAN)" base ad:0x4B20C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 15. "RX_IGNORE_SHORT,This field controls whether or not short packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Short packets are treated.." "0: Short packets are treated as exceptions and..,1: Short packets are ignored and the TR will.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline hexmask.long.byte 0x0 0.--6. 1. "RX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__RCHAN_RCQ,The Rx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value TR based channel mode. This register may only be written when the.." hexmask.long.word 0x0 0.--15. 1. "RXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__RCHAN_ROES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__RCHAN_REOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_2_UDMAP0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Rx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_2_UDMAP0__CFG__RCHAN_THRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." rgroup.long 0xF0++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__RCHAN_RFLOW_RNG,The flow range register is used to control which flows other than the default flow (0x3FFF / channel_number) are allowed to be used with this DMA channel." hexmask.long.word 0x0 16.--30. 1. "FLOWID_CNT,Rx Flow ID Count: This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for this channel. A value of 0 indicates that no flow IDs other than the default are allowed for the channel.." newline hexmask.long.word 0x0 0.--13. 1. "FLOWID_START,Rx Starting Flow ID: Beyond the default flow ID each channel can also make use of a single contiguous range of flow IDs and this field specifies the starting index for that range.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_2_UDMAP0_CFG_RFLOW (NAVSS0_UDMAP_0_VIRT_ALIAS_2_UDMAP0_CFG_RFLOW)" base ad:0x4B20D00000 rgroup.long 0x0++0x1F line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__RFLOW_RFA,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." bitfld.long 0x0 30. "RX_EINFO_PRESENT,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will clear the Extended Packet Info Present bit in.." "0,1" newline bitfld.long 0x0 29. "RX_PSINFO_PRESENT,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will set the PS word count to 0 in the PD and will drop any PS words.." "0,1" newline bitfld.long 0x0 28. "RX_ERROR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor or buffer starvation occurs): 0 = Starvation errors result in dropping packet and reclaiming any used.." "0: Starvation errors result in dropping packet and..,1: Starvation errors result in subsequent re-try of.." newline bitfld.long 0x0 26.--27. "RX_DESC_TYPE,Rx Descriptor Type: This field indicates the descriptor type to use: 0 = Host 1 = RESERVED 2 = Monolithic 3 = RESERVED" "0: Host,1: RESERVED,2: Monolithic,3: RESERVED" newline bitfld.long 0x0 25. "RX_PS_LOCATION,Rx Protocol Specific Location: This bit controls where the Protocol Specific words will be placed in the Host Mode data structure. If this bit is cleared the DMA will clear the Protocol Specific Region Location bit in the PD and will.." "0,1" newline hexmask.long.word 0x0 16.--24. 1. "RX_SOP_OFFSET,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer). This value must be less than the.." newline hexmask.long.word 0x0 0.--15. 1. "RX_DEST_QNUM,Rx Destination Queue: This field indicates the default receive queue that packets on this flow should be placed onto." line.long 0x4 "VIRT_ALIAS_2_UDMAP0__CFG__RFLOW_RFB,The Rx Flow N Configuration Register B contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.byte 0x4 24.--31. 1. "RX_SRC_TAG_HI,Rx Source Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 16.--23. 1. "RX_SRC_TAG_LO,Rx Source Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1." newline hexmask.long.byte 0x4 8.--15. 1. "RX_DEST_TAG_HI,Rx Destination Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 0.--7. 1. "RX_DEST_TAG_LO,Rx Destination Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1." line.long 0x8 "VIRT_ALIAS_2_UDMAP0__CFG__RFLOW_RFC,The Rx Flow N Configuration Register C contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." bitfld.long 0x8 28.--30. "RX_SRC_TAG_HI_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 24.--26. "RX_SRC_TAG_LO_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 20.--22. "RX_DEST_TAG_HI_SEL,Rx Destination Tag High Byte Selector: This field specifies the source for bits 15:8 of the destination tag field in the word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 16.--18. "RX_DEST_TAG_LO_SEL,Rx Destination Tag Low Byte Selector: This field specifies the source for bits 7:0 of the destination tag field in word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 0.--2. "RX_SIZE_THRESH_EN,Rx Packet Sized Based Free Buffer Queue Enables: These bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_threshN fields to determine which FDQ to allocate the.." "0: Do not use the threshold,1: Use the thresholds to select between the 4..,?,?,?,?,?,?" line.long 0xC "VIRT_ALIAS_2_UDMAP0__CFG__RFLOW_RFD,The Rx Flow N Configuration Register D contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0xC 16.--31. 1. "RX_FDQ0_SZ0_QNUM,Rx Free Descriptor 0 Queue Index - Size 0: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value." newline hexmask.long.word 0xC 0.--15. 1. "RX_FDQ1_QNUM,Rx Free Descriptor 1 Queue Index: This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet" line.long 0x10 "VIRT_ALIAS_2_UDMAP0__CFG__RFLOW_RFE,The Rx Flow N Configuration Register E contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x10 16.--31. 1. "RX_FDQ2_QNUM,Rx Free Descriptor 2 Queue Index: This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet" newline hexmask.long.word 0x10 0.--15. 1. "RX_FDQ3_QNUM,Rx Free Descriptor 3 Queue Index: This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet" line.long 0x14 "VIRT_ALIAS_2_UDMAP0__CFG__RFLOW_RFF,The Rx Flow N Configuration Register F contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x14 16.--31. 1. "RX_SIZE_THRESH0,Rx Packet Size Threshold 0: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x14 0.--15. 1. "RX_SIZE_THRESH1,Rx Packet Size Threshold 1: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is greater than the.." line.long 0x18 "VIRT_ALIAS_2_UDMAP0__CFG__RFLOW_RFG,The Rx Flow N Configuration Register G contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x18 16.--31. 1. "RX_SIZE_THRESH2,Rx Packet Size Threshold 2: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x18 0.--15. 1. "RX_FDQ0_SZ1_QNUM,Rx Free Descriptor 0 Queue Index - Size 1: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value. This field is optional." line.long 0x1C "VIRT_ALIAS_2_UDMAP0__CFG__RFLOW_RFH,The Rx Flow N Configuration Register H contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x1C 16.--31. 1. "RX_FDQ0_SZ2_QNUM,Rx Free Descriptor 0 Queue Index - Size 2: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size1 value. This field is optional." newline hexmask.long.word 0x1C 0.--15. 1. "RX_FDQ0_SZ3_QNUM,Rx Free Descriptor 0 Queue Index - Size 3: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size2 value. This field is optional." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_2_UDMAP0_CFG_GCFG (NAVSS0_UDMAP_0_VIRT_ALIAS_2_UDMAP0_CFG_GCFG)" base ad:0x4B21150000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the UDMA-P in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This field sets the timeout duration in clock cycles. This field controls the minimum amount of time that an Rx channel will be required to wait when it encounters a buffer starvation condition and the Rx error handling bit is set to 1.." line.long 0x4 "VIRT_ALIAS_2_UDMAP0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x1C++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__GCFG_UTC_CTRL,The external UTC control register provides a mapping of logical to physical thread IDs ." hexmask.long.word 0x0 0.--15. 1. "UTC_CHAN_START,This field specifies the starting PSI-L thread number for the external UTC" rgroup.long 0x20++0xF line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this UDMA-P instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_2_UDMAP0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this UDMA-P instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_2_UDMAP0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx internal channel count" hexmask.long.word 0x8 9.--17. 1. "ECHAN_CNT,Tx external channel count" hexmask.long.word 0x8 0.--8. 1. "TCHAN_CNT,Tx internal channel count" line.long 0xC "VIRT_ALIAS_2_UDMAP0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,Tx ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,Tx high capacity internal channel count" hexmask.long.word 0xC 0.--13. 1. "RFLOW_CNT,Rx flow table entry count" rgroup.long 0x40++0xF line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__GCFG_PERF0,This register provides thresholds for outstanding virtualized read/write commands from interface mem0" hexmask.long.byte 0x0 16.--23. 1. "VRD_THRESH0,Virt read command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x0 0.--7. 1. "VWR_THRESH0,Virt write command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x4 "VIRT_ALIAS_2_UDMAP0__CFG__GCFG_PERF1,This register provides thresholds for outstanding virtualized read/write commands from interface mem1" hexmask.long.byte 0x4 16.--23. 1. "VRD_THRESH1,Virt read command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x4 0.--7. 1. "VWR_THRESH1,Virt write command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x8 "VIRT_ALIAS_2_UDMAP0__CFG__GCFG_PERF2,This register provides thresholds for outstanding virtualized read commands from interface memr" hexmask.long.byte 0x8 16.--23. 1. "VRD_THRESH2,Virt read command throttling threshold for memr. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." line.long 0xC "VIRT_ALIAS_2_UDMAP0__CFG__GCFG_PERF3,This register provides thresholds for outstanding virtualized write commands from interface memw" hexmask.long.byte 0xC 0.--7. 1. "VWR_THRESH3,Virt write command throttling threshold for memw. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x0 0.--31. 1. "NOGATE_LO,When set inhibits automatic gating of clock." line.long 0x4 "VIRT_ALIAS_2_UDMAP0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x4 0.--31. 1. "NOGATE_HI,When set inhibits automatic gating of clock." rgroup.long 0x78++0xB line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_2_UDMAP0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" line.long 0x8 "VIRT_ALIAS_2_UDMAP0__CFG__GCFG_RFLOWFWOES,The Rx Flow FW OES Register specifies a destination event number to which an event should be sent if an out of range flow ID is received on a packet." hexmask.long.word 0x8 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__GCFG_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check. Values in this register will remain persistent once an exception has been detected.." bitfld.long 0x0 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet. Once this bit is set the remaining fields in this register will not be modified. SW is required to write this bit to 0 to allow another.." "0,1" hexmask.long.word 0x0 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet" hexmask.long.word 0x0 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_2_UDMAP0_CFG_RCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_2_UDMAP0_CFG_RCHANRT)" base ad:0x4B24000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the rx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_2_UDMAP0_CFG_TCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_2_UDMAP0_CFG_TCHANRT)" base ad:0x4B25000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_2_UDMAP0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_3_UDMAP0_CFG_TCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_3_UDMAP0_CFG_TCHAN)" base ad:0x4B30B00000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 30. "TX_FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass extended.." "0: DMA controller will pass extended packet info..,?" newline bitfld.long 0x0 29. "TX_FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass PS words if present in.." "0: DMA controller will pass PS words if present in..,?" newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" newline hexmask.long.byte 0x0 0.--6. 1. "TX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." line.long 0x4 "VIRT_ALIAS_3_UDMAP0__CFG__TCHAN_TCREDIT,The Transfer Request Credit Register indicates how many TR sized buffer slots exist in the associated UTC channel to which this channel is associated. This register only exists for external UTC channels. This.." bitfld.long 0x4 0.--2. "COUNT,Transfer Request Credit Count: this field specifies how many credits for complete TRs are available. This field should be initialized before the channel is enabled and will then increment/decrement as TRs are submitted and responses are received." "0,1,2,3,4,5,6,7" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__TCHAN_TCQ,The Tx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value channel mode. This register may only be written when the channel.." hexmask.long.word 0x0 0.--15. 1. "TXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__TCHAN_TOES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__TCHAN_TEOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_3_UDMAP0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Tx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_3_UDMAP0__CFG__TCHAN_THRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x70++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0x0 0.--12. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_3_UDMAP0_CFG_RCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_3_UDMAP0_CFG_RCHAN)" base ad:0x4B30C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 15. "RX_IGNORE_SHORT,This field controls whether or not short packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Short packets are treated.." "0: Short packets are treated as exceptions and..,1: Short packets are ignored and the TR will.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline hexmask.long.byte 0x0 0.--6. 1. "RX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__RCHAN_RCQ,The Rx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value TR based channel mode. This register may only be written when the.." hexmask.long.word 0x0 0.--15. 1. "RXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__RCHAN_ROES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__RCHAN_REOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_3_UDMAP0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Rx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_3_UDMAP0__CFG__RCHAN_THRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." rgroup.long 0xF0++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__RCHAN_RFLOW_RNG,The flow range register is used to control which flows other than the default flow (0x3FFF / channel_number) are allowed to be used with this DMA channel." hexmask.long.word 0x0 16.--30. 1. "FLOWID_CNT,Rx Flow ID Count: This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for this channel. A value of 0 indicates that no flow IDs other than the default are allowed for the channel.." newline hexmask.long.word 0x0 0.--13. 1. "FLOWID_START,Rx Starting Flow ID: Beyond the default flow ID each channel can also make use of a single contiguous range of flow IDs and this field specifies the starting index for that range.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_3_UDMAP0_CFG_RFLOW (NAVSS0_UDMAP_0_VIRT_ALIAS_3_UDMAP0_CFG_RFLOW)" base ad:0x4B30D00000 rgroup.long 0x0++0x1F line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__RFLOW_RFA,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." bitfld.long 0x0 30. "RX_EINFO_PRESENT,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will clear the Extended Packet Info Present bit in.." "0,1" newline bitfld.long 0x0 29. "RX_PSINFO_PRESENT,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will set the PS word count to 0 in the PD and will drop any PS words.." "0,1" newline bitfld.long 0x0 28. "RX_ERROR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor or buffer starvation occurs): 0 = Starvation errors result in dropping packet and reclaiming any used.." "0: Starvation errors result in dropping packet and..,1: Starvation errors result in subsequent re-try of.." newline bitfld.long 0x0 26.--27. "RX_DESC_TYPE,Rx Descriptor Type: This field indicates the descriptor type to use: 0 = Host 1 = RESERVED 2 = Monolithic 3 = RESERVED" "0: Host,1: RESERVED,2: Monolithic,3: RESERVED" newline bitfld.long 0x0 25. "RX_PS_LOCATION,Rx Protocol Specific Location: This bit controls where the Protocol Specific words will be placed in the Host Mode data structure. If this bit is cleared the DMA will clear the Protocol Specific Region Location bit in the PD and will.." "0,1" newline hexmask.long.word 0x0 16.--24. 1. "RX_SOP_OFFSET,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer). This value must be less than the.." newline hexmask.long.word 0x0 0.--15. 1. "RX_DEST_QNUM,Rx Destination Queue: This field indicates the default receive queue that packets on this flow should be placed onto." line.long 0x4 "VIRT_ALIAS_3_UDMAP0__CFG__RFLOW_RFB,The Rx Flow N Configuration Register B contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.byte 0x4 24.--31. 1. "RX_SRC_TAG_HI,Rx Source Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 16.--23. 1. "RX_SRC_TAG_LO,Rx Source Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1." newline hexmask.long.byte 0x4 8.--15. 1. "RX_DEST_TAG_HI,Rx Destination Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 0.--7. 1. "RX_DEST_TAG_LO,Rx Destination Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1." line.long 0x8 "VIRT_ALIAS_3_UDMAP0__CFG__RFLOW_RFC,The Rx Flow N Configuration Register C contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." bitfld.long 0x8 28.--30. "RX_SRC_TAG_HI_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 24.--26. "RX_SRC_TAG_LO_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 20.--22. "RX_DEST_TAG_HI_SEL,Rx Destination Tag High Byte Selector: This field specifies the source for bits 15:8 of the destination tag field in the word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 16.--18. "RX_DEST_TAG_LO_SEL,Rx Destination Tag Low Byte Selector: This field specifies the source for bits 7:0 of the destination tag field in word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 0.--2. "RX_SIZE_THRESH_EN,Rx Packet Sized Based Free Buffer Queue Enables: These bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_threshN fields to determine which FDQ to allocate the.." "0: Do not use the threshold,1: Use the thresholds to select between the 4..,?,?,?,?,?,?" line.long 0xC "VIRT_ALIAS_3_UDMAP0__CFG__RFLOW_RFD,The Rx Flow N Configuration Register D contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0xC 16.--31. 1. "RX_FDQ0_SZ0_QNUM,Rx Free Descriptor 0 Queue Index - Size 0: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value." newline hexmask.long.word 0xC 0.--15. 1. "RX_FDQ1_QNUM,Rx Free Descriptor 1 Queue Index: This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet" line.long 0x10 "VIRT_ALIAS_3_UDMAP0__CFG__RFLOW_RFE,The Rx Flow N Configuration Register E contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x10 16.--31. 1. "RX_FDQ2_QNUM,Rx Free Descriptor 2 Queue Index: This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet" newline hexmask.long.word 0x10 0.--15. 1. "RX_FDQ3_QNUM,Rx Free Descriptor 3 Queue Index: This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet" line.long 0x14 "VIRT_ALIAS_3_UDMAP0__CFG__RFLOW_RFF,The Rx Flow N Configuration Register F contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x14 16.--31. 1. "RX_SIZE_THRESH0,Rx Packet Size Threshold 0: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x14 0.--15. 1. "RX_SIZE_THRESH1,Rx Packet Size Threshold 1: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is greater than the.." line.long 0x18 "VIRT_ALIAS_3_UDMAP0__CFG__RFLOW_RFG,The Rx Flow N Configuration Register G contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x18 16.--31. 1. "RX_SIZE_THRESH2,Rx Packet Size Threshold 2: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x18 0.--15. 1. "RX_FDQ0_SZ1_QNUM,Rx Free Descriptor 0 Queue Index - Size 1: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value. This field is optional." line.long 0x1C "VIRT_ALIAS_3_UDMAP0__CFG__RFLOW_RFH,The Rx Flow N Configuration Register H contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x1C 16.--31. 1. "RX_FDQ0_SZ2_QNUM,Rx Free Descriptor 0 Queue Index - Size 2: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size1 value. This field is optional." newline hexmask.long.word 0x1C 0.--15. 1. "RX_FDQ0_SZ3_QNUM,Rx Free Descriptor 0 Queue Index - Size 3: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size2 value. This field is optional." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_3_UDMAP0_CFG_GCFG (NAVSS0_UDMAP_0_VIRT_ALIAS_3_UDMAP0_CFG_GCFG)" base ad:0x4B31150000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the UDMA-P in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This field sets the timeout duration in clock cycles. This field controls the minimum amount of time that an Rx channel will be required to wait when it encounters a buffer starvation condition and the Rx error handling bit is set to 1.." line.long 0x4 "VIRT_ALIAS_3_UDMAP0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x1C++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__GCFG_UTC_CTRL,The external UTC control register provides a mapping of logical to physical thread IDs ." hexmask.long.word 0x0 0.--15. 1. "UTC_CHAN_START,This field specifies the starting PSI-L thread number for the external UTC" rgroup.long 0x20++0xF line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this UDMA-P instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_3_UDMAP0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this UDMA-P instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_3_UDMAP0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx internal channel count" hexmask.long.word 0x8 9.--17. 1. "ECHAN_CNT,Tx external channel count" hexmask.long.word 0x8 0.--8. 1. "TCHAN_CNT,Tx internal channel count" line.long 0xC "VIRT_ALIAS_3_UDMAP0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,Tx ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,Tx high capacity internal channel count" hexmask.long.word 0xC 0.--13. 1. "RFLOW_CNT,Rx flow table entry count" rgroup.long 0x40++0xF line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__GCFG_PERF0,This register provides thresholds for outstanding virtualized read/write commands from interface mem0" hexmask.long.byte 0x0 16.--23. 1. "VRD_THRESH0,Virt read command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x0 0.--7. 1. "VWR_THRESH0,Virt write command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x4 "VIRT_ALIAS_3_UDMAP0__CFG__GCFG_PERF1,This register provides thresholds for outstanding virtualized read/write commands from interface mem1" hexmask.long.byte 0x4 16.--23. 1. "VRD_THRESH1,Virt read command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x4 0.--7. 1. "VWR_THRESH1,Virt write command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x8 "VIRT_ALIAS_3_UDMAP0__CFG__GCFG_PERF2,This register provides thresholds for outstanding virtualized read commands from interface memr" hexmask.long.byte 0x8 16.--23. 1. "VRD_THRESH2,Virt read command throttling threshold for memr. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." line.long 0xC "VIRT_ALIAS_3_UDMAP0__CFG__GCFG_PERF3,This register provides thresholds for outstanding virtualized write commands from interface memw" hexmask.long.byte 0xC 0.--7. 1. "VWR_THRESH3,Virt write command throttling threshold for memw. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x0 0.--31. 1. "NOGATE_LO,When set inhibits automatic gating of clock." line.long 0x4 "VIRT_ALIAS_3_UDMAP0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x4 0.--31. 1. "NOGATE_HI,When set inhibits automatic gating of clock." rgroup.long 0x78++0xB line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_3_UDMAP0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" line.long 0x8 "VIRT_ALIAS_3_UDMAP0__CFG__GCFG_RFLOWFWOES,The Rx Flow FW OES Register specifies a destination event number to which an event should be sent if an out of range flow ID is received on a packet." hexmask.long.word 0x8 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__GCFG_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check. Values in this register will remain persistent once an exception has been detected.." bitfld.long 0x0 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet. Once this bit is set the remaining fields in this register will not be modified. SW is required to write this bit to 0 to allow another.." "0,1" hexmask.long.word 0x0 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet" hexmask.long.word 0x0 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_3_UDMAP0_CFG_RCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_3_UDMAP0_CFG_RCHANRT)" base ad:0x4B34000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the rx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_3_UDMAP0_CFG_TCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_3_UDMAP0_CFG_TCHANRT)" base ad:0x4B35000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_3_UDMAP0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_4_UDMAP0_CFG_TCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_4_UDMAP0_CFG_TCHAN)" base ad:0x4B40B00000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 30. "TX_FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass extended.." "0: DMA controller will pass extended packet info..,?" newline bitfld.long 0x0 29. "TX_FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass PS words if present in.." "0: DMA controller will pass PS words if present in..,?" newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" newline hexmask.long.byte 0x0 0.--6. 1. "TX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." line.long 0x4 "VIRT_ALIAS_4_UDMAP0__CFG__TCHAN_TCREDIT,The Transfer Request Credit Register indicates how many TR sized buffer slots exist in the associated UTC channel to which this channel is associated. This register only exists for external UTC channels. This.." bitfld.long 0x4 0.--2. "COUNT,Transfer Request Credit Count: this field specifies how many credits for complete TRs are available. This field should be initialized before the channel is enabled and will then increment/decrement as TRs are submitted and responses are received." "0,1,2,3,4,5,6,7" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__TCHAN_TCQ,The Tx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value channel mode. This register may only be written when the channel.." hexmask.long.word 0x0 0.--15. 1. "TXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__TCHAN_TOES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__TCHAN_TEOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_4_UDMAP0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Tx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_4_UDMAP0__CFG__TCHAN_THRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x70++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0x0 0.--12. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_4_UDMAP0_CFG_RCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_4_UDMAP0_CFG_RCHAN)" base ad:0x4B40C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 15. "RX_IGNORE_SHORT,This field controls whether or not short packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Short packets are treated.." "0: Short packets are treated as exceptions and..,1: Short packets are ignored and the TR will.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline hexmask.long.byte 0x0 0.--6. 1. "RX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__RCHAN_RCQ,The Rx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value TR based channel mode. This register may only be written when the.." hexmask.long.word 0x0 0.--15. 1. "RXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__RCHAN_ROES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__RCHAN_REOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_4_UDMAP0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Rx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_4_UDMAP0__CFG__RCHAN_THRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." rgroup.long 0xF0++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__RCHAN_RFLOW_RNG,The flow range register is used to control which flows other than the default flow (0x3FFF / channel_number) are allowed to be used with this DMA channel." hexmask.long.word 0x0 16.--30. 1. "FLOWID_CNT,Rx Flow ID Count: This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for this channel. A value of 0 indicates that no flow IDs other than the default are allowed for the channel.." newline hexmask.long.word 0x0 0.--13. 1. "FLOWID_START,Rx Starting Flow ID: Beyond the default flow ID each channel can also make use of a single contiguous range of flow IDs and this field specifies the starting index for that range.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_4_UDMAP0_CFG_RFLOW (NAVSS0_UDMAP_0_VIRT_ALIAS_4_UDMAP0_CFG_RFLOW)" base ad:0x4B40D00000 rgroup.long 0x0++0x1F line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__RFLOW_RFA,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." bitfld.long 0x0 30. "RX_EINFO_PRESENT,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will clear the Extended Packet Info Present bit in.." "0,1" newline bitfld.long 0x0 29. "RX_PSINFO_PRESENT,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will set the PS word count to 0 in the PD and will drop any PS words.." "0,1" newline bitfld.long 0x0 28. "RX_ERROR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor or buffer starvation occurs): 0 = Starvation errors result in dropping packet and reclaiming any used.." "0: Starvation errors result in dropping packet and..,1: Starvation errors result in subsequent re-try of.." newline bitfld.long 0x0 26.--27. "RX_DESC_TYPE,Rx Descriptor Type: This field indicates the descriptor type to use: 0 = Host 1 = RESERVED 2 = Monolithic 3 = RESERVED" "0: Host,1: RESERVED,2: Monolithic,3: RESERVED" newline bitfld.long 0x0 25. "RX_PS_LOCATION,Rx Protocol Specific Location: This bit controls where the Protocol Specific words will be placed in the Host Mode data structure. If this bit is cleared the DMA will clear the Protocol Specific Region Location bit in the PD and will.." "0,1" newline hexmask.long.word 0x0 16.--24. 1. "RX_SOP_OFFSET,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer). This value must be less than the.." newline hexmask.long.word 0x0 0.--15. 1. "RX_DEST_QNUM,Rx Destination Queue: This field indicates the default receive queue that packets on this flow should be placed onto." line.long 0x4 "VIRT_ALIAS_4_UDMAP0__CFG__RFLOW_RFB,The Rx Flow N Configuration Register B contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.byte 0x4 24.--31. 1. "RX_SRC_TAG_HI,Rx Source Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 16.--23. 1. "RX_SRC_TAG_LO,Rx Source Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1." newline hexmask.long.byte 0x4 8.--15. 1. "RX_DEST_TAG_HI,Rx Destination Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 0.--7. 1. "RX_DEST_TAG_LO,Rx Destination Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1." line.long 0x8 "VIRT_ALIAS_4_UDMAP0__CFG__RFLOW_RFC,The Rx Flow N Configuration Register C contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." bitfld.long 0x8 28.--30. "RX_SRC_TAG_HI_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 24.--26. "RX_SRC_TAG_LO_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 20.--22. "RX_DEST_TAG_HI_SEL,Rx Destination Tag High Byte Selector: This field specifies the source for bits 15:8 of the destination tag field in the word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 16.--18. "RX_DEST_TAG_LO_SEL,Rx Destination Tag Low Byte Selector: This field specifies the source for bits 7:0 of the destination tag field in word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 0.--2. "RX_SIZE_THRESH_EN,Rx Packet Sized Based Free Buffer Queue Enables: These bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_threshN fields to determine which FDQ to allocate the.." "0: Do not use the threshold,1: Use the thresholds to select between the 4..,?,?,?,?,?,?" line.long 0xC "VIRT_ALIAS_4_UDMAP0__CFG__RFLOW_RFD,The Rx Flow N Configuration Register D contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0xC 16.--31. 1. "RX_FDQ0_SZ0_QNUM,Rx Free Descriptor 0 Queue Index - Size 0: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value." newline hexmask.long.word 0xC 0.--15. 1. "RX_FDQ1_QNUM,Rx Free Descriptor 1 Queue Index: This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet" line.long 0x10 "VIRT_ALIAS_4_UDMAP0__CFG__RFLOW_RFE,The Rx Flow N Configuration Register E contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x10 16.--31. 1. "RX_FDQ2_QNUM,Rx Free Descriptor 2 Queue Index: This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet" newline hexmask.long.word 0x10 0.--15. 1. "RX_FDQ3_QNUM,Rx Free Descriptor 3 Queue Index: This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet" line.long 0x14 "VIRT_ALIAS_4_UDMAP0__CFG__RFLOW_RFF,The Rx Flow N Configuration Register F contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x14 16.--31. 1. "RX_SIZE_THRESH0,Rx Packet Size Threshold 0: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x14 0.--15. 1. "RX_SIZE_THRESH1,Rx Packet Size Threshold 1: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is greater than the.." line.long 0x18 "VIRT_ALIAS_4_UDMAP0__CFG__RFLOW_RFG,The Rx Flow N Configuration Register G contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x18 16.--31. 1. "RX_SIZE_THRESH2,Rx Packet Size Threshold 2: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x18 0.--15. 1. "RX_FDQ0_SZ1_QNUM,Rx Free Descriptor 0 Queue Index - Size 1: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value. This field is optional." line.long 0x1C "VIRT_ALIAS_4_UDMAP0__CFG__RFLOW_RFH,The Rx Flow N Configuration Register H contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x1C 16.--31. 1. "RX_FDQ0_SZ2_QNUM,Rx Free Descriptor 0 Queue Index - Size 2: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size1 value. This field is optional." newline hexmask.long.word 0x1C 0.--15. 1. "RX_FDQ0_SZ3_QNUM,Rx Free Descriptor 0 Queue Index - Size 3: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size2 value. This field is optional." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_4_UDMAP0_CFG_GCFG (NAVSS0_UDMAP_0_VIRT_ALIAS_4_UDMAP0_CFG_GCFG)" base ad:0x4B41150000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the UDMA-P in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This field sets the timeout duration in clock cycles. This field controls the minimum amount of time that an Rx channel will be required to wait when it encounters a buffer starvation condition and the Rx error handling bit is set to 1.." line.long 0x4 "VIRT_ALIAS_4_UDMAP0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x1C++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__GCFG_UTC_CTRL,The external UTC control register provides a mapping of logical to physical thread IDs ." hexmask.long.word 0x0 0.--15. 1. "UTC_CHAN_START,This field specifies the starting PSI-L thread number for the external UTC" rgroup.long 0x20++0xF line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this UDMA-P instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_4_UDMAP0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this UDMA-P instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_4_UDMAP0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx internal channel count" hexmask.long.word 0x8 9.--17. 1. "ECHAN_CNT,Tx external channel count" hexmask.long.word 0x8 0.--8. 1. "TCHAN_CNT,Tx internal channel count" line.long 0xC "VIRT_ALIAS_4_UDMAP0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,Tx ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,Tx high capacity internal channel count" hexmask.long.word 0xC 0.--13. 1. "RFLOW_CNT,Rx flow table entry count" rgroup.long 0x40++0xF line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__GCFG_PERF0,This register provides thresholds for outstanding virtualized read/write commands from interface mem0" hexmask.long.byte 0x0 16.--23. 1. "VRD_THRESH0,Virt read command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x0 0.--7. 1. "VWR_THRESH0,Virt write command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x4 "VIRT_ALIAS_4_UDMAP0__CFG__GCFG_PERF1,This register provides thresholds for outstanding virtualized read/write commands from interface mem1" hexmask.long.byte 0x4 16.--23. 1. "VRD_THRESH1,Virt read command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x4 0.--7. 1. "VWR_THRESH1,Virt write command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x8 "VIRT_ALIAS_4_UDMAP0__CFG__GCFG_PERF2,This register provides thresholds for outstanding virtualized read commands from interface memr" hexmask.long.byte 0x8 16.--23. 1. "VRD_THRESH2,Virt read command throttling threshold for memr. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." line.long 0xC "VIRT_ALIAS_4_UDMAP0__CFG__GCFG_PERF3,This register provides thresholds for outstanding virtualized write commands from interface memw" hexmask.long.byte 0xC 0.--7. 1. "VWR_THRESH3,Virt write command throttling threshold for memw. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x0 0.--31. 1. "NOGATE_LO,When set inhibits automatic gating of clock." line.long 0x4 "VIRT_ALIAS_4_UDMAP0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x4 0.--31. 1. "NOGATE_HI,When set inhibits automatic gating of clock." rgroup.long 0x78++0xB line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_4_UDMAP0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" line.long 0x8 "VIRT_ALIAS_4_UDMAP0__CFG__GCFG_RFLOWFWOES,The Rx Flow FW OES Register specifies a destination event number to which an event should be sent if an out of range flow ID is received on a packet." hexmask.long.word 0x8 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__GCFG_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check. Values in this register will remain persistent once an exception has been detected.." bitfld.long 0x0 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet. Once this bit is set the remaining fields in this register will not be modified. SW is required to write this bit to 0 to allow another.." "0,1" hexmask.long.word 0x0 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet" hexmask.long.word 0x0 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_4_UDMAP0_CFG_RCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_4_UDMAP0_CFG_RCHANRT)" base ad:0x4B44000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the rx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_4_UDMAP0_CFG_TCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_4_UDMAP0_CFG_TCHANRT)" base ad:0x4B45000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_4_UDMAP0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_5_UDMAP0_CFG_TCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_5_UDMAP0_CFG_TCHAN)" base ad:0x4B50B00000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 30. "TX_FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass extended.." "0: DMA controller will pass extended packet info..,?" newline bitfld.long 0x0 29. "TX_FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass PS words if present in.." "0: DMA controller will pass PS words if present in..,?" newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" newline hexmask.long.byte 0x0 0.--6. 1. "TX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." line.long 0x4 "VIRT_ALIAS_5_UDMAP0__CFG__TCHAN_TCREDIT,The Transfer Request Credit Register indicates how many TR sized buffer slots exist in the associated UTC channel to which this channel is associated. This register only exists for external UTC channels. This.." bitfld.long 0x4 0.--2. "COUNT,Transfer Request Credit Count: this field specifies how many credits for complete TRs are available. This field should be initialized before the channel is enabled and will then increment/decrement as TRs are submitted and responses are received." "0,1,2,3,4,5,6,7" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__TCHAN_TCQ,The Tx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value channel mode. This register may only be written when the channel.." hexmask.long.word 0x0 0.--15. 1. "TXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__TCHAN_TOES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__TCHAN_TEOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_5_UDMAP0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Tx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_5_UDMAP0__CFG__TCHAN_THRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x70++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0x0 0.--12. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_5_UDMAP0_CFG_RCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_5_UDMAP0_CFG_RCHAN)" base ad:0x4B50C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 15. "RX_IGNORE_SHORT,This field controls whether or not short packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Short packets are treated.." "0: Short packets are treated as exceptions and..,1: Short packets are ignored and the TR will.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline hexmask.long.byte 0x0 0.--6. 1. "RX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__RCHAN_RCQ,The Rx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value TR based channel mode. This register may only be written when the.." hexmask.long.word 0x0 0.--15. 1. "RXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__RCHAN_ROES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__RCHAN_REOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_5_UDMAP0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Rx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_5_UDMAP0__CFG__RCHAN_THRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." rgroup.long 0xF0++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__RCHAN_RFLOW_RNG,The flow range register is used to control which flows other than the default flow (0x3FFF / channel_number) are allowed to be used with this DMA channel." hexmask.long.word 0x0 16.--30. 1. "FLOWID_CNT,Rx Flow ID Count: This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for this channel. A value of 0 indicates that no flow IDs other than the default are allowed for the channel.." newline hexmask.long.word 0x0 0.--13. 1. "FLOWID_START,Rx Starting Flow ID: Beyond the default flow ID each channel can also make use of a single contiguous range of flow IDs and this field specifies the starting index for that range.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_5_UDMAP0_CFG_RFLOW (NAVSS0_UDMAP_0_VIRT_ALIAS_5_UDMAP0_CFG_RFLOW)" base ad:0x4B50D00000 rgroup.long 0x0++0x1F line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__RFLOW_RFA,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." bitfld.long 0x0 30. "RX_EINFO_PRESENT,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will clear the Extended Packet Info Present bit in.." "0,1" newline bitfld.long 0x0 29. "RX_PSINFO_PRESENT,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will set the PS word count to 0 in the PD and will drop any PS words.." "0,1" newline bitfld.long 0x0 28. "RX_ERROR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor or buffer starvation occurs): 0 = Starvation errors result in dropping packet and reclaiming any used.." "0: Starvation errors result in dropping packet and..,1: Starvation errors result in subsequent re-try of.." newline bitfld.long 0x0 26.--27. "RX_DESC_TYPE,Rx Descriptor Type: This field indicates the descriptor type to use: 0 = Host 1 = RESERVED 2 = Monolithic 3 = RESERVED" "0: Host,1: RESERVED,2: Monolithic,3: RESERVED" newline bitfld.long 0x0 25. "RX_PS_LOCATION,Rx Protocol Specific Location: This bit controls where the Protocol Specific words will be placed in the Host Mode data structure. If this bit is cleared the DMA will clear the Protocol Specific Region Location bit in the PD and will.." "0,1" newline hexmask.long.word 0x0 16.--24. 1. "RX_SOP_OFFSET,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer). This value must be less than the.." newline hexmask.long.word 0x0 0.--15. 1. "RX_DEST_QNUM,Rx Destination Queue: This field indicates the default receive queue that packets on this flow should be placed onto." line.long 0x4 "VIRT_ALIAS_5_UDMAP0__CFG__RFLOW_RFB,The Rx Flow N Configuration Register B contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.byte 0x4 24.--31. 1. "RX_SRC_TAG_HI,Rx Source Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 16.--23. 1. "RX_SRC_TAG_LO,Rx Source Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1." newline hexmask.long.byte 0x4 8.--15. 1. "RX_DEST_TAG_HI,Rx Destination Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 0.--7. 1. "RX_DEST_TAG_LO,Rx Destination Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1." line.long 0x8 "VIRT_ALIAS_5_UDMAP0__CFG__RFLOW_RFC,The Rx Flow N Configuration Register C contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." bitfld.long 0x8 28.--30. "RX_SRC_TAG_HI_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 24.--26. "RX_SRC_TAG_LO_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 20.--22. "RX_DEST_TAG_HI_SEL,Rx Destination Tag High Byte Selector: This field specifies the source for bits 15:8 of the destination tag field in the word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 16.--18. "RX_DEST_TAG_LO_SEL,Rx Destination Tag Low Byte Selector: This field specifies the source for bits 7:0 of the destination tag field in word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 0.--2. "RX_SIZE_THRESH_EN,Rx Packet Sized Based Free Buffer Queue Enables: These bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_threshN fields to determine which FDQ to allocate the.." "0: Do not use the threshold,1: Use the thresholds to select between the 4..,?,?,?,?,?,?" line.long 0xC "VIRT_ALIAS_5_UDMAP0__CFG__RFLOW_RFD,The Rx Flow N Configuration Register D contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0xC 16.--31. 1. "RX_FDQ0_SZ0_QNUM,Rx Free Descriptor 0 Queue Index - Size 0: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value." newline hexmask.long.word 0xC 0.--15. 1. "RX_FDQ1_QNUM,Rx Free Descriptor 1 Queue Index: This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet" line.long 0x10 "VIRT_ALIAS_5_UDMAP0__CFG__RFLOW_RFE,The Rx Flow N Configuration Register E contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x10 16.--31. 1. "RX_FDQ2_QNUM,Rx Free Descriptor 2 Queue Index: This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet" newline hexmask.long.word 0x10 0.--15. 1. "RX_FDQ3_QNUM,Rx Free Descriptor 3 Queue Index: This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet" line.long 0x14 "VIRT_ALIAS_5_UDMAP0__CFG__RFLOW_RFF,The Rx Flow N Configuration Register F contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x14 16.--31. 1. "RX_SIZE_THRESH0,Rx Packet Size Threshold 0: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x14 0.--15. 1. "RX_SIZE_THRESH1,Rx Packet Size Threshold 1: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is greater than the.." line.long 0x18 "VIRT_ALIAS_5_UDMAP0__CFG__RFLOW_RFG,The Rx Flow N Configuration Register G contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x18 16.--31. 1. "RX_SIZE_THRESH2,Rx Packet Size Threshold 2: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x18 0.--15. 1. "RX_FDQ0_SZ1_QNUM,Rx Free Descriptor 0 Queue Index - Size 1: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value. This field is optional." line.long 0x1C "VIRT_ALIAS_5_UDMAP0__CFG__RFLOW_RFH,The Rx Flow N Configuration Register H contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x1C 16.--31. 1. "RX_FDQ0_SZ2_QNUM,Rx Free Descriptor 0 Queue Index - Size 2: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size1 value. This field is optional." newline hexmask.long.word 0x1C 0.--15. 1. "RX_FDQ0_SZ3_QNUM,Rx Free Descriptor 0 Queue Index - Size 3: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size2 value. This field is optional." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_5_UDMAP0_CFG_GCFG (NAVSS0_UDMAP_0_VIRT_ALIAS_5_UDMAP0_CFG_GCFG)" base ad:0x4B51150000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the UDMA-P in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This field sets the timeout duration in clock cycles. This field controls the minimum amount of time that an Rx channel will be required to wait when it encounters a buffer starvation condition and the Rx error handling bit is set to 1.." line.long 0x4 "VIRT_ALIAS_5_UDMAP0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x1C++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__GCFG_UTC_CTRL,The external UTC control register provides a mapping of logical to physical thread IDs ." hexmask.long.word 0x0 0.--15. 1. "UTC_CHAN_START,This field specifies the starting PSI-L thread number for the external UTC" rgroup.long 0x20++0xF line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this UDMA-P instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_5_UDMAP0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this UDMA-P instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_5_UDMAP0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx internal channel count" hexmask.long.word 0x8 9.--17. 1. "ECHAN_CNT,Tx external channel count" hexmask.long.word 0x8 0.--8. 1. "TCHAN_CNT,Tx internal channel count" line.long 0xC "VIRT_ALIAS_5_UDMAP0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,Tx ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,Tx high capacity internal channel count" hexmask.long.word 0xC 0.--13. 1. "RFLOW_CNT,Rx flow table entry count" rgroup.long 0x40++0xF line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__GCFG_PERF0,This register provides thresholds for outstanding virtualized read/write commands from interface mem0" hexmask.long.byte 0x0 16.--23. 1. "VRD_THRESH0,Virt read command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x0 0.--7. 1. "VWR_THRESH0,Virt write command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x4 "VIRT_ALIAS_5_UDMAP0__CFG__GCFG_PERF1,This register provides thresholds for outstanding virtualized read/write commands from interface mem1" hexmask.long.byte 0x4 16.--23. 1. "VRD_THRESH1,Virt read command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x4 0.--7. 1. "VWR_THRESH1,Virt write command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x8 "VIRT_ALIAS_5_UDMAP0__CFG__GCFG_PERF2,This register provides thresholds for outstanding virtualized read commands from interface memr" hexmask.long.byte 0x8 16.--23. 1. "VRD_THRESH2,Virt read command throttling threshold for memr. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." line.long 0xC "VIRT_ALIAS_5_UDMAP0__CFG__GCFG_PERF3,This register provides thresholds for outstanding virtualized write commands from interface memw" hexmask.long.byte 0xC 0.--7. 1. "VWR_THRESH3,Virt write command throttling threshold for memw. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x0 0.--31. 1. "NOGATE_LO,When set inhibits automatic gating of clock." line.long 0x4 "VIRT_ALIAS_5_UDMAP0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x4 0.--31. 1. "NOGATE_HI,When set inhibits automatic gating of clock." rgroup.long 0x78++0xB line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_5_UDMAP0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" line.long 0x8 "VIRT_ALIAS_5_UDMAP0__CFG__GCFG_RFLOWFWOES,The Rx Flow FW OES Register specifies a destination event number to which an event should be sent if an out of range flow ID is received on a packet." hexmask.long.word 0x8 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__GCFG_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check. Values in this register will remain persistent once an exception has been detected.." bitfld.long 0x0 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet. Once this bit is set the remaining fields in this register will not be modified. SW is required to write this bit to 0 to allow another.." "0,1" hexmask.long.word 0x0 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet" hexmask.long.word 0x0 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_5_UDMAP0_CFG_RCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_5_UDMAP0_CFG_RCHANRT)" base ad:0x4B54000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the rx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_5_UDMAP0_CFG_TCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_5_UDMAP0_CFG_TCHANRT)" base ad:0x4B55000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_5_UDMAP0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_6_UDMAP0_CFG_TCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_6_UDMAP0_CFG_TCHAN)" base ad:0x4B60B00000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 30. "TX_FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass extended.." "0: DMA controller will pass extended packet info..,?" newline bitfld.long 0x0 29. "TX_FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass PS words if present in.." "0: DMA controller will pass PS words if present in..,?" newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" newline hexmask.long.byte 0x0 0.--6. 1. "TX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." line.long 0x4 "VIRT_ALIAS_6_UDMAP0__CFG__TCHAN_TCREDIT,The Transfer Request Credit Register indicates how many TR sized buffer slots exist in the associated UTC channel to which this channel is associated. This register only exists for external UTC channels. This.." bitfld.long 0x4 0.--2. "COUNT,Transfer Request Credit Count: this field specifies how many credits for complete TRs are available. This field should be initialized before the channel is enabled and will then increment/decrement as TRs are submitted and responses are received." "0,1,2,3,4,5,6,7" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__TCHAN_TCQ,The Tx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value channel mode. This register may only be written when the channel.." hexmask.long.word 0x0 0.--15. 1. "TXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__TCHAN_TOES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__TCHAN_TEOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_6_UDMAP0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Tx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_6_UDMAP0__CFG__TCHAN_THRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x70++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0x0 0.--12. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_6_UDMAP0_CFG_RCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_6_UDMAP0_CFG_RCHAN)" base ad:0x4B60C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 15. "RX_IGNORE_SHORT,This field controls whether or not short packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Short packets are treated.." "0: Short packets are treated as exceptions and..,1: Short packets are ignored and the TR will.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline hexmask.long.byte 0x0 0.--6. 1. "RX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__RCHAN_RCQ,The Rx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value TR based channel mode. This register may only be written when the.." hexmask.long.word 0x0 0.--15. 1. "RXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__RCHAN_ROES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__RCHAN_REOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_6_UDMAP0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Rx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_6_UDMAP0__CFG__RCHAN_THRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." rgroup.long 0xF0++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__RCHAN_RFLOW_RNG,The flow range register is used to control which flows other than the default flow (0x3FFF / channel_number) are allowed to be used with this DMA channel." hexmask.long.word 0x0 16.--30. 1. "FLOWID_CNT,Rx Flow ID Count: This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for this channel. A value of 0 indicates that no flow IDs other than the default are allowed for the channel.." newline hexmask.long.word 0x0 0.--13. 1. "FLOWID_START,Rx Starting Flow ID: Beyond the default flow ID each channel can also make use of a single contiguous range of flow IDs and this field specifies the starting index for that range.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_6_UDMAP0_CFG_RFLOW (NAVSS0_UDMAP_0_VIRT_ALIAS_6_UDMAP0_CFG_RFLOW)" base ad:0x4B60D00000 rgroup.long 0x0++0x1F line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__RFLOW_RFA,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." bitfld.long 0x0 30. "RX_EINFO_PRESENT,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will clear the Extended Packet Info Present bit in.." "0,1" newline bitfld.long 0x0 29. "RX_PSINFO_PRESENT,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will set the PS word count to 0 in the PD and will drop any PS words.." "0,1" newline bitfld.long 0x0 28. "RX_ERROR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor or buffer starvation occurs): 0 = Starvation errors result in dropping packet and reclaiming any used.." "0: Starvation errors result in dropping packet and..,1: Starvation errors result in subsequent re-try of.." newline bitfld.long 0x0 26.--27. "RX_DESC_TYPE,Rx Descriptor Type: This field indicates the descriptor type to use: 0 = Host 1 = RESERVED 2 = Monolithic 3 = RESERVED" "0: Host,1: RESERVED,2: Monolithic,3: RESERVED" newline bitfld.long 0x0 25. "RX_PS_LOCATION,Rx Protocol Specific Location: This bit controls where the Protocol Specific words will be placed in the Host Mode data structure. If this bit is cleared the DMA will clear the Protocol Specific Region Location bit in the PD and will.." "0,1" newline hexmask.long.word 0x0 16.--24. 1. "RX_SOP_OFFSET,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer). This value must be less than the.." newline hexmask.long.word 0x0 0.--15. 1. "RX_DEST_QNUM,Rx Destination Queue: This field indicates the default receive queue that packets on this flow should be placed onto." line.long 0x4 "VIRT_ALIAS_6_UDMAP0__CFG__RFLOW_RFB,The Rx Flow N Configuration Register B contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.byte 0x4 24.--31. 1. "RX_SRC_TAG_HI,Rx Source Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 16.--23. 1. "RX_SRC_TAG_LO,Rx Source Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1." newline hexmask.long.byte 0x4 8.--15. 1. "RX_DEST_TAG_HI,Rx Destination Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 0.--7. 1. "RX_DEST_TAG_LO,Rx Destination Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1." line.long 0x8 "VIRT_ALIAS_6_UDMAP0__CFG__RFLOW_RFC,The Rx Flow N Configuration Register C contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." bitfld.long 0x8 28.--30. "RX_SRC_TAG_HI_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 24.--26. "RX_SRC_TAG_LO_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 20.--22. "RX_DEST_TAG_HI_SEL,Rx Destination Tag High Byte Selector: This field specifies the source for bits 15:8 of the destination tag field in the word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 16.--18. "RX_DEST_TAG_LO_SEL,Rx Destination Tag Low Byte Selector: This field specifies the source for bits 7:0 of the destination tag field in word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 0.--2. "RX_SIZE_THRESH_EN,Rx Packet Sized Based Free Buffer Queue Enables: These bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_threshN fields to determine which FDQ to allocate the.." "0: Do not use the threshold,1: Use the thresholds to select between the 4..,?,?,?,?,?,?" line.long 0xC "VIRT_ALIAS_6_UDMAP0__CFG__RFLOW_RFD,The Rx Flow N Configuration Register D contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0xC 16.--31. 1. "RX_FDQ0_SZ0_QNUM,Rx Free Descriptor 0 Queue Index - Size 0: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value." newline hexmask.long.word 0xC 0.--15. 1. "RX_FDQ1_QNUM,Rx Free Descriptor 1 Queue Index: This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet" line.long 0x10 "VIRT_ALIAS_6_UDMAP0__CFG__RFLOW_RFE,The Rx Flow N Configuration Register E contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x10 16.--31. 1. "RX_FDQ2_QNUM,Rx Free Descriptor 2 Queue Index: This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet" newline hexmask.long.word 0x10 0.--15. 1. "RX_FDQ3_QNUM,Rx Free Descriptor 3 Queue Index: This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet" line.long 0x14 "VIRT_ALIAS_6_UDMAP0__CFG__RFLOW_RFF,The Rx Flow N Configuration Register F contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x14 16.--31. 1. "RX_SIZE_THRESH0,Rx Packet Size Threshold 0: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x14 0.--15. 1. "RX_SIZE_THRESH1,Rx Packet Size Threshold 1: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is greater than the.." line.long 0x18 "VIRT_ALIAS_6_UDMAP0__CFG__RFLOW_RFG,The Rx Flow N Configuration Register G contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x18 16.--31. 1. "RX_SIZE_THRESH2,Rx Packet Size Threshold 2: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x18 0.--15. 1. "RX_FDQ0_SZ1_QNUM,Rx Free Descriptor 0 Queue Index - Size 1: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value. This field is optional." line.long 0x1C "VIRT_ALIAS_6_UDMAP0__CFG__RFLOW_RFH,The Rx Flow N Configuration Register H contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x1C 16.--31. 1. "RX_FDQ0_SZ2_QNUM,Rx Free Descriptor 0 Queue Index - Size 2: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size1 value. This field is optional." newline hexmask.long.word 0x1C 0.--15. 1. "RX_FDQ0_SZ3_QNUM,Rx Free Descriptor 0 Queue Index - Size 3: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size2 value. This field is optional." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_6_UDMAP0_CFG_GCFG (NAVSS0_UDMAP_0_VIRT_ALIAS_6_UDMAP0_CFG_GCFG)" base ad:0x4B61150000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the UDMA-P in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This field sets the timeout duration in clock cycles. This field controls the minimum amount of time that an Rx channel will be required to wait when it encounters a buffer starvation condition and the Rx error handling bit is set to 1.." line.long 0x4 "VIRT_ALIAS_6_UDMAP0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x1C++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__GCFG_UTC_CTRL,The external UTC control register provides a mapping of logical to physical thread IDs ." hexmask.long.word 0x0 0.--15. 1. "UTC_CHAN_START,This field specifies the starting PSI-L thread number for the external UTC" rgroup.long 0x20++0xF line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this UDMA-P instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_6_UDMAP0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this UDMA-P instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_6_UDMAP0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx internal channel count" hexmask.long.word 0x8 9.--17. 1. "ECHAN_CNT,Tx external channel count" hexmask.long.word 0x8 0.--8. 1. "TCHAN_CNT,Tx internal channel count" line.long 0xC "VIRT_ALIAS_6_UDMAP0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,Tx ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,Tx high capacity internal channel count" hexmask.long.word 0xC 0.--13. 1. "RFLOW_CNT,Rx flow table entry count" rgroup.long 0x40++0xF line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__GCFG_PERF0,This register provides thresholds for outstanding virtualized read/write commands from interface mem0" hexmask.long.byte 0x0 16.--23. 1. "VRD_THRESH0,Virt read command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x0 0.--7. 1. "VWR_THRESH0,Virt write command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x4 "VIRT_ALIAS_6_UDMAP0__CFG__GCFG_PERF1,This register provides thresholds for outstanding virtualized read/write commands from interface mem1" hexmask.long.byte 0x4 16.--23. 1. "VRD_THRESH1,Virt read command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x4 0.--7. 1. "VWR_THRESH1,Virt write command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x8 "VIRT_ALIAS_6_UDMAP0__CFG__GCFG_PERF2,This register provides thresholds for outstanding virtualized read commands from interface memr" hexmask.long.byte 0x8 16.--23. 1. "VRD_THRESH2,Virt read command throttling threshold for memr. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." line.long 0xC "VIRT_ALIAS_6_UDMAP0__CFG__GCFG_PERF3,This register provides thresholds for outstanding virtualized write commands from interface memw" hexmask.long.byte 0xC 0.--7. 1. "VWR_THRESH3,Virt write command throttling threshold for memw. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x0 0.--31. 1. "NOGATE_LO,When set inhibits automatic gating of clock." line.long 0x4 "VIRT_ALIAS_6_UDMAP0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x4 0.--31. 1. "NOGATE_HI,When set inhibits automatic gating of clock." rgroup.long 0x78++0xB line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_6_UDMAP0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" line.long 0x8 "VIRT_ALIAS_6_UDMAP0__CFG__GCFG_RFLOWFWOES,The Rx Flow FW OES Register specifies a destination event number to which an event should be sent if an out of range flow ID is received on a packet." hexmask.long.word 0x8 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__GCFG_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check. Values in this register will remain persistent once an exception has been detected.." bitfld.long 0x0 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet. Once this bit is set the remaining fields in this register will not be modified. SW is required to write this bit to 0 to allow another.." "0,1" hexmask.long.word 0x0 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet" hexmask.long.word 0x0 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_6_UDMAP0_CFG_RCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_6_UDMAP0_CFG_RCHANRT)" base ad:0x4B64000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the rx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_6_UDMAP0_CFG_TCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_6_UDMAP0_CFG_TCHANRT)" base ad:0x4B65000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_6_UDMAP0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_7_UDMAP0_CFG_TCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_7_UDMAP0_CFG_TCHAN)" base ad:0x4B70B00000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 30. "TX_FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass extended.." "0: DMA controller will pass extended packet info..,?" newline bitfld.long 0x0 29. "TX_FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass PS words if present in.." "0: DMA controller will pass PS words if present in..,?" newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" newline hexmask.long.byte 0x0 0.--6. 1. "TX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." line.long 0x4 "VIRT_ALIAS_7_UDMAP0__CFG__TCHAN_TCREDIT,The Transfer Request Credit Register indicates how many TR sized buffer slots exist in the associated UTC channel to which this channel is associated. This register only exists for external UTC channels. This.." bitfld.long 0x4 0.--2. "COUNT,Transfer Request Credit Count: this field specifies how many credits for complete TRs are available. This field should be initialized before the channel is enabled and will then increment/decrement as TRs are submitted and responses are received." "0,1,2,3,4,5,6,7" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__TCHAN_TCQ,The Tx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value channel mode. This register may only be written when the channel.." hexmask.long.word 0x0 0.--15. 1. "TXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__TCHAN_TOES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__TCHAN_TEOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_7_UDMAP0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Tx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_7_UDMAP0__CFG__TCHAN_THRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x70++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0x0 0.--12. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_7_UDMAP0_CFG_RCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_7_UDMAP0_CFG_RCHAN)" base ad:0x4B70C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 15. "RX_IGNORE_SHORT,This field controls whether or not short packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Short packets are treated.." "0: Short packets are treated as exceptions and..,1: Short packets are ignored and the TR will.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline hexmask.long.byte 0x0 0.--6. 1. "RX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__RCHAN_RCQ,The Rx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value TR based channel mode. This register may only be written when the.." hexmask.long.word 0x0 0.--15. 1. "RXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__RCHAN_ROES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__RCHAN_REOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_7_UDMAP0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Rx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_7_UDMAP0__CFG__RCHAN_THRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." rgroup.long 0xF0++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__RCHAN_RFLOW_RNG,The flow range register is used to control which flows other than the default flow (0x3FFF / channel_number) are allowed to be used with this DMA channel." hexmask.long.word 0x0 16.--30. 1. "FLOWID_CNT,Rx Flow ID Count: This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for this channel. A value of 0 indicates that no flow IDs other than the default are allowed for the channel.." newline hexmask.long.word 0x0 0.--13. 1. "FLOWID_START,Rx Starting Flow ID: Beyond the default flow ID each channel can also make use of a single contiguous range of flow IDs and this field specifies the starting index for that range.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_7_UDMAP0_CFG_RFLOW (NAVSS0_UDMAP_0_VIRT_ALIAS_7_UDMAP0_CFG_RFLOW)" base ad:0x4B70D00000 rgroup.long 0x0++0x1F line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__RFLOW_RFA,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." bitfld.long 0x0 30. "RX_EINFO_PRESENT,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will clear the Extended Packet Info Present bit in.." "0,1" newline bitfld.long 0x0 29. "RX_PSINFO_PRESENT,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will set the PS word count to 0 in the PD and will drop any PS words.." "0,1" newline bitfld.long 0x0 28. "RX_ERROR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor or buffer starvation occurs): 0 = Starvation errors result in dropping packet and reclaiming any used.." "0: Starvation errors result in dropping packet and..,1: Starvation errors result in subsequent re-try of.." newline bitfld.long 0x0 26.--27. "RX_DESC_TYPE,Rx Descriptor Type: This field indicates the descriptor type to use: 0 = Host 1 = RESERVED 2 = Monolithic 3 = RESERVED" "0: Host,1: RESERVED,2: Monolithic,3: RESERVED" newline bitfld.long 0x0 25. "RX_PS_LOCATION,Rx Protocol Specific Location: This bit controls where the Protocol Specific words will be placed in the Host Mode data structure. If this bit is cleared the DMA will clear the Protocol Specific Region Location bit in the PD and will.." "0,1" newline hexmask.long.word 0x0 16.--24. 1. "RX_SOP_OFFSET,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer). This value must be less than the.." newline hexmask.long.word 0x0 0.--15. 1. "RX_DEST_QNUM,Rx Destination Queue: This field indicates the default receive queue that packets on this flow should be placed onto." line.long 0x4 "VIRT_ALIAS_7_UDMAP0__CFG__RFLOW_RFB,The Rx Flow N Configuration Register B contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.byte 0x4 24.--31. 1. "RX_SRC_TAG_HI,Rx Source Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 16.--23. 1. "RX_SRC_TAG_LO,Rx Source Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1." newline hexmask.long.byte 0x4 8.--15. 1. "RX_DEST_TAG_HI,Rx Destination Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 0.--7. 1. "RX_DEST_TAG_LO,Rx Destination Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1." line.long 0x8 "VIRT_ALIAS_7_UDMAP0__CFG__RFLOW_RFC,The Rx Flow N Configuration Register C contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." bitfld.long 0x8 28.--30. "RX_SRC_TAG_HI_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 24.--26. "RX_SRC_TAG_LO_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 20.--22. "RX_DEST_TAG_HI_SEL,Rx Destination Tag High Byte Selector: This field specifies the source for bits 15:8 of the destination tag field in the word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 16.--18. "RX_DEST_TAG_LO_SEL,Rx Destination Tag Low Byte Selector: This field specifies the source for bits 7:0 of the destination tag field in word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 0.--2. "RX_SIZE_THRESH_EN,Rx Packet Sized Based Free Buffer Queue Enables: These bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_threshN fields to determine which FDQ to allocate the.." "0: Do not use the threshold,1: Use the thresholds to select between the 4..,?,?,?,?,?,?" line.long 0xC "VIRT_ALIAS_7_UDMAP0__CFG__RFLOW_RFD,The Rx Flow N Configuration Register D contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0xC 16.--31. 1. "RX_FDQ0_SZ0_QNUM,Rx Free Descriptor 0 Queue Index - Size 0: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value." newline hexmask.long.word 0xC 0.--15. 1. "RX_FDQ1_QNUM,Rx Free Descriptor 1 Queue Index: This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet" line.long 0x10 "VIRT_ALIAS_7_UDMAP0__CFG__RFLOW_RFE,The Rx Flow N Configuration Register E contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x10 16.--31. 1. "RX_FDQ2_QNUM,Rx Free Descriptor 2 Queue Index: This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet" newline hexmask.long.word 0x10 0.--15. 1. "RX_FDQ3_QNUM,Rx Free Descriptor 3 Queue Index: This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet" line.long 0x14 "VIRT_ALIAS_7_UDMAP0__CFG__RFLOW_RFF,The Rx Flow N Configuration Register F contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x14 16.--31. 1. "RX_SIZE_THRESH0,Rx Packet Size Threshold 0: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x14 0.--15. 1. "RX_SIZE_THRESH1,Rx Packet Size Threshold 1: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is greater than the.." line.long 0x18 "VIRT_ALIAS_7_UDMAP0__CFG__RFLOW_RFG,The Rx Flow N Configuration Register G contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x18 16.--31. 1. "RX_SIZE_THRESH2,Rx Packet Size Threshold 2: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x18 0.--15. 1. "RX_FDQ0_SZ1_QNUM,Rx Free Descriptor 0 Queue Index - Size 1: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value. This field is optional." line.long 0x1C "VIRT_ALIAS_7_UDMAP0__CFG__RFLOW_RFH,The Rx Flow N Configuration Register H contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x1C 16.--31. 1. "RX_FDQ0_SZ2_QNUM,Rx Free Descriptor 0 Queue Index - Size 2: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size1 value. This field is optional." newline hexmask.long.word 0x1C 0.--15. 1. "RX_FDQ0_SZ3_QNUM,Rx Free Descriptor 0 Queue Index - Size 3: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size2 value. This field is optional." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_7_UDMAP0_CFG_GCFG (NAVSS0_UDMAP_0_VIRT_ALIAS_7_UDMAP0_CFG_GCFG)" base ad:0x4B71150000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the UDMA-P in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This field sets the timeout duration in clock cycles. This field controls the minimum amount of time that an Rx channel will be required to wait when it encounters a buffer starvation condition and the Rx error handling bit is set to 1.." line.long 0x4 "VIRT_ALIAS_7_UDMAP0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x1C++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__GCFG_UTC_CTRL,The external UTC control register provides a mapping of logical to physical thread IDs ." hexmask.long.word 0x0 0.--15. 1. "UTC_CHAN_START,This field specifies the starting PSI-L thread number for the external UTC" rgroup.long 0x20++0xF line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this UDMA-P instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_7_UDMAP0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this UDMA-P instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_7_UDMAP0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx internal channel count" hexmask.long.word 0x8 9.--17. 1. "ECHAN_CNT,Tx external channel count" hexmask.long.word 0x8 0.--8. 1. "TCHAN_CNT,Tx internal channel count" line.long 0xC "VIRT_ALIAS_7_UDMAP0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,Tx ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,Tx high capacity internal channel count" hexmask.long.word 0xC 0.--13. 1. "RFLOW_CNT,Rx flow table entry count" rgroup.long 0x40++0xF line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__GCFG_PERF0,This register provides thresholds for outstanding virtualized read/write commands from interface mem0" hexmask.long.byte 0x0 16.--23. 1. "VRD_THRESH0,Virt read command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x0 0.--7. 1. "VWR_THRESH0,Virt write command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x4 "VIRT_ALIAS_7_UDMAP0__CFG__GCFG_PERF1,This register provides thresholds for outstanding virtualized read/write commands from interface mem1" hexmask.long.byte 0x4 16.--23. 1. "VRD_THRESH1,Virt read command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x4 0.--7. 1. "VWR_THRESH1,Virt write command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x8 "VIRT_ALIAS_7_UDMAP0__CFG__GCFG_PERF2,This register provides thresholds for outstanding virtualized read commands from interface memr" hexmask.long.byte 0x8 16.--23. 1. "VRD_THRESH2,Virt read command throttling threshold for memr. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." line.long 0xC "VIRT_ALIAS_7_UDMAP0__CFG__GCFG_PERF3,This register provides thresholds for outstanding virtualized write commands from interface memw" hexmask.long.byte 0xC 0.--7. 1. "VWR_THRESH3,Virt write command throttling threshold for memw. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x0 0.--31. 1. "NOGATE_LO,When set inhibits automatic gating of clock." line.long 0x4 "VIRT_ALIAS_7_UDMAP0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x4 0.--31. 1. "NOGATE_HI,When set inhibits automatic gating of clock." rgroup.long 0x78++0xB line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_7_UDMAP0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" line.long 0x8 "VIRT_ALIAS_7_UDMAP0__CFG__GCFG_RFLOWFWOES,The Rx Flow FW OES Register specifies a destination event number to which an event should be sent if an out of range flow ID is received on a packet." hexmask.long.word 0x8 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__GCFG_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check. Values in this register will remain persistent once an exception has been detected.." bitfld.long 0x0 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet. Once this bit is set the remaining fields in this register will not be modified. SW is required to write this bit to 0 to allow another.." "0,1" hexmask.long.word 0x0 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet" hexmask.long.word 0x0 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_7_UDMAP0_CFG_RCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_7_UDMAP0_CFG_RCHANRT)" base ad:0x4B74000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the rx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_7_UDMAP0_CFG_TCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_7_UDMAP0_CFG_TCHANRT)" base ad:0x4B75000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_7_UDMAP0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_8_UDMAP0_CFG_TCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_8_UDMAP0_CFG_TCHAN)" base ad:0x4B80B00000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 30. "TX_FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass extended.." "0: DMA controller will pass extended packet info..,?" newline bitfld.long 0x0 29. "TX_FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass PS words if present in.." "0: DMA controller will pass PS words if present in..,?" newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" newline hexmask.long.byte 0x0 0.--6. 1. "TX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." line.long 0x4 "VIRT_ALIAS_8_UDMAP0__CFG__TCHAN_TCREDIT,The Transfer Request Credit Register indicates how many TR sized buffer slots exist in the associated UTC channel to which this channel is associated. This register only exists for external UTC channels. This.." bitfld.long 0x4 0.--2. "COUNT,Transfer Request Credit Count: this field specifies how many credits for complete TRs are available. This field should be initialized before the channel is enabled and will then increment/decrement as TRs are submitted and responses are received." "0,1,2,3,4,5,6,7" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__TCHAN_TCQ,The Tx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value channel mode. This register may only be written when the channel.." hexmask.long.word 0x0 0.--15. 1. "TXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__TCHAN_TOES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__TCHAN_TEOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_8_UDMAP0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Tx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_8_UDMAP0__CFG__TCHAN_THRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x70++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0x0 0.--12. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_8_UDMAP0_CFG_RCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_8_UDMAP0_CFG_RCHAN)" base ad:0x4B80C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 15. "RX_IGNORE_SHORT,This field controls whether or not short packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Short packets are treated.." "0: Short packets are treated as exceptions and..,1: Short packets are ignored and the TR will.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline hexmask.long.byte 0x0 0.--6. 1. "RX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__RCHAN_RCQ,The Rx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value TR based channel mode. This register may only be written when the.." hexmask.long.word 0x0 0.--15. 1. "RXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__RCHAN_ROES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__RCHAN_REOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_8_UDMAP0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Rx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_8_UDMAP0__CFG__RCHAN_THRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." rgroup.long 0xF0++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__RCHAN_RFLOW_RNG,The flow range register is used to control which flows other than the default flow (0x3FFF / channel_number) are allowed to be used with this DMA channel." hexmask.long.word 0x0 16.--30. 1. "FLOWID_CNT,Rx Flow ID Count: This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for this channel. A value of 0 indicates that no flow IDs other than the default are allowed for the channel.." newline hexmask.long.word 0x0 0.--13. 1. "FLOWID_START,Rx Starting Flow ID: Beyond the default flow ID each channel can also make use of a single contiguous range of flow IDs and this field specifies the starting index for that range.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_8_UDMAP0_CFG_RFLOW (NAVSS0_UDMAP_0_VIRT_ALIAS_8_UDMAP0_CFG_RFLOW)" base ad:0x4B80D00000 rgroup.long 0x0++0x1F line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__RFLOW_RFA,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." bitfld.long 0x0 30. "RX_EINFO_PRESENT,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will clear the Extended Packet Info Present bit in.." "0,1" newline bitfld.long 0x0 29. "RX_PSINFO_PRESENT,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will set the PS word count to 0 in the PD and will drop any PS words.." "0,1" newline bitfld.long 0x0 28. "RX_ERROR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor or buffer starvation occurs): 0 = Starvation errors result in dropping packet and reclaiming any used.." "0: Starvation errors result in dropping packet and..,1: Starvation errors result in subsequent re-try of.." newline bitfld.long 0x0 26.--27. "RX_DESC_TYPE,Rx Descriptor Type: This field indicates the descriptor type to use: 0 = Host 1 = RESERVED 2 = Monolithic 3 = RESERVED" "0: Host,1: RESERVED,2: Monolithic,3: RESERVED" newline bitfld.long 0x0 25. "RX_PS_LOCATION,Rx Protocol Specific Location: This bit controls where the Protocol Specific words will be placed in the Host Mode data structure. If this bit is cleared the DMA will clear the Protocol Specific Region Location bit in the PD and will.." "0,1" newline hexmask.long.word 0x0 16.--24. 1. "RX_SOP_OFFSET,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer). This value must be less than the.." newline hexmask.long.word 0x0 0.--15. 1. "RX_DEST_QNUM,Rx Destination Queue: This field indicates the default receive queue that packets on this flow should be placed onto." line.long 0x4 "VIRT_ALIAS_8_UDMAP0__CFG__RFLOW_RFB,The Rx Flow N Configuration Register B contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.byte 0x4 24.--31. 1. "RX_SRC_TAG_HI,Rx Source Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 16.--23. 1. "RX_SRC_TAG_LO,Rx Source Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1." newline hexmask.long.byte 0x4 8.--15. 1. "RX_DEST_TAG_HI,Rx Destination Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 0.--7. 1. "RX_DEST_TAG_LO,Rx Destination Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1." line.long 0x8 "VIRT_ALIAS_8_UDMAP0__CFG__RFLOW_RFC,The Rx Flow N Configuration Register C contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." bitfld.long 0x8 28.--30. "RX_SRC_TAG_HI_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 24.--26. "RX_SRC_TAG_LO_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 20.--22. "RX_DEST_TAG_HI_SEL,Rx Destination Tag High Byte Selector: This field specifies the source for bits 15:8 of the destination tag field in the word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 16.--18. "RX_DEST_TAG_LO_SEL,Rx Destination Tag Low Byte Selector: This field specifies the source for bits 7:0 of the destination tag field in word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 0.--2. "RX_SIZE_THRESH_EN,Rx Packet Sized Based Free Buffer Queue Enables: These bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_threshN fields to determine which FDQ to allocate the.." "0: Do not use the threshold,1: Use the thresholds to select between the 4..,?,?,?,?,?,?" line.long 0xC "VIRT_ALIAS_8_UDMAP0__CFG__RFLOW_RFD,The Rx Flow N Configuration Register D contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0xC 16.--31. 1. "RX_FDQ0_SZ0_QNUM,Rx Free Descriptor 0 Queue Index - Size 0: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value." newline hexmask.long.word 0xC 0.--15. 1. "RX_FDQ1_QNUM,Rx Free Descriptor 1 Queue Index: This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet" line.long 0x10 "VIRT_ALIAS_8_UDMAP0__CFG__RFLOW_RFE,The Rx Flow N Configuration Register E contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x10 16.--31. 1. "RX_FDQ2_QNUM,Rx Free Descriptor 2 Queue Index: This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet" newline hexmask.long.word 0x10 0.--15. 1. "RX_FDQ3_QNUM,Rx Free Descriptor 3 Queue Index: This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet" line.long 0x14 "VIRT_ALIAS_8_UDMAP0__CFG__RFLOW_RFF,The Rx Flow N Configuration Register F contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x14 16.--31. 1. "RX_SIZE_THRESH0,Rx Packet Size Threshold 0: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x14 0.--15. 1. "RX_SIZE_THRESH1,Rx Packet Size Threshold 1: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is greater than the.." line.long 0x18 "VIRT_ALIAS_8_UDMAP0__CFG__RFLOW_RFG,The Rx Flow N Configuration Register G contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x18 16.--31. 1. "RX_SIZE_THRESH2,Rx Packet Size Threshold 2: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x18 0.--15. 1. "RX_FDQ0_SZ1_QNUM,Rx Free Descriptor 0 Queue Index - Size 1: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value. This field is optional." line.long 0x1C "VIRT_ALIAS_8_UDMAP0__CFG__RFLOW_RFH,The Rx Flow N Configuration Register H contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x1C 16.--31. 1. "RX_FDQ0_SZ2_QNUM,Rx Free Descriptor 0 Queue Index - Size 2: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size1 value. This field is optional." newline hexmask.long.word 0x1C 0.--15. 1. "RX_FDQ0_SZ3_QNUM,Rx Free Descriptor 0 Queue Index - Size 3: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size2 value. This field is optional." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_8_UDMAP0_CFG_GCFG (NAVSS0_UDMAP_0_VIRT_ALIAS_8_UDMAP0_CFG_GCFG)" base ad:0x4B81150000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the UDMA-P in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This field sets the timeout duration in clock cycles. This field controls the minimum amount of time that an Rx channel will be required to wait when it encounters a buffer starvation condition and the Rx error handling bit is set to 1.." line.long 0x4 "VIRT_ALIAS_8_UDMAP0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x1C++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__GCFG_UTC_CTRL,The external UTC control register provides a mapping of logical to physical thread IDs ." hexmask.long.word 0x0 0.--15. 1. "UTC_CHAN_START,This field specifies the starting PSI-L thread number for the external UTC" rgroup.long 0x20++0xF line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this UDMA-P instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_8_UDMAP0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this UDMA-P instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_8_UDMAP0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx internal channel count" hexmask.long.word 0x8 9.--17. 1. "ECHAN_CNT,Tx external channel count" hexmask.long.word 0x8 0.--8. 1. "TCHAN_CNT,Tx internal channel count" line.long 0xC "VIRT_ALIAS_8_UDMAP0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,Tx ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,Tx high capacity internal channel count" hexmask.long.word 0xC 0.--13. 1. "RFLOW_CNT,Rx flow table entry count" rgroup.long 0x40++0xF line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__GCFG_PERF0,This register provides thresholds for outstanding virtualized read/write commands from interface mem0" hexmask.long.byte 0x0 16.--23. 1. "VRD_THRESH0,Virt read command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x0 0.--7. 1. "VWR_THRESH0,Virt write command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x4 "VIRT_ALIAS_8_UDMAP0__CFG__GCFG_PERF1,This register provides thresholds for outstanding virtualized read/write commands from interface mem1" hexmask.long.byte 0x4 16.--23. 1. "VRD_THRESH1,Virt read command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x4 0.--7. 1. "VWR_THRESH1,Virt write command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x8 "VIRT_ALIAS_8_UDMAP0__CFG__GCFG_PERF2,This register provides thresholds for outstanding virtualized read commands from interface memr" hexmask.long.byte 0x8 16.--23. 1. "VRD_THRESH2,Virt read command throttling threshold for memr. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." line.long 0xC "VIRT_ALIAS_8_UDMAP0__CFG__GCFG_PERF3,This register provides thresholds for outstanding virtualized write commands from interface memw" hexmask.long.byte 0xC 0.--7. 1. "VWR_THRESH3,Virt write command throttling threshold for memw. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x0 0.--31. 1. "NOGATE_LO,When set inhibits automatic gating of clock." line.long 0x4 "VIRT_ALIAS_8_UDMAP0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x4 0.--31. 1. "NOGATE_HI,When set inhibits automatic gating of clock." rgroup.long 0x78++0xB line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_8_UDMAP0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" line.long 0x8 "VIRT_ALIAS_8_UDMAP0__CFG__GCFG_RFLOWFWOES,The Rx Flow FW OES Register specifies a destination event number to which an event should be sent if an out of range flow ID is received on a packet." hexmask.long.word 0x8 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__GCFG_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check. Values in this register will remain persistent once an exception has been detected.." bitfld.long 0x0 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet. Once this bit is set the remaining fields in this register will not be modified. SW is required to write this bit to 0 to allow another.." "0,1" hexmask.long.word 0x0 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet" hexmask.long.word 0x0 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_8_UDMAP0_CFG_RCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_8_UDMAP0_CFG_RCHANRT)" base ad:0x4B84000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the rx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_8_UDMAP0_CFG_TCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_8_UDMAP0_CFG_TCHANRT)" base ad:0x4B85000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_8_UDMAP0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_9_UDMAP0_CFG_TCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_9_UDMAP0_CFG_TCHAN)" base ad:0x4B90B00000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 30. "TX_FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass extended.." "0: DMA controller will pass extended packet info..,?" newline bitfld.long 0x0 29. "TX_FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass PS words if present in.." "0: DMA controller will pass PS words if present in..,?" newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" newline hexmask.long.byte 0x0 0.--6. 1. "TX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." line.long 0x4 "VIRT_ALIAS_9_UDMAP0__CFG__TCHAN_TCREDIT,The Transfer Request Credit Register indicates how many TR sized buffer slots exist in the associated UTC channel to which this channel is associated. This register only exists for external UTC channels. This.." bitfld.long 0x4 0.--2. "COUNT,Transfer Request Credit Count: this field specifies how many credits for complete TRs are available. This field should be initialized before the channel is enabled and will then increment/decrement as TRs are submitted and responses are received." "0,1,2,3,4,5,6,7" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__TCHAN_TCQ,The Tx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value channel mode. This register may only be written when the channel.." hexmask.long.word 0x0 0.--15. 1. "TXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__TCHAN_TOES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__TCHAN_TEOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_9_UDMAP0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Tx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_9_UDMAP0__CFG__TCHAN_THRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x70++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0x0 0.--12. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_9_UDMAP0_CFG_RCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_9_UDMAP0_CFG_RCHAN)" base ad:0x4B90C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 15. "RX_IGNORE_SHORT,This field controls whether or not short packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Short packets are treated.." "0: Short packets are treated as exceptions and..,1: Short packets are ignored and the TR will.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline hexmask.long.byte 0x0 0.--6. 1. "RX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__RCHAN_RCQ,The Rx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value TR based channel mode. This register may only be written when the.." hexmask.long.word 0x0 0.--15. 1. "RXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__RCHAN_ROES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__RCHAN_REOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_9_UDMAP0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Rx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_9_UDMAP0__CFG__RCHAN_THRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." rgroup.long 0xF0++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__RCHAN_RFLOW_RNG,The flow range register is used to control which flows other than the default flow (0x3FFF / channel_number) are allowed to be used with this DMA channel." hexmask.long.word 0x0 16.--30. 1. "FLOWID_CNT,Rx Flow ID Count: This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for this channel. A value of 0 indicates that no flow IDs other than the default are allowed for the channel.." newline hexmask.long.word 0x0 0.--13. 1. "FLOWID_START,Rx Starting Flow ID: Beyond the default flow ID each channel can also make use of a single contiguous range of flow IDs and this field specifies the starting index for that range.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_9_UDMAP0_CFG_RFLOW (NAVSS0_UDMAP_0_VIRT_ALIAS_9_UDMAP0_CFG_RFLOW)" base ad:0x4B90D00000 rgroup.long 0x0++0x1F line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__RFLOW_RFA,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." bitfld.long 0x0 30. "RX_EINFO_PRESENT,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will clear the Extended Packet Info Present bit in.." "0,1" newline bitfld.long 0x0 29. "RX_PSINFO_PRESENT,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will set the PS word count to 0 in the PD and will drop any PS words.." "0,1" newline bitfld.long 0x0 28. "RX_ERROR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor or buffer starvation occurs): 0 = Starvation errors result in dropping packet and reclaiming any used.." "0: Starvation errors result in dropping packet and..,1: Starvation errors result in subsequent re-try of.." newline bitfld.long 0x0 26.--27. "RX_DESC_TYPE,Rx Descriptor Type: This field indicates the descriptor type to use: 0 = Host 1 = RESERVED 2 = Monolithic 3 = RESERVED" "0: Host,1: RESERVED,2: Monolithic,3: RESERVED" newline bitfld.long 0x0 25. "RX_PS_LOCATION,Rx Protocol Specific Location: This bit controls where the Protocol Specific words will be placed in the Host Mode data structure. If this bit is cleared the DMA will clear the Protocol Specific Region Location bit in the PD and will.." "0,1" newline hexmask.long.word 0x0 16.--24. 1. "RX_SOP_OFFSET,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer). This value must be less than the.." newline hexmask.long.word 0x0 0.--15. 1. "RX_DEST_QNUM,Rx Destination Queue: This field indicates the default receive queue that packets on this flow should be placed onto." line.long 0x4 "VIRT_ALIAS_9_UDMAP0__CFG__RFLOW_RFB,The Rx Flow N Configuration Register B contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.byte 0x4 24.--31. 1. "RX_SRC_TAG_HI,Rx Source Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 16.--23. 1. "RX_SRC_TAG_LO,Rx Source Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1." newline hexmask.long.byte 0x4 8.--15. 1. "RX_DEST_TAG_HI,Rx Destination Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 0.--7. 1. "RX_DEST_TAG_LO,Rx Destination Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1." line.long 0x8 "VIRT_ALIAS_9_UDMAP0__CFG__RFLOW_RFC,The Rx Flow N Configuration Register C contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." bitfld.long 0x8 28.--30. "RX_SRC_TAG_HI_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 24.--26. "RX_SRC_TAG_LO_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 20.--22. "RX_DEST_TAG_HI_SEL,Rx Destination Tag High Byte Selector: This field specifies the source for bits 15:8 of the destination tag field in the word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 16.--18. "RX_DEST_TAG_LO_SEL,Rx Destination Tag Low Byte Selector: This field specifies the source for bits 7:0 of the destination tag field in word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 0.--2. "RX_SIZE_THRESH_EN,Rx Packet Sized Based Free Buffer Queue Enables: These bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_threshN fields to determine which FDQ to allocate the.." "0: Do not use the threshold,1: Use the thresholds to select between the 4..,?,?,?,?,?,?" line.long 0xC "VIRT_ALIAS_9_UDMAP0__CFG__RFLOW_RFD,The Rx Flow N Configuration Register D contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0xC 16.--31. 1. "RX_FDQ0_SZ0_QNUM,Rx Free Descriptor 0 Queue Index - Size 0: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value." newline hexmask.long.word 0xC 0.--15. 1. "RX_FDQ1_QNUM,Rx Free Descriptor 1 Queue Index: This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet" line.long 0x10 "VIRT_ALIAS_9_UDMAP0__CFG__RFLOW_RFE,The Rx Flow N Configuration Register E contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x10 16.--31. 1. "RX_FDQ2_QNUM,Rx Free Descriptor 2 Queue Index: This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet" newline hexmask.long.word 0x10 0.--15. 1. "RX_FDQ3_QNUM,Rx Free Descriptor 3 Queue Index: This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet" line.long 0x14 "VIRT_ALIAS_9_UDMAP0__CFG__RFLOW_RFF,The Rx Flow N Configuration Register F contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x14 16.--31. 1. "RX_SIZE_THRESH0,Rx Packet Size Threshold 0: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x14 0.--15. 1. "RX_SIZE_THRESH1,Rx Packet Size Threshold 1: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is greater than the.." line.long 0x18 "VIRT_ALIAS_9_UDMAP0__CFG__RFLOW_RFG,The Rx Flow N Configuration Register G contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x18 16.--31. 1. "RX_SIZE_THRESH2,Rx Packet Size Threshold 2: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x18 0.--15. 1. "RX_FDQ0_SZ1_QNUM,Rx Free Descriptor 0 Queue Index - Size 1: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value. This field is optional." line.long 0x1C "VIRT_ALIAS_9_UDMAP0__CFG__RFLOW_RFH,The Rx Flow N Configuration Register H contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled." hexmask.long.word 0x1C 16.--31. 1. "RX_FDQ0_SZ2_QNUM,Rx Free Descriptor 0 Queue Index - Size 2: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size1 value. This field is optional." newline hexmask.long.word 0x1C 0.--15. 1. "RX_FDQ0_SZ3_QNUM,Rx Free Descriptor 0 Queue Index - Size 3: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size2 value. This field is optional." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_9_UDMAP0_CFG_GCFG (NAVSS0_UDMAP_0_VIRT_ALIAS_9_UDMAP0_CFG_GCFG)" base ad:0x4B91150000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the UDMA-P in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This field sets the timeout duration in clock cycles. This field controls the minimum amount of time that an Rx channel will be required to wait when it encounters a buffer starvation condition and the Rx error handling bit is set to 1.." line.long 0x4 "VIRT_ALIAS_9_UDMAP0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x1C++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__GCFG_UTC_CTRL,The external UTC control register provides a mapping of logical to physical thread IDs ." hexmask.long.word 0x0 0.--15. 1. "UTC_CHAN_START,This field specifies the starting PSI-L thread number for the external UTC" rgroup.long 0x20++0xF line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this UDMA-P instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_9_UDMAP0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this UDMA-P instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_9_UDMAP0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx internal channel count" hexmask.long.word 0x8 9.--17. 1. "ECHAN_CNT,Tx external channel count" hexmask.long.word 0x8 0.--8. 1. "TCHAN_CNT,Tx internal channel count" line.long 0xC "VIRT_ALIAS_9_UDMAP0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,Tx ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,Tx high capacity internal channel count" hexmask.long.word 0xC 0.--13. 1. "RFLOW_CNT,Rx flow table entry count" rgroup.long 0x40++0xF line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__GCFG_PERF0,This register provides thresholds for outstanding virtualized read/write commands from interface mem0" hexmask.long.byte 0x0 16.--23. 1. "VRD_THRESH0,Virt read command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x0 0.--7. 1. "VWR_THRESH0,Virt write command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x4 "VIRT_ALIAS_9_UDMAP0__CFG__GCFG_PERF1,This register provides thresholds for outstanding virtualized read/write commands from interface mem1" hexmask.long.byte 0x4 16.--23. 1. "VRD_THRESH1,Virt read command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x4 0.--7. 1. "VWR_THRESH1,Virt write command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x8 "VIRT_ALIAS_9_UDMAP0__CFG__GCFG_PERF2,This register provides thresholds for outstanding virtualized read commands from interface memr" hexmask.long.byte 0x8 16.--23. 1. "VRD_THRESH2,Virt read command throttling threshold for memr. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." line.long 0xC "VIRT_ALIAS_9_UDMAP0__CFG__GCFG_PERF3,This register provides thresholds for outstanding virtualized write commands from interface memw" hexmask.long.byte 0xC 0.--7. 1. "VWR_THRESH3,Virt write command throttling threshold for memw. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x0 0.--31. 1. "NOGATE_LO,When set inhibits automatic gating of clock." line.long 0x4 "VIRT_ALIAS_9_UDMAP0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x4 0.--31. 1. "NOGATE_HI,When set inhibits automatic gating of clock." rgroup.long 0x78++0xB line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_9_UDMAP0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" line.long 0x8 "VIRT_ALIAS_9_UDMAP0__CFG__GCFG_RFLOWFWOES,The Rx Flow FW OES Register specifies a destination event number to which an event should be sent if an out of range flow ID is received on a packet." hexmask.long.word 0x8 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__GCFG_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check. Values in this register will remain persistent once an exception has been detected.." bitfld.long 0x0 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet. Once this bit is set the remaining fields in this register will not be modified. SW is required to write this bit to 0 to allow another.." "0,1" hexmask.long.word 0x0 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet" hexmask.long.word 0x0 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_9_UDMAP0_CFG_RCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_9_UDMAP0_CFG_RCHANRT)" base ad:0x4B94000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the rx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_9_UDMAP0_CFG_TCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_9_UDMAP0_CFG_TCHANRT)" base ad:0x4B95000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_9_UDMAP0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_10_UDMAP0_CFG_TCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_10_UDMAP0_CFG_TCHAN)" base ad:0x4BA0B00000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 30. "TX_FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass extended.." "0: DMA controller will pass extended packet info..,?" newline bitfld.long 0x0 29. "TX_FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass PS words if present in.." "0: DMA controller will pass PS words if present in..,?" newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" newline hexmask.long.byte 0x0 0.--6. 1. "TX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." line.long 0x4 "VIRT_ALIAS_10_UDMAP0__CFG__TCHAN_TCREDIT,The Transfer Request Credit Register indicates how many TR sized buffer slots exist in the associated UTC channel to which this channel is associated. This register only exists for external UTC channels. This.." bitfld.long 0x4 0.--2. "COUNT,Transfer Request Credit Count: this field specifies how many credits for complete TRs are available. This field should be initialized before the channel is enabled and will then increment/decrement as TRs are submitted and responses are received." "0,1,2,3,4,5,6,7" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__TCHAN_TCQ,The Tx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value channel mode. This register may only be written when the channel.." hexmask.long.word 0x0 0.--15. 1. "TXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__TCHAN_TOES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__TCHAN_TEOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_10_UDMAP0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Tx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_10_UDMAP0__CFG__TCHAN_THRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x70++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0x0 0.--12. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_10_UDMAP0_CFG_RCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_10_UDMAP0_CFG_RCHAN)" base ad:0x4BA0C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 15. "RX_IGNORE_SHORT,This field controls whether or not short packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Short packets are treated.." "0: Short packets are treated as exceptions and..,1: Short packets are ignored and the TR will.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline hexmask.long.byte 0x0 0.--6. 1. "RX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__RCHAN_RCQ,The Rx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value TR based channel mode. This register may only be written when the.." hexmask.long.word 0x0 0.--15. 1. "RXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__RCHAN_ROES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__RCHAN_REOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_10_UDMAP0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Rx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_10_UDMAP0__CFG__RCHAN_THRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." rgroup.long 0xF0++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__RCHAN_RFLOW_RNG,The flow range register is used to control which flows other than the default flow (0x3FFF / channel_number) are allowed to be used with this DMA channel." hexmask.long.word 0x0 16.--30. 1. "FLOWID_CNT,Rx Flow ID Count: This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for this channel. A value of 0 indicates that no flow IDs other than the default are allowed for the channel.." newline hexmask.long.word 0x0 0.--13. 1. "FLOWID_START,Rx Starting Flow ID: Beyond the default flow ID each channel can also make use of a single contiguous range of flow IDs and this field specifies the starting index for that range.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_10_UDMAP0_CFG_RFLOW (NAVSS0_UDMAP_0_VIRT_ALIAS_10_UDMAP0_CFG_RFLOW)" base ad:0x4BA0D00000 rgroup.long 0x0++0x1F line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__RFLOW_RFA,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." bitfld.long 0x0 30. "RX_EINFO_PRESENT,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will clear the Extended Packet Info Present bit in.." "0,1" newline bitfld.long 0x0 29. "RX_PSINFO_PRESENT,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will set the PS word count to 0 in the PD and will drop any PS words.." "0,1" newline bitfld.long 0x0 28. "RX_ERROR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor or buffer starvation occurs): 0 = Starvation errors result in dropping packet and reclaiming any used.." "0: Starvation errors result in dropping packet and..,1: Starvation errors result in subsequent re-try of.." newline bitfld.long 0x0 26.--27. "RX_DESC_TYPE,Rx Descriptor Type: This field indicates the descriptor type to use: 0 = Host 1 = RESERVED 2 = Monolithic 3 = RESERVED" "0: Host,1: RESERVED,2: Monolithic,3: RESERVED" newline bitfld.long 0x0 25. "RX_PS_LOCATION,Rx Protocol Specific Location: This bit controls where the Protocol Specific words will be placed in the Host Mode data structure. If this bit is cleared the DMA will clear the Protocol Specific Region Location bit in the PD and will.." "0,1" newline hexmask.long.word 0x0 16.--24. 1. "RX_SOP_OFFSET,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer). This value must be less than the.." newline hexmask.long.word 0x0 0.--15. 1. "RX_DEST_QNUM,Rx Destination Queue: This field indicates the default receive queue that packets on this flow should be placed onto." line.long 0x4 "VIRT_ALIAS_10_UDMAP0__CFG__RFLOW_RFB,The Rx Flow N Configuration Register B contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.byte 0x4 24.--31. 1. "RX_SRC_TAG_HI,Rx Source Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 16.--23. 1. "RX_SRC_TAG_LO,Rx Source Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1." newline hexmask.long.byte 0x4 8.--15. 1. "RX_DEST_TAG_HI,Rx Destination Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 0.--7. 1. "RX_DEST_TAG_LO,Rx Destination Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1." line.long 0x8 "VIRT_ALIAS_10_UDMAP0__CFG__RFLOW_RFC,The Rx Flow N Configuration Register C contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." bitfld.long 0x8 28.--30. "RX_SRC_TAG_HI_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 24.--26. "RX_SRC_TAG_LO_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 20.--22. "RX_DEST_TAG_HI_SEL,Rx Destination Tag High Byte Selector: This field specifies the source for bits 15:8 of the destination tag field in the word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 16.--18. "RX_DEST_TAG_LO_SEL,Rx Destination Tag Low Byte Selector: This field specifies the source for bits 7:0 of the destination tag field in word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 0.--2. "RX_SIZE_THRESH_EN,Rx Packet Sized Based Free Buffer Queue Enables: These bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_threshN fields to determine which FDQ to allocate the.." "0: Do not use the threshold,1: Use the thresholds to select between the 4..,?,?,?,?,?,?" line.long 0xC "VIRT_ALIAS_10_UDMAP0__CFG__RFLOW_RFD,The Rx Flow N Configuration Register D contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0xC 16.--31. 1. "RX_FDQ0_SZ0_QNUM,Rx Free Descriptor 0 Queue Index - Size 0: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value." newline hexmask.long.word 0xC 0.--15. 1. "RX_FDQ1_QNUM,Rx Free Descriptor 1 Queue Index: This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet" line.long 0x10 "VIRT_ALIAS_10_UDMAP0__CFG__RFLOW_RFE,The Rx Flow N Configuration Register E contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x10 16.--31. 1. "RX_FDQ2_QNUM,Rx Free Descriptor 2 Queue Index: This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet" newline hexmask.long.word 0x10 0.--15. 1. "RX_FDQ3_QNUM,Rx Free Descriptor 3 Queue Index: This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet" line.long 0x14 "VIRT_ALIAS_10_UDMAP0__CFG__RFLOW_RFF,The Rx Flow N Configuration Register F contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x14 16.--31. 1. "RX_SIZE_THRESH0,Rx Packet Size Threshold 0: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x14 0.--15. 1. "RX_SIZE_THRESH1,Rx Packet Size Threshold 1: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is greater than the.." line.long 0x18 "VIRT_ALIAS_10_UDMAP0__CFG__RFLOW_RFG,The Rx Flow N Configuration Register G contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x18 16.--31. 1. "RX_SIZE_THRESH2,Rx Packet Size Threshold 2: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x18 0.--15. 1. "RX_FDQ0_SZ1_QNUM,Rx Free Descriptor 0 Queue Index - Size 1: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value. This field is optional." line.long 0x1C "VIRT_ALIAS_10_UDMAP0__CFG__RFLOW_RFH,The Rx Flow N Configuration Register H contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x1C 16.--31. 1. "RX_FDQ0_SZ2_QNUM,Rx Free Descriptor 0 Queue Index - Size 2: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size1 value. This field is optional." newline hexmask.long.word 0x1C 0.--15. 1. "RX_FDQ0_SZ3_QNUM,Rx Free Descriptor 0 Queue Index - Size 3: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size2 value. This field is optional." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_10_UDMAP0_CFG_GCFG (NAVSS0_UDMAP_0_VIRT_ALIAS_10_UDMAP0_CFG_GCFG)" base ad:0x4BA1150000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the UDMA-P in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This field sets the timeout duration in clock cycles. This field controls the minimum amount of time that an Rx channel will be required to wait when it encounters a buffer starvation condition and the Rx error handling bit is set to 1.." line.long 0x4 "VIRT_ALIAS_10_UDMAP0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x1C++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__GCFG_UTC_CTRL,The external UTC control register provides a mapping of logical to physical thread IDs ." hexmask.long.word 0x0 0.--15. 1. "UTC_CHAN_START,This field specifies the starting PSI-L thread number for the external UTC" rgroup.long 0x20++0xF line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this UDMA-P instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_10_UDMAP0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this UDMA-P instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_10_UDMAP0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx internal channel count" hexmask.long.word 0x8 9.--17. 1. "ECHAN_CNT,Tx external channel count" hexmask.long.word 0x8 0.--8. 1. "TCHAN_CNT,Tx internal channel count" line.long 0xC "VIRT_ALIAS_10_UDMAP0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,Tx ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,Tx high capacity internal channel count" hexmask.long.word 0xC 0.--13. 1. "RFLOW_CNT,Rx flow table entry count" rgroup.long 0x40++0xF line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__GCFG_PERF0,This register provides thresholds for outstanding virtualized read/write commands from interface mem0" hexmask.long.byte 0x0 16.--23. 1. "VRD_THRESH0,Virt read command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x0 0.--7. 1. "VWR_THRESH0,Virt write command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x4 "VIRT_ALIAS_10_UDMAP0__CFG__GCFG_PERF1,This register provides thresholds for outstanding virtualized read/write commands from interface mem1" hexmask.long.byte 0x4 16.--23. 1. "VRD_THRESH1,Virt read command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x4 0.--7. 1. "VWR_THRESH1,Virt write command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x8 "VIRT_ALIAS_10_UDMAP0__CFG__GCFG_PERF2,This register provides thresholds for outstanding virtualized read commands from interface memr" hexmask.long.byte 0x8 16.--23. 1. "VRD_THRESH2,Virt read command throttling threshold for memr. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." line.long 0xC "VIRT_ALIAS_10_UDMAP0__CFG__GCFG_PERF3,This register provides thresholds for outstanding virtualized write commands from interface memw" hexmask.long.byte 0xC 0.--7. 1. "VWR_THRESH3,Virt write command throttling threshold for memw. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x0 0.--31. 1. "NOGATE_LO,When set inhibits automatic gating of clock." line.long 0x4 "VIRT_ALIAS_10_UDMAP0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x4 0.--31. 1. "NOGATE_HI,When set inhibits automatic gating of clock." rgroup.long 0x78++0xB line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_10_UDMAP0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" line.long 0x8 "VIRT_ALIAS_10_UDMAP0__CFG__GCFG_RFLOWFWOES,The Rx Flow FW OES Register specifies a destination event number to which an event should be sent if an out of range flow ID is received on a packet." hexmask.long.word 0x8 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__GCFG_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check. Values in this register will remain persistent once an exception has been.." bitfld.long 0x0 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet. Once this bit is set the remaining fields in this register will not be modified. SW is required to write this bit to 0 to allow another.." "0,1" hexmask.long.word 0x0 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet" hexmask.long.word 0x0 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_10_UDMAP0_CFG_RCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_10_UDMAP0_CFG_RCHANRT)" base ad:0x4BA4000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the rx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_10_UDMAP0_CFG_TCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_10_UDMAP0_CFG_TCHANRT)" base ad:0x4BA5000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_10_UDMAP0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_11_UDMAP0_CFG_TCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_11_UDMAP0_CFG_TCHAN)" base ad:0x4BB0B00000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 30. "TX_FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass extended.." "0: DMA controller will pass extended packet info..,?" newline bitfld.long 0x0 29. "TX_FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass PS words if present in.." "0: DMA controller will pass PS words if present in..,?" newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" newline hexmask.long.byte 0x0 0.--6. 1. "TX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." line.long 0x4 "VIRT_ALIAS_11_UDMAP0__CFG__TCHAN_TCREDIT,The Transfer Request Credit Register indicates how many TR sized buffer slots exist in the associated UTC channel to which this channel is associated. This register only exists for external UTC channels. This.." bitfld.long 0x4 0.--2. "COUNT,Transfer Request Credit Count: this field specifies how many credits for complete TRs are available. This field should be initialized before the channel is enabled and will then increment/decrement as TRs are submitted and responses are received." "0,1,2,3,4,5,6,7" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__TCHAN_TCQ,The Tx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value channel mode. This register may only be written when the channel.." hexmask.long.word 0x0 0.--15. 1. "TXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__TCHAN_TOES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__TCHAN_TEOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_11_UDMAP0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Tx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_11_UDMAP0__CFG__TCHAN_THRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x70++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0x0 0.--12. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_11_UDMAP0_CFG_RCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_11_UDMAP0_CFG_RCHAN)" base ad:0x4BB0C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 15. "RX_IGNORE_SHORT,This field controls whether or not short packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Short packets are treated.." "0: Short packets are treated as exceptions and..,1: Short packets are ignored and the TR will.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline hexmask.long.byte 0x0 0.--6. 1. "RX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__RCHAN_RCQ,The Rx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value TR based channel mode. This register may only be written when the.." hexmask.long.word 0x0 0.--15. 1. "RXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__RCHAN_ROES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__RCHAN_REOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_11_UDMAP0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Rx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_11_UDMAP0__CFG__RCHAN_THRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." rgroup.long 0xF0++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__RCHAN_RFLOW_RNG,The flow range register is used to control which flows other than the default flow (0x3FFF / channel_number) are allowed to be used with this DMA channel." hexmask.long.word 0x0 16.--30. 1. "FLOWID_CNT,Rx Flow ID Count: This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for this channel. A value of 0 indicates that no flow IDs other than the default are allowed for the channel.." newline hexmask.long.word 0x0 0.--13. 1. "FLOWID_START,Rx Starting Flow ID: Beyond the default flow ID each channel can also make use of a single contiguous range of flow IDs and this field specifies the starting index for that range.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_11_UDMAP0_CFG_RFLOW (NAVSS0_UDMAP_0_VIRT_ALIAS_11_UDMAP0_CFG_RFLOW)" base ad:0x4BB0D00000 rgroup.long 0x0++0x1F line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__RFLOW_RFA,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." bitfld.long 0x0 30. "RX_EINFO_PRESENT,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will clear the Extended Packet Info Present bit in.." "0,1" newline bitfld.long 0x0 29. "RX_PSINFO_PRESENT,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will set the PS word count to 0 in the PD and will drop any PS words.." "0,1" newline bitfld.long 0x0 28. "RX_ERROR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor or buffer starvation occurs): 0 = Starvation errors result in dropping packet and reclaiming any used.." "0: Starvation errors result in dropping packet and..,1: Starvation errors result in subsequent re-try of.." newline bitfld.long 0x0 26.--27. "RX_DESC_TYPE,Rx Descriptor Type: This field indicates the descriptor type to use: 0 = Host 1 = RESERVED 2 = Monolithic 3 = RESERVED" "0: Host,1: RESERVED,2: Monolithic,3: RESERVED" newline bitfld.long 0x0 25. "RX_PS_LOCATION,Rx Protocol Specific Location: This bit controls where the Protocol Specific words will be placed in the Host Mode data structure. If this bit is cleared the DMA will clear the Protocol Specific Region Location bit in the PD and will.." "0,1" newline hexmask.long.word 0x0 16.--24. 1. "RX_SOP_OFFSET,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer). This value must be less than the.." newline hexmask.long.word 0x0 0.--15. 1. "RX_DEST_QNUM,Rx Destination Queue: This field indicates the default receive queue that packets on this flow should be placed onto." line.long 0x4 "VIRT_ALIAS_11_UDMAP0__CFG__RFLOW_RFB,The Rx Flow N Configuration Register B contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.byte 0x4 24.--31. 1. "RX_SRC_TAG_HI,Rx Source Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 16.--23. 1. "RX_SRC_TAG_LO,Rx Source Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1." newline hexmask.long.byte 0x4 8.--15. 1. "RX_DEST_TAG_HI,Rx Destination Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 0.--7. 1. "RX_DEST_TAG_LO,Rx Destination Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1." line.long 0x8 "VIRT_ALIAS_11_UDMAP0__CFG__RFLOW_RFC,The Rx Flow N Configuration Register C contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." bitfld.long 0x8 28.--30. "RX_SRC_TAG_HI_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 24.--26. "RX_SRC_TAG_LO_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 20.--22. "RX_DEST_TAG_HI_SEL,Rx Destination Tag High Byte Selector: This field specifies the source for bits 15:8 of the destination tag field in the word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 16.--18. "RX_DEST_TAG_LO_SEL,Rx Destination Tag Low Byte Selector: This field specifies the source for bits 7:0 of the destination tag field in word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 0.--2. "RX_SIZE_THRESH_EN,Rx Packet Sized Based Free Buffer Queue Enables: These bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_threshN fields to determine which FDQ to allocate the.." "0: Do not use the threshold,1: Use the thresholds to select between the 4..,?,?,?,?,?,?" line.long 0xC "VIRT_ALIAS_11_UDMAP0__CFG__RFLOW_RFD,The Rx Flow N Configuration Register D contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0xC 16.--31. 1. "RX_FDQ0_SZ0_QNUM,Rx Free Descriptor 0 Queue Index - Size 0: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value." newline hexmask.long.word 0xC 0.--15. 1. "RX_FDQ1_QNUM,Rx Free Descriptor 1 Queue Index: This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet" line.long 0x10 "VIRT_ALIAS_11_UDMAP0__CFG__RFLOW_RFE,The Rx Flow N Configuration Register E contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x10 16.--31. 1. "RX_FDQ2_QNUM,Rx Free Descriptor 2 Queue Index: This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet" newline hexmask.long.word 0x10 0.--15. 1. "RX_FDQ3_QNUM,Rx Free Descriptor 3 Queue Index: This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet" line.long 0x14 "VIRT_ALIAS_11_UDMAP0__CFG__RFLOW_RFF,The Rx Flow N Configuration Register F contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x14 16.--31. 1. "RX_SIZE_THRESH0,Rx Packet Size Threshold 0: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x14 0.--15. 1. "RX_SIZE_THRESH1,Rx Packet Size Threshold 1: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is greater than the.." line.long 0x18 "VIRT_ALIAS_11_UDMAP0__CFG__RFLOW_RFG,The Rx Flow N Configuration Register G contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x18 16.--31. 1. "RX_SIZE_THRESH2,Rx Packet Size Threshold 2: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x18 0.--15. 1. "RX_FDQ0_SZ1_QNUM,Rx Free Descriptor 0 Queue Index - Size 1: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value. This field is optional." line.long 0x1C "VIRT_ALIAS_11_UDMAP0__CFG__RFLOW_RFH,The Rx Flow N Configuration Register H contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x1C 16.--31. 1. "RX_FDQ0_SZ2_QNUM,Rx Free Descriptor 0 Queue Index - Size 2: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size1 value. This field is optional." newline hexmask.long.word 0x1C 0.--15. 1. "RX_FDQ0_SZ3_QNUM,Rx Free Descriptor 0 Queue Index - Size 3: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size2 value. This field is optional." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_11_UDMAP0_CFG_GCFG (NAVSS0_UDMAP_0_VIRT_ALIAS_11_UDMAP0_CFG_GCFG)" base ad:0x4BB1150000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the UDMA-P in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This field sets the timeout duration in clock cycles. This field controls the minimum amount of time that an Rx channel will be required to wait when it encounters a buffer starvation condition and the Rx error handling bit is set to 1.." line.long 0x4 "VIRT_ALIAS_11_UDMAP0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x1C++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__GCFG_UTC_CTRL,The external UTC control register provides a mapping of logical to physical thread IDs ." hexmask.long.word 0x0 0.--15. 1. "UTC_CHAN_START,This field specifies the starting PSI-L thread number for the external UTC" rgroup.long 0x20++0xF line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this UDMA-P instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_11_UDMAP0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this UDMA-P instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_11_UDMAP0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx internal channel count" hexmask.long.word 0x8 9.--17. 1. "ECHAN_CNT,Tx external channel count" hexmask.long.word 0x8 0.--8. 1. "TCHAN_CNT,Tx internal channel count" line.long 0xC "VIRT_ALIAS_11_UDMAP0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,Tx ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,Tx high capacity internal channel count" hexmask.long.word 0xC 0.--13. 1. "RFLOW_CNT,Rx flow table entry count" rgroup.long 0x40++0xF line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__GCFG_PERF0,This register provides thresholds for outstanding virtualized read/write commands from interface mem0" hexmask.long.byte 0x0 16.--23. 1. "VRD_THRESH0,Virt read command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x0 0.--7. 1. "VWR_THRESH0,Virt write command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x4 "VIRT_ALIAS_11_UDMAP0__CFG__GCFG_PERF1,This register provides thresholds for outstanding virtualized read/write commands from interface mem1" hexmask.long.byte 0x4 16.--23. 1. "VRD_THRESH1,Virt read command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x4 0.--7. 1. "VWR_THRESH1,Virt write command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x8 "VIRT_ALIAS_11_UDMAP0__CFG__GCFG_PERF2,This register provides thresholds for outstanding virtualized read commands from interface memr" hexmask.long.byte 0x8 16.--23. 1. "VRD_THRESH2,Virt read command throttling threshold for memr. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." line.long 0xC "VIRT_ALIAS_11_UDMAP0__CFG__GCFG_PERF3,This register provides thresholds for outstanding virtualized write commands from interface memw" hexmask.long.byte 0xC 0.--7. 1. "VWR_THRESH3,Virt write command throttling threshold for memw. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x0 0.--31. 1. "NOGATE_LO,When set inhibits automatic gating of clock." line.long 0x4 "VIRT_ALIAS_11_UDMAP0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x4 0.--31. 1. "NOGATE_HI,When set inhibits automatic gating of clock." rgroup.long 0x78++0xB line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_11_UDMAP0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" line.long 0x8 "VIRT_ALIAS_11_UDMAP0__CFG__GCFG_RFLOWFWOES,The Rx Flow FW OES Register specifies a destination event number to which an event should be sent if an out of range flow ID is received on a packet." hexmask.long.word 0x8 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__GCFG_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check. Values in this register will remain persistent once an exception has been.." bitfld.long 0x0 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet. Once this bit is set the remaining fields in this register will not be modified. SW is required to write this bit to 0 to allow another.." "0,1" hexmask.long.word 0x0 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet" hexmask.long.word 0x0 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_11_UDMAP0_CFG_RCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_11_UDMAP0_CFG_RCHANRT)" base ad:0x4BB4000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the rx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_11_UDMAP0_CFG_TCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_11_UDMAP0_CFG_TCHANRT)" base ad:0x4BB5000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_11_UDMAP0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_12_UDMAP0_CFG_TCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_12_UDMAP0_CFG_TCHAN)" base ad:0x4BC0B00000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 30. "TX_FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass extended.." "0: DMA controller will pass extended packet info..,?" newline bitfld.long 0x0 29. "TX_FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass PS words if present in.." "0: DMA controller will pass PS words if present in..,?" newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" newline hexmask.long.byte 0x0 0.--6. 1. "TX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." line.long 0x4 "VIRT_ALIAS_12_UDMAP0__CFG__TCHAN_TCREDIT,The Transfer Request Credit Register indicates how many TR sized buffer slots exist in the associated UTC channel to which this channel is associated. This register only exists for external UTC channels. This.." bitfld.long 0x4 0.--2. "COUNT,Transfer Request Credit Count: this field specifies how many credits for complete TRs are available. This field should be initialized before the channel is enabled and will then increment/decrement as TRs are submitted and responses are received." "0,1,2,3,4,5,6,7" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__TCHAN_TCQ,The Tx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value channel mode. This register may only be written when the channel.." hexmask.long.word 0x0 0.--15. 1. "TXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__TCHAN_TOES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__TCHAN_TEOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_12_UDMAP0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Tx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_12_UDMAP0__CFG__TCHAN_THRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x70++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0x0 0.--12. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_12_UDMAP0_CFG_RCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_12_UDMAP0_CFG_RCHAN)" base ad:0x4BC0C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 15. "RX_IGNORE_SHORT,This field controls whether or not short packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Short packets are treated.." "0: Short packets are treated as exceptions and..,1: Short packets are ignored and the TR will.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline hexmask.long.byte 0x0 0.--6. 1. "RX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__RCHAN_RCQ,The Rx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value TR based channel mode. This register may only be written when the.." hexmask.long.word 0x0 0.--15. 1. "RXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__RCHAN_ROES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__RCHAN_REOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_12_UDMAP0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Rx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_12_UDMAP0__CFG__RCHAN_THRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." rgroup.long 0xF0++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__RCHAN_RFLOW_RNG,The flow range register is used to control which flows other than the default flow (0x3FFF / channel_number) are allowed to be used with this DMA channel." hexmask.long.word 0x0 16.--30. 1. "FLOWID_CNT,Rx Flow ID Count: This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for this channel. A value of 0 indicates that no flow IDs other than the default are allowed for the channel.." newline hexmask.long.word 0x0 0.--13. 1. "FLOWID_START,Rx Starting Flow ID: Beyond the default flow ID each channel can also make use of a single contiguous range of flow IDs and this field specifies the starting index for that range.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_12_UDMAP0_CFG_RFLOW (NAVSS0_UDMAP_0_VIRT_ALIAS_12_UDMAP0_CFG_RFLOW)" base ad:0x4BC0D00000 rgroup.long 0x0++0x1F line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__RFLOW_RFA,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." bitfld.long 0x0 30. "RX_EINFO_PRESENT,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will clear the Extended Packet Info Present bit in.." "0,1" newline bitfld.long 0x0 29. "RX_PSINFO_PRESENT,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will set the PS word count to 0 in the PD and will drop any PS words.." "0,1" newline bitfld.long 0x0 28. "RX_ERROR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor or buffer starvation occurs): 0 = Starvation errors result in dropping packet and reclaiming any used.." "0: Starvation errors result in dropping packet and..,1: Starvation errors result in subsequent re-try of.." newline bitfld.long 0x0 26.--27. "RX_DESC_TYPE,Rx Descriptor Type: This field indicates the descriptor type to use: 0 = Host 1 = RESERVED 2 = Monolithic 3 = RESERVED" "0: Host,1: RESERVED,2: Monolithic,3: RESERVED" newline bitfld.long 0x0 25. "RX_PS_LOCATION,Rx Protocol Specific Location: This bit controls where the Protocol Specific words will be placed in the Host Mode data structure. If this bit is cleared the DMA will clear the Protocol Specific Region Location bit in the PD and will.." "0,1" newline hexmask.long.word 0x0 16.--24. 1. "RX_SOP_OFFSET,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer). This value must be less than the.." newline hexmask.long.word 0x0 0.--15. 1. "RX_DEST_QNUM,Rx Destination Queue: This field indicates the default receive queue that packets on this flow should be placed onto." line.long 0x4 "VIRT_ALIAS_12_UDMAP0__CFG__RFLOW_RFB,The Rx Flow N Configuration Register B contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.byte 0x4 24.--31. 1. "RX_SRC_TAG_HI,Rx Source Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 16.--23. 1. "RX_SRC_TAG_LO,Rx Source Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1." newline hexmask.long.byte 0x4 8.--15. 1. "RX_DEST_TAG_HI,Rx Destination Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 0.--7. 1. "RX_DEST_TAG_LO,Rx Destination Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1." line.long 0x8 "VIRT_ALIAS_12_UDMAP0__CFG__RFLOW_RFC,The Rx Flow N Configuration Register C contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." bitfld.long 0x8 28.--30. "RX_SRC_TAG_HI_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 24.--26. "RX_SRC_TAG_LO_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 20.--22. "RX_DEST_TAG_HI_SEL,Rx Destination Tag High Byte Selector: This field specifies the source for bits 15:8 of the destination tag field in the word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 16.--18. "RX_DEST_TAG_LO_SEL,Rx Destination Tag Low Byte Selector: This field specifies the source for bits 7:0 of the destination tag field in word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 0.--2. "RX_SIZE_THRESH_EN,Rx Packet Sized Based Free Buffer Queue Enables: These bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_threshN fields to determine which FDQ to allocate the.." "0: Do not use the threshold,1: Use the thresholds to select between the 4..,?,?,?,?,?,?" line.long 0xC "VIRT_ALIAS_12_UDMAP0__CFG__RFLOW_RFD,The Rx Flow N Configuration Register D contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0xC 16.--31. 1. "RX_FDQ0_SZ0_QNUM,Rx Free Descriptor 0 Queue Index - Size 0: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value." newline hexmask.long.word 0xC 0.--15. 1. "RX_FDQ1_QNUM,Rx Free Descriptor 1 Queue Index: This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet" line.long 0x10 "VIRT_ALIAS_12_UDMAP0__CFG__RFLOW_RFE,The Rx Flow N Configuration Register E contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x10 16.--31. 1. "RX_FDQ2_QNUM,Rx Free Descriptor 2 Queue Index: This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet" newline hexmask.long.word 0x10 0.--15. 1. "RX_FDQ3_QNUM,Rx Free Descriptor 3 Queue Index: This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet" line.long 0x14 "VIRT_ALIAS_12_UDMAP0__CFG__RFLOW_RFF,The Rx Flow N Configuration Register F contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x14 16.--31. 1. "RX_SIZE_THRESH0,Rx Packet Size Threshold 0: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x14 0.--15. 1. "RX_SIZE_THRESH1,Rx Packet Size Threshold 1: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is greater than the.." line.long 0x18 "VIRT_ALIAS_12_UDMAP0__CFG__RFLOW_RFG,The Rx Flow N Configuration Register G contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x18 16.--31. 1. "RX_SIZE_THRESH2,Rx Packet Size Threshold 2: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x18 0.--15. 1. "RX_FDQ0_SZ1_QNUM,Rx Free Descriptor 0 Queue Index - Size 1: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value. This field is optional." line.long 0x1C "VIRT_ALIAS_12_UDMAP0__CFG__RFLOW_RFH,The Rx Flow N Configuration Register H contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x1C 16.--31. 1. "RX_FDQ0_SZ2_QNUM,Rx Free Descriptor 0 Queue Index - Size 2: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size1 value. This field is optional." newline hexmask.long.word 0x1C 0.--15. 1. "RX_FDQ0_SZ3_QNUM,Rx Free Descriptor 0 Queue Index - Size 3: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size2 value. This field is optional." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_12_UDMAP0_CFG_GCFG (NAVSS0_UDMAP_0_VIRT_ALIAS_12_UDMAP0_CFG_GCFG)" base ad:0x4BC1150000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the UDMA-P in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This field sets the timeout duration in clock cycles. This field controls the minimum amount of time that an Rx channel will be required to wait when it encounters a buffer starvation condition and the Rx error handling bit is set to 1.." line.long 0x4 "VIRT_ALIAS_12_UDMAP0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x1C++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__GCFG_UTC_CTRL,The external UTC control register provides a mapping of logical to physical thread IDs ." hexmask.long.word 0x0 0.--15. 1. "UTC_CHAN_START,This field specifies the starting PSI-L thread number for the external UTC" rgroup.long 0x20++0xF line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this UDMA-P instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_12_UDMAP0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this UDMA-P instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_12_UDMAP0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx internal channel count" hexmask.long.word 0x8 9.--17. 1. "ECHAN_CNT,Tx external channel count" hexmask.long.word 0x8 0.--8. 1. "TCHAN_CNT,Tx internal channel count" line.long 0xC "VIRT_ALIAS_12_UDMAP0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,Tx ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,Tx high capacity internal channel count" hexmask.long.word 0xC 0.--13. 1. "RFLOW_CNT,Rx flow table entry count" rgroup.long 0x40++0xF line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__GCFG_PERF0,This register provides thresholds for outstanding virtualized read/write commands from interface mem0" hexmask.long.byte 0x0 16.--23. 1. "VRD_THRESH0,Virt read command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x0 0.--7. 1. "VWR_THRESH0,Virt write command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x4 "VIRT_ALIAS_12_UDMAP0__CFG__GCFG_PERF1,This register provides thresholds for outstanding virtualized read/write commands from interface mem1" hexmask.long.byte 0x4 16.--23. 1. "VRD_THRESH1,Virt read command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x4 0.--7. 1. "VWR_THRESH1,Virt write command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x8 "VIRT_ALIAS_12_UDMAP0__CFG__GCFG_PERF2,This register provides thresholds for outstanding virtualized read commands from interface memr" hexmask.long.byte 0x8 16.--23. 1. "VRD_THRESH2,Virt read command throttling threshold for memr. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." line.long 0xC "VIRT_ALIAS_12_UDMAP0__CFG__GCFG_PERF3,This register provides thresholds for outstanding virtualized write commands from interface memw" hexmask.long.byte 0xC 0.--7. 1. "VWR_THRESH3,Virt write command throttling threshold for memw. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x0 0.--31. 1. "NOGATE_LO,When set inhibits automatic gating of clock." line.long 0x4 "VIRT_ALIAS_12_UDMAP0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x4 0.--31. 1. "NOGATE_HI,When set inhibits automatic gating of clock." rgroup.long 0x78++0xB line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_12_UDMAP0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" line.long 0x8 "VIRT_ALIAS_12_UDMAP0__CFG__GCFG_RFLOWFWOES,The Rx Flow FW OES Register specifies a destination event number to which an event should be sent if an out of range flow ID is received on a packet." hexmask.long.word 0x8 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__GCFG_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check. Values in this register will remain persistent once an exception has been.." bitfld.long 0x0 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet. Once this bit is set the remaining fields in this register will not be modified. SW is required to write this bit to 0 to allow another.." "0,1" hexmask.long.word 0x0 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet" hexmask.long.word 0x0 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_12_UDMAP0_CFG_RCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_12_UDMAP0_CFG_RCHANRT)" base ad:0x4BC4000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the rx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_12_UDMAP0_CFG_TCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_12_UDMAP0_CFG_TCHANRT)" base ad:0x4BC5000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_12_UDMAP0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_13_UDMAP0_CFG_TCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_13_UDMAP0_CFG_TCHAN)" base ad:0x4BD0B00000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 30. "TX_FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass extended.." "0: DMA controller will pass extended packet info..,?" newline bitfld.long 0x0 29. "TX_FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass PS words if present in.." "0: DMA controller will pass PS words if present in..,?" newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" newline hexmask.long.byte 0x0 0.--6. 1. "TX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." line.long 0x4 "VIRT_ALIAS_13_UDMAP0__CFG__TCHAN_TCREDIT,The Transfer Request Credit Register indicates how many TR sized buffer slots exist in the associated UTC channel to which this channel is associated. This register only exists for external UTC channels. This.." bitfld.long 0x4 0.--2. "COUNT,Transfer Request Credit Count: this field specifies how many credits for complete TRs are available. This field should be initialized before the channel is enabled and will then increment/decrement as TRs are submitted and responses are received." "0,1,2,3,4,5,6,7" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__TCHAN_TCQ,The Tx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value channel mode. This register may only be written when the channel.." hexmask.long.word 0x0 0.--15. 1. "TXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__TCHAN_TOES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__TCHAN_TEOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_13_UDMAP0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Tx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_13_UDMAP0__CFG__TCHAN_THRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x70++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0x0 0.--12. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_13_UDMAP0_CFG_RCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_13_UDMAP0_CFG_RCHAN)" base ad:0x4BD0C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 15. "RX_IGNORE_SHORT,This field controls whether or not short packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Short packets are treated.." "0: Short packets are treated as exceptions and..,1: Short packets are ignored and the TR will.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline hexmask.long.byte 0x0 0.--6. 1. "RX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__RCHAN_RCQ,The Rx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value TR based channel mode. This register may only be written when the.." hexmask.long.word 0x0 0.--15. 1. "RXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__RCHAN_ROES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__RCHAN_REOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_13_UDMAP0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Rx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_13_UDMAP0__CFG__RCHAN_THRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." rgroup.long 0xF0++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__RCHAN_RFLOW_RNG,The flow range register is used to control which flows other than the default flow (0x3FFF / channel_number) are allowed to be used with this DMA channel." hexmask.long.word 0x0 16.--30. 1. "FLOWID_CNT,Rx Flow ID Count: This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for this channel. A value of 0 indicates that no flow IDs other than the default are allowed for the channel.." newline hexmask.long.word 0x0 0.--13. 1. "FLOWID_START,Rx Starting Flow ID: Beyond the default flow ID each channel can also make use of a single contiguous range of flow IDs and this field specifies the starting index for that range.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_13_UDMAP0_CFG_RFLOW (NAVSS0_UDMAP_0_VIRT_ALIAS_13_UDMAP0_CFG_RFLOW)" base ad:0x4BD0D00000 rgroup.long 0x0++0x1F line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__RFLOW_RFA,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." bitfld.long 0x0 30. "RX_EINFO_PRESENT,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will clear the Extended Packet Info Present bit in.." "0,1" newline bitfld.long 0x0 29. "RX_PSINFO_PRESENT,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will set the PS word count to 0 in the PD and will drop any PS words.." "0,1" newline bitfld.long 0x0 28. "RX_ERROR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor or buffer starvation occurs): 0 = Starvation errors result in dropping packet and reclaiming any used.." "0: Starvation errors result in dropping packet and..,1: Starvation errors result in subsequent re-try of.." newline bitfld.long 0x0 26.--27. "RX_DESC_TYPE,Rx Descriptor Type: This field indicates the descriptor type to use: 0 = Host 1 = RESERVED 2 = Monolithic 3 = RESERVED" "0: Host,1: RESERVED,2: Monolithic,3: RESERVED" newline bitfld.long 0x0 25. "RX_PS_LOCATION,Rx Protocol Specific Location: This bit controls where the Protocol Specific words will be placed in the Host Mode data structure. If this bit is cleared the DMA will clear the Protocol Specific Region Location bit in the PD and will.." "0,1" newline hexmask.long.word 0x0 16.--24. 1. "RX_SOP_OFFSET,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer). This value must be less than the.." newline hexmask.long.word 0x0 0.--15. 1. "RX_DEST_QNUM,Rx Destination Queue: This field indicates the default receive queue that packets on this flow should be placed onto." line.long 0x4 "VIRT_ALIAS_13_UDMAP0__CFG__RFLOW_RFB,The Rx Flow N Configuration Register B contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.byte 0x4 24.--31. 1. "RX_SRC_TAG_HI,Rx Source Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 16.--23. 1. "RX_SRC_TAG_LO,Rx Source Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1." newline hexmask.long.byte 0x4 8.--15. 1. "RX_DEST_TAG_HI,Rx Destination Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 0.--7. 1. "RX_DEST_TAG_LO,Rx Destination Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1." line.long 0x8 "VIRT_ALIAS_13_UDMAP0__CFG__RFLOW_RFC,The Rx Flow N Configuration Register C contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." bitfld.long 0x8 28.--30. "RX_SRC_TAG_HI_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 24.--26. "RX_SRC_TAG_LO_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 20.--22. "RX_DEST_TAG_HI_SEL,Rx Destination Tag High Byte Selector: This field specifies the source for bits 15:8 of the destination tag field in the word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 16.--18. "RX_DEST_TAG_LO_SEL,Rx Destination Tag Low Byte Selector: This field specifies the source for bits 7:0 of the destination tag field in word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 0.--2. "RX_SIZE_THRESH_EN,Rx Packet Sized Based Free Buffer Queue Enables: These bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_threshN fields to determine which FDQ to allocate the.." "0: Do not use the threshold,1: Use the thresholds to select between the 4..,?,?,?,?,?,?" line.long 0xC "VIRT_ALIAS_13_UDMAP0__CFG__RFLOW_RFD,The Rx Flow N Configuration Register D contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0xC 16.--31. 1. "RX_FDQ0_SZ0_QNUM,Rx Free Descriptor 0 Queue Index - Size 0: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value." newline hexmask.long.word 0xC 0.--15. 1. "RX_FDQ1_QNUM,Rx Free Descriptor 1 Queue Index: This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet" line.long 0x10 "VIRT_ALIAS_13_UDMAP0__CFG__RFLOW_RFE,The Rx Flow N Configuration Register E contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x10 16.--31. 1. "RX_FDQ2_QNUM,Rx Free Descriptor 2 Queue Index: This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet" newline hexmask.long.word 0x10 0.--15. 1. "RX_FDQ3_QNUM,Rx Free Descriptor 3 Queue Index: This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet" line.long 0x14 "VIRT_ALIAS_13_UDMAP0__CFG__RFLOW_RFF,The Rx Flow N Configuration Register F contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x14 16.--31. 1. "RX_SIZE_THRESH0,Rx Packet Size Threshold 0: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x14 0.--15. 1. "RX_SIZE_THRESH1,Rx Packet Size Threshold 1: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is greater than the.." line.long 0x18 "VIRT_ALIAS_13_UDMAP0__CFG__RFLOW_RFG,The Rx Flow N Configuration Register G contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x18 16.--31. 1. "RX_SIZE_THRESH2,Rx Packet Size Threshold 2: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x18 0.--15. 1. "RX_FDQ0_SZ1_QNUM,Rx Free Descriptor 0 Queue Index - Size 1: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value. This field is optional." line.long 0x1C "VIRT_ALIAS_13_UDMAP0__CFG__RFLOW_RFH,The Rx Flow N Configuration Register H contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x1C 16.--31. 1. "RX_FDQ0_SZ2_QNUM,Rx Free Descriptor 0 Queue Index - Size 2: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size1 value. This field is optional." newline hexmask.long.word 0x1C 0.--15. 1. "RX_FDQ0_SZ3_QNUM,Rx Free Descriptor 0 Queue Index - Size 3: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size2 value. This field is optional." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_13_UDMAP0_CFG_GCFG (NAVSS0_UDMAP_0_VIRT_ALIAS_13_UDMAP0_CFG_GCFG)" base ad:0x4BD1150000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the UDMA-P in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This field sets the timeout duration in clock cycles. This field controls the minimum amount of time that an Rx channel will be required to wait when it encounters a buffer starvation condition and the Rx error handling bit is set to 1.." line.long 0x4 "VIRT_ALIAS_13_UDMAP0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x1C++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__GCFG_UTC_CTRL,The external UTC control register provides a mapping of logical to physical thread IDs ." hexmask.long.word 0x0 0.--15. 1. "UTC_CHAN_START,This field specifies the starting PSI-L thread number for the external UTC" rgroup.long 0x20++0xF line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this UDMA-P instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_13_UDMAP0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this UDMA-P instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_13_UDMAP0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx internal channel count" hexmask.long.word 0x8 9.--17. 1. "ECHAN_CNT,Tx external channel count" hexmask.long.word 0x8 0.--8. 1. "TCHAN_CNT,Tx internal channel count" line.long 0xC "VIRT_ALIAS_13_UDMAP0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,Tx ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,Tx high capacity internal channel count" hexmask.long.word 0xC 0.--13. 1. "RFLOW_CNT,Rx flow table entry count" rgroup.long 0x40++0xF line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__GCFG_PERF0,This register provides thresholds for outstanding virtualized read/write commands from interface mem0" hexmask.long.byte 0x0 16.--23. 1. "VRD_THRESH0,Virt read command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x0 0.--7. 1. "VWR_THRESH0,Virt write command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x4 "VIRT_ALIAS_13_UDMAP0__CFG__GCFG_PERF1,This register provides thresholds for outstanding virtualized read/write commands from interface mem1" hexmask.long.byte 0x4 16.--23. 1. "VRD_THRESH1,Virt read command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x4 0.--7. 1. "VWR_THRESH1,Virt write command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x8 "VIRT_ALIAS_13_UDMAP0__CFG__GCFG_PERF2,This register provides thresholds for outstanding virtualized read commands from interface memr" hexmask.long.byte 0x8 16.--23. 1. "VRD_THRESH2,Virt read command throttling threshold for memr. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." line.long 0xC "VIRT_ALIAS_13_UDMAP0__CFG__GCFG_PERF3,This register provides thresholds for outstanding virtualized write commands from interface memw" hexmask.long.byte 0xC 0.--7. 1. "VWR_THRESH3,Virt write command throttling threshold for memw. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x0 0.--31. 1. "NOGATE_LO,When set inhibits automatic gating of clock." line.long 0x4 "VIRT_ALIAS_13_UDMAP0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x4 0.--31. 1. "NOGATE_HI,When set inhibits automatic gating of clock." rgroup.long 0x78++0xB line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_13_UDMAP0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" line.long 0x8 "VIRT_ALIAS_13_UDMAP0__CFG__GCFG_RFLOWFWOES,The Rx Flow FW OES Register specifies a destination event number to which an event should be sent if an out of range flow ID is received on a packet." hexmask.long.word 0x8 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__GCFG_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check. Values in this register will remain persistent once an exception has been.." bitfld.long 0x0 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet. Once this bit is set the remaining fields in this register will not be modified. SW is required to write this bit to 0 to allow another.." "0,1" hexmask.long.word 0x0 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet" hexmask.long.word 0x0 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_13_UDMAP0_CFG_RCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_13_UDMAP0_CFG_RCHANRT)" base ad:0x4BD4000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the rx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_13_UDMAP0_CFG_TCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_13_UDMAP0_CFG_TCHANRT)" base ad:0x4BD5000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_13_UDMAP0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_14_UDMAP0_CFG_TCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_14_UDMAP0_CFG_TCHAN)" base ad:0x4BE0B00000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 30. "TX_FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass extended.." "0: DMA controller will pass extended packet info..,?" newline bitfld.long 0x0 29. "TX_FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass PS words if present in.." "0: DMA controller will pass PS words if present in..,?" newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" newline hexmask.long.byte 0x0 0.--6. 1. "TX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." line.long 0x4 "VIRT_ALIAS_14_UDMAP0__CFG__TCHAN_TCREDIT,The Transfer Request Credit Register indicates how many TR sized buffer slots exist in the associated UTC channel to which this channel is associated. This register only exists for external UTC channels. This.." bitfld.long 0x4 0.--2. "COUNT,Transfer Request Credit Count: this field specifies how many credits for complete TRs are available. This field should be initialized before the channel is enabled and will then increment/decrement as TRs are submitted and responses are received." "0,1,2,3,4,5,6,7" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__TCHAN_TCQ,The Tx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value channel mode. This register may only be written when the channel.." hexmask.long.word 0x0 0.--15. 1. "TXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__TCHAN_TOES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__TCHAN_TEOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_14_UDMAP0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Tx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_14_UDMAP0__CFG__TCHAN_THRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x70++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0x0 0.--12. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_14_UDMAP0_CFG_RCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_14_UDMAP0_CFG_RCHAN)" base ad:0x4BE0C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 15. "RX_IGNORE_SHORT,This field controls whether or not short packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Short packets are treated.." "0: Short packets are treated as exceptions and..,1: Short packets are ignored and the TR will.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline hexmask.long.byte 0x0 0.--6. 1. "RX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__RCHAN_RCQ,The Rx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value TR based channel mode. This register may only be written when the.." hexmask.long.word 0x0 0.--15. 1. "RXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__RCHAN_ROES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__RCHAN_REOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_14_UDMAP0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Rx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_14_UDMAP0__CFG__RCHAN_THRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." rgroup.long 0xF0++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__RCHAN_RFLOW_RNG,The flow range register is used to control which flows other than the default flow (0x3FFF / channel_number) are allowed to be used with this DMA channel." hexmask.long.word 0x0 16.--30. 1. "FLOWID_CNT,Rx Flow ID Count: This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for this channel. A value of 0 indicates that no flow IDs other than the default are allowed for the channel.." newline hexmask.long.word 0x0 0.--13. 1. "FLOWID_START,Rx Starting Flow ID: Beyond the default flow ID each channel can also make use of a single contiguous range of flow IDs and this field specifies the starting index for that range.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_14_UDMAP0_CFG_RFLOW (NAVSS0_UDMAP_0_VIRT_ALIAS_14_UDMAP0_CFG_RFLOW)" base ad:0x4BE0D00000 rgroup.long 0x0++0x1F line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__RFLOW_RFA,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." bitfld.long 0x0 30. "RX_EINFO_PRESENT,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will clear the Extended Packet Info Present bit in.." "0,1" newline bitfld.long 0x0 29. "RX_PSINFO_PRESENT,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will set the PS word count to 0 in the PD and will drop any PS words.." "0,1" newline bitfld.long 0x0 28. "RX_ERROR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor or buffer starvation occurs): 0 = Starvation errors result in dropping packet and reclaiming any used.." "0: Starvation errors result in dropping packet and..,1: Starvation errors result in subsequent re-try of.." newline bitfld.long 0x0 26.--27. "RX_DESC_TYPE,Rx Descriptor Type: This field indicates the descriptor type to use: 0 = Host 1 = RESERVED 2 = Monolithic 3 = RESERVED" "0: Host,1: RESERVED,2: Monolithic,3: RESERVED" newline bitfld.long 0x0 25. "RX_PS_LOCATION,Rx Protocol Specific Location: This bit controls where the Protocol Specific words will be placed in the Host Mode data structure. If this bit is cleared the DMA will clear the Protocol Specific Region Location bit in the PD and will.." "0,1" newline hexmask.long.word 0x0 16.--24. 1. "RX_SOP_OFFSET,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer). This value must be less than the.." newline hexmask.long.word 0x0 0.--15. 1. "RX_DEST_QNUM,Rx Destination Queue: This field indicates the default receive queue that packets on this flow should be placed onto." line.long 0x4 "VIRT_ALIAS_14_UDMAP0__CFG__RFLOW_RFB,The Rx Flow N Configuration Register B contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.byte 0x4 24.--31. 1. "RX_SRC_TAG_HI,Rx Source Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 16.--23. 1. "RX_SRC_TAG_LO,Rx Source Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1." newline hexmask.long.byte 0x4 8.--15. 1. "RX_DEST_TAG_HI,Rx Destination Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 0.--7. 1. "RX_DEST_TAG_LO,Rx Destination Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1." line.long 0x8 "VIRT_ALIAS_14_UDMAP0__CFG__RFLOW_RFC,The Rx Flow N Configuration Register C contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." bitfld.long 0x8 28.--30. "RX_SRC_TAG_HI_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 24.--26. "RX_SRC_TAG_LO_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 20.--22. "RX_DEST_TAG_HI_SEL,Rx Destination Tag High Byte Selector: This field specifies the source for bits 15:8 of the destination tag field in the word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 16.--18. "RX_DEST_TAG_LO_SEL,Rx Destination Tag Low Byte Selector: This field specifies the source for bits 7:0 of the destination tag field in word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 0.--2. "RX_SIZE_THRESH_EN,Rx Packet Sized Based Free Buffer Queue Enables: These bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_threshN fields to determine which FDQ to allocate the.." "0: Do not use the threshold,1: Use the thresholds to select between the 4..,?,?,?,?,?,?" line.long 0xC "VIRT_ALIAS_14_UDMAP0__CFG__RFLOW_RFD,The Rx Flow N Configuration Register D contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0xC 16.--31. 1. "RX_FDQ0_SZ0_QNUM,Rx Free Descriptor 0 Queue Index - Size 0: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value." newline hexmask.long.word 0xC 0.--15. 1. "RX_FDQ1_QNUM,Rx Free Descriptor 1 Queue Index: This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet" line.long 0x10 "VIRT_ALIAS_14_UDMAP0__CFG__RFLOW_RFE,The Rx Flow N Configuration Register E contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x10 16.--31. 1. "RX_FDQ2_QNUM,Rx Free Descriptor 2 Queue Index: This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet" newline hexmask.long.word 0x10 0.--15. 1. "RX_FDQ3_QNUM,Rx Free Descriptor 3 Queue Index: This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet" line.long 0x14 "VIRT_ALIAS_14_UDMAP0__CFG__RFLOW_RFF,The Rx Flow N Configuration Register F contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x14 16.--31. 1. "RX_SIZE_THRESH0,Rx Packet Size Threshold 0: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x14 0.--15. 1. "RX_SIZE_THRESH1,Rx Packet Size Threshold 1: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is greater than the.." line.long 0x18 "VIRT_ALIAS_14_UDMAP0__CFG__RFLOW_RFG,The Rx Flow N Configuration Register G contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x18 16.--31. 1. "RX_SIZE_THRESH2,Rx Packet Size Threshold 2: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x18 0.--15. 1. "RX_FDQ0_SZ1_QNUM,Rx Free Descriptor 0 Queue Index - Size 1: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value. This field is optional." line.long 0x1C "VIRT_ALIAS_14_UDMAP0__CFG__RFLOW_RFH,The Rx Flow N Configuration Register H contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x1C 16.--31. 1. "RX_FDQ0_SZ2_QNUM,Rx Free Descriptor 0 Queue Index - Size 2: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size1 value. This field is optional." newline hexmask.long.word 0x1C 0.--15. 1. "RX_FDQ0_SZ3_QNUM,Rx Free Descriptor 0 Queue Index - Size 3: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size2 value. This field is optional." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_14_UDMAP0_CFG_GCFG (NAVSS0_UDMAP_0_VIRT_ALIAS_14_UDMAP0_CFG_GCFG)" base ad:0x4BE1150000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the UDMA-P in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This field sets the timeout duration in clock cycles. This field controls the minimum amount of time that an Rx channel will be required to wait when it encounters a buffer starvation condition and the Rx error handling bit is set to 1.." line.long 0x4 "VIRT_ALIAS_14_UDMAP0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x1C++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__GCFG_UTC_CTRL,The external UTC control register provides a mapping of logical to physical thread IDs ." hexmask.long.word 0x0 0.--15. 1. "UTC_CHAN_START,This field specifies the starting PSI-L thread number for the external UTC" rgroup.long 0x20++0xF line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this UDMA-P instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_14_UDMAP0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this UDMA-P instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_14_UDMAP0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx internal channel count" hexmask.long.word 0x8 9.--17. 1. "ECHAN_CNT,Tx external channel count" hexmask.long.word 0x8 0.--8. 1. "TCHAN_CNT,Tx internal channel count" line.long 0xC "VIRT_ALIAS_14_UDMAP0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,Tx ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,Tx high capacity internal channel count" hexmask.long.word 0xC 0.--13. 1. "RFLOW_CNT,Rx flow table entry count" rgroup.long 0x40++0xF line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__GCFG_PERF0,This register provides thresholds for outstanding virtualized read/write commands from interface mem0" hexmask.long.byte 0x0 16.--23. 1. "VRD_THRESH0,Virt read command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x0 0.--7. 1. "VWR_THRESH0,Virt write command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x4 "VIRT_ALIAS_14_UDMAP0__CFG__GCFG_PERF1,This register provides thresholds for outstanding virtualized read/write commands from interface mem1" hexmask.long.byte 0x4 16.--23. 1. "VRD_THRESH1,Virt read command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x4 0.--7. 1. "VWR_THRESH1,Virt write command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x8 "VIRT_ALIAS_14_UDMAP0__CFG__GCFG_PERF2,This register provides thresholds for outstanding virtualized read commands from interface memr" hexmask.long.byte 0x8 16.--23. 1. "VRD_THRESH2,Virt read command throttling threshold for memr. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." line.long 0xC "VIRT_ALIAS_14_UDMAP0__CFG__GCFG_PERF3,This register provides thresholds for outstanding virtualized write commands from interface memw" hexmask.long.byte 0xC 0.--7. 1. "VWR_THRESH3,Virt write command throttling threshold for memw. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x0 0.--31. 1. "NOGATE_LO,When set inhibits automatic gating of clock." line.long 0x4 "VIRT_ALIAS_14_UDMAP0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x4 0.--31. 1. "NOGATE_HI,When set inhibits automatic gating of clock." rgroup.long 0x78++0xB line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_14_UDMAP0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" line.long 0x8 "VIRT_ALIAS_14_UDMAP0__CFG__GCFG_RFLOWFWOES,The Rx Flow FW OES Register specifies a destination event number to which an event should be sent if an out of range flow ID is received on a packet." hexmask.long.word 0x8 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__GCFG_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check. Values in this register will remain persistent once an exception has been.." bitfld.long 0x0 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet. Once this bit is set the remaining fields in this register will not be modified. SW is required to write this bit to 0 to allow another.." "0,1" hexmask.long.word 0x0 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet" hexmask.long.word 0x0 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_14_UDMAP0_CFG_RCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_14_UDMAP0_CFG_RCHANRT)" base ad:0x4BE4000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the rx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_14_UDMAP0_CFG_TCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_14_UDMAP0_CFG_TCHANRT)" base ad:0x4BE5000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_14_UDMAP0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_15_UDMAP0_CFG_TCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_15_UDMAP0_CFG_TCHAN)" base ad:0x4BF0B00000 rgroup.long 0x0++0x7 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 30. "TX_FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass extended.." "0: DMA controller will pass extended packet info..,?" newline bitfld.long 0x0 29. "TX_FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass PS words if present in.." "0: DMA controller will pass PS words if present in..,?" newline bitfld.long 0x0 24.--25. "TX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" newline hexmask.long.byte 0x0 0.--6. 1. "TX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." line.long 0x4 "VIRT_ALIAS_15_UDMAP0__CFG__TCHAN_TCREDIT,The Transfer Request Credit Register indicates how many TR sized buffer slots exist in the associated UTC channel to which this channel is associated. This register only exists for external UTC channels. This.." bitfld.long 0x4 0.--2. "COUNT,Transfer Request Credit Count: this field specifies how many credits for complete TRs are available. This field should be initialized before the channel is enabled and will then increment/decrement as TRs are submitted and responses are received." "0,1,2,3,4,5,6,7" rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__TCHAN_TCQ,The Tx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value channel mode. This register may only be written when the channel.." hexmask.long.word 0x0 0.--15. 1. "TXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__TCHAN_TOES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__TCHAN_TEOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_15_UDMAP0__CFG__TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Tx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_15_UDMAP0__CFG__TCHAN_THRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x70++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be.." hexmask.long.word 0x0 0.--12. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_15_UDMAP0_CFG_RCHAN (NAVSS0_UDMAP_0_VIRT_ALIAS_15_UDMAP0_CFG_RCHAN)" base ad:0x4BF0C00000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 24.--25. "RX_ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED.." newline bitfld.long 0x0 15. "RX_IGNORE_SHORT,This field controls whether or not short packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Short packets are treated.." "0: Short packets are treated as exceptions and..,1: Short packets are ignored and the TR will.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = RESERVED 1 = 64 Bytes 2 = 128 bytes 3 = 256 bytes" "0: RESERVED,?,?,?" newline hexmask.long.byte 0x0 0.--6. 1. "RX_FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." rgroup.long 0x14++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__RCHAN_RCQ,The Rx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value TR based channel mode. This register may only be written when the.." hexmask.long.word 0x0 0.--15. 1. "RXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." rgroup.long 0x20++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__RCHAN_ROES,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x60++0xB line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__RCHAN_REOES,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "VIRT_ALIAS_15_UDMAP0__CFG__RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x4 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "?,?,?,3: bit value which will be output on the..,?,?,?,?" newline bitfld.long 0x4 16.--18. "QOS,Rx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "?,?,?,3: bit value which will be output on the mem*_cqos..,?,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "VIRT_ALIAS_15_UDMAP0__CFG__RCHAN_THRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from.." hexmask.long.word 0x8 0.--15. 1. "THREAD_ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." rgroup.long 0xF0++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__RCHAN_RFLOW_RNG,The flow range register is used to control which flows other than the default flow (0x3FFF / channel_number) are allowed to be used with this DMA channel." hexmask.long.word 0x0 16.--30. 1. "FLOWID_CNT,Rx Flow ID Count: This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for this channel. A value of 0 indicates that no flow IDs other than the default are allowed for the channel.." newline hexmask.long.word 0x0 0.--13. 1. "FLOWID_START,Rx Starting Flow ID: Beyond the default flow ID each channel can also make use of a single contiguous range of flow IDs and this field specifies the starting index for that range.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_15_UDMAP0_CFG_RFLOW (NAVSS0_UDMAP_0_VIRT_ALIAS_15_UDMAP0_CFG_RFLOW)" base ad:0x4BF0D00000 rgroup.long 0x0++0x1F line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__RFLOW_RFA,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." bitfld.long 0x0 30. "RX_EINFO_PRESENT,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will clear the Extended Packet Info Present bit in.." "0,1" newline bitfld.long 0x0 29. "RX_PSINFO_PRESENT,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will set the PS word count to 0 in the PD and will drop any PS words.." "0,1" newline bitfld.long 0x0 28. "RX_ERROR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor or buffer starvation occurs): 0 = Starvation errors result in dropping packet and reclaiming any used.." "0: Starvation errors result in dropping packet and..,1: Starvation errors result in subsequent re-try of.." newline bitfld.long 0x0 26.--27. "RX_DESC_TYPE,Rx Descriptor Type: This field indicates the descriptor type to use: 0 = Host 1 = RESERVED 2 = Monolithic 3 = RESERVED" "0: Host,1: RESERVED,2: Monolithic,3: RESERVED" newline bitfld.long 0x0 25. "RX_PS_LOCATION,Rx Protocol Specific Location: This bit controls where the Protocol Specific words will be placed in the Host Mode data structure. If this bit is cleared the DMA will clear the Protocol Specific Region Location bit in the PD and will.." "0,1" newline hexmask.long.word 0x0 16.--24. 1. "RX_SOP_OFFSET,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer). This value must be less than the.." newline hexmask.long.word 0x0 0.--15. 1. "RX_DEST_QNUM,Rx Destination Queue: This field indicates the default receive queue that packets on this flow should be placed onto." line.long 0x4 "VIRT_ALIAS_15_UDMAP0__CFG__RFLOW_RFB,The Rx Flow N Configuration Register B contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.byte 0x4 24.--31. 1. "RX_SRC_TAG_HI,Rx Source Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 16.--23. 1. "RX_SRC_TAG_LO,Rx Source Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1." newline hexmask.long.byte 0x4 8.--15. 1. "RX_DEST_TAG_HI,Rx Destination Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1." newline hexmask.long.byte 0x4 0.--7. 1. "RX_DEST_TAG_LO,Rx Destination Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1." line.long 0x8 "VIRT_ALIAS_15_UDMAP0__CFG__RFLOW_RFC,The Rx Flow N Configuration Register C contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." bitfld.long 0x8 28.--30. "RX_SRC_TAG_HI_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 24.--26. "RX_SRC_TAG_LO_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,?" newline bitfld.long 0x8 20.--22. "RX_DEST_TAG_HI_SEL,Rx Destination Tag High Byte Selector: This field specifies the source for bits 15:8 of the destination tag field in the word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 16.--18. "RX_DEST_TAG_LO_SEL,Rx Destination Tag Low Byte Selector: This field specifies the source for bits 7:0 of the destination tag field in word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 0.--2. "RX_SIZE_THRESH_EN,Rx Packet Sized Based Free Buffer Queue Enables: These bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_threshN fields to determine which FDQ to allocate the.." "0: Do not use the threshold,1: Use the thresholds to select between the 4..,?,?,?,?,?,?" line.long 0xC "VIRT_ALIAS_15_UDMAP0__CFG__RFLOW_RFD,The Rx Flow N Configuration Register D contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0xC 16.--31. 1. "RX_FDQ0_SZ0_QNUM,Rx Free Descriptor 0 Queue Index - Size 0: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value." newline hexmask.long.word 0xC 0.--15. 1. "RX_FDQ1_QNUM,Rx Free Descriptor 1 Queue Index: This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet" line.long 0x10 "VIRT_ALIAS_15_UDMAP0__CFG__RFLOW_RFE,The Rx Flow N Configuration Register E contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x10 16.--31. 1. "RX_FDQ2_QNUM,Rx Free Descriptor 2 Queue Index: This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet" newline hexmask.long.word 0x10 0.--15. 1. "RX_FDQ3_QNUM,Rx Free Descriptor 3 Queue Index: This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet" line.long 0x14 "VIRT_ALIAS_15_UDMAP0__CFG__RFLOW_RFF,The Rx Flow N Configuration Register F contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x14 16.--31. 1. "RX_SIZE_THRESH0,Rx Packet Size Threshold 0: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x14 0.--15. 1. "RX_SIZE_THRESH1,Rx Packet Size Threshold 1: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is greater than the.." line.long 0x18 "VIRT_ALIAS_15_UDMAP0__CFG__RFLOW_RFG,The Rx Flow N Configuration Register G contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x18 16.--31. 1. "RX_SIZE_THRESH2,Rx Packet Size Threshold 2: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to.." newline hexmask.long.word 0x18 0.--15. 1. "RX_FDQ0_SZ1_QNUM,Rx Free Descriptor 0 Queue Index - Size 1: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value. This field is optional." line.long 0x1C "VIRT_ALIAS_15_UDMAP0__CFG__RFLOW_RFH,The Rx Flow N Configuration Register H contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been.." hexmask.long.word 0x1C 16.--31. 1. "RX_FDQ0_SZ2_QNUM,Rx Free Descriptor 0 Queue Index - Size 2: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size1 value. This field is optional." newline hexmask.long.word 0x1C 0.--15. 1. "RX_FDQ0_SZ3_QNUM,Rx Free Descriptor 0 Queue Index - Size 3: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size2 value. This field is optional." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_15_UDMAP0_CFG_GCFG (NAVSS0_UDMAP_0_VIRT_ALIAS_15_UDMAP0_CFG_GCFG)" base ad:0x4BF1150000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the UDMA-P in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This field sets the timeout duration in clock cycles. This field controls the minimum amount of time that an Rx channel will be required to wait when it encounters a buffer starvation condition and the Rx error handling bit is set to 1.." line.long 0x4 "VIRT_ALIAS_15_UDMAP0__CFG__GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x1C++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__GCFG_UTC_CTRL,The external UTC control register provides a mapping of logical to physical thread IDs ." hexmask.long.word 0x0 0.--15. 1. "UTC_CHAN_START,This field specifies the starting PSI-L thread number for the external UTC" rgroup.long 0x20++0xF line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__GCFG_CAP0,The Capabilities Register 0 specifies which standard features this UDMA-P instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" newline bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" newline bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "VIRT_ALIAS_15_UDMAP0__CFG__GCFG_CAP1,The Capabilities Register 1 specifies which standard features this UDMA-P instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "VIRT_ALIAS_15_UDMAP0__CFG__GCFG_CAP2,The Capabilities Register 2 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx internal channel count" hexmask.long.word 0x8 9.--17. 1. "ECHAN_CNT,Tx external channel count" hexmask.long.word 0x8 0.--8. 1. "TCHAN_CNT,Tx internal channel count" line.long 0xC "VIRT_ALIAS_15_UDMAP0__CFG__GCFG_CAP3,The Capabilities Register 3 specifies how many resources this UDMA-P instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,Tx ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,Tx high capacity internal channel count" hexmask.long.word 0xC 0.--13. 1. "RFLOW_CNT,Rx flow table entry count" rgroup.long 0x40++0xF line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__GCFG_PERF0,This register provides thresholds for outstanding virtualized read/write commands from interface mem0" hexmask.long.byte 0x0 16.--23. 1. "VRD_THRESH0,Virt read command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x0 0.--7. 1. "VWR_THRESH0,Virt write command throttling threshold for mem0. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x4 "VIRT_ALIAS_15_UDMAP0__CFG__GCFG_PERF1,This register provides thresholds for outstanding virtualized read/write commands from interface mem1" hexmask.long.byte 0x4 16.--23. 1. "VRD_THRESH1,Virt read command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." hexmask.long.byte 0x4 0.--7. 1. "VWR_THRESH1,Virt write command throttling threshold for mem1. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." line.long 0x8 "VIRT_ALIAS_15_UDMAP0__CFG__GCFG_PERF2,This register provides thresholds for outstanding virtualized read commands from interface memr" hexmask.long.byte 0x8 16.--23. 1. "VRD_THRESH2,Virt read command throttling threshold for memr. Dispatching will be disabled for virtualized channels whenver the current virtualized read count from this interface meets or exceeds this value." line.long 0xC "VIRT_ALIAS_15_UDMAP0__CFG__GCFG_PERF3,This register provides thresholds for outstanding virtualized write commands from interface memw" hexmask.long.byte 0xC 0.--7. 1. "VWR_THRESH3,Virt write command throttling threshold for memw. Dispatching will be disabled for virtualized channels whenver the current virtualized write count from this interface meets or exceeds this value." rgroup.long 0x60++0x7 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x0 0.--31. 1. "NOGATE_LO,When set inhibits automatic gating of clock." line.long 0x4 "VIRT_ALIAS_15_UDMAP0__CFG__GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long 0x4 0.--31. 1. "NOGATE_HI,When set inhibits automatic gating of clock." rgroup.long 0x78++0xB line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "VIRT_ALIAS_15_UDMAP0__CFG__GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" line.long 0x8 "VIRT_ALIAS_15_UDMAP0__CFG__GCFG_RFLOWFWOES,The Rx Flow FW OES Register specifies a destination event number to which an event should be sent if an out of range flow ID is received on a packet." hexmask.long.word 0x8 0.--15. 1. "EVT_NUM,This is the global event number to be generated" rgroup.long 0x88++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__GCFG_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check. Values in this register will remain persistent once an exception has been.." bitfld.long 0x0 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet. Once this bit is set the remaining fields in this register will not be modified. SW is required to write this bit to 0 to allow another.." "0,1" hexmask.long.word 0x0 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet" hexmask.long.word 0x0 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_15_UDMAP0_CFG_RCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_15_UDMAP0_CFG_RCHANRT)" base ad:0x4BF4000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the rx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMAP_0_VIRT_ALIAS_15_UDMAP0_CFG_TCHANRT (NAVSS0_UDMAP_0_VIRT_ALIAS_15_UDMAP0_CFG_TCHANRT)" base ad:0x4BF5000000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" newline bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" newline rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." line.long 0x4 "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." rgroup.long 0x80++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" rgroup.long 0x200++0x3F line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." rgroup.long 0x400++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." rgroup.long 0x408++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." rgroup.long 0x410++0x3 line.long 0x0 "VIRT_ALIAS_15_UDMAP0__CFG__TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end endif tree.end tree.end tree "NAVSS0_UDMASS_INTA_0" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_UDMASS_INTA0_CFG (NAVSS0_UDMASS_INTA_0_UDMASS_INTA0_CFG)" base ad:0x30802000 rgroup.quad 0x0++0x17 line.quad 0x0 "UDMASS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "UDMASS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "UDMASS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_UDMASS_INTA0_CFG_UNMAP (NAVSS0_UDMASS_INTA_0_UDMASS_INTA0_CFG_UNMAP)" base ad:0x30880000 rgroup.quad 0x3000++0x7 line.quad 0x0 "UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x4000++0x7 line.quad 0x0 "UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x5000++0x7 line.quad 0x0 "UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x6000++0x7 line.quad 0x0 "UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x7000++0x7 line.quad 0x0 "UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x8000++0x7 line.quad 0x0 "UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_UDMASS_INTA0_IMAP (NAVSS0_UDMASS_INTA_0_UDMASS_INTA0_IMAP)" base ad:0x30940000 rgroup.quad 0x0++0x7 line.quad 0x0 "UDMASS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_UDMASS_INTA0_CFG_GCNTCFG (NAVSS0_UDMASS_INTA_0_UDMASS_INTA0_CFG_GCNTCFG)" base ad:0x31040000 rgroup.quad 0x0++0x7 line.quad 0x0 "UDMASS_INTA0__CFG__GCNTCFG_map,The Global Event Mapping register controls the egress global event index for this event count. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_UDMASS_INTA0_CFG_L2G (NAVSS0_UDMASS_INTA_0_UDMASS_INTA0_CFG_L2G)" base ad:0x31100000 rgroup.quad 0x0++0x7 line.quad 0x0 "UDMASS_INTA0__CFG__L2G_map,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane. Both pulse and rising edge local event types are supported. With pulsed events. the event count is.." bitfld.quad 0x0 31. "MODE,Local event detection mode. This field is set to 0 for pulsed events and to 1 for rising edge eventss" "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_UDMASS_INTA0_CFG_MCAST (NAVSS0_UDMASS_INTA_0_UDMASS_INTA0_CFG_MCAST)" base ad:0x31110000 rgroup.quad 0x0++0x7 line.quad 0x0 "UDMASS_INTA0__CFG__MCAST_mcmap,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces. The index of each of the two egress events is stored in this register. which.." bitfld.quad 0x0 63. "IRQMODE1,IRQ Mode Flag 1. When set this register act like a mapper with bitnum in 37:32 and regnum in 46:38." "0,1" hexmask.quad.word 0x0 32.--47. 1. "GEVIDX1,Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable." bitfld.quad 0x0 31. "IRQMODE0,IRQ Mode Flag 0. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX0,Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_UDMASS_INTA0_CFG_GCNTRTI (NAVSS0_UDMASS_INTA_0_UDMASS_INTA0_CFG_GCNTRTI)" base ad:0x33800000 rgroup.quad 0x0++0x7 line.quad 0x0 "UDMASS_INTA0__CFG__GCNTRTI_count,The ETL Count register is read by software to determine how many times the event message has been received. This register can be written to decrement the count by a specified amount to acknowledge that a count has been.." hexmask.quad.long 0x0 0.--31. 1. "CCNT,Current count. This field is incremented by the event count for each message received with this event on the Counted ETL Interface. On write this field will be decremented by the value written. Writing a value greater than the current count is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_UDMASS_INTA0_CFG_INTR (NAVSS0_UDMASS_INTA_0_UDMASS_INTA0_CFG_INTR)" base ad:0x33D00000 rgroup.quad 0x0++0x27 line.quad 0x0 "UDMASS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual interrupt.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "UDMASS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "UDMASS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "UDMASS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "UDMASS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_ALIAS64K_UDMASS_INTA0_CFG_GCNTRTI (NAVSS0_UDMASS_INTA_0_ALIAS64K_UDMASS_INTA0_CFG_GCNTRTI)" base ad:0x4A38000000 rgroup.quad 0x0++0x7 line.quad 0x0 "ALIAS64K_UDMASS_INTA0__CFG__GCNTRTI_count,The ETL Count register is read by software to determine how many times the event message has been received. This register can be written to decrement the count by a specified amount to acknowledge that a count.." hexmask.quad.long 0x0 0.--31. 1. "CCNT,Current count. This field is incremented by the event count for each message received with this event on the Counted ETL Interface. On write this field will be decremented by the value written. Writing a value greater than the current count is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_ALIAS64K_UDMASS_INTA0_CFG_INTR (NAVSS0_UDMASS_INTA_0_ALIAS64K_UDMASS_INTA0_CFG_INTR)" base ad:0x4A3D000000 rgroup.quad 0x0++0x27 line.quad 0x0 "ALIAS64K_UDMASS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "ALIAS64K_UDMASS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "ALIAS64K_UDMASS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "ALIAS64K_UDMASS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "ALIAS64K_UDMASS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_0_UDMASS_INTA0_CFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_0_UDMASS_INTA0_CFG)" base ad:0x4B00802000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_0_UDMASS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_0_UDMASS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_0_UDMASS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_0_UDMASS_INTA0_CFG_UNMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_0_UDMASS_INTA0_CFG_UNMAP)" base ad:0x4B00880000 rgroup.quad 0x3000++0x7 line.quad 0x0 "VIRT_ALIAS_0_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x4000++0x7 line.quad 0x0 "VIRT_ALIAS_0_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x5000++0x7 line.quad 0x0 "VIRT_ALIAS_0_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x6000++0x7 line.quad 0x0 "VIRT_ALIAS_0_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x7000++0x7 line.quad 0x0 "VIRT_ALIAS_0_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x8000++0x7 line.quad 0x0 "VIRT_ALIAS_0_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_0_UDMASS_INTA0_CFG_IMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_0_UDMASS_INTA0_CFG_IMAP)" base ad:0x4B00940000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_0_UDMASS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_0_UDMASS_INTA0_CFG_GCNTCFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_0_UDMASS_INTA0_CFG_GCNTCFG)" base ad:0x4B01040000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_0_UDMASS_INTA0__CFG__GCNTCFG_map,The Global Event Mapping register controls the egress global event index for this event count. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_0_UDMASS_INTA0_CFG_L2G (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_0_UDMASS_INTA0_CFG_L2G)" base ad:0x4B01100000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_0_UDMASS_INTA0__CFG__L2G_map,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane. Both pulse and rising edge local event types are supported. With pulsed events. the event.." bitfld.quad 0x0 31. "MODE,Local event detection mode. This field is set to 0 for pulsed events and to 1 for rising edge eventss" "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_0_UDMASS_INTA0_CFG_MCAST (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_0_UDMASS_INTA0_CFG_MCAST)" base ad:0x4B01110000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_0_UDMASS_INTA0__CFG__MCAST_mcmap,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces. The index of each of the two egress events is stored in this.." bitfld.quad 0x0 63. "IRQMODE1,IRQ Mode Flag 1. When set this register act like a mapper with bitnum in 37:32 and regnum in 46:38." "0,1" hexmask.quad.word 0x0 32.--47. 1. "GEVIDX1,Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable." bitfld.quad 0x0 31. "IRQMODE0,IRQ Mode Flag 0. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX0,Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_0_UDMASS_INTA0_CFG_GCNTRTI (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_0_UDMASS_INTA0_CFG_GCNTRTI)" base ad:0x4B03800000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_0_UDMASS_INTA0__CFG__GCNTRTI_count,The ETL Count register is read by software to determine how many times the event message has been received. This register can be written to decrement the count by a specified amount to acknowledge that a.." hexmask.quad.long 0x0 0.--31. 1. "CCNT,Current count. This field is incremented by the event count for each message received with this event on the Counted ETL Interface. On write this field will be decremented by the value written. Writing a value greater than the current count is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_0_UDMASS_INTA0_CFG_INTR (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_0_UDMASS_INTA0_CFG_INTR)" base ad:0x4B03D00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_0_UDMASS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_0_UDMASS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_0_UDMASS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_0_UDMASS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_0_UDMASS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_1_UDMASS_INTA0_CFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_1_UDMASS_INTA0_CFG)" base ad:0x4B10802000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_1_UDMASS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_1_UDMASS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_1_UDMASS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_1_UDMASS_INTA0_CFG_UNMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_1_UDMASS_INTA0_CFG_UNMAP)" base ad:0x4B10880000 rgroup.quad 0x3000++0x7 line.quad 0x0 "VIRT_ALIAS_1_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x4000++0x7 line.quad 0x0 "VIRT_ALIAS_1_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x5000++0x7 line.quad 0x0 "VIRT_ALIAS_1_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x6000++0x7 line.quad 0x0 "VIRT_ALIAS_1_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x7000++0x7 line.quad 0x0 "VIRT_ALIAS_1_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x8000++0x7 line.quad 0x0 "VIRT_ALIAS_1_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_1_UDMASS_INTA0_CFG_IMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_1_UDMASS_INTA0_CFG_IMAP)" base ad:0x4B10940000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_1_UDMASS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_1_UDMASS_INTA0_CFG_GCNTCFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_1_UDMASS_INTA0_CFG_GCNTCFG)" base ad:0x4B11040000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_1_UDMASS_INTA0__CFG__GCNTCFG_map,The Global Event Mapping register controls the egress global event index for this event count. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_1_UDMASS_INTA0_CFG_L2G (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_1_UDMASS_INTA0_CFG_L2G)" base ad:0x4B11100000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_1_UDMASS_INTA0__CFG__L2G_map,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane. Both pulse and rising edge local event types are supported. With pulsed events. the event.." bitfld.quad 0x0 31. "MODE,Local event detection mode. This field is set to 0 for pulsed events and to 1 for rising edge eventss" "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_1_UDMASS_INTA0_CFG_MCAST (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_1_UDMASS_INTA0_CFG_MCAST)" base ad:0x4B11110000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_1_UDMASS_INTA0__CFG__MCAST_mcmap,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces. The index of each of the two egress events is stored in this.." bitfld.quad 0x0 63. "IRQMODE1,IRQ Mode Flag 1. When set this register act like a mapper with bitnum in 37:32 and regnum in 46:38." "0,1" hexmask.quad.word 0x0 32.--47. 1. "GEVIDX1,Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable." bitfld.quad 0x0 31. "IRQMODE0,IRQ Mode Flag 0. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX0,Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_1_UDMASS_INTA0_CFG_GCNTRTI (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_1_UDMASS_INTA0_CFG_GCNTRTI)" base ad:0x4B13800000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_1_UDMASS_INTA0__CFG__GCNTRTI_count,The ETL Count register is read by software to determine how many times the event message has been received. This register can be written to decrement the count by a specified amount to acknowledge that a.." hexmask.quad.long 0x0 0.--31. 1. "CCNT,Current count. This field is incremented by the event count for each message received with this event on the Counted ETL Interface. On write this field will be decremented by the value written. Writing a value greater than the current count is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_1_UDMASS_INTA0_CFG_INTR (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_1_UDMASS_INTA0_CFG_INTR)" base ad:0x4B13D00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_1_UDMASS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_1_UDMASS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_1_UDMASS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_1_UDMASS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_1_UDMASS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_2_UDMASS_INTA0_CFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_2_UDMASS_INTA0_CFG)" base ad:0x4B20802000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_2_UDMASS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_2_UDMASS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_2_UDMASS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_2_UDMASS_INTA0_CFG_UNMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_2_UDMASS_INTA0_CFG_UNMAP)" base ad:0x4B20880000 rgroup.quad 0x3000++0x7 line.quad 0x0 "VIRT_ALIAS_2_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x4000++0x7 line.quad 0x0 "VIRT_ALIAS_2_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x5000++0x7 line.quad 0x0 "VIRT_ALIAS_2_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x6000++0x7 line.quad 0x0 "VIRT_ALIAS_2_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x7000++0x7 line.quad 0x0 "VIRT_ALIAS_2_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x8000++0x7 line.quad 0x0 "VIRT_ALIAS_2_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_2_UDMASS_INTA0_CFG_IMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_2_UDMASS_INTA0_CFG_IMAP)" base ad:0x4B20940000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_2_UDMASS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_2_UDMASS_INTA0_CFG_GCNTCFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_2_UDMASS_INTA0_CFG_GCNTCFG)" base ad:0x4B21040000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_2_UDMASS_INTA0__CFG__GCNTCFG_map,The Global Event Mapping register controls the egress global event index for this event count. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_2_UDMASS_INTA0_CFG_L2G (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_2_UDMASS_INTA0_CFG_L2G)" base ad:0x4B21100000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_2_UDMASS_INTA0__CFG__L2G_map,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane. Both pulse and rising edge local event types are supported. With pulsed events. the event.." bitfld.quad 0x0 31. "MODE,Local event detection mode. This field is set to 0 for pulsed events and to 1 for rising edge eventss" "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_2_UDMASS_INTA0_CFG_MCAST (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_2_UDMASS_INTA0_CFG_MCAST)" base ad:0x4B21110000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_2_UDMASS_INTA0__CFG__MCAST_mcmap,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces. The index of each of the two egress events is stored in this.." bitfld.quad 0x0 63. "IRQMODE1,IRQ Mode Flag 1. When set this register act like a mapper with bitnum in 37:32 and regnum in 46:38." "0,1" hexmask.quad.word 0x0 32.--47. 1. "GEVIDX1,Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable." bitfld.quad 0x0 31. "IRQMODE0,IRQ Mode Flag 0. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX0,Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_2_UDMASS_INTA0_CFG_GCNTRTI (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_2_UDMASS_INTA0_CFG_GCNTRTI)" base ad:0x4B23800000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_2_UDMASS_INTA0__CFG__GCNTRTI_count,The ETL Count register is read by software to determine how many times the event message has been received. This register can be written to decrement the count by a specified amount to acknowledge that a.." hexmask.quad.long 0x0 0.--31. 1. "CCNT,Current count. This field is incremented by the event count for each message received with this event on the Counted ETL Interface. On write this field will be decremented by the value written. Writing a value greater than the current count is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_2_UDMASS_INTA0_CFG_INTR (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_2_UDMASS_INTA0_CFG_INTR)" base ad:0x4B23D00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_2_UDMASS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_2_UDMASS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_2_UDMASS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_2_UDMASS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_2_UDMASS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_3_UDMASS_INTA0_CFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_3_UDMASS_INTA0_CFG)" base ad:0x4B30802000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_3_UDMASS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_3_UDMASS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_3_UDMASS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_3_UDMASS_INTA0_CFG_UNMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_3_UDMASS_INTA0_CFG_UNMAP)" base ad:0x4B30880000 rgroup.quad 0x3000++0x7 line.quad 0x0 "VIRT_ALIAS_3_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x4000++0x7 line.quad 0x0 "VIRT_ALIAS_3_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x5000++0x7 line.quad 0x0 "VIRT_ALIAS_3_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x6000++0x7 line.quad 0x0 "VIRT_ALIAS_3_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x7000++0x7 line.quad 0x0 "VIRT_ALIAS_3_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x8000++0x7 line.quad 0x0 "VIRT_ALIAS_3_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_3_UDMASS_INTA0_CFG_IMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_3_UDMASS_INTA0_CFG_IMAP)" base ad:0x4B30940000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_3_UDMASS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_3_UDMASS_INTA0_CFG_GCNTCFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_3_UDMASS_INTA0_CFG_GCNTCFG)" base ad:0x4B31040000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_3_UDMASS_INTA0__CFG__GCNTCFG_map,The Global Event Mapping register controls the egress global event index for this event count. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_3_UDMASS_INTA0_CFG_L2G (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_3_UDMASS_INTA0_CFG_L2G)" base ad:0x4B31100000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_3_UDMASS_INTA0__CFG__L2G_map,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane. Both pulse and rising edge local event types are supported. With pulsed events. the event.." bitfld.quad 0x0 31. "MODE,Local event detection mode. This field is set to 0 for pulsed events and to 1 for rising edge eventss" "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_3_UDMASS_INTA0_CFG_MCAST (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_3_UDMASS_INTA0_CFG_MCAST)" base ad:0x4B31110000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_3_UDMASS_INTA0__CFG__MCAST_mcmap,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces. The index of each of the two egress events is stored in this.." bitfld.quad 0x0 63. "IRQMODE1,IRQ Mode Flag 1. When set this register act like a mapper with bitnum in 37:32 and regnum in 46:38." "0,1" hexmask.quad.word 0x0 32.--47. 1. "GEVIDX1,Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable." bitfld.quad 0x0 31. "IRQMODE0,IRQ Mode Flag 0. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX0,Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_3_UDMASS_INTA0_CFG_GCNTRTI (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_3_UDMASS_INTA0_CFG_GCNTRTI)" base ad:0x4B33800000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_3_UDMASS_INTA0__CFG__GCNTRTI_count,The ETL Count register is read by software to determine how many times the event message has been received. This register can be written to decrement the count by a specified amount to acknowledge that a.." hexmask.quad.long 0x0 0.--31. 1. "CCNT,Current count. This field is incremented by the event count for each message received with this event on the Counted ETL Interface. On write this field will be decremented by the value written. Writing a value greater than the current count is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_3_UDMASS_INTA0_CFG_INTR (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_3_UDMASS_INTA0_CFG_INTR)" base ad:0x4B33D00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_3_UDMASS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_3_UDMASS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_3_UDMASS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_3_UDMASS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_3_UDMASS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_4_UDMASS_INTA0_CFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_4_UDMASS_INTA0_CFG)" base ad:0x4B40802000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_4_UDMASS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_4_UDMASS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_4_UDMASS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_4_UDMASS_INTA0_CFG_UNMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_4_UDMASS_INTA0_CFG_UNMAP)" base ad:0x4B40880000 rgroup.quad 0x3000++0x7 line.quad 0x0 "VIRT_ALIAS_4_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x4000++0x7 line.quad 0x0 "VIRT_ALIAS_4_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x5000++0x7 line.quad 0x0 "VIRT_ALIAS_4_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x6000++0x7 line.quad 0x0 "VIRT_ALIAS_4_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x7000++0x7 line.quad 0x0 "VIRT_ALIAS_4_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x8000++0x7 line.quad 0x0 "VIRT_ALIAS_4_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_4_UDMASS_INTA0_CFG_IMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_4_UDMASS_INTA0_CFG_IMAP)" base ad:0x4B40940000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_4_UDMASS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_4_UDMASS_INTA0_CFG_GCNTCFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_4_UDMASS_INTA0_CFG_GCNTCFG)" base ad:0x4B41040000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_4_UDMASS_INTA0__CFG__GCNTCFG_map,The Global Event Mapping register controls the egress global event index for this event count. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_4_UDMASS_INTA0_CFG_L2G (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_4_UDMASS_INTA0_CFG_L2G)" base ad:0x4B41100000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_4_UDMASS_INTA0__CFG__L2G_map,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane. Both pulse and rising edge local event types are supported. With pulsed events. the event.." bitfld.quad 0x0 31. "MODE,Local event detection mode. This field is set to 0 for pulsed events and to 1 for rising edge eventss" "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_4_UDMASS_INTA0_CFG_MCAST (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_4_UDMASS_INTA0_CFG_MCAST)" base ad:0x4B41110000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_4_UDMASS_INTA0__CFG__MCAST_mcmap,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces. The index of each of the two egress events is stored in this.." bitfld.quad 0x0 63. "IRQMODE1,IRQ Mode Flag 1. When set this register act like a mapper with bitnum in 37:32 and regnum in 46:38." "0,1" hexmask.quad.word 0x0 32.--47. 1. "GEVIDX1,Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable." bitfld.quad 0x0 31. "IRQMODE0,IRQ Mode Flag 0. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX0,Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_4_UDMASS_INTA0_CFG_GCNTRTI (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_4_UDMASS_INTA0_CFG_GCNTRTI)" base ad:0x4B43800000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_4_UDMASS_INTA0__CFG__GCNTRTI_count,The ETL Count register is read by software to determine how many times the event message has been received. This register can be written to decrement the count by a specified amount to acknowledge that a.." hexmask.quad.long 0x0 0.--31. 1. "CCNT,Current count. This field is incremented by the event count for each message received with this event on the Counted ETL Interface. On write this field will be decremented by the value written. Writing a value greater than the current count is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_4_UDMASS_INTA0_CFG_INTR (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_4_UDMASS_INTA0_CFG_INTR)" base ad:0x4B43D00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_4_UDMASS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_4_UDMASS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_4_UDMASS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_4_UDMASS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_4_UDMASS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_5_UDMASS_INTA0_CFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_5_UDMASS_INTA0_CFG)" base ad:0x4B50802000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_5_UDMASS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_5_UDMASS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_5_UDMASS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_5_UDMASS_INTA0_CFG_UNMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_5_UDMASS_INTA0_CFG_UNMAP)" base ad:0x4B50880000 rgroup.quad 0x3000++0x7 line.quad 0x0 "VIRT_ALIAS_5_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x4000++0x7 line.quad 0x0 "VIRT_ALIAS_5_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x5000++0x7 line.quad 0x0 "VIRT_ALIAS_5_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x6000++0x7 line.quad 0x0 "VIRT_ALIAS_5_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x7000++0x7 line.quad 0x0 "VIRT_ALIAS_5_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x8000++0x7 line.quad 0x0 "VIRT_ALIAS_5_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_5_UDMASS_INTA0_CFG_IMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_5_UDMASS_INTA0_CFG_IMAP)" base ad:0x4B50940000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_5_UDMASS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_5_UDMASS_INTA0_CFG_GCNTCFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_5_UDMASS_INTA0_CFG_GCNTCFG)" base ad:0x4B51040000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_5_UDMASS_INTA0__CFG__GCNTCFG_map,The Global Event Mapping register controls the egress global event index for this event count. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_5_UDMASS_INTA0_CFG_L2G (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_5_UDMASS_INTA0_CFG_L2G)" base ad:0x4B51100000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_5_UDMASS_INTA0__CFG__L2G_map,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane. Both pulse and rising edge local event types are supported. With pulsed events. the event.." bitfld.quad 0x0 31. "MODE,Local event detection mode. This field is set to 0 for pulsed events and to 1 for rising edge eventss" "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_5_UDMASS_INTA0_CFG_MCAST (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_5_UDMASS_INTA0_CFG_MCAST)" base ad:0x4B51110000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_5_UDMASS_INTA0__CFG__MCAST_mcmap,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces. The index of each of the two egress events is stored in this.." bitfld.quad 0x0 63. "IRQMODE1,IRQ Mode Flag 1. When set this register act like a mapper with bitnum in 37:32 and regnum in 46:38." "0,1" hexmask.quad.word 0x0 32.--47. 1. "GEVIDX1,Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable." bitfld.quad 0x0 31. "IRQMODE0,IRQ Mode Flag 0. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX0,Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_5_UDMASS_INTA0_CFG_GCNTRTI (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_5_UDMASS_INTA0_CFG_GCNTRTI)" base ad:0x4B53800000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_5_UDMASS_INTA0__CFG__GCNTRTI_count,The ETL Count register is read by software to determine how many times the event message has been received. This register can be written to decrement the count by a specified amount to acknowledge that a.." hexmask.quad.long 0x0 0.--31. 1. "CCNT,Current count. This field is incremented by the event count for each message received with this event on the Counted ETL Interface. On write this field will be decremented by the value written. Writing a value greater than the current count is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_5_UDMASS_INTA0_CFG_INTR (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_5_UDMASS_INTA0_CFG_INTR)" base ad:0x4B53D00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_5_UDMASS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_5_UDMASS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_5_UDMASS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_5_UDMASS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_5_UDMASS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_6_UDMASS_INTA0_CFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_6_UDMASS_INTA0_CFG)" base ad:0x4B60802000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_6_UDMASS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_6_UDMASS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_6_UDMASS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_6_UDMASS_INTA0_CFG_UNMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_6_UDMASS_INTA0_CFG_UNMAP)" base ad:0x4B60880000 rgroup.quad 0x3000++0x7 line.quad 0x0 "VIRT_ALIAS_6_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x4000++0x7 line.quad 0x0 "VIRT_ALIAS_6_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x5000++0x7 line.quad 0x0 "VIRT_ALIAS_6_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x6000++0x7 line.quad 0x0 "VIRT_ALIAS_6_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x7000++0x7 line.quad 0x0 "VIRT_ALIAS_6_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x8000++0x7 line.quad 0x0 "VIRT_ALIAS_6_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_6_UDMASS_INTA0_CFG_IMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_6_UDMASS_INTA0_CFG_IMAP)" base ad:0x4B60940000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_6_UDMASS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_6_UDMASS_INTA0_CFG_GCNTCFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_6_UDMASS_INTA0_CFG_GCNTCFG)" base ad:0x4B61040000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_6_UDMASS_INTA0__CFG__GCNTCFG_map,The Global Event Mapping register controls the egress global event index for this event count. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_6_UDMASS_INTA0_CFG_L2G (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_6_UDMASS_INTA0_CFG_L2G)" base ad:0x4B61100000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_6_UDMASS_INTA0__CFG__L2G_map,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane. Both pulse and rising edge local event types are supported. With pulsed events. the event.." bitfld.quad 0x0 31. "MODE,Local event detection mode. This field is set to 0 for pulsed events and to 1 for rising edge eventss" "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_6_UDMASS_INTA0_CFG_MCAST (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_6_UDMASS_INTA0_CFG_MCAST)" base ad:0x4B61110000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_6_UDMASS_INTA0__CFG__MCAST_mcmap,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces. The index of each of the two egress events is stored in this.." bitfld.quad 0x0 63. "IRQMODE1,IRQ Mode Flag 1. When set this register act like a mapper with bitnum in 37:32 and regnum in 46:38." "0,1" hexmask.quad.word 0x0 32.--47. 1. "GEVIDX1,Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable." bitfld.quad 0x0 31. "IRQMODE0,IRQ Mode Flag 0. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX0,Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_6_UDMASS_INTA0_CFG_GCNTRTI (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_6_UDMASS_INTA0_CFG_GCNTRTI)" base ad:0x4B63800000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_6_UDMASS_INTA0__CFG__GCNTRTI_count,The ETL Count register is read by software to determine how many times the event message has been received. This register can be written to decrement the count by a specified amount to acknowledge that a.." hexmask.quad.long 0x0 0.--31. 1. "CCNT,Current count. This field is incremented by the event count for each message received with this event on the Counted ETL Interface. On write this field will be decremented by the value written. Writing a value greater than the current count is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_6_UDMASS_INTA0_CFG_INTR (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_6_UDMASS_INTA0_CFG_INTR)" base ad:0x4B63D00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_6_UDMASS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_6_UDMASS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_6_UDMASS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_6_UDMASS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_6_UDMASS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_7_UDMASS_INTA0_CFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_7_UDMASS_INTA0_CFG)" base ad:0x4B70802000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_7_UDMASS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_7_UDMASS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_7_UDMASS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_7_UDMASS_INTA0_CFG_UNMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_7_UDMASS_INTA0_CFG_UNMAP)" base ad:0x4B70880000 rgroup.quad 0x3000++0x7 line.quad 0x0 "VIRT_ALIAS_7_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x4000++0x7 line.quad 0x0 "VIRT_ALIAS_7_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x5000++0x7 line.quad 0x0 "VIRT_ALIAS_7_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x6000++0x7 line.quad 0x0 "VIRT_ALIAS_7_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x7000++0x7 line.quad 0x0 "VIRT_ALIAS_7_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x8000++0x7 line.quad 0x0 "VIRT_ALIAS_7_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_7_UDMASS_INTA0_CFG_IMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_7_UDMASS_INTA0_CFG_IMAP)" base ad:0x4B70940000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_7_UDMASS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_7_UDMASS_INTA0_CFG_GCNTCFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_7_UDMASS_INTA0_CFG_GCNTCFG)" base ad:0x4B71040000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_7_UDMASS_INTA0__CFG__GCNTCFG_map,The Global Event Mapping register controls the egress global event index for this event count. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_7_UDMASS_INTA0_CFG_L2G (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_7_UDMASS_INTA0_CFG_L2G)" base ad:0x4B71100000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_7_UDMASS_INTA0__CFG__L2G_map,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane. Both pulse and rising edge local event types are supported. With pulsed events. the event.." bitfld.quad 0x0 31. "MODE,Local event detection mode. This field is set to 0 for pulsed events and to 1 for rising edge eventss" "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_7_UDMASS_INTA0_CFG_MCAST (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_7_UDMASS_INTA0_CFG_MCAST)" base ad:0x4B71110000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_7_UDMASS_INTA0__CFG__MCAST_mcmap,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces. The index of each of the two egress events is stored in this.." bitfld.quad 0x0 63. "IRQMODE1,IRQ Mode Flag 1. When set this register act like a mapper with bitnum in 37:32 and regnum in 46:38." "0,1" hexmask.quad.word 0x0 32.--47. 1. "GEVIDX1,Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable." bitfld.quad 0x0 31. "IRQMODE0,IRQ Mode Flag 0. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX0,Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_7_UDMASS_INTA0_CFG_GCNTRTI (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_7_UDMASS_INTA0_CFG_GCNTRTI)" base ad:0x4B73800000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_7_UDMASS_INTA0__CFG__GCNTRTI_count,The ETL Count register is read by software to determine how many times the event message has been received. This register can be written to decrement the count by a specified amount to acknowledge that a.." hexmask.quad.long 0x0 0.--31. 1. "CCNT,Current count. This field is incremented by the event count for each message received with this event on the Counted ETL Interface. On write this field will be decremented by the value written. Writing a value greater than the current count is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_7_UDMASS_INTA0_CFG_INTR (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_7_UDMASS_INTA0_CFG_INTR)" base ad:0x4B73D00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_7_UDMASS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_7_UDMASS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_7_UDMASS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_7_UDMASS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_7_UDMASS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_8_UDMASS_INTA0_CFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_8_UDMASS_INTA0_CFG)" base ad:0x4B80802000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_8_UDMASS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_8_UDMASS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_8_UDMASS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_8_UDMASS_INTA0_CFG_UNMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_8_UDMASS_INTA0_CFG_UNMAP)" base ad:0x4B80880000 rgroup.quad 0x3000++0x7 line.quad 0x0 "VIRT_ALIAS_8_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x4000++0x7 line.quad 0x0 "VIRT_ALIAS_8_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x5000++0x7 line.quad 0x0 "VIRT_ALIAS_8_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x6000++0x7 line.quad 0x0 "VIRT_ALIAS_8_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x7000++0x7 line.quad 0x0 "VIRT_ALIAS_8_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x8000++0x7 line.quad 0x0 "VIRT_ALIAS_8_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_8_UDMASS_INTA0_CFG_IMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_8_UDMASS_INTA0_CFG_IMAP)" base ad:0x4B80940000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_8_UDMASS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_8_UDMASS_INTA0_CFG_GCNTCFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_8_UDMASS_INTA0_CFG_GCNTCFG)" base ad:0x4B81040000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_8_UDMASS_INTA0__CFG__GCNTCFG_map,The Global Event Mapping register controls the egress global event index for this event count. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_8_UDMASS_INTA0_CFG_L2G (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_8_UDMASS_INTA0_CFG_L2G)" base ad:0x4B81100000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_8_UDMASS_INTA0__CFG__L2G_map,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane. Both pulse and rising edge local event types are supported. With pulsed events. the event.." bitfld.quad 0x0 31. "MODE,Local event detection mode. This field is set to 0 for pulsed events and to 1 for rising edge eventss" "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_8_UDMASS_INTA0_CFG_MCAST (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_8_UDMASS_INTA0_CFG_MCAST)" base ad:0x4B81110000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_8_UDMASS_INTA0__CFG__MCAST_mcmap,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces. The index of each of the two egress events is stored in this.." bitfld.quad 0x0 63. "IRQMODE1,IRQ Mode Flag 1. When set this register act like a mapper with bitnum in 37:32 and regnum in 46:38." "0,1" hexmask.quad.word 0x0 32.--47. 1. "GEVIDX1,Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable." bitfld.quad 0x0 31. "IRQMODE0,IRQ Mode Flag 0. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX0,Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_8_UDMASS_INTA0_CFG_GCNTRTI (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_8_UDMASS_INTA0_CFG_GCNTRTI)" base ad:0x4B83800000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_8_UDMASS_INTA0__CFG__GCNTRTI_count,The ETL Count register is read by software to determine how many times the event message has been received. This register can be written to decrement the count by a specified amount to acknowledge that a.." hexmask.quad.long 0x0 0.--31. 1. "CCNT,Current count. This field is incremented by the event count for each message received with this event on the Counted ETL Interface. On write this field will be decremented by the value written. Writing a value greater than the current count is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_8_UDMASS_INTA0_CFG_INTR (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_8_UDMASS_INTA0_CFG_INTR)" base ad:0x4B83D00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_8_UDMASS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_8_UDMASS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_8_UDMASS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_8_UDMASS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_8_UDMASS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_9_UDMASS_INTA0_CFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_9_UDMASS_INTA0_CFG)" base ad:0x4B90802000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_9_UDMASS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_9_UDMASS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_9_UDMASS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_9_UDMASS_INTA0_CFG_UNMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_9_UDMASS_INTA0_CFG_UNMAP)" base ad:0x4B90880000 rgroup.quad 0x3000++0x7 line.quad 0x0 "VIRT_ALIAS_9_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x4000++0x7 line.quad 0x0 "VIRT_ALIAS_9_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x5000++0x7 line.quad 0x0 "VIRT_ALIAS_9_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x6000++0x7 line.quad 0x0 "VIRT_ALIAS_9_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x7000++0x7 line.quad 0x0 "VIRT_ALIAS_9_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x8000++0x7 line.quad 0x0 "VIRT_ALIAS_9_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_9_UDMASS_INTA0_CFG_IMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_9_UDMASS_INTA0_CFG_IMAP)" base ad:0x4B90940000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_9_UDMASS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_9_UDMASS_INTA0_CFG_GCNTCFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_9_UDMASS_INTA0_CFG_GCNTCFG)" base ad:0x4B91040000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_9_UDMASS_INTA0__CFG__GCNTCFG_map,The Global Event Mapping register controls the egress global event index for this event count. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_9_UDMASS_INTA0_CFG_L2G (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_9_UDMASS_INTA0_CFG_L2G)" base ad:0x4B91100000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_9_UDMASS_INTA0__CFG__L2G_map,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane. Both pulse and rising edge local event types are supported. With pulsed events. the event.." bitfld.quad 0x0 31. "MODE,Local event detection mode. This field is set to 0 for pulsed events and to 1 for rising edge eventss" "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_9_UDMASS_INTA0_CFG_MCAST (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_9_UDMASS_INTA0_CFG_MCAST)" base ad:0x4B91110000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_9_UDMASS_INTA0__CFG__MCAST_mcmap,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces. The index of each of the two egress events is stored in this.." bitfld.quad 0x0 63. "IRQMODE1,IRQ Mode Flag 1. When set this register act like a mapper with bitnum in 37:32 and regnum in 46:38." "0,1" hexmask.quad.word 0x0 32.--47. 1. "GEVIDX1,Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable." bitfld.quad 0x0 31. "IRQMODE0,IRQ Mode Flag 0. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX0,Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_9_UDMASS_INTA0_CFG_GCNTRTI (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_9_UDMASS_INTA0_CFG_GCNTRTI)" base ad:0x4B93800000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_9_UDMASS_INTA0__CFG__GCNTRTI_count,The ETL Count register is read by software to determine how many times the event message has been received. This register can be written to decrement the count by a specified amount to acknowledge that a.." hexmask.quad.long 0x0 0.--31. 1. "CCNT,Current count. This field is incremented by the event count for each message received with this event on the Counted ETL Interface. On write this field will be decremented by the value written. Writing a value greater than the current count is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_9_UDMASS_INTA0_CFG_INTR (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_9_UDMASS_INTA0_CFG_INTR)" base ad:0x4B93D00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_9_UDMASS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_9_UDMASS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_9_UDMASS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_9_UDMASS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_9_UDMASS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_10_UDMASS_INTA0_CFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_10_UDMASS_INTA0_CFG)" base ad:0x4BA0802000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_10_UDMASS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_10_UDMASS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_10_UDMASS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_10_UDMASS_INTA0_CFG_UNMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_10_UDMASS_INTA0_CFG_UNMAP)" base ad:0x4BA0880000 rgroup.quad 0x3000++0x7 line.quad 0x0 "VIRT_ALIAS_10_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x4000++0x7 line.quad 0x0 "VIRT_ALIAS_10_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x5000++0x7 line.quad 0x0 "VIRT_ALIAS_10_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x6000++0x7 line.quad 0x0 "VIRT_ALIAS_10_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x7000++0x7 line.quad 0x0 "VIRT_ALIAS_10_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x8000++0x7 line.quad 0x0 "VIRT_ALIAS_10_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_10_UDMASS_INTA0_CFG_IMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_10_UDMASS_INTA0_CFG_IMAP)" base ad:0x4BA0940000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_10_UDMASS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_10_UDMASS_INTA0_CFG_GCNTCFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_10_UDMASS_INTA0_CFG_GCNTCFG)" base ad:0x4BA1040000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_10_UDMASS_INTA0__CFG__GCNTCFG_map,The Global Event Mapping register controls the egress global event index for this event count. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_10_UDMASS_INTA0_CFG_L2G (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_10_UDMASS_INTA0_CFG_L2G)" base ad:0x4BA1100000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_10_UDMASS_INTA0__CFG__L2G_map,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane. Both pulse and rising edge local event types are supported. With pulsed events. the event.." bitfld.quad 0x0 31. "MODE,Local event detection mode. This field is set to 0 for pulsed events and to 1 for rising edge eventss" "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_10_UDMASS_INTA0_CFG_MCAST (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_10_UDMASS_INTA0_CFG_MCAST)" base ad:0x4BA1110000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_10_UDMASS_INTA0__CFG__MCAST_mcmap,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces. The index of each of the two egress events is stored in this.." bitfld.quad 0x0 63. "IRQMODE1,IRQ Mode Flag 1. When set this register act like a mapper with bitnum in 37:32 and regnum in 46:38." "0,1" hexmask.quad.word 0x0 32.--47. 1. "GEVIDX1,Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable." bitfld.quad 0x0 31. "IRQMODE0,IRQ Mode Flag 0. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX0,Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_10_UDMASS_INTA0_CFG_GCNTRTI (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_10_UDMASS_INTA0_CFG_GCNTRTI)" base ad:0x4BA3800000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_10_UDMASS_INTA0__CFG__GCNTRTI_count,The ETL Count register is read by software to determine how many times the event message has been received. This register can be written to decrement the count by a specified amount to acknowledge that a.." hexmask.quad.long 0x0 0.--31. 1. "CCNT,Current count. This field is incremented by the event count for each message received with this event on the Counted ETL Interface. On write this field will be decremented by the value written. Writing a value greater than the current count is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_10_UDMASS_INTA0_CFG_INTR (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_10_UDMASS_INTA0_CFG_INTR)" base ad:0x4BA3D00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_10_UDMASS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_10_UDMASS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_10_UDMASS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_10_UDMASS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_10_UDMASS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_11_UDMASS_INTA0_CFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_11_UDMASS_INTA0_CFG)" base ad:0x4BB0802000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_11_UDMASS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_11_UDMASS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_11_UDMASS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_11_UDMASS_INTA0_CFG_UNMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_11_UDMASS_INTA0_CFG_UNMAP)" base ad:0x4BB0880000 rgroup.quad 0x3000++0x7 line.quad 0x0 "VIRT_ALIAS_11_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x4000++0x7 line.quad 0x0 "VIRT_ALIAS_11_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x5000++0x7 line.quad 0x0 "VIRT_ALIAS_11_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x6000++0x7 line.quad 0x0 "VIRT_ALIAS_11_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x7000++0x7 line.quad 0x0 "VIRT_ALIAS_11_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x8000++0x7 line.quad 0x0 "VIRT_ALIAS_11_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_11_UDMASS_INTA0_CFG_IMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_11_UDMASS_INTA0_CFG_IMAP)" base ad:0x4BB0940000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_11_UDMASS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_11_UDMASS_INTA0_CFG_GCNTCFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_11_UDMASS_INTA0_CFG_GCNTCFG)" base ad:0x4BB1040000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_11_UDMASS_INTA0__CFG__GCNTCFG_map,The Global Event Mapping register controls the egress global event index for this event count. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_11_UDMASS_INTA0_CFG_L2G (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_11_UDMASS_INTA0_CFG_L2G)" base ad:0x4BB1100000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_11_UDMASS_INTA0__CFG__L2G_map,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane. Both pulse and rising edge local event types are supported. With pulsed events. the event.." bitfld.quad 0x0 31. "MODE,Local event detection mode. This field is set to 0 for pulsed events and to 1 for rising edge eventss" "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_11_UDMASS_INTA0_CFG_MCAST (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_11_UDMASS_INTA0_CFG_MCAST)" base ad:0x4BB1110000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_11_UDMASS_INTA0__CFG__MCAST_mcmap,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces. The index of each of the two egress events is stored in this.." bitfld.quad 0x0 63. "IRQMODE1,IRQ Mode Flag 1. When set this register act like a mapper with bitnum in 37:32 and regnum in 46:38." "0,1" hexmask.quad.word 0x0 32.--47. 1. "GEVIDX1,Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable." bitfld.quad 0x0 31. "IRQMODE0,IRQ Mode Flag 0. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX0,Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_11_UDMASS_INTA0_CFG_GCNTRTI (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_11_UDMASS_INTA0_CFG_GCNTRTI)" base ad:0x4BB3800000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_11_UDMASS_INTA0__CFG__GCNTRTI_count,The ETL Count register is read by software to determine how many times the event message has been received. This register can be written to decrement the count by a specified amount to acknowledge that a.." hexmask.quad.long 0x0 0.--31. 1. "CCNT,Current count. This field is incremented by the event count for each message received with this event on the Counted ETL Interface. On write this field will be decremented by the value written. Writing a value greater than the current count is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_11_UDMASS_INTA0_CFG_INTR (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_11_UDMASS_INTA0_CFG_INTR)" base ad:0x4BB3D00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_11_UDMASS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_11_UDMASS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_11_UDMASS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_11_UDMASS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_11_UDMASS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_12_UDMASS_INTA0_CFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_12_UDMASS_INTA0_CFG)" base ad:0x4BC0802000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_12_UDMASS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_12_UDMASS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_12_UDMASS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_12_UDMASS_INTA0_CFG_UNMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_12_UDMASS_INTA0_CFG_UNMAP)" base ad:0x4BC0880000 rgroup.quad 0x3000++0x7 line.quad 0x0 "VIRT_ALIAS_12_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x4000++0x7 line.quad 0x0 "VIRT_ALIAS_12_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x5000++0x7 line.quad 0x0 "VIRT_ALIAS_12_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x6000++0x7 line.quad 0x0 "VIRT_ALIAS_12_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x7000++0x7 line.quad 0x0 "VIRT_ALIAS_12_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x8000++0x7 line.quad 0x0 "VIRT_ALIAS_12_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_12_UDMASS_INTA0_CFG_IMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_12_UDMASS_INTA0_CFG_IMAP)" base ad:0x4BC0940000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_12_UDMASS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_12_UDMASS_INTA0_CFG_GCNTCFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_12_UDMASS_INTA0_CFG_GCNTCFG)" base ad:0x4BC1040000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_12_UDMASS_INTA0__CFG__GCNTCFG_map,The Global Event Mapping register controls the egress global event index for this event count. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_12_UDMASS_INTA0_CFG_L2G (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_12_UDMASS_INTA0_CFG_L2G)" base ad:0x4BC1100000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_12_UDMASS_INTA0__CFG__L2G_map,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane. Both pulse and rising edge local event types are supported. With pulsed events. the event.." bitfld.quad 0x0 31. "MODE,Local event detection mode. This field is set to 0 for pulsed events and to 1 for rising edge eventss" "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_12_UDMASS_INTA0_CFG_MCAST (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_12_UDMASS_INTA0_CFG_MCAST)" base ad:0x4BC1110000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_12_UDMASS_INTA0__CFG__MCAST_mcmap,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces. The index of each of the two egress events is stored in this.." bitfld.quad 0x0 63. "IRQMODE1,IRQ Mode Flag 1. When set this register act like a mapper with bitnum in 37:32 and regnum in 46:38." "0,1" hexmask.quad.word 0x0 32.--47. 1. "GEVIDX1,Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable." bitfld.quad 0x0 31. "IRQMODE0,IRQ Mode Flag 0. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX0,Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_12_UDMASS_INTA0_CFG_GCNTRTI (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_12_UDMASS_INTA0_CFG_GCNTRTI)" base ad:0x4BC3800000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_12_UDMASS_INTA0__CFG__GCNTRTI_count,The ETL Count register is read by software to determine how many times the event message has been received. This register can be written to decrement the count by a specified amount to acknowledge that a.." hexmask.quad.long 0x0 0.--31. 1. "CCNT,Current count. This field is incremented by the event count for each message received with this event on the Counted ETL Interface. On write this field will be decremented by the value written. Writing a value greater than the current count is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_12_UDMASS_INTA0_CFG_INTR (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_12_UDMASS_INTA0_CFG_INTR)" base ad:0x4BC3D00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_12_UDMASS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_12_UDMASS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_12_UDMASS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_12_UDMASS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_12_UDMASS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_13_UDMASS_INTA0_CFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_13_UDMASS_INTA0_CFG)" base ad:0x4BD0802000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_13_UDMASS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_13_UDMASS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_13_UDMASS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_13_UDMASS_INTA0_CFG_UNMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_13_UDMASS_INTA0_CFG_UNMAP)" base ad:0x4BD0880000 rgroup.quad 0x3000++0x7 line.quad 0x0 "VIRT_ALIAS_13_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x4000++0x7 line.quad 0x0 "VIRT_ALIAS_13_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x5000++0x7 line.quad 0x0 "VIRT_ALIAS_13_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x6000++0x7 line.quad 0x0 "VIRT_ALIAS_13_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x7000++0x7 line.quad 0x0 "VIRT_ALIAS_13_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x8000++0x7 line.quad 0x0 "VIRT_ALIAS_13_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_13_UDMASS_INTA0_CFG_IMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_13_UDMASS_INTA0_CFG_IMAP)" base ad:0x4BD0940000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_13_UDMASS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_13_UDMASS_INTA0_CFG_GCNTCFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_13_UDMASS_INTA0_CFG_GCNTCFG)" base ad:0x4BD1040000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_13_UDMASS_INTA0__CFG__GCNTCFG_map,The Global Event Mapping register controls the egress global event index for this event count. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_13_UDMASS_INTA0_CFG_L2G (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_13_UDMASS_INTA0_CFG_L2G)" base ad:0x4BD1100000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_13_UDMASS_INTA0__CFG__L2G_map,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane. Both pulse and rising edge local event types are supported. With pulsed events. the event.." bitfld.quad 0x0 31. "MODE,Local event detection mode. This field is set to 0 for pulsed events and to 1 for rising edge eventss" "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_13_UDMASS_INTA0_CFG_MCAST (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_13_UDMASS_INTA0_CFG_MCAST)" base ad:0x4BD1110000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_13_UDMASS_INTA0__CFG__MCAST_mcmap,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces. The index of each of the two egress events is stored in this.." bitfld.quad 0x0 63. "IRQMODE1,IRQ Mode Flag 1. When set this register act like a mapper with bitnum in 37:32 and regnum in 46:38." "0,1" hexmask.quad.word 0x0 32.--47. 1. "GEVIDX1,Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable." bitfld.quad 0x0 31. "IRQMODE0,IRQ Mode Flag 0. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX0,Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_13_UDMASS_INTA0_CFG_GCNTRTI (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_13_UDMASS_INTA0_CFG_GCNTRTI)" base ad:0x4BD3800000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_13_UDMASS_INTA0__CFG__GCNTRTI_count,The ETL Count register is read by software to determine how many times the event message has been received. This register can be written to decrement the count by a specified amount to acknowledge that a.." hexmask.quad.long 0x0 0.--31. 1. "CCNT,Current count. This field is incremented by the event count for each message received with this event on the Counted ETL Interface. On write this field will be decremented by the value written. Writing a value greater than the current count is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_13_UDMASS_INTA0_CFG_INTR (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_13_UDMASS_INTA0_CFG_INTR)" base ad:0x4BD3D00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_13_UDMASS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_13_UDMASS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_13_UDMASS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_13_UDMASS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_13_UDMASS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_14_UDMASS_INTA0_CFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_14_UDMASS_INTA0_CFG)" base ad:0x4BE0802000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_14_UDMASS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_14_UDMASS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_14_UDMASS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_14_UDMASS_INTA0_CFG_UNMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_14_UDMASS_INTA0_CFG_UNMAP)" base ad:0x4BE0880000 rgroup.quad 0x3000++0x7 line.quad 0x0 "VIRT_ALIAS_14_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x4000++0x7 line.quad 0x0 "VIRT_ALIAS_14_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x5000++0x7 line.quad 0x0 "VIRT_ALIAS_14_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x6000++0x7 line.quad 0x0 "VIRT_ALIAS_14_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x7000++0x7 line.quad 0x0 "VIRT_ALIAS_14_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x8000++0x7 line.quad 0x0 "VIRT_ALIAS_14_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_14_UDMASS_INTA0_CFG_IMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_14_UDMASS_INTA0_CFG_IMAP)" base ad:0x4BE0940000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_14_UDMASS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_14_UDMASS_INTA0_CFG_GCNTCFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_14_UDMASS_INTA0_CFG_GCNTCFG)" base ad:0x4BE1040000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_14_UDMASS_INTA0__CFG__GCNTCFG_map,The Global Event Mapping register controls the egress global event index for this event count. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_14_UDMASS_INTA0_CFG_L2G (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_14_UDMASS_INTA0_CFG_L2G)" base ad:0x4BE1100000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_14_UDMASS_INTA0__CFG__L2G_map,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane. Both pulse and rising edge local event types are supported. With pulsed events. the event.." bitfld.quad 0x0 31. "MODE,Local event detection mode. This field is set to 0 for pulsed events and to 1 for rising edge eventss" "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_14_UDMASS_INTA0_CFG_MCAST (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_14_UDMASS_INTA0_CFG_MCAST)" base ad:0x4BE1110000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_14_UDMASS_INTA0__CFG__MCAST_mcmap,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces. The index of each of the two egress events is stored in this.." bitfld.quad 0x0 63. "IRQMODE1,IRQ Mode Flag 1. When set this register act like a mapper with bitnum in 37:32 and regnum in 46:38." "0,1" hexmask.quad.word 0x0 32.--47. 1. "GEVIDX1,Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable." bitfld.quad 0x0 31. "IRQMODE0,IRQ Mode Flag 0. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX0,Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_14_UDMASS_INTA0_CFG_GCNTRTI (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_14_UDMASS_INTA0_CFG_GCNTRTI)" base ad:0x4BE3800000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_14_UDMASS_INTA0__CFG__GCNTRTI_count,The ETL Count register is read by software to determine how many times the event message has been received. This register can be written to decrement the count by a specified amount to acknowledge that a.." hexmask.quad.long 0x0 0.--31. 1. "CCNT,Current count. This field is incremented by the event count for each message received with this event on the Counted ETL Interface. On write this field will be decremented by the value written. Writing a value greater than the current count is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_14_UDMASS_INTA0_CFG_INTR (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_14_UDMASS_INTA0_CFG_INTR)" base ad:0x4BE3D00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_14_UDMASS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_14_UDMASS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_14_UDMASS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_14_UDMASS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_14_UDMASS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_15_UDMASS_INTA0_CFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_15_UDMASS_INTA0_CFG)" base ad:0x4BF0802000 rgroup.quad 0x0++0x17 line.quad 0x0 "VIRT_ALIAS_15_UDMASS_INTA0__CFG__CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "VIRT_ALIAS_15_UDMASS_INTA0__CFG__CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "VIRT_ALIAS_15_UDMASS_INTA0__CFG__CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_15_UDMASS_INTA0_CFG_UNMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_15_UDMASS_INTA0_CFG_UNMAP)" base ad:0x4BF0880000 rgroup.quad 0x3000++0x7 line.quad 0x0 "VIRT_ALIAS_15_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x4000++0x7 line.quad 0x0 "VIRT_ALIAS_15_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x5000++0x7 line.quad 0x0 "VIRT_ALIAS_15_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x6000++0x7 line.quad 0x0 "VIRT_ALIAS_15_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x7000++0x7 line.quad 0x0 "VIRT_ALIAS_15_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." rgroup.quad 0x8000++0x7 line.quad 0x0 "VIRT_ALIAS_15_UDMASS_INTA0__CFG__UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_15_UDMASS_INTA0_CFG_IMAP (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_15_UDMASS_INTA0_CFG_IMAP)" base ad:0x4BF0940000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_15_UDMASS_INTA0__CFG__IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_15_UDMASS_INTA0_CFG_GCNTCFG (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_15_UDMASS_INTA0_CFG_GCNTCFG)" base ad:0x4BF1040000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_15_UDMASS_INTA0__CFG__GCNTCFG_map,The Global Event Mapping register controls the egress global event index for this event count. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_15_UDMASS_INTA0_CFG_L2G (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_15_UDMASS_INTA0_CFG_L2G)" base ad:0x4BF1100000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_15_UDMASS_INTA0__CFG__L2G_map,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane. Both pulse and rising edge local event types are supported. With pulsed events. the event.." bitfld.quad 0x0 31. "MODE,Local event detection mode. This field is set to 0 for pulsed events and to 1 for rising edge eventss" "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_15_UDMASS_INTA0_CFG_MCAST (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_15_UDMASS_INTA0_CFG_MCAST)" base ad:0x4BF1110000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_15_UDMASS_INTA0__CFG__MCAST_mcmap,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces. The index of each of the two egress events is stored in this.." bitfld.quad 0x0 63. "IRQMODE1,IRQ Mode Flag 1. When set this register act like a mapper with bitnum in 37:32 and regnum in 46:38." "0,1" hexmask.quad.word 0x0 32.--47. 1. "GEVIDX1,Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable." bitfld.quad 0x0 31. "IRQMODE0,IRQ Mode Flag 0. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX0,Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_15_UDMASS_INTA0_CFG_GCNTRTI (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_15_UDMASS_INTA0_CFG_GCNTRTI)" base ad:0x4BF3800000 rgroup.quad 0x0++0x7 line.quad 0x0 "VIRT_ALIAS_15_UDMASS_INTA0__CFG__GCNTRTI_count,The ETL Count register is read by software to determine how many times the event message has been received. This register can be written to decrement the count by a specified amount to acknowledge that a.." hexmask.quad.long 0x0 0.--31. 1. "CCNT,Current count. This field is incremented by the event count for each message received with this event on the Counted ETL Interface. On write this field will be decremented by the value written. Writing a value greater than the current count is.." tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_15_UDMASS_INTA0_CFG_INTR (NAVSS0_UDMASS_INTA_0_VIRT_ALIAS_15_UDMASS_INTA0_CFG_INTR)" base ad:0x4BF3D00000 rgroup.quad 0x0++0x27 line.quad 0x0 "VIRT_ALIAS_15_UDMASS_INTA0__CFG__INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual.." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "VIRT_ALIAS_15_UDMASS_INTA0__CFG__INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive.." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "VIRT_ALIAS_15_UDMASS_INTA0__CFG__INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "VIRT_ALIAS_15_UDMASS_INTA0__CFG__INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "VIRT_ALIAS_15_UDMASS_INTA0__CFG__INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end endif tree.end tree "NAVSS0_VIRTSS_ECC_AGGR" sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_VIRTSS_ECC_AGGR_0_VIRTSS_ECCAGGR_CFG (NAVSS0_VIRTSS_ECC_AGGR_0_VIRTSS_ECCAGGR_CFG)" base ad:0x31002000 rgroup.long 0x0++0x3 line.long 0x0 "VIRTSS_ECCAGGR_CFG_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "VIRTSS_ECCAGGR_CFG_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "VIRTSS_ECCAGGR_CFG_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "VIRTSS_ECCAGGR_CFG_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "VIRTSS_ECCAGGR_CFG_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x7 line.long 0x0 "VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0xB line.long 0x0 "VIRTSS_ECCAGGR_CFG_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x7 line.long 0x0 "VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "VIRTSS_ECCAGGR_CFG_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "VIRTSS_ECCAGGR_CFG_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG (NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG)" base ad:0x4B01002000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0xB line.long 0x0 "VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x7 line.long 0x0 "VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG (NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG)" base ad:0x4B11002000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0xB line.long 0x0 "VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x7 line.long 0x0 "VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG (NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG)" base ad:0x4B21002000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0xB line.long 0x0 "VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x7 line.long 0x0 "VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG (NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG)" base ad:0x4B31002000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0xB line.long 0x0 "VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x7 line.long 0x0 "VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG (NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG)" base ad:0x4B41002000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0xB line.long 0x0 "VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x7 line.long 0x0 "VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG (NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG)" base ad:0x4B51002000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0xB line.long 0x0 "VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x7 line.long 0x0 "VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG (NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG)" base ad:0x4B61002000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0xB line.long 0x0 "VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x7 line.long 0x0 "VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG (NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG)" base ad:0x4B71002000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0xB line.long 0x0 "VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x7 line.long 0x0 "VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG (NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG)" base ad:0x4B81002000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0xB line.long 0x0 "VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x7 line.long 0x0 "VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG (NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG)" base ad:0x4B91002000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0xB line.long 0x0 "VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x7 line.long 0x0 "VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG (NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG)" base ad:0x4BA1002000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0xB line.long 0x0 "VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x7 line.long 0x0 "VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG (NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG)" base ad:0x4BB1002000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0xB line.long 0x0 "VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x7 line.long 0x0 "VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG (NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG)" base ad:0x4BC1002000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0xB line.long 0x0 "VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x7 line.long 0x0 "VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG (NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG)" base ad:0x4BD1002000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0xB line.long 0x0 "VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x7 line.long 0x0 "VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG (NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG)" base ad:0x4BE1002000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0xB line.long 0x0 "VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x7 line.long 0x0 "VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif sif (cpuis("TDA4VE88")||cpuis("TDA4AL88")||cpuis("AM68Ax")) tree "NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG (NAVSS0_VIRTSS_ECC_AGGR_0_VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG)" base ad:0x4BF1002000 rgroup.long 0x0++0x3 line.long 0x0 "VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG_REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x80++0x7 line.long 0x0 "VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG_REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x13C++0xB line.long 0x0 "VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "IO_PVU1_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 9. "PVU0_DST_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 8. "PVU0_CFG_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 7. "PVU0_CFG_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "PVU0_CFG_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PVU0_SRC_TOG_EDC_CTRL_PEND,Interrupt Pending Status for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 4. "PVU0_SRC_TOG_RD_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PVU0_SRC_TOG_WR_RAMECC_PEND,Interrupt Pending Status for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 1. "IO_PVU0_TLB_BANK_RAMCC_PEND,Interrupt Pending Status for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG_REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" rgroup.long 0x180++0x7 line.long 0x0 "VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_SET,Interrupt Enable Set Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "NAVSS512J7AM_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_VIRTSS_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_virtss_cfg_p2p_bridge_virtss_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 30. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 29. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 28. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 27. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 26. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 25. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST5_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "NAVSS512J7AM_VIRTSS_IO_PVU1_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu1_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 10. "IO_PVU1_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu1_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 9. "PVU0_DST_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_dst_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 8. "PVU0_CFG_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 7. "PVU0_CFG_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "PVU0_CFG_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_cfg_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PVU0_SRC_TOG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 4. "PVU0_SRC_TOG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PVU0_SRC_TOG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pvu0_src_tog_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "NAVSS512J7AM_VIRTSS_IO_PVU0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_io_pvu0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 1. "IO_PVU0_TLB_BANK_RAMCC_ENABLE_CLR,Interrupt Enable Clear Register for io_pvu0_tlb_bank_ramcc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG_REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 24. "NAVSS512J7AM_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_CBASS_INT_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_gclk_edc_ctrl_cbass_int_gbusecc_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 22. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 21. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_NAVSS512J7AM_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 20. "NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_cfg_scr_scr_navss512j7am_virtss_data_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 19. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 18. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 17. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 16. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 15. "NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_NAVSS512J7AM_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_scr_scr_navss512j7am_virtss_data_cbass_scr_scr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 14. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_PVU0_CFG_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_cfg_tog_cfg_p2p_bridge_pvu0_cfg_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 13. "NAVSS512J7AM_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_PVU0_SRC_TOG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_pvu0_src_tog_cfg_p2p_bridge_pvu0_src_tog_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 12. "NAVSS512J7AM_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss512j7am_virtss_data_cbass_eccaggr_cfg_p2p_bridge_eccaggr_cfg_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 11. "NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 10. "NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 9. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV4_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 6. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 5. "NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 4. "NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 3. "NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 2. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 1. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 0. "NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_NAVSS512J7AM_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" rgroup.long 0x200++0xF line.long 0x0 "VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end endif tree.end tree.end endif tree "PBIST" base ad:0x0 tree "PBIST0 (PBIST0)" base ad:0xD00000 rgroup.long 0x0++0x7F line.long 0x0 "MEM_RF0L," hexmask.long 0x0 0.--31. 1. "RF0L,Register Files / Instruction Registers RF0 lower (RF0L)" line.long 0x4 "MEM_RF1L," hexmask.long 0x4 0.--31. 1. "RF1L,Register Files / Instruction Registers RF1 lower (RF1L)" line.long 0x8 "MEM_RF2L," hexmask.long 0x8 0.--31. 1. "RF2L,Register Files / Instruction Registers RF2 lower (RF2L)" line.long 0xC "MEM_RF3L," hexmask.long 0xC 0.--31. 1. "RF3L,Register Files / Instruction Registers RF3 lower (RF3L)" line.long 0x10 "MEM_RF4L," hexmask.long 0x10 0.--31. 1. "RF4L,Register Files / Instruction Registers RF4 lower (RF4L)" line.long 0x14 "MEM_RF5L," hexmask.long 0x14 0.--31. 1. "RF5L,Register Files / Instruction Registers RF5 lower (RF5L)" line.long 0x18 "MEM_RF6L," hexmask.long 0x18 0.--31. 1. "RF6L,Register Files / Instruction Registers RF6 lower (RF6L)" line.long 0x1C "MEM_RF7L," hexmask.long 0x1C 0.--31. 1. "RF7L,Register Files / Instruction Registers RF7 lower (RF7L)" line.long 0x20 "MEM_RF8L," hexmask.long 0x20 0.--31. 1. "RF8L,Register Files / Instruction Registers RF8 lower (RF8L)" line.long 0x24 "MEM_RF9L," hexmask.long 0x24 0.--31. 1. "RF9L,Register Files / Instruction Registers RF9 lower (RF9L)" line.long 0x28 "MEM_RF10L," hexmask.long 0x28 0.--31. 1. "RF10L,Register Files / Instruction Registers RF10 lower (RF10L)" line.long 0x2C "MEM_RF11L," hexmask.long 0x2C 0.--31. 1. "RF11L,Register Files / Instruction Registers RF11 lower (RF11L)" line.long 0x30 "MEM_RF12L," hexmask.long 0x30 0.--31. 1. "RF12L,Register Files / Instruction Registers RF12 lower (RF12L)" line.long 0x34 "MEM_RF13L," hexmask.long 0x34 0.--31. 1. "RF13L,Register Files / Instruction Registers RF13 lower (RF13L)" line.long 0x38 "MEM_RF14L," hexmask.long 0x38 0.--31. 1. "RF14L,Register Files / Instruction Registers RF14 lower (RF14L)" line.long 0x3C "MEM_RF15L," hexmask.long 0x3C 0.--31. 1. "RF15L,Register Files / Instruction Registers RF15 lower (RF15L)" line.long 0x40 "MEM_RF0U," hexmask.long 0x40 0.--31. 1. "RF0U,Register Files / Instruction Registers RF0 upper (RF0U)" line.long 0x44 "MEM_RF1U," hexmask.long 0x44 0.--31. 1. "RF1U,Register Files / Instruction Registers RF1 upper (RF1U)" line.long 0x48 "MEM_RF2U," hexmask.long 0x48 0.--31. 1. "RF2U,Register Files / Instruction Registers RF2 upper (RF2U)" line.long 0x4C "MEM_RF3U," hexmask.long 0x4C 0.--31. 1. "RF3U,Register Files / Instruction Registers RF3 upper (RF3U)" line.long 0x50 "MEM_RF4U," hexmask.long 0x50 0.--31. 1. "RF4U,Register Files / Instruction Registers RF4 upper (RF4U)" line.long 0x54 "MEM_RF5U," hexmask.long 0x54 0.--31. 1. "RF5U,Register Files / Instruction Registers RF5 upper (RF5U)" line.long 0x58 "MEM_RF6U," hexmask.long 0x58 0.--31. 1. "RF6U,Register Files / Instruction Registers RF6 upper (RF6U)" line.long 0x5C "MEM_RF7U," hexmask.long 0x5C 0.--31. 1. "RF7U,Register Files / Instruction Registers RF7 upper (RF7U)" line.long 0x60 "MEM_RF8U," hexmask.long 0x60 0.--31. 1. "RF8U,Register Files / Instruction Registers RF8 upper (RF8U)" line.long 0x64 "MEM_RF9U," hexmask.long 0x64 0.--31. 1. "RF9U,Register Files / Instruction Registers RF9 upper (RF9U)" line.long 0x68 "MEM_RF10U," hexmask.long 0x68 0.--31. 1. "RF10U,Register Files / Instruction Registers RF10 upper (RF10U)" line.long 0x6C "MEM_RF11U," hexmask.long 0x6C 0.--31. 1. "RF11U,Register Files / Instruction Registers RF11 upper (RF11U)" line.long 0x70 "MEM_RF12U," hexmask.long 0x70 0.--31. 1. "RF12U,Register Files / Instruction Registers RF12 upper (RF12U)" line.long 0x74 "MEM_RF13U," hexmask.long 0x74 0.--31. 1. "RF13U,Register Files / Instruction Registers RF13 upper (RF13U)" line.long 0x78 "MEM_RF14U," hexmask.long 0x78 0.--31. 1. "RF14U,Register Files / Instruction Registers RF14 upper (RF14U)" line.long 0x7C "MEM_RF15U," hexmask.long 0x7C 0.--31. 1. "RF15U,Register Files / Instruction Registers RF15 upper (RF15U)" rgroup.long 0x100++0x27 line.long 0x0 "MEM_A0," hexmask.long.word 0x0 0.--15. 1. "A0,Variable Address Register 0 (A0)" line.long 0x4 "MEM_A1," hexmask.long.word 0x4 0.--15. 1. "A1,Variable Address Register 1 (A1)" line.long 0x8 "MEM_A2," hexmask.long.word 0x8 0.--15. 1. "A2,Variable Address Register 2 (A2)" line.long 0xC "MEM_A3," hexmask.long.word 0xC 0.--15. 1. "A3,Variable Address Register 3 (A3)" line.long 0x10 "MEM_L0," hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 (L0)" line.long 0x14 "MEM_L1," hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 (L1)" line.long 0x18 "MEM_L2," hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 (L2)" line.long 0x1C "MEM_L3," hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 (L3)" line.long 0x20 "MEM_D," hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 (D1)" hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 (D0)" line.long 0x24 "MEM_E," hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 (E1)" hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 (E0)" rgroup.long 0x130++0x3F line.long 0x0 "MEM_CA0," hexmask.long.word 0x0 0.--15. 1. "CA0,Constant Address Register 0 (CA0)" line.long 0x4 "MEM_CA1," hexmask.long.word 0x4 0.--15. 1. "CA1,Constant Address Register 1 (CA1)" line.long 0x8 "MEM_CA2," hexmask.long.word 0x8 0.--15. 1. "CA2,Constant Address Register 2 (CA2)" line.long 0xC "MEM_CA3," hexmask.long.word 0xC 0.--15. 1. "CA3,Constant Address Register 3 (CA3)" line.long 0x10 "MEM_CL0," hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 (CL0)" line.long 0x14 "MEM_CL1," hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 (CL1)" line.long 0x18 "MEM_CL2," hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 (CL2)" line.long 0x1C "MEM_CL3," hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 (CL3)" line.long 0x20 "MEM_I0," hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 (I0)" line.long 0x24 "MEM_I1," hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 (I1)" line.long 0x28 "MEM_I2," hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 (I2)" line.long 0x2C "MEM_I3," hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 (I3)" line.long 0x30 "MEM_RAMT," hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS" hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS" hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR" hexmask.long.byte 0x30 2.--5. 1. "PLS,Pipeline Latency Select" bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3" line.long 0x34 "MEM_DLR," hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 (BRP)" bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1" bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1" bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode (mainly for ROM testing)" "0,1" bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1" newline bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1" bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1" bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1" bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1" bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1" newline bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1" bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1" line.long 0x38 "MEM_CMS," hexmask.long.byte 0x38 0.--3. 1. "CMS,Clock Mux Select (CMS)" line.long 0x3C "MEM_STR," bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1" bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1" bitfld.long 0x3C 2. "STOP,Stop" "0,1" bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1" bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1" rgroup.quad 0x170++0x7 line.quad 0x0 "MEM_SCR," hexmask.quad.byte 0x0 56.--63. 1. "SCR7,Address Scrambling Register 7" hexmask.quad.byte 0x0 48.--55. 1. "SCR6,Address Scrambling Register 6" hexmask.quad.byte 0x0 40.--47. 1. "SCR5,Address Scrambling Register 5" hexmask.quad.byte 0x0 32.--39. 1. "SCR4,Address Scrambling Register 4" hexmask.quad.byte 0x0 24.--31. 1. "SCR3,Address Scrambling Register 3" newline hexmask.quad.byte 0x0 16.--23. 1. "SCR2,Address Scrambling Register 2" hexmask.quad.byte 0x0 8.--15. 1. "SCR1,Address Scrambling Register 1" hexmask.quad.byte 0x0 0.--7. 1. "SCR0,Address Scrambling Register 0" rgroup.long 0x178++0x13 line.long 0x0 "MEM_CSR," hexmask.long.byte 0x0 24.--31. 1. "CSR3,Chip Select 3 (CSR3)" hexmask.long.byte 0x0 16.--23. 1. "CSR2,Chip Select 2 (CSR2)" hexmask.long.byte 0x0 8.--15. 1. "CSR1,Chip Select 1(CSR1)" hexmask.long.byte 0x0 0.--7. 1. "CSR0,Chip Select 0 (CSR0)" line.long 0x4 "MEM_FDLY," hexmask.long.byte 0x4 0.--7. 1. "FDLY,Fail Delay (FDLY)" line.long 0x8 "MEM_PACT," bitfld.long 0x8 0. "PACT,PBIST Activate (PACT)" "0,1" line.long 0xC "MEM_PID," hexmask.long.byte 0xC 0.--4. 1. "PID,PBIST ID" line.long 0x10 "MEM_OVER," bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1" bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1" bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1" bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1" rgroup.quad 0x190++0x17 line.quad 0x0 "MEM_FSRF," bitfld.quad 0x0 32. "FRSF1,Fail Status Fail - Port 1 (FSRF1)" "0,1" bitfld.quad 0x0 0. "FRSF0,Fail Status Fail - Port 0 (FSRF0)" "0,1" line.quad 0x8 "MEM_FSRC," hexmask.quad.byte 0x8 32.--35. 1. "FSRC1,Fail Status Count - Port 1 (FSRC1)" hexmask.quad.byte 0x8 0.--3. 1. "FSRC0,Fail Status Count - Port 0 (FSRC0)" line.quad 0x10 "MEM_FSRA," hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 (FSRA1)" hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 (FSRA0)" rgroup.long 0x1A8++0x3 line.long 0x0 "MEM_FSRDL0," hexmask.long 0x0 0.--31. 1. "FSRDL0,Fail Status Data - Port 0 (FSRDL0)" rgroup.long 0x1B0++0xF line.long 0x0 "MEM_FSRDL1," hexmask.long 0x0 0.--31. 1. "FSRDL1,Fail Status Data - Port 1 (FSRDL1)" line.long 0x4 "MEM_MARGIN_MODE," bitfld.long 0x4 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3" bitfld.long 0x4 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3" line.long 0x8 "MEM_WRENZ," bitfld.long 0x8 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3" line.long 0xC "MEM_PAGE_PGS," bitfld.long 0xC 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3" rgroup.long 0x1C0++0x7 line.long 0x0 "MEM_ROM," bitfld.long 0x0 0.--1. "ROM,ROM Mask (ROM)" "0,1,2,3" line.long 0x4 "MEM_ALGO," hexmask.long.byte 0x4 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 (ALGO 3)" hexmask.long.byte 0x4 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 (ALGO 2)" hexmask.long.byte 0x4 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 (ALGO 1)" hexmask.long.byte 0x4 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 (ALGO 0)" rgroup.quad 0x1C8++0x7 line.quad 0x0 "MEM_RINFO," hexmask.quad.byte 0x0 56.--63. 1. "U3,RAM Info Mask Upper 3 (RINFOU3)" hexmask.quad.byte 0x0 48.--55. 1. "U2,RAM Info Mask Upper 2 (RINFOU2)" hexmask.quad.byte 0x0 40.--47. 1. "U1,RAM Info Mask Upper 1 (RINFOU1)" hexmask.quad.byte 0x0 32.--39. 1. "U0,RAM Info Mask Upper 0 (RINFOU0)" hexmask.quad.byte 0x0 24.--31. 1. "L3,RAM Info Mask Lower 3 (RINFOL3)" newline hexmask.quad.byte 0x0 16.--23. 1. "L2,RAM Info Mask Lower 2 (RINFOL2)" hexmask.quad.byte 0x0 8.--15. 1. "L1,RAM Info Mask Lower 1 (RINFOL1)" hexmask.quad.byte 0x0 0.--7. 1. "L0,RAM Info Mask Lower 0 (RINFOL0)" tree.end tree "PBIST1 (PBIST1)" base ad:0xD20000 rgroup.long 0x0++0x7F line.long 0x0 "MEM_RF0L," hexmask.long 0x0 0.--31. 1. "RF0L,Register Files / Instruction Registers RF0 lower (RF0L)" line.long 0x4 "MEM_RF1L," hexmask.long 0x4 0.--31. 1. "RF1L,Register Files / Instruction Registers RF1 lower (RF1L)" line.long 0x8 "MEM_RF2L," hexmask.long 0x8 0.--31. 1. "RF2L,Register Files / Instruction Registers RF2 lower (RF2L)" line.long 0xC "MEM_RF3L," hexmask.long 0xC 0.--31. 1. "RF3L,Register Files / Instruction Registers RF3 lower (RF3L)" line.long 0x10 "MEM_RF4L," hexmask.long 0x10 0.--31. 1. "RF4L,Register Files / Instruction Registers RF4 lower (RF4L)" line.long 0x14 "MEM_RF5L," hexmask.long 0x14 0.--31. 1. "RF5L,Register Files / Instruction Registers RF5 lower (RF5L)" line.long 0x18 "MEM_RF6L," hexmask.long 0x18 0.--31. 1. "RF6L,Register Files / Instruction Registers RF6 lower (RF6L)" line.long 0x1C "MEM_RF7L," hexmask.long 0x1C 0.--31. 1. "RF7L,Register Files / Instruction Registers RF7 lower (RF7L)" line.long 0x20 "MEM_RF8L," hexmask.long 0x20 0.--31. 1. "RF8L,Register Files / Instruction Registers RF8 lower (RF8L)" line.long 0x24 "MEM_RF9L," hexmask.long 0x24 0.--31. 1. "RF9L,Register Files / Instruction Registers RF9 lower (RF9L)" line.long 0x28 "MEM_RF10L," hexmask.long 0x28 0.--31. 1. "RF10L,Register Files / Instruction Registers RF10 lower (RF10L)" line.long 0x2C "MEM_RF11L," hexmask.long 0x2C 0.--31. 1. "RF11L,Register Files / Instruction Registers RF11 lower (RF11L)" line.long 0x30 "MEM_RF12L," hexmask.long 0x30 0.--31. 1. "RF12L,Register Files / Instruction Registers RF12 lower (RF12L)" line.long 0x34 "MEM_RF13L," hexmask.long 0x34 0.--31. 1. "RF13L,Register Files / Instruction Registers RF13 lower (RF13L)" line.long 0x38 "MEM_RF14L," hexmask.long 0x38 0.--31. 1. "RF14L,Register Files / Instruction Registers RF14 lower (RF14L)" line.long 0x3C "MEM_RF15L," hexmask.long 0x3C 0.--31. 1. "RF15L,Register Files / Instruction Registers RF15 lower (RF15L)" line.long 0x40 "MEM_RF0U," hexmask.long 0x40 0.--31. 1. "RF0U,Register Files / Instruction Registers RF0 upper (RF0U)" line.long 0x44 "MEM_RF1U," hexmask.long 0x44 0.--31. 1. "RF1U,Register Files / Instruction Registers RF1 upper (RF1U)" line.long 0x48 "MEM_RF2U," hexmask.long 0x48 0.--31. 1. "RF2U,Register Files / Instruction Registers RF2 upper (RF2U)" line.long 0x4C "MEM_RF3U," hexmask.long 0x4C 0.--31. 1. "RF3U,Register Files / Instruction Registers RF3 upper (RF3U)" line.long 0x50 "MEM_RF4U," hexmask.long 0x50 0.--31. 1. "RF4U,Register Files / Instruction Registers RF4 upper (RF4U)" line.long 0x54 "MEM_RF5U," hexmask.long 0x54 0.--31. 1. "RF5U,Register Files / Instruction Registers RF5 upper (RF5U)" line.long 0x58 "MEM_RF6U," hexmask.long 0x58 0.--31. 1. "RF6U,Register Files / Instruction Registers RF6 upper (RF6U)" line.long 0x5C "MEM_RF7U," hexmask.long 0x5C 0.--31. 1. "RF7U,Register Files / Instruction Registers RF7 upper (RF7U)" line.long 0x60 "MEM_RF8U," hexmask.long 0x60 0.--31. 1. "RF8U,Register Files / Instruction Registers RF8 upper (RF8U)" line.long 0x64 "MEM_RF9U," hexmask.long 0x64 0.--31. 1. "RF9U,Register Files / Instruction Registers RF9 upper (RF9U)" line.long 0x68 "MEM_RF10U," hexmask.long 0x68 0.--31. 1. "RF10U,Register Files / Instruction Registers RF10 upper (RF10U)" line.long 0x6C "MEM_RF11U," hexmask.long 0x6C 0.--31. 1. "RF11U,Register Files / Instruction Registers RF11 upper (RF11U)" line.long 0x70 "MEM_RF12U," hexmask.long 0x70 0.--31. 1. "RF12U,Register Files / Instruction Registers RF12 upper (RF12U)" line.long 0x74 "MEM_RF13U," hexmask.long 0x74 0.--31. 1. "RF13U,Register Files / Instruction Registers RF13 upper (RF13U)" line.long 0x78 "MEM_RF14U," hexmask.long 0x78 0.--31. 1. "RF14U,Register Files / Instruction Registers RF14 upper (RF14U)" line.long 0x7C "MEM_RF15U," hexmask.long 0x7C 0.--31. 1. "RF15U,Register Files / Instruction Registers RF15 upper (RF15U)" rgroup.long 0x100++0x27 line.long 0x0 "MEM_A0," hexmask.long.word 0x0 0.--15. 1. "A0,Variable Address Register 0 (A0)" line.long 0x4 "MEM_A1," hexmask.long.word 0x4 0.--15. 1. "A1,Variable Address Register 1 (A1)" line.long 0x8 "MEM_A2," hexmask.long.word 0x8 0.--15. 1. "A2,Variable Address Register 2 (A2)" line.long 0xC "MEM_A3," hexmask.long.word 0xC 0.--15. 1. "A3,Variable Address Register 3 (A3)" line.long 0x10 "MEM_L0," hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 (L0)" line.long 0x14 "MEM_L1," hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 (L1)" line.long 0x18 "MEM_L2," hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 (L2)" line.long 0x1C "MEM_L3," hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 (L3)" line.long 0x20 "MEM_D," hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 (D1)" hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 (D0)" line.long 0x24 "MEM_E," hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 (E1)" hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 (E0)" rgroup.long 0x130++0x3F line.long 0x0 "MEM_CA0," hexmask.long.word 0x0 0.--15. 1. "CA0,Constant Address Register 0 (CA0)" line.long 0x4 "MEM_CA1," hexmask.long.word 0x4 0.--15. 1. "CA1,Constant Address Register 1 (CA1)" line.long 0x8 "MEM_CA2," hexmask.long.word 0x8 0.--15. 1. "CA2,Constant Address Register 2 (CA2)" line.long 0xC "MEM_CA3," hexmask.long.word 0xC 0.--15. 1. "CA3,Constant Address Register 3 (CA3)" line.long 0x10 "MEM_CL0," hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 (CL0)" line.long 0x14 "MEM_CL1," hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 (CL1)" line.long 0x18 "MEM_CL2," hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 (CL2)" line.long 0x1C "MEM_CL3," hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 (CL3)" line.long 0x20 "MEM_I0," hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 (I0)" line.long 0x24 "MEM_I1," hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 (I1)" line.long 0x28 "MEM_I2," hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 (I2)" line.long 0x2C "MEM_I3," hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 (I3)" line.long 0x30 "MEM_RAMT," hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS" hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS" hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR" hexmask.long.byte 0x30 2.--5. 1. "PLS,Pipeline Latency Select" bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3" line.long 0x34 "MEM_DLR," hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 (BRP)" bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1" bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1" bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode (mainly for ROM testing)" "0,1" bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1" newline bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1" bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1" bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1" bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1" bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1" newline bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1" bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1" line.long 0x38 "MEM_CMS," hexmask.long.byte 0x38 0.--3. 1. "CMS,Clock Mux Select (CMS)" line.long 0x3C "MEM_STR," bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1" bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1" bitfld.long 0x3C 2. "STOP,Stop" "0,1" bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1" bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1" rgroup.quad 0x170++0x7 line.quad 0x0 "MEM_SCR," hexmask.quad.byte 0x0 56.--63. 1. "SCR7,Address Scrambling Register 7" hexmask.quad.byte 0x0 48.--55. 1. "SCR6,Address Scrambling Register 6" hexmask.quad.byte 0x0 40.--47. 1. "SCR5,Address Scrambling Register 5" hexmask.quad.byte 0x0 32.--39. 1. "SCR4,Address Scrambling Register 4" hexmask.quad.byte 0x0 24.--31. 1. "SCR3,Address Scrambling Register 3" newline hexmask.quad.byte 0x0 16.--23. 1. "SCR2,Address Scrambling Register 2" hexmask.quad.byte 0x0 8.--15. 1. "SCR1,Address Scrambling Register 1" hexmask.quad.byte 0x0 0.--7. 1. "SCR0,Address Scrambling Register 0" rgroup.long 0x178++0x13 line.long 0x0 "MEM_CSR," hexmask.long.byte 0x0 24.--31. 1. "CSR3,Chip Select 3 (CSR3)" hexmask.long.byte 0x0 16.--23. 1. "CSR2,Chip Select 2 (CSR2)" hexmask.long.byte 0x0 8.--15. 1. "CSR1,Chip Select 1(CSR1)" hexmask.long.byte 0x0 0.--7. 1. "CSR0,Chip Select 0 (CSR0)" line.long 0x4 "MEM_FDLY," hexmask.long.byte 0x4 0.--7. 1. "FDLY,Fail Delay (FDLY)" line.long 0x8 "MEM_PACT," bitfld.long 0x8 0. "PACT,PBIST Activate (PACT)" "0,1" line.long 0xC "MEM_PID," hexmask.long.byte 0xC 0.--4. 1. "PID,PBIST ID" line.long 0x10 "MEM_OVER," bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1" bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1" bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1" bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1" rgroup.quad 0x190++0x17 line.quad 0x0 "MEM_FSRF," bitfld.quad 0x0 32. "FRSF1,Fail Status Fail - Port 1 (FSRF1)" "0,1" bitfld.quad 0x0 0. "FRSF0,Fail Status Fail - Port 0 (FSRF0)" "0,1" line.quad 0x8 "MEM_FSRC," hexmask.quad.byte 0x8 32.--35. 1. "FSRC1,Fail Status Count - Port 1 (FSRC1)" hexmask.quad.byte 0x8 0.--3. 1. "FSRC0,Fail Status Count - Port 0 (FSRC0)" line.quad 0x10 "MEM_FSRA," hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 (FSRA1)" hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 (FSRA0)" rgroup.long 0x1A8++0x3 line.long 0x0 "MEM_FSRDL0," hexmask.long 0x0 0.--31. 1. "FSRDL0,Fail Status Data - Port 0 (FSRDL0)" rgroup.long 0x1B0++0xF line.long 0x0 "MEM_FSRDL1," hexmask.long 0x0 0.--31. 1. "FSRDL1,Fail Status Data - Port 1 (FSRDL1)" line.long 0x4 "MEM_MARGIN_MODE," bitfld.long 0x4 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3" bitfld.long 0x4 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3" line.long 0x8 "MEM_WRENZ," bitfld.long 0x8 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3" line.long 0xC "MEM_PAGE_PGS," bitfld.long 0xC 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3" rgroup.long 0x1C0++0x7 line.long 0x0 "MEM_ROM," bitfld.long 0x0 0.--1. "ROM,ROM Mask (ROM)" "0,1,2,3" line.long 0x4 "MEM_ALGO," hexmask.long.byte 0x4 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 (ALGO 3)" hexmask.long.byte 0x4 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 (ALGO 2)" hexmask.long.byte 0x4 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 (ALGO 1)" hexmask.long.byte 0x4 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 (ALGO 0)" rgroup.quad 0x1C8++0x7 line.quad 0x0 "MEM_RINFO," hexmask.quad.byte 0x0 56.--63. 1. "U3,RAM Info Mask Upper 3 (RINFOU3)" hexmask.quad.byte 0x0 48.--55. 1. "U2,RAM Info Mask Upper 2 (RINFOU2)" hexmask.quad.byte 0x0 40.--47. 1. "U1,RAM Info Mask Upper 1 (RINFOU1)" hexmask.quad.byte 0x0 32.--39. 1. "U0,RAM Info Mask Upper 0 (RINFOU0)" hexmask.quad.byte 0x0 24.--31. 1. "L3,RAM Info Mask Lower 3 (RINFOL3)" newline hexmask.quad.byte 0x0 16.--23. 1. "L2,RAM Info Mask Lower 2 (RINFOL2)" hexmask.quad.byte 0x0 8.--15. 1. "L1,RAM Info Mask Lower 1 (RINFOL1)" hexmask.quad.byte 0x0 0.--7. 1. "L0,RAM Info Mask Lower 0 (RINFOL0)" tree.end tree "PBIST2 (PBIST2)" base ad:0x3380000 rgroup.long 0x0++0x7F line.long 0x0 "MEM_RF0L," hexmask.long 0x0 0.--31. 1. "RF0L,Register Files / Instruction Registers RF0 lower (RF0L)" line.long 0x4 "MEM_RF1L," hexmask.long 0x4 0.--31. 1. "RF1L,Register Files / Instruction Registers RF1 lower (RF1L)" line.long 0x8 "MEM_RF2L," hexmask.long 0x8 0.--31. 1. "RF2L,Register Files / Instruction Registers RF2 lower (RF2L)" line.long 0xC "MEM_RF3L," hexmask.long 0xC 0.--31. 1. "RF3L,Register Files / Instruction Registers RF3 lower (RF3L)" line.long 0x10 "MEM_RF4L," hexmask.long 0x10 0.--31. 1. "RF4L,Register Files / Instruction Registers RF4 lower (RF4L)" line.long 0x14 "MEM_RF5L," hexmask.long 0x14 0.--31. 1. "RF5L,Register Files / Instruction Registers RF5 lower (RF5L)" line.long 0x18 "MEM_RF6L," hexmask.long 0x18 0.--31. 1. "RF6L,Register Files / Instruction Registers RF6 lower (RF6L)" line.long 0x1C "MEM_RF7L," hexmask.long 0x1C 0.--31. 1. "RF7L,Register Files / Instruction Registers RF7 lower (RF7L)" line.long 0x20 "MEM_RF8L," hexmask.long 0x20 0.--31. 1. "RF8L,Register Files / Instruction Registers RF8 lower (RF8L)" line.long 0x24 "MEM_RF9L," hexmask.long 0x24 0.--31. 1. "RF9L,Register Files / Instruction Registers RF9 lower (RF9L)" line.long 0x28 "MEM_RF10L," hexmask.long 0x28 0.--31. 1. "RF10L,Register Files / Instruction Registers RF10 lower (RF10L)" line.long 0x2C "MEM_RF11L," hexmask.long 0x2C 0.--31. 1. "RF11L,Register Files / Instruction Registers RF11 lower (RF11L)" line.long 0x30 "MEM_RF12L," hexmask.long 0x30 0.--31. 1. "RF12L,Register Files / Instruction Registers RF12 lower (RF12L)" line.long 0x34 "MEM_RF13L," hexmask.long 0x34 0.--31. 1. "RF13L,Register Files / Instruction Registers RF13 lower (RF13L)" line.long 0x38 "MEM_RF14L," hexmask.long 0x38 0.--31. 1. "RF14L,Register Files / Instruction Registers RF14 lower (RF14L)" line.long 0x3C "MEM_RF15L," hexmask.long 0x3C 0.--31. 1. "RF15L,Register Files / Instruction Registers RF15 lower (RF15L)" line.long 0x40 "MEM_RF0U," hexmask.long 0x40 0.--31. 1. "RF0U,Register Files / Instruction Registers RF0 upper (RF0U)" line.long 0x44 "MEM_RF1U," hexmask.long 0x44 0.--31. 1. "RF1U,Register Files / Instruction Registers RF1 upper (RF1U)" line.long 0x48 "MEM_RF2U," hexmask.long 0x48 0.--31. 1. "RF2U,Register Files / Instruction Registers RF2 upper (RF2U)" line.long 0x4C "MEM_RF3U," hexmask.long 0x4C 0.--31. 1. "RF3U,Register Files / Instruction Registers RF3 upper (RF3U)" line.long 0x50 "MEM_RF4U," hexmask.long 0x50 0.--31. 1. "RF4U,Register Files / Instruction Registers RF4 upper (RF4U)" line.long 0x54 "MEM_RF5U," hexmask.long 0x54 0.--31. 1. "RF5U,Register Files / Instruction Registers RF5 upper (RF5U)" line.long 0x58 "MEM_RF6U," hexmask.long 0x58 0.--31. 1. "RF6U,Register Files / Instruction Registers RF6 upper (RF6U)" line.long 0x5C "MEM_RF7U," hexmask.long 0x5C 0.--31. 1. "RF7U,Register Files / Instruction Registers RF7 upper (RF7U)" line.long 0x60 "MEM_RF8U," hexmask.long 0x60 0.--31. 1. "RF8U,Register Files / Instruction Registers RF8 upper (RF8U)" line.long 0x64 "MEM_RF9U," hexmask.long 0x64 0.--31. 1. "RF9U,Register Files / Instruction Registers RF9 upper (RF9U)" line.long 0x68 "MEM_RF10U," hexmask.long 0x68 0.--31. 1. "RF10U,Register Files / Instruction Registers RF10 upper (RF10U)" line.long 0x6C "MEM_RF11U," hexmask.long 0x6C 0.--31. 1. "RF11U,Register Files / Instruction Registers RF11 upper (RF11U)" line.long 0x70 "MEM_RF12U," hexmask.long 0x70 0.--31. 1. "RF12U,Register Files / Instruction Registers RF12 upper (RF12U)" line.long 0x74 "MEM_RF13U," hexmask.long 0x74 0.--31. 1. "RF13U,Register Files / Instruction Registers RF13 upper (RF13U)" line.long 0x78 "MEM_RF14U," hexmask.long 0x78 0.--31. 1. "RF14U,Register Files / Instruction Registers RF14 upper (RF14U)" line.long 0x7C "MEM_RF15U," hexmask.long 0x7C 0.--31. 1. "RF15U,Register Files / Instruction Registers RF15 upper (RF15U)" rgroup.long 0x100++0x27 line.long 0x0 "MEM_A0," hexmask.long.word 0x0 0.--15. 1. "A0,Variable Address Register 0 (A0)" line.long 0x4 "MEM_A1," hexmask.long.word 0x4 0.--15. 1. "A1,Variable Address Register 1 (A1)" line.long 0x8 "MEM_A2," hexmask.long.word 0x8 0.--15. 1. "A2,Variable Address Register 2 (A2)" line.long 0xC "MEM_A3," hexmask.long.word 0xC 0.--15. 1. "A3,Variable Address Register 3 (A3)" line.long 0x10 "MEM_L0," hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 (L0)" line.long 0x14 "MEM_L1," hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 (L1)" line.long 0x18 "MEM_L2," hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 (L2)" line.long 0x1C "MEM_L3," hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 (L3)" line.long 0x20 "MEM_D," hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 (D1)" hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 (D0)" line.long 0x24 "MEM_E," hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 (E1)" hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 (E0)" rgroup.long 0x130++0x3F line.long 0x0 "MEM_CA0," hexmask.long.word 0x0 0.--15. 1. "CA0,Constant Address Register 0 (CA0)" line.long 0x4 "MEM_CA1," hexmask.long.word 0x4 0.--15. 1. "CA1,Constant Address Register 1 (CA1)" line.long 0x8 "MEM_CA2," hexmask.long.word 0x8 0.--15. 1. "CA2,Constant Address Register 2 (CA2)" line.long 0xC "MEM_CA3," hexmask.long.word 0xC 0.--15. 1. "CA3,Constant Address Register 3 (CA3)" line.long 0x10 "MEM_CL0," hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 (CL0)" line.long 0x14 "MEM_CL1," hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 (CL1)" line.long 0x18 "MEM_CL2," hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 (CL2)" line.long 0x1C "MEM_CL3," hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 (CL3)" line.long 0x20 "MEM_I0," hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 (I0)" line.long 0x24 "MEM_I1," hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 (I1)" line.long 0x28 "MEM_I2," hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 (I2)" line.long 0x2C "MEM_I3," hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 (I3)" line.long 0x30 "MEM_RAMT," hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS" hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS" hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR" hexmask.long.byte 0x30 2.--5. 1. "PLS,Pipeline Latency Select" bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3" line.long 0x34 "MEM_DLR," hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 (BRP)" bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1" bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1" bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode (mainly for ROM testing)" "0,1" bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1" newline bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1" bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1" bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1" bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1" bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1" newline bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1" bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1" line.long 0x38 "MEM_CMS," hexmask.long.byte 0x38 0.--3. 1. "CMS,Clock Mux Select (CMS)" line.long 0x3C "MEM_STR," bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1" bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1" bitfld.long 0x3C 2. "STOP,Stop" "0,1" bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1" bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1" rgroup.quad 0x170++0x7 line.quad 0x0 "MEM_SCR," hexmask.quad.byte 0x0 56.--63. 1. "SCR7,Address Scrambling Register 7" hexmask.quad.byte 0x0 48.--55. 1. "SCR6,Address Scrambling Register 6" hexmask.quad.byte 0x0 40.--47. 1. "SCR5,Address Scrambling Register 5" hexmask.quad.byte 0x0 32.--39. 1. "SCR4,Address Scrambling Register 4" hexmask.quad.byte 0x0 24.--31. 1. "SCR3,Address Scrambling Register 3" newline hexmask.quad.byte 0x0 16.--23. 1. "SCR2,Address Scrambling Register 2" hexmask.quad.byte 0x0 8.--15. 1. "SCR1,Address Scrambling Register 1" hexmask.quad.byte 0x0 0.--7. 1. "SCR0,Address Scrambling Register 0" rgroup.long 0x178++0x13 line.long 0x0 "MEM_CSR," hexmask.long.byte 0x0 24.--31. 1. "CSR3,Chip Select 3 (CSR3)" hexmask.long.byte 0x0 16.--23. 1. "CSR2,Chip Select 2 (CSR2)" hexmask.long.byte 0x0 8.--15. 1. "CSR1,Chip Select 1(CSR1)" hexmask.long.byte 0x0 0.--7. 1. "CSR0,Chip Select 0 (CSR0)" line.long 0x4 "MEM_FDLY," hexmask.long.byte 0x4 0.--7. 1. "FDLY,Fail Delay (FDLY)" line.long 0x8 "MEM_PACT," bitfld.long 0x8 0. "PACT,PBIST Activate (PACT)" "0,1" line.long 0xC "MEM_PID," hexmask.long.byte 0xC 0.--4. 1. "PID,PBIST ID" line.long 0x10 "MEM_OVER," bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1" bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1" bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1" bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1" rgroup.quad 0x190++0x17 line.quad 0x0 "MEM_FSRF," bitfld.quad 0x0 32. "FRSF1,Fail Status Fail - Port 1 (FSRF1)" "0,1" bitfld.quad 0x0 0. "FRSF0,Fail Status Fail - Port 0 (FSRF0)" "0,1" line.quad 0x8 "MEM_FSRC," hexmask.quad.byte 0x8 32.--35. 1. "FSRC1,Fail Status Count - Port 1 (FSRC1)" hexmask.quad.byte 0x8 0.--3. 1. "FSRC0,Fail Status Count - Port 0 (FSRC0)" line.quad 0x10 "MEM_FSRA," hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 (FSRA1)" hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 (FSRA0)" rgroup.long 0x1A8++0x3 line.long 0x0 "MEM_FSRDL0," hexmask.long 0x0 0.--31. 1. "FSRDL0,Fail Status Data - Port 0 (FSRDL0)" rgroup.long 0x1B0++0xF line.long 0x0 "MEM_FSRDL1," hexmask.long 0x0 0.--31. 1. "FSRDL1,Fail Status Data - Port 1 (FSRDL1)" line.long 0x4 "MEM_MARGIN_MODE," bitfld.long 0x4 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3" bitfld.long 0x4 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3" line.long 0x8 "MEM_WRENZ," bitfld.long 0x8 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3" line.long 0xC "MEM_PAGE_PGS," bitfld.long 0xC 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3" rgroup.long 0x1C0++0x7 line.long 0x0 "MEM_ROM," bitfld.long 0x0 0.--1. "ROM,ROM Mask (ROM)" "0,1,2,3" line.long 0x4 "MEM_ALGO," hexmask.long.byte 0x4 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 (ALGO 3)" hexmask.long.byte 0x4 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 (ALGO 2)" hexmask.long.byte 0x4 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 (ALGO 1)" hexmask.long.byte 0x4 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 (ALGO 0)" rgroup.quad 0x1C8++0x7 line.quad 0x0 "MEM_RINFO," hexmask.quad.byte 0x0 56.--63. 1. "U3,RAM Info Mask Upper 3 (RINFOU3)" hexmask.quad.byte 0x0 48.--55. 1. "U2,RAM Info Mask Upper 2 (RINFOU2)" hexmask.quad.byte 0x0 40.--47. 1. "U1,RAM Info Mask Upper 1 (RINFOU1)" hexmask.quad.byte 0x0 32.--39. 1. "U0,RAM Info Mask Upper 0 (RINFOU0)" hexmask.quad.byte 0x0 24.--31. 1. "L3,RAM Info Mask Lower 3 (RINFOL3)" newline hexmask.quad.byte 0x0 16.--23. 1. "L2,RAM Info Mask Lower 2 (RINFOL2)" hexmask.quad.byte 0x0 8.--15. 1. "L1,RAM Info Mask Lower 1 (RINFOL1)" hexmask.quad.byte 0x0 0.--7. 1. "L0,RAM Info Mask Lower 0 (RINFOL0)" tree.end tree "PBIST3 (PBIST3)" base ad:0x3370000 rgroup.long 0x0++0x7F line.long 0x0 "MEM_RF0L," hexmask.long 0x0 0.--31. 1. "RF0L,Register Files / Instruction Registers RF0 lower (RF0L)" line.long 0x4 "MEM_RF1L," hexmask.long 0x4 0.--31. 1. "RF1L,Register Files / Instruction Registers RF1 lower (RF1L)" line.long 0x8 "MEM_RF2L," hexmask.long 0x8 0.--31. 1. "RF2L,Register Files / Instruction Registers RF2 lower (RF2L)" line.long 0xC "MEM_RF3L," hexmask.long 0xC 0.--31. 1. "RF3L,Register Files / Instruction Registers RF3 lower (RF3L)" line.long 0x10 "MEM_RF4L," hexmask.long 0x10 0.--31. 1. "RF4L,Register Files / Instruction Registers RF4 lower (RF4L)" line.long 0x14 "MEM_RF5L," hexmask.long 0x14 0.--31. 1. "RF5L,Register Files / Instruction Registers RF5 lower (RF5L)" line.long 0x18 "MEM_RF6L," hexmask.long 0x18 0.--31. 1. "RF6L,Register Files / Instruction Registers RF6 lower (RF6L)" line.long 0x1C "MEM_RF7L," hexmask.long 0x1C 0.--31. 1. "RF7L,Register Files / Instruction Registers RF7 lower (RF7L)" line.long 0x20 "MEM_RF8L," hexmask.long 0x20 0.--31. 1. "RF8L,Register Files / Instruction Registers RF8 lower (RF8L)" line.long 0x24 "MEM_RF9L," hexmask.long 0x24 0.--31. 1. "RF9L,Register Files / Instruction Registers RF9 lower (RF9L)" line.long 0x28 "MEM_RF10L," hexmask.long 0x28 0.--31. 1. "RF10L,Register Files / Instruction Registers RF10 lower (RF10L)" line.long 0x2C "MEM_RF11L," hexmask.long 0x2C 0.--31. 1. "RF11L,Register Files / Instruction Registers RF11 lower (RF11L)" line.long 0x30 "MEM_RF12L," hexmask.long 0x30 0.--31. 1. "RF12L,Register Files / Instruction Registers RF12 lower (RF12L)" line.long 0x34 "MEM_RF13L," hexmask.long 0x34 0.--31. 1. "RF13L,Register Files / Instruction Registers RF13 lower (RF13L)" line.long 0x38 "MEM_RF14L," hexmask.long 0x38 0.--31. 1. "RF14L,Register Files / Instruction Registers RF14 lower (RF14L)" line.long 0x3C "MEM_RF15L," hexmask.long 0x3C 0.--31. 1. "RF15L,Register Files / Instruction Registers RF15 lower (RF15L)" line.long 0x40 "MEM_RF0U," hexmask.long 0x40 0.--31. 1. "RF0U,Register Files / Instruction Registers RF0 upper (RF0U)" line.long 0x44 "MEM_RF1U," hexmask.long 0x44 0.--31. 1. "RF1U,Register Files / Instruction Registers RF1 upper (RF1U)" line.long 0x48 "MEM_RF2U," hexmask.long 0x48 0.--31. 1. "RF2U,Register Files / Instruction Registers RF2 upper (RF2U)" line.long 0x4C "MEM_RF3U," hexmask.long 0x4C 0.--31. 1. "RF3U,Register Files / Instruction Registers RF3 upper (RF3U)" line.long 0x50 "MEM_RF4U," hexmask.long 0x50 0.--31. 1. "RF4U,Register Files / Instruction Registers RF4 upper (RF4U)" line.long 0x54 "MEM_RF5U," hexmask.long 0x54 0.--31. 1. "RF5U,Register Files / Instruction Registers RF5 upper (RF5U)" line.long 0x58 "MEM_RF6U," hexmask.long 0x58 0.--31. 1. "RF6U,Register Files / Instruction Registers RF6 upper (RF6U)" line.long 0x5C "MEM_RF7U," hexmask.long 0x5C 0.--31. 1. "RF7U,Register Files / Instruction Registers RF7 upper (RF7U)" line.long 0x60 "MEM_RF8U," hexmask.long 0x60 0.--31. 1. "RF8U,Register Files / Instruction Registers RF8 upper (RF8U)" line.long 0x64 "MEM_RF9U," hexmask.long 0x64 0.--31. 1. "RF9U,Register Files / Instruction Registers RF9 upper (RF9U)" line.long 0x68 "MEM_RF10U," hexmask.long 0x68 0.--31. 1. "RF10U,Register Files / Instruction Registers RF10 upper (RF10U)" line.long 0x6C "MEM_RF11U," hexmask.long 0x6C 0.--31. 1. "RF11U,Register Files / Instruction Registers RF11 upper (RF11U)" line.long 0x70 "MEM_RF12U," hexmask.long 0x70 0.--31. 1. "RF12U,Register Files / Instruction Registers RF12 upper (RF12U)" line.long 0x74 "MEM_RF13U," hexmask.long 0x74 0.--31. 1. "RF13U,Register Files / Instruction Registers RF13 upper (RF13U)" line.long 0x78 "MEM_RF14U," hexmask.long 0x78 0.--31. 1. "RF14U,Register Files / Instruction Registers RF14 upper (RF14U)" line.long 0x7C "MEM_RF15U," hexmask.long 0x7C 0.--31. 1. "RF15U,Register Files / Instruction Registers RF15 upper (RF15U)" rgroup.long 0x100++0x27 line.long 0x0 "MEM_A0," hexmask.long.word 0x0 0.--15. 1. "A0,Variable Address Register 0 (A0)" line.long 0x4 "MEM_A1," hexmask.long.word 0x4 0.--15. 1. "A1,Variable Address Register 1 (A1)" line.long 0x8 "MEM_A2," hexmask.long.word 0x8 0.--15. 1. "A2,Variable Address Register 2 (A2)" line.long 0xC "MEM_A3," hexmask.long.word 0xC 0.--15. 1. "A3,Variable Address Register 3 (A3)" line.long 0x10 "MEM_L0," hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 (L0)" line.long 0x14 "MEM_L1," hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 (L1)" line.long 0x18 "MEM_L2," hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 (L2)" line.long 0x1C "MEM_L3," hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 (L3)" line.long 0x20 "MEM_D," hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 (D1)" hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 (D0)" line.long 0x24 "MEM_E," hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 (E1)" hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 (E0)" rgroup.long 0x130++0x3F line.long 0x0 "MEM_CA0," hexmask.long.word 0x0 0.--15. 1. "CA0,Constant Address Register 0 (CA0)" line.long 0x4 "MEM_CA1," hexmask.long.word 0x4 0.--15. 1. "CA1,Constant Address Register 1 (CA1)" line.long 0x8 "MEM_CA2," hexmask.long.word 0x8 0.--15. 1. "CA2,Constant Address Register 2 (CA2)" line.long 0xC "MEM_CA3," hexmask.long.word 0xC 0.--15. 1. "CA3,Constant Address Register 3 (CA3)" line.long 0x10 "MEM_CL0," hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 (CL0)" line.long 0x14 "MEM_CL1," hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 (CL1)" line.long 0x18 "MEM_CL2," hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 (CL2)" line.long 0x1C "MEM_CL3," hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 (CL3)" line.long 0x20 "MEM_I0," hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 (I0)" line.long 0x24 "MEM_I1," hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 (I1)" line.long 0x28 "MEM_I2," hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 (I2)" line.long 0x2C "MEM_I3," hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 (I3)" line.long 0x30 "MEM_RAMT," hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS" hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS" hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR" hexmask.long.byte 0x30 2.--5. 1. "PLS,Pipeline Latency Select" bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3" line.long 0x34 "MEM_DLR," hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 (BRP)" bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1" bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1" bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode (mainly for ROM testing)" "0,1" bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1" newline bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1" bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1" bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1" bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1" bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1" newline bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1" bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1" line.long 0x38 "MEM_CMS," hexmask.long.byte 0x38 0.--3. 1. "CMS,Clock Mux Select (CMS)" line.long 0x3C "MEM_STR," bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1" bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1" bitfld.long 0x3C 2. "STOP,Stop" "0,1" bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1" bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1" rgroup.quad 0x170++0x7 line.quad 0x0 "MEM_SCR," hexmask.quad.byte 0x0 56.--63. 1. "SCR7,Address Scrambling Register 7" hexmask.quad.byte 0x0 48.--55. 1. "SCR6,Address Scrambling Register 6" hexmask.quad.byte 0x0 40.--47. 1. "SCR5,Address Scrambling Register 5" hexmask.quad.byte 0x0 32.--39. 1. "SCR4,Address Scrambling Register 4" hexmask.quad.byte 0x0 24.--31. 1. "SCR3,Address Scrambling Register 3" newline hexmask.quad.byte 0x0 16.--23. 1. "SCR2,Address Scrambling Register 2" hexmask.quad.byte 0x0 8.--15. 1. "SCR1,Address Scrambling Register 1" hexmask.quad.byte 0x0 0.--7. 1. "SCR0,Address Scrambling Register 0" rgroup.long 0x178++0x13 line.long 0x0 "MEM_CSR," hexmask.long.byte 0x0 24.--31. 1. "CSR3,Chip Select 3 (CSR3)" hexmask.long.byte 0x0 16.--23. 1. "CSR2,Chip Select 2 (CSR2)" hexmask.long.byte 0x0 8.--15. 1. "CSR1,Chip Select 1(CSR1)" hexmask.long.byte 0x0 0.--7. 1. "CSR0,Chip Select 0 (CSR0)" line.long 0x4 "MEM_FDLY," hexmask.long.byte 0x4 0.--7. 1. "FDLY,Fail Delay (FDLY)" line.long 0x8 "MEM_PACT," bitfld.long 0x8 0. "PACT,PBIST Activate (PACT)" "0,1" line.long 0xC "MEM_PID," hexmask.long.byte 0xC 0.--4. 1. "PID,PBIST ID" line.long 0x10 "MEM_OVER," bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1" bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1" bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1" bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1" rgroup.quad 0x190++0x17 line.quad 0x0 "MEM_FSRF," bitfld.quad 0x0 32. "FRSF1,Fail Status Fail - Port 1 (FSRF1)" "0,1" bitfld.quad 0x0 0. "FRSF0,Fail Status Fail - Port 0 (FSRF0)" "0,1" line.quad 0x8 "MEM_FSRC," hexmask.quad.byte 0x8 32.--35. 1. "FSRC1,Fail Status Count - Port 1 (FSRC1)" hexmask.quad.byte 0x8 0.--3. 1. "FSRC0,Fail Status Count - Port 0 (FSRC0)" line.quad 0x10 "MEM_FSRA," hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 (FSRA1)" hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 (FSRA0)" rgroup.long 0x1A8++0x3 line.long 0x0 "MEM_FSRDL0," hexmask.long 0x0 0.--31. 1. "FSRDL0,Fail Status Data - Port 0 (FSRDL0)" rgroup.long 0x1B0++0xF line.long 0x0 "MEM_FSRDL1," hexmask.long 0x0 0.--31. 1. "FSRDL1,Fail Status Data - Port 1 (FSRDL1)" line.long 0x4 "MEM_MARGIN_MODE," bitfld.long 0x4 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3" bitfld.long 0x4 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3" line.long 0x8 "MEM_WRENZ," bitfld.long 0x8 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3" line.long 0xC "MEM_PAGE_PGS," bitfld.long 0xC 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3" rgroup.long 0x1C0++0x7 line.long 0x0 "MEM_ROM," bitfld.long 0x0 0.--1. "ROM,ROM Mask (ROM)" "0,1,2,3" line.long 0x4 "MEM_ALGO," hexmask.long.byte 0x4 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 (ALGO 3)" hexmask.long.byte 0x4 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 (ALGO 2)" hexmask.long.byte 0x4 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 (ALGO 1)" hexmask.long.byte 0x4 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 (ALGO 0)" rgroup.quad 0x1C8++0x7 line.quad 0x0 "MEM_RINFO," hexmask.quad.byte 0x0 56.--63. 1. "U3,RAM Info Mask Upper 3 (RINFOU3)" hexmask.quad.byte 0x0 48.--55. 1. "U2,RAM Info Mask Upper 2 (RINFOU2)" hexmask.quad.byte 0x0 40.--47. 1. "U1,RAM Info Mask Upper 1 (RINFOU1)" hexmask.quad.byte 0x0 32.--39. 1. "U0,RAM Info Mask Upper 0 (RINFOU0)" hexmask.quad.byte 0x0 24.--31. 1. "L3,RAM Info Mask Lower 3 (RINFOL3)" newline hexmask.quad.byte 0x0 16.--23. 1. "L2,RAM Info Mask Lower 2 (RINFOL2)" hexmask.quad.byte 0x0 8.--15. 1. "L1,RAM Info Mask Lower 1 (RINFOL1)" hexmask.quad.byte 0x0 0.--7. 1. "L0,RAM Info Mask Lower 0 (RINFOL0)" tree.end tree "PBIST4 (PBIST4)" base ad:0xD30000 rgroup.long 0x0++0x7F line.long 0x0 "MEM_RF0L," hexmask.long 0x0 0.--31. 1. "RF0L,Register Files / Instruction Registers RF0 lower (RF0L)" line.long 0x4 "MEM_RF1L," hexmask.long 0x4 0.--31. 1. "RF1L,Register Files / Instruction Registers RF1 lower (RF1L)" line.long 0x8 "MEM_RF2L," hexmask.long 0x8 0.--31. 1. "RF2L,Register Files / Instruction Registers RF2 lower (RF2L)" line.long 0xC "MEM_RF3L," hexmask.long 0xC 0.--31. 1. "RF3L,Register Files / Instruction Registers RF3 lower (RF3L)" line.long 0x10 "MEM_RF4L," hexmask.long 0x10 0.--31. 1. "RF4L,Register Files / Instruction Registers RF4 lower (RF4L)" line.long 0x14 "MEM_RF5L," hexmask.long 0x14 0.--31. 1. "RF5L,Register Files / Instruction Registers RF5 lower (RF5L)" line.long 0x18 "MEM_RF6L," hexmask.long 0x18 0.--31. 1. "RF6L,Register Files / Instruction Registers RF6 lower (RF6L)" line.long 0x1C "MEM_RF7L," hexmask.long 0x1C 0.--31. 1. "RF7L,Register Files / Instruction Registers RF7 lower (RF7L)" line.long 0x20 "MEM_RF8L," hexmask.long 0x20 0.--31. 1. "RF8L,Register Files / Instruction Registers RF8 lower (RF8L)" line.long 0x24 "MEM_RF9L," hexmask.long 0x24 0.--31. 1. "RF9L,Register Files / Instruction Registers RF9 lower (RF9L)" line.long 0x28 "MEM_RF10L," hexmask.long 0x28 0.--31. 1. "RF10L,Register Files / Instruction Registers RF10 lower (RF10L)" line.long 0x2C "MEM_RF11L," hexmask.long 0x2C 0.--31. 1. "RF11L,Register Files / Instruction Registers RF11 lower (RF11L)" line.long 0x30 "MEM_RF12L," hexmask.long 0x30 0.--31. 1. "RF12L,Register Files / Instruction Registers RF12 lower (RF12L)" line.long 0x34 "MEM_RF13L," hexmask.long 0x34 0.--31. 1. "RF13L,Register Files / Instruction Registers RF13 lower (RF13L)" line.long 0x38 "MEM_RF14L," hexmask.long 0x38 0.--31. 1. "RF14L,Register Files / Instruction Registers RF14 lower (RF14L)" line.long 0x3C "MEM_RF15L," hexmask.long 0x3C 0.--31. 1. "RF15L,Register Files / Instruction Registers RF15 lower (RF15L)" line.long 0x40 "MEM_RF0U," hexmask.long 0x40 0.--31. 1. "RF0U,Register Files / Instruction Registers RF0 upper (RF0U)" line.long 0x44 "MEM_RF1U," hexmask.long 0x44 0.--31. 1. "RF1U,Register Files / Instruction Registers RF1 upper (RF1U)" line.long 0x48 "MEM_RF2U," hexmask.long 0x48 0.--31. 1. "RF2U,Register Files / Instruction Registers RF2 upper (RF2U)" line.long 0x4C "MEM_RF3U," hexmask.long 0x4C 0.--31. 1. "RF3U,Register Files / Instruction Registers RF3 upper (RF3U)" line.long 0x50 "MEM_RF4U," hexmask.long 0x50 0.--31. 1. "RF4U,Register Files / Instruction Registers RF4 upper (RF4U)" line.long 0x54 "MEM_RF5U," hexmask.long 0x54 0.--31. 1. "RF5U,Register Files / Instruction Registers RF5 upper (RF5U)" line.long 0x58 "MEM_RF6U," hexmask.long 0x58 0.--31. 1. "RF6U,Register Files / Instruction Registers RF6 upper (RF6U)" line.long 0x5C "MEM_RF7U," hexmask.long 0x5C 0.--31. 1. "RF7U,Register Files / Instruction Registers RF7 upper (RF7U)" line.long 0x60 "MEM_RF8U," hexmask.long 0x60 0.--31. 1. "RF8U,Register Files / Instruction Registers RF8 upper (RF8U)" line.long 0x64 "MEM_RF9U," hexmask.long 0x64 0.--31. 1. "RF9U,Register Files / Instruction Registers RF9 upper (RF9U)" line.long 0x68 "MEM_RF10U," hexmask.long 0x68 0.--31. 1. "RF10U,Register Files / Instruction Registers RF10 upper (RF10U)" line.long 0x6C "MEM_RF11U," hexmask.long 0x6C 0.--31. 1. "RF11U,Register Files / Instruction Registers RF11 upper (RF11U)" line.long 0x70 "MEM_RF12U," hexmask.long 0x70 0.--31. 1. "RF12U,Register Files / Instruction Registers RF12 upper (RF12U)" line.long 0x74 "MEM_RF13U," hexmask.long 0x74 0.--31. 1. "RF13U,Register Files / Instruction Registers RF13 upper (RF13U)" line.long 0x78 "MEM_RF14U," hexmask.long 0x78 0.--31. 1. "RF14U,Register Files / Instruction Registers RF14 upper (RF14U)" line.long 0x7C "MEM_RF15U," hexmask.long 0x7C 0.--31. 1. "RF15U,Register Files / Instruction Registers RF15 upper (RF15U)" rgroup.long 0x100++0x27 line.long 0x0 "MEM_A0," hexmask.long.word 0x0 0.--15. 1. "A0,Variable Address Register 0 (A0)" line.long 0x4 "MEM_A1," hexmask.long.word 0x4 0.--15. 1. "A1,Variable Address Register 1 (A1)" line.long 0x8 "MEM_A2," hexmask.long.word 0x8 0.--15. 1. "A2,Variable Address Register 2 (A2)" line.long 0xC "MEM_A3," hexmask.long.word 0xC 0.--15. 1. "A3,Variable Address Register 3 (A3)" line.long 0x10 "MEM_L0," hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 (L0)" line.long 0x14 "MEM_L1," hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 (L1)" line.long 0x18 "MEM_L2," hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 (L2)" line.long 0x1C "MEM_L3," hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 (L3)" line.long 0x20 "MEM_D," hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 (D1)" hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 (D0)" line.long 0x24 "MEM_E," hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 (E1)" hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 (E0)" rgroup.long 0x130++0x3F line.long 0x0 "MEM_CA0," hexmask.long.word 0x0 0.--15. 1. "CA0,Constant Address Register 0 (CA0)" line.long 0x4 "MEM_CA1," hexmask.long.word 0x4 0.--15. 1. "CA1,Constant Address Register 1 (CA1)" line.long 0x8 "MEM_CA2," hexmask.long.word 0x8 0.--15. 1. "CA2,Constant Address Register 2 (CA2)" line.long 0xC "MEM_CA3," hexmask.long.word 0xC 0.--15. 1. "CA3,Constant Address Register 3 (CA3)" line.long 0x10 "MEM_CL0," hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 (CL0)" line.long 0x14 "MEM_CL1," hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 (CL1)" line.long 0x18 "MEM_CL2," hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 (CL2)" line.long 0x1C "MEM_CL3," hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 (CL3)" line.long 0x20 "MEM_I0," hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 (I0)" line.long 0x24 "MEM_I1," hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 (I1)" line.long 0x28 "MEM_I2," hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 (I2)" line.long 0x2C "MEM_I3," hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 (I3)" line.long 0x30 "MEM_RAMT," hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS" hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS" hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR" hexmask.long.byte 0x30 2.--5. 1. "PLS,Pipeline Latency Select" bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3" line.long 0x34 "MEM_DLR," hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 (BRP)" bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1" bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1" bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode (mainly for ROM testing)" "0,1" bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1" newline bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1" bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1" bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1" bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1" bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1" newline bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1" bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1" line.long 0x38 "MEM_CMS," hexmask.long.byte 0x38 0.--3. 1. "CMS,Clock Mux Select (CMS)" line.long 0x3C "MEM_STR," bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1" bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1" bitfld.long 0x3C 2. "STOP,Stop" "0,1" bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1" bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1" rgroup.quad 0x170++0x7 line.quad 0x0 "MEM_SCR," hexmask.quad.byte 0x0 56.--63. 1. "SCR7,Address Scrambling Register 7" hexmask.quad.byte 0x0 48.--55. 1. "SCR6,Address Scrambling Register 6" hexmask.quad.byte 0x0 40.--47. 1. "SCR5,Address Scrambling Register 5" hexmask.quad.byte 0x0 32.--39. 1. "SCR4,Address Scrambling Register 4" hexmask.quad.byte 0x0 24.--31. 1. "SCR3,Address Scrambling Register 3" newline hexmask.quad.byte 0x0 16.--23. 1. "SCR2,Address Scrambling Register 2" hexmask.quad.byte 0x0 8.--15. 1. "SCR1,Address Scrambling Register 1" hexmask.quad.byte 0x0 0.--7. 1. "SCR0,Address Scrambling Register 0" rgroup.long 0x178++0x13 line.long 0x0 "MEM_CSR," hexmask.long.byte 0x0 24.--31. 1. "CSR3,Chip Select 3 (CSR3)" hexmask.long.byte 0x0 16.--23. 1. "CSR2,Chip Select 2 (CSR2)" hexmask.long.byte 0x0 8.--15. 1. "CSR1,Chip Select 1(CSR1)" hexmask.long.byte 0x0 0.--7. 1. "CSR0,Chip Select 0 (CSR0)" line.long 0x4 "MEM_FDLY," hexmask.long.byte 0x4 0.--7. 1. "FDLY,Fail Delay (FDLY)" line.long 0x8 "MEM_PACT," bitfld.long 0x8 0. "PACT,PBIST Activate (PACT)" "0,1" line.long 0xC "MEM_PID," hexmask.long.byte 0xC 0.--4. 1. "PID,PBIST ID" line.long 0x10 "MEM_OVER," bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1" bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1" bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1" bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1" rgroup.quad 0x190++0x17 line.quad 0x0 "MEM_FSRF," bitfld.quad 0x0 32. "FRSF1,Fail Status Fail - Port 1 (FSRF1)" "0,1" bitfld.quad 0x0 0. "FRSF0,Fail Status Fail - Port 0 (FSRF0)" "0,1" line.quad 0x8 "MEM_FSRC," hexmask.quad.byte 0x8 32.--35. 1. "FSRC1,Fail Status Count - Port 1 (FSRC1)" hexmask.quad.byte 0x8 0.--3. 1. "FSRC0,Fail Status Count - Port 0 (FSRC0)" line.quad 0x10 "MEM_FSRA," hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 (FSRA1)" hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 (FSRA0)" rgroup.long 0x1A8++0x3 line.long 0x0 "MEM_FSRDL0," hexmask.long 0x0 0.--31. 1. "FSRDL0,Fail Status Data - Port 0 (FSRDL0)" rgroup.long 0x1B0++0xF line.long 0x0 "MEM_FSRDL1," hexmask.long 0x0 0.--31. 1. "FSRDL1,Fail Status Data - Port 1 (FSRDL1)" line.long 0x4 "MEM_MARGIN_MODE," bitfld.long 0x4 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3" bitfld.long 0x4 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3" line.long 0x8 "MEM_WRENZ," bitfld.long 0x8 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3" line.long 0xC "MEM_PAGE_PGS," bitfld.long 0xC 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3" rgroup.long 0x1C0++0x7 line.long 0x0 "MEM_ROM," bitfld.long 0x0 0.--1. "ROM,ROM Mask (ROM)" "0,1,2,3" line.long 0x4 "MEM_ALGO," hexmask.long.byte 0x4 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 (ALGO 3)" hexmask.long.byte 0x4 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 (ALGO 2)" hexmask.long.byte 0x4 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 (ALGO 1)" hexmask.long.byte 0x4 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 (ALGO 0)" rgroup.quad 0x1C8++0x7 line.quad 0x0 "MEM_RINFO," hexmask.quad.byte 0x0 56.--63. 1. "U3,RAM Info Mask Upper 3 (RINFOU3)" hexmask.quad.byte 0x0 48.--55. 1. "U2,RAM Info Mask Upper 2 (RINFOU2)" hexmask.quad.byte 0x0 40.--47. 1. "U1,RAM Info Mask Upper 1 (RINFOU1)" hexmask.quad.byte 0x0 32.--39. 1. "U0,RAM Info Mask Upper 0 (RINFOU0)" hexmask.quad.byte 0x0 24.--31. 1. "L3,RAM Info Mask Lower 3 (RINFOL3)" newline hexmask.quad.byte 0x0 16.--23. 1. "L2,RAM Info Mask Lower 2 (RINFOL2)" hexmask.quad.byte 0x0 8.--15. 1. "L1,RAM Info Mask Lower 1 (RINFOL1)" hexmask.quad.byte 0x0 0.--7. 1. "L0,RAM Info Mask Lower 0 (RINFOL0)" tree.end tree "PBIST5 (PBIST5)" base ad:0x3340000 rgroup.long 0x0++0x7F line.long 0x0 "MEM_RF0L," hexmask.long 0x0 0.--31. 1. "RF0L,Register Files / Instruction Registers RF0 lower (RF0L)" line.long 0x4 "MEM_RF1L," hexmask.long 0x4 0.--31. 1. "RF1L,Register Files / Instruction Registers RF1 lower (RF1L)" line.long 0x8 "MEM_RF2L," hexmask.long 0x8 0.--31. 1. "RF2L,Register Files / Instruction Registers RF2 lower (RF2L)" line.long 0xC "MEM_RF3L," hexmask.long 0xC 0.--31. 1. "RF3L,Register Files / Instruction Registers RF3 lower (RF3L)" line.long 0x10 "MEM_RF4L," hexmask.long 0x10 0.--31. 1. "RF4L,Register Files / Instruction Registers RF4 lower (RF4L)" line.long 0x14 "MEM_RF5L," hexmask.long 0x14 0.--31. 1. "RF5L,Register Files / Instruction Registers RF5 lower (RF5L)" line.long 0x18 "MEM_RF6L," hexmask.long 0x18 0.--31. 1. "RF6L,Register Files / Instruction Registers RF6 lower (RF6L)" line.long 0x1C "MEM_RF7L," hexmask.long 0x1C 0.--31. 1. "RF7L,Register Files / Instruction Registers RF7 lower (RF7L)" line.long 0x20 "MEM_RF8L," hexmask.long 0x20 0.--31. 1. "RF8L,Register Files / Instruction Registers RF8 lower (RF8L)" line.long 0x24 "MEM_RF9L," hexmask.long 0x24 0.--31. 1. "RF9L,Register Files / Instruction Registers RF9 lower (RF9L)" line.long 0x28 "MEM_RF10L," hexmask.long 0x28 0.--31. 1. "RF10L,Register Files / Instruction Registers RF10 lower (RF10L)" line.long 0x2C "MEM_RF11L," hexmask.long 0x2C 0.--31. 1. "RF11L,Register Files / Instruction Registers RF11 lower (RF11L)" line.long 0x30 "MEM_RF12L," hexmask.long 0x30 0.--31. 1. "RF12L,Register Files / Instruction Registers RF12 lower (RF12L)" line.long 0x34 "MEM_RF13L," hexmask.long 0x34 0.--31. 1. "RF13L,Register Files / Instruction Registers RF13 lower (RF13L)" line.long 0x38 "MEM_RF14L," hexmask.long 0x38 0.--31. 1. "RF14L,Register Files / Instruction Registers RF14 lower (RF14L)" line.long 0x3C "MEM_RF15L," hexmask.long 0x3C 0.--31. 1. "RF15L,Register Files / Instruction Registers RF15 lower (RF15L)" line.long 0x40 "MEM_RF0U," hexmask.long 0x40 0.--31. 1. "RF0U,Register Files / Instruction Registers RF0 upper (RF0U)" line.long 0x44 "MEM_RF1U," hexmask.long 0x44 0.--31. 1. "RF1U,Register Files / Instruction Registers RF1 upper (RF1U)" line.long 0x48 "MEM_RF2U," hexmask.long 0x48 0.--31. 1. "RF2U,Register Files / Instruction Registers RF2 upper (RF2U)" line.long 0x4C "MEM_RF3U," hexmask.long 0x4C 0.--31. 1. "RF3U,Register Files / Instruction Registers RF3 upper (RF3U)" line.long 0x50 "MEM_RF4U," hexmask.long 0x50 0.--31. 1. "RF4U,Register Files / Instruction Registers RF4 upper (RF4U)" line.long 0x54 "MEM_RF5U," hexmask.long 0x54 0.--31. 1. "RF5U,Register Files / Instruction Registers RF5 upper (RF5U)" line.long 0x58 "MEM_RF6U," hexmask.long 0x58 0.--31. 1. "RF6U,Register Files / Instruction Registers RF6 upper (RF6U)" line.long 0x5C "MEM_RF7U," hexmask.long 0x5C 0.--31. 1. "RF7U,Register Files / Instruction Registers RF7 upper (RF7U)" line.long 0x60 "MEM_RF8U," hexmask.long 0x60 0.--31. 1. "RF8U,Register Files / Instruction Registers RF8 upper (RF8U)" line.long 0x64 "MEM_RF9U," hexmask.long 0x64 0.--31. 1. "RF9U,Register Files / Instruction Registers RF9 upper (RF9U)" line.long 0x68 "MEM_RF10U," hexmask.long 0x68 0.--31. 1. "RF10U,Register Files / Instruction Registers RF10 upper (RF10U)" line.long 0x6C "MEM_RF11U," hexmask.long 0x6C 0.--31. 1. "RF11U,Register Files / Instruction Registers RF11 upper (RF11U)" line.long 0x70 "MEM_RF12U," hexmask.long 0x70 0.--31. 1. "RF12U,Register Files / Instruction Registers RF12 upper (RF12U)" line.long 0x74 "MEM_RF13U," hexmask.long 0x74 0.--31. 1. "RF13U,Register Files / Instruction Registers RF13 upper (RF13U)" line.long 0x78 "MEM_RF14U," hexmask.long 0x78 0.--31. 1. "RF14U,Register Files / Instruction Registers RF14 upper (RF14U)" line.long 0x7C "MEM_RF15U," hexmask.long 0x7C 0.--31. 1. "RF15U,Register Files / Instruction Registers RF15 upper (RF15U)" rgroup.long 0x100++0x27 line.long 0x0 "MEM_A0," hexmask.long.word 0x0 0.--15. 1. "A0,Variable Address Register 0 (A0)" line.long 0x4 "MEM_A1," hexmask.long.word 0x4 0.--15. 1. "A1,Variable Address Register 1 (A1)" line.long 0x8 "MEM_A2," hexmask.long.word 0x8 0.--15. 1. "A2,Variable Address Register 2 (A2)" line.long 0xC "MEM_A3," hexmask.long.word 0xC 0.--15. 1. "A3,Variable Address Register 3 (A3)" line.long 0x10 "MEM_L0," hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 (L0)" line.long 0x14 "MEM_L1," hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 (L1)" line.long 0x18 "MEM_L2," hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 (L2)" line.long 0x1C "MEM_L3," hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 (L3)" line.long 0x20 "MEM_D," hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 (D1)" hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 (D0)" line.long 0x24 "MEM_E," hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 (E1)" hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 (E0)" rgroup.long 0x130++0x3F line.long 0x0 "MEM_CA0," hexmask.long.word 0x0 0.--15. 1. "CA0,Constant Address Register 0 (CA0)" line.long 0x4 "MEM_CA1," hexmask.long.word 0x4 0.--15. 1. "CA1,Constant Address Register 1 (CA1)" line.long 0x8 "MEM_CA2," hexmask.long.word 0x8 0.--15. 1. "CA2,Constant Address Register 2 (CA2)" line.long 0xC "MEM_CA3," hexmask.long.word 0xC 0.--15. 1. "CA3,Constant Address Register 3 (CA3)" line.long 0x10 "MEM_CL0," hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 (CL0)" line.long 0x14 "MEM_CL1," hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 (CL1)" line.long 0x18 "MEM_CL2," hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 (CL2)" line.long 0x1C "MEM_CL3," hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 (CL3)" line.long 0x20 "MEM_I0," hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 (I0)" line.long 0x24 "MEM_I1," hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 (I1)" line.long 0x28 "MEM_I2," hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 (I2)" line.long 0x2C "MEM_I3," hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 (I3)" line.long 0x30 "MEM_RAMT," hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS" hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS" hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR" hexmask.long.byte 0x30 2.--5. 1. "PLS,Pipeline Latency Select" bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3" line.long 0x34 "MEM_DLR," hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 (BRP)" bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1" bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1" bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode (mainly for ROM testing)" "0,1" bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1" newline bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1" bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1" bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1" bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1" bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1" newline bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1" bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1" line.long 0x38 "MEM_CMS," hexmask.long.byte 0x38 0.--3. 1. "CMS,Clock Mux Select (CMS)" line.long 0x3C "MEM_STR," bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1" bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1" bitfld.long 0x3C 2. "STOP,Stop" "0,1" bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1" bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1" rgroup.quad 0x170++0x7 line.quad 0x0 "MEM_SCR," hexmask.quad.byte 0x0 56.--63. 1. "SCR7,Address Scrambling Register 7" hexmask.quad.byte 0x0 48.--55. 1. "SCR6,Address Scrambling Register 6" hexmask.quad.byte 0x0 40.--47. 1. "SCR5,Address Scrambling Register 5" hexmask.quad.byte 0x0 32.--39. 1. "SCR4,Address Scrambling Register 4" hexmask.quad.byte 0x0 24.--31. 1. "SCR3,Address Scrambling Register 3" newline hexmask.quad.byte 0x0 16.--23. 1. "SCR2,Address Scrambling Register 2" hexmask.quad.byte 0x0 8.--15. 1. "SCR1,Address Scrambling Register 1" hexmask.quad.byte 0x0 0.--7. 1. "SCR0,Address Scrambling Register 0" rgroup.long 0x178++0x13 line.long 0x0 "MEM_CSR," hexmask.long.byte 0x0 24.--31. 1. "CSR3,Chip Select 3 (CSR3)" hexmask.long.byte 0x0 16.--23. 1. "CSR2,Chip Select 2 (CSR2)" hexmask.long.byte 0x0 8.--15. 1. "CSR1,Chip Select 1(CSR1)" hexmask.long.byte 0x0 0.--7. 1. "CSR0,Chip Select 0 (CSR0)" line.long 0x4 "MEM_FDLY," hexmask.long.byte 0x4 0.--7. 1. "FDLY,Fail Delay (FDLY)" line.long 0x8 "MEM_PACT," bitfld.long 0x8 0. "PACT,PBIST Activate (PACT)" "0,1" line.long 0xC "MEM_PID," hexmask.long.byte 0xC 0.--4. 1. "PID,PBIST ID" line.long 0x10 "MEM_OVER," bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1" bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1" bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1" bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1" rgroup.quad 0x190++0x17 line.quad 0x0 "MEM_FSRF," bitfld.quad 0x0 32. "FRSF1,Fail Status Fail - Port 1 (FSRF1)" "0,1" bitfld.quad 0x0 0. "FRSF0,Fail Status Fail - Port 0 (FSRF0)" "0,1" line.quad 0x8 "MEM_FSRC," hexmask.quad.byte 0x8 32.--35. 1. "FSRC1,Fail Status Count - Port 1 (FSRC1)" hexmask.quad.byte 0x8 0.--3. 1. "FSRC0,Fail Status Count - Port 0 (FSRC0)" line.quad 0x10 "MEM_FSRA," hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 (FSRA1)" hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 (FSRA0)" rgroup.long 0x1A8++0x3 line.long 0x0 "MEM_FSRDL0," hexmask.long 0x0 0.--31. 1. "FSRDL0,Fail Status Data - Port 0 (FSRDL0)" rgroup.long 0x1B0++0xF line.long 0x0 "MEM_FSRDL1," hexmask.long 0x0 0.--31. 1. "FSRDL1,Fail Status Data - Port 1 (FSRDL1)" line.long 0x4 "MEM_MARGIN_MODE," bitfld.long 0x4 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3" bitfld.long 0x4 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3" line.long 0x8 "MEM_WRENZ," bitfld.long 0x8 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3" line.long 0xC "MEM_PAGE_PGS," bitfld.long 0xC 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3" rgroup.long 0x1C0++0x7 line.long 0x0 "MEM_ROM," bitfld.long 0x0 0.--1. "ROM,ROM Mask (ROM)" "0,1,2,3" line.long 0x4 "MEM_ALGO," hexmask.long.byte 0x4 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 (ALGO 3)" hexmask.long.byte 0x4 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 (ALGO 2)" hexmask.long.byte 0x4 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 (ALGO 1)" hexmask.long.byte 0x4 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 (ALGO 0)" rgroup.quad 0x1C8++0x7 line.quad 0x0 "MEM_RINFO," hexmask.quad.byte 0x0 56.--63. 1. "U3,RAM Info Mask Upper 3 (RINFOU3)" hexmask.quad.byte 0x0 48.--55. 1. "U2,RAM Info Mask Upper 2 (RINFOU2)" hexmask.quad.byte 0x0 40.--47. 1. "U1,RAM Info Mask Upper 1 (RINFOU1)" hexmask.quad.byte 0x0 32.--39. 1. "U0,RAM Info Mask Upper 0 (RINFOU0)" hexmask.quad.byte 0x0 24.--31. 1. "L3,RAM Info Mask Lower 3 (RINFOL3)" newline hexmask.quad.byte 0x0 16.--23. 1. "L2,RAM Info Mask Lower 2 (RINFOL2)" hexmask.quad.byte 0x0 8.--15. 1. "L1,RAM Info Mask Lower 1 (RINFOL1)" hexmask.quad.byte 0x0 0.--7. 1. "L0,RAM Info Mask Lower 0 (RINFOL0)" tree.end tree "PBIST7 (PBIST7)" base ad:0x3300000 rgroup.long 0x0++0x7F line.long 0x0 "MEM_RF0L," hexmask.long 0x0 0.--31. 1. "RF0L,Register Files / Instruction Registers RF0 lower (RF0L)" line.long 0x4 "MEM_RF1L," hexmask.long 0x4 0.--31. 1. "RF1L,Register Files / Instruction Registers RF1 lower (RF1L)" line.long 0x8 "MEM_RF2L," hexmask.long 0x8 0.--31. 1. "RF2L,Register Files / Instruction Registers RF2 lower (RF2L)" line.long 0xC "MEM_RF3L," hexmask.long 0xC 0.--31. 1. "RF3L,Register Files / Instruction Registers RF3 lower (RF3L)" line.long 0x10 "MEM_RF4L," hexmask.long 0x10 0.--31. 1. "RF4L,Register Files / Instruction Registers RF4 lower (RF4L)" line.long 0x14 "MEM_RF5L," hexmask.long 0x14 0.--31. 1. "RF5L,Register Files / Instruction Registers RF5 lower (RF5L)" line.long 0x18 "MEM_RF6L," hexmask.long 0x18 0.--31. 1. "RF6L,Register Files / Instruction Registers RF6 lower (RF6L)" line.long 0x1C "MEM_RF7L," hexmask.long 0x1C 0.--31. 1. "RF7L,Register Files / Instruction Registers RF7 lower (RF7L)" line.long 0x20 "MEM_RF8L," hexmask.long 0x20 0.--31. 1. "RF8L,Register Files / Instruction Registers RF8 lower (RF8L)" line.long 0x24 "MEM_RF9L," hexmask.long 0x24 0.--31. 1. "RF9L,Register Files / Instruction Registers RF9 lower (RF9L)" line.long 0x28 "MEM_RF10L," hexmask.long 0x28 0.--31. 1. "RF10L,Register Files / Instruction Registers RF10 lower (RF10L)" line.long 0x2C "MEM_RF11L," hexmask.long 0x2C 0.--31. 1. "RF11L,Register Files / Instruction Registers RF11 lower (RF11L)" line.long 0x30 "MEM_RF12L," hexmask.long 0x30 0.--31. 1. "RF12L,Register Files / Instruction Registers RF12 lower (RF12L)" line.long 0x34 "MEM_RF13L," hexmask.long 0x34 0.--31. 1. "RF13L,Register Files / Instruction Registers RF13 lower (RF13L)" line.long 0x38 "MEM_RF14L," hexmask.long 0x38 0.--31. 1. "RF14L,Register Files / Instruction Registers RF14 lower (RF14L)" line.long 0x3C "MEM_RF15L," hexmask.long 0x3C 0.--31. 1. "RF15L,Register Files / Instruction Registers RF15 lower (RF15L)" line.long 0x40 "MEM_RF0U," hexmask.long 0x40 0.--31. 1. "RF0U,Register Files / Instruction Registers RF0 upper (RF0U)" line.long 0x44 "MEM_RF1U," hexmask.long 0x44 0.--31. 1. "RF1U,Register Files / Instruction Registers RF1 upper (RF1U)" line.long 0x48 "MEM_RF2U," hexmask.long 0x48 0.--31. 1. "RF2U,Register Files / Instruction Registers RF2 upper (RF2U)" line.long 0x4C "MEM_RF3U," hexmask.long 0x4C 0.--31. 1. "RF3U,Register Files / Instruction Registers RF3 upper (RF3U)" line.long 0x50 "MEM_RF4U," hexmask.long 0x50 0.--31. 1. "RF4U,Register Files / Instruction Registers RF4 upper (RF4U)" line.long 0x54 "MEM_RF5U," hexmask.long 0x54 0.--31. 1. "RF5U,Register Files / Instruction Registers RF5 upper (RF5U)" line.long 0x58 "MEM_RF6U," hexmask.long 0x58 0.--31. 1. "RF6U,Register Files / Instruction Registers RF6 upper (RF6U)" line.long 0x5C "MEM_RF7U," hexmask.long 0x5C 0.--31. 1. "RF7U,Register Files / Instruction Registers RF7 upper (RF7U)" line.long 0x60 "MEM_RF8U," hexmask.long 0x60 0.--31. 1. "RF8U,Register Files / Instruction Registers RF8 upper (RF8U)" line.long 0x64 "MEM_RF9U," hexmask.long 0x64 0.--31. 1. "RF9U,Register Files / Instruction Registers RF9 upper (RF9U)" line.long 0x68 "MEM_RF10U," hexmask.long 0x68 0.--31. 1. "RF10U,Register Files / Instruction Registers RF10 upper (RF10U)" line.long 0x6C "MEM_RF11U," hexmask.long 0x6C 0.--31. 1. "RF11U,Register Files / Instruction Registers RF11 upper (RF11U)" line.long 0x70 "MEM_RF12U," hexmask.long 0x70 0.--31. 1. "RF12U,Register Files / Instruction Registers RF12 upper (RF12U)" line.long 0x74 "MEM_RF13U," hexmask.long 0x74 0.--31. 1. "RF13U,Register Files / Instruction Registers RF13 upper (RF13U)" line.long 0x78 "MEM_RF14U," hexmask.long 0x78 0.--31. 1. "RF14U,Register Files / Instruction Registers RF14 upper (RF14U)" line.long 0x7C "MEM_RF15U," hexmask.long 0x7C 0.--31. 1. "RF15U,Register Files / Instruction Registers RF15 upper (RF15U)" rgroup.long 0x100++0x27 line.long 0x0 "MEM_A0," hexmask.long.word 0x0 0.--15. 1. "A0,Variable Address Register 0 (A0)" line.long 0x4 "MEM_A1," hexmask.long.word 0x4 0.--15. 1. "A1,Variable Address Register 1 (A1)" line.long 0x8 "MEM_A2," hexmask.long.word 0x8 0.--15. 1. "A2,Variable Address Register 2 (A2)" line.long 0xC "MEM_A3," hexmask.long.word 0xC 0.--15. 1. "A3,Variable Address Register 3 (A3)" line.long 0x10 "MEM_L0," hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 (L0)" line.long 0x14 "MEM_L1," hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 (L1)" line.long 0x18 "MEM_L2," hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 (L2)" line.long 0x1C "MEM_L3," hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 (L3)" line.long 0x20 "MEM_D," hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 (D1)" hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 (D0)" line.long 0x24 "MEM_E," hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 (E1)" hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 (E0)" rgroup.long 0x130++0x3F line.long 0x0 "MEM_CA0," hexmask.long.word 0x0 0.--15. 1. "CA0,Constant Address Register 0 (CA0)" line.long 0x4 "MEM_CA1," hexmask.long.word 0x4 0.--15. 1. "CA1,Constant Address Register 1 (CA1)" line.long 0x8 "MEM_CA2," hexmask.long.word 0x8 0.--15. 1. "CA2,Constant Address Register 2 (CA2)" line.long 0xC "MEM_CA3," hexmask.long.word 0xC 0.--15. 1. "CA3,Constant Address Register 3 (CA3)" line.long 0x10 "MEM_CL0," hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 (CL0)" line.long 0x14 "MEM_CL1," hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 (CL1)" line.long 0x18 "MEM_CL2," hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 (CL2)" line.long 0x1C "MEM_CL3," hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 (CL3)" line.long 0x20 "MEM_I0," hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 (I0)" line.long 0x24 "MEM_I1," hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 (I1)" line.long 0x28 "MEM_I2," hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 (I2)" line.long 0x2C "MEM_I3," hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 (I3)" line.long 0x30 "MEM_RAMT," hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS" hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS" hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR" hexmask.long.byte 0x30 2.--5. 1. "PLS,Pipeline Latency Select" bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3" line.long 0x34 "MEM_DLR," hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 (BRP)" bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1" bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1" bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode (mainly for ROM testing)" "0,1" bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1" newline bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1" bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1" bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1" bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1" bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1" newline bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1" bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1" line.long 0x38 "MEM_CMS," hexmask.long.byte 0x38 0.--3. 1. "CMS,Clock Mux Select (CMS)" line.long 0x3C "MEM_STR," bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1" bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1" bitfld.long 0x3C 2. "STOP,Stop" "0,1" bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1" bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1" rgroup.quad 0x170++0x7 line.quad 0x0 "MEM_SCR," hexmask.quad.byte 0x0 56.--63. 1. "SCR7,Address Scrambling Register 7" hexmask.quad.byte 0x0 48.--55. 1. "SCR6,Address Scrambling Register 6" hexmask.quad.byte 0x0 40.--47. 1. "SCR5,Address Scrambling Register 5" hexmask.quad.byte 0x0 32.--39. 1. "SCR4,Address Scrambling Register 4" hexmask.quad.byte 0x0 24.--31. 1. "SCR3,Address Scrambling Register 3" newline hexmask.quad.byte 0x0 16.--23. 1. "SCR2,Address Scrambling Register 2" hexmask.quad.byte 0x0 8.--15. 1. "SCR1,Address Scrambling Register 1" hexmask.quad.byte 0x0 0.--7. 1. "SCR0,Address Scrambling Register 0" rgroup.long 0x178++0x13 line.long 0x0 "MEM_CSR," hexmask.long.byte 0x0 24.--31. 1. "CSR3,Chip Select 3 (CSR3)" hexmask.long.byte 0x0 16.--23. 1. "CSR2,Chip Select 2 (CSR2)" hexmask.long.byte 0x0 8.--15. 1. "CSR1,Chip Select 1(CSR1)" hexmask.long.byte 0x0 0.--7. 1. "CSR0,Chip Select 0 (CSR0)" line.long 0x4 "MEM_FDLY," hexmask.long.byte 0x4 0.--7. 1. "FDLY,Fail Delay (FDLY)" line.long 0x8 "MEM_PACT," bitfld.long 0x8 0. "PACT,PBIST Activate (PACT)" "0,1" line.long 0xC "MEM_PID," hexmask.long.byte 0xC 0.--4. 1. "PID,PBIST ID" line.long 0x10 "MEM_OVER," bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1" bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1" bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1" bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1" rgroup.quad 0x190++0x17 line.quad 0x0 "MEM_FSRF," bitfld.quad 0x0 32. "FRSF1,Fail Status Fail - Port 1 (FSRF1)" "0,1" bitfld.quad 0x0 0. "FRSF0,Fail Status Fail - Port 0 (FSRF0)" "0,1" line.quad 0x8 "MEM_FSRC," hexmask.quad.byte 0x8 32.--35. 1. "FSRC1,Fail Status Count - Port 1 (FSRC1)" hexmask.quad.byte 0x8 0.--3. 1. "FSRC0,Fail Status Count - Port 0 (FSRC0)" line.quad 0x10 "MEM_FSRA," hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 (FSRA1)" hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 (FSRA0)" rgroup.long 0x1A8++0x3 line.long 0x0 "MEM_FSRDL0," hexmask.long 0x0 0.--31. 1. "FSRDL0,Fail Status Data - Port 0 (FSRDL0)" rgroup.long 0x1B0++0xF line.long 0x0 "MEM_FSRDL1," hexmask.long 0x0 0.--31. 1. "FSRDL1,Fail Status Data - Port 1 (FSRDL1)" line.long 0x4 "MEM_MARGIN_MODE," bitfld.long 0x4 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3" bitfld.long 0x4 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3" line.long 0x8 "MEM_WRENZ," bitfld.long 0x8 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3" line.long 0xC "MEM_PAGE_PGS," bitfld.long 0xC 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3" rgroup.long 0x1C0++0x7 line.long 0x0 "MEM_ROM," bitfld.long 0x0 0.--1. "ROM,ROM Mask (ROM)" "0,1,2,3" line.long 0x4 "MEM_ALGO," hexmask.long.byte 0x4 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 (ALGO 3)" hexmask.long.byte 0x4 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 (ALGO 2)" hexmask.long.byte 0x4 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 (ALGO 1)" hexmask.long.byte 0x4 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 (ALGO 0)" rgroup.quad 0x1C8++0x7 line.quad 0x0 "MEM_RINFO," hexmask.quad.byte 0x0 56.--63. 1. "U3,RAM Info Mask Upper 3 (RINFOU3)" hexmask.quad.byte 0x0 48.--55. 1. "U2,RAM Info Mask Upper 2 (RINFOU2)" hexmask.quad.byte 0x0 40.--47. 1. "U1,RAM Info Mask Upper 1 (RINFOU1)" hexmask.quad.byte 0x0 32.--39. 1. "U0,RAM Info Mask Upper 0 (RINFOU0)" hexmask.quad.byte 0x0 24.--31. 1. "L3,RAM Info Mask Lower 3 (RINFOL3)" newline hexmask.quad.byte 0x0 16.--23. 1. "L2,RAM Info Mask Lower 2 (RINFOL2)" hexmask.quad.byte 0x0 8.--15. 1. "L1,RAM Info Mask Lower 1 (RINFOL1)" hexmask.quad.byte 0x0 0.--7. 1. "L0,RAM Info Mask Lower 0 (RINFOL0)" tree.end tree "PBIST8 (PBIST8)" base ad:0x3310000 rgroup.long 0x0++0x7F line.long 0x0 "MEM_RF0L," hexmask.long 0x0 0.--31. 1. "RF0L,Register Files / Instruction Registers RF0 lower (RF0L)" line.long 0x4 "MEM_RF1L," hexmask.long 0x4 0.--31. 1. "RF1L,Register Files / Instruction Registers RF1 lower (RF1L)" line.long 0x8 "MEM_RF2L," hexmask.long 0x8 0.--31. 1. "RF2L,Register Files / Instruction Registers RF2 lower (RF2L)" line.long 0xC "MEM_RF3L," hexmask.long 0xC 0.--31. 1. "RF3L,Register Files / Instruction Registers RF3 lower (RF3L)" line.long 0x10 "MEM_RF4L," hexmask.long 0x10 0.--31. 1. "RF4L,Register Files / Instruction Registers RF4 lower (RF4L)" line.long 0x14 "MEM_RF5L," hexmask.long 0x14 0.--31. 1. "RF5L,Register Files / Instruction Registers RF5 lower (RF5L)" line.long 0x18 "MEM_RF6L," hexmask.long 0x18 0.--31. 1. "RF6L,Register Files / Instruction Registers RF6 lower (RF6L)" line.long 0x1C "MEM_RF7L," hexmask.long 0x1C 0.--31. 1. "RF7L,Register Files / Instruction Registers RF7 lower (RF7L)" line.long 0x20 "MEM_RF8L," hexmask.long 0x20 0.--31. 1. "RF8L,Register Files / Instruction Registers RF8 lower (RF8L)" line.long 0x24 "MEM_RF9L," hexmask.long 0x24 0.--31. 1. "RF9L,Register Files / Instruction Registers RF9 lower (RF9L)" line.long 0x28 "MEM_RF10L," hexmask.long 0x28 0.--31. 1. "RF10L,Register Files / Instruction Registers RF10 lower (RF10L)" line.long 0x2C "MEM_RF11L," hexmask.long 0x2C 0.--31. 1. "RF11L,Register Files / Instruction Registers RF11 lower (RF11L)" line.long 0x30 "MEM_RF12L," hexmask.long 0x30 0.--31. 1. "RF12L,Register Files / Instruction Registers RF12 lower (RF12L)" line.long 0x34 "MEM_RF13L," hexmask.long 0x34 0.--31. 1. "RF13L,Register Files / Instruction Registers RF13 lower (RF13L)" line.long 0x38 "MEM_RF14L," hexmask.long 0x38 0.--31. 1. "RF14L,Register Files / Instruction Registers RF14 lower (RF14L)" line.long 0x3C "MEM_RF15L," hexmask.long 0x3C 0.--31. 1. "RF15L,Register Files / Instruction Registers RF15 lower (RF15L)" line.long 0x40 "MEM_RF0U," hexmask.long 0x40 0.--31. 1. "RF0U,Register Files / Instruction Registers RF0 upper (RF0U)" line.long 0x44 "MEM_RF1U," hexmask.long 0x44 0.--31. 1. "RF1U,Register Files / Instruction Registers RF1 upper (RF1U)" line.long 0x48 "MEM_RF2U," hexmask.long 0x48 0.--31. 1. "RF2U,Register Files / Instruction Registers RF2 upper (RF2U)" line.long 0x4C "MEM_RF3U," hexmask.long 0x4C 0.--31. 1. "RF3U,Register Files / Instruction Registers RF3 upper (RF3U)" line.long 0x50 "MEM_RF4U," hexmask.long 0x50 0.--31. 1. "RF4U,Register Files / Instruction Registers RF4 upper (RF4U)" line.long 0x54 "MEM_RF5U," hexmask.long 0x54 0.--31. 1. "RF5U,Register Files / Instruction Registers RF5 upper (RF5U)" line.long 0x58 "MEM_RF6U," hexmask.long 0x58 0.--31. 1. "RF6U,Register Files / Instruction Registers RF6 upper (RF6U)" line.long 0x5C "MEM_RF7U," hexmask.long 0x5C 0.--31. 1. "RF7U,Register Files / Instruction Registers RF7 upper (RF7U)" line.long 0x60 "MEM_RF8U," hexmask.long 0x60 0.--31. 1. "RF8U,Register Files / Instruction Registers RF8 upper (RF8U)" line.long 0x64 "MEM_RF9U," hexmask.long 0x64 0.--31. 1. "RF9U,Register Files / Instruction Registers RF9 upper (RF9U)" line.long 0x68 "MEM_RF10U," hexmask.long 0x68 0.--31. 1. "RF10U,Register Files / Instruction Registers RF10 upper (RF10U)" line.long 0x6C "MEM_RF11U," hexmask.long 0x6C 0.--31. 1. "RF11U,Register Files / Instruction Registers RF11 upper (RF11U)" line.long 0x70 "MEM_RF12U," hexmask.long 0x70 0.--31. 1. "RF12U,Register Files / Instruction Registers RF12 upper (RF12U)" line.long 0x74 "MEM_RF13U," hexmask.long 0x74 0.--31. 1. "RF13U,Register Files / Instruction Registers RF13 upper (RF13U)" line.long 0x78 "MEM_RF14U," hexmask.long 0x78 0.--31. 1. "RF14U,Register Files / Instruction Registers RF14 upper (RF14U)" line.long 0x7C "MEM_RF15U," hexmask.long 0x7C 0.--31. 1. "RF15U,Register Files / Instruction Registers RF15 upper (RF15U)" rgroup.long 0x100++0x27 line.long 0x0 "MEM_A0," hexmask.long.word 0x0 0.--15. 1. "A0,Variable Address Register 0 (A0)" line.long 0x4 "MEM_A1," hexmask.long.word 0x4 0.--15. 1. "A1,Variable Address Register 1 (A1)" line.long 0x8 "MEM_A2," hexmask.long.word 0x8 0.--15. 1. "A2,Variable Address Register 2 (A2)" line.long 0xC "MEM_A3," hexmask.long.word 0xC 0.--15. 1. "A3,Variable Address Register 3 (A3)" line.long 0x10 "MEM_L0," hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 (L0)" line.long 0x14 "MEM_L1," hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 (L1)" line.long 0x18 "MEM_L2," hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 (L2)" line.long 0x1C "MEM_L3," hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 (L3)" line.long 0x20 "MEM_D," hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 (D1)" hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 (D0)" line.long 0x24 "MEM_E," hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 (E1)" hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 (E0)" rgroup.long 0x130++0x3F line.long 0x0 "MEM_CA0," hexmask.long.word 0x0 0.--15. 1. "CA0,Constant Address Register 0 (CA0)" line.long 0x4 "MEM_CA1," hexmask.long.word 0x4 0.--15. 1. "CA1,Constant Address Register 1 (CA1)" line.long 0x8 "MEM_CA2," hexmask.long.word 0x8 0.--15. 1. "CA2,Constant Address Register 2 (CA2)" line.long 0xC "MEM_CA3," hexmask.long.word 0xC 0.--15. 1. "CA3,Constant Address Register 3 (CA3)" line.long 0x10 "MEM_CL0," hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 (CL0)" line.long 0x14 "MEM_CL1," hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 (CL1)" line.long 0x18 "MEM_CL2," hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 (CL2)" line.long 0x1C "MEM_CL3," hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 (CL3)" line.long 0x20 "MEM_I0," hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 (I0)" line.long 0x24 "MEM_I1," hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 (I1)" line.long 0x28 "MEM_I2," hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 (I2)" line.long 0x2C "MEM_I3," hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 (I3)" line.long 0x30 "MEM_RAMT," hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS" hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS" hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR" hexmask.long.byte 0x30 2.--5. 1. "PLS,Pipeline Latency Select" bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3" line.long 0x34 "MEM_DLR," hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 (BRP)" bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1" bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1" bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode (mainly for ROM testing)" "0,1" bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1" newline bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1" bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1" bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1" bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1" bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1" newline bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1" bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1" line.long 0x38 "MEM_CMS," hexmask.long.byte 0x38 0.--3. 1. "CMS,Clock Mux Select (CMS)" line.long 0x3C "MEM_STR," bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1" bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1" bitfld.long 0x3C 2. "STOP,Stop" "0,1" bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1" bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1" rgroup.quad 0x170++0x7 line.quad 0x0 "MEM_SCR," hexmask.quad.byte 0x0 56.--63. 1. "SCR7,Address Scrambling Register 7" hexmask.quad.byte 0x0 48.--55. 1. "SCR6,Address Scrambling Register 6" hexmask.quad.byte 0x0 40.--47. 1. "SCR5,Address Scrambling Register 5" hexmask.quad.byte 0x0 32.--39. 1. "SCR4,Address Scrambling Register 4" hexmask.quad.byte 0x0 24.--31. 1. "SCR3,Address Scrambling Register 3" newline hexmask.quad.byte 0x0 16.--23. 1. "SCR2,Address Scrambling Register 2" hexmask.quad.byte 0x0 8.--15. 1. "SCR1,Address Scrambling Register 1" hexmask.quad.byte 0x0 0.--7. 1. "SCR0,Address Scrambling Register 0" rgroup.long 0x178++0x13 line.long 0x0 "MEM_CSR," hexmask.long.byte 0x0 24.--31. 1. "CSR3,Chip Select 3 (CSR3)" hexmask.long.byte 0x0 16.--23. 1. "CSR2,Chip Select 2 (CSR2)" hexmask.long.byte 0x0 8.--15. 1. "CSR1,Chip Select 1(CSR1)" hexmask.long.byte 0x0 0.--7. 1. "CSR0,Chip Select 0 (CSR0)" line.long 0x4 "MEM_FDLY," hexmask.long.byte 0x4 0.--7. 1. "FDLY,Fail Delay (FDLY)" line.long 0x8 "MEM_PACT," bitfld.long 0x8 0. "PACT,PBIST Activate (PACT)" "0,1" line.long 0xC "MEM_PID," hexmask.long.byte 0xC 0.--4. 1. "PID,PBIST ID" line.long 0x10 "MEM_OVER," bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1" bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1" bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1" bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1" rgroup.quad 0x190++0x17 line.quad 0x0 "MEM_FSRF," bitfld.quad 0x0 32. "FRSF1,Fail Status Fail - Port 1 (FSRF1)" "0,1" bitfld.quad 0x0 0. "FRSF0,Fail Status Fail - Port 0 (FSRF0)" "0,1" line.quad 0x8 "MEM_FSRC," hexmask.quad.byte 0x8 32.--35. 1. "FSRC1,Fail Status Count - Port 1 (FSRC1)" hexmask.quad.byte 0x8 0.--3. 1. "FSRC0,Fail Status Count - Port 0 (FSRC0)" line.quad 0x10 "MEM_FSRA," hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 (FSRA1)" hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 (FSRA0)" rgroup.long 0x1A8++0x3 line.long 0x0 "MEM_FSRDL0," hexmask.long 0x0 0.--31. 1. "FSRDL0,Fail Status Data - Port 0 (FSRDL0)" rgroup.long 0x1B0++0xF line.long 0x0 "MEM_FSRDL1," hexmask.long 0x0 0.--31. 1. "FSRDL1,Fail Status Data - Port 1 (FSRDL1)" line.long 0x4 "MEM_MARGIN_MODE," bitfld.long 0x4 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3" bitfld.long 0x4 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3" line.long 0x8 "MEM_WRENZ," bitfld.long 0x8 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3" line.long 0xC "MEM_PAGE_PGS," bitfld.long 0xC 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3" rgroup.long 0x1C0++0x7 line.long 0x0 "MEM_ROM," bitfld.long 0x0 0.--1. "ROM,ROM Mask (ROM)" "0,1,2,3" line.long 0x4 "MEM_ALGO," hexmask.long.byte 0x4 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 (ALGO 3)" hexmask.long.byte 0x4 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 (ALGO 2)" hexmask.long.byte 0x4 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 (ALGO 1)" hexmask.long.byte 0x4 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 (ALGO 0)" rgroup.quad 0x1C8++0x7 line.quad 0x0 "MEM_RINFO," hexmask.quad.byte 0x0 56.--63. 1. "U3,RAM Info Mask Upper 3 (RINFOU3)" hexmask.quad.byte 0x0 48.--55. 1. "U2,RAM Info Mask Upper 2 (RINFOU2)" hexmask.quad.byte 0x0 40.--47. 1. "U1,RAM Info Mask Upper 1 (RINFOU1)" hexmask.quad.byte 0x0 32.--39. 1. "U0,RAM Info Mask Upper 0 (RINFOU0)" hexmask.quad.byte 0x0 24.--31. 1. "L3,RAM Info Mask Lower 3 (RINFOL3)" newline hexmask.quad.byte 0x0 16.--23. 1. "L2,RAM Info Mask Lower 2 (RINFOL2)" hexmask.quad.byte 0x0 8.--15. 1. "L1,RAM Info Mask Lower 1 (RINFOL1)" hexmask.quad.byte 0x0 0.--7. 1. "L0,RAM Info Mask Lower 0 (RINFOL0)" tree.end tree "PBIST10 (PBIST10)" base ad:0x3390000 rgroup.long 0x0++0x7F line.long 0x0 "MEM_RF0L," hexmask.long 0x0 0.--31. 1. "RF0L,Register Files / Instruction Registers RF0 lower (RF0L)" line.long 0x4 "MEM_RF1L," hexmask.long 0x4 0.--31. 1. "RF1L,Register Files / Instruction Registers RF1 lower (RF1L)" line.long 0x8 "MEM_RF2L," hexmask.long 0x8 0.--31. 1. "RF2L,Register Files / Instruction Registers RF2 lower (RF2L)" line.long 0xC "MEM_RF3L," hexmask.long 0xC 0.--31. 1. "RF3L,Register Files / Instruction Registers RF3 lower (RF3L)" line.long 0x10 "MEM_RF4L," hexmask.long 0x10 0.--31. 1. "RF4L,Register Files / Instruction Registers RF4 lower (RF4L)" line.long 0x14 "MEM_RF5L," hexmask.long 0x14 0.--31. 1. "RF5L,Register Files / Instruction Registers RF5 lower (RF5L)" line.long 0x18 "MEM_RF6L," hexmask.long 0x18 0.--31. 1. "RF6L,Register Files / Instruction Registers RF6 lower (RF6L)" line.long 0x1C "MEM_RF7L," hexmask.long 0x1C 0.--31. 1. "RF7L,Register Files / Instruction Registers RF7 lower (RF7L)" line.long 0x20 "MEM_RF8L," hexmask.long 0x20 0.--31. 1. "RF8L,Register Files / Instruction Registers RF8 lower (RF8L)" line.long 0x24 "MEM_RF9L," hexmask.long 0x24 0.--31. 1. "RF9L,Register Files / Instruction Registers RF9 lower (RF9L)" line.long 0x28 "MEM_RF10L," hexmask.long 0x28 0.--31. 1. "RF10L,Register Files / Instruction Registers RF10 lower (RF10L)" line.long 0x2C "MEM_RF11L," hexmask.long 0x2C 0.--31. 1. "RF11L,Register Files / Instruction Registers RF11 lower (RF11L)" line.long 0x30 "MEM_RF12L," hexmask.long 0x30 0.--31. 1. "RF12L,Register Files / Instruction Registers RF12 lower (RF12L)" line.long 0x34 "MEM_RF13L," hexmask.long 0x34 0.--31. 1. "RF13L,Register Files / Instruction Registers RF13 lower (RF13L)" line.long 0x38 "MEM_RF14L," hexmask.long 0x38 0.--31. 1. "RF14L,Register Files / Instruction Registers RF14 lower (RF14L)" line.long 0x3C "MEM_RF15L," hexmask.long 0x3C 0.--31. 1. "RF15L,Register Files / Instruction Registers RF15 lower (RF15L)" line.long 0x40 "MEM_RF0U," hexmask.long 0x40 0.--31. 1. "RF0U,Register Files / Instruction Registers RF0 upper (RF0U)" line.long 0x44 "MEM_RF1U," hexmask.long 0x44 0.--31. 1. "RF1U,Register Files / Instruction Registers RF1 upper (RF1U)" line.long 0x48 "MEM_RF2U," hexmask.long 0x48 0.--31. 1. "RF2U,Register Files / Instruction Registers RF2 upper (RF2U)" line.long 0x4C "MEM_RF3U," hexmask.long 0x4C 0.--31. 1. "RF3U,Register Files / Instruction Registers RF3 upper (RF3U)" line.long 0x50 "MEM_RF4U," hexmask.long 0x50 0.--31. 1. "RF4U,Register Files / Instruction Registers RF4 upper (RF4U)" line.long 0x54 "MEM_RF5U," hexmask.long 0x54 0.--31. 1. "RF5U,Register Files / Instruction Registers RF5 upper (RF5U)" line.long 0x58 "MEM_RF6U," hexmask.long 0x58 0.--31. 1. "RF6U,Register Files / Instruction Registers RF6 upper (RF6U)" line.long 0x5C "MEM_RF7U," hexmask.long 0x5C 0.--31. 1. "RF7U,Register Files / Instruction Registers RF7 upper (RF7U)" line.long 0x60 "MEM_RF8U," hexmask.long 0x60 0.--31. 1. "RF8U,Register Files / Instruction Registers RF8 upper (RF8U)" line.long 0x64 "MEM_RF9U," hexmask.long 0x64 0.--31. 1. "RF9U,Register Files / Instruction Registers RF9 upper (RF9U)" line.long 0x68 "MEM_RF10U," hexmask.long 0x68 0.--31. 1. "RF10U,Register Files / Instruction Registers RF10 upper (RF10U)" line.long 0x6C "MEM_RF11U," hexmask.long 0x6C 0.--31. 1. "RF11U,Register Files / Instruction Registers RF11 upper (RF11U)" line.long 0x70 "MEM_RF12U," hexmask.long 0x70 0.--31. 1. "RF12U,Register Files / Instruction Registers RF12 upper (RF12U)" line.long 0x74 "MEM_RF13U," hexmask.long 0x74 0.--31. 1. "RF13U,Register Files / Instruction Registers RF13 upper (RF13U)" line.long 0x78 "MEM_RF14U," hexmask.long 0x78 0.--31. 1. "RF14U,Register Files / Instruction Registers RF14 upper (RF14U)" line.long 0x7C "MEM_RF15U," hexmask.long 0x7C 0.--31. 1. "RF15U,Register Files / Instruction Registers RF15 upper (RF15U)" rgroup.long 0x100++0x27 line.long 0x0 "MEM_A0," hexmask.long.word 0x0 0.--15. 1. "A0,Variable Address Register 0 (A0)" line.long 0x4 "MEM_A1," hexmask.long.word 0x4 0.--15. 1. "A1,Variable Address Register 1 (A1)" line.long 0x8 "MEM_A2," hexmask.long.word 0x8 0.--15. 1. "A2,Variable Address Register 2 (A2)" line.long 0xC "MEM_A3," hexmask.long.word 0xC 0.--15. 1. "A3,Variable Address Register 3 (A3)" line.long 0x10 "MEM_L0," hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 (L0)" line.long 0x14 "MEM_L1," hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 (L1)" line.long 0x18 "MEM_L2," hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 (L2)" line.long 0x1C "MEM_L3," hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 (L3)" line.long 0x20 "MEM_D," hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 (D1)" hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 (D0)" line.long 0x24 "MEM_E," hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 (E1)" hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 (E0)" rgroup.long 0x130++0x3F line.long 0x0 "MEM_CA0," hexmask.long.word 0x0 0.--15. 1. "CA0,Constant Address Register 0 (CA0)" line.long 0x4 "MEM_CA1," hexmask.long.word 0x4 0.--15. 1. "CA1,Constant Address Register 1 (CA1)" line.long 0x8 "MEM_CA2," hexmask.long.word 0x8 0.--15. 1. "CA2,Constant Address Register 2 (CA2)" line.long 0xC "MEM_CA3," hexmask.long.word 0xC 0.--15. 1. "CA3,Constant Address Register 3 (CA3)" line.long 0x10 "MEM_CL0," hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 (CL0)" line.long 0x14 "MEM_CL1," hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 (CL1)" line.long 0x18 "MEM_CL2," hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 (CL2)" line.long 0x1C "MEM_CL3," hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 (CL3)" line.long 0x20 "MEM_I0," hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 (I0)" line.long 0x24 "MEM_I1," hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 (I1)" line.long 0x28 "MEM_I2," hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 (I2)" line.long 0x2C "MEM_I3," hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 (I3)" line.long 0x30 "MEM_RAMT," hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS" hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS" hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR" hexmask.long.byte 0x30 2.--5. 1. "PLS,Pipeline Latency Select" bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3" line.long 0x34 "MEM_DLR," hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 (BRP)" bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1" bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1" bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode (mainly for ROM testing)" "0,1" bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1" newline bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1" bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1" bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1" bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1" bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1" newline bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1" bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1" line.long 0x38 "MEM_CMS," hexmask.long.byte 0x38 0.--3. 1. "CMS,Clock Mux Select (CMS)" line.long 0x3C "MEM_STR," bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1" bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1" bitfld.long 0x3C 2. "STOP,Stop" "0,1" bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1" bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1" rgroup.quad 0x170++0x7 line.quad 0x0 "MEM_SCR," hexmask.quad.byte 0x0 56.--63. 1. "SCR7,Address Scrambling Register 7" hexmask.quad.byte 0x0 48.--55. 1. "SCR6,Address Scrambling Register 6" hexmask.quad.byte 0x0 40.--47. 1. "SCR5,Address Scrambling Register 5" hexmask.quad.byte 0x0 32.--39. 1. "SCR4,Address Scrambling Register 4" hexmask.quad.byte 0x0 24.--31. 1. "SCR3,Address Scrambling Register 3" newline hexmask.quad.byte 0x0 16.--23. 1. "SCR2,Address Scrambling Register 2" hexmask.quad.byte 0x0 8.--15. 1. "SCR1,Address Scrambling Register 1" hexmask.quad.byte 0x0 0.--7. 1. "SCR0,Address Scrambling Register 0" rgroup.long 0x178++0x13 line.long 0x0 "MEM_CSR," hexmask.long.byte 0x0 24.--31. 1. "CSR3,Chip Select 3 (CSR3)" hexmask.long.byte 0x0 16.--23. 1. "CSR2,Chip Select 2 (CSR2)" hexmask.long.byte 0x0 8.--15. 1. "CSR1,Chip Select 1(CSR1)" hexmask.long.byte 0x0 0.--7. 1. "CSR0,Chip Select 0 (CSR0)" line.long 0x4 "MEM_FDLY," hexmask.long.byte 0x4 0.--7. 1. "FDLY,Fail Delay (FDLY)" line.long 0x8 "MEM_PACT," bitfld.long 0x8 0. "PACT,PBIST Activate (PACT)" "0,1" line.long 0xC "MEM_PID," hexmask.long.byte 0xC 0.--4. 1. "PID,PBIST ID" line.long 0x10 "MEM_OVER," bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1" bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1" bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1" bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1" rgroup.quad 0x190++0x17 line.quad 0x0 "MEM_FSRF," bitfld.quad 0x0 32. "FRSF1,Fail Status Fail - Port 1 (FSRF1)" "0,1" bitfld.quad 0x0 0. "FRSF0,Fail Status Fail - Port 0 (FSRF0)" "0,1" line.quad 0x8 "MEM_FSRC," hexmask.quad.byte 0x8 32.--35. 1. "FSRC1,Fail Status Count - Port 1 (FSRC1)" hexmask.quad.byte 0x8 0.--3. 1. "FSRC0,Fail Status Count - Port 0 (FSRC0)" line.quad 0x10 "MEM_FSRA," hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 (FSRA1)" hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 (FSRA0)" rgroup.long 0x1A8++0x3 line.long 0x0 "MEM_FSRDL0," hexmask.long 0x0 0.--31. 1. "FSRDL0,Fail Status Data - Port 0 (FSRDL0)" rgroup.long 0x1B0++0xF line.long 0x0 "MEM_FSRDL1," hexmask.long 0x0 0.--31. 1. "FSRDL1,Fail Status Data - Port 1 (FSRDL1)" line.long 0x4 "MEM_MARGIN_MODE," bitfld.long 0x4 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3" bitfld.long 0x4 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3" line.long 0x8 "MEM_WRENZ," bitfld.long 0x8 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3" line.long 0xC "MEM_PAGE_PGS," bitfld.long 0xC 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3" rgroup.long 0x1C0++0x7 line.long 0x0 "MEM_ROM," bitfld.long 0x0 0.--1. "ROM,ROM Mask (ROM)" "0,1,2,3" line.long 0x4 "MEM_ALGO," hexmask.long.byte 0x4 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 (ALGO 3)" hexmask.long.byte 0x4 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 (ALGO 2)" hexmask.long.byte 0x4 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 (ALGO 1)" hexmask.long.byte 0x4 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 (ALGO 0)" rgroup.quad 0x1C8++0x7 line.quad 0x0 "MEM_RINFO," hexmask.quad.byte 0x0 56.--63. 1. "U3,RAM Info Mask Upper 3 (RINFOU3)" hexmask.quad.byte 0x0 48.--55. 1. "U2,RAM Info Mask Upper 2 (RINFOU2)" hexmask.quad.byte 0x0 40.--47. 1. "U1,RAM Info Mask Upper 1 (RINFOU1)" hexmask.quad.byte 0x0 32.--39. 1. "U0,RAM Info Mask Upper 0 (RINFOU0)" hexmask.quad.byte 0x0 24.--31. 1. "L3,RAM Info Mask Lower 3 (RINFOL3)" newline hexmask.quad.byte 0x0 16.--23. 1. "L2,RAM Info Mask Lower 2 (RINFOL2)" hexmask.quad.byte 0x0 8.--15. 1. "L1,RAM Info Mask Lower 1 (RINFOL1)" hexmask.quad.byte 0x0 0.--7. 1. "L0,RAM Info Mask Lower 0 (RINFOL0)" tree.end tree "PBIST11 (PBIST11)" base ad:0x3350000 rgroup.long 0x0++0x7F line.long 0x0 "MEM_RF0L," hexmask.long 0x0 0.--31. 1. "RF0L,Register Files / Instruction Registers RF0 lower (RF0L)" line.long 0x4 "MEM_RF1L," hexmask.long 0x4 0.--31. 1. "RF1L,Register Files / Instruction Registers RF1 lower (RF1L)" line.long 0x8 "MEM_RF2L," hexmask.long 0x8 0.--31. 1. "RF2L,Register Files / Instruction Registers RF2 lower (RF2L)" line.long 0xC "MEM_RF3L," hexmask.long 0xC 0.--31. 1. "RF3L,Register Files / Instruction Registers RF3 lower (RF3L)" line.long 0x10 "MEM_RF4L," hexmask.long 0x10 0.--31. 1. "RF4L,Register Files / Instruction Registers RF4 lower (RF4L)" line.long 0x14 "MEM_RF5L," hexmask.long 0x14 0.--31. 1. "RF5L,Register Files / Instruction Registers RF5 lower (RF5L)" line.long 0x18 "MEM_RF6L," hexmask.long 0x18 0.--31. 1. "RF6L,Register Files / Instruction Registers RF6 lower (RF6L)" line.long 0x1C "MEM_RF7L," hexmask.long 0x1C 0.--31. 1. "RF7L,Register Files / Instruction Registers RF7 lower (RF7L)" line.long 0x20 "MEM_RF8L," hexmask.long 0x20 0.--31. 1. "RF8L,Register Files / Instruction Registers RF8 lower (RF8L)" line.long 0x24 "MEM_RF9L," hexmask.long 0x24 0.--31. 1. "RF9L,Register Files / Instruction Registers RF9 lower (RF9L)" line.long 0x28 "MEM_RF10L," hexmask.long 0x28 0.--31. 1. "RF10L,Register Files / Instruction Registers RF10 lower (RF10L)" line.long 0x2C "MEM_RF11L," hexmask.long 0x2C 0.--31. 1. "RF11L,Register Files / Instruction Registers RF11 lower (RF11L)" line.long 0x30 "MEM_RF12L," hexmask.long 0x30 0.--31. 1. "RF12L,Register Files / Instruction Registers RF12 lower (RF12L)" line.long 0x34 "MEM_RF13L," hexmask.long 0x34 0.--31. 1. "RF13L,Register Files / Instruction Registers RF13 lower (RF13L)" line.long 0x38 "MEM_RF14L," hexmask.long 0x38 0.--31. 1. "RF14L,Register Files / Instruction Registers RF14 lower (RF14L)" line.long 0x3C "MEM_RF15L," hexmask.long 0x3C 0.--31. 1. "RF15L,Register Files / Instruction Registers RF15 lower (RF15L)" line.long 0x40 "MEM_RF0U," hexmask.long 0x40 0.--31. 1. "RF0U,Register Files / Instruction Registers RF0 upper (RF0U)" line.long 0x44 "MEM_RF1U," hexmask.long 0x44 0.--31. 1. "RF1U,Register Files / Instruction Registers RF1 upper (RF1U)" line.long 0x48 "MEM_RF2U," hexmask.long 0x48 0.--31. 1. "RF2U,Register Files / Instruction Registers RF2 upper (RF2U)" line.long 0x4C "MEM_RF3U," hexmask.long 0x4C 0.--31. 1. "RF3U,Register Files / Instruction Registers RF3 upper (RF3U)" line.long 0x50 "MEM_RF4U," hexmask.long 0x50 0.--31. 1. "RF4U,Register Files / Instruction Registers RF4 upper (RF4U)" line.long 0x54 "MEM_RF5U," hexmask.long 0x54 0.--31. 1. "RF5U,Register Files / Instruction Registers RF5 upper (RF5U)" line.long 0x58 "MEM_RF6U," hexmask.long 0x58 0.--31. 1. "RF6U,Register Files / Instruction Registers RF6 upper (RF6U)" line.long 0x5C "MEM_RF7U," hexmask.long 0x5C 0.--31. 1. "RF7U,Register Files / Instruction Registers RF7 upper (RF7U)" line.long 0x60 "MEM_RF8U," hexmask.long 0x60 0.--31. 1. "RF8U,Register Files / Instruction Registers RF8 upper (RF8U)" line.long 0x64 "MEM_RF9U," hexmask.long 0x64 0.--31. 1. "RF9U,Register Files / Instruction Registers RF9 upper (RF9U)" line.long 0x68 "MEM_RF10U," hexmask.long 0x68 0.--31. 1. "RF10U,Register Files / Instruction Registers RF10 upper (RF10U)" line.long 0x6C "MEM_RF11U," hexmask.long 0x6C 0.--31. 1. "RF11U,Register Files / Instruction Registers RF11 upper (RF11U)" line.long 0x70 "MEM_RF12U," hexmask.long 0x70 0.--31. 1. "RF12U,Register Files / Instruction Registers RF12 upper (RF12U)" line.long 0x74 "MEM_RF13U," hexmask.long 0x74 0.--31. 1. "RF13U,Register Files / Instruction Registers RF13 upper (RF13U)" line.long 0x78 "MEM_RF14U," hexmask.long 0x78 0.--31. 1. "RF14U,Register Files / Instruction Registers RF14 upper (RF14U)" line.long 0x7C "MEM_RF15U," hexmask.long 0x7C 0.--31. 1. "RF15U,Register Files / Instruction Registers RF15 upper (RF15U)" rgroup.long 0x100++0x27 line.long 0x0 "MEM_A0," hexmask.long.word 0x0 0.--15. 1. "A0,Variable Address Register 0 (A0)" line.long 0x4 "MEM_A1," hexmask.long.word 0x4 0.--15. 1. "A1,Variable Address Register 1 (A1)" line.long 0x8 "MEM_A2," hexmask.long.word 0x8 0.--15. 1. "A2,Variable Address Register 2 (A2)" line.long 0xC "MEM_A3," hexmask.long.word 0xC 0.--15. 1. "A3,Variable Address Register 3 (A3)" line.long 0x10 "MEM_L0," hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 (L0)" line.long 0x14 "MEM_L1," hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 (L1)" line.long 0x18 "MEM_L2," hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 (L2)" line.long 0x1C "MEM_L3," hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 (L3)" line.long 0x20 "MEM_D," hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 (D1)" hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 (D0)" line.long 0x24 "MEM_E," hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 (E1)" hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 (E0)" rgroup.long 0x130++0x3F line.long 0x0 "MEM_CA0," hexmask.long.word 0x0 0.--15. 1. "CA0,Constant Address Register 0 (CA0)" line.long 0x4 "MEM_CA1," hexmask.long.word 0x4 0.--15. 1. "CA1,Constant Address Register 1 (CA1)" line.long 0x8 "MEM_CA2," hexmask.long.word 0x8 0.--15. 1. "CA2,Constant Address Register 2 (CA2)" line.long 0xC "MEM_CA3," hexmask.long.word 0xC 0.--15. 1. "CA3,Constant Address Register 3 (CA3)" line.long 0x10 "MEM_CL0," hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 (CL0)" line.long 0x14 "MEM_CL1," hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 (CL1)" line.long 0x18 "MEM_CL2," hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 (CL2)" line.long 0x1C "MEM_CL3," hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 (CL3)" line.long 0x20 "MEM_I0," hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 (I0)" line.long 0x24 "MEM_I1," hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 (I1)" line.long 0x28 "MEM_I2," hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 (I2)" line.long 0x2C "MEM_I3," hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 (I3)" line.long 0x30 "MEM_RAMT," hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS" hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS" hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR" hexmask.long.byte 0x30 2.--5. 1. "PLS,Pipeline Latency Select" bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3" line.long 0x34 "MEM_DLR," hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 (BRP)" bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1" bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1" bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode (mainly for ROM testing)" "0,1" bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1" newline bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1" bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1" bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1" bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1" bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1" newline bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1" bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1" line.long 0x38 "MEM_CMS," hexmask.long.byte 0x38 0.--3. 1. "CMS,Clock Mux Select (CMS)" line.long 0x3C "MEM_STR," bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1" bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1" bitfld.long 0x3C 2. "STOP,Stop" "0,1" bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1" bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1" rgroup.quad 0x170++0x7 line.quad 0x0 "MEM_SCR," hexmask.quad.byte 0x0 56.--63. 1. "SCR7,Address Scrambling Register 7" hexmask.quad.byte 0x0 48.--55. 1. "SCR6,Address Scrambling Register 6" hexmask.quad.byte 0x0 40.--47. 1. "SCR5,Address Scrambling Register 5" hexmask.quad.byte 0x0 32.--39. 1. "SCR4,Address Scrambling Register 4" hexmask.quad.byte 0x0 24.--31. 1. "SCR3,Address Scrambling Register 3" newline hexmask.quad.byte 0x0 16.--23. 1. "SCR2,Address Scrambling Register 2" hexmask.quad.byte 0x0 8.--15. 1. "SCR1,Address Scrambling Register 1" hexmask.quad.byte 0x0 0.--7. 1. "SCR0,Address Scrambling Register 0" rgroup.long 0x178++0x13 line.long 0x0 "MEM_CSR," hexmask.long.byte 0x0 24.--31. 1. "CSR3,Chip Select 3 (CSR3)" hexmask.long.byte 0x0 16.--23. 1. "CSR2,Chip Select 2 (CSR2)" hexmask.long.byte 0x0 8.--15. 1. "CSR1,Chip Select 1(CSR1)" hexmask.long.byte 0x0 0.--7. 1. "CSR0,Chip Select 0 (CSR0)" line.long 0x4 "MEM_FDLY," hexmask.long.byte 0x4 0.--7. 1. "FDLY,Fail Delay (FDLY)" line.long 0x8 "MEM_PACT," bitfld.long 0x8 0. "PACT,PBIST Activate (PACT)" "0,1" line.long 0xC "MEM_PID," hexmask.long.byte 0xC 0.--4. 1. "PID,PBIST ID" line.long 0x10 "MEM_OVER," bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1" bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1" bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1" bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1" rgroup.quad 0x190++0x17 line.quad 0x0 "MEM_FSRF," bitfld.quad 0x0 32. "FRSF1,Fail Status Fail - Port 1 (FSRF1)" "0,1" bitfld.quad 0x0 0. "FRSF0,Fail Status Fail - Port 0 (FSRF0)" "0,1" line.quad 0x8 "MEM_FSRC," hexmask.quad.byte 0x8 32.--35. 1. "FSRC1,Fail Status Count - Port 1 (FSRC1)" hexmask.quad.byte 0x8 0.--3. 1. "FSRC0,Fail Status Count - Port 0 (FSRC0)" line.quad 0x10 "MEM_FSRA," hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 (FSRA1)" hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 (FSRA0)" rgroup.long 0x1A8++0x3 line.long 0x0 "MEM_FSRDL0," hexmask.long 0x0 0.--31. 1. "FSRDL0,Fail Status Data - Port 0 (FSRDL0)" rgroup.long 0x1B0++0xF line.long 0x0 "MEM_FSRDL1," hexmask.long 0x0 0.--31. 1. "FSRDL1,Fail Status Data - Port 1 (FSRDL1)" line.long 0x4 "MEM_MARGIN_MODE," bitfld.long 0x4 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3" bitfld.long 0x4 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3" line.long 0x8 "MEM_WRENZ," bitfld.long 0x8 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3" line.long 0xC "MEM_PAGE_PGS," bitfld.long 0xC 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3" rgroup.long 0x1C0++0x7 line.long 0x0 "MEM_ROM," bitfld.long 0x0 0.--1. "ROM,ROM Mask (ROM)" "0,1,2,3" line.long 0x4 "MEM_ALGO," hexmask.long.byte 0x4 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 (ALGO 3)" hexmask.long.byte 0x4 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 (ALGO 2)" hexmask.long.byte 0x4 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 (ALGO 1)" hexmask.long.byte 0x4 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 (ALGO 0)" rgroup.quad 0x1C8++0x7 line.quad 0x0 "MEM_RINFO," hexmask.quad.byte 0x0 56.--63. 1. "U3,RAM Info Mask Upper 3 (RINFOU3)" hexmask.quad.byte 0x0 48.--55. 1. "U2,RAM Info Mask Upper 2 (RINFOU2)" hexmask.quad.byte 0x0 40.--47. 1. "U1,RAM Info Mask Upper 1 (RINFOU1)" hexmask.quad.byte 0x0 32.--39. 1. "U0,RAM Info Mask Upper 0 (RINFOU0)" hexmask.quad.byte 0x0 24.--31. 1. "L3,RAM Info Mask Lower 3 (RINFOL3)" newline hexmask.quad.byte 0x0 16.--23. 1. "L2,RAM Info Mask Lower 2 (RINFOL2)" hexmask.quad.byte 0x0 8.--15. 1. "L1,RAM Info Mask Lower 1 (RINFOL1)" hexmask.quad.byte 0x0 0.--7. 1. "L0,RAM Info Mask Lower 0 (RINFOL0)" tree.end tree.end tree "PCIE1" base ad:0x0 tree "PCIE1_CORE" tree "PCIE1_CORE_CPTS_CFG_CPTS_VBUSP (PCIE1_CORE_CPTS_CFG_CPTS_VBUSP)" base ad:0x2916000 rgroup.long 0x0++0x3 line.long 0x0 "CORE__CPTS_CFG__CPTS_VBUSP_CPTS_IDVER_REG,Identification and Version Register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" rgroup.long 0x4++0x7 line.long 0x0 "CORE__CPTS_CFG__CPTS_VBUSP_CONTROL_REG,Time Sync Control Register" hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" bitfld.long 0x0 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1" newline bitfld.long 0x0 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1" bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1" newline bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1" bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1" newline bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1" bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" newline bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" newline bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" bitfld.long 0x0 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1" newline bitfld.long 0x0 6. "TS_COMP_TOG,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode 1=TS_COMP is in toggle mode" "0: TS_COMP is in non-toggle mode,1: TS_COMP is in toggle mode" bitfld.long 0x0 5. "MODE,Timestamp mode" "0,1" newline bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable" "0,1" bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1" newline bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1" bitfld.long 0x0 1. "INT_TEST,Interrupt test" "0,1" newline bitfld.long 0x0 0. "CPTS_EN,Time sync enable" "0,1" line.long 0x4 "CORE__CPTS_CFG__CPTS_VBUSP_RFTCLK_SEL_REG,RFTCLK Select Register" hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select" rgroup.long 0xC++0x3 line.long 0x0 "CORE__CPTS_CFG__CPTS_VBUSP_TS_PUSH_REG,Time Stamp Event Push Register" bitfld.long 0x0 0. "TS_PUSH,Time stamp event push" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "CORE__CPTS_CFG__CPTS_VBUSP_TS_LOAD_LOW_VAL_REG,Time Stamp Load Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value" rgroup.long 0x14++0x3 line.long 0x0 "CORE__CPTS_CFG__CPTS_VBUSP_TS_LOAD_EN_REG,Time Stamp Load Enable Register" bitfld.long 0x0 0. "TS_LOAD_EN,Time stamp load enable" "0,1" rgroup.long 0x18++0xB line.long 0x0 "CORE__CPTS_CFG__CPTS_VBUSP_TS_COMP_LOW_VAL_REG,Time Stamp Comparison Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time stamp comparison low value" line.long 0x4 "CORE__CPTS_CFG__CPTS_VBUSP_TS_COMP_LEN_REG,Time Stamp Comparison Length Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time stamp comparison length" line.long 0x8 "CORE__CPTS_CFG__CPTS_VBUSP_INTSTAT_RAW_REG,Interrupt Status Register Raw" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "CORE__CPTS_CFG__CPTS_VBUSP_INTSTAT_MASKED_REG,Interrupt Status Register Masked" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" rgroup.long 0x28++0x7 line.long 0x0 "CORE__CPTS_CFG__CPTS_VBUSP_INT_ENABLE_REG,Interrupt Enable Register" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" line.long 0x4 "CORE__CPTS_CFG__CPTS_VBUSP_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount" rgroup.long 0x30++0x3 line.long 0x0 "CORE__CPTS_CFG__CPTS_VBUSP_EVENT_POP_REG,Event Pop Register" bitfld.long 0x0 0. "EVENT_POP,Event pop" "0,1" rgroup.long 0x34++0xF line.long 0x0 "CORE__CPTS_CFG__CPTS_VBUSP_EVENT_0_REG,Event 0 Register" hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp" line.long 0x4 "CORE__CPTS_CFG__CPTS_VBUSP_EVENT_1_REG,Event 1 Register" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1" hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port number" newline hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Event type" hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type" newline hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID" line.long 0x8 "CORE__CPTS_CFG__CPTS_VBUSP_EVENT_2_REG,Event 2 Register" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain" line.long 0xC "CORE__CPTS_CFG__CPTS_VBUSP_EVENT_3_REG,Event 3 Register" hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp" rgroup.long 0x44++0x17 line.long 0x0 "CORE__CPTS_CFG__CPTS_VBUSP_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load high value" line.long 0x4 "CORE__CPTS_CFG__CPTS_VBUSP_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time stamp comparison high value" line.long 0x8 "CORE__CPTS_CFG__CPTS_VBUSP_TS_ADD_VAL_REG,TS Add Value Register" bitfld.long 0x8 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7" line.long 0xC "CORE__CPTS_CFG__CPTS_VBUSP_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register" hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time stamp PPM Low value" line.long 0x10 "CORE__CPTS_CFG__CPTS_VBUSP_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value" line.long 0x14 "CORE__CPTS_CFG__CPTS_VBUSP_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value" rgroup.long 0xE0++0x1B line.long 0x0 "CORE__CPTS_CFG__CPTS_VBUSP_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value" line.long 0x4 "CORE__CPTS_CFG__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value" line.long 0x8 "CORE__CPTS_CFG__CPTS_VBUSP_CONTROL_REG,Time Stamp Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1" line.long 0xC "CORE__CPTS_CFG__CPTS_VBUSP_LENGTH_REG,Time Stamp Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value" line.long 0x10 "CORE__CPTS_CFG__CPTS_VBUSP_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value" line.long 0x14 "CORE__CPTS_CFG__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value" line.long 0x18 "CORE__CPTS_CFG__CPTS_VBUSP_NUDGE_REG,Time Stamp Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value" rgroup.long 0x200++0x1B line.long 0x0 "CORE__CPTS_CFG__CPTS_VBUSP_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp ESTF Generate Function Comparison Low Value" line.long 0x4 "CORE__CPTS_CFG__CPTS_VBUSP_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp ESTF Generate Function Comparison High Value" line.long 0x8 "CORE__CPTS_CFG__CPTS_VBUSP_CONTROL_REG,Time Stamp ESTF Generate Function Control" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1" line.long 0xC "CORE__CPTS_CFG__CPTS_VBUSP_LENGTH_REG,Time Stamp ESTF Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp ESTF Generate Function Length Value" line.long 0x10 "CORE__CPTS_CFG__CPTS_VBUSP_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp ESTF Generate Function PPM Low Value" line.long 0x14 "CORE__CPTS_CFG__CPTS_VBUSP_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value" line.long 0x18 "CORE__CPTS_CFG__CPTS_VBUSP_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value" tree.end tree "PCIE1_CORE_DBN_CFG_PCIE_CORE (PCIE1_CORE_DBN_CFG_PCIE_CORE)" base ad:0xD800000 rgroup.long 0x0++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_vendor_id_device_id,16-bit Vendor ID register and 16-bit Device ID register." hexmask.long.word 0x0 16.--31. 1. "DID,Device ID assigned by the manufacturer of the device. On power-up the Controller sets it to the value defined in the RTL file reg_defaults.h. This field can be written from the APB bus by setting [21] bit high of the.." newline hexmask.long.word 0x0 0.--15. 1. "VID,This is the Vendor ID assigned by PCI SIG to the manufacturer of the device. The Vendor ID is set in the Vendor ID Register within the local management register block." rgroup.long 0x4++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_command_status,16-bit Command Register and 16-bit Status Register." bitfld.long 0x0 31. "DPE,This bit is set when the Controller has received a poisoned TLP. The Parity Error Response enable bit [bit 6] has no effect on the setting of this bit. This field can also be cleared from the local management bus APB by writing a 1 into.." "0,1" newline bitfld.long 0x0 30. "SSE,The Controller sets this bit [i]On receiving an error message from the link if SERR-Enable in PCI Command Register is 1 and SERR-Enable in the Bridge Control Register is also 1. [ii]On any internal Fatal/Non-Fatal error detected if.." "0,1" newline bitfld.long 0x0 29. "RMA,This bit is set when the Controller has received a completion from the link with the Unsupported Request status. This field can also be cleared from the local management APB bus by writing a 1 into this bit position This field can.." "0,1" newline bitfld.long 0x0 28. "RTA,This bit is set when the Controller has received a completion from the link with the Completer Abort status. This field can also be cleared from the local management APB bus by writing a 1 into this bit position. This field can be.." "0,1" newline bitfld.long 0x0 27. "STA,This bit is set when the Controller has sent a completion to the link with the Completer Abort status. This field can also be cleared from the local management APB bus by writing a 1 into this bit position. This field can be forced.." "0,1" newline bitfld.long 0x0 24. "MDPE,When the Parity Error Response enable bit is 1 the Controller sets this bit when it detects the following error conditions: [i] The Controller receives a poisoned request from the link. [ii] The Controller has sent a Poisoned Completion.." "0,1" newline rbitfld.long 0x0 20. "CL,Indicates the presence of PCI Extended Capabilities registers. This bit is hardwired to 1." "0,1" newline rbitfld.long 0x0 19. "IS,This bit is valid only when the Controller is configured to support legacy interrupts. Indicates that the Controller has a pending interrupt that is the Controller has sent an Assert_INTx message but has not transmitted a corresponding.." "0,1" newline bitfld.long 0x0 10. "IMD,Enables or disables the transmission of INTx Assert and De-assert messages from the Controller. The setting of this bit has no effect on the operation of the Controller in the RC mode." "0,1" newline bitfld.long 0x0 8. "SE,Enables the reporting of fatal and non-fatal errors detected by the Controller to the Root Complex." "0,1" newline bitfld.long 0x0 6. "PERE,When this bit is 1 the Controller sets the Master Data Parity Error status bit when it detects the following error conditions: [i] The Controller receives a poisoned completion from the link in response to a request. [ii] The.." "0,1" newline bitfld.long 0x0 2. "BE,For a Function with a Type 1 Configurations Space header[Controller in RP Mode] this bit controls forwarding of Memory or I/O Requests by a Port in the Upstream direction. Note: The Controller does not generate any.." "0,1" newline bitfld.long 0x0 1. "MSE,For a Function with a Type 1 Configuration Space header[Controller in RP Mode] this bit controls the response to Memory Space accesses received on its Primary Side. Note: The Controller does not generate any response.." "0,1" newline bitfld.long 0x0 0. "ISE,For a Function with a Type 1 Configuration Space header [Controller in RP Mode] this bit controls the response to I/O Space accesses received on its Primary Side. Note: The Controller does not generate any response based.." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_revision_id_class_code,This register contains the Revision ID and Class Code associated with the device" hexmask.long.byte 0x0 24.--31. 1. "CC,Identifies the function of the device. On power-up the Controller sets it to the value defined in the RTL file reg_defaults.h. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a.." newline hexmask.long.byte 0x0 16.--23. 1. "SCC,Identifies a sub-category within the selected function. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write." newline hexmask.long.byte 0x0 8.--15. 1. "PIB,Identifies the register set layout of the device. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write." newline hexmask.long.byte 0x0 0.--7. 1. "RID,Assigned by the manufacturer of the device to identify the revision number of the device. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write." rgroup.long 0xC++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_bist_header_latency_cache_line,This location contains the BIST. header-type. Latency Timer and Cache Line Size" hexmask.long.byte 0x0 24.--31. 1. "BR,BIST control register. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write." newline rbitfld.long 0x0 23. "DT,Identifies whether the device supports a single Function or multiple Functions. Hardwired to zero" "0,1" newline hexmask.long.byte 0x0 16.--22. 1. "HT,Identifies format of header. This field is hardwired to 1." newline hexmask.long.byte 0x0 8.--15. 1. "LT,This is an unused field and is hardwired to 0." newline hexmask.long.byte 0x0 0.--7. 1. "CLS,Cache Line Size Register defined in PCI Specifications 3.0. This field can be read or written both from the link and from the local management bus but its value is not used." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_RC_BAR_0,This is the Base Address Register 0 in the Type-1 Config Space. It can be configured" hexmask.long.word 0x4 22.--31. 1. "BAMRW,This field defines the base address of the memory address range. The number of implemented bits in this field determines the BAR aperture configured in Root Complex BAR Configuration Register. All other bits are not writeable and are.." newline hexmask.long.tbyte 0x4 4.--21. 1. "BAMR0,This field defines the base address of the memory address range. The number of implemented bits in this field determines the BAR aperture configured in Root Complex BAR Configuration Register. All other bits are not writeable and are.." newline rbitfld.long 0x4 3. "P0,For memory BAR: This bit reads as 1 when BAR 0 is configured as a prefetchable BAR and as 0 when configured as a non-prefetchable BAR. For IO BAR: This is bit 3 of the base address. The value read in this field is determined by the.." "0,1" newline rbitfld.long 0x4 2. "S0,For memory BAR:This bit reads as 0 when BAR 0 is configured as a 32-bit BAR and as 1 when configured as a 64-bit BAR. For IO BAR: This is bit 3 of the base address. The value read in this field is determined by the setting of Root Complex.." "0,1" newline rbitfld.long 0x4 1. "R7,This bit is hardwired to 0 for both memory and I/O BARs." "0,1" newline rbitfld.long 0x4 0. "MSI0,Specifies whether this BAR defines a memory address range or an I/O address range [0 = memory 1 = I/O]. The value read in this field is determined by the setting of Root Complex BAR Configuration Register." "0: memory,1: I/O]" rgroup.long 0x14++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_RC_BAR_1,This is the Base Address Register 1 in the Type-1 Config Space. It can be configured as a" hexmask.long 0x0 0.--31. 1. "R7,This field is reserved at power-on. This can be changed using BAR configuration regsiter in LM space." rgroup.long 0x18++0xB line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_pcie_bus_numbers,This location contains the 8-bit fields: Primary Bus Number. Secondary Bus Number.Subordinate Bus Number. Secondary Latency" hexmask.long.byte 0x0 24.--31. 1. "SLTN,This field is not implemented." newline hexmask.long.byte 0x0 16.--23. 1. "SUBN,This field can be read and written from the local management bus but its value is not used within the Controller." newline hexmask.long.byte 0x0 8.--15. 1. "SBN,This field can be read and written from the local management bus but its value is not used within the Controller." newline hexmask.long.byte 0x0 0.--7. 1. "PBN,This field can be read and written from the local management bus but its value is not used within the Controller." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_pcie_io_base_limit,This location contains the 8-bit IO Base Register. the 8-bit IO Limit Register and the 16-bit Secondary Status Registers." bitfld.long 0x4 31. "DPE,The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the.." "0,1" newline bitfld.long 0x4 30. "RSE,The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the.." "0,1" newline bitfld.long 0x4 29. "RMA,The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the.." "0,1" newline bitfld.long 0x4 28. "RTA,The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the.." "0,1" newline bitfld.long 0x4 27. "STA,The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the.." "0,1" newline bitfld.long 0x4 24. "MPE,The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the.." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "ILR,This field can be read and written from the local management bus if IO BAR is enabled in the Root Complex BAR configuration register else it is hardwired to zero. Its value is not used within the Controller." newline rbitfld.long 0x4 8. "IOBS2,value set in Type1 cfg IO bar size[bit 20 of RC BAR CONFIG register].If type1 cfg IObar enable bit[bit 19 in RC BAR CONFIG register] is not set then this field will be hard coded to 0." "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "IBR,This field can be read and written from the local management bus if IO BAR is enabled in the Root Complex BAR configuration register else it is hardwired to zero. Its value is not used within the Controller." newline rbitfld.long 0x4 0. "IOBS1,value set in Type1 cfg IO bar size[bit 20 of RC BAR CONFIG register]. If type1 cfg IObar enable bit[bit 19 in RC BAR CONFIG register] is not set then this field will be hard coded to 0." "0,1" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_pcie_mem_base_limit,This location contains the 16-bit Memory Base Register and the 16-bit Memory Limit Register" hexmask.long.word 0x8 20.--31. 1. "MLR,This field can be read and written from the local management APB bus but its value is not used within the Controller." newline hexmask.long.word 0x8 4.--15. 1. "MBR,This field can be read and written from the local management APB bus but its value is not used within the Controller." rgroup.long 0x24++0x13 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_pcie_prefetch_base_limit,This location contains the Prefetchable Memory Base Register and the Prefetchable Memory Limit" hexmask.long.word 0x0 16.--31. 1. "PMLR,This field can be read and written from the local management APB bus if prefetchable memory is enabled in the Root Complex BAR configuration register else it is hardwired to zero. Its value is not used within the Controller." newline hexmask.long.word 0x0 0.--15. 1. "PMBR,This field can be read and written from the local management APB bus if prefetchable memory is enabled in the Root Complex BAR configuration register else it is hardwired to zero. Its value is not used within the Controller." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_pcie_prefetch_base_upper,This location contains the upper 32 bits of the Prefetchable Base Register. This register is" hexmask.long 0x4 0.--31. 1. "PBRU,This field can be read and written from the local management APB bus if 64bit prefetchable memory is enabled in the Root Complex BAR configuration register else it is hardwired to zero. Its value is not used within the Controller." line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_pcie_prefetch_limit_upper,This location contains the upper 32 bits of the Prefetchable Limit Register. This register" hexmask.long 0x8 0.--31. 1. "PLRU,This field can be read and written from the local management APB bus if 64bit prefetchable memory is enabled in the Root Complex BAR configuration register else it is hardwired to zero. Its value is not used within the Controller." line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_i_pcie_io_base_limit_upper,This location contains the upper 16 bits of the IO Base and IO Limit Registers" hexmask.long.word 0xC 16.--31. 1. "ILR,This field can be read and written from the local management bus if 32bit IO BAR is enabled in the Root Complex BAR configuration register else it is hardwired to zero. Its value is not used within the Controller." newline hexmask.long.word 0xC 0.--15. 1. "IBRU,This field can be read and written from the local management bus if 32bit IO BAR is enabled in the Root Complex BAR configuration register else it is hardwired to zero. Its value is not used within the Controller." line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_i_capabilities_pointer,This location contains the pointer to the first PCI Capabilities Structure." hexmask.long.byte 0x10 0.--7. 1. "CP,Contains pointer to the first PCI Capability Structure. This field is set by default to the value defined in the RTL file reg_defaults.h. It can be re-written independently for every Function from the local management APB bus." rgroup.long 0x38++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_rsvd_0E,Reserved" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_intrpt_line_intrpt_pin,This location contains the Interrupt Line Register. the Interrupt Pin Register." bitfld.long 0x4 22. "BCRSBR,This field can be read and written from the local management APB bus. When set it initiates a hot reset on the link." "0,1" newline bitfld.long 0x4 20. "VGA16D,This field can be read and written from the local management APB bus but its value is not used within the Controller." "0,1" newline bitfld.long 0x4 19. "VGAE,This field can be read and written from the local management APB bus but its value is not used within the Controller." "0,1" newline bitfld.long 0x4 18. "ISAE,This field can be read and written from the local management APB bus but its value is not used within the Controller." "0,1" newline bitfld.long 0x4 17. "BCSE,This field can be read and written from the local management APB bus but its value is not used within the Controller." "0,1" newline bitfld.long 0x4 16. "PERE,This field can be read and written from the local management APB bus. It is used only to enable the Master Data Parity Error bit in the Secondary Status Register." "0,1" newline rbitfld.long 0x4 8.--10. "IPR,Identifies the interrupt input [A B C D] to which this Functions interrupt output is connected to [01 = INTA 02 = INTB 03 = INTC 04 = INTD]. The assignment of interrupt inputs to Functions is fixed when the Controller is configured." "?,1: INTA,2: INTB,3: INTC,4: INTD],?,?,?" newline hexmask.long.byte 0x4 0.--7. 1. "ILR,This field can be read and written from the local management bus but its value is not used within the Controller.The given reset value is for PF0." rgroup.long 0x80++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_pwr_mgmt_cap,This location contains the Power Management Capabilities Register. its Capability ID." bitfld.long 0x0 31. "PSDCS,Indicates whether the Function is capable of sending PME messages when in the D3cold state. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write." "0,1" newline bitfld.long 0x0 30. "PSDHS,Indicates whether the Function is capable of sending PME messages when in the D3hot state. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register.." "0,1" newline bitfld.long 0x0 29. "PSD2S,Indicates whether the Function is capable of sending PME messages when in the D2 state. This bit is hardwired to 0 because D2 state is not supported." "0,1" newline bitfld.long 0x0 28. "PSD1S,Indicates whether the Function is capable of sending PME messages when in the D1 state. This bit is set to 1 by default but can be modified from the local management bus by writing into Function 0. All other Functions assume the value.." "0,1" newline bitfld.long 0x0 27. "PSD0S,Indicates whether the Function is capable of sending PME messages when in the D0 state. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write." "0,1" newline bitfld.long 0x0 26. "D2S,Set if the Function supports the D2 power state. Currently hardwired to 0." "0,1" newline bitfld.long 0x0 25. "D1S,Set if the Function supports the D1 power state. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write." "0,1" newline bitfld.long 0x0 22.--24. "MCRAPS,Specifies the maximum current drawn by the device from the aux power source in the D3cold state. This field is not implemented in devices not supporting PME notification when in the D3cold state and is therefore hardwired to 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "DSI,This bit when set indicates that the device requires additional configuration steps beyond setting up its PCI configuration space to bring it to the D0 active state from the D0 uninitialized state. This bit is hardwired to 0." "0,1" newline bitfld.long 0x0 19. "PC,Not applicable to PCI Express. This bit is hardwired to 0." "0,1" newline bitfld.long 0x0 16.--18. "VID,Indicates the version of the PCI Bus Power Management Specifications that the Function implements. This field is set by default to 011 [Version 1.2]. This field can be written from the APB bus by setting [21] bit high of the.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "CP,Contains pointer to the next PCI Capability Structure. The Controller sets it to the value defined in the RTL file reg_defaults.h. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during.." newline hexmask.long.byte 0x0 0.--7. 1. "CID,Identifies that the capability structure is for Power Management. This field is set by default to 01 hex. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management.." rgroup.long 0x84++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_pwr_mgmt_ctrl_stat_rep,This location contains the Power Management Control/Status and Data Registers." hexmask.long.byte 0x0 24.--31. 1. "DR,This optional register is not implemented in the Cadence PCIe Controller. This field is hardwired to 0." newline bitfld.long 0x0 15. "PMES,This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.." "0,1" newline bitfld.long 0x0 8. "PE,This bit can be set or cleared from the local management APB bus by writing a 1 or 0 respectively." "0,1" newline rbitfld.long 0x0 3. "NSR,This bit is set to 1 by default. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write." "0,1" newline bitfld.long 0x0 0.--1. "PS,This field can also be read or written from the local management APBbus." "0,1,2,3" rgroup.long 0x90++0x13 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_msi_ctrl_reg,This register is used only when the Controller is configured to support Message Signaled" rbitfld.long 0x0 24. "MC,can be modified using localmanagement interface" "0,1" newline rbitfld.long 0x0 23. "BAC64,Set to 1 to indicate that the device is capable of generating 64-bit addresses for MSI messages.Can be modified using local management interface" "0,1" newline bitfld.long 0x0 20.--22. "MME,Encodes the number of distinct messages that the Controller is programmed to generate for this Function [000 = 1 001 = 2 010 = 4 011 = 8 100 = 16 101 = 32]. This setting must be based on the number of interrupt inputs of the.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 17.--19. "MMC,Encodes the number of distinct messages that the Controller is capable of generating for this Function [000 = 1 001 = 2 010 = 4 011 = 8 100 = 16 101 = 32]. Thus this field defines the number of the interrupt vectors for this.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "ME,Set by the configuration program to enable the MSI feature. This field can also be written from the local management bus." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "CP1,Pointer to the next PCI Capability Structure. This can be modified from the local management bus. This field can be written from the local management bus." newline hexmask.long.byte 0x0 0.--7. 1. "CID1,Specifies that the capability structure is for MSI. Hardwired to 05 hex." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_msi_msg_low_addr,This register contains the first 32 bits of the address to be used in the MSI messages" hexmask.long 0x4 2.--31. 1. "MAL,Lower bits of the address to be used in MSI messages. This field can also be written from the local management bus." newline rbitfld.long 0x4 0.--1. "R1,The two lower bits of the address are hardwired to 0 to align the address on a double-word boundary." "0,1,2,3" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_msi_msg_hi_addr,This register contains the most significant 32 bits of the 64-bit address sent by the" hexmask.long 0x8 0.--31. 1. "MAH,Contains bits 63:32 of the 64-bit address to be used in MSI Messages. A value of 0 specifies that 32-bit addresses are to be used in the messages. This field can also be written from the local management bus." line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_i_msi_msg_data,This register contains the write data to be used in the MSI messages to be generated for" hexmask.long.word 0xC 16.--31. 1. "R2,Hardwired to 0" newline hexmask.long.word 0xC 0.--15. 1. "MD,Message data to be used for this Function. This field can also be written from the local management bus." line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_i_msi_mask,This register contains the MSI mask bits. one for each of the interrupt levels." bitfld.long 0x10 0. "MM,Mask bits for MSI interrupts. The Multiple Message Capable field of the MSI Control Register specifies the number of distinct interrupts for the Function which determines the number of valid mask bits." "0,1" rgroup.long 0xA4++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_msi_pending_bits,This register contains the MSI pending interrupt bits. one for each of the interrupt" bitfld.long 0x0 0. "MP,Pending bits for MSI interrupts. This field can be written from the APB interface to refelct the current pending status." "0,1" rgroup.long 0xB0++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_msix_ctrl,This register contains the MSI-X configuration bits. the Capability ID for MSI-X and the" bitfld.long 0x0 31. "MSIXE,Set by the configuration program to enable the MSI-X feature. This field can also be written from the local management bus." "0,1" newline bitfld.long 0x0 30. "FM,This bit serves as a global mask to all the interrupt conditions associated with this Function. When this bit is set the Controller will not send out MSI-X messages from this Function. This field can also be written from the local.." "0,1" newline hexmask.long.word 0x0 16.--26. 1. "MSIXTS,Specifies the size of the MSI-X Table that is the number of interrupt vectors defined for the Function. The programmed value is 1 minus the size of the table [that is this field is set to 0 if the table size is 1.]. It can be.." newline hexmask.long.byte 0x0 8.--15. 1. "CP,Contains pointer to the next PCI Capability Structure. This is set to point to the PCI Express Capability Structure at 30 hex. This can be rewritten independently for each Function from the local management bus." newline hexmask.long.byte 0x0 0.--7. 1. "CID,Identifies that the capability structure is for MSI-X. This field is set by default to 11 hex. It can be rewritten independently for each Function from the local management bus." rgroup.long 0xB4++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_msix_tbl_offset,This register is used to specify the location of the MSI-X Table in memory. All the 32" hexmask.long 0x0 3.--31. 1. "TO,Offset of the memory address where the MSI-X Table is located relative to the selected BAR. The three least significant bits of the address are omitted as the addresses are QWORD aligned. Please see the define.." newline bitfld.long 0x0 0.--2. "BARI,Identifies the BAR corresponding to the memory address range where the MSI-X Table is located [000 = BAR 0 001 = BAR 1 ... 101 = BAR 5]. Please see the define den_db_Fx_MSIX_TABLE_BIR values [where x is the function number] for.." "0: BAR 0,1: BAR 1,?,?,?,?,?,?" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_msix_pending_intrpt,This register is used to specify the location of the MSI-X Pending Bit Array (PBA). The" hexmask.long 0x4 3.--31. 1. "PBAO,Offset of the memory address where the PBA is located relative to the selected BAR. The three least significant bits of the address are omitted as the addresses are QWORD aligned. Please see the define den_db_Fx_MSIX_PBA_OFFSET.." newline bitfld.long 0x4 0.--2. "BARI1,Identifies the BAR corresponding to the memory address range where the PBA Structure is located [000 = BAR 0 001 = BAR 1 ... 101 = BAR 5]. The value programmed must be the same as the BAR Indicator configured in the MSI-X Table.." "0: BAR 0,1: BAR 1,?,?,?,?,?,?" rgroup.long 0xC0++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_pcie_cap_list,This location identifies the PCI Express device type and its capabilities. It also" bitfld.long 0x0 30. "TRS,When set to 1 this bit indicates that the device supports routing of Trusted Configuration Requests. Not valid for Endpoints. Hardwired to 0." "0,1" newline hexmask.long.byte 0x0 25.--29. 1. "IMN,Identifies the MSI or MSI-X interrupt vector for the interrupt message generated corresponding to the status bits in the Slot Status Register Root Status Register or this capability structure. This field must be defined based on the.." newline bitfld.long 0x0 24. "SI,When Set this bit indicates that the Link associated with this Port is connected to a slot" "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "DT,Indicates the type of device implementing this Function. This field is hardwired to 4 in the RP mode." newline hexmask.long.byte 0x0 16.--19. 1. "PCV,Identifies the version number of the capability structure. This field is set to 2 by default to indicate that the Controller is compatible to PCI Express Base Specification Revision 3.0. Can be modified using local management interface.." newline hexmask.long.byte 0x0 8.--15. 1. "NCP,Points to the next PCI capability structure. Set to 0 because this is the last capability structure." newline hexmask.long.byte 0x0 0.--7. 1. "CID,Specifies Capability ID assigned by PCI SIG for this structure. This field is hardwired to 10 hex." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_pcie_cap,This register advertises the capabilities of the PCI Express device." bitfld.long 0x4 28. "FLRC,A value of 1b indicates the Function supports the optional Function Level Reset mechanism" "0,1" newline bitfld.long 0x4 26.--27. "CPLS,Specifies the scale used by Slot Power Limit Value. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. ." "0,1,2,3" newline hexmask.long.byte 0x4 18.--25. 1. "CSP,Specifies upper limit on power supplied by slot. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. ." newline bitfld.long 0x4 15. "RER,Enables role-based errer reporting. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write." "0,1" newline bitfld.long 0x4 9.--11. "AL1L,Specifies acceptable latency that the Endpoint can tolerate while transitioning from L1 to L0. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6.--8. "AL0L,Specifies acceptable latency that the Endpoint can tolerate while transitioning from L0S to L0. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 5. "ETFS,hard coded to zero ." "0,1" newline bitfld.long 0x4 3.--4. "PFS,This field is used to extend the tag field by combining unused Function bits with the tag bits. This field is hardwired to 00 to disable this feature." "0,1,2,3" newline bitfld.long 0x4 0.--2. "MP,Specifies maximum payload size supported by the device. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write." "0,1,2,3,4,5,6,7" rgroup.long 0xC8++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_pcie_dev_ctrl_status,This register contains control and status bits associated with the device." hexmask.long.word 0x0 22.--31. 1. "R8,N/A" newline rbitfld.long 0x0 21. "TP,Indicates if any of the Non-Posted requests issued by the RC are still pending." "0,1" newline rbitfld.long 0x0 20. "APD,Set when auxiliary power is detected by the device. This is an unused field." "0,1" newline bitfld.long 0x0 19. "URD,Set to 1 by the Controller when it receives an unsupported request." "0,1" newline bitfld.long 0x0 18. "FED,Set to 1 by the Controller when it detects a fatal error regardless of whether the error is masked." "0,1" newline bitfld.long 0x0 17. "NFED,Set to 1 by the Controller when it detects a non-fatal error regardless of whether the error is masked." "0,1" newline bitfld.long 0x0 16. "CED,Set to 1 by the Controller when it detects a correctable error regardless of whether the error is masked." "0,1" newline rbitfld.long 0x0 15. "R7,Hardwired to 0." "0,1" newline bitfld.long 0x0 12.--14. "MRR,Specifies the maximum size allowed in read requests generated by the device." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "ENS,If this bit is Set the Function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency." "0,1" newline rbitfld.long 0x0 10. "APPME,Hardwired to 0" "0,1" newline rbitfld.long 0x0 9. "PFE,Hardwired to 0" "0,1" newline rbitfld.long 0x0 8. "ETE,extended tag not enabled. Hence hard coded to zero ." "0,1" newline bitfld.long 0x0 5.--7. "MP,Specifies the maximum TLP payload size configured. The device must be able to receive a TLP of this maximum size and should not generate TLP's larger than this value. Software must set this field based on the maximum payload size in the.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "ERO,When set this bit indicates that the device is allowed to set the Relaxed Ordering bit in the Attributes field of transactions initiated from it. when the transactions do not require Strong Ordering." "0,1" newline bitfld.long 0x0 3. "EURR,This bit is used to gate the CORRECTABLE_ERROR_OUT NON_FATAL_ERROR_OUT FATAL_ERROR_OUT output in Root Port mode on receiving unsupported requests. Note: Alternately the SERR Enable bit in the Command Register can also be set to.." "0,1" newline bitfld.long 0x0 2. "EFER,This bit is used to gate the FATAL_ERROR_OUT output of the Controller in Root Port mode. When an Uncorrectable Unmasked Error with Uncorrectable Error Severity set to 1 is detected Internally or when a ERR_FATAL message is received by.." "0,1" newline bitfld.long 0x0 1. "ENFER,This bit is used to gate the NON_FATAL_ERROR_OUT output of the Controller in Root Port mode. When an Uncorrectable Unmasked Error with Uncorrectable Error Severity set to 0 is detected Internally or when a ERR_NON_FATAL message is.." "0,1" newline bitfld.long 0x0 0. "ECER,This bit is used to gate the CORRECTABLE_ERROR_OUT output of the Controller in Root Port mode. When a Correctable and Unmasked Error is detected Internally or when a ERR_CORR message is received by the Controller in Root.." "0,1" rgroup.long 0xCC++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_link_cap,This register advertises the link-specific capabilities of the device incorporating the" hexmask.long.byte 0x0 24.--31. 1. "PN,Specifies the port number assigned to the PCI Express link connected to this device. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write." newline bitfld.long 0x0 22. "ASPMOC,A 1 in this position indicates the device supports the ASPM Optionality feature. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write." "0,1" newline bitfld.long 0x0 21. "LBNC,A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management.." "0,1" newline bitfld.long 0x0 20. "DARC,Set to 1 if the device is capable of reporting that the DL Control and Management State Machine has reached the DL_Active state. This bit is hardwired to 0 as this version of the Controller does not support the feature." "0,1" newline bitfld.long 0x0 19. "SERC,Indicates the capability of the device to report a Surprise Down error condition. This bit is hardwired to 0 as this version of the Controller does not support the feature." "0,1" newline bitfld.long 0x0 18. "CPM,Indicates that the device supports removal of reference clocks. Not supported in this version of the Controller. Hardwired to 0." "0,1" newline bitfld.long 0x0 15.--17. "L1EL,Specifies the exit latency from L1 state. This parameter is dependent on the Physical Layer implementation. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "L0EL,Specifies the time required for the device to transition from L0S to L0. This parameter is dependent on the Physical Layer implementation. This field can be written from the APB bus by setting [21] bit high of the.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10.--11. "ASPM,Indicates the level of ASPM support provided by the device. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write." "0,1,2,3" newline hexmask.long.byte 0x0 4.--9. 1. "MLW,Indicates the maximum number of lanes supported by the device. This field is hardwired based on the setting of the LANE_COUNT_IN strap input." newline hexmask.long.byte 0x0 0.--3. 1. "MLS,Indicates the speeds supported by the link [2.5 GT/s 5 GT/s 8 GT/s 16 GT/s per lane]. This field is hardwired to 0001 [2.5GT/s] when the strap input PCIE_GENERATION_SEL is set to 0 to 0010 [5 GT/s] when.." rgroup.long 0xD0++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_link_ctrl_status,This register contains control and status bits specific to the PCI Express link." bitfld.long 0x0 31. "LABS,This bit is Set by hardware to indicate that hardware has autonomously changed Link speed or width without the Port transitioning through DL_Down status for reasons other than to attempt to correct.." "0,1" newline bitfld.long 0x0 30. "LBMS,This bit is Set by hardware to indicate that either link training has completed following write to retrain link bit or when HW has changed link speed or width to attempt to correct unreliable link operation." "0,1" newline rbitfld.long 0x0 29. "DA,Indicates the status of the Data Link Layer. Set to 1 when the DL Control and Management State Machine has reached the DL_Active state. This bit is hardwired to 0 in this version of the Controller." "0,1" newline rbitfld.long 0x0 28. "SCC,Indicates that the device uses the reference clock provided by the connector. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write." "0,1" newline rbitfld.long 0x0 27. "LTS,This bit is set to 1 when the LTSSM is in the Recovery or Configuration states or if a 1 has been written to the Retrain Link bit but the link training has not yet begun." "0,1" newline hexmask.long.byte 0x0 20.--25. 1. "NLW,Set at the end of link training to the actual link width negotiated between the two sides." newline hexmask.long.byte 0x0 16.--19. 1. "NLS,Negotiated link speed of the device. The only supported speed ids are 2.5 GT/s per lane [0001] 5 GT/s per lane [0010] 8 GT/s per lane [0011] 16 GT/s per lane [0100]." newline bitfld.long 0x0 11. "LABIE,When Set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been Set. This enables an interrupt to be generated through PHY_INTERRUPT_OUT if triggered." "0,1" newline bitfld.long 0x0 10. "LBMIE,When Set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been Set. This enables an interrupt to be generated through PHY_INTERRUPT_OUT if triggered." "0,1" newline bitfld.long 0x0 9. "HAWD,When this bit is set the local application must not request to change the operating width of the link other than attempting to correct unreliable Link operation by reducing Link width." "0,1" newline rbitfld.long 0x0 8. "ECPM,This field is hardwired to 0 when the Controller is in the RC mode." "0,1" newline bitfld.long 0x0 7. "ES,Set to 1 to extend the sequence of ordered sets transmitted while exiting from the L0S state." "0,1" newline bitfld.long 0x0 6. "CCC,A value of 0 indicates that the reference clock of this device is asynchronous to that of the upstream device. A value of 1 indicates that the reference clock is common." "0,1" newline rbitfld.long 0x0 5. "RL,Setting this bit to 1 causes the LTSSM to initiate link training. This bit always reads as 0. This bit can be set by Host SW at any time independent of the LTSSM state. If the LTSSM is not in L0 state the Controller will internally.." "0,1" newline bitfld.long 0x0 4. "LD,Writing a 1 to this bit position causes the LTSSM to go to the Disable Link state. The LTSSM stays in the Disable Link state while this bit is set." "0,1" newline rbitfld.long 0x0 3. "RCB,Indicates the Read Completion Boundary of the Root Port [0 = 64 bytes 1 = 128 bytes]. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write." "0,1" newline bitfld.long 0x0 0.--1. "ASPMC,Controls the level of ASPM support on the PCI Express link associated with the function. The valid setting are 00: ASPM disabled 01: L0s entry enabled L1 disabled 10: L1 entry enabled L0s disabled 11: Both L0s and L1 enabled." "0: ASPM disabled,1: L0s entry enabled,?,?" rgroup.long 0xD4++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_slot_capability,The Slot Capabilities register identifies PCI Express slot specific capabilities." hexmask.long.word 0x0 19.--31. 1. "PSN,This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis regardless of the form.." newline bitfld.long 0x0 18. "NCCS,When Set this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be Set if the hot-plug.." "0,1" newline bitfld.long 0x0 17. "EIP,When Set this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot." "0,1" newline bitfld.long 0x0 15.--16. "SPLS,Specifies the scale used for the Slot Power Limit Value . Range of Values: 00b = 1.0x 01b = 0.1x 10b = 0.01x 11b = 0.001x This register must be implemented if the.." "0,1,2,3" newline hexmask.long.byte 0x0 7.--14. 1. "SPLV,In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by the slot [see Section 6.9] or by other means to the adapter. Power limit [in Watts] is calculated by.." newline bitfld.long 0x0 6. "HPC,When Set this bit indicates that this slot is capable of supporting hot-plug operations." "0,1" newline bitfld.long 0x0 5. "HPS,When Set this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the.." "0,1" newline bitfld.long 0x0 4. "PIP,When Set this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot." "0,1" newline bitfld.long 0x0 3. "AIP,When Set this bit indicates that an Attention Indicator is electrically controlled by the chassis." "0,1" newline bitfld.long 0x0 2. "MRLSP,When Set this bit indicates that an MRL Sensor is implemented on the chassis for this slot." "0,1" newline bitfld.long 0x0 1. "PCP,When Set this bit indicates that a software programmable Power Controller is implemented for this slot/adapter [depending on form factor]." "0,1" newline bitfld.long 0x0 0. "ABPRSNT,When Set this bit indicates that an Attention Button for this slot is electrically controlled by the chassis." "0,1" rgroup.long 0xD8++0xB line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_slot_ctrl_status,This register contains control bits specific to PCI Express slot parameters and status" hexmask.long.byte 0x0 25.--31. 1. "RSCS2,N/A" newline bitfld.long 0x0 24. "DLLSC,This bit is Set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed. In response to a Data Link Layer State Changed event software must read.." "0,1" newline rbitfld.long 0x0 23. "EMIS,If an Electromechanical Interlock is implemented this bit indicates the status of the Electromechanical Interlock. Defined encodings are: 0b Electromechanical Interlock Disengaged.." "0,1" newline rbitfld.long 0x0 22. "PDS,This bit indicates the presence of an adapter in the slot reflected by the logical 'OR' of the Physical Layer in-band presence detect mechanism and if present any out-of-band presence detect mechanism.." "0,1" newline rbitfld.long 0x0 21. "MRLSS,This bit reports the status of the MRL sensor if implemented. Defined encodings are: 0b MRL Closed 1b MRL Open" "0,1" newline bitfld.long 0x0 20. "CMDCMPL,If Command Completed notification is supported [if the No Command Completed Support bit in the Slot Capabilities register is 0b] this bit is Set when a hot-plug command has completed and the Hot-Plug.." "0,1" newline bitfld.long 0x0 19. "PDC,This bit is set when the value reported in the Presence Detect State bit is changed." "0,1" newline bitfld.long 0x0 18. "MRLSC,If an MRL sensor is implemented this bit is Set when a MRL Sensor state change is detected. If an MRL sensor is not implemented this bit must not be Set." "0,1" newline bitfld.long 0x0 17. "PFD,If a Power Controller that supports power fault detection is implemented this bit is Set when the Power Controller detects a power fault at this slot. Note that depending on hardware capability it is.." "0,1" newline bitfld.long 0x0 16. "ABPRSD,If an Attention Button is implemented this bit is Set when the attention button is pressed. If an Attention Button is not supported this bit must not be Set." "0,1" newline bitfld.long 0x0 12. "DLLSCE,If the Data Link Layer Link Active Reporting capability is 1b this bit enables software notification when Data Link Layer Link Active bit is changed. If the Data Link Layer Link Active Reporting Capable bit is 0b .." "0,1" newline rbitfld.long 0x0 11. "EMIC,If an Electromechanical Interlock is implemented a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit always returns a 0b." "0,1" newline bitfld.long 0x0 10. "PCC,If a Power Controller is implemented this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write even if the.." "0,1" newline bitfld.long 0x0 8.--9. "PIC,If a Power Indicator is implemented writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write Defined encodings are: 00b Reserved.." "0,1,2,3" newline bitfld.long 0x0 6.--7. "AIC,If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write Defined encodings are:.." "0,1,2,3" newline bitfld.long 0x0 5. "HPIE,When Set this bit enables generation of an interrupt on enabled hot-plug events. If the Hot Plug Capable bit in the Slot Capabilities register is Clear this bit is permitted to be read-only with a value of 0b." "0,1" newline bitfld.long 0x0 4. "CCIE,If Command Completed notification is supported [if the No Command Completed Support bit in the Slot Capabilities register is 0b] when Set this bit enables software notification when a hot-plug command is.." "0,1" newline bitfld.long 0x0 3. "PDCE,When Set this bit enables software notification on a presence detect changed event. If the Hot-Plug Capable bit in the Slot Capabilities register is 0b this bit is permitted to be read-only with a value of 0b." "0,1" newline bitfld.long 0x0 2. "MSCE,When Set this bit enables software notification on a MRL sensor changed event If the MRL Sensor Present bit in the Slot Capabilities register is Clear this bit is permitted to be read-only with a value of.." "0,1" newline bitfld.long 0x0 1. "PFDE,When Set this bit enables software notification on a power fault event If a Power Controller that supports power fault detection is not implemented this bit is permitted to be read-only with a value of.." "0,1" newline bitfld.long 0x0 0. "ABPE,When Set to 1b this bit enables software notification on an attention button pressed event. If the Attention Button Present bit in the Slot Capabilities register is 0b this bit is permitted to be read-only.." "0,1" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_root_ctrl_cap,This register controls and identifies PCI Express Root Complex specific parameters." rbitfld.long 0x4 4. "CRSSVE,This capability is not implemented and this bit is hardwired to 0b." "0,1" newline bitfld.long 0x4 3. "PMEIE,This field can be read and written from the local management APB bus but its value is not used within the Controller." "0,1" newline bitfld.long 0x4 2. "SEFEE,This field can be read and written from the local management APB bus but its value is not used within the Controller." "0,1" newline bitfld.long 0x4 1. "SENFEE,This field can be read and written from the local management APB bus but its value is not used within the Controller." "0,1" newline bitfld.long 0x4 0. "SECEE,This field can be read and written from the local management APB bus but its value is not used within the Controller." "0,1" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_root_status,This register controls and identifies PCI Express Root Complex specific parameters." rbitfld.long 0x8 17. "PMEP,This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write." "0,1" newline bitfld.long 0x8 16. "PMES,This field is not set by the Controller but can be cleared by writing a 1 from the local management APB bus. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local.." "0,1" newline hexmask.long.word 0x8 0.--15. 1. "PMERID,This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write." rgroup.long 0xE4++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_pcie_cap_2,This register advertises the capabilities of the PCI Express device." bitfld.long 0x0 22.--23. "MEEP,Indicates the maximum number of End-End TLP Prefixes supported by the Function. The supported values are: 01b 1 End-End TLP Prefix 10b 2 End-End TLP Prefixes. This field can be written from the APB bus by setting [21] bit high of.." "0,1,2,3" newline bitfld.long 0x0 21. "EEPS,Indicates whether the Function supports End-End TLP Prefixes. A 1 in this field indicates that the Function supports receiving TLPs containing End-End TLP Prefixes. This field can be written from the APB bus by setting [21] bit.." "0,1" newline bitfld.long 0x0 20. "EXFS,Indicates that the Function supports the 3-bit definition of the Fmt field in the TLP header. This bit is hardwired to 1 for all Physical Functions." "0,1" newline bitfld.long 0x0 18.--19. "OBFF,A 1 in this bit position indicates that the Function supports the Optimized Buffer Flush/Fill [OBFF] capability using message signaling. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR.." "0,1,2,3" newline bitfld.long 0x0 17. "T10RS,If set function supports 1-bit requester capability; otherwise the function does not. This bit can be disabled using local management register." "?,1: bit requester capability; otherwise" newline bitfld.long 0x0 16. "T10CS,If set function supports 1-bit completer capability; otherwise the function does not. This field can be modified using local management interface." "?,1: bit completer capability; otherwise" newline bitfld.long 0x0 12. "TPHC,Hardwired to 0." "0,1" newline bitfld.long 0x0 11. "LMS,A value of 1b indicates support for the optional Latency Tolerance Reporting [LTR] mechanism. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register.." "0,1" newline bitfld.long 0x0 9. "ACS128,Hardwired to 0." "0,1" newline bitfld.long 0x0 8. "ACS64,Hardwired to 0." "0,1" newline bitfld.long 0x0 7. "ACS32,Hardwired to 0." "0,1" newline bitfld.long 0x0 6. "AOPRS,Applicable only to Switch Upstream Ports Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. This field can be written from.." "0,1" newline bitfld.long 0x0 5. "AFS,A 1 in this bit indicates that the device is able to forward TLPs with function number greater than 8. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register.." "0,1" newline bitfld.long 0x0 4. "CTDS,A 1 in this field indicates that the associated Function supports the capability to turn off its Completion timeout. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a.." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "CTR,Specifies the Completion Timeout values supported by the device. This field is set by default to 0010 [10 ms - 250 ms] but can be modified from the local management APB bus. The actual timeout values are in two programmable local.." rgroup.long 0xE8++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_pcie_dev_ctrl_status_2,This register contains control and status bits associated with the device." hexmask.long.tbyte 0x0 15.--31. 1. "R20,N/A" newline bitfld.long 0x0 13.--14. "OBFFE,Enables the Optimized Buffer Flush/Fill [OBFF] capability in the device. Valid settings are 00 [disabled] 01 [Variation A] and 10 [Variation B]." "0,1,2,3" newline rbitfld.long 0x0 12. "T10RE,10bit TAGs generation are not supported in this configuration." "0,1" newline bitfld.long 0x0 10. "LTRME,This must be set to 1 to enable the Latency Tolerance Reporting Mechanism. This bit is implemented only in PF 0. Its default value is 1 but can be modified from the local management bus. This bit is read-only in PF 1." "0,1" newline bitfld.long 0x0 9. "ICE,When this bit is 1 the RC is allowed to set the ID-based Ordering [IDO] Attribute bit in the Completions it generates." "0,1" newline bitfld.long 0x0 8. "IRE,When this bit is 1 the RC is allowed to set the ID-based Ordering [IDO] Attribute bit in the requests it generates." "0,1" newline rbitfld.long 0x0 6. "AORE,This bit must be set to enable the generation of Atomic Op Requests. If the client logic attempts to send an Atomic Op when this bit is not set logic in the Controller will nullify the TLP on its way to the link." "0,1" newline bitfld.long 0x0 5. "AFE,A 1 in this filed indicates that the port treats fields 7:0 of the ID as function number while converting a Type 1 config packet to type 0 config packet." "0,1" newline bitfld.long 0x0 4. "CTD,Setting this bit disables the Completion Timeout in the device." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "CTV,Specifies the Completion Timeout value for the device. Allowable values are 0101 [sub-range 1] and 0110 [sub-range 2]. The corresponding timeout values are stored in the local management register's Completion Timeout Interval Registers 0.." rgroup.long 0xEC++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_link_cap_2,This register advertises the supported link speeds of the Controller." bitfld.long 0x0 31. "R31,Indicates support for the optional Device Readiness Status [DRS] capability. This capability is currently not supported in the Controller." "0,1" newline bitfld.long 0x0 24. "TWRTPDS,When set to 1b this bit indicates that the associated Port supports detection and reporting of two Retimers presence. This bit is valid for both Downstream Ports and Upstream Ports." "0,1" newline bitfld.long 0x0 23. "RTPDS,When set to 1b this bit indicates that the associated Port supports detection and reporting of Retimer presence. This bit is valid for both Downstream Ports and Upstream Ports." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "LSORSSV,If this field is non-zero it indicates that the Port when operating at the indicated speed[s] supports SRIS and also supports receiving SKP OS at the rate defined for SRNS while running in SRIS." newline hexmask.long.byte 0x0 9.--12. 1. "LSOGSSV,If this field is non-zero it indicates that the Port when operating at the indicated speed[s] supports SRIS and also supports software control of the SKP Ordered Set transmission scheduling rate." newline hexmask.long.byte 0x0 1.--4. 1. "SLSV,This field indicates the supported link speeds of the Controller. For each bit a value of 1 indicates that the corresponding link speed is supported while a value of 0 indicates that the corresponding speed is not supported." rgroup.long 0xF0++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_link_ctrl_status_2,This register contains control and status bits specific to the PCI Express link." rbitfld.long 0x0 31. "DMR,DRS is not supported by the Controller and hence this field is not implemented." "0,1" newline rbitfld.long 0x0 28.--30. "DCP,DRS is not supported by the Controller and hence this field is not implemented." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 23. "TWRTP,When set to 1b this bit indicates that two Retimers were present during the most recent Link negotiation." "0,1" newline rbitfld.long 0x0 22. "RTP,When set to 1b this bit indicates that a Retimer was present during the most recent Link negotiation." "0,1" newline bitfld.long 0x0 21. "LE,When the Controller [RP] receives an 8GTs equalization request from an Upstream Port the Controller internally sets this bit to 1. [i.e. when RP is in the Recovery.RcvrCfg state and receives 8 consecutive TS2 Ordered Sets with the.." "0,1" newline rbitfld.long 0x0 20. "EP3S,This bit when set to 1 indicates that the Phase 3 of the Transmitter Equalization procedure has completed successfully. STICKY" "0,1" newline rbitfld.long 0x0 19. "EP2S,This bit when set to 1 indicates that the Phase 2 of the Transmitter Equalization procedure has completed successfully. STICKY" "0,1" newline rbitfld.long 0x0 18. "EP1S,This bit when set to 1 indicates that the Phase 1 of the Transmitter Equalization procedure has completed successfully. STICKY" "0,1" newline rbitfld.long 0x0 17. "EQC,This bit when set to 1 indicates that the Transmitter Equalization procedure has completed. STICKY" "0,1" newline rbitfld.long 0x0 16. "CDEL,This status bit indicates the current operating de-emphasis level of the transmitter [0 = -6dB 1 = -3.5dB]." "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CD,This bit sets the de-emphasis level [for 5 GT/s operation] or the Transmitter Preset level [for 8 GT/s or 16 GT/s operation] when the LTSSM enters the Polling.Compliance state because of software setting the Enter Compliance bit in this.." newline bitfld.long 0x0 11. "CS,When this bit is set to 1 the device will transmit SKP ordered sets between compliance patterns. STICKY" "0,1" newline bitfld.long 0x0 10. "EMC,This field is intended for debug and compliance testing purposes only. If this bit is set to 1 the device will transmit the Modified Compliance Pattern when the LTSSM enters the Polling.Compliance substate. STICKY" "0,1" newline bitfld.long 0x0 7.--9. "TM,This field is intended for debug and compliance testing purposes only. It controls the non-deemphasized voltage level at the transmitter outputs. Its encodings are: 000 = Normal operating range 001 = 800 - 1200 mV for full swing and 400 -.." "0: Normal operating range,?,?,?,?,?,?,?" newline bitfld.long 0x0 6. "SD,This bit selects the de-emphasis level when the Controller is operating at 5 GT/s [0 = -6 dB 1 = -3.5 dB]." "0,1" newline bitfld.long 0x0 5. "HASD,When this bit is set the LTSSM is prevented from changing the operating speed of the link other than reducing the speed to correct unreliable operation of the link. STICKY" "0,1" newline bitfld.long 0x0 4. "EC,This bit is used to force the Endpoint device to enter the Compliance mode. Software sets this bit to 1 and initiates a hot reset to force the device into the Compliance mode. The target speed for the Compliance mode is determined by the.." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "TLS,This field sets the target speed when the software forces the link into Compliance mode by setting the Enter Compliance bit in this register [0001 = 2.5 GT/s 0010 = 5 GT/s 0100 = 8 GT/s 1000 = 16 GT/s]. The default value of this field.." rgroup.long 0x100++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_AER_enhncd_cap,This is the first register in the PCI Express Advanced Error Reporting Capability" hexmask.long.word 0x0 20.--31. 1. "NCO,Indicates offset to the next PCI Express capability structure. The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set." newline hexmask.long.byte 0x0 16.--19. 1. "CV,Specifies the SIG assigned value for the version of the capability structure. This field is set by default to 4'h2." newline hexmask.long.word 0x0 0.--15. 1. "PECID,This field is hardwired to the Capability ID assigned by PCI SIG to the PCI Express AER Extended Capability Structure [0001 hex]." rgroup.long 0x104++0x17 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_uncorr_err_status,This register provides the status of the various uncorrectable errors detected by the" bitfld.long 0x0 22. "UIE,This bit is set when the Controller has detected an internal uncorrectable error [HAL parity error or an uncorrectable ECC error while reading from any of the RAMs]. This bit is also set in response to the client signaling an internal.." "0,1" newline bitfld.long 0x0 20. "URE,This bit is set when the Controller has received a request from the link that it does not support. This error is not Function-specific. This error is considered non-fatal by default except for the special case outlined in PCI Express.." "0,1" newline bitfld.long 0x0 19. "EE,This bit is set when the Controller has detected an ECRC error in a received TLP." "0,1" newline bitfld.long 0x0 18. "MT,This bit is set when the Controller receives a malformed TLP from the link. This error is considered fatal by default. The header of the received TLP with error is logged in the Header Log Registers." "0,1" newline bitfld.long 0x0 17. "RO,This bit is set when the Controller receives a TLP in violation of the receive credit currently available." "0,1" newline bitfld.long 0x0 16. "UC,This bit is set when the Controller has received an unexpected Completion packet from the link." "0,1" newline bitfld.long 0x0 15. "CA,This bit is set when the Controller has returned the Completer Abort [CA] status to a request received from the link. This error is considered non-fatal by default except for the special cases outlined in PCI Express Base Specification.." "0,1" newline bitfld.long 0x0 14. "CT,This bit is set when the completion timer associated with an outstanding request times out. This error is considered non-fatal by default." "0,1" newline bitfld.long 0x0 13. "FCPE,This bit is set when certain violations of the flow control protocol are detected by the Controller." "0,1" newline bitfld.long 0x0 12. "PT,This bit is set when the Controller receives a poisoned TLP from the link. This error is considered non-fatal by default. The header of the received TLP with error is logged in the Header Log Registers." "0,1" newline bitfld.long 0x0 5. "SDES,This error status indicates Link up to Link down event. So Status bit is set upon LINK_DOWN_RESET_OUT event. This field is applicable to RC only and not for EP as per PCIE-spec." "0,1" newline bitfld.long 0x0 4. "DLPE,This bit is set when the Controller receives an Ack or Nak DLLP whose sequence does not correspond to that of an unacknowledged TLP or that of the last acknowledged TLP [for details refer to the PCI Express Base Specifications]." "0,1" newline rbitfld.long 0x0 1.--3. "R25,N/A" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "LTE,This error indicates that link training is not successful and transition back to detect state. This Status bit is set on any LTSSM transition from Configuration to Detect or Recovery to Detect. This field is applicable to RC only.." "0,1" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_uncorr_err_mask,The mask bits in this register control the reporting of uncorrectable errors. For each" bitfld.long 0x4 22. "UIEM,This bit is set to mask the reporting of internal errors. STICKY." "0,1" newline bitfld.long 0x4 20. "UREM,This bit is set to mask the reporting of unexpected requests received from the link. STICKY." "0,1" newline bitfld.long 0x4 19. "EEM,This bit is set to mask the reporting of ECRC errors. STICKY." "0,1" newline bitfld.long 0x4 18. "MTM,This bit is set to mask the reporting of malformed TLPs received from the link. STICKY." "0,1" newline bitfld.long 0x4 17. "ROM,This bit is set to mask the reporting of violations of receive credit. STICKY." "0,1" newline bitfld.long 0x4 16. "UCM,This bit is set to mask the reporting of unexpected Completions received by the Controller. STICKY." "0,1" newline bitfld.long 0x4 15. "CAM,This bit is set to mask the reporting of the Controller sending a Completer Abort. STICKY." "0,1" newline bitfld.long 0x4 14. "CTM,This bit is set to mask the reporting of Completion Timeouts. STICKY." "0,1" newline bitfld.long 0x4 13. "FCPER,This bit is set to mask the reporting of Flow Control Protocol Errors. STICKY." "0,1" newline bitfld.long 0x4 12. "PTM,This bit is set to mask the reporting of a Poisoned TLP. STICKY." "0,1" newline bitfld.long 0x4 5. "SDESM,This bit is set to mask the reporting of Surprise Down Error Status Mask. STICKY. This field is applicable to RC only and not for EP as per PCIE-spec." "0,1" newline bitfld.long 0x4 4. "DLPER,This bit is set to mask the reporting of Data Link Protocol Errors. STICKY." "0,1" newline bitfld.long 0x4 0. "LTEM,This bit is set to mask the reporting of Link Training Error Mask. STICKY. This field is applicable to RC only and not for EP as per PCIE-spec." "0,1" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_uncorr_err_severity,The setting of this register determines whether an uncorrectable error is reported as a" hexmask.long.word 0x8 23.--31. 1. "R37,N/A" newline bitfld.long 0x8 22. "UNCORR_INTRNL_ERR_SVRTY,Severity of internal errors [0 = Non-Fatal 1 = Fatal]." "0: Non-Fatal,1: Fatal]" newline bitfld.long 0x8 20. "URES,Severity of unexpected requests received from the link [0 = Non-Fatal 1 = Fatal]. STICKY." "0: Non-Fatal,1: Fatal]" newline bitfld.long 0x8 19. "EES,Severity of ECRC errors [0 = Non-Fatal 1 = Fatal]. STICKY." "0: Non-Fatal,1: Fatal]" newline bitfld.long 0x8 18. "MTS,Severity of malformed TLPs received from the link [0 = Non-Fatal 1 = Fatal]. STICKY." "0: Non-Fatal,1: Fatal]" newline bitfld.long 0x8 17. "ROS,Severity of receive credit violations [0 = Non-Fatal 1 = Fatal]. STICKY." "0: Non-Fatal,1: Fatal]" newline bitfld.long 0x8 16. "UCS,Severity of unexpected Completions received by the Controller [0 = Non-Fatal 1 = Fatal]. STICKY." "0: Non-Fatal,1: Fatal]" newline bitfld.long 0x8 15. "CAS,Severity of sending a Completer Abort [0 = Non-Fatal 1 = Fatal]. STICKY." "0: Non-Fatal,1: Fatal]" newline bitfld.long 0x8 14. "CTS,Severity of Completion Timeouts [0 = Non-Fatal 1 = Fatal]. STICKY." "0: Non-Fatal,1: Fatal]" newline bitfld.long 0x8 13. "FCPES,Severity of a Flow Control Protocol Error [0 = Non-Fatal 1 = Fatal]. STICKY." "0: Non-Fatal,1: Fatal]" newline bitfld.long 0x8 12. "PTS,Severity of a Poisoned TLP error [0 = Non-Fatal 1 = Fatal]. STICKY." "0: Non-Fatal,1: Fatal]" newline hexmask.long.byte 0x8 6.--11. 1. "R35,N/A" newline bitfld.long 0x8 5. "SDES,surprise down error severity [0 = Non-Fatal 1 = Fatal]. STICKY. This field is applicable to RC only and not for EP as per PCIE-spec." "0: Non-Fatal,1: Fatal]" newline bitfld.long 0x8 4. "DLPES,Severity of Data Link Protocol Errors [0 = Non-Fatal 1 = Fatal]. STICKY." "0: Non-Fatal,1: Fatal]" newline bitfld.long 0x8 0. "LTES,Severity of Link Training Error [0 = Non-Fatal 1 = Fatal]. STICKY. This field is applicable to RC only and not for EP as per PCIE-spec." "0: Non-Fatal,1: Fatal]" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_i_corr_err_status,This register provides the status of the various correctable errors detected by the PCI" bitfld.long 0xC 15. "HLOS,This bit is set on a Header Log Register overflow that is when the header could not be logged in the Header Log Register because it is occupied by a previous header." "0,1" newline bitfld.long 0xC 14. "CIES,This bit is set when the Controller has detected an internal correctable error condition [a correctable ECC error while reading from any of the RAMs]. This bit is also set in response to the client signaling an internal error through the.." "0,1" newline bitfld.long 0xC 13. "ANES,This bit is set when an uncorrectable error occurs which is determined to belong to one of the special cases described in the PCI Express Base Specification 2.0. This causes the Controller to assert the CORRECTABLE_ERROR_OUT output in.." "0,1" newline bitfld.long 0xC 12. "RTTS,This bit is set when the replay timer in the Data Link Layer of the Controller times out causing the Controller to re-transmit a TLP." "0,1" newline bitfld.long 0xC 8. "RNRS,This bit is set when the replay count rolls over after three re-transmissions of a TLP at the Data Link Layer of the Controller." "0,1" newline bitfld.long 0xC 7. "BDS,This bit is set when an LCRC error is detected in a received DLLP and no errors were detected by the Physical Layer." "0,1" newline bitfld.long 0xC 6. "BTS,This bit is set when an error is detected in a received TLP by the Data Link Layer of the Controller the conditions causing this error are [1] an LCRC error [2] the packet terminates with EDB symbol but its LCRC field does not equal the.." "0,1" newline bitfld.long 0xC 0. "RES,This bit is set when an error is detected in the receive side of the Physical Layer of the Controller [e.g. an 8b10b decode error]." "0,1" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_i_corr_err_mask,The mask bits in this register control the reporting of correctable errors. For each" bitfld.long 0x10 15. "HLOM,This bit when set masks the reporting of an error in response to a Header Log register overflow. STICKY." "0,1" newline bitfld.long 0x10 14. "CIEM,This bit when set masks the reporting of an error in response to a corrected internal error condition. STICKY." "0,1" newline bitfld.long 0x10 13. "ANEM,This bit when set masks the reporting of an error in response to an uncorrectable error occurence which is determined to belong to one of the special cases in the PCI Express Base Specification 2.0. STICKY." "0,1" newline bitfld.long 0x10 12. "RTTM,This bit when set masks the reporting of an error in response to a Replay Timer timeout event. STICKY." "0,1" newline bitfld.long 0x10 8. "RNRM,This bit when set masks the reporting of an error in response to a Replay Number Rollover event. STICKY." "0,1" newline bitfld.long 0x10 7. "BDM,This bit when set masks the reporting of an error in response to a 'Bad DLLP' received. STICKY." "0,1" newline bitfld.long 0x10 6. "BTM,This bit when set masks the reporting of an error in response to a 'Bad TLP' received. STICKY." "0,1" newline bitfld.long 0x10 0. "REM,This bit when set masks the reporting of Physical Layer errors. STICKY." "0,1" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_i_adv_err_cap_ctl,This register contains a pointer to the first error that is reported in the" rbitfld.long 0x14 11. "TPLP,If Set and the First Error Pointer is valid indicates that the TLP Prefix Log register contains valid information. If Clear or if First Error Pointer is invalid the TLP Prefix Log register.." "0,1" newline rbitfld.long 0x14 10. "MHRE,Setting this bit enables the RC to log multiple error headers in its Header Log Registers. It is hardwired to 0." "0,1" newline rbitfld.long 0x14 9. "MHRC,This bit is set when the RC has the capability to log more than one error header in its Header Log Registers. It is hardwired to 0." "0,1" newline bitfld.long 0x14 8. "EEC,Setting this bit enables ECRC checking on the receive side of the Controller. This bit is writable from the local management bus. STICKY." "0,1" newline rbitfld.long 0x14 7. "ECC,This read-only bit indicates to the software that the device is capable of checking ECRC in packets received from the link." "0,1" newline bitfld.long 0x14 6. "EEG,Setting this bit enables the ECRC generation on the transmit side of the Controller. This bit is writable from the local management bus. STICKY." "0,1" newline rbitfld.long 0x14 5. "EGC,This read-only bit indicates to the software that the device is capable of generating ECRC in packets transmitted on the link." "0,1" newline hexmask.long.byte 0x14 0.--4. 1. "FEP,This is a 5-bit pointer to the bit position in the Uncorrectable Error Status Register corresponding to the error that was detected first. When there are multiple bits set in the Uncorrectable Error Status Register this field informs the.." rgroup.long 0x11C++0xF line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_hdr_log_0,This is the first of a set of four registers used to capture the header of a TLP" hexmask.long 0x0 0.--31. 1. "HD0,First Dword of captured TLP header. STICKY." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_hdr_log_1,This register contains the second Dword of the captured TLP header. The bytes are stored" hexmask.long 0x4 0.--31. 1. "HD1,Second Dword of captured TLP header. STICKY." line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_hdr_log_2,This register contains the third Dword of the captured TLP header. The bytes are stored" hexmask.long 0x8 0.--31. 1. "HD2,Third Dword of captured TLP header. STICKY." line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_i_hdr_log_3,If the captured TLP header is 4 Dwords long. this register contains its fourth Dword. If" hexmask.long 0xC 0.--31. 1. "HD3,Fourth Dword of captured TLP header. STICKY." rgroup.long 0x12C++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_root_err_cmd,This register contains bits that control how the RC responds to errors reported by" bitfld.long 0x0 2. "FERE,If this bit is set the Controller will active its FATAL_ERROR_OUT output in response to an error message received from the link." "0,1" newline bitfld.long 0x0 1. "NFERE,If this bit is set the Controller will active its NON_FATAL_ERROR_OUT output in response to an error message received from the link." "0,1" newline bitfld.long 0x0 0. "CERE,If this bit is set the Controller will active its CORRECTABLE_ERROR_OUT output in response to an error message received from the link." "0,1" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_root_err_stat,This register contains status information on error messages received from the link (that" bitfld.long 0x4 6. "FEMR,This bit when set indicates that the RC has received one or more Fatal error messages from the link. STICKY" "0,1" newline bitfld.long 0x4 5. "NEMR,This bit when set indicates that the RC has received one or more Non-Fatal error messages from the link. STICKY" "0,1" newline bitfld.long 0x4 4. "FUF,This bit when set indicates that the first Uncorrectable error message received was for a Fatal error. STICKY" "0,1" newline bitfld.long 0x4 3. "MEFNR,This bit is set when the RC receives either a Fatal or Non-Fatal error message from the link and the ERR_FATAL/NONFATAL Received bit is already set. STICKY" "0,1" newline bitfld.long 0x4 2. "EFNR,This bit is set when the RC receives either a Fatal or Non-Fatal error message from the link. STICKY" "0,1" newline bitfld.long 0x4 1. "MECR,This bit is set when the RC receives a Correctable error message from the link if the ERR_COR received bit is already set. STICKY" "0,1" newline bitfld.long 0x4 0. "ECR,This bit is set when the RC receives a Correctable error message from the link. STICKY" "0,1" rgroup.long 0x134++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_err_src_id,This register stores the Register IDs extracted from error messages received by the Root" hexmask.long.word 0x0 16.--31. 1. "EFNSI,This field captures and stores the Requester ID from an ERR_FATAL or ERROR_NONFATAL message received by the RC if the ERR_FATAL or NONFATAL Received bit was not set at the time the message was received. STICKY" newline hexmask.long.word 0x0 0.--15. 1. "ECSI,This field captures and stores the Requester ID from an ERR_COR message received by the RC if the ERR_COR bit was not set at the time the message was received. STICKY" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_tlp_pre_log_0,First TLP Prefix (if present) associated with the TLP whose header is in the Header Log Register." hexmask.long 0x4 0.--31. 1. "HD1,First TLP Prefix of captured TLP STICKY." rgroup.long 0x150++0xB line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_dev_ser_num_cap_hdr,This register contains the PCI Express Extended Capability ID for Device Serial Number" hexmask.long.word 0x0 20.--31. 1. "SNNCO,Indicates offset to the next PCI Express capability structure. The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set." newline hexmask.long.byte 0x0 16.--19. 1. "DSNCV,Specifies the SIG assigned value for the version of the capability structure. This field is set by default to 1 but can be modified from the local management bus by writing into Function 0 from the local management bus." newline hexmask.long.word 0x0 0.--15. 1. "PECID,This field is hardwired to the Capability ID assigned by PCI SIG to the PCI Express Device Serial Number Capability [0001 hex]." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_dev_ser_num_0,This read-only register stored the first 32 bits of the device's serial number." hexmask.long 0x4 0.--31. 1. "DSND0,This field contains the first 32 bits of the device's serial number. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write." line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_dev_ser_num_1,This read-only register stored the last 32 bits of the device's serial number." hexmask.long 0x8 0.--31. 1. "DSND1,This field contains the last 32 bits of the device's serial number. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write." rgroup.long 0x300++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_sec_pcie_cap_hdr_reg,This register contains the PCI Express Extended Capability ID for the Secondary PCI" hexmask.long.word 0x0 20.--31. 1. "NCO,Indicates offset to the next PCI Express capability structure. The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set." newline hexmask.long.byte 0x0 16.--19. 1. "CV,Specifies the SIG assigned value for the version of the capability structure. This field is set by default to 1 but can be modified independently for each PF from [ the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a.." newline hexmask.long.word 0x0 0.--15. 1. "PECI,This field is hardwired to the Capability ID assigned by PCI SIG to the Secondary PCI Express Capability" rgroup.long 0x304++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_link_control3,This register is part of the Secondary PCI Express Extended Capability Structure." hexmask.long.byte 0x0 9.--12. 1. "ELSOSGV,When the Link is in L0 and the bit in this field corresponding to the current Link speed is Set SKP Ordered Sets are scheduled at the rate defined for SRNS overriding the rate required based on the clock tolerance architecture." newline bitfld.long 0x0 1. "LERIE,This bit enables the activation of the LOCAL_INTERRUPT_OUT output of the Controller when the Link Equalization Request bit in the Link Status 2 Register Or the Link Equalization Request 16.0 GT/s in the 16GTs Status Register is set." "0,1" newline bitfld.long 0x0 0. "PE,The state of this bit determines whether the Controller performs link equalization when the link is retrained by the local software. If this bit is set to 1 when the local software sets the Link Retrain bit in the Link Control Register .." "0,1" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_lane_error_status,This register contains one bit per lane indicating the physical-layer error status of" hexmask.long 0x4 4.--31. 1. "R0,N/A" newline hexmask.long.byte 0x4 0.--3. 1. "LES,Each of these bits indicates the error status for the corresponding lane. STICKY." rgroup.long 0x30C++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_lane_equalization_control_0,This register contains the 8.0GT/s Transmitter Preset and the Receiver Preset Hint values for" bitfld.long 0x0 28.--30. "UPRPH1,8.0GT/s Value sent by the Controller as the Receiver Preset Hint for the remote receiver associated with Lane 1. The remote node may use this value to adapt its receiver at the start of the link equalization procedure." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--27. 1. "UPTP1,8.0GT/s Value sent by the Controller as the Transmitter Preset for the remote transmitter associated with Lane 1. The remote node uses this value to set up its transmitter at the start of the link equalization procedure." newline bitfld.long 0x0 20.--22. "DNRPH1,8.0GT/s Receiver Preset Hint value to be used for the local receiver associated with Lane 1. The Controller uses this value to set up the receiver attached to Lane 1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "DNTP1,8.0GT/s Transmitter Preset value to be used for the local transmitter associated with Lane 1. The Controller uses this value to set up the Lane 1 transmitter during link equalization." newline bitfld.long 0x0 12.--14. "UPRPH0,8.0GT/s Value sent by the Controller as the Receiver Preset Hint for the remote receiver associated with Lane 0. The remote node may use this value to adapt its receiver at the start of the link equalization procedure." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "UPTP0,8.0GT/s Value sent by the Controller as the Transmitter Preset for the remote transmitter associated with Lane 0. The remote node uses this value to set up its transmitter at the start of the link equalization procedure." newline bitfld.long 0x0 4.--6. "DNRPH0,8.0GT/s Receiver Preset Hint value to be used for the local receiver associated with Lane 0. The Controller uses this value to set up the receiver attached to Lane 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "DNTP0,8.0GT/s Transmitter Preset value to be used for the local transmitter associated with Lane 0. The Controller uses this value to set up the Lane 0 transmitter during link equalization." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_lane_equalization_control_1,This register contains the 8.0GT/s Transmitter Preset and the Receiver Preset Hint values for" bitfld.long 0x4 28.--30. "UPRPH1,8.0GT/s Value sent by the Controller as the Receiver Preset Hint for the remote receiver associated with Lane 3. The remote node may use this value to adapt its receiver at the start of the link equalization procedure." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 24.--27. 1. "UPTP1,8.0GT/s Value sent by the Controller as the Transmitter Preset for the remote transmitter associated with Lane 3. The remote node uses this value to set up its transmitter at the start of the link equalization procedure." newline bitfld.long 0x4 20.--22. "DNRPH1,8.0GT/s Receiver Preset Hint value to be used for the local receiver associated with Lane 3. The Controller uses this value to set up the receiver attached to Lane 3" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--19. 1. "DNTP1,8.0GT/s Transmitter Preset value to be used for the local transmitter associated with Lane 3. The Controller uses this value to set up the Lane 3 transmitter during link equalization." newline bitfld.long 0x4 12.--14. "UPRPH0,8.0GT/s Value sent by the Controller as the Receiver Preset Hint for the remote receiver associated with Lane 2. The remote node may use this value to adapt its receiver at the start of the link equalization procedure." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "UPTP0,8.0GT/s Value sent by the Controller as the Transmitter Preset for the remote transmitter associated with Lane 2. The remote node uses this value to set up its transmitter at the start of the link equalization procedure." newline bitfld.long 0x4 4.--6. "DNRPH0,8.0GT/s Receiver Preset Hint value to be used for the local receiver associated with Lane 2. The Controller uses this value to set up the receiver attached to Lane 2" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--3. 1. "DNTP0,8.0GT/s Transmitter Preset value to be used for the local transmitter associated with Lane 2. The Controller uses this value to set up the Lane 2 transmitter during link equalization." rgroup.long 0x4C0++0x13 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_VC_enh_cap_header_reg,This is the first register in the Virtual Channel Capability Structure. The VC Capability is present only in" hexmask.long.word 0x0 20.--31. 1. "NCO,Indicates offset to the next PCI Express capability structure. The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set." newline hexmask.long.byte 0x0 16.--19. 1. "CV,Specifies the SIG assigned value for the version of the capability structure. This field is set by default to 1 but can be modified independently for each PF from the local management bus." newline hexmask.long.word 0x0 0.--15. 1. "PECID,This field is hardwired to the Capability ID assigned by PCI SIG to the VC Capability." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_port_vc_cap_reg_1,This register has fields that describe the capabilities of the device with respect to the virtual channels." hexmask.long 0x4 4.--31. 1. "R0,N/A" newline bitfld.long 0x4 0.--2. "EVC,N/A" "0,1,2,3,4,5,6,7" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_port_vc_cap_reg_2,This register has fields that describe the capabilities of the device with respect to the virtual channels." hexmask.long 0x8 0.--31. 1. "R1,N/A" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_i_port_vc_ctrl_sts_reg,This location contains the 16-bit VC Control Register and the 16-bit VC Status Register. These registers" hexmask.long 0xC 0.--31. 1. "R2,N/A" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_i_vc_res_cap_reg_0,This register describes the capabilities associated with VC 0." hexmask.long.word 0x10 16.--31. 1. "R3,N/A" newline bitfld.long 0x10 15. "RST,N/A" "0,1" newline hexmask.long.word 0x10 0.--14. 1. "R1,N/A" rgroup.long 0x4D4++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_vc_res_ctrl_reg_0,This register contains bits to configure VC 0." rbitfld.long 0x0 31. "VCEN,Software uses this bit to enable the VC. For VC0 this bit is hardwired to 1." "0,1" newline hexmask.long.byte 0x0 27.--30. 1. "R6,N/A" newline rbitfld.long 0x0 24.--26. "VCI,VC ID assigned to VC0. For the VC0 this field is read-only and it is hardwired to 00b. For non VC0 case it is allowed to use any VC-ID. This VC-ID has to be unique across all VCs. This must not be same as VC0's ID[VC0 ID=0]." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 20.--23. 1. "R5,N/A" newline rbitfld.long 0x0 17.--19. "PARS,Configures the VC to use a specific port arbitration scheme. This field is not implemented and hardwired to 0." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16. "LPAT,Updates the port arbitration logic from the Port Arbitration Table for VC 0. This bit is not implemented and hardwired to 0." "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "TVM,Indicates the TCs that are mapped to this VC. When bit 0 of this field is set it indicates that TC 0 is mapped to VC 0.By default all TCs are mapped to VC 0." newline rbitfld.long 0x0 0. "TVM0,Indicates the TC0 always mapped to VC0." "0,1" rgroup.long 0x4D8++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_vc_res_sts_reg_0,This register contains status bits associated with VC 0." bitfld.long 0x0 1. "VCNP,This indicates whether the Virtual Channel negotiation is in pending state. The value of this bit is defined only when the link is in the DL_Active state and Virtual Channel is enabled. When this bit is set by hardware it indicates.." "0,1" newline bitfld.long 0x0 0. "PATS,This is not implemented and hardwired to 0." "0,1" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_vc_res_cap_reg_1,This register describes the capabilities associated with VC 1." hexmask.long.word 0x4 16.--31. 1. "R3,N/A" newline bitfld.long 0x4 15. "RST,N/A" "0,1" newline hexmask.long.word 0x4 0.--14. 1. "R1,N/A" rgroup.long 0x4E0++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_vc_res_ctrl_reg_1,This register contains bits to configure VC 1." bitfld.long 0x0 31. "VCEN,Software uses this bit to enable the VC. For VC0 this bit is hardwired to 1." "0,1" newline hexmask.long.byte 0x0 27.--30. 1. "R6,N/A" newline bitfld.long 0x0 24.--26. "VCI,VC ID assigned to VC1. For the VC0 this field is read-only and it is hardwired to 00b. For non VC0 case it is allowed to use any VC-ID. This VC-ID has to be unique across all VCs. This must not be same as VC0's ID[VC0 ID=0]." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 20.--23. 1. "R5,N/A" newline rbitfld.long 0x0 17.--19. "PARS,Configures the VC to use a specific port arbitration scheme. This field is not implemented and hardwired to 0." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16. "LPAT,Updates the port arbitration logic from the Port Arbitration Table for VC 1. This bit is not implemented and hardwired to 0." "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "TVM,Indicates the TCs that are mapped to this VC. When bit 1 of this field is set it indicates that TC 1 is mapped to VC 1.By default all TCs are mapped to VC 0." newline rbitfld.long 0x0 0. "TVM0,Indicates the TC0 always mapped to VC0." "0,1" rgroup.long 0x4E4++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_vc_res_sts_reg_1,This register contains status bits associated with VC 1." bitfld.long 0x0 1. "VCNP,This indicates whether the Virtual Channel negotiation is in pending state. The value of this bit is defined only when the link is in the DL_Active state and Virtual Channel is enabled. When this bit is set by hardware it indicates.." "0,1" newline bitfld.long 0x0 0. "PATS,This is not implemented and hardwired to 0." "0,1" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_vc_res_cap_reg_2,This register describes the capabilities associated with VC 2." hexmask.long.word 0x4 16.--31. 1. "R3,N/A" newline bitfld.long 0x4 15. "RST,N/A" "0,1" newline hexmask.long.word 0x4 0.--14. 1. "R1,N/A" rgroup.long 0x4EC++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_vc_res_ctrl_reg_2,This register contains bits to configure VC 2." bitfld.long 0x0 31. "VCEN,Software uses this bit to enable the VC. For VC0 this bit is hardwired to 1." "0,1" newline hexmask.long.byte 0x0 27.--30. 1. "R6,N/A" newline bitfld.long 0x0 24.--26. "VCI,VC ID assigned to VC2. For the VC0 this field is read-only and it is hardwired to 00b. For non VC0 case it is allowed to use any VC-ID. This VC-ID has to be unique across all VCs. This must not be same as VC0's ID[VC0 ID=0]." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 20.--23. 1. "R5,N/A" newline rbitfld.long 0x0 17.--19. "PARS,Configures the VC to use a specific port arbitration scheme. This field is not implemented and hardwired to 0." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16. "LPAT,Updates the port arbitration logic from the Port Arbitration Table for VC 2. This bit is not implemented and hardwired to 0." "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "TVM,Indicates the TCs that are mapped to this VC. When bit 2 of this field is set it indicates that TC 2 is mapped to VC 2.By default all TCs are mapped to VC 0." newline rbitfld.long 0x0 0. "TVM0,Indicates the TC0 always mapped to VC0." "0,1" rgroup.long 0x4F0++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_vc_res_sts_reg_2,This register contains status bits associated with VC 2." bitfld.long 0x0 1. "VCNP,This indicates whether the Virtual Channel negotiation is in pending state. The value of this bit is defined only when the link is in the DL_Active state and Virtual Channel is enabled. When this bit is set by hardware it indicates.." "0,1" newline bitfld.long 0x0 0. "PATS,This is not implemented and hardwired to 0." "0,1" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_vc_res_cap_reg_3,This register describes the capabilities associated with VC 3." hexmask.long.word 0x4 16.--31. 1. "R3,N/A" newline bitfld.long 0x4 15. "RST,N/A" "0,1" newline hexmask.long.word 0x4 0.--14. 1. "R1,N/A" rgroup.long 0x4F8++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_vc_res_ctrl_reg_3,This register contains bits to configure VC 3." bitfld.long 0x0 31. "VCEN,Software uses this bit to enable the VC. For VC0 this bit is hardwired to 1." "0,1" newline hexmask.long.byte 0x0 27.--30. 1. "R6,N/A" newline bitfld.long 0x0 24.--26. "VCI,VC ID assigned to VC3. For the VC0 this field is read-only and it is hardwired to 00b. For non VC0 case it is allowed to use any VC-ID. This VC-ID has to be unique across all VCs. This must not be same as VC0's ID[VC0 ID=0]." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 20.--23. 1. "R5,N/A" newline rbitfld.long 0x0 17.--19. "PARS,Configures the VC to use a specific port arbitration scheme. This field is not implemented and hardwired to 0." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16. "LPAT,Updates the port arbitration logic from the Port Arbitration Table for VC 3. This bit is not implemented and hardwired to 0." "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "TVM,Indicates the TCs that are mapped to this VC. When bit 3 of this field is set it indicates that TC 3 is mapped to VC 3.By default all TCs are mapped to VC 0." newline rbitfld.long 0x0 0. "TVM0,Indicates the TC0 always mapped to VC0." "0,1" rgroup.long 0x4FC++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_vc_res_sts_reg_3,This register contains status bits associated with VC 3." bitfld.long 0x0 1. "VCNP,This indicates whether the Virtual Channel negotiation is in pending state. The value of this bit is defined only when the link is in the DL_Active state and Virtual Channel is enabled. When this bit is set by hardware it indicates.." "0,1" newline bitfld.long 0x0 0. "PATS,This is not implemented and hardwired to 0." "0,1" rgroup.long 0x900++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_L1_PM_ext_cap_hdr,L1 PM Substates Extended Capability Header Register." hexmask.long.word 0x0 20.--31. 1. "NCO,Indicates offset to the next PCI Express capability structure. The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set." newline hexmask.long.byte 0x0 16.--19. 1. "CV,Specifies the SIG assigned value for the version of the capability structure. This field is set by default to 1 but can be modified from the local management bus." newline hexmask.long.word 0x0 0.--15. 1. "PECID,This field is hardwired to the Capability ID assigned by PCI SIG to the L1 PM Substates Extended Capability Structure [001E hex]." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_L1_PM_cap,This register advertises the L1 PM Substates Capabilities." hexmask.long.byte 0x4 19.--23. 1. "R0,Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time [in us] that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling CLKREQ# asserted before.." newline bitfld.long 0x4 16.--17. "L1PRTPVRONSCALE,Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register. Range of Values 00b = 2us 01b = 10us 10b = 100us 11b =.." "0,1,2,3" newline hexmask.long.byte 0x4 8.--15. 1. "L1PRTCMMDRESTRTIME,Time [in us] required for this Port to re-establish common mode during exit from PM or ASPM L1.2 substate" newline bitfld.long 0x4 4. "L1PMSUPP,When Set this bit indicates that this Port supports L1 PM Substates." "0,1" newline bitfld.long 0x4 3. "L1ASPML11SUPP,When Set this bit indicates that ASPM L1.1 is supported." "0,1" newline bitfld.long 0x4 2. "L1ASPML12SUPP,When Set this bit indicates that ASPM L1.2 is supported." "0,1" newline bitfld.long 0x4 1. "L1PML11SUPP,When Set this bit indicates that PCI-PM L1.1 is supported." "0,1" newline bitfld.long 0x4 0. "L1PML12SUPP,When Set this bit indicates that PCI-PM L1.2 is supported." "0,1" rgroup.long 0x908++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_L1_PM_ctrl_1,L1 PM Substates Control 1 Register" bitfld.long 0x0 29.--31. "L1THRSHLDSC,This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value. 000 - Value times 1 ns 001 - Value times 32 ns 010 - Value times 1024 ns 011 - Value times 32 768.." "0: Value times 1 ns 001,?,?,?,?,?,?,?" newline hexmask.long.word 0x0 16.--25. 1. "L1THRSHLDVAL,Along with the LTR_L1.2_THRESHOLD_Scale this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 [if enabled] or L1.2 [if enabled]." newline hexmask.long.byte 0x0 8.--15. 1. "L1CMMDRESTRTIME,Sets value of TCOMMONMODE [in us] which must be used by the Downstream Port for timing the re-establishment of common mode. This field must only be modified when the ASPM L1.2 Enable and PCI-PM L1.2 Enable bits are both.." newline bitfld.long 0x0 3. "L1ASPML11EN,When Set this bit enables ASPM L1.1." "0,1" newline bitfld.long 0x0 2. "L1ASPML12EN,When Set this bit enables ASPM L1.2." "0,1" newline bitfld.long 0x0 1. "L1PML11EN,When Set this bit enables PCI-PM L1.1." "0,1" newline bitfld.long 0x0 0. "L1PML12EN,When Set this bit enables PCI-PM L1.2." "0,1" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_L1_PM_ctrl_2,L1 PM Substates Control 2 Register" hexmask.long.byte 0x4 3.--7. 1. "L1PWRONVAL,Along with the T_POWER_ON Scale sets the minimum amount of time [in us] that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface. T_POWER_ON is calculated by multiplying the value.." newline bitfld.long 0x4 0.--1. "L1PWRONSC,Specifies the scale used for T_POWER_ON Value. Range of Values 00b = 2us 01b = 10us 10b = 100us 11b = Reserved" "0,1,2,3" rgroup.long 0x910++0xB line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_dl_feature_extended_capability_header_reg,Data Link Feature Extended Capability Structure is used to configure the DL Feature mechanism." hexmask.long.word 0x0 20.--31. 1. "DLFNXCAP,The offset to the next PCI Extended Capability structure." newline hexmask.long.byte 0x0 16.--19. 1. "DLFCAPVER,This field is a PCI-SIG defined version number that indicates the version of the Capability structure present." newline hexmask.long.word 0x0 0.--15. 1. "DLFCAPID,Indicates that the associated extended capability structure is the DL Feature Extended Capability. This field returns a Capability ID of 0025h." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_dl_feature_capabilities_reg,Data Link Feature Capabilities Register.." bitfld.long 0x4 31. "DLFEXEN,If Set this bit indicates that this Port will enter the DL_Feature negotiation state prior to Link Initialization." "0,1" newline bitfld.long 0x4 0. "DLFCAPVER,This bit indicates that this Port supports the Scaled Flow Control Feature." "0,1" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_dl_feature_status_reg,Data Link Feature Status Register.." bitfld.long 0x8 31. "RDLFSVAL,This bit indicates that the Port has received a Data Link Feature DLLP in state DL_Feature [see Section 3.2.1] and that the Remote Data Link Feature Supported and Remote Data Link Feature Ack fields are meaningful." "0,1" newline bitfld.long 0x8 0. "RSFSUP,This bit indicates that the Remote end Device supports the Scaled Flow Control Feature." "0,1" rgroup.long 0x920++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_margining_extended_capability_header_reg,Margining Extended Capability Structure is used to configure the device for Receiver Margining." hexmask.long.word 0x0 20.--31. 1. "MARNXCAP,The offset to the next PCI Extended Capability structure." newline hexmask.long.byte 0x0 16.--19. 1. "MARCAPVER,This field is a PCI-SIG defined version number that indicates the version of the Capability structure present." newline hexmask.long.word 0x0 0.--15. 1. "MARCAPID,Indicates that the associated extended capability structure is the Margining Extended Capability. This field returns a Capability ID of 0027h." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_margining_port_capabilities_status_reg,Margining Port Capabilities and Status Register." bitfld.long 0x4 17. "MSRDY,When Margining uses Driver Software is Set then this bit when Set indicates that the required software has performed the required initialization. The value of this bit is Undefined if Margining users Driver Software is Clear." "0,1" newline bitfld.long 0x4 16. "MRDY,Indicates when the Margining feature is ready to accept margining commands. If the Margining uses Driver Software bit is 1 then the Controller sets this status bit when the Margining Software Ready bit is set and the Link is in Gen4.." "0,1" newline bitfld.long 0x4 0. "MARUDS,If Set indicates that Margining is partially implemented using Device Driver software. Margining Software Ready indicates when this software is initialized. If Clear Margining does not require device driver software." "0,1" rgroup.long 0x928++0xF line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_margining_lane_control_status_reg0,Margining Lane Control and Status Register for Lane 0." hexmask.long.byte 0x0 24.--31. 1. "MPSTS,Margin Payload Status for Margining Commands. This field is reset upon DL Down." newline rbitfld.long 0x0 22. "UMSTS,Usage Model Status for Margining Commands. This field is reset upon DL Down." "0,1" newline rbitfld.long 0x0 19.--21. "MTSTS,Margin Type Status for Margining Commands. This field is reset upon DL Down." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16.--18. "RNSTS,Receiver Number Status for Margining Commands. This field is reset upon DL Down." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "MRGPAY,Margin Payload for Margining Commands. This field is reset upon DL Down." newline bitfld.long 0x0 6. "USGMOD,Usage Model for Margining Commands. This field is reset upon DL Down." "0,1" newline bitfld.long 0x0 3.--5. "MRGTYP,Margin Type for Margining Commands. This field is reset upon DL Down." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RCVNUM,Receiver Number for Margining Commands. This field is reset upon DL Down." "0,1,2,3,4,5,6,7" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_margining_lane_control_status_reg1,Margining Lane Control and Status Register for Lane 1." hexmask.long.byte 0x4 24.--31. 1. "MPSTS,Margin Payload Status for Margining Commands. This field is reset upon DL Down." newline rbitfld.long 0x4 22. "UMSTS,Usage Model Status for Margining Commands. This field is reset upon DL Down." "0,1" newline rbitfld.long 0x4 19.--21. "MTSTS,Margin Type Status for Margining Commands. This field is reset upon DL Down." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 16.--18. "RNSTS,Receiver Number Status for Margining Commands. This field is reset upon DL Down." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--15. 1. "MRGPAY,Margin Payload for Margining Commands. This field is reset upon DL Down." newline bitfld.long 0x4 6. "USGMOD,Usage Model for Margining Commands. This field is reset upon DL Down." "0,1" newline bitfld.long 0x4 3.--5. "MRGTYP,Margin Type for Margining Commands. This field is reset upon DL Down." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "RCVNUM,Receiver Number for Margining Commands. This field is reset upon DL Down." "0,1,2,3,4,5,6,7" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_margining_lane_control_status_reg2,Margining Lane Control and Status Register for Lane 2." hexmask.long.byte 0x8 24.--31. 1. "MPSTS,Margin Payload Status for Margining Commands. This field is reset upon DL Down." newline rbitfld.long 0x8 22. "UMSTS,Usage Model Status for Margining Commands. This field is reset upon DL Down." "0,1" newline rbitfld.long 0x8 19.--21. "MTSTS,Margin Type Status for Margining Commands. This field is reset upon DL Down." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 16.--18. "RNSTS,Receiver Number Status for Margining Commands. This field is reset upon DL Down." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--15. 1. "MRGPAY,Margin Payload for Margining Commands. This field is reset upon DL Down." newline bitfld.long 0x8 6. "USGMOD,Usage Model for Margining Commands. This field is reset upon DL Down." "0,1" newline bitfld.long 0x8 3.--5. "MRGTYP,Margin Type for Margining Commands. This field is reset upon DL Down." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "RCVNUM,Receiver Number for Margining Commands. This field is reset upon DL Down." "0,1,2,3,4,5,6,7" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_i_margining_lane_control_status_reg3,Margining Lane Control and Status Register for Lane 3." hexmask.long.byte 0xC 24.--31. 1. "MPSTS,Margin Payload Status for Margining Commands. This field is reset upon DL Down." newline rbitfld.long 0xC 22. "UMSTS,Usage Model Status for Margining Commands. This field is reset upon DL Down." "0,1" newline rbitfld.long 0xC 19.--21. "MTSTS,Margin Type Status for Margining Commands. This field is reset upon DL Down." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 16.--18. "RNSTS,Receiver Number Status for Margining Commands. This field is reset upon DL Down." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--15. 1. "MRGPAY,Margin Payload for Margining Commands. This field is reset upon DL Down." newline bitfld.long 0xC 6. "USGMOD,Usage Model for Margining Commands. This field is reset upon DL Down." "0,1" newline bitfld.long 0xC 3.--5. "MRGTYP,Margin Type for Margining Commands. This field is reset upon DL Down." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0.--2. "RCVNUM,Receiver Number for Margining Commands. This field is reset upon DL Down." "0,1,2,3,4,5,6,7" rgroup.long 0x9C0++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_pl_16gts_extended_capability_header_reg,Physical Layer 16 GT/s Extended Capability Structure is used to configure the device for Gen4 Equalization and Gen4 Lane Error Reporting." hexmask.long.word 0x0 20.--31. 1. "PL16NXCAP,The offset to the next PCI Extended Capability structure." newline hexmask.long.byte 0x0 16.--19. 1. "PL16CAPVER,This field is a PCI-SIG defined version number that indicates the version of the Capability structure present." newline hexmask.long.word 0x0 0.--15. 1. "PL16CAPID,Indicates that the associated extended capability structure is for Physical layer 16 GT/s. This field returns a Capability ID of 0026h." rgroup.long 0x9C4++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_pl_16gts_capabilities_reg,Physical Layer 16GTs Capabilities Register." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_pl_16gts_control_reg,Physical Layer 16GTs Control Register." line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_pl_16gts_status_reg,Physical Layer 16GTs Status Register." bitfld.long 0x8 4. "LE16,When the Controller [RP] receives an 16GTs equalization request from an Upstream Port the Controller internally sets this bit to 1. [i.e. when RP is in the Recovery.RcvrCfg state and receives 8 consecutive TS2 Ordered Sets with the.." "0,1" newline rbitfld.long 0x8 3. "EP3S16,This bit when set to 1 indicates that the Phase 3 of the Transmitter Equalization procedure has completed successfully for 16.0 GT/s. STICKY." "0,1" newline rbitfld.long 0x8 2. "EP2S16,This bit when set to 1 indicates that the Phase 2 of the Transmitter Equalization procedure has completed successfully for 16.0 GT/s. STICKY." "0,1" newline rbitfld.long 0x8 1. "EP1S16,This bit when set to 1 indicates that the Phase 1 of the Transmitter Equalization procedure has completed successfully for 16.0 GT/s. STICKY." "0,1" newline rbitfld.long 0x8 0. "EQC16,This bit when set to 1 indicates that the Transmitter Equalization procedure has completed for 16.0 GT/s. STICKY." "0,1" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_i_pl_16gts_local_data_parity_mismatch_status_reg,Physical Layer 16GTs Local Data Parity Mismatch Status Register." hexmask.long 0xC 4.--31. 1. "R0,N/A" newline hexmask.long.byte 0xC 0.--3. 1. "LDPMS16,Each bit indicates if the corresponding Lane detected a Data Parity mismatch. A value of 1b indicates that a mismatch was detected on the corresponding Lane Number." line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_i_pl_16gts_first_retimer_data_parity_mismatch_status_reg,Physical Layer 16GTs First Retimer Data Parity Mismatch Status Register." hexmask.long 0x10 4.--31. 1. "R0,N/A" newline hexmask.long.byte 0x10 0.--3. 1. "FRDPMS16,Each bit indicates if the first retimer in the corresponding Lane detected a Data Parity mismatch. A value of 1b indicates that a mismatch was detected on the corresponding Lane Number. The value of this field is.." line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_i_pl_16gts_second_retimer_data_parity_mismatch_status_reg,Physical Layer 16GTs Second Retimer Data Parity Mismatch Status Register." hexmask.long 0x14 4.--31. 1. "R0,N/A" newline hexmask.long.byte 0x14 0.--3. 1. "SRDPMS16,Each bit indicates if the second retimer in the corresponding Lane detected a Data Parity mismatch. A value of 1b indicates that a mismatch was detected on the corresponding Lane Number. The value of this field is.." line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_i_pl_16gts_reserved_reg,Register at offset 1Ch in this capability is Reserved." rgroup.long 0x9E0++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_pl_16gts_lane_equalization_control_reg0,This register contains the Downstream and Upstream Port 16.0GT/s Transmitter Preset for" hexmask.long.byte 0x0 28.--31. 1. "UPTP316,16.0GT/s Lane 3 Transmitter Preset value that the Downstream Port sends on the associated Lane to the Endpoint device during 16GT/s Link Equalization." newline hexmask.long.byte 0x0 24.--27. 1. "DPTP316,Transmitter Preset used for 16.0 GT/s equalization by this Port when the Port is operating as a Downstream Port." newline hexmask.long.byte 0x0 20.--23. 1. "UPTP216,16.0GT/s Lane 2 Transmitter Preset value that the Downstream Port sends on the associated Lane to the Endpoint device during 16GT/s Link Equalization." newline hexmask.long.byte 0x0 16.--19. 1. "DPTP216,Transmitter Preset used for 16.0 GT/s equalization by this Port when the Port is operating as a Downstream Port." newline hexmask.long.byte 0x0 12.--15. 1. "UPTP116,16.0GT/s Lane 1 Transmitter Preset value that the Downstream Port sends on the associated Lane to the Endpoint device during 16GT/s Link Equalization." newline hexmask.long.byte 0x0 8.--11. 1. "DPTP116,Transmitter Preset used for 16.0 GT/s equalization by this Port when the Port is operating as a Downstream Port." newline hexmask.long.byte 0x0 4.--7. 1. "UPTP016,16.0GT/s Lane 0 Transmitter Preset value that the Downstream Port sends on the associated Lane to the Endpoint device during 16GT/s Link Equalization." newline hexmask.long.byte 0x0 0.--3. 1. "DPTP016,Transmitter Preset used for 16.0 GT/s equalization by this Port when the Port is operating as a Downstream Port." rgroup.long 0xA20++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_ptm_extended_capability_header_reg,Precision Time Measurement Extended Capability Structure is used discovering and controlling the distribution of a PTM hierarchy." hexmask.long.word 0x0 20.--31. 1. "PTMNXCAP,The offset to the next PCIe Extended Capability structure." newline hexmask.long.byte 0x0 16.--19. 1. "PTMCAPVER,This field is a PCI-SIG defined version number that indicates the version of the Capability structure present." newline hexmask.long.word 0x0 0.--15. 1. "PTMCAPID,Indicates that the associated extended capability structure is for Precision Time Measurement capability. This field returns a Capability ID of 001Fh." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_ptm_capabilities_reg,PTM Capabilities Register." hexmask.long.byte 0x4 8.--15. 1. "LOCCLKGR,In RC Mode: The Controller uses the CORE_CLK as the Local Clock for PTM. This field is used to indicate the Time Period of the CORE_CLK. If the PTM Root Select is 1 then CORE_CLK is used to provide PTM.." newline bitfld.long 0x4 2. "PTMRTCAP,This bit is used to indicate that the Controller implements PTM Time Source Role and is capable of serving as PTM Root. By default this bit is set to 1 when the Controller is in RC Mode. This bit can be programmed.." "0,1" newline bitfld.long 0x4 1. "PTMRSCAP,This bit is used to indicate support for PTM Responder Role. By default this bit is set to 1 when the Controller is in RC Mode. This bit can be programmed through the local management APB interface if required." "0,1" newline bitfld.long 0x4 0. "PTMRQCAP,This bit is used to indicate support for PTM Requester Role. By default this bit is set to 0 when the Controller is in RC Mode. This bit can be programmed through the local management APB interface if required." "0,1" rgroup.long 0xA28++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_ptm_control_reg,PTM Control Register." hexmask.long.byte 0x0 8.--15. 1. "EFFGRN,This field is used only in PTM Requester Mode and is not used in RC Mode. This field is set to 00 by default in RC Mode." newline bitfld.long 0x0 1. "RTSEL,This field is configured by System SW. When set to 1 and when PTM Enable bit is aslo set to 1 this PTM Source is the PTM Root. Default value of this bit is 0." "0,1" newline bitfld.long 0x0 0. "PTMEN,When Set this function is permitted to participate in the PTM mechanism as PTM Requester. By default this bit is set to 0." "0,1" rgroup.long 0x100000++0x13 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_pl_config_0_reg,This register contains the configured parameters at the Physical Layer of the link. and" bitfld.long 0x0 31. "MLE,When the Controller is operating as a Root Port setting this to 1 causes the LTSSM to initiate a loopback and become the loopback master. This bit is not used in the EndPoint Mode." "0,1" newline rbitfld.long 0x0 30. "R0,A 1 in this field indicates that the remote node advertised Linkwidth Upconfigure Capability in the training sequences in the Configuration.Complete state when the link came up. A 0 indicates that the remote node did not set the Link.." "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "LTSSM,Current state of the LTSSM. The encoding of the states is given in Appendix C." newline hexmask.long.byte 0x0 16.--23. 1. "RLID,Link ID received from other side during link training." newline hexmask.long.byte 0x0 8.--15. 1. "RFC,FTS count received from the other side during link training for use at the 2.5 GT/s link speed. The Controller transmits this many FTS sequences while exiting the L0S state when operating at the 2.5 GT/s speed." newline bitfld.long 0x0 7. "TSS,This bit drives the PIPE_TX_SWING output of the Controller." "0,1" newline bitfld.long 0x0 6. "APER,This bit controls the reporting of Errors Detected by the PHY. The Errors Detected by the PHY include:- - Received errors indicated on PIPE RxStatus interface - 8.0 GT/s Invalid Sync Header received error .." "0,1" newline rbitfld.long 0x0 5. "LTD,The state of this bit indicates whether the Controller completed link training as an upstream port[EndPoint][=0] or a downstream port[Root Port][=1]. Default value depends on CORE_TYPE strap pin." "0,1" newline rbitfld.long 0x0 3.--4. "NS,Current operating speed of link [00 = 2.5G 01 = 5G 10 = 8G 11 = 16G]." "0,1,2,3" newline rbitfld.long 0x0 1.--2. "NLC,Lane count negotiated with other side during link training [00 = x1 01 = x2 10 = x4 11 = x8]." "0: x1,1: x2,?,?" newline rbitfld.long 0x0 0. "LS,Current state of link [1 = link training complete 0 = link training not complete]." "0: link training not complete],1: link training complete" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_pl_config_1_reg,This register contains additional configured parameters at the Physical Layer of the" hexmask.long.byte 0x4 24.--31. 1. "TFC3,FTS count transmitted by the Controller in TS1/TS2 sequences during link training. This value must be set based on the time needed by the receiver to acquire sync while exiting from L0S state." newline hexmask.long.byte 0x4 16.--23. 1. "TFC2,FTS count transmitted by the Controller in TS1/TS2 sequences during link training. This value must be set based on the time needed by the receiver to acquire sync while exiting from L0S state." newline hexmask.long.byte 0x4 8.--15. 1. "TFC1,FTS count transmitted by the Controller in TS1/TS2 sequences during link training. This value must be set based on the time needed by the receiver to acquire sync while exiting from L0S state." newline hexmask.long.byte 0x4 0.--7. 1. "TLI,Link ID transmitted by the device in training sequences in the Root Port mode." line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_dll_tmr_config_reg,This register defines the replay timeout values used by the DL receive and transmit" hexmask.long.word 0x8 16.--24. 1. "RSART,Additional receive side ACK-NAK timer timeout interval. This 9-bit value is added as a signed 2's complement number to the internal ACK-NAK timer timeout value computed by the Controller based on the PCI Express Specifications. This.." newline hexmask.long.word 0x8 0.--8. 1. "TSRT,Additional transmit-side replay timer timeout interval. This 9-bit value is added as a signed 2's complement number to the internal replay timer timeout value computed by the Controller based on the PCI Express Specifications. This.." line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_i_rcv_cred_lim_0_reg,This register contains the initial credit limits advertised by the Controller during th DL" hexmask.long.word 0xC 20.--31. 1. "NPPC,Non-Posted payload credit limit advertised by the Controller for VC 0 . This field is in units of 4 DWords 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 0. 00b => [units of 4 DWords].." newline hexmask.long.byte 0xC 12.--19. 1. "PHC,Posted header credit limit advertised by the Controller for VC 0. This field is in units of 1 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 0. 00b => [units of 1 Packet Header] 01b => [units of.." newline hexmask.long.word 0xC 0.--11. 1. "PPC,Posted payload credit limit advertised by the Controller for VC 0. This field is in units of 4 DWords 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 0. 00b => [units of 4 DWords] 01b => [units.." line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_i_rcv_cred_lim_1_reg,This register contains the initial credit limits advertised by the Controller during the DL" hexmask.long.byte 0x10 24.--31. 1. "CHC,Completion header credit limit advertised by the Controller for VC 0 [in number of packets]. This field is in units of 1 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 0. 00b => [units of 1.." newline hexmask.long.word 0x10 8.--19. 1. "CPC,Completion payload credit limit advertised by the Controller for VC 0 . This field is in units of 4 DWords 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 0. 00b => [units of 4 DWords] 01b.." newline hexmask.long.byte 0x10 0.--7. 1. "NPHCL,Non-Posted header credit limit advertised by the Controller for VC 0 [in number of packets]. This field is in units of 1 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 0. 00b => [units of 1.." rgroup.long 0x100014++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_transm_cred_lim_0_reg,This register contains the initial credit limits received from the opposite node during" hexmask.long.word 0x0 20.--31. 1. "NPPC,Non-Posted payload credit limit received by the Controller for Link 0 . This field is in units of 4 DWords 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 0. 00b => [units of 4 DWords].." newline hexmask.long.byte 0x0 12.--19. 1. "PHC,Posted header credit limit received by the Controller for this link . This field is in units of 1 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 0. 00b => [units of 1 Packet Header] 01b =>.." newline hexmask.long.word 0x0 0.--11. 1. "PPC,Posted payload credit limit received by the Controller for this link . This field is in units of 4 DWords 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 0. 00b => [units of 4 DWords] 01b =>.." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_transm_cred_lim_1_reg,This register contains the initial credit limits received from the opposite node during" hexmask.long.byte 0x4 24.--31. 1. "CHC,Completion header credit limit received by the Controller for VC 0 . This field is in units of 1 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 0. 00b => [units of 1 Packet Header] 01b => [units.." newline hexmask.long.word 0x4 8.--19. 1. "CPC,Completion payload credit limit received by the Controller for VC 0 . This field is in units of 4 DWords 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 0. 00b => [units of 4 DWords].." newline hexmask.long.byte 0x4 0.--7. 1. "NPHC,Non-Posted header credit limit received by the Controller for VC 0 . This field is in units of 1 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 0. 00b => [units of 1 Packet Header] 01b.." rgroup.long 0x10001C++0x3B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_transm_cred_update_int_config_0_reg,This register contains parameters that control how frequently the Controller sends a credit" hexmask.long.word 0x0 16.--31. 1. "MNUI,Minimum credit update interval for non-posted transactions. The Controller follows this minimum interval between issuing posted credit updates on the link. This is to limit the bandwidth use of credit updates. If new credit becomes.." newline hexmask.long.word 0x0 0.--15. 1. "MPUI,Minimum credit update interval for posted transactions. The Controller follows this minimum interval between issuing posted credit updates on the link. This is to limit the bandwidth use of credit updates. If new credit becomes available.." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_transm_cred_update_int_config_1_reg,This register contains parameters that control how frequently the Controller sends a credit" hexmask.long.word 0x4 16.--31. 1. "MUI,Maximum credit update interval for all transactions. If no new credit has become available since the last update the Controller will repeat the last update after this interval. This is to recover from any losses of credit update packets." newline hexmask.long.word 0x4 0.--15. 1. "CUI,Minimum credit update interval for Completion packets. The Controller follows this minimum interval between issuing completion credit updates on the link. This is to limit the bandwidth use of credit updates. If new credit becomes.." line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_L0S_timeout_limit_reg,This register defines the timeout value for transitioning to the L0S power state. If the" hexmask.long.word 0x8 0.--15. 1. "LT,Contains the timeout value [in units of 16 ns] for transitioning to the L0S power state. Setting this parameter to 0 permanently disables the transition to the L0S power state." line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_i_transmit_tlp_count_reg,This register contains the number of Transaction-Layer packets transmitted by the Controller" hexmask.long 0xC 0.--31. 1. "TTC,Count of TLPs transmitted" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_i_transmit_tlp_payload_dword_count_reg,This register contains the aggregate number of payload double-words transmitted in" hexmask.long 0x10 0.--31. 1. "TTPBC,Count of TLPs payload Dwords transmitted" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_i_receive_tlp_count_reg,This register contains the number of Transaction-Layer packets received by the Controller" hexmask.long 0x14 0.--31. 1. "RTC,Count of TLPs received" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_i_receive_tlp_payload_dword_count_reg,This register contains the aggregate number of payload double-words received in" hexmask.long 0x18 0.--31. 1. "RTPDC,Count of TLP payload Dwords received" line.long 0x1C "CORE__DBN_CFG__PCIE_CORE_REG_i_compln_tmout_lim_0_reg,This register contains the timeout value used to detect a completion timeout event for a" hexmask.long.tbyte 0x1C 0.--23. 1. "CTL,Timeout limit for completion timers [in 4 ns cycles]. Default value is 50 ms in 4 ns cycles. Please note that there could be a variation of 0 to +8us on the programmed Completion Timeout." line.long 0x20 "CORE__DBN_CFG__PCIE_CORE_REG_i_compln_tmout_lim_1_reg,This register contains the timeout value used to detect a completion timeout event for a" hexmask.long 0x20 0.--27. 1. "CTL,Timeout limit for completion timers [in 4 ns cycles]. Default value is 200ms in 4ns cycles. Please note that there could be a variation of 0 to +8us on the programmed Completion Timeout." line.long 0x24 "CORE__DBN_CFG__PCIE_CORE_REG_i_L1_st_reentry_delay_reg,This register specifies the time the Controller will wait before it re-enters the L1 state if" hexmask.long 0x24 0.--31. 1. "L1RD,Delay to re-enter L1 after no activity [in units of 16 ns]." line.long 0x28 "CORE__DBN_CFG__PCIE_CORE_REG_i_vendor_id_reg,This register contains the Vendor ID and Subsystem Vendor ID that the device advertises" hexmask.long.word 0x28 16.--31. 1. "SVID,Subsystem Vendor ID" newline hexmask.long.word 0x28 0.--15. 1. "VID,Vendor ID" line.long 0x2C "CORE__DBN_CFG__PCIE_CORE_REG_i_aspm_L1_entry_tmout_delay_reg,This register defines the timeout value for transitioning to the L1 power state under" bitfld.long 0x2C 31. "DISLNRXCHK,This bit is used to configure the ASPM L1 Entry mechanism: 1: Link is checked for IDLE only on the TX to determine ASPM L1 Entry. ASPM L1 entry is initiated if no TLP is transmitted for the L1 timeout period. 0: Link is.." "0: Link is checked for IDLE both on the TX and RX..,1: Link is checked for IDLE only on the TX to.." newline hexmask.long.tbyte 0x2C 0.--19. 1. "L1T,Contains the timeout value[in units of 16 ns] for transitioning to the L1 power state. Setting it to 0 permanently disables the transition to the L1 power state." line.long 0x30 "CORE__DBN_CFG__PCIE_CORE_REG_i_pme_turnoff_ack_delay_reg,Defines the time interval between the Controller receiving a PME_Turn_Off message from the" hexmask.long.word 0x30 0.--15. 1. "PTOAD,Time in microseconds between the Controller receiving a PME_TurnOff message TLP and the Controller sending a PME_TO_Ack response to it. This field must be set to a non-zero value in order for the Controller to send a response. Setting.." line.long 0x34 "CORE__DBN_CFG__PCIE_CORE_REG_i_linkwidth_control_reg,This register can be used to retrain the link to a different width. without bringing the link down." bitfld.long 0x34 31. "EPLSCRL,Writing a 1 into this field results in the Controller re-training the link to change its speed. When setting this bit to 1 the software must also set the EP Target Link Speed field to indicate the speed that the EP desires to change.." "0,1" newline bitfld.long 0x34 24.--25. "EPTLS,This field contains the Link Speed that the EP intends to change to during the re-training. Client needs to ensure that this field is programmed to a speed which is lesser than or equal to the Target Link Speed field of PF0.." "0: GEN1 01,?,?,?" newline bitfld.long 0x34 19. "DSAG4SC,This bit is used Only in RP mode. This bit is not used in EP mode of the Controller. During initial link training if both components advertise Gen4 capability and if Gen3 speed change equalization was successful the Controller.." "0,1" newline bitfld.long 0x34 18. "DSAG3SC,This bit is used Only in RP mode. This bit is not used in EP mode of the Controller. During initial link training if both components advertise Gen3 capability the Controller [RP] autonomously initiates Gen1 to Gen3 speed change .." "0,1" newline bitfld.long 0x34 17. "DSAG2SC,This bit is used Only in RP mode. This bit is not used in EP mode of the Controller. During initial link training if both components advertise Gen2 capability and if Gen2 is the highest common supported speed the Controller [RP].." "0,1" newline bitfld.long 0x34 16. "RL,Writing a 1 into this field results in the Controller re-training the link to change its width. When setting this bit to 1 the software must also set the target lane-map field to indicate the lanes it desires to be part of the link. The.." "0,1" newline hexmask.long.byte 0x34 0.--3. 1. "TLM,This field contains the bitmap of the lanes to be included in forming the link during the re-training. 0001 - Retrain to a x1 link 0011 - Retrain to a x2 link 1111 - Retrain to a x4 link.." line.long 0x38 "CORE__DBN_CFG__PCIE_CORE_REG_i_pl_config_2_reg,This register controls various LTSSM related capabilities." bitfld.long 0x38 1.--2. "DQMDC,As per PCIe specification All Receivers must meet the the Z-RX-DC specification for 2.5 GT/s within 1ms of entering Detect.Quiet LTSSM substate. The LTSSM must stay in this substate until the ZRX-DC specification for.." "0,1,2,3" newline bitfld.long 0x38 0. "LK_TRN,This bit is AND'ed with the input LINK_TRAINING_ENABLE strap to enable Link Training." "0,1" rgroup.long 0x100070++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_multi_vc_conrol_reg,This register contains control bits to control certain multi VC features" bitfld.long 0x0 1. "WAIT_4_ALL_VC_CC_RDY,When this bit is set the controller waits for credits to be available to be able to send atleast 1 max payload TLP in all enabled VCs. When this bit is not set the controller waits for credits to be available to be.." "0,1" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_sris_control_reg,This register contains control bits to enable the SRIS operation in the PHY Layer" bitfld.long 0x4 0. "SRISE,Setting this bit enables SRIS mode in the PHY layer. This bit should be changed before link training begins by holding the LINK_TRAINING_ENABLE input to 1'b0. When SRIS is disabled using this bit the Lower SKP OS Generation Supported.." "0,1" rgroup.long 0x100080++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_rcv_cred_lim_0_reg_vc1,This register contains the initial credit limits advertised by the Controller during th DL" hexmask.long.word 0x0 20.--31. 1. "NPPC,Non-Posted payload credit limit advertised by the Controller for VC 1 . This field is in units of 4 DWords 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 1. 00b => [units of 4 DWords].." newline hexmask.long.byte 0x0 12.--19. 1. "PHC,Posted header credit limit advertised by the Controller for VC 1. This field is in units of 1 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 1. 00b => [units of 1 Packet Header] 01b => [units of.." newline hexmask.long.word 0x0 0.--11. 1. "PPC,Posted payload credit limit advertised by the Controller for VC 1. This field is in units of 4 DWords 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 1. 00b => [units of 4 DWords] 01b => [units.." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_rcv_cred_lim_1_reg_vc1,This register contains the initial credit limits advertised by the Controller during the DL" hexmask.long.byte 0x4 24.--31. 1. "CHC,Completion header credit limit advertised by the Controller for VC 1 [in number of packets]. This field is in units of 1 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 1. 00b => [units of 1.." newline hexmask.long.word 0x4 8.--19. 1. "CPC,Completion payload credit limit advertised by the Controller for VC 1 . This field is in units of 4 DWords 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 1. 00b => [units of 4 DWords] 01b.." newline hexmask.long.byte 0x4 0.--7. 1. "NPHCL,Non-Posted header credit limit advertised by the Controller for VC 1 [in number of packets]. This field is in units of 1 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 1. 00b => [units of 1.." rgroup.long 0x100088++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_transm_cred_lim_0_reg_vc1,This register contains the initial credit limits received from the opposite node during" hexmask.long.word 0x0 20.--31. 1. "NPPC,Non-Posted payload credit limit received by the Controller for Link 0 . This field is in units of 4 DWords 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 1. 00b => [units of 4 DWords].." newline hexmask.long.byte 0x0 12.--19. 1. "PHC,Posted header credit limit received by the Controller for this link . This field is in units of 1 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 1. 00b => [units of 1 Packet Header] 01b =>.." newline hexmask.long.word 0x0 0.--11. 1. "PPC,Posted payload credit limit received by the Controller for this link . This field is in units of 4 DWords 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 1. 00b => [units of 4 DWords] 01b =>.." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_transm_cred_lim_1_reg_vc1,This register contains the initial credit limits received from the opposite node during" hexmask.long.byte 0x4 24.--31. 1. "CHC,Completion header credit limit received by the Controller for VC 1 . This field is in units of 1 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 1. 00b => [units of 1 Packet Header] 01b => [units.." newline hexmask.long.word 0x4 8.--19. 1. "CPC,Completion payload credit limit received by the Controller for VC 1 . This field is in units of 4 DWords 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 1. 00b => [units of 4 DWords].." newline hexmask.long.byte 0x4 0.--7. 1. "NPHC,Non-Posted header credit limit received by the Controller for VC 1 . This field is in units of 1 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 1. 00b => [units of 1 Packet Header] 01b.." rgroup.long 0x100090++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_rcv_cred_lim_0_reg_vc2,This register contains the initial credit limits advertised by the Controller during th DL" hexmask.long.word 0x0 20.--31. 1. "NPPC,Non-Posted payload credit limit advertised by the Controller for VC 2 . This field is in units of 4 DWords 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 2. 00b => [units of 4 DWords].." newline hexmask.long.byte 0x0 12.--19. 1. "PHC,Posted header credit limit advertised by the Controller for VC 2. This field is in units of 1 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 2. 00b => [units of 1 Packet Header] 01b => [units of.." newline hexmask.long.word 0x0 0.--11. 1. "PPC,Posted payload credit limit advertised by the Controller for VC 2. This field is in units of 4 DWords 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 2. 00b => [units of 4 DWords] 01b => [units.." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_rcv_cred_lim_1_reg_vc2,This register contains the initial credit limits advertised by the Controller during the DL" hexmask.long.byte 0x4 24.--31. 1. "CHC,Completion header credit limit advertised by the Controller for VC 2 [in number of packets]. This field is in units of 1 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 2. 00b => [units of 1.." newline hexmask.long.word 0x4 8.--19. 1. "CPC,Completion payload credit limit advertised by the Controller for VC 2 . This field is in units of 4 DWords 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 2. 00b => [units of 4 DWords] 01b.." newline hexmask.long.byte 0x4 0.--7. 1. "NPHCL,Non-Posted header credit limit advertised by the Controller for VC 2 [in number of packets]. This field is in units of 1 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 2. 00b => [units of 1.." rgroup.long 0x100098++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_transm_cred_lim_0_reg_vc2,This register contains the initial credit limits received from the opposite node during" hexmask.long.word 0x0 20.--31. 1. "NPPC,Non-Posted payload credit limit received by the Controller for Link 0 . This field is in units of 4 DWords 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 2. 00b => [units of 4 DWords].." newline hexmask.long.byte 0x0 12.--19. 1. "PHC,Posted header credit limit received by the Controller for this link . This field is in units of 1 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 2. 00b => [units of 1 Packet Header] 01b =>.." newline hexmask.long.word 0x0 0.--11. 1. "PPC,Posted payload credit limit received by the Controller for this link . This field is in units of 4 DWords 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 2. 00b => [units of 4 DWords] 01b =>.." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_transm_cred_lim_1_reg_vc2,This register contains the initial credit limits received from the opposite node during" hexmask.long.byte 0x4 24.--31. 1. "CHC,Completion header credit limit received by the Controller for VC 2 . This field is in units of 1 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 2. 00b => [units of 1 Packet Header] 01b => [units.." newline hexmask.long.word 0x4 8.--19. 1. "CPC,Completion payload credit limit received by the Controller for VC 2 . This field is in units of 4 DWords 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 2. 00b => [units of 4 DWords].." newline hexmask.long.byte 0x4 0.--7. 1. "NPHC,Non-Posted header credit limit received by the Controller for VC 2 . This field is in units of 1 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 2. 00b => [units of 1 Packet Header] 01b.." rgroup.long 0x1000A0++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_rcv_cred_lim_0_reg_vc3,This register contains the initial credit limits advertised by the Controller during th DL" hexmask.long.word 0x0 20.--31. 1. "NPPC,Non-Posted payload credit limit advertised by the Controller for VC 3 . This field is in units of 4 DWords 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 3. 00b => [units of 4 DWords].." newline hexmask.long.byte 0x0 12.--19. 1. "PHC,Posted header credit limit advertised by the Controller for VC 3. This field is in units of 1 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 3. 00b => [units of 1 Packet Header] 01b => [units of.." newline hexmask.long.word 0x0 0.--11. 1. "PPC,Posted payload credit limit advertised by the Controller for VC 3. This field is in units of 4 DWords 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 3. 00b => [units of 4 DWords] 01b => [units.." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_rcv_cred_lim_1_reg_vc3,This register contains the initial credit limits advertised by the Controller during the DL" hexmask.long.byte 0x4 24.--31. 1. "CHC,Completion header credit limit advertised by the Controller for VC 3 [in number of packets]. This field is in units of 1 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 3. 00b => [units of 1.." newline hexmask.long.word 0x4 8.--19. 1. "CPC,Completion payload credit limit advertised by the Controller for VC 3 . This field is in units of 4 DWords 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 3. 00b => [units of 4 DWords] 01b.." newline hexmask.long.byte 0x4 0.--7. 1. "NPHCL,Non-Posted header credit limit advertised by the Controller for VC 3 [in number of packets]. This field is in units of 1 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 3. 00b => [units of 1.." rgroup.long 0x1000A8++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_transm_cred_lim_0_reg_vc3,This register contains the initial credit limits received from the opposite node during" hexmask.long.word 0x0 20.--31. 1. "NPPC,Non-Posted payload credit limit received by the Controller for Link 0 . This field is in units of 4 DWords 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 3. 00b => [units of 4 DWords].." newline hexmask.long.byte 0x0 12.--19. 1. "PHC,Posted header credit limit received by the Controller for this link . This field is in units of 1 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 3. 00b => [units of 1 Packet Header] 01b =>.." newline hexmask.long.word 0x0 0.--11. 1. "PPC,Posted payload credit limit received by the Controller for this link . This field is in units of 4 DWords 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 3. 00b => [units of 4 DWords] 01b =>.." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_transm_cred_lim_1_reg_vc3,This register contains the initial credit limits received from the opposite node during" hexmask.long.byte 0x4 24.--31. 1. "CHC,Completion header credit limit received by the Controller for VC 3 . This field is in units of 1 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 3. 00b => [units of 1 Packet Header] 01b => [units.." newline hexmask.long.word 0x4 8.--19. 1. "CPC,Completion payload credit limit received by the Controller for VC 3 . This field is in units of 4 DWords 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 3. 00b => [units of 4 DWords].." newline hexmask.long.byte 0x4 0.--7. 1. "NPHC,Non-Posted header credit limit received by the Controller for VC 3 . This field is in units of 1 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 3. 00b => [units of 1 Packet Header] 01b.." rgroup.long 0x1000F0++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_fc_init_delay_reg,This register defines the delay value in between successive FC_INIT DLLPs for VCx." hexmask.long.word 0x0 0.--15. 1. "FCINITDLY,Delay between successive sets of P NP CPL FC_INIT DLLP transmissions for VCx." rgroup.long 0x100100++0x13 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_shdw_hdr_log_0_reg,N/A" hexmask.long 0x0 0.--31. 1. "SHDW_HDR_LOG_0,The value here will be reflected in the target function's header log register when f/w sets any bit in the the shadow error register. If the header log is already set in the function's AER space the value here may not get.." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_shdw_hdr_log_1_reg,N/A" hexmask.long 0x4 0.--31. 1. "SHDW_HDR_LOG_1,The value here will be reflected in the target function's header log register when f/w sets any bit in the the shadow error register. If the header log is already set in the function's AER space the value here may not get.." line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_shdw_hdr_log_2_reg,N/A" hexmask.long 0x8 0.--31. 1. "SHDW_HDR_LOG_2,The value here will be reflected in the target function's header log register when f/w sets any bit in the the shadow error register. If the header log is already set in the function's AER space the value here may not get.." line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_i_shdw_hdr_log_3_reg,N/A" hexmask.long 0xC 0.--31. 1. "SHDW_HDR_LOG_3,The value here will be reflected in the target function's header log register when f/w sets any bit in the the shadow error register. If the header log is already set in the function's AER space the value here may not get.." line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_i_shdw_func_num_reg,N/A" hexmask.long.byte 0x10 0.--7. 1. "SHDW_FUNC_NUM,The value here will be the target function number when f/w sets any bit in the shadow error register." rgroup.long 0x100114++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_shdw_ur_err_reg,Shadow register to create UR error via local f/w. Please make sure this register is written to last. after" bitfld.long 0x0 1. "NP_UR_ERR,If this bit is set the corresponding non-posted UR error bits will be set in the AER and device status registers of the target function." "0,1" newline bitfld.long 0x0 0. "P_UR_ERR,If this bit is set the corresponding posted UR error bits will be set in the AER and device status registers of the target function." "0,1" rgroup.long 0x100140++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_pm_clk_frequency_reg,This register should be programmed with the frequency of the PM_CLK input to the Controller." hexmask.long.byte 0x0 0.--7. 1. "PMCLKFRQ,This field specifies the PM_CLK Frequency selected. The encoding is described below: 000000: Reserved 000001: Reserved 000010: PM_CLK is 2 MHz 000011: PM_CLK is 3 MHz 000100:.." rgroup.long 0x100144++0xF line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_debug_dllp_count_gen1_reg,This register indicates the total number of DLLPs received by the Controller in GEN1." hexmask.long 0x0 0.--31. 1. "DLLPCNT1,Reflects the total number of DLLPs received by the Controller at GEN1 speed." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_debug_dllp_count_gen2_reg,This register indicates the total number of DLLPs received by the Controller in GEN2." hexmask.long 0x4 0.--31. 1. "DLLPCNT2,Reflects the total number of DLLPs received by the Controller at GEN2 speed." line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_debug_dllp_count_gen3_reg,This register indicates the total number of DLLPs received by the Controller in GEN3." hexmask.long 0x8 0.--31. 1. "DLLPCNT3,Reflects the total number of DLLPs received by the Controller at GEN3 speed." line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_i_debug_dllp_count_gen4_reg,This register indicates the total number of DLLPs received by the Controller in GEN4." hexmask.long 0xC 0.--31. 1. "DLLPCNT4,Reflects the total number of DLLPs received by the Controller at GEN4 speed." rgroup.long 0x100158++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_vendor_defined_message_tag_reg,The 8-bit Tag field of the Outbound Vendor Defined Messages. transmitted by the Controller. can be programmed in this register." hexmask.long.byte 0x0 0.--7. 1. "VDMTAG,The Controller will use the tag programed in this register for all Outbound Vendor Defined Messages." rgroup.long 0x100200++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_negotiated_lane_map_reg,This register contains a map of the active lanes used by the Controller to form the link" bitfld.long 0x0 16. "LRS,This bit set by the Controller at the end of link training if the LTSSM had to reverse the lane numbers to form the link." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "NLM,Bit i of this field is set to 1 at the end of link training if Lane i is part of the PCIe link. The value of this field is valid only when the link is in L0 or L0s states." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_receive_fts_count_reg,This register contains the FTS count values received from the link partner during link" hexmask.long.byte 0x4 16.--23. 1. "RFC16S,FTS count received from the other side during link training for use at the 16 GT/s link speed. The Controller transmits this many FTS sequences while exiting the L0S state when operating at the 16 GT/s speed." newline hexmask.long.byte 0x4 8.--15. 1. "RFC8S,FTS count received from the other side during link training for use at the 8 GT/s link speed. The Controller transmits this many FTS sequences while exiting the L0S state when operating at the 8 GT/s speed." newline hexmask.long.byte 0x4 0.--7. 1. "RFC5S,FTS count received from the other side during link training for use at the 5 GT/s link speed. The Controller transmits this many FTS sequences while exiting the L0S state when operating at the 5 GT/s speed." rgroup.long 0x100208++0x23 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_debug_mux_control_reg,N/A" bitfld.long 0x0 31. "EFSRTCA,Setting this bit to 0 causes all the enabled Functions to report an error when a Type-1 configuration access is received by the Controller targeted at any Function. Setting it to 1 limits the error reporting to the type-0 Function.." "0,1" newline bitfld.long 0x0 30. "DOC,Setting this bit to 1 disables the ordering check in the Controller between Completions and Posted requests received from the link." "0,1" newline bitfld.long 0x0 29. "DFCUT,When this bit is 0 the Controller will time out and re-train the link when no Flow Control Update DLLPs are received from the link within an interval of 128 us. Setting this bit to 1 disables this timeout. When the advertised receive.." "0,1" newline bitfld.long 0x0 28. "DEI,Setting this bit to 1 disables the inferring of electrical idle in the L0 state. Electrical idle is inferred when no flow control updates and no SKP sequences are received within an interval of 128 us. This bit should not be set during.." "0,1" newline bitfld.long 0x0 27. "DGLUS,Setting this bit to 1 disables the update of the LFSRs in the Gen3 descramblers of the Controller from the values received in SKP sequences. This bit should not be set during normal operation but is useful for testing." "0,1" newline bitfld.long 0x0 26. "IEDPPE,When set to 1 this bit inverts the parity bits generated by the Controller for end-to-end data protection. This will result in the inversion of parity bits for data payloads delivered through the HAL Target Interface request.." "0,1" newline bitfld.long 0x0 25. "ESPC,When this bit is set to 1 the Controller will capture the Slot Power Limit Value and Slot Power Limit Scale parameters from a Set_Slot_Power_Limit message received in the Device Capabilities Register. When this bit is 0 the capture is.." "0,1" newline bitfld.long 0x0 24. "EFLT,This bit is provided to shorten the link training time to facilitate fast simulation of the design especially at the gate level. Enabling this bit has the following effects: 1. The 1 ms 2 ms 12 ms 24 ms 32 ms and 48 ms timeout.." "0,1" newline bitfld.long 0x0 23. "DLUC,The user may set this bit to turn off the link upconfigure capability of the Controller. Setting this bit prevents the Controller from advertising the link upconfigure capability in training sequences transmitted in the.." "0: Controller drives PIPE_TX_ELEC_IDLE==1 AND..,1: Controller drives PIPE_TX_ELEC_IDLE==1 AND.." newline bitfld.long 0x0 22. "DLRFE,When this bit is 1 the Controller will not transition its LTSSM into the Recovery state when it detects a Framing Error at 8 GT/s or 16 GT/s speed [as defined in Section 4.2.2.3.3 of the PCIe Base Specification 3.0. This bit must.." "0,1" newline bitfld.long 0x0 21. "DSHEC,When this bit is 0 the Controller will signal a framing error if it detects a sync header error in the received blocks at 8 GT/s or 16 GT/s speed [A 00 or 11 binary setting of the sync header on the received blocks in any lane.." "0,1" newline bitfld.long 0x0 20. "DCIVMC,When this bit is 1 the Controller will not check for invalid message codes. This bit should normally set to 0 as the invalid message code checking is mandatory in the PCIe 3.0 specifications." "0,1" newline bitfld.long 0x0 19. "DIOAEFC,When this bit is 1 the Controller will not check for illegal OS after EDS as part of Gen3 Framing Error Checks. This bit should normally set to 0 as this is a mandatory Gen3 Framing Error check in the PCIe 3.0 specifications." "0,1" newline bitfld.long 0x0 18. "DOASFC,When this bit is 1 the Controller will not check for OS after SKIP OS as part of Gen3 Framing Error Checks. This bit should normally set to 0 as this is a mandatory Gen3 Framing Error check in the PCIe 3.0 specifications." "0,1" newline bitfld.long 0x0 17. "HPRSUPP,When this bit is 1 data path parity check is disabled on the TX side of the Controller." "0,1" newline bitfld.long 0x0 16. "AWRPRI,When this bit is 1 the AXI bridge places a write request on the HAL Master interface in preference over a read request if both AXI write and AXI read requests are available to be asserted on the same clock cycle." "0,1" newline bitfld.long 0x0 15. "FDS,Disable Scrambling/Descrambling in Gen1/Gen2." "0,1" newline bitfld.long 0x0 14. "DSSPLM,Disable sending Set Slot Power Limit Message if the Slot Capabilitied register is configured" "0,1" newline rbitfld.long 0x0 13. "R1313,N/A" "0,1" newline rbitfld.long 0x0 12. "R1212,N/A" "0,1" newline bitfld.long 0x0 11. "R1111,When this bit is 1 Disable Client TX MUX Completion and PNP request arbitartion roundrobin priority logic added to prevent PNP requests from starving when completions are present" "0,1" newline bitfld.long 0x0 9. "MSIVCMS,Sets the mode of generating MSI_VECTOR_COUNT output for all functions. 0 - MSI_VECTOR_COUNT always outputs the configured value of MSI Multiple Message Enable[2:0] register. 1 - MSI_VECTOR_COUNT outputs the lesser of the MSI Multiple.." "0: MSI_VECTOR_COUNT always outputs the configured..,1: MSI_VECTOR_COUNT outputs the lesser of the MSI.." newline bitfld.long 0x0 8. "DIDBOC,Setting this bit to 1 disables the ID Based Ordering check in the Controller between Completions and Posted requests received from the link." "0,1" newline bitfld.long 0x0 7. "R77,This bit should be set to 0 for backward compatibility." "0,1" newline rbitfld.long 0x0 5.--6. "R6,N/A" "0,1,2,3" newline hexmask.long.byte 0x0 0.--4. 1. "MS,Bits 4:3 select the module and bits 2:0 select the group of signals within the module that are driven on the debug bus. The assignments of signals on the debug outputs of the Controller are given in Appendix B." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_local_error_status_register,This register contains the status of the various events. errors and abnormal conditions in the" bitfld.long 0x4 31. "REORDER_ER_UN,This indicates an uncorrectbale axi slave reorder ram parity/ecc error" "0,1" newline bitfld.long 0x4 30. "AXISLAVE_WFIFO_ER_UN,This indicates an uncorrectbale axi slave write fifo ram parity/ecc error" "0,1" newline bitfld.long 0x4 29. "AXIMASTER_RFIFO_ER_UN,This indicates an uncorrectbale axi master write fifo ram parity/ecc error" "0,1" newline bitfld.long 0x4 28. "AXIMASTER_DIB_ER_UN,This indicates an uncorrectbale axi slave write fifo ram parity/ecc error" "0,1" newline bitfld.long 0x4 25. "MSIXMSKST,This interrupt status bit is used when MSIX Function Mask Enhanced Interrupt Enable bit is set to 0 by the User. This status bit indicates that the MSIX Function Mask bit of any function PF or VF was programmed or.." "0,1" newline bitfld.long 0x4 21. "HAWCD,This interrupt status bit indicates that the Host toggled the Hardware Autonomous Width Change bit in the Link Control Register through a Config Write. Upon this interrupt the Client firmware must read the Link Control Register to check the.." "0,1" newline bitfld.long 0x4 19. "MMVC,This status bit is set whenever the MSI mask register value in the MSI capability register changes value in ANY of the functions in the controller" "0,1" newline bitfld.long 0x4 18. "UTC,Unmapped TC error." "0,1" newline bitfld.long 0x4 17. "EEPE,The Controller detected an End to End Parity Error" "0,1" newline bitfld.long 0x4 11. "CT,A request timed out waiting for completion." "0,1" newline bitfld.long 0x4 10. "FCE,An error was observed in the flow control advertisements from the other side." "0,1" newline bitfld.long 0x4 9. "UCR,Unexpected Completion received from the link." "0,1" newline bitfld.long 0x4 8. "MTR,Malformed TLP received from the link." "0,1" newline bitfld.long 0x4 7. "PE,Phy error detected on receive side. This bit is set when an error is detected in the receive side of the Physical Layer of the Controller [e.g. a bit error or coding violation]. This bit is set upon any of the following errors:.." "0,1" newline bitfld.long 0x4 6. "RTR,Replay timer rolled over after 4 transmissions of the same TLP." "0,1" newline bitfld.long 0x4 5. "RT,Replay timer timed out" "0,1" newline bitfld.long 0x4 4. "CRFO,Overflow occurred in the Completion Receive FIFO." "0,1" newline bitfld.long 0x4 3. "PRFO,Overflow occurred in the PNP Receive FIFO." "0,1" newline bitfld.long 0x4 2. "RRPE,Parity error detected while reading from Replay Buffer RAM." "0,1" newline bitfld.long 0x4 1. "CRFPE,Parity error detected while reading from the Completion Receive FIFO RAM." "0,1" newline bitfld.long 0x4 0. "PRFPE,Parity error detected while reading from the PNP Receive FIFO RAM." "0,1" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_local_intrpt_mask_reg,This register contains a mask bit for each interrupting condition. Setting the bit to 1" bitfld.long 0x8 31. "REORDER_ER_UN,mask for uncorrectbale axi slave reorder ram parity/ecc error" "0,1" newline bitfld.long 0x8 30. "AXISLAVE_WFIFO_ER_UN,mask for uncorrectbale axi slave write fifo ram parity/ecc error" "0,1" newline bitfld.long 0x8 29. "AXIMASTER_RFIFO_ER_UN,mask for uncorrectbale axi master write fifo ram parity/ecc error" "0,1" newline bitfld.long 0x8 28. "AXIMASTER_DIB_ER_UN,mask for uncorrectbale axi slave write fifo ram parity/ecc error" "0,1" newline bitfld.long 0x8 25. "MSIXMSK,This bit is used to mask interrupt that indicates that the MSIX Function Mask bit of any function PF or VF was programmed or configured by Local Firmware Or Host SW." "0,1" newline bitfld.long 0x8 21. "HAWCD,This bit is used to mask interrupt that indicates that the Host toggled the Hardware Autonomous Width Change in the Endpoint Link Control Register through a Config Write." "0,1" newline bitfld.long 0x8 19. "MMVC,MSI mask register value in the MSI capability register changes value in ANY of the functions in the controller" "0,1" newline bitfld.long 0x8 18. "UTC,Unmapped TC error" "0,1" newline bitfld.long 0x8 17. "EEPE,The Controller detected an End to End Parity Error" "0,1" newline bitfld.long 0x8 11. "CT,A request timed out waiting for completion." "0,1" newline bitfld.long 0x8 10. "FCE,An error was observed in the flow control advertisements from the other side." "0,1" newline bitfld.long 0x8 9. "UCR,Unexpected Completion received from the link." "0,1" newline bitfld.long 0x8 8. "MTR,Malformed TLP received from the link." "0,1" newline bitfld.long 0x8 7. "PE,Phy error detected on receive side." "0,1" newline bitfld.long 0x8 6. "RTR,Replay timer rolled over after 4 transmissions of the same TLP." "0,1" newline bitfld.long 0x8 5. "RT,Replay timer timed out" "0,1" newline bitfld.long 0x8 4. "CRFO,Overflow occurred in the Completion Receive FIFO." "0,1" newline bitfld.long 0x8 3. "PRFO,Overflow occurred in the PNP Receive FIFO." "0,1" newline bitfld.long 0x8 2. "RRPE,Parity error detected while reading from Replay Buffer RAM." "0,1" newline bitfld.long 0x8 1. "CRFPE,Parity error detected while reading from the Completion Receive FIFO RAM." "0,1" newline bitfld.long 0x8 0. "PRFPE,Parity error detected while reading from the PNP Receive FIFO RAM." "0,1" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_i_lcrc_err_count_reg,This register contains the count of the number of TLPs received by the Controller with LCRC" hexmask.long.word 0xC 0.--15. 1. "LEC,Number of TLPs received with LCRC errors." line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_i_ecc_corr_err_count_reg,This register contains the count of the number of ECC errors detected and corrected" hexmask.long.byte 0x10 16.--23. 1. "RRCER,Number of correctable errors detected while reading from the Replay Buffer RAM. This is an 8-bit saturating counter that can be cleared by writing all 1's into it." newline hexmask.long.byte 0x10 8.--15. 1. "SFRCER,Number of correctable errors detected while reading from the SC FIFO RAM. This is an 8-bit saturating counter that can be cleared by writing all 1's into it." newline hexmask.long.byte 0x10 0.--7. 1. "PFRCER,Number of correctable errors detected while reading from the PNP FIFO RAM. This is an 8-bit saturating counter that can be cleared by writing all 1's into it." line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_i_ltr_snoop_lat_reg,This register contains the Snoop and No-Snoop Latency parameters used by the Controller when" bitfld.long 0x14 31. "SL,The client software must set this bit to 1 to set the Snoop Latency Requirement bit in the LTR message to be sent." "0,1" newline bitfld.long 0x14 26.--28. "SLS,The client software must program this field with the value to be sent in the Snoop Latency Scale field of the LTR message." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--25. 1. "SLV,The client software must program this field with the value to be sent in the Snoop Latency Value field of the LTR message." newline bitfld.long 0x14 15. "NSLR,The client software must set this bit to 1 to set the No-Snoop Latency Requirement bit in the LTR message to be sent." "0,1" newline rbitfld.long 0x14 13.--14. "R12,N/A" "0,1,2,3" newline bitfld.long 0x14 10.--12. "NSLS,The client software must program this field with the value to be sent in the No-Snoop Latency Scale field of the LTR message." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 0.--9. 1. "NSLV,The client software must program this field with the value to be sent in the No-Snoop Latency Value field of the LTR message." line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_i_ltr_msg_gen_ctl_reg,This register contains fields for the generation of Latency Tolerance Reporting (LTR)" bitfld.long 0x18 12. "TMFPSC,When this bit is set to 1 the Controller will automatically transmit an LTR message when all the Functions in the Controller have transitioned to a non-D0 power state provided that the following conditions are both true: 1. The.." "0,1" newline bitfld.long 0x18 11. "TMLMET,When this bit is set to 1 the Controller will automatically transmit an LTR message whenever the LTR Mechanism Enable bit in the Device Control 2 Register changes from 0 to 1 with the parameters specified in the LTR Snoop/No-Snoop.." "0,1" newline rbitfld.long 0x18 10. "SLM,Setting this bit causes the Controller to transmit an LTR message with the parameters specified in the LTR Snoop/No-Snoop Latency Register [Section 8.4.2.9]. This bit is cleared by the Controller on transmitting the LTR message and stays.." "0,1" newline hexmask.long.word 0x18 0.--9. 1. "MLI,This field specifies the minimum spacing between LTR messages transmitted by the Controller in units of microseconds. The PCI Express Specifications recommend sending no more than two LTR messages within a 500 microsecond interval. The.." line.long 0x1C "CORE__DBN_CFG__PCIE_CORE_REG_i_pme_service_timeout_delay_reg,This register stores the timeout delay parameter for the service timeout mechanism" bitfld.long 0x1C 20. "DPMOPS,When this bit is set Controller will not automatically send a PME message when PM Status bit in PMCSR register is set" "0,1" newline hexmask.long.tbyte 0x1C 0.--19. 1. "PSTD,Specifies the timeout delay for retransmission of PM_PME messages. The value is in units of microseconds. The actual time elapsed has a +1 microseconds tolerance from the value programmed." line.long 0x20 "CORE__DBN_CFG__PCIE_CORE_REG_i_root_port_requestor_id_reg,When the Controller is configured as Root Complex. this ID will be used for all internally" hexmask.long.word 0x20 0.--15. 1. "RPRI,RID [bus device and function numbers] for all TLPs internally generated by Root Port" rgroup.long 0x10022C++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_ep_bus_device_number_reg,When the Controller is configured as End Point. this register holds the Bus and Device number" hexmask.long.byte 0x0 8.--15. 1. "EPBN,Bus Number captured by Function 0 in End Point mode" newline hexmask.long.byte 0x0 0.--4. 1. "EPDN,Device Number captured by Function 0 in End Point mode" rgroup.long 0x100234++0xB line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_debug_mux_control_2_reg,N/A" bitfld.long 0x0 31. "HRLT,If set this bit makes the HOT_RESET_OUT signal behave as a level signal rather than a pulse. When set the HOT_RESET_OUT will be asserted as long as the controller is in the HOT Reset state." "0,1" newline bitfld.long 0x0 29. "DRXRMFR,By default when an Uncorrectable error is detected on a receive FIFO RAM then no packets are read out of the RAM subsequent to the error and the RAMs are frozen. 0 : Receive FIFO RAMs are frozen after.." "0: Receive FIFO RAMs are frozen after an..,1: Receive FIFO RAMs continue to read subsequent.." newline bitfld.long 0x0 28. "DFLRTRB,1 : NP Termination due to FLR/Completion Timeout is delayed till the RX Completion FIFO is Empty. 0 : NP Termination due to FLR is done immediately on receiving FLR/Completion Timeout." "0: NP Termination due to FLR is done immediately on..,1: NP Termination due to FLR/Completion Timeout is.." newline bitfld.long 0x0 27. "DTAE2EP,By default when End to End Parity error is detected on inbound/outbound data streams then all the transmitted outbound packets will be Nullified by the Controller. This bit can be used to turn off nullifying Tx.." "0,1" newline bitfld.long 0x0 25. "MSIXMSKEN,By default the Controller provides a single status bit when any function's MSIX Function Mask is programmed or configured by Local firmware or Host SW. Controller also implements an enhanced MSIX Function Mask.." "0,1" newline bitfld.long 0x0 24. "MSIMSKEN,By default the Controller provides a single status bit when any function's MSI Mask is programmed or configured by Local firmware or Host SW. Controller also implements an enhanced MSI Mask Interrupt mechanism which.." "0,1" newline bitfld.long 0x0 23. "VARCCLKEN,If this bit is set the CORE_CLK input can be driven with Variable Clock depending on the Link Speed similar to the PIPE_PCLK." "0,1" newline hexmask.long.word 0x0 13.--22. 1. "MAXNPREQ,The Controller supports 32 outstanding NP requests that can be initiated by the User. However the number of split completion TLPs that can be stored in the Controller is limited to 128. The Completion FIFO will.." newline bitfld.long 0x0 11. "CMPTOADV,As per PCIe specification on Error Signaling the Requester detecting a Completion Timeout is allowed to handle this as an Advisory Non Fatal Error. 1: Completion Timeout is handled as Advisory Non-Fatal Error." "0: Completion Timeout is handled as normally as a..,1: Completion Timeout is handled as Advisory.." newline bitfld.long 0x0 10. "PSNADV,As per PCIe specification 2.7.2.2 the following Poisoned TLP requests must be handled as Uncorrectable and not as Advisory: I/O Write Request Memory Write Request or non-vendor-defined Message with data that target a Control.." "0: Poisoned TLP of type IOWr,1: Poisoned TLP of type IOWr" newline bitfld.long 0x0 9. "MSIPIMS,If the Client wishes to use the MSI_PENDING_STATUS_IN Signal to Update the MSI pending Bits register this bit needs to be set to 1. Otherwise the Pending Bits register is updated via the APB Interface" "0,1" newline bitfld.long 0x0 8. "ENG4REV05,When operating in Gen4 16GT/s This Enables Gen4 Spec Revision 0.5 EIEOS and SKP features. When disabled the Gen4 1.0 features are enabled by default this bit is ZERO. 1: Enable Gen4 0.5 Features.." "0: Disable Gen4 0,1: Enable Gen4 0" newline bitfld.long 0x0 6.--7. "BLKALNWIN,When in the data stream at Gen3 or higher speeds the pipe_rx_valid is asserted by the PHY. If the block alignment is lost then the PHY may deassert pipe_rx_valid. Controller reports loss of block alignment if.." "0,1,2,3" newline bitfld.long 0x0 5. "BLKALNCHK,When in the data stream at Gen3 or higher speeds the pipe_rx_valid is asserted by the PHY. If the block alignment is lost then the PHY may deassert pipe_rx_valid. Block Alignment may be lost if the received sync.." "0: Enable check for loss of Gen3 Block Alignment..,1: Disable check for loss of Gen3 Block Alignment" newline bitfld.long 0x0 4. "ARICAPMOD,As per SR IOC specification ARI Capable Hierarchy bit is only present in the lowest numbered PF of a Device. The Controller has two modes to determine the lowest numbered PF. 0: the first PF which is enabled [PF0].." "0: the first PF which is enabled [PF0] is taken as..,1: the first PF which has a non-zero TOTAL_VF_COUNT.." newline bitfld.long 0x0 3. "ENLNCHK,As per PCIe specification LTSSM should transition to Disabled after any Lanes that are transmitting TS1 Ordered Sets receive two consecutive TS1 Ordered Sets with the Disable Link bit asserted. Similarly LTSSM should.." "0,1" newline bitfld.long 0x0 2. "DISSDSCHK,As per PCIe specification When using 128b/130b encoding next state is L0 if eight consecutive Symbol Times of Idle data are received on all configured Lanes. The Controller checks to ensure that the Idle symbols of.." "0,1" newline bitfld.long 0x0 1. "EXTSNP,This bit can be set if an extra clock cycle is required by the Client Application logic to respond with the Read Data on Configuration Snoop Interface. Please refer to the user guide section on Configuration Snoop.." "0,1" newline bitfld.long 0x0 0. "DLFFS,As per PIPE 4.2 specification the LOCALLF LOCALFS outputs from PHY can be sampled uponf PHYSTATUS pulse after Reset# OR upon the first PHYSTATUS pulse after speed change to GEN3. This bit can be set to 1 to disable.." "0,1" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_phy_status_1_reg,This status register provides additional debug information about the PHY. Bits 8:0" bitfld.long 0x4 8. "LOSBLKALN,This bit is set if the PHY Loses Block Alignment during data stream. This is detected based upon an unexpected PIPE_RX_VALID input deassertion during data stream. Write a 1 to clear this error." "0,1" newline bitfld.long 0x4 7. "INVSYNHR,This bit is set if an invalid Sync Header is detected. 00 and 11 are Invalid Sync Headers. Write a 1 to clear this error. ." "0,1" newline bitfld.long 0x4 6. "OSAFSDS,This bit is set if an SDS is received after an SDS. This is a framing error. Write a 1 to clear this error." "0,1" newline bitfld.long 0x4 5. "G3FRERR,This bit is set if a framing error is detected while receiving a TLP in Gen3. Example if an invalid token is received in a data stream this error is flagged. Write a 1 to clear this error." "0,1" newline bitfld.long 0x4 4. "OSWOEDS,This bit is set if an Ordered Set Block is received without an EDS. This is a framing error. Write a 1 to clear this error." "0,1" newline bitfld.long 0x4 3. "DATEDS,This bit is set if a Data Block is received after an EDS. Write a 1 to clear this error." "0,1" newline bitfld.long 0x4 2. "ILOSEDS,The Valid OS blocks after an EDS are EIOS EIEOS and SKP. If any other OS blocks are received after EDS then it is a framing error and this bit is asserted." "0,1" newline bitfld.long 0x4 1. "OSASKP,This bit indicates that an Ordered Set BLock was received immediately after a SKIP OS. This is a framing error. Write a 1 to clear this field." "0,1" newline bitfld.long 0x4 0. "TLPPHYER,This bit indicates that a PHY Error was detected on the PIPE_RX_STATUS within a TLP. Write a 1 to clear this field." "0,1" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_debug_mux_control_3_reg,N/A" bitfld.long 0x8 4. "DRC,USed to disable and enable the RCB checker and by default it is enabled" "0,1" newline bitfld.long 0x8 3. "DSDES,Used to disable and enable Surprise Down Error status logging and by default it is enabled" "0,1" newline bitfld.long 0x8 2. "DLTE,Used to disable and enable link training error logging and by default it is enabled" "0,1" newline bitfld.long 0x8 1. "DGDPC,To disable GEN4 data parity check from LM register" "0,1" rgroup.long 0x100300++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_rc_BAR_config_reg,The root complex side of the Controller contains two memory BARs that can be used for" bitfld.long 0x0 31. "RCBCE,This bit must be set to 1 to enable BAR checking in the RC mode. When this bit is set to 0 the Controller will forward all incoming memory requests to the client logic without checking their address ranges." "0,1" newline bitfld.long 0x0 20. "RCBARPIS,Width of IO Base and Limit registers in type1 config space. 0=32 bits 1=64bits" "0,1" newline bitfld.long 0x0 19. "RCBARPIE,Enable for IO Base and Limit registers in type1 config space" "0,1" newline bitfld.long 0x0 18. "RCBARPMS,Width of Prefetchable Memory Base and Limit registers in type1 config space. 0=32 bits 1=64bits" "0,1" newline bitfld.long 0x0 17. "RCBARPME,Enable for Prefetchable memory base and limit registers in type1 config space" "0,1" newline bitfld.long 0x0 14.--16. "RCBAR1C,Specifies the configuration of RC BAR1. The various encodings are: 000: Disabled 001: 32bit IO BAR 010-011: Reserved 100: 32bit memory BAR non prefetchable 101: 32bit memory BAR prefetchable 110-111: Reserved" "0: Disabled,?,?,?,?,?,?,?" newline hexmask.long.byte 0x0 9.--13. 1. "RCBAR1A,This field specifies the aperture of the RC BAR 1. The encodings are: 0000 = 4 00001 =8B ..... 1_1101 = 2G" newline bitfld.long 0x0 6.--8. "RCBAR0C,Specifies the configuration of RC BAR0. The various encodings are: 000: Disabled 001: 32bit IO BAR 010-011: Reserved 100: 32bit memory BAR non prefetchable 101: 32bit memory BAR prefetchable 110: 64bit memory.." "0: Disabled,?,?,?,?,?,?,?" newline hexmask.long.byte 0x0 0.--5. 1. "RCBAR0A,This field specifies the aperture of the RC BAR 0. The encodings are: 0000 = 4 00001 =8B ..... 01_1111 = 8G ....10_0100 = 256G." rgroup.long 0x100360++0xB line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_gen3_default_preset_reg,This is register specifies the default transmitter preset and" hexmask.long.word 0x0 8.--18. 1. "S8GPR,This register can be used to program the Presets that are supported by local Transmitter at 8Gbps. Default value of this register is determined by the SUPPORTED_PRESET strap input. Note: At 8.0 GT/s and.." newline bitfld.long 0x0 4.--6. "GDRXPH,Default receiver preset hint value used for a lane that did not receive EQ TS2 in Recovery.RcvrCfg LTSSM state" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "GDTXP,Default transmitter preset value used for a lane that did not receive EQ TS2 in Recovery.RcvrCfg LTSSM state" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_gen3_gen4_link_eq_timeout_2ms_reg,This register is used to tune the time spent for evaluation per TX Setting in Endpoint Phase 2 (RC Mode Phase 3) of GEN3. GEN4 Link Equalization." bitfld.long 0x4 30.--31. "RXEQABM,When a 24ms timeout occurs in the LTSSM Equalization Phase 2 the Controller aborts Equalization Phase 2 and transitions to Recovery.Rcvr.Lock. In this case the RxEqEval output on the PIPE Interface will be.." "0: Wait for a maximum of 4 PIPE_PCLK period,1: Wait for a maximum of 8 PIPE_PCLK period,?,?" newline bitfld.long 0x4 29. "RXEQABD,In an unexpected case where the PIPE_PCLK stops due to error in equalization this bit can be set to de-couple RxEqInProgress from the rest of the equalization state machine. This bit should not be set for normal usage." "0,1" newline hexmask.long 0x4 0.--27. 1. "LEQT2MS,Time spent for evaluation per TX Setting in Endpoint Phase 2 [RC Mode Phase 3] of Link Equalization specified in multiples of 16ns. eg. the value 125000 will result in 125000*16ns = 2ms. Simulation with reduced time.." line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_pipe_fifo_latency_ctrl_reg,This is register includes bits to control pipe fifo latency" bitfld.long 0x8 1. "DPRFLR,0: If FIFO empty is reached the PIPE RX FIFO accumulates 2 entries before reading the FIFO again. 1: If FIFO empty is reached the PIPE RX FIFO accumulates 6 entries before reading the FIFO again. This is to prevent.." "0: If FIFO empty is reached,1: If FIFO empty is reached" newline bitfld.long 0x8 0. "DPTFCE,By default if FIFO empty is reached the PIPE TX FIFO accumulates 2 entries before reading the FIFO again. This is to prevent FIFO from reaching empty again. This bit must remain at 0 to allow the PIPE.." "0,1" rgroup.long 0x100374++0xB line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_gen4_default_preset_reg,This is register specifies the default transmitter preset and" hexmask.long.word 0x0 8.--18. 1. "S16GPR,This register can be used to program the Presets that are supported by local Transmitter at 16Gbps. Default value of this register is determined by the SUPPORTED_PRESET strap input. Note: At 8.0 GT/s and.." newline bitfld.long 0x0 4.--6. "GDRXPH,Default Gen4 receiver preset hint value used for a lane that did not receive 16G EQ TS2 in Recovery.RcvrCfg LTSSM state" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "GDTXP,Default Gen4 transmitter preset value used for a lane that did not receive 16G EQ TS2 in Recovery.RcvrCfg LTSSM state" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_phy_config_reg3,This is register specifies the PHY Specific registers for used in Gen4" hexmask.long.byte 0x4 0.--7. 1. "TFC4,FTS count transmitted by the Controller in TS1/TS2 sequences during link training. This value must be set based on the time needed by the receiver to acquire sync while exiting from L0S state at 16 GT/s speed." line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_gen3_gen4_link_eq_ctrl_reg,This register is used to Control GEN3. GEN4 Link Equalization Procedure." hexmask.long.byte 0x8 16.--19. 1. "MX16GERL,The number of 16GT/s Equalization Requests must be finite as per PCIe specification. This register can be used to program the maximum number of 16GT/s equalization requests automatically initiated by the Endpoint. 0000: Automatic.." newline hexmask.long.byte 0x8 12.--15. 1. "MX8GERL,The number of 8GT/s Equalization Requests must be finite as per PCIe specification. This register can be used to program the maximum number of 8GT/s equalization requests automatically initiated by the Endpoint. 0000: Automatic 8GT/s.." newline bitfld.long 0x8 9. "QG16GT,This bit can be used to program the Quiesce Guarantee bit of the TS2 in Recovery.Rcvr.Cfg state during 16GT/s Request Equalization." "0,1" newline bitfld.long 0x8 8. "QG8GT,This bit can be used to program the Quiesce Guarantee bit of the TS2 in Recovery.Rcvr.Cfg state during 8GT/s Request Equalization." "0,1" newline bitfld.long 0x8 5. "EP16GRE,Writing a 1 into this field results in the Controller to transition to Recovery. The Request Equalization bit and Equalization Request Data Rate bit in TS2 Ordered Sets will be set to 1 in Recovery.Rcvr.Cfg to request equalization at.." "0,1" newline bitfld.long 0x8 4. "EP8GRE,This bit can be used by Endpoint Device FW to request for 8GT/s Equalization redo. This bit can be set at any time after the Link is Up. Writing a 1 into this field results in the Controller to transition to Recovery. The Request.." "0,1" newline bitfld.long 0x8 0.--2. "MXECC,Controls the number of consecutive RxEqEval iterations with direction change feedback of 00s before Equalization Convergence is inferred. 0 : Infer Convergence after 1 feedback of 000000 1 : Infer Convergence after 2.." "0: Infer Convergence after 1 feedback of 000000,1: Infer Convergence after 2 feedback of 000000,2: Infer Convergence after 3 consecutive feedback..,?,?,?,?,7: Infer Convergence after 8 consecutive feedback.." rgroup.long 0x100380++0xF line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_gen3_link_eq_debug_status_reg_lane0,This register is used to reflect the negotiated TX Preset. Coefficients at the end of GEN3 Link Equalization." hexmask.long.tbyte 0x0 8.--25. 1. "LEQTXCO,TX Coefficients agreed upon for this lane. [25:20] : Post Cursor Coefficient [19:14] : Cursor Coefficient [13:8] : Pre-Cusror Coefficient" newline bitfld.long 0x0 4. "LEQTXPRV,TX Preset Valid Indicator. This bit is set when a TX Preset is received in TS1s with the use_preset bit set in Endpoint Mode Phase 3 or RC Mode Phase 2." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "LEQTXPR,TX Preset agreed upon for this lane" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_gen3_link_eq_debug_status_reg_lane1,This register is used to reflect the negotiated TX Preset. Coefficients at the end of GEN3 Link Equalization." hexmask.long.tbyte 0x4 8.--25. 1. "LEQTXCO,TX Coefficients agreed upon for this lane. [25:20] : Post Cursor Coefficient [19:14] : Cursor Coefficient [13:8] : Pre-Cusror Coefficient" newline bitfld.long 0x4 4. "LEQTXPRV,TX Preset Valid Indicator. This bit is set when a TX Preset is received in TS1s with the use_preset bit set in Endpoint Mode Phase 3 or RC Mode Phase 2." "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "LEQTXPR,TX Preset agreed upon for this lane" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_gen3_link_eq_debug_status_reg_lane2,This register is used to reflect the negotiated TX Preset. Coefficients at the end of GEN3 Link Equalization." hexmask.long.tbyte 0x8 8.--25. 1. "LEQTXCO,TX Coefficients agreed upon for this lane. [25:20] : Post Cursor Coefficient [19:14] : Cursor Coefficient [13:8] : Pre-Cusror Coefficient" newline bitfld.long 0x8 4. "LEQTXPRV,TX Preset Valid Indicator. This bit is set when a TX Preset is received in TS1s with the use_preset bit set in Endpoint Mode Phase 3 or RC Mode Phase 2." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "LEQTXPR,TX Preset agreed upon for this lane" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_i_gen3_link_eq_debug_status_reg_lane3,This register is used to reflect the negotiated TX Preset. Coefficients at the end of GEN3 Link Equalization." hexmask.long.tbyte 0xC 8.--25. 1. "LEQTXCO,TX Coefficients agreed upon for this lane. [25:20] : Post Cursor Coefficient [19:14] : Cursor Coefficient [13:8] : Pre-Cusror Coefficient" newline bitfld.long 0xC 4. "LEQTXPRV,TX Preset Valid Indicator. This bit is set when a TX Preset is received in TS1s with the use_preset bit set in Endpoint Mode Phase 3 or RC Mode Phase 2." "0,1" newline hexmask.long.byte 0xC 0.--3. 1. "LEQTXPR,TX Preset agreed upon for this lane" rgroup.long 0x1003C0++0xF line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_gen4_link_eq_debug_status_reg_lane0,This register is used to reflect the negotiated TX Preset. Coefficients at the end of GEN4 Link Equalization." hexmask.long.tbyte 0x0 8.--25. 1. "LEQTXCO,TX Coefficients agreed upon for this lane. [25:20] : Post Cursor Coefficient [19:14] : Cursor Coefficient [13:8] : Pre-Cusror Coefficient" newline bitfld.long 0x0 4. "LEQTXPRV,TX Preset Valid Indicator. This bit is set when a TX Preset is received in TS1s with the use_preset bit set in Endpoint Mode Phase 3 or RC Mode Phase 2." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "LEQTXPR,TX Preset agreed upon for this lane" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_gen4_link_eq_debug_status_reg_lane1,This register is used to reflect the negotiated TX Preset. Coefficients at the end of GEN4 Link Equalization." hexmask.long.tbyte 0x4 8.--25. 1. "LEQTXCO,TX Coefficients agreed upon for this lane. [25:20] : Post Cursor Coefficient [19:14] : Cursor Coefficient [13:8] : Pre-Cusror Coefficient" newline bitfld.long 0x4 4. "LEQTXPRV,TX Preset Valid Indicator. This bit is set when a TX Preset is received in TS1s with the use_preset bit set in Endpoint Mode Phase 3 or RC Mode Phase 2." "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "LEQTXPR,TX Preset agreed upon for this lane" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_gen4_link_eq_debug_status_reg_lane2,This register is used to reflect the negotiated TX Preset. Coefficients at the end of GEN4 Link Equalization." hexmask.long.tbyte 0x8 8.--25. 1. "LEQTXCO,TX Coefficients agreed upon for this lane. [25:20] : Post Cursor Coefficient [19:14] : Cursor Coefficient [13:8] : Pre-Cusror Coefficient" newline bitfld.long 0x8 4. "LEQTXPRV,TX Preset Valid Indicator. This bit is set when a TX Preset is received in TS1s with the use_preset bit set in Endpoint Mode Phase 3 or RC Mode Phase 2." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "LEQTXPR,TX Preset agreed upon for this lane" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_i_gen4_link_eq_debug_status_reg_lane3,This register is used to reflect the negotiated TX Preset. Coefficients at the end of GEN4 Link Equalization." hexmask.long.tbyte 0xC 8.--25. 1. "LEQTXCO,TX Coefficients agreed upon for this lane. [25:20] : Post Cursor Coefficient [19:14] : Cursor Coefficient [13:8] : Pre-Cusror Coefficient" newline bitfld.long 0xC 4. "LEQTXPRV,TX Preset Valid Indicator. This bit is set when a TX Preset is received in TS1s with the use_preset bit set in Endpoint Mode Phase 3 or RC Mode Phase 2." "0,1" newline hexmask.long.byte 0xC 0.--3. 1. "LEQTXPR,TX Preset agreed upon for this lane" rgroup.long 0x100C80++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_ecc_corr_err_count_reg_axi,This register contains the count of the number of ECC errors detected and corrected" hexmask.long.byte 0x0 24.--31. 1. "AXI_MASTER_DIB_CER,Number of correctable errors detected while reading from the AXI Master Read Data interleave RAM. This is an 8-bit saturating counter that can be cleared by writing all 1s into it." newline hexmask.long.byte 0x0 16.--23. 1. "AXI_MASTER_RFIFO_CER,Number of correctable errors detected while reading from the AXI master read fifo RAM. This is an 8-bit saturating counter that can be cleared by writing all 1's into it." newline hexmask.long.byte 0x0 8.--15. 1. "AXI_SLAVE_WFIFO_CER,Number of correctable errors detected while reading from the AXI slave write fifo RAM. This is an 8-bit saturating counter that can be cleared by writing all 1's into it." newline hexmask.long.byte 0x0 0.--7. 1. "REORDER_CER,Number of correctable errors detected while reading from the AXI slave reorder RAM. This is an 8-bit saturating counter that can be cleared by writing all 1's into it." rgroup.long 0x100C88++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_low_power_debug_and_control0,This register controls internal behavior of controller for low power operations." bitfld.long 0x0 27. "L1DLEUP,Pending Tlps trigger a L1 exit by default. This includes internaly generated messages and internaly blocked TLPs. Setting this bit changes the default behavior. This is required only for debug purpose." "0,1" newline rbitfld.long 0x0 25.--26. "L1EM,This field shows the last entered L1 mode. This is useful for debug. bit 0 - Entry mode was ASPM. Bit 1 - Entry mode was PM. This is reset before any new L1 entry." "0: Entry mode was ASPM,1: Entry mode was PM,?,?" newline bitfld.long 0x0 24. "L1DBRI,Before entering L1 controller internally blocks all TLP and Register Request interface entering controller. interfaces are internally unblocked while exiting L1. This field control this behavior. '1' in this field.." "0,1" newline hexmask.long.tbyte 0x0 0.--23. 1. "L1XDELAY,Normaly L1 substate entry process is initiated immedaitely after LTSSM enters L1. A delay in micro-seconds can be given in this field to delay L1 substate entry process. This timeout has 0-1us margin of error." rgroup.long 0x100C8C++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_low_power_debug_and_control1,This register controls internal behavior of controller for low power operations." hexmask.long.byte 0x0 0.--7. 1. "L1ER,This field shows the values of possible L1 or L1-substate exit triggers. This is useful for debug. this is captured during L1 or L1-substate exit process. this field is reset during L1 entry. 0 : CLIENT_REQ_EXIT_L1.." rgroup.long 0x100C90++0xF line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_low_power_debug_and_control2,This register controls internal behavior of controller for low power operations." bitfld.long 0x0 31. "L1UPACR,Setting this field make the state machine to consider LP_CTRL_POWER_RECOVER_ACK as Client system recovery Complete ACK instead of the Controller power stable ACK. This field is ignored if LP_CTRL_BYPASS_ENABLE unset. If this field is set .." "?,1: substate machines expect that the client system.." newline bitfld.long 0x0 30. "L1CSC,L1-substate removes CORE_CLK. since the registers are implemented in core-clk register access is not possible during L1-substate. If client can supply a slow clock to core[CORE_CLK] during L1-substates APB/mgmt access is possible in.." "?,1: substate and perform register writes" newline bitfld.long 0x0 29. "L1DAET,L1.x turns off clocks to the controller. Default behavior is made to exit L1.x if Register access request is present at register interface. Setting this bit disables this feature. If this bit is set and CLKREQ_IN_N is.." "0,1" newline rbitfld.long 0x0 28. "L1TROW,This is a debug status field. '1' in this field indicates that a timeout has occured while waiting for RX path or OUTstanding packet IDLE conditions. This is cleared on new entry to L1." "0,1" newline bitfld.long 0x0 27. "L1PS,This field enabled power shutoff mechanism in L1.2 state. This field is ignored if L1.x is not enabled. Power on reset value of this register can be adjusted by modifying the define den_db_LP_DBG_CTRL_POWER_SHUTOFF_ENABLE" "0,1" newline bitfld.long 0x0 26. "L1ERC,Enables waiting for RX path IDLE condition before entering L1.x. This checks that all packets from PCIE link has reached client side before entering L1.x. This only a tuning register. Not setting this regsiter will.." "0,1" newline bitfld.long 0x0 25. "L1EOC,Enable waiting for outstanding completions before entering L1.x. Outstanding packets expected from pcie link as well as from AXI side is checked. FOR HAL configurations client has to assert PREVENT_L1x_ENTRY signal to.." "0,1" newline hexmask.long.tbyte 0x0 0.--23. 1. "L1TWROI,This field enables a timeout mechanism while waiting for RX buffers and Outstanding Pkts before turning off power. Controller enters L1 substate after timeout. A value of 0x0 disables this timeout mechanism." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_tl_internal_control,This register controls internal behavior of Transaction layer of controller." bitfld.long 0x4 1. "DOOC,Ordering between outbound Completions and posted packets are maintainted in transaction layer. This is achieved by blocking Completions if required. Completions arrived after EOP of a posted packet are blocked till that posted packet is transmitted." "0,1" newline bitfld.long 0x4 0. "ECFLR,By default controller ignores config request if a function is under going FLR. Setting this bit Makes the controller to respond with CRS response. Power on reset value of this register can be adjusted by modifying the.." "0,1" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_dti_ats_status,This register is for reporting different error conditions/ State in DTI ATS Master" hexmask.long.byte 0x8 17.--21. 1. "ITAG,Itag value which timed out" newline rbitfld.long 0x8 16. "CONSTATE,When set indicates the DTI Master in connected state" "0,1" newline bitfld.long 0x8 3. "ITAGTIMEOUT,When set indicates a timeout in one of the invalidation tags. Invalidation Tag timeout duration = INVTIMERCF * 16ns * INVTIMERCC" "0,1" newline bitfld.long 0x8 2. "INVREQIGNORED,When set indicates that the invalidation request is ignored internally by the DTI Master block" "0,1" newline bitfld.long 0x8 1. "NOTAG,When set indicates the DTI Slave returned an error for the connection request due to non availability of tags." "0,1" newline bitfld.long 0x8 0. "WRONGITAG,When set indicates that the itag field is wrong in the invalidation completion message." "0,1" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_i_dti_ats_ctrl,This register is for the control of DTI ATS Master" bitfld.long 0xC 29. "LDCTRL,This bit when programmed to 1 sends a disconnect request when link down reset happens and sends a connect request when link down indication bit is cleared." "0,1" newline bitfld.long 0xC 28. "DISCONREQ,When set DTI Master triggers a disconnect sequence to the DTI Slave. This bit gets reset to 0 when the DTI master establishes a disconnection." "0,1" newline bitfld.long 0xC 27. "CONREQ,When set DTI Master triggers a connect sequence to the DTI Slave. This bit gets reset to 0 when the DTI master establishes a connection." "0,1" newline hexmask.long.byte 0xC 20.--26. 1. "INVTIMERCC,This is a coarse value which the individual invalidation timers check for reporting a timeout" newline hexmask.long.tbyte 0xC 0.--19. 1. "INVTIMERCF,This is a master counter timeout value which triggers the invalidation tag timers to increment if an active invalidation request is present" rgroup.long 0x100CC0++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_scaled_flow_control_mgmt_vc_select_reg,Scaled Flow Control registers are implemented per VC. The VC is selected using this" hexmask.long.byte 0x0 0.--3. 1. "SFCVCS,The scaled flow management rgeister is implemented per VC. However to limit the number of registers only one VC can be accessed at a time. This register is used to select the VC for which Scaled Flow Control.." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_scaled_flow_control_mgmt_reg,Scaled Flow Control management register. For multi-VC configurations. this register" rbitfld.long 0x4 26.--27. "RCPCS,This register reflects the Completion Payload Credit Scale that is advertised by the remote end device during DL Feature Exchange." "0,1,2,3" newline rbitfld.long 0x4 24.--25. "RCHCS,This register reflects the Completion Header Credit Scale that is advertised by the remote end device during DL Feature Exchange." "0,1,2,3" newline rbitfld.long 0x4 22.--23. "RNPPCS,This register reflects the Non Posted Payload Credit Scale that is advertised by the remote end device during DL Feature Exchange." "0,1,2,3" newline rbitfld.long 0x4 20.--21. "RNPHCS,This register reflects the Non Posted Header Credit Scale that is advertised by the remote end device during DL Feature Exchange." "0,1,2,3" newline rbitfld.long 0x4 18.--19. "RPPCS,This register reflects the Posted Payload Credit Scale that is advertised by the remote end device during DL Feature Exchange." "0,1,2,3" newline rbitfld.long 0x4 16.--17. "RPHCS,This register reflects the Posted Header Credit Scale that is advertised by the remote end device during DL Feature Exchange." "0,1,2,3" newline bitfld.long 0x4 10.--11. "LCPCS,This register can be used to program the Completion Payload Credit Scale that will be advertised by the Controller." "0,1,2,3" newline bitfld.long 0x4 8.--9. "LCHCS,This register can be used to program the Completion Header Credit Scale that will be advertised by the Controller." "0,1,2,3" newline bitfld.long 0x4 6.--7. "LNPPCS,This register can be used to program the Non Posted Payload Credit Scale that will be advertised by the Controller." "0,1,2,3" newline bitfld.long 0x4 4.--5. "LNPHCS,This register can be used to program the Non Posted Header Credit Scale that will be advertised by the Controller." "0,1,2,3" newline bitfld.long 0x4 2.--3. "LPPCS,This register can be used to program the Posted Payload Credit Scale that will be advertised by the Controller." "0,1,2,3" newline bitfld.long 0x4 0.--1. "LPHCS,This register can be used to program the Posted Header Credit Scale that will be advertised by the Controller." "0,1,2,3" rgroup.long 0x100CD0++0xB line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_margining_parameters_1_reg,The Lane Margining at Receiver Parameters of the PHY are advertised in this Register." hexmask.long.byte 0x0 24.--29. 1. "MMVO,Offset from default at maximum step value as percentage of one volt. A 0 value may be reported if the vendor chooses not to report the offset." newline hexmask.long.byte 0x0 18.--23. 1. "MMTO,Offset from default at maximum step value as percentage of a nominal UI at 16.0 GT/s A 0 value may be reported if the vendor chooses not to report the offset." newline hexmask.long.byte 0x0 12.--17. 1. "MNTS,Number of time steps from default [to either left or right] range must be at least +/-0.2 UI. Timing offset must increase monotonically. The number of steps in both positive [toward the end of the unit interval] and.." newline hexmask.long.byte 0x0 5.--11. 1. "MNVS,Number of voltage steps from default [either up or down] minimum range +/-50 mV as measured by 16.0 GT/s reference equalizer Voltage offset must increase monotonically. The number of steps in both positive and negative direction.." newline bitfld.long 0x0 4. "MIES,1b Margining will not produce errors [change in the error rate] in data stream [error sampler is independent] 0b Margining may produce errors in the data stream" "0,1" newline bitfld.long 0x0 3. "MSRM,1b - Sampling Rates M SamplingRateVoltage M SamplingRateTiming are supported 0b - Sample Count is supported" "0,1" newline bitfld.long 0x0 2. "MINDLRTS,1b - Independent Left/Right Timing Margining is supported 0b - Independent Left/Right Timing Margining is not supported" "0,1" newline bitfld.long 0x0 1. "MINDUDVS,1b - Independent Up Down Voltage Margining is supported 0b - Independent Up Down Voltage Margining is not supported" "0,1" newline bitfld.long 0x0 0. "MVS,1b - Voltage Margining is supported 0b - Voltage Margining is not supported" "0,1" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_margining_parameters_2_reg,The Lane Margining at Receiver Parameters of the PHY are advertised in this Register." hexmask.long.byte 0x4 12.--16. 1. "MML,Maximum number of Lanes minus 1 that can be margined at the same time. It is recommended that this value be greater than or equal to the number of Lanes in the Link minus 1. Encoding Behavior is undefined if software.." newline hexmask.long.byte 0x4 6.--11. 1. "MSRT,The ratio of bits tested to bits received during timing margining. A value of 0 is a ratio of 1:64 [1 bit of every 64 bits received] and a value of 63 is a ratio of 64:64 [all bits received]." newline hexmask.long.byte 0x4 0.--5. 1. "MSRV,The ratio of bits tested to bits received during voltage margining. A value of 0 is a ratio of 1:64 [1 bit of every 64 bits received] and a value of 63 is a ratio of 64:64 [all bits received]." line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_margining_local_control_reg,The Lane Margining at Receiver local control fields are implemented in this Register." bitfld.long 0x8 29.--31. "WAWTC,When a WriteCommitted command is issued by the Controller the PHY must respond with a Write_Ack response. The time for which the Controller waits before timing out is controlled by this register." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3. "ESMSUCE,0: [Default Value] When a Clear Error Log Command is received after a Step Margin Command the Controller will process the Clear Error Log and respond with Clear Error Log Status. The Step Margin command is still active in the.." "?,1: When this bit is set to 1" newline bitfld.long 0x8 2. "DMSUSC,By default when a Step Margin command is received the Controller will update Lane Margin status to Margining in Progress when an Error Count update Or a Sample Count update is received from PHY." "0,1" newline bitfld.long 0x8 1. "AMCNG4,By default the Controller will process a Margin Command only if it is received while in 16GT/s L0 State. If a Margin Command is received when the link is not in Gen4-L0 state then the command will.." "0,1" newline bitfld.long 0x8 0. "MSR,This bit can be used to reset the Margining internal registers and Margining state machines in the Controller. When asserted: [i] The State machines will be reset to their default values. [ii] All.." "0,1" rgroup.long 0x100CDC++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_margining_error_status1_reg,The Lane Margining at Receiver SW Error Status fields are implemented in this Register." hexmask.long.byte 0x0 16.--19. 1. "ISWMCLN,This field reports the Lane Number for which the Invalid command was received. 0000: Lane 0. 0001: Lane 1. and so on.. This register is valid only when Bit-4 Invalid SW Margining Command Received .." newline hexmask.long.word 0x0 0.--15. 1. "ISWMC,When the Controller receives an Invalid Margining Command from SW in its configuration register the 16-bit command is logged in this register for debug. Only the first Error is logged in this register." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_margining_error_status2_reg,The Lane Margining at Receiver PHY Error Status fields are implemented in this Register." hexmask.long.byte 0x4 18.--21. 1. "UPRLN,This field reports the Lane Number for which the Controller received an unexpected PHY Response for Lane Margining. Unexpected PHY Response is detected by Controller if PHY writes to the Margin Status or.." newline hexmask.long.byte 0x4 14.--17. 1. "WAWTLN,This field reports the Lane Number for which the Controller detected a 10ms timeout. 0000: Lane 0. 0001: Lane 1. and so on.. This field is valid only when Bit-6 Write Ack Wait Timeout Error of the.." newline hexmask.long.byte 0x4 8.--11. 1. "IPHYMCLN,This field reports the Lane Number for which the Invalid command was received. 0000: Lane 0. 0001: Lane 1. and so on.. This field is valid only when Bit-5 Invalid PHY Margining Command Received .." newline hexmask.long.byte 0x4 0.--7. 1. "IPHYMC,When the Controller receives an Invalid Margining Command from PHY over PIPE Interface the 8-bit PIPE command is logged in this register for debug. Only the first Error is logged in this register." rgroup.long 0x100D00++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_local_error_status_2_register,This is an extension of the Local Error and Status Register." bitfld.long 0x0 14. "LEQRQIN,EP Mode: Indicates that the Controller hardware detected a problem with equalization and automatically requested for equalization redo at the end of the equalization. Controller checks for problems in.." "0,1" newline bitfld.long 0x0 9. "PTMCNTAINV,This status bit indicates that the Controller automatically invalidated PTM Context because of PCIe Link exit from L0 State." "0,1" newline bitfld.long 0x0 8. "NFTSTOS,This status bit indicates that a NFTS Timeout occured. This could occur if the PHY failed to achieve lock on the receive data before the NFTS Timeout during Rx_L0s.FTS state. Local Firmware should consider increasing.." "0,1" newline bitfld.long 0x0 7. "UPRR,This bit indicates that the Controller received an unexpected PHY Response for Lane Margining. The lane on which this error was detected is captured in bits 21:18 of the margining_error_status2_reg register." "0,1" newline bitfld.long 0x0 6. "WAWTE,This bit indicates that the Controller detected a 10ms timeout while waiting for Write Ack Lane Margining response from a PHY. The lane on which this timeout was detected is captured in bits 17:14 of the.." "0,1" newline bitfld.long 0x0 5. "IPHYMCR,This bit validates the 8-bit command stored in bits [7:0] and the Lane Number stored in bits [11:8] of the margining_error_status1_reg register. This bit is set upon receiving the first Error. Local.." "0,1" newline bitfld.long 0x0 4. "ISWMCR,This bit validates the 16-bit command stored in bits [15:0] and the Lane Number stored in bits [19:16] of the margining_error_status1_reg register. This bit is set upon receiving the first Error. Local.." "0,1" newline bitfld.long 0x0 3. "MSIXMSKSETST,This status bit indicates that the MSIX Function Mask of any function PF or VF was programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSIX Function Mask Change Enhanced Interrupt.." "0,1" newline bitfld.long 0x0 2. "MSIXMSKCLST,This status bit indicates that the MSIX Function Mask of any function PF or VF was programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSIX Function Mask Change Enhanced Interrupt.." "0,1" newline bitfld.long 0x0 1. "MSIMSKSETST,This status bit indicates that One or More bits of MSI Mask of any function PF or VF was programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt.." "0,1" newline bitfld.long 0x0 0. "MSIMSKCLST,This status bit indicates that One or More bits of MSI Mask of any function PF or VF was programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable.." "0,1" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_local_intrpt_mask_2_reg,This is an extension of the Local Interrupt Mask Register." bitfld.long 0x4 14. "LEQRQINM,Mask for Link Equalization Request Interrupt." "0,1" newline bitfld.long 0x4 9. "PCAIM,Mask for PTM Context Auto Invalidated event." "0,1" newline bitfld.long 0x4 8. "NFTSTOM,Mask for NFTS Timeout." "0,1" newline bitfld.long 0x4 7. "UPREM,Unexpected PHY Response is detected by Controller if PHY writes to the Margin Status or the Margin NAK bits of RX Margin Status 0 Register when no change in Start Margin or Margin Offset issued by Controller or after the.." "0: Error is not masked,1: Error is masked" newline bitfld.long 0x4 6. "WAWTEM,When a WriteCommitted command is issued by the Controller the PHY must respond with a Write_Ack within 10ms on the PIPE Message Bus Interface. However if the Write_Ack is not received within 10ms the Controller.." "0: Error is not masked,1: Error is masked" newline bitfld.long 0x4 5. "IPHYMEM,When the Controller receives a Margining Command from PHY over the PIPE Interface it checks if the command is valid. The error status is logged in local_error_status_2_register. This bit can be used to Mask asserting.." "0: Error is not masked,1: Error is masked" newline bitfld.long 0x4 4. "ISWMEM,When the Controller receives a Margining Command from SW in its configuration register it checks if the command is valid. The error status is logged in local_error_status_2_register. This bit can be used to Mask.." "0: Error is not masked,1: Error is masked" newline bitfld.long 0x4 3. "MSIXMSKSET,Mask for MSIX Function Mask Cleared Status." "0,1" newline bitfld.long 0x4 2. "MSIXMSKCL,Mask for MSIX Function Mask Set Status." "0,1" newline bitfld.long 0x4 1. "MSIMSKSET,Mask for MSI Mask Set Status." "0,1" newline bitfld.long 0x4 0. "MSIMSKCL,Mask for MSI Mask Cleared Status." "0,1" rgroup.long 0x100D10++0xF line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_msi_mask_cleared_status_1,This status register has one bit per function. Each function has a 32-bit MSI Mask." bitfld.long 0x0 21. "VF15MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF15 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x0 20. "VF14MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF14 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x0 19. "VF13MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF13 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x0 18. "VF12MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF12 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x0 17. "VF11MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF11 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x0 16. "VF10MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF10 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x0 15. "VF9MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF9 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x0 14. "VF8MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF8 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x0 13. "VF7MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF7 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x0 12. "VF6MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF6 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x0 11. "VF5MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF5 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x0 10. "VF4MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF4 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x0 9. "VF3MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF3 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x0 8. "VF2MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF2 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x0 7. "VF1MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF1 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x0 6. "VF0MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF0 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x0 5. "PF5MSIMSKCLST,Each PF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in PF5 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x0 4. "PF4MSIMSKCLST,Each PF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in PF4 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x0 3. "PF3MSIMSKCLST,Each PF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in PF3 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x0 2. "PF2MSIMSKCLST,Each PF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in PF2 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x0 1. "PF1MSIMSKCLST,Each PF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in PF1 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x0 0. "PF0MSIMSKCLST,Each PF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in PF0 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_msi_mask_set_status_1,This status register has one bit per function. Each function has a 32-bit MSI Mask." bitfld.long 0x4 21. "VF15MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF15 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x4 20. "VF14MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF14 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x4 19. "VF13MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF13 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x4 18. "VF12MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF12 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x4 17. "VF11MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF11 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x4 16. "VF10MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF10 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x4 15. "VF9MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF9 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x4 14. "VF8MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF8 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x4 13. "VF7MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF7 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x4 12. "VF6MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF6 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x4 11. "VF5MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF5 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x4 10. "VF4MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF4 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x4 9. "VF3MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF3 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x4 8. "VF2MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF2 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x4 7. "VF1MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF1 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x4 6. "VF0MSIMSKCLST,Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF0 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x4 5. "PF5MSIMSKCLST,Each PF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in PF5 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x4 4. "PF4MSIMSKCLST,Each PF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in PF4 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x4 3. "PF3MSIMSKCLST,Each PF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in PF3 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x4 2. "PF2MSIMSKCLST,Each PF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in PF2 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x4 1. "PF1MSIMSKCLST,Each PF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in PF1 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" newline bitfld.long 0x4 0. "PF0MSIMSKCLST,Each PF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in PF0 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change.." "0,1" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_msix_function_mask_cleared_status_1,This status register has one bit per function. Each function has a 1-bit MSIX Function Mask." bitfld.long 0x8 21. "VF15MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF15 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0x8 20. "VF14MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF14 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0x8 19. "VF13MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF13 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0x8 18. "VF12MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF12 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0x8 17. "VF11MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF11 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0x8 16. "VF10MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF10 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0x8 15. "VF9MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF9 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0x8 14. "VF8MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF8 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0x8 13. "VF7MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF7 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0x8 12. "VF6MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF6 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0x8 11. "VF5MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF5 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0x8 10. "VF4MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF4 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0x8 9. "VF3MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF3 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0x8 8. "VF2MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF2 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0x8 7. "VF1MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF1 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0x8 6. "VF0MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF0 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0x8 5. "PF5MSIXMSKCLST,Each PF has a 1-bit MSIX Function Mask. This status bit is set when the PF5 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0x8 4. "PF4MSIXMSKCLST,Each PF has a 1-bit MSIX Function Mask. This status bit is set when the PF4 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0x8 3. "PF3MSIXMSKCLST,Each PF has a 1-bit MSIX Function Mask. This status bit is set when the PF3 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0x8 2. "PF2MSIXMSKCLST,Each PF has a 1-bit MSIX Function Mask. This status bit is set when the PF2 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0x8 1. "PF1MSIXMSKCLST,Each PF has a 1-bit MSIX Function Mask. This status bit is set when the PF1 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0x8 0. "PF0MSIXMSKCLST,Each PF has a 1-bit MSIX Function Mask. This status bit is set when the PF0 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_msix_function_mask_set_status_1,This status register has one bit per function. Each function has a 1-bit MSIX Function Mask." bitfld.long 0xC 21. "VF15MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF15 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0xC 20. "VF14MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF14 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0xC 19. "VF13MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF13 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0xC 18. "VF12MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF12 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0xC 17. "VF11MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF11 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0xC 16. "VF10MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF10 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0xC 15. "VF9MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF9 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0xC 14. "VF8MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF8 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0xC 13. "VF7MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF7 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0xC 12. "VF6MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF6 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0xC 11. "VF5MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF5 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0xC 10. "VF4MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF4 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0xC 9. "VF3MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF3 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0xC 8. "VF2MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF2 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0xC 7. "VF1MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF1 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0xC 6. "VF0MSIXMSKCLST,Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF0 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0xC 5. "PF5MSIXMSKCLST,Each PF has a 1-bit MSIX Function Mask. This status bit is set when the PF5 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0xC 4. "PF4MSIXMSKCLST,Each PF has a 1-bit MSIX Function Mask. This status bit is set when the PF4 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0xC 3. "PF3MSIXMSKCLST,Each PF has a 1-bit MSIX Function Mask. This status bit is set when the PF3 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0xC 2. "PF2MSIXMSKCLST,Each PF has a 1-bit MSIX Function Mask. This status bit is set when the PF2 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0xC 1. "PF1MSIXMSKCLST,Each PF has a 1-bit MSIX Function Mask. This status bit is set when the PF1 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" newline bitfld.long 0xC 0. "PF0MSIXMSKCLST,Each PF has a 1-bit MSIX Function Mask. This status bit is set when the PF0 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. This bit is set only when the MSIX Function.." "?,1: bit MSIX Function Mask" rgroup.long 0x100DA0++0xB line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_ld_ctrl,This register is for the control of Link Down Indication Auto Reset behavior" bitfld.long 0x0 24. "AUTO_EN,This bit when set indicates that the link down indication auto reset is enabled" "0,1" newline hexmask.long.tbyte 0x0 0.--23. 1. "LDTIMER,This is a counter timeout value which triggers the internal logic to reset the link down indication bit in the AXI Configuration registers" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_rx_elec_idle_filter_control,This register controls the behavior of glitch filter on the pipe rx Electrical Idle" hexmask.long.byte 0x4 24.--31. 1. "GFLCP,This controls the glitch filter on PM Clock domain. This counter indicates the number of PM Clocks the glitch will be filtered out. The total delay of the glitch filter is calculated as [PM Clock Period * Number of PM Clocks] this delay should be.." newline hexmask.long.byte 0x4 16.--23. 1. "GFLCC,This controls the glitch filter on CORE Clock domain. This counter indicates the number of CORE Clocks the glitch will be filtered out. The total delay of the glitch filter is calculated as [CORE Clock Period * Number of CORE Clocks] this delay.." newline hexmask.long.byte 0x4 0.--3. 1. "GFLD,By default controller enables glitch filter on all lanes. Setting this bit to one makes the controller to disable the glitch filter on that corresponding lanes in which the bit is set. When all bits are set to one the.." line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_ptm_local_control_reg,The register bits to Control PTM operation are implemented in this Register." bitfld.long 0x8 28. "DAINVCNT,By default the Controller automatically invalidates PTM Context when the LTSSM exits L0 state. Client may disable this by writing a 1 to this register." "0,1" newline bitfld.long 0x8 27. "INVPTMCNT,Client Firmware may write a 1 to this bit in order to reset the PTM Context. This is a write-only bit. Controller internally clears this bit. Read from this bit returns 0. EP Mode: Resets the PTM.." "0,1" newline bitfld.long 0x8 17. "PTMRSEN,EP Mode: Reserved RP Mode: This bit enables Controller [RP] to respond to the received PTM Requests. PTM Response/PTM ResponseD is determined by the PTM Response.." "0: Controller does not respond for PTM Requests,1: Controller automatically responds with.." newline bitfld.long 0x8 16. "PTMRSM,EP Mode: Reserved. RP Mode: This bit is used to control the number of PTM dialogs used during each PTM Master Time Request. 1 : Two Dialog Mode -.." "0: Request,1: Request" newline hexmask.long.byte 0x8 12.--15. 1. "PTMRINT,EP Mode: In Single Periodic Request Mode this field is used to control the time interval [in us] between PTM Requests within a PTM Context. This represents the time the Requester State Machine waits in the.." newline hexmask.long.byte 0x8 8.--11. 1. "PTMRFRVL,EP Mode: In Periodic Request Mode this field is used to control the time interval [value] between successive PTM Context Refresh. This represents the time the Requester State Machine waits in the VALID_PTM_CONTEXT_STATE." newline hexmask.long.byte 0x8 4.--7. 1. "PTMRFRSC,EP Mode: In Periodic Request Mode this field is used to control the time interval [scale] between successive PTM Context Refresh. This represents the time the Requester State Machine waits in the VALID_PTM_CONTEXT_STATE." newline bitfld.long 0x8 1. "PTMRQEN,EP Mode: This enables Endpoint to request for PTM Master Time. 1 : PTM Requests are Enabled. In Single Request Mode this bit is used to trigger PTM dialog to obtain PTM Master time exactly once." "0: PTM Requests are Disabled,1: PTM Requests are Enabled" newline bitfld.long 0x8 0. "PTMRQM,EP Mode: This bit controls the pattern of PTM Requests issued by the Endpoint. 0: Single Request Mode. 1: Periodic Request Mode. In Single Request Mode Endpoint.." "0: Single Request Mode,1: Periodic Request Mode" rgroup.long 0x100DAC++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_ptm_local_status_reg,The status of PTM Dialog is reflected in this Register." hexmask.long.byte 0x0 0.--3. 1. "PTMCNST,Reflects the current status of the PTM Context. In EP Mode: 0000 - Invalid PTM Context 0001 - Dialog 1 PTM Request Sent 0011 - Dialog 1 PTM Response Received 0111 -.." rgroup.long 0x100DB0++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_ptm_latency_parameters_index_reg,The latency parameters of the PHY may be different at different speeds of operation." hexmask.long.byte 0x0 0.--3. 1. "PTMLATIN,This is used by FW to select the speed for which the Latency parameters are to be programmed. FW is required to set this to each of the supported speeds and program the corresponding latency parameters in the PTM Latency.." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_ptm_latency_parameters_reg,This register is used to define the PHY specific delay parameters." hexmask.long.byte 0x4 28.--31. 1. "RXDLTUN,In EP Mode: This field can be used to add a fixed offset to the captured timestamps t4 and t4_tick. In RP Mode: This field can be used to add a fixed offset to the captured timestamps t2 and.." newline hexmask.long.byte 0x4 24.--27. 1. "TXDLTUN,In EP Mode: This field can be used to add a fixed offset to the captured timestamps t1 and t1_tick. In RP Mode: This field can be used to add a fixed offset to the captured timestamps t3 and.." newline hexmask.long.word 0x4 10.--19. 1. "PTMRXLAT,This field should be programmed with the parameter Receive Latency in [ns] from the PHY Datasheet. Separate value can be programmed for each supported speed of operation. The speed of operation must first be.." newline hexmask.long.word 0x4 0.--9. 1. "PTMTXLAT,This field should be programmed with the parameter Transmit Latency in [ns] from the PHY Datasheet. Separate value can be programmed for each supported speed of operation. The speed of operation must first be.." rgroup.long 0x100DB8++0x2B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_ptm_context_1_reg,PTM Context 1 Register." hexmask.long 0x0 0.--31. 1. "PTMT1T2,EP Mode : Represents the lower 32-bits of timestamp t1 in [ns] as recorded by Endpoint. RP Mode : Represents the lower 32-bits of timestamp t2 in [ns] as recorded by RP." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_ptm_context_2_reg,PTM Context 2 Register." hexmask.long 0x4 0.--31. 1. "PTMT1T2U,EP Mode : Represents the upper 32-bits of timestamp t1 in [ns] as recorded by Endpoint. RP Mode : Represents the upper 32-bits of timestamp t2 in [ns] as recorded by RP." line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_ptm_context_3_reg,PTM Context 3 Register." hexmask.long 0x8 0.--31. 1. "PTMT4T3,EP Mode : Represents the lower 32-bits of timestamp t4 in [ns] as recorded by Endpoint. RP Mode : Represents the lower 32-bits of timestamp t3 in [ns] as recorded by RP." line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_i_ptm_context_4_reg,PTM Context 4 Register." hexmask.long 0xC 0.--31. 1. "PTMT4T3U,EP Mode : Represents the upper 32-bits of timestamp t4 in [ns] as recorded by Endpoint. RP Mode : Represents the upper 32-bits of timestamp t3 in [ns] as recorded by RP." line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_i_ptm_context_5_reg,PTM Context 5 Register." hexmask.long 0x10 0.--31. 1. "PTMT1KT2K,EP Mode : Represents the lower 32-bits of timestamp t1_tick in [ns] as recorded by Endpoint. RP Mode : Represents the lower 32-bits of timestamp t2_tick in [ns] as recorded by RP." line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_i_ptm_context_6_reg,PTM Context 6 Register." hexmask.long 0x14 0.--31. 1. "PTMT1KT2KU,EP Mode : Represents the upper 32-bits of timestamp t1_tick in [ns] as recorded by Endpoint. RP Mode : Represents the upper 32-bits of timestamp t2_tick in [ns] as recorded by RP." line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_i_ptm_context_7_reg,PTM Context 7 Register." hexmask.long 0x18 0.--31. 1. "PTMT4KT3K,EP Mode : Represents the lower 32-bits of timestamp t4_tick in [ns] as recorded by Endpoint. RP Mode : Represents the lower 32-bits of timestamp t3_tick in [ns] as recorded by RP." line.long 0x1C "CORE__DBN_CFG__PCIE_CORE_REG_i_ptm_context_8_reg,PTM Context 8 Register." hexmask.long 0x1C 0.--31. 1. "PTMT4KT3KU,EP Mode : Represents the upper 32-bits of timestamp t4_tick in [ns] as recorded by Endpoint. RP Mode : Represents the upper 32-bits of timestamp t3_tick in [ns] as recorded by RP." line.long 0x20 "CORE__DBN_CFG__PCIE_CORE_REG_i_ptm_context_9_reg,PTM Context 9 Register." hexmask.long 0x20 0.--31. 1. "PTMT3MT2,Propagation Delay. EP Mode : Represents the Propagation Delay [t3 - t2] in [ns] as received in ResponseD Message by Endpoint. RP Mode - Reserved." line.long 0x24 "CORE__DBN_CFG__PCIE_CORE_REG_i_ptm_context_10_reg,PTM Context 10 Register." hexmask.long 0x24 0.--31. 1. "PTMMSTT1T,EP Mode - Represents the lower 32-bits of PTM Master Time at timestamp t1_tick in [ns] as computed by Endpoint. RP Mode - Reserved." line.long 0x28 "CORE__DBN_CFG__PCIE_CORE_REG_i_ptm_context_11_reg,PTM Context 11 Register." hexmask.long 0x28 0.--31. 1. "PTMMSTT1TU,EP Mode - Represents the upper 32-bits of PTM Master Time at timestamp t1_tick in [ns] as computed by Endpoint. RP Mode - Reserved." rgroup.long 0x100DEC++0xB line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_asf_intrpt_status,This register indicates the source of ASF interrupts. The corresponding bit in the mask" bitfld.long 0x0 6. "INTEGRER,Integrity error interrupt" "0,1" newline bitfld.long 0x0 5. "PROTER,Protocol error interrupt" "0,1" newline bitfld.long 0x0 4. "TRANSTOER,Transaction timeouts interrupt" "0,1" newline bitfld.long 0x0 3. "CSRER,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x0 2. "DAPER,Data and address paths error interrupt" "0,1" newline bitfld.long 0x0 1. "SRUCORER,SRAM Uncorrectable error interrupt" "0,1" newline bitfld.long 0x0 0. "SRCORER,SRAM Correctable error interrupt" "0,1" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_asf_intrpt_raw_status,A bit set in this raw register indicates a source of ASF fault in the corresponding feature." bitfld.long 0x4 6. "INTEGRER,Integrity error interrupt" "0,1" newline bitfld.long 0x4 5. "PROTER,Protocol error interrupt" "0,1" newline bitfld.long 0x4 4. "TRANSTOER,Transaction timeouts interrupt" "0,1" newline bitfld.long 0x4 3. "CSRER,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x4 2. "DAPER,Data and address paths error interrupt" "0,1" newline bitfld.long 0x4 1. "SRUCORER,SRAM Uncorrectable error interrupt" "0,1" newline bitfld.long 0x4 0. "SRCORER,SRAM Correctable error interrupt" "0,1" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_asf_intrpt_mask_reg,This Register indicates which interrupt bits in the ASF interrupt status register are masked." bitfld.long 0x8 6. "INTEGRERM,Mask bit for Integrity error interrupt" "0,1" newline bitfld.long 0x8 5. "PROTERM,Mask bit for Protocol error interrupt" "0,1" newline bitfld.long 0x8 4. "TRANTOEM,Mask bit for Transaction timeouts interrupt" "0,1" newline bitfld.long 0x8 3. "CSRERM,Mask bit for Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x8 2. "DAPERM,Mask bit for Data and address paths error interrupt" "0,1" newline bitfld.long 0x8 1. "SRUCORERM,Mask bit for SRAM Uncorrectable error interrupt" "0,1" newline bitfld.long 0x8 0. "SRCORERM,Mask bit for SRAM Correctable error interrupt" "0,1" rgroup.long 0x100DF8++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_asf_intrpt_test,Writing one to individual bits will trigger corresponding interrupt event. The raw" bitfld.long 0x0 6. "INTEGRERT,Test bit for Integrity error interrupt" "0,1" newline bitfld.long 0x0 5. "PROTERT,Test bit for Protocol error interrupt" "0,1" newline bitfld.long 0x0 4. "TRANTOET,Test bit for Transaction timeouts interrupt" "0,1" newline bitfld.long 0x0 3. "CSRERT,Test bit for Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x0 2. "DAPERT,Test bit for Data and address paths error interrupt" "0,1" newline bitfld.long 0x0 1. "SRUCORERT,Test bit for SRAM Uncorrectable error interrupt" "0,1" newline bitfld.long 0x0 0. "SRCORERT,Test bit for SRAM Correctable error interrupt" "0,1" rgroup.long 0x100DFC++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_asf_intrpt_fatal_nonfatal_sel,This register selects whether a fatal (asf_int_fatal) or non-fatal (asf_int_nonfatal) interrupt is" bitfld.long 0x0 6. "INTEGRERS,Enable Integrity error as Fatal" "0,1" newline bitfld.long 0x0 5. "PROTERS,Enable protocol interrupt as fatal" "0,1" newline bitfld.long 0x0 4. "TRANTOES,Enable transaction timeouts interrupt as fatal" "0,1" newline bitfld.long 0x0 3. "CSRERS,Enable configuration and status registers interrupt as fatal" "0,1" newline bitfld.long 0x0 2. "DAPERS,Enable data and address paths interrupt as fatal" "0,1" newline bitfld.long 0x0 1. "SRUCORERS,Enable SRAM Uncorrectable interrupt as fatal" "0,1" newline bitfld.long 0x0 0. "SRCORERS,Enable SRAM correctable interrupt as fatal" "0,1" rgroup.long 0x100E00++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_asf_sram_corr_fault_status,These fields are updated whenever asf_sram_corr_fault input is active" hexmask.long.byte 0x0 24.--31. 1. "SRCORFI,This ENCODING indicates which SRAM Instance has a Correctable Fault. The Encoding of the SRAM is listed under Section: IP Embedded SRAM Protection in Table: SRAM Instance EnCoding" newline hexmask.long.tbyte 0x0 0.--23. 1. "SRCORFADR,This indicates the address where the Correctable fault was observed." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_asf_sram_uncorr_fault_status,These fields are updated whenever asf_sram_uncorr_fault input is active" hexmask.long.byte 0x4 24.--31. 1. "SRUCORFI,This ENCODING indicates which SRAM Instance has a Uncorrectable Fault. The Encoding of the SRAM is shown in Table 26" newline hexmask.long.tbyte 0x4 0.--23. 1. "SRUCRFADR,This indicates the address where the Uncorrectable fault was observed." rgroup.long 0x100E08++0x17 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_asf_sram_fault_statstics,Note that this register clears when software writes to any field" hexmask.long.word 0x0 16.--31. 1. "SRUCORFS,Counts the number of SRAM Uncorrectable errors seen." newline hexmask.long.word 0x0 0.--15. 1. "SRCORFS,Counts the number of SRAM Correctable errors seen." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_asf_trans_to_ctrl,Register to program Transaction timeout in monitor and enable it" bitfld.long 0x4 31. "TRTOEN,Enable transaction timeout monitoring." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "TRTOCTRL,Timer value to use for transaction timeout monitor.This is counted in resolution of 1 ms." line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_asf_trans_to_fault_mask,Disables the Timeout Completion Reporting" bitfld.long 0x8 11. "DTIDTOM,When written to 1 Disables DTI DN I/F timeout Reporting Error status reporting" "0,1" newline bitfld.long 0x8 10. "DTIUTOM,When written to 1 Disables DTI UP I/F timeout Reporting Error status reporting" "0,1" newline bitfld.long 0x8 9. "APBTOM,When written to 1 Disables APB I/F timeout Error status reporting" "0,1" newline bitfld.long 0x8 8. "LMITOM,When written to 1 Disables Local Management I/F timeout Error status reporting" "0,1" newline bitfld.long 0x8 7. "AXSLTOM,When written to 1 Disables AXI Slave I/F timeout Error status reporting" "0,1" newline bitfld.long 0x8 6. "AXMSTOM,When written to 1 Disables AXI Target I/F timeout Error status reporting" "0,1" newline bitfld.long 0x8 5. "HLTGTOM,When written to 1 Disables HAL Target I/F timeout Error status reporting" "0,1" newline bitfld.long 0x8 4. "HLMSTOM,When written to 1 Disables HAL Master I/F timeout Error status reporting" "0,1" newline bitfld.long 0x8 3. "LRESPDTOM,When written to 1 Disables LTSSM Recovery Speed Timeout Error status reporting" "0,1" newline bitfld.long 0x8 2. "LCFLWSTOM,When written to 1 Disables LTSSM Cfg Link Width Start Timeout Error status reporting" "0,1" newline bitfld.long 0x8 1. "LTPLCFTOM,When written to 1 Disables LTSSM Polling Configuration Timeout Error status reporting" "0,1" newline bitfld.long 0x8 0. "PCOMTOM,When written to 1 Disables PCIe Completion Timeout Error status reporting" "0,1" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_i_asf_trans_to_fault_status,If a fault occurs the relevant status bit will be set to 1. Each bit can" bitfld.long 0xC 11. "DTIDTO,DTI DN I/F Timeout detected waiting for a response from User" "0,1" newline bitfld.long 0xC 10. "DTIUTO,DTI UP I/F Timeout detected waiting for a response from User" "0,1" newline bitfld.long 0xC 9. "APBTOM,APB I/F Timeout detected waiting for a response from User" "0,1" newline bitfld.long 0xC 8. "LMITO,Local Management I/F Timeout detected waiting for a response from User" "0,1" newline bitfld.long 0xC 7. "AXSLTO,AXI Slave I/F Timeout detected waiting for a response" "0,1" newline bitfld.long 0xC 6. "AXMSTO,AXI Master I/F Timeout detected waiting for a response" "0,1" newline bitfld.long 0xC 5. "HLTGTO,HAL Target I/F Timeout detected waiting for a response" "0,1" newline bitfld.long 0xC 4. "HLMSTO,HAL Master I/F Timeout detected waiting for a response" "0,1" newline bitfld.long 0xC 3. "LRESPDTO,This Indicates if the states of the LTSSM timed out . 48 ms timeout in Rec.Speed-> Detect" "0,1" newline bitfld.long 0xC 2. "LCFLWSTO,This Indicates if the states of the LTSSM timed out . 24 ms Timeout observed in Cfg.Link.Width.Start -> Detect" "0,1" newline bitfld.long 0xC 1. "LTPLCFTO,This Indicates if the states of the LTSSM timed out . 48 ms Timeout observed for Polling.Cfg-> Detect" "0,1" newline bitfld.long 0xC 0. "PCOMTO,This indicates if a Non Posted requested did NOT receive any competition from remote device with in the completion time specified" "0,1" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_i_asf_protocol_fault_mask,This control register controls if a particular protocol error is disabled" bitfld.long 0x10 15. "AXISLDECM,When set to 1 disables the AXI Slave/Decode Error status reporting" "0,1" newline bitfld.long 0x10 14. "RPLTOM,When set to 1 disables the Replay Timer Timeout status reporting" "0,1" newline bitfld.long 0x10 13. "RPLROLM,When set to 1 disables the Replay Number Rollover Detected status reporting" "0,1" newline bitfld.long 0x10 12. "BADDLPM,When set to 1 disables the Bad DLLP Detected status reporting" "0,1" newline bitfld.long 0x10 11. "BADTLPM,When set to 1 disables the Bad TLP Detected status reporting" "0,1" newline bitfld.long 0x10 10. "PHRCVERM,When set to 1 disables the PHY Receiver Error Detected status reporting" "0,1" newline bitfld.long 0x10 9. "USPREQM,When set to 1 disables the Unsupported Request Error status reporting" "0,1" newline bitfld.long 0x10 8. "ECRCERRM,When set to 1 disables the ECRC Error Detected status reporting" "0,1" newline bitfld.long 0x10 7. "MALTLPEM,When set to 1 disables the Malformed Error status reporting" "0,1" newline bitfld.long 0x10 6. "RCVROVFLM,When set to 1 disables the Receiver Overflow Error status reporting" "0,1" newline bitfld.long 0x10 5. "UNCPLRCM,When set to 1 disables the Unexpcted Completion status reporting" "0,1" newline bitfld.long 0x10 4. "CMPLABTM,When set to 1 disables the Completer Abort Error status reporting" "0,1" newline bitfld.long 0x10 3. "CPLTOM,When set to 1 disables the Completion Timeout status reporting" "0,1" newline bitfld.long 0x10 2. "FCPROERM,When set to 1 disables the Flow Control Protocol Error status reporting" "0,1" newline bitfld.long 0x10 1. "POTLRCVM,When set to 1 disables the Poisoned TLP received status reporting" "0,1" newline bitfld.long 0x10 0. "DLPROTM,When set to 1 disables the Data Link Layer Protocol Error status reporting" "0,1" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_i_asf_protocol_fault_status_reg,This status register holds the different protocol errors observed by the IP." bitfld.long 0x14 15. "AXISLVDEC,This bit is set when the AXI interface sends SLVERR or DECERR to the user" "0,1" newline bitfld.long 0x14 14. "RPLTOM,This bit is set when the replay timer in the Data Link Layer of the Controller times out." "0,1" newline bitfld.long 0x14 13. "RPLROL,This bit is set when the replay count rolls over after three re transmissions of a TLP at the Data Link Layer of the Controller." "0,1" newline bitfld.long 0x14 12. "BADDLP,This bit is set when an LCRC error is detected in a received DLLP" "0,1" newline bitfld.long 0x14 11. "BADTLPM,This bit is set when an error is detected in a received TLP by the Data Link Layer of the Controller." "0,1" newline bitfld.long 0x14 10. "PHRCVER,This bit is set when an error is detected in the receive side of the Physical Layer of the Controller" "0,1" newline bitfld.long 0x14 9. "USPREQ,This bit is set when the Controller has received a request from the link that it does not support." "0,1" newline bitfld.long 0x14 8. "ECRCERR,This bit is set when the Controller has detected an ECRC error in a received TLP" "0,1" newline bitfld.long 0x14 7. "MALTLPER,This bit is set when the Controller receives a malformed TLP from the link." "0,1" newline bitfld.long 0x14 6. "RCVROVFL,This bit is set when the Controller receives a TLP in violation of the receive credit currently available." "0,1" newline bitfld.long 0x14 5. "UNCMLRCV,This bit is set when the Controller has received an unexpected Completion packet from the link" "0,1" newline bitfld.long 0x14 4. "CMPLABT,This bit is set when the Controller has returned the Completer Abort [CA] status to a request received from the link." "0,1" newline bitfld.long 0x14 3. "CPLTO,This bit is set when the completion timer associated with an outstanding request times out." "0,1" newline bitfld.long 0x14 2. "FCPROER,This bit is set when certain violations of the flow control protocol are detected by the Controller." "0,1" newline bitfld.long 0x14 1. "POTLRCV,This bit is set when the Controller receives a poisoned TLP from the link." "0,1" newline bitfld.long 0x14 0. "DLPROT,This bit is set when the Controller receives an Ack or Nak DLLP whose sequence number does not correspond to that of an unacknowledged TLP or that of the last acknowledged TLP" "0,1" rgroup.long 0x100E40++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_asf_magic_num_ctrller_ver_reg,This register contains two read only 16 bit hardcoded values used by the software." hexmask.long.word 0x0 16.--31. 1. "CNTVER,This 16bit value is used to determine the revision number of the controller by the software" newline hexmask.long.word 0x0 0.--15. 1. "MGCNM,This 16bit value is used for verification of base address by the software" rgroup.long 0x100E4C++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_eq_debug_mon_control_reg,The register bits to Control EQ debug Monitor operation are implemented in this Register." rbitfld.long 0x0 10. "CAPTBEH,If this is set the first 64 equalization info events are captured else the last 64 events are captured" "0,1" newline bitfld.long 0x0 7.--9. "CAPTSPDSEL,Selects the Link Speed at which capture is to be done 000 : Any speed 001 : Gen 3 010 : Gen 4 100 : Gen 5" "0: Any speed,1: Gen 3,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "CAPTPHSEL,Selects the Equalization Phase when capture is to be done 01 : Phase 2 10 : Phase 3 11 : Phase 2 and 3" "?,1: Phase 2,?,?" newline hexmask.long.byte 0x0 1.--4. 1. "CAPTLNSEL,Selects the Lane whose Equalization Debug information is to be captured.Please note this signifies the physical lane number." newline bitfld.long 0x0 0. "CLRCAPT,Setting this bit clears all captured information in the EQ Debug Status Registers. If it is unset then capture is allowed in status registers." "0,1" rgroup.long 0x100E50++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_eq_debug_mon_status0_reg,Both the Local and Remote EQ FS and LF values are captured in this Register." hexmask.long.byte 0x0 18.--23. 1. "REMLF,Remote PHY's LF Value Of the Lane and Speed Selected." newline hexmask.long.byte 0x0 12.--17. 1. "REMFS,Remote PHY's FS Value Of the Lane and Speed Selected." newline hexmask.long.byte 0x0 6.--11. 1. "LCLLF,Local PHY's LF Value Of the Lane and Speed Selected." newline hexmask.long.byte 0x0 0.--5. 1. "LCLFS,Local PHY's FS Value Of the Lane and Speed Selected." line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_eq_debug_mon_status_reg,All the Dynamic Equalization information is captured in this Register.This is" bitfld.long 0x4 30.--31. "EQPHASE,Equalization Phase during Capture 00 : Phase 0 01 : Phase 1 10 : Phase 2 11 : Phase 3" "0: Phase 0,1: Phase 1,?,?" newline hexmask.long.byte 0x4 24.--29. 1. "DIRFED,EP Ph2/RC Ph3: Stores Direction Change Feedback or Preset feedback Transmitted to Remote Device. Bit-22 EQPREVD indicates if this is a Preset feedback or Direction Change Feedback. EP Ph3/RC Ph2: Reserved" newline bitfld.long 0x4 23. "COEFFREJ,Phase0: Set to '1' if an unsupported preset is received in Phase0. Phase1: Set to '0' since no reject in phase1. EP Ph2/RC Ph3: Indicates Reject by the Remote end device. This bit indicates that the.." "0: Set to '1' if an unsupported preset is received..,1: Set to '0' since no reject in phase1" newline bitfld.long 0x4 22. "EQPREVD,1: Preset Valid Indicates [21:18] is valid. Phase0: Set to '1' to indicate that the intial Local Preset is Valid. Phase1: Set to '1' to indicate that the advertised Remote Preset is Valid. EP.." "0: Set to '1' to indicate that the intial Local..,1: Set to '1' to indicate that the advertised.." newline hexmask.long.byte 0x4 18.--21. 1. "EQPRE,Phase0: Stores Initial Local TX Preset received in Phase0. Phase1: Stores Initial Remote Preset advertised in Phase1. EP Ph2/RC Phase3: Stores Current Preset of the Remote Device. EP Ph3/RC Phase2:.." newline hexmask.long.tbyte 0x4 0.--17. 1. "EQCOEFF,Phase0: Stores Initial Local TX Coefficients mapped from Initial Preset. Phase1: Stores Initial Remote Coefficients advertised in Phase1. [Cp LF FS] EP Ph2/RC Phase3: Stores Current Coefficients of the Remote.." rgroup.long 0x100E5C++0xF line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_axi_feature_reg,This register is for the control of AXI Features" bitfld.long 0x0 1. "SLVERRCTRL,This bit if set to 1 AXI Slave masks the SLVERR response to be given in case of UR or CRS completion for configuration requests. If this bit is set to 0 UR and CRS completions from the link causes SLVERR at AXI." "0,1" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_i_link_eq_control_2_reg,This register implements fields to control and override Link Equalization." hexmask.long.byte 0x4 17.--20. 1. "G4OVRRPR,This is a debug register field. Can be used in both EP and RP Mode. When enabled using bit-16 this Tx Preset will be applied to the local Transmitter throughout Gen4 regardless of Gen4 Equalization." newline bitfld.long 0x4 16. "G4OVRREN,This is a debug bit. Can be used in both EP and RP Mode. If enabled the Controller locally applies the Gen4 Local Override Tx Preset to the Local Transmitter throughout Gen4. The Controller performs the Override.." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "G4RMTXPR,Used only in EP Mode. If enabled this Tx Preset will be transmitted in 8G EQ TS2s during Gen3 to Gen4 Speed Change negotiation. Also If enabled this Tx Preset will be transmitted in TS1s in the first iteration.." newline bitfld.long 0x4 11. "G4PRRMEN,Used only in EP Mode. This bit enables the Controller to feedback a Tx Preset for the Remote end Transmitter in the first iteration of Link Equalization Phase2 at Gen4 speed. The Gen4 Tx Preset that is used for.." "0,1" newline bitfld.long 0x4 10. "G4EQTSEN,Used only in EP Mode. During Gen3 to Gen4 Speed Change negotiation this bit enables the Controller in EP Mode to transmit 8G EQ TS2 in Recovery.Rcvr.Cfg state instead of standard TS2 as defined in PCIe specification." "0,1" newline hexmask.long.byte 0x4 6.--9. 1. "G3OVRRPR,This is a debug register field. Can be used in both EP and RP Mode. When enabled using bit-5 this Tx Preset will be applied to the local Transmitter throughout Gen3 regardless of Gen3 Equalization." newline bitfld.long 0x4 5. "G3OVRREN,This is a debug bit. Can be used in both EP and RP Mode. If enabled the Controller locally applies the Gen3 Local Override Tx Preset to the Local Transmitter throughout Gen3. The Controller performs the Override.." "0,1" newline hexmask.long.byte 0x4 1.--4. 1. "G3RMTXPR,Used only in EP Mode. When enabled using bit-0 this Tx Preset will be transmitted in TS1s for the Remote end Transmitter in the first iteration of Gen3 Equalization Phase2. Reserved for RP Mode." newline bitfld.long 0x4 0. "G3PRRMEN,Used only in EP Mode. This bit enables the Controller to feedback a Tx Preset for the Remote end Transmitter in the first iteration of Link Equalization Phase2 at Gen3 speed. The Gen3 Tx Preset that is used for.." "0,1" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_i_core_feature_reg,This register is for the control of Core Features" bitfld.long 0x8 1. "APBCTRL,When set the Core will return SLVERR on the APB bus for Read or Writes to Configuration or Local Management registers" "0,1" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_i_dti_ats_ctrl_2,This register is for the control of DTI ATS Master" hexmask.long.word 0xC 16.--31. 1. "TID,This 16 bit value is used to drive the 16 bit TID_DTI_DN pin of the DTI Master" newline hexmask.long.word 0xC 0.--15. 1. "STRMID,This 16 bit value is used to filter [upper 16 bits of the SID is matched with this value] the DTI_ATS_INV_REQ and DTI_ATS_PAGE_RESP messages sent[broadcast] from the SMMU in case of multiple DTI Masters. This value used for the upper 16 bits of.." rgroup.long 0x100E88++0x3 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_i_rx_invert_polarity_reg,This register shows the polarity inversion status of each lane" hexmask.long.byte 0x0 0.--3. 1. "RIPR,shows the polarity inversion status of each lane" rgroup.long 0x400000++0xF line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0x0 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0x0 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x4 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x8 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0xC 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x400014++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x400034++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x400054++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x400074++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x400094++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x4000B4++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x4000D4++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x4000F4++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x400114++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x400134++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x400154++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x400174++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x400194++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x4001B4++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x4001D4++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x4001F4++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x400214++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x400234++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x400254++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x400274++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x400294++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x4002B4++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x4002D4++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x4002F4++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x400314++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x400334++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x400354++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x400374++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x400394++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x4003B4++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x4003D4++0x1B line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through" hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Bits [31:8] of PCIe Address Register for region N" newline rbitfld.long 0xC 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the PCIe address" hexmask.long 0x10 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_desc0,Provides bits 31:0 of the Outbound PCIe Descriptor" hexmask.long 0x14 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0x18 "CORE__DBN_CFG__PCIE_CORE_REG_desc1,Provides bits 63:32 of the PCIe Descriptor" hexmask.long 0x18 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" rgroup.long 0x4003F4++0xB line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_desc3,Provides PASID Value and The present bit" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr0,holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region" newline bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_axi_addr1,holds the base address [63:32] of this region." hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" rgroup.long 0x400800++0x17 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the AXI Address and the number of PCIE address bits passed through" hexmask.long.tbyte 0x0 8.--31. 1. "DATA,Bits [31:8] of AXI Address Register for BAR N" newline rbitfld.long 0x0 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the AXI Address" hexmask.long 0x4 0.--31. 1. "DATA,Bits [63:32] of AXI Address Register for BAR N" line.long 0x8 "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the AXI Address and the number of PCIE address bits passed through" hexmask.long.tbyte 0x8 8.--31. 1. "DATA,Bits [31:8] of AXI Address Register for BAR N" newline rbitfld.long 0x8 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0x8 0.--5. 1. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" line.long 0xC "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the AXI Address" hexmask.long 0xC 0.--31. 1. "DATA,Bits [63:32] of AXI Address Register for BAR N" line.long 0x10 "CORE__DBN_CFG__PCIE_CORE_REG_addr0,Provides bits 31:8 of the AXI Address and the number of PCIE address bits passed through" hexmask.long.tbyte 0x10 8.--31. 1. "DATA,Bits [31:8] of AXI Address Register for BAR N" newline rbitfld.long 0x10 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3" newline hexmask.long.byte 0x10 0.--5. 1. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" line.long 0x14 "CORE__DBN_CFG__PCIE_CORE_REG_addr1,Provides bits 63:32 of the AXI Address" hexmask.long 0x14 0.--31. 1. "DATA,Bits [63:32] of AXI Address Register for BAR N" rgroup.long 0x400820++0x7 line.long 0x0 "CORE__DBN_CFG__PCIE_CORE_REG_c0,N/A" hexmask.long.byte 0x0 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper" newline hexmask.long.word 0x0 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper" line.long 0x4 "CORE__DBN_CFG__PCIE_CORE_REG_L0,N/A" bitfld.long 0x4 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes. client should clear this bit before issueing new traffic to the core" "0,1" tree.end tree "PCIE1_CORE_ECC" tree "PCIE1_CORE_ECC_AGGR0 (PCIE1_CORE_ECC_AGGR0)" base ad:0x2915000 rgroup.long 0x0++0x3 line.long 0x0 "CORE__ECC_AGGR0__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "CORE__ECC_AGGR0__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "CORE__ECC_AGGR0__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "CORE__ECC_AGGR0__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "CORE__ECC_AGGR0__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "CORE__ECC_AGGR0__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 4. "AXI2VBUSM_MST_PEND,Interrupt Pending Status for axi2vbusm_mst_pend" "0,1" bitfld.long 0x4 3. "DIBRAM_RAMECC_PEND,Interrupt Pending Status for dibram_ramecc_pend" "0,1" bitfld.long 0x4 2. "AXISFIFO_RAMECC_PEND,Interrupt Pending Status for axisfifo_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "AXIMFIFO_RAMECC_PEND,Interrupt Pending Status for aximfifo_ramecc_pend" "0,1" bitfld.long 0x4 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "CORE__ECC_AGGR0__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 4. "AXI2VBUSM_MST_ENABLE_SET,Interrupt Enable Set Register for axi2vbusm_mst_pend" "0,1" bitfld.long 0x0 3. "DIBRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dibram_ramecc_pend" "0,1" bitfld.long 0x0 2. "AXISFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisfifo_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "AXIMFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for aximfifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "CORE__ECC_AGGR0__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 4. "AXI2VBUSM_MST_ENABLE_CLR,Interrupt Enable Clear Register for axi2vbusm_mst_pend" "0,1" bitfld.long 0x0 3. "DIBRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dibram_ramecc_pend" "0,1" bitfld.long 0x0 2. "AXISFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisfifo_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "AXIMFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for aximfifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "CORE__ECC_AGGR0__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "CORE__ECC_AGGR0__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 4. "AXI2VBUSM_MST_PEND,Interrupt Pending Status for axi2vbusm_mst_pend" "0,1" bitfld.long 0x4 3. "DIBRAM_RAMECC_PEND,Interrupt Pending Status for dibram_ramecc_pend" "0,1" bitfld.long 0x4 2. "AXISFIFO_RAMECC_PEND,Interrupt Pending Status for axisfifo_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "AXIMFIFO_RAMECC_PEND,Interrupt Pending Status for aximfifo_ramecc_pend" "0,1" bitfld.long 0x4 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "CORE__ECC_AGGR0__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 4. "AXI2VBUSM_MST_ENABLE_SET,Interrupt Enable Set Register for axi2vbusm_mst_pend" "0,1" bitfld.long 0x0 3. "DIBRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dibram_ramecc_pend" "0,1" bitfld.long 0x0 2. "AXISFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisfifo_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "AXIMFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for aximfifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "CORE__ECC_AGGR0__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 4. "AXI2VBUSM_MST_ENABLE_CLR,Interrupt Enable Clear Register for axi2vbusm_mst_pend" "0,1" bitfld.long 0x0 3. "DIBRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dibram_ramecc_pend" "0,1" bitfld.long 0x0 2. "AXISFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisfifo_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "AXIMFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for aximfifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "CORE__ECC_AGGR0__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "CORE__ECC_AGGR0__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "CORE__ECC_AGGR0__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "CORE__ECC_AGGR0__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "PCIE1_CORE_ECC_AGGR1 (PCIE1_CORE_ECC_AGGR1)" base ad:0x2A02000 rgroup.long 0x0++0x3 line.long 0x0 "CORE__ECC_AGGR1__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "CORE__ECC_AGGR1__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "CORE__ECC_AGGR1__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "CORE__ECC_AGGR1__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "CORE__ECC_AGGR1__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "CORE__ECC_AGGR1__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 3. "AXISRODR_RAMECC_PEND,Interrupt Pending Status for axisrodr_ramecc_pend" "0,1" bitfld.long 0x4 2. "RPLYBUF_RAMECC_PEND,Interrupt Pending Status for rplybuf_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "RXCPLFIFO_RAMECC_PEND,Interrupt Pending Status for rxcplfifo_ramecc_pend" "0,1" bitfld.long 0x4 0. "PNPFIFO_RAMECC_PEND,Interrupt Pending Status for pnpfifo_ramecc_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "CORE__ECC_AGGR1__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 3. "AXISRODR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisrodr_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPLYBUF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rplybuf_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "RXCPLFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rxcplfifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "PNPFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pnpfifo_ramecc_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "CORE__ECC_AGGR1__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 3. "AXISRODR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisrodr_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPLYBUF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rplybuf_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "RXCPLFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rxcplfifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "PNPFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pnpfifo_ramecc_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "CORE__ECC_AGGR1__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "CORE__ECC_AGGR1__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 3. "AXISRODR_RAMECC_PEND,Interrupt Pending Status for axisrodr_ramecc_pend" "0,1" bitfld.long 0x4 2. "RPLYBUF_RAMECC_PEND,Interrupt Pending Status for rplybuf_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "RXCPLFIFO_RAMECC_PEND,Interrupt Pending Status for rxcplfifo_ramecc_pend" "0,1" bitfld.long 0x4 0. "PNPFIFO_RAMECC_PEND,Interrupt Pending Status for pnpfifo_ramecc_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "CORE__ECC_AGGR1__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 3. "AXISRODR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisrodr_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPLYBUF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rplybuf_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "RXCPLFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rxcplfifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "PNPFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pnpfifo_ramecc_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "CORE__ECC_AGGR1__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 3. "AXISRODR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisrodr_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPLYBUF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rplybuf_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "RXCPLFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rxcplfifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "PNPFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pnpfifo_ramecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "CORE__ECC_AGGR1__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "CORE__ECC_AGGR1__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "CORE__ECC_AGGR1__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "CORE__ECC_AGGR1__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree.end tree "PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG (PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG)" base ad:0x2910000 rgroup.long 0x0++0x3 line.long 0x0 "CORE__PCIE_INTD_CFG__INTD_CFG_REVISION,Revision Register" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,RTL revisions" newline bitfld.long 0x0 8.--10. "MAJREV,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom revision" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,Minor revision" rgroup.long 0x100++0xB line.long 0x0 "CORE__PCIE_INTD_CFG__INTD_CFG_enable_reg_sys_0,Enable Register 0" bitfld.long 0x0 5. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_5,Enable Set for sys_en_pcie_downstream_5" "0,1" bitfld.long 0x0 4. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_4,Enable Set for sys_en_pcie_downstream_4" "0,1" newline bitfld.long 0x0 3. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_3,Enable Set for sys_en_pcie_downstream_3" "0,1" bitfld.long 0x0 2. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_2,Enable Set for sys_en_pcie_downstream_2" "0,1" newline bitfld.long 0x0 1. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_1,Enable Set for sys_en_pcie_downstream_1" "0,1" bitfld.long 0x0 0. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_0,Enable Set for sys_en_pcie_downstream_0" "0,1" line.long 0x4 "CORE__PCIE_INTD_CFG__INTD_CFG_enable_reg_sys_1,Enable Register 1" bitfld.long 0x4 26. "ENABLE_SYS_EN_PCIE_PWR_STATE,Enable Set for sys_en_pcie_pwr_state" "0,1" bitfld.long 0x4 25. "ENABLE_SYS_EN_PCIE_LEGACY_3,Enable Set for sys_en_pcie_legacy_3" "0,1" newline bitfld.long 0x4 24. "ENABLE_SYS_EN_PCIE_LEGACY_2,Enable Set for sys_en_pcie_legacy_2" "0,1" bitfld.long 0x4 23. "ENABLE_SYS_EN_PCIE_LEGACY_1,Enable Set for sys_en_pcie_legacy_1" "0,1" newline bitfld.long 0x4 22. "ENABLE_SYS_EN_PCIE_LEGACY_0,Enable Set for sys_en_pcie_legacy_0" "0,1" bitfld.long 0x4 21. "ENABLE_SYS_EN_PCIE_FLR_21,Enable Set for sys_en_pcie_flr_21" "0,1" newline bitfld.long 0x4 20. "ENABLE_SYS_EN_PCIE_FLR_20,Enable Set for sys_en_pcie_flr_20" "0,1" bitfld.long 0x4 19. "ENABLE_SYS_EN_PCIE_FLR_19,Enable Set for sys_en_pcie_flr_19" "0,1" newline bitfld.long 0x4 18. "ENABLE_SYS_EN_PCIE_FLR_18,Enable Set for sys_en_pcie_flr_18" "0,1" bitfld.long 0x4 17. "ENABLE_SYS_EN_PCIE_FLR_17,Enable Set for sys_en_pcie_flr_17" "0,1" newline bitfld.long 0x4 16. "ENABLE_SYS_EN_PCIE_FLR_16,Enable Set for sys_en_pcie_flr_16" "0,1" bitfld.long 0x4 15. "ENABLE_SYS_EN_PCIE_FLR_15,Enable Set for sys_en_pcie_flr_15" "0,1" newline bitfld.long 0x4 14. "ENABLE_SYS_EN_PCIE_FLR_14,Enable Set for sys_en_pcie_flr_14" "0,1" bitfld.long 0x4 13. "ENABLE_SYS_EN_PCIE_FLR_13,Enable Set for sys_en_pcie_flr_13" "0,1" newline bitfld.long 0x4 12. "ENABLE_SYS_EN_PCIE_FLR_12,Enable Set for sys_en_pcie_flr_12" "0,1" bitfld.long 0x4 11. "ENABLE_SYS_EN_PCIE_FLR_11,Enable Set for sys_en_pcie_flr_11" "0,1" newline bitfld.long 0x4 10. "ENABLE_SYS_EN_PCIE_FLR_10,Enable Set for sys_en_pcie_flr_10" "0,1" bitfld.long 0x4 9. "ENABLE_SYS_EN_PCIE_FLR_9,Enable Set for sys_en_pcie_flr_9" "0,1" newline bitfld.long 0x4 8. "ENABLE_SYS_EN_PCIE_FLR_8,Enable Set for sys_en_pcie_flr_8" "0,1" bitfld.long 0x4 7. "ENABLE_SYS_EN_PCIE_FLR_7,Enable Set for sys_en_pcie_flr_7" "0,1" newline bitfld.long 0x4 6. "ENABLE_SYS_EN_PCIE_FLR_6,Enable Set for sys_en_pcie_flr_6" "0,1" bitfld.long 0x4 5. "ENABLE_SYS_EN_PCIE_FLR_5,Enable Set for sys_en_pcie_flr_5" "0,1" newline bitfld.long 0x4 4. "ENABLE_SYS_EN_PCIE_FLR_4,Enable Set for sys_en_pcie_flr_4" "0,1" bitfld.long 0x4 3. "ENABLE_SYS_EN_PCIE_FLR_3,Enable Set for sys_en_pcie_flr_3" "0,1" newline bitfld.long 0x4 2. "ENABLE_SYS_EN_PCIE_FLR_2,Enable Set for sys_en_pcie_flr_2" "0,1" bitfld.long 0x4 1. "ENABLE_SYS_EN_PCIE_FLR_1,Enable Set for sys_en_pcie_flr_1" "0,1" newline bitfld.long 0x4 0. "ENABLE_SYS_EN_PCIE_FLR_0,Enable Set for sys_en_pcie_flr_0" "0,1" line.long 0x8 "CORE__PCIE_INTD_CFG__INTD_CFG_enable_reg_sys_2,Enable Register 2" bitfld.long 0x8 11. "ENABLE_SYS_EN_PCIE_PTM,Enable Set for sys_en_pcie_ptm" "0,1" bitfld.long 0x8 10. "ENABLE_SYS_EN_PCIE_LINK_STATE,Enable Set for sys_en_pcie_link_state" "0,1" newline bitfld.long 0x8 9. "ENABLE_SYS_EN_PCIE_HOT_RESET,Enable Set for sys_en_pcie_hot_reset" "0,1" bitfld.long 0x8 8. "ENABLE_SYS_EN_PCIE_ERROR_2,Enable Set for sys_en_pcie_error_2" "0,1" newline bitfld.long 0x8 7. "ENABLE_SYS_EN_PCIE_ERROR_1,Enable Set for sys_en_pcie_error_1" "0,1" bitfld.long 0x8 6. "ENABLE_SYS_EN_PCIE_ERROR_0,Enable Set for sys_en_pcie_error_0" "0,1" newline bitfld.long 0x8 5. "ENABLE_SYS_EN_PCIE_DPA_5,Enable Set for sys_en_pcie_dpa_5" "0,1" bitfld.long 0x8 4. "ENABLE_SYS_EN_PCIE_DPA_4,Enable Set for sys_en_pcie_dpa_4" "0,1" newline bitfld.long 0x8 3. "ENABLE_SYS_EN_PCIE_DPA_3,Enable Set for sys_en_pcie_dpa_3" "0,1" bitfld.long 0x8 2. "ENABLE_SYS_EN_PCIE_DPA_2,Enable Set for sys_en_pcie_dpa_2" "0,1" newline bitfld.long 0x8 1. "ENABLE_SYS_EN_PCIE_DPA_1,Enable Set for sys_en_pcie_dpa_1" "0,1" bitfld.long 0x8 0. "ENABLE_SYS_EN_PCIE_DPA_0,Enable Set for sys_en_pcie_dpa_0" "0,1" rgroup.long 0x300++0xB line.long 0x0 "CORE__PCIE_INTD_CFG__INTD_CFG_enable_clr_reg_sys_0,Enable Clear Register 0" bitfld.long 0x0 5. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_5_CLR,Enable Clear for sys_en_pcie_downstream_5" "0,1" bitfld.long 0x0 4. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_4_CLR,Enable Clear for sys_en_pcie_downstream_4" "0,1" newline bitfld.long 0x0 3. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_3_CLR,Enable Clear for sys_en_pcie_downstream_3" "0,1" bitfld.long 0x0 2. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_2_CLR,Enable Clear for sys_en_pcie_downstream_2" "0,1" newline bitfld.long 0x0 1. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_1_CLR,Enable Clear for sys_en_pcie_downstream_1" "0,1" bitfld.long 0x0 0. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_0_CLR,Enable Clear for sys_en_pcie_downstream_0" "0,1" line.long 0x4 "CORE__PCIE_INTD_CFG__INTD_CFG_enable_clr_reg_sys_1,Enable Clear Register 1" bitfld.long 0x4 26. "ENABLE_SYS_EN_PCIE_PWR_STATE_CLR,Enable Clear for sys_en_pcie_pwr_state" "0,1" bitfld.long 0x4 25. "ENABLE_SYS_EN_PCIE_LEGACY_3_CLR,Enable Clear for sys_en_pcie_legacy_3" "0,1" newline bitfld.long 0x4 24. "ENABLE_SYS_EN_PCIE_LEGACY_2_CLR,Enable Clear for sys_en_pcie_legacy_2" "0,1" bitfld.long 0x4 23. "ENABLE_SYS_EN_PCIE_LEGACY_1_CLR,Enable Clear for sys_en_pcie_legacy_1" "0,1" newline bitfld.long 0x4 22. "ENABLE_SYS_EN_PCIE_LEGACY_0_CLR,Enable Clear for sys_en_pcie_legacy_0" "0,1" bitfld.long 0x4 21. "ENABLE_SYS_EN_PCIE_FLR_21_CLR,Enable Clear for sys_en_pcie_flr_21" "0,1" newline bitfld.long 0x4 20. "ENABLE_SYS_EN_PCIE_FLR_20_CLR,Enable Clear for sys_en_pcie_flr_20" "0,1" bitfld.long 0x4 19. "ENABLE_SYS_EN_PCIE_FLR_19_CLR,Enable Clear for sys_en_pcie_flr_19" "0,1" newline bitfld.long 0x4 18. "ENABLE_SYS_EN_PCIE_FLR_18_CLR,Enable Clear for sys_en_pcie_flr_18" "0,1" bitfld.long 0x4 17. "ENABLE_SYS_EN_PCIE_FLR_17_CLR,Enable Clear for sys_en_pcie_flr_17" "0,1" newline bitfld.long 0x4 16. "ENABLE_SYS_EN_PCIE_FLR_16_CLR,Enable Clear for sys_en_pcie_flr_16" "0,1" bitfld.long 0x4 15. "ENABLE_SYS_EN_PCIE_FLR_15_CLR,Enable Clear for sys_en_pcie_flr_15" "0,1" newline bitfld.long 0x4 14. "ENABLE_SYS_EN_PCIE_FLR_14_CLR,Enable Clear for sys_en_pcie_flr_14" "0,1" bitfld.long 0x4 13. "ENABLE_SYS_EN_PCIE_FLR_13_CLR,Enable Clear for sys_en_pcie_flr_13" "0,1" newline bitfld.long 0x4 12. "ENABLE_SYS_EN_PCIE_FLR_12_CLR,Enable Clear for sys_en_pcie_flr_12" "0,1" bitfld.long 0x4 11. "ENABLE_SYS_EN_PCIE_FLR_11_CLR,Enable Clear for sys_en_pcie_flr_11" "0,1" newline bitfld.long 0x4 10. "ENABLE_SYS_EN_PCIE_FLR_10_CLR,Enable Clear for sys_en_pcie_flr_10" "0,1" bitfld.long 0x4 9. "ENABLE_SYS_EN_PCIE_FLR_9_CLR,Enable Clear for sys_en_pcie_flr_9" "0,1" newline bitfld.long 0x4 8. "ENABLE_SYS_EN_PCIE_FLR_8_CLR,Enable Clear for sys_en_pcie_flr_8" "0,1" bitfld.long 0x4 7. "ENABLE_SYS_EN_PCIE_FLR_7_CLR,Enable Clear for sys_en_pcie_flr_7" "0,1" newline bitfld.long 0x4 6. "ENABLE_SYS_EN_PCIE_FLR_6_CLR,Enable Clear for sys_en_pcie_flr_6" "0,1" bitfld.long 0x4 5. "ENABLE_SYS_EN_PCIE_FLR_5_CLR,Enable Clear for sys_en_pcie_flr_5" "0,1" newline bitfld.long 0x4 4. "ENABLE_SYS_EN_PCIE_FLR_4_CLR,Enable Clear for sys_en_pcie_flr_4" "0,1" bitfld.long 0x4 3. "ENABLE_SYS_EN_PCIE_FLR_3_CLR,Enable Clear for sys_en_pcie_flr_3" "0,1" newline bitfld.long 0x4 2. "ENABLE_SYS_EN_PCIE_FLR_2_CLR,Enable Clear for sys_en_pcie_flr_2" "0,1" bitfld.long 0x4 1. "ENABLE_SYS_EN_PCIE_FLR_1_CLR,Enable Clear for sys_en_pcie_flr_1" "0,1" newline bitfld.long 0x4 0. "ENABLE_SYS_EN_PCIE_FLR_0_CLR,Enable Clear for sys_en_pcie_flr_0" "0,1" line.long 0x8 "CORE__PCIE_INTD_CFG__INTD_CFG_enable_clr_reg_sys_2,Enable Clear Register 2" bitfld.long 0x8 11. "ENABLE_SYS_EN_PCIE_PTM_CLR,Enable Clear for sys_en_pcie_ptm" "0,1" bitfld.long 0x8 10. "ENABLE_SYS_EN_PCIE_LINK_STATE_CLR,Enable Clear for sys_en_pcie_link_state" "0,1" newline bitfld.long 0x8 9. "ENABLE_SYS_EN_PCIE_HOT_RESET_CLR,Enable Clear for sys_en_pcie_hot_reset" "0,1" bitfld.long 0x8 8. "ENABLE_SYS_EN_PCIE_ERROR_2_CLR,Enable Clear for sys_en_pcie_error_2" "0,1" newline bitfld.long 0x8 7. "ENABLE_SYS_EN_PCIE_ERROR_1_CLR,Enable Clear for sys_en_pcie_error_1" "0,1" bitfld.long 0x8 6. "ENABLE_SYS_EN_PCIE_ERROR_0_CLR,Enable Clear for sys_en_pcie_error_0" "0,1" newline bitfld.long 0x8 5. "ENABLE_SYS_EN_PCIE_DPA_5_CLR,Enable Clear for sys_en_pcie_dpa_5" "0,1" bitfld.long 0x8 4. "ENABLE_SYS_EN_PCIE_DPA_4_CLR,Enable Clear for sys_en_pcie_dpa_4" "0,1" newline bitfld.long 0x8 3. "ENABLE_SYS_EN_PCIE_DPA_3_CLR,Enable Clear for sys_en_pcie_dpa_3" "0,1" bitfld.long 0x8 2. "ENABLE_SYS_EN_PCIE_DPA_2_CLR,Enable Clear for sys_en_pcie_dpa_2" "0,1" newline bitfld.long 0x8 1. "ENABLE_SYS_EN_PCIE_DPA_1_CLR,Enable Clear for sys_en_pcie_dpa_1" "0,1" bitfld.long 0x8 0. "ENABLE_SYS_EN_PCIE_DPA_0_CLR,Enable Clear for sys_en_pcie_dpa_0" "0,1" rgroup.long 0x500++0x7 line.long 0x0 "CORE__PCIE_INTD_CFG__INTD_CFG_status_reg_sys_0,Status Register 0" bitfld.long 0x0 5. "STATUS_SYS_PCIE_DOWNSTREAM_5,Status for sys_en_pcie_downstream_5" "0,1" bitfld.long 0x0 4. "STATUS_SYS_PCIE_DOWNSTREAM_4,Status for sys_en_pcie_downstream_4" "0,1" newline bitfld.long 0x0 3. "STATUS_SYS_PCIE_DOWNSTREAM_3,Status for sys_en_pcie_downstream_3" "0,1" bitfld.long 0x0 2. "STATUS_SYS_PCIE_DOWNSTREAM_2,Status for sys_en_pcie_downstream_2" "0,1" newline bitfld.long 0x0 1. "STATUS_SYS_PCIE_DOWNSTREAM_1,Status for sys_en_pcie_downstream_1" "0,1" bitfld.long 0x0 0. "STATUS_SYS_PCIE_DOWNSTREAM_0,Status for sys_en_pcie_downstream_0" "0,1" line.long 0x4 "CORE__PCIE_INTD_CFG__INTD_CFG_status_reg_sys_1,Status Register 1" bitfld.long 0x4 26. "STATUS_SYS_PCIE_PWR_STATE,Status for sys_en_pcie_pwr_state" "0,1" bitfld.long 0x4 25. "STATUS_SYS_PCIE_LEGACY_3,Status for sys_en_pcie_legacy_3" "0,1" newline bitfld.long 0x4 24. "STATUS_SYS_PCIE_LEGACY_2,Status for sys_en_pcie_legacy_2" "0,1" bitfld.long 0x4 23. "STATUS_SYS_PCIE_LEGACY_1,Status for sys_en_pcie_legacy_1" "0,1" newline bitfld.long 0x4 22. "STATUS_SYS_PCIE_LEGACY_0,Status for sys_en_pcie_legacy_0" "0,1" bitfld.long 0x4 21. "STATUS_SYS_PCIE_FLR_21,Status for sys_en_pcie_flr_21" "0,1" newline bitfld.long 0x4 20. "STATUS_SYS_PCIE_FLR_20,Status for sys_en_pcie_flr_20" "0,1" bitfld.long 0x4 19. "STATUS_SYS_PCIE_FLR_19,Status for sys_en_pcie_flr_19" "0,1" newline bitfld.long 0x4 18. "STATUS_SYS_PCIE_FLR_18,Status for sys_en_pcie_flr_18" "0,1" bitfld.long 0x4 17. "STATUS_SYS_PCIE_FLR_17,Status for sys_en_pcie_flr_17" "0,1" newline bitfld.long 0x4 16. "STATUS_SYS_PCIE_FLR_16,Status for sys_en_pcie_flr_16" "0,1" bitfld.long 0x4 15. "STATUS_SYS_PCIE_FLR_15,Status for sys_en_pcie_flr_15" "0,1" newline bitfld.long 0x4 14. "STATUS_SYS_PCIE_FLR_14,Status for sys_en_pcie_flr_14" "0,1" bitfld.long 0x4 13. "STATUS_SYS_PCIE_FLR_13,Status for sys_en_pcie_flr_13" "0,1" newline bitfld.long 0x4 12. "STATUS_SYS_PCIE_FLR_12,Status for sys_en_pcie_flr_12" "0,1" bitfld.long 0x4 11. "STATUS_SYS_PCIE_FLR_11,Status for sys_en_pcie_flr_11" "0,1" newline bitfld.long 0x4 10. "STATUS_SYS_PCIE_FLR_10,Status for sys_en_pcie_flr_10" "0,1" bitfld.long 0x4 9. "STATUS_SYS_PCIE_FLR_9,Status for sys_en_pcie_flr_9" "0,1" newline bitfld.long 0x4 8. "STATUS_SYS_PCIE_FLR_8,Status for sys_en_pcie_flr_8" "0,1" bitfld.long 0x4 7. "STATUS_SYS_PCIE_FLR_7,Status for sys_en_pcie_flr_7" "0,1" newline bitfld.long 0x4 6. "STATUS_SYS_PCIE_FLR_6,Status for sys_en_pcie_flr_6" "0,1" bitfld.long 0x4 5. "STATUS_SYS_PCIE_FLR_5,Status for sys_en_pcie_flr_5" "0,1" newline bitfld.long 0x4 4. "STATUS_SYS_PCIE_FLR_4,Status for sys_en_pcie_flr_4" "0,1" bitfld.long 0x4 3. "STATUS_SYS_PCIE_FLR_3,Status for sys_en_pcie_flr_3" "0,1" newline bitfld.long 0x4 2. "STATUS_SYS_PCIE_FLR_2,Status for sys_en_pcie_flr_2" "0,1" bitfld.long 0x4 1. "STATUS_SYS_PCIE_FLR_1,Status for sys_en_pcie_flr_1" "0,1" newline bitfld.long 0x4 0. "STATUS_SYS_PCIE_FLR_0,Status for sys_en_pcie_flr_0" "0,1" rgroup.long 0x508++0x3 line.long 0x0 "CORE__PCIE_INTD_CFG__INTD_CFG_status_reg_sys_2,Status Register 2" bitfld.long 0x0 11. "STATUS_SYS_PCIE_PTM,Status write 1 to set for sys_en_pcie_ptm" "0,1" bitfld.long 0x0 10. "STATUS_SYS_PCIE_LINK_STATE,Status write 1 to set for sys_en_pcie_link_state" "0,1" newline bitfld.long 0x0 9. "STATUS_SYS_PCIE_HOT_RESET,Status write 1 to set for sys_en_pcie_hot_reset" "0,1" bitfld.long 0x0 8. "STATUS_SYS_PCIE_ERROR_2,Status write 1 to set for sys_en_pcie_error_2" "0,1" newline bitfld.long 0x0 7. "STATUS_SYS_PCIE_ERROR_1,Status write 1 to set for sys_en_pcie_error_1" "0,1" bitfld.long 0x0 6. "STATUS_SYS_PCIE_ERROR_0,Status write 1 to set for sys_en_pcie_error_0" "0,1" newline bitfld.long 0x0 5. "STATUS_SYS_PCIE_DPA_5,Status write 1 to set for sys_en_pcie_dpa_5" "0,1" bitfld.long 0x0 4. "STATUS_SYS_PCIE_DPA_4,Status write 1 to set for sys_en_pcie_dpa_4" "0,1" newline bitfld.long 0x0 3. "STATUS_SYS_PCIE_DPA_3,Status write 1 to set for sys_en_pcie_dpa_3" "0,1" bitfld.long 0x0 2. "STATUS_SYS_PCIE_DPA_2,Status write 1 to set for sys_en_pcie_dpa_2" "0,1" newline bitfld.long 0x0 1. "STATUS_SYS_PCIE_DPA_1,Status write 1 to set for sys_en_pcie_dpa_1" "0,1" bitfld.long 0x0 0. "STATUS_SYS_PCIE_DPA_0,Status write 1 to set for sys_en_pcie_dpa_0" "0,1" rgroup.long 0x708++0x3 line.long 0x0 "CORE__PCIE_INTD_CFG__INTD_CFG_status_clr_reg_sys_2,Status Clear Register 2" bitfld.long 0x0 11. "STATUS_SYS_PCIE_PTM_CLR,Status write 1 to clear for sys_en_pcie_ptm" "0,1" bitfld.long 0x0 10. "STATUS_SYS_PCIE_LINK_STATE_CLR,Status write 1 to clear for sys_en_pcie_link_state" "0,1" newline bitfld.long 0x0 9. "STATUS_SYS_PCIE_HOT_RESET_CLR,Status write 1 to clear for sys_en_pcie_hot_reset" "0,1" bitfld.long 0x0 8. "STATUS_SYS_PCIE_ERROR_2_CLR,Status write 1 to clear for sys_en_pcie_error_2" "0,1" newline bitfld.long 0x0 7. "STATUS_SYS_PCIE_ERROR_1_CLR,Status write 1 to clear for sys_en_pcie_error_1" "0,1" bitfld.long 0x0 6. "STATUS_SYS_PCIE_ERROR_0_CLR,Status write 1 to clear for sys_en_pcie_error_0" "0,1" newline bitfld.long 0x0 5. "STATUS_SYS_PCIE_DPA_5_CLR,Status write 1 to clear for sys_en_pcie_dpa_5" "0,1" bitfld.long 0x0 4. "STATUS_SYS_PCIE_DPA_4_CLR,Status write 1 to clear for sys_en_pcie_dpa_4" "0,1" newline bitfld.long 0x0 3. "STATUS_SYS_PCIE_DPA_3_CLR,Status write 1 to clear for sys_en_pcie_dpa_3" "0,1" bitfld.long 0x0 2. "STATUS_SYS_PCIE_DPA_2_CLR,Status write 1 to clear for sys_en_pcie_dpa_2" "0,1" newline bitfld.long 0x0 1. "STATUS_SYS_PCIE_DPA_1_CLR,Status write 1 to clear for sys_en_pcie_dpa_1" "0,1" bitfld.long 0x0 0. "STATUS_SYS_PCIE_DPA_0_CLR,Status write 1 to clear for sys_en_pcie_dpa_0" "0,1" rgroup.long 0xA80++0x3 line.long 0x0 "CORE__PCIE_INTD_CFG__INTD_CFG_intr_vector_reg_sys,Interrupt Vector for sys" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR_SYS,Interrupt Vector" tree.end tree "PCIE1_CORE_USER_CFG_USER_CFG (PCIE1_CORE_USER_CFG_USER_CFG)" base ad:0x2917000 rgroup.long 0x0++0x3 line.long 0x0 "CORE__USER_CFG__USER_CFG_revid,Module ID register" hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release" newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0xF line.long 0x0 "CORE__USER_CFG__USER_CFG_cmd_status,Command Status register" bitfld.long 0x0 0. "LINK_TRAINING_ENABLE,This bit must be set to 1 to enable the LTSSM to bring up the link. Setting it to 0 forces the LTSSM to stay in the Detect.Quiet state." "0,1" line.long 0x4 "CORE__USER_CFG__USER_CFG_rstcmd,Reset Command and Status register" bitfld.long 0x4 0. "INIT_HOT_RESET,When this bit is set to 1'b1 in the RP mode the core initiates a Hot Reset sequence on the PCIe link. The controller will keep the PCIe link in hot reset when this bit is asserted. When de-asserted controller will bring the PCIe link.." "0,1" line.long 0x8 "CORE__USER_CFG__USER_CFG_initcfg,Initialization configuration register" bitfld.long 0x8 24. "CONFIG_ENABLE,When this bit is set to 0 in the EP mode the Controller will generate a CRS Completion in response to Configuration Requests. When this bit is set to 1 in the EP mode the Controller will generate SC/UR Completion in response to.." "0,1" newline bitfld.long 0x8 22.--23. "VC_COUNT,Number of VCs configured. 00 = 1 VC 01 = 2 VCs 10 = 3 VCs 11 = 4 VCs .. and so on" "0,1,2,3" newline hexmask.long.byte 0x8 15.--21. 1. "MAX_EVAL_ITERATION,Denotes the maximum number of iterations to be performed during the DirectionChange Feedback Link Equalization in case the direction change feedback does not converge to 00. Supported values are 8-63. Recommended Value is from 8-16 to.." newline bitfld.long 0x8 14. "BYPASS_PHASE23,This MMR should be programmed during system boot or initialization. This is used only in Root Port Mode of the PCIe Core. If BYPASS_PHASE23==1: * Phase 2 AND Phase 3 of Link Equalization are bypassed during link equalization If.." "0,1" newline bitfld.long 0x8 13. "BYPASS_REMOTE_TX_EQUALIZATION,This MMR should be programmed during system boot or initialization. IF BYPASS_REMOTE_TX_EQUALIZATION==1: * In End-Point mode Phase 2 of link equalization is bypassed * In Root-Port mode Phase 3 of link equalization is.." "0,1" newline hexmask.long.word 0x8 2.--12. 1. "SUPPORTED_PRESET,This MMR should be programmed during system boot or initialization. SUPPORTED_PRESET[i]=1. Indicates Preset #i supported by PHY. SUPPORTED_PRESET[i]=0. Indicates Preset #i is not supported by PHY. * For Full Swing all presets [P0 - P10].." newline bitfld.long 0x8 1. "DISABLE_GEN3_DC_BALANCE,This bit it is used to disable the transmission of special DC Balance symbols in TS1 training sequences for improving the DC balance of the bit stream at 8.0 GT/s or higher speed. This feature was introduced in the 0.71 version of.." "0,1" newline bitfld.long 0x8 0. "SRIS_ENABLE,Should be set as per the System Reference Clocking Implementation. 0 = Separate Tx and Rx Reference Clocks with No Spread Spectum Clocking - SRNS Mode 1 = Separate Tx and Rx Reference Clocks with Spread Spectum Clocking - SRIS Mode. This is.." "0: Separate Tx and Rx Reference Clocks with No..,1: Separate Tx and Rx Reference Clocks with Spread.." line.long 0xC "CORE__USER_CFG__USER_CFG_pmcmd,Power Management command register" bitfld.long 0xC 2. "POWER_STATE_CHANGE_ACK,Software must assert this bit for a minimum of one cycle in response to the assertion of POWER_STATE_CHANGE_INTERRUPT when it is ready to transition to the low-power state requested by the configuration write request. Software may.." "0,1" newline bitfld.long 0xC 1. "CLIENT_REQ_EXIT_L1_SUBSTATE,Client logic can trigger an explicit L1-substate exit by setting this bit. This bit triggers an exit from L1-substates to L0 if controller is already in L1- substates. Controller waits in L1 state for this signal to become.." "?,1: exit triggers while it waits for de-assertion of.." newline bitfld.long 0xC 0. "CLIENT_REQ_EXIT_L1,Client logic can trigger an explicit L1 exit by setting this bit. This bit triggers an exit to L0 from L1 or from L1-substates. This bit can also be used to block L1 entry in End point controllers." "?,1: substates" rgroup.long 0x14++0x3 line.long 0x0 "CORE__USER_CFG__USER_CFG_linkstatus,Link Status register" hexmask.long.byte 0x0 24.--29. 1. "LTSSM_STATE,Current state of the Link Training and Status State Machine within the core. The encodings of this output are described in Appendix C of the Cadence User guide." newline hexmask.long.byte 0x0 16.--23. 1. "POWER_STATE_CHANGE_FUNCTION_NUM,Function number of the function for which a power state change occurred. Software can read this value when the power_state_change interrupt is asserted to determine the physical function for which the power state change.." newline bitfld.long 0x0 12.--14. "L1_PM_SUBSTATE,This register provides the current state of the L1 PM substates state machine. Its encodings are: 000 = L1-substate machine not active 001 = L1.0 substate. L1_PM_SUBSTATE shows L1.0 after the delay programmed in L1 substate entry delay in.." "0: L1-substate machine not active,1: L1,?,?,?,?,?,?" newline hexmask.long.byte 0x0 8.--11. 1. "LINK_POWER_STATE,Current power state of the PCIe link. 0001 = L0 0010 = L0s 0100 = L1 1000 = L2" newline bitfld.long 0x0 4.--5. "NEGOTIATED_SPEED,Current operating speed of the link is as follows: 11: 16 GT/s 10: 8GT/s 01: 5GT/s 00: 2.5GT/s" "0,1,2,3" newline bitfld.long 0x0 2.--3. "NEGOTIATED_LINK_WIDTH,Current link width are as follows: 10: x4 01: x2 00: x1 Others: Reserved" "0: x1 Others: Reserved,1: x2,?,?" newline bitfld.long 0x0 0.--1. "LINK_STATUS,Status of the PCI Express link. 00 = No receivers detected. 01 = Link training in progress. 10 = Link up DL initialization in progress. 11 = Link up DL initialization completed." "0: No receivers detected,1: Link training in progress,?,?" rgroup.long 0x18++0x7 line.long 0x0 "CORE__USER_CFG__USER_CFG_legacy_intr_set,Legacy interrupt set register" bitfld.long 0x0 3. "INTD_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express. This bit corresponds to INTD of.." "0,1" newline bitfld.long 0x0 2. "INTC_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express. This bit corresponds to INTC of.." "0,1" newline bitfld.long 0x0 1. "INTB_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express. This bit corresponds to INTB of.." "0,1" newline bitfld.long 0x0 0. "INTA_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express. This bit corresponds to INTA of.." "0,1" line.long 0x4 "CORE__USER_CFG__USER_CFG_legacy_int_pending,Legacy interrupt pending set register" bitfld.long 0x4 8. "INT_ACK,When using legacy interrupts this bit indicates that the core has sent an INTx Assert or Deassert message in response to a change in the state of one of the INTx inputs." "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "INT_PENDING_STATUS,When using legacy interrupts this input is used to indicate the interrupt pending status of the Physical Functions. The bit i must be set when an interrupt is pending in Function i." rgroup.long 0x20++0x1F line.long 0x0 "CORE__USER_CFG__USER_CFG_msi_stat,MSI status register" hexmask.long.byte 0x0 0.--5. 1. "MSI_ENABLE,When the core is configured in the EndPoint mode to support MSI interrupts this output is driven by the MSI Enable bit of the MSI Control Registers of the Physical Functions. Bit0 represents the MSI Enable for Physical Function0 and Bit1.." line.long 0x4 "CORE__USER_CFG__USER_CFG_msi_vector,MSI vector register" hexmask.long.tbyte 0x4 0.--17. 1. "MSI_VECTOR_COUNT,When the core is configured in the EndPoint mode to support MSI interrupts these outputs are driven by the Multiple Message Enable bits of the MSI Control Registers associated with Physical Functions. These bits encode the number of.." line.long 0x8 "CORE__USER_CFG__USER_CFG_msi_mask_pf0,PF0 MSI mask register" hexmask.long 0x8 0.--31. 1. "MSI_MASK_PF0,These bits provide the setting of the MSI Mask registers of the Physical Function0." line.long 0xC "CORE__USER_CFG__USER_CFG_msi_mask_pf1,PF1 MSI mask register" hexmask.long 0xC 0.--31. 1. "MSI_MASK_PF1,These bits provide the setting of the MSI Mask registers of the Physical Function1." line.long 0x10 "CORE__USER_CFG__USER_CFG_msi_mask_pf2,PF2 MSI mask register" hexmask.long 0x10 0.--31. 1. "MSI_MASK_PF2,These bits provide the setting of the MSI Mask registers of the Physical Function2." line.long 0x14 "CORE__USER_CFG__USER_CFG_msi_mask_pf3,PF3 MSI mask register" hexmask.long 0x14 0.--31. 1. "MSI_MASK_PF3,These bits provide the setting of the MSI Mask registers of the Physical Function3." line.long 0x18 "CORE__USER_CFG__USER_CFG_msi_mask_pf4,PF4 MSI mask register" hexmask.long 0x18 0.--31. 1. "MSI_MASK_PF4,These bits provide the setting of the MSI Mask registers of the Physical Function4." line.long 0x1C "CORE__USER_CFG__USER_CFG_msi_mask_pf5,PF5 MSI mask register" hexmask.long 0x1C 0.--31. 1. "MSI_MASK_PF5,These bits provide the setting of the MSI Mask registers of the Physical Function5." rgroup.long 0x40++0x17 line.long 0x0 "CORE__USER_CFG__USER_CFG_msi_pending_status_pf0,PF0 MSI pending status input register" hexmask.long 0x0 0.--31. 1. "MSI_PENDING_STATUS_PF0,These inputs provide the status of the MSI pending interrupts for the Physical Function0 from the client to the core. If MSI Pending Status In Mode Select is set to 1 in the Debug Mux Control 2 register in local management the.." line.long 0x4 "CORE__USER_CFG__USER_CFG_msi_pending_status_pf1,PF1 MSI pending status input register" hexmask.long 0x4 0.--31. 1. "MSI_PENDING_STATUS_PF1,These inputs provide the status of the MSI pending interrupts for the Physical Function1 from the client to the core if MSI Pending Status In Mode Select is set to 1 in the Debug Mux Control 2 register in local management the.." line.long 0x8 "CORE__USER_CFG__USER_CFG_msi_pending_status_pf2,PF2 MSI pending status input register" hexmask.long 0x8 0.--31. 1. "MSI_PENDING_STATUS_PF2,These inputs provide the status of the MSI pending interrupts for the Physical Function1 from the client to the core if MSI Pending Status In Mode Select is set to 1 in the Debug Mux Control 2 register in local management the.." line.long 0xC "CORE__USER_CFG__USER_CFG_msi_pending_status_pf3,PF3 MSI pending status input register" hexmask.long 0xC 0.--31. 1. "MSI_PENDING_STATUS_PF3,These inputs provide the status of the MSI pending interrupts for the Physical Function1 from the client to the core if MSI Pending Status In Mode Select is set to 1 in the Debug Mux Control 2 register in local management the.." line.long 0x10 "CORE__USER_CFG__USER_CFG_msi_pending_status_pf4,PF4 MSI pending status input register" hexmask.long 0x10 0.--31. 1. "MSI_PENDING_STATUS_PF4,These inputs provide the status of the MSI pending interrupts for the Physical Function1 from the client to the core if MSI Pending Status In Mode Select is set to 1 in the Debug Mux Control 2 register in local management the.." line.long 0x14 "CORE__USER_CFG__USER_CFG_msi_pending_status_pf5,PF5 MSI pending status input register" hexmask.long 0x14 0.--31. 1. "MSI_PENDING_STATUS_PF5,These inputs provide the status of the MSI pending interrupts for the Physical Function1 from the client to the core if MSI Pending Status In Mode Select is set to 1 in the Debug Mux Control 2 register in local management the.." rgroup.long 0x58++0x5B line.long 0x0 "CORE__USER_CFG__USER_CFG_msi_stat_vf,MSI_VF status register" hexmask.long.word 0x0 0.--15. 1. "VF_MSI_ENABLE,When the core is configured in the EndPoint mode to support MSI interrupts this output is driven by the MSI Enable bit of the MSI Control Registers of the Virtual Functions. Bit0 represents the MSI Enable for Virtual Function0 Bit1.." line.long 0x4 "CORE__USER_CFG__USER_CFG_msi_vector0_vf,MSI_VF vector count register0" hexmask.long.tbyte 0x4 0.--23. 1. "VF_MSI_VECTOR_COUNT0,When the core is configured in the Endpoint mode to support MSI interrupts these outputs are driven by the Multiple Message Enable bits of the MSI Control Registers associated with Virtual Function0 thru Virtual Function7. These.." line.long 0x8 "CORE__USER_CFG__USER_CFG_msi_vector1_vf,MSI_VF vector count register1" hexmask.long.tbyte 0x8 0.--23. 1. "VF_MSI_VECTOR_COUNT1,When the core is configured in the Endpoint mode to support MSI interrupts these outputs are driven by the Multiple Message Enable bits of the MSI Control Registers associated with Virtual Function8 thru Virtual Function15. These.." line.long 0xC "CORE__USER_CFG__USER_CFG_msi_mask_vf0,VF0MSI mask register" hexmask.long 0xC 0.--31. 1. "MSI_MASK_VF0,These bits provide the setting of the MSI Mask registers of the Virtual Function0." line.long 0x10 "CORE__USER_CFG__USER_CFG_msi_mask_vf1,VF1MSI mask register" hexmask.long 0x10 0.--31. 1. "MSI_MASK_VF1,These bits provide the setting of the MSI Mask registers of the Virtual Function1." line.long 0x14 "CORE__USER_CFG__USER_CFG_msi_mask_vf2,VF2MSI mask register" hexmask.long 0x14 0.--31. 1. "MSI_MASK_VF2,These bits provide the setting of the MSI Mask registers of the Virtual Function2." line.long 0x18 "CORE__USER_CFG__USER_CFG_msi_mask_vf3,VF3MSI mask register" hexmask.long 0x18 0.--31. 1. "MSI_MASK_VF3,These bits provide the setting of the MSI Mask registers of the Virtual Function3." line.long 0x1C "CORE__USER_CFG__USER_CFG_msi_mask_vf4,VF4MSI mask register" hexmask.long 0x1C 0.--31. 1. "MSI_MASK_VF4,These bits provide the setting of the MSI Mask registers of the Virtual Function4." line.long 0x20 "CORE__USER_CFG__USER_CFG_msi_mask_vf5,VF5MSI mask register" hexmask.long 0x20 0.--31. 1. "MSI_MASK_VF5,These bits provide the setting of the MSI Mask registers of the Virtual Function5." line.long 0x24 "CORE__USER_CFG__USER_CFG_msi_mask_vf6,VF6MSI mask register" hexmask.long 0x24 0.--31. 1. "MSI_MASK_VF6,These bits provide the setting of the MSI Mask registers of the Virtual Function6." line.long 0x28 "CORE__USER_CFG__USER_CFG_msi_mask_vf7,VF7MSI mask register" hexmask.long 0x28 0.--31. 1. "MSI_MASK_VF7,These bits provide the setting of the MSI Mask registers of the Virtual Function7." line.long 0x2C "CORE__USER_CFG__USER_CFG_msi_mask_vf8,VF8MSI mask register" hexmask.long 0x2C 0.--31. 1. "MSI_MASK_VF8,These bits provide the setting of the MSI Mask registers of the Virtual Function8." line.long 0x30 "CORE__USER_CFG__USER_CFG_msi_mask_vf9,VF9MSI mask register" hexmask.long 0x30 0.--31. 1. "MSI_MASK_VF9,These bits provide the setting of the MSI Mask registers of the Virtual Function9." line.long 0x34 "CORE__USER_CFG__USER_CFG_msi_mask_vf10,VF10MSI mask register" hexmask.long 0x34 0.--31. 1. "MSI_MASK_VF10,These bits provide the setting of the MSI Mask registers of the Virtual Function10." line.long 0x38 "CORE__USER_CFG__USER_CFG_msi_mask_vf11,VF11MSI mask register" hexmask.long 0x38 0.--31. 1. "MSI_MASK_VF11,These bits provide the setting of the MSI Mask registers of the Virtual Function11." line.long 0x3C "CORE__USER_CFG__USER_CFG_msi_mask_vf12,VF12MSI mask register" hexmask.long 0x3C 0.--31. 1. "MSI_MASK_VF12,These bits provide the setting of the MSI Mask registers of the Virtual Function12." line.long 0x40 "CORE__USER_CFG__USER_CFG_msi_mask_vf13,VF13MSI mask register" hexmask.long 0x40 0.--31. 1. "MSI_MASK_VF13,These bits provide the setting of the MSI Mask registers of the Virtual Function13." line.long 0x44 "CORE__USER_CFG__USER_CFG_msi_mask_vf14,VF14MSI mask register" hexmask.long 0x44 0.--31. 1. "MSI_MASK_VF14,These bits provide the setting of the MSI Mask registers of the Virtual Function14." line.long 0x48 "CORE__USER_CFG__USER_CFG_msi_mask_vf15,VF15MSI mask register" hexmask.long 0x48 0.--31. 1. "MSI_MASK_VF15,These bits provide the setting of the MSI Mask registers of the Virtual Function15." line.long 0x4C "CORE__USER_CFG__USER_CFG_msix_stat,MSIX status register" hexmask.long.byte 0x4C 0.--5. 1. "MSIX_ENABLE,These bits reflect the states of the MSI-X Enable bits in the PCI configuration space of Physical Functions.Bit0 represents the MSIX Enable for Physical Function0 and Bit1 represents the MSIX Enable for Physical Function 1" line.long 0x50 "CORE__USER_CFG__USER_CFG_msix_mask,MSIX mask register" hexmask.long.byte 0x50 0.--5. 1. "MSIX_MASK,These bits reflect the states of the MSI-X Function Mask bits in the PCI configuration space of Physical Functions. Bit0 represents Physical Function0 and Bit1 represents Physical Function1" line.long 0x54 "CORE__USER_CFG__USER_CFG_msix_stat_vf,Virtual Function MSIX status register" hexmask.long.word 0x54 0.--15. 1. "VF_MSIX_ENABLE,These bits reflect the states of the MSI-X Enable bits in the PCI configuration space of virtual Functions.Bit0 represents the MSIX Enable for Virtual Function0 Bit1 represents the MSIX Enable for Virtual Function 1 and so on" line.long 0x58 "CORE__USER_CFG__USER_CFG_msix_mask_vf,Virtual Function MSIX mask register" hexmask.long.word 0x58 0.--15. 1. "VF_MSIX_MASK,These bits reflect the states of the MSI-X Function Mask bits in the PCI configuration space of Virtual Functions. Bit0 represents Virtual Function0 Bit1 represents Virtual Function1 and so on" rgroup.long 0xB4++0x7 line.long 0x0 "CORE__USER_CFG__USER_CFG_flr_done,Physical Function-Level Reset Done register" hexmask.long.byte 0x0 0.--5. 1. "FLR_DONE,These bits are connected to the FLR_DONE bits on the PCIe controller core. In EP mode software needs to write a 1 to bit0 within 100ms after PF0 function-level reset interrupt is asserted. The FLR_DONE[0] input of the PCIe controller is pulsed.." line.long 0x4 "CORE__USER_CFG__USER_CFG_vf_flr_done,Virtual Function-Level Reset Done register" hexmask.long.word 0x4 0.--15. 1. "VF_FLR_DONE,These bits are connected to the VF_FLR_DONE bits on the PCIe controller core. In EP mode software needs to write a 1 to bit0 within 100ms after VF0 function-level reset interrupt is asserted. The VF_FLR_DONE[0] input of the PCIe controller.." rgroup.long 0xBC++0x3 line.long 0x0 "CORE__USER_CFG__USER_CFG_ptm_cfg,PTM Timestamp configuration register" bitfld.long 0x0 8.--10. "PTM_EP_TIMER_ADJ,PTM EP Timer tick adjust value. 1 will increment ptm_ep_timer by 1 each clock cycle 2 will increment the timer by 2 .. 7 will increment the timer by 7. The adjust value should be set prior to enabling PTM operation in the PCIe controller." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--6. 1. "PTM_CLK_SEL,Select CPTS HW1 push input. 0 will select ptm_local_timer[0] 1 will select ptm_local_timer[1] ... 63 will select ptm_local_timer[63] and 64 will select ptm_local_timer_out_valid. The values 65 to 127 are unused. The PTM clock select bit.." rgroup.long 0xC0++0x7 line.long 0x0 "CORE__USER_CFG__USER_CFG_ptm_timer_low,PTM timer value lower 32-bits" hexmask.long 0x0 0.--31. 1. "PTM_TIMER_OUT_LOW,ptm_timer_out[31:0] value from PCIe core. Valid in EP mode only" line.long 0x4 "CORE__USER_CFG__USER_CFG_ptm_timer_high,PTM timer value upper 32-bits" hexmask.long 0x4 0.--31. 1. "PTM_TIMER_OUT_HIGH,ptm_timer_out[63:32] value from PCIe core. Valid in EP mode only" rgroup.long 0xC8++0x3 line.long 0x0 "CORE__USER_CFG__USER_CFG_eoi_vector,EOI vector for re-triggering interrupts" hexmask.long.byte 0x0 0.--7. 1. "EOI_VECTOR,EOI vector for level interrupts. Writing the EOI value as specfied to this register will re-trigger a pending interrupt. 0 - Downstream interrupt 1 - FLR interrupt 2 - Legacy interrupt 3 - Power state interrupt" tree.end tree "PCIE1_CORE_VMAP_MMRS (PCIE1_CORE_VMAP_MMRS)" base ad:0x2914000 rgroup.long 0x200++0x3 line.long 0x0 "CORE__VMAP__MMRS_defmap,Inbound virtID default value register" bitfld.long 0x0 20. "ATS_DIS,ATS mode. 1-ATS is disabled 0-ATS is enabled" "0: ATS is enabled,1: ATS is disabled" bitfld.long 0x0 19. "BDF_MODE,Bus default mode. 0-Use default bus numbers 1-Use offset bus numbers" "0: Use default bus numbers,1: Use offset bus numbers" bitfld.long 0x0 16.--17. "DEF_ATYPE,Default address type attribute. 0-Physical Address 1-Intermediate Address 2-Virtual Address 3-Translated Address" "0: Physical Address,1: Intermediate Address,2: Virtual Address,3: Translated Address" newline hexmask.long.word 0x0 0.--11. 1. "DEF_VID,Default match ID" rgroup.long 0x400++0x3 line.long 0x0 "CORE__VMAP__MMRS_ob_virtid_match,Outbound virtid match register" hexmask.long.byte 0x0 5.--11. 1. "VAL,Outbound virtid[11:5] match value. When outbound VBUSM slave interface virtid[11:5] matches the value in this register and the ASEL value is non-zero the PCIe controller address translation unit (ATU) is bypassed. The PCIe TLP descriptor values are.." rgroup.long 0x0++0xB line.long 0x0 "CORE__VMAP__MMRS_ctrl,Control register" bitfld.long 0x0 0. "EN,ID enable" "0,1" line.long 0x4 "CORE__VMAP__MMRS_reqid,Inbound Requester ID mask and value register" hexmask.long.word 0x4 16.--31. 1. "MASK,RequesterID mask" hexmask.long.word 0x4 0.--15. 1. "RID,RequesterID" line.long 0x8 "CORE__VMAP__MMRS_virtid,Inbound Virt ID and Atype register" bitfld.long 0x8 16.--17. "ATYPE,Address type attribute. 0-Physical Address 1-Intermediate Address 2-Virtual Address 3-Translated Address" "0: Physical Address,1: Intermediate Address,2: Virtual Address,3: Translated Address" hexmask.long.word 0x8 0.--11. 1. "VID,Match ID" rgroup.long 0x300++0x3 line.long 0x0 "CORE__VMAP__MMRS_desc,Outbound ASEL non-zero descriptor register" bitfld.long 0x0 29.--31. "TRAFFIC_CLASS,PCIe Traffic Class (TC) associated with the non-zero ASEL request." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "BD_EN,External bus and device number enable. This bit enables the client to supply the bus and device numbers to be used in the requester ID. If this bit is 0 the core uses the captured values of the bus and device numbers to form the Requester ID. If.." "0,1" hexmask.long.byte 0x0 8.--15. 1. "BUS_NUM,PCI Bus Number associated with the request. When descriptor bit[16] is set this field must specify the bus number to be used for the Requester ID. Otherwise this field is ignored by the core." newline hexmask.long.byte 0x0 0.--7. 1. "DEV_FUNC_NUM,PCI Function and Device Number associated with the request. In ARI mode all 8 bits are used to indicate the requesting function number. In legacy mode only bits [3:0] are used to specify function number and bits [7:4] are used to specify.." tree.end tree.end tree "PCIE1_DAT0 (PCIE1_DAT0)" base ad:0x18000000 rgroup.long 0x0++0x3 line.long 0x0 "CORE__CORE_DAT_SLV__PCIE_DAT0_pcie_data_mem,PCIE data region0" hexmask.long 0x0 0.--31. 1. "PCIE_DATA,PCIE data region0" tree.end tree "PCIE1_DAT1 (PCIE1_DAT1)" base ad:0x4100000000 rgroup.long 0x0++0x3 line.long 0x0 "CORE__CORE_DAT_SLV__PCIE_DAT1_pcie_data_mem,PCIE data region1" hexmask.long 0x0 0.--31. 1. "PCIE_DATA,PCIE data region1" tree.end tree.end tree "PDMA" base ad:0x0 tree "PDMA5_REGS (PDMA5_REGS)" base ad:0x27E0000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 3. "RPCF1_RAMECC_PEND,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1" bitfld.long 0x4 2. "RPCF0_RAMECC_PEND,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1" bitfld.long 0x4 1. "TPCF1_RAMECC_PEND,Interrupt Pending Status for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "TPCF0_RAMECC_PEND,Interrupt Pending Status for tpcf0_ramecc_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf0_ramecc_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf0_ramecc_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 3. "RPCF1_RAMECC_PEND,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1" bitfld.long 0x4 2. "RPCF0_RAMECC_PEND,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1" bitfld.long 0x4 1. "TPCF1_RAMECC_PEND,Interrupt Pending Status for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "TPCF0_RAMECC_PEND,Interrupt Pending Status for tpcf0_ramecc_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf0_ramecc_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf0_ramecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "PDMA6_REGS (PDMA6_REGS)" base ad:0x27E1000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 3. "RPCF1_RAMECC_PEND,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1" bitfld.long 0x4 2. "RPCF0_RAMECC_PEND,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1" bitfld.long 0x4 1. "TPCF1_RAMECC_PEND,Interrupt Pending Status for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "TPCF0_RAMECC_PEND,Interrupt Pending Status for tpcf0_ramecc_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf0_ramecc_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf0_ramecc_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 3. "RPCF1_RAMECC_PEND,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1" bitfld.long 0x4 2. "RPCF0_RAMECC_PEND,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1" bitfld.long 0x4 1. "TPCF1_RAMECC_PEND,Interrupt Pending Status for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "TPCF0_RAMECC_PEND,Interrupt Pending Status for tpcf0_ramecc_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf0_ramecc_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf0_ramecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "PDMA7_REGS (PDMA7_REGS)" base ad:0x27E2000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 3. "RPCF1_RAMECC_PEND,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1" bitfld.long 0x4 2. "RPCF0_RAMECC_PEND,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1" bitfld.long 0x4 1. "TPCF1_RAMECC_PEND,Interrupt Pending Status for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "TPCF0_RAMECC_PEND,Interrupt Pending Status for tpcf0_ramecc_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf0_ramecc_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf0_ramecc_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 3. "RPCF1_RAMECC_PEND,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1" bitfld.long 0x4 2. "RPCF0_RAMECC_PEND,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1" bitfld.long 0x4 1. "TPCF1_RAMECC_PEND,Interrupt Pending Status for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "TPCF0_RAMECC_PEND,Interrupt Pending Status for tpcf0_ramecc_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf0_ramecc_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf0_ramecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree.end tree "PLL0_CFG (PLL0_CFG)" base ad:0x680000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_pll0_PID," bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" newline hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x8++0x3 line.long 0x0 "CFG_pll0_CFG," hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" newline bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0: SSM is not present 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0: SSM Wave table is not present 1'b1,?" newline bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0: Fractional PLL 2'b01,?,2: De-Skew PLL,?" rgroup.long 0x10++0x7 line.long 0x0 "CFG_pll0_LOCKKEY0," hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers" newline rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll0_LOCKKEY1," hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers" rgroup.long 0x20++0x3 line.long 0x0 "CFG_pll0_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0: Synchronously select PLL and associated HSDIV..,?" newline bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0: Do not automatically switch to ref clock source..,?" newline bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0: PLL is disabled 1'b1,?" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0: Output clocks are derived from the VCO clock 1'b1,?" newline bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0: Post divide powered down,?" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0: Delta-Sigma modulator is disabled,1: Delta-Sigma modulator is enabled" newline bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0: Fractional NC DAC is disabled,1: Fractional NC DAC is enabled" rgroup.long 0x24++0x3 line.long 0x0 "CFG_pll0_STAT," bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0: PLL is not locked 1'b1,?" rgroup.long 0x30++0xB line.long 0x0 "CFG_pll0_FREQ_CTRL0," hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll0_FREQ_CTRL1," hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll0_DIV_CTRL," bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0: Reserved,1: Divide by 1 3'b010,?,3: Divide by 3 3'b100,?,5: Divide by 5 3'b110,?,7: Divide by 7" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" rgroup.long 0x40++0x7 line.long 0x0 "CFG_pll0_SS_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0: Spread spectrum modulation is enabled 1'b1,?" newline hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" newline bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" newline bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0: Center spread 1'b1,?" newline bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0: Use 128 point triangle wave table 1'b1,?" line.long 0x4 "CFG_pll0_SS_SPREAD," hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" newline hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" rgroup.long 0x60++0x3 line.long 0x0 "CFG_pll0_CAL_CTRL," bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0: Normal operation 1'b1,?" newline bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0: Use the calibration output to set the phase..,?" newline hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x64++0x3 line.long 0x0 "CFG_pll0_CAL_STAT," bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" newline hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" rgroup.long 0x80++0x23 line.long 0x0 "CFG_pll0_HSDIV_CTRL0," bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "CFG_pll0_HSDIV_CTRL1," bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x8 "CFG_pll0_HSDIV_CTRL2," bitfld.long 0x8 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0xC "CFG_pll0_HSDIV_CTRL3," bitfld.long 0xC 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0xC 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0xC 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0xC 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x10 "CFG_pll0_HSDIV_CTRL4," bitfld.long 0x10 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x14 "CFG_pll0_HSDIV_CTRL5," bitfld.long 0x14 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x14 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x14 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x14 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x18 "CFG_pll0_HSDIV_CTRL6," bitfld.long 0x18 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x18 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x18 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x18 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x1C "CFG_pll0_HSDIV_CTRL7," bitfld.long 0x1C 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x1C 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x1C 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x1C 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x20 "CFG_pll0_HSDIV_CTRL8," bitfld.long 0x20 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x20 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x20 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x20 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x1000++0x3 line.long 0x0 "CFG_pll1_PID," bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" newline hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x1008++0x3 line.long 0x0 "CFG_pll1_CFG," hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" newline bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0: SSM is not present 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0: SSM Wave table is not present 1'b1,?" newline bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0: Fractional PLL 2'b01,?,2: De-Skew PLL,?" rgroup.long 0x1010++0x7 line.long 0x0 "CFG_pll1_LOCKKEY0," hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers" newline rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll1_LOCKKEY1," hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition1 registers" rgroup.long 0x1020++0x3 line.long 0x0 "CFG_pll1_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0: Synchronously select PLL and associated HSDIV..,?" newline bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0: Do not automatically switch to ref clock source..,?" newline bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0: PLL is disabled 1'b1,?" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0: Output clocks are derived from the VCO clock 1'b1,?" newline bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0: Post divide powered down,?" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0: Delta-Sigma modulator is disabled,1: Delta-Sigma modulator is enabled" newline bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0: Fractional NC DAC is disabled,1: Fractional NC DAC is enabled" rgroup.long 0x1024++0x3 line.long 0x0 "CFG_pll1_STAT," bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0: PLL is not locked 1'b1,?" rgroup.long 0x1030++0xB line.long 0x0 "CFG_pll1_FREQ_CTRL0," hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll1_FREQ_CTRL1," hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll1_DIV_CTRL," bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0: Reserved,1: Divide by 1 3'b010,?,3: Divide by 3 3'b100,?,5: Divide by 5 3'b110,?,7: Divide by 7" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" rgroup.long 0x1040++0x7 line.long 0x0 "CFG_pll1_SS_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0: Spread spectrum modulation is enabled 1'b1,?" newline hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" newline bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" newline bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0: Center spread 1'b1,?" newline bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0: Use 128 point triangle wave table 1'b1,?" line.long 0x4 "CFG_pll1_SS_SPREAD," hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" newline hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" rgroup.long 0x1060++0x3 line.long 0x0 "CFG_pll1_CAL_CTRL," bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0: Normal operation 1'b1,?" newline bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0: Use the calibration output to set the phase..,?" newline hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x1064++0x3 line.long 0x0 "CFG_pll1_CAL_STAT," bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" newline hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" rgroup.long 0x1080++0x23 line.long 0x0 "CFG_pll1_HSDIV_CTRL0," bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "CFG_pll1_HSDIV_CTRL1," bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x8 "CFG_pll1_HSDIV_CTRL2," bitfld.long 0x8 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0xC "CFG_pll1_HSDIV_CTRL3," bitfld.long 0xC 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0xC 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0xC 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0xC 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x10 "CFG_pll1_HSDIV_CTRL4," bitfld.long 0x10 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x14 "CFG_pll1_HSDIV_CTRL5," bitfld.long 0x14 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x14 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x14 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x14 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x18 "CFG_pll1_HSDIV_CTRL6," bitfld.long 0x18 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x18 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x18 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x18 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x1C "CFG_pll1_HSDIV_CTRL7," bitfld.long 0x1C 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x1C 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x1C 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x1C 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x20 "CFG_pll1_HSDIV_CTRL8," bitfld.long 0x20 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x20 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x20 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x20 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x2000++0x3 line.long 0x0 "CFG_pll2_PID," bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" newline hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x2008++0x3 line.long 0x0 "CFG_pll2_CFG," hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" newline bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0: SSM is not present 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0: SSM Wave table is not present 1'b1,?" newline bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0: Fractional PLL 2'b01,?,2: De-Skew PLL,?" rgroup.long 0x2010++0x7 line.long 0x0 "CFG_pll2_LOCKKEY0," hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers" newline rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll2_LOCKKEY1," hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition2 registers" rgroup.long 0x2020++0x3 line.long 0x0 "CFG_pll2_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0: Synchronously select PLL and associated HSDIV..,?" newline bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0: Do not automatically switch to ref clock source..,?" newline bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0: PLL is disabled 1'b1,?" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0: Output clocks are derived from the VCO clock 1'b1,?" newline bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0: Post divide powered down,?" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0: Delta-Sigma modulator is disabled,1: Delta-Sigma modulator is enabled" newline bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0: Fractional NC DAC is disabled,1: Fractional NC DAC is enabled" rgroup.long 0x2024++0x3 line.long 0x0 "CFG_pll2_STAT," bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0: PLL is not locked 1'b1,?" rgroup.long 0x2030++0xB line.long 0x0 "CFG_pll2_FREQ_CTRL0," hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll2_FREQ_CTRL1," hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll2_DIV_CTRL," bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0: Reserved,1: Divide by 1 3'b010,?,3: Divide by 3 3'b100,?,5: Divide by 5 3'b110,?,7: Divide by 7" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" rgroup.long 0x2040++0x7 line.long 0x0 "CFG_pll2_SS_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0: Spread spectrum modulation is enabled 1'b1,?" newline hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" newline bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" newline bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0: Center spread 1'b1,?" newline bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0: Use 128 point triangle wave table 1'b1,?" line.long 0x4 "CFG_pll2_SS_SPREAD," hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" newline hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" rgroup.long 0x2060++0x3 line.long 0x0 "CFG_pll2_CAL_CTRL," bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0: Normal operation 1'b1,?" newline bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0: Use the calibration output to set the phase..,?" newline hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x2064++0x3 line.long 0x0 "CFG_pll2_CAL_STAT," bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" newline hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" rgroup.long 0x2080++0x1F line.long 0x0 "CFG_pll2_HSDIV_CTRL0," bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "CFG_pll2_HSDIV_CTRL1," bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x8 "CFG_pll2_HSDIV_CTRL2," bitfld.long 0x8 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0xC "CFG_pll2_HSDIV_CTRL3," bitfld.long 0xC 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0xC 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0xC 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0xC 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x10 "CFG_pll2_HSDIV_CTRL4," bitfld.long 0x10 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x14 "CFG_pll2_HSDIV_CTRL5," bitfld.long 0x14 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x14 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x14 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x14 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x18 "CFG_pll2_HSDIV_CTRL6," bitfld.long 0x18 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x18 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x18 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x18 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x1C "CFG_pll2_HSDIV_CTRL7," bitfld.long 0x1C 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x1C 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x1C 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x1C 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x3000++0x3 line.long 0x0 "CFG_pll3_PID," bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" newline hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x3008++0x3 line.long 0x0 "CFG_pll3_CFG," hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" newline bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0: SSM is not present 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0: SSM Wave table is not present 1'b1,?" newline bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0: Fractional PLL 2'b01,?,2: De-Skew PLL,?" rgroup.long 0x3010++0x7 line.long 0x0 "CFG_pll3_LOCKKEY0," hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition3 registers" newline rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll3_LOCKKEY1," hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition3 registers" rgroup.long 0x3020++0x3 line.long 0x0 "CFG_pll3_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0: Synchronously select PLL and associated HSDIV..,?" newline bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0: Do not automatically switch to ref clock source..,?" newline bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0: PLL is disabled 1'b1,?" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0: Output clocks are derived from the VCO clock 1'b1,?" newline bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0: Post divide powered down,?" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0: Delta-Sigma modulator is disabled,1: Delta-Sigma modulator is enabled" newline bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0: Fractional NC DAC is disabled,1: Fractional NC DAC is enabled" rgroup.long 0x3024++0x3 line.long 0x0 "CFG_pll3_STAT," bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0: PLL is not locked 1'b1,?" rgroup.long 0x3030++0xB line.long 0x0 "CFG_pll3_FREQ_CTRL0," hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll3_FREQ_CTRL1," hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll3_DIV_CTRL," bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0: Reserved,1: Divide by 1 3'b010,?,3: Divide by 3 3'b100,?,5: Divide by 5 3'b110,?,7: Divide by 7" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" rgroup.long 0x3040++0x7 line.long 0x0 "CFG_pll3_SS_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0: Spread spectrum modulation is enabled 1'b1,?" newline hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" newline bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" newline bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0: Center spread 1'b1,?" newline bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0: Use 128 point triangle wave table 1'b1,?" line.long 0x4 "CFG_pll3_SS_SPREAD," hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" newline hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" rgroup.long 0x3060++0x3 line.long 0x0 "CFG_pll3_CAL_CTRL," bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0: Normal operation 1'b1,?" newline bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0: Use the calibration output to set the phase..,?" newline hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x3064++0x3 line.long 0x0 "CFG_pll3_CAL_STAT," bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" newline hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" rgroup.long 0x3080++0x13 line.long 0x0 "CFG_pll3_HSDIV_CTRL0," bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "CFG_pll3_HSDIV_CTRL1," bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x8 "CFG_pll3_HSDIV_CTRL2," bitfld.long 0x8 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0xC "CFG_pll3_HSDIV_CTRL3," bitfld.long 0xC 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0xC 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0xC 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0xC 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x10 "CFG_pll3_HSDIV_CTRL4," bitfld.long 0x10 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x4000++0x3 line.long 0x0 "CFG_pll4_PID," bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" newline hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x4008++0x3 line.long 0x0 "CFG_pll4_CFG," hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" newline bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0: SSM is not present 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0: SSM Wave table is not present 1'b1,?" newline bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0: Fractional PLL 2'b01,?,2: De-Skew PLL,?" rgroup.long 0x4010++0x7 line.long 0x0 "CFG_pll4_LOCKKEY0," hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition4 registers" newline rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll4_LOCKKEY1," hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition4 registers" rgroup.long 0x4020++0x3 line.long 0x0 "CFG_pll4_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0: Synchronously select PLL and associated HSDIV..,?" newline bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0: Do not automatically switch to ref clock source..,?" newline bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0: PLL is disabled 1'b1,?" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0: Output clocks are derived from the VCO clock 1'b1,?" newline bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0: Post divide powered down,?" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0: Delta-Sigma modulator is disabled,1: Delta-Sigma modulator is enabled" newline bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0: Fractional NC DAC is disabled,1: Fractional NC DAC is enabled" rgroup.long 0x4024++0x3 line.long 0x0 "CFG_pll4_STAT," bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0: PLL is not locked 1'b1,?" rgroup.long 0x4030++0xB line.long 0x0 "CFG_pll4_FREQ_CTRL0," hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll4_FREQ_CTRL1," hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll4_DIV_CTRL," bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0: Reserved,1: Divide by 1 3'b010,?,3: Divide by 3 3'b100,?,5: Divide by 5 3'b110,?,7: Divide by 7" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" rgroup.long 0x4040++0x7 line.long 0x0 "CFG_pll4_SS_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0: Spread spectrum modulation is enabled 1'b1,?" newline hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" newline bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" newline bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0: Center spread 1'b1,?" newline bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0: Use 128 point triangle wave table 1'b1,?" line.long 0x4 "CFG_pll4_SS_SPREAD," hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" newline hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" rgroup.long 0x4060++0x3 line.long 0x0 "CFG_pll4_CAL_CTRL," bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0: Normal operation 1'b1,?" newline bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0: Use the calibration output to set the phase..,?" newline hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x4064++0x3 line.long 0x0 "CFG_pll4_CAL_STAT," bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" newline hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" rgroup.long 0x4080++0xB line.long 0x0 "CFG_pll4_HSDIV_CTRL0," bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "CFG_pll4_HSDIV_CTRL1," bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x8 "CFG_pll4_HSDIV_CTRL2," bitfld.long 0x8 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x5000++0x3 line.long 0x0 "CFG_pll5_PID," bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" newline hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x5008++0x3 line.long 0x0 "CFG_pll5_CFG," hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" newline bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0: SSM is not present 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0: SSM Wave table is not present 1'b1,?" newline bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0: Fractional PLL 2'b01,?,2: De-Skew PLL,?" rgroup.long 0x5010++0x7 line.long 0x0 "CFG_pll5_LOCKKEY0," hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition5 registers" newline rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll5_LOCKKEY1," hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition5 registers" rgroup.long 0x5020++0x3 line.long 0x0 "CFG_pll5_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0: Synchronously select PLL and associated HSDIV..,?" newline bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0: Do not automatically switch to ref clock source..,?" newline bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0: PLL is disabled 1'b1,?" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0: Output clocks are derived from the VCO clock 1'b1,?" newline bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0: Post divide powered down,?" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0: Delta-Sigma modulator is disabled,1: Delta-Sigma modulator is enabled" newline bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0: Fractional NC DAC is disabled,1: Fractional NC DAC is enabled" rgroup.long 0x5024++0x3 line.long 0x0 "CFG_pll5_STAT," bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0: PLL is not locked 1'b1,?" rgroup.long 0x5030++0xB line.long 0x0 "CFG_pll5_FREQ_CTRL0," hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll5_FREQ_CTRL1," hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll5_DIV_CTRL," bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0: Reserved,1: Divide by 1 3'b010,?,3: Divide by 3 3'b100,?,5: Divide by 5 3'b110,?,7: Divide by 7" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" rgroup.long 0x5040++0x7 line.long 0x0 "CFG_pll5_SS_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0: Spread spectrum modulation is enabled 1'b1,?" newline hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" newline bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" newline bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0: Center spread 1'b1,?" newline bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0: Use 128 point triangle wave table 1'b1,?" line.long 0x4 "CFG_pll5_SS_SPREAD," hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" newline hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" rgroup.long 0x5060++0x3 line.long 0x0 "CFG_pll5_CAL_CTRL," bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0: Normal operation 1'b1,?" newline bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0: Use the calibration output to set the phase..,?" newline hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x5064++0x3 line.long 0x0 "CFG_pll5_CAL_STAT," bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" newline hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" rgroup.long 0x5080++0x7 line.long 0x0 "CFG_pll5_HSDIV_CTRL0," bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "CFG_pll5_HSDIV_CTRL1," bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x6000++0x3 line.long 0x0 "CFG_pll6_PID," bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" newline hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x6008++0x3 line.long 0x0 "CFG_pll6_CFG," hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" newline bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0: SSM is not present 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0: SSM Wave table is not present 1'b1,?" newline bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0: Fractional PLL 2'b01,?,2: De-Skew PLL,?" rgroup.long 0x6010++0x7 line.long 0x0 "CFG_pll6_LOCKKEY0," hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition6 registers" newline rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll6_LOCKKEY1," hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition6 registers" rgroup.long 0x6020++0x3 line.long 0x0 "CFG_pll6_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0: Synchronously select PLL and associated HSDIV..,?" newline bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0: Do not automatically switch to ref clock source..,?" newline bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0: PLL is disabled 1'b1,?" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0: Output clocks are derived from the VCO clock 1'b1,?" newline bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0: Post divide powered down,?" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0: Delta-Sigma modulator is disabled,1: Delta-Sigma modulator is enabled" newline bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0: Fractional NC DAC is disabled,1: Fractional NC DAC is enabled" rgroup.long 0x6024++0x3 line.long 0x0 "CFG_pll6_STAT," bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0: PLL is not locked 1'b1,?" rgroup.long 0x6030++0xB line.long 0x0 "CFG_pll6_FREQ_CTRL0," hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll6_FREQ_CTRL1," hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll6_DIV_CTRL," bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0: Reserved,1: Divide by 1 3'b010,?,3: Divide by 3 3'b100,?,5: Divide by 5 3'b110,?,7: Divide by 7" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" rgroup.long 0x6040++0x7 line.long 0x0 "CFG_pll6_SS_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0: Spread spectrum modulation is enabled 1'b1,?" newline hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" newline bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" newline bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0: Center spread 1'b1,?" newline bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0: Use 128 point triangle wave table 1'b1,?" line.long 0x4 "CFG_pll6_SS_SPREAD," hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" newline hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" rgroup.long 0x6060++0x3 line.long 0x0 "CFG_pll6_CAL_CTRL," bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0: Normal operation 1'b1,?" newline bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0: Use the calibration output to set the phase..,?" newline hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x6064++0x3 line.long 0x0 "CFG_pll6_CAL_STAT," bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" newline hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" rgroup.long 0x6080++0x3 line.long 0x0 "CFG_pll6_HSDIV_CTRL0," bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x7000++0x3 line.long 0x0 "CFG_pll7_PID," bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" newline hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x7008++0x3 line.long 0x0 "CFG_pll7_CFG," hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" newline bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0: SSM is not present 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0: SSM Wave table is not present 1'b1,?" newline bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0: Fractional PLL 2'b01,?,2: De-Skew PLL,?" rgroup.long 0x7010++0x7 line.long 0x0 "CFG_pll7_LOCKKEY0," hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition7 registers" newline rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll7_LOCKKEY1," hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition7 registers" rgroup.long 0x7020++0x3 line.long 0x0 "CFG_pll7_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0: Synchronously select PLL and associated HSDIV..,?" newline bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0: Do not automatically switch to ref clock source..,?" newline bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0: PLL is disabled 1'b1,?" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0: Output clocks are derived from the VCO clock 1'b1,?" newline bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0: Post divide powered down,?" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0: Delta-Sigma modulator is disabled,1: Delta-Sigma modulator is enabled" newline bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0: Fractional NC DAC is disabled,1: Fractional NC DAC is enabled" rgroup.long 0x7024++0x3 line.long 0x0 "CFG_pll7_STAT," bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0: PLL is not locked 1'b1,?" rgroup.long 0x7030++0xB line.long 0x0 "CFG_pll7_FREQ_CTRL0," hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll7_FREQ_CTRL1," hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll7_DIV_CTRL," bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0: Reserved,1: Divide by 1 3'b010,?,3: Divide by 3 3'b100,?,5: Divide by 5 3'b110,?,7: Divide by 7" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" rgroup.long 0x7040++0x7 line.long 0x0 "CFG_pll7_SS_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0: Spread spectrum modulation is enabled 1'b1,?" newline hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" newline bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" newline bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0: Center spread 1'b1,?" newline bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0: Use 128 point triangle wave table 1'b1,?" line.long 0x4 "CFG_pll7_SS_SPREAD," hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" newline hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" rgroup.long 0x7060++0x3 line.long 0x0 "CFG_pll7_CAL_CTRL," bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0: Normal operation 1'b1,?" newline bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0: Use the calibration output to set the phase..,?" newline hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x7064++0x3 line.long 0x0 "CFG_pll7_CAL_STAT," bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" newline hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" rgroup.long 0x7080++0x3 line.long 0x0 "CFG_pll7_HSDIV_CTRL0," bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x8000++0x3 line.long 0x0 "CFG_pll8_PID," bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" newline hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x8008++0x3 line.long 0x0 "CFG_pll8_CFG," hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" newline bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0: SSM is not present 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0: SSM Wave table is not present 1'b1,?" newline bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0: Fractional PLL 2'b01,?,2: De-Skew PLL,?" rgroup.long 0x8010++0x7 line.long 0x0 "CFG_pll8_LOCKKEY0," hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition8 registers" newline rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll8_LOCKKEY1," hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition8 registers" rgroup.long 0x8020++0x3 line.long 0x0 "CFG_pll8_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0: Synchronously select PLL and associated HSDIV..,?" newline bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0: Do not automatically switch to ref clock source..,?" newline bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0: PLL is disabled 1'b1,?" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0: Output clocks are derived from the VCO clock 1'b1,?" newline bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0: Post divide powered down,?" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0: Delta-Sigma modulator is disabled,1: Delta-Sigma modulator is enabled" newline bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0: Fractional NC DAC is disabled,1: Fractional NC DAC is enabled" rgroup.long 0x8024++0x3 line.long 0x0 "CFG_pll8_STAT," bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0: PLL is not locked 1'b1,?" rgroup.long 0x8030++0xB line.long 0x0 "CFG_pll8_FREQ_CTRL0," hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll8_FREQ_CTRL1," hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll8_DIV_CTRL," bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0: Reserved,1: Divide by 1 3'b010,?,3: Divide by 3 3'b100,?,5: Divide by 5 3'b110,?,7: Divide by 7" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" rgroup.long 0x8040++0x7 line.long 0x0 "CFG_pll8_SS_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0: Spread spectrum modulation is enabled 1'b1,?" newline hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" newline bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" newline bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0: Center spread 1'b1,?" newline bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0: Use 128 point triangle wave table 1'b1,?" line.long 0x4 "CFG_pll8_SS_SPREAD," hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" newline hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" rgroup.long 0x8060++0x3 line.long 0x0 "CFG_pll8_CAL_CTRL," bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0: Normal operation 1'b1,?" newline bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0: Use the calibration output to set the phase..,?" newline hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x8064++0x3 line.long 0x0 "CFG_pll8_CAL_STAT," bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" newline hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" rgroup.long 0x8080++0x3 line.long 0x0 "CFG_pll8_HSDIV_CTRL0," bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x9000++0x3 line.long 0x0 "CFG_pll9_PID," bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" newline hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x9008++0x3 line.long 0x0 "CFG_pll9_CFG," hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" newline bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0: SSM is not present 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0: SSM Wave table is not present 1'b1,?" newline bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0: Fractional PLL 2'b01,?,2: De-Skew PLL,?" rgroup.long 0x9010++0x7 line.long 0x0 "CFG_pll9_LOCKKEY0," hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition9 registers" newline rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll9_LOCKKEY1," hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition9 registers" rgroup.long 0x9020++0x3 line.long 0x0 "CFG_pll9_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0: Synchronously select PLL and associated HSDIV..,?" newline bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0: Do not automatically switch to ref clock source..,?" newline bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0: PLL is disabled 1'b1,?" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0: Output clocks are derived from the VCO clock 1'b1,?" newline bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0: Post divide powered down,?" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0: Delta-Sigma modulator is disabled,1: Delta-Sigma modulator is enabled" newline bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0: Fractional NC DAC is disabled,1: Fractional NC DAC is enabled" rgroup.long 0x9024++0x3 line.long 0x0 "CFG_pll9_STAT," bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0: PLL is not locked 1'b1,?" rgroup.long 0x9030++0xB line.long 0x0 "CFG_pll9_FREQ_CTRL0," hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll9_FREQ_CTRL1," hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll9_DIV_CTRL," bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0: Reserved,1: Divide by 1 3'b010,?,3: Divide by 3 3'b100,?,5: Divide by 5 3'b110,?,7: Divide by 7" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" rgroup.long 0x9040++0x7 line.long 0x0 "CFG_pll9_SS_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0: Spread spectrum modulation is enabled 1'b1,?" newline hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" newline bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" newline bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0: Center spread 1'b1,?" newline bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0: Use 128 point triangle wave table 1'b1,?" line.long 0x4 "CFG_pll9_SS_SPREAD," hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" newline hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" rgroup.long 0x9060++0x3 line.long 0x0 "CFG_pll9_CAL_CTRL," bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0: Normal operation 1'b1,?" newline bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0: Use the calibration output to set the phase..,?" newline hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x9064++0x3 line.long 0x0 "CFG_pll9_CAL_STAT," bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" newline hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" rgroup.long 0x9080++0x3 line.long 0x0 "CFG_pll9_HSDIV_CTRL0," bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0xC000++0x3 line.long 0x0 "CFG_pll12_PID," bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" newline hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0xC008++0x3 line.long 0x0 "CFG_pll12_CFG," hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" newline bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0: SSM is not present 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0: SSM Wave table is not present 1'b1,?" newline bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0: Fractional PLL 2'b01,?,2: De-Skew PLL,?" rgroup.long 0xC010++0x7 line.long 0x0 "CFG_pll12_LOCKKEY0," hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition12 registers" newline rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll12_LOCKKEY1," hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition12 registers" rgroup.long 0xC020++0x3 line.long 0x0 "CFG_pll12_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0: Synchronously select PLL and associated HSDIV..,?" newline bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0: Do not automatically switch to ref clock source..,?" newline bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0: PLL is disabled 1'b1,?" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0: Output clocks are derived from the VCO clock 1'b1,?" newline bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0: Post divide powered down,?" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0: Delta-Sigma modulator is disabled,1: Delta-Sigma modulator is enabled" newline bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0: Fractional NC DAC is disabled,1: Fractional NC DAC is enabled" rgroup.long 0xC024++0x3 line.long 0x0 "CFG_pll12_STAT," bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0: PLL is not locked 1'b1,?" rgroup.long 0xC030++0xB line.long 0x0 "CFG_pll12_FREQ_CTRL0," hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll12_FREQ_CTRL1," hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll12_DIV_CTRL," bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0: Reserved,1: Divide by 1 3'b010,?,3: Divide by 3 3'b100,?,5: Divide by 5 3'b110,?,7: Divide by 7" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" rgroup.long 0xC040++0x7 line.long 0x0 "CFG_pll12_SS_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0: Spread spectrum modulation is enabled 1'b1,?" newline hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" newline bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" newline bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0: Center spread 1'b1,?" newline bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0: Use 128 point triangle wave table 1'b1,?" line.long 0x4 "CFG_pll12_SS_SPREAD," hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" newline hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" rgroup.long 0xC060++0x3 line.long 0x0 "CFG_pll12_CAL_CTRL," bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0: Normal operation 1'b1,?" newline bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0: Use the calibration output to set the phase..,?" newline hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0xC064++0x3 line.long 0x0 "CFG_pll12_CAL_STAT," bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" newline hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" rgroup.long 0xC080++0x3 line.long 0x0 "CFG_pll12_HSDIV_CTRL0," bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0xE000++0x3 line.long 0x0 "CFG_pll14_PID," bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" newline hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0xE008++0x3 line.long 0x0 "CFG_pll14_CFG," hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" newline bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0: SSM is not present 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0: SSM Wave table is not present 1'b1,?" newline bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0: Fractional PLL 2'b01,?,2: De-Skew PLL,?" rgroup.long 0xE010++0x7 line.long 0x0 "CFG_pll14_LOCKKEY0," hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition14 registers" newline rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll14_LOCKKEY1," hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition14 registers" rgroup.long 0xE020++0x3 line.long 0x0 "CFG_pll14_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0: Synchronously select PLL and associated HSDIV..,?" newline bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0: Do not automatically switch to ref clock source..,?" newline bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0: PLL is disabled 1'b1,?" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0: Output clocks are derived from the VCO clock 1'b1,?" newline bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0: Post divide powered down,?" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0: Delta-Sigma modulator is disabled,1: Delta-Sigma modulator is enabled" newline bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0: Fractional NC DAC is disabled,1: Fractional NC DAC is enabled" rgroup.long 0xE024++0x3 line.long 0x0 "CFG_pll14_STAT," bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0: PLL is not locked 1'b1,?" rgroup.long 0xE030++0xB line.long 0x0 "CFG_pll14_FREQ_CTRL0," hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll14_FREQ_CTRL1," hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll14_DIV_CTRL," bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0: Reserved,1: Divide by 1 3'b010,?,3: Divide by 3 3'b100,?,5: Divide by 5 3'b110,?,7: Divide by 7" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" rgroup.long 0xE040++0x7 line.long 0x0 "CFG_pll14_SS_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0: Spread spectrum modulation is enabled 1'b1,?" newline hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" newline bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" newline bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0: Center spread 1'b1,?" newline bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0: Use 128 point triangle wave table 1'b1,?" line.long 0x4 "CFG_pll14_SS_SPREAD," hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" newline hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" rgroup.long 0xE060++0x3 line.long 0x0 "CFG_pll14_CAL_CTRL," bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0: Normal operation 1'b1,?" newline bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0: Use the calibration output to set the phase..,?" newline hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0xE064++0x3 line.long 0x0 "CFG_pll14_CAL_STAT," bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" newline hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" rgroup.long 0xE080++0xB line.long 0x0 "CFG_pll14_HSDIV_CTRL0," bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "CFG_pll14_HSDIV_CTRL1," bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x8 "CFG_pll14_HSDIV_CTRL2," bitfld.long 0x8 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x10000++0x3 line.long 0x0 "CFG_pll16_PID," bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" newline hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x10008++0x3 line.long 0x0 "CFG_pll16_CFG," hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" newline bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0: SSM is not present 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0: SSM Wave table is not present 1'b1,?" newline bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0: Fractional PLL 2'b01,?,2: De-Skew PLL,?" rgroup.long 0x10010++0x7 line.long 0x0 "CFG_pll16_LOCKKEY0," hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition16 registers" newline rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll16_LOCKKEY1," hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition16 registers" rgroup.long 0x10020++0x3 line.long 0x0 "CFG_pll16_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0: Synchronously select PLL and associated HSDIV..,?" newline bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0: Do not automatically switch to ref clock source..,?" newline bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0: PLL is disabled 1'b1,?" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0: Output clocks are derived from the VCO clock 1'b1,?" newline bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0: Post divide powered down,?" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0: Delta-Sigma modulator is disabled,1: Delta-Sigma modulator is enabled" newline bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0: Fractional NC DAC is disabled,1: Fractional NC DAC is enabled" rgroup.long 0x10024++0x3 line.long 0x0 "CFG_pll16_STAT," bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0: PLL is not locked 1'b1,?" rgroup.long 0x10030++0xB line.long 0x0 "CFG_pll16_FREQ_CTRL0," hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll16_FREQ_CTRL1," hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll16_DIV_CTRL," bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0: Reserved,1: Divide by 1 3'b010,?,3: Divide by 3 3'b100,?,5: Divide by 5 3'b110,?,7: Divide by 7" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" rgroup.long 0x10040++0x7 line.long 0x0 "CFG_pll16_SS_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0: Spread spectrum modulation is enabled 1'b1,?" newline hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" newline bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" newline bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0: Center spread 1'b1,?" newline bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0: Use 128 point triangle wave table 1'b1,?" line.long 0x4 "CFG_pll16_SS_SPREAD," hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" newline hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" rgroup.long 0x10060++0x3 line.long 0x0 "CFG_pll16_CAL_CTRL," bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0: Normal operation 1'b1,?" newline bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0: Use the calibration output to set the phase..,?" newline hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x10064++0x3 line.long 0x0 "CFG_pll16_CAL_STAT," bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" newline hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" rgroup.long 0x10080++0x7 line.long 0x0 "CFG_pll16_HSDIV_CTRL0," bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "CFG_pll16_HSDIV_CTRL1," bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x11000++0x3 line.long 0x0 "CFG_pll17_PID," bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" newline hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x11008++0x3 line.long 0x0 "CFG_pll17_CFG," hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" newline bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0: SSM is not present 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0: SSM Wave table is not present 1'b1,?" newline bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0: Fractional PLL 2'b01,?,2: De-Skew PLL,?" rgroup.long 0x11010++0x7 line.long 0x0 "CFG_pll17_LOCKKEY0," hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition17 registers" newline rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll17_LOCKKEY1," hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition17 registers" rgroup.long 0x11020++0x3 line.long 0x0 "CFG_pll17_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0: Synchronously select PLL and associated HSDIV..,?" newline bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0: Do not automatically switch to ref clock source..,?" newline bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0: PLL is disabled 1'b1,?" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0: Output clocks are derived from the VCO clock 1'b1,?" newline bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0: Post divide powered down,?" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0: Delta-Sigma modulator is disabled,1: Delta-Sigma modulator is enabled" newline bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0: Fractional NC DAC is disabled,1: Fractional NC DAC is enabled" rgroup.long 0x11024++0x3 line.long 0x0 "CFG_pll17_STAT," bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0: PLL is not locked 1'b1,?" rgroup.long 0x11030++0xB line.long 0x0 "CFG_pll17_FREQ_CTRL0," hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll17_FREQ_CTRL1," hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll17_DIV_CTRL," bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0: Reserved,1: Divide by 1 3'b010,?,3: Divide by 3 3'b100,?,5: Divide by 5 3'b110,?,7: Divide by 7" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" rgroup.long 0x11040++0x7 line.long 0x0 "CFG_pll17_SS_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0: Spread spectrum modulation is enabled 1'b1,?" newline hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" newline bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" newline bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0: Center spread 1'b1,?" newline bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0: Use 128 point triangle wave table 1'b1,?" line.long 0x4 "CFG_pll17_SS_SPREAD," hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" newline hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" rgroup.long 0x11060++0x3 line.long 0x0 "CFG_pll17_CAL_CTRL," bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0: Normal operation 1'b1,?" newline bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0: Use the calibration output to set the phase..,?" newline hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x11064++0x3 line.long 0x0 "CFG_pll17_CAL_STAT," bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" newline hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" rgroup.long 0x11080++0x7 line.long 0x0 "CFG_pll17_HSDIV_CTRL0," bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "CFG_pll17_HSDIV_CTRL1," bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x13000++0x3 line.long 0x0 "CFG_pll19_PID," bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" newline hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x13008++0x3 line.long 0x0 "CFG_pll19_CFG," hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" newline bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0: SSM is not present 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0: SSM Wave table is not present 1'b1,?" newline bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0: Fractional PLL 2'b01,?,2: De-Skew PLL,?" rgroup.long 0x13010++0x7 line.long 0x0 "CFG_pll19_LOCKKEY0," hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition19 registers" newline rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll19_LOCKKEY1," hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition19 registers" rgroup.long 0x13020++0x3 line.long 0x0 "CFG_pll19_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0: Synchronously select PLL and associated HSDIV..,?" newline bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0: Do not automatically switch to ref clock source..,?" newline bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0: PLL is disabled 1'b1,?" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0: Output clocks are derived from the VCO clock 1'b1,?" newline bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0: Post divide powered down,?" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0: Delta-Sigma modulator is disabled,1: Delta-Sigma modulator is enabled" newline bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0: Fractional NC DAC is disabled,1: Fractional NC DAC is enabled" rgroup.long 0x13024++0x3 line.long 0x0 "CFG_pll19_STAT," bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0: PLL is not locked 1'b1,?" rgroup.long 0x13030++0xB line.long 0x0 "CFG_pll19_FREQ_CTRL0," hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll19_FREQ_CTRL1," hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll19_DIV_CTRL," bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0: Reserved,1: Divide by 1 3'b010,?,3: Divide by 3 3'b100,?,5: Divide by 5 3'b110,?,7: Divide by 7" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" rgroup.long 0x13040++0x7 line.long 0x0 "CFG_pll19_SS_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0: Spread spectrum modulation is enabled 1'b1,?" newline hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" newline bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" newline bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0: Center spread 1'b1,?" newline bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0: Use 128 point triangle wave table 1'b1,?" line.long 0x4 "CFG_pll19_SS_SPREAD," hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" newline hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" rgroup.long 0x13060++0x3 line.long 0x0 "CFG_pll19_CAL_CTRL," bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0: Normal operation 1'b1,?" newline bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0: Use the calibration output to set the phase..,?" newline hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x13064++0x3 line.long 0x0 "CFG_pll19_CAL_STAT," bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" newline hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" rgroup.long 0x13080++0x7 line.long 0x0 "CFG_pll19_HSDIV_CTRL0," bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "CFG_pll19_HSDIV_CTRL1," bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x19000++0x3 line.long 0x0 "CFG_pll25_PID," bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" newline hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x19008++0x3 line.long 0x0 "CFG_pll25_CFG," hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" newline bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0: SSM is not present 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0: SSM Wave table is not present 1'b1,?" newline bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0: Fractional PLL 2'b01,?,2: De-Skew PLL,?" rgroup.long 0x19010++0x7 line.long 0x0 "CFG_pll25_LOCKKEY0," hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition25 registers" newline rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll25_LOCKKEY1," hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition25 registers" rgroup.long 0x19020++0x3 line.long 0x0 "CFG_pll25_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0: Synchronously select PLL and associated HSDIV..,?" newline bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0: Do not automatically switch to ref clock source..,?" newline bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0: PLL is disabled 1'b1,?" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0: Output clocks are derived from the VCO clock 1'b1,?" newline bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0: Post divide powered down,?" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0: Delta-Sigma modulator is disabled,1: Delta-Sigma modulator is enabled" newline bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0: Fractional NC DAC is disabled,1: Fractional NC DAC is enabled" rgroup.long 0x19024++0x3 line.long 0x0 "CFG_pll25_STAT," bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0: PLL is not locked 1'b1,?" rgroup.long 0x19030++0xB line.long 0x0 "CFG_pll25_FREQ_CTRL0," hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll25_FREQ_CTRL1," hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll25_DIV_CTRL," bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0: Reserved,1: Divide by 1 3'b010,?,3: Divide by 3 3'b100,?,5: Divide by 5 3'b110,?,7: Divide by 7" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" rgroup.long 0x19040++0x7 line.long 0x0 "CFG_pll25_SS_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0: Spread spectrum modulation is enabled 1'b1,?" newline hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" newline bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" newline bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0: Center spread 1'b1,?" newline bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0: Use 128 point triangle wave table 1'b1,?" line.long 0x4 "CFG_pll25_SS_SPREAD," hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" newline hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" rgroup.long 0x19060++0x3 line.long 0x0 "CFG_pll25_CAL_CTRL," bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0: Normal operation 1'b1,?" newline bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0: Use the calibration output to set the phase..,?" newline hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x19064++0x3 line.long 0x0 "CFG_pll25_CAL_STAT," bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" newline hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" rgroup.long 0x19080++0x7 line.long 0x0 "CFG_pll25_HSDIV_CTRL0," bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "CFG_pll25_HSDIV_CTRL1," bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x1A000++0x3 line.long 0x0 "CFG_pll26_PID," bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" newline hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x1A008++0x3 line.long 0x0 "CFG_pll26_CFG," hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" newline bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0: SSM is not present 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0: SSM Wave table is not present 1'b1,?" newline bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0: Fractional PLL 2'b01,?,2: De-Skew PLL,?" rgroup.long 0x1A010++0x7 line.long 0x0 "CFG_pll26_LOCKKEY0," hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition26 registers" newline rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll26_LOCKKEY1," hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition26 registers" rgroup.long 0x1A020++0x3 line.long 0x0 "CFG_pll26_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0: Synchronously select PLL and associated HSDIV..,?" newline bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0: Do not automatically switch to ref clock source..,?" newline bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0: PLL is disabled 1'b1,?" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0: Output clocks are derived from the VCO clock 1'b1,?" newline bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0: Post divide powered down,?" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0: Delta-Sigma modulator is disabled,1: Delta-Sigma modulator is enabled" newline bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0: Fractional NC DAC is disabled,1: Fractional NC DAC is enabled" rgroup.long 0x1A024++0x3 line.long 0x0 "CFG_pll26_STAT," bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0: PLL is not locked 1'b1,?" rgroup.long 0x1A030++0xB line.long 0x0 "CFG_pll26_FREQ_CTRL0," hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll26_FREQ_CTRL1," hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll26_DIV_CTRL," bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0: Reserved,1: Divide by 1 3'b010,?,3: Divide by 3 3'b100,?,5: Divide by 5 3'b110,?,7: Divide by 7" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" rgroup.long 0x1A040++0x7 line.long 0x0 "CFG_pll26_SS_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0: Spread spectrum modulation is enabled 1'b1,?" newline hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" newline bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" newline bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0: Center spread 1'b1,?" newline bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0: Use 128 point triangle wave table 1'b1,?" line.long 0x4 "CFG_pll26_SS_SPREAD," hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" newline hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" rgroup.long 0x1A060++0x3 line.long 0x0 "CFG_pll26_CAL_CTRL," bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0: Normal operation 1'b1,?" newline bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0: Use the calibration output to set the phase..,?" newline hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x1A064++0x3 line.long 0x0 "CFG_pll26_CAL_STAT," bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" newline hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" rgroup.long 0x1A080++0x3 line.long 0x0 "CFG_pll26_HSDIV_CTRL0," bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x1B000++0x3 line.long 0x0 "CFG_pll27_PID," bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" newline hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x1B008++0x3 line.long 0x0 "CFG_pll27_CFG," hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" newline bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0: SSM is not present 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0: SSM Wave table is not present 1'b1,?" newline bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0: Fractional PLL 2'b01,?,2: De-Skew PLL,?" rgroup.long 0x1B010++0x7 line.long 0x0 "CFG_pll27_LOCKKEY0," hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition27 registers" newline rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll27_LOCKKEY1," hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition27 registers" rgroup.long 0x1B020++0x3 line.long 0x0 "CFG_pll27_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0: Synchronously select PLL and associated HSDIV..,?" newline bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0: Do not automatically switch to ref clock source..,?" newline bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0: PLL is disabled 1'b1,?" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0: Output clocks are derived from the VCO clock 1'b1,?" newline bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0: Post divide powered down,?" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0: Delta-Sigma modulator is disabled,1: Delta-Sigma modulator is enabled" newline bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0: Fractional NC DAC is disabled,1: Fractional NC DAC is enabled" rgroup.long 0x1B024++0x3 line.long 0x0 "CFG_pll27_STAT," bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0: PLL is not locked 1'b1,?" rgroup.long 0x1B030++0xB line.long 0x0 "CFG_pll27_FREQ_CTRL0," hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll27_FREQ_CTRL1," hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll27_DIV_CTRL," bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0: Reserved,1: Divide by 1 3'b010,?,3: Divide by 3 3'b100,?,5: Divide by 5 3'b110,?,7: Divide by 7" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" rgroup.long 0x1B040++0x7 line.long 0x0 "CFG_pll27_SS_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0: Spread spectrum modulation is enabled 1'b1,?" newline hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" newline bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" newline bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0: Center spread 1'b1,?" newline bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0: Use 128 point triangle wave table 1'b1,?" line.long 0x4 "CFG_pll27_SS_SPREAD," hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" newline hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" rgroup.long 0x1B060++0x3 line.long 0x0 "CFG_pll27_CAL_CTRL," bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0: Normal operation 1'b1,?" newline bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0: Use the calibration output to set the phase..,?" newline hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x1B064++0x3 line.long 0x0 "CFG_pll27_CAL_STAT," bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" newline hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" rgroup.long 0x1B080++0x3 line.long 0x0 "CFG_pll27_HSDIV_CTRL0," bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x1C000++0x3 line.long 0x0 "CFG_pll28_PID," bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" newline hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x1C008++0x3 line.long 0x0 "CFG_pll28_CFG," hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" newline bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0: SSM is not present 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0: SSM Wave table is not present 1'b1,?" newline bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0: Fractional PLL 2'b01,?,2: De-Skew PLL,?" rgroup.long 0x1C010++0x7 line.long 0x0 "CFG_pll28_LOCKKEY0," hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition28 registers" newline rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll28_LOCKKEY1," hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition28 registers" rgroup.long 0x1C020++0x3 line.long 0x0 "CFG_pll28_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0: Synchronously select PLL and associated HSDIV..,?" newline bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0: Do not automatically switch to ref clock source..,?" newline bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0: PLL is disabled 1'b1,?" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0: Output clocks are derived from the VCO clock 1'b1,?" newline bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0: Post divide powered down,?" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0: Delta-Sigma modulator is disabled,1: Delta-Sigma modulator is enabled" newline bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0: Fractional NC DAC is disabled,1: Fractional NC DAC is enabled" rgroup.long 0x1C024++0x3 line.long 0x0 "CFG_pll28_STAT," bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0: PLL is not locked 1'b1,?" rgroup.long 0x1C030++0xB line.long 0x0 "CFG_pll28_FREQ_CTRL0," hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll28_FREQ_CTRL1," hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll28_DIV_CTRL," bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0: Reserved,1: Divide by 1 3'b010,?,3: Divide by 3 3'b100,?,5: Divide by 5 3'b110,?,7: Divide by 7" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" rgroup.long 0x1C040++0x7 line.long 0x0 "CFG_pll28_SS_CTRL," bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0: Spread spectrum modulation is enabled 1'b1,?" newline hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" newline bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" newline bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0: Center spread 1'b1,?" newline bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0: Use 128 point triangle wave table 1'b1,?" line.long 0x4 "CFG_pll28_SS_SPREAD," hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" newline hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" rgroup.long 0x1C060++0x3 line.long 0x0 "CFG_pll28_CAL_CTRL," bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0: Normal operation 1'b1,?" newline bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0: Use the calibration output to set the phase..,?" newline hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x1C064++0x3 line.long 0x0 "CFG_pll28_CAL_STAT," bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" newline hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" rgroup.long 0x1C080++0x3 line.long 0x0 "CFG_pll28_HSDIV_CTRL0," bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" newline bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0: Synchronously disable CLKOUT1 1'b1,?" newline bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0: Changes to DIV value synchronized to prevent..,?" newline hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" tree.end tree "PSRAM2KECC0" base ad:0x0 tree "PSRAM2KECC0_ECC_AGGR (PSRAM2KECC0_ECC_AGGR)" base ad:0xC01000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" bitfld.long 0x4 1. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1" bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" bitfld.long 0x0 1. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1" bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" bitfld.long 0x0 1. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1" bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" bitfld.long 0x4 1. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1" bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" bitfld.long 0x0 1. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1" bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" bitfld.long 0x0 1. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1" bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "PSRAM2KECC0_RAM (PSRAM2KECC0_RAM)" rgroup.long 0x0++0x3 line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree.end tree "PSRAMECC0" base ad:0x0 tree "PSRAMECC0_ECC_AGGR (PSRAMECC0_ECC_AGGR)" base ad:0xC00000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" bitfld.long 0x4 1. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1" bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" bitfld.long 0x0 1. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1" bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" bitfld.long 0x0 1. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1" bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" bitfld.long 0x4 1. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1" bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" bitfld.long 0x0 1. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1" bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" bitfld.long 0x0 1. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1" bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "PSRAMECC0_RAM (PSRAMECC0_RAM)" base ad:0x200000 rgroup.long 0x0++0x3 line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree.end tree "R5FSS0" base ad:0x0 tree "R5FSS0_COMMON0" tree "R5FSS0_COMMON0_COMPARE_CFG (R5FSS0_COMMON0_COMPARE_CFG)" base ad:0x5B00000 rgroup.long 0x0++0x7 line.long 0x0 "PULSAR_SL_COMPARE_WRAPPER__CFG__MMRS_CCMSR1,Shows the Error and Self test Status of the CPU CPU Compare block." hexmask.long.word 0x0 17.--31. 1. "RESERVED2,This is the Reserved field" bitfld.long 0x0 16. "CMPE1,This is the CMPE1 field" "0,1" hexmask.long.byte 0x0 9.--15. 1. "RESERVED1,This is the Reserved field" rbitfld.long 0x0 8. "STC1,This is the STC1 field" "0,1" hexmask.long.byte 0x0 2.--7. 1. "RESERVED0,This is the Reserved field" rbitfld.long 0x0 1. "STET1,This is the STET1 field" "0,1" newline rbitfld.long 0x0 0. "STE1,This is the STE1 field" "0,1" line.long 0x4 "PULSAR_SL_COMPARE_WRAPPER__CFG__MMRS_CCMKEYR1,Selects Operating mode of CPU Compare block." hexmask.long 0x4 4.--31. 1. "RESERVED,This is the Reserved field" hexmask.long.byte 0x4 0.--3. 1. "MKEY1,This is the MKEY1 field" rgroup.long 0x10++0xB line.long 0x0 "PULSAR_SL_COMPARE_WRAPPER__CFG__MMRS_CCMSR3,Shows the Error and Self test Status of the CPU CPU Compare block." hexmask.long.word 0x0 17.--31. 1. "RESERVED2,This is the Reserved field" bitfld.long 0x0 16. "CMPE3,This is the CMPE3 field" "0,1" hexmask.long.byte 0x0 9.--15. 1. "RESERVED1,This is the Reserved field" rbitfld.long 0x0 8. "STC3,This is the STC3 field" "0,1" hexmask.long.byte 0x0 2.--7. 1. "RESERVED0,This is the Reserved field" rbitfld.long 0x0 1. "STET3,This is the STET3 field" "0,1" newline rbitfld.long 0x0 0. "STE3,This is the STE3 field" "0,1" line.long 0x4 "PULSAR_SL_COMPARE_WRAPPER__CFG__MMRS_CCMKEYR3,Selects Operating mode of CPU Compare block." hexmask.long 0x4 4.--31. 1. "RESERVED,This is the Reserved field" hexmask.long.byte 0x4 0.--3. 1. "MKEY3,This is the MKEY3 field" line.long 0x8 "PULSAR_SL_COMPARE_WRAPPER__CFG__MMRS_CCMPOLCNTRL,Selects Operating mode of CPU Compare block." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,This is the Reserved field" hexmask.long.byte 0x8 0.--7. 1. "POL_INV,This is the Polarity Inversion field" tree.end tree "R5FSS0_COMMON0_EVNT_BUS_VBUSP_MMRS (R5FSS0_COMMON0_EVNT_BUS_VBUSP_MMRS)" base ad:0x2A2D000 rgroup.long 0x0++0x3 line.long 0x0 "EVNT_BUS__VBUSP__MMRS_DISABLE_CR,This register contains config bits to enable or disable change requests added to the IP" bitfld.long 0x0 0. "COMBINE_TCM_LOCKSTEP_MODE,this bit disables the CR logic to combine TCM in lockstep mode" "0,1" rgroup.long 0x4++0x13 line.long 0x0 "EVNT_BUS__VBUSP__MMRS_PULSAR_CPU0_EVNT_BUS_SB_ERR_CNT_STATUS,Status bits showing the PULSAR CPU0 EVNT_BUS single bit error counters" bitfld.long 0x0 16.--17. "EVNT_BUS8,Status bits showing the PULSAR CPU0 EVNT 8 single bit error counter." "0,1,2,3" bitfld.long 0x0 14.--15. "EVNT_BUS7,Status bits showing the PULSAR CPU0 EVNT 7 single bit error counter." "0,1,2,3" newline bitfld.long 0x0 12.--13. "EVNT_BUS6,Status bits showing the PULSAR CPU0 EVNT 6 single bit error counter." "0,1,2,3" bitfld.long 0x0 10.--11. "EVNT_BUS5,Status bits showing the PULSAR CPU0 EVNT 5 single bit error counter." "0,1,2,3" newline bitfld.long 0x0 8.--9. "EVNT_BUS4,Status bits showing the PULSAR CPU0 EVNT 4 single bit error counter." "0,1,2,3" bitfld.long 0x0 6.--7. "EVNT_BUS3,Status bits showing the PULSAR CPU0 EVNT 3 single bit error counter." "0,1,2,3" newline bitfld.long 0x0 4.--5. "EVNT_BUS2,Status bits showing the PULSAR CPU0 EVNT 2 single bit error counter." "0,1,2,3" bitfld.long 0x0 2.--3. "EVNT_BUS1,Status bits showing the PULSAR CPU0 EVNT 1 single bit error counter." "0,1,2,3" newline bitfld.long 0x0 0.--1. "EVNT_BUS0,Status bits showing the PULSAR CPU0 EVNT 0 single bit error counter." "0,1,2,3" line.long 0x4 "EVNT_BUS__VBUSP__MMRS_PULSAR_CPU1_EVNT_BUS_SB_ERR_CNT_STATUS,Status bits showing the PULSAR CPU1 EVNT_BUS single bit error counters" bitfld.long 0x4 16.--17. "EVNT_BUS8,Status bits showing the PULSAR CPU1 EVNT 8 single bit error counter." "0,1,2,3" bitfld.long 0x4 14.--15. "EVNT_BUS7,Status bits showing the PULSAR CPU1 EVNT 7 single bit error counter." "0,1,2,3" newline bitfld.long 0x4 12.--13. "EVNT_BUS6,Status bits showing the PULSAR CPU1 EVNT 6 single bit error counter." "0,1,2,3" bitfld.long 0x4 10.--11. "EVNT_BUS5,Status bits showing the PULSAR CPU1 EVNT 5 single bit error counter." "0,1,2,3" newline bitfld.long 0x4 8.--9. "EVNT_BUS4,Status bits showing the PULSAR CPU1 EVNT 4 single bit error counter." "0,1,2,3" bitfld.long 0x4 6.--7. "EVNT_BUS3,Status bits showing the PULSAR CPU1 EVNT 3 single bit error counter." "0,1,2,3" newline bitfld.long 0x4 4.--5. "EVNT_BUS2,Status bits showing the PULSAR CPU1 EVNT 2 single bit error counter." "0,1,2,3" bitfld.long 0x4 2.--3. "EVNT_BUS1,Status bits showing the PULSAR CPU1 EVNT 1 single bit error counter." "0,1,2,3" newline bitfld.long 0x4 0.--1. "EVNT_BUS0,Status bits showing the PULSAR CPU1 EVNT 0 single bit error counter." "0,1,2,3" line.long 0x8 "EVNT_BUS__VBUSP__MMRS_PULSAR_CPU0_EVNT_BUS_MB_ERR_CNT_STATUS,Status bits showing the PULSAR CPU0 EVNT_BUS multi bit error counters" bitfld.long 0x8 12.--13. "EVNT_BUS6,Status bits showing the PULSAR CPU0 EVNT 6 multi bit error counter." "0,1,2,3" bitfld.long 0x8 10.--11. "EVNT_BUS5,Status bits showing the PULSAR CPU0 EVNT 5 multi bit error counter." "0,1,2,3" newline bitfld.long 0x8 8.--9. "EVNT_BUS4,Status bits showing the PULSAR CPU0 EVNT 4 multi bit error counter." "0,1,2,3" bitfld.long 0x8 6.--7. "EVNT_BUS3,Status bits showing the PULSAR CPU0 EVNT 3 multi bit error counter." "0,1,2,3" newline bitfld.long 0x8 4.--5. "EVNT_BUS2,Status bits showing the PULSAR CPU0 EVNT 2 multi bit error counter." "0,1,2,3" bitfld.long 0x8 2.--3. "EVNT_BUS1,Status bits showing the PULSAR CPU0 EVNT 1 multi bit error counter." "0,1,2,3" newline bitfld.long 0x8 0.--1. "EVNT_BUS0,Status bits showing the PULSAR CPU0 EVNT 0 multi bit error counter." "0,1,2,3" line.long 0xC "EVNT_BUS__VBUSP__MMRS_PULSAR_CPU1_EVNT_BUS_MB_ERR_CNT_STATUS,Status bits showing the PULSAR CPU1 EVNT_BUS multi bit error counters" bitfld.long 0xC 12.--13. "EVNT_BUS6,Status bits showing the PULSAR CPU1 EVNT 6 multi bit error counter." "0,1,2,3" bitfld.long 0xC 10.--11. "EVNT_BUS5,Status bits showing the PULSAR CPU1 EVNT 5 multi bit error counter." "0,1,2,3" newline bitfld.long 0xC 8.--9. "EVNT_BUS4,Status bits showing the PULSAR CPU1 EVNT 4 multi bit error counter." "0,1,2,3" bitfld.long 0xC 6.--7. "EVNT_BUS3,Status bits showing the PULSAR CPU1 EVNT 3 multi bit error counter." "0,1,2,3" newline bitfld.long 0xC 4.--5. "EVNT_BUS2,Status bits showing the PULSAR CPU1 EVNT 2 multi bit error counter." "0,1,2,3" bitfld.long 0xC 2.--3. "EVNT_BUS1,Status bits showing the PULSAR CPU1 EVNT 1 multi bit error counter." "0,1,2,3" newline bitfld.long 0xC 0.--1. "EVNT_BUS0,Status bits showing the PULSAR CPU1 EVNT 0 multi bit error counter." "0,1,2,3" line.long 0x10 "EVNT_BUS__VBUSP__MMRS_PULSAR_EVNT_BUS_ESM_STATUS,ESM status bits for the PULSAR EVNT BUS" bitfld.long 0x10 3. "CPU1_MULTIPLE_BIT_ERROR,ESM status of CPU1 multiple bit errors on EVNT BUS" "0,1" bitfld.long 0x10 2. "CPU1_SINGLE_BIT_ERROR,ESM status of CPU1 single bit errors on EVNT BUS" "0,1" newline bitfld.long 0x10 1. "CPU0_MULTIPLE_BIT_ERROR,ESM status of CPU0 multiple bit errors on EVNT BUS" "0,1" bitfld.long 0x10 0. "CPU0_SINGLE_BIT_ERROR,ESM status of CPU0 single bit errors on EVNT BUS" "0,1" rgroup.long 0x18++0xF line.long 0x0 "EVNT_BUS__VBUSP__MMRS_PULSAR_EVNT_BUS_ESM_SET,SET the PULSAR EVNT BUS ESM events" bitfld.long 0x0 3. "CPU1_MULTIPLE_BIT_ERROR,SET CPU1 multiple bit errors ESM event" "0,1" bitfld.long 0x0 2. "CPU1_SINGLE_BIT_ERROR,SET CPU1 single bit errors ESM event" "0,1" newline bitfld.long 0x0 1. "CPU0_MULTIPLE_BIT_ERROR,SET CPU0 multiple bit error ESM event" "0,1" bitfld.long 0x0 0. "CPU0_SINGLE_BIT_ERROR,SET CPU0 single bit error ESM event" "0,1" line.long 0x4 "EVNT_BUS__VBUSP__MMRS_PULSAR_EVNT_BUS_ESM_CLR,RESET the PULSAR EVNT BUS ESM events" bitfld.long 0x4 31. "CPU1_EB6_MULTIPLE_BIT_ERROR,Decrement CPU1 Event Bus 31 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 30. "CPU1_EB5_MULTIPLE_BIT_ERROR,Decrement CPU1 Event Bus 30 MULTIPLE BIT Error Counter" "0,1" newline bitfld.long 0x4 29. "CPU1_EB4_MULTIPLE_BIT_ERROR,Decrement CPU1 Event Bus 29 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 28. "CPU1_EB3_MULTIPLE_BIT_ERROR,Decrement CPU1 Event Bus 28 MULTIPLE BIT Error Counter" "0,1" newline bitfld.long 0x4 27. "CPU1_EB2_MULTIPLE_BIT_ERROR,Decrement CPU1 Event Bus 27 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 26. "CPU1_EB1_MULTIPLE_BIT_ERROR,Decrement CPU1 Event Bus 26 MULTIPLE BIT Error Counter" "0,1" newline bitfld.long 0x4 25. "CPU1_EB0_MULTIPLE_BIT_ERROR,Decrement CPU1 Event Bus 25 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 24. "CPU1_EB8_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 24 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 23. "CPU1_EB7_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 23 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 22. "CPU1_EB6_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 22 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 21. "CPU1_EB5_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 21 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 20. "CPU1_EB4_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 20 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 19. "CPU1_EB3_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 19 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 18. "CPU1_EB2_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 18 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 17. "CPU1_EB1_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 17 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 16. "CPU1_EB0_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 16 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 15. "CPU0_EB6_MULTIPLE_BIT_ERROR,Decrement CPU0 Event Bus 15 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 14. "CPU0_EB5_MULTIPLE_BIT_ERROR,Decrement CPU0 Event Bus 14 MULTIPLE BIT Error Counter" "0,1" newline bitfld.long 0x4 13. "CPU0_EB4_MULTIPLE_BIT_ERROR,Decrement CPU0 Event Bus 13 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 12. "CPU0_EB3_MULTIPLE_BIT_ERROR,Decrement CPU0 Event Bus 12 MULTIPLE BIT Error Counter" "0,1" newline bitfld.long 0x4 11. "CPU0_EB2_MULTIPLE_BIT_ERROR,Decrement CPU0 Event Bus 11 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 10. "CPU0_EB1_MULTIPLE_BIT_ERROR,Decrement CPU0 Event Bus 10 MULTIPLE BIT Error Counter" "0,1" newline bitfld.long 0x4 9. "CPU0_EB0_MULTIPLE_BIT_ERROR,Decrement CPU0 Event Bus 9 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 8. "CPU0_EB8_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 8 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 7. "CPU0_EB7_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 7 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 6. "CPU0_EB6_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 6 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 5. "CPU0_EB5_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 5 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 4. "CPU0_EB4_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 4 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 3. "CPU0_EB3_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 3 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 2. "CPU0_EB2_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 2 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 1. "CPU0_EB1_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 1 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 0. "CPU0_EB0_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 0 SINGLE BIT Error Counter" "0,1" line.long 0x8 "EVNT_BUS__VBUSP__MMRS_PULSAR_EVNT_BUS_MASK_ESM_SET,MASK the PULSAR EVNT BUS ESM events" bitfld.long 0x8 3. "CPU1_MULTIPLE_BIT_ERROR,MASK CPU1 multiple bit errors ESM event" "0,1" bitfld.long 0x8 2. "CPU1_SINGLE_BIT_ERROR,MASK CPU1 single bit errors ESM event" "0,1" newline bitfld.long 0x8 1. "CPU0_MULTIPLE_BIT_ERROR,MASK CPU0 multiple bit error ESM event" "0,1" bitfld.long 0x8 0. "CPU0_SINGLE_BIT_ERROR,MASK CPU0 single bit error ESM event" "0,1" line.long 0xC "EVNT_BUS__VBUSP__MMRS_PULSAR_EVNT_BUS_MASK_ESM_CLR,UNMASK the PULSAR EVNT BUS ESM events" bitfld.long 0xC 3. "CPU1_MULTIPLE_BIT_ERROR,UNMASK CPU1 multiple bit errors ESM event" "0,1" bitfld.long 0xC 2. "CPU1_SINGLE_BIT_ERROR,UNMASK CPU1 single bit errors ESM event" "0,1" newline bitfld.long 0xC 1. "CPU0_MULTIPLE_BIT_ERROR,UNMASK CPU0 multiple bit error ESM event" "0,1" bitfld.long 0xC 0. "CPU0_SINGLE_BIT_ERROR,UNMASK CPU0 single bit error ESM event" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "EVNT_BUS__VBUSP__MMRS_PULSAR_EVT_BUS_REVID,Module ID register" hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release" newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" tree.end tree.end tree "R5FSS0_CORE0_ECC_AGGR_CORE0_ECC_AGGR (R5FSS0_CORE0_ECC_AGGR_CORE0_ECC_AGGR)" base ad:0x2A68000 rgroup.long 0x0++0x3 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "CPU0_ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_periph_mst_ramecc_pend" "0,1" newline bitfld.long 0x4 30. "CPU0_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 29. "CPU0_AXI2VBUSM_MEM_MST_RAMECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_mem_mst_ramecc_pend" "0,1" newline bitfld.long 0x4 28. "CPU0_VBUSM2AXI_EDC_PEND,Interrupt Pending Status for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x4 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "B1TCM0_BANK1_PEND,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM0_BANK0_PEND,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x4 24. "B0TCM0_BANK1_PEND,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM0_BANK0_PEND,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x4 22. "ATCM0_BANK1_PEND,Interrupt Pending Status for atcm0_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM0_BANK0_PEND,Interrupt Pending Status for atcm0_bank0_pend" "0,1" newline bitfld.long 0x4 20. "CPU0_DDATA_RAM7_PEND,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_DDATA_RAM6_PEND,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x4 18. "CPU0_DDATA_RAM5_PEND,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_DDATA_RAM4_PEND,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x4 16. "CPU0_DDATA_RAM3_PEND,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_DDATA_RAM2_PEND,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x4 14. "CPU0_DDATA_RAM1_PEND,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_DDATA_RAM0_PEND,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x4 12. "CPU0_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_DTAG_RAM3_PEND,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x4 10. "CPU0_DTAG_RAM2_PEND,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_DTAG_RAM1_PEND,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x4 8. "CPU0_DTAG_RAM0_PEND,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_IDATA_BANK3_PEND,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x4 6. "CPU0_IDATA_BANK2_PEND,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_IDATA_BANK1_PEND,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x4 4. "CPU0_IDATA_BANK0_PEND,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_ITAG_RAM3_PEND,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x4 2. "CPU0_ITAG_RAM2_PEND,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_ITAG_RAM1_PEND,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_ITAG_RAM0_PEND,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1" line.long 0x8 "CPU0_ECC_AGGR__CFG__REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 3. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x8 2. "SCRP_EDC_PEND,Interrupt Pending Status for scrp_edc_pend" "0,1" newline bitfld.long 0x8 1. "CPU0_AHB2VBUSP_EDC_PEND,Interrupt Pending Status for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x8 0. "CPU0_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x80++0x7 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_periph_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "CPU0_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU0_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_mem_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "CPU0_VBUSM2AXI_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1" line.long 0x4 "CPU0_ECC_AGGR__CFG__REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 3. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x4 2. "SCRP_EDC_ENABLE_SET,Interrupt Enable Set Register for scrp_edc_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_AHB2VBUSP_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_periph_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "CPU0_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU0_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_mem_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "CPU0_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram0_pend" "0,1" line.long 0x4 "CPU0_ECC_AGGR__CFG__REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 3. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x4 2. "SCRP_EDC_ENABLE_CLR,Interrupt Enable Clear Register for scrp_edc_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x13C++0xB line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "CPU0_ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_periph_mst_ramecc_pend" "0,1" newline bitfld.long 0x4 30. "CPU0_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 29. "CPU0_AXI2VBUSM_MEM_MST_RAMECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_mem_mst_ramecc_pend" "0,1" newline bitfld.long 0x4 28. "CPU0_VBUSM2AXI_EDC_PEND,Interrupt Pending Status for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x4 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "B1TCM0_BANK1_PEND,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM0_BANK0_PEND,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x4 24. "B0TCM0_BANK1_PEND,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM0_BANK0_PEND,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x4 22. "ATCM0_BANK1_PEND,Interrupt Pending Status for atcm0_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM0_BANK0_PEND,Interrupt Pending Status for atcm0_bank0_pend" "0,1" newline bitfld.long 0x4 20. "CPU0_DDATA_RAM7_PEND,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_DDATA_RAM6_PEND,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x4 18. "CPU0_DDATA_RAM5_PEND,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_DDATA_RAM4_PEND,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x4 16. "CPU0_DDATA_RAM3_PEND,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_DDATA_RAM2_PEND,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x4 14. "CPU0_DDATA_RAM1_PEND,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_DDATA_RAM0_PEND,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x4 12. "CPU0_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_DTAG_RAM3_PEND,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x4 10. "CPU0_DTAG_RAM2_PEND,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_DTAG_RAM1_PEND,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x4 8. "CPU0_DTAG_RAM0_PEND,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_IDATA_BANK3_PEND,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x4 6. "CPU0_IDATA_BANK2_PEND,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_IDATA_BANK1_PEND,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x4 4. "CPU0_IDATA_BANK0_PEND,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_ITAG_RAM3_PEND,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x4 2. "CPU0_ITAG_RAM2_PEND,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_ITAG_RAM1_PEND,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_ITAG_RAM0_PEND,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1" line.long 0x8 "CPU0_ECC_AGGR__CFG__REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 3. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x8 2. "SCRP_EDC_PEND,Interrupt Pending Status for scrp_edc_pend" "0,1" newline bitfld.long 0x8 1. "CPU0_AHB2VBUSP_EDC_PEND,Interrupt Pending Status for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x8 0. "CPU0_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x180++0x7 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_periph_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "CPU0_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU0_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_mem_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "CPU0_VBUSM2AXI_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1" line.long 0x4 "CPU0_ECC_AGGR__CFG__REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 3. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x4 2. "SCRP_EDC_ENABLE_SET,Interrupt Enable Set Register for scrp_edc_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_AHB2VBUSP_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_periph_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "CPU0_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU0_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_mem_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "CPU0_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram0_pend" "0,1" line.long 0x4 "CPU0_ECC_AGGR__CFG__REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 3. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x4 2. "SCRP_EDC_ENABLE_CLR,Interrupt Enable Clear Register for scrp_edc_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "CPU0_ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "CPU0_ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "CPU0_ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "R5FSS0_CORE1_ECC_AGGR_CORE1_ECC_AGGR (R5FSS0_CORE1_ECC_AGGR_CORE1_ECC_AGGR)" base ad:0x5B10000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_periph_mst_ramecc_pend" "0,1" bitfld.long 0x4 30. "CPU1_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 29. "CPU1_AXI2VBUSM_MEM_MST_RAMECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_mem_mst_ramecc_pend" "0,1" bitfld.long 0x4 28. "CPU1_VBUSM2AXI_EDC_PEND,Interrupt Pending Status for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x4 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x4 26. "B1TCM1_BANK1_PEND,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM1_BANK0_PEND,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1" bitfld.long 0x4 24. "B0TCM1_BANK1_PEND,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM1_BANK0_PEND,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1" bitfld.long 0x4 22. "ATCM1_BANK1_PEND,Interrupt Pending Status for atcm1_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM1_BANK0_PEND,Interrupt Pending Status for atcm1_bank0_pend" "0,1" bitfld.long 0x4 20. "CPU1_DDATA_RAM7_PEND,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_DDATA_RAM6_PEND,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x4 18. "CPU1_DDATA_RAM5_PEND,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_DDATA_RAM4_PEND,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x4 16. "CPU1_DDATA_RAM3_PEND,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_DDATA_RAM2_PEND,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x4 14. "CPU1_DDATA_RAM1_PEND,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_DDATA_RAM0_PEND,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x4 12. "CPU1_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_DTAG_RAM3_PEND,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x4 10. "CPU1_DTAG_RAM2_PEND,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_DTAG_RAM1_PEND,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x4 8. "CPU1_DTAG_RAM0_PEND,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_IDATA_BANK3_PEND,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x4 6. "CPU1_IDATA_BANK2_PEND,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_IDATA_BANK1_PEND,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x4 4. "CPU1_IDATA_BANK0_PEND,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_ITAG_RAM3_PEND,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x4 2. "CPU1_ITAG_RAM2_PEND,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_ITAG_RAM1_PEND,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x4 0. "CPU1_ITAG_RAM0_PEND,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1" line.long 0x8 "REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 2. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" bitfld.long 0x8 1. "CPU1_AHB2VBUSP_EDC_PEND,Interrupt Pending Status for cpu1_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x8 0. "CPU1_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x80++0x7 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_periph_mst_ramecc_pend" "0,1" bitfld.long 0x0 30. "CPU1_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU1_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_mem_mst_ramecc_pend" "0,1" bitfld.long 0x0 28. "CPU1_VBUSM2AXI_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1" line.long 0x4 "REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 2. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" bitfld.long 0x4 1. "CPU1_AHB2VBUSP_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU1_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_periph_mst_ramecc_pend" "0,1" bitfld.long 0x0 30. "CPU1_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU1_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_mem_mst_ramecc_pend" "0,1" bitfld.long 0x0 28. "CPU1_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram0_pend" "0,1" line.long 0x4 "REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 2. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" bitfld.long 0x4 1. "CPU1_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU1_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x13C++0xB line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_periph_mst_ramecc_pend" "0,1" bitfld.long 0x4 30. "CPU1_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 29. "CPU1_AXI2VBUSM_MEM_MST_RAMECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_mem_mst_ramecc_pend" "0,1" bitfld.long 0x4 28. "CPU1_VBUSM2AXI_EDC_PEND,Interrupt Pending Status for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x4 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x4 26. "B1TCM1_BANK1_PEND,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM1_BANK0_PEND,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1" bitfld.long 0x4 24. "B0TCM1_BANK1_PEND,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM1_BANK0_PEND,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1" bitfld.long 0x4 22. "ATCM1_BANK1_PEND,Interrupt Pending Status for atcm1_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM1_BANK0_PEND,Interrupt Pending Status for atcm1_bank0_pend" "0,1" bitfld.long 0x4 20. "CPU1_DDATA_RAM7_PEND,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_DDATA_RAM6_PEND,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x4 18. "CPU1_DDATA_RAM5_PEND,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_DDATA_RAM4_PEND,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x4 16. "CPU1_DDATA_RAM3_PEND,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_DDATA_RAM2_PEND,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x4 14. "CPU1_DDATA_RAM1_PEND,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_DDATA_RAM0_PEND,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x4 12. "CPU1_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_DTAG_RAM3_PEND,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x4 10. "CPU1_DTAG_RAM2_PEND,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_DTAG_RAM1_PEND,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x4 8. "CPU1_DTAG_RAM0_PEND,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_IDATA_BANK3_PEND,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x4 6. "CPU1_IDATA_BANK2_PEND,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_IDATA_BANK1_PEND,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x4 4. "CPU1_IDATA_BANK0_PEND,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_ITAG_RAM3_PEND,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x4 2. "CPU1_ITAG_RAM2_PEND,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_ITAG_RAM1_PEND,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x4 0. "CPU1_ITAG_RAM0_PEND,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1" line.long 0x8 "REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 2. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" bitfld.long 0x8 1. "CPU1_AHB2VBUSP_EDC_PEND,Interrupt Pending Status for cpu1_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x8 0. "CPU1_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x180++0x7 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_periph_mst_ramecc_pend" "0,1" bitfld.long 0x0 30. "CPU1_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU1_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_mem_mst_ramecc_pend" "0,1" bitfld.long 0x0 28. "CPU1_VBUSM2AXI_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1" line.long 0x4 "REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 2. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" bitfld.long 0x4 1. "CPU1_AHB2VBUSP_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU1_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_periph_mst_ramecc_pend" "0,1" bitfld.long 0x0 30. "CPU1_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU1_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_mem_mst_ramecc_pend" "0,1" bitfld.long 0x0 28. "CPU1_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram0_pend" "0,1" line.long 0x4 "REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 2. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" bitfld.long 0x4 1. "CPU1_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU1_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree.end tree "R5FSS1" base ad:0x0 tree "R5FSS1_COMMON0" tree "R5FSS1_COMMON0_COMPARE_CFG (R5FSS1_COMMON0_COMPARE_CFG)" base ad:0x5B20000 rgroup.long 0x0++0x7 line.long 0x0 "PULSAR_SL_COMPARE_WRAPPER__CFG__MMRS_CCMSR1,Shows the Error and Self test Status of the CPU CPU Compare block." hexmask.long.word 0x0 17.--31. 1. "RESERVED2,This is the Reserved field" bitfld.long 0x0 16. "CMPE1,This is the CMPE1 field" "0,1" hexmask.long.byte 0x0 9.--15. 1. "RESERVED1,This is the Reserved field" rbitfld.long 0x0 8. "STC1,This is the STC1 field" "0,1" hexmask.long.byte 0x0 2.--7. 1. "RESERVED0,This is the Reserved field" rbitfld.long 0x0 1. "STET1,This is the STET1 field" "0,1" newline rbitfld.long 0x0 0. "STE1,This is the STE1 field" "0,1" line.long 0x4 "PULSAR_SL_COMPARE_WRAPPER__CFG__MMRS_CCMKEYR1,Selects Operating mode of CPU Compare block." hexmask.long 0x4 4.--31. 1. "RESERVED,This is the Reserved field" hexmask.long.byte 0x4 0.--3. 1. "MKEY1,This is the MKEY1 field" rgroup.long 0x10++0xB line.long 0x0 "PULSAR_SL_COMPARE_WRAPPER__CFG__MMRS_CCMSR3,Shows the Error and Self test Status of the CPU CPU Compare block." hexmask.long.word 0x0 17.--31. 1. "RESERVED2,This is the Reserved field" bitfld.long 0x0 16. "CMPE3,This is the CMPE3 field" "0,1" hexmask.long.byte 0x0 9.--15. 1. "RESERVED1,This is the Reserved field" rbitfld.long 0x0 8. "STC3,This is the STC3 field" "0,1" hexmask.long.byte 0x0 2.--7. 1. "RESERVED0,This is the Reserved field" rbitfld.long 0x0 1. "STET3,This is the STET3 field" "0,1" newline rbitfld.long 0x0 0. "STE3,This is the STE3 field" "0,1" line.long 0x4 "PULSAR_SL_COMPARE_WRAPPER__CFG__MMRS_CCMKEYR3,Selects Operating mode of CPU Compare block." hexmask.long 0x4 4.--31. 1. "RESERVED,This is the Reserved field" hexmask.long.byte 0x4 0.--3. 1. "MKEY3,This is the MKEY3 field" line.long 0x8 "PULSAR_SL_COMPARE_WRAPPER__CFG__MMRS_CCMPOLCNTRL,Selects Operating mode of CPU Compare block." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,This is the Reserved field" hexmask.long.byte 0x8 0.--7. 1. "POL_INV,This is the Polarity Inversion field" tree.end tree "R5FSS1_COMMON0_EVNT_BUS_VBUSP_MMRS (R5FSS1_COMMON0_EVNT_BUS_VBUSP_MMRS)" base ad:0x2A2E000 rgroup.long 0x0++0x3 line.long 0x0 "EVNT_BUS__VBUSP__MMRS_DISABLE_CR,This register contains config bits to enable or disable change requests added to the IP" bitfld.long 0x0 0. "COMBINE_TCM_LOCKSTEP_MODE,this bit disables the CR logic to combine TCM in lockstep mode" "0,1" rgroup.long 0x4++0x13 line.long 0x0 "EVNT_BUS__VBUSP__MMRS_PULSAR_CPU0_EVNT_BUS_SB_ERR_CNT_STATUS,Status bits showing the PULSAR CPU0 EVNT_BUS single bit error counters" bitfld.long 0x0 16.--17. "EVNT_BUS8,Status bits showing the PULSAR CPU0 EVNT 8 single bit error counter." "0,1,2,3" bitfld.long 0x0 14.--15. "EVNT_BUS7,Status bits showing the PULSAR CPU0 EVNT 7 single bit error counter." "0,1,2,3" newline bitfld.long 0x0 12.--13. "EVNT_BUS6,Status bits showing the PULSAR CPU0 EVNT 6 single bit error counter." "0,1,2,3" bitfld.long 0x0 10.--11. "EVNT_BUS5,Status bits showing the PULSAR CPU0 EVNT 5 single bit error counter." "0,1,2,3" newline bitfld.long 0x0 8.--9. "EVNT_BUS4,Status bits showing the PULSAR CPU0 EVNT 4 single bit error counter." "0,1,2,3" bitfld.long 0x0 6.--7. "EVNT_BUS3,Status bits showing the PULSAR CPU0 EVNT 3 single bit error counter." "0,1,2,3" newline bitfld.long 0x0 4.--5. "EVNT_BUS2,Status bits showing the PULSAR CPU0 EVNT 2 single bit error counter." "0,1,2,3" bitfld.long 0x0 2.--3. "EVNT_BUS1,Status bits showing the PULSAR CPU0 EVNT 1 single bit error counter." "0,1,2,3" newline bitfld.long 0x0 0.--1. "EVNT_BUS0,Status bits showing the PULSAR CPU0 EVNT 0 single bit error counter." "0,1,2,3" line.long 0x4 "EVNT_BUS__VBUSP__MMRS_PULSAR_CPU1_EVNT_BUS_SB_ERR_CNT_STATUS,Status bits showing the PULSAR CPU1 EVNT_BUS single bit error counters" bitfld.long 0x4 16.--17. "EVNT_BUS8,Status bits showing the PULSAR CPU1 EVNT 8 single bit error counter." "0,1,2,3" bitfld.long 0x4 14.--15. "EVNT_BUS7,Status bits showing the PULSAR CPU1 EVNT 7 single bit error counter." "0,1,2,3" newline bitfld.long 0x4 12.--13. "EVNT_BUS6,Status bits showing the PULSAR CPU1 EVNT 6 single bit error counter." "0,1,2,3" bitfld.long 0x4 10.--11. "EVNT_BUS5,Status bits showing the PULSAR CPU1 EVNT 5 single bit error counter." "0,1,2,3" newline bitfld.long 0x4 8.--9. "EVNT_BUS4,Status bits showing the PULSAR CPU1 EVNT 4 single bit error counter." "0,1,2,3" bitfld.long 0x4 6.--7. "EVNT_BUS3,Status bits showing the PULSAR CPU1 EVNT 3 single bit error counter." "0,1,2,3" newline bitfld.long 0x4 4.--5. "EVNT_BUS2,Status bits showing the PULSAR CPU1 EVNT 2 single bit error counter." "0,1,2,3" bitfld.long 0x4 2.--3. "EVNT_BUS1,Status bits showing the PULSAR CPU1 EVNT 1 single bit error counter." "0,1,2,3" newline bitfld.long 0x4 0.--1. "EVNT_BUS0,Status bits showing the PULSAR CPU1 EVNT 0 single bit error counter." "0,1,2,3" line.long 0x8 "EVNT_BUS__VBUSP__MMRS_PULSAR_CPU0_EVNT_BUS_MB_ERR_CNT_STATUS,Status bits showing the PULSAR CPU0 EVNT_BUS multi bit error counters" bitfld.long 0x8 12.--13. "EVNT_BUS6,Status bits showing the PULSAR CPU0 EVNT 6 multi bit error counter." "0,1,2,3" bitfld.long 0x8 10.--11. "EVNT_BUS5,Status bits showing the PULSAR CPU0 EVNT 5 multi bit error counter." "0,1,2,3" newline bitfld.long 0x8 8.--9. "EVNT_BUS4,Status bits showing the PULSAR CPU0 EVNT 4 multi bit error counter." "0,1,2,3" bitfld.long 0x8 6.--7. "EVNT_BUS3,Status bits showing the PULSAR CPU0 EVNT 3 multi bit error counter." "0,1,2,3" newline bitfld.long 0x8 4.--5. "EVNT_BUS2,Status bits showing the PULSAR CPU0 EVNT 2 multi bit error counter." "0,1,2,3" bitfld.long 0x8 2.--3. "EVNT_BUS1,Status bits showing the PULSAR CPU0 EVNT 1 multi bit error counter." "0,1,2,3" newline bitfld.long 0x8 0.--1. "EVNT_BUS0,Status bits showing the PULSAR CPU0 EVNT 0 multi bit error counter." "0,1,2,3" line.long 0xC "EVNT_BUS__VBUSP__MMRS_PULSAR_CPU1_EVNT_BUS_MB_ERR_CNT_STATUS,Status bits showing the PULSAR CPU1 EVNT_BUS multi bit error counters" bitfld.long 0xC 12.--13. "EVNT_BUS6,Status bits showing the PULSAR CPU1 EVNT 6 multi bit error counter." "0,1,2,3" bitfld.long 0xC 10.--11. "EVNT_BUS5,Status bits showing the PULSAR CPU1 EVNT 5 multi bit error counter." "0,1,2,3" newline bitfld.long 0xC 8.--9. "EVNT_BUS4,Status bits showing the PULSAR CPU1 EVNT 4 multi bit error counter." "0,1,2,3" bitfld.long 0xC 6.--7. "EVNT_BUS3,Status bits showing the PULSAR CPU1 EVNT 3 multi bit error counter." "0,1,2,3" newline bitfld.long 0xC 4.--5. "EVNT_BUS2,Status bits showing the PULSAR CPU1 EVNT 2 multi bit error counter." "0,1,2,3" bitfld.long 0xC 2.--3. "EVNT_BUS1,Status bits showing the PULSAR CPU1 EVNT 1 multi bit error counter." "0,1,2,3" newline bitfld.long 0xC 0.--1. "EVNT_BUS0,Status bits showing the PULSAR CPU1 EVNT 0 multi bit error counter." "0,1,2,3" line.long 0x10 "EVNT_BUS__VBUSP__MMRS_PULSAR_EVNT_BUS_ESM_STATUS,ESM status bits for the PULSAR EVNT BUS" bitfld.long 0x10 3. "CPU1_MULTIPLE_BIT_ERROR,ESM status of CPU1 multiple bit errors on EVNT BUS" "0,1" bitfld.long 0x10 2. "CPU1_SINGLE_BIT_ERROR,ESM status of CPU1 single bit errors on EVNT BUS" "0,1" newline bitfld.long 0x10 1. "CPU0_MULTIPLE_BIT_ERROR,ESM status of CPU0 multiple bit errors on EVNT BUS" "0,1" bitfld.long 0x10 0. "CPU0_SINGLE_BIT_ERROR,ESM status of CPU0 single bit errors on EVNT BUS" "0,1" rgroup.long 0x18++0xF line.long 0x0 "EVNT_BUS__VBUSP__MMRS_PULSAR_EVNT_BUS_ESM_SET,SET the PULSAR EVNT BUS ESM events" bitfld.long 0x0 3. "CPU1_MULTIPLE_BIT_ERROR,SET CPU1 multiple bit errors ESM event" "0,1" bitfld.long 0x0 2. "CPU1_SINGLE_BIT_ERROR,SET CPU1 single bit errors ESM event" "0,1" newline bitfld.long 0x0 1. "CPU0_MULTIPLE_BIT_ERROR,SET CPU0 multiple bit error ESM event" "0,1" bitfld.long 0x0 0. "CPU0_SINGLE_BIT_ERROR,SET CPU0 single bit error ESM event" "0,1" line.long 0x4 "EVNT_BUS__VBUSP__MMRS_PULSAR_EVNT_BUS_ESM_CLR,RESET the PULSAR EVNT BUS ESM events" bitfld.long 0x4 31. "CPU1_EB6_MULTIPLE_BIT_ERROR,Decrement CPU1 Event Bus 31 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 30. "CPU1_EB5_MULTIPLE_BIT_ERROR,Decrement CPU1 Event Bus 30 MULTIPLE BIT Error Counter" "0,1" newline bitfld.long 0x4 29. "CPU1_EB4_MULTIPLE_BIT_ERROR,Decrement CPU1 Event Bus 29 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 28. "CPU1_EB3_MULTIPLE_BIT_ERROR,Decrement CPU1 Event Bus 28 MULTIPLE BIT Error Counter" "0,1" newline bitfld.long 0x4 27. "CPU1_EB2_MULTIPLE_BIT_ERROR,Decrement CPU1 Event Bus 27 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 26. "CPU1_EB1_MULTIPLE_BIT_ERROR,Decrement CPU1 Event Bus 26 MULTIPLE BIT Error Counter" "0,1" newline bitfld.long 0x4 25. "CPU1_EB0_MULTIPLE_BIT_ERROR,Decrement CPU1 Event Bus 25 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 24. "CPU1_EB8_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 24 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 23. "CPU1_EB7_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 23 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 22. "CPU1_EB6_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 22 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 21. "CPU1_EB5_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 21 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 20. "CPU1_EB4_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 20 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 19. "CPU1_EB3_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 19 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 18. "CPU1_EB2_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 18 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 17. "CPU1_EB1_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 17 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 16. "CPU1_EB0_SINGLE_BIT_ERROR,Decrement CPU1 Event Bus 16 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 15. "CPU0_EB6_MULTIPLE_BIT_ERROR,Decrement CPU0 Event Bus 15 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 14. "CPU0_EB5_MULTIPLE_BIT_ERROR,Decrement CPU0 Event Bus 14 MULTIPLE BIT Error Counter" "0,1" newline bitfld.long 0x4 13. "CPU0_EB4_MULTIPLE_BIT_ERROR,Decrement CPU0 Event Bus 13 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 12. "CPU0_EB3_MULTIPLE_BIT_ERROR,Decrement CPU0 Event Bus 12 MULTIPLE BIT Error Counter" "0,1" newline bitfld.long 0x4 11. "CPU0_EB2_MULTIPLE_BIT_ERROR,Decrement CPU0 Event Bus 11 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 10. "CPU0_EB1_MULTIPLE_BIT_ERROR,Decrement CPU0 Event Bus 10 MULTIPLE BIT Error Counter" "0,1" newline bitfld.long 0x4 9. "CPU0_EB0_MULTIPLE_BIT_ERROR,Decrement CPU0 Event Bus 9 MULTIPLE BIT Error Counter" "0,1" bitfld.long 0x4 8. "CPU0_EB8_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 8 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 7. "CPU0_EB7_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 7 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 6. "CPU0_EB6_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 6 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 5. "CPU0_EB5_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 5 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 4. "CPU0_EB4_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 4 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 3. "CPU0_EB3_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 3 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 2. "CPU0_EB2_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 2 SINGLE BIT Error Counter" "0,1" newline bitfld.long 0x4 1. "CPU0_EB1_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 1 SINGLE BIT Error Counter" "0,1" bitfld.long 0x4 0. "CPU0_EB0_SINGLE_BIT_ERROR,Decrement CPU0 Event Bus 0 SINGLE BIT Error Counter" "0,1" line.long 0x8 "EVNT_BUS__VBUSP__MMRS_PULSAR_EVNT_BUS_MASK_ESM_SET,MASK the PULSAR EVNT BUS ESM events" bitfld.long 0x8 3. "CPU1_MULTIPLE_BIT_ERROR,MASK CPU1 multiple bit errors ESM event" "0,1" bitfld.long 0x8 2. "CPU1_SINGLE_BIT_ERROR,MASK CPU1 single bit errors ESM event" "0,1" newline bitfld.long 0x8 1. "CPU0_MULTIPLE_BIT_ERROR,MASK CPU0 multiple bit error ESM event" "0,1" bitfld.long 0x8 0. "CPU0_SINGLE_BIT_ERROR,MASK CPU0 single bit error ESM event" "0,1" line.long 0xC "EVNT_BUS__VBUSP__MMRS_PULSAR_EVNT_BUS_MASK_ESM_CLR,UNMASK the PULSAR EVNT BUS ESM events" bitfld.long 0xC 3. "CPU1_MULTIPLE_BIT_ERROR,UNMASK CPU1 multiple bit errors ESM event" "0,1" bitfld.long 0xC 2. "CPU1_SINGLE_BIT_ERROR,UNMASK CPU1 single bit errors ESM event" "0,1" newline bitfld.long 0xC 1. "CPU0_MULTIPLE_BIT_ERROR,UNMASK CPU0 multiple bit error ESM event" "0,1" bitfld.long 0xC 0. "CPU0_SINGLE_BIT_ERROR,UNMASK CPU0 single bit error ESM event" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "EVNT_BUS__VBUSP__MMRS_PULSAR_EVT_BUS_REVID,Module ID register" hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release" newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" tree.end tree.end tree "R5FSS1_CORE0_ECC_AGGR_CORE0_ECC_AGGR (R5FSS1_CORE0_ECC_AGGR_CORE0_ECC_AGGR)" base ad:0x2A69000 rgroup.long 0x0++0x3 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "CPU0_ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_periph_mst_ramecc_pend" "0,1" newline bitfld.long 0x4 30. "CPU0_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 29. "CPU0_AXI2VBUSM_MEM_MST_RAMECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_mem_mst_ramecc_pend" "0,1" newline bitfld.long 0x4 28. "CPU0_VBUSM2AXI_EDC_PEND,Interrupt Pending Status for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x4 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "B1TCM0_BANK1_PEND,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM0_BANK0_PEND,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x4 24. "B0TCM0_BANK1_PEND,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM0_BANK0_PEND,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x4 22. "ATCM0_BANK1_PEND,Interrupt Pending Status for atcm0_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM0_BANK0_PEND,Interrupt Pending Status for atcm0_bank0_pend" "0,1" newline bitfld.long 0x4 20. "CPU0_DDATA_RAM7_PEND,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_DDATA_RAM6_PEND,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x4 18. "CPU0_DDATA_RAM5_PEND,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_DDATA_RAM4_PEND,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x4 16. "CPU0_DDATA_RAM3_PEND,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_DDATA_RAM2_PEND,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x4 14. "CPU0_DDATA_RAM1_PEND,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_DDATA_RAM0_PEND,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x4 12. "CPU0_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_DTAG_RAM3_PEND,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x4 10. "CPU0_DTAG_RAM2_PEND,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_DTAG_RAM1_PEND,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x4 8. "CPU0_DTAG_RAM0_PEND,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_IDATA_BANK3_PEND,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x4 6. "CPU0_IDATA_BANK2_PEND,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_IDATA_BANK1_PEND,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x4 4. "CPU0_IDATA_BANK0_PEND,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_ITAG_RAM3_PEND,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x4 2. "CPU0_ITAG_RAM2_PEND,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_ITAG_RAM1_PEND,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_ITAG_RAM0_PEND,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1" line.long 0x8 "CPU0_ECC_AGGR__CFG__REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 3. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x8 2. "SCRP_EDC_PEND,Interrupt Pending Status for scrp_edc_pend" "0,1" newline bitfld.long 0x8 1. "CPU0_AHB2VBUSP_EDC_PEND,Interrupt Pending Status for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x8 0. "CPU0_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x80++0x7 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_periph_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "CPU0_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU0_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_mem_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "CPU0_VBUSM2AXI_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1" line.long 0x4 "CPU0_ECC_AGGR__CFG__REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 3. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x4 2. "SCRP_EDC_ENABLE_SET,Interrupt Enable Set Register for scrp_edc_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_AHB2VBUSP_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_periph_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "CPU0_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU0_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_mem_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "CPU0_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram0_pend" "0,1" line.long 0x4 "CPU0_ECC_AGGR__CFG__REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 3. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x4 2. "SCRP_EDC_ENABLE_CLR,Interrupt Enable Clear Register for scrp_edc_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x13C++0xB line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "CPU0_ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_periph_mst_ramecc_pend" "0,1" newline bitfld.long 0x4 30. "CPU0_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 29. "CPU0_AXI2VBUSM_MEM_MST_RAMECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_mem_mst_ramecc_pend" "0,1" newline bitfld.long 0x4 28. "CPU0_VBUSM2AXI_EDC_PEND,Interrupt Pending Status for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x4 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "B1TCM0_BANK1_PEND,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM0_BANK0_PEND,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x4 24. "B0TCM0_BANK1_PEND,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM0_BANK0_PEND,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x4 22. "ATCM0_BANK1_PEND,Interrupt Pending Status for atcm0_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM0_BANK0_PEND,Interrupt Pending Status for atcm0_bank0_pend" "0,1" newline bitfld.long 0x4 20. "CPU0_DDATA_RAM7_PEND,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_DDATA_RAM6_PEND,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x4 18. "CPU0_DDATA_RAM5_PEND,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_DDATA_RAM4_PEND,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x4 16. "CPU0_DDATA_RAM3_PEND,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_DDATA_RAM2_PEND,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x4 14. "CPU0_DDATA_RAM1_PEND,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_DDATA_RAM0_PEND,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x4 12. "CPU0_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_DTAG_RAM3_PEND,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x4 10. "CPU0_DTAG_RAM2_PEND,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_DTAG_RAM1_PEND,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x4 8. "CPU0_DTAG_RAM0_PEND,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_IDATA_BANK3_PEND,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x4 6. "CPU0_IDATA_BANK2_PEND,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_IDATA_BANK1_PEND,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x4 4. "CPU0_IDATA_BANK0_PEND,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_ITAG_RAM3_PEND,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x4 2. "CPU0_ITAG_RAM2_PEND,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_ITAG_RAM1_PEND,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_ITAG_RAM0_PEND,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1" line.long 0x8 "CPU0_ECC_AGGR__CFG__REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 3. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x8 2. "SCRP_EDC_PEND,Interrupt Pending Status for scrp_edc_pend" "0,1" newline bitfld.long 0x8 1. "CPU0_AHB2VBUSP_EDC_PEND,Interrupt Pending Status for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x8 0. "CPU0_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu0_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x180++0x7 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_periph_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "CPU0_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU0_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_mem_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "CPU0_VBUSM2AXI_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1" line.long 0x4 "CPU0_ECC_AGGR__CFG__REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 3. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x4 2. "SCRP_EDC_ENABLE_SET,Interrupt Enable Set Register for scrp_edc_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_AHB2VBUSP_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_periph_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "CPU0_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU0_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_mem_mst_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "CPU0_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram0_pend" "0,1" line.long 0x4 "CPU0_ECC_AGGR__CFG__REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 3. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x4 2. "SCRP_EDC_ENABLE_CLR,Interrupt Enable Clear Register for scrp_edc_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "CPU0_ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "CPU0_ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "CPU0_ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "CPU0_ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "R5FSS1_CORE1_ECC_AGGR_CORE1_ECC_AGGR (R5FSS1_CORE1_ECC_AGGR_CORE1_ECC_AGGR)" base ad:0x5B30000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_periph_mst_ramecc_pend" "0,1" bitfld.long 0x4 30. "CPU1_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 29. "CPU1_AXI2VBUSM_MEM_MST_RAMECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_mem_mst_ramecc_pend" "0,1" bitfld.long 0x4 28. "CPU1_VBUSM2AXI_EDC_PEND,Interrupt Pending Status for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x4 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x4 26. "B1TCM1_BANK1_PEND,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM1_BANK0_PEND,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1" bitfld.long 0x4 24. "B0TCM1_BANK1_PEND,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM1_BANK0_PEND,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1" bitfld.long 0x4 22. "ATCM1_BANK1_PEND,Interrupt Pending Status for atcm1_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM1_BANK0_PEND,Interrupt Pending Status for atcm1_bank0_pend" "0,1" bitfld.long 0x4 20. "CPU1_DDATA_RAM7_PEND,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_DDATA_RAM6_PEND,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x4 18. "CPU1_DDATA_RAM5_PEND,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_DDATA_RAM4_PEND,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x4 16. "CPU1_DDATA_RAM3_PEND,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_DDATA_RAM2_PEND,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x4 14. "CPU1_DDATA_RAM1_PEND,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_DDATA_RAM0_PEND,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x4 12. "CPU1_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_DTAG_RAM3_PEND,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x4 10. "CPU1_DTAG_RAM2_PEND,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_DTAG_RAM1_PEND,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x4 8. "CPU1_DTAG_RAM0_PEND,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_IDATA_BANK3_PEND,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x4 6. "CPU1_IDATA_BANK2_PEND,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_IDATA_BANK1_PEND,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x4 4. "CPU1_IDATA_BANK0_PEND,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_ITAG_RAM3_PEND,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x4 2. "CPU1_ITAG_RAM2_PEND,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_ITAG_RAM1_PEND,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x4 0. "CPU1_ITAG_RAM0_PEND,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1" line.long 0x8 "REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 2. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" bitfld.long 0x8 1. "CPU1_AHB2VBUSP_EDC_PEND,Interrupt Pending Status for cpu1_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x8 0. "CPU1_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x80++0x7 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_periph_mst_ramecc_pend" "0,1" bitfld.long 0x0 30. "CPU1_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU1_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_mem_mst_ramecc_pend" "0,1" bitfld.long 0x0 28. "CPU1_VBUSM2AXI_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1" line.long 0x4 "REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 2. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" bitfld.long 0x4 1. "CPU1_AHB2VBUSP_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU1_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_periph_mst_ramecc_pend" "0,1" bitfld.long 0x0 30. "CPU1_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU1_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_mem_mst_ramecc_pend" "0,1" bitfld.long 0x0 28. "CPU1_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram0_pend" "0,1" line.long 0x4 "REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 2. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" bitfld.long 0x4 1. "CPU1_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU1_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x13C++0xB line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_periph_mst_ramecc_pend" "0,1" bitfld.long 0x4 30. "CPU1_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 29. "CPU1_AXI2VBUSM_MEM_MST_RAMECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_mem_mst_ramecc_pend" "0,1" bitfld.long 0x4 28. "CPU1_VBUSM2AXI_EDC_PEND,Interrupt Pending Status for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x4 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x4 26. "B1TCM1_BANK1_PEND,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM1_BANK0_PEND,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1" bitfld.long 0x4 24. "B0TCM1_BANK1_PEND,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM1_BANK0_PEND,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1" bitfld.long 0x4 22. "ATCM1_BANK1_PEND,Interrupt Pending Status for atcm1_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM1_BANK0_PEND,Interrupt Pending Status for atcm1_bank0_pend" "0,1" bitfld.long 0x4 20. "CPU1_DDATA_RAM7_PEND,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_DDATA_RAM6_PEND,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x4 18. "CPU1_DDATA_RAM5_PEND,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_DDATA_RAM4_PEND,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x4 16. "CPU1_DDATA_RAM3_PEND,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_DDATA_RAM2_PEND,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x4 14. "CPU1_DDATA_RAM1_PEND,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_DDATA_RAM0_PEND,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x4 12. "CPU1_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_DTAG_RAM3_PEND,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x4 10. "CPU1_DTAG_RAM2_PEND,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_DTAG_RAM1_PEND,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x4 8. "CPU1_DTAG_RAM0_PEND,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_IDATA_BANK3_PEND,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x4 6. "CPU1_IDATA_BANK2_PEND,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_IDATA_BANK1_PEND,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x4 4. "CPU1_IDATA_BANK0_PEND,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_ITAG_RAM3_PEND,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x4 2. "CPU1_ITAG_RAM2_PEND,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_ITAG_RAM1_PEND,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x4 0. "CPU1_ITAG_RAM0_PEND,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1" line.long 0x8 "REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 2. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" bitfld.long 0x8 1. "CPU1_AHB2VBUSP_EDC_PEND,Interrupt Pending Status for cpu1_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x8 0. "CPU1_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for cpu1_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x180++0x7 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_periph_mst_ramecc_pend" "0,1" bitfld.long 0x0 30. "CPU1_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU1_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_mem_mst_ramecc_pend" "0,1" bitfld.long 0x0 28. "CPU1_VBUSM2AXI_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1" line.long 0x4 "REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 2. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" bitfld.long 0x4 1. "CPU1_AHB2VBUSP_EDC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU1_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_periph_mst_ramecc_pend" "0,1" bitfld.long 0x0 30. "CPU1_AXI2VBUSM_MEM_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_mem_mst_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 29. "CPU1_AXI2VBUSM_MEM_MST_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_mem_mst_ramecc_pend" "0,1" bitfld.long 0x0 28. "CPU1_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram0_pend" "0,1" line.long 0x4 "REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 2. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" bitfld.long 0x4 1. "CPU1_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU1_AXI2VBUSM_PERIPH_MST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_axi2vbusm_periph_mst_edc_ctrl_busecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree.end tree "RTI" base ad:0x0 tree "RTI0_CFG (RTI0_CFG)" base ad:0x2200000 rgroup.long 0x0++0x1B line.long 0x0 "CFG_GCTRL," hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.." bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode" newline bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" line.long 0x4 "CFG_TBCTRL," bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme" line.long 0x8 "CFG_CAPCTRL," bitfld.long 0x8 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." bitfld.long 0x8 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "CFG_COMPCTRL," bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" newline bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" line.long 0x10 "CFG_FRC0," hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register." line.long 0x14 "CFG_UC0," hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x18 "CFG_CPUC0," hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." rgroup.long 0x20++0x7 line.long 0x0 "CFG_CAFRC0," hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event" line.long 0x4 "CFG_CAUC0," hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.." rgroup.long 0x30++0xB line.long 0x0 "CFG_FRC1," hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register." line.long 0x4 "CFG_UC1," hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x8 "CFG_CPUC1," hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." rgroup.long 0x40++0x7 line.long 0x0 "CFG_CAFRC1," hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event" line.long 0x4 "CFG_CAUC1," hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.." rgroup.long 0x50++0x27 line.long 0x0 "CFG_COMP0," hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x4 "CFG_UDCP0," hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x8 "CFG_COMP1," hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0xC "CFG_UDCP1," hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x10 "CFG_COMP2," hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x14 "CFG_UDCP2," hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x18 "CFG_COMP3," hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x1C "CFG_UDCP3," hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x20 "CFG_TBLCOMP," hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.." line.long 0x24 "CFG_TBHCOMP," hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.." rgroup.long 0x80++0xB line.long 0x0 "CFG_SETINT," bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" line.long 0x4 "CFG_CLEARINT," bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" line.long 0x8 "CFG_INTFLAG," bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" rgroup.long 0x90++0xF line.long 0x0 "CFG_DWDCTRL," hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.." line.long 0x4 "CFG_DWDPRLD," hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.." line.long 0x8 "CFG_WDSTATUS," bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0" line.long 0xC "CFG_WDKEY," hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.." rgroup.long 0xA0++0x3 line.long 0x0 "CFG_DWDCNTR," hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be generated in 1 second. User and.." rgroup.long 0xA4++0x1B line.long 0x0 "CFG_WWDRXNCTRL," hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration or if the watchdog is not.." line.long 0x4 "CFG_WWDSIZECTRL," hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read) privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).." line.long 0x8 "CFG_INTCLRENABLE," hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.." newline hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.." line.long 0xC "CFG_COMP0CLR," hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared. User and privilege.." line.long 0x10 "CFG_COMP1CLR," hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared. User and privilege.." line.long 0x14 "CFG_COMP2CLR," hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared. User and privilege.." line.long 0x18 "CFG_COMP3CLR," hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared. User and privilege.." tree.end tree "RTI1_CFG (RTI1_CFG)" base ad:0x2210000 rgroup.long 0x0++0x1B line.long 0x0 "CFG_GCTRL," hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.." bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode" newline bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" line.long 0x4 "CFG_TBCTRL," bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme" line.long 0x8 "CFG_CAPCTRL," bitfld.long 0x8 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." bitfld.long 0x8 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "CFG_COMPCTRL," bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" newline bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" line.long 0x10 "CFG_FRC0," hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register." line.long 0x14 "CFG_UC0," hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x18 "CFG_CPUC0," hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." rgroup.long 0x20++0x7 line.long 0x0 "CFG_CAFRC0," hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event" line.long 0x4 "CFG_CAUC0," hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.." rgroup.long 0x30++0xB line.long 0x0 "CFG_FRC1," hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register." line.long 0x4 "CFG_UC1," hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x8 "CFG_CPUC1," hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." rgroup.long 0x40++0x7 line.long 0x0 "CFG_CAFRC1," hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event" line.long 0x4 "CFG_CAUC1," hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.." rgroup.long 0x50++0x27 line.long 0x0 "CFG_COMP0," hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x4 "CFG_UDCP0," hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x8 "CFG_COMP1," hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0xC "CFG_UDCP1," hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x10 "CFG_COMP2," hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x14 "CFG_UDCP2," hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x18 "CFG_COMP3," hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x1C "CFG_UDCP3," hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x20 "CFG_TBLCOMP," hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.." line.long 0x24 "CFG_TBHCOMP," hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.." rgroup.long 0x80++0xB line.long 0x0 "CFG_SETINT," bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" line.long 0x4 "CFG_CLEARINT," bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" line.long 0x8 "CFG_INTFLAG," bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" rgroup.long 0x90++0xF line.long 0x0 "CFG_DWDCTRL," hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.." line.long 0x4 "CFG_DWDPRLD," hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.." line.long 0x8 "CFG_WDSTATUS," bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0" line.long 0xC "CFG_WDKEY," hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.." rgroup.long 0xA0++0x3 line.long 0x0 "CFG_DWDCNTR," hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be generated in 1 second. User and.." rgroup.long 0xA4++0x1B line.long 0x0 "CFG_WWDRXNCTRL," hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration or if the watchdog is not.." line.long 0x4 "CFG_WWDSIZECTRL," hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read) privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).." line.long 0x8 "CFG_INTCLRENABLE," hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.." newline hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.." line.long 0xC "CFG_COMP0CLR," hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared. User and privilege.." line.long 0x10 "CFG_COMP1CLR," hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared. User and privilege.." line.long 0x14 "CFG_COMP2CLR," hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared. User and privilege.." line.long 0x18 "CFG_COMP3CLR," hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared. User and privilege.." tree.end tree "RTI15_CFG (RTI15_CFG)" base ad:0x22F0000 rgroup.long 0x0++0x1B line.long 0x0 "CFG_GCTRL," hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.." bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode" newline bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" line.long 0x4 "CFG_TBCTRL," bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme" line.long 0x8 "CFG_CAPCTRL," bitfld.long 0x8 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." bitfld.long 0x8 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "CFG_COMPCTRL," bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" newline bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" line.long 0x10 "CFG_FRC0," hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register." line.long 0x14 "CFG_UC0," hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x18 "CFG_CPUC0," hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." rgroup.long 0x20++0x7 line.long 0x0 "CFG_CAFRC0," hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event" line.long 0x4 "CFG_CAUC0," hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.." rgroup.long 0x30++0xB line.long 0x0 "CFG_FRC1," hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register." line.long 0x4 "CFG_UC1," hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x8 "CFG_CPUC1," hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." rgroup.long 0x40++0x7 line.long 0x0 "CFG_CAFRC1," hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event" line.long 0x4 "CFG_CAUC1," hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.." rgroup.long 0x50++0x27 line.long 0x0 "CFG_COMP0," hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x4 "CFG_UDCP0," hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x8 "CFG_COMP1," hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0xC "CFG_UDCP1," hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x10 "CFG_COMP2," hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x14 "CFG_UDCP2," hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x18 "CFG_COMP3," hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x1C "CFG_UDCP3," hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x20 "CFG_TBLCOMP," hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.." line.long 0x24 "CFG_TBHCOMP," hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.." rgroup.long 0x80++0xB line.long 0x0 "CFG_SETINT," bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" line.long 0x4 "CFG_CLEARINT," bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" line.long 0x8 "CFG_INTFLAG," bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" rgroup.long 0x90++0xF line.long 0x0 "CFG_DWDCTRL," hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.." line.long 0x4 "CFG_DWDPRLD," hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.." line.long 0x8 "CFG_WDSTATUS," bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0" line.long 0xC "CFG_WDKEY," hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.." rgroup.long 0xA0++0x3 line.long 0x0 "CFG_DWDCNTR," hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be generated in 1 second. User and.." rgroup.long 0xA4++0x1B line.long 0x0 "CFG_WWDRXNCTRL," hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration or if the watchdog is not.." line.long 0x4 "CFG_WWDSIZECTRL," hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read) privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).." line.long 0x8 "CFG_INTCLRENABLE," hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.." newline hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.." line.long 0xC "CFG_COMP0CLR," hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared. User and privilege.." line.long 0x10 "CFG_COMP1CLR," hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared. User and privilege.." line.long 0x14 "CFG_COMP2CLR," hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared. User and privilege.." line.long 0x18 "CFG_COMP3CLR," hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared. User and privilege.." tree.end tree "RTI16_CFG (RTI16_CFG)" base ad:0x2300000 rgroup.long 0x0++0x1B line.long 0x0 "CFG_GCTRL," hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.." bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode" newline bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" line.long 0x4 "CFG_TBCTRL," bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme" line.long 0x8 "CFG_CAPCTRL," bitfld.long 0x8 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." bitfld.long 0x8 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "CFG_COMPCTRL," bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" newline bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" line.long 0x10 "CFG_FRC0," hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register." line.long 0x14 "CFG_UC0," hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x18 "CFG_CPUC0," hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." rgroup.long 0x20++0x7 line.long 0x0 "CFG_CAFRC0," hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event" line.long 0x4 "CFG_CAUC0," hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.." rgroup.long 0x30++0xB line.long 0x0 "CFG_FRC1," hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register." line.long 0x4 "CFG_UC1," hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x8 "CFG_CPUC1," hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." rgroup.long 0x40++0x7 line.long 0x0 "CFG_CAFRC1," hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event" line.long 0x4 "CFG_CAUC1," hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.." rgroup.long 0x50++0x27 line.long 0x0 "CFG_COMP0," hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x4 "CFG_UDCP0," hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x8 "CFG_COMP1," hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0xC "CFG_UDCP1," hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x10 "CFG_COMP2," hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x14 "CFG_UDCP2," hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x18 "CFG_COMP3," hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x1C "CFG_UDCP3," hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x20 "CFG_TBLCOMP," hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.." line.long 0x24 "CFG_TBHCOMP," hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.." rgroup.long 0x80++0xB line.long 0x0 "CFG_SETINT," bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" line.long 0x4 "CFG_CLEARINT," bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" line.long 0x8 "CFG_INTFLAG," bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" rgroup.long 0x90++0xF line.long 0x0 "CFG_DWDCTRL," hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.." line.long 0x4 "CFG_DWDPRLD," hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.." line.long 0x8 "CFG_WDSTATUS," bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0" line.long 0xC "CFG_WDKEY," hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.." rgroup.long 0xA0++0x3 line.long 0x0 "CFG_DWDCNTR," hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be generated in 1 second. User and.." rgroup.long 0xA4++0x1B line.long 0x0 "CFG_WWDRXNCTRL," hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration or if the watchdog is not.." line.long 0x4 "CFG_WWDSIZECTRL," hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read) privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).." line.long 0x8 "CFG_INTCLRENABLE," hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.." newline hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.." line.long 0xC "CFG_COMP0CLR," hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared. User and privilege.." line.long 0x10 "CFG_COMP1CLR," hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared. User and privilege.." line.long 0x14 "CFG_COMP2CLR," hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared. User and privilege.." line.long 0x18 "CFG_COMP3CLR," hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared. User and privilege.." tree.end tree "RTI17_CFG (RTI17_CFG)" base ad:0x2310000 rgroup.long 0x0++0x1B line.long 0x0 "CFG_GCTRL," hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.." bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode" newline bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" line.long 0x4 "CFG_TBCTRL," bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme" line.long 0x8 "CFG_CAPCTRL," bitfld.long 0x8 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." bitfld.long 0x8 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "CFG_COMPCTRL," bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" newline bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" line.long 0x10 "CFG_FRC0," hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register." line.long 0x14 "CFG_UC0," hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x18 "CFG_CPUC0," hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." rgroup.long 0x20++0x7 line.long 0x0 "CFG_CAFRC0," hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event" line.long 0x4 "CFG_CAUC0," hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.." rgroup.long 0x30++0xB line.long 0x0 "CFG_FRC1," hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register." line.long 0x4 "CFG_UC1," hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x8 "CFG_CPUC1," hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." rgroup.long 0x40++0x7 line.long 0x0 "CFG_CAFRC1," hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event" line.long 0x4 "CFG_CAUC1," hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.." rgroup.long 0x50++0x27 line.long 0x0 "CFG_COMP0," hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x4 "CFG_UDCP0," hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x8 "CFG_COMP1," hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0xC "CFG_UDCP1," hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x10 "CFG_COMP2," hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x14 "CFG_UDCP2," hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x18 "CFG_COMP3," hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x1C "CFG_UDCP3," hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x20 "CFG_TBLCOMP," hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.." line.long 0x24 "CFG_TBHCOMP," hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.." rgroup.long 0x80++0xB line.long 0x0 "CFG_SETINT," bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" line.long 0x4 "CFG_CLEARINT," bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" line.long 0x8 "CFG_INTFLAG," bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" rgroup.long 0x90++0xF line.long 0x0 "CFG_DWDCTRL," hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.." line.long 0x4 "CFG_DWDPRLD," hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.." line.long 0x8 "CFG_WDSTATUS," bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0" line.long 0xC "CFG_WDKEY," hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.." rgroup.long 0xA0++0x3 line.long 0x0 "CFG_DWDCNTR," hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be generated in 1 second. User and.." rgroup.long 0xA4++0x1B line.long 0x0 "CFG_WWDRXNCTRL," hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration or if the watchdog is not.." line.long 0x4 "CFG_WWDSIZECTRL," hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read) privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).." line.long 0x8 "CFG_INTCLRENABLE," hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.." newline hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.." line.long 0xC "CFG_COMP0CLR," hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared. User and privilege.." line.long 0x10 "CFG_COMP1CLR," hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared. User and privilege.." line.long 0x14 "CFG_COMP2CLR," hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared. User and privilege.." line.long 0x18 "CFG_COMP3CLR," hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared. User and privilege.." tree.end tree "RTI28_CFG (RTI28_CFG)" base ad:0x23C0000 rgroup.long 0x0++0x1B line.long 0x0 "CFG_GCTRL," hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.." bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode" newline bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" line.long 0x4 "CFG_TBCTRL," bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme" line.long 0x8 "CFG_CAPCTRL," bitfld.long 0x8 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." bitfld.long 0x8 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "CFG_COMPCTRL," bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" newline bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" line.long 0x10 "CFG_FRC0," hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register." line.long 0x14 "CFG_UC0," hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x18 "CFG_CPUC0," hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." rgroup.long 0x20++0x7 line.long 0x0 "CFG_CAFRC0," hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event" line.long 0x4 "CFG_CAUC0," hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.." rgroup.long 0x30++0xB line.long 0x0 "CFG_FRC1," hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register." line.long 0x4 "CFG_UC1," hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x8 "CFG_CPUC1," hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." rgroup.long 0x40++0x7 line.long 0x0 "CFG_CAFRC1," hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event" line.long 0x4 "CFG_CAUC1," hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.." rgroup.long 0x50++0x27 line.long 0x0 "CFG_COMP0," hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x4 "CFG_UDCP0," hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x8 "CFG_COMP1," hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0xC "CFG_UDCP1," hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x10 "CFG_COMP2," hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x14 "CFG_UDCP2," hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x18 "CFG_COMP3," hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x1C "CFG_UDCP3," hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x20 "CFG_TBLCOMP," hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.." line.long 0x24 "CFG_TBHCOMP," hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.." rgroup.long 0x80++0xB line.long 0x0 "CFG_SETINT," bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" line.long 0x4 "CFG_CLEARINT," bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" line.long 0x8 "CFG_INTFLAG," bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" rgroup.long 0x90++0xF line.long 0x0 "CFG_DWDCTRL," hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.." line.long 0x4 "CFG_DWDPRLD," hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.." line.long 0x8 "CFG_WDSTATUS," bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0" line.long 0xC "CFG_WDKEY," hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.." rgroup.long 0xA0++0x3 line.long 0x0 "CFG_DWDCNTR," hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be generated in 1 second. User and.." rgroup.long 0xA4++0x1B line.long 0x0 "CFG_WWDRXNCTRL," hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration or if the watchdog is not.." line.long 0x4 "CFG_WWDSIZECTRL," hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read) privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).." line.long 0x8 "CFG_INTCLRENABLE," hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.." newline hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.." line.long 0xC "CFG_COMP0CLR," hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared. User and privilege.." line.long 0x10 "CFG_COMP1CLR," hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared. User and privilege.." line.long 0x14 "CFG_COMP2CLR," hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared. User and privilege.." line.long 0x18 "CFG_COMP3CLR," hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared. User and privilege.." tree.end tree "RTI29_CFG (RTI29_CFG)" base ad:0x23D0000 rgroup.long 0x0++0x1B line.long 0x0 "CFG_GCTRL," hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.." bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode" newline bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" line.long 0x4 "CFG_TBCTRL," bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme" line.long 0x8 "CFG_CAPCTRL," bitfld.long 0x8 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." bitfld.long 0x8 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "CFG_COMPCTRL," bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" newline bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" line.long 0x10 "CFG_FRC0," hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register." line.long 0x14 "CFG_UC0," hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x18 "CFG_CPUC0," hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." rgroup.long 0x20++0x7 line.long 0x0 "CFG_CAFRC0," hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event" line.long 0x4 "CFG_CAUC0," hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.." rgroup.long 0x30++0xB line.long 0x0 "CFG_FRC1," hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register." line.long 0x4 "CFG_UC1," hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x8 "CFG_CPUC1," hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." rgroup.long 0x40++0x7 line.long 0x0 "CFG_CAFRC1," hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event" line.long 0x4 "CFG_CAUC1," hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.." rgroup.long 0x50++0x27 line.long 0x0 "CFG_COMP0," hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x4 "CFG_UDCP0," hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x8 "CFG_COMP1," hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0xC "CFG_UDCP1," hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x10 "CFG_COMP2," hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x14 "CFG_UDCP2," hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x18 "CFG_COMP3," hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x1C "CFG_UDCP3," hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x20 "CFG_TBLCOMP," hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.." line.long 0x24 "CFG_TBHCOMP," hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.." rgroup.long 0x80++0xB line.long 0x0 "CFG_SETINT," bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" line.long 0x4 "CFG_CLEARINT," bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" line.long 0x8 "CFG_INTFLAG," bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" rgroup.long 0x90++0xF line.long 0x0 "CFG_DWDCTRL," hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.." line.long 0x4 "CFG_DWDPRLD," hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.." line.long 0x8 "CFG_WDSTATUS," bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0" line.long 0xC "CFG_WDKEY," hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.." rgroup.long 0xA0++0x3 line.long 0x0 "CFG_DWDCNTR," hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be generated in 1 second. User and.." rgroup.long 0xA4++0x1B line.long 0x0 "CFG_WWDRXNCTRL," hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration or if the watchdog is not.." line.long 0x4 "CFG_WWDSIZECTRL," hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read) privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).." line.long 0x8 "CFG_INTCLRENABLE," hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.." newline hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.." line.long 0xC "CFG_COMP0CLR," hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared. User and privilege.." line.long 0x10 "CFG_COMP1CLR," hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared. User and privilege.." line.long 0x14 "CFG_COMP2CLR," hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared. User and privilege.." line.long 0x18 "CFG_COMP3CLR," hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared. User and privilege.." tree.end tree "RTI30_CFG (RTI30_CFG)" base ad:0x23E0000 rgroup.long 0x0++0x1B line.long 0x0 "CFG_GCTRL," hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.." bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode" newline bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" line.long 0x4 "CFG_TBCTRL," bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme" line.long 0x8 "CFG_CAPCTRL," bitfld.long 0x8 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." bitfld.long 0x8 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "CFG_COMPCTRL," bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" newline bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" line.long 0x10 "CFG_FRC0," hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register." line.long 0x14 "CFG_UC0," hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x18 "CFG_CPUC0," hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." rgroup.long 0x20++0x7 line.long 0x0 "CFG_CAFRC0," hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event" line.long 0x4 "CFG_CAUC0," hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.." rgroup.long 0x30++0xB line.long 0x0 "CFG_FRC1," hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register." line.long 0x4 "CFG_UC1," hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x8 "CFG_CPUC1," hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." rgroup.long 0x40++0x7 line.long 0x0 "CFG_CAFRC1," hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event" line.long 0x4 "CFG_CAUC1," hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.." rgroup.long 0x50++0x27 line.long 0x0 "CFG_COMP0," hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x4 "CFG_UDCP0," hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x8 "CFG_COMP1," hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0xC "CFG_UDCP1," hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x10 "CFG_COMP2," hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x14 "CFG_UDCP2," hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x18 "CFG_COMP3," hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x1C "CFG_UDCP3," hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x20 "CFG_TBLCOMP," hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.." line.long 0x24 "CFG_TBHCOMP," hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.." rgroup.long 0x80++0xB line.long 0x0 "CFG_SETINT," bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" line.long 0x4 "CFG_CLEARINT," bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" line.long 0x8 "CFG_INTFLAG," bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" rgroup.long 0x90++0xF line.long 0x0 "CFG_DWDCTRL," hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.." line.long 0x4 "CFG_DWDPRLD," hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.." line.long 0x8 "CFG_WDSTATUS," bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0" line.long 0xC "CFG_WDKEY," hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.." rgroup.long 0xA0++0x3 line.long 0x0 "CFG_DWDCNTR," hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be generated in 1 second. User and.." rgroup.long 0xA4++0x1B line.long 0x0 "CFG_WWDRXNCTRL," hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration or if the watchdog is not.." line.long 0x4 "CFG_WWDSIZECTRL," hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read) privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).." line.long 0x8 "CFG_INTCLRENABLE," hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.." newline hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.." line.long 0xC "CFG_COMP0CLR," hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared. User and privilege.." line.long 0x10 "CFG_COMP1CLR," hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared. User and privilege.." line.long 0x14 "CFG_COMP2CLR," hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared. User and privilege.." line.long 0x18 "CFG_COMP3CLR," hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared. User and privilege.." tree.end tree "RTI31_CFG (RTI31_CFG)" base ad:0x23F0000 rgroup.long 0x0++0x1B line.long 0x0 "CFG_GCTRL," hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.." bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode" newline bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" line.long 0x4 "CFG_TBCTRL," bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme" line.long 0x8 "CFG_CAPCTRL," bitfld.long 0x8 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." bitfld.long 0x8 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "CFG_COMPCTRL," bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" newline bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" line.long 0x10 "CFG_FRC0," hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register." line.long 0x14 "CFG_UC0," hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x18 "CFG_CPUC0," hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." rgroup.long 0x20++0x7 line.long 0x0 "CFG_CAFRC0," hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event" line.long 0x4 "CFG_CAUC0," hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.." rgroup.long 0x30++0xB line.long 0x0 "CFG_FRC1," hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register." line.long 0x4 "CFG_UC1," hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x8 "CFG_CPUC1," hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." rgroup.long 0x40++0x7 line.long 0x0 "CFG_CAFRC1," hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event" line.long 0x4 "CFG_CAUC1," hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.." rgroup.long 0x50++0x27 line.long 0x0 "CFG_COMP0," hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x4 "CFG_UDCP0," hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x8 "CFG_COMP1," hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0xC "CFG_UDCP1," hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x10 "CFG_COMP2," hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x14 "CFG_UDCP2," hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x18 "CFG_COMP3," hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x1C "CFG_UDCP3," hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x20 "CFG_TBLCOMP," hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.." line.long 0x24 "CFG_TBHCOMP," hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.." rgroup.long 0x80++0xB line.long 0x0 "CFG_SETINT," bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" line.long 0x4 "CFG_CLEARINT," bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" line.long 0x8 "CFG_INTFLAG," bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" rgroup.long 0x90++0xF line.long 0x0 "CFG_DWDCTRL," hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.." line.long 0x4 "CFG_DWDPRLD," hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.." line.long 0x8 "CFG_WDSTATUS," bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0" line.long 0xC "CFG_WDKEY," hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.." rgroup.long 0xA0++0x3 line.long 0x0 "CFG_DWDCNTR," hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be generated in 1 second. User and.." rgroup.long 0xA4++0x1B line.long 0x0 "CFG_WWDRXNCTRL," hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration or if the watchdog is not.." line.long 0x4 "CFG_WWDSIZECTRL," hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read) privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).." line.long 0x8 "CFG_INTCLRENABLE," hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.." newline hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.." line.long 0xC "CFG_COMP0CLR," hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared. User and privilege.." line.long 0x10 "CFG_COMP1CLR," hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared. User and privilege.." line.long 0x14 "CFG_COMP2CLR," hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared. User and privilege.." line.long 0x18 "CFG_COMP3CLR," hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared. User and privilege.." tree.end tree.end tree "SEC_MMR0" base ad:0x0 tree "SEC_MMR0_BOOT_CTRL (SEC_MMR0_BOOT_CTRL)" base ad:0x45A40000 rgroup.long 0x0++0x3 line.long 0x0 "CFG0_PID," hexmask.long.word 0x0 16.--31. 1. "PID_MSB16," newline hexmask.long.byte 0x0 11.--15. 1. "PID_MISC," newline bitfld.long 0x0 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "PID_CUSTOM," "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR," rgroup.long 0x20++0x3 line.long 0x0 "CFG0_CLSTR0_DEF," bitfld.long 0x0 16.--18. "CLSTR0_DEF_CORE_NUM,Number of cores in cluster 001 - Single Core 010 - Dual Core 100 - Quad Core" "?,1: Single Core 010,?,?,?,?,?,?" newline hexmask.long.byte 0x0 8.--15. 1. "CLSTR0_DEF_DSP_CORE_TYPE,DSP core type configuration Field values (others are reserved): 8'h00 - C7x 8'h01 - C6x 8'hFF - Not DSP" newline hexmask.long.byte 0x0 0.--7. 1. "CLSTR0_DEF_ARM_CORE_TYPE,ARM core type configuration Field values (others are reserved): 8'h00 - A53 8'h01 - A57 8'h10 - R5 8'hFF - Not ARM" rgroup.long 0x40++0x3 line.long 0x0 "CFG0_CLSTR0_CFG," hexmask.long 0x0 5.--31. 1. "CLSTR0_CFG_CLSTR_CFG_RSVD,Reserved for future use. Write '0' to ensure compatibility with future devices." newline bitfld.long 0x0 4. "CLSTR0_CFG_MEM_INIT_DIS,Disables SRAM initialization (TCM Cache Tags etc) at reset Initialization must be performed for proper initial ECC initialization. The mem_init_dis value must be selected prior to R5 reset assertion. 1'b0 - Perform memory.." "0: Perform memory initialization 1'b1,?" newline rbitfld.long 0x0 3. "CLSTR0_CFG_LOCKSTEP_EN,Lockstep enable. Indicates if R5 lockstep operation is supported on the device" "0,1" newline bitfld.long 0x0 2. "CLSTR0_CFG_DBG_NO_CLKSTOP,CPU clockstop behavior 0 - CPU clocks stopped and nCLOCKSTOPPED asserted in standby mode 1 - CPU clocks not stopped in standby mode" "0: CPU clocks stopped and nCLOCKSTOPPED asserted in..,?" newline bitfld.long 0x0 1. "CLSTR0_CFG_TEINIT,Exception handling state at reset: 0 - ARM mode 1 - Thumb mode" "0: ARM mode 1,?" newline bitfld.long 0x0 0. "CLSTR0_CFG_LOCKSTEP,When set Core0 and Core1 operate in lockstep mode. Can only be changed if lockstep operation is supported as indicated by CLSTR0_CFG_lockstep_en = 1. If CLSTR0_CFG_lockstep_en = 0 lockstep is not supported this bit will be read.." "0,1" rgroup.long 0x80++0x3 line.long 0x0 "CFG0_CLSTR0_PMCTRL," hexmask.long 0x0 0.--31. 1. "RESERVED,Not used for Pulsar / C66" rgroup.long 0x90++0x3 line.long 0x0 "CFG0_CLSTR0_PMSTAT," hexmask.long 0x0 0.--31. 1. "RESERVED,Not used for Pulsar / C66" rgroup.long 0x100++0x3 line.long 0x0 "CFG0_CLSTR0_CORE0_CFG," bitfld.long 0x0 15. "CLSTR0_CORE0_CFG_NMFI_EN,Enable Core0 Non-Maskable Fast Interrupts" "0,1" newline bitfld.long 0x0 11. "CLSTR0_CORE0_CFG_TCM_RSTBASE,Core0 A/BTCM Reset Base Address Indicator 0 - BTCM located at address 0x0 1 - ATCM located at address 0x0" "0: BTCM located at address 0x0 1,?" newline bitfld.long 0x0 7. "CLSTR0_CORE0_CFG_BTCM_EN,Enable Core0 BTCM RAM at reset" "0,1" newline bitfld.long 0x0 3. "CLSTR0_CORE0_CFG_ATCM_EN,Enable Core0 ATCM RAM at reset" "0,1" rgroup.long 0x110++0x7 line.long 0x0 "CFG0_CLSTR0_CORE0_BOOTVECT_LO," hexmask.long 0x0 7.--31. 1. "CLSTR0_CORE0_BOOTVECT_LO_VECT_ADDR,Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]. Note bits 6:0 of the Vector Table address are always 0." line.long 0x4 "CFG0_CLSTR0_CORE0_BOOTVECT_HI," hexmask.long.word 0x4 0.--15. 1. "CLSTR0_CORE0_BOOTVECT_HI_VECT_ADDR,Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]." rgroup.long 0x120++0x3 line.long 0x0 "CFG0_CLSTR0_CORE0_PMCTRL," bitfld.long 0x0 0. "CLSTR0_CORE0_PMCTRL_CORE_HALT,Halt Core0" "0,1" rgroup.long 0x130++0x3 line.long 0x0 "CFG0_CLSTR0_CORE0_PMSTAT," bitfld.long 0x0 3. "CLSTR0_CORE0_PMSTAT_CLK_GATE,Core0 Clocked stopped due to WFI or WFE state" "0,1" newline bitfld.long 0x0 1. "CLSTR0_CORE0_PMSTAT_WFE,Core0 WFE When 0 indicates that Core0 is in the WFE state" "0,1" newline bitfld.long 0x0 0. "CLSTR0_CORE0_PMSTAT_WFI,Core0 WFI When 0 indicates that Core0 is in the WFI state" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "CFG0_CLSTR0_CORE1_CFG," bitfld.long 0x0 15. "CLSTR0_CORE1_CFG_NMFI_EN,Enable Core1 Non-Maskable Fast Interrupts" "0,1" newline bitfld.long 0x0 11. "CLSTR0_CORE1_CFG_TCM_RSTBASE,Core1 A/BTCM Reset Base Address Indicator 0 - BTCM located at address 0x0 1 - ATCM located at address 0x0" "0: BTCM located at address 0x0 1,?" newline bitfld.long 0x0 7. "CLSTR0_CORE1_CFG_BTCM_EN,Enable Core1 BTCM RAM at reset" "0,1" newline bitfld.long 0x0 3. "CLSTR0_CORE1_CFG_ATCM_EN,Enable Core1 ATCM RAM at reset" "0,1" rgroup.long 0x190++0x7 line.long 0x0 "CFG0_CLSTR0_CORE1_BOOTVECT_LO," hexmask.long 0x0 7.--31. 1. "CLSTR0_CORE1_BOOTVECT_LO_VECT_ADDR,Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]. Note bits 6:0 of the Vector Table address are always 0." line.long 0x4 "CFG0_CLSTR0_CORE1_BOOTVECT_HI," hexmask.long.word 0x4 0.--15. 1. "CLSTR0_CORE1_BOOTVECT_HI_VECT_ADDR,Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]." rgroup.long 0x1A0++0x3 line.long 0x0 "CFG0_CLSTR0_CORE1_PMCTRL," bitfld.long 0x0 0. "CLSTR0_CORE1_PMCTRL_CORE_HALT,Halt Core1" "0,1" rgroup.long 0x1B0++0x3 line.long 0x0 "CFG0_CLSTR0_CORE1_PMSTAT," bitfld.long 0x0 3. "CLSTR0_CORE1_PMSTAT_CLK_GATE,Core1 Clocked stopped due to WFI or WFE state" "0,1" newline bitfld.long 0x0 1. "CLSTR0_CORE1_PMSTAT_WFE,Core1 WFE When 0 indicates that Core1 is in the WFE state" "0,1" newline bitfld.long 0x0 0. "CLSTR0_CORE1_PMSTAT_WFI,Core1 WFI When 0 indicates that Core1 is in the WFI state" "0,1" rgroup.long 0x1020++0x3 line.long 0x0 "CFG0_CLSTR1_DEF," bitfld.long 0x0 16.--18. "CLSTR1_DEF_CORE_NUM,Number of cores in cluster 001 - Single Core 010 - Dual Core 100 - Quad Core" "?,1: Single Core 010,?,?,?,?,?,?" newline hexmask.long.byte 0x0 8.--15. 1. "CLSTR1_DEF_DSP_CORE_TYPE,DSP core type configuration Field values (others are reserved): 8'h00 - C7x 8'h01 - C6x 8'hFF - Not DSP" newline hexmask.long.byte 0x0 0.--7. 1. "CLSTR1_DEF_ARM_CORE_TYPE,ARM core type configuration Field values (others are reserved): 8'h00 - A53 8'h01 - A57 8'h10 - R5 8'hFF - Not ARM" rgroup.long 0x1040++0x3 line.long 0x0 "CFG0_CLSTR1_CFG," hexmask.long 0x0 5.--31. 1. "CLSTR1_CFG_CLSTR_CFG_RSVD,Reserved for future use. Write '0' to ensure compatibility with future devices." newline bitfld.long 0x0 4. "CLSTR1_CFG_MEM_INIT_DIS,Disables SRAM initialization (TCM Cache Tags etc) at reset Initialization must be performed for proper initial ECC initialization. The mem_init_dis value must be selected prior to R5 reset assertion. 1'b0 - Perform memory.." "0: Perform memory initialization 1'b1,?" newline rbitfld.long 0x0 3. "CLSTR1_CFG_LOCKSTEP_EN,Lockstep enable. Indicates if R5 lockstep operation is supported on the device" "0,1" newline bitfld.long 0x0 2. "CLSTR1_CFG_DBG_NO_CLKSTOP,CPU clockstop behavior 0 - CPU clocks stopped and nCLOCKSTOPPED asserted in standby mode 1 - CPU clocks not stopped in standby mode" "0: CPU clocks stopped and nCLOCKSTOPPED asserted in..,?" newline bitfld.long 0x0 1. "CLSTR1_CFG_TEINIT,Exception handling state at reset: 0 - ARM mode 1 - Thumb mode" "0: ARM mode 1,?" newline bitfld.long 0x0 0. "CLSTR1_CFG_LOCKSTEP,When set Core0 and Core1 operate in lockstep mode. Can only be changed if lockstep operation is supported as indicated by CLSTR1_CFG_lockstep_en = 1. If CLSTR1_CFG_lockstep_en = 0 lockstep is not supported this bit will be read.." "0,1" rgroup.long 0x1080++0x3 line.long 0x0 "CFG0_CLSTR1_PMCTRL," hexmask.long 0x0 0.--31. 1. "RESERVED,Not used for Pulsar / C66" rgroup.long 0x1090++0x3 line.long 0x0 "CFG0_CLSTR1_PMSTAT," hexmask.long 0x0 0.--31. 1. "RESERVED,Not used for Pulsar / C66" rgroup.long 0x1100++0x3 line.long 0x0 "CFG0_CLSTR1_CORE0_CFG," bitfld.long 0x0 15. "CLSTR1_CORE0_CFG_NMFI_EN,Enable Core0 Non-Maskable Fast Interrupts" "0,1" newline bitfld.long 0x0 11. "CLSTR1_CORE0_CFG_TCM_RSTBASE,Core0 A/BTCM Reset Base Address Indicator 0 - BTCM located at address 0x0 1 - ATCM located at address 0x0" "0: BTCM located at address 0x0 1,?" newline bitfld.long 0x0 7. "CLSTR1_CORE0_CFG_BTCM_EN,Enable Core0 BTCM RAM at reset" "0,1" newline bitfld.long 0x0 3. "CLSTR1_CORE0_CFG_ATCM_EN,Enable Core0 ATCM RAM at reset" "0,1" rgroup.long 0x1110++0x7 line.long 0x0 "CFG0_CLSTR1_CORE0_BOOTVECT_LO," hexmask.long 0x0 7.--31. 1. "CLSTR1_CORE0_BOOTVECT_LO_VECT_ADDR,Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]. Note bits 6:0 of the Vector Table address are always 0." line.long 0x4 "CFG0_CLSTR1_CORE0_BOOTVECT_HI," hexmask.long.word 0x4 0.--15. 1. "CLSTR1_CORE0_BOOTVECT_HI_VECT_ADDR,Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]." rgroup.long 0x1120++0x3 line.long 0x0 "CFG0_CLSTR1_CORE0_PMCTRL," bitfld.long 0x0 0. "CLSTR1_CORE0_PMCTRL_CORE_HALT,Halt Core0" "0,1" rgroup.long 0x1130++0x3 line.long 0x0 "CFG0_CLSTR1_CORE0_PMSTAT," bitfld.long 0x0 3. "CLSTR1_CORE0_PMSTAT_CLK_GATE,Core0 Clocked stopped due to WFI or WFE state" "0,1" newline bitfld.long 0x0 1. "CLSTR1_CORE0_PMSTAT_WFE,Core0 WFE When 0 indicates that Core0 is in the WFE state" "0,1" newline bitfld.long 0x0 0. "CLSTR1_CORE0_PMSTAT_WFI,Core0 WFI When 0 indicates that Core0 is in the WFI state" "0,1" rgroup.long 0x1180++0x3 line.long 0x0 "CFG0_CLSTR1_CORE1_CFG," bitfld.long 0x0 15. "CLSTR1_CORE1_CFG_NMFI_EN,Enable Core1 Non-Maskable Fast Interrupts" "0,1" newline bitfld.long 0x0 11. "CLSTR1_CORE1_CFG_TCM_RSTBASE,Core1 A/BTCM Reset Base Address Indicator 0 - BTCM located at address 0x0 1 - ATCM located at address 0x0" "0: BTCM located at address 0x0 1,?" newline bitfld.long 0x0 7. "CLSTR1_CORE1_CFG_BTCM_EN,Enable Core1 BTCM RAM at reset" "0,1" newline bitfld.long 0x0 3. "CLSTR1_CORE1_CFG_ATCM_EN,Enable Core1 ATCM RAM at reset" "0,1" rgroup.long 0x1190++0x7 line.long 0x0 "CFG0_CLSTR1_CORE1_BOOTVECT_LO," hexmask.long 0x0 7.--31. 1. "CLSTR1_CORE1_BOOTVECT_LO_VECT_ADDR,Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]. Note bits 6:0 of the Vector Table address are always 0." line.long 0x4 "CFG0_CLSTR1_CORE1_BOOTVECT_HI," hexmask.long.word 0x4 0.--15. 1. "CLSTR1_CORE1_BOOTVECT_HI_VECT_ADDR,Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]." rgroup.long 0x11A0++0x3 line.long 0x0 "CFG0_CLSTR1_CORE1_PMCTRL," bitfld.long 0x0 0. "CLSTR1_CORE1_PMCTRL_CORE_HALT,Halt Core1" "0,1" rgroup.long 0x11B0++0x3 line.long 0x0 "CFG0_CLSTR1_CORE1_PMSTAT," bitfld.long 0x0 3. "CLSTR1_CORE1_PMSTAT_CLK_GATE,Core1 Clocked stopped due to WFI or WFE state" "0,1" newline bitfld.long 0x0 1. "CLSTR1_CORE1_PMSTAT_WFE,Core1 WFE When 0 indicates that Core1 is in the WFE state" "0,1" newline bitfld.long 0x0 0. "CLSTR1_CORE1_PMSTAT_WFI,Core1 WFI When 0 indicates that Core1 is in the WFI state" "0,1" rgroup.long 0x2020++0x3 line.long 0x0 "CFG0_CLSTR2_DEF," bitfld.long 0x0 16.--18. "CLSTR2_DEF_CORE_NUM,Number of cores in cluster 001 - Single Core 010 - Dual Core 100 - Quad Core" "?,1: Single Core 010,?,?,?,?,?,?" newline hexmask.long.byte 0x0 8.--15. 1. "CLSTR2_DEF_DSP_CORE_TYPE,DSP core type configuration Field values (others are reserved): 8'h00 - C7x 8'h01 - C6x 8'hFF - Not DSP" newline hexmask.long.byte 0x0 0.--7. 1. "CLSTR2_DEF_ARM_CORE_TYPE,ARM core type configuration Field values (others are reserved): 8'h00 - A53 8'h01 - A57 8'h10 - R5 8'hFF - Not ARM" rgroup.long 0x2040++0x3 line.long 0x0 "CFG0_CLSTR2_CFG," hexmask.long 0x0 5.--31. 1. "CLSTR2_CFG_CLSTR_CFG_RSVD,Reserved for future use. Write '0' to ensure compatibility with future devices." newline bitfld.long 0x0 4. "CLSTR2_CFG_MEM_INIT_DIS,Disables SRAM initialization (TCM Cache Tags etc) at reset Initialization must be performed for proper initial ECC initialization. The mem_init_dis value must be selected prior to R5 reset assertion. 1'b0 - Perform memory.." "0: Perform memory initialization 1'b1,?" newline rbitfld.long 0x0 3. "CLSTR2_CFG_LOCKSTEP_EN,Lockstep enable. Indicates if R5 lockstep operation is supported on the device" "0,1" newline bitfld.long 0x0 2. "CLSTR2_CFG_DBG_NO_CLKSTOP,CPU clockstop behavior 0 - CPU clocks stopped and nCLOCKSTOPPED asserted in standby mode 1 - CPU clocks not stopped in standby mode" "0: CPU clocks stopped and nCLOCKSTOPPED asserted in..,?" newline bitfld.long 0x0 1. "CLSTR2_CFG_TEINIT,Exception handling state at reset: 0 - ARM mode 1 - Thumb mode" "0: ARM mode 1,?" newline bitfld.long 0x0 0. "CLSTR2_CFG_LOCKSTEP,When set Core0 and Core1 operate in lockstep mode. Can only be changed if lockstep operation is supported as indicated by CLSTR2_CFG_lockstep_en = 1. If CLSTR2_CFG_lockstep_en = 0 lockstep is not supported this bit will be read.." "0,1" rgroup.long 0x2080++0x3 line.long 0x0 "CFG0_CLSTR2_PMCTRL," hexmask.long 0x0 0.--31. 1. "RESERVED,Not used for Pulsar / C66" rgroup.long 0x2090++0x3 line.long 0x0 "CFG0_CLSTR2_PMSTAT," hexmask.long 0x0 0.--31. 1. "RESERVED,Not used for Pulsar / C66" rgroup.long 0x2100++0x3 line.long 0x0 "CFG0_CLSTR2_CORE0_CFG," bitfld.long 0x0 15. "CLSTR2_CORE0_CFG_NMFI_EN,Enable Core0 Non-Maskable Fast Interrupts" "0,1" newline bitfld.long 0x0 11. "CLSTR2_CORE0_CFG_TCM_RSTBASE,Core0 A/BTCM Reset Base Address Indicator 0 - BTCM located at address 0x0 1 - ATCM located at address 0x0" "0: BTCM located at address 0x0 1,?" newline bitfld.long 0x0 7. "CLSTR2_CORE0_CFG_BTCM_EN,Enable Core0 BTCM RAM at reset" "0,1" newline bitfld.long 0x0 3. "CLSTR2_CORE0_CFG_ATCM_EN,Enable Core0 ATCM RAM at reset" "0,1" rgroup.long 0x2110++0x7 line.long 0x0 "CFG0_CLSTR2_CORE0_BOOTVECT_LO," hexmask.long 0x0 7.--31. 1. "CLSTR2_CORE0_BOOTVECT_LO_VECT_ADDR,Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]. Note bits 6:0 of the Vector Table address are always 0." line.long 0x4 "CFG0_CLSTR2_CORE0_BOOTVECT_HI," hexmask.long.word 0x4 0.--15. 1. "CLSTR2_CORE0_BOOTVECT_HI_VECT_ADDR,Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]." rgroup.long 0x2120++0x3 line.long 0x0 "CFG0_CLSTR2_CORE0_PMCTRL," bitfld.long 0x0 0. "CLSTR2_CORE0_PMCTRL_CORE_HALT,Halt Core0" "0,1" rgroup.long 0x2130++0x3 line.long 0x0 "CFG0_CLSTR2_CORE0_PMSTAT," bitfld.long 0x0 3. "CLSTR2_CORE0_PMSTAT_CLK_GATE,Core0 Clocked stopped due to WFI or WFE state" "0,1" newline bitfld.long 0x0 1. "CLSTR2_CORE0_PMSTAT_WFE,Core0 WFE When 0 indicates that Core0 is in the WFE state" "0,1" newline bitfld.long 0x0 0. "CLSTR2_CORE0_PMSTAT_WFI,Core0 WFI When 0 indicates that Core0 is in the WFI state" "0,1" rgroup.long 0x2180++0x3 line.long 0x0 "CFG0_CLSTR2_CORE1_CFG," bitfld.long 0x0 15. "CLSTR2_CORE1_CFG_NMFI_EN,Enable Core1 Non-Maskable Fast Interrupts" "0,1" newline bitfld.long 0x0 11. "CLSTR2_CORE1_CFG_TCM_RSTBASE,Core1 A/BTCM Reset Base Address Indicator 0 - BTCM located at address 0x0 1 - ATCM located at address 0x0" "0: BTCM located at address 0x0 1,?" newline bitfld.long 0x0 7. "CLSTR2_CORE1_CFG_BTCM_EN,Enable Core1 BTCM RAM at reset" "0,1" newline bitfld.long 0x0 3. "CLSTR2_CORE1_CFG_ATCM_EN,Enable Core1 ATCM RAM at reset" "0,1" rgroup.long 0x2190++0x7 line.long 0x0 "CFG0_CLSTR2_CORE1_BOOTVECT_LO," hexmask.long 0x0 7.--31. 1. "CLSTR2_CORE1_BOOTVECT_LO_VECT_ADDR,Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]. Note bits 6:0 of the Vector Table address are always 0." line.long 0x4 "CFG0_CLSTR2_CORE1_BOOTVECT_HI," hexmask.long.word 0x4 0.--15. 1. "CLSTR2_CORE1_BOOTVECT_HI_VECT_ADDR,Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]." rgroup.long 0x21A0++0x3 line.long 0x0 "CFG0_CLSTR2_CORE1_PMCTRL," bitfld.long 0x0 0. "CLSTR2_CORE1_PMCTRL_CORE_HALT,Halt Core1" "0,1" rgroup.long 0x21B0++0x3 line.long 0x0 "CFG0_CLSTR2_CORE1_PMSTAT," bitfld.long 0x0 3. "CLSTR2_CORE1_PMSTAT_CLK_GATE,Core1 Clocked stopped due to WFI or WFE state" "0,1" newline bitfld.long 0x0 1. "CLSTR2_CORE1_PMSTAT_WFE,Core1 WFE When 0 indicates that Core1 is in the WFE state" "0,1" newline bitfld.long 0x0 0. "CLSTR2_CORE1_PMSTAT_WFI,Core1 WFI When 0 indicates that Core1 is in the WFI state" "0,1" tree.end tree "SEC_MMR0_DBG_CTRL (SEC_MMR0_DBG_CTRL)" base ad:0x45944000 rgroup.long 0x0++0x3 line.long 0x0 "CFG2_CLSTR0_CORE0_DBG_CFG," hexmask.long.byte 0x0 12.--15. 1. "CLSTR0_CORE0_DBG_CFG_DBGEN,Core0 Invasive debug enable. This is a fault tolerant bitfield that must be set 4'hA to enable 4'b1010 - Enabled others - Disabled" hexmask.long.byte 0x0 8.--11. 1. "CLSTR0_CORE0_DBG_CFG_NIDEN,Core0 Non-invasive debug enable. This is a fault tolerant bitfield that must be set 4'hA to enable 4'b1010 - Enabled others - Disabled" rgroup.long 0x40++0x3 line.long 0x0 "CFG2_CLSTR0_CORE1_DBG_CFG," hexmask.long.byte 0x0 12.--15. 1. "CLSTR0_CORE1_DBG_CFG_DBGEN,Core1 Invasive debug enable. This is a fault tolerant bitfield that must be set 4'hA to enable 4'b1010 - Enabled others - Disabled" hexmask.long.byte 0x0 8.--11. 1. "CLSTR0_CORE1_DBG_CFG_NIDEN,Core1 Non-invasive debug enable. This is a fault tolerant bitfield that must be set 4'hA to enable 4'b1010 - Enabled others - Disabled" rgroup.long 0x1000++0x3 line.long 0x0 "CFG2_CLSTR1_CORE0_DBG_CFG," hexmask.long.byte 0x0 12.--15. 1. "CLSTR1_CORE0_DBG_CFG_DBGEN,Core0 Invasive debug enable. This is a fault tolerant bitfield that must be set 4'hA to enable 4'b1010 - Enabled others - Disabled" hexmask.long.byte 0x0 8.--11. 1. "CLSTR1_CORE0_DBG_CFG_NIDEN,Core0 Non-invasive debug enable. This is a fault tolerant bitfield that must be set 4'hA to enable 4'b1010 - Enabled others - Disabled" rgroup.long 0x1040++0x3 line.long 0x0 "CFG2_CLSTR1_CORE1_DBG_CFG," hexmask.long.byte 0x0 12.--15. 1. "CLSTR1_CORE1_DBG_CFG_DBGEN,Core1 Invasive debug enable. This is a fault tolerant bitfield that must be set 4'hA to enable 4'b1010 - Enabled others - Disabled" hexmask.long.byte 0x0 8.--11. 1. "CLSTR1_CORE1_DBG_CFG_NIDEN,Core1 Non-invasive debug enable. This is a fault tolerant bitfield that must be set 4'hA to enable 4'b1010 - Enabled others - Disabled" rgroup.long 0x2000++0x3 line.long 0x0 "CFG2_CLSTR2_CORE0_DBG_CFG," hexmask.long.byte 0x0 12.--15. 1. "CLSTR2_CORE0_DBG_CFG_DBGEN,Core0 Invasive debug enable. This is a fault tolerant bitfield that must be set 4'hA to enable 4'b1010 - Enabled others - Disabled" hexmask.long.byte 0x0 8.--11. 1. "CLSTR2_CORE0_DBG_CFG_NIDEN,Core0 Non-invasive debug enable. This is a fault tolerant bitfield that must be set 4'hA to enable 4'b1010 - Enabled others - Disabled" rgroup.long 0x2040++0x3 line.long 0x0 "CFG2_CLSTR2_CORE1_DBG_CFG," hexmask.long.byte 0x0 12.--15. 1. "CLSTR2_CORE1_DBG_CFG_DBGEN,Core1 Invasive debug enable. This is a fault tolerant bitfield that must be set 4'hA to enable 4'b1010 - Enabled others - Disabled" hexmask.long.byte 0x0 8.--11. 1. "CLSTR2_CORE1_DBG_CFG_NIDEN,Core1 Non-invasive debug enable. This is a fault tolerant bitfield that must be set 4'hA to enable 4'b1010 - Enabled others - Disabled" tree.end tree.end tree "SERDES_10G0 (SERDES_10G0)" base ad:0x5060000 wgroup.long 0x40++0x7 line.long 0x0 "WIZ16B8M4CT2_CMN_SSM_BANDGAP_TMR__CMN_SSM_SM_CTRL,Startup state machine control register" hexmask.long.byte 0x0 16.--20. 1. "CMN_SSM_BANDGAP_TMR_4_0,Bandgap enable state timer value : Value used for the timer when the startup state machine is in the bandgap enable state. This timer delay is specified as the number of reference clocks to count. This value creates a delay of.." line.long 0x4 "WIZ16B8M4CT2_CMN_SSM_BIAS_TMR,Bias enable timer register" hexmask.long.byte 0x4 0.--6. 1. "CMN_SSM_BIAS_TMR_6_0,Bias enable state timer value : Value used for the timer when the startup state machine is in the bias enable state. This timer delay is specified as the number of reference clocks to count. This value creates a delay of 1 uSec." wgroup.long 0x50++0xB line.long 0x0 "WIZ16B8M4CT2_CMN_PLLSM0_PLLEN_TMR__CMN_PLLSM0_SM_CTRL,PLL 0 control state machine control register" hexmask.long.byte 0x0 16.--19. 1. "CMN_PLLSM0_PLLEN_TMR_3_0,PLL enable state timer value : Value used for the timer when the startup state machine is in the PLL enable state. This timer delay is specified as the number of reference clocks to count." line.long 0x4 "WIZ16B8M4CT2_CMN_PLLSM0_PLLVREF_TMR__CMN_PLLSM0_PLLPRE_TMR,PLL 0 pre-charge timer register" hexmask.long.byte 0x4 0.--7. 1. "CMN_PLLSM0_PLLPRE_TMR_7_0,PLL pre-charge state timer value : Value used for the timer when the startup state machine is in the PLL pre-charge state. This timer delay is specified as the number of reference clocks to count. This value creates a delay of.." line.long 0x8 "WIZ16B8M4CT2_CMN_PLLSM0_PLLCLKDIS_TMR__CMN_PLLSM0_PLLLOCK_TMR,PLL 0 lock delay timer register" hexmask.long.word 0x8 0.--9. 1. "CMN_PLLSM0_PLLLOCK_TMR_9_0,PLL lock delay state timer value : Value used for the timer when the startup state machine is in the PLL lock delay state. This timer delay is specified as the number of reference clocks to count." wgroup.long 0x60++0xB line.long 0x0 "WIZ16B8M4CT2_CMN_PLLSM1_PLLEN_TMR__CMN_PLLSM1_SM_CTRL,PLL 1 control state machine control register" hexmask.long.byte 0x0 16.--19. 1. "CMN_PLLSM1_PLLEN_TMR_3_0,PLL enable state timer value : Value used for the timer when the startup state machine is in the PLL enable state. This timer delay is specified as the number of reference clocks to count." line.long 0x4 "WIZ16B8M4CT2_CMN_PLLSM1_PLLVREF_TMR__CMN_PLLSM1_PLLPRE_TMR,PLL 1 pre-charge timer register" hexmask.long.byte 0x4 0.--7. 1. "CMN_PLLSM1_PLLPRE_TMR_7_0,PLL pre-charge state timer value : Value used for the timer when the startup state machine is in the PLL pre-charge state. This timer delay is specified as the number of reference clocks to count." line.long 0x8 "WIZ16B8M4CT2_CMN_PLLSM1_PLLCLKDIS_TMR__CMN_PLLSM1_PLLLOCK_TMR,PLL 1 lock delay timer register" hexmask.long.word 0x8 0.--9. 1. "CMN_PLLSM1_PLLLOCK_TMR_9_0,PLL lock delay state timer value : Value used for the timer when the startup state machine is in the PLL lock delay state. This timer delay is specified as the number of reference clocks to count." wgroup.long 0x80++0x3 line.long 0x0 "WIZ16B8M4CT2_CMN_CDIAG_CDB_PWRI_OVRD__CMN_CDIAG_PWRI_TMR,Common power island control timer register" bitfld.long 0x0 31. "CMN_CDIAG_CDB_PWRI_OVRD_15,Power island controller input override enable: When enabled the power island control state machine input override bits in this register will drive the power island control state machine directly and override any control from.." "0: Override disabled 1'b1: Override enabled,?" newline bitfld.long 0x0 30. "CMN_CDIAG_CDB_PWRI_OVRD_14,Power island controller output override enable: When enabled the power island control state machine output override bits in this register will drive the power island control state machine outputs and override any control from.." "0: Override disabled 1'b1: Override enabled,?" newline bitfld.long 0x0 27. "CMN_CDIAG_CDB_PWRI_OVRD_11,Power suspend request override: When enabled this bit will override the power_suspend_req input of the power island control state machine. Note that whenever changing the state of this bit no other CDB register access should.." "0,1" newline rbitfld.long 0x0 26. "CMN_CDIAG_CDB_PWRI_OVRD_10,Power suspend acknowledge: This is the current state of the power_suspend_ack output from the power island control state machine. Note that this bit will always be set to 1'b1 after the power island is enabled as a function.." "0,1" newline bitfld.long 0x0 25. "CMN_CDIAG_CDB_PWRI_OVRD_9,Power recover request override: When enabled this bit will override the power_recover_req input of the power island control state machine. Note that whenever changing the state of this bit no other CDB register access should.." "0,1" newline rbitfld.long 0x0 24. "CMN_CDIAG_CDB_PWRI_OVRD_8,Power recover acknowledge: This is the current state of the power_recover_ack output from the power island control state machine. Note that this bit will always be set to 1'b1 after the power island is enabled as a function of.." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "CMN_CDIAG_CDB_PWRI_OVRD_7_0,Power island controller output override: When enabled the bits in this field will override the output signals from the power island control state machine. The following are the power island control state machine output.." wgroup.long 0x8C++0x3 line.long 0x0 "WIZ16B8M4CT2_CMN_CDIAG_XCVRC_PWRI_OVRD__CMN_CDIAG_CCAL_PWRI_STAT,Common common calibration power island control status register" bitfld.long 0x0 31. "CMN_CDIAG_XCVRC_PWRI_OVRD_15,Power island controller input override enable: When enabled the power island control state machine input override bits in this register will drive the power island control state machine directly and override any control.." "0: Override disabled 1'b1: Override enabled,?" newline bitfld.long 0x0 30. "CMN_CDIAG_XCVRC_PWRI_OVRD_14,Power island controller output override enable: When enabled the power island control state machine output override bits in this register will drive the power island control state machine outputs and override any control.." "0: Override disabled 1'b1: Override enabled,?" newline bitfld.long 0x0 27. "CMN_CDIAG_XCVRC_PWRI_OVRD_11,Power suspend request override: When enabled this bit will override the power_suspend_req input of the power island control state machine." "0,1" newline rbitfld.long 0x0 26. "CMN_CDIAG_XCVRC_PWRI_OVRD_10,Power suspend acknowledge: This is the current state of the power_suspend_ack output from the power island control state machine. Note that this bit will always be set to 1'b1 after the power island is enabled as a function.." "0,1" newline bitfld.long 0x0 25. "CMN_CDIAG_XCVRC_PWRI_OVRD_9,Power recover request override: When enabled this bit will override the power_recover_req input of the power island control state machine." "0,1" newline rbitfld.long 0x0 24. "CMN_CDIAG_XCVRC_PWRI_OVRD_8,Power recover acknowledge: This is the current state of the power_recover_ack output from the power island control state machine. Note that this bit will always be set to 1'b1 after the power island is enabled as a function.." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "CMN_CDIAG_XCVRC_PWRI_OVRD_7_0,Power island controller output override: When enabled the bits in this field will override the output signals from the power island control state machine. The following are the power island control state machine output.." wgroup.long 0xC8++0x3 line.long 0x0 "WIZ16B8M4CT2_CMN_BGCAL_ITER_TMR__CMN_BGCAL_INIT_TMR,Bandgap calibration initialization timer register" hexmask.long.word 0x0 16.--24. 1. "CMN_BGCAL_ITER_TMR_8_0,Iteration wait timer value: This is the number of cmn_ref_clk clocks to wait between when a value is placed on the bandgap calibration signals going to the analog and when the comparator value coming from the analog circuits can.." newline hexmask.long.word 0x0 0.--8. 1. "CMN_BGCAL_INIT_TMR_8_0,Initialization wait timer value: This is the number of cmn_ref_clk clocks to wait between when the analog bandgap calibration circuits are enabled and when the first values are placed on the bandgap calibration signals going to.." wgroup.long 0xE8++0x3 line.long 0x0 "WIZ16B8M4CT2_CMN_IBCAL_ITER_TMR__CMN_IBCAL_INIT_TMR,External bias current calibration initialization timer register" hexmask.long.byte 0x0 16.--22. 1. "CMN_IBCAL_ITER_TMR_6_0,Iteration wait timer value: This is the number of cmn_ref_clk clocks to wait between when a value is placed on the calibration selection bus going to the analog and when the comparator value coming from the analog circuits can be.." newline hexmask.long.byte 0x0 0.--6. 1. "CMN_IBCAL_INIT_TMR_6_0,Initialization wait timer value: This is the number of cmn_ref_clk clocks to wait between when the analog calibration circuits are enabled and when the first calibration selection value is placed on the calibration code bus going.." wgroup.long 0x104++0xF line.long 0x0 "WIZ16B8M4CT2_CMN_PLL0_VCOCAL_OVRD__CMN_PLL0_VCOCAL_TCTRL,PLL 0 VCO calibration timer control register" bitfld.long 0x0 0.--2. "CMN_PLL0_VCOCAL_TCTRL_2_0,VCO calibration initial time scale control: This field specifies the calibration start time scaling factor applied to the VCO calibration when running the initial step size for the calibration code if not set to 1. Setting this.." "0: Div 1 3'b001 : Div 2 3'b010 : Div 4 3'b011 : Div..,?,?,?,?,?,?,?" line.long 0x4 "WIZ16B8M4CT2_CMN_PLL0_VCOCAL_ITER_TMR__CMN_PLL0_VCOCAL_INIT_TMR,PLL 0 VCO calibration initialization timer register" hexmask.long.word 0x4 16.--29. 1. "CMN_PLL0_VCOCAL_ITER_TMR_13_0,Iteration wait timer value: This is the number of clocks to wait between when a calibration code is driven to the analog and when the clock rates are measured." newline hexmask.long.word 0x4 0.--13. 1. "CMN_PLL0_VCOCAL_INIT_TMR_13_0,Initialization wait timer value: This is the number of clocks to wait between when the analog VCO calibration circuits are enabled and when the first calibration code is driven to the analog. Note that this results in the.." line.long 0x8 "WIZ16B8M4CT2_CMN_PLL0_VCOCAL_REFTIM_START,PLL 0 VCO calibration reference clock timer start value register" hexmask.long.word 0x8 0.--13. 1. "CMN_PLL0_VCOCAL_REFTIM_START_13_0,PLL VCO calibration reference clock timer start value : This is the value that is loaded into the reference clock timer as the starting point for that timer when running VCO calibration. The value in this field must.." line.long 0xC "WIZ16B8M4CT2_CMN_PLL0_VCOCAL_PLLCNT_START,PLL 0 VCO calibration PLL clock counter start value register" hexmask.long.word 0xC 0.--13. 1. "CMN_PLL0_VCOCAL_PLLCNT_START_13_0,PLL VCO calibration PLL clock counter start value : This is the value that is loaded into the PLL clock counter as the starting point for that counter when running VCO calibration. When programming this register it is.." wgroup.long 0x120++0xB line.long 0x0 "WIZ16B8M4CT2_CMN_PLL0_FRACDIVL_M0__CMN_PLL0_INTDIV_M0,PLL 0 feedback divider integer register mode 0" hexmask.long.word 0x0 16.--31. 1. "CMN_PLL0_FRACDIVL_M0_15_0,pll_fb_div_fractional: Value of the pll_fb_div_fractional[15:0] signal." newline hexmask.long.word 0x0 0.--8. 1. "CMN_PLL0_INTDIV_M0_8_0,pll_fb_div_integer value: Value of the pll_fb_div_integer signal." line.long 0x4 "WIZ16B8M4CT2_CMN_PLL0_HIGH_THR_M0__CMN_PLL0_FRACDIVH_M0,PLL 0 feedback divider fractional high register mode 0" hexmask.long.word 0x4 16.--24. 1. "CMN_PLL0_HIGH_THR_M0_8_0,pll_fb_div_high_theshold: Value of the pll_fb_div_high_threshold signal. The value of this register should be 2/3 the value of the combined integer and fractional divider values and rounded up to the next even number." newline bitfld.long 0x4 0.--2. "CMN_PLL0_FRACDIVH_M0_2_0,pll_fb_div_fractional: Value of the pll_fb_div_fractional[18:16] signal." "0,1,2,3,4,5,6,7" line.long 0x8 "WIZ16B8M4CT2_CMN_PLL0_DSM_FBH_OVRD_M0__CMN_PLL0_DSM_DIAG_M0,PLL 0 delta sigma modulator diagnostics register mode 0" bitfld.long 0x8 15. "CMN_PLL0_DSM_DIAG_M0_15,Delta sigma bypass enable: When set to 1'b1 the delta sigma modulator will be bypassed and the output will be the value specified for the internal pll_fb_div_integer signal." "0,1" newline bitfld.long 0x8 14. "CMN_PLL0_DSM_DIAG_M0_14,PLL feedback divider override enable : When active (1'b1) the feedback divider low and high override values in the PLL 0 delta sigma modulator feedback divider value high override register mode 0 on page 114 and PLL 0 delta sigma.." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "CMN_PLL0_DSM_DIAG_M0_3_0,PLL feedback divider latency adjustment: This signal specifies a value to be subtracted from the feedback divider settings before they are output on the cmnda_pll0_fb_div_high and cmnda_pll0_fb_div_low signals." wgroup.long 0x130++0x1B line.long 0x0 "WIZ16B8M4CT2_CMN_PLL0_SS_CTRL2_M0__CMN_PLL0_SS_CTRL1_M0,PLL 0 spread spectrum control register 1 mode 0" hexmask.long.word 0x0 16.--30. 1. "CMN_PLL0_SS_CTRL2_M0_14_0,Amplitude step size: Value of the amplitude_step_size pin on the spread spectrum waveform generator. Note that this field should not be set to 0 when spread spectrum is enabled." newline bitfld.long 0x0 1. "CMN_PLL0_SS_CTRL1_M0_1,Spread spectrum waveform generator disable: Setting this bit to a 1'b1 will disable the spread spectrum waveform generator." "0,1" newline bitfld.long 0x0 0. "CMN_PLL0_SS_CTRL1_M0_0,Spread spectrum enable during VCO calibration : Setting this bit to a 1'b1 will enable the spread spectrum function while VCO calibration is taking place." "0,1" line.long 0x4 "WIZ16B8M4CT2_CMN_PLL0_SS_CTRL4_M0__CMN_PLL0_SS_CTRL3_M0,PLL 0 spread spectrum control register 3 mode 0" hexmask.long.byte 0x4 16.--22. 1. "CMN_PLL0_SS_CTRL4_M0_6_0,Time step size: Value for the time_step_size pin on the spread spectrum waveform generator. Note that this field should not be set to 0 when spread spectrum is enabled." newline hexmask.long.byte 0x4 0.--6. 1. "CMN_PLL0_SS_CTRL3_M0_6_0,Number of steps: Value of the num_steps pin on the spread spectrum waveform generator. Note that this field should not be set to 0 when spread spectrum is enabled." line.long 0x8 "WIZ16B8M4CT2_CMN_PLL0_LOCK_REFCNT_IDLE__CMN_PLL0_LOCK_REFCNT_START,PLL 0 lock reference counter start value register" hexmask.long.word 0x8 0.--11. 1. "CMN_PLL0_LOCK_REFCNT_START_11_0,PLL lock reference counter start value : This is the value that is loaded into the PLL lock detect reference counter as the starting point for that counter when checking for PLL lock. Note that the value required here.." line.long 0xC "WIZ16B8M4CT2_CMN_PLL0_LOCK_PLLCNT_THR__CMN_PLL0_LOCK_PLLCNT_START,PLL 0 lock PLL counter start value register" hexmask.long.word 0xC 16.--27. 1. "CMN_PLL0_LOCK_PLLCNT_THR_11_0,PLL lock counter threshold value : This is the value used by the PLL lock detection logic to determine if the PLL has locked. If the two counters in the PLL lock detection logic differ by less than this value the PLL is.." newline hexmask.long.word 0xC 0.--11. 1. "CMN_PLL0_LOCK_PLLCNT_START_11_0,PLL lock PLL counter start value : This is the value that is loaded into the PLL lock detect PLL counter as the starting point for that counter when checking for PLL lock. The value is the number of PLL feedback divider.." line.long 0x10 "WIZ16B8M4CT2_CMN_PLL0_FRACDIVL_M1__CMN_PLL0_INTDIV_M1,PLL 0 feedback divider integer register mode 1" hexmask.long.word 0x10 16.--31. 1. "CMN_PLL0_FRACDIVL_M1_15_0,pll_fb_div_fractional: Value of the pll_fb_div_fractional[15:0] signal." newline hexmask.long.word 0x10 0.--8. 1. "CMN_PLL0_INTDIV_M1_8_0,pll_fb_div_integer value: Value of the pll_fb_div_integer signal." line.long 0x14 "WIZ16B8M4CT2_CMN_PLL0_HIGH_THR_M1__CMN_PLL0_FRACDIVH_M1,PLL 0 feedback divider fractional high register mode 1" hexmask.long.word 0x14 16.--24. 1. "CMN_PLL0_HIGH_THR_M1_8_0,pll_fb_div_high_theshold: Value of the pll_fb_div_high_threshold signal. The value of this register should be 2/3 the value of the combined integer and fractional divider values and rounded up to the next even number." newline bitfld.long 0x14 0.--2. "CMN_PLL0_FRACDIVH_M1_2_0,pll_fb_div_fractional: Value of the pll_fb_div_fractional[18:16] signal." "0,1,2,3,4,5,6,7" line.long 0x18 "WIZ16B8M4CT2_CMN_PLL0_DSM_FBH_OVRD_M1__CMN_PLL0_DSM_DIAG_M1,PLL 0 delta sigma modulator diagnostics register mode 1" bitfld.long 0x18 15. "CMN_PLL0_DSM_DIAG_M1_15,Delta sigma bypass enable: When set to 1'b1 the delta sigma modulator will be bypassed and the output will be the value specified for the internal pll_fb_div_integer signal." "0,1" newline bitfld.long 0x18 14. "CMN_PLL0_DSM_DIAG_M1_14,PLL feedback divider override enable : When active (1'b1) the feedback divider low and high override values in the PLL 0 delta sigma modulator feedback divider value high override register mode 0 on page 114 and PLL 0 delta sigma.." "0,1" newline hexmask.long.byte 0x18 0.--3. 1. "CMN_PLL0_DSM_DIAG_M1_3_0,PLL feedback divider latency adjustment: This signal specifies a value to be subtracted from the feedback divider settings before they are output on the cmnda_pll0_fb_div_high and cmnda_pll0_fb_div_low signals." wgroup.long 0x150++0x7 line.long 0x0 "WIZ16B8M4CT2_CMN_PLL0_SS_CTRL2_M1__CMN_PLL0_SS_CTRL1_M1,PLL 0 spread spectrum control register 1 mode 1" hexmask.long.word 0x0 16.--30. 1. "CMN_PLL0_SS_CTRL2_M1_14_0,Amplitude step size: Value of the amplitude_step_size pin on the spread spectrum waveform generator. Note that this field should not be set to 0 when spread spectrum is enabled." newline bitfld.long 0x0 1. "CMN_PLL0_SS_CTRL1_M1_1,Spread spectrum waveform generator disable: Setting this bit to a 1'b1 will disable the spread spectrum waveform generator." "0,1" newline bitfld.long 0x0 0. "CMN_PLL0_SS_CTRL1_M1_0,Spread spectrum enable during VCO calibration : Setting this bit to a 1'b1 will enable the spread spectrum function while VCO calibration is taking place." "0,1" line.long 0x4 "WIZ16B8M4CT2_CMN_PLL0_SS_CTRL4_M1__CMN_PLL0_SS_CTRL3_M1,PLL 0 spread spectrum control register 3 mode 1" hexmask.long.byte 0x4 16.--22. 1. "CMN_PLL0_SS_CTRL4_M1_6_0,Time step size: Value for the time_step_size pin on the spread spectrum waveform generator. Note that this field should not be set to 0 when spread spectrum is enabled." newline hexmask.long.byte 0x4 0.--6. 1. "CMN_PLL0_SS_CTRL3_M1_6_0,Number of steps: Value of the num_steps pin on the spread spectrum waveform generator. Note that this field should not be set to 0 when spread spectrum is enabled." wgroup.long 0x184++0xF line.long 0x0 "WIZ16B8M4CT2_CMN_PLL1_VCOCAL_OVRD__CMN_PLL1_VCOCAL_TCTRL,PLL 1 VCO calibration timer control register" bitfld.long 0x0 0.--2. "CMN_PLL1_VCOCAL_TCTRL_2_0,VCO calibration initial time scale control: This field specifies the calibration start time scaling factor applied to the VCO calibration when running the initial step size for the calibration code if not set to 1. Setting this.." "0: Div 1 3'b001 : Div 2 3'b010 : Div 4 3'b011 : Div..,?,?,?,?,?,?,?" line.long 0x4 "WIZ16B8M4CT2_CMN_PLL1_VCOCAL_ITER_TMR__CMN_PLL1_VCOCAL_INIT_TMR,PLL 1 VCO calibration initialization timer register" hexmask.long.word 0x4 16.--29. 1. "CMN_PLL1_VCOCAL_ITER_TMR_13_0,Iteration wait timer value: This is the number of clocks to wait between when a calibration code is driven to the analog and when the clock rates are measured." newline hexmask.long.word 0x4 0.--13. 1. "CMN_PLL1_VCOCAL_INIT_TMR_13_0,Initialization wait timer value: This is the number of clocks to wait between when the analog VCO calibration circuits are enabled and when the first calibration code is driven to the analog. Note that the reset value for.." line.long 0x8 "WIZ16B8M4CT2_CMN_PLL1_VCOCAL_REFTIM_START,PLL 1 VCO calibration reference clock timer start value register" hexmask.long.word 0x8 0.--13. 1. "CMN_PLL1_VCOCAL_REFTIM_START_13_0,PLL VCO calibration reference clock timer start value : This is the value that is loaded into the reference clock timer as the starting point for that timer when running VCO calibration. The value in this field must.." line.long 0xC "WIZ16B8M4CT2_CMN_PLL1_VCOCAL_PLLCNT_START,PLL 1 VCO calibration PLL clock counter start value register" hexmask.long.word 0xC 0.--13. 1. "CMN_PLL1_VCOCAL_PLLCNT_START_13_0,PLL VCO calibration PLL clock counter start value : This is the value that is loaded into the PLL clock counter as the starting point for that counter when running VCO calibration. When programming this register it is.." wgroup.long 0x1A0++0xB line.long 0x0 "WIZ16B8M4CT2_CMN_PLL1_FRACDIVL_M0__CMN_PLL1_INTDIV_M0,PLL 1 feedback divider integer register mode 0" hexmask.long.word 0x0 16.--31. 1. "CMN_PLL1_FRACDIVL_M0_15_0,pll_fb_div_fractional: Value of the pll_fb_div_fractional[15:0] signal." newline hexmask.long.word 0x0 0.--8. 1. "CMN_PLL1_INTDIV_M0_8_0,pll_fb_div_integer value: Value of the pll_fb_div_integer signal." line.long 0x4 "WIZ16B8M4CT2_CMN_PLL1_HIGH_THR_M0__CMN_PLL1_FRACDIVH_M0,PLL 1 feedback divider fractional high register mode 0" hexmask.long.word 0x4 16.--24. 1. "CMN_PLL1_HIGH_THR_M0_8_0,pll_fb_div_high_theshold: Value of the pll_fb_div_high_threshold signal. The value of this register should be 2/3 the value of the combined integer and fractional divider values and rounded up to the next even number." newline bitfld.long 0x4 0.--2. "CMN_PLL1_FRACDIVH_M0_2_0,pll_fb_div_fractional: Value of the pll_fb_div_fractional[18:16] signal." "0,1,2,3,4,5,6,7" line.long 0x8 "WIZ16B8M4CT2_CMN_PLL1_DSM_FBH_OVRD_M0__CMN_PLL1_DSM_DIAG_M0,PLL 1 delta sigma modulator diagnostics register mode 0" bitfld.long 0x8 15. "CMN_PLL1_DSM_DIAG_M0_15,Delta sigma bypass enable: When set to 1'b1 the delta sigma modulator will be bypassed and the output will be the value specified for the internal pll_fb_div_integer signal." "0,1" newline bitfld.long 0x8 14. "CMN_PLL1_DSM_DIAG_M0_14,PLL feedback divider override enable : When active (1'b1) the feedback divider low and high override values in the PLL 1 delta sigma modulator feedback divider value high override register mode 0 on page 123 and PLL 1 delta sigma.." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "CMN_PLL1_DSM_DIAG_M0_3_0,PLL feedback divider latency adjustment: This signal specifies a value to be subtracted from the feedback divider settings before they are output on the cmnda_pll1_fb_div_high and cmnda_pll1_fb_div_low signals." wgroup.long 0x1B0++0xF line.long 0x0 "WIZ16B8M4CT2_CMN_PLL1_SS_CTRL2_M0__CMN_PLL1_SS_CTRL1_M0,PLL 1 spread spectrum control register 1 mode 0" hexmask.long.word 0x0 16.--30. 1. "CMN_PLL1_SS_CTRL2_M0_14_0,Amplitude step size: Value of the amplitude_step_size pin on the spread spectrum waveform generator. Note that this field should not be set to 0 when spread spectrum is enabled." newline bitfld.long 0x0 1. "CMN_PLL1_SS_CTRL1_M0_1,Spread spectrum waveform generator disable: Setting this bit to a 1'b1 will disable the spread spectrum waveform generator." "0,1" newline bitfld.long 0x0 0. "CMN_PLL1_SS_CTRL1_M0_0,Spread spectrum enable during VCO calibration : Setting this bit to a 1'b1 will enable the spread spectrum function while VCO calibration is taking place." "0,1" line.long 0x4 "WIZ16B8M4CT2_CMN_PLL1_SS_CTRL4_M0__CMN_PLL1_SS_CTRL3_M0,PLL 1 spread spectrum control register 3 mode 0" hexmask.long.byte 0x4 16.--22. 1. "CMN_PLL1_SS_CTRL4_M0_6_0,Time step size: Value for the time_step_size pin on the spread spectrum waveform generator. Note that this field should not be set to 0 when spread spectrum is enabled." newline hexmask.long.byte 0x4 0.--6. 1. "CMN_PLL1_SS_CTRL3_M0_6_0,Number of steps: Value of the num_steps pin on the spread spectrum waveform generator. Note that this field should not be set to 0 when spread spectrum is enabled." line.long 0x8 "WIZ16B8M4CT2_CMN_PLL1_LOCK_REFCNT_IDLE__CMN_PLL1_LOCK_REFCNT_START,PLL 1 lock reference counter start value register" hexmask.long.word 0x8 0.--11. 1. "CMN_PLL1_LOCK_REFCNT_START_11_0,PLL lock reference counter start value : This is the value that is loaded into the PLL lock detect reference counter as the starting point for that counter when checking for PLL lock. Note that the value required here.." line.long 0xC "WIZ16B8M4CT2_CMN_PLL1_LOCK_PLLCNT_THR__CMN_PLL1_LOCK_PLLCNT_START,PLL 1 lock PLL counter start value register" hexmask.long.word 0xC 16.--27. 1. "CMN_PLL1_LOCK_PLLCNT_THR_11_0,PLL lock counter threshold value : This is the value used by the PLL lock detection logic to determine if the PLL has locked. If the two counters in the PLL lock detection logic differ by less than this value the PLL is.." newline hexmask.long.word 0xC 0.--11. 1. "CMN_PLL1_LOCK_PLLCNT_START_11_0,PLL lock PLL counter start value : This is the value that is loaded into the PLL lock detect PLL counter as the starting point for that counter when checking for PLL lock. The value is the number of PLL feedback divider.." wgroup.long 0x204++0x7 line.long 0x0 "WIZ16B8M4CT2_CMN_TXPUCAL_TUNE__CMN_TXPUCAL_START,TX pull-up resistor calibration start register" hexmask.long.byte 0x0 16.--22. 1. "CMN_TXPUCAL_TUNE_6_0,Resistor calibration tune value: The value of this field is added to the automatically calibrated code or the override code if override is enabled. Note that this value is a twos complement value so the calibrated code can be.." line.long 0x4 "WIZ16B8M4CT2_CMN_TXPUCAL_ITER_TMR__CMN_TXPUCAL_INIT_TMR,TX pull-up resistor calibration initialization timer register" hexmask.long.byte 0x4 16.--22. 1. "CMN_TXPUCAL_ITER_TMR_6_0,Iteration wait timer value: This is the number of cmn_ref_clk clocks to wait between when a value is placed on the resistor selection bus going to the analog and when the comparator value coming from the analog circuits can be.." newline hexmask.long.byte 0x4 0.--6. 1. "CMN_TXPUCAL_INIT_TMR_6_0,Initialization wait timer value: This is the number of cmn_ref_clk clocks to wait between when the analog resistor calibration circuits are enabled and when the first resistor selection values are placed on the resistor.." wgroup.long 0x214++0x7 line.long 0x0 "WIZ16B8M4CT2_CMN_TXPDCAL_TUNE__CMN_TXPDCAL_START,TX pull-down resistor calibration start register" hexmask.long.byte 0x0 16.--22. 1. "CMN_TXPDCAL_TUNE_6_0,Resistor calibration tune value: The value of this field is added to the automatically calibrated code or the override code if override is enabled. Note that this value is a twos complement value so the calibrated code can be.." line.long 0x4 "WIZ16B8M4CT2_CMN_TXPDCAL_ITER_TMR__CMN_TXPDCAL_INIT_TMR,TX pull-down resistor calibration initialization timer register" hexmask.long.byte 0x4 16.--22. 1. "CMN_TXPDCAL_ITER_TMR_6_0,Iteration wait timer value: This is the number of cmn_ref_clk clocks to wait between when a value is placed on the resistor selection bus going to the analog and when the comparator value coming from the analog circuits can be.." newline hexmask.long.byte 0x4 0.--6. 1. "CMN_TXPDCAL_INIT_TMR_6_0,Initialization wait timer value: This is the number of cmn_ref_clk clocks to wait between when the analog resistor calibration circuits are enabled and when the first resistor selection values are placed on the resistor.." wgroup.long 0x228++0x3 line.long 0x0 "WIZ16B8M4CT2_CMN_RXCAL_ITER_TMR__CMN_RXCAL_INIT_TMR,RX resistor calibration initialization timer register" hexmask.long.word 0x0 16.--27. 1. "CMN_RXCAL_ITER_TMR_11_0,Iteration wait timer value: This is the number of cmn_ref_clk clocks to wait between when a value is placed on the resistor selection bus going to the analog and when the comparator value coming from the analog circuits can be.." newline hexmask.long.word 0x0 0.--11. 1. "CMN_RXCAL_INIT_TMR_11_0,Initialization wait timer value: This is the number of cmn_ref_clk clocks to wait between when the analog resistor calibration circuits are enabled and when the first resistor selection values are placed on the resistor selection.." wgroup.long 0x248++0xB line.long 0x0 "WIZ16B8M4CT2_CMN_SD_CAL_ITER_TMR__CMN_SD_CAL_INIT_TMR,Signal detect clock calibration initialization timer register" hexmask.long.byte 0x0 16.--23. 1. "CMN_SD_CAL_ITER_TMR_7_0,Iteration wait timer value: This is the number of clocks to wait between when a calibration code is driven to the analog and when the clock rates are measured. Note that this results in the minimum number of cmn_ref_clk clocks.." newline hexmask.long.byte 0x0 0.--7. 1. "CMN_SD_CAL_INIT_TMR_7_0,Initialization wait timer value: This is the number of clocks to wait between when the analog calibration circuits are enabled and when the first calibration code is driven to the analog. Note that this results in the minimum.." line.long 0x4 "WIZ16B8M4CT2_CMN_SD_CAL_REFTIM_START,Signal detect clock calibration reference clock timer start value register" hexmask.long.byte 0x4 0.--7. 1. "CMN_SD_CAL_REFTIM_START_7_0,Calibration reference clock timer start value : This is the value that is loaded into the reference clock timer as the starting point for that timer when running calibration. Note that the actual number of clocks counted is.." line.long 0x8 "WIZ16B8M4CT2_CMN_SD_CAL_PLLCNT_START,Signal detect clock calibration PLL clock counter start value register" hexmask.long.word 0x8 0.--9. 1. "CMN_SD_CAL_PLLCNT_START_9_0,Calibration feedback clock counter start value : This is the value that is loaded into the PLL clock counter as the starting point for that counter when running calibration. Note that the actual number of clocks counted is.." wgroup.long 0x340++0x3 line.long 0x0 "WIZ16B8M4CT2_CMN_PDIAG_PLL0_CLK_SEL_M0__CMN_PDIAG_PLL0_CTRL_M0,PLL 0 control register mode 0" bitfld.long 0x0 31. "CMN_PDIAG_PLL0_CLK_SEL_M0_15,PLL 0 clock 1 divider enable: This bit enables the divider used to generate the cmnda_pll0_clk_1 from the PLL high speed clock." "0,1" newline bitfld.long 0x0 28.--30. "CMN_PDIAG_PLL0_CLK_SEL_M0_14_12,PLL 0 clock 1 divider select: This field selects the divider value used to generate the cmnda_pll0_clk_1 from the PLL high speed clock by driving the cmnda_pll0_clk_1_div_sel signal to the analog. The encoding of this.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--27. 1. "CMN_PDIAG_PLL0_CLK_SEL_M0_11_8,PLL 0 clock 0 and derived reference clock divider select: This field selects the divider value used to generate the cmnda_pll0_clk_0 and derived reference clock from the PLL high speed clock by driving the.." newline bitfld.long 0x0 16.--17. "CMN_PDIAG_PLL0_CLK_SEL_M0_1_0,PLL 0 clock select: This field selects one of 3 possible high speed output clocks from PLL 0 to drive on the high speed analog clock 0 by driving the cmnda_pll0_clk_sel signal to the analog. The encoding for this is as.." "0: Divide by 1 2'b01: Divide by 2 2'b10: Divide by..,?,?,?" newline hexmask.long.byte 0x0 12.--15. 1. "CMN_PDIAG_PLL0_CTRL_M0_15_12,This field controls the Ring VCO Frequency drift with temperature. It controls the mix of vtref bias and external bias to keep the temperature drift for the ring low by driving the cmnda_pll0_vco_ring_cmos_sel signal going.." newline bitfld.long 0x0 8. "CMN_PDIAG_PLL0_CTRL_M0_8,PLL VCO select: Selects the VCO mode of operation by driving the cmnda_pll0_vco_sel signal going into the common analog. 1'b0: LC tank mode 1'b1: Ring oscillator mode" "0: LC tank mode 1'b1: Ring oscillator mode,?" newline bitfld.long 0x0 5. "CMN_PDIAG_PLL0_CTRL_M0_5,PLL feedback divider clock select: This signal selects which internal PLL clock will be used to drive the cmnda_pll0_fb_divider_clk by driving the cmnda_pll0_fb_divider_clk_sel signal going into the common analog. 1'b0: Feedback.." "0: Feedback divider clock 1'b1: PLL digital rate..,?" newline bitfld.long 0x0 4. "CMN_PDIAG_PLL0_CTRL_M0_4,PLL feedback divider pre-scale: controls the feedback divider pre-scale by driving the cmnda_pll0_div24_sel signal going into the common analog. One should read the description of the PLL in section 10.4 Dual VCO PLL on page.." "0: Divide by 2,1: Divide by 4" newline bitfld.long 0x0 0.--1. "CMN_PDIAG_PLL0_CTRL_M0_1_0,PLL PFD reset delay: Controls the minimum reset pulse width for the PFD. This drives the cmnda_pll0_pfd_rst_dly signal going into the common analog. The following lists the reset pulse width values for typical conditions for.." "0: Delay = 257,1: Delay = 337,2: Delay = 415,3: Delay = 493" wgroup.long 0x348++0x7 line.long 0x0 "WIZ16B8M4CT2_CMN_PDIAG_PLL0_CP_IADJ_M0__CMN_PDIAG_PLL0_CP_PADJ_M0,PLL 0 charge pump proportional path adjust register mode 0" hexmask.long.byte 0x0 24.--31. 1. "CMN_PDIAG_PLL0_CP_IADJ_M0_15_8,PLL charge pump integral path capacitance adjust: Adjusts the charge pump integral path capacitance by driving the cmnda_pll0_cp_int_cap_adj signal going to the analog." newline hexmask.long.byte 0x0 16.--23. 1. "CMN_PDIAG_PLL0_CP_IADJ_M0_7_0,PLL charge pump integral path current adjust: Adjusts the charge pump integral path current by driving the cmnda_pll0_cp_int_cur_adj signal going to the analog." newline hexmask.long.byte 0x0 8.--15. 1. "CMN_PDIAG_PLL0_CP_PADJ_M0_15_8,PLL charge pump proportional path capacitance adjust: Adjusts the charge pump proportional path capacitance by driving the cmnda_pll0_cp_prop_cap_adj signal going to the analog." newline hexmask.long.byte 0x0 0.--7. 1. "CMN_PDIAG_PLL0_CP_PADJ_M0_7_0,PLL charge pump proportional path current adjust: Adjusts the charge pump proportional path current by driving the cmnda_pll0_cp_prop_cur_adj signal going to the analog." line.long 0x4 "WIZ16B8M4CT2_CMN_PDIAG_PLL0_CP_TUNE_M0__CMN_PDIAG_PLL0_FILT_PADJ_M0,PLL 0 proportional path filter adjust register mode 0" hexmask.long.byte 0x4 8.--11. 1. "CMN_PDIAG_PLL0_FILT_PADJ_M0_11_8,PLL proportional path filter capacitance adjust: Adjusts the proportional path filter capacitance by driving the cmnda_pll0_filt_c_adj signal going to the analog." newline hexmask.long.byte 0x4 0.--3. 1. "CMN_PDIAG_PLL0_FILT_PADJ_M0_3_0,PLL proportional path filter resistance adjust: Adjusts the proportional path filter resistance by driving the cmnda_pll0_filt_r_adj signal going to the analog." wgroup.long 0x360++0x3 line.long 0x0 "WIZ16B8M4CT2_CMN_PDIAG_PLL0_CLK_SEL_M1__CMN_PDIAG_PLL0_CTRL_M1,PLL 0 control register mode 1" hexmask.long.byte 0x0 12.--15. 1. "CMN_PDIAG_PLL0_CTRL_M1_15_12,This field controls the Ring VCO Frequency drift with temperature. It controls the mix of vtref bias and external bias to keep the temperature drift for the ring low by driving the cmnda_pll0_vco_ring_cmos_sel signal going.." newline bitfld.long 0x0 8. "CMN_PDIAG_PLL0_CTRL_M1_8,PLL VCO select: Selects the VCO mode of operation by driving the cmnda_pll0_vco_sel signal going into the common analog. 1'b0: LC tank mode 1'b1: Ring oscillator mode" "0: LC tank mode 1'b1: Ring oscillator mode,?" newline bitfld.long 0x0 5. "CMN_PDIAG_PLL0_CTRL_M1_5,PLL feedback divider clock select: This signal selects which internal PLL clock will be used to drive the cmnda_pll0_fb_divider_clk driving the cmnda_pll0_fb_divider_clk_sel signal going into the common analog. 1'b0: Feedback.." "0: Feedback divider clock 1'b1: PLL digital rate..,?" newline bitfld.long 0x0 4. "CMN_PDIAG_PLL0_CTRL_M1_4,PLL feedback divider pre-scale: controls the feedback divider pre-scale by driving the cmnda_pll0_div24_sel signal going into the common analog. One should read the description of the PLL in section 10.4 Dual VCO PLL on page.." "0: Divide by 2,1: Divide by 4" newline bitfld.long 0x0 0.--1. "CMN_PDIAG_PLL0_CTRL_M1_1_0,PLL PFD reset delay: Controls the minimum reset pulse width for the PFD. This drives the cmnda_pll0_pfd_rst_dly signal going into the common analog. The following lists the reset pulse width values for typical conditions for.." "0: Delay = 257,1: Delay = 337,2: Delay = 415,3: Delay = 493" wgroup.long 0x368++0x7 line.long 0x0 "WIZ16B8M4CT2_CMN_PDIAG_PLL0_CP_IADJ_M1__CMN_PDIAG_PLL0_CP_PADJ_M1,PLL 0 charge pump proportional path adjust register mode 1" hexmask.long.byte 0x0 24.--31. 1. "CMN_PDIAG_PLL0_CP_IADJ_M1_15_8,PLL charge pump integral path capacitance adjust: Adjusts the charge pump integral path capacitance by driving the cmnda_pll0_cp_int_cap_adj signal going to the analog." newline hexmask.long.byte 0x0 16.--23. 1. "CMN_PDIAG_PLL0_CP_IADJ_M1_7_0,PLL charge pump integral path current adjust: Adjusts the charge pump integral path current by driving the cmnda_pll0_cp_int_cur_adj signal going to the analog." newline hexmask.long.byte 0x0 8.--15. 1. "CMN_PDIAG_PLL0_CP_PADJ_M1_15_8,PLL charge pump proportional path capacitance adjust: Adjusts the charge pump proportional path capacitance by driving the cmnda_pll0_cp_prop_cap_adj signal going to the analog." newline hexmask.long.byte 0x0 0.--7. 1. "CMN_PDIAG_PLL0_CP_PADJ_M1_7_0,PLL charge pump proportional path current adjust: Adjusts the charge pump proportional path current by driving the cmnda_pll0_cp_prop_cur_adj signal going to the analog." line.long 0x4 "WIZ16B8M4CT2_CMN_PDIAG_PLL0_CP_TUNE_M1__CMN_PDIAG_PLL0_FILT_PADJ_M1,PLL 0 proportional path filter adjust register mode 1" hexmask.long.byte 0x4 8.--11. 1. "CMN_PDIAG_PLL0_FILT_PADJ_M1_11_8,PLL proportional path filter capacitance adjust: Adjusts the proportional path filter capacitance by driving the cmnda_pll0_filt_c_adj signal going to the analog." newline hexmask.long.byte 0x4 0.--3. 1. "CMN_PDIAG_PLL0_FILT_PADJ_M1_3_0,PLL proportional path filter resistance adjust: Adjusts the proportional path filter resistance by driving the cmnda_pll0_filt_r_adj signal going to the analog." wgroup.long 0x380++0x3 line.long 0x0 "WIZ16B8M4CT2_CMN_PDIAG_PLL1_CLK_SEL_M0__CMN_PDIAG_PLL1_CTRL_M0,PLL 1 control register mode 0" bitfld.long 0x0 31. "CMN_PDIAG_PLL1_CLK_SEL_M0_15,PLL 1 clock 1 divider enable: This bit enables the divider used to generate the cmnda_pll1_clk_1 from the PLL high speed clock." "0,1" newline bitfld.long 0x0 28.--30. "CMN_PDIAG_PLL1_CLK_SEL_M0_14_12,PLL 1 clock 1 divider select: This field selects the divider value used to generate the cmnda_pll1_clk_1 from the PLL high speed clock by driving the cmnda_pll1_clk_1_div_sel signal to the analog. The encoding of this.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--27. 1. "CMN_PDIAG_PLL1_CLK_SEL_M0_11_8,PLL 1 clock 0 and derived reference clock divider select: This field selects the divider value used to generate the cmnda_pll1_clk_0 and derived reference clock from the PLL high speed clock by driving the.." newline bitfld.long 0x0 16.--17. "CMN_PDIAG_PLL1_CLK_SEL_M0_1_0,PLL 1 clock select: This field selects one of 3 possible high speed output clocks from PLL 1 to drive on the high speed analog clock 1 by driving the cmnda_pll1_clk_sel signal to the analog. The encoding for this is as.." "0: Divide by 1 2'b01: Divide by 2 2'b10: Divide by..,?,?,?" newline hexmask.long.byte 0x0 12.--15. 1. "CMN_PDIAG_PLL1_CTRL_M0_15_12,This field controls the Ring VCO Frequency drift with temperature. It controls the mix of vtref bias and external bias to keep the temperature drift for the ring low by driving the cmnda_pll1_vco_ring_cmos_sel signal going.." newline bitfld.long 0x0 8. "CMN_PDIAG_PLL1_CTRL_M0_8,PLL VCO select: Selects the VCO mode of operation by driving the cmnda_pll1_vco_sel signal going into the common analog. 1'b0: LC tank mode 1'b1: Ring oscillator mode" "0: LC tank mode 1'b1: Ring oscillator mode,?" newline bitfld.long 0x0 5. "CMN_PDIAG_PLL1_CTRL_M0_5,PLL feedback divider clock select: This signal selects which internal PLL clock will be used to drive the cmnda_pll1_fb_divider_clk driving the cmnda_pll1_fb_divider_clk_sel signal going into the common analog. 1'b0: Feedback.." "0: Feedback divider clock 1'b1: PLL digital rate..,?" newline bitfld.long 0x0 4. "CMN_PDIAG_PLL1_CTRL_M0_4,PLL feedback divider pre-scale: controls the feedback divider pre-scale by driving the cmnda_pll1_div24_sel signal going into the common analog. One should read the description of the PLL in section 10.4 Dual VCO PLL on page.." "0: Divide by 2,1: Divide by 4" newline bitfld.long 0x0 0.--1. "CMN_PDIAG_PLL1_CTRL_M0_1_0,PLL PFD reset delay: Controls the minimum reset pulse width for the PFD. This drives the cmnda_pll1_pfd_rst_dly signal going into the common analog. The following lists the reset pulse width values for typical conditions for.." "0: Delay = 257,1: Delay = 337,2: Delay = 415,3: Delay = 493" wgroup.long 0x388++0x7 line.long 0x0 "WIZ16B8M4CT2_CMN_PDIAG_PLL1_CP_IADJ_M0__CMN_PDIAG_PLL1_CP_PADJ_M0,PLL 1 charge pump proportional path adjust register mode 0" hexmask.long.byte 0x0 24.--31. 1. "CMN_PDIAG_PLL1_CP_IADJ_M0_15_8,PLL charge pump integral path capacitance adjust: Adjusts the charge pump integral path capacitance by driving the cmnda_pll1_cp_int_cap_adj signal going to the analog." newline hexmask.long.byte 0x0 16.--23. 1. "CMN_PDIAG_PLL1_CP_IADJ_M0_7_0,PLL charge pump integral path current adjust: Adjusts the charge pump integral path current by driving the cmnda_pll1_cp_int_cur_adj signal going to the analog." newline hexmask.long.byte 0x0 8.--15. 1. "CMN_PDIAG_PLL1_CP_PADJ_M0_15_8,PLL charge pump proportional path capacitance adjust: Adjusts the charge pump proportional path capacitance by driving the cmnda_pll1_cp_prop_cap_adj signal going to the analog." newline hexmask.long.byte 0x0 0.--7. 1. "CMN_PDIAG_PLL1_CP_PADJ_M0_7_0,PLL charge pump proportional path current adjust: Adjusts the charge pump proportional path current by driving the cmnda_pll0_cp_prop_cur_adj signal going to the analog." line.long 0x4 "WIZ16B8M4CT2_CMN_PDIAG_PLL1_CP_TUNE_M0__CMN_PDIAG_PLL1_FILT_PADJ_M0,PLL 1 proportional path filter adjust register mode 0" hexmask.long.byte 0x4 8.--11. 1. "CMN_PDIAG_PLL1_FILT_PADJ_M0_11_8,PLL proportional path filter capacitance adjust: Adjusts the proportional path filter capacitance by driving the cmnda_pll1_filt_c_adj signal going to the analog." newline hexmask.long.byte 0x4 0.--3. 1. "CMN_PDIAG_PLL1_FILT_PADJ_M0_3_0,PLL proportional path filter resistance adjust: Adjusts the proportional path filter resistance by driving the cmnda_pll1_filt_r_adj signal going to the analog." wgroup.long 0x3C0++0x3 line.long 0x0 "WIZ16B8M4CT2_CMN_DIAG_BIAS_OVRD1__CMN_DIAG_BANDGAP_OVRD,Bandgap override register" bitfld.long 0x0 28.--30. "CMN_DIAG_BIAS_OVRD1_14_12,Receiver resistor calibration current adjust: This field is used to adjust the receiver resistor calibration bias current. It drives the cmnda_bias_rx_rescal_adj signal going to the analog. The following list shows the.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "CMN_DIAG_BIAS_OVRD1_10_8,Transmitter resistor calibration current adjust: This field is used to adjust the transmitter resistor calibration bias current. It drives the cmnda_bias_tx_rescal_adj signal going to the analog. The following list shows the.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 20.--23. 1. "CMN_DIAG_BIAS_OVRD1_7_4,Reserved - spare" newline bitfld.long 0x0 16. "CMN_DIAG_BIAS_OVRD1_0,Reserved - spare" "0,1" rgroup.long 0x400++0x3 line.long 0x0 "WIZ16B8M4CT2_MOD_VER,The Module and Version Register identifies the module identifier and revision of the WIZ16B8M4CT2 module." bitfld.long 0x0 30.--31. "SCHEME,Module Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Module Business Unit" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,WIZ16B8M4CT2 module ID." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VERSION,RTL Version." newline bitfld.long 0x0 8.--10. "MAJOR_REVISION,Major Revision." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM_REVISION,Custom Revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REVISION,Minor Revision." rgroup.long 0x404++0xF line.long 0x0 "WIZ16B8M4CT2_SERDES_CTRL,Sets the SERDES control state." bitfld.long 0x0 31. "POR_EN,The por_en allows the system to place the SERDES in a reset state Access to the SERDES registers are ignored." "0,1" line.long 0x4 "WIZ16B8M4CT2_SERDES_TOP_CTRL,The SERDES Top Level Control" bitfld.long 0x4 30.--31. "PMA_CMN_REFCLK_MODE,The PMA common differential reference clock mode - Sets the mode of operation for differential reference clock input. Must be set before the de-assertion of apb_preset_n/phy_reset_n. 2'b00 - 100 MHz and greater differential.." "?,?,2: Less than 100 MHz differential reference clock,3: Less than 100 MHz single ended DC coupled test.." newline bitfld.long 0x4 28.--29. "PMA_CMN_REFCLK_INT_MODE,The PMA common internal reference clock mode - Sets the mode of operation for internal reference clock input. Must be set before the de-assertion of apb_preset_n/phy_reset_n. 2'b00 - Reserved 2'b01 - 100 MHz and greater.." "0: Reserved 2'b01,?,2: Reserved 2'b11,?" newline bitfld.long 0x4 26.--27. "PMA_CMN_REFCLK_DIG_DIV,The PMA common reference clock digital divide ratio select - Must be set before the de-assertion of apb_preset_n/phy_reset_n. 2'b00 - Divide by 1 (set for reference clock in the 19.2 to 27MHz range) 2'b01 - Divide by 2.." "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8" newline bitfld.long 0x4 23. "PHY_PMA_SUSPEND_OVERRIDE,The PHY PMA common suspend override enable: 1 = disables suspending the PMA common when all links are in low power state (L1 SS PCIe P2 USB P3 power down disabled etc.). 0 = PMA common will be suspended when all links are in.." "0: PMA common will be suspended when all links are..,1: disables suspending the PMA common when all.." line.long 0x8 "WIZ16B8M4CT2_SERDES_RST,The SERDES Reset Register controls the Phy reset and REFCLK selection for the SERDES." bitfld.long 0x8 31. "PHY_RESET_N,The PHY reset : Asserting this signal low will reset all PHY logic for the entire PHY with the exception of the APB registers and TAP controller. Note: Upon de-assertion all PHY inputs must be driven as described in the PIPE specification.." "0,1" newline bitfld.long 0x8 30. "PHY_EN_REFCLK,The PHY reference clock enable: When cmn_refclk_

is configured as a reference clock output 1 = glitch-less enable of the reference clock output. 0 = glitch-less turn off reference clock output. Used in L1.x entry/exit protocol. Note:.." "0: glitch-less turn off reference clock output,1: glitch-less enable of the reference clock output" newline bitfld.long 0x8 29. "PLL1_REFCLK_SEL,The PMA common PLL1 reference clock source select - 0 - Selects cmn_refclk_ as reference clock source 1 - Selects pma_cmn_refclk_int as reference clock source. Note: This field is write protected when register field ~iphy_reset_n.." "0: Selects cmn_refclk_ as reference clock..,?" newline bitfld.long 0x8 28. "PLL0_REFCLK_SEL,The PMA common PLL0 reference clock source select - 0 - Selects cmn_refclk_ as reference clock source 1 - Selects pma_cmn_refclk_int as reference clock source. Note: This field is write protected when register field ~iphy_reset_n.." "0: Selects cmn_refclk_ as reference clock..,?" newline bitfld.long 0x8 27. "REFCLK_TERM_DIS,The PMA common differential reference clock termination disable - enables/disables termination for difference reference clock input (cmn_refclk_

). Must be set before the de-assertion of apb_preset_n/phy_reset_n. 1 = termination.." "0: termination enabled,1: termination disabled" newline bitfld.long 0x8 24. "REFCLK_DIG_SEL,The PMA common reference clock select - Selects the reference clock source for the digital logic between cmn_refclk_

and pma_cmn_refclk_int. Must be set before the de-assertion of apb_preset_n/phy_reset_n. 0 - cmn_refclk_

1 -.." "0: cmn_refclk_

1,?" line.long 0xC "WIZ16B8M4CT2_SERDES_TYPEC,The SERDES Type C control register allows the external lanes selection to be swapped." bitfld.long 0xC 31. "LN23_SWAP,The~iln23_swap will swap the lanes 2 and 3. That is all control for lane 2 will apply to lane 3 and vice versa. You cannot set ~iln23_swap to swap lanes in a link. That is If lanes 2 and 3 are used for a single link of PCIe the ~iln23_swap.." "0,1" newline bitfld.long 0xC 30. "LN10_SWAP,The ~iln10_swap will swap the lanes 0 and 1. That is all control for lane 0 will apply to lane 1 and vice versa. You cannot set ~iln10_swap to swap lanes in a link. That is If lanes 0 and 1 are used for a single link of PCIe the ~iln10_swap.." "0,1" rgroup.long 0x440++0xF line.long 0x0 "WIZ16B8M4CT2_IRQSTATUS_RAW_SYS,The System Interrupt Raw Status Register holds the raw status of the SERDES power timout interrupts." bitfld.long 0x0 3. "P3_PHY_PWR_TIMEOUT_SYS,Phy Power Timeout occured for lane 3 error. That is the lane power state took too long to occur.. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no.." "0,1" newline bitfld.long 0x0 2. "P2_PHY_PWR_TIMEOUT_SYS,Phy Power Timeout occured for lane 2 error. That is the lane power state took too long to occur.. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no.." "0,1" newline bitfld.long 0x0 1. "P1_PHY_PWR_TIMEOUT_SYS,Phy Power Timeout occured for lane 1 error. That is the lane power state took too long to occur.. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no.." "0,1" newline bitfld.long 0x0 0. "P0_PHY_PWR_TIMEOUT_SYS,Phy Power Timeout occured for lane 0 error. That is the lane power state took too long to occur.. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no.." "0,1" line.long 0x4 "WIZ16B8M4CT2_IRQSTATUS_SYS,The System Interrupt Status Register holds the masked status for the SERDES power timout interrupts." bitfld.long 0x4 3. "P3_PHY_PWR_TIMEOUT_SYS,Phy Power Timeout occured for lane 3 error. That is the lane power state took too long to occur.. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no.." "0,1" newline bitfld.long 0x4 2. "P2_PHY_PWR_TIMEOUT_SYS,Phy Power Timeout occured for lane 2 error. That is the lane power state took too long to occur.. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no.." "0,1" newline bitfld.long 0x4 1. "P1_PHY_PWR_TIMEOUT_SYS,Phy Power Timeout occured for lane 1 error. That is the lane power state took too long to occur.. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no.." "0,1" newline bitfld.long 0x4 0. "P0_PHY_PWR_TIMEOUT_SYS,Phy Power Timeout occured for lane 0 error. That is the lane power state took too long to occur.. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no.." "0,1" line.long 0x8 "WIZ16B8M4CT2_IRQENABLE_SET_SYS,The System Interrupt Enable Set Register holds the interrupt enable status of the SERDES power timout interrupts." bitfld.long 0x8 3. "EN_P3_PHY_PWR_TIMEOUT_SYS,Interrupt Enable set for Phy Power Timeout for lane 3 error. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 2. "EN_P2_PHY_PWR_TIMEOUT_SYS,Interrupt Enable set for Phy Power Timeout for lane 2 error. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 1. "EN_P1_PHY_PWR_TIMEOUT_SYS,Interrupt Enable set for Phy Power Timeout for lane 1 error. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 0. "EN_P0_PHY_PWR_TIMEOUT_SYS,Interrupt Enable set for Phy Power Timeout for lane 0 error. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" line.long 0xC "WIZ16B8M4CT2_IRQENABLE_CLR_SYS,The System Interrupt Enable Clear Register holds the interrupt enable status of the SERDES power timout interrupts." bitfld.long 0xC 3. "EN_P3_PHY_PWR_TIMEOUT_SYS,Interrupt Enable clear for Phy Power Timeout for lane 3 error. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 2. "EN_P2_PHY_PWR_TIMEOUT_SYS,Interrupt Enable clear for Phy Power Timeout for lane 2 error. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 1. "EN_P1_PHY_PWR_TIMEOUT_SYS,Interrupt Enable clear for Phy Power Timeout for lane 1 error. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 0. "EN_P0_PHY_PWR_TIMEOUT_SYS,Interrupt Enable clear for Phy Power Timeout for lane 0 error. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" rgroup.long 0x480++0x7 line.long 0x0 "WIZ16B8M4CT2_LANECTL0,The Lane Control Register sets the lane specific modes of operation." bitfld.long 0x0 31. "P0_ENABLE,The p0_enable is AND'd with the IPx_LNy_reset_n to enable the lane." "0,1" newline bitfld.long 0x0 30. "P0_FORCE_ENABLE,The p0_force_enable is OR'd with the IPx_LNy_reset_n to force enable the lane." "0,1" newline bitfld.long 0x0 29. "P0_ALIGN,The p0_align will auto align the RAW interface to 8B10B comma characters." "0,1" newline bitfld.long 0x0 28. "P0_RAW_AUTO_START,The p0_raw_auto_start will auto sequence the RAW interface according to the configuration settings" "0,1" newline bitfld.long 0x0 24.--25. "P0_STANDARD_MODE,Standard Mode specified by Cadence." "0,1,2,3" newline bitfld.long 0x0 22.--23. "P0_FULLRT_DIV,Full Rate divider for 2x MAC speed mode. The PMA PLL full rate clock divider select - divide ratio for pma_pllclk_fullrt_ln_*. 00 = Divide by 1 01 = Divide by 2 10 = Divide by 4 11 = Divide by 8" "0: Divide by 1,1: Divide by 2,?,?" newline bitfld.long 0x0 20.--21. "P0_MAC_SRC_SEL,MAC clock source select : Selects which PMA clock to use as clock souse for pcs_mac_clk*_ln_*. 2'b00 - PMA output xcvr_pll_clk_datart_ln_* for the associated lane. 2'b01 - PMA output xcvr_pll_clk_fullrt_ln_* for the associated lane." "0: PMA output xcvr_pll_clk_datart_ln_* for the..,1: PMA output xcvr_pll_clk_fullrt_ln_* for the..,2: PMA output cmn_ref_clk_rcv,3: Reserved" newline bitfld.long 0x0 18.--19. "P0_REFCLK_SEL,Refclk Select determines which clocks will be used for the IP refclk signal. 0 - pma_pllclk_fullrt_ln_0 is used. 1 - pcs_mac_clk_ln_0 is used. 2 - pcs_mac_clk_divx0_ln_0 is used. 3 - pcs_mac_clk_divx1_ln_0 is used." "0: pma_pllclk_fullrt_ln_0 is used,1: pcs_mac_clk_ln_0 is used,2: pcs_mac_clk_divx0_ln_0 is used,3: pcs_mac_clk_divx1_ln_0 is used" newline bitfld.long 0x0 8.--9. "P0_TXFCLK_SEL,Fclk Select determines which clocks will be used for the IP txfclk signal. 0 - pma_pllclk_fullrt_ln_0 is used. 1 - pcs_mac_clk_ln_0 is used. 2 - pcs_mac_clk_divx0_ln_0 is used. 3 - pcs_mac_clk_divx1_ln_0 is used." "0: pma_pllclk_fullrt_ln_0 is used,1: pcs_mac_clk_ln_0 is used,2: pcs_mac_clk_divx0_ln_0 is used,3: pcs_mac_clk_divx1_ln_0 is used" newline bitfld.long 0x0 6.--7. "P0_RXFCLK_SEL,Fclk Select determines which clocks will be used for the IP rxfclk signal. 0 - pma_rx_rd_clk2x_ln_0 is used. 1 - pma_rx_rd_clk_ln_0 is used. 2 - rd_div2_clk0 is used. 3 - rd_div4_clk0 is used." "0: pma_rx_rd_clk2x_ln_0 is used,1: pma_rx_rd_clk_ln_0 is used,2: rd_div2_clk0 is used,3: rd_div4_clk0 is used" line.long 0x4 "WIZ16B8M4CT2_LANEDIV0,The Lane Divider Register sets the lane specific dividers of" hexmask.long.byte 0x4 16.--22. 1. "P0_MAC_DIV_SEL0,The ~ip0_mac_div_sel0 controls the divider for lane 0 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx0_ln_*. 7'd0 : Reserved 7'd1 : Divide by 1 7'd2 : Divide by 2 7'd3 : Divide by 3 ... 7'dn :.." newline hexmask.long.word 0x4 0.--8. 1. "P0_MAC_DIV_SEL1,The ~ip0_mac_div_sel1 controls the divider for lane 0 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx1_ln_*. 9'd0 : Reserved 9'd1 : Divide by 1 9'd2 : Divide by 2 9'd3 : Divide by 3 ... 9'dn :.." rgroup.long 0x488++0x7 line.long 0x0 "WIZ16B8M4CT2_LANALIGN0,The Lane Align reports the 8B10B alignment delay from the Comma aligner when 8B10B protocol is used in RAW mode." bitfld.long 0x0 8. "P0_ALIGN_RX_DETECT,The ~ip0_align_rx_detect indicates that alignment has happened and The ~ip0_align_rx_delay is valid." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "P0_ALIGN_RX_DELAY,The ~ip0_align_rx_delay indicates the number of bits that are added to align the data to an 8B10B alignment. This value should be added to the latency of the receiver so that an accurate time of Time Sync packets can be calculated." line.long 0x4 "WIZ16B8M4CT2_LANESTS0,The lane Status reports the lane state information for debug purposes." bitfld.long 0x4 4.--5. "P0_IP_SEL,The ~ip0_ip_sel indicates the current IP lane selection for the lane." "0,1,2,3" newline bitfld.long 0x4 1. "P0_MASTER,The ~ip0_master indicates the lane is a base lane for a multi lane link. When '1' Lane is lane 0 of a multi lane link When '0' lane is part of a multi lane link." "0,1" rgroup.long 0x4C0++0x7 line.long 0x0 "WIZ16B8M4CT2_LANECTL1,The Lane Control Register sets the lane specific modes of operation." bitfld.long 0x0 31. "P1_ENABLE,The p1_enable is AND'd with the IPx_LNy_reset_n to enable the lane." "0,1" newline bitfld.long 0x0 30. "P1_FORCE_ENABLE,The p1_force_enable is OR'd with the IPx_LNy_reset_n to force enable the lane." "0,1" newline bitfld.long 0x0 29. "P1_ALIGN,The p1_align will auto align the RAW interface to 8B10B comma characters." "0,1" newline bitfld.long 0x0 28. "P1_RAW_AUTO_START,The p1_raw_auto_start will auto sequence the RAW interface according to the configuration settings" "0,1" newline bitfld.long 0x0 24.--25. "P1_STANDARD_MODE,Standard Mode specified by Cadence." "0,1,2,3" newline bitfld.long 0x0 22.--23. "P1_FULLRT_DIV,Full Rate divider for 2x MAC speed mode. The PMA PLL full rate clock divider select - divide ratio for pma_pllclk_fullrt_ln_*. 00 = Divide by 1 01 = Divide by 2 10 = Divide by 4 11 = Divide by 8" "0: Divide by 1,1: Divide by 2,?,?" newline bitfld.long 0x0 20.--21. "P1_MAC_SRC_SEL,MAC clock source select : Selects which PMA clock to use as clock souse for pcs_mac_clk*_ln_*. 2'b00 - PMA output xcvr_pll_clk_datart_ln_* for the associated lane. 2'b01 - PMA output xcvr_pll_clk_fullrt_ln_* for the associated lane." "0: PMA output xcvr_pll_clk_datart_ln_* for the..,1: PMA output xcvr_pll_clk_fullrt_ln_* for the..,2: PMA output cmn_ref_clk_rcv,3: Reserved" newline bitfld.long 0x0 18.--19. "P1_REFCLK_SEL,Refclk Select determines which clocks will be used for the IP refclk signal. 0 - pma_pllclk_fullrt_ln_1 is used. 1 - pcs_mac_clk_ln_1 is used. 2 - pcs_mac_clk_divx0_ln_1 is used. 3 - pcs_mac_clk_divx1_ln_1 is used." "0: pma_pllclk_fullrt_ln_1 is used,1: pcs_mac_clk_ln_1 is used,2: pcs_mac_clk_divx0_ln_1 is used,3: pcs_mac_clk_divx1_ln_1 is used" newline bitfld.long 0x0 8.--9. "P1_TXFCLK_SEL,Fclk Select determines which clocks will be used for the IP txfclk signal. 0 - pma_pllclk_fullrt_ln_1 is used. 1 - pcs_mac_clk_ln_1 is used. 2 - pcs_mac_clk_divx0_ln_1 is used. 3 - pcs_mac_clk_divx1_ln_1 is used." "0: pma_pllclk_fullrt_ln_1 is used,1: pcs_mac_clk_ln_1 is used,2: pcs_mac_clk_divx0_ln_1 is used,3: pcs_mac_clk_divx1_ln_1 is used" newline bitfld.long 0x0 6.--7. "P1_RXFCLK_SEL,Fclk Select determines which clocks will be used for the IP rxfclk signal. 0 - pma_rx_rd_clk2x_ln_1 is used. 1 - pma_rx_rd_clk_ln_1 is used. 2 - rd_div2_clk1 is used. 3 - rd_div4_clk1 is used." "0: pma_rx_rd_clk2x_ln_1 is used,1: pma_rx_rd_clk_ln_1 is used,2: rd_div2_clk1 is used,3: rd_div4_clk1 is used" line.long 0x4 "WIZ16B8M4CT2_LANEDIV1,The Lane Divider Register sets the lane specific dividers of" hexmask.long.byte 0x4 16.--22. 1. "P1_MAC_DIV_SEL0,The ~ip1_mac_div_sel0 controls the divider for lane 1 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx0_ln_*. 7'd0 : Reserved 7'd1 : Divide by 1 7'd2 : Divide by 2 7'd3 : Divide by 3 ... 7'dn :.." newline hexmask.long.word 0x4 0.--8. 1. "P1_MAC_DIV_SEL1,The ~ip1_mac_div_sel1 controls the divider for lane 1 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx1_ln_*. 9'd0 : Reserved 9'd1 : Divide by 1 9'd2 : Divide by 2 9'd3 : Divide by 3 ... 9'dn :.." rgroup.long 0x4C8++0x7 line.long 0x0 "WIZ16B8M4CT2_LANALIGN1,The Lane Align reports the 8B10B alignment delay from the Comma aligner when 8B10B protocol is used in RAW mode." bitfld.long 0x0 8. "P1_ALIGN_RX_DETECT,The ~ip1_align_rx_detect indicates that alignment has happened and The ~ip1_align_rx_delay is valid." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "P1_ALIGN_RX_DELAY,The ~ip1_align_rx_delay indicates the number of bits that are added to align the data to an 8B10B alignment. This value should be added to the latency of the receiver so that an accurate time of Time Sync packets can be calculated." line.long 0x4 "WIZ16B8M4CT2_LANESTS1,The lane Status reports the lane state information for debug purposes." bitfld.long 0x4 4.--5. "P1_IP_SEL,The ~ip1_ip_sel indicates the current IP lane selection for the lane." "0,1,2,3" newline bitfld.long 0x4 1. "P1_MASTER,The ~ip1_master indicates the lane is a base lane for a multi lane link. When '1' Lane is lane 0 of a multi lane link When '0' lane is part of a multi lane link." "0,1" rgroup.long 0x500++0x7 line.long 0x0 "WIZ16B8M4CT2_LANECTL2,The Lane Control Register sets the lane specific modes of operation." bitfld.long 0x0 31. "P2_ENABLE,The p2_enable is AND'd with the IPx_LNy_reset_n to enable the lane." "0,1" newline bitfld.long 0x0 30. "P2_FORCE_ENABLE,The p2_force_enable is OR'd with the IPx_LNy_reset_n to force enable the lane." "0,1" newline bitfld.long 0x0 29. "P2_ALIGN,The p2_align will auto align the RAW interface to 8B10B comma characters." "0,1" newline bitfld.long 0x0 28. "P2_RAW_AUTO_START,The p2_raw_auto_start will auto sequence the RAW interface according to the configuration settings" "0,1" newline bitfld.long 0x0 24.--25. "P2_STANDARD_MODE,Standard Mode specified by Cadence." "0,1,2,3" newline bitfld.long 0x0 22.--23. "P2_FULLRT_DIV,Full Rate divider for 2x MAC speed mode. The PMA PLL full rate clock divider select - divide ratio for pma_pllclk_fullrt_ln_*. 00 = Divide by 1 01 = Divide by 2 10 = Divide by 4 11 = Divide by 8" "0: Divide by 1,1: Divide by 2,?,?" newline bitfld.long 0x0 20.--21. "P2_MAC_SRC_SEL,MAC clock source select : Selects which PMA clock to use as clock souse for pcs_mac_clk*_ln_*. 2'b00 - PMA output xcvr_pll_clk_datart_ln_* for the associated lane. 2'b01 - PMA output xcvr_pll_clk_fullrt_ln_* for the associated lane." "0: PMA output xcvr_pll_clk_datart_ln_* for the..,1: PMA output xcvr_pll_clk_fullrt_ln_* for the..,2: PMA output cmn_ref_clk_rcv,3: Reserved" newline bitfld.long 0x0 18.--19. "P2_REFCLK_SEL,Refclk Select determines which clocks will be used for the IP refclk signal. 0 - pma_pllclk_fullrt_ln_2 is used. 1 - pcs_mac_clk_ln_2 is used. 2 - pcs_mac_clk_divx0_ln_2 is used. 3 - pcs_mac_clk_divx1_ln_2 is used." "0: pma_pllclk_fullrt_ln_2 is used,1: pcs_mac_clk_ln_2 is used,2: pcs_mac_clk_divx0_ln_2 is used,3: pcs_mac_clk_divx1_ln_2 is used" newline bitfld.long 0x0 8.--9. "P2_TXFCLK_SEL,Fclk Select determines which clocks will be used for the IP txfclk signal. 0 - pma_pllclk_fullrt_ln_2 is used. 1 - pcs_mac_clk_ln_2 is used. 2 - pcs_mac_clk_divx0_ln_2 is used. 3 - pcs_mac_clk_divx1_ln_2 is used." "0: pma_pllclk_fullrt_ln_2 is used,1: pcs_mac_clk_ln_2 is used,2: pcs_mac_clk_divx0_ln_2 is used,3: pcs_mac_clk_divx1_ln_2 is used" newline bitfld.long 0x0 6.--7. "P2_RXFCLK_SEL,Fclk Select determines which clocks will be used for the IP rxfclk signal. 0 - pma_rx_rd_clk2x_ln_2 is used. 1 - pma_rx_rd_clk_ln_2 is used. 2 - rd_div2_clk2 is used. 3 - rd_div4_clk2 is used." "0: pma_rx_rd_clk2x_ln_2 is used,1: pma_rx_rd_clk_ln_2 is used,2: rd_div2_clk2 is used,3: rd_div4_clk2 is used" line.long 0x4 "WIZ16B8M4CT2_LANEDIV2,The Lane Divider Register sets the lane specific dividers of" hexmask.long.byte 0x4 16.--22. 1. "P2_MAC_DIV_SEL0,The ~ip2_mac_div_sel0 controls the divider for lane 2 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx0_ln_*. 7'd0 : Reserved 7'd1 : Divide by 1 7'd2 : Divide by 2 7'd3 : Divide by 3 ... 7'dn :.." newline hexmask.long.word 0x4 0.--8. 1. "P2_MAC_DIV_SEL1,The ~ip2_mac_div_sel1 controls the divider for lane 2 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx1_ln_*. 9'd0 : Reserved 9'd1 : Divide by 1 9'd2 : Divide by 2 9'd3 : Divide by 3 ... 9'dn :.." rgroup.long 0x508++0x7 line.long 0x0 "WIZ16B8M4CT2_LANALIGN2,The Lane Align reports the 8B10B alignment delay from the Comma aligner when 8B10B protocol is used in RAW mode." bitfld.long 0x0 8. "P2_ALIGN_RX_DETECT,The ~ip2_align_rx_detect indicates that alignment has happened and The ~ip2_align_rx_delay is valid." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "P2_ALIGN_RX_DELAY,The ~ip2_align_rx_delay indicates the number of bits that are added to align the data to an 8B10B alignment. This value should be added to the latency of the receiver so that an accurate time of Time Sync packets can be calculated." line.long 0x4 "WIZ16B8M4CT2_LANESTS2,The lane Status reports the lane state information for debug purposes." bitfld.long 0x4 4.--5. "P2_IP_SEL,The ~ip2_ip_sel indicates the current IP lane selection for the lane." "0,1,2,3" newline bitfld.long 0x4 1. "P2_MASTER,The ~ip2_master indicates the lane is a base lane for a multi lane link. When '1' Lane is lane 0 of a multi lane link When '0' lane is part of a multi lane link." "0,1" rgroup.long 0x540++0x7 line.long 0x0 "WIZ16B8M4CT2_LANECTL3,The Lane Control Register sets the lane specific modes of operation." bitfld.long 0x0 31. "P3_ENABLE,The p3_enable is AND'd with the IPx_LNy_reset_n to enable the lane." "0,1" newline bitfld.long 0x0 30. "P3_FORCE_ENABLE,The p3_force_enable is OR'd with the IPx_LNy_reset_n to force enable the lane." "0,1" newline bitfld.long 0x0 29. "P3_ALIGN,The p3_align will auto align the RAW interface to 8B10B comma characters." "0,1" newline bitfld.long 0x0 28. "P3_RAW_AUTO_START,The p3_raw_auto_start will auto sequence the RAW interface according to the configuration settings" "0,1" newline bitfld.long 0x0 24.--25. "P3_STANDARD_MODE,Standard Mode specified by Cadence." "0,1,2,3" newline bitfld.long 0x0 22.--23. "P3_FULLRT_DIV,Full Rate divider for 2x MAC speed mode. The PMA PLL full rate clock divider select - divide ratio for pma_pllclk_fullrt_ln_*. 00 = Divide by 1 01 = Divide by 2 10 = Divide by 4 11 = Divide by 8" "0: Divide by 1,1: Divide by 2,?,?" newline bitfld.long 0x0 20.--21. "P3_MAC_SRC_SEL,MAC clock source select : Selects which PMA clock to use as clock souse for pcs_mac_clk*_ln_*. 2'b00 - PMA output xcvr_pll_clk_datart_ln_* for the associated lane. 2'b01 - PMA output xcvr_pll_clk_fullrt_ln_* for the associated lane." "0: PMA output xcvr_pll_clk_datart_ln_* for the..,1: PMA output xcvr_pll_clk_fullrt_ln_* for the..,2: PMA output cmn_ref_clk_rcv,3: Reserved" newline bitfld.long 0x0 18.--19. "P3_REFCLK_SEL,Refclk Select determines which clocks will be used for the IP refclk signal. 0 - pma_pllclk_fullrt_ln_3 is used. 1 - pcs_mac_clk_ln_3 is used. 2 - pcs_mac_clk_divx0_ln_3 is used. 3 - pcs_mac_clk_divx1_ln_3 is used." "0: pma_pllclk_fullrt_ln_3 is used,1: pcs_mac_clk_ln_3 is used,2: pcs_mac_clk_divx0_ln_3 is used,3: pcs_mac_clk_divx1_ln_3 is used" newline bitfld.long 0x0 8.--9. "P3_TXFCLK_SEL,Fclk Select determines which clocks will be used for the IP txfclk signal. 0 - pma_pllclk_fullrt_ln_3 is used. 1 - pcs_mac_clk_ln_3 is used. 2 - pcs_mac_clk_divx0_ln_3 is used. 3 - pcs_mac_clk_divx1_ln_3 is used." "0: pma_pllclk_fullrt_ln_3 is used,1: pcs_mac_clk_ln_3 is used,2: pcs_mac_clk_divx0_ln_3 is used,3: pcs_mac_clk_divx1_ln_3 is used" newline bitfld.long 0x0 6.--7. "P3_RXFCLK_SEL,Fclk Select determines which clocks will be used for the IP rxfclk signal. 0 - pma_rx_rd_clk2x_ln_3 is used. 1 - pma_rx_rd_clk_ln_3 is used. 2 - rd_div2_clk3 is used. 3 - rd_div4_clk3 is used." "0: pma_rx_rd_clk2x_ln_3 is used,1: pma_rx_rd_clk_ln_3 is used,2: rd_div2_clk3 is used,3: rd_div4_clk3 is used" line.long 0x4 "WIZ16B8M4CT2_LANEDIV3,The Lane Divider Register sets the lane specific dividers of" hexmask.long.byte 0x4 16.--22. 1. "P3_MAC_DIV_SEL0,The ~ip3_mac_div_sel0 controls the divider for lane 3 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx0_ln_*. 7'd0 : Reserved 7'd1 : Divide by 1 7'd2 : Divide by 2 7'd3 : Divide by 3 ... 7'dn :.." newline hexmask.long.word 0x4 0.--8. 1. "P3_MAC_DIV_SEL1,The ~ip3_mac_div_sel1 controls the divider for lane 3 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx1_ln_*. 9'd0 : Reserved 9'd1 : Divide by 1 9'd2 : Divide by 2 9'd3 : Divide by 3 ... 9'dn :.." rgroup.long 0x548++0x7 line.long 0x0 "WIZ16B8M4CT2_LANALIGN3,The Lane Align reports the 8B10B alignment delay from the Comma aligner when 8B10B protocol is used in RAW mode." bitfld.long 0x0 8. "P3_ALIGN_RX_DETECT,The ~ip3_align_rx_detect indicates that alignment has happened and The ~ip3_align_rx_delay is valid." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "P3_ALIGN_RX_DELAY,The ~ip3_align_rx_delay indicates the number of bits that are added to align the data to an 8B10B alignment. This value should be added to the latency of the receiver so that an accurate time of Time Sync packets can be calculated." line.long 0x4 "WIZ16B8M4CT2_LANESTS3,The lane Status reports the lane state information for debug purposes." bitfld.long 0x4 4.--5. "P3_IP_SEL,The ~ip3_ip_sel indicates the current IP lane selection for the lane." "0,1,2,3" newline bitfld.long 0x4 1. "P3_MASTER,The ~ip3_master indicates the lane is a base lane for a multi lane link. When '1' Lane is lane 0 of a multi lane link When '0' lane is part of a multi lane link." "0,1" rgroup.long 0x5F8++0x7 line.long 0x0 "WIZ16B8M4CT2_DTB_MUX_SEL,The digital test bus mux select determines the value on the test bus." hexmask.long.byte 0x0 0.--4. 1. "DTB_MUX_SEL,See cadence documentation on digital test bus." line.long 0x4 "WIZ16B8M4CT2_DIAG_TEST,The Diagnostic Test Register allows the system to validate the read and write of all data bits." hexmask.long 0x4 0.--31. 1. "DIAG_REG,Diagnostic register. This register allows full read/write of all data bits to be tested." rgroup.long 0x2000++0x3 line.long 0x0 "WIZ16B8M4CT2_RESERVEDBIT13ADDRESSA,Reserved Address bit 13 area A" hexmask.long 0x0 0.--31. 1. "RES_BIT13_ADR_A,Write only test region A" rgroup.long 0x4080++0x3 line.long 0x0 "WIZ16B8M4CT2_TX_TXCC_PRE_OVRD__TX_TXCC_CTRL,TX coefficient controller control register" bitfld.long 0x0 12.--13. "TX_TXCC_CTRL_13_12,Margin multiplier rounding control: This field controls the rounding function on the margin multiplier. 2'b00 : Round to nearest integer 2'b01 : Floor 2'b10 : Ceiling" "0: Round to nearest integer 2'b01 : Floor 2'b10 :..,?,?,?" newline bitfld.long 0x0 10.--11. "TX_TXCC_CTRL_11_10,LF value multiplier rounding control: This field controls the rounding function on the LF value multiplier. 2'b00 : Round to nearest integer 2'b01 : Floor 2'b10 : Ceiling" "0: Round to nearest integer 2'b01 : Floor 2'b10 :..,?,?,?" newline bitfld.long 0x0 8.--9. "TX_TXCC_CTRL_9_8,Calculated post-emphasis multiplier rounding control: This field controls the rounding function on the calculated post-emphasis multiplier. 2'b00 : Round to nearest integer 2'b01 : Floor 2'b10 : Ceiling" "0: Round to nearest integer 2'b01 : Floor 2'b10 :..,?,?,?" newline bitfld.long 0x0 6.--7. "TX_TXCC_CTRL_7_6,Calculated pre-emphasis multiplier rounding control: This field controls the rounding function on the pre-emphasis multiplier. 2'b00 : Round to nearest integer 2'b01 : Floor 2'b10 : Ceiling" "0: Round to nearest integer 2'b01 : Floor 2'b10 :..,?,?,?" newline bitfld.long 0x0 4.--5. "TX_TXCC_CTRL_5_4,Coefficient calculator multiplier rounding control: This field controls the rounding function on the coefficient calculator multiplier. 2'b00 : Round to nearest integer 2'b01 : Floor 2'b10 : Ceiling" "0: Round to nearest integer 2'b01 : Floor 2'b10 :..,?,?,?" newline bitfld.long 0x0 3. "TX_TXCC_CTRL_3,De-emphasis control standard mode 3 value: This bit controls the de-emphasis mode when the xcvr_standard_mode is set to 2'b11. 1'b0 : Use the calculated de-emphasis values based on the 2 least significant bits of the top level.." "0: Use the calculated de-emphasis values based on..,1: Use the coefficient values on all 18 bits of the.." newline bitfld.long 0x0 2. "TX_TXCC_CTRL_2,De-emphasis control standard mode 2 value: This bit controls the de-emphasis mode when the xcvr_standard_mode is set to 2'b10. 1'b0 : Use the calculated de-emphasis values based on the 2 least significant bits of the top level.." "0: Use the calculated de-emphasis values based on..,1: Use the coefficient values on all 18 bits of the.." newline bitfld.long 0x0 1. "TX_TXCC_CTRL_1,De-emphasis control standard mode 1 value: This bit controls the de-emphasis mode when the xcvr_standard_mode is set to 2'b01. 1'b0 : Use the calculated de-emphasis values based on the 2 least significant bits of the top level.." "0: Use the calculated de-emphasis values based on..,1: Use the coefficient values on all 18 bits of the.." newline bitfld.long 0x0 0. "TX_TXCC_CTRL_0,De-emphasis control standard mode 0 value: This bit controls the de-emphasis mode when the xcvr_standard_mode is set to 2'b00. 1'b0 : Use the calculated de-emphasis values based on the 2 least significant bits of the top level.." "0: Use the calculated de-emphasis values based on..,1: Use the coefficient values on all 18 bits of the.." rgroup.long 0x4098++0x3 line.long 0x0 "WIZ16B8M4CT2_TX_TXCC_CPOST_MULT_01__TX_TXCC_CPOST_MULT_00,Calculated post emphasis multiplier value 00 register" hexmask.long.byte 0x0 16.--23. 1. "TX_TXCC_CPOST_MULT_01_7_0,Calculated post emphasis multiplier value 01: The value in this field specifies the multiplier value used to generate the calculated post emphasis value from the FS value when tx_deemphasis[1:0] = 2'b01. The following describes.." newline hexmask.long.byte 0x0 0.--7. 1. "TX_TXCC_CPOST_MULT_00_7_0,Calculated post emphasis multiplier value 00: The value in this field specifies the multiplier value used to generate the calculated post emphasis value from the FS value when tx_deemphasis[1:0] = 2'b00. The following describes.." rgroup.long 0x40A0++0x3 line.long 0x0 "WIZ16B8M4CT2_TX_TXCC_MGNFS_MULT_001__TX_TXCC_MGNFS_MULT_000,Margin full swing multiplier value 000 register" hexmask.long.byte 0x0 0.--7. 1. "TX_TXCC_MGNFS_MULT_000_7_0,Margin full swing multiplier value 000: The value in this field specifies the multiplier value used to generate the margin value from the resistor calibration value when tx_vmargin = 3'b000 and tx_low_power_swing_en = 1'b0." rgroup.long 0x40C8++0xB line.long 0x0 "WIZ16B8M4CT2_TX_TXCC_P5PRE_COEF_MULT__TX_TXCC_P4PRE_COEF_MULT,Preset 4 pre emphasis coefficient multiplier value register" hexmask.long.byte 0x0 16.--23. 1. "TX_TXCC_P5PRE_COEF_MULT_7_0,Preset 5 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 5 pre emphasis coefficient value from the FS value. The following describes the.." line.long 0x4 "WIZ16B8M4CT2_TX_TXCC_P7PRE_COEF_MULT__TX_TXCC_P6PRE_COEF_MULT,Preset 6 pre emphasis coefficient multiplier value register" hexmask.long.byte 0x4 16.--23. 1. "TX_TXCC_P7PRE_COEF_MULT_7_0,Preset 7 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 7 pre emphasis coefficient value from the FS value. The following describes the.." line.long 0x8 "WIZ16B8M4CT2_TX_TXCC_P9PRE_COEF_MULT__TX_TXCC_P8PRE_COEF_MULT,Preset 8 pre emphasis coefficient multiplier value register" hexmask.long.byte 0x8 16.--23. 1. "TX_TXCC_P9PRE_COEF_MULT_7_0,Preset 9 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 9 pre emphasis coefficient value from the FS value. The following describes the.." newline hexmask.long.byte 0x8 0.--7. 1. "TX_TXCC_P8PRE_COEF_MULT_7_0,Preset 8 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 8 pre emphasis coefficient value from the FS value. The following describes the.." rgroup.long 0x40E0++0x7 line.long 0x0 "WIZ16B8M4CT2_TX_TXCC_P1POST_COEF_MULT__TX_TXCC_P0POST_COEF_MULT,Preset 0 post emphasis coefficient multiplier value register" hexmask.long.byte 0x0 16.--23. 1. "TX_TXCC_P1POST_COEF_MULT_7_0,Preset 1 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 1 post emphasis coefficient value from the FS value. The following describes the.." newline hexmask.long.byte 0x0 0.--7. 1. "TX_TXCC_P0POST_COEF_MULT_7_0,Preset 0 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 0 post emphasis coefficient value from the FS value. The following describes the.." line.long 0x4 "WIZ16B8M4CT2_TX_TXCC_P3POST_COEF_MULT__TX_TXCC_P2POST_COEF_MULT,Preset 2 post emphasis coefficient multiplier value register" hexmask.long.byte 0x4 0.--7. 1. "TX_TXCC_P2POST_COEF_MULT_7_0,Preset 2 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 2 post emphasis coefficient value from the FS value. The following describes the.." rgroup.long 0x40EC++0x7 line.long 0x0 "WIZ16B8M4CT2_TX_TXCC_P7POST_COEF_MULT__TX_TXCC_P6POST_COEF_MULT,Preset 6 post emphasis coefficient multiplier value register" hexmask.long.byte 0x0 16.--23. 1. "TX_TXCC_P7POST_COEF_MULT_7_0,Preset 7 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 7 post emphasis coefficient value from the FS value. The following describes the.." line.long 0x4 "WIZ16B8M4CT2_TX_TXCC_P9POST_COEF_MULT__TX_TXCC_P8POST_COEF_MULT,Preset 8 post emphasis coefficient multiplier value register" hexmask.long.byte 0x4 0.--7. 1. "TX_TXCC_P8POST_COEF_MULT_7_0,Preset 8 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 8 post emphasis coefficient value from the FS value. The following describes the.." rgroup.long 0x4180++0x7 line.long 0x0 "WIZ16B8M4CT2_DRV_DIAG_LANE_FCM_EN_SWAIT_TMR__DRV_DIAG_LANE_FCM_EN_TO,Lane fast common mode enable timeout register" bitfld.long 0x0 15. "DRV_DIAG_LANE_FCM_EN_TO_15,Bypass fast establishment of common mode enable: When enabled the fast establishment of common mode function will be bypassed. When bypassed the lane fast common mode enable timeout value field in this register can be used.." "0,1" newline hexmask.long.word 0x0 0.--11. 1. "DRV_DIAG_LANE_FCM_EN_TO_11_0,Lane fast common mode enable timeout value: The usage of the value of this field is a function of the state of the bypass fast establishment of common mode enable bit in this register. Bypass disabled (normal operation): This.." line.long 0x4 "WIZ16B8M4CT2_DRV_DIAG_LANE_FCM_EN_TUNE__DRV_DIAG_LANE_FCM_EN_MGN_TMR,Lane fast common mode enable margin timer register" hexmask.long.word 0x4 0.--11. 1. "DRV_DIAG_LANE_FCM_EN_MGN_TMR_11_0,Lane fast common mode enable margin timer value: This specifies the number of reference clock cycles the fast establishment of common mode process will enable all the margin segments for. The default value of this.." rgroup.long 0x418C++0x3 line.long 0x0 "WIZ16B8M4CT2_DRV_DIAG_TX_DRV,TX driver diagnostic register" bitfld.long 0x0 7. "DRV_DIAG_TX_DRV_7,TX boost enable: Increases the transmitter amplitude for fast data transitions by controlling the txda_drv_boost_en signal going to the analog." "0,1" newline bitfld.long 0x0 4.--5. "DRV_DIAG_TX_DRV_5_4,TX boost tune: Controls the transmitter boost amplitude when the transmitter boost function is enabled using the TX boost enable bit in this register by controlling the txda_drv_boost_tune signal going to the analog. The following.." "0: Minimum Boost 2'b01: 2'b10: 2'b11: Maximum Boost,?,?,?" newline bitfld.long 0x0 1. "DRV_DIAG_TX_DRV_1,TX pre-driver pull up control: When the pre-driver is disabled this bit controls the state of the pre-driver output by controlling the txda_drv_predrv_pullup signal going to the analog. 1'b0 : Pulled low 1'b1 : Pulled high" "0: Pulled low 1'b1 : Pulled high,?" newline bitfld.long 0x0 0. "DRV_DIAG_TX_DRV_0,TX driver margin type: Selects the margining type the driver will operate in by controlling the txda_drv_margin_type signal going to the analog. 1'b0 : Classical margining - High power margining that complies with the driver.." "0: Classical margining,1: Low-Power margining" rgroup.long 0x41C8++0xF line.long 0x0 "WIZ16B8M4CT2_XCVR_DIAG_PLLDRC_CTRL__XCVR_DIAG_XDP_PWRI_STAT,Transceiver transceiver data path power island control status register" bitfld.long 0x0 30.--31. "XCVR_DIAG_PLLDRC_CTRL_15_14,Digital PLL clock select standard mode 3: This bit controls which full rate PLL clock is selected when xcvr_standard_mode is set to 2'b11. 2'b00 : PLL clock 0 from the PLL 0. 2'b01 : PLL clock 1 from the PLL 0. 2'b10 : PLL.." "0: PLL clock 0 from the PLL 0,1: PLL clock 1 from the PLL 0,2: PLL clock 0 from the PLL 1,3: PLL clock 1 from the PLL 1" newline bitfld.long 0x0 28.--29. "XCVR_DIAG_PLLDRC_CTRL_13_12,Digital PLL data rate divider standard mode 3 value: This field will directly control the xcvr_pll_clk_datart_div signal which controls which divided clock is selected when generating the xcvr_pll_clk_datart clock when.." "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8" newline bitfld.long 0x0 26.--27. "XCVR_DIAG_PLLDRC_CTRL_11_10,Digital PLL clock select standard mode 2: This bit controls which full rate PLL clock is selected when xcvr_standard_mode is set to 2'b10. 2'b00 : PLL clock 0 from the PLL 0. 2'b01 : PLL clock 1 from the PLL 0. 2'b10 : PLL.." "0: PLL clock 0 from the PLL 0,1: PLL clock 1 from the PLL 0,2: PLL clock 0 from the PLL 1,3: PLL clock 1 from the PLL 1" newline bitfld.long 0x0 24.--25. "XCVR_DIAG_PLLDRC_CTRL_9_8,Digital PLL data rate divider standard mode 2 value: This field will directly control the xcvr_pll_clk_datart_div signal which controls which divided clock is selected when generating the xcvr_pll_clk_datart clock when.." "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8" newline bitfld.long 0x0 22.--23. "XCVR_DIAG_PLLDRC_CTRL_7_6,Digital PLL clock select standard mode 1: This bit controls which full rate PLL clock is selected when xcvr_standard_mode is set to 2'b01. 2'b00 : PLL clock 0 from the PLL 0. 2'b01 : PLL clock 1 from the PLL 0. 2'b10 : PLL.." "0: PLL clock 0 from the PLL 0,1: PLL clock 1 from the PLL 0,2: PLL clock 0 from the PLL 1,3: PLL clock 1 from the PLL 1" newline bitfld.long 0x0 20.--21. "XCVR_DIAG_PLLDRC_CTRL_5_4,Digital PLL data rate divider standard mode 1 value: This field will directly control the xcvr_pll_clk_datart_div signal which controls which divided clock is selected when generating the xcvr_pll_clk_datart clock when.." "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8" newline bitfld.long 0x0 18.--19. "XCVR_DIAG_PLLDRC_CTRL_3_2,Digital PLL clock select standard mode 0: This bit controls which full rate PLL clock is selected when xcvr_standard_mode is set to 2'b00. 2'b00 : PLL clock 0 from the PLL 0. 2'b01 : PLL clock 1 from the PLL 0. 2'b10 : PLL.." "0: PLL clock 0 from the PLL 0,1: PLL clock 1 from the PLL 0,2: PLL clock 0 from the PLL 1,3: PLL clock 1 from the PLL 1" newline bitfld.long 0x0 16.--17. "XCVR_DIAG_PLLDRC_CTRL_1_0,Digital PLL data rate divider standard mode 0 value: This field will directly control the xcvr_pll_clk_datart_div signal which controls which divided clock is selected when generating the xcvr_pll_clk_datart clock when.." "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8" line.long 0x4 "WIZ16B8M4CT2_XCVR_DIAG_HSCLK_DIV__XCVR_DIAG_HSCLK_SEL,Transceiver high speed clock select register" bitfld.long 0x4 28.--30. "XCVR_DIAG_HSCLK_DIV_14_12,Transceiver clock divider select standard mode 3: This field selects the divider value used to divide the selected analog high speed clock by when generating the transmit and receive clocks when xcvr_standard_mode is set to.." "0: Div 1 3'b001: Div 2 3'b010: Div 3 3'b011: Div 4..,?,?,3: This field selects the divider value used to..,?,?,?,?" newline bitfld.long 0x4 24.--26. "XCVR_DIAG_HSCLK_DIV_10_8,Transceiver clock divider select standard mode 2: This field selects the divider value used to divide the selected analog high speed clock by when generating the transmit and receive clocks when xcvr_standard_mode is set to.." "0: Div 1 3'b001: Div 2 3'b010: Div 3 3'b011: Div 4..,?,2: This field selects the divider value used to..,?,?,?,?,?" newline bitfld.long 0x4 20.--22. "XCVR_DIAG_HSCLK_DIV_6_4,Transceiver clock divider select standard mode 1: This field selects the divider value used to divide the selected analog high speed clock by when generating the transmit and receive clocks when xcvr_standard_mode is set to.." "0: Div 1 3'b001: Div 2 3'b010: Div 3 3'b011: Div 4..,1: This field selects the divider value used to..,?,?,?,?,?,?" newline bitfld.long 0x4 16.--18. "XCVR_DIAG_HSCLK_DIV_2_0,Transceiver clock divider select standard mode 0: This field selects the divider value used to divide the selected analog high speed clock by when generating the transmit and receive clocks when xcvr_standard_mode is set to.." "0: Div 1 3'b001: Div 2 3'b010: Div 3 3'b011: Div 4..,?,?,?,?,?,?,?" newline bitfld.long 0x4 12.--13. "XCVR_DIAG_HSCLK_SEL_13_12,High speed clock select standard mode 3: This specifies which analog high speed clock is selected when xcvr_standard_mode is set to 2'b11 by driving the xcvrda_clk_sel signal to the analog as specified below. 2'b00 : clock 0." "0: clock 0,1: clock 1,2: Reserved,3: Reserved" newline bitfld.long 0x4 8.--9. "XCVR_DIAG_HSCLK_SEL_9_8,High speed clock select standard mode 2: This specifies which analog high speed clock is selected when xcvr_standard_mode is set to 2'b10 by driving the xcvrda_clk_sel signal to the analog as specified below. 2'b00 : clock 0." "0: clock 0,1: clock 1,2: Reserved,3: Reserved" newline bitfld.long 0x4 4.--5. "XCVR_DIAG_HSCLK_SEL_5_4,High speed clock select standard mode 1: This specifies which analog high speed clock is selected when xcvr_standard_mode is set to 2'b01 by driving the xcvrda_clk_sel signal to the analog as specified below. 2'b00 : clock 0." "0: clock 0,1: clock 1,2: Reserved,3: Reserved" newline bitfld.long 0x4 0.--1. "XCVR_DIAG_HSCLK_SEL_1_0,High speed clock select standard mode 0: This specifies which analog high speed clock is selected when xcvr_standard_mode is set to 2'b00 by driving the xcvrda_clk_sel signal to the analog as specified below. 2'b00 : clock 0." "0: clock 0,1: clock 1,2: Reserved,3: Reserved" line.long 0x8 "WIZ16B8M4CT2_XCVR_DIAG_RXCLK_CTRL__XCVR_DIAG_TXCLK_CTRL,TX clock control register" bitfld.long 0x8 31. "XCVR_DIAG_RXCLK_CTRL_15,RX deserializer clock invert: This bit is used to optionally invert the deserializer clock (rxda_des_clk) for diagnostic purposes." "0,1" newline bitfld.long 0x8 30. "XCVR_DIAG_RXCLK_CTRL_14,RX 2x clock enable: This bit enables the receiver 2x clock function by driving the rxda_des_clk_2x_en signal going to the analog. Note that this clock is only designed to be used in modes where the data width is 20 bits. 1'b0 :.." "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x8 29. "XCVR_DIAG_RXCLK_CTRL_13,RX PI E path clock select: Controls which PI clock drives the E path clocks by driving the rxda_pi_i_drv_e_en signal going to the analog. 1'b0: E PI clock 1'b1: IQ PI clock" "0: E PI clock 1'b1: IQ PI clock,?" newline bitfld.long 0x8 23. "XCVR_DIAG_RXCLK_CTRL_7,PI output clock divider enable standard mode 3: This bit controls the rxda_pi_out_clk_div_en to enable the PI output clock divider when xcvr_standard_mode is set to 2'b11. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x8 22. "XCVR_DIAG_RXCLK_CTRL_6,PI output clock divider enable standard mode 2: This bit controls the rxda_pi_out_clk_div_en to enable the PI output clock divider when xcvr_standard_mode is set to 2'b10. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x8 21. "XCVR_DIAG_RXCLK_CTRL_5,PI output clock divider enable standard mode 1: This bit controls the rxda_pi_out_clk_div_en to enable the PI output clock divider when xcvr_standard_mode is set to 2'b01. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,1: This bit controls the rxda_pi_out_clk_div_en to.." newline bitfld.long 0x8 20. "XCVR_DIAG_RXCLK_CTRL_4,PI output clock divider enable standard mode 0: This bit controls the rxda_pi_out_clk_div_en to enable the PI output clock divider when xcvr_standard_mode is set to 2'b00. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,?" line.long 0xC "WIZ16B8M4CT2_XCVR_DIAG_PSC_OVRD__XCVR_DIAG_BIDI_CTRL,Transceiver bidirectional control register" bitfld.long 0xC 19. "XCVR_DIAG_PSC_OVRD_3,Receiver DFE enable mask value standard mode 3: This bit will controls the rx_dfe_eq_enable_std_mask digital signal which can be used to mask off the rxda_dfe_eq_enable signal coming from the power state controller and going into.." "0: The signal will be masked off,1: The signal to pass through unchanged" newline bitfld.long 0xC 18. "XCVR_DIAG_PSC_OVRD_2,Receiver DFE enable mask value standard mode 2: This bit will controls the rx_dfe_eq_enable_std_mask digital signal which can be used to mask off the rxda_dfe_eq_enable signal coming from the power state controller and going into.." "0: The signal will be masked off,1: The signal to pass through unchanged" newline bitfld.long 0xC 17. "XCVR_DIAG_PSC_OVRD_1,Receiver DFE enable mask value standard mode 1: This bit will controls the rx_dfe_eq_enable_std_mask digital signal which can be used to mask off the rxda_dfe_eq_enable signal coming from the power state controller and going into.." "0: The signal will be masked off,1: The signal to pass through unchanged" newline bitfld.long 0xC 16. "XCVR_DIAG_PSC_OVRD_0,Receiver DFE enable mask value standard mode 0: This bit will controls the rx_dfe_eq_enable_std_mask digital signal which can be used to mask off the rxda_dfe_eq_enable signal coming from the power state controller and going into.." "0: The signal will be masked off,1: The signal to pass through unchanged" newline bitfld.long 0xC 7. "XCVR_DIAG_BIDI_CTRL_7,Receiver enable standard mode 3: When bidirectional bumps are implemented in the transceiver this bit is a global enable for the receiver function when xcvr_standard_mode is set to 2'b11. When bidirectional bumps are not.." "0: RX disabled 1'b1 : RX enabled,?" newline bitfld.long 0xC 6. "XCVR_DIAG_BIDI_CTRL_6,Receiver enable standard mode 2: When bidirectional bumps are implemented in the transceiver this bit is a global enable for the receiver function when xcvr_standard_mode is set to 2'b10. When bidirectional bumps are not.." "0: RX disabled 1'b1 : RX enabled,?" newline bitfld.long 0xC 5. "XCVR_DIAG_BIDI_CTRL_5,Receiver enable standard mode 1: When bidirectional bumps are implemented in the transceiver this bit is a global enable for the receiver function when xcvr_standard_mode is set to 2'b01. When bidirectional bumps are not.." "0: RX disabled 1'b1 : RX enabled,1: When bidirectional bumps are implemented in the.." newline bitfld.long 0xC 4. "XCVR_DIAG_BIDI_CTRL_4,Receiver enable standard mode 0: When bidirectional bumps are implemented in the transceiver this bit is a global enable for the receiver function when xcvr_standard_mode is set to 2'b00. When bidirectional bumps are not.." "0: RX disabled 1'b1 : RX enabled,?" newline bitfld.long 0xC 3. "XCVR_DIAG_BIDI_CTRL_3,Transmitter enable standard mode 3: When bidirectional bumps are implemented in the transceiver this bit is a global enable for the transmitter function when xcvr_standard_mode is set to 2'b11. When bidirectional bumps are not.." "0: TX disabled 1'b1 : TX enabled,?" newline bitfld.long 0xC 2. "XCVR_DIAG_BIDI_CTRL_2,Transmitter enable standard mode 2: When bidirectional bumps are implemented in the transceiver this bit is a global enable for the transmitter function when xcvr_standard_mode is set to 2'b10. When bidirectional bumps are not.." "0: TX disabled 1'b1 : TX enabled,?" newline bitfld.long 0xC 1. "XCVR_DIAG_BIDI_CTRL_1,Transmitter enable standard mode 1: When bidirectional bumps are implemented in the transceiver this bit is a global enable for the transmitter function when xcvr_standard_mode is set to 2'b01. When bidirectional bumps are not.." "0: TX disabled 1'b1 : TX enabled,1: When bidirectional bumps are implemented in the.." newline bitfld.long 0xC 0. "XCVR_DIAG_BIDI_CTRL_0,Transmitter enable standard mode 0: When bidirectional bumps are implemented in the transceiver this bit is a global enable for the transmitter function when xcvr_standard_mode is set to 2'b00. When bidirectional bumps are not.." "0: TX disabled 1'b1 : TX enabled,?" rgroup.long 0x4200++0x7 line.long 0x0 "WIZ16B8M4CT2_TX_PSC_A1__TX_PSC_A0,Transmitter A0 power state definition register" bitfld.long 0x0 27. "TX_PSC_A1_11,TX driver common mode enable extend control" "0,1" newline bitfld.long 0x0 26. "TX_PSC_A1_10,Force txda_lfps_sel active" "0,1" newline bitfld.long 0x0 25. "TX_PSC_A1_9,LFPS clock gate enable" "0,1" newline bitfld.long 0x0 24. "TX_PSC_A1_8,Reserved - spare" "0,1" newline bitfld.long 0x0 23. "TX_PSC_A1_7,Transmitter low current mode" "0,1" newline bitfld.long 0x0 22. "TX_PSC_A1_6,Transmitter mission mode enable" "0,1" newline bitfld.long 0x0 21. "TX_PSC_A1_5,TX driver common mode enable" "0,1" newline bitfld.long 0x0 20. "TX_PSC_A1_4,TX driver enable" "0,1" newline bitfld.long 0x0 19. "TX_PSC_A1_3,TX post-emphasis enable (C+1)" "0,1" newline bitfld.long 0x0 18. "TX_PSC_A1_2,TX pre-emphasis enable (C-1)" "0,1" newline bitfld.long 0x0 17. "TX_PSC_A1_1,TX pre-driver enable" "0,1" newline bitfld.long 0x0 16. "TX_PSC_A1_0,TX serializer enable" "0,1" newline bitfld.long 0x0 11. "TX_PSC_A0_11,TX driver common mode enable extend control: Specifies which power states the tx_cmn_mode_en_ext signal is considered valid in and can be used to force the driver to continue to be in the common mode state." "0,1" newline bitfld.long 0x0 10. "TX_PSC_A0_10,Force txda_lfps_sel active: Setting this bit forces the txda_lfps_sel signal going to the analog to be driven active. Note that this function is implemented for additional power savings. In the analog this signal controls a MUX select.." "0,1" newline bitfld.long 0x0 9. "TX_PSC_A0_9,LFPS clock gate enable: Enables the LFPS clock gate when an LFPS clock is required." "0,1" newline bitfld.long 0x0 8. "TX_PSC_A0_8,Reserved - spare" "0,1" newline bitfld.long 0x0 7. "TX_PSC_A0_7,Transmitter low current mode: Enables a low current consumption mode within the common mode voltage circuit in the driver via the txda_drv_idle_lowi_en signal going to the analog." "0,1" newline bitfld.long 0x0 6. "TX_PSC_A0_6,Transmitter mission mode enable: Enables the analog circuits in the driver required to run in mission mode via the txda_drv_mission_en signal going to the analog." "0,1" newline bitfld.long 0x0 5. "TX_PSC_A0_5,TX driver common mode enable: Enables the common mode voltage circuits in the driver." "0,1" newline bitfld.long 0x0 4. "TX_PSC_A0_4,TX driver enable: Enables the transmitter driver via the H bridge driver controller." "0,1" newline bitfld.long 0x0 3. "TX_PSC_A0_3,TX post-emphasis enable (C+1): Enables the transmitter circuits related to the post-emphasis function." "0,1" newline bitfld.long 0x0 2. "TX_PSC_A0_2,TX pre-emphasis enable (C-1): Enables the transmitter circuits related to the pre-emphasis function." "0,1" newline bitfld.long 0x0 1. "TX_PSC_A0_1,TX pre-driver enable: Enables the transmitter pre-driver driver data selection MUX and receiver detect." "0,1" newline bitfld.long 0x0 0. "TX_PSC_A0_0,TX serializer enable: Enables the serializer and related clock divider circuits." "0,1" line.long 0x4 "WIZ16B8M4CT2_TX_PSC_A3__TX_PSC_A2,Transmitter A2 power state definition register" bitfld.long 0x4 27. "TX_PSC_A3_11,TX driver common mode enable extend control" "0,1" newline bitfld.long 0x4 26. "TX_PSC_A3_10,Force txda_lfps_sel active" "0,1" newline bitfld.long 0x4 25. "TX_PSC_A3_9,LFPS clock gate enable" "0,1" newline bitfld.long 0x4 24. "TX_PSC_A3_8,Reserved - spare" "0,1" newline bitfld.long 0x4 23. "TX_PSC_A3_7,Transmitter low current mode" "0,1" newline bitfld.long 0x4 22. "TX_PSC_A3_6,Transmitter mission mode enable" "0,1" newline bitfld.long 0x4 21. "TX_PSC_A3_5,TX driver common mode enable" "0,1" newline bitfld.long 0x4 20. "TX_PSC_A3_4,TX driver enable" "0,1" newline bitfld.long 0x4 19. "TX_PSC_A3_3,TX post-emphasis enable (C+1)" "0,1" newline bitfld.long 0x4 18. "TX_PSC_A3_2,TX pre-emphasis enable (C-1)" "0,1" newline bitfld.long 0x4 17. "TX_PSC_A3_1,TX pre-driver enable" "0,1" newline bitfld.long 0x4 16. "TX_PSC_A3_0,TX serializer enable" "0,1" newline bitfld.long 0x4 11. "TX_PSC_A2_11,TX driver common mode enable extend control" "0,1" newline bitfld.long 0x4 10. "TX_PSC_A2_10,Force txda_lfps_sel active" "0,1" newline bitfld.long 0x4 9. "TX_PSC_A2_9,LFPS clock gate enable" "0,1" newline bitfld.long 0x4 8. "TX_PSC_A2_8,Reserved - spare" "0,1" newline bitfld.long 0x4 7. "TX_PSC_A2_7,Transmitter low current mode" "0,1" newline bitfld.long 0x4 6. "TX_PSC_A2_6,Transmitter mission mode enable" "0,1" newline bitfld.long 0x4 5. "TX_PSC_A2_5,TX driver common mode enable" "0,1" newline bitfld.long 0x4 4. "TX_PSC_A2_4,TX driver enable" "0,1" newline bitfld.long 0x4 3. "TX_PSC_A2_3,TX post-emphasis enable (C+1)" "0,1" newline bitfld.long 0x4 2. "TX_PSC_A2_2,TX pre-emphasis enable (C-1)" "0,1" newline bitfld.long 0x4 1. "TX_PSC_A2_1,TX pre-driver enable" "0,1" newline bitfld.long 0x4 0. "TX_PSC_A2_0,TX serializer enable" "0,1" rgroup.long 0x4244++0x3 line.long 0x0 "WIZ16B8M4CT2_TX_RCVDET_ST_TMR__TX_RCVDET_EN_TMR,Transmit receiver detect enable timer register" hexmask.long.word 0x0 16.--31. 1. "TX_RCVDET_ST_TMR_15_0,Start wait time value: This is the number of clocks the receiver detect state machine waits between driving the txda_rcvdet_start signal active and checking the results on the txda_rcvdet_detected_n signal coming from the analog." rgroup.long 0x43CC++0x3 line.long 0x0 "WIZ16B8M4CT2_TX_DIAG_ACYA__TX_DIAG_DCYA,Transmitter digital cover your alternatives register" hexmask.long.word 0x0 17.--31. 1. "TX_DIAG_ACYA_15_1,Reserved - spare" newline bitfld.long 0x0 16. "TX_DIAG_ACYA_0,HBDC latch control: Controls the state of the latches associated with the H bridge driver controller related signals in the H bridge driver encoder logic digital in the transmitter analog as well as the boost enable and level control.." "0: Latches transparent 1'b1: Latches gated,?" rgroup.long 0x6000++0x3 line.long 0x0 "WIZ16B8M4CT2_RESERVEDBIT13ADDRESSB,Reserved Address bit 13 area B" hexmask.long 0x0 0.--31. 1. "RES_BIT13_ADR_B,Write only test region B" rgroup.long 0x8000++0x7 line.long 0x0 "WIZ16B8M4CT2_RX_PSC_A1__RX_PSC_A0,Receiver A0 power state definition register" bitfld.long 0x0 28. "RX_PSC_A1_12,RX signal detect enable extend control" "0,1" newline bitfld.long 0x0 27. "RX_PSC_A1_11,RX signal detect filter enable" "0,1" newline bitfld.long 0x0 26. "RX_PSC_A1_10,RX LFPS detect filter enable" "0,1" newline bitfld.long 0x0 25. "RX_PSC_A1_9,Reserved - spare" "0,1" newline bitfld.long 0x0 24. "RX_PSC_A1_8,RX signal detect enable" "0,1" newline bitfld.long 0x0 21.--23. "RX_PSC_A1_7_5,Reserved - spare" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RX_PSC_A1_4,RX equalizer engine enable" "0,1" newline bitfld.long 0x0 19. "RX_PSC_A1_3,RX DFE equalization enable." "0,1" newline bitfld.long 0x0 18. "RX_PSC_A1_2,RX PI enable" "0,1" newline bitfld.long 0x0 17. "RX_PSC_A1_1,RX e path enable (calibration and eye surf only)" "0,1" newline bitfld.long 0x0 16. "RX_PSC_A1_0,RX enable" "0,1" newline bitfld.long 0x0 12. "RX_PSC_A0_12,RX signal detect enable extend control: Specifies which power states the rx_sig_det_en_ext signal is considered valid in and can be used to force the signal detect functions to remain on." "0,1" newline bitfld.long 0x0 11. "RX_PSC_A0_11,RX signal detect filter enable: Enables the receiver signal detect filter function in the digital receiver controller." "0,1" newline bitfld.long 0x0 10. "RX_PSC_A0_10,RX LFPS detect filter enable: Enables the receiver LFPS detect filter function in the digital receiver controller." "0,1" newline bitfld.long 0x0 9. "RX_PSC_A0_9,Reserved - spare" "0,1" newline bitfld.long 0x0 8. "RX_PSC_A0_8,RX signal detect enable: Enables the receiver signal detect function. This drives the rxda_sd_en signal going to the analog. Note that this bit needs to be active for LFPS detect functions to work because these functions share the same.." "0,1" newline bitfld.long 0x0 5.--7. "RX_PSC_A0_7_5,Reserved - spare" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "RX_PSC_A0_4,RX equalizer engine enable: Specifies which power state the REE runs in. 1'b0: Disabled 1'b1: Enabled" "0: Disabled 1'b1: Enabled,?" newline bitfld.long 0x0 3. "RX_PSC_A0_3,RX DFE equalization enable: Enables the receiver DFE equalization circuits via the rxda_dfe_eq_enable signal." "0,1" newline bitfld.long 0x0 2. "RX_PSC_A0_2,RX PI enable: Enables the receiver circuits related to the PI and associated clocking components." "0,1" newline bitfld.long 0x0 1. "RX_PSC_A0_1,RX e path enable (calibration and eye surf only) : Enables the receiver circuits related to the eye plot PI and e path deserializer for calibration and eye surf." "0,1" newline bitfld.long 0x0 0. "RX_PSC_A0_0,RX enable: Enables the receiver circuits related to the CDRLF Sampler FE and Deserializer." "0,1" line.long 0x4 "WIZ16B8M4CT2_RX_PSC_A3__RX_PSC_A2,Receiver A2 power state definition register" bitfld.long 0x4 28. "RX_PSC_A3_12,RX signal detect enable extend control" "0,1" newline bitfld.long 0x4 27. "RX_PSC_A3_11,RX signal detect filter enable" "0,1" newline bitfld.long 0x4 26. "RX_PSC_A3_10,RX LFPS detect filter enable" "0,1" newline bitfld.long 0x4 25. "RX_PSC_A3_9,Reserved - spare" "0,1" newline bitfld.long 0x4 24. "RX_PSC_A3_8,RX signal detect enable" "0,1" newline bitfld.long 0x4 21.--23. "RX_PSC_A3_7_5,Reserved - spare" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RX_PSC_A3_4,RX equalizer engine enable" "0,1" newline bitfld.long 0x4 19. "RX_PSC_A3_3,RX DFE equalization enable." "0,1" newline bitfld.long 0x4 18. "RX_PSC_A3_2,RX PI enable" "0,1" newline bitfld.long 0x4 17. "RX_PSC_A3_1,RX e path enable (calibration and eye surf only)" "0,1" newline bitfld.long 0x4 16. "RX_PSC_A3_0,RX enable" "0,1" newline bitfld.long 0x4 12. "RX_PSC_A2_12,RX signal detect enable extend control" "0,1" newline bitfld.long 0x4 11. "RX_PSC_A2_11,RX signal detect filter enable" "0,1" newline bitfld.long 0x4 10. "RX_PSC_A2_10,RX LFPS detect filter enable" "0,1" newline bitfld.long 0x4 9. "RX_PSC_A2_9,Reserved - spare" "0,1" newline bitfld.long 0x4 8. "RX_PSC_A2_8,RX signal detect enable" "0,1" newline bitfld.long 0x4 5.--7. "RX_PSC_A2_7_5,Reserved - spare" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4. "RX_PSC_A2_4,RX equalizer engine enable" "0,1" newline bitfld.long 0x4 3. "RX_PSC_A2_3,RX DFE equalization enable." "0,1" newline bitfld.long 0x4 2. "RX_PSC_A2_2,RX PI enable" "0,1" newline bitfld.long 0x4 1. "RX_PSC_A2_1,RX e path enable (calibration and eye surf only)" "0,1" newline bitfld.long 0x4 0. "RX_PSC_A2_0,RX enable" "0,1" rgroup.long 0x800C++0x3 line.long 0x0 "WIZ16B8M4CT2_RX_PSC_RDY__RX_PSC_CAL,Receiver calibration power state definition register" bitfld.long 0x0 12. "RX_PSC_CAL_12,RX signal detect enable extend control" "0,1" newline bitfld.long 0x0 11. "RX_PSC_CAL_11,RX signal detect filter enable" "0,1" newline bitfld.long 0x0 10. "RX_PSC_CAL_10,RX LFPS detect filter enable" "0,1" newline bitfld.long 0x0 9. "RX_PSC_CAL_9,Reserved - spare" "0,1" newline bitfld.long 0x0 8. "RX_PSC_CAL_8,RX signal detect enable" "0,1" newline bitfld.long 0x0 5.--7. "RX_PSC_CAL_7_5,Reserved - spare" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "RX_PSC_CAL_4,RX equalizer engine enable" "0,1" newline bitfld.long 0x0 3. "RX_PSC_CAL_3,RX DFE equalization enable." "0,1" newline bitfld.long 0x0 2. "RX_PSC_CAL_2,RX PI enable" "0,1" newline bitfld.long 0x0 1. "RX_PSC_CAL_1,RX e path enable (calibration and eye surf only)" "0,1" newline bitfld.long 0x0 0. "RX_PSC_CAL_0,RX enable" "0,1" rgroup.long 0x8088++0x3 line.long 0x0 "WIZ16B8M4CT2_RX_SDCAL0_ITER_TMR__RX_SDCAL0_INIT_TMR,Signal detect calibration 0 initialization timer register" hexmask.long.word 0x0 16.--24. 1. "RX_SDCAL0_ITER_TMR_8_0,Iteration wait timer value: This is the number of cmn_ref_clk clocks to wait between when a value is placed on the calibration code signals going to the analog and when the comparator value coming from the analog circuits can be.." newline hexmask.long.word 0x0 0.--8. 1. "RX_SDCAL0_INIT_TMR_8_0,Initialization wait timer value: This is the number of cmn_ref_clk clocks to wait between when the analog calibration circuits are enabled and when the first values are placed on the calibration code signals going to the analog." rgroup.long 0x8098++0x3 line.long 0x0 "WIZ16B8M4CT2_RX_SDCAL1_ITER_TMR__RX_SDCAL1_INIT_TMR,Signal detect calibration 1 initialization timer register" hexmask.long.word 0x0 16.--24. 1. "RX_SDCAL1_ITER_TMR_8_0,Iteration wait timer value: This is the number of cmn_ref_clk clocks to wait between when a value is placed on the calibration code signals going to the analog and when the comparator value coming from the analog circuits can be.." newline hexmask.long.word 0x0 0.--8. 1. "RX_SDCAL1_INIT_TMR_8_0,Initialization wait timer value: This is the number of cmn_ref_clk clocks to wait between when the analog calibration circuits are enabled and when the first values are placed on the calibration code signals going to the analog." rgroup.long 0x8100++0x7 line.long 0x0 "WIZ16B8M4CT2_RX_CDRLF_CNFG2__RX_CDRLF_CNFG,CDRLF configuration register (!)" bitfld.long 0x0 30. "RX_CDRLF_CNFG2_14,CDRLF second order loop integrator max clear enable: This signal enables the function in the CDRLF where the second order loop integrator is cleared when it reaches the maximum value." "0,1" newline rbitfld.long 0x0 29. "RX_CDRLF_CNFG2_13,CDRLF fast phase lock locked detected: This register bit is the current status of the fphl_locked pin on the CDRLF and indicates the fast phase lock process is complete." "0,1" newline bitfld.long 0x0 28. "RX_CDRLF_CNFG2_12,CDRLF fast phase lock diagnostic enable: This register bit can control the fphl_start pin on the CDRLF. for diagnostic purposes. If the CDRLF fast phase lock enabled by signal detect bit in this register is enabled then either signal.." "0,1" newline bitfld.long 0x0 27. "RX_CDRLF_CNFG2_11,CDRLF fast phase lock enabled by signal detect: When active signal detect will control the fphl_start pin on the CDRLF. This will cause fast phase lock to be enabled whenever the macro detects a transition from electrical idle to high.." "0,1" newline bitfld.long 0x0 26. "RX_CDRLF_CNFG2_10,CDRLF reset on CDRLF PM Accumulator Max: Activating (1'b1) this bit will force the CDRLF to be reset when the PM accumulator in the CDRLF reaches is maximum absolute value (the largest positive or negative value)." "0,1" newline bitfld.long 0x0 25. "RX_CDRLF_CNFG2_9,CDRLF freeze on electrical idle detect: Activating (1'b1) this bit will force the CDRLF to be freeze in its current state when the receiver signal detect detects an electrical idle. When high speed data is detected the freeze will be.." "0,1" newline bitfld.long 0x0 24. "RX_CDRLF_CNFG2_8,CDRLF reset on electrical idle detect: Activating (1'b1) this bit will force the CDRLF to be reset when the receiver signal detect detects an electrical idle. When high speed data is detected the reset will be released." "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "RX_CDRLF_CNFG2_5_0,CDRLF second order loop integrator threshold : This value is the maximum magnitude the CDRLF second order loop integrator will be allowed to go to. Note that this field must never be set to a value less than 2 (6'b000010)." newline bitfld.long 0x0 15. "RX_CDRLF_CNFG_15,CDLRF reset hold: When active (1'b1) the CDRLF will be held in reset beyond the time that it would normally be released by its asynchronous release signals. The CDRLF will be held in reset until this bit is deactivated (1'b0). Note:.." "0,1" newline bitfld.long 0x0 12.--14. "RX_CDRLF_CNFG_14_12,CDRLF diagnostic mode control: This field controls the information driven on the rx_pi_val_ln_{15:0}[7:0] signal when in diagnostics mode." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "RX_CDRLF_CNFG_11,CDRLF second order loop disable: Activating (1'b1) this bit will disable the CDRLF second order loop. Note: This signal is intended be for verification purposes only. It should be set to 1'b0 for normal operation." "0,1" newline hexmask.long.byte 0x0 6.--10. 1. "RX_CDRLF_CNFG_10_6,CDRLF second order loop sigma delta update rate: This is the value that is added to or subtracted from the second order loop accumulator register when the serial data sample clock is detected as being out of phase with the serial data.." newline bitfld.long 0x0 5. "RX_CDRLF_CNFG_5,CDRLF first order loop disable: Activating (1'b1) this bit will disable the CDRLF first order loop. Note: This signal is intended to be for verification purposes only. It should be set to 1'b0 for normal operation." "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "RX_CDRLF_CNFG_4_0,CDRLF first order loop sigma delta update rate: This is the value that is added to or subtracted from the first order loop accumulator register when the serial data sample clock is detected as being out of phase with the serial data on.." line.long 0x4 "WIZ16B8M4CT2_RX_CDRLF_MGN_DIAG__RX_CDRLF_CNFG3,CDRLF configuration register 3 (!)" bitfld.long 0x4 3. "RX_CDRLF_CNFG3_3,CDRLF data filter enable standard mode 3 : Enables the filter function for the data that feeds into the CDRLF from the deserializer using the rxda_cdrlf_data_filter_en_n signal when xcvr_standard_mode is set to 2'b11. 1'b0 : Enable.." "0: Enable filter of 1010 patterns from the CDRLF,1: No CDRLF data filter function enabled" newline bitfld.long 0x4 2. "RX_CDRLF_CNFG3_2,CDRLF data filter enable standard mode 2 : Enables the filter function for the data that feeds into the CDRLF from the deserializer using the rxda_cdrlf_data_filter_en_n signal when xcvr_standard_mode is set to 2'b10. 1'b0 : Enable.." "0: Enable filter of 1010 patterns from the CDRLF,1: No CDRLF data filter function enabled" newline bitfld.long 0x4 1. "RX_CDRLF_CNFG3_1,CDRLF data filter enable standard mode 1 : Enables the filter function for the data that feeds into the CDRLF from the deserializer using the rxda_cdrlf_data_filter_en_n signal when xcvr_standard_mode is set to 2'b01. 1'b0 : Enable.." "0: Enable filter of 1010 patterns from the CDRLF,1: No CDRLF data filter function enabled" newline bitfld.long 0x4 0. "RX_CDRLF_CNFG3_0,CDRLF data filter enable standard mode 0 : Enables the filter function for the data that feeds into the CDRLF from the deserializer using the rxda_cdrlf_data_filter_en_n signal when xcvr_standard_mode is set to 2'b00. 1'b0 : Enable.." "0: Enable filter of 1010 patterns from the CDRLF,1: No CDRLF data filter function enabled" rgroup.long 0x8120++0x3 line.long 0x0 "WIZ16B8M4CT2_RX_SIGDET_HL_DLY_TMR__RX_SIGDET_HL_FILT_TMR,Receiver signal detect filter high to low filter timer register (!)" hexmask.long.byte 0x0 16.--21. 1. "RX_SIGDET_HL_DLY_TMR_5_0,Signal detect filter high to low delay timer value: This is the value loaded into the delay timer in the signal detect high to low filter circuit." newline hexmask.long.byte 0x0 0.--5. 1. "RX_SIGDET_HL_FILT_TMR_5_0,Signal detect filter high to low filter timer value: This is the value loaded into the filter timer in the signal detect high to low filter circuit." rgroup.long 0x8210++0x7 line.long 0x0 "WIZ16B8M4CT2_RX_REE_GCSM1_EQENM_PH1__RX_REE_GCSM1_CTRL,REE general control state machine 1 control register" bitfld.long 0x0 31. "RX_REE_GCSM1_EQENM_PH1_15,Reserved - spare" "0,1" newline bitfld.long 0x0 30. "RX_REE_GCSM1_EQENM_PH1_14,Ignore 1010 controller : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x0 29. "RX_REE_GCSM1_EQENM_PH1_13,TX equalization evaluator : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x0 28. "RX_REE_GCSM1_EQENM_PH1_12,TX post cursor control : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x0 27. "RX_REE_GCSM1_EQENM_PH1_11,TX pre cursor control : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x0 26. "RX_REE_GCSM1_EQENM_PH1_10,Short channel correction : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x0 25. "RX_REE_GCSM1_EQENM_PH1_9,RX attenuation : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x0 24. "RX_REE_GCSM1_EQENM_PH1_8,RX VGA gain : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x0 23. "RX_REE_GCSM1_EQENM_PH1_7,RX offset correction coefficient : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x0 22. "RX_REE_GCSM1_EQENM_PH1_6,RX peaking amp gain : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x0 21. "RX_REE_GCSM1_EQENM_PH1_5,RX low frequency equalizer adaptive control : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x0 20. "RX_REE_GCSM1_EQENM_PH1_4,Reserved - spare" "0,1" newline bitfld.long 0x0 19. "RX_REE_GCSM1_EQENM_PH1_3,Reserved - spare" "0,1" newline bitfld.long 0x0 18. "RX_REE_GCSM1_EQENM_PH1_2,RX tap 3 : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x0 17. "RX_REE_GCSM1_EQENM_PH1_1,RX tap 2 : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x0 16. "RX_REE_GCSM1_EQENM_PH1_0,RX tap 1 : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "?,1: When set to 1'b1" newline bitfld.long 0x0 3. "RX_REE_GCSM1_CTRL_3,Equalization function reset enable: Enables the reset of the functions controlled by this state machine using the rx_ree_fcn_reset_n signal when the equalization mode changes. 1'b1 : Enabled 1'b0 : Disabled" "?,1: Enabled 1'b0 : Disabled" newline bitfld.long 0x0 2. "RX_REE_GCSM1_CTRL_2,Loop enable: Controls when the equalization functions in this state machine are run one time or loop continuously." "0,1" newline bitfld.long 0x0 1. "RX_REE_GCSM1_CTRL_1,Force run equalization: Setting this bit to a 1'b1 will force the general control state machine to run independent of the macro functions that normally run the equalization." "0,1" newline bitfld.long 0x0 0. "RX_REE_GCSM1_CTRL_0,Enable: This bit enables the general control state machine function. 1'b1 : Enabled 1'b0 : Disabled" "?,1: Enabled 1'b0 : Disabled" line.long 0x4 "WIZ16B8M4CT2_RX_REE_GCSM1_START_TMR__RX_REE_GCSM1_EQENM_PH2,REE general control state machine 1 phase 2 equalization enable mask register" bitfld.long 0x4 15. "RX_REE_GCSM1_EQENM_PH2_15,Reserved - spare" "0,1" newline bitfld.long 0x4 14. "RX_REE_GCSM1_EQENM_PH2_14,Ignore 1010 controller : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x4 13. "RX_REE_GCSM1_EQENM_PH2_13,TX equalization evaluator : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x4 12. "RX_REE_GCSM1_EQENM_PH2_12,TX post cursor control : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x4 11. "RX_REE_GCSM1_EQENM_PH2_11,TX pre cursor control : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x4 10. "RX_REE_GCSM1_EQENM_PH2_10,Short channel correction : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x4 9. "RX_REE_GCSM1_EQENM_PH2_9,RX attenuation : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x4 8. "RX_REE_GCSM1_EQENM_PH2_8,RX VGA gain : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x4 7. "RX_REE_GCSM1_EQENM_PH2_7,RX offset correction coefficient : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x4 6. "RX_REE_GCSM1_EQENM_PH2_6,RX peaking amp gain : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x4 5. "RX_REE_GCSM1_EQENM_PH2_5,RX low frequency equalizer adaptive control : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x4 4. "RX_REE_GCSM1_EQENM_PH2_4,Reserved - spare" "0,1" newline bitfld.long 0x4 3. "RX_REE_GCSM1_EQENM_PH2_3,Reserved - spare" "0,1" newline bitfld.long 0x4 2. "RX_REE_GCSM1_EQENM_PH2_2,RX tap 3 : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x4 1. "RX_REE_GCSM1_EQENM_PH2_1,RX tap 2 : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x4 0. "RX_REE_GCSM1_EQENM_PH2_0,RX tap 1 : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "?,1: When set to 1'b1" rgroup.long 0x8220++0x3 line.long 0x0 "WIZ16B8M4CT2_RX_REE_GCSM2_EQENM_PH1__RX_REE_GCSM2_CTRL,REE general control state machine 2 control register" bitfld.long 0x0 3. "RX_REE_GCSM2_CTRL_3,Equalization function reset enable: Enables the reset of the functions controlled by this state machine using the rx_ree_fcn_reset_n signal when the equalization mode changes. 1'b1 : Enabled 1'b0 : Disabled" "?,1: Enabled 1'b0 : Disabled" newline bitfld.long 0x0 2. "RX_REE_GCSM2_CTRL_2,Loop enable: Controls when the equalization functions in this state machine are run one time or loop continuously." "0,1" newline bitfld.long 0x0 1. "RX_REE_GCSM2_CTRL_1,Force run equalization: Setting this bit to a 1'b1 will force the general control state machine to run independent of the macro functions that normally run the equalization." "0,1" newline bitfld.long 0x0 0. "RX_REE_GCSM2_CTRL_0,Enable: This bit enables the general control state machine function. 1'b1 : Enabled 1'b0 : Disabled" "?,1: Enabled 1'b0 : Disabled" rgroup.long 0x8230++0x3 line.long 0x0 "WIZ16B8M4CT2_RX_REE_PERGCSM_EQENM_PH1__RX_REE_PERGCSM_CTRL,REE periodic general control state machine control register" bitfld.long 0x0 3. "RX_REE_PERGCSM_CTRL_3,Equalization function reset enable: Enables the reset of the functions controlled by this state machine using the rx_ree_fcn_reset_n pin when the equalization mode changes. 1'b1 : Enabled 1'b0 : Disabled" "?,1: Enabled 1'b0 : Disabled" newline bitfld.long 0x0 2. "RX_REE_PERGCSM_CTRL_2,Loop enable: Controls when the equalization functions in this state machine are run one time or loop continuously." "0,1" newline bitfld.long 0x0 1. "RX_REE_PERGCSM_CTRL_1,Force run equalization: Setting this bit to a 1'b1 will force the general control state machine to run independent of the macro functions that normally run the equalization." "0,1" newline bitfld.long 0x0 0. "RX_REE_PERGCSM_CTRL_0,Enable: This bit enables the general control state machine function. 1'b1 : Enabled 1'b0 : Disabled" "?,1: Enabled 1'b0 : Disabled" rgroup.long 0x8290++0x3 line.long 0x0 "WIZ16B8M4CT2_RX_REE_ATTEN_THR__RX_REE_ATTEN_CTRL,REE attenuation control register (!)" hexmask.long.byte 0x0 24.--28. 1. "RX_REE_ATTEN_THR_12_8,Attenuation high threshold value: High threshold value to compare against the VGA gain accumulator value. Note that the value on this field is not a twos complement value (There is no sign bit and it is always a positive number)." newline hexmask.long.byte 0x0 16.--20. 1. "RX_REE_ATTEN_THR_4_0,Attenuation low threshold value: Low threshold value to compare against the VGA gain accumulator value. Note that the value on this field is not a twos complement value (There is no sign bit and it is always a positive number)." rgroup.long 0x82E0++0x7 line.long 0x0 "WIZ16B8M4CT2_RX_REE_TAP1_CLIP__RX_REE_ADDR_CFG,REE adder configuration register (!)" bitfld.long 0x0 24.--26. "RX_REE_TAP1_CLIP_10_8,VGA target gain adjust multiplier: Controls how much to multiply the VGA target gain adjust by when calculating the tap threshold. The following are valid values and the corresponding multiplier values. 3'b000 : x 0.00 3'b001 : x.." "0: x 0,1: x 0,2: x 0,3: x 0,4: x 1,5: x 1,6: x 1,7: x 1" newline hexmask.long.byte 0x0 16.--20. 1. "RX_REE_TAP1_CLIP_4_0,Threshold adjust: Controls how much the threshold can be adjusted by after multiplying the VGA target gain adjust multiplier with the VGA target gain adjust. Note that this field is a positive number (not twos complement). Note :.." line.long 0x4 "WIZ16B8M4CT2_RX_REE_CTRL_DATA_MASK__RX_REE_TAP2TON_CLIP,REE taps 2 and 3 clip control register (!)" bitfld.long 0x4 8.--10. "RX_REE_TAP2TON_CLIP_10_8,VGA target gain adjust multiplier: Controls how much to multiply the VGA target gain adjust by when calculating the tap threshold. The following are valid values and the corresponding multiplier values. 3'b000 : x 0.00 3'b001.." "0: x 0,1: x 0,2: x 0,3: x 0,4: x 1,5: x 1,6: x 1,7: x 1" newline hexmask.long.byte 0x4 0.--4. 1. "RX_REE_TAP2TON_CLIP_4_0,Threshold adjust: Controls how much the threshold can be adjusted by after multiplying the VGA target gain adjust multiplier with the VGA target gain adjust. Note that this field is a positive number (not twos complement). Note.." rgroup.long 0x82EC++0x7 line.long 0x0 "WIZ16B8M4CT2_RX_REE_SMGM_CTRL1__RX_REE_TXEQEVAL_CTRL,REE TX equalization evaluator control register (!)" bitfld.long 0x0 27. "RX_REE_SMGM_CTRL1_11,REE Periodic general control state machine enable standard mode 3: This bit will control if the REE periodic general control state machine will run when xcvr_standard_mode is set to 2'b11. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x0 26. "RX_REE_SMGM_CTRL1_10,REE Periodic general control state machine enable standard mode 2: This bit will control if the REE periodic general control state machine will run when xcvr_standard_mode is set to 2'b10. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x0 25. "RX_REE_SMGM_CTRL1_9,REE Periodic general control state machine enable standard mode 1: This bit will control if the REE periodic general control state machine will run when xcvr_standard_mode is set to 2'b01. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,1: This bit will control if the REE periodic.." newline bitfld.long 0x0 24. "RX_REE_SMGM_CTRL1_8,REE Periodic general control state machine enable standard mode 0: This bit will control if the REE periodic general control state machine will run when xcvr_standard_mode is set to 2'b00. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x0 23. "RX_REE_SMGM_CTRL1_7,REE general control state machine 2 enable standard mode 3: This bit will control if the REE general control state machine 2 will run when xcvr_standard_mode is set to 2'b11. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x0 22. "RX_REE_SMGM_CTRL1_6,REE general control state machine 2 enable standard mode 2: This bit will control if the REE general control state machine 2 will run when xcvr_standard_mode is set to 2'b10. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x0 21. "RX_REE_SMGM_CTRL1_5,REE general control state machine 2 enable standard mode 1: This bit will control if the REE general control state machine 2 will run when xcvr_standard_mode is set to 2'b01. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,1: This bit will control if the REE general control.." newline bitfld.long 0x0 20. "RX_REE_SMGM_CTRL1_4,REE general control state machine 2 enable standard mode 0: This bit will control if the REE general control state machine 2 will run when xcvr_standard_mode is set to 2'b00. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x0 19. "RX_REE_SMGM_CTRL1_3,REE general control state machine 1 enable standard mode 3: This bit will control if the REE general control state machine 1 will run when xcvr_standard_mode is set to 2'b11. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x0 18. "RX_REE_SMGM_CTRL1_2,REE general control state machine 1 enable standard mode 2: This bit will control if the REE general control state machine 1 will run when xcvr_standard_mode is set to 2'b10. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x0 17. "RX_REE_SMGM_CTRL1_1,REE general control state machine 1 enable standard mode 1: This bit will control if the REE general control state machine 1 will run when xcvr_standard_mode is set to 2'b01. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,1: This bit will control if the REE general control.." newline bitfld.long 0x0 16. "RX_REE_SMGM_CTRL1_0,REE general control state machine 1 enable standard mode 0: This bit will control if the REE general control state machine 1 will run when xcvr_standard_mode is set to 2'b00. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,?" line.long 0x4 "WIZ16B8M4CT2_RX_REE_TXEQEVAL_PRE__RX_REE_SMGM_CTRL2,REE control state machine gen mode control register 2 (!)" bitfld.long 0x4 15. "RX_REE_SMGM_CTRL2_15,REE PCIe Gen 3 TX equalization state machine E path en standard mode 3: This bit controls if the REE PCIE Gen 3 TX equalization state machine will enable the analog E path when xcvr_standard_mode is set to 2'b11. 1'b0 : Disabled 1'b1.." "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x4 14. "RX_REE_SMGM_CTRL2_14,REE PCIe Gen 3 TX equalization state machine E path en standard mode 2: This bit controls if the REE PCIE Gen 3 TX equalization state machine will enable the analog E path when xcvr_standard_mode is set to 2'b10. 1'b0 : Disabled 1'b1.." "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x4 13. "RX_REE_SMGM_CTRL2_13,REE PCIe Gen 3 TX equalization state machine E path en standard mode 1: This bit controls if the REE PCIE Gen 3 TX equalization state machine will enable the analog E path when xcvr_standard_mode is set to 2'b01. 1'b0 : Disabled 1'b1.." "0: Disabled 1'b1 : Enabled,1: This bit controls if the REE PCIE Gen 3 TX.." newline bitfld.long 0x4 12. "RX_REE_SMGM_CTRL2_12,REE PCIe Gen 3 TX equalization state machine E path en standard mode 0: This bit controls if the REE PCIE Gen 3 TX equalization state machine will enable the analog E path when xcvr_standard_mode is set to 2'b00. 1'b0 : Disabled 1'b1.." "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x4 11. "RX_REE_SMGM_CTRL2_11,REE Periodic general control state machine E path en standard mode 3: This bit controls if the REE periodic general control state machine will enable the analog E path when xcvr_standard_mode is set to 2'b11. 1'b0 : Disabled 1'b1 :.." "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x4 10. "RX_REE_SMGM_CTRL2_10,REE Periodic general control state machine E path en standard mode 2: This bit controls if the REE periodic general control state machine will enable the analog E path when xcvr_standard_mode is set to 2'b10. 1'b0 : Disabled 1'b1 :.." "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x4 9. "RX_REE_SMGM_CTRL2_9,REE Periodic general control state machine E path en standard mode 1: This bit controls if the REE periodic general control state machine will enable the analog E path when xcvr_standard_mode is set to 2'b01. 1'b0 : Disabled 1'b1 :.." "0: Disabled 1'b1 : Enabled,1: This bit controls if the REE periodic general.." newline bitfld.long 0x4 8. "RX_REE_SMGM_CTRL2_8,REE Periodic general control state machine E path en standard mode 0: This bit controls if the REE periodic general control state machine will enable the analog E path when xcvr_standard_mode is set to 2'b00. 1'b0 : Disabled 1'b1 :.." "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x4 7. "RX_REE_SMGM_CTRL2_7,REE general control state machine 2 E path en standard mode 3: This bit controls if the REE general control state machine 2 will enable the analog E path when xcvr_standard_mode is set to 2'b11. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x4 6. "RX_REE_SMGM_CTRL2_6,REE general control state machine 2 E path en standard mode 2: This bit controls if the REE general control state machine 2 will enable the analog E path when xcvr_standard_mode is set to 2'b10. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x4 5. "RX_REE_SMGM_CTRL2_5,REE general control state machine 2 E path en standard mode 1: This bit controls if the REE general control state machine 2 will enable the analog E path when xcvr_standard_mode is set to 2'b01. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,1: This bit controls if the REE general control.." newline bitfld.long 0x4 4. "RX_REE_SMGM_CTRL2_4,REE general control state machine 2 E path en standard mode 0: This bit controls if the REE general control state machine 2 will enable the analog E path when xcvr_standard_mode is set to 2'b00. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x4 3. "RX_REE_SMGM_CTRL2_3,REE general control state machine 1 E path en standard mode 3: This bit controls if the REE general control state machine 1 will enable the analog E path when xcvr_standard_mode is set to 2'b11. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x4 2. "RX_REE_SMGM_CTRL2_2,REE general control state machine 1 E path en standard mode 2: This bit controls if the REE general control state machine 1 will enable the analog E path when xcvr_standard_mode is set to 2'b10. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x4 1. "RX_REE_SMGM_CTRL2_1,REE general control state machine 1 E path en standard mode 1: This bit controls if the REE general control state machine 1 will enable the analog E path when xcvr_standard_mode is set to 2'b01. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,1: This bit controls if the REE general control.." newline bitfld.long 0x4 0. "RX_REE_SMGM_CTRL2_0,REE general control state machine 1 E path en standard mode 0: This bit controls if the REE general control state machine 1 will enable the analog E path when xcvr_standard_mode is set to 2'b00. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,?" rgroup.long 0x83C0++0xB line.long 0x0 "WIZ16B8M4CT2_RX_DIAG_DFE_AMP_TUNE__RX_DIAG_DFE_CTRL,Receiver DFE control register (!)" bitfld.long 0x0 28.--30. "RX_DIAG_DFE_AMP_TUNE_14_12,DFE constant gm bias tune: Adjusts the constant gm bias. 3'b000: -34 uA 3'b001 3'b010 3'b011 3'b100: - 50 uA 3'b101 3'b110 3'b111: -62 uA" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 27. "RX_DIAG_DFE_AMP_TUNE_11,DFE VGA constant gm bias enable: Enables the VGA constant gm bias. This bit drives the rxda_vga_cnst_gm_en signal going to the analog. 1'b0 : Disabled. 1'b1 : Enabled." "0: Disabled,1: Enabled" newline bitfld.long 0x0 24.--26. "RX_DIAG_DFE_AMP_TUNE_10_8,DFE VGA amp current adjust: Adjusts the current for the DFE VGA amp using the rxda_vga_current_adj signal as specified below. Note that the percentages are approximate values. 3'b000: +30% (maximum) ... 3'b101: 0% ... 3'b111:.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "RX_DIAG_DFE_AMP_TUNE_7,DFE peaking constant gm bias enable: Enables the peaking constant gm bias. This bit drives the rxda_peak_cnst_gm_en signal going to the analog. 1'b0 : Disabled. 1'b1 : Enabled." "0: Disabled,1: Enabled" newline bitfld.long 0x0 20.--22. "RX_DIAG_DFE_AMP_TUNE_6_4,DFE peaking amp current adjust: Adjusts the current for the DFE peaking amp using the rxda_peak_current_adj signal as specified below. Note that the percentages are approximate values. 3'b000: +30% (maximum) ... 3'b101: 0% ..." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "RX_DIAG_DFE_AMP_TUNE_3,DFE summing constant gm bias enable: Enables the summing constant gm bias. This bit drives the rxda_sum_cnst_gm_en signal going to the analog. 1'b0 : Disabled. 1'b1 : Enabled." "0: Disabled,1: Enabled" newline bitfld.long 0x0 16.--18. "RX_DIAG_DFE_AMP_TUNE_2_0,DFE summing amp current adjust: Adjusts the current for the DFE summing amp using the rxda_sum_current_adj signal as specified below. Note that the percentages are approximate values. 3'b000: +30% (maximum) ... 3'b101: 0% ..." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "RX_DIAG_DFE_CTRL_3,Receiver DFE low frequency equalization enable value standard mode 3: This bit controls the rxda_dfe_lfeq_en signal going to the analog which is used to enable the receiver DFE low frequency equalization analog circuits when.." "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x0 2. "RX_DIAG_DFE_CTRL_2,Receiver DFE low frequency equalization enable value standard mode 2: This bit controls the rxda_dfe_lfeq_en signal going to the analog which is used to enable the receiver DFE low frequency equalization analog circuits when.." "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x0 1. "RX_DIAG_DFE_CTRL_1,Receiver DFE low frequency equalization enable value standard mode 1: This bit controls the rxda_dfe_lfeq_en signal going to the analog which is used to enable the receiver DFE low frequency equalization analog circuits when.." "0: Disabled 1'b1 : Enabled,1: This bit controls the rxda_dfe_lfeq_en signal.." newline bitfld.long 0x0 0. "RX_DIAG_DFE_CTRL_0,Receiver DFE low frequency equalization enable value standard mode 0: This bit controls the rxda_dfe_lfeq_en signal going to the analog which is used to enable the receiver DFE low frequency equalization analog circuits when.." "0: Disabled 1'b1 : Enabled,?" line.long 0x4 "WIZ16B8M4CT2_RX_DIAG_DFE_AMP_TUNE_3__RX_DIAG_DFE_AMP_TUNE_2,DFE amp fine tuning 2 register (!)" bitfld.long 0x4 19. "RX_DIAG_DFE_AMP_TUNE_3_3,DFE VGA stage 1 boost standard mode 3: This bit enables the active inductors boost function in stage 1 of the VGA for high data rates when xcvr_standard_mode is set to 2'b11. This bit controls the rxda_vga_st1_actind_en signal.." "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x4 18. "RX_DIAG_DFE_AMP_TUNE_3_2,DFE VGA stage 1 boost standard mode 2: This bit enables the active inductors boost function in stage 1 of the VGA for high data rates when xcvr_standard_mode is set to 2'b10. This bit controls the rxda_vga_st1_actind_en signal.." "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x4 17. "RX_DIAG_DFE_AMP_TUNE_3_1,DFE VGA stage 1 boost standard mode 1: This bit enables the active inductors boost function in stage 1 of the VGA for high data rates when xcvr_standard_mode is set to 2'b01. This bit controls the rxda_vga_st1_actind_en signal.." "0: Disabled 1'b1 : Enabled,1: This bit enables the active inductors boost.." newline bitfld.long 0x4 16. "RX_DIAG_DFE_AMP_TUNE_3_0,DFE VGA stage 1 boost standard mode 0: This bit enables the active inductors boost function in stage 1 of the VGA for high data rates when xcvr_standard_mode is set to 2'b00. This bit controls the rxda_vga_st1_actind_en signal.." "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x4 12.--13. "RX_DIAG_DFE_AMP_TUNE_2_13_12,Receiver peaking amp common mode adjust: Adjusts the common mode voltage for the receiver peaking amp by driving the rxda_fe_pkamp_cm_adj signal to the analog. 2'b00 : Nominal common mode voltage. 2'b01 : Reduces the common.." "0: Nominal common mode voltage,1: Reduces the common mode voltage by one step,2: Increases the common mode voltage by one step,3: Reserved" newline bitfld.long 0x4 11. "RX_DIAG_DFE_AMP_TUNE_2_11,DFE low frequency equalizer constant gm bias enable: Enables the low frequency equalizer constant gm bias. This bit drives the rxda_lfeq_cnst_gm_en signal going to the analog. 1'b0 : Disabled. 1'b1 : Enabled." "0: Disabled,1: Enabled" newline bitfld.long 0x4 8.--10. "RX_DIAG_DFE_AMP_TUNE_2_10_8,DFE low frequency equalizer current adjust: Adjusts the current for the DFE low frequency equalizer using the rxda_lfeq_current_adj signal as specified below. Note that the percentages are approximate values. 3'b000: +30%.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "RX_DIAG_DFE_AMP_TUNE_2_7,DFE peaking amp boost: Enables the active inductors boost function in the peaking amp for high data rates. This bit controls the rxda_peak_actind_en signal going to the analog. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x4 6. "RX_DIAG_DFE_AMP_TUNE_2_6,Reserved - Spare" "0,1" newline bitfld.long 0x4 5. "RX_DIAG_DFE_AMP_TUNE_2_5,DFE VGA stage 2 boost: Enables the active inductors boost function in stage 2 of the VGA for high data rates. This bit controls the rxda_vga_st2_actind_en signal going to the analog. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x4 4. "RX_DIAG_DFE_AMP_TUNE_2_4,DFE RX Tap 1 DAC Range Select: Controls the tap 1 DAC range in the analog DFE. This bit controls the rxda_dfe_tap_1_range signal going to the analog. 1'b0: Normal operation 1'b1: The tap 1 DAC range is increased." "0: Normal operation 1'b1: The tap 1 DAC range is..,?" newline bitfld.long 0x4 0.--1. "RX_DIAG_DFE_AMP_TUNE_2_1_0,DFE RX amp current adjust: Adjusts the mix of constant-gm and External Current for RX front end amplifiers. This controls the rxda_cnstgm_ext_sel signal going into the analog. The encoding of the rxda_cnstgm_ext_sel signal .." "0: X 3'b000 : gm_bias = 25u,1: X 3'b001 : gm_bias = 30u,2: X 3'b011 : gm_bias = 35u,3: X 3'b111 : gm_bias = 40u" line.long 0x8 "WIZ16B8M4CT2_RX_DIAG_NQST_CTRL__RX_DIAG_REE_DAC_CTRL,REE DAC control register (!)" hexmask.long.byte 0x8 28.--31. 1. "RX_DIAG_NQST_CTRL_15_12,RX nyquist select value standard mode 3: This field specifies the receiver DFE nyquist frequency select value on the rxda_dfe_nqst_sel signal driven to the analog when xcvr_standard_mode is set to 2'b11." newline hexmask.long.byte 0x8 24.--27. 1. "RX_DIAG_NQST_CTRL_11_8,RX nyquist select value standard mode 2: This field specifies the receiver DFE nyquist frequency select value on the rxda_dfe_nqst_sel signal driven to the analog when xcvr_standard_mode is set to 2'b10." newline hexmask.long.byte 0x8 20.--23. 1. "RX_DIAG_NQST_CTRL_7_4,RX nyquist select value standard mode 1: This field specifies the receiver DFE nyquist frequency select value on the rxda_dfe_nqst_sel signal driven to the analog when xcvr_standard_mode is set to 2'b01." newline hexmask.long.byte 0x8 16.--19. 1. "RX_DIAG_NQST_CTRL_3_0,RX nyquist select value standard mode 0: This field specifies the receiver DFE nyquist frequency select value on the rxda_dfe_nqst_sel signal driven to the analog when xcvr_standard_mode is set to 2'b00." rgroup.long 0x83D0++0x3 line.long 0x0 "WIZ16B8M4CT2_RX_DIAG_SH_SIGDET__RX_DIAG_SIGDET_TUNE,RX signal detect tuning and control register (!)" bitfld.long 0x0 14. "RX_DIAG_SIGDET_TUNE_14,Signal detect calibration half gain select: Controls the resolution of each step in the signal detect calibration code by adjusting the gain of signal detect offset correction by driving the rxda_sd_cal_halfgain signal going to.." "0,1" newline bitfld.long 0x0 12.--13. "RX_DIAG_SIGDET_TUNE_13_12,Signal detect filter function select: Selects which of the two RX signal detect filter functions are enabled. As specified below. 2'b00 : Reserved 2'b01 : RX low to high filter disabled RX high to low filter enabled. 2'b10 :.." "0: Reserved 2'b01 : RX low to high filter disabled,?,2: RX low to high filter enabled,3: RX low to high filter enabled" newline bitfld.long 0x0 7. "RX_DIAG_SIGDET_TUNE_7,Receiver signal detect invert samplers: Inverts the behavior of the rxda_sd_pulse_high and rxda_sd_pulse_low samplers by driving the rxda_sd_invert_samplers signal to the analog. 1'b0 : Normal mode : The rxda_sd_pulse_high sampler.." "0: Normal mode : The rxda_sd_pulse_high sampler..,1: Inverted mode : The rxda_sd_pulse_high sampler.." newline bitfld.long 0x0 6. "RX_DIAG_SIGDET_TUNE_6,Receiver signal detect squelch pulse none: Enable the squelch function for the rxda_sd_pulse_none signal by driving the rxda_sd_squelch_pulse_none signal to the analog. This debug feature could allow the detection of LFPS signals.." "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x0 5. "RX_DIAG_SIGDET_TUNE_5,Receiver signal detect one comparator mode: Enables one comparator mode as a power reduction option by driving the rxda_sd_onecomp_mode_en signal to the analog. 1'b0 : Both signal detect comparators functioning. 1'b1 : One signal.." "0: Both signal detect comparators functioning,1: One signal detect comparator functioning" newline bitfld.long 0x0 4. "RX_DIAG_SIGDET_TUNE_4,Receiver signal detect DC coupled path enable: Enables a DC coupled path to the signal detect for verification and testability purposes by driving the rxda_sd_dcpath_en signal to the analog. 1'b0 : Disabled 1'b1 : Enabled" "0: Disabled 1'b1 : Enabled,?" newline bitfld.long 0x0 0.--2. "RX_DIAG_SIGDET_TUNE_2_0,Signal detect level: Sets the reference voltage level at which the comparators will detect a signal by driving the rxda_sd_siglvl_n signal going to the analog. The following specifies the encoding of this signal. 3'b000 :.." "0,1,2,3,4,5,6,7" rgroup.long 0x83E8++0x3 line.long 0x0 "WIZ16B8M4CT2_RX_DIAG_PI_CAP__RX_DIAG_PI_RATE,PI rate selection register (!)" bitfld.long 0x0 28.--30. "RX_DIAG_PI_CAP_14_12,PI capacitor selection standard mode 3: This field is used to implement waveform shaping inside the PI CML cells by changing the capacitive loading. As the data rate decreases this is used to increase cap loading to maintain.." "0: Default capacitance required for wave shaping..,1: Increased capacitance required for wave shaping..,?,3: This field is used to implement waveform shaping..,?,?,?,7: Reserved" newline bitfld.long 0x0 24.--26. "RX_DIAG_PI_CAP_10_8,PI capacitor selection standard mode 2: This field is used to implement waveform shaping inside the PI CML cells by changing the capacitive loading. As the data rate decreases this is used to increase cap loading to maintain.." "0: Default capacitance required for wave shaping..,1: Increased capacitance required for wave shaping..,2: This field is used to implement waveform shaping..,?,?,?,?,7: Reserved" newline bitfld.long 0x0 20.--22. "RX_DIAG_PI_CAP_6_4,PI capacitor selection standard mode 1: This field is used to implement waveform shaping inside the PI CML cells by changing the capacitive loading. As the data rate decreases this is used to increase cap loading to maintain.." "0: Default capacitance required for wave shaping..,1: Increased capacitance required for wave shaping..,?,?,?,?,?,7: Reserved" newline bitfld.long 0x0 16.--18. "RX_DIAG_PI_CAP_2_0,PI capacitor selection standard mode 0: This field is used to implement waveform shaping inside the PI CML cells by changing the capacitive loading. As the data rate decreases this is used to increase cap loading to maintain.." "0: Default capacitance required for wave shaping..,1: Increased capacitance required for wave shaping..,?,?,?,?,?,7: Reserved" newline bitfld.long 0x0 12.--14. "RX_DIAG_PI_RATE_14_12,PI rate selection standard mode 3: This field is used to scale the power of the CML cells inside the PI to tune it for a given data rate by driving the rxda_pi_rate_sel signal going into the analog when xcvr_standard_mode is set.." "?,?,2: Reserved 3'b011: 2X power scaling for the CML..,3: This field is used to scale the power of the CML..,?,?,?,7: Reserved" newline bitfld.long 0x0 8.--10. "RX_DIAG_PI_RATE_10_8,PI rate selection standard mode 2: This field is used to scale the power of the CML cells inside the PI to tune it for a given data rate by driving the rxda_pi_rate_sel signal going into the analog when xcvr_standard_mode is set to.." "?,?,2: Reserved 3'b011: 2X power scaling for the CML..,?,?,?,?,7: Reserved" newline bitfld.long 0x0 4.--6. "RX_DIAG_PI_RATE_6_4,PI rate selection standard mode 1: This field is used to scale the power of the CML cells inside the PI to tune it for a given data rate by driving the rxda_pi_rate_sel signal going into the analog when xcvr_standard_mode is set to.." "?,1: This field is used to scale the power of the CML..,2: Reserved 3'b011: 2X power scaling for the CML..,?,?,?,?,7: Reserved" newline bitfld.long 0x0 0.--2. "RX_DIAG_PI_RATE_2_0,PI rate selection standard mode 0: This field is used to scale the power of the CML cells inside the PI to tune it for a given data rate by driving the rxda_pi_rate_sel signal going into the analog when xcvr_standard_mode is set to.." "0: This field is used to scale the power of the CML..,?,2: Reserved 3'b011: 2X power scaling for the CML..,?,?,?,?,7: Reserved" rgroup.long 0x83FC++0x3 line.long 0x0 "WIZ16B8M4CT2_RX_DIAG_ACYA__RX_DIAG_DCYA,Receiver digital cover your alternatives register (!)" hexmask.long.byte 0x0 24.--31. 1. "RX_DIAG_ACYA_15_8,Reserved - spare" newline bitfld.long 0x0 23. "RX_DIAG_ACYA_7,Serial loopback sampler setup time reduction select (TX only lane implementation): For TX only lane implementations this bit can be used to reduce the setup time (providing more hold margin) for the serial loopback data. This function is.." "0: Default setup time 1'b1: Reduced setup time,?" newline hexmask.long.byte 0x0 18.--22. 1. "RX_DIAG_ACYA_6_2,Reserved - spare" newline bitfld.long 0x0 17. "RX_DIAG_ACYA_1,Force receiver signal detect clock enable: This bit is used to force the receiver signal detect clock (rxda_sd_clk) driven from the analog to be enabled independent of whether the analog signal detect function is enabled or not. 1'b0:.." "0: Clock not forced to be enabled 1'b1: Clock..,?" newline bitfld.long 0x0 16. "RX_DIAG_ACYA_0,Full rate clock duty cycle correction enable: Enables the analog duty cycle correction function for the full rate clock that drives the divide by 2 circuit to generate the half rate I and Q clocks. 1'b0: Enabled 1'b1: Disabled" "0: Enabled 1'b1: Disabled,?" rgroup.long 0xA000++0x3 line.long 0x0 "WIZ16B8M4CT2_RESERVEDBIT13ADDRESSC,Reserved Address bit 13 area C" hexmask.long 0x0 0.--31. 1. "RES_BIT13_ADR_C,Write only test region C" rgroup.long 0xC000++0x17 line.long 0x0 "WIZ16B8M4CT2_PHY_PIPE_CMN_CTRL2__PHY_PIPE_CMN_CTRL1,PIPE common control1 register" hexmask.long.byte 0x0 28.--31. 1. "PHY_PIPE_CMN_CTRL2_15_12,USB SuperSpeed Tx LFPS Stretch : Minimum number of data rate clock cycles in which PMA tx_lfps_en signal is asserted for USB SuperSpeed rate. Number of data rate clock cycles must be X 1 PMA RefClk cycle." newline hexmask.long.byte 0x0 24.--27. 1. "PHY_PIPE_CMN_CTRL2_11_8,USB SuperSpeedPlus Tx LFPS Stretch : Minimum number of data rate clock cycles in which PMA tx_lfps_en signal is asserted for USB SuperSpeedPlus rate. Number of data rate clock cycles must be X 1 PMA RefClk cycle." newline bitfld.long 0x0 22. "PHY_PIPE_CMN_CTRL2_6,PCIe PCS TX electrical idle pre release:When this bit is set the TX electrical idle release to the PMA is advanced 1 cycle to allow the adjustment of the datapath timing" "0,1" newline bitfld.long 0x0 21. "PHY_PIPE_CMN_CTRL2_5,RX equaliser complete mask: When this bit is cleared the PHY will return direction change of 0 when PMA indicates evaluation complete. Subsequent evaluation requests would clear the PMA iteration counters. When set high the PMA.." "0,1" newline bitfld.long 0x0 20. "PHY_PIPE_CMN_CTRL2_4,PCIe PCS EIOS cycle error mask: When this bit is enabled and the pipe rx interface is outputting an EIOS symbol decode errors will be masked out" "0,1" newline bitfld.long 0x0 19. "PHY_PIPE_CMN_CTRL2_3,USB Gen 2 Bit Error Correction Disable: When this bit is high bit error correction on SKP and SDS symbols is disabled." "0,1" newline bitfld.long 0x0 18. "PHY_PIPE_CMN_CTRL2_2,USB PIPE3 Compatibility Mode enable : When this bit is set to 1 USB PIPE3 compatibility mode is enabled. In this mode when operating in nominal empty Elasticity Buffer mode when the EB buffer goes empty instead of de-asserting.." "0,1" newline bitfld.long 0x0 17. "PHY_PIPE_CMN_CTRL2_1,USB Loopback Slave Error Count disable: When this bit is set to 1 disables the error count for US loopback slave such that the error count is not inserted into the BCNT OS." "0,1" newline bitfld.long 0x0 16. "PHY_PIPE_CMN_CTRL2_0,USB Elasticity Buffer Re-align enable: When this bit is set to 1 when Rx for a USB link is initially started the elasticity buffer is re-aligned to its idle point upon seeing 3 consecutive COMMAs (i.e. from TS1/TS2s) in the same.." "0,1" newline bitfld.long 0x0 12. "PHY_PIPE_CMN_CTRL1_12,PHY APB access timeout: When set an APB read/write request to PHY registers failed (i.e. timed out). When set this bit is cleared upon read." "0,1" newline bitfld.long 0x0 10. "PHY_PIPE_CMN_CTRL1_10,PCIe PCS Comma realign: This field controls the comma alignment state machine to re-align to new bit position without going to loss of sync state. The requirement of the new bit position should meet the number of COMMAs as per.." "0,1" newline bitfld.long 0x0 9. "PHY_PIPE_CMN_CTRL1_9,Block alignment clear on EIOS : When set upon receiving a PCIe EIOS 128b/130b block alignment is reset regardless of Rx signal detect from the PMA (applies for PCIe Gen 3 only). ()" "0,1" newline bitfld.long 0x0 8. "PHY_PIPE_CMN_CTRL1_8,Comma alignment clear on EIOS : When set upon receiving a PCIe EIOS Comma Alignment is reset regardless of Rx signal detect from the PMA (applies for PCIe Gen 1/2 only). ()" "0,1" newline bitfld.long 0x0 7. "PHY_PIPE_CMN_CTRL1_7,Block alignment ignore Rx SigDetect : When set 128b/13xb block alignment will not be reset due to loss of signal detection from the PMA (applies for PCIe Gen 3 and USB3.1 Gen 2 only). ()" "0,1" newline bitfld.long 0x0 6. "PHY_PIPE_CMN_CTRL1_6,Comma alignment ignore Rx SigDetect : When set Comma alignment will not be reset due to loss of signal detection from the PMA (applies for PCIe Gen 1/2 and USB3.1 Gen 1 only). ()" "0,1" newline bitfld.long 0x0 4.--5. "PHY_PIPE_CMN_CTRL1_5_4,Rx signal detect delay : Selects the number of clock cycles of delay to add to the PMA signal detect when the bit alignment blocks should be reset after losing signal. ()" "0,1,2,3" newline bitfld.long 0x0 1. "PHY_PIPE_CMN_CTRL1_1,RefClk disable override: 1 = overrides turning off reference clock receiver by forcing cmn_refclk_disable PMA input low. 0 = normal control of cmn_refclk_disable PMA input by PHY logic. ()" "0: normal control of cmn_refclk_disable PMA input..,1: overrides turning off reference clock receiver.." newline bitfld.long 0x0 0. "PHY_PIPE_CMN_CTRL1_0,PHY RefClk enable input ingnore : 0 = ignore phy_en_refclk PHY input (forces low internally). 1 = phy_en_refclk_used as specified for controling enable/disable of cmn_refclk_Xp/mX. ()" "0: ignore phy_en_refclk PHY input,1: phy_en_refclk_used as specified for controling.." line.long 0x4 "WIZ16B8M4CT2_PHY_PIPE_COM_LOCK_CFG2__PHY_PIPE_COM_LOCK_CFG1,PIPE comma lock configuration1 register ()" hexmask.long.byte 0x4 24.--31. 1. "PHY_PIPE_COM_LOCK_CFG2_15_8,PCIe PCS Comma lock count fast: The number of COMMA symbols that needs to be seen in the same bit position for the comma state machine to lock. This field is used while the PCS is in P0 state after an EIOS has been seen ie.." newline hexmask.long.byte 0x4 16.--23. 1. "PHY_PIPE_COM_LOCK_CFG2_7_0,PCIe PCS Comma lock count: The number of COMMA symbols that needs to be seen in the same bit position for the comma state machine to lock. This field is used while the PCS is transitioning back to the P0 power state." newline hexmask.long.byte 0x4 12.--15. 1. "PHY_PIPE_COM_LOCK_CFG1_15_12,PCIe PCS Comma unlock count: The number of COMMA symbols that need to be seen in the wrong bit position before the comma alignment state machine will transition to RESYNC or LOS state" newline hexmask.long.word 0x4 0.--11. 1. "PHY_PIPE_COM_LOCK_CFG1_11_0,PCIe PCS Comma full lock count: The number of COMMA symbols that need to be seen in the same bit position for the comma alignment state machine to lock. The field is used for initial reset lock." line.long 0x8 "WIZ16B8M4CT2_PHY_PIPE_LANE_DSBL__PHY_PIPE_EIE_LOCK_CFG,PIPE EIEOS lock configuration register ()" hexmask.long.byte 0x8 16.--23. 1. "PHY_PIPE_LANE_DSBL_7_0,PIPE lane disable: Each bit corresponds to a lane (i.e. bit [0] -X lane 0 bit [1] -X lane 1 etc). When set the corresponding PIPE lane is disabled. Lanes that are disabled will transmit electrical idle and will not return any.." newline hexmask.long.byte 0x8 12.--15. 1. "PHY_PIPE_EIE_LOCK_CFG_15_12,EIE lock count fast: The number of EIEOS blocks that need to be seen in the same bit postion for the alignment state machine to lock for Gen3/4. The field is used while the PCS is in P0 state after an EIEOS has been seen" newline hexmask.long.byte 0x8 8.--11. 1. "PHY_PIPE_EIE_LOCK_CFG_11_8,EIE lock count : The number of EIEOS blocks that need to be seen in the same bit postion for the alignment state machine to lock for Gen3/4. The field is used while the PCS is transitioning out of a power state change and not.." newline hexmask.long.byte 0x8 0.--7. 1. "PHY_PIPE_EIE_LOCK_CFG_7_0,EIE full lock count: The number of EIEOS blocks that need to be seen in the same bit postion for the alignment state machine to lock for Gen3/4. The field is used for initial after reset lock or lock after a rate change" line.long 0xC "WIZ16B8M4CT2_PHY_PIPE_RX_ELEC_IDLE_DLY__PHY_PIPE_RCV_DET_INH,PIPE receiver detect inhibit register ()" hexmask.long.byte 0xC 26.--31. 1. "PHY_PIPE_RX_ELEC_IDLE_DLY_15_10,PCIe PCS L1.x exit Rx electrical idle force fast count : Counter load value to hold PIPE Rx Electrical Idle high upon exit from L1.x. Counter is loaded and starts counting down after phy_l*_rx_elec_idle_det_en is.." newline hexmask.long.word 0xC 16.--25. 1. "PHY_PIPE_RX_ELEC_IDLE_DLY_9_0,PCIe PCS L1.x exit Rx electrical idle force full count : Counter load value to hold PIPE Rx Electrical Idle high upon exit from L1.x when the PMA common was powered down. Counter is loaded and starts counting down upon.." newline hexmask.long.word 0xC 0.--15. 1. "PHY_PIPE_RCV_DET_INH_15_0,PCS Receiver Detect Inhibit Counter Load Value: Counter load value to delay receiver detection request to PMA until PMA common mode is within the required range. The timer (running on divided reference clock from PMA) starts.." line.long 0x10 "WIZ16B8M4CT2_PHY_ISO_CMN_CTRL,PHY common control signal isolation register ()" rbitfld.long 0x10 12. "PHY_ISO_CMN_CTRL_12,Current value of phy_refclk_reqd PHY output." "0,1" newline bitfld.long 0x10 8. "PHY_ISO_CMN_CTRL_8,Drives phy_refclk_en PHY input when in PHY macro and PMA isolation mode." "0,1" newline bitfld.long 0x10 5. "PHY_ISO_CMN_CTRL_5,Drives phy_pma_suspend_override PHY input when in PHY macro and PMA isolation mode." "0,1" newline bitfld.long 0x10 4. "PHY_ISO_CMN_CTRL_4,Drives refclk_rcvr_pwrdn internal PHY signal when in PHY macro and PMA isolation mode (1 = powers down the reference clock receiver). During normal operation refclk_rcvr_pwrdn is driven from ~abp_preset_n which powers down the.." "?,1: powers down the reference clock receiver)" newline bitfld.long 0x10 0. "PHY_ISO_CMN_CTRL_0,Drives phy_reset_n PHY input when in PHY macro and PMA isolation mode." "0,1" line.long 0x14 "WIZ16B8M4CT2_PHY_STATE_CHG_TIMEOUT,PHY state change monitor timeout" hexmask.long.word 0x14 0.--15. 1. "PHY_STATE_CHG_TIMEOUT_15_0,State change timeout: Bits [19:4] of the state change timeout (bits [3:0] are zero). The timeout is the maximum number of APB clock cycles (abp_pclk) that are allowed for completion of a PHY power state change for the link." rgroup.long 0xC01C++0xF line.long 0x0 "WIZ16B8M4CT2_PHY_AUTO_CFG_SPDUP__PHY_PLL_CFG,PHY speedup control register" rbitfld.long 0x0 19. "PHY_AUTO_CFG_SPDUP_3,Speedup configuration complete: 1 = PHY speedup configuration is complete 0 = not complete." "0: not complete,1: PHY speedup configuration is complete" newline bitfld.long 0x0 18. "PHY_AUTO_CFG_SPDUP_2,Speedup configuration stall: 1 = upon completion of PHY speedup configuration do not release reset to PMA until this bit is cleared 0 = release reset to PMA upon completion of PHY speedup configuration. Do not set high when [1] =.." "0: release reset to PMA upon completion of PHY..,1: upon completion of PHY speedup configuration" newline bitfld.long 0x0 17. "PHY_AUTO_CFG_SPDUP_1,Speedup configuration enable: If set to 1 upon de-assertion (high) of phy_reset_n the PHY will be configured for simulation speedup. Only for use in RTL or gate-level simulations. Not for use in silicon." "0,1" newline bitfld.long 0x0 1. "PHY_PLL_CFG_1,PLL configuration: 0 = PHY configured to only use PLL0 / PLL1 disabled. 1 = PHY configured to use both PLL0 and PLL1." "0: PHY configured to only use PLL0 / PLL1 disabled,1: PHY configured to use both PLL0 and PLL1" newline bitfld.long 0x0 0. "PHY_PLL_CFG_0,Single link PCIe configuration : 1 = PHY configured such that there is only a single PCIe link (1xN) and all PCIe rates will be driven by PLL0. Any other links are not PCIe and will not use PLL0. 0 = ALl other configurations. This is a.." "0: ALl other configurations,1: PHY configured such that there is only a single.." line.long 0x4 "WIZ16B8M4CT2_PHY_REFCLK_DET_THRES_HIGH__PHY_REFCLK_DET_THRES_LOW,PHY external reference clock detect low threshold register" hexmask.long.word 0x4 16.--31. 1. "PHY_REFCLK_DET_THRES_HIGH_15_0,External Reference Clock Active Detect High Threshold: This is the maximum number of external reference clock cycles which must be counted during the measurement interval to indicate a valid clock detected. The default.." newline hexmask.long.word 0x4 0.--15. 1. "PHY_REFCLK_DET_THRES_LOW_15_0,External Reference Clock Active Detect Low Threshold: This is the minimum number of external reference clock cycles which must be counted during the measurement interval to indicate a valid clock detected. The default value.." line.long 0x8 "WIZ16B8M4CT2_PHY_REFCLK_DET_OP_DELAY__PHY_REFCLK_DET_INTERVAL,PHY external reference clock detect measurement interval register" hexmask.long.byte 0x8 24.--31. 1. "PHY_REFCLK_DET_OP_DELAY_15_8,External Reference Clock Active Detect End Delay: This is the number of apb_pclk cycles to wait upon completion of measurement interval before capturing the result (accounts for synchronization delays)." newline hexmask.long.byte 0x8 16.--23. 1. "PHY_REFCLK_DET_OP_DELAY_7_0,External Reference Clock Active Detect Start Delay: This is the number of apb_pclk cycles to wait prior to start of measurement interval (accounts for enable delay of reference clock in PMA)." newline hexmask.long.word 0x8 0.--15. 1. "PHY_REFCLK_DET_INTERVAL_15_0,External Reference Clock Active Detect Measurement Interval: This is the number of apb_pclk cycles in which to count external reference clock cycles. The default corresponds to 5 us for 200 MHz apb_clk and 100 us for 10 MHz.." line.long 0xC "WIZ16B8M4CT2_PHY_REFCLK_DET_ISO_CTRL,PHY external reference clock detect isolation control register" rbitfld.long 0xC 12. "PHY_REFCLK_DET_ISO_CTRL_12,Captures the current value of the pma_cmn_ext_refclk_detected_cfg PHY input." "0,1" newline rbitfld.long 0xC 9. "PHY_REFCLK_DET_ISO_CTRL_9,Current value of pma_cmn_ext_refclk_detected PHY output." "0,1" newline rbitfld.long 0xC 8. "PHY_REFCLK_DET_ISO_CTRL_8,Current value of pma_cmn_ext_refclk_detected_valid PHY output." "0,1" newline bitfld.long 0xC 0. "PHY_REFCLK_DET_ISO_CTRL_0,External Reference Clock Active Detect Start: Write with 1 to initiate an external reference clock active detect operation. Any previous operation must have completed prior to writing with 1." "0,1" rgroup.long 0xC040++0x7 line.long 0x0 "WIZ16B8M4CT2_PHY_PIPE_USB3_GEN2_PRE_CFG1__PHY_PIPE_USB3_GEN2_PRE_CFG0,PHY USB3 Gen 2 pre-shoot configuration 0 register ()" hexmask.long.byte 0x0 24.--31. 1. "PHY_PIPE_USB3_GEN2_PRE_CFG1_15_8,USB3 Gen 2 transmit pre-shoot multiplier configuration 3: For a lane configured for USB3 mode at Gen 3 data rate sets the multiplier configuration for the Tx de-emphasis pre-shoot (C-1) when pipe_lXX_tx_deemphasis[1:0].." newline hexmask.long.byte 0x0 16.--23. 1. "PHY_PIPE_USB3_GEN2_PRE_CFG1_7_0,USB3 Gen 2 transmit pre-shoot multiplier configuration 2: For a lane configured for USB3 mode at Gen 3 data rate sets the multiplier configuration for the Tx de-emphasis pre-shoot (C1) when pipe_lXX_tx_deemphasis[1:0] ==.." newline hexmask.long.byte 0x0 8.--15. 1. "PHY_PIPE_USB3_GEN2_PRE_CFG0_15_8,USB3 Gen 2 transmit pre-shoot multiplier configuration 1: For a lane configured for USB3 mode at Gen 3 data rate sets the multiplier configuration for the Tx de-emphasis pre-shoot (C-1) when pipe_lXX_tx_deemphasis[1:0].." newline hexmask.long.byte 0x0 0.--7. 1. "PHY_PIPE_USB3_GEN2_PRE_CFG0_7_0,USB3 Gen 2 transmit pre-shoot multiplier configuration 0: For a lane configured for USB3 mode at Gen 3 data rate sets the multiplier configuration for the Tx de-emphasis pre-shoot (C-1) when pipe_lXX_tx_deemphasis[1:0].." line.long 0x4 "WIZ16B8M4CT2_PHY_PIPE_USB3_GEN2_POST_CFG1__PHY_PIPE_USB3_GEN2_POST_CFG0,PHY USB3 Gen 2 de-emphasis configuration 0 register ()" hexmask.long.byte 0x4 24.--31. 1. "PHY_PIPE_USB3_GEN2_POST_CFG1_15_8,USB3 Gen 2 transmit pre-shoot multiplier configuration 3: For a lane configured for USB3 mode at Gen 3 data rate sets the multiplier configuration for the Tx de-emphasis (C1) when pipe_lXX_tx_deemphasis[1:0] == 0b11.." newline hexmask.long.byte 0x4 16.--23. 1. "PHY_PIPE_USB3_GEN2_POST_CFG1_7_0,USB3 Gen 2 transmit pre-shoot multiplier configuration 2: For a lane configured for USB3 mode at Gen 3 data rate sets the multiplier configuration for the Tx de-emphasis (C1) when pipe_lXX_tx_deemphasis[1:0] == 0b10 for.." newline hexmask.long.byte 0x4 8.--15. 1. "PHY_PIPE_USB3_GEN2_POST_CFG0_15_8,USB3 Gen 2 transmit pre-shoot multiplier configuration 1: For a lane configured for USB3 mode at Gen 3 data rate sets the multiplier configuration for the Tx de-emphasis (C1) when pipe_lXX_tx_deemphasis[1:0] == 0b01.." newline hexmask.long.byte 0x4 0.--7. 1. "PHY_PIPE_USB3_GEN2_POST_CFG0_7_0,USB3 Gen 2 transmit pre-shoot multiplier configuration 0: For a lane configured for USB3 mode at Gen 3 data rate sets the multiplier configuration for the Tx de-emphasis (C1) when pipe_lXX_tx_deemphasis[1:0] == 0b00 for.." rgroup.long 0xD000++0x17 line.long 0x0 "WIZ16B8M4CT2_PHY_PIPE_ISO_TX_LPC_LO__PHY_PIPE_ISO_TX_CTRL,PIPE TX control signal isolation register ()" hexmask.long.byte 0x0 24.--29. 1. "PHY_PIPE_ISO_TX_LPC_LO_13_8,Current value of pipe_tx_local_tx_preset_coefficients[11:6] for the associated lane when PHY_PCS_ISO_TX_LPC_HI[15] == 1. Otherwise 0." newline hexmask.long.byte 0x0 16.--21. 1. "PHY_PIPE_ISO_TX_LPC_LO_5_0,Current value of pipe_tx_local_tx_preset_coefficients[5:0] for the associated lane when PHY_PCS_ISO_TX_LPC_HI[15] == 1. Otherwise 0." newline hexmask.long.byte 0x0 12.--15. 1. "PHY_PIPE_ISO_TX_CTRL_15_12,Drives pipe_tx_data_k PHY input for the associated lane when in PHY macro and PMA isolation modes." newline bitfld.long 0x0 8. "PHY_PIPE_ISO_TX_CTRL_8,Drives pipe_tx_ones_zeros input for the associated lane when in PHY macro and PMA isolation modes." "0,1" newline bitfld.long 0x0 4. "PHY_PIPE_ISO_TX_CTRL_4,Drives pipe_tx_elec_idle PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1" newline bitfld.long 0x0 3. "PHY_PIPE_ISO_TX_CTRL_3,Drives pipe_tx_128b_enc_byp PHY input for the associated lane when in PHY macro and PMA isolation modes." "0,1" newline bitfld.long 0x0 2. "PHY_PIPE_ISO_TX_CTRL_2,Drives pipe_tx_compliance PHY input for the associated lane when in PHY macro and PMA isolation modes." "0,1" newline bitfld.long 0x0 0.--1. "PHY_PIPE_ISO_TX_CTRL_1_0,Drives pipe_tx_pattern PHY input for the associated lane when in PHY macro and PMA isolation modes." "0,1,2,3" line.long 0x4 "WIZ16B8M4CT2_PHY_PCS_ISO_TX_DMPH_LO__PHY_PIPE_ISO_TX_LPC_HI,PIPE TX local preset coefficients high isolation register ()" hexmask.long.byte 0x4 24.--29. 1. "PHY_PCS_ISO_TX_DMPH_LO_13_8,Drives pipe_tx_deemph[11:6] PHY input for the associated lane when in PHY macro and PMA isolation mode." newline hexmask.long.byte 0x4 16.--21. 1. "PHY_PCS_ISO_TX_DMPH_LO_5_0,Drives pipe_tx_deemph[5:0] PHY input for the associated lane when in PHY macro and PMA isolation mode." newline rbitfld.long 0x4 15. "PHY_PIPE_ISO_TX_LPC_HI_15,Set upon assertion of pipe_tx_local_tx_coeff_vld PHY output for the associated lane. Cleared upon writing PHY_PCS_ISO_TX_LPC_HI[12] with a 0." "0,1" newline bitfld.long 0x4 12. "PHY_PIPE_ISO_TX_LPC_HI_12,Drives pipe_tx_get_local_preset_coef PHY output for the associated lane when in PHY macro and PMA isolation modes" "0,1" newline hexmask.long.byte 0x4 8.--11. 1. "PHY_PIPE_ISO_TX_LPC_HI_11_8,Drives pipe_tx_local_preset_index PHY output for the associated lane when in PHY macro and PMA isolation modes." newline hexmask.long.byte 0x4 0.--5. 1. "PHY_PIPE_ISO_TX_LPC_HI_5_0,Current value of pipe_tx_local_tx_preset_coefficients[17:12] for the associated lane when PHY_PCS_ISO_TX_LPC_HI[15] == 1. Otherwise 0." line.long 0x8 "WIZ16B8M4CT2_PHY_PIPE_ISO_TX_FSLF__PHY_PIPE_ISO_TX_DMPH_HI,PIPE TX deemphasis high isolation register ()" hexmask.long.byte 0x8 24.--29. 1. "PHY_PIPE_ISO_TX_FSLF_13_8,Current value of pipe_tx_local_fs PHY output for the associated lane. (Not re-synchronized to apb_pclk)" newline hexmask.long.byte 0x8 16.--21. 1. "PHY_PIPE_ISO_TX_FSLF_5_0,Current value of pipe_tx_local_lf PHY output for the associated lane. (Not re-synchronized to apb_pclk)" newline hexmask.long.byte 0x8 0.--5. 1. "PHY_PIPE_ISO_TX_DMPH_HI_5_0,Drives pipe_tx_deemph[17:12] PHY input for the associated lane when in PHY macro and PMA isolation modes." line.long 0xC "WIZ16B8M4CT2_PHY_PCS_ISO_TX_DATA_HI__PHY_PCS_ISO_TX_DATA_LO,PCS TX PIPE data low isolation register ()" hexmask.long.word 0xC 16.--31. 1. "PHY_PCS_ISO_TX_DATA_HI_15_0,Drives pipe_tx_data[31:16] PHY input for the associated lane when in PHY macro and PMA isolation mode." newline hexmask.long.word 0xC 0.--15. 1. "PHY_PCS_ISO_TX_DATA_LO_15_0,Drives pipe_tx_data[15:0] PHY input for the associated lane when in PHY macro and PMA isolation mode." line.long 0x10 "WIZ16B8M4CT2_PHY_PIPE_ISO_RX_EQ_EVAL__PHY_PCS_ISO_RX_CTRL,PCS RX control signal isolation register ()" bitfld.long 0x10 28. "PHY_PIPE_ISO_RX_EQ_EVAL_12,Drives pipe_invalid_request for the associated lane when in PHY macro and PMA isolation modes." "0,1" newline bitfld.long 0x10 27. "PHY_PIPE_ISO_RX_EQ_EVAL_11,pipe_link_eval_dir_change[5:4] bit reversal enable. When low no bit reversal. When high the bit positions for pipe_link_eval_dir_change[5:4] PHY output for the associated lane are reversed." "0,1" newline bitfld.long 0x10 26. "PHY_PIPE_ISO_RX_EQ_EVAL_10,pipe_link_eval_dir_change[3:2] bit reversal enable. When low no bit reversal. When high the bit positions for pipe_link_eval_dir_change[3:2] PHY output for the associated lane are reversed." "0,1" newline bitfld.long 0x10 25. "PHY_PIPE_ISO_RX_EQ_EVAL_9,pipe_link_eval_dir_change[1:0] bit reversal enable. When low no bit reversal. When high the bit positions for pipe_link_eval_dir_change[1:0] PHY output for the associated lane are reversed.]" "0,1" newline bitfld.long 0x10 24. "PHY_PIPE_ISO_RX_EQ_EVAL_8,Drives pipe_rx_eval PHY input for the associated lane when in PHY macro and PMA isolation modes." "0,1" newline rbitfld.long 0x10 22. "PHY_PIPE_ISO_RX_EQ_EVAL_6,Captures pipe_phy_status for Rx equalization evaluation PHY output for the associated lane (does not include power state change signaling). Set when pipe_phy_status is high and pipe_rx_eq_eval to the PCS is high (i.e. after the.." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "PHY_PIPE_ISO_RX_EQ_EVAL_5_0,pipe_link_eval_dir_change PHY output for the associated lane (prior to bit reversal logic) upon completion of Rx equalization evaluation. Captured upon assertion of Rx equalization eval pipe_phy_status when pipe_rx_eq_eval to.." newline hexmask.long.byte 0x10 12.--15. 1. "PHY_PCS_ISO_RX_CTRL_15_12,Current value of pipe_rx_data_k PHY output for the associated lane when PHY_PCS_ISO_RX_CTRL[5] == 1. Otherwise 0. (Not re-synchronized to apb_pclk)" newline bitfld.long 0x10 9. "PHY_PCS_ISO_RX_CTRL_9,Drives pipe_rx_eq_training PHY input for the associated lane when in PHY macro and PMA isolation modes." "0,1" newline bitfld.long 0x10 8. "PHY_PCS_ISO_RX_CTRL_8,Drives pipe_rx_termination PHY input for the associated lane when in PHY macro and PMA isolation modes." "0,1" newline bitfld.long 0x10 7. "PHY_PCS_ISO_RX_CTRL_7,Drives pipe_rx_polarity PHY input for the associated lane when in PHY macro and PMA isolation modes." "0,1" newline rbitfld.long 0x10 5. "PHY_PCS_ISO_RX_CTRL_5,Current value of pipe_rx_valid PHY output for the associated lane." "0,1" newline rbitfld.long 0x10 4. "PHY_PCS_ISO_RX_CTRL_4,Current value of pipe_rx_elec_idle PHY output for the associated lane." "0,1" newline rbitfld.long 0x10 3. "PHY_PCS_ISO_RX_CTRL_3,Current value of pipe_align_detect PHY output for the associated lane." "0,1" newline rbitfld.long 0x10 0.--2. "PHY_PCS_ISO_RX_CTRL_2_0,Current value of pipe_rx_status PHY output for the associated lane. Holds the highest priority pipe_rx_status value seen since the last register read. Cleared upon read." "0,1,2,3,4,5,6,7" line.long 0x14 "WIZ16B8M4CT2_PHY_PCS_ISO_LINK_CTRL__PHY_ISO_LINK_CFG,PHY link configuration isolation register" rbitfld.long 0x14 29. "PHY_PCS_ISO_LINK_CTRL_13,Current value of phy_l*_ack_l1_x PHY output for the associated lane. ()" "0,1" newline bitfld.long 0x14 28. "PHY_PCS_ISO_LINK_CTRL_12,Drives the phy_l*_ent_l1_x PHY input for the associated lane when in PHY macro and PMA isolation modes. (Link signal - for multi-lane links master lane used for all lanes in link.)" "0,1" newline bitfld.long 0x14 27. "PHY_PCS_ISO_LINK_CTRL_11,Drives the phy_l*_rx_elec_idle_det_en PHY input for the associated lane when in PHY macro and PMA isolation modes. (Link signal - for multi-lane links master lane used for all lanes in link.)" "0,1" newline bitfld.long 0x14 26. "PHY_PCS_ISO_LINK_CTRL_10,Drives the phy_l*_tx_cmn_mode_en PHY input for the associated lane when in PHY macro and PMA isolation modes. (Link signal - for multi-lane links master lane used for all lanes in link.)" "0,1" newline bitfld.long 0x14 24.--25. "PHY_PCS_ISO_LINK_CTRL_9_8,Drives the pipe_l*_rate PHY input for the associated lane when in PHY macro and PMA isolation modes. (Link signal - for multi-lane links master lane used for all lanes in link.)" "0,1,2,3" newline bitfld.long 0x14 20.--22. "PHY_PCS_ISO_LINK_CTRL_6_4,Drives the pipe_l*_powerdown PHY input for the associated lane when in PHY macro and PMA isolation modes. (Link signal - for multi-lane links master lane used for all lanes in link.)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 18. "PHY_PCS_ISO_LINK_CTRL_2,Drives the pipe_l*_tx_det_rx_lpbk PHY input for the associated lane when in PHY macro and PMA isolation modes. (Link signal - for multi-lane links master lane used for all lanes in link.)" "0,1" newline rbitfld.long 0x14 17. "PHY_PCS_ISO_LINK_CTRL_1,Captures pipe_l*_phy_status (for power state and rate change) PHY output for the associated lane. Set when pipe_phy_status is high and cleared upon read if pipe_phy_status is low. ()" "0,1" newline bitfld.long 0x14 16. "PHY_PCS_ISO_LINK_CTRL_0,Drives the phy_l*_reset_n PHY input for the associated lane when in PHY macro and PMA isolation modes. (Link signal - for multi-lane links master lane used for all lanes in link.)" "0,1" newline bitfld.long 0x14 15. "PHY_ISO_LINK_CFG_15,Drives phy_link_cfg_ln_{nnnn} PHY input when in PHY macro and PMA isolation modes." "0,1" newline bitfld.long 0x14 12. "PHY_ISO_LINK_CFG_12,Drives pipe_l{nnnn}_32bit_sel PHY input when in PHY macro and PMA isolation modes." "0,1" newline bitfld.long 0x14 8.--9. "PHY_ISO_LINK_CFG_9_8,Drives pma_fullrt_div_ln_{nnnn} PHY input when in PHY macro and PMA isolation modes." "0,1,2,3" newline bitfld.long 0x14 5. "PHY_ISO_LINK_CFG_5,Drives pipe_l{nnnn}_pcie_l1_ss_sel PHY input when in PHY macro and PMA isolation mode." "0,1" newline bitfld.long 0x14 4. "PHY_ISO_LINK_CFG_4,Drives pipe_l{nnnn}_eb_mode PHY input when in PHY macro and PMA isolation modes." "0,1" newline bitfld.long 0x14 0.--1. "PHY_ISO_LINK_CFG_1_0,Drives phy_l{nnnn}_mode PHY input when in PHY macro and PMA isolation modes." "0,1,2,3" rgroup.long 0xD018++0x7 line.long 0x0 "WIZ16B8M4CT2_PHY_PIPE_ISO_USB_BER_CNT,PIPE USB Gen 1 loopback slave BER count register ()" hexmask.long.byte 0x0 8.--15. 1. "PHY_PIPE_ISO_USB_BER_CNT_15_8,Reerved" newline hexmask.long.byte 0x0 0.--7. 1. "PHY_PIPE_ISO_USB_BER_CNT_7_0,Current value of USB 3.1 Gen 1 loopback slave Bit Error Count from the PCS." line.long 0x4 "WIZ16B8M4CT2_PHY_PCS_ISO_RX_DATA_HI__PHY_PCS_ISO_RX_DATA_LO,PCS RX data low isolation register ()" hexmask.long.word 0x4 16.--31. 1. "PHY_PCS_ISO_RX_DATA_HI_15_0,Current value of pipe_rx_data[31:16] PHY output. (Not re-synchronized to apb_pclk)" newline hexmask.long.word 0x4 0.--15. 1. "PHY_PCS_ISO_RX_DATA_LO_15_0,Current value of pipe_rx_data[15:0] PHY output. (Not re-synchronized to apb_pclk)" rgroup.long 0xD020++0x7 line.long 0x0 "WIZ16B8M4CT2_PHY_ETH_ISO_MAC_CLK_DIV__PHY_ETH_ISO_MAC_CLK_CFG,Ethernet MAC clock configuration isolation register" hexmask.long.word 0x0 23.--31. 1. "PHY_ETH_ISO_MAC_CLK_DIV_15_7,Drives mac_div_sel1 PHY input for the associated lane when in PHY macro and PMA isolation mode." newline hexmask.long.byte 0x0 16.--22. 1. "PHY_ETH_ISO_MAC_CLK_DIV_6_0,Drives mac_div_sel0 PHY input for the associated lane when in PHY macro and PMA isolation mode." newline bitfld.long 0x0 0.--1. "PHY_ETH_ISO_MAC_CLK_CFG_1_0,Drives mac_src_sel PHY input for the associated lane when in PHY macro and PMA isolation mode." "0,1,2,3" line.long 0x4 "WIZ16B8M4CT2_PHY_INTERRUPT_STS,PHY interrupt status register" bitfld.long 0x4 15. "PHY_INTERRUPT_STS_15,State change monitor enable - 1 = state change monitor enabled 0 = state change monitor disabled. Note: Only the master lane's state change monitor for a link is enabled. The state change monitor for a slave lane is disabled.." "0: state change monitor disabled,1: state change monitor enabled" newline rbitfld.long 0x4 8.--10. "PHY_INTERRUPT_STS_10_8,Next power state/data rate - Only valid when one of the interrupt status bits is set. Indicates the requested power state or data rate for the state change failure. For PIPE requests loaded based on the following: For Raw.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 4.--6. "PHY_INTERRUPT_STS_6_4,Current power state/data rate - Only valid when one of the interrupt status bits is set. Indicates the starting power state or data rate for the state change failure. For PIPE requests loaded based on the following: For Raw.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 1. "PHY_INTERRUPT_STS_1,Data rate state change interrupt status - Set to 1 upon data rate change timeout. Cleared upon read. Bit is writeable to allow the interrupt to be set manually for test purposes.Only set high by data rate change timeout if bit[0] ==.." "0,1" newline bitfld.long 0x4 0. "PHY_INTERRUPT_STS_0,Power state change interrupt status - Set to 1 upon power state change timeout. Cleared upon read. Bit is writeable to allow the interrupt to set manually for test purposes. Only set high by power state change timeout if bit[1] == 0." "0,1" rgroup.long 0xE000++0xF line.long 0x0 "WIZ16B8M4CT2_PHY_PMA_CMN_CTRL2__PHY_PMA_CMN_CTRL1,PMA common control1 register" rbitfld.long 0x0 23. "PHY_PMA_CMN_CTRL2_7,Current value of cmn_pll1_locked PMA output" "0,1" newline rbitfld.long 0x0 22. "PHY_PMA_CMN_CTRL2_6,Current value of cmn_pll0_locked PMA output" "0,1" newline rbitfld.long 0x0 21. "PHY_PMA_CMN_CTRL2_5,Current value of cmn_pll1_clk_en_ack PMA output" "0,1" newline rbitfld.long 0x0 20. "PHY_PMA_CMN_CTRL2_4,Current value of cmn_pll0_clk_en_ack PMA output" "0,1" newline rbitfld.long 0x0 19. "PHY_PMA_CMN_CTRL2_3,Current value of cmn_pll1_disabled PMA output" "0,1" newline rbitfld.long 0x0 18. "PHY_PMA_CMN_CTRL2_2,Current value of cmn_pll0_disabled PMA output" "0,1" newline rbitfld.long 0x0 17. "PHY_PMA_CMN_CTRL2_1,Current value of cmn_pll1_ready PMA output" "0,1" newline rbitfld.long 0x0 16. "PHY_PMA_CMN_CTRL2_0,Current value of cmn_pll0_ready PMA output" "0,1" newline bitfld.long 0x0 6. "PHY_PMA_CMN_CTRL1_6,Drives cmn_refclk_rcv_out_en PMA input" "0,1" newline rbitfld.long 0x0 5. "PHY_PMA_CMN_CTRL1_5,Current value of cmn_macro_suspend_ack PMA output" "0,1" newline rbitfld.long 0x0 4. "PHY_PMA_CMN_CTRL1_4,Current value of cmn_refclk_active PMA output" "0,1" newline rbitfld.long 0x0 0. "PHY_PMA_CMN_CTRL1_0,Current value of cmn_ready pin PMA output" "0,1" line.long 0x4 "WIZ16B8M4CT2_PHY_PMA_PLL_RAW_CTRL__PHY_PMA_SSM_STATE,PMA SSM current state register" bitfld.long 0x4 17. "PHY_PMA_PLL_RAW_CTRL_1,Raw SerDes PLL1 control : When set to 1 cmn_pll1_en PMA input is controlled by PHY logic. When set to 0 cmn_pll1_en PMA input is forced low. When PLL1 is driving lanes configured for Raw SerDes operation this bit allows.." "0,1" newline bitfld.long 0x4 16. "PHY_PMA_PLL_RAW_CTRL_0,Raw SerDes PLL0 control : When set to 1 cmn_pll0_en PMA input is controlled by PHY logic. When set to 0 cmn_pll0_en PMA input is forced low. When PLL0 is driving lanes configured for Raw SerDes operation this bit allows.." "0,1" newline hexmask.long.word 0x4 0.--8. 1. "PHY_PMA_SSM_STATE_8_0,PMA SSM : Current state of the PMA startup state machine. PMA output (Not re-synchronized to apb_pclk)" line.long 0x8 "WIZ16B8M4CT2_PHY_PMA_ISO_PLL_CTRL0__PHY_PMA_ISO_CMN_CTRL,PMA common control signal isolation register" bitfld.long 0x8 23. "PHY_PMA_ISO_PLL_CTRL0_7,Drives cmn_pll1_ref_clk_sel PMA input when in PHY macro or PMA isolation mode." "0,1" newline bitfld.long 0x8 22. "PHY_PMA_ISO_PLL_CTRL0_6,Drives cmn_pll0_ref_clk_sel PMA input when in PHY macro or PMA isolation mode." "0,1" newline bitfld.long 0x8 21. "PHY_PMA_ISO_PLL_CTRL0_5,Drives cmn_pll1_mode_sel PMA input when in PMA isolation mode." "0,1" newline bitfld.long 0x8 20. "PHY_PMA_ISO_PLL_CTRL0_4,Drives cmn_pll0_mode_sel PMA input when in PMA isolation mode." "0,1" newline bitfld.long 0x8 19. "PHY_PMA_ISO_PLL_CTRL0_3,Drives cmn_pll1_clk_en PMA input when in PMA isolation mode" "0,1" newline bitfld.long 0x8 18. "PHY_PMA_ISO_PLL_CTRL0_2,Drives cmn_pll0_clk_en PMA input when in PMA isolation mode" "0,1" newline bitfld.long 0x8 17. "PHY_PMA_ISO_PLL_CTRL0_1,Drives cmn_pll1_en PMA input when in PMA isolation mode" "0,1" newline bitfld.long 0x8 16. "PHY_PMA_ISO_PLL_CTRL0_0,Drives cmn_pll0_en PMA input when in PMA isolation mode" "0,1" newline bitfld.long 0x8 15. "PHY_PMA_ISO_CMN_CTRL_15,Drives cmn_ref_clk_term_en PMA input when in PHY macro or PMA isolation modes" "0,1" newline bitfld.long 0x8 14. "PHY_PMA_ISO_CMN_CTRL_14,Drives cmn_ref_clk_dig_sel PMA input when in PHY macro or PMA isolation modes" "0,1" newline bitfld.long 0x8 12.--13. "PHY_PMA_ISO_CMN_CTRL_13_12,Drives cmn_ref_clk_dig_div PMA input when in PHY macro or PMA isolation modes" "0,1,2,3" newline bitfld.long 0x8 10.--11. "PHY_PMA_ISO_CMN_CTRL_11_10,Drives cmn_ref_clk_int_mode PMA input when in PHY macro and PMA isolation modes." "0,1,2,3" newline bitfld.long 0x8 8.--9. "PHY_PMA_ISO_CMN_CTRL_9_8,Drives cmn_ref_clk0_mode PMA input when in PHY macro and PMA isolation modes." "0,1,2,3" newline rbitfld.long 0x8 7. "PHY_PMA_ISO_CMN_CTRL_7,Current value of cmn_clock_stop_ack PMA output." "0,1" newline bitfld.long 0x8 6. "PHY_PMA_ISO_CMN_CTRL_6,Drives cmn_clock_stop_req PMA input when in PMA isolation mode" "0,1" newline bitfld.long 0x8 4. "PHY_PMA_ISO_CMN_CTRL_4,Drives cmn_ref_clk0_clk_gate_en PMA input when in PMA isolation mode." "0,1" newline bitfld.long 0x8 3. "PHY_PMA_ISO_CMN_CTRL_3,Drives cmn_refclk_disable PMA input when in PMA isolation mode." "0,1" newline bitfld.long 0x8 2. "PHY_PMA_ISO_CMN_CTRL_2,Drives cmn_macro_suspend_req PMA input when in PMA isolation mode." "0,1" newline bitfld.long 0x8 0. "PHY_PMA_ISO_CMN_CTRL_0,Drives cmn_reset_n PMA input when in PMA isolation mode." "0,1" line.long 0xC "WIZ16B8M4CT2_PHY_PMA_ISO_PLL_CTRL1,PMA PLL control1 isolation register" hexmask.long.byte 0xC 12.--15. 1. "PHY_PMA_ISO_PLL_CTRL1_15_12,Drives cmn_pll1_clk_datart1_div PMA input when in PMA isolation mode" newline hexmask.long.byte 0xC 8.--11. 1. "PHY_PMA_ISO_PLL_CTRL1_11_8,Drives cmn_pll1_clk_datart0_div PMA input when in PMA isolation mode" newline hexmask.long.byte 0xC 4.--7. 1. "PHY_PMA_ISO_PLL_CTRL1_7_4,Drives cmn_pll0_clk_datart1_div PMA input when in PMA isolation mode" newline hexmask.long.byte 0xC 0.--3. 1. "PHY_PMA_ISO_PLL_CTRL1_3_0,Drives cmn_pll0_clk_datart0_div PMA input when in PMA isolation mode" rgroup.long 0xE014++0x7 line.long 0x0 "WIZ16B8M4CT2_PHY_PMA_PLL0_SM_STATE,PMA PLL0 State Machine current state register" hexmask.long.word 0x0 16.--27. 1. "PHY_PMA_PLL0_SM_STATE_11_0,Current value of cmn_pllsm0_state[11:0]. PMA output (Debug only: Not re-synchronized)" line.long 0x4 "WIZ16B8M4CT2_PHY_PMA_PLL1_SM_STATE,PMA PLL1 State Machine current state register" hexmask.long.word 0x4 0.--11. 1. "PHY_PMA_PLL1_SM_STATE_11_0,Current value of cmn_pllsm1_state[11:0]. PMA output (Debug only: Not re-synchronized)" rgroup.long 0xE01C++0x3 line.long 0x0 "WIZ16B8M4CT2_PHY_PMA_ISOLATION_CTRL,PMA Isolation control register" bitfld.long 0x0 31. "PHY_PMA_ISOLATION_CTRL_15,PHY/PMA isolation enable (isolation_en) - When set enables isolation (PHY or PMA)." "0,1" newline bitfld.long 0x0 30. "PHY_PMA_ISOLATION_CTRL_14,PHY/PMA common isolation enable (cmn_isolation_en) - When in PHY Macro Isolation Mode the PHY common isolation register(s) are selected. When in PMA Isolation Mode the PMA common isolation register(s) are selected." "0,1" newline bitfld.long 0x0 28. "PHY_PMA_ISOLATION_CTRL_12,PHY/PMA isolation mode select (isolation_mode_sel) - When isolation_en is set this bit selects between PHY isolation mode and PMA isolation mode. 0 = PHYMacro isolation mode; 1 = PMA isolation mode." "0: PHYMacro isolation mode;,1: PMA isolation mode" newline hexmask.long.byte 0x0 16.--23. 1. "PHY_PMA_ISOLATION_CTRL_7_0,PHY/PMA lane isolation enable (ln_isolation_en) - When in PHY Macro Isolation Mode the selected PHY lane(s) isolation registers are selected. When in PMA Isolation Mode the selected PMA lane(s) isolation registers are.." rgroup.long 0xF000++0x1B line.long 0x0 "WIZ16B8M4CT2_PHY_PMA_XCVR_LPBK__PHY_PMA_XCVR_CTRL,PMA transceiver control register" bitfld.long 0x0 24. "PHY_PMA_XCVR_LPBK_8,Drives the tx_bist_hold PMA input for all lanes in the associated link (i.e. the bit associated with the master lane of the link drives all lanes in the link). Synchronized to transmit data rate clock." "0,1" newline bitfld.long 0x0 21. "PHY_PMA_XCVR_LPBK_5,Drives the xcvr_lpbk_fe_parallel_en PMA input for the associated lane." "0,1" newline bitfld.long 0x0 20. "PHY_PMA_XCVR_LPBK_4,Drives the xcvr_lpbk_ne_parallel_en PMA input for the associated lane." "0,1" newline bitfld.long 0x0 19. "PHY_PMA_XCVR_LPBK_3,Drives the xcvr_lpbk_recovered_clk_en PMA input for the associated lane." "0,1" newline bitfld.long 0x0 18. "PHY_PMA_XCVR_LPBK_2,Drives the xcvr_lpbk_line_en PMA input for the associated lane." "0,1" newline bitfld.long 0x0 17. "PHY_PMA_XCVR_LPBK_1,Drives the xcvr_lpbk_isi_gen_en PMA input for the associated lane." "0,1" newline bitfld.long 0x0 16. "PHY_PMA_XCVR_LPBK_0,Drives the xcvr_lpbk_serial_en PMA input for the associated lane." "0,1" newline bitfld.long 0x0 8. "PHY_PMA_XCVR_CTRL_8,Drives the tx_differential_invert PMA input for the associated lane." "0,1" newline rbitfld.long 0x0 4. "PHY_PMA_XCVR_CTRL_4,Current value of rx_cdrlf_fphl_locked PMA output for the associated lane." "0,1" newline rbitfld.long 0x0 3. "PHY_PMA_XCVR_CTRL_3,Current value of rx_bist_status PMA output for the associated lane." "0,1" newline rbitfld.long 0x0 2. "PHY_PMA_XCVR_CTRL_2,Current value of rx_bist_err_toggle PMA output for the associated lane." "0,1" newline rbitfld.long 0x0 1. "PHY_PMA_XCVR_CTRL_1,Current value of rx_bist_sync PMA output for the associated lane." "0,1" newline bitfld.long 0x0 0. "PHY_PMA_XCVR_CTRL_0,Drives the rx_differential_invert PMA input for the associated lane." "0,1" line.long 0x4 "WIZ16B8M4CT2_PHY_PMA_ISO_XCVR_CTRL__PHY_PMA_PI_POS,PMA Transceiver control isolation register" rbitfld.long 0x4 31. "PHY_PMA_ISO_XCVR_CTRL_15,Current value of xcvr_pll_clk_en_ack PMA output for the associated lane." "0,1" newline bitfld.long 0x4 29. "PHY_PMA_ISO_XCVR_CTRL_13,Drives tx_lfps_en PMA input for the associated lane when in PMA isolation mode." "0,1" newline bitfld.long 0x4 28. "PHY_PMA_ISO_XCVR_CTRL_12,Drives tx_elec_idle PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1" newline rbitfld.long 0x4 27. "PHY_PMA_ISO_XCVR_CTRL_11,Current value of tx_rcv_detected PMA output for the associated lane. (Not re-synchronized to apb_pclk)" "0,1" newline rbitfld.long 0x4 26. "PHY_PMA_ISO_XCVR_CTRL_10,Current value of tx_rcv_detect_done PMA ouptut for the associated lane." "0,1" newline bitfld.long 0x4 25. "PHY_PMA_ISO_XCVR_CTRL_9,Drives tx_rcv_detect_en PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1" newline bitfld.long 0x4 24. "PHY_PMA_ISO_XCVR_CTRL_8,Drives xcvr_link_reset_n PMA input for the associated lane when in PMA isolation mode." "0,1" newline bitfld.long 0x4 23. "PHY_PMA_ISO_XCVR_CTRL_7,Drives xcvr_pll_clk_en PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1" newline bitfld.long 0x4 21. "PHY_PMA_ISO_XCVR_CTRL_5,Drives xcvr_lane_suspend PMA input for the associated lane when in PMA isolation mode." "0,1" newline rbitfld.long 0x4 20. "PHY_PMA_ISO_XCVR_CTRL_4,Current value of rx_lfps_detect PMA output for the associated lane." "0,1" newline rbitfld.long 0x4 19. "PHY_PMA_ISO_XCVR_CTRL_3,Current value of rx_signal_detect PMA output for the associated lane." "0,1" newline bitfld.long 0x4 17. "PHY_PMA_ISO_XCVR_CTRL_1,Drives rx_termination PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "PHY_PMA_PI_POS_15_8,Current value of rx_pi_val PMA output for the associated lane." newline hexmask.long.byte 0x4 0.--7. 1. "PHY_PMA_PI_POS_7_0,Current value of rx_eye_plot_pi_val PMA output for the associated lane." line.long 0x8 "WIZ16B8M4CT2_PHY_PMA_ISO_TX_LPC_HI__PHY_PMA_ISO_TX_LPC_LO,PMA transmitter local preset coefficient low isolation register" rbitfld.long 0x8 31. "PHY_PMA_ISO_TX_LPC_HI_15,Current value of tx_local_preset_coef_valid PMA output for the associated lane." "0,1" newline bitfld.long 0x8 28. "PHY_PMA_ISO_TX_LPC_HI_12,Drives tx_get_local_preset_coef PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1" newline hexmask.long.byte 0x8 24.--27. 1. "PHY_PMA_ISO_TX_LPC_HI_11_8,Drives tx_local_preset_index PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." newline hexmask.long.byte 0x8 16.--21. 1. "PHY_PMA_ISO_TX_LPC_HI_5_0,Value of tx_local_tx_preset_coef[17:12] PMA output for the associated lane captured upon assertion of tx_local_preset_coef_valid for the associated lane. Cleared upon read." newline hexmask.long.byte 0x8 8.--13. 1. "PHY_PMA_ISO_TX_LPC_LO_13_8,Value of tx_local_tx_preset_coef[11:6] PMA output for the associated lane captured upon assertion of tx_local_preset_coef_valid for the associated lane. Cleared upon read." newline hexmask.long.byte 0x8 0.--5. 1. "PHY_PMA_ISO_TX_LPC_LO_5_0,Value of tx_local_tx_preset_coef[5:0] PMA output for the associated lane captured upon assertion of tx_local_preset_coef_valid for the associated lane. Cleared upon read." line.long 0xC "WIZ16B8M4CT2_PHY_PMA_ISO_TX_DMPH_HI__PHY_PMA_ISO_TX_DMPH_LO,PMA Tx de-emphasis low isolation register" hexmask.long.byte 0xC 16.--21. 1. "PHY_PMA_ISO_TX_DMPH_HI_5_0,Drives tx_deemphasis[17:12] PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." newline hexmask.long.byte 0xC 8.--13. 1. "PHY_PMA_ISO_TX_DMPH_LO_13_8,Drives tx_deemphasis[11:6] PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." newline hexmask.long.byte 0xC 0.--5. 1. "PHY_PMA_ISO_TX_DMPH_LO_5_0,Drives tx_deemphasis[5:0] PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." line.long 0x10 "WIZ16B8M4CT2_PHY_PMA_ISO_TX_MGN__PHY_PMA_ISO_TX_FSLF,PMA Tx FS/LF isolation register" bitfld.long 0x10 24. "PHY_PMA_ISO_TX_MGN_8,Drives tx_low_power_swing_en PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1" newline bitfld.long 0x10 16.--18. "PHY_PMA_ISO_TX_MGN_2_0,Drives tx_vmargin PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 8.--13. 1. "PHY_PMA_ISO_TX_FSLF_13_8,Current value of tx_local_fs PMA ouptut for the associated lane. (Not re-synchronized to apb_pclk)" newline hexmask.long.byte 0x10 0.--5. 1. "PHY_PMA_ISO_TX_FSLF_5_0,Current value of tx_local_lf PMA ouptut for the associated lane. (Not re-synchronized to apb_pclk)" line.long 0x14 "WIZ16B8M4CT2_PHY_PMA_ISO_PWRST_CTRL__PHY_PMA_ISO_LINK_MODE,PMA Isolation mode control register" bitfld.long 0x14 31. "PHY_PMA_ISO_PWRST_CTRL_15,rx_sig_det_en_ext_ln_{nnnn} PMA input when in PMA isolation mode. (Used for PCIe)" "0,1" newline bitfld.long 0x14 30. "PHY_PMA_ISO_PWRST_CTRL_14,tx_cmn_mode_en_ext_ln_{nnnn} PMA input when in PMA isolation mode. (Used for PCIe)" "0,1" newline hexmask.long.byte 0x14 24.--29. 1. "PHY_PMA_ISO_PWRST_CTRL_13_8,Current value of xcvr_power_state_ack_ln_{nnnn} PMA output." newline hexmask.long.byte 0x14 16.--21. 1. "PHY_PMA_ISO_PWRST_CTRL_5_0,Drives xcvr_power_state_req_ln_{nnnn} PMA input when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode.." newline bitfld.long 0x14 15. "PHY_PMA_ISO_LINK_MODE_15,tx_reset_n_ln_{nnnn} PMA input when in PMA isolation mode." "0,1" newline bitfld.long 0x14 14. "PHY_PMA_ISO_LINK_MODE_14,rx_reset_n_ln_{nnnn} PMA input when in PMA isolation mode." "0,1" newline bitfld.long 0x14 4.--5. "PHY_PMA_ISO_LINK_MODE_5_4,Drives xcvr_standard_mode_ln_{nnnn} PMA input when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1,2,3" newline bitfld.long 0x14 0.--2. "PHY_PMA_ISO_LINK_MODE_2_0,Drives xcvr_data_width_ln_{nnnn} PMA input when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1,2,3,4,5,6,7" line.long 0x18 "WIZ16B8M4CT2_PHY_PMA_ISO_RX_EQ_CTRL,PMA RX equalization control isolation register" bitfld.long 0x18 29. "PHY_PMA_ISO_RX_EQ_CTRL_13,Drives rx_eq_training_data_valid PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1" newline bitfld.long 0x18 28. "PHY_PMA_ISO_RX_EQ_CTRL_12,Drives rx_eq_training PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1" newline hexmask.long.byte 0x18 20.--25. 1. "PHY_PMA_ISO_RX_EQ_CTRL_9_4,The value of rx_link_eval_fb_dir_change PMA output for the associated lane upon assertion of rx_eq_eval_status to PMA. Cleared upon read." newline rbitfld.long 0x18 19. "PHY_PMA_ISO_RX_EQ_CTRL_3,The value of rx_eq_eval_complete PMA output for the associated lane upon assertion of rx_eq_eval_status. Cleared upon read." "0,1" newline bitfld.long 0x18 18. "PHY_PMA_ISO_RX_EQ_CTRL_2,Drives rx_invalid_request PMA input for the associated lane when in PMA isolation mode." "0,1" newline rbitfld.long 0x18 17. "PHY_PMA_ISO_RX_EQ_CTRL_1,Current value of rx_eq_eval_status PMA output for the associated lane." "0,1" newline bitfld.long 0x18 16. "PHY_PMA_ISO_RX_EQ_CTRL_0,Drives rx_eq_eval PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1" rgroup.long 0xF01C++0x7 line.long 0x0 "WIZ16B8M4CT2_PHY_PMA_ISO_DATA_HI__PHY_PMA_ISO_DATA_LO,PMA low data isolation register" hexmask.long.byte 0x0 16.--19. 1. "PHY_PMA_ISO_DATA_HI_3_0,Current value of rx_rd[19:16] PMA output for the current lane. (Not re-synchronized to apb_pclk). This register can be written and the value will drive tx_td[19:16] for the associated lane when in PMA isolation mode or PHY.." newline hexmask.long.word 0x0 0.--15. 1. "PHY_PMA_ISO_DATA_LO_15_0,Current value of rx_rd[15:0] PMA output for the current lane. (Not re-synchronized to apb_pclk). This register can be written and the value will drive tx_td[15:0] for the associated lane when in PMA isolation mode or PHY.." line.long 0x4 "WIZ16B8M4CT2_PHY_PMA_PSM_STATE_HI__PHY_PMA_PSM_STATE_LO,PMA PSM current state lower register" bitfld.long 0x4 28. "PHY_PMA_PSM_STATE_HI_12,Current value of xcvr_psm_ready for the associated lane." "0,1" newline hexmask.long.word 0x4 16.--25. 1. "PHY_PMA_PSM_STATE_HI_9_0,Current value of xcvr_psm_state[25:16] for the associated lane - PMA power state machine state. (Not re-synchronized to apb_pclk)" newline hexmask.long.word 0x4 0.--15. 1. "PHY_PMA_PSM_STATE_LO_15_0,Current value of xcvr_psm_state[15:0] for the associated lane - PMA power state machine state. (Not re-synchronized to apb_pclk)" tree.end tree "TIMER" base ad:0x0 tree "TIMER0_CFG (TIMER0_CFG)" base ad:0x2400000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER1_CFG (TIMER1_CFG)" base ad:0x2410000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER2_CFG (TIMER2_CFG)" base ad:0x2420000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER3_CFG (TIMER3_CFG)" base ad:0x2430000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER4_CFG (TIMER4_CFG)" base ad:0x2440000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER5_CFG (TIMER5_CFG)" base ad:0x2450000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER6_CFG (TIMER6_CFG)" base ad:0x2460000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER7_CFG (TIMER7_CFG)" base ad:0x2470000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER8_CFG (TIMER8_CFG)" base ad:0x2480000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER9_CFG (TIMER9_CFG)" base ad:0x2490000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER10_CFG (TIMER10_CFG)" base ad:0x24A0000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER11_CFG (TIMER11_CFG)" base ad:0x24B0000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER12_CFG (TIMER12_CFG)" base ad:0x24C0000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER13_CFG (TIMER13_CFG)" base ad:0x24D0000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER14_CFG (TIMER14_CFG)" base ad:0x24E0000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER15_CFG (TIMER15_CFG)" base ad:0x24F0000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER16_CFG (TIMER16_CFG)" base ad:0x2500000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER17_CFG (TIMER17_CFG)" base ad:0x2510000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER18_CFG (TIMER18_CFG)" base ad:0x2520000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER19_CFG (TIMER19_CFG)" base ad:0x2530000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR," bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" rgroup.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" rgroup.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" rgroup.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree.end tree "TIMESYNC_INTRTR0_INTR_ROUTER_CFG (TIMESYNC_INTRTR0_INTR_ROUTER_CFG)" base ad:0xA40000 rgroup.long 0x0++0x3 line.long 0x0 "INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" rgroup.long 0x4++0x3 line.long 0x0 "INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.byte 0x0 0.--5. 1. "MUX_CNTL,Mux control for interrupt N" tree.end tree "UART" base ad:0x0 tree "UART0 (UART0)" base ad:0x2800000 rgroup.long 0x0++0x3 line.long 0x0 "MEM_DLL,Divisor Latches Low Register" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" rgroup.long 0x0++0x7 line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" line.long 0x4 "MEM_DLH,Divisor Latches High Register" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.." bitfld.long 0x0 6.--7. "NOT_USED2," "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "NOT_USED1," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x7 line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "CTS_IT," "0,1" newline bitfld.long 0x0 6. "RTS_IT," "0,1" newline bitfld.long 0x0 5. "XOFF_IT," "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE," "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT," "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" line.long 0x4 "MEM_EFR,Enhanced Feature Register" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" rgroup.long 0x8++0x3 line.long 0x0 "MEM_FCR,Notes:" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered. If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of.." "0,1,2,3" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 0. "FIFO_EN," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE," newline bitfld.long 0x0 0. "IT_PENDING," "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "DIV_EN," "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1," "0,1" newline bitfld.long 0x0 3. "PARITY_EN," "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3" line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline rbitfld.long 0x4 7. "RESERVED," "0,1" newline bitfld.long 0x4 6. "TCR_TLR," "0,1" newline bitfld.long 0x4 5. "XON_EN," "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN," "0,1" newline bitfld.long 0x4 3. "CD_STS_CH," "0,1" newline bitfld.long 0x4 2. "RI_STS_CH," "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1" newline bitfld.long 0x4 0. "DTR," "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_CIR," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "RESERVED," "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_IRDA," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL," "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE," "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG," "0,1" newline bitfld.long 0x0 3. "ABORT," "0,1" newline bitfld.long 0x0 2. "CRC," "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_UART," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "RX_FIFO_STS," "0,1" newline bitfld.long 0x0 6. "TX_SR_E," "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E," "0,1" newline bitfld.long 0x0 4. "RX_BI," "0,1" newline bitfld.long 0x0 3. "RX_FE," "0,1" newline bitfld.long 0x0 2. "RX_PE," "0,1" newline bitfld.long 0x0 1. "RX_OE," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS," "0,1" newline bitfld.long 0x0 0. "CTS_STS," "0,1" rgroup.long 0x18++0x3 line.long 0x0 "MEM_TCR,Transmission Control Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" rgroup.long 0x18++0x7 line.long 0x0 "MEM_XOFF1,XOFF1 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" rgroup.long 0x1C++0x3 line.long 0x0 "MEM_TLR,Trigger Level Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" rgroup.long 0x1C++0xB line.long 0x0 "MEM_XOFF2,XOFF2 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP," "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7" line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is :" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_SFLSR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR," "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR," "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT," "0,1" newline bitfld.long 0x0 1. "CRC_ERROR," "0,1" newline bitfld.long 0x0 0. "RESERVED0," "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_TXFLL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" rgroup.long 0x2C++0x7 line.long 0x0 "MEM_TXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "MEM_RXFLL,IrDA modes only." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "MEM_SFREGL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" rgroup.long 0x34++0x3 line.long 0x0 "MEM_RXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "MEM_SFREGH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" rgroup.long 0x38++0x3 line.long 0x0 "MEM_BLR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED," rgroup.long 0x38++0x3 line.long 0x0 "MEM_UASR,UART Autobauding Status Register" bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." rgroup.long 0x3C++0xF line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX," "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "RX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 5. "DSR_IT," "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT," "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL," "0,1" line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x8 3.--7. 1. "RESERVED," newline bitfld.long 0x8 2. "DMA_COUNTER_RST," "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL," "0,1" line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED," newline hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." rgroup.long 0x54++0x3 line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "MEM_SYSS," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED," newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" rgroup.long 0x5C++0x7 line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN," "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT," "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY," "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY," "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY," "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY," "0,1" line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.." rgroup.long 0x64++0x7 line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL," line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL," rgroup.long 0x6C++0xB line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED," newline bitfld.long 0x0 2. "RHR_IT_DIS," "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED," newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1" line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED," line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED," rgroup.long 0x80++0x23 line.long 0x0 "MEM_MDR3,Mode definition register 3." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2," newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1" line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "MEM_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1," newline rbitfld.long 0x8 7. "RESERVED," "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7" line.long 0xC "MEM_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1," newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "MEM_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1," newline rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "MEM_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1," newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "MEM_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" rgroup.long 0xA4++0xF line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" line.long 0x4 "MEM_MAR,Multidrop Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "MEM_MMR,Multidrop Mask Register" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART1 (UART1)" base ad:0x2810000 rgroup.long 0x0++0x3 line.long 0x0 "MEM_DLL,Divisor Latches Low Register" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" rgroup.long 0x0++0x7 line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" line.long 0x4 "MEM_DLH,Divisor Latches High Register" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.." bitfld.long 0x0 6.--7. "NOT_USED2," "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "NOT_USED1," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x7 line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "CTS_IT," "0,1" newline bitfld.long 0x0 6. "RTS_IT," "0,1" newline bitfld.long 0x0 5. "XOFF_IT," "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE," "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT," "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" line.long 0x4 "MEM_EFR,Enhanced Feature Register" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" rgroup.long 0x8++0x3 line.long 0x0 "MEM_FCR,Notes:" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered. If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of.." "0,1,2,3" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 0. "FIFO_EN," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE," newline bitfld.long 0x0 0. "IT_PENDING," "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "DIV_EN," "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1," "0,1" newline bitfld.long 0x0 3. "PARITY_EN," "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3" line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline rbitfld.long 0x4 7. "RESERVED," "0,1" newline bitfld.long 0x4 6. "TCR_TLR," "0,1" newline bitfld.long 0x4 5. "XON_EN," "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN," "0,1" newline bitfld.long 0x4 3. "CD_STS_CH," "0,1" newline bitfld.long 0x4 2. "RI_STS_CH," "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1" newline bitfld.long 0x4 0. "DTR," "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_CIR," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "RESERVED," "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_IRDA," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL," "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE," "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG," "0,1" newline bitfld.long 0x0 3. "ABORT," "0,1" newline bitfld.long 0x0 2. "CRC," "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_UART," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "RX_FIFO_STS," "0,1" newline bitfld.long 0x0 6. "TX_SR_E," "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E," "0,1" newline bitfld.long 0x0 4. "RX_BI," "0,1" newline bitfld.long 0x0 3. "RX_FE," "0,1" newline bitfld.long 0x0 2. "RX_PE," "0,1" newline bitfld.long 0x0 1. "RX_OE," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS," "0,1" newline bitfld.long 0x0 0. "CTS_STS," "0,1" rgroup.long 0x18++0x3 line.long 0x0 "MEM_TCR,Transmission Control Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" rgroup.long 0x18++0x7 line.long 0x0 "MEM_XOFF1,XOFF1 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" rgroup.long 0x1C++0x3 line.long 0x0 "MEM_TLR,Trigger Level Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" rgroup.long 0x1C++0xB line.long 0x0 "MEM_XOFF2,XOFF2 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP," "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7" line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is :" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_SFLSR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR," "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR," "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT," "0,1" newline bitfld.long 0x0 1. "CRC_ERROR," "0,1" newline bitfld.long 0x0 0. "RESERVED0," "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_TXFLL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" rgroup.long 0x2C++0x7 line.long 0x0 "MEM_TXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "MEM_RXFLL,IrDA modes only." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "MEM_SFREGL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" rgroup.long 0x34++0x3 line.long 0x0 "MEM_RXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "MEM_SFREGH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" rgroup.long 0x38++0x3 line.long 0x0 "MEM_BLR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED," rgroup.long 0x38++0x3 line.long 0x0 "MEM_UASR,UART Autobauding Status Register" bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." rgroup.long 0x3C++0xF line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX," "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "RX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 5. "DSR_IT," "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT," "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL," "0,1" line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x8 3.--7. 1. "RESERVED," newline bitfld.long 0x8 2. "DMA_COUNTER_RST," "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL," "0,1" line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED," newline hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." rgroup.long 0x54++0x3 line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "MEM_SYSS," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED," newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" rgroup.long 0x5C++0x7 line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN," "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT," "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY," "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY," "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY," "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY," "0,1" line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.." rgroup.long 0x64++0x7 line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL," line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL," rgroup.long 0x6C++0xB line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED," newline bitfld.long 0x0 2. "RHR_IT_DIS," "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED," newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1" line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED," line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED," rgroup.long 0x80++0x23 line.long 0x0 "MEM_MDR3,Mode definition register 3." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2," newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1" line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "MEM_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1," newline rbitfld.long 0x8 7. "RESERVED," "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7" line.long 0xC "MEM_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1," newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "MEM_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1," newline rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "MEM_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1," newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "MEM_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" rgroup.long 0xA4++0xF line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" line.long 0x4 "MEM_MAR,Multidrop Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "MEM_MMR,Multidrop Mask Register" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART2 (UART2)" base ad:0x2820000 rgroup.long 0x0++0x3 line.long 0x0 "MEM_DLL,Divisor Latches Low Register" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" rgroup.long 0x0++0x7 line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" line.long 0x4 "MEM_DLH,Divisor Latches High Register" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.." bitfld.long 0x0 6.--7. "NOT_USED2," "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "NOT_USED1," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x7 line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "CTS_IT," "0,1" newline bitfld.long 0x0 6. "RTS_IT," "0,1" newline bitfld.long 0x0 5. "XOFF_IT," "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE," "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT," "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" line.long 0x4 "MEM_EFR,Enhanced Feature Register" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" rgroup.long 0x8++0x3 line.long 0x0 "MEM_FCR,Notes:" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered. If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of.." "0,1,2,3" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 0. "FIFO_EN," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE," newline bitfld.long 0x0 0. "IT_PENDING," "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "DIV_EN," "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1," "0,1" newline bitfld.long 0x0 3. "PARITY_EN," "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3" line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline rbitfld.long 0x4 7. "RESERVED," "0,1" newline bitfld.long 0x4 6. "TCR_TLR," "0,1" newline bitfld.long 0x4 5. "XON_EN," "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN," "0,1" newline bitfld.long 0x4 3. "CD_STS_CH," "0,1" newline bitfld.long 0x4 2. "RI_STS_CH," "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1" newline bitfld.long 0x4 0. "DTR," "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_CIR," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "RESERVED," "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_IRDA," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL," "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE," "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG," "0,1" newline bitfld.long 0x0 3. "ABORT," "0,1" newline bitfld.long 0x0 2. "CRC," "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_UART," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "RX_FIFO_STS," "0,1" newline bitfld.long 0x0 6. "TX_SR_E," "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E," "0,1" newline bitfld.long 0x0 4. "RX_BI," "0,1" newline bitfld.long 0x0 3. "RX_FE," "0,1" newline bitfld.long 0x0 2. "RX_PE," "0,1" newline bitfld.long 0x0 1. "RX_OE," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS," "0,1" newline bitfld.long 0x0 0. "CTS_STS," "0,1" rgroup.long 0x18++0x3 line.long 0x0 "MEM_TCR,Transmission Control Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" rgroup.long 0x18++0x7 line.long 0x0 "MEM_XOFF1,XOFF1 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" rgroup.long 0x1C++0x3 line.long 0x0 "MEM_TLR,Trigger Level Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" rgroup.long 0x1C++0xB line.long 0x0 "MEM_XOFF2,XOFF2 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP," "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7" line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is :" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_SFLSR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR," "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR," "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT," "0,1" newline bitfld.long 0x0 1. "CRC_ERROR," "0,1" newline bitfld.long 0x0 0. "RESERVED0," "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_TXFLL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" rgroup.long 0x2C++0x7 line.long 0x0 "MEM_TXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "MEM_RXFLL,IrDA modes only." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "MEM_SFREGL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" rgroup.long 0x34++0x3 line.long 0x0 "MEM_RXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "MEM_SFREGH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" rgroup.long 0x38++0x3 line.long 0x0 "MEM_BLR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED," rgroup.long 0x38++0x3 line.long 0x0 "MEM_UASR,UART Autobauding Status Register" bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." rgroup.long 0x3C++0xF line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX," "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "RX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 5. "DSR_IT," "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT," "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL," "0,1" line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x8 3.--7. 1. "RESERVED," newline bitfld.long 0x8 2. "DMA_COUNTER_RST," "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL," "0,1" line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED," newline hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." rgroup.long 0x54++0x3 line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "MEM_SYSS," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED," newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" rgroup.long 0x5C++0x7 line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN," "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT," "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY," "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY," "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY," "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY," "0,1" line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.." rgroup.long 0x64++0x7 line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL," line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL," rgroup.long 0x6C++0xB line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED," newline bitfld.long 0x0 2. "RHR_IT_DIS," "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED," newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1" line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED," line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED," rgroup.long 0x80++0x23 line.long 0x0 "MEM_MDR3,Mode definition register 3." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2," newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1" line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "MEM_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1," newline rbitfld.long 0x8 7. "RESERVED," "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7" line.long 0xC "MEM_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1," newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "MEM_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1," newline rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "MEM_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1," newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "MEM_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" rgroup.long 0xA4++0xF line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" line.long 0x4 "MEM_MAR,Multidrop Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "MEM_MMR,Multidrop Mask Register" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART3 (UART3)" base ad:0x2830000 rgroup.long 0x0++0x3 line.long 0x0 "MEM_DLL,Divisor Latches Low Register" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" rgroup.long 0x0++0x7 line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" line.long 0x4 "MEM_DLH,Divisor Latches High Register" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.." bitfld.long 0x0 6.--7. "NOT_USED2," "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "NOT_USED1," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x7 line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "CTS_IT," "0,1" newline bitfld.long 0x0 6. "RTS_IT," "0,1" newline bitfld.long 0x0 5. "XOFF_IT," "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE," "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT," "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" line.long 0x4 "MEM_EFR,Enhanced Feature Register" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" rgroup.long 0x8++0x3 line.long 0x0 "MEM_FCR,Notes:" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered. If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of.." "0,1,2,3" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 0. "FIFO_EN," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE," newline bitfld.long 0x0 0. "IT_PENDING," "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "DIV_EN," "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1," "0,1" newline bitfld.long 0x0 3. "PARITY_EN," "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3" line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline rbitfld.long 0x4 7. "RESERVED," "0,1" newline bitfld.long 0x4 6. "TCR_TLR," "0,1" newline bitfld.long 0x4 5. "XON_EN," "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN," "0,1" newline bitfld.long 0x4 3. "CD_STS_CH," "0,1" newline bitfld.long 0x4 2. "RI_STS_CH," "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1" newline bitfld.long 0x4 0. "DTR," "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_CIR," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "RESERVED," "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_IRDA," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL," "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE," "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG," "0,1" newline bitfld.long 0x0 3. "ABORT," "0,1" newline bitfld.long 0x0 2. "CRC," "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_UART," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "RX_FIFO_STS," "0,1" newline bitfld.long 0x0 6. "TX_SR_E," "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E," "0,1" newline bitfld.long 0x0 4. "RX_BI," "0,1" newline bitfld.long 0x0 3. "RX_FE," "0,1" newline bitfld.long 0x0 2. "RX_PE," "0,1" newline bitfld.long 0x0 1. "RX_OE," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS," "0,1" newline bitfld.long 0x0 0. "CTS_STS," "0,1" rgroup.long 0x18++0x3 line.long 0x0 "MEM_TCR,Transmission Control Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" rgroup.long 0x18++0x7 line.long 0x0 "MEM_XOFF1,XOFF1 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" rgroup.long 0x1C++0x3 line.long 0x0 "MEM_TLR,Trigger Level Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" rgroup.long 0x1C++0xB line.long 0x0 "MEM_XOFF2,XOFF2 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP," "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7" line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is :" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_SFLSR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR," "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR," "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT," "0,1" newline bitfld.long 0x0 1. "CRC_ERROR," "0,1" newline bitfld.long 0x0 0. "RESERVED0," "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_TXFLL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" rgroup.long 0x2C++0x7 line.long 0x0 "MEM_TXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "MEM_RXFLL,IrDA modes only." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "MEM_SFREGL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" rgroup.long 0x34++0x3 line.long 0x0 "MEM_RXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "MEM_SFREGH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" rgroup.long 0x38++0x3 line.long 0x0 "MEM_BLR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED," rgroup.long 0x38++0x3 line.long 0x0 "MEM_UASR,UART Autobauding Status Register" bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." rgroup.long 0x3C++0xF line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX," "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "RX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 5. "DSR_IT," "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT," "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL," "0,1" line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x8 3.--7. 1. "RESERVED," newline bitfld.long 0x8 2. "DMA_COUNTER_RST," "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL," "0,1" line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED," newline hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." rgroup.long 0x54++0x3 line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "MEM_SYSS," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED," newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" rgroup.long 0x5C++0x7 line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN," "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT," "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY," "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY," "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY," "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY," "0,1" line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.." rgroup.long 0x64++0x7 line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL," line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL," rgroup.long 0x6C++0xB line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED," newline bitfld.long 0x0 2. "RHR_IT_DIS," "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED," newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1" line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED," line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED," rgroup.long 0x80++0x23 line.long 0x0 "MEM_MDR3,Mode definition register 3." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2," newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1" line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "MEM_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1," newline rbitfld.long 0x8 7. "RESERVED," "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7" line.long 0xC "MEM_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1," newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "MEM_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1," newline rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "MEM_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1," newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "MEM_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" rgroup.long 0xA4++0xF line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" line.long 0x4 "MEM_MAR,Multidrop Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "MEM_MMR,Multidrop Mask Register" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART4 (UART4)" base ad:0x2840000 rgroup.long 0x0++0x3 line.long 0x0 "MEM_DLL,Divisor Latches Low Register" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" rgroup.long 0x0++0x7 line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" line.long 0x4 "MEM_DLH,Divisor Latches High Register" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.." bitfld.long 0x0 6.--7. "NOT_USED2," "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "NOT_USED1," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x7 line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "CTS_IT," "0,1" newline bitfld.long 0x0 6. "RTS_IT," "0,1" newline bitfld.long 0x0 5. "XOFF_IT," "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE," "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT," "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" line.long 0x4 "MEM_EFR,Enhanced Feature Register" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" rgroup.long 0x8++0x3 line.long 0x0 "MEM_FCR,Notes:" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered. If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of.." "0,1,2,3" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 0. "FIFO_EN," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE," newline bitfld.long 0x0 0. "IT_PENDING," "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "DIV_EN," "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1," "0,1" newline bitfld.long 0x0 3. "PARITY_EN," "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3" line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline rbitfld.long 0x4 7. "RESERVED," "0,1" newline bitfld.long 0x4 6. "TCR_TLR," "0,1" newline bitfld.long 0x4 5. "XON_EN," "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN," "0,1" newline bitfld.long 0x4 3. "CD_STS_CH," "0,1" newline bitfld.long 0x4 2. "RI_STS_CH," "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1" newline bitfld.long 0x4 0. "DTR," "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_CIR," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "RESERVED," "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_IRDA," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL," "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE," "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG," "0,1" newline bitfld.long 0x0 3. "ABORT," "0,1" newline bitfld.long 0x0 2. "CRC," "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_UART," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "RX_FIFO_STS," "0,1" newline bitfld.long 0x0 6. "TX_SR_E," "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E," "0,1" newline bitfld.long 0x0 4. "RX_BI," "0,1" newline bitfld.long 0x0 3. "RX_FE," "0,1" newline bitfld.long 0x0 2. "RX_PE," "0,1" newline bitfld.long 0x0 1. "RX_OE," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS," "0,1" newline bitfld.long 0x0 0. "CTS_STS," "0,1" rgroup.long 0x18++0x3 line.long 0x0 "MEM_TCR,Transmission Control Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" rgroup.long 0x18++0x7 line.long 0x0 "MEM_XOFF1,XOFF1 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" rgroup.long 0x1C++0x3 line.long 0x0 "MEM_TLR,Trigger Level Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" rgroup.long 0x1C++0xB line.long 0x0 "MEM_XOFF2,XOFF2 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP," "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7" line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is :" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_SFLSR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR," "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR," "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT," "0,1" newline bitfld.long 0x0 1. "CRC_ERROR," "0,1" newline bitfld.long 0x0 0. "RESERVED0," "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_TXFLL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" rgroup.long 0x2C++0x7 line.long 0x0 "MEM_TXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "MEM_RXFLL,IrDA modes only." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "MEM_SFREGL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" rgroup.long 0x34++0x3 line.long 0x0 "MEM_RXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "MEM_SFREGH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" rgroup.long 0x38++0x3 line.long 0x0 "MEM_BLR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED," rgroup.long 0x38++0x3 line.long 0x0 "MEM_UASR,UART Autobauding Status Register" bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." rgroup.long 0x3C++0xF line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX," "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "RX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 5. "DSR_IT," "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT," "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL," "0,1" line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x8 3.--7. 1. "RESERVED," newline bitfld.long 0x8 2. "DMA_COUNTER_RST," "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL," "0,1" line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED," newline hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." rgroup.long 0x54++0x3 line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "MEM_SYSS," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED," newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" rgroup.long 0x5C++0x7 line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN," "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT," "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY," "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY," "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY," "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY," "0,1" line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.." rgroup.long 0x64++0x7 line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL," line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL," rgroup.long 0x6C++0xB line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED," newline bitfld.long 0x0 2. "RHR_IT_DIS," "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED," newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1" line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED," line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED," rgroup.long 0x80++0x23 line.long 0x0 "MEM_MDR3,Mode definition register 3." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2," newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1" line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "MEM_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1," newline rbitfld.long 0x8 7. "RESERVED," "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7" line.long 0xC "MEM_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1," newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "MEM_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1," newline rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "MEM_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1," newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "MEM_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" rgroup.long 0xA4++0xF line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" line.long 0x4 "MEM_MAR,Multidrop Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "MEM_MMR,Multidrop Mask Register" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART5 (UART5)" base ad:0x2850000 rgroup.long 0x0++0x3 line.long 0x0 "MEM_DLL,Divisor Latches Low Register" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" rgroup.long 0x0++0x7 line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" line.long 0x4 "MEM_DLH,Divisor Latches High Register" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.." bitfld.long 0x0 6.--7. "NOT_USED2," "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "NOT_USED1," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x7 line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "CTS_IT," "0,1" newline bitfld.long 0x0 6. "RTS_IT," "0,1" newline bitfld.long 0x0 5. "XOFF_IT," "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE," "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT," "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" line.long 0x4 "MEM_EFR,Enhanced Feature Register" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" rgroup.long 0x8++0x3 line.long 0x0 "MEM_FCR,Notes:" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered. If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of.." "0,1,2,3" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 0. "FIFO_EN," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE," newline bitfld.long 0x0 0. "IT_PENDING," "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "DIV_EN," "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1," "0,1" newline bitfld.long 0x0 3. "PARITY_EN," "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3" line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline rbitfld.long 0x4 7. "RESERVED," "0,1" newline bitfld.long 0x4 6. "TCR_TLR," "0,1" newline bitfld.long 0x4 5. "XON_EN," "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN," "0,1" newline bitfld.long 0x4 3. "CD_STS_CH," "0,1" newline bitfld.long 0x4 2. "RI_STS_CH," "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1" newline bitfld.long 0x4 0. "DTR," "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_CIR," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "RESERVED," "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_IRDA," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL," "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE," "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG," "0,1" newline bitfld.long 0x0 3. "ABORT," "0,1" newline bitfld.long 0x0 2. "CRC," "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_UART," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "RX_FIFO_STS," "0,1" newline bitfld.long 0x0 6. "TX_SR_E," "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E," "0,1" newline bitfld.long 0x0 4. "RX_BI," "0,1" newline bitfld.long 0x0 3. "RX_FE," "0,1" newline bitfld.long 0x0 2. "RX_PE," "0,1" newline bitfld.long 0x0 1. "RX_OE," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS," "0,1" newline bitfld.long 0x0 0. "CTS_STS," "0,1" rgroup.long 0x18++0x3 line.long 0x0 "MEM_TCR,Transmission Control Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" rgroup.long 0x18++0x7 line.long 0x0 "MEM_XOFF1,XOFF1 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" rgroup.long 0x1C++0x3 line.long 0x0 "MEM_TLR,Trigger Level Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" rgroup.long 0x1C++0xB line.long 0x0 "MEM_XOFF2,XOFF2 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP," "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7" line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is :" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_SFLSR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR," "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR," "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT," "0,1" newline bitfld.long 0x0 1. "CRC_ERROR," "0,1" newline bitfld.long 0x0 0. "RESERVED0," "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_TXFLL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" rgroup.long 0x2C++0x7 line.long 0x0 "MEM_TXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "MEM_RXFLL,IrDA modes only." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "MEM_SFREGL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" rgroup.long 0x34++0x3 line.long 0x0 "MEM_RXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "MEM_SFREGH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" rgroup.long 0x38++0x3 line.long 0x0 "MEM_BLR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED," rgroup.long 0x38++0x3 line.long 0x0 "MEM_UASR,UART Autobauding Status Register" bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." rgroup.long 0x3C++0xF line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX," "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "RX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 5. "DSR_IT," "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT," "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL," "0,1" line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x8 3.--7. 1. "RESERVED," newline bitfld.long 0x8 2. "DMA_COUNTER_RST," "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL," "0,1" line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED," newline hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." rgroup.long 0x54++0x3 line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "MEM_SYSS," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED," newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" rgroup.long 0x5C++0x7 line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN," "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT," "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY," "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY," "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY," "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY," "0,1" line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.." rgroup.long 0x64++0x7 line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL," line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL," rgroup.long 0x6C++0xB line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED," newline bitfld.long 0x0 2. "RHR_IT_DIS," "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED," newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1" line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED," line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED," rgroup.long 0x80++0x23 line.long 0x0 "MEM_MDR3,Mode definition register 3." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2," newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1" line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "MEM_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1," newline rbitfld.long 0x8 7. "RESERVED," "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7" line.long 0xC "MEM_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1," newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "MEM_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1," newline rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "MEM_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1," newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "MEM_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" rgroup.long 0xA4++0xF line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" line.long 0x4 "MEM_MAR,Multidrop Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "MEM_MMR,Multidrop Mask Register" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART6 (UART6)" base ad:0x2860000 rgroup.long 0x0++0x3 line.long 0x0 "MEM_DLL,Divisor Latches Low Register" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" rgroup.long 0x0++0x7 line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" line.long 0x4 "MEM_DLH,Divisor Latches High Register" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.." bitfld.long 0x0 6.--7. "NOT_USED2," "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "NOT_USED1," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x7 line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "CTS_IT," "0,1" newline bitfld.long 0x0 6. "RTS_IT," "0,1" newline bitfld.long 0x0 5. "XOFF_IT," "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE," "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT," "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" line.long 0x4 "MEM_EFR,Enhanced Feature Register" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" rgroup.long 0x8++0x3 line.long 0x0 "MEM_FCR,Notes:" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered. If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of.." "0,1,2,3" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 0. "FIFO_EN," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE," newline bitfld.long 0x0 0. "IT_PENDING," "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "DIV_EN," "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1," "0,1" newline bitfld.long 0x0 3. "PARITY_EN," "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3" line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline rbitfld.long 0x4 7. "RESERVED," "0,1" newline bitfld.long 0x4 6. "TCR_TLR," "0,1" newline bitfld.long 0x4 5. "XON_EN," "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN," "0,1" newline bitfld.long 0x4 3. "CD_STS_CH," "0,1" newline bitfld.long 0x4 2. "RI_STS_CH," "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1" newline bitfld.long 0x4 0. "DTR," "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_CIR," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "RESERVED," "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_IRDA," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL," "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE," "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG," "0,1" newline bitfld.long 0x0 3. "ABORT," "0,1" newline bitfld.long 0x0 2. "CRC," "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_UART," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "RX_FIFO_STS," "0,1" newline bitfld.long 0x0 6. "TX_SR_E," "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E," "0,1" newline bitfld.long 0x0 4. "RX_BI," "0,1" newline bitfld.long 0x0 3. "RX_FE," "0,1" newline bitfld.long 0x0 2. "RX_PE," "0,1" newline bitfld.long 0x0 1. "RX_OE," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS," "0,1" newline bitfld.long 0x0 0. "CTS_STS," "0,1" rgroup.long 0x18++0x3 line.long 0x0 "MEM_TCR,Transmission Control Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" rgroup.long 0x18++0x7 line.long 0x0 "MEM_XOFF1,XOFF1 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" rgroup.long 0x1C++0x3 line.long 0x0 "MEM_TLR,Trigger Level Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" rgroup.long 0x1C++0xB line.long 0x0 "MEM_XOFF2,XOFF2 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP," "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7" line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is :" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_SFLSR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR," "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR," "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT," "0,1" newline bitfld.long 0x0 1. "CRC_ERROR," "0,1" newline bitfld.long 0x0 0. "RESERVED0," "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_TXFLL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" rgroup.long 0x2C++0x7 line.long 0x0 "MEM_TXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "MEM_RXFLL,IrDA modes only." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "MEM_SFREGL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" rgroup.long 0x34++0x3 line.long 0x0 "MEM_RXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "MEM_SFREGH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" rgroup.long 0x38++0x3 line.long 0x0 "MEM_BLR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED," rgroup.long 0x38++0x3 line.long 0x0 "MEM_UASR,UART Autobauding Status Register" bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." rgroup.long 0x3C++0xF line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX," "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "RX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 5. "DSR_IT," "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT," "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL," "0,1" line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x8 3.--7. 1. "RESERVED," newline bitfld.long 0x8 2. "DMA_COUNTER_RST," "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL," "0,1" line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED," newline hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." rgroup.long 0x54++0x3 line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "MEM_SYSS," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED," newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" rgroup.long 0x5C++0x7 line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN," "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT," "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY," "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY," "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY," "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY," "0,1" line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.." rgroup.long 0x64++0x7 line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL," line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL," rgroup.long 0x6C++0xB line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED," newline bitfld.long 0x0 2. "RHR_IT_DIS," "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED," newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1" line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED," line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED," rgroup.long 0x80++0x23 line.long 0x0 "MEM_MDR3,Mode definition register 3." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2," newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1" line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "MEM_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1," newline rbitfld.long 0x8 7. "RESERVED," "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7" line.long 0xC "MEM_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1," newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "MEM_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1," newline rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "MEM_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1," newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "MEM_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" rgroup.long 0xA4++0xF line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" line.long 0x4 "MEM_MAR,Multidrop Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "MEM_MMR,Multidrop Mask Register" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART7 (UART7)" base ad:0x2870000 rgroup.long 0x0++0x3 line.long 0x0 "MEM_DLL,Divisor Latches Low Register" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" rgroup.long 0x0++0x7 line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" line.long 0x4 "MEM_DLH,Divisor Latches High Register" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.." bitfld.long 0x0 6.--7. "NOT_USED2," "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "NOT_USED1," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x7 line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "CTS_IT," "0,1" newline bitfld.long 0x0 6. "RTS_IT," "0,1" newline bitfld.long 0x0 5. "XOFF_IT," "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE," "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT," "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" line.long 0x4 "MEM_EFR,Enhanced Feature Register" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" rgroup.long 0x8++0x3 line.long 0x0 "MEM_FCR,Notes:" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered. If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of.." "0,1,2,3" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 0. "FIFO_EN," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE," newline bitfld.long 0x0 0. "IT_PENDING," "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "DIV_EN," "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1," "0,1" newline bitfld.long 0x0 3. "PARITY_EN," "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3" line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline rbitfld.long 0x4 7. "RESERVED," "0,1" newline bitfld.long 0x4 6. "TCR_TLR," "0,1" newline bitfld.long 0x4 5. "XON_EN," "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN," "0,1" newline bitfld.long 0x4 3. "CD_STS_CH," "0,1" newline bitfld.long 0x4 2. "RI_STS_CH," "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1" newline bitfld.long 0x4 0. "DTR," "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_CIR," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "RESERVED," "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_IRDA," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL," "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE," "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG," "0,1" newline bitfld.long 0x0 3. "ABORT," "0,1" newline bitfld.long 0x0 2. "CRC," "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_UART," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "RX_FIFO_STS," "0,1" newline bitfld.long 0x0 6. "TX_SR_E," "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E," "0,1" newline bitfld.long 0x0 4. "RX_BI," "0,1" newline bitfld.long 0x0 3. "RX_FE," "0,1" newline bitfld.long 0x0 2. "RX_PE," "0,1" newline bitfld.long 0x0 1. "RX_OE," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS," "0,1" newline bitfld.long 0x0 0. "CTS_STS," "0,1" rgroup.long 0x18++0x3 line.long 0x0 "MEM_TCR,Transmission Control Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" rgroup.long 0x18++0x7 line.long 0x0 "MEM_XOFF1,XOFF1 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" rgroup.long 0x1C++0x3 line.long 0x0 "MEM_TLR,Trigger Level Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" rgroup.long 0x1C++0xB line.long 0x0 "MEM_XOFF2,XOFF2 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP," "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7" line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is :" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_SFLSR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR," "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR," "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT," "0,1" newline bitfld.long 0x0 1. "CRC_ERROR," "0,1" newline bitfld.long 0x0 0. "RESERVED0," "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_TXFLL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" rgroup.long 0x2C++0x7 line.long 0x0 "MEM_TXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "MEM_RXFLL,IrDA modes only." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "MEM_SFREGL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" rgroup.long 0x34++0x3 line.long 0x0 "MEM_RXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "MEM_SFREGH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" rgroup.long 0x38++0x3 line.long 0x0 "MEM_BLR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED," rgroup.long 0x38++0x3 line.long 0x0 "MEM_UASR,UART Autobauding Status Register" bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." rgroup.long 0x3C++0xF line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX," "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "RX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 5. "DSR_IT," "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT," "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL," "0,1" line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x8 3.--7. 1. "RESERVED," newline bitfld.long 0x8 2. "DMA_COUNTER_RST," "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL," "0,1" line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED," newline hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." rgroup.long 0x54++0x3 line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "MEM_SYSS," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED," newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" rgroup.long 0x5C++0x7 line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN," "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT," "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY," "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY," "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY," "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY," "0,1" line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.." rgroup.long 0x64++0x7 line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL," line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL," rgroup.long 0x6C++0xB line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED," newline bitfld.long 0x0 2. "RHR_IT_DIS," "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED," newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1" line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED," line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED," rgroup.long 0x80++0x23 line.long 0x0 "MEM_MDR3,Mode definition register 3." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2," newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1" line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "MEM_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1," newline rbitfld.long 0x8 7. "RESERVED," "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7" line.long 0xC "MEM_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1," newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "MEM_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1," newline rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "MEM_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1," newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "MEM_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" rgroup.long 0xA4++0xF line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" line.long 0x4 "MEM_MAR,Multidrop Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "MEM_MMR,Multidrop Mask Register" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART8 (UART8)" base ad:0x2880000 rgroup.long 0x0++0x3 line.long 0x0 "MEM_DLL,Divisor Latches Low Register" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" rgroup.long 0x0++0x7 line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" line.long 0x4 "MEM_DLH,Divisor Latches High Register" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.." bitfld.long 0x0 6.--7. "NOT_USED2," "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "NOT_USED1," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x7 line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "CTS_IT," "0,1" newline bitfld.long 0x0 6. "RTS_IT," "0,1" newline bitfld.long 0x0 5. "XOFF_IT," "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE," "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT," "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" line.long 0x4 "MEM_EFR,Enhanced Feature Register" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" rgroup.long 0x8++0x3 line.long 0x0 "MEM_FCR,Notes:" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered. If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of.." "0,1,2,3" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 0. "FIFO_EN," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE," newline bitfld.long 0x0 0. "IT_PENDING," "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "DIV_EN," "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1," "0,1" newline bitfld.long 0x0 3. "PARITY_EN," "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3" line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline rbitfld.long 0x4 7. "RESERVED," "0,1" newline bitfld.long 0x4 6. "TCR_TLR," "0,1" newline bitfld.long 0x4 5. "XON_EN," "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN," "0,1" newline bitfld.long 0x4 3. "CD_STS_CH," "0,1" newline bitfld.long 0x4 2. "RI_STS_CH," "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1" newline bitfld.long 0x4 0. "DTR," "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_CIR," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "RESERVED," "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_IRDA," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL," "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE," "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG," "0,1" newline bitfld.long 0x0 3. "ABORT," "0,1" newline bitfld.long 0x0 2. "CRC," "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_UART," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "RX_FIFO_STS," "0,1" newline bitfld.long 0x0 6. "TX_SR_E," "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E," "0,1" newline bitfld.long 0x0 4. "RX_BI," "0,1" newline bitfld.long 0x0 3. "RX_FE," "0,1" newline bitfld.long 0x0 2. "RX_PE," "0,1" newline bitfld.long 0x0 1. "RX_OE," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS," "0,1" newline bitfld.long 0x0 0. "CTS_STS," "0,1" rgroup.long 0x18++0x3 line.long 0x0 "MEM_TCR,Transmission Control Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" rgroup.long 0x18++0x7 line.long 0x0 "MEM_XOFF1,XOFF1 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" rgroup.long 0x1C++0x3 line.long 0x0 "MEM_TLR,Trigger Level Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" rgroup.long 0x1C++0xB line.long 0x0 "MEM_XOFF2,XOFF2 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP," "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7" line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is :" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_SFLSR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR," "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR," "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT," "0,1" newline bitfld.long 0x0 1. "CRC_ERROR," "0,1" newline bitfld.long 0x0 0. "RESERVED0," "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_TXFLL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" rgroup.long 0x2C++0x7 line.long 0x0 "MEM_TXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "MEM_RXFLL,IrDA modes only." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "MEM_SFREGL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" rgroup.long 0x34++0x3 line.long 0x0 "MEM_RXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "MEM_SFREGH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" rgroup.long 0x38++0x3 line.long 0x0 "MEM_BLR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED," rgroup.long 0x38++0x3 line.long 0x0 "MEM_UASR,UART Autobauding Status Register" bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." rgroup.long 0x3C++0xF line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX," "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "RX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 5. "DSR_IT," "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT," "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL," "0,1" line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x8 3.--7. 1. "RESERVED," newline bitfld.long 0x8 2. "DMA_COUNTER_RST," "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL," "0,1" line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED," newline hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." rgroup.long 0x54++0x3 line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "MEM_SYSS," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED," newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" rgroup.long 0x5C++0x7 line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN," "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT," "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY," "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY," "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY," "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY," "0,1" line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.." rgroup.long 0x64++0x7 line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL," line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL," rgroup.long 0x6C++0xB line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED," newline bitfld.long 0x0 2. "RHR_IT_DIS," "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED," newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1" line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED," line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED," rgroup.long 0x80++0x23 line.long 0x0 "MEM_MDR3,Mode definition register 3." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2," newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1" line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "MEM_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1," newline rbitfld.long 0x8 7. "RESERVED," "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7" line.long 0xC "MEM_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1," newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "MEM_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1," newline rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "MEM_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1," newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "MEM_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" rgroup.long 0xA4++0xF line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" line.long 0x4 "MEM_MAR,Multidrop Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "MEM_MMR,Multidrop Mask Register" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART9 (UART9)" base ad:0x2890000 rgroup.long 0x0++0x3 line.long 0x0 "MEM_DLL,Divisor Latches Low Register" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" rgroup.long 0x0++0x7 line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" line.long 0x4 "MEM_DLH,Divisor Latches High Register" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.." bitfld.long 0x0 6.--7. "NOT_USED2," "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "NOT_USED1," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x7 line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "CTS_IT," "0,1" newline bitfld.long 0x0 6. "RTS_IT," "0,1" newline bitfld.long 0x0 5. "XOFF_IT," "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE," "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT," "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" line.long 0x4 "MEM_EFR,Enhanced Feature Register" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" rgroup.long 0x8++0x3 line.long 0x0 "MEM_FCR,Notes:" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered. If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of.." "0,1,2,3" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 0. "FIFO_EN," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE," newline bitfld.long 0x0 0. "IT_PENDING," "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "DIV_EN," "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1," "0,1" newline bitfld.long 0x0 3. "PARITY_EN," "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3" line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline rbitfld.long 0x4 7. "RESERVED," "0,1" newline bitfld.long 0x4 6. "TCR_TLR," "0,1" newline bitfld.long 0x4 5. "XON_EN," "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN," "0,1" newline bitfld.long 0x4 3. "CD_STS_CH," "0,1" newline bitfld.long 0x4 2. "RI_STS_CH," "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1" newline bitfld.long 0x4 0. "DTR," "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_CIR," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "RESERVED," "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_IRDA," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL," "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE," "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG," "0,1" newline bitfld.long 0x0 3. "ABORT," "0,1" newline bitfld.long 0x0 2. "CRC," "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_UART," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "RX_FIFO_STS," "0,1" newline bitfld.long 0x0 6. "TX_SR_E," "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E," "0,1" newline bitfld.long 0x0 4. "RX_BI," "0,1" newline bitfld.long 0x0 3. "RX_FE," "0,1" newline bitfld.long 0x0 2. "RX_PE," "0,1" newline bitfld.long 0x0 1. "RX_OE," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS," "0,1" newline bitfld.long 0x0 0. "CTS_STS," "0,1" rgroup.long 0x18++0x3 line.long 0x0 "MEM_TCR,Transmission Control Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" rgroup.long 0x18++0x7 line.long 0x0 "MEM_XOFF1,XOFF1 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" rgroup.long 0x1C++0x3 line.long 0x0 "MEM_TLR,Trigger Level Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" rgroup.long 0x1C++0xB line.long 0x0 "MEM_XOFF2,XOFF2 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP," "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7" line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is :" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_SFLSR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR," "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR," "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT," "0,1" newline bitfld.long 0x0 1. "CRC_ERROR," "0,1" newline bitfld.long 0x0 0. "RESERVED0," "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_TXFLL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" rgroup.long 0x2C++0x7 line.long 0x0 "MEM_TXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "MEM_RXFLL,IrDA modes only." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "MEM_SFREGL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" rgroup.long 0x34++0x3 line.long 0x0 "MEM_RXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "MEM_SFREGH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" rgroup.long 0x38++0x3 line.long 0x0 "MEM_BLR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED," rgroup.long 0x38++0x3 line.long 0x0 "MEM_UASR,UART Autobauding Status Register" bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." rgroup.long 0x3C++0xF line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX," "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "RX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 5. "DSR_IT," "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT," "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL," "0,1" line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x8 3.--7. 1. "RESERVED," newline bitfld.long 0x8 2. "DMA_COUNTER_RST," "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL," "0,1" line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED," newline hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." rgroup.long 0x54++0x3 line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "MEM_SYSS," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED," newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" rgroup.long 0x5C++0x7 line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN," "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT," "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY," "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY," "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY," "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY," "0,1" line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.." rgroup.long 0x64++0x7 line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL," line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL," rgroup.long 0x6C++0xB line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED," newline bitfld.long 0x0 2. "RHR_IT_DIS," "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED," newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1" line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED," line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED," rgroup.long 0x80++0x23 line.long 0x0 "MEM_MDR3,Mode definition register 3." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2," newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1" line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "MEM_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1," newline rbitfld.long 0x8 7. "RESERVED," "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7" line.long 0xC "MEM_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1," newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "MEM_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1," newline rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "MEM_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1," newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "MEM_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" rgroup.long 0xA4++0xF line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" line.long 0x4 "MEM_MAR,Multidrop Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "MEM_MMR,Multidrop Mask Register" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree.end tree "USB0" base ad:0x0 tree "USB0_ECC_AGGR (USB0_ECC_AGGR)" base ad:0x2A13000 rgroup.long 0x0++0x3 line.long 0x0 "A_ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "A_ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "A_ECC_AGGR__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "A_ECC_AGGR__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "A_ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "A_ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "RAMECC_PEND,Interrupt Pending Status for ramecc_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "A_ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "RAMECC_ENABLE_SET,Interrupt Enable Set Register for ramecc_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "A_ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "A_ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "A_ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "RAMECC_PEND,Interrupt Pending Status for ramecc_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "A_ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "RAMECC_ENABLE_SET,Interrupt Enable Set Register for ramecc_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "A_ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "A_ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "A_ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "A_ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "A_ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "USB0_MMR_MMRVBP_USBSS_CMN (USB0_MMR_MMRVBP_USBSS_CMN)" base ad:0x4104000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__USBSS_CMN_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0xF line.long 0x0 "MMR__MMRVBP__USBSS_CMN_USB3P0SS_W1,Wrapper register containing soft reset. mode selection. and overcurrent indicator." hexmask.long.word 0x0 20.--31. 1. "RSVD3,Reserved bits set 3" newline bitfld.long 0x0 19. "USB2_ONLY_MODE,Selects USB2 only mode. Has to be written before setting pwrup_rst_n bit. This bit has to be set when SERDES is not assigned to this USB instance. For example when the Wiz is configured to allocate the serdes lanes for another function .." "0,1" newline bitfld.long 0x0 17.--18. "MODESTRAP,Modestrap input to the Controller. Has to be written before setting pwrup_rst_n bit. 00 - Controller not configured as Host or Device 01 - Controller is initially configured as Host 10 - Controller is initially configured as Device. Please.." "0: Controller not configured as Host or Device,1: Controller is initially configured as Host,?,?" newline bitfld.long 0x0 16. "OVERCURRENT_N,Overcurrent indicator to the Controller" "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "RSVD2,Reserved bits set 2" newline bitfld.long 0x0 9. "MODESTRAP_SEL,Select signal. Has to be written before setting pwrup_rst_n bit. 1 - modestrap MMR bits are used 0 - usb_mode_strap input is used" "0: usb_mode_strap input is used,1: modestrap MMR bits are used" newline bitfld.long 0x0 8. "OVERCURRENT_SEL,Overcurrent MMR select. Has to be written before setting pwrup_rst_n bit. 1 - overcurrent MMR bit is used 0 - port_overcurrent_n input is used" "0: port_overcurrent_n input is used,1: overcurrent MMR bit is used" newline hexmask.long.byte 0x0 1.--7. 1. "RSVD1,Reserved bits set 1" newline bitfld.long 0x0 0. "PWRUP_RST_N,Power up reset for the Controller. Set this bit after initialization steps like modestrap configuration extended capability register configuration etc." "0,1" line.long 0x4 "MMR__MMRVBP__USBSS_CMN_STATIC_CONFIG,Wrapper register containing static settings. All bits in this register have to be written before setting pwrup_rst_n bit in USB3P0SS_W1 register. All bits in this register directly drive the USB2 PHY inputs. Please.." hexmask.long.tbyte 0x4 9.--31. 1. "RSVD,Reserved bits" newline hexmask.long.byte 0x4 5.--8. 1. "PLL_REF_SEL,This register directly drives the pllrefsel[3:0] input to USB2 PHY. Indicates the frequency of the REF_CLOCK input used by the USB PLL. This value should match the frequency value of either the HFOSC0 or HFOSC1 oscillator as selected by the.." newline bitfld.long 0x4 3.--4. "LOOPBACK_MODE,This register directly drives the loopback[1:0] input to USB2 PHY. Loopback mode selection - 00: Loopback OFF 01: LS Loopback ON 10: FS Loopback ON 11: HS Loopback ON." "0: Loopback OFF,1: LS Loopback ON,?,?" newline bitfld.long 0x4 1.--2. "VBUS_SEL,This register directly drives the vbus_sel[1:0] input to the PHY. VBUS select - 00: VBUS = 5.25V/3.3V 01: VBUS/3 external divider is active so VBUS could be upto 11V." "0: VBUS = 5,1: VBUS/3 external divider is active,?,?" newline bitfld.long 0x4 0. "LANE_REVERSE,This register directly drives the lane_reverse input to USB2 PHY. Lane reverse selection. When set this bit indicates that D+ and D- lines have to be swapped." "0,1" line.long 0x8 "MMR__MMRVBP__USBSS_CMN_PHY_TEST,Register containing PLL bypass select. BIST control and status" hexmask.long.word 0x8 18.--31. 1. "RSVD,Reserved bits" newline bitfld.long 0x8 17. "BIST_MODE,Set for bist mode. This is used for overriding PHY ports for BIST." "0,1" newline hexmask.long.byte 0x8 9.--16. 1. "BIST_ERROR_COUNT,Number of bytes that have errors while running BIST. The count resets when bist_on is set." newline rbitfld.long 0x8 8. "BIST_ERROR,If set this bit indicates that BIST completed with error." "0,1" newline rbitfld.long 0x8 7. "BIST_COMPLETE,If set this bit indicates that the BIST operation is completed." "0,1" newline bitfld.long 0x8 6. "BIST_ON,Setting this bit starts the BIST operation." "0,1" newline bitfld.long 0x8 5. "BIST_MODE_EN,BIST Mode Enable. 0 = BIST not enabled 1 = BIST enabled" "0: BIST not enabled,1: BIST enabled" newline hexmask.long.byte 0x8 1.--4. 1. "BIST_MODE_SEL,BIST Mode Selection. bist_mode_sel[3]: 0 = 8-bit interface 1 = 16-bit interface; bist_mode_sel[2]: 0 = error injection disabled 1 = error injection enabled; bist_mode_sel[1]: 0 = device mode 1 = host mode; bist_mode_sel[0]: 0 = High.." newline bitfld.long 0x8 0. "PLL_BYPASS_MODE,Setting this bit disables the PLL clock and bypasses it with PLL reference clock." "0,1" line.long 0xC "MMR__MMRVBP__USBSS_CMN_USB3P0SS_DEBUG_CTRL,USB Controller debug selection register" hexmask.long 0xC 5.--31. 1. "RSVD,Reserved bits" newline hexmask.long.byte 0xC 0.--4. 1. "DEBUG_SEL,Debug selection" rgroup.long 0x14++0x7 line.long 0x0 "MMR__MMRVBP__USBSS_CMN_USB3P0SS_DEBUG_INFO,USB Controller debug information register" hexmask.long 0x0 0.--31. 1. "DEBUG_INFO,Debug information selected by debug_sel" line.long 0x4 "MMR__MMRVBP__USBSS_CMN_USB3P0SS_DEBUG_LINK_STATE,USB Controller debug link state information" bitfld.long 0x4 31. "RSVD,Reserved bits" "0,1" newline hexmask.long 0x4 0.--30. 1. "DEBUG_LINK_STATE,Debug link state information" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__USBSS_CMN_USB3P0SS_DEVICE_CTRL,Register for device control" hexmask.long 0x0 1.--31. 1. "RSVD,Reserved bits" newline bitfld.long 0x0 0. "DEV_WAKEUP,Set this bit to trigger device wakeup interrupt on irq_intr[7]" "0,1" tree.end tree "USB0_PHY2 (USB0_PHY2)" base ad:0x4108000 rgroup.long 0x0++0x4F line.long 0x0 "PHY2_AFE_TX_REG0,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x0 7. "TX_ANA_REG0,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0x0 2.--6. 1. "BF_6_2,This is a reserved register or field. It should not be written or read and the value should be ignored." newline bitfld.long 0x0 1. "BF_1,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x0 0. "BF_0,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x4 "PHY2_AFE_TX_REG1,HS TX trimming" bitfld.long 0x4 7. "TX_ANA_REG1,0 SCALE1 VALUE IS 0 1 SCALE1 VALUE IS 0.5" "0,1" newline hexmask.long.byte 0x4 1.--6. 1. "BF_6_1,000000 BOOST CODE VALUE IS 0 000001 BOOST CODE VALUE IS 1 000010 BOOST CODE VALUE IS 2 00011 BOOST CODE VALUE IS 3 000100 BOOST CODE VALUE IS 4 000101 BOOST CODE VALUE IS 5 000110 BOOST CODE VALUE IS 6 000111 BOOST CODE VALUE IS 7 001000.." newline bitfld.long 0x4 0. "BF_0,0 Default BOOST CODE = 8 1 BOOST CODE can be controlled by BITS [6:1]." "0,1" line.long 0x8 "PHY2_AFE_TX_REG2,HS TX trimming" bitfld.long 0x8 7. "TX_ANA_REG2,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 6. "BF_6,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0x8 1.--5. 1. "BF_5_1,00000 DEEMP CODE VALUE IS 0 00001 DEEMP CODE VALUE IS 1 00010 DEEMP CODE VALUE IS 2 00011 DEEMP CODE VALUE IS 3 00100 DEEMP CODE VALUE IS 4 00101 DEEMP CODE VALUE IS 5 00110 DEEMP CODE VALUE IS 6 00111 DEEMP CODE VALUE IS 7 01000 DEEMP.." newline bitfld.long 0x8 0. "BF_0,0 Default DEEMP CODE = 8 1 DEEMP CODE can be controlled by BITS 5:1." "0,1" line.long 0xC "PHY2_AFE_TX_REG3,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0xC 5.--7. "TX_ANA_REG3,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 1.--4. 1. "BF_4_1,This is a reserved register or field. It should not be written or read and the value should be ignored." newline bitfld.long 0xC 0. "BF_0,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x10 "PHY2_AFE_TX_REG4,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x10 7. "TX_ANA_REG4,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 6. "BF_6,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 5. "BF_5,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0x10 1.--4. 1. "BF_4_1,This is a reserved register or field. It should not be written or read and the value should be ignored." newline bitfld.long 0x10 0. "BF_0,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x14 "PHY2_AFE_TX_REG5,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x14 7. "AFE_TX_REG5,UNUSED" "0,1" newline hexmask.long.byte 0x14 1.--6. 1. "BF_6_1,This is a reserved register or field. It should not be written or read and the value should be ignored." newline bitfld.long 0x14 0. "BF_0,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x18 "PHY2_AFE_TX_REG6,LSTX rise time trimming" hexmask.long.byte 0x18 0.--7. 1. "TX_ANA_REG6,Bit 7 = unused. Bbits 6:3= 0000 Typical LSTx rise time = 375ns 0001 Typical LSTx rise time =215ns 0010 Typical LSTx rise time =215ns 0011 Typical LSTx rise time =150ns 0100 Typical LSTx rise time =215ns 0101 Typical LSTx rise time.." line.long 0x1C "PHY2_AFE_TX_REG7,FSTX rise time trimming" hexmask.long.byte 0x1C 0.--7. 1. "TX_ANA_REG7,Bits 7:5= reserved. Bits 4:1= 0000 Typical FSTx rise time = 16.6ns 0001 Typical FSTx rise time =16.1ns 0010 Typical FSTx rise time =15.6ns 0011 Typical FSTx rise time =15.2ns 0100 Typical FSTx rise time =14.7ns 0101 Typical FSTx rise.." line.long 0x20 "PHY2_AFE_TX_REG8,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x20 0.--7. 1. "TX_ANA_REG8,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x24 "PHY2_AFE_TX_REG9,Register AFE_TX_REG9" hexmask.long.byte 0x24 0.--7. 1. "TX_ANA_REG9,Bits 7:4= 0000 Typical LSTx fall time = 450ns 0001 Typical LSTx fall time = 225ns 0010 Typical LSTx fall time =150ns 0011 Typical LSTx fall time =225ns 0100 Typical LSTx fall time =150ns 0101 Typical LSTx fall time =150ns 0110 Typical.." line.long 0x28 "PHY2_AFE_TX_REG10,FSTX fall time trimming" hexmask.long.byte 0x28 0.--7. 1. "TX_ANA_REG10,Bits 7:5= reserved. Bits 4:1= 0000 Typical FSTx fall time = 16.6ns 0001 Typical FSTx fall time =16.1ns 0010 Typical FSTx fall time =15.6ns 0011 Typical FSTx fall time =15.2ns 0100 Typical FSTx fall time =14.7ns 0101 Typical FSTx fall.." line.long 0x2C "PHY2_AFE_TX_REG11,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x2C 0.--7. 1. "TX_ANA_REG11,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x30 "PHY2_AFE_TX_REG12,Register AFE_TX_REG12" bitfld.long 0x30 7. "TX_ANA_REG12,unused" "0,1" newline bitfld.long 0x30 6. "BF_6,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x30 5. "BF_5,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x30 4. "BF_4,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x30 3. "BF_3,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x30 2. "BF_2,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x30 0.--1. "BF_1_0,00- SCALE2 set to 0 01- SCALE2 set to 1 10- SCALE2 set to 1 11- SCALE2 set to 2" "0: SCALE2 set to 0,1: SCALE2 set to 1,?,?" line.long 0x34 "PHY2_AFE_RX_REG0,Trim the squelch threshold" hexmask.long.byte 0x34 0.--7. 1. "RX_ANA_REG0,Bits 7:6= reserved. Bits 5:0= 000000 keep squelch threshold at default value 100000 increade squelch threshold by 5mv 110000 increade squelch threshold by 10mv 111000 increade squelch threshold by 15mv 000001 reduce squelch threshold by.." line.long 0x38 "PHY2_AFE_RX_REG1,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x38 0.--7. 1. "RX_ANA_REG1,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x3C "PHY2_AFE_RX_REG2,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x3C 0.--7. 1. "RX_ANA_REG2,reerved" line.long 0x40 "PHY2_AFE_RX_REG3,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x40 0.--7. 1. "RX_ANA_REG3,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x44 "PHY2_AFE_RX_REG4,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x44 0.--7. 1. "RX_ANA_REG4,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x48 "PHY2_AFE_RX_REG5,Single ended receivers threshold trimming" hexmask.long.byte 0x48 0.--7. 1. "RX_ANA_REG5,Bits 7:3= reserved. Bits 2:1= 01 Switching thresholds for single ended receivers increased by 100mV 10 Switching thresholds for single ended receivers reduced by 100mV. Bit 0= 0 Default Switching Thresholds for Single ended receivers 1 SERx.." line.long 0x4C "PHY2_AFE_RX_REG6,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x4C 0.--7. 1. "RX_ANA_REG6,This is a reserved register or field. It should not be written or read and the value should be ignored." rgroup.long 0x50++0xF line.long 0x0 "PHY2_AFE_TX_REG13,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x0 0.--7. 1. "TX_ANA_REG13,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x4 "PHY2_AFE_TX_REG14,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x4 0.--7. 1. "TX_ANA_REG14,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x8 "PHY2_AFE_RX_REG7,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x8 0.--7. 1. "RX_ANA_REG7,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0xC "PHY2_AFE_RX_REG8,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0xC 0.--7. 1. "RX_ANA_REG8,This is a reserved register or field. It should not be written or read and the value should be ignored." rgroup.long 0x60++0x7 line.long 0x0 "PHY2_AFE_UNUSED_REG0,AFE_UNUSED_REG0" hexmask.long.byte 0x0 0.--7. 1. "AFE_UNUSED_REG0,unused" line.long 0x4 "PHY2_AFE_UNUSED_REG1,AFE_UNUSED_REG1" hexmask.long.byte 0x4 0.--7. 1. "AFE_UNUSED_REG1,unused" rgroup.long 0x80++0x47 line.long 0x0 "PHY2_AFE_BG_REG0,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x0 0.--7. 1. "BG_ANA_REG0,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x4 "PHY2_AFE_BG_REG1,BG bias current trimming" hexmask.long.byte 0x4 0.--7. 1. "BG_ANA_REG1,Bits 7:6= 00- PLL charge pump bias current 5uA 01- PLL charge pump bias current 4uA 10- PLL charge pump bias current 6uA 11- PLL charge pump bias current 5uA. Bits 5:4= 00- PLL DAC bias bias current bias current 5uA 01- PLL DAC bias bias.." line.long 0x8 "PHY2_AFE_BG_REG2,BG bias current trimming" hexmask.long.byte 0x8 0.--7. 1. "BG_ANA_REG2,Bits 7:5= 000 High speed receiver bias 5uA 100 High speed receiver bias 1uA 001 High speed receiver bias 4uA 010 High speed receiver bias 6uA 101 High speed receiver bias 2uA. Bits 4:2= 000 Trasmission Envelope Detector bias current 5uA .." line.long 0xC "PHY2_AFE_BG_REG3,Register AFE_BG_REG3" hexmask.long.byte 0xC 0.--7. 1. "BG_ANA_REG3,Bits 7:6= reserved Bits 5:4= 00 [Default] BG_OK_CORE Generated Internally 01 BG_OK_CORE Generated Internally 10 Force BG_OK_CORE =0 11 Force BG_OK_CORE =1. Bits 3:0=0000 Invalid state 0001 Higher start sense voltage weaker start-up pull.." line.long 0x10 "PHY2_AFE_CALIB_REG0,Calibration resistance trimming" hexmask.long.byte 0x10 0.--7. 1. "CALIB_ANA_REG0,Bits 5:0= 000000 Calibrate termination resistor to default value 000001 Calibrate termination resistor by -5% to default value 000011 Calibrate termination resistor by -10% to default value 000111 Calibrate termination resistor by - 15%.." line.long 0x14 "PHY2_AFE_BC_REG0,register AFE_BC_REG0" hexmask.long.byte 0x14 0.--7. 1. "BC_ANA_REG0,Bit 0= 0 Battery_charging_DAC_RES_CALIB CODE CANNOT BE CONTROLLED BY ANALOG TEST BITS 1 Battery_charging_DAC_RES_CALIB CODE CAN BE CONTROLLED BY ANALOG TEST BITS. Bits 5:1= 00000 Battery_charging_DAC_RES_CALIB CODE FORCED TO 0 00001.." line.long 0x18 "PHY2_AFE_BC_REG1,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x18 0.--7. 1. "BC_ANA_REG1,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x1C "PHY2_AFE_BC_REG2,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x1C 0.--7. 1. "BC_ANA_REG2,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x20 "PHY2_AFE_BC_REG3,Register AFE_BC_REG3" hexmask.long.byte 0x20 0.--7. 1. "BC_ANA_REG3,Bit 0= 0 Do not overdrive SESS_VLD comparator enable signal 1 Overdrive SESS_VLD comparator enable signal. Bit 1= 0 SESS_VLD comparator disabled 1 SESS_VLD comparator enabled. Bit 2= 0 Do not overdrive VBUS_VLD comparator enable signal 1.." line.long 0x24 "PHY2_AFE_BC_REG4,Register AFE_BC_REG4" hexmask.long.byte 0x24 0.--7. 1. "BC_ANA_REG4,Bits 2:0= reserved. Bit 3= 0- VBUS_VLD comparator output low 1- VBUS_VLD comparator output high. Bit 4= 0- Do not overdrive VBUS_VLD comparator output 1- Overdrive VBUS_VLD comparator output. Bit 5= 0- SESS_VLD comparator output low 1-.." line.long 0x28 "PHY2_AFE_BC_REG5,Register AFE_BC_REG5" hexmask.long.byte 0x28 0.--7. 1. "BC_ANA_REG5,Bit 0= 0- Do not overdrive ID comparator output 1- Overdrive ID comparator output. Bit 1= 0 Do not overdrive VBUS_DIV signal 1- Overdrive VBUS_DIV signal. Bit 2= 0- VBUS_DIV signal low 1- VBUS_DIV signal high. Bits 7:3= reserved." line.long 0x2C "PHY2_AFE_BC_REG6,Register AFE_BC_REG6" hexmask.long.byte 0x2C 0.--7. 1. "BC_ANA_REG6,register AFE_BC_REG6" line.long 0x30 "PHY2_AFE_PLL_REG0,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x30 0.--7. 1. "AFE_PLL_REG0,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x34 "PHY2_AFE_PLL_REG1,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x34 0.--7. 1. "AFE_PLL_REG1,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x38 "PHY2_AFE_PLL_REG2,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x38 0.--7. 1. "AFE_PLL_REG2,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x3C "PHY2_AFE_PLL_REG3,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x3C 0.--7. 1. "AFE_PLL_REG3,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x40 "PHY2_AFE_PLL_REG4,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x40 0.--7. 1. "AFE_PLL_REG4,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x44 "PHY2_AFE_PLL_REG5,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x44 0.--7. 1. "AFE_PLL_REG5,This is a reserved register or field. It should not be written or read and the value should be ignored." rgroup.long 0xC8++0xF line.long 0x0 "PHY2_AFE_BG_REG4,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x0 0.--7. 1. "BG_ANA_REG4,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x4 "PHY2_AFE_CALIB_REG1,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x4 0.--7. 1. "CALIB_ANA_REG1,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x8 "PHY2_AFE_BC_REG7,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x8 0.--7. 1. "BC_ANA_REG7,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0xC "PHY2_AFE_PLL_REG6,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0xC 0.--7. 1. "PLL_ANA_REG6,This is a reserved register or field. It should not be written or read and the value should be ignored." rgroup.long 0xD8++0x7 line.long 0x0 "PHY2_AFE_UNUSED_REG2,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x0 0.--7. 1. "UNUSED,unused" line.long 0x4 "PHY2_AFE_UNUSED_REG3,AFE_UNUSED_REG3" hexmask.long.byte 0x4 0.--7. 1. "UNUSED,unused" rgroup.long 0x100++0x43 line.long 0x0 "PHY2_PLL_REG0,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x0 0.--7. 1. "INITIAL_WAIT_TIME,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x4 "PHY2_PLL_REG1,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x4 3.--7. 1. "RST_FDBK_DIV_DELAY_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." newline bitfld.long 0x4 2. "RST_FDBK_DIV_DELAY_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x4 1. "FBDIV_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x4 0. "INITIAL_WAIT_TIME_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x8 "PHY2_PLL_REG2,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x8 7. "UNUSED,UNUSED" "0,1" newline bitfld.long 0x8 6. "VCO_SETTLING_TIME_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0x8 0.--5. 1. "VCO_SETTLING_TIME,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0xC "PHY2_PLL_REG3,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0xC 0.--7. 1. "FBDIV_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x10 "PHY2_PLL_REG4,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x10 7. "UNUSED,UNUSED" "0,1" newline bitfld.long 0x10 6. "PLL_LOCK_TIME_15,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 5. "PD_PFD_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 4. "PD_PFD_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 3. "PLL_LOCK_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 2. "PLL_LOCK_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 1. "COARSEDONE_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 0. "COARSEDONE_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x14 "PHY2_PLL_REG5,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x14 7. "STARTLOOP_EN_4_0,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 6. "STARTLOOP_EN_5,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 5. "STARTLOOP_5,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0x14 0.--4. 1. "STARTLOOP_4_0,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x18 "PHY2_PLL_REG6,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x18 7. "UNUSED,unused" "0,1" newline bitfld.long 0x18 6. "COARSE_CODE_SEL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 5. "LSB_ERROR_0P5,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 4. "BIG_JUMP_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 3. "VCO_CNT_WINDOW_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 2. "VCO_CNT_WINDOW_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 1. "RST_FDBK_DIV_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 0. "RST_FDBK_DIV_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x1C "PHY2_PLL_REG7,refclock selection" bitfld.long 0x1C 5.--7. "UNUSED,unused" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 1.--4. 1. "REFCLK_SEL,0000 Refclock selection for 9.6 MHz 0001 Refclock selection for 10 MHz 0010 Refclock selection for 12 MHz 0011 Refclock selection for 19.2 MHz 0100 Refclock selection for 20 MHz 0101 Refclock selection for 24 MHz 0110 Refclock selection.." newline bitfld.long 0x1C 0. "REFCLK_SEL_EN,0 PLLREFSEL Value not taken from PLL_REG7[4:1] 1 PLLREFSEL Value taken from PLL_REG7[4:1]." "0,1" line.long 0x20 "PHY2_PLL_REG8,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x20 0.--7. 1. "COARSE_CODE,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x24 "PHY2_PLL_REG9,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x24 7. "COARSE_CODE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x24 6. "V2I_CODE_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0x24 0.--5. 1. "V2I_CODE,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x28 "PHY2_PLL_REG10,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x28 7. "UNUSED,unused" "0,1" newline hexmask.long.byte 0x28 2.--6. 1. "IPDIV_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." newline bitfld.long 0x28 1. "IPDIV_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x28 0. "COARSE_CODE_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x2C "PHY2_PLL_REG11,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x2C 7. "PLL_STANDBY,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x2C 6. "PLL_STANDBY_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x2C 5. "PLL_PD,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x2C 4. "PLL_PD_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x2C 3. "PLL_PSO_DEL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x2C 2. "PLL_PSO_DEL_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x2C 1. "PLL_PSO,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x2C 0. "PLL_PSO_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x30 "PHY2_PLL_REG12,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x30 6.--7. "UNUSED,unused" "0,1,2,3" newline bitfld.long 0x30 5. "PLL_LDO_REF_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x30 4. "PLL_LDO_REF_EN_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x30 3. "PLL_LDO_CORE_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x30 2. "PLL_LDO_CORE_EN_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x30 1. "PLL_PD_ANA,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x30 0. "PLL_PD_ANA_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x34 "PHY2_PLL_REG13,PLL clockon test mode" bitfld.long 0x34 7. "PLL_CLKON,0 pll clock is not always running 1 pll clock is always running." "0,1" newline hexmask.long.byte 0x34 1.--6. 1. "PLL_LDO_REF_CORE,This is a reserved register or field. It should not be written or read and the value should be ignored." newline bitfld.long 0x34 0. "PLL_LDO_REF_CORE_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x38 "PHY2_PLL_REG14,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x38 5.--7. "PLL_LDO_CNT_THRESHOLD,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 4. "PLL_LDO_CNT_THRESHOLD_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x38 1.--3. "PLL_LDO_ISO_CNT_THRESHOLD,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 0. "PLL_LDO_ISO_CNT_THRESHOLD_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x3C "PHY2_PLL_UNUSED_REG0,unused" hexmask.long.byte 0x3C 0.--7. 1. "UNUSED,UNUSED" line.long 0x40 "PHY2_PLL_UNUSED_REG1,unused" hexmask.long.byte 0x40 0.--7. 1. "UNUSED,UNUSED" rgroup.long 0x144++0xB line.long 0x0 "PHY2_PLL_REG15,Coarse_code values" bitfld.long 0x0 7. "PLL_LOCK,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x0 6. "COARSEDONE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x0 5. "VCO_CNT_WIN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x0 4. "RST_FDBK_DIV,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x0 3. "UNUSED,UNUSED" "0,1" newline bitfld.long 0x0 2. "PD_PFD,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x0 1. "STARTLOOP,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x0 0. "COARSE_CODE_8,0 MSB of coarse_code for PLL VCO." "0,1" line.long 0x4 "PHY2_PLL_REG16,Coarse_code values" hexmask.long.byte 0x4 0.--7. 1. "COARSE_CODE,01011010 8 LSBs of coarse code for PLL VCO" line.long 0x8 "PHY2_PLL_UNUSED_REG2,unused" hexmask.long.byte 0x8 0.--7. 1. "UNUSED,UNUSED" rgroup.long 0x180++0x33 line.long 0x0 "PHY2_CALIB_REG0,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x0 7. "CALIB_CLK,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x0 6. "CALIB_CLK_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x0 5. "COMP_OUT,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0x0 1.--4. 1. "INIT_WAIT_OVR,This is a reserved register or field. It should not be written or read and the value should be ignored." newline bitfld.long 0x0 0. "INIT_WAIT_OVR_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x4 "PHY2_CALIB_REG1,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x4 7. "UNUSED,unused" "0,1" newline hexmask.long.byte 0x4 1.--6. 1. "CALIB_CODE,This is a reserved register or field. It should not be written or read and the value should be ignored." newline bitfld.long 0x4 0. "CALIB_CODE_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x8 "PHY2_BC_REG0,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x8 4.--7. 1. "UNUSED,UNUSED" newline bitfld.long 0x8 3. "ADP_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 2. "ADP_EN_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 1. "ID_PULLUP,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 0. "ID_PULLUP_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0xC "PHY2_BC_REG1,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0xC 7. "ADP_SOURCE_I_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0xC 6. "ADP_SOURCE_I_EN_CTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0xC 5. "ADP_SINK_I_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0xC 4. "ADP_SINK_I_EN_CTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0xC 3. "ADP_SENSE_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0xC 2. "ADP_SENSE_EN_CTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0xC 1. "ADP_PROBE_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0xC 0. "ADP_PROBE_EN_CTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x10 "PHY2_BC_REG2,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x10 7. "IDM_SINK_EN_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 6. "IDM_SINK_EN_CNTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 5. "IDP_SINK_EN_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 4. "IDP_SINK_EN_CNTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 3. "IDP_SRC_EN_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 2. "IDP_SRC_EN_CNTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 1. "BC_EN_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 0. "BC_EN_CNTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x14 "PHY2_BC_REG3,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x14 7. "DM_VDAT_REF_COMP_EN_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 6. "DM_VDAT_REF_COMP_EN_CNTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 5. "DP_VDAT_REF_COMP_EN_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 4. "DP_VDAT_REF_COMP_EN_CNTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 3. "VDP_SRC_EN_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 2. "VDP_SRC_EN_CNTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 1. "VDM_SRC_EN_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 0. "VDM_SRC_EN_CNTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x18 "PHY2_BC_REG4,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x18 7. "RID_A_REF_EN_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 6. "RID_A_REF_EN_CNTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 5. "RID_FLOAT_REF_EN_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 4. "RID_FLOAT_REF_EN_CNTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 3. "RID_NONFLOAT_COMP_EN_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 2. "RID_NONFLOAT_COMP_EN_CNTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 1. "RID_FLOAT_COMP_EN_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 0. "RID_FLOAT_COMP_EN_CNTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x1C "PHY2_BC_REG5,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x1C 7. "RID_B_C_COMP_EN_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 6. "RID_B_C_COMP_EN_CNTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 5. "RID_A_COMP_EN_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 4. "RID_A_COMP_EN_CNTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 3. "RID_C_REF_EN_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 2. "RID_C_REF_EN_CNTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 1. "RID_B_REF_EN_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 0. "RID_B_REF_EN_CNTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x20 "PHY2_BC_REG6,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x20 3.--7. 1. "BC_DELAY_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." newline bitfld.long 0x20 2. "BC_DELAY_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x20 1. "DM_VLGC_COMP_EN_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x20 0. "DM_VLGC_COMP_EN_CNTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x24 "PHY2_BC_REG7,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x24 7. "RID_NONFLOAT_SRC_EN_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x24 6. "RID_NONFLOAT_SRC_EN_CNTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x24 5. "RID_FLOAT_SRC_EN_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x24 4. "RID_FLOAT_SRC_EN_CNTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x24 3. "RESET_CNTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x24 2. "DM_CURRENT_SRC_EN_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x24 1. "DM_CURRENT_SRC_EN_CNTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x24 0. "UNUSED,unused" "0,1" line.long 0x28 "PHY2_TED_REG0,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x28 7. "CALIB_CODE_UP_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x28 5.--6. "DELAY_VALUE,Delay is 8us" "0,1,2,3" newline bitfld.long 0x28 4. "DELAY_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x28 3. "CALIB_DONE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x28 2. "CALIIB_DONE_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x28 1. "COMP_OUT_DOWN_INV,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x28 0. "COMP_OUT_UP_INV,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x2C "PHY2_TED_REG1,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x2C 4.--7. 1. "CALIB_CODE_DOWN,This is a reserved register or field. It should not be written or read and the value should be ignored." newline hexmask.long.byte 0x2C 0.--3. 1. "CALIB_CODE_UP,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x30 "PHY2_TED_REG2,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x30 5.--7. "UNUSED,unused" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 4. "CALIB_MODE_DN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x30 3. "CALIB_MODE_DN_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x30 2. "CALIB_MODE_UP,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x30 1. "CALIB_MODE_UP_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x30 0. "CALIB_CODE_DN_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" rgroup.long 0x1B4++0x23 line.long 0x0 "PHY2_CALIB_REG2,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x0 4.--7. 1. "UNUSED,unused" newline bitfld.long 0x0 3. "CALIB_CMP,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x0 2. "CALIB_PD,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x0 1. "CALIB_CLOCK,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x0 0. "CALIB_DONE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x4 "PHY2_CALIB_REG3,Resistor calibration code" bitfld.long 0x4 5.--7. "UNUSED,unused" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--4. 1. "BG_UNIT_RES_CALIB,Resistor calibration code from the calibration block" line.long 0x8 "PHY2_BC_REG8,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x8 7. "DCD_COMP,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 6. "ADP_SENSE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 5. "ADP_PROBE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 4. "BVALID,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 3. "VBUSVALID,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 2. "IDDIG,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 0.--1. "UNUSED,unused" "0,1,2,3" line.long 0xC "PHY2_BC_REG9,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0xC 7. "O_DM_VDAT_REF_COMP_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0xC 6. "O_DP_VDAT_REF_COMP_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0xC 5. "O_VDM_SRC_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0xC 4. "O_VDP_SRC_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0xC 3. "O_IDM_SINK_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0xC 2. "O_IDP_SINK_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0xC 1. "O_IDP_SRC_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0xC 0. "O_BC_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x10 "PHY2_BC_REG10,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x10 7. "O_RID_B_C_COMP_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 6. "O_RID_A_COMP_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 5. "O_RID_C_REF_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 4. "O_RID_B_REF_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 3. "O_RID_A_REF_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 2. "O_RID_FLOAT_REF_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 1. "O_RID_NONFLOAT_SRC_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 0. "O_RID_FLOAT_SRC_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x14 "PHY2_BC_REG11,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x14 7. "O_IDM_SRC_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 6. "I_AFE_RXDP_ANA,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 5. "I_AFE_RXDM_ANA,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 4. "I_RID_B_C_COMP_STS,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 3. "I_RID_A_COMP_STS,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 2. "I_DM_VDAT_REF_COMP_STS,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 1. "I_DP_VDAT_REF_COMP_STS,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 0. "O_DM_VLGC_COMP_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x18 "PHY2_BC_REG12,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x18 7. "RID_GND_COMP_STS,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 6. "RID_FLOAT_COMP_STS,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 5. "RID_C_COMP_STS,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 4. "RID_B_COMP_STS,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 3. "RID_A_COMP_STS,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 2. "DM_VLGC_COMP_STS,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 1. "DM_VDAT_REF_COMP_STS,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 0. "DP_VDAT_REF_COMP_STS,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x1C "PHY2_TED_REG3,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x1C 4.--7. 1. "CALIB_CODE_DOWN,This is a reserved register or field. It should not be written or read and the value should be ignored." newline bitfld.long 0x1C 3. "COMPARATOR_DOWN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 2. "CALIB_DONE_DOWN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 0.--1. "UNUSED,UNUSED" "0,1,2,3" line.long 0x20 "PHY2_TED_REG4,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x20 4.--7. 1. "CALIB_CODE_UP,This is a reserved register or field. It should not be written or read and the value should be ignored." newline bitfld.long 0x20 3. "COMPARATOR_UP,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x20 2. "CALIB_DONE_UP,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x20 0.--1. "UNUSED,UNUSED" "0,1,2,3" rgroup.long 0x1D8++0x17 line.long 0x0 "PHY2_DIG_UNUSED_REG0,UNUSED" bitfld.long 0x0 7. "GLITCH_FILTER_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "UNUSED,UNUSED" line.long 0x4 "PHY2_DIG_UNUSED_REG1,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x4 3.--7. 1. "UNUSED,UNUSED" newline bitfld.long 0x4 1.--2. "THRESHOLD_OVR_VALUE_MSB,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3" newline bitfld.long 0x4 0. "THRESHOLD_OVR_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x8 "PHY2_DIG_UNUSED_REG2,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x8 0.--7. 1. "THRESHOLD_OVR_VALUE_LSB,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0xC "PHY2_DIG_UNUSED_REG3,UNUSED" hexmask.long.byte 0xC 0.--7. 1. "UNUSED,UNUSED" line.long 0x10 "PHY2_INTERRUPT_REG1,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x10 7. "IRSR,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 6. "ISR,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0x10 0.--5. 1. "UNUSED,UNUSED" line.long 0x14 "PHY2_INTERRUPT_REG2,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x14 1.--7. 1. "UNUSED,UNUSED" newline bitfld.long 0x14 0. "IMR,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" rgroup.long 0x200++0x33 line.long 0x0 "PHY2_RX_REG0,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x0 5.--7. "FSLS_NO_EOP_TIMEOUT,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "FSLS_TIMEOUT_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x0 3. "HS_SYNC_DET_BITS,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x0 1.--2. "FS_EOP_SE0_THRESHOLD,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3" newline bitfld.long 0x0 0. "FS_EOP_SE0_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x4 "PHY2_RX_REG1,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x4 2.--7. 1. "LS_EOP_SE0_THRESHOLD,This is a reserved register or field. It should not be written or read and the value should be ignored." newline bitfld.long 0x4 1. "LS_EOP_SE0_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x4 0. "FS_NO_EOP_TIMEOUT_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x8 "PHY2_TX_REG0,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x8 4.--7. 1. "UNUSED,unused" newline bitfld.long 0x8 3. "FS_PREAMBLE_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 1.--2. "SOF_EXTENSION,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3" newline bitfld.long 0x8 0. "SOF_EXTENSION_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0xC "PHY2_TX_REG1,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0xC 0.--7. 1. "PREAMBLE_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x10 "PHY2_CDR_REG0,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x10 6.--7. "UNUSED,unused" "0,1,2,3" newline bitfld.long 0x10 4.--5. "PLL_CLKDIV,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3" newline bitfld.long 0x10 3. "PLL_CLKDIV_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 1.--2. "SQUELCH_DELAY,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3" newline bitfld.long 0x10 0. "SQUELCH_DELAY_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x14 "PHY2_CDR_REG1,dynamic calib controls" bitfld.long 0x14 7. "UNUSED,unused" "0,1" newline bitfld.long 0x14 6. "CALIB_COMP_OUT,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 3.--5. "CALIB_SPC_THRESHOLD,000 The time interval between succesive calibrations is 0us 001 The time interval between succesive calibrations is 1us 010 The time interval between succesive calibrations is 2us 011 The time interval between succesive.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 2. "CALIB_SPC_THRESHOLD_EN,0 The time interval between succesive calibrations is taken as 5us by default 1 The time interval between succesive calibrations is taken from CDR_REG1[5:3]" "0,1" newline bitfld.long 0x14 1. "CALIB_ITERATION,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 0. "DYNAMIC_CALIB_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x18 "PHY2_CDR_REG2,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x18 7. "UNUSED,unused" "0,1" newline bitfld.long 0x18 6. "HSRX_EN_DEL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 5. "HSRX_EN_DEL_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 4. "HSRX_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 3. "HSRX_EN_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 2. "CALIB_CLOCK,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 1. "CALIB_CLOCK_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 0. "CALIB_OUT_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x1C "PHY2_CDR_REG3,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x1C 7. "CALIB_ACTIVE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 6. "CALIB_DONE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "CALIB_CODE,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x20 "PHY2_CDR_REG4,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x20 7. "CLK_GATE_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x20 6. "CLK_GATE_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x20 5. "CLK_GATE_SQ_MASK,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x20 3.--4. "LATENCY_THRESHOLD,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3" newline bitfld.long 0x20 2. "LATENCY_THRESHOLD_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x20 1. "DECISION_ERROR_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x20 0. "FILTER_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x24 "PHY2_CDR_REG5,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x24 3.--7. 1. "UNUSED,unused" newline bitfld.long 0x24 2. "SAMPLE_5X_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x24 1. "SMALL_PULSE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x24 0. "SMALL_PULSE_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x28 "PHY2_CDR_REG6,unused" hexmask.long.byte 0x28 0.--7. 1. "UNUSED,unused" line.long 0x2C "PHY2_CDR_REG7,unused" hexmask.long.byte 0x2C 0.--7. 1. "UNUSED,unused" line.long 0x30 "PHY2_CDR_REG8,unused" hexmask.long.byte 0x30 0.--7. 1. "UNUSED,unused" rgroup.long 0x234++0x33 line.long 0x0 "PHY2_RX_REG2,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x0 7. "EB_ERROR,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x0 6. "CDR_ERROR,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x0 5. "SYNC_DETECTED,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x0 4. "EOP_DETECTED,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x0 3. "HS_EOP_CONDITION,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x0 2. "NORMAL_EOP,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x0 1. "ALIGNMENT_ERROR,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x0 0. "NO_EOP,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x4 "PHY2_RX_REG3,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x4 7. "HS_EOP_DETECTED,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x4 6. "SE0_VALIDATED,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x4 5. "LSFS_EOP_DETECTED,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x4 4. "BIT_UNSTUFF_ERROR,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x4 1.--3. "RX_STATE_BITUNSTUFF,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "START_FLAG,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x8 "PHY2_RX_REG4,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x8 7. "RXACTIVE_REG,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 6. "DEASSERT_RXACTIVE_REG,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0x8 0.--5. 1. "UNUSED,unused" line.long 0xC "PHY2_RX_REG5,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0xC 0.--7. 1. "SIE_CNT_UPPER,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x10 "PHY2_RX_REG6,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x10 0.--7. 1. "PHY_CNT_UPPER,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x14 "PHY2_RX_REG7,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x14 4.--7. 1. "PHY_CNT_LOWER,This is a reserved register or field. It should not be written or read and the value should be ignored." newline hexmask.long.byte 0x14 0.--3. 1. "SIE_CNT_LOWER,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x18 "PHY2_TX_REG2,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x18 4.--7. 1. "TX_HS_STATE,This is a reserved register or field. It should not be written or read and the value should be ignored." newline bitfld.long 0x18 3. "EOP_TRANSMITTED,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 2. "HS_BITSTUFF_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 1. "RESUME_EOP,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x18 0. "REMOTE_WAKEUP,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x1C "PHY2_TX_REG3,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x1C 4.--7. 1. "TX_LSFS_STATE,This is a reserved register or field. It should not be written or read and the value should be ignored." newline bitfld.long 0x1C 1.--3. "PD_STATE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0. "PREAMBLE_SENT,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x20 "PHY2_TX_REG4,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x20 2.--7. 1. "UNUSED,unused" newline bitfld.long 0x20 1. "LSFS_BITSTUFF_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x20 0. "LS_KEEP_ALIVE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x24 "PHY2_CDR_REG9,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x24 3.--7. 1. "UNUSED,UNUSED" newline bitfld.long 0x24 2. "I_ANA_COMP_OUT,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x24 1. "SAMPLER_CALIB_DONE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x24 0. "ANA_CALIB_ACTIVE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x28 "PHY2_CDR_REG10,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x28 6.--7. "UNUSED,unused" "0,1,2,3" newline hexmask.long.byte 0x28 0.--5. 1. "CALIB_CODE,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x2C "PHY2_CDR_REG11,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x2C 4.--7. 1. "SMALL_PULSE,This is a reserved register or field. It should not be written or read and the value should be ignored." newline bitfld.long 0x2C 3. "O_HSRX_REC_DICISION_ERROR,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x2C 2. "O_ANA_CLK_GATE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x2C 1. "RECEIVE_START,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x2C 0. "I_ANA_TED_SQUELCH,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x30 "PHY2_CDR_RE12,unused" hexmask.long.byte 0x30 0.--7. 1. "UNUSED,unused" rgroup.long 0x268++0xF line.long 0x0 "PHY2_DIG_TXRX_UNUSED_REG0,UNUSED" hexmask.long.byte 0x0 0.--7. 1. "UNUSED,UNUSED" line.long 0x4 "PHY2_DIG_TXRX_UNUSED_REG1,UNUSED" hexmask.long.byte 0x4 0.--7. 1. "UNUSED,UNUSED" line.long 0x8 "PHY2_DIG_TXRX_UNUSED_REG2,UNUSED" hexmask.long.byte 0x8 0.--7. 1. "UNUSED,UNUSED" line.long 0xC "PHY2_DIG_TXRX_UNUSED_REG3,UNUSED" hexmask.long.byte 0xC 0.--7. 1. "UNUSED,UNUSED" rgroup.long 0x280++0x8B line.long 0x0 "PHY2_UTMI_REG0,register UTMI_REG0" bitfld.long 0x0 6.--7. "LOOPBACK_SEL,00 Loopback mode selection = 00 : Reserved 01 Loopback mode selection = 01 : LS 10 Loopback mode selection = 10 : FS 11 Loopback mode selection = 11 : HS" "0: Reserved,1: LS,?,?" newline bitfld.long 0x0 5. "LOOPBACK_EN,0 Loopback mode selection is taken from primary input port-loopback[1:0] 1 Loopback mode selection is taken from UTMI_REG0[7:6]." "0,1" newline hexmask.long.byte 0x0 1.--4. 1. "BIST_MODE_SEL,0 BIST for 8 bit 1 BIST for 16 bit 0 Error injection disabled 1 Error injection enabled 0 BIST for device mode 1 BIST for host mode 0 BIST for HS mode 1 BIST for FS mode." newline bitfld.long 0x0 0. "BIST_EN,0 BIST control signals taken from primary input BIST related ports 1 BIST signals taken from UTMI REG0[4:1] UTMI_REG1[7:6] UTMI_REG5[7:6]" "0,1" line.long 0x4 "PHY2_UTMI_REG1,bist error injection. soft resets" bitfld.long 0x4 6.--7. "BIST_ERR,00 Introduce error on first packet bist error injection = 00 01 Introduce error on second packet bist error injection = 01 10 Introduce error on third packet bist error injection = 10 11 Introduce error on last packet bist error injection.." "0,1,2,3" newline bitfld.long 0x4 5. "BIST_SOFT_RST,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x4 4. "TX_LSFS_SOFT_RST,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x4 3. "TX_HS_SOFT_RST,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x4 2. "CLKDIV_SOFT_RST,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x4 1. "CALIB_SOFT_RST,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x4 0. "PHY_SOFT_RST,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x8 "PHY2_UTMI_REG2,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x8 7. "RX_CNTRL_SOFT_RST,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 6. "SHIFT_REG_SOFT_RST,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 5. "BITUNSTUFF_SOFT_RST,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 4. "NRZI_DEC_SOFT_RST,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 3. "EOP_DET_SOFT_RST,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 2. "SYNC_DET_SOFT_RST,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 1. "LSFS_DLL_SOFT_RST,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 0. "RX_HS_SOFT_RST,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0xC "PHY2_UTMI_REG3,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0xC 7. "HS_RX_ERR,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0xC 6. "LS_LINESTATE_FIL_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0xC 1.--5. 1. "FS_LINESTATE_FIL_CNT,This is a reserved register or field. It should not be written or read and the value should be ignored." newline bitfld.long 0xC 0. "FS_LINESTATE_FIL_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x10 "PHY2_UTMI_REG4,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x10 0.--7. 1. "LS_LINESTATE_FIL_CNT,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x14 "PHY2_UTMI_REG5,BIST. hsrx data" bitfld.long 0x14 7. "BIST_MODE_EN,0 BIST mode en is taken from primary input port- bist_mode_en 1 bist_mode_en is turned on." "0,1" newline bitfld.long 0x14 6. "BIST_ON,0 BIST on is taken from primary input port- bist_on 1 bist_on is enabled." "0,1" newline bitfld.long 0x14 5. "HSTX_BOOST_DEAMP_OFF,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 4. "HSTX_BOOST,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 3. "HS_SAMP,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 2. "HS_SAMP_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 1. "HSRX,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 0. "HSRX_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x18 "PHY2_UTMI_REG6,vbusvalid control. hs drive en threshold" bitfld.long 0x18 7. "VBUSVALID_CNTRL,0 vbusvalid comparator is not enabled in L3 device Powered Off state 1 vbusvalid comparator is enabled in L3 device Powered Off state" "0,1" newline bitfld.long 0x18 6. "VBUSVALID_L3_DEV_EN,0 Vbusvalid comparator output comes on vbusvalid primary output port 1 Sessvalid comparator output comes on vbusvalid primary output port." "0,1" newline hexmask.long.byte 0x18 1.--5. 1. "HS_DRVEN_THRESHOLD,This is a reserved register or field. It should not be written or read and the value should be ignored." newline bitfld.long 0x18 0. "HS_DRVEN_TH_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x1C "PHY2_UTMI_REG7,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x1C 7. "HSTX_BC_MODE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 6. "HSTX_BC_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 5. "HSTX_CHIRP_MODE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 4. "HSTX_CHIRP_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 3. "HSTX_EN_DEL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 2. "HSTX_EN_DEL_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 1. "HSTX,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 0. "HSTX_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x20 "PHY2_UTMI_REG8,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x20 7. "HS_TERM,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x20 6. "HS_TERM_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x20 5. "HSTX_DATA,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x20 4. "HSTX_DATA_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x20 3. "HSTX_DRV,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x20 2. "HSTX_DRV_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x20 1. "HSTX_PREDRV,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x20 0. "HSTX_PREDRV_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x24 "PHY2_UTMI_REG9,hs delay values" bitfld.long 0x24 7. "CLKOFF_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x24 4.--6. "SDC_SPACE,000- The time between successive resistor calibration is 0ms 001- The time between successive resistor calibration is 500ms 010- The time between successive resistor calibration is 1000ms 011- The time between successive resistor calibration.." "0: The time between successive resistor calibration..,1: The time between successive resistor calibration..,?,?,?,?,?,?" newline bitfld.long 0x24 3. "SDC_SPACE_EN,0- The time between successive resistor calibration taken as 1s by default 1- The time between successive resistor calibration taken from UTMI_REG9[6:4]." "0: The time between successive resistor calibration..,1: The time between successive resistor calibration.." newline bitfld.long 0x24 1.--2. "HSTX_EN_DEL_TH,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3" newline bitfld.long 0x24 0. "HSTX_EN_DEL_TH_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x28 "PHY2_UTMI_REG10,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x28 7. "PLL_CLKON,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x28 6. "PLL_CLKON_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x28 5. "BG_PD_BG_OK,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x28 4. "BG_PD_BG_OK_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x28 3. "LSFS_SERX,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x28 2. "LSFS_SERX_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x28 1. "LSFS_RX,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x28 0. "LSFS_RX_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x2C "PHY2_UTMI_REG11,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x2C 7. "CLEAN_LINESTATE_SERX_MASK_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x2C 6. "SERX_MASK_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x2C 4.--5. "SERX_MASK_THRESHOLD,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3" newline bitfld.long 0x2C 3. "LSFS_TX,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x2C 2. "LSFS_TX_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x2C 1. "FSLS_EDGESEL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x2C 0. "FSLS_EDGESEL_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x30 "PHY2_UTMI_REG12,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x30 6.--7. "SERX_BIAS_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3" newline bitfld.long 0x30 5. "FSLS_TX_DATA,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x30 4. "FSLS_TX_DATA_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x30 3. "FSLS_TX_SE0,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x30 2. "FSLS_TX_SE0_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x30 1. "FSLS_TX_DRV,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x30 0. "FSLS_TX_DRV_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x34 "PHY2_UTMI_REG13,serial mode" bitfld.long 0x34 7. "FSLS_SERIALMODE_PULLUP2,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x34 6. "FSLS_SERIALMODE_PULLUP2_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x34 5. "DM_PULLDOWN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x34 4. "DM_PULLDOWN_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x34 3. "DP_PULLDOWN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x34 2. "DP_PULLDOWN_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x34 1. "LANE_REVERSE,0- Polarity inversion of DP/DM is not done 1- Polarity inversion of DP/DM is done" "0: Polarity inversion of DP/DM is not done,1: Polarity inversion of DP/DM is done" newline bitfld.long 0x34 0. "LANE_REVERSE_EN,0- Lane Reverse Value is taken from primary input portlane_reverse 1- Lane Reverse Value taken from UTMI_REG13[1]" "0: Lane Reverse Value is taken from primary input..,1: Lane Reverse Value taken from UTMI_REG13[1]" line.long 0x38 "PHY2_UTMI_REG14,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x38 7. "DM_PULLUP2,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x38 6. "DM_PULLUP2_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x38 5. "DP_PULLUP2,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x38 4. "DP_PULLUP2_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x38 3. "DM_PULLUP1,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x38 2. "DM_PULLUP1_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x38 1. "DP_PULLUP1,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x38 0. "DP_PULLUP1_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x3C "PHY2_UTMI_REG15,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x3C 6.--7. "TXVALID_GATE_THRESHOLD_FS,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3" newline bitfld.long 0x3C 4.--5. "TXVALID_GATE_THRESHOLD_HS,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3" newline bitfld.long 0x3C 3. "TED_EN_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x3C 2. "TED_EN_CNT,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x3C 1. "ED_EN_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x3C 0. "ED_EN_CNT,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x40 "PHY2_UTMI_REG16,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x40 0.--7. 1. "UNUSED,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x44 "PHY2_UTMI_REG17,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x44 6.--7. "SQUELCH_COUNT_IDLE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3" newline bitfld.long 0x44 5. "SQUELCH_COUNT_IDLE_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0x44 1.--4. 1. "TX_SQ_CNT,This is a reserved register or field. It should not be written or read and the value should be ignored." newline bitfld.long 0x44 0. "TX_SQ_CNT_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x48 "PHY2_UTMI_REG18,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x48 7. "SLEEP_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x48 6. "SLEEP_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x48 5. "BIST_POWERUP,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x48 4. "BIST_POWERUP_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x48 3. "POWERUP_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x48 2. "UNUSED,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x48 1. "CLIPPER_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x48 0. "CLIPPER_EN_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x4C "PHY2_UTMI_REG19,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x4C 1.--7. 1. "UNUSED,unused" newline bitfld.long 0x4C 0. "TED_SW_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x50 "PHY2_UTMI_REG20,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x50 7. "HOSTDISCON_RST_REG,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x50 6. "HOSTDISCON_RST_REG_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0x50 1.--5. 1. "CALIB_RST_DT,This is a reserved register or field. It should not be written or read and the value should be ignored." newline bitfld.long 0x50 0. "CALIB_RST_DT_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x54 "PHY2_UTMI_REG21,Register UTMI_REG21" bitfld.long 0x54 7. "CALIB_TRIGER_POSEDGE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x54 6. "AUTO_CAL_ENABLE,0- Dynamic resistor calibration is disabled 1- Dynamic resistor calibration is enabled" "0: Dynamic resistor calibration is disabled,1: Dynamic resistor calibration is enabled" newline bitfld.long 0x54 5. "ABSVALID,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x54 4. "ABSVALID_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x54 3. "VBUSVALID,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x54 2. "VBUSVALID_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x54 1. "SUSPENDM,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x54 0. "SUSPENDM_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x58 "PHY2_UTMI_REG22,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x58 0.--7. 1. "BCCALIB_OFFSET,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x5C "PHY2_UTMI_REG23,hscalib code offset" hexmask.long.byte 0x5C 0.--7. 1. "HSCALIB_OFFSET,Bit 0= 0- Final resistor calibration code going to HSTX is not offsetted 1- Offset given by bits [6:2] is considered for computation of final resistor code going to HSTX. Bit 1= 0- ADD the offset given in bits [6:2] to the resistor.." line.long 0x60 "PHY2_UTMI_REG24,fscalib code offset" hexmask.long.byte 0x60 0.--7. 1. "FSCALIB_OFFSET,Bit 0= 0- Final resistor calibration code going to FSTX is not offsetted 1- Offset given by bits [6:2] is used for computation of final resistor code going to FSTX. Bit 1= 0- ADD the offset given in bits [6:2] to the Resistor calibration.." line.long 0x64 "PHY2_UTMI_REG25,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x64 7. "UNUSED,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0x64 0.--6. 1. "HSCALIB,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x68 "PHY2_UTMI_REG26,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x68 7. "UNUSED,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0x68 0.--6. 1. "FSCALIB,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x6C "PHY2_UTMI_REG27,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x6C 7. "UNUSED,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0x6C 0.--6. 1. "BCCALIB,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x70 "PHY2_UTMI_REG28,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x70 7. "CDR_EB_WR_RESET,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0x70 1.--6. 1. "UNUSED,This is a reserved register or field. It should not be written or read and the value should be ignored." newline bitfld.long 0x70 0. "SERX_EN_CNTRL_OPMODE01,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x74 "PHY2_UTMI_REG29,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x74 6.--7. "UNUSED,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3" newline bitfld.long 0x74 5. "PLL_STANDALONE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x74 4. "PLL_STANDALONE_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0x74 0.--3. 1. "SPARE_OUT,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x78 "PHY2_UTMI_REG30,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x78 7. "UNUSED,unused" "0,1" newline bitfld.long 0x78 6. "PLL_480_CLOCK_GATE_OVR,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x78 5. "SCAN_ATS_HS_CLOCK_GATE_OVR,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x78 4. "VCO_PLL_CLOCK_GATE_OVR,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x78 3. "DIG_DIV_REFCLOCK_GATE_OVR,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x78 2. "FB_CLOCK_GATE_OVR,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x78 1. "ANA_DIV_REFCLOCK_GATE_OVR,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x78 0. "HS_CLOCK_GATE_OVR,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x7C "PHY2_UTMI_UNUSED_REG0,unused" hexmask.long.byte 0x7C 0.--7. 1. "UNUSED,unused" line.long 0x80 "PHY2_UTMI_UNUSED_REG1,unused" hexmask.long.byte 0x80 0.--7. 1. "UNUSED,unused" line.long 0x84 "PHY2_UTMI_UNUSED_REG2,unused" hexmask.long.byte 0x84 0.--7. 1. "UNUSED,unused" line.long 0x88 "PHY2_UTMI_UNUSED_REG3,unused" hexmask.long.byte 0x88 0.--7. 1. "UNUSED,unused" rgroup.long 0x30C++0x7B line.long 0x0 "PHY2_UTMI_REG31,bist" hexmask.long.byte 0x0 2.--7. 1. "UNUSED,UNUSED" newline bitfld.long 0x0 1. "BIST_ERROR,0- BIST resulted in no Error 1- BIST resulted in Error" "0: BIST resulted in no Error,1: BIST resulted in Error" newline bitfld.long 0x0 0. "BIST_COMPLETE,0- BIST is Not complete 1- BIST is Complete" "0: BIST is Not complete,1: BIST is Complete" line.long 0x4 "PHY2_UTMI_REG32,bist error count" hexmask.long.byte 0x4 0.--7. 1. "BIST_ERR_COUNT,00000000 Number of bytes that resulted in error while running BIST" line.long 0x8 "PHY2_UTMI_REG33,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x8 7. "BG_POWERGOOD,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 6. "AFE_HSRX_DIFF_DATA,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 5. "HSRX_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 4. "HSRX_SAMPLER_ENABLE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 3. "CHIRP_MODE_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 2. "HSTX_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 1. "HSTX_EN_DELAYED,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x8 0. "HSTX_BOOST_DEAMP_OFF,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0xC "PHY2_UTMI_REG34,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0xC 7. "O_DPRPU1_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0xC 6. "O_DMRPU1_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0xC 5. "O_DPRPU2_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0xC 4. "O_DMRPU2_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0xC 3. "O_DPRPD_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0xC 2. "O_DMRPD_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0xC 1. "O_OTGC_ID_PULLUP_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0xC 0. "O_FS_EDGE_SEL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x10 "PHY2_UTMI_REG35,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x10 7. "I_AFE_LSFSRX_ANA,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 6. "O_LSFSTX_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 5. "O_LSFSDRV_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 4. "O_LSFS_DDI,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 3. "O_ASSERT_SEZERO,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 2. "O_LSFSRX_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 1. "O_SERX_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x10 0. "O_SERX_BIAS_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x14 "PHY2_UTMI_REG36,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x14 7. "O_PLL_PSO,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 6. "O_PLL_PSO_DELAY,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x14 5. "O_PLL_PD,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0x14 0.--4. 1. "O_PLL_IPDIV,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x18 "PHY2_UTMI_REG37,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x18 0.--7. 1. "O_PLL_FBDIV_VALUE,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x1C "PHY2_UTMI_REG38,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x1C 7. "O_PLL_STANDBY,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 6. "O_PLL_LDO_CORE_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 5. "O_PLL_LDO_REF_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 4. "O_AFE_SUSPENDM,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 3. "O_OTGC_VBUSVALID_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 2. "O_OTGC_ABSVALID_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 1. "O_AFE_CLIPPER_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x1C 0. "O_PLL_LDO_ISOLATION_CNTRL,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x20 "PHY2_UTMI_REG39,unused" hexmask.long.byte 0x20 0.--7. 1. "UNUSED,unused" line.long 0x24 "PHY2_UTMI_REG40,unused" hexmask.long.byte 0x24 0.--7. 1. "UNUSED,unused" line.long 0x28 "PHY2_UTMI_REG41,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x28 7. "I_TED_SQUELCH_ANA,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x28 6. "I_USB2_RESCAL_CALIB_DONE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0x28 0.--5. 1. "HS_CALIB_CODE,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x2C "PHY2_UTMI_REG42,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x2C 7. "HS_SOF,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x2C 6. "ALL_CALIB_DONE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0x2C 0.--5. 1. "FS_CALIB_CODE,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x30 "PHY2_UTMI_REG43,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x30 7. "LS_MODE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x30 6. "FS_MODE_PRE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0x30 0.--5. 1. "BC_CALIB_CODE,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x34 "PHY2_UTMI_REG44,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x34 7. "RSTN_REFCLOCK,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x34 6. "RSTN_HS_CLOCK,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x34 5. "RSTN_HS_TX_CLOCK,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x34 4. "RSTN_BYTE_CLOCK,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x34 3. "RSTN_SIECLOCK,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x34 2. "RSTN_CLKDIV,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x34 1. "RSTN_CALIB_CLKDIV,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x34 0. "UDC_RSTN_CDR_ASYNC,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x38 "PHY2_UTMI_REG45,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x38 7. "UDC_CALIB_RSTN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x38 6. "UDC_APB_RSTN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x38 5. "O_RSTN_CDR_ASYNC,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x38 4. "O_PLL_CALIB_RSTN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x38 3. "BIST_MODE_RSTN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x38 2. "O_USB2_CALIB_RSTN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x38 1. "UDC_BC_CALIB_RSTN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x38 0. "GLOBAL_RESETN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x3C "PHY2_UTMI_REG46,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x3C 7. "UNUSED,unused" "0,1" newline bitfld.long 0x3C 6. "RECOVERY_CNT_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x3C 4.--5. "CLEAN_LINESTATE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3" newline hexmask.long.byte 0x3C 0.--3. 1. "BC_STATE_MACHINE_STATUS,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x40 "PHY2_UTMI_REG47,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x40 7. "FILTER_CNT_EN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x40 5.--6. "HOST_OPMODE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3" newline bitfld.long 0x40 3.--4. "DEV_OPMODE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3" newline bitfld.long 0x40 2. "I_DED_ANA,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x40 1. "HS_HOSTDISCONNECT,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x40 0. "LSFS_HOSTDISCONNECT,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x44 "PHY2_UTMI_REG48,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x44 6.--7. "BIST_TX_STATE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3" newline hexmask.long.byte 0x44 0.--5. 1. "DATA_CNT_TX,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x48 "PHY2_UTMI_REG49,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x48 6.--7. "BIST_RX_STATE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3" newline hexmask.long.byte 0x48 0.--5. 1. "DATA_CNT_RX,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x4C "PHY2_UTMI_REG50,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x4C 4.--7. 1. "BIST_TOP_STATE,This is a reserved register or field. It should not be written or read and the value should be ignored." newline bitfld.long 0x4C 3. "INC_DATA_CNT_TX,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x4C 2. "INC_DATA_CNT_RX,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x4C 1. "O_BG_PD,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x4C 0. "O_BG_PD_BG_OK,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x50 "PHY2_UTMI_REG51,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x50 6.--7. "POWERDOWN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3" newline bitfld.long 0x50 5. "RESET,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x50 4. "SUSPENDM,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x50 3. "TERMSELECT,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x50 2. "DATABUS16_8,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x50 1. "DPPULLDOWN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x50 0. "DMPULLDOWN,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x54 "PHY2_UTMI_REG52,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x54 7. "LANE_REVERSE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x54 6. "TXBITSTUFFENABLE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x54 5. "TXBITSTUFFENABLEH,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x54 3.--4. "XCVRSELECT,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3" newline bitfld.long 0x54 1.--2. "LINESTATE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3" newline bitfld.long 0x54 0. "HOSTDISCONNECT,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x58 "PHY2_UTMI_REG53,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x58 7. "FSLSSERIALMODE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x58 6. "TX_ENABLE_N,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x58 5. "TX_DAT,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x58 4. "TX_SE0,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x58 3. "SLEEPM,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x58 2. "UNUSED,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x58 0.--1. "OPMODE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1,2,3" line.long 0x5C "PHY2_UTMI_REG54,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x5C 7. "RX_DP,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x5C 6. "RX_DM,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x5C 5. "RX_RCV,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline hexmask.long.byte 0x5C 0.--4. 1. "UNUSED,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x60 "PHY2_UTMI_REG55,This is a reserved register or field. It should not be written or read. and the value should be ignored." bitfld.long 0x60 7. "TXVALIDH,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x60 6. "TXVALID,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x60 5. "TXREADY,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x60 4. "RXVALIDH,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x60 3. "RXVALID,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x60 2. "RXACTIVE,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x60 1. "RXERROR,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" newline bitfld.long 0x60 0. "UNUSED,This is a reserved register or field. It should not be written or read and the value should be ignored." "0,1" line.long 0x64 "PHY2_UTMI_REG56,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x64 0.--7. 1. "DATAIN_UPPER,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x68 "PHY2_UTMI_REG57,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x68 0.--7. 1. "DATAIN_LOWER,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x6C "PHY2_UTMI_REG58,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x6C 0.--7. 1. "DATAOUT_UPPER,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x70 "PHY2_UTMI_REG59,This is a reserved register or field. It should not be written or read. and the value should be ignored." hexmask.long.byte 0x70 0.--7. 1. "DATAOUT_LOWER,This is a reserved register or field. It should not be written or read and the value should be ignored." line.long 0x74 "PHY2_UTMI_UNUSED_REG6,UNUSED" hexmask.long.byte 0x74 0.--7. 1. "UNUSED,unused" line.long 0x78 "PHY2_UTMI_UNUSED_REG7,UNUSED" hexmask.long.byte 0x78 0.--7. 1. "UNUSED,unused" tree.end tree "USB0_RAMS_INJ_CFG (USB0_RAMS_INJ_CFG)" base ad:0x2A10000 rgroup.long 0x0++0x7 line.long 0x0 "RAMS__INJ_CFG__CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "RAMS__INJ_CFG__CFG_INFO,The Info Register gives the configuration Inforrmation of this module." hexmask.long.byte 0x4 0.--5. 1. "ENDPOINTS,Total number of Targets supported by this configuration" rgroup.long 0x8++0x3 line.long 0x0 "RAMS__INJ_CFG__CFG_SFT_RST,The Global Soft Reset Register clears all programmable registers and returns the injector to idle state" hexmask.long.byte 0x0 0.--3. 1. "KEY,Write 4'b1010 to issue a soft reset. All other written values are ignored. Always read as 0" rgroup.long 0x10++0xF line.long 0x0 "RAMS__INJ_CFG__CFG_BIT1,This register defines the first bit to be flipped when injection is enabled" hexmask.long.word 0x0 0.--15. 1. "BIT1,First bit to be flipped on an error injection" line.long 0x4 "RAMS__INJ_CFG__CFG_BIT2,This register defines the second bit to be flipped if 2-bit injection is enabled" hexmask.long.word 0x4 0.--15. 1. "BIT2,Second bit to be flipped on an error injection if 2-bit injection is chosen." line.long 0x8 "RAMS__INJ_CFG__CFG_TRGT,This is the target selection regsiter" hexmask.long.byte 0x8 0.--4. 1. "TRGT,Select which target to interact with. Writes of a value higher than the number of targets supported by this configuration will have no effect" line.long 0xC "RAMS__INJ_CFG__CFG_CTRL,Controls the injection" hexmask.long.byte 0xC 8.--12. 1. "TRGT,Indicates which target is selected by the TRGT register" rbitfld.long 0xC 2. "DONE,Indicates that the target selected by TRGT has completed error injection. This status supercedes the armed bit" "0,1" bitfld.long 0xC 1. "TWOBIT,Write 1 to trigger a 2-bit error in target selected by TRGT regsiter. Write 0 to finish or cancel 2-bit injection. If both 1 and 2-bit injection are set 2-bit injection will be performed" "0,1" bitfld.long 0xC 0. "ONEBIT,Write 1 to trigger a 1-bit error in target selected by TRGT regsiter. Write 0 to finish or cancel 1-bit injection" "?,1: bit injection" rgroup.long 0x20++0x3 line.long 0x0 "RAMS__INJ_CFG__CFG_STATUS,Controls the injection" bitfld.long 0x0 2. "ARMED,Indicates that the target selected by TRGT is ARMED for error injection" "0,1" tree.end tree "USB0_VBP2APB_WRAP_CONTROLLER_VBP_CORE_ADDR_MAP (USB0_VBP2APB_WRAP_CONTROLLER_VBP_CORE_ADDR_MAP)" base ad:0x6000000 rgroup.long 0x0++0xB line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_CDNS_DID,Cadence Device ID Register" hexmask.long 0x0 0.--31. 1. "DID,Cadence Device ID Register IP4024E" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_CDNS_RID,Cadence Revision ID Register" hexmask.long.word 0x4 16.--31. 1. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline hexmask.long.word 0x4 0.--15. 1. "CDNS_RID,CDNS_RID" line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_OTGCAPABILITY,OTG Capabilities register" hexmask.long.word 0x8 20.--31. 1. "OTG3REVISION,Specifies implemeted OTG3.0 specification revision" newline hexmask.long.word 0x8 8.--19. 1. "OTG2REVISION,Specifies implemeted OTG2.0 specification revision" newline bitfld.long 0x8 6.--7. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." "0,1,2,3" newline bitfld.long 0x8 5. "REFCLK_DISABLE,PHY Reference clock control disable. 0 - PHY Reference clock control supported 1 - PHY Reference clock control not supported" "0: PHY Reference clock control supported 1,?" newline bitfld.long 0x8 4. "RSP_SUPPORT,RSP support. 0 - RSP not supported 1 - RSP supported" "0: RSP not supported 1,?" newline bitfld.long 0x8 3. "BC_SUPPORT,BC Support [Battery Charging specification rev 1.2]. 0 - BC not supported 1 - BC supported" "0: BC not supported 1,?" newline bitfld.long 0x8 2. "ADP_SUPPORT,ADP support. 0 - ADP not supported 1 - ADP supported" "0: ADP not supported 1,?" newline bitfld.long 0x8 1. "HNP_SUPPORT,HNP support. 0 - HNP not supported 1 - HNP supported" "0: HNP not supported 1,?" newline bitfld.long 0x8 0. "SRP_SUPPORT,SRP support. 0 - SRP not supported 1 - SRP supported" "0: SRP not supported 1,?" rgroup.long 0x10++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_OTGCMD,OTGCMD" rbitfld.long 0x0 31. "RSVD2,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." "0,1" newline bitfld.long 0x0 30. "DEV_VBUS_DEB_SHORT_CLR,Disable forcing Device short VBUS debounce time. Setting this bit causes DEV_VBUS_DEB_SHORT bit in OTGSTS clear." "0,1" newline bitfld.long 0x0 29. "DEV_VBUS_DEB_SHORT_SET,Enable forcing Device short VBUS debounce time. This bit should be set while switching from Host to Device mode takes place. Setting this bit should be done in the same time when Device mode is activated [DEV_BUS_REQ]." "0,1" newline bitfld.long 0x0 28. "INIT_SRP,Initiate SRP" "0,1" newline bitfld.long 0x0 27. "OTG2_SWITCH_TO_PERIPH,Switch to Peripheral mode when operating at USB 2.0" "0,1" newline bitfld.long 0x0 26. "B_HNP_EN_CLR,This bit should be written if software wants to clear b_hnp_enable" "0,1" newline bitfld.long 0x0 25. "B_HNP_EN_SET,This bit should be written if SetFeature[b_hnp_enable] has been accepted." "0,1" newline bitfld.long 0x0 24. "A_SET_B_HNP_EN_CLR,This bit should be written if upcoming USB 2.0 bus suspend should not cause Role Swap." "0,1" newline bitfld.long 0x0 23. "A_SET_B_HNP_EN_SET,This bit should be written if SetFeature[b_hnp_enable] has been sent." "0,1" newline bitfld.long 0x0 22. "SS_PERIPH_DISABLED_CLR,Enable SuperSpeed peripheral device functionality." "0,1" newline bitfld.long 0x0 21. "SS_PERIPH_DISABLED_SET,Disable SuperSpeed peripheral device functionality. Can be used only if Peripheral mode is not active." "0,1" newline bitfld.long 0x0 20. "SS_HOST_DISABLED_CLR,Enable SuperSpeed host functionality." "0,1" newline bitfld.long 0x0 19. "SS_HOST_DISABLED_SET,Disable SuperSpeed host functionality. Can be used only if Host mode is not active." "0,1" newline bitfld.long 0x0 18. "D_WRST_FOR_SWAP_CLR,Upcoming received Warm Reset should not be treated as Role Swapping indication. This bit should be set after Warm Reset for Role Swap is received on the Port" "0,1" newline bitfld.long 0x0 17. "D_WRST_FOR_SWAP_SET,Upcoming Warm Reset will be received for Role Swapping. This bit should be set before Warm Reset for Role Swap is received on the Port" "0,1" newline bitfld.long 0x0 16. "H_WRST_FOR_SWAP_CLR,Upcoming Warm Reset will not be generated for Role Swapping. This bit should be set after Warm Reset for Role Swap is generated on the Port" "0,1" newline bitfld.long 0x0 15. "H_WRST_FOR_SWAP_SET,Upcoming Warm Reset will be generated for Role Swapping. This bit should be set before Warm Reset for Role Swap is generated on the Port" "0,1" newline bitfld.long 0x0 14. "DEV_DEVEN_FORCE_CLR,Clear forcing Device DEVEN bit to 1. Setting this bit causes DEV_DEVEN_FORCE bit in OTGSTS clear." "0,1" newline bitfld.long 0x0 13. "DEV_DEVEN_FORCE_SET,Set forcing Device DEVEN bit to 1. This bit may be set while switching from Host to Device mode takes place. Setting this bit should be done in the same time when Device mode is activated [DEV_BUS_REQ]. Setting.." "0,1" newline bitfld.long 0x0 12. "HOST_POWER_OFF,Power Down CDNSXHCI." "0,1" newline bitfld.long 0x0 11. "DEV_POWER_OFF,Power Down USBSS-DEV." "0,1" newline bitfld.long 0x0 10. "DIS_VBUS_DROP,Do not disable vbus while bus is dropped. This bit is valid only if DEV_BUS_DROP or HOST_BUS_DROP are set." "0,1" newline bitfld.long 0x0 9. "HOST_BUS_DROP,Drop the bus for Host mode. This bit should be set when Host mode is no longer needed. It will clear HOST_ACTIVE bit is OTGSTS register" "0,1" newline bitfld.long 0x0 8. "DEV_BUS_DROP,Drop the bus for Device mode. This bit should be set when Device mode is no longer needed. It will clear DEV_ACTIVE bit is OTGSTS register" "0,1" newline bitfld.long 0x0 7. "DEV_SESS_VLD_USE_CLR,Device should use a_vbus_vld as vbus valid indication. This bit should be set in the same time when DEV_BUS_REQ" "0,1" newline bitfld.long 0x0 6. "DEV_SESS_VLD_USE_SET,Device should use b_sess_vld as vbus valid indication. This bit should be set in the same time when DEV_BUS_REQ" "0,1" newline bitfld.long 0x0 5. "A_DEV_DIS,Configure OTG as B-Device. It is only valid if OTG mode is enabled. This bit should be set in the same time when OTG_EN" "0,1" newline bitfld.long 0x0 4. "A_DEV_EN,Configure OTG as A-Device. It is only valid if OTG mode is enabled. This bit should be set in the same time when OTG_EN" "0,1" newline bitfld.long 0x0 3. "OTG_DIS,Disable OTG mode. It will clear OTG_IS_ENABLED bit is OTGSTS register" "0,1" newline bitfld.long 0x0 2. "OTG_EN,Enable OTG mode. It will set OTG_IS_ENABLED bit is OTGSTS register" "0,1" newline bitfld.long 0x0 1. "HOST_BUS_REQ,Request the bus for Host mode. It will set HOST_ACTIVE bit is OTGSTS register" "0,1" newline bitfld.long 0x0 0. "DEV_BUS_REQ,Request the bus for Device mode. It will set DEV_ACTIVE bit is OTGSTS register" "0,1" rgroup.long 0x14++0x7 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_OTGSTS,OTGSTS" bitfld.long 0x0 31. "VBUS_VALID_PHY,PHY VBUS valid comparator status" "0,1" newline bitfld.long 0x0 30. "SESS_VALID_PHY,PHY Session valid comparator status" "0,1" newline bitfld.long 0x0 29. "HOST_DISCONNECT_PHY,PHY hostdisconnect status" "0,1" newline bitfld.long 0x0 28. "IDDIG_PHY,PHY UTMI iddig status" "0,1" newline bitfld.long 0x0 27. "DEV_READY,Device mode is turned on. registers in USBSS-DEV domain are accessible through APB" "0,1" newline bitfld.long 0x0 26. "XHC_READY,Host mode is turned on. registers in CDNSXHCI AUX domain are accessible through APB" "0,1" newline bitfld.long 0x0 25. "B_HNP_EN,SetFeature[b_hnp_enable] has been accepted." "0,1" newline bitfld.long 0x0 24. "RSVD4,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." "0,1" newline bitfld.long 0x0 23. "A_SET_B_HNP_EN,SetFeature[b_hnp_enable] has been sent and is valid." "0,1" newline bitfld.long 0x0 22. "RSVD3,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." "0,1" newline bitfld.long 0x0 20.--21. "LINESTATE,PHY UTMI linestate status" "0,1,2,3" newline bitfld.long 0x0 19. "SRP_DET_NOT_COMPLIANT_DEV,OTG A-device detected not compilant device. If this bit is set then OTG A-device should disable SRP detection until not compilant device is disconnected [SRP_NOT_COMP_DEV_REMOVED_INT]" "0,1" newline bitfld.long 0x0 18. "SRP_INITIAL_CONDITION_MET,SRP initial condition are met. OTG B-device software should issue SRP puluse onli if this bit is set." "0,1" newline bitfld.long 0x0 17. "D_WRST_FOR_SWAP,Upcoming Warm Reset will be received for Role Swapping from Peripheral to Host." "0,1" newline bitfld.long 0x0 16. "DEV_DEVEN_FORCE,Device forcing DEVEN bit is enabled." "0,1" newline bitfld.long 0x0 15. "H_WRST_FOR_SWAP,Upcoming Warm Reset will be generated for Role Swapping from Host to Peripheral." "0,1" newline bitfld.long 0x0 12.--14. "STRAP,Value of the strap pins. 000 - no default configuration 010 - Controller initiall configured as Host 100 - Controller initially configured as Device other - Reserved [might be used for Type-C]" "0: no default configuration 010,?,?,?,?,?,?,?" newline bitfld.long 0x0 11. "OTG_NRDY,OTG Controller not ready. Software shall not read nor write any register except OTGISTS if this bit is set." "0,1" newline bitfld.long 0x0 10. "DEV_SESS_VLD_USE,Device mode vbus valid indication: 0: a_vbus_vld is used as vbus valid 1: b_sess_vld is used as vbus valid" "0: a_vbus_vld is used as vbus valid,1: b_sess_vld is used as vbus valid" newline bitfld.long 0x0 9. "DEV_VBUS_DEB_SHORT,Device forcing short VBUS decounce is enabled." "0,1" newline bitfld.long 0x0 8. "SS_PERIPH_DISABLED,SuperSpeed device functionality is disabled. Port will be operating at USB 2.0 speed." "0,1" newline bitfld.long 0x0 7. "SS_HOST_DISABLED,SuperSpeed host functionality is disabled. Port will be operating at USB 2.0 speed." "0,1" newline bitfld.long 0x0 6. "OTG_MODE,OTG mode: 0 - A-Device 1 - B-Device Valid only if OTG_IS_ENABLED is 1." "0: A-Device 1,?" newline bitfld.long 0x0 5. "OTG_IS_ENABLED,OTG functionality is enabled" "0,1" newline bitfld.long 0x0 4. "HOST_ACTIVE,Device mode is active. NOTE: It is possible that Host is in inactive state [even turned off] while HOST_ACTIVE is 1." "0,1" newline bitfld.long 0x0 3. "DEV_ACTIVE,Device mode is active. NOTE: It is possible that Device is in inactive state [even turned off] while DEV_ACTIVE is 1." "0,1" newline bitfld.long 0x0 2. "SESSION_VALID,The sessionvalid status visible to the controller" "0,1" newline bitfld.long 0x0 1. "VBUS_VALID,The vbusvalid status visible to the controller" "0,1" newline bitfld.long 0x0 0. "ID_VALUE,Current value of the ID pin visible to the controller. It is only valid when idpullup in PORTOVERRIDE_TYPE register is set to '1'. ID_VALUE must be valid within 50ms after idpullup is set to '1'" "0,1" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_OTGSTATE,OTGSTATE" hexmask.long.word 0x4 22.--31. 1. "RSVD3,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline bitfld.long 0x4 19.--21. "HOST_POWER_STATE,Current state of the Host power controlling FSM: 3'b000 : POWER_IDLE 3'b001 : POWER_OFF_ACK 3'b010 : POWER_OFF_MAIN_ACK 3'b011 : POWER_OFF 3'b100 : POWER_ON_REQ.." "0: POWER_IDLE 3'b001 : POWER_OFF_ACK 3'b010 :..,?,?,?,?,?,?,?" newline bitfld.long 0x4 16.--18. "DEV_POWER_STATE,Current state of the Device power controlling FSM: 3'b000 : POWER_IDLE 3'b001 : POWER_OFF_ACK 3'b010 : POWER_OFF_MAIN_ACK 3'b011 : POWER_OFF 3'b100 : POWER_ON_REQ.." "0: POWER_IDLE 3'b001 : POWER_OFF_ACK 3'b010 :..,?,?,?,?,?,?,?" newline bitfld.long 0x4 14.--15. "RSVD2,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." "0,1,2,3" newline bitfld.long 0x4 12.--13. "UTMI_CTRL,Current state of the USB2 UTMI mux selector. 2'b00 : Both modes off. OTG takes control over UTMI [SRP BC] 2'b01 : Host active. 2'b10 : Device active. 2'b11 : Illegal [both.." "0: Both modes off,1: Host active,2: Device active,3: Illegal [both modes off]" newline bitfld.long 0x4 10.--11. "PIPE_CTRL,Current state of the USB3 PIPE mux selector. 2'b00 : Both modes off. 2'b01 : Host active. 2'b10 : Device active. 2'b11 : Illegal [both modes off]" "0: Both modes off,1: Host active,2: Device active,3: Illegal [both modes off]" newline bitfld.long 0x4 8.--9. "APB_AXI_CTRL,Current state of the ABP/AXI mux selector. 2'b00 : Both modes off. 2'b01 : Host active. 2'b10 : Device active. 2'b11 : Illegal [both modes off]" "0: Both modes off,1: Host active,2: Device active,3: Illegal [both modes off]" newline bitfld.long 0x4 6.--7. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." "0,1,2,3" newline bitfld.long 0x4 3.--5. "HOST_OTG_STATE,Current state of the OTG Host FSM. 3'b000 : H_IDLE 3'b001 : H_VBUS_ON 3'b010 : H_VBUS_FAILED 3'b011 : H_OTG_HOST_MODE 3'b100 : H_HOST_MODE 3'b101 : H_SWITCH_TO_DEVICE.." "0: H_IDLE 3'b001 : H_VBUS_ON 3'b010 : H_VBUS_FAILED..,?,?,?,?,?,?,?" newline bitfld.long 0x4 0.--2. "DEV_OTG_STATE,Current state of the OTG Device FSM. 3'b000 : DEV_IDLE 3'b001 : DEV_MODE 3'b010 : DEV_SRP 3'b011 : DEV_WAIT_VBUS_FALL 3'b100 : DEV_SWITCH_TO_HOST 3'b101 :.." "0: DEV_IDLE 3'b001 : DEV_MODE 3'b010 : DEV_SRP..,?,?,?,?,?,?,?" rgroup.long 0x20++0xF line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_OTGIEN,OTGIEN" bitfld.long 0x0 31. "DM_VLGC_COMP_RISE_INT_EN,DM VLGC comparator rise detect interrupt enable" "0,1" newline bitfld.long 0x0 30. "DCD_COMP_FALL_INT_EN,DCD comparator fall detect interrupt enable" "0,1" newline bitfld.long 0x0 29. "DCD_COMP_RISE_INT_EN,DCD comparator rise detect interrupt enable" "0,1" newline bitfld.long 0x0 28. "DP_VDAT_REF_RISE_INT_EN,DP VDAT comparator rise detect interrupt enable" "0,1" newline bitfld.long 0x0 27. "DM_VDAT_REF_RISE_INT_EN,DM VDAT comparator rise detect interrupt enable" "0,1" newline bitfld.long 0x0 26. "RID_A_RISE_INT_EN,RID A comparator rise detect interrupt enable" "0,1" newline bitfld.long 0x0 25. "RID_B_RISE_INT_EN,RID B comparator rise detect interrupt enable" "0,1" newline bitfld.long 0x0 24. "RID_C_RISE_INT_EN,RID C comparator rise detect interrupt enable" "0,1" newline bitfld.long 0x0 23. "RID_GND_RISE_INT_EN,RID GND comparator rise detect interrupt enable" "0,1" newline bitfld.long 0x0 22. "RID_FLOAT_RISE_INT_EN,RID floating comparator rise detect interrupt enable" "0,1" newline bitfld.long 0x0 21. "RID_FLOAT_FALL_INT_EN,RID floating comparator detect interrupt enable" "0,1" newline bitfld.long 0x0 20. "H_WRST_GEN_CMPL_INT_EN,Host Warm Reset generation completed interrupt enable." "0,1" newline bitfld.long 0x0 19. "H_POLL_ENTRY_INT_EN,Host Polling state entry interrupt enable." "0,1" newline bitfld.long 0x0 18. "TIMER_TMOUT_INT_EN,Timer timeout interrupt enable." "0,1" newline bitfld.long 0x0 17. "TB_AIDL_BDIS_MIN_TMOUT_INT_EN,The bus has been in Idle state for the required time during HNP interrupt enable." "0,1" newline bitfld.long 0x0 16. "TB_ASE0_BRST_TMOUT_INT_EN,No response from A-Device to HNP interrupt enable." "0,1" newline bitfld.long 0x0 15. "SRP_CMPL_INT_EN,SRP completed interrupt enable." "0,1" newline bitfld.long 0x0 14. "SRP_FAIL_INT_EN,No response from SRP from A-Device interrupt enable." "0,1" newline bitfld.long 0x0 13. "OVERCURRENT_INT_EN,Overcurrent condition detected interrupt enable." "0,1" newline bitfld.long 0x0 12. "SRP_NOT_COMP_DEV_REMOVED_INT_EN,Non cmpliant device disconnect interrupt enable" "0,1" newline bitfld.long 0x0 11. "SRP_DET_INT_EN,SRP pulse detected interrupt enable. NOTE: SRP detection can be enabled only if core is enabled to work as a A-device [OTGSTS.OTG_MODE=0]" "0,1" newline bitfld.long 0x0 10. "TA_BIDL_ADIS_TMOUT_INT_EN,No activity from B-Device timeout interrupt enable." "0,1" newline bitfld.long 0x0 9. "TA_AIDL_BDIS_TMOUT_INT_EN,No response from B-Device for HNP interrupt enable." "0,1" newline bitfld.long 0x0 8. "ADP_PROBE_COMPLETED_INT_EN,ADP probe completed interrupt enable" "0,1" newline bitfld.long 0x0 7. "PROBE_RISE_INT_EN,ADP probe comparator rise detected interrupt enable" "0,1" newline bitfld.long 0x0 6. "SENSE_RISE_INT_EN,ADP sense comparator rise detected interrupt enable" "0,1" newline bitfld.long 0x0 5. "VBUSVALID_FALL_INT_EN,Vbusvalid fall detected interrupt enable." "0,1" newline bitfld.long 0x0 4. "VBUSVALID_RISE_INT_EN,Vbusvalid fall detected interrupt enable." "0,1" newline bitfld.long 0x0 3. "OTGSESSVALID_FALL_INT_EN,Otgsessvalid fall detected interrupt enable." "0,1" newline bitfld.long 0x0 2. "OTGSESSVALID_RISE_INT_EN,Otgsessvalid rise detected interrupt enable." "0,1" newline bitfld.long 0x0 1. "VBUS_ON_FAILED_INT_EN,Enabling Vbus by A-Device has failed interrupt enable." "0,1" newline bitfld.long 0x0 0. "ID_CHANGE_INT_EN,ID change interrupt enable" "0,1" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_OTGIVECT,OTGIVECT" bitfld.long 0x4 31. "DM_VLGC_COMP_RISE_INT,DM VLGC comparator rise detect interrupt" "0,1" newline bitfld.long 0x4 30. "DCD_COMP_FALL_INT,DCD comparator fall detect interrupt" "0,1" newline bitfld.long 0x4 29. "DCD_COMP_RISE_INT,DCD comparator rise detect interrupt" "0,1" newline bitfld.long 0x4 28. "DP_VDAT_REF_RISE_INT,DP VDAT comparator rise detect interrupt" "0,1" newline bitfld.long 0x4 27. "DM_VDAT_REF_RISE_INT,DM VDAT comparator rise detect interrupt" "0,1" newline bitfld.long 0x4 26. "RID_A_RISE_INT,RID A comparator rise detect interrupt" "0,1" newline bitfld.long 0x4 25. "RID_B_RISE_INT,RID B comparator rise detect interrupt" "0,1" newline bitfld.long 0x4 24. "RID_C_RISE_INT,RID C comparator rise detect interrupt" "0,1" newline bitfld.long 0x4 23. "RID_GND_RISE_INT,RID GND comparator rise detect interrupt" "0,1" newline bitfld.long 0x4 22. "RID_FLOAT_RISE_INT,RID floating comparator rise detect interrupt" "0,1" newline bitfld.long 0x4 21. "RID_FLOAT_FALL_INT,RID floating comparator detect interrupt" "0,1" newline bitfld.long 0x4 20. "H_WRST_GEN_CMPL_INT,Host Warm Reset generation completed interrupt." "0,1" newline bitfld.long 0x4 19. "H_POLLTRY_INT,Host Polling state entry interrupt." "0,1" newline bitfld.long 0x4 18. "TIMER_TMOUT_INT,Timer timeout interrupt." "0,1" newline bitfld.long 0x4 17. "TB_AIDL_BDIS_MIN_TMOUT_INT,The bus has been in Idle state for the required time during HNP interrupt." "0,1" newline bitfld.long 0x4 16. "TB_ASE0_BRST_TMOUT_INT,No response from A-Device to HNP interrupt." "0,1" newline bitfld.long 0x4 15. "SRP_CMPL_INT,SRP completed interrupt." "0,1" newline bitfld.long 0x4 14. "SRP_FAIL_INT,No response from SRP from A-Device interrupt." "0,1" newline bitfld.long 0x4 13. "OVERCURRENT_INT,Overcurrent condition detected interrupt." "0,1" newline bitfld.long 0x4 12. "SRP_NOT_COMP_DEV_REMOVED_INT,Not cmpliant device disconnect detect interrupt." "0,1" newline bitfld.long 0x4 11. "SRP_DET_INT,SRP pulse detected interrupt." "0,1" newline bitfld.long 0x4 10. "TA_BIDL_ADIS_TMOUT_INT,No activity from B-Device timeout interrupt." "0,1" newline bitfld.long 0x4 9. "TA_AIDL_BDIS_TMOUT_INT,No response from B-Device for HNP interrupt." "0,1" newline bitfld.long 0x4 8. "ADP_PROBE_COMPLETED_INT,ADP completed. Status is reported in OTGADPSTS register." "0,1" newline bitfld.long 0x4 7. "PROBE_RISE_INT,ADP probe comparator rise detected interrupt" "0,1" newline bitfld.long 0x4 6. "SENSE_RISE_INT,ADP sense comparator rise detected interrupt" "0,1" newline bitfld.long 0x4 5. "VBUSVALID_FALL_INT,Vbusvalid fall detected interrupt." "0,1" newline bitfld.long 0x4 4. "VBUSVALID_RISE_INT,Vbusvalid fall detected interrupt." "0,1" newline bitfld.long 0x4 3. "OTGSESSVALID_FALL_INT,Otgsessvalid fall detected interrupt." "0,1" newline bitfld.long 0x4 2. "OTGSESSVALID_RISE_INT,Otgsessvalid rise detected interrupt." "0,1" newline bitfld.long 0x4 1. "VBUS_ON_FAILED_INT,Enabling Vbus by A-Device has failed. This bit should be cleared before enabling subsequent connection as host." "0,1" newline bitfld.long 0x4 0. "ID_CHANGE_INT,ID change interrupt" "0,1" line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_CLK_FREQ,CLK_FREQ" hexmask.long.word 0x8 16.--31. 1. "CLK_FREQ_KHZ,CLK_FREQ_KHZ defines how many cycles are needed to determine 1 ms clock base for stb_clk_predft. Example: Let's say that stb_clk_predft frequency is 32kHz. With CLK_FREQ_KHZ set to 32 time base would be.." newline hexmask.long.word 0x8 0.--15. 1. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_OTGTMR,OTGTMR" bitfld.long 0xC 31. "ITC_EN,ITC ENABLE for device mode 0 - Device IOC and ISP interrupts moderation by OTG_IVECT interrupt from OTGTMR is disabled. 1 - The OTGTMR is used for Device IOC and ISP interrupts moderation. The OTG_IVECT from OTGTMR is not.." "0: Device IOC and ISP interrupts moderation by..,1: The OTGTMR is used for Device IOC and ISP.." newline hexmask.long.word 0xC 21.--30. 1. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline bitfld.long 0xC 20. "TIMER_STOP,Stop timer" "0,1" newline bitfld.long 0xC 19. "TIMER_START,Start timer" "0,1" newline bitfld.long 0xC 18. "TIMER_WRITE,Timer value and units write strobe" "0,1" newline bitfld.long 0xC 16.--17. "TIMEOUT_UNITS,Time units: 0 - hundreds of microseconds [valid only if otg controller clock is in MHz range] 1 - milliseconds 2 - tens of milliseconds 3 - hundreds of milliseconds Valid only if.." "0: hundreds of microseconds [valid only if otg..,?,2: tens of milliseconds 3,?" newline hexmask.long.word 0xC 0.--15. 1. "TIMEOUT_VALUE,Timeout value for timer. Valid only if TIMER_WRITE is 1." rgroup.long 0x40++0xF line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_OTGSIMULATE,OTGSIMULATE" hexmask.long 0x0 1.--31. 1. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline bitfld.long 0x0 0. "OTG_CFG_FAST_SIMS,Debug Feature. This bit is for simulation modes only. It enables reductions to OTG timings. '0': Normal timings '1': Enable fast simulation timing modes This bit should be written '0' in normal.." "0,1" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_OVERRIDE,PORT_OVERRIDE" hexmask.long.byte 0x4 28.--31. 1. "RSVD3,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline bitfld.long 0x4 27. "OVERRIDE_SLEEPM_SFR,SFR sleepm control. Value this bit is passed to PHY sleepm signal. This bit is valid only with PORT_OVERRIDE. override_sleepm_sel set to '1'." "0,1" newline bitfld.long 0x4 26. "OVERRIDE_SLEEPM_SEL,sleepm override select. This register allows SW driver override sleepm pin as follows: 0: sleepm is controlled from active controller [host/device/none] 1: sleepm controlled from SFR" "0: sleepm is controlled from active controller..,1: sleepm controlled from SFR" newline bitfld.long 0x4 25. "OVERRIDE_SUSPENDM_SFR,SFR suspendm control. Value this bit is passed to PHY suspendm signal. This bit is valid only with PORT_OVERRIDE. override_suspendm_sel set to '1'." "0,1" newline bitfld.long 0x4 24. "OVERRIDE_SUSPENDM_SEL,suspendm override select. This register allows SW driver override suspendm pin as follows: 0: suspendm is controlled from active controller [host/device/none] 1: suspendm controlled from SFR" "0: suspendm is controlled from active controller..,1: suspendm controlled from SFR" newline bitfld.long 0x4 22.--23. "OVERRIDE_XCVRSEL_SFR,SFR xcvrselect control. Value of these bits is passed to PHY xcvrselect signal. This bit is valid only with PORT_OVERRRIDE. override_opmode_sel set to 1" "0,1,2,3" newline bitfld.long 0x4 21. "OVERRIDE_XCVRSEL_SEL,xcvrselect override select. This register allows SW driver override xcvrselect pin as follows: 0: xcvrselect is controlled from active controller [host/device] 1: xcvrselect controlled from SFR" "0: xcvrselect is controlled from active controller..,1: xcvrselect controlled from SFR" newline bitfld.long 0x4 20. "OVERRIDE_TXBITSTUFF_SFR,SFR txbitstuffenable control. Value this bit is passed to PHY txbitstuffenable signal. This bit is valid only with PORT_OVERRRIDE. override_txbitstuff_sel set to 1." "0,1" newline bitfld.long 0x4 19. "OVERRIDE_TXBITSTUFF_SEL,txbitstuffenable override select. This register allows SW driver override txbitstuffenable pin as follows: 0: txbitstuffenable is controlled from active controller [host/device] 1: txbitstuffenable controlled from SFR" "0: txbitstuffenable is controlled from active..,1: txbitstuffenable controlled from SFR" newline bitfld.long 0x4 17.--18. "OVERRIDE_OPMODE_SFR,SFR opmode control. Value these bits is passed to PHY opmode signal. This bit is valid only with PORT_OVERRRIDE. override_opmode_sel set to 1." "0,1,2,3" newline bitfld.long 0x4 16. "OVERRIDE_OPMODE_SEL,opmode override select. This register allows SW driver override opmode pin as follows: 0: opmode is controlled from active controller [host/device] 1: opmode controlled from SFR" "0: opmode is controlled from active controller..,1: opmode controlled from SFR" newline bitfld.long 0x4 15. "OVERRIDE_TERMSEL_SFR,SFR overcurrent control. 0: overcurrent = 0 1: overcurrent = 1 This bit is valid only with PORT_OVERRRIDE.overcurrent_sel set to '1'. Note: overcurrent active state is low." "0: overcurrent = 0,1: overcurrent = 1 This bit is valid only with.." newline bitfld.long 0x4 14. "OVERRIDE_TERMSEL_SEL,termselect override select. This register allows SW driver override termselect pin as follows: 0: txbitstuffenable is controlled from active controller [host/device] 1: txbitstuffenable controlled from SFR" "0: txbitstuffenable is controlled from active..,1: txbitstuffenable controlled from SFR" newline bitfld.long 0x4 13. "OVERCURRENT_SFR,SFR termselect control. Value this bit is passed to PHY termselect signal. This bit is valid only with PORT_OVERRRIDE. override_termsel_sel set to 1." "0,1" newline bitfld.long 0x4 12. "OVERCURRENT_SEL,Overcurrent override select This register allows SW driver override overcurrent pin as follows: 0: overcurrent is controlled from external FAULT detector 1: overcurrent controlled from SFR" "0: overcurrent is controlled from external FAULT..,1: overcurrent controlled from SFR" newline bitfld.long 0x4 11. "SESS_VLD_SFR,SFR Vbusvalid/Sessvalid control. 0: Vbusvalid/Sessvalid = 0 1: Vbusvalid/Sessvalid = 1 This bit is valid only with PORT_OVERRRIDE.sess_vld_sel set to '1'." "0: Vbusvalid/Sessvalid = 0,1: Vbusvalid/Sessvalid = 1 This bit is valid only.." newline bitfld.long 0x4 10. "SESS_VLD_SEL,Vbusvalid/Sessvalid override select. This register allows SW driver override Vbusvalid/Sessvalid pins as follows: 0: Vbusvalid/Sessvalid are controlled from OTG PHY 1: Vbusvalid/Sessvalid are controlled from SFR" "0: Vbusvalid/Sessvalid are controlled from OTG PHY,1: Vbusvalid/Sessvalid are controlled from SFR" newline bitfld.long 0x4 9. "IDDIG_SFR,SFR iddig control. 0: iddig = 0 1: iddig = 1 This bit is valid only with PORT_OVERRRIDE.iddig_sel set to '1'." "0: iddig = 0,1: iddig = 1 This bit is valid only with.." newline bitfld.long 0x4 8. "IDDIG_SEL,IDDIG override select. This register allows SW driver override iddig pin as follows: 0: iddig is controlled from OTG PHY 1: iddig controlled from SFR" "0: iddig is controlled from OTG PHY,1: iddig controlled from SFR" newline rbitfld.long 0x4 7. "RSVD2,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." "0,1" newline bitfld.long 0x4 6. "DRIVE_VBUS_SFR,0: drive_vbus = 0 1: drive_vbus = 1 This bit is valid only with USB2_PORT_OVERRRIDE.drive_vbus_sel set to '1'. This bit is auto-cleared upon over-current condition. Over-current doesn't disable vbus forcing." "0: drive_vbus = 0,1: drive_vbus = 1 This bit is valid only with.." newline bitfld.long 0x4 5. "DRIVE_VBUS_SEL,This register allows SW driver take control over drive_vbus as follows: 0: drive_vbus controlled from OTG controller 1: drive_vbus controlled from SFR" "0: drive_vbus controlled from OTG controller,1: drive_vbus controlled from SFR" newline rbitfld.long 0x4 4. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." "0,1" newline bitfld.long 0x4 3. "BC_DMPULLDOWN,dmpulldown enable This bit is valid only with PORT_OVERRRIDE.pulldownctrl_sel set to 1" "0,1" newline bitfld.long 0x4 2. "BC_DPPULLDOWN,BC dppulldown enable This bit is valid only with PORT_OVERRRIDE.pulldownctrl_sel set to 1" "0,1" newline bitfld.long 0x4 1. "BC_PULLDOWNCTRL,pulldowncotrol 1: puldowns are controlled by dppulldown_sfr and dmpulldown_sfr 0: puldowns are controlled by OTG" "0: puldowns are controlled by OTG,1: puldowns are controlled by dppulldown_sfr and.." newline bitfld.long 0x4 0. "IDPULLUP,ID Pin Sample Enable: Active High. Signal that enables the sampling of the analog ID line. 0: Sampling of ID pin is disabled iddig is not valid 1: Sampling of ID pin is enabled" "0: Sampling of ID pin is disabled,1: Sampling of ID pin is enabled" line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_SUSP_CTRL,SUSP_TIMING_CTRL. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for informative purposes." hexmask.long.word 0x8 20.--31. 1. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline rbitfld.long 0x8 19. "SUSPEND_DELAY_CAPABILITY,Suspend delay capability. This is a configuration only field therefore it can be changed by Software only during configuration phase when Power-On Reset [pwrup_rst_n] is asserted." "0,1" newline bitfld.long 0x8 18. "SLEEP_RESIDENCY_ENABLE,sleep minimum residency enable. This is a configuration only field therefore it can be changed by Software only during configuration phase when Power-On Reset [pwrup_rst_n] is asserted." "0,1" newline bitfld.long 0x8 17. "SUSPEND_RESIDENCY_ENABLE,suspend minimum residency enable. This is a configuration only field therefore it can be changed by Software only during configuration phase when Power-On Reset [pwrup_rst_n] is asserted." "0,1" newline bitfld.long 0x8 16. "SUSPEND_DELAY_ENABLE,suspend delay enable. This is a configuration only field therefore it can be changed by Software only during configuration phase when Power-On Reset [pwrup_rst_n] is asserted." "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "SUSPEND_RESIDENCY,Suspend/Sleep minimum residency time [us]. This is a configuration only field therefore it can be changed by Software only during configuration phase when Power-On Reset [pwrup_rst_n] is asserted." newline hexmask.long.byte 0x8 0.--7. 1. "SUSPEND_DELAY,Suspend assertion delay time [us]. This is a configuration only field therefore it can be changed by Software only during configuration phase when Power-On Reset [pwrup_rst_n] is asserted." line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_PHYRST_CFG,USB20 PHY reset workaround config" hexmask.long.byte 0xC 25.--31. 1. "RSVD3,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline bitfld.long 0xC 24. "PHYRST_SFR_RST,Software USB20 PHy reset: 0 - SW utmi_reset not asserted 1 - SW utmi_reset asserted" "0: SW utmi_reset not asserted 1,?" newline hexmask.long.word 0xC 13.--23. 1. "RSVD2,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline hexmask.long.byte 0xC 8.--12. 1. "PHYRST_A_VALUE,phyrst_a Rx fail timeout value. Value of this register is used as a timeout value for detecting Rx fail [utmi_rxactive is not up during Rx] Value of this register represent maximum number of UTMI clock cycles where.." newline hexmask.long.byte 0xC 4.--7. 1. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline bitfld.long 0xC 3. "PHYRST_D_ENABLE,Reset PHY after each utmi_opmode change from 2'b10 to any other value: 0 - disabled 1 - enabled" "0: disabled 1,?" newline bitfld.long 0xC 2. "PHYRST_C_ENABLE,Reset PHY after each utmi_opmode change from 2'b01 to any other value: 0 - disabled 1 - enabled" "0: disabled 1,?" newline bitfld.long 0xC 1. "PHYRST_B_ENABLE,Reset PHY after each transmitted packet in High-Speed: 0 - disabled 1 - enabled" "0: disabled 1,?" newline bitfld.long 0xC 0. "PHYRST_A_ENABLE,Reset PHY if Rx fail is detected: 0 - disabled 1 - enabled" "0: disabled 1,?" rgroup.long 0x50++0x7 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_OTGANASTS,OTGADPBCSTS" hexmask.long.byte 0x0 25.--31. 1. "RSVD2,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline bitfld.long 0x0 24. "ADP_CHRG_TMOUT_DET,ADP charge timeout detected" "0,1" newline bitfld.long 0x0 21.--23. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RID_A,RID A status reg" "0,1" newline bitfld.long 0x0 19. "RID_B,RID B status reg" "0,1" newline bitfld.long 0x0 18. "RID_C,RID C status reg" "0,1" newline bitfld.long 0x0 17. "RID_GND,RID GND status reg" "0,1" newline bitfld.long 0x0 16. "RID_FLOAT,RID float status reg" "0,1" newline bitfld.long 0x0 14.--15. "LINESTATE,Line State: These signals reflect the current state of the single ended receivers. They are combinatorial until a 'usable' sieclock is available then they are synchronized to sieclock. They reflect the current state of.." "0: SE0 [Single Ended Zero] 01: 'J' State 10: 'K'..,?,?,?" newline bitfld.long 0x0 13. "IDDIG,ID Pin Status: Indicates whether the connected USB plug is Micro-A or Micro-B. This is only valid when idpullup is set to '1'. It must be valid within 50ms after idpullup is set to '1'. 0: Connected plug is a Micro-A.." "0: Connected plug is a Micro-A,1: Connected plug is a Micro-B" newline bitfld.long 0x0 12. "RID_A_COMP_STS,RID A comparator status 1: RID_A Detected on ID Pin 0: RID_A not Detected on ID Pin" "0: RID_A not Detected on ID Pin,1: RID_A Detected on ID Pin" newline bitfld.long 0x0 11. "RID_B_COMP_STS,RID B comparator status 1: RID_B Detected on ID Pin 0: RID_B not Detected on ID Pin" "0: RID_B not Detected on ID Pin,1: RID_B Detected on ID Pin" newline bitfld.long 0x0 10. "RID_C_COMP_STS,RID C comparator status 1: RID_C Detected on ID Pin 0: RID_C not Detected on ID Pin" "0: RID_C not Detected on ID Pin,1: RID_C Detected on ID Pin" newline bitfld.long 0x0 9. "RID_GND_COMP_STS,RID GND comparator status 1: RID_GND Detected on ID Pin 0: RID_GND not Detected on ID Pin" "0: RID_GND not Detected on ID Pin,1: RID_GND Detected on ID Pin" newline bitfld.long 0x0 8. "RID_FLOAT_COMP_STS,RID float comparator status 1: RID_FLOAT Detected on ID Pin 0: RID_FLOAT not Detected on ID Pin" "0: RID_FLOAT not Detected on ID Pin,1: RID_FLOAT Detected on ID Pin" newline bitfld.long 0x0 7. "SESSEND,VBUS Valid: Indicates if the voltage on VBUS is at a valid level for operation [4.4V less than VTH less than 4.75V]. 0: VBUS less than 4.4V 1: VBUS > 4.75V" "0: VBUS less than 4,1: VBUS > 4" newline bitfld.long 0x0 6. "ADP_SENSE_ANA,Output of ADP Sense Comparator. 0: VBUS less than 0.2V 1: VBUS > 0.55V" "0: VBUS less than 0,1: VBUS > 0" newline bitfld.long 0x0 5. "ADP_PROBE_ANA,Output of ADP Probe Comparator. 0: VBUS less than 0.6V 1: VBUS > 0.75V" "0: VBUS less than 0,1: VBUS > 0" newline bitfld.long 0x0 4. "OTGSESSVALID,B-Peripheral is Valid: Indicates if the session for a B-Peripheral is valid [0.8V less than VTH less than 4.0V]. The signal bvalid from OTG 1.3 is now renamed as otgsessvalid. 0: VBUS less than 0.8V 1:.." "0: VBUS less than 0,1: VBUS > 4" newline bitfld.long 0x0 3. "DCD_COMP_STS,Data Contact Detect [DCD] Comparator Status 1: DP line is asserted 0: DP line is not asserted" "0: DP line is not asserted,1: DP line is asserted" newline bitfld.long 0x0 2. "DM_VLGC_COMP_STS,1: DM > VLGC Detected 0: DM less than VLGC Detected Note: This status shall be re-used from the single ended receiver output of D- whenever dm_vlgc_comp_en is '1'." "0: DM less than VLGC Detected Note: This status..,1: DM > VLGC Detected" newline bitfld.long 0x0 1. "DM_VDAT_REF_COMP_STS,1: DM > VDAT_REF Detected 0: DM less than VDAT_REF Detected Note: This status shall be re-used from the single ended receiver output of D- whenever dm_vdat_ref_comp_en is '1'." "0: DM less than VDAT_REF Detected Note: This status..,1: DM > VDAT_REF Detected" newline bitfld.long 0x0 0. "DP_VDAT_REF_COMP_STS,1: DP > VDAT_REF Detected 0: DP less than VDAT_REF Detected Note: This status shall be re-used from the single ended receiver output of D+ whenever dp_vdat_ref_comp_en is '1'." "0: DP less than VDAT_REF Detected Note: This status..,1: DP > VDAT_REF Detected" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ADP_RAMP_TIME,ADP_RAMP_TIME" hexmask.long 0x4 0.--31. 1. "ADP_RAMP_TIME,ADP ramp time measurement value. Software should read this register upon ADP_PROBE_COMPLETED_INT_EN interrupt detection" rgroup.long 0x58++0x13 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_OTGCTRL1,OTGCTRL1" hexmask.long.word 0x0 21.--31. 1. "RSVD2,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline bitfld.long 0x0 20. "RID_NONFLOAT_COMP_EN,1: RID Non-Float Comparator Enabled 0: RID Non-Float Comparator Disabled Note: This ID Comparator enable is used to detect the presence of RID_A or RID_B or RID_C or RID_GND when the ID pin is.." "0: RID Non-Float Comparator Disabled Note: This ID..,1: RID Non-Float Comparator Enabled" newline bitfld.long 0x0 19. "RID_FLOAT_COMP_EN,1: RID Float Comparator Enabled 0: RID Float Comparator Disabled Note: This ID Comparator enable is used to detect whether the ID line is floating or non-floating. If it is identified to be.." "0: RID Float Comparator Disabled Note: This ID..,1: RID Float Comparator Enabled" newline bitfld.long 0x0 18. "DP_VDAT_REF_COMP_EN,1: DP to VDAT_REF Comparator Enabled 0: DP to VDAT_REF Comparator Disabled" "0: DP to VDAT_REF Comparator Disabled,1: DP to VDAT_REF Comparator Enabled" newline bitfld.long 0x0 17. "DM_VLGC_COMP_EN,1: DM to VLGC Comparator Enabled 0: DM to VLGC Comparator Disabled" "0: DM to VLGC Comparator Disabled,1: DM to VLGC Comparator Enabled" newline bitfld.long 0x0 16. "DM_VDAT_REF_COMP_EN,1: DM to VDAT_REF Comparator Enabled 0: DM to VDAT_REF Comparator Disabled" "0: DM to VDAT_REF Comparator Disabled,1: DM to VDAT_REF Comparator Enabled" newline rbitfld.long 0x0 14.--15. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." "0,1,2,3" newline bitfld.long 0x0 13. "VDP_SRC_EN,1: Voltage Source on DP Enabled 0: Voltage Source on DP Disabled" "0: Voltage Source on DP Disabled,1: Voltage Source on DP Enabled" newline bitfld.long 0x0 12. "VDM_SRC_EN,1: Voltage Source on DM Enabled 0: Voltage Source on DM Disabled" "0: Voltage Source on DM Disabled,1: Voltage Source on DM Enabled" newline bitfld.long 0x0 11. "IDP_SRC_EN,1: Current Source on DP Enabled 0: Current Source on DP Disabled" "0: Current Source on DP Disabled,1: Current Source on DP Enabled" newline bitfld.long 0x0 10. "IDP_SINK_EN,1: Current Sink on DP Enabled 0: Current Sink on DP Disabled" "0: Current Sink on DP Disabled,1: Current Sink on DP Enabled" newline bitfld.long 0x0 9. "IDM_SINK_EN,1: Current Sink on DM Enabled 0: Current Sink on DM Disabled" "0: Current Sink on DM Disabled,1: Current Sink on DM Enabled" newline bitfld.long 0x0 8. "BC_EN,Battery Charging Circuits Master Enable. 1: BC Enabled 0: BC Disabled" "0: BC Disabled,1: BC Enabled" newline bitfld.long 0x0 7. "ADP_AUTO,ADP mode. If set to 1 ADP probing is controlled by internal FSM. If set to 0 then software should control ADP sequence." "0,1" newline bitfld.long 0x0 6. "DO_ADP_SNS,ADP sensing enable in automated mode" "0,1" newline bitfld.long 0x0 5. "DO_ADP_PRB,ADP probing enable in automated mode" "0,1" newline bitfld.long 0x0 4. "ADP_SOURCE_CURRENT_EN,When this signal is high VBUS is charged to the probe threshold [0.75V]. This signal should be asserted 5us after the assertion of adp_en. 0: ADP Source Current Enable OFF 1: ADP Source Current.." "0: ADP Source Current Enable OFF,1: ADP Source Current Enable ON" newline bitfld.long 0x0 3. "ADP_SINK_CURRENT_EN,When this signal is high VBUS is discharged to ground. This signal should be asserted 5us after the assertion of adp_en. 0: ADP Sink Current Enable OFF 1: ADP Sink Current Enable ON" "0: ADP Sink Current Enable OFF,1: ADP Sink Current Enable ON" newline bitfld.long 0x0 2. "ADP_SENSE_EN,This signal enables the probe mode of the ADP. During this mode sense comparators and the current sources will be ON based on the source and sink current enables. 0: ADP Probe Sense OFF 1: ADP Probe Sense.." "0: ADP Probe Sense OFF,1: ADP Probe Sense ON" newline bitfld.long 0x0 1. "ADP_PROBE_EN,This signal enables the probe mode of the ADP. During this mode probe comparators and the current sources will be ON based on the source and sink current enables. 0: ADP Probe Mode OFF 1: ADP Probe Mode ON" "0: ADP Probe Mode OFF,1: ADP Probe Mode ON" newline bitfld.long 0x0 0. "ADP_EN,ADP Feature Enable. This signal is the master enable for all the ADP PHY logics. 0: ADP Logics are powered OFF 1: ADP Logics are powered ON" "0: ADP Logics are powered OFF,1: ADP Logics are powered ON" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_OTGCTRL2,OTGCTRL2" hexmask.long.byte 0x4 24.--31. 1. "T_ADP_DSCHG,ADP probing discharge time. T_ADP_DSCHG = {reg_value} * 1 ms" newline hexmask.long.byte 0x4 16.--23. 1. "ADP_CHRG_TMOUT,ADP probing timeout value. Defines maximum time for ADP charging. If this time is reached during charging then adp_chrg_tmout_det bit in OTGADPBCSTS is set ADP_CHRG_TMOUT = {reg_value} * 1 ms" newline hexmask.long.byte 0x4 8.--15. 1. "TB_ADP_PRB,B-device ADP probing period. TB_ADP_PRB = {reg_value} * 10 ms" newline hexmask.long.byte 0x4 0.--7. 1. "TA_ADP_PRB,A-device ADP probing period. TA_ADP_PRB = {reg_value} * 10 ms" line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_VBUSVALID_DBNC_CFG,VBUSVALID_DBNC_CFG" bitfld.long 0x8 31. "VBUSVALID_DBNC_DIS,Vbusvalid debounce disable" "0,1" newline hexmask.long.byte 0x8 26.--30. 1. "RSVD2,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline hexmask.long.word 0x8 16.--25. 1. "VBUSVALID_FALL_DBNC_VAL,Vbusvalid off debounce: Debounce timer value = reg value x 100us" newline hexmask.long.byte 0x8 10.--15. 1. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline hexmask.long.word 0x8 0.--9. 1. "VBUSVALID_RISE_DBNC_VAL,Vbusvalid on debounce: Debounce timer value = reg value x 100us" line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_SESSVALID_DBNC_CFG,SESSVALID_DBNC_CFG" bitfld.long 0xC 31. "SESSVALID_DBNC_DIS,Sessvalid debounce disable" "0,1" newline hexmask.long.byte 0xC 26.--30. 1. "RSVD2,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline hexmask.long.word 0xC 16.--25. 1. "SESSVALID_OFF_DBNC_VAL,Sessvalid off debounce: Debounce timer value = reg value x 100us" newline hexmask.long.byte 0xC 10.--15. 1. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline hexmask.long.word 0xC 0.--9. 1. "SESSVALID_ON_DBNC_VAL,Sessvalid on debounce: Debounce timer value = reg value x 100us" line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_IDDIG_DBNC_CFG,IDDIG_DBNC_CFG" bitfld.long 0x10 31. "IDDIG_DBNC_DIS,Iddig debounce disable" "0,1" newline hexmask.long.byte 0x10 26.--30. 1. "RSVD2,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline hexmask.long.word 0x10 16.--25. 1. "IDDIG_OFF_DBNC_VAL,Sessvalid off debounce: Debounce timer value = reg value x 100us" newline hexmask.long.byte 0x10 10.--15. 1. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline hexmask.long.word 0x10 0.--9. 1. "IDDIG_ON_DBNC_VAL,Sessvalid on debounce: Debounce timer value = reg value x 100us" rgroup.long 0x8C++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_DB_ASF_MEM_MASK,Cadence Device ID Register" hexmask.long 0x0 0.--31. 1. "DB_ASF_MEM_MASK,Debug Feature. 0-DISABLE/1-ENABLE ECC check for memories" rgroup.long 0x100++0x13 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_asf_int_status,ASF Interrupt Status Register. This register indicates the source of ASF interrupts. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this.." hexmask.long 0x0 5.--31. 1. "RSVD2,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline bitfld.long 0x0 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1" newline rbitfld.long 0x0 2.--3. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." "0,1,2,3" newline bitfld.long 0x0 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x0 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_asf_int_raw_status,ASF Interrupt Raw Status Register. A bit set in this raw register indicates a source of ASF fault in the correspoding feature. Writing to either raw or masked status registers. clear both.." hexmask.long 0x4 5.--31. 1. "RSVD2,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline bitfld.long 0x4 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1" newline rbitfld.long 0x4 2.--3. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." "0,1,2,3" newline bitfld.long 0x4 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x4 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1" line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_asf_int_mask,The ASF interrupt mask register indicating which interrupt bits in the ASF interrupt status register are masked. All bits are set at reset. Clear the individual bit to enable the corresponding.." hexmask.long 0x8 5.--31. 1. "RSVD2,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline bitfld.long 0x8 4. "ASF_TRANS_TO_ERR_MASK,Mask bit for transaction timeouts error interrupt." "0,1" newline rbitfld.long 0x8 2.--3. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." "0,1,2,3" newline bitfld.long 0x8 1. "ASF_SRAM_UNCORR_ERR_MASK,Mask bit for SRAM uncorrectable error interrupt." "0,1" newline bitfld.long 0x8 0. "ASF_SRAM_CORR_ERR_MASK,Mask bit for SRAM correctable error interrupt." "0,1" line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_asf_int_test,The ASF interrupt test register emulate hardware even. Write one to individual bit to trigger single event in (masked and raw) status registers according to mask and will generate interrrupt.." hexmask.long 0xC 5.--31. 1. "RSVD2,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline bitfld.long 0xC 4. "ASF_TRANS_TO_ERR_TEST,Test bit for transaction timeouts error interrupt." "0,1" newline rbitfld.long 0xC 2.--3. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." "0,1,2,3" newline bitfld.long 0xC 1. "ASF_SRAM_UNCORR_ERR_TEST,Test bit for SRAM uncorrectable error interrupt." "0,1" newline bitfld.long 0xC 0. "ASF_SRAM_CORR_ERR_TEST,Test bit for SRAM correctable error interrupt." "0,1" line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_asf_fatal_nonfatal_select,The fatal or non-fatal interrupt register selects whether a fatal (asf_int_fatal) or non-fatal (asf_int_nonfatal) interrupt is triggered. If the bit of the event will be set to one.." hexmask.long 0x10 5.--31. 1. "RSVD2,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline bitfld.long 0x10 4. "ASF_TRANS_TO_ERR,Enable transaction timeouts error interrupt as fatal." "0,1" newline rbitfld.long 0x10 2.--3. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." "0,1,2,3" newline bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR,Enable SRAM uncorrectable error interrupt as fatal." "0,1" newline bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR,Enable SRAM correctable error interrupt as fatal." "0,1" rgroup.long 0x114++0x13 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_RSVD_6_ASF,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the.." hexmask.long 0x0 0.--31. 1. "RSVD_1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_RSVD_7_ASF,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the.." hexmask.long 0x4 0.--31. 1. "RSVD_1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_RSVD_8_ASF,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the.." hexmask.long 0x8 0.--31. 1. "RSVD_1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_asf_sram_corr_fault_status,Status register for SRAM correctable fault. These fields are updated whenever asf_sram_corr_fault input is active." hexmask.long.byte 0xC 24.--31. 1. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault." newline hexmask.long.tbyte 0xC 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault." line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_asf_sram_uncorr_fault_status,Status register for SRAM uncorrectable fault. These fields are updated whenever asf_sram_uncorr_fault input is active." hexmask.long.byte 0x10 24.--31. 1. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault." newline hexmask.long.tbyte 0x10 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault." rgroup.long 0x128++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_asf_sram_fault_stats,Statistics register for SRAM faults. Note that this register clears when software writes to any field." hexmask.long.word 0x0 16.--31. 1. "ASF_SRAM_FAULT_UNCORR_STATS,Count of number of uncorrectable errors if implemented. Count value will saturate at 0xffff." newline hexmask.long.word 0x0 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS,Count of number of correctable errors if implemented. Count value will saturate at 0xffff." rgroup.long 0x12C++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_RSVD_12_ASF,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the.." hexmask.long 0x0 0.--31. 1. "RSVD_1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." rgroup.long 0x130++0xB line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_asf_trans_to_ctrl,Control register to configure the ASF transaction timeout monitors." bitfld.long 0x0 31. "ASF_TRANS_TO_EN,Enable transaction timeout monitoring." "0,1" newline hexmask.long.word 0x0 16.--30. 1. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline hexmask.long.word 0x0 0.--15. 1. "ASF_TRANS_TO_CTRL,Timer value to use for transaction timeout monitor." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_asf_trans_to_fault_mask,Control register to mask out ASF transaction timeout faults from triggering interrupts. On reset. all bits are set to mask out all sources. Clear the corresponding bit to enable the.." hexmask.long 0x4 0.--31. 1. "ASF_TRANS_TO_FAULT_MASK,Mask register for each ASF transaction timeout fault source." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_asf_trans_to_fault_status,Status register for transaction timeouts fault. If a fault occurs the relevant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit." hexmask.long 0x8 6.--31. 1. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline bitfld.long 0x8 5. "ASF_TRANS_TIMEOUT_BAXI,Status bits for transaction timeouts faults - AXI Timeout [BAXI]" "0,1" newline bitfld.long 0x8 4. "ASF_TRANS_TIMEOUT_RAXI,Status bits for transaction timeouts faults - AXI Timeout [RAXI]" "0,1" newline bitfld.long 0x8 3. "ASF_TRANS_TIMEOUT_ARAXI,Status bits for transaction timeouts faults - AXI Timeout [ARAXI]" "0,1" newline bitfld.long 0x8 2. "ASF_TRANS_TIMEOUT_WAXI,Status bits for transaction timeouts faults - AXI Timeout [WAXI]" "0,1" newline bitfld.long 0x8 1. "ASF_TRANS_TIMEOUT_AWAXI,Status bits for transaction timeouts faults - AXI Timeout [AWAXI]" "0,1" newline bitfld.long 0x8 0. "ASF_TRANS_TIMEOUT_APB,Status bit for transaction timeout faults - APB timeout." "0,1" rgroup.long 0x13C++0xB line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_RSVD_16_ASF,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the.." hexmask.long 0x0 0.--31. 1. "RSVD_1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_RSVD_17_ASF,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the.." hexmask.long 0x4 0.--31. 1. "RSVD_1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_RSVD_18_ASF,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the.." hexmask.long 0x8 0.--31. 1. "RSVD_1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." rgroup.long 0x10000++0x23 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_HCIVERSION_CAPLENGTH,HCIVERSION_CAPLENGTH" hexmask.long.word 0x0 16.--31. 1. "HCIVERSION,Host Controller Interface Version Number [HCIVERSION]. This is a two-byte register containing a BCD encoding of the xHCI specification revision number supported by this host controller. The most significant byte of this register.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline hexmask.long.byte 0x0 0.--7. 1. "CAPLENGTH,Capability Registers Length [CAPLENGTH]. This register is used as an offset to add to register base to find the beginning of the Operational Register Space." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_HCSPARAMS1,Structural Parameters 1 (HCSPARAMS1). This register defines basic structural parameters supported by this xHC implementation: Number of Device Slots support. Interrupters. Root Hub ports." hexmask.long.byte 0x4 24.--31. 1. "MAXPORTS,Number of Ports [MaxPorts]. This field specifies the maximum Port Number value i.e. the highest numbered Port Register Set that are addressable in the Operational Register Space. Valid values are in the range of 1h to FFh. The.." newline hexmask.long.byte 0x4 19.--23. 1. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline hexmask.long.word 0x4 8.--18. 1. "MAXINTRS,Number of Interrupters [MaxIntrs]. This field specifies the number of Interrupters implemented on this host controller. Each Interrupter may be allocated to a MSI or MSI-X vector and controls its generation and moderation. The value.." newline hexmask.long.byte 0x4 0.--7. 1. "MAXSLOTS,Number of Device Slots [MaxSlots]. This field specifies the maximum number of Device Context Structures and Doorbell Array entries this host controller can support. Valid values are in the range of 1 to 255. The value of 0 is reserved." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_HCSPARAMS2,Structural Parameters 2 (HCSPARAMS 2). This register defines additional xHC structural parameters." hexmask.long.byte 0x8 27.--31. 1. "MAXSPBUFLO,Max Scratchpad Buffers [Max Scratchpad Bufs Lo]. Default = implementation dependent. Valid values for Max Scratchpad Buffers [Hi and Lo] are 0-1023. This field indicates the low order 5 bits of the number of Scratchpad Buffers.." newline bitfld.long 0x8 26. "SPR,Scratchpad Restore [SPR]. Default = implementation dependent. If Max Scratchpad Buffers is > 0 then this flag indicates whether the xHC uses the Scratchpad Buffers for saving state when executing Save and Restore State operations. If Max Scratchpad.." "0,1" newline hexmask.long.byte 0x8 21.--25. 1. "MAXSPBUFHI,Max Scratchpad Buffers [Max Scratchpad Bufs Hi]. Default = implementation dependent. This field indicates the high order 5 bits of the number of Scratchpad Buffers system software shall reserve for the xHC. Refer to section 4.20 of.." newline hexmask.long.word 0x8 8.--20. 1. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline hexmask.long.byte 0x8 4.--7. 1. "ERSTMAX,Event Ring Segment Table Max [ERST Max]. Default = implementation dependent. Valid values are 0-15. This field determines the maximum value supported the Event Ring Segment Table Base Size registers [5.5.2.3.1] where: The maximum.." newline hexmask.long.byte 0x8 0.--3. 1. "IST,Isochronous Scheduling Threshold [IST]. Default = implementation dependent. The value in this field indicates to system software the minimum distance [in time] that it is required to stay ahead of the host controller while adding TRBs in order to.." line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_HCSPARAMS3,Structural Parameters 3 (HCSPARAMS3). This register defines link exit latency related structural parameters." hexmask.long.word 0xC 16.--31. 1. "U2DEVEXITLAT,U2 Device Exit Latency. Worst case latency to transition from U2 to U0. Applies to all root hub ports. The following are permissible values: 0000h Zero 0001h Less than 1 s. 0002h Less than.." newline hexmask.long.byte 0xC 8.--15. 1. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline hexmask.long.byte 0xC 0.--7. 1. "U1DEVEXITLAT,U1 Device Exit Latency. Worst case latency to transition a root hub Port Link State [PLS] from U1 to U0. Applies to all root hub ports. The following are permissible values: 00h Zero 01h Less than 1.." line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_HCCPARAMS,Capability Parameters (HCCPARAMS). This register defines optional capabilities supported by the xHCI. The default values for all fields in this register are implementation dependent." hexmask.long.word 0x10 16.--31. 1. "XECP,xHCI Extended Capabilities Pointer [xECP]. This field indicates the existence of a capabilities list. The value of this field indicates a relative offset in 32-bit words from Base to the beginning of the first extended capability. For example .." newline hexmask.long.byte 0x10 12.--15. 1. "MAXPSASIZE,Maximum Primary Stream Array Size [MaxPSASize]. This fields identifies the maximum size Primary Stream Array that the xHC supports. The Primary Stream Array size = 2^[MaxPSASize+1]. Valid MaxPSASize values are 0 to 15 where 0 indicates that.." newline bitfld.long 0x10 10.--11. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." "0,1,2,3" newline bitfld.long 0x10 9. "SPC,Stopped - Short Packet Capability [SPC]. This flag indicates that the host controller implementation is capable of generating a Stopped - Short Packet Completion Code. Refer to section 4.6.9 of xHCI specification for more information." "0,1" newline bitfld.long 0x10 8. "PAE,Parse All Event Data [PAE]. This flag indicates whether the host controller implementation Parses all Event Data TRBs while advancing to the next TD after a Short Packet or it skips all but the first Event Data TRB. A '1' in this bit indicates that.." "0,1" newline bitfld.long 0x10 7. "NSS,No Secondary SID Support [NSS]. This flag indicates whether the host controller implementation supports Secondary Stream IDs. A '1'in this bit indicates that Secondary Stream ID decoding is not supported. A '0' in this bit indicates that Secondary.." "0,1" newline bitfld.long 0x10 6. "LTC,Latency Tolerance Messaging Capability [LTC]. This flag indicates whether the host controller implementation supports Latency Tolerance Messaging [LTM]. A '1' in this bit indicates that LTM is supported. A 0 in this bit indicates that LTM is not.." "0,1" newline bitfld.long 0x10 5. "LHRC,Light HC Reset Capability [LHRC]. This flag indicates whether the host controller implementation supports a Light Host Controller Reset. A '1' in this bit indicates that Light Host Controller Reset is supported. A '0' in this bit indicates that.." "0,1" newline bitfld.long 0x10 4. "PIND,Port Indicators [PIND]. This bit indicates whether the xHC root hub ports support port indicator control. When this bit is a '1' the port status and control registers include a read/writeable field for controlling the state of the port indicator." "0,1" newline bitfld.long 0x10 3. "PPC,Port Power Control [PPC]. This flag indicates whether the host controller implementation includes port power control. A '1' in this bit indicates the ports have port power switches. A '0' in this bit indicates the port do not have port power.." "0,1" newline bitfld.long 0x10 2. "CSZ,Context Size [CSZ]. If this bit is set to '1' then the xHC uses 64 byte Context data structures. If this bit is cleared to 0 then the xHC uses 32 byte Context data structures. Note: This flag does not apply to Stream Contexts." "0,1" newline bitfld.long 0x10 1. "BNC,BW Negotiation Capability [BNC]. This flag identifies whether the xHC has implemented the Bandwidth Negotiation. Values for this flag have the following interpretation: '0': BW Negotiation not implemented '1': BW.." "0,1" newline bitfld.long 0x10 0. "AC64,64-bit Addressing Capability [AC64]. This flag documents the addressing range capability of this implementation. The value of this flag determines whether the xHC has implemented the high order 32 bits of 64 bit register and data structure pointer.." "0,1" line.long 0x14 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_DBOFF,This register defines the offset of the Doorbell Array base address from the Base." hexmask.long 0x14 2.--31. 1. "DAO,Doorbell Array Offset RO. Default = implementation dependent. This field defines the offset in Dwords of the Doorbell Array base address from the Base [i.e. the base address of the xHCI Capability register address space]." newline bitfld.long 0x14 0.--1. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." "0,1,2,3" line.long 0x18 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_RTSOFF,This register defines the offset of the xHCI Runtime Registers from the Base." hexmask.long 0x18 5.--31. 1. "RRSO,Runtime Register Space Offset RO. Default = implementation dependent. This field defines the 32-byte offset of the xHCI Runtime Registers from the Base. i.e. Runtime Register Base Address = Base + Runtime Register Set Offset." newline hexmask.long.byte 0x18 0.--4. 1. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." line.long 0x1C "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_HCCPARAMS2,Capability Parameters 2 (HCCPARAMS2). This register defines optional capabilities supported by the xHCI. The default values for all fields in this register are implementation dependent." hexmask.long 0x1C 4.--31. 1. "RSVD2,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline bitfld.long 0x1C 3. "CTC,This bit indicates whether the xHC USB3 Root Hub ports support the Compliance Transition Enabled [CTE] flag. When this bit is 1 USB3 Root Hub port state machine transitions to the Compliance substate shall be explicitly enabled software. When this.." "0,1" newline bitfld.long 0x1C 0.--2. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." "0,1,2,3,4,5,6,7" line.long 0x20 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_RSVD_CR,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value.." hexmask.long 0x20 0.--31. 1. "RSVD_1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." rgroup.long 0x10080++0x7 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_USBCMD,USB Command Register (USBCMD). The Command Register indicates the command to be executed by the serial bus host controller. Writing to the register causes a command to be executed." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP2,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline bitfld.long 0x0 11. "EU3S,Enable U3 MFINDEX Stop [EU3S] RW. Default = '0'. When set to '1' the xHC may stop the MFINDEX counting action if all Root Hub ports are in the U3 Disconnected Disabled or Powered-off state. When cleared to '0' the xHC may stop the MFINDEX.." "0,1" newline bitfld.long 0x0 10. "EWE,Enable Wrap Event [EWE] RW. Default = '0'. When set to '1' the xHC shall generate a MFINDEX Wrap Event every time the MFINDEX register transitions from 03FFFh to 0. When cleared to '0' no MFINDEX Wrap Events are generated. Refer to section 4.14.2.." "0,1" newline bitfld.long 0x0 9. "CRS,Controller Restore State [CRS] RW. Default = '0'. When set to '1' and HCHalted [HCH] = '1' then the xHC shall perform a Restore State operation and restore its internal state. When set to '1' and Run/Stop [R/S] = '1' or HCHalted [HCH] = '0' or.." "0,1" newline bitfld.long 0x0 8. "CSS,Controller Save State [CSS] RW. Default = '0'. When written by software with '1' and HCHalted [HCH] = '1' then the xHC shall save any internal state that may be restored by a subsequent Restore State operation. When written by software with '1' and.." "0,1" newline rbitfld.long 0x0 7. "LHCRST,Light Host Controller Reset [LHCRST] RO or RW. Optional normative. Default = '0'. If the Light HC Reset Capability [LHRC] bit in the HCCPARAMS register is '1' then this flag allows the driver to reset the xHC without affecting the.." "0,1" newline rbitfld.long 0x0 4.--6. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "HSEE,Host System Error Enable [HSEE] RW. Default = '0'. When this bit is a '1' and the HSE bit in the USBSTS register is a '1' the xHC shall assert out-of-band error signaling to the host. The signaling is.." "0,1" newline bitfld.long 0x0 2. "INTE,Interrupter Enable [INTE] RW. Default = '0'. This bit provides system software with a means of enabling or disabling the host system interrupts generated by Interrupters. When this bit is a '1' then Interrupter host system interrupt generation is.." "0,1" newline bitfld.long 0x0 1. "HCRST,Host Controller Reset [HCRST] RW. Default = '0'. This control bit is used by software to reset the host controller. The effects of this bit on the xHC and the Root Hub registers are similar to a Chip Hardware Reset. When software writes a '1' to.." "0,1" newline bitfld.long 0x0 0. "R_S,Run/Stop [R/S] RW. Default = '0'. '1' = Run. '0' = Stop. When set to a '1' the xHC proceeds with execution of the schedule. The xHC continues execution as long as this bit is set to a '1'. When this bit is cleared to '0' the xHC.." "0,1" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_USBSTS,USB Status Register (USBSTS). This register indicates pending interrupts and various states of the Host Controller. The status resulting from a transaction on the serial bus is not indicated in this.." hexmask.long.tbyte 0x4 13.--31. 1. "RSVDP,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline rbitfld.long 0x4 12. "HCE,Host Controller Error [HCE] RO. Default = '0'. '0' = No internal xHC error conditions exist and '1' = Internal xHC error condition. This flag shall be set to indicate that an internal error condition has been detected which requires software to.." "0,1" newline rbitfld.long 0x4 11. "CNR,Controller Not Ready [CNR] RO. Default = '1'. '0' = Ready and '1' = Not Ready. When this bit is '1' software shall not read or write any register of the xHC other than those explicitly listed in the Design Specification section titled Register.." "0,1" newline bitfld.long 0x4 10. "SRE,Save/Restore Error [SRE] RW1C. Default = '0'. If an error occurs during a Save or Restore operation this bit shall be set to '1'. This bit shall be cleared to '0' when a Save or Restore operation is initiated or when written with '1'. Refer to.." "0,1" newline rbitfld.long 0x4 9. "RSS,Restore State Status [RSS] RO. Default = '0'. When the Controller Restore State [CRS] flag in the USBCMD register is written with '1' this bit shall be set to '1' and remain '1' while the xHC restores its internal state. When the Restore State.." "0,1" newline rbitfld.long 0x4 8. "SSS,Save State Status [SSS] RO. Default = '0'. When the Controller Save State [CSS] flag in the USBCMD register is written with '1' this bit shall be set to '1' and remain '1' while the xHC saves its internal state. When the Save State operation is.." "0,1" newline rbitfld.long 0x4 5.--7. "RSVDZ2,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4. "PCD,Port Change Detect [PCD] RW1C. Default = '0'. The xHC sets this bit to a '1' when any port has a change bit transition from a '0' to a '1'. This bit is allowed to be maintained in the Aux Power well. Alternatively it is also acceptable that on a.." "0,1" newline bitfld.long 0x4 3. "EINT,Event Interrupt [EINT] RW1C. Default = '0'. The xHC sets this bit to '1' when the Interrupt Pending [IP] bit of any Interrupter transitions from '0' to '1'. Refer to section 7.1.2 of xHCI specification for use. Software that uses EINT shall clear.." "0,1" newline bitfld.long 0x4 2. "HSE,Host System Error [HSE] RW1C. Default = '0'. The xHC sets this bit to '1' when a serious error is detected either internal to the xHC or during a host system access involving the xHC module. [In a PCI system conditions that set this bit to 1.." "0,1" newline rbitfld.long 0x4 1. "RSVDZ1,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." "0,1" newline rbitfld.long 0x4 0. "HCH,HCHalted [HCH] RO. Default = '1'. This bit is a '0' whenever the Run/Stop [R/S] bit is a '1'. The xHC sets this bit to '1' after it has stopped executing as a result of the Run/Stop [R/S] bit being cleared to '0' either by software or by the xHC.." "0,1" rgroup.long 0x10088++0xB line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_PAGESIZE,Page Size Register (PAGESIZE)." hexmask.long.word 0x0 16.--31. 1. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline hexmask.long.word 0x0 0.--15. 1. "PAGESIZE,Page Size RO. Default = Implementation defined. This field defines the page size supported by the xHC implementation. This xHC supports a page size of 2^[n+12] if bit n is Set. For example if bit 0 is Set the xHC.." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_RSVDZ8C,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits." hexmask.long 0x4 0.--31. 1. "RSVDZ_1,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_RSVDZ90,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits." hexmask.long 0x8 0.--31. 1. "RSVDZ_1,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." rgroup.long 0x10094++0xB line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_DNCTRL,Device Notification Control Register (DNCTRL). This register is used by software to enable or disable the reporting of the reception of specific USB Device Notification Transaction Packets. A.." hexmask.long.word 0x0 16.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline bitfld.long 0x0 15. "N15,Notification Enable flag 15" "0,1" newline bitfld.long 0x0 14. "N14,Notification Enable flag 14" "0,1" newline bitfld.long 0x0 13. "N13,Notification Enable flag 13" "0,1" newline bitfld.long 0x0 12. "N12,Notification Enable flag 12" "0,1" newline bitfld.long 0x0 11. "N11,Notification Enable flag 11" "0,1" newline bitfld.long 0x0 10. "N10,Notification Enable flag 10" "0,1" newline bitfld.long 0x0 9. "N9,Notification Enable flag 9" "0,1" newline bitfld.long 0x0 8. "N8,Notification Enable flag 8" "0,1" newline bitfld.long 0x0 7. "N7,Notification Enable flag 7" "0,1" newline bitfld.long 0x0 6. "N6,Notification Enable flag 6" "0,1" newline bitfld.long 0x0 5. "N5,Notification Enable flag 5" "0,1" newline bitfld.long 0x0 4. "N4,Notification Enable flag 4" "0,1" newline bitfld.long 0x0 3. "N3,Notification Enable flag 3. BUS_INTERVAL_ADJUSTMENT_MESSAGE." "0,1" newline bitfld.long 0x0 2. "N2,Notification Enable flag 2. LATENCY_TOLERANCE_MESSAGE." "0,1" newline bitfld.long 0x0 1. "N1,Notification Enable flag 1" "0,1" newline bitfld.long 0x0 0. "N0,Notification Enable flag 0" "0,1" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_CRCR_LO,Command Ring Control Register Low (CRCR_L). The Command Ring Control Register provides Command Ring control and status capabilities. and identifies the address and Cycle bit state of the Command Ring.." hexmask.long 0x4 6.--31. 1. "CRPTR_L,Command Ring Pointer Low RW. Default = 0. This field defines low order bits of the initial value of the 64-bit Command Ring Dequeue Pointer. Writes to this field are ignored when Command Ring Running [CRR] = '1'. If the CRCR is written while the.." newline rbitfld.long 0x4 4.--5. "RSVD1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." "0,1,2,3" newline rbitfld.long 0x4 3. "CRR,Command Ring Running [CRR] RO. Default = '0'. This flag is set to '1' if the Run/Stop [R/S] bit is '1' and the Host Controller Doorbell register is written with the DB Reason field set to Host Controller Command. It is cleared to '0' when the.." "0,1" newline bitfld.long 0x4 2. "CA,Command Abort [CA] RW1S. Default = '0'. Writing a '1' to this bit shall immediately terminate the currently executing command stop the Command Ring and generate a Command Completion Event with the Completion Code set to Command Ring Stopped. Refer.." "0,1" newline bitfld.long 0x4 1. "CS,Command Stop [CS] RW1S. Default = '0'. Writing a '1' to this bit shall stop the operation of the Command Ring after the completion of the currently executing command and generate a Command Completion Event with the Completion Code set to Command.." "0,1" newline bitfld.long 0x4 0. "RCS,Ring Cycle State [RCS] RW. This bit identifies the value of the xHC Consumer Cycle State [CCS] flag for the TRB referenced by the Command Ring Pointer. Refer to section 4.9.3 of xHCI specification for more information. Writes to this flag are.." "0,1" line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_CRCR_HI,Command Ring Control Register High (CRCR_HI). The Command Ring Control Register provides high order bits of the Command Ring Dequeue Pointer." hexmask.long 0x8 0.--31. 1. "CRPTR_H,Command Ring Pointer High RW. Default = 0. This field defines high order bits of the initial value of the 64-bit Command Ring Dequeue Pointer. Writes to this field are ignored when Command Ring Running [CRR] = '1'. If the CRCR is written while.." rgroup.long 0x100A0++0xF line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_RSVDZA0,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits." hexmask.long 0x0 0.--31. 1. "RSVDZ_1,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_RSVDZA4,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits." hexmask.long 0x4 0.--31. 1. "RSVDZ_1,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_RSVDZA8,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits." hexmask.long 0x8 0.--31. 1. "RSVDZ_1,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_RSVDZAC,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits." hexmask.long 0xC 0.--31. 1. "RSVDZ_1,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." rgroup.long 0x100B0++0xB line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_DCBAAP_LO,Device Context Base Address Array Pointer Register (DCBAAP_LO). The Device Context Base Address Array Pointer Register identifies the base address of the Device Context Base Address Array." hexmask.long 0x0 6.--31. 1. "DCBAAPTR_L,Device Context Base Address Array Pointer RW. Default = 0. This field defines low order bits of the 64-bit base address of the Device Context Pointer Array. A table of address pointers that reference Device Context structures for the devices.." newline hexmask.long.byte 0x0 0.--5. 1. "RSVDZ1,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_DCBAAP_HI,Device Context Base Address Array Pointer Register (DCBAAP_HI). The Device Context Base Address Array Pointer Register identifies the base address of the Device Context Base Address Array." hexmask.long 0x4 0.--31. 1. "DCBAAPTR_H,Device Context Base Address Array Pointer RW. Default = 0. This field defines high order bits of the 64-bit base address of the Device Context Pointer Array. A table of address pointers that reference Device Context structures for the devices.." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_CONFIG,Configure Register (CONFIG). This register defines runtime xHC configuration parameters." hexmask.long.tbyte 0x8 8.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline hexmask.long.byte 0x8 0.--7. 1. "MAXSLOTSEN,Max Device Slots Enabled [MaxSlotsEn] RW. Default = 0. This field specifies the maximum number of enabled Device Slots. Valid values are in the range of 0 to MaxSlots. Enabled Devices Slots are allocated contiguously. e.g. A value of 16.." rgroup.long 0x100BC++0x7 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_RSVDZBC,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits." hexmask.long 0x0 0.--31. 1. "RSVDZ_1,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_RSVDZ_OP,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits." hexmask.long 0x4 0.--31. 1. "RSVDZ_1,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." rgroup.long 0x10480++0x7 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_PORTSC1USB2,Port Status and Control Register for USB2 protocol port. This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high." rbitfld.long 0x0 31. "RSVDZ_4,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." "0,1" newline rbitfld.long 0x0 30. "DR,Device Removable [DR] RO. This flag indicates if this port has a removable device attached. '0' = Device is removable. '1' = Device is non-removable." "0,1" newline rbitfld.long 0x0 28.--29. "RSVDZ_3,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." "0,1,2,3" newline bitfld.long 0x0 27. "WOE,Wake on Over-current Enable [WOE] RWS. Default = '0'. Writing this bit to a '1' enables the port to be sensitive to over-current conditions as system wake-up events. Refer to section 4.15 of xHCI specification for operational model." "0,1" newline bitfld.long 0x0 26. "WDE,Wake on Disconnect Enable [WDE] RWS. Default = '0'. Writing this bit to a '1' enables the port to be sensitive to device disconnects as system wake-up events. Refer to section 4.15 of xHCI specification for operational model." "0,1" newline bitfld.long 0x0 25. "WCE,Wake on Connect Enable [WCE] RWS. Default = '0'. Writing this bit to a '1' enables the port to be sensitive to device connects as system wake-up events. Refer to section 4.15 of xHCI specification for operational model." "0,1" newline rbitfld.long 0x0 24. "CAS,Cold Attach Status [CAS] RO. Default = '0'. '1' = Far-end Receiver Terminations were detected in the Disconnected state and the Root Hub Port State Machine was unable to advance to the Enabled state. Refer to sections 4.19.8 of xHCI.." "0,1" newline rbitfld.long 0x0 23. "RSVDZ_2,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." "0,1" newline bitfld.long 0x0 22. "PLC,Port Link State Change [PLC] RW1CS. Default = '0'. This flag is set to '1' due to the following PLS transitions: U3 -> Resume [Wakeup signaling from a device] Resume -> Recovery -> U0 [Device Resume complete.." "0: U0 [L1 Entry Reject [USB2 protocol ports only]],?" newline bitfld.long 0x0 21. "PRC,Port Reset Change [PRC] RW1CS. Default = '0'. This flag is set to '1' due to a '1' to '0' transition of Port Reset [PR] e.g. when any reset processing [Warm or Hot] on this port is complete. Note that this flag shall not be set to.." "0,1" newline bitfld.long 0x0 20. "OCC,Over-current Change [OCC] RW1CS. Default = '0'. This bit shall be set to a '1' when there is a '0' to '1' or '1' to '0' transition of Over-current Active [OCA]. Software shall clear this bit by writing a '1' to it. Refer to section.." "0,1" newline bitfld.long 0x0 19. "WRC,Warm Port Reset Change [WRC] RW1CS/RsvdZ. Default = '0'. This bit is set when Warm Reset processing on this port completes. '0' = No change. '1' = Warm Reset complete. Note that this flag shall not be set to '1' if the Warm Reset.." "0,1" newline bitfld.long 0x0 18. "PEC,Port Enabled/Disabled Change [PEC] RW1CS. Default = '0'. '1' = change in PED. '0' = No change. Note that this flag shall not be set if the PED transition was due to software setting PP to '0'. Software shall clear this bit by writing a.." "0,1" newline bitfld.long 0x0 17. "CSC,Connect Status Change [CSC] RW1CS. Default = '0'. '1' = Change in CCS. '0' = No change. This flag indicates a change has occurred in the ports Current Connect Status [CCS] or Cold Attach Status [CAS] bits. Note that this.." "0,1" newline bitfld.long 0x0 16. "LWS,Port Link State Write Strobe [LWS] RW. Default = '0'. When this bit is set to '1' on a write reference to this register this flag enables writes to the PLS field. When '0' write data in PLS field is ignored. Reads to this bit return '0'." "0,1" newline bitfld.long 0x0 14.--15. "PIC,Port Indicator Control [PIC] RWS. Default = '0'. Writing to these bits has no effect if the Port Indicators [PIND] bit in the HCCPARAMS register is a '0'. If PIND bit is a '1' then the bit encodings are: 0: Port indicators.." "0: Port indicators are off,1: Amber,2: Green,3: Undefined" newline hexmask.long.byte 0x0 10.--13. 1. "PORTSPEED,Port Speed [Port Speed] ROS. Default = '0'. This field identifies the speed of the connected USB Device. This field is only relevant if a device is connected [CCS = '1'] in all other cases this field shall indicate Undefined.." newline bitfld.long 0x0 9. "PP,Port Power [PP] RWS. Default = '1'. This flag reflects a port's logical power control state. Because host controllers can implement different methods of port power switching this flag may or may not represent whether [VBus] power is.." "0,1" newline hexmask.long.byte 0x0 5.--8. 1. "PLS,Port Link State [PLS] RWS. Default = RxDetect ['5']. This field is used to power manage the port and reflects its current link state. When the port is in the Enabled state system software may set the link U state by writing this field. System.." newline bitfld.long 0x0 4. "PR,Port Reset [PR] RW1S. Default = '0'. '1' = Port Reset signaling is asserted. '0' = Port is not in Reset. When software writes a '1' to this bit generating a '0' to '1' transition the bus reset sequence is initiated. USB2 protocol ports.." "0,1" newline rbitfld.long 0x0 3. "OCA,Over-current Active [OCA] RO. Default = '0'. '1' = This port currently has an over-current condition. '0' = This port does not have an over-current condition. This bit shall automatically transition from a '1' to a '0' when.." "0,1" newline rbitfld.long 0x0 2. "RSVDZ_1,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." "0,1" newline bitfld.long 0x0 1. "PED,Port Enabled/Disabled [PED] RW1CS. Default = '0'. '1' = Enabled. '0' = Disabled. Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag. A port may be disabled by software writing a '1' to this.." "0,1" newline rbitfld.long 0x0 0. "CCS,Current Connect Status [CCS] ROS. Default = '0'. '1' = A device is connected to the port. '0' = A device is not connected. This value reflects the current state of the port and may not correspond directly to the event that.." "0,1" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_PORTPMSC1USB2,The USB2 Port Power Management Status and Control register. Provides the USB2 LPM parameters necessary for the xHC to generate a LPM Token to the downstream device. This register may be read from.." hexmask.long.byte 0x4 28.--31. 1. "PTC,Port Test Control RW. Default = '0'. When this field is '0' the port is NOT operating in a test mode. A non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value. A.." newline hexmask.long.word 0x4 17.--27. 1. "RSVDP,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline bitfld.long 0x4 16. "HLE,Hardware LPM Enable [HLE] RW. Default = '0'. If this bit is set to '1' then hardware controlled LPM shall be enabled for this port. Refer to section 4.23.5.1.1.1 of xHCI specification. If the USB2 Hardware LPM Capability is not supported [HLC =.." "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "L1DS,L1 Device Slot RW. Default = 0. System software sets this field to indicate the ID of the Device Slot associated with the device directly attached to the Root Hub port. A value of '0' indicates no device is present. The xHC uses this field to.." newline hexmask.long.byte 0x4 4.--7. 1. "BESL,Best Effort Service Latency [BESL] RW. Default = 0. System software sets this field to indicate to the recipient device how long the xHC will drive resume if it [the xHC] initiates an exit from L1. The BESL value encoding is defined.." newline bitfld.long 0x4 3. "RWE,Remote Wake Enable [RWE] RW. Default = '0'. System software sets this flag to enable or disable the device for remote wake from L1. The value of this flag shall temporarily [while in L1] override the current setting of the Remote Wake feature set by.." "0,1" newline rbitfld.long 0x4 0.--2. "L1S,L1 Status [L1S] RO. Default = 0. This field is used by software to determine whether an L1-based suspend request [LPM transaction] was successful specifically: 0: Invalid - This field shall be ignored by software. 1:.." "0: Invalid,1: Success,2: Not Yet,3: Not Supported,4: Timeout/Error,?,?,7: Reserved The value of this field is only valid.." rgroup.long 0x10488++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_RSVDP1USB2,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits." hexmask.long 0x0 0.--31. 1. "RSVDP_1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." rgroup.long 0x1048C++0xB line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_PORT1HLPMC,The optional normative USB2 Port Hardware LPM Control register provides the USB2 LPM parameters necessary for the xHC to automatically generate a LPM Token to the downstream device. Refer to section.." hexmask.long.tbyte 0x0 14.--31. 1. "RSVDP,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline hexmask.long.byte 0x0 10.--13. 1. "BESLD,Best Effort Service Latency Deep [BESLD] RWS. Default = '0'. System software sets this field to indicate to the recipient device how long the xHC will drive resume on an exit from U2. Refer to section 4.23.5.1.1.1 of xHCI specification for more.." newline hexmask.long.byte 0x0 2.--9. 1. "L1_TIMEOUT,L1 Timeout RWS. Default = 00h. Timeout value for the L1 inactivity timer [LPM Timer]. This field shall be set to 00h by the assertion of PR to '1'. Refer to section 4.23.5.1.1.1 of xHci specification for more information on L1 Timeout.." newline bitfld.long 0x0 0.--1. "HIRDM,Host Initiated Resume Duration Mode [HIRDM] RWS. Default = 0h. Indicates which HIRD value should be used. The following are permissible values: 0: Initiate L1 using BESL only on timeout. [default] 1: Initiate.." "0: Initiate L1 using BESL only on timeout,1: Initiate L1 using BESLD on timeout,2: Reserved,?" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_PORTSC1USB3,Port Status and Control Register for USB3 protocol port. The register cannot be accessed if USB3 PHY is not active (i.e. when there is no USB3 PHY or when USB3 PHY has not started providing USB3.." bitfld.long 0x4 31. "WPR,Warm Port Reset [WPR] RW1S. Default = '0'. When software writes a '1' to this bit the Warm Reset sequence as defined in the USB3 Specification is initiated and the PR flag is set to '1'. Once initiated the PR PRC and WRC flags shall reflect the.." "0,1" newline rbitfld.long 0x4 30. "DR,Device Removable [DR] RO. This flag indicates if this port has a removable device attached. '0' = Device is removable. '1' = Device is non-removable." "0,1" newline rbitfld.long 0x4 28.--29. "RSVDZ_2,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." "0,1,2,3" newline bitfld.long 0x4 27. "WOE,Wake on Over-current Enable [WOE] RWS. Default = '0'. Writing this bit to a '1' enables the port to be sensitive to over-current conditions as system wake-up events. Refer to section 4.15 of xHCI specification for operational model." "0,1" newline bitfld.long 0x4 26. "WDE,Wake on Disconnect Enable [WDE] RWS. Default = '0'. Writing this bit to a '1' enables the port to be sensitive to device disconnects as system wake-up events. Refer to section 4.15 of xHCI specification for operational model." "0,1" newline bitfld.long 0x4 25. "WCE,Wake on Connect Enable [WCE] RWS. Default = '0'. Writing this bit to a '1' enables the port to be sensitive to device connects as system wake-up events. Refer to section 4.15 of xHCI specification for operational model." "0,1" newline rbitfld.long 0x4 24. "CAS,Cold Attach Status [CAS] RO. Default = '0'. '1' = Far-end Receiver Terminations were detected in the Disconnected state and the Root Hub Port State Machine was unable to advance to the Enabled state. Refer to sections 4.19.8 of xHCI.." "0,1" newline bitfld.long 0x4 23. "CEC,Port Config Error Change [CEC] RW1CS. Default = '0'. This flag indicates that the port failed to configure its link partner. '0' = No change. '1' = Port Config Error detected. Software shall clear this bit by writing a.." "0,1" newline bitfld.long 0x4 22. "PLC,Port Link State Change [PLC] RW1CS. Default = '0'. This flag is set to '1' due to the following PLS transitions: U3 -> Resume [Wakeup signaling from a device] Resume -> Recovery -> U0 [Device Resume.." "0: U0 [L1 Entry Reject [USB2 protocol ports only]],?" newline bitfld.long 0x4 21. "PRC,Port Reset Change [PRC] RW1CS. Default = '0'. This flag is set to '1' due to a '1' to '0' transition of Port Reset [PR] e.g. when any reset processing [Warm or Hot] on this port is complete. Note that this flag shall not be set to.." "0,1" newline bitfld.long 0x4 20. "OCC,Over-current Change [OCC] RW1CS. Default = '0'. This bit shall be set to a '1' when there is a '0' to '1' or '1' to '0' transition of Over-current Active [OCA]. Software shall clear this bit by writing a '1' to it. Refer to section.." "0,1" newline bitfld.long 0x4 19. "WRC,Warm Port Reset Change [WRC] RW1CS. Default = '0'. This bit is set when Warm Reset processing on this port completes. '0' = No change. '1' = Warm Reset complete. Note that this flag shall not be set to '1' if the Warm Reset processing.." "0,1" newline bitfld.long 0x4 18. "PEC,Port Enabled/Disabled Change [PEC] RW1CS. Default = '0'. '1' = change in PED. '0' = No change. Note that this flag shall not be set if the PED transition was due to software setting PP to '0'. Software shall clear this bit by writing.." "0,1" newline bitfld.long 0x4 17. "CSC,Connect Status Change [CSC] RW1CS. Default = '0'. '1' = Change in CCS. '0' = No change. This flag indicates a change has occurred in the ports Current Connect Status [CCS] or Cold Attach Status [CAS] bits. Note that.." "0,1" newline bitfld.long 0x4 16. "LWS,Port Link State Write Strobe [LWS] RW. Default = '0'. When this bit is set to '1' on a write reference to this register this flag enables writes to the PLS field. When '0' write data in PLS field is ignored. Reads to this bit return '0'." "0,1" newline bitfld.long 0x4 14.--15. "PIC,Port Indicator Control [PIC] RWS. Default = '0'. Writing to these bits has no effect if the Port Indicators [PIND] bit in the HCCPARAMS register is a '0'. If PIND bit is a '1' then the bit encodings are: 0: Port indicators.." "0: Port indicators are off,1: Amber,2: Green,3: Undefined" newline hexmask.long.byte 0x4 10.--13. 1. "PORTSPEED,Port Speed [Port Speed] ROS. Default = '0'. This field identifies the speed of the connected USB Device. This field is only relevant if a device is connected [CCS = '1'] in all other cases this field shall indicate Undefined.." newline bitfld.long 0x4 9. "PP,Port Power [PP] RWS. Default = '1'. This flag reflects a port's logical power control state. Because host controllers can implement different methods of port power switching this flag may or may not represent whether [VBus] power is.." "0,1" newline hexmask.long.byte 0x4 5.--8. 1. "PLS,Port Link State [PLS] RWS. Default = RxDetect ['5']. This field is used to power manage the port and reflects its current link state. When the port is in the Enabled state system software may set the link U state by writing this field. System.." newline bitfld.long 0x4 4. "PR,Port Reset [PR] RW1S. Default = '0'. '1' = Port Reset signaling is asserted. '0' = Port is not in Reset. When software writes a '1' to this bit generating a '0' to '1' transition the bus reset sequence is initiated. USB3 protocol.." "0,1" newline rbitfld.long 0x4 3. "OCA,Over-current Active [OCA] RO. Default = '0'. '1' = This port currently has an over-current condition. '0' = This port does not have an over-current condition. This bit shall automatically transition from a '1' to a '0'.." "0,1" newline rbitfld.long 0x4 2. "RSVDZ_1,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." "0,1" newline bitfld.long 0x4 1. "PED,Port Enabled/Disabled [PED] RW1CS. Default = '0'. '1' = Enabled. '0' = Disabled. Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag. A port may be disabled by software writing a '1' to.." "0,1" newline rbitfld.long 0x4 0. "CCS,Current Connect Status [CCS] ROS. Default = '0'. '1' = A device is connected to the port. '0' = A device is not connected. This value reflects the current state of the port and may not correspond directly to the event that.." "0,1" line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_PORTPMSC1USB3,USB3 Port Power Management Status and Control register. Controls the SuperSpeed USB link U-State timeouts. The register cannot be accessed if USB3 PHY is not active (i.e. when there is no USB3 PHY.." hexmask.long.word 0x8 17.--31. 1. "RSVDP,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline bitfld.long 0x8 16. "FLA,Force Link PM Accept [FLA] RW. Default = '0'. When this bit is set to '1' the port shall generate a Set Link Function LMP with the Force_LinkPM_Accept bit asserted ['1']. When this bit is cleared to '0' the port shall generate a Set Link Function.." "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "U2_TIMEOUT,U2 Timeout RWS. Default = 0. Timeout value for U2 inactivity timer. If equal to FFh the port is disabled from initiating U2 entry. This field shall be set to '0' by the assertion of PR to '1'. Refer to section 4.19.4.1 of xHCI.." newline hexmask.long.byte 0x8 0.--7. 1. "U1_TIMEOUT,U1 Timeout RWS. Default = 0. Timeout value for U1 inactivity timer. If equal to FFh the port is disabled from initiating U1 entry. This field shall be set to '0' by the assertion of PR to '1'. Refer to section 4.19.4.1 of xHCI.." rgroup.long 0x10498++0x7 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_PORTLI1,The USB3 Port Link Info register reports the Link Error Count." hexmask.long.word 0x0 16.--31. 1. "RSVDP,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline hexmask.long.word 0x0 0.--15. 1. "LEC,Link Error Count RO. Default = '0'. This field returns the number of link errors detected by the port. This value shall be reset to '0' by the assertion of a Chip Hardware Reset HCRST when PR transitions from 1 to 0 or when CCS = transitions.." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_RSVDP1USB3,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits." hexmask.long 0x4 0.--31. 1. "RSVDP_1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." rgroup.long 0x12000++0x7 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_MFINDEX,This register is used by the system software to determine the current periodic frame. The register value is" hexmask.long.tbyte 0x0 14.--31. 1. "RSVDZ1,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." newline hexmask.long.word 0x0 0.--13. 1. "MFINDEX,Microframe Index RO. The value in this register increments at the end of each microframe [e.g. 125us.]. Bits [13:3] may be used to determine the current 1ms Frame Index. Note: Setting frindex_wr_en to '1' [bit 31 of.." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_RSVDZ_RT,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits." hexmask.long 0x4 0.--31. 1. "RSVDZ_1,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." rgroup.long 0x12020++0xB line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_IMAN0,Interrupter Management Register (IMAN). The Interrupter Management register allows system software to enable. disable. detect. and force xHC interrupts." hexmask.long 0x0 2.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline bitfld.long 0x0 1. "IE,Interrupt Enable [IE] RW. Default = '0'. This flag specifies whether the Interrupter is capable of generating an interrupt. When this bit and the IP bit are set ['1'] the Interrupter shall generate an interrupt when the Interrupter Moderation.." "0,1" newline bitfld.long 0x0 0. "IP,Interrupt Pending [IP] RW1C. Default = '0'. This flag represents the current state of the Interrupter. If IP = '1' an interrupt is pending for this Interrupter. A '0' value indicates that no interrupt is pending for the Interrupter. Refer to section.." "0,1" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_IMOD0,Interrupter Moderation Register (IMOD). The Interrupter Moderation Register controls the interrupt moderation feature of an Interrupter. allowing system software to throttle the interrupt rate generated.." hexmask.long.word 0x4 16.--31. 1. "IMODC,Interrupt Moderation Counter [IMODC] RW. Default = undefined. Down counter. Loaded with the IMODI value whenever IP is cleared to '0' counts down to 0 and stops. The associated interrupt shall be signaled whenever this counter is zero the.." newline hexmask.long.word 0x4 0.--15. 1. "IMODI,Interrupt Moderation Interval [IMODI] RW. Default = 'hFA0' [~1ms]. Minimum inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables interrupt throttling logic and interrupts shall be generated immediately.." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTSZ0,Event Ring Segment Table Size Register (ERSTSZ). The Event Ring Segment Table Size Register defines the number of segments supported by the Event Ring Segment Table." hexmask.long.word 0x8 16.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline hexmask.long.word 0x8 0.--15. 1. "ERSTS,Event Ring Segment Table Size RW. Default = 0. This field identifies the number of valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event Ring Segment Table Base Address register. The maximum value.." rgroup.long 0x1202C++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_reserved0,Reserved" hexmask.long 0x0 0.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." rgroup.long 0x12030++0x1B line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTBA0_LO,The Event Ring Segment Table Base Address Register identifies the start address of the Event Ring Segment Table." hexmask.long 0x0 6.--31. 1. "ERSTBADDR_LO,Event Ring Segment Table Base Address Register RW. Default = 0. This field defines the low order bit [25:0] of the start address of the Event Ring Segment Table [the address is 58 bits wide] . Writing this register sets the Event Ring State.." newline hexmask.long.byte 0x0 0.--5. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTBA0_HI,The Event Ring Segment Table Base Address Register identifies the start address of the Event Ring Segment Table." hexmask.long 0x4 0.--31. 1. "ERSTBADDR_HI,Event Ring Segment Table Base Address Register RW. Default = 0. This field defines the high order bits [57:26] of the start address of the Event Ring Segment Table [the address is 58 bits wide] . Writing this register sets the Event Ring.." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERDP0_LO,Event Ring Dequeue Pointer Register (ERDP). The Event Ring Dequeue Pointer Register is written by software to define the Event Ring Dequeue Pointer location to the xHC. Software updates this pointer.." hexmask.long 0x8 4.--31. 1. "ERDPTR,Event Ring Dequeue Pointer RW. Default = 0. This field defines the 28 low order bits of the 64-bit address of the current Event Ring Dequeue Pointer." newline bitfld.long 0x8 3. "EHB,Event Handler Busy [EHB] RW1C. Default = '0'. This flag shall be set to '1' when the IP bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written. Refer to section 4.17.2 of xHCI specification for more information" "0,1" newline bitfld.long 0x8 0.--2. "DESI,Dequeue ERST Segment Index [DESI]. Default = 0. This field may be used by the xHC to accelerate checking the Event Ring full condition. This field is written with the low order 3 bits of the offset of the ERST entry which defines the Event Ring.." "0,1,2,3,4,5,6,7" line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERDP0_HI,Event Ring Dequeue Pointer Register (ERDP). The Event Ring Dequeue Pointer Register is written by software to define the Event Ring Dequeue Pointer location to the xHC. Software updates this pointer.." hexmask.long 0xC 0.--31. 1. "ERDPTR_HI,Event Ring Dequeue Pointer RW. Default = 0. This field defines the 32 high order bits of the 64-bit address of the current Event Ring Dequeue Pointer." line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_IMAN1,Interrupter Management Register (IMAN). The Interrupter Management register allows system software to enable. disable. detect. and force xHC interrupts." hexmask.long 0x10 2.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline bitfld.long 0x10 1. "IE,Interrupt Enable [IE] RW. Default = '0'. This flag specifies whether the Interrupter is capable of generating an interrupt. When this bit and the IP bit are set ['1'] the Interrupter shall generate an interrupt when the Interrupter Moderation.." "0,1" newline bitfld.long 0x10 0. "IP,Interrupt Pending [IP] RW1C. Default = '0'. This flag represents the current state of the Interrupter. If IP = '1' an interrupt is pending for this Interrupter. A '0' value indicates that no interrupt is pending for the Interrupter. Refer to section.." "0,1" line.long 0x14 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_IMOD1,Interrupter Moderation Register (IMOD). The Interrupter Moderation Register controls the interrupt moderation feature of an Interrupter. allowing system software to throttle the interrupt rate generated.." hexmask.long.word 0x14 16.--31. 1. "IMODC,Interrupt Moderation Counter [IMODC] RW. Default = undefined. Down counter. Loaded with the IMODI value whenever IP is cleared to '0' counts down to 0 and stops. The associated interrupt shall be signaled whenever this counter is zero the.." newline hexmask.long.word 0x14 0.--15. 1. "IMODI,Interrupt Moderation Interval [IMODI] RW. Default = 'hFA0' [~1ms]. Minimum inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables interrupt throttling logic and interrupts shall be generated immediately.." line.long 0x18 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTSZ1,Event Ring Segment Table Size Register (ERSTSZ). The Event Ring Segment Table Size Register defines the number of segments supported by the Event Ring Segment Table." hexmask.long.word 0x18 16.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline hexmask.long.word 0x18 0.--15. 1. "ERSTS,Event Ring Segment Table Size RW. Default = 0. This field identifies the number of valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event Ring Segment Table Base Address register. The maximum value.." rgroup.long 0x1204C++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_reserved1,Reserved" hexmask.long 0x0 0.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." rgroup.long 0x12050++0x1B line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTBA1_LO,The Event Ring Segment Table Base Address Register identifies the start address of the Event Ring Segment Table." hexmask.long 0x0 6.--31. 1. "ERSTBADDR_LO,Event Ring Segment Table Base Address Register RW. Default = 0. This field defines the low order bit [25:0] of the start address of the Event Ring Segment Table [the address is 58 bits wide] . Writing this register sets the Event Ring State.." newline hexmask.long.byte 0x0 0.--5. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTBA1_HI,The Event Ring Segment Table Base Address Register identifies the start address of the Event Ring Segment Table." hexmask.long 0x4 0.--31. 1. "ERSTBADDR_HI,Event Ring Segment Table Base Address Register RW. Default = 0. This field defines the high order bits [57:26] of the start address of the Event Ring Segment Table [the address is 58 bits wide] . Writing this register sets the Event Ring.." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERDP1_LO,Event Ring Dequeue Pointer Register (ERDP). The Event Ring Dequeue Pointer Register is written by software to define the Event Ring Dequeue Pointer location to the xHC. Software updates this pointer.." hexmask.long 0x8 4.--31. 1. "ERDPTR,Event Ring Dequeue Pointer RW. Default = 0. This field defines the 28 low order bits of the 64-bit address of the current Event Ring Dequeue Pointer." newline bitfld.long 0x8 3. "EHB,Event Handler Busy [EHB] RW1C. Default = '0'. This flag shall be set to '1' when the IP bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written. Refer to section 4.17.2 of xHCI specification for more information" "0,1" newline bitfld.long 0x8 0.--2. "DESI,Dequeue ERST Segment Index [DESI]. Default = 0. This field may be used by the xHC to accelerate checking the Event Ring full condition. This field is written with the low order 3 bits of the offset of the ERST entry which defines the Event Ring.." "0,1,2,3,4,5,6,7" line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERDP1_HI,Event Ring Dequeue Pointer Register (ERDP). The Event Ring Dequeue Pointer Register is written by software to define the Event Ring Dequeue Pointer location to the xHC. Software updates this pointer.." hexmask.long 0xC 0.--31. 1. "ERDPTR_HI,Event Ring Dequeue Pointer RW. Default = 0. This field defines the 32 high order bits of the 64-bit address of the current Event Ring Dequeue Pointer." line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_IMAN2,Interrupter Management Register (IMAN). The Interrupter Management register allows system software to enable. disable. detect. and force xHC interrupts." hexmask.long 0x10 2.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline bitfld.long 0x10 1. "IE,Interrupt Enable [IE] RW. Default = '0'. This flag specifies whether the Interrupter is capable of generating an interrupt. When this bit and the IP bit are set ['1'] the Interrupter shall generate an interrupt when the Interrupter Moderation.." "0,1" newline bitfld.long 0x10 0. "IP,Interrupt Pending [IP] RW1C. Default = '0'. This flag represents the current state of the Interrupter. If IP = '1' an interrupt is pending for this Interrupter. A '0' value indicates that no interrupt is pending for the Interrupter. Refer to section.." "0,1" line.long 0x14 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_IMOD2,Interrupter Moderation Register (IMOD). The Interrupter Moderation Register controls the interrupt moderation feature of an Interrupter. allowing system software to throttle the interrupt rate generated.." hexmask.long.word 0x14 16.--31. 1. "IMODC,Interrupt Moderation Counter [IMODC] RW. Default = undefined. Down counter. Loaded with the IMODI value whenever IP is cleared to '0' counts down to 0 and stops. The associated interrupt shall be signaled whenever this counter is zero the.." newline hexmask.long.word 0x14 0.--15. 1. "IMODI,Interrupt Moderation Interval [IMODI] RW. Default = 'hFA0' [~1ms]. Minimum inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables interrupt throttling logic and interrupts shall be generated immediately.." line.long 0x18 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTSZ2,Event Ring Segment Table Size Register (ERSTSZ). The Event Ring Segment Table Size Register defines the number of segments supported by the Event Ring Segment Table." hexmask.long.word 0x18 16.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline hexmask.long.word 0x18 0.--15. 1. "ERSTS,Event Ring Segment Table Size RW. Default = 0. This field identifies the number of valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event Ring Segment Table Base Address register. The maximum value.." rgroup.long 0x1206C++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_reserved2,Reserved" hexmask.long 0x0 0.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." rgroup.long 0x12070++0x1B line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTBA2_LO,The Event Ring Segment Table Base Address Register identifies the start address of the Event Ring Segment Table." hexmask.long 0x0 6.--31. 1. "ERSTBADDR_LO,Event Ring Segment Table Base Address Register RW. Default = 0. This field defines the low order bit [25:0] of the start address of the Event Ring Segment Table [the address is 58 bits wide] . Writing this register sets the Event Ring State.." newline hexmask.long.byte 0x0 0.--5. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTBA2_HI,The Event Ring Segment Table Base Address Register identifies the start address of the Event Ring Segment Table." hexmask.long 0x4 0.--31. 1. "ERSTBADDR_HI,Event Ring Segment Table Base Address Register RW. Default = 0. This field defines the high order bits [57:26] of the start address of the Event Ring Segment Table [the address is 58 bits wide] . Writing this register sets the Event Ring.." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERDP2_LO,Event Ring Dequeue Pointer Register (ERDP). The Event Ring Dequeue Pointer Register is written by software to define the Event Ring Dequeue Pointer location to the xHC. Software updates this pointer.." hexmask.long 0x8 4.--31. 1. "ERDPTR,Event Ring Dequeue Pointer RW. Default = 0. This field defines the 28 low order bits of the 64-bit address of the current Event Ring Dequeue Pointer." newline bitfld.long 0x8 3. "EHB,Event Handler Busy [EHB] RW1C. Default = '0'. This flag shall be set to '1' when the IP bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written. Refer to section 4.17.2 of xHCI specification for more information" "0,1" newline bitfld.long 0x8 0.--2. "DESI,Dequeue ERST Segment Index [DESI]. Default = 0. This field may be used by the xHC to accelerate checking the Event Ring full condition. This field is written with the low order 3 bits of the offset of the ERST entry which defines the Event Ring.." "0,1,2,3,4,5,6,7" line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERDP2_HI,Event Ring Dequeue Pointer Register (ERDP). The Event Ring Dequeue Pointer Register is written by software to define the Event Ring Dequeue Pointer location to the xHC. Software updates this pointer.." hexmask.long 0xC 0.--31. 1. "ERDPTR_HI,Event Ring Dequeue Pointer RW. Default = 0. This field defines the 32 high order bits of the 64-bit address of the current Event Ring Dequeue Pointer." line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_IMAN3,Interrupter Management Register (IMAN). The Interrupter Management register allows system software to enable. disable. detect. and force xHC interrupts." hexmask.long 0x10 2.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline bitfld.long 0x10 1. "IE,Interrupt Enable [IE] RW. Default = '0'. This flag specifies whether the Interrupter is capable of generating an interrupt. When this bit and the IP bit are set ['1'] the Interrupter shall generate an interrupt when the Interrupter Moderation.." "0,1" newline bitfld.long 0x10 0. "IP,Interrupt Pending [IP] RW1C. Default = '0'. This flag represents the current state of the Interrupter. If IP = '1' an interrupt is pending for this Interrupter. A '0' value indicates that no interrupt is pending for the Interrupter. Refer to section.." "0,1" line.long 0x14 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_IMOD3,Interrupter Moderation Register (IMOD). The Interrupter Moderation Register controls the interrupt moderation feature of an Interrupter. allowing system software to throttle the interrupt rate generated.." hexmask.long.word 0x14 16.--31. 1. "IMODC,Interrupt Moderation Counter [IMODC] RW. Default = undefined. Down counter. Loaded with the IMODI value whenever IP is cleared to '0' counts down to 0 and stops. The associated interrupt shall be signaled whenever this counter is zero the.." newline hexmask.long.word 0x14 0.--15. 1. "IMODI,Interrupt Moderation Interval [IMODI] RW. Default = 'hFA0' [~1ms]. Minimum inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables interrupt throttling logic and interrupts shall be generated immediately.." line.long 0x18 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTSZ3,Event Ring Segment Table Size Register (ERSTSZ). The Event Ring Segment Table Size Register defines the number of segments supported by the Event Ring Segment Table." hexmask.long.word 0x18 16.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline hexmask.long.word 0x18 0.--15. 1. "ERSTS,Event Ring Segment Table Size RW. Default = 0. This field identifies the number of valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event Ring Segment Table Base Address register. The maximum value.." rgroup.long 0x1208C++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_reserved3,Reserved" hexmask.long 0x0 0.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." rgroup.long 0x12090++0x1B line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTBA3_LO,The Event Ring Segment Table Base Address Register identifies the start address of the Event Ring Segment Table." hexmask.long 0x0 6.--31. 1. "ERSTBADDR_LO,Event Ring Segment Table Base Address Register RW. Default = 0. This field defines the low order bit [25:0] of the start address of the Event Ring Segment Table [the address is 58 bits wide] . Writing this register sets the Event Ring State.." newline hexmask.long.byte 0x0 0.--5. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTBA3_HI,The Event Ring Segment Table Base Address Register identifies the start address of the Event Ring Segment Table." hexmask.long 0x4 0.--31. 1. "ERSTBADDR_HI,Event Ring Segment Table Base Address Register RW. Default = 0. This field defines the high order bits [57:26] of the start address of the Event Ring Segment Table [the address is 58 bits wide] . Writing this register sets the Event Ring.." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERDP3_LO,Event Ring Dequeue Pointer Register (ERDP). The Event Ring Dequeue Pointer Register is written by software to define the Event Ring Dequeue Pointer location to the xHC. Software updates this pointer.." hexmask.long 0x8 4.--31. 1. "ERDPTR,Event Ring Dequeue Pointer RW. Default = 0. This field defines the 28 low order bits of the 64-bit address of the current Event Ring Dequeue Pointer." newline bitfld.long 0x8 3. "EHB,Event Handler Busy [EHB] RW1C. Default = '0'. This flag shall be set to '1' when the IP bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written. Refer to section 4.17.2 of xHCI specification for more information" "0,1" newline bitfld.long 0x8 0.--2. "DESI,Dequeue ERST Segment Index [DESI]. Default = 0. This field may be used by the xHC to accelerate checking the Event Ring full condition. This field is written with the low order 3 bits of the offset of the ERST entry which defines the Event Ring.." "0,1,2,3,4,5,6,7" line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERDP3_HI,Event Ring Dequeue Pointer Register (ERDP). The Event Ring Dequeue Pointer Register is written by software to define the Event Ring Dequeue Pointer location to the xHC. Software updates this pointer.." hexmask.long 0xC 0.--31. 1. "ERDPTR_HI,Event Ring Dequeue Pointer RW. Default = 0. This field defines the 32 high order bits of the 64-bit address of the current Event Ring Dequeue Pointer." line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_IMAN4,Interrupter Management Register (IMAN). The Interrupter Management register allows system software to enable. disable. detect. and force xHC interrupts." hexmask.long 0x10 2.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline bitfld.long 0x10 1. "IE,Interrupt Enable [IE] RW. Default = '0'. This flag specifies whether the Interrupter is capable of generating an interrupt. When this bit and the IP bit are set ['1'] the Interrupter shall generate an interrupt when the Interrupter Moderation.." "0,1" newline bitfld.long 0x10 0. "IP,Interrupt Pending [IP] RW1C. Default = '0'. This flag represents the current state of the Interrupter. If IP = '1' an interrupt is pending for this Interrupter. A '0' value indicates that no interrupt is pending for the Interrupter. Refer to section.." "0,1" line.long 0x14 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_IMOD4,Interrupter Moderation Register (IMOD). The Interrupter Moderation Register controls the interrupt moderation feature of an Interrupter. allowing system software to throttle the interrupt rate generated.." hexmask.long.word 0x14 16.--31. 1. "IMODC,Interrupt Moderation Counter [IMODC] RW. Default = undefined. Down counter. Loaded with the IMODI value whenever IP is cleared to '0' counts down to 0 and stops. The associated interrupt shall be signaled whenever this counter is zero the.." newline hexmask.long.word 0x14 0.--15. 1. "IMODI,Interrupt Moderation Interval [IMODI] RW. Default = 'hFA0' [~1ms]. Minimum inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables interrupt throttling logic and interrupts shall be generated immediately.." line.long 0x18 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTSZ4,Event Ring Segment Table Size Register (ERSTSZ). The Event Ring Segment Table Size Register defines the number of segments supported by the Event Ring Segment Table." hexmask.long.word 0x18 16.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline hexmask.long.word 0x18 0.--15. 1. "ERSTS,Event Ring Segment Table Size RW. Default = 0. This field identifies the number of valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event Ring Segment Table Base Address register. The maximum value.." rgroup.long 0x120AC++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_reserved4,Reserved" hexmask.long 0x0 0.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." rgroup.long 0x120B0++0x1B line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTBA4_LO,The Event Ring Segment Table Base Address Register identifies the start address of the Event Ring Segment Table." hexmask.long 0x0 6.--31. 1. "ERSTBADDR_LO,Event Ring Segment Table Base Address Register RW. Default = 0. This field defines the low order bit [25:0] of the start address of the Event Ring Segment Table [the address is 58 bits wide] . Writing this register sets the Event Ring State.." newline hexmask.long.byte 0x0 0.--5. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTBA4_HI,The Event Ring Segment Table Base Address Register identifies the start address of the Event Ring Segment Table." hexmask.long 0x4 0.--31. 1. "ERSTBADDR_HI,Event Ring Segment Table Base Address Register RW. Default = 0. This field defines the high order bits [57:26] of the start address of the Event Ring Segment Table [the address is 58 bits wide] . Writing this register sets the Event Ring.." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERDP4_LO,Event Ring Dequeue Pointer Register (ERDP). The Event Ring Dequeue Pointer Register is written by software to define the Event Ring Dequeue Pointer location to the xHC. Software updates this pointer.." hexmask.long 0x8 4.--31. 1. "ERDPTR,Event Ring Dequeue Pointer RW. Default = 0. This field defines the 28 low order bits of the 64-bit address of the current Event Ring Dequeue Pointer." newline bitfld.long 0x8 3. "EHB,Event Handler Busy [EHB] RW1C. Default = '0'. This flag shall be set to '1' when the IP bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written. Refer to section 4.17.2 of xHCI specification for more information" "0,1" newline bitfld.long 0x8 0.--2. "DESI,Dequeue ERST Segment Index [DESI]. Default = 0. This field may be used by the xHC to accelerate checking the Event Ring full condition. This field is written with the low order 3 bits of the offset of the ERST entry which defines the Event Ring.." "0,1,2,3,4,5,6,7" line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERDP4_HI,Event Ring Dequeue Pointer Register (ERDP). The Event Ring Dequeue Pointer Register is written by software to define the Event Ring Dequeue Pointer location to the xHC. Software updates this pointer.." hexmask.long 0xC 0.--31. 1. "ERDPTR_HI,Event Ring Dequeue Pointer RW. Default = 0. This field defines the 32 high order bits of the 64-bit address of the current Event Ring Dequeue Pointer." line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_IMAN5,Interrupter Management Register (IMAN). The Interrupter Management register allows system software to enable. disable. detect. and force xHC interrupts." hexmask.long 0x10 2.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline bitfld.long 0x10 1. "IE,Interrupt Enable [IE] RW. Default = '0'. This flag specifies whether the Interrupter is capable of generating an interrupt. When this bit and the IP bit are set ['1'] the Interrupter shall generate an interrupt when the Interrupter Moderation.." "0,1" newline bitfld.long 0x10 0. "IP,Interrupt Pending [IP] RW1C. Default = '0'. This flag represents the current state of the Interrupter. If IP = '1' an interrupt is pending for this Interrupter. A '0' value indicates that no interrupt is pending for the Interrupter. Refer to section.." "0,1" line.long 0x14 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_IMOD5,Interrupter Moderation Register (IMOD). The Interrupter Moderation Register controls the interrupt moderation feature of an Interrupter. allowing system software to throttle the interrupt rate generated.." hexmask.long.word 0x14 16.--31. 1. "IMODC,Interrupt Moderation Counter [IMODC] RW. Default = undefined. Down counter. Loaded with the IMODI value whenever IP is cleared to '0' counts down to 0 and stops. The associated interrupt shall be signaled whenever this counter is zero the.." newline hexmask.long.word 0x14 0.--15. 1. "IMODI,Interrupt Moderation Interval [IMODI] RW. Default = 'hFA0' [~1ms]. Minimum inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables interrupt throttling logic and interrupts shall be generated immediately.." line.long 0x18 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTSZ5,Event Ring Segment Table Size Register (ERSTSZ). The Event Ring Segment Table Size Register defines the number of segments supported by the Event Ring Segment Table." hexmask.long.word 0x18 16.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline hexmask.long.word 0x18 0.--15. 1. "ERSTS,Event Ring Segment Table Size RW. Default = 0. This field identifies the number of valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event Ring Segment Table Base Address register. The maximum value.." rgroup.long 0x120CC++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_reserved5,Reserved" hexmask.long 0x0 0.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." rgroup.long 0x120D0++0x1B line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTBA5_LO,The Event Ring Segment Table Base Address Register identifies the start address of the Event Ring Segment Table." hexmask.long 0x0 6.--31. 1. "ERSTBADDR_LO,Event Ring Segment Table Base Address Register RW. Default = 0. This field defines the low order bit [25:0] of the start address of the Event Ring Segment Table [the address is 58 bits wide] . Writing this register sets the Event Ring State.." newline hexmask.long.byte 0x0 0.--5. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTBA5_HI,The Event Ring Segment Table Base Address Register identifies the start address of the Event Ring Segment Table." hexmask.long 0x4 0.--31. 1. "ERSTBADDR_HI,Event Ring Segment Table Base Address Register RW. Default = 0. This field defines the high order bits [57:26] of the start address of the Event Ring Segment Table [the address is 58 bits wide] . Writing this register sets the Event Ring.." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERDP5_LO,Event Ring Dequeue Pointer Register (ERDP). The Event Ring Dequeue Pointer Register is written by software to define the Event Ring Dequeue Pointer location to the xHC. Software updates this pointer.." hexmask.long 0x8 4.--31. 1. "ERDPTR,Event Ring Dequeue Pointer RW. Default = 0. This field defines the 28 low order bits of the 64-bit address of the current Event Ring Dequeue Pointer." newline bitfld.long 0x8 3. "EHB,Event Handler Busy [EHB] RW1C. Default = '0'. This flag shall be set to '1' when the IP bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written. Refer to section 4.17.2 of xHCI specification for more information" "0,1" newline bitfld.long 0x8 0.--2. "DESI,Dequeue ERST Segment Index [DESI]. Default = 0. This field may be used by the xHC to accelerate checking the Event Ring full condition. This field is written with the low order 3 bits of the offset of the ERST entry which defines the Event Ring.." "0,1,2,3,4,5,6,7" line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERDP5_HI,Event Ring Dequeue Pointer Register (ERDP). The Event Ring Dequeue Pointer Register is written by software to define the Event Ring Dequeue Pointer location to the xHC. Software updates this pointer.." hexmask.long 0xC 0.--31. 1. "ERDPTR_HI,Event Ring Dequeue Pointer RW. Default = 0. This field defines the 32 high order bits of the 64-bit address of the current Event Ring Dequeue Pointer." line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_IMAN6,Interrupter Management Register (IMAN). The Interrupter Management register allows system software to enable. disable. detect. and force xHC interrupts." hexmask.long 0x10 2.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline bitfld.long 0x10 1. "IE,Interrupt Enable [IE] RW. Default = '0'. This flag specifies whether the Interrupter is capable of generating an interrupt. When this bit and the IP bit are set ['1'] the Interrupter shall generate an interrupt when the Interrupter Moderation.." "0,1" newline bitfld.long 0x10 0. "IP,Interrupt Pending [IP] RW1C. Default = '0'. This flag represents the current state of the Interrupter. If IP = '1' an interrupt is pending for this Interrupter. A '0' value indicates that no interrupt is pending for the Interrupter. Refer to section.." "0,1" line.long 0x14 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_IMOD6,Interrupter Moderation Register (IMOD). The Interrupter Moderation Register controls the interrupt moderation feature of an Interrupter. allowing system software to throttle the interrupt rate generated.." hexmask.long.word 0x14 16.--31. 1. "IMODC,Interrupt Moderation Counter [IMODC] RW. Default = undefined. Down counter. Loaded with the IMODI value whenever IP is cleared to '0' counts down to 0 and stops. The associated interrupt shall be signaled whenever this counter is zero the.." newline hexmask.long.word 0x14 0.--15. 1. "IMODI,Interrupt Moderation Interval [IMODI] RW. Default = 'hFA0' [~1ms]. Minimum inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables interrupt throttling logic and interrupts shall be generated immediately.." line.long 0x18 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTSZ6,Event Ring Segment Table Size Register (ERSTSZ). The Event Ring Segment Table Size Register defines the number of segments supported by the Event Ring Segment Table." hexmask.long.word 0x18 16.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline hexmask.long.word 0x18 0.--15. 1. "ERSTS,Event Ring Segment Table Size RW. Default = 0. This field identifies the number of valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event Ring Segment Table Base Address register. The maximum value.." rgroup.long 0x120EC++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_reserved6,Reserved" hexmask.long 0x0 0.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." rgroup.long 0x120F0++0x1B line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTBA6_LO,The Event Ring Segment Table Base Address Register identifies the start address of the Event Ring Segment Table." hexmask.long 0x0 6.--31. 1. "ERSTBADDR_LO,Event Ring Segment Table Base Address Register RW. Default = 0. This field defines the low order bit [25:0] of the start address of the Event Ring Segment Table [the address is 58 bits wide] . Writing this register sets the Event Ring State.." newline hexmask.long.byte 0x0 0.--5. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTBA6_HI,The Event Ring Segment Table Base Address Register identifies the start address of the Event Ring Segment Table." hexmask.long 0x4 0.--31. 1. "ERSTBADDR_HI,Event Ring Segment Table Base Address Register RW. Default = 0. This field defines the high order bits [57:26] of the start address of the Event Ring Segment Table [the address is 58 bits wide] . Writing this register sets the Event Ring.." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERDP6_LO,Event Ring Dequeue Pointer Register (ERDP). The Event Ring Dequeue Pointer Register is written by software to define the Event Ring Dequeue Pointer location to the xHC. Software updates this pointer.." hexmask.long 0x8 4.--31. 1. "ERDPTR,Event Ring Dequeue Pointer RW. Default = 0. This field defines the 28 low order bits of the 64-bit address of the current Event Ring Dequeue Pointer." newline bitfld.long 0x8 3. "EHB,Event Handler Busy [EHB] RW1C. Default = '0'. This flag shall be set to '1' when the IP bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written. Refer to section 4.17.2 of xHCI specification for more information" "0,1" newline bitfld.long 0x8 0.--2. "DESI,Dequeue ERST Segment Index [DESI]. Default = 0. This field may be used by the xHC to accelerate checking the Event Ring full condition. This field is written with the low order 3 bits of the offset of the ERST entry which defines the Event Ring.." "0,1,2,3,4,5,6,7" line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERDP6_HI,Event Ring Dequeue Pointer Register (ERDP). The Event Ring Dequeue Pointer Register is written by software to define the Event Ring Dequeue Pointer location to the xHC. Software updates this pointer.." hexmask.long 0xC 0.--31. 1. "ERDPTR_HI,Event Ring Dequeue Pointer RW. Default = 0. This field defines the 32 high order bits of the 64-bit address of the current Event Ring Dequeue Pointer." line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_IMAN7,Interrupter Management Register (IMAN). The Interrupter Management register allows system software to enable. disable. detect. and force xHC interrupts." hexmask.long 0x10 2.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline bitfld.long 0x10 1. "IE,Interrupt Enable [IE] RW. Default = '0'. This flag specifies whether the Interrupter is capable of generating an interrupt. When this bit and the IP bit are set ['1'] the Interrupter shall generate an interrupt when the Interrupter Moderation.." "0,1" newline bitfld.long 0x10 0. "IP,Interrupt Pending [IP] RW1C. Default = '0'. This flag represents the current state of the Interrupter. If IP = '1' an interrupt is pending for this Interrupter. A '0' value indicates that no interrupt is pending for the Interrupter. Refer to section.." "0,1" line.long 0x14 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_IMOD7,Interrupter Moderation Register (IMOD). The Interrupter Moderation Register controls the interrupt moderation feature of an Interrupter. allowing system software to throttle the interrupt rate generated.." hexmask.long.word 0x14 16.--31. 1. "IMODC,Interrupt Moderation Counter [IMODC] RW. Default = undefined. Down counter. Loaded with the IMODI value whenever IP is cleared to '0' counts down to 0 and stops. The associated interrupt shall be signaled whenever this counter is zero the.." newline hexmask.long.word 0x14 0.--15. 1. "IMODI,Interrupt Moderation Interval [IMODI] RW. Default = 'hFA0' [~1ms]. Minimum inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables interrupt throttling logic and interrupts shall be generated immediately.." line.long 0x18 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTSZ7,Event Ring Segment Table Size Register (ERSTSZ). The Event Ring Segment Table Size Register defines the number of segments supported by the Event Ring Segment Table." hexmask.long.word 0x18 16.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline hexmask.long.word 0x18 0.--15. 1. "ERSTS,Event Ring Segment Table Size RW. Default = 0. This field identifies the number of valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event Ring Segment Table Base Address register. The maximum value.." rgroup.long 0x1210C++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_reserved7,Reserved" hexmask.long 0x0 0.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." rgroup.long 0x12110++0xF line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTBA7_LO,The Event Ring Segment Table Base Address Register identifies the start address of the Event Ring Segment Table." hexmask.long 0x0 6.--31. 1. "ERSTBADDR_LO,Event Ring Segment Table Base Address Register RW. Default = 0. This field defines the low order bit [25:0] of the start address of the Event Ring Segment Table [the address is 58 bits wide] . Writing this register sets the Event Ring State.." newline hexmask.long.byte 0x0 0.--5. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERSTBA7_HI,The Event Ring Segment Table Base Address Register identifies the start address of the Event Ring Segment Table." hexmask.long 0x4 0.--31. 1. "ERSTBADDR_HI,Event Ring Segment Table Base Address Register RW. Default = 0. This field defines the high order bits [57:26] of the start address of the Event Ring Segment Table [the address is 58 bits wide] . Writing this register sets the Event Ring.." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERDP7_LO,Event Ring Dequeue Pointer Register (ERDP). The Event Ring Dequeue Pointer Register is written by software to define the Event Ring Dequeue Pointer location to the xHC. Software updates this pointer.." hexmask.long 0x8 4.--31. 1. "ERDPTR,Event Ring Dequeue Pointer RW. Default = 0. This field defines the 28 low order bits of the 64-bit address of the current Event Ring Dequeue Pointer." newline bitfld.long 0x8 3. "EHB,Event Handler Busy [EHB] RW1C. Default = '0'. This flag shall be set to '1' when the IP bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written. Refer to section 4.17.2 of xHCI specification for more information" "0,1" newline bitfld.long 0x8 0.--2. "DESI,Dequeue ERST Segment Index [DESI]. Default = 0. This field may be used by the xHC to accelerate checking the Event Ring full condition. This field is written with the low order 3 bits of the offset of the ERST entry which defines the Event Ring.." "0,1,2,3,4,5,6,7" line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ERDP7_HI,Event Ring Dequeue Pointer Register (ERDP). The Event Ring Dequeue Pointer Register is written by software to define the Event Ring Dequeue Pointer location to the xHC. Software updates this pointer.." hexmask.long 0xC 0.--31. 1. "ERDPTR_HI,Event Ring Dequeue Pointer RW. Default = 0. This field defines the 32 high order bits of the 64-bit address of the current Event Ring Dequeue Pointer." rgroup.long 0x13000++0x7 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_DB0,Host Controller Doorbell. The Doorbell Array is organized as an array of up to 256 Doorbell Registers. One 32-bit Doorbell Register is defined in the array for each Device Slot. System software utilizes the.." hexmask.long.word 0x0 16.--31. 1. "DB_STREAM_ID,DB Stream ID RW. Doorbell Stream ID. If the endpoint of a Device Context Doorbell defines Streams then this field shall be used to identify which Stream of the endpoint the doorbell reference is targeting. System software is responsible.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDZ1,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." newline hexmask.long.byte 0x0 0.--7. 1. "DB_TARGET,DB Target RW. Doorbell Target. This field defines the target of the doorbell reference. The table below defines the xHC notification that is generated by ringing the doorbell. Note that Doorbell Register 0 is dedicated to Command Ring and.." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_DB,The Doorbell Array is organized as an array of up to 256 Doorbell Registers. One 32-bit Doorbell Register is defined in the array for each Device Slot. System software utilizes the Doorbell Register to.." hexmask.long.word 0x4 16.--31. 1. "DB_STREAM_ID,DB Stream ID RW. Doorbell Stream ID. If the endpoint of a Device Context Doorbell defines Streams then this field shall be used to identify which Stream of the endpoint the doorbell reference is targeting. System software is responsible.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDZ1,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." newline hexmask.long.byte 0x4 0.--7. 1. "DB_TARGET,DB Target RW. Doorbell Target. This field defines the target of the doorbell reference. The table below defines the xHC notification that is generated by ringing the doorbell. Possible values: 0: Reserved.." rgroup.long 0x18000++0xF line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_PORT_CAP_REG,Extended capability for USB 3.0 Port. This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high. This is a vendor defined.." hexmask.long.byte 0x0 26.--31. 1. "RESERVED1,Reserved RO" newline bitfld.long 0x0 25. "LPM_2_STB_SWITCH_EN,Enable switching to stb_clk." "0,1" newline rbitfld.long 0x0 24. "LPM_2_STB_SWITCH_CAPABLE,xHC is capable of switching to stb_clk." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "XHCI_PORT_CAP_REV,XHCI_PORT_CAP_REV : revision of the Port Capability structure ." newline hexmask.long.byte 0x0 8.--15. 1. "XHCI_PORT_CAPABILITY_DW,XHCI_PORT_CAPABILITY_DW. Next Item Pointer. This field provides an offset pointing to the location of next item in the functions capability list." newline hexmask.long.byte 0x0 0.--7. 1. "XHCI_PORT_CAP_ID,XHCI_PORT_CAP_ID. Port capability ID." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_PORT_1_REG,Extended capability for USB 3.0 Port. This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high. This is a vendor defined.." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved RO" newline bitfld.long 0x4 15. "U1_LFPS_TIME_WR_STROBE,Minimum U1 LFPS generation time write stobe. Returns '0' when read." "0,1" newline hexmask.long.byte 0x4 8.--14. 1. "U1_LFPS_MINGEN_TIME,Minimum U1 LFPS generation time. Written only if U1_LFPS_TIME_WR_STROBE is 1." newline rbitfld.long 0x4 7. "RESERVED5,Reserved RO" "0,1" newline bitfld.long 0x4 6. "CPOLLINGTIMEOUT_EN,Enable cPollingTimeout" "0,1" newline bitfld.long 0x4 5. "TTIME_FOR_RESET_EN,Enable tTimeForResetError timer" "0,1" newline bitfld.long 0x4 4. "SKP_OS_FIX,Change counting number of symbols for SKP OS insertion [only for the 1st SKP OS]" "0,1" newline bitfld.long 0x4 3. "U3_SPUR_LFPS_FIX,Enable filtering out spurious LFPS when entering U3 state" "0,1" newline bitfld.long 0x4 1.--2. "TERM_DEB_MAX,Number of the consecutive lack of Far-end Rx Termination detected that causes transition from SS.Inactive to RxDetect state" "0,1,2,3" newline bitfld.long 0x4 0. "TRAINING_FAIL,When reading: Link Polling training error flag status When writing '1': clear the Link Polling training error flag When writing '0': no effect" "0,1" line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_CDNS_DEBUG_BUS_CAP,xHCI Debug Bus Capability. This is a vendor defined capability. Please refer to Integration Guide for further details of debug bus usage." bitfld.long 0x8 31. "CPU_DEBUG_EN,Debug Bus Enable RW. When 0 allows the xhci_debug_sel primary input to control selection of Debug Bus sources. When 1 allows the cpu_debug_bus_sel field in the XECP_CDNS_DEBUG_BUS_CTRL register to control selection of Debug Bus sources." "0,1" newline hexmask.long.word 0x8 16.--30. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline hexmask.long.byte 0x8 8.--15. 1. "XHCI_DEBUG_BUS_DW,Next Capability Pointer RO. This field indicates the location of the next capability with respect to the effective address of this capability." newline hexmask.long.byte 0x8 0.--7. 1. "XHCI_DEBUG_BUS_CAP_ID,Capability ID RO. This field identifies the extended capability. For xHCI Debug Bus its' value is 196." line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_CDNS_DEBUG_BUS_CTRL,xHCI Debug Bus Control. This is a vendor defined capability. Please refer to Integration Guide for further details of debug bus usage." hexmask.long 0xC 5.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline hexmask.long.byte 0xC 0.--4. 1. "CPU_DEBUG_BUS_SEL,Debug Bus Select RW. Value of this field determines a source of Debug Bus. Default value after reset is 0." rgroup.long 0x18010++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_CDNS_DEBUG_BUS_STATUS,xHCI Debug Bus Status. This is a vendor defined capability. Please refer to Integration Guide for further details of debug bus usage." hexmask.long 0x0 0.--31. 1. "XHCI_DEBUG_BUS,Debug Bus RO. Debug Bus current value. Note for multi-bit probes this register is only suitable for analysing a static value due to simplified clock domain synchronisation" rgroup.long 0x18014++0x1B line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_PM_CAP,Extended Power Management capability register. Defined in section 7.3 of xHCI specification. Reuses power management structures defined in PCI bus Power Management specification. This register may.." hexmask.long.byte 0x0 27.--31. 1. "PME_SUPPORT,Power Management Capabilities: PME_Support. Default = device specific. This 5-bit field indicates the power states in which the function may assert PME#. A value of '0' for any bit indicates that the function is not capable of.." newline rbitfld.long 0x0 26. "D2_SUPPORT,Power Management Capabilities: D2_Support. Default = device specific. If this bit is a '1' this function supports the D2 Power Management State. Functions that do not support D2 must always return a value of '0' for this bit." "0,1" newline rbitfld.long 0x0 25. "D1_SUPPORT,Power Management Capabilities: D1_Support. Default = device specific. If this bit is a '1' this function supports the D1 Power Management State. Functions that do not support D1 must always return a value of '0' for this bit." "0,1" newline bitfld.long 0x0 22.--24. "AUX_CURRENT,Power Management Capabilities: Aux_Current. Default = device specific. This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. If the Data Register field of XECP_PM_PMCSR has been implemented by.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 21. "DSI,Power Management Capabilities: DSI. Default = device specific. The Device Specific Initialization bit indicates whether special initialization of this function is required [beyond the standard PCI configuration header] before the.." "0,1" newline rbitfld.long 0x0 19. "PME_CLOCK,Power Management Capabilities: PME Clock. Default = '0'. When this bit is a '1' it indicates that the function relies on the presence of the PCI clock for PME# operation. When this bit is a '0' it indicates that no PCI clock is required for.." "0,1" newline rbitfld.long 0x0 16.--18. "VERSION,Power Management Capabilities: Version. Default = '011'. A value of '011' indicates that this function complies with revision 1.2 of the PCI Power Management Interface Specification." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "XHCI_PM_CAPABILITY_DW,XHCI_PM_CAPABILITY_DW. Next Item Pointer. This field provides an offset pointing to the location of next item in the functions capability list." newline hexmask.long.byte 0x0 0.--7. 1. "XHCI_PM_CAP_ID,XHCI_PM_CAP_ID. Power Management capability ID." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_PM_PMCSR,Extended Power Management Control/Status register. Defined in section 7.3 of xHCI specification. Reuses power management structures defined in PCI bus Power Management specification. This register.." hexmask.long.byte 0x4 24.--31. 1. "DATA_REGISTER,Data register. This register is used to report the state dependent data requested by the Data_Select field of XECP_PM_PMCSR register. The value of Data register is scaled by the value reported by the Data_Scale field of XECP_PM_PMCSR.." newline rbitfld.long 0x4 23. "BPCC_EN,PMCSR Bridge Support Extensions: BPCC_En [Bus Power/Clock Control Enable]. External strap or internally hardwired. A '1' indicates that the bus power/clock control mechanism as defined in Section 4.7.1 PCI bus Power Management.." "0,1" newline rbitfld.long 0x4 22. "B2_B3,PMCSR Bridge Support Extensions: B2_B3# [B2/B3 support for D3hot]. External strap or internally hardwired. The state of this bit determines the action that is to occur as a direct result of programming the function to D3hot." "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "RESERVED,PMCSR Bridge Support Extensions: reserved" newline bitfld.long 0x4 15. "PME_STATUS,Power Management Control/Status Register: PME_Status. This bit is set when the function would normally assert the PME# signal independent of the state of the PME_En bit. Writing a '1' to this bit will clear it and.." "0,1" newline rbitfld.long 0x4 13.--14. "DATA_SCALE,Power Management Control/Status Register: Data_Scale. Default = device specific. This 2-bit read-only field indicates the scaling factor to be used when interpreting the value of the Data register field of XECP_PM_PMCSR.." "?,?,2: bit read-only field indicates the scaling factor..,?" newline hexmask.long.byte 0x4 9.--12. 1. "DATA_SELECT,Power Management Control/Status Register: Data_Select. Default = zero. This 4-bit field is used to select which data is to be reported through the Data register and Data_Scale fields of XECP_PM_PMCSR register. This.." newline bitfld.long 0x4 8. "PME_EN,Power Management Control/Status Register: PME_En. A '1' in this field enables the function to assert PME#. When '0' PME# assertion is disabled. This bit defaults to '0' if the function does not support PME#.." "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED,Power Management Control/Status Register: reserved" newline rbitfld.long 0x4 3. "NO_SOFT_RESET,Power Management Control/Status Register: No_Soft_Reset. Default = device specific. When set to '1' this bit indicates that devices transitioning from D3hot to D0 because of PowerState commands do not perform an internal reset." "0,1" newline bitfld.long 0x4 2. "RESERVED,Power Management Control/Status Register: reserved" "0,1" newline bitfld.long 0x4 0.--1. "POWERSTATE,Power Management Control/Status Register: PowerState. Default = zero. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. Possible values:.." "?,?,2: bit field is used both to determine the current..,?" line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_MSI_CAP,Message Signaled Interrupts (MSI) configuration register. This register may be read at any time. including whilst the CNR field in the USBSTS register is high. It can be written only when.." hexmask.long.byte 0x8 25.--31. 1. "RESERVED,MSI Message Control: Reserved. Always returns 0 on a read and a write operation has no effect." newline rbitfld.long 0x8 24. "PER_VECTOR_MASKING,MSI Message Control: Per-vector masking capable. If '1' the function supports MSI per-vector masking. If '0' the function does not support MSI per-vector masking. This bit is read only." "0,1" newline rbitfld.long 0x8 23. "AC64,MSI Message Control: 64 bit address capable. If '1' the function is capable of generating sending a 64-bit message address. If '0' the function is not capable of generating sending a 64-bit message.." "0,1" newline bitfld.long 0x8 20.--22. "MSI_MME,MSI Message Control: Multiple Message Enable. Software writes to this field to indicate the number of allocated vectors [equal to or less than the number of requested vectors]. The number of allocated vectors.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 17.--19. "MSI_MMC,MSI Message Control: Multiple Message Capable. System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two [if a.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16. "MSI_EN,MSI Message Control: MSI enable. System configuration software sets this bit to enable MSI. A device driver is prohibited from writing this bit to mask a functions service request. If '0' the.." "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "XECP_MSI_CAP_OFFSET,Pointer to the next item in the capabilities list. A non-zero value in this field indicates a relative offset in 32-bit words from this 32-bit word to the beginning of the next extended capability." newline hexmask.long.byte 0x8 0.--7. 1. "MSI_ID,Capability ID for Message Signaled Interrupts. The value of 05h in this field identifies the function as being MSI capable." line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_MSI_ADDR_L,Message Lower Address for MSI. If the Message Enable bit of MSI Message Control (bit 16 of the XCEP_MSI_CAP register) is set. the contents of this register specify the DWORD-aligned address.." hexmask.long 0xC 2.--31. 1. "MSI_ADDR_LOW,Message Lower Address for MSI. System-specified message address. If the Message Enable bit of MSI Message Control [bit 16 of the XCEP_MSI_CAP register] is set the contents of this register specify the DWORD-aligned address for the MSI.." newline bitfld.long 0xC 0.--1. "RESERVED,Reserved. Always returns zero on read. Write operations have no effect. Those bits are driven to zero during the address phase." "0,1,2,3" line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_MSI_ADDR_H,Message Upper Address for MSI. System-specified message upper address." hexmask.long 0x10 0.--31. 1. "MSI_ADDR_HI,Message Upper Address for MSI. System-specified message upper address. Note: This field should not be written unless the Message Enable bit of MSI Message Control [bit 16 of the XCEP_MSI_CAP register] is cleared. This.." line.long 0x14 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_MSI_DATA,Message data for MSI. This register may be read from to at any time. including whilst the CNR field in the USBSTS register is high. It can be written only when controller is stopped (bit HCH of.." hexmask.long.word 0x14 16.--31. 1. "RSVD,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At present.." newline hexmask.long.word 0x14 0.--15. 1. "MSI_DATA,System-specified message data. If the Message Enable bit of MSI Message Control [bit 16 of the XCEP_MSI_CAP register] is set the message data is driven onto the lower word [bits [15:0]] of the memory write transactions data phase. Bits [31:16].." line.long 0x18 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_AXI_CAP,AXI Master Wrapper Extended Capability. This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high. This is a vendor defined capability." bitfld.long 0x18 31. "AXI_HALT,AXI HALT RW. The AXI Master wrapper's control bit. When set the AXI Master wrapper will complete current CORE REQ [or IRQ] and stop acknowledging next ones. If the xHC is stopped the AXI Master wrapper is halted automatically. If.." "0,1" newline rbitfld.long 0x18 30. "AXI_IDLE,AXI IDLE RO. Information about the AXI Master wrapper state: '0': no pending action required by the AXI Master wrapper '1': the AXI Master wrapper has outstanding transactions. Note: HCH halted bit will not.." "0,1" newline bitfld.long 0x18 29. "AXI_ERROR,AXI ERROR RW1C. Provides an information about AXI ERROR response on B or R channel. This flag is cleared by writing '1' to it. Once set it is held until cleared. The condition setting this register will also assert HSE. This flag may be read.." "0,1" newline rbitfld.long 0x18 27.--28. "RSVDP2,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." "0,1,2,3" newline rbitfld.long 0x18 24.--26. "AXI_DATA_BUS_SIZE,AXI_DATA_WORD_SIZE RO. AXI data buses size capability. It uses AXI AxSIZE Encoding. Values of 64-bit ['011'] or 128-bit ['100'] are supported through compile time configuration." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 23. "AXI_DISABLE_OOO,Disable Out-Of-Order R channel responses [AXI_MASTER_WRAPPER_DISABLE_OOO] RO. This relates to number of IDs used at AXI IF. If Out-Of-Order R channel responses are not disabled this count may be greater than one and in such a.." "0,1" newline rbitfld.long 0x18 22. "AXI_MASTER_WRAPPER_SPLIT_BYTE_BURSTS,AXI_MASTER_WRAPPER_SPLIT_BYTE_BURSTS RO. Presents information about AXI byte burst capability: '0': no byte bursts '1': byte bursts enabled." "0,1" newline hexmask.long.byte 0x18 17.--21. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline rbitfld.long 0x18 16. "AXI_ADDRESS_WIDTH_64,AXI address bus width capability RO. '0': 32-bit address bus width '1': 64-bit address bus width." "0,1" newline hexmask.long.byte 0x18 8.--15. 1. "XECP_AXI_CAP_OFFSET,Next capability Offset RO. This field points to the xHC MMIO space offset of the next xHCI extended capability pointer. A value of 00h indicates the end of the extended capability list. A non-zero value in this register indicates a.." newline hexmask.long.byte 0x18 0.--7. 1. "AXI_CAP_ID,VEND_DEF_AXI_MASTER_WRAPPER_CAP_ID RO. Vendor defined xHCI Extended Capability: 0xC2. This field identifies the AXI wrapper xHCI Extended capability." rgroup.long 0x18030++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_AXI_CFG0,AXI Master Wrapper Extended Capability Configuration Register. This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high." hexmask.long.byte 0x0 24.--31. 1. "AXI_RD_DEPTH,AXI READ_BUFFER_DEPTH RO. Number of AXI Read beats that can be buffered by the AXI Master wrapper. The value written to this field should be the Number of AXI Read beats that can be buffered by the AXI Master wrapper minus 1." newline bitfld.long 0x0 22.--23. "RSVDZ2,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "AXI_MAX_RD_OT,AXI MAX_READ_OUTSTANDING RO. Maximum number of Outstanding Read Transactions initiated by the AXI Master wrapper in AR channel. The value written to this field should be the Maximum number of Outstanding Read Transactions initiated by the.." newline hexmask.long.byte 0x0 8.--15. 1. "AXI_WR_DEPTH,AXI WRITE_BUFFER_DEPTH RO. Number of AXI Write beats that can be buffered by the AXI Master wrapper. The value written to this field should be the number of AXI Write beats that can be buffered by the AXI Master wrapper minus 1." newline bitfld.long 0x0 6.--7. "RSVDZ1,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "AXI_MAX_WR_OT,AXI MAX_WRITE_OUTSTANDING RO. Maximum number of Outstanding Write Transactions initiated by the AXI Master wrapper in AW channel. The value written to this field should be the Maximum number of Outstanding Write Transactions initiated by.." rgroup.long 0x18034++0xB line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_AXI_CTRL0,AXI Master Wrapper Extended Capability Control Register 0. This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high." hexmask.long 0x0 4.--31. 1. "RSVDP,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline hexmask.long.byte 0x0 0.--3. 1. "AXI_BMAX,AXI BMAX RW. The register controls maximum burst length - it is used by the AXI Master wrapper to determine maximum value of AxLEN. It uses AXI AxLEN encoding. Default value is the maximum supported one and it is implementation specific." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_AXI_CTRL1,AXI Master Wrapper Extended Capability Control Register 1. This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high." hexmask.long.word 0x4 22.--31. 1. "RSVDP2,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline hexmask.long.byte 0x4 16.--21. 1. "AXI_ROT,AXI READ_OUTSTANDING RW. Number of outstanding read transactions that can be initiated by the AXI Master wrapper. Default value of this field is MAX_READ_OUTSTANDING-1 [see AXI_MAX_RD_OT field of XECP_AXI_CFG0 register]. Writing value greater.." newline hexmask.long.word 0x4 6.--15. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline hexmask.long.byte 0x4 0.--5. 1. "AXI_WOT,AXI WRITE_OUTSTANDING RW. Number of outstanding write transactions that can be initiated by the AXI Master wrapper. Default value of this field is MAX_WRITE_OUTSTANDING-1 [see AXI_MAX_WR_OT field of XECP_AXI_CFG0]. Writing value greater than the.." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_AXI_CTRL2,AXI Master Wrapper Extended Capability Control Register 2. This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high." hexmask.long.tbyte 0x8 8.--31. 1. "RSVDP,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline hexmask.long.byte 0x8 0.--7. 1. "AXI_WTHRES,AXI Write Buffer Threshold RW. When performing an AXI write burst this field specifies the minimum number of required AXI beats buffered prior to starting the burst on AXI W-Channel by asserting wvalid. This allows.." rgroup.long 0x18040++0x1B line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_SUPP_USB2_CAP0,xHCI Supported Protocol Capability." hexmask.long.byte 0x0 24.--31. 1. "MAJOR_REV,Major Specification Release Number in Binary-Coded Decimal [i.e. version 3.x is 03h]. This field identifies the major release number component of the specification with which the xHC is compliant." newline hexmask.long.byte 0x0 16.--23. 1. "MINOR_REV,Minor Specification Release Number in Binary-Coded Decimal [i.e. version x.10 is 10h]. This field identifies the minor release number component of the specification with which the xHC is compliant." newline hexmask.long.byte 0x0 8.--15. 1. "NEXTCAPID,This field indicates the location of the next capability with respect to the effective address of this capability. Refer to Table 142 of xHCI specification for more information on this field." newline hexmask.long.byte 0x0 0.--7. 1. "PID,Capability ID. The value identifies the capability as Supported Protocol." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_SUPP_USB2_CAP1,xHCI Supported Protocol Capability." hexmask.long 0x4 0.--31. 1. "USB_STRING,Name String RO. This field is a mnemonic name string that references the specification with which the xHC is compliant. Four ASCII characters may be defined. Allowed characters are: alphanumeric space and.." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_SUPP_USB2_CAP2,xHCI Supported Protocol Capability. USB 2.0 protocol" hexmask.long.byte 0x8 28.--31. 1. "PSIC,Protocol Speed ID Count: 3 USB 2.0 Speed [High Full Low]. This field indicates the number of Protocol Speed ID [PSI] Dwords that the xHCI Supported Protocol Capability data structure contains. If this field is non-zero then all speeds supported.." newline hexmask.long.byte 0x8 21.--27. 1. "RSVDP_2,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline bitfld.long 0x8 20. "HLC_BESL,HLC_BESL. In xHCI 1.0 specification this field is reserved RsvdP see section 7.2.2.1.3. The field is described in xHCI 1.1 specification: BESL LPM Capability [BLC] RO. Default = Implementation dependent. If this bit.." "0,1" newline bitfld.long 0x8 19. "HLC,Hardware LPM Capability. Default = Implementation dependent. If this bit is set to '1' the ports described by this xHCI Supported Protocol Capability support hardware controlled USB2 Link Power Management. Refer to section.." "0,1" newline bitfld.long 0x8 18. "IHI,Integrated Hub Implemented. Default = Implementation dependent. If this bit is cleared to '0' the Root Hub to External xHC port mapping adheres to the default mapping described in section 4.24.2.1 of xHCI specification. If this bit is.." "0,1" newline bitfld.long 0x8 17. "HSO,High-speed Only. Default = Implementation dependent. If this bit is cleared to '0' the USB2 ports described by this capability are Low- Full- and High-speed capable. If this bit is set to '1' the USB2 ports described by this.." "0,1" newline bitfld.long 0x8 16. "L1C,If '1'LPM is supported [mandatory in xHCI1_00]. In xHCI specification this field is reserved RsvdP see section 7.2.2.1.3" "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "COMPATIBLE_PORT_COUNT,This field identifies the number of consecutive Root Hub Ports [starting at the Compatible Port Offset] that support this protocol. Valid values are 1 to MaxPorts." newline hexmask.long.byte 0x8 0.--7. 1. "COMPATIBLE_PORT_OFFSET,This field specifies the starting Port Number of Root Hub Ports that support this protocol. Valid values are 1 to MaxPorts." line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_SUPP_USB2_PROTOCOL_SLOT_TYPE,Protocol Slot Type. xHCI Supported Protocol Capability" hexmask.long 0xC 5.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline hexmask.long.byte 0xC 0.--4. 1. "PST,This field specifies the Protocol Slot Type value which may be specified when allocating Device Slots that support this protocol. Valid values are 0 to 31. Refer to sections 4.6.3 and 7.2.2.1.4 of xHCI specification." line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_PSI_FULL_SPEED,Protocol Speed ID. xHCI Supported Protocol Capability" hexmask.long.word 0x10 16.--31. 1. "PSIM,Protocol Speed ID Mantissa. This field defines the mantissa that shall be applied to the PSIE when calculating the maximum bit rate represented by this PSI Dword." newline hexmask.long.byte 0x10 9.--15. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline bitfld.long 0x10 8. "PFD,PSI Full-duplex. If this bit is '1' the link is full-duplex and if '0' the link is half-duplex." "0,1" newline bitfld.long 0x10 6.--7. "PLT,PSI Type. This field identifies whether the PSI Dword defines a symmetric or asymmetric bit rate and if asymmetric then this field also indicates if this Dword defines the receive or transmit bit rate. Note that the.." "0: Symmetric [Single PSI Dword],1: Reserved,2: Asymmetric Rx [Paired with Asymmetric Tx PSI..,3: Asymmetric Tx [Immediately follows Rx Asymmetric.." newline bitfld.long 0x10 4.--5. "PSIE,Protocol Speed ID Exponent. This field defines the base 10 exponent times 3 that shall be applied to the Protocol Speed ID Mantissa when calculating the maximum bit rate represented by this PSI Dword. PSIE Values and.." "0: Bits per second,1: Kb/s,2: Mb/s,3: Gb/s" newline hexmask.long.byte 0x10 0.--3. 1. "PSIV,Protocol Speed ID Value. If a device is attached that operates at the bit rate defined by this PSI Dword then the value of this field shall be reported in the Port Speed field of PORTSC register [5.4.8 of xHCI specification] of a.." line.long 0x14 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_PSI_LOW_SPEED,Protocol Speed ID. xHCI Supported Protocol Capability" hexmask.long.word 0x14 16.--31. 1. "PSIM,Protocol Speed ID Mantissa. This field defines the mantissa that shall be applied to the PSIE when calculating the maximum bit rate represented by this PSI Dword." newline hexmask.long.byte 0x14 9.--15. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline bitfld.long 0x14 8. "PFD,PSI Full-duplex. If this bit is '1' the link is full-duplex and if '0' the link is half-duplex." "0,1" newline bitfld.long 0x14 6.--7. "PLT,PSI Type. This field identifies whether the PSI Dword defines a symmetric or asymmetric bit rate and if asymmetric then this field also indicates if this Dword defines the receive or transmit bit rate. Note that the.." "0: Symmetric Single [PSI Dword],1: Reserved,2: Asymmetric Rx [Paired with Asymmetric Tx PSI..,3: Asymmetric Tx [Immediately follows Rx Asymmetric.." newline bitfld.long 0x14 4.--5. "PSIE,Protocol Speed ID Exponent. This field defines the base 10 exponent times 3 that shall be applied to the Protocol Speed ID Mantissa when calculating the maximum bit rate represented by this PSI Dword. PSIE Values and.." "0: Bits per second,1: Kb/s,2: Mb/s,3: Gb/s" newline hexmask.long.byte 0x14 0.--3. 1. "PSIV,Protocol Speed ID Value. If a device is attached that operates at the bit rate defined by this PSI Dword then the value of this field shall be reported in the Port Speed field of PORTSC register [5.4.8 of xHCI specification] of a.." line.long 0x18 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_PSI_HIGH_SPEED,Protocol Speed ID. xHCI Supported Protocol Capability" hexmask.long.word 0x18 16.--31. 1. "PSIM,Protocol Speed ID Mantissa. This field defines the mantissa that shall be applied to the PSIE when calculating the maximum bit rate represented by this PSI Dword." newline hexmask.long.byte 0x18 9.--15. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline bitfld.long 0x18 8. "PFD,PSI Full-duplex. If this bit is '1' the link is full-duplex and if '0' the link is half-duplex." "0,1" newline bitfld.long 0x18 6.--7. "PLT,PSI Type. This field identifies whether the PSI Dword defines a symmetric or asymmetric bit rate and if asymmetric then this field also indicates if this Dword defines the receive or transmit bit rate. Note that the.." "0: Symmetric Single [PSI Dword],1: Reserved,2: Asymmetric Rx [Paired with Asymmetric Tx PSI..,3: Asymmetric Tx [Immediately follows Rx Asymmetric.." newline bitfld.long 0x18 4.--5. "PSIE,Protocol Speed ID Exponent. This field defines the base 10 exponent times 3 that shall be applied to the Protocol Speed ID Mantissa when calculating the maximum bit rate represented by this PSI Dword. PSIE Values and.." "0: Bits per second,1: Kb/s,2: Mb/s,3: Gb/s" newline hexmask.long.byte 0x18 0.--3. 1. "PSIV,Protocol Speed ID Value. If a device is attached that operates at the bit rate defined by this PSI Dword then the value of this field shall be reported in the Port Speed field of PORTSC register [5.4.8 of xHCI specification] of a.." rgroup.long 0x18060++0x13 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_SUPP_USB3_CAP0,xHCI Supported Protocol Capability." hexmask.long.byte 0x0 24.--31. 1. "MAJOR_REV,Major Specification Release Number in Binary-Coded Decimal [i.e. version 3.x is 03h]. This field identifies the major release number component of the specification with which the xHC is compliant." newline hexmask.long.byte 0x0 16.--23. 1. "MINOR_REV,Minor Specification Release Number in Binary-Coded Decimal [i.e. version x.10 is 10h]. This field identifies the minor release number component of the specification with which the xHC is compliant." newline hexmask.long.byte 0x0 8.--15. 1. "NEXTCAPID,This field indicates the location of the next capability with respect to the effective address of this capability. Refer to Table 142 of xHCI specification for more information on this field." newline hexmask.long.byte 0x0 0.--7. 1. "PID,Capability ID. The value identifies the capability as Supported Protocol." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_SUPP_USB3_CAP1,xHCI Supported Protocol Capability." hexmask.long 0x4 0.--31. 1. "USB_STRING,Name String RO. This field is a mnemonic name string that references the specification with which the xHC is compliant. Four ASCII characters may be defined. Allowed characters are: alphanumeric space and.." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_SUPP_USB3_CAP2,xHCI Supported Protocol Capability. USB 3.0 protocol" hexmask.long.byte 0x8 28.--31. 1. "PSIC,Protocol Speed ID CountCount : 1 USB 3.0 Speed [Super Speed]. This field indicates the number of Protocol Speed ID [PSI] Dwords that the xHCI Supported Protocol Capability data structure contains. If this field is non-zero then all.." newline hexmask.long.word 0x8 16.--27. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline hexmask.long.byte 0x8 8.--15. 1. "COMPATIBLE_PORT_COUNT,This field identifies the number of consecutive Root Hub Ports [starting at the Compatible Port Offset] that support this protocol. Valid values are 1 to MaxPorts." newline hexmask.long.byte 0x8 0.--7. 1. "COMPATIBLE_PORT_OFFSET,This field specifies the starting Port Number of Root Hub Ports that support this protocol. Valid values are 1 to MaxPorts." line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_SUPP_USB3_PROTOCOL_SLOT_TYPE,Protocol Slot Type. xHCI Supported Protocol Capability" hexmask.long 0xC 5.--31. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline hexmask.long.byte 0xC 0.--4. 1. "PST,This field specifies the Protocol Slot Type value which may be specified when allocating Device Slots that support this protocol. Valid values are 0 to 31. Refer to sections 4.6.3 and 7.2.2.1.4 of xHCI specification." line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_PSI_SUPER_SPEED,Protocol Speed ID. xHCI Supported Protocol Capability" hexmask.long.word 0x10 16.--31. 1. "PSIM,Protocol Speed ID Mantissa. This field defines the mantissa that shall be applied to the PSIE when calculating the maximum bit rate represented by this PSI Dword." newline hexmask.long.byte 0x10 9.--15. 1. "RSVDP1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline bitfld.long 0x10 8. "PFD,PSI Full-duplex. If this bit is '1' the link is full-duplex and if '0' the link is half-duplex." "0,1" newline bitfld.long 0x10 6.--7. "PLT,PSI Type. This field identifies whether the PSI Dword defines a symmetric or asymmetric bit rate and if asymmetric then this field also indicates if this Dword defines the receive or transmit bit rate. Note that the.." "0: Symmetric Single [PSI Dword],1: Reserved,2: Asymmetric Rx [Paired with Asymmetric Tx PSI..,3: Asymmetric Tx [Immediately follows Rx Asymmetric.." newline bitfld.long 0x10 4.--5. "PSIE,Protocol Speed ID Exponent. This field defines the base 10 exponent times 3 that shall be applied to the Protocol Speed ID Mantissa when calculating the maximum bit rate represented by this PSI Dword. PSIE Values and.." "0: Bits per second,1: Kb/s,2: Mb/s,3: Gb/s" newline hexmask.long.byte 0x10 0.--3. 1. "PSIV,Protocol Speed ID Value. If a device is attached that operates at the bit rate defined by this PSI Dword then the value of this field shall be reported in the Port Speed field of PORTSC register [5.4.8 of xHCI specification] of a.." rgroup.long 0x18080++0x17 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_CMDM_STS0,Command Ring related status register. Command manager status debug register. This is a vendor defined capability. This register is reserved. This register should not be modified by software. It.." bitfld.long 0x0 31. "IDMA_CNTX_IN_USE,Indicates that IDMA module currently owns the context access :" "0,1" newline bitfld.long 0x0 30. "ODMA_CNTX_IN_USE,Indicates that ODMA module currently owns currently the context access" "0,1" newline bitfld.long 0x0 29. "TRM_CNTX_IN_USE,Indicates that TRM modules owns the context access currently" "0,1" newline bitfld.long 0x0 28. "CMDM_CNTX_LOCK_REQ,Indicates that Command Manager has requested a context lock." "0,1" newline bitfld.long 0x0 27. "CMDM_STOP_REQ,Indicates that Command Ring stop command is in progress." "0,1" newline bitfld.long 0x0 26. "CMDM_CLR_DB_REQ,Indicates that clearing an EP out of schedule is in progress." "0,1" newline bitfld.long 0x0 25. "ODMA_ADDRESS_DEV_DONE,Indicates that current address device command is done by ODMA." "0,1" newline bitfld.long 0x0 24. "ODMA_ADDRESS_DEV_PENDING,Indicates that ODMA has an address device command in progress." "0,1" newline bitfld.long 0x0 23. "UPDATE_ENDPT_ACTIVE,Indicates that updating of EP state is in progress" "0,1" newline bitfld.long 0x0 22. "DBM_EP_UPD_REQ,Indicates that Doorbell Manager is issuing and EP update due to a doorbell ring on an EP that is in stop state" "0,1" newline bitfld.long 0x0 21. "TRM_EPERR_UPD_REQ,Indicates that Transfer Ring Manager is issuing and EP update due to an EP error condition detected" "0,1" newline bitfld.long 0x0 20. "TRM_STALL_REQ,Indicates that transfer ring manager is issuing and EP state update due to stall received" "0,1" newline bitfld.long 0x0 19. "RESERVED_R,Reserved field RO" "0,1" newline bitfld.long 0x0 18. "STOPPING_CMD_RING,Indicates that a STOP on the Command Ring is in progress" "0,1" newline bitfld.long 0x0 17. "HOST_CMD_DB_RANG_STICKY,Indicates that command ring has a doorbell pending" "0,1" newline bitfld.long 0x0 16. "CMD_RUNNING,Indicates that the command ring is running" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "XECP_CMDM_NEXT_CAP_OFFSET,Next capability offset" newline hexmask.long.byte 0x0 0.--7. 1. "VEND_DEF_CMDM_CAP_ID_193,Vendor defined capability ID. Command Ring Manager capability ID." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_CMDM_RESERVED_1,Event ring manager module reserved space. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for.." hexmask.long 0x4 0.--31. 1. "RESERVED_R,Reserved field RO." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_CMDM_RESERVED_2,Event ring manager module reserved space. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for.." hexmask.long 0x8 0.--31. 1. "RESERVED_R,Reserved field RO." line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_CMDM_RESERVED_3,Event ring manager module reserved space. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for.." hexmask.long 0xC 0.--31. 1. "RESERVED_R,Reserved field RO." line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_CMDM_RESERVED_4,Event ring manager module reserved space. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for.." hexmask.long 0x10 0.--31. 1. "RESERVED_R,Reserved field RO." line.long 0x14 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_CMDM_RESERVED_5,Event ring manager module reserved space. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for.." hexmask.long 0x14 0.--31. 1. "RESERVED_R,Reserved field RO." rgroup.long 0x18098++0xB line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_CMDM_CTRL_REG1,Command Manager Control register 1. This register contains fields which control the behavior of the Command Manager in the xHCI. The functions controlled by this register are made available.." hexmask.long.byte 0x0 28.--31. 1. "DEFAULT_INTR_EP_BANDWIDTH,Bandwidth calculation parameter: Default bandwidth for an Interrupt Endpoint." newline hexmask.long.byte 0x0 24.--27. 1. "DEFAULT_ISOCH_EP_BANDWIDTH,Bandwidth calculation parameter: Default bandwidth for an Isochronous Endpoint." newline bitfld.long 0x0 23. "EVAL_CNTX_BW_SCAN_EN,Enable the Host Controller's Bandwidth checks for the Evaluate Context Command. Rescan the BW during evaluate context" "0,1" newline bitfld.long 0x0 22. "FEATURE_RETRY_EN,Enable the EOB and NPKT==0 [called NYET condition for USB3] to be used to update a retry bit during stream switching operation. This is an internal safety feature. It should be treated as reserved bit." "0,1" newline bitfld.long 0x0 21. "CFG_ENDPT_CNTX_LOCK_DIS,Context lock mechanism to ensure command manager has exclusive access to internal context. This is a disable bit to allow software to turn off the context lock for configure endpoint command. This is a test/debug feature." "0,1" newline bitfld.long 0x0 20. "ENABLE_MAX_EP_CACHE,enable_max_ep_cache" "0,1" newline bitfld.long 0x0 19. "REPORT_BANDWIDTH_SKIP_SCAN,report_bandwidth_skip_scan" "0,1" newline bitfld.long 0x0 18. "FORCE_BANDWIDTH_SYS_PASS,force_bandwidth_sys_pass" "0,1" newline bitfld.long 0x0 17. "FORCE_BANDWIDTH_PASS,force_bandwidth_pass" "0,1" newline bitfld.long 0x0 16. "CLR_SPLIT_STATE_WITH_TSPSET,This bit allows engine to reset the split states when reset endpoint with TSP is posted. The split state is an internal context field in DMA engine. '0': Indicates that reset endpoint with TSP will preserve the.." "0,1" newline bitfld.long 0x0 15. "CLR_EP_CNTX_4DIS_SLOT,'0': Disable clearing internal TRM and DMA context as well as the internal EP status signals during a disable slot command. '1': Enable clearing internal TRM and DMA context as well as the internal EP status signals.." "0,1" newline bitfld.long 0x0 14. "EVAL_EPST_CHECK_EN,'0': Disable evaluating the endpoint state during an Evaluate Context command '1': Enable EP state check during an Evaluate Context command. If failed context error will be returned." "0,1" newline bitfld.long 0x0 13. "INIT_RETRY,init_retry. Reserved to always read value of '1'." "0,1" newline bitfld.long 0x0 12. "GLOB_TSP_EN,'0': Disable the global context preservation. '1': Enable the internal context preservation for all commands that needs to preserve some of the internal context fields as a command with TSP would." "0,1" newline bitfld.long 0x0 11. "CLR_EP_CNTX_4CFG_ENDPT,'0': Disable clearing other internal EP status signals during a configure endpoint command. '1': Enable clearing other internal EP related status signals such as EP scheduled array credit stored per EP etc. during a.." "0,1" newline bitfld.long 0x0 10. "CLR_EP_CNTX_4RST_DEVICE,'0': Disable clearing other internal EP status signals during a reset device command. '1': Enable clearing other internal EP related status signals such as EP scheduled array credit stored per EP etc. during a reset.." "0,1" newline bitfld.long 0x0 9. "CLR_EP_CNTX_4RST_ENDPT,'0': Disable clearing other internal EP status signals during a reset endpoint command. '1': Enable clearing other internal EP related status signals such as EP scheduled array credit stored per EP. etc. during a reset.." "0,1" newline bitfld.long 0x0 8. "CLR_EP_CNTX_4EN_SLOT,'0': Disable clearing other internal EP status signals during an enable slot command. '1': Enable clearing other internal EP related status signals such as EP scheduled array credit stored per EP. etc. during an enable.." "0,1" newline bitfld.long 0x0 7. "CLR_CNTX_4ENCFGENDPT,'0': Disable clearing internal TRM and DMA context during a configure endpoint command. '1': Enable clearing internal TRM and DMA context during a configure endpoint command." "0,1" newline bitfld.long 0x0 6. "CLR_CNTX_4ENADDR,'0': Disable clearing internal TRM and DMA context during an address device command. '1': Enable clearing internal TRM and DMA context during an address device command." "0,1" newline bitfld.long 0x0 5. "CLR_CNTX_4ENSLOT_REG,'0': Disable clearing internal TRM and DMA context during an enable slot command. '1': Enable clearing internal TRM and DMA context during an enable slot command." "0,1" newline bitfld.long 0x0 4. "CLR_CNTX_4RSTDEV,'0': Disable clearing internal TRM and DMA context during a reset device command. '1': Enable clearing internal TRM and DMA context during a reset device command." "0,1" newline bitfld.long 0x0 3. "ADDR_DEV_SLST_BSR_CHECK_EN,'0': Address device does not return the error for this condition. '1': Enable the EP state [default state] check with address device command with BSR. If failed an event with context state error will be generated." "0,1" newline bitfld.long 0x0 2. "CLR_CNTX_4SETDQPTR,'0': Disable clearing internal TRM and DMA context during a set TR DQ pointer command. '1': Enable clearing internal TRM and DMA context during a set TR DQ pointer command." "0,1" newline bitfld.long 0x0 1. "FORCE_BANDWIDTH_FAIL,'0': Bandwidth calculation handled normally. '1': Forces a failure in the endpoint bandwidth calculation so that engine will reject a configure EP command." "0,1" newline bitfld.long 0x0 0. "UPDATE_ENDPT_EVENT_ENABLE,'0': Disable generation of the completion event. '1': Enable the command manager to generate a completion event after an EP state update due to internal error. This bit is for test debug." "0,1" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_CMDM_CTRL_REG2,Command Manager Control register 2. This register contains fields which control the behavior of the Command Manager in the xHCI. The functions controlled by this register are made available.." bitfld.long 0x4 31. "DOING_2DW_OCNTX_WR_EN,Enable only to update the EP state to output context on every EP output context update condition. This is to allow to have a control over either update the entire EPoutput context field or only update the first two DWORDs." "0,1" newline bitfld.long 0x4 30. "STOP_ENDPT_2MS_TIMEOUT_EN,Enable a delay to stop endpoint command that is executed in XFER engine. '0': XFER engine will not wait. '1': XFER engine will always wait for 2 ms before it checks whether an EP transfer ring is at a.." "0,1" newline bitfld.long 0x4 29. "SLOT_ID_OVERIDE_EN,Force '0' on slot ID when a command transfer event is generated. '0': not forced '1': Forced to 0." "0,1" newline bitfld.long 0x4 28. "SRE,Force and error on save command always. '0': do not force '1': always force return save error." "0,1" newline bitfld.long 0x4 27. "ALL_CLK_GATE_DIS,'0': Turn ON the TTE clock. '1': Turn OFF the TTE clock." "0,1" newline bitfld.long 0x4 26. "CLR_EP_CNTX_4STOP_ENDPT,'0': Disable clearing other internal per EP status signal during a stop endpoint command. '1': Enable clearing other internal per EP status signal during a stop endpoint command." "0,1" newline bitfld.long 0x4 25. "CLR_EP_CNTX_4STALL_UPD,'0': Disable clearing other internal EP status signal during stall handling. '1': Enable clearing other internal EP status signal during stall handling." "0,1" newline bitfld.long 0x4 24. "MOVE_XFER_DQPTR_2CPL_DQPTR_EN,'0': The internal context write DQ pointer moved to internal read pointer during reset EP command. '1': The write DQ pointer stays as it was during reset endpoint command." "0,1" newline bitfld.long 0x4 23. "CLR_CNTX_4RST_ENDPT_REG,'0': Disable clearing internal TRM and DMA context during a reset endpoint command. '1': Enable clearing internal TRM and DMA context during a reset endpoint command." "0,1" newline bitfld.long 0x4 22. "ENABLE_BW_CAL,'0': Disable hardware bandwidth calculations. '1': Enable hardware bandwidth calculations." "0,1" newline bitfld.long 0x4 21. "CMD_ST_DIS_REG,'0': Delay processing command ring TRB while internal context requests are pending. '1': Process command ring TRBs normally." "0,1" newline bitfld.long 0x4 20. "SET_DQPTR_CLR_EP_ARYS,'0': Disable clearing other internal EP status signals during a set DQ pointer command. '1': Enable clearing other internal EP status signals during a set DQ pointer command." "0,1" newline bitfld.long 0x4 19. "FORCE_RESET_ENDPT_REG,'0': Check the slot and endpoint state prior to processing a reset endpoint command. '1': Ignore the slot and endpoint state when processing a reset endpoint command." "0,1" newline bitfld.long 0x4 18. "TSP_4SET_DQPTR_REG,'0': Disable sequence number preservation during set DQ pointer command. '1': Enable sequence number to be preserved during set DQ pointer command." "0,1" newline bitfld.long 0x4 17. "TRM_BREAK_LOOP_EN,trm_break_loop_en. This is an internal safeguard register. It enables a different mechanism of handling stop endpoint command. It should be treated as a reserved field. The default should not be alternate unless specific.." "0,1" newline bitfld.long 0x4 16. "INCREASE_UPDATE_EP_PRIORITY_EN,Increase Update EP priority over commands in the command ring to avoid prolonging STALL handling. '0': Pending commands have a higher priority than update endpoint processing. '1': Update endpoint.." "0,1" newline bitfld.long 0x4 15. "DISABLE_STALL_CLR_EP,'0': Stall handling does clear the internal EP status signals. '1': Disable the clear function when stall response received." "0,1" newline bitfld.long 0x4 14. "BURST_SIZE_DEFAULT_EN,When context is first initialized it is assumed one remote NPKT. It is also assumed that max burst size as remote NPKT. This bit enables to assume max burst size as remote NPKT. '0': Assume 1 NPKT." "0,1" newline hexmask.long.word 0x4 0.--13. 1. "CLR_ST,Clear state machine present state: Setting a specified bit to '1' will reset the corresponding command manager state machine to the starting/idle state. bit-0: disable slot state machine. bit-1: enable.." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_CMDM_CTRL_REG3,Command Manager Control register 3. This register contains fields which control the behavior of the Command Manager in the xHCI. The functions controlled by this register are made available.." bitfld.long 0x8 31. "FRINDEX_WR_EN,MFIndex register write enable. For debug purposes." "0,1" newline bitfld.long 0x8 30. "IGNORE_HI_ATOMIC_EN,ignore_hi_atomic_en" "0,1" newline bitfld.long 0x8 29. "EXTRA_DB_RM_4STOP_EN,extra_db_rm_4stop_en" "0,1" newline bitfld.long 0x8 28. "DISABLE_NON0EP_CNTX_CLR,disable_non0ep_cntx_clr" "0,1" newline bitfld.long 0x8 27. "DISABLE_SETDQPTR_CLR_STREAM_ST,disable_setdqptr_clr_stream_st. Disable setTRDQPtr from clearing the current stream state." "0,1" newline bitfld.long 0x8 26. "UPDATE_CNTX_WHEN_STOPPED,update_cntx_when_stopped. Allow setTRDQPtr cmd to update the local context anytime the EP is not running [otherwise checks CSTREAMID]." "0,1" newline bitfld.long 0x8 25. "STOP_EP_CLR_LCSTREAM_ID_EN,stop_ep_clr_lcstream_id_en. Enable stop endpoint command to return stream st to disabled [0] in EP context." "0,1" newline bitfld.long 0x8 24. "SET_BURST_SIZE_4PRDC_DIS,set_burst_size_4prdc_dis" "0,1" newline bitfld.long 0x8 23. "STREAM_ALWAYS_UPDATE_CNTX,stream_always_update_cntx" "0,1" newline bitfld.long 0x8 22. "ALLOW_CLR_4STOP,allow_clr_4stop" "0,1" newline bitfld.long 0x8 21. "STOP_EP_CLR_STREAM_ST_EN,stop_ep_clr_stream_st_en. Enable stop endpoint command to return stream st to disabled [0] in EP context." "0,1" newline bitfld.long 0x8 20. "BREAK_CNTX_LOCK_EN,break_cntx_lock_en" "0,1" newline bitfld.long 0x8 19. "STOP_2TIMEOUT_EN,stop_2timeout_en. Stop transaction timeout." "0,1" newline bitfld.long 0x8 18. "CLR_TRM_DMA_CNTX_EN,clr_trm_dma_cntx_en" "0,1" newline bitfld.long 0x8 16.--17. "DISABLE_SLOT_TIMER_SELECT,These two bits specify the delay that we can have for disable slot state to be completed. We can delay the generation of the command transfer event during disable slot command. Possible values: '00': delay is.." "0,1,2,3" newline hexmask.long.byte 0x8 8.--15. 1. "DEFAULT_HS_BANDWD_AVAIL,The default available bandwidth to advertise on each HS port in 10 0ncrements [80%]. Bandwidth Calculation is a reserved field for PPT." newline hexmask.long.byte 0x8 0.--7. 1. "DEFAULT_PORT_BANDWD_AVAIL,The default available bandwidth to advertise on each LS FS SS port in 10 0ncrements [90%]. Bandwidth calculation is a reserved field for PPT." rgroup.long 0x180B0++0x7 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_CAP,This is a register that describes the host controller's extended capability location. It is modified and maintained by BIOS." hexmask.long.word 0x0 16.--31. 1. "RESERVED_R,Reserved field RO." newline hexmask.long.byte 0x0 8.--15. 1. "XECP_HOST_NEXT_CAP_OFFSET,Next xHCI Extended Capability Pointer. This field points to the xHC MMIO space offset of the next xHCI extended capability pointer. A value of 00h indicates the end of the extended capability list. A non-zero value in this.." newline hexmask.long.byte 0x0 0.--7. 1. "VEND_DEF_HOST_CAP_ID_192,Capability ID. This field identifies the xHCI Extended capability. 192-255 are IDs available for vendor specific extensions to the xHCI." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_RSVD,Reserved space. This register is reserved. This register should not be accessed by software. It is described only for informative purposes." hexmask.long 0x4 0.--31. 1. "RESERVED,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." rgroup.long 0x180B8++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CLR_MASK_REG,Override Endpoint Flow Control. This is a register that is used to clear the internal scheduler's mask that is used to stop scheduling a particular Endpoint. Allows software to clear.." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_R,Reserved field RO" newline hexmask.long.byte 0x0 5.--9. 1. "SLOT_NUM,Slot number." newline hexmask.long.byte 0x0 1.--4. 1. "EP_NUM,Endpoint number" newline bitfld.long 0x0 0. "EP_DIR,Indicates the direction of the Endpoint" "0,1" rgroup.long 0x180BC++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CLR_IN_EP_VALID_REG,Clear Active IN EP ID Control. This register is used to clear the internal valid IN EP array that TRM stored in order to guarantee one IN EP per port. This register allows software.." hexmask.long 0x0 0.--31. 1. "PORT_NUM,This field indicates the port number." rgroup.long 0x180C0++0x7 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CLR_PMASK_REG,Clear Poll Mask Control. This is a register that is used to clear the internal scheduler's poll mask that is used to indicate whether we need to poll this EP. This is used for USB2. This.." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_R,Reserved field RO" newline hexmask.long.byte 0x0 5.--9. 1. "SLOT_NUM,Slot number" newline hexmask.long.byte 0x0 1.--4. 1. "EP_NUM,Endpoint number" newline bitfld.long 0x0 0. "EP_DIR,Indicates the direction of the Endpoint" "0,1" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_OCRD_REG,Port Credit Control. This is a register that is used to add or subtract a per port credit or to control the TRM's XFER and CPL states. This is a vendor defined capability. This register.." bitfld.long 0x4 31. "CLR_XFER_ST,Write '1' to force XFER state return to IDLE" "0,1" newline bitfld.long 0x4 30. "CLR_CPL_ST,Write '1' to force CPL state return to IDLE" "0,1" newline bitfld.long 0x4 29. "PLUS_OCRD,Add one credit to a port" "0,1" newline bitfld.long 0x4 28. "MINUS_OCRD,Subtract one credit from a port" "0,1" newline bitfld.long 0x4 27. "MINUS_4RFIFO,Indicates whether the subtract command operates on TX FIFO credit or RX FIFO credit." "0,1" newline rbitfld.long 0x4 26. "ST_UPD_REG,Slot state control. st_upd_reg" "0,1" newline hexmask.long.tbyte 0x4 8.--25. 1. "RESERVED_R,Reserved field RO" newline hexmask.long.byte 0x4 0.--7. 1. "PORT_NUM,port number" rgroup.long 0x180C8++0x7 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_TEST_BUS_LO,Test Bus Low Bits: Host controller test bus low 32 bits. The register is used to read the internal states and other important signals. The host control test bus is gathered from.." hexmask.long 0x0 0.--31. 1. "TEST_BUS_LO,Host controller test bus low 32-bits." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_TEST_BUS_HI,Test Bus High Bits: Host controller test bus high 32 bits. This register is used to read the internal states and other important signals. The host control test bus is gathered from.." hexmask.long 0x4 0.--31. 1. "TEST_BUS_HI,Host controller test bus high 32-bits." rgroup.long 0x180D0++0x13 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_TRM_REG1,Host Control Transfer Manager (TRM) register. This register contains fields. which control the behavior of the Transfer Manager in the xHCI. The functions controlled by this register are.." bitfld.long 0x0 31. "TRB_PACE_EN,Must be set to '0'." "0,1" newline bitfld.long 0x0 30. "USB2_NAK_AUTO_DETECT_REG_EN,'0': Disables a special function which detects NAK received and goes into a single packet pace mode so that we do not burst ahead. '1': Enables a special function which detects NAK received and goes into a single.." "0,1" newline bitfld.long 0x0 29. "DISABLE_CPL_SST_MDATA_ERR,'0': Enable the error check. '1': Disable the error check for Data Move stream state. It will generate a transfer event with prime PIPE error completion code if an error is detected." "0,1" newline bitfld.long 0x0 28. "DISABLE_CPL_SST_PPIPE_ERR,'0': Enable the error check '1': Disable the error check for prime PIPE stream state. It will generate a transfer event with prime PIPE error completion code if an error is detected." "0,1" newline bitfld.long 0x0 27. "ENABLE_NOOP_UPD,This bit has been modified for its usage since PPT A0. It is used to allow NO-OP TRB to be treated in a same way as link TRB. In other words it will update the internal context when it is fetched while the internal context cache TRB FIFO.." "0,1" newline bitfld.long 0x0 26. "EP_HALT_2RETRY_EN,This is a special internal condition enable for CPL engine which it enables all EP halt conditions detected to cause the proper actions in a response. '0': Disabled '1': Enabled. Note: Only default.." "0,1" newline bitfld.long 0x0 25. "TRB_ERR_RM_DB_EN,This is a special internal branch condition control in XFER engine which does the EP transfer ring process. When this bit is set a retry condition identified by completion engine will cause XFER engine to stop what it is currently in.." "0,1" newline bitfld.long 0x0 24. "DISABLE_IMD_4NODMA,This is a special internal branch condition control in XFER engine which does the EP transfer ring process. When this bit is set the XFER will not continue even if the next TRB is identified as a non DMA TRB. The engine will then wait.." "0,1" newline bitfld.long 0x0 23. "WRITE_ERDP_LO,When ERDP register is updated by software it is expected as an atomic function since this is a 64-bit register. It is expected that the ERDP [64-bit register] is updated together when ERDP high 32 is written. We have this bit designed to.." "0,1" newline bitfld.long 0x0 22. "CPL_DB_RANG_EN,Setting this bit to '1' will force an internal doorbell ring on the EP that it has received a response." "0,1" newline bitfld.long 0x0 21. "DISABLE_ERDY_DROP,'0': Drop ERDYs received when not in a flow control state. '1': Do not drop ERDYs received when not in a flow control state. Note: We typically drop unexpected ERDY" "0,1" newline bitfld.long 0x0 20. "DEADLOCK_DETECT_EN,'0': Disable timeout of TRB error processing. '1': Enable timeout of a TRB processing in few critical states that possibly have a deadlock for unexpected reason. A vendor defined completion code is generated.." "0,1" newline bitfld.long 0x0 19. "SHORT_ERR_4MSI_EN,This bit is modified to enable a feature where we can control whether or not to report an event with completion code of Missed Service Error when a short packet response has been received not in the expected service interval." "0,1" newline bitfld.long 0x0 18. "NO_OP_AS_TD,This bit is modified to enable the NO_OP TRB as a TD when Missing Service Interval Error has encountered. This is only for PPT B0 LPT and CB. '0': disable '1': enable." "0,1" newline bitfld.long 0x0 17. "PHASE1_IMD_EN,Enable a special branch condition of the XFER ring process state. This is to ensure that we have a DMA request issued to DMA engine during a PHASE1 process of the TTE. '0': disabled '1': enabled" "0,1" newline bitfld.long 0x0 16. "SET_ADDR_ERR_EN,'0': Disable error reporting if a SETUP TRB contains the following: bRequest = SET_ADDRES bmRequestType = [DTD] Host-to-device Type = Standard Recipient = Device. '1': Enable error reporting for this case." "0,1" newline bitfld.long 0x0 15. "ISO_0LEN_LPF_EN,Enables a special internal state branch condition for periodic EP during its transfer ring process. If we have identified that the next TRB is a non DMAnable TRB such as LINK TRB or Event data TRB then this bit enables XFER engine to.." "0,1" newline bitfld.long 0x0 14. "XFER_BLOCK_EN,Not used. XFER engine has a new function that provides a support to ISO EP within a long PCIe delayed system. The long delay can cause missing service interval while pending response has not all been returned. This bit enables engine to.." "0,1" newline bitfld.long 0x0 13. "SINGLE_BURST_EN,'0': Bulk and interrupt endpoints use burst size defined by endpoint context. '1: Force the Bulk and Interrupt endpoints to use a burst size of 1." "?,1: Force the Bulk and Interrupt endpoints to use a.." newline bitfld.long 0x0 12. "ENT_EN,'0': ENT bit is ignored. '1': ENT bit is processed. The transfer engine will service the next TRB." "0,1" newline bitfld.long 0x0 11. "CTRL_REG_CLR_BNDRY,Setting this bit to '1' will force the transfer engine to set the packet boundary flag. This flag is an important flag which may cause a deadlock. This is a safety feature that we have plugged in." "0,1" newline bitfld.long 0x0 10. "FLUSH_2CLR_VALID_EN,This bit is modified to support PPTB0 LPT and CP for a feature that we will clear the single IN EP array based on ISO flush or short flush. '0': Indicate that we do not need to clear IN EP array based on flush.." "0,1" newline bitfld.long 0x0 9. "IN_NPKT_PACE_DISABLE,Setting this bit to '1' will force the transfer engine state machine to exit the CPL_WAIT state. This is designed to avoid unexpected deadlock in CPL_WAIT state." "0,1" newline bitfld.long 0x0 8. "TRB_CACHE_INVALIDE_EN,'0': Disable internal TRB cache invalidation. '1': Enable internal TRB cache invalidation auto detect function. This will allow engine to handle more than 4 TRBs per packet." "0,1" newline bitfld.long 0x0 7. "NPKT0_FC_DISABLE,'0': USB3 responses with NumPkts equal to 0 will be treated as a flow control condition. '1': USB3 responses with NumPkts equal to 0 will not be treated as a flow control condition." "0,1" newline bitfld.long 0x0 6. "EN_BB_PORT_DISABLE,'0': Babble errors will not disable the port. '1': Babble errors will disable the auto detect function This will allow engine to handle more than 4 TRBs per packet." "0,1" newline bitfld.long 0x0 5. "CPL_PKT_CLR_MASK_EN,Enable a function which clears a mask of an EP on any response of that EP. '0': Clear the scheduler mask normally '1': Clear the scheduler mask on each received packet." "0,1" newline bitfld.long 0x0 4. "XPORT_CRD_DISABLE,This bit is designed to allow XFER engine to do a transfer without checking against the available port credit. '0': Advertises accurate buffer credit information to the scheduler. '1': Advertises non-zero.." "0,1" newline bitfld.long 0x0 3. "DISABLE_STALL,'0': Process stalls reported by the DMA engine. '1': Ignore stall response received reported by the DMA engine." "0,1" newline bitfld.long 0x0 2. "LINK_NOP_SUCESS_EN,'0': Process transaction errors due to CERR count reached or transaction timeout reported by the DMA engine. '1': Ignore transaction errors reported by the DMA engine." "0,1" newline bitfld.long 0x0 1. "DISABLE_FC_4INRDY,'0': Obey the NPKT0 and EOB flow control. '1': Ignore received flow control for implied NRDY [e.g EOB or NPKT=0] for USB3 only" "0,1" newline bitfld.long 0x0 0. "IN_TD_PACE_ENABLE,'0': Disable TD pacing for IN endpoint. '1': Enable TD pacing for IN endpoints." "0,1" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_SCH_REG1,Host Control Scheduler register. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for informative.." hexmask.long.byte 0x4 28.--31. 1. "SCH_LIMIT_PRDC,Host Control Scheduler: sch_limit_prdc" newline bitfld.long 0x4 27. "SCH_BLOCK_PENDING_EN,Host Control Scheduler: sch_block_pending_en" "0,1" newline bitfld.long 0x4 26. "SCH_ASYNC_1PKT_SPLIT_PREF,Host Control Scheduler: sch_async_1pkt_split_pref" "0,1" newline bitfld.long 0x4 25. "SCH_TT_OVERLAP_ALL_INS,Host Control Scheduler: sch_tt_overlap_all_ins" "0,1" newline bitfld.long 0x4 24. "SCH_ASYNC_PRDC_CC_DIS,Host Control Scheduler: sch_async_prdc_cc_dis" "0,1" newline bitfld.long 0x4 22.--23. "SCH_CCLK_PRDC_DONE_CHECK,Host Control Scheduler: sch_cclk_prdc_done_check" "0,1,2,3" newline bitfld.long 0x4 21. "SCH_STOP_SERVE_NC,Host Control Scheduler: Enable Stop serving packets to disabled port" "0,1" newline bitfld.long 0x4 20. "TTE_4,TTE: Reserved" "0,1" newline bitfld.long 0x4 19. "DISABLE_GL_HUB_INT_FIX,TTE: disable_gl_hub_int_fix" "0,1" newline bitfld.long 0x4 18. "DISABLE_GL_HUB_ISO_FIX,TTE: disable_gl_hub_iso_fix" "0,1" newline bitfld.long 0x4 16.--17. "TTE_3,TTE: Reserved" "0,1,2,3" newline bitfld.long 0x4 15. "TTE_2,TTE: Disable split error request to TRM on unserved interrupt-INs" "0,1" newline bitfld.long 0x4 14. "TTE_1,TTE: Disable checking of missed microframes" "0,1" newline bitfld.long 0x4 13. "TTE_0,TTE: Disable interrupt complete split limit to 3 micro frames" "0,1" newline bitfld.long 0x4 11.--12. "CACHE_SIZE_CTRL,Command Manager: Context cache enable" "0,1,2,3" newline bitfld.long 0x4 9.--10. "MAXEP,Command Manager: Allow dynamically setting different max EP allowed. The max EP supported scales with the scratch pad size. This allows driver to allocate small memory sizes if it needed. 0: 32 EPs 1: 16 EPs 2: 8.." "0,1,2,3" newline bitfld.long 0x4 8. "SCRATCH_PAD_EN,Command Manager: Enables scratch pad function" "0,1" newline bitfld.long 0x4 7. "SCH_ASYNC_1PKT_PERF,Host Control Scheduler: Disable burst limit '1' for async in presence of another port periodic packets." "0,1" newline bitfld.long 0x4 6. "SCH_ASYNC_OUT_MAX_PERF,Host Control Scheduler: Enable maximal out performance [may cause unfairness or short term starvation]." "0,1" newline bitfld.long 0x4 4.--5. "SCH_SORT_PATTERN,Host Control Scheduler: Search priority. Possible values: '00': Sort by Interval then ISO over interrupt '01' '10' '11': Experimental sort algorithms." "0,1,2,3" newline bitfld.long 0x4 3. "TTE_ENABLE_INTROUT_OVERLAP_STOP,Host Control Scheduler: tte_enable_introut_overlap_stop" "0,1" newline bitfld.long 0x4 2. "SCH_2,Host Control Scheduler: Disable TTE IN overlap" "0,1" newline bitfld.long 0x4 1. "TRM_ACTIVE_IN_EP_VALID,Host Control Scheduler: Disable TRM active IN EP valid check function" "0,1" newline bitfld.long 0x4 0. "POLL_DELAY_DIS,Host Control Scheduler: Disable poll delay function" "0,1" line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_ODMA_REG,Host Control ODMA. This register contains a number of fields that provide a specific level of configurability for the OUT DMA Engine in the xHCI. This functionality is above and beyond.." hexmask.long.tbyte 0x8 15.--31. 1. "RESERVED_RW,Reserved field RW" newline bitfld.long 0x8 14. "SPEED_UP_TIMEOUT,'0': Disable the speed up transaction timeout function. '1': Enable the transaction timeout speed up based on no-connect detected on a particular port" "0,1" newline bitfld.long 0x8 13. "ACK_CRD_CHECK_EN,'0': Disable the ACK credit check function '1': Enable the ACK credit check function that ODMA provides" "0,1" newline bitfld.long 0x8 12. "EP_BASE_TIMER,'0': Employs a 1us EP Transaction Base Timer. Enables a Timeout range from 16us to 64us '1': Employs a 125us EP Transaction Base Timer. Enables a Timeout range from 2ms to 8ms" "0,1" newline bitfld.long 0x8 11. "ODMA_11,Setting this field will prohibit the Set Address Finite State Machine Credit Handshake with TTE Logic" "0,1" newline bitfld.long 0x8 10. "EP_TIMER_TICK,Setting this field will disable the EP Transaction Timer function when the Command Manager is performing a Stop Endpoint Command or when the LTSSM is in Recovery" "0,1" newline bitfld.long 0x8 9. "ODMA_9,Setting this field prohibits the Set Address Finite State Machine from being flow controlled when an ACK with NPKT=0 is received in response to the SETUP DP initiated during SET_ADDRESS" "0,1" newline bitfld.long 0x8 8. "CLEAR_CNTX_LOCKS,Setting this field generates a pulse that clears the ownership of the context semaphore that is shared between the Out DMA Response and Completion Finite State Machines" "0,1" newline bitfld.long 0x8 7. "ODMA_7,Setting this field generates a pulse that implicitly returns all of the Out DMA ACK credits on all ports" "0,1" newline bitfld.long 0x8 6. "ODMA_SET_ADDR_TO_IDLE,Setting this field generates a pulse that returns the Out DMA Set Address Finite State Machine into the IDLE state" "0,1" newline bitfld.long 0x8 5. "ODMA_COMPLETION_TO_IDLE,Setting this field generates a pulse that returns the Out DMA Completion Finite State Machine into the IDLE state" "0,1" newline bitfld.long 0x8 4. "ODMA_RESP_TO_IDLE,Setting this field generates a pulse that returns the Out DMA Response Finite State Machine into the IDLE state." "0,1" newline bitfld.long 0x8 3. "ODMA_RD_TO_IDLE,Setting this field generates a pulse that returns the Out DMA Read Finite State Machine into the IDLE state." "0,1" newline bitfld.long 0x8 1.--2. "EP_TRANS_TIMEOUT_LEN,Controls the duration of the EP Transaction Timeout [depends on the settings of EP Transaction Base Timer [bit[12]]]. Possible values: 0: 64us [[12]=0] or 8ms [[12]=1] EP Transaction Timeout 1:.." "?,?,?,3: EP Transaction Timer is DISABLED" newline bitfld.long 0x8 0. "EP_TRANS_TIMEOUT_EN,'0': Enables the EP Transaction Timeout Function '1': Disables the EP Transaction Timeout Function" "0,1" line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_IDMA_REG,Host Control IDMA. This register contains a number of fields that provide a specific level of configurability for the IN DMA Engine in the xHCI. This functionality is above and beyond.." bitfld.long 0xC 31. "EVENT_FIFO_DIS,Used in Event Manager. '0': Enable single ring optimization '1': Disable single ring optimization." "0,1" newline bitfld.long 0xC 30. "EVENT_PRIORITY,Used in Event Manager. '0': CPL Engine priority over XFER Manager '1': XFER Manager priority over CPL Engine." "0,1" newline bitfld.long 0xC 29. "DB_EVENT_GEN_EN,Used in Doorbell Manager. '0': Do not generate an event. '1': Enable an event generated with completion code TRB_CMPL_ENDPOINT_NOT_ENABLED_ERR when a doorbell ring on an EP which has not running or stop state." "0,1" newline bitfld.long 0xC 28. "IDMA_28,'0': Drop Deferred Ack/Ack TPs. [default] [Bug #5481] '1': Allow Deferred Ack/Ack TPs." "0,1" newline bitfld.long 0xC 27. "IDMA_27,'0': Drop Deferred Stream Reject TPs. [default] [Bug #5434] '1': Allow Deferred Stream Reject TPs." "0,1" newline bitfld.long 0xC 26. "TIMER_TICK1,Allows to select the EP Timer Tick to be either the 1us timer tick or the 125us timer tick or the 1ms timer tick or the 4ms timer tick based on the setting of this bit and bit 10 of this register. The encoding is as follows.." "0,1" newline bitfld.long 0xC 25. "IDMA_25,Flush TTE Address FIFO" "0,1" newline bitfld.long 0xC 24. "IDMA_24,'0': Flush an Async Address FIFO '1': Flush a Periodic Address FIFO." "0,1" newline hexmask.long.byte 0xC 19.--23. 1. "IDMA_23_19,Port Number of Address FIFO to Flush." newline bitfld.long 0xC 18. "IDMA_ADDR_FIFO_FLUSH_BIT,Flush IDMA Address FIFO strobe." "0,1" newline bitfld.long 0xC 17. "IDMA_17,'0': All ACK ACKs are put in the Periodic Header FIFO in XPPE '1': Only Periodic ACK ACKs are put in the Periodic Header FIFO in XPPE." "0,1" newline bitfld.long 0xC 16. "IDMA_PTR_BUF_ROOM_SET,'0': Default IDMA Pointer Buffer Room to 8 : Requires strobe of host_ctrl_idma_reg[3][idma_ptr_buf_room_restore_pulse] to take effect '1': Default IDMA Pointer Buffer Room to 4 : Requires strobe of.." "0,1" newline bitfld.long 0xC 15. "IDMA_15,Disable drop spurious DP when i_npkt==0" "0,1" newline bitfld.long 0xC 14. "IDMA_14,Disable drop spurious DP when EP is in flow conrtrol." "0,1" newline bitfld.long 0xC 13. "IDMA_13,Disable dropping all deferred packets on ISO Endpoints." "0,1" newline bitfld.long 0xC 12. "SPEED_UP_TIMEOUT,'0': Disable the speed up transaction timeout function. '1': Enable the transaction timeout speed up based on no-connect detected on a particular port" "0,1" newline bitfld.long 0xC 11. "SEQ_NUM_ADJ_ON_NRDY,'0': Enable sequence number adjustment on NRDY received for USB3 when we are expecting a response. '1': Enable sequence number adjustment on any NRDY received for USB3." "0,1" newline bitfld.long 0xC 10. "TIMER_TICK0,'0': Employs a 1us EP Transaction Base Timer. Enables a Timeout range from 16us to 64us. '1': Employs a 125us EP Transaction Base Timer. Enables a Timeout range from 2ms to 8ms." "0,1" newline bitfld.long 0xC 9. "IDMA_9,Setting this field will disable the EP Transaction Timer function when the Command Manager is performing a Stop Endpoint Command or when the LTSSM is in Recovery" "0,1" newline bitfld.long 0xC 8. "COMPLIANCE_ISO_ENABLE,Setting this field enables the Compliance Isochronous mode of operation. It bounds the upper limit on the NPKT field for all ISO Acknowledgments generated from the Host to the value of 2." "0,1" newline bitfld.long 0xC 7. "CLEAR_CNTX_LOCKS,Setting this field generates a pulse that clears the ownership of the context semaphore that is shared between the IN DMA Acknowledge and Data Mover Finite State Machines" "0,1" newline bitfld.long 0xC 6. "DM_PST_CLR_PULSE,Setting this field generates a pulse that returns the IN DMA Data Mover Finite State Machine into the IDLE state" "0,1" newline bitfld.long 0xC 5. "ACK_PST_CLR_PULSE,Setting this field generates a pulse that returns the IN DMA Acknowledge Finite State Machine into the IDLE state." "0,1" newline bitfld.long 0xC 4. "RESTORE_RDP_CREDITS_PULSE,Setting this field generates a pulse that implicitly returns all of the IN DMA Data Packet credits on all ports." "0,1" newline bitfld.long 0xC 3. "IDMA_PTR_BUF_ROOM_RESTORE_PULSE,Setting this field generates a pulse that clears all the Read and Write Pointers associated with the various DMA Address FIFOs causing them to appear empty" "0,1" newline bitfld.long 0xC 1.--2. "EP_TIMER_TICK,'00': 1us/125us/1ms/4ms EP Timer Tick '01': 2us/250us/2ms/8ms EP Timer Tick '10': 4us/500us/4ms/16ms EP Timer Tick '11': Disabled EP Timer Tick" "0,1,2,3" newline bitfld.long 0xC 0. "EP_TRANS_TIMEOUT_EN,'0': Enables the EP Transaction Timeout Function '1': Disables the EP Transaction Timeout Function." "0,1" line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_PORT_CTRL,Global Port Control. Specific control register for port power management etc. This is a vendor defined capability. This register is reserved. This register should not be accessed by.." hexmask.long.word 0x10 20.--31. 1. "RESERVED_R,Reserved field RO" newline bitfld.long 0x10 19. "LOCK_HEADER_DATA_EN,lock_header_data_en" "0,1" newline bitfld.long 0x10 18. "RD_WR_ADDR_CONFLICT_EN,rd_wr_addr_conflict_en" "0,1" newline bitfld.long 0x10 17. "OVERFLOW_SYS_ERR_EN,'0': Disable error generation. '1': Enable to generate a host system error when receive buffer overflow on any ports." "0,1" newline hexmask.long.byte 0x10 13.--16. 1. "HBUF_WATER_MARK_REG_CCLK,This 4-bit register is designed as a water mark for when to turn on link FC credit return disable. This is used in xhc_prot_rppe.v for receive buffer management. We have 8 header credit in per port receive buffer. When buffer.." newline bitfld.long 0x10 12. "ENABLE_ITP_XMT,Bit[s] of this field are designated to individually control each USB3 port to enable ITP transmission. 0: Do not Transmit any ITP. 1: Transmit ITP" "0: Do not Transmit any ITP,1: Transmit ITP" newline bitfld.long 0x10 11. "PCIE_GASKET,Reserved to '1'. Note: An internal register bit for PCIe gasket. It is only valid for value of '1'" "0,1" newline bitfld.long 0x10 9.--10. "RESERVED_RW,Reserved field RW" "0,1,2,3" newline hexmask.long.byte 0x10 4.--8. 1. "TEST_BUS_SEL_CTRL_BITS,Test bus select control bits. 0: Clock Reset and Power management Debug bus 1: PCIe PIPE Bus 2: USB3 PIPE Bus 3: USB2 UTMI Bus 4: TRM Debug Bus 5: Scheduler Debug.." newline hexmask.long.byte 0x10 0.--3. 1. "RES1,Reserved to 1 [reserved for PP]" rgroup.long 0x18100++0x23 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_AUX_CTRL_REG,AUX Reset Control. Reset Control register. This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high. This is a vendor defined.." rbitfld.long 0x0 31. "RESERVED_R,Reserved field RO This field should not be modified by software." "0,1" newline bitfld.long 0x0 30. "PERST_FILTER_DIS,reserved. perst_filter_dis This field should not be modified by software." "0,1" newline bitfld.long 0x0 29. "PCIE_PHY_RST_SEL,This bit enables AUX reset control module to assert the pcie_phy_reset either from PIPE reset or from Aux power up reset only. The pcie_phy_reset is an internal signal for CB PHY only. '0': Aux PowerUp Reset '1':.." "0,1" newline bitfld.long 0x0 28. "PERST_2PWDOWN_EN,This bit enables the AUX PM control module to assert mac_phy_powerdown state to P1 as soon as PERST# is deasserted. If disabled then the AUX PM control state will follow its nature cause to determine the power down states for PIPE." "0,1" newline bitfld.long 0x0 27. "PERST_4MAIN_EN,This bit enables the internal reset control module to immediately start a reset assertion process when PERST# is deasserted without waiting for PCIe device is out of D3 state. This is for warm reboot only. The PERST# can still have impact.." "0: disabled '1: enabled PERST# as an immediately..,?" newline bitfld.long 0x0 26. "IGNORE_PERST_EN,This bit disables the PERST# to cause an internal reset. '0: enable '1: disable the PERST# This field should not be modified by software." "0: enable '1: disable the PERST# This field should..,?" newline bitfld.long 0x0 25. "FAST_SIM_RST,This bit enables a speed up function or AUX reset at startup. Normally we wait for 20ms after AUX power level has reached. When in speed up mode we wait only around 3-4us. '0: Disabled '1: Enabled for fast sim. This.." "0: Disabled,1: Enabled for fast sim" newline bitfld.long 0x0 24. "IGNORE_LINKDOWN_RST_4UPORT,When set to '1' ignore a port reset that is caused by a USB port link went down. This field should not be modified by software." "0,1" newline bitfld.long 0x0 23. "IGNORE_MAIN_PWRUP_2USB_PHY,When set to '1' ignore main powerup reset to USB PHY PIPE reset This field should not be modified by software." "0,1" newline bitfld.long 0x0 22. "COLD_RST_N_PULSE,When set to '1' allow software to fire a cold reset to USB port logic This field should not be modified by software." "0,1" newline bitfld.long 0x0 21. "IGNORE_HCRESET_4USB2,When set to '1' ignore HC reset to reset the USB2 Port logic This field should not be modified by software." "0,1" newline bitfld.long 0x0 20. "IGNORE_HC_WARM_RST_4UPHY_PON,When set to '1' ignore HC reset to the USB PHY power-on reset This field should not be modified by software." "0,1" newline bitfld.long 0x0 19. "IGNORE_MAIN_PWRUP_HC_2PCORE,When set to '1' enable the HC liked reset caused by PCIe link down condition detected. If PCIe link down detected a link down reset will always be fired to PCIe core. This field should not be modified by software." "0,1" newline bitfld.long 0x0 18. "EEPROM_LOAD_ON_MAIN,When set to '1' enable EEPROM reload on every main power-up This field should not be modified by software." "0,1" newline bitfld.long 0x0 17. "IGNORE_HC_RST_2PCIE_PHY,When set to '1' ignore HC reset to the PCIe PHY PIPE reset This field should not be modified by software." "0,1" newline bitfld.long 0x0 16. "IGNORE_MAC_PHY_PIPE_RST,When set to '1' ignore the LTSSM of USB link state transition caused reset to USB PHY PIPE reset This field should not be modified by software." "0,1" newline bitfld.long 0x0 15. "IGNORE_WARM_RST_4UPHY_PON,When set to '1' ignore warm reset of the portSC to the USB PHY power on reset This field should not be modified by software." "0,1" newline bitfld.long 0x0 14. "PCIE_LINKDOWN_RST_EN,When set to '1' allow PCIe link down to cause a reset to the rest of the core as the HC reset would. This field should not be modified by software." "0,1" newline bitfld.long 0x0 13. "IGNORE_HOT_RST_4U3PORT,When set to '1' ignore hot reset to the USB3 port logic This field should not be modified by software." "0,1" newline bitfld.long 0x0 12. "IGNORE_WARM_RST_4U3PORT,When set to '1' ignore warm reset to the USB3 port logic This field should not be modified by software." "0,1" newline bitfld.long 0x0 11. "IGNORE_MAIN_PWRUP_4U3PORT,When set to '1' ignore main power up reset to USB3 port logic This field should not be modified by software." "0,1" newline bitfld.long 0x0 10. "IGNORE_MAIN_PWRUP_4U2PORT,When set to '1' ignore main power up reset to USB2 port logic This field should not be modified by software." "0,1" newline bitfld.long 0x0 9. "IGNORE_MAIN_PWRUP_2PCORE,When set to '1' ignore main power up reset to PCIe core This field should not be modified by software." "0,1" newline bitfld.long 0x0 8. "IGNORE_MAIN_PWRUP_2PCIE_PHY,When set to '1' ignore main power up reset to PCIe PHY This field should not be modified by software." "0,1" newline bitfld.long 0x0 7. "IGNORE_HC_WARM_RST_2USB_PHY,When set to '1' ignore HC reset to the USB PHY This field should not be modified by software." "0,1" newline bitfld.long 0x0 6. "IGNORE_WARM_RST_2USB_PHY,When set to '1' ignore warm reset to the USB PHY This field should not be modified by software." "0,1" newline bitfld.long 0x0 5. "IGNORE_MAIN_PWRUP_RST,When set to '1' it enables the reset isolation function that we have added during HC reset or Per port reset. This field should not be modified by software." "0,1" newline bitfld.long 0x0 4. "PM_CTRL_MAIN_RST_EN,When set to '1' allow main power off condition to trigger a main power domain reset This field should not be modified by software." "0,1" newline bitfld.long 0x0 3. "IGNORE_PERST_4MAIN_PWRUP,When set to '1' ignore waiting for PERST# deassertion during main power show down. This field should not be modified by software." "0,1" newline bitfld.long 0x0 2. "IGNORE_PERST_4FD_RST,When fundamental reset is asserted during AUX power up if this bit is set then we will ignore PERST# such that purely wait for timeout to deassert fundamental reset. This field should not be modified by software." "0,1" newline bitfld.long 0x0 0.--1. "FORCE_FD_RST,Writing to this field a value of 2'b11 will cause a fundamental reset. The only valid write values are 2'b11 or 2'b00 This field should not be modified by software." "0,1,2,3" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_BW_OV_SS_REG,Super Speed Bandwidth Overload. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for informative.." hexmask.long.byte 0x4 24.--31. 1. "RESERVED_R,Reserved field RO" newline hexmask.long.word 0x4 12.--23. 1. "MAX_TT_BW,Max. TT BW allowed. See white paper" newline hexmask.long.word 0x4 0.--11. 1. "SS_BW_CALC,BW calculation: Overhead per packet for SS BW calculations. See white paper." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_BW_OV_HS_REG,High Speed TT Bandwidth Overload. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for informative.." hexmask.long.byte 0x8 24.--31. 1. "RESERVED_R,Reserved field RO" newline hexmask.long.word 0x8 12.--23. 1. "BW_OV_HS,BW calculation: Overhead per packet for HS-TT BW calculations. See white paper." newline hexmask.long.word 0x8 0.--11. 1. "BW_OV_HS_TT,BW calculation: Overhead per packet for HS BW calculations. See white paper." line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_BW_OV_FS_LS_REG,Bandwidth Overload Full and Low Speed. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for.." hexmask.long.byte 0xC 24.--31. 1. "RESERVED_R,Reserved field RO" newline hexmask.long.word 0xC 12.--23. 1. "FS_BW_CALC,BW calculation: Overhead per packet for FS BW calculations. See white paper." newline hexmask.long.word 0xC 0.--11. 1. "LS_BW_CALC,BW calculation: Overhead per packet for LS BW calculations. See white paper." line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_BW_OV_SYS_REG,System Bandwidth Overload. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for informative purposes." hexmask.long.byte 0x10 24.--31. 1. "RESERVED_R,Reserved field RO" newline hexmask.long.word 0x10 12.--23. 1. "BW_OV_SYS_TT,BW calculation: Overhead per TT packet for System BW calculations. See white paper." newline hexmask.long.word 0x10 0.--11. 1. "SYS_BW_CALC,BW calculation: Overhead per packet for System BW calculations. See white paper." line.long 0x14 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG,Scheduler Async Delay. Global defaults for inserting delays between packets in the scheduler for asynchronous types. This is a vendor defined capability. This register is.." hexmask.long.word 0x14 20.--31. 1. "RESERVED_R,Reserved field RO" newline bitfld.long 0x14 19. "HS_BULK_DELAY_EN,High-Speed Bulk Delay Enable" "0,1" newline bitfld.long 0x14 16.--18. "HS_BULK_DELAY_DEF,High-Speed Bulk Delay Default [0=125us 1=250us 2=500us 3=1ms ]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 15. "FS_BULK_DELAY_EN,Full-Speed Bulk Delay Enable" "0,1" newline bitfld.long 0x14 12.--14. "FS_BULK_DELAY_DEF,Full-Speed Bulk Delay Default [0=125us 1=250us 2=500us 3=1ms ]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 11. "HS_CTRL_DELAY_EN,High-Speed Control Delay Enable" "0,1" newline bitfld.long 0x14 8.--10. "HS_CTRL_DELAY_DEF,High-Speed Control Delay Default [0=125us 1=250us 2=500us 3=1ms ]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 7. "FS_CTRL_DELAY_EN,Full-Speed Control Delay Enable" "0,1" newline bitfld.long 0x14 4.--6. "FS_CTRL_DELAY_DEF,Full-Speed Control Default [0=125us 1=250us 2=500us 3=1ms ]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 3. "LS_CTRL_DELAY_EN,Low-Speed Control Delay Enable" "0,1" newline bitfld.long 0x14 0.--2. "LS_CTRL_DELAY_DEF,Low-Speed Control Delay Default [0=125us 1=250us 2=500us 3=1ms ]" "0,1,2,3,4,5,6,7" line.long 0x18 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_UPORTS_PON_RST_REG,AUX Power PHY Reset. This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high. Allow a USB PHY reset being issued by.." hexmask.long 0x18 4.--31. 1. "RESERVED_R,Reserved field RO" newline hexmask.long.byte 0x18 0.--3. 1. "USB_PHY_PORT_NUM,Indicates the port number of the USB PHY" line.long 0x1C "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_TRM_REG3,Host Control Transfer Manager (TRM) register. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for.." hexmask.long.word 0x1C 16.--31. 1. "RESERVED_R,Reserved field RO" newline hexmask.long.byte 0x1C 9.--15. 1. "RESERVED_RW,Reserved field RW" newline bitfld.long 0x1C 8. "CPL_EXTRA_DB_RANG_EN,cpl_extra_db_rang_en" "0,1" newline bitfld.long 0x1C 7. "CFG_EN_MISS_DOUBLE,'0': Do not enable cache control to double fetch on miss. '1': Enable cache control to double fetch on miss." "0,1" newline bitfld.long 0x1C 6. "CFG_EN_DEFER_BC,'0': Disable cache control to defer misses on bulk/control EPs. '1': Enable cache control to defer misses on bulk/control EPs." "0,1" newline bitfld.long 0x1C 4.--5. "CFG_EN_LOOK_POS,Enable cache control trigger position lookahead." "0,1,2,3" newline bitfld.long 0x1C 3. "CFG_CACHE_DEBUG,cfg_cache_debug. Available when TRB_CACHE_DEBUG_EN is defined" "0,1" newline bitfld.long 0x1C 2. "CFG_EN_HIT_INVALID,'0': Disable cache control hit invalid with invalid CS '1': Enable cache control hit invalid with invalid CS." "0,1" newline bitfld.long 0x1C 1. "CFG_EN_LOOKAHEAD,'0': Disable cache control lookahead '1': Enable cache control lookahead." "0,1" newline bitfld.long 0x1C 0. "CFG_EN_CACHE,'0': Disable cache control '1': Enable cache control." "0,1" line.long 0x20 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_AUX_CTRL_REG1,AUX Power Management Control 1. This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high. This is a vendor defined capability." bitfld.long 0x20 31. "D3_HOT_PME_EN,d3_hot_pme_en" "0,1" newline bitfld.long 0x20 30. "LOW_PWR_CCLK_GATE_EN,This bit enables gate-off the core clock when AUX PM control is in low power state. '0': disable this function '1': enabled to gate off the core clock." "0,1" newline bitfld.long 0x20 29. "EXTEND_PHYSTATUS_EN,This bit is there for a bug fix where we need to ensure that phystatus did not get lost during the rate change where clock switch logic takes some cycles to complete. such that the PCie's core clock is at half of the PCIe PHY pclk." "0,1" newline bitfld.long 0x20 28. "DIRECT_RATE_PASS_EN,Disable the overwrite function in AUX PM control module for its initiated rate change. '0': allows AUX PM control module to initiate its PCIE rate change when it needs to enable P2 overwrite P1 function. '1':.." "0,1" newline bitfld.long 0x20 27. "USE_PERST_4FD_RST,Enable AUX reset module to treat every PERST# as a fundamental reset '0': disabled '1': enabled. This field should not be modified by software" "0,1" newline bitfld.long 0x20 26. "POWERDOWN_P1_EN,This is a test/control bit. This bit is designed to control the lowest powerdown state of the PCIe that AUX PM module signaled to PIPE is P1. '0': drive as normal operation. '1': always drive to P1 instead of P2" "0,1" newline bitfld.long 0x20 25. "SET_SSV_EN,When set to '1' set the SSV flag." "0,1" newline bitfld.long 0x20 24. "CLR_SSV_EN,When set to '1' clear the SSV flag" "0,1" newline bitfld.long 0x20 23. "SR_CMD_SAVE_EN,A debug control bit which is used to enable save'n'restore function. '0': disabled. '1': enabled" "0,1" newline bitfld.long 0x20 22. "RESERVED,reserved RW" "0,1" newline bitfld.long 0x20 21. "CLR_SAVE_FLAG,This bit sets the internal save_restore_enable flag to '0' when written to '1'. Software is expected to clear this bit after it wrote this bit to '1'. This is for test/debug purpose of the save'n'restore function. '0': allows.." "0,1" newline bitfld.long 0x20 20. "CFG_PCIE_TXREG_PD,cfg_pcie_txreg_pd" "0,1" newline bitfld.long 0x20 18.--19. "CFG_IOB_DRIVESTRENGTH,Controls the drive strength of the IO buffer. Set default IO Strength to 8ma" "0,1,2,3" newline bitfld.long 0x20 17. "CFG_USB_P2_EN,Cfg_Usb_p2_en" "0,1" newline bitfld.long 0x20 16. "CFG_CLK_GATE_DIS,Cfg_clk_gate_dis" "0,1" newline bitfld.long 0x20 15. "CFG_RXDET_P3_EN,Cfg_rxdet_p3_en. Enable rxdet U3 mode" "0,1" newline bitfld.long 0x20 14. "CFG_PIPE_RST_EN,Cfg_pipe_rst_en_sync." "0,1" newline bitfld.long 0x20 13. "ELECIDLE_MASK_EN,This bit enables the AUX PM control state machine to take over txelecidle signal of the PIPE during several special conditions. '0': Disable the mask. '1': Allow mask to mac_phy_txeleidle of PCIe core." "0,1" newline bitfld.long 0x20 12. "PME_STATUS_EN,This bit enables the PCIe status function. '0': xHC as a PCIe device will not generate any PME nor report PME status. '1': xHC as a PCIe device will generate the PME message." "0,1" newline bitfld.long 0x20 11. "ISOLATION_EN,When set to '1' enable isolation function for dual power zone. This field should not be modified by software" "0,1" newline bitfld.long 0x20 10. "NEW_OW_EN,This bit allows the AUX PM control module to decide whether we entered into P2 overwrite condition based on the power down state of the PCIe core is at P1 or the LTSSM of PCIe core is in L1. What we used to have is based on P1 of the PCIe core.." "0,1" newline bitfld.long 0x20 9. "CCLK_GATE_DISABLE,When set to '1' disable core clock gating based on low power state entered." "0,1" newline bitfld.long 0x20 8. "PHYSTATUS_FALL_TIMEOUT_EN,When set to '1' enable PHY status timeout function which is designed to cover the PCIePHY issue that we may have not be able to detect the PHY status toggle. This is a safety feature in case we have gotten into a deadlock.." "0,1" newline bitfld.long 0x20 7. "IGNORE_AUX_PME_EN,When set to '1' ignore the aux_pm_en reg from PCIe core to continue the remote wake/clock switching support" "0,1" newline bitfld.long 0x20 6. "P2_OVERWRITE_P1_EN,When set to '1' enable P2 overwrite P1 when PCIe core has indicated the transition from P0 to P1. This is to enable entering the even lower power state." "0,1" newline bitfld.long 0x20 5. "ENABLE_P2_ENTER,When set to '1' enables the remote wake function by allowing P2 clock/switching and P2 entering" "0,1" newline hexmask.long.byte 0x20 1.--4. 1. "PM_STATE,Forced power management state can be set here. States encoding: PM_ACTIVE : 4'h0. REQ_CLK_SWITCH_2AUX : 4'h1. DRIVE_PHY_2P2 : 4'h2. WAIT_4WAKE :.." newline bitfld.long 0x20 0. "FORCE_PM_STATE,When set to '1' force PM state to go to the state indicated in field pm_state [bits [4:1]]. This bit is the force PM state register it is a pulse only [read by software will always give '0']" "0,1" rgroup.long 0x18128++0x1B line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_WATERMARK_REG,Port Watermark. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for informative purposes." hexmask.long.word 0x0 16.--31. 1. "RBUF_WATER_MARK,RBUF water mark" newline hexmask.long.word 0x0 0.--15. 1. "XBUF_WATER_MARK,XBUF water mark" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_PORT_LINK_REG,SuperSpeed Port Link Control. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for informative.." hexmask.long.byte 0x4 27.--31. 1. "FORCE_LTSSM_STATE,LTSSM state to be forced. This value is for test purpose only. Setting bit 4 enables: cfg_relax_rxpolarity_en. Setting bit 3 enables: cfg_relax_linkfunc_en. Setting bit 2 enables: cfg_link_func_en." newline bitfld.long 0x4 26. "FORCE_LTSSM,'0': Normal operation mode '1': Direct link to a specific state specified by force_ltssm_state field [bits [31:27]]. This bit is for test purpose only. It shall be written '0' in normal operation mode." "0,1" newline bitfld.long 0x4 25. "FORCE_LTSSM_U0,'0': Normal operation mode '1': Direct link to U0 This bit is for test purpose only. It shall be written '0' in normal operation mode." "0,1" newline hexmask.long.byte 0x4 21.--24. 1. "FORCE_COMP_PATTERN,Compliance pattern to be forced to enter compliance mode. This value is for test purpose only." newline bitfld.long 0x4 20. "LINK_ERR_CNT_SLV_EN,link_err_cnt_slv_en" "0,1" newline bitfld.long 0x4 17.--19. "DBG_MODE_SEL,Debug mode select: bit[0]: cfg_port_init_ctrl [if set to '1' tPortConfiguration less than 21us] bit[1]: cfg_relax_ts2_en bit[2]: cfg_relax_lfps_en." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15.--16. "CFG_LOWPOWER_LATENCY,cfg_lowpower_latency" "0,1,2,3" newline bitfld.long 0x4 12.--14. "CFG_NORM_RECOV_VAL,This value defines the minimum time for the link to stay in Recovery. Active other than from U3. The granuity is 128us." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 9.--11. "CFG_U3_RECOV_VAL,This value defines the minimum time for the link to stay in Polling.Active and Recovery.Active from U3. The granuity is 128us." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8. "CFG_FORCE_PM_ACCEPT,'0': Normal operation mode. '1': Force link to accept power management command." "0,1" newline bitfld.long 0x4 7. "CFG_RECOVERY,'0': Normal operation mode '1': Direct link to Recovery from U0." "0,1" newline bitfld.long 0x4 6. "CFG_FAST_TRAINING,'0': Normal operation mode '1': Link fast training mode. This bit should be written '0' in normal operation." "0,1" newline bitfld.long 0x4 5. "CFG_DIS_SCRMB,'0': Enable link scrambler '1': Disable link scrambler." "0,1" newline bitfld.long 0x4 4. "CFG_SYMBOL_ERR_EN,'0': Disable detecting RxData error using RxStatus signal '1': Enable detecting RxData error using RxStatus signal." "0,1" newline bitfld.long 0x4 3. "CFG_U2_ENABLE,'0': Normal operation mode '1': Direct link to U2 from U0. This bit is for test purpose only. It shall be written '0' in normal operation mode." "0,1" newline bitfld.long 0x4 2. "CFG_U1_ENABLE,'0': Normal operation mode '1': Direct link to U1 from U0. This bit is for test purpose only. It shall be written '0' in normal operation mode." "0,1" newline bitfld.long 0x4 1. "CFG_LPBK_MODE,'0': Disable link loopback master mode '1': Enable link loopback master mode." "0,1" newline bitfld.long 0x4 0. "CFG_DIS_COMP,'0': Enable link compliance mode '1': Disable link compliance mode." "0,1" line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_USB2_LINK_MGR_CTRL_REG1,USB2 Port Link Control 1.2.3.4. This set of registers is used to control the USB set of timers. They are spread over 4 registers each 32 bits wide. This set of registers may be read.." hexmask.long.byte 0x8 24.--31. 1. "TIMER_DISCONNECT_DETECT_LO,Number of microseconds of SE0 in FS/LS mode to register disconnect had occurred. First 8 MSB." newline bitfld.long 0x8 23. "USB2_PM_DEBUG,USB2_PM_DEBUG. usb2_link_mgr_debug register." "0,1" newline bitfld.long 0x8 22. "USB2_PM_DEBUG_LATENCY_TOL_MSG,Latency Tolerance Scheme ['0'=when HWLPM is enabled / '1'=when L1 is active]." "0,1" newline bitfld.long 0x8 21. "USB2_PM_DEBUG_RESUME_DEB_DIS,Clr to eliminate debounce on remote wake detect." "0,1" newline bitfld.long 0x8 20. "USB2_PM_DEBUG_HW_LPM_ERRATA,Set to switch the HIRD to BESL format." "0,1" newline bitfld.long 0x8 19. "USB2_PM_DEBUG_HW_LPM_ERRATA1,Set to change the scale of HW LPM timeout to 256us increments." "0,1" newline bitfld.long 0x8 18. "USB2_PM_DEBUG_ENABLE_FLUSH_TO,Set to enable flush state timeouts." "0,1" newline bitfld.long 0x8 17. "USB2_PM_DEBUG_EOP_DETECT,Set to enable full length SE0 detect." "0,1" newline bitfld.long 0x8 16. "USB2_PM_DEBUG_FORCE_FULL_SPEED,Set to reject device chirp and force full-speed" "0,1" newline bitfld.long 0x8 15. "USB2_PM_DEBUG_SPLIT_192_LIMITDIS,Use to disable 192 byte limit checking on." "0,1" newline bitfld.long 0x8 14. "USB2_PM_DEBUG_FS_LS_EXT_DISCON,Use UTMI HostDisconnect input for FS/LS" "0,1" newline bitfld.long 0x8 13. "USB2_PM_DEBUG_UTMIRST2,Select UTMI Reset Source 2" "0,1" newline bitfld.long 0x8 12. "USB2_PM_DEBUG_UTMIRST1,Select UTMI Reset Source 1" "0,1" newline bitfld.long 0x8 11. "USB2_PM_DEBUG_ENABLE_DISC_WIN,Enable HS disconnect Window." "0,1" newline bitfld.long 0x8 10. "USB2_PM_DEBUG_DIS_PORT_ERR,Enable Remote Wake Resume Trap." "0,1" newline bitfld.long 0x8 9. "USB2_PM_DEBUG_DIS_ISO_PEEK,Disable waiting for last indication for USB2 ISO." "0,1" newline bitfld.long 0x8 8. "USB2_PM_DEBUG_DIRECT_RESUME,Use FS/LS serial I/F to drive resume." "0,1" newline bitfld.long 0x8 7. "USB2_PM_DEBUG_DROPPING,If new ping on endpoint that already had PING drop the PING." "0,1" newline bitfld.long 0x8 6. "USB2_PM_DEBUG_FORCEPING,If retry on endpoint that should have PING force the PING." "0,1" newline bitfld.long 0x8 5. "USB2_PM_DEBUG_AUTOPING,After NYET and new packet coming to same EP - ping N times before give up and flush." "0,1" newline bitfld.long 0x8 4. "USB2_PM_DEBUG_PHY_SUSDISALL,Disable PHY suspend for all states." "0,1" newline bitfld.long 0x8 3. "USB2_PM_DEBUG_PHY_CLKGATEDIS,Disable PHY suspend during disconnect." "0,1" newline bitfld.long 0x8 2. "USB2_PM_DEBUG_PHY_RSTDISCON,Disable Clock Gate" "0,1" newline bitfld.long 0x8 1. "USB2_PM_DEBUG_PHY_RST,Control PHY Reset Directly" "0,1" newline bitfld.long 0x8 0. "USB2_PM_DEBUG_QUICK_SIM,Short Timer Values For Simulation of USB2.0 parameters. Please refer to Integration Guide section on Debug Features" "0,1" line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_USB2_LINK_MGR_CTRL_REG2,USB2 Port Link Control 1. 2. 3. 4. This set of registers is used to control the USB set of timers. They are spread over 4 registers each 32 bits wide. This set of registers may be.." bitfld.long 0xC 31. "TIMER_RESET_0,Number of microseconds for total reset duration" "0,1" newline hexmask.long.word 0xC 18.--30. 1. "TIMER_CHIRP_K_DETECT,Number of microseconds of Chirp-K to register that a device is chirping" newline hexmask.long.word 0xC 5.--17. 1. "TIMER_CONNECT_DETECT,Number of microseconds of K/J in disconnected state to register connect has occurred. Last 5 LSBs." newline hexmask.long.byte 0xC 0.--4. 1. "TIMER_DISCONNECT_DETECT_HI,Number of microseconds of SE0 in FS/LS mode to register disconnect had occurred. Last 5 LSBs." line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_USB2_LINK_MGR_CTRL_REG3,USB2 Port Link Control 1. 2. 3. 4. These set of registers is used to control the USB set of timers. They are spread over 4 registers each 32 bits wide. This set of registers may be.." hexmask.long.byte 0x10 28.--31. 1. "TIMER_U2_SETTLE,Number of microseconds after entering U2. linestate changes are ignored as bus settles. First 4 LSB." newline hexmask.long.word 0x10 15.--27. 1. "TIMER_U3_SETTLE,Number of microseconds after entering U3. linestate changes are ignored as bus settles" newline hexmask.long.word 0x10 0.--14. 1. "TIMER_RESET,Number of microseconds for total reset duration" line.long 0x14 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_USB2_LINK_MGR_CTRL_REG4,USB2 Port Link Control 1. 2. 3. 4. These set of registers is used to control the USB set of timers. They are spread over 4 registers each 32 bits wide. This set of registers may be.." hexmask.long.byte 0x14 25.--31. 1. "RESERVED_R,Reserved field RO" newline hexmask.long.word 0x14 9.--24. 1. "TIMER_RESUME_U2_REFLECT,Number of microseconds after detecting U2 remote wake condition to reflect K" newline hexmask.long.word 0x14 0.--8. 1. "TIMER_U2_SETTLE,Number of microseconds after entering U2. linestate changes are ignored as bus settles. Last 9 MSB." line.long 0x18 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_BW_CTRL_REG,USB2 Max Bandwidth Control. This register is reserved. This register should not be accessed by software. It is described only for informative purposes." hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved. For Hardware Bandwidth Calculation Only" newline hexmask.long.byte 0x18 12.--15. 1. "BW_CTRL_15_12,Max. Percentage BW allowed for SS [default: 80]" newline hexmask.long.byte 0x18 8.--11. 1. "BW_SYS_FACTOR,System factor for Bandwidth calculation" newline hexmask.long.byte 0x18 0.--7. 1. "BW_CTRL_7_0,Miscellaneous Bandwidth calculator configuration bits" rgroup.long 0x18144++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_FPGA_REVISION_REG,FPGA_REVISION_REG. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for informative purposes." hexmask.long 0x0 0.--31. 1. "FPGA_REVISION_REG_DEFAULT,FPGA_REVISION_REG_DEFAULT" rgroup.long 0x18148++0xB line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_INTF_CTRL_REG,Host interface control register. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for informative.." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED_R,Reserved field RO" newline rbitfld.long 0x0 8. "PROT_HDR_RBUF_OVERFLOW_CCLK,prot_hdr_rbuf_overflow_cclk." "0,1" newline bitfld.long 0x0 6.--7. "CFG_MAX_NUM_OF_RD,cfg_max_num_of_rd. This is to control how many max number of read that we allow ODMA read to issue. '00': can issue 16 reads '10': can issue 8 reads '01': can issue 4 reads" "0,1,2,3" newline hexmask.long.byte 0x0 2.--5. 1. "HOST_INTF_CTRL,host_intf_ctrl" newline bitfld.long 0x0 1. "HC_HALT_TIMEOUT_EN,hc_halt_timeout_en. An internal register bit used to control whether or not to use the hc halt status timer of 15ms" "0,1" newline bitfld.long 0x0 0. "HOST_ERR_MASK,host_err_mask. If set to '1' do not mask the host system error" "0,1" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_BW_OV_SS_BURST_REG,BW_OV_SS_BURST_REG. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for informative purposes." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved. For Hardware Bandwidth Calculation Only" newline hexmask.long.word 0x4 12.--23. 1. "BW_OV_SYS_BURST,bw_ov_sys_burst" newline hexmask.long.word 0x4 0.--11. 1. "BW_OV_SS_BURST,bw_ov_ss_burst" line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_TRM_REG2,Host Control Transfer Manager (TRM) register. This register contains fields. which control the behavior of the Transfer Manager in the xHCI. The functions controlled by this register are.." bitfld.long 0x8 31. "INSERT_CPL_IDMA_WAIT_EN,This bit is added for bug FR2601. It is for cache invalidate case where xHC engine needs to insert wait states for completion engine when the completion has received a short packet before XFER engine has finished the TRB fetch for.." "0,1" newline bitfld.long 0x8 30. "PKT_BNDRY_BLOCK_HALT_EN,This bit is added for bug FR2642. It is to delay the completion engine to generate an event due to internal error conditions that halted an EP until XFER engine has reached a packet boundary. '0': Disabled.." "0,1" newline bitfld.long 0x8 29. "NON_DMA_IMD_EN,This bit is added for bug FR2639. It enables the internal functions where xHC engine needs to immediately serve the EP again. '0': disabled '1': enabled" "0,1" newline bitfld.long 0x8 28. "ERR_CPL_CODE_STORE_EN,This bit is added for bug FR2495. It enables that error completion code of the first error condition detected within an TD. so that we can report the same error completion codes for all other TRBs within this TD. '0':.." "0,1" newline bitfld.long 0x8 27. "TRM_ODMA_FIFO_DISABLE,This bit disables a new feature where xHC engine will have an ODMA FIFO added for the commands between TRM and ODMA. so that we can avoid the back-pressure situation due to the number of outstanding PCIe read limitation. This is for.." "0,1" newline bitfld.long 0x8 26. "TTE_PKT_BNDRY_EXIT,This bit is added for bug FR2446. It is to enable TRM to only send one IN request for TTE 1st phase request even if it has not reached the packet boundary. '0': Disabled '1': Enabled" "0,1" newline bitfld.long 0x8 25. "TTE_IN_EP_BLOCK_EN,This bit is added for bug FR2395. It disables the single IN EP for TTE function. '0': Disabled '1': Allow only single IN EP per port for TTE." "0,1" newline bitfld.long 0x8 24. "IGNORE_NPKT_4PRDC,This bit is added for bug FR2333 where the xHC engine has always ignored the credit returned from device for its OUT EP buffers when the EP is a periodic EP. '0': Enable the xHC engine to follow the flow control .." "0,1" newline bitfld.long 0x8 23. "DOUBLE_CLR_MASK_DIS,This bit is added for bug FR2283. This is to ensure only one clear pulse generated when a completion has received [disable CPL engine from sending multiple clear]. '0': Disabled '1': Enabled." "0,1" newline bitfld.long 0x8 22. "STOP_2MS_4TTE_EN,This bit enables a 2ms timeout for all TTE related EP stop endpoint command. The xHC engine will not check whether there is a pending response in context. It will only wait for 2ms and indicates that EP has been stopped. '0':.." "0,1" newline bitfld.long 0x8 21. "SECOND_EVENT_FOR_ISP_EN,This bit enables xHC engine TRM to report the second or more events on an ISP flush on a second or more TRBs with ISP bit set that are flushed for a short packet response received. '0': Disables this feature .." "0,1" newline bitfld.long 0x8 20. "DEV_MBS_CAP_EN,This bit enables a new feature where the completion engine of TRM can check the credit returned from remote device to not excceed its max burst size. If it does we will keep the internal credits in the context to the max burst size so.." "0,1" newline bitfld.long 0x8 19. "DEADLOCK_TRB_ERR_EN,This bit enables an internally detected deadlock situation being treated as an TRB_ERR when reports the event. This is an internal debug function. '0': Disables this feature '1': Enables this feature." "0,1" newline bitfld.long 0x8 18. "MULTI_NON0_CTRL_EP_EN,This bit enables the xHC engine to fully support the non-0 control EP. This bit allows the xHC TRM to keep track of on non-0 control EP per port so that the responses can be routed to the correct DMA engine. '0':.." "0,1" newline bitfld.long 0x8 17. "ENT_AT_END_OF_TD_EN,This bit enables xHC engine to evaluate the next TRB even if the EP is at the end of a TD. '0': Disables this feature '1': Enables this feature." "0,1" newline bitfld.long 0x8 16. "MSI_CNT_EN,This bit enables the new Missing service interval detection mechanism. xHC engine will count how many service interval that it missed and skip over that many TDs. '0': Disables this feature '1': Enables this feature." "0,1" newline bitfld.long 0x8 15. "SKIP_INTR_4RESP_EN,This bit enables a feature where xHC engine will skip a service interval when an Interrupt EP has missed its service interval. '0': Disables this feature '1': Enables to skip a service interval." "0,1" newline bitfld.long 0x8 14. "ODMA_CRD_CAL_EN,New feature added to prevent the back-pressure from ODMA due to the fact that it ran out of ODMA timeout timer resources. This is for performance enhancement. We have put into the ODMA credit is part of resource calculation before TRM.." "0,1" newline bitfld.long 0x8 13. "RPORT_CRD_CHECK_DIS,The xHC engine has a feature that can check with Receive Port Credit per root port to whether or not allow the next schedule onto this port [disable the RPORT credit check for IDMA]. This is for performance enhancement." "0,1" newline bitfld.long 0x8 12. "DISABLE_CPL_SST_IDEQ0_ERR,'0': Report received stream ID of 0x0000 as an error. '1': Disable the error reporting for a received stream ID value of 0x0000. Note: only used when an endpoint is configured for stream operation." "0,1" newline bitfld.long 0x8 11. "STREAM_IDLE2PRIME_EN,Enable the host to transfer to the prime-pipe state [and transmit a prime pipe] on each transfer back to the IDLE state. '0': Feature disabled '1': Feature enabled. Note: Used only when an.." "0,1" newline bitfld.long 0x8 10. "STREAM_ID_MATCH_EN,stream_id_match_en" "0,1" newline bitfld.long 0x8 9. "TRM_ADV_DETECT_EN,'0': Disable this function in XFER engine. '1': Enable the XFER engine to auto detecting a missing service interval function when there is a long delay such that we missed a service interval due to the pending response." "0,1" newline bitfld.long 0x8 8. "SUPPORT_0LEN_TTE_EN,'0': Disable this function. '1': Enable the function to support 0length TTE second phase request from TTE module." "0,1" newline bitfld.long 0x8 7. "PKT_BNDRY_2IGNORE_NTRB_EN,'0': Disable this function. '1': Enable a packet pace function under a special condition. This is an internal feature of XFER engine. It is not expected to be used other than default." "0,1" newline bitfld.long 0x8 6. "FC_ON_2INCOMPLET_EN,'0': do not enable this function. '1': assert the sch_req_incomplete signal in XFER engine when a context FC is ON. This is an internal safety feature for XFER engine." "0,1" newline bitfld.long 0x8 5. "SETADDR_OVERRIDE,'0': Disable the address device command to query a port credit before it is executed in ODMA engine '1': Enable the address device command to query a port credit before it is executed in ODMA engine." "0,1" newline bitfld.long 0x8 4. "USE_EMPTY_4TTE_OVERLAP,'0': Enable XFER engine to use a no-pending response flag as a way of identifying a TTE overlap condition '1': Enable XFER engine to use context empty flag not assert as a way of identifying a TTE overlap condition." "0,1" newline bitfld.long 0x8 3. "CNTX_1ST_TD_EN,'0': disable the context storage '1': enable the context storage for a flag to identify a DMA request as the first of TD DMA request." "0,1" newline bitfld.long 0x8 2. "UPORT_CRD_UPD_EN,'0': Disable the credit redeem '1': Enable the credit redeem when a port is in NC state." "0,1" newline bitfld.long 0x8 1. "ISO_CNT_2NODMA_EN,'0': Disable this non DMA TRB detect function '1': Enable the function where XFER engine uses the remaining burst count as an indication that the next TRB on the transfer ring for an ISO TD is either link TRB or event.." "0,1" newline bitfld.long 0x8 0. "RESERVE_TRB_EN,'0': report TRB ERR for reserved TRB type '1': enable XFER engine to process a reserved TRB type as a NO-OP TRB." "0,1" rgroup.long 0x18168++0x7 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_BW_MAX1_REG,HOST_CTRL_BW_MAX1_REG. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for informative purposes." hexmask.long.byte 0x0 24.--31. 1. "FSLS_BHUB_MAX_BW,Max. Percentage BW allowed for FS/LS behind hub [default: 90]" newline hexmask.long.byte 0x0 16.--23. 1. "SS_MAX_BW,Max. Percentage BW allowed for SS [default: 80]" newline hexmask.long.byte 0x0 8.--15. 1. "HS_MAX_BW,Max. Percentage BW allowed for HS [default: 80]" newline hexmask.long.byte 0x0 0.--7. 1. "FSLS_MAX_BW,Max. Percentage BW allowed for FS/LS [default: 90]" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_BW_MAX2_REG,HOST_CTRL_BW_MAX2_REG. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for informative purposes." hexmask.long.byte 0x4 28.--31. 1. "RESERVED_R,Reserved field RO" newline hexmask.long 0x4 0.--27. 1. "BW_MAX_REG59_32,bw_max_reg[59:32]" rgroup.long 0x18170++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_USB2_LINESTATE_REG,USB2_LINESTATE_REG. This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high. This register may be read from or written to.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_R,Reserved field RO" newline hexmask.long.word 0x0 8.--23. 1. "PDOWN_STATUS,pdown_status" newline hexmask.long.byte 0x0 0.--7. 1. "UTMI_LINESTATE,utmi_linestate" rgroup.long 0x18174++0x13 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_PROTO_GAP_TIMER1_REG,HOST_PROTO_GAP_TIMER1_REG. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for informative.." hexmask.long.byte 0x0 24.--31. 1. "USB2_PROTO_PKT_GAP_FS,USB2_PROTO_PKT_GAP_FS" newline hexmask.long.byte 0x0 16.--23. 1. "USB2_PROTO_PKT_GAP_HS_RX,USB2_PROTO_PKT_GAP_HS_RX" newline hexmask.long.byte 0x0 8.--15. 1. "USB2_PROTO_PKT_GAP_HS_SOF,USB2_PROTO_PKT_GAP_HS_SOF" newline hexmask.long.byte 0x0 0.--7. 1. "USB2_PROTO_PKT_GAP_HS,USB2_PROTO_PKT_GAP_HS" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_PROTO_GAP_TIMER2_REG,HOST_PROTO_GAP_TIMER2_REG. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for informative.." hexmask.long.byte 0x4 24.--31. 1. "RESERVED_R,Reserved field RO" newline hexmask.long.byte 0x4 16.--23. 1. "USB2_PROTO_PKT_GAP_LS_HTX,USB2_PROTO_PKT_GAP_LS_HTX" newline hexmask.long.byte 0x4 8.--15. 1. "USB2_PROTO_PKT_GAP_LS_HRX,USB2_PROTO_PKT_GAP_LS_HRX" newline hexmask.long.byte 0x4 0.--7. 1. "USB2_PROTO_PKT_GAP_LS,USB2_PROTO_PKT_GAP_LS" line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_PROTO_BTO_TIMER_REG,HOST_PROTO_BTO_TIMER_REG. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for informative.." hexmask.long.word 0x8 21.--31. 1. "USB2_PROTO_BTO_LS,USB2_PROTO_BTO_LS" newline hexmask.long.word 0x8 10.--20. 1. "USB2_PROTO_BTO_FS,USB2_PROTO_BTO_FS" newline hexmask.long.word 0x8 0.--9. 1. "USB2_PROTO_BTO_HS,USB2_PROTO_BTO_HS" line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_PSCH_REG,HOST_CTRL_PSCH_REG. Specific control register for Power Scheduler. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is.." hexmask.long.byte 0xC 24.--31. 1. "PSCH_HOST_CTRL_REG_I_31_24,PSCH_HOST_CTRL_REG_I_31_24" newline hexmask.long.tbyte 0xC 0.--23. 1. "RESERVED_RW,Reserved field RW" line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_PSCH1_REG,HOST_CTRL_PSCH1_REG. Specific internal used control register for Power Scheduler. This is a vendor defined capability. This register is reserved. This register should not be accessed by.." hexmask.long.word 0x10 16.--31. 1. "RESERVED_R,Reserved field RO" newline hexmask.long.byte 0x10 12.--15. 1. "RESERVED_RW2,Reserved field RW" newline bitfld.long 0x10 10.--11. "IDLE_SCALE,PSCH_HOST_CTRL_REG_I_43_42. idle_scale. 0=1c . 1=1us. 2=125us" "0,1,2,3" newline hexmask.long.word 0x10 0.--9. 1. "RESERVED_RW1,Reserved field RW" rgroup.long 0x18190++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_LTM_REG,HOST_CTRL_LTM_REG. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for informative purposes." hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED_R,Reserved field RO" newline hexmask.long.word 0x0 0.--11. 1. "BELT_SELECTED,Reports several of the latencies depending on the last programmed belt_select value: 0: LTV value programmed 1: Lowest BELT received 2: Last received LTM per Slot 3: Last received LTM per.." rgroup.long 0x18194++0xF line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_AUX_CTRL_REG2,AUX Power Management Control 1. This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high. This is a vendor defined capability." bitfld.long 0x0 31. "UPORTS_CHANGE_DETECT_EN,uports_change_detect_en" "0,1" newline bitfld.long 0x0 30. "SNPS_PHYSTATUS_DONE_L23_DIS,snps_phystatus_done_l23_dis" "0,1" newline bitfld.long 0x0 29. "SNPS_PHYSTATUS_DONE_L1_DIS,snps_phystatus_done_l1_dis" "0,1" newline bitfld.long 0x0 28. "SHADOW_DECODE_DIS,shadow_decode_dis" "0,1" newline bitfld.long 0x0 27. "BATT_CHARGE_D3_EN,batt_charge_d3_en" "0,1" newline bitfld.long 0x0 26. "CFG_DEBOUNCE_EN,cfg_debounce_en" "0,1" newline bitfld.long 0x0 25. "CFG_DBGP_DIS_AUTO,cfg_dbgp_dis_auto" "0,1" newline bitfld.long 0x0 24. "AUTO_PM_EXIT_L1_EN,This bit enables a L1 exit notification to SNPS PCIe core. There is a case where USB ports have waked up and AUX PM module has started the wakeup process. The AUX PM control state got into a wait for P0 state because it needs to wait.." "0,1" newline bitfld.long 0x0 23. "CFG_PSCEG_DIS_SEL,'0': Assert PLC for disconnection '1': Do not assert PLC for disconnection" "0,1" newline bitfld.long 0x0 22. "CFG_LTSSM_IDLE2TS2,This bit enables a feature in PCie core LTSSM to treat IDLE received as TS2 when LTSSM is in wait for TS2 receive state. This is a function requested from PHY where it is possible to not able to receive TS2 without error." "0,1" newline bitfld.long 0x0 21. "P2_OVERWRITE_WHENL1_EN,We have added a feature where if PCIe core LTSSM enters L1 due to the D3hot the aux PM control will not start a P2 overwrite function in anticipating for the next L23 enter. '0': enables P2 overwrite even if we are in.." "0,1" newline bitfld.long 0x0 20. "CFG_U3_AUTO,'0': Disables the port to enter U3 automatically when in U1/U2 '1': Enables the port to enter U3 automatically when in U1/U2." "0,1" newline bitfld.long 0x0 19. "PDOWN_2LINK_RST_EN_REG,pdown_2link_rst_en" "0,1" newline bitfld.long 0x0 18. "U0_WAKE_TIMEOUT_EN,This bit enables a feature in AUX PM module where if PCIe core LTSSM is in P0 for a duration of time we will exit the deep sleep state. This is for failure control in case. '0': disable this feature '1':.." "0,1" newline bitfld.long 0x0 17. "CFG_U2_P3_LFPS_TIME,This bit selects U2 exit LFPS timer value. '0': 320ns - 400ns in 25MHz domain '1': 240ns - 320ns in 25MHz domain." "0,1" newline bitfld.long 0x0 16. "WAKE_EXIT_USE_LVL_EN,This bit enables a function that AUX PM module exits from the deep sleep state due to the USB ports wakeup level signal. We have added this feature where USB ports will generate a wakeup level signal to wakeup the AUX PM module if it.." "0,1" newline bitfld.long 0x0 14.--15. "CFG_U2_P3_TIMEOUT,This field defines the timeout value to enter P3 mode in U2. 00: 7us - 8us 01: 511us - 512us 10: disables the timer [0us] 11: disables the timer [0us]." "0,1,2,3" newline bitfld.long 0x0 13. "CFG_U2_P3_EN,'0': disables PHY P3 mode in U2. '1': enables PHY P3 mode in U2." "0,1" newline bitfld.long 0x0 11.--12. "RESERVED_RW2,Reserved field RW" "0,1,2,3" newline bitfld.long 0x0 10. "PRDC_PREVENT_L1_EN,This bit enables a function that the SPNS PCIe core is controlled by xHCI engine internal periodic EP traffic conditions. '0': Disabled this function '1': Enables the xHC engine to request an exit of L1 when the.." "0,1" newline bitfld.long 0x0 9. "CFG_PSCEG_SEL,This bit selects the port status change event generation mode. '0': port status change event is only blocked by the individual status change bit. '1': port status change event is blocked until all status change bit.." "0,1" newline hexmask.long.byte 0x0 4.--8. 1. "RESERVED_RW1,Reserved field RW" newline bitfld.long 0x0 3. "IDLE_WAKEUP_EN,This bit enables the AUX PM module to automatically wakeup from deep power down when engine has detected non-idle condition. '0': feature disabled '1': feature enabled" "0,1" newline bitfld.long 0x0 2. "P0_DRIVE_DIS,This bit ensures the P1 drive during PERST#. '0': feature disabled '1': feature enabled." "0,1" newline bitfld.long 0x0 1. "CFG_FAST_SIMS,This bit is for simulation modes only. It enables further reductions to simulation timings in addition to cfg_fast_training. Please refer to Integration Guide Debug Features section '0': Normal timings '1': Enable.." "0,1" newline bitfld.long 0x0 0. "AUTO_P2_OW_EN_REG,This bit enables a feature where we can get P2 overwrite to automatically turned on when there is no pending traffic in the engine. '0': feature disabled '1': feature enabled. This field should not be modified.." "0,1" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_AUX_CTRL_REG3,Configuration bits for USB2 PHY. This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high. This is a vendor defined capability." hexmask.long.word 0x4 20.--31. 1. "RESERVED_R,Reserved field RO" newline hexmask.long.byte 0x4 16.--19. 1. "HS_DC_V_LVL_ADJ,HS DC Voltage Level Adjustment" newline hexmask.long.byte 0x4 12.--15. 1. "FSLS_SRC_IMPD_ADJ,FS/LS Source Impedance Adjustment" newline bitfld.long 0x4 11. "HS_TRANS_PRE_EMPH_EN,HS Transmitter Pre-Emphasis Enable" "0,1" newline bitfld.long 0x4 10. "HS_TRANS_RS_TIME_ADJ,HS Transmitter Rise/Fall Time Adjustment" "0,1" newline bitfld.long 0x4 8.--9. "TRANS_HS_CROSS_ADJ,Transmitter High-Speed Crossover Adjustment" "0,1,2,3" newline bitfld.long 0x4 5.--7. "STA,Squelch Threshold Adjustment" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 2.--4. "PHY_MISC_CTRL_REG_4_2,phy_misc_ctrl_reg[4:2]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--1. "PHY_MISC_CTRL_REG_1_0,phy_misc_ctrl_reg[1:0]" "0,1,2,3" line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_DEBUG_CTRL_REG,DEBUG_CTRL_REG. This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high. This is a vendor defined capability. This register is.." bitfld.long 0x8 29.--31. "CFG_PCIE_GASKET_CTRL,cfg_pcie_gasket_ctrl[2:0] This field should not be modified by software" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 25.--28. 1. "CFG_L1_L0S_CTRL,cfg_l1_l0s_ctrl[3:0] This field should not be modified by software" newline hexmask.long.byte 0x8 20.--24. 1. "NEW_NB_CTRL_REG,new_nb_ctrl_reg. Used in aux_pm module to keep old NB behavior. This field should not be modified by software" newline hexmask.long.byte 0x8 16.--19. 1. "CFG_PM_DEBUG_CTRL,cfg_pm_debug_ctrl. Used in aux_power_logic.v for debug. This field should not be modified by software" newline bitfld.long 0x8 15. "CFG_RESUME_WAKE_DIS,cfg_resume_wake_dis This field should not be modified by software" "0,1" newline bitfld.long 0x8 14. "CFG_RESUME_TIMER_EN,cfg_resume_timer_en This field should not be modified by software" "0,1" newline hexmask.long.byte 0x8 10.--13. 1. "RESERVED_RW,Reserved field RW This field should not be modified by software" newline bitfld.long 0x8 9. "SW_EEPROM_EN,debug control for CoosBay: sw_eeprom_en This field should not be modified by software" "0,1" newline bitfld.long 0x8 8. "PORT_PWR_CTRL_TOGGLE,debug control for CoosBay: port_pwr_ctrl_toggle This field should not be modified by software" "0,1" newline bitfld.long 0x8 7. "DEBUG_EN_TOGGLE,debug control for CoosBay: debug_en_toggle This field should not be modified by software" "0,1" newline bitfld.long 0x8 5.--6. "DEBUG_FINE_MODE_SEL,debug_fine_mode_sel This field should not be modified by software" "0,1,2,3" newline hexmask.long.byte 0x8 0.--4. 1. "DEBUG_MODE_SEL,debug_mode_sel This field should not be modified by software" line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_SCH_REG2,Host Control Scheduler. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for informative purposes." hexmask.long.byte 0xC 24.--31. 1. "RESERVED_R,Reserved field RO" newline hexmask.long.word 0xC 15.--23. 1. "RESERVED_RW1,Reserved field RW" newline hexmask.long.byte 0xC 8.--14. 1. "SERVICE_TIME_WATERMARK,service_time_watermark" newline hexmask.long.byte 0xC 4.--7. 1. "RESERVED_RW0,Reserved field RW" newline bitfld.long 0xC 3. "SCH_POLL_DBRANG_DIS,Host Control Scheduler: sch_poll_dbrang_dis" "0,1" newline bitfld.long 0xC 2. "SCH_ALWAYS_RESERVE_DIS,Host Control Scheduler: sch_always_reserve_dis" "0,1" newline bitfld.long 0xC 1. "SCH_POLL_RESERVATION_DIS,Host Control Scheduler: sch_poll_reservation_dis" "0,1" newline bitfld.long 0xC 0. "SCH_PRDC_RETRY_USB2_DIS,Host Control Scheduler: sch_prdc_retry_usb2_dis" "0,1" rgroup.long 0x181A4++0xB line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_AUX_DEBUG_READ_ONLY,AUX_DEBUG_READ_ONLY. This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high. This is a vendor defined capability. This.." hexmask.long 0x0 2.--31. 1. "RESERVED_R,Reserved field RO" newline bitfld.long 0x0 1. "P2_OVERWRITE_ENTER,p2_overwrite_enter sticky bit" "0,1" newline bitfld.long 0x0 0. "ALL_UPORTS_IN_U3NC,all_uports_in_u3nc. If set all ports are in U3NC state." "0,1" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_AUX_CTRL_PORTNUM_REG,AUX_CTRL_PORTNUM_REG. This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high. This is a vendor defined capability. This.." hexmask.long.byte 0x4 24.--31. 1. "LIMIT_MAX_SLOTS,Limit Max slots to fewer then synthesized [strap]" newline hexmask.long.byte 0x4 16.--23. 1. "LIMIT_MAX_NPORTS,Limit Max ports to fewer then synthesized [strap]" newline hexmask.long.byte 0x4 8.--15. 1. "LIMIT_NPORTS_USB3,Limit USB3 ports to fewer then synthesized [strap] This field should not be modified by software" newline hexmask.long.byte 0x4 0.--7. 1. "LIMIT_NPORTS_USB2,Limit USB2 ports to fewer then synthesized [strap]" line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_AUX_CTRL_DEV_REMOVE_REG,Feature #3002 (Device Removable in PORTSC). This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high. This register is.." hexmask.long.word 0x8 16.--31. 1. "RESERVED_R,Reserved field RO" newline hexmask.long.byte 0x8 8.--15. 1. "DEVICE_REMOVABLE_USB3,Set to 1 if port has non-removable device [strap to 0/1]" newline hexmask.long.byte 0x8 0.--7. 1. "DEVICE_REMOVABLE_USB2,Set to 1 if port has non-removable device [strap to 0/1]" rgroup.long 0x181E0++0xB line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_TTE_REG1,Specific control register for SCH. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for informative.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_R,Reserved field RO" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED_RW,Reserved field RW" newline bitfld.long 0x0 1. "EOB_INT_DIS,Disable end of burst workaround INT [0 length on final MDATA]" "0,1" newline bitfld.long 0x0 0. "EOB_ISO_DIS,Disable end of burst workaround ISO [0 length on final MDATA]" "0,1" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_LTM_REG1,HOST_CTRL_LTM_REG1. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for informative purposes." bitfld.long 0x4 30.--31. "BELT_SELECT,Selects which BELT value should be reported on the belt_selected field when the register is read. 0 - LTV value programmed 1 - Lowest BELT received 2 - Last received LTM per Slot 3 - Last received LTM per Port." "0: LTV value programmed,1: Lowest BELT received,2: Last received LTM per Slot,3: Last received LTM per Port" newline bitfld.long 0x4 29. "BELT_USB2_EN,belt_usb2_en active '0' default enabled" "0,1" newline bitfld.long 0x4 28. "BELT_USB3_EN,belt_usb3_en active '0' default enabled" "0,1" newline bitfld.long 0x4 27. "BELT_PCIE_EN,belt_pcie_en default disabled" "0,1" newline bitfld.long 0x4 26. "BELT_FORCE_RECOMPUTE,belt_force_recompute" "0,1" newline bitfld.long 0x4 25. "BELT_FORCE_DISABLEALL,belt_force_disable_all" "0,1" newline bitfld.long 0x4 24. "BELT_FORCE_DISABLESLOT,belt_force_disable_slot" "0,1" newline hexmask.long.byte 0x4 16.--23. 1. "BELT_PORT_SELECT,Port Number for the BELT reported on the belt_selected field when belt_select is 3" newline hexmask.long.word 0x4 0.--15. 1. "BELT_SLOT_SELECT,Slot-ID for BELT reported on the belt_selected field when belt_select is 2" line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_LTM_REG2,HOST_CTRL_LTM_REG2. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for informative purposes." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED_R,Reserved field RO" newline hexmask.long.word 0x8 0.--11. 1. "DEFAULT_PCIE_LTM,DEFAULT_PCIE_LTM converted from ns with convert_ns2belt" rgroup.long 0x18200++0x7 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_AUX_SCRATCHPAD_0,For internal use. This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high. This is a vendor defined capability. This.." hexmask.long 0x0 0.--31. 1. "RESERVED_RW,Reserved field RW" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_AUX_SCRATCHPAD_1,For internal use. This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high. This is a vendor defined capability. This.." hexmask.long 0x4 0.--31. 1. "RESERVED_RW,Reserved field RW" rgroup.long 0x18210++0xB line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_BATTERY_CHARGE_REG,Battery charge mode and enable register. This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high. This is a vendor defined.." hexmask.long.byte 0x0 25.--31. 1. "BATTERY_CHARGE_MODE_EN_REG,The register allows enabling battery charge mode for each USB2 port." newline hexmask.long.tbyte 0x0 1.--24. 1. "RESERVED,Reserved field RO." newline bitfld.long 0x0 0. "BATTERY_CHARGE_MODE_REG,The register allows setting battery charge mode for each USB2 port." "0,1" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_BATTERY_CHARGE_REG1,Battery charge control register 1. This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high. This is a vendor defined.." rbitfld.long 0x4 31. "RESERVED_R,Reserved field RO" "0,1" newline hexmask.long 0x4 0.--30. 1. "BATTERY_CHARGE_CTRL_REG1_DEFAULT,BATTERY_CHARGE_CTRL_REG1_DEFAULT" line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_BATTERY_CHARGE_REG2,Battery charge control register 2. This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high. This is a vendor defined.." hexmask.long.byte 0x8 24.--31. 1. "RESERVED_R,Reserved field RO" newline hexmask.long.tbyte 0x8 0.--23. 1. "BATTERY_CHARGE_CTRL_REG2_DEFAULT,BATTERY_CHARGE_CTRL_REG2_DEFAULT" rgroup.long 0x1821C++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_BATTERY_CHARGE_REG3,Battery charge debug register. This register may be read from or written to at any time. including whilst the CNR field in the USBSTS register is high. This is a vendor defined.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_R,Reserved field RO" newline hexmask.long.tbyte 0x0 0.--23. 1. "BATTERY_CHARGE_DEBUG,Battery charge debug" rgroup.long 0x18220++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_HOST_CTRL_PORT_LINK_REG1,Feature #581. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for informative purposes." hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED_RW,Reserved field RW" newline bitfld.long 0x0 12.--13. "CFG_TIEBREAK_MODE,cfg_tiebreak_mode" "0,1,2,3" newline hexmask.long.byte 0x0 8.--11. 1. "CFG_TIEBREAK_VAL,cfg_tiebreak_val" newline hexmask.long.byte 0x0 2.--7. 1. "LINK_LTSSM_DEBUG_CTRL,link_debug_ctrl register:.link_ltssm_debug_ctrl. Possible values: stay_in_idle : bit 0 set. stay_in_ts1 : bit 1 set. stay_in_ts2 : bit 2 set. stay_in_tseq : bit 3 set." newline bitfld.long 0x0 0.--1. "LINK_8B_DEBUG_CTRL,link_debug_ctrl register:.link_8b_debug_ctrl. bit[0]: xmt_d102 bit[1]: xmt_comma." "0,1,2,3" rgroup.long 0x18370++0x7 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_USBLEGSUP,USB Legacy Support Capability. This register is an xHCI extended capability register. This register is used by pre-OS software (BIOS) and the operating system to coordinate ownership of the xHC." hexmask.long.byte 0x0 25.--31. 1. "RSVD2,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline bitfld.long 0x0 24. "HCOSOS,HC OS Owned Semaphore RW. Default = '0'. System software sets this bit to request ownership of the xHC. Ownership is obtained when this bit reads as '1' and the HC BIOS Owned Semaphore bit [HCBIOSOS] reads as '0'." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "RSVD1,Reserved: Reserved for future RO implementations. Registers or memory that shall be treated as read-only by system software. Rsvd registers shall return zero when read. Software shall ignore the value read from these bits. Note: At.." newline bitfld.long 0x0 16. "HCBIOSOS,HC BIOS Owned Semaphore [HCBIOSOS] RW. Default = '0'. The BIOS sets this bit to establish ownership of the xHC. System BIOS will set this bit to '0' in response to a request for ownership of the xHC by system software." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "NEXTCP,Next Capability Pointer RO. This field indicates the location of the next capability with respect to the effective address of this capability. A non-zero value in this register indicates a relative offset in Dwords from this Dword to the.." newline hexmask.long.byte 0x0 0.--7. 1. "CID,USB Legacy Support Capability ID RO. This capability provides the xHCI Pre-OS to OS Handoff Synchronization support capability." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_USBLEGCTLSTS,USB Legacy Support Control Status. Pre-OS (BIOS) software uses this register to enable System Management Interrupts (SMIs) for every xHCI/USB event it needs to track. Some bits of this.." bitfld.long 0x4 31. "SMIBAR,SMI on BAR RW1C. Default = '0'. This bit is set to '1' whenever the Base Address Register [BAR] is written." "0,1" newline bitfld.long 0x4 30. "SMIPCIC,SMI on PCI Command RW1C. Default = '0'. This bit is set to '1' whenever the PCI Command Register is written." "0,1" newline bitfld.long 0x4 29. "SMIOSOC,SMI on OS Ownership Change RW1C. Default = '0'. This bit is set to '1' whenever the HC OS Owned Semaphore bit in the USBLEGSUP register transitions from '1' to a '0' or '0' to a '1'." "0,1" newline hexmask.long.byte 0x4 21.--28. 1. "RSVD4,Reserved and Zero: Reserved for future RW1C implementations. Software shall use zero for writes to these bits. Note: At present the fields are implemented as RO." newline rbitfld.long 0x4 20. "SMIHSE,SMI on Host System Error RO. Default = '0'. Shadow bit of Host System Error [HSE] bit in the USBSTS register. Refer to Section 5.4.2 of xHCI specification for definition and effects of the events associated with this bit being set to '1'." "0,1" newline rbitfld.long 0x4 17.--19. "RSVD3,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 16. "SMIEI,SMI on Event Interrupt RO. Default = '0'. Shadow bit of Event Interrupt [EINT] bit in the USBSTS register. Refer to Section 5.4.2 of xHCI specification for definition. This bit follows the state the Event Interrupt [EINT] bit in the USBSTS.." "0,1" newline bitfld.long 0x4 15. "SMIBARE,SMI on BAR Enable RW. Default = '0'. When this bit is '1' and SMI on BAR is '1' then the host controller will issue an SMI." "0,1" newline bitfld.long 0x4 14. "SMIPCICE,SMI on PCI Command Enable RW. Default = '0'. When this bit is '1' and SMI on PCI Command is '1' then the host controller will issue an SMI." "0,1" newline bitfld.long 0x4 13. "SMIOSOE,SMI on OS Ownership Enable RW. Default = '0'. When this bit is a '1' AND the OS Ownership Change bit is '1' the host controller will issue an SMI." "0,1" newline hexmask.long.byte 0x4 5.--12. 1. "RSVD2,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." newline bitfld.long 0x4 4. "SMIHSEE,SMI on Host System Error Enable RW. Default = '0'. When this bit is a '1' and the SMI on Host System Error bit [below] in this register is a '1' the host controller will issue an SMI immediately." "0,1" newline rbitfld.long 0x4 1.--3. "RSVD1,Reserved and Preserved: Reserved for future RW implementations. Software shall preserve the value read for writes to bits. Note: At present the fields are implemented as RO." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "USBSMIE,USB SMI Enable RW. Default = '0'. When this bit is a '1' and the SMI on Event Interrupt bit [below] in this register is a '1' the host controller will issue an SMI immediately." "0,1" rgroup.long 0x18800++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_XECP_USB3_TEST_PORT0_REG,USB3_TEST_PORT_REG. This is a vendor defined capability. This register is reserved. This register should not be accessed by software. It is described only for informative purposes." hexmask.long.word 0x0 17.--31. 1. "LINK_TEST_LOOP_PASS,link_test_loop_pass" newline rbitfld.long 0x0 16. "LINK_TEST_DONE,link_test_done This field should not be modified by software" "0,1" newline hexmask.long.word 0x0 1.--15. 1. "USB3_TEST_LOOP_NUM,USB3_test_loop_num" newline bitfld.long 0x0 0. "USB3_TEST_CTRL,USB3_test_ctrl" "0,1" rgroup.long 0x20000++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_usb_conf,Global Configuration Register" bitfld.long 0x0 31. "LGO_SSINACT,SS.Inactive state entry request [SS mode only]. This bit can be used only if USBSS-DEV is part of the CDNS USB OTG Controller [USB_CAP.OTG_READY bit is 1 while reading]. In other cases should not be used and returns 0 when read. Writing '1'.." "0,1" newline bitfld.long 0x0 30. "LGO_U2,U2 state entry request [SS mode only]. Writing '1' will trigger an attempt to perform transition to U2 state. This bit will be automatically cleared to '0' after link layer finishes U2 request. Result of the request [link layer enters U2 or.." "0,1" newline bitfld.long 0x0 29. "LGO_U1,U1 state entry request [SS mode only]. Writing '1' will trigger an attempt to perform transition to U1 state. This bit will be automatically cleared to '0' after link layer finishes U1 request. Result of the request [link layer enters U1 or not].." "0,1" newline bitfld.long 0x0 28. "LGO_U0,U0 state entry request [SS mode only]. Writing '1' will trigger an attempt to perform transition to U0 state. If the link is suspended [U3 state] and CPU set this bit to'1' link will start driving resume signaling on its upstream link to indicate.." "0,1" newline bitfld.long 0x0 27. "U2DS,U2 state entry disable [SS mode only]. Writing '1' to this bit disables link layer from entering U2 state. Status of this bit can be checked in the USB_STS register. When both U2EN and U2DS bits are set to '1' while writing to USB_CONF register .." "0,1" newline bitfld.long 0x0 26. "U2EN,U2 state entry enable [device side SS mode only]. Writing '1' to this bit enables link layer to enter U2 state. Status of this bit can be checked in the USB_STS register. Writing '0' has no effect. When both U2EN and U2DS bits are set to '1' while.." "0,1" newline bitfld.long 0x0 25. "U1DS,U1 state entry disable [SS mode only]. Writing '1' to this bit disables link layer from entering U1 state. Status of this bit can be checked in the USB_STS register. Writing '0' has no effect. When both U1EN and U1DS bits are set to '1' while.." "0,1" newline bitfld.long 0x0 24. "U1EN,U1 state entry enable [device side SS mode only] Writing '1' to this bit enables link layer to enter U1 state. Status of this bit can be checked in the USB_STS register. Writing '0' has no effect. When both U1EN and U1DS bits are set to '1' while.." "0,1" newline rbitfld.long 0x0 23. "RESERVED3,Reserved field. Write ignored. 0 when read" "0,1" newline bitfld.long 0x0 22. "CLK3OFFDS,USB 3.0 clock gate enable. Writing '1' to this bit disables pclk clock turning-off when device enters U3 link state in SS mode. The actual 'USB 3.0 clock gate' status in can be checked in the USB_STS.USB3OFF register. When both CLK3OFFDS and.." "0,1" newline bitfld.long 0x0 21. "CLK3OFFEN,USB 3.0 clock gate disable. Writing '1' to this bit enables pclk clock turning-off when device enters U3 link state in SS mode. The actual 'USB 3.0 clock gate' status in can be checked in the USB_STS.USB3OFF register. When both CLK3OFFDS and.." "0,1" newline bitfld.long 0x0 20. "LGO_L0,L0 LPM state entry request [HS/FS mode only]. Writing '1' will trigger an attempt to perform transition to L0 LPM state. This bit will be automatically cleared to '0' after LPM enter L0 state. Result of the request [LPM enters L0 or not] can be.." "0,1" newline bitfld.long 0x0 19. "CLK2OFFDS,USB 2.0 clock gate enable. Writing '1' to this bit disables hsfs clock turning-off when device enters L2 LPM state in HS/FS mode. The actual 'USB 2.0 clock gate' status in can be checked in the USB_STS.USB2OFF register. When both CLK2OFFDS and.." "0,1" newline bitfld.long 0x0 18. "CLK2OFFEN,USB 2.0 clock gate disable. Writing '1' to this bit enables hsfs clock turning-off when device enters L2 LPM state in HS/FS mode. The actual 'USB 2.0 clock gate' status in can be checked in the USB_STS.USB2OFF register. When both CLK2OFFDS and.." "0,1" newline bitfld.long 0x0 17. "L1DS,L1 LPM state entry disable [HS/FS mode only]. Writing '1' to this bit disables USB2.0 LPM from entering L1 state. Status of this bit can be checked in the USB_STS register. Writing '0' has no effect. When both L1EN and L1DS bits are set to '1'.." "0,1" newline bitfld.long 0x0 16. "L1EN,L1 LPM state entry enable [device side HS/FS mode only]. Writing '1' to this bit enables USB2.0 LPM to enter L1 state. Status of this bit can be checked in the USB_STS register. Writing '0' has no effect. When both L1EN and L1DS bits are set to.." "0,1" newline bitfld.long 0x0 15. "DEVDS,Device disable. Writing '1' to the DEVDS bit sets to '0' the USB_STS.DEVS bit. Check also the DEVEN bit description. Writing '0' has no effect. This bit is always '0' while reading." "0,1" newline bitfld.long 0x0 14. "DEVEN,Device enable. After Power-On-Reset the USBSS_DEV is disconnected from the USB bus. To connect the device into the USB bus the software has to write '1' to DEVEN bit - this couse connection of the VBUS input to the internal device logic and.." "0,1" newline bitfld.long 0x0 13. "SFORCE_FS,Set Force Full Speed. Writing '1' to this bit forces Full Speed when USBSS-DEV operates in USB2.0 mode [disables High Speed]. When both SFORCE_FS and CFORCE_FS bits are set to '1' while writing to USB_CONF register the device behaviour is.." "0,1" newline bitfld.long 0x0 12. "CFORCE_FS,Clear Force Full Speed. Writing '1' to this bit stop forcing Full Speed when USBSS-DEV operates in USB2.0 mode [stop disabling High Speed]. When both SFORCE_FS and CFORCE_FS bits are set to '1' while writing to USB_CONF register the device.." "0,1" newline bitfld.long 0x0 11. "DMAOFFDS,DMA clock turn-off disable. Writing '1' to this bit disables DMA clock turning-off when device exits U0 link state in SuperSpeed mode. When both DMAOFFDS and DMAOFFEN bits are set to '1' while writing to USB_CONF register the device behaviour.." "0,1" newline bitfld.long 0x0 10. "DMAOFFEN,DMA clock turn-off enable. Writing '1' to this bit enables DMA clock turning-off when device exits U0 link state in SuperSpeed mode. When both DMAOFFDS and DMAOFFEN bits are set to '1' while writing to USB_CONF register the device behaviour is.." "0,1" newline rbitfld.long 0x0 9. "RESERVED2,Reserved field. Write ignored. 0 when read" "0,1" newline rbitfld.long 0x0 8. "RESERVED1,Reserved field. Write ignored. 0 when read" "0,1" newline bitfld.long 0x0 7. "SWRST,Device software reset. When set to 1 the entire USBSS-DEV is reset. The SWRST resets most flip-flops in entire USBSS-DEV. This bit is also used to connect disconnected device. Writing '0' has no effect." "0,1" newline bitfld.long 0x0 6. "BENDIAN,Big Endian Access. Writing '1' to this bit sets Big Endian byte order for SFRs access. Writing '0' has no effect. When both LENDIAN and BENDIAN bits are set to '1' while writing to USB_CONF register the device behaviour is udefined. This bit is.." "0,1" newline bitfld.long 0x0 5. "LENDIAN,Little Endian access. Writing '1' to this bit sets Little Endian byte order for SFRs access. By default [after hardware reset] USBSS-DEV acts as little-endian device. Writing '0' has no effect. When both LENDIAN and BENDIAN bits are set to '1'.." "0,1" newline bitfld.long 0x0 4. "USB2DIS,Disconnect USB device in HS/FS. Writing '1' to this bit disconnects USB in HS/FS. The actual USB connection status in HS/FS can be checked in the USB_STS register. Writing '0' has no effect. To connect disconnected device CPU performs software.." "0,1" newline bitfld.long 0x0 3. "USB3DIS,Disconnect USB device in SuperSpeed. Writing '1' to this bit disconnects USB in Super Speed. The actual USB connection status in the SS mode can be checked in the USB_STS register. If link is in U3 [SuperSpeed PHY clock is disabled] while.." "0,1" newline rbitfld.long 0x0 2. "RESERVED0,Reserved field. Write ignored. 0 when read" "0,1" newline bitfld.long 0x0 1. "CFGSET,Set Configuration. Software writes '1' to this bit when it receives SET_CONFIGURATION request with non-zero configuration number. CPU sets this bit after setting requested configuration and before setting REQ_CMPL bit in the EP_CMD register." "0,1" newline bitfld.long 0x0 0. "CFGRST,Reset USB device configuration. Writing '1' to this bit resets USB device configuration leaving only EP0 IN/OUT active [all other EP-related registers will be loaded with default values]. Any configuration/interface change including adding new.." "0,1" rgroup.long 0x20004++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_usb_sts,Global Status Register" bitfld.long 0x0 31. "ENDIAN,SFR Endian status. Little/Big Endian byte order for SFR access: 0 - Little Endian order [default after hardware reset] 1 - Big Endian order" "0: Little Endian order [default after hardware..,?" newline bitfld.long 0x0 30. "DMAOFF,DMA clock turn-off status. DMA clock turn-off/enable status: 0 - DMA clock is always on [default after hardware reset] 1 - DMA clock turn-off in U1 U2 and U3 [SS mode] is enabled." "0: DMA clock is always on [default after hardware..,?" newline hexmask.long.byte 0x0 26.--29. 1. "LST,SuperSpeed Link LTSSM state. This field reflects USBSS-DEV current SuperSpeed link state: 0 - U0 State 1 - U1 State 2 - U2 State 3 - U3 State [Device Suspended] 4 - Disabled State 5 - RxDetect State 6 - Inactive State 7 - Polling State 8 -.." newline bitfld.long 0x0 25. "U2ENS,U2 state enable status [valid in SS mode only]: 0 - Entering to U2 state disabled 1 - Entering to U2 state enabled" "0: Entering to U2 state disabled 1,?" newline bitfld.long 0x0 24. "U1ENS,U1 state enable status [valid in SS mode only]: 0 - Entering to U1 state disabled 1 - Entering to U1 state enabled" "0: Entering to U1 state disabled 1,?" newline bitfld.long 0x0 22.--23. "RESERVED2,Reserved field. Write ignored. 0 when read" "0,1,2,3" newline bitfld.long 0x0 21. "DISABLE_HS,DisableHS status [valid for HS/FS mode only] 0 - High Speed operations in USB2.0 [FS/HS] mode not disabled 1 - High Speed operations in USB2.0 [FS/HS] mode disabled" "0: High Speed operations in USB2,1: High Speed operations in USB2" newline bitfld.long 0x0 20. "USB2CONS,HS/FS mode connection enable status [valid for HS/FS mode only]. 0 - the disconnect bit for HS/FS mode is set [USB_CONF.USB2DIS] 1 - the disconnect bit for HS/FS mode is not set [device can be connected in this mode] The actual connection status.." "0: the disconnect bit for HS/FS mode is set [USB_CONF,1: the disconnect bit for HS/FS mode is not set.." newline bitfld.long 0x0 18.--19. "LPMST,HS/FS LPM state [valid for HS/FS mode only]. This field reflects USBSS-DEV current LPM [used in HS/FS mode] state: 0 - L0 State 1 - L1 State 2 - L2 State 3 - L3 State" "0: L0 State 1,?,2: L2 State 3,?" newline bitfld.long 0x0 17. "VBUSS,Internal VBUS connection status. 0 - internal VBUS is not detected 1 - internal VBUS is detected" "0: internal VBUS is not detected 1,?" newline bitfld.long 0x0 16. "L1ENS,L1 LPM state enable status [valid for HS/FS mode only]. 0 - Entering to L1 LPM state disabled 1 - Entering to L1 LPM state enabled" "0: Entering to L1 LPM state disabled 1,?" newline bitfld.long 0x0 15. "ADDRESSED,Address status: 0 - USB device is default state 1 - USB device is at least in address state [Function Address was set by the SW]" "0: USB device is default state 1,?" newline bitfld.long 0x0 14. "DEVS,Device enable Status 0 - USB device is disabled [VBUS input is disconnected from internal logic] 1 - USB device is enabled [VBUS input is connected to the internal logic] This bit can be changed by setting DEVEN or DEVDS bits in USB_CONF register." "0: USB device is disabled [VBUS input is..,?" newline bitfld.long 0x0 11.--13. "RESERVED1,Reserved field. Write ignored. 0 when read" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "IN_RST,Controler in reset state. This bit indicate that whole [in case of POR] or part of controller [in case of SWRST or USB resets] currently is in reset state. As controller has registers in both clock domains [system and USB] internal reset.." "0: Internal reset is active 1,?" newline bitfld.long 0x0 9. "CLK3OFF,PCLK clock turn-off status. When CLK3OFF bit is '0' the phypowerdown output signal is not set to '11' in U3 link state thus USB3.0 PHY does not turn off the pclk clock. 0 - pclk clock is always on 1 - pclk clock turn-off in U3 [SS mode] is.." "0: pclk clock is always on 1,?" newline bitfld.long 0x0 8. "CLK2OFF,HS/FS clock turn-off status. When CLK2OFF bit is '0' the utmisuspendm output signal is not set low in USB2.0 suspend state [L2 state] thus USB2.0 PHY does not turn off the hsfs clock 0 - hsfs clock is always on 1 - hsfs clock turn-off in L2.." "0: hsfs clock is always on 1,?" newline bitfld.long 0x0 7. "ENDIAN_MIRROR,Little/Big Endian byte order for SFR access. 0 - Little Endian order [default after hardware reset] 1 - Big Endian order Endian byte order for SFR access can be changed by setting BENDIAN or LEDNIAN bits in USB_CONF register." "0: Little Endian order [default after hardware..,?" newline bitfld.long 0x0 4.--6. "USBSPEED,Device speed: 0: undef. 1: LowSpeed [not supported] 2: FullSpeed 3: HighSpeed 4: SuperSpeed 5-7: Reserved" "0: undef,1: LowSpeed [not supported],2: FullSpeed,3: HighSpeed,4: SuperSpeed,?,?,7: Reserved" newline bitfld.long 0x0 3. "RESERVED0,Reserved field. Write ignored. 0 when read" "0,1" newline bitfld.long 0x0 2. "USB3CONS,SuperSpeed connection status. 0 - USB in SuperSpeed mode disconnected 1 - USB in SuperSpeed mode connected" "0: USB in SuperSpeed mode disconnected 1,?" newline bitfld.long 0x0 1. "MEM_OV,On-chip memory overflow. 0 - On-chip memory status OK 1 - On-chip memory overflow Memory overflow may occur if during enumeration [SET_CONFIGURATION request] device software will try to turn on too many endpoints or will try to set too much.." "0: On-chip memory status OK 1,?" newline bitfld.long 0x0 0. "CFGSTS,Configuration status. 1 - device is in the configured state 0 - device is not configured This bit set during SET_CONFIGURATION request means that status stage of this request was finished successfully thus device configuration was finished.." "?,1: device is in the configured state 0" rgroup.long 0x20008++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_usb_cmd,Global Command Register" hexmask.long.byte 0x0 28.--31. 1. "RESERVED1,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x0 24.--27. 1. "DNLTM_BELT_11_8,Device Notification 'Latency Tolerance Message' - BELT value [11:8] [SS mode only]. If user writes '1' to SDNLTM bit the device will send Device Notification 'Latency Tolerance Message' with 'BELT[11:8]' field value equal to.." newline hexmask.long.byte 0x0 16.--23. 1. "DNLTM_BELT_7_0,Device Notification 'Latency Tolerance Message' - BELT value [7:0] / Device Notification 'Function Wake' - Interface value [SS mode only]. This field must be filled up before one of the USB_CMD.SDNLTM/SDNFW bits is set and cannot be.." newline rbitfld.long 0x0 14.--15. "RESERVED0,Reserved field. Write ignored. 0 when read" "0,1,2,3" newline bitfld.long 0x0 13. "SPKT,Send Custom Transaction Packet [SS mode only] Writing '1' will trigger an attempt to send Custom TP as defined in the USB3.0 specification. The packet contents that will be send as TP to the host must be previously prepared in the CPKT1 [will be.." "0,1" newline bitfld.long 0x0 12. "SDNLTM,Send Latency Tolerance Message Device Notification TP [SS mode only]. Writing '1' will trigger an attempt to send Device Notification 'Latency Tolerance Message' with 'BELT' field set to DNLTM_BELT. This bit will be automatically cleared if the.." "0,1" newline bitfld.long 0x0 10.--11. "TMODE_SEL,Test mode selector [HS/FS mode only]. This field contains selected Test Mode - Device will enter this Test mode when '1' is written to STMODE. USB 2.0 Test mode selector: 00 - Test_J 01 - Test_K 10 - Test_SE0_NAK 11 - Test_Packet This field.." "0: Test_J,1: Test_K,?,?" newline bitfld.long 0x0 9. "STMODE,Set Test Mode [HS/FS mode only]. Writing the value '1 'to this bit causes the device enters into test mode selected by the TMODE_SEL field. Writing '0' has no effect. This bit is always '0' while reading." "0,1" newline bitfld.long 0x0 8. "SDNFW,Send Function Wake Device Notification TP [SS mode only]. Writing '1' will trigger an attempt to send 'Device Notification' with 'Interface' field set to DNFW_INT. This bit will be automatically cleared if the FW Notification TP is sent and only.." "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "FADDR,Function Address. This field is saved to the device only when the field SET_ADDR is set '1 ' during write to USB_CMD register. Software is responsible for entering the address of the device during SET_ADDRESS request service. This field should be.." newline bitfld.long 0x0 0. "SET_ADDR,Set Function Address. Writing the value '1 'to this bit causes the device is assigned to the USB Function Address according to the FADDR field. The device address must be saved by software when operating SET_ADDRESS request. After saving device.." "0,1" rgroup.long 0x2000C++0x7 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_usb_iptn,USB ITPN Reserved" hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0x0 0.--13. 1. "ITPN,ITP[SS] / SOF [HS/FS] number. In SS mode this field represent number of last ITP received from host. In HS/FS mode this field represent number of last SOF received from host." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_usb_lpm,USB LPM Register" hexmask.long 0x4 5.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline bitfld.long 0x4 4. "BRW,Remote Wakeup Enable [bRemoteWake]" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "HIRD,Host Initiated Resume Duration. This is the Resume duration from L1 LPM state received from the host in the latest Extended Token packet. For more information see chapter: 'HS/FS mode - Link Power Management'" rgroup.long 0x20014++0x1B line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_usb_ien,Interrupt Enable Register" rbitfld.long 0x0 30.--31. "RESERVED4,Reserved field. Write ignored. 0 when read" "0,1,2,3" newline bitfld.long 0x0 29. "UWRESEIEN,End of the USB SS warm reset interrupt enable. This bit enables requesting a UWRESEI interrupt" "0,1" newline bitfld.long 0x0 28. "UWRESSIEN,Start of the USB SS warm reset interrupt enable. This bit enables requesting a UWRESSI interrupt" "0,1" newline rbitfld.long 0x0 27. "RESERVED3,Reserved field. Write ignored. 0 when read" "0,1" newline bitfld.long 0x0 26. "CFGRESIEN,Configuration reset interrupt enable. This bit enables requesting a CFGRESI interrupt" "0,1" newline bitfld.long 0x0 25. "L1EXTIEN,LPM L1 state exit interrupt enable. This bit enables requesting an L1EXTI interrupt." "0,1" newline bitfld.long 0x0 24. "L1ENTIEN,LPM L1 state enter interrupt enable. This bit enables requesting an L1ENTI interrupt." "0,1" newline rbitfld.long 0x0 22.--23. "RESERVED2,Reserved field. Write ignored. 0 when read" "0,1,2,3" newline bitfld.long 0x0 21. "L2EXTIEN,LPM L2 state exit interrupt enable. This bit enables requesting a L2EXTI interrupt." "0,1" newline bitfld.long 0x0 20. "L2ENTIEN,LPM L2 state enter interrupt enable. This bit enables requesting a L2ENTI interrupt." "0,1" newline rbitfld.long 0x0 19. "RESERVED1,Reserved field. Write ignored. 0 when read" "0,1" newline bitfld.long 0x0 18. "U2RESIEN,USB reset [HS/FS mode] interrupt enable. This bit enables requesting an U2RESI interrupt." "0,1" newline bitfld.long 0x0 17. "DIS2IEN,HS/FS mode disconnection interrupt enable. This bit enables requesting a DIS2I interrupt." "0,1" newline bitfld.long 0x0 16. "CON2IEN,HS/FS mode connection interrupt enable. This bit enables requesting a CON2I interrupt." "0,1" newline rbitfld.long 0x0 13.--15. "RESERVED0,Reserved field. Write ignored. 0 when read" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12. "SPKTIEN,Send Custom Packet interrupt enable. This bit enables requesting a Send Custom Packet interrupt." "0,1" newline bitfld.long 0x0 11. "WAKEIEN,Wakeup interrupt enable. This bit enables requesting a Wakeup interrupt." "0,1" newline bitfld.long 0x0 10. "ITPIEN,ITP/SOF packet detected interrupt enable. This bit enables requesting an ITPI interrupt." "0,1" newline bitfld.long 0x0 9. "U1EXTIEN,SS link U1 state exit interrupt enable. This bit enables requesting an U1EXTI interrupt." "0,1" newline bitfld.long 0x0 8. "U1ENTIEN,SS link U1 state enter interrupt enable. This bit enables requesting an U1ENTI interrupt." "0,1" newline bitfld.long 0x0 7. "U2EXTIEN,SS link U2 state exit interrupt enable. This bit enables requesting an U2EXTI interrupt." "0,1" newline bitfld.long 0x0 6. "U2ENTIEN,SS link U2 state enter interrupt enable. This bit enables requesting an U2ENTI interrupt." "0,1" newline bitfld.long 0x0 5. "U3EXTIEN,SS link U3 state exit interrupt enable [wakeup]. This bit enables requesting an U3EXTI interrupt." "0,1" newline bitfld.long 0x0 4. "U3ENTIEN,SS link U3 state enter interrupt enable [suspend]. This bit enables requesting an U3ENTI interrupt." "0,1" newline bitfld.long 0x0 3. "UHRESIEN,USB SS hot reset interrupt enable. This bit enables requesting an UHRESI interrupt." "0,1" newline bitfld.long 0x0 2. "UWRESIEN,USB SS warm reset interrupt enable. This bit enables requesting an UWRESI interrupt." "0,1" newline bitfld.long 0x0 1. "DISIEN,SS disconnection interrupt enable. This bit enables requesting a DISI interrupt." "0,1" newline bitfld.long 0x0 0. "CONIEN,SS connection interrupt enable. This bit enables requesting a CONI interrupt." "0,1" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_usb_ists,USB Interrupt Status Register" rbitfld.long 0x4 30.--31. "RESERVED4,Reserved field. Write ignored. 0 when read" "0,1,2,3" newline bitfld.long 0x4 29. "UWRESEI,End of the USB warm reset detected. This interrupt is requested after the SuperSpeed warm reset ends. This interrupt is reported on the irqs[0] pin." "0,1" newline bitfld.long 0x4 28. "UWRESSI,Start of the USB warm reset detected. This interrupt is requested as soon as the SuperSpeed warm reset signalling is detected. This interrupt is reported on the irqs[0] pin." "0,1" newline rbitfld.long 0x4 27. "RESERVED3,Reserved field. Write ignored. 0 when read" "0,1" newline bitfld.long 0x4 26. "CFGRESI,USB configuration reset detected. This interrupt is requested after the device internally resets its endpoints onfiguration. This is done after each USB reset [UWRESI UWRESI or U2RESI] after each connection event [CONI CON2I] and after.." "0,1" newline bitfld.long 0x4 25. "L1EXTI,LPM L1 state exit detected This interrupt informs that HS/FS LPM exit L1 state. This interrupt is reported on the irqs[0] pin." "0,1" newline bitfld.long 0x4 24. "L1ENTI,LPM L1 state enter detected This interrupt informs that HS/FS LPM enter L1 state. This interrupt is reported on the irqs[0] pin." "0,1" newline rbitfld.long 0x4 22.--23. "RESERVED2,Reserved field. Write ignored. 0 when read" "0,1,2,3" newline bitfld.long 0x4 21. "L2EXTI,LPM L2 state exit detected This interrupt informs that HS/FS LPM exit L2 state. This interrupt is reported on the irqs[1] pin." "0,1" newline bitfld.long 0x4 20. "L2ENTI,LPM L2 state enter detected This interrupt informs that HS/FS LPM enter L2 state. This interrupt is reported on the irqs[0] pin." "0,1" newline rbitfld.long 0x4 19. "RESERVED1,Reserved field. Write ignored. 0 when read" "0,1" newline bitfld.long 0x4 18. "U2RESI,USB reset [HS/FS mode] detected This interrupt is requested after the USB reset in HS/FS mode ends. This interrupt is reported on the irqs[0] pin." "0,1" newline bitfld.long 0x4 17. "DIS2I,HS/FS mode disconnection detected This interrupt informs that HS/FS upstream port was disconncted from the USB line. This interrupt is reported on the irqs[0] pin." "0,1" newline bitfld.long 0x4 16. "CON2I,HS/FS mode connection detected This interrupt informs that HS/FS upstream port was conncted to the USB line This interrupt is reported on the irqs[0] pin." "0,1" newline rbitfld.long 0x4 13.--15. "RESERVED0,Reserved field. Write ignored. 0 when read" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12. "SPKTI,Send Custom Packet This interrupt informs that Custom Packet prepared in the USB_CPKT1-3 registers and triggered with USB_CMD.SPKT bit was already sent. This interrupt is reported on the irqs[0] pin." "0,1" newline bitfld.long 0x4 11. "WAKEI,This interrupt informs that at wakeup pin appeared active state. This interrupt is reported on the irqs[1] pin." "0,1" newline bitfld.long 0x4 10. "ITPI,ITP/SOF packet detected In SuperSpeed mode this interrupt informs that ITP packet was received. In FS/HS mode this interrupt informs that SOF was detected. This interrupt is reported on the irqs[0] pin." "0,1" newline bitfld.long 0x4 9. "U1EXTI,SS link U1 state exit detected This interrupt informs that SuperSpeed link exit U1 state. This interrupt is reported on the irqs[0] pin." "0,1" newline bitfld.long 0x4 8. "U1ENTI,SS link U1 state enter detected This interrupt informs that SuperSpeed link enter U1 state. This interrupt is reported on the irqs[0] pin." "0,1" newline bitfld.long 0x4 7. "U2EXTI,SS link U2 state exit detected This interrupt informs that SuperSpeed link exit U2 state. This interrupt is reported on the irqs[0] pin." "0,1" newline bitfld.long 0x4 6. "U2ENTI,SS link U2 state enter detected This interrupt informs that SuperSpeed link enter U2 state. This interrupt is reported on the irqs[0] pin." "0,1" newline bitfld.long 0x4 5. "U3EXTI,SS link U3 state exit detected [wakeup] This interrupt informs that SuperSpeed link exit U3 state. This interrupt is reported on the irqs[1] pin." "0,1" newline bitfld.long 0x4 4. "U3ENTI,SS link U3 state enter detected [suspend] This interrupt informs that SuperSpeed link enter U3 state. This interrupt is reported on the irqs[0] pin." "0,1" newline bitfld.long 0x4 3. "UHRESI,USB SS hot reset detected This interrupt is requested after the SuperSpeed hot reset ends. This interrupt is reported on the irqs[0] pin." "0,1" newline bitfld.long 0x4 2. "UWRESI,USB SS warm reset detected This interrupt is requested after the SuperSpeed warm reset ends or when USBSS-DEVs LTSSM exits Polling.LFPS state. After this reset SW should reininitialize the controller. This interrupt is reported on the irqs[0] pin." "0,1" newline bitfld.long 0x4 1. "DISI,SS disconnection detected This interrupt informs that SuperSpeed link was disconncted from the USB line. This interrupt is reported on the irqs[0] pin." "0,1" newline bitfld.long 0x4 0. "CONI,SS connection detected This interrupt informs that SuperSpeed link was conncted to the USB line This interrupt is reported on the irqs[0] pin." "0,1" line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ep_sel,Endpoint Select Register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1,Reserved field. Write ignored. 0 when read" newline bitfld.long 0x8 7. "DIR,Selected Endpoint direction. 0-OUT Endpoint selected 1-IN Endpoint selected" "0: OUT Endpoint selected,1: IN Endpoint selected" newline rbitfld.long 0x8 4.--6. "RESERVED0,Reserved field. Write ignored. 0 when read" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--3. 1. "EPNO,Selected Endpoint number" line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ep_traddr,Endpoint Transfer Ring Address Register" hexmask.long 0xC 0.--31. 1. "TRADDR,Transfer Ring address. Address of transfer ring for endpoint selected by endpoint select register. Based on this address DMA will fetch transfer descriptors from system memory. This register can be used as dequeue pointer. CPU can use this.." line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ep_cfg,Endpoint Configuration Register" hexmask.long.byte 0x10 27.--31. 1. "BUFFERING,Max number of buffered packets. The maximum number of packets the device can buffer in the on-chip memory for a specified endpoint. Valid values are from 0 to 15. Value 0 means that 1 on-chip buffer is available for the appropriate endpoint." newline hexmask.long.word 0x10 16.--26. 1. "MAXPKTSIZE,Max packet size. The maximum packet size this endpoint is capable of sending or receiving. SuperSpeed mode: For control endpoints this field is set to 512. For bulk endpoint types this field is set to 1024. For interrupt and isochronous.." newline bitfld.long 0x10 14.--15. "MULT,ISO max burst SuperSpeed mode: A zero-based value that indicates the maximum number of bursts within a service interval that this endpoint supports. This field is only valid for isochronous endpoints. A value of zero indicates that the device.." "0,1,2,3" newline rbitfld.long 0x10 12.--13. "RESERVED1,Reserved field. Write ignored. 0 when read" "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "MAXBURST,Maximum Burst size. The maximum number of packets the endpoint can send or receive as part of a burst. Valid values are from 0 to 15. A value of 0 indicates that the endpoint can only burst one packet at a time and a value of 15 indicates that.." newline bitfld.long 0x10 7. "EPENDIAN,DMA transfer endianness. When the conversion is ON the byte order within DWORD is inverted. While the bit is set the software confirms that the transfer length is a multiplication of 4 bytes. Enabling the conversion is possible only when.." "0: Endianess conversion OFF,1: Endianess conversion ON" newline rbitfld.long 0x10 6. "RESERVED0,Reserved field. Write ignored. 0 when read" "0,1" newline bitfld.long 0x10 5. "SID_CHK,SID check[only in SS mode for BULK OUT EP] This field can be set only for SS bulk OUT endpoints with stream support enabled 1] If SID_CHK bit is set the device checks whether the incoming packets from the host to the particular OUT endpoint have.." "0: SID chceck at device input OFF,1: SID chceck at device input ON" newline bitfld.long 0x10 4. "TDL_CHK,TDL check[only in SS mode for BULK OUT EP]. This field has to be set for stream capable SS bulk endpoints and it can be set for other bulk endpoint. The OUT bulk endpoints If the TDL_CHK bit is set if the device takes the packets to the OUT.." "0: Do not check the TDL value when..,1: Check the TDL value when sending/receiving.." newline bitfld.long 0x10 3. "STREAM_EN,Stream support enable [only in SS mode]. This bit must be set to enable a stream transfes on a bulk endpoint 0: Stream support OFF 1: Stream support ON" "0: Stream support OFF,1: Stream support ON" newline bitfld.long 0x10 1.--2. "EPTYPE,Endpoint type. 0: control 1: isochronous 2: bulk 3: interrupt. Endpoint type is programmable however certain types of transmissions require hardware support that must be incorporated prior to implementation. That can be done only for.." "0: control,1: isochronous,2: bulk,3: interrupt" newline bitfld.long 0x10 0. "ENABLE,Endpoint enable. If endpoint is disabled [the ENABLE bit is cleared] the endpoint will not: - request any interrupts - start any transmission over the DMA Even if Endpoint is disabled software can set DRDY bit for it but the DMA transmission.." "0: disabled,1: enabled Reset value of this bit for EP0 is 1" line.long 0x14 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ep_cmd,Endpoint Command Register" hexmask.long.word 0x14 16.--31. 1. "ERDY_SID,ERDY Stream ID value [used in SS mode]. This field contains SID - it will be sent to host in ERDY packet [by writing '1' to ERDY]. This field is meaningfull only in SuperSpeed mode." newline hexmask.long.byte 0x14 8.--15. 1. "RESERVED1,Reserved field. Write ignored. 0 when read" newline bitfld.long 0x14 7. "DFLUSH,Data flush. Writing '1' to this bit performs the following actions for particular endpoint: - clears DRDY bit and stops DMA transfer - flush endpoint data from on chip buffers As in case of Endpoint reset [EPRST bit] after endpoint data flush the.." "0,1" newline bitfld.long 0x14 6. "DRDY,Transfer descriptor ready. Transfer Descriptor Ready for selected endpoint [0 - no effect 1 - starts transfer]. Writing '1' to this bit informs USBSS-DEV that in-system memory has prepared a new Transfer Descriptor for selected endpoints. If an IN.." "0: no effect,1: starts transfer]" newline bitfld.long 0x14 5. "REQ_CMPL,Request complete. 0 : no effect 1 : informs device that Request service is complete Bit valid only for endpoint 0. Writing '1' to this bit informs USBSS-DEV that software finished USB request service and device can send ACK answer for the.." "0: no effect,1: informs device that Request service is complete.." newline rbitfld.long 0x14 4. "RESERVED0,Reserved field. Write ignored. 0 when read" "0,1" newline bitfld.long 0x14 3. "ERDY,Send ERDY TP. Writing '1' to this bit forces the device to send ERDY TP with stream ID equal to ERDY_SID. This bit is necessary to support SS bulk stream transfers. This bit is also used during control transfers [in both modes: HS/FS and SS]:.." "0,1" newline bitfld.long 0x14 2. "CSTALL,Endpoint STALL clear. Writing '1' to this bit cause the endpoint becames not halted. 0: no effect 1: clears endpoint STALL" "0: no effect,1: clears endpoint STALL" newline bitfld.long 0x14 1. "SSTALL,Endpoint STALL set. Writing '1' to this bit cause the endpoint is halted. 0: no effect 1: STALLs endpoint" "0: no effect,1: STALLs endpoint" newline bitfld.long 0x14 0. "EPRST,Endpoint reset. 0: no effect 1: resets endpoint This command performs the following actions for particular endpoint: - clears DRDY bit and stops DMA transfer - clears on-chip buffers - clears sequence number in SS mode or Data Toggle in HS/FS mode.." "0: no effect,1: resets endpoint This command performs the.." line.long 0x18 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ep_sts,Endpoint Status Register." bitfld.long 0x18 31. "STPWAIT,Bit used only for EP0. If setup packet is received correctly and stored in the on-chip buffer this bit is set to 1 and interrupt is generated. Setup packet is applicable only to control transmissions [EP0]. This interrupt can be masked by the.." "0,1" newline rbitfld.long 0x18 29.--30. "RESERVED1,Reserved field. Write ignored. 0 when read" "0,1,2,3" newline rbitfld.long 0x18 28. "OUTQ_VAL,OUT queue valid flag. This field indicates whether the endpoint number of the OUT packet waiting for transmission by the DMA is valid or not. In other words whether the packet queue is not empty. As there is one buffers queue for all Out.." "0: queue of out packets is empty thus OUTQ_NO is..,?" newline hexmask.long.byte 0x18 24.--27. 1. "OUTQ_NO,OUT queue endpoint number. This field shows the number of the endpoint to which the packet received by the host currently is waiting to be transmitted by the DMA from the on-chip buffers to the system memory. As there is one buffers queue for.." newline hexmask.long.byte 0x18 20.--23. 1. "RESERVED0,Reserved field. Write ignored. 0 when read" newline bitfld.long 0x18 19. "IOT,Interrupt On Transfer complete. This interrupt is generated when the TDL is decremented to zero. It means that the device - does not expect to have more packets from the host [OUT EP] - does not want to send more packets [IN EP] More information.." "0,1" newline rbitfld.long 0x18 17.--18. "SPSMST,Stream Protocol State Machine State [only for Bulk stream endpoints] This field is valid only for stream capable bulk endpoints and reflects the current state of the Stream Protocol State Machine for selected endpoint: 0 - DISABLED 1 - IDLE 2 -.." "0: DISABLED 1,?,2: START_STREAM 3,?" newline rbitfld.long 0x18 16. "HOSTPP,Host Packet Pending [only for SS mode]. Depending on whether the endpoint is enabled for streams or not this bit behaves as follows: 1]For stream enabled bulk endpoints [EP_CFG.EPSTREAM_EN bit set]: This bit reflects the PP bit in the last packet.." "0,1" newline bitfld.long 0x18 15. "ISOERR,ISO transmission error. Error of isochronous transmission. This bit is set during data transmission to/from ISO endpoints while the last data transfer at PIPE IF is in current micro frame. For ISO IN endpoints: If host asks for data packet and.." "0: length DATA packet to the host,?" newline bitfld.long 0x18 14. "OUTSMM,OUT size mismatch. This bit is set when host sends a different data size than device was anticipating [according to Data Length field in TRB]. In such a case the DMA updates length field in current TRB updates TRADDR [next TRB address] and.." "0,1" newline bitfld.long 0x18 13. "SIDERR,Stream error [used only in SS mode] If host requested IN [sent OUT] packet with particular Stream ID and device is actually programmed to transfer packets with different Stream ID [SID written in the EP_CMD.ERDY_SID field] the host IN request.." "0,1" newline bitfld.long 0x18 12. "PRIME,Prime [used only in SS mode]. This bit is set when the device receives the packet with PRIME ID. This interrupt can be masked by the corresponding bit in EP_STS_EN register. Writing '1' to this bit clears the interrupt." "0,1" newline rbitfld.long 0x18 11. "CCS,Current Cycle Status. Informs about current value of C bit corresponding to DMA ownership of TRBs for selected endpoint. For more information about TRBs C bit see chapter 2.11.3. This bit is only a status bit [not an interrupt flag]." "0,1" newline rbitfld.long 0x18 10. "BUFFEMPTY,Endpoint Buffer Empty. When this bit is set to '1' there are no packets for the particular endpoint in the on-chip buffers. This bit is only a status bit [not an interrupt flag]." "0,1" newline rbitfld.long 0x18 9. "DBUSY,DMA busy. This bit is set to '1' while the DMA services the endpoint. Through the service means either actual transmission of data between on-chip cache and system memory for particular endpoint or a pending data transmission which has already.." "0,1" newline bitfld.long 0x18 8. "NRDY,Not ready [used only in SS mode]. This bit is automatically set to 1 when for some reason endpoint enters Flow Control. If ERDY is sent automatically by the endpoint [what is done when current TDL value is greater then zero] this interrupt bit is.." "0,1" newline bitfld.long 0x18 7. "TRBERR,TRB error. This bit is set if DMA read corrupted TRB [wrong C bit value or TRB type]. Address of the TRB is stored in the EP_TRADDR register. This interrupt can be masked by the corresponding bit in EP_STS_EN register. If this error occurs the.." "0,1" newline bitfld.long 0x18 6. "MD_EXIT,EXIT from MOVE DATA State [used only for stream transfers in SS mode] This bit is set to '1' if stream capable endpoint exits from MOVE DATA state of Bulk IN/OUT Stream Ptrotocol State Machine [ISPSM/OSPSM]. Stream support is class-dependent." "0,1" newline bitfld.long 0x18 5. "STREAMR,Stream Rejected [used only in SS mode]. This bit is set to '1' if device tries to initiate stream number and host does not accept it. Stream support is class-dependent. This interrupt can be masked by the corresponding bit in STREAMREN register." "0,1" newline bitfld.long 0x18 4. "DESCMIS,Transfer descriptor missing. This bit is set to 1 and interrupt is generated when any of the following conditions are met: - device is requested to send data to host and none of Transfer Descriptor is prepared [IN transfer] - device receives OUT.." "?,1: This interrupt is not generated for ISO IN.." newline bitfld.long 0x18 3. "ISP,Interrupt on Short Packet. This bit is set to 1 and interrupt is generated when a transfer containing less data than MaxPacket for a given endpoint has been completed and transfer descriptor has been updated.Enabling or disabling of interrupt is.." "0,1" newline bitfld.long 0x18 2. "IOC,Interrupt On Complete When DMA transfer is completed and transfer descriptor is updated then this bit is set to 1 and interrupt is generated. Enabling or disabling of this interrupt is realized by IOC bit in transfer descriptor. Additionally this.." "0,1" newline rbitfld.long 0x18 1. "STALL,Endpoint STALL status 0 - endpoint is not stalled 1 - endpoint is stalled This bit is not treated as an interrupt [not reported in the EP__ISTS register]. This bit is read-only." "0: endpoint is not stalled 1,?" newline bitfld.long 0x18 0. "SETUP,Setup transfer complete. Bit used only for EP0. If setup type transmission has been completed and data from host has been received and copied to system memory this bit is set to '1' and interrupt is generated. Setup packet is applicable only to.." "0,1" rgroup.long 0x20030++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ep_sts_sid,Endpoint Status Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0x0 0.--15. 1. "SID,Stream ID [used only in SS mode]. Stream ID of packet which generates interrupt. The interrupts that update the SID field are: - SIDERR for EP OUT - SIDERR/DESCMIS for EP IN For the above interrupts the values of the SID field reflects: - in case.." rgroup.long 0x20034++0xB line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ep_sts_en,Endpoint Status Register Enable" bitfld.long 0x0 31. "STPWAITEN,Setup Wait interrupt enable. This bit enables the STPWAIT interrupt. Valid only for EP0" "0,1" newline hexmask.long.word 0x0 20.--30. 1. "RESERVED3,Reserved field. Write ignored. 0 when read" newline bitfld.long 0x0 19. "IOTEN,Interrupt on Transmission complete enable. This bit enables the IOT interrupt." "0,1" newline rbitfld.long 0x0 16.--18. "RESERVED2,Reserved field. Write ignored. 0 when read" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "ISOERREN,ISO transmission error enable. This bit enables the ISOERR interrupt." "0,1" newline bitfld.long 0x0 14. "OUTSMMEN,OUT size mismatch enable. This bit enables the OUTSMM interrupt." "0,1" newline bitfld.long 0x0 13. "SIDERREN,Stream error enable. This bit enables the SIDERR interrupt." "0,1" newline bitfld.long 0x0 12. "PRIMEEN,Prime enable. This bit enables the PRIME interrupt." "0,1" newline rbitfld.long 0x0 9.--11. "RESERVED1,Reserved field. Write ignored. 0 when read" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "NRDYEN,NRDY enable. This bit enables the NRDY interrupt." "0,1" newline bitfld.long 0x0 7. "TRBERREN,TRB enable. This bit enables the TRBERR interrupt." "0,1" newline bitfld.long 0x0 6. "MD_EXITEN,Move Data Exit enable. This bit enables the MD_EXIT interrupt." "0,1" newline bitfld.long 0x0 5. "STREAMREN,Stream Rejected enable. This bit enables the STREAMR interrupt." "0,1" newline bitfld.long 0x0 4. "DESCMISEN,OUT transfer missing descriptor enable. This bit enables the DESCMIS interrupt." "0,1" newline rbitfld.long 0x0 1.--3. "RESERVED0,Reserved field. Write ignored. 0 when read" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SETUPEN,Setup transfer complete. This bit enables the SETUP interrupt. Valid only for EP0." "0,1" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_drbl,Doorbell Register - used for initiating transfers with one access to USBSS-DEV. without use of the EP_SEL register(+EP_CMD.DRDY)" bitfld.long 0x4 31. "DRBL15I,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 30. "DRBL14I,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 29. "DRBL13I,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 28. "DRBL12I,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 27. "DRBL11I,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 26. "DRBL10I,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 25. "DRBL9I,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 24. "DRBL8I,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 23. "DRBL7I,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 22. "DRBL6I,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 21. "DRBL5I,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 20. "DRBL4I,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 19. "DRBL3I,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 18. "DRBL2I,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 17. "DRBL1I,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 16. "DRBL0I,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 15. "DRBL15O,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 14. "DRBL14O,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 13. "DRBL13O,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 12. "DRBL12O,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 11. "DRBL11O,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 10. "DRBL10O,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 9. "DRBL9O,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 8. "DRBL8O,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 7. "DRBL7O,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 6. "DRBL6O,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 5. "DRBL5O,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 4. "DRBL4O,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 3. "DRBL3O,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 2. "DRBL2O,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 1. "DRBL1O,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" newline bitfld.long 0x4 0. "DRBL0O,Dorbel Bit - used for initiating transfers for selected Endpoint" "0,1" line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ep_ien,Endpoints Interrupt Enable Register (1 - enables interrupt. 0 - disables interrupt)" bitfld.long 0x8 31. "EINEN15,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 30. "EINEN14,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 29. "EINEN13,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 28. "EINEN12,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 27. "EINEN11,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 26. "EINEN10,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 25. "EINEN9,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 24. "EINEN8,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 23. "EINEN7,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 22. "EINEN6,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 21. "EINEN5,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 20. "EINEN4,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 19. "EINEN3,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 18. "EINEN2,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 17. "EINEN1,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 16. "EINEN0,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 15. "EOUTEN15,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 14. "EOUTEN14,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 13. "EOUTEN13,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 12. "EOUTEN12,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 11. "EOUTEN11,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 10. "EOUTEN10,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 9. "EOUTEN9,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 8. "EOUTEN8,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 7. "EOUTEN7,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 6. "EOUTEN6,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 5. "EOUTEN5,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 4. "EOUTEN4,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 3. "EOUTEN3,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 2. "EOUTEN2,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 1. "EOUTEN1,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" newline bitfld.long 0x8 0. "EOUTEN0,Endpoints Interrupt Enable Bit [1 - enables interrupt 0 - disables interrupt]" "0: disables interrupt],1: enables interrupt" rgroup.long 0x20040++0x3 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ep_ists,Endpoints Interrupt Status Register. The EIN.n/EOUT.n bit corresponds to interrupt request of n-number endpoint. The reason for interrupt can be read from EP_STS. Interrupt remains valid until given.." bitfld.long 0x0 31. "EIN15,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 30. "EIN14,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 29. "EIN13,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 28. "EIN12,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 27. "EIN11,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 26. "EIN10,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 25. "EIN9,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 24. "EIN8,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 23. "EIN7,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 22. "EIN6,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 21. "EIN5,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 20. "EIN4,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 19. "EIN3,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 18. "EIN2,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 17. "EIN1,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 16. "EIN0,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 15. "EOUT15,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 14. "EOUT14,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 13. "EOUT13,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 12. "EOUT12,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 11. "EOUT11,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 10. "EOUT10,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 9. "EOUT9,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 8. "EOUT8,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 7. "EOUT7,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 6. "EOUT6,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 5. "EOUT5,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 4. "EOUT4,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 3. "EOUT3,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 2. "EOUT2,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 1. "EOUT1,Endpoints Interrupt Status Bit." "0,1" newline bitfld.long 0x0 0. "EOUT0,Endpoints Interrupt Status Bit." "0,1" rgroup.long 0x20044++0x7 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_usb_pwr,Global power configuration register" bitfld.long 0x0 31. "FAST_REG_ACCESS,Fast Registers Access. When Device Port is in a low power state [U3/L2/Not Connected] accesses to registers listed in section 2.3 of USBSS-DEV design specification may take long time. In order to enable fast register access in that case .." "0,1" newline rbitfld.long 0x0 30. "FAST_REG_ACCESS_STAT,Fast Registers Access status. This bit informs if Fast Registers Access is enabled. It should be used as described in FAST_REG_ACCESS bit." "0,1" newline hexmask.long.tbyte 0x0 10.--29. 1. "RESERVED1,Reserved field. Write ignored. 0 when read" newline rbitfld.long 0x0 9. "STB_CLK_SWITCH_DONE,Status bit indicating that operation required by STB_CLK_SWITCH_EN write is completed. This bit is optional and implemented only when support for OTG is implemented [indicated by OTG_READY bit set to 1]." "0,1" newline bitfld.long 0x0 8. "STB_CLK_SWITCH_EN,Enables turning-off Reference Clock. This bit is optional and implemented only when support for OTG is implemented [indicated by OTG_READY bit set to 1]. Should not be used when PHY Reference clock control is not supported" "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED0,Reserved field. Write ignored. 0 when read" newline bitfld.long 0x0 1. "PSO_DS,Power Shut Off capability disable. Writing '1' to this bit disables power domains switching capability and clears the PSO_EN bit. It is recommended to set this bit after during U3EXTI interrupt service." "0,1" newline bitfld.long 0x0 0. "PSO_EN,Power Shut Off capability enable. Writing '1' to this bit enables dower domains switching capability and clears the PSO_DS bit. The Domain will be switched off if both PSO_EN will be set and the USB controller will be in the in the U3 state. It is.." "0,1" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_usb_conf2,USB configuration register 2" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline bitfld.long 0x4 0. "AHB_RETRY_EN,AHB retry enable. This bit enables the AHB retrys for AHB slave interface. This bit has no effect when AHB slave interface is not implemented." "0,1" rgroup.long 0x2004C++0x17 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_usb_cap1,USB Capability Register 1" bitfld.long 0x0 29.--31. "RESERVED,This field is reserved and it is always 0 when reading." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "TDL_FROM_TRB,This field informs if device controller supports automatic internal TDL calculation basing on the size provided in TRB for DMULT mode: - 0 - controller doesn't support automatic internal TDL calculation - 1 -.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x0 27. "OTG_READY,This field informs if device is OTG ready: - pure device mode: 0x0 - some features and ports for CDNS USB OTG controller are implemented: 0x1." "0,1" newline bitfld.long 0x0 26. "U2PHY_WIDTH,USB2 PHY Interface width. This field reflects width of USB2 PHY interface implemented: - 8 bit interface: 0x0 - 16 bit interface: 0x1. Note: The ULPI interface is always 8-bit wide." "0,1" newline bitfld.long 0x0 25. "U2PHY_TYPE,USB2 PHY Interface type. This field reflects type of USB2 PHY interface implemented: - UTMI: 0x0 - ULPI: 0x1." "0,1" newline bitfld.long 0x0 24. "U2PHY_EN,USB2 PHY Interface enable. This field informs if USB2 PHY interface is implemented: - interface NOT implemented: 0x0 - interface implemented: 0x1." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "U3PHY_WIDTH,USB3 PHY Interface width. This field reflects width of USB3 PHY interface implemented: - 0x0: 8 bit PIPE interface - 0x1: 16 bit PIPE interface - 0x2: 32 bit PIPE interface - 0x3: 64.." newline hexmask.long.byte 0x0 16.--19. 1. "U3PHY_TYPE,USB3 PHY Interface type. This field reflects type of USB3 PHY interface implemented: - 0x0: USB PIPE - 0x1: RMMI - 0x2-0xF: reserved" newline hexmask.long.byte 0x0 12.--15. 1. "DMA_WIDTH,DMA Interface width. This field reflects width of DMA interface implemented: - 0x0: reserved - 0x1: reserved - 0x2: 32 bit interface - 0x3: 64 bit interface - 0x4-0xF:.." newline hexmask.long.byte 0x0 8.--11. 1. "DMA_TYPE,DMA Interface type. This field reflects type of DMA interface implemented: - 0x0: OCP - 0x1: AHB - 0x2: PLB - 0x3: AXI - 0x4-0xF: reserved" newline hexmask.long.byte 0x0 4.--7. 1. "SFR_WIDTH,SFR Interface width. This field reflects width of SFR interface implemented: - 0x0: 8 bit interface - 0x1: 16 bit interface - 0x2: 32 bit interface - 0x3: 64 bit interface .." newline hexmask.long.byte 0x0 0.--3. 1. "SFR_TYPE,SFR Interface type. This field reflects type of SFR interface implemented: 0x0 - OCP 0x1 - AHB 0x2 - PLB 0x3 - AXI 0x4 - APB 0x5-0xF - reserved." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_usb_cap2,USB Capability Register" hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED,This field is reserved and it is always 0 when reading." newline hexmask.long.byte 0x4 8.--12. 1. "MAX_MEM_SIZE,Max supported mem size. This field reflects width of on-chip RAM address bus width which determines max supported mem size: 0x0-0x7 reserved 0x8 - support for 4kB mem 0x9 - support for 8kB mem 0xA - support for 16kB mem 0xB - support.." newline hexmask.long.byte 0x4 0.--7. 1. "ACTUAL_MEM_SIZE,The actual size of the connected On-chip RAM memory in kB: - 0 means 256 kB [max supported mem size] - value other than 0 reflects the mem size in kB. This value reflects the.." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_usb_cap3,USB Capability Register 3. Implemented Endpoints. EPIN.n/EPOUT.n bit informs if n-number endpoint is implemented in the hardware. Default: all EP" hexmask.long.word 0x8 16.--31. 1. "EPIN_N,Endpoints IN" newline hexmask.long.word 0x8 0.--15. 1. "EPOUT_N,Endpoints OUT" line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_usb_cap4,ISO HW support for Endpoints implemented EPINI.n/EPOUTI.n bit informs if n- number endpoint has ISO support implemented in the hardware. Note that EP0 is not intended for isochronous transfers. so both.." hexmask.long.word 0xC 16.--31. 1. "EPINI_N,Endpoints IN" newline hexmask.long.word 0xC 0.--15. 1. "EPOUTI_N,Endpoints OUT" line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_usb_cap5,Bulk Stream HW support for Endpoints implemented. EPINS.n/EPOUTS.n bit informs if n-number endpoint has Bulk Stream support implemented in the hardware. Note that EP0 is not intended for stream.." hexmask.long.word 0x10 16.--31. 1. "EPINI_N,Endpoints IN" newline hexmask.long.word 0x10 0.--15. 1. "EPOUTI_N,Endpoints OUT" line.long 0x14 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_usb_cap6,Device controller version." hexmask.long 0x14 0.--31. 1. "VERSION,Device controller version." rgroup.long 0x20064++0x33 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_usb_cpkt1,Custom Packet value." hexmask.long 0x0 0.--31. 1. "CPKT1,Custom Packet value 1." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_usb_cpkt2,Custom Packet value." hexmask.long 0x4 0.--31. 1. "CPKT2,Custom Packet value 2." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_usb_cpkt3,Custom Packet value." hexmask.long 0x8 0.--31. 1. "CPKT3,Custom Packet value 3." line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ep_dma_ext_addr,Upper address for DMA" hexmask.long.word 0xC 16.--31. 1. "RESERVED0,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0xC 0.--15. 1. "EP_DMA_ADDR_H,Transfer Ring address. This register specify upper [above 32-bits] DMA address for each endpoint separatelly. This part of DMA address is not modified by the DMA. CPU can use this register [read it or write to it] only when endpoint is.." line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_buf_addr,Address for On-chip Buffer operations." hexmask.long 0x10 0.--31. 1. "BUF_ADDR,On-chip Memory Address. This register specify the address of the on-chip memory cell which is accessed using BUF_CTRL register." line.long 0x14 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_buf_data,Data for On-chip Buffer operations." hexmask.long 0x14 0.--31. 1. "BUF_DATA,Data for On-chip Buffer operations. This register specify the address of the on-chip memory cell which is accessed using BUF_CTRL register. For write operation this register must be written before WRITE command is issued using BUF_CTRL register." line.long 0x18 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_buf_ctrl,On-chip Buffer Access register." rbitfld.long 0x18 31. "BUF_CMD_STS,Status of BUF_CMD operations. This bit is set high when controller performs BUF CMD IWD and IWU operations. When it is set no other SFR or DMA operation can be issued to the controller." "0,1" newline hexmask.long 0x18 6.--30. 1. "RESERVED0,Reserved field. Write ignored. 0 when read" newline bitfld.long 0x18 5. "BUF_CMD_IWD,Incremental write counting down to device on-chip mem. Used for incremental writing data into device on-chip memory starting from address pointed by BUF_ADDR register [two lsb rounded down to 0]. To write data to memory the following order.." "0,1" newline bitfld.long 0x18 4. "BUF_CMD_IWU,Incremental write counting up to device on-chip mem. Used for incremental writing data into device on-chip memory starting from address pointed by BUF_ADDR register [two lsb rounded down to 0]. To write data to memory the following order.." "0,1" newline bitfld.long 0x18 3. "BUF_CMD_WR4,Write 4 words [16B] to device on-chip mem. Used for writing 4 words [4x duplicated BUF_DATA data] into device on-chip memory at address pointed by BUF_ADDR register [two lsb rounded down to 0]. To write data to memory the following order.." "0,1" newline bitfld.long 0x18 2. "BUF_CMD_RD,Read data [32B] from device on-chip mem. Used for reading data [1 word] from device on-chip memory from address pointed by BUF_ADDR register. To read data from memory the following order must be maintained: 1] BUF_ADDR register must be set.." "0,1" newline bitfld.long 0x18 1. "BUF_CMD_WR,Write 1 word [4B] to device on-chip mem. Used for writing 1 word [as prepared in BUF_DATA register] into device on-chip memory at address pointed by BUF_ADDR register. To write data to memory the following order must be maintained: 1].." "0,1" newline bitfld.long 0x18 0. "BUF_CMD_SET,Buffer Command Set. This bit must be written 1 in conjuction with one of WR RD WR4 IWD or IWU commands to make command effective. Only one command can be set at a moment. Commands WR WR4 and RD are executed immediatelly but after issuing.." "0,1" line.long 0x1C "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_dtrans,DMA transfer configuration Register (1 - DMULT mode. 0 - DSINGLE mode). Bits 0..15 applies to EPOUT0..EPOUT15 and bits 16..31 applies to EPIN0..EPIN15" bitfld.long 0x1C 31. "DTRANS15I,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 30. "DTRANS14I,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 29. "DTRANS13I,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 28. "DTRANS12I,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 27. "DTRANS11I,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 26. "DTRANS10I,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 25. "DTRANS9I,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 24. "DTRANS8I,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 23. "DTRANS7I,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 22. "DTRANS6I,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 21. "DTRANS5I,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 20. "DTRANS4I,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 19. "DTRANS3I,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 18. "DTRANS2I,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 17. "DTRANS1I,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 16. "DTRANS0I,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 15. "DTRANS15O,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 14. "DTRANS14O,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 13. "DTRANS13O,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 12. "DTRANS12O,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 11. "DTRANS11O,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 10. "DTRANS10O,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 9. "DTRANS9O,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 8. "DTRANS8O,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 7. "DTRANS7O,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 6. "DTRANS6O,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 5. "DTRANS5O,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 4. "DTRANS4O,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 3. "DTRANS3O,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 2. "DTRANS2O,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 1. "DTRANS1O,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" newline bitfld.long 0x1C 0. "DTRANS0O,DMA transfer configuration status for selected Endpoint[0 - single request - Single TRB chain. Single request [DRDY/Doorbell] triggers DMA which transfers single TRB chain only and ends the EP transfer. 1 - single request - Multiple TRB chain." "0: single request,1: single request" line.long 0x20 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_tdl_from_trb,Source of TDL configuration Register (1 - TDL read by DMA from TD_SIZE field in TRB . 0 - TDL programmed through EP_TDL register). Bits 0..15 applies to EPOUT0..EPOUT15 and bits 16..31 applies to.." bitfld.long 0x20 31. "TDL_FROM_TRB15I,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 30. "TDL_FROM_TRB14I,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 29. "TDL_FROM_TRB13I,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 28. "TDL_FROM_TRB12I,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 27. "TDL_FROM_TRB11I,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 26. "TDL_FROM_TRB10I,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 25. "TDL_FROM_TRB9I,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 24. "TDL_FROM_TRB8I,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 23. "TDL_FROM_TRB7I,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 22. "TDL_FROM_TRB6I,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 21. "TDL_FROM_TRB5I,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 20. "TDL_FROM_TRB4I,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 19. "TDL_FROM_TRB3I,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 18. "TDL_FROM_TRB2I,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 17. "TDL_FROM_TRB1I,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 16. "TDL_FROM_TRB0I,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 15. "TDL_FROM_TRB15O,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 14. "TDL_FROM_TRB14O,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 13. "TDL_FROM_TRB13O,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 12. "TDL_FROM_TRB12O,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 11. "TDL_FROM_TRB11O,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 10. "TDL_FROM_TRB10O,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 9. "TDL_FROM_TRB9O,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 8. "TDL_FROM_TRB8O,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 7. "TDL_FROM_TRB7O,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 6. "TDL_FROM_TRB6O,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 5. "TDL_FROM_TRB5O,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 4. "TDL_FROM_TRB4O,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 3. "TDL_FROM_TRB3O,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 2. "TDL_FROM_TRB2O,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 1. "TDL_FROM_TRB1O,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." newline bitfld.long 0x20 0. "TDL_FROM_TRB0O,This field informs if support for automatic internal TDL calculation basing on the size provided in TRB for DMULT mode is enabled for selected Endpoint. To enable/disable this feature use the ENABLE_TDL_TRB/DISABLE_TDL_TRB bits in the.." "0: controller doesn't support automatic internal..,1: controller supports automatic internal TDL.." line.long 0x24 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_tdl_beh,TDL behavior configuration Register. Value 0 means that USB short packet decrements TDL. value 1 means that USB short packet clears-blocks TDL (defined by TDL_BEH2 register). When specific Endpoint.." bitfld.long 0x24 31. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x24 30. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x24 29. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x24 28. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x24 27. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x24 26. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x24 25. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x24 24. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x24 23. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x24 22. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x24 21. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x24 20. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x24 19. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x24 18. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x24 17. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x24 16. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x24 15. "TDL_BEH15O,TDL behavior configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x24 14. "TDL_BEH14O,TDL behavior configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x24 13. "TDL_BEH13O,TDL behavior configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x24 12. "TDL_BEH12O,TDL behavior configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x24 11. "TDL_BEH11O,TDL behavior configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x24 10. "TDL_BEH10O,TDL behavior configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x24 9. "TDL_BEH9O,TDL behavior configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x24 8. "TDL_BEH8O,TDL behavior configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x24 7. "TDL_BEH7O,TDL behavior configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x24 6. "TDL_BEH6O,TDL behavior configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x24 5. "TDL_BEH5O,TDL behavior configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x24 4. "TDL_BEH4O,TDL behavior configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x24 3. "TDL_BEH3O,TDL behavior configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x24 2. "TDL_BEH2O,TDL behavior configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x24 1. "TDL_BEH1O,TDL behavior configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x24 0. "TDL_BEH0O,TDL behavior configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" line.long 0x28 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_ep_tdl,Endpoint TDL Register" hexmask.long.tbyte 0x28 11.--31. 1. "RESERVED0,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0x28 0.--10. 1. "TDL,This field can be used to update/read internal TDL counter when TDL_FROM_TRB mode is not enabled for specific Endpoint.Writing into this field any non-zero value will result in adding to existing TDL value the new written value. A as the maximum.." line.long 0x2C "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_tdl_beh2,TDL behavior 2 configuration Register. Value 0 means that USB short packet temporary gates TDL for protocol. allowing SW to read curent value of TDL. After SW reads TDL (on IOT irq) it should clear TDL.." bitfld.long 0x2C 31. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x2C 30. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x2C 29. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x2C 28. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x2C 27. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x2C 26. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x2C 25. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x2C 24. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x2C 23. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x2C 22. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x2C 21. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x2C 20. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x2C 19. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x2C 18. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x2C 17. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x2C 16. "RESERVED,Reserved field. Write ignored. 0 when read." "0,1" newline bitfld.long 0x2C 15. "TDL_BEH215O,TDL behavior 2 configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x2C 14. "TDL_BEH214O,TDL behavior 2 configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x2C 13. "TDL_BEH213O,TDL behavior 2 configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x2C 12. "TDL_BEH212O,TDL behavior 2 configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x2C 11. "TDL_BEH211O,TDL behavior 2 configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x2C 10. "TDL_BEH210O,TDL behavior 2 configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x2C 9. "TDL_BEH29O,TDL behavior 2 configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x2C 8. "TDL_BEH28O,TDL behavior 2 configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x2C 7. "TDL_BEH27O,TDL behavior 2 configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x2C 6. "TDL_BEH26O,TDL behavior 2 configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x2C 5. "TDL_BEH25O,TDL behavior 2 configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x2C 4. "TDL_BEH24O,TDL behavior 2 configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x2C 3. "TDL_BEH23O,TDL behavior 2 configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x2C 2. "TDL_BEH22O,TDL behavior 2 configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x2C 1. "TDL_BEH21O,TDL behavior 2 configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" newline bitfld.long 0x2C 0. "TDL_BEH20O,TDL behavior 2 configuration Bit. This register configures TDL behavior for selected Endpoint." "0,1" line.long 0x30 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_dma_adv_td,DMA Advance TD configuration Register (0 - when stopped during transfer. DMA will advance its address only to the next TRB (+12) start address. 1 - when stopped during transfer (e.g. on USB short.." bitfld.long 0x30 31. "DMA_ADV_TD15I,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 30. "DMA_ADV_TD14I,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 29. "DMA_ADV_TD13I,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 28. "DMA_ADV_TD12I,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 27. "DMA_ADV_TD11I,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 26. "DMA_ADV_TD10I,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 25. "DMA_ADV_TD9I,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 24. "DMA_ADV_TD8I,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 23. "DMA_ADV_TD7I,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 22. "DMA_ADV_TD6I,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 21. "DMA_ADV_TD5I,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 20. "DMA_ADV_TD4I,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 19. "DMA_ADV_TD3I,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 18. "DMA_ADV_TD2I,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 17. "DMA_ADV_TD1I,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 16. "DMA_ADV_TD0I,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 15. "DMA_ADV_TD15O,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 14. "DMA_ADV_TD14O,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 13. "DMA_ADV_TD13O,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 12. "DMA_ADV_TD12O,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 11. "DMA_ADV_TD11O,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 10. "DMA_ADV_TD10O,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 9. "DMA_ADV_TD9O,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 8. "DMA_ADV_TD8O,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 7. "DMA_ADV_TD7O,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 6. "DMA_ADV_TD6O,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 5. "DMA_ADV_TD5O,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 4. "DMA_ADV_TD4O,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 3. "DMA_ADV_TD3O,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 2. "DMA_ADV_TD2O,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 1. "DMA_ADV_TD1O,DMA Advance TD configuration Register for selected Endpoint." "0,1" newline bitfld.long 0x30 0. "DMA_ADV_TD0O,DMA Advance TD configuration Register for selected Endpoint." "0,1" rgroup.long 0x20100++0x8B line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg1,VBUS debouncer Configuration Register 1" hexmask.long.word 0x0 18.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.tbyte 0x0 0.--17. 1. "DEBOUNCER_CNT,This parameter defines the VBUS debouncer delay i.e. the time interval between the VBUS detection on device input and the start of using it internally. Resolution of this parameter is 128 ns. For simulation purposes it is.." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_dbg_link1,USB3.0 Configuration Register 2" hexmask.long.byte 0x4 28.--31. 1. "RESERVED1,Reserved field. Write ignored. 0 when read" newline bitfld.long 0x4 27. "LFPS_GEN_PING_SET,Set the LFPS_GEN_PING_SET value Writing '1' to this bit writes the LFPS_GEN_PING field value to the device. This bit is automatically cleared. Writing '0' has no effect." "0,1" newline bitfld.long 0x4 26. "RXDET_BREAK_DIS_SET,Set the RXDET_BREAK_DIS value Writing '1' to this bit writes the RXDET_BREAK_DIS field value to the device. This bit is automatically cleared. Writing '0' has no effect." "0,1" newline bitfld.long 0x4 25. "LFPS_MIN_GEN_U1_EXIT_SET,Set the LFPS_MIN_GEN_U1_EXIT value Writing '1' to this bit writes the LFPS_MIN_GEN_U1_EXIT field value to the device. This bit is automatically cleared. Writing '0' has no effect." "0,1" newline bitfld.long 0x4 24. "LFPS_MIN_DET_U1_EXIT_SET,Set the LFPS_MIN_DET_U1_EXIT value Writing '1' to this bit writes the LFPS_MIN_DET_U1_EXIT field value to the device. This bit is automatically cleared. Writing '0' has no effect." "0,1" newline rbitfld.long 0x4 22.--23. "RESERVED0,Reserved field. Write ignored. 0 when read" "0,1,2,3" newline hexmask.long.byte 0x4 17.--21. 1. "LFPS_GEN_PING,LFPS_GEN_PING value This parameter configures the LFPS.Ping generation time as shown in the chapter 4. This field is saved to the device only when the field LFPS_GEN_PING_SET is set to '1' during write to the DBG_LINK1 register." newline bitfld.long 0x4 16. "RXDET_BREAK_DIS,RXDET_BREAK_DIS value This parameter configures terminating the Far-end Receiver termination detection sequence: '0': it is possible that USBSS_DEV will terminate Far-end receiver termination detection sequence '1': USBSS_DEV.." "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "LFPS_MIN_GEN_U1_EXIT,LFPS_MIN_GEN_U1_EXIT value This parameter configures the minimum time for phytxelecidle deassertion when LFPS.U1_Exit signalling is generated as shown in the chapter 4. This field is saved to the device only when the field.." newline hexmask.long.byte 0x4 0.--7. 1. "LFPS_MIN_DET_U1_EXIT,LFPS_MIN_DET_U1_EXIT value This parameter configures the minimum time required for decoding the received LFPS as an LFPS.U1_Exit. Example is shown in the chapter 4. This field is saved to the device only when the field.." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_dbg_link2,USB3.0 Configuration Register 3" bitfld.long 0x8 31. "TXDET_DVAL_SET,Set the TXDET deassertion value Writing '1' to this bit writes the TXDET_DVAL field value to the device. This bit is automatically cleared. Writing '0' has no effect." "0,1" newline bitfld.long 0x8 30. "PHYRXVAL_DVAL_SET,Set the Phyrxvalid latency deassertion value Writing '1' to this bit writes the PHYRXVAL_DVAL field value to the device. This bit is automatically cleared. Writing '0' has no effect.0" "0,1" newline bitfld.long 0x8 29. "RXEQTR_DVAL_SET,Set the rxeqtraining deassertion value Writing '1' to this bit writes the RXEQTR_DVAL field value to the device. This bit is automatically cleared. Writing '0' has no effect." "0,1" newline bitfld.long 0x8 28. "RXEQTR_AVAL_SET,Set the rxeqtraining assertion value Writing '1' to this bit writes the RXEQTR_AVAL field value to the device. This bit is automatically cleared. Writing '0' has no effect." "0,1" newline rbitfld.long 0x8 27. "RESERVED,Reserved field. Write ignored. 0 when read" "0,1" newline bitfld.long 0x8 24.--26. "TXDET_DVAL,TXDET deassertion value This parameter configures the phytxdetrx_loop deassertion time after phystatus deassertion during Far-end receiver termination sequence as shown in the chapter 4. This field is saved to the device only when the.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 16.--23. 1. "PHYRXVAL_DVAL,Phyrxvalid latency deassertion value This parameter enables extending internal phyrxdata and phyrxdatak validity as shown in the chapter 4. This field is saved to the device only when the field PHYRXVAL_DVAL_SET is set to '1' during.." newline hexmask.long.byte 0x8 8.--15. 1. "RXEQTR_DVAL,Rxeqtraining deassertion value This parameter configures phyrxeqtraining deasserting time as shown in the chapter 4. This field is saved to the device only when the field RXEQTR_DVAL_SET is set to '1' during write to the DBG_LINK2.." newline hexmask.long.byte 0x8 0.--7. 1. "RXEQTR_AVAL,Rxeqtraining assertion value This parameter configures phyrxeqtraining asserting time as shown in the chapter 4. This field is saved to the device only when the field RXEQTR_AVAL_SET is set to '1' during write to the DBG_LINK2 register." line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg4,USB3.0 Configuration Register 4" bitfld.long 0xC 30.--31. "RXDETECT_QUIET_TIMEOUT_PRESCALE,PRESCALER for RXDETECT_QUIET_TIMEOUT : - 0x0 : 8ns [PHY pclk clock] - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout" "?,?,?,3: no clock" newline hexmask.long.tbyte 0xC 8.--29. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0xC 0.--7. 1. "RXDETECT_QUIET_TIMEOUT,RXDETECT_QUIET_TIMEOUT value Resolution of this parameter is selected by RXDETECT_QUIET_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 11*100us =~1ms [SystemC device ENV] - 13*1us =~12us.." line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg5,USB3.0 Configuration Register 5" bitfld.long 0x10 30.--31. "U3_HDSK_FAIL_TIMEOUT_PRESCALE,PRESCALER for U3_HDSK_FAIL_TIMEOUT : - 0x0 : 8ns [PHY pclk clock] - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout" "?,?,?,3: no clock" newline hexmask.long.tbyte 0x10 11.--29. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0x10 0.--10. 1. "U3_HDSK_FAIL_TIMEOUT,U3_HDSK_FAIL_TIMEOUT value Resolution of this parameter is selected by U3_HDSK_FAIL_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 11*100us =~1ms [SystemC device ENV] - 11*100us =~1ms [VIP.." line.long 0x14 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg6,Configuration Register 6" bitfld.long 0x14 30.--31. "SSINACTIVE_QUIET_TIMEOUT_PRESCALE,PRESCALER for SSINACTIVE_QUIET_TIMEOUT value: - 0x0 : 8ns [PHY pclk clock] - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout" "?,?,?,3: no clock" newline hexmask.long.tbyte 0x14 8.--29. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x14 0.--7. 1. "SSINACTIVE_QUIET_TIMEOUT,SSINACTIVE_QUIET_TIMEOUT value Resolution of this parameter is selected by SSINACTIVE_QUIET_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 11*100us =~1ms [SystemC device ENV] - 13*1us.." line.long 0x18 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg7,USB3.0 Configuration Register 7" bitfld.long 0x18 30.--31. "POLLING_LFPS_TIMEOUT_PRESCALE,PRESCALER for POLLING_LFPS_TIMEOUT value: - 0x0 : 8ns [PHY pclk clock] - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout" "?,?,?,3: no clock" newline hexmask.long.tbyte 0x18 13.--29. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0x18 0.--12. 1. "POLLING_LFPS_TIMEOUT,POLLING_LFPS_TIMEOUT value Resolution of this parameter is selected by POLLING_LFPS_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 11*100us =~1ms [SystemC device ENV] - 481*1us =~480us [VIP.." line.long 0x1C "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg8,USB3.0 Configuration Register 8" bitfld.long 0x1C 30.--31. "POLLING_ACTIVE_TIMEOUT_PRESCALE,PRESCALER for POLLING_ACTIVE_TIMEOUT value: - 0x0 : 8ns [PHY pclk clock] - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout" "?,?,?,3: no clock" newline hexmask.long.tbyte 0x1C 10.--29. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0x1C 0.--9. 1. "POLLING_ACTIVE_TIMEOUT,POLLING_ACTIVE_TIMEOUT value Resolution of this parameter is selected by POLLING_ACTIVE_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 11*100us =~1ms [SystemC device ENV] - 31*1us =~30us.." line.long 0x20 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg9,USB3.0 Configuration Register 9" bitfld.long 0x20 30.--31. "POLLING_IDLE_TIMEOUT_PRESCALE,PRESCALER for POLLING_IDLE_TIMEOUT value: - 0x0 : 8ns [PHY pclk clock] - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout" "?,?,?,3: no clock" newline hexmask.long 0x20 5.--29. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x20 0.--4. 1. "POLLING_IDLE_TIMEOUT,POLLING_IDLE_TIMEOUT value Resolution of this parameter is selected by POLLING_IDLE_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 21*100us =~2ms [SystemC device ENV] - 3*1us =~2us [VIP based.." line.long 0x24 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg10,USB3.0 Configuration Register 10" bitfld.long 0x24 30.--31. "POLLING_CONF_TIMEOUT_PRESCALE,PRESCALER for POLLING_CONF_TIMEOUT value: - 0x0 : 8ns [PHY pclk clock] - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout" "?,?,?,3: no clock" newline hexmask.long.tbyte 0x24 8.--29. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x24 0.--7. 1. "POLLING_CONF_TIMEOUT,POLLING_CONF_TIMEOUT value Resolution of this parameter is selected by POLLING_CONF_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 11*100us =~1ms [SystemC device ENV] - 31*1us =~30us [VIP.." line.long 0x28 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg11,USB3.0 Configuration Register 11" bitfld.long 0x28 30.--31. "RECOVERY_ACTIVE_TIMEOUT_PRESCALE,PRESCALER for RECOVERY_ACTIVE_TIMEOUT value: - 0x0 : 8ns [PHY pclk clock] - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout" "?,?,?,3: no clock" newline hexmask.long.tbyte 0x28 8.--29. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x28 0.--7. 1. "RECOVERY_ACTIVE_TIMEOUT,RECOVERY_ACTIVE_TIMEOUT value Resolution of this parameter is selected by RECOVERY_ACTIVE_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 11*100us =~1ms [SystemC device ENV] - 101*1us.." line.long 0x2C "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg12,USB3.0 Configuration Register 12" bitfld.long 0x2C 30.--31. "RECOVERY_CONF_TIMEOUT_PRESCALE,PRESCALER for RECOVERY_CONF_TIMEOUT value: - 0x0 : 8ns [PHY pclk clock] - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout" "?,?,?,3: no clock" newline hexmask.long.tbyte 0x2C 8.--29. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x2C 0.--7. 1. "RECOVERY_CONF_TIMEOUT,RECOVERY_CONF_TIMEOUT value Resolution of this parameter is selected by RECOVERY_CONF_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 11*100us =~1ms [SystemC device ENV] - 101*1us =~100us.." line.long 0x30 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg13,USB3.0 Configuration Register 13" bitfld.long 0x30 30.--31. "RECOVERY_IDLE_TIMEOUT_PRESCALE,PRESCALER for RECOVERY_IDLE_TIMEOUT value: - 0x0 : 8ns [PHY pclk clock] - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout" "?,?,?,3: no clock" newline hexmask.long.tbyte 0x30 5.--27. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x30 0.--4. 1. "RECOVERY_IDLE_TIMEOUT,RECOVERY_IDLE_TIMEOUT value Resolution of this parameter is selected by RECOVERY_IDLE_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 21*100us =~2ms [SystemC device ENV] - 3*1us =~3us [VIP.." line.long 0x34 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg14,USB3.0 Configuration Register 14" bitfld.long 0x34 30.--31. "HOTRESET_ACTIVE_TIMEOUT_PRESCALE,PRESCALER for HOTRESET_ACTIVE_TIMEOUT value: - 0x0 : 8ns [PHY pclk clock] - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout" "?,?,?,3: no clock" newline hexmask.long.tbyte 0x34 8.--29. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x34 0.--7. 1. "HOTRESET_ACTIVE_TIMEOUT,HOTRESET_ACTIVE_TIMEOUT value Resolution of this parameter is selected by HOTRESET_ACTIVE_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 21*100us =~2ms [SystemC device ENV] - 13*1us =~13us.." line.long 0x38 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg15,USB3.0 Configuration Register 15" bitfld.long 0x38 30.--31. "HOTRESET_EXIT_TIMEOUT_PRESCALE,PRESCALER for HOTRESET_EXIT_TIMEOUT value: - 0x0 : 8ns [PHY pclk clock] - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout" "?,?,?,3: no clock" newline hexmask.long 0x38 5.--29. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x38 0.--4. 1. "HOTRESET_EXIT_TIMEOUT,HOTRESET_EXIT_TIMEOUT value Resolution of this parameter is selected by HOTRESET_EXIT_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 21*100us =~2ms [SystemC device ENV] - 3*1us =~3us [VIP.." line.long 0x3C "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg16,USB3.0 Configuration Register 16" bitfld.long 0x3C 30.--31. "LFPS_PING_REPEAT_PRESCALE,PRESCALER for LFPS_PING_REPEAT value: - 0x0 : 8ns [PHY pclk clock] - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout" "?,?,?,3: no clock" newline hexmask.long.tbyte 0x3C 12.--29. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0x3C 0.--11. 1. "LFPS_PING_REPEAT,LFPS_PING_REPEAT value Resolution of this parameter is selected by LFPS_PING_REPEAT_PRESCALE. For simulation purposes it is recommended to set the value: - 6*100us =~0.5ms [SystemC device ENV] - 4*100us =~400us [VIP based ENV].." line.long 0x40 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg17,USB3.0 Configuration Register 17" bitfld.long 0x40 30.--31. "PENDING_HP_TIMEOUT_PRESCALE,PRESCALER for PENDING_HP_TIMEOUT value: - 0x0 : 8ns [PHY pclk clock] - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout" "?,?,?,3: no clock" newline hexmask.long.tbyte 0x40 10.--29. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0x40 0.--9. 1. "PENDING_HP_TIMEOUT,PENDING_HP_TIMEOUT value Resolution of this parameter is selected by PENDING_HP_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 437*8ns =~3.5us [SystemC device ENV] - 437*8ns =~3.5us [VIP based.." line.long 0x44 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg18,USB3.0 Configuration Register 18" bitfld.long 0x44 30.--31. "CREDIT_HP_TIMEOUT_PRESCALE,PRESCALER for CREDIT_HP_TIMEOUT value: - 0x0 : 8ns [PHY pclk clock] - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout" "?,?,?,3: no clock" newline hexmask.long.tbyte 0x44 7.--29. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x44 0.--6. 1. "CREDIT_HP_TIMEOUT,CREDIT_HP_TIMEOUT value Resolution of this parameter is selected by CREDIT_HP_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 11*100us =~1ms [SystemC device ENV] - 11*100us =~1ms [VIP based ENV].." line.long 0x48 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg19,USB3.0 Configuration Register 19" bitfld.long 0x48 30.--31. "LUP_TIMEOUT_PRESCALE,PRESCALER for LUP_TIMEOUT value: - 0x0 : 8ns [PHY pclk clock] - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout" "?,?,?,3: no clock" newline hexmask.long.tbyte 0x48 10.--29. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0x48 0.--9. 1. "LUP_TIMEOUT,LUP_TIMEOUT value Resolution of this parameter is selected by LUP_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 11*1us =~11us [SystemC device ENV] - 11*1us =~11us [VIP based ENV] For synthesis.." line.long 0x4C "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg20,USB3.0 Configuration Register 20" bitfld.long 0x4C 30.--31. "LDN_TIMEOUT_PRESCALE,PRESCALER for LDN_TIMEOUT value: - 0x0 : 8ns [PHY pclk clock] - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout" "?,?,?,3: no clock" newline hexmask.long.tbyte 0x4C 8.--29. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x4C 0.--7. 1. "LDN_TIMEOUT,LDN_TIMEOUT value Resolution of this parameter is selected by LDN_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 11*100us =~1ms [SystemC device ENV] - 129*1us =~129us [VIP based ENV] For synthesis.." line.long 0x50 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg21,USB3.0 Configuration Register 21" bitfld.long 0x50 30.--31. "PM_LC_TIMEOUT_PRESCALE,PRESCALER for PM_LC_TIMEOUT value: - 0x0 : 8ns [PHY pclk clock] - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout" "?,?,?,3: no clock" newline hexmask.long.tbyte 0x50 10.--29. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0x50 0.--9. 1. "PM_LC_TIMEOUT,PM_LC_TIMEOUT value Resolution of this parameter is selected by PM_LC_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 400*8ns =~3.2us [SystemC device ENV] - 400*8ns =~3.2us [VIP based ENV] For.." line.long 0x54 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg22,USB3.0 Configuration Register 22" bitfld.long 0x54 30.--31. "PM_ENTRY_TIMEOUT_PRESCALE,PRESCALER for PM_ENTRY_TIMEOUT value: - 0x0 : 8ns [PHY pclk clock] - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout" "?,?,?,3: no clock" newline hexmask.long.tbyte 0x54 11.--29. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0x54 0.--10. 1. "PM_ENTRY_TIMEOUT,PM_ENTRY_TIMEOUT value Resolution of this parameter is selected by PM_ENTRY_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 800*8ns =~6.4us [SystemC device ENV] - 800*8ns =~6.4us [VIP based ENV].." line.long 0x58 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg23,USB3.0 Configuration Register 23" bitfld.long 0x58 30.--31. "UX_EXIT_TIMEOUT_PRESCALE,PRESCALER for UX_EXIT_TIMEOUT value: - 0x0 : 8ns [PHY pclk clock] - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout" "?,?,?,3: no clock" newline hexmask.long.tbyte 0x58 7.--29. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x58 0.--6. 1. "UX_EXIT_TIMEOUT,UX_EXIT_TIMEOUT value Resolution of this parameter is selected by UX_EXIT_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 8*100us =~800us [SystemC device ENV] - 3*100us =~300us [VIP based ENV].." line.long 0x5C "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg24,USB3.0 Configuration Register 24" hexmask.long.word 0x5C 23.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.tbyte 0x5C 0.--22. 1. "LFPS_DET_RESET_MIN,LFPS_DET_RESET_MIN value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 395833 [~3.16ms] For synthesis purposes it is recommended to set the value 2375000 [~19ms]" line.long 0x60 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg25,USB3.0 Configuration Register 25" hexmask.long.byte 0x60 24.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.tbyte 0x60 0.--23. 1. "LFPS_DET_RESET_MAX,LFPS_DET_RESET_MAX value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 5000000 [~40ms] For synthesis purposes it is recommended to set the value 15000000 [~120ms]" line.long 0x64 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg26,USB3.0 Configuration Register 26" hexmask.long 0x64 7.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x64 0.--6. 1. "LFPS_DET_POLLING_MIN,LFPS_DET_POLLING_MIN value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 75 [~0.6us] For synthesis purposes it is recommended to set the value 75 [~0.6us]" line.long 0x68 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg27,USB3.0 Configuration Register 27" hexmask.long.tbyte 0x68 8.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x68 0.--7. 1. "LFPS_DET_POLLING_MAX,LFPS_DET_POLLING_MAX value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 175 [~1.4us] For synthesis purposes it is recommended to set the value 175 [~1.4us]" line.long 0x6C "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg28,USB3.0 Configuration Register 28" hexmask.long 0x6C 3.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline bitfld.long 0x6C 0.--2. "LFPS_DET_PING_MIN,LFPS_DET_PING_MIN value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 4 [~40ns] For synthesis purposes it is recommended to set the value 4 [~40ns]" "0,1,2,3,4,5,6,7" line.long 0x70 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg29,USB3.0 Configuration Register 29" hexmask.long 0x70 5.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x70 0.--4. 1. "LFPS_DET_PING_MAX,LFPS_DET_PING_MAX value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 23 [~200ns] For synthesis purposes it is recommended to set the value 23 [~200ns]" line.long 0x74 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg30,USB3.0 Configuration Register 30" hexmask.long 0x74 6.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x74 0.--5. 1. "LFPS_DET_U1EXIT_MIN,LFPS_DET_U1EXIT_MIN value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 36 [~300ns] For synthesis purposes it is recommended to set the value 36 [~300ns]" line.long 0x78 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg31,USB3.0 Configuration Register 31" hexmask.long 0x78 7.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x78 0.--6. 1. "LFPS_DET_U1EXIT_MAX,LFPS_DET_U1EXIT_MAX value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 111 [~900ns] For synthesis purposes it is recommended to set the value 111 [~900ns]" line.long 0x7C "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg32,USB3.0 Configuration Register 32" hexmask.long 0x7C 6.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x7C 0.--5. 1. "LFPS_DET_U2EXIT_MIN,LFPS_DET_U2EXIT_MIN value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 36 [~300ns] For synthesis purposes it is recommended to set the value 36 [~300ns]" line.long 0x80 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg33,USB3.0 Configuration Register 33" hexmask.long.word 0x80 18.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.tbyte 0x80 0.--17. 1. "LFPS_DET_U2EXIT_MAX,LFPS_DET_U2EXIT_MAX value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 250000 [~2ms] For synthesis purposes it is recommended to set the value 250000 [~2ms]" line.long 0x84 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg34,USB3.0 Configuration Register 34" hexmask.long 0x84 6.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x84 0.--5. 1. "LFPS_DET_U3EXIT_MIN,LFPS_DET_U3EXIT_MIN value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 36 [~300ns] For synthesis purposes it is recommended to set the value 36 [~300ns]" line.long 0x88 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg35,USB3.0 Configuration Register 35" hexmask.long.word 0x88 21.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.tbyte 0x88 0.--20. 1. "LFPS_DET_U3EXIT_MAX,LFPS_DET_U3EXIT_MAX value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 1250000 [~10ms] For synthesis purposes it is recommended to set the value 1250000 [~10ms]" rgroup.long 0x201AC++0x6F line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg36,USB3.0 Configuration Register 36" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x0 0.--4. 1. "LFPS_GEN_PING,LFPS_GEN_PING value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 24 [~200ns] For synthesis purposes it is recommended to set the value 24 [~200ns]" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg37,USB3.0 Configuration Register 37" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x4 0.--7. 1. "LFPS_GEN_POLLING,LFPS_GEN_POLLING value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 125 [~1us] For synthesis purposes it is recommended to set the value 125 [~1us]" line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg38,USB3.0 Configuration Register 38" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.tbyte 0x8 0.--17. 1. "LFPS_GEN_U1EXIT,LFPS_GEN_U1EXIT value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 62500 [~500us] For synthesis purposes it is recommended to set the value 250000 [~2ms]" line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg39,USB3.0 Configuration Register 39" hexmask.long.word 0xC 21.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.tbyte 0xC 0.--20. 1. "LFPS_GEN_U3EXIT,LFPS_GEN_U3EXIT value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 125000 [~1ms] For synthesis purposes it is recommended to set the value 1250000 [~10ms]" line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg40,USB3.0 Configuration Register 40" hexmask.long 0x10 7.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x10 0.--6. 1. "LFPS_MIN_GEN_U1EXIT,LFPS_MIN_GEN_U1EXIT value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 87 [~696ns] For synthesis purposes it is recommended to set the value 87 [~696ns]" line.long 0x14 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg41,USB3.0 Configuration Register 41" hexmask.long.tbyte 0x14 15.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0x14 0.--14. 1. "LFPS_MIN_GEN_U2EXIT,LFPS_MIN_GEN_U2EXIT value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 12500 [~100us] For synthesis purposes it is recommended to set the value 12500 [~100us]" line.long 0x18 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg42,USB3.0 Configuration Register 42" hexmask.long.tbyte 0x18 11.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0x18 0.--10. 1. "LFPS_POLLING_REPEAT,LFPS_POLLING_REPEAT value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 1250 [~10us] For synthesis purposes it is recommended to set the value 1250 [~10us]" line.long 0x1C "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg43,USB3.0 Configuration Register 43" hexmask.long.tbyte 0x1C 11.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0x1C 0.--10. 1. "LFPS_POLLING_MAX_TREPEAT,LFPS_POLLING_MAX_TREPEAT value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 1750 [~14us] For synthesis purposes it is recommended to set the value 1750 [~14us]" line.long 0x20 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg44,USB3.0 Configuration Register 44" hexmask.long.tbyte 0x20 11.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0x20 0.--10. 1. "LFPS_POLLING_MIN_TREPEAT,LFPS_POLLING_MIN_TREPEAT value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 748 [~6us] For synthesis purposes it is recommended to set the value 748 [~6us]" line.long 0x24 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg45,USB3.0 Configuration Register 45" bitfld.long 0x24 30.--31. "ITP_WAKEUP_TIMEOUT_PRESCALE,PRESCALER for ITP_WAKEUP_TIMEOUT value: - 0x0 : 8ns [PHY pclk clock] - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout" "?,?,?,3: no clock" newline hexmask.long.tbyte 0x24 7.--29. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x24 0.--6. 1. "ITP_WAKEUP_TIMEOUT,ITP_WAKEUP_TIMEOUT value Resolution of this parameter is selected by ITP_WAKEUP_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 101*1us =~100us [SystemC device ENV] - 101*1us =~100us [VIP based.." line.long 0x28 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg46,USB3.0 Configuration Register 46" hexmask.long.word 0x28 16.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0x28 0.--15. 1. "TSEQ_QUANTITY,TSEQ_QUANTITY value This parameter defines the number of TSEQ training sequences to be sent during Polling.RxEq state. For simulation purposes it is recommended to set the value 655 For synthesis purposes it is recommended to.." line.long 0x2C "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg47,USB3.0 Configuration Register 47" hexmask.long.word 0x2C 20.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.tbyte 0x2C 0.--19. 1. "ERDY_TIMEOUT_CNT,ERDY_TIMEOUT_CNT value Resolution of this parameter is 1 us. For simulation purposes it is recommended to set the value 16 [~15 us] For synthesis purposes it is recommended to set the value ~512001 [~512ms]" line.long 0x30 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg48,USB2.0 Configuration Register 48" hexmask.long.word 0x30 18.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.tbyte 0x30 0.--17. 1. "TWTRSTFS_J_CNT,Time a device operating in full speed must wait before begin the transition to the Suspend state after it see a constant Idle state on their upstream facing bus lines. Resolution of this parameter is 33.3 ns. For simulation.." line.long 0x34 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg49,USB2.0 Configuration Register 49" hexmask.long.word 0x34 16.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0x34 0.--15. 1. "TUCH_CNT,TUCH: Minimum duration of a Chirp K from a high-speed capable device within the reset protocol. Resolution of this parameter is 33.3 ns. For simulation purposes it is recommended to set the value 129 [~4.3us] For synthesis purposes.." line.long 0x38 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg50,USB2.0 Configuration Register 50" hexmask.long.tbyte 0x38 12.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0x38 0.--11. 1. "TWAITCHK_CNT,Time to wait before device will start to drive Chirp K after detecting reset signalling. Resolution of this parameter is 33.3 ns. For simulation purposes it is recommended to set the value 30 [~1us] For synthesis purposes it is.." line.long 0x3C "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg51,USB2.0 Configuration Register 51" hexmask.long.word 0x3C 17.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.tbyte 0x3C 0.--16. 1. "TWTFS_CNT,TWTFS: Time after end of upstream chirp at which device reverts to full speed default state if no downstream chirp is detected. Resolution of this parameter is 33.3 ns. For simulation purposes it is recommended to set the value 1000.." line.long 0x40 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg52,USB2.0 Configuration Register 52" hexmask.long.word 0x40 17.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.tbyte 0x40 0.--16. 1. "TWTREV_CNT,TWTREV: Time a high-speed capable device operating in high-speed must wait after start of SE0 before reverting to full-speed. Resolution of this parameter is 33.3 ns. For simulation purposes it is recommended to set the value 90112.." line.long 0x44 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg53,USB2.0 Configuration Register 53" hexmask.long.tbyte 0x44 15.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0x44 0.--14. 1. "TWTRSTHS_CNT,TWTRSTHS: Time a device must wait after reverting to full-speed before sampling the bus state for SE0 and beginning the high-speed detection handshake. Resolution of this parameter is 33.3 ns. For simulation purposes it is.." line.long 0x48 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg54,USB2.0 Configuration Register 54" hexmask.long.word 0x48 18.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.tbyte 0x48 0.--17. 1. "TWTRSM_CNT,TWTRSM: Period of idle bus before device can initiate resume. Resolution of this parameter is 33.3 ns. For simulation purposes it is recommended to set the value 150016 [~5ms] For synthesis purposes it is recommended to set the.." line.long 0x4C "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg55,USB2.0 Configuration Register 55" hexmask.long.word 0x4C 16.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0x4C 0.--15. 1. "TDRSMUP_CNT,TDRSMUP: Duration of driving resume upstream. Resolution of this parameter is 33.3 ns. For simulation purposes it is recommended to set the value 32768 [~1.1ms] For synthesis purposes it is recommended to set the value 32768 [~1.1ms]" line.long 0x50 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg56,USB2.0 Configuration Register 56" hexmask.long 0x50 6.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x50 0.--5. 1. "TOUTHS_CNT,Time after device expecting a response to a transmission will timeout the transaction. Resolution of this parameter is 33.3 ns. For simulation purposes it is recommended to set the value 48 [~1.6us] For synthesis purposes it is.." line.long 0x54 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg57,USB3.0 Configuration Register 57" hexmask.long 0x54 2.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline bitfld.long 0x54 0.--1. "LFPS_DEB_WIDTH,LFPS_DEB_WIDTH value This parameter defines the LFPS debouncer delay. Only two values are allowed: 0x1 or 0x2. For simulation purposes it is recommended to set the value 1. For synthesis purposes it is recommended to set the.." "0,1,2,3" line.long 0x58 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg58,USB3.0 Configuration Register 58" hexmask.long.word 0x58 18.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.tbyte 0x58 0.--17. 1. "LFPS_GEN_U2EXIT,LFPS_GEN_U2EXIT value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 62500 [~500us] For synthesis purposes it is recommended to set the value 250000 [~2ms]" line.long 0x5C "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg59,USB3.0 Configuration Register 59" hexmask.long.word 0x5C 16.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0x5C 0.--15. 1. "LFPS_MIN_GEN_U3EXIT,LFPS_MIN_GEN_U3EXIT value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 12500 [~100us] For synthesis purposes it is recommended to set the value 12500 [~100us]" line.long 0x60 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg60,USB3.0 Configuration Register 60" hexmask.long 0x60 7.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x60 0.--6. 1. "PORT_CONFIG_TIMEOUT,PORT_CONFIG_TIMEOUT value Resolution of this parameter is 1 us. For simulation purposes it is recommended to set the value 21 [~20us] For synthesis purposes it is recommended to set the value 21 [~20us]" line.long 0x64 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg61,USB3.0 Configuration Register 61" hexmask.long.tbyte 0x64 11.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0x64 0.--10. 1. "LFPS_POL_LFPS_TO_RXEQ,LFPS_POL_LFPS_TO_RXEQ value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value 250 [~2us] For synthesis purposes it is recommended to set the value 250 [~2us]" line.long 0x68 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg62,USB3.0 Configuration Register 62" bitfld.long 0x68 30.--31. "PHY_TX_LATENCY_PRESCALE,PRESCALER for PHY_TX_LATENCY value: - 0x0 : 8ns [PHY pclk clock] - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout" "?,?,?,3: no clock" newline hexmask.long.tbyte 0x68 6.--29. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x68 0.--5. 1. "PHY_TX_LATENCY,PHY_TX_LATENCY value This parameter defines latency from when data appear on PIPE interface to channel + 3 time units [defined by PHY_TX_LATENCY_PRESCALE]. For simulation purposes it is recommended to set the value 11. For.." line.long 0x6C "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg63,USB3.0 Configuration Register 63" hexmask.long.tbyte 0x6C 15.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.word 0x6C 0.--14. 1. "U2_INACTIVITY_TMOUT,U2_INACTIVITY_TMOUT value Resolution of this parameter is 8 ns. For simulation purposes it is recommended to set the value: - 31999*8ns =~256us [SystemC device ENV] - 249*8ns =~2us [VIP based ENV] For synthesis purposes it.." rgroup.long 0x20220++0xB line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg64,USB2.0 Configuration Register 64" hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x0 0.--6. 1. "TFILTSE0,TFILTSE0: Reset Handshake Protocol: Time for which a suspended highspeed capable device must see a continuous SE0 before beginning the high-speed detection handshake. Resolution of this parameter is 33.3ns. For simulation purposes it is.." line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg65,USB2.0 Configuration Register 65" hexmask.long.tbyte 0x4 15.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x4 0.--6. 1. "TFILT,TFILT: Time for which a Chirp J or Chirp K must be continuously detected [filtered] by hub or device during Reset handshake. Resolution of this parameter is 33.3 ns. For simulation purposes it is recommended to set the value: - 75*33.3ns.." line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_cfg_reg66,USB2.0 Configuration Register 66" hexmask.long.tbyte 0x8 15.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x8 0.--6. 1. "TWTRSTFS_SE0,TWTRSTFS: Time a high-speed capable device operating in non-suspended fullspeed must wait after start of SE0 before beginning the high-speed detection handshake. Resolution of this parameter is 33.3 ns. For simulation purposes it is.." rgroup.long 0x20300++0x17 line.long 0x0 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_dma_axi_ctrl,DMA AXI Master Control register." hexmask.long.byte 0x0 26.--31. 1. "RESERVED3,Reserved field. Write ignored. 0 when read" newline bitfld.long 0x0 24.--25. "MAWLOCK,The mawlock pin configuration" "0,1,2,3" newline hexmask.long.byte 0x0 20.--23. 1. "MAWCACHE,The mawcache pin configuration" newline rbitfld.long 0x0 19. "RESERVED2,Reserved field. Write ignored. 0 when read" "0,1" newline bitfld.long 0x0 16.--18. "MAWPROT,The mawprot pin configuration" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED1,Reserved field. Write ignored. 0 when read" newline bitfld.long 0x0 8.--9. "MARLOCK,The marlock pin configuration" "0,1,2,3" newline hexmask.long.byte 0x0 4.--7. 1. "MARCACHE,The marcache pin configuration" newline rbitfld.long 0x0 3. "RESERVED0,Reserved field. Write ignored. 0 when read" "0,1" newline bitfld.long 0x0 0.--2. "MARPROT,The marprot pin configuration" "0,1,2,3,4,5,6,7" line.long 0x4 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_dma_axi_id,DMA AXI Master ID register." hexmask.long.word 0x4 21.--31. 1. "RESERVED1,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x4 16.--20. 1. "MAR_ID,The marid pin configuration" newline hexmask.long.word 0x4 5.--15. 1. "RESERVED0,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x4 0.--4. 1. "MAW_ID,The mawid and mwid pin configuration" line.long 0x8 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_dma_axi_cap,DMA AXI Master Extended Capability register." rbitfld.long 0x8 31. "RESERVED2,Reserved field. Write ignored. 0 when read" "0,1" newline rbitfld.long 0x8 30. "AXI_IDLE,This bit provides information about the AXI Master state: '1': no pending action required by the AXI Master wrapper '0': the AXI Master wrapper has outstanding transactions." "0,1" newline bitfld.long 0x8 29. "AXI_SLVERR,This bit provides an information about AXI SLAVE ERROR response on B or R channel. This flag is cleared by writing '1' to it. Once set it is held until cleared." "0,1" newline bitfld.long 0x8 28. "AXI_DECERR,This bit provides an information about AXI DECODE ERROR response on B or R channel. This flag is cleared by writing '1' to it. Once set it is held until cleared." "0,1" newline hexmask.long.byte 0x8 22.--27. 1. "RESERVED1,Reserved field. Write ignored. 0 when read" newline bitfld.long 0x8 21. "AXI_SLVERR_EN,This bit enables interrupt on AXI SLAVE ERROR detection. When 1 and AXI_SLVERR is 1 then AXI SLAVE ERROR interrupt is requested. When 0 - disabled interrupt from this source" "0: disabled interrupt from this source,?" newline bitfld.long 0x8 20. "AXI_DECERR_EN,This bit enables interrupt on AXI DECODE ERROR detection. When 1 and AXI_DECERR is 1 then AXI DECODE ERROR interrupt is requested. When 0 - disabled interrupt from this source" "0: disabled interrupt from this source,?" newline hexmask.long.tbyte 0x8 0.--19. 1. "RESERVED0,Reserved field. Write ignored. 0 when read" line.long 0xC "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_dma_axi_ctrl0,DMA AXI Master Control0 register." hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0xC 0.--3. 1. "B_MAX,The register controls maximum burst length - it is used by the AXI Master wrapper to determine maximum value of AxLEN. It uses AXI AxLEN encoding. Default value is the maximum supported one and it is implementation specific. Width of this register.." line.long 0x10 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_dma_axi_ctrl1,DMA AXI Master Control1 register." hexmask.long.word 0x10 21.--31. 1. "RESERVED1,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x10 16.--20. 1. "WOT,Number of outstanding write transactions that can be initiated by the AXI Master wrapper. Default value of this field is CDNS_USBSSDEV_AXI_WCD-1 [define parameter]. The value written to this field should be the requested number of outstanding write.." newline hexmask.long.word 0x10 5.--15. 1. "RESERVED0,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x10 0.--4. 1. "ROT,Number of outstanding read transactions that can be initiated by the AXI Master wrapper. Default value of this field is CDNS_USBSSDEV_AXI_WCD-1 [define parameter]. The value written to this field should be the requested number of outstanding read.." line.long 0x14 "VBP2APB_WRAP__CONTROLLER_VBP__CORE_ADDR_MAP_dma_axi_ctrl2,AXI Master Wrapper Extended Capability Control Register 2. This register may be read from or written to at any time." hexmask.long 0x14 7.--31. 1. "RESERVED0,Reserved field. Write ignored. 0 when read" newline hexmask.long.byte 0x14 0.--6. 1. "AXI_WTHRES,AXI Write Buffer Threshold RW. When performing an AXI write burst this field specifies the minimum number of required AXI beats buffered prior to starting the burst on AXI W-Channel by asserting wvalid. This allows.." tree.end tree.end tree "VPAC0" base ad:0x0 tree "VPAC0_CP_INTD_CFG_INTD_CFG (VPAC0_CP_INTD_CFG_INTD_CFG)" base ad:0x3804000 rgroup.long 0x0++0x3 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_REVISION,Revision Register" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTLVER,RTL revisions" newline bitfld.long 0x0 8.--10. "MAJREV,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,Minor revision" rgroup.long 0x10++0x3 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_eoi_reg,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector" rgroup.long 0x14++0x3 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg,Interrupt Vector Register" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR,Interrupt Vector Register" rgroup.long 0x100++0x17F line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_0_0,Enable Register 0" bitfld.long 0x0 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_CR_CFG_ERR,Enable Set for level_vpac_out_0_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x0 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for level_vpac_out_0_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x0 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for level_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x0 23. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for level_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x0 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x0 21. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x0 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for level_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x0 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for level_vpac_out_0_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x0 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_EE_CFG_ERR,Enable Set for level_vpac_out_0_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x0 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for level_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x0 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for level_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x0 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCC_CFG_ERR,Enable Set for level_vpac_out_0_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x0 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCFA_CFG_ERR,Enable Set for level_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x0 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_VP_ERR,Enable Set for level_vpac_out_0_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x0 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for level_vpac_out_0_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x0 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for level_vpac_out_0_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x0 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_DONE,Enable Set for level_vpac_out_0_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x0 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_START,Enable Set for level_vpac_out_0_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x0 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_CFG_ERR,Enable Set for level_vpac_out_0_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x0 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for level_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x0 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for level_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x0 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for level_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x0 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for level_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x0 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for level_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x0 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_AF_PULSE,Enable Set for level_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x0 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for level_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x0 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_CFG_ERR,Enable Set for level_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_0_1,Enable Register 1" bitfld.long 0x4 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_VBUSM_RD_ERR,Enable Set for level_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x4 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_SL2_WR_ERR,Enable Set for level_vpac_out_0_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x4 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_FR_DONE_EVT,Enable Set for level_vpac_out_0_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x4 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_INT_SZOVF,Enable Set for level_vpac_out_0_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x4 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_IFR_OUTOFBOUND,Enable Set for level_vpac_out_0_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x4 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for level_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x4 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for level_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x4 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x4 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x8 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_0_2,Enable Register 2" bitfld.long 0x8 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_NF_SL2_RD_ERR,Enable Set for level_vpac_out_0_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x8 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_NF_SL2_WR_ERR,Enable Set for level_vpac_out_0_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x8 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_NF_FRAME_DONE,Enable Set for level_vpac_out_0_en_nf_frame_done" "0,1" newline bitfld.long 0x8 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x8 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x8 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for level_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x8 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for level_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xC "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_0_3,Enable Register 3" bitfld.long 0xC 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_6,Enable Set for level_vpac_out_0_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xC 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_5,Enable Set for level_vpac_out_0_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xC 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_4,Enable Set for level_vpac_out_0_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xC 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_2,Enable Set for level_vpac_out_0_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xC 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_vpac_out_0_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xC 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_1_LEVEL,Enable Set for level_vpac_out_0_en_spare_pend_1_level" "0,1" newline bitfld.long 0xC 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_1_PULSE,Enable Set for level_vpac_out_0_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0xC 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_0_LEVEL,Enable Set for level_vpac_out_0_en_spare_pend_0_level" "0,1" newline bitfld.long 0xC 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_0_PULSE,Enable Set for level_vpac_out_0_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xC 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_DEC_1,Enable Set for level_vpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0xC 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_DEC_0,Enable Set for level_vpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0xC 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_6,Enable Set for level_vpac_out_0_en_tdone_6" "0,1" newline bitfld.long 0xC 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_5,Enable Set for level_vpac_out_0_en_tdone_5" "0,1" newline bitfld.long 0xC 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_4,Enable Set for level_vpac_out_0_en_tdone_4" "0,1" newline bitfld.long 0xC 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_2,Enable Set for level_vpac_out_0_en_tdone_2" "0,1" newline bitfld.long 0xC 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_0,Enable Set for level_vpac_out_0_en_tdone_0" "0,1" newline bitfld.long 0xC 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_6,Enable Set for level_vpac_out_0_en_pipe_done_6" "0,1" newline bitfld.long 0xC 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_5,Enable Set for level_vpac_out_0_en_pipe_done_5" "0,1" newline bitfld.long 0xC 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_4,Enable Set for level_vpac_out_0_en_pipe_done_4" "0,1" newline bitfld.long 0xC 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_3,Enable Set for level_vpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0xC 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_2,Enable Set for level_vpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0xC 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_1,Enable Set for level_vpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0xC 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_0,Enable Set for level_vpac_out_0_en_pipe_done_0" "0,1" line.long 0x10 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_0_4,Enable Register 4" bitfld.long 0x10 31. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_31,Enable Set for level_vpac_out_0_en_utc0_complete_31" "0,1" newline bitfld.long 0x10 30. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_30,Enable Set for level_vpac_out_0_en_utc0_complete_30" "0,1" newline bitfld.long 0x10 29. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_29,Enable Set for level_vpac_out_0_en_utc0_complete_29" "0,1" newline bitfld.long 0x10 28. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_28,Enable Set for level_vpac_out_0_en_utc0_complete_28" "0,1" newline bitfld.long 0x10 27. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_27,Enable Set for level_vpac_out_0_en_utc0_complete_27" "0,1" newline bitfld.long 0x10 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_26,Enable Set for level_vpac_out_0_en_utc0_complete_26" "0,1" newline bitfld.long 0x10 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_25,Enable Set for level_vpac_out_0_en_utc0_complete_25" "0,1" newline bitfld.long 0x10 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_24,Enable Set for level_vpac_out_0_en_utc0_complete_24" "0,1" newline bitfld.long 0x10 23. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_23,Enable Set for level_vpac_out_0_en_utc0_complete_23" "0,1" newline bitfld.long 0x10 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_22,Enable Set for level_vpac_out_0_en_utc0_complete_22" "0,1" newline bitfld.long 0x10 21. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_21,Enable Set for level_vpac_out_0_en_utc0_complete_21" "0,1" newline bitfld.long 0x10 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_20,Enable Set for level_vpac_out_0_en_utc0_complete_20" "0,1" newline bitfld.long 0x10 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_19,Enable Set for level_vpac_out_0_en_utc0_complete_19" "0,1" newline bitfld.long 0x10 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_18,Enable Set for level_vpac_out_0_en_utc0_complete_18" "0,1" newline bitfld.long 0x10 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_17,Enable Set for level_vpac_out_0_en_utc0_complete_17" "0,1" newline bitfld.long 0x10 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_16,Enable Set for level_vpac_out_0_en_utc0_complete_16" "0,1" newline bitfld.long 0x10 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_15,Enable Set for level_vpac_out_0_en_utc0_complete_15" "0,1" newline bitfld.long 0x10 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_14,Enable Set for level_vpac_out_0_en_utc0_complete_14" "0,1" newline bitfld.long 0x10 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_13,Enable Set for level_vpac_out_0_en_utc0_complete_13" "0,1" newline bitfld.long 0x10 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_12,Enable Set for level_vpac_out_0_en_utc0_complete_12" "0,1" newline bitfld.long 0x10 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_11,Enable Set for level_vpac_out_0_en_utc0_complete_11" "0,1" newline bitfld.long 0x10 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_10,Enable Set for level_vpac_out_0_en_utc0_complete_10" "0,1" newline bitfld.long 0x10 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_9,Enable Set for level_vpac_out_0_en_utc0_complete_9" "0,1" newline bitfld.long 0x10 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_8,Enable Set for level_vpac_out_0_en_utc0_complete_8" "0,1" newline bitfld.long 0x10 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_7,Enable Set for level_vpac_out_0_en_utc0_complete_7" "0,1" newline bitfld.long 0x10 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_6,Enable Set for level_vpac_out_0_en_utc0_complete_6" "0,1" newline bitfld.long 0x10 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_5,Enable Set for level_vpac_out_0_en_utc0_complete_5" "0,1" newline bitfld.long 0x10 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_4,Enable Set for level_vpac_out_0_en_utc0_complete_4" "0,1" newline bitfld.long 0x10 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_3,Enable Set for level_vpac_out_0_en_utc0_complete_3" "0,1" newline bitfld.long 0x10 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_2,Enable Set for level_vpac_out_0_en_utc0_complete_2" "0,1" newline bitfld.long 0x10 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_1,Enable Set for level_vpac_out_0_en_utc0_complete_1" "0,1" newline bitfld.long 0x10 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_0,Enable Set for level_vpac_out_0_en_utc0_complete_0" "0,1" line.long 0x14 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_0_5,Enable Register 5" bitfld.long 0x14 31. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_31,Enable Set for level_vpac_out_0_en_utc1_complete_31" "0,1" newline bitfld.long 0x14 30. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_30,Enable Set for level_vpac_out_0_en_utc1_complete_30" "0,1" newline bitfld.long 0x14 29. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_29,Enable Set for level_vpac_out_0_en_utc1_complete_29" "0,1" newline bitfld.long 0x14 28. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_28,Enable Set for level_vpac_out_0_en_utc1_complete_28" "0,1" newline bitfld.long 0x14 27. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_27,Enable Set for level_vpac_out_0_en_utc1_complete_27" "0,1" newline bitfld.long 0x14 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_26,Enable Set for level_vpac_out_0_en_utc1_complete_26" "0,1" newline bitfld.long 0x14 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_25,Enable Set for level_vpac_out_0_en_utc1_complete_25" "0,1" newline bitfld.long 0x14 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_24,Enable Set for level_vpac_out_0_en_utc1_complete_24" "0,1" newline bitfld.long 0x14 23. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_23,Enable Set for level_vpac_out_0_en_utc1_complete_23" "0,1" newline bitfld.long 0x14 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_22,Enable Set for level_vpac_out_0_en_utc1_complete_22" "0,1" newline bitfld.long 0x14 21. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_21,Enable Set for level_vpac_out_0_en_utc1_complete_21" "0,1" newline bitfld.long 0x14 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_20,Enable Set for level_vpac_out_0_en_utc1_complete_20" "0,1" newline bitfld.long 0x14 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_19,Enable Set for level_vpac_out_0_en_utc1_complete_19" "0,1" newline bitfld.long 0x14 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_18,Enable Set for level_vpac_out_0_en_utc1_complete_18" "0,1" newline bitfld.long 0x14 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_17,Enable Set for level_vpac_out_0_en_utc1_complete_17" "0,1" newline bitfld.long 0x14 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_16,Enable Set for level_vpac_out_0_en_utc1_complete_16" "0,1" newline bitfld.long 0x14 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_15,Enable Set for level_vpac_out_0_en_utc1_complete_15" "0,1" newline bitfld.long 0x14 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_14,Enable Set for level_vpac_out_0_en_utc1_complete_14" "0,1" newline bitfld.long 0x14 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_13,Enable Set for level_vpac_out_0_en_utc1_complete_13" "0,1" newline bitfld.long 0x14 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_12,Enable Set for level_vpac_out_0_en_utc1_complete_12" "0,1" newline bitfld.long 0x14 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_11,Enable Set for level_vpac_out_0_en_utc1_complete_11" "0,1" newline bitfld.long 0x14 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_10,Enable Set for level_vpac_out_0_en_utc1_complete_10" "0,1" newline bitfld.long 0x14 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_9,Enable Set for level_vpac_out_0_en_utc1_complete_9" "0,1" newline bitfld.long 0x14 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_8,Enable Set for level_vpac_out_0_en_utc1_complete_8" "0,1" newline bitfld.long 0x14 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_7,Enable Set for level_vpac_out_0_en_utc1_complete_7" "0,1" newline bitfld.long 0x14 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_6,Enable Set for level_vpac_out_0_en_utc1_complete_6" "0,1" newline bitfld.long 0x14 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_5,Enable Set for level_vpac_out_0_en_utc1_complete_5" "0,1" newline bitfld.long 0x14 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_4,Enable Set for level_vpac_out_0_en_utc1_complete_4" "0,1" newline bitfld.long 0x14 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_3,Enable Set for level_vpac_out_0_en_utc1_complete_3" "0,1" newline bitfld.long 0x14 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_2,Enable Set for level_vpac_out_0_en_utc1_complete_2" "0,1" newline bitfld.long 0x14 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_1,Enable Set for level_vpac_out_0_en_utc1_complete_1" "0,1" newline bitfld.long 0x14 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_0,Enable Set for level_vpac_out_0_en_utc1_complete_0" "0,1" line.long 0x18 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_0_6,Enable Register 6" bitfld.long 0x18 31. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_63,Enable Set for level_vpac_out_0_en_utc1_complete_63" "0,1" newline bitfld.long 0x18 30. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_62,Enable Set for level_vpac_out_0_en_utc1_complete_62" "0,1" newline bitfld.long 0x18 29. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_61,Enable Set for level_vpac_out_0_en_utc1_complete_61" "0,1" newline bitfld.long 0x18 28. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_60,Enable Set for level_vpac_out_0_en_utc1_complete_60" "0,1" newline bitfld.long 0x18 27. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_59,Enable Set for level_vpac_out_0_en_utc1_complete_59" "0,1" newline bitfld.long 0x18 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_58,Enable Set for level_vpac_out_0_en_utc1_complete_58" "0,1" newline bitfld.long 0x18 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_57,Enable Set for level_vpac_out_0_en_utc1_complete_57" "0,1" newline bitfld.long 0x18 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_56,Enable Set for level_vpac_out_0_en_utc1_complete_56" "0,1" newline bitfld.long 0x18 23. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_55,Enable Set for level_vpac_out_0_en_utc1_complete_55" "0,1" newline bitfld.long 0x18 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_54,Enable Set for level_vpac_out_0_en_utc1_complete_54" "0,1" newline bitfld.long 0x18 21. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_53,Enable Set for level_vpac_out_0_en_utc1_complete_53" "0,1" newline bitfld.long 0x18 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_52,Enable Set for level_vpac_out_0_en_utc1_complete_52" "0,1" newline bitfld.long 0x18 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_51,Enable Set for level_vpac_out_0_en_utc1_complete_51" "0,1" newline bitfld.long 0x18 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_50,Enable Set for level_vpac_out_0_en_utc1_complete_50" "0,1" newline bitfld.long 0x18 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_49,Enable Set for level_vpac_out_0_en_utc1_complete_49" "0,1" newline bitfld.long 0x18 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_48,Enable Set for level_vpac_out_0_en_utc1_complete_48" "0,1" newline bitfld.long 0x18 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_47,Enable Set for level_vpac_out_0_en_utc1_complete_47" "0,1" newline bitfld.long 0x18 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_46,Enable Set for level_vpac_out_0_en_utc1_complete_46" "0,1" newline bitfld.long 0x18 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_45,Enable Set for level_vpac_out_0_en_utc1_complete_45" "0,1" newline bitfld.long 0x18 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_44,Enable Set for level_vpac_out_0_en_utc1_complete_44" "0,1" newline bitfld.long 0x18 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_43,Enable Set for level_vpac_out_0_en_utc1_complete_43" "0,1" newline bitfld.long 0x18 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_42,Enable Set for level_vpac_out_0_en_utc1_complete_42" "0,1" newline bitfld.long 0x18 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_41,Enable Set for level_vpac_out_0_en_utc1_complete_41" "0,1" newline bitfld.long 0x18 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_40,Enable Set for level_vpac_out_0_en_utc1_complete_40" "0,1" newline bitfld.long 0x18 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_39,Enable Set for level_vpac_out_0_en_utc1_complete_39" "0,1" newline bitfld.long 0x18 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_38,Enable Set for level_vpac_out_0_en_utc1_complete_38" "0,1" newline bitfld.long 0x18 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_37,Enable Set for level_vpac_out_0_en_utc1_complete_37" "0,1" newline bitfld.long 0x18 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_36,Enable Set for level_vpac_out_0_en_utc1_complete_36" "0,1" newline bitfld.long 0x18 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_35,Enable Set for level_vpac_out_0_en_utc1_complete_35" "0,1" newline bitfld.long 0x18 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_34,Enable Set for level_vpac_out_0_en_utc1_complete_34" "0,1" newline bitfld.long 0x18 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_33,Enable Set for level_vpac_out_0_en_utc1_complete_33" "0,1" newline bitfld.long 0x18 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_32,Enable Set for level_vpac_out_0_en_utc1_complete_32" "0,1" line.long 0x1C "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_0_7,Enable Register 7" bitfld.long 0x1C 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_CTM_PULSE,Enable Set for level_vpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0x1C 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_PROT_ERR,Enable Set for level_vpac_out_0_en_utc1_prot_err" "0,1" newline bitfld.long 0x1C 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_PROT_ERR,Enable Set for level_vpac_out_0_en_utc0_prot_err" "0,1" newline bitfld.long 0x1C 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_ERROR,Enable Set for level_vpac_out_0_en_utc1_error" "0,1" newline bitfld.long 0x1C 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_ERROR,Enable Set for level_vpac_out_0_en_utc0_error" "0,1" line.long 0x20 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_1_0,Enable Register 8" bitfld.long 0x20 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_CR_CFG_ERR,Enable Set for level_vpac_out_1_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x20 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for level_vpac_out_1_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x20 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for level_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x20 23. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for level_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x20 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x20 21. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x20 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for level_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x20 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for level_vpac_out_1_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x20 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_EE_CFG_ERR,Enable Set for level_vpac_out_1_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x20 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for level_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x20 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for level_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x20 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCC_CFG_ERR,Enable Set for level_vpac_out_1_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x20 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCFA_CFG_ERR,Enable Set for level_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x20 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_VP_ERR,Enable Set for level_vpac_out_1_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x20 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for level_vpac_out_1_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x20 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for level_vpac_out_1_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x20 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_DONE,Enable Set for level_vpac_out_1_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x20 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_START,Enable Set for level_vpac_out_1_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x20 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_CFG_ERR,Enable Set for level_vpac_out_1_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x20 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for level_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x20 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for level_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x20 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for level_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x20 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for level_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x20 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for level_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x20 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_AF_PULSE,Enable Set for level_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x20 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for level_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x20 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_CFG_ERR,Enable Set for level_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1" line.long 0x24 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_1_1,Enable Register 9" bitfld.long 0x24 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_VBUSM_RD_ERR,Enable Set for level_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x24 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_SL2_WR_ERR,Enable Set for level_vpac_out_1_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x24 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_FR_DONE_EVT,Enable Set for level_vpac_out_1_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x24 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_INT_SZOVF,Enable Set for level_vpac_out_1_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x24 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_IFR_OUTOFBOUND,Enable Set for level_vpac_out_1_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x24 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for level_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x24 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for level_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x24 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x24 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x28 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_1_2,Enable Register 10" bitfld.long 0x28 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_NF_SL2_RD_ERR,Enable Set for level_vpac_out_1_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x28 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_NF_SL2_WR_ERR,Enable Set for level_vpac_out_1_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x28 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_NF_FRAME_DONE,Enable Set for level_vpac_out_1_en_nf_frame_done" "0,1" newline bitfld.long 0x28 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x28 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x28 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for level_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x28 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for level_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x2C "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_1_3,Enable Register 11" bitfld.long 0x2C 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_6,Enable Set for level_vpac_out_1_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x2C 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_5,Enable Set for level_vpac_out_1_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x2C 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_4,Enable Set for level_vpac_out_1_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x2C 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_2,Enable Set for level_vpac_out_1_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x2C 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_vpac_out_1_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x2C 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_1_LEVEL,Enable Set for level_vpac_out_1_en_spare_pend_1_level" "0,1" newline bitfld.long 0x2C 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_1_PULSE,Enable Set for level_vpac_out_1_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x2C 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_0_LEVEL,Enable Set for level_vpac_out_1_en_spare_pend_0_level" "0,1" newline bitfld.long 0x2C 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_0_PULSE,Enable Set for level_vpac_out_1_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x2C 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_DEC_1,Enable Set for level_vpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0x2C 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_DEC_0,Enable Set for level_vpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0x2C 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_6,Enable Set for level_vpac_out_1_en_tdone_6" "0,1" newline bitfld.long 0x2C 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_5,Enable Set for level_vpac_out_1_en_tdone_5" "0,1" newline bitfld.long 0x2C 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_4,Enable Set for level_vpac_out_1_en_tdone_4" "0,1" newline bitfld.long 0x2C 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_2,Enable Set for level_vpac_out_1_en_tdone_2" "0,1" newline bitfld.long 0x2C 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_0,Enable Set for level_vpac_out_1_en_tdone_0" "0,1" newline bitfld.long 0x2C 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_6,Enable Set for level_vpac_out_1_en_pipe_done_6" "0,1" newline bitfld.long 0x2C 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_5,Enable Set for level_vpac_out_1_en_pipe_done_5" "0,1" newline bitfld.long 0x2C 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_4,Enable Set for level_vpac_out_1_en_pipe_done_4" "0,1" newline bitfld.long 0x2C 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_3,Enable Set for level_vpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0x2C 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_2,Enable Set for level_vpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0x2C 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_1,Enable Set for level_vpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0x2C 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_0,Enable Set for level_vpac_out_1_en_pipe_done_0" "0,1" line.long 0x30 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_1_4,Enable Register 12" bitfld.long 0x30 31. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_31,Enable Set for level_vpac_out_1_en_utc0_complete_31" "0,1" newline bitfld.long 0x30 30. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_30,Enable Set for level_vpac_out_1_en_utc0_complete_30" "0,1" newline bitfld.long 0x30 29. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_29,Enable Set for level_vpac_out_1_en_utc0_complete_29" "0,1" newline bitfld.long 0x30 28. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_28,Enable Set for level_vpac_out_1_en_utc0_complete_28" "0,1" newline bitfld.long 0x30 27. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_27,Enable Set for level_vpac_out_1_en_utc0_complete_27" "0,1" newline bitfld.long 0x30 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_26,Enable Set for level_vpac_out_1_en_utc0_complete_26" "0,1" newline bitfld.long 0x30 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_25,Enable Set for level_vpac_out_1_en_utc0_complete_25" "0,1" newline bitfld.long 0x30 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_24,Enable Set for level_vpac_out_1_en_utc0_complete_24" "0,1" newline bitfld.long 0x30 23. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_23,Enable Set for level_vpac_out_1_en_utc0_complete_23" "0,1" newline bitfld.long 0x30 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_22,Enable Set for level_vpac_out_1_en_utc0_complete_22" "0,1" newline bitfld.long 0x30 21. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_21,Enable Set for level_vpac_out_1_en_utc0_complete_21" "0,1" newline bitfld.long 0x30 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_20,Enable Set for level_vpac_out_1_en_utc0_complete_20" "0,1" newline bitfld.long 0x30 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_19,Enable Set for level_vpac_out_1_en_utc0_complete_19" "0,1" newline bitfld.long 0x30 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_18,Enable Set for level_vpac_out_1_en_utc0_complete_18" "0,1" newline bitfld.long 0x30 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_17,Enable Set for level_vpac_out_1_en_utc0_complete_17" "0,1" newline bitfld.long 0x30 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_16,Enable Set for level_vpac_out_1_en_utc0_complete_16" "0,1" newline bitfld.long 0x30 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_15,Enable Set for level_vpac_out_1_en_utc0_complete_15" "0,1" newline bitfld.long 0x30 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_14,Enable Set for level_vpac_out_1_en_utc0_complete_14" "0,1" newline bitfld.long 0x30 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_13,Enable Set for level_vpac_out_1_en_utc0_complete_13" "0,1" newline bitfld.long 0x30 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_12,Enable Set for level_vpac_out_1_en_utc0_complete_12" "0,1" newline bitfld.long 0x30 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_11,Enable Set for level_vpac_out_1_en_utc0_complete_11" "0,1" newline bitfld.long 0x30 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_10,Enable Set for level_vpac_out_1_en_utc0_complete_10" "0,1" newline bitfld.long 0x30 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_9,Enable Set for level_vpac_out_1_en_utc0_complete_9" "0,1" newline bitfld.long 0x30 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_8,Enable Set for level_vpac_out_1_en_utc0_complete_8" "0,1" newline bitfld.long 0x30 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_7,Enable Set for level_vpac_out_1_en_utc0_complete_7" "0,1" newline bitfld.long 0x30 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_6,Enable Set for level_vpac_out_1_en_utc0_complete_6" "0,1" newline bitfld.long 0x30 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_5,Enable Set for level_vpac_out_1_en_utc0_complete_5" "0,1" newline bitfld.long 0x30 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_4,Enable Set for level_vpac_out_1_en_utc0_complete_4" "0,1" newline bitfld.long 0x30 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_3,Enable Set for level_vpac_out_1_en_utc0_complete_3" "0,1" newline bitfld.long 0x30 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_2,Enable Set for level_vpac_out_1_en_utc0_complete_2" "0,1" newline bitfld.long 0x30 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_1,Enable Set for level_vpac_out_1_en_utc0_complete_1" "0,1" newline bitfld.long 0x30 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_0,Enable Set for level_vpac_out_1_en_utc0_complete_0" "0,1" line.long 0x34 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_1_5,Enable Register 13" bitfld.long 0x34 31. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_31,Enable Set for level_vpac_out_1_en_utc1_complete_31" "0,1" newline bitfld.long 0x34 30. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_30,Enable Set for level_vpac_out_1_en_utc1_complete_30" "0,1" newline bitfld.long 0x34 29. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_29,Enable Set for level_vpac_out_1_en_utc1_complete_29" "0,1" newline bitfld.long 0x34 28. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_28,Enable Set for level_vpac_out_1_en_utc1_complete_28" "0,1" newline bitfld.long 0x34 27. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_27,Enable Set for level_vpac_out_1_en_utc1_complete_27" "0,1" newline bitfld.long 0x34 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_26,Enable Set for level_vpac_out_1_en_utc1_complete_26" "0,1" newline bitfld.long 0x34 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_25,Enable Set for level_vpac_out_1_en_utc1_complete_25" "0,1" newline bitfld.long 0x34 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_24,Enable Set for level_vpac_out_1_en_utc1_complete_24" "0,1" newline bitfld.long 0x34 23. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_23,Enable Set for level_vpac_out_1_en_utc1_complete_23" "0,1" newline bitfld.long 0x34 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_22,Enable Set for level_vpac_out_1_en_utc1_complete_22" "0,1" newline bitfld.long 0x34 21. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_21,Enable Set for level_vpac_out_1_en_utc1_complete_21" "0,1" newline bitfld.long 0x34 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_20,Enable Set for level_vpac_out_1_en_utc1_complete_20" "0,1" newline bitfld.long 0x34 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_19,Enable Set for level_vpac_out_1_en_utc1_complete_19" "0,1" newline bitfld.long 0x34 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_18,Enable Set for level_vpac_out_1_en_utc1_complete_18" "0,1" newline bitfld.long 0x34 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_17,Enable Set for level_vpac_out_1_en_utc1_complete_17" "0,1" newline bitfld.long 0x34 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_16,Enable Set for level_vpac_out_1_en_utc1_complete_16" "0,1" newline bitfld.long 0x34 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_15,Enable Set for level_vpac_out_1_en_utc1_complete_15" "0,1" newline bitfld.long 0x34 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_14,Enable Set for level_vpac_out_1_en_utc1_complete_14" "0,1" newline bitfld.long 0x34 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_13,Enable Set for level_vpac_out_1_en_utc1_complete_13" "0,1" newline bitfld.long 0x34 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_12,Enable Set for level_vpac_out_1_en_utc1_complete_12" "0,1" newline bitfld.long 0x34 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_11,Enable Set for level_vpac_out_1_en_utc1_complete_11" "0,1" newline bitfld.long 0x34 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_10,Enable Set for level_vpac_out_1_en_utc1_complete_10" "0,1" newline bitfld.long 0x34 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_9,Enable Set for level_vpac_out_1_en_utc1_complete_9" "0,1" newline bitfld.long 0x34 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_8,Enable Set for level_vpac_out_1_en_utc1_complete_8" "0,1" newline bitfld.long 0x34 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_7,Enable Set for level_vpac_out_1_en_utc1_complete_7" "0,1" newline bitfld.long 0x34 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_6,Enable Set for level_vpac_out_1_en_utc1_complete_6" "0,1" newline bitfld.long 0x34 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_5,Enable Set for level_vpac_out_1_en_utc1_complete_5" "0,1" newline bitfld.long 0x34 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_4,Enable Set for level_vpac_out_1_en_utc1_complete_4" "0,1" newline bitfld.long 0x34 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_3,Enable Set for level_vpac_out_1_en_utc1_complete_3" "0,1" newline bitfld.long 0x34 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_2,Enable Set for level_vpac_out_1_en_utc1_complete_2" "0,1" newline bitfld.long 0x34 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_1,Enable Set for level_vpac_out_1_en_utc1_complete_1" "0,1" newline bitfld.long 0x34 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_0,Enable Set for level_vpac_out_1_en_utc1_complete_0" "0,1" line.long 0x38 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_1_6,Enable Register 14" bitfld.long 0x38 31. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_63,Enable Set for level_vpac_out_1_en_utc1_complete_63" "0,1" newline bitfld.long 0x38 30. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_62,Enable Set for level_vpac_out_1_en_utc1_complete_62" "0,1" newline bitfld.long 0x38 29. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_61,Enable Set for level_vpac_out_1_en_utc1_complete_61" "0,1" newline bitfld.long 0x38 28. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_60,Enable Set for level_vpac_out_1_en_utc1_complete_60" "0,1" newline bitfld.long 0x38 27. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_59,Enable Set for level_vpac_out_1_en_utc1_complete_59" "0,1" newline bitfld.long 0x38 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_58,Enable Set for level_vpac_out_1_en_utc1_complete_58" "0,1" newline bitfld.long 0x38 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_57,Enable Set for level_vpac_out_1_en_utc1_complete_57" "0,1" newline bitfld.long 0x38 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_56,Enable Set for level_vpac_out_1_en_utc1_complete_56" "0,1" newline bitfld.long 0x38 23. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_55,Enable Set for level_vpac_out_1_en_utc1_complete_55" "0,1" newline bitfld.long 0x38 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_54,Enable Set for level_vpac_out_1_en_utc1_complete_54" "0,1" newline bitfld.long 0x38 21. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_53,Enable Set for level_vpac_out_1_en_utc1_complete_53" "0,1" newline bitfld.long 0x38 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_52,Enable Set for level_vpac_out_1_en_utc1_complete_52" "0,1" newline bitfld.long 0x38 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_51,Enable Set for level_vpac_out_1_en_utc1_complete_51" "0,1" newline bitfld.long 0x38 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_50,Enable Set for level_vpac_out_1_en_utc1_complete_50" "0,1" newline bitfld.long 0x38 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_49,Enable Set for level_vpac_out_1_en_utc1_complete_49" "0,1" newline bitfld.long 0x38 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_48,Enable Set for level_vpac_out_1_en_utc1_complete_48" "0,1" newline bitfld.long 0x38 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_47,Enable Set for level_vpac_out_1_en_utc1_complete_47" "0,1" newline bitfld.long 0x38 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_46,Enable Set for level_vpac_out_1_en_utc1_complete_46" "0,1" newline bitfld.long 0x38 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_45,Enable Set for level_vpac_out_1_en_utc1_complete_45" "0,1" newline bitfld.long 0x38 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_44,Enable Set for level_vpac_out_1_en_utc1_complete_44" "0,1" newline bitfld.long 0x38 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_43,Enable Set for level_vpac_out_1_en_utc1_complete_43" "0,1" newline bitfld.long 0x38 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_42,Enable Set for level_vpac_out_1_en_utc1_complete_42" "0,1" newline bitfld.long 0x38 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_41,Enable Set for level_vpac_out_1_en_utc1_complete_41" "0,1" newline bitfld.long 0x38 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_40,Enable Set for level_vpac_out_1_en_utc1_complete_40" "0,1" newline bitfld.long 0x38 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_39,Enable Set for level_vpac_out_1_en_utc1_complete_39" "0,1" newline bitfld.long 0x38 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_38,Enable Set for level_vpac_out_1_en_utc1_complete_38" "0,1" newline bitfld.long 0x38 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_37,Enable Set for level_vpac_out_1_en_utc1_complete_37" "0,1" newline bitfld.long 0x38 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_36,Enable Set for level_vpac_out_1_en_utc1_complete_36" "0,1" newline bitfld.long 0x38 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_35,Enable Set for level_vpac_out_1_en_utc1_complete_35" "0,1" newline bitfld.long 0x38 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_34,Enable Set for level_vpac_out_1_en_utc1_complete_34" "0,1" newline bitfld.long 0x38 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_33,Enable Set for level_vpac_out_1_en_utc1_complete_33" "0,1" newline bitfld.long 0x38 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_32,Enable Set for level_vpac_out_1_en_utc1_complete_32" "0,1" line.long 0x3C "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_1_7,Enable Register 15" bitfld.long 0x3C 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_CTM_PULSE,Enable Set for level_vpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0x3C 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_PROT_ERR,Enable Set for level_vpac_out_1_en_utc1_prot_err" "0,1" newline bitfld.long 0x3C 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_PROT_ERR,Enable Set for level_vpac_out_1_en_utc0_prot_err" "0,1" newline bitfld.long 0x3C 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_ERROR,Enable Set for level_vpac_out_1_en_utc1_error" "0,1" newline bitfld.long 0x3C 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_ERROR,Enable Set for level_vpac_out_1_en_utc0_error" "0,1" line.long 0x40 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_2_0,Enable Register 16" bitfld.long 0x40 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_CR_CFG_ERR,Enable Set for level_vpac_out_2_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x40 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for level_vpac_out_2_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x40 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for level_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x40 23. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for level_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x40 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x40 21. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x40 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for level_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x40 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for level_vpac_out_2_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x40 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_EE_CFG_ERR,Enable Set for level_vpac_out_2_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x40 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for level_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x40 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for level_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x40 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCC_CFG_ERR,Enable Set for level_vpac_out_2_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x40 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCFA_CFG_ERR,Enable Set for level_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x40 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_VP_ERR,Enable Set for level_vpac_out_2_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x40 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for level_vpac_out_2_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x40 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for level_vpac_out_2_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x40 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_DONE,Enable Set for level_vpac_out_2_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x40 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_START,Enable Set for level_vpac_out_2_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x40 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_CFG_ERR,Enable Set for level_vpac_out_2_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x40 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for level_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x40 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for level_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x40 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for level_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x40 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for level_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x40 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for level_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x40 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_AF_PULSE,Enable Set for level_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x40 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for level_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x40 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_CFG_ERR,Enable Set for level_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1" line.long 0x44 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_2_1,Enable Register 17" bitfld.long 0x44 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_VBUSM_RD_ERR,Enable Set for level_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x44 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_SL2_WR_ERR,Enable Set for level_vpac_out_2_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x44 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_FR_DONE_EVT,Enable Set for level_vpac_out_2_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x44 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_INT_SZOVF,Enable Set for level_vpac_out_2_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x44 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_IFR_OUTOFBOUND,Enable Set for level_vpac_out_2_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x44 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for level_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x44 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for level_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x44 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x44 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x48 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_2_2,Enable Register 18" bitfld.long 0x48 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_NF_SL2_RD_ERR,Enable Set for level_vpac_out_2_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x48 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_NF_SL2_WR_ERR,Enable Set for level_vpac_out_2_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x48 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_NF_FRAME_DONE,Enable Set for level_vpac_out_2_en_nf_frame_done" "0,1" newline bitfld.long 0x48 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x48 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x48 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for level_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x48 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for level_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x4C "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_2_3,Enable Register 19" bitfld.long 0x4C 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_6,Enable Set for level_vpac_out_2_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x4C 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_5,Enable Set for level_vpac_out_2_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x4C 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_4,Enable Set for level_vpac_out_2_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x4C 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_2,Enable Set for level_vpac_out_2_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x4C 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_vpac_out_2_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x4C 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_1_LEVEL,Enable Set for level_vpac_out_2_en_spare_pend_1_level" "0,1" newline bitfld.long 0x4C 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_1_PULSE,Enable Set for level_vpac_out_2_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x4C 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_0_LEVEL,Enable Set for level_vpac_out_2_en_spare_pend_0_level" "0,1" newline bitfld.long 0x4C 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_0_PULSE,Enable Set for level_vpac_out_2_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x4C 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_DEC_1,Enable Set for level_vpac_out_2_en_spare_dec_1" "0,1" newline bitfld.long 0x4C 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_DEC_0,Enable Set for level_vpac_out_2_en_spare_dec_0" "0,1" newline bitfld.long 0x4C 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_6,Enable Set for level_vpac_out_2_en_tdone_6" "0,1" newline bitfld.long 0x4C 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_5,Enable Set for level_vpac_out_2_en_tdone_5" "0,1" newline bitfld.long 0x4C 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_4,Enable Set for level_vpac_out_2_en_tdone_4" "0,1" newline bitfld.long 0x4C 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_2,Enable Set for level_vpac_out_2_en_tdone_2" "0,1" newline bitfld.long 0x4C 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_0,Enable Set for level_vpac_out_2_en_tdone_0" "0,1" newline bitfld.long 0x4C 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_6,Enable Set for level_vpac_out_2_en_pipe_done_6" "0,1" newline bitfld.long 0x4C 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_5,Enable Set for level_vpac_out_2_en_pipe_done_5" "0,1" newline bitfld.long 0x4C 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_4,Enable Set for level_vpac_out_2_en_pipe_done_4" "0,1" newline bitfld.long 0x4C 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_3,Enable Set for level_vpac_out_2_en_pipe_done_3" "0,1" newline bitfld.long 0x4C 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_2,Enable Set for level_vpac_out_2_en_pipe_done_2" "0,1" newline bitfld.long 0x4C 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_1,Enable Set for level_vpac_out_2_en_pipe_done_1" "0,1" newline bitfld.long 0x4C 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_0,Enable Set for level_vpac_out_2_en_pipe_done_0" "0,1" line.long 0x50 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_2_4,Enable Register 20" bitfld.long 0x50 31. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_31,Enable Set for level_vpac_out_2_en_utc0_complete_31" "0,1" newline bitfld.long 0x50 30. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_30,Enable Set for level_vpac_out_2_en_utc0_complete_30" "0,1" newline bitfld.long 0x50 29. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_29,Enable Set for level_vpac_out_2_en_utc0_complete_29" "0,1" newline bitfld.long 0x50 28. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_28,Enable Set for level_vpac_out_2_en_utc0_complete_28" "0,1" newline bitfld.long 0x50 27. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_27,Enable Set for level_vpac_out_2_en_utc0_complete_27" "0,1" newline bitfld.long 0x50 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_26,Enable Set for level_vpac_out_2_en_utc0_complete_26" "0,1" newline bitfld.long 0x50 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_25,Enable Set for level_vpac_out_2_en_utc0_complete_25" "0,1" newline bitfld.long 0x50 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_24,Enable Set for level_vpac_out_2_en_utc0_complete_24" "0,1" newline bitfld.long 0x50 23. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_23,Enable Set for level_vpac_out_2_en_utc0_complete_23" "0,1" newline bitfld.long 0x50 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_22,Enable Set for level_vpac_out_2_en_utc0_complete_22" "0,1" newline bitfld.long 0x50 21. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_21,Enable Set for level_vpac_out_2_en_utc0_complete_21" "0,1" newline bitfld.long 0x50 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_20,Enable Set for level_vpac_out_2_en_utc0_complete_20" "0,1" newline bitfld.long 0x50 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_19,Enable Set for level_vpac_out_2_en_utc0_complete_19" "0,1" newline bitfld.long 0x50 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_18,Enable Set for level_vpac_out_2_en_utc0_complete_18" "0,1" newline bitfld.long 0x50 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_17,Enable Set for level_vpac_out_2_en_utc0_complete_17" "0,1" newline bitfld.long 0x50 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_16,Enable Set for level_vpac_out_2_en_utc0_complete_16" "0,1" newline bitfld.long 0x50 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_15,Enable Set for level_vpac_out_2_en_utc0_complete_15" "0,1" newline bitfld.long 0x50 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_14,Enable Set for level_vpac_out_2_en_utc0_complete_14" "0,1" newline bitfld.long 0x50 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_13,Enable Set for level_vpac_out_2_en_utc0_complete_13" "0,1" newline bitfld.long 0x50 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_12,Enable Set for level_vpac_out_2_en_utc0_complete_12" "0,1" newline bitfld.long 0x50 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_11,Enable Set for level_vpac_out_2_en_utc0_complete_11" "0,1" newline bitfld.long 0x50 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_10,Enable Set for level_vpac_out_2_en_utc0_complete_10" "0,1" newline bitfld.long 0x50 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_9,Enable Set for level_vpac_out_2_en_utc0_complete_9" "0,1" newline bitfld.long 0x50 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_8,Enable Set for level_vpac_out_2_en_utc0_complete_8" "0,1" newline bitfld.long 0x50 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_7,Enable Set for level_vpac_out_2_en_utc0_complete_7" "0,1" newline bitfld.long 0x50 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_6,Enable Set for level_vpac_out_2_en_utc0_complete_6" "0,1" newline bitfld.long 0x50 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_5,Enable Set for level_vpac_out_2_en_utc0_complete_5" "0,1" newline bitfld.long 0x50 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_4,Enable Set for level_vpac_out_2_en_utc0_complete_4" "0,1" newline bitfld.long 0x50 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_3,Enable Set for level_vpac_out_2_en_utc0_complete_3" "0,1" newline bitfld.long 0x50 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_2,Enable Set for level_vpac_out_2_en_utc0_complete_2" "0,1" newline bitfld.long 0x50 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_1,Enable Set for level_vpac_out_2_en_utc0_complete_1" "0,1" newline bitfld.long 0x50 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_0,Enable Set for level_vpac_out_2_en_utc0_complete_0" "0,1" line.long 0x54 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_2_5,Enable Register 21" bitfld.long 0x54 31. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_31,Enable Set for level_vpac_out_2_en_utc1_complete_31" "0,1" newline bitfld.long 0x54 30. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_30,Enable Set for level_vpac_out_2_en_utc1_complete_30" "0,1" newline bitfld.long 0x54 29. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_29,Enable Set for level_vpac_out_2_en_utc1_complete_29" "0,1" newline bitfld.long 0x54 28. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_28,Enable Set for level_vpac_out_2_en_utc1_complete_28" "0,1" newline bitfld.long 0x54 27. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_27,Enable Set for level_vpac_out_2_en_utc1_complete_27" "0,1" newline bitfld.long 0x54 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_26,Enable Set for level_vpac_out_2_en_utc1_complete_26" "0,1" newline bitfld.long 0x54 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_25,Enable Set for level_vpac_out_2_en_utc1_complete_25" "0,1" newline bitfld.long 0x54 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_24,Enable Set for level_vpac_out_2_en_utc1_complete_24" "0,1" newline bitfld.long 0x54 23. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_23,Enable Set for level_vpac_out_2_en_utc1_complete_23" "0,1" newline bitfld.long 0x54 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_22,Enable Set for level_vpac_out_2_en_utc1_complete_22" "0,1" newline bitfld.long 0x54 21. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_21,Enable Set for level_vpac_out_2_en_utc1_complete_21" "0,1" newline bitfld.long 0x54 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_20,Enable Set for level_vpac_out_2_en_utc1_complete_20" "0,1" newline bitfld.long 0x54 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_19,Enable Set for level_vpac_out_2_en_utc1_complete_19" "0,1" newline bitfld.long 0x54 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_18,Enable Set for level_vpac_out_2_en_utc1_complete_18" "0,1" newline bitfld.long 0x54 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_17,Enable Set for level_vpac_out_2_en_utc1_complete_17" "0,1" newline bitfld.long 0x54 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_16,Enable Set for level_vpac_out_2_en_utc1_complete_16" "0,1" newline bitfld.long 0x54 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_15,Enable Set for level_vpac_out_2_en_utc1_complete_15" "0,1" newline bitfld.long 0x54 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_14,Enable Set for level_vpac_out_2_en_utc1_complete_14" "0,1" newline bitfld.long 0x54 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_13,Enable Set for level_vpac_out_2_en_utc1_complete_13" "0,1" newline bitfld.long 0x54 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_12,Enable Set for level_vpac_out_2_en_utc1_complete_12" "0,1" newline bitfld.long 0x54 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_11,Enable Set for level_vpac_out_2_en_utc1_complete_11" "0,1" newline bitfld.long 0x54 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_10,Enable Set for level_vpac_out_2_en_utc1_complete_10" "0,1" newline bitfld.long 0x54 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_9,Enable Set for level_vpac_out_2_en_utc1_complete_9" "0,1" newline bitfld.long 0x54 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_8,Enable Set for level_vpac_out_2_en_utc1_complete_8" "0,1" newline bitfld.long 0x54 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_7,Enable Set for level_vpac_out_2_en_utc1_complete_7" "0,1" newline bitfld.long 0x54 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_6,Enable Set for level_vpac_out_2_en_utc1_complete_6" "0,1" newline bitfld.long 0x54 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_5,Enable Set for level_vpac_out_2_en_utc1_complete_5" "0,1" newline bitfld.long 0x54 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_4,Enable Set for level_vpac_out_2_en_utc1_complete_4" "0,1" newline bitfld.long 0x54 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_3,Enable Set for level_vpac_out_2_en_utc1_complete_3" "0,1" newline bitfld.long 0x54 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_2,Enable Set for level_vpac_out_2_en_utc1_complete_2" "0,1" newline bitfld.long 0x54 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_1,Enable Set for level_vpac_out_2_en_utc1_complete_1" "0,1" newline bitfld.long 0x54 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_0,Enable Set for level_vpac_out_2_en_utc1_complete_0" "0,1" line.long 0x58 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_2_6,Enable Register 22" bitfld.long 0x58 31. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_63,Enable Set for level_vpac_out_2_en_utc1_complete_63" "0,1" newline bitfld.long 0x58 30. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_62,Enable Set for level_vpac_out_2_en_utc1_complete_62" "0,1" newline bitfld.long 0x58 29. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_61,Enable Set for level_vpac_out_2_en_utc1_complete_61" "0,1" newline bitfld.long 0x58 28. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_60,Enable Set for level_vpac_out_2_en_utc1_complete_60" "0,1" newline bitfld.long 0x58 27. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_59,Enable Set for level_vpac_out_2_en_utc1_complete_59" "0,1" newline bitfld.long 0x58 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_58,Enable Set for level_vpac_out_2_en_utc1_complete_58" "0,1" newline bitfld.long 0x58 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_57,Enable Set for level_vpac_out_2_en_utc1_complete_57" "0,1" newline bitfld.long 0x58 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_56,Enable Set for level_vpac_out_2_en_utc1_complete_56" "0,1" newline bitfld.long 0x58 23. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_55,Enable Set for level_vpac_out_2_en_utc1_complete_55" "0,1" newline bitfld.long 0x58 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_54,Enable Set for level_vpac_out_2_en_utc1_complete_54" "0,1" newline bitfld.long 0x58 21. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_53,Enable Set for level_vpac_out_2_en_utc1_complete_53" "0,1" newline bitfld.long 0x58 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_52,Enable Set for level_vpac_out_2_en_utc1_complete_52" "0,1" newline bitfld.long 0x58 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_51,Enable Set for level_vpac_out_2_en_utc1_complete_51" "0,1" newline bitfld.long 0x58 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_50,Enable Set for level_vpac_out_2_en_utc1_complete_50" "0,1" newline bitfld.long 0x58 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_49,Enable Set for level_vpac_out_2_en_utc1_complete_49" "0,1" newline bitfld.long 0x58 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_48,Enable Set for level_vpac_out_2_en_utc1_complete_48" "0,1" newline bitfld.long 0x58 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_47,Enable Set for level_vpac_out_2_en_utc1_complete_47" "0,1" newline bitfld.long 0x58 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_46,Enable Set for level_vpac_out_2_en_utc1_complete_46" "0,1" newline bitfld.long 0x58 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_45,Enable Set for level_vpac_out_2_en_utc1_complete_45" "0,1" newline bitfld.long 0x58 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_44,Enable Set for level_vpac_out_2_en_utc1_complete_44" "0,1" newline bitfld.long 0x58 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_43,Enable Set for level_vpac_out_2_en_utc1_complete_43" "0,1" newline bitfld.long 0x58 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_42,Enable Set for level_vpac_out_2_en_utc1_complete_42" "0,1" newline bitfld.long 0x58 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_41,Enable Set for level_vpac_out_2_en_utc1_complete_41" "0,1" newline bitfld.long 0x58 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_40,Enable Set for level_vpac_out_2_en_utc1_complete_40" "0,1" newline bitfld.long 0x58 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_39,Enable Set for level_vpac_out_2_en_utc1_complete_39" "0,1" newline bitfld.long 0x58 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_38,Enable Set for level_vpac_out_2_en_utc1_complete_38" "0,1" newline bitfld.long 0x58 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_37,Enable Set for level_vpac_out_2_en_utc1_complete_37" "0,1" newline bitfld.long 0x58 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_36,Enable Set for level_vpac_out_2_en_utc1_complete_36" "0,1" newline bitfld.long 0x58 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_35,Enable Set for level_vpac_out_2_en_utc1_complete_35" "0,1" newline bitfld.long 0x58 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_34,Enable Set for level_vpac_out_2_en_utc1_complete_34" "0,1" newline bitfld.long 0x58 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_33,Enable Set for level_vpac_out_2_en_utc1_complete_33" "0,1" newline bitfld.long 0x58 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_32,Enable Set for level_vpac_out_2_en_utc1_complete_32" "0,1" line.long 0x5C "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_2_7,Enable Register 23" bitfld.long 0x5C 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_CTM_PULSE,Enable Set for level_vpac_out_2_en_ctm_pulse" "0,1" newline bitfld.long 0x5C 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_PROT_ERR,Enable Set for level_vpac_out_2_en_utc1_prot_err" "0,1" newline bitfld.long 0x5C 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_PROT_ERR,Enable Set for level_vpac_out_2_en_utc0_prot_err" "0,1" newline bitfld.long 0x5C 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_ERROR,Enable Set for level_vpac_out_2_en_utc1_error" "0,1" newline bitfld.long 0x5C 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_ERROR,Enable Set for level_vpac_out_2_en_utc0_error" "0,1" line.long 0x60 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_3_0,Enable Register 24" bitfld.long 0x60 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_CR_CFG_ERR,Enable Set for level_vpac_out_3_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x60 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for level_vpac_out_3_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x60 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for level_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x60 23. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for level_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x60 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x60 21. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x60 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for level_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x60 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for level_vpac_out_3_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x60 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_EE_CFG_ERR,Enable Set for level_vpac_out_3_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x60 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for level_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x60 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for level_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x60 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCC_CFG_ERR,Enable Set for level_vpac_out_3_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x60 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCFA_CFG_ERR,Enable Set for level_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x60 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_VP_ERR,Enable Set for level_vpac_out_3_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x60 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for level_vpac_out_3_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x60 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for level_vpac_out_3_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x60 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_DONE,Enable Set for level_vpac_out_3_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x60 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_START,Enable Set for level_vpac_out_3_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x60 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_CFG_ERR,Enable Set for level_vpac_out_3_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x60 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for level_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x60 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for level_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x60 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for level_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x60 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for level_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x60 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for level_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x60 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_AF_PULSE,Enable Set for level_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x60 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for level_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x60 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_CFG_ERR,Enable Set for level_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1" line.long 0x64 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_3_1,Enable Register 25" bitfld.long 0x64 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_VBUSM_RD_ERR,Enable Set for level_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x64 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_SL2_WR_ERR,Enable Set for level_vpac_out_3_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x64 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_FR_DONE_EVT,Enable Set for level_vpac_out_3_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x64 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_INT_SZOVF,Enable Set for level_vpac_out_3_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x64 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_IFR_OUTOFBOUND,Enable Set for level_vpac_out_3_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x64 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for level_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x64 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for level_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x64 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x64 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x68 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_3_2,Enable Register 26" bitfld.long 0x68 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_NF_SL2_RD_ERR,Enable Set for level_vpac_out_3_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x68 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_NF_SL2_WR_ERR,Enable Set for level_vpac_out_3_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x68 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_NF_FRAME_DONE,Enable Set for level_vpac_out_3_en_nf_frame_done" "0,1" newline bitfld.long 0x68 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x68 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x68 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for level_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x68 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for level_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x6C "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_3_3,Enable Register 27" bitfld.long 0x6C 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_6,Enable Set for level_vpac_out_3_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x6C 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_5,Enable Set for level_vpac_out_3_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x6C 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_4,Enable Set for level_vpac_out_3_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x6C 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_2,Enable Set for level_vpac_out_3_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x6C 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_vpac_out_3_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x6C 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_1_LEVEL,Enable Set for level_vpac_out_3_en_spare_pend_1_level" "0,1" newline bitfld.long 0x6C 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_1_PULSE,Enable Set for level_vpac_out_3_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x6C 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_0_LEVEL,Enable Set for level_vpac_out_3_en_spare_pend_0_level" "0,1" newline bitfld.long 0x6C 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_0_PULSE,Enable Set for level_vpac_out_3_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x6C 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_DEC_1,Enable Set for level_vpac_out_3_en_spare_dec_1" "0,1" newline bitfld.long 0x6C 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_DEC_0,Enable Set for level_vpac_out_3_en_spare_dec_0" "0,1" newline bitfld.long 0x6C 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_6,Enable Set for level_vpac_out_3_en_tdone_6" "0,1" newline bitfld.long 0x6C 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_5,Enable Set for level_vpac_out_3_en_tdone_5" "0,1" newline bitfld.long 0x6C 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_4,Enable Set for level_vpac_out_3_en_tdone_4" "0,1" newline bitfld.long 0x6C 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_2,Enable Set for level_vpac_out_3_en_tdone_2" "0,1" newline bitfld.long 0x6C 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_0,Enable Set for level_vpac_out_3_en_tdone_0" "0,1" newline bitfld.long 0x6C 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_6,Enable Set for level_vpac_out_3_en_pipe_done_6" "0,1" newline bitfld.long 0x6C 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_5,Enable Set for level_vpac_out_3_en_pipe_done_5" "0,1" newline bitfld.long 0x6C 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_4,Enable Set for level_vpac_out_3_en_pipe_done_4" "0,1" newline bitfld.long 0x6C 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_3,Enable Set for level_vpac_out_3_en_pipe_done_3" "0,1" newline bitfld.long 0x6C 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_2,Enable Set for level_vpac_out_3_en_pipe_done_2" "0,1" newline bitfld.long 0x6C 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_1,Enable Set for level_vpac_out_3_en_pipe_done_1" "0,1" newline bitfld.long 0x6C 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_0,Enable Set for level_vpac_out_3_en_pipe_done_0" "0,1" line.long 0x70 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_3_4,Enable Register 28" bitfld.long 0x70 31. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_31,Enable Set for level_vpac_out_3_en_utc0_complete_31" "0,1" newline bitfld.long 0x70 30. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_30,Enable Set for level_vpac_out_3_en_utc0_complete_30" "0,1" newline bitfld.long 0x70 29. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_29,Enable Set for level_vpac_out_3_en_utc0_complete_29" "0,1" newline bitfld.long 0x70 28. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_28,Enable Set for level_vpac_out_3_en_utc0_complete_28" "0,1" newline bitfld.long 0x70 27. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_27,Enable Set for level_vpac_out_3_en_utc0_complete_27" "0,1" newline bitfld.long 0x70 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_26,Enable Set for level_vpac_out_3_en_utc0_complete_26" "0,1" newline bitfld.long 0x70 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_25,Enable Set for level_vpac_out_3_en_utc0_complete_25" "0,1" newline bitfld.long 0x70 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_24,Enable Set for level_vpac_out_3_en_utc0_complete_24" "0,1" newline bitfld.long 0x70 23. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_23,Enable Set for level_vpac_out_3_en_utc0_complete_23" "0,1" newline bitfld.long 0x70 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_22,Enable Set for level_vpac_out_3_en_utc0_complete_22" "0,1" newline bitfld.long 0x70 21. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_21,Enable Set for level_vpac_out_3_en_utc0_complete_21" "0,1" newline bitfld.long 0x70 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_20,Enable Set for level_vpac_out_3_en_utc0_complete_20" "0,1" newline bitfld.long 0x70 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_19,Enable Set for level_vpac_out_3_en_utc0_complete_19" "0,1" newline bitfld.long 0x70 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_18,Enable Set for level_vpac_out_3_en_utc0_complete_18" "0,1" newline bitfld.long 0x70 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_17,Enable Set for level_vpac_out_3_en_utc0_complete_17" "0,1" newline bitfld.long 0x70 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_16,Enable Set for level_vpac_out_3_en_utc0_complete_16" "0,1" newline bitfld.long 0x70 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_15,Enable Set for level_vpac_out_3_en_utc0_complete_15" "0,1" newline bitfld.long 0x70 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_14,Enable Set for level_vpac_out_3_en_utc0_complete_14" "0,1" newline bitfld.long 0x70 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_13,Enable Set for level_vpac_out_3_en_utc0_complete_13" "0,1" newline bitfld.long 0x70 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_12,Enable Set for level_vpac_out_3_en_utc0_complete_12" "0,1" newline bitfld.long 0x70 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_11,Enable Set for level_vpac_out_3_en_utc0_complete_11" "0,1" newline bitfld.long 0x70 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_10,Enable Set for level_vpac_out_3_en_utc0_complete_10" "0,1" newline bitfld.long 0x70 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_9,Enable Set for level_vpac_out_3_en_utc0_complete_9" "0,1" newline bitfld.long 0x70 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_8,Enable Set for level_vpac_out_3_en_utc0_complete_8" "0,1" newline bitfld.long 0x70 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_7,Enable Set for level_vpac_out_3_en_utc0_complete_7" "0,1" newline bitfld.long 0x70 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_6,Enable Set for level_vpac_out_3_en_utc0_complete_6" "0,1" newline bitfld.long 0x70 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_5,Enable Set for level_vpac_out_3_en_utc0_complete_5" "0,1" newline bitfld.long 0x70 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_4,Enable Set for level_vpac_out_3_en_utc0_complete_4" "0,1" newline bitfld.long 0x70 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_3,Enable Set for level_vpac_out_3_en_utc0_complete_3" "0,1" newline bitfld.long 0x70 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_2,Enable Set for level_vpac_out_3_en_utc0_complete_2" "0,1" newline bitfld.long 0x70 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_1,Enable Set for level_vpac_out_3_en_utc0_complete_1" "0,1" newline bitfld.long 0x70 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_0,Enable Set for level_vpac_out_3_en_utc0_complete_0" "0,1" line.long 0x74 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_3_5,Enable Register 29" bitfld.long 0x74 31. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_31,Enable Set for level_vpac_out_3_en_utc1_complete_31" "0,1" newline bitfld.long 0x74 30. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_30,Enable Set for level_vpac_out_3_en_utc1_complete_30" "0,1" newline bitfld.long 0x74 29. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_29,Enable Set for level_vpac_out_3_en_utc1_complete_29" "0,1" newline bitfld.long 0x74 28. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_28,Enable Set for level_vpac_out_3_en_utc1_complete_28" "0,1" newline bitfld.long 0x74 27. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_27,Enable Set for level_vpac_out_3_en_utc1_complete_27" "0,1" newline bitfld.long 0x74 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_26,Enable Set for level_vpac_out_3_en_utc1_complete_26" "0,1" newline bitfld.long 0x74 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_25,Enable Set for level_vpac_out_3_en_utc1_complete_25" "0,1" newline bitfld.long 0x74 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_24,Enable Set for level_vpac_out_3_en_utc1_complete_24" "0,1" newline bitfld.long 0x74 23. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_23,Enable Set for level_vpac_out_3_en_utc1_complete_23" "0,1" newline bitfld.long 0x74 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_22,Enable Set for level_vpac_out_3_en_utc1_complete_22" "0,1" newline bitfld.long 0x74 21. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_21,Enable Set for level_vpac_out_3_en_utc1_complete_21" "0,1" newline bitfld.long 0x74 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_20,Enable Set for level_vpac_out_3_en_utc1_complete_20" "0,1" newline bitfld.long 0x74 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_19,Enable Set for level_vpac_out_3_en_utc1_complete_19" "0,1" newline bitfld.long 0x74 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_18,Enable Set for level_vpac_out_3_en_utc1_complete_18" "0,1" newline bitfld.long 0x74 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_17,Enable Set for level_vpac_out_3_en_utc1_complete_17" "0,1" newline bitfld.long 0x74 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_16,Enable Set for level_vpac_out_3_en_utc1_complete_16" "0,1" newline bitfld.long 0x74 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_15,Enable Set for level_vpac_out_3_en_utc1_complete_15" "0,1" newline bitfld.long 0x74 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_14,Enable Set for level_vpac_out_3_en_utc1_complete_14" "0,1" newline bitfld.long 0x74 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_13,Enable Set for level_vpac_out_3_en_utc1_complete_13" "0,1" newline bitfld.long 0x74 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_12,Enable Set for level_vpac_out_3_en_utc1_complete_12" "0,1" newline bitfld.long 0x74 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_11,Enable Set for level_vpac_out_3_en_utc1_complete_11" "0,1" newline bitfld.long 0x74 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_10,Enable Set for level_vpac_out_3_en_utc1_complete_10" "0,1" newline bitfld.long 0x74 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_9,Enable Set for level_vpac_out_3_en_utc1_complete_9" "0,1" newline bitfld.long 0x74 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_8,Enable Set for level_vpac_out_3_en_utc1_complete_8" "0,1" newline bitfld.long 0x74 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_7,Enable Set for level_vpac_out_3_en_utc1_complete_7" "0,1" newline bitfld.long 0x74 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_6,Enable Set for level_vpac_out_3_en_utc1_complete_6" "0,1" newline bitfld.long 0x74 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_5,Enable Set for level_vpac_out_3_en_utc1_complete_5" "0,1" newline bitfld.long 0x74 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_4,Enable Set for level_vpac_out_3_en_utc1_complete_4" "0,1" newline bitfld.long 0x74 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_3,Enable Set for level_vpac_out_3_en_utc1_complete_3" "0,1" newline bitfld.long 0x74 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_2,Enable Set for level_vpac_out_3_en_utc1_complete_2" "0,1" newline bitfld.long 0x74 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_1,Enable Set for level_vpac_out_3_en_utc1_complete_1" "0,1" newline bitfld.long 0x74 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_0,Enable Set for level_vpac_out_3_en_utc1_complete_0" "0,1" line.long 0x78 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_3_6,Enable Register 30" bitfld.long 0x78 31. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_63,Enable Set for level_vpac_out_3_en_utc1_complete_63" "0,1" newline bitfld.long 0x78 30. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_62,Enable Set for level_vpac_out_3_en_utc1_complete_62" "0,1" newline bitfld.long 0x78 29. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_61,Enable Set for level_vpac_out_3_en_utc1_complete_61" "0,1" newline bitfld.long 0x78 28. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_60,Enable Set for level_vpac_out_3_en_utc1_complete_60" "0,1" newline bitfld.long 0x78 27. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_59,Enable Set for level_vpac_out_3_en_utc1_complete_59" "0,1" newline bitfld.long 0x78 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_58,Enable Set for level_vpac_out_3_en_utc1_complete_58" "0,1" newline bitfld.long 0x78 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_57,Enable Set for level_vpac_out_3_en_utc1_complete_57" "0,1" newline bitfld.long 0x78 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_56,Enable Set for level_vpac_out_3_en_utc1_complete_56" "0,1" newline bitfld.long 0x78 23. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_55,Enable Set for level_vpac_out_3_en_utc1_complete_55" "0,1" newline bitfld.long 0x78 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_54,Enable Set for level_vpac_out_3_en_utc1_complete_54" "0,1" newline bitfld.long 0x78 21. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_53,Enable Set for level_vpac_out_3_en_utc1_complete_53" "0,1" newline bitfld.long 0x78 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_52,Enable Set for level_vpac_out_3_en_utc1_complete_52" "0,1" newline bitfld.long 0x78 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_51,Enable Set for level_vpac_out_3_en_utc1_complete_51" "0,1" newline bitfld.long 0x78 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_50,Enable Set for level_vpac_out_3_en_utc1_complete_50" "0,1" newline bitfld.long 0x78 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_49,Enable Set for level_vpac_out_3_en_utc1_complete_49" "0,1" newline bitfld.long 0x78 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_48,Enable Set for level_vpac_out_3_en_utc1_complete_48" "0,1" newline bitfld.long 0x78 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_47,Enable Set for level_vpac_out_3_en_utc1_complete_47" "0,1" newline bitfld.long 0x78 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_46,Enable Set for level_vpac_out_3_en_utc1_complete_46" "0,1" newline bitfld.long 0x78 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_45,Enable Set for level_vpac_out_3_en_utc1_complete_45" "0,1" newline bitfld.long 0x78 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_44,Enable Set for level_vpac_out_3_en_utc1_complete_44" "0,1" newline bitfld.long 0x78 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_43,Enable Set for level_vpac_out_3_en_utc1_complete_43" "0,1" newline bitfld.long 0x78 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_42,Enable Set for level_vpac_out_3_en_utc1_complete_42" "0,1" newline bitfld.long 0x78 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_41,Enable Set for level_vpac_out_3_en_utc1_complete_41" "0,1" newline bitfld.long 0x78 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_40,Enable Set for level_vpac_out_3_en_utc1_complete_40" "0,1" newline bitfld.long 0x78 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_39,Enable Set for level_vpac_out_3_en_utc1_complete_39" "0,1" newline bitfld.long 0x78 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_38,Enable Set for level_vpac_out_3_en_utc1_complete_38" "0,1" newline bitfld.long 0x78 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_37,Enable Set for level_vpac_out_3_en_utc1_complete_37" "0,1" newline bitfld.long 0x78 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_36,Enable Set for level_vpac_out_3_en_utc1_complete_36" "0,1" newline bitfld.long 0x78 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_35,Enable Set for level_vpac_out_3_en_utc1_complete_35" "0,1" newline bitfld.long 0x78 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_34,Enable Set for level_vpac_out_3_en_utc1_complete_34" "0,1" newline bitfld.long 0x78 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_33,Enable Set for level_vpac_out_3_en_utc1_complete_33" "0,1" newline bitfld.long 0x78 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_32,Enable Set for level_vpac_out_3_en_utc1_complete_32" "0,1" line.long 0x7C "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_3_7,Enable Register 31" bitfld.long 0x7C 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_CTM_PULSE,Enable Set for level_vpac_out_3_en_ctm_pulse" "0,1" newline bitfld.long 0x7C 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_PROT_ERR,Enable Set for level_vpac_out_3_en_utc1_prot_err" "0,1" newline bitfld.long 0x7C 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_PROT_ERR,Enable Set for level_vpac_out_3_en_utc0_prot_err" "0,1" newline bitfld.long 0x7C 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_ERROR,Enable Set for level_vpac_out_3_en_utc1_error" "0,1" newline bitfld.long 0x7C 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_ERROR,Enable Set for level_vpac_out_3_en_utc0_error" "0,1" line.long 0x80 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_4_0,Enable Register 32" bitfld.long 0x80 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_CR_CFG_ERR,Enable Set for level_vpac_out_4_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x80 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for level_vpac_out_4_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x80 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for level_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x80 23. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for level_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x80 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x80 21. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x80 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for level_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x80 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for level_vpac_out_4_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x80 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_EE_CFG_ERR,Enable Set for level_vpac_out_4_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x80 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for level_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x80 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for level_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x80 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCC_CFG_ERR,Enable Set for level_vpac_out_4_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x80 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCFA_CFG_ERR,Enable Set for level_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x80 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_VP_ERR,Enable Set for level_vpac_out_4_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x80 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for level_vpac_out_4_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x80 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for level_vpac_out_4_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x80 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_DONE,Enable Set for level_vpac_out_4_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x80 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_START,Enable Set for level_vpac_out_4_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x80 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_CFG_ERR,Enable Set for level_vpac_out_4_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x80 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for level_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x80 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for level_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x80 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for level_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x80 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for level_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x80 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for level_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x80 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_AF_PULSE,Enable Set for level_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x80 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for level_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x80 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_CFG_ERR,Enable Set for level_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1" line.long 0x84 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_4_1,Enable Register 33" bitfld.long 0x84 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_VBUSM_RD_ERR,Enable Set for level_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x84 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_SL2_WR_ERR,Enable Set for level_vpac_out_4_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x84 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_FR_DONE_EVT,Enable Set for level_vpac_out_4_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x84 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_INT_SZOVF,Enable Set for level_vpac_out_4_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x84 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_IFR_OUTOFBOUND,Enable Set for level_vpac_out_4_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x84 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for level_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x84 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for level_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x84 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x84 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x88 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_4_2,Enable Register 34" bitfld.long 0x88 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_NF_SL2_RD_ERR,Enable Set for level_vpac_out_4_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x88 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_NF_SL2_WR_ERR,Enable Set for level_vpac_out_4_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x88 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_NF_FRAME_DONE,Enable Set for level_vpac_out_4_en_nf_frame_done" "0,1" newline bitfld.long 0x88 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x88 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x88 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for level_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x88 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for level_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x8C "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_4_3,Enable Register 35" bitfld.long 0x8C 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_6,Enable Set for level_vpac_out_4_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x8C 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_5,Enable Set for level_vpac_out_4_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x8C 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_4,Enable Set for level_vpac_out_4_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x8C 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_2,Enable Set for level_vpac_out_4_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x8C 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_vpac_out_4_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x8C 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_1_LEVEL,Enable Set for level_vpac_out_4_en_spare_pend_1_level" "0,1" newline bitfld.long 0x8C 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_1_PULSE,Enable Set for level_vpac_out_4_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x8C 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_0_LEVEL,Enable Set for level_vpac_out_4_en_spare_pend_0_level" "0,1" newline bitfld.long 0x8C 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_0_PULSE,Enable Set for level_vpac_out_4_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x8C 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_DEC_1,Enable Set for level_vpac_out_4_en_spare_dec_1" "0,1" newline bitfld.long 0x8C 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_DEC_0,Enable Set for level_vpac_out_4_en_spare_dec_0" "0,1" newline bitfld.long 0x8C 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_6,Enable Set for level_vpac_out_4_en_tdone_6" "0,1" newline bitfld.long 0x8C 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_5,Enable Set for level_vpac_out_4_en_tdone_5" "0,1" newline bitfld.long 0x8C 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_4,Enable Set for level_vpac_out_4_en_tdone_4" "0,1" newline bitfld.long 0x8C 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_2,Enable Set for level_vpac_out_4_en_tdone_2" "0,1" newline bitfld.long 0x8C 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_0,Enable Set for level_vpac_out_4_en_tdone_0" "0,1" newline bitfld.long 0x8C 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_6,Enable Set for level_vpac_out_4_en_pipe_done_6" "0,1" newline bitfld.long 0x8C 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_5,Enable Set for level_vpac_out_4_en_pipe_done_5" "0,1" newline bitfld.long 0x8C 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_4,Enable Set for level_vpac_out_4_en_pipe_done_4" "0,1" newline bitfld.long 0x8C 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_3,Enable Set for level_vpac_out_4_en_pipe_done_3" "0,1" newline bitfld.long 0x8C 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_2,Enable Set for level_vpac_out_4_en_pipe_done_2" "0,1" newline bitfld.long 0x8C 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_1,Enable Set for level_vpac_out_4_en_pipe_done_1" "0,1" newline bitfld.long 0x8C 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_0,Enable Set for level_vpac_out_4_en_pipe_done_0" "0,1" line.long 0x90 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_4_4,Enable Register 36" bitfld.long 0x90 31. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_31,Enable Set for level_vpac_out_4_en_utc0_complete_31" "0,1" newline bitfld.long 0x90 30. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_30,Enable Set for level_vpac_out_4_en_utc0_complete_30" "0,1" newline bitfld.long 0x90 29. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_29,Enable Set for level_vpac_out_4_en_utc0_complete_29" "0,1" newline bitfld.long 0x90 28. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_28,Enable Set for level_vpac_out_4_en_utc0_complete_28" "0,1" newline bitfld.long 0x90 27. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_27,Enable Set for level_vpac_out_4_en_utc0_complete_27" "0,1" newline bitfld.long 0x90 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_26,Enable Set for level_vpac_out_4_en_utc0_complete_26" "0,1" newline bitfld.long 0x90 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_25,Enable Set for level_vpac_out_4_en_utc0_complete_25" "0,1" newline bitfld.long 0x90 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_24,Enable Set for level_vpac_out_4_en_utc0_complete_24" "0,1" newline bitfld.long 0x90 23. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_23,Enable Set for level_vpac_out_4_en_utc0_complete_23" "0,1" newline bitfld.long 0x90 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_22,Enable Set for level_vpac_out_4_en_utc0_complete_22" "0,1" newline bitfld.long 0x90 21. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_21,Enable Set for level_vpac_out_4_en_utc0_complete_21" "0,1" newline bitfld.long 0x90 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_20,Enable Set for level_vpac_out_4_en_utc0_complete_20" "0,1" newline bitfld.long 0x90 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_19,Enable Set for level_vpac_out_4_en_utc0_complete_19" "0,1" newline bitfld.long 0x90 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_18,Enable Set for level_vpac_out_4_en_utc0_complete_18" "0,1" newline bitfld.long 0x90 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_17,Enable Set for level_vpac_out_4_en_utc0_complete_17" "0,1" newline bitfld.long 0x90 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_16,Enable Set for level_vpac_out_4_en_utc0_complete_16" "0,1" newline bitfld.long 0x90 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_15,Enable Set for level_vpac_out_4_en_utc0_complete_15" "0,1" newline bitfld.long 0x90 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_14,Enable Set for level_vpac_out_4_en_utc0_complete_14" "0,1" newline bitfld.long 0x90 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_13,Enable Set for level_vpac_out_4_en_utc0_complete_13" "0,1" newline bitfld.long 0x90 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_12,Enable Set for level_vpac_out_4_en_utc0_complete_12" "0,1" newline bitfld.long 0x90 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_11,Enable Set for level_vpac_out_4_en_utc0_complete_11" "0,1" newline bitfld.long 0x90 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_10,Enable Set for level_vpac_out_4_en_utc0_complete_10" "0,1" newline bitfld.long 0x90 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_9,Enable Set for level_vpac_out_4_en_utc0_complete_9" "0,1" newline bitfld.long 0x90 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_8,Enable Set for level_vpac_out_4_en_utc0_complete_8" "0,1" newline bitfld.long 0x90 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_7,Enable Set for level_vpac_out_4_en_utc0_complete_7" "0,1" newline bitfld.long 0x90 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_6,Enable Set for level_vpac_out_4_en_utc0_complete_6" "0,1" newline bitfld.long 0x90 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_5,Enable Set for level_vpac_out_4_en_utc0_complete_5" "0,1" newline bitfld.long 0x90 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_4,Enable Set for level_vpac_out_4_en_utc0_complete_4" "0,1" newline bitfld.long 0x90 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_3,Enable Set for level_vpac_out_4_en_utc0_complete_3" "0,1" newline bitfld.long 0x90 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_2,Enable Set for level_vpac_out_4_en_utc0_complete_2" "0,1" newline bitfld.long 0x90 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_1,Enable Set for level_vpac_out_4_en_utc0_complete_1" "0,1" newline bitfld.long 0x90 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_0,Enable Set for level_vpac_out_4_en_utc0_complete_0" "0,1" line.long 0x94 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_4_5,Enable Register 37" bitfld.long 0x94 31. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_31,Enable Set for level_vpac_out_4_en_utc1_complete_31" "0,1" newline bitfld.long 0x94 30. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_30,Enable Set for level_vpac_out_4_en_utc1_complete_30" "0,1" newline bitfld.long 0x94 29. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_29,Enable Set for level_vpac_out_4_en_utc1_complete_29" "0,1" newline bitfld.long 0x94 28. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_28,Enable Set for level_vpac_out_4_en_utc1_complete_28" "0,1" newline bitfld.long 0x94 27. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_27,Enable Set for level_vpac_out_4_en_utc1_complete_27" "0,1" newline bitfld.long 0x94 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_26,Enable Set for level_vpac_out_4_en_utc1_complete_26" "0,1" newline bitfld.long 0x94 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_25,Enable Set for level_vpac_out_4_en_utc1_complete_25" "0,1" newline bitfld.long 0x94 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_24,Enable Set for level_vpac_out_4_en_utc1_complete_24" "0,1" newline bitfld.long 0x94 23. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_23,Enable Set for level_vpac_out_4_en_utc1_complete_23" "0,1" newline bitfld.long 0x94 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_22,Enable Set for level_vpac_out_4_en_utc1_complete_22" "0,1" newline bitfld.long 0x94 21. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_21,Enable Set for level_vpac_out_4_en_utc1_complete_21" "0,1" newline bitfld.long 0x94 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_20,Enable Set for level_vpac_out_4_en_utc1_complete_20" "0,1" newline bitfld.long 0x94 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_19,Enable Set for level_vpac_out_4_en_utc1_complete_19" "0,1" newline bitfld.long 0x94 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_18,Enable Set for level_vpac_out_4_en_utc1_complete_18" "0,1" newline bitfld.long 0x94 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_17,Enable Set for level_vpac_out_4_en_utc1_complete_17" "0,1" newline bitfld.long 0x94 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_16,Enable Set for level_vpac_out_4_en_utc1_complete_16" "0,1" newline bitfld.long 0x94 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_15,Enable Set for level_vpac_out_4_en_utc1_complete_15" "0,1" newline bitfld.long 0x94 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_14,Enable Set for level_vpac_out_4_en_utc1_complete_14" "0,1" newline bitfld.long 0x94 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_13,Enable Set for level_vpac_out_4_en_utc1_complete_13" "0,1" newline bitfld.long 0x94 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_12,Enable Set for level_vpac_out_4_en_utc1_complete_12" "0,1" newline bitfld.long 0x94 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_11,Enable Set for level_vpac_out_4_en_utc1_complete_11" "0,1" newline bitfld.long 0x94 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_10,Enable Set for level_vpac_out_4_en_utc1_complete_10" "0,1" newline bitfld.long 0x94 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_9,Enable Set for level_vpac_out_4_en_utc1_complete_9" "0,1" newline bitfld.long 0x94 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_8,Enable Set for level_vpac_out_4_en_utc1_complete_8" "0,1" newline bitfld.long 0x94 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_7,Enable Set for level_vpac_out_4_en_utc1_complete_7" "0,1" newline bitfld.long 0x94 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_6,Enable Set for level_vpac_out_4_en_utc1_complete_6" "0,1" newline bitfld.long 0x94 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_5,Enable Set for level_vpac_out_4_en_utc1_complete_5" "0,1" newline bitfld.long 0x94 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_4,Enable Set for level_vpac_out_4_en_utc1_complete_4" "0,1" newline bitfld.long 0x94 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_3,Enable Set for level_vpac_out_4_en_utc1_complete_3" "0,1" newline bitfld.long 0x94 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_2,Enable Set for level_vpac_out_4_en_utc1_complete_2" "0,1" newline bitfld.long 0x94 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_1,Enable Set for level_vpac_out_4_en_utc1_complete_1" "0,1" newline bitfld.long 0x94 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_0,Enable Set for level_vpac_out_4_en_utc1_complete_0" "0,1" line.long 0x98 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_4_6,Enable Register 38" bitfld.long 0x98 31. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_63,Enable Set for level_vpac_out_4_en_utc1_complete_63" "0,1" newline bitfld.long 0x98 30. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_62,Enable Set for level_vpac_out_4_en_utc1_complete_62" "0,1" newline bitfld.long 0x98 29. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_61,Enable Set for level_vpac_out_4_en_utc1_complete_61" "0,1" newline bitfld.long 0x98 28. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_60,Enable Set for level_vpac_out_4_en_utc1_complete_60" "0,1" newline bitfld.long 0x98 27. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_59,Enable Set for level_vpac_out_4_en_utc1_complete_59" "0,1" newline bitfld.long 0x98 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_58,Enable Set for level_vpac_out_4_en_utc1_complete_58" "0,1" newline bitfld.long 0x98 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_57,Enable Set for level_vpac_out_4_en_utc1_complete_57" "0,1" newline bitfld.long 0x98 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_56,Enable Set for level_vpac_out_4_en_utc1_complete_56" "0,1" newline bitfld.long 0x98 23. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_55,Enable Set for level_vpac_out_4_en_utc1_complete_55" "0,1" newline bitfld.long 0x98 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_54,Enable Set for level_vpac_out_4_en_utc1_complete_54" "0,1" newline bitfld.long 0x98 21. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_53,Enable Set for level_vpac_out_4_en_utc1_complete_53" "0,1" newline bitfld.long 0x98 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_52,Enable Set for level_vpac_out_4_en_utc1_complete_52" "0,1" newline bitfld.long 0x98 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_51,Enable Set for level_vpac_out_4_en_utc1_complete_51" "0,1" newline bitfld.long 0x98 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_50,Enable Set for level_vpac_out_4_en_utc1_complete_50" "0,1" newline bitfld.long 0x98 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_49,Enable Set for level_vpac_out_4_en_utc1_complete_49" "0,1" newline bitfld.long 0x98 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_48,Enable Set for level_vpac_out_4_en_utc1_complete_48" "0,1" newline bitfld.long 0x98 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_47,Enable Set for level_vpac_out_4_en_utc1_complete_47" "0,1" newline bitfld.long 0x98 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_46,Enable Set for level_vpac_out_4_en_utc1_complete_46" "0,1" newline bitfld.long 0x98 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_45,Enable Set for level_vpac_out_4_en_utc1_complete_45" "0,1" newline bitfld.long 0x98 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_44,Enable Set for level_vpac_out_4_en_utc1_complete_44" "0,1" newline bitfld.long 0x98 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_43,Enable Set for level_vpac_out_4_en_utc1_complete_43" "0,1" newline bitfld.long 0x98 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_42,Enable Set for level_vpac_out_4_en_utc1_complete_42" "0,1" newline bitfld.long 0x98 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_41,Enable Set for level_vpac_out_4_en_utc1_complete_41" "0,1" newline bitfld.long 0x98 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_40,Enable Set for level_vpac_out_4_en_utc1_complete_40" "0,1" newline bitfld.long 0x98 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_39,Enable Set for level_vpac_out_4_en_utc1_complete_39" "0,1" newline bitfld.long 0x98 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_38,Enable Set for level_vpac_out_4_en_utc1_complete_38" "0,1" newline bitfld.long 0x98 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_37,Enable Set for level_vpac_out_4_en_utc1_complete_37" "0,1" newline bitfld.long 0x98 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_36,Enable Set for level_vpac_out_4_en_utc1_complete_36" "0,1" newline bitfld.long 0x98 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_35,Enable Set for level_vpac_out_4_en_utc1_complete_35" "0,1" newline bitfld.long 0x98 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_34,Enable Set for level_vpac_out_4_en_utc1_complete_34" "0,1" newline bitfld.long 0x98 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_33,Enable Set for level_vpac_out_4_en_utc1_complete_33" "0,1" newline bitfld.long 0x98 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_32,Enable Set for level_vpac_out_4_en_utc1_complete_32" "0,1" line.long 0x9C "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_4_7,Enable Register 39" bitfld.long 0x9C 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_CTM_PULSE,Enable Set for level_vpac_out_4_en_ctm_pulse" "0,1" newline bitfld.long 0x9C 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_PROT_ERR,Enable Set for level_vpac_out_4_en_utc1_prot_err" "0,1" newline bitfld.long 0x9C 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_PROT_ERR,Enable Set for level_vpac_out_4_en_utc0_prot_err" "0,1" newline bitfld.long 0x9C 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_ERROR,Enable Set for level_vpac_out_4_en_utc1_error" "0,1" newline bitfld.long 0x9C 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_ERROR,Enable Set for level_vpac_out_4_en_utc0_error" "0,1" line.long 0xA0 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_5_0,Enable Register 40" bitfld.long 0xA0 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_CR_CFG_ERR,Enable Set for level_vpac_out_5_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xA0 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for level_vpac_out_5_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xA0 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for level_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xA0 23. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for level_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xA0 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xA0 21. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xA0 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for level_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xA0 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for level_vpac_out_5_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xA0 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_EE_CFG_ERR,Enable Set for level_vpac_out_5_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xA0 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for level_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xA0 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for level_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xA0 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCC_CFG_ERR,Enable Set for level_vpac_out_5_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xA0 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCFA_CFG_ERR,Enable Set for level_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xA0 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_VP_ERR,Enable Set for level_vpac_out_5_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xA0 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for level_vpac_out_5_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xA0 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for level_vpac_out_5_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xA0 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_DONE,Enable Set for level_vpac_out_5_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xA0 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_START,Enable Set for level_vpac_out_5_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xA0 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_CFG_ERR,Enable Set for level_vpac_out_5_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xA0 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for level_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xA0 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for level_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xA0 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for level_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xA0 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for level_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xA0 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for level_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xA0 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_AF_PULSE,Enable Set for level_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xA0 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for level_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xA0 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_CFG_ERR,Enable Set for level_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1" line.long 0xA4 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_5_1,Enable Register 41" bitfld.long 0xA4 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_VBUSM_RD_ERR,Enable Set for level_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xA4 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_SL2_WR_ERR,Enable Set for level_vpac_out_5_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xA4 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_FR_DONE_EVT,Enable Set for level_vpac_out_5_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xA4 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_INT_SZOVF,Enable Set for level_vpac_out_5_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xA4 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_IFR_OUTOFBOUND,Enable Set for level_vpac_out_5_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xA4 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for level_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xA4 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for level_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xA4 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xA4 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xA8 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_5_2,Enable Register 42" bitfld.long 0xA8 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_NF_SL2_RD_ERR,Enable Set for level_vpac_out_5_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0xA8 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_NF_SL2_WR_ERR,Enable Set for level_vpac_out_5_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0xA8 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_NF_FRAME_DONE,Enable Set for level_vpac_out_5_en_nf_frame_done" "0,1" newline bitfld.long 0xA8 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xA8 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xA8 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for level_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xA8 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for level_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xAC "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_5_3,Enable Register 43" bitfld.long 0xAC 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_6,Enable Set for level_vpac_out_5_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xAC 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_5,Enable Set for level_vpac_out_5_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xAC 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_4,Enable Set for level_vpac_out_5_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xAC 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_2,Enable Set for level_vpac_out_5_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xAC 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_vpac_out_5_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xAC 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_1_LEVEL,Enable Set for level_vpac_out_5_en_spare_pend_1_level" "0,1" newline bitfld.long 0xAC 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_1_PULSE,Enable Set for level_vpac_out_5_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0xAC 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_0_LEVEL,Enable Set for level_vpac_out_5_en_spare_pend_0_level" "0,1" newline bitfld.long 0xAC 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_0_PULSE,Enable Set for level_vpac_out_5_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xAC 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_DEC_1,Enable Set for level_vpac_out_5_en_spare_dec_1" "0,1" newline bitfld.long 0xAC 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_DEC_0,Enable Set for level_vpac_out_5_en_spare_dec_0" "0,1" newline bitfld.long 0xAC 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_6,Enable Set for level_vpac_out_5_en_tdone_6" "0,1" newline bitfld.long 0xAC 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_5,Enable Set for level_vpac_out_5_en_tdone_5" "0,1" newline bitfld.long 0xAC 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_4,Enable Set for level_vpac_out_5_en_tdone_4" "0,1" newline bitfld.long 0xAC 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_2,Enable Set for level_vpac_out_5_en_tdone_2" "0,1" newline bitfld.long 0xAC 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_0,Enable Set for level_vpac_out_5_en_tdone_0" "0,1" newline bitfld.long 0xAC 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_6,Enable Set for level_vpac_out_5_en_pipe_done_6" "0,1" newline bitfld.long 0xAC 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_5,Enable Set for level_vpac_out_5_en_pipe_done_5" "0,1" newline bitfld.long 0xAC 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_4,Enable Set for level_vpac_out_5_en_pipe_done_4" "0,1" newline bitfld.long 0xAC 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_3,Enable Set for level_vpac_out_5_en_pipe_done_3" "0,1" newline bitfld.long 0xAC 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_2,Enable Set for level_vpac_out_5_en_pipe_done_2" "0,1" newline bitfld.long 0xAC 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_1,Enable Set for level_vpac_out_5_en_pipe_done_1" "0,1" newline bitfld.long 0xAC 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_0,Enable Set for level_vpac_out_5_en_pipe_done_0" "0,1" line.long 0xB0 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_5_4,Enable Register 44" bitfld.long 0xB0 31. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_31,Enable Set for level_vpac_out_5_en_utc0_complete_31" "0,1" newline bitfld.long 0xB0 30. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_30,Enable Set for level_vpac_out_5_en_utc0_complete_30" "0,1" newline bitfld.long 0xB0 29. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_29,Enable Set for level_vpac_out_5_en_utc0_complete_29" "0,1" newline bitfld.long 0xB0 28. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_28,Enable Set for level_vpac_out_5_en_utc0_complete_28" "0,1" newline bitfld.long 0xB0 27. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_27,Enable Set for level_vpac_out_5_en_utc0_complete_27" "0,1" newline bitfld.long 0xB0 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_26,Enable Set for level_vpac_out_5_en_utc0_complete_26" "0,1" newline bitfld.long 0xB0 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_25,Enable Set for level_vpac_out_5_en_utc0_complete_25" "0,1" newline bitfld.long 0xB0 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_24,Enable Set for level_vpac_out_5_en_utc0_complete_24" "0,1" newline bitfld.long 0xB0 23. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_23,Enable Set for level_vpac_out_5_en_utc0_complete_23" "0,1" newline bitfld.long 0xB0 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_22,Enable Set for level_vpac_out_5_en_utc0_complete_22" "0,1" newline bitfld.long 0xB0 21. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_21,Enable Set for level_vpac_out_5_en_utc0_complete_21" "0,1" newline bitfld.long 0xB0 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_20,Enable Set for level_vpac_out_5_en_utc0_complete_20" "0,1" newline bitfld.long 0xB0 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_19,Enable Set for level_vpac_out_5_en_utc0_complete_19" "0,1" newline bitfld.long 0xB0 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_18,Enable Set for level_vpac_out_5_en_utc0_complete_18" "0,1" newline bitfld.long 0xB0 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_17,Enable Set for level_vpac_out_5_en_utc0_complete_17" "0,1" newline bitfld.long 0xB0 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_16,Enable Set for level_vpac_out_5_en_utc0_complete_16" "0,1" newline bitfld.long 0xB0 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_15,Enable Set for level_vpac_out_5_en_utc0_complete_15" "0,1" newline bitfld.long 0xB0 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_14,Enable Set for level_vpac_out_5_en_utc0_complete_14" "0,1" newline bitfld.long 0xB0 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_13,Enable Set for level_vpac_out_5_en_utc0_complete_13" "0,1" newline bitfld.long 0xB0 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_12,Enable Set for level_vpac_out_5_en_utc0_complete_12" "0,1" newline bitfld.long 0xB0 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_11,Enable Set for level_vpac_out_5_en_utc0_complete_11" "0,1" newline bitfld.long 0xB0 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_10,Enable Set for level_vpac_out_5_en_utc0_complete_10" "0,1" newline bitfld.long 0xB0 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_9,Enable Set for level_vpac_out_5_en_utc0_complete_9" "0,1" newline bitfld.long 0xB0 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_8,Enable Set for level_vpac_out_5_en_utc0_complete_8" "0,1" newline bitfld.long 0xB0 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_7,Enable Set for level_vpac_out_5_en_utc0_complete_7" "0,1" newline bitfld.long 0xB0 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_6,Enable Set for level_vpac_out_5_en_utc0_complete_6" "0,1" newline bitfld.long 0xB0 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_5,Enable Set for level_vpac_out_5_en_utc0_complete_5" "0,1" newline bitfld.long 0xB0 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_4,Enable Set for level_vpac_out_5_en_utc0_complete_4" "0,1" newline bitfld.long 0xB0 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_3,Enable Set for level_vpac_out_5_en_utc0_complete_3" "0,1" newline bitfld.long 0xB0 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_2,Enable Set for level_vpac_out_5_en_utc0_complete_2" "0,1" newline bitfld.long 0xB0 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_1,Enable Set for level_vpac_out_5_en_utc0_complete_1" "0,1" newline bitfld.long 0xB0 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_0,Enable Set for level_vpac_out_5_en_utc0_complete_0" "0,1" line.long 0xB4 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_5_5,Enable Register 45" bitfld.long 0xB4 31. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_31,Enable Set for level_vpac_out_5_en_utc1_complete_31" "0,1" newline bitfld.long 0xB4 30. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_30,Enable Set for level_vpac_out_5_en_utc1_complete_30" "0,1" newline bitfld.long 0xB4 29. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_29,Enable Set for level_vpac_out_5_en_utc1_complete_29" "0,1" newline bitfld.long 0xB4 28. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_28,Enable Set for level_vpac_out_5_en_utc1_complete_28" "0,1" newline bitfld.long 0xB4 27. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_27,Enable Set for level_vpac_out_5_en_utc1_complete_27" "0,1" newline bitfld.long 0xB4 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_26,Enable Set for level_vpac_out_5_en_utc1_complete_26" "0,1" newline bitfld.long 0xB4 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_25,Enable Set for level_vpac_out_5_en_utc1_complete_25" "0,1" newline bitfld.long 0xB4 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_24,Enable Set for level_vpac_out_5_en_utc1_complete_24" "0,1" newline bitfld.long 0xB4 23. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_23,Enable Set for level_vpac_out_5_en_utc1_complete_23" "0,1" newline bitfld.long 0xB4 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_22,Enable Set for level_vpac_out_5_en_utc1_complete_22" "0,1" newline bitfld.long 0xB4 21. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_21,Enable Set for level_vpac_out_5_en_utc1_complete_21" "0,1" newline bitfld.long 0xB4 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_20,Enable Set for level_vpac_out_5_en_utc1_complete_20" "0,1" newline bitfld.long 0xB4 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_19,Enable Set for level_vpac_out_5_en_utc1_complete_19" "0,1" newline bitfld.long 0xB4 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_18,Enable Set for level_vpac_out_5_en_utc1_complete_18" "0,1" newline bitfld.long 0xB4 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_17,Enable Set for level_vpac_out_5_en_utc1_complete_17" "0,1" newline bitfld.long 0xB4 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_16,Enable Set for level_vpac_out_5_en_utc1_complete_16" "0,1" newline bitfld.long 0xB4 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_15,Enable Set for level_vpac_out_5_en_utc1_complete_15" "0,1" newline bitfld.long 0xB4 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_14,Enable Set for level_vpac_out_5_en_utc1_complete_14" "0,1" newline bitfld.long 0xB4 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_13,Enable Set for level_vpac_out_5_en_utc1_complete_13" "0,1" newline bitfld.long 0xB4 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_12,Enable Set for level_vpac_out_5_en_utc1_complete_12" "0,1" newline bitfld.long 0xB4 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_11,Enable Set for level_vpac_out_5_en_utc1_complete_11" "0,1" newline bitfld.long 0xB4 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_10,Enable Set for level_vpac_out_5_en_utc1_complete_10" "0,1" newline bitfld.long 0xB4 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_9,Enable Set for level_vpac_out_5_en_utc1_complete_9" "0,1" newline bitfld.long 0xB4 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_8,Enable Set for level_vpac_out_5_en_utc1_complete_8" "0,1" newline bitfld.long 0xB4 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_7,Enable Set for level_vpac_out_5_en_utc1_complete_7" "0,1" newline bitfld.long 0xB4 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_6,Enable Set for level_vpac_out_5_en_utc1_complete_6" "0,1" newline bitfld.long 0xB4 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_5,Enable Set for level_vpac_out_5_en_utc1_complete_5" "0,1" newline bitfld.long 0xB4 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_4,Enable Set for level_vpac_out_5_en_utc1_complete_4" "0,1" newline bitfld.long 0xB4 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_3,Enable Set for level_vpac_out_5_en_utc1_complete_3" "0,1" newline bitfld.long 0xB4 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_2,Enable Set for level_vpac_out_5_en_utc1_complete_2" "0,1" newline bitfld.long 0xB4 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_1,Enable Set for level_vpac_out_5_en_utc1_complete_1" "0,1" newline bitfld.long 0xB4 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_0,Enable Set for level_vpac_out_5_en_utc1_complete_0" "0,1" line.long 0xB8 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_5_6,Enable Register 46" bitfld.long 0xB8 31. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_63,Enable Set for level_vpac_out_5_en_utc1_complete_63" "0,1" newline bitfld.long 0xB8 30. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_62,Enable Set for level_vpac_out_5_en_utc1_complete_62" "0,1" newline bitfld.long 0xB8 29. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_61,Enable Set for level_vpac_out_5_en_utc1_complete_61" "0,1" newline bitfld.long 0xB8 28. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_60,Enable Set for level_vpac_out_5_en_utc1_complete_60" "0,1" newline bitfld.long 0xB8 27. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_59,Enable Set for level_vpac_out_5_en_utc1_complete_59" "0,1" newline bitfld.long 0xB8 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_58,Enable Set for level_vpac_out_5_en_utc1_complete_58" "0,1" newline bitfld.long 0xB8 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_57,Enable Set for level_vpac_out_5_en_utc1_complete_57" "0,1" newline bitfld.long 0xB8 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_56,Enable Set for level_vpac_out_5_en_utc1_complete_56" "0,1" newline bitfld.long 0xB8 23. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_55,Enable Set for level_vpac_out_5_en_utc1_complete_55" "0,1" newline bitfld.long 0xB8 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_54,Enable Set for level_vpac_out_5_en_utc1_complete_54" "0,1" newline bitfld.long 0xB8 21. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_53,Enable Set for level_vpac_out_5_en_utc1_complete_53" "0,1" newline bitfld.long 0xB8 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_52,Enable Set for level_vpac_out_5_en_utc1_complete_52" "0,1" newline bitfld.long 0xB8 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_51,Enable Set for level_vpac_out_5_en_utc1_complete_51" "0,1" newline bitfld.long 0xB8 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_50,Enable Set for level_vpac_out_5_en_utc1_complete_50" "0,1" newline bitfld.long 0xB8 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_49,Enable Set for level_vpac_out_5_en_utc1_complete_49" "0,1" newline bitfld.long 0xB8 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_48,Enable Set for level_vpac_out_5_en_utc1_complete_48" "0,1" newline bitfld.long 0xB8 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_47,Enable Set for level_vpac_out_5_en_utc1_complete_47" "0,1" newline bitfld.long 0xB8 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_46,Enable Set for level_vpac_out_5_en_utc1_complete_46" "0,1" newline bitfld.long 0xB8 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_45,Enable Set for level_vpac_out_5_en_utc1_complete_45" "0,1" newline bitfld.long 0xB8 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_44,Enable Set for level_vpac_out_5_en_utc1_complete_44" "0,1" newline bitfld.long 0xB8 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_43,Enable Set for level_vpac_out_5_en_utc1_complete_43" "0,1" newline bitfld.long 0xB8 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_42,Enable Set for level_vpac_out_5_en_utc1_complete_42" "0,1" newline bitfld.long 0xB8 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_41,Enable Set for level_vpac_out_5_en_utc1_complete_41" "0,1" newline bitfld.long 0xB8 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_40,Enable Set for level_vpac_out_5_en_utc1_complete_40" "0,1" newline bitfld.long 0xB8 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_39,Enable Set for level_vpac_out_5_en_utc1_complete_39" "0,1" newline bitfld.long 0xB8 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_38,Enable Set for level_vpac_out_5_en_utc1_complete_38" "0,1" newline bitfld.long 0xB8 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_37,Enable Set for level_vpac_out_5_en_utc1_complete_37" "0,1" newline bitfld.long 0xB8 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_36,Enable Set for level_vpac_out_5_en_utc1_complete_36" "0,1" newline bitfld.long 0xB8 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_35,Enable Set for level_vpac_out_5_en_utc1_complete_35" "0,1" newline bitfld.long 0xB8 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_34,Enable Set for level_vpac_out_5_en_utc1_complete_34" "0,1" newline bitfld.long 0xB8 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_33,Enable Set for level_vpac_out_5_en_utc1_complete_33" "0,1" newline bitfld.long 0xB8 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_32,Enable Set for level_vpac_out_5_en_utc1_complete_32" "0,1" line.long 0xBC "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_5_7,Enable Register 47" bitfld.long 0xBC 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_CTM_PULSE,Enable Set for level_vpac_out_5_en_ctm_pulse" "0,1" newline bitfld.long 0xBC 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_PROT_ERR,Enable Set for level_vpac_out_5_en_utc1_prot_err" "0,1" newline bitfld.long 0xBC 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_PROT_ERR,Enable Set for level_vpac_out_5_en_utc0_prot_err" "0,1" newline bitfld.long 0xBC 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_ERROR,Enable Set for level_vpac_out_5_en_utc1_error" "0,1" newline bitfld.long 0xBC 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_ERROR,Enable Set for level_vpac_out_5_en_utc0_error" "0,1" line.long 0xC0 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_0_0,Enable Register 48" bitfld.long 0xC0 26. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_CR_CFG_ERR,Enable Set for pulse_vpac_out_0_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xC0 25. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for pulse_vpac_out_0_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xC0 24. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for pulse_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xC0 23. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for pulse_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xC0 22. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xC0 21. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xC0 20. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for pulse_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xC0 19. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for pulse_vpac_out_0_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xC0 18. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_EE_CFG_ERR,Enable Set for pulse_vpac_out_0_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xC0 17. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for pulse_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xC0 16. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for pulse_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xC0 15. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCC_CFG_ERR,Enable Set for pulse_vpac_out_0_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xC0 14. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCFA_CFG_ERR,Enable Set for pulse_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xC0 13. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_VP_ERR,Enable Set for pulse_vpac_out_0_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xC0 12. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for pulse_vpac_out_0_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xC0 11. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for pulse_vpac_out_0_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xC0 10. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_DONE,Enable Set for pulse_vpac_out_0_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xC0 9. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_START,Enable Set for pulse_vpac_out_0_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xC0 8. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_CFG_ERR,Enable Set for pulse_vpac_out_0_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xC0 7. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for pulse_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xC0 6. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for pulse_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xC0 5. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for pulse_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xC0 4. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for pulse_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xC0 3. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for pulse_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xC0 2. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_AF_PULSE,Enable Set for pulse_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xC0 1. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for pulse_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xC0 0. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_CFG_ERR,Enable Set for pulse_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1" line.long 0xC4 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_0_1,Enable Register 49" bitfld.long 0xC4 8. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_VBUSM_RD_ERR,Enable Set for pulse_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xC4 7. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_SL2_WR_ERR,Enable Set for pulse_vpac_out_0_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xC4 6. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_FR_DONE_EVT,Enable Set for pulse_vpac_out_0_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xC4 5. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_INT_SZOVF,Enable Set for pulse_vpac_out_0_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xC4 4. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_IFR_OUTOFBOUND,Enable Set for pulse_vpac_out_0_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xC4 3. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for pulse_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xC4 2. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for pulse_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xC4 1. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xC4 0. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xC8 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_0_2,Enable Register 50" bitfld.long 0xC8 10. "ENABLE_PULSE_VPAC_OUT_0_EN_NF_SL2_RD_ERR,Enable Set for pulse_vpac_out_0_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0xC8 9. "ENABLE_PULSE_VPAC_OUT_0_EN_NF_SL2_WR_ERR,Enable Set for pulse_vpac_out_0_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0xC8 8. "ENABLE_PULSE_VPAC_OUT_0_EN_NF_FRAME_DONE,Enable Set for pulse_vpac_out_0_en_nf_frame_done" "0,1" newline bitfld.long 0xC8 3. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xC8 2. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xC8 1. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for pulse_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xC8 0. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for pulse_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xCC "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_0_3,Enable Register 51" bitfld.long 0xCC 26. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_6,Enable Set for pulse_vpac_out_0_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xCC 25. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_5,Enable Set for pulse_vpac_out_0_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xCC 24. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_4,Enable Set for pulse_vpac_out_0_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xCC 22. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_2,Enable Set for pulse_vpac_out_0_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xCC 20. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_vpac_out_0_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xCC 19. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_1_LEVEL,Enable Set for pulse_vpac_out_0_en_spare_pend_1_level" "0,1" newline bitfld.long 0xCC 18. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_1_PULSE,Enable Set for pulse_vpac_out_0_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0xCC 17. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_0_LEVEL,Enable Set for pulse_vpac_out_0_en_spare_pend_0_level" "0,1" newline bitfld.long 0xCC 16. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_0_PULSE,Enable Set for pulse_vpac_out_0_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xCC 15. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_DEC_1,Enable Set for pulse_vpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0xCC 14. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_DEC_0,Enable Set for pulse_vpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0xCC 13. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_6,Enable Set for pulse_vpac_out_0_en_tdone_6" "0,1" newline bitfld.long 0xCC 12. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_5,Enable Set for pulse_vpac_out_0_en_tdone_5" "0,1" newline bitfld.long 0xCC 11. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_4,Enable Set for pulse_vpac_out_0_en_tdone_4" "0,1" newline bitfld.long 0xCC 9. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_2,Enable Set for pulse_vpac_out_0_en_tdone_2" "0,1" newline bitfld.long 0xCC 7. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_0,Enable Set for pulse_vpac_out_0_en_tdone_0" "0,1" newline bitfld.long 0xCC 6. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_6,Enable Set for pulse_vpac_out_0_en_pipe_done_6" "0,1" newline bitfld.long 0xCC 5. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_5,Enable Set for pulse_vpac_out_0_en_pipe_done_5" "0,1" newline bitfld.long 0xCC 4. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_4,Enable Set for pulse_vpac_out_0_en_pipe_done_4" "0,1" newline bitfld.long 0xCC 3. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_3,Enable Set for pulse_vpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0xCC 2. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_2,Enable Set for pulse_vpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0xCC 1. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_1,Enable Set for pulse_vpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0xCC 0. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_0,Enable Set for pulse_vpac_out_0_en_pipe_done_0" "0,1" line.long 0xD0 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_0_4,Enable Register 52" bitfld.long 0xD0 31. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_31,Enable Set for pulse_vpac_out_0_en_utc0_complete_31" "0,1" newline bitfld.long 0xD0 30. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_30,Enable Set for pulse_vpac_out_0_en_utc0_complete_30" "0,1" newline bitfld.long 0xD0 29. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_29,Enable Set for pulse_vpac_out_0_en_utc0_complete_29" "0,1" newline bitfld.long 0xD0 28. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_28,Enable Set for pulse_vpac_out_0_en_utc0_complete_28" "0,1" newline bitfld.long 0xD0 27. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_27,Enable Set for pulse_vpac_out_0_en_utc0_complete_27" "0,1" newline bitfld.long 0xD0 26. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_26,Enable Set for pulse_vpac_out_0_en_utc0_complete_26" "0,1" newline bitfld.long 0xD0 25. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_25,Enable Set for pulse_vpac_out_0_en_utc0_complete_25" "0,1" newline bitfld.long 0xD0 24. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_24,Enable Set for pulse_vpac_out_0_en_utc0_complete_24" "0,1" newline bitfld.long 0xD0 23. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_23,Enable Set for pulse_vpac_out_0_en_utc0_complete_23" "0,1" newline bitfld.long 0xD0 22. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_22,Enable Set for pulse_vpac_out_0_en_utc0_complete_22" "0,1" newline bitfld.long 0xD0 21. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_21,Enable Set for pulse_vpac_out_0_en_utc0_complete_21" "0,1" newline bitfld.long 0xD0 20. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_20,Enable Set for pulse_vpac_out_0_en_utc0_complete_20" "0,1" newline bitfld.long 0xD0 19. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_19,Enable Set for pulse_vpac_out_0_en_utc0_complete_19" "0,1" newline bitfld.long 0xD0 18. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_18,Enable Set for pulse_vpac_out_0_en_utc0_complete_18" "0,1" newline bitfld.long 0xD0 17. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_17,Enable Set for pulse_vpac_out_0_en_utc0_complete_17" "0,1" newline bitfld.long 0xD0 16. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_16,Enable Set for pulse_vpac_out_0_en_utc0_complete_16" "0,1" newline bitfld.long 0xD0 15. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_15,Enable Set for pulse_vpac_out_0_en_utc0_complete_15" "0,1" newline bitfld.long 0xD0 14. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_14,Enable Set for pulse_vpac_out_0_en_utc0_complete_14" "0,1" newline bitfld.long 0xD0 13. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_13,Enable Set for pulse_vpac_out_0_en_utc0_complete_13" "0,1" newline bitfld.long 0xD0 12. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_12,Enable Set for pulse_vpac_out_0_en_utc0_complete_12" "0,1" newline bitfld.long 0xD0 11. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_11,Enable Set for pulse_vpac_out_0_en_utc0_complete_11" "0,1" newline bitfld.long 0xD0 10. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_10,Enable Set for pulse_vpac_out_0_en_utc0_complete_10" "0,1" newline bitfld.long 0xD0 9. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_9,Enable Set for pulse_vpac_out_0_en_utc0_complete_9" "0,1" newline bitfld.long 0xD0 8. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_8,Enable Set for pulse_vpac_out_0_en_utc0_complete_8" "0,1" newline bitfld.long 0xD0 7. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_7,Enable Set for pulse_vpac_out_0_en_utc0_complete_7" "0,1" newline bitfld.long 0xD0 6. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_6,Enable Set for pulse_vpac_out_0_en_utc0_complete_6" "0,1" newline bitfld.long 0xD0 5. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_5,Enable Set for pulse_vpac_out_0_en_utc0_complete_5" "0,1" newline bitfld.long 0xD0 4. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_4,Enable Set for pulse_vpac_out_0_en_utc0_complete_4" "0,1" newline bitfld.long 0xD0 3. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_3,Enable Set for pulse_vpac_out_0_en_utc0_complete_3" "0,1" newline bitfld.long 0xD0 2. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_2,Enable Set for pulse_vpac_out_0_en_utc0_complete_2" "0,1" newline bitfld.long 0xD0 1. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_1,Enable Set for pulse_vpac_out_0_en_utc0_complete_1" "0,1" newline bitfld.long 0xD0 0. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_0,Enable Set for pulse_vpac_out_0_en_utc0_complete_0" "0,1" line.long 0xD4 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_0_5,Enable Register 53" bitfld.long 0xD4 31. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_31,Enable Set for pulse_vpac_out_0_en_utc1_complete_31" "0,1" newline bitfld.long 0xD4 30. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_30,Enable Set for pulse_vpac_out_0_en_utc1_complete_30" "0,1" newline bitfld.long 0xD4 29. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_29,Enable Set for pulse_vpac_out_0_en_utc1_complete_29" "0,1" newline bitfld.long 0xD4 28. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_28,Enable Set for pulse_vpac_out_0_en_utc1_complete_28" "0,1" newline bitfld.long 0xD4 27. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_27,Enable Set for pulse_vpac_out_0_en_utc1_complete_27" "0,1" newline bitfld.long 0xD4 26. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_26,Enable Set for pulse_vpac_out_0_en_utc1_complete_26" "0,1" newline bitfld.long 0xD4 25. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_25,Enable Set for pulse_vpac_out_0_en_utc1_complete_25" "0,1" newline bitfld.long 0xD4 24. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_24,Enable Set for pulse_vpac_out_0_en_utc1_complete_24" "0,1" newline bitfld.long 0xD4 23. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_23,Enable Set for pulse_vpac_out_0_en_utc1_complete_23" "0,1" newline bitfld.long 0xD4 22. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_22,Enable Set for pulse_vpac_out_0_en_utc1_complete_22" "0,1" newline bitfld.long 0xD4 21. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_21,Enable Set for pulse_vpac_out_0_en_utc1_complete_21" "0,1" newline bitfld.long 0xD4 20. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_20,Enable Set for pulse_vpac_out_0_en_utc1_complete_20" "0,1" newline bitfld.long 0xD4 19. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_19,Enable Set for pulse_vpac_out_0_en_utc1_complete_19" "0,1" newline bitfld.long 0xD4 18. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_18,Enable Set for pulse_vpac_out_0_en_utc1_complete_18" "0,1" newline bitfld.long 0xD4 17. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_17,Enable Set for pulse_vpac_out_0_en_utc1_complete_17" "0,1" newline bitfld.long 0xD4 16. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_16,Enable Set for pulse_vpac_out_0_en_utc1_complete_16" "0,1" newline bitfld.long 0xD4 15. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_15,Enable Set for pulse_vpac_out_0_en_utc1_complete_15" "0,1" newline bitfld.long 0xD4 14. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_14,Enable Set for pulse_vpac_out_0_en_utc1_complete_14" "0,1" newline bitfld.long 0xD4 13. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_13,Enable Set for pulse_vpac_out_0_en_utc1_complete_13" "0,1" newline bitfld.long 0xD4 12. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_12,Enable Set for pulse_vpac_out_0_en_utc1_complete_12" "0,1" newline bitfld.long 0xD4 11. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_11,Enable Set for pulse_vpac_out_0_en_utc1_complete_11" "0,1" newline bitfld.long 0xD4 10. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_10,Enable Set for pulse_vpac_out_0_en_utc1_complete_10" "0,1" newline bitfld.long 0xD4 9. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_9,Enable Set for pulse_vpac_out_0_en_utc1_complete_9" "0,1" newline bitfld.long 0xD4 8. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_8,Enable Set for pulse_vpac_out_0_en_utc1_complete_8" "0,1" newline bitfld.long 0xD4 7. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_7,Enable Set for pulse_vpac_out_0_en_utc1_complete_7" "0,1" newline bitfld.long 0xD4 6. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_6,Enable Set for pulse_vpac_out_0_en_utc1_complete_6" "0,1" newline bitfld.long 0xD4 5. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_5,Enable Set for pulse_vpac_out_0_en_utc1_complete_5" "0,1" newline bitfld.long 0xD4 4. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_4,Enable Set for pulse_vpac_out_0_en_utc1_complete_4" "0,1" newline bitfld.long 0xD4 3. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_3,Enable Set for pulse_vpac_out_0_en_utc1_complete_3" "0,1" newline bitfld.long 0xD4 2. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_2,Enable Set for pulse_vpac_out_0_en_utc1_complete_2" "0,1" newline bitfld.long 0xD4 1. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_1,Enable Set for pulse_vpac_out_0_en_utc1_complete_1" "0,1" newline bitfld.long 0xD4 0. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_0,Enable Set for pulse_vpac_out_0_en_utc1_complete_0" "0,1" line.long 0xD8 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_0_6,Enable Register 54" bitfld.long 0xD8 31. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_63,Enable Set for pulse_vpac_out_0_en_utc1_complete_63" "0,1" newline bitfld.long 0xD8 30. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_62,Enable Set for pulse_vpac_out_0_en_utc1_complete_62" "0,1" newline bitfld.long 0xD8 29. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_61,Enable Set for pulse_vpac_out_0_en_utc1_complete_61" "0,1" newline bitfld.long 0xD8 28. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_60,Enable Set for pulse_vpac_out_0_en_utc1_complete_60" "0,1" newline bitfld.long 0xD8 27. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_59,Enable Set for pulse_vpac_out_0_en_utc1_complete_59" "0,1" newline bitfld.long 0xD8 26. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_58,Enable Set for pulse_vpac_out_0_en_utc1_complete_58" "0,1" newline bitfld.long 0xD8 25. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_57,Enable Set for pulse_vpac_out_0_en_utc1_complete_57" "0,1" newline bitfld.long 0xD8 24. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_56,Enable Set for pulse_vpac_out_0_en_utc1_complete_56" "0,1" newline bitfld.long 0xD8 23. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_55,Enable Set for pulse_vpac_out_0_en_utc1_complete_55" "0,1" newline bitfld.long 0xD8 22. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_54,Enable Set for pulse_vpac_out_0_en_utc1_complete_54" "0,1" newline bitfld.long 0xD8 21. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_53,Enable Set for pulse_vpac_out_0_en_utc1_complete_53" "0,1" newline bitfld.long 0xD8 20. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_52,Enable Set for pulse_vpac_out_0_en_utc1_complete_52" "0,1" newline bitfld.long 0xD8 19. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_51,Enable Set for pulse_vpac_out_0_en_utc1_complete_51" "0,1" newline bitfld.long 0xD8 18. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_50,Enable Set for pulse_vpac_out_0_en_utc1_complete_50" "0,1" newline bitfld.long 0xD8 17. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_49,Enable Set for pulse_vpac_out_0_en_utc1_complete_49" "0,1" newline bitfld.long 0xD8 16. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_48,Enable Set for pulse_vpac_out_0_en_utc1_complete_48" "0,1" newline bitfld.long 0xD8 15. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_47,Enable Set for pulse_vpac_out_0_en_utc1_complete_47" "0,1" newline bitfld.long 0xD8 14. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_46,Enable Set for pulse_vpac_out_0_en_utc1_complete_46" "0,1" newline bitfld.long 0xD8 13. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_45,Enable Set for pulse_vpac_out_0_en_utc1_complete_45" "0,1" newline bitfld.long 0xD8 12. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_44,Enable Set for pulse_vpac_out_0_en_utc1_complete_44" "0,1" newline bitfld.long 0xD8 11. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_43,Enable Set for pulse_vpac_out_0_en_utc1_complete_43" "0,1" newline bitfld.long 0xD8 10. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_42,Enable Set for pulse_vpac_out_0_en_utc1_complete_42" "0,1" newline bitfld.long 0xD8 9. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_41,Enable Set for pulse_vpac_out_0_en_utc1_complete_41" "0,1" newline bitfld.long 0xD8 8. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_40,Enable Set for pulse_vpac_out_0_en_utc1_complete_40" "0,1" newline bitfld.long 0xD8 7. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_39,Enable Set for pulse_vpac_out_0_en_utc1_complete_39" "0,1" newline bitfld.long 0xD8 6. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_38,Enable Set for pulse_vpac_out_0_en_utc1_complete_38" "0,1" newline bitfld.long 0xD8 5. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_37,Enable Set for pulse_vpac_out_0_en_utc1_complete_37" "0,1" newline bitfld.long 0xD8 4. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_36,Enable Set for pulse_vpac_out_0_en_utc1_complete_36" "0,1" newline bitfld.long 0xD8 3. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_35,Enable Set for pulse_vpac_out_0_en_utc1_complete_35" "0,1" newline bitfld.long 0xD8 2. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_34,Enable Set for pulse_vpac_out_0_en_utc1_complete_34" "0,1" newline bitfld.long 0xD8 1. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_33,Enable Set for pulse_vpac_out_0_en_utc1_complete_33" "0,1" newline bitfld.long 0xD8 0. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_32,Enable Set for pulse_vpac_out_0_en_utc1_complete_32" "0,1" line.long 0xDC "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_0_7,Enable Register 55" bitfld.long 0xDC 4. "ENABLE_PULSE_VPAC_OUT_0_EN_CTM_PULSE,Enable Set for pulse_vpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0xDC 3. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_PROT_ERR,Enable Set for pulse_vpac_out_0_en_utc1_prot_err" "0,1" newline bitfld.long 0xDC 2. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_PROT_ERR,Enable Set for pulse_vpac_out_0_en_utc0_prot_err" "0,1" newline bitfld.long 0xDC 1. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_ERROR,Enable Set for pulse_vpac_out_0_en_utc1_error" "0,1" newline bitfld.long 0xDC 0. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_ERROR,Enable Set for pulse_vpac_out_0_en_utc0_error" "0,1" line.long 0xE0 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_1_0,Enable Register 56" bitfld.long 0xE0 26. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_CR_CFG_ERR,Enable Set for pulse_vpac_out_1_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xE0 25. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for pulse_vpac_out_1_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xE0 24. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for pulse_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xE0 23. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for pulse_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xE0 22. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xE0 21. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xE0 20. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for pulse_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xE0 19. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for pulse_vpac_out_1_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xE0 18. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_EE_CFG_ERR,Enable Set for pulse_vpac_out_1_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xE0 17. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for pulse_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xE0 16. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for pulse_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xE0 15. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCC_CFG_ERR,Enable Set for pulse_vpac_out_1_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xE0 14. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCFA_CFG_ERR,Enable Set for pulse_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xE0 13. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_VP_ERR,Enable Set for pulse_vpac_out_1_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xE0 12. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for pulse_vpac_out_1_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xE0 11. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for pulse_vpac_out_1_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xE0 10. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_DONE,Enable Set for pulse_vpac_out_1_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xE0 9. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_START,Enable Set for pulse_vpac_out_1_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xE0 8. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_CFG_ERR,Enable Set for pulse_vpac_out_1_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xE0 7. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for pulse_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xE0 6. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for pulse_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xE0 5. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for pulse_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xE0 4. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for pulse_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xE0 3. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for pulse_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xE0 2. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_AF_PULSE,Enable Set for pulse_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xE0 1. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for pulse_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xE0 0. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_CFG_ERR,Enable Set for pulse_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1" line.long 0xE4 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_1_1,Enable Register 57" bitfld.long 0xE4 8. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_VBUSM_RD_ERR,Enable Set for pulse_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xE4 7. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_SL2_WR_ERR,Enable Set for pulse_vpac_out_1_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xE4 6. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_FR_DONE_EVT,Enable Set for pulse_vpac_out_1_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xE4 5. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_INT_SZOVF,Enable Set for pulse_vpac_out_1_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xE4 4. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_IFR_OUTOFBOUND,Enable Set for pulse_vpac_out_1_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xE4 3. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for pulse_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xE4 2. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for pulse_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xE4 1. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xE4 0. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xE8 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_1_2,Enable Register 58" bitfld.long 0xE8 10. "ENABLE_PULSE_VPAC_OUT_1_EN_NF_SL2_RD_ERR,Enable Set for pulse_vpac_out_1_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0xE8 9. "ENABLE_PULSE_VPAC_OUT_1_EN_NF_SL2_WR_ERR,Enable Set for pulse_vpac_out_1_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0xE8 8. "ENABLE_PULSE_VPAC_OUT_1_EN_NF_FRAME_DONE,Enable Set for pulse_vpac_out_1_en_nf_frame_done" "0,1" newline bitfld.long 0xE8 3. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xE8 2. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xE8 1. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for pulse_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xE8 0. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for pulse_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xEC "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_1_3,Enable Register 59" bitfld.long 0xEC 26. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_6,Enable Set for pulse_vpac_out_1_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xEC 25. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_5,Enable Set for pulse_vpac_out_1_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xEC 24. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_4,Enable Set for pulse_vpac_out_1_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xEC 22. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_2,Enable Set for pulse_vpac_out_1_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xEC 20. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_vpac_out_1_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xEC 19. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_1_LEVEL,Enable Set for pulse_vpac_out_1_en_spare_pend_1_level" "0,1" newline bitfld.long 0xEC 18. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_1_PULSE,Enable Set for pulse_vpac_out_1_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0xEC 17. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_0_LEVEL,Enable Set for pulse_vpac_out_1_en_spare_pend_0_level" "0,1" newline bitfld.long 0xEC 16. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_0_PULSE,Enable Set for pulse_vpac_out_1_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xEC 15. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_DEC_1,Enable Set for pulse_vpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0xEC 14. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_DEC_0,Enable Set for pulse_vpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0xEC 13. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_6,Enable Set for pulse_vpac_out_1_en_tdone_6" "0,1" newline bitfld.long 0xEC 12. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_5,Enable Set for pulse_vpac_out_1_en_tdone_5" "0,1" newline bitfld.long 0xEC 11. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_4,Enable Set for pulse_vpac_out_1_en_tdone_4" "0,1" newline bitfld.long 0xEC 9. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_2,Enable Set for pulse_vpac_out_1_en_tdone_2" "0,1" newline bitfld.long 0xEC 7. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_0,Enable Set for pulse_vpac_out_1_en_tdone_0" "0,1" newline bitfld.long 0xEC 6. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_6,Enable Set for pulse_vpac_out_1_en_pipe_done_6" "0,1" newline bitfld.long 0xEC 5. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_5,Enable Set for pulse_vpac_out_1_en_pipe_done_5" "0,1" newline bitfld.long 0xEC 4. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_4,Enable Set for pulse_vpac_out_1_en_pipe_done_4" "0,1" newline bitfld.long 0xEC 3. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_3,Enable Set for pulse_vpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0xEC 2. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_2,Enable Set for pulse_vpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0xEC 1. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_1,Enable Set for pulse_vpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0xEC 0. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_0,Enable Set for pulse_vpac_out_1_en_pipe_done_0" "0,1" line.long 0xF0 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_1_4,Enable Register 60" bitfld.long 0xF0 31. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_31,Enable Set for pulse_vpac_out_1_en_utc0_complete_31" "0,1" newline bitfld.long 0xF0 30. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_30,Enable Set for pulse_vpac_out_1_en_utc0_complete_30" "0,1" newline bitfld.long 0xF0 29. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_29,Enable Set for pulse_vpac_out_1_en_utc0_complete_29" "0,1" newline bitfld.long 0xF0 28. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_28,Enable Set for pulse_vpac_out_1_en_utc0_complete_28" "0,1" newline bitfld.long 0xF0 27. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_27,Enable Set for pulse_vpac_out_1_en_utc0_complete_27" "0,1" newline bitfld.long 0xF0 26. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_26,Enable Set for pulse_vpac_out_1_en_utc0_complete_26" "0,1" newline bitfld.long 0xF0 25. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_25,Enable Set for pulse_vpac_out_1_en_utc0_complete_25" "0,1" newline bitfld.long 0xF0 24. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_24,Enable Set for pulse_vpac_out_1_en_utc0_complete_24" "0,1" newline bitfld.long 0xF0 23. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_23,Enable Set for pulse_vpac_out_1_en_utc0_complete_23" "0,1" newline bitfld.long 0xF0 22. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_22,Enable Set for pulse_vpac_out_1_en_utc0_complete_22" "0,1" newline bitfld.long 0xF0 21. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_21,Enable Set for pulse_vpac_out_1_en_utc0_complete_21" "0,1" newline bitfld.long 0xF0 20. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_20,Enable Set for pulse_vpac_out_1_en_utc0_complete_20" "0,1" newline bitfld.long 0xF0 19. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_19,Enable Set for pulse_vpac_out_1_en_utc0_complete_19" "0,1" newline bitfld.long 0xF0 18. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_18,Enable Set for pulse_vpac_out_1_en_utc0_complete_18" "0,1" newline bitfld.long 0xF0 17. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_17,Enable Set for pulse_vpac_out_1_en_utc0_complete_17" "0,1" newline bitfld.long 0xF0 16. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_16,Enable Set for pulse_vpac_out_1_en_utc0_complete_16" "0,1" newline bitfld.long 0xF0 15. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_15,Enable Set for pulse_vpac_out_1_en_utc0_complete_15" "0,1" newline bitfld.long 0xF0 14. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_14,Enable Set for pulse_vpac_out_1_en_utc0_complete_14" "0,1" newline bitfld.long 0xF0 13. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_13,Enable Set for pulse_vpac_out_1_en_utc0_complete_13" "0,1" newline bitfld.long 0xF0 12. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_12,Enable Set for pulse_vpac_out_1_en_utc0_complete_12" "0,1" newline bitfld.long 0xF0 11. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_11,Enable Set for pulse_vpac_out_1_en_utc0_complete_11" "0,1" newline bitfld.long 0xF0 10. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_10,Enable Set for pulse_vpac_out_1_en_utc0_complete_10" "0,1" newline bitfld.long 0xF0 9. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_9,Enable Set for pulse_vpac_out_1_en_utc0_complete_9" "0,1" newline bitfld.long 0xF0 8. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_8,Enable Set for pulse_vpac_out_1_en_utc0_complete_8" "0,1" newline bitfld.long 0xF0 7. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_7,Enable Set for pulse_vpac_out_1_en_utc0_complete_7" "0,1" newline bitfld.long 0xF0 6. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_6,Enable Set for pulse_vpac_out_1_en_utc0_complete_6" "0,1" newline bitfld.long 0xF0 5. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_5,Enable Set for pulse_vpac_out_1_en_utc0_complete_5" "0,1" newline bitfld.long 0xF0 4. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_4,Enable Set for pulse_vpac_out_1_en_utc0_complete_4" "0,1" newline bitfld.long 0xF0 3. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_3,Enable Set for pulse_vpac_out_1_en_utc0_complete_3" "0,1" newline bitfld.long 0xF0 2. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_2,Enable Set for pulse_vpac_out_1_en_utc0_complete_2" "0,1" newline bitfld.long 0xF0 1. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_1,Enable Set for pulse_vpac_out_1_en_utc0_complete_1" "0,1" newline bitfld.long 0xF0 0. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_0,Enable Set for pulse_vpac_out_1_en_utc0_complete_0" "0,1" line.long 0xF4 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_1_5,Enable Register 61" bitfld.long 0xF4 31. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_31,Enable Set for pulse_vpac_out_1_en_utc1_complete_31" "0,1" newline bitfld.long 0xF4 30. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_30,Enable Set for pulse_vpac_out_1_en_utc1_complete_30" "0,1" newline bitfld.long 0xF4 29. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_29,Enable Set for pulse_vpac_out_1_en_utc1_complete_29" "0,1" newline bitfld.long 0xF4 28. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_28,Enable Set for pulse_vpac_out_1_en_utc1_complete_28" "0,1" newline bitfld.long 0xF4 27. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_27,Enable Set for pulse_vpac_out_1_en_utc1_complete_27" "0,1" newline bitfld.long 0xF4 26. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_26,Enable Set for pulse_vpac_out_1_en_utc1_complete_26" "0,1" newline bitfld.long 0xF4 25. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_25,Enable Set for pulse_vpac_out_1_en_utc1_complete_25" "0,1" newline bitfld.long 0xF4 24. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_24,Enable Set for pulse_vpac_out_1_en_utc1_complete_24" "0,1" newline bitfld.long 0xF4 23. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_23,Enable Set for pulse_vpac_out_1_en_utc1_complete_23" "0,1" newline bitfld.long 0xF4 22. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_22,Enable Set for pulse_vpac_out_1_en_utc1_complete_22" "0,1" newline bitfld.long 0xF4 21. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_21,Enable Set for pulse_vpac_out_1_en_utc1_complete_21" "0,1" newline bitfld.long 0xF4 20. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_20,Enable Set for pulse_vpac_out_1_en_utc1_complete_20" "0,1" newline bitfld.long 0xF4 19. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_19,Enable Set for pulse_vpac_out_1_en_utc1_complete_19" "0,1" newline bitfld.long 0xF4 18. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_18,Enable Set for pulse_vpac_out_1_en_utc1_complete_18" "0,1" newline bitfld.long 0xF4 17. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_17,Enable Set for pulse_vpac_out_1_en_utc1_complete_17" "0,1" newline bitfld.long 0xF4 16. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_16,Enable Set for pulse_vpac_out_1_en_utc1_complete_16" "0,1" newline bitfld.long 0xF4 15. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_15,Enable Set for pulse_vpac_out_1_en_utc1_complete_15" "0,1" newline bitfld.long 0xF4 14. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_14,Enable Set for pulse_vpac_out_1_en_utc1_complete_14" "0,1" newline bitfld.long 0xF4 13. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_13,Enable Set for pulse_vpac_out_1_en_utc1_complete_13" "0,1" newline bitfld.long 0xF4 12. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_12,Enable Set for pulse_vpac_out_1_en_utc1_complete_12" "0,1" newline bitfld.long 0xF4 11. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_11,Enable Set for pulse_vpac_out_1_en_utc1_complete_11" "0,1" newline bitfld.long 0xF4 10. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_10,Enable Set for pulse_vpac_out_1_en_utc1_complete_10" "0,1" newline bitfld.long 0xF4 9. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_9,Enable Set for pulse_vpac_out_1_en_utc1_complete_9" "0,1" newline bitfld.long 0xF4 8. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_8,Enable Set for pulse_vpac_out_1_en_utc1_complete_8" "0,1" newline bitfld.long 0xF4 7. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_7,Enable Set for pulse_vpac_out_1_en_utc1_complete_7" "0,1" newline bitfld.long 0xF4 6. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_6,Enable Set for pulse_vpac_out_1_en_utc1_complete_6" "0,1" newline bitfld.long 0xF4 5. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_5,Enable Set for pulse_vpac_out_1_en_utc1_complete_5" "0,1" newline bitfld.long 0xF4 4. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_4,Enable Set for pulse_vpac_out_1_en_utc1_complete_4" "0,1" newline bitfld.long 0xF4 3. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_3,Enable Set for pulse_vpac_out_1_en_utc1_complete_3" "0,1" newline bitfld.long 0xF4 2. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_2,Enable Set for pulse_vpac_out_1_en_utc1_complete_2" "0,1" newline bitfld.long 0xF4 1. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_1,Enable Set for pulse_vpac_out_1_en_utc1_complete_1" "0,1" newline bitfld.long 0xF4 0. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_0,Enable Set for pulse_vpac_out_1_en_utc1_complete_0" "0,1" line.long 0xF8 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_1_6,Enable Register 62" bitfld.long 0xF8 31. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_63,Enable Set for pulse_vpac_out_1_en_utc1_complete_63" "0,1" newline bitfld.long 0xF8 30. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_62,Enable Set for pulse_vpac_out_1_en_utc1_complete_62" "0,1" newline bitfld.long 0xF8 29. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_61,Enable Set for pulse_vpac_out_1_en_utc1_complete_61" "0,1" newline bitfld.long 0xF8 28. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_60,Enable Set for pulse_vpac_out_1_en_utc1_complete_60" "0,1" newline bitfld.long 0xF8 27. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_59,Enable Set for pulse_vpac_out_1_en_utc1_complete_59" "0,1" newline bitfld.long 0xF8 26. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_58,Enable Set for pulse_vpac_out_1_en_utc1_complete_58" "0,1" newline bitfld.long 0xF8 25. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_57,Enable Set for pulse_vpac_out_1_en_utc1_complete_57" "0,1" newline bitfld.long 0xF8 24. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_56,Enable Set for pulse_vpac_out_1_en_utc1_complete_56" "0,1" newline bitfld.long 0xF8 23. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_55,Enable Set for pulse_vpac_out_1_en_utc1_complete_55" "0,1" newline bitfld.long 0xF8 22. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_54,Enable Set for pulse_vpac_out_1_en_utc1_complete_54" "0,1" newline bitfld.long 0xF8 21. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_53,Enable Set for pulse_vpac_out_1_en_utc1_complete_53" "0,1" newline bitfld.long 0xF8 20. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_52,Enable Set for pulse_vpac_out_1_en_utc1_complete_52" "0,1" newline bitfld.long 0xF8 19. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_51,Enable Set for pulse_vpac_out_1_en_utc1_complete_51" "0,1" newline bitfld.long 0xF8 18. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_50,Enable Set for pulse_vpac_out_1_en_utc1_complete_50" "0,1" newline bitfld.long 0xF8 17. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_49,Enable Set for pulse_vpac_out_1_en_utc1_complete_49" "0,1" newline bitfld.long 0xF8 16. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_48,Enable Set for pulse_vpac_out_1_en_utc1_complete_48" "0,1" newline bitfld.long 0xF8 15. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_47,Enable Set for pulse_vpac_out_1_en_utc1_complete_47" "0,1" newline bitfld.long 0xF8 14. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_46,Enable Set for pulse_vpac_out_1_en_utc1_complete_46" "0,1" newline bitfld.long 0xF8 13. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_45,Enable Set for pulse_vpac_out_1_en_utc1_complete_45" "0,1" newline bitfld.long 0xF8 12. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_44,Enable Set for pulse_vpac_out_1_en_utc1_complete_44" "0,1" newline bitfld.long 0xF8 11. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_43,Enable Set for pulse_vpac_out_1_en_utc1_complete_43" "0,1" newline bitfld.long 0xF8 10. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_42,Enable Set for pulse_vpac_out_1_en_utc1_complete_42" "0,1" newline bitfld.long 0xF8 9. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_41,Enable Set for pulse_vpac_out_1_en_utc1_complete_41" "0,1" newline bitfld.long 0xF8 8. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_40,Enable Set for pulse_vpac_out_1_en_utc1_complete_40" "0,1" newline bitfld.long 0xF8 7. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_39,Enable Set for pulse_vpac_out_1_en_utc1_complete_39" "0,1" newline bitfld.long 0xF8 6. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_38,Enable Set for pulse_vpac_out_1_en_utc1_complete_38" "0,1" newline bitfld.long 0xF8 5. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_37,Enable Set for pulse_vpac_out_1_en_utc1_complete_37" "0,1" newline bitfld.long 0xF8 4. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_36,Enable Set for pulse_vpac_out_1_en_utc1_complete_36" "0,1" newline bitfld.long 0xF8 3. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_35,Enable Set for pulse_vpac_out_1_en_utc1_complete_35" "0,1" newline bitfld.long 0xF8 2. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_34,Enable Set for pulse_vpac_out_1_en_utc1_complete_34" "0,1" newline bitfld.long 0xF8 1. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_33,Enable Set for pulse_vpac_out_1_en_utc1_complete_33" "0,1" newline bitfld.long 0xF8 0. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_32,Enable Set for pulse_vpac_out_1_en_utc1_complete_32" "0,1" line.long 0xFC "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_1_7,Enable Register 63" bitfld.long 0xFC 4. "ENABLE_PULSE_VPAC_OUT_1_EN_CTM_PULSE,Enable Set for pulse_vpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0xFC 3. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_PROT_ERR,Enable Set for pulse_vpac_out_1_en_utc1_prot_err" "0,1" newline bitfld.long 0xFC 2. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_PROT_ERR,Enable Set for pulse_vpac_out_1_en_utc0_prot_err" "0,1" newline bitfld.long 0xFC 1. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_ERROR,Enable Set for pulse_vpac_out_1_en_utc1_error" "0,1" newline bitfld.long 0xFC 0. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_ERROR,Enable Set for pulse_vpac_out_1_en_utc0_error" "0,1" line.long 0x100 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_2_0,Enable Register 64" bitfld.long 0x100 26. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_CR_CFG_ERR,Enable Set for pulse_vpac_out_2_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x100 25. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for pulse_vpac_out_2_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x100 24. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for pulse_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x100 23. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for pulse_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x100 22. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x100 21. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x100 20. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for pulse_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x100 19. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for pulse_vpac_out_2_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x100 18. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_EE_CFG_ERR,Enable Set for pulse_vpac_out_2_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x100 17. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for pulse_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x100 16. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for pulse_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x100 15. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCC_CFG_ERR,Enable Set for pulse_vpac_out_2_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x100 14. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCFA_CFG_ERR,Enable Set for pulse_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x100 13. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_VP_ERR,Enable Set for pulse_vpac_out_2_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x100 12. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for pulse_vpac_out_2_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x100 11. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for pulse_vpac_out_2_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x100 10. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_DONE,Enable Set for pulse_vpac_out_2_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x100 9. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_START,Enable Set for pulse_vpac_out_2_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x100 8. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_CFG_ERR,Enable Set for pulse_vpac_out_2_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x100 7. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for pulse_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x100 6. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for pulse_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x100 5. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for pulse_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x100 4. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for pulse_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x100 3. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for pulse_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x100 2. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_AF_PULSE,Enable Set for pulse_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x100 1. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for pulse_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x100 0. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_CFG_ERR,Enable Set for pulse_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1" line.long 0x104 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_2_1,Enable Register 65" bitfld.long 0x104 8. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_VBUSM_RD_ERR,Enable Set for pulse_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x104 7. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_SL2_WR_ERR,Enable Set for pulse_vpac_out_2_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x104 6. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_FR_DONE_EVT,Enable Set for pulse_vpac_out_2_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x104 5. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_INT_SZOVF,Enable Set for pulse_vpac_out_2_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x104 4. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_IFR_OUTOFBOUND,Enable Set for pulse_vpac_out_2_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x104 3. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for pulse_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x104 2. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for pulse_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x104 1. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x104 0. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x108 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_2_2,Enable Register 66" bitfld.long 0x108 10. "ENABLE_PULSE_VPAC_OUT_2_EN_NF_SL2_RD_ERR,Enable Set for pulse_vpac_out_2_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x108 9. "ENABLE_PULSE_VPAC_OUT_2_EN_NF_SL2_WR_ERR,Enable Set for pulse_vpac_out_2_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x108 8. "ENABLE_PULSE_VPAC_OUT_2_EN_NF_FRAME_DONE,Enable Set for pulse_vpac_out_2_en_nf_frame_done" "0,1" newline bitfld.long 0x108 3. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x108 2. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x108 1. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for pulse_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x108 0. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for pulse_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x10C "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_2_3,Enable Register 67" bitfld.long 0x10C 26. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_6,Enable Set for pulse_vpac_out_2_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x10C 25. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_5,Enable Set for pulse_vpac_out_2_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x10C 24. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_4,Enable Set for pulse_vpac_out_2_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x10C 22. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_2,Enable Set for pulse_vpac_out_2_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x10C 20. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_vpac_out_2_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x10C 19. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_1_LEVEL,Enable Set for pulse_vpac_out_2_en_spare_pend_1_level" "0,1" newline bitfld.long 0x10C 18. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_1_PULSE,Enable Set for pulse_vpac_out_2_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x10C 17. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_0_LEVEL,Enable Set for pulse_vpac_out_2_en_spare_pend_0_level" "0,1" newline bitfld.long 0x10C 16. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_0_PULSE,Enable Set for pulse_vpac_out_2_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x10C 15. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_DEC_1,Enable Set for pulse_vpac_out_2_en_spare_dec_1" "0,1" newline bitfld.long 0x10C 14. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_DEC_0,Enable Set for pulse_vpac_out_2_en_spare_dec_0" "0,1" newline bitfld.long 0x10C 13. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_6,Enable Set for pulse_vpac_out_2_en_tdone_6" "0,1" newline bitfld.long 0x10C 12. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_5,Enable Set for pulse_vpac_out_2_en_tdone_5" "0,1" newline bitfld.long 0x10C 11. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_4,Enable Set for pulse_vpac_out_2_en_tdone_4" "0,1" newline bitfld.long 0x10C 9. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_2,Enable Set for pulse_vpac_out_2_en_tdone_2" "0,1" newline bitfld.long 0x10C 7. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_0,Enable Set for pulse_vpac_out_2_en_tdone_0" "0,1" newline bitfld.long 0x10C 6. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_6,Enable Set for pulse_vpac_out_2_en_pipe_done_6" "0,1" newline bitfld.long 0x10C 5. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_5,Enable Set for pulse_vpac_out_2_en_pipe_done_5" "0,1" newline bitfld.long 0x10C 4. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_4,Enable Set for pulse_vpac_out_2_en_pipe_done_4" "0,1" newline bitfld.long 0x10C 3. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_3,Enable Set for pulse_vpac_out_2_en_pipe_done_3" "0,1" newline bitfld.long 0x10C 2. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_2,Enable Set for pulse_vpac_out_2_en_pipe_done_2" "0,1" newline bitfld.long 0x10C 1. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_1,Enable Set for pulse_vpac_out_2_en_pipe_done_1" "0,1" newline bitfld.long 0x10C 0. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_0,Enable Set for pulse_vpac_out_2_en_pipe_done_0" "0,1" line.long 0x110 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_2_4,Enable Register 68" bitfld.long 0x110 31. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_31,Enable Set for pulse_vpac_out_2_en_utc0_complete_31" "0,1" newline bitfld.long 0x110 30. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_30,Enable Set for pulse_vpac_out_2_en_utc0_complete_30" "0,1" newline bitfld.long 0x110 29. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_29,Enable Set for pulse_vpac_out_2_en_utc0_complete_29" "0,1" newline bitfld.long 0x110 28. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_28,Enable Set for pulse_vpac_out_2_en_utc0_complete_28" "0,1" newline bitfld.long 0x110 27. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_27,Enable Set for pulse_vpac_out_2_en_utc0_complete_27" "0,1" newline bitfld.long 0x110 26. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_26,Enable Set for pulse_vpac_out_2_en_utc0_complete_26" "0,1" newline bitfld.long 0x110 25. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_25,Enable Set for pulse_vpac_out_2_en_utc0_complete_25" "0,1" newline bitfld.long 0x110 24. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_24,Enable Set for pulse_vpac_out_2_en_utc0_complete_24" "0,1" newline bitfld.long 0x110 23. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_23,Enable Set for pulse_vpac_out_2_en_utc0_complete_23" "0,1" newline bitfld.long 0x110 22. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_22,Enable Set for pulse_vpac_out_2_en_utc0_complete_22" "0,1" newline bitfld.long 0x110 21. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_21,Enable Set for pulse_vpac_out_2_en_utc0_complete_21" "0,1" newline bitfld.long 0x110 20. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_20,Enable Set for pulse_vpac_out_2_en_utc0_complete_20" "0,1" newline bitfld.long 0x110 19. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_19,Enable Set for pulse_vpac_out_2_en_utc0_complete_19" "0,1" newline bitfld.long 0x110 18. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_18,Enable Set for pulse_vpac_out_2_en_utc0_complete_18" "0,1" newline bitfld.long 0x110 17. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_17,Enable Set for pulse_vpac_out_2_en_utc0_complete_17" "0,1" newline bitfld.long 0x110 16. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_16,Enable Set for pulse_vpac_out_2_en_utc0_complete_16" "0,1" newline bitfld.long 0x110 15. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_15,Enable Set for pulse_vpac_out_2_en_utc0_complete_15" "0,1" newline bitfld.long 0x110 14. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_14,Enable Set for pulse_vpac_out_2_en_utc0_complete_14" "0,1" newline bitfld.long 0x110 13. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_13,Enable Set for pulse_vpac_out_2_en_utc0_complete_13" "0,1" newline bitfld.long 0x110 12. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_12,Enable Set for pulse_vpac_out_2_en_utc0_complete_12" "0,1" newline bitfld.long 0x110 11. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_11,Enable Set for pulse_vpac_out_2_en_utc0_complete_11" "0,1" newline bitfld.long 0x110 10. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_10,Enable Set for pulse_vpac_out_2_en_utc0_complete_10" "0,1" newline bitfld.long 0x110 9. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_9,Enable Set for pulse_vpac_out_2_en_utc0_complete_9" "0,1" newline bitfld.long 0x110 8. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_8,Enable Set for pulse_vpac_out_2_en_utc0_complete_8" "0,1" newline bitfld.long 0x110 7. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_7,Enable Set for pulse_vpac_out_2_en_utc0_complete_7" "0,1" newline bitfld.long 0x110 6. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_6,Enable Set for pulse_vpac_out_2_en_utc0_complete_6" "0,1" newline bitfld.long 0x110 5. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_5,Enable Set for pulse_vpac_out_2_en_utc0_complete_5" "0,1" newline bitfld.long 0x110 4. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_4,Enable Set for pulse_vpac_out_2_en_utc0_complete_4" "0,1" newline bitfld.long 0x110 3. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_3,Enable Set for pulse_vpac_out_2_en_utc0_complete_3" "0,1" newline bitfld.long 0x110 2. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_2,Enable Set for pulse_vpac_out_2_en_utc0_complete_2" "0,1" newline bitfld.long 0x110 1. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_1,Enable Set for pulse_vpac_out_2_en_utc0_complete_1" "0,1" newline bitfld.long 0x110 0. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_0,Enable Set for pulse_vpac_out_2_en_utc0_complete_0" "0,1" line.long 0x114 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_2_5,Enable Register 69" bitfld.long 0x114 31. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_31,Enable Set for pulse_vpac_out_2_en_utc1_complete_31" "0,1" newline bitfld.long 0x114 30. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_30,Enable Set for pulse_vpac_out_2_en_utc1_complete_30" "0,1" newline bitfld.long 0x114 29. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_29,Enable Set for pulse_vpac_out_2_en_utc1_complete_29" "0,1" newline bitfld.long 0x114 28. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_28,Enable Set for pulse_vpac_out_2_en_utc1_complete_28" "0,1" newline bitfld.long 0x114 27. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_27,Enable Set for pulse_vpac_out_2_en_utc1_complete_27" "0,1" newline bitfld.long 0x114 26. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_26,Enable Set for pulse_vpac_out_2_en_utc1_complete_26" "0,1" newline bitfld.long 0x114 25. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_25,Enable Set for pulse_vpac_out_2_en_utc1_complete_25" "0,1" newline bitfld.long 0x114 24. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_24,Enable Set for pulse_vpac_out_2_en_utc1_complete_24" "0,1" newline bitfld.long 0x114 23. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_23,Enable Set for pulse_vpac_out_2_en_utc1_complete_23" "0,1" newline bitfld.long 0x114 22. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_22,Enable Set for pulse_vpac_out_2_en_utc1_complete_22" "0,1" newline bitfld.long 0x114 21. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_21,Enable Set for pulse_vpac_out_2_en_utc1_complete_21" "0,1" newline bitfld.long 0x114 20. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_20,Enable Set for pulse_vpac_out_2_en_utc1_complete_20" "0,1" newline bitfld.long 0x114 19. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_19,Enable Set for pulse_vpac_out_2_en_utc1_complete_19" "0,1" newline bitfld.long 0x114 18. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_18,Enable Set for pulse_vpac_out_2_en_utc1_complete_18" "0,1" newline bitfld.long 0x114 17. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_17,Enable Set for pulse_vpac_out_2_en_utc1_complete_17" "0,1" newline bitfld.long 0x114 16. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_16,Enable Set for pulse_vpac_out_2_en_utc1_complete_16" "0,1" newline bitfld.long 0x114 15. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_15,Enable Set for pulse_vpac_out_2_en_utc1_complete_15" "0,1" newline bitfld.long 0x114 14. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_14,Enable Set for pulse_vpac_out_2_en_utc1_complete_14" "0,1" newline bitfld.long 0x114 13. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_13,Enable Set for pulse_vpac_out_2_en_utc1_complete_13" "0,1" newline bitfld.long 0x114 12. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_12,Enable Set for pulse_vpac_out_2_en_utc1_complete_12" "0,1" newline bitfld.long 0x114 11. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_11,Enable Set for pulse_vpac_out_2_en_utc1_complete_11" "0,1" newline bitfld.long 0x114 10. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_10,Enable Set for pulse_vpac_out_2_en_utc1_complete_10" "0,1" newline bitfld.long 0x114 9. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_9,Enable Set for pulse_vpac_out_2_en_utc1_complete_9" "0,1" newline bitfld.long 0x114 8. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_8,Enable Set for pulse_vpac_out_2_en_utc1_complete_8" "0,1" newline bitfld.long 0x114 7. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_7,Enable Set for pulse_vpac_out_2_en_utc1_complete_7" "0,1" newline bitfld.long 0x114 6. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_6,Enable Set for pulse_vpac_out_2_en_utc1_complete_6" "0,1" newline bitfld.long 0x114 5. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_5,Enable Set for pulse_vpac_out_2_en_utc1_complete_5" "0,1" newline bitfld.long 0x114 4. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_4,Enable Set for pulse_vpac_out_2_en_utc1_complete_4" "0,1" newline bitfld.long 0x114 3. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_3,Enable Set for pulse_vpac_out_2_en_utc1_complete_3" "0,1" newline bitfld.long 0x114 2. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_2,Enable Set for pulse_vpac_out_2_en_utc1_complete_2" "0,1" newline bitfld.long 0x114 1. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_1,Enable Set for pulse_vpac_out_2_en_utc1_complete_1" "0,1" newline bitfld.long 0x114 0. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_0,Enable Set for pulse_vpac_out_2_en_utc1_complete_0" "0,1" line.long 0x118 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_2_6,Enable Register 70" bitfld.long 0x118 31. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_63,Enable Set for pulse_vpac_out_2_en_utc1_complete_63" "0,1" newline bitfld.long 0x118 30. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_62,Enable Set for pulse_vpac_out_2_en_utc1_complete_62" "0,1" newline bitfld.long 0x118 29. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_61,Enable Set for pulse_vpac_out_2_en_utc1_complete_61" "0,1" newline bitfld.long 0x118 28. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_60,Enable Set for pulse_vpac_out_2_en_utc1_complete_60" "0,1" newline bitfld.long 0x118 27. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_59,Enable Set for pulse_vpac_out_2_en_utc1_complete_59" "0,1" newline bitfld.long 0x118 26. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_58,Enable Set for pulse_vpac_out_2_en_utc1_complete_58" "0,1" newline bitfld.long 0x118 25. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_57,Enable Set for pulse_vpac_out_2_en_utc1_complete_57" "0,1" newline bitfld.long 0x118 24. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_56,Enable Set for pulse_vpac_out_2_en_utc1_complete_56" "0,1" newline bitfld.long 0x118 23. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_55,Enable Set for pulse_vpac_out_2_en_utc1_complete_55" "0,1" newline bitfld.long 0x118 22. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_54,Enable Set for pulse_vpac_out_2_en_utc1_complete_54" "0,1" newline bitfld.long 0x118 21. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_53,Enable Set for pulse_vpac_out_2_en_utc1_complete_53" "0,1" newline bitfld.long 0x118 20. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_52,Enable Set for pulse_vpac_out_2_en_utc1_complete_52" "0,1" newline bitfld.long 0x118 19. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_51,Enable Set for pulse_vpac_out_2_en_utc1_complete_51" "0,1" newline bitfld.long 0x118 18. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_50,Enable Set for pulse_vpac_out_2_en_utc1_complete_50" "0,1" newline bitfld.long 0x118 17. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_49,Enable Set for pulse_vpac_out_2_en_utc1_complete_49" "0,1" newline bitfld.long 0x118 16. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_48,Enable Set for pulse_vpac_out_2_en_utc1_complete_48" "0,1" newline bitfld.long 0x118 15. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_47,Enable Set for pulse_vpac_out_2_en_utc1_complete_47" "0,1" newline bitfld.long 0x118 14. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_46,Enable Set for pulse_vpac_out_2_en_utc1_complete_46" "0,1" newline bitfld.long 0x118 13. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_45,Enable Set for pulse_vpac_out_2_en_utc1_complete_45" "0,1" newline bitfld.long 0x118 12. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_44,Enable Set for pulse_vpac_out_2_en_utc1_complete_44" "0,1" newline bitfld.long 0x118 11. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_43,Enable Set for pulse_vpac_out_2_en_utc1_complete_43" "0,1" newline bitfld.long 0x118 10. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_42,Enable Set for pulse_vpac_out_2_en_utc1_complete_42" "0,1" newline bitfld.long 0x118 9. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_41,Enable Set for pulse_vpac_out_2_en_utc1_complete_41" "0,1" newline bitfld.long 0x118 8. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_40,Enable Set for pulse_vpac_out_2_en_utc1_complete_40" "0,1" newline bitfld.long 0x118 7. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_39,Enable Set for pulse_vpac_out_2_en_utc1_complete_39" "0,1" newline bitfld.long 0x118 6. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_38,Enable Set for pulse_vpac_out_2_en_utc1_complete_38" "0,1" newline bitfld.long 0x118 5. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_37,Enable Set for pulse_vpac_out_2_en_utc1_complete_37" "0,1" newline bitfld.long 0x118 4. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_36,Enable Set for pulse_vpac_out_2_en_utc1_complete_36" "0,1" newline bitfld.long 0x118 3. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_35,Enable Set for pulse_vpac_out_2_en_utc1_complete_35" "0,1" newline bitfld.long 0x118 2. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_34,Enable Set for pulse_vpac_out_2_en_utc1_complete_34" "0,1" newline bitfld.long 0x118 1. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_33,Enable Set for pulse_vpac_out_2_en_utc1_complete_33" "0,1" newline bitfld.long 0x118 0. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_32,Enable Set for pulse_vpac_out_2_en_utc1_complete_32" "0,1" line.long 0x11C "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_2_7,Enable Register 71" bitfld.long 0x11C 4. "ENABLE_PULSE_VPAC_OUT_2_EN_CTM_PULSE,Enable Set for pulse_vpac_out_2_en_ctm_pulse" "0,1" newline bitfld.long 0x11C 3. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_PROT_ERR,Enable Set for pulse_vpac_out_2_en_utc1_prot_err" "0,1" newline bitfld.long 0x11C 2. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_PROT_ERR,Enable Set for pulse_vpac_out_2_en_utc0_prot_err" "0,1" newline bitfld.long 0x11C 1. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_ERROR,Enable Set for pulse_vpac_out_2_en_utc1_error" "0,1" newline bitfld.long 0x11C 0. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_ERROR,Enable Set for pulse_vpac_out_2_en_utc0_error" "0,1" line.long 0x120 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_3_0,Enable Register 72" bitfld.long 0x120 26. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_CR_CFG_ERR,Enable Set for pulse_vpac_out_3_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x120 25. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for pulse_vpac_out_3_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x120 24. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for pulse_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x120 23. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for pulse_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x120 22. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x120 21. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x120 20. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for pulse_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x120 19. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for pulse_vpac_out_3_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x120 18. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_EE_CFG_ERR,Enable Set for pulse_vpac_out_3_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x120 17. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for pulse_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x120 16. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for pulse_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x120 15. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCC_CFG_ERR,Enable Set for pulse_vpac_out_3_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x120 14. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCFA_CFG_ERR,Enable Set for pulse_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x120 13. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_VP_ERR,Enable Set for pulse_vpac_out_3_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x120 12. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for pulse_vpac_out_3_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x120 11. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for pulse_vpac_out_3_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x120 10. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_DONE,Enable Set for pulse_vpac_out_3_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x120 9. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_START,Enable Set for pulse_vpac_out_3_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x120 8. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_CFG_ERR,Enable Set for pulse_vpac_out_3_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x120 7. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for pulse_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x120 6. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for pulse_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x120 5. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for pulse_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x120 4. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for pulse_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x120 3. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for pulse_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x120 2. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_AF_PULSE,Enable Set for pulse_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x120 1. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for pulse_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x120 0. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_CFG_ERR,Enable Set for pulse_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1" line.long 0x124 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_3_1,Enable Register 73" bitfld.long 0x124 8. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_VBUSM_RD_ERR,Enable Set for pulse_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x124 7. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_SL2_WR_ERR,Enable Set for pulse_vpac_out_3_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x124 6. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_FR_DONE_EVT,Enable Set for pulse_vpac_out_3_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x124 5. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_INT_SZOVF,Enable Set for pulse_vpac_out_3_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x124 4. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_IFR_OUTOFBOUND,Enable Set for pulse_vpac_out_3_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x124 3. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for pulse_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x124 2. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for pulse_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x124 1. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x124 0. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x128 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_3_2,Enable Register 74" bitfld.long 0x128 10. "ENABLE_PULSE_VPAC_OUT_3_EN_NF_SL2_RD_ERR,Enable Set for pulse_vpac_out_3_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x128 9. "ENABLE_PULSE_VPAC_OUT_3_EN_NF_SL2_WR_ERR,Enable Set for pulse_vpac_out_3_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x128 8. "ENABLE_PULSE_VPAC_OUT_3_EN_NF_FRAME_DONE,Enable Set for pulse_vpac_out_3_en_nf_frame_done" "0,1" newline bitfld.long 0x128 3. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x128 2. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x128 1. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for pulse_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x128 0. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for pulse_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x12C "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_3_3,Enable Register 75" bitfld.long 0x12C 26. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_6,Enable Set for pulse_vpac_out_3_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x12C 25. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_5,Enable Set for pulse_vpac_out_3_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x12C 24. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_4,Enable Set for pulse_vpac_out_3_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x12C 22. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_2,Enable Set for pulse_vpac_out_3_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x12C 20. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_vpac_out_3_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x12C 19. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_1_LEVEL,Enable Set for pulse_vpac_out_3_en_spare_pend_1_level" "0,1" newline bitfld.long 0x12C 18. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_1_PULSE,Enable Set for pulse_vpac_out_3_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x12C 17. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_0_LEVEL,Enable Set for pulse_vpac_out_3_en_spare_pend_0_level" "0,1" newline bitfld.long 0x12C 16. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_0_PULSE,Enable Set for pulse_vpac_out_3_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x12C 15. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_DEC_1,Enable Set for pulse_vpac_out_3_en_spare_dec_1" "0,1" newline bitfld.long 0x12C 14. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_DEC_0,Enable Set for pulse_vpac_out_3_en_spare_dec_0" "0,1" newline bitfld.long 0x12C 13. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_6,Enable Set for pulse_vpac_out_3_en_tdone_6" "0,1" newline bitfld.long 0x12C 12. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_5,Enable Set for pulse_vpac_out_3_en_tdone_5" "0,1" newline bitfld.long 0x12C 11. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_4,Enable Set for pulse_vpac_out_3_en_tdone_4" "0,1" newline bitfld.long 0x12C 9. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_2,Enable Set for pulse_vpac_out_3_en_tdone_2" "0,1" newline bitfld.long 0x12C 7. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_0,Enable Set for pulse_vpac_out_3_en_tdone_0" "0,1" newline bitfld.long 0x12C 6. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_6,Enable Set for pulse_vpac_out_3_en_pipe_done_6" "0,1" newline bitfld.long 0x12C 5. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_5,Enable Set for pulse_vpac_out_3_en_pipe_done_5" "0,1" newline bitfld.long 0x12C 4. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_4,Enable Set for pulse_vpac_out_3_en_pipe_done_4" "0,1" newline bitfld.long 0x12C 3. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_3,Enable Set for pulse_vpac_out_3_en_pipe_done_3" "0,1" newline bitfld.long 0x12C 2. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_2,Enable Set for pulse_vpac_out_3_en_pipe_done_2" "0,1" newline bitfld.long 0x12C 1. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_1,Enable Set for pulse_vpac_out_3_en_pipe_done_1" "0,1" newline bitfld.long 0x12C 0. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_0,Enable Set for pulse_vpac_out_3_en_pipe_done_0" "0,1" line.long 0x130 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_3_4,Enable Register 76" bitfld.long 0x130 31. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_31,Enable Set for pulse_vpac_out_3_en_utc0_complete_31" "0,1" newline bitfld.long 0x130 30. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_30,Enable Set for pulse_vpac_out_3_en_utc0_complete_30" "0,1" newline bitfld.long 0x130 29. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_29,Enable Set for pulse_vpac_out_3_en_utc0_complete_29" "0,1" newline bitfld.long 0x130 28. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_28,Enable Set for pulse_vpac_out_3_en_utc0_complete_28" "0,1" newline bitfld.long 0x130 27. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_27,Enable Set for pulse_vpac_out_3_en_utc0_complete_27" "0,1" newline bitfld.long 0x130 26. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_26,Enable Set for pulse_vpac_out_3_en_utc0_complete_26" "0,1" newline bitfld.long 0x130 25. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_25,Enable Set for pulse_vpac_out_3_en_utc0_complete_25" "0,1" newline bitfld.long 0x130 24. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_24,Enable Set for pulse_vpac_out_3_en_utc0_complete_24" "0,1" newline bitfld.long 0x130 23. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_23,Enable Set for pulse_vpac_out_3_en_utc0_complete_23" "0,1" newline bitfld.long 0x130 22. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_22,Enable Set for pulse_vpac_out_3_en_utc0_complete_22" "0,1" newline bitfld.long 0x130 21. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_21,Enable Set for pulse_vpac_out_3_en_utc0_complete_21" "0,1" newline bitfld.long 0x130 20. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_20,Enable Set for pulse_vpac_out_3_en_utc0_complete_20" "0,1" newline bitfld.long 0x130 19. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_19,Enable Set for pulse_vpac_out_3_en_utc0_complete_19" "0,1" newline bitfld.long 0x130 18. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_18,Enable Set for pulse_vpac_out_3_en_utc0_complete_18" "0,1" newline bitfld.long 0x130 17. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_17,Enable Set for pulse_vpac_out_3_en_utc0_complete_17" "0,1" newline bitfld.long 0x130 16. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_16,Enable Set for pulse_vpac_out_3_en_utc0_complete_16" "0,1" newline bitfld.long 0x130 15. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_15,Enable Set for pulse_vpac_out_3_en_utc0_complete_15" "0,1" newline bitfld.long 0x130 14. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_14,Enable Set for pulse_vpac_out_3_en_utc0_complete_14" "0,1" newline bitfld.long 0x130 13. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_13,Enable Set for pulse_vpac_out_3_en_utc0_complete_13" "0,1" newline bitfld.long 0x130 12. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_12,Enable Set for pulse_vpac_out_3_en_utc0_complete_12" "0,1" newline bitfld.long 0x130 11. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_11,Enable Set for pulse_vpac_out_3_en_utc0_complete_11" "0,1" newline bitfld.long 0x130 10. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_10,Enable Set for pulse_vpac_out_3_en_utc0_complete_10" "0,1" newline bitfld.long 0x130 9. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_9,Enable Set for pulse_vpac_out_3_en_utc0_complete_9" "0,1" newline bitfld.long 0x130 8. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_8,Enable Set for pulse_vpac_out_3_en_utc0_complete_8" "0,1" newline bitfld.long 0x130 7. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_7,Enable Set for pulse_vpac_out_3_en_utc0_complete_7" "0,1" newline bitfld.long 0x130 6. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_6,Enable Set for pulse_vpac_out_3_en_utc0_complete_6" "0,1" newline bitfld.long 0x130 5. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_5,Enable Set for pulse_vpac_out_3_en_utc0_complete_5" "0,1" newline bitfld.long 0x130 4. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_4,Enable Set for pulse_vpac_out_3_en_utc0_complete_4" "0,1" newline bitfld.long 0x130 3. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_3,Enable Set for pulse_vpac_out_3_en_utc0_complete_3" "0,1" newline bitfld.long 0x130 2. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_2,Enable Set for pulse_vpac_out_3_en_utc0_complete_2" "0,1" newline bitfld.long 0x130 1. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_1,Enable Set for pulse_vpac_out_3_en_utc0_complete_1" "0,1" newline bitfld.long 0x130 0. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_0,Enable Set for pulse_vpac_out_3_en_utc0_complete_0" "0,1" line.long 0x134 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_3_5,Enable Register 77" bitfld.long 0x134 31. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_31,Enable Set for pulse_vpac_out_3_en_utc1_complete_31" "0,1" newline bitfld.long 0x134 30. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_30,Enable Set for pulse_vpac_out_3_en_utc1_complete_30" "0,1" newline bitfld.long 0x134 29. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_29,Enable Set for pulse_vpac_out_3_en_utc1_complete_29" "0,1" newline bitfld.long 0x134 28. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_28,Enable Set for pulse_vpac_out_3_en_utc1_complete_28" "0,1" newline bitfld.long 0x134 27. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_27,Enable Set for pulse_vpac_out_3_en_utc1_complete_27" "0,1" newline bitfld.long 0x134 26. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_26,Enable Set for pulse_vpac_out_3_en_utc1_complete_26" "0,1" newline bitfld.long 0x134 25. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_25,Enable Set for pulse_vpac_out_3_en_utc1_complete_25" "0,1" newline bitfld.long 0x134 24. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_24,Enable Set for pulse_vpac_out_3_en_utc1_complete_24" "0,1" newline bitfld.long 0x134 23. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_23,Enable Set for pulse_vpac_out_3_en_utc1_complete_23" "0,1" newline bitfld.long 0x134 22. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_22,Enable Set for pulse_vpac_out_3_en_utc1_complete_22" "0,1" newline bitfld.long 0x134 21. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_21,Enable Set for pulse_vpac_out_3_en_utc1_complete_21" "0,1" newline bitfld.long 0x134 20. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_20,Enable Set for pulse_vpac_out_3_en_utc1_complete_20" "0,1" newline bitfld.long 0x134 19. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_19,Enable Set for pulse_vpac_out_3_en_utc1_complete_19" "0,1" newline bitfld.long 0x134 18. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_18,Enable Set for pulse_vpac_out_3_en_utc1_complete_18" "0,1" newline bitfld.long 0x134 17. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_17,Enable Set for pulse_vpac_out_3_en_utc1_complete_17" "0,1" newline bitfld.long 0x134 16. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_16,Enable Set for pulse_vpac_out_3_en_utc1_complete_16" "0,1" newline bitfld.long 0x134 15. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_15,Enable Set for pulse_vpac_out_3_en_utc1_complete_15" "0,1" newline bitfld.long 0x134 14. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_14,Enable Set for pulse_vpac_out_3_en_utc1_complete_14" "0,1" newline bitfld.long 0x134 13. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_13,Enable Set for pulse_vpac_out_3_en_utc1_complete_13" "0,1" newline bitfld.long 0x134 12. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_12,Enable Set for pulse_vpac_out_3_en_utc1_complete_12" "0,1" newline bitfld.long 0x134 11. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_11,Enable Set for pulse_vpac_out_3_en_utc1_complete_11" "0,1" newline bitfld.long 0x134 10. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_10,Enable Set for pulse_vpac_out_3_en_utc1_complete_10" "0,1" newline bitfld.long 0x134 9. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_9,Enable Set for pulse_vpac_out_3_en_utc1_complete_9" "0,1" newline bitfld.long 0x134 8. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_8,Enable Set for pulse_vpac_out_3_en_utc1_complete_8" "0,1" newline bitfld.long 0x134 7. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_7,Enable Set for pulse_vpac_out_3_en_utc1_complete_7" "0,1" newline bitfld.long 0x134 6. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_6,Enable Set for pulse_vpac_out_3_en_utc1_complete_6" "0,1" newline bitfld.long 0x134 5. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_5,Enable Set for pulse_vpac_out_3_en_utc1_complete_5" "0,1" newline bitfld.long 0x134 4. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_4,Enable Set for pulse_vpac_out_3_en_utc1_complete_4" "0,1" newline bitfld.long 0x134 3. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_3,Enable Set for pulse_vpac_out_3_en_utc1_complete_3" "0,1" newline bitfld.long 0x134 2. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_2,Enable Set for pulse_vpac_out_3_en_utc1_complete_2" "0,1" newline bitfld.long 0x134 1. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_1,Enable Set for pulse_vpac_out_3_en_utc1_complete_1" "0,1" newline bitfld.long 0x134 0. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_0,Enable Set for pulse_vpac_out_3_en_utc1_complete_0" "0,1" line.long 0x138 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_3_6,Enable Register 78" bitfld.long 0x138 31. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_63,Enable Set for pulse_vpac_out_3_en_utc1_complete_63" "0,1" newline bitfld.long 0x138 30. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_62,Enable Set for pulse_vpac_out_3_en_utc1_complete_62" "0,1" newline bitfld.long 0x138 29. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_61,Enable Set for pulse_vpac_out_3_en_utc1_complete_61" "0,1" newline bitfld.long 0x138 28. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_60,Enable Set for pulse_vpac_out_3_en_utc1_complete_60" "0,1" newline bitfld.long 0x138 27. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_59,Enable Set for pulse_vpac_out_3_en_utc1_complete_59" "0,1" newline bitfld.long 0x138 26. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_58,Enable Set for pulse_vpac_out_3_en_utc1_complete_58" "0,1" newline bitfld.long 0x138 25. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_57,Enable Set for pulse_vpac_out_3_en_utc1_complete_57" "0,1" newline bitfld.long 0x138 24. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_56,Enable Set for pulse_vpac_out_3_en_utc1_complete_56" "0,1" newline bitfld.long 0x138 23. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_55,Enable Set for pulse_vpac_out_3_en_utc1_complete_55" "0,1" newline bitfld.long 0x138 22. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_54,Enable Set for pulse_vpac_out_3_en_utc1_complete_54" "0,1" newline bitfld.long 0x138 21. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_53,Enable Set for pulse_vpac_out_3_en_utc1_complete_53" "0,1" newline bitfld.long 0x138 20. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_52,Enable Set for pulse_vpac_out_3_en_utc1_complete_52" "0,1" newline bitfld.long 0x138 19. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_51,Enable Set for pulse_vpac_out_3_en_utc1_complete_51" "0,1" newline bitfld.long 0x138 18. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_50,Enable Set for pulse_vpac_out_3_en_utc1_complete_50" "0,1" newline bitfld.long 0x138 17. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_49,Enable Set for pulse_vpac_out_3_en_utc1_complete_49" "0,1" newline bitfld.long 0x138 16. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_48,Enable Set for pulse_vpac_out_3_en_utc1_complete_48" "0,1" newline bitfld.long 0x138 15. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_47,Enable Set for pulse_vpac_out_3_en_utc1_complete_47" "0,1" newline bitfld.long 0x138 14. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_46,Enable Set for pulse_vpac_out_3_en_utc1_complete_46" "0,1" newline bitfld.long 0x138 13. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_45,Enable Set for pulse_vpac_out_3_en_utc1_complete_45" "0,1" newline bitfld.long 0x138 12. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_44,Enable Set for pulse_vpac_out_3_en_utc1_complete_44" "0,1" newline bitfld.long 0x138 11. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_43,Enable Set for pulse_vpac_out_3_en_utc1_complete_43" "0,1" newline bitfld.long 0x138 10. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_42,Enable Set for pulse_vpac_out_3_en_utc1_complete_42" "0,1" newline bitfld.long 0x138 9. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_41,Enable Set for pulse_vpac_out_3_en_utc1_complete_41" "0,1" newline bitfld.long 0x138 8. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_40,Enable Set for pulse_vpac_out_3_en_utc1_complete_40" "0,1" newline bitfld.long 0x138 7. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_39,Enable Set for pulse_vpac_out_3_en_utc1_complete_39" "0,1" newline bitfld.long 0x138 6. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_38,Enable Set for pulse_vpac_out_3_en_utc1_complete_38" "0,1" newline bitfld.long 0x138 5. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_37,Enable Set for pulse_vpac_out_3_en_utc1_complete_37" "0,1" newline bitfld.long 0x138 4. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_36,Enable Set for pulse_vpac_out_3_en_utc1_complete_36" "0,1" newline bitfld.long 0x138 3. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_35,Enable Set for pulse_vpac_out_3_en_utc1_complete_35" "0,1" newline bitfld.long 0x138 2. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_34,Enable Set for pulse_vpac_out_3_en_utc1_complete_34" "0,1" newline bitfld.long 0x138 1. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_33,Enable Set for pulse_vpac_out_3_en_utc1_complete_33" "0,1" newline bitfld.long 0x138 0. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_32,Enable Set for pulse_vpac_out_3_en_utc1_complete_32" "0,1" line.long 0x13C "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_3_7,Enable Register 79" bitfld.long 0x13C 4. "ENABLE_PULSE_VPAC_OUT_3_EN_CTM_PULSE,Enable Set for pulse_vpac_out_3_en_ctm_pulse" "0,1" newline bitfld.long 0x13C 3. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_PROT_ERR,Enable Set for pulse_vpac_out_3_en_utc1_prot_err" "0,1" newline bitfld.long 0x13C 2. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_PROT_ERR,Enable Set for pulse_vpac_out_3_en_utc0_prot_err" "0,1" newline bitfld.long 0x13C 1. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_ERROR,Enable Set for pulse_vpac_out_3_en_utc1_error" "0,1" newline bitfld.long 0x13C 0. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_ERROR,Enable Set for pulse_vpac_out_3_en_utc0_error" "0,1" line.long 0x140 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_4_0,Enable Register 80" bitfld.long 0x140 26. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_CR_CFG_ERR,Enable Set for pulse_vpac_out_4_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x140 25. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for pulse_vpac_out_4_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x140 24. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for pulse_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x140 23. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for pulse_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x140 22. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x140 21. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x140 20. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for pulse_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x140 19. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for pulse_vpac_out_4_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x140 18. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_EE_CFG_ERR,Enable Set for pulse_vpac_out_4_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x140 17. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for pulse_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x140 16. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for pulse_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x140 15. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCC_CFG_ERR,Enable Set for pulse_vpac_out_4_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x140 14. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCFA_CFG_ERR,Enable Set for pulse_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x140 13. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_VP_ERR,Enable Set for pulse_vpac_out_4_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x140 12. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for pulse_vpac_out_4_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x140 11. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for pulse_vpac_out_4_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x140 10. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_DONE,Enable Set for pulse_vpac_out_4_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x140 9. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_START,Enable Set for pulse_vpac_out_4_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x140 8. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_CFG_ERR,Enable Set for pulse_vpac_out_4_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x140 7. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for pulse_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x140 6. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for pulse_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x140 5. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for pulse_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x140 4. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for pulse_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x140 3. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for pulse_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x140 2. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_AF_PULSE,Enable Set for pulse_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x140 1. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for pulse_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x140 0. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_CFG_ERR,Enable Set for pulse_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1" line.long 0x144 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_4_1,Enable Register 81" bitfld.long 0x144 8. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_VBUSM_RD_ERR,Enable Set for pulse_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x144 7. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_SL2_WR_ERR,Enable Set for pulse_vpac_out_4_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x144 6. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_FR_DONE_EVT,Enable Set for pulse_vpac_out_4_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x144 5. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_INT_SZOVF,Enable Set for pulse_vpac_out_4_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x144 4. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_IFR_OUTOFBOUND,Enable Set for pulse_vpac_out_4_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x144 3. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for pulse_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x144 2. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for pulse_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x144 1. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x144 0. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x148 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_4_2,Enable Register 82" bitfld.long 0x148 10. "ENABLE_PULSE_VPAC_OUT_4_EN_NF_SL2_RD_ERR,Enable Set for pulse_vpac_out_4_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x148 9. "ENABLE_PULSE_VPAC_OUT_4_EN_NF_SL2_WR_ERR,Enable Set for pulse_vpac_out_4_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x148 8. "ENABLE_PULSE_VPAC_OUT_4_EN_NF_FRAME_DONE,Enable Set for pulse_vpac_out_4_en_nf_frame_done" "0,1" newline bitfld.long 0x148 3. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x148 2. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x148 1. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for pulse_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x148 0. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for pulse_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x14C "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_4_3,Enable Register 83" bitfld.long 0x14C 26. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_6,Enable Set for pulse_vpac_out_4_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x14C 25. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_5,Enable Set for pulse_vpac_out_4_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x14C 24. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_4,Enable Set for pulse_vpac_out_4_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x14C 22. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_2,Enable Set for pulse_vpac_out_4_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x14C 20. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_vpac_out_4_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x14C 19. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_1_LEVEL,Enable Set for pulse_vpac_out_4_en_spare_pend_1_level" "0,1" newline bitfld.long 0x14C 18. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_1_PULSE,Enable Set for pulse_vpac_out_4_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x14C 17. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_0_LEVEL,Enable Set for pulse_vpac_out_4_en_spare_pend_0_level" "0,1" newline bitfld.long 0x14C 16. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_0_PULSE,Enable Set for pulse_vpac_out_4_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x14C 15. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_DEC_1,Enable Set for pulse_vpac_out_4_en_spare_dec_1" "0,1" newline bitfld.long 0x14C 14. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_DEC_0,Enable Set for pulse_vpac_out_4_en_spare_dec_0" "0,1" newline bitfld.long 0x14C 13. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_6,Enable Set for pulse_vpac_out_4_en_tdone_6" "0,1" newline bitfld.long 0x14C 12. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_5,Enable Set for pulse_vpac_out_4_en_tdone_5" "0,1" newline bitfld.long 0x14C 11. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_4,Enable Set for pulse_vpac_out_4_en_tdone_4" "0,1" newline bitfld.long 0x14C 9. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_2,Enable Set for pulse_vpac_out_4_en_tdone_2" "0,1" newline bitfld.long 0x14C 7. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_0,Enable Set for pulse_vpac_out_4_en_tdone_0" "0,1" newline bitfld.long 0x14C 6. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_6,Enable Set for pulse_vpac_out_4_en_pipe_done_6" "0,1" newline bitfld.long 0x14C 5. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_5,Enable Set for pulse_vpac_out_4_en_pipe_done_5" "0,1" newline bitfld.long 0x14C 4. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_4,Enable Set for pulse_vpac_out_4_en_pipe_done_4" "0,1" newline bitfld.long 0x14C 3. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_3,Enable Set for pulse_vpac_out_4_en_pipe_done_3" "0,1" newline bitfld.long 0x14C 2. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_2,Enable Set for pulse_vpac_out_4_en_pipe_done_2" "0,1" newline bitfld.long 0x14C 1. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_1,Enable Set for pulse_vpac_out_4_en_pipe_done_1" "0,1" newline bitfld.long 0x14C 0. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_0,Enable Set for pulse_vpac_out_4_en_pipe_done_0" "0,1" line.long 0x150 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_4_4,Enable Register 84" bitfld.long 0x150 31. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_31,Enable Set for pulse_vpac_out_4_en_utc0_complete_31" "0,1" newline bitfld.long 0x150 30. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_30,Enable Set for pulse_vpac_out_4_en_utc0_complete_30" "0,1" newline bitfld.long 0x150 29. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_29,Enable Set for pulse_vpac_out_4_en_utc0_complete_29" "0,1" newline bitfld.long 0x150 28. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_28,Enable Set for pulse_vpac_out_4_en_utc0_complete_28" "0,1" newline bitfld.long 0x150 27. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_27,Enable Set for pulse_vpac_out_4_en_utc0_complete_27" "0,1" newline bitfld.long 0x150 26. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_26,Enable Set for pulse_vpac_out_4_en_utc0_complete_26" "0,1" newline bitfld.long 0x150 25. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_25,Enable Set for pulse_vpac_out_4_en_utc0_complete_25" "0,1" newline bitfld.long 0x150 24. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_24,Enable Set for pulse_vpac_out_4_en_utc0_complete_24" "0,1" newline bitfld.long 0x150 23. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_23,Enable Set for pulse_vpac_out_4_en_utc0_complete_23" "0,1" newline bitfld.long 0x150 22. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_22,Enable Set for pulse_vpac_out_4_en_utc0_complete_22" "0,1" newline bitfld.long 0x150 21. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_21,Enable Set for pulse_vpac_out_4_en_utc0_complete_21" "0,1" newline bitfld.long 0x150 20. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_20,Enable Set for pulse_vpac_out_4_en_utc0_complete_20" "0,1" newline bitfld.long 0x150 19. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_19,Enable Set for pulse_vpac_out_4_en_utc0_complete_19" "0,1" newline bitfld.long 0x150 18. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_18,Enable Set for pulse_vpac_out_4_en_utc0_complete_18" "0,1" newline bitfld.long 0x150 17. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_17,Enable Set for pulse_vpac_out_4_en_utc0_complete_17" "0,1" newline bitfld.long 0x150 16. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_16,Enable Set for pulse_vpac_out_4_en_utc0_complete_16" "0,1" newline bitfld.long 0x150 15. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_15,Enable Set for pulse_vpac_out_4_en_utc0_complete_15" "0,1" newline bitfld.long 0x150 14. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_14,Enable Set for pulse_vpac_out_4_en_utc0_complete_14" "0,1" newline bitfld.long 0x150 13. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_13,Enable Set for pulse_vpac_out_4_en_utc0_complete_13" "0,1" newline bitfld.long 0x150 12. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_12,Enable Set for pulse_vpac_out_4_en_utc0_complete_12" "0,1" newline bitfld.long 0x150 11. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_11,Enable Set for pulse_vpac_out_4_en_utc0_complete_11" "0,1" newline bitfld.long 0x150 10. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_10,Enable Set for pulse_vpac_out_4_en_utc0_complete_10" "0,1" newline bitfld.long 0x150 9. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_9,Enable Set for pulse_vpac_out_4_en_utc0_complete_9" "0,1" newline bitfld.long 0x150 8. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_8,Enable Set for pulse_vpac_out_4_en_utc0_complete_8" "0,1" newline bitfld.long 0x150 7. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_7,Enable Set for pulse_vpac_out_4_en_utc0_complete_7" "0,1" newline bitfld.long 0x150 6. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_6,Enable Set for pulse_vpac_out_4_en_utc0_complete_6" "0,1" newline bitfld.long 0x150 5. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_5,Enable Set for pulse_vpac_out_4_en_utc0_complete_5" "0,1" newline bitfld.long 0x150 4. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_4,Enable Set for pulse_vpac_out_4_en_utc0_complete_4" "0,1" newline bitfld.long 0x150 3. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_3,Enable Set for pulse_vpac_out_4_en_utc0_complete_3" "0,1" newline bitfld.long 0x150 2. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_2,Enable Set for pulse_vpac_out_4_en_utc0_complete_2" "0,1" newline bitfld.long 0x150 1. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_1,Enable Set for pulse_vpac_out_4_en_utc0_complete_1" "0,1" newline bitfld.long 0x150 0. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_0,Enable Set for pulse_vpac_out_4_en_utc0_complete_0" "0,1" line.long 0x154 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_4_5,Enable Register 85" bitfld.long 0x154 31. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_31,Enable Set for pulse_vpac_out_4_en_utc1_complete_31" "0,1" newline bitfld.long 0x154 30. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_30,Enable Set for pulse_vpac_out_4_en_utc1_complete_30" "0,1" newline bitfld.long 0x154 29. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_29,Enable Set for pulse_vpac_out_4_en_utc1_complete_29" "0,1" newline bitfld.long 0x154 28. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_28,Enable Set for pulse_vpac_out_4_en_utc1_complete_28" "0,1" newline bitfld.long 0x154 27. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_27,Enable Set for pulse_vpac_out_4_en_utc1_complete_27" "0,1" newline bitfld.long 0x154 26. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_26,Enable Set for pulse_vpac_out_4_en_utc1_complete_26" "0,1" newline bitfld.long 0x154 25. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_25,Enable Set for pulse_vpac_out_4_en_utc1_complete_25" "0,1" newline bitfld.long 0x154 24. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_24,Enable Set for pulse_vpac_out_4_en_utc1_complete_24" "0,1" newline bitfld.long 0x154 23. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_23,Enable Set for pulse_vpac_out_4_en_utc1_complete_23" "0,1" newline bitfld.long 0x154 22. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_22,Enable Set for pulse_vpac_out_4_en_utc1_complete_22" "0,1" newline bitfld.long 0x154 21. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_21,Enable Set for pulse_vpac_out_4_en_utc1_complete_21" "0,1" newline bitfld.long 0x154 20. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_20,Enable Set for pulse_vpac_out_4_en_utc1_complete_20" "0,1" newline bitfld.long 0x154 19. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_19,Enable Set for pulse_vpac_out_4_en_utc1_complete_19" "0,1" newline bitfld.long 0x154 18. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_18,Enable Set for pulse_vpac_out_4_en_utc1_complete_18" "0,1" newline bitfld.long 0x154 17. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_17,Enable Set for pulse_vpac_out_4_en_utc1_complete_17" "0,1" newline bitfld.long 0x154 16. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_16,Enable Set for pulse_vpac_out_4_en_utc1_complete_16" "0,1" newline bitfld.long 0x154 15. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_15,Enable Set for pulse_vpac_out_4_en_utc1_complete_15" "0,1" newline bitfld.long 0x154 14. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_14,Enable Set for pulse_vpac_out_4_en_utc1_complete_14" "0,1" newline bitfld.long 0x154 13. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_13,Enable Set for pulse_vpac_out_4_en_utc1_complete_13" "0,1" newline bitfld.long 0x154 12. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_12,Enable Set for pulse_vpac_out_4_en_utc1_complete_12" "0,1" newline bitfld.long 0x154 11. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_11,Enable Set for pulse_vpac_out_4_en_utc1_complete_11" "0,1" newline bitfld.long 0x154 10. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_10,Enable Set for pulse_vpac_out_4_en_utc1_complete_10" "0,1" newline bitfld.long 0x154 9. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_9,Enable Set for pulse_vpac_out_4_en_utc1_complete_9" "0,1" newline bitfld.long 0x154 8. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_8,Enable Set for pulse_vpac_out_4_en_utc1_complete_8" "0,1" newline bitfld.long 0x154 7. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_7,Enable Set for pulse_vpac_out_4_en_utc1_complete_7" "0,1" newline bitfld.long 0x154 6. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_6,Enable Set for pulse_vpac_out_4_en_utc1_complete_6" "0,1" newline bitfld.long 0x154 5. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_5,Enable Set for pulse_vpac_out_4_en_utc1_complete_5" "0,1" newline bitfld.long 0x154 4. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_4,Enable Set for pulse_vpac_out_4_en_utc1_complete_4" "0,1" newline bitfld.long 0x154 3. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_3,Enable Set for pulse_vpac_out_4_en_utc1_complete_3" "0,1" newline bitfld.long 0x154 2. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_2,Enable Set for pulse_vpac_out_4_en_utc1_complete_2" "0,1" newline bitfld.long 0x154 1. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_1,Enable Set for pulse_vpac_out_4_en_utc1_complete_1" "0,1" newline bitfld.long 0x154 0. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_0,Enable Set for pulse_vpac_out_4_en_utc1_complete_0" "0,1" line.long 0x158 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_4_6,Enable Register 86" bitfld.long 0x158 31. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_63,Enable Set for pulse_vpac_out_4_en_utc1_complete_63" "0,1" newline bitfld.long 0x158 30. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_62,Enable Set for pulse_vpac_out_4_en_utc1_complete_62" "0,1" newline bitfld.long 0x158 29. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_61,Enable Set for pulse_vpac_out_4_en_utc1_complete_61" "0,1" newline bitfld.long 0x158 28. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_60,Enable Set for pulse_vpac_out_4_en_utc1_complete_60" "0,1" newline bitfld.long 0x158 27. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_59,Enable Set for pulse_vpac_out_4_en_utc1_complete_59" "0,1" newline bitfld.long 0x158 26. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_58,Enable Set for pulse_vpac_out_4_en_utc1_complete_58" "0,1" newline bitfld.long 0x158 25. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_57,Enable Set for pulse_vpac_out_4_en_utc1_complete_57" "0,1" newline bitfld.long 0x158 24. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_56,Enable Set for pulse_vpac_out_4_en_utc1_complete_56" "0,1" newline bitfld.long 0x158 23. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_55,Enable Set for pulse_vpac_out_4_en_utc1_complete_55" "0,1" newline bitfld.long 0x158 22. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_54,Enable Set for pulse_vpac_out_4_en_utc1_complete_54" "0,1" newline bitfld.long 0x158 21. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_53,Enable Set for pulse_vpac_out_4_en_utc1_complete_53" "0,1" newline bitfld.long 0x158 20. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_52,Enable Set for pulse_vpac_out_4_en_utc1_complete_52" "0,1" newline bitfld.long 0x158 19. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_51,Enable Set for pulse_vpac_out_4_en_utc1_complete_51" "0,1" newline bitfld.long 0x158 18. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_50,Enable Set for pulse_vpac_out_4_en_utc1_complete_50" "0,1" newline bitfld.long 0x158 17. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_49,Enable Set for pulse_vpac_out_4_en_utc1_complete_49" "0,1" newline bitfld.long 0x158 16. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_48,Enable Set for pulse_vpac_out_4_en_utc1_complete_48" "0,1" newline bitfld.long 0x158 15. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_47,Enable Set for pulse_vpac_out_4_en_utc1_complete_47" "0,1" newline bitfld.long 0x158 14. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_46,Enable Set for pulse_vpac_out_4_en_utc1_complete_46" "0,1" newline bitfld.long 0x158 13. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_45,Enable Set for pulse_vpac_out_4_en_utc1_complete_45" "0,1" newline bitfld.long 0x158 12. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_44,Enable Set for pulse_vpac_out_4_en_utc1_complete_44" "0,1" newline bitfld.long 0x158 11. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_43,Enable Set for pulse_vpac_out_4_en_utc1_complete_43" "0,1" newline bitfld.long 0x158 10. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_42,Enable Set for pulse_vpac_out_4_en_utc1_complete_42" "0,1" newline bitfld.long 0x158 9. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_41,Enable Set for pulse_vpac_out_4_en_utc1_complete_41" "0,1" newline bitfld.long 0x158 8. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_40,Enable Set for pulse_vpac_out_4_en_utc1_complete_40" "0,1" newline bitfld.long 0x158 7. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_39,Enable Set for pulse_vpac_out_4_en_utc1_complete_39" "0,1" newline bitfld.long 0x158 6. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_38,Enable Set for pulse_vpac_out_4_en_utc1_complete_38" "0,1" newline bitfld.long 0x158 5. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_37,Enable Set for pulse_vpac_out_4_en_utc1_complete_37" "0,1" newline bitfld.long 0x158 4. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_36,Enable Set for pulse_vpac_out_4_en_utc1_complete_36" "0,1" newline bitfld.long 0x158 3. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_35,Enable Set for pulse_vpac_out_4_en_utc1_complete_35" "0,1" newline bitfld.long 0x158 2. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_34,Enable Set for pulse_vpac_out_4_en_utc1_complete_34" "0,1" newline bitfld.long 0x158 1. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_33,Enable Set for pulse_vpac_out_4_en_utc1_complete_33" "0,1" newline bitfld.long 0x158 0. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_32,Enable Set for pulse_vpac_out_4_en_utc1_complete_32" "0,1" line.long 0x15C "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_4_7,Enable Register 87" bitfld.long 0x15C 4. "ENABLE_PULSE_VPAC_OUT_4_EN_CTM_PULSE,Enable Set for pulse_vpac_out_4_en_ctm_pulse" "0,1" newline bitfld.long 0x15C 3. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_PROT_ERR,Enable Set for pulse_vpac_out_4_en_utc1_prot_err" "0,1" newline bitfld.long 0x15C 2. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_PROT_ERR,Enable Set for pulse_vpac_out_4_en_utc0_prot_err" "0,1" newline bitfld.long 0x15C 1. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_ERROR,Enable Set for pulse_vpac_out_4_en_utc1_error" "0,1" newline bitfld.long 0x15C 0. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_ERROR,Enable Set for pulse_vpac_out_4_en_utc0_error" "0,1" line.long 0x160 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_5_0,Enable Register 88" bitfld.long 0x160 26. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_CR_CFG_ERR,Enable Set for pulse_vpac_out_5_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x160 25. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for pulse_vpac_out_5_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x160 24. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for pulse_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x160 23. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for pulse_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x160 22. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x160 21. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x160 20. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for pulse_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x160 19. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for pulse_vpac_out_5_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x160 18. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_EE_CFG_ERR,Enable Set for pulse_vpac_out_5_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x160 17. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for pulse_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x160 16. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for pulse_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x160 15. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCC_CFG_ERR,Enable Set for pulse_vpac_out_5_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x160 14. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCFA_CFG_ERR,Enable Set for pulse_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x160 13. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_VP_ERR,Enable Set for pulse_vpac_out_5_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x160 12. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for pulse_vpac_out_5_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x160 11. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for pulse_vpac_out_5_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x160 10. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_DONE,Enable Set for pulse_vpac_out_5_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x160 9. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_START,Enable Set for pulse_vpac_out_5_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x160 8. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_CFG_ERR,Enable Set for pulse_vpac_out_5_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x160 7. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for pulse_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x160 6. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for pulse_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x160 5. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for pulse_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x160 4. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for pulse_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x160 3. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for pulse_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x160 2. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_AF_PULSE,Enable Set for pulse_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x160 1. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for pulse_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x160 0. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_CFG_ERR,Enable Set for pulse_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1" line.long 0x164 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_5_1,Enable Register 89" bitfld.long 0x164 8. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_VBUSM_RD_ERR,Enable Set for pulse_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x164 7. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_SL2_WR_ERR,Enable Set for pulse_vpac_out_5_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x164 6. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_FR_DONE_EVT,Enable Set for pulse_vpac_out_5_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x164 5. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_INT_SZOVF,Enable Set for pulse_vpac_out_5_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x164 4. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_IFR_OUTOFBOUND,Enable Set for pulse_vpac_out_5_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x164 3. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for pulse_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x164 2. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for pulse_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x164 1. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x164 0. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x168 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_5_2,Enable Register 90" bitfld.long 0x168 10. "ENABLE_PULSE_VPAC_OUT_5_EN_NF_SL2_RD_ERR,Enable Set for pulse_vpac_out_5_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x168 9. "ENABLE_PULSE_VPAC_OUT_5_EN_NF_SL2_WR_ERR,Enable Set for pulse_vpac_out_5_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x168 8. "ENABLE_PULSE_VPAC_OUT_5_EN_NF_FRAME_DONE,Enable Set for pulse_vpac_out_5_en_nf_frame_done" "0,1" newline bitfld.long 0x168 3. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x168 2. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x168 1. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for pulse_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x168 0. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for pulse_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x16C "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_5_3,Enable Register 91" bitfld.long 0x16C 26. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_6,Enable Set for pulse_vpac_out_5_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x16C 25. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_5,Enable Set for pulse_vpac_out_5_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x16C 24. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_4,Enable Set for pulse_vpac_out_5_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x16C 22. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_2,Enable Set for pulse_vpac_out_5_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x16C 20. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_vpac_out_5_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x16C 19. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_1_LEVEL,Enable Set for pulse_vpac_out_5_en_spare_pend_1_level" "0,1" newline bitfld.long 0x16C 18. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_1_PULSE,Enable Set for pulse_vpac_out_5_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x16C 17. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_0_LEVEL,Enable Set for pulse_vpac_out_5_en_spare_pend_0_level" "0,1" newline bitfld.long 0x16C 16. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_0_PULSE,Enable Set for pulse_vpac_out_5_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x16C 15. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_DEC_1,Enable Set for pulse_vpac_out_5_en_spare_dec_1" "0,1" newline bitfld.long 0x16C 14. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_DEC_0,Enable Set for pulse_vpac_out_5_en_spare_dec_0" "0,1" newline bitfld.long 0x16C 13. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_6,Enable Set for pulse_vpac_out_5_en_tdone_6" "0,1" newline bitfld.long 0x16C 12. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_5,Enable Set for pulse_vpac_out_5_en_tdone_5" "0,1" newline bitfld.long 0x16C 11. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_4,Enable Set for pulse_vpac_out_5_en_tdone_4" "0,1" newline bitfld.long 0x16C 9. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_2,Enable Set for pulse_vpac_out_5_en_tdone_2" "0,1" newline bitfld.long 0x16C 7. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_0,Enable Set for pulse_vpac_out_5_en_tdone_0" "0,1" newline bitfld.long 0x16C 6. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_6,Enable Set for pulse_vpac_out_5_en_pipe_done_6" "0,1" newline bitfld.long 0x16C 5. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_5,Enable Set for pulse_vpac_out_5_en_pipe_done_5" "0,1" newline bitfld.long 0x16C 4. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_4,Enable Set for pulse_vpac_out_5_en_pipe_done_4" "0,1" newline bitfld.long 0x16C 3. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_3,Enable Set for pulse_vpac_out_5_en_pipe_done_3" "0,1" newline bitfld.long 0x16C 2. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_2,Enable Set for pulse_vpac_out_5_en_pipe_done_2" "0,1" newline bitfld.long 0x16C 1. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_1,Enable Set for pulse_vpac_out_5_en_pipe_done_1" "0,1" newline bitfld.long 0x16C 0. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_0,Enable Set for pulse_vpac_out_5_en_pipe_done_0" "0,1" line.long 0x170 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_5_4,Enable Register 92" bitfld.long 0x170 31. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_31,Enable Set for pulse_vpac_out_5_en_utc0_complete_31" "0,1" newline bitfld.long 0x170 30. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_30,Enable Set for pulse_vpac_out_5_en_utc0_complete_30" "0,1" newline bitfld.long 0x170 29. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_29,Enable Set for pulse_vpac_out_5_en_utc0_complete_29" "0,1" newline bitfld.long 0x170 28. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_28,Enable Set for pulse_vpac_out_5_en_utc0_complete_28" "0,1" newline bitfld.long 0x170 27. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_27,Enable Set for pulse_vpac_out_5_en_utc0_complete_27" "0,1" newline bitfld.long 0x170 26. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_26,Enable Set for pulse_vpac_out_5_en_utc0_complete_26" "0,1" newline bitfld.long 0x170 25. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_25,Enable Set for pulse_vpac_out_5_en_utc0_complete_25" "0,1" newline bitfld.long 0x170 24. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_24,Enable Set for pulse_vpac_out_5_en_utc0_complete_24" "0,1" newline bitfld.long 0x170 23. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_23,Enable Set for pulse_vpac_out_5_en_utc0_complete_23" "0,1" newline bitfld.long 0x170 22. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_22,Enable Set for pulse_vpac_out_5_en_utc0_complete_22" "0,1" newline bitfld.long 0x170 21. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_21,Enable Set for pulse_vpac_out_5_en_utc0_complete_21" "0,1" newline bitfld.long 0x170 20. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_20,Enable Set for pulse_vpac_out_5_en_utc0_complete_20" "0,1" newline bitfld.long 0x170 19. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_19,Enable Set for pulse_vpac_out_5_en_utc0_complete_19" "0,1" newline bitfld.long 0x170 18. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_18,Enable Set for pulse_vpac_out_5_en_utc0_complete_18" "0,1" newline bitfld.long 0x170 17. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_17,Enable Set for pulse_vpac_out_5_en_utc0_complete_17" "0,1" newline bitfld.long 0x170 16. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_16,Enable Set for pulse_vpac_out_5_en_utc0_complete_16" "0,1" newline bitfld.long 0x170 15. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_15,Enable Set for pulse_vpac_out_5_en_utc0_complete_15" "0,1" newline bitfld.long 0x170 14. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_14,Enable Set for pulse_vpac_out_5_en_utc0_complete_14" "0,1" newline bitfld.long 0x170 13. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_13,Enable Set for pulse_vpac_out_5_en_utc0_complete_13" "0,1" newline bitfld.long 0x170 12. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_12,Enable Set for pulse_vpac_out_5_en_utc0_complete_12" "0,1" newline bitfld.long 0x170 11. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_11,Enable Set for pulse_vpac_out_5_en_utc0_complete_11" "0,1" newline bitfld.long 0x170 10. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_10,Enable Set for pulse_vpac_out_5_en_utc0_complete_10" "0,1" newline bitfld.long 0x170 9. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_9,Enable Set for pulse_vpac_out_5_en_utc0_complete_9" "0,1" newline bitfld.long 0x170 8. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_8,Enable Set for pulse_vpac_out_5_en_utc0_complete_8" "0,1" newline bitfld.long 0x170 7. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_7,Enable Set for pulse_vpac_out_5_en_utc0_complete_7" "0,1" newline bitfld.long 0x170 6. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_6,Enable Set for pulse_vpac_out_5_en_utc0_complete_6" "0,1" newline bitfld.long 0x170 5. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_5,Enable Set for pulse_vpac_out_5_en_utc0_complete_5" "0,1" newline bitfld.long 0x170 4. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_4,Enable Set for pulse_vpac_out_5_en_utc0_complete_4" "0,1" newline bitfld.long 0x170 3. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_3,Enable Set for pulse_vpac_out_5_en_utc0_complete_3" "0,1" newline bitfld.long 0x170 2. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_2,Enable Set for pulse_vpac_out_5_en_utc0_complete_2" "0,1" newline bitfld.long 0x170 1. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_1,Enable Set for pulse_vpac_out_5_en_utc0_complete_1" "0,1" newline bitfld.long 0x170 0. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_0,Enable Set for pulse_vpac_out_5_en_utc0_complete_0" "0,1" line.long 0x174 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_5_5,Enable Register 93" bitfld.long 0x174 31. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_31,Enable Set for pulse_vpac_out_5_en_utc1_complete_31" "0,1" newline bitfld.long 0x174 30. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_30,Enable Set for pulse_vpac_out_5_en_utc1_complete_30" "0,1" newline bitfld.long 0x174 29. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_29,Enable Set for pulse_vpac_out_5_en_utc1_complete_29" "0,1" newline bitfld.long 0x174 28. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_28,Enable Set for pulse_vpac_out_5_en_utc1_complete_28" "0,1" newline bitfld.long 0x174 27. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_27,Enable Set for pulse_vpac_out_5_en_utc1_complete_27" "0,1" newline bitfld.long 0x174 26. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_26,Enable Set for pulse_vpac_out_5_en_utc1_complete_26" "0,1" newline bitfld.long 0x174 25. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_25,Enable Set for pulse_vpac_out_5_en_utc1_complete_25" "0,1" newline bitfld.long 0x174 24. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_24,Enable Set for pulse_vpac_out_5_en_utc1_complete_24" "0,1" newline bitfld.long 0x174 23. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_23,Enable Set for pulse_vpac_out_5_en_utc1_complete_23" "0,1" newline bitfld.long 0x174 22. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_22,Enable Set for pulse_vpac_out_5_en_utc1_complete_22" "0,1" newline bitfld.long 0x174 21. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_21,Enable Set for pulse_vpac_out_5_en_utc1_complete_21" "0,1" newline bitfld.long 0x174 20. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_20,Enable Set for pulse_vpac_out_5_en_utc1_complete_20" "0,1" newline bitfld.long 0x174 19. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_19,Enable Set for pulse_vpac_out_5_en_utc1_complete_19" "0,1" newline bitfld.long 0x174 18. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_18,Enable Set for pulse_vpac_out_5_en_utc1_complete_18" "0,1" newline bitfld.long 0x174 17. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_17,Enable Set for pulse_vpac_out_5_en_utc1_complete_17" "0,1" newline bitfld.long 0x174 16. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_16,Enable Set for pulse_vpac_out_5_en_utc1_complete_16" "0,1" newline bitfld.long 0x174 15. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_15,Enable Set for pulse_vpac_out_5_en_utc1_complete_15" "0,1" newline bitfld.long 0x174 14. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_14,Enable Set for pulse_vpac_out_5_en_utc1_complete_14" "0,1" newline bitfld.long 0x174 13. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_13,Enable Set for pulse_vpac_out_5_en_utc1_complete_13" "0,1" newline bitfld.long 0x174 12. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_12,Enable Set for pulse_vpac_out_5_en_utc1_complete_12" "0,1" newline bitfld.long 0x174 11. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_11,Enable Set for pulse_vpac_out_5_en_utc1_complete_11" "0,1" newline bitfld.long 0x174 10. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_10,Enable Set for pulse_vpac_out_5_en_utc1_complete_10" "0,1" newline bitfld.long 0x174 9. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_9,Enable Set for pulse_vpac_out_5_en_utc1_complete_9" "0,1" newline bitfld.long 0x174 8. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_8,Enable Set for pulse_vpac_out_5_en_utc1_complete_8" "0,1" newline bitfld.long 0x174 7. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_7,Enable Set for pulse_vpac_out_5_en_utc1_complete_7" "0,1" newline bitfld.long 0x174 6. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_6,Enable Set for pulse_vpac_out_5_en_utc1_complete_6" "0,1" newline bitfld.long 0x174 5. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_5,Enable Set for pulse_vpac_out_5_en_utc1_complete_5" "0,1" newline bitfld.long 0x174 4. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_4,Enable Set for pulse_vpac_out_5_en_utc1_complete_4" "0,1" newline bitfld.long 0x174 3. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_3,Enable Set for pulse_vpac_out_5_en_utc1_complete_3" "0,1" newline bitfld.long 0x174 2. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_2,Enable Set for pulse_vpac_out_5_en_utc1_complete_2" "0,1" newline bitfld.long 0x174 1. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_1,Enable Set for pulse_vpac_out_5_en_utc1_complete_1" "0,1" newline bitfld.long 0x174 0. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_0,Enable Set for pulse_vpac_out_5_en_utc1_complete_0" "0,1" line.long 0x178 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_5_6,Enable Register 94" bitfld.long 0x178 31. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_63,Enable Set for pulse_vpac_out_5_en_utc1_complete_63" "0,1" newline bitfld.long 0x178 30. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_62,Enable Set for pulse_vpac_out_5_en_utc1_complete_62" "0,1" newline bitfld.long 0x178 29. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_61,Enable Set for pulse_vpac_out_5_en_utc1_complete_61" "0,1" newline bitfld.long 0x178 28. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_60,Enable Set for pulse_vpac_out_5_en_utc1_complete_60" "0,1" newline bitfld.long 0x178 27. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_59,Enable Set for pulse_vpac_out_5_en_utc1_complete_59" "0,1" newline bitfld.long 0x178 26. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_58,Enable Set for pulse_vpac_out_5_en_utc1_complete_58" "0,1" newline bitfld.long 0x178 25. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_57,Enable Set for pulse_vpac_out_5_en_utc1_complete_57" "0,1" newline bitfld.long 0x178 24. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_56,Enable Set for pulse_vpac_out_5_en_utc1_complete_56" "0,1" newline bitfld.long 0x178 23. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_55,Enable Set for pulse_vpac_out_5_en_utc1_complete_55" "0,1" newline bitfld.long 0x178 22. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_54,Enable Set for pulse_vpac_out_5_en_utc1_complete_54" "0,1" newline bitfld.long 0x178 21. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_53,Enable Set for pulse_vpac_out_5_en_utc1_complete_53" "0,1" newline bitfld.long 0x178 20. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_52,Enable Set for pulse_vpac_out_5_en_utc1_complete_52" "0,1" newline bitfld.long 0x178 19. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_51,Enable Set for pulse_vpac_out_5_en_utc1_complete_51" "0,1" newline bitfld.long 0x178 18. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_50,Enable Set for pulse_vpac_out_5_en_utc1_complete_50" "0,1" newline bitfld.long 0x178 17. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_49,Enable Set for pulse_vpac_out_5_en_utc1_complete_49" "0,1" newline bitfld.long 0x178 16. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_48,Enable Set for pulse_vpac_out_5_en_utc1_complete_48" "0,1" newline bitfld.long 0x178 15. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_47,Enable Set for pulse_vpac_out_5_en_utc1_complete_47" "0,1" newline bitfld.long 0x178 14. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_46,Enable Set for pulse_vpac_out_5_en_utc1_complete_46" "0,1" newline bitfld.long 0x178 13. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_45,Enable Set for pulse_vpac_out_5_en_utc1_complete_45" "0,1" newline bitfld.long 0x178 12. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_44,Enable Set for pulse_vpac_out_5_en_utc1_complete_44" "0,1" newline bitfld.long 0x178 11. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_43,Enable Set for pulse_vpac_out_5_en_utc1_complete_43" "0,1" newline bitfld.long 0x178 10. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_42,Enable Set for pulse_vpac_out_5_en_utc1_complete_42" "0,1" newline bitfld.long 0x178 9. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_41,Enable Set for pulse_vpac_out_5_en_utc1_complete_41" "0,1" newline bitfld.long 0x178 8. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_40,Enable Set for pulse_vpac_out_5_en_utc1_complete_40" "0,1" newline bitfld.long 0x178 7. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_39,Enable Set for pulse_vpac_out_5_en_utc1_complete_39" "0,1" newline bitfld.long 0x178 6. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_38,Enable Set for pulse_vpac_out_5_en_utc1_complete_38" "0,1" newline bitfld.long 0x178 5. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_37,Enable Set for pulse_vpac_out_5_en_utc1_complete_37" "0,1" newline bitfld.long 0x178 4. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_36,Enable Set for pulse_vpac_out_5_en_utc1_complete_36" "0,1" newline bitfld.long 0x178 3. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_35,Enable Set for pulse_vpac_out_5_en_utc1_complete_35" "0,1" newline bitfld.long 0x178 2. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_34,Enable Set for pulse_vpac_out_5_en_utc1_complete_34" "0,1" newline bitfld.long 0x178 1. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_33,Enable Set for pulse_vpac_out_5_en_utc1_complete_33" "0,1" newline bitfld.long 0x178 0. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_32,Enable Set for pulse_vpac_out_5_en_utc1_complete_32" "0,1" line.long 0x17C "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_5_7,Enable Register 95" bitfld.long 0x17C 4. "ENABLE_PULSE_VPAC_OUT_5_EN_CTM_PULSE,Enable Set for pulse_vpac_out_5_en_ctm_pulse" "0,1" newline bitfld.long 0x17C 3. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_PROT_ERR,Enable Set for pulse_vpac_out_5_en_utc1_prot_err" "0,1" newline bitfld.long 0x17C 2. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_PROT_ERR,Enable Set for pulse_vpac_out_5_en_utc0_prot_err" "0,1" newline bitfld.long 0x17C 1. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_ERROR,Enable Set for pulse_vpac_out_5_en_utc1_error" "0,1" newline bitfld.long 0x17C 0. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_ERROR,Enable Set for pulse_vpac_out_5_en_utc0_error" "0,1" rgroup.long 0x300++0x17F line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_0_0,Enable Clear Register 0" bitfld.long 0x0 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x0 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for level_vpac_out_0_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x0 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for level_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x0 23. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x0 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x0 21. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x0 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x0 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x0 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x0 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x0 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x0 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x0 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x0 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x0 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x0 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x0 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for level_vpac_out_0_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x0 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for level_vpac_out_0_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x0 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x0 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x0 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x0 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x0 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for level_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x0 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for level_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x0 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for level_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x0 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for level_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x0 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_0_1,Enable Clear Register 1" bitfld.long 0x4 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for level_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x4 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_0_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x4 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_0_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x4 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_INT_SZOVF_CLR,Enable Clear for level_vpac_out_0_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x4 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_0_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x4 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x4 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x4 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x4 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x8 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_0_2,Enable Clear Register 2" bitfld.long 0x8 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_NF_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_0_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x8 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_NF_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_0_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x8 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_NF_FRAME_DONE_CLR,Enable Clear for level_vpac_out_0_en_nf_frame_done" "0,1" newline bitfld.long 0x8 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x8 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x8 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for level_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x8 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for level_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xC "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_0_3,Enable Clear Register 3" bitfld.long 0xC 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for level_vpac_out_0_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xC 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for level_vpac_out_0_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xC 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for level_vpac_out_0_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xC 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for level_vpac_out_0_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xC 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_vpac_out_0_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xC 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for level_vpac_out_0_en_spare_pend_1_level" "0,1" newline bitfld.long 0xC 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for level_vpac_out_0_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0xC 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for level_vpac_out_0_en_spare_pend_0_level" "0,1" newline bitfld.long 0xC 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for level_vpac_out_0_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xC 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_DEC_1_CLR,Enable Clear for level_vpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0xC 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_DEC_0_CLR,Enable Clear for level_vpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0xC 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_6_CLR,Enable Clear for level_vpac_out_0_en_tdone_6" "0,1" newline bitfld.long 0xC 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_5_CLR,Enable Clear for level_vpac_out_0_en_tdone_5" "0,1" newline bitfld.long 0xC 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_4_CLR,Enable Clear for level_vpac_out_0_en_tdone_4" "0,1" newline bitfld.long 0xC 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_2_CLR,Enable Clear for level_vpac_out_0_en_tdone_2" "0,1" newline bitfld.long 0xC 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_0_CLR,Enable Clear for level_vpac_out_0_en_tdone_0" "0,1" newline bitfld.long 0xC 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_6_CLR,Enable Clear for level_vpac_out_0_en_pipe_done_6" "0,1" newline bitfld.long 0xC 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_5_CLR,Enable Clear for level_vpac_out_0_en_pipe_done_5" "0,1" newline bitfld.long 0xC 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_4_CLR,Enable Clear for level_vpac_out_0_en_pipe_done_4" "0,1" newline bitfld.long 0xC 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_3_CLR,Enable Clear for level_vpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0xC 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_2_CLR,Enable Clear for level_vpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0xC 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_1_CLR,Enable Clear for level_vpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0xC 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_0_CLR,Enable Clear for level_vpac_out_0_en_pipe_done_0" "0,1" line.long 0x10 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_0_4,Enable Clear Register 4" bitfld.long 0x10 31. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_31_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_31" "0,1" newline bitfld.long 0x10 30. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_30_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_30" "0,1" newline bitfld.long 0x10 29. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_29_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_29" "0,1" newline bitfld.long 0x10 28. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_28_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_28" "0,1" newline bitfld.long 0x10 27. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_27_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_27" "0,1" newline bitfld.long 0x10 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_26_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_26" "0,1" newline bitfld.long 0x10 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_25_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_25" "0,1" newline bitfld.long 0x10 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_24_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_24" "0,1" newline bitfld.long 0x10 23. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_23_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_23" "0,1" newline bitfld.long 0x10 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_22_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_22" "0,1" newline bitfld.long 0x10 21. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_21_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_21" "0,1" newline bitfld.long 0x10 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_20_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_20" "0,1" newline bitfld.long 0x10 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_19_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_19" "0,1" newline bitfld.long 0x10 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_18_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_18" "0,1" newline bitfld.long 0x10 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_17_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_17" "0,1" newline bitfld.long 0x10 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_16_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_16" "0,1" newline bitfld.long 0x10 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_15_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_15" "0,1" newline bitfld.long 0x10 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_14_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_14" "0,1" newline bitfld.long 0x10 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_13_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_13" "0,1" newline bitfld.long 0x10 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_12_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_12" "0,1" newline bitfld.long 0x10 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_11_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_11" "0,1" newline bitfld.long 0x10 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_10_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_10" "0,1" newline bitfld.long 0x10 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_9_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_9" "0,1" newline bitfld.long 0x10 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_8_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_8" "0,1" newline bitfld.long 0x10 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_7_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_7" "0,1" newline bitfld.long 0x10 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_6_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_6" "0,1" newline bitfld.long 0x10 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_5_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_5" "0,1" newline bitfld.long 0x10 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_4_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_4" "0,1" newline bitfld.long 0x10 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_3_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_3" "0,1" newline bitfld.long 0x10 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_2_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_2" "0,1" newline bitfld.long 0x10 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_1_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_1" "0,1" newline bitfld.long 0x10 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_0_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_0" "0,1" line.long 0x14 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_0_5,Enable Clear Register 5" bitfld.long 0x14 31. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_31_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_31" "0,1" newline bitfld.long 0x14 30. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_30_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_30" "0,1" newline bitfld.long 0x14 29. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_29_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_29" "0,1" newline bitfld.long 0x14 28. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_28_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_28" "0,1" newline bitfld.long 0x14 27. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_27_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_27" "0,1" newline bitfld.long 0x14 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_26_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_26" "0,1" newline bitfld.long 0x14 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_25_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_25" "0,1" newline bitfld.long 0x14 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_24_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_24" "0,1" newline bitfld.long 0x14 23. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_23_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_23" "0,1" newline bitfld.long 0x14 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_22_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_22" "0,1" newline bitfld.long 0x14 21. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_21_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_21" "0,1" newline bitfld.long 0x14 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_20_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_20" "0,1" newline bitfld.long 0x14 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_19_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_19" "0,1" newline bitfld.long 0x14 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_18_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_18" "0,1" newline bitfld.long 0x14 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_17_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_17" "0,1" newline bitfld.long 0x14 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_16_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_16" "0,1" newline bitfld.long 0x14 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_15_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_15" "0,1" newline bitfld.long 0x14 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_14_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_14" "0,1" newline bitfld.long 0x14 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_13_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_13" "0,1" newline bitfld.long 0x14 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_12_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_12" "0,1" newline bitfld.long 0x14 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_11_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_11" "0,1" newline bitfld.long 0x14 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_10_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_10" "0,1" newline bitfld.long 0x14 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_9_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_9" "0,1" newline bitfld.long 0x14 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_8_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_8" "0,1" newline bitfld.long 0x14 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_7_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_7" "0,1" newline bitfld.long 0x14 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_6_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_6" "0,1" newline bitfld.long 0x14 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_5_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_5" "0,1" newline bitfld.long 0x14 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_4_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_4" "0,1" newline bitfld.long 0x14 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_3_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_3" "0,1" newline bitfld.long 0x14 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_2_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_2" "0,1" newline bitfld.long 0x14 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_1_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_1" "0,1" newline bitfld.long 0x14 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_0_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_0" "0,1" line.long 0x18 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_0_6,Enable Clear Register 6" bitfld.long 0x18 31. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_63_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_63" "0,1" newline bitfld.long 0x18 30. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_62_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_62" "0,1" newline bitfld.long 0x18 29. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_61_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_61" "0,1" newline bitfld.long 0x18 28. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_60_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_60" "0,1" newline bitfld.long 0x18 27. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_59_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_59" "0,1" newline bitfld.long 0x18 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_58_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_58" "0,1" newline bitfld.long 0x18 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_57_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_57" "0,1" newline bitfld.long 0x18 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_56_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_56" "0,1" newline bitfld.long 0x18 23. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_55_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_55" "0,1" newline bitfld.long 0x18 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_54_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_54" "0,1" newline bitfld.long 0x18 21. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_53_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_53" "0,1" newline bitfld.long 0x18 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_52_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_52" "0,1" newline bitfld.long 0x18 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_51_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_51" "0,1" newline bitfld.long 0x18 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_50_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_50" "0,1" newline bitfld.long 0x18 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_49_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_49" "0,1" newline bitfld.long 0x18 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_48_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_48" "0,1" newline bitfld.long 0x18 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_47_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_47" "0,1" newline bitfld.long 0x18 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_46_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_46" "0,1" newline bitfld.long 0x18 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_45_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_45" "0,1" newline bitfld.long 0x18 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_44_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_44" "0,1" newline bitfld.long 0x18 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_43_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_43" "0,1" newline bitfld.long 0x18 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_42_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_42" "0,1" newline bitfld.long 0x18 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_41_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_41" "0,1" newline bitfld.long 0x18 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_40_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_40" "0,1" newline bitfld.long 0x18 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_39_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_39" "0,1" newline bitfld.long 0x18 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_38_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_38" "0,1" newline bitfld.long 0x18 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_37_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_37" "0,1" newline bitfld.long 0x18 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_36_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_36" "0,1" newline bitfld.long 0x18 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_35_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_35" "0,1" newline bitfld.long 0x18 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_34_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_34" "0,1" newline bitfld.long 0x18 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_33_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_33" "0,1" newline bitfld.long 0x18 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_32_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_32" "0,1" line.long 0x1C "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_0_7,Enable Clear Register 7" bitfld.long 0x1C 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_CTM_PULSE_CLR,Enable Clear for level_vpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0x1C 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_PROT_ERR_CLR,Enable Clear for level_vpac_out_0_en_utc1_prot_err" "0,1" newline bitfld.long 0x1C 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_PROT_ERR_CLR,Enable Clear for level_vpac_out_0_en_utc0_prot_err" "0,1" newline bitfld.long 0x1C 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_ERROR_CLR,Enable Clear for level_vpac_out_0_en_utc1_error" "0,1" newline bitfld.long 0x1C 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_ERROR_CLR,Enable Clear for level_vpac_out_0_en_utc0_error" "0,1" line.long 0x20 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_1_0,Enable Clear Register 8" bitfld.long 0x20 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x20 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for level_vpac_out_1_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x20 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for level_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x20 23. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x20 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x20 21. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x20 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x20 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x20 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x20 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x20 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x20 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x20 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x20 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x20 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x20 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x20 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for level_vpac_out_1_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x20 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for level_vpac_out_1_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x20 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x20 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x20 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x20 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x20 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for level_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x20 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for level_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x20 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for level_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x20 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for level_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x20 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1" line.long 0x24 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_1_1,Enable Clear Register 9" bitfld.long 0x24 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for level_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x24 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_1_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x24 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_1_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x24 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_INT_SZOVF_CLR,Enable Clear for level_vpac_out_1_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x24 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_1_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x24 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x24 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x24 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x24 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x28 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_1_2,Enable Clear Register 10" bitfld.long 0x28 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_NF_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_1_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x28 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_NF_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_1_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x28 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_NF_FRAME_DONE_CLR,Enable Clear for level_vpac_out_1_en_nf_frame_done" "0,1" newline bitfld.long 0x28 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x28 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x28 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for level_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x28 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for level_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x2C "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_1_3,Enable Clear Register 11" bitfld.long 0x2C 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for level_vpac_out_1_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x2C 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for level_vpac_out_1_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x2C 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for level_vpac_out_1_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x2C 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for level_vpac_out_1_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x2C 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_vpac_out_1_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x2C 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for level_vpac_out_1_en_spare_pend_1_level" "0,1" newline bitfld.long 0x2C 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for level_vpac_out_1_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x2C 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for level_vpac_out_1_en_spare_pend_0_level" "0,1" newline bitfld.long 0x2C 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for level_vpac_out_1_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x2C 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_DEC_1_CLR,Enable Clear for level_vpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0x2C 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_DEC_0_CLR,Enable Clear for level_vpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0x2C 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_6_CLR,Enable Clear for level_vpac_out_1_en_tdone_6" "0,1" newline bitfld.long 0x2C 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_5_CLR,Enable Clear for level_vpac_out_1_en_tdone_5" "0,1" newline bitfld.long 0x2C 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_4_CLR,Enable Clear for level_vpac_out_1_en_tdone_4" "0,1" newline bitfld.long 0x2C 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_2_CLR,Enable Clear for level_vpac_out_1_en_tdone_2" "0,1" newline bitfld.long 0x2C 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_0_CLR,Enable Clear for level_vpac_out_1_en_tdone_0" "0,1" newline bitfld.long 0x2C 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_6_CLR,Enable Clear for level_vpac_out_1_en_pipe_done_6" "0,1" newline bitfld.long 0x2C 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_5_CLR,Enable Clear for level_vpac_out_1_en_pipe_done_5" "0,1" newline bitfld.long 0x2C 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_4_CLR,Enable Clear for level_vpac_out_1_en_pipe_done_4" "0,1" newline bitfld.long 0x2C 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_3_CLR,Enable Clear for level_vpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0x2C 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_2_CLR,Enable Clear for level_vpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0x2C 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_1_CLR,Enable Clear for level_vpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0x2C 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_0_CLR,Enable Clear for level_vpac_out_1_en_pipe_done_0" "0,1" line.long 0x30 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_1_4,Enable Clear Register 12" bitfld.long 0x30 31. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_31_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_31" "0,1" newline bitfld.long 0x30 30. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_30_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_30" "0,1" newline bitfld.long 0x30 29. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_29_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_29" "0,1" newline bitfld.long 0x30 28. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_28_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_28" "0,1" newline bitfld.long 0x30 27. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_27_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_27" "0,1" newline bitfld.long 0x30 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_26_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_26" "0,1" newline bitfld.long 0x30 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_25_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_25" "0,1" newline bitfld.long 0x30 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_24_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_24" "0,1" newline bitfld.long 0x30 23. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_23_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_23" "0,1" newline bitfld.long 0x30 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_22_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_22" "0,1" newline bitfld.long 0x30 21. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_21_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_21" "0,1" newline bitfld.long 0x30 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_20_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_20" "0,1" newline bitfld.long 0x30 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_19_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_19" "0,1" newline bitfld.long 0x30 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_18_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_18" "0,1" newline bitfld.long 0x30 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_17_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_17" "0,1" newline bitfld.long 0x30 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_16_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_16" "0,1" newline bitfld.long 0x30 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_15_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_15" "0,1" newline bitfld.long 0x30 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_14_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_14" "0,1" newline bitfld.long 0x30 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_13_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_13" "0,1" newline bitfld.long 0x30 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_12_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_12" "0,1" newline bitfld.long 0x30 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_11_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_11" "0,1" newline bitfld.long 0x30 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_10_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_10" "0,1" newline bitfld.long 0x30 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_9_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_9" "0,1" newline bitfld.long 0x30 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_8_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_8" "0,1" newline bitfld.long 0x30 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_7_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_7" "0,1" newline bitfld.long 0x30 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_6_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_6" "0,1" newline bitfld.long 0x30 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_5_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_5" "0,1" newline bitfld.long 0x30 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_4_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_4" "0,1" newline bitfld.long 0x30 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_3_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_3" "0,1" newline bitfld.long 0x30 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_2_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_2" "0,1" newline bitfld.long 0x30 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_1_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_1" "0,1" newline bitfld.long 0x30 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_0_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_0" "0,1" line.long 0x34 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_1_5,Enable Clear Register 13" bitfld.long 0x34 31. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_31_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_31" "0,1" newline bitfld.long 0x34 30. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_30_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_30" "0,1" newline bitfld.long 0x34 29. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_29_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_29" "0,1" newline bitfld.long 0x34 28. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_28_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_28" "0,1" newline bitfld.long 0x34 27. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_27_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_27" "0,1" newline bitfld.long 0x34 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_26_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_26" "0,1" newline bitfld.long 0x34 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_25_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_25" "0,1" newline bitfld.long 0x34 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_24_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_24" "0,1" newline bitfld.long 0x34 23. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_23_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_23" "0,1" newline bitfld.long 0x34 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_22_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_22" "0,1" newline bitfld.long 0x34 21. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_21_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_21" "0,1" newline bitfld.long 0x34 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_20_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_20" "0,1" newline bitfld.long 0x34 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_19_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_19" "0,1" newline bitfld.long 0x34 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_18_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_18" "0,1" newline bitfld.long 0x34 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_17_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_17" "0,1" newline bitfld.long 0x34 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_16_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_16" "0,1" newline bitfld.long 0x34 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_15_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_15" "0,1" newline bitfld.long 0x34 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_14_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_14" "0,1" newline bitfld.long 0x34 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_13_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_13" "0,1" newline bitfld.long 0x34 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_12_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_12" "0,1" newline bitfld.long 0x34 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_11_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_11" "0,1" newline bitfld.long 0x34 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_10_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_10" "0,1" newline bitfld.long 0x34 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_9_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_9" "0,1" newline bitfld.long 0x34 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_8_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_8" "0,1" newline bitfld.long 0x34 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_7_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_7" "0,1" newline bitfld.long 0x34 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_6_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_6" "0,1" newline bitfld.long 0x34 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_5_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_5" "0,1" newline bitfld.long 0x34 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_4_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_4" "0,1" newline bitfld.long 0x34 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_3_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_3" "0,1" newline bitfld.long 0x34 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_2_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_2" "0,1" newline bitfld.long 0x34 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_1_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_1" "0,1" newline bitfld.long 0x34 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_0_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_0" "0,1" line.long 0x38 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_1_6,Enable Clear Register 14" bitfld.long 0x38 31. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_63_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_63" "0,1" newline bitfld.long 0x38 30. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_62_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_62" "0,1" newline bitfld.long 0x38 29. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_61_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_61" "0,1" newline bitfld.long 0x38 28. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_60_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_60" "0,1" newline bitfld.long 0x38 27. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_59_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_59" "0,1" newline bitfld.long 0x38 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_58_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_58" "0,1" newline bitfld.long 0x38 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_57_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_57" "0,1" newline bitfld.long 0x38 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_56_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_56" "0,1" newline bitfld.long 0x38 23. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_55_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_55" "0,1" newline bitfld.long 0x38 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_54_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_54" "0,1" newline bitfld.long 0x38 21. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_53_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_53" "0,1" newline bitfld.long 0x38 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_52_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_52" "0,1" newline bitfld.long 0x38 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_51_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_51" "0,1" newline bitfld.long 0x38 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_50_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_50" "0,1" newline bitfld.long 0x38 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_49_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_49" "0,1" newline bitfld.long 0x38 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_48_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_48" "0,1" newline bitfld.long 0x38 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_47_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_47" "0,1" newline bitfld.long 0x38 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_46_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_46" "0,1" newline bitfld.long 0x38 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_45_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_45" "0,1" newline bitfld.long 0x38 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_44_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_44" "0,1" newline bitfld.long 0x38 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_43_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_43" "0,1" newline bitfld.long 0x38 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_42_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_42" "0,1" newline bitfld.long 0x38 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_41_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_41" "0,1" newline bitfld.long 0x38 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_40_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_40" "0,1" newline bitfld.long 0x38 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_39_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_39" "0,1" newline bitfld.long 0x38 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_38_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_38" "0,1" newline bitfld.long 0x38 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_37_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_37" "0,1" newline bitfld.long 0x38 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_36_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_36" "0,1" newline bitfld.long 0x38 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_35_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_35" "0,1" newline bitfld.long 0x38 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_34_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_34" "0,1" newline bitfld.long 0x38 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_33_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_33" "0,1" newline bitfld.long 0x38 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_32_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_32" "0,1" line.long 0x3C "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_1_7,Enable Clear Register 15" bitfld.long 0x3C 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_CTM_PULSE_CLR,Enable Clear for level_vpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0x3C 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_PROT_ERR_CLR,Enable Clear for level_vpac_out_1_en_utc1_prot_err" "0,1" newline bitfld.long 0x3C 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_PROT_ERR_CLR,Enable Clear for level_vpac_out_1_en_utc0_prot_err" "0,1" newline bitfld.long 0x3C 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_ERROR_CLR,Enable Clear for level_vpac_out_1_en_utc1_error" "0,1" newline bitfld.long 0x3C 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_ERROR_CLR,Enable Clear for level_vpac_out_1_en_utc0_error" "0,1" line.long 0x40 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_2_0,Enable Clear Register 16" bitfld.long 0x40 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x40 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for level_vpac_out_2_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x40 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for level_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x40 23. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x40 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x40 21. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x40 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x40 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x40 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x40 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x40 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x40 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x40 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x40 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x40 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x40 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x40 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for level_vpac_out_2_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x40 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for level_vpac_out_2_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x40 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x40 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x40 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x40 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x40 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for level_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x40 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for level_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x40 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for level_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x40 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for level_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x40 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1" line.long 0x44 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_2_1,Enable Clear Register 17" bitfld.long 0x44 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for level_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x44 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_2_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x44 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_2_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x44 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_INT_SZOVF_CLR,Enable Clear for level_vpac_out_2_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x44 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_2_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x44 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x44 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x44 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x44 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x48 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_2_2,Enable Clear Register 18" bitfld.long 0x48 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_NF_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_2_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x48 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_NF_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_2_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x48 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_NF_FRAME_DONE_CLR,Enable Clear for level_vpac_out_2_en_nf_frame_done" "0,1" newline bitfld.long 0x48 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x48 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x48 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for level_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x48 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for level_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x4C "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_2_3,Enable Clear Register 19" bitfld.long 0x4C 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for level_vpac_out_2_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x4C 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for level_vpac_out_2_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x4C 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for level_vpac_out_2_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x4C 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for level_vpac_out_2_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x4C 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_vpac_out_2_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x4C 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for level_vpac_out_2_en_spare_pend_1_level" "0,1" newline bitfld.long 0x4C 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for level_vpac_out_2_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x4C 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for level_vpac_out_2_en_spare_pend_0_level" "0,1" newline bitfld.long 0x4C 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for level_vpac_out_2_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x4C 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_DEC_1_CLR,Enable Clear for level_vpac_out_2_en_spare_dec_1" "0,1" newline bitfld.long 0x4C 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_DEC_0_CLR,Enable Clear for level_vpac_out_2_en_spare_dec_0" "0,1" newline bitfld.long 0x4C 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_6_CLR,Enable Clear for level_vpac_out_2_en_tdone_6" "0,1" newline bitfld.long 0x4C 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_5_CLR,Enable Clear for level_vpac_out_2_en_tdone_5" "0,1" newline bitfld.long 0x4C 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_4_CLR,Enable Clear for level_vpac_out_2_en_tdone_4" "0,1" newline bitfld.long 0x4C 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_2_CLR,Enable Clear for level_vpac_out_2_en_tdone_2" "0,1" newline bitfld.long 0x4C 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_0_CLR,Enable Clear for level_vpac_out_2_en_tdone_0" "0,1" newline bitfld.long 0x4C 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_6_CLR,Enable Clear for level_vpac_out_2_en_pipe_done_6" "0,1" newline bitfld.long 0x4C 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_5_CLR,Enable Clear for level_vpac_out_2_en_pipe_done_5" "0,1" newline bitfld.long 0x4C 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_4_CLR,Enable Clear for level_vpac_out_2_en_pipe_done_4" "0,1" newline bitfld.long 0x4C 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_3_CLR,Enable Clear for level_vpac_out_2_en_pipe_done_3" "0,1" newline bitfld.long 0x4C 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_2_CLR,Enable Clear for level_vpac_out_2_en_pipe_done_2" "0,1" newline bitfld.long 0x4C 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_1_CLR,Enable Clear for level_vpac_out_2_en_pipe_done_1" "0,1" newline bitfld.long 0x4C 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_0_CLR,Enable Clear for level_vpac_out_2_en_pipe_done_0" "0,1" line.long 0x50 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_2_4,Enable Clear Register 20" bitfld.long 0x50 31. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_31_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_31" "0,1" newline bitfld.long 0x50 30. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_30_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_30" "0,1" newline bitfld.long 0x50 29. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_29_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_29" "0,1" newline bitfld.long 0x50 28. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_28_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_28" "0,1" newline bitfld.long 0x50 27. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_27_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_27" "0,1" newline bitfld.long 0x50 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_26_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_26" "0,1" newline bitfld.long 0x50 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_25_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_25" "0,1" newline bitfld.long 0x50 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_24_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_24" "0,1" newline bitfld.long 0x50 23. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_23_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_23" "0,1" newline bitfld.long 0x50 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_22_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_22" "0,1" newline bitfld.long 0x50 21. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_21_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_21" "0,1" newline bitfld.long 0x50 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_20_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_20" "0,1" newline bitfld.long 0x50 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_19_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_19" "0,1" newline bitfld.long 0x50 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_18_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_18" "0,1" newline bitfld.long 0x50 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_17_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_17" "0,1" newline bitfld.long 0x50 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_16_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_16" "0,1" newline bitfld.long 0x50 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_15_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_15" "0,1" newline bitfld.long 0x50 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_14_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_14" "0,1" newline bitfld.long 0x50 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_13_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_13" "0,1" newline bitfld.long 0x50 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_12_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_12" "0,1" newline bitfld.long 0x50 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_11_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_11" "0,1" newline bitfld.long 0x50 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_10_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_10" "0,1" newline bitfld.long 0x50 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_9_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_9" "0,1" newline bitfld.long 0x50 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_8_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_8" "0,1" newline bitfld.long 0x50 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_7_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_7" "0,1" newline bitfld.long 0x50 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_6_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_6" "0,1" newline bitfld.long 0x50 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_5_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_5" "0,1" newline bitfld.long 0x50 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_4_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_4" "0,1" newline bitfld.long 0x50 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_3_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_3" "0,1" newline bitfld.long 0x50 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_2_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_2" "0,1" newline bitfld.long 0x50 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_1_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_1" "0,1" newline bitfld.long 0x50 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_0_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_0" "0,1" line.long 0x54 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_2_5,Enable Clear Register 21" bitfld.long 0x54 31. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_31_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_31" "0,1" newline bitfld.long 0x54 30. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_30_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_30" "0,1" newline bitfld.long 0x54 29. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_29_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_29" "0,1" newline bitfld.long 0x54 28. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_28_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_28" "0,1" newline bitfld.long 0x54 27. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_27_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_27" "0,1" newline bitfld.long 0x54 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_26_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_26" "0,1" newline bitfld.long 0x54 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_25_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_25" "0,1" newline bitfld.long 0x54 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_24_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_24" "0,1" newline bitfld.long 0x54 23. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_23_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_23" "0,1" newline bitfld.long 0x54 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_22_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_22" "0,1" newline bitfld.long 0x54 21. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_21_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_21" "0,1" newline bitfld.long 0x54 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_20_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_20" "0,1" newline bitfld.long 0x54 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_19_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_19" "0,1" newline bitfld.long 0x54 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_18_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_18" "0,1" newline bitfld.long 0x54 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_17_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_17" "0,1" newline bitfld.long 0x54 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_16_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_16" "0,1" newline bitfld.long 0x54 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_15_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_15" "0,1" newline bitfld.long 0x54 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_14_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_14" "0,1" newline bitfld.long 0x54 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_13_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_13" "0,1" newline bitfld.long 0x54 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_12_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_12" "0,1" newline bitfld.long 0x54 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_11_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_11" "0,1" newline bitfld.long 0x54 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_10_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_10" "0,1" newline bitfld.long 0x54 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_9_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_9" "0,1" newline bitfld.long 0x54 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_8_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_8" "0,1" newline bitfld.long 0x54 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_7_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_7" "0,1" newline bitfld.long 0x54 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_6_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_6" "0,1" newline bitfld.long 0x54 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_5_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_5" "0,1" newline bitfld.long 0x54 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_4_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_4" "0,1" newline bitfld.long 0x54 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_3_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_3" "0,1" newline bitfld.long 0x54 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_2_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_2" "0,1" newline bitfld.long 0x54 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_1_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_1" "0,1" newline bitfld.long 0x54 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_0_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_0" "0,1" line.long 0x58 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_2_6,Enable Clear Register 22" bitfld.long 0x58 31. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_63_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_63" "0,1" newline bitfld.long 0x58 30. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_62_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_62" "0,1" newline bitfld.long 0x58 29. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_61_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_61" "0,1" newline bitfld.long 0x58 28. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_60_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_60" "0,1" newline bitfld.long 0x58 27. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_59_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_59" "0,1" newline bitfld.long 0x58 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_58_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_58" "0,1" newline bitfld.long 0x58 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_57_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_57" "0,1" newline bitfld.long 0x58 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_56_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_56" "0,1" newline bitfld.long 0x58 23. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_55_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_55" "0,1" newline bitfld.long 0x58 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_54_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_54" "0,1" newline bitfld.long 0x58 21. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_53_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_53" "0,1" newline bitfld.long 0x58 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_52_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_52" "0,1" newline bitfld.long 0x58 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_51_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_51" "0,1" newline bitfld.long 0x58 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_50_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_50" "0,1" newline bitfld.long 0x58 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_49_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_49" "0,1" newline bitfld.long 0x58 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_48_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_48" "0,1" newline bitfld.long 0x58 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_47_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_47" "0,1" newline bitfld.long 0x58 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_46_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_46" "0,1" newline bitfld.long 0x58 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_45_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_45" "0,1" newline bitfld.long 0x58 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_44_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_44" "0,1" newline bitfld.long 0x58 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_43_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_43" "0,1" newline bitfld.long 0x58 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_42_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_42" "0,1" newline bitfld.long 0x58 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_41_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_41" "0,1" newline bitfld.long 0x58 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_40_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_40" "0,1" newline bitfld.long 0x58 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_39_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_39" "0,1" newline bitfld.long 0x58 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_38_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_38" "0,1" newline bitfld.long 0x58 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_37_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_37" "0,1" newline bitfld.long 0x58 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_36_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_36" "0,1" newline bitfld.long 0x58 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_35_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_35" "0,1" newline bitfld.long 0x58 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_34_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_34" "0,1" newline bitfld.long 0x58 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_33_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_33" "0,1" newline bitfld.long 0x58 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_32_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_32" "0,1" line.long 0x5C "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_2_7,Enable Clear Register 23" bitfld.long 0x5C 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_CTM_PULSE_CLR,Enable Clear for level_vpac_out_2_en_ctm_pulse" "0,1" newline bitfld.long 0x5C 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_PROT_ERR_CLR,Enable Clear for level_vpac_out_2_en_utc1_prot_err" "0,1" newline bitfld.long 0x5C 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_PROT_ERR_CLR,Enable Clear for level_vpac_out_2_en_utc0_prot_err" "0,1" newline bitfld.long 0x5C 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_ERROR_CLR,Enable Clear for level_vpac_out_2_en_utc1_error" "0,1" newline bitfld.long 0x5C 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_ERROR_CLR,Enable Clear for level_vpac_out_2_en_utc0_error" "0,1" line.long 0x60 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_3_0,Enable Clear Register 24" bitfld.long 0x60 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x60 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for level_vpac_out_3_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x60 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for level_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x60 23. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x60 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x60 21. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x60 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x60 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x60 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x60 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x60 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x60 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x60 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x60 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x60 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x60 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x60 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for level_vpac_out_3_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x60 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for level_vpac_out_3_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x60 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x60 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x60 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x60 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x60 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for level_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x60 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for level_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x60 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for level_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x60 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for level_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x60 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1" line.long 0x64 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_3_1,Enable Clear Register 25" bitfld.long 0x64 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for level_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x64 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_3_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x64 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_3_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x64 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_INT_SZOVF_CLR,Enable Clear for level_vpac_out_3_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x64 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_3_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x64 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x64 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x64 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x64 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x68 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_3_2,Enable Clear Register 26" bitfld.long 0x68 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_NF_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_3_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x68 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_NF_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_3_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x68 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_NF_FRAME_DONE_CLR,Enable Clear for level_vpac_out_3_en_nf_frame_done" "0,1" newline bitfld.long 0x68 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x68 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x68 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for level_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x68 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for level_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x6C "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_3_3,Enable Clear Register 27" bitfld.long 0x6C 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for level_vpac_out_3_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x6C 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for level_vpac_out_3_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x6C 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for level_vpac_out_3_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x6C 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for level_vpac_out_3_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x6C 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_vpac_out_3_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x6C 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for level_vpac_out_3_en_spare_pend_1_level" "0,1" newline bitfld.long 0x6C 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for level_vpac_out_3_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x6C 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for level_vpac_out_3_en_spare_pend_0_level" "0,1" newline bitfld.long 0x6C 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for level_vpac_out_3_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x6C 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_DEC_1_CLR,Enable Clear for level_vpac_out_3_en_spare_dec_1" "0,1" newline bitfld.long 0x6C 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_DEC_0_CLR,Enable Clear for level_vpac_out_3_en_spare_dec_0" "0,1" newline bitfld.long 0x6C 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_6_CLR,Enable Clear for level_vpac_out_3_en_tdone_6" "0,1" newline bitfld.long 0x6C 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_5_CLR,Enable Clear for level_vpac_out_3_en_tdone_5" "0,1" newline bitfld.long 0x6C 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_4_CLR,Enable Clear for level_vpac_out_3_en_tdone_4" "0,1" newline bitfld.long 0x6C 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_2_CLR,Enable Clear for level_vpac_out_3_en_tdone_2" "0,1" newline bitfld.long 0x6C 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_0_CLR,Enable Clear for level_vpac_out_3_en_tdone_0" "0,1" newline bitfld.long 0x6C 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_6_CLR,Enable Clear for level_vpac_out_3_en_pipe_done_6" "0,1" newline bitfld.long 0x6C 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_5_CLR,Enable Clear for level_vpac_out_3_en_pipe_done_5" "0,1" newline bitfld.long 0x6C 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_4_CLR,Enable Clear for level_vpac_out_3_en_pipe_done_4" "0,1" newline bitfld.long 0x6C 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_3_CLR,Enable Clear for level_vpac_out_3_en_pipe_done_3" "0,1" newline bitfld.long 0x6C 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_2_CLR,Enable Clear for level_vpac_out_3_en_pipe_done_2" "0,1" newline bitfld.long 0x6C 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_1_CLR,Enable Clear for level_vpac_out_3_en_pipe_done_1" "0,1" newline bitfld.long 0x6C 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_0_CLR,Enable Clear for level_vpac_out_3_en_pipe_done_0" "0,1" line.long 0x70 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_3_4,Enable Clear Register 28" bitfld.long 0x70 31. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_31_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_31" "0,1" newline bitfld.long 0x70 30. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_30_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_30" "0,1" newline bitfld.long 0x70 29. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_29_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_29" "0,1" newline bitfld.long 0x70 28. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_28_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_28" "0,1" newline bitfld.long 0x70 27. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_27_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_27" "0,1" newline bitfld.long 0x70 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_26_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_26" "0,1" newline bitfld.long 0x70 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_25_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_25" "0,1" newline bitfld.long 0x70 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_24_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_24" "0,1" newline bitfld.long 0x70 23. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_23_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_23" "0,1" newline bitfld.long 0x70 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_22_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_22" "0,1" newline bitfld.long 0x70 21. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_21_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_21" "0,1" newline bitfld.long 0x70 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_20_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_20" "0,1" newline bitfld.long 0x70 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_19_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_19" "0,1" newline bitfld.long 0x70 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_18_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_18" "0,1" newline bitfld.long 0x70 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_17_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_17" "0,1" newline bitfld.long 0x70 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_16_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_16" "0,1" newline bitfld.long 0x70 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_15_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_15" "0,1" newline bitfld.long 0x70 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_14_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_14" "0,1" newline bitfld.long 0x70 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_13_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_13" "0,1" newline bitfld.long 0x70 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_12_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_12" "0,1" newline bitfld.long 0x70 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_11_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_11" "0,1" newline bitfld.long 0x70 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_10_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_10" "0,1" newline bitfld.long 0x70 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_9_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_9" "0,1" newline bitfld.long 0x70 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_8_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_8" "0,1" newline bitfld.long 0x70 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_7_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_7" "0,1" newline bitfld.long 0x70 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_6_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_6" "0,1" newline bitfld.long 0x70 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_5_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_5" "0,1" newline bitfld.long 0x70 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_4_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_4" "0,1" newline bitfld.long 0x70 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_3_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_3" "0,1" newline bitfld.long 0x70 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_2_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_2" "0,1" newline bitfld.long 0x70 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_1_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_1" "0,1" newline bitfld.long 0x70 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_0_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_0" "0,1" line.long 0x74 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_3_5,Enable Clear Register 29" bitfld.long 0x74 31. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_31_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_31" "0,1" newline bitfld.long 0x74 30. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_30_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_30" "0,1" newline bitfld.long 0x74 29. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_29_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_29" "0,1" newline bitfld.long 0x74 28. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_28_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_28" "0,1" newline bitfld.long 0x74 27. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_27_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_27" "0,1" newline bitfld.long 0x74 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_26_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_26" "0,1" newline bitfld.long 0x74 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_25_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_25" "0,1" newline bitfld.long 0x74 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_24_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_24" "0,1" newline bitfld.long 0x74 23. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_23_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_23" "0,1" newline bitfld.long 0x74 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_22_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_22" "0,1" newline bitfld.long 0x74 21. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_21_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_21" "0,1" newline bitfld.long 0x74 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_20_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_20" "0,1" newline bitfld.long 0x74 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_19_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_19" "0,1" newline bitfld.long 0x74 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_18_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_18" "0,1" newline bitfld.long 0x74 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_17_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_17" "0,1" newline bitfld.long 0x74 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_16_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_16" "0,1" newline bitfld.long 0x74 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_15_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_15" "0,1" newline bitfld.long 0x74 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_14_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_14" "0,1" newline bitfld.long 0x74 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_13_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_13" "0,1" newline bitfld.long 0x74 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_12_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_12" "0,1" newline bitfld.long 0x74 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_11_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_11" "0,1" newline bitfld.long 0x74 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_10_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_10" "0,1" newline bitfld.long 0x74 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_9_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_9" "0,1" newline bitfld.long 0x74 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_8_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_8" "0,1" newline bitfld.long 0x74 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_7_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_7" "0,1" newline bitfld.long 0x74 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_6_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_6" "0,1" newline bitfld.long 0x74 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_5_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_5" "0,1" newline bitfld.long 0x74 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_4_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_4" "0,1" newline bitfld.long 0x74 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_3_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_3" "0,1" newline bitfld.long 0x74 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_2_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_2" "0,1" newline bitfld.long 0x74 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_1_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_1" "0,1" newline bitfld.long 0x74 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_0_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_0" "0,1" line.long 0x78 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_3_6,Enable Clear Register 30" bitfld.long 0x78 31. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_63_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_63" "0,1" newline bitfld.long 0x78 30. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_62_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_62" "0,1" newline bitfld.long 0x78 29. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_61_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_61" "0,1" newline bitfld.long 0x78 28. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_60_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_60" "0,1" newline bitfld.long 0x78 27. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_59_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_59" "0,1" newline bitfld.long 0x78 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_58_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_58" "0,1" newline bitfld.long 0x78 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_57_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_57" "0,1" newline bitfld.long 0x78 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_56_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_56" "0,1" newline bitfld.long 0x78 23. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_55_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_55" "0,1" newline bitfld.long 0x78 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_54_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_54" "0,1" newline bitfld.long 0x78 21. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_53_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_53" "0,1" newline bitfld.long 0x78 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_52_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_52" "0,1" newline bitfld.long 0x78 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_51_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_51" "0,1" newline bitfld.long 0x78 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_50_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_50" "0,1" newline bitfld.long 0x78 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_49_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_49" "0,1" newline bitfld.long 0x78 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_48_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_48" "0,1" newline bitfld.long 0x78 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_47_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_47" "0,1" newline bitfld.long 0x78 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_46_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_46" "0,1" newline bitfld.long 0x78 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_45_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_45" "0,1" newline bitfld.long 0x78 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_44_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_44" "0,1" newline bitfld.long 0x78 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_43_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_43" "0,1" newline bitfld.long 0x78 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_42_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_42" "0,1" newline bitfld.long 0x78 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_41_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_41" "0,1" newline bitfld.long 0x78 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_40_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_40" "0,1" newline bitfld.long 0x78 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_39_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_39" "0,1" newline bitfld.long 0x78 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_38_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_38" "0,1" newline bitfld.long 0x78 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_37_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_37" "0,1" newline bitfld.long 0x78 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_36_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_36" "0,1" newline bitfld.long 0x78 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_35_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_35" "0,1" newline bitfld.long 0x78 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_34_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_34" "0,1" newline bitfld.long 0x78 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_33_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_33" "0,1" newline bitfld.long 0x78 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_32_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_32" "0,1" line.long 0x7C "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_3_7,Enable Clear Register 31" bitfld.long 0x7C 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_CTM_PULSE_CLR,Enable Clear for level_vpac_out_3_en_ctm_pulse" "0,1" newline bitfld.long 0x7C 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_PROT_ERR_CLR,Enable Clear for level_vpac_out_3_en_utc1_prot_err" "0,1" newline bitfld.long 0x7C 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_PROT_ERR_CLR,Enable Clear for level_vpac_out_3_en_utc0_prot_err" "0,1" newline bitfld.long 0x7C 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_ERROR_CLR,Enable Clear for level_vpac_out_3_en_utc1_error" "0,1" newline bitfld.long 0x7C 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_ERROR_CLR,Enable Clear for level_vpac_out_3_en_utc0_error" "0,1" line.long 0x80 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_4_0,Enable Clear Register 32" bitfld.long 0x80 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x80 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for level_vpac_out_4_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x80 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for level_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x80 23. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x80 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x80 21. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x80 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x80 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x80 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x80 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x80 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x80 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x80 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x80 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x80 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x80 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x80 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for level_vpac_out_4_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x80 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for level_vpac_out_4_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x80 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x80 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x80 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x80 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x80 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for level_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x80 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for level_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x80 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for level_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x80 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for level_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x80 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1" line.long 0x84 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_4_1,Enable Clear Register 33" bitfld.long 0x84 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for level_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x84 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_4_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x84 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_4_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x84 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_INT_SZOVF_CLR,Enable Clear for level_vpac_out_4_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x84 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_4_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x84 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x84 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x84 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x84 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x88 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_4_2,Enable Clear Register 34" bitfld.long 0x88 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_NF_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_4_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x88 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_NF_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_4_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x88 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_NF_FRAME_DONE_CLR,Enable Clear for level_vpac_out_4_en_nf_frame_done" "0,1" newline bitfld.long 0x88 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x88 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x88 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for level_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x88 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for level_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x8C "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_4_3,Enable Clear Register 35" bitfld.long 0x8C 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for level_vpac_out_4_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x8C 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for level_vpac_out_4_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x8C 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for level_vpac_out_4_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x8C 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for level_vpac_out_4_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x8C 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_vpac_out_4_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x8C 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for level_vpac_out_4_en_spare_pend_1_level" "0,1" newline bitfld.long 0x8C 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for level_vpac_out_4_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x8C 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for level_vpac_out_4_en_spare_pend_0_level" "0,1" newline bitfld.long 0x8C 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for level_vpac_out_4_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x8C 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_DEC_1_CLR,Enable Clear for level_vpac_out_4_en_spare_dec_1" "0,1" newline bitfld.long 0x8C 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_DEC_0_CLR,Enable Clear for level_vpac_out_4_en_spare_dec_0" "0,1" newline bitfld.long 0x8C 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_6_CLR,Enable Clear for level_vpac_out_4_en_tdone_6" "0,1" newline bitfld.long 0x8C 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_5_CLR,Enable Clear for level_vpac_out_4_en_tdone_5" "0,1" newline bitfld.long 0x8C 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_4_CLR,Enable Clear for level_vpac_out_4_en_tdone_4" "0,1" newline bitfld.long 0x8C 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_2_CLR,Enable Clear for level_vpac_out_4_en_tdone_2" "0,1" newline bitfld.long 0x8C 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_0_CLR,Enable Clear for level_vpac_out_4_en_tdone_0" "0,1" newline bitfld.long 0x8C 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_6_CLR,Enable Clear for level_vpac_out_4_en_pipe_done_6" "0,1" newline bitfld.long 0x8C 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_5_CLR,Enable Clear for level_vpac_out_4_en_pipe_done_5" "0,1" newline bitfld.long 0x8C 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_4_CLR,Enable Clear for level_vpac_out_4_en_pipe_done_4" "0,1" newline bitfld.long 0x8C 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_3_CLR,Enable Clear for level_vpac_out_4_en_pipe_done_3" "0,1" newline bitfld.long 0x8C 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_2_CLR,Enable Clear for level_vpac_out_4_en_pipe_done_2" "0,1" newline bitfld.long 0x8C 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_1_CLR,Enable Clear for level_vpac_out_4_en_pipe_done_1" "0,1" newline bitfld.long 0x8C 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_0_CLR,Enable Clear for level_vpac_out_4_en_pipe_done_0" "0,1" line.long 0x90 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_4_4,Enable Clear Register 36" bitfld.long 0x90 31. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_31_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_31" "0,1" newline bitfld.long 0x90 30. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_30_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_30" "0,1" newline bitfld.long 0x90 29. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_29_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_29" "0,1" newline bitfld.long 0x90 28. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_28_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_28" "0,1" newline bitfld.long 0x90 27. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_27_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_27" "0,1" newline bitfld.long 0x90 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_26_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_26" "0,1" newline bitfld.long 0x90 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_25_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_25" "0,1" newline bitfld.long 0x90 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_24_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_24" "0,1" newline bitfld.long 0x90 23. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_23_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_23" "0,1" newline bitfld.long 0x90 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_22_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_22" "0,1" newline bitfld.long 0x90 21. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_21_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_21" "0,1" newline bitfld.long 0x90 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_20_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_20" "0,1" newline bitfld.long 0x90 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_19_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_19" "0,1" newline bitfld.long 0x90 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_18_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_18" "0,1" newline bitfld.long 0x90 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_17_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_17" "0,1" newline bitfld.long 0x90 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_16_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_16" "0,1" newline bitfld.long 0x90 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_15_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_15" "0,1" newline bitfld.long 0x90 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_14_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_14" "0,1" newline bitfld.long 0x90 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_13_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_13" "0,1" newline bitfld.long 0x90 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_12_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_12" "0,1" newline bitfld.long 0x90 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_11_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_11" "0,1" newline bitfld.long 0x90 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_10_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_10" "0,1" newline bitfld.long 0x90 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_9_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_9" "0,1" newline bitfld.long 0x90 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_8_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_8" "0,1" newline bitfld.long 0x90 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_7_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_7" "0,1" newline bitfld.long 0x90 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_6_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_6" "0,1" newline bitfld.long 0x90 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_5_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_5" "0,1" newline bitfld.long 0x90 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_4_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_4" "0,1" newline bitfld.long 0x90 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_3_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_3" "0,1" newline bitfld.long 0x90 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_2_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_2" "0,1" newline bitfld.long 0x90 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_1_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_1" "0,1" newline bitfld.long 0x90 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_0_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_0" "0,1" line.long 0x94 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_4_5,Enable Clear Register 37" bitfld.long 0x94 31. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_31_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_31" "0,1" newline bitfld.long 0x94 30. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_30_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_30" "0,1" newline bitfld.long 0x94 29. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_29_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_29" "0,1" newline bitfld.long 0x94 28. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_28_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_28" "0,1" newline bitfld.long 0x94 27. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_27_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_27" "0,1" newline bitfld.long 0x94 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_26_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_26" "0,1" newline bitfld.long 0x94 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_25_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_25" "0,1" newline bitfld.long 0x94 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_24_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_24" "0,1" newline bitfld.long 0x94 23. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_23_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_23" "0,1" newline bitfld.long 0x94 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_22_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_22" "0,1" newline bitfld.long 0x94 21. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_21_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_21" "0,1" newline bitfld.long 0x94 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_20_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_20" "0,1" newline bitfld.long 0x94 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_19_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_19" "0,1" newline bitfld.long 0x94 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_18_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_18" "0,1" newline bitfld.long 0x94 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_17_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_17" "0,1" newline bitfld.long 0x94 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_16_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_16" "0,1" newline bitfld.long 0x94 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_15_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_15" "0,1" newline bitfld.long 0x94 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_14_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_14" "0,1" newline bitfld.long 0x94 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_13_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_13" "0,1" newline bitfld.long 0x94 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_12_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_12" "0,1" newline bitfld.long 0x94 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_11_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_11" "0,1" newline bitfld.long 0x94 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_10_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_10" "0,1" newline bitfld.long 0x94 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_9_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_9" "0,1" newline bitfld.long 0x94 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_8_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_8" "0,1" newline bitfld.long 0x94 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_7_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_7" "0,1" newline bitfld.long 0x94 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_6_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_6" "0,1" newline bitfld.long 0x94 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_5_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_5" "0,1" newline bitfld.long 0x94 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_4_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_4" "0,1" newline bitfld.long 0x94 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_3_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_3" "0,1" newline bitfld.long 0x94 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_2_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_2" "0,1" newline bitfld.long 0x94 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_1_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_1" "0,1" newline bitfld.long 0x94 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_0_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_0" "0,1" line.long 0x98 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_4_6,Enable Clear Register 38" bitfld.long 0x98 31. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_63_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_63" "0,1" newline bitfld.long 0x98 30. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_62_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_62" "0,1" newline bitfld.long 0x98 29. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_61_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_61" "0,1" newline bitfld.long 0x98 28. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_60_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_60" "0,1" newline bitfld.long 0x98 27. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_59_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_59" "0,1" newline bitfld.long 0x98 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_58_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_58" "0,1" newline bitfld.long 0x98 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_57_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_57" "0,1" newline bitfld.long 0x98 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_56_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_56" "0,1" newline bitfld.long 0x98 23. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_55_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_55" "0,1" newline bitfld.long 0x98 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_54_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_54" "0,1" newline bitfld.long 0x98 21. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_53_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_53" "0,1" newline bitfld.long 0x98 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_52_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_52" "0,1" newline bitfld.long 0x98 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_51_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_51" "0,1" newline bitfld.long 0x98 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_50_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_50" "0,1" newline bitfld.long 0x98 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_49_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_49" "0,1" newline bitfld.long 0x98 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_48_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_48" "0,1" newline bitfld.long 0x98 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_47_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_47" "0,1" newline bitfld.long 0x98 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_46_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_46" "0,1" newline bitfld.long 0x98 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_45_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_45" "0,1" newline bitfld.long 0x98 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_44_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_44" "0,1" newline bitfld.long 0x98 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_43_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_43" "0,1" newline bitfld.long 0x98 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_42_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_42" "0,1" newline bitfld.long 0x98 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_41_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_41" "0,1" newline bitfld.long 0x98 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_40_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_40" "0,1" newline bitfld.long 0x98 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_39_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_39" "0,1" newline bitfld.long 0x98 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_38_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_38" "0,1" newline bitfld.long 0x98 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_37_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_37" "0,1" newline bitfld.long 0x98 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_36_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_36" "0,1" newline bitfld.long 0x98 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_35_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_35" "0,1" newline bitfld.long 0x98 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_34_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_34" "0,1" newline bitfld.long 0x98 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_33_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_33" "0,1" newline bitfld.long 0x98 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_32_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_32" "0,1" line.long 0x9C "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_4_7,Enable Clear Register 39" bitfld.long 0x9C 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_CTM_PULSE_CLR,Enable Clear for level_vpac_out_4_en_ctm_pulse" "0,1" newline bitfld.long 0x9C 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_PROT_ERR_CLR,Enable Clear for level_vpac_out_4_en_utc1_prot_err" "0,1" newline bitfld.long 0x9C 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_PROT_ERR_CLR,Enable Clear for level_vpac_out_4_en_utc0_prot_err" "0,1" newline bitfld.long 0x9C 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_ERROR_CLR,Enable Clear for level_vpac_out_4_en_utc1_error" "0,1" newline bitfld.long 0x9C 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_ERROR_CLR,Enable Clear for level_vpac_out_4_en_utc0_error" "0,1" line.long 0xA0 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_5_0,Enable Clear Register 40" bitfld.long 0xA0 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xA0 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for level_vpac_out_5_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xA0 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for level_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xA0 23. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xA0 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xA0 21. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xA0 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xA0 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xA0 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xA0 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xA0 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xA0 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xA0 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xA0 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xA0 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xA0 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xA0 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for level_vpac_out_5_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xA0 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for level_vpac_out_5_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xA0 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xA0 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xA0 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xA0 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xA0 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for level_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xA0 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for level_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xA0 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for level_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xA0 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for level_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xA0 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1" line.long 0xA4 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_5_1,Enable Clear Register 41" bitfld.long 0xA4 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for level_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xA4 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_5_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xA4 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_5_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xA4 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_INT_SZOVF_CLR,Enable Clear for level_vpac_out_5_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xA4 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_5_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xA4 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xA4 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xA4 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xA4 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xA8 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_5_2,Enable Clear Register 42" bitfld.long 0xA8 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_NF_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_5_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0xA8 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_NF_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_5_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0xA8 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_NF_FRAME_DONE_CLR,Enable Clear for level_vpac_out_5_en_nf_frame_done" "0,1" newline bitfld.long 0xA8 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xA8 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xA8 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for level_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xA8 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for level_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xAC "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_5_3,Enable Clear Register 43" bitfld.long 0xAC 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for level_vpac_out_5_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xAC 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for level_vpac_out_5_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xAC 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for level_vpac_out_5_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xAC 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for level_vpac_out_5_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xAC 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_vpac_out_5_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xAC 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for level_vpac_out_5_en_spare_pend_1_level" "0,1" newline bitfld.long 0xAC 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for level_vpac_out_5_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0xAC 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for level_vpac_out_5_en_spare_pend_0_level" "0,1" newline bitfld.long 0xAC 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for level_vpac_out_5_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xAC 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_DEC_1_CLR,Enable Clear for level_vpac_out_5_en_spare_dec_1" "0,1" newline bitfld.long 0xAC 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_DEC_0_CLR,Enable Clear for level_vpac_out_5_en_spare_dec_0" "0,1" newline bitfld.long 0xAC 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_6_CLR,Enable Clear for level_vpac_out_5_en_tdone_6" "0,1" newline bitfld.long 0xAC 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_5_CLR,Enable Clear for level_vpac_out_5_en_tdone_5" "0,1" newline bitfld.long 0xAC 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_4_CLR,Enable Clear for level_vpac_out_5_en_tdone_4" "0,1" newline bitfld.long 0xAC 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_2_CLR,Enable Clear for level_vpac_out_5_en_tdone_2" "0,1" newline bitfld.long 0xAC 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_0_CLR,Enable Clear for level_vpac_out_5_en_tdone_0" "0,1" newline bitfld.long 0xAC 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_6_CLR,Enable Clear for level_vpac_out_5_en_pipe_done_6" "0,1" newline bitfld.long 0xAC 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_5_CLR,Enable Clear for level_vpac_out_5_en_pipe_done_5" "0,1" newline bitfld.long 0xAC 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_4_CLR,Enable Clear for level_vpac_out_5_en_pipe_done_4" "0,1" newline bitfld.long 0xAC 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_3_CLR,Enable Clear for level_vpac_out_5_en_pipe_done_3" "0,1" newline bitfld.long 0xAC 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_2_CLR,Enable Clear for level_vpac_out_5_en_pipe_done_2" "0,1" newline bitfld.long 0xAC 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_1_CLR,Enable Clear for level_vpac_out_5_en_pipe_done_1" "0,1" newline bitfld.long 0xAC 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_0_CLR,Enable Clear for level_vpac_out_5_en_pipe_done_0" "0,1" line.long 0xB0 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_5_4,Enable Clear Register 44" bitfld.long 0xB0 31. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_31_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_31" "0,1" newline bitfld.long 0xB0 30. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_30_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_30" "0,1" newline bitfld.long 0xB0 29. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_29_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_29" "0,1" newline bitfld.long 0xB0 28. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_28_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_28" "0,1" newline bitfld.long 0xB0 27. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_27_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_27" "0,1" newline bitfld.long 0xB0 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_26_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_26" "0,1" newline bitfld.long 0xB0 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_25_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_25" "0,1" newline bitfld.long 0xB0 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_24_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_24" "0,1" newline bitfld.long 0xB0 23. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_23_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_23" "0,1" newline bitfld.long 0xB0 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_22_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_22" "0,1" newline bitfld.long 0xB0 21. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_21_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_21" "0,1" newline bitfld.long 0xB0 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_20_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_20" "0,1" newline bitfld.long 0xB0 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_19_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_19" "0,1" newline bitfld.long 0xB0 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_18_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_18" "0,1" newline bitfld.long 0xB0 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_17_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_17" "0,1" newline bitfld.long 0xB0 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_16_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_16" "0,1" newline bitfld.long 0xB0 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_15_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_15" "0,1" newline bitfld.long 0xB0 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_14_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_14" "0,1" newline bitfld.long 0xB0 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_13_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_13" "0,1" newline bitfld.long 0xB0 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_12_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_12" "0,1" newline bitfld.long 0xB0 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_11_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_11" "0,1" newline bitfld.long 0xB0 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_10_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_10" "0,1" newline bitfld.long 0xB0 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_9_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_9" "0,1" newline bitfld.long 0xB0 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_8_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_8" "0,1" newline bitfld.long 0xB0 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_7_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_7" "0,1" newline bitfld.long 0xB0 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_6_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_6" "0,1" newline bitfld.long 0xB0 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_5_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_5" "0,1" newline bitfld.long 0xB0 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_4_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_4" "0,1" newline bitfld.long 0xB0 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_3_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_3" "0,1" newline bitfld.long 0xB0 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_2_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_2" "0,1" newline bitfld.long 0xB0 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_1_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_1" "0,1" newline bitfld.long 0xB0 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_0_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_0" "0,1" line.long 0xB4 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_5_5,Enable Clear Register 45" bitfld.long 0xB4 31. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_31_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_31" "0,1" newline bitfld.long 0xB4 30. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_30_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_30" "0,1" newline bitfld.long 0xB4 29. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_29_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_29" "0,1" newline bitfld.long 0xB4 28. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_28_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_28" "0,1" newline bitfld.long 0xB4 27. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_27_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_27" "0,1" newline bitfld.long 0xB4 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_26_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_26" "0,1" newline bitfld.long 0xB4 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_25_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_25" "0,1" newline bitfld.long 0xB4 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_24_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_24" "0,1" newline bitfld.long 0xB4 23. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_23_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_23" "0,1" newline bitfld.long 0xB4 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_22_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_22" "0,1" newline bitfld.long 0xB4 21. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_21_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_21" "0,1" newline bitfld.long 0xB4 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_20_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_20" "0,1" newline bitfld.long 0xB4 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_19_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_19" "0,1" newline bitfld.long 0xB4 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_18_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_18" "0,1" newline bitfld.long 0xB4 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_17_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_17" "0,1" newline bitfld.long 0xB4 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_16_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_16" "0,1" newline bitfld.long 0xB4 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_15_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_15" "0,1" newline bitfld.long 0xB4 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_14_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_14" "0,1" newline bitfld.long 0xB4 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_13_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_13" "0,1" newline bitfld.long 0xB4 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_12_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_12" "0,1" newline bitfld.long 0xB4 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_11_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_11" "0,1" newline bitfld.long 0xB4 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_10_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_10" "0,1" newline bitfld.long 0xB4 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_9_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_9" "0,1" newline bitfld.long 0xB4 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_8_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_8" "0,1" newline bitfld.long 0xB4 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_7_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_7" "0,1" newline bitfld.long 0xB4 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_6_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_6" "0,1" newline bitfld.long 0xB4 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_5_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_5" "0,1" newline bitfld.long 0xB4 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_4_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_4" "0,1" newline bitfld.long 0xB4 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_3_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_3" "0,1" newline bitfld.long 0xB4 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_2_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_2" "0,1" newline bitfld.long 0xB4 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_1_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_1" "0,1" newline bitfld.long 0xB4 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_0_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_0" "0,1" line.long 0xB8 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_5_6,Enable Clear Register 46" bitfld.long 0xB8 31. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_63_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_63" "0,1" newline bitfld.long 0xB8 30. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_62_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_62" "0,1" newline bitfld.long 0xB8 29. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_61_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_61" "0,1" newline bitfld.long 0xB8 28. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_60_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_60" "0,1" newline bitfld.long 0xB8 27. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_59_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_59" "0,1" newline bitfld.long 0xB8 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_58_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_58" "0,1" newline bitfld.long 0xB8 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_57_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_57" "0,1" newline bitfld.long 0xB8 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_56_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_56" "0,1" newline bitfld.long 0xB8 23. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_55_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_55" "0,1" newline bitfld.long 0xB8 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_54_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_54" "0,1" newline bitfld.long 0xB8 21. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_53_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_53" "0,1" newline bitfld.long 0xB8 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_52_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_52" "0,1" newline bitfld.long 0xB8 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_51_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_51" "0,1" newline bitfld.long 0xB8 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_50_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_50" "0,1" newline bitfld.long 0xB8 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_49_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_49" "0,1" newline bitfld.long 0xB8 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_48_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_48" "0,1" newline bitfld.long 0xB8 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_47_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_47" "0,1" newline bitfld.long 0xB8 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_46_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_46" "0,1" newline bitfld.long 0xB8 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_45_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_45" "0,1" newline bitfld.long 0xB8 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_44_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_44" "0,1" newline bitfld.long 0xB8 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_43_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_43" "0,1" newline bitfld.long 0xB8 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_42_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_42" "0,1" newline bitfld.long 0xB8 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_41_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_41" "0,1" newline bitfld.long 0xB8 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_40_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_40" "0,1" newline bitfld.long 0xB8 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_39_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_39" "0,1" newline bitfld.long 0xB8 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_38_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_38" "0,1" newline bitfld.long 0xB8 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_37_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_37" "0,1" newline bitfld.long 0xB8 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_36_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_36" "0,1" newline bitfld.long 0xB8 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_35_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_35" "0,1" newline bitfld.long 0xB8 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_34_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_34" "0,1" newline bitfld.long 0xB8 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_33_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_33" "0,1" newline bitfld.long 0xB8 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_32_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_32" "0,1" line.long 0xBC "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_5_7,Enable Clear Register 47" bitfld.long 0xBC 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_CTM_PULSE_CLR,Enable Clear for level_vpac_out_5_en_ctm_pulse" "0,1" newline bitfld.long 0xBC 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_PROT_ERR_CLR,Enable Clear for level_vpac_out_5_en_utc1_prot_err" "0,1" newline bitfld.long 0xBC 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_PROT_ERR_CLR,Enable Clear for level_vpac_out_5_en_utc0_prot_err" "0,1" newline bitfld.long 0xBC 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_ERROR_CLR,Enable Clear for level_vpac_out_5_en_utc1_error" "0,1" newline bitfld.long 0xBC 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_ERROR_CLR,Enable Clear for level_vpac_out_5_en_utc0_error" "0,1" line.long 0xC0 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_0_0,Enable Clear Register 48" bitfld.long 0xC0 26. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xC0 25. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xC0 24. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xC0 23. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xC0 22. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xC0 21. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xC0 20. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xC0 19. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xC0 18. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xC0 17. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xC0 16. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xC0 15. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xC0 14. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xC0 13. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xC0 12. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xC0 11. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xC0 10. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xC0 9. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xC0 8. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xC0 7. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xC0 6. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xC0 5. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xC0 4. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xC0 3. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xC0 2. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xC0 1. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xC0 0. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1" line.long 0xC4 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_0_1,Enable Clear Register 49" bitfld.long 0xC4 8. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xC4 7. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xC4 6. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xC4 5. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_INT_SZOVF_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xC4 4. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xC4 3. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xC4 2. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xC4 1. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xC4 0. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xC8 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_0_2,Enable Clear Register 50" bitfld.long 0xC8 10. "ENABLE_PULSE_VPAC_OUT_0_EN_NF_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0xC8 9. "ENABLE_PULSE_VPAC_OUT_0_EN_NF_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0xC8 8. "ENABLE_PULSE_VPAC_OUT_0_EN_NF_FRAME_DONE_CLR,Enable Clear for pulse_vpac_out_0_en_nf_frame_done" "0,1" newline bitfld.long 0xC8 3. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xC8 2. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xC8 1. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for pulse_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xC8 0. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for pulse_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xCC "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_0_3,Enable Clear Register 51" bitfld.long 0xCC 26. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for pulse_vpac_out_0_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xCC 25. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for pulse_vpac_out_0_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xCC 24. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for pulse_vpac_out_0_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xCC 22. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for pulse_vpac_out_0_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xCC 20. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_vpac_out_0_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xCC 19. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for pulse_vpac_out_0_en_spare_pend_1_level" "0,1" newline bitfld.long 0xCC 18. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for pulse_vpac_out_0_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0xCC 17. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for pulse_vpac_out_0_en_spare_pend_0_level" "0,1" newline bitfld.long 0xCC 16. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for pulse_vpac_out_0_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xCC 15. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_vpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0xCC 14. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_vpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0xCC 13. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_6_CLR,Enable Clear for pulse_vpac_out_0_en_tdone_6" "0,1" newline bitfld.long 0xCC 12. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_5_CLR,Enable Clear for pulse_vpac_out_0_en_tdone_5" "0,1" newline bitfld.long 0xCC 11. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_4_CLR,Enable Clear for pulse_vpac_out_0_en_tdone_4" "0,1" newline bitfld.long 0xCC 9. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_2_CLR,Enable Clear for pulse_vpac_out_0_en_tdone_2" "0,1" newline bitfld.long 0xCC 7. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_0_CLR,Enable Clear for pulse_vpac_out_0_en_tdone_0" "0,1" newline bitfld.long 0xCC 6. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_6_CLR,Enable Clear for pulse_vpac_out_0_en_pipe_done_6" "0,1" newline bitfld.long 0xCC 5. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_5_CLR,Enable Clear for pulse_vpac_out_0_en_pipe_done_5" "0,1" newline bitfld.long 0xCC 4. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_4_CLR,Enable Clear for pulse_vpac_out_0_en_pipe_done_4" "0,1" newline bitfld.long 0xCC 3. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_vpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0xCC 2. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_vpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0xCC 1. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_vpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0xCC 0. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_vpac_out_0_en_pipe_done_0" "0,1" line.long 0xD0 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_0_4,Enable Clear Register 52" bitfld.long 0xD0 31. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_31" "0,1" newline bitfld.long 0xD0 30. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_30" "0,1" newline bitfld.long 0xD0 29. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_29" "0,1" newline bitfld.long 0xD0 28. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_28" "0,1" newline bitfld.long 0xD0 27. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_27" "0,1" newline bitfld.long 0xD0 26. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_26" "0,1" newline bitfld.long 0xD0 25. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_25" "0,1" newline bitfld.long 0xD0 24. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_24" "0,1" newline bitfld.long 0xD0 23. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_23" "0,1" newline bitfld.long 0xD0 22. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_22" "0,1" newline bitfld.long 0xD0 21. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_21" "0,1" newline bitfld.long 0xD0 20. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_20" "0,1" newline bitfld.long 0xD0 19. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_19" "0,1" newline bitfld.long 0xD0 18. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_18" "0,1" newline bitfld.long 0xD0 17. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_17" "0,1" newline bitfld.long 0xD0 16. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_16" "0,1" newline bitfld.long 0xD0 15. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_15" "0,1" newline bitfld.long 0xD0 14. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_14" "0,1" newline bitfld.long 0xD0 13. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_13" "0,1" newline bitfld.long 0xD0 12. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_12" "0,1" newline bitfld.long 0xD0 11. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_11" "0,1" newline bitfld.long 0xD0 10. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_10" "0,1" newline bitfld.long 0xD0 9. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_9" "0,1" newline bitfld.long 0xD0 8. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_8" "0,1" newline bitfld.long 0xD0 7. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_7" "0,1" newline bitfld.long 0xD0 6. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_6" "0,1" newline bitfld.long 0xD0 5. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_5" "0,1" newline bitfld.long 0xD0 4. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_4" "0,1" newline bitfld.long 0xD0 3. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_3" "0,1" newline bitfld.long 0xD0 2. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_2" "0,1" newline bitfld.long 0xD0 1. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_1" "0,1" newline bitfld.long 0xD0 0. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_0" "0,1" line.long 0xD4 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_0_5,Enable Clear Register 53" bitfld.long 0xD4 31. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_31" "0,1" newline bitfld.long 0xD4 30. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_30" "0,1" newline bitfld.long 0xD4 29. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_29" "0,1" newline bitfld.long 0xD4 28. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_28" "0,1" newline bitfld.long 0xD4 27. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_27" "0,1" newline bitfld.long 0xD4 26. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_26" "0,1" newline bitfld.long 0xD4 25. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_25" "0,1" newline bitfld.long 0xD4 24. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_24" "0,1" newline bitfld.long 0xD4 23. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_23" "0,1" newline bitfld.long 0xD4 22. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_22" "0,1" newline bitfld.long 0xD4 21. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_21" "0,1" newline bitfld.long 0xD4 20. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_20" "0,1" newline bitfld.long 0xD4 19. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_19" "0,1" newline bitfld.long 0xD4 18. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_18" "0,1" newline bitfld.long 0xD4 17. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_17" "0,1" newline bitfld.long 0xD4 16. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_16" "0,1" newline bitfld.long 0xD4 15. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_15" "0,1" newline bitfld.long 0xD4 14. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_14" "0,1" newline bitfld.long 0xD4 13. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_13" "0,1" newline bitfld.long 0xD4 12. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_12" "0,1" newline bitfld.long 0xD4 11. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_11" "0,1" newline bitfld.long 0xD4 10. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_10" "0,1" newline bitfld.long 0xD4 9. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_9" "0,1" newline bitfld.long 0xD4 8. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_8" "0,1" newline bitfld.long 0xD4 7. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_7" "0,1" newline bitfld.long 0xD4 6. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_6" "0,1" newline bitfld.long 0xD4 5. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_5" "0,1" newline bitfld.long 0xD4 4. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_4" "0,1" newline bitfld.long 0xD4 3. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_3" "0,1" newline bitfld.long 0xD4 2. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_2" "0,1" newline bitfld.long 0xD4 1. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_1" "0,1" newline bitfld.long 0xD4 0. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_0" "0,1" line.long 0xD8 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_0_6,Enable Clear Register 54" bitfld.long 0xD8 31. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_63_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_63" "0,1" newline bitfld.long 0xD8 30. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_62_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_62" "0,1" newline bitfld.long 0xD8 29. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_61_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_61" "0,1" newline bitfld.long 0xD8 28. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_60_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_60" "0,1" newline bitfld.long 0xD8 27. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_59_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_59" "0,1" newline bitfld.long 0xD8 26. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_58_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_58" "0,1" newline bitfld.long 0xD8 25. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_57_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_57" "0,1" newline bitfld.long 0xD8 24. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_56_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_56" "0,1" newline bitfld.long 0xD8 23. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_55_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_55" "0,1" newline bitfld.long 0xD8 22. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_54_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_54" "0,1" newline bitfld.long 0xD8 21. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_53_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_53" "0,1" newline bitfld.long 0xD8 20. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_52_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_52" "0,1" newline bitfld.long 0xD8 19. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_51_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_51" "0,1" newline bitfld.long 0xD8 18. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_50_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_50" "0,1" newline bitfld.long 0xD8 17. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_49_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_49" "0,1" newline bitfld.long 0xD8 16. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_48_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_48" "0,1" newline bitfld.long 0xD8 15. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_47_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_47" "0,1" newline bitfld.long 0xD8 14. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_46_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_46" "0,1" newline bitfld.long 0xD8 13. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_45_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_45" "0,1" newline bitfld.long 0xD8 12. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_44_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_44" "0,1" newline bitfld.long 0xD8 11. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_43_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_43" "0,1" newline bitfld.long 0xD8 10. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_42_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_42" "0,1" newline bitfld.long 0xD8 9. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_41_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_41" "0,1" newline bitfld.long 0xD8 8. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_40_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_40" "0,1" newline bitfld.long 0xD8 7. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_39_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_39" "0,1" newline bitfld.long 0xD8 6. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_38_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_38" "0,1" newline bitfld.long 0xD8 5. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_37_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_37" "0,1" newline bitfld.long 0xD8 4. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_36_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_36" "0,1" newline bitfld.long 0xD8 3. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_35_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_35" "0,1" newline bitfld.long 0xD8 2. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_34_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_34" "0,1" newline bitfld.long 0xD8 1. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_33_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_33" "0,1" newline bitfld.long 0xD8 0. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_32_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_32" "0,1" line.long 0xDC "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_0_7,Enable Clear Register 55" bitfld.long 0xDC 4. "ENABLE_PULSE_VPAC_OUT_0_EN_CTM_PULSE_CLR,Enable Clear for pulse_vpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0xDC 3. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_prot_err" "0,1" newline bitfld.long 0xDC 2. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_prot_err" "0,1" newline bitfld.long 0xDC 1. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_ERROR_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_error" "0,1" newline bitfld.long 0xDC 0. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_ERROR_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_error" "0,1" line.long 0xE0 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_1_0,Enable Clear Register 56" bitfld.long 0xE0 26. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xE0 25. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xE0 24. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xE0 23. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xE0 22. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xE0 21. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xE0 20. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xE0 19. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xE0 18. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xE0 17. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xE0 16. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xE0 15. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xE0 14. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xE0 13. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xE0 12. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xE0 11. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xE0 10. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xE0 9. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xE0 8. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xE0 7. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xE0 6. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xE0 5. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xE0 4. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xE0 3. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xE0 2. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xE0 1. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xE0 0. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1" line.long 0xE4 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_1_1,Enable Clear Register 57" bitfld.long 0xE4 8. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xE4 7. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xE4 6. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xE4 5. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_INT_SZOVF_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xE4 4. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xE4 3. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xE4 2. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xE4 1. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xE4 0. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xE8 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_1_2,Enable Clear Register 58" bitfld.long 0xE8 10. "ENABLE_PULSE_VPAC_OUT_1_EN_NF_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0xE8 9. "ENABLE_PULSE_VPAC_OUT_1_EN_NF_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0xE8 8. "ENABLE_PULSE_VPAC_OUT_1_EN_NF_FRAME_DONE_CLR,Enable Clear for pulse_vpac_out_1_en_nf_frame_done" "0,1" newline bitfld.long 0xE8 3. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xE8 2. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xE8 1. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for pulse_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xE8 0. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for pulse_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xEC "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_1_3,Enable Clear Register 59" bitfld.long 0xEC 26. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for pulse_vpac_out_1_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xEC 25. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for pulse_vpac_out_1_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xEC 24. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for pulse_vpac_out_1_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xEC 22. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for pulse_vpac_out_1_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xEC 20. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_vpac_out_1_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xEC 19. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for pulse_vpac_out_1_en_spare_pend_1_level" "0,1" newline bitfld.long 0xEC 18. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for pulse_vpac_out_1_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0xEC 17. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for pulse_vpac_out_1_en_spare_pend_0_level" "0,1" newline bitfld.long 0xEC 16. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for pulse_vpac_out_1_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xEC 15. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_vpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0xEC 14. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_vpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0xEC 13. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_6_CLR,Enable Clear for pulse_vpac_out_1_en_tdone_6" "0,1" newline bitfld.long 0xEC 12. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_5_CLR,Enable Clear for pulse_vpac_out_1_en_tdone_5" "0,1" newline bitfld.long 0xEC 11. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_4_CLR,Enable Clear for pulse_vpac_out_1_en_tdone_4" "0,1" newline bitfld.long 0xEC 9. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_2_CLR,Enable Clear for pulse_vpac_out_1_en_tdone_2" "0,1" newline bitfld.long 0xEC 7. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_0_CLR,Enable Clear for pulse_vpac_out_1_en_tdone_0" "0,1" newline bitfld.long 0xEC 6. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_6_CLR,Enable Clear for pulse_vpac_out_1_en_pipe_done_6" "0,1" newline bitfld.long 0xEC 5. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_5_CLR,Enable Clear for pulse_vpac_out_1_en_pipe_done_5" "0,1" newline bitfld.long 0xEC 4. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_4_CLR,Enable Clear for pulse_vpac_out_1_en_pipe_done_4" "0,1" newline bitfld.long 0xEC 3. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_vpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0xEC 2. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_vpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0xEC 1. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_vpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0xEC 0. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_vpac_out_1_en_pipe_done_0" "0,1" line.long 0xF0 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_1_4,Enable Clear Register 60" bitfld.long 0xF0 31. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_31" "0,1" newline bitfld.long 0xF0 30. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_30" "0,1" newline bitfld.long 0xF0 29. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_29" "0,1" newline bitfld.long 0xF0 28. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_28" "0,1" newline bitfld.long 0xF0 27. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_27" "0,1" newline bitfld.long 0xF0 26. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_26" "0,1" newline bitfld.long 0xF0 25. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_25" "0,1" newline bitfld.long 0xF0 24. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_24" "0,1" newline bitfld.long 0xF0 23. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_23" "0,1" newline bitfld.long 0xF0 22. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_22" "0,1" newline bitfld.long 0xF0 21. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_21" "0,1" newline bitfld.long 0xF0 20. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_20" "0,1" newline bitfld.long 0xF0 19. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_19" "0,1" newline bitfld.long 0xF0 18. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_18" "0,1" newline bitfld.long 0xF0 17. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_17" "0,1" newline bitfld.long 0xF0 16. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_16" "0,1" newline bitfld.long 0xF0 15. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_15" "0,1" newline bitfld.long 0xF0 14. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_14" "0,1" newline bitfld.long 0xF0 13. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_13" "0,1" newline bitfld.long 0xF0 12. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_12" "0,1" newline bitfld.long 0xF0 11. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_11" "0,1" newline bitfld.long 0xF0 10. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_10" "0,1" newline bitfld.long 0xF0 9. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_9" "0,1" newline bitfld.long 0xF0 8. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_8" "0,1" newline bitfld.long 0xF0 7. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_7" "0,1" newline bitfld.long 0xF0 6. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_6" "0,1" newline bitfld.long 0xF0 5. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_5" "0,1" newline bitfld.long 0xF0 4. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_4" "0,1" newline bitfld.long 0xF0 3. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_3" "0,1" newline bitfld.long 0xF0 2. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_2" "0,1" newline bitfld.long 0xF0 1. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_1" "0,1" newline bitfld.long 0xF0 0. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_0" "0,1" line.long 0xF4 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_1_5,Enable Clear Register 61" bitfld.long 0xF4 31. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_31" "0,1" newline bitfld.long 0xF4 30. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_30" "0,1" newline bitfld.long 0xF4 29. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_29" "0,1" newline bitfld.long 0xF4 28. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_28" "0,1" newline bitfld.long 0xF4 27. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_27" "0,1" newline bitfld.long 0xF4 26. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_26" "0,1" newline bitfld.long 0xF4 25. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_25" "0,1" newline bitfld.long 0xF4 24. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_24" "0,1" newline bitfld.long 0xF4 23. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_23" "0,1" newline bitfld.long 0xF4 22. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_22" "0,1" newline bitfld.long 0xF4 21. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_21" "0,1" newline bitfld.long 0xF4 20. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_20" "0,1" newline bitfld.long 0xF4 19. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_19" "0,1" newline bitfld.long 0xF4 18. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_18" "0,1" newline bitfld.long 0xF4 17. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_17" "0,1" newline bitfld.long 0xF4 16. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_16" "0,1" newline bitfld.long 0xF4 15. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_15" "0,1" newline bitfld.long 0xF4 14. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_14" "0,1" newline bitfld.long 0xF4 13. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_13" "0,1" newline bitfld.long 0xF4 12. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_12" "0,1" newline bitfld.long 0xF4 11. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_11" "0,1" newline bitfld.long 0xF4 10. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_10" "0,1" newline bitfld.long 0xF4 9. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_9" "0,1" newline bitfld.long 0xF4 8. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_8" "0,1" newline bitfld.long 0xF4 7. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_7" "0,1" newline bitfld.long 0xF4 6. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_6" "0,1" newline bitfld.long 0xF4 5. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_5" "0,1" newline bitfld.long 0xF4 4. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_4" "0,1" newline bitfld.long 0xF4 3. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_3" "0,1" newline bitfld.long 0xF4 2. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_2" "0,1" newline bitfld.long 0xF4 1. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_1" "0,1" newline bitfld.long 0xF4 0. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_0" "0,1" line.long 0xF8 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_1_6,Enable Clear Register 62" bitfld.long 0xF8 31. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_63_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_63" "0,1" newline bitfld.long 0xF8 30. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_62_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_62" "0,1" newline bitfld.long 0xF8 29. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_61_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_61" "0,1" newline bitfld.long 0xF8 28. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_60_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_60" "0,1" newline bitfld.long 0xF8 27. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_59_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_59" "0,1" newline bitfld.long 0xF8 26. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_58_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_58" "0,1" newline bitfld.long 0xF8 25. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_57_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_57" "0,1" newline bitfld.long 0xF8 24. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_56_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_56" "0,1" newline bitfld.long 0xF8 23. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_55_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_55" "0,1" newline bitfld.long 0xF8 22. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_54_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_54" "0,1" newline bitfld.long 0xF8 21. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_53_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_53" "0,1" newline bitfld.long 0xF8 20. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_52_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_52" "0,1" newline bitfld.long 0xF8 19. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_51_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_51" "0,1" newline bitfld.long 0xF8 18. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_50_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_50" "0,1" newline bitfld.long 0xF8 17. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_49_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_49" "0,1" newline bitfld.long 0xF8 16. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_48_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_48" "0,1" newline bitfld.long 0xF8 15. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_47_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_47" "0,1" newline bitfld.long 0xF8 14. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_46_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_46" "0,1" newline bitfld.long 0xF8 13. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_45_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_45" "0,1" newline bitfld.long 0xF8 12. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_44_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_44" "0,1" newline bitfld.long 0xF8 11. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_43_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_43" "0,1" newline bitfld.long 0xF8 10. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_42_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_42" "0,1" newline bitfld.long 0xF8 9. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_41_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_41" "0,1" newline bitfld.long 0xF8 8. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_40_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_40" "0,1" newline bitfld.long 0xF8 7. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_39_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_39" "0,1" newline bitfld.long 0xF8 6. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_38_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_38" "0,1" newline bitfld.long 0xF8 5. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_37_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_37" "0,1" newline bitfld.long 0xF8 4. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_36_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_36" "0,1" newline bitfld.long 0xF8 3. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_35_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_35" "0,1" newline bitfld.long 0xF8 2. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_34_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_34" "0,1" newline bitfld.long 0xF8 1. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_33_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_33" "0,1" newline bitfld.long 0xF8 0. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_32_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_32" "0,1" line.long 0xFC "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_1_7,Enable Clear Register 63" bitfld.long 0xFC 4. "ENABLE_PULSE_VPAC_OUT_1_EN_CTM_PULSE_CLR,Enable Clear for pulse_vpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0xFC 3. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_prot_err" "0,1" newline bitfld.long 0xFC 2. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_prot_err" "0,1" newline bitfld.long 0xFC 1. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_ERROR_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_error" "0,1" newline bitfld.long 0xFC 0. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_ERROR_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_error" "0,1" line.long 0x100 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_2_0,Enable Clear Register 64" bitfld.long 0x100 26. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x100 25. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x100 24. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x100 23. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x100 22. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x100 21. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x100 20. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x100 19. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x100 18. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x100 17. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x100 16. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x100 15. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x100 14. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x100 13. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x100 12. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x100 11. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x100 10. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x100 9. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x100 8. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x100 7. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x100 6. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x100 5. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x100 4. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x100 3. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x100 2. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x100 1. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x100 0. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1" line.long 0x104 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_2_1,Enable Clear Register 65" bitfld.long 0x104 8. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x104 7. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x104 6. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x104 5. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_INT_SZOVF_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x104 4. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x104 3. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x104 2. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x104 1. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x104 0. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x108 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_2_2,Enable Clear Register 66" bitfld.long 0x108 10. "ENABLE_PULSE_VPAC_OUT_2_EN_NF_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x108 9. "ENABLE_PULSE_VPAC_OUT_2_EN_NF_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x108 8. "ENABLE_PULSE_VPAC_OUT_2_EN_NF_FRAME_DONE_CLR,Enable Clear for pulse_vpac_out_2_en_nf_frame_done" "0,1" newline bitfld.long 0x108 3. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x108 2. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x108 1. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for pulse_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x108 0. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for pulse_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x10C "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_2_3,Enable Clear Register 67" bitfld.long 0x10C 26. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for pulse_vpac_out_2_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x10C 25. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for pulse_vpac_out_2_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x10C 24. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for pulse_vpac_out_2_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x10C 22. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for pulse_vpac_out_2_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x10C 20. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_vpac_out_2_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x10C 19. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for pulse_vpac_out_2_en_spare_pend_1_level" "0,1" newline bitfld.long 0x10C 18. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for pulse_vpac_out_2_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x10C 17. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for pulse_vpac_out_2_en_spare_pend_0_level" "0,1" newline bitfld.long 0x10C 16. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for pulse_vpac_out_2_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x10C 15. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_vpac_out_2_en_spare_dec_1" "0,1" newline bitfld.long 0x10C 14. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_vpac_out_2_en_spare_dec_0" "0,1" newline bitfld.long 0x10C 13. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_6_CLR,Enable Clear for pulse_vpac_out_2_en_tdone_6" "0,1" newline bitfld.long 0x10C 12. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_5_CLR,Enable Clear for pulse_vpac_out_2_en_tdone_5" "0,1" newline bitfld.long 0x10C 11. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_4_CLR,Enable Clear for pulse_vpac_out_2_en_tdone_4" "0,1" newline bitfld.long 0x10C 9. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_2_CLR,Enable Clear for pulse_vpac_out_2_en_tdone_2" "0,1" newline bitfld.long 0x10C 7. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_0_CLR,Enable Clear for pulse_vpac_out_2_en_tdone_0" "0,1" newline bitfld.long 0x10C 6. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_6_CLR,Enable Clear for pulse_vpac_out_2_en_pipe_done_6" "0,1" newline bitfld.long 0x10C 5. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_5_CLR,Enable Clear for pulse_vpac_out_2_en_pipe_done_5" "0,1" newline bitfld.long 0x10C 4. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_4_CLR,Enable Clear for pulse_vpac_out_2_en_pipe_done_4" "0,1" newline bitfld.long 0x10C 3. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_vpac_out_2_en_pipe_done_3" "0,1" newline bitfld.long 0x10C 2. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_vpac_out_2_en_pipe_done_2" "0,1" newline bitfld.long 0x10C 1. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_vpac_out_2_en_pipe_done_1" "0,1" newline bitfld.long 0x10C 0. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_vpac_out_2_en_pipe_done_0" "0,1" line.long 0x110 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_2_4,Enable Clear Register 68" bitfld.long 0x110 31. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_31" "0,1" newline bitfld.long 0x110 30. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_30" "0,1" newline bitfld.long 0x110 29. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_29" "0,1" newline bitfld.long 0x110 28. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_28" "0,1" newline bitfld.long 0x110 27. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_27" "0,1" newline bitfld.long 0x110 26. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_26" "0,1" newline bitfld.long 0x110 25. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_25" "0,1" newline bitfld.long 0x110 24. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_24" "0,1" newline bitfld.long 0x110 23. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_23" "0,1" newline bitfld.long 0x110 22. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_22" "0,1" newline bitfld.long 0x110 21. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_21" "0,1" newline bitfld.long 0x110 20. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_20" "0,1" newline bitfld.long 0x110 19. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_19" "0,1" newline bitfld.long 0x110 18. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_18" "0,1" newline bitfld.long 0x110 17. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_17" "0,1" newline bitfld.long 0x110 16. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_16" "0,1" newline bitfld.long 0x110 15. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_15" "0,1" newline bitfld.long 0x110 14. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_14" "0,1" newline bitfld.long 0x110 13. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_13" "0,1" newline bitfld.long 0x110 12. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_12" "0,1" newline bitfld.long 0x110 11. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_11" "0,1" newline bitfld.long 0x110 10. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_10" "0,1" newline bitfld.long 0x110 9. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_9" "0,1" newline bitfld.long 0x110 8. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_8" "0,1" newline bitfld.long 0x110 7. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_7" "0,1" newline bitfld.long 0x110 6. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_6" "0,1" newline bitfld.long 0x110 5. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_5" "0,1" newline bitfld.long 0x110 4. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_4" "0,1" newline bitfld.long 0x110 3. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_3" "0,1" newline bitfld.long 0x110 2. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_2" "0,1" newline bitfld.long 0x110 1. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_1" "0,1" newline bitfld.long 0x110 0. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_0" "0,1" line.long 0x114 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_2_5,Enable Clear Register 69" bitfld.long 0x114 31. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_31" "0,1" newline bitfld.long 0x114 30. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_30" "0,1" newline bitfld.long 0x114 29. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_29" "0,1" newline bitfld.long 0x114 28. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_28" "0,1" newline bitfld.long 0x114 27. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_27" "0,1" newline bitfld.long 0x114 26. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_26" "0,1" newline bitfld.long 0x114 25. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_25" "0,1" newline bitfld.long 0x114 24. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_24" "0,1" newline bitfld.long 0x114 23. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_23" "0,1" newline bitfld.long 0x114 22. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_22" "0,1" newline bitfld.long 0x114 21. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_21" "0,1" newline bitfld.long 0x114 20. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_20" "0,1" newline bitfld.long 0x114 19. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_19" "0,1" newline bitfld.long 0x114 18. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_18" "0,1" newline bitfld.long 0x114 17. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_17" "0,1" newline bitfld.long 0x114 16. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_16" "0,1" newline bitfld.long 0x114 15. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_15" "0,1" newline bitfld.long 0x114 14. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_14" "0,1" newline bitfld.long 0x114 13. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_13" "0,1" newline bitfld.long 0x114 12. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_12" "0,1" newline bitfld.long 0x114 11. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_11" "0,1" newline bitfld.long 0x114 10. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_10" "0,1" newline bitfld.long 0x114 9. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_9" "0,1" newline bitfld.long 0x114 8. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_8" "0,1" newline bitfld.long 0x114 7. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_7" "0,1" newline bitfld.long 0x114 6. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_6" "0,1" newline bitfld.long 0x114 5. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_5" "0,1" newline bitfld.long 0x114 4. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_4" "0,1" newline bitfld.long 0x114 3. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_3" "0,1" newline bitfld.long 0x114 2. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_2" "0,1" newline bitfld.long 0x114 1. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_1" "0,1" newline bitfld.long 0x114 0. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_0" "0,1" line.long 0x118 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_2_6,Enable Clear Register 70" bitfld.long 0x118 31. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_63_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_63" "0,1" newline bitfld.long 0x118 30. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_62_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_62" "0,1" newline bitfld.long 0x118 29. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_61_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_61" "0,1" newline bitfld.long 0x118 28. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_60_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_60" "0,1" newline bitfld.long 0x118 27. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_59_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_59" "0,1" newline bitfld.long 0x118 26. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_58_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_58" "0,1" newline bitfld.long 0x118 25. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_57_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_57" "0,1" newline bitfld.long 0x118 24. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_56_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_56" "0,1" newline bitfld.long 0x118 23. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_55_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_55" "0,1" newline bitfld.long 0x118 22. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_54_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_54" "0,1" newline bitfld.long 0x118 21. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_53_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_53" "0,1" newline bitfld.long 0x118 20. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_52_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_52" "0,1" newline bitfld.long 0x118 19. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_51_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_51" "0,1" newline bitfld.long 0x118 18. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_50_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_50" "0,1" newline bitfld.long 0x118 17. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_49_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_49" "0,1" newline bitfld.long 0x118 16. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_48_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_48" "0,1" newline bitfld.long 0x118 15. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_47_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_47" "0,1" newline bitfld.long 0x118 14. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_46_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_46" "0,1" newline bitfld.long 0x118 13. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_45_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_45" "0,1" newline bitfld.long 0x118 12. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_44_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_44" "0,1" newline bitfld.long 0x118 11. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_43_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_43" "0,1" newline bitfld.long 0x118 10. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_42_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_42" "0,1" newline bitfld.long 0x118 9. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_41_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_41" "0,1" newline bitfld.long 0x118 8. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_40_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_40" "0,1" newline bitfld.long 0x118 7. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_39_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_39" "0,1" newline bitfld.long 0x118 6. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_38_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_38" "0,1" newline bitfld.long 0x118 5. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_37_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_37" "0,1" newline bitfld.long 0x118 4. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_36_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_36" "0,1" newline bitfld.long 0x118 3. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_35_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_35" "0,1" newline bitfld.long 0x118 2. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_34_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_34" "0,1" newline bitfld.long 0x118 1. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_33_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_33" "0,1" newline bitfld.long 0x118 0. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_32_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_32" "0,1" line.long 0x11C "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_2_7,Enable Clear Register 71" bitfld.long 0x11C 4. "ENABLE_PULSE_VPAC_OUT_2_EN_CTM_PULSE_CLR,Enable Clear for pulse_vpac_out_2_en_ctm_pulse" "0,1" newline bitfld.long 0x11C 3. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_prot_err" "0,1" newline bitfld.long 0x11C 2. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_prot_err" "0,1" newline bitfld.long 0x11C 1. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_ERROR_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_error" "0,1" newline bitfld.long 0x11C 0. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_ERROR_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_error" "0,1" line.long 0x120 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_3_0,Enable Clear Register 72" bitfld.long 0x120 26. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x120 25. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x120 24. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x120 23. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x120 22. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x120 21. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x120 20. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x120 19. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x120 18. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x120 17. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x120 16. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x120 15. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x120 14. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x120 13. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x120 12. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x120 11. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x120 10. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x120 9. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x120 8. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x120 7. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x120 6. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x120 5. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x120 4. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x120 3. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x120 2. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x120 1. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x120 0. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1" line.long 0x124 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_3_1,Enable Clear Register 73" bitfld.long 0x124 8. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x124 7. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x124 6. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x124 5. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_INT_SZOVF_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x124 4. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x124 3. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x124 2. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x124 1. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x124 0. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x128 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_3_2,Enable Clear Register 74" bitfld.long 0x128 10. "ENABLE_PULSE_VPAC_OUT_3_EN_NF_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x128 9. "ENABLE_PULSE_VPAC_OUT_3_EN_NF_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x128 8. "ENABLE_PULSE_VPAC_OUT_3_EN_NF_FRAME_DONE_CLR,Enable Clear for pulse_vpac_out_3_en_nf_frame_done" "0,1" newline bitfld.long 0x128 3. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x128 2. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x128 1. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for pulse_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x128 0. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for pulse_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x12C "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_3_3,Enable Clear Register 75" bitfld.long 0x12C 26. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for pulse_vpac_out_3_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x12C 25. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for pulse_vpac_out_3_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x12C 24. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for pulse_vpac_out_3_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x12C 22. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for pulse_vpac_out_3_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x12C 20. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_vpac_out_3_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x12C 19. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for pulse_vpac_out_3_en_spare_pend_1_level" "0,1" newline bitfld.long 0x12C 18. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for pulse_vpac_out_3_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x12C 17. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for pulse_vpac_out_3_en_spare_pend_0_level" "0,1" newline bitfld.long 0x12C 16. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for pulse_vpac_out_3_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x12C 15. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_vpac_out_3_en_spare_dec_1" "0,1" newline bitfld.long 0x12C 14. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_vpac_out_3_en_spare_dec_0" "0,1" newline bitfld.long 0x12C 13. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_6_CLR,Enable Clear for pulse_vpac_out_3_en_tdone_6" "0,1" newline bitfld.long 0x12C 12. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_5_CLR,Enable Clear for pulse_vpac_out_3_en_tdone_5" "0,1" newline bitfld.long 0x12C 11. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_4_CLR,Enable Clear for pulse_vpac_out_3_en_tdone_4" "0,1" newline bitfld.long 0x12C 9. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_2_CLR,Enable Clear for pulse_vpac_out_3_en_tdone_2" "0,1" newline bitfld.long 0x12C 7. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_0_CLR,Enable Clear for pulse_vpac_out_3_en_tdone_0" "0,1" newline bitfld.long 0x12C 6. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_6_CLR,Enable Clear for pulse_vpac_out_3_en_pipe_done_6" "0,1" newline bitfld.long 0x12C 5. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_5_CLR,Enable Clear for pulse_vpac_out_3_en_pipe_done_5" "0,1" newline bitfld.long 0x12C 4. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_4_CLR,Enable Clear for pulse_vpac_out_3_en_pipe_done_4" "0,1" newline bitfld.long 0x12C 3. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_vpac_out_3_en_pipe_done_3" "0,1" newline bitfld.long 0x12C 2. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_vpac_out_3_en_pipe_done_2" "0,1" newline bitfld.long 0x12C 1. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_vpac_out_3_en_pipe_done_1" "0,1" newline bitfld.long 0x12C 0. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_vpac_out_3_en_pipe_done_0" "0,1" line.long 0x130 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_3_4,Enable Clear Register 76" bitfld.long 0x130 31. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_31" "0,1" newline bitfld.long 0x130 30. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_30" "0,1" newline bitfld.long 0x130 29. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_29" "0,1" newline bitfld.long 0x130 28. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_28" "0,1" newline bitfld.long 0x130 27. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_27" "0,1" newline bitfld.long 0x130 26. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_26" "0,1" newline bitfld.long 0x130 25. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_25" "0,1" newline bitfld.long 0x130 24. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_24" "0,1" newline bitfld.long 0x130 23. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_23" "0,1" newline bitfld.long 0x130 22. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_22" "0,1" newline bitfld.long 0x130 21. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_21" "0,1" newline bitfld.long 0x130 20. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_20" "0,1" newline bitfld.long 0x130 19. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_19" "0,1" newline bitfld.long 0x130 18. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_18" "0,1" newline bitfld.long 0x130 17. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_17" "0,1" newline bitfld.long 0x130 16. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_16" "0,1" newline bitfld.long 0x130 15. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_15" "0,1" newline bitfld.long 0x130 14. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_14" "0,1" newline bitfld.long 0x130 13. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_13" "0,1" newline bitfld.long 0x130 12. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_12" "0,1" newline bitfld.long 0x130 11. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_11" "0,1" newline bitfld.long 0x130 10. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_10" "0,1" newline bitfld.long 0x130 9. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_9" "0,1" newline bitfld.long 0x130 8. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_8" "0,1" newline bitfld.long 0x130 7. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_7" "0,1" newline bitfld.long 0x130 6. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_6" "0,1" newline bitfld.long 0x130 5. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_5" "0,1" newline bitfld.long 0x130 4. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_4" "0,1" newline bitfld.long 0x130 3. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_3" "0,1" newline bitfld.long 0x130 2. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_2" "0,1" newline bitfld.long 0x130 1. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_1" "0,1" newline bitfld.long 0x130 0. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_0" "0,1" line.long 0x134 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_3_5,Enable Clear Register 77" bitfld.long 0x134 31. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_31" "0,1" newline bitfld.long 0x134 30. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_30" "0,1" newline bitfld.long 0x134 29. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_29" "0,1" newline bitfld.long 0x134 28. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_28" "0,1" newline bitfld.long 0x134 27. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_27" "0,1" newline bitfld.long 0x134 26. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_26" "0,1" newline bitfld.long 0x134 25. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_25" "0,1" newline bitfld.long 0x134 24. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_24" "0,1" newline bitfld.long 0x134 23. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_23" "0,1" newline bitfld.long 0x134 22. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_22" "0,1" newline bitfld.long 0x134 21. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_21" "0,1" newline bitfld.long 0x134 20. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_20" "0,1" newline bitfld.long 0x134 19. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_19" "0,1" newline bitfld.long 0x134 18. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_18" "0,1" newline bitfld.long 0x134 17. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_17" "0,1" newline bitfld.long 0x134 16. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_16" "0,1" newline bitfld.long 0x134 15. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_15" "0,1" newline bitfld.long 0x134 14. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_14" "0,1" newline bitfld.long 0x134 13. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_13" "0,1" newline bitfld.long 0x134 12. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_12" "0,1" newline bitfld.long 0x134 11. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_11" "0,1" newline bitfld.long 0x134 10. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_10" "0,1" newline bitfld.long 0x134 9. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_9" "0,1" newline bitfld.long 0x134 8. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_8" "0,1" newline bitfld.long 0x134 7. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_7" "0,1" newline bitfld.long 0x134 6. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_6" "0,1" newline bitfld.long 0x134 5. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_5" "0,1" newline bitfld.long 0x134 4. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_4" "0,1" newline bitfld.long 0x134 3. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_3" "0,1" newline bitfld.long 0x134 2. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_2" "0,1" newline bitfld.long 0x134 1. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_1" "0,1" newline bitfld.long 0x134 0. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_0" "0,1" line.long 0x138 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_3_6,Enable Clear Register 78" bitfld.long 0x138 31. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_63_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_63" "0,1" newline bitfld.long 0x138 30. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_62_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_62" "0,1" newline bitfld.long 0x138 29. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_61_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_61" "0,1" newline bitfld.long 0x138 28. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_60_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_60" "0,1" newline bitfld.long 0x138 27. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_59_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_59" "0,1" newline bitfld.long 0x138 26. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_58_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_58" "0,1" newline bitfld.long 0x138 25. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_57_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_57" "0,1" newline bitfld.long 0x138 24. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_56_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_56" "0,1" newline bitfld.long 0x138 23. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_55_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_55" "0,1" newline bitfld.long 0x138 22. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_54_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_54" "0,1" newline bitfld.long 0x138 21. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_53_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_53" "0,1" newline bitfld.long 0x138 20. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_52_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_52" "0,1" newline bitfld.long 0x138 19. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_51_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_51" "0,1" newline bitfld.long 0x138 18. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_50_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_50" "0,1" newline bitfld.long 0x138 17. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_49_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_49" "0,1" newline bitfld.long 0x138 16. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_48_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_48" "0,1" newline bitfld.long 0x138 15. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_47_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_47" "0,1" newline bitfld.long 0x138 14. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_46_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_46" "0,1" newline bitfld.long 0x138 13. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_45_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_45" "0,1" newline bitfld.long 0x138 12. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_44_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_44" "0,1" newline bitfld.long 0x138 11. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_43_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_43" "0,1" newline bitfld.long 0x138 10. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_42_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_42" "0,1" newline bitfld.long 0x138 9. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_41_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_41" "0,1" newline bitfld.long 0x138 8. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_40_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_40" "0,1" newline bitfld.long 0x138 7. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_39_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_39" "0,1" newline bitfld.long 0x138 6. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_38_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_38" "0,1" newline bitfld.long 0x138 5. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_37_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_37" "0,1" newline bitfld.long 0x138 4. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_36_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_36" "0,1" newline bitfld.long 0x138 3. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_35_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_35" "0,1" newline bitfld.long 0x138 2. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_34_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_34" "0,1" newline bitfld.long 0x138 1. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_33_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_33" "0,1" newline bitfld.long 0x138 0. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_32_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_32" "0,1" line.long 0x13C "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_3_7,Enable Clear Register 79" bitfld.long 0x13C 4. "ENABLE_PULSE_VPAC_OUT_3_EN_CTM_PULSE_CLR,Enable Clear for pulse_vpac_out_3_en_ctm_pulse" "0,1" newline bitfld.long 0x13C 3. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_prot_err" "0,1" newline bitfld.long 0x13C 2. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_prot_err" "0,1" newline bitfld.long 0x13C 1. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_ERROR_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_error" "0,1" newline bitfld.long 0x13C 0. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_ERROR_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_error" "0,1" line.long 0x140 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_4_0,Enable Clear Register 80" bitfld.long 0x140 26. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x140 25. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x140 24. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x140 23. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x140 22. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x140 21. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x140 20. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x140 19. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x140 18. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x140 17. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x140 16. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x140 15. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x140 14. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x140 13. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x140 12. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x140 11. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x140 10. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x140 9. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x140 8. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x140 7. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x140 6. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x140 5. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x140 4. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x140 3. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x140 2. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x140 1. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x140 0. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1" line.long 0x144 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_4_1,Enable Clear Register 81" bitfld.long 0x144 8. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x144 7. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x144 6. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x144 5. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_INT_SZOVF_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x144 4. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x144 3. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x144 2. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x144 1. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x144 0. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x148 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_4_2,Enable Clear Register 82" bitfld.long 0x148 10. "ENABLE_PULSE_VPAC_OUT_4_EN_NF_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x148 9. "ENABLE_PULSE_VPAC_OUT_4_EN_NF_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x148 8. "ENABLE_PULSE_VPAC_OUT_4_EN_NF_FRAME_DONE_CLR,Enable Clear for pulse_vpac_out_4_en_nf_frame_done" "0,1" newline bitfld.long 0x148 3. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x148 2. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x148 1. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for pulse_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x148 0. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for pulse_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x14C "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_4_3,Enable Clear Register 83" bitfld.long 0x14C 26. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for pulse_vpac_out_4_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x14C 25. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for pulse_vpac_out_4_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x14C 24. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for pulse_vpac_out_4_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x14C 22. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for pulse_vpac_out_4_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x14C 20. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_vpac_out_4_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x14C 19. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for pulse_vpac_out_4_en_spare_pend_1_level" "0,1" newline bitfld.long 0x14C 18. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for pulse_vpac_out_4_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x14C 17. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for pulse_vpac_out_4_en_spare_pend_0_level" "0,1" newline bitfld.long 0x14C 16. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for pulse_vpac_out_4_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x14C 15. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_vpac_out_4_en_spare_dec_1" "0,1" newline bitfld.long 0x14C 14. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_vpac_out_4_en_spare_dec_0" "0,1" newline bitfld.long 0x14C 13. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_6_CLR,Enable Clear for pulse_vpac_out_4_en_tdone_6" "0,1" newline bitfld.long 0x14C 12. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_5_CLR,Enable Clear for pulse_vpac_out_4_en_tdone_5" "0,1" newline bitfld.long 0x14C 11. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_4_CLR,Enable Clear for pulse_vpac_out_4_en_tdone_4" "0,1" newline bitfld.long 0x14C 9. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_2_CLR,Enable Clear for pulse_vpac_out_4_en_tdone_2" "0,1" newline bitfld.long 0x14C 7. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_0_CLR,Enable Clear for pulse_vpac_out_4_en_tdone_0" "0,1" newline bitfld.long 0x14C 6. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_6_CLR,Enable Clear for pulse_vpac_out_4_en_pipe_done_6" "0,1" newline bitfld.long 0x14C 5. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_5_CLR,Enable Clear for pulse_vpac_out_4_en_pipe_done_5" "0,1" newline bitfld.long 0x14C 4. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_4_CLR,Enable Clear for pulse_vpac_out_4_en_pipe_done_4" "0,1" newline bitfld.long 0x14C 3. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_vpac_out_4_en_pipe_done_3" "0,1" newline bitfld.long 0x14C 2. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_vpac_out_4_en_pipe_done_2" "0,1" newline bitfld.long 0x14C 1. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_vpac_out_4_en_pipe_done_1" "0,1" newline bitfld.long 0x14C 0. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_vpac_out_4_en_pipe_done_0" "0,1" line.long 0x150 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_4_4,Enable Clear Register 84" bitfld.long 0x150 31. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_31" "0,1" newline bitfld.long 0x150 30. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_30" "0,1" newline bitfld.long 0x150 29. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_29" "0,1" newline bitfld.long 0x150 28. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_28" "0,1" newline bitfld.long 0x150 27. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_27" "0,1" newline bitfld.long 0x150 26. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_26" "0,1" newline bitfld.long 0x150 25. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_25" "0,1" newline bitfld.long 0x150 24. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_24" "0,1" newline bitfld.long 0x150 23. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_23" "0,1" newline bitfld.long 0x150 22. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_22" "0,1" newline bitfld.long 0x150 21. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_21" "0,1" newline bitfld.long 0x150 20. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_20" "0,1" newline bitfld.long 0x150 19. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_19" "0,1" newline bitfld.long 0x150 18. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_18" "0,1" newline bitfld.long 0x150 17. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_17" "0,1" newline bitfld.long 0x150 16. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_16" "0,1" newline bitfld.long 0x150 15. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_15" "0,1" newline bitfld.long 0x150 14. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_14" "0,1" newline bitfld.long 0x150 13. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_13" "0,1" newline bitfld.long 0x150 12. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_12" "0,1" newline bitfld.long 0x150 11. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_11" "0,1" newline bitfld.long 0x150 10. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_10" "0,1" newline bitfld.long 0x150 9. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_9" "0,1" newline bitfld.long 0x150 8. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_8" "0,1" newline bitfld.long 0x150 7. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_7" "0,1" newline bitfld.long 0x150 6. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_6" "0,1" newline bitfld.long 0x150 5. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_5" "0,1" newline bitfld.long 0x150 4. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_4" "0,1" newline bitfld.long 0x150 3. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_3" "0,1" newline bitfld.long 0x150 2. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_2" "0,1" newline bitfld.long 0x150 1. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_1" "0,1" newline bitfld.long 0x150 0. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_0" "0,1" line.long 0x154 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_4_5,Enable Clear Register 85" bitfld.long 0x154 31. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_31" "0,1" newline bitfld.long 0x154 30. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_30" "0,1" newline bitfld.long 0x154 29. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_29" "0,1" newline bitfld.long 0x154 28. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_28" "0,1" newline bitfld.long 0x154 27. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_27" "0,1" newline bitfld.long 0x154 26. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_26" "0,1" newline bitfld.long 0x154 25. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_25" "0,1" newline bitfld.long 0x154 24. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_24" "0,1" newline bitfld.long 0x154 23. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_23" "0,1" newline bitfld.long 0x154 22. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_22" "0,1" newline bitfld.long 0x154 21. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_21" "0,1" newline bitfld.long 0x154 20. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_20" "0,1" newline bitfld.long 0x154 19. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_19" "0,1" newline bitfld.long 0x154 18. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_18" "0,1" newline bitfld.long 0x154 17. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_17" "0,1" newline bitfld.long 0x154 16. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_16" "0,1" newline bitfld.long 0x154 15. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_15" "0,1" newline bitfld.long 0x154 14. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_14" "0,1" newline bitfld.long 0x154 13. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_13" "0,1" newline bitfld.long 0x154 12. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_12" "0,1" newline bitfld.long 0x154 11. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_11" "0,1" newline bitfld.long 0x154 10. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_10" "0,1" newline bitfld.long 0x154 9. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_9" "0,1" newline bitfld.long 0x154 8. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_8" "0,1" newline bitfld.long 0x154 7. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_7" "0,1" newline bitfld.long 0x154 6. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_6" "0,1" newline bitfld.long 0x154 5. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_5" "0,1" newline bitfld.long 0x154 4. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_4" "0,1" newline bitfld.long 0x154 3. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_3" "0,1" newline bitfld.long 0x154 2. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_2" "0,1" newline bitfld.long 0x154 1. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_1" "0,1" newline bitfld.long 0x154 0. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_0" "0,1" line.long 0x158 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_4_6,Enable Clear Register 86" bitfld.long 0x158 31. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_63_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_63" "0,1" newline bitfld.long 0x158 30. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_62_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_62" "0,1" newline bitfld.long 0x158 29. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_61_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_61" "0,1" newline bitfld.long 0x158 28. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_60_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_60" "0,1" newline bitfld.long 0x158 27. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_59_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_59" "0,1" newline bitfld.long 0x158 26. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_58_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_58" "0,1" newline bitfld.long 0x158 25. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_57_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_57" "0,1" newline bitfld.long 0x158 24. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_56_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_56" "0,1" newline bitfld.long 0x158 23. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_55_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_55" "0,1" newline bitfld.long 0x158 22. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_54_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_54" "0,1" newline bitfld.long 0x158 21. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_53_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_53" "0,1" newline bitfld.long 0x158 20. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_52_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_52" "0,1" newline bitfld.long 0x158 19. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_51_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_51" "0,1" newline bitfld.long 0x158 18. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_50_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_50" "0,1" newline bitfld.long 0x158 17. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_49_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_49" "0,1" newline bitfld.long 0x158 16. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_48_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_48" "0,1" newline bitfld.long 0x158 15. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_47_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_47" "0,1" newline bitfld.long 0x158 14. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_46_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_46" "0,1" newline bitfld.long 0x158 13. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_45_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_45" "0,1" newline bitfld.long 0x158 12. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_44_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_44" "0,1" newline bitfld.long 0x158 11. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_43_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_43" "0,1" newline bitfld.long 0x158 10. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_42_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_42" "0,1" newline bitfld.long 0x158 9. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_41_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_41" "0,1" newline bitfld.long 0x158 8. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_40_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_40" "0,1" newline bitfld.long 0x158 7. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_39_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_39" "0,1" newline bitfld.long 0x158 6. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_38_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_38" "0,1" newline bitfld.long 0x158 5. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_37_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_37" "0,1" newline bitfld.long 0x158 4. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_36_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_36" "0,1" newline bitfld.long 0x158 3. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_35_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_35" "0,1" newline bitfld.long 0x158 2. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_34_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_34" "0,1" newline bitfld.long 0x158 1. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_33_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_33" "0,1" newline bitfld.long 0x158 0. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_32_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_32" "0,1" line.long 0x15C "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_4_7,Enable Clear Register 87" bitfld.long 0x15C 4. "ENABLE_PULSE_VPAC_OUT_4_EN_CTM_PULSE_CLR,Enable Clear for pulse_vpac_out_4_en_ctm_pulse" "0,1" newline bitfld.long 0x15C 3. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_prot_err" "0,1" newline bitfld.long 0x15C 2. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_prot_err" "0,1" newline bitfld.long 0x15C 1. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_ERROR_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_error" "0,1" newline bitfld.long 0x15C 0. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_ERROR_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_error" "0,1" line.long 0x160 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_5_0,Enable Clear Register 88" bitfld.long 0x160 26. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x160 25. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x160 24. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x160 23. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x160 22. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x160 21. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x160 20. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x160 19. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x160 18. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x160 17. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x160 16. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x160 15. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x160 14. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x160 13. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x160 12. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x160 11. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x160 10. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x160 9. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x160 8. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x160 7. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x160 6. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x160 5. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x160 4. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x160 3. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x160 2. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x160 1. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x160 0. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1" line.long 0x164 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_5_1,Enable Clear Register 89" bitfld.long 0x164 8. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x164 7. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x164 6. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x164 5. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_INT_SZOVF_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x164 4. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x164 3. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x164 2. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x164 1. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x164 0. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x168 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_5_2,Enable Clear Register 90" bitfld.long 0x168 10. "ENABLE_PULSE_VPAC_OUT_5_EN_NF_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x168 9. "ENABLE_PULSE_VPAC_OUT_5_EN_NF_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x168 8. "ENABLE_PULSE_VPAC_OUT_5_EN_NF_FRAME_DONE_CLR,Enable Clear for pulse_vpac_out_5_en_nf_frame_done" "0,1" newline bitfld.long 0x168 3. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x168 2. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x168 1. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for pulse_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x168 0. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for pulse_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x16C "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_5_3,Enable Clear Register 91" bitfld.long 0x16C 26. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for pulse_vpac_out_5_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x16C 25. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for pulse_vpac_out_5_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x16C 24. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for pulse_vpac_out_5_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x16C 22. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for pulse_vpac_out_5_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x16C 20. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_vpac_out_5_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x16C 19. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for pulse_vpac_out_5_en_spare_pend_1_level" "0,1" newline bitfld.long 0x16C 18. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for pulse_vpac_out_5_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x16C 17. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for pulse_vpac_out_5_en_spare_pend_0_level" "0,1" newline bitfld.long 0x16C 16. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for pulse_vpac_out_5_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x16C 15. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_vpac_out_5_en_spare_dec_1" "0,1" newline bitfld.long 0x16C 14. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_vpac_out_5_en_spare_dec_0" "0,1" newline bitfld.long 0x16C 13. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_6_CLR,Enable Clear for pulse_vpac_out_5_en_tdone_6" "0,1" newline bitfld.long 0x16C 12. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_5_CLR,Enable Clear for pulse_vpac_out_5_en_tdone_5" "0,1" newline bitfld.long 0x16C 11. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_4_CLR,Enable Clear for pulse_vpac_out_5_en_tdone_4" "0,1" newline bitfld.long 0x16C 9. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_2_CLR,Enable Clear for pulse_vpac_out_5_en_tdone_2" "0,1" newline bitfld.long 0x16C 7. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_0_CLR,Enable Clear for pulse_vpac_out_5_en_tdone_0" "0,1" newline bitfld.long 0x16C 6. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_6_CLR,Enable Clear for pulse_vpac_out_5_en_pipe_done_6" "0,1" newline bitfld.long 0x16C 5. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_5_CLR,Enable Clear for pulse_vpac_out_5_en_pipe_done_5" "0,1" newline bitfld.long 0x16C 4. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_4_CLR,Enable Clear for pulse_vpac_out_5_en_pipe_done_4" "0,1" newline bitfld.long 0x16C 3. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_vpac_out_5_en_pipe_done_3" "0,1" newline bitfld.long 0x16C 2. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_vpac_out_5_en_pipe_done_2" "0,1" newline bitfld.long 0x16C 1. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_vpac_out_5_en_pipe_done_1" "0,1" newline bitfld.long 0x16C 0. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_vpac_out_5_en_pipe_done_0" "0,1" line.long 0x170 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_5_4,Enable Clear Register 92" bitfld.long 0x170 31. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_31" "0,1" newline bitfld.long 0x170 30. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_30" "0,1" newline bitfld.long 0x170 29. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_29" "0,1" newline bitfld.long 0x170 28. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_28" "0,1" newline bitfld.long 0x170 27. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_27" "0,1" newline bitfld.long 0x170 26. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_26" "0,1" newline bitfld.long 0x170 25. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_25" "0,1" newline bitfld.long 0x170 24. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_24" "0,1" newline bitfld.long 0x170 23. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_23" "0,1" newline bitfld.long 0x170 22. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_22" "0,1" newline bitfld.long 0x170 21. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_21" "0,1" newline bitfld.long 0x170 20. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_20" "0,1" newline bitfld.long 0x170 19. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_19" "0,1" newline bitfld.long 0x170 18. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_18" "0,1" newline bitfld.long 0x170 17. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_17" "0,1" newline bitfld.long 0x170 16. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_16" "0,1" newline bitfld.long 0x170 15. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_15" "0,1" newline bitfld.long 0x170 14. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_14" "0,1" newline bitfld.long 0x170 13. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_13" "0,1" newline bitfld.long 0x170 12. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_12" "0,1" newline bitfld.long 0x170 11. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_11" "0,1" newline bitfld.long 0x170 10. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_10" "0,1" newline bitfld.long 0x170 9. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_9" "0,1" newline bitfld.long 0x170 8. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_8" "0,1" newline bitfld.long 0x170 7. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_7" "0,1" newline bitfld.long 0x170 6. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_6" "0,1" newline bitfld.long 0x170 5. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_5" "0,1" newline bitfld.long 0x170 4. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_4" "0,1" newline bitfld.long 0x170 3. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_3" "0,1" newline bitfld.long 0x170 2. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_2" "0,1" newline bitfld.long 0x170 1. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_1" "0,1" newline bitfld.long 0x170 0. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_0" "0,1" line.long 0x174 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_5_5,Enable Clear Register 93" bitfld.long 0x174 31. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_31" "0,1" newline bitfld.long 0x174 30. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_30" "0,1" newline bitfld.long 0x174 29. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_29" "0,1" newline bitfld.long 0x174 28. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_28" "0,1" newline bitfld.long 0x174 27. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_27" "0,1" newline bitfld.long 0x174 26. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_26" "0,1" newline bitfld.long 0x174 25. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_25" "0,1" newline bitfld.long 0x174 24. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_24" "0,1" newline bitfld.long 0x174 23. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_23" "0,1" newline bitfld.long 0x174 22. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_22" "0,1" newline bitfld.long 0x174 21. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_21" "0,1" newline bitfld.long 0x174 20. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_20" "0,1" newline bitfld.long 0x174 19. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_19" "0,1" newline bitfld.long 0x174 18. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_18" "0,1" newline bitfld.long 0x174 17. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_17" "0,1" newline bitfld.long 0x174 16. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_16" "0,1" newline bitfld.long 0x174 15. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_15" "0,1" newline bitfld.long 0x174 14. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_14" "0,1" newline bitfld.long 0x174 13. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_13" "0,1" newline bitfld.long 0x174 12. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_12" "0,1" newline bitfld.long 0x174 11. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_11" "0,1" newline bitfld.long 0x174 10. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_10" "0,1" newline bitfld.long 0x174 9. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_9" "0,1" newline bitfld.long 0x174 8. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_8" "0,1" newline bitfld.long 0x174 7. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_7" "0,1" newline bitfld.long 0x174 6. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_6" "0,1" newline bitfld.long 0x174 5. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_5" "0,1" newline bitfld.long 0x174 4. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_4" "0,1" newline bitfld.long 0x174 3. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_3" "0,1" newline bitfld.long 0x174 2. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_2" "0,1" newline bitfld.long 0x174 1. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_1" "0,1" newline bitfld.long 0x174 0. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_0" "0,1" line.long 0x178 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_5_6,Enable Clear Register 94" bitfld.long 0x178 31. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_63_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_63" "0,1" newline bitfld.long 0x178 30. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_62_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_62" "0,1" newline bitfld.long 0x178 29. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_61_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_61" "0,1" newline bitfld.long 0x178 28. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_60_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_60" "0,1" newline bitfld.long 0x178 27. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_59_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_59" "0,1" newline bitfld.long 0x178 26. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_58_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_58" "0,1" newline bitfld.long 0x178 25. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_57_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_57" "0,1" newline bitfld.long 0x178 24. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_56_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_56" "0,1" newline bitfld.long 0x178 23. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_55_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_55" "0,1" newline bitfld.long 0x178 22. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_54_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_54" "0,1" newline bitfld.long 0x178 21. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_53_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_53" "0,1" newline bitfld.long 0x178 20. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_52_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_52" "0,1" newline bitfld.long 0x178 19. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_51_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_51" "0,1" newline bitfld.long 0x178 18. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_50_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_50" "0,1" newline bitfld.long 0x178 17. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_49_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_49" "0,1" newline bitfld.long 0x178 16. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_48_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_48" "0,1" newline bitfld.long 0x178 15. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_47_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_47" "0,1" newline bitfld.long 0x178 14. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_46_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_46" "0,1" newline bitfld.long 0x178 13. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_45_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_45" "0,1" newline bitfld.long 0x178 12. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_44_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_44" "0,1" newline bitfld.long 0x178 11. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_43_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_43" "0,1" newline bitfld.long 0x178 10. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_42_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_42" "0,1" newline bitfld.long 0x178 9. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_41_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_41" "0,1" newline bitfld.long 0x178 8. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_40_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_40" "0,1" newline bitfld.long 0x178 7. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_39_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_39" "0,1" newline bitfld.long 0x178 6. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_38_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_38" "0,1" newline bitfld.long 0x178 5. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_37_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_37" "0,1" newline bitfld.long 0x178 4. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_36_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_36" "0,1" newline bitfld.long 0x178 3. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_35_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_35" "0,1" newline bitfld.long 0x178 2. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_34_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_34" "0,1" newline bitfld.long 0x178 1. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_33_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_33" "0,1" newline bitfld.long 0x178 0. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_32_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_32" "0,1" line.long 0x17C "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_5_7,Enable Clear Register 95" bitfld.long 0x17C 4. "ENABLE_PULSE_VPAC_OUT_5_EN_CTM_PULSE_CLR,Enable Clear for pulse_vpac_out_5_en_ctm_pulse" "0,1" newline bitfld.long 0x17C 3. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_prot_err" "0,1" newline bitfld.long 0x17C 2. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_prot_err" "0,1" newline bitfld.long 0x17C 1. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_ERROR_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_error" "0,1" newline bitfld.long 0x17C 0. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_ERROR_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_error" "0,1" rgroup.long 0x500++0x17F line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_0_0,Status Register 0" bitfld.long 0x0 26. "STATUS_LEVEL_VPAC_OUT_0_VISS0_CR_CFG_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x0 25. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for level_vpac_out_0_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x0 24. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for level_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x0 23. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x0 22. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x0 21. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x0 20. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for level_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x0 19. "STATUS_LEVEL_VPAC_OUT_0_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x0 18. "STATUS_LEVEL_VPAC_OUT_0_VISS0_EE_CFG_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x0 17. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x0 16. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x0 15. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCC_CFG_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x0 14. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCFA_CFG_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x0 13. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_VP_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x0 12. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x0 11. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x0 10. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_FILT_DONE,Status write 1 to set for level_vpac_out_0_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x0 9. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_FILT_START,Status write 1 to set for level_vpac_out_0_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x0 8. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_CFG_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x0 7. "STATUS_LEVEL_VPAC_OUT_0_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x0 6. "STATUS_LEVEL_VPAC_OUT_0_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x0 5. "STATUS_LEVEL_VPAC_OUT_0_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x0 4. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for level_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x0 3. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for level_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x0 2. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_AF_PULSE,Status write 1 to set for level_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x0 1. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for level_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x0 0. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_CFG_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_0_1,Status Register 1" bitfld.long 0x4 8. "STATUS_LEVEL_VPAC_OUT_0_LDC0_VBUSM_RD_ERR,Status write 1 to set for level_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x4 7. "STATUS_LEVEL_VPAC_OUT_0_LDC0_SL2_WR_ERR,Status write 1 to set for level_vpac_out_0_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x4 6. "STATUS_LEVEL_VPAC_OUT_0_LDC0_FR_DONE_EVT,Status write 1 to set for level_vpac_out_0_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x4 5. "STATUS_LEVEL_VPAC_OUT_0_LDC0_INT_SZOVF,Status write 1 to set for level_vpac_out_0_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x4 4. "STATUS_LEVEL_VPAC_OUT_0_LDC0_IFR_OUTOFBOUND,Status write 1 to set for level_vpac_out_0_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x4 3. "STATUS_LEVEL_VPAC_OUT_0_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x4 2. "STATUS_LEVEL_VPAC_OUT_0_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x4 1. "STATUS_LEVEL_VPAC_OUT_0_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x4 0. "STATUS_LEVEL_VPAC_OUT_0_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x8 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_0_2,Status Register 2" bitfld.long 0x8 10. "STATUS_LEVEL_VPAC_OUT_0_NF_SL2_RD_ERR,Status write 1 to set for level_vpac_out_0_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x8 9. "STATUS_LEVEL_VPAC_OUT_0_NF_SL2_WR_ERR,Status write 1 to set for level_vpac_out_0_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x8 8. "STATUS_LEVEL_VPAC_OUT_0_NF_FRAME_DONE,Status write 1 to set for level_vpac_out_0_en_nf_frame_done" "0,1" newline bitfld.long 0x8 3. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x8 2. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x8 1. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for level_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x8 0. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for level_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xC "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_0_3,Status Register 3" bitfld.long 0xC 26. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_6,Status write 1 to set for level_vpac_out_0_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xC 25. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_5,Status write 1 to set for level_vpac_out_0_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xC 24. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_4,Status write 1 to set for level_vpac_out_0_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xC 22. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_2,Status write 1 to set for level_vpac_out_0_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xC 20. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_vpac_out_0_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0xC 19. "STATUS_LEVEL_VPAC_OUT_0_SPARE_PEND_1_LEVEL,Status for level_vpac_out_0_en_spare_pend_1_level" "0,1" newline rbitfld.long 0xC 18. "STATUS_LEVEL_VPAC_OUT_0_SPARE_PEND_1_PULSE,Status for level_vpac_out_0_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0xC 17. "STATUS_LEVEL_VPAC_OUT_0_SPARE_PEND_0_LEVEL,Status for level_vpac_out_0_en_spare_pend_0_level" "0,1" newline rbitfld.long 0xC 16. "STATUS_LEVEL_VPAC_OUT_0_SPARE_PEND_0_PULSE,Status for level_vpac_out_0_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xC 15. "STATUS_LEVEL_VPAC_OUT_0_SPARE_DEC_1,Status write 1 to set for level_vpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0xC 14. "STATUS_LEVEL_VPAC_OUT_0_SPARE_DEC_0,Status write 1 to set for level_vpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0xC 13. "STATUS_LEVEL_VPAC_OUT_0_TDONE_6,Status write 1 to set for level_vpac_out_0_en_tdone_6" "0,1" newline bitfld.long 0xC 12. "STATUS_LEVEL_VPAC_OUT_0_TDONE_5,Status write 1 to set for level_vpac_out_0_en_tdone_5" "0,1" newline bitfld.long 0xC 11. "STATUS_LEVEL_VPAC_OUT_0_TDONE_4,Status write 1 to set for level_vpac_out_0_en_tdone_4" "0,1" newline bitfld.long 0xC 9. "STATUS_LEVEL_VPAC_OUT_0_TDONE_2,Status write 1 to set for level_vpac_out_0_en_tdone_2" "0,1" newline bitfld.long 0xC 7. "STATUS_LEVEL_VPAC_OUT_0_TDONE_0,Status write 1 to set for level_vpac_out_0_en_tdone_0" "0,1" newline bitfld.long 0xC 6. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_6,Status write 1 to set for level_vpac_out_0_en_pipe_done_6" "0,1" newline bitfld.long 0xC 5. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_5,Status write 1 to set for level_vpac_out_0_en_pipe_done_5" "0,1" newline bitfld.long 0xC 4. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_4,Status write 1 to set for level_vpac_out_0_en_pipe_done_4" "0,1" newline bitfld.long 0xC 3. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_3,Status write 1 to set for level_vpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0xC 2. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_2,Status write 1 to set for level_vpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0xC 1. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_1,Status write 1 to set for level_vpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0xC 0. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_0,Status write 1 to set for level_vpac_out_0_en_pipe_done_0" "0,1" line.long 0x10 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_0_4,Status Register 4" bitfld.long 0x10 31. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_31,Status write 1 to set for level_vpac_out_0_en_utc0_complete_31" "0,1" newline bitfld.long 0x10 30. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_30,Status write 1 to set for level_vpac_out_0_en_utc0_complete_30" "0,1" newline bitfld.long 0x10 29. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_29,Status write 1 to set for level_vpac_out_0_en_utc0_complete_29" "0,1" newline bitfld.long 0x10 28. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_28,Status write 1 to set for level_vpac_out_0_en_utc0_complete_28" "0,1" newline bitfld.long 0x10 27. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_27,Status write 1 to set for level_vpac_out_0_en_utc0_complete_27" "0,1" newline bitfld.long 0x10 26. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_26,Status write 1 to set for level_vpac_out_0_en_utc0_complete_26" "0,1" newline bitfld.long 0x10 25. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_25,Status write 1 to set for level_vpac_out_0_en_utc0_complete_25" "0,1" newline bitfld.long 0x10 24. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_24,Status write 1 to set for level_vpac_out_0_en_utc0_complete_24" "0,1" newline bitfld.long 0x10 23. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_23,Status write 1 to set for level_vpac_out_0_en_utc0_complete_23" "0,1" newline bitfld.long 0x10 22. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_22,Status write 1 to set for level_vpac_out_0_en_utc0_complete_22" "0,1" newline bitfld.long 0x10 21. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_21,Status write 1 to set for level_vpac_out_0_en_utc0_complete_21" "0,1" newline bitfld.long 0x10 20. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_20,Status write 1 to set for level_vpac_out_0_en_utc0_complete_20" "0,1" newline bitfld.long 0x10 19. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_19,Status write 1 to set for level_vpac_out_0_en_utc0_complete_19" "0,1" newline bitfld.long 0x10 18. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_18,Status write 1 to set for level_vpac_out_0_en_utc0_complete_18" "0,1" newline bitfld.long 0x10 17. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_17,Status write 1 to set for level_vpac_out_0_en_utc0_complete_17" "0,1" newline bitfld.long 0x10 16. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_16,Status write 1 to set for level_vpac_out_0_en_utc0_complete_16" "0,1" newline bitfld.long 0x10 15. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_15,Status write 1 to set for level_vpac_out_0_en_utc0_complete_15" "0,1" newline bitfld.long 0x10 14. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_14,Status write 1 to set for level_vpac_out_0_en_utc0_complete_14" "0,1" newline bitfld.long 0x10 13. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_13,Status write 1 to set for level_vpac_out_0_en_utc0_complete_13" "0,1" newline bitfld.long 0x10 12. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_12,Status write 1 to set for level_vpac_out_0_en_utc0_complete_12" "0,1" newline bitfld.long 0x10 11. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_11,Status write 1 to set for level_vpac_out_0_en_utc0_complete_11" "0,1" newline bitfld.long 0x10 10. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_10,Status write 1 to set for level_vpac_out_0_en_utc0_complete_10" "0,1" newline bitfld.long 0x10 9. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_9,Status write 1 to set for level_vpac_out_0_en_utc0_complete_9" "0,1" newline bitfld.long 0x10 8. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_8,Status write 1 to set for level_vpac_out_0_en_utc0_complete_8" "0,1" newline bitfld.long 0x10 7. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_7,Status write 1 to set for level_vpac_out_0_en_utc0_complete_7" "0,1" newline bitfld.long 0x10 6. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_6,Status write 1 to set for level_vpac_out_0_en_utc0_complete_6" "0,1" newline bitfld.long 0x10 5. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_5,Status write 1 to set for level_vpac_out_0_en_utc0_complete_5" "0,1" newline bitfld.long 0x10 4. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_4,Status write 1 to set for level_vpac_out_0_en_utc0_complete_4" "0,1" newline bitfld.long 0x10 3. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_3,Status write 1 to set for level_vpac_out_0_en_utc0_complete_3" "0,1" newline bitfld.long 0x10 2. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_2,Status write 1 to set for level_vpac_out_0_en_utc0_complete_2" "0,1" newline bitfld.long 0x10 1. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_1,Status write 1 to set for level_vpac_out_0_en_utc0_complete_1" "0,1" newline bitfld.long 0x10 0. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_0,Status write 1 to set for level_vpac_out_0_en_utc0_complete_0" "0,1" line.long 0x14 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_0_5,Status Register 5" bitfld.long 0x14 31. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_31,Status write 1 to set for level_vpac_out_0_en_utc1_complete_31" "0,1" newline bitfld.long 0x14 30. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_30,Status write 1 to set for level_vpac_out_0_en_utc1_complete_30" "0,1" newline bitfld.long 0x14 29. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_29,Status write 1 to set for level_vpac_out_0_en_utc1_complete_29" "0,1" newline bitfld.long 0x14 28. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_28,Status write 1 to set for level_vpac_out_0_en_utc1_complete_28" "0,1" newline bitfld.long 0x14 27. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_27,Status write 1 to set for level_vpac_out_0_en_utc1_complete_27" "0,1" newline bitfld.long 0x14 26. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_26,Status write 1 to set for level_vpac_out_0_en_utc1_complete_26" "0,1" newline bitfld.long 0x14 25. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_25,Status write 1 to set for level_vpac_out_0_en_utc1_complete_25" "0,1" newline bitfld.long 0x14 24. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_24,Status write 1 to set for level_vpac_out_0_en_utc1_complete_24" "0,1" newline bitfld.long 0x14 23. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_23,Status write 1 to set for level_vpac_out_0_en_utc1_complete_23" "0,1" newline bitfld.long 0x14 22. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_22,Status write 1 to set for level_vpac_out_0_en_utc1_complete_22" "0,1" newline bitfld.long 0x14 21. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_21,Status write 1 to set for level_vpac_out_0_en_utc1_complete_21" "0,1" newline bitfld.long 0x14 20. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_20,Status write 1 to set for level_vpac_out_0_en_utc1_complete_20" "0,1" newline bitfld.long 0x14 19. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_19,Status write 1 to set for level_vpac_out_0_en_utc1_complete_19" "0,1" newline bitfld.long 0x14 18. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_18,Status write 1 to set for level_vpac_out_0_en_utc1_complete_18" "0,1" newline bitfld.long 0x14 17. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_17,Status write 1 to set for level_vpac_out_0_en_utc1_complete_17" "0,1" newline bitfld.long 0x14 16. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_16,Status write 1 to set for level_vpac_out_0_en_utc1_complete_16" "0,1" newline bitfld.long 0x14 15. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_15,Status write 1 to set for level_vpac_out_0_en_utc1_complete_15" "0,1" newline bitfld.long 0x14 14. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_14,Status write 1 to set for level_vpac_out_0_en_utc1_complete_14" "0,1" newline bitfld.long 0x14 13. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_13,Status write 1 to set for level_vpac_out_0_en_utc1_complete_13" "0,1" newline bitfld.long 0x14 12. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_12,Status write 1 to set for level_vpac_out_0_en_utc1_complete_12" "0,1" newline bitfld.long 0x14 11. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_11,Status write 1 to set for level_vpac_out_0_en_utc1_complete_11" "0,1" newline bitfld.long 0x14 10. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_10,Status write 1 to set for level_vpac_out_0_en_utc1_complete_10" "0,1" newline bitfld.long 0x14 9. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_9,Status write 1 to set for level_vpac_out_0_en_utc1_complete_9" "0,1" newline bitfld.long 0x14 8. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_8,Status write 1 to set for level_vpac_out_0_en_utc1_complete_8" "0,1" newline bitfld.long 0x14 7. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_7,Status write 1 to set for level_vpac_out_0_en_utc1_complete_7" "0,1" newline bitfld.long 0x14 6. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_6,Status write 1 to set for level_vpac_out_0_en_utc1_complete_6" "0,1" newline bitfld.long 0x14 5. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_5,Status write 1 to set for level_vpac_out_0_en_utc1_complete_5" "0,1" newline bitfld.long 0x14 4. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_4,Status write 1 to set for level_vpac_out_0_en_utc1_complete_4" "0,1" newline bitfld.long 0x14 3. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_3,Status write 1 to set for level_vpac_out_0_en_utc1_complete_3" "0,1" newline bitfld.long 0x14 2. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_2,Status write 1 to set for level_vpac_out_0_en_utc1_complete_2" "0,1" newline bitfld.long 0x14 1. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_1,Status write 1 to set for level_vpac_out_0_en_utc1_complete_1" "0,1" newline bitfld.long 0x14 0. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_0,Status write 1 to set for level_vpac_out_0_en_utc1_complete_0" "0,1" line.long 0x18 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_0_6,Status Register 6" bitfld.long 0x18 31. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_63,Status write 1 to set for level_vpac_out_0_en_utc1_complete_63" "0,1" newline bitfld.long 0x18 30. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_62,Status write 1 to set for level_vpac_out_0_en_utc1_complete_62" "0,1" newline bitfld.long 0x18 29. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_61,Status write 1 to set for level_vpac_out_0_en_utc1_complete_61" "0,1" newline bitfld.long 0x18 28. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_60,Status write 1 to set for level_vpac_out_0_en_utc1_complete_60" "0,1" newline bitfld.long 0x18 27. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_59,Status write 1 to set for level_vpac_out_0_en_utc1_complete_59" "0,1" newline bitfld.long 0x18 26. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_58,Status write 1 to set for level_vpac_out_0_en_utc1_complete_58" "0,1" newline bitfld.long 0x18 25. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_57,Status write 1 to set for level_vpac_out_0_en_utc1_complete_57" "0,1" newline bitfld.long 0x18 24. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_56,Status write 1 to set for level_vpac_out_0_en_utc1_complete_56" "0,1" newline bitfld.long 0x18 23. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_55,Status write 1 to set for level_vpac_out_0_en_utc1_complete_55" "0,1" newline bitfld.long 0x18 22. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_54,Status write 1 to set for level_vpac_out_0_en_utc1_complete_54" "0,1" newline bitfld.long 0x18 21. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_53,Status write 1 to set for level_vpac_out_0_en_utc1_complete_53" "0,1" newline bitfld.long 0x18 20. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_52,Status write 1 to set for level_vpac_out_0_en_utc1_complete_52" "0,1" newline bitfld.long 0x18 19. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_51,Status write 1 to set for level_vpac_out_0_en_utc1_complete_51" "0,1" newline bitfld.long 0x18 18. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_50,Status write 1 to set for level_vpac_out_0_en_utc1_complete_50" "0,1" newline bitfld.long 0x18 17. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_49,Status write 1 to set for level_vpac_out_0_en_utc1_complete_49" "0,1" newline bitfld.long 0x18 16. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_48,Status write 1 to set for level_vpac_out_0_en_utc1_complete_48" "0,1" newline bitfld.long 0x18 15. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_47,Status write 1 to set for level_vpac_out_0_en_utc1_complete_47" "0,1" newline bitfld.long 0x18 14. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_46,Status write 1 to set for level_vpac_out_0_en_utc1_complete_46" "0,1" newline bitfld.long 0x18 13. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_45,Status write 1 to set for level_vpac_out_0_en_utc1_complete_45" "0,1" newline bitfld.long 0x18 12. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_44,Status write 1 to set for level_vpac_out_0_en_utc1_complete_44" "0,1" newline bitfld.long 0x18 11. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_43,Status write 1 to set for level_vpac_out_0_en_utc1_complete_43" "0,1" newline bitfld.long 0x18 10. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_42,Status write 1 to set for level_vpac_out_0_en_utc1_complete_42" "0,1" newline bitfld.long 0x18 9. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_41,Status write 1 to set for level_vpac_out_0_en_utc1_complete_41" "0,1" newline bitfld.long 0x18 8. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_40,Status write 1 to set for level_vpac_out_0_en_utc1_complete_40" "0,1" newline bitfld.long 0x18 7. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_39,Status write 1 to set for level_vpac_out_0_en_utc1_complete_39" "0,1" newline bitfld.long 0x18 6. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_38,Status write 1 to set for level_vpac_out_0_en_utc1_complete_38" "0,1" newline bitfld.long 0x18 5. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_37,Status write 1 to set for level_vpac_out_0_en_utc1_complete_37" "0,1" newline bitfld.long 0x18 4. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_36,Status write 1 to set for level_vpac_out_0_en_utc1_complete_36" "0,1" newline bitfld.long 0x18 3. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_35,Status write 1 to set for level_vpac_out_0_en_utc1_complete_35" "0,1" newline bitfld.long 0x18 2. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_34,Status write 1 to set for level_vpac_out_0_en_utc1_complete_34" "0,1" newline bitfld.long 0x18 1. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_33,Status write 1 to set for level_vpac_out_0_en_utc1_complete_33" "0,1" newline bitfld.long 0x18 0. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_32,Status write 1 to set for level_vpac_out_0_en_utc1_complete_32" "0,1" line.long 0x1C "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_0_7,Status Register 7" bitfld.long 0x1C 4. "STATUS_LEVEL_VPAC_OUT_0_CTM_PULSE,Status write 1 to set for level_vpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0x1C 3. "STATUS_LEVEL_VPAC_OUT_0_UTC1_PROT_ERR,Status write 1 to set for level_vpac_out_0_en_utc1_prot_err" "0,1" newline bitfld.long 0x1C 2. "STATUS_LEVEL_VPAC_OUT_0_UTC0_PROT_ERR,Status write 1 to set for level_vpac_out_0_en_utc0_prot_err" "0,1" newline bitfld.long 0x1C 1. "STATUS_LEVEL_VPAC_OUT_0_UTC1_ERROR,Status write 1 to set for level_vpac_out_0_en_utc1_error" "0,1" newline bitfld.long 0x1C 0. "STATUS_LEVEL_VPAC_OUT_0_UTC0_ERROR,Status write 1 to set for level_vpac_out_0_en_utc0_error" "0,1" line.long 0x20 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_1_0,Status Register 8" bitfld.long 0x20 26. "STATUS_LEVEL_VPAC_OUT_1_VISS0_CR_CFG_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x20 25. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for level_vpac_out_1_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x20 24. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for level_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x20 23. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x20 22. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x20 21. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x20 20. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for level_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x20 19. "STATUS_LEVEL_VPAC_OUT_1_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x20 18. "STATUS_LEVEL_VPAC_OUT_1_VISS0_EE_CFG_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x20 17. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x20 16. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x20 15. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCC_CFG_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x20 14. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCFA_CFG_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x20 13. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_VP_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x20 12. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x20 11. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x20 10. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_FILT_DONE,Status write 1 to set for level_vpac_out_1_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x20 9. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_FILT_START,Status write 1 to set for level_vpac_out_1_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x20 8. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_CFG_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x20 7. "STATUS_LEVEL_VPAC_OUT_1_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x20 6. "STATUS_LEVEL_VPAC_OUT_1_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x20 5. "STATUS_LEVEL_VPAC_OUT_1_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x20 4. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for level_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x20 3. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for level_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x20 2. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_AF_PULSE,Status write 1 to set for level_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x20 1. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for level_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x20 0. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_CFG_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1" line.long 0x24 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_1_1,Status Register 9" bitfld.long 0x24 8. "STATUS_LEVEL_VPAC_OUT_1_LDC0_VBUSM_RD_ERR,Status write 1 to set for level_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x24 7. "STATUS_LEVEL_VPAC_OUT_1_LDC0_SL2_WR_ERR,Status write 1 to set for level_vpac_out_1_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x24 6. "STATUS_LEVEL_VPAC_OUT_1_LDC0_FR_DONE_EVT,Status write 1 to set for level_vpac_out_1_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x24 5. "STATUS_LEVEL_VPAC_OUT_1_LDC0_INT_SZOVF,Status write 1 to set for level_vpac_out_1_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x24 4. "STATUS_LEVEL_VPAC_OUT_1_LDC0_IFR_OUTOFBOUND,Status write 1 to set for level_vpac_out_1_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x24 3. "STATUS_LEVEL_VPAC_OUT_1_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x24 2. "STATUS_LEVEL_VPAC_OUT_1_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x24 1. "STATUS_LEVEL_VPAC_OUT_1_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x24 0. "STATUS_LEVEL_VPAC_OUT_1_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x28 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_1_2,Status Register 10" bitfld.long 0x28 10. "STATUS_LEVEL_VPAC_OUT_1_NF_SL2_RD_ERR,Status write 1 to set for level_vpac_out_1_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x28 9. "STATUS_LEVEL_VPAC_OUT_1_NF_SL2_WR_ERR,Status write 1 to set for level_vpac_out_1_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x28 8. "STATUS_LEVEL_VPAC_OUT_1_NF_FRAME_DONE,Status write 1 to set for level_vpac_out_1_en_nf_frame_done" "0,1" newline bitfld.long 0x28 3. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x28 2. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x28 1. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for level_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x28 0. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for level_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x2C "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_1_3,Status Register 11" bitfld.long 0x2C 26. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_6,Status write 1 to set for level_vpac_out_1_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x2C 25. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_5,Status write 1 to set for level_vpac_out_1_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x2C 24. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_4,Status write 1 to set for level_vpac_out_1_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x2C 22. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_2,Status write 1 to set for level_vpac_out_1_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x2C 20. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_vpac_out_1_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0x2C 19. "STATUS_LEVEL_VPAC_OUT_1_SPARE_PEND_1_LEVEL,Status for level_vpac_out_1_en_spare_pend_1_level" "0,1" newline rbitfld.long 0x2C 18. "STATUS_LEVEL_VPAC_OUT_1_SPARE_PEND_1_PULSE,Status for level_vpac_out_1_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0x2C 17. "STATUS_LEVEL_VPAC_OUT_1_SPARE_PEND_0_LEVEL,Status for level_vpac_out_1_en_spare_pend_0_level" "0,1" newline rbitfld.long 0x2C 16. "STATUS_LEVEL_VPAC_OUT_1_SPARE_PEND_0_PULSE,Status for level_vpac_out_1_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x2C 15. "STATUS_LEVEL_VPAC_OUT_1_SPARE_DEC_1,Status write 1 to set for level_vpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0x2C 14. "STATUS_LEVEL_VPAC_OUT_1_SPARE_DEC_0,Status write 1 to set for level_vpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0x2C 13. "STATUS_LEVEL_VPAC_OUT_1_TDONE_6,Status write 1 to set for level_vpac_out_1_en_tdone_6" "0,1" newline bitfld.long 0x2C 12. "STATUS_LEVEL_VPAC_OUT_1_TDONE_5,Status write 1 to set for level_vpac_out_1_en_tdone_5" "0,1" newline bitfld.long 0x2C 11. "STATUS_LEVEL_VPAC_OUT_1_TDONE_4,Status write 1 to set for level_vpac_out_1_en_tdone_4" "0,1" newline bitfld.long 0x2C 9. "STATUS_LEVEL_VPAC_OUT_1_TDONE_2,Status write 1 to set for level_vpac_out_1_en_tdone_2" "0,1" newline bitfld.long 0x2C 7. "STATUS_LEVEL_VPAC_OUT_1_TDONE_0,Status write 1 to set for level_vpac_out_1_en_tdone_0" "0,1" newline bitfld.long 0x2C 6. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_6,Status write 1 to set for level_vpac_out_1_en_pipe_done_6" "0,1" newline bitfld.long 0x2C 5. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_5,Status write 1 to set for level_vpac_out_1_en_pipe_done_5" "0,1" newline bitfld.long 0x2C 4. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_4,Status write 1 to set for level_vpac_out_1_en_pipe_done_4" "0,1" newline bitfld.long 0x2C 3. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_3,Status write 1 to set for level_vpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0x2C 2. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_2,Status write 1 to set for level_vpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0x2C 1. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_1,Status write 1 to set for level_vpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0x2C 0. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_0,Status write 1 to set for level_vpac_out_1_en_pipe_done_0" "0,1" line.long 0x30 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_1_4,Status Register 12" bitfld.long 0x30 31. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_31,Status write 1 to set for level_vpac_out_1_en_utc0_complete_31" "0,1" newline bitfld.long 0x30 30. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_30,Status write 1 to set for level_vpac_out_1_en_utc0_complete_30" "0,1" newline bitfld.long 0x30 29. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_29,Status write 1 to set for level_vpac_out_1_en_utc0_complete_29" "0,1" newline bitfld.long 0x30 28. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_28,Status write 1 to set for level_vpac_out_1_en_utc0_complete_28" "0,1" newline bitfld.long 0x30 27. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_27,Status write 1 to set for level_vpac_out_1_en_utc0_complete_27" "0,1" newline bitfld.long 0x30 26. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_26,Status write 1 to set for level_vpac_out_1_en_utc0_complete_26" "0,1" newline bitfld.long 0x30 25. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_25,Status write 1 to set for level_vpac_out_1_en_utc0_complete_25" "0,1" newline bitfld.long 0x30 24. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_24,Status write 1 to set for level_vpac_out_1_en_utc0_complete_24" "0,1" newline bitfld.long 0x30 23. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_23,Status write 1 to set for level_vpac_out_1_en_utc0_complete_23" "0,1" newline bitfld.long 0x30 22. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_22,Status write 1 to set for level_vpac_out_1_en_utc0_complete_22" "0,1" newline bitfld.long 0x30 21. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_21,Status write 1 to set for level_vpac_out_1_en_utc0_complete_21" "0,1" newline bitfld.long 0x30 20. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_20,Status write 1 to set for level_vpac_out_1_en_utc0_complete_20" "0,1" newline bitfld.long 0x30 19. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_19,Status write 1 to set for level_vpac_out_1_en_utc0_complete_19" "0,1" newline bitfld.long 0x30 18. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_18,Status write 1 to set for level_vpac_out_1_en_utc0_complete_18" "0,1" newline bitfld.long 0x30 17. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_17,Status write 1 to set for level_vpac_out_1_en_utc0_complete_17" "0,1" newline bitfld.long 0x30 16. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_16,Status write 1 to set for level_vpac_out_1_en_utc0_complete_16" "0,1" newline bitfld.long 0x30 15. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_15,Status write 1 to set for level_vpac_out_1_en_utc0_complete_15" "0,1" newline bitfld.long 0x30 14. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_14,Status write 1 to set for level_vpac_out_1_en_utc0_complete_14" "0,1" newline bitfld.long 0x30 13. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_13,Status write 1 to set for level_vpac_out_1_en_utc0_complete_13" "0,1" newline bitfld.long 0x30 12. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_12,Status write 1 to set for level_vpac_out_1_en_utc0_complete_12" "0,1" newline bitfld.long 0x30 11. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_11,Status write 1 to set for level_vpac_out_1_en_utc0_complete_11" "0,1" newline bitfld.long 0x30 10. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_10,Status write 1 to set for level_vpac_out_1_en_utc0_complete_10" "0,1" newline bitfld.long 0x30 9. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_9,Status write 1 to set for level_vpac_out_1_en_utc0_complete_9" "0,1" newline bitfld.long 0x30 8. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_8,Status write 1 to set for level_vpac_out_1_en_utc0_complete_8" "0,1" newline bitfld.long 0x30 7. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_7,Status write 1 to set for level_vpac_out_1_en_utc0_complete_7" "0,1" newline bitfld.long 0x30 6. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_6,Status write 1 to set for level_vpac_out_1_en_utc0_complete_6" "0,1" newline bitfld.long 0x30 5. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_5,Status write 1 to set for level_vpac_out_1_en_utc0_complete_5" "0,1" newline bitfld.long 0x30 4. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_4,Status write 1 to set for level_vpac_out_1_en_utc0_complete_4" "0,1" newline bitfld.long 0x30 3. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_3,Status write 1 to set for level_vpac_out_1_en_utc0_complete_3" "0,1" newline bitfld.long 0x30 2. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_2,Status write 1 to set for level_vpac_out_1_en_utc0_complete_2" "0,1" newline bitfld.long 0x30 1. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_1,Status write 1 to set for level_vpac_out_1_en_utc0_complete_1" "0,1" newline bitfld.long 0x30 0. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_0,Status write 1 to set for level_vpac_out_1_en_utc0_complete_0" "0,1" line.long 0x34 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_1_5,Status Register 13" bitfld.long 0x34 31. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_31,Status write 1 to set for level_vpac_out_1_en_utc1_complete_31" "0,1" newline bitfld.long 0x34 30. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_30,Status write 1 to set for level_vpac_out_1_en_utc1_complete_30" "0,1" newline bitfld.long 0x34 29. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_29,Status write 1 to set for level_vpac_out_1_en_utc1_complete_29" "0,1" newline bitfld.long 0x34 28. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_28,Status write 1 to set for level_vpac_out_1_en_utc1_complete_28" "0,1" newline bitfld.long 0x34 27. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_27,Status write 1 to set for level_vpac_out_1_en_utc1_complete_27" "0,1" newline bitfld.long 0x34 26. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_26,Status write 1 to set for level_vpac_out_1_en_utc1_complete_26" "0,1" newline bitfld.long 0x34 25. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_25,Status write 1 to set for level_vpac_out_1_en_utc1_complete_25" "0,1" newline bitfld.long 0x34 24. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_24,Status write 1 to set for level_vpac_out_1_en_utc1_complete_24" "0,1" newline bitfld.long 0x34 23. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_23,Status write 1 to set for level_vpac_out_1_en_utc1_complete_23" "0,1" newline bitfld.long 0x34 22. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_22,Status write 1 to set for level_vpac_out_1_en_utc1_complete_22" "0,1" newline bitfld.long 0x34 21. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_21,Status write 1 to set for level_vpac_out_1_en_utc1_complete_21" "0,1" newline bitfld.long 0x34 20. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_20,Status write 1 to set for level_vpac_out_1_en_utc1_complete_20" "0,1" newline bitfld.long 0x34 19. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_19,Status write 1 to set for level_vpac_out_1_en_utc1_complete_19" "0,1" newline bitfld.long 0x34 18. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_18,Status write 1 to set for level_vpac_out_1_en_utc1_complete_18" "0,1" newline bitfld.long 0x34 17. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_17,Status write 1 to set for level_vpac_out_1_en_utc1_complete_17" "0,1" newline bitfld.long 0x34 16. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_16,Status write 1 to set for level_vpac_out_1_en_utc1_complete_16" "0,1" newline bitfld.long 0x34 15. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_15,Status write 1 to set for level_vpac_out_1_en_utc1_complete_15" "0,1" newline bitfld.long 0x34 14. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_14,Status write 1 to set for level_vpac_out_1_en_utc1_complete_14" "0,1" newline bitfld.long 0x34 13. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_13,Status write 1 to set for level_vpac_out_1_en_utc1_complete_13" "0,1" newline bitfld.long 0x34 12. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_12,Status write 1 to set for level_vpac_out_1_en_utc1_complete_12" "0,1" newline bitfld.long 0x34 11. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_11,Status write 1 to set for level_vpac_out_1_en_utc1_complete_11" "0,1" newline bitfld.long 0x34 10. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_10,Status write 1 to set for level_vpac_out_1_en_utc1_complete_10" "0,1" newline bitfld.long 0x34 9. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_9,Status write 1 to set for level_vpac_out_1_en_utc1_complete_9" "0,1" newline bitfld.long 0x34 8. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_8,Status write 1 to set for level_vpac_out_1_en_utc1_complete_8" "0,1" newline bitfld.long 0x34 7. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_7,Status write 1 to set for level_vpac_out_1_en_utc1_complete_7" "0,1" newline bitfld.long 0x34 6. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_6,Status write 1 to set for level_vpac_out_1_en_utc1_complete_6" "0,1" newline bitfld.long 0x34 5. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_5,Status write 1 to set for level_vpac_out_1_en_utc1_complete_5" "0,1" newline bitfld.long 0x34 4. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_4,Status write 1 to set for level_vpac_out_1_en_utc1_complete_4" "0,1" newline bitfld.long 0x34 3. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_3,Status write 1 to set for level_vpac_out_1_en_utc1_complete_3" "0,1" newline bitfld.long 0x34 2. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_2,Status write 1 to set for level_vpac_out_1_en_utc1_complete_2" "0,1" newline bitfld.long 0x34 1. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_1,Status write 1 to set for level_vpac_out_1_en_utc1_complete_1" "0,1" newline bitfld.long 0x34 0. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_0,Status write 1 to set for level_vpac_out_1_en_utc1_complete_0" "0,1" line.long 0x38 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_1_6,Status Register 14" bitfld.long 0x38 31. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_63,Status write 1 to set for level_vpac_out_1_en_utc1_complete_63" "0,1" newline bitfld.long 0x38 30. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_62,Status write 1 to set for level_vpac_out_1_en_utc1_complete_62" "0,1" newline bitfld.long 0x38 29. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_61,Status write 1 to set for level_vpac_out_1_en_utc1_complete_61" "0,1" newline bitfld.long 0x38 28. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_60,Status write 1 to set for level_vpac_out_1_en_utc1_complete_60" "0,1" newline bitfld.long 0x38 27. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_59,Status write 1 to set for level_vpac_out_1_en_utc1_complete_59" "0,1" newline bitfld.long 0x38 26. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_58,Status write 1 to set for level_vpac_out_1_en_utc1_complete_58" "0,1" newline bitfld.long 0x38 25. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_57,Status write 1 to set for level_vpac_out_1_en_utc1_complete_57" "0,1" newline bitfld.long 0x38 24. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_56,Status write 1 to set for level_vpac_out_1_en_utc1_complete_56" "0,1" newline bitfld.long 0x38 23. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_55,Status write 1 to set for level_vpac_out_1_en_utc1_complete_55" "0,1" newline bitfld.long 0x38 22. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_54,Status write 1 to set for level_vpac_out_1_en_utc1_complete_54" "0,1" newline bitfld.long 0x38 21. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_53,Status write 1 to set for level_vpac_out_1_en_utc1_complete_53" "0,1" newline bitfld.long 0x38 20. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_52,Status write 1 to set for level_vpac_out_1_en_utc1_complete_52" "0,1" newline bitfld.long 0x38 19. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_51,Status write 1 to set for level_vpac_out_1_en_utc1_complete_51" "0,1" newline bitfld.long 0x38 18. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_50,Status write 1 to set for level_vpac_out_1_en_utc1_complete_50" "0,1" newline bitfld.long 0x38 17. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_49,Status write 1 to set for level_vpac_out_1_en_utc1_complete_49" "0,1" newline bitfld.long 0x38 16. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_48,Status write 1 to set for level_vpac_out_1_en_utc1_complete_48" "0,1" newline bitfld.long 0x38 15. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_47,Status write 1 to set for level_vpac_out_1_en_utc1_complete_47" "0,1" newline bitfld.long 0x38 14. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_46,Status write 1 to set for level_vpac_out_1_en_utc1_complete_46" "0,1" newline bitfld.long 0x38 13. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_45,Status write 1 to set for level_vpac_out_1_en_utc1_complete_45" "0,1" newline bitfld.long 0x38 12. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_44,Status write 1 to set for level_vpac_out_1_en_utc1_complete_44" "0,1" newline bitfld.long 0x38 11. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_43,Status write 1 to set for level_vpac_out_1_en_utc1_complete_43" "0,1" newline bitfld.long 0x38 10. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_42,Status write 1 to set for level_vpac_out_1_en_utc1_complete_42" "0,1" newline bitfld.long 0x38 9. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_41,Status write 1 to set for level_vpac_out_1_en_utc1_complete_41" "0,1" newline bitfld.long 0x38 8. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_40,Status write 1 to set for level_vpac_out_1_en_utc1_complete_40" "0,1" newline bitfld.long 0x38 7. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_39,Status write 1 to set for level_vpac_out_1_en_utc1_complete_39" "0,1" newline bitfld.long 0x38 6. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_38,Status write 1 to set for level_vpac_out_1_en_utc1_complete_38" "0,1" newline bitfld.long 0x38 5. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_37,Status write 1 to set for level_vpac_out_1_en_utc1_complete_37" "0,1" newline bitfld.long 0x38 4. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_36,Status write 1 to set for level_vpac_out_1_en_utc1_complete_36" "0,1" newline bitfld.long 0x38 3. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_35,Status write 1 to set for level_vpac_out_1_en_utc1_complete_35" "0,1" newline bitfld.long 0x38 2. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_34,Status write 1 to set for level_vpac_out_1_en_utc1_complete_34" "0,1" newline bitfld.long 0x38 1. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_33,Status write 1 to set for level_vpac_out_1_en_utc1_complete_33" "0,1" newline bitfld.long 0x38 0. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_32,Status write 1 to set for level_vpac_out_1_en_utc1_complete_32" "0,1" line.long 0x3C "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_1_7,Status Register 15" bitfld.long 0x3C 4. "STATUS_LEVEL_VPAC_OUT_1_CTM_PULSE,Status write 1 to set for level_vpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0x3C 3. "STATUS_LEVEL_VPAC_OUT_1_UTC1_PROT_ERR,Status write 1 to set for level_vpac_out_1_en_utc1_prot_err" "0,1" newline bitfld.long 0x3C 2. "STATUS_LEVEL_VPAC_OUT_1_UTC0_PROT_ERR,Status write 1 to set for level_vpac_out_1_en_utc0_prot_err" "0,1" newline bitfld.long 0x3C 1. "STATUS_LEVEL_VPAC_OUT_1_UTC1_ERROR,Status write 1 to set for level_vpac_out_1_en_utc1_error" "0,1" newline bitfld.long 0x3C 0. "STATUS_LEVEL_VPAC_OUT_1_UTC0_ERROR,Status write 1 to set for level_vpac_out_1_en_utc0_error" "0,1" line.long 0x40 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_2_0,Status Register 16" bitfld.long 0x40 26. "STATUS_LEVEL_VPAC_OUT_2_VISS0_CR_CFG_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x40 25. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for level_vpac_out_2_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x40 24. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for level_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x40 23. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x40 22. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x40 21. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x40 20. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for level_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x40 19. "STATUS_LEVEL_VPAC_OUT_2_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x40 18. "STATUS_LEVEL_VPAC_OUT_2_VISS0_EE_CFG_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x40 17. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x40 16. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x40 15. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCC_CFG_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x40 14. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCFA_CFG_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x40 13. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_VP_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x40 12. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x40 11. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x40 10. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_FILT_DONE,Status write 1 to set for level_vpac_out_2_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x40 9. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_FILT_START,Status write 1 to set for level_vpac_out_2_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x40 8. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_CFG_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x40 7. "STATUS_LEVEL_VPAC_OUT_2_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x40 6. "STATUS_LEVEL_VPAC_OUT_2_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x40 5. "STATUS_LEVEL_VPAC_OUT_2_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x40 4. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for level_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x40 3. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for level_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x40 2. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_AF_PULSE,Status write 1 to set for level_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x40 1. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for level_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x40 0. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_CFG_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1" line.long 0x44 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_2_1,Status Register 17" bitfld.long 0x44 8. "STATUS_LEVEL_VPAC_OUT_2_LDC0_VBUSM_RD_ERR,Status write 1 to set for level_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x44 7. "STATUS_LEVEL_VPAC_OUT_2_LDC0_SL2_WR_ERR,Status write 1 to set for level_vpac_out_2_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x44 6. "STATUS_LEVEL_VPAC_OUT_2_LDC0_FR_DONE_EVT,Status write 1 to set for level_vpac_out_2_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x44 5. "STATUS_LEVEL_VPAC_OUT_2_LDC0_INT_SZOVF,Status write 1 to set for level_vpac_out_2_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x44 4. "STATUS_LEVEL_VPAC_OUT_2_LDC0_IFR_OUTOFBOUND,Status write 1 to set for level_vpac_out_2_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x44 3. "STATUS_LEVEL_VPAC_OUT_2_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x44 2. "STATUS_LEVEL_VPAC_OUT_2_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x44 1. "STATUS_LEVEL_VPAC_OUT_2_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x44 0. "STATUS_LEVEL_VPAC_OUT_2_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x48 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_2_2,Status Register 18" bitfld.long 0x48 10. "STATUS_LEVEL_VPAC_OUT_2_NF_SL2_RD_ERR,Status write 1 to set for level_vpac_out_2_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x48 9. "STATUS_LEVEL_VPAC_OUT_2_NF_SL2_WR_ERR,Status write 1 to set for level_vpac_out_2_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x48 8. "STATUS_LEVEL_VPAC_OUT_2_NF_FRAME_DONE,Status write 1 to set for level_vpac_out_2_en_nf_frame_done" "0,1" newline bitfld.long 0x48 3. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x48 2. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x48 1. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for level_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x48 0. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for level_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x4C "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_2_3,Status Register 19" bitfld.long 0x4C 26. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_6,Status write 1 to set for level_vpac_out_2_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x4C 25. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_5,Status write 1 to set for level_vpac_out_2_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x4C 24. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_4,Status write 1 to set for level_vpac_out_2_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x4C 22. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_2,Status write 1 to set for level_vpac_out_2_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x4C 20. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_vpac_out_2_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0x4C 19. "STATUS_LEVEL_VPAC_OUT_2_SPARE_PEND_1_LEVEL,Status for level_vpac_out_2_en_spare_pend_1_level" "0,1" newline rbitfld.long 0x4C 18. "STATUS_LEVEL_VPAC_OUT_2_SPARE_PEND_1_PULSE,Status for level_vpac_out_2_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0x4C 17. "STATUS_LEVEL_VPAC_OUT_2_SPARE_PEND_0_LEVEL,Status for level_vpac_out_2_en_spare_pend_0_level" "0,1" newline rbitfld.long 0x4C 16. "STATUS_LEVEL_VPAC_OUT_2_SPARE_PEND_0_PULSE,Status for level_vpac_out_2_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x4C 15. "STATUS_LEVEL_VPAC_OUT_2_SPARE_DEC_1,Status write 1 to set for level_vpac_out_2_en_spare_dec_1" "0,1" newline bitfld.long 0x4C 14. "STATUS_LEVEL_VPAC_OUT_2_SPARE_DEC_0,Status write 1 to set for level_vpac_out_2_en_spare_dec_0" "0,1" newline bitfld.long 0x4C 13. "STATUS_LEVEL_VPAC_OUT_2_TDONE_6,Status write 1 to set for level_vpac_out_2_en_tdone_6" "0,1" newline bitfld.long 0x4C 12. "STATUS_LEVEL_VPAC_OUT_2_TDONE_5,Status write 1 to set for level_vpac_out_2_en_tdone_5" "0,1" newline bitfld.long 0x4C 11. "STATUS_LEVEL_VPAC_OUT_2_TDONE_4,Status write 1 to set for level_vpac_out_2_en_tdone_4" "0,1" newline bitfld.long 0x4C 9. "STATUS_LEVEL_VPAC_OUT_2_TDONE_2,Status write 1 to set for level_vpac_out_2_en_tdone_2" "0,1" newline bitfld.long 0x4C 7. "STATUS_LEVEL_VPAC_OUT_2_TDONE_0,Status write 1 to set for level_vpac_out_2_en_tdone_0" "0,1" newline bitfld.long 0x4C 6. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_6,Status write 1 to set for level_vpac_out_2_en_pipe_done_6" "0,1" newline bitfld.long 0x4C 5. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_5,Status write 1 to set for level_vpac_out_2_en_pipe_done_5" "0,1" newline bitfld.long 0x4C 4. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_4,Status write 1 to set for level_vpac_out_2_en_pipe_done_4" "0,1" newline bitfld.long 0x4C 3. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_3,Status write 1 to set for level_vpac_out_2_en_pipe_done_3" "0,1" newline bitfld.long 0x4C 2. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_2,Status write 1 to set for level_vpac_out_2_en_pipe_done_2" "0,1" newline bitfld.long 0x4C 1. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_1,Status write 1 to set for level_vpac_out_2_en_pipe_done_1" "0,1" newline bitfld.long 0x4C 0. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_0,Status write 1 to set for level_vpac_out_2_en_pipe_done_0" "0,1" line.long 0x50 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_2_4,Status Register 20" bitfld.long 0x50 31. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_31,Status write 1 to set for level_vpac_out_2_en_utc0_complete_31" "0,1" newline bitfld.long 0x50 30. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_30,Status write 1 to set for level_vpac_out_2_en_utc0_complete_30" "0,1" newline bitfld.long 0x50 29. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_29,Status write 1 to set for level_vpac_out_2_en_utc0_complete_29" "0,1" newline bitfld.long 0x50 28. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_28,Status write 1 to set for level_vpac_out_2_en_utc0_complete_28" "0,1" newline bitfld.long 0x50 27. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_27,Status write 1 to set for level_vpac_out_2_en_utc0_complete_27" "0,1" newline bitfld.long 0x50 26. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_26,Status write 1 to set for level_vpac_out_2_en_utc0_complete_26" "0,1" newline bitfld.long 0x50 25. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_25,Status write 1 to set for level_vpac_out_2_en_utc0_complete_25" "0,1" newline bitfld.long 0x50 24. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_24,Status write 1 to set for level_vpac_out_2_en_utc0_complete_24" "0,1" newline bitfld.long 0x50 23. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_23,Status write 1 to set for level_vpac_out_2_en_utc0_complete_23" "0,1" newline bitfld.long 0x50 22. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_22,Status write 1 to set for level_vpac_out_2_en_utc0_complete_22" "0,1" newline bitfld.long 0x50 21. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_21,Status write 1 to set for level_vpac_out_2_en_utc0_complete_21" "0,1" newline bitfld.long 0x50 20. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_20,Status write 1 to set for level_vpac_out_2_en_utc0_complete_20" "0,1" newline bitfld.long 0x50 19. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_19,Status write 1 to set for level_vpac_out_2_en_utc0_complete_19" "0,1" newline bitfld.long 0x50 18. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_18,Status write 1 to set for level_vpac_out_2_en_utc0_complete_18" "0,1" newline bitfld.long 0x50 17. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_17,Status write 1 to set for level_vpac_out_2_en_utc0_complete_17" "0,1" newline bitfld.long 0x50 16. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_16,Status write 1 to set for level_vpac_out_2_en_utc0_complete_16" "0,1" newline bitfld.long 0x50 15. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_15,Status write 1 to set for level_vpac_out_2_en_utc0_complete_15" "0,1" newline bitfld.long 0x50 14. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_14,Status write 1 to set for level_vpac_out_2_en_utc0_complete_14" "0,1" newline bitfld.long 0x50 13. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_13,Status write 1 to set for level_vpac_out_2_en_utc0_complete_13" "0,1" newline bitfld.long 0x50 12. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_12,Status write 1 to set for level_vpac_out_2_en_utc0_complete_12" "0,1" newline bitfld.long 0x50 11. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_11,Status write 1 to set for level_vpac_out_2_en_utc0_complete_11" "0,1" newline bitfld.long 0x50 10. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_10,Status write 1 to set for level_vpac_out_2_en_utc0_complete_10" "0,1" newline bitfld.long 0x50 9. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_9,Status write 1 to set for level_vpac_out_2_en_utc0_complete_9" "0,1" newline bitfld.long 0x50 8. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_8,Status write 1 to set for level_vpac_out_2_en_utc0_complete_8" "0,1" newline bitfld.long 0x50 7. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_7,Status write 1 to set for level_vpac_out_2_en_utc0_complete_7" "0,1" newline bitfld.long 0x50 6. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_6,Status write 1 to set for level_vpac_out_2_en_utc0_complete_6" "0,1" newline bitfld.long 0x50 5. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_5,Status write 1 to set for level_vpac_out_2_en_utc0_complete_5" "0,1" newline bitfld.long 0x50 4. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_4,Status write 1 to set for level_vpac_out_2_en_utc0_complete_4" "0,1" newline bitfld.long 0x50 3. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_3,Status write 1 to set for level_vpac_out_2_en_utc0_complete_3" "0,1" newline bitfld.long 0x50 2. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_2,Status write 1 to set for level_vpac_out_2_en_utc0_complete_2" "0,1" newline bitfld.long 0x50 1. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_1,Status write 1 to set for level_vpac_out_2_en_utc0_complete_1" "0,1" newline bitfld.long 0x50 0. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_0,Status write 1 to set for level_vpac_out_2_en_utc0_complete_0" "0,1" line.long 0x54 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_2_5,Status Register 21" bitfld.long 0x54 31. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_31,Status write 1 to set for level_vpac_out_2_en_utc1_complete_31" "0,1" newline bitfld.long 0x54 30. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_30,Status write 1 to set for level_vpac_out_2_en_utc1_complete_30" "0,1" newline bitfld.long 0x54 29. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_29,Status write 1 to set for level_vpac_out_2_en_utc1_complete_29" "0,1" newline bitfld.long 0x54 28. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_28,Status write 1 to set for level_vpac_out_2_en_utc1_complete_28" "0,1" newline bitfld.long 0x54 27. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_27,Status write 1 to set for level_vpac_out_2_en_utc1_complete_27" "0,1" newline bitfld.long 0x54 26. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_26,Status write 1 to set for level_vpac_out_2_en_utc1_complete_26" "0,1" newline bitfld.long 0x54 25. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_25,Status write 1 to set for level_vpac_out_2_en_utc1_complete_25" "0,1" newline bitfld.long 0x54 24. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_24,Status write 1 to set for level_vpac_out_2_en_utc1_complete_24" "0,1" newline bitfld.long 0x54 23. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_23,Status write 1 to set for level_vpac_out_2_en_utc1_complete_23" "0,1" newline bitfld.long 0x54 22. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_22,Status write 1 to set for level_vpac_out_2_en_utc1_complete_22" "0,1" newline bitfld.long 0x54 21. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_21,Status write 1 to set for level_vpac_out_2_en_utc1_complete_21" "0,1" newline bitfld.long 0x54 20. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_20,Status write 1 to set for level_vpac_out_2_en_utc1_complete_20" "0,1" newline bitfld.long 0x54 19. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_19,Status write 1 to set for level_vpac_out_2_en_utc1_complete_19" "0,1" newline bitfld.long 0x54 18. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_18,Status write 1 to set for level_vpac_out_2_en_utc1_complete_18" "0,1" newline bitfld.long 0x54 17. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_17,Status write 1 to set for level_vpac_out_2_en_utc1_complete_17" "0,1" newline bitfld.long 0x54 16. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_16,Status write 1 to set for level_vpac_out_2_en_utc1_complete_16" "0,1" newline bitfld.long 0x54 15. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_15,Status write 1 to set for level_vpac_out_2_en_utc1_complete_15" "0,1" newline bitfld.long 0x54 14. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_14,Status write 1 to set for level_vpac_out_2_en_utc1_complete_14" "0,1" newline bitfld.long 0x54 13. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_13,Status write 1 to set for level_vpac_out_2_en_utc1_complete_13" "0,1" newline bitfld.long 0x54 12. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_12,Status write 1 to set for level_vpac_out_2_en_utc1_complete_12" "0,1" newline bitfld.long 0x54 11. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_11,Status write 1 to set for level_vpac_out_2_en_utc1_complete_11" "0,1" newline bitfld.long 0x54 10. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_10,Status write 1 to set for level_vpac_out_2_en_utc1_complete_10" "0,1" newline bitfld.long 0x54 9. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_9,Status write 1 to set for level_vpac_out_2_en_utc1_complete_9" "0,1" newline bitfld.long 0x54 8. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_8,Status write 1 to set for level_vpac_out_2_en_utc1_complete_8" "0,1" newline bitfld.long 0x54 7. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_7,Status write 1 to set for level_vpac_out_2_en_utc1_complete_7" "0,1" newline bitfld.long 0x54 6. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_6,Status write 1 to set for level_vpac_out_2_en_utc1_complete_6" "0,1" newline bitfld.long 0x54 5. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_5,Status write 1 to set for level_vpac_out_2_en_utc1_complete_5" "0,1" newline bitfld.long 0x54 4. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_4,Status write 1 to set for level_vpac_out_2_en_utc1_complete_4" "0,1" newline bitfld.long 0x54 3. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_3,Status write 1 to set for level_vpac_out_2_en_utc1_complete_3" "0,1" newline bitfld.long 0x54 2. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_2,Status write 1 to set for level_vpac_out_2_en_utc1_complete_2" "0,1" newline bitfld.long 0x54 1. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_1,Status write 1 to set for level_vpac_out_2_en_utc1_complete_1" "0,1" newline bitfld.long 0x54 0. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_0,Status write 1 to set for level_vpac_out_2_en_utc1_complete_0" "0,1" line.long 0x58 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_2_6,Status Register 22" bitfld.long 0x58 31. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_63,Status write 1 to set for level_vpac_out_2_en_utc1_complete_63" "0,1" newline bitfld.long 0x58 30. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_62,Status write 1 to set for level_vpac_out_2_en_utc1_complete_62" "0,1" newline bitfld.long 0x58 29. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_61,Status write 1 to set for level_vpac_out_2_en_utc1_complete_61" "0,1" newline bitfld.long 0x58 28. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_60,Status write 1 to set for level_vpac_out_2_en_utc1_complete_60" "0,1" newline bitfld.long 0x58 27. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_59,Status write 1 to set for level_vpac_out_2_en_utc1_complete_59" "0,1" newline bitfld.long 0x58 26. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_58,Status write 1 to set for level_vpac_out_2_en_utc1_complete_58" "0,1" newline bitfld.long 0x58 25. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_57,Status write 1 to set for level_vpac_out_2_en_utc1_complete_57" "0,1" newline bitfld.long 0x58 24. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_56,Status write 1 to set for level_vpac_out_2_en_utc1_complete_56" "0,1" newline bitfld.long 0x58 23. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_55,Status write 1 to set for level_vpac_out_2_en_utc1_complete_55" "0,1" newline bitfld.long 0x58 22. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_54,Status write 1 to set for level_vpac_out_2_en_utc1_complete_54" "0,1" newline bitfld.long 0x58 21. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_53,Status write 1 to set for level_vpac_out_2_en_utc1_complete_53" "0,1" newline bitfld.long 0x58 20. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_52,Status write 1 to set for level_vpac_out_2_en_utc1_complete_52" "0,1" newline bitfld.long 0x58 19. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_51,Status write 1 to set for level_vpac_out_2_en_utc1_complete_51" "0,1" newline bitfld.long 0x58 18. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_50,Status write 1 to set for level_vpac_out_2_en_utc1_complete_50" "0,1" newline bitfld.long 0x58 17. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_49,Status write 1 to set for level_vpac_out_2_en_utc1_complete_49" "0,1" newline bitfld.long 0x58 16. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_48,Status write 1 to set for level_vpac_out_2_en_utc1_complete_48" "0,1" newline bitfld.long 0x58 15. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_47,Status write 1 to set for level_vpac_out_2_en_utc1_complete_47" "0,1" newline bitfld.long 0x58 14. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_46,Status write 1 to set for level_vpac_out_2_en_utc1_complete_46" "0,1" newline bitfld.long 0x58 13. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_45,Status write 1 to set for level_vpac_out_2_en_utc1_complete_45" "0,1" newline bitfld.long 0x58 12. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_44,Status write 1 to set for level_vpac_out_2_en_utc1_complete_44" "0,1" newline bitfld.long 0x58 11. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_43,Status write 1 to set for level_vpac_out_2_en_utc1_complete_43" "0,1" newline bitfld.long 0x58 10. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_42,Status write 1 to set for level_vpac_out_2_en_utc1_complete_42" "0,1" newline bitfld.long 0x58 9. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_41,Status write 1 to set for level_vpac_out_2_en_utc1_complete_41" "0,1" newline bitfld.long 0x58 8. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_40,Status write 1 to set for level_vpac_out_2_en_utc1_complete_40" "0,1" newline bitfld.long 0x58 7. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_39,Status write 1 to set for level_vpac_out_2_en_utc1_complete_39" "0,1" newline bitfld.long 0x58 6. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_38,Status write 1 to set for level_vpac_out_2_en_utc1_complete_38" "0,1" newline bitfld.long 0x58 5. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_37,Status write 1 to set for level_vpac_out_2_en_utc1_complete_37" "0,1" newline bitfld.long 0x58 4. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_36,Status write 1 to set for level_vpac_out_2_en_utc1_complete_36" "0,1" newline bitfld.long 0x58 3. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_35,Status write 1 to set for level_vpac_out_2_en_utc1_complete_35" "0,1" newline bitfld.long 0x58 2. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_34,Status write 1 to set for level_vpac_out_2_en_utc1_complete_34" "0,1" newline bitfld.long 0x58 1. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_33,Status write 1 to set for level_vpac_out_2_en_utc1_complete_33" "0,1" newline bitfld.long 0x58 0. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_32,Status write 1 to set for level_vpac_out_2_en_utc1_complete_32" "0,1" line.long 0x5C "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_2_7,Status Register 23" bitfld.long 0x5C 4. "STATUS_LEVEL_VPAC_OUT_2_CTM_PULSE,Status write 1 to set for level_vpac_out_2_en_ctm_pulse" "0,1" newline bitfld.long 0x5C 3. "STATUS_LEVEL_VPAC_OUT_2_UTC1_PROT_ERR,Status write 1 to set for level_vpac_out_2_en_utc1_prot_err" "0,1" newline bitfld.long 0x5C 2. "STATUS_LEVEL_VPAC_OUT_2_UTC0_PROT_ERR,Status write 1 to set for level_vpac_out_2_en_utc0_prot_err" "0,1" newline bitfld.long 0x5C 1. "STATUS_LEVEL_VPAC_OUT_2_UTC1_ERROR,Status write 1 to set for level_vpac_out_2_en_utc1_error" "0,1" newline bitfld.long 0x5C 0. "STATUS_LEVEL_VPAC_OUT_2_UTC0_ERROR,Status write 1 to set for level_vpac_out_2_en_utc0_error" "0,1" line.long 0x60 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_3_0,Status Register 24" bitfld.long 0x60 26. "STATUS_LEVEL_VPAC_OUT_3_VISS0_CR_CFG_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x60 25. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for level_vpac_out_3_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x60 24. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for level_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x60 23. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x60 22. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x60 21. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x60 20. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for level_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x60 19. "STATUS_LEVEL_VPAC_OUT_3_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x60 18. "STATUS_LEVEL_VPAC_OUT_3_VISS0_EE_CFG_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x60 17. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x60 16. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x60 15. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCC_CFG_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x60 14. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCFA_CFG_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x60 13. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_VP_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x60 12. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x60 11. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x60 10. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_FILT_DONE,Status write 1 to set for level_vpac_out_3_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x60 9. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_FILT_START,Status write 1 to set for level_vpac_out_3_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x60 8. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_CFG_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x60 7. "STATUS_LEVEL_VPAC_OUT_3_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x60 6. "STATUS_LEVEL_VPAC_OUT_3_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x60 5. "STATUS_LEVEL_VPAC_OUT_3_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x60 4. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for level_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x60 3. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for level_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x60 2. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_AF_PULSE,Status write 1 to set for level_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x60 1. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for level_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x60 0. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_CFG_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1" line.long 0x64 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_3_1,Status Register 25" bitfld.long 0x64 8. "STATUS_LEVEL_VPAC_OUT_3_LDC0_VBUSM_RD_ERR,Status write 1 to set for level_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x64 7. "STATUS_LEVEL_VPAC_OUT_3_LDC0_SL2_WR_ERR,Status write 1 to set for level_vpac_out_3_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x64 6. "STATUS_LEVEL_VPAC_OUT_3_LDC0_FR_DONE_EVT,Status write 1 to set for level_vpac_out_3_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x64 5. "STATUS_LEVEL_VPAC_OUT_3_LDC0_INT_SZOVF,Status write 1 to set for level_vpac_out_3_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x64 4. "STATUS_LEVEL_VPAC_OUT_3_LDC0_IFR_OUTOFBOUND,Status write 1 to set for level_vpac_out_3_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x64 3. "STATUS_LEVEL_VPAC_OUT_3_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x64 2. "STATUS_LEVEL_VPAC_OUT_3_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x64 1. "STATUS_LEVEL_VPAC_OUT_3_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x64 0. "STATUS_LEVEL_VPAC_OUT_3_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x68 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_3_2,Status Register 26" bitfld.long 0x68 10. "STATUS_LEVEL_VPAC_OUT_3_NF_SL2_RD_ERR,Status write 1 to set for level_vpac_out_3_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x68 9. "STATUS_LEVEL_VPAC_OUT_3_NF_SL2_WR_ERR,Status write 1 to set for level_vpac_out_3_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x68 8. "STATUS_LEVEL_VPAC_OUT_3_NF_FRAME_DONE,Status write 1 to set for level_vpac_out_3_en_nf_frame_done" "0,1" newline bitfld.long 0x68 3. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x68 2. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x68 1. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for level_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x68 0. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for level_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x6C "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_3_3,Status Register 27" bitfld.long 0x6C 26. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_6,Status write 1 to set for level_vpac_out_3_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x6C 25. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_5,Status write 1 to set for level_vpac_out_3_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x6C 24. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_4,Status write 1 to set for level_vpac_out_3_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x6C 22. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_2,Status write 1 to set for level_vpac_out_3_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x6C 20. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_vpac_out_3_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0x6C 19. "STATUS_LEVEL_VPAC_OUT_3_SPARE_PEND_1_LEVEL,Status for level_vpac_out_3_en_spare_pend_1_level" "0,1" newline rbitfld.long 0x6C 18. "STATUS_LEVEL_VPAC_OUT_3_SPARE_PEND_1_PULSE,Status for level_vpac_out_3_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0x6C 17. "STATUS_LEVEL_VPAC_OUT_3_SPARE_PEND_0_LEVEL,Status for level_vpac_out_3_en_spare_pend_0_level" "0,1" newline rbitfld.long 0x6C 16. "STATUS_LEVEL_VPAC_OUT_3_SPARE_PEND_0_PULSE,Status for level_vpac_out_3_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x6C 15. "STATUS_LEVEL_VPAC_OUT_3_SPARE_DEC_1,Status write 1 to set for level_vpac_out_3_en_spare_dec_1" "0,1" newline bitfld.long 0x6C 14. "STATUS_LEVEL_VPAC_OUT_3_SPARE_DEC_0,Status write 1 to set for level_vpac_out_3_en_spare_dec_0" "0,1" newline bitfld.long 0x6C 13. "STATUS_LEVEL_VPAC_OUT_3_TDONE_6,Status write 1 to set for level_vpac_out_3_en_tdone_6" "0,1" newline bitfld.long 0x6C 12. "STATUS_LEVEL_VPAC_OUT_3_TDONE_5,Status write 1 to set for level_vpac_out_3_en_tdone_5" "0,1" newline bitfld.long 0x6C 11. "STATUS_LEVEL_VPAC_OUT_3_TDONE_4,Status write 1 to set for level_vpac_out_3_en_tdone_4" "0,1" newline bitfld.long 0x6C 9. "STATUS_LEVEL_VPAC_OUT_3_TDONE_2,Status write 1 to set for level_vpac_out_3_en_tdone_2" "0,1" newline bitfld.long 0x6C 7. "STATUS_LEVEL_VPAC_OUT_3_TDONE_0,Status write 1 to set for level_vpac_out_3_en_tdone_0" "0,1" newline bitfld.long 0x6C 6. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_6,Status write 1 to set for level_vpac_out_3_en_pipe_done_6" "0,1" newline bitfld.long 0x6C 5. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_5,Status write 1 to set for level_vpac_out_3_en_pipe_done_5" "0,1" newline bitfld.long 0x6C 4. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_4,Status write 1 to set for level_vpac_out_3_en_pipe_done_4" "0,1" newline bitfld.long 0x6C 3. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_3,Status write 1 to set for level_vpac_out_3_en_pipe_done_3" "0,1" newline bitfld.long 0x6C 2. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_2,Status write 1 to set for level_vpac_out_3_en_pipe_done_2" "0,1" newline bitfld.long 0x6C 1. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_1,Status write 1 to set for level_vpac_out_3_en_pipe_done_1" "0,1" newline bitfld.long 0x6C 0. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_0,Status write 1 to set for level_vpac_out_3_en_pipe_done_0" "0,1" line.long 0x70 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_3_4,Status Register 28" bitfld.long 0x70 31. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_31,Status write 1 to set for level_vpac_out_3_en_utc0_complete_31" "0,1" newline bitfld.long 0x70 30. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_30,Status write 1 to set for level_vpac_out_3_en_utc0_complete_30" "0,1" newline bitfld.long 0x70 29. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_29,Status write 1 to set for level_vpac_out_3_en_utc0_complete_29" "0,1" newline bitfld.long 0x70 28. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_28,Status write 1 to set for level_vpac_out_3_en_utc0_complete_28" "0,1" newline bitfld.long 0x70 27. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_27,Status write 1 to set for level_vpac_out_3_en_utc0_complete_27" "0,1" newline bitfld.long 0x70 26. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_26,Status write 1 to set for level_vpac_out_3_en_utc0_complete_26" "0,1" newline bitfld.long 0x70 25. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_25,Status write 1 to set for level_vpac_out_3_en_utc0_complete_25" "0,1" newline bitfld.long 0x70 24. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_24,Status write 1 to set for level_vpac_out_3_en_utc0_complete_24" "0,1" newline bitfld.long 0x70 23. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_23,Status write 1 to set for level_vpac_out_3_en_utc0_complete_23" "0,1" newline bitfld.long 0x70 22. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_22,Status write 1 to set for level_vpac_out_3_en_utc0_complete_22" "0,1" newline bitfld.long 0x70 21. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_21,Status write 1 to set for level_vpac_out_3_en_utc0_complete_21" "0,1" newline bitfld.long 0x70 20. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_20,Status write 1 to set for level_vpac_out_3_en_utc0_complete_20" "0,1" newline bitfld.long 0x70 19. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_19,Status write 1 to set for level_vpac_out_3_en_utc0_complete_19" "0,1" newline bitfld.long 0x70 18. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_18,Status write 1 to set for level_vpac_out_3_en_utc0_complete_18" "0,1" newline bitfld.long 0x70 17. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_17,Status write 1 to set for level_vpac_out_3_en_utc0_complete_17" "0,1" newline bitfld.long 0x70 16. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_16,Status write 1 to set for level_vpac_out_3_en_utc0_complete_16" "0,1" newline bitfld.long 0x70 15. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_15,Status write 1 to set for level_vpac_out_3_en_utc0_complete_15" "0,1" newline bitfld.long 0x70 14. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_14,Status write 1 to set for level_vpac_out_3_en_utc0_complete_14" "0,1" newline bitfld.long 0x70 13. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_13,Status write 1 to set for level_vpac_out_3_en_utc0_complete_13" "0,1" newline bitfld.long 0x70 12. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_12,Status write 1 to set for level_vpac_out_3_en_utc0_complete_12" "0,1" newline bitfld.long 0x70 11. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_11,Status write 1 to set for level_vpac_out_3_en_utc0_complete_11" "0,1" newline bitfld.long 0x70 10. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_10,Status write 1 to set for level_vpac_out_3_en_utc0_complete_10" "0,1" newline bitfld.long 0x70 9. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_9,Status write 1 to set for level_vpac_out_3_en_utc0_complete_9" "0,1" newline bitfld.long 0x70 8. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_8,Status write 1 to set for level_vpac_out_3_en_utc0_complete_8" "0,1" newline bitfld.long 0x70 7. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_7,Status write 1 to set for level_vpac_out_3_en_utc0_complete_7" "0,1" newline bitfld.long 0x70 6. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_6,Status write 1 to set for level_vpac_out_3_en_utc0_complete_6" "0,1" newline bitfld.long 0x70 5. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_5,Status write 1 to set for level_vpac_out_3_en_utc0_complete_5" "0,1" newline bitfld.long 0x70 4. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_4,Status write 1 to set for level_vpac_out_3_en_utc0_complete_4" "0,1" newline bitfld.long 0x70 3. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_3,Status write 1 to set for level_vpac_out_3_en_utc0_complete_3" "0,1" newline bitfld.long 0x70 2. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_2,Status write 1 to set for level_vpac_out_3_en_utc0_complete_2" "0,1" newline bitfld.long 0x70 1. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_1,Status write 1 to set for level_vpac_out_3_en_utc0_complete_1" "0,1" newline bitfld.long 0x70 0. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_0,Status write 1 to set for level_vpac_out_3_en_utc0_complete_0" "0,1" line.long 0x74 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_3_5,Status Register 29" bitfld.long 0x74 31. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_31,Status write 1 to set for level_vpac_out_3_en_utc1_complete_31" "0,1" newline bitfld.long 0x74 30. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_30,Status write 1 to set for level_vpac_out_3_en_utc1_complete_30" "0,1" newline bitfld.long 0x74 29. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_29,Status write 1 to set for level_vpac_out_3_en_utc1_complete_29" "0,1" newline bitfld.long 0x74 28. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_28,Status write 1 to set for level_vpac_out_3_en_utc1_complete_28" "0,1" newline bitfld.long 0x74 27. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_27,Status write 1 to set for level_vpac_out_3_en_utc1_complete_27" "0,1" newline bitfld.long 0x74 26. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_26,Status write 1 to set for level_vpac_out_3_en_utc1_complete_26" "0,1" newline bitfld.long 0x74 25. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_25,Status write 1 to set for level_vpac_out_3_en_utc1_complete_25" "0,1" newline bitfld.long 0x74 24. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_24,Status write 1 to set for level_vpac_out_3_en_utc1_complete_24" "0,1" newline bitfld.long 0x74 23. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_23,Status write 1 to set for level_vpac_out_3_en_utc1_complete_23" "0,1" newline bitfld.long 0x74 22. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_22,Status write 1 to set for level_vpac_out_3_en_utc1_complete_22" "0,1" newline bitfld.long 0x74 21. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_21,Status write 1 to set for level_vpac_out_3_en_utc1_complete_21" "0,1" newline bitfld.long 0x74 20. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_20,Status write 1 to set for level_vpac_out_3_en_utc1_complete_20" "0,1" newline bitfld.long 0x74 19. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_19,Status write 1 to set for level_vpac_out_3_en_utc1_complete_19" "0,1" newline bitfld.long 0x74 18. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_18,Status write 1 to set for level_vpac_out_3_en_utc1_complete_18" "0,1" newline bitfld.long 0x74 17. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_17,Status write 1 to set for level_vpac_out_3_en_utc1_complete_17" "0,1" newline bitfld.long 0x74 16. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_16,Status write 1 to set for level_vpac_out_3_en_utc1_complete_16" "0,1" newline bitfld.long 0x74 15. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_15,Status write 1 to set for level_vpac_out_3_en_utc1_complete_15" "0,1" newline bitfld.long 0x74 14. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_14,Status write 1 to set for level_vpac_out_3_en_utc1_complete_14" "0,1" newline bitfld.long 0x74 13. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_13,Status write 1 to set for level_vpac_out_3_en_utc1_complete_13" "0,1" newline bitfld.long 0x74 12. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_12,Status write 1 to set for level_vpac_out_3_en_utc1_complete_12" "0,1" newline bitfld.long 0x74 11. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_11,Status write 1 to set for level_vpac_out_3_en_utc1_complete_11" "0,1" newline bitfld.long 0x74 10. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_10,Status write 1 to set for level_vpac_out_3_en_utc1_complete_10" "0,1" newline bitfld.long 0x74 9. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_9,Status write 1 to set for level_vpac_out_3_en_utc1_complete_9" "0,1" newline bitfld.long 0x74 8. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_8,Status write 1 to set for level_vpac_out_3_en_utc1_complete_8" "0,1" newline bitfld.long 0x74 7. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_7,Status write 1 to set for level_vpac_out_3_en_utc1_complete_7" "0,1" newline bitfld.long 0x74 6. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_6,Status write 1 to set for level_vpac_out_3_en_utc1_complete_6" "0,1" newline bitfld.long 0x74 5. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_5,Status write 1 to set for level_vpac_out_3_en_utc1_complete_5" "0,1" newline bitfld.long 0x74 4. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_4,Status write 1 to set for level_vpac_out_3_en_utc1_complete_4" "0,1" newline bitfld.long 0x74 3. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_3,Status write 1 to set for level_vpac_out_3_en_utc1_complete_3" "0,1" newline bitfld.long 0x74 2. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_2,Status write 1 to set for level_vpac_out_3_en_utc1_complete_2" "0,1" newline bitfld.long 0x74 1. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_1,Status write 1 to set for level_vpac_out_3_en_utc1_complete_1" "0,1" newline bitfld.long 0x74 0. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_0,Status write 1 to set for level_vpac_out_3_en_utc1_complete_0" "0,1" line.long 0x78 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_3_6,Status Register 30" bitfld.long 0x78 31. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_63,Status write 1 to set for level_vpac_out_3_en_utc1_complete_63" "0,1" newline bitfld.long 0x78 30. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_62,Status write 1 to set for level_vpac_out_3_en_utc1_complete_62" "0,1" newline bitfld.long 0x78 29. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_61,Status write 1 to set for level_vpac_out_3_en_utc1_complete_61" "0,1" newline bitfld.long 0x78 28. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_60,Status write 1 to set for level_vpac_out_3_en_utc1_complete_60" "0,1" newline bitfld.long 0x78 27. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_59,Status write 1 to set for level_vpac_out_3_en_utc1_complete_59" "0,1" newline bitfld.long 0x78 26. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_58,Status write 1 to set for level_vpac_out_3_en_utc1_complete_58" "0,1" newline bitfld.long 0x78 25. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_57,Status write 1 to set for level_vpac_out_3_en_utc1_complete_57" "0,1" newline bitfld.long 0x78 24. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_56,Status write 1 to set for level_vpac_out_3_en_utc1_complete_56" "0,1" newline bitfld.long 0x78 23. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_55,Status write 1 to set for level_vpac_out_3_en_utc1_complete_55" "0,1" newline bitfld.long 0x78 22. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_54,Status write 1 to set for level_vpac_out_3_en_utc1_complete_54" "0,1" newline bitfld.long 0x78 21. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_53,Status write 1 to set for level_vpac_out_3_en_utc1_complete_53" "0,1" newline bitfld.long 0x78 20. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_52,Status write 1 to set for level_vpac_out_3_en_utc1_complete_52" "0,1" newline bitfld.long 0x78 19. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_51,Status write 1 to set for level_vpac_out_3_en_utc1_complete_51" "0,1" newline bitfld.long 0x78 18. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_50,Status write 1 to set for level_vpac_out_3_en_utc1_complete_50" "0,1" newline bitfld.long 0x78 17. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_49,Status write 1 to set for level_vpac_out_3_en_utc1_complete_49" "0,1" newline bitfld.long 0x78 16. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_48,Status write 1 to set for level_vpac_out_3_en_utc1_complete_48" "0,1" newline bitfld.long 0x78 15. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_47,Status write 1 to set for level_vpac_out_3_en_utc1_complete_47" "0,1" newline bitfld.long 0x78 14. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_46,Status write 1 to set for level_vpac_out_3_en_utc1_complete_46" "0,1" newline bitfld.long 0x78 13. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_45,Status write 1 to set for level_vpac_out_3_en_utc1_complete_45" "0,1" newline bitfld.long 0x78 12. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_44,Status write 1 to set for level_vpac_out_3_en_utc1_complete_44" "0,1" newline bitfld.long 0x78 11. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_43,Status write 1 to set for level_vpac_out_3_en_utc1_complete_43" "0,1" newline bitfld.long 0x78 10. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_42,Status write 1 to set for level_vpac_out_3_en_utc1_complete_42" "0,1" newline bitfld.long 0x78 9. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_41,Status write 1 to set for level_vpac_out_3_en_utc1_complete_41" "0,1" newline bitfld.long 0x78 8. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_40,Status write 1 to set for level_vpac_out_3_en_utc1_complete_40" "0,1" newline bitfld.long 0x78 7. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_39,Status write 1 to set for level_vpac_out_3_en_utc1_complete_39" "0,1" newline bitfld.long 0x78 6. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_38,Status write 1 to set for level_vpac_out_3_en_utc1_complete_38" "0,1" newline bitfld.long 0x78 5. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_37,Status write 1 to set for level_vpac_out_3_en_utc1_complete_37" "0,1" newline bitfld.long 0x78 4. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_36,Status write 1 to set for level_vpac_out_3_en_utc1_complete_36" "0,1" newline bitfld.long 0x78 3. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_35,Status write 1 to set for level_vpac_out_3_en_utc1_complete_35" "0,1" newline bitfld.long 0x78 2. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_34,Status write 1 to set for level_vpac_out_3_en_utc1_complete_34" "0,1" newline bitfld.long 0x78 1. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_33,Status write 1 to set for level_vpac_out_3_en_utc1_complete_33" "0,1" newline bitfld.long 0x78 0. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_32,Status write 1 to set for level_vpac_out_3_en_utc1_complete_32" "0,1" line.long 0x7C "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_3_7,Status Register 31" bitfld.long 0x7C 4. "STATUS_LEVEL_VPAC_OUT_3_CTM_PULSE,Status write 1 to set for level_vpac_out_3_en_ctm_pulse" "0,1" newline bitfld.long 0x7C 3. "STATUS_LEVEL_VPAC_OUT_3_UTC1_PROT_ERR,Status write 1 to set for level_vpac_out_3_en_utc1_prot_err" "0,1" newline bitfld.long 0x7C 2. "STATUS_LEVEL_VPAC_OUT_3_UTC0_PROT_ERR,Status write 1 to set for level_vpac_out_3_en_utc0_prot_err" "0,1" newline bitfld.long 0x7C 1. "STATUS_LEVEL_VPAC_OUT_3_UTC1_ERROR,Status write 1 to set for level_vpac_out_3_en_utc1_error" "0,1" newline bitfld.long 0x7C 0. "STATUS_LEVEL_VPAC_OUT_3_UTC0_ERROR,Status write 1 to set for level_vpac_out_3_en_utc0_error" "0,1" line.long 0x80 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_4_0,Status Register 32" bitfld.long 0x80 26. "STATUS_LEVEL_VPAC_OUT_4_VISS0_CR_CFG_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x80 25. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for level_vpac_out_4_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x80 24. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for level_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x80 23. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x80 22. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x80 21. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x80 20. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for level_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x80 19. "STATUS_LEVEL_VPAC_OUT_4_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x80 18. "STATUS_LEVEL_VPAC_OUT_4_VISS0_EE_CFG_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x80 17. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x80 16. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x80 15. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCC_CFG_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x80 14. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCFA_CFG_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x80 13. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_VP_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x80 12. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x80 11. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x80 10. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_FILT_DONE,Status write 1 to set for level_vpac_out_4_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x80 9. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_FILT_START,Status write 1 to set for level_vpac_out_4_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x80 8. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_CFG_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x80 7. "STATUS_LEVEL_VPAC_OUT_4_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x80 6. "STATUS_LEVEL_VPAC_OUT_4_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x80 5. "STATUS_LEVEL_VPAC_OUT_4_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x80 4. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for level_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x80 3. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for level_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x80 2. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_AF_PULSE,Status write 1 to set for level_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x80 1. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for level_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x80 0. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_CFG_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1" line.long 0x84 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_4_1,Status Register 33" bitfld.long 0x84 8. "STATUS_LEVEL_VPAC_OUT_4_LDC0_VBUSM_RD_ERR,Status write 1 to set for level_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x84 7. "STATUS_LEVEL_VPAC_OUT_4_LDC0_SL2_WR_ERR,Status write 1 to set for level_vpac_out_4_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x84 6. "STATUS_LEVEL_VPAC_OUT_4_LDC0_FR_DONE_EVT,Status write 1 to set for level_vpac_out_4_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x84 5. "STATUS_LEVEL_VPAC_OUT_4_LDC0_INT_SZOVF,Status write 1 to set for level_vpac_out_4_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x84 4. "STATUS_LEVEL_VPAC_OUT_4_LDC0_IFR_OUTOFBOUND,Status write 1 to set for level_vpac_out_4_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x84 3. "STATUS_LEVEL_VPAC_OUT_4_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x84 2. "STATUS_LEVEL_VPAC_OUT_4_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x84 1. "STATUS_LEVEL_VPAC_OUT_4_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x84 0. "STATUS_LEVEL_VPAC_OUT_4_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x88 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_4_2,Status Register 34" bitfld.long 0x88 10. "STATUS_LEVEL_VPAC_OUT_4_NF_SL2_RD_ERR,Status write 1 to set for level_vpac_out_4_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x88 9. "STATUS_LEVEL_VPAC_OUT_4_NF_SL2_WR_ERR,Status write 1 to set for level_vpac_out_4_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x88 8. "STATUS_LEVEL_VPAC_OUT_4_NF_FRAME_DONE,Status write 1 to set for level_vpac_out_4_en_nf_frame_done" "0,1" newline bitfld.long 0x88 3. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x88 2. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x88 1. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for level_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x88 0. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for level_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x8C "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_4_3,Status Register 35" bitfld.long 0x8C 26. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_6,Status write 1 to set for level_vpac_out_4_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x8C 25. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_5,Status write 1 to set for level_vpac_out_4_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x8C 24. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_4,Status write 1 to set for level_vpac_out_4_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x8C 22. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_2,Status write 1 to set for level_vpac_out_4_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x8C 20. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_vpac_out_4_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0x8C 19. "STATUS_LEVEL_VPAC_OUT_4_SPARE_PEND_1_LEVEL,Status for level_vpac_out_4_en_spare_pend_1_level" "0,1" newline rbitfld.long 0x8C 18. "STATUS_LEVEL_VPAC_OUT_4_SPARE_PEND_1_PULSE,Status for level_vpac_out_4_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0x8C 17. "STATUS_LEVEL_VPAC_OUT_4_SPARE_PEND_0_LEVEL,Status for level_vpac_out_4_en_spare_pend_0_level" "0,1" newline rbitfld.long 0x8C 16. "STATUS_LEVEL_VPAC_OUT_4_SPARE_PEND_0_PULSE,Status for level_vpac_out_4_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x8C 15. "STATUS_LEVEL_VPAC_OUT_4_SPARE_DEC_1,Status write 1 to set for level_vpac_out_4_en_spare_dec_1" "0,1" newline bitfld.long 0x8C 14. "STATUS_LEVEL_VPAC_OUT_4_SPARE_DEC_0,Status write 1 to set for level_vpac_out_4_en_spare_dec_0" "0,1" newline bitfld.long 0x8C 13. "STATUS_LEVEL_VPAC_OUT_4_TDONE_6,Status write 1 to set for level_vpac_out_4_en_tdone_6" "0,1" newline bitfld.long 0x8C 12. "STATUS_LEVEL_VPAC_OUT_4_TDONE_5,Status write 1 to set for level_vpac_out_4_en_tdone_5" "0,1" newline bitfld.long 0x8C 11. "STATUS_LEVEL_VPAC_OUT_4_TDONE_4,Status write 1 to set for level_vpac_out_4_en_tdone_4" "0,1" newline bitfld.long 0x8C 9. "STATUS_LEVEL_VPAC_OUT_4_TDONE_2,Status write 1 to set for level_vpac_out_4_en_tdone_2" "0,1" newline bitfld.long 0x8C 7. "STATUS_LEVEL_VPAC_OUT_4_TDONE_0,Status write 1 to set for level_vpac_out_4_en_tdone_0" "0,1" newline bitfld.long 0x8C 6. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_6,Status write 1 to set for level_vpac_out_4_en_pipe_done_6" "0,1" newline bitfld.long 0x8C 5. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_5,Status write 1 to set for level_vpac_out_4_en_pipe_done_5" "0,1" newline bitfld.long 0x8C 4. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_4,Status write 1 to set for level_vpac_out_4_en_pipe_done_4" "0,1" newline bitfld.long 0x8C 3. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_3,Status write 1 to set for level_vpac_out_4_en_pipe_done_3" "0,1" newline bitfld.long 0x8C 2. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_2,Status write 1 to set for level_vpac_out_4_en_pipe_done_2" "0,1" newline bitfld.long 0x8C 1. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_1,Status write 1 to set for level_vpac_out_4_en_pipe_done_1" "0,1" newline bitfld.long 0x8C 0. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_0,Status write 1 to set for level_vpac_out_4_en_pipe_done_0" "0,1" line.long 0x90 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_4_4,Status Register 36" bitfld.long 0x90 31. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_31,Status write 1 to set for level_vpac_out_4_en_utc0_complete_31" "0,1" newline bitfld.long 0x90 30. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_30,Status write 1 to set for level_vpac_out_4_en_utc0_complete_30" "0,1" newline bitfld.long 0x90 29. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_29,Status write 1 to set for level_vpac_out_4_en_utc0_complete_29" "0,1" newline bitfld.long 0x90 28. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_28,Status write 1 to set for level_vpac_out_4_en_utc0_complete_28" "0,1" newline bitfld.long 0x90 27. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_27,Status write 1 to set for level_vpac_out_4_en_utc0_complete_27" "0,1" newline bitfld.long 0x90 26. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_26,Status write 1 to set for level_vpac_out_4_en_utc0_complete_26" "0,1" newline bitfld.long 0x90 25. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_25,Status write 1 to set for level_vpac_out_4_en_utc0_complete_25" "0,1" newline bitfld.long 0x90 24. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_24,Status write 1 to set for level_vpac_out_4_en_utc0_complete_24" "0,1" newline bitfld.long 0x90 23. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_23,Status write 1 to set for level_vpac_out_4_en_utc0_complete_23" "0,1" newline bitfld.long 0x90 22. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_22,Status write 1 to set for level_vpac_out_4_en_utc0_complete_22" "0,1" newline bitfld.long 0x90 21. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_21,Status write 1 to set for level_vpac_out_4_en_utc0_complete_21" "0,1" newline bitfld.long 0x90 20. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_20,Status write 1 to set for level_vpac_out_4_en_utc0_complete_20" "0,1" newline bitfld.long 0x90 19. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_19,Status write 1 to set for level_vpac_out_4_en_utc0_complete_19" "0,1" newline bitfld.long 0x90 18. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_18,Status write 1 to set for level_vpac_out_4_en_utc0_complete_18" "0,1" newline bitfld.long 0x90 17. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_17,Status write 1 to set for level_vpac_out_4_en_utc0_complete_17" "0,1" newline bitfld.long 0x90 16. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_16,Status write 1 to set for level_vpac_out_4_en_utc0_complete_16" "0,1" newline bitfld.long 0x90 15. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_15,Status write 1 to set for level_vpac_out_4_en_utc0_complete_15" "0,1" newline bitfld.long 0x90 14. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_14,Status write 1 to set for level_vpac_out_4_en_utc0_complete_14" "0,1" newline bitfld.long 0x90 13. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_13,Status write 1 to set for level_vpac_out_4_en_utc0_complete_13" "0,1" newline bitfld.long 0x90 12. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_12,Status write 1 to set for level_vpac_out_4_en_utc0_complete_12" "0,1" newline bitfld.long 0x90 11. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_11,Status write 1 to set for level_vpac_out_4_en_utc0_complete_11" "0,1" newline bitfld.long 0x90 10. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_10,Status write 1 to set for level_vpac_out_4_en_utc0_complete_10" "0,1" newline bitfld.long 0x90 9. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_9,Status write 1 to set for level_vpac_out_4_en_utc0_complete_9" "0,1" newline bitfld.long 0x90 8. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_8,Status write 1 to set for level_vpac_out_4_en_utc0_complete_8" "0,1" newline bitfld.long 0x90 7. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_7,Status write 1 to set for level_vpac_out_4_en_utc0_complete_7" "0,1" newline bitfld.long 0x90 6. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_6,Status write 1 to set for level_vpac_out_4_en_utc0_complete_6" "0,1" newline bitfld.long 0x90 5. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_5,Status write 1 to set for level_vpac_out_4_en_utc0_complete_5" "0,1" newline bitfld.long 0x90 4. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_4,Status write 1 to set for level_vpac_out_4_en_utc0_complete_4" "0,1" newline bitfld.long 0x90 3. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_3,Status write 1 to set for level_vpac_out_4_en_utc0_complete_3" "0,1" newline bitfld.long 0x90 2. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_2,Status write 1 to set for level_vpac_out_4_en_utc0_complete_2" "0,1" newline bitfld.long 0x90 1. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_1,Status write 1 to set for level_vpac_out_4_en_utc0_complete_1" "0,1" newline bitfld.long 0x90 0. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_0,Status write 1 to set for level_vpac_out_4_en_utc0_complete_0" "0,1" line.long 0x94 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_4_5,Status Register 37" bitfld.long 0x94 31. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_31,Status write 1 to set for level_vpac_out_4_en_utc1_complete_31" "0,1" newline bitfld.long 0x94 30. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_30,Status write 1 to set for level_vpac_out_4_en_utc1_complete_30" "0,1" newline bitfld.long 0x94 29. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_29,Status write 1 to set for level_vpac_out_4_en_utc1_complete_29" "0,1" newline bitfld.long 0x94 28. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_28,Status write 1 to set for level_vpac_out_4_en_utc1_complete_28" "0,1" newline bitfld.long 0x94 27. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_27,Status write 1 to set for level_vpac_out_4_en_utc1_complete_27" "0,1" newline bitfld.long 0x94 26. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_26,Status write 1 to set for level_vpac_out_4_en_utc1_complete_26" "0,1" newline bitfld.long 0x94 25. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_25,Status write 1 to set for level_vpac_out_4_en_utc1_complete_25" "0,1" newline bitfld.long 0x94 24. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_24,Status write 1 to set for level_vpac_out_4_en_utc1_complete_24" "0,1" newline bitfld.long 0x94 23. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_23,Status write 1 to set for level_vpac_out_4_en_utc1_complete_23" "0,1" newline bitfld.long 0x94 22. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_22,Status write 1 to set for level_vpac_out_4_en_utc1_complete_22" "0,1" newline bitfld.long 0x94 21. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_21,Status write 1 to set for level_vpac_out_4_en_utc1_complete_21" "0,1" newline bitfld.long 0x94 20. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_20,Status write 1 to set for level_vpac_out_4_en_utc1_complete_20" "0,1" newline bitfld.long 0x94 19. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_19,Status write 1 to set for level_vpac_out_4_en_utc1_complete_19" "0,1" newline bitfld.long 0x94 18. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_18,Status write 1 to set for level_vpac_out_4_en_utc1_complete_18" "0,1" newline bitfld.long 0x94 17. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_17,Status write 1 to set for level_vpac_out_4_en_utc1_complete_17" "0,1" newline bitfld.long 0x94 16. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_16,Status write 1 to set for level_vpac_out_4_en_utc1_complete_16" "0,1" newline bitfld.long 0x94 15. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_15,Status write 1 to set for level_vpac_out_4_en_utc1_complete_15" "0,1" newline bitfld.long 0x94 14. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_14,Status write 1 to set for level_vpac_out_4_en_utc1_complete_14" "0,1" newline bitfld.long 0x94 13. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_13,Status write 1 to set for level_vpac_out_4_en_utc1_complete_13" "0,1" newline bitfld.long 0x94 12. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_12,Status write 1 to set for level_vpac_out_4_en_utc1_complete_12" "0,1" newline bitfld.long 0x94 11. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_11,Status write 1 to set for level_vpac_out_4_en_utc1_complete_11" "0,1" newline bitfld.long 0x94 10. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_10,Status write 1 to set for level_vpac_out_4_en_utc1_complete_10" "0,1" newline bitfld.long 0x94 9. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_9,Status write 1 to set for level_vpac_out_4_en_utc1_complete_9" "0,1" newline bitfld.long 0x94 8. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_8,Status write 1 to set for level_vpac_out_4_en_utc1_complete_8" "0,1" newline bitfld.long 0x94 7. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_7,Status write 1 to set for level_vpac_out_4_en_utc1_complete_7" "0,1" newline bitfld.long 0x94 6. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_6,Status write 1 to set for level_vpac_out_4_en_utc1_complete_6" "0,1" newline bitfld.long 0x94 5. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_5,Status write 1 to set for level_vpac_out_4_en_utc1_complete_5" "0,1" newline bitfld.long 0x94 4. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_4,Status write 1 to set for level_vpac_out_4_en_utc1_complete_4" "0,1" newline bitfld.long 0x94 3. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_3,Status write 1 to set for level_vpac_out_4_en_utc1_complete_3" "0,1" newline bitfld.long 0x94 2. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_2,Status write 1 to set for level_vpac_out_4_en_utc1_complete_2" "0,1" newline bitfld.long 0x94 1. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_1,Status write 1 to set for level_vpac_out_4_en_utc1_complete_1" "0,1" newline bitfld.long 0x94 0. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_0,Status write 1 to set for level_vpac_out_4_en_utc1_complete_0" "0,1" line.long 0x98 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_4_6,Status Register 38" bitfld.long 0x98 31. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_63,Status write 1 to set for level_vpac_out_4_en_utc1_complete_63" "0,1" newline bitfld.long 0x98 30. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_62,Status write 1 to set for level_vpac_out_4_en_utc1_complete_62" "0,1" newline bitfld.long 0x98 29. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_61,Status write 1 to set for level_vpac_out_4_en_utc1_complete_61" "0,1" newline bitfld.long 0x98 28. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_60,Status write 1 to set for level_vpac_out_4_en_utc1_complete_60" "0,1" newline bitfld.long 0x98 27. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_59,Status write 1 to set for level_vpac_out_4_en_utc1_complete_59" "0,1" newline bitfld.long 0x98 26. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_58,Status write 1 to set for level_vpac_out_4_en_utc1_complete_58" "0,1" newline bitfld.long 0x98 25. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_57,Status write 1 to set for level_vpac_out_4_en_utc1_complete_57" "0,1" newline bitfld.long 0x98 24. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_56,Status write 1 to set for level_vpac_out_4_en_utc1_complete_56" "0,1" newline bitfld.long 0x98 23. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_55,Status write 1 to set for level_vpac_out_4_en_utc1_complete_55" "0,1" newline bitfld.long 0x98 22. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_54,Status write 1 to set for level_vpac_out_4_en_utc1_complete_54" "0,1" newline bitfld.long 0x98 21. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_53,Status write 1 to set for level_vpac_out_4_en_utc1_complete_53" "0,1" newline bitfld.long 0x98 20. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_52,Status write 1 to set for level_vpac_out_4_en_utc1_complete_52" "0,1" newline bitfld.long 0x98 19. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_51,Status write 1 to set for level_vpac_out_4_en_utc1_complete_51" "0,1" newline bitfld.long 0x98 18. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_50,Status write 1 to set for level_vpac_out_4_en_utc1_complete_50" "0,1" newline bitfld.long 0x98 17. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_49,Status write 1 to set for level_vpac_out_4_en_utc1_complete_49" "0,1" newline bitfld.long 0x98 16. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_48,Status write 1 to set for level_vpac_out_4_en_utc1_complete_48" "0,1" newline bitfld.long 0x98 15. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_47,Status write 1 to set for level_vpac_out_4_en_utc1_complete_47" "0,1" newline bitfld.long 0x98 14. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_46,Status write 1 to set for level_vpac_out_4_en_utc1_complete_46" "0,1" newline bitfld.long 0x98 13. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_45,Status write 1 to set for level_vpac_out_4_en_utc1_complete_45" "0,1" newline bitfld.long 0x98 12. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_44,Status write 1 to set for level_vpac_out_4_en_utc1_complete_44" "0,1" newline bitfld.long 0x98 11. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_43,Status write 1 to set for level_vpac_out_4_en_utc1_complete_43" "0,1" newline bitfld.long 0x98 10. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_42,Status write 1 to set for level_vpac_out_4_en_utc1_complete_42" "0,1" newline bitfld.long 0x98 9. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_41,Status write 1 to set for level_vpac_out_4_en_utc1_complete_41" "0,1" newline bitfld.long 0x98 8. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_40,Status write 1 to set for level_vpac_out_4_en_utc1_complete_40" "0,1" newline bitfld.long 0x98 7. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_39,Status write 1 to set for level_vpac_out_4_en_utc1_complete_39" "0,1" newline bitfld.long 0x98 6. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_38,Status write 1 to set for level_vpac_out_4_en_utc1_complete_38" "0,1" newline bitfld.long 0x98 5. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_37,Status write 1 to set for level_vpac_out_4_en_utc1_complete_37" "0,1" newline bitfld.long 0x98 4. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_36,Status write 1 to set for level_vpac_out_4_en_utc1_complete_36" "0,1" newline bitfld.long 0x98 3. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_35,Status write 1 to set for level_vpac_out_4_en_utc1_complete_35" "0,1" newline bitfld.long 0x98 2. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_34,Status write 1 to set for level_vpac_out_4_en_utc1_complete_34" "0,1" newline bitfld.long 0x98 1. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_33,Status write 1 to set for level_vpac_out_4_en_utc1_complete_33" "0,1" newline bitfld.long 0x98 0. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_32,Status write 1 to set for level_vpac_out_4_en_utc1_complete_32" "0,1" line.long 0x9C "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_4_7,Status Register 39" bitfld.long 0x9C 4. "STATUS_LEVEL_VPAC_OUT_4_CTM_PULSE,Status write 1 to set for level_vpac_out_4_en_ctm_pulse" "0,1" newline bitfld.long 0x9C 3. "STATUS_LEVEL_VPAC_OUT_4_UTC1_PROT_ERR,Status write 1 to set for level_vpac_out_4_en_utc1_prot_err" "0,1" newline bitfld.long 0x9C 2. "STATUS_LEVEL_VPAC_OUT_4_UTC0_PROT_ERR,Status write 1 to set for level_vpac_out_4_en_utc0_prot_err" "0,1" newline bitfld.long 0x9C 1. "STATUS_LEVEL_VPAC_OUT_4_UTC1_ERROR,Status write 1 to set for level_vpac_out_4_en_utc1_error" "0,1" newline bitfld.long 0x9C 0. "STATUS_LEVEL_VPAC_OUT_4_UTC0_ERROR,Status write 1 to set for level_vpac_out_4_en_utc0_error" "0,1" line.long 0xA0 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_5_0,Status Register 40" bitfld.long 0xA0 26. "STATUS_LEVEL_VPAC_OUT_5_VISS0_CR_CFG_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xA0 25. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for level_vpac_out_5_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xA0 24. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for level_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xA0 23. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xA0 22. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xA0 21. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xA0 20. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for level_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xA0 19. "STATUS_LEVEL_VPAC_OUT_5_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xA0 18. "STATUS_LEVEL_VPAC_OUT_5_VISS0_EE_CFG_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xA0 17. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xA0 16. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xA0 15. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCC_CFG_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xA0 14. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCFA_CFG_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xA0 13. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_VP_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xA0 12. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xA0 11. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xA0 10. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_FILT_DONE,Status write 1 to set for level_vpac_out_5_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xA0 9. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_FILT_START,Status write 1 to set for level_vpac_out_5_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xA0 8. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_CFG_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xA0 7. "STATUS_LEVEL_VPAC_OUT_5_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xA0 6. "STATUS_LEVEL_VPAC_OUT_5_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xA0 5. "STATUS_LEVEL_VPAC_OUT_5_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xA0 4. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for level_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xA0 3. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for level_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xA0 2. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_AF_PULSE,Status write 1 to set for level_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xA0 1. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for level_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xA0 0. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_CFG_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1" line.long 0xA4 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_5_1,Status Register 41" bitfld.long 0xA4 8. "STATUS_LEVEL_VPAC_OUT_5_LDC0_VBUSM_RD_ERR,Status write 1 to set for level_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xA4 7. "STATUS_LEVEL_VPAC_OUT_5_LDC0_SL2_WR_ERR,Status write 1 to set for level_vpac_out_5_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xA4 6. "STATUS_LEVEL_VPAC_OUT_5_LDC0_FR_DONE_EVT,Status write 1 to set for level_vpac_out_5_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xA4 5. "STATUS_LEVEL_VPAC_OUT_5_LDC0_INT_SZOVF,Status write 1 to set for level_vpac_out_5_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xA4 4. "STATUS_LEVEL_VPAC_OUT_5_LDC0_IFR_OUTOFBOUND,Status write 1 to set for level_vpac_out_5_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xA4 3. "STATUS_LEVEL_VPAC_OUT_5_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xA4 2. "STATUS_LEVEL_VPAC_OUT_5_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xA4 1. "STATUS_LEVEL_VPAC_OUT_5_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xA4 0. "STATUS_LEVEL_VPAC_OUT_5_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xA8 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_5_2,Status Register 42" bitfld.long 0xA8 10. "STATUS_LEVEL_VPAC_OUT_5_NF_SL2_RD_ERR,Status write 1 to set for level_vpac_out_5_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0xA8 9. "STATUS_LEVEL_VPAC_OUT_5_NF_SL2_WR_ERR,Status write 1 to set for level_vpac_out_5_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0xA8 8. "STATUS_LEVEL_VPAC_OUT_5_NF_FRAME_DONE,Status write 1 to set for level_vpac_out_5_en_nf_frame_done" "0,1" newline bitfld.long 0xA8 3. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xA8 2. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xA8 1. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for level_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xA8 0. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for level_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xAC "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_5_3,Status Register 43" bitfld.long 0xAC 26. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_6,Status write 1 to set for level_vpac_out_5_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xAC 25. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_5,Status write 1 to set for level_vpac_out_5_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xAC 24. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_4,Status write 1 to set for level_vpac_out_5_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xAC 22. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_2,Status write 1 to set for level_vpac_out_5_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xAC 20. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_vpac_out_5_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0xAC 19. "STATUS_LEVEL_VPAC_OUT_5_SPARE_PEND_1_LEVEL,Status for level_vpac_out_5_en_spare_pend_1_level" "0,1" newline rbitfld.long 0xAC 18. "STATUS_LEVEL_VPAC_OUT_5_SPARE_PEND_1_PULSE,Status for level_vpac_out_5_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0xAC 17. "STATUS_LEVEL_VPAC_OUT_5_SPARE_PEND_0_LEVEL,Status for level_vpac_out_5_en_spare_pend_0_level" "0,1" newline rbitfld.long 0xAC 16. "STATUS_LEVEL_VPAC_OUT_5_SPARE_PEND_0_PULSE,Status for level_vpac_out_5_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xAC 15. "STATUS_LEVEL_VPAC_OUT_5_SPARE_DEC_1,Status write 1 to set for level_vpac_out_5_en_spare_dec_1" "0,1" newline bitfld.long 0xAC 14. "STATUS_LEVEL_VPAC_OUT_5_SPARE_DEC_0,Status write 1 to set for level_vpac_out_5_en_spare_dec_0" "0,1" newline bitfld.long 0xAC 13. "STATUS_LEVEL_VPAC_OUT_5_TDONE_6,Status write 1 to set for level_vpac_out_5_en_tdone_6" "0,1" newline bitfld.long 0xAC 12. "STATUS_LEVEL_VPAC_OUT_5_TDONE_5,Status write 1 to set for level_vpac_out_5_en_tdone_5" "0,1" newline bitfld.long 0xAC 11. "STATUS_LEVEL_VPAC_OUT_5_TDONE_4,Status write 1 to set for level_vpac_out_5_en_tdone_4" "0,1" newline bitfld.long 0xAC 9. "STATUS_LEVEL_VPAC_OUT_5_TDONE_2,Status write 1 to set for level_vpac_out_5_en_tdone_2" "0,1" newline bitfld.long 0xAC 7. "STATUS_LEVEL_VPAC_OUT_5_TDONE_0,Status write 1 to set for level_vpac_out_5_en_tdone_0" "0,1" newline bitfld.long 0xAC 6. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_6,Status write 1 to set for level_vpac_out_5_en_pipe_done_6" "0,1" newline bitfld.long 0xAC 5. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_5,Status write 1 to set for level_vpac_out_5_en_pipe_done_5" "0,1" newline bitfld.long 0xAC 4. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_4,Status write 1 to set for level_vpac_out_5_en_pipe_done_4" "0,1" newline bitfld.long 0xAC 3. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_3,Status write 1 to set for level_vpac_out_5_en_pipe_done_3" "0,1" newline bitfld.long 0xAC 2. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_2,Status write 1 to set for level_vpac_out_5_en_pipe_done_2" "0,1" newline bitfld.long 0xAC 1. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_1,Status write 1 to set for level_vpac_out_5_en_pipe_done_1" "0,1" newline bitfld.long 0xAC 0. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_0,Status write 1 to set for level_vpac_out_5_en_pipe_done_0" "0,1" line.long 0xB0 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_5_4,Status Register 44" bitfld.long 0xB0 31. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_31,Status write 1 to set for level_vpac_out_5_en_utc0_complete_31" "0,1" newline bitfld.long 0xB0 30. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_30,Status write 1 to set for level_vpac_out_5_en_utc0_complete_30" "0,1" newline bitfld.long 0xB0 29. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_29,Status write 1 to set for level_vpac_out_5_en_utc0_complete_29" "0,1" newline bitfld.long 0xB0 28. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_28,Status write 1 to set for level_vpac_out_5_en_utc0_complete_28" "0,1" newline bitfld.long 0xB0 27. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_27,Status write 1 to set for level_vpac_out_5_en_utc0_complete_27" "0,1" newline bitfld.long 0xB0 26. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_26,Status write 1 to set for level_vpac_out_5_en_utc0_complete_26" "0,1" newline bitfld.long 0xB0 25. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_25,Status write 1 to set for level_vpac_out_5_en_utc0_complete_25" "0,1" newline bitfld.long 0xB0 24. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_24,Status write 1 to set for level_vpac_out_5_en_utc0_complete_24" "0,1" newline bitfld.long 0xB0 23. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_23,Status write 1 to set for level_vpac_out_5_en_utc0_complete_23" "0,1" newline bitfld.long 0xB0 22. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_22,Status write 1 to set for level_vpac_out_5_en_utc0_complete_22" "0,1" newline bitfld.long 0xB0 21. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_21,Status write 1 to set for level_vpac_out_5_en_utc0_complete_21" "0,1" newline bitfld.long 0xB0 20. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_20,Status write 1 to set for level_vpac_out_5_en_utc0_complete_20" "0,1" newline bitfld.long 0xB0 19. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_19,Status write 1 to set for level_vpac_out_5_en_utc0_complete_19" "0,1" newline bitfld.long 0xB0 18. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_18,Status write 1 to set for level_vpac_out_5_en_utc0_complete_18" "0,1" newline bitfld.long 0xB0 17. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_17,Status write 1 to set for level_vpac_out_5_en_utc0_complete_17" "0,1" newline bitfld.long 0xB0 16. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_16,Status write 1 to set for level_vpac_out_5_en_utc0_complete_16" "0,1" newline bitfld.long 0xB0 15. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_15,Status write 1 to set for level_vpac_out_5_en_utc0_complete_15" "0,1" newline bitfld.long 0xB0 14. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_14,Status write 1 to set for level_vpac_out_5_en_utc0_complete_14" "0,1" newline bitfld.long 0xB0 13. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_13,Status write 1 to set for level_vpac_out_5_en_utc0_complete_13" "0,1" newline bitfld.long 0xB0 12. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_12,Status write 1 to set for level_vpac_out_5_en_utc0_complete_12" "0,1" newline bitfld.long 0xB0 11. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_11,Status write 1 to set for level_vpac_out_5_en_utc0_complete_11" "0,1" newline bitfld.long 0xB0 10. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_10,Status write 1 to set for level_vpac_out_5_en_utc0_complete_10" "0,1" newline bitfld.long 0xB0 9. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_9,Status write 1 to set for level_vpac_out_5_en_utc0_complete_9" "0,1" newline bitfld.long 0xB0 8. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_8,Status write 1 to set for level_vpac_out_5_en_utc0_complete_8" "0,1" newline bitfld.long 0xB0 7. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_7,Status write 1 to set for level_vpac_out_5_en_utc0_complete_7" "0,1" newline bitfld.long 0xB0 6. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_6,Status write 1 to set for level_vpac_out_5_en_utc0_complete_6" "0,1" newline bitfld.long 0xB0 5. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_5,Status write 1 to set for level_vpac_out_5_en_utc0_complete_5" "0,1" newline bitfld.long 0xB0 4. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_4,Status write 1 to set for level_vpac_out_5_en_utc0_complete_4" "0,1" newline bitfld.long 0xB0 3. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_3,Status write 1 to set for level_vpac_out_5_en_utc0_complete_3" "0,1" newline bitfld.long 0xB0 2. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_2,Status write 1 to set for level_vpac_out_5_en_utc0_complete_2" "0,1" newline bitfld.long 0xB0 1. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_1,Status write 1 to set for level_vpac_out_5_en_utc0_complete_1" "0,1" newline bitfld.long 0xB0 0. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_0,Status write 1 to set for level_vpac_out_5_en_utc0_complete_0" "0,1" line.long 0xB4 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_5_5,Status Register 45" bitfld.long 0xB4 31. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_31,Status write 1 to set for level_vpac_out_5_en_utc1_complete_31" "0,1" newline bitfld.long 0xB4 30. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_30,Status write 1 to set for level_vpac_out_5_en_utc1_complete_30" "0,1" newline bitfld.long 0xB4 29. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_29,Status write 1 to set for level_vpac_out_5_en_utc1_complete_29" "0,1" newline bitfld.long 0xB4 28. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_28,Status write 1 to set for level_vpac_out_5_en_utc1_complete_28" "0,1" newline bitfld.long 0xB4 27. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_27,Status write 1 to set for level_vpac_out_5_en_utc1_complete_27" "0,1" newline bitfld.long 0xB4 26. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_26,Status write 1 to set for level_vpac_out_5_en_utc1_complete_26" "0,1" newline bitfld.long 0xB4 25. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_25,Status write 1 to set for level_vpac_out_5_en_utc1_complete_25" "0,1" newline bitfld.long 0xB4 24. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_24,Status write 1 to set for level_vpac_out_5_en_utc1_complete_24" "0,1" newline bitfld.long 0xB4 23. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_23,Status write 1 to set for level_vpac_out_5_en_utc1_complete_23" "0,1" newline bitfld.long 0xB4 22. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_22,Status write 1 to set for level_vpac_out_5_en_utc1_complete_22" "0,1" newline bitfld.long 0xB4 21. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_21,Status write 1 to set for level_vpac_out_5_en_utc1_complete_21" "0,1" newline bitfld.long 0xB4 20. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_20,Status write 1 to set for level_vpac_out_5_en_utc1_complete_20" "0,1" newline bitfld.long 0xB4 19. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_19,Status write 1 to set for level_vpac_out_5_en_utc1_complete_19" "0,1" newline bitfld.long 0xB4 18. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_18,Status write 1 to set for level_vpac_out_5_en_utc1_complete_18" "0,1" newline bitfld.long 0xB4 17. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_17,Status write 1 to set for level_vpac_out_5_en_utc1_complete_17" "0,1" newline bitfld.long 0xB4 16. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_16,Status write 1 to set for level_vpac_out_5_en_utc1_complete_16" "0,1" newline bitfld.long 0xB4 15. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_15,Status write 1 to set for level_vpac_out_5_en_utc1_complete_15" "0,1" newline bitfld.long 0xB4 14. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_14,Status write 1 to set for level_vpac_out_5_en_utc1_complete_14" "0,1" newline bitfld.long 0xB4 13. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_13,Status write 1 to set for level_vpac_out_5_en_utc1_complete_13" "0,1" newline bitfld.long 0xB4 12. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_12,Status write 1 to set for level_vpac_out_5_en_utc1_complete_12" "0,1" newline bitfld.long 0xB4 11. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_11,Status write 1 to set for level_vpac_out_5_en_utc1_complete_11" "0,1" newline bitfld.long 0xB4 10. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_10,Status write 1 to set for level_vpac_out_5_en_utc1_complete_10" "0,1" newline bitfld.long 0xB4 9. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_9,Status write 1 to set for level_vpac_out_5_en_utc1_complete_9" "0,1" newline bitfld.long 0xB4 8. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_8,Status write 1 to set for level_vpac_out_5_en_utc1_complete_8" "0,1" newline bitfld.long 0xB4 7. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_7,Status write 1 to set for level_vpac_out_5_en_utc1_complete_7" "0,1" newline bitfld.long 0xB4 6. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_6,Status write 1 to set for level_vpac_out_5_en_utc1_complete_6" "0,1" newline bitfld.long 0xB4 5. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_5,Status write 1 to set for level_vpac_out_5_en_utc1_complete_5" "0,1" newline bitfld.long 0xB4 4. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_4,Status write 1 to set for level_vpac_out_5_en_utc1_complete_4" "0,1" newline bitfld.long 0xB4 3. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_3,Status write 1 to set for level_vpac_out_5_en_utc1_complete_3" "0,1" newline bitfld.long 0xB4 2. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_2,Status write 1 to set for level_vpac_out_5_en_utc1_complete_2" "0,1" newline bitfld.long 0xB4 1. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_1,Status write 1 to set for level_vpac_out_5_en_utc1_complete_1" "0,1" newline bitfld.long 0xB4 0. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_0,Status write 1 to set for level_vpac_out_5_en_utc1_complete_0" "0,1" line.long 0xB8 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_5_6,Status Register 46" bitfld.long 0xB8 31. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_63,Status write 1 to set for level_vpac_out_5_en_utc1_complete_63" "0,1" newline bitfld.long 0xB8 30. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_62,Status write 1 to set for level_vpac_out_5_en_utc1_complete_62" "0,1" newline bitfld.long 0xB8 29. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_61,Status write 1 to set for level_vpac_out_5_en_utc1_complete_61" "0,1" newline bitfld.long 0xB8 28. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_60,Status write 1 to set for level_vpac_out_5_en_utc1_complete_60" "0,1" newline bitfld.long 0xB8 27. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_59,Status write 1 to set for level_vpac_out_5_en_utc1_complete_59" "0,1" newline bitfld.long 0xB8 26. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_58,Status write 1 to set for level_vpac_out_5_en_utc1_complete_58" "0,1" newline bitfld.long 0xB8 25. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_57,Status write 1 to set for level_vpac_out_5_en_utc1_complete_57" "0,1" newline bitfld.long 0xB8 24. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_56,Status write 1 to set for level_vpac_out_5_en_utc1_complete_56" "0,1" newline bitfld.long 0xB8 23. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_55,Status write 1 to set for level_vpac_out_5_en_utc1_complete_55" "0,1" newline bitfld.long 0xB8 22. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_54,Status write 1 to set for level_vpac_out_5_en_utc1_complete_54" "0,1" newline bitfld.long 0xB8 21. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_53,Status write 1 to set for level_vpac_out_5_en_utc1_complete_53" "0,1" newline bitfld.long 0xB8 20. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_52,Status write 1 to set for level_vpac_out_5_en_utc1_complete_52" "0,1" newline bitfld.long 0xB8 19. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_51,Status write 1 to set for level_vpac_out_5_en_utc1_complete_51" "0,1" newline bitfld.long 0xB8 18. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_50,Status write 1 to set for level_vpac_out_5_en_utc1_complete_50" "0,1" newline bitfld.long 0xB8 17. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_49,Status write 1 to set for level_vpac_out_5_en_utc1_complete_49" "0,1" newline bitfld.long 0xB8 16. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_48,Status write 1 to set for level_vpac_out_5_en_utc1_complete_48" "0,1" newline bitfld.long 0xB8 15. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_47,Status write 1 to set for level_vpac_out_5_en_utc1_complete_47" "0,1" newline bitfld.long 0xB8 14. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_46,Status write 1 to set for level_vpac_out_5_en_utc1_complete_46" "0,1" newline bitfld.long 0xB8 13. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_45,Status write 1 to set for level_vpac_out_5_en_utc1_complete_45" "0,1" newline bitfld.long 0xB8 12. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_44,Status write 1 to set for level_vpac_out_5_en_utc1_complete_44" "0,1" newline bitfld.long 0xB8 11. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_43,Status write 1 to set for level_vpac_out_5_en_utc1_complete_43" "0,1" newline bitfld.long 0xB8 10. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_42,Status write 1 to set for level_vpac_out_5_en_utc1_complete_42" "0,1" newline bitfld.long 0xB8 9. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_41,Status write 1 to set for level_vpac_out_5_en_utc1_complete_41" "0,1" newline bitfld.long 0xB8 8. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_40,Status write 1 to set for level_vpac_out_5_en_utc1_complete_40" "0,1" newline bitfld.long 0xB8 7. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_39,Status write 1 to set for level_vpac_out_5_en_utc1_complete_39" "0,1" newline bitfld.long 0xB8 6. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_38,Status write 1 to set for level_vpac_out_5_en_utc1_complete_38" "0,1" newline bitfld.long 0xB8 5. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_37,Status write 1 to set for level_vpac_out_5_en_utc1_complete_37" "0,1" newline bitfld.long 0xB8 4. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_36,Status write 1 to set for level_vpac_out_5_en_utc1_complete_36" "0,1" newline bitfld.long 0xB8 3. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_35,Status write 1 to set for level_vpac_out_5_en_utc1_complete_35" "0,1" newline bitfld.long 0xB8 2. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_34,Status write 1 to set for level_vpac_out_5_en_utc1_complete_34" "0,1" newline bitfld.long 0xB8 1. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_33,Status write 1 to set for level_vpac_out_5_en_utc1_complete_33" "0,1" newline bitfld.long 0xB8 0. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_32,Status write 1 to set for level_vpac_out_5_en_utc1_complete_32" "0,1" line.long 0xBC "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_5_7,Status Register 47" bitfld.long 0xBC 4. "STATUS_LEVEL_VPAC_OUT_5_CTM_PULSE,Status write 1 to set for level_vpac_out_5_en_ctm_pulse" "0,1" newline bitfld.long 0xBC 3. "STATUS_LEVEL_VPAC_OUT_5_UTC1_PROT_ERR,Status write 1 to set for level_vpac_out_5_en_utc1_prot_err" "0,1" newline bitfld.long 0xBC 2. "STATUS_LEVEL_VPAC_OUT_5_UTC0_PROT_ERR,Status write 1 to set for level_vpac_out_5_en_utc0_prot_err" "0,1" newline bitfld.long 0xBC 1. "STATUS_LEVEL_VPAC_OUT_5_UTC1_ERROR,Status write 1 to set for level_vpac_out_5_en_utc1_error" "0,1" newline bitfld.long 0xBC 0. "STATUS_LEVEL_VPAC_OUT_5_UTC0_ERROR,Status write 1 to set for level_vpac_out_5_en_utc0_error" "0,1" line.long 0xC0 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_0_0,Status Register 48" bitfld.long 0xC0 26. "STATUS_PULSE_VPAC_OUT_0_VISS0_CR_CFG_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xC0 25. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for pulse_vpac_out_0_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xC0 24. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for pulse_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xC0 23. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xC0 22. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xC0 21. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xC0 20. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xC0 19. "STATUS_PULSE_VPAC_OUT_0_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xC0 18. "STATUS_PULSE_VPAC_OUT_0_VISS0_EE_CFG_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xC0 17. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xC0 16. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xC0 15. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCC_CFG_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xC0 14. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCFA_CFG_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xC0 13. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_VP_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xC0 12. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xC0 11. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xC0 10. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_FILT_DONE,Status write 1 to set for pulse_vpac_out_0_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xC0 9. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_FILT_START,Status write 1 to set for pulse_vpac_out_0_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xC0 8. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_CFG_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xC0 7. "STATUS_PULSE_VPAC_OUT_0_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xC0 6. "STATUS_PULSE_VPAC_OUT_0_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xC0 5. "STATUS_PULSE_VPAC_OUT_0_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xC0 4. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for pulse_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xC0 3. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for pulse_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xC0 2. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_AF_PULSE,Status write 1 to set for pulse_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xC0 1. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for pulse_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xC0 0. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_CFG_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1" line.long 0xC4 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_0_1,Status Register 49" bitfld.long 0xC4 8. "STATUS_PULSE_VPAC_OUT_0_LDC0_VBUSM_RD_ERR,Status write 1 to set for pulse_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xC4 7. "STATUS_PULSE_VPAC_OUT_0_LDC0_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_0_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xC4 6. "STATUS_PULSE_VPAC_OUT_0_LDC0_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_0_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xC4 5. "STATUS_PULSE_VPAC_OUT_0_LDC0_INT_SZOVF,Status write 1 to set for pulse_vpac_out_0_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xC4 4. "STATUS_PULSE_VPAC_OUT_0_LDC0_IFR_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_0_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xC4 3. "STATUS_PULSE_VPAC_OUT_0_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xC4 2. "STATUS_PULSE_VPAC_OUT_0_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xC4 1. "STATUS_PULSE_VPAC_OUT_0_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xC4 0. "STATUS_PULSE_VPAC_OUT_0_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xC8 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_0_2,Status Register 50" bitfld.long 0xC8 10. "STATUS_PULSE_VPAC_OUT_0_NF_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_0_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0xC8 9. "STATUS_PULSE_VPAC_OUT_0_NF_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_0_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0xC8 8. "STATUS_PULSE_VPAC_OUT_0_NF_FRAME_DONE,Status write 1 to set for pulse_vpac_out_0_en_nf_frame_done" "0,1" newline bitfld.long 0xC8 3. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xC8 2. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xC8 1. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for pulse_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xC8 0. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for pulse_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xCC "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_0_3,Status Register 51" bitfld.long 0xCC 26. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_6,Status write 1 to set for pulse_vpac_out_0_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xCC 25. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_5,Status write 1 to set for pulse_vpac_out_0_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xCC 24. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_4,Status write 1 to set for pulse_vpac_out_0_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xCC 22. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_2,Status write 1 to set for pulse_vpac_out_0_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xCC 20. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_vpac_out_0_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0xCC 19. "STATUS_PULSE_VPAC_OUT_0_SPARE_PEND_1_LEVEL,Status for pulse_vpac_out_0_en_spare_pend_1_level" "0,1" newline rbitfld.long 0xCC 18. "STATUS_PULSE_VPAC_OUT_0_SPARE_PEND_1_PULSE,Status for pulse_vpac_out_0_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0xCC 17. "STATUS_PULSE_VPAC_OUT_0_SPARE_PEND_0_LEVEL,Status for pulse_vpac_out_0_en_spare_pend_0_level" "0,1" newline rbitfld.long 0xCC 16. "STATUS_PULSE_VPAC_OUT_0_SPARE_PEND_0_PULSE,Status for pulse_vpac_out_0_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xCC 15. "STATUS_PULSE_VPAC_OUT_0_SPARE_DEC_1,Status write 1 to set for pulse_vpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0xCC 14. "STATUS_PULSE_VPAC_OUT_0_SPARE_DEC_0,Status write 1 to set for pulse_vpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0xCC 13. "STATUS_PULSE_VPAC_OUT_0_TDONE_6,Status write 1 to set for pulse_vpac_out_0_en_tdone_6" "0,1" newline bitfld.long 0xCC 12. "STATUS_PULSE_VPAC_OUT_0_TDONE_5,Status write 1 to set for pulse_vpac_out_0_en_tdone_5" "0,1" newline bitfld.long 0xCC 11. "STATUS_PULSE_VPAC_OUT_0_TDONE_4,Status write 1 to set for pulse_vpac_out_0_en_tdone_4" "0,1" newline bitfld.long 0xCC 9. "STATUS_PULSE_VPAC_OUT_0_TDONE_2,Status write 1 to set for pulse_vpac_out_0_en_tdone_2" "0,1" newline bitfld.long 0xCC 7. "STATUS_PULSE_VPAC_OUT_0_TDONE_0,Status write 1 to set for pulse_vpac_out_0_en_tdone_0" "0,1" newline bitfld.long 0xCC 6. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_6,Status write 1 to set for pulse_vpac_out_0_en_pipe_done_6" "0,1" newline bitfld.long 0xCC 5. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_5,Status write 1 to set for pulse_vpac_out_0_en_pipe_done_5" "0,1" newline bitfld.long 0xCC 4. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_4,Status write 1 to set for pulse_vpac_out_0_en_pipe_done_4" "0,1" newline bitfld.long 0xCC 3. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_3,Status write 1 to set for pulse_vpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0xCC 2. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_2,Status write 1 to set for pulse_vpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0xCC 1. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_1,Status write 1 to set for pulse_vpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0xCC 0. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_0,Status write 1 to set for pulse_vpac_out_0_en_pipe_done_0" "0,1" line.long 0xD0 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_0_4,Status Register 52" bitfld.long 0xD0 31. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_31,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_31" "0,1" newline bitfld.long 0xD0 30. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_30,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_30" "0,1" newline bitfld.long 0xD0 29. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_29,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_29" "0,1" newline bitfld.long 0xD0 28. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_28,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_28" "0,1" newline bitfld.long 0xD0 27. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_27,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_27" "0,1" newline bitfld.long 0xD0 26. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_26,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_26" "0,1" newline bitfld.long 0xD0 25. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_25,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_25" "0,1" newline bitfld.long 0xD0 24. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_24,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_24" "0,1" newline bitfld.long 0xD0 23. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_23,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_23" "0,1" newline bitfld.long 0xD0 22. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_22,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_22" "0,1" newline bitfld.long 0xD0 21. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_21,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_21" "0,1" newline bitfld.long 0xD0 20. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_20,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_20" "0,1" newline bitfld.long 0xD0 19. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_19,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_19" "0,1" newline bitfld.long 0xD0 18. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_18,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_18" "0,1" newline bitfld.long 0xD0 17. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_17,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_17" "0,1" newline bitfld.long 0xD0 16. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_16,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_16" "0,1" newline bitfld.long 0xD0 15. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_15,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_15" "0,1" newline bitfld.long 0xD0 14. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_14,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_14" "0,1" newline bitfld.long 0xD0 13. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_13,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_13" "0,1" newline bitfld.long 0xD0 12. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_12,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_12" "0,1" newline bitfld.long 0xD0 11. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_11,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_11" "0,1" newline bitfld.long 0xD0 10. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_10,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_10" "0,1" newline bitfld.long 0xD0 9. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_9,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_9" "0,1" newline bitfld.long 0xD0 8. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_8,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_8" "0,1" newline bitfld.long 0xD0 7. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_7,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_7" "0,1" newline bitfld.long 0xD0 6. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_6,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_6" "0,1" newline bitfld.long 0xD0 5. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_5,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_5" "0,1" newline bitfld.long 0xD0 4. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_4,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_4" "0,1" newline bitfld.long 0xD0 3. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_3,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_3" "0,1" newline bitfld.long 0xD0 2. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_2,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_2" "0,1" newline bitfld.long 0xD0 1. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_1,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_1" "0,1" newline bitfld.long 0xD0 0. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_0,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_0" "0,1" line.long 0xD4 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_0_5,Status Register 53" bitfld.long 0xD4 31. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_31,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_31" "0,1" newline bitfld.long 0xD4 30. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_30,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_30" "0,1" newline bitfld.long 0xD4 29. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_29,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_29" "0,1" newline bitfld.long 0xD4 28. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_28,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_28" "0,1" newline bitfld.long 0xD4 27. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_27,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_27" "0,1" newline bitfld.long 0xD4 26. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_26,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_26" "0,1" newline bitfld.long 0xD4 25. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_25,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_25" "0,1" newline bitfld.long 0xD4 24. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_24,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_24" "0,1" newline bitfld.long 0xD4 23. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_23,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_23" "0,1" newline bitfld.long 0xD4 22. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_22,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_22" "0,1" newline bitfld.long 0xD4 21. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_21,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_21" "0,1" newline bitfld.long 0xD4 20. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_20,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_20" "0,1" newline bitfld.long 0xD4 19. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_19,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_19" "0,1" newline bitfld.long 0xD4 18. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_18,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_18" "0,1" newline bitfld.long 0xD4 17. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_17,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_17" "0,1" newline bitfld.long 0xD4 16. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_16,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_16" "0,1" newline bitfld.long 0xD4 15. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_15,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_15" "0,1" newline bitfld.long 0xD4 14. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_14,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_14" "0,1" newline bitfld.long 0xD4 13. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_13,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_13" "0,1" newline bitfld.long 0xD4 12. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_12,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_12" "0,1" newline bitfld.long 0xD4 11. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_11,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_11" "0,1" newline bitfld.long 0xD4 10. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_10,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_10" "0,1" newline bitfld.long 0xD4 9. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_9,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_9" "0,1" newline bitfld.long 0xD4 8. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_8,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_8" "0,1" newline bitfld.long 0xD4 7. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_7,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_7" "0,1" newline bitfld.long 0xD4 6. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_6,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_6" "0,1" newline bitfld.long 0xD4 5. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_5,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_5" "0,1" newline bitfld.long 0xD4 4. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_4,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_4" "0,1" newline bitfld.long 0xD4 3. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_3,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_3" "0,1" newline bitfld.long 0xD4 2. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_2,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_2" "0,1" newline bitfld.long 0xD4 1. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_1,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_1" "0,1" newline bitfld.long 0xD4 0. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_0,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_0" "0,1" line.long 0xD8 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_0_6,Status Register 54" bitfld.long 0xD8 31. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_63,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_63" "0,1" newline bitfld.long 0xD8 30. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_62,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_62" "0,1" newline bitfld.long 0xD8 29. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_61,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_61" "0,1" newline bitfld.long 0xD8 28. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_60,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_60" "0,1" newline bitfld.long 0xD8 27. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_59,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_59" "0,1" newline bitfld.long 0xD8 26. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_58,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_58" "0,1" newline bitfld.long 0xD8 25. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_57,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_57" "0,1" newline bitfld.long 0xD8 24. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_56,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_56" "0,1" newline bitfld.long 0xD8 23. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_55,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_55" "0,1" newline bitfld.long 0xD8 22. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_54,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_54" "0,1" newline bitfld.long 0xD8 21. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_53,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_53" "0,1" newline bitfld.long 0xD8 20. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_52,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_52" "0,1" newline bitfld.long 0xD8 19. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_51,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_51" "0,1" newline bitfld.long 0xD8 18. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_50,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_50" "0,1" newline bitfld.long 0xD8 17. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_49,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_49" "0,1" newline bitfld.long 0xD8 16. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_48,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_48" "0,1" newline bitfld.long 0xD8 15. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_47,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_47" "0,1" newline bitfld.long 0xD8 14. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_46,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_46" "0,1" newline bitfld.long 0xD8 13. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_45,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_45" "0,1" newline bitfld.long 0xD8 12. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_44,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_44" "0,1" newline bitfld.long 0xD8 11. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_43,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_43" "0,1" newline bitfld.long 0xD8 10. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_42,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_42" "0,1" newline bitfld.long 0xD8 9. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_41,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_41" "0,1" newline bitfld.long 0xD8 8. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_40,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_40" "0,1" newline bitfld.long 0xD8 7. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_39,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_39" "0,1" newline bitfld.long 0xD8 6. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_38,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_38" "0,1" newline bitfld.long 0xD8 5. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_37,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_37" "0,1" newline bitfld.long 0xD8 4. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_36,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_36" "0,1" newline bitfld.long 0xD8 3. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_35,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_35" "0,1" newline bitfld.long 0xD8 2. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_34,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_34" "0,1" newline bitfld.long 0xD8 1. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_33,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_33" "0,1" newline bitfld.long 0xD8 0. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_32,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_32" "0,1" line.long 0xDC "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_0_7,Status Register 55" bitfld.long 0xDC 4. "STATUS_PULSE_VPAC_OUT_0_CTM_PULSE,Status write 1 to set for pulse_vpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0xDC 3. "STATUS_PULSE_VPAC_OUT_0_UTC1_PROT_ERR,Status write 1 to set for pulse_vpac_out_0_en_utc1_prot_err" "0,1" newline bitfld.long 0xDC 2. "STATUS_PULSE_VPAC_OUT_0_UTC0_PROT_ERR,Status write 1 to set for pulse_vpac_out_0_en_utc0_prot_err" "0,1" newline bitfld.long 0xDC 1. "STATUS_PULSE_VPAC_OUT_0_UTC1_ERROR,Status write 1 to set for pulse_vpac_out_0_en_utc1_error" "0,1" newline bitfld.long 0xDC 0. "STATUS_PULSE_VPAC_OUT_0_UTC0_ERROR,Status write 1 to set for pulse_vpac_out_0_en_utc0_error" "0,1" line.long 0xE0 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_1_0,Status Register 56" bitfld.long 0xE0 26. "STATUS_PULSE_VPAC_OUT_1_VISS0_CR_CFG_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xE0 25. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for pulse_vpac_out_1_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xE0 24. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for pulse_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xE0 23. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xE0 22. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xE0 21. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xE0 20. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xE0 19. "STATUS_PULSE_VPAC_OUT_1_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xE0 18. "STATUS_PULSE_VPAC_OUT_1_VISS0_EE_CFG_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xE0 17. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xE0 16. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xE0 15. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCC_CFG_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xE0 14. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCFA_CFG_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xE0 13. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_VP_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xE0 12. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xE0 11. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xE0 10. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_FILT_DONE,Status write 1 to set for pulse_vpac_out_1_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xE0 9. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_FILT_START,Status write 1 to set for pulse_vpac_out_1_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xE0 8. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_CFG_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xE0 7. "STATUS_PULSE_VPAC_OUT_1_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xE0 6. "STATUS_PULSE_VPAC_OUT_1_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xE0 5. "STATUS_PULSE_VPAC_OUT_1_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xE0 4. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for pulse_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xE0 3. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for pulse_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xE0 2. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_AF_PULSE,Status write 1 to set for pulse_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xE0 1. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for pulse_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xE0 0. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_CFG_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1" line.long 0xE4 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_1_1,Status Register 57" bitfld.long 0xE4 8. "STATUS_PULSE_VPAC_OUT_1_LDC0_VBUSM_RD_ERR,Status write 1 to set for pulse_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xE4 7. "STATUS_PULSE_VPAC_OUT_1_LDC0_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_1_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xE4 6. "STATUS_PULSE_VPAC_OUT_1_LDC0_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_1_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xE4 5. "STATUS_PULSE_VPAC_OUT_1_LDC0_INT_SZOVF,Status write 1 to set for pulse_vpac_out_1_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xE4 4. "STATUS_PULSE_VPAC_OUT_1_LDC0_IFR_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_1_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xE4 3. "STATUS_PULSE_VPAC_OUT_1_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xE4 2. "STATUS_PULSE_VPAC_OUT_1_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xE4 1. "STATUS_PULSE_VPAC_OUT_1_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xE4 0. "STATUS_PULSE_VPAC_OUT_1_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xE8 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_1_2,Status Register 58" bitfld.long 0xE8 10. "STATUS_PULSE_VPAC_OUT_1_NF_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_1_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0xE8 9. "STATUS_PULSE_VPAC_OUT_1_NF_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_1_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0xE8 8. "STATUS_PULSE_VPAC_OUT_1_NF_FRAME_DONE,Status write 1 to set for pulse_vpac_out_1_en_nf_frame_done" "0,1" newline bitfld.long 0xE8 3. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xE8 2. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xE8 1. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for pulse_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xE8 0. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for pulse_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xEC "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_1_3,Status Register 59" bitfld.long 0xEC 26. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_6,Status write 1 to set for pulse_vpac_out_1_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xEC 25. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_5,Status write 1 to set for pulse_vpac_out_1_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xEC 24. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_4,Status write 1 to set for pulse_vpac_out_1_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xEC 22. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_2,Status write 1 to set for pulse_vpac_out_1_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xEC 20. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_vpac_out_1_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0xEC 19. "STATUS_PULSE_VPAC_OUT_1_SPARE_PEND_1_LEVEL,Status for pulse_vpac_out_1_en_spare_pend_1_level" "0,1" newline rbitfld.long 0xEC 18. "STATUS_PULSE_VPAC_OUT_1_SPARE_PEND_1_PULSE,Status for pulse_vpac_out_1_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0xEC 17. "STATUS_PULSE_VPAC_OUT_1_SPARE_PEND_0_LEVEL,Status for pulse_vpac_out_1_en_spare_pend_0_level" "0,1" newline rbitfld.long 0xEC 16. "STATUS_PULSE_VPAC_OUT_1_SPARE_PEND_0_PULSE,Status for pulse_vpac_out_1_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xEC 15. "STATUS_PULSE_VPAC_OUT_1_SPARE_DEC_1,Status write 1 to set for pulse_vpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0xEC 14. "STATUS_PULSE_VPAC_OUT_1_SPARE_DEC_0,Status write 1 to set for pulse_vpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0xEC 13. "STATUS_PULSE_VPAC_OUT_1_TDONE_6,Status write 1 to set for pulse_vpac_out_1_en_tdone_6" "0,1" newline bitfld.long 0xEC 12. "STATUS_PULSE_VPAC_OUT_1_TDONE_5,Status write 1 to set for pulse_vpac_out_1_en_tdone_5" "0,1" newline bitfld.long 0xEC 11. "STATUS_PULSE_VPAC_OUT_1_TDONE_4,Status write 1 to set for pulse_vpac_out_1_en_tdone_4" "0,1" newline bitfld.long 0xEC 9. "STATUS_PULSE_VPAC_OUT_1_TDONE_2,Status write 1 to set for pulse_vpac_out_1_en_tdone_2" "0,1" newline bitfld.long 0xEC 7. "STATUS_PULSE_VPAC_OUT_1_TDONE_0,Status write 1 to set for pulse_vpac_out_1_en_tdone_0" "0,1" newline bitfld.long 0xEC 6. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_6,Status write 1 to set for pulse_vpac_out_1_en_pipe_done_6" "0,1" newline bitfld.long 0xEC 5. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_5,Status write 1 to set for pulse_vpac_out_1_en_pipe_done_5" "0,1" newline bitfld.long 0xEC 4. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_4,Status write 1 to set for pulse_vpac_out_1_en_pipe_done_4" "0,1" newline bitfld.long 0xEC 3. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_3,Status write 1 to set for pulse_vpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0xEC 2. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_2,Status write 1 to set for pulse_vpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0xEC 1. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_1,Status write 1 to set for pulse_vpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0xEC 0. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_0,Status write 1 to set for pulse_vpac_out_1_en_pipe_done_0" "0,1" line.long 0xF0 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_1_4,Status Register 60" bitfld.long 0xF0 31. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_31,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_31" "0,1" newline bitfld.long 0xF0 30. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_30,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_30" "0,1" newline bitfld.long 0xF0 29. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_29,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_29" "0,1" newline bitfld.long 0xF0 28. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_28,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_28" "0,1" newline bitfld.long 0xF0 27. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_27,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_27" "0,1" newline bitfld.long 0xF0 26. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_26,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_26" "0,1" newline bitfld.long 0xF0 25. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_25,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_25" "0,1" newline bitfld.long 0xF0 24. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_24,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_24" "0,1" newline bitfld.long 0xF0 23. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_23,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_23" "0,1" newline bitfld.long 0xF0 22. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_22,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_22" "0,1" newline bitfld.long 0xF0 21. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_21,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_21" "0,1" newline bitfld.long 0xF0 20. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_20,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_20" "0,1" newline bitfld.long 0xF0 19. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_19,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_19" "0,1" newline bitfld.long 0xF0 18. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_18,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_18" "0,1" newline bitfld.long 0xF0 17. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_17,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_17" "0,1" newline bitfld.long 0xF0 16. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_16,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_16" "0,1" newline bitfld.long 0xF0 15. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_15,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_15" "0,1" newline bitfld.long 0xF0 14. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_14,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_14" "0,1" newline bitfld.long 0xF0 13. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_13,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_13" "0,1" newline bitfld.long 0xF0 12. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_12,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_12" "0,1" newline bitfld.long 0xF0 11. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_11,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_11" "0,1" newline bitfld.long 0xF0 10. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_10,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_10" "0,1" newline bitfld.long 0xF0 9. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_9,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_9" "0,1" newline bitfld.long 0xF0 8. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_8,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_8" "0,1" newline bitfld.long 0xF0 7. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_7,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_7" "0,1" newline bitfld.long 0xF0 6. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_6,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_6" "0,1" newline bitfld.long 0xF0 5. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_5,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_5" "0,1" newline bitfld.long 0xF0 4. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_4,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_4" "0,1" newline bitfld.long 0xF0 3. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_3,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_3" "0,1" newline bitfld.long 0xF0 2. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_2,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_2" "0,1" newline bitfld.long 0xF0 1. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_1,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_1" "0,1" newline bitfld.long 0xF0 0. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_0,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_0" "0,1" line.long 0xF4 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_1_5,Status Register 61" bitfld.long 0xF4 31. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_31,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_31" "0,1" newline bitfld.long 0xF4 30. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_30,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_30" "0,1" newline bitfld.long 0xF4 29. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_29,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_29" "0,1" newline bitfld.long 0xF4 28. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_28,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_28" "0,1" newline bitfld.long 0xF4 27. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_27,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_27" "0,1" newline bitfld.long 0xF4 26. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_26,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_26" "0,1" newline bitfld.long 0xF4 25. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_25,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_25" "0,1" newline bitfld.long 0xF4 24. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_24,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_24" "0,1" newline bitfld.long 0xF4 23. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_23,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_23" "0,1" newline bitfld.long 0xF4 22. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_22,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_22" "0,1" newline bitfld.long 0xF4 21. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_21,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_21" "0,1" newline bitfld.long 0xF4 20. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_20,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_20" "0,1" newline bitfld.long 0xF4 19. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_19,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_19" "0,1" newline bitfld.long 0xF4 18. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_18,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_18" "0,1" newline bitfld.long 0xF4 17. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_17,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_17" "0,1" newline bitfld.long 0xF4 16. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_16,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_16" "0,1" newline bitfld.long 0xF4 15. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_15,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_15" "0,1" newline bitfld.long 0xF4 14. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_14,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_14" "0,1" newline bitfld.long 0xF4 13. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_13,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_13" "0,1" newline bitfld.long 0xF4 12. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_12,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_12" "0,1" newline bitfld.long 0xF4 11. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_11,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_11" "0,1" newline bitfld.long 0xF4 10. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_10,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_10" "0,1" newline bitfld.long 0xF4 9. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_9,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_9" "0,1" newline bitfld.long 0xF4 8. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_8,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_8" "0,1" newline bitfld.long 0xF4 7. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_7,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_7" "0,1" newline bitfld.long 0xF4 6. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_6,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_6" "0,1" newline bitfld.long 0xF4 5. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_5,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_5" "0,1" newline bitfld.long 0xF4 4. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_4,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_4" "0,1" newline bitfld.long 0xF4 3. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_3,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_3" "0,1" newline bitfld.long 0xF4 2. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_2,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_2" "0,1" newline bitfld.long 0xF4 1. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_1,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_1" "0,1" newline bitfld.long 0xF4 0. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_0,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_0" "0,1" line.long 0xF8 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_1_6,Status Register 62" bitfld.long 0xF8 31. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_63,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_63" "0,1" newline bitfld.long 0xF8 30. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_62,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_62" "0,1" newline bitfld.long 0xF8 29. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_61,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_61" "0,1" newline bitfld.long 0xF8 28. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_60,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_60" "0,1" newline bitfld.long 0xF8 27. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_59,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_59" "0,1" newline bitfld.long 0xF8 26. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_58,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_58" "0,1" newline bitfld.long 0xF8 25. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_57,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_57" "0,1" newline bitfld.long 0xF8 24. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_56,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_56" "0,1" newline bitfld.long 0xF8 23. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_55,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_55" "0,1" newline bitfld.long 0xF8 22. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_54,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_54" "0,1" newline bitfld.long 0xF8 21. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_53,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_53" "0,1" newline bitfld.long 0xF8 20. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_52,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_52" "0,1" newline bitfld.long 0xF8 19. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_51,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_51" "0,1" newline bitfld.long 0xF8 18. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_50,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_50" "0,1" newline bitfld.long 0xF8 17. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_49,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_49" "0,1" newline bitfld.long 0xF8 16. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_48,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_48" "0,1" newline bitfld.long 0xF8 15. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_47,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_47" "0,1" newline bitfld.long 0xF8 14. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_46,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_46" "0,1" newline bitfld.long 0xF8 13. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_45,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_45" "0,1" newline bitfld.long 0xF8 12. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_44,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_44" "0,1" newline bitfld.long 0xF8 11. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_43,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_43" "0,1" newline bitfld.long 0xF8 10. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_42,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_42" "0,1" newline bitfld.long 0xF8 9. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_41,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_41" "0,1" newline bitfld.long 0xF8 8. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_40,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_40" "0,1" newline bitfld.long 0xF8 7. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_39,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_39" "0,1" newline bitfld.long 0xF8 6. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_38,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_38" "0,1" newline bitfld.long 0xF8 5. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_37,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_37" "0,1" newline bitfld.long 0xF8 4. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_36,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_36" "0,1" newline bitfld.long 0xF8 3. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_35,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_35" "0,1" newline bitfld.long 0xF8 2. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_34,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_34" "0,1" newline bitfld.long 0xF8 1. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_33,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_33" "0,1" newline bitfld.long 0xF8 0. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_32,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_32" "0,1" line.long 0xFC "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_1_7,Status Register 63" bitfld.long 0xFC 4. "STATUS_PULSE_VPAC_OUT_1_CTM_PULSE,Status write 1 to set for pulse_vpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0xFC 3. "STATUS_PULSE_VPAC_OUT_1_UTC1_PROT_ERR,Status write 1 to set for pulse_vpac_out_1_en_utc1_prot_err" "0,1" newline bitfld.long 0xFC 2. "STATUS_PULSE_VPAC_OUT_1_UTC0_PROT_ERR,Status write 1 to set for pulse_vpac_out_1_en_utc0_prot_err" "0,1" newline bitfld.long 0xFC 1. "STATUS_PULSE_VPAC_OUT_1_UTC1_ERROR,Status write 1 to set for pulse_vpac_out_1_en_utc1_error" "0,1" newline bitfld.long 0xFC 0. "STATUS_PULSE_VPAC_OUT_1_UTC0_ERROR,Status write 1 to set for pulse_vpac_out_1_en_utc0_error" "0,1" line.long 0x100 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_2_0,Status Register 64" bitfld.long 0x100 26. "STATUS_PULSE_VPAC_OUT_2_VISS0_CR_CFG_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x100 25. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for pulse_vpac_out_2_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x100 24. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for pulse_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x100 23. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x100 22. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x100 21. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x100 20. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x100 19. "STATUS_PULSE_VPAC_OUT_2_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x100 18. "STATUS_PULSE_VPAC_OUT_2_VISS0_EE_CFG_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x100 17. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x100 16. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x100 15. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCC_CFG_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x100 14. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCFA_CFG_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x100 13. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_VP_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x100 12. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x100 11. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x100 10. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_FILT_DONE,Status write 1 to set for pulse_vpac_out_2_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x100 9. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_FILT_START,Status write 1 to set for pulse_vpac_out_2_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x100 8. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_CFG_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x100 7. "STATUS_PULSE_VPAC_OUT_2_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x100 6. "STATUS_PULSE_VPAC_OUT_2_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x100 5. "STATUS_PULSE_VPAC_OUT_2_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x100 4. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for pulse_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x100 3. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for pulse_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x100 2. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_AF_PULSE,Status write 1 to set for pulse_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x100 1. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for pulse_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x100 0. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_CFG_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1" line.long 0x104 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_2_1,Status Register 65" bitfld.long 0x104 8. "STATUS_PULSE_VPAC_OUT_2_LDC0_VBUSM_RD_ERR,Status write 1 to set for pulse_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x104 7. "STATUS_PULSE_VPAC_OUT_2_LDC0_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_2_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x104 6. "STATUS_PULSE_VPAC_OUT_2_LDC0_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_2_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x104 5. "STATUS_PULSE_VPAC_OUT_2_LDC0_INT_SZOVF,Status write 1 to set for pulse_vpac_out_2_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x104 4. "STATUS_PULSE_VPAC_OUT_2_LDC0_IFR_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_2_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x104 3. "STATUS_PULSE_VPAC_OUT_2_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x104 2. "STATUS_PULSE_VPAC_OUT_2_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x104 1. "STATUS_PULSE_VPAC_OUT_2_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x104 0. "STATUS_PULSE_VPAC_OUT_2_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x108 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_2_2,Status Register 66" bitfld.long 0x108 10. "STATUS_PULSE_VPAC_OUT_2_NF_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_2_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x108 9. "STATUS_PULSE_VPAC_OUT_2_NF_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_2_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x108 8. "STATUS_PULSE_VPAC_OUT_2_NF_FRAME_DONE,Status write 1 to set for pulse_vpac_out_2_en_nf_frame_done" "0,1" newline bitfld.long 0x108 3. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x108 2. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x108 1. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for pulse_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x108 0. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for pulse_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x10C "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_2_3,Status Register 67" bitfld.long 0x10C 26. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_6,Status write 1 to set for pulse_vpac_out_2_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x10C 25. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_5,Status write 1 to set for pulse_vpac_out_2_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x10C 24. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_4,Status write 1 to set for pulse_vpac_out_2_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x10C 22. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_2,Status write 1 to set for pulse_vpac_out_2_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x10C 20. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_vpac_out_2_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0x10C 19. "STATUS_PULSE_VPAC_OUT_2_SPARE_PEND_1_LEVEL,Status for pulse_vpac_out_2_en_spare_pend_1_level" "0,1" newline rbitfld.long 0x10C 18. "STATUS_PULSE_VPAC_OUT_2_SPARE_PEND_1_PULSE,Status for pulse_vpac_out_2_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0x10C 17. "STATUS_PULSE_VPAC_OUT_2_SPARE_PEND_0_LEVEL,Status for pulse_vpac_out_2_en_spare_pend_0_level" "0,1" newline rbitfld.long 0x10C 16. "STATUS_PULSE_VPAC_OUT_2_SPARE_PEND_0_PULSE,Status for pulse_vpac_out_2_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x10C 15. "STATUS_PULSE_VPAC_OUT_2_SPARE_DEC_1,Status write 1 to set for pulse_vpac_out_2_en_spare_dec_1" "0,1" newline bitfld.long 0x10C 14. "STATUS_PULSE_VPAC_OUT_2_SPARE_DEC_0,Status write 1 to set for pulse_vpac_out_2_en_spare_dec_0" "0,1" newline bitfld.long 0x10C 13. "STATUS_PULSE_VPAC_OUT_2_TDONE_6,Status write 1 to set for pulse_vpac_out_2_en_tdone_6" "0,1" newline bitfld.long 0x10C 12. "STATUS_PULSE_VPAC_OUT_2_TDONE_5,Status write 1 to set for pulse_vpac_out_2_en_tdone_5" "0,1" newline bitfld.long 0x10C 11. "STATUS_PULSE_VPAC_OUT_2_TDONE_4,Status write 1 to set for pulse_vpac_out_2_en_tdone_4" "0,1" newline bitfld.long 0x10C 9. "STATUS_PULSE_VPAC_OUT_2_TDONE_2,Status write 1 to set for pulse_vpac_out_2_en_tdone_2" "0,1" newline bitfld.long 0x10C 7. "STATUS_PULSE_VPAC_OUT_2_TDONE_0,Status write 1 to set for pulse_vpac_out_2_en_tdone_0" "0,1" newline bitfld.long 0x10C 6. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_6,Status write 1 to set for pulse_vpac_out_2_en_pipe_done_6" "0,1" newline bitfld.long 0x10C 5. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_5,Status write 1 to set for pulse_vpac_out_2_en_pipe_done_5" "0,1" newline bitfld.long 0x10C 4. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_4,Status write 1 to set for pulse_vpac_out_2_en_pipe_done_4" "0,1" newline bitfld.long 0x10C 3. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_3,Status write 1 to set for pulse_vpac_out_2_en_pipe_done_3" "0,1" newline bitfld.long 0x10C 2. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_2,Status write 1 to set for pulse_vpac_out_2_en_pipe_done_2" "0,1" newline bitfld.long 0x10C 1. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_1,Status write 1 to set for pulse_vpac_out_2_en_pipe_done_1" "0,1" newline bitfld.long 0x10C 0. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_0,Status write 1 to set for pulse_vpac_out_2_en_pipe_done_0" "0,1" line.long 0x110 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_2_4,Status Register 68" bitfld.long 0x110 31. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_31,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_31" "0,1" newline bitfld.long 0x110 30. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_30,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_30" "0,1" newline bitfld.long 0x110 29. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_29,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_29" "0,1" newline bitfld.long 0x110 28. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_28,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_28" "0,1" newline bitfld.long 0x110 27. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_27,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_27" "0,1" newline bitfld.long 0x110 26. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_26,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_26" "0,1" newline bitfld.long 0x110 25. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_25,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_25" "0,1" newline bitfld.long 0x110 24. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_24,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_24" "0,1" newline bitfld.long 0x110 23. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_23,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_23" "0,1" newline bitfld.long 0x110 22. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_22,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_22" "0,1" newline bitfld.long 0x110 21. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_21,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_21" "0,1" newline bitfld.long 0x110 20. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_20,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_20" "0,1" newline bitfld.long 0x110 19. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_19,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_19" "0,1" newline bitfld.long 0x110 18. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_18,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_18" "0,1" newline bitfld.long 0x110 17. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_17,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_17" "0,1" newline bitfld.long 0x110 16. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_16,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_16" "0,1" newline bitfld.long 0x110 15. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_15,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_15" "0,1" newline bitfld.long 0x110 14. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_14,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_14" "0,1" newline bitfld.long 0x110 13. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_13,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_13" "0,1" newline bitfld.long 0x110 12. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_12,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_12" "0,1" newline bitfld.long 0x110 11. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_11,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_11" "0,1" newline bitfld.long 0x110 10. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_10,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_10" "0,1" newline bitfld.long 0x110 9. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_9,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_9" "0,1" newline bitfld.long 0x110 8. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_8,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_8" "0,1" newline bitfld.long 0x110 7. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_7,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_7" "0,1" newline bitfld.long 0x110 6. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_6,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_6" "0,1" newline bitfld.long 0x110 5. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_5,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_5" "0,1" newline bitfld.long 0x110 4. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_4,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_4" "0,1" newline bitfld.long 0x110 3. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_3,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_3" "0,1" newline bitfld.long 0x110 2. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_2,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_2" "0,1" newline bitfld.long 0x110 1. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_1,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_1" "0,1" newline bitfld.long 0x110 0. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_0,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_0" "0,1" line.long 0x114 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_2_5,Status Register 69" bitfld.long 0x114 31. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_31,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_31" "0,1" newline bitfld.long 0x114 30. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_30,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_30" "0,1" newline bitfld.long 0x114 29. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_29,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_29" "0,1" newline bitfld.long 0x114 28. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_28,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_28" "0,1" newline bitfld.long 0x114 27. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_27,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_27" "0,1" newline bitfld.long 0x114 26. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_26,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_26" "0,1" newline bitfld.long 0x114 25. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_25,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_25" "0,1" newline bitfld.long 0x114 24. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_24,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_24" "0,1" newline bitfld.long 0x114 23. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_23,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_23" "0,1" newline bitfld.long 0x114 22. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_22,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_22" "0,1" newline bitfld.long 0x114 21. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_21,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_21" "0,1" newline bitfld.long 0x114 20. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_20,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_20" "0,1" newline bitfld.long 0x114 19. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_19,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_19" "0,1" newline bitfld.long 0x114 18. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_18,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_18" "0,1" newline bitfld.long 0x114 17. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_17,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_17" "0,1" newline bitfld.long 0x114 16. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_16,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_16" "0,1" newline bitfld.long 0x114 15. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_15,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_15" "0,1" newline bitfld.long 0x114 14. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_14,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_14" "0,1" newline bitfld.long 0x114 13. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_13,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_13" "0,1" newline bitfld.long 0x114 12. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_12,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_12" "0,1" newline bitfld.long 0x114 11. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_11,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_11" "0,1" newline bitfld.long 0x114 10. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_10,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_10" "0,1" newline bitfld.long 0x114 9. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_9,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_9" "0,1" newline bitfld.long 0x114 8. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_8,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_8" "0,1" newline bitfld.long 0x114 7. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_7,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_7" "0,1" newline bitfld.long 0x114 6. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_6,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_6" "0,1" newline bitfld.long 0x114 5. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_5,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_5" "0,1" newline bitfld.long 0x114 4. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_4,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_4" "0,1" newline bitfld.long 0x114 3. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_3,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_3" "0,1" newline bitfld.long 0x114 2. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_2,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_2" "0,1" newline bitfld.long 0x114 1. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_1,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_1" "0,1" newline bitfld.long 0x114 0. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_0,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_0" "0,1" line.long 0x118 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_2_6,Status Register 70" bitfld.long 0x118 31. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_63,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_63" "0,1" newline bitfld.long 0x118 30. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_62,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_62" "0,1" newline bitfld.long 0x118 29. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_61,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_61" "0,1" newline bitfld.long 0x118 28. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_60,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_60" "0,1" newline bitfld.long 0x118 27. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_59,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_59" "0,1" newline bitfld.long 0x118 26. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_58,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_58" "0,1" newline bitfld.long 0x118 25. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_57,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_57" "0,1" newline bitfld.long 0x118 24. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_56,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_56" "0,1" newline bitfld.long 0x118 23. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_55,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_55" "0,1" newline bitfld.long 0x118 22. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_54,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_54" "0,1" newline bitfld.long 0x118 21. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_53,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_53" "0,1" newline bitfld.long 0x118 20. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_52,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_52" "0,1" newline bitfld.long 0x118 19. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_51,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_51" "0,1" newline bitfld.long 0x118 18. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_50,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_50" "0,1" newline bitfld.long 0x118 17. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_49,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_49" "0,1" newline bitfld.long 0x118 16. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_48,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_48" "0,1" newline bitfld.long 0x118 15. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_47,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_47" "0,1" newline bitfld.long 0x118 14. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_46,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_46" "0,1" newline bitfld.long 0x118 13. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_45,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_45" "0,1" newline bitfld.long 0x118 12. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_44,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_44" "0,1" newline bitfld.long 0x118 11. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_43,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_43" "0,1" newline bitfld.long 0x118 10. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_42,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_42" "0,1" newline bitfld.long 0x118 9. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_41,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_41" "0,1" newline bitfld.long 0x118 8. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_40,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_40" "0,1" newline bitfld.long 0x118 7. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_39,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_39" "0,1" newline bitfld.long 0x118 6. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_38,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_38" "0,1" newline bitfld.long 0x118 5. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_37,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_37" "0,1" newline bitfld.long 0x118 4. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_36,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_36" "0,1" newline bitfld.long 0x118 3. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_35,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_35" "0,1" newline bitfld.long 0x118 2. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_34,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_34" "0,1" newline bitfld.long 0x118 1. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_33,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_33" "0,1" newline bitfld.long 0x118 0. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_32,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_32" "0,1" line.long 0x11C "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_2_7,Status Register 71" bitfld.long 0x11C 4. "STATUS_PULSE_VPAC_OUT_2_CTM_PULSE,Status write 1 to set for pulse_vpac_out_2_en_ctm_pulse" "0,1" newline bitfld.long 0x11C 3. "STATUS_PULSE_VPAC_OUT_2_UTC1_PROT_ERR,Status write 1 to set for pulse_vpac_out_2_en_utc1_prot_err" "0,1" newline bitfld.long 0x11C 2. "STATUS_PULSE_VPAC_OUT_2_UTC0_PROT_ERR,Status write 1 to set for pulse_vpac_out_2_en_utc0_prot_err" "0,1" newline bitfld.long 0x11C 1. "STATUS_PULSE_VPAC_OUT_2_UTC1_ERROR,Status write 1 to set for pulse_vpac_out_2_en_utc1_error" "0,1" newline bitfld.long 0x11C 0. "STATUS_PULSE_VPAC_OUT_2_UTC0_ERROR,Status write 1 to set for pulse_vpac_out_2_en_utc0_error" "0,1" line.long 0x120 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_3_0,Status Register 72" bitfld.long 0x120 26. "STATUS_PULSE_VPAC_OUT_3_VISS0_CR_CFG_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x120 25. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for pulse_vpac_out_3_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x120 24. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for pulse_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x120 23. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x120 22. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x120 21. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x120 20. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x120 19. "STATUS_PULSE_VPAC_OUT_3_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x120 18. "STATUS_PULSE_VPAC_OUT_3_VISS0_EE_CFG_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x120 17. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x120 16. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x120 15. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCC_CFG_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x120 14. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCFA_CFG_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x120 13. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_VP_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x120 12. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x120 11. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x120 10. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_FILT_DONE,Status write 1 to set for pulse_vpac_out_3_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x120 9. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_FILT_START,Status write 1 to set for pulse_vpac_out_3_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x120 8. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_CFG_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x120 7. "STATUS_PULSE_VPAC_OUT_3_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x120 6. "STATUS_PULSE_VPAC_OUT_3_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x120 5. "STATUS_PULSE_VPAC_OUT_3_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x120 4. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for pulse_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x120 3. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for pulse_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x120 2. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_AF_PULSE,Status write 1 to set for pulse_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x120 1. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for pulse_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x120 0. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_CFG_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1" line.long 0x124 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_3_1,Status Register 73" bitfld.long 0x124 8. "STATUS_PULSE_VPAC_OUT_3_LDC0_VBUSM_RD_ERR,Status write 1 to set for pulse_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x124 7. "STATUS_PULSE_VPAC_OUT_3_LDC0_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_3_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x124 6. "STATUS_PULSE_VPAC_OUT_3_LDC0_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_3_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x124 5. "STATUS_PULSE_VPAC_OUT_3_LDC0_INT_SZOVF,Status write 1 to set for pulse_vpac_out_3_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x124 4. "STATUS_PULSE_VPAC_OUT_3_LDC0_IFR_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_3_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x124 3. "STATUS_PULSE_VPAC_OUT_3_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x124 2. "STATUS_PULSE_VPAC_OUT_3_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x124 1. "STATUS_PULSE_VPAC_OUT_3_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x124 0. "STATUS_PULSE_VPAC_OUT_3_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x128 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_3_2,Status Register 74" bitfld.long 0x128 10. "STATUS_PULSE_VPAC_OUT_3_NF_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_3_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x128 9. "STATUS_PULSE_VPAC_OUT_3_NF_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_3_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x128 8. "STATUS_PULSE_VPAC_OUT_3_NF_FRAME_DONE,Status write 1 to set for pulse_vpac_out_3_en_nf_frame_done" "0,1" newline bitfld.long 0x128 3. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x128 2. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x128 1. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for pulse_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x128 0. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for pulse_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x12C "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_3_3,Status Register 75" bitfld.long 0x12C 26. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_6,Status write 1 to set for pulse_vpac_out_3_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x12C 25. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_5,Status write 1 to set for pulse_vpac_out_3_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x12C 24. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_4,Status write 1 to set for pulse_vpac_out_3_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x12C 22. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_2,Status write 1 to set for pulse_vpac_out_3_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x12C 20. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_vpac_out_3_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0x12C 19. "STATUS_PULSE_VPAC_OUT_3_SPARE_PEND_1_LEVEL,Status for pulse_vpac_out_3_en_spare_pend_1_level" "0,1" newline rbitfld.long 0x12C 18. "STATUS_PULSE_VPAC_OUT_3_SPARE_PEND_1_PULSE,Status for pulse_vpac_out_3_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0x12C 17. "STATUS_PULSE_VPAC_OUT_3_SPARE_PEND_0_LEVEL,Status for pulse_vpac_out_3_en_spare_pend_0_level" "0,1" newline rbitfld.long 0x12C 16. "STATUS_PULSE_VPAC_OUT_3_SPARE_PEND_0_PULSE,Status for pulse_vpac_out_3_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x12C 15. "STATUS_PULSE_VPAC_OUT_3_SPARE_DEC_1,Status write 1 to set for pulse_vpac_out_3_en_spare_dec_1" "0,1" newline bitfld.long 0x12C 14. "STATUS_PULSE_VPAC_OUT_3_SPARE_DEC_0,Status write 1 to set for pulse_vpac_out_3_en_spare_dec_0" "0,1" newline bitfld.long 0x12C 13. "STATUS_PULSE_VPAC_OUT_3_TDONE_6,Status write 1 to set for pulse_vpac_out_3_en_tdone_6" "0,1" newline bitfld.long 0x12C 12. "STATUS_PULSE_VPAC_OUT_3_TDONE_5,Status write 1 to set for pulse_vpac_out_3_en_tdone_5" "0,1" newline bitfld.long 0x12C 11. "STATUS_PULSE_VPAC_OUT_3_TDONE_4,Status write 1 to set for pulse_vpac_out_3_en_tdone_4" "0,1" newline bitfld.long 0x12C 9. "STATUS_PULSE_VPAC_OUT_3_TDONE_2,Status write 1 to set for pulse_vpac_out_3_en_tdone_2" "0,1" newline bitfld.long 0x12C 7. "STATUS_PULSE_VPAC_OUT_3_TDONE_0,Status write 1 to set for pulse_vpac_out_3_en_tdone_0" "0,1" newline bitfld.long 0x12C 6. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_6,Status write 1 to set for pulse_vpac_out_3_en_pipe_done_6" "0,1" newline bitfld.long 0x12C 5. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_5,Status write 1 to set for pulse_vpac_out_3_en_pipe_done_5" "0,1" newline bitfld.long 0x12C 4. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_4,Status write 1 to set for pulse_vpac_out_3_en_pipe_done_4" "0,1" newline bitfld.long 0x12C 3. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_3,Status write 1 to set for pulse_vpac_out_3_en_pipe_done_3" "0,1" newline bitfld.long 0x12C 2. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_2,Status write 1 to set for pulse_vpac_out_3_en_pipe_done_2" "0,1" newline bitfld.long 0x12C 1. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_1,Status write 1 to set for pulse_vpac_out_3_en_pipe_done_1" "0,1" newline bitfld.long 0x12C 0. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_0,Status write 1 to set for pulse_vpac_out_3_en_pipe_done_0" "0,1" line.long 0x130 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_3_4,Status Register 76" bitfld.long 0x130 31. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_31,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_31" "0,1" newline bitfld.long 0x130 30. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_30,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_30" "0,1" newline bitfld.long 0x130 29. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_29,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_29" "0,1" newline bitfld.long 0x130 28. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_28,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_28" "0,1" newline bitfld.long 0x130 27. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_27,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_27" "0,1" newline bitfld.long 0x130 26. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_26,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_26" "0,1" newline bitfld.long 0x130 25. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_25,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_25" "0,1" newline bitfld.long 0x130 24. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_24,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_24" "0,1" newline bitfld.long 0x130 23. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_23,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_23" "0,1" newline bitfld.long 0x130 22. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_22,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_22" "0,1" newline bitfld.long 0x130 21. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_21,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_21" "0,1" newline bitfld.long 0x130 20. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_20,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_20" "0,1" newline bitfld.long 0x130 19. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_19,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_19" "0,1" newline bitfld.long 0x130 18. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_18,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_18" "0,1" newline bitfld.long 0x130 17. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_17,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_17" "0,1" newline bitfld.long 0x130 16. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_16,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_16" "0,1" newline bitfld.long 0x130 15. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_15,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_15" "0,1" newline bitfld.long 0x130 14. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_14,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_14" "0,1" newline bitfld.long 0x130 13. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_13,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_13" "0,1" newline bitfld.long 0x130 12. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_12,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_12" "0,1" newline bitfld.long 0x130 11. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_11,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_11" "0,1" newline bitfld.long 0x130 10. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_10,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_10" "0,1" newline bitfld.long 0x130 9. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_9,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_9" "0,1" newline bitfld.long 0x130 8. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_8,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_8" "0,1" newline bitfld.long 0x130 7. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_7,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_7" "0,1" newline bitfld.long 0x130 6. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_6,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_6" "0,1" newline bitfld.long 0x130 5. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_5,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_5" "0,1" newline bitfld.long 0x130 4. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_4,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_4" "0,1" newline bitfld.long 0x130 3. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_3,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_3" "0,1" newline bitfld.long 0x130 2. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_2,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_2" "0,1" newline bitfld.long 0x130 1. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_1,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_1" "0,1" newline bitfld.long 0x130 0. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_0,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_0" "0,1" line.long 0x134 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_3_5,Status Register 77" bitfld.long 0x134 31. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_31,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_31" "0,1" newline bitfld.long 0x134 30. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_30,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_30" "0,1" newline bitfld.long 0x134 29. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_29,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_29" "0,1" newline bitfld.long 0x134 28. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_28,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_28" "0,1" newline bitfld.long 0x134 27. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_27,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_27" "0,1" newline bitfld.long 0x134 26. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_26,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_26" "0,1" newline bitfld.long 0x134 25. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_25,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_25" "0,1" newline bitfld.long 0x134 24. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_24,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_24" "0,1" newline bitfld.long 0x134 23. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_23,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_23" "0,1" newline bitfld.long 0x134 22. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_22,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_22" "0,1" newline bitfld.long 0x134 21. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_21,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_21" "0,1" newline bitfld.long 0x134 20. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_20,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_20" "0,1" newline bitfld.long 0x134 19. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_19,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_19" "0,1" newline bitfld.long 0x134 18. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_18,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_18" "0,1" newline bitfld.long 0x134 17. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_17,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_17" "0,1" newline bitfld.long 0x134 16. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_16,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_16" "0,1" newline bitfld.long 0x134 15. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_15,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_15" "0,1" newline bitfld.long 0x134 14. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_14,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_14" "0,1" newline bitfld.long 0x134 13. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_13,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_13" "0,1" newline bitfld.long 0x134 12. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_12,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_12" "0,1" newline bitfld.long 0x134 11. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_11,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_11" "0,1" newline bitfld.long 0x134 10. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_10,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_10" "0,1" newline bitfld.long 0x134 9. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_9,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_9" "0,1" newline bitfld.long 0x134 8. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_8,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_8" "0,1" newline bitfld.long 0x134 7. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_7,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_7" "0,1" newline bitfld.long 0x134 6. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_6,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_6" "0,1" newline bitfld.long 0x134 5. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_5,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_5" "0,1" newline bitfld.long 0x134 4. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_4,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_4" "0,1" newline bitfld.long 0x134 3. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_3,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_3" "0,1" newline bitfld.long 0x134 2. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_2,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_2" "0,1" newline bitfld.long 0x134 1. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_1,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_1" "0,1" newline bitfld.long 0x134 0. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_0,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_0" "0,1" line.long 0x138 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_3_6,Status Register 78" bitfld.long 0x138 31. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_63,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_63" "0,1" newline bitfld.long 0x138 30. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_62,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_62" "0,1" newline bitfld.long 0x138 29. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_61,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_61" "0,1" newline bitfld.long 0x138 28. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_60,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_60" "0,1" newline bitfld.long 0x138 27. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_59,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_59" "0,1" newline bitfld.long 0x138 26. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_58,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_58" "0,1" newline bitfld.long 0x138 25. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_57,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_57" "0,1" newline bitfld.long 0x138 24. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_56,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_56" "0,1" newline bitfld.long 0x138 23. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_55,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_55" "0,1" newline bitfld.long 0x138 22. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_54,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_54" "0,1" newline bitfld.long 0x138 21. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_53,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_53" "0,1" newline bitfld.long 0x138 20. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_52,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_52" "0,1" newline bitfld.long 0x138 19. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_51,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_51" "0,1" newline bitfld.long 0x138 18. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_50,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_50" "0,1" newline bitfld.long 0x138 17. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_49,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_49" "0,1" newline bitfld.long 0x138 16. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_48,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_48" "0,1" newline bitfld.long 0x138 15. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_47,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_47" "0,1" newline bitfld.long 0x138 14. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_46,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_46" "0,1" newline bitfld.long 0x138 13. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_45,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_45" "0,1" newline bitfld.long 0x138 12. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_44,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_44" "0,1" newline bitfld.long 0x138 11. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_43,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_43" "0,1" newline bitfld.long 0x138 10. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_42,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_42" "0,1" newline bitfld.long 0x138 9. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_41,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_41" "0,1" newline bitfld.long 0x138 8. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_40,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_40" "0,1" newline bitfld.long 0x138 7. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_39,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_39" "0,1" newline bitfld.long 0x138 6. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_38,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_38" "0,1" newline bitfld.long 0x138 5. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_37,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_37" "0,1" newline bitfld.long 0x138 4. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_36,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_36" "0,1" newline bitfld.long 0x138 3. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_35,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_35" "0,1" newline bitfld.long 0x138 2. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_34,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_34" "0,1" newline bitfld.long 0x138 1. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_33,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_33" "0,1" newline bitfld.long 0x138 0. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_32,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_32" "0,1" line.long 0x13C "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_3_7,Status Register 79" bitfld.long 0x13C 4. "STATUS_PULSE_VPAC_OUT_3_CTM_PULSE,Status write 1 to set for pulse_vpac_out_3_en_ctm_pulse" "0,1" newline bitfld.long 0x13C 3. "STATUS_PULSE_VPAC_OUT_3_UTC1_PROT_ERR,Status write 1 to set for pulse_vpac_out_3_en_utc1_prot_err" "0,1" newline bitfld.long 0x13C 2. "STATUS_PULSE_VPAC_OUT_3_UTC0_PROT_ERR,Status write 1 to set for pulse_vpac_out_3_en_utc0_prot_err" "0,1" newline bitfld.long 0x13C 1. "STATUS_PULSE_VPAC_OUT_3_UTC1_ERROR,Status write 1 to set for pulse_vpac_out_3_en_utc1_error" "0,1" newline bitfld.long 0x13C 0. "STATUS_PULSE_VPAC_OUT_3_UTC0_ERROR,Status write 1 to set for pulse_vpac_out_3_en_utc0_error" "0,1" line.long 0x140 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_4_0,Status Register 80" bitfld.long 0x140 26. "STATUS_PULSE_VPAC_OUT_4_VISS0_CR_CFG_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x140 25. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for pulse_vpac_out_4_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x140 24. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for pulse_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x140 23. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x140 22. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x140 21. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x140 20. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x140 19. "STATUS_PULSE_VPAC_OUT_4_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x140 18. "STATUS_PULSE_VPAC_OUT_4_VISS0_EE_CFG_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x140 17. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x140 16. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x140 15. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCC_CFG_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x140 14. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCFA_CFG_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x140 13. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_VP_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x140 12. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x140 11. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x140 10. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_FILT_DONE,Status write 1 to set for pulse_vpac_out_4_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x140 9. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_FILT_START,Status write 1 to set for pulse_vpac_out_4_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x140 8. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_CFG_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x140 7. "STATUS_PULSE_VPAC_OUT_4_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x140 6. "STATUS_PULSE_VPAC_OUT_4_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x140 5. "STATUS_PULSE_VPAC_OUT_4_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x140 4. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for pulse_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x140 3. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for pulse_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x140 2. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_AF_PULSE,Status write 1 to set for pulse_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x140 1. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for pulse_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x140 0. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_CFG_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1" line.long 0x144 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_4_1,Status Register 81" bitfld.long 0x144 8. "STATUS_PULSE_VPAC_OUT_4_LDC0_VBUSM_RD_ERR,Status write 1 to set for pulse_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x144 7. "STATUS_PULSE_VPAC_OUT_4_LDC0_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_4_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x144 6. "STATUS_PULSE_VPAC_OUT_4_LDC0_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_4_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x144 5. "STATUS_PULSE_VPAC_OUT_4_LDC0_INT_SZOVF,Status write 1 to set for pulse_vpac_out_4_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x144 4. "STATUS_PULSE_VPAC_OUT_4_LDC0_IFR_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_4_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x144 3. "STATUS_PULSE_VPAC_OUT_4_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x144 2. "STATUS_PULSE_VPAC_OUT_4_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x144 1. "STATUS_PULSE_VPAC_OUT_4_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x144 0. "STATUS_PULSE_VPAC_OUT_4_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x148 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_4_2,Status Register 82" bitfld.long 0x148 10. "STATUS_PULSE_VPAC_OUT_4_NF_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_4_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x148 9. "STATUS_PULSE_VPAC_OUT_4_NF_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_4_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x148 8. "STATUS_PULSE_VPAC_OUT_4_NF_FRAME_DONE,Status write 1 to set for pulse_vpac_out_4_en_nf_frame_done" "0,1" newline bitfld.long 0x148 3. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x148 2. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x148 1. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for pulse_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x148 0. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for pulse_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x14C "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_4_3,Status Register 83" bitfld.long 0x14C 26. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_6,Status write 1 to set for pulse_vpac_out_4_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x14C 25. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_5,Status write 1 to set for pulse_vpac_out_4_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x14C 24. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_4,Status write 1 to set for pulse_vpac_out_4_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x14C 22. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_2,Status write 1 to set for pulse_vpac_out_4_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x14C 20. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_vpac_out_4_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0x14C 19. "STATUS_PULSE_VPAC_OUT_4_SPARE_PEND_1_LEVEL,Status for pulse_vpac_out_4_en_spare_pend_1_level" "0,1" newline rbitfld.long 0x14C 18. "STATUS_PULSE_VPAC_OUT_4_SPARE_PEND_1_PULSE,Status for pulse_vpac_out_4_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0x14C 17. "STATUS_PULSE_VPAC_OUT_4_SPARE_PEND_0_LEVEL,Status for pulse_vpac_out_4_en_spare_pend_0_level" "0,1" newline rbitfld.long 0x14C 16. "STATUS_PULSE_VPAC_OUT_4_SPARE_PEND_0_PULSE,Status for pulse_vpac_out_4_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x14C 15. "STATUS_PULSE_VPAC_OUT_4_SPARE_DEC_1,Status write 1 to set for pulse_vpac_out_4_en_spare_dec_1" "0,1" newline bitfld.long 0x14C 14. "STATUS_PULSE_VPAC_OUT_4_SPARE_DEC_0,Status write 1 to set for pulse_vpac_out_4_en_spare_dec_0" "0,1" newline bitfld.long 0x14C 13. "STATUS_PULSE_VPAC_OUT_4_TDONE_6,Status write 1 to set for pulse_vpac_out_4_en_tdone_6" "0,1" newline bitfld.long 0x14C 12. "STATUS_PULSE_VPAC_OUT_4_TDONE_5,Status write 1 to set for pulse_vpac_out_4_en_tdone_5" "0,1" newline bitfld.long 0x14C 11. "STATUS_PULSE_VPAC_OUT_4_TDONE_4,Status write 1 to set for pulse_vpac_out_4_en_tdone_4" "0,1" newline bitfld.long 0x14C 9. "STATUS_PULSE_VPAC_OUT_4_TDONE_2,Status write 1 to set for pulse_vpac_out_4_en_tdone_2" "0,1" newline bitfld.long 0x14C 7. "STATUS_PULSE_VPAC_OUT_4_TDONE_0,Status write 1 to set for pulse_vpac_out_4_en_tdone_0" "0,1" newline bitfld.long 0x14C 6. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_6,Status write 1 to set for pulse_vpac_out_4_en_pipe_done_6" "0,1" newline bitfld.long 0x14C 5. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_5,Status write 1 to set for pulse_vpac_out_4_en_pipe_done_5" "0,1" newline bitfld.long 0x14C 4. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_4,Status write 1 to set for pulse_vpac_out_4_en_pipe_done_4" "0,1" newline bitfld.long 0x14C 3. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_3,Status write 1 to set for pulse_vpac_out_4_en_pipe_done_3" "0,1" newline bitfld.long 0x14C 2. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_2,Status write 1 to set for pulse_vpac_out_4_en_pipe_done_2" "0,1" newline bitfld.long 0x14C 1. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_1,Status write 1 to set for pulse_vpac_out_4_en_pipe_done_1" "0,1" newline bitfld.long 0x14C 0. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_0,Status write 1 to set for pulse_vpac_out_4_en_pipe_done_0" "0,1" line.long 0x150 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_4_4,Status Register 84" bitfld.long 0x150 31. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_31,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_31" "0,1" newline bitfld.long 0x150 30. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_30,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_30" "0,1" newline bitfld.long 0x150 29. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_29,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_29" "0,1" newline bitfld.long 0x150 28. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_28,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_28" "0,1" newline bitfld.long 0x150 27. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_27,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_27" "0,1" newline bitfld.long 0x150 26. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_26,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_26" "0,1" newline bitfld.long 0x150 25. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_25,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_25" "0,1" newline bitfld.long 0x150 24. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_24,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_24" "0,1" newline bitfld.long 0x150 23. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_23,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_23" "0,1" newline bitfld.long 0x150 22. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_22,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_22" "0,1" newline bitfld.long 0x150 21. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_21,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_21" "0,1" newline bitfld.long 0x150 20. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_20,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_20" "0,1" newline bitfld.long 0x150 19. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_19,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_19" "0,1" newline bitfld.long 0x150 18. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_18,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_18" "0,1" newline bitfld.long 0x150 17. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_17,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_17" "0,1" newline bitfld.long 0x150 16. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_16,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_16" "0,1" newline bitfld.long 0x150 15. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_15,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_15" "0,1" newline bitfld.long 0x150 14. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_14,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_14" "0,1" newline bitfld.long 0x150 13. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_13,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_13" "0,1" newline bitfld.long 0x150 12. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_12,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_12" "0,1" newline bitfld.long 0x150 11. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_11,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_11" "0,1" newline bitfld.long 0x150 10. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_10,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_10" "0,1" newline bitfld.long 0x150 9. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_9,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_9" "0,1" newline bitfld.long 0x150 8. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_8,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_8" "0,1" newline bitfld.long 0x150 7. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_7,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_7" "0,1" newline bitfld.long 0x150 6. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_6,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_6" "0,1" newline bitfld.long 0x150 5. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_5,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_5" "0,1" newline bitfld.long 0x150 4. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_4,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_4" "0,1" newline bitfld.long 0x150 3. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_3,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_3" "0,1" newline bitfld.long 0x150 2. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_2,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_2" "0,1" newline bitfld.long 0x150 1. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_1,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_1" "0,1" newline bitfld.long 0x150 0. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_0,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_0" "0,1" line.long 0x154 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_4_5,Status Register 85" bitfld.long 0x154 31. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_31,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_31" "0,1" newline bitfld.long 0x154 30. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_30,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_30" "0,1" newline bitfld.long 0x154 29. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_29,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_29" "0,1" newline bitfld.long 0x154 28. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_28,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_28" "0,1" newline bitfld.long 0x154 27. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_27,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_27" "0,1" newline bitfld.long 0x154 26. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_26,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_26" "0,1" newline bitfld.long 0x154 25. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_25,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_25" "0,1" newline bitfld.long 0x154 24. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_24,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_24" "0,1" newline bitfld.long 0x154 23. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_23,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_23" "0,1" newline bitfld.long 0x154 22. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_22,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_22" "0,1" newline bitfld.long 0x154 21. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_21,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_21" "0,1" newline bitfld.long 0x154 20. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_20,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_20" "0,1" newline bitfld.long 0x154 19. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_19,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_19" "0,1" newline bitfld.long 0x154 18. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_18,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_18" "0,1" newline bitfld.long 0x154 17. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_17,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_17" "0,1" newline bitfld.long 0x154 16. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_16,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_16" "0,1" newline bitfld.long 0x154 15. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_15,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_15" "0,1" newline bitfld.long 0x154 14. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_14,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_14" "0,1" newline bitfld.long 0x154 13. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_13,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_13" "0,1" newline bitfld.long 0x154 12. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_12,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_12" "0,1" newline bitfld.long 0x154 11. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_11,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_11" "0,1" newline bitfld.long 0x154 10. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_10,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_10" "0,1" newline bitfld.long 0x154 9. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_9,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_9" "0,1" newline bitfld.long 0x154 8. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_8,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_8" "0,1" newline bitfld.long 0x154 7. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_7,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_7" "0,1" newline bitfld.long 0x154 6. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_6,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_6" "0,1" newline bitfld.long 0x154 5. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_5,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_5" "0,1" newline bitfld.long 0x154 4. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_4,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_4" "0,1" newline bitfld.long 0x154 3. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_3,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_3" "0,1" newline bitfld.long 0x154 2. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_2,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_2" "0,1" newline bitfld.long 0x154 1. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_1,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_1" "0,1" newline bitfld.long 0x154 0. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_0,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_0" "0,1" line.long 0x158 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_4_6,Status Register 86" bitfld.long 0x158 31. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_63,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_63" "0,1" newline bitfld.long 0x158 30. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_62,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_62" "0,1" newline bitfld.long 0x158 29. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_61,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_61" "0,1" newline bitfld.long 0x158 28. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_60,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_60" "0,1" newline bitfld.long 0x158 27. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_59,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_59" "0,1" newline bitfld.long 0x158 26. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_58,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_58" "0,1" newline bitfld.long 0x158 25. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_57,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_57" "0,1" newline bitfld.long 0x158 24. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_56,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_56" "0,1" newline bitfld.long 0x158 23. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_55,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_55" "0,1" newline bitfld.long 0x158 22. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_54,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_54" "0,1" newline bitfld.long 0x158 21. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_53,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_53" "0,1" newline bitfld.long 0x158 20. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_52,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_52" "0,1" newline bitfld.long 0x158 19. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_51,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_51" "0,1" newline bitfld.long 0x158 18. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_50,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_50" "0,1" newline bitfld.long 0x158 17. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_49,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_49" "0,1" newline bitfld.long 0x158 16. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_48,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_48" "0,1" newline bitfld.long 0x158 15. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_47,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_47" "0,1" newline bitfld.long 0x158 14. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_46,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_46" "0,1" newline bitfld.long 0x158 13. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_45,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_45" "0,1" newline bitfld.long 0x158 12. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_44,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_44" "0,1" newline bitfld.long 0x158 11. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_43,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_43" "0,1" newline bitfld.long 0x158 10. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_42,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_42" "0,1" newline bitfld.long 0x158 9. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_41,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_41" "0,1" newline bitfld.long 0x158 8. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_40,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_40" "0,1" newline bitfld.long 0x158 7. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_39,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_39" "0,1" newline bitfld.long 0x158 6. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_38,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_38" "0,1" newline bitfld.long 0x158 5. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_37,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_37" "0,1" newline bitfld.long 0x158 4. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_36,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_36" "0,1" newline bitfld.long 0x158 3. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_35,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_35" "0,1" newline bitfld.long 0x158 2. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_34,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_34" "0,1" newline bitfld.long 0x158 1. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_33,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_33" "0,1" newline bitfld.long 0x158 0. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_32,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_32" "0,1" line.long 0x15C "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_4_7,Status Register 87" bitfld.long 0x15C 4. "STATUS_PULSE_VPAC_OUT_4_CTM_PULSE,Status write 1 to set for pulse_vpac_out_4_en_ctm_pulse" "0,1" newline bitfld.long 0x15C 3. "STATUS_PULSE_VPAC_OUT_4_UTC1_PROT_ERR,Status write 1 to set for pulse_vpac_out_4_en_utc1_prot_err" "0,1" newline bitfld.long 0x15C 2. "STATUS_PULSE_VPAC_OUT_4_UTC0_PROT_ERR,Status write 1 to set for pulse_vpac_out_4_en_utc0_prot_err" "0,1" newline bitfld.long 0x15C 1. "STATUS_PULSE_VPAC_OUT_4_UTC1_ERROR,Status write 1 to set for pulse_vpac_out_4_en_utc1_error" "0,1" newline bitfld.long 0x15C 0. "STATUS_PULSE_VPAC_OUT_4_UTC0_ERROR,Status write 1 to set for pulse_vpac_out_4_en_utc0_error" "0,1" line.long 0x160 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_5_0,Status Register 88" bitfld.long 0x160 26. "STATUS_PULSE_VPAC_OUT_5_VISS0_CR_CFG_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x160 25. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for pulse_vpac_out_5_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x160 24. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for pulse_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x160 23. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x160 22. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x160 21. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x160 20. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x160 19. "STATUS_PULSE_VPAC_OUT_5_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x160 18. "STATUS_PULSE_VPAC_OUT_5_VISS0_EE_CFG_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x160 17. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x160 16. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x160 15. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCC_CFG_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x160 14. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCFA_CFG_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x160 13. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_VP_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x160 12. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x160 11. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x160 10. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_FILT_DONE,Status write 1 to set for pulse_vpac_out_5_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x160 9. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_FILT_START,Status write 1 to set for pulse_vpac_out_5_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x160 8. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_CFG_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x160 7. "STATUS_PULSE_VPAC_OUT_5_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x160 6. "STATUS_PULSE_VPAC_OUT_5_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x160 5. "STATUS_PULSE_VPAC_OUT_5_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x160 4. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for pulse_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x160 3. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for pulse_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x160 2. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_AF_PULSE,Status write 1 to set for pulse_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x160 1. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for pulse_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x160 0. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_CFG_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1" line.long 0x164 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_5_1,Status Register 89" bitfld.long 0x164 8. "STATUS_PULSE_VPAC_OUT_5_LDC0_VBUSM_RD_ERR,Status write 1 to set for pulse_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x164 7. "STATUS_PULSE_VPAC_OUT_5_LDC0_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_5_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x164 6. "STATUS_PULSE_VPAC_OUT_5_LDC0_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_5_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x164 5. "STATUS_PULSE_VPAC_OUT_5_LDC0_INT_SZOVF,Status write 1 to set for pulse_vpac_out_5_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x164 4. "STATUS_PULSE_VPAC_OUT_5_LDC0_IFR_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_5_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x164 3. "STATUS_PULSE_VPAC_OUT_5_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x164 2. "STATUS_PULSE_VPAC_OUT_5_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x164 1. "STATUS_PULSE_VPAC_OUT_5_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x164 0. "STATUS_PULSE_VPAC_OUT_5_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x168 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_5_2,Status Register 90" bitfld.long 0x168 10. "STATUS_PULSE_VPAC_OUT_5_NF_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_5_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x168 9. "STATUS_PULSE_VPAC_OUT_5_NF_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_5_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x168 8. "STATUS_PULSE_VPAC_OUT_5_NF_FRAME_DONE,Status write 1 to set for pulse_vpac_out_5_en_nf_frame_done" "0,1" newline bitfld.long 0x168 3. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x168 2. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x168 1. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for pulse_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x168 0. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for pulse_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x16C "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_5_3,Status Register 91" bitfld.long 0x16C 26. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_6,Status write 1 to set for pulse_vpac_out_5_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x16C 25. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_5,Status write 1 to set for pulse_vpac_out_5_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x16C 24. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_4,Status write 1 to set for pulse_vpac_out_5_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x16C 22. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_2,Status write 1 to set for pulse_vpac_out_5_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x16C 20. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_vpac_out_5_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0x16C 19. "STATUS_PULSE_VPAC_OUT_5_SPARE_PEND_1_LEVEL,Status for pulse_vpac_out_5_en_spare_pend_1_level" "0,1" newline rbitfld.long 0x16C 18. "STATUS_PULSE_VPAC_OUT_5_SPARE_PEND_1_PULSE,Status for pulse_vpac_out_5_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0x16C 17. "STATUS_PULSE_VPAC_OUT_5_SPARE_PEND_0_LEVEL,Status for pulse_vpac_out_5_en_spare_pend_0_level" "0,1" newline rbitfld.long 0x16C 16. "STATUS_PULSE_VPAC_OUT_5_SPARE_PEND_0_PULSE,Status for pulse_vpac_out_5_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x16C 15. "STATUS_PULSE_VPAC_OUT_5_SPARE_DEC_1,Status write 1 to set for pulse_vpac_out_5_en_spare_dec_1" "0,1" newline bitfld.long 0x16C 14. "STATUS_PULSE_VPAC_OUT_5_SPARE_DEC_0,Status write 1 to set for pulse_vpac_out_5_en_spare_dec_0" "0,1" newline bitfld.long 0x16C 13. "STATUS_PULSE_VPAC_OUT_5_TDONE_6,Status write 1 to set for pulse_vpac_out_5_en_tdone_6" "0,1" newline bitfld.long 0x16C 12. "STATUS_PULSE_VPAC_OUT_5_TDONE_5,Status write 1 to set for pulse_vpac_out_5_en_tdone_5" "0,1" newline bitfld.long 0x16C 11. "STATUS_PULSE_VPAC_OUT_5_TDONE_4,Status write 1 to set for pulse_vpac_out_5_en_tdone_4" "0,1" newline bitfld.long 0x16C 9. "STATUS_PULSE_VPAC_OUT_5_TDONE_2,Status write 1 to set for pulse_vpac_out_5_en_tdone_2" "0,1" newline bitfld.long 0x16C 7. "STATUS_PULSE_VPAC_OUT_5_TDONE_0,Status write 1 to set for pulse_vpac_out_5_en_tdone_0" "0,1" newline bitfld.long 0x16C 6. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_6,Status write 1 to set for pulse_vpac_out_5_en_pipe_done_6" "0,1" newline bitfld.long 0x16C 5. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_5,Status write 1 to set for pulse_vpac_out_5_en_pipe_done_5" "0,1" newline bitfld.long 0x16C 4. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_4,Status write 1 to set for pulse_vpac_out_5_en_pipe_done_4" "0,1" newline bitfld.long 0x16C 3. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_3,Status write 1 to set for pulse_vpac_out_5_en_pipe_done_3" "0,1" newline bitfld.long 0x16C 2. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_2,Status write 1 to set for pulse_vpac_out_5_en_pipe_done_2" "0,1" newline bitfld.long 0x16C 1. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_1,Status write 1 to set for pulse_vpac_out_5_en_pipe_done_1" "0,1" newline bitfld.long 0x16C 0. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_0,Status write 1 to set for pulse_vpac_out_5_en_pipe_done_0" "0,1" line.long 0x170 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_5_4,Status Register 92" bitfld.long 0x170 31. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_31,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_31" "0,1" newline bitfld.long 0x170 30. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_30,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_30" "0,1" newline bitfld.long 0x170 29. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_29,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_29" "0,1" newline bitfld.long 0x170 28. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_28,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_28" "0,1" newline bitfld.long 0x170 27. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_27,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_27" "0,1" newline bitfld.long 0x170 26. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_26,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_26" "0,1" newline bitfld.long 0x170 25. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_25,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_25" "0,1" newline bitfld.long 0x170 24. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_24,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_24" "0,1" newline bitfld.long 0x170 23. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_23,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_23" "0,1" newline bitfld.long 0x170 22. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_22,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_22" "0,1" newline bitfld.long 0x170 21. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_21,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_21" "0,1" newline bitfld.long 0x170 20. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_20,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_20" "0,1" newline bitfld.long 0x170 19. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_19,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_19" "0,1" newline bitfld.long 0x170 18. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_18,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_18" "0,1" newline bitfld.long 0x170 17. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_17,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_17" "0,1" newline bitfld.long 0x170 16. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_16,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_16" "0,1" newline bitfld.long 0x170 15. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_15,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_15" "0,1" newline bitfld.long 0x170 14. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_14,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_14" "0,1" newline bitfld.long 0x170 13. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_13,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_13" "0,1" newline bitfld.long 0x170 12. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_12,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_12" "0,1" newline bitfld.long 0x170 11. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_11,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_11" "0,1" newline bitfld.long 0x170 10. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_10,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_10" "0,1" newline bitfld.long 0x170 9. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_9,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_9" "0,1" newline bitfld.long 0x170 8. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_8,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_8" "0,1" newline bitfld.long 0x170 7. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_7,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_7" "0,1" newline bitfld.long 0x170 6. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_6,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_6" "0,1" newline bitfld.long 0x170 5. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_5,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_5" "0,1" newline bitfld.long 0x170 4. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_4,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_4" "0,1" newline bitfld.long 0x170 3. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_3,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_3" "0,1" newline bitfld.long 0x170 2. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_2,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_2" "0,1" newline bitfld.long 0x170 1. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_1,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_1" "0,1" newline bitfld.long 0x170 0. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_0,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_0" "0,1" line.long 0x174 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_5_5,Status Register 93" bitfld.long 0x174 31. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_31,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_31" "0,1" newline bitfld.long 0x174 30. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_30,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_30" "0,1" newline bitfld.long 0x174 29. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_29,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_29" "0,1" newline bitfld.long 0x174 28. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_28,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_28" "0,1" newline bitfld.long 0x174 27. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_27,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_27" "0,1" newline bitfld.long 0x174 26. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_26,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_26" "0,1" newline bitfld.long 0x174 25. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_25,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_25" "0,1" newline bitfld.long 0x174 24. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_24,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_24" "0,1" newline bitfld.long 0x174 23. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_23,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_23" "0,1" newline bitfld.long 0x174 22. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_22,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_22" "0,1" newline bitfld.long 0x174 21. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_21,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_21" "0,1" newline bitfld.long 0x174 20. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_20,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_20" "0,1" newline bitfld.long 0x174 19. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_19,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_19" "0,1" newline bitfld.long 0x174 18. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_18,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_18" "0,1" newline bitfld.long 0x174 17. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_17,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_17" "0,1" newline bitfld.long 0x174 16. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_16,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_16" "0,1" newline bitfld.long 0x174 15. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_15,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_15" "0,1" newline bitfld.long 0x174 14. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_14,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_14" "0,1" newline bitfld.long 0x174 13. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_13,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_13" "0,1" newline bitfld.long 0x174 12. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_12,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_12" "0,1" newline bitfld.long 0x174 11. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_11,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_11" "0,1" newline bitfld.long 0x174 10. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_10,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_10" "0,1" newline bitfld.long 0x174 9. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_9,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_9" "0,1" newline bitfld.long 0x174 8. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_8,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_8" "0,1" newline bitfld.long 0x174 7. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_7,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_7" "0,1" newline bitfld.long 0x174 6. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_6,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_6" "0,1" newline bitfld.long 0x174 5. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_5,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_5" "0,1" newline bitfld.long 0x174 4. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_4,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_4" "0,1" newline bitfld.long 0x174 3. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_3,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_3" "0,1" newline bitfld.long 0x174 2. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_2,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_2" "0,1" newline bitfld.long 0x174 1. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_1,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_1" "0,1" newline bitfld.long 0x174 0. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_0,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_0" "0,1" line.long 0x178 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_5_6,Status Register 94" bitfld.long 0x178 31. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_63,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_63" "0,1" newline bitfld.long 0x178 30. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_62,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_62" "0,1" newline bitfld.long 0x178 29. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_61,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_61" "0,1" newline bitfld.long 0x178 28. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_60,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_60" "0,1" newline bitfld.long 0x178 27. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_59,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_59" "0,1" newline bitfld.long 0x178 26. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_58,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_58" "0,1" newline bitfld.long 0x178 25. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_57,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_57" "0,1" newline bitfld.long 0x178 24. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_56,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_56" "0,1" newline bitfld.long 0x178 23. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_55,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_55" "0,1" newline bitfld.long 0x178 22. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_54,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_54" "0,1" newline bitfld.long 0x178 21. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_53,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_53" "0,1" newline bitfld.long 0x178 20. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_52,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_52" "0,1" newline bitfld.long 0x178 19. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_51,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_51" "0,1" newline bitfld.long 0x178 18. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_50,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_50" "0,1" newline bitfld.long 0x178 17. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_49,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_49" "0,1" newline bitfld.long 0x178 16. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_48,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_48" "0,1" newline bitfld.long 0x178 15. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_47,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_47" "0,1" newline bitfld.long 0x178 14. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_46,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_46" "0,1" newline bitfld.long 0x178 13. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_45,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_45" "0,1" newline bitfld.long 0x178 12. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_44,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_44" "0,1" newline bitfld.long 0x178 11. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_43,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_43" "0,1" newline bitfld.long 0x178 10. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_42,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_42" "0,1" newline bitfld.long 0x178 9. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_41,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_41" "0,1" newline bitfld.long 0x178 8. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_40,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_40" "0,1" newline bitfld.long 0x178 7. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_39,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_39" "0,1" newline bitfld.long 0x178 6. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_38,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_38" "0,1" newline bitfld.long 0x178 5. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_37,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_37" "0,1" newline bitfld.long 0x178 4. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_36,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_36" "0,1" newline bitfld.long 0x178 3. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_35,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_35" "0,1" newline bitfld.long 0x178 2. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_34,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_34" "0,1" newline bitfld.long 0x178 1. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_33,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_33" "0,1" newline bitfld.long 0x178 0. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_32,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_32" "0,1" line.long 0x17C "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_5_7,Status Register 95" bitfld.long 0x17C 4. "STATUS_PULSE_VPAC_OUT_5_CTM_PULSE,Status write 1 to set for pulse_vpac_out_5_en_ctm_pulse" "0,1" newline bitfld.long 0x17C 3. "STATUS_PULSE_VPAC_OUT_5_UTC1_PROT_ERR,Status write 1 to set for pulse_vpac_out_5_en_utc1_prot_err" "0,1" newline bitfld.long 0x17C 2. "STATUS_PULSE_VPAC_OUT_5_UTC0_PROT_ERR,Status write 1 to set for pulse_vpac_out_5_en_utc0_prot_err" "0,1" newline bitfld.long 0x17C 1. "STATUS_PULSE_VPAC_OUT_5_UTC1_ERROR,Status write 1 to set for pulse_vpac_out_5_en_utc1_error" "0,1" newline bitfld.long 0x17C 0. "STATUS_PULSE_VPAC_OUT_5_UTC0_ERROR,Status write 1 to set for pulse_vpac_out_5_en_utc0_error" "0,1" rgroup.long 0x700++0x17F line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_0_0,Status Clear Register 0" bitfld.long 0x0 26. "STATUS_LEVEL_VPAC_OUT_0_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x0 25. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x0 24. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x0 23. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x0 22. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x0 21. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x0 20. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x0 19. "STATUS_LEVEL_VPAC_OUT_0_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x0 18. "STATUS_LEVEL_VPAC_OUT_0_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x0 17. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x0 16. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x0 15. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x0 14. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x0 13. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x0 12. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x0 11. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x0 10. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x0 9. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x0 8. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x0 7. "STATUS_LEVEL_VPAC_OUT_0_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x0 6. "STATUS_LEVEL_VPAC_OUT_0_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x0 5. "STATUS_LEVEL_VPAC_OUT_0_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x0 4. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x0 3. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x0 2. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x0 1. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x0 0. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_0_1,Status Clear Register 1" bitfld.long 0x4 8. "STATUS_LEVEL_VPAC_OUT_0_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x4 7. "STATUS_LEVEL_VPAC_OUT_0_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x4 6. "STATUS_LEVEL_VPAC_OUT_0_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x4 5. "STATUS_LEVEL_VPAC_OUT_0_LDC0_INT_SZOVF_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x4 4. "STATUS_LEVEL_VPAC_OUT_0_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x4 3. "STATUS_LEVEL_VPAC_OUT_0_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x4 2. "STATUS_LEVEL_VPAC_OUT_0_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x4 1. "STATUS_LEVEL_VPAC_OUT_0_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x4 0. "STATUS_LEVEL_VPAC_OUT_0_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x8 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_0_2,Status Clear Register 2" bitfld.long 0x8 10. "STATUS_LEVEL_VPAC_OUT_0_NF_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x8 9. "STATUS_LEVEL_VPAC_OUT_0_NF_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x8 8. "STATUS_LEVEL_VPAC_OUT_0_NF_FRAME_DONE_CLR,Status write 1 to clear for level_vpac_out_0_en_nf_frame_done" "0,1" newline bitfld.long 0x8 3. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x8 2. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x8 1. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for level_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x8 0. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for level_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xC "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_0_3,Status Clear Register 3" bitfld.long 0xC 26. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for level_vpac_out_0_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xC 25. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for level_vpac_out_0_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xC 24. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for level_vpac_out_0_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xC 22. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for level_vpac_out_0_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xC 20. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_vpac_out_0_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xC 15. "STATUS_LEVEL_VPAC_OUT_0_SPARE_DEC_1_CLR,Status write 1 to clear for level_vpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0xC 14. "STATUS_LEVEL_VPAC_OUT_0_SPARE_DEC_0_CLR,Status write 1 to clear for level_vpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0xC 13. "STATUS_LEVEL_VPAC_OUT_0_TDONE_6_CLR,Status write 1 to clear for level_vpac_out_0_en_tdone_6" "0,1" newline bitfld.long 0xC 12. "STATUS_LEVEL_VPAC_OUT_0_TDONE_5_CLR,Status write 1 to clear for level_vpac_out_0_en_tdone_5" "0,1" newline bitfld.long 0xC 11. "STATUS_LEVEL_VPAC_OUT_0_TDONE_4_CLR,Status write 1 to clear for level_vpac_out_0_en_tdone_4" "0,1" newline bitfld.long 0xC 9. "STATUS_LEVEL_VPAC_OUT_0_TDONE_2_CLR,Status write 1 to clear for level_vpac_out_0_en_tdone_2" "0,1" newline bitfld.long 0xC 7. "STATUS_LEVEL_VPAC_OUT_0_TDONE_0_CLR,Status write 1 to clear for level_vpac_out_0_en_tdone_0" "0,1" newline bitfld.long 0xC 6. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_6_CLR,Status write 1 to clear for level_vpac_out_0_en_pipe_done_6" "0,1" newline bitfld.long 0xC 5. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_5_CLR,Status write 1 to clear for level_vpac_out_0_en_pipe_done_5" "0,1" newline bitfld.long 0xC 4. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_4_CLR,Status write 1 to clear for level_vpac_out_0_en_pipe_done_4" "0,1" newline bitfld.long 0xC 3. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_3_CLR,Status write 1 to clear for level_vpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0xC 2. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_2_CLR,Status write 1 to clear for level_vpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0xC 1. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_1_CLR,Status write 1 to clear for level_vpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0xC 0. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_0_CLR,Status write 1 to clear for level_vpac_out_0_en_pipe_done_0" "0,1" line.long 0x10 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_0_4,Status Clear Register 4" bitfld.long 0x10 31. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_31" "0,1" newline bitfld.long 0x10 30. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_30" "0,1" newline bitfld.long 0x10 29. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_29" "0,1" newline bitfld.long 0x10 28. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_28" "0,1" newline bitfld.long 0x10 27. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_27" "0,1" newline bitfld.long 0x10 26. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_26" "0,1" newline bitfld.long 0x10 25. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_25" "0,1" newline bitfld.long 0x10 24. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_24" "0,1" newline bitfld.long 0x10 23. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_23" "0,1" newline bitfld.long 0x10 22. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_22" "0,1" newline bitfld.long 0x10 21. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_21" "0,1" newline bitfld.long 0x10 20. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_20" "0,1" newline bitfld.long 0x10 19. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_19" "0,1" newline bitfld.long 0x10 18. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_18" "0,1" newline bitfld.long 0x10 17. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_17" "0,1" newline bitfld.long 0x10 16. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_16" "0,1" newline bitfld.long 0x10 15. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_15" "0,1" newline bitfld.long 0x10 14. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_14" "0,1" newline bitfld.long 0x10 13. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_13" "0,1" newline bitfld.long 0x10 12. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_12" "0,1" newline bitfld.long 0x10 11. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_11" "0,1" newline bitfld.long 0x10 10. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_10" "0,1" newline bitfld.long 0x10 9. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_9" "0,1" newline bitfld.long 0x10 8. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_8" "0,1" newline bitfld.long 0x10 7. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_7" "0,1" newline bitfld.long 0x10 6. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_6" "0,1" newline bitfld.long 0x10 5. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_5" "0,1" newline bitfld.long 0x10 4. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_4" "0,1" newline bitfld.long 0x10 3. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_3" "0,1" newline bitfld.long 0x10 2. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_2" "0,1" newline bitfld.long 0x10 1. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_1" "0,1" newline bitfld.long 0x10 0. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_0" "0,1" line.long 0x14 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_0_5,Status Clear Register 5" bitfld.long 0x14 31. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_31" "0,1" newline bitfld.long 0x14 30. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_30" "0,1" newline bitfld.long 0x14 29. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_29" "0,1" newline bitfld.long 0x14 28. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_28" "0,1" newline bitfld.long 0x14 27. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_27" "0,1" newline bitfld.long 0x14 26. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_26" "0,1" newline bitfld.long 0x14 25. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_25" "0,1" newline bitfld.long 0x14 24. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_24" "0,1" newline bitfld.long 0x14 23. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_23" "0,1" newline bitfld.long 0x14 22. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_22" "0,1" newline bitfld.long 0x14 21. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_21" "0,1" newline bitfld.long 0x14 20. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_20" "0,1" newline bitfld.long 0x14 19. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_19" "0,1" newline bitfld.long 0x14 18. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_18" "0,1" newline bitfld.long 0x14 17. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_17" "0,1" newline bitfld.long 0x14 16. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_16" "0,1" newline bitfld.long 0x14 15. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_15" "0,1" newline bitfld.long 0x14 14. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_14" "0,1" newline bitfld.long 0x14 13. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_13" "0,1" newline bitfld.long 0x14 12. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_12" "0,1" newline bitfld.long 0x14 11. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_11" "0,1" newline bitfld.long 0x14 10. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_10" "0,1" newline bitfld.long 0x14 9. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_9" "0,1" newline bitfld.long 0x14 8. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_8" "0,1" newline bitfld.long 0x14 7. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_7" "0,1" newline bitfld.long 0x14 6. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_6" "0,1" newline bitfld.long 0x14 5. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_5" "0,1" newline bitfld.long 0x14 4. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_4" "0,1" newline bitfld.long 0x14 3. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_3" "0,1" newline bitfld.long 0x14 2. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_2" "0,1" newline bitfld.long 0x14 1. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_1" "0,1" newline bitfld.long 0x14 0. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_0" "0,1" line.long 0x18 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_0_6,Status Clear Register 6" bitfld.long 0x18 31. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_63_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_63" "0,1" newline bitfld.long 0x18 30. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_62_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_62" "0,1" newline bitfld.long 0x18 29. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_61_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_61" "0,1" newline bitfld.long 0x18 28. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_60_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_60" "0,1" newline bitfld.long 0x18 27. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_59_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_59" "0,1" newline bitfld.long 0x18 26. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_58_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_58" "0,1" newline bitfld.long 0x18 25. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_57_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_57" "0,1" newline bitfld.long 0x18 24. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_56_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_56" "0,1" newline bitfld.long 0x18 23. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_55_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_55" "0,1" newline bitfld.long 0x18 22. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_54_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_54" "0,1" newline bitfld.long 0x18 21. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_53_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_53" "0,1" newline bitfld.long 0x18 20. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_52_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_52" "0,1" newline bitfld.long 0x18 19. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_51_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_51" "0,1" newline bitfld.long 0x18 18. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_50_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_50" "0,1" newline bitfld.long 0x18 17. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_49_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_49" "0,1" newline bitfld.long 0x18 16. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_48_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_48" "0,1" newline bitfld.long 0x18 15. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_47_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_47" "0,1" newline bitfld.long 0x18 14. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_46_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_46" "0,1" newline bitfld.long 0x18 13. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_45_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_45" "0,1" newline bitfld.long 0x18 12. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_44_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_44" "0,1" newline bitfld.long 0x18 11. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_43_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_43" "0,1" newline bitfld.long 0x18 10. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_42_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_42" "0,1" newline bitfld.long 0x18 9. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_41_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_41" "0,1" newline bitfld.long 0x18 8. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_40_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_40" "0,1" newline bitfld.long 0x18 7. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_39_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_39" "0,1" newline bitfld.long 0x18 6. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_38_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_38" "0,1" newline bitfld.long 0x18 5. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_37_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_37" "0,1" newline bitfld.long 0x18 4. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_36_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_36" "0,1" newline bitfld.long 0x18 3. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_35_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_35" "0,1" newline bitfld.long 0x18 2. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_34_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_34" "0,1" newline bitfld.long 0x18 1. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_33_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_33" "0,1" newline bitfld.long 0x18 0. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_32_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_32" "0,1" line.long 0x1C "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_0_7,Status Clear Register 7" bitfld.long 0x1C 4. "STATUS_LEVEL_VPAC_OUT_0_CTM_PULSE_CLR,Status write 1 to clear for level_vpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0x1C 3. "STATUS_LEVEL_VPAC_OUT_0_UTC1_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_prot_err" "0,1" newline bitfld.long 0x1C 2. "STATUS_LEVEL_VPAC_OUT_0_UTC0_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_prot_err" "0,1" newline bitfld.long 0x1C 1. "STATUS_LEVEL_VPAC_OUT_0_UTC1_ERROR_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_error" "0,1" newline bitfld.long 0x1C 0. "STATUS_LEVEL_VPAC_OUT_0_UTC0_ERROR_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_error" "0,1" line.long 0x20 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_1_0,Status Clear Register 8" bitfld.long 0x20 26. "STATUS_LEVEL_VPAC_OUT_1_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x20 25. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x20 24. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x20 23. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x20 22. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x20 21. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x20 20. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x20 19. "STATUS_LEVEL_VPAC_OUT_1_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x20 18. "STATUS_LEVEL_VPAC_OUT_1_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x20 17. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x20 16. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x20 15. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x20 14. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x20 13. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x20 12. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x20 11. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x20 10. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x20 9. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x20 8. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x20 7. "STATUS_LEVEL_VPAC_OUT_1_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x20 6. "STATUS_LEVEL_VPAC_OUT_1_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x20 5. "STATUS_LEVEL_VPAC_OUT_1_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x20 4. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x20 3. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x20 2. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x20 1. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x20 0. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1" line.long 0x24 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_1_1,Status Clear Register 9" bitfld.long 0x24 8. "STATUS_LEVEL_VPAC_OUT_1_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x24 7. "STATUS_LEVEL_VPAC_OUT_1_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x24 6. "STATUS_LEVEL_VPAC_OUT_1_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x24 5. "STATUS_LEVEL_VPAC_OUT_1_LDC0_INT_SZOVF_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x24 4. "STATUS_LEVEL_VPAC_OUT_1_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x24 3. "STATUS_LEVEL_VPAC_OUT_1_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x24 2. "STATUS_LEVEL_VPAC_OUT_1_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x24 1. "STATUS_LEVEL_VPAC_OUT_1_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x24 0. "STATUS_LEVEL_VPAC_OUT_1_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x28 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_1_2,Status Clear Register 10" bitfld.long 0x28 10. "STATUS_LEVEL_VPAC_OUT_1_NF_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x28 9. "STATUS_LEVEL_VPAC_OUT_1_NF_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x28 8. "STATUS_LEVEL_VPAC_OUT_1_NF_FRAME_DONE_CLR,Status write 1 to clear for level_vpac_out_1_en_nf_frame_done" "0,1" newline bitfld.long 0x28 3. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x28 2. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x28 1. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for level_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x28 0. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for level_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x2C "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_1_3,Status Clear Register 11" bitfld.long 0x2C 26. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for level_vpac_out_1_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x2C 25. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for level_vpac_out_1_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x2C 24. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for level_vpac_out_1_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x2C 22. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for level_vpac_out_1_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x2C 20. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_vpac_out_1_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x2C 15. "STATUS_LEVEL_VPAC_OUT_1_SPARE_DEC_1_CLR,Status write 1 to clear for level_vpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0x2C 14. "STATUS_LEVEL_VPAC_OUT_1_SPARE_DEC_0_CLR,Status write 1 to clear for level_vpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0x2C 13. "STATUS_LEVEL_VPAC_OUT_1_TDONE_6_CLR,Status write 1 to clear for level_vpac_out_1_en_tdone_6" "0,1" newline bitfld.long 0x2C 12. "STATUS_LEVEL_VPAC_OUT_1_TDONE_5_CLR,Status write 1 to clear for level_vpac_out_1_en_tdone_5" "0,1" newline bitfld.long 0x2C 11. "STATUS_LEVEL_VPAC_OUT_1_TDONE_4_CLR,Status write 1 to clear for level_vpac_out_1_en_tdone_4" "0,1" newline bitfld.long 0x2C 9. "STATUS_LEVEL_VPAC_OUT_1_TDONE_2_CLR,Status write 1 to clear for level_vpac_out_1_en_tdone_2" "0,1" newline bitfld.long 0x2C 7. "STATUS_LEVEL_VPAC_OUT_1_TDONE_0_CLR,Status write 1 to clear for level_vpac_out_1_en_tdone_0" "0,1" newline bitfld.long 0x2C 6. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_6_CLR,Status write 1 to clear for level_vpac_out_1_en_pipe_done_6" "0,1" newline bitfld.long 0x2C 5. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_5_CLR,Status write 1 to clear for level_vpac_out_1_en_pipe_done_5" "0,1" newline bitfld.long 0x2C 4. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_4_CLR,Status write 1 to clear for level_vpac_out_1_en_pipe_done_4" "0,1" newline bitfld.long 0x2C 3. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_3_CLR,Status write 1 to clear for level_vpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0x2C 2. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_2_CLR,Status write 1 to clear for level_vpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0x2C 1. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_1_CLR,Status write 1 to clear for level_vpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0x2C 0. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_0_CLR,Status write 1 to clear for level_vpac_out_1_en_pipe_done_0" "0,1" line.long 0x30 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_1_4,Status Clear Register 12" bitfld.long 0x30 31. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_31" "0,1" newline bitfld.long 0x30 30. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_30" "0,1" newline bitfld.long 0x30 29. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_29" "0,1" newline bitfld.long 0x30 28. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_28" "0,1" newline bitfld.long 0x30 27. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_27" "0,1" newline bitfld.long 0x30 26. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_26" "0,1" newline bitfld.long 0x30 25. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_25" "0,1" newline bitfld.long 0x30 24. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_24" "0,1" newline bitfld.long 0x30 23. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_23" "0,1" newline bitfld.long 0x30 22. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_22" "0,1" newline bitfld.long 0x30 21. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_21" "0,1" newline bitfld.long 0x30 20. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_20" "0,1" newline bitfld.long 0x30 19. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_19" "0,1" newline bitfld.long 0x30 18. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_18" "0,1" newline bitfld.long 0x30 17. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_17" "0,1" newline bitfld.long 0x30 16. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_16" "0,1" newline bitfld.long 0x30 15. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_15" "0,1" newline bitfld.long 0x30 14. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_14" "0,1" newline bitfld.long 0x30 13. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_13" "0,1" newline bitfld.long 0x30 12. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_12" "0,1" newline bitfld.long 0x30 11. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_11" "0,1" newline bitfld.long 0x30 10. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_10" "0,1" newline bitfld.long 0x30 9. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_9" "0,1" newline bitfld.long 0x30 8. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_8" "0,1" newline bitfld.long 0x30 7. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_7" "0,1" newline bitfld.long 0x30 6. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_6" "0,1" newline bitfld.long 0x30 5. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_5" "0,1" newline bitfld.long 0x30 4. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_4" "0,1" newline bitfld.long 0x30 3. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_3" "0,1" newline bitfld.long 0x30 2. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_2" "0,1" newline bitfld.long 0x30 1. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_1" "0,1" newline bitfld.long 0x30 0. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_0" "0,1" line.long 0x34 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_1_5,Status Clear Register 13" bitfld.long 0x34 31. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_31" "0,1" newline bitfld.long 0x34 30. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_30" "0,1" newline bitfld.long 0x34 29. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_29" "0,1" newline bitfld.long 0x34 28. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_28" "0,1" newline bitfld.long 0x34 27. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_27" "0,1" newline bitfld.long 0x34 26. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_26" "0,1" newline bitfld.long 0x34 25. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_25" "0,1" newline bitfld.long 0x34 24. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_24" "0,1" newline bitfld.long 0x34 23. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_23" "0,1" newline bitfld.long 0x34 22. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_22" "0,1" newline bitfld.long 0x34 21. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_21" "0,1" newline bitfld.long 0x34 20. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_20" "0,1" newline bitfld.long 0x34 19. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_19" "0,1" newline bitfld.long 0x34 18. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_18" "0,1" newline bitfld.long 0x34 17. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_17" "0,1" newline bitfld.long 0x34 16. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_16" "0,1" newline bitfld.long 0x34 15. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_15" "0,1" newline bitfld.long 0x34 14. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_14" "0,1" newline bitfld.long 0x34 13. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_13" "0,1" newline bitfld.long 0x34 12. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_12" "0,1" newline bitfld.long 0x34 11. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_11" "0,1" newline bitfld.long 0x34 10. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_10" "0,1" newline bitfld.long 0x34 9. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_9" "0,1" newline bitfld.long 0x34 8. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_8" "0,1" newline bitfld.long 0x34 7. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_7" "0,1" newline bitfld.long 0x34 6. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_6" "0,1" newline bitfld.long 0x34 5. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_5" "0,1" newline bitfld.long 0x34 4. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_4" "0,1" newline bitfld.long 0x34 3. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_3" "0,1" newline bitfld.long 0x34 2. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_2" "0,1" newline bitfld.long 0x34 1. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_1" "0,1" newline bitfld.long 0x34 0. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_0" "0,1" line.long 0x38 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_1_6,Status Clear Register 14" bitfld.long 0x38 31. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_63_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_63" "0,1" newline bitfld.long 0x38 30. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_62_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_62" "0,1" newline bitfld.long 0x38 29. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_61_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_61" "0,1" newline bitfld.long 0x38 28. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_60_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_60" "0,1" newline bitfld.long 0x38 27. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_59_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_59" "0,1" newline bitfld.long 0x38 26. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_58_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_58" "0,1" newline bitfld.long 0x38 25. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_57_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_57" "0,1" newline bitfld.long 0x38 24. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_56_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_56" "0,1" newline bitfld.long 0x38 23. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_55_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_55" "0,1" newline bitfld.long 0x38 22. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_54_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_54" "0,1" newline bitfld.long 0x38 21. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_53_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_53" "0,1" newline bitfld.long 0x38 20. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_52_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_52" "0,1" newline bitfld.long 0x38 19. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_51_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_51" "0,1" newline bitfld.long 0x38 18. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_50_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_50" "0,1" newline bitfld.long 0x38 17. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_49_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_49" "0,1" newline bitfld.long 0x38 16. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_48_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_48" "0,1" newline bitfld.long 0x38 15. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_47_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_47" "0,1" newline bitfld.long 0x38 14. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_46_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_46" "0,1" newline bitfld.long 0x38 13. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_45_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_45" "0,1" newline bitfld.long 0x38 12. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_44_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_44" "0,1" newline bitfld.long 0x38 11. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_43_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_43" "0,1" newline bitfld.long 0x38 10. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_42_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_42" "0,1" newline bitfld.long 0x38 9. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_41_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_41" "0,1" newline bitfld.long 0x38 8. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_40_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_40" "0,1" newline bitfld.long 0x38 7. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_39_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_39" "0,1" newline bitfld.long 0x38 6. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_38_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_38" "0,1" newline bitfld.long 0x38 5. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_37_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_37" "0,1" newline bitfld.long 0x38 4. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_36_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_36" "0,1" newline bitfld.long 0x38 3. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_35_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_35" "0,1" newline bitfld.long 0x38 2. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_34_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_34" "0,1" newline bitfld.long 0x38 1. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_33_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_33" "0,1" newline bitfld.long 0x38 0. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_32_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_32" "0,1" line.long 0x3C "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_1_7,Status Clear Register 15" bitfld.long 0x3C 4. "STATUS_LEVEL_VPAC_OUT_1_CTM_PULSE_CLR,Status write 1 to clear for level_vpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0x3C 3. "STATUS_LEVEL_VPAC_OUT_1_UTC1_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_prot_err" "0,1" newline bitfld.long 0x3C 2. "STATUS_LEVEL_VPAC_OUT_1_UTC0_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_prot_err" "0,1" newline bitfld.long 0x3C 1. "STATUS_LEVEL_VPAC_OUT_1_UTC1_ERROR_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_error" "0,1" newline bitfld.long 0x3C 0. "STATUS_LEVEL_VPAC_OUT_1_UTC0_ERROR_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_error" "0,1" line.long 0x40 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_2_0,Status Clear Register 16" bitfld.long 0x40 26. "STATUS_LEVEL_VPAC_OUT_2_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x40 25. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x40 24. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x40 23. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x40 22. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x40 21. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x40 20. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x40 19. "STATUS_LEVEL_VPAC_OUT_2_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x40 18. "STATUS_LEVEL_VPAC_OUT_2_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x40 17. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x40 16. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x40 15. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x40 14. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x40 13. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x40 12. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x40 11. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x40 10. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x40 9. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x40 8. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x40 7. "STATUS_LEVEL_VPAC_OUT_2_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x40 6. "STATUS_LEVEL_VPAC_OUT_2_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x40 5. "STATUS_LEVEL_VPAC_OUT_2_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x40 4. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x40 3. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x40 2. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x40 1. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x40 0. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1" line.long 0x44 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_2_1,Status Clear Register 17" bitfld.long 0x44 8. "STATUS_LEVEL_VPAC_OUT_2_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x44 7. "STATUS_LEVEL_VPAC_OUT_2_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x44 6. "STATUS_LEVEL_VPAC_OUT_2_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x44 5. "STATUS_LEVEL_VPAC_OUT_2_LDC0_INT_SZOVF_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x44 4. "STATUS_LEVEL_VPAC_OUT_2_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x44 3. "STATUS_LEVEL_VPAC_OUT_2_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x44 2. "STATUS_LEVEL_VPAC_OUT_2_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x44 1. "STATUS_LEVEL_VPAC_OUT_2_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x44 0. "STATUS_LEVEL_VPAC_OUT_2_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x48 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_2_2,Status Clear Register 18" bitfld.long 0x48 10. "STATUS_LEVEL_VPAC_OUT_2_NF_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x48 9. "STATUS_LEVEL_VPAC_OUT_2_NF_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x48 8. "STATUS_LEVEL_VPAC_OUT_2_NF_FRAME_DONE_CLR,Status write 1 to clear for level_vpac_out_2_en_nf_frame_done" "0,1" newline bitfld.long 0x48 3. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x48 2. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x48 1. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for level_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x48 0. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for level_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x4C "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_2_3,Status Clear Register 19" bitfld.long 0x4C 26. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for level_vpac_out_2_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x4C 25. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for level_vpac_out_2_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x4C 24. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for level_vpac_out_2_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x4C 22. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for level_vpac_out_2_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x4C 20. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_vpac_out_2_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x4C 15. "STATUS_LEVEL_VPAC_OUT_2_SPARE_DEC_1_CLR,Status write 1 to clear for level_vpac_out_2_en_spare_dec_1" "0,1" newline bitfld.long 0x4C 14. "STATUS_LEVEL_VPAC_OUT_2_SPARE_DEC_0_CLR,Status write 1 to clear for level_vpac_out_2_en_spare_dec_0" "0,1" newline bitfld.long 0x4C 13. "STATUS_LEVEL_VPAC_OUT_2_TDONE_6_CLR,Status write 1 to clear for level_vpac_out_2_en_tdone_6" "0,1" newline bitfld.long 0x4C 12. "STATUS_LEVEL_VPAC_OUT_2_TDONE_5_CLR,Status write 1 to clear for level_vpac_out_2_en_tdone_5" "0,1" newline bitfld.long 0x4C 11. "STATUS_LEVEL_VPAC_OUT_2_TDONE_4_CLR,Status write 1 to clear for level_vpac_out_2_en_tdone_4" "0,1" newline bitfld.long 0x4C 9. "STATUS_LEVEL_VPAC_OUT_2_TDONE_2_CLR,Status write 1 to clear for level_vpac_out_2_en_tdone_2" "0,1" newline bitfld.long 0x4C 7. "STATUS_LEVEL_VPAC_OUT_2_TDONE_0_CLR,Status write 1 to clear for level_vpac_out_2_en_tdone_0" "0,1" newline bitfld.long 0x4C 6. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_6_CLR,Status write 1 to clear for level_vpac_out_2_en_pipe_done_6" "0,1" newline bitfld.long 0x4C 5. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_5_CLR,Status write 1 to clear for level_vpac_out_2_en_pipe_done_5" "0,1" newline bitfld.long 0x4C 4. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_4_CLR,Status write 1 to clear for level_vpac_out_2_en_pipe_done_4" "0,1" newline bitfld.long 0x4C 3. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_3_CLR,Status write 1 to clear for level_vpac_out_2_en_pipe_done_3" "0,1" newline bitfld.long 0x4C 2. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_2_CLR,Status write 1 to clear for level_vpac_out_2_en_pipe_done_2" "0,1" newline bitfld.long 0x4C 1. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_1_CLR,Status write 1 to clear for level_vpac_out_2_en_pipe_done_1" "0,1" newline bitfld.long 0x4C 0. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_0_CLR,Status write 1 to clear for level_vpac_out_2_en_pipe_done_0" "0,1" line.long 0x50 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_2_4,Status Clear Register 20" bitfld.long 0x50 31. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_31" "0,1" newline bitfld.long 0x50 30. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_30" "0,1" newline bitfld.long 0x50 29. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_29" "0,1" newline bitfld.long 0x50 28. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_28" "0,1" newline bitfld.long 0x50 27. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_27" "0,1" newline bitfld.long 0x50 26. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_26" "0,1" newline bitfld.long 0x50 25. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_25" "0,1" newline bitfld.long 0x50 24. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_24" "0,1" newline bitfld.long 0x50 23. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_23" "0,1" newline bitfld.long 0x50 22. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_22" "0,1" newline bitfld.long 0x50 21. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_21" "0,1" newline bitfld.long 0x50 20. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_20" "0,1" newline bitfld.long 0x50 19. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_19" "0,1" newline bitfld.long 0x50 18. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_18" "0,1" newline bitfld.long 0x50 17. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_17" "0,1" newline bitfld.long 0x50 16. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_16" "0,1" newline bitfld.long 0x50 15. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_15" "0,1" newline bitfld.long 0x50 14. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_14" "0,1" newline bitfld.long 0x50 13. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_13" "0,1" newline bitfld.long 0x50 12. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_12" "0,1" newline bitfld.long 0x50 11. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_11" "0,1" newline bitfld.long 0x50 10. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_10" "0,1" newline bitfld.long 0x50 9. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_9" "0,1" newline bitfld.long 0x50 8. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_8" "0,1" newline bitfld.long 0x50 7. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_7" "0,1" newline bitfld.long 0x50 6. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_6" "0,1" newline bitfld.long 0x50 5. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_5" "0,1" newline bitfld.long 0x50 4. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_4" "0,1" newline bitfld.long 0x50 3. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_3" "0,1" newline bitfld.long 0x50 2. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_2" "0,1" newline bitfld.long 0x50 1. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_1" "0,1" newline bitfld.long 0x50 0. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_0" "0,1" line.long 0x54 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_2_5,Status Clear Register 21" bitfld.long 0x54 31. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_31" "0,1" newline bitfld.long 0x54 30. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_30" "0,1" newline bitfld.long 0x54 29. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_29" "0,1" newline bitfld.long 0x54 28. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_28" "0,1" newline bitfld.long 0x54 27. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_27" "0,1" newline bitfld.long 0x54 26. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_26" "0,1" newline bitfld.long 0x54 25. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_25" "0,1" newline bitfld.long 0x54 24. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_24" "0,1" newline bitfld.long 0x54 23. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_23" "0,1" newline bitfld.long 0x54 22. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_22" "0,1" newline bitfld.long 0x54 21. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_21" "0,1" newline bitfld.long 0x54 20. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_20" "0,1" newline bitfld.long 0x54 19. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_19" "0,1" newline bitfld.long 0x54 18. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_18" "0,1" newline bitfld.long 0x54 17. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_17" "0,1" newline bitfld.long 0x54 16. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_16" "0,1" newline bitfld.long 0x54 15. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_15" "0,1" newline bitfld.long 0x54 14. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_14" "0,1" newline bitfld.long 0x54 13. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_13" "0,1" newline bitfld.long 0x54 12. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_12" "0,1" newline bitfld.long 0x54 11. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_11" "0,1" newline bitfld.long 0x54 10. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_10" "0,1" newline bitfld.long 0x54 9. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_9" "0,1" newline bitfld.long 0x54 8. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_8" "0,1" newline bitfld.long 0x54 7. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_7" "0,1" newline bitfld.long 0x54 6. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_6" "0,1" newline bitfld.long 0x54 5. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_5" "0,1" newline bitfld.long 0x54 4. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_4" "0,1" newline bitfld.long 0x54 3. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_3" "0,1" newline bitfld.long 0x54 2. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_2" "0,1" newline bitfld.long 0x54 1. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_1" "0,1" newline bitfld.long 0x54 0. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_0" "0,1" line.long 0x58 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_2_6,Status Clear Register 22" bitfld.long 0x58 31. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_63_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_63" "0,1" newline bitfld.long 0x58 30. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_62_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_62" "0,1" newline bitfld.long 0x58 29. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_61_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_61" "0,1" newline bitfld.long 0x58 28. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_60_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_60" "0,1" newline bitfld.long 0x58 27. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_59_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_59" "0,1" newline bitfld.long 0x58 26. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_58_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_58" "0,1" newline bitfld.long 0x58 25. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_57_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_57" "0,1" newline bitfld.long 0x58 24. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_56_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_56" "0,1" newline bitfld.long 0x58 23. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_55_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_55" "0,1" newline bitfld.long 0x58 22. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_54_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_54" "0,1" newline bitfld.long 0x58 21. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_53_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_53" "0,1" newline bitfld.long 0x58 20. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_52_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_52" "0,1" newline bitfld.long 0x58 19. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_51_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_51" "0,1" newline bitfld.long 0x58 18. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_50_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_50" "0,1" newline bitfld.long 0x58 17. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_49_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_49" "0,1" newline bitfld.long 0x58 16. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_48_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_48" "0,1" newline bitfld.long 0x58 15. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_47_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_47" "0,1" newline bitfld.long 0x58 14. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_46_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_46" "0,1" newline bitfld.long 0x58 13. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_45_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_45" "0,1" newline bitfld.long 0x58 12. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_44_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_44" "0,1" newline bitfld.long 0x58 11. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_43_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_43" "0,1" newline bitfld.long 0x58 10. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_42_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_42" "0,1" newline bitfld.long 0x58 9. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_41_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_41" "0,1" newline bitfld.long 0x58 8. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_40_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_40" "0,1" newline bitfld.long 0x58 7. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_39_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_39" "0,1" newline bitfld.long 0x58 6. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_38_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_38" "0,1" newline bitfld.long 0x58 5. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_37_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_37" "0,1" newline bitfld.long 0x58 4. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_36_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_36" "0,1" newline bitfld.long 0x58 3. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_35_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_35" "0,1" newline bitfld.long 0x58 2. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_34_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_34" "0,1" newline bitfld.long 0x58 1. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_33_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_33" "0,1" newline bitfld.long 0x58 0. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_32_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_32" "0,1" line.long 0x5C "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_2_7,Status Clear Register 23" bitfld.long 0x5C 4. "STATUS_LEVEL_VPAC_OUT_2_CTM_PULSE_CLR,Status write 1 to clear for level_vpac_out_2_en_ctm_pulse" "0,1" newline bitfld.long 0x5C 3. "STATUS_LEVEL_VPAC_OUT_2_UTC1_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_prot_err" "0,1" newline bitfld.long 0x5C 2. "STATUS_LEVEL_VPAC_OUT_2_UTC0_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_prot_err" "0,1" newline bitfld.long 0x5C 1. "STATUS_LEVEL_VPAC_OUT_2_UTC1_ERROR_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_error" "0,1" newline bitfld.long 0x5C 0. "STATUS_LEVEL_VPAC_OUT_2_UTC0_ERROR_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_error" "0,1" line.long 0x60 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_3_0,Status Clear Register 24" bitfld.long 0x60 26. "STATUS_LEVEL_VPAC_OUT_3_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x60 25. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x60 24. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x60 23. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x60 22. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x60 21. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x60 20. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x60 19. "STATUS_LEVEL_VPAC_OUT_3_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x60 18. "STATUS_LEVEL_VPAC_OUT_3_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x60 17. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x60 16. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x60 15. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x60 14. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x60 13. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x60 12. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x60 11. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x60 10. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x60 9. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x60 8. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x60 7. "STATUS_LEVEL_VPAC_OUT_3_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x60 6. "STATUS_LEVEL_VPAC_OUT_3_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x60 5. "STATUS_LEVEL_VPAC_OUT_3_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x60 4. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x60 3. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x60 2. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x60 1. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x60 0. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1" line.long 0x64 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_3_1,Status Clear Register 25" bitfld.long 0x64 8. "STATUS_LEVEL_VPAC_OUT_3_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x64 7. "STATUS_LEVEL_VPAC_OUT_3_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x64 6. "STATUS_LEVEL_VPAC_OUT_3_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x64 5. "STATUS_LEVEL_VPAC_OUT_3_LDC0_INT_SZOVF_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x64 4. "STATUS_LEVEL_VPAC_OUT_3_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x64 3. "STATUS_LEVEL_VPAC_OUT_3_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x64 2. "STATUS_LEVEL_VPAC_OUT_3_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x64 1. "STATUS_LEVEL_VPAC_OUT_3_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x64 0. "STATUS_LEVEL_VPAC_OUT_3_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x68 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_3_2,Status Clear Register 26" bitfld.long 0x68 10. "STATUS_LEVEL_VPAC_OUT_3_NF_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x68 9. "STATUS_LEVEL_VPAC_OUT_3_NF_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x68 8. "STATUS_LEVEL_VPAC_OUT_3_NF_FRAME_DONE_CLR,Status write 1 to clear for level_vpac_out_3_en_nf_frame_done" "0,1" newline bitfld.long 0x68 3. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x68 2. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x68 1. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for level_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x68 0. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for level_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x6C "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_3_3,Status Clear Register 27" bitfld.long 0x6C 26. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for level_vpac_out_3_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x6C 25. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for level_vpac_out_3_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x6C 24. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for level_vpac_out_3_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x6C 22. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for level_vpac_out_3_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x6C 20. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_vpac_out_3_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x6C 15. "STATUS_LEVEL_VPAC_OUT_3_SPARE_DEC_1_CLR,Status write 1 to clear for level_vpac_out_3_en_spare_dec_1" "0,1" newline bitfld.long 0x6C 14. "STATUS_LEVEL_VPAC_OUT_3_SPARE_DEC_0_CLR,Status write 1 to clear for level_vpac_out_3_en_spare_dec_0" "0,1" newline bitfld.long 0x6C 13. "STATUS_LEVEL_VPAC_OUT_3_TDONE_6_CLR,Status write 1 to clear for level_vpac_out_3_en_tdone_6" "0,1" newline bitfld.long 0x6C 12. "STATUS_LEVEL_VPAC_OUT_3_TDONE_5_CLR,Status write 1 to clear for level_vpac_out_3_en_tdone_5" "0,1" newline bitfld.long 0x6C 11. "STATUS_LEVEL_VPAC_OUT_3_TDONE_4_CLR,Status write 1 to clear for level_vpac_out_3_en_tdone_4" "0,1" newline bitfld.long 0x6C 9. "STATUS_LEVEL_VPAC_OUT_3_TDONE_2_CLR,Status write 1 to clear for level_vpac_out_3_en_tdone_2" "0,1" newline bitfld.long 0x6C 7. "STATUS_LEVEL_VPAC_OUT_3_TDONE_0_CLR,Status write 1 to clear for level_vpac_out_3_en_tdone_0" "0,1" newline bitfld.long 0x6C 6. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_6_CLR,Status write 1 to clear for level_vpac_out_3_en_pipe_done_6" "0,1" newline bitfld.long 0x6C 5. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_5_CLR,Status write 1 to clear for level_vpac_out_3_en_pipe_done_5" "0,1" newline bitfld.long 0x6C 4. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_4_CLR,Status write 1 to clear for level_vpac_out_3_en_pipe_done_4" "0,1" newline bitfld.long 0x6C 3. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_3_CLR,Status write 1 to clear for level_vpac_out_3_en_pipe_done_3" "0,1" newline bitfld.long 0x6C 2. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_2_CLR,Status write 1 to clear for level_vpac_out_3_en_pipe_done_2" "0,1" newline bitfld.long 0x6C 1. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_1_CLR,Status write 1 to clear for level_vpac_out_3_en_pipe_done_1" "0,1" newline bitfld.long 0x6C 0. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_0_CLR,Status write 1 to clear for level_vpac_out_3_en_pipe_done_0" "0,1" line.long 0x70 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_3_4,Status Clear Register 28" bitfld.long 0x70 31. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_31" "0,1" newline bitfld.long 0x70 30. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_30" "0,1" newline bitfld.long 0x70 29. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_29" "0,1" newline bitfld.long 0x70 28. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_28" "0,1" newline bitfld.long 0x70 27. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_27" "0,1" newline bitfld.long 0x70 26. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_26" "0,1" newline bitfld.long 0x70 25. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_25" "0,1" newline bitfld.long 0x70 24. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_24" "0,1" newline bitfld.long 0x70 23. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_23" "0,1" newline bitfld.long 0x70 22. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_22" "0,1" newline bitfld.long 0x70 21. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_21" "0,1" newline bitfld.long 0x70 20. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_20" "0,1" newline bitfld.long 0x70 19. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_19" "0,1" newline bitfld.long 0x70 18. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_18" "0,1" newline bitfld.long 0x70 17. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_17" "0,1" newline bitfld.long 0x70 16. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_16" "0,1" newline bitfld.long 0x70 15. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_15" "0,1" newline bitfld.long 0x70 14. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_14" "0,1" newline bitfld.long 0x70 13. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_13" "0,1" newline bitfld.long 0x70 12. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_12" "0,1" newline bitfld.long 0x70 11. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_11" "0,1" newline bitfld.long 0x70 10. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_10" "0,1" newline bitfld.long 0x70 9. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_9" "0,1" newline bitfld.long 0x70 8. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_8" "0,1" newline bitfld.long 0x70 7. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_7" "0,1" newline bitfld.long 0x70 6. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_6" "0,1" newline bitfld.long 0x70 5. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_5" "0,1" newline bitfld.long 0x70 4. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_4" "0,1" newline bitfld.long 0x70 3. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_3" "0,1" newline bitfld.long 0x70 2. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_2" "0,1" newline bitfld.long 0x70 1. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_1" "0,1" newline bitfld.long 0x70 0. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_0" "0,1" line.long 0x74 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_3_5,Status Clear Register 29" bitfld.long 0x74 31. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_31" "0,1" newline bitfld.long 0x74 30. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_30" "0,1" newline bitfld.long 0x74 29. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_29" "0,1" newline bitfld.long 0x74 28. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_28" "0,1" newline bitfld.long 0x74 27. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_27" "0,1" newline bitfld.long 0x74 26. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_26" "0,1" newline bitfld.long 0x74 25. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_25" "0,1" newline bitfld.long 0x74 24. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_24" "0,1" newline bitfld.long 0x74 23. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_23" "0,1" newline bitfld.long 0x74 22. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_22" "0,1" newline bitfld.long 0x74 21. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_21" "0,1" newline bitfld.long 0x74 20. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_20" "0,1" newline bitfld.long 0x74 19. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_19" "0,1" newline bitfld.long 0x74 18. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_18" "0,1" newline bitfld.long 0x74 17. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_17" "0,1" newline bitfld.long 0x74 16. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_16" "0,1" newline bitfld.long 0x74 15. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_15" "0,1" newline bitfld.long 0x74 14. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_14" "0,1" newline bitfld.long 0x74 13. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_13" "0,1" newline bitfld.long 0x74 12. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_12" "0,1" newline bitfld.long 0x74 11. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_11" "0,1" newline bitfld.long 0x74 10. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_10" "0,1" newline bitfld.long 0x74 9. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_9" "0,1" newline bitfld.long 0x74 8. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_8" "0,1" newline bitfld.long 0x74 7. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_7" "0,1" newline bitfld.long 0x74 6. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_6" "0,1" newline bitfld.long 0x74 5. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_5" "0,1" newline bitfld.long 0x74 4. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_4" "0,1" newline bitfld.long 0x74 3. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_3" "0,1" newline bitfld.long 0x74 2. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_2" "0,1" newline bitfld.long 0x74 1. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_1" "0,1" newline bitfld.long 0x74 0. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_0" "0,1" line.long 0x78 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_3_6,Status Clear Register 30" bitfld.long 0x78 31. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_63_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_63" "0,1" newline bitfld.long 0x78 30. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_62_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_62" "0,1" newline bitfld.long 0x78 29. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_61_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_61" "0,1" newline bitfld.long 0x78 28. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_60_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_60" "0,1" newline bitfld.long 0x78 27. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_59_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_59" "0,1" newline bitfld.long 0x78 26. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_58_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_58" "0,1" newline bitfld.long 0x78 25. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_57_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_57" "0,1" newline bitfld.long 0x78 24. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_56_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_56" "0,1" newline bitfld.long 0x78 23. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_55_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_55" "0,1" newline bitfld.long 0x78 22. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_54_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_54" "0,1" newline bitfld.long 0x78 21. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_53_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_53" "0,1" newline bitfld.long 0x78 20. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_52_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_52" "0,1" newline bitfld.long 0x78 19. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_51_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_51" "0,1" newline bitfld.long 0x78 18. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_50_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_50" "0,1" newline bitfld.long 0x78 17. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_49_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_49" "0,1" newline bitfld.long 0x78 16. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_48_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_48" "0,1" newline bitfld.long 0x78 15. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_47_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_47" "0,1" newline bitfld.long 0x78 14. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_46_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_46" "0,1" newline bitfld.long 0x78 13. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_45_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_45" "0,1" newline bitfld.long 0x78 12. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_44_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_44" "0,1" newline bitfld.long 0x78 11. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_43_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_43" "0,1" newline bitfld.long 0x78 10. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_42_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_42" "0,1" newline bitfld.long 0x78 9. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_41_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_41" "0,1" newline bitfld.long 0x78 8. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_40_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_40" "0,1" newline bitfld.long 0x78 7. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_39_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_39" "0,1" newline bitfld.long 0x78 6. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_38_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_38" "0,1" newline bitfld.long 0x78 5. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_37_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_37" "0,1" newline bitfld.long 0x78 4. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_36_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_36" "0,1" newline bitfld.long 0x78 3. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_35_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_35" "0,1" newline bitfld.long 0x78 2. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_34_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_34" "0,1" newline bitfld.long 0x78 1. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_33_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_33" "0,1" newline bitfld.long 0x78 0. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_32_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_32" "0,1" line.long 0x7C "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_3_7,Status Clear Register 31" bitfld.long 0x7C 4. "STATUS_LEVEL_VPAC_OUT_3_CTM_PULSE_CLR,Status write 1 to clear for level_vpac_out_3_en_ctm_pulse" "0,1" newline bitfld.long 0x7C 3. "STATUS_LEVEL_VPAC_OUT_3_UTC1_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_prot_err" "0,1" newline bitfld.long 0x7C 2. "STATUS_LEVEL_VPAC_OUT_3_UTC0_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_prot_err" "0,1" newline bitfld.long 0x7C 1. "STATUS_LEVEL_VPAC_OUT_3_UTC1_ERROR_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_error" "0,1" newline bitfld.long 0x7C 0. "STATUS_LEVEL_VPAC_OUT_3_UTC0_ERROR_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_error" "0,1" line.long 0x80 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_4_0,Status Clear Register 32" bitfld.long 0x80 26. "STATUS_LEVEL_VPAC_OUT_4_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x80 25. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x80 24. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x80 23. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x80 22. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x80 21. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x80 20. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x80 19. "STATUS_LEVEL_VPAC_OUT_4_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x80 18. "STATUS_LEVEL_VPAC_OUT_4_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x80 17. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x80 16. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x80 15. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x80 14. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x80 13. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x80 12. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x80 11. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x80 10. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x80 9. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x80 8. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x80 7. "STATUS_LEVEL_VPAC_OUT_4_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x80 6. "STATUS_LEVEL_VPAC_OUT_4_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x80 5. "STATUS_LEVEL_VPAC_OUT_4_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x80 4. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x80 3. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x80 2. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x80 1. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x80 0. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1" line.long 0x84 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_4_1,Status Clear Register 33" bitfld.long 0x84 8. "STATUS_LEVEL_VPAC_OUT_4_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x84 7. "STATUS_LEVEL_VPAC_OUT_4_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x84 6. "STATUS_LEVEL_VPAC_OUT_4_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x84 5. "STATUS_LEVEL_VPAC_OUT_4_LDC0_INT_SZOVF_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x84 4. "STATUS_LEVEL_VPAC_OUT_4_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x84 3. "STATUS_LEVEL_VPAC_OUT_4_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x84 2. "STATUS_LEVEL_VPAC_OUT_4_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x84 1. "STATUS_LEVEL_VPAC_OUT_4_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x84 0. "STATUS_LEVEL_VPAC_OUT_4_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x88 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_4_2,Status Clear Register 34" bitfld.long 0x88 10. "STATUS_LEVEL_VPAC_OUT_4_NF_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x88 9. "STATUS_LEVEL_VPAC_OUT_4_NF_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x88 8. "STATUS_LEVEL_VPAC_OUT_4_NF_FRAME_DONE_CLR,Status write 1 to clear for level_vpac_out_4_en_nf_frame_done" "0,1" newline bitfld.long 0x88 3. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x88 2. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x88 1. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for level_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x88 0. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for level_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x8C "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_4_3,Status Clear Register 35" bitfld.long 0x8C 26. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for level_vpac_out_4_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x8C 25. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for level_vpac_out_4_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x8C 24. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for level_vpac_out_4_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x8C 22. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for level_vpac_out_4_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x8C 20. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_vpac_out_4_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x8C 15. "STATUS_LEVEL_VPAC_OUT_4_SPARE_DEC_1_CLR,Status write 1 to clear for level_vpac_out_4_en_spare_dec_1" "0,1" newline bitfld.long 0x8C 14. "STATUS_LEVEL_VPAC_OUT_4_SPARE_DEC_0_CLR,Status write 1 to clear for level_vpac_out_4_en_spare_dec_0" "0,1" newline bitfld.long 0x8C 13. "STATUS_LEVEL_VPAC_OUT_4_TDONE_6_CLR,Status write 1 to clear for level_vpac_out_4_en_tdone_6" "0,1" newline bitfld.long 0x8C 12. "STATUS_LEVEL_VPAC_OUT_4_TDONE_5_CLR,Status write 1 to clear for level_vpac_out_4_en_tdone_5" "0,1" newline bitfld.long 0x8C 11. "STATUS_LEVEL_VPAC_OUT_4_TDONE_4_CLR,Status write 1 to clear for level_vpac_out_4_en_tdone_4" "0,1" newline bitfld.long 0x8C 9. "STATUS_LEVEL_VPAC_OUT_4_TDONE_2_CLR,Status write 1 to clear for level_vpac_out_4_en_tdone_2" "0,1" newline bitfld.long 0x8C 7. "STATUS_LEVEL_VPAC_OUT_4_TDONE_0_CLR,Status write 1 to clear for level_vpac_out_4_en_tdone_0" "0,1" newline bitfld.long 0x8C 6. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_6_CLR,Status write 1 to clear for level_vpac_out_4_en_pipe_done_6" "0,1" newline bitfld.long 0x8C 5. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_5_CLR,Status write 1 to clear for level_vpac_out_4_en_pipe_done_5" "0,1" newline bitfld.long 0x8C 4. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_4_CLR,Status write 1 to clear for level_vpac_out_4_en_pipe_done_4" "0,1" newline bitfld.long 0x8C 3. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_3_CLR,Status write 1 to clear for level_vpac_out_4_en_pipe_done_3" "0,1" newline bitfld.long 0x8C 2. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_2_CLR,Status write 1 to clear for level_vpac_out_4_en_pipe_done_2" "0,1" newline bitfld.long 0x8C 1. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_1_CLR,Status write 1 to clear for level_vpac_out_4_en_pipe_done_1" "0,1" newline bitfld.long 0x8C 0. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_0_CLR,Status write 1 to clear for level_vpac_out_4_en_pipe_done_0" "0,1" line.long 0x90 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_4_4,Status Clear Register 36" bitfld.long 0x90 31. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_31" "0,1" newline bitfld.long 0x90 30. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_30" "0,1" newline bitfld.long 0x90 29. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_29" "0,1" newline bitfld.long 0x90 28. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_28" "0,1" newline bitfld.long 0x90 27. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_27" "0,1" newline bitfld.long 0x90 26. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_26" "0,1" newline bitfld.long 0x90 25. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_25" "0,1" newline bitfld.long 0x90 24. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_24" "0,1" newline bitfld.long 0x90 23. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_23" "0,1" newline bitfld.long 0x90 22. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_22" "0,1" newline bitfld.long 0x90 21. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_21" "0,1" newline bitfld.long 0x90 20. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_20" "0,1" newline bitfld.long 0x90 19. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_19" "0,1" newline bitfld.long 0x90 18. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_18" "0,1" newline bitfld.long 0x90 17. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_17" "0,1" newline bitfld.long 0x90 16. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_16" "0,1" newline bitfld.long 0x90 15. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_15" "0,1" newline bitfld.long 0x90 14. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_14" "0,1" newline bitfld.long 0x90 13. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_13" "0,1" newline bitfld.long 0x90 12. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_12" "0,1" newline bitfld.long 0x90 11. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_11" "0,1" newline bitfld.long 0x90 10. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_10" "0,1" newline bitfld.long 0x90 9. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_9" "0,1" newline bitfld.long 0x90 8. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_8" "0,1" newline bitfld.long 0x90 7. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_7" "0,1" newline bitfld.long 0x90 6. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_6" "0,1" newline bitfld.long 0x90 5. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_5" "0,1" newline bitfld.long 0x90 4. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_4" "0,1" newline bitfld.long 0x90 3. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_3" "0,1" newline bitfld.long 0x90 2. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_2" "0,1" newline bitfld.long 0x90 1. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_1" "0,1" newline bitfld.long 0x90 0. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_0" "0,1" line.long 0x94 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_4_5,Status Clear Register 37" bitfld.long 0x94 31. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_31" "0,1" newline bitfld.long 0x94 30. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_30" "0,1" newline bitfld.long 0x94 29. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_29" "0,1" newline bitfld.long 0x94 28. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_28" "0,1" newline bitfld.long 0x94 27. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_27" "0,1" newline bitfld.long 0x94 26. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_26" "0,1" newline bitfld.long 0x94 25. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_25" "0,1" newline bitfld.long 0x94 24. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_24" "0,1" newline bitfld.long 0x94 23. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_23" "0,1" newline bitfld.long 0x94 22. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_22" "0,1" newline bitfld.long 0x94 21. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_21" "0,1" newline bitfld.long 0x94 20. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_20" "0,1" newline bitfld.long 0x94 19. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_19" "0,1" newline bitfld.long 0x94 18. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_18" "0,1" newline bitfld.long 0x94 17. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_17" "0,1" newline bitfld.long 0x94 16. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_16" "0,1" newline bitfld.long 0x94 15. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_15" "0,1" newline bitfld.long 0x94 14. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_14" "0,1" newline bitfld.long 0x94 13. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_13" "0,1" newline bitfld.long 0x94 12. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_12" "0,1" newline bitfld.long 0x94 11. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_11" "0,1" newline bitfld.long 0x94 10. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_10" "0,1" newline bitfld.long 0x94 9. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_9" "0,1" newline bitfld.long 0x94 8. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_8" "0,1" newline bitfld.long 0x94 7. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_7" "0,1" newline bitfld.long 0x94 6. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_6" "0,1" newline bitfld.long 0x94 5. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_5" "0,1" newline bitfld.long 0x94 4. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_4" "0,1" newline bitfld.long 0x94 3. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_3" "0,1" newline bitfld.long 0x94 2. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_2" "0,1" newline bitfld.long 0x94 1. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_1" "0,1" newline bitfld.long 0x94 0. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_0" "0,1" line.long 0x98 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_4_6,Status Clear Register 38" bitfld.long 0x98 31. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_63_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_63" "0,1" newline bitfld.long 0x98 30. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_62_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_62" "0,1" newline bitfld.long 0x98 29. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_61_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_61" "0,1" newline bitfld.long 0x98 28. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_60_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_60" "0,1" newline bitfld.long 0x98 27. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_59_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_59" "0,1" newline bitfld.long 0x98 26. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_58_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_58" "0,1" newline bitfld.long 0x98 25. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_57_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_57" "0,1" newline bitfld.long 0x98 24. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_56_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_56" "0,1" newline bitfld.long 0x98 23. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_55_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_55" "0,1" newline bitfld.long 0x98 22. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_54_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_54" "0,1" newline bitfld.long 0x98 21. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_53_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_53" "0,1" newline bitfld.long 0x98 20. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_52_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_52" "0,1" newline bitfld.long 0x98 19. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_51_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_51" "0,1" newline bitfld.long 0x98 18. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_50_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_50" "0,1" newline bitfld.long 0x98 17. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_49_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_49" "0,1" newline bitfld.long 0x98 16. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_48_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_48" "0,1" newline bitfld.long 0x98 15. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_47_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_47" "0,1" newline bitfld.long 0x98 14. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_46_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_46" "0,1" newline bitfld.long 0x98 13. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_45_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_45" "0,1" newline bitfld.long 0x98 12. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_44_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_44" "0,1" newline bitfld.long 0x98 11. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_43_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_43" "0,1" newline bitfld.long 0x98 10. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_42_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_42" "0,1" newline bitfld.long 0x98 9. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_41_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_41" "0,1" newline bitfld.long 0x98 8. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_40_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_40" "0,1" newline bitfld.long 0x98 7. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_39_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_39" "0,1" newline bitfld.long 0x98 6. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_38_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_38" "0,1" newline bitfld.long 0x98 5. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_37_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_37" "0,1" newline bitfld.long 0x98 4. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_36_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_36" "0,1" newline bitfld.long 0x98 3. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_35_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_35" "0,1" newline bitfld.long 0x98 2. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_34_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_34" "0,1" newline bitfld.long 0x98 1. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_33_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_33" "0,1" newline bitfld.long 0x98 0. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_32_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_32" "0,1" line.long 0x9C "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_4_7,Status Clear Register 39" bitfld.long 0x9C 4. "STATUS_LEVEL_VPAC_OUT_4_CTM_PULSE_CLR,Status write 1 to clear for level_vpac_out_4_en_ctm_pulse" "0,1" newline bitfld.long 0x9C 3. "STATUS_LEVEL_VPAC_OUT_4_UTC1_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_prot_err" "0,1" newline bitfld.long 0x9C 2. "STATUS_LEVEL_VPAC_OUT_4_UTC0_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_prot_err" "0,1" newline bitfld.long 0x9C 1. "STATUS_LEVEL_VPAC_OUT_4_UTC1_ERROR_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_error" "0,1" newline bitfld.long 0x9C 0. "STATUS_LEVEL_VPAC_OUT_4_UTC0_ERROR_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_error" "0,1" line.long 0xA0 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_5_0,Status Clear Register 40" bitfld.long 0xA0 26. "STATUS_LEVEL_VPAC_OUT_5_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xA0 25. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xA0 24. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xA0 23. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xA0 22. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xA0 21. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xA0 20. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xA0 19. "STATUS_LEVEL_VPAC_OUT_5_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xA0 18. "STATUS_LEVEL_VPAC_OUT_5_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xA0 17. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xA0 16. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xA0 15. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xA0 14. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xA0 13. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xA0 12. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xA0 11. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xA0 10. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xA0 9. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xA0 8. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xA0 7. "STATUS_LEVEL_VPAC_OUT_5_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xA0 6. "STATUS_LEVEL_VPAC_OUT_5_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xA0 5. "STATUS_LEVEL_VPAC_OUT_5_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xA0 4. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xA0 3. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xA0 2. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xA0 1. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xA0 0. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1" line.long 0xA4 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_5_1,Status Clear Register 41" bitfld.long 0xA4 8. "STATUS_LEVEL_VPAC_OUT_5_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xA4 7. "STATUS_LEVEL_VPAC_OUT_5_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xA4 6. "STATUS_LEVEL_VPAC_OUT_5_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xA4 5. "STATUS_LEVEL_VPAC_OUT_5_LDC0_INT_SZOVF_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xA4 4. "STATUS_LEVEL_VPAC_OUT_5_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xA4 3. "STATUS_LEVEL_VPAC_OUT_5_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xA4 2. "STATUS_LEVEL_VPAC_OUT_5_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xA4 1. "STATUS_LEVEL_VPAC_OUT_5_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xA4 0. "STATUS_LEVEL_VPAC_OUT_5_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xA8 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_5_2,Status Clear Register 42" bitfld.long 0xA8 10. "STATUS_LEVEL_VPAC_OUT_5_NF_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0xA8 9. "STATUS_LEVEL_VPAC_OUT_5_NF_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0xA8 8. "STATUS_LEVEL_VPAC_OUT_5_NF_FRAME_DONE_CLR,Status write 1 to clear for level_vpac_out_5_en_nf_frame_done" "0,1" newline bitfld.long 0xA8 3. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xA8 2. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xA8 1. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for level_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xA8 0. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for level_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xAC "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_5_3,Status Clear Register 43" bitfld.long 0xAC 26. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for level_vpac_out_5_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xAC 25. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for level_vpac_out_5_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xAC 24. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for level_vpac_out_5_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xAC 22. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for level_vpac_out_5_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xAC 20. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_vpac_out_5_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xAC 15. "STATUS_LEVEL_VPAC_OUT_5_SPARE_DEC_1_CLR,Status write 1 to clear for level_vpac_out_5_en_spare_dec_1" "0,1" newline bitfld.long 0xAC 14. "STATUS_LEVEL_VPAC_OUT_5_SPARE_DEC_0_CLR,Status write 1 to clear for level_vpac_out_5_en_spare_dec_0" "0,1" newline bitfld.long 0xAC 13. "STATUS_LEVEL_VPAC_OUT_5_TDONE_6_CLR,Status write 1 to clear for level_vpac_out_5_en_tdone_6" "0,1" newline bitfld.long 0xAC 12. "STATUS_LEVEL_VPAC_OUT_5_TDONE_5_CLR,Status write 1 to clear for level_vpac_out_5_en_tdone_5" "0,1" newline bitfld.long 0xAC 11. "STATUS_LEVEL_VPAC_OUT_5_TDONE_4_CLR,Status write 1 to clear for level_vpac_out_5_en_tdone_4" "0,1" newline bitfld.long 0xAC 9. "STATUS_LEVEL_VPAC_OUT_5_TDONE_2_CLR,Status write 1 to clear for level_vpac_out_5_en_tdone_2" "0,1" newline bitfld.long 0xAC 7. "STATUS_LEVEL_VPAC_OUT_5_TDONE_0_CLR,Status write 1 to clear for level_vpac_out_5_en_tdone_0" "0,1" newline bitfld.long 0xAC 6. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_6_CLR,Status write 1 to clear for level_vpac_out_5_en_pipe_done_6" "0,1" newline bitfld.long 0xAC 5. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_5_CLR,Status write 1 to clear for level_vpac_out_5_en_pipe_done_5" "0,1" newline bitfld.long 0xAC 4. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_4_CLR,Status write 1 to clear for level_vpac_out_5_en_pipe_done_4" "0,1" newline bitfld.long 0xAC 3. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_3_CLR,Status write 1 to clear for level_vpac_out_5_en_pipe_done_3" "0,1" newline bitfld.long 0xAC 2. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_2_CLR,Status write 1 to clear for level_vpac_out_5_en_pipe_done_2" "0,1" newline bitfld.long 0xAC 1. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_1_CLR,Status write 1 to clear for level_vpac_out_5_en_pipe_done_1" "0,1" newline bitfld.long 0xAC 0. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_0_CLR,Status write 1 to clear for level_vpac_out_5_en_pipe_done_0" "0,1" line.long 0xB0 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_5_4,Status Clear Register 44" bitfld.long 0xB0 31. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_31" "0,1" newline bitfld.long 0xB0 30. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_30" "0,1" newline bitfld.long 0xB0 29. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_29" "0,1" newline bitfld.long 0xB0 28. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_28" "0,1" newline bitfld.long 0xB0 27. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_27" "0,1" newline bitfld.long 0xB0 26. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_26" "0,1" newline bitfld.long 0xB0 25. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_25" "0,1" newline bitfld.long 0xB0 24. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_24" "0,1" newline bitfld.long 0xB0 23. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_23" "0,1" newline bitfld.long 0xB0 22. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_22" "0,1" newline bitfld.long 0xB0 21. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_21" "0,1" newline bitfld.long 0xB0 20. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_20" "0,1" newline bitfld.long 0xB0 19. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_19" "0,1" newline bitfld.long 0xB0 18. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_18" "0,1" newline bitfld.long 0xB0 17. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_17" "0,1" newline bitfld.long 0xB0 16. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_16" "0,1" newline bitfld.long 0xB0 15. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_15" "0,1" newline bitfld.long 0xB0 14. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_14" "0,1" newline bitfld.long 0xB0 13. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_13" "0,1" newline bitfld.long 0xB0 12. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_12" "0,1" newline bitfld.long 0xB0 11. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_11" "0,1" newline bitfld.long 0xB0 10. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_10" "0,1" newline bitfld.long 0xB0 9. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_9" "0,1" newline bitfld.long 0xB0 8. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_8" "0,1" newline bitfld.long 0xB0 7. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_7" "0,1" newline bitfld.long 0xB0 6. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_6" "0,1" newline bitfld.long 0xB0 5. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_5" "0,1" newline bitfld.long 0xB0 4. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_4" "0,1" newline bitfld.long 0xB0 3. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_3" "0,1" newline bitfld.long 0xB0 2. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_2" "0,1" newline bitfld.long 0xB0 1. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_1" "0,1" newline bitfld.long 0xB0 0. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_0" "0,1" line.long 0xB4 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_5_5,Status Clear Register 45" bitfld.long 0xB4 31. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_31" "0,1" newline bitfld.long 0xB4 30. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_30" "0,1" newline bitfld.long 0xB4 29. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_29" "0,1" newline bitfld.long 0xB4 28. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_28" "0,1" newline bitfld.long 0xB4 27. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_27" "0,1" newline bitfld.long 0xB4 26. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_26" "0,1" newline bitfld.long 0xB4 25. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_25" "0,1" newline bitfld.long 0xB4 24. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_24" "0,1" newline bitfld.long 0xB4 23. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_23" "0,1" newline bitfld.long 0xB4 22. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_22" "0,1" newline bitfld.long 0xB4 21. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_21" "0,1" newline bitfld.long 0xB4 20. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_20" "0,1" newline bitfld.long 0xB4 19. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_19" "0,1" newline bitfld.long 0xB4 18. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_18" "0,1" newline bitfld.long 0xB4 17. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_17" "0,1" newline bitfld.long 0xB4 16. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_16" "0,1" newline bitfld.long 0xB4 15. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_15" "0,1" newline bitfld.long 0xB4 14. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_14" "0,1" newline bitfld.long 0xB4 13. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_13" "0,1" newline bitfld.long 0xB4 12. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_12" "0,1" newline bitfld.long 0xB4 11. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_11" "0,1" newline bitfld.long 0xB4 10. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_10" "0,1" newline bitfld.long 0xB4 9. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_9" "0,1" newline bitfld.long 0xB4 8. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_8" "0,1" newline bitfld.long 0xB4 7. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_7" "0,1" newline bitfld.long 0xB4 6. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_6" "0,1" newline bitfld.long 0xB4 5. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_5" "0,1" newline bitfld.long 0xB4 4. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_4" "0,1" newline bitfld.long 0xB4 3. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_3" "0,1" newline bitfld.long 0xB4 2. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_2" "0,1" newline bitfld.long 0xB4 1. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_1" "0,1" newline bitfld.long 0xB4 0. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_0" "0,1" line.long 0xB8 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_5_6,Status Clear Register 46" bitfld.long 0xB8 31. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_63_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_63" "0,1" newline bitfld.long 0xB8 30. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_62_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_62" "0,1" newline bitfld.long 0xB8 29. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_61_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_61" "0,1" newline bitfld.long 0xB8 28. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_60_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_60" "0,1" newline bitfld.long 0xB8 27. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_59_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_59" "0,1" newline bitfld.long 0xB8 26. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_58_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_58" "0,1" newline bitfld.long 0xB8 25. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_57_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_57" "0,1" newline bitfld.long 0xB8 24. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_56_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_56" "0,1" newline bitfld.long 0xB8 23. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_55_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_55" "0,1" newline bitfld.long 0xB8 22. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_54_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_54" "0,1" newline bitfld.long 0xB8 21. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_53_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_53" "0,1" newline bitfld.long 0xB8 20. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_52_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_52" "0,1" newline bitfld.long 0xB8 19. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_51_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_51" "0,1" newline bitfld.long 0xB8 18. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_50_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_50" "0,1" newline bitfld.long 0xB8 17. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_49_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_49" "0,1" newline bitfld.long 0xB8 16. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_48_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_48" "0,1" newline bitfld.long 0xB8 15. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_47_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_47" "0,1" newline bitfld.long 0xB8 14. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_46_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_46" "0,1" newline bitfld.long 0xB8 13. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_45_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_45" "0,1" newline bitfld.long 0xB8 12. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_44_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_44" "0,1" newline bitfld.long 0xB8 11. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_43_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_43" "0,1" newline bitfld.long 0xB8 10. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_42_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_42" "0,1" newline bitfld.long 0xB8 9. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_41_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_41" "0,1" newline bitfld.long 0xB8 8. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_40_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_40" "0,1" newline bitfld.long 0xB8 7. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_39_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_39" "0,1" newline bitfld.long 0xB8 6. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_38_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_38" "0,1" newline bitfld.long 0xB8 5. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_37_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_37" "0,1" newline bitfld.long 0xB8 4. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_36_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_36" "0,1" newline bitfld.long 0xB8 3. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_35_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_35" "0,1" newline bitfld.long 0xB8 2. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_34_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_34" "0,1" newline bitfld.long 0xB8 1. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_33_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_33" "0,1" newline bitfld.long 0xB8 0. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_32_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_32" "0,1" line.long 0xBC "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_5_7,Status Clear Register 47" bitfld.long 0xBC 4. "STATUS_LEVEL_VPAC_OUT_5_CTM_PULSE_CLR,Status write 1 to clear for level_vpac_out_5_en_ctm_pulse" "0,1" newline bitfld.long 0xBC 3. "STATUS_LEVEL_VPAC_OUT_5_UTC1_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_prot_err" "0,1" newline bitfld.long 0xBC 2. "STATUS_LEVEL_VPAC_OUT_5_UTC0_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_prot_err" "0,1" newline bitfld.long 0xBC 1. "STATUS_LEVEL_VPAC_OUT_5_UTC1_ERROR_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_error" "0,1" newline bitfld.long 0xBC 0. "STATUS_LEVEL_VPAC_OUT_5_UTC0_ERROR_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_error" "0,1" line.long 0xC0 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_0_0,Status Clear Register 48" bitfld.long 0xC0 26. "STATUS_PULSE_VPAC_OUT_0_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xC0 25. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xC0 24. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xC0 23. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xC0 22. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xC0 21. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xC0 20. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xC0 19. "STATUS_PULSE_VPAC_OUT_0_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xC0 18. "STATUS_PULSE_VPAC_OUT_0_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xC0 17. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xC0 16. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xC0 15. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xC0 14. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xC0 13. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xC0 12. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xC0 11. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xC0 10. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xC0 9. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xC0 8. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xC0 7. "STATUS_PULSE_VPAC_OUT_0_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xC0 6. "STATUS_PULSE_VPAC_OUT_0_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xC0 5. "STATUS_PULSE_VPAC_OUT_0_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xC0 4. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xC0 3. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xC0 2. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xC0 1. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xC0 0. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1" line.long 0xC4 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_0_1,Status Clear Register 49" bitfld.long 0xC4 8. "STATUS_PULSE_VPAC_OUT_0_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xC4 7. "STATUS_PULSE_VPAC_OUT_0_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xC4 6. "STATUS_PULSE_VPAC_OUT_0_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xC4 5. "STATUS_PULSE_VPAC_OUT_0_LDC0_INT_SZOVF_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xC4 4. "STATUS_PULSE_VPAC_OUT_0_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xC4 3. "STATUS_PULSE_VPAC_OUT_0_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xC4 2. "STATUS_PULSE_VPAC_OUT_0_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xC4 1. "STATUS_PULSE_VPAC_OUT_0_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xC4 0. "STATUS_PULSE_VPAC_OUT_0_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xC8 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_0_2,Status Clear Register 50" bitfld.long 0xC8 10. "STATUS_PULSE_VPAC_OUT_0_NF_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0xC8 9. "STATUS_PULSE_VPAC_OUT_0_NF_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0xC8 8. "STATUS_PULSE_VPAC_OUT_0_NF_FRAME_DONE_CLR,Status write 1 to clear for pulse_vpac_out_0_en_nf_frame_done" "0,1" newline bitfld.long 0xC8 3. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xC8 2. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xC8 1. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for pulse_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xC8 0. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for pulse_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xCC "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_0_3,Status Clear Register 51" bitfld.long 0xCC 26. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for pulse_vpac_out_0_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xCC 25. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for pulse_vpac_out_0_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xCC 24. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for pulse_vpac_out_0_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xCC 22. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for pulse_vpac_out_0_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xCC 20. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_vpac_out_0_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xCC 15. "STATUS_PULSE_VPAC_OUT_0_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_vpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0xCC 14. "STATUS_PULSE_VPAC_OUT_0_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_vpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0xCC 13. "STATUS_PULSE_VPAC_OUT_0_TDONE_6_CLR,Status write 1 to clear for pulse_vpac_out_0_en_tdone_6" "0,1" newline bitfld.long 0xCC 12. "STATUS_PULSE_VPAC_OUT_0_TDONE_5_CLR,Status write 1 to clear for pulse_vpac_out_0_en_tdone_5" "0,1" newline bitfld.long 0xCC 11. "STATUS_PULSE_VPAC_OUT_0_TDONE_4_CLR,Status write 1 to clear for pulse_vpac_out_0_en_tdone_4" "0,1" newline bitfld.long 0xCC 9. "STATUS_PULSE_VPAC_OUT_0_TDONE_2_CLR,Status write 1 to clear for pulse_vpac_out_0_en_tdone_2" "0,1" newline bitfld.long 0xCC 7. "STATUS_PULSE_VPAC_OUT_0_TDONE_0_CLR,Status write 1 to clear for pulse_vpac_out_0_en_tdone_0" "0,1" newline bitfld.long 0xCC 6. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_6_CLR,Status write 1 to clear for pulse_vpac_out_0_en_pipe_done_6" "0,1" newline bitfld.long 0xCC 5. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_5_CLR,Status write 1 to clear for pulse_vpac_out_0_en_pipe_done_5" "0,1" newline bitfld.long 0xCC 4. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_4_CLR,Status write 1 to clear for pulse_vpac_out_0_en_pipe_done_4" "0,1" newline bitfld.long 0xCC 3. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_vpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0xCC 2. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_vpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0xCC 1. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_vpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0xCC 0. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_vpac_out_0_en_pipe_done_0" "0,1" line.long 0xD0 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_0_4,Status Clear Register 52" bitfld.long 0xD0 31. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_31" "0,1" newline bitfld.long 0xD0 30. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_30" "0,1" newline bitfld.long 0xD0 29. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_29" "0,1" newline bitfld.long 0xD0 28. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_28" "0,1" newline bitfld.long 0xD0 27. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_27" "0,1" newline bitfld.long 0xD0 26. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_26" "0,1" newline bitfld.long 0xD0 25. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_25" "0,1" newline bitfld.long 0xD0 24. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_24" "0,1" newline bitfld.long 0xD0 23. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_23" "0,1" newline bitfld.long 0xD0 22. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_22" "0,1" newline bitfld.long 0xD0 21. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_21" "0,1" newline bitfld.long 0xD0 20. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_20" "0,1" newline bitfld.long 0xD0 19. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_19" "0,1" newline bitfld.long 0xD0 18. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_18" "0,1" newline bitfld.long 0xD0 17. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_17" "0,1" newline bitfld.long 0xD0 16. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_16" "0,1" newline bitfld.long 0xD0 15. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_15" "0,1" newline bitfld.long 0xD0 14. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_14" "0,1" newline bitfld.long 0xD0 13. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_13" "0,1" newline bitfld.long 0xD0 12. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_12" "0,1" newline bitfld.long 0xD0 11. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_11" "0,1" newline bitfld.long 0xD0 10. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_10" "0,1" newline bitfld.long 0xD0 9. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_9" "0,1" newline bitfld.long 0xD0 8. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_8" "0,1" newline bitfld.long 0xD0 7. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_7" "0,1" newline bitfld.long 0xD0 6. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_6" "0,1" newline bitfld.long 0xD0 5. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_5" "0,1" newline bitfld.long 0xD0 4. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_4" "0,1" newline bitfld.long 0xD0 3. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_3" "0,1" newline bitfld.long 0xD0 2. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_2" "0,1" newline bitfld.long 0xD0 1. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_1" "0,1" newline bitfld.long 0xD0 0. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_0" "0,1" line.long 0xD4 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_0_5,Status Clear Register 53" bitfld.long 0xD4 31. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_31" "0,1" newline bitfld.long 0xD4 30. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_30" "0,1" newline bitfld.long 0xD4 29. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_29" "0,1" newline bitfld.long 0xD4 28. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_28" "0,1" newline bitfld.long 0xD4 27. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_27" "0,1" newline bitfld.long 0xD4 26. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_26" "0,1" newline bitfld.long 0xD4 25. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_25" "0,1" newline bitfld.long 0xD4 24. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_24" "0,1" newline bitfld.long 0xD4 23. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_23" "0,1" newline bitfld.long 0xD4 22. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_22" "0,1" newline bitfld.long 0xD4 21. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_21" "0,1" newline bitfld.long 0xD4 20. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_20" "0,1" newline bitfld.long 0xD4 19. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_19" "0,1" newline bitfld.long 0xD4 18. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_18" "0,1" newline bitfld.long 0xD4 17. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_17" "0,1" newline bitfld.long 0xD4 16. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_16" "0,1" newline bitfld.long 0xD4 15. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_15" "0,1" newline bitfld.long 0xD4 14. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_14" "0,1" newline bitfld.long 0xD4 13. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_13" "0,1" newline bitfld.long 0xD4 12. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_12" "0,1" newline bitfld.long 0xD4 11. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_11" "0,1" newline bitfld.long 0xD4 10. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_10" "0,1" newline bitfld.long 0xD4 9. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_9" "0,1" newline bitfld.long 0xD4 8. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_8" "0,1" newline bitfld.long 0xD4 7. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_7" "0,1" newline bitfld.long 0xD4 6. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_6" "0,1" newline bitfld.long 0xD4 5. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_5" "0,1" newline bitfld.long 0xD4 4. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_4" "0,1" newline bitfld.long 0xD4 3. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_3" "0,1" newline bitfld.long 0xD4 2. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_2" "0,1" newline bitfld.long 0xD4 1. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_1" "0,1" newline bitfld.long 0xD4 0. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_0" "0,1" line.long 0xD8 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_0_6,Status Clear Register 54" bitfld.long 0xD8 31. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_63_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_63" "0,1" newline bitfld.long 0xD8 30. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_62_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_62" "0,1" newline bitfld.long 0xD8 29. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_61_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_61" "0,1" newline bitfld.long 0xD8 28. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_60_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_60" "0,1" newline bitfld.long 0xD8 27. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_59_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_59" "0,1" newline bitfld.long 0xD8 26. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_58_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_58" "0,1" newline bitfld.long 0xD8 25. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_57_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_57" "0,1" newline bitfld.long 0xD8 24. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_56_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_56" "0,1" newline bitfld.long 0xD8 23. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_55_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_55" "0,1" newline bitfld.long 0xD8 22. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_54_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_54" "0,1" newline bitfld.long 0xD8 21. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_53_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_53" "0,1" newline bitfld.long 0xD8 20. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_52_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_52" "0,1" newline bitfld.long 0xD8 19. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_51_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_51" "0,1" newline bitfld.long 0xD8 18. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_50_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_50" "0,1" newline bitfld.long 0xD8 17. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_49_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_49" "0,1" newline bitfld.long 0xD8 16. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_48_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_48" "0,1" newline bitfld.long 0xD8 15. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_47_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_47" "0,1" newline bitfld.long 0xD8 14. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_46_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_46" "0,1" newline bitfld.long 0xD8 13. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_45_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_45" "0,1" newline bitfld.long 0xD8 12. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_44_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_44" "0,1" newline bitfld.long 0xD8 11. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_43_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_43" "0,1" newline bitfld.long 0xD8 10. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_42_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_42" "0,1" newline bitfld.long 0xD8 9. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_41_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_41" "0,1" newline bitfld.long 0xD8 8. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_40_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_40" "0,1" newline bitfld.long 0xD8 7. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_39_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_39" "0,1" newline bitfld.long 0xD8 6. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_38_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_38" "0,1" newline bitfld.long 0xD8 5. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_37_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_37" "0,1" newline bitfld.long 0xD8 4. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_36_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_36" "0,1" newline bitfld.long 0xD8 3. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_35_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_35" "0,1" newline bitfld.long 0xD8 2. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_34_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_34" "0,1" newline bitfld.long 0xD8 1. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_33_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_33" "0,1" newline bitfld.long 0xD8 0. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_32_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_32" "0,1" line.long 0xDC "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_0_7,Status Clear Register 55" bitfld.long 0xDC 4. "STATUS_PULSE_VPAC_OUT_0_CTM_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0xDC 3. "STATUS_PULSE_VPAC_OUT_0_UTC1_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_prot_err" "0,1" newline bitfld.long 0xDC 2. "STATUS_PULSE_VPAC_OUT_0_UTC0_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_prot_err" "0,1" newline bitfld.long 0xDC 1. "STATUS_PULSE_VPAC_OUT_0_UTC1_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_error" "0,1" newline bitfld.long 0xDC 0. "STATUS_PULSE_VPAC_OUT_0_UTC0_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_error" "0,1" line.long 0xE0 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_1_0,Status Clear Register 56" bitfld.long 0xE0 26. "STATUS_PULSE_VPAC_OUT_1_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xE0 25. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xE0 24. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xE0 23. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xE0 22. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xE0 21. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xE0 20. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xE0 19. "STATUS_PULSE_VPAC_OUT_1_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xE0 18. "STATUS_PULSE_VPAC_OUT_1_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xE0 17. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xE0 16. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xE0 15. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xE0 14. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xE0 13. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xE0 12. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xE0 11. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xE0 10. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xE0 9. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xE0 8. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xE0 7. "STATUS_PULSE_VPAC_OUT_1_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xE0 6. "STATUS_PULSE_VPAC_OUT_1_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xE0 5. "STATUS_PULSE_VPAC_OUT_1_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xE0 4. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xE0 3. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xE0 2. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xE0 1. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xE0 0. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1" line.long 0xE4 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_1_1,Status Clear Register 57" bitfld.long 0xE4 8. "STATUS_PULSE_VPAC_OUT_1_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xE4 7. "STATUS_PULSE_VPAC_OUT_1_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xE4 6. "STATUS_PULSE_VPAC_OUT_1_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xE4 5. "STATUS_PULSE_VPAC_OUT_1_LDC0_INT_SZOVF_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xE4 4. "STATUS_PULSE_VPAC_OUT_1_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xE4 3. "STATUS_PULSE_VPAC_OUT_1_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xE4 2. "STATUS_PULSE_VPAC_OUT_1_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xE4 1. "STATUS_PULSE_VPAC_OUT_1_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xE4 0. "STATUS_PULSE_VPAC_OUT_1_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xE8 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_1_2,Status Clear Register 58" bitfld.long 0xE8 10. "STATUS_PULSE_VPAC_OUT_1_NF_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0xE8 9. "STATUS_PULSE_VPAC_OUT_1_NF_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0xE8 8. "STATUS_PULSE_VPAC_OUT_1_NF_FRAME_DONE_CLR,Status write 1 to clear for pulse_vpac_out_1_en_nf_frame_done" "0,1" newline bitfld.long 0xE8 3. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xE8 2. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xE8 1. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for pulse_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xE8 0. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for pulse_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xEC "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_1_3,Status Clear Register 59" bitfld.long 0xEC 26. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for pulse_vpac_out_1_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xEC 25. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for pulse_vpac_out_1_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xEC 24. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for pulse_vpac_out_1_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xEC 22. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for pulse_vpac_out_1_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xEC 20. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_vpac_out_1_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xEC 15. "STATUS_PULSE_VPAC_OUT_1_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_vpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0xEC 14. "STATUS_PULSE_VPAC_OUT_1_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_vpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0xEC 13. "STATUS_PULSE_VPAC_OUT_1_TDONE_6_CLR,Status write 1 to clear for pulse_vpac_out_1_en_tdone_6" "0,1" newline bitfld.long 0xEC 12. "STATUS_PULSE_VPAC_OUT_1_TDONE_5_CLR,Status write 1 to clear for pulse_vpac_out_1_en_tdone_5" "0,1" newline bitfld.long 0xEC 11. "STATUS_PULSE_VPAC_OUT_1_TDONE_4_CLR,Status write 1 to clear for pulse_vpac_out_1_en_tdone_4" "0,1" newline bitfld.long 0xEC 9. "STATUS_PULSE_VPAC_OUT_1_TDONE_2_CLR,Status write 1 to clear for pulse_vpac_out_1_en_tdone_2" "0,1" newline bitfld.long 0xEC 7. "STATUS_PULSE_VPAC_OUT_1_TDONE_0_CLR,Status write 1 to clear for pulse_vpac_out_1_en_tdone_0" "0,1" newline bitfld.long 0xEC 6. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_6_CLR,Status write 1 to clear for pulse_vpac_out_1_en_pipe_done_6" "0,1" newline bitfld.long 0xEC 5. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_5_CLR,Status write 1 to clear for pulse_vpac_out_1_en_pipe_done_5" "0,1" newline bitfld.long 0xEC 4. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_4_CLR,Status write 1 to clear for pulse_vpac_out_1_en_pipe_done_4" "0,1" newline bitfld.long 0xEC 3. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_vpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0xEC 2. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_vpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0xEC 1. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_vpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0xEC 0. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_vpac_out_1_en_pipe_done_0" "0,1" line.long 0xF0 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_1_4,Status Clear Register 60" bitfld.long 0xF0 31. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_31" "0,1" newline bitfld.long 0xF0 30. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_30" "0,1" newline bitfld.long 0xF0 29. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_29" "0,1" newline bitfld.long 0xF0 28. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_28" "0,1" newline bitfld.long 0xF0 27. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_27" "0,1" newline bitfld.long 0xF0 26. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_26" "0,1" newline bitfld.long 0xF0 25. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_25" "0,1" newline bitfld.long 0xF0 24. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_24" "0,1" newline bitfld.long 0xF0 23. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_23" "0,1" newline bitfld.long 0xF0 22. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_22" "0,1" newline bitfld.long 0xF0 21. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_21" "0,1" newline bitfld.long 0xF0 20. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_20" "0,1" newline bitfld.long 0xF0 19. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_19" "0,1" newline bitfld.long 0xF0 18. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_18" "0,1" newline bitfld.long 0xF0 17. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_17" "0,1" newline bitfld.long 0xF0 16. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_16" "0,1" newline bitfld.long 0xF0 15. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_15" "0,1" newline bitfld.long 0xF0 14. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_14" "0,1" newline bitfld.long 0xF0 13. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_13" "0,1" newline bitfld.long 0xF0 12. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_12" "0,1" newline bitfld.long 0xF0 11. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_11" "0,1" newline bitfld.long 0xF0 10. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_10" "0,1" newline bitfld.long 0xF0 9. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_9" "0,1" newline bitfld.long 0xF0 8. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_8" "0,1" newline bitfld.long 0xF0 7. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_7" "0,1" newline bitfld.long 0xF0 6. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_6" "0,1" newline bitfld.long 0xF0 5. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_5" "0,1" newline bitfld.long 0xF0 4. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_4" "0,1" newline bitfld.long 0xF0 3. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_3" "0,1" newline bitfld.long 0xF0 2. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_2" "0,1" newline bitfld.long 0xF0 1. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_1" "0,1" newline bitfld.long 0xF0 0. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_0" "0,1" line.long 0xF4 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_1_5,Status Clear Register 61" bitfld.long 0xF4 31. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_31" "0,1" newline bitfld.long 0xF4 30. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_30" "0,1" newline bitfld.long 0xF4 29. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_29" "0,1" newline bitfld.long 0xF4 28. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_28" "0,1" newline bitfld.long 0xF4 27. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_27" "0,1" newline bitfld.long 0xF4 26. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_26" "0,1" newline bitfld.long 0xF4 25. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_25" "0,1" newline bitfld.long 0xF4 24. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_24" "0,1" newline bitfld.long 0xF4 23. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_23" "0,1" newline bitfld.long 0xF4 22. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_22" "0,1" newline bitfld.long 0xF4 21. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_21" "0,1" newline bitfld.long 0xF4 20. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_20" "0,1" newline bitfld.long 0xF4 19. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_19" "0,1" newline bitfld.long 0xF4 18. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_18" "0,1" newline bitfld.long 0xF4 17. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_17" "0,1" newline bitfld.long 0xF4 16. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_16" "0,1" newline bitfld.long 0xF4 15. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_15" "0,1" newline bitfld.long 0xF4 14. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_14" "0,1" newline bitfld.long 0xF4 13. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_13" "0,1" newline bitfld.long 0xF4 12. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_12" "0,1" newline bitfld.long 0xF4 11. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_11" "0,1" newline bitfld.long 0xF4 10. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_10" "0,1" newline bitfld.long 0xF4 9. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_9" "0,1" newline bitfld.long 0xF4 8. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_8" "0,1" newline bitfld.long 0xF4 7. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_7" "0,1" newline bitfld.long 0xF4 6. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_6" "0,1" newline bitfld.long 0xF4 5. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_5" "0,1" newline bitfld.long 0xF4 4. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_4" "0,1" newline bitfld.long 0xF4 3. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_3" "0,1" newline bitfld.long 0xF4 2. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_2" "0,1" newline bitfld.long 0xF4 1. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_1" "0,1" newline bitfld.long 0xF4 0. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_0" "0,1" line.long 0xF8 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_1_6,Status Clear Register 62" bitfld.long 0xF8 31. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_63_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_63" "0,1" newline bitfld.long 0xF8 30. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_62_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_62" "0,1" newline bitfld.long 0xF8 29. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_61_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_61" "0,1" newline bitfld.long 0xF8 28. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_60_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_60" "0,1" newline bitfld.long 0xF8 27. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_59_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_59" "0,1" newline bitfld.long 0xF8 26. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_58_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_58" "0,1" newline bitfld.long 0xF8 25. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_57_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_57" "0,1" newline bitfld.long 0xF8 24. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_56_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_56" "0,1" newline bitfld.long 0xF8 23. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_55_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_55" "0,1" newline bitfld.long 0xF8 22. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_54_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_54" "0,1" newline bitfld.long 0xF8 21. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_53_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_53" "0,1" newline bitfld.long 0xF8 20. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_52_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_52" "0,1" newline bitfld.long 0xF8 19. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_51_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_51" "0,1" newline bitfld.long 0xF8 18. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_50_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_50" "0,1" newline bitfld.long 0xF8 17. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_49_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_49" "0,1" newline bitfld.long 0xF8 16. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_48_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_48" "0,1" newline bitfld.long 0xF8 15. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_47_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_47" "0,1" newline bitfld.long 0xF8 14. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_46_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_46" "0,1" newline bitfld.long 0xF8 13. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_45_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_45" "0,1" newline bitfld.long 0xF8 12. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_44_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_44" "0,1" newline bitfld.long 0xF8 11. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_43_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_43" "0,1" newline bitfld.long 0xF8 10. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_42_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_42" "0,1" newline bitfld.long 0xF8 9. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_41_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_41" "0,1" newline bitfld.long 0xF8 8. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_40_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_40" "0,1" newline bitfld.long 0xF8 7. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_39_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_39" "0,1" newline bitfld.long 0xF8 6. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_38_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_38" "0,1" newline bitfld.long 0xF8 5. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_37_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_37" "0,1" newline bitfld.long 0xF8 4. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_36_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_36" "0,1" newline bitfld.long 0xF8 3. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_35_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_35" "0,1" newline bitfld.long 0xF8 2. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_34_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_34" "0,1" newline bitfld.long 0xF8 1. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_33_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_33" "0,1" newline bitfld.long 0xF8 0. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_32_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_32" "0,1" line.long 0xFC "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_1_7,Status Clear Register 63" bitfld.long 0xFC 4. "STATUS_PULSE_VPAC_OUT_1_CTM_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0xFC 3. "STATUS_PULSE_VPAC_OUT_1_UTC1_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_prot_err" "0,1" newline bitfld.long 0xFC 2. "STATUS_PULSE_VPAC_OUT_1_UTC0_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_prot_err" "0,1" newline bitfld.long 0xFC 1. "STATUS_PULSE_VPAC_OUT_1_UTC1_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_error" "0,1" newline bitfld.long 0xFC 0. "STATUS_PULSE_VPAC_OUT_1_UTC0_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_error" "0,1" line.long 0x100 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_2_0,Status Clear Register 64" bitfld.long 0x100 26. "STATUS_PULSE_VPAC_OUT_2_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x100 25. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x100 24. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x100 23. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x100 22. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x100 21. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x100 20. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x100 19. "STATUS_PULSE_VPAC_OUT_2_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x100 18. "STATUS_PULSE_VPAC_OUT_2_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x100 17. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x100 16. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x100 15. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x100 14. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x100 13. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x100 12. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x100 11. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x100 10. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x100 9. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x100 8. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x100 7. "STATUS_PULSE_VPAC_OUT_2_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x100 6. "STATUS_PULSE_VPAC_OUT_2_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x100 5. "STATUS_PULSE_VPAC_OUT_2_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x100 4. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x100 3. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x100 2. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x100 1. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x100 0. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1" line.long 0x104 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_2_1,Status Clear Register 65" bitfld.long 0x104 8. "STATUS_PULSE_VPAC_OUT_2_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x104 7. "STATUS_PULSE_VPAC_OUT_2_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x104 6. "STATUS_PULSE_VPAC_OUT_2_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x104 5. "STATUS_PULSE_VPAC_OUT_2_LDC0_INT_SZOVF_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x104 4. "STATUS_PULSE_VPAC_OUT_2_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x104 3. "STATUS_PULSE_VPAC_OUT_2_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x104 2. "STATUS_PULSE_VPAC_OUT_2_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x104 1. "STATUS_PULSE_VPAC_OUT_2_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x104 0. "STATUS_PULSE_VPAC_OUT_2_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x108 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_2_2,Status Clear Register 66" bitfld.long 0x108 10. "STATUS_PULSE_VPAC_OUT_2_NF_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x108 9. "STATUS_PULSE_VPAC_OUT_2_NF_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x108 8. "STATUS_PULSE_VPAC_OUT_2_NF_FRAME_DONE_CLR,Status write 1 to clear for pulse_vpac_out_2_en_nf_frame_done" "0,1" newline bitfld.long 0x108 3. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x108 2. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x108 1. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for pulse_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x108 0. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for pulse_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x10C "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_2_3,Status Clear Register 67" bitfld.long 0x10C 26. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for pulse_vpac_out_2_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x10C 25. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for pulse_vpac_out_2_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x10C 24. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for pulse_vpac_out_2_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x10C 22. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for pulse_vpac_out_2_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x10C 20. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_vpac_out_2_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x10C 15. "STATUS_PULSE_VPAC_OUT_2_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_vpac_out_2_en_spare_dec_1" "0,1" newline bitfld.long 0x10C 14. "STATUS_PULSE_VPAC_OUT_2_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_vpac_out_2_en_spare_dec_0" "0,1" newline bitfld.long 0x10C 13. "STATUS_PULSE_VPAC_OUT_2_TDONE_6_CLR,Status write 1 to clear for pulse_vpac_out_2_en_tdone_6" "0,1" newline bitfld.long 0x10C 12. "STATUS_PULSE_VPAC_OUT_2_TDONE_5_CLR,Status write 1 to clear for pulse_vpac_out_2_en_tdone_5" "0,1" newline bitfld.long 0x10C 11. "STATUS_PULSE_VPAC_OUT_2_TDONE_4_CLR,Status write 1 to clear for pulse_vpac_out_2_en_tdone_4" "0,1" newline bitfld.long 0x10C 9. "STATUS_PULSE_VPAC_OUT_2_TDONE_2_CLR,Status write 1 to clear for pulse_vpac_out_2_en_tdone_2" "0,1" newline bitfld.long 0x10C 7. "STATUS_PULSE_VPAC_OUT_2_TDONE_0_CLR,Status write 1 to clear for pulse_vpac_out_2_en_tdone_0" "0,1" newline bitfld.long 0x10C 6. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_6_CLR,Status write 1 to clear for pulse_vpac_out_2_en_pipe_done_6" "0,1" newline bitfld.long 0x10C 5. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_5_CLR,Status write 1 to clear for pulse_vpac_out_2_en_pipe_done_5" "0,1" newline bitfld.long 0x10C 4. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_4_CLR,Status write 1 to clear for pulse_vpac_out_2_en_pipe_done_4" "0,1" newline bitfld.long 0x10C 3. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_vpac_out_2_en_pipe_done_3" "0,1" newline bitfld.long 0x10C 2. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_vpac_out_2_en_pipe_done_2" "0,1" newline bitfld.long 0x10C 1. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_vpac_out_2_en_pipe_done_1" "0,1" newline bitfld.long 0x10C 0. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_vpac_out_2_en_pipe_done_0" "0,1" line.long 0x110 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_2_4,Status Clear Register 68" bitfld.long 0x110 31. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_31" "0,1" newline bitfld.long 0x110 30. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_30" "0,1" newline bitfld.long 0x110 29. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_29" "0,1" newline bitfld.long 0x110 28. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_28" "0,1" newline bitfld.long 0x110 27. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_27" "0,1" newline bitfld.long 0x110 26. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_26" "0,1" newline bitfld.long 0x110 25. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_25" "0,1" newline bitfld.long 0x110 24. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_24" "0,1" newline bitfld.long 0x110 23. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_23" "0,1" newline bitfld.long 0x110 22. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_22" "0,1" newline bitfld.long 0x110 21. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_21" "0,1" newline bitfld.long 0x110 20. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_20" "0,1" newline bitfld.long 0x110 19. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_19" "0,1" newline bitfld.long 0x110 18. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_18" "0,1" newline bitfld.long 0x110 17. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_17" "0,1" newline bitfld.long 0x110 16. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_16" "0,1" newline bitfld.long 0x110 15. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_15" "0,1" newline bitfld.long 0x110 14. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_14" "0,1" newline bitfld.long 0x110 13. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_13" "0,1" newline bitfld.long 0x110 12. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_12" "0,1" newline bitfld.long 0x110 11. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_11" "0,1" newline bitfld.long 0x110 10. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_10" "0,1" newline bitfld.long 0x110 9. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_9" "0,1" newline bitfld.long 0x110 8. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_8" "0,1" newline bitfld.long 0x110 7. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_7" "0,1" newline bitfld.long 0x110 6. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_6" "0,1" newline bitfld.long 0x110 5. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_5" "0,1" newline bitfld.long 0x110 4. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_4" "0,1" newline bitfld.long 0x110 3. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_3" "0,1" newline bitfld.long 0x110 2. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_2" "0,1" newline bitfld.long 0x110 1. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_1" "0,1" newline bitfld.long 0x110 0. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_0" "0,1" line.long 0x114 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_2_5,Status Clear Register 69" bitfld.long 0x114 31. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_31" "0,1" newline bitfld.long 0x114 30. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_30" "0,1" newline bitfld.long 0x114 29. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_29" "0,1" newline bitfld.long 0x114 28. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_28" "0,1" newline bitfld.long 0x114 27. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_27" "0,1" newline bitfld.long 0x114 26. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_26" "0,1" newline bitfld.long 0x114 25. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_25" "0,1" newline bitfld.long 0x114 24. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_24" "0,1" newline bitfld.long 0x114 23. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_23" "0,1" newline bitfld.long 0x114 22. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_22" "0,1" newline bitfld.long 0x114 21. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_21" "0,1" newline bitfld.long 0x114 20. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_20" "0,1" newline bitfld.long 0x114 19. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_19" "0,1" newline bitfld.long 0x114 18. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_18" "0,1" newline bitfld.long 0x114 17. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_17" "0,1" newline bitfld.long 0x114 16. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_16" "0,1" newline bitfld.long 0x114 15. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_15" "0,1" newline bitfld.long 0x114 14. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_14" "0,1" newline bitfld.long 0x114 13. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_13" "0,1" newline bitfld.long 0x114 12. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_12" "0,1" newline bitfld.long 0x114 11. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_11" "0,1" newline bitfld.long 0x114 10. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_10" "0,1" newline bitfld.long 0x114 9. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_9" "0,1" newline bitfld.long 0x114 8. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_8" "0,1" newline bitfld.long 0x114 7. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_7" "0,1" newline bitfld.long 0x114 6. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_6" "0,1" newline bitfld.long 0x114 5. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_5" "0,1" newline bitfld.long 0x114 4. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_4" "0,1" newline bitfld.long 0x114 3. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_3" "0,1" newline bitfld.long 0x114 2. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_2" "0,1" newline bitfld.long 0x114 1. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_1" "0,1" newline bitfld.long 0x114 0. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_0" "0,1" line.long 0x118 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_2_6,Status Clear Register 70" bitfld.long 0x118 31. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_63_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_63" "0,1" newline bitfld.long 0x118 30. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_62_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_62" "0,1" newline bitfld.long 0x118 29. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_61_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_61" "0,1" newline bitfld.long 0x118 28. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_60_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_60" "0,1" newline bitfld.long 0x118 27. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_59_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_59" "0,1" newline bitfld.long 0x118 26. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_58_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_58" "0,1" newline bitfld.long 0x118 25. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_57_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_57" "0,1" newline bitfld.long 0x118 24. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_56_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_56" "0,1" newline bitfld.long 0x118 23. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_55_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_55" "0,1" newline bitfld.long 0x118 22. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_54_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_54" "0,1" newline bitfld.long 0x118 21. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_53_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_53" "0,1" newline bitfld.long 0x118 20. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_52_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_52" "0,1" newline bitfld.long 0x118 19. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_51_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_51" "0,1" newline bitfld.long 0x118 18. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_50_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_50" "0,1" newline bitfld.long 0x118 17. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_49_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_49" "0,1" newline bitfld.long 0x118 16. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_48_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_48" "0,1" newline bitfld.long 0x118 15. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_47_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_47" "0,1" newline bitfld.long 0x118 14. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_46_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_46" "0,1" newline bitfld.long 0x118 13. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_45_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_45" "0,1" newline bitfld.long 0x118 12. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_44_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_44" "0,1" newline bitfld.long 0x118 11. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_43_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_43" "0,1" newline bitfld.long 0x118 10. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_42_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_42" "0,1" newline bitfld.long 0x118 9. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_41_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_41" "0,1" newline bitfld.long 0x118 8. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_40_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_40" "0,1" newline bitfld.long 0x118 7. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_39_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_39" "0,1" newline bitfld.long 0x118 6. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_38_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_38" "0,1" newline bitfld.long 0x118 5. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_37_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_37" "0,1" newline bitfld.long 0x118 4. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_36_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_36" "0,1" newline bitfld.long 0x118 3. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_35_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_35" "0,1" newline bitfld.long 0x118 2. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_34_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_34" "0,1" newline bitfld.long 0x118 1. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_33_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_33" "0,1" newline bitfld.long 0x118 0. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_32_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_32" "0,1" line.long 0x11C "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_2_7,Status Clear Register 71" bitfld.long 0x11C 4. "STATUS_PULSE_VPAC_OUT_2_CTM_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ctm_pulse" "0,1" newline bitfld.long 0x11C 3. "STATUS_PULSE_VPAC_OUT_2_UTC1_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_prot_err" "0,1" newline bitfld.long 0x11C 2. "STATUS_PULSE_VPAC_OUT_2_UTC0_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_prot_err" "0,1" newline bitfld.long 0x11C 1. "STATUS_PULSE_VPAC_OUT_2_UTC1_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_error" "0,1" newline bitfld.long 0x11C 0. "STATUS_PULSE_VPAC_OUT_2_UTC0_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_error" "0,1" line.long 0x120 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_3_0,Status Clear Register 72" bitfld.long 0x120 26. "STATUS_PULSE_VPAC_OUT_3_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x120 25. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x120 24. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x120 23. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x120 22. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x120 21. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x120 20. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x120 19. "STATUS_PULSE_VPAC_OUT_3_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x120 18. "STATUS_PULSE_VPAC_OUT_3_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x120 17. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x120 16. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x120 15. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x120 14. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x120 13. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x120 12. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x120 11. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x120 10. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x120 9. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x120 8. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x120 7. "STATUS_PULSE_VPAC_OUT_3_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x120 6. "STATUS_PULSE_VPAC_OUT_3_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x120 5. "STATUS_PULSE_VPAC_OUT_3_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x120 4. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x120 3. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x120 2. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x120 1. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x120 0. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1" line.long 0x124 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_3_1,Status Clear Register 73" bitfld.long 0x124 8. "STATUS_PULSE_VPAC_OUT_3_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x124 7. "STATUS_PULSE_VPAC_OUT_3_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x124 6. "STATUS_PULSE_VPAC_OUT_3_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x124 5. "STATUS_PULSE_VPAC_OUT_3_LDC0_INT_SZOVF_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x124 4. "STATUS_PULSE_VPAC_OUT_3_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x124 3. "STATUS_PULSE_VPAC_OUT_3_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x124 2. "STATUS_PULSE_VPAC_OUT_3_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x124 1. "STATUS_PULSE_VPAC_OUT_3_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x124 0. "STATUS_PULSE_VPAC_OUT_3_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x128 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_3_2,Status Clear Register 74" bitfld.long 0x128 10. "STATUS_PULSE_VPAC_OUT_3_NF_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x128 9. "STATUS_PULSE_VPAC_OUT_3_NF_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x128 8. "STATUS_PULSE_VPAC_OUT_3_NF_FRAME_DONE_CLR,Status write 1 to clear for pulse_vpac_out_3_en_nf_frame_done" "0,1" newline bitfld.long 0x128 3. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x128 2. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x128 1. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for pulse_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x128 0. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for pulse_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x12C "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_3_3,Status Clear Register 75" bitfld.long 0x12C 26. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for pulse_vpac_out_3_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x12C 25. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for pulse_vpac_out_3_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x12C 24. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for pulse_vpac_out_3_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x12C 22. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for pulse_vpac_out_3_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x12C 20. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_vpac_out_3_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x12C 15. "STATUS_PULSE_VPAC_OUT_3_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_vpac_out_3_en_spare_dec_1" "0,1" newline bitfld.long 0x12C 14. "STATUS_PULSE_VPAC_OUT_3_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_vpac_out_3_en_spare_dec_0" "0,1" newline bitfld.long 0x12C 13. "STATUS_PULSE_VPAC_OUT_3_TDONE_6_CLR,Status write 1 to clear for pulse_vpac_out_3_en_tdone_6" "0,1" newline bitfld.long 0x12C 12. "STATUS_PULSE_VPAC_OUT_3_TDONE_5_CLR,Status write 1 to clear for pulse_vpac_out_3_en_tdone_5" "0,1" newline bitfld.long 0x12C 11. "STATUS_PULSE_VPAC_OUT_3_TDONE_4_CLR,Status write 1 to clear for pulse_vpac_out_3_en_tdone_4" "0,1" newline bitfld.long 0x12C 9. "STATUS_PULSE_VPAC_OUT_3_TDONE_2_CLR,Status write 1 to clear for pulse_vpac_out_3_en_tdone_2" "0,1" newline bitfld.long 0x12C 7. "STATUS_PULSE_VPAC_OUT_3_TDONE_0_CLR,Status write 1 to clear for pulse_vpac_out_3_en_tdone_0" "0,1" newline bitfld.long 0x12C 6. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_6_CLR,Status write 1 to clear for pulse_vpac_out_3_en_pipe_done_6" "0,1" newline bitfld.long 0x12C 5. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_5_CLR,Status write 1 to clear for pulse_vpac_out_3_en_pipe_done_5" "0,1" newline bitfld.long 0x12C 4. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_4_CLR,Status write 1 to clear for pulse_vpac_out_3_en_pipe_done_4" "0,1" newline bitfld.long 0x12C 3. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_vpac_out_3_en_pipe_done_3" "0,1" newline bitfld.long 0x12C 2. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_vpac_out_3_en_pipe_done_2" "0,1" newline bitfld.long 0x12C 1. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_vpac_out_3_en_pipe_done_1" "0,1" newline bitfld.long 0x12C 0. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_vpac_out_3_en_pipe_done_0" "0,1" line.long 0x130 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_3_4,Status Clear Register 76" bitfld.long 0x130 31. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_31" "0,1" newline bitfld.long 0x130 30. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_30" "0,1" newline bitfld.long 0x130 29. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_29" "0,1" newline bitfld.long 0x130 28. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_28" "0,1" newline bitfld.long 0x130 27. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_27" "0,1" newline bitfld.long 0x130 26. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_26" "0,1" newline bitfld.long 0x130 25. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_25" "0,1" newline bitfld.long 0x130 24. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_24" "0,1" newline bitfld.long 0x130 23. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_23" "0,1" newline bitfld.long 0x130 22. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_22" "0,1" newline bitfld.long 0x130 21. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_21" "0,1" newline bitfld.long 0x130 20. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_20" "0,1" newline bitfld.long 0x130 19. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_19" "0,1" newline bitfld.long 0x130 18. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_18" "0,1" newline bitfld.long 0x130 17. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_17" "0,1" newline bitfld.long 0x130 16. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_16" "0,1" newline bitfld.long 0x130 15. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_15" "0,1" newline bitfld.long 0x130 14. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_14" "0,1" newline bitfld.long 0x130 13. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_13" "0,1" newline bitfld.long 0x130 12. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_12" "0,1" newline bitfld.long 0x130 11. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_11" "0,1" newline bitfld.long 0x130 10. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_10" "0,1" newline bitfld.long 0x130 9. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_9" "0,1" newline bitfld.long 0x130 8. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_8" "0,1" newline bitfld.long 0x130 7. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_7" "0,1" newline bitfld.long 0x130 6. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_6" "0,1" newline bitfld.long 0x130 5. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_5" "0,1" newline bitfld.long 0x130 4. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_4" "0,1" newline bitfld.long 0x130 3. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_3" "0,1" newline bitfld.long 0x130 2. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_2" "0,1" newline bitfld.long 0x130 1. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_1" "0,1" newline bitfld.long 0x130 0. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_0" "0,1" line.long 0x134 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_3_5,Status Clear Register 77" bitfld.long 0x134 31. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_31" "0,1" newline bitfld.long 0x134 30. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_30" "0,1" newline bitfld.long 0x134 29. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_29" "0,1" newline bitfld.long 0x134 28. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_28" "0,1" newline bitfld.long 0x134 27. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_27" "0,1" newline bitfld.long 0x134 26. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_26" "0,1" newline bitfld.long 0x134 25. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_25" "0,1" newline bitfld.long 0x134 24. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_24" "0,1" newline bitfld.long 0x134 23. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_23" "0,1" newline bitfld.long 0x134 22. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_22" "0,1" newline bitfld.long 0x134 21. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_21" "0,1" newline bitfld.long 0x134 20. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_20" "0,1" newline bitfld.long 0x134 19. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_19" "0,1" newline bitfld.long 0x134 18. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_18" "0,1" newline bitfld.long 0x134 17. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_17" "0,1" newline bitfld.long 0x134 16. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_16" "0,1" newline bitfld.long 0x134 15. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_15" "0,1" newline bitfld.long 0x134 14. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_14" "0,1" newline bitfld.long 0x134 13. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_13" "0,1" newline bitfld.long 0x134 12. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_12" "0,1" newline bitfld.long 0x134 11. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_11" "0,1" newline bitfld.long 0x134 10. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_10" "0,1" newline bitfld.long 0x134 9. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_9" "0,1" newline bitfld.long 0x134 8. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_8" "0,1" newline bitfld.long 0x134 7. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_7" "0,1" newline bitfld.long 0x134 6. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_6" "0,1" newline bitfld.long 0x134 5. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_5" "0,1" newline bitfld.long 0x134 4. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_4" "0,1" newline bitfld.long 0x134 3. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_3" "0,1" newline bitfld.long 0x134 2. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_2" "0,1" newline bitfld.long 0x134 1. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_1" "0,1" newline bitfld.long 0x134 0. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_0" "0,1" line.long 0x138 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_3_6,Status Clear Register 78" bitfld.long 0x138 31. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_63_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_63" "0,1" newline bitfld.long 0x138 30. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_62_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_62" "0,1" newline bitfld.long 0x138 29. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_61_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_61" "0,1" newline bitfld.long 0x138 28. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_60_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_60" "0,1" newline bitfld.long 0x138 27. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_59_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_59" "0,1" newline bitfld.long 0x138 26. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_58_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_58" "0,1" newline bitfld.long 0x138 25. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_57_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_57" "0,1" newline bitfld.long 0x138 24. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_56_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_56" "0,1" newline bitfld.long 0x138 23. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_55_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_55" "0,1" newline bitfld.long 0x138 22. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_54_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_54" "0,1" newline bitfld.long 0x138 21. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_53_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_53" "0,1" newline bitfld.long 0x138 20. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_52_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_52" "0,1" newline bitfld.long 0x138 19. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_51_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_51" "0,1" newline bitfld.long 0x138 18. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_50_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_50" "0,1" newline bitfld.long 0x138 17. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_49_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_49" "0,1" newline bitfld.long 0x138 16. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_48_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_48" "0,1" newline bitfld.long 0x138 15. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_47_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_47" "0,1" newline bitfld.long 0x138 14. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_46_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_46" "0,1" newline bitfld.long 0x138 13. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_45_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_45" "0,1" newline bitfld.long 0x138 12. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_44_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_44" "0,1" newline bitfld.long 0x138 11. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_43_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_43" "0,1" newline bitfld.long 0x138 10. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_42_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_42" "0,1" newline bitfld.long 0x138 9. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_41_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_41" "0,1" newline bitfld.long 0x138 8. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_40_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_40" "0,1" newline bitfld.long 0x138 7. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_39_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_39" "0,1" newline bitfld.long 0x138 6. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_38_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_38" "0,1" newline bitfld.long 0x138 5. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_37_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_37" "0,1" newline bitfld.long 0x138 4. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_36_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_36" "0,1" newline bitfld.long 0x138 3. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_35_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_35" "0,1" newline bitfld.long 0x138 2. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_34_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_34" "0,1" newline bitfld.long 0x138 1. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_33_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_33" "0,1" newline bitfld.long 0x138 0. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_32_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_32" "0,1" line.long 0x13C "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_3_7,Status Clear Register 79" bitfld.long 0x13C 4. "STATUS_PULSE_VPAC_OUT_3_CTM_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ctm_pulse" "0,1" newline bitfld.long 0x13C 3. "STATUS_PULSE_VPAC_OUT_3_UTC1_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_prot_err" "0,1" newline bitfld.long 0x13C 2. "STATUS_PULSE_VPAC_OUT_3_UTC0_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_prot_err" "0,1" newline bitfld.long 0x13C 1. "STATUS_PULSE_VPAC_OUT_3_UTC1_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_error" "0,1" newline bitfld.long 0x13C 0. "STATUS_PULSE_VPAC_OUT_3_UTC0_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_error" "0,1" line.long 0x140 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_4_0,Status Clear Register 80" bitfld.long 0x140 26. "STATUS_PULSE_VPAC_OUT_4_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x140 25. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x140 24. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x140 23. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x140 22. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x140 21. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x140 20. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x140 19. "STATUS_PULSE_VPAC_OUT_4_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x140 18. "STATUS_PULSE_VPAC_OUT_4_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x140 17. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x140 16. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x140 15. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x140 14. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x140 13. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x140 12. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x140 11. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x140 10. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x140 9. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x140 8. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x140 7. "STATUS_PULSE_VPAC_OUT_4_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x140 6. "STATUS_PULSE_VPAC_OUT_4_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x140 5. "STATUS_PULSE_VPAC_OUT_4_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x140 4. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x140 3. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x140 2. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x140 1. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x140 0. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1" line.long 0x144 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_4_1,Status Clear Register 81" bitfld.long 0x144 8. "STATUS_PULSE_VPAC_OUT_4_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x144 7. "STATUS_PULSE_VPAC_OUT_4_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x144 6. "STATUS_PULSE_VPAC_OUT_4_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x144 5. "STATUS_PULSE_VPAC_OUT_4_LDC0_INT_SZOVF_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x144 4. "STATUS_PULSE_VPAC_OUT_4_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x144 3. "STATUS_PULSE_VPAC_OUT_4_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x144 2. "STATUS_PULSE_VPAC_OUT_4_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x144 1. "STATUS_PULSE_VPAC_OUT_4_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x144 0. "STATUS_PULSE_VPAC_OUT_4_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x148 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_4_2,Status Clear Register 82" bitfld.long 0x148 10. "STATUS_PULSE_VPAC_OUT_4_NF_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x148 9. "STATUS_PULSE_VPAC_OUT_4_NF_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x148 8. "STATUS_PULSE_VPAC_OUT_4_NF_FRAME_DONE_CLR,Status write 1 to clear for pulse_vpac_out_4_en_nf_frame_done" "0,1" newline bitfld.long 0x148 3. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x148 2. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x148 1. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for pulse_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x148 0. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for pulse_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x14C "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_4_3,Status Clear Register 83" bitfld.long 0x14C 26. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for pulse_vpac_out_4_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x14C 25. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for pulse_vpac_out_4_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x14C 24. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for pulse_vpac_out_4_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x14C 22. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for pulse_vpac_out_4_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x14C 20. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_vpac_out_4_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x14C 15. "STATUS_PULSE_VPAC_OUT_4_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_vpac_out_4_en_spare_dec_1" "0,1" newline bitfld.long 0x14C 14. "STATUS_PULSE_VPAC_OUT_4_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_vpac_out_4_en_spare_dec_0" "0,1" newline bitfld.long 0x14C 13. "STATUS_PULSE_VPAC_OUT_4_TDONE_6_CLR,Status write 1 to clear for pulse_vpac_out_4_en_tdone_6" "0,1" newline bitfld.long 0x14C 12. "STATUS_PULSE_VPAC_OUT_4_TDONE_5_CLR,Status write 1 to clear for pulse_vpac_out_4_en_tdone_5" "0,1" newline bitfld.long 0x14C 11. "STATUS_PULSE_VPAC_OUT_4_TDONE_4_CLR,Status write 1 to clear for pulse_vpac_out_4_en_tdone_4" "0,1" newline bitfld.long 0x14C 9. "STATUS_PULSE_VPAC_OUT_4_TDONE_2_CLR,Status write 1 to clear for pulse_vpac_out_4_en_tdone_2" "0,1" newline bitfld.long 0x14C 7. "STATUS_PULSE_VPAC_OUT_4_TDONE_0_CLR,Status write 1 to clear for pulse_vpac_out_4_en_tdone_0" "0,1" newline bitfld.long 0x14C 6. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_6_CLR,Status write 1 to clear for pulse_vpac_out_4_en_pipe_done_6" "0,1" newline bitfld.long 0x14C 5. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_5_CLR,Status write 1 to clear for pulse_vpac_out_4_en_pipe_done_5" "0,1" newline bitfld.long 0x14C 4. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_4_CLR,Status write 1 to clear for pulse_vpac_out_4_en_pipe_done_4" "0,1" newline bitfld.long 0x14C 3. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_vpac_out_4_en_pipe_done_3" "0,1" newline bitfld.long 0x14C 2. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_vpac_out_4_en_pipe_done_2" "0,1" newline bitfld.long 0x14C 1. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_vpac_out_4_en_pipe_done_1" "0,1" newline bitfld.long 0x14C 0. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_vpac_out_4_en_pipe_done_0" "0,1" line.long 0x150 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_4_4,Status Clear Register 84" bitfld.long 0x150 31. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_31" "0,1" newline bitfld.long 0x150 30. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_30" "0,1" newline bitfld.long 0x150 29. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_29" "0,1" newline bitfld.long 0x150 28. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_28" "0,1" newline bitfld.long 0x150 27. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_27" "0,1" newline bitfld.long 0x150 26. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_26" "0,1" newline bitfld.long 0x150 25. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_25" "0,1" newline bitfld.long 0x150 24. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_24" "0,1" newline bitfld.long 0x150 23. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_23" "0,1" newline bitfld.long 0x150 22. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_22" "0,1" newline bitfld.long 0x150 21. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_21" "0,1" newline bitfld.long 0x150 20. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_20" "0,1" newline bitfld.long 0x150 19. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_19" "0,1" newline bitfld.long 0x150 18. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_18" "0,1" newline bitfld.long 0x150 17. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_17" "0,1" newline bitfld.long 0x150 16. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_16" "0,1" newline bitfld.long 0x150 15. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_15" "0,1" newline bitfld.long 0x150 14. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_14" "0,1" newline bitfld.long 0x150 13. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_13" "0,1" newline bitfld.long 0x150 12. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_12" "0,1" newline bitfld.long 0x150 11. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_11" "0,1" newline bitfld.long 0x150 10. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_10" "0,1" newline bitfld.long 0x150 9. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_9" "0,1" newline bitfld.long 0x150 8. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_8" "0,1" newline bitfld.long 0x150 7. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_7" "0,1" newline bitfld.long 0x150 6. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_6" "0,1" newline bitfld.long 0x150 5. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_5" "0,1" newline bitfld.long 0x150 4. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_4" "0,1" newline bitfld.long 0x150 3. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_3" "0,1" newline bitfld.long 0x150 2. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_2" "0,1" newline bitfld.long 0x150 1. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_1" "0,1" newline bitfld.long 0x150 0. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_0" "0,1" line.long 0x154 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_4_5,Status Clear Register 85" bitfld.long 0x154 31. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_31" "0,1" newline bitfld.long 0x154 30. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_30" "0,1" newline bitfld.long 0x154 29. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_29" "0,1" newline bitfld.long 0x154 28. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_28" "0,1" newline bitfld.long 0x154 27. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_27" "0,1" newline bitfld.long 0x154 26. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_26" "0,1" newline bitfld.long 0x154 25. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_25" "0,1" newline bitfld.long 0x154 24. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_24" "0,1" newline bitfld.long 0x154 23. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_23" "0,1" newline bitfld.long 0x154 22. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_22" "0,1" newline bitfld.long 0x154 21. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_21" "0,1" newline bitfld.long 0x154 20. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_20" "0,1" newline bitfld.long 0x154 19. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_19" "0,1" newline bitfld.long 0x154 18. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_18" "0,1" newline bitfld.long 0x154 17. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_17" "0,1" newline bitfld.long 0x154 16. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_16" "0,1" newline bitfld.long 0x154 15. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_15" "0,1" newline bitfld.long 0x154 14. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_14" "0,1" newline bitfld.long 0x154 13. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_13" "0,1" newline bitfld.long 0x154 12. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_12" "0,1" newline bitfld.long 0x154 11. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_11" "0,1" newline bitfld.long 0x154 10. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_10" "0,1" newline bitfld.long 0x154 9. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_9" "0,1" newline bitfld.long 0x154 8. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_8" "0,1" newline bitfld.long 0x154 7. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_7" "0,1" newline bitfld.long 0x154 6. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_6" "0,1" newline bitfld.long 0x154 5. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_5" "0,1" newline bitfld.long 0x154 4. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_4" "0,1" newline bitfld.long 0x154 3. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_3" "0,1" newline bitfld.long 0x154 2. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_2" "0,1" newline bitfld.long 0x154 1. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_1" "0,1" newline bitfld.long 0x154 0. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_0" "0,1" line.long 0x158 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_4_6,Status Clear Register 86" bitfld.long 0x158 31. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_63_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_63" "0,1" newline bitfld.long 0x158 30. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_62_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_62" "0,1" newline bitfld.long 0x158 29. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_61_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_61" "0,1" newline bitfld.long 0x158 28. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_60_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_60" "0,1" newline bitfld.long 0x158 27. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_59_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_59" "0,1" newline bitfld.long 0x158 26. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_58_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_58" "0,1" newline bitfld.long 0x158 25. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_57_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_57" "0,1" newline bitfld.long 0x158 24. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_56_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_56" "0,1" newline bitfld.long 0x158 23. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_55_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_55" "0,1" newline bitfld.long 0x158 22. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_54_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_54" "0,1" newline bitfld.long 0x158 21. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_53_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_53" "0,1" newline bitfld.long 0x158 20. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_52_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_52" "0,1" newline bitfld.long 0x158 19. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_51_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_51" "0,1" newline bitfld.long 0x158 18. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_50_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_50" "0,1" newline bitfld.long 0x158 17. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_49_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_49" "0,1" newline bitfld.long 0x158 16. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_48_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_48" "0,1" newline bitfld.long 0x158 15. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_47_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_47" "0,1" newline bitfld.long 0x158 14. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_46_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_46" "0,1" newline bitfld.long 0x158 13. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_45_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_45" "0,1" newline bitfld.long 0x158 12. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_44_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_44" "0,1" newline bitfld.long 0x158 11. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_43_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_43" "0,1" newline bitfld.long 0x158 10. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_42_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_42" "0,1" newline bitfld.long 0x158 9. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_41_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_41" "0,1" newline bitfld.long 0x158 8. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_40_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_40" "0,1" newline bitfld.long 0x158 7. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_39_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_39" "0,1" newline bitfld.long 0x158 6. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_38_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_38" "0,1" newline bitfld.long 0x158 5. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_37_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_37" "0,1" newline bitfld.long 0x158 4. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_36_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_36" "0,1" newline bitfld.long 0x158 3. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_35_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_35" "0,1" newline bitfld.long 0x158 2. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_34_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_34" "0,1" newline bitfld.long 0x158 1. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_33_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_33" "0,1" newline bitfld.long 0x158 0. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_32_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_32" "0,1" line.long 0x15C "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_4_7,Status Clear Register 87" bitfld.long 0x15C 4. "STATUS_PULSE_VPAC_OUT_4_CTM_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ctm_pulse" "0,1" newline bitfld.long 0x15C 3. "STATUS_PULSE_VPAC_OUT_4_UTC1_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_prot_err" "0,1" newline bitfld.long 0x15C 2. "STATUS_PULSE_VPAC_OUT_4_UTC0_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_prot_err" "0,1" newline bitfld.long 0x15C 1. "STATUS_PULSE_VPAC_OUT_4_UTC1_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_error" "0,1" newline bitfld.long 0x15C 0. "STATUS_PULSE_VPAC_OUT_4_UTC0_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_error" "0,1" line.long 0x160 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_5_0,Status Clear Register 88" bitfld.long 0x160 26. "STATUS_PULSE_VPAC_OUT_5_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x160 25. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x160 24. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x160 23. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x160 22. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x160 21. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x160 20. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x160 19. "STATUS_PULSE_VPAC_OUT_5_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x160 18. "STATUS_PULSE_VPAC_OUT_5_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x160 17. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x160 16. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x160 15. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x160 14. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x160 13. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x160 12. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x160 11. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x160 10. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x160 9. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x160 8. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x160 7. "STATUS_PULSE_VPAC_OUT_5_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x160 6. "STATUS_PULSE_VPAC_OUT_5_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x160 5. "STATUS_PULSE_VPAC_OUT_5_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x160 4. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x160 3. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x160 2. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x160 1. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x160 0. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1" line.long 0x164 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_5_1,Status Clear Register 89" bitfld.long 0x164 8. "STATUS_PULSE_VPAC_OUT_5_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x164 7. "STATUS_PULSE_VPAC_OUT_5_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x164 6. "STATUS_PULSE_VPAC_OUT_5_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x164 5. "STATUS_PULSE_VPAC_OUT_5_LDC0_INT_SZOVF_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x164 4. "STATUS_PULSE_VPAC_OUT_5_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x164 3. "STATUS_PULSE_VPAC_OUT_5_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x164 2. "STATUS_PULSE_VPAC_OUT_5_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x164 1. "STATUS_PULSE_VPAC_OUT_5_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x164 0. "STATUS_PULSE_VPAC_OUT_5_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x168 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_5_2,Status Clear Register 90" bitfld.long 0x168 10. "STATUS_PULSE_VPAC_OUT_5_NF_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_nf_sl2_rd_err" "0,1" newline bitfld.long 0x168 9. "STATUS_PULSE_VPAC_OUT_5_NF_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_nf_sl2_wr_err" "0,1" newline bitfld.long 0x168 8. "STATUS_PULSE_VPAC_OUT_5_NF_FRAME_DONE_CLR,Status write 1 to clear for pulse_vpac_out_5_en_nf_frame_done" "0,1" newline bitfld.long 0x168 3. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x168 2. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x168 1. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for pulse_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x168 0. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for pulse_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x16C "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_5_3,Status Clear Register 91" bitfld.long 0x16C 26. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for pulse_vpac_out_5_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x16C 25. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for pulse_vpac_out_5_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x16C 24. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for pulse_vpac_out_5_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x16C 22. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for pulse_vpac_out_5_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x16C 20. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_vpac_out_5_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x16C 15. "STATUS_PULSE_VPAC_OUT_5_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_vpac_out_5_en_spare_dec_1" "0,1" newline bitfld.long 0x16C 14. "STATUS_PULSE_VPAC_OUT_5_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_vpac_out_5_en_spare_dec_0" "0,1" newline bitfld.long 0x16C 13. "STATUS_PULSE_VPAC_OUT_5_TDONE_6_CLR,Status write 1 to clear for pulse_vpac_out_5_en_tdone_6" "0,1" newline bitfld.long 0x16C 12. "STATUS_PULSE_VPAC_OUT_5_TDONE_5_CLR,Status write 1 to clear for pulse_vpac_out_5_en_tdone_5" "0,1" newline bitfld.long 0x16C 11. "STATUS_PULSE_VPAC_OUT_5_TDONE_4_CLR,Status write 1 to clear for pulse_vpac_out_5_en_tdone_4" "0,1" newline bitfld.long 0x16C 9. "STATUS_PULSE_VPAC_OUT_5_TDONE_2_CLR,Status write 1 to clear for pulse_vpac_out_5_en_tdone_2" "0,1" newline bitfld.long 0x16C 7. "STATUS_PULSE_VPAC_OUT_5_TDONE_0_CLR,Status write 1 to clear for pulse_vpac_out_5_en_tdone_0" "0,1" newline bitfld.long 0x16C 6. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_6_CLR,Status write 1 to clear for pulse_vpac_out_5_en_pipe_done_6" "0,1" newline bitfld.long 0x16C 5. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_5_CLR,Status write 1 to clear for pulse_vpac_out_5_en_pipe_done_5" "0,1" newline bitfld.long 0x16C 4. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_4_CLR,Status write 1 to clear for pulse_vpac_out_5_en_pipe_done_4" "0,1" newline bitfld.long 0x16C 3. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_vpac_out_5_en_pipe_done_3" "0,1" newline bitfld.long 0x16C 2. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_vpac_out_5_en_pipe_done_2" "0,1" newline bitfld.long 0x16C 1. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_vpac_out_5_en_pipe_done_1" "0,1" newline bitfld.long 0x16C 0. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_vpac_out_5_en_pipe_done_0" "0,1" line.long 0x170 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_5_4,Status Clear Register 92" bitfld.long 0x170 31. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_31" "0,1" newline bitfld.long 0x170 30. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_30" "0,1" newline bitfld.long 0x170 29. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_29" "0,1" newline bitfld.long 0x170 28. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_28" "0,1" newline bitfld.long 0x170 27. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_27" "0,1" newline bitfld.long 0x170 26. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_26" "0,1" newline bitfld.long 0x170 25. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_25" "0,1" newline bitfld.long 0x170 24. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_24" "0,1" newline bitfld.long 0x170 23. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_23" "0,1" newline bitfld.long 0x170 22. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_22" "0,1" newline bitfld.long 0x170 21. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_21" "0,1" newline bitfld.long 0x170 20. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_20" "0,1" newline bitfld.long 0x170 19. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_19" "0,1" newline bitfld.long 0x170 18. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_18" "0,1" newline bitfld.long 0x170 17. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_17" "0,1" newline bitfld.long 0x170 16. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_16" "0,1" newline bitfld.long 0x170 15. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_15" "0,1" newline bitfld.long 0x170 14. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_14" "0,1" newline bitfld.long 0x170 13. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_13" "0,1" newline bitfld.long 0x170 12. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_12" "0,1" newline bitfld.long 0x170 11. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_11" "0,1" newline bitfld.long 0x170 10. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_10" "0,1" newline bitfld.long 0x170 9. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_9" "0,1" newline bitfld.long 0x170 8. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_8" "0,1" newline bitfld.long 0x170 7. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_7" "0,1" newline bitfld.long 0x170 6. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_6" "0,1" newline bitfld.long 0x170 5. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_5" "0,1" newline bitfld.long 0x170 4. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_4" "0,1" newline bitfld.long 0x170 3. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_3" "0,1" newline bitfld.long 0x170 2. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_2" "0,1" newline bitfld.long 0x170 1. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_1" "0,1" newline bitfld.long 0x170 0. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_0" "0,1" line.long 0x174 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_5_5,Status Clear Register 93" bitfld.long 0x174 31. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_31" "0,1" newline bitfld.long 0x174 30. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_30" "0,1" newline bitfld.long 0x174 29. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_29" "0,1" newline bitfld.long 0x174 28. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_28" "0,1" newline bitfld.long 0x174 27. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_27" "0,1" newline bitfld.long 0x174 26. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_26" "0,1" newline bitfld.long 0x174 25. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_25" "0,1" newline bitfld.long 0x174 24. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_24" "0,1" newline bitfld.long 0x174 23. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_23" "0,1" newline bitfld.long 0x174 22. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_22" "0,1" newline bitfld.long 0x174 21. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_21" "0,1" newline bitfld.long 0x174 20. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_20" "0,1" newline bitfld.long 0x174 19. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_19" "0,1" newline bitfld.long 0x174 18. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_18" "0,1" newline bitfld.long 0x174 17. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_17" "0,1" newline bitfld.long 0x174 16. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_16" "0,1" newline bitfld.long 0x174 15. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_15" "0,1" newline bitfld.long 0x174 14. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_14" "0,1" newline bitfld.long 0x174 13. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_13" "0,1" newline bitfld.long 0x174 12. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_12" "0,1" newline bitfld.long 0x174 11. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_11" "0,1" newline bitfld.long 0x174 10. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_10" "0,1" newline bitfld.long 0x174 9. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_9" "0,1" newline bitfld.long 0x174 8. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_8" "0,1" newline bitfld.long 0x174 7. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_7" "0,1" newline bitfld.long 0x174 6. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_6" "0,1" newline bitfld.long 0x174 5. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_5" "0,1" newline bitfld.long 0x174 4. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_4" "0,1" newline bitfld.long 0x174 3. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_3" "0,1" newline bitfld.long 0x174 2. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_2" "0,1" newline bitfld.long 0x174 1. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_1" "0,1" newline bitfld.long 0x174 0. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_0" "0,1" line.long 0x178 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_5_6,Status Clear Register 94" bitfld.long 0x178 31. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_63_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_63" "0,1" newline bitfld.long 0x178 30. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_62_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_62" "0,1" newline bitfld.long 0x178 29. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_61_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_61" "0,1" newline bitfld.long 0x178 28. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_60_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_60" "0,1" newline bitfld.long 0x178 27. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_59_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_59" "0,1" newline bitfld.long 0x178 26. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_58_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_58" "0,1" newline bitfld.long 0x178 25. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_57_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_57" "0,1" newline bitfld.long 0x178 24. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_56_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_56" "0,1" newline bitfld.long 0x178 23. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_55_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_55" "0,1" newline bitfld.long 0x178 22. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_54_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_54" "0,1" newline bitfld.long 0x178 21. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_53_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_53" "0,1" newline bitfld.long 0x178 20. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_52_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_52" "0,1" newline bitfld.long 0x178 19. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_51_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_51" "0,1" newline bitfld.long 0x178 18. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_50_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_50" "0,1" newline bitfld.long 0x178 17. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_49_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_49" "0,1" newline bitfld.long 0x178 16. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_48_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_48" "0,1" newline bitfld.long 0x178 15. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_47_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_47" "0,1" newline bitfld.long 0x178 14. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_46_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_46" "0,1" newline bitfld.long 0x178 13. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_45_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_45" "0,1" newline bitfld.long 0x178 12. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_44_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_44" "0,1" newline bitfld.long 0x178 11. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_43_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_43" "0,1" newline bitfld.long 0x178 10. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_42_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_42" "0,1" newline bitfld.long 0x178 9. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_41_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_41" "0,1" newline bitfld.long 0x178 8. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_40_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_40" "0,1" newline bitfld.long 0x178 7. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_39_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_39" "0,1" newline bitfld.long 0x178 6. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_38_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_38" "0,1" newline bitfld.long 0x178 5. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_37_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_37" "0,1" newline bitfld.long 0x178 4. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_36_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_36" "0,1" newline bitfld.long 0x178 3. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_35_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_35" "0,1" newline bitfld.long 0x178 2. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_34_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_34" "0,1" newline bitfld.long 0x178 1. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_33_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_33" "0,1" newline bitfld.long 0x178 0. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_32_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_32" "0,1" line.long 0x17C "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_5_7,Status Clear Register 95" bitfld.long 0x17C 4. "STATUS_PULSE_VPAC_OUT_5_CTM_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ctm_pulse" "0,1" newline bitfld.long 0x17C 3. "STATUS_PULSE_VPAC_OUT_5_UTC1_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_prot_err" "0,1" newline bitfld.long 0x17C 2. "STATUS_PULSE_VPAC_OUT_5_UTC0_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_prot_err" "0,1" newline bitfld.long 0x17C 1. "STATUS_PULSE_VPAC_OUT_5_UTC1_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_error" "0,1" newline bitfld.long 0x17C 0. "STATUS_PULSE_VPAC_OUT_5_UTC0_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_error" "0,1" rgroup.long 0xA80++0x2F line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_level_vpac_out_0,Interrupt Vector for level_vpac_out_0" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR_LEVEL_VPAC_OUT_0,Interrupt Vector" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_level_vpac_out_1,Interrupt Vector for level_vpac_out_1" hexmask.long 0x4 0.--31. 1. "INTR_VECTOR_LEVEL_VPAC_OUT_1,Interrupt Vector" line.long 0x8 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_level_vpac_out_2,Interrupt Vector for level_vpac_out_2" hexmask.long 0x8 0.--31. 1. "INTR_VECTOR_LEVEL_VPAC_OUT_2,Interrupt Vector" line.long 0xC "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_level_vpac_out_3,Interrupt Vector for level_vpac_out_3" hexmask.long 0xC 0.--31. 1. "INTR_VECTOR_LEVEL_VPAC_OUT_3,Interrupt Vector" line.long 0x10 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_level_vpac_out_4,Interrupt Vector for level_vpac_out_4" hexmask.long 0x10 0.--31. 1. "INTR_VECTOR_LEVEL_VPAC_OUT_4,Interrupt Vector" line.long 0x14 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_level_vpac_out_5,Interrupt Vector for level_vpac_out_5" hexmask.long 0x14 0.--31. 1. "INTR_VECTOR_LEVEL_VPAC_OUT_5,Interrupt Vector" line.long 0x18 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_pulse_vpac_out_0,Interrupt Vector for pulse_vpac_out_0" hexmask.long 0x18 0.--31. 1. "INTR_VECTOR_PULSE_VPAC_OUT_0,Interrupt Vector" line.long 0x1C "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_pulse_vpac_out_1,Interrupt Vector for pulse_vpac_out_1" hexmask.long 0x1C 0.--31. 1. "INTR_VECTOR_PULSE_VPAC_OUT_1,Interrupt Vector" line.long 0x20 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_pulse_vpac_out_2,Interrupt Vector for pulse_vpac_out_2" hexmask.long 0x20 0.--31. 1. "INTR_VECTOR_PULSE_VPAC_OUT_2,Interrupt Vector" line.long 0x24 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_pulse_vpac_out_3,Interrupt Vector for pulse_vpac_out_3" hexmask.long 0x24 0.--31. 1. "INTR_VECTOR_PULSE_VPAC_OUT_3,Interrupt Vector" line.long 0x28 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_pulse_vpac_out_4,Interrupt Vector for pulse_vpac_out_4" hexmask.long 0x28 0.--31. 1. "INTR_VECTOR_PULSE_VPAC_OUT_4,Interrupt Vector" line.long 0x2C "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_pulse_vpac_out_5,Interrupt Vector for pulse_vpac_out_5" hexmask.long 0x2C 0.--31. 1. "INTR_VECTOR_PULSE_VPAC_OUT_5,Interrupt Vector" tree.end tree "VPAC0_CTSET2_WRAP_CFG_CTSET2_CFG (VPAC0_CTSET2_WRAP_CFG_CTSET2_CFG)" base ad:0x3802000 rgroup.long 0x0++0x3 line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTSETID,CTSET identification register" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old Scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,The value 10b designates this as Processor Business Unit IP" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Function : Indicates a Debug IP (0x2nn) and 0x80 is the identifier for CT-SET" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VERSION,This field changes on bug fix and resets to '0' when either Minor Revision or Major Revision field changes" bitfld.long 0x0 8.--10. "MAJOR_REV,Major Revision. This field changes when there is a major feature change." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device. 0 if non-custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor Revision. This field changes when features are scaled up or down" rgroup.long 0x10++0x3 line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTSETSYSCFG,CTSET system configuration register" hexmask.long 0x0 4.--31. 1. "RESERVED1,Reserved returns 0" bitfld.long 0x0 2.--3. "IDLEMODE,Sets the Idle Mode for CTSET (0=Force Idle 1=No Idle 2=Smart Idle 3= Smart Idle wakeup)" "0: Force Idle,1: No Idle,2: Smart Idle,3: Smart Idle wakeup)" rbitfld.long 0x0 1. "RESERVED,Reserved returns 0" "0,1" newline bitfld.long 0x0 0. "SOFTRESET,This will reset entire CTSET except the registers and the CFG interface. This bit is automatically cleared by hardware. Reads always return 0" "0,1" rgroup.long 0x14++0xB line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_SETSTR,CTSET status register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED1,Reserved returns 0" bitfld.long 0x0 8. "HWFIFOEMPTY,System Event Trace FIFO status 1 is empty 0 means captured data not yet exported" "0,1" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Reserved returns 0" newline bitfld.long 0x0 0. "RESETDONE,Reset status 0 means reset ongoing 1 indicates completed" "0,1" line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_DBGTIMELOW,The 32 low order bits of the debug time value supplied on the time input interface" hexmask.long 0x4 0.--31. 1. "DBGTIME,debug time" line.long 0x8 "CTSET2_WRAP__CFG__CTSET2_CFG_DBGTIMEHI,The 32 high order bits of the debug time value supplied on the time input interface" hexmask.long 0x8 0.--31. 1. "DBGTIME,debug time" rgroup.long 0x24++0x7 line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTSETCFG,The 32 low order bits of the debug time value supplied on the time input interface The 32 high order bits of the debug time value supplied on the time input interface. Reading DBGTIMEHI latches the lower 32 bits of.." hexmask.long.byte 0x0 28.--31. 1. "CLAIM,Claim control and status. To program any bits other than 31 : 28 CTSET ownership must be claimed using bits 31 : 28." hexmask.long.tbyte 0x0 8.--27. 1. "RESERVED2,Reserved returns 0" bitfld.long 0x0 7. "SYSEVENTCAPTEN,When 1 the System event capture is enabled" "0,1" newline rbitfld.long 0x0 5.--6. "RESERVED1,Reserved returns 0" "0,1,2,3" bitfld.long 0x0 4. "EVENTLEVEL,0 enables low level event detection 1 enables high level event detection" "0,1" bitfld.long 0x0 3. "MSGMODE,Message generated based on event detection 0 is sampling window 1 is event detection" "0,1" newline bitfld.long 0x0 2. "STOPCAPT,Stop capturing system events from external trigger detection" "0,1" bitfld.long 0x0 1. "STARTCAPT,Start capturing system events from external trigger detection" "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved returns 0" "0,1" line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_SETSPLREG,System Event Sampling Window register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x4 0.--7. 1. "WINDOWSIZE,System events sampling window size expressed as CTSET cycles" rgroup.long 0x30++0x23 line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL1,System event detection enable register 1" bitfld.long 0x0 31. "EVENT32DETEN,Event(32) Detection Enable" "0,1" bitfld.long 0x0 30. "EVENT31DETEN,Event(31) Detection Enable" "0,1" bitfld.long 0x0 29. "EVENT30DETEN,Event(30) Detection Enable" "0,1" newline bitfld.long 0x0 28. "EVENT29DETEN,Event(29) Detection Enable" "0,1" bitfld.long 0x0 27. "EVENT28DETEN,Event(28) Detection Enable" "0,1" bitfld.long 0x0 26. "EVENT27DETEN,Event(27) Detection Enable" "0,1" newline bitfld.long 0x0 25. "EVENT26DETEN,Event(26) Detection Enable" "0,1" bitfld.long 0x0 24. "EVENT25DETEN,Event(25) Detection Enable" "0,1" bitfld.long 0x0 23. "EVENT24DETEN,Event(24) Detection Enable" "0,1" newline bitfld.long 0x0 22. "EVENT23DETEN,Event(23) Detection Enable" "0,1" bitfld.long 0x0 21. "EVENT22DETEN,Event(22) Detection Enable" "0,1" bitfld.long 0x0 20. "EVENT21DETEN,Event(21) Detection Enable" "0,1" newline bitfld.long 0x0 19. "EVENT20DETEN,Event(20) Detection Enable" "0,1" bitfld.long 0x0 18. "EVENT19DETEN,Event(19) Detection Enable" "0,1" bitfld.long 0x0 17. "EVENT18DETEN,Event(18) Detection Enable" "0,1" newline bitfld.long 0x0 16. "EVENT17DETEN,Event(17) Detection Enable" "0,1" bitfld.long 0x0 15. "EVENT16DETEN,Event(16) Detection Enable" "0,1" bitfld.long 0x0 14. "EVENT15DETEN,Event(15) Detection Enable" "0,1" newline bitfld.long 0x0 13. "EVENT14DETEN,Event(14) Detection Enable" "0,1" bitfld.long 0x0 12. "EVENT13DETEN,Event(13) Detection Enable" "0,1" bitfld.long 0x0 11. "EVENT12DETEN,Event(12) Detection Enable" "0,1" newline bitfld.long 0x0 10. "EVENT11DETEN,Event(11) Detection Enable" "0,1" bitfld.long 0x0 9. "EVENT10DETEN,Event(10) Detection Enable" "0,1" bitfld.long 0x0 8. "EVENT9DETEN,Event(9) Detection Enable" "0,1" newline bitfld.long 0x0 7. "EVENT8DETEN,Event(8) Detection Enable" "0,1" bitfld.long 0x0 6. "EVENT7DETEN,Event(7) Detection Enable" "0,1" bitfld.long 0x0 5. "EVENT6DETEN,Event(6) Detection Enable" "0,1" newline bitfld.long 0x0 4. "EVENT5DETEN,Event(5) Detection Enable" "0,1" bitfld.long 0x0 3. "EVENT4DETEN,Event(4) Detection Enable" "0,1" bitfld.long 0x0 2. "EVENT3DETEN,Event(3) Detection Enable" "0,1" newline bitfld.long 0x0 1. "EVENT2DETEN,Event(2) Detection Enable" "0,1" bitfld.long 0x0 0. "EVENT1DETEN,Event(1) Detection Enable" "0,1" line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL2,System event detection enable register 2 (if number of events > 32)" bitfld.long 0x4 31. "EVENT64DETEN,Event(64) Detection Enable" "0,1" bitfld.long 0x4 30. "EVENT63DETEN,Event(63) Detection Enable" "0,1" bitfld.long 0x4 29. "EVENT62DETEN,Event(62) Detection Enable" "0,1" newline bitfld.long 0x4 28. "EVENT61DETEN,Event(61) Detection Enable" "0,1" bitfld.long 0x4 27. "EVENT60DETEN,Event(60) Detection Enable" "0,1" bitfld.long 0x4 26. "EVENT59DETEN,Event(59) Detection Enable" "0,1" newline bitfld.long 0x4 25. "EVENT58DETEN,Event(58) Detection Enable" "0,1" bitfld.long 0x4 24. "EVENT57DETEN,Event(57) Detection Enable" "0,1" bitfld.long 0x4 23. "EVENT56DETEN,Event(56) Detection Enable" "0,1" newline bitfld.long 0x4 22. "EVENT55DETEN,Event(55) Detection Enable" "0,1" bitfld.long 0x4 21. "EVENT54DETEN,Event(54) Detection Enable" "0,1" bitfld.long 0x4 20. "EVENT53DETEN,Event(53) Detection Enable" "0,1" newline bitfld.long 0x4 19. "EVENT52DETEN,Event(52) Detection Enable" "0,1" bitfld.long 0x4 18. "EVENT51DETEN,Event(51) Detection Enable" "0,1" bitfld.long 0x4 17. "EVENT50DETEN,Event(50) Detection Enable" "0,1" newline bitfld.long 0x4 16. "EVENT49DETEN,Event(49) Detection Enable" "0,1" bitfld.long 0x4 15. "EVENT48DETEN,Event(48) Detection Enable" "0,1" bitfld.long 0x4 14. "EVENT47DETEN,Event(47) Detection Enable" "0,1" newline bitfld.long 0x4 13. "EVENT46DETEN,Event(46) Detection Enable" "0,1" bitfld.long 0x4 12. "EVENT45DETEN,Event(45) Detection Enable" "0,1" bitfld.long 0x4 11. "EVENT44DETEN,Event(44) Detection Enable" "0,1" newline bitfld.long 0x4 10. "EVENT43DETEN,Event(43) Detection Enable" "0,1" bitfld.long 0x4 9. "EVENT42DETEN,Event(42) Detection Enable" "0,1" bitfld.long 0x4 8. "EVENT41DETEN,Event(41) Detection Enable" "0,1" newline bitfld.long 0x4 7. "EVENT40DETEN,Event(40) Detection Enable" "0,1" bitfld.long 0x4 6. "EVENT39DETEN,Event(39) Detection Enable" "0,1" bitfld.long 0x4 5. "EVENT38DETEN,Event(38) Detection Enable" "0,1" newline bitfld.long 0x4 4. "EVENT37DETEN,Event(37) Detection Enable" "0,1" bitfld.long 0x4 3. "EVENT36DETEN,Event(36) Detection Enable" "0,1" bitfld.long 0x4 2. "EVENT35DETEN,Event(35) Detection Enable" "0,1" newline bitfld.long 0x4 1. "EVENT34DETEN,Event(34) Detection Enable" "0,1" bitfld.long 0x4 0. "EVENT33DETEN,Event(33) Detection Enable" "0,1" line.long 0x8 "CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL3,System event detection enable register 3 (if number of events > 64)" bitfld.long 0x8 31. "EVENT96DETEN,Event(96) Detection Enable" "0,1" bitfld.long 0x8 30. "EVENT95DETEN,Event(95) Detection Enable" "0,1" bitfld.long 0x8 29. "EVENT94DETEN,Event(94) Detection Enable" "0,1" newline bitfld.long 0x8 28. "EVENT93DETEN,Event(93) Detection Enable" "0,1" bitfld.long 0x8 27. "EVENT92DETEN,Event(92) Detection Enable" "0,1" bitfld.long 0x8 26. "EVENT91DETEN,Event(91) Detection Enable" "0,1" newline bitfld.long 0x8 25. "EVENT90DETEN,Event(90) Detection Enable" "0,1" bitfld.long 0x8 24. "EVENT89DETEN,Event(89) Detection Enable" "0,1" bitfld.long 0x8 23. "EVENT88DETEN,Event(88) Detection Enable" "0,1" newline bitfld.long 0x8 22. "EVENT87DETEN,Event(87) Detection Enable" "0,1" bitfld.long 0x8 21. "EVENT86DETEN,Event(86) Detection Enable" "0,1" bitfld.long 0x8 20. "EVENT85DETEN,Event(85) Detection Enable" "0,1" newline bitfld.long 0x8 19. "EVENT84DETEN,Event(84) Detection Enable" "0,1" bitfld.long 0x8 18. "EVENT83DETEN,Event(83) Detection Enable" "0,1" bitfld.long 0x8 17. "EVENT82DETEN,Event(82) Detection Enable" "0,1" newline bitfld.long 0x8 16. "EVENT81DETEN,Event(81) Detection Enable" "0,1" bitfld.long 0x8 15. "EVENT80DETEN,Event(80) Detection Enable" "0,1" bitfld.long 0x8 14. "EVENT79DETEN,Event(79) Detection Enable" "0,1" newline bitfld.long 0x8 13. "EVENT78DETEN,Event(78) Detection Enable" "0,1" bitfld.long 0x8 12. "EVENT77DETEN,Event(77) Detection Enable" "0,1" bitfld.long 0x8 11. "EVENT76DETEN,Event(76) Detection Enable" "0,1" newline bitfld.long 0x8 10. "EVENT75DETEN,Event(75) Detection Enable" "0,1" bitfld.long 0x8 9. "EVENT74DETEN,Event(74) Detection Enable" "0,1" bitfld.long 0x8 8. "EVENT73DETEN,Event(73) Detection Enable" "0,1" newline bitfld.long 0x8 7. "EVENT72DETEN,Event(72) Detection Enable" "0,1" bitfld.long 0x8 6. "EVENT71DETEN,Event(71) Detection Enable" "0,1" bitfld.long 0x8 5. "EVENT70DETEN,Event(70) Detection Enable" "0,1" newline bitfld.long 0x8 4. "EVENT69DETEN,Event(69) Detection Enable" "0,1" bitfld.long 0x8 3. "EVENT68DETEN,Event(68) Detection Enable" "0,1" bitfld.long 0x8 2. "EVENT67DETEN,Event(67) Detection Enable" "0,1" newline bitfld.long 0x8 1. "EVENT66DETEN,Event(66) Detection Enable" "0,1" bitfld.long 0x8 0. "EVENT65DETEN,Event(65) Detection Enable" "0,1" line.long 0xC "CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL4,System event detection enable register 4 (if number of events > 96)" bitfld.long 0xC 31. "EVENT128DETEN,Event(128) Detection Enable" "0,1" bitfld.long 0xC 30. "EVENT127DETEN,Event(127) Detection Enable" "0,1" bitfld.long 0xC 29. "EVENT126DETEN,Event(126) Detection Enable" "0,1" newline bitfld.long 0xC 28. "EVENT125DETEN,Event(125) Detection Enable" "0,1" bitfld.long 0xC 27. "EVENT124DETEN,Event(124) Detection Enable" "0,1" bitfld.long 0xC 26. "EVENT123DETEN,Event(123) Detection Enable" "0,1" newline bitfld.long 0xC 25. "EVENT122DETEN,Event(122) Detection Enable" "0,1" bitfld.long 0xC 24. "EVENT121DETEN,Event(121) Detection Enable" "0,1" bitfld.long 0xC 23. "EVENT120DETEN,Event(120) Detection Enable" "0,1" newline bitfld.long 0xC 22. "EVENT119DETEN,Event(119) Detection Enable" "0,1" bitfld.long 0xC 21. "EVENT118DETEN,Event(118) Detection Enable" "0,1" bitfld.long 0xC 20. "EVENT117DETEN,Event(117) Detection Enable" "0,1" newline bitfld.long 0xC 19. "EVENT116DETEN,Event(116) Detection Enable" "0,1" bitfld.long 0xC 18. "EVENT115DETEN,Event(115) Detection Enable" "0,1" bitfld.long 0xC 17. "EVENT114DETEN,Event(114) Detection Enable" "0,1" newline bitfld.long 0xC 16. "EVENT113DETEN,Event(113) Detection Enable" "0,1" bitfld.long 0xC 15. "EVENT112DETEN,Event(112) Detection Enable" "0,1" bitfld.long 0xC 14. "EVENT111DETEN,Event(111) Detection Enable" "0,1" newline bitfld.long 0xC 13. "EVENT110DETEN,Event(110) Detection Enable" "0,1" bitfld.long 0xC 12. "EVENT109DETEN,Event(109) Detection Enable" "0,1" bitfld.long 0xC 11. "EVENT108DETEN,Event(108) Detection Enable" "0,1" newline bitfld.long 0xC 10. "EVENT107DETEN,Event(107) Detection Enable" "0,1" bitfld.long 0xC 9. "EVENT106DETEN,Event(106) Detection Enable" "0,1" bitfld.long 0xC 8. "EVENT105DETEN,Event(105) Detection Enable" "0,1" newline bitfld.long 0xC 7. "EVENT104DETEN,Event(104) Detection Enable" "0,1" bitfld.long 0xC 6. "EVENT103DETEN,Event(103) Detection Enable" "0,1" bitfld.long 0xC 5. "EVENT102DETEN,Event(102) Detection Enable" "0,1" newline bitfld.long 0xC 4. "EVENT101DETEN,Event(101) Detection Enable" "0,1" bitfld.long 0xC 3. "EVENT100DETEN,Event(100) Detection Enable" "0,1" bitfld.long 0xC 2. "EVENT99DETEN,Event(99) Detection Enable" "0,1" newline bitfld.long 0xC 1. "EVENT98DETEN,Event(98) Detection Enable" "0,1" bitfld.long 0xC 0. "EVENT97DETEN,Event(97) Detection Enable" "0,1" line.long 0x10 "CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL5,System event detection enable register 5 (if number of events > 128)" bitfld.long 0x10 31. "EVENT160DETEN,Event(160) Detection Enable" "0,1" bitfld.long 0x10 30. "EVENT159DETEN,Event(159) Detection Enable" "0,1" bitfld.long 0x10 29. "EVENT158DETEN,Event(158) Detection Enable" "0,1" newline bitfld.long 0x10 28. "EVENT157DETEN,Event(157) Detection Enable" "0,1" bitfld.long 0x10 27. "EVENT156DETEN,Event(156) Detection Enable" "0,1" bitfld.long 0x10 26. "EVENT155DETEN,Event(155) Detection Enable" "0,1" newline bitfld.long 0x10 25. "EVENT154DETEN,Event(154) Detection Enable" "0,1" bitfld.long 0x10 24. "EVENT153DETEN,Event(153) Detection Enable" "0,1" bitfld.long 0x10 23. "EVENT152DETEN,Event(152) Detection Enable" "0,1" newline bitfld.long 0x10 22. "EVENT151DETEN,Event(151) Detection Enable" "0,1" bitfld.long 0x10 21. "EVENT150DETEN,Event(150) Detection Enable" "0,1" bitfld.long 0x10 20. "EVENT149DETEN,Event(149) Detection Enable" "0,1" newline bitfld.long 0x10 19. "EVENT148DETEN,Event(148) Detection Enable" "0,1" bitfld.long 0x10 18. "EVENT147DETEN,Event(147) Detection Enable" "0,1" bitfld.long 0x10 17. "EVENT1468DETEN,Event(146) Detection Enable" "0,1" newline bitfld.long 0x10 16. "EVENT145DETEN,Event(145) Detection Enable" "0,1" bitfld.long 0x10 15. "EVENT144DETEN,Event(144) Detection Enable" "0,1" bitfld.long 0x10 14. "EVENT143DETEN,Event(143) Detection Enable" "0,1" newline bitfld.long 0x10 13. "EVENT142DETEN,Event(142) Detection Enable" "0,1" bitfld.long 0x10 12. "EVENT141DETEN,Event(141) Detection Enable" "0,1" bitfld.long 0x10 11. "EVENT140DETEN,Event(140) Detection Enable" "0,1" newline bitfld.long 0x10 10. "EVENT139DETEN,Event(139) Detection Enable" "0,1" bitfld.long 0x10 9. "EVENT138DETEN,Event(138) Detection Enable" "0,1" bitfld.long 0x10 8. "EVENT137DETEN,Event(137) Detection Enable" "0,1" newline bitfld.long 0x10 7. "EVENT136DETEN,Event(136) Detection Enable" "0,1" bitfld.long 0x10 6. "EVENT135DETEN,Event(135) Detection Enable" "0,1" bitfld.long 0x10 5. "EVENT134DETEN,Event(134) Detection Enable" "0,1" newline bitfld.long 0x10 4. "EVENT133DETEN,Event(133) Detection Enable" "0,1" bitfld.long 0x10 3. "EVENT132DETEN,Event(132) Detection Enable" "0,1" bitfld.long 0x10 2. "EVENT131DETEN,Event(131) Detection Enable" "0,1" newline bitfld.long 0x10 1. "EVENT130DETEN,Event(130) Detection Enable" "0,1" bitfld.long 0x10 0. "EVENT129DETEN,Event(129) Detection Enable" "0,1" line.long 0x14 "CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL6,System event detection enable register 6 (if number of events > 160)" bitfld.long 0x14 31. "EVENT192DETEN,Event(192) Detection Enable" "0,1" bitfld.long 0x14 30. "EVENT191DETEN,Event(191) Detection Enable" "0,1" bitfld.long 0x14 29. "EVENT190DETEN,Event(190) Detection Enable" "0,1" newline bitfld.long 0x14 28. "EVENT189DETEN,Event(189) Detection Enable" "0,1" bitfld.long 0x14 27. "EVENT188DETEN,Event(188) Detection Enable" "0,1" bitfld.long 0x14 26. "EVENT187DETEN,Event(187) Detection Enable" "0,1" newline bitfld.long 0x14 25. "EVENT186DETEN,Event(186) Detection Enable" "0,1" bitfld.long 0x14 24. "EVENT185DETEN,Event(185) Detection Enable" "0,1" bitfld.long 0x14 23. "EVENT184DETEN,Event(184) Detection Enable" "0,1" newline bitfld.long 0x14 22. "EVENT183DETEN,Event(183) Detection Enable" "0,1" bitfld.long 0x14 21. "EVENT182DETEN,Event(182) Detection Enable" "0,1" bitfld.long 0x14 20. "EVENT181DETEN,Event(181) Detection Enable" "0,1" newline bitfld.long 0x14 19. "EVENT180DETEN,Event(180) Detection Enable" "0,1" bitfld.long 0x14 18. "EVENT179DETEN,Event(179) Detection Enable" "0,1" bitfld.long 0x14 17. "EVENT178DETEN,Event(178) Detection Enable" "0,1" newline bitfld.long 0x14 16. "EVENT177DETEN,Event(177) Detection Enable" "0,1" bitfld.long 0x14 15. "EVENT176DETEN,Event(176) Detection Enable" "0,1" bitfld.long 0x14 14. "EVENT175DETEN,Event(175) Detection Enable" "0,1" newline bitfld.long 0x14 13. "EVENT174DETEN,Event(174) Detection Enable" "0,1" bitfld.long 0x14 12. "EVENT173DETEN,Event(173) Detection Enable" "0,1" bitfld.long 0x14 11. "EVENT172DETEN,Event(172) Detection Enable" "0,1" newline bitfld.long 0x14 10. "EVENT171DETEN,Event(171) Detection Enable" "0,1" bitfld.long 0x14 9. "EVENT170DETEN,Event(170) Detection Enable" "0,1" bitfld.long 0x14 8. "EVENT169DETEN,Event(169) Detection Enable" "0,1" newline bitfld.long 0x14 7. "EVENT168DETEN,Event(168) Detection Enable" "0,1" bitfld.long 0x14 6. "EVENT167DETEN,Event(167) Detection Enable" "0,1" bitfld.long 0x14 5. "EVENT166DETEN,Event(166) Detection Enable" "0,1" newline bitfld.long 0x14 4. "EVENT165DETEN,Event(165) Detection Enable" "0,1" bitfld.long 0x14 3. "EVENT164DETEN,Event(164) Detection Enable" "0,1" bitfld.long 0x14 2. "EVENT163DETEN,Event(163) Detection Enable" "0,1" newline bitfld.long 0x14 1. "EVENT162DETEN,Event(162) Detection Enable" "0,1" bitfld.long 0x14 0. "EVENT161DETEN,Event(161) Detection Enable" "0,1" line.long 0x18 "CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL7,System event detection enable register 7 (if number of events > 192)" bitfld.long 0x18 31. "EVENT224DETEN,Event(224) Detection Enable" "0,1" bitfld.long 0x18 30. "EVENT223DETEN,Event(223) Detection Enable" "0,1" bitfld.long 0x18 29. "EVENT222DETEN,Event(222) Detection Enable" "0,1" newline bitfld.long 0x18 28. "EVENT221DETEN,Event(221) Detection Enable" "0,1" bitfld.long 0x18 27. "EVENT220DETEN,Event(220) Detection Enable" "0,1" bitfld.long 0x18 26. "EVENT219DETEN,Event(219) Detection Enable" "0,1" newline bitfld.long 0x18 25. "EVENT218DETEN,Event(218) Detection Enable" "0,1" bitfld.long 0x18 24. "EVENT217DETEN,Event(217) Detection Enable" "0,1" bitfld.long 0x18 23. "EVENT216DETEN,Event(216) Detection Enable" "0,1" newline bitfld.long 0x18 22. "EVENT215DETEN,Event(215) Detection Enable" "0,1" bitfld.long 0x18 21. "EVENT214DETEN,Event(214) Detection Enable" "0,1" bitfld.long 0x18 20. "EVENT213DETEN,Event(213) Detection Enable" "0,1" newline bitfld.long 0x18 19. "EVENT212DETEN,Event(212) Detection Enable" "0,1" bitfld.long 0x18 18. "EVENT211DETEN,Event(211) Detection Enable" "0,1" bitfld.long 0x18 17. "EVENT210DETEN,Event(210) Detection Enable" "0,1" newline bitfld.long 0x18 16. "EVENT209DETEN,Event(209) Detection Enable" "0,1" bitfld.long 0x18 15. "EVENT208DETEN,Event(208) Detection Enable" "0,1" bitfld.long 0x18 14. "EVENT207DETEN,Event(207) Detection Enable" "0,1" newline bitfld.long 0x18 13. "EVENT206DETEN,Event(206) Detection Enable" "0,1" bitfld.long 0x18 12. "EVENT205DETEN,Event(205) Detection Enable" "0,1" bitfld.long 0x18 11. "EVENT204DETEN,Event(204) Detection Enable" "0,1" newline bitfld.long 0x18 10. "EVENT203DETEN,Event(203) Detection Enable" "0,1" bitfld.long 0x18 9. "EVENT202DETEN,Event(202) Detection Enable" "0,1" bitfld.long 0x18 8. "EVENT201DETEN,Event(201) Detection Enable" "0,1" newline bitfld.long 0x18 7. "EVENT200DETEN,Event(200) Detection Enable" "0,1" bitfld.long 0x18 6. "EVENT199DETEN,Event(199) Detection Enable" "0,1" bitfld.long 0x18 5. "EVENT198DETEN,Event(198) Detection Enable" "0,1" newline bitfld.long 0x18 4. "EVENT197DETEN,Event(197) Detection Enable" "0,1" bitfld.long 0x18 3. "EVENT196DETEN,Event(196) Detection Enable" "0,1" bitfld.long 0x18 2. "EVENT195DETEN,Event(195) Detection Enable" "0,1" newline bitfld.long 0x18 1. "EVENT194DETEN,Event(194) Detection Enable" "0,1" bitfld.long 0x18 0. "EVENT193DETEN,Event(193) Detection Enable" "0,1" line.long 0x1C "CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL8,System event detection enable register 8 (if number of events > 224)" bitfld.long 0x1C 31. "EVENT256DETEN,Event(256) Detection Enable" "0,1" bitfld.long 0x1C 30. "EVENT255DETEN,Event(255) Detection Enable" "0,1" bitfld.long 0x1C 29. "EVENT254DETEN,Event(254) Detection Enable" "0,1" newline bitfld.long 0x1C 28. "EVENT253DETEN,Event(253) Detection Enable" "0,1" bitfld.long 0x1C 27. "EVENT252DETEN,Event(252) Detection Enable" "0,1" bitfld.long 0x1C 26. "EVENT251DETEN,Event(251) Detection Enable" "0,1" newline bitfld.long 0x1C 25. "EVENT250DETEN,Event(250) Detection Enable" "0,1" bitfld.long 0x1C 24. "EVENT249DETEN,Event(249) Detection Enable" "0,1" bitfld.long 0x1C 23. "EVENT248DETEN,Event(248) Detection Enable" "0,1" newline bitfld.long 0x1C 22. "EVENT247DETEN,Event(247) Detection Enable" "0,1" bitfld.long 0x1C 21. "EVENT246DETEN,Event(246) Detection Enable" "0,1" bitfld.long 0x1C 20. "EVENT245DETEN,Event(245) Detection Enable" "0,1" newline bitfld.long 0x1C 19. "EVENT244DETEN,Event(244) Detection Enable" "0,1" bitfld.long 0x1C 18. "EVENT243DETEN,Event(243) Detection Enable" "0,1" bitfld.long 0x1C 17. "EVENT242DETEN,Event(242) Detection Enable" "0,1" newline bitfld.long 0x1C 16. "EVENT241DETEN,Event(241) Detection Enable" "0,1" bitfld.long 0x1C 15. "EVENT240DETEN,Event(240) Detection Enable" "0,1" bitfld.long 0x1C 14. "EVENT239DETEN,Event(239) Detection Enable" "0,1" newline bitfld.long 0x1C 13. "EVENT238DETEN,Event(238) Detection Enable" "0,1" bitfld.long 0x1C 12. "EVENT237DETEN,Event(237) Detection Enable" "0,1" bitfld.long 0x1C 11. "EVENT236DETEN,Event(236) Detection Enable" "0,1" newline bitfld.long 0x1C 10. "EVENT235DETEN,Event(235) Detection Enable" "0,1" bitfld.long 0x1C 9. "EVENT234DETEN,Event(234) Detection Enable" "0,1" bitfld.long 0x1C 8. "EVENT233DETEN,Event(233) Detection Enable" "0,1" newline bitfld.long 0x1C 7. "EVENT232DETEN,Event(232) Detection Enable" "0,1" bitfld.long 0x1C 6. "EVENT231DETEN,Event(231) Detection Enable" "0,1" bitfld.long 0x1C 5. "EVENT230DETEN,Event(230) Detection Enable" "0,1" newline bitfld.long 0x1C 4. "EVENT229DETEN,Event(229) Detection Enable" "0,1" bitfld.long 0x1C 3. "EVENT228DETEN,Event(228) Detection Enable" "0,1" bitfld.long 0x1C 2. "EVENT227DETEN,Event(227) Detection Enable" "0,1" newline bitfld.long 0x1C 1. "EVENT226DETEN,Event(226) Detection Enable" "0,1" bitfld.long 0x1C 0. "EVENT225DETEN,Event(225) Detection Enable" "0,1" line.long 0x20 "CTSET2_WRAP__CFG__CTSET2_CFG_SETMSTID,System Event Master ID" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x20 0.--7. 1. "MASTID,HW Master ID for System Event module. Software may overwrite the value at any time but this is only recommended for scenarios where top-level configuration errors result in a collision between HW master IDs" rgroup.long 0x800++0x7 line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTL,Counter Timer Control" hexmask.long.byte 0x0 26.--31. 1. "NUMSTM,Number of counters that can export via STM" hexmask.long.byte 0x0 18.--25. 1. "NUMINPT,Number of event input signals" hexmask.long.byte 0x0 13.--17. 1. "NUMTIMR,Number of timers in the module" newline hexmask.long.byte 0x0 7.--12. 1. "NUMCNTR,Number of counters in the module" hexmask.long.byte 0x0 3.--6. 1. "REVID,Revision ID of CTSET" bitfld.long 0x0 1. "RESERVED,Reserved returns 0" "0,1" newline bitfld.long 0x0 0. "NUMCOREMD,Indicated the number of mode bus interfaces 0 is 2 CPU buses 1 is 4 buses" "0,1" line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTNUMDBG,Counter Timer Number Debug Event Register" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x4 0.--2. "NUMEVT,Number of input selectors for debug events" "0,1,2,3,4,5,6,7" rgroup.long 0x808++0x3 line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTUSERACCCTL,Counter Timer User Access Control. can only be written in priviledged mode" hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x0 2. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x0 1. "RUSER,Counter functions while system is in Root-User mode" "0,1" newline bitfld.long 0x0 0. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" rgroup.long 0x820++0x13 line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTSTMCNTL,Counter Timer STM Control register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x0 6.--11. 1. "NUMXPORT,The total number of counters designated for export" rbitfld.long 0x0 5. "XPORTACT,Indicates if a frame is currently being written to the STM." "0,1" newline bitfld.long 0x0 4. "CCMPORT,SW control of CCM message export" "0,1" bitfld.long 0x0 3. "CCMAVAIL,CTSET supports CCM export" "0,1" bitfld.long 0x0 2. "CSMXPORT,SW control of CSM message export" "0,1" newline bitfld.long 0x0 1. "SENDOVR,Send overflow data in CSM frame" "0,1" bitfld.long 0x0 0. "ENBL,CTSET STM global enable for counter/timer messages" "0,1" line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTSTMMSTID,Counter Timer STM Master ID register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x4 0.--7. 1. "MASTID,HW Master ID for System Event module" line.long 0x8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTSTMINTVL,Counter Timer STM Interval Register" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.word 0x8 0.--14. 1. "INTERVAL,Counter Timer Periodic export interval" line.long 0xC "CTSET2_WRAP__CFG__CTSET2_CFG_CTSTMSEL0,Counter Timer STM Counter Select Register 0. This Selects Counter 0 to 31" hexmask.long 0xC 0.--31. 1. "COUNTSEL,The individual bit is this field indicate whether the corresponding counter value is included in the CSM message generated via the STM interface" line.long 0x10 "CTSET2_WRAP__CFG__CTSET2_CFG_CTSTMSEL1,Counter Timer STM Counter Select Register 1. This Selects Counter 32 to 63" hexmask.long 0x10 0.--31. 1. "COUNTSEL,The individual bit is this field indicate whether the corresponding counter value is included in the CSM message generated via the STM interface" rgroup.long 0x840++0x3F line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR0,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x0 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR1,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x4 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR2,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x8 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0xC "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR3,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0xC 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x10 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR4,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x10 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x14 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR5,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x14 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x18 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR6,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x18 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x1C "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR7,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x1C 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x20 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR8,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x20 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x24 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR9,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x24 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x28 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR10,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x28 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x2C "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR11,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x2C 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x30 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR12,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x30 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x34 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR13,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x34 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x38 "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR14,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x38 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x3C "CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR15,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x3C 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" rgroup.long 0x8A0++0x1F line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL0,Timer Interval Register 0. Interval match value for timer 0 in CTSET Timer Interval Register 1. Interval match value for timer 1 in CTSET Timer Interval Register 2. Interval match value for timer 2 in CTSET Timer.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x0 0.--7. 1. "INPSEL,Counter Timer input selection" line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL1,Counter Timer Debug Event Register 1" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x4 0.--7. 1. "INPSEL,Counter Timer input selection" line.long 0x8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL2,Counter Timer Debug Event Register 2" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x8 0.--7. 1. "INPSEL,Counter Timer input selection" line.long 0xC "CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL3,Counter Timer Debug Event Register 3" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0xC 0.--7. 1. "INPSEL,Counter Timer input selection" line.long 0x10 "CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL4,Counter Timer Debug Event Register 4" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x10 0.--7. 1. "INPSEL,Counter Timer input selection" line.long 0x14 "CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL5,Counter Timer Debug Event Register5" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x14 0.--7. 1. "INPSEL,Counter Timer input selection" line.long 0x18 "CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL6,Counter Timer Debug Event Register 6" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x18 0.--7. 1. "INPSEL,Counter Timer input selection" line.long 0x1C "CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL7,Counter Timer Debug Event Register 7" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x1C 0.--7. 1. "INPSEL,Counter Timer input selection" rgroup.long 0x9F0++0x18F line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTGNBL0,Counter Timer Global Enable Register 0. This enables Counter 0 to 31" hexmask.long.byte 0x0 0.--7. 1. "ENABLE,The individual bit is this field enables the corresponding counter. Bits 30 and 31 will be high if global time stamp output interface is enabled" line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTGNBL1,Counter Timer Global Enable Register 1. This enables Counter 32 to 63" hexmask.long.byte 0x4 0.--7. 1. "ENABLE,The individual bit is this field enables the corresponding counter" line.long 0x8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTGRST0,Counter Timer Global Reset Register 0. This resets Counter 0 to 31" hexmask.long.byte 0x8 0.--7. 1. "RESET,The individual bit is this field resets the corresponding counter. These bits are self-clearing once a '1' is written after the counters are reset these bits are cleared. When Global Time Stamp output interface is enabled counter 31 and counter.." line.long 0xC "CTSET2_WRAP__CFG__CTSET2_CFG_CTGRST1,Counter Timer Global Reset Register 0. This resets Counter 32 to 63" hexmask.long.byte 0xC 0.--7. 1. "RESET,The individual bit is this field resets the corresponding counter. These bits are self-clearing once a '1' is written after the counters are reset these bits are cleared." line.long 0x10 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR0,Counter Timer Control Register 0" hexmask.long.byte 0x10 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x10 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x10 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x10 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x10 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x10 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x10 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x10 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x10 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x10 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x10 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x10 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x10 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x10 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x10 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x10 0. "ENBL,Counter enable control" "0,1" line.long 0x14 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR1,Counter Timer Control Register 1" hexmask.long.byte 0x14 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x14 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x14 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x14 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x14 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x14 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x14 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x14 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x14 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x14 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x14 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x14 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x14 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x14 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x14 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x14 0. "ENBL,Counter enable control" "0,1" line.long 0x18 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR2,Counter Timer Control Register 2" hexmask.long.byte 0x18 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x18 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x18 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x18 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x18 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x18 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x18 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x18 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x18 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x18 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x18 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x18 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x18 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x18 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x18 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x18 0. "ENBL,Counter enable control" "0,1" line.long 0x1C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR3,Counter Timer Control Register 3" hexmask.long.byte 0x1C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x1C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x1C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x1C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x1C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x1C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x1C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x1C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x1C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x1C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x1C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x1C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x1C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x1C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x1C 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x1C 0. "ENBL,Counter enable control" "0,1" line.long 0x20 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR4,Counter Timer Control Register 4" hexmask.long.byte 0x20 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x20 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x20 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x20 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x20 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x20 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x20 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x20 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x20 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x20 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x20 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x20 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x20 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x20 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x20 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x20 0. "ENBL,Counter enable control" "0,1" line.long 0x24 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR5,Counter Timer Control Register 5" hexmask.long.byte 0x24 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x24 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x24 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x24 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x24 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x24 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x24 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x24 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x24 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x24 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x24 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x24 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x24 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x24 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x24 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x24 0. "ENBL,Counter enable control" "0,1" line.long 0x28 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR6,Counter Timer Control Register 6" hexmask.long.byte 0x28 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x28 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x28 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x28 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x28 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x28 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x28 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x28 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x28 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x28 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x28 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x28 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x28 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x28 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x28 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x28 0. "ENBL,Counter enable control" "0,1" line.long 0x2C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR7,Counter Timer Control Register 7" hexmask.long.byte 0x2C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x2C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x2C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x2C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x2C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x2C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x2C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x2C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x2C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x2C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x2C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x2C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x2C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x2C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x2C 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x2C 0. "ENBL,Counter enable control" "0,1" line.long 0x30 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR8,Counter Timer Control Register 8" hexmask.long.byte 0x30 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x30 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x30 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x30 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x30 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x30 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x30 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x30 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x30 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x30 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x30 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x30 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x30 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x30 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x30 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x30 0. "ENBL,Counter enable control" "0,1" line.long 0x34 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR9,Counter Timer Control Register 9" hexmask.long.byte 0x34 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x34 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x34 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x34 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x34 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x34 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x34 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x34 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x34 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x34 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x34 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x34 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x34 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x34 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x34 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x34 0. "ENBL,Counter enable control" "0,1" line.long 0x38 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR10,Counter Timer Control Register 10" hexmask.long.byte 0x38 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x38 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x38 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x38 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x38 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x38 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x38 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x38 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x38 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x38 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x38 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x38 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x38 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x38 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x38 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x38 0. "ENBL,Counter enable control" "0,1" line.long 0x3C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR11,Counter Timer Control Register 11" hexmask.long.byte 0x3C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x3C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x3C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x3C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x3C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x3C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x3C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x3C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x3C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x3C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x3C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x3C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x3C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x3C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x3C 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x3C 0. "ENBL,Counter enable control" "0,1" line.long 0x40 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR12,Counter Timer Control Register 12" hexmask.long.byte 0x40 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x40 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x40 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x40 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x40 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x40 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x40 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x40 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x40 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x40 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x40 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x40 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x40 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x40 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x40 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x40 0. "ENBL,Counter enable control" "0,1" line.long 0x44 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR13,Counter Timer Control Register 13" hexmask.long.byte 0x44 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x44 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x44 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x44 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x44 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x44 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x44 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x44 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x44 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x44 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x44 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x44 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x44 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x44 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x44 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x44 0. "ENBL,Counter enable control" "0,1" line.long 0x48 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR14,Counter Timer Control Register 14" hexmask.long.byte 0x48 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x48 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x48 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x48 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x48 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x48 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x48 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x48 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x48 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x48 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x48 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x48 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x48 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x48 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x48 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x48 0. "ENBL,Counter enable control" "0,1" line.long 0x4C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR15,Counter Timer Control Register 15" hexmask.long.byte 0x4C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x4C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x4C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x4C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x4C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x4C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x4C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x4C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x4C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x4C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x4C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x4C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x4C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x4C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x4C 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x4C 0. "ENBL,Counter enable control" "0,1" line.long 0x50 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR16,Counter Timer Control Register 16" hexmask.long.byte 0x50 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x50 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x50 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x50 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x50 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x50 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x50 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x50 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x50 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x50 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x50 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x50 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x50 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x50 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x50 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x50 0. "ENBL,Counter enable control" "0,1" line.long 0x54 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR17,Counter Timer Control Register 17" hexmask.long.byte 0x54 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x54 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x54 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x54 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x54 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x54 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x54 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x54 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x54 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x54 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x54 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x54 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x54 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x54 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x54 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x54 0. "ENBL,Counter enable control" "0,1" line.long 0x58 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR18,Counter Timer Control Register 18" hexmask.long.byte 0x58 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x58 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x58 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x58 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x58 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x58 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x58 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x58 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x58 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x58 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x58 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x58 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x58 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x58 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x58 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x58 0. "ENBL,Counter enable control" "0,1" line.long 0x5C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR19,Counter Timer Control Register 19" hexmask.long.byte 0x5C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x5C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x5C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x5C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x5C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x5C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x5C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x5C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x5C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x5C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x5C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x5C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x5C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x5C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x5C 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x5C 0. "ENBL,Counter enable control" "0,1" line.long 0x60 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR20,Counter Timer Control Register 20" hexmask.long.byte 0x60 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x60 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x60 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x60 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x60 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x60 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x60 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x60 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x60 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x60 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x60 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x60 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x60 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x60 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x60 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x60 0. "ENBL,Counter enable control" "0,1" line.long 0x64 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR21,Counter Timer Control Register 21" hexmask.long.byte 0x64 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x64 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x64 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x64 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x64 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x64 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x64 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x64 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x64 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x64 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x64 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x64 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x64 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x64 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x64 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x64 0. "ENBL,Counter enable control" "0,1" line.long 0x68 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR22,Counter Timer Control Register 22" hexmask.long.byte 0x68 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x68 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x68 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x68 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x68 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x68 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x68 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x68 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x68 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x68 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x68 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x68 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x68 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x68 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x68 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x68 0. "ENBL,Counter enable control" "0,1" line.long 0x6C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR23,Counter Timer Control Register 23" hexmask.long.byte 0x6C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x6C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x6C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x6C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x6C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x6C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x6C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x6C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x6C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x6C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x6C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x6C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x6C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x6C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x6C 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x6C 0. "ENBL,Counter enable control" "0,1" line.long 0x70 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR24,Counter Timer Control Register 24" hexmask.long.byte 0x70 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x70 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x70 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x70 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x70 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x70 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x70 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x70 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x70 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x70 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x70 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x70 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x70 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x70 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x70 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x70 0. "ENBL,Counter enable control" "0,1" line.long 0x74 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR25,Counter Timer Control Register 25" hexmask.long.byte 0x74 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x74 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x74 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x74 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x74 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x74 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x74 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x74 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x74 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x74 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x74 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x74 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x74 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x74 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x74 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x74 0. "ENBL,Counter enable control" "0,1" line.long 0x78 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR26,Counter Timer Control Register 26" hexmask.long.byte 0x78 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x78 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x78 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x78 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x78 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x78 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x78 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x78 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x78 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x78 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x78 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x78 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x78 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x78 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x78 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x78 0. "ENBL,Counter enable control" "0,1" line.long 0x7C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR27,Counter Timer Control Register 27" hexmask.long.byte 0x7C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x7C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x7C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x7C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x7C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x7C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x7C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x7C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x7C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x7C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x7C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x7C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x7C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x7C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x7C 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x7C 0. "ENBL,Counter enable control" "0,1" line.long 0x80 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR28,Counter Timer Control Register 28" hexmask.long.byte 0x80 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x80 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x80 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x80 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x80 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x80 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x80 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x80 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x80 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x80 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x80 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x80 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x80 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x80 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x80 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x80 0. "ENBL,Counter enable control" "0,1" line.long 0x84 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR29,Counter Timer Control Register 29" hexmask.long.byte 0x84 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x84 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x84 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x84 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x84 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x84 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x84 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x84 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x84 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x84 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x84 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x84 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x84 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x84 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x84 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x84 0. "ENBL,Counter enable control" "0,1" line.long 0x88 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR30,Counter Timer Control Register 30" hexmask.long.byte 0x88 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x88 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x88 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x88 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x88 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x88 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x88 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x88 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x88 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x88 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x88 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x88 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x88 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x88 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x88 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x88 0. "ENBL,Counter enable control" "0,1" line.long 0x8C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCR31,Counter Timer Control Register 31" hexmask.long.byte 0x8C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x8C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" bitfld.long 0x8C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" newline bitfld.long 0x8C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" bitfld.long 0x8C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x8C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x8C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x8C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x8C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x8C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" bitfld.long 0x8C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x8C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x8C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x8C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x8C 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x8C 0. "ENBL,Counter enable control" "0,1" line.long 0x90 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN0,Counter/Timer Ownership register 0" bitfld.long 0x90 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0x90 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0x90 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0x90 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x94 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN1,Counter/Timer Ownership register 1" bitfld.long 0x94 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0x94 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0x94 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0x94 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x98 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN2,Counter/Timer Ownership register 2" bitfld.long 0x98 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0x98 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0x98 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0x98 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x9C "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN3,Counter/Timer Ownership register 3" bitfld.long 0x9C 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0x9C 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0x9C 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0x9C 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xA0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN4,Counter/Timer Ownership register 4" bitfld.long 0xA0 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xA0 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xA0 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xA0 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xA4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN5,Counter/Timer Ownership register 5" bitfld.long 0xA4 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xA4 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xA4 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xA4 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xA8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN6,Counter/Timer Ownership register 6" bitfld.long 0xA8 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xA8 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xA8 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xA8 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xAC "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN7,Counter/Timer Ownership register 7" bitfld.long 0xAC 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xAC 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xAC 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xAC 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xB0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN8,Counter/Timer Ownership register 8" bitfld.long 0xB0 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xB0 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xB0 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xB0 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xB4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN9,Counter/Timer Ownership register 9" bitfld.long 0xB4 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xB4 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xB4 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xB4 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xB8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN10,Counter/Timer Ownership register 10" bitfld.long 0xB8 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xB8 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xB8 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xB8 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xBC "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN11,Counter/Timer Ownership register 11" bitfld.long 0xBC 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xBC 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xBC 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xBC 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xC0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN12,Counter/Timer Ownership register 12" bitfld.long 0xC0 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xC0 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xC0 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xC0 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xC4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN13,Counter/Timer Ownership register 13" bitfld.long 0xC4 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xC4 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xC4 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xC4 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xC8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN14,Counter/Timer Ownership register 14" bitfld.long 0xC8 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xC8 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xC8 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xC8 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xCC "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN15,Counter/Timer Ownership register 15" bitfld.long 0xCC 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xCC 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xCC 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xCC 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xD0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN16,Counter/Timer Ownership register 16" bitfld.long 0xD0 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xD0 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xD0 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xD0 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xD4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN17,Counter/Timer Ownership register 17" bitfld.long 0xD4 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xD4 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xD4 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xD4 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xD8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN18,Counter/Timer Ownership register 18" bitfld.long 0xD8 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xD8 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xD8 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xD8 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xDC "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN19,Counter/Timer Ownership register 19" bitfld.long 0xDC 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xDC 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xDC 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xDC 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xE0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN20,Counter/Timer Ownership register 20" bitfld.long 0xE0 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xE0 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xE0 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xE0 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xE4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN21,Counter/Timer Ownership register 21" bitfld.long 0xE4 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xE4 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xE4 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xE4 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xE8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN22,Counter/Timer Ownership register 22" bitfld.long 0xE8 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xE8 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xE8 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xE8 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xEC "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN23,Counter/Timer Ownership register2 3" bitfld.long 0xEC 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xEC 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xEC 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xEC 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xF0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN24,Counter/Timer Ownership register 24" bitfld.long 0xF0 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xF0 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xF0 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xF0 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xF4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN25,Counter/Timer Ownership register 25" bitfld.long 0xF4 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xF4 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xF4 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xF4 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xF8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN26,Counter/Timer Ownership register 26" bitfld.long 0xF8 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xF8 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xF8 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xF8 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xFC "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN27,Counter/Timer Ownership register 27" bitfld.long 0xFC 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0xFC 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0xFC 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0xFC 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x100 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN28,Counter/Timer Ownership register 28" bitfld.long 0x100 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0x100 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0x100 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0x100 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x104 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN29,Counter/Timer Ownership register 29" bitfld.long 0x104 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0x104 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0x104 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0x104 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x108 "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN30,Counter/Timer Ownership register 30" bitfld.long 0x108 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0x108 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0x108 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0x108 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x10C "CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN31,Counter/Timer Ownership register 31" bitfld.long 0x10C 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop)" bitfld.long 0x10C 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" rbitfld.long 0x10C 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" newline hexmask.long 0x10C 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x110 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT0,Counter Timer 0 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x110 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x110 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x110 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x110 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x110 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x110 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x110 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x110 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x110 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x114 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT1,Counter Timer 1 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x114 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x114 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x114 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x114 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x114 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x114 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x114 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x114 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x114 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x118 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT2,Counter Timer 2 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x118 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x118 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x118 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x118 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x118 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x118 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x118 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x118 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x118 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x11C "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT3,Counter Timer 3 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x11C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x11C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x11C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x11C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x11C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x11C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x11C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x11C 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x11C 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x120 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT4,Counter Timer 4 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x120 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x120 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x120 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x120 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x120 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x120 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x120 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x120 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x120 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x124 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT5,Counter Timer 5 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x124 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x124 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x124 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x124 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x124 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x124 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x124 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x124 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x124 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x128 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT6,Counter Timer 6 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x128 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x128 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x128 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x128 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x128 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x128 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x128 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x128 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x128 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x12C "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT7,Counter Timer 7 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x12C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x12C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x12C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x12C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x12C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x12C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x12C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x12C 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x12C 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x130 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT8,Counter Timer 8 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x130 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x130 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x130 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x130 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x130 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x130 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x130 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x130 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x130 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x134 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT9,Counter Timer 9 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x134 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x134 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x134 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x134 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x134 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x134 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x134 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x134 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x134 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x138 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT10,Counter Timer 10 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x138 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x138 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x138 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x138 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x138 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x138 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x138 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x138 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x138 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x13C "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT11,Counter Timer 11 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x13C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x13C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x13C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x13C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x13C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x13C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x13C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x13C 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x13C 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x140 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT12,Counter Timer 12 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x140 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x140 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x140 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x140 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x140 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x140 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x140 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x140 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x140 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x144 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT13,Counter Timer 13 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x144 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x144 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x144 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x144 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x144 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x144 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x144 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x144 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x144 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x148 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT14,Counter Timer 14 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x148 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x148 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x148 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x148 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x148 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x148 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x148 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x148 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x148 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x14C "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT15,Counter Timer 15 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x14C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x14C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x14C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x14C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x14C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x14C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x14C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x14C 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x14C 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x150 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT16,Counter Timer 16 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x150 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x150 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x150 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x150 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x150 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x150 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x150 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x150 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x150 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x154 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT17,Counter Timer 17 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x154 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x154 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x154 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x154 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x154 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x154 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x154 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x154 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x154 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x158 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT18,Counter Timer 18 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x158 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x158 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x158 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x158 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x158 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x158 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x158 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x158 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x158 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x15C "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT19,Counter Timer 19 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x15C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x15C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x15C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x15C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x15C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x15C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x15C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x15C 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x15C 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x160 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT20,Counter Timer 20 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x160 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x160 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x160 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x160 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x160 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x160 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x160 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x160 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x160 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x164 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT21,Counter Timer 21 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x164 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x164 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x164 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x164 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x164 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x164 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x164 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x164 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x164 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x168 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT22,Counter Timer 22 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x168 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x168 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x168 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x168 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x168 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x168 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x168 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x168 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x168 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x16C "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT23,Counter Timer 23 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x16C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x16C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x16C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x16C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x16C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x16C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x16C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x16C 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x16C 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x170 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT24,Counter Timer 24 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x170 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x170 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x170 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x170 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x170 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x170 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x170 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x170 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x170 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x174 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT25,Counter Timer 25 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x174 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x174 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x174 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x174 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x174 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x174 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x174 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x174 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x174 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x178 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT26,Counter Timer 26 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x178 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x178 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x178 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x178 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x178 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x178 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x178 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x178 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x178 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x17C "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT27,Counter Timer 27 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x17C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x17C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x17C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x17C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x17C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x17C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x17C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x17C 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x17C 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x180 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT28,Counter Timer 28 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x180 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x180 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x180 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x180 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x180 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x180 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x180 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x180 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x180 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x184 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT29,Counter Timer 29 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x184 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x184 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x184 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x184 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x184 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x184 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x184 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x184 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x184 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x188 "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT30,Counter Timer 30 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x188 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x188 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x188 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x188 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x188 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x188 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x188 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x188 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x188 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x18C "CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT31,Counter Timer 31 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x18C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x18C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" bitfld.long 0x18C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x18C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" bitfld.long 0x18C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x18C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x18C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x18C 1. "IDLE,Counter functions while system/core is in idle" "0,1" bitfld.long 0x18C 0. "FREE,Counter functions while system/core is halted" "0,1" rgroup.long 0xB80++0x7F line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR0,Counter Timer Counter Register 0" hexmask.long 0x0 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR1,Counter Timer Counter Register 1" hexmask.long 0x4 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR2,Counter Timer Counter Register 2" hexmask.long 0x8 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0xC "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR3,Counter Timer Counter Register 3" hexmask.long 0xC 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x10 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR4,Counter Timer Counter Register 4" hexmask.long 0x10 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x14 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR5,Counter Timer Counter Register 5" hexmask.long 0x14 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x18 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR6,Counter Timer Counter Register 6" hexmask.long 0x18 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x1C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR7,Counter Timer Counter Register 7" hexmask.long 0x1C 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x20 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR8,Counter Timer Counter Register 8" hexmask.long 0x20 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x24 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR9,Counter Timer Counter Register 9" hexmask.long 0x24 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x28 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR10,Counter Timer Counter Register 10" hexmask.long 0x28 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x2C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR11,Counter Timer Counter Register 11" hexmask.long 0x2C 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x30 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR12,Counter Timer Counter Register 12" hexmask.long 0x30 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x34 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR13,Counter Timer Counter Register 13" hexmask.long 0x34 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x38 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR14,Counter Timer Counter Register 14" hexmask.long 0x38 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x3C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR15,Counter Timer Counter Register 15" hexmask.long 0x3C 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x40 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR16,Counter Timer Counter Register 16" hexmask.long 0x40 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x44 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR17,Counter Timer Counter Register 17" hexmask.long 0x44 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x48 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR18,Counter Timer Counter Register 18" hexmask.long 0x48 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x4C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR19,Counter Timer Counter Register 19" hexmask.long 0x4C 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x50 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR20,Counter Timer Counter Register 20" hexmask.long 0x50 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x54 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR21,Counter Timer Counter Register 21" hexmask.long 0x54 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x58 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR22,Counter Timer Counter Register 22" hexmask.long 0x58 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x5C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR23,Counter Timer Counter Register 23" hexmask.long 0x5C 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x60 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR24,Counter Timer Counter Register 24" hexmask.long 0x60 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x64 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR25,Counter Timer Counter Register 25" hexmask.long 0x64 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x68 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR26,Counter Timer Counter Register 26" hexmask.long 0x68 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x6C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR27,Counter Timer Counter Register 27" hexmask.long 0x6C 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x70 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR28,Counter Timer Counter Register 28" hexmask.long 0x70 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x74 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR29,Counter Timer Counter Register 29" hexmask.long 0x74 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x78 "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR30,Counter Timer Counter Register 30" hexmask.long 0x78 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x7C "CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR31,Counter Timer Counter Register 31" hexmask.long 0x7C 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." rgroup.long 0xC00++0x13 line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_CT_EOI,Counter Timer EOI Register. This register is the End of Interrupt used by SW to signal HW that an interrupt event service is complete and an interrupt can be rearmed. This register exists only if NUMTIMR > 0" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x0 0. "EOI,EOI value" "0,1" line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_CTIRQSTAT_RAW,Counter Timer IRQSTATUS RAW Register. This register indicates the raw status of the interrupt. It can be written by SW for testing. This register exists only if NUMTIMR > 0" hexmask.long 0x4 0.--31. 1. "TIM_INTN_IRQ,IRQSTATUS_RAW value. The individual bits is this field correspond to individual interrupts generated for each timer associated with Counter Timer Control Register (CTCRn : INT)." line.long 0x8 "CTSET2_WRAP__CFG__CTSET2_CFG_CTIRQSTAT,Counter Timer IRQSTATUS Register. This bit clears the interrupt event. SW can also read this bit to indicate that the interrupt is active and enabled. This register exists only if NUMTIMR > 0" hexmask.long 0x8 0.--31. 1. "TIM_INTN_IE,IRQSTATUS value. The individual bits is this field correspond to individual interrupts generated for each timer associated with Counter Timer Control Register (CTCRn : INT)." line.long 0xC "CTSET2_WRAP__CFG__CTSET2_CFG_CTIRQENABLE_SET,Counter Timer IRQENABLE_SET Register. This register is to enable generation of Interrupt Event used by SW. This register exists only if NUMTIMR > 0" hexmask.long 0xC 0.--31. 1. "TIM_INTN_IES,IRQSET value. This bit sets the enable of the interrupt event. SW can also read this bit to determine if the interrupt is enabled. The individual bits is this field correspond to individual interrupts generated for each timer associated with.." line.long 0x10 "CTSET2_WRAP__CFG__CTSET2_CFG_CTIRQENABLE_CLR,Counter Timer IRQENABLE_CLR Register. This register is to disable generation of Interrupt Event used by SW. This register exists only if NUMTIMR > 0" hexmask.long 0x10 0.--31. 1. "TIM_INTN_IEC,IRQCLR value. This bit clears the enable of the interrupt event. SW can also read this bit to determine if the interrupt is enabled. The individual bits is this field correspond to individual interrupts generated for each timer associated.." rgroup.long 0x1800++0x7 line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_STPTCR,STP Trace Control Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED3,Reserved returns 0" rbitfld.long 0x0 24. "MOD_FIFOFULL,STPMI2ATB internal MID packet fifo is full" "0,1" rbitfld.long 0x0 23. "DATA_FIFOFULL,STPMI2ATB internal Data packet fifo is full" "0,1" newline hexmask.long.tbyte 0x0 6.--22. 1. "RESERVED2,Reserved returns 0" bitfld.long 0x0 5. "COMPEN,Compression of Data enable" "0,1" rbitfld.long 0x0 3.--4. "RESERVED1,Reserved returns 0" "0,1,2,3" newline rbitfld.long 0x0 2. "SYNCEN,The value 1 indicates STPASYNC is supported" "0,1" bitfld.long 0x0 1. "TSEN,Timestamp Enable. This bit is static and should not be changed dynamically. This should be changed before client is enabled." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved returns 0" "0,1" line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_STPTID,STP Trace ID Register" hexmask.long 0x4 7.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x4 0.--6. 1. "TRACEID,Trace ID value. Software may overwrite the value at any time but this is only recommended for scenarios where top-level configuration errors result in a collision between HW master IDs" rgroup.long 0x1810++0x7 line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_STPASYNC,STP Synchronization Control Register" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x0 12. "EXPMODE,Exponent mode A value of 1 sets count to 2 to the Nth where Nth is ((bits 11 : 8)+12). A value of 0 sets Count to N (bits 11 : 0)" "0,1" hexmask.long.word 0x0 0.--11. 1. "COUNT,The number of bytes between Synchronization packets" line.long 0x4 "CTSET2_WRAP__CFG__CTSET2_CFG_STPFFCR,STP Flush Control Register" hexmask.long 0x4 6.--31. 1. "RESERVED1,Reserved returns 0" bitfld.long 0x4 5. "FORCEFLUSH,Write a 1 to force a flush automatically clears after the operation is complete" "0,1" rbitfld.long 0x4 2.--4. "RESERVED,Reserved returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 1. "ASYNCPE,Async Priority Enable. 0 indicates ASYNC packet priority is lower than trace. 1 indicates priority escalates on second synchronization request" "0,1" bitfld.long 0x4 0. "AUTOFLUSH,Auto flush enable. When set on every complete data (ATDATA : WIDTH) in the fifo written data is exported out when ATREADY is asserted. This should be written before client IP enabled" "0,1" rgroup.long 0x1818++0x3 line.long 0x0 "CTSET2_WRAP__CFG__CTSET2_CFG_STPFEAT1,STP Features 1 Register" hexmask.long.byte 0x0 27.--31. 1. "STP_RTLVER,RTL Version. Reset each time major or minor version is updated" bitfld.long 0x0 24.--26. "STP_MAJVER,Functional Major Version. This is the first version of STPMI2ATB" "0,1,2,3,4,5,6,7" bitfld.long 0x0 22.--23. "STP_CUSTVER,Custom Version (not used)" "0,1,2,3" newline hexmask.long.byte 0x0 17.--21. 1. "STP_MINVER,Functional Minor Version" hexmask.long.word 0x0 8.--16. 1. "RESERVED,Reserved returns 0" bitfld.long 0x0 4.--6. "VERSION,STP2.0 Time Stamp Value of 011 indicates Natural binary timestamp a value of 100 indicates gray binary timestamps" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "PROT,Protocol Revision. Value of 0001 indicates STP 2.0" tree.end tree "VPAC0_DRU_UTC" tree "VPAC0_DRU_UTC_VPAC0" tree "VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU (VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU)" base ad:0x3A00000 rgroup.quad 0x0++0xF line.quad 0x0 "DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_dru_pid,Peripheral ID Register" bitfld.quad 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.quad 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.quad.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.quad.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.quad 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.quad 0x8 "DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_dru_capabilities,DRU Capabilities: Lists the capabilities of the channel for TR TYPE and formatting functions" bitfld.quad 0x8 48. "VCOMP,The DRU supports video compression mode" "0,1" bitfld.quad 0x8 47. "ACOMP,The DRU supports analytic compression mode" "0,1" hexmask.quad.byte 0x8 43.--46. 1. "SECTR,Maximum second TR function that is supported" hexmask.quad.byte 0x8 39.--42. 1. "DFMT,Maximum data reformatting function that is supported" newline hexmask.quad.byte 0x8 35.--38. 1. "ELTYPE,Maximum element type value that is supported" bitfld.quad 0x8 32.--34. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1,2,3,4,5,6,7" hexmask.quad.word 0x8 20.--31. 1. "RSVD_CONF_SPEC,Reserved for Configuration Specific Features. This implementation has no configuration specific features." bitfld.quad 0x8 19. "GLOBAL_TRIG,Global Triggers 0 and 1 are supported" "0,1" newline bitfld.quad 0x8 18. "LOCAL_TRIG,Dedicated Local Trigger is supported" "0,1" bitfld.quad 0x8 17. "EOL,EOL Field is supported" "0,1" bitfld.quad 0x8 16. "TRSTATIC,STATIC Field is supported" "0,1" bitfld.quad 0x8 15. "TYPE15,Type 15 TR is supported" "0,1" newline bitfld.quad 0x8 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.quad 0x8 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.quad 0x8 12. "TYPE12,Type 12 TR is supported" "0,1" bitfld.quad 0x8 11. "TYPE11,Type 11 TR is supported" "0,1" newline bitfld.quad 0x8 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.quad 0x8 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.quad 0x8 8. "TYPE8,Type 8 TR is supported" "0,1" bitfld.quad 0x8 7. "TYPE7,Type 7 TR is supported" "0,1" newline bitfld.quad 0x8 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.quad 0x8 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.quad 0x8 4. "TYPE4,Type 4 TR is supported" "0,1" bitfld.quad 0x8 3. "TYPE3,Type 3 TR is supported" "0,1" newline bitfld.quad 0x8 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.quad 0x8 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.quad 0x8 0. "TYPE0,Type 0 TR is supported" "0,1" rgroup.quad 0x40++0x7 line.quad 0x0 "DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_dru_pri_mask0,DRU Priority Masks: Enables locking a buffer to be used only by the priority queues" bitfld.quad 0x0 63. "MASK63,Buffer 63 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 62. "MASK62,Buffer 62 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 61. "MASK61,Buffer 61 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 60. "MASK60,Buffer 60 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 59. "MASK59,Buffer 59 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 58. "MASK58,Buffer 58 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 57. "MASK57,Buffer 57 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 56. "MASK56,Buffer 56 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 55. "MASK55,Buffer 55 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 54. "MASK54,Buffer 54 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 53. "MASK53,Buffer 53 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 52. "MASK52,Buffer 52 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 51. "MASK51,Buffer 51 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 50. "MASK50,Buffer 50 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 49. "MASK49,Buffer 49 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 48. "MASK48,Buffer 48 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 47. "MASK47,Buffer 47 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 46. "MASK46,Buffer 46 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 45. "MASK45,Buffer 45 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 44. "MASK44,Buffer 44 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 43. "MASK43,Buffer 43 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 42. "MASK42,Buffer 42 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 41. "MASK41,Buffer 41 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 40. "MASK40,Buffer 40 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 39. "MASK39,Buffer 39 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 38. "MASK38,Buffer 38 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 37. "MASK37,Buffer 37 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 36. "MASK36,Buffer 36 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 35. "MASK35,Buffer 35 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 34. "MASK34,Buffer 34 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 33. "MASK33,Buffer 33 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 32. "MASK32,Buffer 32 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 31. "MASK31,Buffer 31 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 30. "MASK30,Buffer 30 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 29. "MASK29,Buffer 29 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 28. "MASK28,Buffer 28 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 27. "MASK27,Buffer 27 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 26. "MASK26,Buffer 26 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 25. "MASK25,Buffer 25 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 24. "MASK24,Buffer 24 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 23. "MASK23,Buffer 23 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 22. "MASK22,Buffer 22 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 21. "MASK21,Buffer 21 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 20. "MASK20,Buffer 20 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 19. "MASK19,Buffer 19 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 18. "MASK18,Buffer 18 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 17. "MASK17,Buffer 17 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 16. "MASK16,Buffer 16 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 15. "MASK15,Buffer 15 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 14. "MASK14,Buffer 14 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 13. "MASK13,Buffer 13 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 12. "MASK12,Buffer 12 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 11. "MASK11,Buffer 11 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 10. "MASK10,Buffer 10 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 9. "MASK9,Buffer 9 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 8. "MASK8,Buffer 8 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 7. "MASK7,Buffer 7 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 6. "MASK6,Buffer 6 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 5. "MASK5,Buffer 5 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 4. "MASK4,Buffer 4 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 3. "MASK3,Buffer 3 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 2. "MASK2,Buffer 2 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 1. "MASK1,Buffer 1 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 0. "MASK0,Buffer 0 can only be used by the Priority queue if set to 1." "0,1" tree.end tree "VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CAUSE (VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CAUSE)" base ad:0x3AE0000 rgroup.quad 0x0++0x7 line.quad 0x0 "DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CAUSE_cause,Error Register cause for channels 0 to 15" bitfld.quad 0x0 63. "R_ERR15,Masked error bit for Tx channel n+15" "0,1" bitfld.quad 0x0 62. "R_PEND15,Masked completion ring pending bit for Rx channel n+15" "0,1" bitfld.quad 0x0 61. "T_ERR15,Masked error bit for Tx channel n+15" "0,1" bitfld.quad 0x0 60. "T_PEND15,Masked completion ring pending bit for Tx channel n+15" "0,1" bitfld.quad 0x0 59. "R_ERR14,Masked error bit for Tx channel n+14" "0,1" bitfld.quad 0x0 58. "R_PEND14,Masked completion ring pending bit for Rx channel n+14" "0,1" bitfld.quad 0x0 57. "T_ERR14,Masked error bit for Tx channel n+14" "0,1" newline bitfld.quad 0x0 56. "T_PEND14,Masked completion ring pending bit for Tx channel n+14" "0,1" bitfld.quad 0x0 55. "R_ERR13,Masked error bit for Tx channel n+13" "0,1" bitfld.quad 0x0 54. "R_PEND13,Masked completion ring pending bit for Rx channel n+13" "0,1" bitfld.quad 0x0 53. "T_ERR13,Masked error bit for Tx channel n+13" "0,1" bitfld.quad 0x0 52. "T_PEND13,Masked completion ring pending bit for Tx channel n+13" "0,1" bitfld.quad 0x0 51. "R_ERR12,Masked error bit for Tx channel n+12" "0,1" bitfld.quad 0x0 50. "R_PEND12,Masked completion ring pending bit for Rx channel n+12" "0,1" newline bitfld.quad 0x0 49. "T_ERR12,Masked error bit for Tx channel n+12" "0,1" bitfld.quad 0x0 48. "T_PEND12,Masked completion ring pending bit for Tx channel n+12" "0,1" bitfld.quad 0x0 47. "R_ERR11,Masked error bit for Tx channel n+11" "0,1" bitfld.quad 0x0 46. "R_PEND11,Masked completion ring pending bit for Rx channel n+11" "0,1" bitfld.quad 0x0 45. "T_ERR11,Masked error bit for Tx channel n+11" "0,1" bitfld.quad 0x0 44. "T_PEND11,Masked completion ring pending bit for Tx channel n+11" "0,1" bitfld.quad 0x0 43. "R_ERR10,Masked error bit for Tx channel n+10" "0,1" newline bitfld.quad 0x0 42. "R_PEND10,Masked completion ring pending bit for Rx channel n+10" "0,1" bitfld.quad 0x0 41. "T_ERR10,Masked error bit for Tx channel n+10" "0,1" bitfld.quad 0x0 40. "T_PEND10,Masked completion ring pending bit for Tx channel n+10" "0,1" bitfld.quad 0x0 39. "R_ERR9,Masked error bit for Tx channel n+9" "0,1" bitfld.quad 0x0 38. "R_PEND9,Masked completion ring pending bit for Rx channel n+9" "0,1" bitfld.quad 0x0 37. "T_ERR9,Masked error bit for Tx channel n+9" "0,1" bitfld.quad 0x0 36. "T_PEND9,Masked completion ring pending bit for Tx channel n+9" "0,1" newline bitfld.quad 0x0 35. "R_ERR8,Masked error bit for Tx channel n+8" "0,1" bitfld.quad 0x0 34. "R_PEND8,Masked completion ring pending bit for Rx channel n+8" "0,1" bitfld.quad 0x0 33. "T_ERR8,Masked error bit for Tx channel n+8" "0,1" bitfld.quad 0x0 32. "T_PEND8,Masked completion ring pending bit for Tx channel n+8" "0,1" bitfld.quad 0x0 31. "R_ERR7,Masked error bit for Tx channel n+7" "0,1" bitfld.quad 0x0 30. "R_PEND7,Masked completion ring pending bit for Rx channel n+7" "0,1" bitfld.quad 0x0 29. "T_ERR7,Masked error bit for Tx channel n+7" "0,1" newline bitfld.quad 0x0 28. "T_PEND7,Masked completion ring pending bit for Tx channel n+7" "0,1" bitfld.quad 0x0 27. "R_ERR6,Masked error bit for Tx channel n+6" "0,1" bitfld.quad 0x0 26. "R_PEND6,Masked completion ring pending bit for Rx channel n+6" "0,1" bitfld.quad 0x0 25. "T_ERR6,Masked error bit for Tx channel n+6" "0,1" bitfld.quad 0x0 24. "T_PEND6,Masked completion ring pending bit for Tx channel n+6" "0,1" bitfld.quad 0x0 23. "R_ERR5,Masked error bit for Tx channel n+5" "0,1" bitfld.quad 0x0 22. "R_PEND5,Masked completion ring pending bit for Rx channel n+5" "0,1" newline bitfld.quad 0x0 21. "T_ERR5,Masked error bit for Tx channel n+5" "0,1" bitfld.quad 0x0 20. "T_PEND5,Masked completion ring pending bit for Tx channel n+5" "0,1" bitfld.quad 0x0 19. "R_ERR4,Masked error bit for Tx channel n+4" "0,1" bitfld.quad 0x0 18. "R_PEND4,Masked completion ring pending bit for Rx channel n+4" "0,1" bitfld.quad 0x0 17. "T_ERR4,Masked error bit for Tx channel n+4" "0,1" bitfld.quad 0x0 16. "T_PEND4,Masked completion ring pending bit for Tx channel n+4" "0,1" bitfld.quad 0x0 15. "R_ERR3,Masked error bit for Tx channel n+3" "0,1" newline bitfld.quad 0x0 14. "R_PEND3,Masked completion ring pending bit for Rx channel n+3" "0,1" bitfld.quad 0x0 13. "T_ERR3,Masked error bit for Tx channel n+3" "0,1" bitfld.quad 0x0 12. "T_PEND3,Masked completion ring pending bit for Tx channel n+3" "0,1" bitfld.quad 0x0 11. "R_ERR2,Masked error bit for Tx channel n+2" "0,1" bitfld.quad 0x0 10. "R_PEND2,Masked completion ring pending bit for Rx channel n+2" "0,1" bitfld.quad 0x0 9. "T_ERR2,Masked error bit for Tx channel n+2" "0,1" bitfld.quad 0x0 8. "T_PEND2,Masked completion ring pending bit for Tx channel n+2" "0,1" newline bitfld.quad 0x0 7. "R_ERR1,Masked error bit for Tx channel n+1" "0,1" bitfld.quad 0x0 6. "R_PEND1,Masked completion ring pending bit for Rx channel n+1" "0,1" bitfld.quad 0x0 5. "T_ERR1,Masked error bit for Tx channel n+1" "0,1" bitfld.quad 0x0 4. "T_PEND1,Masked completion ring pending bit for Tx channel n+1" "0,1" bitfld.quad 0x0 3. "R_ERR0,Masked error bit for Tx channel n" "0,1" bitfld.quad 0x0 2. "R_PEND0,Masked completion ring pending bit for Rx channel n" "0,1" bitfld.quad 0x0 1. "T_ERR0,Masked error bit for Tx channel n" "0,1" newline bitfld.quad 0x0 0. "T_PEND0,Masked completion ring pending bit for Tx channel n" "0,1" tree.end tree "VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHNRT (VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHNRT)" base ad:0x3A40000 rgroup.quad 0x0++0x7 line.quad 0x0 "DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHNRT_cfg,Channel Configuration Register. The Channel Configuration Register is used to initialize static mode settings for the DMA Channel. The register may only be written when the chanel is disable in the.." bitfld.quad 0x0 31. "PAUSE_ON_ERR,Pause on Error. This field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW to.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." bitfld.quad 0x0 19. "CHAN_TYPE_OWNER,This field controls how the TR is received by the UTC. If it is 0 then the SUBMISSION registers must be written to submit it. If it is a 1 then the TR will be received through PSIL." "0,1" newline rbitfld.quad 0x0 16.--18. "CHAN_TYPE,This field states the TR type that is being used it along with CHAN_TYPE_OWNER field make up the 4 bit CHAN_TYPE for a KS3 DMA UTC. The value of this is all zeroes. To reflect that the UTC DRU only does TRs through pass by value mechanisms." "0,1,2,3,4,5,6,7" rgroup.quad 0x20++0x7 line.quad 0x0 "DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHNRT_choes0,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number.." hexmask.quad.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated." rgroup.quad 0x60++0x7 line.quad 0x0 "DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHNRT_chst_sched,Channel Static Scheduler Config Register" bitfld.quad 0x0 0.--2. "QUEUE,This is the queue number that is written" "0,1,2,3,4,5,6,7" tree.end tree "VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHRT (VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHRT)" base ad:0x3A60000 rgroup.quad 0x0++0xF line.quad 0x0 "DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHRT_chrt_ctl,The channel realtime control register contains real-time cotrol and status information for the DMA Channel. The fields in this regsiter can be changed while the channel is in operation." bitfld.quad 0x0 31. "ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared.." newline bitfld.quad 0x0 30. "TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" newline bitfld.quad 0x0 29. "PAUSE,Channel pause: Setting this bit will request the channel to pause processing at the next packet boundary. This is a more graceful method of halting processing than disabling the channel as it will not allow any current packets to underflow." "0,1" newline bitfld.quad 0x0 28. "FORCED_TEARDOWN,Channel forced teardown: Setting this bit will request the channel to be torn down forcefulyy. This field will clear after a channel teardown is complete." "0,1" line.quad 0x8 "DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHRT_chrt_swtrig,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way." bitfld.quad 0x8 2. "LOCAL_TRIGGER0,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel. This will trigger LOCAL Event" "0,1" newline bitfld.quad 0x8 1. "GLOBAL_TRIGGER1,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel. This will trigger Global Event 1" "0,1" newline bitfld.quad 0x8 0. "GLOBAL_TRIGGER0,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel. This will trigger Global Event 0" "0,1" rgroup.quad 0x10++0xF line.quad 0x0 "DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHRT_chrt_status_det,The channel status details" bitfld.quad 0x0 63. "CH_ACTIVE,The channel has some active work" "0,1" newline bitfld.quad 0x0 62. "WR_ACTIVE,The top TR has submitted a sub-TR to the write portion of the queue" "0,1" newline bitfld.quad 0x0 61. "RD_ACTIVE,The top TR has submitted a sub-TR to the read portion of the queue" "0,1" newline hexmask.quad.byte 0x0 24.--31. 1. "TR_IN_QUEUE_CNT,The number of TRs for the channel that are in the queue FIFO" newline hexmask.quad.byte 0x0 16.--23. 1. "TR_CNT,The number of TRs in the channel FIFO" newline hexmask.quad.byte 0x0 8.--15. 1. "CMD_ID,The last cmd_id given to the write queue" newline hexmask.quad.byte 0x0 4.--7. 1. "INFO,The info of the error that was received" newline hexmask.quad.byte 0x0 0.--3. 1. "STATUS_TYPE,The type of error that was received" line.quad 0x8 "DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHRT_chrt_status_cnt,The channel count details" hexmask.quad.word 0x8 48.--63. 1. "ICNT3,The last icnt3 given to the write queue" newline hexmask.quad.word 0x8 32.--47. 1. "ICNT2,The last icnt2 given to the write queue" newline hexmask.quad.word 0x8 16.--31. 1. "ICNT1,The last icnt1 given to the write queue" newline hexmask.quad.word 0x8 0.--15. 1. "ICNT0,The last icnt0 given to the write queue" tree.end tree "VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_QUEUE (VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_QUEUE)" base ad:0x3A08000 rgroup.quad 0x0++0x7 line.quad 0x0 "DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_QUEUE_cfg,Configuration Register for Queue 0" hexmask.quad.long 0x0 32.--63. 1. "RSVD,Reserved." hexmask.quad.byte 0x0 24.--31. 1. "REARB_WAIT,This is the number of commands that will be sent by other queues before allowing the queue to arbitrate again for the right to send commands. This is only started when a queue exhausted its consecutive trans count." hexmask.quad.byte 0x0 16.--23. 1. "CONSECUTIVE_TRANS,This is the number of consecutive transactions that will be sent before allowing another queue of equal level to arbitrate to send commands. This is the maximum number of commands that it can send. If the queue has any delays such as.." newline bitfld.quad 0x0 8.--10. "QOS,This configures the QOS for QUEUE0. This should only be set for fixed priority queues and the lower queue should have the lower QoS." "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x0 4.--7. 1. "ORDERID,This configures the orderid for QUEUE0." bitfld.quad 0x0 0.--2. "PRI,This configures the priority for QUEUE0. This will be the priority that will be presented on the External bus for all commands from this queue." "0,1,2,3,4,5,6,7" rgroup.quad 0x40++0x7 line.quad 0x0 "DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_QUEUE_status,Status Register for Queue 0" hexmask.quad.word 0x0 27.--35. 1. "RD_TOTAL,This is the channel that the read half is currently working on." hexmask.quad.word 0x0 18.--26. 1. "RD_TOP,This is the channel that the read half is currently working on." hexmask.quad.word 0x0 9.--17. 1. "WR_TOTAL,This is the channel that the read half is currently working on." newline hexmask.quad.word 0x0 0.--8. 1. "WR_TOP,This is the channel that the write half is currently working on." tree.end tree "VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_SET (VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_SET)" base ad:0x3A04000 rgroup.quad 0x0++0x7 line.quad 0x0 "DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_SET_dru_shared_evt_set,DRU Shared Event Set Register" bitfld.quad 0x0 0. "PROT_ERR,Set the Prot Error event" "0,1" rgroup.quad 0x40++0x7 line.quad 0x0 "DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_SET_dru_comp_evt_set0,DRU Completion Event Set Register" bitfld.quad 0x0 31. "COMP_EVT31,Set the Completion Event for channel 31" "0,1" bitfld.quad 0x0 30. "COMP_EVT30,Set the Completion Event for channel 30" "0,1" bitfld.quad 0x0 29. "COMP_EVT29,Set the Completion Event for channel 29" "0,1" bitfld.quad 0x0 28. "COMP_EVT28,Set the Completion Event for channel 28" "0,1" bitfld.quad 0x0 27. "COMP_EVT27,Set the Completion Event for channel 27" "0,1" newline bitfld.quad 0x0 26. "COMP_EVT26,Set the Completion Event for channel 26" "0,1" bitfld.quad 0x0 25. "COMP_EVT25,Set the Completion Event for channel 25" "0,1" bitfld.quad 0x0 24. "COMP_EVT24,Set the Completion Event for channel 24" "0,1" bitfld.quad 0x0 23. "COMP_EVT23,Set the Completion Event for channel 23" "0,1" bitfld.quad 0x0 22. "COMP_EVT22,Set the Completion Event for channel 22" "0,1" newline bitfld.quad 0x0 21. "COMP_EVT21,Set the Completion Event for channel 21" "0,1" bitfld.quad 0x0 20. "COMP_EVT20,Set the Completion Event for channel 20" "0,1" bitfld.quad 0x0 19. "COMP_EVT19,Set the Completion Event for channel 19" "0,1" bitfld.quad 0x0 18. "COMP_EVT18,Set the Completion Event for channel 18" "0,1" bitfld.quad 0x0 17. "COMP_EVT17,Set the Completion Event for channel 17" "0,1" newline bitfld.quad 0x0 16. "COMP_EVT16,Set the Completion Event for channel 16" "0,1" bitfld.quad 0x0 15. "COMP_EVT15,Set the Completion Event for channel 15" "0,1" bitfld.quad 0x0 14. "COMP_EVT14,Set the Completion Event for channel 14" "0,1" bitfld.quad 0x0 13. "COMP_EVT13,Set the Completion Event for channel 13" "0,1" bitfld.quad 0x0 12. "COMP_EVT12,Set the Completion Event for channel 12" "0,1" newline bitfld.quad 0x0 11. "COMP_EVT11,Set the Completion Event for channel 11" "0,1" bitfld.quad 0x0 10. "COMP_EVT10,Set the Completion Event for channel 10" "0,1" bitfld.quad 0x0 9. "COMP_EVT9,Set the Completion Event for channel 9" "0,1" bitfld.quad 0x0 8. "COMP_EVT8,Set the Completion Event for channel 8" "0,1" bitfld.quad 0x0 7. "COMP_EVT7,Set the Completion Event for channel 7" "0,1" newline bitfld.quad 0x0 6. "COMP_EVT6,Set the Completion Event for channel 6" "0,1" bitfld.quad 0x0 5. "COMP_EVT5,Set the Completion Event for channel 5" "0,1" bitfld.quad 0x0 4. "COMP_EVT4,Set the Completion Event for channel 4" "0,1" bitfld.quad 0x0 3. "COMP_EVT3,Set the Completion Event for channel 3" "0,1" bitfld.quad 0x0 2. "COMP_EVT2,Set the Completion Event for channel 2" "0,1" newline bitfld.quad 0x0 1. "COMP_EVT1,Set the Completion Event for channel 1" "0,1" bitfld.quad 0x0 0. "COMP_EVT0,Set the Completion Event for channel 0" "0,1" rgroup.quad 0x80++0x7 line.quad 0x0 "DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_SET_dru_err_evt_set0,DRU Error Event Set Register" bitfld.quad 0x0 31. "ERR_EVT31,Set the Error Event for channel 31" "0,1" bitfld.quad 0x0 30. "ERR_EVT30,Set the Error Event for channel 30" "0,1" bitfld.quad 0x0 29. "ERR_EVT29,Set the Error Event for channel 29" "0,1" bitfld.quad 0x0 28. "ERR_EVT28,Set the Error Event for channel 28" "0,1" bitfld.quad 0x0 27. "ERR_EVT27,Set the Error Event for channel 27" "0,1" newline bitfld.quad 0x0 26. "ERR_EVT26,Set the Error Event for channel 26" "0,1" bitfld.quad 0x0 25. "ERR_EVT25,Set the Error Event for channel 25" "0,1" bitfld.quad 0x0 24. "ERR_EVT24,Set the Error Event for channel 24" "0,1" bitfld.quad 0x0 23. "ERR_EVT23,Set the Error Event for channel 23" "0,1" bitfld.quad 0x0 22. "ERR_EVT22,Set the Error Event for channel 22" "0,1" newline bitfld.quad 0x0 21. "ERR_EVT21,Set the Error Event for channel 21" "0,1" bitfld.quad 0x0 20. "ERR_EVT20,Set the Error Event for channel 20" "0,1" bitfld.quad 0x0 19. "ERR_EVT19,Set the Error Event for channel 19" "0,1" bitfld.quad 0x0 18. "ERR_EVT18,Set the Error Event for channel 18" "0,1" bitfld.quad 0x0 17. "ERR_EVT17,Set the Error Event for channel 17" "0,1" newline bitfld.quad 0x0 16. "ERR_EVT16,Set the Error Event for channel 16" "0,1" bitfld.quad 0x0 15. "ERR_EVT15,Set the Error Event for channel 15" "0,1" bitfld.quad 0x0 14. "ERR_EVT14,Set the Error Event for channel 14" "0,1" bitfld.quad 0x0 13. "ERR_EVT13,Set the Error Event for channel 13" "0,1" bitfld.quad 0x0 12. "ERR_EVT12,Set the Error Event for channel 12" "0,1" newline bitfld.quad 0x0 11. "ERR_EVT11,Set the Error Event for channel 11" "0,1" bitfld.quad 0x0 10. "ERR_EVT10,Set the Error Event for channel 10" "0,1" bitfld.quad 0x0 9. "ERR_EVT9,Set the Error Event for channel 9" "0,1" bitfld.quad 0x0 8. "ERR_EVT8,Set the Error Event for channel 8" "0,1" bitfld.quad 0x0 7. "ERR_EVT7,Set the Error Event for channel 7" "0,1" newline bitfld.quad 0x0 6. "ERR_EVT6,Set the Error Event for channel 6" "0,1" bitfld.quad 0x0 5. "ERR_EVT5,Set the Error Event for channel 5" "0,1" bitfld.quad 0x0 4. "ERR_EVT4,Set the Error Event for channel 4" "0,1" bitfld.quad 0x0 3. "ERR_EVT3,Set the Error Event for channel 3" "0,1" bitfld.quad 0x0 2. "ERR_EVT2,Set the Error Event for channel 2" "0,1" newline bitfld.quad 0x0 1. "ERR_EVT1,Set the Error Event for channel 1" "0,1" bitfld.quad 0x0 0. "ERR_EVT0,Set the Error Event for channel 0" "0,1" rgroup.quad 0xC0++0x7 line.quad 0x0 "DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_SET_dru_local_evt_set0,DRU Local Event Set Register" bitfld.quad 0x0 31. "COMP_EVT31,Set the Local Event for channel 31" "0,1" bitfld.quad 0x0 30. "COMP_EVT30,Set the Local Event for channel 30" "0,1" bitfld.quad 0x0 29. "COMP_EVT29,Set the Local Event for channel 29" "0,1" bitfld.quad 0x0 28. "COMP_EVT28,Set the Local Event for channel 28" "0,1" bitfld.quad 0x0 27. "COMP_EVT27,Set the Local Event for channel 27" "0,1" newline bitfld.quad 0x0 26. "COMP_EVT26,Set the Local Event for channel 26" "0,1" bitfld.quad 0x0 25. "COMP_EVT25,Set the Local Event for channel 25" "0,1" bitfld.quad 0x0 24. "COMP_EVT24,Set the Local Event for channel 24" "0,1" bitfld.quad 0x0 23. "COMP_EVT23,Set the Local Event for channel 23" "0,1" bitfld.quad 0x0 22. "COMP_EVT22,Set the Local Event for channel 22" "0,1" newline bitfld.quad 0x0 21. "COMP_EVT21,Set the Local Event for channel 21" "0,1" bitfld.quad 0x0 20. "COMP_EVT20,Set the Local Event for channel 20" "0,1" bitfld.quad 0x0 19. "COMP_EVT19,Set the Local Event for channel 19" "0,1" bitfld.quad 0x0 18. "COMP_EVT18,Set the Local Event for channel 18" "0,1" bitfld.quad 0x0 17. "COMP_EVT17,Set the Local Event for channel 17" "0,1" newline bitfld.quad 0x0 16. "COMP_EVT16,Set the Local Event for channel 16" "0,1" bitfld.quad 0x0 15. "COMP_EVT15,Set the Local Event for channel 15" "0,1" bitfld.quad 0x0 14. "COMP_EVT14,Set the Local Event for channel 14" "0,1" bitfld.quad 0x0 13. "COMP_EVT13,Set the Local Event for channel 13" "0,1" bitfld.quad 0x0 12. "COMP_EVT12,Set the Local Event for channel 12" "0,1" newline bitfld.quad 0x0 11. "COMP_EVT11,Set the Local Event for channel 11" "0,1" bitfld.quad 0x0 10. "COMP_EVT10,Set the Local Event for channel 10" "0,1" bitfld.quad 0x0 9. "COMP_EVT9,Set the Local Event for channel 9" "0,1" bitfld.quad 0x0 8. "COMP_EVT8,Set the Local Event for channel 8" "0,1" bitfld.quad 0x0 7. "COMP_EVT7,Set the Local Event for channel 7" "0,1" newline bitfld.quad 0x0 6. "COMP_EVT6,Set the Local Event for channel 6" "0,1" bitfld.quad 0x0 5. "COMP_EVT5,Set the Local Event for channel 5" "0,1" bitfld.quad 0x0 4. "COMP_EVT4,Set the Local Event for channel 4" "0,1" bitfld.quad 0x0 3. "COMP_EVT3,Set the Local Event for channel 3" "0,1" bitfld.quad 0x0 2. "COMP_EVT2,Set the Local Event for channel 2" "0,1" newline bitfld.quad 0x0 1. "COMP_EVT1,Set the Local Event for channel 1" "0,1" bitfld.quad 0x0 0. "COMP_EVT0,Set the Local Event for channel 0" "0,1" tree.end tree.end tree "VPAC0_DRU_UTC_VPAC1" tree "VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU (VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU)" base ad:0x3B00000 rgroup.quad 0x0++0xF line.quad 0x0 "DRU_UTC_VPAC1__DRU_MMR_CFG__DRU_DRU_DRU_dru_pid,Peripheral ID Register" bitfld.quad 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.quad 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.quad.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.quad.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.quad 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.quad 0x8 "DRU_UTC_VPAC1__DRU_MMR_CFG__DRU_DRU_DRU_dru_capabilities,DRU Capabilities: Lists the capabilities of the channel for TR TYPE and formatting functions" hexmask.quad.byte 0x8 43.--46. 1. "SECTR,Maximum second TR function that is supported" hexmask.quad.byte 0x8 39.--42. 1. "DFMT,Maximum data reformatting function that is supported" hexmask.quad.byte 0x8 35.--38. 1. "ELTYPE,Maximum element type value that is supported" bitfld.quad 0x8 32.--34. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x8 20.--31. 1. "RSVD_CONF_SPEC,Reserved for Configuration Specific Features. This implementation has no configuration specific features." bitfld.quad 0x8 19. "GLOBAL_TRIG,Global Triggers 0 and 1 are supported" "0,1" bitfld.quad 0x8 18. "LOCAL_TRIG,Dedicated Local Trigger is supported" "0,1" bitfld.quad 0x8 17. "EOL,EOL Field is supported" "0,1" newline bitfld.quad 0x8 16. "TRSTATIC,STATIC Field is supported" "0,1" bitfld.quad 0x8 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.quad 0x8 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.quad 0x8 13. "TYPE13,Type 13 TR is supported" "0,1" newline bitfld.quad 0x8 12. "TYPE12,Type 12 TR is supported" "0,1" bitfld.quad 0x8 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.quad 0x8 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.quad 0x8 9. "TYPE9,Type 9 TR is supported" "0,1" newline bitfld.quad 0x8 8. "TYPE8,Type 8 TR is supported" "0,1" bitfld.quad 0x8 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.quad 0x8 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.quad 0x8 5. "TYPE5,Type 5 TR is supported" "0,1" newline bitfld.quad 0x8 4. "TYPE4,Type 4 TR is supported" "0,1" bitfld.quad 0x8 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.quad 0x8 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.quad 0x8 1. "TYPE1,Type 1 TR is supported" "0,1" newline bitfld.quad 0x8 0. "TYPE0,Type 0 TR is supported" "0,1" rgroup.quad 0x40++0x7 line.quad 0x0 "DRU_UTC_VPAC1__DRU_MMR_CFG__DRU_DRU_DRU_dru_pri_mask0,DRU Priority Masks: Enables locking a buffer to be used only by the priority queues" bitfld.quad 0x0 63. "MASK63,Buffer 63 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 62. "MASK62,Buffer 62 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 61. "MASK61,Buffer 61 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 60. "MASK60,Buffer 60 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 59. "MASK59,Buffer 59 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 58. "MASK58,Buffer 58 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 57. "MASK57,Buffer 57 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 56. "MASK56,Buffer 56 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 55. "MASK55,Buffer 55 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 54. "MASK54,Buffer 54 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 53. "MASK53,Buffer 53 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 52. "MASK52,Buffer 52 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 51. "MASK51,Buffer 51 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 50. "MASK50,Buffer 50 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 49. "MASK49,Buffer 49 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 48. "MASK48,Buffer 48 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 47. "MASK47,Buffer 47 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 46. "MASK46,Buffer 46 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 45. "MASK45,Buffer 45 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 44. "MASK44,Buffer 44 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 43. "MASK43,Buffer 43 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 42. "MASK42,Buffer 42 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 41. "MASK41,Buffer 41 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 40. "MASK40,Buffer 40 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 39. "MASK39,Buffer 39 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 38. "MASK38,Buffer 38 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 37. "MASK37,Buffer 37 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 36. "MASK36,Buffer 36 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 35. "MASK35,Buffer 35 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 34. "MASK34,Buffer 34 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 33. "MASK33,Buffer 33 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 32. "MASK32,Buffer 32 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 31. "MASK31,Buffer 31 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 30. "MASK30,Buffer 30 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 29. "MASK29,Buffer 29 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 28. "MASK28,Buffer 28 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 27. "MASK27,Buffer 27 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 26. "MASK26,Buffer 26 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 25. "MASK25,Buffer 25 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 24. "MASK24,Buffer 24 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 23. "MASK23,Buffer 23 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 22. "MASK22,Buffer 22 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 21. "MASK21,Buffer 21 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 20. "MASK20,Buffer 20 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 19. "MASK19,Buffer 19 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 18. "MASK18,Buffer 18 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 17. "MASK17,Buffer 17 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 16. "MASK16,Buffer 16 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 15. "MASK15,Buffer 15 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 14. "MASK14,Buffer 14 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 13. "MASK13,Buffer 13 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 12. "MASK12,Buffer 12 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 11. "MASK11,Buffer 11 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 10. "MASK10,Buffer 10 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 9. "MASK9,Buffer 9 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 8. "MASK8,Buffer 8 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 7. "MASK7,Buffer 7 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 6. "MASK6,Buffer 6 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 5. "MASK5,Buffer 5 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 4. "MASK4,Buffer 4 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 3. "MASK3,Buffer 3 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 2. "MASK2,Buffer 2 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 1. "MASK1,Buffer 1 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 0. "MASK0,Buffer 0 can only be used by the Priority queue if set to 1." "0,1" tree.end tree "VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CAUSE (VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CAUSE)" base ad:0x3BE0000 rgroup.quad 0x0++0x7 line.quad 0x0 "DRU_UTC_VPAC1__DRU_MMR_CFG__DRU_DRU_DRU_CAUSE_cause,Error Register cause for channels 0 to 15" bitfld.quad 0x0 63. "R_ERR15,Masked error bit for Tx channel n+15" "0,1" bitfld.quad 0x0 62. "R_PEND15,Masked completion ring pending bit for Rx channel n+15" "0,1" bitfld.quad 0x0 61. "T_ERR15,Masked error bit for Tx channel n+15" "0,1" bitfld.quad 0x0 60. "T_PEND15,Masked completion ring pending bit for Tx channel n+15" "0,1" bitfld.quad 0x0 59. "R_ERR14,Masked error bit for Tx channel n+14" "0,1" bitfld.quad 0x0 58. "R_PEND14,Masked completion ring pending bit for Rx channel n+14" "0,1" bitfld.quad 0x0 57. "T_ERR14,Masked error bit for Tx channel n+14" "0,1" newline bitfld.quad 0x0 56. "T_PEND14,Masked completion ring pending bit for Tx channel n+14" "0,1" bitfld.quad 0x0 55. "R_ERR13,Masked error bit for Tx channel n+13" "0,1" bitfld.quad 0x0 54. "R_PEND13,Masked completion ring pending bit for Rx channel n+13" "0,1" bitfld.quad 0x0 53. "T_ERR13,Masked error bit for Tx channel n+13" "0,1" bitfld.quad 0x0 52. "T_PEND13,Masked completion ring pending bit for Tx channel n+13" "0,1" bitfld.quad 0x0 51. "R_ERR12,Masked error bit for Tx channel n+12" "0,1" bitfld.quad 0x0 50. "R_PEND12,Masked completion ring pending bit for Rx channel n+12" "0,1" newline bitfld.quad 0x0 49. "T_ERR12,Masked error bit for Tx channel n+12" "0,1" bitfld.quad 0x0 48. "T_PEND12,Masked completion ring pending bit for Tx channel n+12" "0,1" bitfld.quad 0x0 47. "R_ERR11,Masked error bit for Tx channel n+11" "0,1" bitfld.quad 0x0 46. "R_PEND11,Masked completion ring pending bit for Rx channel n+11" "0,1" bitfld.quad 0x0 45. "T_ERR11,Masked error bit for Tx channel n+11" "0,1" bitfld.quad 0x0 44. "T_PEND11,Masked completion ring pending bit for Tx channel n+11" "0,1" bitfld.quad 0x0 43. "R_ERR10,Masked error bit for Tx channel n+10" "0,1" newline bitfld.quad 0x0 42. "R_PEND10,Masked completion ring pending bit for Rx channel n+10" "0,1" bitfld.quad 0x0 41. "T_ERR10,Masked error bit for Tx channel n+10" "0,1" bitfld.quad 0x0 40. "T_PEND10,Masked completion ring pending bit for Tx channel n+10" "0,1" bitfld.quad 0x0 39. "R_ERR9,Masked error bit for Tx channel n+9" "0,1" bitfld.quad 0x0 38. "R_PEND9,Masked completion ring pending bit for Rx channel n+9" "0,1" bitfld.quad 0x0 37. "T_ERR9,Masked error bit for Tx channel n+9" "0,1" bitfld.quad 0x0 36. "T_PEND9,Masked completion ring pending bit for Tx channel n+9" "0,1" newline bitfld.quad 0x0 35. "R_ERR8,Masked error bit for Tx channel n+8" "0,1" bitfld.quad 0x0 34. "R_PEND8,Masked completion ring pending bit for Rx channel n+8" "0,1" bitfld.quad 0x0 33. "T_ERR8,Masked error bit for Tx channel n+8" "0,1" bitfld.quad 0x0 32. "T_PEND8,Masked completion ring pending bit for Tx channel n+8" "0,1" bitfld.quad 0x0 31. "R_ERR7,Masked error bit for Tx channel n+7" "0,1" bitfld.quad 0x0 30. "R_PEND7,Masked completion ring pending bit for Rx channel n+7" "0,1" bitfld.quad 0x0 29. "T_ERR7,Masked error bit for Tx channel n+7" "0,1" newline bitfld.quad 0x0 28. "T_PEND7,Masked completion ring pending bit for Tx channel n+7" "0,1" bitfld.quad 0x0 27. "R_ERR6,Masked error bit for Tx channel n+6" "0,1" bitfld.quad 0x0 26. "R_PEND6,Masked completion ring pending bit for Rx channel n+6" "0,1" bitfld.quad 0x0 25. "T_ERR6,Masked error bit for Tx channel n+6" "0,1" bitfld.quad 0x0 24. "T_PEND6,Masked completion ring pending bit for Tx channel n+6" "0,1" bitfld.quad 0x0 23. "R_ERR5,Masked error bit for Tx channel n+5" "0,1" bitfld.quad 0x0 22. "R_PEND5,Masked completion ring pending bit for Rx channel n+5" "0,1" newline bitfld.quad 0x0 21. "T_ERR5,Masked error bit for Tx channel n+5" "0,1" bitfld.quad 0x0 20. "T_PEND5,Masked completion ring pending bit for Tx channel n+5" "0,1" bitfld.quad 0x0 19. "R_ERR4,Masked error bit for Tx channel n+4" "0,1" bitfld.quad 0x0 18. "R_PEND4,Masked completion ring pending bit for Rx channel n+4" "0,1" bitfld.quad 0x0 17. "T_ERR4,Masked error bit for Tx channel n+4" "0,1" bitfld.quad 0x0 16. "T_PEND4,Masked completion ring pending bit for Tx channel n+4" "0,1" bitfld.quad 0x0 15. "R_ERR3,Masked error bit for Tx channel n+3" "0,1" newline bitfld.quad 0x0 14. "R_PEND3,Masked completion ring pending bit for Rx channel n+3" "0,1" bitfld.quad 0x0 13. "T_ERR3,Masked error bit for Tx channel n+3" "0,1" bitfld.quad 0x0 12. "T_PEND3,Masked completion ring pending bit for Tx channel n+3" "0,1" bitfld.quad 0x0 11. "R_ERR2,Masked error bit for Tx channel n+2" "0,1" bitfld.quad 0x0 10. "R_PEND2,Masked completion ring pending bit for Rx channel n+2" "0,1" bitfld.quad 0x0 9. "T_ERR2,Masked error bit for Tx channel n+2" "0,1" bitfld.quad 0x0 8. "T_PEND2,Masked completion ring pending bit for Tx channel n+2" "0,1" newline bitfld.quad 0x0 7. "R_ERR1,Masked error bit for Tx channel n+1" "0,1" bitfld.quad 0x0 6. "R_PEND1,Masked completion ring pending bit for Rx channel n+1" "0,1" bitfld.quad 0x0 5. "T_ERR1,Masked error bit for Tx channel n+1" "0,1" bitfld.quad 0x0 4. "T_PEND1,Masked completion ring pending bit for Tx channel n+1" "0,1" bitfld.quad 0x0 3. "R_ERR0,Masked error bit for Tx channel n" "0,1" bitfld.quad 0x0 2. "R_PEND0,Masked completion ring pending bit for Rx channel n" "0,1" bitfld.quad 0x0 1. "T_ERR0,Masked error bit for Tx channel n" "0,1" newline bitfld.quad 0x0 0. "T_PEND0,Masked completion ring pending bit for Tx channel n" "0,1" tree.end tree "VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CHNRT (VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CHNRT)" base ad:0x3B40000 rgroup.quad 0x0++0x7 line.quad 0x0 "DRU_UTC_VPAC1__DRU_MMR_CFG__DRU_DRU_DRU_CHNRT_cfg,Channel Configuration Register. The Channel Configuration Register is used to initialize static mode settings for the DMA Channel. The register may only be written when the chanel is disable in the.." bitfld.quad 0x0 31. "PAUSE_ON_ERR,Pause on Error. This field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW to.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." bitfld.quad 0x0 19. "CHAN_TYPE_OWNER,This field controls how the TR is received by the UTC. If it is 0 then the SUBMISSION registers must be written to submit it. If it is a 1 then the TR will be received through PSIL." "0,1" newline rbitfld.quad 0x0 16.--18. "CHAN_TYPE,This field states the TR type that is being used it along with CHAN_TYPE_OWNER field make up the 4 bit CHAN_TYPE for a KS3 DMA UTC. The value of this is all zeroes. To reflect that the UTC DRU only does TRs through pass by value mechanisms." "0,1,2,3,4,5,6,7" rgroup.quad 0x20++0x7 line.quad 0x0 "DRU_UTC_VPAC1__DRU_MMR_CFG__DRU_DRU_DRU_CHNRT_choes0,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number.." hexmask.quad.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated." rgroup.quad 0x60++0x7 line.quad 0x0 "DRU_UTC_VPAC1__DRU_MMR_CFG__DRU_DRU_DRU_CHNRT_chst_sched,Channel Static Scheduler Config Register" bitfld.quad 0x0 0.--2. "QUEUE,This is the queue number that is written" "0,1,2,3,4,5,6,7" tree.end tree "VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CHRT (VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CHRT)" base ad:0x3B60000 rgroup.quad 0x0++0xF line.quad 0x0 "DRU_UTC_VPAC1__DRU_MMR_CFG__DRU_DRU_DRU_CHRT_chrt_ctl,The channel realtime control register contains real-time cotrol and status information for the DMA Channel. The fields in this regsiter can be changed while the channel is in operation." bitfld.quad 0x0 31. "ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared.." newline bitfld.quad 0x0 30. "TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" newline bitfld.quad 0x0 29. "PAUSE,Channel pause: Setting this bit will request the channel to pause processing at the next packet boundary. This is a more graceful method of halting processing than disabling the channel as it will not allow any current packets to underflow." "0,1" newline bitfld.quad 0x0 28. "FORCED_TEARDOWN,Channel forced teardown: Setting this bit will request the channel to be torn down forcefulyy. This field will clear after a channel teardown is complete." "0,1" line.quad 0x8 "DRU_UTC_VPAC1__DRU_MMR_CFG__DRU_DRU_DRU_CHRT_chrt_swtrig,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way." bitfld.quad 0x8 2. "LOCAL_TRIGGER0,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel. This will trigger LOCAL Event" "0,1" newline bitfld.quad 0x8 1. "GLOBAL_TRIGGER1,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel. This will trigger Global Event 1" "0,1" newline bitfld.quad 0x8 0. "GLOBAL_TRIGGER0,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel. This will trigger Global Event 0" "0,1" rgroup.quad 0x10++0xF line.quad 0x0 "DRU_UTC_VPAC1__DRU_MMR_CFG__DRU_DRU_DRU_CHRT_chrt_status_det,The channel status details" hexmask.quad.byte 0x0 8.--15. 1. "CMD_ID,The last cmd_id given to the write queue" newline hexmask.quad.byte 0x0 4.--7. 1. "INFO,The info of the error that was received" newline hexmask.quad.byte 0x0 0.--3. 1. "STATUS_TYPE,The type of error that was received" line.quad 0x8 "DRU_UTC_VPAC1__DRU_MMR_CFG__DRU_DRU_DRU_CHRT_chrt_status_cnt,The channel count details" hexmask.quad.word 0x8 48.--63. 1. "ICNT3,The last icnt3 given to the write queue" newline hexmask.quad.word 0x8 32.--47. 1. "ICNT2,The last icnt2 given to the write queue" newline hexmask.quad.word 0x8 16.--31. 1. "ICNT1,The last icnt1 given to the write queue" newline hexmask.quad.word 0x8 0.--15. 1. "ICNT0,The last icnt0 given to the write queue" tree.end tree "VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_QUEUE (VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_QUEUE)" base ad:0x3B08000 rgroup.quad 0x0++0x7 line.quad 0x0 "DRU_UTC_VPAC1__DRU_MMR_CFG__DRU_DRU_DRU_QUEUE_cfg,Configuration Register for Queue 0" hexmask.quad.long 0x0 32.--63. 1. "RSVD,Reserved." hexmask.quad.byte 0x0 24.--31. 1. "REARB_WAIT,This is the number of commands that will be sent by other queues before allowing the queue to arbitrate again for the right to send commands. This is only started when a queue exhausted its consecutive trans count." hexmask.quad.byte 0x0 16.--23. 1. "CONSECUTIVE_TRANS,This is the number of consecutive transactions that will be sent before allowing another queue of equal level to arbitrate to send commands. This is the maximum number of commands that it can send. If the queue has any delays such as.." newline bitfld.quad 0x0 8.--10. "QOS,This configures the QOS for QUEUE0. This should only be set for fixed priority queues and the lower queue should have the lower QoS." "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x0 4.--7. 1. "ORDERID,This configures the orderid for QUEUE0." bitfld.quad 0x0 0.--2. "PRI,This configures the priority for QUEUE0. This will be the priority that will be presented on the External bus for all commands from this queue." "0,1,2,3,4,5,6,7" rgroup.quad 0x40++0x7 line.quad 0x0 "DRU_UTC_VPAC1__DRU_MMR_CFG__DRU_DRU_DRU_QUEUE_status,Status Register for Queue 0" hexmask.quad.word 0x0 27.--35. 1. "RD_TOTAL,This is the channel that the read half is currently working on." hexmask.quad.word 0x0 18.--26. 1. "RD_TOP,This is the channel that the read half is currently working on." hexmask.quad.word 0x0 9.--17. 1. "WR_TOTAL,This is the channel that the read half is currently working on." newline hexmask.quad.word 0x0 0.--8. 1. "WR_TOP,This is the channel that the write half is currently working on." tree.end tree "VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_SET (VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_SET)" base ad:0x3B04000 rgroup.quad 0x0++0x7 line.quad 0x0 "DRU_UTC_VPAC1__DRU_MMR_CFG__DRU_DRU_DRU_SET_dru_shared_evt_set,DRU Shared Event Set Register" bitfld.quad 0x0 0. "PROT_ERR,Set the Prot Error event" "0,1" rgroup.quad 0x40++0x7 line.quad 0x0 "DRU_UTC_VPAC1__DRU_MMR_CFG__DRU_DRU_DRU_SET_dru_comp_evt_set0,DRU Completion Event Set Register" bitfld.quad 0x0 63. "COMP_EVT63,Set the Completion Event for channel 63" "0,1" bitfld.quad 0x0 62. "COMP_EVT62,Set the Completion Event for channel 62" "0,1" bitfld.quad 0x0 61. "COMP_EVT61,Set the Completion Event for channel 61" "0,1" bitfld.quad 0x0 60. "COMP_EVT60,Set the Completion Event for channel 60" "0,1" bitfld.quad 0x0 59. "COMP_EVT59,Set the Completion Event for channel 59" "0,1" newline bitfld.quad 0x0 58. "COMP_EVT58,Set the Completion Event for channel 58" "0,1" bitfld.quad 0x0 57. "COMP_EVT57,Set the Completion Event for channel 57" "0,1" bitfld.quad 0x0 56. "COMP_EVT56,Set the Completion Event for channel 56" "0,1" bitfld.quad 0x0 55. "COMP_EVT55,Set the Completion Event for channel 55" "0,1" bitfld.quad 0x0 54. "COMP_EVT54,Set the Completion Event for channel 54" "0,1" newline bitfld.quad 0x0 53. "COMP_EVT53,Set the Completion Event for channel 53" "0,1" bitfld.quad 0x0 52. "COMP_EVT52,Set the Completion Event for channel 52" "0,1" bitfld.quad 0x0 51. "COMP_EVT51,Set the Completion Event for channel 51" "0,1" bitfld.quad 0x0 50. "COMP_EVT50,Set the Completion Event for channel 50" "0,1" bitfld.quad 0x0 49. "COMP_EVT49,Set the Completion Event for channel 49" "0,1" newline bitfld.quad 0x0 48. "COMP_EVT48,Set the Completion Event for channel 48" "0,1" bitfld.quad 0x0 47. "COMP_EVT47,Set the Completion Event for channel 47" "0,1" bitfld.quad 0x0 46. "COMP_EVT46,Set the Completion Event for channel 46" "0,1" bitfld.quad 0x0 45. "COMP_EVT45,Set the Completion Event for channel 45" "0,1" bitfld.quad 0x0 44. "COMP_EVT44,Set the Completion Event for channel 44" "0,1" newline bitfld.quad 0x0 43. "COMP_EVT43,Set the Completion Event for channel 43" "0,1" bitfld.quad 0x0 42. "COMP_EVT42,Set the Completion Event for channel 42" "0,1" bitfld.quad 0x0 41. "COMP_EVT41,Set the Completion Event for channel 41" "0,1" bitfld.quad 0x0 40. "COMP_EVT40,Set the Completion Event for channel 40" "0,1" bitfld.quad 0x0 39. "COMP_EVT39,Set the Completion Event for channel 39" "0,1" newline bitfld.quad 0x0 38. "COMP_EVT38,Set the Completion Event for channel 38" "0,1" bitfld.quad 0x0 37. "COMP_EVT37,Set the Completion Event for channel 37" "0,1" bitfld.quad 0x0 36. "COMP_EVT36,Set the Completion Event for channel 36" "0,1" bitfld.quad 0x0 35. "COMP_EVT35,Set the Completion Event for channel 35" "0,1" bitfld.quad 0x0 34. "COMP_EVT34,Set the Completion Event for channel 34" "0,1" newline bitfld.quad 0x0 33. "COMP_EVT33,Set the Completion Event for channel 33" "0,1" bitfld.quad 0x0 32. "COMP_EVT32,Set the Completion Event for channel 32" "0,1" bitfld.quad 0x0 31. "COMP_EVT31,Set the Completion Event for channel 31" "0,1" bitfld.quad 0x0 30. "COMP_EVT30,Set the Completion Event for channel 30" "0,1" bitfld.quad 0x0 29. "COMP_EVT29,Set the Completion Event for channel 29" "0,1" newline bitfld.quad 0x0 28. "COMP_EVT28,Set the Completion Event for channel 28" "0,1" bitfld.quad 0x0 27. "COMP_EVT27,Set the Completion Event for channel 27" "0,1" bitfld.quad 0x0 26. "COMP_EVT26,Set the Completion Event for channel 26" "0,1" bitfld.quad 0x0 25. "COMP_EVT25,Set the Completion Event for channel 25" "0,1" bitfld.quad 0x0 24. "COMP_EVT24,Set the Completion Event for channel 24" "0,1" newline bitfld.quad 0x0 23. "COMP_EVT23,Set the Completion Event for channel 23" "0,1" bitfld.quad 0x0 22. "COMP_EVT22,Set the Completion Event for channel 22" "0,1" bitfld.quad 0x0 21. "COMP_EVT21,Set the Completion Event for channel 21" "0,1" bitfld.quad 0x0 20. "COMP_EVT20,Set the Completion Event for channel 20" "0,1" bitfld.quad 0x0 19. "COMP_EVT19,Set the Completion Event for channel 19" "0,1" newline bitfld.quad 0x0 18. "COMP_EVT18,Set the Completion Event for channel 18" "0,1" bitfld.quad 0x0 17. "COMP_EVT17,Set the Completion Event for channel 17" "0,1" bitfld.quad 0x0 16. "COMP_EVT16,Set the Completion Event for channel 16" "0,1" bitfld.quad 0x0 15. "COMP_EVT15,Set the Completion Event for channel 15" "0,1" bitfld.quad 0x0 14. "COMP_EVT14,Set the Completion Event for channel 14" "0,1" newline bitfld.quad 0x0 13. "COMP_EVT13,Set the Completion Event for channel 13" "0,1" bitfld.quad 0x0 12. "COMP_EVT12,Set the Completion Event for channel 12" "0,1" bitfld.quad 0x0 11. "COMP_EVT11,Set the Completion Event for channel 11" "0,1" bitfld.quad 0x0 10. "COMP_EVT10,Set the Completion Event for channel 10" "0,1" bitfld.quad 0x0 9. "COMP_EVT9,Set the Completion Event for channel 9" "0,1" newline bitfld.quad 0x0 8. "COMP_EVT8,Set the Completion Event for channel 8" "0,1" bitfld.quad 0x0 7. "COMP_EVT7,Set the Completion Event for channel 7" "0,1" bitfld.quad 0x0 6. "COMP_EVT6,Set the Completion Event for channel 6" "0,1" bitfld.quad 0x0 5. "COMP_EVT5,Set the Completion Event for channel 5" "0,1" bitfld.quad 0x0 4. "COMP_EVT4,Set the Completion Event for channel 4" "0,1" newline bitfld.quad 0x0 3. "COMP_EVT3,Set the Completion Event for channel 3" "0,1" bitfld.quad 0x0 2. "COMP_EVT2,Set the Completion Event for channel 2" "0,1" bitfld.quad 0x0 1. "COMP_EVT1,Set the Completion Event for channel 1" "0,1" bitfld.quad 0x0 0. "COMP_EVT0,Set the Completion Event for channel 0" "0,1" rgroup.quad 0x80++0x7 line.quad 0x0 "DRU_UTC_VPAC1__DRU_MMR_CFG__DRU_DRU_DRU_SET_dru_err_evt_set0,DRU Error Event Set Register" bitfld.quad 0x0 63. "ERR_EVT63,Set the Error Event for channel 63" "0,1" bitfld.quad 0x0 62. "ERR_EVT62,Set the Error Event for channel 62" "0,1" bitfld.quad 0x0 61. "ERR_EVT61,Set the Error Event for channel 61" "0,1" bitfld.quad 0x0 60. "ERR_EVT60,Set the Error Event for channel 60" "0,1" bitfld.quad 0x0 59. "ERR_EVT59,Set the Error Event for channel 59" "0,1" newline bitfld.quad 0x0 58. "ERR_EVT58,Set the Error Event for channel 58" "0,1" bitfld.quad 0x0 57. "ERR_EVT57,Set the Error Event for channel 57" "0,1" bitfld.quad 0x0 56. "ERR_EVT56,Set the Error Event for channel 56" "0,1" bitfld.quad 0x0 55. "ERR_EVT55,Set the Error Event for channel 55" "0,1" bitfld.quad 0x0 54. "ERR_EVT54,Set the Error Event for channel 54" "0,1" newline bitfld.quad 0x0 53. "ERR_EVT53,Set the Error Event for channel 53" "0,1" bitfld.quad 0x0 52. "ERR_EVT52,Set the Error Event for channel 52" "0,1" bitfld.quad 0x0 51. "ERR_EVT51,Set the Error Event for channel 51" "0,1" bitfld.quad 0x0 50. "ERR_EVT50,Set the Error Event for channel 50" "0,1" bitfld.quad 0x0 49. "ERR_EVT49,Set the Error Event for channel 49" "0,1" newline bitfld.quad 0x0 48. "ERR_EVT48,Set the Error Event for channel 48" "0,1" bitfld.quad 0x0 47. "ERR_EVT47,Set the Error Event for channel 47" "0,1" bitfld.quad 0x0 46. "ERR_EVT46,Set the Error Event for channel 46" "0,1" bitfld.quad 0x0 45. "ERR_EVT45,Set the Error Event for channel 45" "0,1" bitfld.quad 0x0 44. "ERR_EVT44,Set the Error Event for channel 44" "0,1" newline bitfld.quad 0x0 43. "ERR_EVT43,Set the Error Event for channel 43" "0,1" bitfld.quad 0x0 42. "ERR_EVT42,Set the Error Event for channel 42" "0,1" bitfld.quad 0x0 41. "ERR_EVT41,Set the Error Event for channel 41" "0,1" bitfld.quad 0x0 40. "ERR_EVT40,Set the Error Event for channel 40" "0,1" bitfld.quad 0x0 39. "ERR_EVT39,Set the Error Event for channel 39" "0,1" newline bitfld.quad 0x0 38. "ERR_EVT38,Set the Error Event for channel 38" "0,1" bitfld.quad 0x0 37. "ERR_EVT37,Set the Error Event for channel 37" "0,1" bitfld.quad 0x0 36. "ERR_EVT36,Set the Error Event for channel 36" "0,1" bitfld.quad 0x0 35. "ERR_EVT35,Set the Error Event for channel 35" "0,1" bitfld.quad 0x0 34. "ERR_EVT34,Set the Error Event for channel 34" "0,1" newline bitfld.quad 0x0 33. "ERR_EVT33,Set the Error Event for channel 33" "0,1" bitfld.quad 0x0 32. "ERR_EVT32,Set the Error Event for channel 32" "0,1" bitfld.quad 0x0 31. "ERR_EVT31,Set the Error Event for channel 31" "0,1" bitfld.quad 0x0 30. "ERR_EVT30,Set the Error Event for channel 30" "0,1" bitfld.quad 0x0 29. "ERR_EVT29,Set the Error Event for channel 29" "0,1" newline bitfld.quad 0x0 28. "ERR_EVT28,Set the Error Event for channel 28" "0,1" bitfld.quad 0x0 27. "ERR_EVT27,Set the Error Event for channel 27" "0,1" bitfld.quad 0x0 26. "ERR_EVT26,Set the Error Event for channel 26" "0,1" bitfld.quad 0x0 25. "ERR_EVT25,Set the Error Event for channel 25" "0,1" bitfld.quad 0x0 24. "ERR_EVT24,Set the Error Event for channel 24" "0,1" newline bitfld.quad 0x0 23. "ERR_EVT23,Set the Error Event for channel 23" "0,1" bitfld.quad 0x0 22. "ERR_EVT22,Set the Error Event for channel 22" "0,1" bitfld.quad 0x0 21. "ERR_EVT21,Set the Error Event for channel 21" "0,1" bitfld.quad 0x0 20. "ERR_EVT20,Set the Error Event for channel 20" "0,1" bitfld.quad 0x0 19. "ERR_EVT19,Set the Error Event for channel 19" "0,1" newline bitfld.quad 0x0 18. "ERR_EVT18,Set the Error Event for channel 18" "0,1" bitfld.quad 0x0 17. "ERR_EVT17,Set the Error Event for channel 17" "0,1" bitfld.quad 0x0 16. "ERR_EVT16,Set the Error Event for channel 16" "0,1" bitfld.quad 0x0 15. "ERR_EVT15,Set the Error Event for channel 15" "0,1" bitfld.quad 0x0 14. "ERR_EVT14,Set the Error Event for channel 14" "0,1" newline bitfld.quad 0x0 13. "ERR_EVT13,Set the Error Event for channel 13" "0,1" bitfld.quad 0x0 12. "ERR_EVT12,Set the Error Event for channel 12" "0,1" bitfld.quad 0x0 11. "ERR_EVT11,Set the Error Event for channel 11" "0,1" bitfld.quad 0x0 10. "ERR_EVT10,Set the Error Event for channel 10" "0,1" bitfld.quad 0x0 9. "ERR_EVT9,Set the Error Event for channel 9" "0,1" newline bitfld.quad 0x0 8. "ERR_EVT8,Set the Error Event for channel 8" "0,1" bitfld.quad 0x0 7. "ERR_EVT7,Set the Error Event for channel 7" "0,1" bitfld.quad 0x0 6. "ERR_EVT6,Set the Error Event for channel 6" "0,1" bitfld.quad 0x0 5. "ERR_EVT5,Set the Error Event for channel 5" "0,1" bitfld.quad 0x0 4. "ERR_EVT4,Set the Error Event for channel 4" "0,1" newline bitfld.quad 0x0 3. "ERR_EVT3,Set the Error Event for channel 3" "0,1" bitfld.quad 0x0 2. "ERR_EVT2,Set the Error Event for channel 2" "0,1" bitfld.quad 0x0 1. "ERR_EVT1,Set the Error Event for channel 1" "0,1" bitfld.quad 0x0 0. "ERR_EVT0,Set the Error Event for channel 0" "0,1" rgroup.quad 0xC0++0x7 line.quad 0x0 "DRU_UTC_VPAC1__DRU_MMR_CFG__DRU_DRU_DRU_SET_dru_local_evt_set0,DRU Local Event Set Register" bitfld.quad 0x0 63. "COMP_EVT63,Set the Local Event for channel 63" "0,1" bitfld.quad 0x0 62. "COMP_EVT62,Set the Local Event for channel 62" "0,1" bitfld.quad 0x0 61. "COMP_EVT61,Set the Local Event for channel 61" "0,1" bitfld.quad 0x0 60. "COMP_EVT60,Set the Local Event for channel 60" "0,1" bitfld.quad 0x0 59. "COMP_EVT59,Set the Local Event for channel 59" "0,1" newline bitfld.quad 0x0 58. "COMP_EVT58,Set the Local Event for channel 58" "0,1" bitfld.quad 0x0 57. "COMP_EVT57,Set the Local Event for channel 57" "0,1" bitfld.quad 0x0 56. "COMP_EVT56,Set the Local Event for channel 56" "0,1" bitfld.quad 0x0 55. "COMP_EVT55,Set the Local Event for channel 55" "0,1" bitfld.quad 0x0 54. "COMP_EVT54,Set the Local Event for channel 54" "0,1" newline bitfld.quad 0x0 53. "COMP_EVT53,Set the Local Event for channel 53" "0,1" bitfld.quad 0x0 52. "COMP_EVT52,Set the Local Event for channel 52" "0,1" bitfld.quad 0x0 51. "COMP_EVT51,Set the Local Event for channel 51" "0,1" bitfld.quad 0x0 50. "COMP_EVT50,Set the Local Event for channel 50" "0,1" bitfld.quad 0x0 49. "COMP_EVT49,Set the Local Event for channel 49" "0,1" newline bitfld.quad 0x0 48. "COMP_EVT48,Set the Local Event for channel 48" "0,1" bitfld.quad 0x0 47. "COMP_EVT47,Set the Local Event for channel 47" "0,1" bitfld.quad 0x0 46. "COMP_EVT46,Set the Local Event for channel 46" "0,1" bitfld.quad 0x0 45. "COMP_EVT45,Set the Local Event for channel 45" "0,1" bitfld.quad 0x0 44. "COMP_EVT44,Set the Local Event for channel 44" "0,1" newline bitfld.quad 0x0 43. "COMP_EVT43,Set the Local Event for channel 43" "0,1" bitfld.quad 0x0 42. "COMP_EVT42,Set the Local Event for channel 42" "0,1" bitfld.quad 0x0 41. "COMP_EVT41,Set the Local Event for channel 41" "0,1" bitfld.quad 0x0 40. "COMP_EVT40,Set the Local Event for channel 40" "0,1" bitfld.quad 0x0 39. "COMP_EVT39,Set the Local Event for channel 39" "0,1" newline bitfld.quad 0x0 38. "COMP_EVT38,Set the Local Event for channel 38" "0,1" bitfld.quad 0x0 37. "COMP_EVT37,Set the Local Event for channel 37" "0,1" bitfld.quad 0x0 36. "COMP_EVT36,Set the Local Event for channel 36" "0,1" bitfld.quad 0x0 35. "COMP_EVT35,Set the Local Event for channel 35" "0,1" bitfld.quad 0x0 34. "COMP_EVT34,Set the Local Event for channel 34" "0,1" newline bitfld.quad 0x0 33. "COMP_EVT33,Set the Local Event for channel 33" "0,1" bitfld.quad 0x0 32. "COMP_EVT32,Set the Local Event for channel 32" "0,1" bitfld.quad 0x0 31. "COMP_EVT31,Set the Local Event for channel 31" "0,1" bitfld.quad 0x0 30. "COMP_EVT30,Set the Local Event for channel 30" "0,1" bitfld.quad 0x0 29. "COMP_EVT29,Set the Local Event for channel 29" "0,1" newline bitfld.quad 0x0 28. "COMP_EVT28,Set the Local Event for channel 28" "0,1" bitfld.quad 0x0 27. "COMP_EVT27,Set the Local Event for channel 27" "0,1" bitfld.quad 0x0 26. "COMP_EVT26,Set the Local Event for channel 26" "0,1" bitfld.quad 0x0 25. "COMP_EVT25,Set the Local Event for channel 25" "0,1" bitfld.quad 0x0 24. "COMP_EVT24,Set the Local Event for channel 24" "0,1" newline bitfld.quad 0x0 23. "COMP_EVT23,Set the Local Event for channel 23" "0,1" bitfld.quad 0x0 22. "COMP_EVT22,Set the Local Event for channel 22" "0,1" bitfld.quad 0x0 21. "COMP_EVT21,Set the Local Event for channel 21" "0,1" bitfld.quad 0x0 20. "COMP_EVT20,Set the Local Event for channel 20" "0,1" bitfld.quad 0x0 19. "COMP_EVT19,Set the Local Event for channel 19" "0,1" newline bitfld.quad 0x0 18. "COMP_EVT18,Set the Local Event for channel 18" "0,1" bitfld.quad 0x0 17. "COMP_EVT17,Set the Local Event for channel 17" "0,1" bitfld.quad 0x0 16. "COMP_EVT16,Set the Local Event for channel 16" "0,1" bitfld.quad 0x0 15. "COMP_EVT15,Set the Local Event for channel 15" "0,1" bitfld.quad 0x0 14. "COMP_EVT14,Set the Local Event for channel 14" "0,1" newline bitfld.quad 0x0 13. "COMP_EVT13,Set the Local Event for channel 13" "0,1" bitfld.quad 0x0 12. "COMP_EVT12,Set the Local Event for channel 12" "0,1" bitfld.quad 0x0 11. "COMP_EVT11,Set the Local Event for channel 11" "0,1" bitfld.quad 0x0 10. "COMP_EVT10,Set the Local Event for channel 10" "0,1" bitfld.quad 0x0 9. "COMP_EVT9,Set the Local Event for channel 9" "0,1" newline bitfld.quad 0x0 8. "COMP_EVT8,Set the Local Event for channel 8" "0,1" bitfld.quad 0x0 7. "COMP_EVT7,Set the Local Event for channel 7" "0,1" bitfld.quad 0x0 6. "COMP_EVT6,Set the Local Event for channel 6" "0,1" bitfld.quad 0x0 5. "COMP_EVT5,Set the Local Event for channel 5" "0,1" bitfld.quad 0x0 4. "COMP_EVT4,Set the Local Event for channel 4" "0,1" newline bitfld.quad 0x0 3. "COMP_EVT3,Set the Local Event for channel 3" "0,1" bitfld.quad 0x0 2. "COMP_EVT2,Set the Local Event for channel 2" "0,1" bitfld.quad 0x0 1. "COMP_EVT1,Set the Local Event for channel 1" "0,1" bitfld.quad 0x0 0. "COMP_EVT0,Set the Local Event for channel 0" "0,1" tree.end tree.end tree.end tree "VPAC0_ECC_AGGR (VPAC0_ECC_AGGR)" base ad:0x2A60000 rgroup.long 0x0++0x3 line.long 0x0 "KSDW_ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "KSDW_ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "KSDW_ECC_AGGR__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "KSDW_ECC_AGGR__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "KSDW_ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "KSDW_ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 13. "UTC1_DRU_STATE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc1_dru_state_buffer0_ecc_pend" "0,1" bitfld.long 0x4 12. "UTC1_DRU_QUEUE_BUFFER2_ECC_PEND,Interrupt Pending Status for utc1_dru_queue_buffer2_ecc_pend" "0,1" newline bitfld.long 0x4 11. "UTC1_DRU_QUEUE_BUFFER1_ECC_PEND,Interrupt Pending Status for utc1_dru_queue_buffer1_ecc_pend" "0,1" bitfld.long 0x4 10. "UTC1_DRU_QUEUE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc1_dru_queue_buffer0_ecc_pend" "0,1" newline bitfld.long 0x4 9. "UTC1_TPRAM_DRU_RESPONSE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc1_tpram_dru_response_buffer0_ecc_pend" "0,1" bitfld.long 0x4 8. "UTC1_DRU_PSI_EDC_PEND,Interrupt Pending Status for utc1_dru_psi_edc_pend" "0,1" newline bitfld.long 0x4 7. "UTC1_DRU_ENG_EDC_PEND,Interrupt Pending Status for utc1_dru_eng_edc_pend" "0,1" bitfld.long 0x4 6. "UTC0_DRU_STATE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc0_dru_state_buffer0_ecc_pend" "0,1" newline bitfld.long 0x4 5. "UTC0_DRU_QUEUE_BUFFER2_ECC_PEND,Interrupt Pending Status for utc0_dru_queue_buffer2_ecc_pend" "0,1" bitfld.long 0x4 4. "UTC0_DRU_QUEUE_BUFFER1_ECC_PEND,Interrupt Pending Status for utc0_dru_queue_buffer1_ecc_pend" "0,1" newline bitfld.long 0x4 3. "UTC0_DRU_QUEUE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc0_dru_queue_buffer0_ecc_pend" "0,1" bitfld.long 0x4 2. "UTC0_TPRAM_DRU_RESPONSE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc0_tpram_dru_response_buffer0_ecc_pend" "0,1" newline bitfld.long 0x4 1. "UTC0_DRU_PSI_EDC_PEND,Interrupt Pending Status for utc0_dru_psi_edc_pend" "0,1" bitfld.long 0x4 0. "UTC0_DRU_ENG_EDC_PEND,Interrupt Pending Status for utc0_dru_eng_edc_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "KSDW_ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 13. "UTC1_DRU_STATE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_state_buffer0_ecc_pend" "0,1" bitfld.long 0x0 12. "UTC1_DRU_QUEUE_BUFFER2_ECC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_queue_buffer2_ecc_pend" "0,1" newline bitfld.long 0x0 11. "UTC1_DRU_QUEUE_BUFFER1_ECC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_queue_buffer1_ecc_pend" "0,1" bitfld.long 0x0 10. "UTC1_DRU_QUEUE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_queue_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 9. "UTC1_TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc1_tpram_dru_response_buffer0_ecc_pend" "0,1" bitfld.long 0x0 8. "UTC1_DRU_PSI_EDC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_psi_edc_pend" "0,1" newline bitfld.long 0x0 7. "UTC1_DRU_ENG_EDC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_eng_edc_pend" "0,1" bitfld.long 0x0 6. "UTC0_DRU_STATE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_state_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 5. "UTC0_DRU_QUEUE_BUFFER2_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_queue_buffer2_ecc_pend" "0,1" bitfld.long 0x0 4. "UTC0_DRU_QUEUE_BUFFER1_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_queue_buffer1_ecc_pend" "0,1" newline bitfld.long 0x0 3. "UTC0_DRU_QUEUE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_queue_buffer0_ecc_pend" "0,1" bitfld.long 0x0 2. "UTC0_TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_tpram_dru_response_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 1. "UTC0_DRU_PSI_EDC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_psi_edc_pend" "0,1" bitfld.long 0x0 0. "UTC0_DRU_ENG_EDC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_eng_edc_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "KSDW_ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 13. "UTC1_DRU_STATE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_state_buffer0_ecc_pend" "0,1" bitfld.long 0x0 12. "UTC1_DRU_QUEUE_BUFFER2_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_queue_buffer2_ecc_pend" "0,1" newline bitfld.long 0x0 11. "UTC1_DRU_QUEUE_BUFFER1_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_queue_buffer1_ecc_pend" "0,1" bitfld.long 0x0 10. "UTC1_DRU_QUEUE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_queue_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 9. "UTC1_TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_tpram_dru_response_buffer0_ecc_pend" "0,1" bitfld.long 0x0 8. "UTC1_DRU_PSI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_psi_edc_pend" "0,1" newline bitfld.long 0x0 7. "UTC1_DRU_ENG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_eng_edc_pend" "0,1" bitfld.long 0x0 6. "UTC0_DRU_STATE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_state_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 5. "UTC0_DRU_QUEUE_BUFFER2_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_queue_buffer2_ecc_pend" "0,1" bitfld.long 0x0 4. "UTC0_DRU_QUEUE_BUFFER1_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_queue_buffer1_ecc_pend" "0,1" newline bitfld.long 0x0 3. "UTC0_DRU_QUEUE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_queue_buffer0_ecc_pend" "0,1" bitfld.long 0x0 2. "UTC0_TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_tpram_dru_response_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 1. "UTC0_DRU_PSI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_psi_edc_pend" "0,1" bitfld.long 0x0 0. "UTC0_DRU_ENG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_eng_edc_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "KSDW_ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "KSDW_ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 13. "UTC1_DRU_STATE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc1_dru_state_buffer0_ecc_pend" "0,1" bitfld.long 0x4 12. "UTC1_DRU_QUEUE_BUFFER2_ECC_PEND,Interrupt Pending Status for utc1_dru_queue_buffer2_ecc_pend" "0,1" newline bitfld.long 0x4 11. "UTC1_DRU_QUEUE_BUFFER1_ECC_PEND,Interrupt Pending Status for utc1_dru_queue_buffer1_ecc_pend" "0,1" bitfld.long 0x4 10. "UTC1_DRU_QUEUE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc1_dru_queue_buffer0_ecc_pend" "0,1" newline bitfld.long 0x4 9. "UTC1_TPRAM_DRU_RESPONSE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc1_tpram_dru_response_buffer0_ecc_pend" "0,1" bitfld.long 0x4 8. "UTC1_DRU_PSI_EDC_PEND,Interrupt Pending Status for utc1_dru_psi_edc_pend" "0,1" newline bitfld.long 0x4 7. "UTC1_DRU_ENG_EDC_PEND,Interrupt Pending Status for utc1_dru_eng_edc_pend" "0,1" bitfld.long 0x4 6. "UTC0_DRU_STATE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc0_dru_state_buffer0_ecc_pend" "0,1" newline bitfld.long 0x4 5. "UTC0_DRU_QUEUE_BUFFER2_ECC_PEND,Interrupt Pending Status for utc0_dru_queue_buffer2_ecc_pend" "0,1" bitfld.long 0x4 4. "UTC0_DRU_QUEUE_BUFFER1_ECC_PEND,Interrupt Pending Status for utc0_dru_queue_buffer1_ecc_pend" "0,1" newline bitfld.long 0x4 3. "UTC0_DRU_QUEUE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc0_dru_queue_buffer0_ecc_pend" "0,1" bitfld.long 0x4 2. "UTC0_TPRAM_DRU_RESPONSE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc0_tpram_dru_response_buffer0_ecc_pend" "0,1" newline bitfld.long 0x4 1. "UTC0_DRU_PSI_EDC_PEND,Interrupt Pending Status for utc0_dru_psi_edc_pend" "0,1" bitfld.long 0x4 0. "UTC0_DRU_ENG_EDC_PEND,Interrupt Pending Status for utc0_dru_eng_edc_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "KSDW_ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 13. "UTC1_DRU_STATE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_state_buffer0_ecc_pend" "0,1" bitfld.long 0x0 12. "UTC1_DRU_QUEUE_BUFFER2_ECC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_queue_buffer2_ecc_pend" "0,1" newline bitfld.long 0x0 11. "UTC1_DRU_QUEUE_BUFFER1_ECC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_queue_buffer1_ecc_pend" "0,1" bitfld.long 0x0 10. "UTC1_DRU_QUEUE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_queue_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 9. "UTC1_TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc1_tpram_dru_response_buffer0_ecc_pend" "0,1" bitfld.long 0x0 8. "UTC1_DRU_PSI_EDC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_psi_edc_pend" "0,1" newline bitfld.long 0x0 7. "UTC1_DRU_ENG_EDC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_eng_edc_pend" "0,1" bitfld.long 0x0 6. "UTC0_DRU_STATE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_state_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 5. "UTC0_DRU_QUEUE_BUFFER2_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_queue_buffer2_ecc_pend" "0,1" bitfld.long 0x0 4. "UTC0_DRU_QUEUE_BUFFER1_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_queue_buffer1_ecc_pend" "0,1" newline bitfld.long 0x0 3. "UTC0_DRU_QUEUE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_queue_buffer0_ecc_pend" "0,1" bitfld.long 0x0 2. "UTC0_TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_tpram_dru_response_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 1. "UTC0_DRU_PSI_EDC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_psi_edc_pend" "0,1" bitfld.long 0x0 0. "UTC0_DRU_ENG_EDC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_eng_edc_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "KSDW_ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 13. "UTC1_DRU_STATE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_state_buffer0_ecc_pend" "0,1" bitfld.long 0x0 12. "UTC1_DRU_QUEUE_BUFFER2_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_queue_buffer2_ecc_pend" "0,1" newline bitfld.long 0x0 11. "UTC1_DRU_QUEUE_BUFFER1_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_queue_buffer1_ecc_pend" "0,1" bitfld.long 0x0 10. "UTC1_DRU_QUEUE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_queue_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 9. "UTC1_TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_tpram_dru_response_buffer0_ecc_pend" "0,1" bitfld.long 0x0 8. "UTC1_DRU_PSI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_psi_edc_pend" "0,1" newline bitfld.long 0x0 7. "UTC1_DRU_ENG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_eng_edc_pend" "0,1" bitfld.long 0x0 6. "UTC0_DRU_STATE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_state_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 5. "UTC0_DRU_QUEUE_BUFFER2_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_queue_buffer2_ecc_pend" "0,1" bitfld.long 0x0 4. "UTC0_DRU_QUEUE_BUFFER1_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_queue_buffer1_ecc_pend" "0,1" newline bitfld.long 0x0 3. "UTC0_DRU_QUEUE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_queue_buffer0_ecc_pend" "0,1" bitfld.long 0x0 2. "UTC0_TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_tpram_dru_response_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 1. "UTC0_DRU_PSI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_psi_edc_pend" "0,1" bitfld.long 0x0 0. "UTC0_DRU_ENG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_eng_edc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "KSDW_ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "KSDW_ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "KSDW_ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "KSDW_ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "VPAC0_HTS_S_VBUSP (VPAC0_HTS_S_VBUSP)" base ad:0x3810000 rgroup.long 0x0++0x1B line.long 0x0 "HTS__S_VBUSP__REGS_pipeline_control_0,Enable pipeline to activate all connected scheduler" bitfld.long 0x0 2.--4. "HW_EN_EVTSELECT,Hw triggered pipeline enable on internally generated hts_event[hw_en_evtselect]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1. "HW_EN,Hw event triggerred Pipeline 0 enable '1': activate pipeline to receive hw event as described in hw_en_evtselect and hts_event_gen.evt_select '0' : hw event based pipeline is not enabled" "0,1" newline bitfld.long 0x0 0. "PIPE_EN,Pipeline 0 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_pipeline_control_1,Enable pipeline to activate all connected scheduler" bitfld.long 0x4 2.--4. "HW_EN_EVTSELECT,Hw triggered pipeline enable on internally generated hts_event[hw_en_evtselect]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 1. "HW_EN,Hw event triggerred Pipeline 1 enable '1': activate pipeline to receive hw event as described in hw_en_evtselect and hts_event_gen.evt_select '0' : hw event based pipeline is not enabled" "0,1" newline bitfld.long 0x4 0. "PIPE_EN,Pipeline 1 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_pipeline_control_2,Enable pipeline to activate all connected scheduler" bitfld.long 0x8 2.--4. "HW_EN_EVTSELECT,Hw triggered pipeline enable on internally generated hts_event[hw_en_evtselect]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 1. "HW_EN,Hw event triggerred Pipeline 2 enable '1': activate pipeline to receive hw event as described in hw_en_evtselect and hts_event_gen.evt_select '0' : hw event based pipeline is not enabled" "0,1" newline bitfld.long 0x8 0. "PIPE_EN,Pipeline 2 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_pipeline_control_3,Enable pipeline to activate all connected scheduler" bitfld.long 0xC 2.--4. "HW_EN_EVTSELECT,Hw triggered pipeline enable on internally generated hts_event[hw_en_evtselect]" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 1. "HW_EN,Hw event triggerred Pipeline 3 enable '1': activate pipeline to receive hw event as described in hw_en_evtselect and hts_event_gen.evt_select '0' : hw event based pipeline is not enabled" "0,1" newline bitfld.long 0xC 0. "PIPE_EN,Pipeline 3 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_pipeline_control_4,Enable pipeline to activate all connected scheduler" bitfld.long 0x10 2.--4. "HW_EN_EVTSELECT,Hw triggered pipeline enable on internally generated hts_event[hw_en_evtselect]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 1. "HW_EN,Hw event triggerred Pipeline 4 enable '1': activate pipeline to receive hw event as described in hw_en_evtselect and hts_event_gen.evt_select '0' : hw event based pipeline is not enabled" "0,1" newline bitfld.long 0x10 0. "PIPE_EN,Pipeline 4 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1" line.long 0x14 "HTS__S_VBUSP__REGS_pipeline_control_5,Enable pipeline to activate all connected scheduler" bitfld.long 0x14 2.--4. "HW_EN_EVTSELECT,Hw triggered pipeline enable on internally generated hts_event[hw_en_evtselect]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 1. "HW_EN,Hw event triggerred Pipeline 5 enable '1': activate pipeline to receive hw event as described in hw_en_evtselect and hts_event_gen.evt_select '0' : hw event based pipeline is not enabled" "0,1" newline bitfld.long 0x14 0. "PIPE_EN,Pipeline 5 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1" line.long 0x18 "HTS__S_VBUSP__REGS_pipeline_control_6,Enable pipeline to activate all connected scheduler" bitfld.long 0x18 2.--4. "HW_EN_EVTSELECT,Hw triggered pipeline enable on internally generated hts_event[hw_en_evtselect]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 1. "HW_EN,Hw event triggerred Pipeline 6 enable '1': activate pipeline to receive hw event as described in hw_en_evtselect and hts_event_gen.evt_select '0' : hw event based pipeline is not enabled" "0,1" newline bitfld.long 0x18 0. "PIPE_EN,Pipeline 6 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_PID,HTS PID" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and new scheme. Spare bit to encode future schemes" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU indicator DSPS ==> 0x0 WTBU ==> 0x1 Processors ==> 0x2" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family. If there is no level of software compatibility a new FUNC number and hence PID should be assigned." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version. R as described in PDR with additional clarifications and definitions below. Must be easily ECO-able or controlled during fabrication. Ideally through a top level metal mask or e-fuse. This number is maintained/owned by IP design.." newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision. X as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. X is part of IP numbering X.Y.R.Z. X changes ONLY when: (1) There is a major feature addition. An.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library (CSL) / Drivers. 0 if non-custom." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision. Y as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. Y changes ONLY when: (1) Features are scaled (up or down). Flexibility exists in that this.." rgroup.long 0x48++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_pipe_dbg_cntl,Pipeline Debug Control register is used by debug software to control pipeline debug behavior" rbitfld.long 0x0 17.--19. "DEBUG_STATE,Current state of Debug activity" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "ABORT_DEBUG,'1' -> Abort Debug activity on debug enabled pipelines '0' no impact" "0,1" newline bitfld.long 0x0 6. "PIPE_DBG_DIS_6,'1' -> Pipeline6 doesn't respond to debug events '0' Pipeline5 respond to debug events" "0,1" newline bitfld.long 0x0 5. "PIPE_DBG_DIS_5,'1' -> Pipeline5 doesn't respond to debug events '0' Pipeline5 respond to debug events" "0,1" newline bitfld.long 0x0 4. "PIPE_DBG_DIS_4,'1' -> Pipeline4 doesn't respond to debug events '0' Pipeline4 respond to debug events" "0,1" newline bitfld.long 0x0 3. "PIPE_DBG_DIS_3,'1' -> Pipeline3 doesn't respond to debug events '0' Pipeline3 respond to debug events" "0,1" newline bitfld.long 0x0 2. "PIPE_DBG_DIS_2,'1' -> Pipeline2 doesn't respond to debug events '0' Pipeline2 respond to debug events" "0,1" newline bitfld.long 0x0 1. "PIPE_DBG_DIS_1,'1' -> Pipeline1 doesn't respond to debug events '0' Pipeline1 respond to debug events" "0,1" newline bitfld.long 0x0 0. "PIPE_DBG_DIS_0,'1' -> Pipeline0 doesn't respond to debug events '0' Pipeline0 respond to debug events" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_dbg_cap,Debug Capability register is used by debug software to determine which optional debug modules are present and how many instances of each module exist." bitfld.long 0x0 30. "DBG_INT_STEP_SUP,Indicates that debug execution control can determine if single step blocks or allows interrupts. b0 No step/interrupt control b1 Step interrupt control via DBG_INT_STEP_IN" "0,1" newline bitfld.long 0x0 29. "DBG_WP_DATA_SUP,Indicates if the WP resources has corresponding data qualification. b0 - Not supported. b1 - Data qualifiers are supported." "0: Not supported,1: Data qualifiers are supported" newline bitfld.long 0x0 28. "DBG_OWN_SUP,Indicates if the HWA supports an module ownership. v2.0 and above. b0 - Not Supported. b1 - Ownership supported." "0: Not Supported,1: Ownership supported" newline bitfld.long 0x0 27. "DBG_INDIRECT_SUP,Indicates if the HWA supports an indirect memory access port. v2.0 and above. b0 - Not Supported. b1 - Indirect port supported." "0: Not Supported,1: Indirect port supported" newline bitfld.long 0x0 26. "DBG_SWBP_SUP,Whether HWA Core supports SWBP or not. b0 - Not Supported. b1 - Supported." "0: Not Supported,1: Supported" newline bitfld.long 0x0 25. "DBQ_RESET_SUP,Whether HWA Core reset is supported or not which does not affect debug logic. b0 - Not Supported. b1 - Supported." "0: Not Supported,1: Supported" newline bitfld.long 0x0 24. "SYS_EXE_REQ,Whether HWA Core Execution status and control is supported. b0 - Not Supported. b1 - Supported." "0: Not Supported,1: Supported" newline bitfld.long 0x0 23. "TRIG_OUTPUT,b0 - Trigger Outputs are not supported. b1 - Trigger Outputs are supported." "0: Trigger Outputs are not supported,1: Trigger Outputs are supported" newline bitfld.long 0x0 22. "TRIG_INPUT,b0 - Trigger Inputs are not supported. b1 - Trigger Inputs are supported." "0: Trigger Inputs are not supported,1: Trigger Inputs are supported" newline bitfld.long 0x0 20.--21. "TRIG_CHNS,Number of Trigger Channels Supported. b00 ------ No channels supported. b01 ------ One channel supported. b10 ------ Two channels supported. Others ---- Reserved." "0: No channels supported,1: One channel supported,2: Two channels supported,?" newline hexmask.long.byte 0x0 16.--19. 1. "NUM_CNTRS,The number of counter modules that exist. The registers supporting the counter modules must be implemented consecutively in the memory map." newline hexmask.long.byte 0x0 12.--15. 1. "NUM_WPS,The number of watchpoint modules that exist. The registers supporting the watchpoint modules must be implemented consecutively in the memory map" newline hexmask.long.byte 0x0 8.--11. 1. "NUM_BPS,The number of breakpoint modules that exist. The registers supporting the breakpoint modules must be implemented consecutively in the memory map." newline hexmask.long.byte 0x0 4.--7. 1. "REV_MAJ,Major Revision" newline hexmask.long.byte 0x0 0.--3. 1. "REV_MIN,Minor Revision" rgroup.long 0x50++0x23 line.long 0x0 "HTS__S_VBUSP__REGS_dbg_cntl,Debug Control register is used by debug software to control all of the basic debug functions." bitfld.long 0x0 26. "DBG_RESET_OCC,Sticky status bit to reflect reset has been generated" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "DBG_EMU0_CNTL,EMU0 output control. The cross trigger output control. The value in this field determines the behavior of the outputs generated on EMU0. NOTE: The effect of setting any non-zero value is ignored if the HWA Core is currently in HALTED.." newline rbitfld.long 0x0 12. "DBG_HALT_EMU0,Execution halted due to trigger in on EMU0 input Set to '1' when halt due to EMU0 input completes Set to '0' when execution resumes" "0,1" newline rbitfld.long 0x0 11. "DBG_HALT_USER,Execution halted due to register update of DBG_HALT Set to '1' when halt due to DBG_HALT update completes Set to '0' when execution resumes" "0,1" newline rbitfld.long 0x0 10. "DBG_HALT_STEP,Execution halted due to single step completion Set to '1' when the single step completes Set to '0' when execution resumes" "0,1" newline rbitfld.long 0x0 7. "DBG_EXE_STAT,The execution status of the module Set to '1' when halted due to debug event Set to '0' when execution resumes" "0,1" newline bitfld.long 0x0 5. "DBG_EMU0_EN,EMU0 input trigger enable Writing '1' enables halting on the falling edge of the EMU0 input Writing '0' disables halts via EMU0 input" "0,1" newline bitfld.long 0x0 2. "DBG_SINGLE_STEP_EN,Single Step Execution enable. When this bit is set the accelerator core shall be halted upon execution of a single instruction. This is after the accelerator core has left the halted state by clearing the DBG_HALT control bit." "0,1" newline bitfld.long 0x0 1. "DBG_RESTART,Debug Restart Status bit.This bit is normally set when the DBG_HALT bit transitions from '1' to '0' when the natural execution state is entered.It is a sticky bit. It may also be set when a synchronous run causes the accelerator to leave.." "0,1" newline bitfld.long 0x0 0. "DBG_HALT,Global debug run control. The bit will be read as being set upon entry to HALTED state due to halted state being entered because of SWBP HWBP HWWP EMU0 / 1 trigger or manual halt requested through this control. Writing '1' when read '0'.." "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_hts_event_gen0,select one of internal hts_event of width 34 out of 3'b0.pipeline_eop[6:0].1'b0.start_frame_evt.2'b0.hwa_eop[8:0].2'b0.hwa_init[8:0] bus as hts_event0" hexmask.long.byte 0x4 0.--5. 1. "EVT_SELECT,internal hts_event index for hts_event_gen0" line.long 0x8 "HTS__S_VBUSP__REGS_hts_event_gen1,select one of internal hts_event of width 34 out of 3'b0.pipeline_eop[6:0].1'b0.start_frame_evt.2'b0.hwa_eop[8:0].2'b0.hwa_init[8:0] bus as hts_event1" hexmask.long.byte 0x8 0.--5. 1. "EVT_SELECT,internal hts_event index for hts_event_gen1" line.long 0xC "HTS__S_VBUSP__REGS_hts_event_gen2,select one of internal hts_event of width 34 out of 3'b0.pipeline_eop[6:0].1'b0.start_frame_evt.2'b0.hwa_eop[8:0].2'b0.hwa_init[8:0] bus as hts_event2" hexmask.long.byte 0xC 0.--5. 1. "EVT_SELECT,internal hts_event index for hts_event_gen2" line.long 0x10 "HTS__S_VBUSP__REGS_hts_event_gen3,select one of internal hts_event of width 34 out of 3'b0.pipeline_eop[6:0].1'b0.start_frame_evt.2'b0.hwa_eop[8:0].2'b0.hwa_init[8:0] bus as hts_event3" hexmask.long.byte 0x10 0.--5. 1. "EVT_SELECT,internal hts_event index for hts_event_gen3" line.long 0x14 "HTS__S_VBUSP__REGS_hts_event_gen4,select one of internal hts_event of width 34 out of 3'b0.pipeline_eop[6:0].1'b0.start_frame_evt.2'b0.hwa_eop[8:0].2'b0.hwa_init[8:0] bus as hts_event4" hexmask.long.byte 0x14 0.--5. 1. "EVT_SELECT,internal hts_event index for hts_event_gen4" line.long 0x18 "HTS__S_VBUSP__REGS_hts_event_gen5,select one of internal hts_event of width 34 out of 3'b0.pipeline_eop[6:0].1'b0.start_frame_evt.2'b0.hwa_eop[8:0].2'b0.hwa_init[8:0] bus as hts_event5" hexmask.long.byte 0x18 0.--5. 1. "EVT_SELECT,internal hts_event index for hts_event_gen5" line.long 0x1C "HTS__S_VBUSP__REGS_hts_event_gen6,select one of internal hts_event of width 34 out of 3'b0.pipeline_eop[6:0].1'b0.start_frame_evt.2'b0.hwa_eop[8:0].2'b0.hwa_init[8:0] bus as hts_event6" hexmask.long.byte 0x1C 0.--5. 1. "EVT_SELECT,internal hts_event index for hts_event_gen6" line.long 0x20 "HTS__S_VBUSP__REGS_hts_event_gen7,select one of internal hts_event of width 34 out of 3'b0.pipeline_eop[6:0].1'b0.start_frame_evt.2'b0.hwa_eop[8:0].2'b0.hwa_init[8:0] bus as hts_event7" hexmask.long.byte 0x20 0.--5. 1. "EVT_SELECT,internal hts_event index for hts_event_gen7" rgroup.long 0x100++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA0_scheduler_control,Scheduler Control Register" bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA0 Scheduler resources must not be read during halted state. '1'-> HWA0 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA0 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA0 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA0_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further start. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value. when enabled it triggers tdone_intr when (tdone_count==hop_thread_count) '0' -> No count ; Note that tdone_count value is.." "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA0_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA0 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA0 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA0_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA0 sch '0' --> Disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA0_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP feature." hexmask.long.word 0x10 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA0 scheduler skip-enabled prod socket" newline hexmask.long.word 0x10 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA0 scheduler skip-enabled prod socket" rgroup.long 0x120++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA0_cons0_control,Controlling consumer socket 0 for HWA0" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x128++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA0_cons1_control,Controlling consumer socket 1 for HWA0" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" rgroup.long 0x130++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA0_cons2_control,Controlling consumer socket 2 for HWA0" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 2" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1" rgroup.long 0x138++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA0_cons3_control,Controlling consumer socket 3 for HWA0" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 3" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 3 enable '0' Disable" "0,1" rgroup.long 0x140++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA0_cons4_control,Controlling consumer socket 4 for HWA0" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 4" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 4 enable '0' Disable" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA0_cons5_control,Controlling consumer socket 5 for HWA0" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 5" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 5 enable '0' Disable" "0,1" rgroup.long 0x160++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA0_prod0_control,Controlling producer socket0 for HWA0" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 0. tdone_mask[mask_select] applies to prod_socket0. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA0_prod0_buf_control,Controlling producer socket0 buffer for HWA0" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA0_prod0_count,Defining count values for pre/post load for generating pend by HWA0 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA0_pa0_control,control register to manage pattern adapter on HWA0 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA0_pa0_prodcount,count values for HWA0 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x180++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA0_prod1_control,Controlling producer socket1 for HWA0" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 1. tdone_mask[mask_select] applies to prod_socket1. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA0_prod1_buf_control,Controlling producer socket1 buffer for HWA0" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA0_prod1_count,Defining count values for pre/post load for generating pend by HWA0 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA0_pa1_control,control register to manage pattern adapter on HWA0 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA0_pa1_prodcount,count values for HWA0 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x1A0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA0_prod2_control,Controlling producer socket2 for HWA0" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 2. tdone_mask[mask_select] applies to prod_socket2. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA0_prod2_buf_control,Controlling producer socket2 buffer for HWA0" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA0_prod2_count,Defining count values for pre/post load for generating pend by HWA0 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA0_pa2_control,control register to manage pattern adapter on HWA0 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA0_pa2_prodcount,count values for HWA0 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x1C0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA0_prod3_control,Controlling producer socket3 for HWA0" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 3. tdone_mask[mask_select] applies to prod_socket3. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA0_prod3_buf_control,Controlling producer socket3 buffer for HWA0" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA0_prod3_count,Defining count values for pre/post load for generating pend by HWA0 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA0_pa3_control,control register to manage pattern adapter on HWA0 prod socket3" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA0_pa3_prodcount,count values for HWA0 prod socket3" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x1E0++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA0_prod4_control,Controlling producer socket4 for HWA0" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 4. tdone_mask[mask_select] applies to prod_socket4. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 4 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 4 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 4 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 4 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 4 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA0_prod4_buf_control,Controlling producer socket4 buffer for HWA0" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA0_prod4_count,Defining count values for pre/post load for generating pend by HWA0 prod4" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x200++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA0_prod5_control,Controlling producer socket5 for HWA0" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 5. tdone_mask[mask_select] applies to prod_socket5. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 5 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 5 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 5 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 5 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 5. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 5 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA0_prod5_buf_control,Controlling producer socket5 buffer for HWA0" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA0_prod5_count,Defining count values for pre/post load for generating pend by HWA0 prod5" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x220++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA0_prod6_control,Controlling producer socket6 for HWA0" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 6. tdone_mask[mask_select] applies to prod_socket6. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 6 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 6 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 6 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 6 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 6. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 6 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA0_prod6_buf_control,Controlling producer socket6 buffer for HWA0" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA0_prod6_count,Defining count values for pre/post load for generating pend by HWA0 prod6" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x360++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA1_scheduler_control,Scheduler Control Register" bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA1 Scheduler resources must not be read during halted state. '1'-> HWA1 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA1 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA1 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA1_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further start. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value. when enabled it triggers tdone_intr when (tdone_count==hop_thread_count) '0' -> No count ; Note that tdone_count value is.." "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA1_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA1 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA1 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA1_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA1 sch '0' --> Disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA1_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP feature." hexmask.long.word 0x10 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA1 scheduler skip-enabled prod socket" newline hexmask.long.word 0x10 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA1 scheduler skip-enabled prod socket" rgroup.long 0x380++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA1_cons0_control,Controlling consumer socket 0 for HWA1" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x388++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA1_cons1_control,Controlling consumer socket 1 for HWA1" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" rgroup.long 0x390++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA1_cons2_control,Controlling consumer socket 2 for HWA1" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 2" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1" rgroup.long 0x398++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA1_cons3_control,Controlling consumer socket 3 for HWA1" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 3" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 3 enable '0' Disable" "0,1" rgroup.long 0x3A0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA1_cons4_control,Controlling consumer socket 4 for HWA1" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 4" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 4 enable '0' Disable" "0,1" rgroup.long 0x3A8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA1_cons5_control,Controlling consumer socket 5 for HWA1" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 5" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 5 enable '0' Disable" "0,1" rgroup.long 0x3C0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA1_prod0_control,Controlling producer socket0 for HWA1" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 0. tdone_mask[mask_select] applies to prod_socket0. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA1_prod0_buf_control,Controlling producer socket0 buffer for HWA1" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA1_prod0_count,Defining count values for pre/post load for generating pend by HWA1 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA1_pa0_control,control register to manage pattern adapter on HWA1 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA1_pa0_prodcount,count values for HWA1 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x3E0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA1_prod1_control,Controlling producer socket1 for HWA1" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 1. tdone_mask[mask_select] applies to prod_socket1. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA1_prod1_buf_control,Controlling producer socket1 buffer for HWA1" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA1_prod1_count,Defining count values for pre/post load for generating pend by HWA1 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA1_pa1_control,control register to manage pattern adapter on HWA1 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA1_pa1_prodcount,count values for HWA1 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x400++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA1_prod2_control,Controlling producer socket2 for HWA1" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 2. tdone_mask[mask_select] applies to prod_socket2. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA1_prod2_buf_control,Controlling producer socket2 buffer for HWA1" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA1_prod2_count,Defining count values for pre/post load for generating pend by HWA1 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA1_pa2_control,control register to manage pattern adapter on HWA1 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA1_pa2_prodcount,count values for HWA1 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x420++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA1_prod3_control,Controlling producer socket3 for HWA1" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 3. tdone_mask[mask_select] applies to prod_socket3. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA1_prod3_buf_control,Controlling producer socket3 buffer for HWA1" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA1_prod3_count,Defining count values for pre/post load for generating pend by HWA1 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA1_pa3_control,control register to manage pattern adapter on HWA1 prod socket3" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA1_pa3_prodcount,count values for HWA1 prod socket3" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x440++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA1_prod4_control,Controlling producer socket4 for HWA1" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 4. tdone_mask[mask_select] applies to prod_socket4. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 4 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 4 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 4 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 4 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 4 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA1_prod4_buf_control,Controlling producer socket4 buffer for HWA1" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA1_prod4_count,Defining count values for pre/post load for generating pend by HWA1 prod4" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x460++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA1_prod5_control,Controlling producer socket5 for HWA1" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 5. tdone_mask[mask_select] applies to prod_socket5. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 5 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 5 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 5 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 5 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 5. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 5 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA1_prod5_buf_control,Controlling producer socket5 buffer for HWA1" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA1_prod5_count,Defining count values for pre/post load for generating pend by HWA1 prod5" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x480++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA1_prod6_control,Controlling producer socket6 for HWA1" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 6. tdone_mask[mask_select] applies to prod_socket6. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 6 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 6 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 6 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 6 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 6. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 6 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA1_prod6_buf_control,Controlling producer socket6 buffer for HWA1" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA1_prod6_count,Defining count values for pre/post load for generating pend by HWA1 prod6" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x5C0++0xF line.long 0x0 "HTS__S_VBUSP__REGS_HWA2_scheduler_control,Scheduler Control Register" bitfld.long 0x0 22. "EOR_EN,'1' -> LDC REGION/sub-frame feature enabled '0' LDC works in Frame mode only" "0,1" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA2 Scheduler resources must not be read during halted state. '1'-> HWA2 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA2 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA2 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA2_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value . when enabled it triggers tdone_intr when (tdone_count==hop_thread_count) '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA2_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA2 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA2 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA2_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA2 sch '0' --> Disable" "0,1" rgroup.long 0x5E0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA2_cons0_control,Controlling consumer socket 0 for HWA2" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA2 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x5E8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA2_cons1_control,Controlling consumer socket 1 for HWA2" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA2 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" rgroup.long 0x5F0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA2_cons2_control,Controlling consumer socket 2 for HWA2" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA2 cons socket 2" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1" rgroup.long 0x620++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA2_prod0_control,Controlling producer socket0 for HWA2" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 0. tdone_mask[mask_select] applies to prod_socket0. Valid value in range 0 - 4" newline bitfld.long 0x0 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 0 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (0+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior;,1: Prod Socket 0 is used to trigger DMA channel to..,2: Prod Socket 0 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x0 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA2_prod0_buf_control,Controlling producer socket0 buffer for HWA2" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA2_prod0_count,Defining count values for pre/post load for generating pend by HWA2 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA2_pa0_control,control register to manage pattern adapter on HWA2 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA2_pa0_prodcount,count values for HWA2 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x640++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA2_prod1_control,Controlling producer socket1 for HWA2" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 1. tdone_mask[mask_select] applies to prod_socket1. Valid value in range 0 - 4" newline bitfld.long 0x0 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 1 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (1+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior;,1: Prod Socket 1 is used to trigger DMA channel to..,2: Prod Socket 1 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x0 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA2_prod1_buf_control,Controlling producer socket1 buffer for HWA2" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA2_prod1_count,Defining count values for pre/post load for generating pend by HWA2 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA2_pa1_control,control register to manage pattern adapter on HWA2 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA2_pa1_prodcount,count values for HWA2 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x660++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA2_prod2_control,Controlling producer socket2 for HWA2" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 2. tdone_mask[mask_select] applies to prod_socket2. Valid value in range 0 - 4" newline bitfld.long 0x0 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 2 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (2+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior;,1: Prod Socket 2 is used to trigger DMA channel to..,2: Prod Socket 2 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x0 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA2_prod2_buf_control,Controlling producer socket2 buffer for HWA2" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA2_prod2_count,Defining count values for pre/post load for generating pend by HWA2 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA2_pa2_control,control register to manage pattern adapter on HWA2 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA2_pa2_prodcount,count values for HWA2 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x680++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA2_prod3_control,Controlling producer socket3 for HWA2" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 3. tdone_mask[mask_select] applies to prod_socket3. Valid value in range 0 - 4" newline bitfld.long 0x0 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 3 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (3+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior;,1: Prod Socket 3 is used to trigger DMA channel to..,2: Prod Socket 3 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x0 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA2_prod3_buf_control,Controlling producer socket3 buffer for HWA2" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA2_prod3_count,Defining count values for pre/post load for generating pend by HWA2 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA2_pa3_control,control register to manage pattern adapter on HWA2 prod socket3" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA2_pa3_prodcount,count values for HWA2 prod socket3" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x6A0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA2_prod4_control,Controlling producer socket4 for HWA2" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 4. tdone_mask[mask_select] applies to prod_socket4. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 4 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 4 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 4 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 4 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA2_prod4_buf_control,Controlling producer socket4 buffer for HWA2" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA2_prod4_count,Defining count values for pre/post load for generating pend by HWA2 prod4" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA2_pa4_control,control register to manage pattern adapter on HWA2 prod socket4" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA2_pa4_prodcount,count values for HWA2 prod socket4" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x6C0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA2_prod5_control,Controlling producer socket5 for HWA2" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 5. tdone_mask[mask_select] applies to prod_socket5. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 5 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 5 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 5 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 5. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 5 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA2_prod5_buf_control,Controlling producer socket5 buffer for HWA2" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA2_prod5_count,Defining count values for pre/post load for generating pend by HWA2 prod5" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA2_pa5_control,control register to manage pattern adapter on HWA2 prod socket5" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA2_pa5_prodcount,count values for HWA2 prod socket5" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x6E0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA2_prod6_control,Controlling producer socket6 for HWA2" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 6. tdone_mask[mask_select] applies to prod_socket6. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 6 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 6 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 6 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 6. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 6 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA2_prod6_buf_control,Controlling producer socket6 buffer for HWA2" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA2_prod6_count,Defining count values for pre/post load for generating pend by HWA2 prod6" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA2_pa6_control,control register to manage pattern adapter on HWA2 prod socket6" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA2_pa6_prodcount,count values for HWA2 prod socket6" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x700++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA2_prod7_control,Controlling producer socket7 for HWA2" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 7. tdone_mask[mask_select] applies to prod_socket7. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 7 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 7 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 7 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 7. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 7 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA2_prod7_buf_control,Controlling producer socket7 buffer for HWA2" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA2_prod7_count,Defining count values for pre/post load for generating pend by HWA2 prod7" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x820++0xF line.long 0x0 "HTS__S_VBUSP__REGS_HWA3_scheduler_control,Scheduler Control Register" bitfld.long 0x0 22. "EOR_EN,'1' -> LDC REGION/sub-frame feature enabled '0' LDC works in Frame mode only" "0,1" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA3 Scheduler resources must not be read during halted state. '1'-> HWA3 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA3 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA3 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA3_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value . when enabled it triggers tdone_intr when (tdone_count==hop_thread_count) '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA3_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA3 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA3 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA3_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA3 sch '0' --> Disable" "0,1" rgroup.long 0x840++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA3_cons0_control,Controlling consumer socket 0 for HWA3" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA3 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x848++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA3_cons1_control,Controlling consumer socket 1 for HWA3" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA3 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" rgroup.long 0x850++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA3_cons2_control,Controlling consumer socket 2 for HWA3" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA3 cons socket 2" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1" rgroup.long 0x880++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA3_prod0_control,Controlling producer socket0 for HWA3" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 0. tdone_mask[mask_select] applies to prod_socket0. Valid value in range 0 - 4" newline bitfld.long 0x0 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 0 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (0+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior;,1: Prod Socket 0 is used to trigger DMA channel to..,2: Prod Socket 0 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x0 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA3_prod0_buf_control,Controlling producer socket0 buffer for HWA3" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA3_prod0_count,Defining count values for pre/post load for generating pend by HWA3 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA3_pa0_control,control register to manage pattern adapter on HWA3 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA3_pa0_prodcount,count values for HWA3 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x8A0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA3_prod1_control,Controlling producer socket1 for HWA3" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 1. tdone_mask[mask_select] applies to prod_socket1. Valid value in range 0 - 4" newline bitfld.long 0x0 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 1 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (1+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior;,1: Prod Socket 1 is used to trigger DMA channel to..,2: Prod Socket 1 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x0 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA3_prod1_buf_control,Controlling producer socket1 buffer for HWA3" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA3_prod1_count,Defining count values for pre/post load for generating pend by HWA3 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA3_pa1_control,control register to manage pattern adapter on HWA3 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA3_pa1_prodcount,count values for HWA3 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x8C0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA3_prod2_control,Controlling producer socket2 for HWA3" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 2. tdone_mask[mask_select] applies to prod_socket2. Valid value in range 0 - 4" newline bitfld.long 0x0 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 2 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (2+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior;,1: Prod Socket 2 is used to trigger DMA channel to..,2: Prod Socket 2 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x0 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA3_prod2_buf_control,Controlling producer socket2 buffer for HWA3" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA3_prod2_count,Defining count values for pre/post load for generating pend by HWA3 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA3_pa2_control,control register to manage pattern adapter on HWA3 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA3_pa2_prodcount,count values for HWA3 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x8E0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA3_prod3_control,Controlling producer socket3 for HWA3" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 3. tdone_mask[mask_select] applies to prod_socket3. Valid value in range 0 - 4" newline bitfld.long 0x0 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 3 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (3+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior;,1: Prod Socket 3 is used to trigger DMA channel to..,2: Prod Socket 3 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x0 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA3_prod3_buf_control,Controlling producer socket3 buffer for HWA3" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA3_prod3_count,Defining count values for pre/post load for generating pend by HWA3 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA3_pa3_control,control register to manage pattern adapter on HWA3 prod socket3" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA3_pa3_prodcount,count values for HWA3 prod socket3" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x900++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA3_prod4_control,Controlling producer socket4 for HWA3" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 4. tdone_mask[mask_select] applies to prod_socket4. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 4 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 4 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 4 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 4 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA3_prod4_buf_control,Controlling producer socket4 buffer for HWA3" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA3_prod4_count,Defining count values for pre/post load for generating pend by HWA3 prod4" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA3_pa4_control,control register to manage pattern adapter on HWA3 prod socket4" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA3_pa4_prodcount,count values for HWA3 prod socket4" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x920++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA3_prod5_control,Controlling producer socket5 for HWA3" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 5. tdone_mask[mask_select] applies to prod_socket5. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 5 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 5 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 5 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 5. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 5 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA3_prod5_buf_control,Controlling producer socket5 buffer for HWA3" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA3_prod5_count,Defining count values for pre/post load for generating pend by HWA3 prod5" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA3_pa5_control,control register to manage pattern adapter on HWA3 prod socket5" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA3_pa5_prodcount,count values for HWA3 prod socket5" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x940++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA3_prod6_control,Controlling producer socket6 for HWA3" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 6. tdone_mask[mask_select] applies to prod_socket6. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 6 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 6 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 6 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 6. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 6 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA3_prod6_buf_control,Controlling producer socket6 buffer for HWA3" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA3_prod6_count,Defining count values for pre/post load for generating pend by HWA3 prod6" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA3_pa6_control,control register to manage pattern adapter on HWA3 prod socket6" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA3_pa6_prodcount,count values for HWA3 prod socket6" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x960++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA3_prod7_control,Controlling producer socket7 for HWA3" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 7. tdone_mask[mask_select] applies to prod_socket7. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 7 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 7 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 7 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 7. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 7 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA3_prod7_buf_control,Controlling producer socket7 buffer for HWA3" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA3_prod7_count,Defining count values for pre/post load for generating pend by HWA3 prod7" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xA80++0xF line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_scheduler_control,Scheduler Control Register" bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA4 Scheduler resources must not be read during halted state. '1'-> HWA4 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA4 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA4 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA4_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value. when enabled it triggers tdone_intr when (tdone_count==hop_thread_count) '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA4_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA4 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA4 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA4_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA4 sch '0' --> Disable" "0,1" rgroup.long 0xAA0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_cons0_control,Controlling consumer socket 0 for HWA4" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA4 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0xAA8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_cons1_control,Controlling consumer socket 1 for HWA4" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA4 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" rgroup.long 0xAB0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_cons2_control,Controlling consumer socket 2 for HWA4" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA4 cons socket 2" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1" rgroup.long 0xAE0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_prod0_control,Controlling producer socket0 for HWA4" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 0. tdone_mask[mask_select] applies to prod_socket0. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA4_prod0_buf_control,Controlling producer socket0 buffer for HWA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA4_prod0_count,Defining count values for pre/post load for generating pend by HWA4 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA4_pa0_control,control register to manage pattern adapter on HWA4 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA4_pa0_prodcount,count values for HWA4 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0xB00++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_prod1_control,Controlling producer socket1 for HWA4" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 1. tdone_mask[mask_select] applies to prod_socket1. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA4_prod1_buf_control,Controlling producer socket1 buffer for HWA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA4_prod1_count,Defining count values for pre/post load for generating pend by HWA4 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA4_pa1_control,control register to manage pattern adapter on HWA4 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA4_pa1_prodcount,count values for HWA4 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0xB20++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_prod2_control,Controlling producer socket2 for HWA4" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 2. tdone_mask[mask_select] applies to prod_socket2. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA4_prod2_buf_control,Controlling producer socket2 buffer for HWA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA4_prod2_count,Defining count values for pre/post load for generating pend by HWA4 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xB40++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_prod3_control,Controlling producer socket3 for HWA4" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 3. tdone_mask[mask_select] applies to prod_socket3. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA4_prod3_buf_control,Controlling producer socket3 buffer for HWA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA4_prod3_count,Defining count values for pre/post load for generating pend by HWA4 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xB60++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_prod4_control,Controlling producer socket4 for HWA4" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 4. tdone_mask[mask_select] applies to prod_socket4. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 4 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 4 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 4 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 4 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA4_prod4_buf_control,Controlling producer socket4 buffer for HWA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA4_prod4_count,Defining count values for pre/post load for generating pend by HWA4 prod4" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xB80++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_prod5_control,Controlling producer socket5 for HWA4" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 5. tdone_mask[mask_select] applies to prod_socket5. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 5 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 5 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 5 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 5. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 5 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA4_prod5_buf_control,Controlling producer socket5 buffer for HWA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA4_prod5_count,Defining count values for pre/post load for generating pend by HWA4 prod5" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xBA0++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_prod6_control,Controlling producer socket6 for HWA4" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 6. tdone_mask[mask_select] applies to prod_socket6. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 6 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 6 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 6 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 6. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 6 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA4_prod6_buf_control,Controlling producer socket6 buffer for HWA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA4_prod6_count,Defining count values for pre/post load for generating pend by HWA4 prod6" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xBC0++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_prod7_control,Controlling producer socket7 for HWA4" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 7. tdone_mask[mask_select] applies to prod_socket7. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 7 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 7 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 7 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 7. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 7 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA4_prod7_buf_control,Controlling producer socket7 buffer for HWA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA4_prod7_count,Defining count values for pre/post load for generating pend by HWA4 prod7" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xBE0++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_prod8_control,Controlling producer socket8 for HWA4" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 8. tdone_mask[mask_select] applies to prod_socket8. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 8 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 8 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 8 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 8. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 8 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA4_prod8_buf_control,Controlling producer socket8 buffer for HWA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA4_prod8_count,Defining count values for pre/post load for generating pend by HWA4 prod8" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xC00++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_prod9_control,Controlling producer socket9 for HWA4" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 9. tdone_mask[mask_select] applies to prod_socket9. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 9 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 9 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 9 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 9. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 9 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA4_prod9_buf_control,Controlling producer socket9 buffer for HWA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA4_prod9_count,Defining count values for pre/post load for generating pend by HWA4 prod9" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xC20++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA4_prod10_control,Controlling producer socket10 for HWA4" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 10. tdone_mask[mask_select] applies to prod_socket10. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 10 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 10 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 10 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 10. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 10 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA4_prod10_buf_control,Controlling producer socket10 buffer for HWA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA4_prod10_count,Defining count values for pre/post load for generating pend by HWA4 prod10" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xCE0++0xF line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_scheduler_control,Scheduler Control Register" bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA5 Scheduler resources must not be read during halted state. '1'-> HWA5 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA5 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA5 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA5_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value. when enabled it triggers tdone_intr when (tdone_count==hop_thread_count) '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA5_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA5 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA5 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA5_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA5 sch '0' --> Disable" "0,1" rgroup.long 0xD00++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_cons0_control,Controlling consumer socket 0 for HWA5" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA5 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0xD08++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_cons1_control,Controlling consumer socket 1 for HWA5" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA5 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" rgroup.long 0xD10++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_cons2_control,Controlling consumer socket 2 for HWA5" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA5 cons socket 2" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1" rgroup.long 0xD40++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_prod0_control,Controlling producer socket0 for HWA5" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 0. tdone_mask[mask_select] applies to prod_socket0. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA5_prod0_buf_control,Controlling producer socket0 buffer for HWA5" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA5_prod0_count,Defining count values for pre/post load for generating pend by HWA5 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA5_pa0_control,control register to manage pattern adapter on HWA5 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA5_pa0_prodcount,count values for HWA5 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0xD60++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_prod1_control,Controlling producer socket1 for HWA5" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 1. tdone_mask[mask_select] applies to prod_socket1. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA5_prod1_buf_control,Controlling producer socket1 buffer for HWA5" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA5_prod1_count,Defining count values for pre/post load for generating pend by HWA5 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA5_pa1_control,control register to manage pattern adapter on HWA5 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA5_pa1_prodcount,count values for HWA5 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0xD80++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_prod2_control,Controlling producer socket2 for HWA5" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 2. tdone_mask[mask_select] applies to prod_socket2. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA5_prod2_buf_control,Controlling producer socket2 buffer for HWA5" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA5_prod2_count,Defining count values for pre/post load for generating pend by HWA5 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xDA0++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_prod3_control,Controlling producer socket3 for HWA5" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 3. tdone_mask[mask_select] applies to prod_socket3. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA5_prod3_buf_control,Controlling producer socket3 buffer for HWA5" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA5_prod3_count,Defining count values for pre/post load for generating pend by HWA5 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xDC0++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_prod4_control,Controlling producer socket4 for HWA5" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 4. tdone_mask[mask_select] applies to prod_socket4. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 4 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 4 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 4 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 4 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA5_prod4_buf_control,Controlling producer socket4 buffer for HWA5" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA5_prod4_count,Defining count values for pre/post load for generating pend by HWA5 prod4" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xDE0++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_prod5_control,Controlling producer socket5 for HWA5" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 5. tdone_mask[mask_select] applies to prod_socket5. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 5 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 5 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 5 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 5. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 5 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA5_prod5_buf_control,Controlling producer socket5 buffer for HWA5" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA5_prod5_count,Defining count values for pre/post load for generating pend by HWA5 prod5" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xE00++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_prod6_control,Controlling producer socket6 for HWA5" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 6. tdone_mask[mask_select] applies to prod_socket6. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 6 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 6 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 6 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 6. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 6 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA5_prod6_buf_control,Controlling producer socket6 buffer for HWA5" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA5_prod6_count,Defining count values for pre/post load for generating pend by HWA5 prod6" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xE20++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_prod7_control,Controlling producer socket7 for HWA5" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 7. tdone_mask[mask_select] applies to prod_socket7. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 7 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 7 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 7 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 7. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 7 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA5_prod7_buf_control,Controlling producer socket7 buffer for HWA5" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA5_prod7_count,Defining count values for pre/post load for generating pend by HWA5 prod7" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xE40++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_prod8_control,Controlling producer socket8 for HWA5" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 8. tdone_mask[mask_select] applies to prod_socket8. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 8 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 8 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 8 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 8. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 8 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA5_prod8_buf_control,Controlling producer socket8 buffer for HWA5" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA5_prod8_count,Defining count values for pre/post load for generating pend by HWA5 prod8" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xE60++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_prod9_control,Controlling producer socket9 for HWA5" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 9. tdone_mask[mask_select] applies to prod_socket9. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 9 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 9 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 9 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 9. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 9 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA5_prod9_buf_control,Controlling producer socket9 buffer for HWA5" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA5_prod9_count,Defining count values for pre/post load for generating pend by HWA5 prod9" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xE80++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA5_prod10_control,Controlling producer socket10 for HWA5" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 10. tdone_mask[mask_select] applies to prod_socket10. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 10 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 10 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 10 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 10. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 10 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA5_prod10_buf_control,Controlling producer socket10 buffer for HWA5" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA5_prod10_count,Defining count values for pre/post load for generating pend by HWA5 prod10" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0xF40++0xF line.long 0x0 "HTS__S_VBUSP__REGS_HWA6_scheduler_control,Scheduler Control Register" bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA6 Scheduler resources must not be read during halted state. '1'-> HWA6 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA6 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA6 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA6_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value . when enabled it triggers tdone_intr when (tdone_count==hop_thread_count) '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA6_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA6 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA6 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA6_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA6 sch '0' --> Disable" "0,1" rgroup.long 0xF60++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA6_cons0_control,Controlling consumer socket 0 for HWA6" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA6 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0xF68++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA6_cons1_control,Controlling consumer socket 1 for HWA6" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA6 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" rgroup.long 0xFA0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA6_prod0_control,Controlling producer socket0 for HWA6" bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA6 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA6_prod0_buf_control,Controlling producer socket0 buffer for HWA6" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA6_prod0_count,Defining count values for pre/post load for generating pend by HWA6 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA6_pa0_control,control register to manage pattern adapter on HWA6 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA6_pa0_prodcount,count values for HWA6 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0xFC0++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA6_prod1_control,Controlling producer socket1 for HWA6" bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA6 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA6_prod1_buf_control,Controlling producer socket1 buffer for HWA6" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA6_prod1_count,Defining count values for pre/post load for generating pend by HWA6 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x11A0++0xF line.long 0x0 "HTS__S_VBUSP__REGS_HWA7_scheduler_control,Scheduler Control Register" bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA7 Scheduler resources must not be read during halted state. '1'-> HWA7 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA7 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA7 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA7_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further start. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value . when enabled it triggers tdone_intr when (tdone_count==hop_thread_count) '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA7_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA7 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA7 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA7_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA7 sch '0' --> Disable" "0,1" rgroup.long 0x11C0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA7_cons0_control,Controlling consumer socket 0 for HWA7" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x11C8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA7_cons1_control,Controlling consumer socket 1 for HWA7" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" rgroup.long 0x11D0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA7_cons2_control,Controlling consumer socket 2 for HWA7" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 2" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1" rgroup.long 0x11D8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA7_cons3_control,Controlling consumer socket 3 for HWA7" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 3" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 3 enable '0' Disable" "0,1" rgroup.long 0x11E0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA7_cons4_control,Controlling consumer socket 4 for HWA7" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 4" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 4 enable '0' Disable" "0,1" rgroup.long 0x1200++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA7_prod0_control,Controlling producer socket0 for HWA7" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 0. tdone_mask[mask_select] applies to prod_socket0. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA7_prod0_buf_control,Controlling producer socket0 buffer for HWA7" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA7_prod0_count,Defining count values for pre/post load for generating pend by HWA7 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA7_pa0_control,control register to manage pattern adapter on HWA7 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA7_pa0_prodcount,count values for HWA7 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x1220++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA7_prod1_control,Controlling producer socket1 for HWA7" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 1. tdone_mask[mask_select] applies to prod_socket1. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA7_prod1_buf_control,Controlling producer socket1 buffer for HWA7" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA7_prod1_count,Defining count values for pre/post load for generating pend by HWA7 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA7_pa1_control,control register to manage pattern adapter on HWA7 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA7_pa1_prodcount,count values for HWA7 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x1240++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA7_prod2_control,Controlling producer socket2 for HWA7" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 2. tdone_mask[mask_select] applies to prod_socket2. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA7_prod2_buf_control,Controlling producer socket2 buffer for HWA7" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA7_prod2_count,Defining count values for pre/post load for generating pend by HWA7 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA7_pa2_control,control register to manage pattern adapter on HWA7 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA7_pa2_prodcount,count values for HWA7 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x1260++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA7_prod3_control,Controlling producer socket3 for HWA7" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 3. tdone_mask[mask_select] applies to prod_socket3. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA7_prod3_buf_control,Controlling producer socket3 buffer for HWA7" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA7_prod3_count,Defining count values for pre/post load for generating pend by HWA7 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA7_pa3_control,control register to manage pattern adapter on HWA7 prod socket3" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA7_pa3_prodcount,count values for HWA7 prod socket3" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x1280++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA7_prod4_control,Controlling producer socket4 for HWA7" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 4. tdone_mask[mask_select] applies to prod_socket4. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 4 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 4 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 4 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 4 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA7_prod4_buf_control,Controlling producer socket4 buffer for HWA7" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA7_prod4_count,Defining count values for pre/post load for generating pend by HWA7 prod4" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x1400++0xF line.long 0x0 "HTS__S_VBUSP__REGS_HWA8_scheduler_control,Scheduler Control Register" bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA8 Scheduler resources must not be read during halted state. '1'-> HWA8 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA8 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA8 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA8_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further start. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value . when enabled it triggers tdone_intr when (tdone_count==hop_thread_count) '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA8_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA8 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA8 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1" line.long 0xC "HTS__S_VBUSP__REGS_HWA8_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA8 sch '0' --> Disable" "0,1" rgroup.long 0x1420++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA8_cons0_control,Controlling consumer socket 0 for HWA8" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x1428++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA8_cons1_control,Controlling consumer socket 1 for HWA8" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" rgroup.long 0x1430++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA8_cons2_control,Controlling consumer socket 2 for HWA8" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 2" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1" rgroup.long 0x1438++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA8_cons3_control,Controlling consumer socket 3 for HWA8" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 3" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 3 enable '0' Disable" "0,1" rgroup.long 0x1440++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA8_cons4_control,Controlling consumer socket 4 for HWA8" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 4" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 4 enable '0' Disable" "0,1" rgroup.long 0x1460++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA8_prod0_control,Controlling producer socket0 for HWA8" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 0. tdone_mask[mask_select] applies to prod_socket0. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA8_prod0_buf_control,Controlling producer socket0 buffer for HWA8" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA8_prod0_count,Defining count values for pre/post load for generating pend by HWA8 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA8_pa0_control,control register to manage pattern adapter on HWA8 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA8_pa0_prodcount,count values for HWA8 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x1480++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA8_prod1_control,Controlling producer socket1 for HWA8" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 1. tdone_mask[mask_select] applies to prod_socket1. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA8_prod1_buf_control,Controlling producer socket1 buffer for HWA8" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA8_prod1_count,Defining count values for pre/post load for generating pend by HWA8 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA8_pa1_control,control register to manage pattern adapter on HWA8 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA8_pa1_prodcount,count values for HWA8 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x14A0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA8_prod2_control,Controlling producer socket2 for HWA8" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 2. tdone_mask[mask_select] applies to prod_socket2. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA8_prod2_buf_control,Controlling producer socket2 buffer for HWA8" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA8_prod2_count,Defining count values for pre/post load for generating pend by HWA8 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA8_pa2_control,control register to manage pattern adapter on HWA8 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA8_pa2_prodcount,count values for HWA8 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x14C0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA8_prod3_control,Controlling producer socket3 for HWA8" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 3. tdone_mask[mask_select] applies to prod_socket3. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA8_prod3_buf_control,Controlling producer socket3 buffer for HWA8" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA8_prod3_count,Defining count values for pre/post load for generating pend by HWA8 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA8_pa3_control,control register to manage pattern adapter on HWA8 prod socket3" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA8_pa3_prodcount,count values for HWA8 prod socket3" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x14E0++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA8_prod4_control,Controlling producer socket4 for HWA8" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 4. tdone_mask[mask_select] applies to prod_socket4. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 4 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 4 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 4 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 4 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA8_prod4_buf_control,Controlling producer socket4 buffer for HWA8" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA8_prod4_count,Defining count values for pre/post load for generating pend by HWA8 prod4" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x1D80++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_HWA12_scheduler_control,Scheduler Control Register" bitfld.long 0x0 25. "CHANNEL_LINK_EN,'1' -> Trigger dma_channel_no for chanel_count_set0.count0 times --> Trigger dma_channel_no+1 for chanel_count_set0.count1 times --> Trigger dma_channel_no+2 for chanel_count_set1.count0 times .. repeat till either total count reaches HOP.." "0,1" newline bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "0,1" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1" newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA12" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA12 Scheduler resources must not be read during halted state. '1'-> HWA12 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA12 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA12 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA12_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x1D90++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA12_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP feature." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA12 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA12 scheduler skip-enabled prod socket" rgroup.long 0x1DA0++0x17 line.long 0x0 "HTS__S_VBUSP__REGS_HWA12_channel_count_set0,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x0 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+1 HWA12_channel_count_set0.count1 times before linking to next HWA12_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x0 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+0 HWA12_channel_count_set0.count0 times before linking to count1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA12_channel_count_set1,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x4 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+3 HWA12_channel_count_set1.count1 times before linking to next HWA12_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x4 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+2 HWA12_channel_count_set1.count0 times before linking to count1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA12_channel_count_set2,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x8 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+5 HWA12_channel_count_set2.count1 times before linking to next HWA12_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x8 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+4 HWA12_channel_count_set2.count0 times before linking to count1" line.long 0xC "HTS__S_VBUSP__REGS_HWA12_channel_count_set3,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0xC 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+7 HWA12_channel_count_set3.count1 times before linking to next HWA12_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0xC 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+6 HWA12_channel_count_set3.count0 times before linking to count1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA12_channel_count_set4,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x10 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+9 HWA12_channel_count_set4.count1 times before linking to next HWA12_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x10 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+8 HWA12_channel_count_set4.count0 times before linking to count1" line.long 0x14 "HTS__S_VBUSP__REGS_HWA12_channel_count_set5,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x14 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+11 HWA12_channel_count_set5.count1 times before linking to next HWA12_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x14 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+10 HWA12_channel_count_set5.count0 times before linking to count1" rgroup.long 0x1DE0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA12_cons0_control,Controlling consumer socket 0 for HWA12" bitfld.long 0x0 31. "EHWA_PROD,'1' -> spare consumer is connected to external host producer '0' --> no external host producer" "0,1" newline bitfld.long 0x0 30. "SET_PEND,writing '1' sets pend on consumer socket" "0,1" newline hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA12 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x1DE8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA12_cons1_control,Controlling consumer socket 1 for HWA12" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA12 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" rgroup.long 0x1E20++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA12_prod0_control,Controlling producer socket0 for HWA12" bitfld.long 0x0 31. "EHWA_CONS,'1' -> spare consumer is connected to external host consumer '0' --> no external host consumer" "0,1" newline bitfld.long 0x0 30. "PROD_DEC,writing '1' decrement prod count value" "0,1" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA12 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA12_prod0_buf_control,Controlling producer socket0 buffer for HWA12" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA12_prod0_count,Defining count values for pre/post load for generating pend by HWA12 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA12_pa0_control,control register to manage pattern adapter on HWA12 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA12_pa0_prodcount,count values for HWA12 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x1E40++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA12_prod1_control,Controlling producer socket1 for HWA12" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA12 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA12_prod1_buf_control,Controlling producer socket1 buffer for HWA12" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA12_prod1_count,Defining count values for pre/post load for generating pend by HWA12 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA12_pa1_control,control register to manage pattern adapter on HWA12 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA12_pa1_prodcount,count values for HWA12 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x1E60++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA12_prod2_control,Controlling producer socket2 for HWA12" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA12 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA12_prod2_buf_control,Controlling producer socket2 buffer for HWA12" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA12_prod2_count,Defining count values for pre/post load for generating pend by HWA12 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA12_pa2_control,control register to manage pattern adapter on HWA12 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA12_pa2_prodcount,count values for HWA12 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x1E80++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA12_prod3_control,Controlling producer socket3 for HWA12" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA12 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA12_prod3_buf_control,Controlling producer socket3 buffer for HWA12" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA12_prod3_count,Defining count values for pre/post load for generating pend by HWA12 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x2020++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_HWA13_scheduler_control,Scheduler Control Register" bitfld.long 0x0 25. "CHANNEL_LINK_EN,'1' -> Trigger dma_channel_no for chanel_count_set0.count0 times --> Trigger dma_channel_no+1 for chanel_count_set0.count1 times --> Trigger dma_channel_no+2 for chanel_count_set1.count0 times .. repeat till either total count reaches HOP.." "0,1" newline bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "0,1" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1" newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA13" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA13 Scheduler resources must not be read during halted state. '1'-> HWA13 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA13 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA13 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA13_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x2030++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA13_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP feature." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA13 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA13 scheduler skip-enabled prod socket" rgroup.long 0x2040++0x17 line.long 0x0 "HTS__S_VBUSP__REGS_HWA13_channel_count_set0,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x0 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+1 HWA13_channel_count_set0.count1 times before linking to next HWA13_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x0 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+0 HWA13_channel_count_set0.count0 times before linking to count1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA13_channel_count_set1,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x4 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+3 HWA13_channel_count_set1.count1 times before linking to next HWA13_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x4 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+2 HWA13_channel_count_set1.count0 times before linking to count1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA13_channel_count_set2,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x8 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+5 HWA13_channel_count_set2.count1 times before linking to next HWA13_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x8 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+4 HWA13_channel_count_set2.count0 times before linking to count1" line.long 0xC "HTS__S_VBUSP__REGS_HWA13_channel_count_set3,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0xC 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+7 HWA13_channel_count_set3.count1 times before linking to next HWA13_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0xC 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+6 HWA13_channel_count_set3.count0 times before linking to count1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA13_channel_count_set4,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x10 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+9 HWA13_channel_count_set4.count1 times before linking to next HWA13_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x10 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+8 HWA13_channel_count_set4.count0 times before linking to count1" line.long 0x14 "HTS__S_VBUSP__REGS_HWA13_channel_count_set5,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x14 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+11 HWA13_channel_count_set5.count1 times before linking to next HWA13_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x14 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+10 HWA13_channel_count_set5.count0 times before linking to count1" rgroup.long 0x2080++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA13_cons0_control,Controlling consumer socket 0 for HWA13" bitfld.long 0x0 31. "EHWA_PROD,'1' -> spare consumer is connected to external host producer '0' --> no external host producer" "0,1" newline bitfld.long 0x0 30. "SET_PEND,writing '1' sets pend on consumer socket" "0,1" newline hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA13 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x2088++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA13_cons1_control,Controlling consumer socket 1 for HWA13" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA13 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" rgroup.long 0x20C0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA13_prod0_control,Controlling producer socket0 for HWA13" bitfld.long 0x0 31. "EHWA_CONS,'1' -> spare consumer is connected to external host consumer '0' --> no external host consumer" "0,1" newline bitfld.long 0x0 30. "PROD_DEC,writing '1' decrement prod count value" "0,1" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA13 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA13_prod0_buf_control,Controlling producer socket0 buffer for HWA13" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA13_prod0_count,Defining count values for pre/post load for generating pend by HWA13 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA13_pa0_control,control register to manage pattern adapter on HWA13 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA13_pa0_prodcount,count values for HWA13 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x20E0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA13_prod1_control,Controlling producer socket1 for HWA13" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA13 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA13_prod1_buf_control,Controlling producer socket1 buffer for HWA13" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA13_prod1_count,Defining count values for pre/post load for generating pend by HWA13 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA13_pa1_control,control register to manage pattern adapter on HWA13 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA13_pa1_prodcount,count values for HWA13 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x2100++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA13_prod2_control,Controlling producer socket2 for HWA13" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA13 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA13_prod2_buf_control,Controlling producer socket2 buffer for HWA13" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA13_prod2_count,Defining count values for pre/post load for generating pend by HWA13 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA13_pa2_control,control register to manage pattern adapter on HWA13 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA13_pa2_prodcount,count values for HWA13 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x2120++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA13_prod3_control,Controlling producer socket3 for HWA13" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA13 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA13_prod3_buf_control,Controlling producer socket3 buffer for HWA13" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA13_prod3_count,Defining count values for pre/post load for generating pend by HWA13 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x22C0++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_HWA14_scheduler_control,Scheduler Control Register" bitfld.long 0x0 25. "CHANNEL_LINK_EN,'1' -> Trigger dma_channel_no for chanel_count_set0.count0 times --> Trigger dma_channel_no+1 for chanel_count_set0.count1 times --> Trigger dma_channel_no+2 for chanel_count_set1.count0 times .. repeat till either total count reaches HOP.." "0,1" newline bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "0,1" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1" newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA14" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA14 Scheduler resources must not be read during halted state. '1'-> HWA14 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA14 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA14 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA14_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x22D0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA14_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP feature." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA14 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA14 scheduler skip-enabled prod socket" rgroup.long 0x22E0++0x17 line.long 0x0 "HTS__S_VBUSP__REGS_HWA14_channel_count_set0,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x0 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+1 HWA14_channel_count_set0.count1 times before linking to next HWA14_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x0 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+0 HWA14_channel_count_set0.count0 times before linking to count1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA14_channel_count_set1,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x4 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+3 HWA14_channel_count_set1.count1 times before linking to next HWA14_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x4 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+2 HWA14_channel_count_set1.count0 times before linking to count1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA14_channel_count_set2,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x8 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+5 HWA14_channel_count_set2.count1 times before linking to next HWA14_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x8 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+4 HWA14_channel_count_set2.count0 times before linking to count1" line.long 0xC "HTS__S_VBUSP__REGS_HWA14_channel_count_set3,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0xC 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+7 HWA14_channel_count_set3.count1 times before linking to next HWA14_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0xC 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+6 HWA14_channel_count_set3.count0 times before linking to count1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA14_channel_count_set4,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x10 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+9 HWA14_channel_count_set4.count1 times before linking to next HWA14_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x10 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+8 HWA14_channel_count_set4.count0 times before linking to count1" line.long 0x14 "HTS__S_VBUSP__REGS_HWA14_channel_count_set5,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x14 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+11 HWA14_channel_count_set5.count1 times before linking to next HWA14_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x14 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+10 HWA14_channel_count_set5.count0 times before linking to count1" rgroup.long 0x2320++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA14_cons0_control,Controlling consumer socket 0 for HWA14" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA14 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x2328++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA14_cons1_control,Controlling consumer socket 1 for HWA14" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA14 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" rgroup.long 0x2360++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA14_prod0_control,Controlling producer socket0 for HWA14" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA14 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA14_prod0_buf_control,Controlling producer socket0 buffer for HWA14" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA14_prod0_count,Defining count values for pre/post load for generating pend by HWA14 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA14_pa0_control,control register to manage pattern adapter on HWA14 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA14_pa0_prodcount,count values for HWA14 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x2380++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA14_prod1_control,Controlling producer socket1 for HWA14" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA14 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA14_prod1_buf_control,Controlling producer socket1 buffer for HWA14" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA14_prod1_count,Defining count values for pre/post load for generating pend by HWA14 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA14_pa1_control,control register to manage pattern adapter on HWA14 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA14_pa1_prodcount,count values for HWA14 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x23A0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA14_prod2_control,Controlling producer socket2 for HWA14" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA14 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA14_prod2_buf_control,Controlling producer socket2 buffer for HWA14" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA14_prod2_count,Defining count values for pre/post load for generating pend by HWA14 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA14_pa2_control,control register to manage pattern adapter on HWA14 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA14_pa2_prodcount,count values for HWA14 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x23C0++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA14_prod3_control,Controlling producer socket3 for HWA14" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA14 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA14_prod3_buf_control,Controlling producer socket3 buffer for HWA14" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA14_prod3_count,Defining count values for pre/post load for generating pend by HWA14 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x2560++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_HWA15_scheduler_control,Scheduler Control Register" bitfld.long 0x0 25. "CHANNEL_LINK_EN,'1' -> Trigger dma_channel_no for chanel_count_set0.count0 times --> Trigger dma_channel_no+1 for chanel_count_set0.count1 times --> Trigger dma_channel_no+2 for chanel_count_set1.count0 times .. repeat till either total count reaches HOP.." "0,1" newline bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "0,1" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1" newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA15" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA15 Scheduler resources must not be read during halted state. '1'-> HWA15 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA15 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA15 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA15_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x2570++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA15_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP feature." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA15 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA15 scheduler skip-enabled prod socket" rgroup.long 0x2580++0x17 line.long 0x0 "HTS__S_VBUSP__REGS_HWA15_channel_count_set0,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x0 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+1 HWA15_channel_count_set0.count1 times before linking to next HWA15_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x0 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+0 HWA15_channel_count_set0.count0 times before linking to count1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA15_channel_count_set1,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x4 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+3 HWA15_channel_count_set1.count1 times before linking to next HWA15_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x4 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+2 HWA15_channel_count_set1.count0 times before linking to count1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA15_channel_count_set2,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x8 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+5 HWA15_channel_count_set2.count1 times before linking to next HWA15_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x8 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+4 HWA15_channel_count_set2.count0 times before linking to count1" line.long 0xC "HTS__S_VBUSP__REGS_HWA15_channel_count_set3,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0xC 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+7 HWA15_channel_count_set3.count1 times before linking to next HWA15_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0xC 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+6 HWA15_channel_count_set3.count0 times before linking to count1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA15_channel_count_set4,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x10 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+9 HWA15_channel_count_set4.count1 times before linking to next HWA15_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x10 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+8 HWA15_channel_count_set4.count0 times before linking to count1" line.long 0x14 "HTS__S_VBUSP__REGS_HWA15_channel_count_set5,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x14 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+11 HWA15_channel_count_set5.count1 times before linking to next HWA15_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x14 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+10 HWA15_channel_count_set5.count0 times before linking to count1" rgroup.long 0x25C0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA15_cons0_control,Controlling consumer socket 0 for HWA15" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA15 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x25C8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA15_cons1_control,Controlling consumer socket 1 for HWA15" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA15 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" rgroup.long 0x2600++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA15_prod0_control,Controlling producer socket0 for HWA15" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA15 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA15_prod0_buf_control,Controlling producer socket0 buffer for HWA15" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA15_prod0_count,Defining count values for pre/post load for generating pend by HWA15 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA15_pa0_control,control register to manage pattern adapter on HWA15 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA15_pa0_prodcount,count values for HWA15 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x2620++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA15_prod1_control,Controlling producer socket1 for HWA15" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA15 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA15_prod1_buf_control,Controlling producer socket1 buffer for HWA15" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA15_prod1_count,Defining count values for pre/post load for generating pend by HWA15 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA15_pa1_control,control register to manage pattern adapter on HWA15 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA15_pa1_prodcount,count values for HWA15 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x2640++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA15_prod2_control,Controlling producer socket2 for HWA15" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA15 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA15_prod2_buf_control,Controlling producer socket2 buffer for HWA15" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA15_prod2_count,Defining count values for pre/post load for generating pend by HWA15 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA15_pa2_control,control register to manage pattern adapter on HWA15 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA15_pa2_prodcount,count values for HWA15 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x2660++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA15_prod3_control,Controlling producer socket3 for HWA15" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA15 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA15_prod3_buf_control,Controlling producer socket3 buffer for HWA15" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA15_prod3_count,Defining count values for pre/post load for generating pend by HWA15 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x2800++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_HWA16_scheduler_control,Scheduler Control Register" bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "0,1" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1" newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA16" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA16 Scheduler resources must not be read during halted state. '1'-> HWA16 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA16 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA16 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA16_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x2810++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA16_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP feature." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA16 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA16 scheduler skip-enabled prod socket" rgroup.long 0x2860++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA16_cons0_control,Controlling consumer socket 0 for HWA16" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA16 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x2868++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA16_cons1_control,Controlling consumer socket 1 for HWA16" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA16 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" rgroup.long 0x28A0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA16_prod0_control,Controlling producer socket0 for HWA16" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA16 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA16_prod0_buf_control,Controlling producer socket0 buffer for HWA16" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA16_prod0_count,Defining count values for pre/post load for generating pend by HWA16 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA16_pa0_control,control register to manage pattern adapter on HWA16 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA16_pa0_prodcount,count values for HWA16 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x28C0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA16_prod1_control,Controlling producer socket1 for HWA16" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA16 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA16_prod1_buf_control,Controlling producer socket1 buffer for HWA16" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA16_prod1_count,Defining count values for pre/post load for generating pend by HWA16 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA16_pa1_control,control register to manage pattern adapter on HWA16 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA16_pa1_prodcount,count values for HWA16 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x28E0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA16_prod2_control,Controlling producer socket2 for HWA16" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA16 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA16_prod2_buf_control,Controlling producer socket2 buffer for HWA16" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA16_prod2_count,Defining count values for pre/post load for generating pend by HWA16 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA16_pa2_control,control register to manage pattern adapter on HWA16 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA16_pa2_prodcount,count values for HWA16 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x2900++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA16_prod3_control,Controlling producer socket3 for HWA16" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA16 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA16_prod3_buf_control,Controlling producer socket3 buffer for HWA16" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA16_prod3_count,Defining count values for pre/post load for generating pend by HWA16 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x2AA0++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_HWA17_scheduler_control,Scheduler Control Register" bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "0,1" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1" newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA17" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA17 Scheduler resources must not be read during halted state. '1'-> HWA17 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA17 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA17 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA17_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x2AB0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA17_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP feature." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA17 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA17 scheduler skip-enabled prod socket" rgroup.long 0x2B00++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA17_cons0_control,Controlling consumer socket 0 for HWA17" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA17 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x2B08++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA17_cons1_control,Controlling consumer socket 1 for HWA17" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA17 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" rgroup.long 0x2B40++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA17_prod0_control,Controlling producer socket0 for HWA17" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA17 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA17_prod0_buf_control,Controlling producer socket0 buffer for HWA17" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA17_prod0_count,Defining count values for pre/post load for generating pend by HWA17 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA17_pa0_control,control register to manage pattern adapter on HWA17 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA17_pa0_prodcount,count values for HWA17 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x2B60++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA17_prod1_control,Controlling producer socket1 for HWA17" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA17 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA17_prod1_buf_control,Controlling producer socket1 buffer for HWA17" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA17_prod1_count,Defining count values for pre/post load for generating pend by HWA17 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA17_pa1_control,control register to manage pattern adapter on HWA17 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA17_pa1_prodcount,count values for HWA17 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x2B80++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA17_prod2_control,Controlling producer socket2 for HWA17" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA17 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA17_prod2_buf_control,Controlling producer socket2 buffer for HWA17" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA17_prod2_count,Defining count values for pre/post load for generating pend by HWA17 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA17_pa2_control,control register to manage pattern adapter on HWA17 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA17_pa2_prodcount,count values for HWA17 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x2BA0++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA17_prod3_control,Controlling producer socket3 for HWA17" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA17 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA17_prod3_buf_control,Controlling producer socket3 buffer for HWA17" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA17_prod3_count,Defining count values for pre/post load for generating pend by HWA17 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x2D40++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_HWA18_scheduler_control,Scheduler Control Register" bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "0,1" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1" newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA18" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA18 Scheduler resources must not be read during halted state. '1'-> HWA18 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA18 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA18 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA18_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x2D50++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA18_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP feature." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA18 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA18 scheduler skip-enabled prod socket" rgroup.long 0x2DA0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA18_cons0_control,Controlling consumer socket 0 for HWA18" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA18 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x2DA8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA18_cons1_control,Controlling consumer socket 1 for HWA18" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA18 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" rgroup.long 0x2DE0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA18_prod0_control,Controlling producer socket0 for HWA18" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA18 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA18_prod0_buf_control,Controlling producer socket0 buffer for HWA18" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA18_prod0_count,Defining count values for pre/post load for generating pend by HWA18 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA18_pa0_control,control register to manage pattern adapter on HWA18 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA18_pa0_prodcount,count values for HWA18 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x2E00++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA18_prod1_control,Controlling producer socket1 for HWA18" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA18 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA18_prod1_buf_control,Controlling producer socket1 buffer for HWA18" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA18_prod1_count,Defining count values for pre/post load for generating pend by HWA18 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA18_pa1_control,control register to manage pattern adapter on HWA18 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA18_pa1_prodcount,count values for HWA18 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x2E20++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA18_prod2_control,Controlling producer socket2 for HWA18" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA18 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA18_prod2_buf_control,Controlling producer socket2 buffer for HWA18" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA18_prod2_count,Defining count values for pre/post load for generating pend by HWA18 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA18_pa2_control,control register to manage pattern adapter on HWA18 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA18_pa2_prodcount,count values for HWA18 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x2E40++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA18_prod3_control,Controlling producer socket3 for HWA18" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA18 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA18_prod3_buf_control,Controlling producer socket3 buffer for HWA18" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA18_prod3_count,Defining count values for pre/post load for generating pend by HWA18 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x2FE0++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_HWA19_scheduler_control,Scheduler Control Register" bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "0,1" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1" newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA19" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA19 Scheduler resources must not be read during halted state. '1'-> HWA19 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA19 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA19 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA19_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x2FF0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA19_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP feature." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA19 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA19 scheduler skip-enabled prod socket" rgroup.long 0x3040++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA19_cons0_control,Controlling consumer socket 0 for HWA19" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA19 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x3048++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA19_cons1_control,Controlling consumer socket 1 for HWA19" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA19 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" rgroup.long 0x3080++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA19_prod0_control,Controlling producer socket0 for HWA19" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA19 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA19_prod0_buf_control,Controlling producer socket0 buffer for HWA19" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA19_prod0_count,Defining count values for pre/post load for generating pend by HWA19 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA19_pa0_control,control register to manage pattern adapter on HWA19 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA19_pa0_prodcount,count values for HWA19 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x30A0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA19_prod1_control,Controlling producer socket1 for HWA19" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA19 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA19_prod1_buf_control,Controlling producer socket1 buffer for HWA19" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA19_prod1_count,Defining count values for pre/post load for generating pend by HWA19 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA19_pa1_control,control register to manage pattern adapter on HWA19 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA19_pa1_prodcount,count values for HWA19 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x30C0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA19_prod2_control,Controlling producer socket2 for HWA19" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA19 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA19_prod2_buf_control,Controlling producer socket2 buffer for HWA19" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA19_prod2_count,Defining count values for pre/post load for generating pend by HWA19 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA19_pa2_control,control register to manage pattern adapter on HWA19 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA19_pa2_prodcount,count values for HWA19 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x30E0++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA19_prod3_control,Controlling producer socket3 for HWA19" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA19 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA19_prod3_buf_control,Controlling producer socket3 buffer for HWA19" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA19_prod3_count,Defining count values for pre/post load for generating pend by HWA19 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x3280++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_HWA20_scheduler_control,Scheduler Control Register" bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "0,1" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1" newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA20" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA20 Scheduler resources must not be read during halted state. '1'-> HWA20 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA20 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA20 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA20_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x3290++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA20_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP feature." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA20 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA20 scheduler skip-enabled prod socket" rgroup.long 0x32E0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA20_cons0_control,Controlling consumer socket 0 for HWA20" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA20 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x32E8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA20_cons1_control,Controlling consumer socket 1 for HWA20" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA20 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" rgroup.long 0x3320++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA20_prod0_control,Controlling producer socket0 for HWA20" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA20 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA20_prod0_buf_control,Controlling producer socket0 buffer for HWA20" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA20_prod0_count,Defining count values for pre/post load for generating pend by HWA20 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA20_pa0_control,control register to manage pattern adapter on HWA20 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA20_pa0_prodcount,count values for HWA20 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x3340++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA20_prod1_control,Controlling producer socket1 for HWA20" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA20 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA20_prod1_buf_control,Controlling producer socket1 buffer for HWA20" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA20_prod1_count,Defining count values for pre/post load for generating pend by HWA20 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA20_pa1_control,control register to manage pattern adapter on HWA20 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA20_pa1_prodcount,count values for HWA20 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x3360++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA20_prod2_control,Controlling producer socket2 for HWA20" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA20 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA20_prod2_buf_control,Controlling producer socket2 buffer for HWA20" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA20_prod2_count,Defining count values for pre/post load for generating pend by HWA20 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA20_pa2_control,control register to manage pattern adapter on HWA20 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA20_pa2_prodcount,count values for HWA20 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x3380++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA20_prod3_control,Controlling producer socket3 for HWA20" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA20 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA20_prod3_buf_control,Controlling producer socket3 buffer for HWA20" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA20_prod3_count,Defining count values for pre/post load for generating pend by HWA20 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x3520++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_HWA21_scheduler_control,Scheduler Control Register" bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "0,1" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1" newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA21" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA21 Scheduler resources must not be read during halted state. '1'-> HWA21 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA21 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA21 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA21_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x3530++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA21_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP feature." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA21 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA21 scheduler skip-enabled prod socket" rgroup.long 0x3580++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA21_cons0_control,Controlling consumer socket 0 for HWA21" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA21 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x3588++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA21_cons1_control,Controlling consumer socket 1 for HWA21" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA21 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" rgroup.long 0x35C0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA21_prod0_control,Controlling producer socket0 for HWA21" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA21 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA21_prod0_buf_control,Controlling producer socket0 buffer for HWA21" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA21_prod0_count,Defining count values for pre/post load for generating pend by HWA21 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA21_pa0_control,control register to manage pattern adapter on HWA21 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA21_pa0_prodcount,count values for HWA21 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x35E0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA21_prod1_control,Controlling producer socket1 for HWA21" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA21 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA21_prod1_buf_control,Controlling producer socket1 buffer for HWA21" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA21_prod1_count,Defining count values for pre/post load for generating pend by HWA21 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA21_pa1_control,control register to manage pattern adapter on HWA21 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA21_pa1_prodcount,count values for HWA21 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x3600++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA21_prod2_control,Controlling producer socket2 for HWA21" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA21 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA21_prod2_buf_control,Controlling producer socket2 buffer for HWA21" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA21_prod2_count,Defining count values for pre/post load for generating pend by HWA21 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA21_pa2_control,control register to manage pattern adapter on HWA21 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA21_pa2_prodcount,count values for HWA21 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x3620++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA21_prod3_control,Controlling producer socket3 for HWA21" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA21 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA21_prod3_buf_control,Controlling producer socket3 buffer for HWA21" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA21_prod3_count,Defining count values for pre/post load for generating pend by HWA21 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x4240++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_HWA26_scheduler_control,Scheduler Control Register" bitfld.long 0x0 25. "CHANNEL_LINK_EN,'1' -> Trigger dma_channel_no for chanel_count_set0.count0 times --> Trigger dma_channel_no+1 for chanel_count_set0.count1 times --> Trigger dma_channel_no+2 for chanel_count_set1.count0 times .. repeat till either total count reaches HOP.." "0,1" newline bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "0,1" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1" newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA26" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA26 Scheduler resources must not be read during halted state. '1'-> HWA26 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA26 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA26 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA26_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x4250++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA26_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP feature." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA26 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA26 scheduler skip-enabled prod socket" rgroup.long 0x4260++0x17 line.long 0x0 "HTS__S_VBUSP__REGS_HWA26_channel_count_set0,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x0 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+1 HWA26_channel_count_set0.count1 times before linking to next HWA26_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x0 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+0 HWA26_channel_count_set0.count0 times before linking to count1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA26_channel_count_set1,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x4 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+3 HWA26_channel_count_set1.count1 times before linking to next HWA26_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x4 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+2 HWA26_channel_count_set1.count0 times before linking to count1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA26_channel_count_set2,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x8 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+5 HWA26_channel_count_set2.count1 times before linking to next HWA26_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x8 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+4 HWA26_channel_count_set2.count0 times before linking to count1" line.long 0xC "HTS__S_VBUSP__REGS_HWA26_channel_count_set3,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0xC 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+7 HWA26_channel_count_set3.count1 times before linking to next HWA26_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0xC 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+6 HWA26_channel_count_set3.count0 times before linking to count1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA26_channel_count_set4,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x10 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+9 HWA26_channel_count_set4.count1 times before linking to next HWA26_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x10 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+8 HWA26_channel_count_set4.count0 times before linking to count1" line.long 0x14 "HTS__S_VBUSP__REGS_HWA26_channel_count_set5,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x14 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+11 HWA26_channel_count_set5.count1 times before linking to next HWA26_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x14 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+10 HWA26_channel_count_set5.count0 times before linking to count1" rgroup.long 0x42A0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA26_cons0_control,Controlling consumer socket 0 for HWA26" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA26 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x42A8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA26_cons1_control,Controlling consumer socket 1 for HWA26" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA26 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" rgroup.long 0x42E0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA26_prod0_control,Controlling producer socket0 for HWA26" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 16. "DYNAMIC_TH_EN,'1' -> Dynamic Thresholding Enabled for Producer socket 0 '0' Disable Dynamic Thresholding" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA26 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA26_prod0_buf_control,Controlling producer socket0 buffer for HWA26" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA26_prod0_count,Defining count values for pre/post load for generating pend by HWA26 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA26_pa0_control,control register to manage pattern adapter on HWA26 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA26_pa0_prodcount,count values for HWA26 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x4300++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA26_prod1_control,Controlling producer socket1 for HWA26" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 16. "DYNAMIC_TH_EN,'1' -> Dynamic Thresholding Enabled for Producer socket 1 '0' Disable Dynamic Thresholding" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA26 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA26_prod1_buf_control,Controlling producer socket1 buffer for HWA26" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA26_prod1_count,Defining count values for pre/post load for generating pend by HWA26 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA26_pa1_control,control register to manage pattern adapter on HWA26 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA26_pa1_prodcount,count values for HWA26 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x4320++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA26_prod2_control,Controlling producer socket2 for HWA26" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 16. "DYNAMIC_TH_EN,'1' -> Dynamic Thresholding Enabled for Producer socket 2 '0' Disable Dynamic Thresholding" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA26 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA26_prod2_buf_control,Controlling producer socket2 buffer for HWA26" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA26_prod2_count,Defining count values for pre/post load for generating pend by HWA26 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA26_pa2_control,control register to manage pattern adapter on HWA26 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA26_pa2_prodcount,count values for HWA26 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x4340++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA26_prod3_control,Controlling producer socket3 for HWA26" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA26 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA26_prod3_buf_control,Controlling producer socket3 buffer for HWA26" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA26_prod3_count,Defining count values for pre/post load for generating pend by HWA26 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x44E0++0x1FF line.long 0x0 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold0,csmaxcount and count_dec value for Row No 0. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 0 when dynamic threshold feature is enabled" newline hexmask.long.word 0x0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 0 when dynamic threshold feature is enabled" line.long 0x4 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold1,csmaxcount and count_dec value for Row No 1. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 1 when dynamic threshold feature is enabled" newline hexmask.long.word 0x4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 1 when dynamic threshold feature is enabled" line.long 0x8 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold2,csmaxcount and count_dec value for Row No 2. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 2 when dynamic threshold feature is enabled" newline hexmask.long.word 0x8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 2 when dynamic threshold feature is enabled" line.long 0xC "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold3,csmaxcount and count_dec value for Row No 3. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 3 when dynamic threshold feature is enabled" newline hexmask.long.word 0xC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 3 when dynamic threshold feature is enabled" line.long 0x10 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold4,csmaxcount and count_dec value for Row No 4. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x10 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 4 when dynamic threshold feature is enabled" newline hexmask.long.word 0x10 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 4 when dynamic threshold feature is enabled" line.long 0x14 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold5,csmaxcount and count_dec value for Row No 5. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x14 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 5 when dynamic threshold feature is enabled" newline hexmask.long.word 0x14 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 5 when dynamic threshold feature is enabled" line.long 0x18 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold6,csmaxcount and count_dec value for Row No 6. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x18 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 6 when dynamic threshold feature is enabled" newline hexmask.long.word 0x18 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 6 when dynamic threshold feature is enabled" line.long 0x1C "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold7,csmaxcount and count_dec value for Row No 7. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 7 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 7 when dynamic threshold feature is enabled" line.long 0x20 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold8,csmaxcount and count_dec value for Row No 8. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x20 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 8 when dynamic threshold feature is enabled" newline hexmask.long.word 0x20 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 8 when dynamic threshold feature is enabled" line.long 0x24 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold9,csmaxcount and count_dec value for Row No 9. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x24 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 9 when dynamic threshold feature is enabled" newline hexmask.long.word 0x24 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 9 when dynamic threshold feature is enabled" line.long 0x28 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold10,csmaxcount and count_dec value for Row No 10. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x28 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 10 when dynamic threshold feature is enabled" newline hexmask.long.word 0x28 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 10 when dynamic threshold feature is enabled" line.long 0x2C "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold11,csmaxcount and count_dec value for Row No 11. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x2C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 11 when dynamic threshold feature is enabled" newline hexmask.long.word 0x2C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 11 when dynamic threshold feature is enabled" line.long 0x30 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold12,csmaxcount and count_dec value for Row No 12. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x30 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 12 when dynamic threshold feature is enabled" newline hexmask.long.word 0x30 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 12 when dynamic threshold feature is enabled" line.long 0x34 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold13,csmaxcount and count_dec value for Row No 13. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x34 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 13 when dynamic threshold feature is enabled" newline hexmask.long.word 0x34 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 13 when dynamic threshold feature is enabled" line.long 0x38 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold14,csmaxcount and count_dec value for Row No 14. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x38 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 14 when dynamic threshold feature is enabled" newline hexmask.long.word 0x38 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 14 when dynamic threshold feature is enabled" line.long 0x3C "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold15,csmaxcount and count_dec value for Row No 15. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x3C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 15 when dynamic threshold feature is enabled" newline hexmask.long.word 0x3C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 15 when dynamic threshold feature is enabled" line.long 0x40 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold16,csmaxcount and count_dec value for Row No 16. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x40 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 16 when dynamic threshold feature is enabled" newline hexmask.long.word 0x40 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 16 when dynamic threshold feature is enabled" line.long 0x44 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold17,csmaxcount and count_dec value for Row No 17. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x44 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 17 when dynamic threshold feature is enabled" newline hexmask.long.word 0x44 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 17 when dynamic threshold feature is enabled" line.long 0x48 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold18,csmaxcount and count_dec value for Row No 18. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x48 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 18 when dynamic threshold feature is enabled" newline hexmask.long.word 0x48 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 18 when dynamic threshold feature is enabled" line.long 0x4C "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold19,csmaxcount and count_dec value for Row No 19. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x4C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 19 when dynamic threshold feature is enabled" newline hexmask.long.word 0x4C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 19 when dynamic threshold feature is enabled" line.long 0x50 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold20,csmaxcount and count_dec value for Row No 20. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x50 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 20 when dynamic threshold feature is enabled" newline hexmask.long.word 0x50 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 20 when dynamic threshold feature is enabled" line.long 0x54 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold21,csmaxcount and count_dec value for Row No 21. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x54 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 21 when dynamic threshold feature is enabled" newline hexmask.long.word 0x54 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 21 when dynamic threshold feature is enabled" line.long 0x58 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold22,csmaxcount and count_dec value for Row No 22. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x58 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 22 when dynamic threshold feature is enabled" newline hexmask.long.word 0x58 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 22 when dynamic threshold feature is enabled" line.long 0x5C "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold23,csmaxcount and count_dec value for Row No 23. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x5C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 23 when dynamic threshold feature is enabled" newline hexmask.long.word 0x5C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 23 when dynamic threshold feature is enabled" line.long 0x60 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold24,csmaxcount and count_dec value for Row No 24. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x60 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 24 when dynamic threshold feature is enabled" newline hexmask.long.word 0x60 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 24 when dynamic threshold feature is enabled" line.long 0x64 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold25,csmaxcount and count_dec value for Row No 25. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x64 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 25 when dynamic threshold feature is enabled" newline hexmask.long.word 0x64 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 25 when dynamic threshold feature is enabled" line.long 0x68 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold26,csmaxcount and count_dec value for Row No 26. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x68 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 26 when dynamic threshold feature is enabled" newline hexmask.long.word 0x68 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 26 when dynamic threshold feature is enabled" line.long 0x6C "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold27,csmaxcount and count_dec value for Row No 27. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x6C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 27 when dynamic threshold feature is enabled" newline hexmask.long.word 0x6C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 27 when dynamic threshold feature is enabled" line.long 0x70 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold28,csmaxcount and count_dec value for Row No 28. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x70 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 28 when dynamic threshold feature is enabled" newline hexmask.long.word 0x70 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 28 when dynamic threshold feature is enabled" line.long 0x74 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold29,csmaxcount and count_dec value for Row No 29. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x74 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 29 when dynamic threshold feature is enabled" newline hexmask.long.word 0x74 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 29 when dynamic threshold feature is enabled" line.long 0x78 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold30,csmaxcount and count_dec value for Row No 30. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x78 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 30 when dynamic threshold feature is enabled" newline hexmask.long.word 0x78 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 30 when dynamic threshold feature is enabled" line.long 0x7C "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold31,csmaxcount and count_dec value for Row No 31. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x7C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 31 when dynamic threshold feature is enabled" newline hexmask.long.word 0x7C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 31 when dynamic threshold feature is enabled" line.long 0x80 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold32,csmaxcount and count_dec value for Row No 32. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x80 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 32 when dynamic threshold feature is enabled" newline hexmask.long.word 0x80 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 32 when dynamic threshold feature is enabled" line.long 0x84 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold33,csmaxcount and count_dec value for Row No 33. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x84 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 33 when dynamic threshold feature is enabled" newline hexmask.long.word 0x84 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 33 when dynamic threshold feature is enabled" line.long 0x88 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold34,csmaxcount and count_dec value for Row No 34. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x88 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 34 when dynamic threshold feature is enabled" newline hexmask.long.word 0x88 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 34 when dynamic threshold feature is enabled" line.long 0x8C "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold35,csmaxcount and count_dec value for Row No 35. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x8C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 35 when dynamic threshold feature is enabled" newline hexmask.long.word 0x8C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 35 when dynamic threshold feature is enabled" line.long 0x90 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold36,csmaxcount and count_dec value for Row No 36. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x90 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 36 when dynamic threshold feature is enabled" newline hexmask.long.word 0x90 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 36 when dynamic threshold feature is enabled" line.long 0x94 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold37,csmaxcount and count_dec value for Row No 37. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x94 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 37 when dynamic threshold feature is enabled" newline hexmask.long.word 0x94 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 37 when dynamic threshold feature is enabled" line.long 0x98 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold38,csmaxcount and count_dec value for Row No 38. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x98 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 38 when dynamic threshold feature is enabled" newline hexmask.long.word 0x98 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 38 when dynamic threshold feature is enabled" line.long 0x9C "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold39,csmaxcount and count_dec value for Row No 39. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x9C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 39 when dynamic threshold feature is enabled" newline hexmask.long.word 0x9C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 39 when dynamic threshold feature is enabled" line.long 0xA0 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold40,csmaxcount and count_dec value for Row No 40. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xA0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 40 when dynamic threshold feature is enabled" newline hexmask.long.word 0xA0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 40 when dynamic threshold feature is enabled" line.long 0xA4 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold41,csmaxcount and count_dec value for Row No 41. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xA4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 41 when dynamic threshold feature is enabled" newline hexmask.long.word 0xA4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 41 when dynamic threshold feature is enabled" line.long 0xA8 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold42,csmaxcount and count_dec value for Row No 42. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xA8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 42 when dynamic threshold feature is enabled" newline hexmask.long.word 0xA8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 42 when dynamic threshold feature is enabled" line.long 0xAC "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold43,csmaxcount and count_dec value for Row No 43. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xAC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 43 when dynamic threshold feature is enabled" newline hexmask.long.word 0xAC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 43 when dynamic threshold feature is enabled" line.long 0xB0 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold44,csmaxcount and count_dec value for Row No 44. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xB0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 44 when dynamic threshold feature is enabled" newline hexmask.long.word 0xB0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 44 when dynamic threshold feature is enabled" line.long 0xB4 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold45,csmaxcount and count_dec value for Row No 45. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xB4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 45 when dynamic threshold feature is enabled" newline hexmask.long.word 0xB4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 45 when dynamic threshold feature is enabled" line.long 0xB8 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold46,csmaxcount and count_dec value for Row No 46. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xB8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 46 when dynamic threshold feature is enabled" newline hexmask.long.word 0xB8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 46 when dynamic threshold feature is enabled" line.long 0xBC "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold47,csmaxcount and count_dec value for Row No 47. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xBC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 47 when dynamic threshold feature is enabled" newline hexmask.long.word 0xBC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 47 when dynamic threshold feature is enabled" line.long 0xC0 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold48,csmaxcount and count_dec value for Row No 48. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xC0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 48 when dynamic threshold feature is enabled" newline hexmask.long.word 0xC0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 48 when dynamic threshold feature is enabled" line.long 0xC4 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold49,csmaxcount and count_dec value for Row No 49. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xC4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 49 when dynamic threshold feature is enabled" newline hexmask.long.word 0xC4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 49 when dynamic threshold feature is enabled" line.long 0xC8 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold50,csmaxcount and count_dec value for Row No 50. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xC8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 50 when dynamic threshold feature is enabled" newline hexmask.long.word 0xC8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 50 when dynamic threshold feature is enabled" line.long 0xCC "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold51,csmaxcount and count_dec value for Row No 51. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xCC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 51 when dynamic threshold feature is enabled" newline hexmask.long.word 0xCC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 51 when dynamic threshold feature is enabled" line.long 0xD0 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold52,csmaxcount and count_dec value for Row No 52. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xD0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 52 when dynamic threshold feature is enabled" newline hexmask.long.word 0xD0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 52 when dynamic threshold feature is enabled" line.long 0xD4 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold53,csmaxcount and count_dec value for Row No 53. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xD4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 53 when dynamic threshold feature is enabled" newline hexmask.long.word 0xD4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 53 when dynamic threshold feature is enabled" line.long 0xD8 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold54,csmaxcount and count_dec value for Row No 54. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xD8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 54 when dynamic threshold feature is enabled" newline hexmask.long.word 0xD8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 54 when dynamic threshold feature is enabled" line.long 0xDC "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold55,csmaxcount and count_dec value for Row No 55. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xDC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 55 when dynamic threshold feature is enabled" newline hexmask.long.word 0xDC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 55 when dynamic threshold feature is enabled" line.long 0xE0 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold56,csmaxcount and count_dec value for Row No 56. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xE0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 56 when dynamic threshold feature is enabled" newline hexmask.long.word 0xE0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 56 when dynamic threshold feature is enabled" line.long 0xE4 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold57,csmaxcount and count_dec value for Row No 57. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xE4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 57 when dynamic threshold feature is enabled" newline hexmask.long.word 0xE4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 57 when dynamic threshold feature is enabled" line.long 0xE8 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold58,csmaxcount and count_dec value for Row No 58. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xE8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 58 when dynamic threshold feature is enabled" newline hexmask.long.word 0xE8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 58 when dynamic threshold feature is enabled" line.long 0xEC "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold59,csmaxcount and count_dec value for Row No 59. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xEC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 59 when dynamic threshold feature is enabled" newline hexmask.long.word 0xEC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 59 when dynamic threshold feature is enabled" line.long 0xF0 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold60,csmaxcount and count_dec value for Row No 60. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xF0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 60 when dynamic threshold feature is enabled" newline hexmask.long.word 0xF0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 60 when dynamic threshold feature is enabled" line.long 0xF4 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold61,csmaxcount and count_dec value for Row No 61. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xF4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 61 when dynamic threshold feature is enabled" newline hexmask.long.word 0xF4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 61 when dynamic threshold feature is enabled" line.long 0xF8 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold62,csmaxcount and count_dec value for Row No 62. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xF8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 62 when dynamic threshold feature is enabled" newline hexmask.long.word 0xF8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 62 when dynamic threshold feature is enabled" line.long 0xFC "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold63,csmaxcount and count_dec value for Row No 63. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xFC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 63 when dynamic threshold feature is enabled" newline hexmask.long.word 0xFC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 63 when dynamic threshold feature is enabled" line.long 0x100 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold64,csmaxcount and count_dec value for Row No 64. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x100 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 64 when dynamic threshold feature is enabled" newline hexmask.long.word 0x100 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 64 when dynamic threshold feature is enabled" line.long 0x104 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold65,csmaxcount and count_dec value for Row No 65. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x104 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 65 when dynamic threshold feature is enabled" newline hexmask.long.word 0x104 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 65 when dynamic threshold feature is enabled" line.long 0x108 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold66,csmaxcount and count_dec value for Row No 66. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x108 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 66 when dynamic threshold feature is enabled" newline hexmask.long.word 0x108 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 66 when dynamic threshold feature is enabled" line.long 0x10C "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold67,csmaxcount and count_dec value for Row No 67. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x10C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 67 when dynamic threshold feature is enabled" newline hexmask.long.word 0x10C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 67 when dynamic threshold feature is enabled" line.long 0x110 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold68,csmaxcount and count_dec value for Row No 68. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x110 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 68 when dynamic threshold feature is enabled" newline hexmask.long.word 0x110 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 68 when dynamic threshold feature is enabled" line.long 0x114 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold69,csmaxcount and count_dec value for Row No 69. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x114 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 69 when dynamic threshold feature is enabled" newline hexmask.long.word 0x114 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 69 when dynamic threshold feature is enabled" line.long 0x118 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold70,csmaxcount and count_dec value for Row No 70. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x118 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 70 when dynamic threshold feature is enabled" newline hexmask.long.word 0x118 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 70 when dynamic threshold feature is enabled" line.long 0x11C "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold71,csmaxcount and count_dec value for Row No 71. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x11C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 71 when dynamic threshold feature is enabled" newline hexmask.long.word 0x11C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 71 when dynamic threshold feature is enabled" line.long 0x120 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold72,csmaxcount and count_dec value for Row No 72. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x120 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 72 when dynamic threshold feature is enabled" newline hexmask.long.word 0x120 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 72 when dynamic threshold feature is enabled" line.long 0x124 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold73,csmaxcount and count_dec value for Row No 73. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x124 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 73 when dynamic threshold feature is enabled" newline hexmask.long.word 0x124 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 73 when dynamic threshold feature is enabled" line.long 0x128 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold74,csmaxcount and count_dec value for Row No 74. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x128 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 74 when dynamic threshold feature is enabled" newline hexmask.long.word 0x128 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 74 when dynamic threshold feature is enabled" line.long 0x12C "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold75,csmaxcount and count_dec value for Row No 75. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x12C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 75 when dynamic threshold feature is enabled" newline hexmask.long.word 0x12C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 75 when dynamic threshold feature is enabled" line.long 0x130 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold76,csmaxcount and count_dec value for Row No 76. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x130 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 76 when dynamic threshold feature is enabled" newline hexmask.long.word 0x130 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 76 when dynamic threshold feature is enabled" line.long 0x134 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold77,csmaxcount and count_dec value for Row No 77. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x134 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 77 when dynamic threshold feature is enabled" newline hexmask.long.word 0x134 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 77 when dynamic threshold feature is enabled" line.long 0x138 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold78,csmaxcount and count_dec value for Row No 78. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x138 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 78 when dynamic threshold feature is enabled" newline hexmask.long.word 0x138 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 78 when dynamic threshold feature is enabled" line.long 0x13C "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold79,csmaxcount and count_dec value for Row No 79. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x13C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 79 when dynamic threshold feature is enabled" newline hexmask.long.word 0x13C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 79 when dynamic threshold feature is enabled" line.long 0x140 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold80,csmaxcount and count_dec value for Row No 80. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x140 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 80 when dynamic threshold feature is enabled" newline hexmask.long.word 0x140 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 80 when dynamic threshold feature is enabled" line.long 0x144 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold81,csmaxcount and count_dec value for Row No 81. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x144 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 81 when dynamic threshold feature is enabled" newline hexmask.long.word 0x144 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 81 when dynamic threshold feature is enabled" line.long 0x148 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold82,csmaxcount and count_dec value for Row No 82. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x148 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 82 when dynamic threshold feature is enabled" newline hexmask.long.word 0x148 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 82 when dynamic threshold feature is enabled" line.long 0x14C "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold83,csmaxcount and count_dec value for Row No 83. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x14C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 83 when dynamic threshold feature is enabled" newline hexmask.long.word 0x14C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 83 when dynamic threshold feature is enabled" line.long 0x150 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold84,csmaxcount and count_dec value for Row No 84. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x150 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 84 when dynamic threshold feature is enabled" newline hexmask.long.word 0x150 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 84 when dynamic threshold feature is enabled" line.long 0x154 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold85,csmaxcount and count_dec value for Row No 85. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x154 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 85 when dynamic threshold feature is enabled" newline hexmask.long.word 0x154 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 85 when dynamic threshold feature is enabled" line.long 0x158 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold86,csmaxcount and count_dec value for Row No 86. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x158 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 86 when dynamic threshold feature is enabled" newline hexmask.long.word 0x158 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 86 when dynamic threshold feature is enabled" line.long 0x15C "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold87,csmaxcount and count_dec value for Row No 87. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x15C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 87 when dynamic threshold feature is enabled" newline hexmask.long.word 0x15C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 87 when dynamic threshold feature is enabled" line.long 0x160 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold88,csmaxcount and count_dec value for Row No 88. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x160 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 88 when dynamic threshold feature is enabled" newline hexmask.long.word 0x160 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 88 when dynamic threshold feature is enabled" line.long 0x164 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold89,csmaxcount and count_dec value for Row No 89. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x164 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 89 when dynamic threshold feature is enabled" newline hexmask.long.word 0x164 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 89 when dynamic threshold feature is enabled" line.long 0x168 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold90,csmaxcount and count_dec value for Row No 90. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x168 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 90 when dynamic threshold feature is enabled" newline hexmask.long.word 0x168 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 90 when dynamic threshold feature is enabled" line.long 0x16C "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold91,csmaxcount and count_dec value for Row No 91. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x16C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 91 when dynamic threshold feature is enabled" newline hexmask.long.word 0x16C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 91 when dynamic threshold feature is enabled" line.long 0x170 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold92,csmaxcount and count_dec value for Row No 92. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x170 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 92 when dynamic threshold feature is enabled" newline hexmask.long.word 0x170 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 92 when dynamic threshold feature is enabled" line.long 0x174 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold93,csmaxcount and count_dec value for Row No 93. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x174 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 93 when dynamic threshold feature is enabled" newline hexmask.long.word 0x174 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 93 when dynamic threshold feature is enabled" line.long 0x178 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold94,csmaxcount and count_dec value for Row No 94. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x178 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 94 when dynamic threshold feature is enabled" newline hexmask.long.word 0x178 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 94 when dynamic threshold feature is enabled" line.long 0x17C "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold95,csmaxcount and count_dec value for Row No 95. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x17C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 95 when dynamic threshold feature is enabled" newline hexmask.long.word 0x17C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 95 when dynamic threshold feature is enabled" line.long 0x180 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold96,csmaxcount and count_dec value for Row No 96. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x180 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 96 when dynamic threshold feature is enabled" newline hexmask.long.word 0x180 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 96 when dynamic threshold feature is enabled" line.long 0x184 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold97,csmaxcount and count_dec value for Row No 97. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x184 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 97 when dynamic threshold feature is enabled" newline hexmask.long.word 0x184 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 97 when dynamic threshold feature is enabled" line.long 0x188 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold98,csmaxcount and count_dec value for Row No 98. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x188 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 98 when dynamic threshold feature is enabled" newline hexmask.long.word 0x188 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 98 when dynamic threshold feature is enabled" line.long 0x18C "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold99,csmaxcount and count_dec value for Row No 99. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x18C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 99 when dynamic threshold feature is enabled" newline hexmask.long.word 0x18C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 99 when dynamic threshold feature is enabled" line.long 0x190 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold100,csmaxcount and count_dec value for Row No 100. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x190 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 100 when dynamic threshold feature is enabled" newline hexmask.long.word 0x190 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 100 when dynamic threshold feature is enabled" line.long 0x194 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold101,csmaxcount and count_dec value for Row No 101. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x194 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 101 when dynamic threshold feature is enabled" newline hexmask.long.word 0x194 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 101 when dynamic threshold feature is enabled" line.long 0x198 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold102,csmaxcount and count_dec value for Row No 102. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x198 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 102 when dynamic threshold feature is enabled" newline hexmask.long.word 0x198 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 102 when dynamic threshold feature is enabled" line.long 0x19C "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold103,csmaxcount and count_dec value for Row No 103. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x19C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 103 when dynamic threshold feature is enabled" newline hexmask.long.word 0x19C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 103 when dynamic threshold feature is enabled" line.long 0x1A0 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold104,csmaxcount and count_dec value for Row No 104. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1A0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 104 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1A0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 104 when dynamic threshold feature is enabled" line.long 0x1A4 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold105,csmaxcount and count_dec value for Row No 105. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1A4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 105 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1A4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 105 when dynamic threshold feature is enabled" line.long 0x1A8 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold106,csmaxcount and count_dec value for Row No 106. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1A8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 106 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1A8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 106 when dynamic threshold feature is enabled" line.long 0x1AC "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold107,csmaxcount and count_dec value for Row No 107. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1AC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 107 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1AC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 107 when dynamic threshold feature is enabled" line.long 0x1B0 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold108,csmaxcount and count_dec value for Row No 108. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1B0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 108 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1B0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 108 when dynamic threshold feature is enabled" line.long 0x1B4 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold109,csmaxcount and count_dec value for Row No 109. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1B4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 109 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1B4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 109 when dynamic threshold feature is enabled" line.long 0x1B8 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold110,csmaxcount and count_dec value for Row No 110. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1B8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 110 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1B8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 110 when dynamic threshold feature is enabled" line.long 0x1BC "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold111,csmaxcount and count_dec value for Row No 111. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1BC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 111 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1BC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 111 when dynamic threshold feature is enabled" line.long 0x1C0 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold112,csmaxcount and count_dec value for Row No 112. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1C0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 112 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1C0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 112 when dynamic threshold feature is enabled" line.long 0x1C4 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold113,csmaxcount and count_dec value for Row No 113. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1C4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 113 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1C4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 113 when dynamic threshold feature is enabled" line.long 0x1C8 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold114,csmaxcount and count_dec value for Row No 114. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1C8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 114 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1C8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 114 when dynamic threshold feature is enabled" line.long 0x1CC "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold115,csmaxcount and count_dec value for Row No 115. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1CC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 115 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1CC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 115 when dynamic threshold feature is enabled" line.long 0x1D0 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold116,csmaxcount and count_dec value for Row No 116. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1D0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 116 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1D0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 116 when dynamic threshold feature is enabled" line.long 0x1D4 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold117,csmaxcount and count_dec value for Row No 117. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1D4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 117 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1D4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 117 when dynamic threshold feature is enabled" line.long 0x1D8 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold118,csmaxcount and count_dec value for Row No 118. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1D8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 118 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1D8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 118 when dynamic threshold feature is enabled" line.long 0x1DC "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold119,csmaxcount and count_dec value for Row No 119. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1DC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 119 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1DC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 119 when dynamic threshold feature is enabled" line.long 0x1E0 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold120,csmaxcount and count_dec value for Row No 120. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1E0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 120 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1E0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 120 when dynamic threshold feature is enabled" line.long 0x1E4 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold121,csmaxcount and count_dec value for Row No 121. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1E4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 121 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1E4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 121 when dynamic threshold feature is enabled" line.long 0x1E8 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold122,csmaxcount and count_dec value for Row No 122. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1E8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 122 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1E8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 122 when dynamic threshold feature is enabled" line.long 0x1EC "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold123,csmaxcount and count_dec value for Row No 123. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1EC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 123 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1EC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 123 when dynamic threshold feature is enabled" line.long 0x1F0 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold124,csmaxcount and count_dec value for Row No 124. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1F0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 124 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1F0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 124 when dynamic threshold feature is enabled" line.long 0x1F4 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold125,csmaxcount and count_dec value for Row No 125. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1F4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 125 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1F4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 125 when dynamic threshold feature is enabled" line.long 0x1F8 "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold126,csmaxcount and count_dec value for Row No 126. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1F8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 126 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1F8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 126 when dynamic threshold feature is enabled" line.long 0x1FC "HTS__S_VBUSP__REGS_HWA26_dynamic_threshold127,csmaxcount and count_dec value for Row No 127. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1FC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 127 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1FC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 127 when dynamic threshold feature is enabled" rgroup.long 0x4780++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_HWA27_scheduler_control,Scheduler Control Register" bitfld.long 0x0 25. "CHANNEL_LINK_EN,'1' -> Trigger dma_channel_no for chanel_count_set0.count0 times --> Trigger dma_channel_no+1 for chanel_count_set0.count1 times --> Trigger dma_channel_no+2 for chanel_count_set1.count0 times .. repeat till either total count reaches HOP.." "0,1" newline bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "0,1" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1" newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA27" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA27 Scheduler resources must not be read during halted state. '1'-> HWA27 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA27 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA27 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA27_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x4790++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA27_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP feature." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA27 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA27 scheduler skip-enabled prod socket" rgroup.long 0x47A0++0x17 line.long 0x0 "HTS__S_VBUSP__REGS_HWA27_channel_count_set0,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x0 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+1 HWA27_channel_count_set0.count1 times before linking to next HWA27_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x0 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+0 HWA27_channel_count_set0.count0 times before linking to count1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA27_channel_count_set1,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x4 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+3 HWA27_channel_count_set1.count1 times before linking to next HWA27_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x4 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+2 HWA27_channel_count_set1.count0 times before linking to count1" line.long 0x8 "HTS__S_VBUSP__REGS_HWA27_channel_count_set2,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x8 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+5 HWA27_channel_count_set2.count1 times before linking to next HWA27_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x8 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+4 HWA27_channel_count_set2.count0 times before linking to count1" line.long 0xC "HTS__S_VBUSP__REGS_HWA27_channel_count_set3,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0xC 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+7 HWA27_channel_count_set3.count1 times before linking to next HWA27_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0xC 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+6 HWA27_channel_count_set3.count0 times before linking to count1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA27_channel_count_set4,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x10 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+9 HWA27_channel_count_set4.count1 times before linking to next HWA27_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x10 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+8 HWA27_channel_count_set4.count0 times before linking to count1" line.long 0x14 "HTS__S_VBUSP__REGS_HWA27_channel_count_set5,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x14 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+11 HWA27_channel_count_set5.count1 times before linking to next HWA27_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x14 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+10 HWA27_channel_count_set5.count0 times before linking to count1" rgroup.long 0x47E0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA27_cons0_control,Controlling consumer socket 0 for HWA27" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA27 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x47E8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_HWA27_cons1_control,Controlling consumer socket 1 for HWA27" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA27 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1" rgroup.long 0x4820++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA27_prod0_control,Controlling producer socket0 for HWA27" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 16. "DYNAMIC_TH_EN,'1' -> Dynamic Thresholding Enabled for Producer socket 0 '0' Disable Dynamic Thresholding" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA27 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA27_prod0_buf_control,Controlling producer socket0 buffer for HWA27" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA27_prod0_count,Defining count values for pre/post load for generating pend by HWA27 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA27_pa0_control,control register to manage pattern adapter on HWA27 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA27_pa0_prodcount,count values for HWA27 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x4840++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA27_prod1_control,Controlling producer socket1 for HWA27" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 16. "DYNAMIC_TH_EN,'1' -> Dynamic Thresholding Enabled for Producer socket 1 '0' Disable Dynamic Thresholding" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA27 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA27_prod1_buf_control,Controlling producer socket1 buffer for HWA27" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA27_prod1_count,Defining count values for pre/post load for generating pend by HWA27 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA27_pa1_control,control register to manage pattern adapter on HWA27 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA27_pa1_prodcount,count values for HWA27 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x4860++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_HWA27_prod2_control,Controlling producer socket2 for HWA27" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 16. "DYNAMIC_TH_EN,'1' -> Dynamic Thresholding Enabled for Producer socket 2 '0' Disable Dynamic Thresholding" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA27 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA27_prod2_buf_control,Controlling producer socket2 buffer for HWA27" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA27_prod2_count,Defining count values for pre/post load for generating pend by HWA27 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_HWA27_pa2_control,control register to manage pattern adapter on HWA27 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_HWA27_pa2_prodcount,count values for HWA27 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x4880++0xB line.long 0x0 "HTS__S_VBUSP__REGS_HWA27_prod3_control,Controlling producer socket3 for HWA27" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "0,1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "0,1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA27 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_HWA27_prod3_buf_control,Controlling producer socket3 buffer for HWA27" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_HWA27_prod3_count,Defining count values for pre/post load for generating pend by HWA27 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x4A20++0x1FF line.long 0x0 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold0,csmaxcount and count_dec value for Row No 0. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 0 when dynamic threshold feature is enabled" newline hexmask.long.word 0x0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 0 when dynamic threshold feature is enabled" line.long 0x4 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold1,csmaxcount and count_dec value for Row No 1. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 1 when dynamic threshold feature is enabled" newline hexmask.long.word 0x4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 1 when dynamic threshold feature is enabled" line.long 0x8 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold2,csmaxcount and count_dec value for Row No 2. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 2 when dynamic threshold feature is enabled" newline hexmask.long.word 0x8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 2 when dynamic threshold feature is enabled" line.long 0xC "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold3,csmaxcount and count_dec value for Row No 3. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 3 when dynamic threshold feature is enabled" newline hexmask.long.word 0xC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 3 when dynamic threshold feature is enabled" line.long 0x10 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold4,csmaxcount and count_dec value for Row No 4. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x10 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 4 when dynamic threshold feature is enabled" newline hexmask.long.word 0x10 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 4 when dynamic threshold feature is enabled" line.long 0x14 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold5,csmaxcount and count_dec value for Row No 5. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x14 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 5 when dynamic threshold feature is enabled" newline hexmask.long.word 0x14 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 5 when dynamic threshold feature is enabled" line.long 0x18 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold6,csmaxcount and count_dec value for Row No 6. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x18 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 6 when dynamic threshold feature is enabled" newline hexmask.long.word 0x18 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 6 when dynamic threshold feature is enabled" line.long 0x1C "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold7,csmaxcount and count_dec value for Row No 7. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 7 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 7 when dynamic threshold feature is enabled" line.long 0x20 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold8,csmaxcount and count_dec value for Row No 8. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x20 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 8 when dynamic threshold feature is enabled" newline hexmask.long.word 0x20 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 8 when dynamic threshold feature is enabled" line.long 0x24 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold9,csmaxcount and count_dec value for Row No 9. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x24 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 9 when dynamic threshold feature is enabled" newline hexmask.long.word 0x24 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 9 when dynamic threshold feature is enabled" line.long 0x28 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold10,csmaxcount and count_dec value for Row No 10. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x28 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 10 when dynamic threshold feature is enabled" newline hexmask.long.word 0x28 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 10 when dynamic threshold feature is enabled" line.long 0x2C "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold11,csmaxcount and count_dec value for Row No 11. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x2C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 11 when dynamic threshold feature is enabled" newline hexmask.long.word 0x2C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 11 when dynamic threshold feature is enabled" line.long 0x30 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold12,csmaxcount and count_dec value for Row No 12. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x30 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 12 when dynamic threshold feature is enabled" newline hexmask.long.word 0x30 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 12 when dynamic threshold feature is enabled" line.long 0x34 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold13,csmaxcount and count_dec value for Row No 13. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x34 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 13 when dynamic threshold feature is enabled" newline hexmask.long.word 0x34 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 13 when dynamic threshold feature is enabled" line.long 0x38 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold14,csmaxcount and count_dec value for Row No 14. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x38 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 14 when dynamic threshold feature is enabled" newline hexmask.long.word 0x38 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 14 when dynamic threshold feature is enabled" line.long 0x3C "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold15,csmaxcount and count_dec value for Row No 15. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x3C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 15 when dynamic threshold feature is enabled" newline hexmask.long.word 0x3C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 15 when dynamic threshold feature is enabled" line.long 0x40 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold16,csmaxcount and count_dec value for Row No 16. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x40 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 16 when dynamic threshold feature is enabled" newline hexmask.long.word 0x40 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 16 when dynamic threshold feature is enabled" line.long 0x44 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold17,csmaxcount and count_dec value for Row No 17. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x44 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 17 when dynamic threshold feature is enabled" newline hexmask.long.word 0x44 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 17 when dynamic threshold feature is enabled" line.long 0x48 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold18,csmaxcount and count_dec value for Row No 18. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x48 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 18 when dynamic threshold feature is enabled" newline hexmask.long.word 0x48 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 18 when dynamic threshold feature is enabled" line.long 0x4C "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold19,csmaxcount and count_dec value for Row No 19. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x4C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 19 when dynamic threshold feature is enabled" newline hexmask.long.word 0x4C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 19 when dynamic threshold feature is enabled" line.long 0x50 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold20,csmaxcount and count_dec value for Row No 20. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x50 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 20 when dynamic threshold feature is enabled" newline hexmask.long.word 0x50 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 20 when dynamic threshold feature is enabled" line.long 0x54 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold21,csmaxcount and count_dec value for Row No 21. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x54 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 21 when dynamic threshold feature is enabled" newline hexmask.long.word 0x54 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 21 when dynamic threshold feature is enabled" line.long 0x58 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold22,csmaxcount and count_dec value for Row No 22. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x58 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 22 when dynamic threshold feature is enabled" newline hexmask.long.word 0x58 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 22 when dynamic threshold feature is enabled" line.long 0x5C "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold23,csmaxcount and count_dec value for Row No 23. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x5C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 23 when dynamic threshold feature is enabled" newline hexmask.long.word 0x5C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 23 when dynamic threshold feature is enabled" line.long 0x60 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold24,csmaxcount and count_dec value for Row No 24. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x60 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 24 when dynamic threshold feature is enabled" newline hexmask.long.word 0x60 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 24 when dynamic threshold feature is enabled" line.long 0x64 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold25,csmaxcount and count_dec value for Row No 25. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x64 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 25 when dynamic threshold feature is enabled" newline hexmask.long.word 0x64 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 25 when dynamic threshold feature is enabled" line.long 0x68 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold26,csmaxcount and count_dec value for Row No 26. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x68 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 26 when dynamic threshold feature is enabled" newline hexmask.long.word 0x68 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 26 when dynamic threshold feature is enabled" line.long 0x6C "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold27,csmaxcount and count_dec value for Row No 27. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x6C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 27 when dynamic threshold feature is enabled" newline hexmask.long.word 0x6C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 27 when dynamic threshold feature is enabled" line.long 0x70 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold28,csmaxcount and count_dec value for Row No 28. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x70 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 28 when dynamic threshold feature is enabled" newline hexmask.long.word 0x70 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 28 when dynamic threshold feature is enabled" line.long 0x74 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold29,csmaxcount and count_dec value for Row No 29. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x74 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 29 when dynamic threshold feature is enabled" newline hexmask.long.word 0x74 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 29 when dynamic threshold feature is enabled" line.long 0x78 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold30,csmaxcount and count_dec value for Row No 30. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x78 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 30 when dynamic threshold feature is enabled" newline hexmask.long.word 0x78 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 30 when dynamic threshold feature is enabled" line.long 0x7C "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold31,csmaxcount and count_dec value for Row No 31. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x7C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 31 when dynamic threshold feature is enabled" newline hexmask.long.word 0x7C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 31 when dynamic threshold feature is enabled" line.long 0x80 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold32,csmaxcount and count_dec value for Row No 32. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x80 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 32 when dynamic threshold feature is enabled" newline hexmask.long.word 0x80 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 32 when dynamic threshold feature is enabled" line.long 0x84 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold33,csmaxcount and count_dec value for Row No 33. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x84 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 33 when dynamic threshold feature is enabled" newline hexmask.long.word 0x84 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 33 when dynamic threshold feature is enabled" line.long 0x88 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold34,csmaxcount and count_dec value for Row No 34. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x88 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 34 when dynamic threshold feature is enabled" newline hexmask.long.word 0x88 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 34 when dynamic threshold feature is enabled" line.long 0x8C "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold35,csmaxcount and count_dec value for Row No 35. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x8C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 35 when dynamic threshold feature is enabled" newline hexmask.long.word 0x8C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 35 when dynamic threshold feature is enabled" line.long 0x90 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold36,csmaxcount and count_dec value for Row No 36. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x90 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 36 when dynamic threshold feature is enabled" newline hexmask.long.word 0x90 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 36 when dynamic threshold feature is enabled" line.long 0x94 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold37,csmaxcount and count_dec value for Row No 37. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x94 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 37 when dynamic threshold feature is enabled" newline hexmask.long.word 0x94 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 37 when dynamic threshold feature is enabled" line.long 0x98 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold38,csmaxcount and count_dec value for Row No 38. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x98 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 38 when dynamic threshold feature is enabled" newline hexmask.long.word 0x98 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 38 when dynamic threshold feature is enabled" line.long 0x9C "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold39,csmaxcount and count_dec value for Row No 39. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x9C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 39 when dynamic threshold feature is enabled" newline hexmask.long.word 0x9C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 39 when dynamic threshold feature is enabled" line.long 0xA0 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold40,csmaxcount and count_dec value for Row No 40. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xA0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 40 when dynamic threshold feature is enabled" newline hexmask.long.word 0xA0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 40 when dynamic threshold feature is enabled" line.long 0xA4 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold41,csmaxcount and count_dec value for Row No 41. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xA4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 41 when dynamic threshold feature is enabled" newline hexmask.long.word 0xA4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 41 when dynamic threshold feature is enabled" line.long 0xA8 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold42,csmaxcount and count_dec value for Row No 42. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xA8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 42 when dynamic threshold feature is enabled" newline hexmask.long.word 0xA8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 42 when dynamic threshold feature is enabled" line.long 0xAC "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold43,csmaxcount and count_dec value for Row No 43. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xAC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 43 when dynamic threshold feature is enabled" newline hexmask.long.word 0xAC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 43 when dynamic threshold feature is enabled" line.long 0xB0 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold44,csmaxcount and count_dec value for Row No 44. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xB0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 44 when dynamic threshold feature is enabled" newline hexmask.long.word 0xB0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 44 when dynamic threshold feature is enabled" line.long 0xB4 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold45,csmaxcount and count_dec value for Row No 45. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xB4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 45 when dynamic threshold feature is enabled" newline hexmask.long.word 0xB4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 45 when dynamic threshold feature is enabled" line.long 0xB8 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold46,csmaxcount and count_dec value for Row No 46. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xB8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 46 when dynamic threshold feature is enabled" newline hexmask.long.word 0xB8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 46 when dynamic threshold feature is enabled" line.long 0xBC "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold47,csmaxcount and count_dec value for Row No 47. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xBC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 47 when dynamic threshold feature is enabled" newline hexmask.long.word 0xBC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 47 when dynamic threshold feature is enabled" line.long 0xC0 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold48,csmaxcount and count_dec value for Row No 48. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xC0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 48 when dynamic threshold feature is enabled" newline hexmask.long.word 0xC0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 48 when dynamic threshold feature is enabled" line.long 0xC4 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold49,csmaxcount and count_dec value for Row No 49. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xC4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 49 when dynamic threshold feature is enabled" newline hexmask.long.word 0xC4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 49 when dynamic threshold feature is enabled" line.long 0xC8 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold50,csmaxcount and count_dec value for Row No 50. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xC8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 50 when dynamic threshold feature is enabled" newline hexmask.long.word 0xC8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 50 when dynamic threshold feature is enabled" line.long 0xCC "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold51,csmaxcount and count_dec value for Row No 51. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xCC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 51 when dynamic threshold feature is enabled" newline hexmask.long.word 0xCC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 51 when dynamic threshold feature is enabled" line.long 0xD0 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold52,csmaxcount and count_dec value for Row No 52. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xD0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 52 when dynamic threshold feature is enabled" newline hexmask.long.word 0xD0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 52 when dynamic threshold feature is enabled" line.long 0xD4 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold53,csmaxcount and count_dec value for Row No 53. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xD4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 53 when dynamic threshold feature is enabled" newline hexmask.long.word 0xD4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 53 when dynamic threshold feature is enabled" line.long 0xD8 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold54,csmaxcount and count_dec value for Row No 54. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xD8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 54 when dynamic threshold feature is enabled" newline hexmask.long.word 0xD8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 54 when dynamic threshold feature is enabled" line.long 0xDC "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold55,csmaxcount and count_dec value for Row No 55. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xDC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 55 when dynamic threshold feature is enabled" newline hexmask.long.word 0xDC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 55 when dynamic threshold feature is enabled" line.long 0xE0 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold56,csmaxcount and count_dec value for Row No 56. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xE0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 56 when dynamic threshold feature is enabled" newline hexmask.long.word 0xE0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 56 when dynamic threshold feature is enabled" line.long 0xE4 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold57,csmaxcount and count_dec value for Row No 57. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xE4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 57 when dynamic threshold feature is enabled" newline hexmask.long.word 0xE4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 57 when dynamic threshold feature is enabled" line.long 0xE8 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold58,csmaxcount and count_dec value for Row No 58. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xE8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 58 when dynamic threshold feature is enabled" newline hexmask.long.word 0xE8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 58 when dynamic threshold feature is enabled" line.long 0xEC "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold59,csmaxcount and count_dec value for Row No 59. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xEC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 59 when dynamic threshold feature is enabled" newline hexmask.long.word 0xEC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 59 when dynamic threshold feature is enabled" line.long 0xF0 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold60,csmaxcount and count_dec value for Row No 60. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xF0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 60 when dynamic threshold feature is enabled" newline hexmask.long.word 0xF0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 60 when dynamic threshold feature is enabled" line.long 0xF4 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold61,csmaxcount and count_dec value for Row No 61. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xF4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 61 when dynamic threshold feature is enabled" newline hexmask.long.word 0xF4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 61 when dynamic threshold feature is enabled" line.long 0xF8 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold62,csmaxcount and count_dec value for Row No 62. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xF8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 62 when dynamic threshold feature is enabled" newline hexmask.long.word 0xF8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 62 when dynamic threshold feature is enabled" line.long 0xFC "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold63,csmaxcount and count_dec value for Row No 63. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xFC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 63 when dynamic threshold feature is enabled" newline hexmask.long.word 0xFC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 63 when dynamic threshold feature is enabled" line.long 0x100 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold64,csmaxcount and count_dec value for Row No 64. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x100 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 64 when dynamic threshold feature is enabled" newline hexmask.long.word 0x100 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 64 when dynamic threshold feature is enabled" line.long 0x104 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold65,csmaxcount and count_dec value for Row No 65. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x104 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 65 when dynamic threshold feature is enabled" newline hexmask.long.word 0x104 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 65 when dynamic threshold feature is enabled" line.long 0x108 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold66,csmaxcount and count_dec value for Row No 66. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x108 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 66 when dynamic threshold feature is enabled" newline hexmask.long.word 0x108 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 66 when dynamic threshold feature is enabled" line.long 0x10C "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold67,csmaxcount and count_dec value for Row No 67. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x10C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 67 when dynamic threshold feature is enabled" newline hexmask.long.word 0x10C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 67 when dynamic threshold feature is enabled" line.long 0x110 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold68,csmaxcount and count_dec value for Row No 68. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x110 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 68 when dynamic threshold feature is enabled" newline hexmask.long.word 0x110 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 68 when dynamic threshold feature is enabled" line.long 0x114 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold69,csmaxcount and count_dec value for Row No 69. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x114 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 69 when dynamic threshold feature is enabled" newline hexmask.long.word 0x114 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 69 when dynamic threshold feature is enabled" line.long 0x118 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold70,csmaxcount and count_dec value for Row No 70. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x118 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 70 when dynamic threshold feature is enabled" newline hexmask.long.word 0x118 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 70 when dynamic threshold feature is enabled" line.long 0x11C "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold71,csmaxcount and count_dec value for Row No 71. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x11C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 71 when dynamic threshold feature is enabled" newline hexmask.long.word 0x11C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 71 when dynamic threshold feature is enabled" line.long 0x120 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold72,csmaxcount and count_dec value for Row No 72. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x120 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 72 when dynamic threshold feature is enabled" newline hexmask.long.word 0x120 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 72 when dynamic threshold feature is enabled" line.long 0x124 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold73,csmaxcount and count_dec value for Row No 73. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x124 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 73 when dynamic threshold feature is enabled" newline hexmask.long.word 0x124 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 73 when dynamic threshold feature is enabled" line.long 0x128 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold74,csmaxcount and count_dec value for Row No 74. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x128 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 74 when dynamic threshold feature is enabled" newline hexmask.long.word 0x128 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 74 when dynamic threshold feature is enabled" line.long 0x12C "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold75,csmaxcount and count_dec value for Row No 75. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x12C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 75 when dynamic threshold feature is enabled" newline hexmask.long.word 0x12C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 75 when dynamic threshold feature is enabled" line.long 0x130 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold76,csmaxcount and count_dec value for Row No 76. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x130 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 76 when dynamic threshold feature is enabled" newline hexmask.long.word 0x130 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 76 when dynamic threshold feature is enabled" line.long 0x134 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold77,csmaxcount and count_dec value for Row No 77. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x134 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 77 when dynamic threshold feature is enabled" newline hexmask.long.word 0x134 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 77 when dynamic threshold feature is enabled" line.long 0x138 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold78,csmaxcount and count_dec value for Row No 78. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x138 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 78 when dynamic threshold feature is enabled" newline hexmask.long.word 0x138 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 78 when dynamic threshold feature is enabled" line.long 0x13C "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold79,csmaxcount and count_dec value for Row No 79. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x13C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 79 when dynamic threshold feature is enabled" newline hexmask.long.word 0x13C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 79 when dynamic threshold feature is enabled" line.long 0x140 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold80,csmaxcount and count_dec value for Row No 80. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x140 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 80 when dynamic threshold feature is enabled" newline hexmask.long.word 0x140 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 80 when dynamic threshold feature is enabled" line.long 0x144 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold81,csmaxcount and count_dec value for Row No 81. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x144 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 81 when dynamic threshold feature is enabled" newline hexmask.long.word 0x144 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 81 when dynamic threshold feature is enabled" line.long 0x148 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold82,csmaxcount and count_dec value for Row No 82. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x148 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 82 when dynamic threshold feature is enabled" newline hexmask.long.word 0x148 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 82 when dynamic threshold feature is enabled" line.long 0x14C "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold83,csmaxcount and count_dec value for Row No 83. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x14C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 83 when dynamic threshold feature is enabled" newline hexmask.long.word 0x14C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 83 when dynamic threshold feature is enabled" line.long 0x150 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold84,csmaxcount and count_dec value for Row No 84. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x150 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 84 when dynamic threshold feature is enabled" newline hexmask.long.word 0x150 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 84 when dynamic threshold feature is enabled" line.long 0x154 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold85,csmaxcount and count_dec value for Row No 85. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x154 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 85 when dynamic threshold feature is enabled" newline hexmask.long.word 0x154 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 85 when dynamic threshold feature is enabled" line.long 0x158 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold86,csmaxcount and count_dec value for Row No 86. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x158 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 86 when dynamic threshold feature is enabled" newline hexmask.long.word 0x158 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 86 when dynamic threshold feature is enabled" line.long 0x15C "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold87,csmaxcount and count_dec value for Row No 87. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x15C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 87 when dynamic threshold feature is enabled" newline hexmask.long.word 0x15C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 87 when dynamic threshold feature is enabled" line.long 0x160 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold88,csmaxcount and count_dec value for Row No 88. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x160 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 88 when dynamic threshold feature is enabled" newline hexmask.long.word 0x160 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 88 when dynamic threshold feature is enabled" line.long 0x164 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold89,csmaxcount and count_dec value for Row No 89. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x164 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 89 when dynamic threshold feature is enabled" newline hexmask.long.word 0x164 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 89 when dynamic threshold feature is enabled" line.long 0x168 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold90,csmaxcount and count_dec value for Row No 90. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x168 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 90 when dynamic threshold feature is enabled" newline hexmask.long.word 0x168 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 90 when dynamic threshold feature is enabled" line.long 0x16C "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold91,csmaxcount and count_dec value for Row No 91. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x16C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 91 when dynamic threshold feature is enabled" newline hexmask.long.word 0x16C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 91 when dynamic threshold feature is enabled" line.long 0x170 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold92,csmaxcount and count_dec value for Row No 92. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x170 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 92 when dynamic threshold feature is enabled" newline hexmask.long.word 0x170 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 92 when dynamic threshold feature is enabled" line.long 0x174 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold93,csmaxcount and count_dec value for Row No 93. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x174 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 93 when dynamic threshold feature is enabled" newline hexmask.long.word 0x174 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 93 when dynamic threshold feature is enabled" line.long 0x178 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold94,csmaxcount and count_dec value for Row No 94. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x178 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 94 when dynamic threshold feature is enabled" newline hexmask.long.word 0x178 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 94 when dynamic threshold feature is enabled" line.long 0x17C "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold95,csmaxcount and count_dec value for Row No 95. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x17C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 95 when dynamic threshold feature is enabled" newline hexmask.long.word 0x17C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 95 when dynamic threshold feature is enabled" line.long 0x180 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold96,csmaxcount and count_dec value for Row No 96. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x180 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 96 when dynamic threshold feature is enabled" newline hexmask.long.word 0x180 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 96 when dynamic threshold feature is enabled" line.long 0x184 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold97,csmaxcount and count_dec value for Row No 97. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x184 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 97 when dynamic threshold feature is enabled" newline hexmask.long.word 0x184 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 97 when dynamic threshold feature is enabled" line.long 0x188 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold98,csmaxcount and count_dec value for Row No 98. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x188 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 98 when dynamic threshold feature is enabled" newline hexmask.long.word 0x188 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 98 when dynamic threshold feature is enabled" line.long 0x18C "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold99,csmaxcount and count_dec value for Row No 99. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x18C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 99 when dynamic threshold feature is enabled" newline hexmask.long.word 0x18C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 99 when dynamic threshold feature is enabled" line.long 0x190 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold100,csmaxcount and count_dec value for Row No 100. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x190 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 100 when dynamic threshold feature is enabled" newline hexmask.long.word 0x190 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 100 when dynamic threshold feature is enabled" line.long 0x194 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold101,csmaxcount and count_dec value for Row No 101. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x194 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 101 when dynamic threshold feature is enabled" newline hexmask.long.word 0x194 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 101 when dynamic threshold feature is enabled" line.long 0x198 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold102,csmaxcount and count_dec value for Row No 102. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x198 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 102 when dynamic threshold feature is enabled" newline hexmask.long.word 0x198 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 102 when dynamic threshold feature is enabled" line.long 0x19C "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold103,csmaxcount and count_dec value for Row No 103. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x19C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 103 when dynamic threshold feature is enabled" newline hexmask.long.word 0x19C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 103 when dynamic threshold feature is enabled" line.long 0x1A0 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold104,csmaxcount and count_dec value for Row No 104. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1A0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 104 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1A0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 104 when dynamic threshold feature is enabled" line.long 0x1A4 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold105,csmaxcount and count_dec value for Row No 105. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1A4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 105 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1A4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 105 when dynamic threshold feature is enabled" line.long 0x1A8 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold106,csmaxcount and count_dec value for Row No 106. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1A8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 106 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1A8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 106 when dynamic threshold feature is enabled" line.long 0x1AC "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold107,csmaxcount and count_dec value for Row No 107. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1AC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 107 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1AC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 107 when dynamic threshold feature is enabled" line.long 0x1B0 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold108,csmaxcount and count_dec value for Row No 108. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1B0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 108 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1B0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 108 when dynamic threshold feature is enabled" line.long 0x1B4 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold109,csmaxcount and count_dec value for Row No 109. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1B4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 109 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1B4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 109 when dynamic threshold feature is enabled" line.long 0x1B8 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold110,csmaxcount and count_dec value for Row No 110. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1B8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 110 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1B8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 110 when dynamic threshold feature is enabled" line.long 0x1BC "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold111,csmaxcount and count_dec value for Row No 111. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1BC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 111 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1BC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 111 when dynamic threshold feature is enabled" line.long 0x1C0 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold112,csmaxcount and count_dec value for Row No 112. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1C0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 112 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1C0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 112 when dynamic threshold feature is enabled" line.long 0x1C4 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold113,csmaxcount and count_dec value for Row No 113. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1C4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 113 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1C4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 113 when dynamic threshold feature is enabled" line.long 0x1C8 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold114,csmaxcount and count_dec value for Row No 114. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1C8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 114 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1C8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 114 when dynamic threshold feature is enabled" line.long 0x1CC "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold115,csmaxcount and count_dec value for Row No 115. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1CC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 115 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1CC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 115 when dynamic threshold feature is enabled" line.long 0x1D0 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold116,csmaxcount and count_dec value for Row No 116. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1D0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 116 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1D0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 116 when dynamic threshold feature is enabled" line.long 0x1D4 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold117,csmaxcount and count_dec value for Row No 117. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1D4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 117 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1D4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 117 when dynamic threshold feature is enabled" line.long 0x1D8 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold118,csmaxcount and count_dec value for Row No 118. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1D8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 118 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1D8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 118 when dynamic threshold feature is enabled" line.long 0x1DC "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold119,csmaxcount and count_dec value for Row No 119. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1DC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 119 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1DC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 119 when dynamic threshold feature is enabled" line.long 0x1E0 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold120,csmaxcount and count_dec value for Row No 120. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1E0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 120 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1E0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 120 when dynamic threshold feature is enabled" line.long 0x1E4 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold121,csmaxcount and count_dec value for Row No 121. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1E4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 121 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1E4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 121 when dynamic threshold feature is enabled" line.long 0x1E8 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold122,csmaxcount and count_dec value for Row No 122. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1E8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 122 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1E8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 122 when dynamic threshold feature is enabled" line.long 0x1EC "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold123,csmaxcount and count_dec value for Row No 123. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1EC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 123 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1EC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 123 when dynamic threshold feature is enabled" line.long 0x1F0 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold124,csmaxcount and count_dec value for Row No 124. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1F0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 124 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1F0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 124 when dynamic threshold feature is enabled" line.long 0x1F4 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold125,csmaxcount and count_dec value for Row No 125. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1F4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 125 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1F4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 125 when dynamic threshold feature is enabled" line.long 0x1F8 "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold126,csmaxcount and count_dec value for Row No 126. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1F8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 126 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1F8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 126 when dynamic threshold feature is enabled" line.long 0x1FC "HTS__S_VBUSP__REGS_HWA27_dynamic_threshold127,csmaxcount and count_dec value for Row No 127. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1FC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 127 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1FC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 127 when dynamic threshold feature is enabled" rgroup.long 0x5740++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA0_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA0" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA0 Scheduler resources must not be read during halted state. '1'-> DMA0 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA0 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA0 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA0_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x5760++0xB line.long 0x0 "HTS__S_VBUSP__REGS_DMA0_prod0_control,Controlling producer socket0 for DMA0" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA0 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA0_prod0_buf_control,Controlling producer socket0 buffer for DMA0" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA0_prod0_count,Defining count values for pre/post load for generating pend by DMA0 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x5780++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA1_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA1" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA1 Scheduler resources must not be read during halted state. '1'-> DMA1 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA1 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA1 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA1_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x57A0++0xB line.long 0x0 "HTS__S_VBUSP__REGS_DMA1_prod0_control,Controlling producer socket0 for DMA1" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA1 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA1_prod0_buf_control,Controlling producer socket0 buffer for DMA1" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA1_prod0_count,Defining count values for pre/post load for generating pend by DMA1 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x57C0++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA2_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA2" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA2 Scheduler resources must not be read during halted state. '1'-> DMA2 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA2 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA2 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA2_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x57E0++0xB line.long 0x0 "HTS__S_VBUSP__REGS_DMA2_prod0_control,Controlling producer socket0 for DMA2" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA2 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA2_prod0_buf_control,Controlling producer socket0 buffer for DMA2" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA2_prod0_count,Defining count values for pre/post load for generating pend by DMA2 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x5800++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA3_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA3" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA3 Scheduler resources must not be read during halted state. '1'-> DMA3 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA3 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA3 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA3_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x5820++0xB line.long 0x0 "HTS__S_VBUSP__REGS_DMA3_prod0_control,Controlling producer socket0 for DMA3" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA3 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA3_prod0_buf_control,Controlling producer socket0 buffer for DMA3" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA3_prod0_count,Defining count values for pre/post load for generating pend by DMA3 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x5840++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA4_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA4" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA4 Scheduler resources must not be read during halted state. '1'-> DMA4 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA4 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA4 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA4_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x5860++0xB line.long 0x0 "HTS__S_VBUSP__REGS_DMA4_prod0_control,Controlling producer socket0 for DMA4" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA4 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA4_prod0_buf_control,Controlling producer socket0 buffer for DMA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA4_prod0_count,Defining count values for pre/post load for generating pend by DMA4 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x5940++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA8_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA8" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA8 Scheduler resources must not be read during halted state. '1'-> DMA8 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA8 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA8 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA8_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x5960++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_DMA8_prod0_control,Controlling producer socket0 for DMA8" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA8 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA8_prod0_buf_control,Controlling producer socket0 buffer for DMA8" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA8_prod0_count,Defining count values for pre/post load for generating pend by DMA8 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_DMA8_pa0_control,control register to manage pattern adapter on DMA8 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_DMA8_pa0_prodcount,count values for HWA8 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x5980++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA9_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA9" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA9 Scheduler resources must not be read during halted state. '1'-> DMA9 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA9 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA9 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA9_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x59A0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_DMA9_prod0_control,Controlling producer socket0 for DMA9" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA9 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA9_prod0_buf_control,Controlling producer socket0 buffer for DMA9" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA9_prod0_count,Defining count values for pre/post load for generating pend by DMA9 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_DMA9_pa0_control,control register to manage pattern adapter on DMA9 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_DMA9_pa0_prodcount,count values for HWA9 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x59C0++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA10_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA10" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA10 Scheduler resources must not be read during halted state. '1'-> DMA10 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA10 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA10 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA10_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x59E0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_DMA10_prod0_control,Controlling producer socket0 for DMA10" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA10 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA10_prod0_buf_control,Controlling producer socket0 buffer for DMA10" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA10_prod0_count,Defining count values for pre/post load for generating pend by DMA10 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_DMA10_pa0_control,control register to manage pattern adapter on DMA10 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_DMA10_pa0_prodcount,count values for HWA10 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x5F40++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA32_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA32" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA32 Scheduler resources must not be read during halted state. '1'-> DMA32 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA32 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA32 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA32_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x5F60++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_DMA32_prod0_control,Controlling producer socket0 for DMA32" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA32 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA32_prod0_buf_control,Controlling producer socket0 buffer for DMA32" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA32_prod0_count,Defining count values for pre/post load for generating pend by DMA32 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_DMA32_pa0_control,control register to manage pattern adapter on DMA32 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_DMA32_pa0_prodcount,count values for HWA32 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x5F80++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA33_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA33" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA33 Scheduler resources must not be read during halted state. '1'-> DMA33 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA33 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA33 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA33_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x5FA0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_DMA33_prod0_control,Controlling producer socket0 for DMA33" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA33 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA33_prod0_buf_control,Controlling producer socket0 buffer for DMA33" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA33_prod0_count,Defining count values for pre/post load for generating pend by DMA33 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_DMA33_pa0_control,control register to manage pattern adapter on DMA33 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_DMA33_pa0_prodcount,count values for HWA33 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x6140++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA40_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA40" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA40 Scheduler resources must not be read during halted state. '1'-> DMA40 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA40 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA40 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA40_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x6160++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_DMA40_prod0_control,Controlling producer socket0 for DMA40" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA40 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA40_prod0_buf_control,Controlling producer socket0 buffer for DMA40" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA40_prod0_count,Defining count values for pre/post load for generating pend by DMA40 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_DMA40_pa0_control,control register to manage pattern adapter on DMA40 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_DMA40_pa0_prodcount,count values for HWA40 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x6180++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA41_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA41" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA41 Scheduler resources must not be read during halted state. '1'-> DMA41 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA41 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA41 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA41_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x61A0++0x13 line.long 0x0 "HTS__S_VBUSP__REGS_DMA41_prod0_control,Controlling producer socket0 for DMA41" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA41 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA41_prod0_buf_control,Controlling producer socket0 buffer for DMA41" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA41_prod0_count,Defining count values for pre/post load for generating pend by DMA41 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "HTS__S_VBUSP__REGS_DMA41_pa0_control,control register to manage pattern adapter on DMA41 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0,1" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1" line.long 0x10 "HTS__S_VBUSP__REGS_DMA41_pa0_prodcount,count values for HWA41 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" rgroup.long 0x6340++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA48_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA48" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA48 Scheduler resources must not be read during halted state. '1'-> DMA48 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA48 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA48 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA48_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x6360++0xB line.long 0x0 "HTS__S_VBUSP__REGS_DMA48_prod0_control,Controlling producer socket0 for DMA48" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA48 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA48_prod0_buf_control,Controlling producer socket0 buffer for DMA48" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA48_prod0_count,Defining count values for pre/post load for generating pend by DMA48 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x6540++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA56_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA56" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA56 Scheduler resources must not be read during halted state. '1'-> DMA56 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA56 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA56 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA56_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x6560++0xB line.long 0x0 "HTS__S_VBUSP__REGS_DMA56_prod0_control,Controlling producer socket0 for DMA56" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA56 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA56_prod0_buf_control,Controlling producer socket0 buffer for DMA56" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA56_prod0_count,Defining count values for pre/post load for generating pend by DMA56 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x6580++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA57_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA57" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA57 Scheduler resources must not be read during halted state. '1'-> DMA57 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA57 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA57 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA57_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x65A0++0xB line.long 0x0 "HTS__S_VBUSP__REGS_DMA57_prod0_control,Controlling producer socket0 for DMA57" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA57 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA57_prod0_buf_control,Controlling producer socket0 buffer for DMA57" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA57_prod0_count,Defining count values for pre/post load for generating pend by DMA57 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x65C0++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA58_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA58" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA58 Scheduler resources must not be read during halted state. '1'-> DMA58 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA58 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA58 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA58_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x65E0++0xB line.long 0x0 "HTS__S_VBUSP__REGS_DMA58_prod0_control,Controlling producer socket0 for DMA58" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA58 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA58_prod0_buf_control,Controlling producer socket0 buffer for DMA58" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA58_prod0_count,Defining count values for pre/post load for generating pend by DMA58 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x6600++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA59_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA59" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA59 Scheduler resources must not be read during halted state. '1'-> DMA59 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA59 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA59 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA59_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x6620++0xB line.long 0x0 "HTS__S_VBUSP__REGS_DMA59_prod0_control,Controlling producer socket0 for DMA59" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA59 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA59_prod0_buf_control,Controlling producer socket0 buffer for DMA59" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA59_prod0_count,Defining count values for pre/post load for generating pend by DMA59 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x6740++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA64_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA64" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA64 Scheduler resources must not be read during halted state. '1'-> DMA64 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA64 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA64 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA64_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x6760++0xB line.long 0x0 "HTS__S_VBUSP__REGS_DMA64_prod0_control,Controlling producer socket0 for DMA64" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA64 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA64_prod0_buf_control,Controlling producer socket0 buffer for DMA64" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA64_prod0_count,Defining count values for pre/post load for generating pend by DMA64 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x6780++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA65_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA65" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA65 Scheduler resources must not be read during halted state. '1'-> DMA65 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA65 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA65 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA65_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x67A0++0xB line.long 0x0 "HTS__S_VBUSP__REGS_DMA65_prod0_control,Controlling producer socket0 for DMA65" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA65 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA65_prod0_buf_control,Controlling producer socket0 buffer for DMA65" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA65_prod0_count,Defining count values for pre/post load for generating pend by DMA65 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x67C0++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA66_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA66" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA66 Scheduler resources must not be read during halted state. '1'-> DMA66 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA66 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA66 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA66_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x67E0++0xB line.long 0x0 "HTS__S_VBUSP__REGS_DMA66_prod0_control,Controlling producer socket0 for DMA66" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA66 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA66_prod0_buf_control,Controlling producer socket0 buffer for DMA66" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA66_prod0_count,Defining count values for pre/post load for generating pend by DMA66 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x6800++0x7 line.long 0x0 "HTS__S_VBUSP__REGS_DMA67_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA67" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA67 Scheduler resources must not be read during halted state. '1'-> DMA67 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA67 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA67 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA67_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0,1" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1" rgroup.long 0x6820++0xB line.long 0x0 "HTS__S_VBUSP__REGS_DMA67_prod0_control,Controlling producer socket0 for DMA67" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA67 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1" line.long 0x4 "HTS__S_VBUSP__REGS_DMA67_prod0_buf_control,Controlling producer socket0 buffer for DMA67" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "HTS__S_VBUSP__REGS_DMA67_prod0_count,Defining count values for pre/post load for generating pend by DMA67 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" rgroup.long 0x9340++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA240_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA240" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA240 Scheduler resources must not be read during halted state. '1'-> DMA240 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA240 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA240 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9360++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA240_cons0_control,Controlling consumer socket 0 for DMA240" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA240 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9368++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA241_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA241" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA241 Scheduler resources must not be read during halted state. '1'-> DMA241 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA241 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA241 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9388++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA241_cons0_control,Controlling consumer socket 0 for DMA241" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA241 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9390++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA242_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA242" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA242 Scheduler resources must not be read during halted state. '1'-> DMA242 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA242 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA242 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x93B0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA242_cons0_control,Controlling consumer socket 0 for DMA242" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA242 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x93B8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA243_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA243" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA243 Scheduler resources must not be read during halted state. '1'-> DMA243 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA243 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA243 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x93D8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA243_cons0_control,Controlling consumer socket 0 for DMA243" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA243 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x93E0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA244_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA244" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA244 Scheduler resources must not be read during halted state. '1'-> DMA244 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA244 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA244 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9400++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA244_cons0_control,Controlling consumer socket 0 for DMA244" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA244 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9408++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA245_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA245" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA245 Scheduler resources must not be read during halted state. '1'-> DMA245 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA245 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA245 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9428++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA245_cons0_control,Controlling consumer socket 0 for DMA245" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA245 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x95C0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA256_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA256" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA256 Scheduler resources must not be read during halted state. '1'-> DMA256 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA256 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA256 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x95E0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA256_cons0_control,Controlling consumer socket 0 for DMA256" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA256 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x95E8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA257_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA257" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA257 Scheduler resources must not be read during halted state. '1'-> DMA257 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA257 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA257 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9608++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA257_cons0_control,Controlling consumer socket 0 for DMA257" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA257 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9610++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA258_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA258" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA258 Scheduler resources must not be read during halted state. '1'-> DMA258 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA258 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA258 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9630++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA258_cons0_control,Controlling consumer socket 0 for DMA258" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA258 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9638++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA259_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA259" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA259 Scheduler resources must not be read during halted state. '1'-> DMA259 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA259 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA259 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9658++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA259_cons0_control,Controlling consumer socket 0 for DMA259" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA259 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9660++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA260_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA260" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA260 Scheduler resources must not be read during halted state. '1'-> DMA260 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA260 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA260 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9680++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA260_cons0_control,Controlling consumer socket 0 for DMA260" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA260 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9688++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA261_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA261" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA261 Scheduler resources must not be read during halted state. '1'-> DMA261 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA261 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA261 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x96A8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA261_cons0_control,Controlling consumer socket 0 for DMA261" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA261 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9840++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA272_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA272" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA272 Scheduler resources must not be read during halted state. '1'-> DMA272 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA272 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA272 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9860++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA272_cons0_control,Controlling consumer socket 0 for DMA272" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA272 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9868++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA273_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA273" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA273 Scheduler resources must not be read during halted state. '1'-> DMA273 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA273 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA273 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9888++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA273_cons0_control,Controlling consumer socket 0 for DMA273" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA273 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9890++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA274_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA274" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA274 Scheduler resources must not be read during halted state. '1'-> DMA274 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA274 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA274 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x98B0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA274_cons0_control,Controlling consumer socket 0 for DMA274" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA274 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x98B8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA275_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA275" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA275 Scheduler resources must not be read during halted state. '1'-> DMA275 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA275 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA275 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x98D8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA275_cons0_control,Controlling consumer socket 0 for DMA275" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA275 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9AC0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA288_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA288" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA288 Scheduler resources must not be read during halted state. '1'-> DMA288 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA288 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA288 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9AE0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA288_cons0_control,Controlling consumer socket 0 for DMA288" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA288 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9AE8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA289_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA289" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA289 Scheduler resources must not be read during halted state. '1'-> DMA289 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA289 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA289 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9B08++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA289_cons0_control,Controlling consumer socket 0 for DMA289" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA289 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9B10++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA290_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA290" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA290 Scheduler resources must not be read during halted state. '1'-> DMA290 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA290 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA290 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9B30++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA290_cons0_control,Controlling consumer socket 0 for DMA290" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA290 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9B38++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA291_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA291" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA291 Scheduler resources must not be read during halted state. '1'-> DMA291 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA291 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA291 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9B58++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA291_cons0_control,Controlling consumer socket 0 for DMA291" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA291 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9D40++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA304_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA304" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA304 Scheduler resources must not be read during halted state. '1'-> DMA304 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA304 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA304 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9D60++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA304_cons0_control,Controlling consumer socket 0 for DMA304" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA304 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9D68++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA305_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA305" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA305 Scheduler resources must not be read during halted state. '1'-> DMA305 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA305 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA305 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9D88++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA305_cons0_control,Controlling consumer socket 0 for DMA305" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA305 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9D90++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA306_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA306" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA306 Scheduler resources must not be read during halted state. '1'-> DMA306 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA306 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA306 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9DB0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA306_cons0_control,Controlling consumer socket 0 for DMA306" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA306 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9DB8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA307_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA307" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA307 Scheduler resources must not be read during halted state. '1'-> DMA307 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA307 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA307 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9DD8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA307_cons0_control,Controlling consumer socket 0 for DMA307" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA307 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9DE0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA308_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA308" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA308 Scheduler resources must not be read during halted state. '1'-> DMA308 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA308 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA308 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9E00++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA308_cons0_control,Controlling consumer socket 0 for DMA308" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA308 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9E08++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA309_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA309" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA309 Scheduler resources must not be read during halted state. '1'-> DMA309 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA309 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA309 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9E28++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA309_cons0_control,Controlling consumer socket 0 for DMA309" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA309 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9E30++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA310_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA310" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA310 Scheduler resources must not be read during halted state. '1'-> DMA310 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA310 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA310 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9E50++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA310_cons0_control,Controlling consumer socket 0 for DMA310" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA310 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9E58++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA311_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA311" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA311 Scheduler resources must not be read during halted state. '1'-> DMA311 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA311 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA311 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9E78++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA311_cons0_control,Controlling consumer socket 0 for DMA311" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA311 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9E80++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA312_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA312" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA312 Scheduler resources must not be read during halted state. '1'-> DMA312 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA312 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA312 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9EA0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA312_cons0_control,Controlling consumer socket 0 for DMA312" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA312 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0x9EA8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA313_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA313" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA313 Scheduler resources must not be read during halted state. '1'-> DMA313 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA313 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA313 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0x9EC8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA313_cons0_control,Controlling consumer socket 0 for DMA313" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA313 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0xA240++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA336_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA336" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA336 Scheduler resources must not be read during halted state. '1'-> DMA336 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA336 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA336 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0xA260++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA336_cons0_control,Controlling consumer socket 0 for DMA336" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA336 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0xA4C0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA352_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA352" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA352 Scheduler resources must not be read during halted state. '1'-> DMA352 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA352 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA352 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0xA4E0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA352_cons0_control,Controlling consumer socket 0 for DMA352" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA352 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0xA4E8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA353_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA353" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA353 Scheduler resources must not be read during halted state. '1'-> DMA353 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA353 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA353 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0xA508++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA353_cons0_control,Controlling consumer socket 0 for DMA353" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA353 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0xA510++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA354_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA354" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA354 Scheduler resources must not be read during halted state. '1'-> DMA354 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA354 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA354 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0xA530++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA354_cons0_control,Controlling consumer socket 0 for DMA354" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA354 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0xA538++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA355_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA355" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA355 Scheduler resources must not be read during halted state. '1'-> DMA355 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA355 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA355 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0xA558++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA355_cons0_control,Controlling consumer socket 0 for DMA355" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA355 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0xA740++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA368_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA368" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA368 Scheduler resources must not be read during halted state. '1'-> DMA368 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA368 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA368 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0xA760++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA368_cons0_control,Controlling consumer socket 0 for DMA368" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA368 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0xA768++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA369_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA369" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA369 Scheduler resources must not be read during halted state. '1'-> DMA369 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA369 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA369 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0xA788++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA369_cons0_control,Controlling consumer socket 0 for DMA369" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA369 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0xA790++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA370_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA370" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA370 Scheduler resources must not be read during halted state. '1'-> DMA370 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA370 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA370 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0xA7B0++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA370_cons0_control,Controlling consumer socket 0 for DMA370" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA370 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" rgroup.long 0xA7B8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA371_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA371" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA371 Scheduler resources must not be read during halted state. '1'-> DMA371 Scheduler resources are readable during halted state" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA371 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA371 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" rgroup.long 0xA7D8++0x3 line.long 0x0 "HTS__S_VBUSP__REGS_DMA371_cons0_control,Controlling consumer socket 0 for DMA371" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA371 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1" tree.end tree "VPAC0_LDC_ECC_AGGR (VPAC0_LDC_ECC_AGGR)" base ad:0x2A63000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 11. "MESHMEM_B3_P1_RAMECC_PEND,Interrupt Pending Status for meshmem_b3_p1_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "MESHMEM_B2_P1_RAMECC_PEND,Interrupt Pending Status for meshmem_b2_p1_ramecc_pend" "0,1" newline bitfld.long 0x4 9. "MESHMEM_B1_P1_RAMECC_PEND,Interrupt Pending Status for meshmem_b1_p1_ramecc_pend" "0,1" newline bitfld.long 0x4 8. "MESHMEM_B0_P1_RAMECC_PEND,Interrupt Pending Status for meshmem_b0_p1_ramecc_pend" "0,1" newline bitfld.long 0x4 7. "MESHMEM_B3_P0_RAMECC_PEND,Interrupt Pending Status for meshmem_b3_p0_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "MESHMEM_B2_P0_RAMECC_PEND,Interrupt Pending Status for meshmem_b2_p0_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "MESHMEM_B1_P0_RAMECC_PEND,Interrupt Pending Status for meshmem_b1_p0_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "MESHMEM_B0_P0_RAMECC_PEND,Interrupt Pending Status for meshmem_b0_p0_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "DUALC_LUT_B1_RAMECC_PEND,Interrupt Pending Status for dualc_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "DUALC_LUT_B0_RAMECC_PEND,Interrupt Pending Status for dualc_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "DUALY_LUT_B1_RAMECC_PEND,Interrupt Pending Status for dualy_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "DUALY_LUT_B0_RAMECC_PEND,Interrupt Pending Status for dualy_lut_b0_ramecc_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 11. "MESHMEM_B3_P1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b3_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "MESHMEM_B2_P1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b2_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "MESHMEM_B1_P1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b1_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "MESHMEM_B0_P1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b0_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "MESHMEM_B3_P0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b3_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "MESHMEM_B2_P0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b2_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "MESHMEM_B1_P0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b1_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "MESHMEM_B0_P0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b0_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "DUALC_LUT_B1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dualc_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "DUALC_LUT_B0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dualc_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "DUALY_LUT_B1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dualy_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "DUALY_LUT_B0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dualy_lut_b0_ramecc_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 11. "MESHMEM_B3_P1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b3_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "MESHMEM_B2_P1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b2_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "MESHMEM_B1_P1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b1_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "MESHMEM_B0_P1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b0_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "MESHMEM_B3_P0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b3_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "MESHMEM_B2_P0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b2_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "MESHMEM_B1_P0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b1_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "MESHMEM_B0_P0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b0_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "DUALC_LUT_B1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dualc_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "DUALC_LUT_B0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dualc_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "DUALY_LUT_B1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dualy_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "DUALY_LUT_B0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dualy_lut_b0_ramecc_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 11. "MESHMEM_B3_P1_RAMECC_PEND,Interrupt Pending Status for meshmem_b3_p1_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "MESHMEM_B2_P1_RAMECC_PEND,Interrupt Pending Status for meshmem_b2_p1_ramecc_pend" "0,1" newline bitfld.long 0x4 9. "MESHMEM_B1_P1_RAMECC_PEND,Interrupt Pending Status for meshmem_b1_p1_ramecc_pend" "0,1" newline bitfld.long 0x4 8. "MESHMEM_B0_P1_RAMECC_PEND,Interrupt Pending Status for meshmem_b0_p1_ramecc_pend" "0,1" newline bitfld.long 0x4 7. "MESHMEM_B3_P0_RAMECC_PEND,Interrupt Pending Status for meshmem_b3_p0_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "MESHMEM_B2_P0_RAMECC_PEND,Interrupt Pending Status for meshmem_b2_p0_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "MESHMEM_B1_P0_RAMECC_PEND,Interrupt Pending Status for meshmem_b1_p0_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "MESHMEM_B0_P0_RAMECC_PEND,Interrupt Pending Status for meshmem_b0_p0_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "DUALC_LUT_B1_RAMECC_PEND,Interrupt Pending Status for dualc_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "DUALC_LUT_B0_RAMECC_PEND,Interrupt Pending Status for dualc_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "DUALY_LUT_B1_RAMECC_PEND,Interrupt Pending Status for dualy_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "DUALY_LUT_B0_RAMECC_PEND,Interrupt Pending Status for dualy_lut_b0_ramecc_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 11. "MESHMEM_B3_P1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b3_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "MESHMEM_B2_P1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b2_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "MESHMEM_B1_P1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b1_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "MESHMEM_B0_P1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b0_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "MESHMEM_B3_P0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b3_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "MESHMEM_B2_P0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b2_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "MESHMEM_B1_P0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b1_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "MESHMEM_B0_P0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b0_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "DUALC_LUT_B1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dualc_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "DUALC_LUT_B0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dualc_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "DUALY_LUT_B1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dualy_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "DUALY_LUT_B0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dualy_lut_b0_ramecc_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 11. "MESHMEM_B3_P1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b3_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "MESHMEM_B2_P1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b2_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "MESHMEM_B1_P1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b1_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "MESHMEM_B0_P1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b0_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "MESHMEM_B3_P0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b3_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "MESHMEM_B2_P0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b2_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "MESHMEM_B1_P0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b1_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "MESHMEM_B0_P0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b0_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "DUALC_LUT_B1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dualc_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "DUALC_LUT_B0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dualc_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "DUALY_LUT_B1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dualy_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "DUALY_LUT_B0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dualy_lut_b0_ramecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "VPAC0_PAR_VPAC" tree "VPAC0_PAR_VPAC_LDC0" tree "VPAC0_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_CBCR_VBUSPI_CBCR_MEM (VPAC0_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_CBCR_VBUSPI_CBCR_MEM)" base ad:0x3830000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__MEMCFG_LOOP__CBCR_VBUSPI__CBCR_MEM_RAM,cbcr memory" hexmask.long.tbyte 0x0 0.--23. 1. "MEM,Memory location" tree.end tree "VPAC0_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_MESH_VBUSPI_MESH_MEM (VPAC0_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_MESH_VBUSPI_MESH_MEM)" base ad:0x3822000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__MEMCFG_LOOP__MESH_VBUSPI__MESH_MEM_RAM,mesh memory" hexmask.long 0x0 0.--31. 1. "MEM,Memory location" tree.end tree "VPAC0_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_Y_VBUSPI_Y_MEM (VPAC0_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_Y_VBUSPI_Y_MEM)" base ad:0x3828000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__MEMCFG_LOOP__Y_VBUSPI__Y_MEM_RAM,y memory" hexmask.long.tbyte 0x0 0.--23. 1. "MEM,Memory location" tree.end tree "VPAC0_PAR_VPAC_LDC0_S_VBUSP_MMR_VBUSP (VPAC0_PAR_VPAC_LDC0_S_VBUSP_MMR_VBUSP)" base ad:0x3820000 rgroup.long 0x0++0x7 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_REVISION_REG,LDC PID" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and new scheme. Spare bit to encode future schemes" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU indicator DSPS ==> 0x0 WTBU ==> 0x1 Processors ==> 0x2" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family. If there is no level of software compatibility a new FUNC number and hence PID should be assigned." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version. R as described in PDR with additional clarifications and definitions below. Must be easily ECO-able or controlled during fabrication. Ideally through a top level metal mask or e-fuse. This number is maintained/owned by IP design.." newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision. X as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. X is part of IP numbering X.Y.R.Z. X changes ONLY when: (1) There is a major feature addition. An.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library (CSL) / Drivers. 0 if non-custom." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision. Y as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. Y changes ONLY when: (1) Features are scaled (up or down). Flexibility exists in that this.." line.long 0x4 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_PRIVATE_MEMSIZE,Memory size mentioned is for both ping and pong combined." hexmask.long.byte 0x4 16.--23. 1. "MESH,Mesh Private pixel memory size in KBytes" newline hexmask.long.byte 0x4 8.--15. 1. "CHROMA,Chroma Private pixel memory size in KBytes" newline hexmask.long.byte 0x4 0.--7. 1. "LUMA,Luma Private pixel memory size in KBytes" rgroup.long 0x8++0x8B line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_CTRL,Control Register to Enable/Disable and select modes of operation" bitfld.long 0x0 24. "HYBD_ADDREN,Hybrid addressing scheme Enable. Enabled when part of the data stored in circular buffer and rest in Linear addressing buffers. When enabled IP_CIRCEN should be high and can only be enabled in frame mode." "0,1" newline bitfld.long 0x0 17.--18. "CH_IP_DFMT,Chroma Input pixel data format. Valid only independent chroma channel control is enbaled (CH_CHANCTRL_EN=1). 0: 8-bit format 1: 12-bit packed format 2: 12-bit unpacked format 3: Reserved" "?,?,?,3: Reserved" newline bitfld.long 0x0 16. "CH_CHANCTRL_EN,Enable for Independent Chroma Channel parameters. Can be enabled only when chroma data is in separate buffer. When enabled Chroma channel parameters - Input Data Format/Line Offset/Circular buffer size/hybrid addressing parameters should.." "0,1" newline bitfld.long 0x0 14. "REGMODE_EN,Enables for Frame division into multiple regions. Needs to be enabled only when more than one region per frame. 0 - Disable 1 - Enable When enabled LDC provides option to configure independent block size parameters for each region" "0: Disable 1,?" newline bitfld.long 0x0 13. "OP_DATAMODE,Output Pixel Data Mode; Used when input is YUV422* mode. 0: YUV422 mode 1: convert to YUV420 output data;" "0: YUV422 mode,1: convert to YUV420 output data;" newline bitfld.long 0x0 12. "IP_HTS_ROWSYNC,Enables control of Input Fetch with HTS at Block Row level. 0 - Disable 1 - Enable When enabled input fetch of first block in row is gated with corresponding HTS Tstart number. This allows synchronization between VISS and LDC or/and.." "0: Disable 1,?" newline bitfld.long 0x0 11. "IP_CIRCEN,Enables circular addressing mode on input pixel fetch. Can only be enabled in Frame mode. 0 - Disable circular addressing for input data. 1 - Enable circular addressing." "0: Disable circular addressing for input data,1: Enable circular addressing" newline bitfld.long 0x0 10. "ALIGN_12BIT,Alignment of 12-bit pixel in 16-bit unpacked data format on input pixel data. Common for both Luma and Chroma channels. 0 - LSB Aligned 1 - MSB Aligned" "0: LSB Aligned 1,?" newline bitfld.long 0x0 9. "PWARPEN,Perspective warp transform Enable. Set to 1 to enable use of PWARP_GH.G and PWARP_GH.H" "0,1" newline bitfld.long 0x0 7.--8. "IP_DFMT,Input Pixel Data Format 0: 8-bit format 1: 12-bit packed format 2: 12-bit unpacked format 3: Reserved" "?,?,?,3: Reserved" newline hexmask.long.byte 0x0 3.--6. 1. "IP_DATAMODE,Input Pixel Data Mode 0: YUV422 UYVY Interleaved data 1: YUV420_Y Luma Data Only 2: YUV420 Data 3: YUV420_UV Chroma Data Only. 4: YUV422_SP Semi-Planar Data. 5: Y1_Y2 - 2 independent channel data at full resolution in separate.." newline rbitfld.long 0x0 2. "BUSY,Idle/Busy Status 0: Idle 1: Busy Set on hts_init when LDC_EN is high cleared on Frame completion" "0: Idle,1: Busy Set on hts_init when LDC_EN is high" newline bitfld.long 0x0 1. "LDMAPEN,Distortion Back Mapping Enable. 1: Enabled 0: Disabled" "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "LDC_EN,Write 1 to enable LDC function. Auto cleared by HW at the end of Frame in OneShoft mode. In continuous mode needs to cleared by SW at the end to enter Idle condition" "0,1" line.long 0x4 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_CFG,LDC Configuration register." bitfld.long 0x4 6. "YINT_TYP,Interpolation type for Y data. 0: bicubic 1: bilinear" "0: bicubic,1: bilinear" newline bitfld.long 0x4 2. "CNTU_MODE,Continuous mode enable. When enabled LDC HW won't disable at the end of frame and will start frame processing on hts_init. 0: One Shot mode (default) - LDC enable is cleared at the end of frame 1: Continous mode - LDC will continue to be.." "0: One Shot mode,1: Continous mode" newline bitfld.long 0x4 1. "CLKCG_OVERIDE,Reserved. Write has no effect" "0,1" line.long 0x8 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_MESHTABLE_CFG,Defines the down-sampling factors used for the mesh offset tables" bitfld.long 0x8 0.--2. "M,Mesh table down-sampling factor (by 2^M in both horizontal and Vertical). 0: 1 - no down-sampling 1: 2 - 2x down-sampling 2: 4 3: 8 4: 16 5: 32 6: 64 7:128" "?,1: no down-sampling,?,?,?,?,?,?" line.long 0xC "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_MESH_FRSZ,Mesh data mapping is available for this Frame size. Actual number of mesh data entires depend Mesh Frame size and Mesh sampling factor. This Frame size is independent from COMPUTE_FRSZ" hexmask.long.word 0xC 16.--29. 1. "H,Mesh Frame height in Lines" newline hexmask.long.word 0xC 0.--13. 1. "W,Mesh Frame Width" line.long 0x10 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_COMPUTE_FRSZ,H corresponds to the total number of lines to process. W corresponds to the number of pixels to process in each line. This parameters must be loaded as actual pixel counts. NOT pixel counts - 1." hexmask.long.word 0x10 16.--29. 1. "H,Output Frame height in Lines. Must be even" newline hexmask.long.word 0x10 0.--13. 1. "W,Output Frame Width. Must be even" line.long 0x14 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_INITXY,LDC Initial Output Co-ordinate to process" hexmask.long.word 0x14 16.--28. 1. "INITY,Output starting Y-coordinate. must be even" newline hexmask.long.word 0x14 0.--12. 1. "INITX,Output starting X-coordinate. must be even" line.long 0x18 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_INPUT_FRSZ,Defines the total input frame size" hexmask.long.word 0x18 16.--29. 1. "H,Input Frame height in Lines. Must be even" newline hexmask.long.word 0x18 0.--13. 1. "W,Input Frame Width in Pixels. Must be even" line.long 0x1C "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_OUT_BLKSZ,LDC Output Block parameter registers. These parameters represent actual pixel counts. NOT pixel counts - 1. OBW must be greater than 0 and less than or equal to frame width (COMPUTE_FRSZ.W). OBH must be.." hexmask.long.byte 0x1C 16.--19. 1. "PIXPAD,Pixel pad" newline hexmask.long.byte 0x1C 8.--15. 1. "OBH,Output block height must be >0 and even" newline hexmask.long.byte 0x1C 0.--7. 1. "OBW,Output block width must be >0 and multiple of 8" line.long 0x20 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_AFF_AB,LDC Affine Transwarp A/B" hexmask.long.word 0x20 16.--31. 1. "B,Affine transwarp B (S16Q12)" newline hexmask.long.word 0x20 0.--15. 1. "A,Affine transwarp A (S16Q12)" line.long 0x24 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_AFF_CD,LDC Affine Transwarp C/D" hexmask.long.word 0x24 16.--31. 1. "D,Affine transwarp D (S16Q12)" newline hexmask.long.word 0x24 0.--15. 1. "C,Affine transwarp C (S16Q3)" line.long 0x28 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_AFF_EF,LDC Affine Transwarp E/F" hexmask.long.word 0x28 16.--31. 1. "F,Affine transwarp F (S16Q3)" newline hexmask.long.word 0x28 0.--15. 1. "E,Affine transwarp E (S16Q12)" line.long 0x2C "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_PWARP_GH,LDC Perspective Transformation Parameters. G and H" hexmask.long.word 0x2C 16.--31. 1. "H,Perspective Transformation H (S16Q23)" newline hexmask.long.word 0x2C 0.--15. 1. "G,Perspective Transformation H (S16Q23)" line.long 0x30 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_MESH_BASE_H,Higher 16-bit of Mesh Table Base Address" hexmask.long.word 0x30 0.--15. 1. "ADDR,Higher 16-bit of Read Base address for mesh offset table" line.long 0x34 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_MESH_BASE_L,Lower 32-bit of Mesh Table Base Address" hexmask.long 0x34 0.--31. 1. "ADDR,Lower 32-bit of Read Base address for mesh offset table. Must be 16-byte aligned so four LSB are coded to 0" line.long 0x38 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_MESH_OFST,Defines the stride between rows for the Mesh table in bytes." hexmask.long.word 0x38 0.--15. 1. "OFST,LDC Mesh table line offset must be 16-byte aligned so four LSB are coded to 0" line.long 0x3C "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_RD_BASE_H,Higher 16-bit of Input Frame Base Address" hexmask.long.word 0x3C 0.--15. 1. "ADDR,Higher 16-bit of Input Frame Base Address" line.long 0x40 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_RD_BASE_L,Lower 32-bit of Input Frame Base Address" hexmask.long 0x40 0.--31. 1. "ADDR,Lower 32-bit of Read Base address of Input Frame Base Address. Must be 16-byte aligned so four LSB are coded to 0" line.long 0x44 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_RD_420C_BASE_H,Higher 16-bit of Input Frame 420C Base Address" hexmask.long.word 0x44 0.--15. 1. "ADDR,Higher 16-bit of Input Frame Chroma Base Address in YUV420" line.long 0x48 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_RD_420C_BASE_L,Lower 32-bit of Input Frame Chroma Base Address in YUV420" hexmask.long 0x48 0.--31. 1. "ADDR,Lower 32-bit of Read Base address of Input Frame Chroma Base Address in YUV420. Must be 16-byte aligned so four LSB are coded to 0" line.long 0x4C "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_RD_OFST,Define stride between lines in the Input Frame in bytes and circular buffer height" hexmask.long.word 0x4C 16.--29. 1. "MOD,Sets the circular buffer size if circular buffering mode is used. The circular buffer is sized in terms of number of lines and has to be multiple of 2" newline hexmask.long.word 0x4C 0.--15. 1. "OFST,Read frame line offset must be 16-byte aligned so internally [3:0] bits are hard-wired zero. OFST is common for Luma and Chroma in YUV420 mode" line.long 0x50 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_CH_RD_OFST,Define Chroma stride between lines in the Input Frame in bytes and chroma circular buffer height. Used when CH_CHANCTRL_EN is enabled" hexmask.long.word 0x50 16.--29. 1. "MOD,Sets the circular buffer size if circular buffering mode is used. The circular buffer is sized in terms of number of chroma lines" newline hexmask.long.word 0x50 0.--15. 1. "OFST,Read frame line offset must be 16-byte aligned so internally [3:0] bits are hard-wired zero." line.long 0x54 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_VBUSMR_CFG,Control VBUSM Read Interface" hexmask.long.word 0x54 16.--27. 1. "BW_CTRL,Limits the mean bandwidth (computed over one block) that the LDC module can request for read from system memory. 0: The BW limiter is bypassed 1~4095: maximum number of bytes per 256 cycles. Examples: 1 : 1.17 MBytes/s @ 300 MHz 4095 :.." newline hexmask.long.byte 0x54 3.--7. 1. "TAG_CNT,Limits the maximum number of outstanding LDC requests to TAG_CNT+1" newline bitfld.long 0x54 1.--2. "MAX_BURSTLEN,Limits the maximum burst length that could be used by LDC. Each burst is of 16 bytes. HW also breaks the command at max burst size boundary. For K3 devices it is best to keep burst size of 8 which command size of 128 bytes. 0: 16 1: 8.." "0,1,2,3" line.long 0x58 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_COREOUT_CHANCFG,LDC Core to LSE output channel enable control" bitfld.long 0x58 3. "CH3_EN,Enable for LDC Core to LSE Channel_3 connection used for Chroma Dual output. Expected to be enabled in Y1_Y2Y3 Data mode" "0,1" newline bitfld.long 0x58 2. "CH2_EN,Enable for LDC Core to LSE Channel_2 connection used for Luma Dual output. Should be disabled in Y1_Y2Y3 Data mode" "0,1" newline bitfld.long 0x58 1. "RSRV_CH1,Primary Chroma channel (LSE Channel_1) enable extracted from output data mode" "0,1" newline bitfld.long 0x58 0. "RSRV_CH0,Primary Luuma channel (LSE Channel_0) enable extracted from output data mode" "0,1" line.long 0x5C "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_DUALOUT_CFG,Configuration for Dual Luma and Chroma channels and LUT" hexmask.long.byte 0x5C 21.--24. 1. "COUT_BITDPTH,Chroma Output Data Bit depth. Output clipped at 2^COUT_BITDPTH -1. Valid values 12-8" newline hexmask.long.byte 0x5C 17.--20. 1. "CIN_BITDPTH,Chroma Input Data Bit depth. Should same as YIN_BITDPTH. Valid values 12 to 8" newline bitfld.long 0x5C 16. "CLUT_EN,Chroma LUT mapping enable. If disabled data is sent as it is bypassing LUT mapping. Expected to be disabled in Y1_Y2Y3 Data mode" "0,1" newline hexmask.long.byte 0x5C 5.--8. 1. "YOUT_BITDPTH,Luma Output Data Bit depth. Output clipped at 2^YOUT_BITDPTH -1. Valid values 12-8" newline hexmask.long.byte 0x5C 1.--4. 1. "YIN_BITDPTH,Luma Input Data Bit depth. Valid values 12 to 8" newline bitfld.long 0x5C 0. "YLUT_EN,Luma LUT mapping enable. If disabled data is sent as it is bypassing LUT mapping" "0,1" line.long 0x60 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_IBUF_PIX_START,Expected to be used when Circular buffer is enabled. SW needs to make sure that all required pixel data is after this start pixel. Base address and Off Set needs to align with Pixel Start" hexmask.long.word 0x60 16.--28. 1. "STARTY,Vertical pixel start position. Must be Even and should be programmed as '0' when hybrid addressing mode is enabled" newline hexmask.long.word 0x60 0.--12. 1. "STARTX,Horizontal pixel start position. Must be align to 16-byte base address" line.long 0x64 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_HYBD_CBUFF_PARAM,Valid when HYBD_ADDREN is enabled. Frame data from Start to end line is stored in Circular buffer and rest of the data in stored in linear buffer(s)" hexmask.long.word 0x64 16.--28. 1. "STARTLINE,Start line of the frame which is stored in the circular buffer. Must be even" newline hexmask.long.word 0x64 0.--12. 1. "ENDLINE,End line of the frame which is stored in the circular buffer. Must be Odd" line.long 0x68 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_HYBD_CBUFF_BA_H,Higher 16-bit of circular buffer base address in hydrid addressing mode. Valid when HYBD_ADDREN is enabled." hexmask.long.word 0x68 0.--15. 1. "ADDR,Higher 16-bit of circular buffer base address in hydrid addressing mode" line.long 0x6C "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_HYBD_CBUFF_BA_L,Lower 32-bit of circular buffer base address in hydrid addressing mode. Valid when HYBD_ADDREN is enabled." hexmask.long 0x6C 0.--31. 1. "ADDR,Lower 32-bit of circular buffer base address in hydrid addressing mode. Must be 16-byte aligned so four LSB are coded to 0" line.long 0x70 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_HYBD_BUFF2_BA_H,Higher 16-bit of second linear buffer base address in hydrid addressing mode. Valid when HYBD_ADDREN is enabled." hexmask.long.word 0x70 0.--15. 1. "ADDR,Higher 16-bit of second linear buffer base address in hydrid addressing mode" line.long 0x74 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_HYBD_BUFF2_BA_L,Lower 32-bit of second linear buffer base address in hydrid addressing mode. Valid when HYBD_ADDREN is enabled." hexmask.long 0x74 0.--31. 1. "ADDR,Lower 32-bit of second linear buffer base address in hydrid addressing mode. Must be 16-byte aligned so four LSB are coded to 0" line.long 0x78 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_HYBD_CHCBUFF_PARAM,Valid when both CH_CHANCTRL_EN and HYBD_ADDREN are enabled. Frame data from Start to end line is stored in Circular buffer and rest of the data in stored in linear buffers. Program them assuming.." hexmask.long.word 0x78 16.--28. 1. "STARTLINE,Start line of the frame which is stored in the circular buffer. Must be even" newline hexmask.long.word 0x78 0.--12. 1. "ENDLINE,End line of the frame which is stored in the circular buffer. Must be odd" line.long 0x7C "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_HYBD_CHCBUFF_BA_H,Higher 16-bit of chroma circular buffer base address in hydrid addressing mode. Valid when HYBD_ADDREN is enabled." hexmask.long.word 0x7C 0.--15. 1. "ADDR,Higher 16-bit of circular buffer base address in hydrid addressing mode" line.long 0x80 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_HYBD_CHCBUFF_BA_L,Lower 32-bit of chroma circular buffer base address in hydrid addressing mode. Valid when HYBD_ADDREN is enabled." hexmask.long 0x80 0.--31. 1. "ADDR,Lower 32-bit of circular buffer base address in hydrid addressing mode. Must be 16-byte aligned so four LSB are coded to 0" line.long 0x84 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_HYBD_CHBUFF2_BA_H,Higher 16-bit of second linear chroma buffer base address in hydrid addressing mode. Valid when HYBD_ADDREN is enabled." hexmask.long.word 0x84 0.--15. 1. "ADDR,Higher 16-bit of second linear buffer base address in hydrid addressing mode" line.long 0x88 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_HYBD_CHBUFF2_BA_L,Lower 32-bit of second linear chroma buffer base address in hydrid addressing mode. Valid when HYBD_ADDREN is enabled." hexmask.long 0x88 0.--31. 1. "ADDR,Lower 32-bit of second linear buffer base address in hydrid addressing mode. Must be 16-byte aligned so four LSB are coded to 0" rgroup.long 0xE0++0xF line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_REGN_W12_SZ,Horizontal slice width for Region division" hexmask.long.word 0x0 16.--29. 1. "W2,Width of second horizontal slice. (Minimum of 8 and must be even)" newline hexmask.long.word 0x0 0.--13. 1. "W1,Width of first horizontal slice. (Minimum of 8 and must be even)" line.long 0x4 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_REGN_W3_SZ,Horizontal slice width for Region division" hexmask.long.word 0x4 0.--13. 1. "W3,Width of third horizontal slice. (Minimum of 8 and must be even)" line.long 0x8 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_REGN_H12_SZ,vertical slice height for Region division" hexmask.long.word 0x8 16.--29. 1. "H2,Height of second vertical slice. (must be even)" newline hexmask.long.word 0x8 0.--13. 1. "H1,Height of first vertical slice. (must be even)" line.long 0xC "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_REGN_H3_SZ,Vertical slice height for Region division" hexmask.long.word 0xC 0.--13. 1. "H3,Height of third vertical slice. (must be even)" rgroup.long 0x200++0x7 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_ERR_STATUS,Control VBUSM Read Interface" bitfld.long 0x0 8.--10. "VBUSMR_ERR,VBUSM Read I/F Last Error Status. Write '1' to clear works independently for each bit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5. "INT_SZOVF,Internal operation has overflown the HW supported block or frame sizes. Should be fixed" "0,1" newline bitfld.long 0x0 4. "M_IBLK_MEMOVF,Mesh block storage requirement is more than internal memory available. Should be fixed" "0,1" newline bitfld.long 0x0 3. "P_IBLK_MEMOVF,Input pixel block storage requirement is more than internal memory available. Should be fixed" "0,1" newline bitfld.long 0x0 2. "IFRAME_OUTB,Either Mesh data or Input pixel data required is going out of valid frame available" "0,1" newline bitfld.long 0x0 1. "M_IBLK_OUTB,Mesh Input Block out of Bound. Mesh data required for block is not available in the prefetched internal memory. Should be fine." "0,1" newline bitfld.long 0x0 0. "P_IBLK_OUTB,Pixel Input Block out of Bound. Pixel data required for block is not available in the prefetched internal memory. PIX_PAD is not enough" "0,1" line.long 0x4 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_DEBUG_CTRL,Control the memory access selection" bitfld.long 0x4 0. "CFG_MEMACC_SEL,VBUSP Configuration access control. 0 - VBUSP can access Ping memories 1 - VBUSP can access pong memories All private memories Mesh Luma Chroma will share same.." "0: VBUSP can access Ping memories 1,?" rgroup.long 0x208++0x17 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_DEBUG_STATUS,LDC Debug Status Register" bitfld.long 0x0 24. "PROC_STATUS,Block Processing status. 0 - Block Processing is ongoing 1 - Either block processing is completed or not started" "0: Block Processing is ongoing 1,?" newline bitfld.long 0x0 16.--18. "FETCH_RESPSTATE,VBUSM Fetch Response state machine 3'd0 = ST_RESP_IDLE.." "0: ST_RESP_IDLE 3'd1 = ST_RESP_MREQWAIT 3'd2 =..,?,?,?,?,?,?,?" newline hexmask.long.byte 0x0 8.--12. 1. "FETCH_REQSTATE,VBUSM Fetch Request state machine 5'b00_000 = ST_REQ_IDLE.." newline hexmask.long.byte 0x0 0.--3. 1. "CTRL_STATE,Main Control State machine 4'd0 = STATE_IDLE.." line.long 0x4 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_FR_PDFTCH,Pixel bytes fetched by VBUSM Read Interface. It is updated on every command issued and cleared at the beginning frame fetch. Reading at the end of the frame will provide total number of pixel data.." hexmask.long 0x4 0.--31. 1. "PBYTES,Pixel bytes fetched for current Frame. Reading at the end of frame will provide pixel data fetched for entire frame" line.long 0x8 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_FR_MDFTCH,Mesh bytes fetched by VBUSM Read Interface. It is updated on every command issued and cleared at the beginning frame fetch. Reading at the end of the frame will provide total number of mesh data band.." hexmask.long 0x8 0.--31. 1. "MBYTES,Mesh bytes fetched for current Frame. Reading at the end of frame will provide Mesh data fetched for entire frame" line.long 0xC "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_PIXMEMOVF_BLK,Starting co-ordinates of first output block for which input pixel buffer overflowed" hexmask.long.word 0xC 16.--28. 1. "Y,Start Y Co-ordinate" newline hexmask.long.word 0xC 0.--12. 1. "X,Start X Co-ordinate" line.long 0x10 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_MESHMEMOVF_BLK,Starting co-ordinates of first output block for which input mesh buffer overflowed" hexmask.long.word 0x10 16.--28. 1. "Y,Start Y Co-ordinate" newline hexmask.long.word 0x10 0.--12. 1. "X,Start X Co-ordinate" line.long 0x14 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_OUTOFBOUND_BLK,Starting co-ordinates of first output block for which PIX_PAD is not enough" hexmask.long.word 0x14 16.--28. 1. "Y,Start Y Co-ordinate" newline hexmask.long.word 0x14 0.--12. 1. "X,Start X Co-ordinate" rgroup.long 0x100++0x7 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_CTRL,Region Control Register" bitfld.long 0x0 0. "ENABLE,Enable for processing of this region. This is can be used to selectively disable processing of some regions (default enabled). 1 - Process the region i.e. no skipping 0 - Don't process the region" "0: Don't process the region,1: Process the region i" line.long 0x4 "PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_OUT_BLKSZ,Block size and Pixel Pad config" hexmask.long.byte 0x4 16.--19. 1. "PIXPAD,Pixel pad" newline hexmask.long.byte 0x4 8.--15. 1. "OBH,Output block height must be >0 and even. Should be less than or equal to corresponding region height" newline hexmask.long.byte 0x4 0.--7. 1. "OBW,Output block width must be >0 and multiple of 8. Should be less than or equal to corresponding region width" tree.end tree "VPAC0_PAR_VPAC_LDC0_S_VBUSP_PIXWRINTF_DUALC_LUTCFG_DUALC_LUT (VPAC0_PAR_VPAC_LDC0_S_VBUSP_PIXWRINTF_DUALC_LUTCFG_DUALC_LUT)" base ad:0x3821000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__PIXWRINTF__DUALC_LUTCFG__DUALC_LUT_LUT,dualc width conversion LUT" hexmask.long.word 0x0 16.--27. 1. "LUT_1,Bank-1" hexmask.long.word 0x0 0.--11. 1. "LUT_0,Bank-0" tree.end tree "VPAC0_PAR_VPAC_LDC0_S_VBUSP_PIXWRINTF_DUALY_LUTCFG_DUALY_LUT (VPAC0_PAR_VPAC_LDC0_S_VBUSP_PIXWRINTF_DUALY_LUTCFG_DUALY_LUT)" base ad:0x3820800 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__PIXWRINTF__DUALY_LUTCFG__DUALY_LUT_LUT,dualy width conversion LUT" hexmask.long.word 0x0 16.--27. 1. "LUT_1,Bank-1" hexmask.long.word 0x0 0.--11. 1. "LUT_0,Bank-0" tree.end tree "VPAC0_PAR_VPAC_LDC0_S_VBUSP_VPAC_LDC_LSE_CFG_VP (VPAC0_PAR_VPAC_LDC0_S_VBUSP_VPAC_LDC_LSE_CFG_VP)" base ad:0x3820400 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_status_param,The STATUS_PARAM register returns the LSE compile configuration parameters." bitfld.long 0x0 30.--31. "BYPASS_CH,Number of available input channel selection for loopback mode" "0,1,2,3" newline bitfld.long 0x0 29. "OUT_SKIP_EN,Output Auto-Skip Enable" "0,1" newline bitfld.long 0x0 28. "CORE_OUT_2D,1D or 2D output addressing mode(2D if 1)" "0,1" newline hexmask.long.byte 0x0 23.--27. 1. "CORE_OUT_DW,Core Output Channel Data Width" newline bitfld.long 0x0 22. "LINE_SKIP_EN,Source Line Inc by 2 Supported (if 1)" "0,1" newline bitfld.long 0x0 21. "BIT_AOFFSET,Source nibble offset address Supported (if 1)" "0,1" newline bitfld.long 0x0 20. "HV_INSERT,H/VBLANK Insertion Supported (if 1)" "0,1" newline bitfld.long 0x0 17.--19. "PIX_MX_HT,Core_Input Pixel Matrix Height" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 12.--16. 1. "CORE_DW,Core Input Data Bus Width" newline bitfld.long 0x0 10.--11. "SL2_OUT_H3A_CH,Number of SL2 H3A Output Channels" "0,1,2,3" newline hexmask.long.byte 0x0 6.--9. 1. "SL2_OUT_CH,Number of SL2 Output Channels" newline bitfld.long 0x0 3.--5. "SL2_IN_CH_THR,Number of Input Channels per thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "VPORT_THR,Number of VPORT input enabled" "0,1" newline bitfld.long 0x0 0.--1. "NTHR,Number of threads supported" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_status_error,The STATUS_ERROR register returns the LSE error status." hexmask.long.byte 0x0 8.--14. 1. "VM_WR_ERR,VBUSM I/F Last Write Error Status [14:11] Write Channel Number [10:8] VBUSM write error status" rgroup.long 0x8++0x3 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_status_idle_mode,The STATUS_IDLE_MODE register returns IDLE status of LSE VBUSM port and in/output channels - 0: IDLE 1: ACTIVE" hexmask.long.byte 0x0 12.--15. 1. "LSE_OUT_CHAN,Output Channel[3:0] Status" newline bitfld.long 0x0 1. "VM_WR_PORT,SL2 vbusm I/F Write Port Status" "0,1" rgroup.long 0xC++0x3 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_cfg_lse,The CFG_LSE register configures the LSE general hardware modes." bitfld.long 0x0 8. "PSA_EN,Test mode Output Channel Signature Generation Enable 0: Disable (default) 1: Enable When enabled LSE generates a unique CRC signature for each output channel's frame data at frame completion." "0: Disable,1: Enable When enabled" newline bitfld.long 0x0 4. "VM_ARB_FIXED_MODE,VBUSM Arbitration Fixed Mode select 0: Round-Robin Arbitration (default) 1: Fixed-mode Arbitration" "0: Round-Robin Arbitration,1: Fixed-mode Arbitration" rgroup.long 0x13C++0x3 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_dst_common_cfg,The DST_COMMON_CFG register captures common configuration for the output channels" hexmask.long.byte 0x0 0.--5. 1. "ROUNDING_OFFSET,output channel rounding offset value. Default value to be considered 6'h08" rgroup.long 0x140++0x3 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_psa_signature,The PSA_SIGNATURE register returns the captured PSA signature value of the last frame data of output channel [a]." hexmask.long 0x0 0.--31. 1. "VALUE,32-bit CRC signature value" rgroup.long 0x1E0++0x3 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_dbg,The DBG register returns the current status of internal FSM - TI internal use only." hexmask.long 0x0 0.--31. 1. "STATUS,Debug status" rgroup.long 0x50++0xF line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_buf_cfg,The DST_BUF_CFG register configures the output buffer channel ." rbitfld.long 0x0 31. "CH_DISABLED,Channel Disable Status (read-only) 0: (Default) Chanel is enabled for Y UV or YUV422 data transfer to SL2 memory. All configurations associated with this DST_BUF[a] are valid. 1: Channel is disabled for SL2 data transfer (because the.." "?,1: Channel is disabled for SL2 data transfer" newline bitfld.long 0x0 29. "YUV422_INTLV_ORDER,YUV422 Interleaving Order Selection 0: UYVY 1: YUYV Only Applicable if this output channel is YUV422 output capable LUMA channel. Otherwise setting has no effect." "0: UYVY 1: YUYV Only Applicable if this output..,?" newline bitfld.long 0x0 28. "YUV422_OUT_EN,YUV422 Interleaved Output Merge Enable 0: Disable 1: Enable When enabled this channel interleaves data from the associated chroma data output channel to output YUV422 interleaved data to the SL2 memory. Only Applicable if this output.." "0: Disable,1: Enable When enabled" newline bitfld.long 0x0 10. "ENABLE_SIGNED_ACCLERATOR_DATA,Specify the acclerator data to be signed or unsigned 0: Unsigned data (By default) 1: Signed Data" "0: Unsigned data,1: Signed Data" newline bitfld.long 0x0 9. "ENABLE_OUTPUT_PIXEL_ROUNDING,enable acclerator pixel output rounding 0: Disable rounding logic 1: Enable rounding logic" "0: Disable rounding logic 1: Enable rounding logic,?" newline bitfld.long 0x0 4. "PIX_FMT_ALIGN,Output Pixel Container Alignment 0: LSB-aligned 1: MSB-aligned" "0: LSB-aligned,1: MSB-aligned" newline bitfld.long 0x0 2.--3. "PIX_FMT_CNTRSZ,Output Pixel Container Size Sel 0: 8-bit 1: 12-bit 2: 16-bit 3: reserved Output pixel container size must be same or larger than output pixel width. If yuv422_out_en is set pix_fmt_cntrsz must be 0." "?,?,?,3: reserved Output pixel container size must be.." newline bitfld.long 0x0 0.--1. "PIX_FMT_PW,Output Pixel Width Sel 0: 8-bit 1: 12-bit 2: reserved 3: 16-bit The width defines the bit-depth of the pixel data to be stored in the pixel container." "?,?,2: reserved,?" line.long 0x4 "PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_buf_attr0,The DST_BUF_ATTR0 register configures the attributes of the output SL2 buffer ." hexmask.long.word 0x4 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)" newline hexmask.long.word 0x4 6.--15. 1. "BUF_STRIDE,Buffer Stride Size [15:6] (64 byte multiple) stride size" newline hexmask.long.byte 0x4 0.--5. 1. "BUF_STRIDE_6_LSB,Buffer Stride Size [5:0] - 6 LSB bits of buffer stride size should always be 0. Writes have no effect. Always read as 0" line.long 0x8 "PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_buf_attr1,The DST_BUF_ATTR1 register configures the 2D Block attributes of the output SL2 buffer ." hexmask.long.word 0x8 16.--25. 1. "CBUF_BPR_CHAN,Circular Buffer - 2D blocks per row defined by cbuf_stride (selected when bpr_sel_mode=0)" newline bitfld.long 0x8 2. "TDONE_GEN_MODE,HTS Tdone Generation Mode for 2D transfer 0: Generate Tdone on every 2D block completion 1: Generate Tdone only at the end of CBUF_BPR Must be common across all DST channels and Must be set to 0 when BPR settings for enabled output.." "0: Generate Tdone on every 2D block completion,1: Generate Tdone only at the end of CBUF_BPR Must.." newline bitfld.long 0x8 1. "BPR_SEL_MODE,CBUF BPR Selection mode 0: Use cbuf_bpr_chan (applied to all regions) for this output channel 1: Use the common multi-region BPR parameters" "0: Use cbuf_bpr_chan,1: Use the common multi-region BPR parameters" newline bitfld.long 0x8 0. "CBUF_VWRAP_EN,CBUF Vertical Wrap Enable 0: Disable (for Memory to Memory data transfer mode) 1: Enable (for In-Line Rasterization Mode)" "0: Disable,1: Enable" line.long 0xC "PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_buf_ba,The DST_BUF_BA register configures the base address of the output SL2 circular buffer ." bitfld.long 0xC 31. "ENABLE,Output Channel Enable 0: Disable 1: Enable" "0: Disable,1: Enable" newline hexmask.long.tbyte 0xC 6.--23. 1. "ADDR,Base Address[23:6] - (64 Byte aligned) byte address" newline hexmask.long.byte 0xC 0.--5. 1. "ADDR_6_LSB,Base Address[5:0] - 6 LSB bits of address should always be 0. Writes have no effect. Always read as 0" rgroup.long 0x100++0x3 line.long 0x0 "PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_row,The COMMON_CFG_ROW registers configure the common CBUF_BPR values for regions of all output channels." hexmask.long.word 0x0 20.--29. 1. "BPR0,Region [a 0] CBUF_BPR value" newline hexmask.long.word 0x0 10.--19. 1. "BPR1,Region [a 1] CBUF_BPR value" newline hexmask.long.word 0x0 0.--9. 1. "BPR2,Region [a 2] CBUF_BPR value" tree.end tree.end tree "VPAC0_PAR_VPAC_MSC" tree "VPAC0_PAR_VPAC_MSC_CFG_VP_CFG_VP (VPAC0_PAR_VPAC_MSC_CFG_VP_CFG_VP)" base ad:0x38C0000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_MSC__CFG_VP__CFG__VP__REGS_revision,The REVISION Register contains the major and minor revisions for the VPAC MSC HWA module." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and new scheme. Spare bit to encode future schemes" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU indicator DSPS ==> 0x0 WTBU ==> 0x1 Processors ==> 0x2" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family. If there is no level of software compatibility a new FUNC number and hence PID should be assigned." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version. R as described in PDR with additional clarifications and definitions below. Must be easily ECO-able or controlled during fabrication. Ideally through a top level metal mask or e-fuse. This number is maintained/owned by IP design.." newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision. X as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. X is part of IP numbering X.Y.R.Z. X changes ONLY when: (1) There is a major feature addition." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library (CSL) / Drivers. 0 if non-c ustom." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision. Y as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owne r. Y changes ONLY when: (1) Features are scaled (up or down). Flexibility exists in that this.." rgroup.long 0x4++0x3 line.long 0x0 "PAR_VPAC_MSC__CFG_VP__CFG__VP__REGS_control,The CONTROL Register allows the CPU to control various aspects of the module." bitfld.long 0x0 0. "MSC_ENABLE,MSC Core Enable: Enables the MSC HWA. (Must be enabled even when MSC is strictly in the loopback-only mode. Individual resizing filter is enabled only when the output buffer associated with the filter is enabled in the LSE configuration.) 0:.." "0: Disable,1: Enable" rgroup.long 0x10++0x13 line.long 0x0 "PAR_VPAC_MSC__CFG_VP__CFG__VP__REGS_cfg,The FILT[a]_CFG register configures the modes of FILTER channel [a]." bitfld.long 0x0 22. "SIGNED_DATA,Integer type of input and output frame data: 0 : Unsigned 12-bit (default) 1 : Signed 12-bit" "0: Unsigned 12-bit,1: Signed 12-bit" newline hexmask.long.byte 0x0 18.--21. 1. "COEF_SHIFT,Coef Shift Size: configures the precision of the 10-bit signed filter coefficients (valid Shift range: 5~9) : 5: Shift by 5 (5-bit fraction) 6: Shift by 6 (6-bit fraction) 7: Shift by 7 (7-bit fraction) 8: Shift by 8 (8-bit.." newline bitfld.long 0x0 17. "UV_MODE,Source data interleave format: 0 - non-interleaved (Y data) 1 - interleaved (UV data)" "0: non-interleaved,1: interleaved" newline bitfld.long 0x0 16. "SAT_MODE,Filter Output Saturation Mode 0 - [0..4095] clipping 1 - [-2048.. 2047] clip followed by +2048 This is used only when signed_data=0 (unsigned data type)." "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "SP_VS_COEF_SEL,Single Phase Vertical Filter Coef Selection (sp_vs_coef_src = 0) 0000 : Use Dedicated SP coef-0 0001 : Use Dedicated SP coef-1 (sp_hs_coef_src = 1) N : Use (N+16)th entry of 5-tap/32-phase filter coef set 0 (N = 0..15)" newline bitfld.long 0x0 11. "SP_VS_COEF_SRC,Single Phase Vertical Filter Coef Source Selection 0 : Use one of two dedicated single phase coeffs 1 : Use the custom single phase coeff table (5-tap/32-phase Filter coef set 0) If set to 1 5-tap/32-phase filter coef set-0 is to.." "0: Use one of two dedicated single phase coeffs,1: Use the custom single phase coeff table" newline hexmask.long.byte 0x0 7.--10. 1. "SP_HS_COEF_SEL,Single Phase Horizontal Filter Coef Selection (sp_hs_coef_src = 0) 0000 : Use Dedicated SP coef-0 0001 : Use Dedicated SP coef-1 (sp_hs_coef_src = 1) N : Use Nth entry of 5-tap/32-phase filter coef set 0 (N = 0..15)" newline bitfld.long 0x0 6. "SP_HS_COEF_SRC,Single Phase Horizontal Filter Coef Source Selection 0 : Use one of two dedicated single phase coeffs 1 : Use the custom single phase coeff table (5-tap/32-phase Filter coef set 0) If set to 1 5-tap/32-phase filter coef set-0 is.." "0: Use one of two dedicated single phase coeffs,1: Use the custom single phase coeff table" newline bitfld.long 0x0 4.--5. "VS_COEF_SEL,Multi-phase Vertical Coef Selection (Phase_mode=0) 00 : 5-tap/32-phase Filter coef sets 0 & 1 10 : 5-tap/32-phase Filter Coef sets 2 & 3 (Phase_mode=1) 00 : 5-tap/32-phase Filter coef set 0 01 : 5-tap/32-phase Filter coef set 1.." "0,1,2,3" newline bitfld.long 0x0 2.--3. "HS_COEF_SEL,Multi-phase Horizontal Coef Selection (Phase_mode=0) 00 : 5-tap/32-phase Filter coef sets 0 & 1 10 : 5-tap/32-phase Filter Coef sets 2 & 3 (Phase_mode=1) 00 : 5-tap/32-phase Filter coef set 0 01 : 5-tap/32-phase Filter coef set 1.." "0,1,2,3" newline bitfld.long 0x0 1. "PHASE_MODE,Filter Phase mode selection 0 - 64 phases 1 - 32 phases" "0,1" newline bitfld.long 0x0 0. "FILTER_MODE,Filter Mode 0 : Single Phase Filter (e.g. Gaussian Filter for Pyramid generation) 1: Multi-phase Scaling Filter" "0: Single Phase Filter,1: Multi-phase Scaling Filter" line.long 0x4 "PAR_VPAC_MSC__CFG_VP__CFG__VP__REGS_src_roi,The FILT[a]_SRC_ROI register configures the input ROI position within the input super frame for FILTER channel [a]. Set to 0 if ROI is full-size." hexmask.long.word 0x4 16.--28. 1. "Y_OFFSET,Source Y offset" newline hexmask.long.word 0x4 0.--12. 1. "X_OFFSET,Source X offset (Must be an even # when FILT_CFG.uv_mode=1)" line.long 0x8 "PAR_VPAC_MSC__CFG_VP__CFG__VP__REGS_out_size,The FILT[a]_OUT_SIZE configures the output size for FILTER channel [a]." hexmask.long.word 0x8 16.--28. 1. "HEIGHT,Output Height" newline hexmask.long.word 0x8 0.--12. 1. "WIDTH,Output Width" line.long 0xC "PAR_VPAC_MSC__CFG_VP__CFG__VP__REGS_firinc,The FILT[a]_FIRINC register configures the FIRINC attributes of FILTER channel [a]." hexmask.long.word 0xC 16.--30. 1. "VS,FIRINC of VS filter" newline hexmask.long.word 0xC 0.--14. 1. "HS,FIRINC of HS filter" line.long 0x10 "PAR_VPAC_MSC__CFG_VP__CFG__VP__REGS_acc_init,The FILT[a]_ACC_INIT register configures the FIRINC attributes of FILTER channel [a]." hexmask.long.word 0x10 16.--27. 1. "VS,ACC_INIT of VS filter" newline hexmask.long.word 0x10 0.--11. 1. "HS,ACC_INIT of HS filter" rgroup.long 0x180++0x7 line.long 0x0 "PAR_VPAC_MSC__CFG_VP__CFG__VP__REGS_c210,Single Phase Coef Set[a] coefficients C2/C1/C0" hexmask.long.word 0x0 20.--29. 1. "FIR_C2,Signed coefficient C2" newline hexmask.long.word 0x0 10.--19. 1. "FIR_C1,Signed coefficient C1" newline hexmask.long.word 0x0 0.--9. 1. "FIR_C0,Signed coefficient C0" line.long 0x4 "PAR_VPAC_MSC__CFG_VP__CFG__VP__REGS_c43,Single Phase Coef Set[a] coefficients C4/C3" hexmask.long.word 0x4 10.--19. 1. "FIR_C4,Signed coefficient C4" newline hexmask.long.word 0x4 0.--9. 1. "FIR_C3,Signed coefficient C3" rgroup.long 0x200++0x7 line.long 0x0 "PAR_VPAC_MSC__CFG_VP__CFG__VP__REGS_c210,Multi Phase Coef Set[a] Phase[b] coefficients C2/C1/C0" hexmask.long.word 0x0 20.--29. 1. "FIR_C2,Signed coefficient C2" newline hexmask.long.word 0x0 10.--19. 1. "FIR_C1,Signed coefficient C1" newline hexmask.long.word 0x0 0.--9. 1. "FIR_C0,Signed coefficient C0" line.long 0x4 "PAR_VPAC_MSC__CFG_VP__CFG__VP__REGS_c43,Multi Phase Coef Set[a] Phase[b] coefficients C4/C3" hexmask.long.word 0x4 10.--19. 1. "FIR_C4,Signed coefficient C4" newline hexmask.long.word 0x4 0.--9. 1. "FIR_C3,Signed coefficient C3" tree.end tree "VPAC0_PAR_VPAC_MSC_CFG_VP_LSE_CFG_VP (VPAC0_PAR_VPAC_MSC_CFG_VP_LSE_CFG_VP)" base ad:0x38C0800 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_status_param,The STATUS_PARAM register returns the LSE compile configuration parameters." bitfld.long 0x0 30.--31. "BYPASS_CH,Number of available input channel selection for loopback mode" "0,1,2,3" newline bitfld.long 0x0 29. "OUT_SKIP_EN,Output Auto-Skip Enable" "0,1" newline bitfld.long 0x0 28. "CORE_OUT_2D,1D or 2D output addressing mode(2D if 1)" "0,1" newline hexmask.long.byte 0x0 23.--27. 1. "CORE_OUT_DW,Core Output Channel Data Width" newline bitfld.long 0x0 22. "LINE_SKIP_EN,Source Line Inc by 2 Supported (if 1)" "0,1" newline bitfld.long 0x0 21. "BIT_AOFFSET,Source nibble offset address Supported (if 1)" "0,1" newline bitfld.long 0x0 20. "HV_INSERT,H/VBLANK Insertion Supported (if 1)" "0,1" newline bitfld.long 0x0 17.--19. "PIX_MX_HT,Core_Input Pixel Matrix Height" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 12.--16. 1. "CORE_DW,Core Input Data Bus Width" newline bitfld.long 0x0 10.--11. "SL2_OUT_H3A_CH,Number of SL2 H3A Output Channels" "0,1,2,3" newline hexmask.long.byte 0x0 6.--9. 1. "SL2_OUT_CH,Number of SL2 Output Channels" newline bitfld.long 0x0 3.--5. "SL2_IN_CH_THR,Number of Input Channels per thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "VPORT_THR,Number of VPORT input enabled" "0,1" newline bitfld.long 0x0 0.--1. "NTHR,Number of threads supported" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_status_error,The STATUS_ERROR register returns the LSE error status." hexmask.long.byte 0x0 8.--14. 1. "VM_WR_ERR,VBUSM I/F Last Write Error Status [14:11] Write Channel Number [10:8] VBUSM write error status" newline hexmask.long.byte 0x0 0.--4. 1. "VM_RD_ERR,VBUSM I/F Last Read Error Status [4:3] Read Channel Number [2:0] VBUSM read error status" rgroup.long 0x8++0x3 line.long 0x0 "PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_status_idle_mode,The STATUS_IDLE_MODE register returns IDLE status of LSE VBUSM port and in/output channels - 0: IDLE 1: ACTIVE" hexmask.long.word 0x0 12.--21. 1. "LSE_OUT_CHAN,Output Channel[9:0] Status" newline hexmask.long.byte 0x0 4.--7. 1. "LSE_IN_CHAN,Input Channel[3:0] Status" newline bitfld.long 0x0 1. "VM_WR_PORT,SL2 vbusm I/F Write Port Status" "0,1" newline bitfld.long 0x0 0. "VM_RD_PORT,SL2 vbusm I/F Read Port Status" "0,1" rgroup.long 0xC++0x3 line.long 0x0 "PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_cfg_lse,The CFG_LSE register configures the LSE general hardware modes." bitfld.long 0x0 8. "PSA_EN,Test mode Output Channel Signature Generation Enable 0: Disable (default) 1: Enable When enabled LSE generates a unique CRC signature for each output channel's frame data at frame completion." "0: Disable,1: Enable When enabled" newline bitfld.long 0x0 4. "VM_ARB_FIXED_MODE,VBUSM Arbitration Fixed Mode select 0: Round-Robin Arbitration (default) 1: Fixed-mode Arbitration" "0: Round-Robin Arbitration,1: Fixed-mode Arbitration" newline bitfld.long 0x0 1. "LOOPBACK_CORE_EN,Functional path (data to HWA core) enable during loopback mode 0: Disable 1: Enable When enabled the loopback-enabled input channel is used also for CORE data input. Otherwise it is strictly used for the loopback path." "0: Disable,1: Enable When enabled" newline bitfld.long 0x0 0. "LOOPBACK_EN,LSE loopback mode enable 0: Disable 1: Enable When enabled the second thread's input channel data (middle tap data) is looped back out to the last (#9) output channel." "0: Disable,1: Enable When enabled" rgroup.long 0x13C++0x3 line.long 0x0 "PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_dst_common_cfg,The DST_COMMON_CFG register captures common configuration for the output channels" hexmask.long.byte 0x0 0.--5. 1. "ROUNDING_OFFSET,output channel rounding offset value. Default value to be considered 6'h08" rgroup.long 0x140++0x3 line.long 0x0 "PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_psa_signature,The PSA_SIGNATURE register returns the captured PSA signature value of the last frame data of output channel [a]." hexmask.long 0x0 0.--31. 1. "VALUE,32-bit CRC signature value" rgroup.long 0x170++0x7 line.long 0x0 "PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_src0_cfg1,The src0_cfg1 register configures the input channels for the processing thread [a]" bitfld.long 0x0 6. "SKIP_SL2_READS,When set skips SL2 reads from the channel and channel0 read_data is redirected to the current channel" "0,1" newline bitfld.long 0x0 5. "ENABLE_CHAN_SPECIFIC_PARAMS,Enables channel specific SRC_CFG and FRAME_SIZE parameters. 0 : Current channel config parameters are derived from chan0 MMR's. 1 : Current channel config parameters are derived from channel specific MMR's" "0: Current channel config parameters are derived..,1: Current channel config parameters are derived.." newline bitfld.long 0x0 4. "PIX_FMT_ALIGN,Input Pixel Container Alignment 0: LSB-aligned 1: MSB-aligned" "0: LSB-aligned,1: MSB-aligned" newline bitfld.long 0x0 2.--3. "PIX_FMT_CNTRSZ,Input Pixel Container Size Sel 0: 8-bit 1: 12-bit 2: 16-bit 3: reserved Input pixel container size must be same or larger than input pixel width." "?,?,?,3: reserved Input pixel container size must be same.." newline bitfld.long 0x0 0.--1. "PIX_FMT_PW,Input Pixel Width Sel 0: 8-bit 1: 12-bit 2: 14-bit 3: 16-bit The width defines the bit-depth of the pixel data to be extracted from the pixel container." "0,1,2,3" line.long 0x4 "PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_src0_frame_size1,The src0_frame_size1 register configures the frame size of all input buffers for the processing thread [a]." hexmask.long.word 0x4 0.--12. 1. "WIDTH,SL2 - Source Buffer Width (number of pixels)" rgroup.long 0x190++0x7 line.long 0x0 "PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_src1_cfg1,The src1_cfg1 register configures the input channels for the processing thread [a]" bitfld.long 0x0 6. "SKIP_SL2_READS,When set skips SL2 reads from the channel and channel0 read_data is redirected to the current channel" "0,1" newline bitfld.long 0x0 5. "ENABLE_CHAN_SPECIFIC_PARAMS,Enables channel specific SRC_CFG and FRAME_SIZE parameters. 0 : Current channel config parameters are derived from chan0 MMR's. 1 : Current channel config parameters are derived from channel specific MMR's" "0: Current channel config parameters are derived..,1: Current channel config parameters are derived.." newline bitfld.long 0x0 4. "PIX_FMT_ALIGN,Input Pixel Container Alignment 0: LSB-aligned 1: MSB-aligned" "0: LSB-aligned,1: MSB-aligned" newline bitfld.long 0x0 2.--3. "PIX_FMT_CNTRSZ,Input Pixel Container Size Sel 0: 8-bit 1: 12-bit 2: 16-bit 3: reserved Input pixel container size must be same or larger than input pixel width." "?,?,?,3: reserved Input pixel container size must be same.." newline bitfld.long 0x0 0.--1. "PIX_FMT_PW,Input Pixel Width Sel 0: 8-bit 1: 12-bit 2: 14-bit 3: 16-bit The width defines the bit-depth of the pixel data to be extracted from the pixel container." "0,1,2,3" line.long 0x4 "PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_src1_frame_size1,The src1_frame_size1 register configures the frame size of all input buffers for the processing thread [a]." hexmask.long.word 0x4 0.--12. 1. "WIDTH,SL2 - Source Buffer Width (number of pixels)" rgroup.long 0x1E0++0x3 line.long 0x0 "PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_dbg,The DBG register returns the current status of internal FSM - TI internal use only." hexmask.long 0x0 0.--31. 1. "STATUS,Debug status" rgroup.long 0x10++0x3 line.long 0x0 "PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_cfg,The SRC[a]_CFG register configures the input channels for the processing thread [a]" bitfld.long 0x0 19.--21. "KERN_TPAD_SZ,Input kernel top padding lines valid=0..2 for msc" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "KERN_BPAD_SZ,Input kernel bottom padding lines valid=0..2 for msc" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 12.--15. 1. "KERN_LN_OFFSET,Input kernel starting line position valid=0..4 for msc" newline hexmask.long.byte 0x0 8.--11. 1. "KERN_SZ_HEIGHT,Actual number of input kernel lines (height) valid=1..5 for msc" newline bitfld.long 0x0 7. "SRC_LN_INC_2,Source Line address Increment by 2 enable 0: Disable 1: Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 4. "PIX_FMT_ALIGN,Input Pixel Container Alignment 0: LSB-aligned 1: MSB-aligned" "0: LSB-aligned,1: MSB-aligned" newline bitfld.long 0x0 2.--3. "PIX_FMT_CNTRSZ,Input Pixel Container Size Sel 0: 8-bit 1: 12-bit 2: 16-bit 3: reserved Input pixel container size must be same or larger than input pixel width." "?,?,?,3: reserved Input pixel container size must be same.." newline bitfld.long 0x0 0.--1. "PIX_FMT_PW,Input Pixel Width Sel 0: 8-bit 1: 12-bit 2: 14-bit 3: 16-bit The width defines the bit-depth of the pixel data to be extracted from the pixel container." "0,1,2,3" rgroup.long 0x18++0xB line.long 0x0 "PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_frame_size,The SRC[a]_FRAME_SIZE register configures the frame size of all input buffers for the processing thread [a]." hexmask.long.word 0x0 16.--28. 1. "HEIGHT,SL2 - Source Buffer Height (number of lines)" newline hexmask.long.word 0x0 0.--12. 1. "WIDTH,SL2 - Source Buffer Width (number of pixels)" line.long 0x4 "PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_buf_attr,The SRC[a]_BUF_ATTR register configures the common attributes of all SL2 source buffers for the processing thread [a]." hexmask.long.byte 0x4 25.--31. 1. "START_NIB_OFFSET,Buffer Line start offset within the first SL2 data word - in half-byte (nibble) resolution" newline hexmask.long.word 0x4 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)" newline hexmask.long.word 0x4 6.--15. 1. "BUF_STRIDE,Buffer Stride Size [15:6] (64 byte multiple) stride size" newline hexmask.long.byte 0x4 0.--5. 1. "BUF_STRIDE_6_LSB,Buffer Stride Size [5:0] - 6 LSB bits of buffer stride size should always be 0. Writes have no effect. Always read as 0" line.long 0x8 "PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_buf_ba,The SRC[a]_BUF_BA[b] register configures the base address of the SL2 source buffer [b] for the processing thread [a]." bitfld.long 0x8 31. "ENABLE,Input Buffer Enable 0: Disable 1: Enable When the processing thread is enabled at least one of the input buffer must be enabled" "0: Disable,1: Enable When the processing thread is enabled" newline bitfld.long 0x8 30. "SKIP_ODD_LINE_PROC,This bit when set skips odd line processing" "0,1" newline bitfld.long 0x8 29. "SKIP_ALTERNATE_LINE_PROC,This bit when enabled skips processing of lines. This is used in YUV420 MSC scalar processing Y and UV pixels on the single HTS thread" "0,1" newline bitfld.long 0x8 28. "ENABLE_INTERLEAVED_PIXEL_EXTRACTION,This bit when set enable interleaved pixel extraction. usecases : YUV422 scenarios" "0,1" newline bitfld.long 0x8 27. "EXTRACT_INTERLEAVED_ODD_PIXELS,This bit is valid when enable_interleaved_pixel_extraction is set. 1 : Odd pixels extracted 0 : Even pixels extracted" "0: Even pixels extracted,1: Odd pixels extracted" newline hexmask.long.tbyte 0x8 6.--23. 1. "ADDR,Base Address[23:6] - (64 Byte aligned) byte address" newline hexmask.long.byte 0x8 0.--5. 1. "ADDR_6_LSB,Base Address[5:0] - 6 LSB bits of address should always be 0. Writes have no effect. Always read as 0" rgroup.long 0x50++0x7 line.long 0x0 "PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_buf_cfg,The DST[a]_BUF_CFG register configures the output buffer channel [a]." rbitfld.long 0x0 31. "CH_DISABLED,Channel Disable Status (read-only) 0: (Default) Chanel is enabled for Y UV or YUV422 data transfer to SL2 memory. All configurations associated with this DST_BUF[a] are valid. 1: Channel is disabled for SL2 data transfer (because the.." "?,1: Channel is disabled for SL2 data transfer" newline bitfld.long 0x0 29. "YUV422_INTLV_ORDER,YUV422 Interleaving Order Selection 0: UYVY 1: YUYV Only Applicable if this output channel is YUV422 output capable LUMA channel. Otherwise setting has no effect." "0: UYVY 1: YUYV Only Applicable if this output..,?" newline bitfld.long 0x0 28. "YUV422_OUT_EN,YUV422 Interleaved Output Merge Enable 0: Disable 1: Enable When enabled this channel interleaves data from the associated chroma data output channel to output YUV422 interleaved data to the SL2 memory. Only Applicable if this output.." "0: Disable,1: Enable When enabled" newline bitfld.long 0x0 10. "ENABLE_SIGNED_ACCLERATOR_DATA,Specify the acclerator data to be signed or unsigned 0: Unsigned data (By default) 1: Signed Data" "0: Unsigned data,1: Signed Data" newline bitfld.long 0x0 9. "ENABLE_OUTPUT_PIXEL_ROUNDING,enable acclerator pixel output rounding 0: Disable rounding logic 1: Enable rounding logic" "0: Disable rounding logic 1: Enable rounding logic,?" newline bitfld.long 0x0 8. "CHAN_THREAD_MAP,Output Channel - channel mapping per each thread 0: Mapped to channel-0 1: Mapped to channel-1" "0: Mapped to channel-0 1: Mapped to channel-1,?" newline bitfld.long 0x0 7. "THREAD_MAP,Output Channel - thread mapping 0: Mapped to Thread-0 1: Mapped to Thread-1" "0: Mapped to Thread-0 1: Mapped to Thread-1,?" newline bitfld.long 0x0 4. "PIX_FMT_ALIGN,Output Pixel Container Alignment 0: LSB-aligned 1: MSB-aligned" "0: LSB-aligned,1: MSB-aligned" newline bitfld.long 0x0 2.--3. "PIX_FMT_CNTRSZ,Output Pixel Container Size Sel 0: 8-bit 1: 12-bit 2: 16-bit 3: reserved Output pixel container size must be same or larger than output pixel width. If yuv422_out_en is set pix_fmt_cntrsz must be 0." "?,?,?,3: reserved Output pixel container size must be.." newline bitfld.long 0x0 0.--1. "PIX_FMT_PW,Output Pixel Width Sel 0: 8-bit 1: 12-bit 2: reserved 3: 16-bit The width defines the bit-depth of the pixel data to be stored in the pixel container." "?,?,2: reserved,?" line.long 0x4 "PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_buf_attr0,The DST[a]_BUF_ATTR0 register configures the attributes of the output SL2 buffer [a]." hexmask.long.word 0x4 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)" newline hexmask.long.word 0x4 6.--15. 1. "BUF_STRIDE,Buffer Stride Size [15:6] (64 byte multiple) stride size" newline hexmask.long.byte 0x4 0.--5. 1. "BUF_STRIDE_6_LSB,Buffer Stride Size [5:0] - 6 LSB bits of buffer stride size should always be 0. Writes have no effect. Always read as 0" rgroup.long 0x5C++0x3 line.long 0x0 "PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_buf_ba,The DST[a]_BUF_BA register configures the base address of the output SL2 circular buffer [a]." bitfld.long 0x0 31. "ENABLE,Output Channel Enable 0: Disable 1: Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 30. "SKIP_ODD_LINE_PROC,This bit when set skips odd line processing" "0,1" newline bitfld.long 0x0 29. "SKIP_ALTERNATE_LINE_PROC,This bit when enabled skips processing of lines. This is used in YUV420 MSC scalar processing Y and UV pixels on the single HTS thread" "0,1" newline hexmask.long.tbyte 0x0 6.--23. 1. "ADDR,Base Address[23:6] - (64 Byte aligned) byte address" newline hexmask.long.byte 0x0 0.--5. 1. "ADDR_6_LSB,Base Address[5:0] - 6 LSB bits of address should always be 0. Writes have no effect. Always read as 0" tree.end tree.end tree "VPAC0_PAR_VPAC_NF" tree "VPAC0_PAR_VPAC_NF_S_VBUSP_MMR_VBUSP_NF_CFG (VPAC0_PAR_VPAC_NF_S_VBUSP_MMR_VBUSP_NF_CFG)" base ad:0x38C2000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_NF__S_VBUSP__MMR__MMR_VBUSP__NF_CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" rgroup.long 0x4++0x7 line.long 0x0 "PAR_VPAC_NF__S_VBUSP__MMR__MMR_VBUSP__NF_CFG_CONTROL,This contains parameters to control NF Core" bitfld.long 0x0 29.--31. "SUB_TABLE_SELECT,Defines which sub table is used statically. Only valid when adaptive_mode is disabled This allows the SW to statically define which sub table to use throughout the frame. SW must set this before the first line of the frame.." "0: sub Table 0 selected,1: sub Table 1 selected,?,?,?,?,?,7: sub Table 7 selected" newline bitfld.long 0x0 27.--28. "NUM_SUB_TABLES,Defines the number of sub-tables 0 = 1 table 1 = 2 sub tables.." "0,1,2,3" newline hexmask.long.word 0x0 15.--26. 1. "OUTPUT_OFFSET,unsigned offset value to added to output after shifting and before clipping" newline hexmask.long.byte 0x0 11.--14. 1. "OUTPUT_SHIFT,Signed 4 bit (24 is added before using it inside IP)" newline hexmask.long.byte 0x0 6.--10. 1. "RSVD,Always read as 0. Writes have no affect" newline bitfld.long 0x0 5. "INTERLEAVE_MODE,Interleave Mode. 0 = Disabled 1 = Enabled" "0: Disabled,1: Enabled" newline bitfld.long 0x0 4. "SKIP_ODD_MODE,Skip Odd Mode. 0 = Disabled 1 = Enabled" "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "SKIP_MODE,Skip Mode. 0 = Disabled 1 = Enabled" "0: Disabled,1: Enabled" newline bitfld.long 0x0 2. "ADAPTIVE_MODE,Defines what controls the selection of the sub table. 0 = Bi-lateral filtering Adaptive mode is Disabled and sub_table_select defines which sub table is used.." "0: Bi-lateral filtering Adaptive mode is Disabled..,1: Bi-lateral filtering Adaptive mode is Enabled.." newline bitfld.long 0x0 1. "ENABLE_GENERIC_FILTERING,Filter mode 0=> Bi-lateral filtering 1= Generic 2D Filtering" "0: Bi-lateral filtering,1: Generic 2D Filtering" line.long 0x4 "PAR_VPAC_NF__S_VBUSP__MMR__MMR_VBUSP__NF_CFG_CENTER_WEIGHT,Contain center weight parameter" hexmask.long.tbyte 0x4 9.--31. 1. "RSVD,Always read as 0. Writes have no affect" newline hexmask.long.word 0x4 0.--8. 1. "CENTRAL_PIXEL_WEIGHT_W00,Central pixel weight 8 bit unsigned in Bi-lateral filtering 9 bit signed in Generic 2D Filtering" rgroup.long 0x80++0x3 line.long 0x0 "PAR_VPAC_NF__S_VBUSP__MMR__MMR_VBUSP__NF_CFG_DEBUG,Debug" bitfld.long 0x0 31. "BYPASS,Bypass Mode When enabled output equals the input namely C2_R0 input matrix" "0,1" newline hexmask.long.tbyte 0x0 12.--29. 1. "RSVD,Always read as 0. Writes have no affect" newline hexmask.long.byte 0x0 8.--11. 1. "OUT_COUNT,output free running counter gets reset on start of line" newline hexmask.long.byte 0x0 4.--7. 1. "IN_COUNT,input free running counter gets reset on start of line" newline hexmask.long.byte 0x0 0.--3. 1. "T_STATE,StateMachine State" rgroup.long 0x100++0x3 line.long 0x0 "PAR_VPAC_NF__S_VBUSP__MMR__MMR_VBUSP__NF_CFG_Weight_LUT,This contains weights for LUT. These acts as 1280 size LUT (8 bit each) in Bi-lateral mode. while 24 size (9 bit in 16 bit container) in Generic Filtering mode" hexmask.long.byte 0x0 24.--31. 1. "W_3,weight W_3" newline hexmask.long.byte 0x0 16.--23. 1. "W_2,weight W_2" newline hexmask.long.byte 0x0 8.--15. 1. "W_1,weight W_1" newline hexmask.long.byte 0x0 0.--7. 1. "W_0,weight W_0" tree.end tree "VPAC0_PAR_VPAC_NF_S_VBUSP_VPAC_NF_LSE_CFG_VP (VPAC0_PAR_VPAC_NF_S_VBUSP_VPAC_NF_LSE_CFG_VP)" base ad:0x38C3000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_NF__S_VBUSP__VPAC_NF_LSE__CFG_VP__REGS_status_param,The STATUS_PARAM register returns the LSE compile configuration parameters." bitfld.long 0x0 30.--31. "BYPASS_CH,Number of available input channel selection for loopback mode" "0,1,2,3" newline bitfld.long 0x0 29. "OUT_SKIP_EN,Output Auto-Skip Enable" "0,1" newline bitfld.long 0x0 28. "CORE_OUT_2D,1D or 2D output addressing mode(2D if 1)" "0,1" newline hexmask.long.byte 0x0 23.--27. 1. "CORE_OUT_DW,Core Output Channel Data Width" newline bitfld.long 0x0 22. "LINE_SKIP_EN,Source Line Inc by 2 Supported (if 1)" "0,1" newline bitfld.long 0x0 21. "BIT_AOFFSET,Source nibble offset address Supported (if 1)" "0,1" newline bitfld.long 0x0 20. "HV_INSERT,H/VBLANK Insertion Supported (if 1)" "0,1" newline bitfld.long 0x0 17.--19. "PIX_MX_HT,Core_Input Pixel Matrix Height" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 12.--16. 1. "CORE_DW,Core Input Data Bus Width" newline bitfld.long 0x0 10.--11. "SL2_OUT_H3A_CH,Number of SL2 H3A Output Channels" "0,1,2,3" newline hexmask.long.byte 0x0 6.--9. 1. "SL2_OUT_CH,Number of SL2 Output Channels" newline bitfld.long 0x0 3.--5. "SL2_IN_CH_THR,Number of Input Channels per thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "VPORT_THR,Number of VPORT input enabled" "0,1" newline bitfld.long 0x0 0.--1. "NTHR,Number of threads supported" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "PAR_VPAC_NF__S_VBUSP__VPAC_NF_LSE__CFG_VP__REGS_status_error,The STATUS_ERROR register returns the LSE error status." hexmask.long.byte 0x0 8.--14. 1. "VM_WR_ERR,VBUSM I/F Last Write Error Status [14:11] Write Channel Number [10:8] VBUSM write error status" newline hexmask.long.byte 0x0 0.--4. 1. "VM_RD_ERR,VBUSM I/F Last Read Error Status [4:3] Read Channel Number [2:0] VBUSM read error status" rgroup.long 0x8++0x3 line.long 0x0 "PAR_VPAC_NF__S_VBUSP__VPAC_NF_LSE__CFG_VP__REGS_status_idle_mode,The STATUS_IDLE_MODE register returns IDLE status of LSE VBUSM port and in/output channels - 0: IDLE 1: ACTIVE" bitfld.long 0x0 12. "LSE_OUT_CHAN,Output Channel[0:0] Status" "0,1" newline bitfld.long 0x0 4. "LSE_IN_CHAN,Input Channel[0:0] Status" "0,1" newline bitfld.long 0x0 1. "VM_WR_PORT,SL2 vbusm I/F Write Port Status" "0,1" newline bitfld.long 0x0 0. "VM_RD_PORT,SL2 vbusm I/F Read Port Status" "0,1" rgroup.long 0xC++0x3 line.long 0x0 "PAR_VPAC_NF__S_VBUSP__VPAC_NF_LSE__CFG_VP__REGS_cfg_lse,The CFG_LSE register configures the LSE general hardware modes." bitfld.long 0x0 8. "PSA_EN,Test mode Output Channel Signature Generation Enable 0: Disable (default) 1: Enable When enabled LSE generates a unique CRC signature for each output channel's frame data at frame completion." "0: Disable,1: Enable When enabled" newline bitfld.long 0x0 4. "VM_ARB_FIXED_MODE,VBUSM Arbitration Fixed Mode select 0: Round-Robin Arbitration (default) 1: Fixed-mode Arbitration" "0: Round-Robin Arbitration,1: Fixed-mode Arbitration" newline bitfld.long 0x0 1. "LOOPBACK_CORE_EN,Functional path (data to HWA core) enable during loopback mode 0: Disable 1: Enable When enabled the loopback-enabled input channel is used also for CORE data input. Otherwise it is strictly used for the loopback path." "0: Disable,1: Enable When enabled" newline bitfld.long 0x0 0. "LOOPBACK_EN,LSE loopback mode enable 0: Disable 1: Enable When enabled the input channel data (middle tap data) is looped back out to the output channel." "0: Disable,1: Enable When enabled" rgroup.long 0x140++0x3 line.long 0x0 "PAR_VPAC_NF__S_VBUSP__VPAC_NF_LSE__CFG_VP__REGS_psa_signature,The PSA_SIGNATURE register returns the captured PSA signature value of the last frame data of output channel [a]." hexmask.long 0x0 0.--31. 1. "VALUE,32-bit CRC signature value" rgroup.long 0x1E0++0x3 line.long 0x0 "PAR_VPAC_NF__S_VBUSP__VPAC_NF_LSE__CFG_VP__REGS_dbg,The DBG register returns the current status of internal FSM - TI internal use only." hexmask.long 0x0 0.--31. 1. "STATUS,Debug status" rgroup.long 0x10++0x3 line.long 0x0 "PAR_VPAC_NF__S_VBUSP__VPAC_NF_LSE__CFG_VP__REGS_cfg,The SRC_CFG register configures the input channels for the processing thread" bitfld.long 0x0 19.--21. "KERN_TPAD_SZ,Input kernel top padding lines valid=0..2 for nf" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "KERN_BPAD_SZ,Input kernel bottom padding lines valid=0..2 for nf" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 12.--15. 1. "KERN_LN_OFFSET,Input kernel starting line position valid=0..4 for nf" newline hexmask.long.byte 0x0 8.--11. 1. "KERN_SZ_HEIGHT,Actual number of input kernel lines (height) valid=1..5 for nf" newline bitfld.long 0x0 7. "SRC_LN_INC_2,Source Line address Increment by 2 enable 0: Disable 1: Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 4. "PIX_FMT_ALIGN,Input Pixel Container Alignment 0: LSB-aligned 1: MSB-aligned" "0: LSB-aligned,1: MSB-aligned" newline bitfld.long 0x0 2.--3. "PIX_FMT_CNTRSZ,Input Pixel Container Size Sel 0: 8-bit 1: 12-bit 2: 16-bit 3: reserved Input pixel container size must be same or larger than input pixel width." "?,?,?,3: reserved Input pixel container size must be same.." newline bitfld.long 0x0 0.--1. "PIX_FMT_PW,Input Pixel Width Sel 0: 8-bit 1: 12-bit 2: 14-bit 3: 16-bit The width defines the bit-depth of the pixel data to be extracted from the pixel container." "0,1,2,3" rgroup.long 0x18++0xB line.long 0x0 "PAR_VPAC_NF__S_VBUSP__VPAC_NF_LSE__CFG_VP__REGS_frame_size,The SRC_FRAME_SIZE register configures the frame size of all input buffers for the processing thread ." hexmask.long.word 0x0 16.--28. 1. "HEIGHT,SL2 - Source Buffer Height (number of lines)" newline hexmask.long.word 0x0 0.--12. 1. "WIDTH,SL2 - Source Buffer Width (number of pixels)" line.long 0x4 "PAR_VPAC_NF__S_VBUSP__VPAC_NF_LSE__CFG_VP__REGS_buf_attr,The SRC_BUF_ATTR register configures the common attributes of all SL2 source buffers for the processing thread ." hexmask.long.byte 0x4 25.--31. 1. "START_NIB_OFFSET,Buffer Line start offset within the first SL2 data word - in half-byte (nibble) resolution" newline hexmask.long.word 0x4 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)" newline hexmask.long.word 0x4 6.--15. 1. "BUF_STRIDE,Buffer Stride Size [15:6] (64 byte multiple) stride size" newline hexmask.long.byte 0x4 0.--5. 1. "BUF_STRIDE_6_LSB,Buffer Stride Size [5:0] - 6 LSB bits of buffer stride size should always be 0. Writes have no effect. Always read as 0" line.long 0x8 "PAR_VPAC_NF__S_VBUSP__VPAC_NF_LSE__CFG_VP__REGS_buf_ba,The SRC_BUF_BA register configures the base address of the SL2 source buffer for the processing thread ." bitfld.long 0x8 31. "ENABLE,Input Buffer Enable 0: Disable 1: Enable When the processing thread is enabled at least one of the input buffer must be enabled" "0: Disable,1: Enable When the processing thread is enabled" newline hexmask.long.tbyte 0x8 6.--23. 1. "ADDR,Base Address[23:6] - (64 Byte aligned) byte address" newline hexmask.long.byte 0x8 0.--5. 1. "ADDR_6_LSB,Base Address[5:0] - 6 LSB bits of address should always be 0. Writes have no effect. Always read as 0" rgroup.long 0x50++0x7 line.long 0x0 "PAR_VPAC_NF__S_VBUSP__VPAC_NF_LSE__CFG_VP__REGS_buf_cfg,The DST_BUF_CFG register configures the output buffer channel ." bitfld.long 0x0 4. "PIX_FMT_ALIGN,Output Pixel Container Alignment 0: LSB-aligned 1: MSB-aligned" "0: LSB-aligned,1: MSB-aligned" newline bitfld.long 0x0 2.--3. "PIX_FMT_CNTRSZ,Output Pixel Container Size Sel 0: 8-bit 1: 12-bit 2: 16-bit 3: reserved Output pixel container size must be same or larger than output pixel width." "?,?,?,3: reserved Output pixel container size must be.." newline bitfld.long 0x0 0.--1. "PIX_FMT_PW,Output Pixel Width Sel 0: 8-bit 1: 12-bit 2: reserved 3: 16-bit The width defines the bit-depth of the pixel data to be stored in the pixel container." "?,?,2: reserved,?" line.long 0x4 "PAR_VPAC_NF__S_VBUSP__VPAC_NF_LSE__CFG_VP__REGS_buf_attr0,The DST_BUF_ATTR0 register configures the attributes of the output SL2 buffer ." hexmask.long.word 0x4 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)" newline hexmask.long.word 0x4 6.--15. 1. "BUF_STRIDE,Buffer Stride Size [15:6] (64 byte multiple) stride size" newline hexmask.long.byte 0x4 0.--5. 1. "BUF_STRIDE_6_LSB,Buffer Stride Size [5:0] - 6 LSB bits of buffer stride size should always be 0. Writes have no effect. Always read as 0" rgroup.long 0x5C++0x3 line.long 0x0 "PAR_VPAC_NF__S_VBUSP__VPAC_NF_LSE__CFG_VP__REGS_buf_ba,The DST_BUF_BA register configures the base address of the output SL2 circular buffer ." bitfld.long 0x0 31. "ENABLE,Output Channel Enable 0: Disable 1: Enable" "0: Disable,1: Enable" newline hexmask.long.tbyte 0x0 6.--23. 1. "ADDR,Base Address[23:6] - (64 Byte aligned) byte address" newline hexmask.long.byte 0x0 0.--5. 1. "ADDR_6_LSB,Base Address[5:0] - 6 LSB bits of address should always be 0. Writes have no effect. Always read as 0" tree.end tree.end tree "VPAC0_PAR_VPAC_VISS0" tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_K3_GLBCE_TOP_CFG_GLBCE (VPAC0_PAR_VPAC_VISS0_S_VBUSP_K3_GLBCE_TOP_CFG_GLBCE)" base ad:0x3903800 rgroup.long 0x0++0xAF line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_CFG,GLBCE Configuration Registers" bitfld.long 0x0 0. "SWRST,Reserved for this version for HW. This bit initiate software reset process" "0,1" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_MODE,GLBCE Mode Control register" bitfld.long 0x4 0. "OST,One shot mode or continuous mode One shot mode turns itself off after each frame Note that this bit only controls the enable signal and does not revert the statistics to the default status To revert the cache content to the default status you.." "0,1" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_CONTROL0,GLBCE Control Register 0 (control_0)" rbitfld.long 0x8 4. "CCTL,Color Control [CCTL] - Enabling this processing will result in more accurate colors processing The color correction algorithm is required on gamma corrected sources It reduces the saturation in dark areas when they are being amplified and saturates.." "0,1" bitfld.long 0x8 3. "MB,Max Bayer Type- Use this bit to select the algorithm used for calculating intensity 0b: Algorithm 1 1b: Algorithm 2 [Recommended]" "0,1" newline rbitfld.long 0x8 1.--2. "RESERVED0,These bits are read only Controls the storage of image sensor RAW data in memory This bit is loaded with the timing of the internal VD signal: it becomes active starting at the lead of the VD signal that comes after 1 is written in this bit" "0,1,2,3" bitfld.long 0x8 0. "ONOFF,GLBCE On/Off - This bit turns GLBCE processing ON and OFF When GLBCE is OFF the video data passes to the output without any changes Disabling GLBCE using this bit is equivalent to setting the Strength parameter to 0 Many internal modules run in.." "0,1" line.long 0xC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_CONTROL1,Connected to iridix_control1 parameter in GLBCE Core" hexmask.long.byte 0xC 0.--7. 1. "CONTROL1,Connected Control1 port" line.long 0x10 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_BLACK_LEVEL,Black Level Register (black_level)" hexmask.long.word 0x10 0.--15. 1. "VAL,The value stored in Black Level Port will be used as zero level for GLBCE processing in all unsigned data channels Data below Black level will not be processed and stay unchanged" line.long 0x14 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WHITE_LEVEL,White Level Register (white_level)" hexmask.long.word 0x14 0.--15. 1. "VAL,The value stored in White Level Port will be used as white level for GLBCE processing in all unsigned data channels Data above White level will not be processed and stay unchanged" line.long 0x18 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_VARIANCE,Affects the sensitivity of the transform to different areas of the image. and can be increased in order to emphasize small regions (e.g. faces)." hexmask.long.byte 0x18 4.--7. 1. "VARIANCEINTENSITY,Variance Intensity - Sets the degree of sensitivity in the luminance domain Maximum Variance is 0xF and minimum Variance is 0x0" hexmask.long.byte 0x18 0.--3. 1. "VARIANCESPACE,Variance Space - Sets the degree of spatial sensitivity of the algorithm As this parameter is made smaller the algorithm focuses on smaller regions within the image Maximum Variance is 0xF and minimum Variance is 0x0" line.long 0x1C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LIMIT_AMPL,The parameters" hexmask.long.byte 0x1C 4.--7. 1. "BRIGHTAMPLIFICATIONLIMIT,Bright amplification limit - The resultant tone curve cannot be lower than bright amplification limit line controlled by the bright amplification limit parameter See Chapter 4 of the spec document for more explanation Maximum.." hexmask.long.byte 0x1C 0.--3. 1. "DARKAMPLIFICATIONLIMIT,Dark amplification limit - The resultant tone curve cannot be higher than dark amplification limit line controlled by the dark amplification limit parameter See Chapter 4 of the spec for more explanation Maximum limit is 0xF when.." line.long 0x20 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_DITHER,Dithering Register (dither)" bitfld.long 0x20 0.--2. "DITHER,000b: No dithering 001b: One least significant bit of the output signal is dithered 010b: Two bits are dithered 011b: Three bits are dithered 100b: Four bits are dithered All other values : Four bits are dithered" "0,1,2,3,4,5,6,7" line.long 0x24 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_SLOPE_MAX,Slope Max Limit Register (slope_max)" hexmask.long.byte 0x24 0.--7. 1. "SLOPEMAXLIMIT,Slope Max Limit - Slope Max Limit is used to restrict the slope of the tone-curve generated by GLBCE When Slope Max Limit parameter is set to 0xFF the tone curve slope generated by GLBCE is not limited [maximum slope 15] When this value.." line.long 0x28 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_SLOPE_MIN,Slope Min Limit Register (slope_min)" hexmask.long.byte 0x28 0.--7. 1. "SLOPEMINLIMIT,Slope Min Limit - Slope Min Limit is used to restrict the slope of the tone-curve generated by GLBCE When Slope Min Limit parameter is set to 0x00 the tone curve slope generated by GLBCE is not limited When this value is set to FF GLBCE.." line.long 0x2C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_00,Asymmetry Function LUT" hexmask.long.word 0x2C 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x30 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_01,Asymmetry Function LUT" hexmask.long.word 0x30 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x34 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_02,Asymmetry Function LUT" hexmask.long.word 0x34 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x38 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_03,Asymmetry Function LUT" hexmask.long.word 0x38 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x3C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_04,Asymmetry Function LUT" hexmask.long.word 0x3C 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x40 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_05,Asymmetry Function LUT" hexmask.long.word 0x40 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x44 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_06,Asymmetry Function LUT" hexmask.long.word 0x44 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x48 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_07,Asymmetry Function LUT" hexmask.long.word 0x48 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x4C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_08,Asymmetry Function LUT" hexmask.long.word 0x4C 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x50 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_09,Asymmetry Function LUT" hexmask.long.word 0x50 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x54 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_10,Asymmetry Function LUT" hexmask.long.word 0x54 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x58 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_11,Asymmetry Function LUT" hexmask.long.word 0x58 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x5C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_12,Asymmetry Function LUT" hexmask.long.word 0x5C 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x60 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_13,Asymmetry Function LUT" hexmask.long.word 0x60 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x64 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_14,Asymmetry Function LUT" hexmask.long.word 0x64 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x68 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_15,Asymmetry Function LUT" hexmask.long.word 0x68 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x6C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_16,Asymmetry Function LUT" hexmask.long.word 0x6C 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x70 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_17,Asymmetry Function LUT" hexmask.long.word 0x70 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x74 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_18,Asymmetry Function LUT" hexmask.long.word 0x74 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x78 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_19,Asymmetry Function LUT" hexmask.long.word 0x78 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x7C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_20,Asymmetry Function LUT" hexmask.long.word 0x7C 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x80 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_21,Asymmetry Function LUT" hexmask.long.word 0x80 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x84 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_22,Asymmetry Function LUT" hexmask.long.word 0x84 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x88 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_23,Asymmetry Function LUT" hexmask.long.word 0x88 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x8C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_24,Asymmetry Function LUT" hexmask.long.word 0x8C 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x90 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_25,Asymmetry Function LUT" hexmask.long.word 0x90 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x94 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_26,Asymmetry Function LUT" hexmask.long.word 0x94 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x98 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_27,Asymmetry Function LUT" hexmask.long.word 0x98 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x9C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_28,Asymmetry Function LUT" hexmask.long.word 0x9C 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0xA0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_29,Asymmetry Function LUT" hexmask.long.word 0xA0 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0xA4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_30,Asymmetry Function LUT" hexmask.long.word 0xA4 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0xA8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_31,Asymmetry Function LUT" hexmask.long.word 0xA8 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0xAC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_32,Asymmetry Function LUT" hexmask.long.word 0xAC 0.--15. 1. "VAL,Asymmetry LUT Entry" rgroup.long 0xB0++0x7 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FORMAT_CONTROL_REG0,Data format port specifies the input data format so that the GLBCE core can process the different input data formats. This register is reserved for this version of HW" bitfld.long 0x0 0.--1. "DATAFORMAT,This value is reserved The color format is always RGB and this value should be fixed 0" "0,1,2,3" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FORMAT_CONTROL_REG1,Control Reg1" bitfld.long 0x4 7. "AUTOSIZE,This value is read only. GLBCE in this HW version never use Auto-size mode" "0,1" bitfld.long 0x4 6. "AUTOPOS,This value is read only. GLBCE in this HW version always runs in Auto Position mode" "0,1" newline bitfld.long 0x4 4.--5. "FCMODE,Field Correction Mode" "0,1,2,3" bitfld.long 0x4 1. "VSPOL,Vertical Sync Polarity This value is read only The SWITCH block always convert the polarity to rising edge active" "0,1" newline bitfld.long 0x4 0. "HSPOL,Horizontal Sync Polarity This value is read only The SWITCH block always convert the polarity to rising edge active" "0,1" rgroup.long 0xB8++0x623 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FRAME_WIDTH,Frame Width is the number of pixels in an active line. This port is used only in non-automatic mode." hexmask.long.word 0x0 0.--15. 1. "VAL,Frame Width. minimum of 480" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FRAME_HEIGHT,Frame Height is the number of active lines in one field." hexmask.long.word 0x4 0.--15. 1. "VAL,Frame Height. minimum of 240" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_STRENGTH_IR,Strength (Strength of GLBCE) - This Port sets processing Strength. Minimum value is 0. maximum is 255." hexmask.long.byte 0x8 0.--7. 1. "VAL,0x00: Video data will not be processed at all and will go to the output unchanged 0xFF: Maximum strength" line.long 0xC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_PERCEPT_EN,Enable for GLBCE Perceptual LUT function" bitfld.long 0xC 1. "FWD_EN,Forward Perceptual LUT enable" "0,1" bitfld.long 0xC 0. "REV_EN,Reverse Perceptual LUT enable[" "0,1" line.long 0x10 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_00,Reverse Perceptual LUT" hexmask.long.word 0x10 0.--15. 1. "VAL,LUT Value" line.long 0x14 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_01,Reverse Perceptual LUT" hexmask.long.word 0x14 0.--15. 1. "VAL,LUT Value" line.long 0x18 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_02,Reverse Perceptual LUT" hexmask.long.word 0x18 0.--15. 1. "VAL,LUT Value" line.long 0x1C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_03,Reverse Perceptual LUT" hexmask.long.word 0x1C 0.--15. 1. "VAL,LUT Value" line.long 0x20 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_04,Reverse Perceptual LUT" hexmask.long.word 0x20 0.--15. 1. "VAL,LUT Value" line.long 0x24 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_05,Reverse Perceptual LUT" hexmask.long.word 0x24 0.--15. 1. "VAL,LUT Value" line.long 0x28 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_06,Reverse Perceptual LUT" hexmask.long.word 0x28 0.--15. 1. "VAL,LUT Value" line.long 0x2C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_07,Reverse Perceptual LUT" hexmask.long.word 0x2C 0.--15. 1. "VAL,LUT Value" line.long 0x30 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_08,Reverse Perceptual LUT" hexmask.long.word 0x30 0.--15. 1. "VAL,LUT Value" line.long 0x34 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_09,Reverse Perceptual LUT" hexmask.long.word 0x34 0.--15. 1. "VAL,LUT Value" line.long 0x38 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_10,Reverse Perceptual LUT" hexmask.long.word 0x38 0.--15. 1. "VAL,LUT Value" line.long 0x3C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_11,Reverse Perceptual LUT" hexmask.long.word 0x3C 0.--15. 1. "VAL,LUT Value" line.long 0x40 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_12,Reverse Perceptual LUT" hexmask.long.word 0x40 0.--15. 1. "VAL,LUT Value" line.long 0x44 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_13,Reverse Perceptual LUT" hexmask.long.word 0x44 0.--15. 1. "VAL,LUT Value" line.long 0x48 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_14,Reverse Perceptual LUT" hexmask.long.word 0x48 0.--15. 1. "VAL,LUT Value" line.long 0x4C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_15,Reverse Perceptual LUT" hexmask.long.word 0x4C 0.--15. 1. "VAL,LUT Value" line.long 0x50 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_16,Reverse Perceptual LUT" hexmask.long.word 0x50 0.--15. 1. "VAL,LUT Value" line.long 0x54 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_17,Reverse Perceptual LUT" hexmask.long.word 0x54 0.--15. 1. "VAL,LUT Value" line.long 0x58 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_18,Reverse Perceptual LUT" hexmask.long.word 0x58 0.--15. 1. "VAL,LUT Value" line.long 0x5C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_19,Reverse Perceptual LUT" hexmask.long.word 0x5C 0.--15. 1. "VAL,LUT Value" line.long 0x60 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_20,Reverse Perceptual LUT" hexmask.long.word 0x60 0.--15. 1. "VAL,LUT Value" line.long 0x64 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_21,Reverse Perceptual LUT" hexmask.long.word 0x64 0.--15. 1. "VAL,LUT Value" line.long 0x68 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_22,Reverse Perceptual LUT" hexmask.long.word 0x68 0.--15. 1. "VAL,LUT Value" line.long 0x6C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_23,Reverse Perceptual LUT" hexmask.long.word 0x6C 0.--15. 1. "VAL,LUT Value" line.long 0x70 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_24,Reverse Perceptual LUT" hexmask.long.word 0x70 0.--15. 1. "VAL,LUT Value" line.long 0x74 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_25,Reverse Perceptual LUT" hexmask.long.word 0x74 0.--15. 1. "VAL,LUT Value" line.long 0x78 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_26,Reverse Perceptual LUT" hexmask.long.word 0x78 0.--15. 1. "VAL,LUT Value" line.long 0x7C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_27,Reverse Perceptual LUT" hexmask.long.word 0x7C 0.--15. 1. "VAL,LUT Value" line.long 0x80 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_28,Reverse Perceptual LUT" hexmask.long.word 0x80 0.--15. 1. "VAL,LUT Value" line.long 0x84 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_29,Reverse Perceptual LUT" hexmask.long.word 0x84 0.--15. 1. "VAL,LUT Value" line.long 0x88 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_30,Reverse Perceptual LUT" hexmask.long.word 0x88 0.--15. 1. "VAL,LUT Value" line.long 0x8C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_31,Reverse Perceptual LUT" hexmask.long.word 0x8C 0.--15. 1. "VAL,LUT Value" line.long 0x90 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_32,Reverse Perceptual LUT" hexmask.long.word 0x90 0.--15. 1. "VAL,LUT Value" line.long 0x94 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_33,Reverse Perceptual LUT" hexmask.long.word 0x94 0.--15. 1. "VAL,LUT Value" line.long 0x98 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_34,Reverse Perceptual LUT" hexmask.long.word 0x98 0.--15. 1. "VAL,LUT Value" line.long 0x9C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_35,Reverse Perceptual LUT" hexmask.long.word 0x9C 0.--15. 1. "VAL,LUT Value" line.long 0xA0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_36,Reverse Perceptual LUT" hexmask.long.word 0xA0 0.--15. 1. "VAL,LUT Value" line.long 0xA4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_37,Reverse Perceptual LUT" hexmask.long.word 0xA4 0.--15. 1. "VAL,LUT Value" line.long 0xA8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_38,Reverse Perceptual LUT" hexmask.long.word 0xA8 0.--15. 1. "VAL,LUT Value" line.long 0xAC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_39,Reverse Perceptual LUT" hexmask.long.word 0xAC 0.--15. 1. "VAL,LUT Value" line.long 0xB0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_40,Reverse Perceptual LUT" hexmask.long.word 0xB0 0.--15. 1. "VAL,LUT Value" line.long 0xB4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_41,Reverse Perceptual LUT" hexmask.long.word 0xB4 0.--15. 1. "VAL,LUT Value" line.long 0xB8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_42,Reverse Perceptual LUT" hexmask.long.word 0xB8 0.--15. 1. "VAL,LUT Value" line.long 0xBC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_43,Reverse Perceptual LUT" hexmask.long.word 0xBC 0.--15. 1. "VAL,LUT Value" line.long 0xC0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_44,Reverse Perceptual LUT" hexmask.long.word 0xC0 0.--15. 1. "VAL,LUT Value" line.long 0xC4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_45,Reverse Perceptual LUT" hexmask.long.word 0xC4 0.--15. 1. "VAL,LUT Value" line.long 0xC8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_46,Reverse Perceptual LUT" hexmask.long.word 0xC8 0.--15. 1. "VAL,LUT Value" line.long 0xCC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_47,Reverse Perceptual LUT" hexmask.long.word 0xCC 0.--15. 1. "VAL,LUT Value" line.long 0xD0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_48,Reverse Perceptual LUT" hexmask.long.word 0xD0 0.--15. 1. "VAL,LUT Value" line.long 0xD4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_49,Reverse Perceptual LUT" hexmask.long.word 0xD4 0.--15. 1. "VAL,LUT Value" line.long 0xD8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_50,Reverse Perceptual LUT" hexmask.long.word 0xD8 0.--15. 1. "VAL,LUT Value" line.long 0xDC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_51,Reverse Perceptual LUT" hexmask.long.word 0xDC 0.--15. 1. "VAL,LUT Value" line.long 0xE0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_52,Reverse Perceptual LUT" hexmask.long.word 0xE0 0.--15. 1. "VAL,LUT Value" line.long 0xE4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_53,Reverse Perceptual LUT" hexmask.long.word 0xE4 0.--15. 1. "VAL,LUT Value" line.long 0xE8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_54,Reverse Perceptual LUT" hexmask.long.word 0xE8 0.--15. 1. "VAL,LUT Value" line.long 0xEC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_55,Reverse Perceptual LUT" hexmask.long.word 0xEC 0.--15. 1. "VAL,LUT Value" line.long 0xF0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_56,Reverse Perceptual LUT" hexmask.long.word 0xF0 0.--15. 1. "VAL,LUT Value" line.long 0xF4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_57,Reverse Perceptual LUT" hexmask.long.word 0xF4 0.--15. 1. "VAL,LUT Value" line.long 0xF8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_58,Reverse Perceptual LUT" hexmask.long.word 0xF8 0.--15. 1. "VAL,LUT Value" line.long 0xFC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_59,Reverse Perceptual LUT" hexmask.long.word 0xFC 0.--15. 1. "VAL,LUT Value" line.long 0x100 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_60,Reverse Perceptual LUT" hexmask.long.word 0x100 0.--15. 1. "VAL,LUT Value" line.long 0x104 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_61,Reverse Perceptual LUT" hexmask.long.word 0x104 0.--15. 1. "VAL,LUT Value" line.long 0x108 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_62,Reverse Perceptual LUT" hexmask.long.word 0x108 0.--15. 1. "VAL,LUT Value" line.long 0x10C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_63,Reverse Perceptual LUT" hexmask.long.word 0x10C 0.--15. 1. "VAL,LUT Value" line.long 0x110 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_64,Reverse Perceptual LUT" hexmask.long.word 0x110 0.--15. 1. "VAL,LUT Value" line.long 0x114 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_00,Forward Perception LUT" hexmask.long.word 0x114 0.--15. 1. "VAL,LUT Value" line.long 0x118 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_01,Forward Perception LUT" hexmask.long.word 0x118 0.--15. 1. "VAL,LUT Value" line.long 0x11C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_02,Forward Perception LUT" hexmask.long.word 0x11C 0.--15. 1. "VAL,LUT Value" line.long 0x120 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_03,Forward Perception LUT" hexmask.long.word 0x120 0.--15. 1. "VAL,LUT Value" line.long 0x124 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_04,Forward Perception LUT" hexmask.long.word 0x124 0.--15. 1. "VAL,LUT Value" line.long 0x128 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_05,Forward Perception LUT" hexmask.long.word 0x128 0.--15. 1. "VAL,LUT Value" line.long 0x12C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_06,Forward Perception LUT" hexmask.long.word 0x12C 0.--15. 1. "VAL,LUT Value" line.long 0x130 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_07,Forward Perception LUT" hexmask.long.word 0x130 0.--15. 1. "VAL,LUT Value" line.long 0x134 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_08,Forward Perception LUT" hexmask.long.word 0x134 0.--15. 1. "VAL,LUT Value" line.long 0x138 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_09,Forward Perception LUT" hexmask.long.word 0x138 0.--15. 1. "VAL,LUT Value" line.long 0x13C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_10,Forward Perception LUT" hexmask.long.word 0x13C 0.--15. 1. "VAL,LUT Value" line.long 0x140 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_11,Forward Perception LUT" hexmask.long.word 0x140 0.--15. 1. "VAL,LUT Value" line.long 0x144 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_12,Forward Perception LUT" hexmask.long.word 0x144 0.--15. 1. "VAL,LUT Value" line.long 0x148 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_13,Forward Perception LUT" hexmask.long.word 0x148 0.--15. 1. "VAL,LUT Value" line.long 0x14C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_14,Forward Perception LUT" hexmask.long.word 0x14C 0.--15. 1. "VAL,LUT Value" line.long 0x150 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_15,Forward Perception LUT" hexmask.long.word 0x150 0.--15. 1. "VAL,LUT Value" line.long 0x154 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_16,Forward Perception LUT" hexmask.long.word 0x154 0.--15. 1. "VAL,LUT Value" line.long 0x158 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_17,Forward Perception LUT" hexmask.long.word 0x158 0.--15. 1. "VAL,LUT Value" line.long 0x15C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_18,Forward Perception LUT" hexmask.long.word 0x15C 0.--15. 1. "VAL,LUT Value" line.long 0x160 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_19,Forward Perception LUT" hexmask.long.word 0x160 0.--15. 1. "VAL,LUT Value" line.long 0x164 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_20,Forward Perception LUT" hexmask.long.word 0x164 0.--15. 1. "VAL,LUT Value" line.long 0x168 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_21,Forward Perception LUT" hexmask.long.word 0x168 0.--15. 1. "VAL,LUT Value" line.long 0x16C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_22,Forward Perception LUT" hexmask.long.word 0x16C 0.--15. 1. "VAL,LUT Value" line.long 0x170 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_23,Forward Perception LUT" hexmask.long.word 0x170 0.--15. 1. "VAL,LUT Value" line.long 0x174 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_24,Forward Perception LUT" hexmask.long.word 0x174 0.--15. 1. "VAL,LUT Value" line.long 0x178 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_25,Forward Perception LUT" hexmask.long.word 0x178 0.--15. 1. "VAL,LUT Value" line.long 0x17C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_26,Forward Perception LUT" hexmask.long.word 0x17C 0.--15. 1. "VAL,LUT Value" line.long 0x180 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_27,Forward Perception LUT" hexmask.long.word 0x180 0.--15. 1. "VAL,LUT Value" line.long 0x184 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_28,Forward Perception LUT" hexmask.long.word 0x184 0.--15. 1. "VAL,LUT Value" line.long 0x188 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_29,Forward Perception LUT" hexmask.long.word 0x188 0.--15. 1. "VAL,LUT Value" line.long 0x18C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_30,Forward Perception LUT" hexmask.long.word 0x18C 0.--15. 1. "VAL,LUT Value" line.long 0x190 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_31,Forward Perception LUT" hexmask.long.word 0x190 0.--15. 1. "VAL,LUT Value" line.long 0x194 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_32,Forward Perception LUT" hexmask.long.word 0x194 0.--15. 1. "VAL,LUT Value" line.long 0x198 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_33,Forward Perception LUT" hexmask.long.word 0x198 0.--15. 1. "VAL,LUT Value" line.long 0x19C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_34,Forward Perception LUT" hexmask.long.word 0x19C 0.--15. 1. "VAL,LUT Value" line.long 0x1A0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_35,Forward Perception LUT" hexmask.long.word 0x1A0 0.--15. 1. "VAL,LUT Value" line.long 0x1A4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_36,Forward Perception LUT" hexmask.long.word 0x1A4 0.--15. 1. "VAL,LUT Value" line.long 0x1A8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_37,Forward Perception LUT" hexmask.long.word 0x1A8 0.--15. 1. "VAL,LUT Value" line.long 0x1AC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_38,Forward Perception LUT" hexmask.long.word 0x1AC 0.--15. 1. "VAL,LUT Value" line.long 0x1B0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_39,Forward Perception LUT" hexmask.long.word 0x1B0 0.--15. 1. "VAL,LUT Value" line.long 0x1B4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_40,Forward Perception LUT" hexmask.long.word 0x1B4 0.--15. 1. "VAL,LUT Value" line.long 0x1B8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_41,Forward Perception LUT" hexmask.long.word 0x1B8 0.--15. 1. "VAL,LUT Value" line.long 0x1BC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_42,Forward Perception LUT" hexmask.long.word 0x1BC 0.--15. 1. "VAL,LUT Value" line.long 0x1C0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_43,Forward Perception LUT" hexmask.long.word 0x1C0 0.--15. 1. "VAL,LUT Value" line.long 0x1C4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_44,Forward Perception LUT" hexmask.long.word 0x1C4 0.--15. 1. "VAL,LUT Value" line.long 0x1C8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_45,Forward Perception LUT" hexmask.long.word 0x1C8 0.--15. 1. "VAL,LUT Value" line.long 0x1CC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_46,Forward Perception LUT" hexmask.long.word 0x1CC 0.--15. 1. "VAL,LUT Value" line.long 0x1D0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_47,Forward Perception LUT" hexmask.long.word 0x1D0 0.--15. 1. "VAL,LUT Value" line.long 0x1D4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_48,Forward Perception LUT" hexmask.long.word 0x1D4 0.--15. 1. "VAL,LUT Value" line.long 0x1D8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_49,Forward Perception LUT" hexmask.long.word 0x1D8 0.--15. 1. "VAL,LUT Value" line.long 0x1DC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_50,Forward Perception LUT" hexmask.long.word 0x1DC 0.--15. 1. "VAL,LUT Value" line.long 0x1E0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_51,Forward Perception LUT" hexmask.long.word 0x1E0 0.--15. 1. "VAL,LUT Value" line.long 0x1E4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_52,Forward Perception LUT" hexmask.long.word 0x1E4 0.--15. 1. "VAL,LUT Value" line.long 0x1E8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_53,Forward Perception LUT" hexmask.long.word 0x1E8 0.--15. 1. "VAL,LUT Value" line.long 0x1EC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_54,Forward Perception LUT" hexmask.long.word 0x1EC 0.--15. 1. "VAL,LUT Value" line.long 0x1F0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_55,Forward Perception LUT" hexmask.long.word 0x1F0 0.--15. 1. "VAL,LUT Value" line.long 0x1F4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_56,Forward Perception LUT" hexmask.long.word 0x1F4 0.--15. 1. "VAL,LUT Value" line.long 0x1F8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_57,Forward Perception LUT" hexmask.long.word 0x1F8 0.--15. 1. "VAL,LUT Value" line.long 0x1FC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_58,Forward Perception LUT" hexmask.long.word 0x1FC 0.--15. 1. "VAL,LUT Value" line.long 0x200 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_59,Forward Perception LUT" hexmask.long.word 0x200 0.--15. 1. "VAL,LUT Value" line.long 0x204 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_60,Forward Perception LUT" hexmask.long.word 0x204 0.--15. 1. "VAL,LUT Value" line.long 0x208 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_61,Forward Perception LUT" hexmask.long.word 0x208 0.--15. 1. "VAL,LUT Value" line.long 0x20C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_62,Forward Perception LUT" hexmask.long.word 0x20C 0.--15. 1. "VAL,LUT Value" line.long 0x210 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_63,Forward Perception LUT" hexmask.long.word 0x210 0.--15. 1. "VAL,LUT Value" line.long 0x214 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_64,Forward Perception LUT" hexmask.long.word 0x214 0.--15. 1. "VAL,LUT Value" line.long 0x218 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_EN,WDR Gamma LUT Enable" bitfld.long 0x218 0. "EN,Frontend WDR LUT enable" "0,1" line.long 0x21C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_00,Frontend WDR LUT" hexmask.long.word 0x21C 0.--15. 1. "VAL,LUT Value" line.long 0x220 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_01,Frontend WDR LUT" hexmask.long.word 0x220 0.--15. 1. "VAL,LUT Value" line.long 0x224 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_02,Frontend WDR LUT" hexmask.long.word 0x224 0.--15. 1. "VAL,LUT Value" line.long 0x228 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_03,Frontend WDR LUT" hexmask.long.word 0x228 0.--15. 1. "VAL,LUT Value" line.long 0x22C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_04,Frontend WDR LUT" hexmask.long.word 0x22C 0.--15. 1. "VAL,LUT Value" line.long 0x230 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_05,Frontend WDR LUT" hexmask.long.word 0x230 0.--15. 1. "VAL,LUT Value" line.long 0x234 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_06,Frontend WDR LUT" hexmask.long.word 0x234 0.--15. 1. "VAL,LUT Value" line.long 0x238 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_07,Frontend WDR LUT" hexmask.long.word 0x238 0.--15. 1. "VAL,LUT Value" line.long 0x23C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_08,Frontend WDR LUT" hexmask.long.word 0x23C 0.--15. 1. "VAL,LUT Value" line.long 0x240 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_09,Frontend WDR LUT" hexmask.long.word 0x240 0.--15. 1. "VAL,LUT Value" line.long 0x244 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_10,Frontend WDR LUT" hexmask.long.word 0x244 0.--15. 1. "VAL,LUT Value" line.long 0x248 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_11,Frontend WDR LUT" hexmask.long.word 0x248 0.--15. 1. "VAL,LUT Value" line.long 0x24C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_12,Frontend WDR LUT" hexmask.long.word 0x24C 0.--15. 1. "VAL,LUT Value" line.long 0x250 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_13,Frontend WDR LUT" hexmask.long.word 0x250 0.--15. 1. "VAL,LUT Value" line.long 0x254 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_14,Frontend WDR LUT" hexmask.long.word 0x254 0.--15. 1. "VAL,LUT Value" line.long 0x258 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_15,Frontend WDR LUT" hexmask.long.word 0x258 0.--15. 1. "VAL,LUT Value" line.long 0x25C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_16,Frontend WDR LUT" hexmask.long.word 0x25C 0.--15. 1. "VAL,LUT Value" line.long 0x260 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_17,Frontend WDR LUT" hexmask.long.word 0x260 0.--15. 1. "VAL,LUT Value" line.long 0x264 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_18,Frontend WDR LUT" hexmask.long.word 0x264 0.--15. 1. "VAL,LUT Value" line.long 0x268 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_19,Frontend WDR LUT" hexmask.long.word 0x268 0.--15. 1. "VAL,LUT Value" line.long 0x26C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_20,Frontend WDR LUT" hexmask.long.word 0x26C 0.--15. 1. "VAL,LUT Value" line.long 0x270 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_21,Frontend WDR LUT" hexmask.long.word 0x270 0.--15. 1. "VAL,LUT Value" line.long 0x274 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_22,Frontend WDR LUT" hexmask.long.word 0x274 0.--15. 1. "VAL,LUT Value" line.long 0x278 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_23,Frontend WDR LUT" hexmask.long.word 0x278 0.--15. 1. "VAL,LUT Value" line.long 0x27C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_24,Frontend WDR LUT" hexmask.long.word 0x27C 0.--15. 1. "VAL,LUT Value" line.long 0x280 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_25,Frontend WDR LUT" hexmask.long.word 0x280 0.--15. 1. "VAL,LUT Value" line.long 0x284 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_26,Frontend WDR LUT" hexmask.long.word 0x284 0.--15. 1. "VAL,LUT Value" line.long 0x288 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_27,Frontend WDR LUT" hexmask.long.word 0x288 0.--15. 1. "VAL,LUT Value" line.long 0x28C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_28,Frontend WDR LUT" hexmask.long.word 0x28C 0.--15. 1. "VAL,LUT Value" line.long 0x290 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_29,Frontend WDR LUT" hexmask.long.word 0x290 0.--15. 1. "VAL,LUT Value" line.long 0x294 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_30,Frontend WDR LUT" hexmask.long.word 0x294 0.--15. 1. "VAL,LUT Value" line.long 0x298 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_31,Frontend WDR LUT" hexmask.long.word 0x298 0.--15. 1. "VAL,LUT Value" line.long 0x29C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_32,Frontend WDR LUT" hexmask.long.word 0x29C 0.--15. 1. "VAL,LUT Value" line.long 0x2A0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_33,Frontend WDR LUT" hexmask.long.word 0x2A0 0.--15. 1. "VAL,LUT Value" line.long 0x2A4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_34,Frontend WDR LUT" hexmask.long.word 0x2A4 0.--15. 1. "VAL,LUT Value" line.long 0x2A8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_35,Frontend WDR LUT" hexmask.long.word 0x2A8 0.--15. 1. "VAL,LUT Value" line.long 0x2AC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_36,Frontend WDR LUT" hexmask.long.word 0x2AC 0.--15. 1. "VAL,LUT Value" line.long 0x2B0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_37,Frontend WDR LUT" hexmask.long.word 0x2B0 0.--15. 1. "VAL,LUT Value" line.long 0x2B4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_38,Frontend WDR LUT" hexmask.long.word 0x2B4 0.--15. 1. "VAL,LUT Value" line.long 0x2B8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_39,Frontend WDR LUT" hexmask.long.word 0x2B8 0.--15. 1. "VAL,LUT Value" line.long 0x2BC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_40,Frontend WDR LUT" hexmask.long.word 0x2BC 0.--15. 1. "VAL,LUT Value" line.long 0x2C0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_41,Frontend WDR LUT" hexmask.long.word 0x2C0 0.--15. 1. "VAL,LUT Value" line.long 0x2C4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_42,Frontend WDR LUT" hexmask.long.word 0x2C4 0.--15. 1. "VAL,LUT Value" line.long 0x2C8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_43,Frontend WDR LUT" hexmask.long.word 0x2C8 0.--15. 1. "VAL,LUT Value" line.long 0x2CC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_44,Frontend WDR LUT" hexmask.long.word 0x2CC 0.--15. 1. "VAL,LUT Value" line.long 0x2D0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_45,Frontend WDR LUT" hexmask.long.word 0x2D0 0.--15. 1. "VAL,LUT Value" line.long 0x2D4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_46,Frontend WDR LUT" hexmask.long.word 0x2D4 0.--15. 1. "VAL,LUT Value" line.long 0x2D8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_47,Frontend WDR LUT" hexmask.long.word 0x2D8 0.--15. 1. "VAL,LUT Value" line.long 0x2DC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_48,Frontend WDR LUT" hexmask.long.word 0x2DC 0.--15. 1. "VAL,LUT Value" line.long 0x2E0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_49,Frontend WDR LUT" hexmask.long.word 0x2E0 0.--15. 1. "VAL,LUT Value" line.long 0x2E4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_50,Frontend WDR LUT" hexmask.long.word 0x2E4 0.--15. 1. "VAL,LUT Value" line.long 0x2E8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_51,Frontend WDR LUT" hexmask.long.word 0x2E8 0.--15. 1. "VAL,LUT Value" line.long 0x2EC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_52,Frontend WDR LUT" hexmask.long.word 0x2EC 0.--15. 1. "VAL,LUT Value" line.long 0x2F0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_53,Frontend WDR LUT" hexmask.long.word 0x2F0 0.--15. 1. "VAL,LUT Value" line.long 0x2F4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_54,Frontend WDR LUT" hexmask.long.word 0x2F4 0.--15. 1. "VAL,LUT Value" line.long 0x2F8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_55,Frontend WDR LUT" hexmask.long.word 0x2F8 0.--15. 1. "VAL,LUT Value" line.long 0x2FC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_56,Frontend WDR LUT" hexmask.long.word 0x2FC 0.--15. 1. "VAL,LUT Value" line.long 0x300 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_57,Frontend WDR LUT" hexmask.long.word 0x300 0.--15. 1. "VAL,LUT Value" line.long 0x304 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_58,Frontend WDR LUT" hexmask.long.word 0x304 0.--15. 1. "VAL,LUT Value" line.long 0x308 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_59,Frontend WDR LUT" hexmask.long.word 0x308 0.--15. 1. "VAL,LUT Value" line.long 0x30C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_60,Frontend WDR LUT" hexmask.long.word 0x30C 0.--15. 1. "VAL,LUT Value" line.long 0x310 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_61,Frontend WDR LUT" hexmask.long.word 0x310 0.--15. 1. "VAL,LUT Value" line.long 0x314 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_62,Frontend WDR LUT" hexmask.long.word 0x314 0.--15. 1. "VAL,LUT Value" line.long 0x318 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_63,Frontend WDR LUT" hexmask.long.word 0x318 0.--15. 1. "VAL,LUT Value" line.long 0x31C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_64,Frontend WDR LUT" hexmask.long.word 0x31C 0.--15. 1. "VAL,LUT Value" line.long 0x320 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_65,Frontend WDR LUT" hexmask.long.word 0x320 0.--15. 1. "VAL,LUT Value" line.long 0x324 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_66,Frontend WDR LUT" hexmask.long.word 0x324 0.--15. 1. "VAL,LUT Value" line.long 0x328 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_67,Frontend WDR LUT" hexmask.long.word 0x328 0.--15. 1. "VAL,LUT Value" line.long 0x32C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_68,Frontend WDR LUT" hexmask.long.word 0x32C 0.--15. 1. "VAL,LUT Value" line.long 0x330 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_69,Frontend WDR LUT" hexmask.long.word 0x330 0.--15. 1. "VAL,LUT Value" line.long 0x334 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_70,Frontend WDR LUT" hexmask.long.word 0x334 0.--15. 1. "VAL,LUT Value" line.long 0x338 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_71,Frontend WDR LUT" hexmask.long.word 0x338 0.--15. 1. "VAL,LUT Value" line.long 0x33C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_72,Frontend WDR LUT" hexmask.long.word 0x33C 0.--15. 1. "VAL,LUT Value" line.long 0x340 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_73,Frontend WDR LUT" hexmask.long.word 0x340 0.--15. 1. "VAL,LUT Value" line.long 0x344 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_74,Frontend WDR LUT" hexmask.long.word 0x344 0.--15. 1. "VAL,LUT Value" line.long 0x348 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_75,Frontend WDR LUT" hexmask.long.word 0x348 0.--15. 1. "VAL,LUT Value" line.long 0x34C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_76,Frontend WDR LUT" hexmask.long.word 0x34C 0.--15. 1. "VAL,LUT Value" line.long 0x350 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_77,Frontend WDR LUT" hexmask.long.word 0x350 0.--15. 1. "VAL,LUT Value" line.long 0x354 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_78,Frontend WDR LUT" hexmask.long.word 0x354 0.--15. 1. "VAL,LUT Value" line.long 0x358 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_79,Frontend WDR LUT" hexmask.long.word 0x358 0.--15. 1. "VAL,LUT Value" line.long 0x35C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_80,Frontend WDR LUT" hexmask.long.word 0x35C 0.--15. 1. "VAL,LUT Value" line.long 0x360 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_81,Frontend WDR LUT" hexmask.long.word 0x360 0.--15. 1. "VAL,LUT Value" line.long 0x364 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_82,Frontend WDR LUT" hexmask.long.word 0x364 0.--15. 1. "VAL,LUT Value" line.long 0x368 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_83,Frontend WDR LUT" hexmask.long.word 0x368 0.--15. 1. "VAL,LUT Value" line.long 0x36C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_84,Frontend WDR LUT" hexmask.long.word 0x36C 0.--15. 1. "VAL,LUT Value" line.long 0x370 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_85,Frontend WDR LUT" hexmask.long.word 0x370 0.--15. 1. "VAL,LUT Value" line.long 0x374 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_86,Frontend WDR LUT" hexmask.long.word 0x374 0.--15. 1. "VAL,LUT Value" line.long 0x378 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_87,Frontend WDR LUT" hexmask.long.word 0x378 0.--15. 1. "VAL,LUT Value" line.long 0x37C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_88,Frontend WDR LUT" hexmask.long.word 0x37C 0.--15. 1. "VAL,LUT Value" line.long 0x380 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_89,Frontend WDR LUT" hexmask.long.word 0x380 0.--15. 1. "VAL,LUT Value" line.long 0x384 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_90,Frontend WDR LUT" hexmask.long.word 0x384 0.--15. 1. "VAL,LUT Value" line.long 0x388 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_91,Frontend WDR LUT" hexmask.long.word 0x388 0.--15. 1. "VAL,LUT Value" line.long 0x38C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_92,Frontend WDR LUT" hexmask.long.word 0x38C 0.--15. 1. "VAL,LUT Value" line.long 0x390 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_93,Frontend WDR LUT" hexmask.long.word 0x390 0.--15. 1. "VAL,LUT Value" line.long 0x394 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_94,Frontend WDR LUT" hexmask.long.word 0x394 0.--15. 1. "VAL,LUT Value" line.long 0x398 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_95,Frontend WDR LUT" hexmask.long.word 0x398 0.--15. 1. "VAL,LUT Value" line.long 0x39C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_96,Frontend WDR LUT" hexmask.long.word 0x39C 0.--15. 1. "VAL,LUT Value" line.long 0x3A0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_97,Frontend WDR LUT" hexmask.long.word 0x3A0 0.--15. 1. "VAL,LUT Value" line.long 0x3A4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_98,Frontend WDR LUT" hexmask.long.word 0x3A4 0.--15. 1. "VAL,LUT Value" line.long 0x3A8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_99,Frontend WDR LUT" hexmask.long.word 0x3A8 0.--15. 1. "VAL,LUT Value" line.long 0x3AC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_100,Frontend WDR LUT" hexmask.long.word 0x3AC 0.--15. 1. "VAL,LUT Value" line.long 0x3B0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_101,Frontend WDR LUT" hexmask.long.word 0x3B0 0.--15. 1. "VAL,LUT Value" line.long 0x3B4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_102,Frontend WDR LUT" hexmask.long.word 0x3B4 0.--15. 1. "VAL,LUT Value" line.long 0x3B8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_103,Frontend WDR LUT" hexmask.long.word 0x3B8 0.--15. 1. "VAL,LUT Value" line.long 0x3BC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_104,Frontend WDR LUT" hexmask.long.word 0x3BC 0.--15. 1. "VAL,LUT Value" line.long 0x3C0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_105,Frontend WDR LUT" hexmask.long.word 0x3C0 0.--15. 1. "VAL,LUT Value" line.long 0x3C4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_106,Frontend WDR LUT" hexmask.long.word 0x3C4 0.--15. 1. "VAL,LUT Value" line.long 0x3C8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_107,Frontend WDR LUT" hexmask.long.word 0x3C8 0.--15. 1. "VAL,LUT Value" line.long 0x3CC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_108,Frontend WDR LUT" hexmask.long.word 0x3CC 0.--15. 1. "VAL,LUT Value" line.long 0x3D0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_109,Frontend WDR LUT" hexmask.long.word 0x3D0 0.--15. 1. "VAL,LUT Value" line.long 0x3D4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_110,Frontend WDR LUT" hexmask.long.word 0x3D4 0.--15. 1. "VAL,LUT Value" line.long 0x3D8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_111,Frontend WDR LUT" hexmask.long.word 0x3D8 0.--15. 1. "VAL,LUT Value" line.long 0x3DC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_112,Frontend WDR LUT" hexmask.long.word 0x3DC 0.--15. 1. "VAL,LUT Value" line.long 0x3E0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_113,Frontend WDR LUT" hexmask.long.word 0x3E0 0.--15. 1. "VAL,LUT Value" line.long 0x3E4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_114,Frontend WDR LUT" hexmask.long.word 0x3E4 0.--15. 1. "VAL,LUT Value" line.long 0x3E8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_115,Frontend WDR LUT" hexmask.long.word 0x3E8 0.--15. 1. "VAL,LUT Value" line.long 0x3EC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_116,Frontend WDR LUT" hexmask.long.word 0x3EC 0.--15. 1. "VAL,LUT Value" line.long 0x3F0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_117,Frontend WDR LUT" hexmask.long.word 0x3F0 0.--15. 1. "VAL,LUT Value" line.long 0x3F4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_118,Frontend WDR LUT" hexmask.long.word 0x3F4 0.--15. 1. "VAL,LUT Value" line.long 0x3F8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_119,Frontend WDR LUT" hexmask.long.word 0x3F8 0.--15. 1. "VAL,LUT Value" line.long 0x3FC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_120,Frontend WDR LUT" hexmask.long.word 0x3FC 0.--15. 1. "VAL,LUT Value" line.long 0x400 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_121,Frontend WDR LUT" hexmask.long.word 0x400 0.--15. 1. "VAL,LUT Value" line.long 0x404 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_122,Frontend WDR LUT" hexmask.long.word 0x404 0.--15. 1. "VAL,LUT Value" line.long 0x408 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_123,Frontend WDR LUT" hexmask.long.word 0x408 0.--15. 1. "VAL,LUT Value" line.long 0x40C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_124,Frontend WDR LUT" hexmask.long.word 0x40C 0.--15. 1. "VAL,LUT Value" line.long 0x410 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_125,Frontend WDR LUT" hexmask.long.word 0x410 0.--15. 1. "VAL,LUT Value" line.long 0x414 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_126,Frontend WDR LUT" hexmask.long.word 0x414 0.--15. 1. "VAL,LUT Value" line.long 0x418 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_127,Frontend WDR LUT" hexmask.long.word 0x418 0.--15. 1. "VAL,LUT Value" line.long 0x41C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_128,Frontend WDR LUT" hexmask.long.word 0x41C 0.--15. 1. "VAL,LUT Value" line.long 0x420 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_129,Frontend WDR LUT" hexmask.long.word 0x420 0.--15. 1. "VAL,LUT Value" line.long 0x424 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_130,Frontend WDR LUT" hexmask.long.word 0x424 0.--15. 1. "VAL,LUT Value" line.long 0x428 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_131,Frontend WDR LUT" hexmask.long.word 0x428 0.--15. 1. "VAL,LUT Value" line.long 0x42C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_132,Frontend WDR LUT" hexmask.long.word 0x42C 0.--15. 1. "VAL,LUT Value" line.long 0x430 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_133,Frontend WDR LUT" hexmask.long.word 0x430 0.--15. 1. "VAL,LUT Value" line.long 0x434 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_134,Frontend WDR LUT" hexmask.long.word 0x434 0.--15. 1. "VAL,LUT Value" line.long 0x438 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_135,Frontend WDR LUT" hexmask.long.word 0x438 0.--15. 1. "VAL,LUT Value" line.long 0x43C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_136,Frontend WDR LUT" hexmask.long.word 0x43C 0.--15. 1. "VAL,LUT Value" line.long 0x440 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_137,Frontend WDR LUT" hexmask.long.word 0x440 0.--15. 1. "VAL,LUT Value" line.long 0x444 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_138,Frontend WDR LUT" hexmask.long.word 0x444 0.--15. 1. "VAL,LUT Value" line.long 0x448 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_139,Frontend WDR LUT" hexmask.long.word 0x448 0.--15. 1. "VAL,LUT Value" line.long 0x44C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_140,Frontend WDR LUT" hexmask.long.word 0x44C 0.--15. 1. "VAL,LUT Value" line.long 0x450 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_141,Frontend WDR LUT" hexmask.long.word 0x450 0.--15. 1. "VAL,LUT Value" line.long 0x454 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_142,Frontend WDR LUT" hexmask.long.word 0x454 0.--15. 1. "VAL,LUT Value" line.long 0x458 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_143,Frontend WDR LUT" hexmask.long.word 0x458 0.--15. 1. "VAL,LUT Value" line.long 0x45C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_144,Frontend WDR LUT" hexmask.long.word 0x45C 0.--15. 1. "VAL,LUT Value" line.long 0x460 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_145,Frontend WDR LUT" hexmask.long.word 0x460 0.--15. 1. "VAL,LUT Value" line.long 0x464 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_146,Frontend WDR LUT" hexmask.long.word 0x464 0.--15. 1. "VAL,LUT Value" line.long 0x468 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_147,Frontend WDR LUT" hexmask.long.word 0x468 0.--15. 1. "VAL,LUT Value" line.long 0x46C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_148,Frontend WDR LUT" hexmask.long.word 0x46C 0.--15. 1. "VAL,LUT Value" line.long 0x470 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_149,Frontend WDR LUT" hexmask.long.word 0x470 0.--15. 1. "VAL,LUT Value" line.long 0x474 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_150,Frontend WDR LUT" hexmask.long.word 0x474 0.--15. 1. "VAL,LUT Value" line.long 0x478 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_151,Frontend WDR LUT" hexmask.long.word 0x478 0.--15. 1. "VAL,LUT Value" line.long 0x47C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_152,Frontend WDR LUT" hexmask.long.word 0x47C 0.--15. 1. "VAL,LUT Value" line.long 0x480 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_153,Frontend WDR LUT" hexmask.long.word 0x480 0.--15. 1. "VAL,LUT Value" line.long 0x484 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_154,Frontend WDR LUT" hexmask.long.word 0x484 0.--15. 1. "VAL,LUT Value" line.long 0x488 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_155,Frontend WDR LUT" hexmask.long.word 0x488 0.--15. 1. "VAL,LUT Value" line.long 0x48C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_156,Frontend WDR LUT" hexmask.long.word 0x48C 0.--15. 1. "VAL,LUT Value" line.long 0x490 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_157,Frontend WDR LUT" hexmask.long.word 0x490 0.--15. 1. "VAL,LUT Value" line.long 0x494 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_158,Frontend WDR LUT" hexmask.long.word 0x494 0.--15. 1. "VAL,LUT Value" line.long 0x498 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_159,Frontend WDR LUT" hexmask.long.word 0x498 0.--15. 1. "VAL,LUT Value" line.long 0x49C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_160,Frontend WDR LUT" hexmask.long.word 0x49C 0.--15. 1. "VAL,LUT Value" line.long 0x4A0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_161,Frontend WDR LUT" hexmask.long.word 0x4A0 0.--15. 1. "VAL,LUT Value" line.long 0x4A4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_162,Frontend WDR LUT" hexmask.long.word 0x4A4 0.--15. 1. "VAL,LUT Value" line.long 0x4A8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_163,Frontend WDR LUT" hexmask.long.word 0x4A8 0.--15. 1. "VAL,LUT Value" line.long 0x4AC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_164,Frontend WDR LUT" hexmask.long.word 0x4AC 0.--15. 1. "VAL,LUT Value" line.long 0x4B0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_165,Frontend WDR LUT" hexmask.long.word 0x4B0 0.--15. 1. "VAL,LUT Value" line.long 0x4B4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_166,Frontend WDR LUT" hexmask.long.word 0x4B4 0.--15. 1. "VAL,LUT Value" line.long 0x4B8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_167,Frontend WDR LUT" hexmask.long.word 0x4B8 0.--15. 1. "VAL,LUT Value" line.long 0x4BC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_168,Frontend WDR LUT" hexmask.long.word 0x4BC 0.--15. 1. "VAL,LUT Value" line.long 0x4C0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_169,Frontend WDR LUT" hexmask.long.word 0x4C0 0.--15. 1. "VAL,LUT Value" line.long 0x4C4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_170,Frontend WDR LUT" hexmask.long.word 0x4C4 0.--15. 1. "VAL,LUT Value" line.long 0x4C8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_171,Frontend WDR LUT" hexmask.long.word 0x4C8 0.--15. 1. "VAL,LUT Value" line.long 0x4CC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_172,Frontend WDR LUT" hexmask.long.word 0x4CC 0.--15. 1. "VAL,LUT Value" line.long 0x4D0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_173,Frontend WDR LUT" hexmask.long.word 0x4D0 0.--15. 1. "VAL,LUT Value" line.long 0x4D4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_174,Frontend WDR LUT" hexmask.long.word 0x4D4 0.--15. 1. "VAL,LUT Value" line.long 0x4D8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_175,Frontend WDR LUT" hexmask.long.word 0x4D8 0.--15. 1. "VAL,LUT Value" line.long 0x4DC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_176,Frontend WDR LUT" hexmask.long.word 0x4DC 0.--15. 1. "VAL,LUT Value" line.long 0x4E0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_177,Frontend WDR LUT" hexmask.long.word 0x4E0 0.--15. 1. "VAL,LUT Value" line.long 0x4E4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_178,Frontend WDR LUT" hexmask.long.word 0x4E4 0.--15. 1. "VAL,LUT Value" line.long 0x4E8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_179,Frontend WDR LUT" hexmask.long.word 0x4E8 0.--15. 1. "VAL,LUT Value" line.long 0x4EC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_180,Frontend WDR LUT" hexmask.long.word 0x4EC 0.--15. 1. "VAL,LUT Value" line.long 0x4F0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_181,Frontend WDR LUT" hexmask.long.word 0x4F0 0.--15. 1. "VAL,LUT Value" line.long 0x4F4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_182,Frontend WDR LUT" hexmask.long.word 0x4F4 0.--15. 1. "VAL,LUT Value" line.long 0x4F8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_183,Frontend WDR LUT" hexmask.long.word 0x4F8 0.--15. 1. "VAL,LUT Value" line.long 0x4FC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_184,Frontend WDR LUT" hexmask.long.word 0x4FC 0.--15. 1. "VAL,LUT Value" line.long 0x500 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_185,Frontend WDR LUT" hexmask.long.word 0x500 0.--15. 1. "VAL,LUT Value" line.long 0x504 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_186,Frontend WDR LUT" hexmask.long.word 0x504 0.--15. 1. "VAL,LUT Value" line.long 0x508 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_187,Frontend WDR LUT" hexmask.long.word 0x508 0.--15. 1. "VAL,LUT Value" line.long 0x50C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_188,Frontend WDR LUT" hexmask.long.word 0x50C 0.--15. 1. "VAL,LUT Value" line.long 0x510 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_189,Frontend WDR LUT" hexmask.long.word 0x510 0.--15. 1. "VAL,LUT Value" line.long 0x514 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_190,Frontend WDR LUT" hexmask.long.word 0x514 0.--15. 1. "VAL,LUT Value" line.long 0x518 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_191,Frontend WDR LUT" hexmask.long.word 0x518 0.--15. 1. "VAL,LUT Value" line.long 0x51C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_192,Frontend WDR LUT" hexmask.long.word 0x51C 0.--15. 1. "VAL,LUT Value" line.long 0x520 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_193,Frontend WDR LUT" hexmask.long.word 0x520 0.--15. 1. "VAL,LUT Value" line.long 0x524 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_194,Frontend WDR LUT" hexmask.long.word 0x524 0.--15. 1. "VAL,LUT Value" line.long 0x528 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_195,Frontend WDR LUT" hexmask.long.word 0x528 0.--15. 1. "VAL,LUT Value" line.long 0x52C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_196,Frontend WDR LUT" hexmask.long.word 0x52C 0.--15. 1. "VAL,LUT Value" line.long 0x530 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_197,Frontend WDR LUT" hexmask.long.word 0x530 0.--15. 1. "VAL,LUT Value" line.long 0x534 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_198,Frontend WDR LUT" hexmask.long.word 0x534 0.--15. 1. "VAL,LUT Value" line.long 0x538 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_199,Frontend WDR LUT" hexmask.long.word 0x538 0.--15. 1. "VAL,LUT Value" line.long 0x53C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_200,Frontend WDR LUT" hexmask.long.word 0x53C 0.--15. 1. "VAL,LUT Value" line.long 0x540 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_201,Frontend WDR LUT" hexmask.long.word 0x540 0.--15. 1. "VAL,LUT Value" line.long 0x544 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_202,Frontend WDR LUT" hexmask.long.word 0x544 0.--15. 1. "VAL,LUT Value" line.long 0x548 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_203,Frontend WDR LUT" hexmask.long.word 0x548 0.--15. 1. "VAL,LUT Value" line.long 0x54C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_204,Frontend WDR LUT" hexmask.long.word 0x54C 0.--15. 1. "VAL,LUT Value" line.long 0x550 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_205,Frontend WDR LUT" hexmask.long.word 0x550 0.--15. 1. "VAL,LUT Value" line.long 0x554 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_206,Frontend WDR LUT" hexmask.long.word 0x554 0.--15. 1. "VAL,LUT Value" line.long 0x558 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_207,Frontend WDR LUT" hexmask.long.word 0x558 0.--15. 1. "VAL,LUT Value" line.long 0x55C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_208,Frontend WDR LUT" hexmask.long.word 0x55C 0.--15. 1. "VAL,LUT Value" line.long 0x560 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_209,Frontend WDR LUT" hexmask.long.word 0x560 0.--15. 1. "VAL,LUT Value" line.long 0x564 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_210,Frontend WDR LUT" hexmask.long.word 0x564 0.--15. 1. "VAL,LUT Value" line.long 0x568 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_211,Frontend WDR LUT" hexmask.long.word 0x568 0.--15. 1. "VAL,LUT Value" line.long 0x56C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_212,Frontend WDR LUT" hexmask.long.word 0x56C 0.--15. 1. "VAL,LUT Value" line.long 0x570 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_213,Frontend WDR LUT" hexmask.long.word 0x570 0.--15. 1. "VAL,LUT Value" line.long 0x574 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_214,Frontend WDR LUT" hexmask.long.word 0x574 0.--15. 1. "VAL,LUT Value" line.long 0x578 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_215,Frontend WDR LUT" hexmask.long.word 0x578 0.--15. 1. "VAL,LUT Value" line.long 0x57C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_216,Frontend WDR LUT" hexmask.long.word 0x57C 0.--15. 1. "VAL,LUT Value" line.long 0x580 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_217,Frontend WDR LUT" hexmask.long.word 0x580 0.--15. 1. "VAL,LUT Value" line.long 0x584 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_218,Frontend WDR LUT" hexmask.long.word 0x584 0.--15. 1. "VAL,LUT Value" line.long 0x588 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_219,Frontend WDR LUT" hexmask.long.word 0x588 0.--15. 1. "VAL,LUT Value" line.long 0x58C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_220,Frontend WDR LUT" hexmask.long.word 0x58C 0.--15. 1. "VAL,LUT Value" line.long 0x590 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_221,Frontend WDR LUT" hexmask.long.word 0x590 0.--15. 1. "VAL,LUT Value" line.long 0x594 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_222,Frontend WDR LUT" hexmask.long.word 0x594 0.--15. 1. "VAL,LUT Value" line.long 0x598 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_223,Frontend WDR LUT" hexmask.long.word 0x598 0.--15. 1. "VAL,LUT Value" line.long 0x59C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_224,Frontend WDR LUT" hexmask.long.word 0x59C 0.--15. 1. "VAL,LUT Value" line.long 0x5A0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_225,Frontend WDR LUT" hexmask.long.word 0x5A0 0.--15. 1. "VAL,LUT Value" line.long 0x5A4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_226,Frontend WDR LUT" hexmask.long.word 0x5A4 0.--15. 1. "VAL,LUT Value" line.long 0x5A8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_227,Frontend WDR LUT" hexmask.long.word 0x5A8 0.--15. 1. "VAL,LUT Value" line.long 0x5AC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_228,Frontend WDR LUT" hexmask.long.word 0x5AC 0.--15. 1. "VAL,LUT Value" line.long 0x5B0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_229,Frontend WDR LUT" hexmask.long.word 0x5B0 0.--15. 1. "VAL,LUT Value" line.long 0x5B4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_230,Frontend WDR LUT" hexmask.long.word 0x5B4 0.--15. 1. "VAL,LUT Value" line.long 0x5B8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_231,Frontend WDR LUT" hexmask.long.word 0x5B8 0.--15. 1. "VAL,LUT Value" line.long 0x5BC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_232,Frontend WDR LUT" hexmask.long.word 0x5BC 0.--15. 1. "VAL,LUT Value" line.long 0x5C0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_233,Frontend WDR LUT" hexmask.long.word 0x5C0 0.--15. 1. "VAL,LUT Value" line.long 0x5C4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_234,Frontend WDR LUT" hexmask.long.word 0x5C4 0.--15. 1. "VAL,LUT Value" line.long 0x5C8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_235,Frontend WDR LUT" hexmask.long.word 0x5C8 0.--15. 1. "VAL,LUT Value" line.long 0x5CC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_236,Frontend WDR LUT" hexmask.long.word 0x5CC 0.--15. 1. "VAL,LUT Value" line.long 0x5D0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_237,Frontend WDR LUT" hexmask.long.word 0x5D0 0.--15. 1. "VAL,LUT Value" line.long 0x5D4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_238,Frontend WDR LUT" hexmask.long.word 0x5D4 0.--15. 1. "VAL,LUT Value" line.long 0x5D8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_239,Frontend WDR LUT" hexmask.long.word 0x5D8 0.--15. 1. "VAL,LUT Value" line.long 0x5DC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_240,Frontend WDR LUT" hexmask.long.word 0x5DC 0.--15. 1. "VAL,LUT Value" line.long 0x5E0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_241,Frontend WDR LUT" hexmask.long.word 0x5E0 0.--15. 1. "VAL,LUT Value" line.long 0x5E4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_242,Frontend WDR LUT" hexmask.long.word 0x5E4 0.--15. 1. "VAL,LUT Value" line.long 0x5E8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_243,Frontend WDR LUT" hexmask.long.word 0x5E8 0.--15. 1. "VAL,LUT Value" line.long 0x5EC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_244,Frontend WDR LUT" hexmask.long.word 0x5EC 0.--15. 1. "VAL,LUT Value" line.long 0x5F0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_245,Frontend WDR LUT" hexmask.long.word 0x5F0 0.--15. 1. "VAL,LUT Value" line.long 0x5F4 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_246,Frontend WDR LUT" hexmask.long.word 0x5F4 0.--15. 1. "VAL,LUT Value" line.long 0x5F8 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_247,Frontend WDR LUT" hexmask.long.word 0x5F8 0.--15. 1. "VAL,LUT Value" line.long 0x5FC "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_248,Frontend WDR LUT" hexmask.long.word 0x5FC 0.--15. 1. "VAL,LUT Value" line.long 0x600 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_249,Frontend WDR LUT" hexmask.long.word 0x600 0.--15. 1. "VAL,LUT Value" line.long 0x604 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_250,Frontend WDR LUT" hexmask.long.word 0x604 0.--15. 1. "VAL,LUT Value" line.long 0x608 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_251,Frontend WDR LUT" hexmask.long.word 0x608 0.--15. 1. "VAL,LUT Value" line.long 0x60C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_252,Frontend WDR LUT" hexmask.long.word 0x60C 0.--15. 1. "VAL,LUT Value" line.long 0x610 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_253,Frontend WDR LUT" hexmask.long.word 0x610 0.--15. 1. "VAL,LUT Value" line.long 0x614 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_254,Frontend WDR LUT" hexmask.long.word 0x614 0.--15. 1. "VAL,LUT Value" line.long 0x618 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_255,Frontend WDR LUT" hexmask.long.word 0x618 0.--15. 1. "VAL,LUT Value" line.long 0x61C "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_256,Frontend WDR LUT" hexmask.long.word 0x61C 0.--15. 1. "VAL,LUT Value" line.long 0x620 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_TILE_OUT_POS,Tile processing signals" hexmask.long.word 0x620 16.--31. 1. "TOP,Tile Top position" hexmask.long.word 0x620 0.--15. 1. "LEFT,Tile Left position" rgroup.long 0x6E0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_TILE_OUT_SIZE,Tile processing signals" hexmask.long.word 0x0 16.--31. 1. "HEIGHT,Tile Height" hexmask.long.word 0x0 0.--15. 1. "WIDTH,Tile Width" rgroup.long 0x6E8++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_TILE_CONTROL,Tile Processing Control register" bitfld.long 0x0 4. "LAST,Last time" "0,1" bitfld.long 0x0 3. "COLLECTION_DISABLE,Statistics collection disable" "0,1" newline bitfld.long 0x0 2. "UPDATE_DSABLE,Statistics update disable" "0,1" bitfld.long 0x0 0. "ENABLE,Tile processing Enable" "0,1" rgroup.long 0x6EC++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_OUTPUT_FLAGS,Tile status register" hexmask.long.word 0x0 0.--15. 1. "TILE_STATUS,Tile Status" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_K3_GLBCE_TOP_STATMEM_CFG_GLBCE_STATMEM (VPAC0_PAR_VPAC_VISS0_S_VBUSP_K3_GLBCE_TOP_STATMEM_CFG_GLBCE_STATMEM)" base ad:0x3904000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__STATMEM_CFG__GLBCE_STATMEM_statmem,odd and even banks are combined for one 32-bit access" hexmask.long.word 0x0 16.--31. 1. "ODD,Odd bank" hexmask.long.word 0x0 0.--15. 1. "EVEN,Even bank" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP (VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP)" base ad:0x3900000 rgroup.long 0x0++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_REVISION_REG,VISS PID" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and new scheme. Spare bit to encode future schemes" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU indicator DSPS ==> 0x0 WTBU ==> 0x1 Processors ==> 0x2" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family. If there is no level of software compatibility a new FUNC number and hence PID should be assigned." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version. R as described in PDR with additional clarifications and definitions below. Must be easily ECO-able or controlled during fabrication. Ideally through a top level metal mask or e-fuse. This number is maintained/owned by IP design.." newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision. X as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. X is part of IP numbering X.Y.R.Z. X changes ONLY when: (1) There is a major feature addition. An.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library (CSL) / Drivers. 0 if non-custom." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision. Y as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. Y changes ONLY when: (1) Features are scaled (up or down). Flexibility exists in that this.." line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_VISS_FUSE_STATUS,Register captures the Fuse control status. Shouldn't be captured into TRM" bitfld.long 0x4 1. "NIKON_DISABLE,Availability of NIKON specific feature HW in H3A. '0' -> Nikon features are available '1' -> Nikon features are not available" "0,1" newline bitfld.long 0x4 0. "GLBCE_DISABLE,Availability GLBCE HW. '0' -> GLBCE function HW is available '1' -> GLBCE function HW is not available" "0,1" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_VISS_LINEMEM_SIZE,Captures the no. of pixels per line supported by the VISS" hexmask.long.word 0x8 0.--13. 1. "LINEMEM_SZ,No. of pixels per line supported by the VISS HWAs Memories" rgroup.long 0xC++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_SYSCONFIG,system Configuration" bitfld.long 0x0 1. "CLKCG_OVERIDE,Reserved for this HW version" "0,1" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_VISS_CNTL,VISS top control" bitfld.long 0x4 2. "CAC_EN,'1' -> CAC is ON '0' -> CAC is off i.e. bypass CAC. Read the bit status for completion of write. Even when '0' Configuration access to CAC will be successful." "0,1" newline bitfld.long 0x4 1. "NSF4V_EN,'1' -> NSF4V is ON '0' -> NSF4V is off i.e. bypass NSF4V. Read the bit status for completion of write. Even when '0' Configuration access to NSF4V will be successful." "0,1" newline bitfld.long 0x4 0. "GLBCE_EN,'1' -> GLBCE is ON '0' -> GLBCE is off i.e. bypass GLBCE. Read the bit status for completion of write. When '0' Configuration access to GLBCE End points (MMR Statastics memory ) will result in Error response." "0,1" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_FREEPCLK_CFG,Register to control and configure Free running pixel clock to whole VISS pipe line" hexmask.long.word 0x8 16.--28. 1. "CNTVAL,Number of free pixel clocks to be provided" newline rbitfld.long 0x8 1. "PCLKFREE_STATE,Status of Free running pixel clock state. 0 - Free running pixel Clock is not being provided currently 1 - Free running pixel Clock is getting provided" "0: Free running pixel Clock is not being provided..,?" newline bitfld.long 0x8 0. "PCLKFREE_EN,Enable to provide Free running pixel clocks at the end of frame for VISS data pipe line. Needs to be enabled before end of a frame to provide free running pixel clock after that particular frame" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_FCP2_CNTL,FCP2 Input Control register" hexmask.long.byte 0x0 16.--23. 1. "IN_PIPEDLY,No. of pixel clock pipe delay on FCP2 input Vport. Used for matching with horizontal delay upto FCP Input" newline bitfld.long 0x0 1.--2. "IN_SEL,Input path to FCP2. 0 - RFE output 1 - NSF4V output 2 - GLBCE output 3 - CAC output" "0: RFE output 1,?,2: GLBCE output 3,?" newline bitfld.long 0x0 0. "PIXCLK_EN,Enable for FCP2 Pixel clock. 0 - FCP2 Pixel clock gated 1 - Pixel clock is enabled for FCP2" "0: FCP2 Pixel clock gated 1,?" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_LSEOUT_MUX_CNTL,FCP2 Input Control register" bitfld.long 0x4 16.--17. "S8SEL,LSE[4] - S8 output channel driver. 0 - FCP S8 Channel 1 - FCP2 S8 Channel Others - In valid" "0: FCP S8 Channel 1,?,?,?" newline bitfld.long 0x4 12.--14. "UV8SEL,LSE[3] - UV8 output channel driver. 0 - FCP UV12 Channel 1 - FCP2 UV12 Channel 2 - FCP UV8 Channel 3 - FCP2 UV8 Channel Others - In valid" "0: FCP UV12 Channel 1,?,2: FCP UV8 Channel 3,?,?,?,?,?" newline bitfld.long 0x4 8.--10. "Y8SEL,LSE[2] - Y8 output channel driver. 0 - FCP Y12 Channel 1 - FCP2 Y12 Channel 2 - FCP Y8 Channel 3 - FCP2 Y8 Channel Others - In valid" "0: FCP Y12 Channel 1,?,2: FCP Y8 Channel 3,?,?,?,?,?" newline bitfld.long 0x4 4.--6. "UV12SEL,LSE[1] - UV12 output channel driver. 0 - FCP UV12 Channel 1 - FCP2 UV12 Channel 2 - FCP UV8 Channel 3 - FCP2 UV8 Channel Others - In valid" "0: FCP UV12 Channel 1,?,2: FCP UV8 Channel 3,?,?,?,?,?" newline bitfld.long 0x4 0.--2. "Y12SEL,LSE[0] - Y12 output channel driver. 0 - FCP Y12 Channel 1 - FCP2 Y12 Channel 2 - FCP Y8 Channel 3 - FCP2 Y8 Channel Others - In valid" "0: FCP Y12 Channel 1,?,2: FCP Y8 Channel 3,?,?,?,?,?" rgroup.long 0x80++0x7 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_VISS_DBG_CTL,Enable for VISS debug staus capture" bitfld.long 0x0 1. "PRTL_WR_EN,Enable to Capture Partial Write to any VISS end point" "0,1" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_VISS_DBG_STAT,Set/Clear for VISS debug status" bitfld.long 0x4 1. "PRTL_WR,Status/Clear for Partial Write to any VISS end point. Set on Partial Write at VISS_Top input Cfg interface" "0,1" rgroup.long 0x100++0x13 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_GLBCECONFIG,GLBCE Configuration" bitfld.long 0x0 0. "GLBCE_PCLKFREE,'1'-> GLBCE pclk is free running '0' -> GLBCE pclk is gated pixel clock" "0,1" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_GLBCE_VPSYNCDLY,Delay of GLBCE Core. used to regenerate VS/VE VPORT signals" hexmask.long.byte 0x4 8.--15. 1. "V_DLY,Line delay between GLBCE.VS_In to GLBCE.VS_Out" newline hexmask.long.byte 0x4 0.--7. 1. "H_DLY,Cycle delay between GLBCE.HS_In to GLBCE.HS_Out minus 1" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_GLBCE_INT_STAT,Set on internal interutp event and clr by SW" bitfld.long 0x8 6. "VSYNC_ERR,status/clear for GLBCE VSYNC Delay programmation error. Set Delayed sync signals doesn't match with sync signal generated from GLBCE Core" "0,1" newline bitfld.long 0x8 5. "HSYNC_ERR,status/clear for GLBCE HSYNC Delay programmation error. Set Delayed sync signals doesn't match with sync signal generated from GLBCE Core" "0,1" newline bitfld.long 0x8 4. "VP_ERR,status/clear for GLBCE Input frame start error. Set Input frame is started while filtering is going on" "0,1" newline bitfld.long 0x8 3. "FILT_DONE,status/clear for GLBCE Filtering Done event. Set when GLBCE Filtering is completed." "0,1" newline bitfld.long 0x8 2. "FILT_START,status/clear for GLBCE Filtering Start event. Set when GLBCE Filtering starts" "0,1" newline bitfld.long 0x8 1. "STATMEM_CFG_ERR,status/clear for statastics memory configuration error. Set when access happen to statastics memory in the middle of processing" "0,1" newline bitfld.long 0x8 0. "MMR_CFG_ERR,status/clear for mmr configuration error. Set when writes happen to non-shadowed registers in the middle of processing" "0,1" line.long 0xC "PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_GLBCE_DBG_CTL,Enable for GLBCE debug events" bitfld.long 0xC 4. "EOF_EN,Enable for EOF at GLBCE output" "0,1" newline bitfld.long 0xC 3. "EOL_EN,Enable for EOL at GLBCE output" "0,1" newline bitfld.long 0xC 2. "SOF_EN,Enable for SOF at GLBCE input" "0,1" newline bitfld.long 0xC 1. "SOL_EN,Enable for SOL at GLBCE input" "0,1" newline bitfld.long 0xC 0. "DBG_EN,Enable debug features set to '0' to disable all debug events" "0,1" line.long 0x10 "PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_GLBCE_DBG_STAT,Set/Clear for GLBCE debug events" bitfld.long 0x10 4. "EOF,Status/Clear for EOF at GLBCE output. Set on EOF at GLBCE output" "0,1" newline bitfld.long 0x10 3. "EOL,Status/Clear for EOL at GLBCE output. Set on EOL at GLBCE output" "0,1" newline bitfld.long 0x10 2. "SOF,Status/Clear for SOF at GLBCE input. Set on SOF at GLBCE input" "0,1" newline bitfld.long 0x10 1. "SOL,Status/Clear for SOL at GLBCE input. Set on SOL at GLBCE input" "0,1" rgroup.long 0x180++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_NSF4V_INT_STAT,Set on internal interutp event and clr by SW" bitfld.long 0x0 4. "VBLANK_ERR,status/clear for Vorizontal Blanking Error. Set when Vertical Blanking too short between frames" "0,1" newline bitfld.long 0x0 3. "HBLANK_ERR,status/clear for Horizontal Blanking Error. Set when Horzontal Blanking too short between lines" "0,1" newline bitfld.long 0x0 2. "RAWHIST_CFG_ERR,status/clear for RawHistogram Read incomplete. Set when SW starts reading Raw Histogram data (read from location '0') but didn't complete (read from '127' location) before end of next frame" "0,1" newline bitfld.long 0x0 1. "LUT_CFG_ERR,status/clear for Histogram LUT memory configuration error. Set VBUSP access of RAM while NSF data path using LUT for functional purpose" "0,1" newline bitfld.long 0x0 0. "LINEMEM_CFG_ERR,status/clear for Line mem configuration error. Set when VBUSP diagnostic read access of RAM while NSF data path using RAM for functional purpose" "0,1" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_NSF4V_DBG_CTL,Enable for NSF4V debug events" bitfld.long 0x4 4. "EOF_EN,Enable for EOF at NSF4V output" "0,1" newline bitfld.long 0x4 3. "EOL_EN,Enable for EOL at NSF4V output" "0,1" newline bitfld.long 0x4 2. "SOF_EN,Enable for SOF at NSF4V input" "0,1" newline bitfld.long 0x4 1. "SOL_EN,Enable for SOL at NSF4V input" "0,1" newline bitfld.long 0x4 0. "DBG_EN,Enable debug features set to '0' to disable all debug events" "0,1" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_NSF4V_DBG_STAT,Set/Clear for NSF4V debug events" bitfld.long 0x8 4. "EOF,Status/Clear for EOF at NSF4V output. Set on EOF at NSF4V output" "0,1" newline bitfld.long 0x8 3. "EOL,Status/Clear for EOL at NSF4V output. Set on EOL at NSF4V output" "0,1" newline bitfld.long 0x8 2. "SOF,Status/Clear for SOF at NSF4V input. Set on SOF at NSF4V input" "0,1" newline bitfld.long 0x8 1. "SOL,Status/Clear for SOL at NSF4V input. Set on SOL at NSF4V input" "0,1" rgroup.long 0x1A0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_DBGEVT_CTL,Enable for NSF4V debug events" bitfld.long 0x0 4.--5. "SEL3,Mux select for GLBCE and CAC VPORT events. 0 - Select GLBCE events 1 - Select CAC events Common mux control for SOL SOF EOL and EOF events between the GLBCE and CAC" "0: Select GLBCE events 1,?,?,?" newline bitfld.long 0x0 2.--3. "SEL2,Mux select for CFA SOLs and FCP2 fcc_eop event. 0 - FCP.cfa_sof_event 1 - FCP2.cfa_sof_event 2 - FCP2.fcc_eop_event 3. Invalid" "0: FCP,1: FCP2,2: FCP2,?" newline bitfld.long 0x0 0.--1. "SEL1,Mux select for CFA SOLs and FCP2 fcc_stall event. 0 - FCP.cfa_sol_event 1 - FCP2.cfa_sol_event 2 - FCP2.fcc_stall_event 3. Invalid" "0: FCP,1: FCP2,2: FCP2,?" rgroup.long 0x1C0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_TEST_CNTL,Control register for TEST. Shouldn't be used in functional mode" bitfld.long 0x0 0. "GATED_MEM_CLKF,Control to force functional clock to H3A and CAC line memory for Pbist Config test. '1' - Free running functional clock is supplied to H3A line memory '0' - Gated Pixel clock is supplied in functional operation" "0,1" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_CAC_S_VBUSP_CORE_LUT_CFG_LUT_MEM (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_CAC_S_VBUSP_CORE_LUT_CFG_LUT_MEM)" base ad:0x3982000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_CAC__S_VBUSP__CORE__LUT_CFG__LUT_MEM_lut,Only full 32-bit access it allowed for ECC reasons" hexmask.long.byte 0x0 24.--31. 1. "ODD_DY,Vertical Displacement for Odd Line" hexmask.long.byte 0x0 16.--23. 1. "ODD_DX,Horizontal Displacement for Odd Line" hexmask.long.byte 0x0 8.--15. 1. "EVEN_DY,Vertical Displacement for Even Line starting with '0'" hexmask.long.byte 0x0 0.--7. 1. "EVEN_DX,Horizontal Displacement for Even Line starting with '0'" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_CAC_S_VBUSP_LINEMEM_CFG_LINE_MEM (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_CAC_S_VBUSP_LINEMEM_CFG_LINE_MEM)" base ad:0x3984000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_CAC__S_VBUSP____LINEMEM_CFG__LINE_MEM_MEM,Only full 32-bit access it allowed" hexmask.long 0x0 0.--31. 1. "PIXD,No Byte or Word Access. Only full 32-bit access it allowed" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_CAC_S_VBUSP_MMRCFG_CAC (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_CAC_S_VBUSP_MMRCFG_CAC)" base ad:0x3980000 rgroup.long 0x4++0xF line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_CAC__S_VBUSP__MMR__MMRCFG__CAC_REGS_CTRL,Control Register to Enable/Disable and select modes of operation" hexmask.long.byte 0x0 8.--11. 1. "COLOR_EN,Enable for CAC processing in 2x2 pixel grid. bit[0] - row[0]col[0] bit[1] - row[0]col[1] bit[2] - row[1]col[0] bit[3] - row[1]col[1]. One pixel should be enabled in each row of 2x2. 10 or 01 combinations are allowed in each row." line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_CAC__S_VBUSP__MMR__MMRCFG__CAC_REGS_FRAMESZ,Actual frame size is configured value + 1" hexmask.long.word 0x4 16.--28. 1. "HEIGHT,Number of Lines per frame. Actual Frame height is HEIGHT +1. Actual frame height should minimum of 32 and multiple of 2" hexmask.long.word 0x4 0.--12. 1. "WIDTH,Number of pixels per line. Actual Frame width is WIDTH +1. Actual frame width should minimum of 64 and multiple of 2" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_CAC__S_VBUSP__MMR__MMRCFG__CAC_REGS_BLOCKSZ,Size of Block and each block will have 2 LUT entries with displacement value" hexmask.long.byte 0x8 0.--7. 1. "SIZE,Height and Width of Subsampled Block. Each block will have 2 displacement entries for SIZExSIZE block ; one for even line and other for odd line. Minimum of 8 and maximum of 128. Should be multiple of 4" line.long 0xC "PAR_VPAC_VISS0__S_VBUSP__VISS_CAC__S_VBUSP__MMR__MMRCFG__CAC_REGS_BLOCKCNT,LUT Grid size. Should cover frame size plus 1 for interpolation. VCNT * HCNT <= 2048" hexmask.long.word 0xC 16.--25. 1. "VCNT,LUT Grid heighti i.e. no. of blocks in vertical direction. (VCNT-1)* BLOCKSZ.SIZE >= frame_height and max value is 512" hexmask.long.word 0xC 0.--9. 1. "HCNT,LUT Grid width i.e. no. of blocks in horizontal direction. (HCNT-1)* BLOCKSZ.SIZE >= frame_width and max value is 512" rgroup.long 0x80++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_CAC__S_VBUSP__MMR__MMRCFG__CAC_REGS_INT_STAT,Set on internal interupt event and clr by SW" bitfld.long 0x0 0. "LUT_CFG_ERR,status/clear for mmr configuration error. Set when Config access happen to LUT memory in the middle of processing" "0,1" rgroup.long 0x100++0x7 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_CAC__S_VBUSP__MMR__MMRCFG__CAC_REGS_DBG_CTL,Control the memory access selection" hexmask.long.byte 0x0 8.--11. 1. "LINEMEM_SEL,0-6: CAC corrected line memory. i.e. EnLine0..6 7-9: Bypassed pixel Line memory. i.e. BypLine0..2" bitfld.long 0x0 4. "EOF_EN,Enable for EOF at CAC output" "0,1" bitfld.long 0x0 3. "EOL_EN,Enable for EOL at CAC output" "0,1" bitfld.long 0x0 2. "SOF_EN,Enable for SOF at CAC input" "0,1" newline bitfld.long 0x0 1. "SOL_EN,Enable for SOL at CAC input" "0,1" bitfld.long 0x0 0. "DBG_EN,Enable debug features set to '0' to disable all debug events" "0,1" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_CAC__S_VBUSP__MMR__MMRCFG__CAC_REGS_DBG_STAT,Set/Clear for CAC debug events" bitfld.long 0x4 4. "EOF,Status/Clear for EOF at CAC output. Set on EOF at CAC output" "0,1" bitfld.long 0x4 3. "EOL,Status/Clear for EOL at CAC output. Set on EOL at CAC output" "0,1" bitfld.long 0x4 2. "SOF,Status/Clear for SOF at CAC input. Set on SOF at CAC input" "0,1" bitfld.long 0x4 1. "SOL,Status/Clear for SOL at CAC input. Set on SOL at CAC input" "0,1" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA)" base ad:0x3968000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_LUT,The LUT table contains the information used to reduce the pixle width to 12 from 13-16" hexmask.long.word 0x0 16.--31. 1. "LUT_ENTRY_HI,The upper LUT entry n+1." newline hexmask.long.word 0x0 0.--15. 1. "LUT_ENTRY_LO,The lower LUT entry n+0." rgroup.long 0x1004++0x7 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_CFG_0,The Control Register controls the input width and height of the module." hexmask.long.word 0x0 16.--28. 1. "HEIGHT,Height of the input image" newline hexmask.long.word 0x0 0.--12. 1. "WIDTH,Width of the input image" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_CFG_1,The Control Register identifies the bit width of the input image" bitfld.long 0x4 11. "BYPASS_CORE3,Setting the ~ibypass_core3 bit will bypass filtering operation output = input" "0,1" newline bitfld.long 0x4 10. "BYPASS_CORE2,Setting the ~ibypass_core2 bit will bypass filtering operation output = input" "0,1" newline bitfld.long 0x4 9. "BYPASS_CORE1,Setting the ~ibypass_core1 bit will bypass filtering operation output = input" "0,1" newline bitfld.long 0x4 8. "BYPASS_CORE0,Setting the ~ibypass_core0 bit will bypass filtering operation output = input" "0,1" newline bitfld.long 0x4 6. "EN16BITMODE,0->legacy mode 1->Enhanced 16 bit CFA mode enabled when LUT is disabled" "0: legacy mode,1: Enhanced 16 bit CFA mode" newline bitfld.long 0x4 5. "LUT_ENABLE,0->Use shift(bitwidth-12) 1->Use LUT" "0: Use shift,1: Use LUT" newline hexmask.long.byte 0x4 0.--4. 1. "BITWIDTH,BitWidth of the input image values greater than 16 will be treated as 16 and values less than 12 will be treated as 12." rgroup.long 0x1D8C++0x47 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_GRAD_CFG,Gradient configuration for all 4 cores" bitfld.long 0x0 25.--26. "BLENDMODECORE3,Core-3 Blend (0:Input-0 1: Input0/1 2: Input 0/1/2 3 : Adaptive Input0/1/2 )" "0: Input-0,1: Input0/1,2: Input 0/1/2,3: Adaptive Input0/1/2 )" newline bitfld.long 0x0 24. "BITMASKSELCORE3,Core-3 Bitmask Select (0: Set-0 1: Set-1)" "0: Set-0,1: Set-1)" newline bitfld.long 0x0 17.--18. "BLENDMODECORE2,Core-2 Blend (0:Input-0 1: Input0/1 2: Input 0/1/2 3 : Adaptive Input0/1/2 )" "0: Input-0,1: Input0/1,2: Input 0/1/2,3: Adaptive Input0/1/2 )" newline bitfld.long 0x0 16. "BITMASKSELCORE2,Core-2 Bitmask Select (0: Set-0 1: Set-1)" "0: Set-0,1: Set-1)" newline bitfld.long 0x0 9.--10. "BLENDMODECORE1,Core-1 Blend (0:Input-0 1: Input0/1 2: Input 0/1/2 3 : Adaptive Input0/1/2 )" "0: Input-0,1: Input0/1,2: Input 0/1/2,3: Adaptive Input0/1/2 )" newline bitfld.long 0x0 8. "BITMASKSELCORE1,Core-1 Bitmask Select (0: Set-0 1: Set-1)" "0: Set-0,1: Set-1)" newline bitfld.long 0x0 1.--2. "BLENDMODECORE0,Core-0 Blend (0:Input-0 1: Input0/1 2: Input 0/1/2 3 : Adaptive Input0/1/2 )" "0: Input-0,1: Input0/1,2: Input 0/1/2,3: Adaptive Input0/1/2 )" newline bitfld.long 0x0 0. "BITMASKSELCORE0,Core-0 Bitmask Select (0: Set-0 1: Set-1)" "0: Set-0,1: Set-1)" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_SET0_GRAD_HZ,Gradient Bitfield selector. Set-0 for Horizontal" hexmask.long.byte 0x4 24.--31. 1. "PHASE3,Bitfield selector for Phase-3" newline hexmask.long.byte 0x4 16.--23. 1. "PHASE2,Bitfield selector for Phase-2" newline hexmask.long.byte 0x4 8.--15. 1. "PHASE1,Bitfield selector for Phase-1" newline hexmask.long.byte 0x4 0.--7. 1. "PHASE0,Bitfield selector for Phase-0" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_SET0_GRAD_VT,Gradient Bitfield selector. Set-0 for Vertical" hexmask.long.byte 0x8 24.--31. 1. "PHASE3,Bitfield selector for Phase-3" newline hexmask.long.byte 0x8 16.--23. 1. "PHASE2,Bitfield selector for Phase-2" newline hexmask.long.byte 0x8 8.--15. 1. "PHASE1,Bitfield selector for Phase-1" newline hexmask.long.byte 0x8 0.--7. 1. "PHASE0,Bitfield selector for Phase-0" line.long 0xC "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_SET0_INTENSITY0,Intensity Bitfield selector and shift for phase0/1" hexmask.long.byte 0xC 28.--31. 1. "SHIFT_PH1,Intensity shift for Phase-1" newline hexmask.long.byte 0xC 16.--19. 1. "BITFIELD_PH1,Intensity Bitfield selector for Phase-1" newline hexmask.long.byte 0xC 12.--15. 1. "SHIFT_PH0,Intensity shift for Phase-0" newline hexmask.long.byte 0xC 0.--3. 1. "BITFIELD_PH0,Intensity Bitfield selector for Phase-0" line.long 0x10 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_SET0_INTENSITY1,Intensity Bitfield selector and shift for phase2/3" hexmask.long.byte 0x10 28.--31. 1. "SHIFT_PH3,Intensity shift for Phase-3" newline hexmask.long.byte 0x10 16.--19. 1. "BITFIELD_PH3,Intensity Bitfield selector for Phase-3" newline hexmask.long.byte 0x10 12.--15. 1. "SHIFT_PH2,Intensity shift for Phase-2" newline hexmask.long.byte 0x10 0.--3. 1. "BITFIELD_PH2,Intensity Bitfield selector for Phase-2" line.long 0x14 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_SET1_GRAD_HZ,Gradient Bitfield selector. Set-1 for Horizontal" hexmask.long.byte 0x14 24.--31. 1. "PHASE3,Bitfield selector for Phase-3" newline hexmask.long.byte 0x14 16.--23. 1. "PHASE2,Bitfield selector for Phase-2" newline hexmask.long.byte 0x14 8.--15. 1. "PHASE1,Bitfield selector for Phase-1" newline hexmask.long.byte 0x14 0.--7. 1. "PHASE0,Bitfield selector for Phase-0" line.long 0x18 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_SET1_GRAD_VT,Gradient Bitfield selector. Set-1 for Vertical" hexmask.long.byte 0x18 24.--31. 1. "PHASE3,Bitfield selector for Phase-3" newline hexmask.long.byte 0x18 16.--23. 1. "PHASE2,Bitfield selector for Phase-2" newline hexmask.long.byte 0x18 8.--15. 1. "PHASE1,Bitfield selector for Phase-1" newline hexmask.long.byte 0x18 0.--7. 1. "PHASE0,Bitfield selector for Phase-0" line.long 0x1C "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_SET1_INTENSITY0,Intensity Bitfield selector and shift for phase0/1" hexmask.long.byte 0x1C 28.--31. 1. "SHIFT_PH1,Intensity shift for Phase-1" newline hexmask.long.byte 0x1C 16.--19. 1. "BITFIELD_PH1,Intensity Bitfield selector for Phase-1" newline hexmask.long.byte 0x1C 12.--15. 1. "SHIFT_PH0,Intensity shift for Phase-0" newline hexmask.long.byte 0x1C 0.--3. 1. "BITFIELD_PH0,Intensity Bitfield selector for Phase-0" line.long 0x20 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_SET1_INTENSITY1,Intensity Bitfield selector and shift for phase2/3" hexmask.long.byte 0x20 28.--31. 1. "SHIFT_PH3,Intensity shift for Phase-3" newline hexmask.long.byte 0x20 16.--19. 1. "BITFIELD_PH3,Intensity Bitfield selector for Phase-3" newline hexmask.long.byte 0x20 12.--15. 1. "SHIFT_PH2,Intensity shift for Phase-2" newline hexmask.long.byte 0x20 0.--3. 1. "BITFIELD_PH2,Intensity Bitfield selector for Phase-2" line.long 0x24 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_SET0_THR0_1,Set0 Thr0_1 for H/V Grad difference" hexmask.long.word 0x24 16.--31. 1. "THR_1,H/V Grad diff Threshold_1" newline hexmask.long.word 0x24 0.--15. 1. "THR_0,H/V Grad diff Threshold_0" line.long 0x28 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_SET0_THR2_3,Set0 Thr2_3 for H/V Grad difference" hexmask.long.word 0x28 16.--31. 1. "THR_3,H/V Grad diff Threshold_3" newline hexmask.long.word 0x28 0.--15. 1. "THR_2,H/V Grad diff Threshold_2" line.long 0x2C "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_SET0_THR4_5,Set0 Thr4_5 for H/V Grad difference" hexmask.long.word 0x2C 16.--31. 1. "THR_5,H/V Grad diff Threshold_5" newline hexmask.long.word 0x2C 0.--15. 1. "THR_4,H/V Grad diff Threshold_4" line.long 0x30 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_SET0_THR6,Set0 Thr6 for H/V Grad difference" hexmask.long.word 0x30 0.--15. 1. "THR_6,H/V Grad diff Threshold_6" line.long 0x34 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_SET1_THR0_1,Set1 Thr0_1 for H/V Grad difference" hexmask.long.word 0x34 16.--31. 1. "THR_1,H/V Grad diff Threshold_1" newline hexmask.long.word 0x34 0.--15. 1. "THR_0,H/V Grad diff Threshold_0" line.long 0x38 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_SET1_THR2_3,Set1 Thr2_3 for H/V Grad difference" hexmask.long.word 0x38 16.--31. 1. "THR_3,H/V Grad diff Threshold_3" newline hexmask.long.word 0x38 0.--15. 1. "THR_2,H/V Grad diff Threshold_2" line.long 0x3C "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_SET1_THR4_5,Set1 Thr4_5 for H/V Grad difference" hexmask.long.word 0x3C 16.--31. 1. "THR_5,H/V Grad diff Threshold_5" newline hexmask.long.word 0x3C 0.--15. 1. "THR_4,H/V Grad diff Threshold_4" line.long 0x40 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_SET1_THR6,Set1 Thr6 for H/V Grad difference" hexmask.long.word 0x40 0.--15. 1. "THR_6,H/V Grad diff Threshold_6" line.long 0x44 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_INT_STATUS,Status/clear register for flexcfa interrupts" bitfld.long 0x44 4. "CLUT_CFG_ERR,status/clear for error on CLUT cfg set when software accesses CLUT during active frame causing potential frame corruption. Write 1 to clear write 0 has no effect." "0,1" newline bitfld.long 0x44 3. "DLUT_CFG_ERR,status/clear for error on DLUT cfg set when software accesses DLUT during active frame causing potential frame corruption. Write 1 to clear write 0 has no effect." "0,1" newline bitfld.long 0x44 2. "CFA_MMR_ERR,status/clear for error writes to the FIR Filter MMRs during active frame causing potential frame corruption. Write 1 to clear write 0 has no effect." "0,1" newline bitfld.long 0x44 1. "CFA_PIX_ERR,status/clear for error on line array set when software accesses pixel array during active frame causing potential frame corruption. Write 1 to clear write 0 has no effect." "0,1" newline bitfld.long 0x44 0. "LUT_CFG_ERR,status/clear for error on LUT cfg set when software accesses LUT during active frame causing potential frame corruption. Write 1 to clear write 0 has no effect." "0,1" rgroup.long 0x2000++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_DEBUG_CTL,Enable for different debug events" bitfld.long 0x0 2. "SOF_EN,Enable for sof event" "0,1" newline bitfld.long 0x0 1. "SOL_EN,Enable for sol event" "0,1" newline bitfld.long 0x0 0. "DBG_EN,Enable debug features set to '0' to disable all debug events" "0,1" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_DEBUG_STATUS,Set/Clear for debug events" bitfld.long 0x4 2. "SOF_EVENT,Status/Clear for sof event write '1' to clear" "0,1" newline bitfld.long 0x4 1. "SOL_EVENT,Status/Clear for sol event write '1' to clear" "0,1" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_LINE_SEL,Selector for which line memory is read or written" bitfld.long 0x8 0.--2. "LINE_SELECTOR,Selects which line is read or written from the line memory array. The current line is updated at Start-Of-Line so if the memory is read during a line that is being written the data for the current_line will contain the new data for this.." "?,?,2: current line,3: current line,4: current line,?,?,?" rgroup.long 0x2010++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_DANDC_COM_CTRL,This register handles the general conrtrol bits for the DLUT CCM and CLUT blocks that preceed the CC module in the FCP." bitfld.long 0x0 27. "DISFIR3,Disables the FIR filter for C3 to save power" "0,1" newline bitfld.long 0x0 26. "DISFIR2,Disables the FIR filter for C2 to save power" "0,1" newline bitfld.long 0x0 25. "DISFIR1,Disables the FIR filter for C1 to save power" "0,1" newline bitfld.long 0x0 24. "DISFIR0,Disables the FIR filter for C0 to save power" "0,1" newline bitfld.long 0x0 10. "CMPDLUTEN,Enables the CLUT" "0,1" newline bitfld.long 0x0 9. "CCMEN,Enables the CCM" "0,1" newline bitfld.long 0x0 8. "DCMPDLUTEN,Enables the DLUT" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "LINEARBITWIDTH,Defines the DLUT output bit width the CCM clipping bit width and the CLUT input bit width valid values are 12-24. Values less than 12 12 will be used values greater than 24 24 will be used. Useful combinations are 12/16/20/24" rgroup.long 0x2040++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH0_ICH1_0,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x0 16.--27. 1. "CCM_OCH0_ICH1,Defines the 12 bit signed wieght for the C0 output channel from the C1 input channel" newline hexmask.long.word 0x0 0.--11. 1. "CCM_OCH0_ICH0,Defines the 12 bit signed wieght for the C0 output channel from the C0 input channel" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH0_ICH3_2,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x4 16.--27. 1. "CCM_OCH0_ICH3,Defines the 12 bit signed wieght for the C0 output channel from the C3 input channel" newline hexmask.long.word 0x4 0.--11. 1. "CCM_OCH0_ICH2,Defines the 12 bit signed wieght for the C0 output channel from the C2 input channel" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH0_OFFSET,Defines the 26 bit signed S26Q24 offset for CCM" hexmask.long 0x8 0.--25. 1. "CCM_OCH0_OFFSET,Defines the 26 bit signed offset for the C0 output channel" rgroup.long 0x2050++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH1_ICH1_0,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x0 16.--27. 1. "CCM_OCH1_ICH1,Defines the 12 bit signed wieght for the C1 output channel from the C1 input channel" newline hexmask.long.word 0x0 0.--11. 1. "CCM_OCH1_ICH0,Defines the 12 bit signed wieght for the C1 output channel from the C0 input channel" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH1_ICH3_2,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x4 16.--27. 1. "CCM_OCH1_ICH3,Defines the 12 bit signed wieght for the C1 output channel from the C3 input channel" newline hexmask.long.word 0x4 0.--11. 1. "CCM_OCH1_ICH2,Defines the 12 bit signed wieght for the C1 output channel from the C2 input channel" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH1_OFFSET,Defines the 26 bit signed S26Q24 offset for CCM" hexmask.long 0x8 0.--25. 1. "CCM_OCH1_OFFSET,Defines the 26 bit signed offset for the C1 output channel" rgroup.long 0x2060++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH2_ICH1_0,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x0 16.--27. 1. "CCM_OCH2_ICH1,Defines the 12 bit signed wieght for the C2 output channel from the C1 input channel" newline hexmask.long.word 0x0 0.--11. 1. "CCM_OCH2_ICH0,Defines the 12 bit signed wieght for the C2 output channel from the C0 input channel" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH2_ICH3_2,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x4 16.--27. 1. "CCM_OCH2_ICH3,Defines the 12 bit signed wieght for the C2 output channel from the C3 input channel" newline hexmask.long.word 0x4 0.--11. 1. "CCM_OCH2_ICH2,Defines the 12 bit signed wieght for the C2 output channel from the C2 input channel" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH2_OFFSET,Defines the 26 bit signed S26Q24 offset for CCM" hexmask.long 0x8 0.--25. 1. "CCM_OCH2_OFFSET,Defines the 26 bit signed offset for the C2 output channel" rgroup.long 0x2070++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH3_ICH1_0,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x0 16.--27. 1. "CCM_OCH3_ICH1,Defines the 12 bit signed wieght for the C3 output channel from the C1 input channel" newline hexmask.long.word 0x0 0.--11. 1. "CCM_OCH3_ICH0,Defines the 12 bit signed wieght for the C3 output channel from the C0 input channel" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH3_ICH3_2,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x4 16.--27. 1. "CCM_OCH3_ICH3,Defines the 12 bit signed wieght for the C3 output channel from the C3 input channel" newline hexmask.long.word 0x4 0.--11. 1. "CCM_OCH3_ICH2,Defines the 12 bit signed wieght for the C3 output channel from the C2 input channel" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH3_OFFSET,Defines the 26 bit signed S26Q24 offset for CCM" hexmask.long 0x8 0.--25. 1. "CCM_OCH3_OFFSET,Defines the 26 bit signed offset for the C3 output channel" rgroup.long 0x2080++0xF line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_FIR_SCALES_1_0,Defines the FIR output scaler for FIR filters 1 and 0" hexmask.long.word 0x0 16.--29. 1. "FIR_SCALER1,Defines the U14Q8 scaler for FIR filter 1" newline hexmask.long.word 0x0 0.--13. 1. "FIR_SCALER0,Defines the U14Q8 scaler for FIR filter 0" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_FIR_SCALES_3_2,Defines the FIR output scaler for FIR filters 3 and 2" hexmask.long.word 0x4 16.--29. 1. "FIR_SCALER3,Defines the U14Q8 scaler for FIR filter 3" newline hexmask.long.word 0x4 0.--13. 1. "FIR_SCALER2,Defines the U14Q8 scaler for FIR filter 2" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_FIR_OFFSETS_1_0,Defines the FIR output offset for FIR filters 1 and 0" hexmask.long.word 0x8 16.--31. 1. "FIR_OFFSET1,Defines the U16 offset for FIR filter 1" newline hexmask.long.word 0x8 0.--15. 1. "FIR_OFFSET0,Defines the U16 offset for FIR filter 0" line.long 0xC "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_FIR_OFFSETS_3_2,Defines the FIR output offset for FIR filters 3 and 2" hexmask.long.word 0xC 16.--31. 1. "FIR_OFFSET3,Defines the U16 offset for FIR filter 3" newline hexmask.long.word 0xC 0.--15. 1. "FIR_OFFSET2,Defines the U16 offset for FIR filter 2" rgroup.long 0x2C00++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_CLUT0,The LUT table contains the information used to reduce the pixle width to 24 from 12" hexmask.long.word 0x0 16.--27. 1. "LUT_ENTRY_HI,The upper LUT entry n+1." newline hexmask.long.word 0x0 0.--11. 1. "LUT_ENTRY_LO,The lower LUT entry n+0." rgroup.long 0x3100++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_CLUT1,The LUT table contains the information used to reduce the pixle width to 24 from 12" hexmask.long.word 0x0 16.--27. 1. "LUT_ENTRY_HI,The upper LUT entry n+1." newline hexmask.long.word 0x0 0.--11. 1. "LUT_ENTRY_LO,The lower LUT entry n+0." rgroup.long 0x3600++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_CLUT2,The LUT table contains the information used to reduce the pixle width to 24 from 12" hexmask.long.word 0x0 16.--27. 1. "LUT_ENTRY_HI,The upper LUT entry n+1." newline hexmask.long.word 0x0 0.--11. 1. "LUT_ENTRY_LO,The lower LUT entry n+0." rgroup.long 0x3B00++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_CLUT3,The LUT table contains the information used to reduce the pixle width to 24 from 12" hexmask.long.word 0x0 16.--27. 1. "LUT_ENTRY_HI,The upper LUT entry n+1." newline hexmask.long.word 0x0 0.--11. 1. "LUT_ENTRY_LO,The lower LUT entry n+0." rgroup.long 0x4000++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_PIXEL_RAM,The pixel RAM contains the array of 16 bit pixels stored and used by the CFA logic. Pixels are 16 bit aligned. Pixels can only be written two at a time." hexmask.long.word 0x0 16.--31. 1. "PIXEL_HI,The 16 bit pixel data for the selected line upper pixel 'n+1'" newline hexmask.long.word 0x0 0.--15. 1. "PIXEL_LO,The 16 bit pixel data for the selected line lower pixel 'n'" rgroup.long 0x100C++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_REGS_coef,Coefficients for a=core. b=dir. c=phase. d=row. column=e*2+1 and e*2" hexmask.long.word 0x0 16.--24. 1. "COEF_1,Coefficient - e*2+1" newline hexmask.long.word 0x0 0.--8. 1. "COEF_0,Coefficient - e*2" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_DLUTS (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_DLUTS)" base ad:0x395C000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_DLUTS_DLUT0,The LUT table contains the information used to expand the pixel width from 16 to 24" hexmask.long.tbyte 0x0 0.--23. 1. "LUT_ENTRY,The lower LUT entry" rgroup.long 0x1000++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_DLUTS_DLUT1,The LUT table contains the information used to expand the pixel width from 16 to 24" hexmask.long.tbyte 0x0 0.--23. 1. "LUT_ENTRY,The lower LUT entry" rgroup.long 0x2000++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_DLUTS_DLUT2,The LUT table contains the information used to expand the pixel width from 16 to 24" hexmask.long.tbyte 0x0 0.--23. 1. "LUT_ENTRY,The lower LUT entry" rgroup.long 0x3000++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__CFA_VBUSP__FLEXCFA_DLUTS_DLUT3,The LUT table contains the information used to expand the pixel width from 16 to 24" hexmask.long.tbyte 0x0 0.--23. 1. "LUT_ENTRY,The lower LUT entry" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_EE_VBUSP_FLEXEE (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_EE_VBUSP_FLEXEE)" base ad:0x3960000 rgroup.long 0x0++0x1B line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_EE_CFG_0,The Control Register controls the input width and height of the module." hexmask.long.word 0x0 16.--28. 1. "HEIGHT,Height of the input image" newline hexmask.long.word 0x0 0.--12. 1. "WIDTH,Width of the input image" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_EE_CFG_1,The CEE route config Register controls the routing of trafic through and around the EE." bitfld.long 0x4 28. "YUV12_CL_ALIGN,Enables the alignment of the Chroma and Luma for the yuv12 stream. The aligner can align the Chroma and Luma +-19 pixel clocks. 1: Enable alignment. 0: Pass Chroma and Luma as they arrive." "0: Pass Chroma and Luma as they arrive,1: Enable alignment" newline bitfld.long 0x4 24. "YUV8_CL_ALIGN,Enables the alignment of the Chroma and Luma for the yuv8 stream. The aligner can align the Chroma and Luma +-19 pixel clocks. 1: Enable alignment. 0: Pass Chroma and Luma as they arrive." "0: Pass Chroma and Luma as they arrive,1: Enable alignment" newline bitfld.long 0x4 22. "EE_FE_MUX_SEL,Selects which data stream to pass through the EE block. 0: Selects the yuv12 stream. 1: selects the yuv8 stream." "0: Selects the yuv12 stream,1: selects the yuv8 stream" newline bitfld.long 0x4 18.--19. "SHIFTLEFT_NUM,Sects the amount to shift left the incoming pixel to the EE block. 0: No Shift. 1: Shift by 2. 2: Shift by 4. 3: Reserved for future expansion." "0: No Shift,1: Shift by 2,2: Shift by 4,3: Reserved for future expansion" newline bitfld.long 0x4 16.--17. "SHIFTRIGHT_NUM,Sects the amount to shift right the outgoing pixel from the EE block. 0: No Shift. 1: Shift by 2. 2: Shift by 4. 3: Reserved for future expansion." "0: No Shift,1: Shift by 2,2: Shift by 4,3: Reserved for future expansion" newline bitfld.long 0x4 12. "LLSE12_MUX_SEL,Selects Luma stream for the yuv12 output. 0: Bypass EE block. 1: Use EE Luma Output." "0: Bypass EE block,1: Use EE Luma Output" newline bitfld.long 0x4 8. "CLSE12_MUX_SEL,Selects Chroma stream for the yuv12 output. 0: Bypass EE block. 1: Use EE Chroma Output." "0: Bypass EE block,1: Use EE Chroma Output" newline bitfld.long 0x4 4. "LLSE8_MUX_SEL,Selects Luma stream for the yuv8 output. 0: Bypass EE block. 1: Use EE Luma Output." "0: Bypass EE block,1: Use EE Luma Output" newline bitfld.long 0x4 0. "CLSE8_MUX_SEL,Selects Chroma stream for the yuv8 output. 0: Bypass EE block. 1: Use EE Chroma Output." "0: Bypass EE block,1: Use EE Chroma Output" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_EE_ENABLE,The EE Enable register control the internal bypass of the EE block." bitfld.long 0x8 0. "YEE_ENABLE,The EE Enable register control the internal bypass of the EE block." "0,1" line.long 0xC "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_YEE_SHIFT,The YEE Shift register controls the down shift length of high pass filter (HPF) in edge enhancer" hexmask.long.byte 0xC 0.--5. 1. "YEE_SHIFT,The down shift length of high pass filter (HPF) in edge enhancer takes the output of the 5x5 HPF and shifts it by the selected amount. Only values 0-31 are valid." line.long 0x10 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R0_C0,The YEE Coefficient Row 0 Column 0 defines the Multiplier coefficient in HPF" hexmask.long.word 0x10 0.--9. 1. "YEE_COEF_R0_C0,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." line.long 0x14 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R0_C1,The YEE Coefficient Row 0 Column 1 defines the Multiplier coefficient in HPF" hexmask.long.word 0x14 0.--9. 1. "YEE_COEF_R0_C1,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." line.long 0x18 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R0_C2,The YEE Coefficient Row 0 Column 2 defines the Multiplier coefficient in HPF" hexmask.long.word 0x18 0.--9. 1. "YEE_COEF_R0_C2,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." rgroup.long 0x20++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R1_C0,The YEE Coefficient Row 1 Column 0 defines the Multiplier coefficient in HPF" hexmask.long.word 0x0 0.--9. 1. "YEE_COEF_R1_C0,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R1_C1,The YEE Coefficient Row 1 Column 1 defines the Multiplier coefficient in HPF" hexmask.long.word 0x4 0.--9. 1. "YEE_COEF_R1_C1,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R1_C2,The YEE Coefficient Row 1 Column 2 defines the Multiplier coefficient in HPF" hexmask.long.word 0x8 0.--9. 1. "YEE_COEF_R1_C2,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." rgroup.long 0x30++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R2_C0,The YEE Coefficient Row 2 Column 0 defines the Multiplier coefficient in HPF" hexmask.long.word 0x0 0.--9. 1. "YEE_COEF_R2_C0,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R2_C1,The YEE Coefficient Row 2 Column 1 defines the Multiplier coefficient in HPF" hexmask.long.word 0x4 0.--9. 1. "YEE_COEF_R2_C1,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R2_C2,The YEE Coefficient Row 2 Column 2 defines the Multiplier coefficient in HPF" hexmask.long.word 0x8 0.--9. 1. "YEE_COEF_R2_C2,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." rgroup.long 0x40++0x1F line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_YEE_E_THR,The Edge Enhancer lower threshold before referring to LUT." hexmask.long.word 0x0 0.--9. 1. "YEE_E_THR,The yee_e_thr is the Shrink Threshold before the LUT scaled by 16x." line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_YEE_MERGESEL,The Merge selects the output that is added to the target pixel." bitfld.long 0x4 0. "YEE_MERGESEL,The yee_mergesel selects either the sum of the LUT and edge sharpener output of the max of the absolute values from both. 0: selects the SUM. 1: elects the absolute value max." "0: selects the SUM,1: elects the absolute value max" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_YES_E_HAL,The Halo selects Halo reduction mode." bitfld.long 0x8 0. "YES_E_HAL,The yes_e_hal selects whether the 3x3 gradients is used to clip the target pixel. 0: Halo reduction off. 1: Halo reduction on." "0: Halo reduction off,1: Halo reduction on" line.long 0xC "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_YES_G_GAIN,The Edge sharpener. gain value on gradient" hexmask.long.byte 0xC 0.--7. 1. "YES_G_GAIN,Sets the Gradient Gain value" line.long 0x10 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_YES_E_GAIN,The Edge sharpener gain" hexmask.long.word 0x10 0.--11. 1. "YES_E_GAIN,Sets the Edge sharpener Band-pass filter gain" line.long 0x14 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_YES_E_THR1,The Edge sharpener HPF value lower limit" hexmask.long.word 0x14 0.--15. 1. "YES_E_THR1,Sets the Edge sharpener HPF value lower limit shrink threshold" line.long 0x18 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_YES_E_THR2,The Edge sharpener HPF value upper limit (after 6 bit right shift)" hexmask.long.word 0x18 0.--9. 1. "YES_E_THR2,Sets the Edge sharpener HPF value upper limit (after 6 bit right shift) clip threshold" line.long 0x1C "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_YES_G_OFT,The Edge sharpener. offset value on gradient" hexmask.long.word 0x1C 0.--9. 1. "YES_G_OFT,Sets the Edge sharpener offset value on gradient" rgroup.long 0x100++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_INT_STATUS,Status/clear register for flexee interrupts" bitfld.long 0x0 3. "EE_HZ_ALIGN8,status/clear for EE horizontal aligner yuv8 overflow error indicates that the luma and chroma line starts were not within hardware synchronization limits. Write 1 to clear write 0 has no effect." "0,1" newline bitfld.long 0x0 2. "EE_HZ_ALIGN12,status/clear for EE horizontal aligner yuv12 overflow error indicates that the luma and chroma line starts were not within hardware synchronization limits. Write 1 to clear write 0 has no effect." "0,1" newline bitfld.long 0x0 1. "EE_PIX_ERR,status/clear for error on line array set when software accesses EE pixel array during active frame causing potential frame corruption. Write 1 to clear write 0 has no effect." "0,1" newline bitfld.long 0x0 0. "EELUT_CFG_ERR,status/clear for error on EE LUT cfg set when software accesses EE LUT during active frame causing potential frame corruption. Write 1 to clear write 0 has no effect." "0,1" rgroup.long 0x1008++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_LINE_SEL,Selector for which line memory is read or written" bitfld.long 0x0 0.--2. "LINE_SELECTOR,Selects which line is read or written from the line memory array. The current line is updated at Start-Of-Line so if the memory is read during a line that is being written the data for the current_line will contain the new data for this.." "?,?,2: current line,3: current line,4: current side band line,5: current side band line,?,?" rgroup.long 0x2000++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_EELUT_RAM,The host will program the EE LUT RAM so that the pixels are translated from 14 bit to 12 bit using LUT entries." hexmask.long.word 0x0 16.--28. 1. "EELUT_ENTRY_HI,The lower EE LUT entry n+1." newline hexmask.long.word 0x0 0.--12. 1. "EELUT_ENTRY_LO,The lower EE LUT entry n+0." rgroup.long 0x4000++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__EE_VBUSP__FLEXEE_REGS_PIXEL_RAM,The pixel RAM contains the array of 12 bit pixels stored and used by the CFA logic. Pixels are 16 bit aligned. Pixels can only be written two at a time." hexmask.long.word 0x0 16.--27. 1. "PIXEL_HI,The 12 bit pixel data for the selected line upper pixel 'n+1'" newline hexmask.long.word 0x0 0.--11. 1. "PIXEL_LO,The 12 bit pixel data for the selected line lower pixel 'n'" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC)" base ad:0x3970000 rgroup.long 0x0++0x6B line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_CFG_0,The Control Register controls the input width and height of the module." hexmask.long.word 0x0 16.--28. 1. "HEIGHT,Height of the input image" newline hexmask.long.word 0x0 0.--12. 1. "WIDTH,Width of the input image" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_CFG_1,Configuration Register for top level data flow" bitfld.long 0x4 27. "CHROMA_MODE,Mux for 422/420 (0:420 Chroma 1: 422 Chroma)" "0,1" newline bitfld.long 0x4 26. "MUXRGBHSV_MUX_V,Mux for V calculation (0:Select non WB corrected data 1: Select WB corrected data)" "0: Select non WB corrected data,1: Select WB corrected data)" newline bitfld.long 0x4 25. "MUXRGBHSV_H2,Mux for S/V calculation (0:Select B 1: Select Max(RGB))" "0: Select B,1: Select Max" newline bitfld.long 0x4 24. "MUXRGBHSV_H1,Mux for S/V calculation (0:Select R 1: Select Min(RGB))" "0: Select R,1: Select Min" newline bitfld.long 0x4 18.--19. "S8B8OUTEN,'0': Disable All '1': S8 enable 2:B8 enable 3:C4 enable" "?,?,2: B8 enable,3: C4 enable" newline bitfld.long 0x4 16.--17. "C8G8OUTEN,'0': Disable All '1': C8 enable 2:G8 enable 3:C3 enable" "?,?,2: G8 enable,3: C3 enable" newline bitfld.long 0x4 14.--15. "Y8R8OUTEN,'0': Disable all '1': Y8 enable 2:R8 enable 3:C2 enable" "?,?,2: R8 enable,3: C2 enable" newline bitfld.long 0x4 12.--13. "C12OUTEN,'0': Disable all '1': C12 enable '2': C1 enable" "0,1,2,3" newline bitfld.long 0x4 11. "Y12OUTEN,'0': Disable Y12 output '1': Enable Y12 output" "0,1" newline bitfld.long 0x4 6. "MUXRGBHSV,Input Select for RGBHSV (0:In after Contrast 1: In before Contrast)" "0: In after Contrast,1: In before Contrast)" newline bitfld.long 0x4 4.--5. "MUXY8_OUT,Mux for Y-8 Output (0:MuxC1_4 1:RGB2YUV 2:RGB2HSV)" "0: MuxC1_4,1: RGB2YUV,2: RGB2HSV),?" newline bitfld.long 0x4 2.--3. "MUXY12_OUT,Mux for Y-12 Output (0:MuxC1_4 1:RGB2YUV 2:RGB2HSV 3:C1 enable)" "0: MuxC1_4,1: RGB2YUV,2: RGB2HSV,3: C1 enable)" newline bitfld.long 0x4 0.--1. "MUXC1_4,Mux for selecting C input (0:C0 1:C1 2:C2 3:C3)" "0: C0,1: C1,2: C2,3: C3)" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_CFG_2,Configuration Register-2" hexmask.long.byte 0x8 13.--16. 1. "Y8INBITWIDTH,Bitwidth of input to 12to8 module (Y8) for shift(Program as 12 or lower)" newline hexmask.long.byte 0x8 9.--12. 1. "CONTRASTBITCLIP,Clip Value set as 2^ContrastBitClip -1" newline bitfld.long 0x8 8. "CONTRASTEN,0:Disable 1: Enable Contrast" "0: Disable,1: Enable Contrast" newline bitfld.long 0x8 6. "HSVSATMODE,0:Max(RGB) - Min(RGB) 1:Sum(RGB) - Min(RGB)" "0: Max,1: Sum" newline bitfld.long 0x8 4.--5. "HSVSATDIVMODE,0:One 1:Max(RGB) 2: 4095 -V 3:Sum(RGB)" "0: One,1: Max,?,3: Sum" newline bitfld.long 0x8 3. "SATLUTEN,'1':Use LUT '0':Use shift" "0,1" newline bitfld.long 0x8 2. "RGB8LUTEN,'1':Use LUT '0':Use shift" "0,1" newline bitfld.long 0x8 1. "Y8LUTEN,'1':Use LUT '0':Use shift" "0,1" newline bitfld.long 0x8 0. "C8LUTEN,'1':Use LUT '0':Use shift" "0,1" line.long 0xC "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_CFG_Hist_1,Configuration-1 Register for histogram" hexmask.long.word 0xC 16.--28. 1. "HISTSTARTY,Y Start for Histogram ROI should be >= 1" newline bitfld.long 0xC 14. "BANK,bank select for Histogram" "0,1" newline hexmask.long.word 0xC 1.--13. 1. "HISTSTARTX,X Start for Histogram ROI should be even" newline bitfld.long 0xC 0. "HISTEN,Enable bit for histogram" "0,1" line.long 0x10 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_CFG_Hist_2,Configuration-2 Register for histogram" hexmask.long.word 0x10 16.--28. 1. "HISTSIZEY,Y Size (Height) for Histogram ROI" newline bitfld.long 0x10 13.--15. "HISTMODE,Histogram Mode 0:Col-0(R) 1:Col-1(G) 2:Col-2(B) 3:MuxC1_4 4:(R+2G+B)/4 5:Col-0(R)" "0: Col-0,1: Col-1,2: Col-2,3: MuxC1_4,?,5: Col-0,?,?" newline hexmask.long.word 0x10 0.--12. 1. "HISTSIZEX,X Size (Width) for Histogram ROI should be > 256 & even" line.long 0x14 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_CCM_W0_0_1,CCM Weights for Row0" hexmask.long.word 0x14 16.--27. 1. "W_1,Weight W_01 : (S12 b)" newline hexmask.long.word 0x14 0.--11. 1. "W_0,Weight W_00 : (S12 b)" line.long 0x18 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_CCM_W0_2_3,CCM Weights for Row0" hexmask.long.word 0x18 16.--27. 1. "W_3,Weight W_03 : (S12 b)" newline hexmask.long.word 0x18 0.--11. 1. "W_2,Weight W_02 : (S12 b)" line.long 0x1C "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_CCM_OFFSET_0,CCM OFFSET for Row0" hexmask.long.word 0x1C 0.--12. 1. "OFFSET_0,OFFSET_0 : (S13 b)" line.long 0x20 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_CCM_W1_0_1,CCM Weights for Row1" hexmask.long.word 0x20 16.--27. 1. "W_1,Weight W_11 : (S12 b)" newline hexmask.long.word 0x20 0.--11. 1. "W_0,Weight W_10 : (S12 b)" line.long 0x24 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_CCM_W1_2_3,CCM Weights for Row1" hexmask.long.word 0x24 16.--27. 1. "W_3,Weight W_13 : (S12 b)" newline hexmask.long.word 0x24 0.--11. 1. "W_2,Weight W_12 : (S12 b)" line.long 0x28 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_CCM_OFFSET_1,CCM OFFSET for Row1" hexmask.long.word 0x28 0.--12. 1. "OFFSET_1,OFFSET_1 : (S13 b)" line.long 0x2C "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_CCM_W2_0_1,CCM Weights for Row2" hexmask.long.word 0x2C 16.--27. 1. "W_1,Weight W_21 : (S12 b)" newline hexmask.long.word 0x2C 0.--11. 1. "W_0,Weight W_20 : (S12 b)" line.long 0x30 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_CCM_W2_2_3,CCM Weights for Row2" hexmask.long.word 0x30 16.--27. 1. "W_3,Weight W_23 : (S12 b)" newline hexmask.long.word 0x30 0.--11. 1. "W_2,Weight W_22 : (S12 b)" line.long 0x34 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_CCM_OFFSET_2,CCM OFFSET for Row2" hexmask.long.word 0x34 0.--12. 1. "OFFSET_2,OFFSET_2 : (S13 b)" line.long 0x38 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_RGBYUV_W01,Weight/Offset for Row0" hexmask.long.word 0x38 16.--27. 1. "W_02,Weight W_02 : (S12 b)" newline hexmask.long.word 0x38 0.--11. 1. "W_01,Weight W_01 : (S12 b)" line.long 0x3C "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_RGBYUV_W02,Weight/Offset for Row0" hexmask.long.word 0x3C 16.--28. 1. "OFFSET_0,Offset_0 : (S13b)" newline hexmask.long.word 0x3C 0.--11. 1. "W_03,Weight W_03 : (S12 b)" line.long 0x40 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_RGBYUV_W11,Weight/Offset for Row1" hexmask.long.word 0x40 16.--27. 1. "W_12,Weight W_12 : (S12 b)" newline hexmask.long.word 0x40 0.--11. 1. "W_11,Weight W_11 : (S12 b)" line.long 0x44 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_RGBYUV_W12,Weight/Offset for Row1" hexmask.long.word 0x44 16.--28. 1. "OFFSET_1,Offset_1 : (S13b)" newline hexmask.long.word 0x44 0.--11. 1. "W_13,Weight W_13 : (S12 b)" line.long 0x48 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_RGBYUV_W21,Weight/Offset for Row2" hexmask.long.word 0x48 16.--27. 1. "W_22,Weight W_22 : (S12 b)" newline hexmask.long.word 0x48 0.--11. 1. "W_21,Weight W_21 : (S12 b)" line.long 0x4C "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_RGBYUV_W22,Weight/Offset for Row2" hexmask.long.word 0x4C 16.--28. 1. "OFFSET_2,Offset_2 : (S13b)" newline hexmask.long.word 0x4C 0.--11. 1. "W_23,Weight W_23 : (S12 b)" line.long 0x50 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_RGBHSV_W0,Weights 11/12 for V calculation" hexmask.long.word 0x50 16.--27. 1. "W12,Weight W12 (Signed 12b)" newline hexmask.long.word 0x50 0.--11. 1. "W11,Weight W11 (Signed 12b)" line.long 0x54 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_RGBHSV_W1,Weights13 and Offset_1 for V Calculation" hexmask.long.word 0x54 16.--28. 1. "OFFSET_1,Offset_1 (Signed 13b)" newline hexmask.long.word 0x54 0.--11. 1. "W13,Weight W13 (Signed 12b)" line.long 0x58 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_RGBHSV_WB_LINLOGTHR_1,Dynamic WB Thr limit" hexmask.long.word 0x58 16.--27. 1. "THR_1,THR_1 / G-Channel Thr (U 12b)" newline hexmask.long.word 0x58 0.--11. 1. "THR_0,THR_0 / R-Channel Thr (U 12b)" line.long 0x5C "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_RGBHSV_WB_LINLOGTHR_2,Dynamic WB Thr limit and SatMinThr" hexmask.long.word 0x5C 16.--27. 1. "SATMINTHR,Thr for comparing Min(RGB) limit" newline hexmask.long.word 0x5C 0.--11. 1. "THR_2,THR_2 / B-Channel Thr (U 12b)" line.long 0x60 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_RGBHSV_OFF1,WB Offset for Saturation" hexmask.long.word 0x60 16.--27. 1. "OFFSET_2,Offset_2 (U 12b)" newline hexmask.long.word 0x60 0.--11. 1. "OFFSET_1,Offset-1 (U 12b)" line.long 0x64 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_RGBHSV_OFF2,WB Offsets for Saturation" hexmask.long.word 0x64 0.--11. 1. "OFFSET_3,Offset-3 (U 12b)" line.long 0x68 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_FLEXCC_INT_STATUS,Status/clear register for flexcc interrupts" bitfld.long 0x68 11. "HIST_READ_ERR,status/clear for histogram memory set when mem access has occurred to the first location but not to the last location during active frame implying that full histogram was not read . Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 10. "LUT_12TO82_CFG_ERR,status/clear for 12to8_2_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 9. "LUT_12TO81_CFG_ERR,status/clear for 12to8_1_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 8. "LUT_12TO80_CFG_ERR,status/clear for 12to8_0_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 7. "CONTRAST2_CFG_ERR,status/clear for contrast2_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 6. "CONTRAST1_CFG_ERR,status/clear for contrast1_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 5. "CONTRAST0_CFG_ERR,status/clear for contrast0_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 4. "OVERFLOW_IF_S8B8,status/clear for overflow on s8b8 i/f set when fifo overflows causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 3. "OVERFLOW_IF_C8G8,status/clear for overflow on c8g8 i/f set when fifo overflows causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 2. "OVERFLOW_IF_Y8R8,status/clear for overflow on y8r8 i/f set when fifo overflows causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 1. "OVERFLOW_IF_UV12,status/clear for overflow on uv12 i/f set when fifo overflows causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 0. "OVERFLOW_IF_Y12,status/clear for overflow on y12 i/f set when fifo overflows causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" rgroup.long 0x100++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_DEBUG_CTL,Enable for different debug events" bitfld.long 0x0 12. "FLEXCC_EOP_EN,Enable for flexcc eop" "0,1" newline bitfld.long 0x0 11. "EOF_IF_S8B8_EN,Enable for eof on s8b8" "0,1" newline bitfld.long 0x0 10. "EOL_IF_S8B8_EN,Enable for eol on s8b8" "0,1" newline bitfld.long 0x0 9. "EOF_IF_C8G8_EN,Enable for eof on c8g8" "0,1" newline bitfld.long 0x0 8. "EOL_IF_C8G8_EN,Enable for eol on c8g8" "0,1" newline bitfld.long 0x0 7. "EOF_IF_Y8R8_EN,Enable for eof on y8r8" "0,1" newline bitfld.long 0x0 6. "EOL_IF_Y8R8_EN,Enable for eol on y8r8" "0,1" newline bitfld.long 0x0 5. "EOF_IF_UV12_EN,Enable for eof on uv12" "0,1" newline bitfld.long 0x0 4. "EOL_IF_UV12_EN,Enable for eol on uv12" "0,1" newline bitfld.long 0x0 3. "EOF_IF_Y12_EN,Enable for eof on y12" "0,1" newline bitfld.long 0x0 2. "EOL_IF_Y12_EN,Enable for eol on y12" "0,1" newline bitfld.long 0x0 1. "STALL_EN,Enable for stall event" "0,1" newline bitfld.long 0x0 0. "DBG_EN,Enable debug features set to '0' to disable all debug events" "0,1" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_DEBUG_STATUS,Set/Clear for debug events" bitfld.long 0x4 12. "FLEXCC_EOP_EVENT,Status/Clear for flexcc eop write '1' to clear" "0,1" newline bitfld.long 0x4 11. "EOF_IF_S8B8_EVENT,Status/Clear for eof on s8b8 write '1' to clear" "0,1" newline bitfld.long 0x4 10. "EOL_IF_S8B8_EVENT,Status/Clear for eol on s8b8 write '1' to clear" "0,1" newline bitfld.long 0x4 9. "EOF_IF_C8G8_EVENT,Status/Clear for eof on c8g8 write '1' to clear" "0,1" newline bitfld.long 0x4 8. "EOL_IF_C8G8_EVENT,Status/Clear for eol on c8g8 write '1' to clear" "0,1" newline bitfld.long 0x4 7. "EOF_IF_Y8R8_EVENT,Status/Clear for eof on y8r8 write '1' to clear" "0,1" newline bitfld.long 0x4 6. "EOL_IF_Y8R8_EVENT,Status/Clear for eol on y8r8 write '1' to clear" "0,1" newline bitfld.long 0x4 5. "EOF_IF_UV12_EVENT,Status/Clear for eof on uv12 write '1' to clear" "0,1" newline bitfld.long 0x4 4. "EOL_IF_UV12_EVENT,Status/Clear for eol on uv12 write '1' to clear" "0,1" newline bitfld.long 0x4 3. "EOF_IF_Y12_EVENT,Status/Clear for eof on y12 write '1' to clear" "0,1" newline bitfld.long 0x4 2. "EOL_IF_Y12_EVENT,Status/Clear for eol on y12 write '1' to clear" "0,1" newline bitfld.long 0x4 1. "STALL_EVENT,Status/Clear for stall event write '1' to clear" "0,1" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_REGS_DEBUG_RAW,Set/Clear for debug RAW mode" bitfld.long 0x8 0. "DBG_RAW_MODE,Enable debug RAW mode takes input from RAWFE and delivers to FlexCC as C1={raw[11:0]} C2={4'd0 raw[7:0]} C3={4'd0 raw[15:8]} c4={8'd0 raw[15:12]}" "0,1" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_C8G8 (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_C8G8)" base ad:0x3972800 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_C8G8_LUT_C8G8,Memory for 12to8 LUT" hexmask.long.byte 0x0 16.--23. 1. "LUT_1,Bank-1" hexmask.long.byte 0x0 0.--7. 1. "LUT_0,Bank-0" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_CONTRASTC1 (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_CONTRASTC1)" base ad:0x3970800 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_CONTRASTC1_LUT_contrastC1,Memory for contrast C1" hexmask.long.word 0x0 16.--27. 1. "LUT_1,Bank-1" hexmask.long.word 0x0 0.--11. 1. "LUT_0,Bank-0" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_CONTRASTC2 (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_CONTRASTC2)" base ad:0x3971000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_CONTRASTC2_LUT_contrastC2,Memory for contrast C1" hexmask.long.word 0x0 16.--27. 1. "LUT_1,Bank-1" hexmask.long.word 0x0 0.--11. 1. "LUT_0,Bank-0" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_CONTRASTC3 (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_CONTRASTC3)" base ad:0x3971800 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_CONTRASTC3_LUT_contrastC3,Memory for contrast C1" hexmask.long.word 0x0 16.--27. 1. "LUT_1,Bank-1" hexmask.long.word 0x0 0.--11. 1. "LUT_0,Bank-0" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_HIST (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_HIST)" base ad:0x3973800 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_HIST_HIST,Memory for Histogram" hexmask.long.tbyte 0x0 0.--19. 1. "HIST_VAL,Bank-0" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_LINE (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_LINE)" base ad:0x3978000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_LINE_LINE_MEM,Memory for 2 lines of yuv444to420" hexmask.long.word 0x0 16.--27. 1. "LINE_1,Line-1" hexmask.long.word 0x0 0.--11. 1. "LINE_0,Line-0" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_S8B8 (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_S8B8)" base ad:0x3973000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_S8B8_LUT_S8B8,Memory for 12to8 LUT" hexmask.long.byte 0x0 16.--23. 1. "LUT_1,Bank-1" hexmask.long.byte 0x0 0.--7. 1. "LUT_0,Bank-0" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_Y8R8 (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_Y8R8)" base ad:0x3972000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP2__FCC_VBUSP__FLEXCC_Y8R8_LUT_Y8R8,Memory for 12to8 LUT" hexmask.long.byte 0x0 16.--23. 1. "LUT_1,Bank-1" hexmask.long.byte 0x0 0.--7. 1. "LUT_0,Bank-0" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_CFA_VBUSP_FLEXCFA (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_CFA_VBUSP_FLEXCFA)" base ad:0x3908000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_LUT,The LUT table contains the information used to reduce the pixle width to 12 from 13-16" hexmask.long.word 0x0 16.--31. 1. "LUT_ENTRY_HI,The upper LUT entry n+1." newline hexmask.long.word 0x0 0.--15. 1. "LUT_ENTRY_LO,The lower LUT entry n+0." rgroup.long 0x1004++0x7 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CFG_0,The Control Register controls the input width and height of the module." hexmask.long.word 0x0 16.--28. 1. "HEIGHT,Height of the input image" newline hexmask.long.word 0x0 0.--12. 1. "WIDTH,Width of the input image" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CFG_1,The Control Register identifies the bit width of the input image" bitfld.long 0x4 11. "BYPASS_CORE3,Setting the ~ibypass_core3 bit will bypass filtering operation output = input" "0,1" newline bitfld.long 0x4 10. "BYPASS_CORE2,Setting the ~ibypass_core2 bit will bypass filtering operation output = input" "0,1" newline bitfld.long 0x4 9. "BYPASS_CORE1,Setting the ~ibypass_core1 bit will bypass filtering operation output = input" "0,1" newline bitfld.long 0x4 8. "BYPASS_CORE0,Setting the ~ibypass_core0 bit will bypass filtering operation output = input" "0,1" newline bitfld.long 0x4 6. "EN16BITMODE,0->legacy mode 1->Enhanced 16 bit CFA mode enabled when LUT is disabled" "0: legacy mode,1: Enhanced 16 bit CFA mode" newline bitfld.long 0x4 5. "LUT_ENABLE,0->Use shift(bitwidth-12) 1->Use LUT" "0: Use shift,1: Use LUT" newline hexmask.long.byte 0x4 0.--4. 1. "BITWIDTH,BitWidth of the input image values greater than 16 will be treated as 16 and values less than 12 will be treated as 12." rgroup.long 0x1D8C++0x47 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_GRAD_CFG,Gradient configuration for all 4 cores" bitfld.long 0x0 25.--26. "BLENDMODECORE3,Core-3 Blend (0:Input-0 1: Input0/1 2: Input 0/1/2 3 : Adaptive Input0/1/2 )" "0: Input-0,1: Input0/1,2: Input 0/1/2,3: Adaptive Input0/1/2 )" newline bitfld.long 0x0 24. "BITMASKSELCORE3,Core-3 Bitmask Select (0: Set-0 1: Set-1)" "0: Set-0,1: Set-1)" newline bitfld.long 0x0 17.--18. "BLENDMODECORE2,Core-2 Blend (0:Input-0 1: Input0/1 2: Input 0/1/2 3 : Adaptive Input0/1/2 )" "0: Input-0,1: Input0/1,2: Input 0/1/2,3: Adaptive Input0/1/2 )" newline bitfld.long 0x0 16. "BITMASKSELCORE2,Core-2 Bitmask Select (0: Set-0 1: Set-1)" "0: Set-0,1: Set-1)" newline bitfld.long 0x0 9.--10. "BLENDMODECORE1,Core-1 Blend (0:Input-0 1: Input0/1 2: Input 0/1/2 3 : Adaptive Input0/1/2 )" "0: Input-0,1: Input0/1,2: Input 0/1/2,3: Adaptive Input0/1/2 )" newline bitfld.long 0x0 8. "BITMASKSELCORE1,Core-1 Bitmask Select (0: Set-0 1: Set-1)" "0: Set-0,1: Set-1)" newline bitfld.long 0x0 1.--2. "BLENDMODECORE0,Core-0 Blend (0:Input-0 1: Input0/1 2: Input 0/1/2 3 : Adaptive Input0/1/2 )" "0: Input-0,1: Input0/1,2: Input 0/1/2,3: Adaptive Input0/1/2 )" newline bitfld.long 0x0 0. "BITMASKSELCORE0,Core-0 Bitmask Select (0: Set-0 1: Set-1)" "0: Set-0,1: Set-1)" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET0_GRAD_HZ,Gradient Bitfield selector. Set-0 for Horizontal" hexmask.long.byte 0x4 24.--31. 1. "PHASE3,Bitfield selector for Phase-3" newline hexmask.long.byte 0x4 16.--23. 1. "PHASE2,Bitfield selector for Phase-2" newline hexmask.long.byte 0x4 8.--15. 1. "PHASE1,Bitfield selector for Phase-1" newline hexmask.long.byte 0x4 0.--7. 1. "PHASE0,Bitfield selector for Phase-0" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET0_GRAD_VT,Gradient Bitfield selector. Set-0 for Vertical" hexmask.long.byte 0x8 24.--31. 1. "PHASE3,Bitfield selector for Phase-3" newline hexmask.long.byte 0x8 16.--23. 1. "PHASE2,Bitfield selector for Phase-2" newline hexmask.long.byte 0x8 8.--15. 1. "PHASE1,Bitfield selector for Phase-1" newline hexmask.long.byte 0x8 0.--7. 1. "PHASE0,Bitfield selector for Phase-0" line.long 0xC "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET0_INTENSITY0,Intensity Bitfield selector and shift for phase0/1" hexmask.long.byte 0xC 28.--31. 1. "SHIFT_PH1,Intensity shift for Phase-1" newline hexmask.long.byte 0xC 16.--19. 1. "BITFIELD_PH1,Intensity Bitfield selector for Phase-1" newline hexmask.long.byte 0xC 12.--15. 1. "SHIFT_PH0,Intensity shift for Phase-0" newline hexmask.long.byte 0xC 0.--3. 1. "BITFIELD_PH0,Intensity Bitfield selector for Phase-0" line.long 0x10 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET0_INTENSITY1,Intensity Bitfield selector and shift for phase2/3" hexmask.long.byte 0x10 28.--31. 1. "SHIFT_PH3,Intensity shift for Phase-3" newline hexmask.long.byte 0x10 16.--19. 1. "BITFIELD_PH3,Intensity Bitfield selector for Phase-3" newline hexmask.long.byte 0x10 12.--15. 1. "SHIFT_PH2,Intensity shift for Phase-2" newline hexmask.long.byte 0x10 0.--3. 1. "BITFIELD_PH2,Intensity Bitfield selector for Phase-2" line.long 0x14 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET1_GRAD_HZ,Gradient Bitfield selector. Set-1 for Horizontal" hexmask.long.byte 0x14 24.--31. 1. "PHASE3,Bitfield selector for Phase-3" newline hexmask.long.byte 0x14 16.--23. 1. "PHASE2,Bitfield selector for Phase-2" newline hexmask.long.byte 0x14 8.--15. 1. "PHASE1,Bitfield selector for Phase-1" newline hexmask.long.byte 0x14 0.--7. 1. "PHASE0,Bitfield selector for Phase-0" line.long 0x18 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET1_GRAD_VT,Gradient Bitfield selector. Set-1 for Vertical" hexmask.long.byte 0x18 24.--31. 1. "PHASE3,Bitfield selector for Phase-3" newline hexmask.long.byte 0x18 16.--23. 1. "PHASE2,Bitfield selector for Phase-2" newline hexmask.long.byte 0x18 8.--15. 1. "PHASE1,Bitfield selector for Phase-1" newline hexmask.long.byte 0x18 0.--7. 1. "PHASE0,Bitfield selector for Phase-0" line.long 0x1C "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET1_INTENSITY0,Intensity Bitfield selector and shift for phase0/1" hexmask.long.byte 0x1C 28.--31. 1. "SHIFT_PH1,Intensity shift for Phase-1" newline hexmask.long.byte 0x1C 16.--19. 1. "BITFIELD_PH1,Intensity Bitfield selector for Phase-1" newline hexmask.long.byte 0x1C 12.--15. 1. "SHIFT_PH0,Intensity shift for Phase-0" newline hexmask.long.byte 0x1C 0.--3. 1. "BITFIELD_PH0,Intensity Bitfield selector for Phase-0" line.long 0x20 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET1_INTENSITY1,Intensity Bitfield selector and shift for phase2/3" hexmask.long.byte 0x20 28.--31. 1. "SHIFT_PH3,Intensity shift for Phase-3" newline hexmask.long.byte 0x20 16.--19. 1. "BITFIELD_PH3,Intensity Bitfield selector for Phase-3" newline hexmask.long.byte 0x20 12.--15. 1. "SHIFT_PH2,Intensity shift for Phase-2" newline hexmask.long.byte 0x20 0.--3. 1. "BITFIELD_PH2,Intensity Bitfield selector for Phase-2" line.long 0x24 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET0_THR0_1,Set0 Thr0_1 for H/V Grad difference" hexmask.long.word 0x24 16.--31. 1. "THR_1,H/V Grad diff Threshold_1" newline hexmask.long.word 0x24 0.--15. 1. "THR_0,H/V Grad diff Threshold_0" line.long 0x28 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET0_THR2_3,Set0 Thr2_3 for H/V Grad difference" hexmask.long.word 0x28 16.--31. 1. "THR_3,H/V Grad diff Threshold_3" newline hexmask.long.word 0x28 0.--15. 1. "THR_2,H/V Grad diff Threshold_2" line.long 0x2C "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET0_THR4_5,Set0 Thr4_5 for H/V Grad difference" hexmask.long.word 0x2C 16.--31. 1. "THR_5,H/V Grad diff Threshold_5" newline hexmask.long.word 0x2C 0.--15. 1. "THR_4,H/V Grad diff Threshold_4" line.long 0x30 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET0_THR6,Set0 Thr6 for H/V Grad difference" hexmask.long.word 0x30 0.--15. 1. "THR_6,H/V Grad diff Threshold_6" line.long 0x34 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET1_THR0_1,Set1 Thr0_1 for H/V Grad difference" hexmask.long.word 0x34 16.--31. 1. "THR_1,H/V Grad diff Threshold_1" newline hexmask.long.word 0x34 0.--15. 1. "THR_0,H/V Grad diff Threshold_0" line.long 0x38 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET1_THR2_3,Set1 Thr2_3 for H/V Grad difference" hexmask.long.word 0x38 16.--31. 1. "THR_3,H/V Grad diff Threshold_3" newline hexmask.long.word 0x38 0.--15. 1. "THR_2,H/V Grad diff Threshold_2" line.long 0x3C "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET1_THR4_5,Set1 Thr4_5 for H/V Grad difference" hexmask.long.word 0x3C 16.--31. 1. "THR_5,H/V Grad diff Threshold_5" newline hexmask.long.word 0x3C 0.--15. 1. "THR_4,H/V Grad diff Threshold_4" line.long 0x40 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET1_THR6,Set1 Thr6 for H/V Grad difference" hexmask.long.word 0x40 0.--15. 1. "THR_6,H/V Grad diff Threshold_6" line.long 0x44 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_INT_STATUS,Status/clear register for flexcfa interrupts" bitfld.long 0x44 4. "CLUT_CFG_ERR,status/clear for error on CLUT cfg set when software accesses CLUT during active frame causing potential frame corruption. Write 1 to clear write 0 has no effect." "0,1" newline bitfld.long 0x44 3. "DLUT_CFG_ERR,status/clear for error on DLUT cfg set when software accesses DLUT during active frame causing potential frame corruption. Write 1 to clear write 0 has no effect." "0,1" newline bitfld.long 0x44 2. "CFA_MMR_ERR,status/clear for error writes to the FIR Filter MMRs during active frame causing potential frame corruption. Write 1 to clear write 0 has no effect." "0,1" newline bitfld.long 0x44 1. "CFA_PIX_ERR,status/clear for error on line array set when software accesses pixel array during active frame causing potential frame corruption. Write 1 to clear write 0 has no effect." "0,1" newline bitfld.long 0x44 0. "LUT_CFG_ERR,status/clear for error on LUT cfg set when software accesses LUT during active frame causing potential frame corruption. Write 1 to clear write 0 has no effect." "0,1" rgroup.long 0x2000++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_DEBUG_CTL,Enable for different debug events" bitfld.long 0x0 2. "SOF_EN,Enable for sof event" "0,1" newline bitfld.long 0x0 1. "SOL_EN,Enable for sol event" "0,1" newline bitfld.long 0x0 0. "DBG_EN,Enable debug features set to '0' to disable all debug events" "0,1" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_DEBUG_STATUS,Set/Clear for debug events" bitfld.long 0x4 2. "SOF_EVENT,Status/Clear for sof event write '1' to clear" "0,1" newline bitfld.long 0x4 1. "SOL_EVENT,Status/Clear for sol event write '1' to clear" "0,1" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_LINE_SEL,Selector for which line memory is read or written" bitfld.long 0x8 0.--2. "LINE_SELECTOR,Selects which line is read or written from the line memory array. The current line is updated at Start-Of-Line so if the memory is read during a line that is being written the data for the current_line will contain the new data for this.." "?,?,2: current line,3: current line,4: current line,?,?,?" rgroup.long 0x2010++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_DANDC_COM_CTRL,This register handles the general conrtrol bits for the DLUT CCM and CLUT blocks that preceed the CC module in the FCP." bitfld.long 0x0 27. "DISFIR3,Disables the FIR filter for C3 to save power" "0,1" newline bitfld.long 0x0 26. "DISFIR2,Disables the FIR filter for C2 to save power" "0,1" newline bitfld.long 0x0 25. "DISFIR1,Disables the FIR filter for C1 to save power" "0,1" newline bitfld.long 0x0 24. "DISFIR0,Disables the FIR filter for C0 to save power" "0,1" newline bitfld.long 0x0 10. "CMPDLUTEN,Enables the CLUT" "0,1" newline bitfld.long 0x0 9. "CCMEN,Enables the CCM" "0,1" newline bitfld.long 0x0 8. "DCMPDLUTEN,Enables the DLUT" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "LINEARBITWIDTH,Defines the DLUT output bit width the CCM clipping bit width and the CLUT input bit width valid values are 12-24. Values less than 12 12 will be used values greater than 24 24 will be used. Useful combinations are 12/16/20/24" rgroup.long 0x2040++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH0_ICH1_0,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x0 16.--27. 1. "CCM_OCH0_ICH1,Defines the 12 bit signed wieght for the C0 output channel from the C1 input channel" newline hexmask.long.word 0x0 0.--11. 1. "CCM_OCH0_ICH0,Defines the 12 bit signed wieght for the C0 output channel from the C0 input channel" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH0_ICH3_2,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x4 16.--27. 1. "CCM_OCH0_ICH3,Defines the 12 bit signed wieght for the C0 output channel from the C3 input channel" newline hexmask.long.word 0x4 0.--11. 1. "CCM_OCH0_ICH2,Defines the 12 bit signed wieght for the C0 output channel from the C2 input channel" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH0_OFFSET,Defines the 26 bit signed S26Q24 offset for CCM" hexmask.long 0x8 0.--25. 1. "CCM_OCH0_OFFSET,Defines the 26 bit signed offset for the C0 output channel" rgroup.long 0x2050++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH1_ICH1_0,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x0 16.--27. 1. "CCM_OCH1_ICH1,Defines the 12 bit signed wieght for the C1 output channel from the C1 input channel" newline hexmask.long.word 0x0 0.--11. 1. "CCM_OCH1_ICH0,Defines the 12 bit signed wieght for the C1 output channel from the C0 input channel" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH1_ICH3_2,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x4 16.--27. 1. "CCM_OCH1_ICH3,Defines the 12 bit signed wieght for the C1 output channel from the C3 input channel" newline hexmask.long.word 0x4 0.--11. 1. "CCM_OCH1_ICH2,Defines the 12 bit signed wieght for the C1 output channel from the C2 input channel" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH1_OFFSET,Defines the 26 bit signed S26Q24 offset for CCM" hexmask.long 0x8 0.--25. 1. "CCM_OCH1_OFFSET,Defines the 26 bit signed offset for the C1 output channel" rgroup.long 0x2060++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH2_ICH1_0,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x0 16.--27. 1. "CCM_OCH2_ICH1,Defines the 12 bit signed wieght for the C2 output channel from the C1 input channel" newline hexmask.long.word 0x0 0.--11. 1. "CCM_OCH2_ICH0,Defines the 12 bit signed wieght for the C2 output channel from the C0 input channel" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH2_ICH3_2,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x4 16.--27. 1. "CCM_OCH2_ICH3,Defines the 12 bit signed wieght for the C2 output channel from the C3 input channel" newline hexmask.long.word 0x4 0.--11. 1. "CCM_OCH2_ICH2,Defines the 12 bit signed wieght for the C2 output channel from the C2 input channel" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH2_OFFSET,Defines the 26 bit signed S26Q24 offset for CCM" hexmask.long 0x8 0.--25. 1. "CCM_OCH2_OFFSET,Defines the 26 bit signed offset for the C2 output channel" rgroup.long 0x2070++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH3_ICH1_0,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x0 16.--27. 1. "CCM_OCH3_ICH1,Defines the 12 bit signed wieght for the C3 output channel from the C1 input channel" newline hexmask.long.word 0x0 0.--11. 1. "CCM_OCH3_ICH0,Defines the 12 bit signed wieght for the C3 output channel from the C0 input channel" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH3_ICH3_2,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x4 16.--27. 1. "CCM_OCH3_ICH3,Defines the 12 bit signed wieght for the C3 output channel from the C3 input channel" newline hexmask.long.word 0x4 0.--11. 1. "CCM_OCH3_ICH2,Defines the 12 bit signed wieght for the C3 output channel from the C2 input channel" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH3_OFFSET,Defines the 26 bit signed S26Q24 offset for CCM" hexmask.long 0x8 0.--25. 1. "CCM_OCH3_OFFSET,Defines the 26 bit signed offset for the C3 output channel" rgroup.long 0x2080++0xF line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_FIR_SCALES_1_0,Defines the FIR output scaler for FIR filters 1 and 0" hexmask.long.word 0x0 16.--29. 1. "FIR_SCALER1,Defines the U14Q8 scaler for FIR filter 1" newline hexmask.long.word 0x0 0.--13. 1. "FIR_SCALER0,Defines the U14Q8 scaler for FIR filter 0" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_FIR_SCALES_3_2,Defines the FIR output scaler for FIR filters 3 and 2" hexmask.long.word 0x4 16.--29. 1. "FIR_SCALER3,Defines the U14Q8 scaler for FIR filter 3" newline hexmask.long.word 0x4 0.--13. 1. "FIR_SCALER2,Defines the U14Q8 scaler for FIR filter 2" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_FIR_OFFSETS_1_0,Defines the FIR output offset for FIR filters 1 and 0" hexmask.long.word 0x8 16.--31. 1. "FIR_OFFSET1,Defines the U16 offset for FIR filter 1" newline hexmask.long.word 0x8 0.--15. 1. "FIR_OFFSET0,Defines the U16 offset for FIR filter 0" line.long 0xC "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_FIR_OFFSETS_3_2,Defines the FIR output offset for FIR filters 3 and 2" hexmask.long.word 0xC 16.--31. 1. "FIR_OFFSET3,Defines the U16 offset for FIR filter 3" newline hexmask.long.word 0xC 0.--15. 1. "FIR_OFFSET2,Defines the U16 offset for FIR filter 2" rgroup.long 0x2C00++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CLUT0,The LUT table contains the information used to reduce the pixle width to 24 from 12" hexmask.long.word 0x0 16.--27. 1. "LUT_ENTRY_HI,The upper LUT entry n+1." newline hexmask.long.word 0x0 0.--11. 1. "LUT_ENTRY_LO,The lower LUT entry n+0." rgroup.long 0x3100++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CLUT1,The LUT table contains the information used to reduce the pixle width to 24 from 12" hexmask.long.word 0x0 16.--27. 1. "LUT_ENTRY_HI,The upper LUT entry n+1." newline hexmask.long.word 0x0 0.--11. 1. "LUT_ENTRY_LO,The lower LUT entry n+0." rgroup.long 0x3600++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CLUT2,The LUT table contains the information used to reduce the pixle width to 24 from 12" hexmask.long.word 0x0 16.--27. 1. "LUT_ENTRY_HI,The upper LUT entry n+1." newline hexmask.long.word 0x0 0.--11. 1. "LUT_ENTRY_LO,The lower LUT entry n+0." rgroup.long 0x3B00++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CLUT3,The LUT table contains the information used to reduce the pixle width to 24 from 12" hexmask.long.word 0x0 16.--27. 1. "LUT_ENTRY_HI,The upper LUT entry n+1." newline hexmask.long.word 0x0 0.--11. 1. "LUT_ENTRY_LO,The lower LUT entry n+0." rgroup.long 0x4000++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_PIXEL_RAM,The pixel RAM contains the array of 16 bit pixels stored and used by the CFA logic. Pixels are 16 bit aligned. Pixels can only be written two at a time." hexmask.long.word 0x0 16.--31. 1. "PIXEL_HI,The 16 bit pixel data for the selected line upper pixel 'n+1'" newline hexmask.long.word 0x0 0.--15. 1. "PIXEL_LO,The 16 bit pixel data for the selected line lower pixel 'n'" rgroup.long 0x100C++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_coef,Coefficients for a=core. b=dir. c=phase. d=row. column=e*2+1 and e*2" hexmask.long.word 0x0 16.--24. 1. "COEF_1,Coefficient - e*2+1" newline hexmask.long.word 0x0 0.--8. 1. "COEF_0,Coefficient - e*2" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_CFA_VBUSP_FLEXCFA_DLUTS (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_CFA_VBUSP_FLEXCFA_DLUTS)" base ad:0x3958000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_DLUTS_DLUT0,The LUT table contains the information used to expand the pixel width from 16 to 24" hexmask.long.tbyte 0x0 0.--23. 1. "LUT_ENTRY,The lower LUT entry" rgroup.long 0x1000++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_DLUTS_DLUT1,The LUT table contains the information used to expand the pixel width from 16 to 24" hexmask.long.tbyte 0x0 0.--23. 1. "LUT_ENTRY,The lower LUT entry" rgroup.long 0x2000++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_DLUTS_DLUT2,The LUT table contains the information used to expand the pixel width from 16 to 24" hexmask.long.tbyte 0x0 0.--23. 1. "LUT_ENTRY,The lower LUT entry" rgroup.long 0x3000++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_DLUTS_DLUT3,The LUT table contains the information used to expand the pixel width from 16 to 24" hexmask.long.tbyte 0x0 0.--23. 1. "LUT_ENTRY,The lower LUT entry" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_EE_VBUSP_FLEXEE (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_EE_VBUSP_FLEXEE)" base ad:0x3950000 rgroup.long 0x0++0x1B line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_EE_CFG_0,The Control Register controls the input width and height of the module." hexmask.long.word 0x0 16.--28. 1. "HEIGHT,Height of the input image" newline hexmask.long.word 0x0 0.--12. 1. "WIDTH,Width of the input image" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_EE_CFG_1,The CEE route config Register controls the routing of trafic through and around the EE." bitfld.long 0x4 28. "YUV12_CL_ALIGN,Enables the alignment of the Chroma and Luma for the yuv12 stream. The aligner can align the Chroma and Luma +-19 pixel clocks. 1: Enable alignment. 0: Pass Chroma and Luma as they arrive." "0: Pass Chroma and Luma as they arrive,1: Enable alignment" newline bitfld.long 0x4 24. "YUV8_CL_ALIGN,Enables the alignment of the Chroma and Luma for the yuv8 stream. The aligner can align the Chroma and Luma +-19 pixel clocks. 1: Enable alignment. 0: Pass Chroma and Luma as they arrive." "0: Pass Chroma and Luma as they arrive,1: Enable alignment" newline bitfld.long 0x4 22. "EE_FE_MUX_SEL,Selects which data stream to pass through the EE block. 0: Selects the yuv12 stream. 1: selects the yuv8 stream." "0: Selects the yuv12 stream,1: selects the yuv8 stream" newline bitfld.long 0x4 18.--19. "SHIFTLEFT_NUM,Sects the amount to shift left the incoming pixel to the EE block. 0: No Shift. 1: Shift by 2. 2: Shift by 4. 3: Reserved for future expansion." "0: No Shift,1: Shift by 2,2: Shift by 4,3: Reserved for future expansion" newline bitfld.long 0x4 16.--17. "SHIFTRIGHT_NUM,Sects the amount to shift right the outgoing pixel from the EE block. 0: No Shift. 1: Shift by 2. 2: Shift by 4. 3: Reserved for future expansion." "0: No Shift,1: Shift by 2,2: Shift by 4,3: Reserved for future expansion" newline bitfld.long 0x4 12. "LLSE12_MUX_SEL,Selects Luma stream for the yuv12 output. 0: Bypass EE block. 1: Use EE Luma Output." "0: Bypass EE block,1: Use EE Luma Output" newline bitfld.long 0x4 8. "CLSE12_MUX_SEL,Selects Chroma stream for the yuv12 output. 0: Bypass EE block. 1: Use EE Chroma Output." "0: Bypass EE block,1: Use EE Chroma Output" newline bitfld.long 0x4 4. "LLSE8_MUX_SEL,Selects Luma stream for the yuv8 output. 0: Bypass EE block. 1: Use EE Luma Output." "0: Bypass EE block,1: Use EE Luma Output" newline bitfld.long 0x4 0. "CLSE8_MUX_SEL,Selects Chroma stream for the yuv8 output. 0: Bypass EE block. 1: Use EE Chroma Output." "0: Bypass EE block,1: Use EE Chroma Output" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_EE_ENABLE,The EE Enable register control the internal bypass of the EE block." bitfld.long 0x8 0. "YEE_ENABLE,The EE Enable register control the internal bypass of the EE block." "0,1" line.long 0xC "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_SHIFT,The YEE Shift register controls the down shift length of high pass filter (HPF) in edge enhancer" hexmask.long.byte 0xC 0.--5. 1. "YEE_SHIFT,The down shift length of high pass filter (HPF) in edge enhancer takes the output of the 5x5 HPF and shifts it by the selected amount. Only values 0-31 are valid." line.long 0x10 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R0_C0,The YEE Coefficient Row 0 Column 0 defines the Multiplier coefficient in HPF" hexmask.long.word 0x10 0.--9. 1. "YEE_COEF_R0_C0,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." line.long 0x14 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R0_C1,The YEE Coefficient Row 0 Column 1 defines the Multiplier coefficient in HPF" hexmask.long.word 0x14 0.--9. 1. "YEE_COEF_R0_C1,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." line.long 0x18 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R0_C2,The YEE Coefficient Row 0 Column 2 defines the Multiplier coefficient in HPF" hexmask.long.word 0x18 0.--9. 1. "YEE_COEF_R0_C2,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." rgroup.long 0x20++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R1_C0,The YEE Coefficient Row 1 Column 0 defines the Multiplier coefficient in HPF" hexmask.long.word 0x0 0.--9. 1. "YEE_COEF_R1_C0,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R1_C1,The YEE Coefficient Row 1 Column 1 defines the Multiplier coefficient in HPF" hexmask.long.word 0x4 0.--9. 1. "YEE_COEF_R1_C1,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R1_C2,The YEE Coefficient Row 1 Column 2 defines the Multiplier coefficient in HPF" hexmask.long.word 0x8 0.--9. 1. "YEE_COEF_R1_C2,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." rgroup.long 0x30++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R2_C0,The YEE Coefficient Row 2 Column 0 defines the Multiplier coefficient in HPF" hexmask.long.word 0x0 0.--9. 1. "YEE_COEF_R2_C0,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R2_C1,The YEE Coefficient Row 2 Column 1 defines the Multiplier coefficient in HPF" hexmask.long.word 0x4 0.--9. 1. "YEE_COEF_R2_C1,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R2_C2,The YEE Coefficient Row 2 Column 2 defines the Multiplier coefficient in HPF" hexmask.long.word 0x8 0.--9. 1. "YEE_COEF_R2_C2,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." rgroup.long 0x40++0x1F line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_E_THR,The Edge Enhancer lower threshold before referring to LUT." hexmask.long.word 0x0 0.--9. 1. "YEE_E_THR,The yee_e_thr is the Shrink Threshold before the LUT scaled by 16x." line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_MERGESEL,The Merge selects the output that is added to the target pixel." bitfld.long 0x4 0. "YEE_MERGESEL,The yee_mergesel selects either the sum of the LUT and edge sharpener output of the max of the absolute values from both. 0: selects the SUM. 1: elects the absolute value max." "0: selects the SUM,1: elects the absolute value max" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YES_E_HAL,The Halo selects Halo reduction mode." bitfld.long 0x8 0. "YES_E_HAL,The yes_e_hal selects whether the 3x3 gradients is used to clip the target pixel. 0: Halo reduction off. 1: Halo reduction on." "0: Halo reduction off,1: Halo reduction on" line.long 0xC "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YES_G_GAIN,The Edge sharpener. gain value on gradient" hexmask.long.byte 0xC 0.--7. 1. "YES_G_GAIN,Sets the Gradient Gain value" line.long 0x10 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YES_E_GAIN,The Edge sharpener gain" hexmask.long.word 0x10 0.--11. 1. "YES_E_GAIN,Sets the Edge sharpener Band-pass filter gain" line.long 0x14 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YES_E_THR1,The Edge sharpener HPF value lower limit" hexmask.long.word 0x14 0.--15. 1. "YES_E_THR1,Sets the Edge sharpener HPF value lower limit shrink threshold" line.long 0x18 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YES_E_THR2,The Edge sharpener HPF value upper limit (after 6 bit right shift)" hexmask.long.word 0x18 0.--9. 1. "YES_E_THR2,Sets the Edge sharpener HPF value upper limit (after 6 bit right shift) clip threshold" line.long 0x1C "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YES_G_OFT,The Edge sharpener. offset value on gradient" hexmask.long.word 0x1C 0.--9. 1. "YES_G_OFT,Sets the Edge sharpener offset value on gradient" rgroup.long 0x100++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_INT_STATUS,Status/clear register for flexee interrupts" bitfld.long 0x0 3. "EE_HZ_ALIGN8,status/clear for EE horizontal aligner yuv8 overflow error indicates that the luma and chroma line starts were not within hardware synchronization limits. Write 1 to clear write 0 has no effect." "0,1" newline bitfld.long 0x0 2. "EE_HZ_ALIGN12,status/clear for EE horizontal aligner yuv12 overflow error indicates that the luma and chroma line starts were not within hardware synchronization limits. Write 1 to clear write 0 has no effect." "0,1" newline bitfld.long 0x0 1. "EE_PIX_ERR,status/clear for error on line array set when software accesses EE pixel array during active frame causing potential frame corruption. Write 1 to clear write 0 has no effect." "0,1" newline bitfld.long 0x0 0. "EELUT_CFG_ERR,status/clear for error on EE LUT cfg set when software accesses EE LUT during active frame causing potential frame corruption. Write 1 to clear write 0 has no effect." "0,1" rgroup.long 0x1008++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_LINE_SEL,Selector for which line memory is read or written" bitfld.long 0x0 0.--2. "LINE_SELECTOR,Selects which line is read or written from the line memory array. The current line is updated at Start-Of-Line so if the memory is read during a line that is being written the data for the current_line will contain the new data for this.." "?,?,2: current line,3: current line,4: current side band line,5: current side band line,?,?" rgroup.long 0x2000++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_EELUT_RAM,The host will program the EE LUT RAM so that the pixels are translated from 14 bit to 12 bit using LUT entries." hexmask.long.word 0x0 16.--28. 1. "EELUT_ENTRY_HI,The lower EE LUT entry n+1." newline hexmask.long.word 0x0 0.--12. 1. "EELUT_ENTRY_LO,The lower EE LUT entry n+0." rgroup.long 0x4000++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_PIXEL_RAM,The pixel RAM contains the array of 12 bit pixels stored and used by the CFA logic. Pixels are 16 bit aligned. Pixels can only be written two at a time." hexmask.long.word 0x0 16.--27. 1. "PIXEL_HI,The 12 bit pixel data for the selected line upper pixel 'n+1'" newline hexmask.long.word 0x0 0.--11. 1. "PIXEL_LO,The 12 bit pixel data for the selected line lower pixel 'n'" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC)" base ad:0x3910000 rgroup.long 0x0++0x6B line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CFG_0,The Control Register controls the input width and height of the module." hexmask.long.word 0x0 16.--28. 1. "HEIGHT,Height of the input image" newline hexmask.long.word 0x0 0.--12. 1. "WIDTH,Width of the input image" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CFG_1,Configuration Register for top level data flow" bitfld.long 0x4 27. "CHROMA_MODE,Mux for 422/420 (0:420 Chroma 1: 422 Chroma)" "0,1" newline bitfld.long 0x4 26. "MUXRGBHSV_MUX_V,Mux for V calculation (0:Select non WB corrected data 1: Select WB corrected data)" "0: Select non WB corrected data,1: Select WB corrected data)" newline bitfld.long 0x4 25. "MUXRGBHSV_H2,Mux for S/V calculation (0:Select B 1: Select Max(RGB))" "0: Select B,1: Select Max" newline bitfld.long 0x4 24. "MUXRGBHSV_H1,Mux for S/V calculation (0:Select R 1: Select Min(RGB))" "0: Select R,1: Select Min" newline bitfld.long 0x4 18.--19. "S8B8OUTEN,'0': Disable All '1': S8 enable 2:B8 enable 3:C4 enable" "?,?,2: B8 enable,3: C4 enable" newline bitfld.long 0x4 16.--17. "C8G8OUTEN,'0': Disable All '1': C8 enable 2:G8 enable 3:C3 enable" "?,?,2: G8 enable,3: C3 enable" newline bitfld.long 0x4 14.--15. "Y8R8OUTEN,'0': Disable all '1': Y8 enable 2:R8 enable 3:C2 enable" "?,?,2: R8 enable,3: C2 enable" newline bitfld.long 0x4 12.--13. "C12OUTEN,'0': Disable all '1': C12 enable '2': C1 enable" "0,1,2,3" newline bitfld.long 0x4 11. "Y12OUTEN,'0': Disable Y12 output '1': Enable Y12 output" "0,1" newline bitfld.long 0x4 6. "MUXRGBHSV,Input Select for RGBHSV (0:In after Contrast 1: In before Contrast)" "0: In after Contrast,1: In before Contrast)" newline bitfld.long 0x4 4.--5. "MUXY8_OUT,Mux for Y-8 Output (0:MuxC1_4 1:RGB2YUV 2:RGB2HSV)" "0: MuxC1_4,1: RGB2YUV,2: RGB2HSV),?" newline bitfld.long 0x4 2.--3. "MUXY12_OUT,Mux for Y-12 Output (0:MuxC1_4 1:RGB2YUV 2:RGB2HSV 3:C1 enable)" "0: MuxC1_4,1: RGB2YUV,2: RGB2HSV,3: C1 enable)" newline bitfld.long 0x4 0.--1. "MUXC1_4,Mux for selecting C input (0:C0 1:C1 2:C2 3:C3)" "0: C0,1: C1,2: C2,3: C3)" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CFG_2,Configuration Register-2" hexmask.long.byte 0x8 13.--16. 1. "Y8INBITWIDTH,Bitwidth of input to 12to8 module (Y8) for shift(Program as 12 or lower)" newline hexmask.long.byte 0x8 9.--12. 1. "CONTRASTBITCLIP,Clip Value set as 2^ContrastBitClip -1" newline bitfld.long 0x8 8. "CONTRASTEN,0:Disable 1: Enable Contrast" "0: Disable,1: Enable Contrast" newline bitfld.long 0x8 6. "HSVSATMODE,0:Max(RGB) - Min(RGB) 1:Sum(RGB) - Min(RGB)" "0: Max,1: Sum" newline bitfld.long 0x8 4.--5. "HSVSATDIVMODE,0:One 1:Max(RGB) 2: 4095 -V 3:Sum(RGB)" "0: One,1: Max,?,3: Sum" newline bitfld.long 0x8 3. "SATLUTEN,'1':Use LUT '0':Use shift" "0,1" newline bitfld.long 0x8 2. "RGB8LUTEN,'1':Use LUT '0':Use shift" "0,1" newline bitfld.long 0x8 1. "Y8LUTEN,'1':Use LUT '0':Use shift" "0,1" newline bitfld.long 0x8 0. "C8LUTEN,'1':Use LUT '0':Use shift" "0,1" line.long 0xC "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CFG_Hist_1,Configuration-1 Register for histogram" hexmask.long.word 0xC 16.--28. 1. "HISTSTARTY,Y Start for Histogram ROI should be >= 1" newline bitfld.long 0xC 14. "BANK,bank select for Histogram" "0,1" newline hexmask.long.word 0xC 1.--13. 1. "HISTSTARTX,X Start for Histogram ROI should be even" newline bitfld.long 0xC 0. "HISTEN,Enable bit for histogram" "0,1" line.long 0x10 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CFG_Hist_2,Configuration-2 Register for histogram" hexmask.long.word 0x10 16.--28. 1. "HISTSIZEY,Y Size (Height) for Histogram ROI" newline bitfld.long 0x10 13.--15. "HISTMODE,Histogram Mode 0:Col-0(R) 1:Col-1(G) 2:Col-2(B) 3:MuxC1_4 4:(R+2G+B)/4 5:Col-0(R)" "0: Col-0,1: Col-1,2: Col-2,3: MuxC1_4,?,5: Col-0,?,?" newline hexmask.long.word 0x10 0.--12. 1. "HISTSIZEX,X Size (Width) for Histogram ROI should be > 256 & even" line.long 0x14 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CCM_W0_0_1,CCM Weights for Row0" hexmask.long.word 0x14 16.--27. 1. "W_1,Weight W_01 : (S12 b)" newline hexmask.long.word 0x14 0.--11. 1. "W_0,Weight W_00 : (S12 b)" line.long 0x18 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CCM_W0_2_3,CCM Weights for Row0" hexmask.long.word 0x18 16.--27. 1. "W_3,Weight W_03 : (S12 b)" newline hexmask.long.word 0x18 0.--11. 1. "W_2,Weight W_02 : (S12 b)" line.long 0x1C "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CCM_OFFSET_0,CCM OFFSET for Row0" hexmask.long.word 0x1C 0.--12. 1. "OFFSET_0,OFFSET_0 : (S13 b)" line.long 0x20 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CCM_W1_0_1,CCM Weights for Row1" hexmask.long.word 0x20 16.--27. 1. "W_1,Weight W_11 : (S12 b)" newline hexmask.long.word 0x20 0.--11. 1. "W_0,Weight W_10 : (S12 b)" line.long 0x24 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CCM_W1_2_3,CCM Weights for Row1" hexmask.long.word 0x24 16.--27. 1. "W_3,Weight W_13 : (S12 b)" newline hexmask.long.word 0x24 0.--11. 1. "W_2,Weight W_12 : (S12 b)" line.long 0x28 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CCM_OFFSET_1,CCM OFFSET for Row1" hexmask.long.word 0x28 0.--12. 1. "OFFSET_1,OFFSET_1 : (S13 b)" line.long 0x2C "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CCM_W2_0_1,CCM Weights for Row2" hexmask.long.word 0x2C 16.--27. 1. "W_1,Weight W_21 : (S12 b)" newline hexmask.long.word 0x2C 0.--11. 1. "W_0,Weight W_20 : (S12 b)" line.long 0x30 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CCM_W2_2_3,CCM Weights for Row2" hexmask.long.word 0x30 16.--27. 1. "W_3,Weight W_23 : (S12 b)" newline hexmask.long.word 0x30 0.--11. 1. "W_2,Weight W_22 : (S12 b)" line.long 0x34 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CCM_OFFSET_2,CCM OFFSET for Row2" hexmask.long.word 0x34 0.--12. 1. "OFFSET_2,OFFSET_2 : (S13 b)" line.long 0x38 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBYUV_W01,Weight/Offset for Row0" hexmask.long.word 0x38 16.--27. 1. "W_02,Weight W_02 : (S12 b)" newline hexmask.long.word 0x38 0.--11. 1. "W_01,Weight W_01 : (S12 b)" line.long 0x3C "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBYUV_W02,Weight/Offset for Row0" hexmask.long.word 0x3C 16.--28. 1. "OFFSET_0,Offset_0 : (S13b)" newline hexmask.long.word 0x3C 0.--11. 1. "W_03,Weight W_03 : (S12 b)" line.long 0x40 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBYUV_W11,Weight/Offset for Row1" hexmask.long.word 0x40 16.--27. 1. "W_12,Weight W_12 : (S12 b)" newline hexmask.long.word 0x40 0.--11. 1. "W_11,Weight W_11 : (S12 b)" line.long 0x44 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBYUV_W12,Weight/Offset for Row1" hexmask.long.word 0x44 16.--28. 1. "OFFSET_1,Offset_1 : (S13b)" newline hexmask.long.word 0x44 0.--11. 1. "W_13,Weight W_13 : (S12 b)" line.long 0x48 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBYUV_W21,Weight/Offset for Row2" hexmask.long.word 0x48 16.--27. 1. "W_22,Weight W_22 : (S12 b)" newline hexmask.long.word 0x48 0.--11. 1. "W_21,Weight W_21 : (S12 b)" line.long 0x4C "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBYUV_W22,Weight/Offset for Row2" hexmask.long.word 0x4C 16.--28. 1. "OFFSET_2,Offset_2 : (S13b)" newline hexmask.long.word 0x4C 0.--11. 1. "W_23,Weight W_23 : (S12 b)" line.long 0x50 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBHSV_W0,Weights 11/12 for V calculation" hexmask.long.word 0x50 16.--27. 1. "W12,Weight W12 (Signed 12b)" newline hexmask.long.word 0x50 0.--11. 1. "W11,Weight W11 (Signed 12b)" line.long 0x54 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBHSV_W1,Weights13 and Offset_1 for V Calculation" hexmask.long.word 0x54 16.--28. 1. "OFFSET_1,Offset_1 (Signed 13b)" newline hexmask.long.word 0x54 0.--11. 1. "W13,Weight W13 (Signed 12b)" line.long 0x58 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBHSV_WB_LINLOGTHR_1,Dynamic WB Thr limit" hexmask.long.word 0x58 16.--27. 1. "THR_1,THR_1 / G-Channel Thr (U 12b)" newline hexmask.long.word 0x58 0.--11. 1. "THR_0,THR_0 / R-Channel Thr (U 12b)" line.long 0x5C "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBHSV_WB_LINLOGTHR_2,Dynamic WB Thr limit and SatMinThr" hexmask.long.word 0x5C 16.--27. 1. "SATMINTHR,Thr for comparing Min(RGB) limit" newline hexmask.long.word 0x5C 0.--11. 1. "THR_2,THR_2 / B-Channel Thr (U 12b)" line.long 0x60 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBHSV_OFF1,WB Offset for Saturation" hexmask.long.word 0x60 16.--27. 1. "OFFSET_2,Offset_2 (U 12b)" newline hexmask.long.word 0x60 0.--11. 1. "OFFSET_1,Offset-1 (U 12b)" line.long 0x64 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBHSV_OFF2,WB Offsets for Saturation" hexmask.long.word 0x64 0.--11. 1. "OFFSET_3,Offset-3 (U 12b)" line.long 0x68 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_FLEXCC_INT_STATUS,Status/clear register for flexcc interrupts" bitfld.long 0x68 11. "HIST_READ_ERR,status/clear for histogram memory set when mem access has occurred to the first location but not to the last location during active frame implying that full histogram was not read . Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 10. "LUT_12TO82_CFG_ERR,status/clear for 12to8_2_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 9. "LUT_12TO81_CFG_ERR,status/clear for 12to8_1_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 8. "LUT_12TO80_CFG_ERR,status/clear for 12to8_0_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 7. "CONTRAST2_CFG_ERR,status/clear for contrast2_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 6. "CONTRAST1_CFG_ERR,status/clear for contrast1_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 5. "CONTRAST0_CFG_ERR,status/clear for contrast0_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 4. "OVERFLOW_IF_S8B8,status/clear for overflow on s8b8 i/f set when fifo overflows causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 3. "OVERFLOW_IF_C8G8,status/clear for overflow on c8g8 i/f set when fifo overflows causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 2. "OVERFLOW_IF_Y8R8,status/clear for overflow on y8r8 i/f set when fifo overflows causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 1. "OVERFLOW_IF_UV12,status/clear for overflow on uv12 i/f set when fifo overflows causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 0. "OVERFLOW_IF_Y12,status/clear for overflow on y12 i/f set when fifo overflows causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" rgroup.long 0x100++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_DEBUG_CTL,Enable for different debug events" bitfld.long 0x0 12. "FLEXCC_EOP_EN,Enable for flexcc eop" "0,1" newline bitfld.long 0x0 11. "EOF_IF_S8B8_EN,Enable for eof on s8b8" "0,1" newline bitfld.long 0x0 10. "EOL_IF_S8B8_EN,Enable for eol on s8b8" "0,1" newline bitfld.long 0x0 9. "EOF_IF_C8G8_EN,Enable for eof on c8g8" "0,1" newline bitfld.long 0x0 8. "EOL_IF_C8G8_EN,Enable for eol on c8g8" "0,1" newline bitfld.long 0x0 7. "EOF_IF_Y8R8_EN,Enable for eof on y8r8" "0,1" newline bitfld.long 0x0 6. "EOL_IF_Y8R8_EN,Enable for eol on y8r8" "0,1" newline bitfld.long 0x0 5. "EOF_IF_UV12_EN,Enable for eof on uv12" "0,1" newline bitfld.long 0x0 4. "EOL_IF_UV12_EN,Enable for eol on uv12" "0,1" newline bitfld.long 0x0 3. "EOF_IF_Y12_EN,Enable for eof on y12" "0,1" newline bitfld.long 0x0 2. "EOL_IF_Y12_EN,Enable for eol on y12" "0,1" newline bitfld.long 0x0 1. "STALL_EN,Enable for stall event" "0,1" newline bitfld.long 0x0 0. "DBG_EN,Enable debug features set to '0' to disable all debug events" "0,1" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_DEBUG_STATUS,Set/Clear for debug events" bitfld.long 0x4 12. "FLEXCC_EOP_EVENT,Status/Clear for flexcc eop write '1' to clear" "0,1" newline bitfld.long 0x4 11. "EOF_IF_S8B8_EVENT,Status/Clear for eof on s8b8 write '1' to clear" "0,1" newline bitfld.long 0x4 10. "EOL_IF_S8B8_EVENT,Status/Clear for eol on s8b8 write '1' to clear" "0,1" newline bitfld.long 0x4 9. "EOF_IF_C8G8_EVENT,Status/Clear for eof on c8g8 write '1' to clear" "0,1" newline bitfld.long 0x4 8. "EOL_IF_C8G8_EVENT,Status/Clear for eol on c8g8 write '1' to clear" "0,1" newline bitfld.long 0x4 7. "EOF_IF_Y8R8_EVENT,Status/Clear for eof on y8r8 write '1' to clear" "0,1" newline bitfld.long 0x4 6. "EOL_IF_Y8R8_EVENT,Status/Clear for eol on y8r8 write '1' to clear" "0,1" newline bitfld.long 0x4 5. "EOF_IF_UV12_EVENT,Status/Clear for eof on uv12 write '1' to clear" "0,1" newline bitfld.long 0x4 4. "EOL_IF_UV12_EVENT,Status/Clear for eol on uv12 write '1' to clear" "0,1" newline bitfld.long 0x4 3. "EOF_IF_Y12_EVENT,Status/Clear for eof on y12 write '1' to clear" "0,1" newline bitfld.long 0x4 2. "EOL_IF_Y12_EVENT,Status/Clear for eol on y12 write '1' to clear" "0,1" newline bitfld.long 0x4 1. "STALL_EVENT,Status/Clear for stall event write '1' to clear" "0,1" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_DEBUG_RAW,Set/Clear for debug RAW mode" bitfld.long 0x8 0. "DBG_RAW_MODE,Enable debug RAW mode takes input from RAWFE and delivers to FlexCC as C1={raw[11:0]} C2={4'd0 raw[7:0]} C3={4'd0 raw[15:8]} c4={8'd0 raw[15:12]}" "0,1" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_C8G8 (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_C8G8)" base ad:0x3912800 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_C8G8_LUT_C8G8,Memory for 12to8 LUT" hexmask.long.byte 0x0 16.--23. 1. "LUT_1,Bank-1" hexmask.long.byte 0x0 0.--7. 1. "LUT_0,Bank-0" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC1 (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC1)" base ad:0x3910800 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_CONTRASTC1_LUT_contrastC1,Memory for contrast C1" hexmask.long.word 0x0 16.--27. 1. "LUT_1,Bank-1" hexmask.long.word 0x0 0.--11. 1. "LUT_0,Bank-0" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC2 (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC2)" base ad:0x3911000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_CONTRASTC2_LUT_contrastC2,Memory for contrast C1" hexmask.long.word 0x0 16.--27. 1. "LUT_1,Bank-1" hexmask.long.word 0x0 0.--11. 1. "LUT_0,Bank-0" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC3 (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC3)" base ad:0x3911800 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_CONTRASTC3_LUT_contrastC3,Memory for contrast C1" hexmask.long.word 0x0 16.--27. 1. "LUT_1,Bank-1" hexmask.long.word 0x0 0.--11. 1. "LUT_0,Bank-0" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_HIST (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_HIST)" base ad:0x3913800 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_HIST_HIST,Memory for Histogram" hexmask.long.tbyte 0x0 0.--19. 1. "HIST_VAL,Bank-0" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_LINE (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_LINE)" base ad:0x3918000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_LINE_LINE_MEM,Memory for 2 lines of yuv444to420" hexmask.long.word 0x0 16.--27. 1. "LINE_1,Line-1" hexmask.long.word 0x0 0.--11. 1. "LINE_0,Line-0" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_S8B8 (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_S8B8)" base ad:0x3913000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_S8B8_LUT_S8B8,Memory for 12to8 LUT" hexmask.long.byte 0x0 16.--23. 1. "LUT_1,Bank-1" hexmask.long.byte 0x0 0.--7. 1. "LUT_0,Bank-0" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_Y8R8 (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_Y8R8)" base ad:0x3912000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_Y8R8_LUT_Y8R8,Memory for 12to8 LUT" hexmask.long.byte 0x0 16.--23. 1. "LUT_1,Bank-1" hexmask.long.byte 0x0 0.--7. 1. "LUT_0,Bank-0" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_MEM_MMRRAM_VBUSP_MMR_RAM (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_MEM_MMRRAM_VBUSP_MMR_RAM)" base ad:0x3944000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_DBG_MEM,Warning: reading or writing this MMR during operation will corrupt processing resulting in bad output data and will result in error interrupt firing." hexmask.long 0x0 0.--31. 1. "DATA,Adr range selects which RAM address to index. (Wr or rd beyond populated RAM adr result in non productive cycles and rd returns zero)" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_MMR_VBUSP_NSF4VCORE (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_MMR_VBUSP_NSF4VCORE)" base ad:0x3940000 rgroup.long 0x4++0x13 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_dbg,Diagnostic Register Control" hexmask.long.byte 0x0 0.--5. 1. "RAM_MUX_CFG,Diagnostic Rd Wr access to Embedded RAM Selector Mux. This bit controls the mux select or which RAM and which section of that RAM are assessed via the VBUSP read of RAM. (This MMR is not shadowed)" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_ctrl,All modes are set here" bitfld.long 0x4 12. "LSCC_EN_CFG,enable Lens Shading Correction Compensation. When disabled implments a unity gain" "0,1" newline hexmask.long.byte 0x4 8.--11. 1. "LSCC_SETSEL_CFG,bit per BAYER color component indicating which of two sets of 16 segment PWL Curve to use for LSCC. 0: use set0 1: use set1" newline bitfld.long 0x4 4. "TN_MODE_CFG,single bit controlling T_n calculation 0: use u_mode bits to indicate which LL2 to average and which bits to keep independent without averaging 1: independent no averaging" "0: use u_mode bits to indicate which LL2 to average..,1: independent no averaging" newline hexmask.long.byte 0x4 0.--3. 1. "U_MODE_CFG,bit per BAYER color component indicating Decomp sub component 0: average with others 1: independent color component do not average for calculation of U Suppress. bit[0]:color 0 at (v=0 h=0) bit[1]:color 1 at (v=0 h=1) bit[2]:color 2.." line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_dim,Input Output Frame dimensions in units of pixels. Same value for input and output" hexmask.long.word 0x8 16.--28. 1. "IH_CFG,(U13) input height in units of pixels minus 1." newline hexmask.long.word 0x8 0.--12. 1. "IW_CFG,(U13) input width in units of pixels minus 1. Max usable value determined by populated line buffer RAM size" line.long 0xC "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_LSCC,Lens Shading Correction Compensation. First control register" hexmask.long.word 0xC 20.--28. 1. "GMAX_CFG,(U4.5) LSCC maximum gain. Any calculated value is clipped to this max value" newline hexmask.long.byte 0xC 16.--19. 1. "T_CFG,(U4) LSCC radius dynamic range select. T is the right shift amount prior to MSB clip." newline hexmask.long.byte 0xC 8.--15. 1. "KV_CFG,(U2.6) LSCC horizontal or Y Gain for elliptical lens" newline hexmask.long.byte 0xC 0.--7. 1. "KH_CFG,(U2.6) LSCC vertical or X Gain for elliptical lens" line.long 0x10 "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_LSCC_cent,Lens Shading Correction Compensation. Programmable Center of frame" hexmask.long.word 0x10 16.--29. 1. "Y_CFG,(S14) Vertical (Y) position of lens center. Negative value supports the case where processed frame starts after the center. HW supports center config with below constraint. if (Y_cfg < 0) # negative DIM.ih_cfg + abs(Y_cfg) < 8K else #.." newline hexmask.long.word 0x10 0.--13. 1. "X_CFG,(S14) Horizontal (X) position of lens center. Negative value supports the case where processed frame starts after the center. HW supports center config with below constraint. if (X_cfg < 0) # negative DIM.iw_cfg + abs(X_cfg) < 8K else #.." rgroup.long 0x1C++0xF line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_Tn_Scale,Tn scaling factor multiplied by all 4 color components Tn after 12 segment PWL. Different scaling factor per level" hexmask.long.byte 0x0 16.--23. 1. "TN3_CFG,(U3.5) Level3. Sub-bands 7 8 9" newline hexmask.long.byte 0x0 8.--15. 1. "TN2_CFG,(U3.5) Level2. Sub-bands 4 5 6" newline hexmask.long.byte 0x0 0.--7. 1. "TN1_CFG,(U3.5) Level1. Sub-bands 0 1 2" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_U_knee,U suppression curve knee. Same knee value for all 9 levels x 4 color components." hexmask.long.byte 0x4 0.--5. 1. "U_KNEE_CFG,(U0.6) U Suppress curve knee. X (LL2) value which separates constant suppression of 1.0 from linear suppression." line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_WhiteBal0,White Balance Gain (Part0). Separate Gain for each of 4 colors" hexmask.long.word 0x8 16.--28. 1. "GAIN1_CFG,(U4.9) Gain for color 1" newline hexmask.long.word 0x8 0.--12. 1. "GAIN0_CFG,(U4.9) Gain for color 0" line.long 0xC "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_WhiteBal1,White Balance Gain (Part1). Separate Gain for each of 4 colors" hexmask.long.word 0xC 16.--28. 1. "GAIN3_CFG,(U4.9) Gain for color 3" newline hexmask.long.word 0xC 0.--12. 1. "GAIN2_CFG,(U4.9) Gain for color 2" rgroup.long 0x3F0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_DWB_CNTL,Dynamic White Balance Control Register" bitfld.long 0x0 0. "DWB_EN,Dynamic White Balance Enable" "0,1" rgroup.long 0x5F0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_Hist_Ctrl,Has control parameters related to Raw Domain Histogram" hexmask.long.byte 0x0 16.--23. 1. "ROI_EN,Enable for ROIs. Each bit corresponds to one ROI. bit[x] to ROI[x]. Use lower index regions if less than 8 regions are needed." newline hexmask.long.byte 0x0 9.--13. 1. "INBITWDTH,BitWidth of the input image values greater than 16 will be treated as 16 and values less than 12 will be treated as 12" newline bitfld.long 0x0 8. "LUT_EN,0->Use shift(bitwidth-12) 1->Use LUT" "0: Use shift,1: Use LUT" newline bitfld.long 0x0 5. "BANK,Bank attached to Histogram HW Datapath. Shadowed and internal control is updated outisde of active frame 0 -> HW access Bank0 & Cfg MMR access Bank1 1 -> HW access Bank1 & Cfg MMR access Bank0." "0: HW access Bank0 & Cfg MMR access Bank1 1,?" newline hexmask.long.byte 0x0 1.--4. 1. "PHASESEL,Histogram Phase select enable; one bit for each color channel. Up to 2 bits can be enabled; only bit can be enabled per line. bit[0]:color 0 at (v=0 h=0) bit[1]:color 1 at (v=0 h=1) bit[2]:color 2 at (v=1 h=0) bit[3]:color 3 at (v=1 h=1)" newline bitfld.long 0x0 0. "HIST_EN,Raw domain Histogram Enable. When enbaled minimum frame width has to be 128" "0,1" rgroup.long 0x500++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_dwb_wght01,Weights to calculate intensity" hexmask.long.word 0x0 16.--24. 1. "W1,U9Q8 Weight1" newline hexmask.long.word 0x0 0.--8. 1. "W0,U9Q8 Weight0" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_dwb_wght23,Weights to calculate intensity" hexmask.long.word 0x4 16.--24. 1. "W3,U9Q8 Weight3" newline hexmask.long.word 0x4 0.--8. 1. "W2,U9Q8 Weight2" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_dwb_wght45,Weights to calculate intensity" hexmask.long.word 0x8 16.--24. 1. "W5,U9Q8 Weight5" newline hexmask.long.word 0x8 0.--8. 1. "W4,U9Q8 Weight4" rgroup.long 0x600++0x7 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_Start,Start Pixel location for the region" hexmask.long.word 0x0 16.--28. 1. "STARTY,Valid line start Vertically. Needs to be even. Minimum is 2 and should be greater than previous region EndY" newline hexmask.long.word 0x0 0.--12. 1. "STARTX,Valid pixel start Horizontally. Has to be even" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_End,End Pixel location for the region" hexmask.long.word 0x4 16.--28. 1. "ENDY,Valid line end Vertically. Min region height is 8 and region height has to be even" newline hexmask.long.word 0x4 0.--12. 1. "ENDX,Valid pixel end Horizontally. Min region width is 8 and region width has to be even" rgroup.long 0x60++0x7 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_tn0,T_n 12 segment piecewise linear curve Part0 (4 color x 12 segment)" hexmask.long.word 0x0 16.--30. 1. "Y_CFG,(U15) Y (U) value. T_n resulting value from lookup. Starting point from which SLOPE will linearly calculate between X Y points" newline hexmask.long.word 0x0 0.--15. 1. "X_CFG,(U16) X (LL2) value. LL2 averaged input value into lookup rounded down to nearest X value. (X0 programmed value is unused and defaults to a value of 0 in hardware implementation)" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_tn1,T_n 12 segment piecewise linear curve Part1 (4 color x 12 segment)" hexmask.long.word 0x4 0.--15. 1. "S_CFG,(S5.11) S value. Slope value used calculated linear interpolation between X Y points" rgroup.long 0x200++0x7 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_lsccCurve0,LSCC 16 segment piecewise linear curve Part0 (2 set x 16 segment)" hexmask.long.word 0x0 16.--24. 1. "Y_CFG,(U15.0) Y (U) value. LSCC Gain resulting value from lookup. Starting point from which SLOPE will linearly calculate between X Y points" newline hexmask.long.word 0x0 0.--15. 1. "X_CFG,(U16) X (normalized radius from center) value. Input rounded down to nearest X value. (X0 programmed value is unused and defaults to a value of 0 in hardware implementation)" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_lsccCurve1,LSCC 16 segment piecewise linear curve Part1 (2 set x 16 segment)" hexmask.long.word 0x4 0.--15. 1. "S_CFG,(S5.11) S value. Slope value used calculated linear interpolation between X Y points" rgroup.long 0x400++0x7 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_dwbCurve0,Dynamic WB 8 segment piecewise linear curve Part0. 4 color x 8 segment" hexmask.long.word 0x0 16.--27. 1. "Y_CFG,U12Q8 Y Reference value from the segment. Starting point from which SLOPE will linearly calculate between X Y points" newline hexmask.long.word 0x0 0.--15. 1. "X_CFG,U16 X Intesity value. X0 programmed value is unused and defaults to a value of 0 in hardware implementation" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_dwbCurve1,Dynamic WB 8 segment piecewise linear curve Part1 (4 color x 8 segment)" hexmask.long.word 0x4 0.--15. 1. "S_CFG,S16Q12 Slope value for the segment. Slope value used calculated linear interpolation between X Y points" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_RAWHIST_HISTDATA_VBUSP_RAWHIST (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_RAWHIST_HISTDATA_VBUSP_RAWHIST)" base ad:0x3940800 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__RAWHIST__HISTDATA_VBUSP__RAWHIST_HIST,Memory for Histogram" hexmask.long.tbyte 0x0 0.--21. 1. "HIST_VAL,Histogram Data" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_RAWHIST_HISTLUT_VBUSP_RAWHIST_LUT (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_RAWHIST_HISTLUT_VBUSP_RAWHIST_LUT)" base ad:0x3941000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__RAWHIST__HISTLUT_VBUSP__RAWHIST_LUT_HIST_LUT,LUT to convert from 16-bit to 12-bit" hexmask.long.word 0x0 16.--27. 1. "LUT_1,Entry 2*n+1 in Bank-1" hexmask.long.word 0x0 0.--11. 1. "LUT_0,Entry 2*n in Bank-0" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_DPC_LRAM_RAWFE_DPC_LRAM (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_DPC_LRAM_RAWFE_DPC_LRAM)" base ad:0x3924000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__DPC__LRAM__RAWFE_DPC_LRAM_ram1,Input image width and height." tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_DPC_RAM_RAWFE_DPC_LUT_RAM (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_DPC_RAM_RAWFE_DPC_LUT_RAM)" base ad:0x3923000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__DPC__RAM__RAWFE_DPC_LUT_RAM_ram1,Input image width and height." tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_LUT_RAM_RAWFE_H3A_LUT_RAM (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_LUT_RAM_RAWFE_H3A_LUT_RAM)" base ad:0x3922800 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_LUT__RAM__RAWFE_H3A_LUT_RAM_ram1,Input image width and height." tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_WRAP_ARAM_RAWFE_H3A_ARAM (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_WRAP_ARAM_RAWFE_H3A_ARAM)" base ad:0x3930000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__ARAM__RAWFE_H3A_ARAM_ram1,Input image width and height." tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_WRAP_CFG_RAWFE_H3A_CFG (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_WRAP_CFG_RAWFE_H3A_CFG)" base ad:0x3920400 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_PID,Peripheral Revision and Class Information" bitfld.long 0x0 30.--31. "SCHEME,PID scheme type" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,PID func revision" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,PID rtl revision" newline bitfld.long 0x0 8.--10. "MAJOR,PID major revision" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,PID minor revision" rgroup.long 0x4++0x7B line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_PCR,Peripheral Control Register" hexmask.long.word 0x0 22.--31. 1. "AVE2LMT,AE/AWB Saturation Limit This is the value that all sub sampled pixels in the AE/AWB engine are compared to If the data is greater or equal to this data then the block is considered saturated" newline bitfld.long 0x0 21. "OVF,H3A module overflow status bit If the H3A module overflows it will keep sending data The software can read this status bit during vertical blanking period to ensure that no overflow happened while writing out the data to SDRAM There is also an.." "0,1" newline bitfld.long 0x0 20. "AF_VF_EN,AF Vertical Focus Enable" "0,1" newline bitfld.long 0x0 19. "AEW_MED_EN,AE/AWB Median filter Enable If the median filter is enabled then the 1st 2 and last 2 pixels in the frame are not filtered" "0,1" newline rbitfld.long 0x0 18. "BUSYAEAWB,Busy bit for AE/AWB" "0,1" newline bitfld.long 0x0 17. "AEW_ALAW_EN,AE/AWB A-law Enable" "0,1" newline bitfld.long 0x0 16. "AEW_EN,AE/AWB enable" "0,1" newline rbitfld.long 0x0 15. "BUSYAF,Busy bit for AF" "0,1" newline bitfld.long 0x0 14. "FVMODE,Focus Value Accumulation Mode" "0,1" newline bitfld.long 0x0 11.--13. "RGBPOS,Red Green and blue pixel location in the AF windows RGBPOS[0]: GR and GB as Bayer pattern RGBPOS[1]: RG and GB as Bayer pattern RGBPOS[2]: GR and BG as Bayer pattern RGBPOS[3]: RG and BG as Bayer pattern RGBPOS[4]: GG and RB as custom pattern.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 3.--10. 1. "MED_TH,Median filter threshold" newline bitfld.long 0x0 2. "AF_MED_EN,Auto Focus Median filter Enable If the median filter is enabled then the 1st 2 and last 2 pixels in the frame are not in the valid region Therefore the paxel start/end and IIR filter start positions should not be set within the 1st and last 2.." "0,1" newline bitfld.long 0x0 1. "AF_ALAW_EN,AF A-law table enable" "0,1" newline bitfld.long 0x0 0. "AF_EN,AF enable" "0,1" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFPAX1,Setup for the AF Engine Paxel Configuration" hexmask.long.byte 0x4 16.--23. 1. "PAXW,AF Engine Paxel Width The width of the paxel is the value of this register plus 1 multiplied by 2 The minimum width is 16 pixels if pixel clock is or less of the vpss clock If pixel clock is equal to vpss clock the minimum width is 32 pixels * This.." newline hexmask.long.byte 0x4 0.--7. 1. "PAXH,AF Engine Paxel Height The height of the paxel is the value of this register plus 1 multiplied by 2 with a final value of 2-256 [even] * This value is shadowed and latched on the rising edge of VSYNC" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFPAX2,Setup for the AF Engine Paxel Configuration" hexmask.long.byte 0x8 17.--20. 1. "AFINCH,AF Engine Column Increments Number of columns to increment in a paxel plus 1 multiplied by 2 Thus the number of columns that can be skipped between two processed line pairs is 2-32 [even] The starting two columns in a paxel are first processed.." newline hexmask.long.byte 0x8 13.--16. 1. "AFINCV,AF Engine Line Increments Number of lines to increment in a Paxel plus 1 multiplied by 2 Incrementing the line in a paxel is always done on a line pair due to the fact that the RGB pattern falls in two lines If all the lines are to be processed .." newline hexmask.long.byte 0x8 6.--12. 1. "PAXVC,AF Engine Vertical Paxel Count The number of paxels in the vertical direction plus 1 The maximum number of vertical paxels in a frame should not exceed 128 The value should be set to ensure that the bandwidth requirements and buffer size are not.." newline hexmask.long.byte 0x8 0.--5. 1. "PAXHC,AF Engine Horizontal Paxel Count The number of paxels in the horizontal direction plus 1 It is illegal to set a number that is greater than 35 [total of 36 paxels in the horizontal direction] The minimum number of paxels should be 2 [valid range.." line.long 0xC "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFPAXSTART,Start Position for AF Engine Paxels" hexmask.long.word 0xC 16.--27. 1. "PAXSH,AF Engine Paxel Horizontal start position Range: 2-4094 PAXSH must be equal to or greater than [IIRSH + 2] This value must be even if Vertical mode is not enabled If Vertical mode is enabled then the lower bit of PAXSH and IIRSH must be equal *.." newline hexmask.long.word 0xC 0.--11. 1. "PAXSV,AF Engine Paxel Vertical start position Range: 0-4095 Sets the vertical line for the first paxel This value must be greater then or equal to 8 if the vertical mode is enabled * This value is shadowed and latched on the rising edge of VSYNC" line.long 0x10 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFIIRSH,Start Position for IIRSH" hexmask.long.word 0x10 0.--11. 1. "IIRSH,AF Engine IIR Horizontal Start Position Range from 0-4094 When the horizontal position of a line equals this value the shift registers are cleared on the next pixel This value must be even if Vertical mode is not enabled If vertical mode is enabled.." line.long 0x14 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFBUFST,SDRAM destination address for AF engine statistics" hexmask.long 0x14 5.--31. 1. "AFBUFST,SDRAM destination address for AF engine statistics The SDRAM destination address for the AF statistics The 6 LSBs are ignored address shall be on a 64-byte boundary This field can be altered even when the AF is busy Change will take place only.." line.long 0x18 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF010,IIR filter coefficient data for SET 0." hexmask.long.word 0x18 16.--27. 1. "COEFF1,AF Engine IIR filter Coefficient #1 [Set 0] The range is signed -32 <= value <= 31 +63/64" newline hexmask.long.word 0x18 0.--11. 1. "COEFF0,AF Engine IIR filter Coefficient #0 [Set 0] The range is signed -32 <= value <= 31 +63/64" line.long 0x1C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF032,IIR filter coefficient data for SET 0." hexmask.long.word 0x1C 16.--27. 1. "COEFF3,AF Engine IIR filter Coefficient #3 [Set 0] The range is signed -32 <= value <= 31 +63/64" newline hexmask.long.word 0x1C 0.--11. 1. "COEFF2,AF Engine IIR filter Coefficient #2 [Set 0] The range is signed -32 <= value <= 31 +63/64" line.long 0x20 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF054,IIR filter coefficient data for SET 0." hexmask.long.word 0x20 16.--27. 1. "COEFF5,AF Engine IIR filter Coefficient #5 [Set 0] The range is signed -32 <= value <= 31 +63/64" newline hexmask.long.word 0x20 0.--11. 1. "COEFF4,AF Engine IIR filter Coefficient #4 [Set 0] The range is signed -32 <= value <= 31 +63/64" line.long 0x24 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF076,IIR filter coefficient data for SET 0." hexmask.long.word 0x24 16.--27. 1. "COEFF7,AF Engine IIR filter Coefficient #7 [Set 0] The range is signed -32 <= value <= 31 +63/64" newline hexmask.long.word 0x24 0.--11. 1. "COEFF6,AF Engine IIR filter Coefficient #6 [Set 0] The range is signed -32 <= value <= 31 +63/64" line.long 0x28 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF098,IIR filter coefficient data for SET 0." hexmask.long.word 0x28 16.--27. 1. "COEFF9,AF Engine IIR filter Coefficient #9 [Set 0] The range is signed -32 <= value <= 31 +63/64" newline hexmask.long.word 0x28 0.--11. 1. "COEFF8,AF Engine IIR filter Coefficient #8 [Set 0] The range is signed -32 <= value <= 31 +63/64" line.long 0x2C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF0010,IIR filter coefficient data for SET 0." hexmask.long.word 0x2C 0.--11. 1. "COEFF10,AF Engine IIR filter Coefficient #10 [Set 0] The range is signed -32 <= value <= 31 +63/64" line.long 0x30 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF110,IIR filter coefficient data for SET 1." hexmask.long.word 0x30 16.--27. 1. "COEFF1,AF Engine IIR filter Coefficient #1 [Set 1] The range is signed -32 <= value <= 31 +63/64" newline hexmask.long.word 0x30 0.--11. 1. "COEFF0,AF Engine IIR filter Coefficient #0 [Set 1] The range is signed -32 <= value <= 31 +63/64" line.long 0x34 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF132,IIR filter coefficient data for SET 1." hexmask.long.word 0x34 16.--27. 1. "COEFF3,AF Engine IIR filter Coefficient #3 [Set 1] The range is signed -32 <= value <= 31 +63/64" newline hexmask.long.word 0x34 0.--11. 1. "COEFF2,AF Engine IIR filter Coefficient #2 [Set 1] The range is signed -32 <= value <= 31 +63/64" line.long 0x38 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF154,IIR filter coefficient data for SET 1." hexmask.long.word 0x38 16.--27. 1. "COEFF5,AF Engine IIR filter Coefficient #5 [Set 1] The range is signed -32 <= value <= 31 +63/64" newline hexmask.long.word 0x38 0.--11. 1. "COEFF4,AF Engine IIR filter Coefficient #4 [Set 1] The range is signed -32 <= value <= 31 +63/64" line.long 0x3C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF176,IIR filter coefficient data for SET 1." hexmask.long.word 0x3C 16.--27. 1. "COEFF7,AF Engine IIR filter Coefficient #7 [Set 1] The range is signed -32 <= value <= 31 +63/64" newline hexmask.long.word 0x3C 0.--11. 1. "COEFF6,AF Engine IIR filter Coefficient #6 [Set 1] The range is signed -32 <= value <= 31 +63/64" line.long 0x40 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF198,IIR filter coefficient data for SET 1." hexmask.long.word 0x40 16.--27. 1. "COEFF9,AF Engine IIR filter Coefficient #9 [Set 1] The range is signed -32 <= value <= 31 +63/64" newline hexmask.long.word 0x40 0.--11. 1. "COEFF8,AF Engine IIR filter Coefficient #8 [Set 1] The range is signed -32 <= value <= 31 +63/64" line.long 0x44 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF1010,IIR filter coefficient data for SET 1." hexmask.long.word 0x44 0.--11. 1. "COEFF10,AF Engine IIR filter Coefficient #10 [Set 1] The range is signed -32 <= value <= 31 +63/64" line.long 0x48 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AEWWIN1,Configuration for AE/AWB Windows." hexmask.long.byte 0x48 24.--31. 1. "WINH,AE/AWB Engine Window Height This specifies the window height in an even number of pixels the window height is the value plus 1 multiplied by 2 The final value can be from 2-512 [even] * This value is shadowed and latched on the rising edge of VSYNC" newline hexmask.long.byte 0x48 13.--20. 1. "WINW,AE/AWB Engine Window Width This specifies the window width in an even number of pixels the window width is the value plus 1 multiplied by 2 The minimum width is expected to be 8 pixels * This value is shadowed and latched on the rising edge of VSYNC" newline hexmask.long.byte 0x48 6.--12. 1. "WINVC,AE/AWB Engine Vertical Window Count The number of windows in the vertical direction plus 1 The maximum number of vertical windows in a frame should not exceed 128 The value should be set to ensure that the bandwidth requirements and buffer size are.." newline hexmask.long.byte 0x48 0.--5. 1. "WINHC,AE/AWB Engine Horizontal Window Count The number of horizontal windows plus 1 The maximum number of horizontal windows is 35 plus 1 [36] The minimum number of windows should be 2 [valid range for the field is 1-35] * This value is shadowed and.." line.long 0x4C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AEWINSTART,Start position for AE/AWB Windows." hexmask.long.word 0x4C 16.--27. 1. "WINSV,AE/AWB Engine Vertical Window Start Position Sets the first line for the first window Range 0-4095 * This value is shadowed and latched on the rising edge of VSYNC" newline hexmask.long.word 0x4C 0.--11. 1. "WINSH,AE/AWB Engine Horizontal Window Start Position Sets the horizontal position for the first window on each line Range 0-4095 * This value is shadowed and latched on the rising edge of VSYNC" line.long 0x50 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AEWINBLK,Start position and height for black line of AE/AWB Windows" hexmask.long.word 0x50 16.--27. 1. "WINSV,AE/AWB Engine Vertical Window Start Position for single black line of windows Sets the first line for the single black line of windows * This value is shadowed and latched on the rising edge of VSYNC Range 0-4095 Note that the horizontal start and.." newline hexmask.long.byte 0x50 0.--6. 1. "WINH,AE/AWB Engine Window Height for the single black line of windows This specifies the window height in an even number of pixels the window height is the value plus 1 multiplied by 2 The final value can be from 2-256 [even] * This value is shadowed.." line.long 0x54 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AEWSUBWIN,Configuration for subsample data in AE/AWB window." hexmask.long.byte 0x54 8.--11. 1. "AEWINCV,AE/AWB Engine Vertical Sampling Point Increment Sets vertical distance between sub-samples within a window plus 1 multiplied by 2 The final range is 2-32 * This value is shadowed and latched on the rising edge of VSYNC" newline hexmask.long.byte 0x54 0.--3. 1. "AEWINCH,AE/AWB Engine Horizontal Sampling Point Increment Sets horizontal distance between sub-samples within a window plus 1 multiplied by 2 The final range is 2-32 * This value is shadowed and latched on the rising edge of VSYNC" line.long 0x58 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AEWBUFST,SDRAM destination address for AE/AWB engine statistics" hexmask.long 0x58 5.--31. 1. "AEWBUFST,SDRAM destination address for AE/AWB engine statistics The start location in SDRAM for the AE/AWB statistics The 6 LSB are ignored address should be on a 64-byte boundary This field can be altered even when the AE/AWB is busy Change will take.." line.long 0x5C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AEWCFG,Configuration for AE/AWB" bitfld.long 0x5C 8.--9. "AEFMT,AE/AWB output format 0 = sum of squares 1 = min/max 2 = sum only; no sum of squares or min/max * This value is shadowed and latched on the rising edge of VSYNC" "0: sum of squares,1: min/max,2: sum only; no sum of squares or min/max * This..,?" newline hexmask.long.byte 0x5C 0.--3. 1. "SUMSHFT,AE/AWB engine shift value for the accumulation of pixel values This bitfield sets the right shift value which is applied on the result of the pixel accumulation before it is stored in the packet The accumulation takes place on 26 bits which is.." line.long 0x60 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_LINE_START,Line Framing Logic Register" hexmask.long.word 0x60 16.--31. 1. "SLV,Start Line Vertical Specifies how many lines after the VD rising edge the real frame starts" newline hexmask.long.word 0x60 0.--15. 1. "LINE_START,Line Start The framing module uses the LINE_START bitfield to find the position of the first pixel to place into the line buffer Range: 0-65535" line.long 0x64 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_VFV_CFG1,Vertical focus value configuration 1." hexmask.long.byte 0x64 24.--31. 1. "VCOEF1_3,Vertical FV FIR 1 coefficient 3" newline hexmask.long.byte 0x64 16.--23. 1. "VCOEF1_2,Vertical FV FIR 1 coefficient 2" newline hexmask.long.byte 0x64 8.--15. 1. "VCOEF1_1,Vertical FV FIR 1 coefficient 1" newline hexmask.long.byte 0x64 0.--7. 1. "VCOEF1_0,Vertical FV FIR 1 coefficient 0" line.long 0x68 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_VFV_CFG2,Vertical focus value configuration 2." hexmask.long.word 0x68 16.--31. 1. "VTHR1,Threshold for vertical FV FIR 1" newline hexmask.long.byte 0x68 0.--7. 1. "VCOEF1_4,Vertical FV FIR 1 coefficient 4" line.long 0x6C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_VFV_CFG3,Vertical focus value configuration 4." hexmask.long.byte 0x6C 24.--31. 1. "VCOEF2_3,Vertical FV FIR 2 coefficient 3" newline hexmask.long.byte 0x6C 16.--23. 1. "VCOEF2_2,Vertical FV FIR 2 coefficient 2" newline hexmask.long.byte 0x6C 8.--15. 1. "VCOEF2_1,Vertical FV FIR 2 coefficient 1" newline hexmask.long.byte 0x6C 0.--7. 1. "VCOEF2_0,Vertical FV FIR 2 coefficient 0" line.long 0x70 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_VFV_CFG4,Vertical focus value configuration 4." hexmask.long.word 0x70 16.--31. 1. "VTHR2,Threshold for vertical FV FIR 2" newline hexmask.long.byte 0x70 0.--7. 1. "VCOEF2_4,Vertical FV FIR 2 coefficient 4" line.long 0x74 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_HVF_THR,Horizontal Focus Value Threshold" hexmask.long.word 0x74 16.--31. 1. "HTHR2,Threshold for horizontal FV IIR 2" newline hexmask.long.word 0x74 0.--15. 1. "HTHR1,Threshold for horizontal FV IIR 1" line.long 0x78 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_ADVANCED,advanced setting register. NOT FOR TRM" hexmask.long.word 0x78 16.--31. 1. "ID,Below information should not be in TRM To access the other bitfields [AF_MODE/AEW_MODE] certain value should be written to this ID field first First the ID is written to this field Second the AF_MODE or/and AEW_MODE is written" newline bitfld.long 0x78 4. "AEW_MODE,This bit should not be included in TRM This bit is accesible only if ID is set to 0xDC00 AE/AWB engine custom mode [AVE2 mode] select" "0,1" newline bitfld.long 0x78 0. "AF_MODE,AF engine mode Below information should not be included in TRM The effect of this bit changes based on the ID value If other value than 0xCA00 or 0xDC00 is set to ID this field has no effect" "0,1" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_WRAP_LRAM_RAWFE_H3A_LRAM (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_WRAP_LRAM_RAWFE_H3A_LRAM)" base ad:0x3932000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__LRAM__RAWFE_H3A_LRAM_ram1,Input image width and height." tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LSC_RAM_RAWFE_LSC_LUT_RAM (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LSC_RAM_RAWFE_LSC_LUT_RAM)" base ad:0x3928000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__LSC__RAM__RAWFE_LSC_LUT_RAM_ram1,Input image width and height." tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LUT1_RAM_RAWFE_PWL_LUT1_RAM (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LUT1_RAM_RAWFE_PWL_LUT1_RAM)" base ad:0x3921800 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__LUT1__RAM__RAWFE_PWL_LUT1_RAM_ram1,Input image width and height." tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LUT2_RAM_RAWFE_PWL_LUT2_RAM (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LUT2_RAM_RAWFE_PWL_LUT2_RAM)" base ad:0x3921000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__LUT2__RAM__RAWFE_PWL_LUT2_RAM_ram1,Input image width and height." tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LUT3_RAM_RAWFE_PWL_LUT3_RAM (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LUT3_RAM_RAWFE_PWL_LUT3_RAM)" base ad:0x3920800 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__LUT3__RAM__RAWFE_PWL_LUT3_RAM_ram1,Input image width and height." tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_MMR_S_VBUSP_RAWFE_CFG (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_MMR_S_VBUSP_RAWFE_CFG)" base ad:0x3920000 rgroup.long 0x0++0x19B line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_IMAGE_CFG,Input image width and height." hexmask.long.word 0x0 16.--28. 1. "HEIGHT,image height" newline hexmask.long.word 0x0 0.--12. 1. "WIDTH,image width" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_SHADOW_CFG,shadow configuration" bitfld.long 0x4 0. "LUT3_SHDW_EN,use LUT2 ram as LUT table for LUT3 processing" "0,1" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_MASK_SH,Long frame PWL mask and shift values" hexmask.long.byte 0x8 16.--19. 1. "SHIFT,number of right shift" newline hexmask.long.word 0x8 0.--15. 1. "MASK,mask bit pattern" line.long 0xC "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_EN,Long frame PWL enable" bitfld.long 0xC 0. "ENABLE,enable" "0,1" line.long 0x10 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_THRX12,Long frame PWL threshold X1 and X2 - Unsigned" hexmask.long.word 0x10 16.--31. 1. "THR_X2,threshold X2" newline hexmask.long.word 0x10 0.--15. 1. "THR_X1,threshold X1" line.long 0x14 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_THRX3,Long frame PWL threshold X3 - Unsigned" hexmask.long.word 0x14 0.--15. 1. "THR_X3,threshold X3" line.long 0x18 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_THRY1,Long frame PWL threshold Y1 - Unsigned" hexmask.long.tbyte 0x18 0.--23. 1. "THR_Y1,threshold Y1" line.long 0x1C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_THRY2,Long frame PWL threshold Y2 - Unsigned" hexmask.long.tbyte 0x1C 0.--23. 1. "THR_Y2,threshold Y2" line.long 0x20 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_THRY3,Long frame PWL threshold Y3 - Unsigned" hexmask.long.tbyte 0x20 0.--23. 1. "THR_Y3,threshold Y3" line.long 0x24 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_SLP12,Long frame PWL slope 1 and 2 - Unsigned" hexmask.long.word 0x24 16.--31. 1. "SLOPE_2,slope 2" newline hexmask.long.word 0x24 0.--15. 1. "SLOPE_1,slope 1" line.long 0x28 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_SLP34,Long frame PWL slope 3 and 4 - Unsigned" hexmask.long.word 0x28 16.--31. 1. "SLOPE_4,slope 4" newline hexmask.long.word 0x28 0.--15. 1. "SLOPE_3,slope 3" line.long 0x2C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_SLPSH_CLIP,Long frame PWL slope shift and clip" hexmask.long.tbyte 0x2C 8.--31. 1. "CLIP,clip value" newline hexmask.long.byte 0x2C 0.--7. 1. "SLOPE_SHIFT,shift value for slope must not exceed decimal 33." line.long 0x30 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_OFF1,Long frame Offset 1" hexmask.long.byte 0x30 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0x30 0.--23. 1. "OFST00,S24 Offset at pixel 00" line.long 0x34 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_OFF2,Long frame Offset 2" hexmask.long.byte 0x34 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0x34 0.--23. 1. "OFST01,S24 Offset at pixel 01" line.long 0x38 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_OFF3,Long frame Offset 3" hexmask.long.byte 0x38 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0x38 0.--23. 1. "OFST10,S24 Offset at pixel 10" line.long 0x3C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_OFF4,Long frame Offset 4" hexmask.long.byte 0x3C 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0x3C 0.--23. 1. "OFST11,S24 Offset at pixel 11" line.long 0x40 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_WB_gain12,Long Frame white balance gain 1 and 2" hexmask.long.word 0x40 16.--28. 1. "WB_GAIN01,U13Q9 WB gain at pixel 01" newline hexmask.long.word 0x40 0.--12. 1. "WB_GAIN00,U13Q9 WB gain at pixel 00" line.long 0x44 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_WB_gain34,Long Frame white balance gain 3 and 4" hexmask.long.word 0x44 16.--28. 1. "WB_GAIN11,U13Q9 WB gain at pixel 11" newline hexmask.long.word 0x44 0.--12. 1. "WB_GAIN10,U13Q9 WB gain at pixel 10" line.long 0x48 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_LUT,Long frame PWL LUT configuration" hexmask.long.byte 0x48 1.--5. 1. "LUT_BITS,LUT input bit depth up to 24" newline bitfld.long 0x48 0. "LUT_EN,enable LUT based compression" "0,1" line.long 0x4C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_LUTCLIP,Long frame PWL LUT output clip value" hexmask.long.word 0x4C 0.--15. 1. "LUTCLIP,LUT clip value" line.long 0x50 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_MASK_SH,Short frame PWL mask and shift values" hexmask.long.byte 0x50 16.--19. 1. "SHIFT,number of right shift" newline hexmask.long.word 0x50 0.--15. 1. "MASK,mask bit pattern" line.long 0x54 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_EN,Short frame PWL enable" bitfld.long 0x54 0. "ENABLE,enable" "0,1" line.long 0x58 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_THRX12,Short frame PWL threshold X1 and X2 - Unsigned" hexmask.long.word 0x58 16.--31. 1. "THR_X2,threshold X2" newline hexmask.long.word 0x58 0.--15. 1. "THR_X1,threshold X1" line.long 0x5C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_THRX3,Short frame PWL threshold X3 - Unsigned" hexmask.long.word 0x5C 0.--15. 1. "THR_X3,threshold X3" line.long 0x60 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_THRY1,Short frame PWL threshold Y1 - Unsigned" hexmask.long.tbyte 0x60 0.--23. 1. "THR_Y1,threshold Y1" line.long 0x64 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_THRY2,Short frame PWL threshold Y2 - Unsigned" hexmask.long.tbyte 0x64 0.--23. 1. "THR_Y2,threshold Y2" line.long 0x68 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_THRY3,Short frame PWL threshold Y3 - Unsigned" hexmask.long.tbyte 0x68 0.--23. 1. "THR_Y3,threshold Y3" line.long 0x6C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_SLP12,Short frame PWL slope 1 and 2 - Unsigned" hexmask.long.word 0x6C 16.--31. 1. "SLOPE_2,slope 2" newline hexmask.long.word 0x6C 0.--15. 1. "SLOPE_1,slope 1" line.long 0x70 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_SLP34,Short frame PWL slope 3 and 4 - Unsigned" hexmask.long.word 0x70 16.--31. 1. "SLOPE_4,slope 4" newline hexmask.long.word 0x70 0.--15. 1. "SLOPE_3,slope 3" line.long 0x74 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_SLPSH_CLIP,Short frame PWL slope shift and clip" hexmask.long.tbyte 0x74 8.--31. 1. "CLIP,clip value" newline hexmask.long.byte 0x74 0.--7. 1. "SLOPE_SHIFT,shift value for slope must not exceed decimal 33" line.long 0x78 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_LUT,Short frame PWL LUT configuration" hexmask.long.byte 0x78 1.--5. 1. "LUT_BITS,LUT input bit depth up to 24" newline bitfld.long 0x78 0. "LUT_EN,enable LUT based compression" "0,1" line.long 0x7C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_LUTCLIP,Short frame PWL LUT output clip value" hexmask.long.word 0x7C 0.--15. 1. "LUTCLIP,LUT clip value" line.long 0x80 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_OFF1,Short frame WB Offset 1" hexmask.long.byte 0x80 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0x80 0.--23. 1. "OFST00,S24 WB Offset at pixel 00" line.long 0x84 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_OFF2,Short frame Offset 2" hexmask.long.byte 0x84 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0x84 0.--23. 1. "OFST01,S24 Offset at pixel 01" line.long 0x88 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_OFF3,Short frame Offset 3" hexmask.long.byte 0x88 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0x88 0.--23. 1. "OFST10,S24 Offset at pixel 10" line.long 0x8C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_OFF4,Short frame Offset 4" hexmask.long.byte 0x8C 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0x8C 0.--23. 1. "OFST11,S24 Offset at pixel 11" line.long 0x90 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_WB_gain12,Short Frame white balance gain 1 and 2" hexmask.long.word 0x90 16.--28. 1. "WB_GAIN01,U13Q9 WB gain at pixel 01" newline hexmask.long.word 0x90 0.--12. 1. "WB_GAIN00,U13Q9 WB gain at pixel 00" line.long 0x94 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_WB_gain34,Short Frame white balance gain 3 and 4" hexmask.long.word 0x94 16.--28. 1. "WB_GAIN11,U13Q9 WB gain at pixel 11" newline hexmask.long.word 0x94 0.--12. 1. "WB_GAIN10,U13Q9 WB gain at pixel 10" line.long 0x98 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_MASK_SH,Very short frame PWL mask and shift values" hexmask.long.byte 0x98 16.--19. 1. "SHIFT,number of right shift" newline hexmask.long.word 0x98 0.--15. 1. "MASK,mask bit pattern" line.long 0x9C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_EN,Very short frame PWL enable" bitfld.long 0x9C 0. "ENABLE,enable" "0,1" line.long 0xA0 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_THRX12,Very short frame PWL threshold X1 and X2 - Unsigned" hexmask.long.word 0xA0 16.--31. 1. "THR_X2,threshold X2" newline hexmask.long.word 0xA0 0.--15. 1. "THR_X1,threshold X1" line.long 0xA4 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_THRX3,Very short frame PWL threshold X3 - Unsigned" hexmask.long.word 0xA4 0.--15. 1. "THR_X3,threshold X3" line.long 0xA8 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_THRY1,Very short frame PWL threshold Y1 - Unsigned" hexmask.long.tbyte 0xA8 0.--23. 1. "THR_Y1,threshold Y1" line.long 0xAC "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_THRY2,Very short frame PWL threshold Y2 - Unsigned" hexmask.long.tbyte 0xAC 0.--23. 1. "THR_Y2,threshold Y2" line.long 0xB0 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_THRY3,Very short frame PWL threshold Y3 - Unsigned" hexmask.long.tbyte 0xB0 0.--23. 1. "THR_Y3,threshold Y3" line.long 0xB4 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_SLP12,Very short frame PWL slope 1 and 2 - Unsigned" hexmask.long.word 0xB4 16.--31. 1. "SLOPE_2,slope 2" newline hexmask.long.word 0xB4 0.--15. 1. "SLOPE_1,slope 1" line.long 0xB8 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_SLP34,Very short frame PWL slope 3 and 4 - Unsigned" hexmask.long.word 0xB8 16.--31. 1. "SLOPE_4,slope 4" newline hexmask.long.word 0xB8 0.--15. 1. "SLOPE_3,slope 3" line.long 0xBC "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_SLPSH_CLIP,Very short frame PWL slope shift and clip" hexmask.long.tbyte 0xBC 8.--31. 1. "CLIP,clip value" newline hexmask.long.byte 0xBC 0.--7. 1. "SLOPE_SHIFT,shift value for slope must not exceed decimal 33" line.long 0xC0 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_LUT,Very short frame PWL LUT configuration" hexmask.long.byte 0xC0 1.--5. 1. "LUT_BITS,LUT input bit depth up to 24" newline bitfld.long 0xC0 0. "LUT_EN,enable LUT based compression" "0,1" line.long 0xC4 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_LUTCLIP,Very short frame PWL LUT output clip value" hexmask.long.word 0xC4 0.--15. 1. "LUTCLIP,LUT clip value" line.long 0xC8 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_OFF1,Very Short frame Offset 1" hexmask.long.byte 0xC8 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0xC8 0.--23. 1. "OFST00,S24 Offset at pixel 00" line.long 0xCC "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_OFF2,Very Short frame Offset 2" hexmask.long.byte 0xCC 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0xCC 0.--23. 1. "OFST01,S24 Offset at pixel 01" line.long 0xD0 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_OFF3,Very Short frame Offset 3" hexmask.long.byte 0xD0 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0xD0 0.--23. 1. "OFST10,S24 Offset at pixel 10" line.long 0xD4 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_OFF4,Very Short frame Offset 4" hexmask.long.byte 0xD4 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0xD4 0.--23. 1. "OFST11,S24 Offset at pixel 11" line.long 0xD8 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_WB_gain12,Very Short Frame white balance gain 1 and 2" hexmask.long.word 0xD8 16.--28. 1. "WB_GAIN01,U13Q9 WB gain at pixel 01" newline hexmask.long.word 0xD8 0.--12. 1. "WB_GAIN00,U13Q9 WB gain at pixel 00" line.long 0xDC "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_WB_gain34,Very Short Frame white balance gain 3 and 4" hexmask.long.word 0xDC 16.--28. 1. "WB_GAIN11,U13Q9 WB gain at pixel 11" newline hexmask.long.word 0xDC 0.--12. 1. "WB_GAIN10,U13Q9 WB gain at pixel 10" line.long 0xE0 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_CFG,First stage WDR merge configuration" bitfld.long 0xE0 14. "CFG_WGT_SEL,Select source for weight calculation (0:long 1: short)" "0: long,1: short)" newline hexmask.long.byte 0xE0 10.--13. 1. "CFG_SBIT,U4 short exposure image bit shift" newline hexmask.long.byte 0xE0 6.--9. 1. "CFG_LBIT,U4 long exposure image bit shift" newline hexmask.long.byte 0xE0 1.--5. 1. "CFG_DST,U5 down shift value after WDR merge" newline bitfld.long 0xE0 0. "CFG_EN,enable" "0,1" line.long 0xE4 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_GAIN,First stage WDR merge gain" hexmask.long.word 0xE4 16.--31. 1. "GSHORT,U16Q15 gain for long frame" newline hexmask.long.word 0xE4 0.--15. 1. "GLONG,U16Q15 gain for short frame" line.long 0xE8 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_LBLK12,First stage WDR merge black level 1 and 2 for long frame" hexmask.long.word 0xE8 16.--27. 1. "LBK01,U12 black level for long frame at pixel 01" newline hexmask.long.word 0xE8 0.--11. 1. "LBK00,U12 black level for long frame at pixel 00" line.long 0xEC "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_LBLK34,First stage WDR merge black level 3 and 4 for long frame" hexmask.long.word 0xEC 16.--27. 1. "LBK11,U12 black level for long frame at pixel 11" newline hexmask.long.word 0xEC 0.--11. 1. "LBK10,U12 black level for long frame at pixel 10" line.long 0xF0 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_SBLK12,First stage WDR merge black level 1 and 2 for short frame" hexmask.long.word 0xF0 16.--27. 1. "SBK01,U12 black level for short frame at pixel 01" newline hexmask.long.word 0xF0 0.--11. 1. "SBK00,U12 black level for short frame at pixel 00" line.long 0xF4 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_SBLK34,First stage WDR merge black level 3 and 4 for short frame" hexmask.long.word 0xF4 16.--27. 1. "SBK11,U12 black level for short frame at pixel 11" newline hexmask.long.word 0xF4 0.--11. 1. "SBK10,U12 black level for short frame at pixel 10" line.long 0xF8 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_LWB12,First stage WDR merge WB gain 1 and 2 for long frame" hexmask.long.word 0xF8 16.--28. 1. "WB01,U13Q9 WB gain for long frame at pixel 01" newline hexmask.long.word 0xF8 0.--12. 1. "WB00,U13Q9 WB gain for long frame at pixel 00" line.long 0xFC "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_LWB34,First stage WDR merge WB gain 3 and 4 for long frame" hexmask.long.word 0xFC 16.--28. 1. "WB11,U13Q9 WB gain for long frame at pixel 11" newline hexmask.long.word 0xFC 0.--12. 1. "WB10,U13Q9 WB gain for long frame at pixel 10" line.long 0x100 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_SWB12,First stage WDR merge WB gain 1 and 2 for short frame" hexmask.long.word 0x100 16.--28. 1. "WB01,U13Q9 WB gain for short frame at pixel 01" newline hexmask.long.word 0x100 0.--12. 1. "WB00,U13Q9 WB gain for short frame at pixel 00" line.long 0x104 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_SWB34,First stage WDR merge WB gain 3 and 4 for short frame" hexmask.long.word 0x104 16.--28. 1. "WB11,U13Q9 WB gain for short frame at pixel 11" newline hexmask.long.word 0x104 0.--12. 1. "WB10,U13Q9 WB gain for short frame at pixel 10" line.long 0x108 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_WDRTHR_BF,First stage WDR merge parameter WDRTHR and BF" hexmask.long.word 0x108 16.--31. 1. "BF,S16 bf parameter for merge" newline hexmask.long.word 0x108 0.--15. 1. "WDRTHR,U16 WDR threshold for merge" line.long 0x10C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_AF,First stage WDR merge parameter AF" hexmask.long.byte 0x10C 16.--21. 1. "AFE,U6 af_e parameter for merge" newline hexmask.long.word 0x10C 0.--15. 1. "AFM,S16 af_m parameter for merge" line.long 0x110 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_MA,First stage WDR merge parameter MA" hexmask.long.word 0x110 16.--31. 1. "MAS,U16 slope for merge MA filter" newline hexmask.long.word 0x110 0.--15. 1. "MAD,U16 lower threshold for merge MA filter" line.long 0x114 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_CLIP_SFT,First stage WDR merge clip value and shift before weight block" bitfld.long 0x114 20.--22. "WTSFT,U3 shift before weight block" "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x114 0.--19. 1. "CLIP,U20 output clip value. It is a software restriction to always ensure that the clipped value is a 16-bit number for first wdr stage." line.long 0x118 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_CFG,Second stage WDR merge configuration" bitfld.long 0x118 14. "CFG_WGT_SEL,Select source for weight calculation (0:long 1: short)" "0: long,1: short)" newline hexmask.long.byte 0x118 10.--13. 1. "CFG_SBIT,U4 short exposure image bit shift" newline hexmask.long.byte 0x118 6.--9. 1. "CFG_LBIT,U4 long exposure image bit shift" newline hexmask.long.byte 0x118 1.--5. 1. "CFG_DST,U5 down shift value after WDR merge" newline bitfld.long 0x118 0. "CFG_EN,enable" "0,1" line.long 0x11C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_GAIN,Second stage WDR merge gain" hexmask.long.word 0x11C 16.--31. 1. "GSHORT,U16Q15 gain for long frame" newline hexmask.long.word 0x11C 0.--15. 1. "GLONG,U16Q15 gain for short frame" line.long 0x120 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_LBLK12,Second stage WDR merge black level 1 and 2 for long frame" hexmask.long.word 0x120 16.--27. 1. "LBK01,U12 black level for long frame at pixel 01" newline hexmask.long.word 0x120 0.--11. 1. "LBK00,U12 black level for long frame at pixel 00" line.long 0x124 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_LBLK34,Second stage WDR merge black level 3 and 4 for long frame" hexmask.long.word 0x124 16.--27. 1. "LBK11,U12 black level for long frame at pixel 11" newline hexmask.long.word 0x124 0.--11. 1. "LBK10,U12 black level for long frame at pixel 10" line.long 0x128 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_SBLK12,Second stage WDR merge black level 1 and 2 for short frame" hexmask.long.word 0x128 16.--27. 1. "SBK01,U12 black level for short frame at pixel 01" newline hexmask.long.word 0x128 0.--11. 1. "SBK00,U12 black level for short frame at pixel 00" line.long 0x12C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_SBLK34,Second stage WDR merge black level 3 and 4 for short frame" hexmask.long.word 0x12C 16.--27. 1. "SBK11,U12 black level for short frame at pixel 11" newline hexmask.long.word 0x12C 0.--11. 1. "SBK10,U12 black level for short frame at pixel 10" line.long 0x130 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_LWB12,Second stage WDR merge WB gain 1 and 2 for long frame" hexmask.long.word 0x130 16.--28. 1. "WB01,U13Q9 WB gain for long frame at pixel 01" newline hexmask.long.word 0x130 0.--12. 1. "WB00,U13Q9 WB gain for long frame at pixel 00" line.long 0x134 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_LWB34,Second stage WDR merge WB gain 3 and 4 for long frame" hexmask.long.word 0x134 16.--28. 1. "WB11,U13Q9 WB gain for long frame at pixel 11" newline hexmask.long.word 0x134 0.--12. 1. "WB10,U13Q9 WB gain for long frame at pixel 10" line.long 0x138 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_SWB12,Second stage WDR merge WB gain 1 and 2 for short frame" hexmask.long.word 0x138 16.--28. 1. "WB01,U13Q9 WB gain for short frame at pixel 01" newline hexmask.long.word 0x138 0.--12. 1. "WB00,U13Q9 WB gain for short frame at pixel 00" line.long 0x13C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_SWB34,Second stage WDR merge WB gain 3 and 4 for short frame" hexmask.long.word 0x13C 16.--28. 1. "WB11,U13Q9 WB gain for short frame at pixel 11" newline hexmask.long.word 0x13C 0.--12. 1. "WB10,U13Q9 WB gain for short frame at pixel 10" line.long 0x140 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_WDRTHR_BF,Second stage WDR merge parameter WDRTHR and BF" hexmask.long.word 0x140 16.--31. 1. "BF,S16 bf parameter for merge" newline hexmask.long.word 0x140 0.--15. 1. "WDRTHR,U16 WDR threshold for merge" line.long 0x144 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_AF,Second stage WDR merge parameter AF" hexmask.long.byte 0x144 16.--21. 1. "AFE,U6 af_e parameter for merge" newline hexmask.long.word 0x144 0.--15. 1. "AFM,S16 af_m parameter for merge" line.long 0x148 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_MA,Second stage WDR merge parameter MA" hexmask.long.word 0x148 16.--31. 1. "MAS,U16 slope for merge MA filter" newline hexmask.long.word 0x148 0.--15. 1. "MAD,U16 lower threshold for merge MA filter" line.long 0x14C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_CLIP_SFT,Second stage WDR merge clip value and shift before weight block" bitfld.long 0x14C 20.--22. "WTSFT,U3 shift before weight block" "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x14C 0.--19. 1. "CLIP,U20 output clip value" line.long 0x150 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_MRGLUT_CFG,Merge LUT configuration" hexmask.long.word 0x150 16.--31. 1. "CLIP,U16 LUT output clip" newline hexmask.long.byte 0x150 1.--5. 1. "BITS,U5 LUT input bit depth up to 24" newline bitfld.long 0x150 0. "EN,LUT enable" "0,1" line.long 0x154 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_LUTDPC_CFG,LUTDPC configuration" hexmask.long.byte 0x154 2.--9. 1. "SIZE,U8 number of LUT entires - 1" newline bitfld.long 0x154 1. "SEL,replace with black (0) or whithe (1)" "0,1" newline bitfld.long 0x154 0. "EN,LUTDPC enable" "0,1" line.long 0x158 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_EN,OTFDPC enable" bitfld.long 0x158 0. "EN,OTF DPC enable" "0,1" line.long 0x15C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_THRSLP1,OTFDPC threshold and slope 1" hexmask.long.word 0x15C 16.--27. 1. "SLP1,S12Q8 slope at 0" newline hexmask.long.word 0x15C 0.--15. 1. "THR1,U16 threshold at 0" line.long 0x160 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_THRSLP2,OTFDPC threshold and slope 2" hexmask.long.word 0x160 16.--27. 1. "SLP1,S12Q8 slope at 512" newline hexmask.long.word 0x160 0.--15. 1. "THR1,U16 threshold at 512" line.long 0x164 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_THRSLP3,OTFDPC threshold and slope 3" hexmask.long.word 0x164 16.--27. 1. "SLP1,S12Q8 slope at 1024" newline hexmask.long.word 0x164 0.--15. 1. "THR1,U16 threshold at 1024" line.long 0x168 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_THRSLP4,OTFDPC threshold and slope 4" hexmask.long.word 0x168 16.--27. 1. "SLP1,S12Q8 slope at 2048" newline hexmask.long.word 0x168 0.--15. 1. "THR1,U16 threshold at 2048" line.long 0x16C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_THRSLP5,OTFDPC threshold and slope 5" hexmask.long.word 0x16C 16.--27. 1. "SLP1,S12Q8 slope at 4096" newline hexmask.long.word 0x16C 0.--15. 1. "THR1,U16 threshold at 4096" line.long 0x170 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_THRSLP6,OTFDPC threshold and slope 6" hexmask.long.word 0x170 16.--27. 1. "SLP1,S12Q8 slope at 8192" newline hexmask.long.word 0x170 0.--15. 1. "THR1,U16 threshold at 8192" line.long 0x174 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_THRSLP7,OTFDPC threshold and slope 7" hexmask.long.word 0x174 16.--27. 1. "SLP1,S12Q8 slope at 16384" newline hexmask.long.word 0x174 0.--15. 1. "THR1,U16 threshold at 16384" line.long 0x178 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_THRSLP8,OTFDPC threshold and slope 8" hexmask.long.word 0x178 16.--27. 1. "SLP1,S12Q8 slope at 32768" newline hexmask.long.word 0x178 0.--15. 1. "THR1,U16 threshold at 32768" line.long 0x17C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_LSC_CFG,LSC configuration" bitfld.long 0x17C 7.--9. "GAIN_FORMAT,LSC LUT gain format 0:Q8 1:Q8+1 2:Q7 3:Q7+1 4:Q6 5:Q6+1 6:Q5 7:Q5+1" "0: Q8,1: Q8+1,2: Q7,3: Q7+1,4: Q6,5: Q6+1,6: Q5,7: Q5+1" newline bitfld.long 0x17C 4.--6. "MODE_N,vertical LSC LUT downsampling 3:8x 4:16x 5:32x 6:64x 7:128x" "0,1,2,3,4,5,6,7" newline bitfld.long 0x17C 1.--3. "MODE_M,horizontal LSC LUT downsampling 3:8x 4:16x 5:32x 6:64x 7:128x" "0,1,2,3,4,5,6,7" newline bitfld.long 0x17C 0. "EN,LSC enable" "0,1" line.long 0x180 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WB2_offset12,WB2 white balance offset 1 and 2" hexmask.long.word 0x180 16.--31. 1. "WB_OFST01,S16 WB offset at pixel 01" newline hexmask.long.word 0x180 0.--15. 1. "WB_OFST00,S16 WB offset at pixel 00" line.long 0x184 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WB2_offset34,WB2 white balance offset 3 and 4" hexmask.long.word 0x184 16.--31. 1. "WB_OFST11,S16 WB offset at pixel 11" newline hexmask.long.word 0x184 0.--15. 1. "WB_OFST10,S16 WB offset at pixel 10" line.long 0x188 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WB2_gain12,WB2 white balance gain 1 and 2" hexmask.long.word 0x188 16.--28. 1. "WB_GAIN01,U13Q9 WB gain at pixel 01" newline hexmask.long.word 0x188 0.--12. 1. "WB_GAIN00,U13Q9 WB gain at pixel 00" line.long 0x18C "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WB2_gain34,WB2 white balance gain 3 and 4" hexmask.long.word 0x18C 16.--28. 1. "WB_GAIN11,U13Q9 WB gain at pixel 11" newline hexmask.long.word 0x18C 0.--12. 1. "WB_GAIN10,U13Q9 WB gain at pixel 10" line.long 0x190 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_H3AMUX_CFG,H3A MUX configuration" hexmask.long.byte 0x190 2.--5. 1. "SHIFT,U8 number of right shift from 0 to 14" newline bitfld.long 0x190 0.--1. "SEL,H3A input selection 0: long frame 1: short frame 2: very short frame 3: LSC output" "0: long frame,1: short frame,2: very short frame,3: LSC output" line.long 0x194 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_H3ALUT_CFG,H3A LUT configuration" hexmask.long.word 0x194 16.--25. 1. "CLIP,U10 LUT output clip value" newline hexmask.long.byte 0x194 1.--5. 1. "BITS,U5 LUT input bit depth up to 24" newline bitfld.long 0x194 0. "EN,LUT enable" "0,1" line.long 0x198 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_RAWFE_INT_STAT,status/clear register for rawfe interrupts" bitfld.long 0x198 9. "LSC_CFG_ERR,status/clear for lsc config error. This is set when a write or read occurs in the middle of frame processing. This results in data corruption for the frame. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x198 8. "DPC_LINE_CFG_ERR,status/clear for dpc line config error. This is set when a write or read occurs in the middle of frame processing. This results in data corruption for the frame. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x198 7. "DPC_LUT_CFG_ERR,status/clear for dpc lut configuration error. This is set when a write or read occurs in the middle of frame processing. This results in data corruption for the frame. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x198 6. "H3A_ACCM_CFG_ERR,status/clear for h3a accum configuration error. This is set when a write or read occurs in the middle of frame processing. This results in data corruption for the frame. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x198 5. "H3A_LINE_CFG_ERR,status/clear for h3a line configuration error. This is set when a write or read occurs in the middle of frame processing. This results in data corruption for the frame. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x198 4. "H3A_LUT_CFG_ERR,status/clear for h3a lut configuration error. This is set when a write or read occurs in the middle of frame processing. This results in data corruption for the frame. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x198 3. "WDR_LUT_CFG_ERR,status/clear for wdr lut configuration error. This is set when a write or read occurs in the middle of frame processing. This results in data corruption for the frame. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x198 2. "LUT3_CFG_ERR,status/clear for lut3 configuration error. This is set when a write or read occurs in the middle of frame processing. This results in data corruption for the frame. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x198 1. "LUT2_CFG_ERR,status/clear for lut2 configuration error. This is set when a write or read occurs in the middle of frame processing. This results in data corruption for the frame. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x198 0. "LUT1_CFG_ERR,status/clear for lut1 configuration error. This is set when a write or read occurs in the middle of frame processing. This results in data corruption for the frame. write 1 to clear event status write of 0 has no affect" "0,1" rgroup.long 0x200++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_DBG_CTL,debug event and control register" bitfld.long 0x0 12.--13. "DPC_LINE_SEL,select for which dpc line ram to read on debug interface" "0,1,2,3" newline bitfld.long 0x0 11. "PIPE_ADV_EN_EVENT,enable for pixal pipe line advanced" "0,1" newline bitfld.long 0x0 10. "DPC_OTF_CORR_EN_EVENT,enable for dpc otf corrected a pixel" "0,1" newline bitfld.long 0x0 9. "LSE_INTF_STALL_EN_EVENT,enable for lse slave port stalled by rawfe" "0,1" newline bitfld.long 0x0 8. "LSE_MST_STALL_EN_EVENT,enable for lse maaster port stalled on H3A out I/F" "0,1" newline bitfld.long 0x0 7. "LSE_SLV_STALL_EN_EVENT,enable for lse not sending data in frame on pixel I/F" "0,1" newline bitfld.long 0x0 6. "HE_EN_EVENT,enable for horizantal end" "0,1" newline bitfld.long 0x0 5. "HS_EN_EVENT,enable for horizantal start" "0,1" newline bitfld.long 0x0 4. "VE_EN_EVENT,enable for verticle end" "0,1" newline bitfld.long 0x0 3. "VS_EN_EVENT,enable for verticle start" "0,1" newline bitfld.long 0x0 2. "X_Y_EN_EVENT,enable for x y position match event; Only generates event no halt" "0,1" newline bitfld.long 0x0 1. "X_Y_EN_HALT,enable for x y position match halt; Halts Pipe clear this bit to resume. Only way to resume is to clear this bit back to 0. You would need to clear the status bit after clearing this bit." "0,1" newline bitfld.long 0x0 0. "DBG_EN,Enable debug features set to '0' to disable all events" "0,1" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_DBG_HWBP,x.y event for event matching" hexmask.long.word 0x4 16.--28. 1. "Y_POS,pixel y position" newline hexmask.long.word 0x4 0.--12. 1. "X_POS,pixel x position" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_DBG_STAT1,status/clear register for debug events" bitfld.long 0x8 11. "PIPE_ADV_EVENT,status/clear for pixal pipe line advanced" "0,1" newline bitfld.long 0x8 10. "DPC_OTF_CORR_EVENT,status/clear for dpc otf corrected a pixel. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x8 9. "LSE_INTF_STALL_EVENT,status/clear for lse slave port stalled by rawfe. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x8 8. "LSE_MST_STALL_EVENT,status/clear for lse maaster port stalled. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x8 7. "LSE_SLV_STALL_EVENT,status/clear for lse not sending data in frame. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x8 6. "HE_EVENT,status/clear for horizantal end. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x8 5. "HS_EVENT,status/clear for horizantal start. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x8 4. "VE_EVENT,status/clear for verticle end. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x8 3. "VS_EVENT,status/clear for verticle start. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x8 2. "X_Y_EVENT,status/clear for x y position match event. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x8 1. "X_Y_HALT,status/clear for x y position match halt. write 1 to clear event status write of 0 has no affect" "0,1" rgroup.long 0x20C++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_DBG_STAT2,current x.y position in frame" hexmask.long.word 0x0 16.--28. 1. "Y_POS,current y position" newline hexmask.long.word 0x0 0.--12. 1. "X_POS,current x position" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_DBG_STAT3,internal state status" hexmask.long 0x4 2.--31. 1. "DPC_MIRROR_STAT,dpc mirror status" newline bitfld.long 0x4 0.--1. "DPC_LINE_RAM_CTL,ram control for understanding the phase of DPC line rams circular buffer for debug reads" "0,1,2,3" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_DBG_STAT4,internal state status" hexmask.long 0x8 0.--31. 1. "LSC_DBG_STAT,lsc state machine" tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_WDR_LUT_RAM_RAWFE_WDR_LUT_RAM (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_WDR_LUT_RAM_RAWFE_WDR_LUT_RAM)" base ad:0x3922000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__WDR_LUT__RAM__RAWFE_WDR_LUT_RAM_ram1,Input image width and height." tree.end tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VPAC_VISS_LSE_CFG_VP (VPAC0_PAR_VPAC_VISS0_S_VBUSP_VPAC_VISS_LSE_CFG_VP)" base ad:0x3900400 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_status_param,The STATUS_PARAM register returns the LSE compile configuration parameters." bitfld.long 0x0 30.--31. "BYPASS_CH,Number of available input channel selection for loopback mode" "0,1,2,3" newline bitfld.long 0x0 29. "OUT_SKIP_EN,Output Auto-Skip Enable" "0,1" newline bitfld.long 0x0 28. "CORE_OUT_2D,1D or 2D output addressing mode(2D if 1)" "0,1" newline hexmask.long.byte 0x0 23.--27. 1. "CORE_OUT_DW,Core Output Channel Data Width" newline bitfld.long 0x0 22. "LINE_SKIP_EN,Source Line Inc by 2 Supported (if 1)" "0,1" newline bitfld.long 0x0 21. "BIT_AOFFSET,Source nibble offset address Supported (if 1)" "0,1" newline bitfld.long 0x0 20. "HV_INSERT,H/VBLANK Insertion Supported (if 1)" "0,1" newline bitfld.long 0x0 17.--19. "PIX_MX_HT,Core_Input Pixel Matrix Height" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 12.--16. 1. "CORE_DW,Core Input Data Bus Width" newline bitfld.long 0x0 10.--11. "SL2_OUT_H3A_CH,Number of SL2 H3A Output Channels" "0,1,2,3" newline hexmask.long.byte 0x0 6.--9. 1. "SL2_OUT_CH,Number of SL2 Output Channels" newline bitfld.long 0x0 3.--5. "SL2_IN_CH_THR,Number of Input Channels per thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "VPORT_THR,Number of VPORT input enabled" "0,1" newline bitfld.long 0x0 0.--1. "NTHR,Number of threads supported" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_status_error,The STATUS_ERROR register returns the LSE error status." hexmask.long.word 0x0 16.--26. 1. "VPORT_IN_ERR,VPORT_CAL Input Error Status Protocol Errors [26] VS without HS [25] VE without HE [24] VS-VS (missing VE) Error [23] HS-HS (missing HE) Error [22] HE-HE (missing HS) Error [21] VE-VE (missing VS) Error Frame Size Errors [20].." newline hexmask.long.byte 0x0 8.--14. 1. "VM_WR_ERR,VBUSM I/F Last Write Error Status [14:11] Write Channel Number [10:8] VBUSM write error status" newline hexmask.long.byte 0x0 0.--4. 1. "VM_RD_ERR,VBUSM I/F Last Read Error Status [4:3] Read Channel Number [2:0] VBUSM read error status" rgroup.long 0x8++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_status_idle_mode,The STATUS_IDLE_MODE register returns IDLE status of LSE VBUSM port and in/output channels - 0: IDLE 1: ACTIVE" bitfld.long 0x0 24. "LSE_OUT_H3A_CHAN,Output H3A Channel Status" "0,1" newline hexmask.long.byte 0x0 12.--16. 1. "LSE_OUT_CHAN,Output Channel[4:0] Status" newline bitfld.long 0x0 11. "VPORT_IN_CHAN,CAL I/F Vport Input Cahnnel Status" "0,1" newline bitfld.long 0x0 4.--6. "LSE_IN_CHAN,Input Channel[2:0] Status" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1. "VM_WR_PORT,SL2 vbusm I/F Write Port Status" "0,1" newline bitfld.long 0x0 0. "VM_RD_PORT,SL2 vbusm I/F Read Port Status" "0,1" rgroup.long 0xC++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_cfg_lse,The CFG_LSE register configures the LSE general hardware modes." bitfld.long 0x0 8. "PSA_EN,Test mode Output Channel Signature Generation Enable 0: Disable (default) 1: Enable When enabled LSE generates a unique CRC signature for each output channel's frame data at frame completion." "0: Disable,1: Enable When enabled" newline bitfld.long 0x0 5. "IN_CH_SYNC_MODE,Input Channel Transfer Sync Mode (applicable only for VISS) 0: Line Mode 1: Frame Mode (default) When set to 0 (Line Mode) LSE waits for a HTS_TSTART on every line reads from SL2. When set to 1 (Frame Mode) LSE waits for the.." "0: Line Mode 1: Frame Mode,?" newline bitfld.long 0x0 4. "VM_ARB_FIXED_MODE,VBUSM Arbitration Fixed Mode select 0: Round-Robin Arbitration (default) 1: Fixed-mode Arbitration" "0: Round-Robin Arbitration,1: Fixed-mode Arbitration" newline bitfld.long 0x0 2.--3. "LOOPBACK_IN_CH_SEL,Loopback Input Channel Select (applicable only for VISS) 0: Ch0/CAL_Vport_In 1: Ch1 2: Ch2" "0: Ch0/CAL_Vport_In,1: Ch1,2: Ch2,?" newline bitfld.long 0x0 1. "LOOPBACK_CORE_EN,Functional path (data to HWA core) enable during loopback mode 0: Disable 1: Enable When enabled the loopback-enabled input channel is used also for CORE data input. Otherwise it is strictly used for the loopback path." "0: Disable,1: Enable When enabled" newline bitfld.long 0x0 0. "LOOPBACK_EN,LSE loopback mode enable 0: Disable 1: Enable When enabled selected input channel data is looped back out to the last (#4) output channel." "0: Disable,1: Enable When enabled" rgroup.long 0x13C++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_dst_common_cfg,The DST_COMMON_CFG register captures common configuration for the output channels" hexmask.long.byte 0x0 0.--5. 1. "ROUNDING_OFFSET,output channel rounding offset value. Default value to be considered 6'h08" rgroup.long 0x140++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_psa_signature,The PSA_SIGNATURE register returns the captured PSA signature value of the last frame data of output channel [a]." hexmask.long 0x0 0.--31. 1. "VALUE,32-bit CRC signature value" rgroup.long 0x1E0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_dbg,The DBG register returns the current status of internal FSM - TI internal use only." hexmask.long 0x0 0.--31. 1. "STATUS,Debug status" rgroup.long 0x10++0x13 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_cfg,The SRC_CFG register configures the input channels for the processing thread" hexmask.long.word 0x0 22.--31. 1. "VP_HBLNK_CNT,Number of HBlank Pixels to insert between active lines for internal vport interface to core. (Max=1023) Must be set to 0 if hblank insertion is not needed by HWA_CORE Else must be at least 2 (2 or more hblank cycles)" newline bitfld.long 0x0 4. "PIX_FMT_ALIGN,Input Pixel Container Alignment 0: LSB-aligned 1: MSB-aligned" "0: LSB-aligned,1: MSB-aligned" newline bitfld.long 0x0 2.--3. "PIX_FMT_CNTRSZ,Input Pixel Container Size Sel 0: 8-bit 1: 12-bit 2: 16-bit 3: reserved Input pixel container size must be same or larger than input pixel width." "?,?,?,3: reserved Input pixel container size must be same.." newline bitfld.long 0x0 0.--1. "PIX_FMT_PW,Input Pixel Width Sel 0: 8-bit 1: 12-bit 2: 14-bit 3: 16-bit The width defines the bit-depth of the pixel data to be extracted from the pixel container." "0,1,2,3" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_vpin_cfg,The SRC_VPIN_CFG register configures the VPORT input channel for the processing thread" bitfld.long 0x4 4. "VP_PROTOCOL_CHK,Vport Input Data Protocol Check Enable 0: Disable 1: Enable" "0: Disable,1: Enable" newline bitfld.long 0x4 2.--3. "VPORT_PW,Vport Pixel Data Width Sel 0: 8-bit 1: 12-bit 2: 14-bit 3: 16-bit Vport Pixels are always LSB aligned in 16-bit halfword" "0,1,2,3" newline bitfld.long 0x4 1. "VPORT_TWO_PIXEL,Number of pixels per vport cycles 0: 1 pixels 1: 2 pixels" "0,1" newline bitfld.long 0x4 0. "VPORT_EN,vport_en 0: Disable 1: Enable When Enabled external VPORT input data is selected instead of SRC channel 0 of this thread" "0: Disable,1: Enable When Enabled" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_frame_size,The SRC_FRAME_SIZE register configures the frame size of all input buffers for the processing thread ." hexmask.long.word 0x8 16.--28. 1. "HEIGHT,SL2 - Source Buffer Height (number of lines)" newline hexmask.long.word 0x8 0.--12. 1. "WIDTH,SL2 - Source Buffer Width (number of pixels)" line.long 0xC "PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_buf_attr,The SRC_BUF_ATTR register configures the common attributes of all SL2 source buffers for the processing thread ." hexmask.long.word 0xC 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)" newline hexmask.long.word 0xC 6.--15. 1. "BUF_STRIDE,Buffer Stride Size [15:6] (64 byte multiple) stride size" newline hexmask.long.byte 0xC 0.--5. 1. "BUF_STRIDE_6_LSB,Buffer Stride Size [5:0] - 6 LSB bits of buffer stride size should always be 0. Writes have no effect. Always read as 0" line.long 0x10 "PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_buf_ba,The SRC_BUF_BA[b] register configures the base address of the SL2 source buffer [b] for the processing thread ." bitfld.long 0x10 31. "ENABLE,Input Buffer Enable 0: Disable 1: Enable When the processing thread is enabled at least one of the input buffer must be enabled" "0: Disable,1: Enable When the processing thread is enabled" newline hexmask.long.tbyte 0x10 6.--23. 1. "ADDR,Base Address[23:6] - (64 Byte aligned) byte address" newline hexmask.long.byte 0x10 0.--5. 1. "ADDR_6_LSB,Base Address[5:0] - 6 LSB bits of address should always be 0. Writes have no effect. Always read as 0" rgroup.long 0x50++0x7 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_buf_cfg,The DST_BUF_CFG register configures the output buffer channel ." rbitfld.long 0x0 31. "CH_DISABLED,Channel Disable Status (read-only) 0: (Default) Chanel is enabled for Y UV or YUV422 data transfer to SL2 memory. All configurations associated with this DST_BUF[a] are valid. 1: Channel is disabled for SL2 data transfer (because the.." "?,1: Channel is disabled for SL2 data transfer" newline bitfld.long 0x0 29. "YUV422_INTLV_ORDER,YUV422 Interleaving Order Selection 0: UYVY 1: YUYV Only Applicable if this output channel is YUV422 output capable LUMA channel. Otherwise setting has no effect." "0: UYVY 1: YUYV Only Applicable if this output..,?" newline bitfld.long 0x0 28. "YUV422_OUT_EN,YUV422 Interleaved Output Merge Enable 0: Disable 1: Enable When enabled this channel interleaves data from the associated chroma data output channel to output YUV422 interleaved data to the SL2 memory. Only Applicable if this output.." "0: Disable,1: Enable When enabled" newline bitfld.long 0x0 10. "ENABLE_SIGNED_ACCLERATOR_DATA,Specify the acclerator data to be signed or unsigned 0: Unsigned data (By default) 1: Signed Data" "0: Unsigned data,1: Signed Data" newline bitfld.long 0x0 9. "ENABLE_OUTPUT_PIXEL_ROUNDING,enable acclerator pixel output rounding 0: Disable rounding logic 1: Enable rounding logic" "0: Disable rounding logic 1: Enable rounding logic,?" newline bitfld.long 0x0 4. "PIX_FMT_ALIGN,Output Pixel Container Alignment 0: LSB-aligned 1: MSB-aligned" "0: LSB-aligned,1: MSB-aligned" newline bitfld.long 0x0 2.--3. "PIX_FMT_CNTRSZ,Output Pixel Container Size Sel 0: 8-bit 1: 12-bit 2: 16-bit 3: reserved Output pixel container size must be same or larger than output pixel width. If yuv422_out_en is set pix_fmt_cntrsz must be 0." "?,?,?,3: reserved Output pixel container size must be.." newline bitfld.long 0x0 0.--1. "PIX_FMT_PW,Output Pixel Width Sel 0: 8-bit 1: 12-bit 2: reserved 3: 16-bit The width defines the bit-depth of the pixel data to be stored in the pixel container." "?,?,2: reserved,?" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_buf_attr0,The DST_BUF_ATTR0 register configures the attributes of the output SL2 buffer ." hexmask.long.byte 0x4 25.--31. 1. "LOUT_SKIP_INIT,Line Out Initial Skip Count - The number of initial HTS tstart/tdone cycles with no output from the core on this output channel. The LSE will auto-generate the channel done status during these cycles." newline hexmask.long.word 0x4 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)" newline hexmask.long.word 0x4 6.--15. 1. "BUF_STRIDE,Buffer Stride Size [15:6] (64 byte multiple) stride size" newline hexmask.long.byte 0x4 0.--5. 1. "BUF_STRIDE_6_LSB,Buffer Stride Size [5:0] - 6 LSB bits of buffer stride size should always be 0. Writes have no effect. Always read as 0" rgroup.long 0x5C++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_buf_ba,The DST_BUF_BA register configures the base address of the output SL2 circular buffer ." bitfld.long 0x0 31. "ENABLE,Output Channel Enable 0: Disable 1: Enable" "0: Disable,1: Enable" newline hexmask.long.tbyte 0x0 6.--23. 1. "ADDR,Base Address[23:6] - (64 Byte aligned) byte address" newline hexmask.long.byte 0x0 0.--5. 1. "ADDR_6_LSB,Base Address[5:0] - 6 LSB bits of address should always be 0. Writes have no effect. Always read as 0" rgroup.long 0xF0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_buf_attr,The H3A_BUF_ATTR register configures the attributes of the H3A output SL2 buffer." hexmask.long.word 0x0 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of H3A Line buffers)" newline hexmask.long.word 0x0 6.--15. 1. "H3A_LN_SIZE,H3A Output Done Line Size [15:0] Size of H3A output line size in bytes for HTS Done generation (64 byte multiple) This is equivalent to Buf_Stride." newline hexmask.long.byte 0x0 0.--5. 1. "H3A_LN_SIZE_6_LSB,H3A Output Done Line Size [5:0] - 6 LSB bits should always be 0. Writes have no effect. Always read as 0" rgroup.long 0xF8++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_buf_ba,The H3A_BUF_BA register configures the base address of the H3A output SL2 circular buffer." bitfld.long 0x0 31. "ENABLE,Output H3A Buffer Enable 0: Disable 1: Enable" "0: Disable,1: Enable" newline hexmask.long.tbyte 0x0 6.--23. 1. "ADDR,Base Address[23:6] - (64 Byte aligned) byte address" newline hexmask.long.byte 0x0 0.--5. 1. "ADDR_6_LSB,Base Address[5:0] - 6 LSB bits of address should always be 0. Writes have no effect. Always read as 0" tree.end tree.end tree.end tree "VPAC0_VISS_ECC_AGGR (VPAC0_VISS_ECC_AGGR)" base ad:0x2A61000 rgroup.long 0x0++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xF line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "FCC_LUT1_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 30. "FCC_LUT1_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 29. "FCC_LUT0_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_lut0_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 28. "FCC_LUT0_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_lut0_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 27. "FCC_CONT_LUT3_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "FCC_CONT_LUT3_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut3_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 25. "FCC_CONT_LUT2_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 24. "FCC_CONT_LUT2_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 23. "FCC_CONT_LUT1_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 22. "FCC_CONT_LUT1_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "FCC_HIST_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_hist_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "FCC_HIST_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_hist_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "STAT_MEM7_RAMECC_PEND,Interrupt Pending Status for stat_mem7_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "STAT_MEM6_RAMECC_PEND,Interrupt Pending Status for stat_mem6_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "STAT_MEM5_RAMECC_PEND,Interrupt Pending Status for stat_mem5_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "STAT_MEM4_RAMECC_PEND,Interrupt Pending Status for stat_mem4_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "STAT_MEM3_RAMECC_PEND,Interrupt Pending Status for stat_mem3_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "STAT_MEM2_RAMECC_PEND,Interrupt Pending Status for stat_mem2_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "STAT_MEM1_RAMECC_PEND,Interrupt Pending Status for stat_mem1_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "STAT_MEM0_RAMECC_PEND,Interrupt Pending Status for stat_mem0_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "H3A_LUT_RAM1_RAMECC_PEND,Interrupt Pending Status for h3a_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "H3A_LUT_RAM0_RAMECC_PEND,Interrupt Pending Status for h3a_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 9. "LSC_RAMECC_PEND,Interrupt Pending Status for lsc_ramecc_pend" "0,1" newline bitfld.long 0x4 8. "DPC_LUT_RAMECC_PEND,Interrupt Pending Status for dpc_lut_ramecc_pend" "0,1" newline bitfld.long 0x4 7. "WDR_LUT_RAM1_RAMECC_PEND,Interrupt Pending Status for wdr_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "WDR_LUT_RAM0_RAMECC_PEND,Interrupt Pending Status for wdr_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "LUT1_RAM1_RAMECC_PEND,Interrupt Pending Status for lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "LUT1_RAM0_RAMECC_PEND,Interrupt Pending Status for lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "LUT2_RAM1_RAMECC_PEND,Interrupt Pending Status for lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "LUT2_RAM0_RAMECC_PEND,Interrupt Pending Status for lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "LUT3_RAM1_RAMECC_PEND,Interrupt Pending Status for lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "LUT3_RAM0_RAMECC_PEND,Interrupt Pending Status for lut3_ram0_ramecc_pend" "0,1" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 31. "FCP2_FCC_CONT_LUT2_RAM1_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_cont_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 30. "FCP2_FCC_CONT_LUT2_RAM0_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_cont_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x8 29. "FCP2_FCC_CONT_LUT1_RAM1_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_cont_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 28. "FCP2_FCC_CONT_LUT1_RAM0_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_cont_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x8 27. "FCP2_FCC_HIST_RAM1_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_hist_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 26. "FCP2_FCC_HIST_RAM0_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_hist_ram0_ramecc_pend" "0,1" newline bitfld.long 0x8 25. "DLUT3_1_RAMECC_PEND,Interrupt Pending Status for dlut3_1_ramecc_pend" "0,1" newline bitfld.long 0x8 24. "DLUT3_0_RAMECC_PEND,Interrupt Pending Status for dlut3_0_ramecc_pend" "0,1" newline bitfld.long 0x8 23. "DLUT2_1_RAMECC_PEND,Interrupt Pending Status for dlut2_1_ramecc_pend" "0,1" newline bitfld.long 0x8 22. "DLUT2_0_RAMECC_PEND,Interrupt Pending Status for dlut2_0_ramecc_pend" "0,1" newline bitfld.long 0x8 21. "DLUT1_1_RAMECC_PEND,Interrupt Pending Status for dlut1_1_ramecc_pend" "0,1" newline bitfld.long 0x8 20. "DLUT1_0_RAMECC_PEND,Interrupt Pending Status for dlut1_0_ramecc_pend" "0,1" newline bitfld.long 0x8 19. "DLUT0_1_RAMECC_PEND,Interrupt Pending Status for dlut0_1_ramecc_pend" "0,1" newline bitfld.long 0x8 18. "DLUT0_0_RAMECC_PEND,Interrupt Pending Status for dlut0_0_ramecc_pend" "0,1" newline bitfld.long 0x8 17. "CLUT3_1_RAMECC_PEND,Interrupt Pending Status for clut3_1_ramecc_pend" "0,1" newline bitfld.long 0x8 16. "CLUT3_0_RAMECC_PEND,Interrupt Pending Status for clut3_0_ramecc_pend" "0,1" newline bitfld.long 0x8 15. "CLUT2_1_RAMECC_PEND,Interrupt Pending Status for clut2_1_ramecc_pend" "0,1" newline bitfld.long 0x8 14. "CLUT2_0_RAMECC_PEND,Interrupt Pending Status for clut2_0_ramecc_pend" "0,1" newline bitfld.long 0x8 13. "CLUT1_1_RAMECC_PEND,Interrupt Pending Status for clut1_1_ramecc_pend" "0,1" newline bitfld.long 0x8 12. "CLUT1_0_RAMECC_PEND,Interrupt Pending Status for clut1_0_ramecc_pend" "0,1" newline bitfld.long 0x8 11. "CLUT0_1_RAMECC_PEND,Interrupt Pending Status for clut0_1_ramecc_pend" "0,1" newline bitfld.long 0x8 10. "CLUT0_0_RAMECC_PEND,Interrupt Pending Status for clut0_0_ramecc_pend" "0,1" newline bitfld.long 0x8 9. "HIST_DATA_B1_RAMECC_PEND,Interrupt Pending Status for hist_data_b1_ramecc_pend" "0,1" newline bitfld.long 0x8 8. "HIST_DATA_B0_RAMECC_PEND,Interrupt Pending Status for hist_data_b0_ramecc_pend" "0,1" newline bitfld.long 0x8 7. "HIST_LUT_B1_RAMECC_PEND,Interrupt Pending Status for hist_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x8 6. "HIST_LUT_B0_RAMECC_PEND,Interrupt Pending Status for hist_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x8 5. "EELUT_1_RAMECC_PEND,Interrupt Pending Status for eelut_1_ramecc_pend" "0,1" newline bitfld.long 0x8 4. "EELUT_0_RAMECC_PEND,Interrupt Pending Status for eelut_0_ramecc_pend" "0,1" newline bitfld.long 0x8 3. "LUT_1_RAMECC_PEND,Interrupt Pending Status for lut_1_ramecc_pend" "0,1" newline bitfld.long 0x8 2. "LUT_0_RAMECC_PEND,Interrupt Pending Status for lut_0_ramecc_pend" "0,1" newline bitfld.long 0x8 1. "FCC_LUT2_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 0. "FCC_LUT2_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_lut2_ram0_ramecc_pend" "0,1" line.long 0xC "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_status_reg2,Interrupt Status Register 2" bitfld.long 0xC 28. "MESHLUT_RAMECC_PEND,Interrupt Pending Status for meshlut_ramecc_pend" "0,1" newline bitfld.long 0xC 27. "FCP2_EELUT_1_RAMECC_PEND,Interrupt Pending Status for fcp2_eelut_1_ramecc_pend" "0,1" newline bitfld.long 0xC 26. "FCP2_EELUT_0_RAMECC_PEND,Interrupt Pending Status for fcp2_eelut_0_ramecc_pend" "0,1" newline bitfld.long 0xC 25. "FCP2_DLUT3_1_RAMECC_PEND,Interrupt Pending Status for fcp2_dlut3_1_ramecc_pend" "0,1" newline bitfld.long 0xC 24. "FCP2_DLUT3_0_RAMECC_PEND,Interrupt Pending Status for fcp2_dlut3_0_ramecc_pend" "0,1" newline bitfld.long 0xC 23. "FCP2_DLUT2_1_RAMECC_PEND,Interrupt Pending Status for fcp2_dlut2_1_ramecc_pend" "0,1" newline bitfld.long 0xC 22. "FCP2_DLUT2_0_RAMECC_PEND,Interrupt Pending Status for fcp2_dlut2_0_ramecc_pend" "0,1" newline bitfld.long 0xC 21. "FCP2_DLUT1_1_RAMECC_PEND,Interrupt Pending Status for fcp2_dlut1_1_ramecc_pend" "0,1" newline bitfld.long 0xC 20. "FCP2_DLUT1_0_RAMECC_PEND,Interrupt Pending Status for fcp2_dlut1_0_ramecc_pend" "0,1" newline bitfld.long 0xC 19. "FCP2_DLUT0_1_RAMECC_PEND,Interrupt Pending Status for fcp2_dlut0_1_ramecc_pend" "0,1" newline bitfld.long 0xC 18. "FCP2_DLUT0_0_RAMECC_PEND,Interrupt Pending Status for fcp2_dlut0_0_ramecc_pend" "0,1" newline bitfld.long 0xC 17. "FCP2_CLUT3_1_RAMECC_PEND,Interrupt Pending Status for fcp2_clut3_1_ramecc_pend" "0,1" newline bitfld.long 0xC 16. "FCP2_CLUT3_0_RAMECC_PEND,Interrupt Pending Status for fcp2_clut3_0_ramecc_pend" "0,1" newline bitfld.long 0xC 15. "FCP2_CLUT2_1_RAMECC_PEND,Interrupt Pending Status for fcp2_clut2_1_ramecc_pend" "0,1" newline bitfld.long 0xC 14. "FCP2_CLUT2_0_RAMECC_PEND,Interrupt Pending Status for fcp2_clut2_0_ramecc_pend" "0,1" newline bitfld.long 0xC 13. "FCP2_CLUT1_1_RAMECC_PEND,Interrupt Pending Status for fcp2_clut1_1_ramecc_pend" "0,1" newline bitfld.long 0xC 12. "FCP2_CLUT1_0_RAMECC_PEND,Interrupt Pending Status for fcp2_clut1_0_ramecc_pend" "0,1" newline bitfld.long 0xC 11. "FCP2_CLUT0_1_RAMECC_PEND,Interrupt Pending Status for fcp2_clut0_1_ramecc_pend" "0,1" newline bitfld.long 0xC 10. "FCP2_CLUT0_0_RAMECC_PEND,Interrupt Pending Status for fcp2_clut0_0_ramecc_pend" "0,1" newline bitfld.long 0xC 9. "FCP2_LUT_1_RAMECC_PEND,Interrupt Pending Status for fcp2_lut_1_ramecc_pend" "0,1" newline bitfld.long 0xC 8. "FCP2_LUT_0_RAMECC_PEND,Interrupt Pending Status for fcp2_lut_0_ramecc_pend" "0,1" newline bitfld.long 0xC 7. "FCP2_FCC_LUT2_RAM1_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0xC 6. "FCP2_FCC_LUT2_RAM0_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0xC 5. "FCP2_FCC_LUT1_RAM1_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0xC 4. "FCP2_FCC_LUT1_RAM0_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0xC 3. "FCP2_FCC_LUT0_RAM1_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_lut0_ram1_ramecc_pend" "0,1" newline bitfld.long 0xC 2. "FCP2_FCC_LUT0_RAM0_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_lut0_ram0_ramecc_pend" "0,1" newline bitfld.long 0xC 1. "FCP2_FCC_CONT_LUT3_RAM1_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_cont_lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0xC 0. "FCP2_FCC_CONT_LUT3_RAM0_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_cont_lut3_ram0_ramecc_pend" "0,1" rgroup.long 0x80++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "FCC_LUT1_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "FCC_LUT1_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "FCC_LUT0_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut0_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "FCC_LUT0_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut0_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "FCC_CONT_LUT3_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "FCC_CONT_LUT3_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut3_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "FCC_CONT_LUT2_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 24. "FCC_CONT_LUT2_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "FCC_CONT_LUT1_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 22. "FCC_CONT_LUT1_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "FCC_HIST_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_hist_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "FCC_HIST_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_hist_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 19. "STAT_MEM7_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem7_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "STAT_MEM6_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem6_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "STAT_MEM5_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem5_ramecc_pend" "0,1" newline bitfld.long 0x0 16. "STAT_MEM4_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem4_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "STAT_MEM3_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem3_ramecc_pend" "0,1" newline bitfld.long 0x0 14. "STAT_MEM2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem2_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "STAT_MEM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem1_ramecc_pend" "0,1" newline bitfld.long 0x0 12. "STAT_MEM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem0_ramecc_pend" "0,1" newline bitfld.long 0x0 11. "H3A_LUT_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for h3a_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "H3A_LUT_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for h3a_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "LSC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lsc_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "DPC_LUT_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dpc_lut_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "WDR_LUT_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for wdr_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "WDR_LUT_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for wdr_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "LUT1_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "LUT1_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "LUT2_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "LUT2_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "LUT3_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "LUT3_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut3_ram0_ramecc_pend" "0,1" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 31. "FCP2_FCC_CONT_LUT2_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_cont_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 30. "FCP2_FCC_CONT_LUT2_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_cont_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 29. "FCP2_FCC_CONT_LUT1_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_cont_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 28. "FCP2_FCC_CONT_LUT1_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_cont_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 27. "FCP2_FCC_HIST_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_hist_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "FCP2_FCC_HIST_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_hist_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 25. "DLUT3_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut3_1_ramecc_pend" "0,1" newline bitfld.long 0x4 24. "DLUT3_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut3_0_ramecc_pend" "0,1" newline bitfld.long 0x4 23. "DLUT2_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut2_1_ramecc_pend" "0,1" newline bitfld.long 0x4 22. "DLUT2_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut2_0_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "DLUT1_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut1_1_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "DLUT1_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut1_0_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "DLUT0_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut0_1_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "DLUT0_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut0_0_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "CLUT3_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut3_1_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "CLUT3_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut3_0_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "CLUT2_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut2_1_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "CLUT2_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut2_0_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "CLUT1_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut1_1_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "CLUT1_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut1_0_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "CLUT0_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut0_1_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "CLUT0_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut0_0_ramecc_pend" "0,1" newline bitfld.long 0x4 9. "HIST_DATA_B1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hist_data_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 8. "HIST_DATA_B0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hist_data_b0_ramecc_pend" "0,1" newline bitfld.long 0x4 7. "HIST_LUT_B1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hist_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "HIST_LUT_B0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hist_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "EELUT_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for eelut_1_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "EELUT_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for eelut_0_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "LUT_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut_1_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "LUT_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut_0_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "FCC_LUT2_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "FCC_LUT2_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut2_ram0_ramecc_pend" "0,1" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_enable_set_reg2,Interrupt Enable Set Register 2" bitfld.long 0x8 28. "MESHLUT_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshlut_ramecc_pend" "0,1" newline bitfld.long 0x8 27. "FCP2_EELUT_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_eelut_1_ramecc_pend" "0,1" newline bitfld.long 0x8 26. "FCP2_EELUT_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_eelut_0_ramecc_pend" "0,1" newline bitfld.long 0x8 25. "FCP2_DLUT3_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_dlut3_1_ramecc_pend" "0,1" newline bitfld.long 0x8 24. "FCP2_DLUT3_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_dlut3_0_ramecc_pend" "0,1" newline bitfld.long 0x8 23. "FCP2_DLUT2_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_dlut2_1_ramecc_pend" "0,1" newline bitfld.long 0x8 22. "FCP2_DLUT2_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_dlut2_0_ramecc_pend" "0,1" newline bitfld.long 0x8 21. "FCP2_DLUT1_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_dlut1_1_ramecc_pend" "0,1" newline bitfld.long 0x8 20. "FCP2_DLUT1_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_dlut1_0_ramecc_pend" "0,1" newline bitfld.long 0x8 19. "FCP2_DLUT0_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_dlut0_1_ramecc_pend" "0,1" newline bitfld.long 0x8 18. "FCP2_DLUT0_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_dlut0_0_ramecc_pend" "0,1" newline bitfld.long 0x8 17. "FCP2_CLUT3_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_clut3_1_ramecc_pend" "0,1" newline bitfld.long 0x8 16. "FCP2_CLUT3_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_clut3_0_ramecc_pend" "0,1" newline bitfld.long 0x8 15. "FCP2_CLUT2_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_clut2_1_ramecc_pend" "0,1" newline bitfld.long 0x8 14. "FCP2_CLUT2_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_clut2_0_ramecc_pend" "0,1" newline bitfld.long 0x8 13. "FCP2_CLUT1_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_clut1_1_ramecc_pend" "0,1" newline bitfld.long 0x8 12. "FCP2_CLUT1_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_clut1_0_ramecc_pend" "0,1" newline bitfld.long 0x8 11. "FCP2_CLUT0_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_clut0_1_ramecc_pend" "0,1" newline bitfld.long 0x8 10. "FCP2_CLUT0_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_clut0_0_ramecc_pend" "0,1" newline bitfld.long 0x8 9. "FCP2_LUT_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_lut_1_ramecc_pend" "0,1" newline bitfld.long 0x8 8. "FCP2_LUT_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_lut_0_ramecc_pend" "0,1" newline bitfld.long 0x8 7. "FCP2_FCC_LUT2_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 6. "FCP2_FCC_LUT2_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x8 5. "FCP2_FCC_LUT1_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 4. "FCP2_FCC_LUT1_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x8 3. "FCP2_FCC_LUT0_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_lut0_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 2. "FCP2_FCC_LUT0_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_lut0_ram0_ramecc_pend" "0,1" newline bitfld.long 0x8 1. "FCP2_FCC_CONT_LUT3_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_cont_lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 0. "FCP2_FCC_CONT_LUT3_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_cont_lut3_ram0_ramecc_pend" "0,1" rgroup.long 0xC0++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "FCC_LUT1_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "FCC_LUT1_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "FCC_LUT0_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut0_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "FCC_LUT0_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut0_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "FCC_CONT_LUT3_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "FCC_CONT_LUT3_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut3_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "FCC_CONT_LUT2_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 24. "FCC_CONT_LUT2_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "FCC_CONT_LUT1_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 22. "FCC_CONT_LUT1_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "FCC_HIST_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_hist_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "FCC_HIST_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_hist_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 19. "STAT_MEM7_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem7_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "STAT_MEM6_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem6_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "STAT_MEM5_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem5_ramecc_pend" "0,1" newline bitfld.long 0x0 16. "STAT_MEM4_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem4_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "STAT_MEM3_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem3_ramecc_pend" "0,1" newline bitfld.long 0x0 14. "STAT_MEM2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem2_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "STAT_MEM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem1_ramecc_pend" "0,1" newline bitfld.long 0x0 12. "STAT_MEM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem0_ramecc_pend" "0,1" newline bitfld.long 0x0 11. "H3A_LUT_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for h3a_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "H3A_LUT_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for h3a_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "LSC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lsc_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "DPC_LUT_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dpc_lut_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "WDR_LUT_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for wdr_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "WDR_LUT_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for wdr_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "LUT1_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "LUT1_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "LUT2_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "LUT2_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "LUT3_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "LUT3_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut3_ram0_ramecc_pend" "0,1" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 31. "FCP2_FCC_CONT_LUT2_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_cont_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 30. "FCP2_FCC_CONT_LUT2_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_cont_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 29. "FCP2_FCC_CONT_LUT1_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_cont_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 28. "FCP2_FCC_CONT_LUT1_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_cont_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 27. "FCP2_FCC_HIST_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_hist_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "FCP2_FCC_HIST_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_hist_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 25. "DLUT3_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut3_1_ramecc_pend" "0,1" newline bitfld.long 0x4 24. "DLUT3_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut3_0_ramecc_pend" "0,1" newline bitfld.long 0x4 23. "DLUT2_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut2_1_ramecc_pend" "0,1" newline bitfld.long 0x4 22. "DLUT2_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut2_0_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "DLUT1_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut1_1_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "DLUT1_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut1_0_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "DLUT0_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut0_1_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "DLUT0_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut0_0_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "CLUT3_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut3_1_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "CLUT3_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut3_0_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "CLUT2_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut2_1_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "CLUT2_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut2_0_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "CLUT1_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut1_1_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "CLUT1_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut1_0_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "CLUT0_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut0_1_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "CLUT0_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut0_0_ramecc_pend" "0,1" newline bitfld.long 0x4 9. "HIST_DATA_B1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hist_data_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 8. "HIST_DATA_B0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hist_data_b0_ramecc_pend" "0,1" newline bitfld.long 0x4 7. "HIST_LUT_B1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hist_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "HIST_LUT_B0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hist_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "EELUT_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for eelut_1_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "EELUT_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for eelut_0_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "LUT_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut_1_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "LUT_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut_0_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "FCC_LUT2_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "FCC_LUT2_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut2_ram0_ramecc_pend" "0,1" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_enable_clr_reg2,Interrupt Enable Clear Register 2" bitfld.long 0x8 28. "MESHLUT_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshlut_ramecc_pend" "0,1" newline bitfld.long 0x8 27. "FCP2_EELUT_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_eelut_1_ramecc_pend" "0,1" newline bitfld.long 0x8 26. "FCP2_EELUT_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_eelut_0_ramecc_pend" "0,1" newline bitfld.long 0x8 25. "FCP2_DLUT3_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_dlut3_1_ramecc_pend" "0,1" newline bitfld.long 0x8 24. "FCP2_DLUT3_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_dlut3_0_ramecc_pend" "0,1" newline bitfld.long 0x8 23. "FCP2_DLUT2_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_dlut2_1_ramecc_pend" "0,1" newline bitfld.long 0x8 22. "FCP2_DLUT2_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_dlut2_0_ramecc_pend" "0,1" newline bitfld.long 0x8 21. "FCP2_DLUT1_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_dlut1_1_ramecc_pend" "0,1" newline bitfld.long 0x8 20. "FCP2_DLUT1_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_dlut1_0_ramecc_pend" "0,1" newline bitfld.long 0x8 19. "FCP2_DLUT0_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_dlut0_1_ramecc_pend" "0,1" newline bitfld.long 0x8 18. "FCP2_DLUT0_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_dlut0_0_ramecc_pend" "0,1" newline bitfld.long 0x8 17. "FCP2_CLUT3_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_clut3_1_ramecc_pend" "0,1" newline bitfld.long 0x8 16. "FCP2_CLUT3_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_clut3_0_ramecc_pend" "0,1" newline bitfld.long 0x8 15. "FCP2_CLUT2_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_clut2_1_ramecc_pend" "0,1" newline bitfld.long 0x8 14. "FCP2_CLUT2_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_clut2_0_ramecc_pend" "0,1" newline bitfld.long 0x8 13. "FCP2_CLUT1_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_clut1_1_ramecc_pend" "0,1" newline bitfld.long 0x8 12. "FCP2_CLUT1_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_clut1_0_ramecc_pend" "0,1" newline bitfld.long 0x8 11. "FCP2_CLUT0_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_clut0_1_ramecc_pend" "0,1" newline bitfld.long 0x8 10. "FCP2_CLUT0_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_clut0_0_ramecc_pend" "0,1" newline bitfld.long 0x8 9. "FCP2_LUT_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_lut_1_ramecc_pend" "0,1" newline bitfld.long 0x8 8. "FCP2_LUT_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_lut_0_ramecc_pend" "0,1" newline bitfld.long 0x8 7. "FCP2_FCC_LUT2_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 6. "FCP2_FCC_LUT2_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x8 5. "FCP2_FCC_LUT1_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 4. "FCP2_FCC_LUT1_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x8 3. "FCP2_FCC_LUT0_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_lut0_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 2. "FCP2_FCC_LUT0_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_lut0_ram0_ramecc_pend" "0,1" newline bitfld.long 0x8 1. "FCP2_FCC_CONT_LUT3_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_cont_lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 0. "FCP2_FCC_CONT_LUT3_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_cont_lut3_ram0_ramecc_pend" "0,1" rgroup.long 0x13C++0xF line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "FCC_LUT1_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 30. "FCC_LUT1_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 29. "FCC_LUT0_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_lut0_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 28. "FCC_LUT0_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_lut0_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 27. "FCC_CONT_LUT3_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "FCC_CONT_LUT3_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut3_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 25. "FCC_CONT_LUT2_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 24. "FCC_CONT_LUT2_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 23. "FCC_CONT_LUT1_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 22. "FCC_CONT_LUT1_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "FCC_HIST_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_hist_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "FCC_HIST_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_hist_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "STAT_MEM7_RAMECC_PEND,Interrupt Pending Status for stat_mem7_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "STAT_MEM6_RAMECC_PEND,Interrupt Pending Status for stat_mem6_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "STAT_MEM5_RAMECC_PEND,Interrupt Pending Status for stat_mem5_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "STAT_MEM4_RAMECC_PEND,Interrupt Pending Status for stat_mem4_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "STAT_MEM3_RAMECC_PEND,Interrupt Pending Status for stat_mem3_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "STAT_MEM2_RAMECC_PEND,Interrupt Pending Status for stat_mem2_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "STAT_MEM1_RAMECC_PEND,Interrupt Pending Status for stat_mem1_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "STAT_MEM0_RAMECC_PEND,Interrupt Pending Status for stat_mem0_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "H3A_LUT_RAM1_RAMECC_PEND,Interrupt Pending Status for h3a_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "H3A_LUT_RAM0_RAMECC_PEND,Interrupt Pending Status for h3a_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 9. "LSC_RAMECC_PEND,Interrupt Pending Status for lsc_ramecc_pend" "0,1" newline bitfld.long 0x4 8. "DPC_LUT_RAMECC_PEND,Interrupt Pending Status for dpc_lut_ramecc_pend" "0,1" newline bitfld.long 0x4 7. "WDR_LUT_RAM1_RAMECC_PEND,Interrupt Pending Status for wdr_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "WDR_LUT_RAM0_RAMECC_PEND,Interrupt Pending Status for wdr_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "LUT1_RAM1_RAMECC_PEND,Interrupt Pending Status for lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "LUT1_RAM0_RAMECC_PEND,Interrupt Pending Status for lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "LUT2_RAM1_RAMECC_PEND,Interrupt Pending Status for lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "LUT2_RAM0_RAMECC_PEND,Interrupt Pending Status for lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "LUT3_RAM1_RAMECC_PEND,Interrupt Pending Status for lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "LUT3_RAM0_RAMECC_PEND,Interrupt Pending Status for lut3_ram0_ramecc_pend" "0,1" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 31. "FCP2_FCC_CONT_LUT2_RAM1_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_cont_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 30. "FCP2_FCC_CONT_LUT2_RAM0_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_cont_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x8 29. "FCP2_FCC_CONT_LUT1_RAM1_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_cont_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 28. "FCP2_FCC_CONT_LUT1_RAM0_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_cont_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x8 27. "FCP2_FCC_HIST_RAM1_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_hist_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 26. "FCP2_FCC_HIST_RAM0_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_hist_ram0_ramecc_pend" "0,1" newline bitfld.long 0x8 25. "DLUT3_1_RAMECC_PEND,Interrupt Pending Status for dlut3_1_ramecc_pend" "0,1" newline bitfld.long 0x8 24. "DLUT3_0_RAMECC_PEND,Interrupt Pending Status for dlut3_0_ramecc_pend" "0,1" newline bitfld.long 0x8 23. "DLUT2_1_RAMECC_PEND,Interrupt Pending Status for dlut2_1_ramecc_pend" "0,1" newline bitfld.long 0x8 22. "DLUT2_0_RAMECC_PEND,Interrupt Pending Status for dlut2_0_ramecc_pend" "0,1" newline bitfld.long 0x8 21. "DLUT1_1_RAMECC_PEND,Interrupt Pending Status for dlut1_1_ramecc_pend" "0,1" newline bitfld.long 0x8 20. "DLUT1_0_RAMECC_PEND,Interrupt Pending Status for dlut1_0_ramecc_pend" "0,1" newline bitfld.long 0x8 19. "DLUT0_1_RAMECC_PEND,Interrupt Pending Status for dlut0_1_ramecc_pend" "0,1" newline bitfld.long 0x8 18. "DLUT0_0_RAMECC_PEND,Interrupt Pending Status for dlut0_0_ramecc_pend" "0,1" newline bitfld.long 0x8 17. "CLUT3_1_RAMECC_PEND,Interrupt Pending Status for clut3_1_ramecc_pend" "0,1" newline bitfld.long 0x8 16. "CLUT3_0_RAMECC_PEND,Interrupt Pending Status for clut3_0_ramecc_pend" "0,1" newline bitfld.long 0x8 15. "CLUT2_1_RAMECC_PEND,Interrupt Pending Status for clut2_1_ramecc_pend" "0,1" newline bitfld.long 0x8 14. "CLUT2_0_RAMECC_PEND,Interrupt Pending Status for clut2_0_ramecc_pend" "0,1" newline bitfld.long 0x8 13. "CLUT1_1_RAMECC_PEND,Interrupt Pending Status for clut1_1_ramecc_pend" "0,1" newline bitfld.long 0x8 12. "CLUT1_0_RAMECC_PEND,Interrupt Pending Status for clut1_0_ramecc_pend" "0,1" newline bitfld.long 0x8 11. "CLUT0_1_RAMECC_PEND,Interrupt Pending Status for clut0_1_ramecc_pend" "0,1" newline bitfld.long 0x8 10. "CLUT0_0_RAMECC_PEND,Interrupt Pending Status for clut0_0_ramecc_pend" "0,1" newline bitfld.long 0x8 9. "HIST_DATA_B1_RAMECC_PEND,Interrupt Pending Status for hist_data_b1_ramecc_pend" "0,1" newline bitfld.long 0x8 8. "HIST_DATA_B0_RAMECC_PEND,Interrupt Pending Status for hist_data_b0_ramecc_pend" "0,1" newline bitfld.long 0x8 7. "HIST_LUT_B1_RAMECC_PEND,Interrupt Pending Status for hist_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x8 6. "HIST_LUT_B0_RAMECC_PEND,Interrupt Pending Status for hist_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x8 5. "EELUT_1_RAMECC_PEND,Interrupt Pending Status for eelut_1_ramecc_pend" "0,1" newline bitfld.long 0x8 4. "EELUT_0_RAMECC_PEND,Interrupt Pending Status for eelut_0_ramecc_pend" "0,1" newline bitfld.long 0x8 3. "LUT_1_RAMECC_PEND,Interrupt Pending Status for lut_1_ramecc_pend" "0,1" newline bitfld.long 0x8 2. "LUT_0_RAMECC_PEND,Interrupt Pending Status for lut_0_ramecc_pend" "0,1" newline bitfld.long 0x8 1. "FCC_LUT2_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 0. "FCC_LUT2_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_lut2_ram0_ramecc_pend" "0,1" line.long 0xC "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_status_reg2,Interrupt Status Register 2" bitfld.long 0xC 28. "MESHLUT_RAMECC_PEND,Interrupt Pending Status for meshlut_ramecc_pend" "0,1" newline bitfld.long 0xC 27. "FCP2_EELUT_1_RAMECC_PEND,Interrupt Pending Status for fcp2_eelut_1_ramecc_pend" "0,1" newline bitfld.long 0xC 26. "FCP2_EELUT_0_RAMECC_PEND,Interrupt Pending Status for fcp2_eelut_0_ramecc_pend" "0,1" newline bitfld.long 0xC 25. "FCP2_DLUT3_1_RAMECC_PEND,Interrupt Pending Status for fcp2_dlut3_1_ramecc_pend" "0,1" newline bitfld.long 0xC 24. "FCP2_DLUT3_0_RAMECC_PEND,Interrupt Pending Status for fcp2_dlut3_0_ramecc_pend" "0,1" newline bitfld.long 0xC 23. "FCP2_DLUT2_1_RAMECC_PEND,Interrupt Pending Status for fcp2_dlut2_1_ramecc_pend" "0,1" newline bitfld.long 0xC 22. "FCP2_DLUT2_0_RAMECC_PEND,Interrupt Pending Status for fcp2_dlut2_0_ramecc_pend" "0,1" newline bitfld.long 0xC 21. "FCP2_DLUT1_1_RAMECC_PEND,Interrupt Pending Status for fcp2_dlut1_1_ramecc_pend" "0,1" newline bitfld.long 0xC 20. "FCP2_DLUT1_0_RAMECC_PEND,Interrupt Pending Status for fcp2_dlut1_0_ramecc_pend" "0,1" newline bitfld.long 0xC 19. "FCP2_DLUT0_1_RAMECC_PEND,Interrupt Pending Status for fcp2_dlut0_1_ramecc_pend" "0,1" newline bitfld.long 0xC 18. "FCP2_DLUT0_0_RAMECC_PEND,Interrupt Pending Status for fcp2_dlut0_0_ramecc_pend" "0,1" newline bitfld.long 0xC 17. "FCP2_CLUT3_1_RAMECC_PEND,Interrupt Pending Status for fcp2_clut3_1_ramecc_pend" "0,1" newline bitfld.long 0xC 16. "FCP2_CLUT3_0_RAMECC_PEND,Interrupt Pending Status for fcp2_clut3_0_ramecc_pend" "0,1" newline bitfld.long 0xC 15. "FCP2_CLUT2_1_RAMECC_PEND,Interrupt Pending Status for fcp2_clut2_1_ramecc_pend" "0,1" newline bitfld.long 0xC 14. "FCP2_CLUT2_0_RAMECC_PEND,Interrupt Pending Status for fcp2_clut2_0_ramecc_pend" "0,1" newline bitfld.long 0xC 13. "FCP2_CLUT1_1_RAMECC_PEND,Interrupt Pending Status for fcp2_clut1_1_ramecc_pend" "0,1" newline bitfld.long 0xC 12. "FCP2_CLUT1_0_RAMECC_PEND,Interrupt Pending Status for fcp2_clut1_0_ramecc_pend" "0,1" newline bitfld.long 0xC 11. "FCP2_CLUT0_1_RAMECC_PEND,Interrupt Pending Status for fcp2_clut0_1_ramecc_pend" "0,1" newline bitfld.long 0xC 10. "FCP2_CLUT0_0_RAMECC_PEND,Interrupt Pending Status for fcp2_clut0_0_ramecc_pend" "0,1" newline bitfld.long 0xC 9. "FCP2_LUT_1_RAMECC_PEND,Interrupt Pending Status for fcp2_lut_1_ramecc_pend" "0,1" newline bitfld.long 0xC 8. "FCP2_LUT_0_RAMECC_PEND,Interrupt Pending Status for fcp2_lut_0_ramecc_pend" "0,1" newline bitfld.long 0xC 7. "FCP2_FCC_LUT2_RAM1_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0xC 6. "FCP2_FCC_LUT2_RAM0_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0xC 5. "FCP2_FCC_LUT1_RAM1_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0xC 4. "FCP2_FCC_LUT1_RAM0_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0xC 3. "FCP2_FCC_LUT0_RAM1_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_lut0_ram1_ramecc_pend" "0,1" newline bitfld.long 0xC 2. "FCP2_FCC_LUT0_RAM0_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_lut0_ram0_ramecc_pend" "0,1" newline bitfld.long 0xC 1. "FCP2_FCC_CONT_LUT3_RAM1_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_cont_lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0xC 0. "FCP2_FCC_CONT_LUT3_RAM0_RAMECC_PEND,Interrupt Pending Status for fcp2_fcc_cont_lut3_ram0_ramecc_pend" "0,1" rgroup.long 0x180++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "FCC_LUT1_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "FCC_LUT1_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "FCC_LUT0_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut0_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "FCC_LUT0_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut0_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "FCC_CONT_LUT3_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "FCC_CONT_LUT3_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut3_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "FCC_CONT_LUT2_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 24. "FCC_CONT_LUT2_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "FCC_CONT_LUT1_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 22. "FCC_CONT_LUT1_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "FCC_HIST_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_hist_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "FCC_HIST_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_hist_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 19. "STAT_MEM7_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem7_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "STAT_MEM6_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem6_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "STAT_MEM5_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem5_ramecc_pend" "0,1" newline bitfld.long 0x0 16. "STAT_MEM4_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem4_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "STAT_MEM3_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem3_ramecc_pend" "0,1" newline bitfld.long 0x0 14. "STAT_MEM2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem2_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "STAT_MEM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem1_ramecc_pend" "0,1" newline bitfld.long 0x0 12. "STAT_MEM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem0_ramecc_pend" "0,1" newline bitfld.long 0x0 11. "H3A_LUT_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for h3a_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "H3A_LUT_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for h3a_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "LSC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lsc_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "DPC_LUT_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dpc_lut_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "WDR_LUT_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for wdr_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "WDR_LUT_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for wdr_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "LUT1_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "LUT1_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "LUT2_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "LUT2_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "LUT3_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "LUT3_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut3_ram0_ramecc_pend" "0,1" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 31. "FCP2_FCC_CONT_LUT2_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_cont_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 30. "FCP2_FCC_CONT_LUT2_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_cont_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 29. "FCP2_FCC_CONT_LUT1_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_cont_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 28. "FCP2_FCC_CONT_LUT1_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_cont_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 27. "FCP2_FCC_HIST_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_hist_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "FCP2_FCC_HIST_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_hist_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 25. "DLUT3_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut3_1_ramecc_pend" "0,1" newline bitfld.long 0x4 24. "DLUT3_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut3_0_ramecc_pend" "0,1" newline bitfld.long 0x4 23. "DLUT2_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut2_1_ramecc_pend" "0,1" newline bitfld.long 0x4 22. "DLUT2_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut2_0_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "DLUT1_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut1_1_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "DLUT1_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut1_0_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "DLUT0_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut0_1_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "DLUT0_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut0_0_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "CLUT3_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut3_1_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "CLUT3_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut3_0_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "CLUT2_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut2_1_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "CLUT2_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut2_0_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "CLUT1_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut1_1_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "CLUT1_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut1_0_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "CLUT0_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut0_1_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "CLUT0_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut0_0_ramecc_pend" "0,1" newline bitfld.long 0x4 9. "HIST_DATA_B1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hist_data_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 8. "HIST_DATA_B0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hist_data_b0_ramecc_pend" "0,1" newline bitfld.long 0x4 7. "HIST_LUT_B1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hist_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "HIST_LUT_B0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hist_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "EELUT_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for eelut_1_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "EELUT_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for eelut_0_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "LUT_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut_1_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "LUT_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut_0_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "FCC_LUT2_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "FCC_LUT2_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut2_ram0_ramecc_pend" "0,1" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_enable_set_reg2,Interrupt Enable Set Register 2" bitfld.long 0x8 28. "MESHLUT_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshlut_ramecc_pend" "0,1" newline bitfld.long 0x8 27. "FCP2_EELUT_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_eelut_1_ramecc_pend" "0,1" newline bitfld.long 0x8 26. "FCP2_EELUT_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_eelut_0_ramecc_pend" "0,1" newline bitfld.long 0x8 25. "FCP2_DLUT3_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_dlut3_1_ramecc_pend" "0,1" newline bitfld.long 0x8 24. "FCP2_DLUT3_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_dlut3_0_ramecc_pend" "0,1" newline bitfld.long 0x8 23. "FCP2_DLUT2_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_dlut2_1_ramecc_pend" "0,1" newline bitfld.long 0x8 22. "FCP2_DLUT2_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_dlut2_0_ramecc_pend" "0,1" newline bitfld.long 0x8 21. "FCP2_DLUT1_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_dlut1_1_ramecc_pend" "0,1" newline bitfld.long 0x8 20. "FCP2_DLUT1_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_dlut1_0_ramecc_pend" "0,1" newline bitfld.long 0x8 19. "FCP2_DLUT0_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_dlut0_1_ramecc_pend" "0,1" newline bitfld.long 0x8 18. "FCP2_DLUT0_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_dlut0_0_ramecc_pend" "0,1" newline bitfld.long 0x8 17. "FCP2_CLUT3_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_clut3_1_ramecc_pend" "0,1" newline bitfld.long 0x8 16. "FCP2_CLUT3_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_clut3_0_ramecc_pend" "0,1" newline bitfld.long 0x8 15. "FCP2_CLUT2_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_clut2_1_ramecc_pend" "0,1" newline bitfld.long 0x8 14. "FCP2_CLUT2_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_clut2_0_ramecc_pend" "0,1" newline bitfld.long 0x8 13. "FCP2_CLUT1_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_clut1_1_ramecc_pend" "0,1" newline bitfld.long 0x8 12. "FCP2_CLUT1_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_clut1_0_ramecc_pend" "0,1" newline bitfld.long 0x8 11. "FCP2_CLUT0_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_clut0_1_ramecc_pend" "0,1" newline bitfld.long 0x8 10. "FCP2_CLUT0_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_clut0_0_ramecc_pend" "0,1" newline bitfld.long 0x8 9. "FCP2_LUT_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_lut_1_ramecc_pend" "0,1" newline bitfld.long 0x8 8. "FCP2_LUT_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_lut_0_ramecc_pend" "0,1" newline bitfld.long 0x8 7. "FCP2_FCC_LUT2_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 6. "FCP2_FCC_LUT2_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x8 5. "FCP2_FCC_LUT1_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 4. "FCP2_FCC_LUT1_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x8 3. "FCP2_FCC_LUT0_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_lut0_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 2. "FCP2_FCC_LUT0_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_lut0_ram0_ramecc_pend" "0,1" newline bitfld.long 0x8 1. "FCP2_FCC_CONT_LUT3_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_cont_lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 0. "FCP2_FCC_CONT_LUT3_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcp2_fcc_cont_lut3_ram0_ramecc_pend" "0,1" rgroup.long 0x1C0++0xB line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "FCC_LUT1_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "FCC_LUT1_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "FCC_LUT0_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut0_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "FCC_LUT0_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut0_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "FCC_CONT_LUT3_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "FCC_CONT_LUT3_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut3_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "FCC_CONT_LUT2_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 24. "FCC_CONT_LUT2_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "FCC_CONT_LUT1_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 22. "FCC_CONT_LUT1_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "FCC_HIST_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_hist_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "FCC_HIST_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_hist_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 19. "STAT_MEM7_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem7_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "STAT_MEM6_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem6_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "STAT_MEM5_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem5_ramecc_pend" "0,1" newline bitfld.long 0x0 16. "STAT_MEM4_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem4_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "STAT_MEM3_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem3_ramecc_pend" "0,1" newline bitfld.long 0x0 14. "STAT_MEM2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem2_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "STAT_MEM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem1_ramecc_pend" "0,1" newline bitfld.long 0x0 12. "STAT_MEM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem0_ramecc_pend" "0,1" newline bitfld.long 0x0 11. "H3A_LUT_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for h3a_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "H3A_LUT_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for h3a_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "LSC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lsc_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "DPC_LUT_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dpc_lut_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "WDR_LUT_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for wdr_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "WDR_LUT_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for wdr_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "LUT1_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "LUT1_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "LUT2_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "LUT2_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "LUT3_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "LUT3_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut3_ram0_ramecc_pend" "0,1" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 31. "FCP2_FCC_CONT_LUT2_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_cont_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 30. "FCP2_FCC_CONT_LUT2_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_cont_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 29. "FCP2_FCC_CONT_LUT1_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_cont_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 28. "FCP2_FCC_CONT_LUT1_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_cont_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 27. "FCP2_FCC_HIST_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_hist_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "FCP2_FCC_HIST_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_hist_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 25. "DLUT3_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut3_1_ramecc_pend" "0,1" newline bitfld.long 0x4 24. "DLUT3_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut3_0_ramecc_pend" "0,1" newline bitfld.long 0x4 23. "DLUT2_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut2_1_ramecc_pend" "0,1" newline bitfld.long 0x4 22. "DLUT2_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut2_0_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "DLUT1_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut1_1_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "DLUT1_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut1_0_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "DLUT0_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut0_1_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "DLUT0_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut0_0_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "CLUT3_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut3_1_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "CLUT3_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut3_0_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "CLUT2_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut2_1_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "CLUT2_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut2_0_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "CLUT1_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut1_1_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "CLUT1_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut1_0_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "CLUT0_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut0_1_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "CLUT0_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut0_0_ramecc_pend" "0,1" newline bitfld.long 0x4 9. "HIST_DATA_B1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hist_data_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 8. "HIST_DATA_B0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hist_data_b0_ramecc_pend" "0,1" newline bitfld.long 0x4 7. "HIST_LUT_B1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hist_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "HIST_LUT_B0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hist_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "EELUT_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for eelut_1_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "EELUT_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for eelut_0_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "LUT_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut_1_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "LUT_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut_0_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "FCC_LUT2_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "FCC_LUT2_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut2_ram0_ramecc_pend" "0,1" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_enable_clr_reg2,Interrupt Enable Clear Register 2" bitfld.long 0x8 28. "MESHLUT_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshlut_ramecc_pend" "0,1" newline bitfld.long 0x8 27. "FCP2_EELUT_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_eelut_1_ramecc_pend" "0,1" newline bitfld.long 0x8 26. "FCP2_EELUT_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_eelut_0_ramecc_pend" "0,1" newline bitfld.long 0x8 25. "FCP2_DLUT3_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_dlut3_1_ramecc_pend" "0,1" newline bitfld.long 0x8 24. "FCP2_DLUT3_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_dlut3_0_ramecc_pend" "0,1" newline bitfld.long 0x8 23. "FCP2_DLUT2_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_dlut2_1_ramecc_pend" "0,1" newline bitfld.long 0x8 22. "FCP2_DLUT2_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_dlut2_0_ramecc_pend" "0,1" newline bitfld.long 0x8 21. "FCP2_DLUT1_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_dlut1_1_ramecc_pend" "0,1" newline bitfld.long 0x8 20. "FCP2_DLUT1_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_dlut1_0_ramecc_pend" "0,1" newline bitfld.long 0x8 19. "FCP2_DLUT0_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_dlut0_1_ramecc_pend" "0,1" newline bitfld.long 0x8 18. "FCP2_DLUT0_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_dlut0_0_ramecc_pend" "0,1" newline bitfld.long 0x8 17. "FCP2_CLUT3_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_clut3_1_ramecc_pend" "0,1" newline bitfld.long 0x8 16. "FCP2_CLUT3_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_clut3_0_ramecc_pend" "0,1" newline bitfld.long 0x8 15. "FCP2_CLUT2_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_clut2_1_ramecc_pend" "0,1" newline bitfld.long 0x8 14. "FCP2_CLUT2_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_clut2_0_ramecc_pend" "0,1" newline bitfld.long 0x8 13. "FCP2_CLUT1_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_clut1_1_ramecc_pend" "0,1" newline bitfld.long 0x8 12. "FCP2_CLUT1_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_clut1_0_ramecc_pend" "0,1" newline bitfld.long 0x8 11. "FCP2_CLUT0_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_clut0_1_ramecc_pend" "0,1" newline bitfld.long 0x8 10. "FCP2_CLUT0_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_clut0_0_ramecc_pend" "0,1" newline bitfld.long 0x8 9. "FCP2_LUT_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_lut_1_ramecc_pend" "0,1" newline bitfld.long 0x8 8. "FCP2_LUT_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_lut_0_ramecc_pend" "0,1" newline bitfld.long 0x8 7. "FCP2_FCC_LUT2_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 6. "FCP2_FCC_LUT2_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x8 5. "FCP2_FCC_LUT1_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 4. "FCP2_FCC_LUT1_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x8 3. "FCP2_FCC_LUT0_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_lut0_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 2. "FCP2_FCC_LUT0_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_lut0_ram0_ramecc_pend" "0,1" newline bitfld.long 0x8 1. "FCP2_FCC_CONT_LUT3_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_cont_lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 0. "FCP2_FCC_CONT_LUT3_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcp2_fcc_cont_lut3_ram0_ramecc_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "VPAC0_VPAC_REGS_VPAC_REGS_CFG_IP_MMRS (VPAC0_VPAC_REGS_VPAC_REGS_CFG_IP_MMRS)" base ad:0x3800000 rgroup.long 0x0++0x3 line.long 0x0 "VPAC_REGS__VPAC_REGS_CFG__IP_MMRS_PID,VPAC PID" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and new scheme. Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU indicator DSPS ==> 0x0 WTBU ==> 0x1 Processors ==> 0x2" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family. If there is no level of software compatibility a new FUNC number and hence PID should be assigned." hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version. R as described in PDR with additional clarifications and definitions below. Must be easily ECO-able or controlled during fabrication. Ideally through a top level metal mask or e-fuse. This number is maintained/owned by IP design.." newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision. X as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. X is part of IP numbering X.Y.R.Z. X changes ONLY when: (1) There is a major feature addition. An.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library (CSL) / Drivers. 0 if non-custom." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision. Y as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. Y changes ONLY when: (1) Features are scaled (up or down). Flexibility exists in that this.." rgroup.long 0x4++0xF line.long 0x0 "VPAC_REGS__VPAC_REGS_CFG__IP_MMRS_ENABLE,VPAC accelerators Enable; used in clock gating accelerator when disabled. NOT SUPPORTED IN current VERSION" bitfld.long 0x0 5. "NF_ENABLE,'1' --> nf is enabled '0' --> nf is disabled" "0,1" bitfld.long 0x0 4. "MSC_ENABLE,'1' --> msc is enabled '0' --> msc is disabled" "0,1" newline bitfld.long 0x0 2. "LDC0_ENABLE,'1' --> ldc0 is enabled '0' --> ldc0 is disabled" "0,1" bitfld.long 0x0 0. "VISS0_ENABLE,'1' --> viss0 is enabled '0' --> viss0 is disabled" "0,1" line.long 0x4 "VPAC_REGS__VPAC_REGS_CFG__IP_MMRS_CG_ENABLE_OVERRIDE,Register to override the dynamic auto clock gating done in VPAC to reduce power.By default these bits are 0. it should be set to 1 only when we encounter some silicon bug." bitfld.long 0x4 28. "VPAC_ASYNC_DATAMST1M2M_CG_NOGATE,'1' --> No clock gating in data_mst1 async m2m '0' --> clock gating enabled" "0,1" bitfld.long 0x4 27. "VPAC_ASYNC_DATAMST0M2M_CG_NOGATE,'1' --> No clock gating in data_mst0 async m2m '0' --> clock gating enabled" "0,1" newline bitfld.long 0x4 26. "VPAC_ASYNC_MEMSLVM2M_CG_NOGATE,'1' --> No clock gating in mem_slv async m2m '0' --> clock gating enabled" "0,1" bitfld.long 0x4 25. "VPAC_ASYNC_LDCM2M_CG_NOGATE,'1' --> No clock gating in ldc_mst async m2m '0' --> clock gating enabled" "0,1" newline bitfld.long 0x4 24. "VPAC_ASYNC_FWMCBASS_CG_NOGATE,'1' --> No clock gating in vpac fw vbusm async cbass '0' --> clock gating enabled" "0,1" bitfld.long 0x4 23. "VPAC_ASYNC_FWPCBASS_CG_NOGATE,'1' --> No clock gating in vpac fw vbusp async cbass '0' --> clock gating enabled" "0,1" newline bitfld.long 0x4 22. "VPAC_ASYNC_CFGCBASS_CG_NOGATE,'1' --> No clock gating in vpac config async cbass '0' --> clock gating enabled" "0,1" bitfld.long 0x4 21. "VPAC_MEMSLVM2M_CG_NOGATE,'1' --> No clock gating in memslv rd reassembly m2m '0' --> clock gating enabled" "0,1" newline bitfld.long 0x4 20. "VPAC_UTC1RDM2M_CG_NOGATE,'1' --> No clock gating in utc1 rd reassembly m2m '0' --> clock gating enabled" "0,1" bitfld.long 0x4 19. "VPAC_UTC0RDM2M_CG_NOGATE,'1' --> No clock gating in utc0 rd reassembly m2m '0' --> clock gating enabled" "0,1" newline bitfld.long 0x4 18. "VPAC_CFGCBASS_CG_NOGATE,'1' --> No clock gating in vpac config cbass '0' --> clock gating enabled" "0,1" bitfld.long 0x4 17. "VISS0_CBASS_CG_NOGATE,'1' --> No clock gating in viss cbass '0' --> clock gating enabled" "0,1" newline bitfld.long 0x4 16. "HTS_CG_OVERRIDE,'1' --> clock gating override '0' --> No clock gating override" "0,1" bitfld.long 0x4 4. "MSC_CG_OVERRIDE,'1' --> clock gating override '0' --> No clock gating override" "0,1" newline bitfld.long 0x4 2. "LDC0_CG_OVERRIDE,'1' --> clock gating override '0' --> No clock gating override" "0,1" bitfld.long 0x4 0. "VISS0_CG_OVERRIDE,'1' --> clock gating override '0' --> No clock gating override" "0,1" line.long 0x8 "VPAC_REGS__VPAC_REGS_CFG__IP_MMRS_VPAC_CTRL,Register to control and do event selection for VPAC module" bitfld.long 0x8 4. "CTSET_DMA_SOC_DBG,select config for CTSET[206:175] '0' --> select UTC1 (NRT) utc1_ctset_intr[31:0] '1' --> Select ldc0_rd utc1_ext utc0_ext master ports (sreq rreq creq stall valid creq)" "0,1" bitfld.long 0x8 3. "CTSET_UTC_SL2_DBG,select config for CTSET[254:239] '0' --> select ext_ctset_event[15:0] '1' --> Select utc1_wr utc1_rd utc0_wr utc0_rd master ports (sreq rreq creq stall valid creq)" "0,1" newline bitfld.long 0x8 2. "CTSET_HWA_SL2_DBG,select config for CTSET[142:111] '0' --> Select UTC1 (NRT) utc1_channel_start[31:0] '1' --> Select nf msc ldc0 viss0 master ports (sreq rreq creq stall valid creq)" "0,1" bitfld.long 0x8 1. "CTSET_RT_UTC_OUT,select config for CTSET[238:207] '0' --> Select UTC1 (NRT) utc1_ctset_intr[63:32] '1' --> Select UTC0 (RT) utc0_ctset_intr[31:0]" "0,1" newline bitfld.long 0x8 0. "CTSET_RT_UTC_IN,select config for CTSET[174:143] '0' --> Select UTC1 (NRT) utc1_channel_start[63:32] '1' --> Select UTC0 (RT) utc0_channel_start[31:0]" "0,1" line.long 0xC "VPAC_REGS__VPAC_REGS_CFG__IP_MMRS_VPAC_TEST_CTRL,Register to control testing config" bitfld.long 0xC 1. "UTC1_CFG_PBIST_OVERRIDE,'1' --> Config pbist mode: forces UTC1 interface to allow free running clock to RAM during config PBIST '0' --> FUNC mode" "0,1" bitfld.long 0xC 0. "UTC0_CFG_PBIST_OVERRIDE,'1' --> Config pbist mode: forces UTC0 interface to allow free running clock to RAM during config PBIST '0' --> FUNC mode" "0,1" tree.end tree.end tree "vusr_dual0_REGS (vusr_dual0_REGS)" base ad:0x2AFD000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0x7 line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 7. "ODF_W1_PEND,Interrupt Pending Status for odf_w1_pend" "0,1" bitfld.long 0x4 6. "ODF_W0_PEND,Interrupt Pending Status for odf_w0_pend" "0,1" bitfld.long 0x4 5. "OCF_W1_PEND,Interrupt Pending Status for ocf_w1_pend" "0,1" bitfld.long 0x4 4. "OCF_W0_PEND,Interrupt Pending Status for ocf_w0_pend" "0,1" newline bitfld.long 0x4 3. "IDF_W1_PEND,Interrupt Pending Status for idf_w1_pend" "0,1" bitfld.long 0x4 2. "IDF_W0_PEND,Interrupt Pending Status for idf_w0_pend" "0,1" bitfld.long 0x4 1. "ICF_W1_PEND,Interrupt Pending Status for icf_w1_pend" "0,1" bitfld.long 0x4 0. "ICF_W0_PEND,Interrupt Pending Status for icf_w0_pend" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 7. "ODF_W1_ENABLE_SET,Interrupt Enable Set Register for odf_w1_pend" "0,1" bitfld.long 0x0 6. "ODF_W0_ENABLE_SET,Interrupt Enable Set Register for odf_w0_pend" "0,1" bitfld.long 0x0 5. "OCF_W1_ENABLE_SET,Interrupt Enable Set Register for ocf_w1_pend" "0,1" bitfld.long 0x0 4. "OCF_W0_ENABLE_SET,Interrupt Enable Set Register for ocf_w0_pend" "0,1" newline bitfld.long 0x0 3. "IDF_W1_ENABLE_SET,Interrupt Enable Set Register for idf_w1_pend" "0,1" bitfld.long 0x0 2. "IDF_W0_ENABLE_SET,Interrupt Enable Set Register for idf_w0_pend" "0,1" bitfld.long 0x0 1. "ICF_W1_ENABLE_SET,Interrupt Enable Set Register for icf_w1_pend" "0,1" bitfld.long 0x0 0. "ICF_W0_ENABLE_SET,Interrupt Enable Set Register for icf_w0_pend" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 7. "ODF_W1_ENABLE_CLR,Interrupt Enable Clear Register for odf_w1_pend" "0,1" bitfld.long 0x0 6. "ODF_W0_ENABLE_CLR,Interrupt Enable Clear Register for odf_w0_pend" "0,1" bitfld.long 0x0 5. "OCF_W1_ENABLE_CLR,Interrupt Enable Clear Register for ocf_w1_pend" "0,1" bitfld.long 0x0 4. "OCF_W0_ENABLE_CLR,Interrupt Enable Clear Register for ocf_w0_pend" "0,1" newline bitfld.long 0x0 3. "IDF_W1_ENABLE_CLR,Interrupt Enable Clear Register for idf_w1_pend" "0,1" bitfld.long 0x0 2. "IDF_W0_ENABLE_CLR,Interrupt Enable Clear Register for idf_w0_pend" "0,1" bitfld.long 0x0 1. "ICF_W1_ENABLE_CLR,Interrupt Enable Clear Register for icf_w1_pend" "0,1" bitfld.long 0x0 0. "ICF_W0_ENABLE_CLR,Interrupt Enable Clear Register for icf_w0_pend" "0,1" rgroup.long 0x13C++0x7 line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 7. "ODF_W1_PEND,Interrupt Pending Status for odf_w1_pend" "0,1" bitfld.long 0x4 6. "ODF_W0_PEND,Interrupt Pending Status for odf_w0_pend" "0,1" bitfld.long 0x4 5. "OCF_W1_PEND,Interrupt Pending Status for ocf_w1_pend" "0,1" bitfld.long 0x4 4. "OCF_W0_PEND,Interrupt Pending Status for ocf_w0_pend" "0,1" newline bitfld.long 0x4 3. "IDF_W1_PEND,Interrupt Pending Status for idf_w1_pend" "0,1" bitfld.long 0x4 2. "IDF_W0_PEND,Interrupt Pending Status for idf_w0_pend" "0,1" bitfld.long 0x4 1. "ICF_W1_PEND,Interrupt Pending Status for icf_w1_pend" "0,1" bitfld.long 0x4 0. "ICF_W0_PEND,Interrupt Pending Status for icf_w0_pend" "0,1" rgroup.long 0x180++0x3 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 7. "ODF_W1_ENABLE_SET,Interrupt Enable Set Register for odf_w1_pend" "0,1" bitfld.long 0x0 6. "ODF_W0_ENABLE_SET,Interrupt Enable Set Register for odf_w0_pend" "0,1" bitfld.long 0x0 5. "OCF_W1_ENABLE_SET,Interrupt Enable Set Register for ocf_w1_pend" "0,1" bitfld.long 0x0 4. "OCF_W0_ENABLE_SET,Interrupt Enable Set Register for ocf_w0_pend" "0,1" newline bitfld.long 0x0 3. "IDF_W1_ENABLE_SET,Interrupt Enable Set Register for idf_w1_pend" "0,1" bitfld.long 0x0 2. "IDF_W0_ENABLE_SET,Interrupt Enable Set Register for idf_w0_pend" "0,1" bitfld.long 0x0 1. "ICF_W1_ENABLE_SET,Interrupt Enable Set Register for icf_w1_pend" "0,1" bitfld.long 0x0 0. "ICF_W0_ENABLE_SET,Interrupt Enable Set Register for icf_w0_pend" "0,1" rgroup.long 0x1C0++0x3 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 7. "ODF_W1_ENABLE_CLR,Interrupt Enable Clear Register for odf_w1_pend" "0,1" bitfld.long 0x0 6. "ODF_W0_ENABLE_CLR,Interrupt Enable Clear Register for odf_w0_pend" "0,1" bitfld.long 0x0 5. "OCF_W1_ENABLE_CLR,Interrupt Enable Clear Register for ocf_w1_pend" "0,1" bitfld.long 0x0 4. "OCF_W0_ENABLE_CLR,Interrupt Enable Clear Register for ocf_w0_pend" "0,1" newline bitfld.long 0x0 3. "IDF_W1_ENABLE_CLR,Interrupt Enable Clear Register for idf_w1_pend" "0,1" bitfld.long 0x0 2. "IDF_W0_ENABLE_CLR,Interrupt Enable Clear Register for idf_w0_pend" "0,1" bitfld.long 0x0 1. "ICF_W1_ENABLE_CLR,Interrupt Enable Clear Register for icf_w1_pend" "0,1" bitfld.long 0x0 0. "ICF_W0_ENABLE_CLR,Interrupt Enable Clear Register for icf_w0_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "WKUP" base ad:0x0 tree "WKUP_CBASS0" tree "WKUP_CBASS0_ERR (WKUP_CBASS0_ERR)" base ad:0x42400000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,EOI Register" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end tree "WKUP_CBASS0_GLB (WKUP_CBASS0_GLB)" base ad:0x45B02000 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x4++0x3 line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x20++0x3 line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." rgroup.long 0x40++0x7 line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree "WKUP_CBASS0_QOS (WKUP_CBASS0_QOS)" base ad:0x45D00000 rgroup.long 0x100++0x3 line.long 0x0 "QOS_REGS_Isms_wkup_0_tifs_vbusp_m_map0,The Map Register defines the fields for the master Isms_wkup_0.tifs_vbusp_m per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" rgroup.long 0x500++0x3 line.long 0x0 "QOS_REGS_Isms_wkup_0_hsm_vbusp_m_map0,The Map Register defines the fields for the master Isms_wkup_0.hsm_vbusp_m per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" tree.end tree.end tree "WKUP_CTRL_MMR0_CFG0 (WKUP_CTRL_MMR0_CFG0)" base ad:0x43000000 rgroup.long 0x0++0xB line.long 0x0 "CFG0_PID," hexmask.long.word 0x0 16.--31. 1. "PID_MSB16," newline hexmask.long.byte 0x0 11.--15. 1. "PID_MISC," newline bitfld.long 0x0 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "PID_CUSTOM," "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR," line.long 0x4 "CFG0_MMR_CFG0," hexmask.long.word 0x4 16.--31. 1. "MMR_CFG0_CFG_REV,Major configuration release" newline hexmask.long.word 0x4 0.--15. 1. "MMR_CFG0_SPEC_REV,Minor spec-only revision. Doesn't require new RTL release" line.long 0x8 "CFG0_MMR_CFG1," bitfld.long 0x8 31. "MMR_CFG1_PROXY_EN,Proxy addressing enabled" "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "MMR_CFG1_PARTITIONS,Indicates present partitions" rgroup.long 0x14++0x7 line.long 0x0 "CFG0_JTAGID," hexmask.long.byte 0x0 28.--31. 1. "JTAGID_VARIANT,Used to indicate new PGs" newline hexmask.long.word 0x0 12.--27. 1. "JTAGID_PARTNO,Part number for boundary scan" newline hexmask.long.word 0x0 1.--11. 1. "JTAGID_MFG,Indicates manufacturer" newline bitfld.long 0x0 0. "JTAGID_LSB,Always 1" "0,1" line.long 0x4 "CFG0_JTAG_USER_ID," hexmask.long 0x4 0.--31. 1. "JTAG_USER_ID_USERCODE,Device information" rgroup.long 0x20++0xF line.long 0x0 "CFG0_DIE_ID0," hexmask.long 0x0 0.--31. 1. "DIE_ID0_DIEID,Contains individual die information" line.long 0x4 "CFG0_DIE_ID1," hexmask.long 0x4 0.--31. 1. "DIE_ID1_DIEID,Contains individual die information" line.long 0x8 "CFG0_DIE_ID2," hexmask.long 0x8 0.--31. 1. "DIE_ID2_DIEID,Contains individual die information" line.long 0xC "CFG0_DIE_ID3," hexmask.long 0xC 0.--31. 1. "DIE_ID3_DIEID,Contains individual die information" rgroup.long 0x30++0x3 line.long 0x0 "CFG0_WKUP_DEVSTAT," hexmask.long.byte 0x0 16.--23. 1. "WKUP_DEVSTAT_MAIN_BOOTMODE,Specifies the device Primary and Backup boot media. Bit assignments defined by ROM" newline hexmask.long.word 0x0 0.--9. 1. "WKUP_DEVSTAT_MCU_BOOTMODE,Indicates MCU boot mode. Bits 9:8 - Power-on Self Test mode (if POST_SEL_STAT = 0x0) 00 - POST mode 1 (See POST_OPT_opt1_xxx bitfields) 01 - POST mode 2 (See POST_OPT_opt2_xxx bitfields) 10 - POST mode 3.." rgroup.long 0x34++0xB line.long 0x0 "CFG0_WKUP_BOOTCFG," hexmask.long.byte 0x0 16.--23. 1. "WKUP_BOOTCFG_MAIN_BOOTMODE,Specifies the device Primary and Backup boot media as latched at PORz Bit assignments assigned by ROM" newline hexmask.long.word 0x0 0.--9. 1. "WKUP_BOOTCFG_MCU_BOOTMODE,Indicates MCU boot mode as latched at power-on reset" line.long 0x4 "CFG0_POST_SEL_STAT," bitfld.long 0x4 0.--1. "POST_SEL_STAT_POST_SEL_STAT,Indicates which POST option was selected at power-up" "0,1,2,3" line.long 0x8 "CFG0_POST_OPT," bitfld.long 0x8 19. "POST_OPT_OPT3_MCU_PBIST_EN,MCU R5 PBIST enabled" "0,1" newline bitfld.long 0x8 18. "POST_OPT_OPT3_MCU_LBIST_EN,MCU R5 LBIST enabled" "0,1" newline bitfld.long 0x8 17. "POST_OPT_OPT3_SMS_LBIST_EN,SMS LBIST enabled" "0,1" newline bitfld.long 0x8 16. "POST_OPT_OPT3_PARALLEL_EN,Selects SMS/MCU R5 LBIST sequencing 0 - Serial (SMS LBIST performed first) 1 - Parallel" "0: Serial,1: Parallel" newline bitfld.long 0x8 11. "POST_OPT_OPT2_MCU_PBIST_EN,MCU R5 PBIST enabled" "0,1" newline bitfld.long 0x8 10. "POST_OPT_OPT2_MCU_LBIST_EN,MCU R5 LBIST enabled" "0,1" newline bitfld.long 0x8 9. "POST_OPT_OPT2_SMS_LBIST_EN,SMS LBIST enabled" "0,1" newline bitfld.long 0x8 8. "POST_OPT_OPT2_PARALLEL_EN,Selects SMS/MCU R5 LBIST sequencing 0 - Serial (SMS LBIST performed first) 1 - Parallel" "0: Serial,1: Parallel" newline bitfld.long 0x8 3. "POST_OPT_OPT1_MCU_PBIST_EN,MCU R5 PBIST enabled" "0,1" newline bitfld.long 0x8 2. "POST_OPT_OPT1_MCU_LBIST_EN,MCU R5 LBIST enabled" "0,1" newline bitfld.long 0x8 1. "POST_OPT_OPT1_SMS_LBIST_EN,SMS LBIST enabled" "0,1" newline bitfld.long 0x8 0. "POST_OPT_OPT1_PARALLEL_EN,Selects SMS/MCU R5 LBIST sequencing 0 - Serial (SMS LBIST performed first) 1 - Parallel" "0: Serial,1: Parallel" rgroup.long 0x44++0x3 line.long 0x0 "CFG0_BOOT_PROGRESS," hexmask.long 0x0 0.--31. 1. "BOOT_PROGRESS_PROGRESS,Written by ROM to indicate boot progression. Values and their meaning are determined by the ROM." rgroup.long 0x4C++0x3 line.long 0x0 "CFG0_ROM_INIT," hexmask.long.byte 0x0 0.--3. 1. "ROM_INIT_PLL_FRAC_INIT,Indicates whether to perform fractional PLL calibration as part of boot PLL initialization. 0xA - Perform PLL calibration 0xD - Reserved Others - No PLL calibration" rgroup.long 0x50++0x3 line.long 0x0 "CFG0_RESET_SRC_STAT," bitfld.long 0x0 24. "RESET_SRC_STAT_THERMAL_RST,When set indicates that a VTM Max Temp Thermal reset occurred. Write 1 to clear this bit." "0,1" newline bitfld.long 0x0 20. "RESET_SRC_STAT_DBUGSS_RST,When set indicates that a Debug reset occurred. Write 1 to clear this bit." "0,1" newline bitfld.long 0x0 19. "RESET_SRC_STAT_COLD_OUT_RST,When set indicates that a SMS Cold reset occurred. Write 1 to clear this bit." "0,1" newline bitfld.long 0x0 16. "RESET_SRC_STAT_WARM_OUT_RST,When set indicates that a SMS Warm reset occurred. Write 1 to clear this bit." "0,1" newline bitfld.long 0x0 11. "RESET_SRC_STAT_PORZ_PIN,When set indicates that a PORz pin reset occurred. Write 1 to clear this bit." "0,1" newline bitfld.long 0x0 9. "RESET_SRC_STAT_RESET_REQZ_PIN,When set indicates that a RESET_REQz pin reset occurred. Write 1 to clear this bit." "0,1" newline bitfld.long 0x0 8. "RESET_SRC_STAT_MCU_RSTZ_PIN,When set indicates that a MCU_RESETz pin reset occurred. Write 1 to clear this bit." "0,1" newline bitfld.long 0x0 3. "RESET_SRC_STAT_SW_MAIN_POR,When set indicates that a Software MAIN Power-on reset occurred. Write 1 to clear this bit." "0,1" newline bitfld.long 0x0 1. "RESET_SRC_STAT_SW_MAIN_WARMRST,When set indicates that a Software MAIN Warm reset occurred. Write 1 to clear this bit." "0,1" newline bitfld.long 0x0 0. "RESET_SRC_STAT_SW_MCU_WARMRST,When set indicates that a Software MCU Warm reset occurred. Write 1 to clear this bit." "0,1" rgroup.long 0x60++0x1F line.long 0x0 "CFG0_DEVICE_FEATURE0," bitfld.long 0x0 7. "DEVICE_FEATURE0_MPU_CLUSTER1_CORE3,MPU Cluster1 Core 3 is enabled when set" "0,1" newline bitfld.long 0x0 6. "DEVICE_FEATURE0_MPU_CLUSTER1_CORE2,MPU Cluster1 Core 2 is enabled when set" "0,1" newline bitfld.long 0x0 5. "DEVICE_FEATURE0_MPU_CLUSTER1_CORE1,MPU Cluster1 Core 1 is enabled when set" "0,1" newline bitfld.long 0x0 4. "DEVICE_FEATURE0_MPU_CLUSTER1_CORE0,MPU Cluster1 Core 0 is enabled when set" "0,1" newline bitfld.long 0x0 3. "DEVICE_FEATURE0_MPU_CLUSTER0_CORE3,MPU Cluster0 Core 3 is enabled when set" "0,1" newline bitfld.long 0x0 2. "DEVICE_FEATURE0_MPU_CLUSTER0_CORE2,MPU Cluster0 Core 2 is enabled when set" "0,1" newline bitfld.long 0x0 1. "DEVICE_FEATURE0_MPU_CLUSTER0_CORE1,MPU Cluster0 Core 1 is enabled when set" "0,1" newline bitfld.long 0x0 0. "DEVICE_FEATURE0_MPU_CLUSTER0_CORE0,MPU Cluster0 Core 0 is enabled when set" "0,1" line.long 0x4 "CFG0_DEVICE_FEATURE1," bitfld.long 0x4 19. "DEVICE_FEATURE1_C71_CORE3,C71 Core3 is enabled when set" "0,1" newline bitfld.long 0x4 18. "DEVICE_FEATURE1_C71_CORE2,C71 Core2 is enabled when set" "0,1" newline bitfld.long 0x4 17. "DEVICE_FEATURE1_C71_CORE1,C71 Core1 is enabled when set" "0,1" newline bitfld.long 0x4 16. "DEVICE_FEATURE1_C71_CORE0,C71 Core0 is enabled when set" "0,1" newline bitfld.long 0x4 13. "DEVICE_FEATURE1_GPU_1,GPU1 is enabled when set" "0,1" newline bitfld.long 0x4 12. "DEVICE_FEATURE1_GPU,GPU is enabled when set" "0,1" newline bitfld.long 0x4 5. "DEVICE_FEATURE1_MCU_CLUSTER2_CORE1,MAIN MCU Cluster2 Core1 is enabled when set" "0,1" newline bitfld.long 0x4 4. "DEVICE_FEATURE1_MCU_CLUSTER2_CORE0,MAIN MCU Cluster2 Core0 is enabled when set" "0,1" newline bitfld.long 0x4 3. "DEVICE_FEATURE1_MCU_CLUSTER1_CORE1,MAIN MCU Cluster1 Core1 is enabled when set" "0,1" newline bitfld.long 0x4 2. "DEVICE_FEATURE1_MCU_CLUSTER1_CORE0,MAIN MCU Cluster1 Core0 is enabled when set" "0,1" newline bitfld.long 0x4 1. "DEVICE_FEATURE1_MCU_CLUSTER0_CORE1,MAIN MCU Cluster0 Core1 is enabled when set" "0,1" newline bitfld.long 0x4 0. "DEVICE_FEATURE1_MCU_CLUSTER0_CORE0,MAIN MCU Cluster0 Core0 is enabled when set" "0,1" line.long 0x8 "CFG0_DEVICE_FEATURE2," bitfld.long 0x8 17. "DEVICE_FEATURE2_SPARE1,WKUP_Spare1 LPSC is enabled when set" "0,1" newline bitfld.long 0x8 16. "DEVICE_FEATURE2_SPARE0,WKUP_Spare0 LPSC is enabled when set" "0,1" newline bitfld.long 0x8 12. "DEVICE_FEATURE2_ADC1,MCU ADC1 is enabled when set" "0,1" newline bitfld.long 0x8 11. "DEVICE_FEATURE2_CRYPTO_SM34_EN,MCU SA3_UL Crypto Module SM3/SM4 enabled" "0,1" newline bitfld.long 0x8 10. "DEVICE_FEATURE2_CRYPTO_PKA_EN,MCU SA2_UL Crypto Module PKA enabled" "0,1" newline bitfld.long 0x8 9. "DEVICE_FEATURE2_CRYPTO_ENCR_EN,MCU SA2_UL Crypto Module AES/3DES/DBRG enabled" "0,1" newline bitfld.long 0x8 8. "DEVICE_FEATURE2_CRYPTO_SHA_EN,MCU SA2_UL Crypto Module SHA/MD5 enabled" "0,1" newline bitfld.long 0x8 7. "DEVICE_FEATURE2_AES_AUTH_EN,AES authentication is enabled in MCU_FlashSS and SMS when set" "0,1" newline bitfld.long 0x8 6. "DEVICE_FEATURE2_HYPERBUS,MCU_Hyperbus is enabled when set" "0,1" newline bitfld.long 0x8 5. "DEVICE_FEATURE2_OSPI1,MCU_OSPI1 is enabled when set" "0,1" newline bitfld.long 0x8 4. "DEVICE_FEATURE2_OSPI0,MCU_OSPI0 is enabled when set" "0,1" newline bitfld.long 0x8 3. "DEVICE_FEATURE2_MCU_MCAN1,MCU_MCAN1 is enabled when set" "0,1" newline bitfld.long 0x8 1. "DEVICE_FEATURE2_MCU_MCAN0,MCU_MCAN0 is enabled when set" "0,1" newline bitfld.long 0x8 0. "DEVICE_FEATURE2_MCU_MCAN_FD_MODE,FD mode is supported on MCU_MCAN[1:0] when set" "0,1" line.long 0xC "CFG0_DEVICE_FEATURE3," bitfld.long 0xC 31. "DEVICE_FEATURE3_EMIF3,EMIF3 is enabled when set" "0,1" newline bitfld.long 0xC 30. "DEVICE_FEATURE3_EMIF2,EMIF2 is enabled when set" "0,1" newline bitfld.long 0xC 29. "DEVICE_FEATURE3_EMIF1,EMIF1 is enabled when set" "0,1" newline bitfld.long 0xC 28. "DEVICE_FEATURE3_EMIF0,EMIF0 is enabled when set" "0,1" newline bitfld.long 0xC 22. "DEVICE_FEATURE3_MMC_4B1,4-bit MMC/SD02 is enabled when set" "0,1" newline bitfld.long 0xC 21. "DEVICE_FEATURE3_MMC_4B0,4-bit MMC/SD1 is enabled when set" "0,1" newline bitfld.long 0xC 20. "DEVICE_FEATURE3_MMC_8B,8-bit MMC/SD0 is enabled when set" "0,1" newline bitfld.long 0xC 19. "DEVICE_FEATURE3_HYPERLINK,Hyperlink interface is enabled when set" "0,1" newline bitfld.long 0xC 12. "DEVICE_FEATURE3_SERDES4,Serdes4 is enabled when set" "0,1" newline bitfld.long 0xC 11. "DEVICE_FEATURE3_SERDES3,Serdes3 is enabled when set" "0,1" newline bitfld.long 0xC 10. "DEVICE_FEATURE3_SERDES2,Serdes2 is enabled when set" "0,1" newline bitfld.long 0xC 9. "DEVICE_FEATURE3_SERDES1,Serdes1 is enabled when set" "0,1" newline bitfld.long 0xC 8. "DEVICE_FEATURE3_SERDES0,Serdes0 is enabled when set" "0,1" newline bitfld.long 0xC 7. "DEVICE_FEATURE3_PCIE3,PCIe3 is enabled when set" "0,1" newline bitfld.long 0xC 6. "DEVICE_FEATURE3_PCIE2,PCIe2 is enabled when set" "0,1" newline bitfld.long 0xC 5. "DEVICE_FEATURE3_PCIE1,PCIe1 is enabled when set" "0,1" newline bitfld.long 0xC 4. "DEVICE_FEATURE3_PCIE0,PCIe0 is enabled when set" "0,1" newline bitfld.long 0xC 0. "DEVICE_FEATURE3_USB0,USB0 is enabled when set" "0,1" line.long 0x10 "CFG0_DEVICE_FEATURE4," bitfld.long 0x10 27. "DEVICE_FEATURE4_VID_CODEC1,Video encoder/decoder 1 is enabled when set" "0,1" newline bitfld.long 0x10 26. "DEVICE_FEATURE4_VID_CODEC0,Video encoder/decoder 0 is enabled when set" "0,1" newline bitfld.long 0x10 25. "DEVICE_FEATURE4_DECODER,Video decoder is enabled when set" "0,1" newline bitfld.long 0x10 24. "DEVICE_FEATURE4_ENCODER0,Video encoder 0 is enabled when set" "0,1" newline bitfld.long 0x10 19. "DEVICE_FEATURE4_VPAC1,VPAC1 is enabled when set" "0,1" newline bitfld.long 0x10 18. "DEVICE_FEATURE4_VPAC0,VPAC0 is enabled when set" "0,1" newline bitfld.long 0x10 17. "DEVICE_FEATURE4_SDE,DMPAC Stereo Disparity Engine is enabled when set" "0,1" newline bitfld.long 0x10 16. "DEVICE_FEATURE4_DMPAC,DMPAC is enabled when set" "0,1" newline bitfld.long 0x10 12. "DEVICE_FEATURE4_EDP0,Embedded display port 0 is enabled when set" "0,1" newline bitfld.long 0x10 9. "DEVICE_FEATURE4_CSITX1,CSI_TX1 is enabled when set" "0,1" newline bitfld.long 0x10 8. "DEVICE_FEATURE4_CSITX0,CSI_TX0 is enabled when set" "0,1" newline bitfld.long 0x10 6. "DEVICE_FEATURE4_CSIRX2,CSI_RX2 is enabled when set" "0,1" newline bitfld.long 0x10 5. "DEVICE_FEATURE4_CSIRX1,CSI_RX1 is enabled when set" "0,1" newline bitfld.long 0x10 4. "DEVICE_FEATURE4_CSIRX0,CSI_RX0 is enabled when set" "0,1" newline bitfld.long 0x10 3. "DEVICE_FEATURE4_DSI1,DSI1 is enabled when set" "0,1" newline bitfld.long 0x10 2. "DEVICE_FEATURE4_DSI0,DSI0 is enabled when set" "0,1" newline bitfld.long 0x10 0. "DEVICE_FEATURE4_DSS,DSS is enabled when set" "0,1" line.long 0x14 "CFG0_DEVICE_FEATURE5," bitfld.long 0x14 17. "DEVICE_FEATURE5_MCAN17,MCAN17 is enabled when set" "0,1" newline bitfld.long 0x14 16. "DEVICE_FEATURE5_MCAN16,MCAN16 is enabled when set" "0,1" newline bitfld.long 0x14 15. "DEVICE_FEATURE5_MCAN15,MCAN15 is enabled when set" "0,1" newline bitfld.long 0x14 14. "DEVICE_FEATURE5_MCAN14,MCAN14 is enabled when set" "0,1" newline bitfld.long 0x14 13. "DEVICE_FEATURE5_MCAN13,MCAN13 is enabled when set" "0,1" newline bitfld.long 0x14 12. "DEVICE_FEATURE5_MCAN12,MCAN12 is enabled when set" "0,1" newline bitfld.long 0x14 11. "DEVICE_FEATURE5_MCAN11,MCAN11 is enabled when set" "0,1" newline bitfld.long 0x14 10. "DEVICE_FEATURE5_MCAN10,MCAN10 is enabled when set" "0,1" newline bitfld.long 0x14 9. "DEVICE_FEATURE5_MCAN9,MCAN9 is enabled when set" "0,1" newline bitfld.long 0x14 8. "DEVICE_FEATURE5_MCAN8,MCAN8 is enabled when set" "0,1" newline bitfld.long 0x14 7. "DEVICE_FEATURE5_MCAN7,MCAN7 is enabled when set" "0,1" newline bitfld.long 0x14 6. "DEVICE_FEATURE5_MCAN6,MCAN6 is enabled when set" "0,1" newline bitfld.long 0x14 5. "DEVICE_FEATURE5_MCAN5,MCAN5 is enabled when set" "0,1" newline bitfld.long 0x14 4. "DEVICE_FEATURE5_MCAN4,MCAN4 is enabled when set" "0,1" newline bitfld.long 0x14 3. "DEVICE_FEATURE5_MCAN3,MCAN3 is enabled when set" "0,1" newline bitfld.long 0x14 2. "DEVICE_FEATURE5_MCAN2,MCAN2 is enabled when set" "0,1" newline bitfld.long 0x14 1. "DEVICE_FEATURE5_MCAN1,MCAN1 is enabled when set" "0,1" newline bitfld.long 0x14 0. "DEVICE_FEATURE5_MCAN0,MCAN0 is enabled when set" "0,1" line.long 0x18 "CFG0_DEVICE_FEATURE6," bitfld.long 0x18 26. "DEVICE_FEATURE6_SPARE6,Spare6 LPSC is enabled when set" "0,1" newline bitfld.long 0x18 25. "DEVICE_FEATURE6_SPARE5,Spare5 LPSC is enabled when set" "0,1" newline bitfld.long 0x18 24. "DEVICE_FEATURE6_SPARE4,Spare4 LPSC is enabled when set" "0,1" newline bitfld.long 0x18 22. "DEVICE_FEATURE6_PER_SPARE2,PER Spare2 LPSC is enabled when set" "0,1" newline bitfld.long 0x18 21. "DEVICE_FEATURE6_PER_SPARE1,PER Spare1 LPSC is enabled when set" "0,1" newline bitfld.long 0x18 20. "DEVICE_FEATURE6_PER_SPARE0,PER Spare0 LPSC is enabled when set" "0,1" newline bitfld.long 0x18 9. "DEVICE_FEATURE6_I3C,MAIN domain I3C is enabled when set" "0,1" newline bitfld.long 0x18 8. "DEVICE_FEATURE6_MOTOR_PER,Motor control peripherals (eCAP eQEP eHRPWM) are enabled when set" "0,1" newline bitfld.long 0x18 7. "DEVICE_FEATURE6_ATL,Audio tracking logic is enabled when set" "0,1" newline bitfld.long 0x18 5. "DEVICE_FEATURE6_SA2_UL,MAIN domain security accelerator is enabled when set" "0,1" newline bitfld.long 0x18 4. "DEVICE_FEATURE6_CPSW5,4 Channel Q/SGMII Ethernet switch enabled when set" "0,1" newline bitfld.long 0x18 3. "DEVICE_FEATURE6_CPSW2,1 Channel Ethernet switch enabled when set" "0,1" newline bitfld.long 0x18 0. "DEVICE_FEATURE6_UFS0,UFS interface 0 is enabled when set" "0,1" line.long 0x1C "CFG0_DEVICE_FEATURE7," bitfld.long 0x1C 23. "DEVICE_FEATURE7_BSPARE_PD7_3,Bolt-on bspare_pda7_3 LPSC is enabled when set" "0,1" newline bitfld.long 0x1C 22. "DEVICE_FEATURE7_BSPARE_PD7_2,Not used" "0,1" newline bitfld.long 0x1C 21. "DEVICE_FEATURE7_ANA_3_DRU,Analytics 3 DRU is enabled when set" "0,1" newline bitfld.long 0x1C 20. "DEVICE_FEATURE7_ANA_3,Analytics 3 block is enabled when set" "0,1" newline bitfld.long 0x1C 19. "DEVICE_FEATURE7_ANA_2_DRU,Analytics 2 DRU is enabled when set" "0,1" newline bitfld.long 0x1C 18. "DEVICE_FEATURE7_ANA_2,Analytics 2 block is enabled when set" "0,1" newline bitfld.long 0x1C 17. "DEVICE_FEATURE7_ANA_1_DRU,Analytics 1 DRU is enabled when set" "0,1" newline bitfld.long 0x1C 16. "DEVICE_FEATURE7_ANA_1,Analytics 1 block is enabled when set" "0,1" newline bitfld.long 0x1C 15. "DEVICE_FEATURE7_ANA_0_DRU,Analytics 0 DRU is enabled when set" "0,1" newline bitfld.long 0x1C 14. "DEVICE_FEATURE7_ANA_0,Analytics 0 block is enabled when set" "0,1" newline bitfld.long 0x1C 11. "DEVICE_FEATURE7_BSPARE_PD2_1,Bolt-on bspare_pda2_1 LPSC is enabled when set" "0,1" newline bitfld.long 0x1C 7. "DEVICE_FEATURE7_BSPARE_AON7,Bolt-on bspare_pdaon_7 LPSC is enabled when set" "0,1" newline bitfld.long 0x1C 6. "DEVICE_FEATURE7_BSPARE_AON6,Bolt-on bspare_pdaon_6 LPSC is enabled when set" "0,1" newline bitfld.long 0x1C 5. "DEVICE_FEATURE7_BSPARE_AON5,Bolt-on bspare_pdaon_5 LPSC is enabled when set" "0,1" newline bitfld.long 0x1C 4. "DEVICE_FEATURE7_BSPARE_AON4,Bolt-on bspare_pdaon_4 LPSC is enabled when set" "0,1" newline bitfld.long 0x1C 3. "DEVICE_FEATURE7_BSPARE_AON3,Bolt-on bspare_pdaon_3 LPSC is enabled when set" "0,1" newline bitfld.long 0x1C 2. "DEVICE_FEATURE7_BSPARE_AON2,Bolt-on bspare_pdaon_2 LPSC is enabled when set" "0,1" newline bitfld.long 0x1C 1. "DEVICE_FEATURE7_BSPARE_AON1,Bolt-on bspare_pdaon_1 LPSC is enabled when set" "0,1" newline bitfld.long 0x1C 0. "DEVICE_FEATURE7_BSPARE_AON0,Bolt-on bspare_pdaon_0 LPSC is enabled when set" "0,1" rgroup.long 0x200++0xB line.long 0x0 "CFG0_DBG_CBA_ERR_STAT," bitfld.long 0x0 1. "DBG_CBA_ERR_STAT_MAIN_DBG_ERR,Main Debug bus segment error" "0,1" line.long 0x4 "CFG0_FW_CBA_ERR_STAT," bitfld.long 0x4 2. "FW_CBA_ERR_STAT_MAIN_FW_ERR,MAIN Firewall bus segment error" "0,1" newline bitfld.long 0x4 1. "FW_CBA_ERR_STAT_MCU_FW_ERR,MCU Firewall bus segment error" "0,1" newline bitfld.long 0x4 0. "FW_CBA_ERR_STAT_WKUP_FW_ERR,WKUP Firewall bus segment error" "0,1" line.long 0x8 "CFG0_NONFW_CBA_ERR_STAT," bitfld.long 0x8 5. "NONFW_CBA_ERR_STAT_MAIN_INFRA_NS_CBA_ERR,MAIN Infrastructure non-safe bus segment error" "0,1" newline bitfld.long 0x8 4. "NONFW_CBA_ERR_STAT_DBG_CBA_ERR,Debug bus aggregated error. See DBG_CBA_ERR_STAT for specific segment information." "0,1" newline bitfld.long 0x8 3. "NONFW_CBA_ERR_STAT_WKUP_CBA_ERR,WKUP Data bus segment error" "0,1" newline bitfld.long 0x8 2. "NONFW_CBA_ERR_STAT_MCU_CBA_ERR,MCU Data bus segment error" "0,1" newline bitfld.long 0x8 1. "NONFW_CBA_ERR_STAT_MAIN_INFRA_CBA_ERR,MAIN Infrastructure safe bus segment error" "0,1" newline bitfld.long 0x8 0. "NONFW_CBA_ERR_STAT_MAIN_CBA_ERR,MAIN Data bus aggregated error. See MAIN_CBA_ERR_STAT for specific segment information" "0,1" rgroup.long 0x210++0x3 line.long 0x0 "CFG0_MAIN_CBA_ERR_STAT," bitfld.long 0x0 18. "MAIN_CBA_ERR_STAT_PULSAR1_MEM_CBA_ERR,MAIN R5 Cluster 1 Memory Data bus segment error" "0,1" newline bitfld.long 0x0 17. "MAIN_CBA_ERR_STAT_PULSAR0_SLV_CBA_ERR,MAIN R5 Cluster 0 Slave Data bus segment error" "0,1" newline bitfld.long 0x0 16. "MAIN_CBA_ERR_STAT_PULSAR0_MEM_CBA_ERR,MAIN R5 Cluster 0 Memory Data bus segment error" "0,1" newline bitfld.long 0x0 13. "MAIN_CBA_ERR_STAT_IPPHY_SAFE_CBA_ERR,MAIN Phy safe Data bus segment error" "0,1" newline bitfld.long 0x0 10. "MAIN_CBA_ERR_STAT_IPPHY_CBA_ERR,MAIN Phy non-safe Data bus segment error" "0,1" newline bitfld.long 0x0 9. "MAIN_CBA_ERR_STAT_CSI_CBA_ERR,MAIN CSI Data bus segment error" "0,1" newline bitfld.long 0x0 7. "MAIN_CBA_ERR_STAT_DEBUG_CBA_ERR,MAIN Debug Data bus segment error" "0,1" newline bitfld.long 0x0 6. "MAIN_CBA_ERR_STAT_HC2_CBA_ERR,MAIN HC2 Data bus segment error" "0,1" newline bitfld.long 0x0 5. "MAIN_CBA_ERR_STAT_HC_CFG_CBA_ERR,MAIN HC CFG Data bus segment error" "0,1" newline bitfld.long 0x0 4. "MAIN_CBA_ERR_STAT_AC_CFG_NS_CBA_ERR,MAIN AC non-safe CFG Data bus segment error" "0,1" newline bitfld.long 0x0 3. "MAIN_CBA_ERR_STAT_RC_CFG_CBA_ERR,MAIN RC CFG Data bus segment error" "0,1" newline bitfld.long 0x0 2. "MAIN_CBA_ERR_STAT_RC_CBA_ERR,MAIN RC Data bus segment error" "0,1" newline bitfld.long 0x0 1. "MAIN_CBA_ERR_STAT_AC_CFG_CBA_ERR,MAIN AC CFG Data bus segment error" "0,1" newline bitfld.long 0x0 0. "MAIN_CBA_ERR_STAT_AC_CBA_ERR,MAIN AC Data bus segment error" "0,1" rgroup.long 0x300++0xF line.long 0x0 "CFG0_WKUP_SPARE_FUSE0," hexmask.long 0x0 0.--31. 1. "WKUP_SPARE_FUSE0_FUSE_VAL,Fuse value" line.long 0x4 "CFG0_WKUP_SPARE_FUSE1," hexmask.long 0x4 0.--31. 1. "WKUP_SPARE_FUSE1_FUSE_VAL,Fuse value" line.long 0x8 "CFG0_WKUP_SPARE_FUSE2," hexmask.long 0x8 0.--31. 1. "WKUP_SPARE_FUSE2_FUSE_VAL,Fuse value" line.long 0xC "CFG0_WKUP_SPARE_FUSE3," hexmask.long 0xC 0.--31. 1. "WKUP_SPARE_FUSE3_FUSE_VAL,Fuse value" rgroup.long 0x350++0x7 line.long 0x0 "CFG0_SPARE_PLL0_CAL," hexmask.long.word 0x0 0.--11. 1. "SPARE_PLL0_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL0_cal_in to begin the PLL calibration sequence." line.long 0x4 "CFG0_SPARE_PLL1_CAL," hexmask.long.word 0x4 0.--11. 1. "SPARE_PLL1_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL1_cal_in to begin the PLL calibration sequence." rgroup.long 0x360++0xB line.long 0x0 "CFG0_MCU_PLL0_CAL," hexmask.long.word 0x0 0.--11. 1. "MCU_PLL0_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL0_cal_in to begin the PLL calibration sequence." line.long 0x4 "CFG0_MCU_PLL1_CAL," hexmask.long.word 0x4 0.--11. 1. "MCU_PLL1_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL1_cal_in to begin the PLL calibration sequence." line.long 0x8 "CFG0_MCU_PLL2_CAL," hexmask.long.word 0x8 0.--11. 1. "MCU_PLL2_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL2_cal_in to begin the PLL calibration sequence." rgroup.long 0x380++0x27 line.long 0x0 "CFG0_MAIN_PLL0_CAL," hexmask.long.word 0x0 0.--11. 1. "MAIN_PLL0_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL0_cal_in to begin the PLL calibration sequence." line.long 0x4 "CFG0_MAIN_PLL1_CAL," hexmask.long.word 0x4 0.--11. 1. "MAIN_PLL1_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL1_cal_in to begin the PLL calibration sequence." line.long 0x8 "CFG0_MAIN_PLL2_CAL," hexmask.long.word 0x8 0.--11. 1. "MAIN_PLL2_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL2_cal_in to begin the PLL calibration sequence." line.long 0xC "CFG0_MAIN_PLL3_CAL," hexmask.long.word 0xC 0.--11. 1. "MAIN_PLL3_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL3_cal_in to begin the PLL calibration sequence." line.long 0x10 "CFG0_MAIN_PLL4_CAL," hexmask.long.word 0x10 0.--11. 1. "MAIN_PLL4_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL4_cal_in to begin the PLL calibration sequence." line.long 0x14 "CFG0_MAIN_PLL5_CAL," hexmask.long.word 0x14 0.--11. 1. "MAIN_PLL5_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL5_cal_in to begin the PLL calibration sequence." line.long 0x18 "CFG0_MAIN_PLL6_CAL," hexmask.long.word 0x18 0.--11. 1. "MAIN_PLL6_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL6_cal_in to begin the PLL calibration sequence." line.long 0x1C "CFG0_MAIN_PLL7_CAL," hexmask.long.word 0x1C 0.--11. 1. "MAIN_PLL7_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL7_cal_in to begin the PLL calibration sequence." line.long 0x20 "CFG0_MAIN_PLL8_CAL," hexmask.long.word 0x20 0.--11. 1. "MAIN_PLL8_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL8_cal_in to begin the PLL calibration sequence." line.long 0x24 "CFG0_MAIN_PLL9_CAL," hexmask.long.word 0x24 0.--11. 1. "MAIN_PLL9_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL9_cal_in to begin the PLL calibration sequence." rgroup.long 0x3B0++0x3 line.long 0x0 "CFG0_MAIN_PLL12_CAL," hexmask.long.word 0x0 0.--11. 1. "MAIN_PLL12_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL12_cal_in to begin the PLL calibration sequence." rgroup.long 0x3B8++0x3 line.long 0x0 "CFG0_MAIN_PLL14_CAL," hexmask.long.word 0x0 0.--11. 1. "MAIN_PLL14_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL14_cal_in to begin the PLL calibration sequence." rgroup.long 0x3C0++0x7 line.long 0x0 "CFG0_MAIN_PLL16_CAL," hexmask.long.word 0x0 0.--11. 1. "MAIN_PLL16_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL16_cal_in to begin the PLL calibration sequence." line.long 0x4 "CFG0_MAIN_PLL17_CAL," hexmask.long.word 0x4 0.--11. 1. "MAIN_PLL17_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL17_cal_in to begin the PLL calibration sequence." rgroup.long 0x3CC++0x3 line.long 0x0 "CFG0_MAIN_PLL19_CAL," hexmask.long.word 0x0 0.--11. 1. "MAIN_PLL19_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL19_cal_in to begin the PLL calibration sequence." rgroup.long 0x3E4++0xF line.long 0x0 "CFG0_MAIN_PLL25_CAL," hexmask.long.word 0x0 0.--11. 1. "MAIN_PLL25_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL25_cal_in to begin the PLL calibration sequence." line.long 0x4 "CFG0_MAIN_PLL26_CAL," hexmask.long.word 0x4 0.--11. 1. "MAIN_PLL26_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL26_cal_in to begin the PLL calibration sequence." line.long 0x8 "CFG0_MAIN_PLL27_CAL," hexmask.long.word 0x8 0.--11. 1. "MAIN_PLL27_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL27_cal_in to begin the PLL calibration sequence." line.long 0xC "CFG0_MAIN_PLL28_CAL," hexmask.long.word 0xC 0.--11. 1. "MAIN_PLL28_CAL_DEF_CAL_VAL,PLL Initial calibration value This value can be used as the initial value written to PLL28_cal_in to begin the PLL calibration sequence." rgroup.long 0x1008++0x1B line.long 0x0 "CFG0_LOCK0_KICK0," hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK0_KICK1," hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1,- KICK1 component" line.long 0x8 "CFG0_intr_raw_status," bitfld.long 0x8 3. "PROXY_ERR,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 2. "KICK_ERR,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 1. "ADDR_ERR,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0xC "CFG0_intr_enabled_status_clear," bitfld.long 0xC 3. "ENABLED_PROXY_ERR,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 2. "ENABLED_KICK_ERR,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x10 "CFG0_intr_enable," bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0x14 "CFG0_intr_enable_clear," bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x18 "CFG0_eoi," hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x1024++0xB line.long 0x0 "CFG0_fault_address," hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault Address." line.long 0x4 "CFG0_fault_type_status," bitfld.long 0x4 6. "FAULT_NS,Non-secure access." "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir.." line.long 0x8 "CFG0_fault_attr_status," hexmask.long.word 0x8 20.--31. 1. "FAULT_XID,XID." newline hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID,Route ID." newline hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID,Privilege ID." rgroup.long 0x1030++0x3 line.long 0x0 "CFG0_fault_clear," bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" rgroup.long 0x1100++0x1F line.long 0x0 "CFG0_CLAIMREG_P0_R0_READONLY," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P0_R0_READONLY,Claim bits for Partition 0" line.long 0x4 "CFG0_CLAIMREG_P0_R1_READONLY," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P0_R1_READONLY,Claim bits for Partition 0" line.long 0x8 "CFG0_CLAIMREG_P0_R2_READONLY," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P0_R2_READONLY,Claim bits for Partition 0" line.long 0xC "CFG0_CLAIMREG_P0_R3_READONLY," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P0_R3_READONLY,Claim bits for Partition 0" line.long 0x10 "CFG0_CLAIMREG_P0_R4_READONLY," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P0_R4_READONLY,Claim bits for Partition 0" line.long 0x14 "CFG0_CLAIMREG_P0_R5_READONLY," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P0_R5_READONLY,Claim bits for Partition 0" line.long 0x18 "CFG0_CLAIMREG_P0_R6_READONLY," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P0_R6_READONLY,Claim bits for Partition 0" line.long 0x1C "CFG0_CLAIMREG_P0_R7_READONLY," hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P0_R7_READONLY,Claim bits for Partition 0" rgroup.long 0x2000++0xB line.long 0x0 "CFG0_PID_PROXY," hexmask.long.word 0x0 16.--31. 1. "PID_MSB16_PROXY," newline hexmask.long.byte 0x0 11.--15. 1. "PID_MISC_PROXY," newline bitfld.long 0x0 8.--10. "PID_MAJOR_PROXY," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "PID_CUSTOM_PROXY," "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR_PROXY," line.long 0x4 "CFG0_MMR_CFG0_PROXY," hexmask.long.word 0x4 16.--31. 1. "MMR_CFG0_CFG_REV_PROXY,Major configuration release" newline hexmask.long.word 0x4 0.--15. 1. "MMR_CFG0_SPEC_REV_PROXY,Minor spec-only revision. Doesn't require new RTL release" line.long 0x8 "CFG0_MMR_CFG1_PROXY," bitfld.long 0x8 31. "MMR_CFG1_PROXY_EN_PROXY,Proxy addressing enabled" "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "MMR_CFG1_PARTITIONS_PROXY,Indicates present partitions" rgroup.long 0x2014++0x7 line.long 0x0 "CFG0_JTAGID_PROXY," hexmask.long.byte 0x0 28.--31. 1. "JTAGID_VARIANT_PROXY,Used to indicate new PGs" newline hexmask.long.word 0x0 12.--27. 1. "JTAGID_PARTNO_PROXY,Part number for boundary scan" newline hexmask.long.word 0x0 1.--11. 1. "JTAGID_MFG_PROXY,Indicates manufacturer" newline bitfld.long 0x0 0. "JTAGID_LSB_PROXY,Always 1" "0,1" line.long 0x4 "CFG0_JTAG_USER_ID_PROXY," hexmask.long 0x4 0.--31. 1. "JTAG_USER_ID_USERCODE_PROXY,Device information" rgroup.long 0x2020++0xF line.long 0x0 "CFG0_DIE_ID0_PROXY," hexmask.long 0x0 0.--31. 1. "DIE_ID0_DIEID_PROXY,Contains individual die information" line.long 0x4 "CFG0_DIE_ID1_PROXY," hexmask.long 0x4 0.--31. 1. "DIE_ID1_DIEID_PROXY,Contains individual die information" line.long 0x8 "CFG0_DIE_ID2_PROXY," hexmask.long 0x8 0.--31. 1. "DIE_ID2_DIEID_PROXY,Contains individual die information" line.long 0xC "CFG0_DIE_ID3_PROXY," hexmask.long 0xC 0.--31. 1. "DIE_ID3_DIEID_PROXY,Contains individual die information" rgroup.long 0x2030++0x3 line.long 0x0 "CFG0_WKUP_DEVSTAT_PROXY," hexmask.long.byte 0x0 16.--23. 1. "WKUP_DEVSTAT_MAIN_BOOTMODE_PROXY,Specifies the device Primary and Backup boot media. Bit assignments defined by ROM" newline hexmask.long.word 0x0 0.--9. 1. "WKUP_DEVSTAT_MCU_BOOTMODE_PROXY,Indicates MCU boot mode. Bits 9:8 - Power-on Self Test mode (if POST_SEL_STAT = 0x0) 00 - POST mode 1 (See POST_OPT_opt1_xxx bitfields) 01 - POST mode 2 (See POST_OPT_opt2_xxx bitfields) 10 - POST.." rgroup.long 0x2034++0xB line.long 0x0 "CFG0_WKUP_BOOTCFG_PROXY," hexmask.long.byte 0x0 16.--23. 1. "WKUP_BOOTCFG_MAIN_BOOTMODE_PROXY,Specifies the device Primary and Backup boot media as latched at PORz Bit assignments assigned by ROM" newline hexmask.long.word 0x0 0.--9. 1. "WKUP_BOOTCFG_MCU_BOOTMODE_PROXY,Indicates MCU boot mode as latched at power-on reset" line.long 0x4 "CFG0_POST_SEL_STAT_PROXY," bitfld.long 0x4 0.--1. "POST_SEL_STAT_POST_SEL_STAT_PROXY,Indicates which POST option was selected at power-up" "0,1,2,3" line.long 0x8 "CFG0_POST_OPT_PROXY," bitfld.long 0x8 19. "POST_OPT_OPT3_MCU_PBIST_EN_PROXY,MCU R5 PBIST enabled" "0,1" newline bitfld.long 0x8 18. "POST_OPT_OPT3_MCU_LBIST_EN_PROXY,MCU R5 LBIST enabled" "0,1" newline bitfld.long 0x8 17. "POST_OPT_OPT3_SMS_LBIST_EN_PROXY,SMS LBIST enabled" "0,1" newline bitfld.long 0x8 16. "POST_OPT_OPT3_PARALLEL_EN_PROXY,Selects SMS/MCU R5 LBIST sequencing 0 - Serial (SMS LBIST performed first) 1 - Parallel" "0: Serial,1: Parallel" newline bitfld.long 0x8 11. "POST_OPT_OPT2_MCU_PBIST_EN_PROXY,MCU R5 PBIST enabled" "0,1" newline bitfld.long 0x8 10. "POST_OPT_OPT2_MCU_LBIST_EN_PROXY,MCU R5 LBIST enabled" "0,1" newline bitfld.long 0x8 9. "POST_OPT_OPT2_SMS_LBIST_EN_PROXY,SMS LBIST enabled" "0,1" newline bitfld.long 0x8 8. "POST_OPT_OPT2_PARALLEL_EN_PROXY,Selects SMS/MCU R5 LBIST sequencing 0 - Serial (SMS LBIST performed first) 1 - Parallel" "0: Serial,1: Parallel" newline bitfld.long 0x8 3. "POST_OPT_OPT1_MCU_PBIST_EN_PROXY,MCU R5 PBIST enabled" "0,1" newline bitfld.long 0x8 2. "POST_OPT_OPT1_MCU_LBIST_EN_PROXY,MCU R5 LBIST enabled" "0,1" newline bitfld.long 0x8 1. "POST_OPT_OPT1_SMS_LBIST_EN_PROXY,SMS LBIST enabled" "0,1" newline bitfld.long 0x8 0. "POST_OPT_OPT1_PARALLEL_EN_PROXY,Selects SMS/MCU R5 LBIST sequencing 0 - Serial (SMS LBIST performed first) 1 - Parallel" "0: Serial,1: Parallel" rgroup.long 0x2044++0x3 line.long 0x0 "CFG0_BOOT_PROGRESS_PROXY," hexmask.long 0x0 0.--31. 1. "BOOT_PROGRESS_PROGRESS_PROXY,Written by ROM to indicate boot progression. Values and their meaning are determined by the ROM." rgroup.long 0x204C++0x3 line.long 0x0 "CFG0_ROM_INIT_PROXY," hexmask.long.byte 0x0 0.--3. 1. "ROM_INIT_PLL_FRAC_INIT_PROXY,Indicates whether to perform fractional PLL calibration as part of boot PLL initialization. 0xA - Perform PLL calibration 0xD - Reserved Others - No PLL calibration" rgroup.long 0x2050++0x3 line.long 0x0 "CFG0_RESET_SRC_STAT_PROXY," bitfld.long 0x0 24. "RESET_SRC_STAT_THERMAL_RST_PROXY,When set indicates that a VTM Max Temp Thermal reset occurred. Write 1 to clear this bit." "0,1" newline bitfld.long 0x0 20. "RESET_SRC_STAT_DBUGSS_RST_PROXY,When set indicates that a Debug reset occurred. Write 1 to clear this bit." "0,1" newline bitfld.long 0x0 19. "RESET_SRC_STAT_COLD_OUT_RST_PROXY,When set indicates that a SMS Cold reset occurred. Write 1 to clear this bit." "0,1" newline bitfld.long 0x0 16. "RESET_SRC_STAT_WARM_OUT_RST_PROXY,When set indicates that a SMS Warm reset occurred. Write 1 to clear this bit." "0,1" newline bitfld.long 0x0 11. "RESET_SRC_STAT_PORZ_PIN_PROXY,When set indicates that a PORz pin reset occurred. Write 1 to clear this bit." "0,1" newline bitfld.long 0x0 9. "RESET_SRC_STAT_RESET_REQZ_PIN_PROXY,When set indicates that a RESET_REQz pin reset occurred. Write 1 to clear this bit." "0,1" newline bitfld.long 0x0 8. "RESET_SRC_STAT_MCU_RSTZ_PIN_PROXY,When set indicates that a MCU_RESETz pin reset occurred. Write 1 to clear this bit." "0,1" newline bitfld.long 0x0 3. "RESET_SRC_STAT_SW_MAIN_POR_PROXY,When set indicates that a Software MAIN Power-on reset occurred. Write 1 to clear this bit." "0,1" newline bitfld.long 0x0 1. "RESET_SRC_STAT_SW_MAIN_WARMRST_PROXY,When set indicates that a Software MAIN Warm reset occurred. Write 1 to clear this bit." "0,1" newline bitfld.long 0x0 0. "RESET_SRC_STAT_SW_MCU_WARMRST_PROXY,When set indicates that a Software MCU Warm reset occurred. Write 1 to clear this bit." "0,1" rgroup.long 0x2060++0x1F line.long 0x0 "CFG0_DEVICE_FEATURE0_PROXY," bitfld.long 0x0 7. "DEVICE_FEATURE0_MPU_CLUSTER1_CORE3_PROXY,MPU Cluster1 Core 3 is enabled when set" "0,1" newline bitfld.long 0x0 6. "DEVICE_FEATURE0_MPU_CLUSTER1_CORE2_PROXY,MPU Cluster1 Core 2 is enabled when set" "0,1" newline bitfld.long 0x0 5. "DEVICE_FEATURE0_MPU_CLUSTER1_CORE1_PROXY,MPU Cluster1 Core 1 is enabled when set" "0,1" newline bitfld.long 0x0 4. "DEVICE_FEATURE0_MPU_CLUSTER1_CORE0_PROXY,MPU Cluster1 Core 0 is enabled when set" "0,1" newline bitfld.long 0x0 3. "DEVICE_FEATURE0_MPU_CLUSTER0_CORE3_PROXY,MPU Cluster0 Core 3 is enabled when set" "0,1" newline bitfld.long 0x0 2. "DEVICE_FEATURE0_MPU_CLUSTER0_CORE2_PROXY,MPU Cluster0 Core 2 is enabled when set" "0,1" newline bitfld.long 0x0 1. "DEVICE_FEATURE0_MPU_CLUSTER0_CORE1_PROXY,MPU Cluster0 Core 1 is enabled when set" "0,1" newline bitfld.long 0x0 0. "DEVICE_FEATURE0_MPU_CLUSTER0_CORE0_PROXY,MPU Cluster0 Core 0 is enabled when set" "0,1" line.long 0x4 "CFG0_DEVICE_FEATURE1_PROXY," bitfld.long 0x4 19. "DEVICE_FEATURE1_C71_CORE3_PROXY,C71 Core3 is enabled when set" "0,1" newline bitfld.long 0x4 18. "DEVICE_FEATURE1_C71_CORE2_PROXY,C71 Core2 is enabled when set" "0,1" newline bitfld.long 0x4 17. "DEVICE_FEATURE1_C71_CORE1_PROXY,C71 Core1 is enabled when set" "0,1" newline bitfld.long 0x4 16. "DEVICE_FEATURE1_C71_CORE0_PROXY,C71 Core0 is enabled when set" "0,1" newline bitfld.long 0x4 13. "DEVICE_FEATURE1_GPU_1_PROXY,GPU1 is enabled when set" "0,1" newline bitfld.long 0x4 12. "DEVICE_FEATURE1_GPU_PROXY,GPU is enabled when set" "0,1" newline bitfld.long 0x4 5. "DEVICE_FEATURE1_MCU_CLUSTER2_CORE1_PROXY,MAIN MCU Cluster2 Core1 is enabled when set" "0,1" newline bitfld.long 0x4 4. "DEVICE_FEATURE1_MCU_CLUSTER2_CORE0_PROXY,MAIN MCU Cluster2 Core0 is enabled when set" "0,1" newline bitfld.long 0x4 3. "DEVICE_FEATURE1_MCU_CLUSTER1_CORE1_PROXY,MAIN MCU Cluster1 Core1 is enabled when set" "0,1" newline bitfld.long 0x4 2. "DEVICE_FEATURE1_MCU_CLUSTER1_CORE0_PROXY,MAIN MCU Cluster1 Core0 is enabled when set" "0,1" newline bitfld.long 0x4 1. "DEVICE_FEATURE1_MCU_CLUSTER0_CORE1_PROXY,MAIN MCU Cluster0 Core1 is enabled when set" "0,1" newline bitfld.long 0x4 0. "DEVICE_FEATURE1_MCU_CLUSTER0_CORE0_PROXY,MAIN MCU Cluster0 Core0 is enabled when set" "0,1" line.long 0x8 "CFG0_DEVICE_FEATURE2_PROXY," bitfld.long 0x8 17. "DEVICE_FEATURE2_SPARE1_PROXY,WKUP_Spare1 LPSC is enabled when set" "0,1" newline bitfld.long 0x8 16. "DEVICE_FEATURE2_SPARE0_PROXY,WKUP_Spare0 LPSC is enabled when set" "0,1" newline bitfld.long 0x8 12. "DEVICE_FEATURE2_ADC1_PROXY,MCU ADC1 is enabled when set" "0,1" newline bitfld.long 0x8 11. "DEVICE_FEATURE2_CRYPTO_SM34_EN_PROXY,MCU SA3_UL Crypto Module SM3/SM4 enabled" "0,1" newline bitfld.long 0x8 10. "DEVICE_FEATURE2_CRYPTO_PKA_EN_PROXY,MCU SA2_UL Crypto Module PKA enabled" "0,1" newline bitfld.long 0x8 9. "DEVICE_FEATURE2_CRYPTO_ENCR_EN_PROXY,MCU SA2_UL Crypto Module AES/3DES/DBRG enabled" "0,1" newline bitfld.long 0x8 8. "DEVICE_FEATURE2_CRYPTO_SHA_EN_PROXY,MCU SA2_UL Crypto Module SHA/MD5 enabled" "0,1" newline bitfld.long 0x8 7. "DEVICE_FEATURE2_AES_AUTH_EN_PROXY,AES authentication is enabled in MCU_FlashSS and SMS when set" "0,1" newline bitfld.long 0x8 6. "DEVICE_FEATURE2_HYPERBUS_PROXY,MCU_Hyperbus is enabled when set" "0,1" newline bitfld.long 0x8 5. "DEVICE_FEATURE2_OSPI1_PROXY,MCU_OSPI1 is enabled when set" "0,1" newline bitfld.long 0x8 4. "DEVICE_FEATURE2_OSPI0_PROXY,MCU_OSPI0 is enabled when set" "0,1" newline bitfld.long 0x8 3. "DEVICE_FEATURE2_MCU_MCAN1_PROXY,MCU_MCAN1 is enabled when set" "0,1" newline bitfld.long 0x8 1. "DEVICE_FEATURE2_MCU_MCAN0_PROXY,MCU_MCAN0 is enabled when set" "0,1" newline bitfld.long 0x8 0. "DEVICE_FEATURE2_MCU_MCAN_FD_MODE_PROXY,FD mode is supported on MCU_MCAN[1:0] when set" "0,1" line.long 0xC "CFG0_DEVICE_FEATURE3_PROXY," bitfld.long 0xC 31. "DEVICE_FEATURE3_EMIF3_PROXY,EMIF3 is enabled when set" "0,1" newline bitfld.long 0xC 30. "DEVICE_FEATURE3_EMIF2_PROXY,EMIF2 is enabled when set" "0,1" newline bitfld.long 0xC 29. "DEVICE_FEATURE3_EMIF1_PROXY,EMIF1 is enabled when set" "0,1" newline bitfld.long 0xC 28. "DEVICE_FEATURE3_EMIF0_PROXY,EMIF0 is enabled when set" "0,1" newline bitfld.long 0xC 22. "DEVICE_FEATURE3_MMC_4B1_PROXY,4-bit MMC/SD02 is enabled when set" "0,1" newline bitfld.long 0xC 21. "DEVICE_FEATURE3_MMC_4B0_PROXY,4-bit MMC/SD1 is enabled when set" "0,1" newline bitfld.long 0xC 20. "DEVICE_FEATURE3_MMC_8B_PROXY,8-bit MMC/SD0 is enabled when set" "0,1" newline bitfld.long 0xC 19. "DEVICE_FEATURE3_HYPERLINK_PROXY,Hyperlink interface is enabled when set" "0,1" newline bitfld.long 0xC 12. "DEVICE_FEATURE3_SERDES4_PROXY,Serdes4 is enabled when set" "0,1" newline bitfld.long 0xC 11. "DEVICE_FEATURE3_SERDES3_PROXY,Serdes3 is enabled when set" "0,1" newline bitfld.long 0xC 10. "DEVICE_FEATURE3_SERDES2_PROXY,Serdes2 is enabled when set" "0,1" newline bitfld.long 0xC 9. "DEVICE_FEATURE3_SERDES1_PROXY,Serdes1 is enabled when set" "0,1" newline bitfld.long 0xC 8. "DEVICE_FEATURE3_SERDES0_PROXY,Serdes0 is enabled when set" "0,1" newline bitfld.long 0xC 7. "DEVICE_FEATURE3_PCIE3_PROXY,PCIe3 is enabled when set" "0,1" newline bitfld.long 0xC 6. "DEVICE_FEATURE3_PCIE2_PROXY,PCIe2 is enabled when set" "0,1" newline bitfld.long 0xC 5. "DEVICE_FEATURE3_PCIE1_PROXY,PCIe1 is enabled when set" "0,1" newline bitfld.long 0xC 4. "DEVICE_FEATURE3_PCIE0_PROXY,PCIe0 is enabled when set" "0,1" newline bitfld.long 0xC 0. "DEVICE_FEATURE3_USB0_PROXY,USB0 is enabled when set" "0,1" line.long 0x10 "CFG0_DEVICE_FEATURE4_PROXY," bitfld.long 0x10 27. "DEVICE_FEATURE4_VID_CODEC1_PROXY,Video encoder/decoder 1 is enabled when set" "0,1" newline bitfld.long 0x10 26. "DEVICE_FEATURE4_VID_CODEC0_PROXY,Video encoder/decoder 0 is enabled when set" "0,1" newline bitfld.long 0x10 25. "DEVICE_FEATURE4_DECODER_PROXY,Video decoder is enabled when set" "0,1" newline bitfld.long 0x10 24. "DEVICE_FEATURE4_ENCODER0_PROXY,Video encoder 0 is enabled when set" "0,1" newline bitfld.long 0x10 19. "DEVICE_FEATURE4_VPAC1_PROXY,VPAC1 is enabled when set" "0,1" newline bitfld.long 0x10 18. "DEVICE_FEATURE4_VPAC0_PROXY,VPAC0 is enabled when set" "0,1" newline bitfld.long 0x10 17. "DEVICE_FEATURE4_SDE_PROXY,DMPAC Stereo Disparity Engine is enabled when set" "0,1" newline bitfld.long 0x10 16. "DEVICE_FEATURE4_DMPAC_PROXY,DMPAC is enabled when set" "0,1" newline bitfld.long 0x10 12. "DEVICE_FEATURE4_EDP0_PROXY,Embedded display port 0 is enabled when set" "0,1" newline bitfld.long 0x10 9. "DEVICE_FEATURE4_CSITX1_PROXY,CSI_TX1 is enabled when set" "0,1" newline bitfld.long 0x10 8. "DEVICE_FEATURE4_CSITX0_PROXY,CSI_TX0 is enabled when set" "0,1" newline bitfld.long 0x10 6. "DEVICE_FEATURE4_CSIRX2_PROXY,CSI_RX2 is enabled when set" "0,1" newline bitfld.long 0x10 5. "DEVICE_FEATURE4_CSIRX1_PROXY,CSI_RX1 is enabled when set" "0,1" newline bitfld.long 0x10 4. "DEVICE_FEATURE4_CSIRX0_PROXY,CSI_RX0 is enabled when set" "0,1" newline bitfld.long 0x10 3. "DEVICE_FEATURE4_DSI1_PROXY,DSI1 is enabled when set" "0,1" newline bitfld.long 0x10 2. "DEVICE_FEATURE4_DSI0_PROXY,DSI0 is enabled when set" "0,1" newline bitfld.long 0x10 0. "DEVICE_FEATURE4_DSS_PROXY,DSS is enabled when set" "0,1" line.long 0x14 "CFG0_DEVICE_FEATURE5_PROXY," bitfld.long 0x14 17. "DEVICE_FEATURE5_MCAN17_PROXY,MCAN17 is enabled when set" "0,1" newline bitfld.long 0x14 16. "DEVICE_FEATURE5_MCAN16_PROXY,MCAN16 is enabled when set" "0,1" newline bitfld.long 0x14 15. "DEVICE_FEATURE5_MCAN15_PROXY,MCAN15 is enabled when set" "0,1" newline bitfld.long 0x14 14. "DEVICE_FEATURE5_MCAN14_PROXY,MCAN14 is enabled when set" "0,1" newline bitfld.long 0x14 13. "DEVICE_FEATURE5_MCAN13_PROXY,MCAN13 is enabled when set" "0,1" newline bitfld.long 0x14 12. "DEVICE_FEATURE5_MCAN12_PROXY,MCAN12 is enabled when set" "0,1" newline bitfld.long 0x14 11. "DEVICE_FEATURE5_MCAN11_PROXY,MCAN11 is enabled when set" "0,1" newline bitfld.long 0x14 10. "DEVICE_FEATURE5_MCAN10_PROXY,MCAN10 is enabled when set" "0,1" newline bitfld.long 0x14 9. "DEVICE_FEATURE5_MCAN9_PROXY,MCAN9 is enabled when set" "0,1" newline bitfld.long 0x14 8. "DEVICE_FEATURE5_MCAN8_PROXY,MCAN8 is enabled when set" "0,1" newline bitfld.long 0x14 7. "DEVICE_FEATURE5_MCAN7_PROXY,MCAN7 is enabled when set" "0,1" newline bitfld.long 0x14 6. "DEVICE_FEATURE5_MCAN6_PROXY,MCAN6 is enabled when set" "0,1" newline bitfld.long 0x14 5. "DEVICE_FEATURE5_MCAN5_PROXY,MCAN5 is enabled when set" "0,1" newline bitfld.long 0x14 4. "DEVICE_FEATURE5_MCAN4_PROXY,MCAN4 is enabled when set" "0,1" newline bitfld.long 0x14 3. "DEVICE_FEATURE5_MCAN3_PROXY,MCAN3 is enabled when set" "0,1" newline bitfld.long 0x14 2. "DEVICE_FEATURE5_MCAN2_PROXY,MCAN2 is enabled when set" "0,1" newline bitfld.long 0x14 1. "DEVICE_FEATURE5_MCAN1_PROXY,MCAN1 is enabled when set" "0,1" newline bitfld.long 0x14 0. "DEVICE_FEATURE5_MCAN0_PROXY,MCAN0 is enabled when set" "0,1" line.long 0x18 "CFG0_DEVICE_FEATURE6_PROXY," bitfld.long 0x18 26. "DEVICE_FEATURE6_SPARE6_PROXY,Spare6 LPSC is enabled when set" "0,1" newline bitfld.long 0x18 25. "DEVICE_FEATURE6_SPARE5_PROXY,Spare5 LPSC is enabled when set" "0,1" newline bitfld.long 0x18 24. "DEVICE_FEATURE6_SPARE4_PROXY,Spare4 LPSC is enabled when set" "0,1" newline bitfld.long 0x18 22. "DEVICE_FEATURE6_PER_SPARE2_PROXY,PER Spare2 LPSC is enabled when set" "0,1" newline bitfld.long 0x18 21. "DEVICE_FEATURE6_PER_SPARE1_PROXY,PER Spare1 LPSC is enabled when set" "0,1" newline bitfld.long 0x18 20. "DEVICE_FEATURE6_PER_SPARE0_PROXY,PER Spare0 LPSC is enabled when set" "0,1" newline bitfld.long 0x18 9. "DEVICE_FEATURE6_I3C_PROXY,MAIN domain I3C is enabled when set" "0,1" newline bitfld.long 0x18 8. "DEVICE_FEATURE6_MOTOR_PER_PROXY,Motor control peripherals (eCAP eQEP eHRPWM) are enabled when set" "0,1" newline bitfld.long 0x18 7. "DEVICE_FEATURE6_ATL_PROXY,Audio tracking logic is enabled when set" "0,1" newline bitfld.long 0x18 5. "DEVICE_FEATURE6_SA2_UL_PROXY,MAIN domain security accelerator is enabled when set" "0,1" newline bitfld.long 0x18 4. "DEVICE_FEATURE6_CPSW5_PROXY,4 Channel Q/SGMII Ethernet switch enabled when set" "0,1" newline bitfld.long 0x18 3. "DEVICE_FEATURE6_CPSW2_PROXY,1 Channel Ethernet switch enabled when set" "0,1" newline bitfld.long 0x18 0. "DEVICE_FEATURE6_UFS0_PROXY,UFS interface 0 is enabled when set" "0,1" line.long 0x1C "CFG0_DEVICE_FEATURE7_PROXY," bitfld.long 0x1C 23. "DEVICE_FEATURE7_BSPARE_PD7_3_PROXY,Bolt-on bspare_pda7_3 LPSC is enabled when set" "0,1" newline bitfld.long 0x1C 22. "DEVICE_FEATURE7_BSPARE_PD7_2_PROXY,Not used" "0,1" newline bitfld.long 0x1C 21. "DEVICE_FEATURE7_ANA_3_DRU_PROXY,Analytics 3 DRU is enabled when set" "0,1" newline bitfld.long 0x1C 20. "DEVICE_FEATURE7_ANA_3_PROXY,Analytics 3 block is enabled when set" "0,1" newline bitfld.long 0x1C 19. "DEVICE_FEATURE7_ANA_2_DRU_PROXY,Analytics 2 DRU is enabled when set" "0,1" newline bitfld.long 0x1C 18. "DEVICE_FEATURE7_ANA_2_PROXY,Analytics 2 block is enabled when set" "0,1" newline bitfld.long 0x1C 17. "DEVICE_FEATURE7_ANA_1_DRU_PROXY,Analytics 1 DRU is enabled when set" "0,1" newline bitfld.long 0x1C 16. "DEVICE_FEATURE7_ANA_1_PROXY,Analytics 1 block is enabled when set" "0,1" newline bitfld.long 0x1C 15. "DEVICE_FEATURE7_ANA_0_DRU_PROXY,Analytics 0 DRU is enabled when set" "0,1" newline bitfld.long 0x1C 14. "DEVICE_FEATURE7_ANA_0_PROXY,Analytics 0 block is enabled when set" "0,1" newline bitfld.long 0x1C 11. "DEVICE_FEATURE7_BSPARE_PD2_1_PROXY,Bolt-on bspare_pda2_1 LPSC is enabled when set" "0,1" newline bitfld.long 0x1C 7. "DEVICE_FEATURE7_BSPARE_AON7_PROXY,Bolt-on bspare_pdaon_7 LPSC is enabled when set" "0,1" newline bitfld.long 0x1C 6. "DEVICE_FEATURE7_BSPARE_AON6_PROXY,Bolt-on bspare_pdaon_6 LPSC is enabled when set" "0,1" newline bitfld.long 0x1C 5. "DEVICE_FEATURE7_BSPARE_AON5_PROXY,Bolt-on bspare_pdaon_5 LPSC is enabled when set" "0,1" newline bitfld.long 0x1C 4. "DEVICE_FEATURE7_BSPARE_AON4_PROXY,Bolt-on bspare_pdaon_4 LPSC is enabled when set" "0,1" newline bitfld.long 0x1C 3. "DEVICE_FEATURE7_BSPARE_AON3_PROXY,Bolt-on bspare_pdaon_3 LPSC is enabled when set" "0,1" newline bitfld.long 0x1C 2. "DEVICE_FEATURE7_BSPARE_AON2_PROXY,Bolt-on bspare_pdaon_2 LPSC is enabled when set" "0,1" newline bitfld.long 0x1C 1. "DEVICE_FEATURE7_BSPARE_AON1_PROXY,Bolt-on bspare_pdaon_1 LPSC is enabled when set" "0,1" newline bitfld.long 0x1C 0. "DEVICE_FEATURE7_BSPARE_AON0_PROXY,Bolt-on bspare_pdaon_0 LPSC is enabled when set" "0,1" rgroup.long 0x2200++0xB line.long 0x0 "CFG0_DBG_CBA_ERR_STAT_PROXY," bitfld.long 0x0 1. "DBG_CBA_ERR_STAT_MAIN_DBG_ERR_PROXY,Main Debug bus segment error" "0,1" line.long 0x4 "CFG0_FW_CBA_ERR_STAT_PROXY," bitfld.long 0x4 2. "FW_CBA_ERR_STAT_MAIN_FW_ERR_PROXY,MAIN Firewall bus segment error" "0,1" newline bitfld.long 0x4 1. "FW_CBA_ERR_STAT_MCU_FW_ERR_PROXY,MCU Firewall bus segment error" "0,1" newline bitfld.long 0x4 0. "FW_CBA_ERR_STAT_WKUP_FW_ERR_PROXY,WKUP Firewall bus segment error" "0,1" line.long 0x8 "CFG0_NONFW_CBA_ERR_STAT_PROXY," bitfld.long 0x8 5. "NONFW_CBA_ERR_STAT_MAIN_INFRA_NS_CBA_ERR_PROXY,MAIN Infrastructure non-safe bus segment error" "0,1" newline bitfld.long 0x8 4. "NONFW_CBA_ERR_STAT_DBG_CBA_ERR_PROXY,Debug bus aggregated error. See DBG_CBA_ERR_STAT for specific segment information." "0,1" newline bitfld.long 0x8 3. "NONFW_CBA_ERR_STAT_WKUP_CBA_ERR_PROXY,WKUP Data bus segment error" "0,1" newline bitfld.long 0x8 2. "NONFW_CBA_ERR_STAT_MCU_CBA_ERR_PROXY,MCU Data bus segment error" "0,1" newline bitfld.long 0x8 1. "NONFW_CBA_ERR_STAT_MAIN_INFRA_CBA_ERR_PROXY,MAIN Infrastructure safe bus segment error" "0,1" newline bitfld.long 0x8 0. "NONFW_CBA_ERR_STAT_MAIN_CBA_ERR_PROXY,MAIN Data bus aggregated error. See MAIN_CBA_ERR_STAT for specific segment information" "0,1" rgroup.long 0x2210++0x3 line.long 0x0 "CFG0_MAIN_CBA_ERR_STAT_PROXY," bitfld.long 0x0 18. "MAIN_CBA_ERR_STAT_PULSAR1_MEM_CBA_ERR_PROXY,MAIN R5 Cluster 1 Memory Data bus segment error" "0,1" newline bitfld.long 0x0 17. "MAIN_CBA_ERR_STAT_PULSAR0_SLV_CBA_ERR_PROXY,MAIN R5 Cluster 0 Slave Data bus segment error" "0,1" newline bitfld.long 0x0 16. "MAIN_CBA_ERR_STAT_PULSAR0_MEM_CBA_ERR_PROXY,MAIN R5 Cluster 0 Memory Data bus segment error" "0,1" newline bitfld.long 0x0 13. "MAIN_CBA_ERR_STAT_IPPHY_SAFE_CBA_ERR_PROXY,MAIN Phy safe Data bus segment error" "0,1" newline bitfld.long 0x0 10. "MAIN_CBA_ERR_STAT_IPPHY_CBA_ERR_PROXY,MAIN Phy non-safe Data bus segment error" "0,1" newline bitfld.long 0x0 9. "MAIN_CBA_ERR_STAT_CSI_CBA_ERR_PROXY,MAIN CSI Data bus segment error" "0,1" newline bitfld.long 0x0 7. "MAIN_CBA_ERR_STAT_DEBUG_CBA_ERR_PROXY,MAIN Debug Data bus segment error" "0,1" newline bitfld.long 0x0 6. "MAIN_CBA_ERR_STAT_HC2_CBA_ERR_PROXY,MAIN HC2 Data bus segment error" "0,1" newline bitfld.long 0x0 5. "MAIN_CBA_ERR_STAT_HC_CFG_CBA_ERR_PROXY,MAIN HC CFG Data bus segment error" "0,1" newline bitfld.long 0x0 4. "MAIN_CBA_ERR_STAT_AC_CFG_NS_CBA_ERR_PROXY,MAIN AC non-safe CFG Data bus segment error" "0,1" newline bitfld.long 0x0 3. "MAIN_CBA_ERR_STAT_RC_CFG_CBA_ERR_PROXY,MAIN RC CFG Data bus segment error" "0,1" newline bitfld.long 0x0 2. "MAIN_CBA_ERR_STAT_RC_CBA_ERR_PROXY,MAIN RC Data bus segment error" "0,1" newline bitfld.long 0x0 1. "MAIN_CBA_ERR_STAT_AC_CFG_CBA_ERR_PROXY,MAIN AC CFG Data bus segment error" "0,1" newline bitfld.long 0x0 0. "MAIN_CBA_ERR_STAT_AC_CBA_ERR_PROXY,MAIN AC Data bus segment error" "0,1" rgroup.long 0x2300++0xF line.long 0x0 "CFG0_WKUP_SPARE_FUSE0_PROXY," hexmask.long 0x0 0.--31. 1. "WKUP_SPARE_FUSE0_FUSE_VAL_PROXY,Fuse value" line.long 0x4 "CFG0_WKUP_SPARE_FUSE1_PROXY," hexmask.long 0x4 0.--31. 1. "WKUP_SPARE_FUSE1_FUSE_VAL_PROXY,Fuse value" line.long 0x8 "CFG0_WKUP_SPARE_FUSE2_PROXY," hexmask.long 0x8 0.--31. 1. "WKUP_SPARE_FUSE2_FUSE_VAL_PROXY,Fuse value" line.long 0xC "CFG0_WKUP_SPARE_FUSE3_PROXY," hexmask.long 0xC 0.--31. 1. "WKUP_SPARE_FUSE3_FUSE_VAL_PROXY,Fuse value" rgroup.long 0x2350++0x7 line.long 0x0 "CFG0_SPARE_PLL0_CAL_PROXY," hexmask.long.word 0x0 0.--11. 1. "SPARE_PLL0_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL0_cal_in to begin the PLL calibration sequence." line.long 0x4 "CFG0_SPARE_PLL1_CAL_PROXY," hexmask.long.word 0x4 0.--11. 1. "SPARE_PLL1_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL1_cal_in to begin the PLL calibration sequence." rgroup.long 0x2360++0xB line.long 0x0 "CFG0_MCU_PLL0_CAL_PROXY," hexmask.long.word 0x0 0.--11. 1. "MCU_PLL0_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL0_cal_in to begin the PLL calibration sequence." line.long 0x4 "CFG0_MCU_PLL1_CAL_PROXY," hexmask.long.word 0x4 0.--11. 1. "MCU_PLL1_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL1_cal_in to begin the PLL calibration sequence." line.long 0x8 "CFG0_MCU_PLL2_CAL_PROXY," hexmask.long.word 0x8 0.--11. 1. "MCU_PLL2_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL2_cal_in to begin the PLL calibration sequence." rgroup.long 0x2380++0x27 line.long 0x0 "CFG0_MAIN_PLL0_CAL_PROXY," hexmask.long.word 0x0 0.--11. 1. "MAIN_PLL0_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL0_cal_in to begin the PLL calibration sequence." line.long 0x4 "CFG0_MAIN_PLL1_CAL_PROXY," hexmask.long.word 0x4 0.--11. 1. "MAIN_PLL1_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL1_cal_in to begin the PLL calibration sequence." line.long 0x8 "CFG0_MAIN_PLL2_CAL_PROXY," hexmask.long.word 0x8 0.--11. 1. "MAIN_PLL2_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL2_cal_in to begin the PLL calibration sequence." line.long 0xC "CFG0_MAIN_PLL3_CAL_PROXY," hexmask.long.word 0xC 0.--11. 1. "MAIN_PLL3_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL3_cal_in to begin the PLL calibration sequence." line.long 0x10 "CFG0_MAIN_PLL4_CAL_PROXY," hexmask.long.word 0x10 0.--11. 1. "MAIN_PLL4_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL4_cal_in to begin the PLL calibration sequence." line.long 0x14 "CFG0_MAIN_PLL5_CAL_PROXY," hexmask.long.word 0x14 0.--11. 1. "MAIN_PLL5_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL5_cal_in to begin the PLL calibration sequence." line.long 0x18 "CFG0_MAIN_PLL6_CAL_PROXY," hexmask.long.word 0x18 0.--11. 1. "MAIN_PLL6_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL6_cal_in to begin the PLL calibration sequence." line.long 0x1C "CFG0_MAIN_PLL7_CAL_PROXY," hexmask.long.word 0x1C 0.--11. 1. "MAIN_PLL7_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL7_cal_in to begin the PLL calibration sequence." line.long 0x20 "CFG0_MAIN_PLL8_CAL_PROXY," hexmask.long.word 0x20 0.--11. 1. "MAIN_PLL8_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL8_cal_in to begin the PLL calibration sequence." line.long 0x24 "CFG0_MAIN_PLL9_CAL_PROXY," hexmask.long.word 0x24 0.--11. 1. "MAIN_PLL9_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL9_cal_in to begin the PLL calibration sequence." rgroup.long 0x23B0++0x3 line.long 0x0 "CFG0_MAIN_PLL12_CAL_PROXY," hexmask.long.word 0x0 0.--11. 1. "MAIN_PLL12_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL12_cal_in to begin the PLL calibration sequence." rgroup.long 0x23B8++0x3 line.long 0x0 "CFG0_MAIN_PLL14_CAL_PROXY," hexmask.long.word 0x0 0.--11. 1. "MAIN_PLL14_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL14_cal_in to begin the PLL calibration sequence." rgroup.long 0x23C0++0x7 line.long 0x0 "CFG0_MAIN_PLL16_CAL_PROXY," hexmask.long.word 0x0 0.--11. 1. "MAIN_PLL16_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL16_cal_in to begin the PLL calibration sequence." line.long 0x4 "CFG0_MAIN_PLL17_CAL_PROXY," hexmask.long.word 0x4 0.--11. 1. "MAIN_PLL17_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL17_cal_in to begin the PLL calibration sequence." rgroup.long 0x23CC++0x3 line.long 0x0 "CFG0_MAIN_PLL19_CAL_PROXY," hexmask.long.word 0x0 0.--11. 1. "MAIN_PLL19_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL19_cal_in to begin the PLL calibration sequence." rgroup.long 0x23E4++0xF line.long 0x0 "CFG0_MAIN_PLL25_CAL_PROXY," hexmask.long.word 0x0 0.--11. 1. "MAIN_PLL25_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL25_cal_in to begin the PLL calibration sequence." line.long 0x4 "CFG0_MAIN_PLL26_CAL_PROXY," hexmask.long.word 0x4 0.--11. 1. "MAIN_PLL26_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL26_cal_in to begin the PLL calibration sequence." line.long 0x8 "CFG0_MAIN_PLL27_CAL_PROXY," hexmask.long.word 0x8 0.--11. 1. "MAIN_PLL27_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL27_cal_in to begin the PLL calibration sequence." line.long 0xC "CFG0_MAIN_PLL28_CAL_PROXY," hexmask.long.word 0xC 0.--11. 1. "MAIN_PLL28_CAL_DEF_CAL_VAL_PROXY,PLL Initial calibration value This value can be used as the initial value written to PLL28_cal_in to begin the PLL calibration sequence." rgroup.long 0x3008++0x1B line.long 0x0 "CFG0_LOCK0_KICK0_PROXY," hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK0_KICK1_PROXY," hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1_PROXY,- KICK1 component" line.long 0x8 "CFG0_intr_raw_status_PROXY," bitfld.long 0x8 3. "PROXY_ERR_PROXY,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 2. "KICK_ERR_PROXY,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 1. "ADDR_ERR_PROXY,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 0. "PROT_ERR_PROXY,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0xC "CFG0_intr_enabled_status_clear_PROXY," bitfld.long 0xC 3. "ENABLED_PROXY_ERR_PROXY,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 2. "ENABLED_KICK_ERR_PROXY,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 1. "ENABLED_ADDR_ERR_PROXY,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 0. "ENABLED_PROT_ERR_PROXY,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x10 "CFG0_intr_enable_PROXY," bitfld.long 0x10 3. "PROXY_ERR_EN_PROXY,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 2. "KICK_ERR_EN_PROXY,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 1. "ADDR_ERR_EN_PROXY,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 0. "PROT_ERR_EN_PROXY,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0x14 "CFG0_intr_enable_clear_PROXY," bitfld.long 0x14 3. "PROXY_ERR_EN_CLR_PROXY,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 2. "KICK_ERR_EN_CLR_PROXY,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 1. "ADDR_ERR_EN_CLR_PROXY,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 0. "PROT_ERR_EN_CLR_PROXY,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x18 "CFG0_eoi_PROXY," hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR_PROXY,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x3024++0xB line.long 0x0 "CFG0_fault_address_PROXY," hexmask.long 0x0 0.--31. 1. "FAULT_ADDR_PROXY,Fault Address." line.long 0x4 "CFG0_fault_type_status_PROXY," bitfld.long 0x4 6. "FAULT_NS_PROXY,Non-secure access." "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE_PROXY,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv =.." line.long 0x8 "CFG0_fault_attr_status_PROXY," hexmask.long.word 0x8 20.--31. 1. "FAULT_XID_PROXY,XID." newline hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID_PROXY,Route ID." newline hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID_PROXY,Privilege ID." rgroup.long 0x3030++0x3 line.long 0x0 "CFG0_fault_clear_PROXY," bitfld.long 0x0 0. "FAULT_CLR_PROXY,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" rgroup.long 0x3100++0x1F line.long 0x0 "CFG0_CLAIMREG_P0_R0," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P0_R0,Claim bits for Partition 0" line.long 0x4 "CFG0_CLAIMREG_P0_R1," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P0_R1,Claim bits for Partition 0" line.long 0x8 "CFG0_CLAIMREG_P0_R2," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P0_R2,Claim bits for Partition 0" line.long 0xC "CFG0_CLAIMREG_P0_R3," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P0_R3,Claim bits for Partition 0" line.long 0x10 "CFG0_CLAIMREG_P0_R4," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P0_R4,Claim bits for Partition 0" line.long 0x14 "CFG0_CLAIMREG_P0_R5," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P0_R5,Claim bits for Partition 0" line.long 0x18 "CFG0_CLAIMREG_P0_R6," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P0_R6,Claim bits for Partition 0" line.long 0x1C "CFG0_CLAIMREG_P0_R7," hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P0_R7,Claim bits for Partition 0" rgroup.long 0x4004++0x7 line.long 0x0 "CFG0_MAIN_PWR_CTRL," bitfld.long 0x0 16. "MAIN_PWR_CTRL_WAKE_EN,When set drives the PMIC_WAKE0 output (low). This bit should be set to 1'b1 only for diagnostic purposes. 0 - PMIC_WAKE0 output is tri-stated (controlled by IO daisy-chain wakeup) 1 - Force PMIC_WAKE0 output enable (PMIC_WAKE0.." "0: PMIC_WAKE0 output is tri-stated,1: Force PMIC_WAKE0 output enable" newline bitfld.long 0x0 0. "MAIN_PWR_CTRL_PWR_EN,When set drives the PMIC_PWR_EN1 output to turn on the MAIN voltage domain" "0,1" line.long 0x4 "CFG0_MCU_PWR_CTRL," bitfld.long 0x4 16. "MCU_PWR_CTRL_WAKE_EN,When set drives the PMIC_WAKE1 output (low). This bit should be set to 1'b1 only for diagnostic purposes. 0 - PMIC_WAKE1 output is tri-stated (controlled by IO daisy-chain wakeup) 1 - Force PMIC_WAKE1 output enable (PMIC_WAKE1.." "0: PMIC_WAKE1 output is tri-stated,1: Force PMIC_WAKE1 output enable" rgroup.long 0x4020++0x3 line.long 0x0 "CFG0_WKUP_GPIO_CTRL," bitfld.long 0x0 0. "WKUP_GPIO_CTRL_WAKEN,Enables WKUP_GPIO wakeup event operation by controlling the WKUP_GPIO LPSC clockstop_ack behavior. 1'b0 - No WKUP_GPIO wakeup support. WKUP_GPIO vbus clock is gated on LPSC clkstop_req. Field values (others are reserved): 1'b0 -.." "0: No WKUP_GPIO wakeup support,1: WKUP_GPIO wakeup enabled" rgroup.long 0x4030++0x3 line.long 0x0 "CFG0_WKUP_I2C0_CTRL," bitfld.long 0x0 0. "WKUP_I2C0_CTRL_HS_MCS_EN,HS Mode master current source enable. When set enables the current-source pull-up on the SCL output. Only one master on the I2C bus should enable SCL current sourcing." "0,1" rgroup.long 0x4084++0x17 line.long 0x0 "CFG0_DBOUNCE_CFG1," hexmask.long.byte 0x0 0.--5. 1. "DBOUNCE_CFG1_DB_CFG,Configures the debounce period used for I/Os with debounce_sel1 enabled. See the J7 IO Integration Spec for details." line.long 0x4 "CFG0_DBOUNCE_CFG2," hexmask.long.byte 0x4 0.--5. 1. "DBOUNCE_CFG2_DB_CFG,Configures the debounce period used for I/Os with debounce_sel2 enabled. See the J7 IO Integration Spec for details." line.long 0x8 "CFG0_DBOUNCE_CFG3," hexmask.long.byte 0x8 0.--5. 1. "DBOUNCE_CFG3_DB_CFG,Configures the debounce period used for I/Os with debounce_sel3 enabled. See the J7 IO Integration Spec for details." line.long 0xC "CFG0_DBOUNCE_CFG4," hexmask.long.byte 0xC 0.--5. 1. "DBOUNCE_CFG4_DB_CFG,Configures the debounce period used for I/Os with debounce_sel4 enabled. See the J7 IO Integration Spec for details." line.long 0x10 "CFG0_DBOUNCE_CFG5," hexmask.long.byte 0x10 0.--5. 1. "DBOUNCE_CFG5_DB_CFG,Configures the debounce period used for I/Os with debounce_sel5 enabled. See the J7 IO Integration Spec for details." line.long 0x14 "CFG0_DBOUNCE_CFG6," hexmask.long.byte 0x14 0.--5. 1. "DBOUNCE_CFG6_DB_CFG,Configures the debounce period used for I/Os with debounce_sel6 enabled. See the J7 IO Integration Spec for details." rgroup.long 0x40C0++0x1F line.long 0x0 "CFG0_H_IO_DRVSTRNGTH0," hexmask.long.byte 0x0 0.--3. 1. "H_IO_DRVSTRNGTH0_DRV_STR,Indicates the 4-bit DS value sent to horizontal IO buffers with a PADCONFIG DS value of 2'b00" line.long 0x4 "CFG0_H_IO_DRVSTRNGTH1," hexmask.long.byte 0x4 0.--3. 1. "H_IO_DRVSTRNGTH1_DRV_STR,Indicates the 4-bit DS value sent to horizontal IO buffers with a PADCONFIG DS value of 2'b01" line.long 0x8 "CFG0_H_IO_DRVSTRNGTH2," hexmask.long.byte 0x8 0.--3. 1. "H_IO_DRVSTRNGTH2_DRV_STR,Indicates the 4-bit DS value sent to horizontal IO buffers with a PADCONFIG DS value of 2'b10" line.long 0xC "CFG0_H_IO_DRVSTRNGTH3," hexmask.long.byte 0xC 0.--3. 1. "H_IO_DRVSTRNGTH3_DRV_STR,Indicates the 4-bit DS value sent to horizontal IO buffers with a PADCONFIG DS value of 2'b11" line.long 0x10 "CFG0_V_IO_DRVSTRNGTH0," hexmask.long.byte 0x10 0.--3. 1. "V_IO_DRVSTRNGTH0_DRV_STR,Indicates the 4-bit DS value sent to vertical IO buffers with a PADCONFIG DS value of 2'b00" line.long 0x14 "CFG0_V_IO_DRVSTRNGTH1," hexmask.long.byte 0x14 0.--3. 1. "V_IO_DRVSTRNGTH1_DRV_STR,Indicates the 4-bit DS value sent to vertical IO buffers with a PADCONFIG DS value of 2'b01" line.long 0x18 "CFG0_V_IO_DRVSTRNGTH2," hexmask.long.byte 0x18 0.--3. 1. "V_IO_DRVSTRNGTH2_DRV_STR,Indicates the 4-bit DS value sent to vertical IO buffers with a PADCONFIG DS value of 2'b10" line.long 0x1C "CFG0_V_IO_DRVSTRNGTH3," hexmask.long.byte 0x1C 0.--3. 1. "V_IO_DRVSTRNGTH3_DRV_STR,Indicates the 4-bit DS value sent to vertical IO buffers with a PADCONFIG DS value of 2'b11" rgroup.long 0x4100++0x1F line.long 0x0 "CFG0_WKUP_SPARE_CTRL0," hexmask.long 0x0 0.--31. 1. "WKUP_SPARE_CTRL0_SPARE_OUT,Write 1 to pulse bits. Reset by PORz only. Do not optimize away outputs" line.long 0x4 "CFG0_WKUP_SPARE_CTRL1," hexmask.long 0x4 0.--31. 1. "WKUP_SPARE_CTRL1_SPARE_OUT,Read/write bits. Reset by PORz only. Do not optimize away outputs" line.long 0x8 "CFG0_WKUP_SPARE_CTRL2," hexmask.long 0x8 0.--31. 1. "WKUP_SPARE_CTRL2_SPARE_OUT,Read/write bits. Reset by PORz only. Do not optimize away outputs" line.long 0xC "CFG0_WKUP_SPARE_CTRL3," hexmask.long 0xC 0.--31. 1. "WKUP_SPARE_CTRL3_SPARE_OUT,Read/write bits. Reset by PORz only. Do not optimize away outputs" line.long 0x10 "CFG0_WKUP_SPARE_CTRL4," hexmask.long 0x10 0.--31. 1. "WKUP_SPARE_CTRL4_SPARE_OUT,Write 1 to pulse bits. Reset by any reset. Do not optimize away outputs" line.long 0x14 "CFG0_WKUP_SPARE_CTRL5," hexmask.long 0x14 0.--31. 1. "WKUP_SPARE_CTRL5_SPARE_OUT,Read/write bits. Reset by any reset. Do not optimize away outputs" line.long 0x18 "CFG0_WKUP_SPARE_CTRL6," hexmask.long 0x18 0.--31. 1. "WKUP_SPARE_CTRL6_SPARE_OUT,Read/write bits. Reset by any reset. Do not optimize away outputs" line.long 0x1C "CFG0_WKUP_SPARE_CTRL7," hexmask.long 0x1C 0.--31. 1. "WKUP_SPARE_CTRL7_SPARE_OUT,Read/write bits. Reset by any reset. Do not optimize away outputs" rgroup.long 0x4140++0x1F line.long 0x0 "CFG0_WKUP_SPARE_STAT0," hexmask.long 0x0 0.--31. 1. "WKUP_SPARE_STAT0_SPARE_IN,Read-only bits. Reset by PORz only. Do not optimize away inputs" line.long 0x4 "CFG0_WKUP_SPARE_STAT1," hexmask.long 0x4 0.--31. 1. "WKUP_SPARE_STAT1_SPARE_IN,Read-only bits. Reset by PORz only. Do not optimize away inputs" line.long 0x8 "CFG0_WKUP_SPARE_STAT2," hexmask.long 0x8 0.--31. 1. "WKUP_SPARE_STAT2_SPARE_IN,Read-only bits. Reset by PORz only. Do not optimize away inputs" line.long 0xC "CFG0_WKUP_SPARE_STAT3," hexmask.long 0xC 0.--31. 1. "WKUP_SPARE_STAT3_SPARE_IN,Read-only bits. Reset by PORz only. Do not optimize away inputs" line.long 0x10 "CFG0_WKUP_SPARE_STAT4," hexmask.long 0x10 0.--31. 1. "WKUP_SPARE_STAT4_SPARE_IN,Read-only bits. Reset by any reset. Do not optimize away inputs" line.long 0x14 "CFG0_WKUP_SPARE_STAT5," hexmask.long 0x14 0.--31. 1. "WKUP_SPARE_STAT5_SPARE_IN,Read-only bits. Reset by any reset. Do not optimize away inputs" line.long 0x18 "CFG0_WKUP_SPARE_STAT6," hexmask.long 0x18 0.--31. 1. "WKUP_SPARE_STAT6_SPARE_IN,Read-only bits. Reset by any reset. Do not optimize away inputs" line.long 0x1C "CFG0_WKUP_SPARE_STAT7," hexmask.long 0x1C 0.--31. 1. "WKUP_SPARE_STAT7_SPARE_IN,Read-only bits. Reset by any reset. Do not optimize away inputs" rgroup.long 0x5008++0x7 line.long 0x0 "CFG0_LOCK1_KICK0," hexmask.long 0x0 0.--31. 1. "LOCK1_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK1_KICK1," hexmask.long 0x4 0.--31. 1. "LOCK1_KICK1,- KICK1 component" rgroup.long 0x5100++0xB line.long 0x0 "CFG0_CLAIMREG_P1_R0_READONLY," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P1_R0_READONLY,Claim bits for Partition 1" line.long 0x4 "CFG0_CLAIMREG_P1_R1_READONLY," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P1_R1_READONLY,Claim bits for Partition 1" line.long 0x8 "CFG0_CLAIMREG_P1_R2_READONLY," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P1_R2_READONLY,Claim bits for Partition 1" rgroup.long 0x6004++0x7 line.long 0x0 "CFG0_MAIN_PWR_CTRL_PROXY," bitfld.long 0x0 16. "MAIN_PWR_CTRL_WAKE_EN_PROXY,When set drives the PMIC_WAKE0 output (low). This bit should be set to 1'b1 only for diagnostic purposes. 0 - PMIC_WAKE0 output is tri-stated (controlled by IO daisy-chain wakeup) 1 - Force PMIC_WAKE0 output enable.." "0: PMIC_WAKE0 output is tri-stated,1: Force PMIC_WAKE0 output enable" newline bitfld.long 0x0 0. "MAIN_PWR_CTRL_PWR_EN_PROXY,When set drives the PMIC_PWR_EN1 output to turn on the MAIN voltage domain" "0,1" line.long 0x4 "CFG0_MCU_PWR_CTRL_PROXY," bitfld.long 0x4 16. "MCU_PWR_CTRL_WAKE_EN_PROXY,When set drives the PMIC_WAKE1 output (low). This bit should be set to 1'b1 only for diagnostic purposes. 0 - PMIC_WAKE1 output is tri-stated (controlled by IO daisy-chain wakeup) 1 - Force PMIC_WAKE1 output enable.." "0: PMIC_WAKE1 output is tri-stated,1: Force PMIC_WAKE1 output enable" rgroup.long 0x6020++0x3 line.long 0x0 "CFG0_WKUP_GPIO_CTRL_PROXY," bitfld.long 0x0 0. "WKUP_GPIO_CTRL_WAKEN_PROXY,Enables WKUP_GPIO wakeup event operation by controlling the WKUP_GPIO LPSC clockstop_ack behavior. 1'b0 - No WKUP_GPIO wakeup support. WKUP_GPIO vbus clock is gated on LPSC clkstop_req. Field values (others are reserved):.." "0: No WKUP_GPIO wakeup support,1: WKUP_GPIO wakeup enabled" rgroup.long 0x6030++0x3 line.long 0x0 "CFG0_WKUP_I2C0_CTRL_PROXY," bitfld.long 0x0 0. "WKUP_I2C0_CTRL_HS_MCS_EN_PROXY,HS Mode master current source enable. When set enables the current-source pull-up on the SCL output. Only one master on the I2C bus should enable SCL current sourcing." "0,1" rgroup.long 0x6084++0x17 line.long 0x0 "CFG0_DBOUNCE_CFG1_PROXY," hexmask.long.byte 0x0 0.--5. 1. "DBOUNCE_CFG1_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel1 enabled. See the J7 IO Integration Spec for details." line.long 0x4 "CFG0_DBOUNCE_CFG2_PROXY," hexmask.long.byte 0x4 0.--5. 1. "DBOUNCE_CFG2_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel2 enabled. See the J7 IO Integration Spec for details." line.long 0x8 "CFG0_DBOUNCE_CFG3_PROXY," hexmask.long.byte 0x8 0.--5. 1. "DBOUNCE_CFG3_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel3 enabled. See the J7 IO Integration Spec for details." line.long 0xC "CFG0_DBOUNCE_CFG4_PROXY," hexmask.long.byte 0xC 0.--5. 1. "DBOUNCE_CFG4_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel4 enabled. See the J7 IO Integration Spec for details." line.long 0x10 "CFG0_DBOUNCE_CFG5_PROXY," hexmask.long.byte 0x10 0.--5. 1. "DBOUNCE_CFG5_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel5 enabled. See the J7 IO Integration Spec for details." line.long 0x14 "CFG0_DBOUNCE_CFG6_PROXY," hexmask.long.byte 0x14 0.--5. 1. "DBOUNCE_CFG6_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel6 enabled. See the J7 IO Integration Spec for details." rgroup.long 0x60C0++0x1F line.long 0x0 "CFG0_H_IO_DRVSTRNGTH0_PROXY," hexmask.long.byte 0x0 0.--3. 1. "H_IO_DRVSTRNGTH0_DRV_STR_PROXY,Indicates the 4-bit DS value sent to horizontal IO buffers with a PADCONFIG DS value of 2'b00" line.long 0x4 "CFG0_H_IO_DRVSTRNGTH1_PROXY," hexmask.long.byte 0x4 0.--3. 1. "H_IO_DRVSTRNGTH1_DRV_STR_PROXY,Indicates the 4-bit DS value sent to horizontal IO buffers with a PADCONFIG DS value of 2'b01" line.long 0x8 "CFG0_H_IO_DRVSTRNGTH2_PROXY," hexmask.long.byte 0x8 0.--3. 1. "H_IO_DRVSTRNGTH2_DRV_STR_PROXY,Indicates the 4-bit DS value sent to horizontal IO buffers with a PADCONFIG DS value of 2'b10" line.long 0xC "CFG0_H_IO_DRVSTRNGTH3_PROXY," hexmask.long.byte 0xC 0.--3. 1. "H_IO_DRVSTRNGTH3_DRV_STR_PROXY,Indicates the 4-bit DS value sent to horizontal IO buffers with a PADCONFIG DS value of 2'b11" line.long 0x10 "CFG0_V_IO_DRVSTRNGTH0_PROXY," hexmask.long.byte 0x10 0.--3. 1. "V_IO_DRVSTRNGTH0_DRV_STR_PROXY,Indicates the 4-bit DS value sent to vertical IO buffers with a PADCONFIG DS value of 2'b00" line.long 0x14 "CFG0_V_IO_DRVSTRNGTH1_PROXY," hexmask.long.byte 0x14 0.--3. 1. "V_IO_DRVSTRNGTH1_DRV_STR_PROXY,Indicates the 4-bit DS value sent to vertical IO buffers with a PADCONFIG DS value of 2'b01" line.long 0x18 "CFG0_V_IO_DRVSTRNGTH2_PROXY," hexmask.long.byte 0x18 0.--3. 1. "V_IO_DRVSTRNGTH2_DRV_STR_PROXY,Indicates the 4-bit DS value sent to vertical IO buffers with a PADCONFIG DS value of 2'b10" line.long 0x1C "CFG0_V_IO_DRVSTRNGTH3_PROXY," hexmask.long.byte 0x1C 0.--3. 1. "V_IO_DRVSTRNGTH3_DRV_STR_PROXY,Indicates the 4-bit DS value sent to vertical IO buffers with a PADCONFIG DS value of 2'b11" rgroup.long 0x6100++0x1F line.long 0x0 "CFG0_WKUP_SPARE_CTRL0_PROXY," hexmask.long 0x0 0.--31. 1. "WKUP_SPARE_CTRL0_SPARE_OUT_PROXY,Write 1 to pulse bits. Reset by PORz only. Do not optimize away outputs" line.long 0x4 "CFG0_WKUP_SPARE_CTRL1_PROXY," hexmask.long 0x4 0.--31. 1. "WKUP_SPARE_CTRL1_SPARE_OUT_PROXY,Read/write bits. Reset by PORz only. Do not optimize away outputs" line.long 0x8 "CFG0_WKUP_SPARE_CTRL2_PROXY," hexmask.long 0x8 0.--31. 1. "WKUP_SPARE_CTRL2_SPARE_OUT_PROXY,Read/write bits. Reset by PORz only. Do not optimize away outputs" line.long 0xC "CFG0_WKUP_SPARE_CTRL3_PROXY," hexmask.long 0xC 0.--31. 1. "WKUP_SPARE_CTRL3_SPARE_OUT_PROXY,Read/write bits. Reset by PORz only. Do not optimize away outputs" line.long 0x10 "CFG0_WKUP_SPARE_CTRL4_PROXY," hexmask.long 0x10 0.--31. 1. "WKUP_SPARE_CTRL4_SPARE_OUT_PROXY,Write 1 to pulse bits. Reset by any reset. Do not optimize away outputs" line.long 0x14 "CFG0_WKUP_SPARE_CTRL5_PROXY," hexmask.long 0x14 0.--31. 1. "WKUP_SPARE_CTRL5_SPARE_OUT_PROXY,Read/write bits. Reset by any reset. Do not optimize away outputs" line.long 0x18 "CFG0_WKUP_SPARE_CTRL6_PROXY," hexmask.long 0x18 0.--31. 1. "WKUP_SPARE_CTRL6_SPARE_OUT_PROXY,Read/write bits. Reset by any reset. Do not optimize away outputs" line.long 0x1C "CFG0_WKUP_SPARE_CTRL7_PROXY," hexmask.long 0x1C 0.--31. 1. "WKUP_SPARE_CTRL7_SPARE_OUT_PROXY,Read/write bits. Reset by any reset. Do not optimize away outputs" rgroup.long 0x6140++0x1F line.long 0x0 "CFG0_WKUP_SPARE_STAT0_PROXY," hexmask.long 0x0 0.--31. 1. "WKUP_SPARE_STAT0_SPARE_IN_PROXY,Read-only bits. Reset by PORz only. Do not optimize away inputs" line.long 0x4 "CFG0_WKUP_SPARE_STAT1_PROXY," hexmask.long 0x4 0.--31. 1. "WKUP_SPARE_STAT1_SPARE_IN_PROXY,Read-only bits. Reset by PORz only. Do not optimize away inputs" line.long 0x8 "CFG0_WKUP_SPARE_STAT2_PROXY," hexmask.long 0x8 0.--31. 1. "WKUP_SPARE_STAT2_SPARE_IN_PROXY,Read-only bits. Reset by PORz only. Do not optimize away inputs" line.long 0xC "CFG0_WKUP_SPARE_STAT3_PROXY," hexmask.long 0xC 0.--31. 1. "WKUP_SPARE_STAT3_SPARE_IN_PROXY,Read-only bits. Reset by PORz only. Do not optimize away inputs" line.long 0x10 "CFG0_WKUP_SPARE_STAT4_PROXY," hexmask.long 0x10 0.--31. 1. "WKUP_SPARE_STAT4_SPARE_IN_PROXY,Read-only bits. Reset by any reset. Do not optimize away inputs" line.long 0x14 "CFG0_WKUP_SPARE_STAT5_PROXY," hexmask.long 0x14 0.--31. 1. "WKUP_SPARE_STAT5_SPARE_IN_PROXY,Read-only bits. Reset by any reset. Do not optimize away inputs" line.long 0x18 "CFG0_WKUP_SPARE_STAT6_PROXY," hexmask.long 0x18 0.--31. 1. "WKUP_SPARE_STAT6_SPARE_IN_PROXY,Read-only bits. Reset by any reset. Do not optimize away inputs" line.long 0x1C "CFG0_WKUP_SPARE_STAT7_PROXY," hexmask.long 0x1C 0.--31. 1. "WKUP_SPARE_STAT7_SPARE_IN_PROXY,Read-only bits. Reset by any reset. Do not optimize away inputs" rgroup.long 0x7008++0x7 line.long 0x0 "CFG0_LOCK1_KICK0_PROXY," hexmask.long 0x0 0.--31. 1. "LOCK1_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK1_KICK1_PROXY," hexmask.long 0x4 0.--31. 1. "LOCK1_KICK1_PROXY,- KICK1 component" rgroup.long 0x7100++0xB line.long 0x0 "CFG0_CLAIMREG_P1_R0," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P1_R0,Claim bits for Partition 1" line.long 0x4 "CFG0_CLAIMREG_P1_R1," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P1_R1,Claim bits for Partition 1" line.long 0x8 "CFG0_CLAIMREG_P1_R2," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P1_R2,Claim bits for Partition 1" rgroup.long 0x8000++0x3 line.long 0x0 "CFG0_MCU_OBSCLK_CTRL," bitfld.long 0x0 24. "MCU_OBSCLK_CTRL_OUT_MUX_SEL,MCU_OBSCLK pin output mux selection. Note when HFOSC0_CLK is selected (1'b1) the MCU_OBSCLK_CTRL_clk_sel field must be programmed to 4'b0001. 1'b0 - The output of the MCU_OBSCLK output divider is output on the pin 1'b1 -.." "0: The output of the MCU_OBSCLK output divider is..,?" newline bitfld.long 0x0 16. "MCU_OBSCLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the OBSCLK divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed." "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "MCU_OBSCLK_CTRL_CLK_DIV,MCU_OBSCLK pin clock selection output divider Output clock is divided by clk_div+1" newline hexmask.long.byte 0x0 0.--3. 1. "MCU_OBSCLK_CTRL_CLK_SEL,MCU_OBSCLK pin clock selection Field values (others are reserved): 4'b0000 - CLK_12M_RC 4'b0001 - '0' 4'b0010 - MCU_PLL0_HSDIV0_CLKOUT 4'b0011 - MCU_PLLCTL_OBSCLK 4'b0100 - MCU_PLL1_HSDIV1_CLKOUT 4'b0101 - MCU_PLL1_HSDIV2_CLKOUT.." rgroup.long 0x8014++0xB line.long 0x0 "CFG0_HFOSC1_CTRL," bitfld.long 0x0 7. "HFOSC1_CTRL_PD_C,Oscillator powerdown control. When set oscillator is disabled. Oscillator output is tristated if bp_c=0" "0,1" newline bitfld.long 0x0 4. "HFOSC1_CTRL_BP_C,Oscillator bypass control. When set oscillator is in bypass mode" "0,1" line.long 0x4 "CFG0_HFOSC0_TRIM," bitfld.long 0x4 31. "HFOSC0_TRIM_TRIM_EN,Apply MMR values to OSC trim inputs instead of tie-offs" "0,1" newline bitfld.long 0x4 24.--25. "HFOSC0_TRIM_FREQ_RNG,Sets the frequency range of operation based on: I(MIRRBIAS) = I(AGC) + 4x I(BIAS) (I(BIAS) : Bias current to AMP_AGC Block I(AGC) : Current from AGC Loop and mirrored)" "0,1,2,3" newline bitfld.long 0x4 20.--21. "HFOSC0_TRIM_HYST,Sets comparator hysteresis" "0,1,2,3" newline bitfld.long 0x4 16.--18. "HFOSC0_TRIM_I_MULT,AGC AMP current multiplication gain I(MIRRBIAS) = I(AGC) + 4x I(BIAS) (I(BIAS) : Bias current to AMP_AGC Block I(AGC) : Current from AGC Loop and mirrored)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--13. 1. "HFOSC0_TRIM_R_REF,Sets the AMP AGC bias current r_ref(5:3) are not used." newline hexmask.long.byte 0x4 4.--7. 1. "HFOSC0_TRIM_I_IBIAS_COMP,Sets the COMP bias current x = 1 uA" newline hexmask.long.byte 0x4 0.--3. 1. "HFOSC0_TRIM_R_IBIAS_REF,Sets the base IBIAS reference" line.long 0x8 "CFG0_HFOSC1_TRIM," bitfld.long 0x8 31. "HFOSC1_TRIM_TRIM_EN,Apply MMR values to OSC trim inputs instead of tie-offs" "0,1" newline bitfld.long 0x8 24.--25. "HFOSC1_TRIM_FREQ_RNG,Sets the frequency range of operation based on: I(MIRRBIAS) = I(AGC) + 4x I(BIAS) (I(BIAS) : Bias current to AMP_AGC Block I(AGC) : Current from AGC Loop and mirrored)" "0,1,2,3" newline bitfld.long 0x8 20.--21. "HFOSC1_TRIM_HYST,Sets comparator hysteresis" "0,1,2,3" newline bitfld.long 0x8 16.--18. "HFOSC1_TRIM_I_MULT,AGC AMP current multiplication gain I(MIRRBIAS) = I(AGC) + 4x I(BIAS) (I(BIAS) : Bias current to AMP_AGC Block I(AGC) : Current from AGC Loop and mirrored)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--13. 1. "HFOSC1_TRIM_R_REF,Sets the AMP AGC bias current r_ref(5:3) are not used." newline hexmask.long.byte 0x8 4.--7. 1. "HFOSC1_TRIM_I_IBIAS_COMP,Sets the COMP bias current x = 1 uA" newline hexmask.long.byte 0x8 0.--3. 1. "HFOSC1_TRIM_R_IBIAS_REF,Sets the base IBIAS reference" rgroup.long 0x8024++0x3 line.long 0x0 "CFG0_RC12M_OSC_TRIM," bitfld.long 0x0 6. "RC12M_OSC_TRIM_TRIMOSC_COARSE_DIR,Coarse adjustment direction. If output is greater than 12.5 0 - Coarse adjustment decreases frequency 1 - Coarse adjustment increases frequency" "0: Coarse adjustment decreases frequency 1,?" newline bitfld.long 0x0 3.--5. "RC12M_OSC_TRIM_TRIMOSC_COARSE,Coarse adjustment. Frequency is decreased or increased by 1.25 MHz per value based on the trimosc_coarse_dir value." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RC12M_OSC_TRIM_TRIMOSC_FINE,Fine adjustment. Decreases the frequency by 250 KHz per value." "0,1,2,3,4,5,6,7" rgroup.long 0x8050++0x3 line.long 0x0 "CFG0_MCU_PLL_CLKSEL," bitfld.long 0x0 31. "MCU_PLL_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a mcu_reset_z for MCU PLL[2:0]. This bit must not be set until after the corresponding byp_warm_rst bit has been cleared.." "0,1" newline bitfld.long 0x0 23. "MCU_PLL_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when an MCU warm reset occurs and will keep MCU PLL[2:0] in bypass mode.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x0 8. "MCU_PLL_CLKSEL_CLKLOSS_SWTCH_EN,When set enables automatic switching of MCU PLL[2:0] clock source to CLK_12M_RC if HFOSC0 clock loss is detected" "0,1" rgroup.long 0x8060++0x7 line.long 0x0 "CFG0_WKUP_PER_CLKSEL," bitfld.long 0x0 0. "WKUP_PER_CLKSEL_MCUPLL_BYPASS,Select the main oscillator clock rather than the PLL generated clock as the functional clock (PLL BYPASS mode). 1'b0: WKUP_I2C functional clock is MCU_PLL1_HSDIV3_CLKOUT WKUP_USART functional clock is MCU_PLL1_HSDIV3_CLKOUT.." "0: WKUP_I2C functional clock is..,1: WKUP_I2C functional clock is HFOSC0_CLKOUT.." line.long 0x4 "CFG0_WKUP_USART_CLKSEL," bitfld.long 0x4 0. "WKUP_USART_CLKSEL_CLK_SEL,WKUP_USART0 FCLK selection 1'b0 - MCU_PLL1_HSDIV3_CLKOUT 1'b1 - MAIN_PLL_HSDIV5_CLKOUT" "0: MCU_PLL1_HSDIV3_CLKOUT 1'b1,?" rgroup.long 0x8070++0x3 line.long 0x0 "CFG0_WKUP_GPIO_CLKSEL," bitfld.long 0x0 0.--1. "WKUP_GPIO_CLKSEL_WAKE_CLK_SEL,WKUP_GPIO clock selection. Must be set to MCU_SYSCLK0/4 whenever WKUP_GPIO VBUS interface is enabled. Other clock source may be selected as a wake up clock for DeepSleep modes after WKUP_GPIO is gated off through LPSC." "0: MCU_SYSCLK0 / 8 2'b01,?,2: CLK_32K 2'b11,?" rgroup.long 0x8080++0x27 line.long 0x0 "CFG0_MAIN_PLL0_CLKSEL," bitfld.long 0x0 31. "MAIN_PLL0_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL0. This bit must not be set until after the corresponding byp_warm_rst bit has been cleared.." "0,1" newline bitfld.long 0x0 23. "MAIN_PLL0_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL0 in bypass mode.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x0 0. "MAIN_PLL0_CLKSEL_CLK_SEL,Selects the clock source for MAIN PLL0 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0x4 "CFG0_MAIN_PLL1_CLKSEL," bitfld.long 0x4 31. "MAIN_PLL1_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL1 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled." "0,1" newline bitfld.long 0x4 23. "MAIN_PLL1_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is cleared to 1'b0 when a MAIN warm reset occurs which will cause MAIN PLL1 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behavior. Because.." "0,1" newline bitfld.long 0x4 0. "MAIN_PLL1_CLKSEL_CLK_SEL,Selects the clock source for MAIN PLL1 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0x8 "CFG0_MAIN_PLL2_CLKSEL," bitfld.long 0x8 31. "MAIN_PLL2_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL2 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled." "0,1" newline bitfld.long 0x8 23. "MAIN_PLL2_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is cleared to 1'b0 when a MAIN warm reset occurs which will cause MAIN PLL2 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behavior. Because.." "0,1" newline bitfld.long 0x8 0. "MAIN_PLL2_CLKSEL_CLK_SEL,Selects the clock source for MAIN PLL2 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0xC "CFG0_MAIN_PLL3_CLKSEL," bitfld.long 0xC 31. "MAIN_PLL3_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL3 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled." "0,1" newline bitfld.long 0xC 23. "MAIN_PLL3_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is cleared to 1'b0 when a MAIN warm reset occurs which will cause MAIN PLL3 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behavior. Because.." "0,1" newline bitfld.long 0xC 0. "MAIN_PLL3_CLKSEL_CLK_SEL,Selects the clock source for MAIN PLL3 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0x10 "CFG0_MAIN_PLL4_CLKSEL," bitfld.long 0x10 31. "MAIN_PLL4_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL4. This bit must not be set until after the corresponding byp_warm_rst bit has been cleared.." "0,1" newline bitfld.long 0x10 23. "MAIN_PLL4_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL4 in bypass mode.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x10 4. "MAIN_PLL4_CLKSEL_XREF_SEL,Selects the alternate clock source for MAIN PLL4 1'b0 - Use HFOSC0_CLKOUT or HFOSC1 CLKOUT as selected by clk_sel bit 1'b1 - Use EXT_REFCLK1" "0: Use HFOSC0_CLKOUT or HFOSC1 CLKOUT as selected..,?" newline bitfld.long 0x10 0. "MAIN_PLL4_CLKSEL_CLK_SEL,Selects the clock source for MAIN PLL4 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0x14 "CFG0_MAIN_PLL5_CLKSEL," bitfld.long 0x14 31. "MAIN_PLL5_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL5. This bit must not be set until after the corresponding byp_warm_rst bit has been cleared.." "0,1" newline bitfld.long 0x14 23. "MAIN_PLL5_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL5 in bypass mode.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x14 0. "MAIN_PLL5_CLKSEL_CLK_SEL,Selects the clock source for MAIN PLL5 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0x18 "CFG0_MAIN_PLL6_CLKSEL," bitfld.long 0x18 31. "MAIN_PLL6_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL6. This bit must not be set until after the corresponding byp_warm_rst bit has been cleared.." "0,1" newline bitfld.long 0x18 23. "MAIN_PLL6_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL6 in bypass mode.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x18 0. "MAIN_PLL6_CLKSEL_CLK_SEL,Selects the clock source for MAIN PLL6 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0x1C "CFG0_MAIN_PLL7_CLKSEL," bitfld.long 0x1C 31. "MAIN_PLL7_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL7. This bit must not be set until after the corresponding byp_warm_rst bit has been cleared.." "0,1" newline bitfld.long 0x1C 23. "MAIN_PLL7_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL7 in bypass mode.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x1C 0. "MAIN_PLL7_CLKSEL_CLK_SEL,Selects the clock source for MAIN PLL7 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0x20 "CFG0_MAIN_PLL8_CLKSEL," bitfld.long 0x20 31. "MAIN_PLL8_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL8. This bit must not be set until after the corresponding byp_warm_rst bit has been cleared.." "0,1" newline bitfld.long 0x20 23. "MAIN_PLL8_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL8 in bypass mode.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x20 0. "MAIN_PLL8_CLKSEL_CLK_SEL,Selects the clock source for MAIN PLL8 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0x24 "CFG0_MAIN_PLL9_CLKSEL," bitfld.long 0x24 31. "MAIN_PLL9_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL9. This bit must not be set until after the corresponding byp_warm_rst bit has been cleared.." "0,1" newline bitfld.long 0x24 23. "MAIN_PLL9_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL9 in bypass mode.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x24 0. "MAIN_PLL9_CLKSEL_CLK_SEL,Selects the clock source for MAIN PLL9 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" rgroup.long 0x80B0++0x3 line.long 0x0 "CFG0_MAIN_PLL12_CLKSEL," bitfld.long 0x0 31. "MAIN_PLL12_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL12. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x0 23. "MAIN_PLL12_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL12 in bypass mode.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x0 0. "MAIN_PLL12_CLKSEL_CLK_SEL,Selects the clock source for MAIN PLL12 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" rgroup.long 0x80B8++0x3 line.long 0x0 "CFG0_MAIN_PLL14_CLKSEL," bitfld.long 0x0 31. "MAIN_PLL14_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL14. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x0 23. "MAIN_PLL14_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL14 in bypass mode.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x0 0. "MAIN_PLL14_CLKSEL_CLK_SEL,Selects the clock source for MAIN PLL14 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" rgroup.long 0x80C0++0x7 line.long 0x0 "CFG0_MAIN_PLL16_CLKSEL," bitfld.long 0x0 31. "MAIN_PLL16_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL16 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled." "0,1" newline bitfld.long 0x0 23. "MAIN_PLL16_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is cleared to 1'b0 when a MAIN warm reset occurs which will cause MAIN PLL16 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behavior. Because.." "0,1" newline bitfld.long 0x0 0. "MAIN_PLL16_CLKSEL_CLK_SEL,Selects the clock source for MAIN PLL16 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0x4 "CFG0_MAIN_PLL17_CLKSEL," bitfld.long 0x4 31. "MAIN_PLL17_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL17 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled." "0,1" newline bitfld.long 0x4 23. "MAIN_PLL17_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is cleared to 1'b0 when a MAIN warm reset occurs which will cause MAIN PLL17 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behavior. Because.." "0,1" newline bitfld.long 0x4 0. "MAIN_PLL17_CLKSEL_CLK_SEL,Selects the clock source for MAIN PLL17 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" rgroup.long 0x80CC++0x3 line.long 0x0 "CFG0_MAIN_PLL19_CLKSEL," bitfld.long 0x0 31. "MAIN_PLL19_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL19 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled." "0,1" newline bitfld.long 0x0 23. "MAIN_PLL19_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is cleared to 1'b0 when a MAIN warm reset occurs which will cause MAIN PLL19 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behavior. Because.." "0,1" newline bitfld.long 0x0 0. "MAIN_PLL19_CLKSEL_CLK_SEL,Selects the clock source for MAIN PLL19 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" rgroup.long 0x80E4++0xF line.long 0x0 "CFG0_MAIN_PLL25_CLKSEL," bitfld.long 0x0 31. "MAIN_PLL25_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL25. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x0 23. "MAIN_PLL25_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL25 in bypass mode.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x0 0. "MAIN_PLL25_CLKSEL_CLK_SEL,Selects the clock source for MAIN PLL25 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0x4 "CFG0_MAIN_PLL26_CLKSEL," bitfld.long 0x4 31. "MAIN_PLL26_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL26. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x4 23. "MAIN_PLL26_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL26 in bypass mode.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x4 0. "MAIN_PLL26_CLKSEL_CLK_SEL,Selects the clock source for MAIN PLL26 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0x8 "CFG0_MAIN_PLL27_CLKSEL," bitfld.long 0x8 31. "MAIN_PLL27_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL27. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x8 23. "MAIN_PLL27_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL27 in bypass mode.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x8 0. "MAIN_PLL27_CLKSEL_CLK_SEL,Selects the clock source for MAIN PLL27 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0xC "CFG0_MAIN_PLL28_CLKSEL," bitfld.long 0xC 31. "MAIN_PLL28_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL28. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0xC 23. "MAIN_PLL28_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL28 in bypass mode.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0xC 0. "MAIN_PLL28_CLKSEL_CLK_SEL,Selects the clock source for MAIN PLL28 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" rgroup.long 0x8100++0x3 line.long 0x0 "CFG0_MAIN_SYSCLK_CTRL," bitfld.long 0x0 8. "MAIN_SYSCLK_CTRL_SYSCLK1_GATE,When set gates off SYSCLK1 output of the MAIN PLL Controller" "0,1" newline bitfld.long 0x0 0. "MAIN_SYSCLK_CTRL_SYSCLK0_GATE,When set gates off SYSCLK0 (MCLK1) output of the MAIN PLL Controller" "0,1" rgroup.long 0x8110++0x7 line.long 0x0 "CFG0_MCU_SPI0_CLKSEL," bitfld.long 0x0 16. "MCU_SPI0_CLKSEL_MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection 1'b0 - Internal clock loopback 1'b1 - Loopback from pad" "0: Internal clock loopback 1'b1,?" line.long 0x4 "CFG0_MCU_SPI1_CLKSEL," bitfld.long 0x4 16. "MCU_SPI1_CLKSEL_MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection 1'b0 - Internal clock loopback 1'b1 - Loopback from pad" "0: Internal clock loopback 1'b1,?" rgroup.long 0x9008++0x7 line.long 0x0 "CFG0_LOCK2_KICK0," hexmask.long 0x0 0.--31. 1. "LOCK2_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK2_KICK1," hexmask.long 0x4 0.--31. 1. "LOCK2_KICK1,- KICK1 component" rgroup.long 0x9100++0xB line.long 0x0 "CFG0_CLAIMREG_P2_R0_READONLY," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P2_R0_READONLY,Claim bits for Partition 2" line.long 0x4 "CFG0_CLAIMREG_P2_R1_READONLY," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P2_R1_READONLY,Claim bits for Partition 2" line.long 0x8 "CFG0_CLAIMREG_P2_R2_READONLY," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P2_R2_READONLY,Claim bits for Partition 2" rgroup.long 0xA000++0x3 line.long 0x0 "CFG0_MCU_OBSCLK_CTRL_PROXY," bitfld.long 0x0 24. "MCU_OBSCLK_CTRL_OUT_MUX_SEL_PROXY,MCU_OBSCLK pin output mux selection. Note when HFOSC0_CLK is selected (1'b1) the MCU_OBSCLK_CTRL_clk_sel field must be programmed to 4'b0001. 1'b0 - The output of the MCU_OBSCLK output divider is output on the pin.." "0: The output of the MCU_OBSCLK output divider is..,?" newline bitfld.long 0x0 16. "MCU_OBSCLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the OBSCLK divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed." "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "MCU_OBSCLK_CTRL_CLK_DIV_PROXY,MCU_OBSCLK pin clock selection output divider Output clock is divided by clk_div+1" newline hexmask.long.byte 0x0 0.--3. 1. "MCU_OBSCLK_CTRL_CLK_SEL_PROXY,MCU_OBSCLK pin clock selection Field values (others are reserved): 4'b0000 - CLK_12M_RC 4'b0001 - '0' 4'b0010 - MCU_PLL0_HSDIV0_CLKOUT 4'b0011 - MCU_PLLCTL_OBSCLK 4'b0100 - MCU_PLL1_HSDIV1_CLKOUT 4'b0101 -.." rgroup.long 0xA014++0xB line.long 0x0 "CFG0_HFOSC1_CTRL_PROXY," bitfld.long 0x0 7. "HFOSC1_CTRL_PD_C_PROXY,Oscillator powerdown control. When set oscillator is disabled. Oscillator output is tristated if bp_c=0" "0,1" newline bitfld.long 0x0 4. "HFOSC1_CTRL_BP_C_PROXY,Oscillator bypass control. When set oscillator is in bypass mode" "0,1" line.long 0x4 "CFG0_HFOSC0_TRIM_PROXY," bitfld.long 0x4 31. "HFOSC0_TRIM_TRIM_EN_PROXY,Apply MMR values to OSC trim inputs instead of tie-offs" "0,1" newline bitfld.long 0x4 24.--25. "HFOSC0_TRIM_FREQ_RNG_PROXY,Sets the frequency range of operation based on: I(MIRRBIAS) = I(AGC) + 4x I(BIAS) (I(BIAS) : Bias current to AMP_AGC Block I(AGC) : Current from AGC Loop and mirrored)" "0,1,2,3" newline bitfld.long 0x4 20.--21. "HFOSC0_TRIM_HYST_PROXY,Sets comparator hysteresis" "0,1,2,3" newline bitfld.long 0x4 16.--18. "HFOSC0_TRIM_I_MULT_PROXY,AGC AMP current multiplication gain I(MIRRBIAS) = I(AGC) + 4x I(BIAS) (I(BIAS) : Bias current to AMP_AGC Block I(AGC) : Current from AGC Loop and mirrored)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--13. 1. "HFOSC0_TRIM_R_REF_PROXY,Sets the AMP AGC bias current r_ref(5:3) are not used." newline hexmask.long.byte 0x4 4.--7. 1. "HFOSC0_TRIM_I_IBIAS_COMP_PROXY,Sets the COMP bias current x = 1 uA" newline hexmask.long.byte 0x4 0.--3. 1. "HFOSC0_TRIM_R_IBIAS_REF_PROXY,Sets the base IBIAS reference" line.long 0x8 "CFG0_HFOSC1_TRIM_PROXY," bitfld.long 0x8 31. "HFOSC1_TRIM_TRIM_EN_PROXY,Apply MMR values to OSC trim inputs instead of tie-offs" "0,1" newline bitfld.long 0x8 24.--25. "HFOSC1_TRIM_FREQ_RNG_PROXY,Sets the frequency range of operation based on: I(MIRRBIAS) = I(AGC) + 4x I(BIAS) (I(BIAS) : Bias current to AMP_AGC Block I(AGC) : Current from AGC Loop and mirrored)" "0,1,2,3" newline bitfld.long 0x8 20.--21. "HFOSC1_TRIM_HYST_PROXY,Sets comparator hysteresis" "0,1,2,3" newline bitfld.long 0x8 16.--18. "HFOSC1_TRIM_I_MULT_PROXY,AGC AMP current multiplication gain I(MIRRBIAS) = I(AGC) + 4x I(BIAS) (I(BIAS) : Bias current to AMP_AGC Block I(AGC) : Current from AGC Loop and mirrored)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--13. 1. "HFOSC1_TRIM_R_REF_PROXY,Sets the AMP AGC bias current r_ref(5:3) are not used." newline hexmask.long.byte 0x8 4.--7. 1. "HFOSC1_TRIM_I_IBIAS_COMP_PROXY,Sets the COMP bias current x = 1 uA" newline hexmask.long.byte 0x8 0.--3. 1. "HFOSC1_TRIM_R_IBIAS_REF_PROXY,Sets the base IBIAS reference" rgroup.long 0xA024++0x3 line.long 0x0 "CFG0_RC12M_OSC_TRIM_PROXY," bitfld.long 0x0 6. "RC12M_OSC_TRIM_TRIMOSC_COARSE_DIR_PROXY,Coarse adjustment direction. If output is greater than 12.5 0 - Coarse adjustment decreases frequency 1 - Coarse adjustment increases frequency" "0: Coarse adjustment decreases frequency 1,?" newline bitfld.long 0x0 3.--5. "RC12M_OSC_TRIM_TRIMOSC_COARSE_PROXY,Coarse adjustment. Frequency is decreased or increased by 1.25 MHz per value based on the trimosc_coarse_dir value." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RC12M_OSC_TRIM_TRIMOSC_FINE_PROXY,Fine adjustment. Decreases the frequency by 250 KHz per value." "0,1,2,3,4,5,6,7" rgroup.long 0xA050++0x3 line.long 0x0 "CFG0_MCU_PLL_CLKSEL_PROXY," bitfld.long 0x0 31. "MCU_PLL_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a mcu_reset_z for MCU PLL[2:0]. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x0 23. "MCU_PLL_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when an MCU warm reset occurs and will keep MCU PLL[2:0] in bypass.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x0 8. "MCU_PLL_CLKSEL_CLKLOSS_SWTCH_EN_PROXY,When set enables automatic switching of MCU PLL[2:0] clock source to CLK_12M_RC if HFOSC0 clock loss is detected" "0,1" rgroup.long 0xA060++0x7 line.long 0x0 "CFG0_WKUP_PER_CLKSEL_PROXY," bitfld.long 0x0 0. "WKUP_PER_CLKSEL_MCUPLL_BYPASS_PROXY,Select the main oscillator clock rather than the PLL generated clock as the functional clock (PLL BYPASS mode). 1'b0: WKUP_I2C functional clock is MCU_PLL1_HSDIV3_CLKOUT WKUP_USART functional clock is.." "0: WKUP_I2C functional clock is..,1: WKUP_I2C functional clock is HFOSC0_CLKOUT.." line.long 0x4 "CFG0_WKUP_USART_CLKSEL_PROXY," bitfld.long 0x4 0. "WKUP_USART_CLKSEL_CLK_SEL_PROXY,WKUP_USART0 FCLK selection 1'b0 - MCU_PLL1_HSDIV3_CLKOUT 1'b1 - MAIN_PLL_HSDIV5_CLKOUT" "0: MCU_PLL1_HSDIV3_CLKOUT 1'b1,?" rgroup.long 0xA070++0x3 line.long 0x0 "CFG0_WKUP_GPIO_CLKSEL_PROXY," bitfld.long 0x0 0.--1. "WKUP_GPIO_CLKSEL_WAKE_CLK_SEL_PROXY,WKUP_GPIO clock selection. Must be set to MCU_SYSCLK0/4 whenever WKUP_GPIO VBUS interface is enabled. Other clock source may be selected as a wake up clock for DeepSleep modes after WKUP_GPIO is gated off through.." "0: MCU_SYSCLK0 / 8 2'b01,?,2: CLK_32K 2'b11,?" rgroup.long 0xA080++0x27 line.long 0x0 "CFG0_MAIN_PLL0_CLKSEL_PROXY," bitfld.long 0x0 31. "MAIN_PLL0_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL0. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x0 23. "MAIN_PLL0_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL0 in bypass.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x0 0. "MAIN_PLL0_CLKSEL_CLK_SEL_PROXY,Selects the clock source for MAIN PLL0 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0x4 "CFG0_MAIN_PLL1_CLKSEL_PROXY," bitfld.long 0x4 31. "MAIN_PLL1_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL1 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled." "0,1" newline bitfld.long 0x4 23. "MAIN_PLL1_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is cleared to 1'b0 when a MAIN warm reset occurs which will cause MAIN PLL1 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behavior." "0,1" newline bitfld.long 0x4 0. "MAIN_PLL1_CLKSEL_CLK_SEL_PROXY,Selects the clock source for MAIN PLL1 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0x8 "CFG0_MAIN_PLL2_CLKSEL_PROXY," bitfld.long 0x8 31. "MAIN_PLL2_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL2 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled." "0,1" newline bitfld.long 0x8 23. "MAIN_PLL2_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is cleared to 1'b0 when a MAIN warm reset occurs which will cause MAIN PLL2 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behavior." "0,1" newline bitfld.long 0x8 0. "MAIN_PLL2_CLKSEL_CLK_SEL_PROXY,Selects the clock source for MAIN PLL2 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0xC "CFG0_MAIN_PLL3_CLKSEL_PROXY," bitfld.long 0xC 31. "MAIN_PLL3_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL3 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled." "0,1" newline bitfld.long 0xC 23. "MAIN_PLL3_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is cleared to 1'b0 when a MAIN warm reset occurs which will cause MAIN PLL3 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behavior." "0,1" newline bitfld.long 0xC 0. "MAIN_PLL3_CLKSEL_CLK_SEL_PROXY,Selects the clock source for MAIN PLL3 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0x10 "CFG0_MAIN_PLL4_CLKSEL_PROXY," bitfld.long 0x10 31. "MAIN_PLL4_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL4. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x10 23. "MAIN_PLL4_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL4 in bypass.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x10 4. "MAIN_PLL4_CLKSEL_XREF_SEL_PROXY,Selects the alternate clock source for MAIN PLL4 1'b0 - Use HFOSC0_CLKOUT or HFOSC1 CLKOUT as selected by clk_sel bit 1'b1 - Use EXT_REFCLK1" "0: Use HFOSC0_CLKOUT or HFOSC1 CLKOUT as selected..,?" newline bitfld.long 0x10 0. "MAIN_PLL4_CLKSEL_CLK_SEL_PROXY,Selects the clock source for MAIN PLL4 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0x14 "CFG0_MAIN_PLL5_CLKSEL_PROXY," bitfld.long 0x14 31. "MAIN_PLL5_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL5. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x14 23. "MAIN_PLL5_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL5 in bypass.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x14 0. "MAIN_PLL5_CLKSEL_CLK_SEL_PROXY,Selects the clock source for MAIN PLL5 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0x18 "CFG0_MAIN_PLL6_CLKSEL_PROXY," bitfld.long 0x18 31. "MAIN_PLL6_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL6. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x18 23. "MAIN_PLL6_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL6 in bypass.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x18 0. "MAIN_PLL6_CLKSEL_CLK_SEL_PROXY,Selects the clock source for MAIN PLL6 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0x1C "CFG0_MAIN_PLL7_CLKSEL_PROXY," bitfld.long 0x1C 31. "MAIN_PLL7_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL7. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x1C 23. "MAIN_PLL7_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL7 in bypass.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x1C 0. "MAIN_PLL7_CLKSEL_CLK_SEL_PROXY,Selects the clock source for MAIN PLL7 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0x20 "CFG0_MAIN_PLL8_CLKSEL_PROXY," bitfld.long 0x20 31. "MAIN_PLL8_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL8. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x20 23. "MAIN_PLL8_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL8 in bypass.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x20 0. "MAIN_PLL8_CLKSEL_CLK_SEL_PROXY,Selects the clock source for MAIN PLL8 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0x24 "CFG0_MAIN_PLL9_CLKSEL_PROXY," bitfld.long 0x24 31. "MAIN_PLL9_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL9. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x24 23. "MAIN_PLL9_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL9 in bypass.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x24 0. "MAIN_PLL9_CLKSEL_CLK_SEL_PROXY,Selects the clock source for MAIN PLL9 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" rgroup.long 0xA0B0++0x3 line.long 0x0 "CFG0_MAIN_PLL12_CLKSEL_PROXY," bitfld.long 0x0 31. "MAIN_PLL12_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL12. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x0 23. "MAIN_PLL12_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL12 in bypass.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x0 0. "MAIN_PLL12_CLKSEL_CLK_SEL_PROXY,Selects the clock source for MAIN PLL12 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" rgroup.long 0xA0B8++0x3 line.long 0x0 "CFG0_MAIN_PLL14_CLKSEL_PROXY," bitfld.long 0x0 31. "MAIN_PLL14_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL14. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x0 23. "MAIN_PLL14_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL14 in bypass.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x0 0. "MAIN_PLL14_CLKSEL_CLK_SEL_PROXY,Selects the clock source for MAIN PLL14 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" rgroup.long 0xA0C0++0x7 line.long 0x0 "CFG0_MAIN_PLL16_CLKSEL_PROXY," bitfld.long 0x0 31. "MAIN_PLL16_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL16 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled." "0,1" newline bitfld.long 0x0 23. "MAIN_PLL16_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is cleared to 1'b0 when a MAIN warm reset occurs which will cause MAIN PLL16 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behavior." "0,1" newline bitfld.long 0x0 0. "MAIN_PLL16_CLKSEL_CLK_SEL_PROXY,Selects the clock source for MAIN PLL16 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0x4 "CFG0_MAIN_PLL17_CLKSEL_PROXY," bitfld.long 0x4 31. "MAIN_PLL17_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL17 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled." "0,1" newline bitfld.long 0x4 23. "MAIN_PLL17_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is cleared to 1'b0 when a MAIN warm reset occurs which will cause MAIN PLL17 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behavior." "0,1" newline bitfld.long 0x4 0. "MAIN_PLL17_CLKSEL_CLK_SEL_PROXY,Selects the clock source for MAIN PLL17 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" rgroup.long 0xA0CC++0x3 line.long 0x0 "CFG0_MAIN_PLL19_CLKSEL_PROXY," bitfld.long 0x0 31. "MAIN_PLL19_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL19 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled." "0,1" newline bitfld.long 0x0 23. "MAIN_PLL19_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is cleared to 1'b0 when a MAIN warm reset occurs which will cause MAIN PLL19 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behavior." "0,1" newline bitfld.long 0x0 0. "MAIN_PLL19_CLKSEL_CLK_SEL_PROXY,Selects the clock source for MAIN PLL19 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" rgroup.long 0xA0E4++0xF line.long 0x0 "CFG0_MAIN_PLL25_CLKSEL_PROXY," bitfld.long 0x0 31. "MAIN_PLL25_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL25. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x0 23. "MAIN_PLL25_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL25 in bypass.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x0 0. "MAIN_PLL25_CLKSEL_CLK_SEL_PROXY,Selects the clock source for MAIN PLL25 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0x4 "CFG0_MAIN_PLL26_CLKSEL_PROXY," bitfld.long 0x4 31. "MAIN_PLL26_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL26. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x4 23. "MAIN_PLL26_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL26 in bypass.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x4 0. "MAIN_PLL26_CLKSEL_CLK_SEL_PROXY,Selects the clock source for MAIN PLL26 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0x8 "CFG0_MAIN_PLL27_CLKSEL_PROXY," bitfld.long 0x8 31. "MAIN_PLL27_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL27. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x8 23. "MAIN_PLL27_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL27 in bypass.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x8 0. "MAIN_PLL27_CLKSEL_CLK_SEL_PROXY,Selects the clock source for MAIN PLL27 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" line.long 0xC "CFG0_MAIN_PLL28_CLKSEL_PROXY," bitfld.long 0xC 31. "MAIN_PLL28_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set enables software control of exit from bypass mode on a main_reset_z for MAIN PLL28. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0xC 23. "MAIN_PLL28_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL28 in bypass.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0xC 0. "MAIN_PLL28_CLKSEL_CLK_SEL_PROXY,Selects the clock source for MAIN PLL28 1'b0 - Use HFOSC0_CLKOUT 1'b1 - Use HFOSC1_CLKOUT" "0: Use HFOSC0_CLKOUT 1'b1,?" rgroup.long 0xA100++0x3 line.long 0x0 "CFG0_MAIN_SYSCLK_CTRL_PROXY," bitfld.long 0x0 8. "MAIN_SYSCLK_CTRL_SYSCLK1_GATE_PROXY,When set gates off SYSCLK1 output of the MAIN PLL Controller" "0,1" newline bitfld.long 0x0 0. "MAIN_SYSCLK_CTRL_SYSCLK0_GATE_PROXY,When set gates off SYSCLK0 (MCLK1) output of the MAIN PLL Controller" "0,1" rgroup.long 0xA110++0x7 line.long 0x0 "CFG0_MCU_SPI0_CLKSEL_PROXY," bitfld.long 0x0 16. "MCU_SPI0_CLKSEL_MSTR_LB_CLKSEL_PROXY,Master mode receive capture clock loopback selection 1'b0 - Internal clock loopback 1'b1 - Loopback from pad" "0: Internal clock loopback 1'b1,?" line.long 0x4 "CFG0_MCU_SPI1_CLKSEL_PROXY," bitfld.long 0x4 16. "MCU_SPI1_CLKSEL_MSTR_LB_CLKSEL_PROXY,Master mode receive capture clock loopback selection 1'b0 - Internal clock loopback 1'b1 - Loopback from pad" "0: Internal clock loopback 1'b1,?" rgroup.long 0xB008++0x7 line.long 0x0 "CFG0_LOCK2_KICK0_PROXY," hexmask.long 0x0 0.--31. 1. "LOCK2_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK2_KICK1_PROXY," hexmask.long 0x4 0.--31. 1. "LOCK2_KICK1_PROXY,- KICK1 component" rgroup.long 0xB100++0xB line.long 0x0 "CFG0_CLAIMREG_P2_R0," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P2_R0,Claim bits for Partition 2" line.long 0x4 "CFG0_CLAIMREG_P2_R1," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P2_R1,Claim bits for Partition 2" line.long 0x8 "CFG0_CLAIMREG_P2_R2," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P2_R2,Claim bits for Partition 2" rgroup.long 0xC000++0x1B line.long 0x0 "CFG0_SMS_LBIST_CTRL," bitfld.long 0x0 31. "SMS_LBIST_CTRL_BIST_RESET,(Active low) This bitfield is not used. The bist_reset control for SMS is generated by the POST state machine. The bitfield still reflects the efuse value." "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "SMS_LBIST_CTRL_BIST_RUN,This bitfield is not used. The bist_run control for SMS is generated by the POST state machine. The bitfield still reflects the efuse value." newline hexmask.long.byte 0x0 12.--15. 1. "SMS_LBIST_CTRL_RUNBIST_MODE,Runbist mode enable if all bits are 1" newline bitfld.long 0x0 8.--9. "SMS_LBIST_CTRL_DC_DEF,Clock delay after scan_enable switching" "0,1,2,3" line.long 0x4 "CFG0_SMS_LBIST_PATCOUNT," hexmask.long.word 0x4 16.--29. 1. "SMS_LBIST_PATCOUNT_STATIC_PC_DEF,Number of stuck-at patterns to run" newline hexmask.long.byte 0x4 8.--11. 1. "SMS_LBIST_PATCOUNT_SET_PC_DEF,Number of set patterns to run" newline hexmask.long.byte 0x4 4.--7. 1. "SMS_LBIST_PATCOUNT_RESET_PC_DEF,Number of reset patterns to run" newline hexmask.long.byte 0x4 0.--3. 1. "SMS_LBIST_PATCOUNT_SCAN_PC_DEF,Number of chain test patterns to run" line.long 0x8 "CFG0_SMS_LBIST_SEED0," hexmask.long 0x8 0.--31. 1. "SMS_LBIST_SEED0_PRPG_DEF,Initial seed for PRPG (bits 31:0)" line.long 0xC "CFG0_SMS_LBIST_SEED1," hexmask.long.tbyte 0xC 0.--20. 1. "SMS_LBIST_SEED1_PRPG_DEF,Initial seed for PRPG (bits 52:32)" line.long 0x10 "CFG0_SMS_LBIST_SPARE0," hexmask.long 0x10 0.--31. 1. "SMS_LBIST_SPARE0_SPARE0,LBIST spare bits" line.long 0x14 "CFG0_SMS_LBIST_SPARE1," hexmask.long 0x14 0.--31. 1. "SMS_LBIST_SPARE1_SPARE1,LBIST spare bits" line.long 0x18 "CFG0_SMS_LBIST_STAT," rbitfld.long 0x18 31. "SMS_LBIST_STAT_BIST_DONE,LBIST is done" "0,1" newline rbitfld.long 0x18 15. "SMS_LBIST_STAT_BIST_RUNNING,LBIST is running" "0,1" newline bitfld.long 0x18 8.--9. "SMS_LBIST_STAT_OUT_MUX_CTL,Selects source of LBIST output 00 - LBIST IP PID value 01 - LBIST CTRL ID value 1x - MISR value" "0: LBIST IP PID value 01,?,?,?" newline hexmask.long.byte 0x18 0.--7. 1. "SMS_LBIST_STAT_MISR_MUX_CTL,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR." rgroup.long 0xC01C++0x3 line.long 0x0 "CFG0_SMS_LBIST_MISR," hexmask.long 0x0 0.--31. 1. "SMS_LBIST_MISR_MISR_RESULT,32-bits of MISR value selected by misr_mux_ctl" rgroup.long 0xC280++0x3 line.long 0x0 "CFG0_SMS_LBIST_SIG," hexmask.long 0x0 0.--31. 1. "SMS_LBIST_SIG_MISR_SIG,MISR signature" rgroup.long 0xC2C0++0x7 line.long 0x0 "CFG0_WKUP_POST_STAT," bitfld.long 0x0 17. "WKUP_POST_STAT_FPOST_PLL_LOCK_TIMEOUT,Indicates PLL lock timeout for Fast POST mode operation. 0 - PLLs locked Fast POST mode was entered 1 - PLLs lock timeout occurred. Slow speed POST was performed" "0: PLLs locked,1: PLLs lock timeout occurred" newline bitfld.long 0x0 16. "WKUP_POST_STAT_FPOST_PLL_LOCKLOSS,Indicates if PLL lock was lost during POST 0 - No PLL lock loss. Fast POST was executed 1 - PLL lock was lost. POST was terminated" "0: No PLL lock loss,1: PLL lock was lost" newline bitfld.long 0x0 15. "WKUP_POST_STAT_POST_MCU_PBIST_FAIL,MCU PBIST failed" "0,1" newline bitfld.long 0x0 9. "WKUP_POST_STAT_POST_MCU_PBIST_TIMEOUT,MCU PBIST timed out" "0,1" newline bitfld.long 0x0 8. "WKUP_POST_STAT_POST_MCU_PBIST_DONE,MCU PBIST done" "0,1" newline bitfld.long 0x0 5. "WKUP_POST_STAT_POST_MCU_LBIST_TIMEOUT,MCU LBIST timed out" "0,1" newline bitfld.long 0x0 4. "WKUP_POST_STAT_POST_SMS_LBIST_TIMEOUT,SMS LBIST timed out" "0,1" newline bitfld.long 0x0 1. "WKUP_POST_STAT_POST_MCU_LBIST_DONE,MCU LBIST done" "0,1" newline bitfld.long 0x0 0. "WKUP_POST_STAT_POST_SMS_LBIST_DONE,SMS LBIST done" "0,1" line.long 0x4 "CFG0_WKUP_POST_CFG0," bitfld.long 0x4 31. "WKUP_POST_CFG0_FAST_POST_EN,Enable Fast POST mode" "0,1" newline bitfld.long 0x4 28.--30. "WKUP_POST_CFG0_POST_DIV2,Fast POST PLL secondary post-divider value" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 24.--26. "WKUP_POST_CFG0_POST_DIV1,Fast POST PLL primary post-divider value" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--21. 1. "WKUP_POST_CFG0_REF_DIV,Fast POST PLL reference clock pre-divider value" newline hexmask.long.word 0x4 0.--11. 1. "WKUP_POST_CFG0_FB_DIV_INT,Fast POST PLL feedback divider (integer portion) value" rgroup.long 0xC2CC++0x3 line.long 0x0 "CFG0_WKUP_POST_CFG1," bitfld.long 0x0 31. "WKUP_POST_CFG1_FAST_POST_EN,Enable Fast POST mode" "0,1" newline bitfld.long 0x0 28.--30. "WKUP_POST_CFG1_POST_DIV2,Fast POST PLL secondary post-divider value" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "WKUP_POST_CFG1_POST_DIV1,Fast POST PLL primary post-divider value" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--21. 1. "WKUP_POST_CFG1_REF_DIV,Fast POST PLL reference clock pre-divider value" newline hexmask.long.word 0x0 0.--11. 1. "WKUP_POST_CFG1_FB_DIV_INT,Fast POST PLL feedback divider (integer portion) value" rgroup.long 0xC300++0x3 line.long 0x0 "CFG0_WKUP_FUSE_CRC_CTRL," bitfld.long 0x0 2. "WKUP_FUSE_CRC_CTRL_CRC_EN_2,Enable eFuse CRC error output for chain 2" "0,1" newline bitfld.long 0x0 1. "WKUP_FUSE_CRC_CTRL_CRC_EN_1,Enable eFuse CRC error output for chain 1" "0,1" rgroup.long 0xC304++0x7 line.long 0x0 "CFG0_WKUP_CHAIN1_CRC_FUSE," hexmask.long 0x0 0.--31. 1. "WKUP_CHAIN1_CRC_FUSE_CRC,Stored chain CRC" line.long 0x4 "CFG0_WKUP_CHAIN2_CRC_FUSE," hexmask.long 0x4 0.--31. 1. "WKUP_CHAIN2_CRC_FUSE_CRC,Stored chain CRC" rgroup.long 0xC320++0xB line.long 0x0 "CFG0_WKUP_FUSE_CRC_STAT," bitfld.long 0x0 31. "WKUP_FUSE_CRC_STAT_AUTOLD_ERR,Indicates eFuse autoload or programmation error on any chain" "0,1" newline bitfld.long 0x0 2. "WKUP_FUSE_CRC_STAT_CRC_ERR_2,Indicates eFuse CRC error on chain 2" "0,1" newline bitfld.long 0x0 1. "WKUP_FUSE_CRC_STAT_CRC_ERR_1,Indicates eFuse CRC error on chain 1" "0,1" line.long 0x4 "CFG0_WKUP_CHAIN1_CRC_CALC," hexmask.long 0x4 0.--31. 1. "WKUP_CHAIN1_CRC_CALC_CRC,Calculated chain CRC" line.long 0x8 "CFG0_WKUP_CHAIN2_CRC_CALC," hexmask.long 0x8 0.--31. 1. "WKUP_CHAIN2_CRC_CALC_CRC,Calculated chain CRC" rgroup.long 0xD008++0x7 line.long 0x0 "CFG0_LOCK3_KICK0," hexmask.long 0x0 0.--31. 1. "LOCK3_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK3_KICK1," hexmask.long 0x4 0.--31. 1. "LOCK3_KICK1,- KICK1 component" rgroup.long 0xD100++0x1B line.long 0x0 "CFG0_CLAIMREG_P3_R0_READONLY," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P3_R0_READONLY,Claim bits for Partition 3" line.long 0x4 "CFG0_CLAIMREG_P3_R1_READONLY," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P3_R1_READONLY,Claim bits for Partition 3" line.long 0x8 "CFG0_CLAIMREG_P3_R2_READONLY," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P3_R2_READONLY,Claim bits for Partition 3" line.long 0xC "CFG0_CLAIMREG_P3_R3_READONLY," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P3_R3_READONLY,Claim bits for Partition 3" line.long 0x10 "CFG0_CLAIMREG_P3_R4_READONLY," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P3_R4_READONLY,Claim bits for Partition 3" line.long 0x14 "CFG0_CLAIMREG_P3_R5_READONLY," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P3_R5_READONLY,Claim bits for Partition 3" line.long 0x18 "CFG0_CLAIMREG_P3_R6_READONLY," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P3_R6_READONLY,Claim bits for Partition 3" rgroup.long 0xE000++0x1B line.long 0x0 "CFG0_SMS_LBIST_CTRL_PROXY," bitfld.long 0x0 31. "SMS_LBIST_CTRL_BIST_RESET_PROXY,(Active low) This bitfield is not used. The bist_reset control for SMS is generated by the POST state machine. The bitfield still reflects the efuse value." "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "SMS_LBIST_CTRL_BIST_RUN_PROXY,This bitfield is not used. The bist_run control for SMS is generated by the POST state machine. The bitfield still reflects the efuse value." newline hexmask.long.byte 0x0 12.--15. 1. "SMS_LBIST_CTRL_RUNBIST_MODE_PROXY,Runbist mode enable if all bits are 1" newline bitfld.long 0x0 8.--9. "SMS_LBIST_CTRL_DC_DEF_PROXY,Clock delay after scan_enable switching" "0,1,2,3" line.long 0x4 "CFG0_SMS_LBIST_PATCOUNT_PROXY," hexmask.long.word 0x4 16.--29. 1. "SMS_LBIST_PATCOUNT_STATIC_PC_DEF_PROXY,Number of stuck-at patterns to run" newline hexmask.long.byte 0x4 8.--11. 1. "SMS_LBIST_PATCOUNT_SET_PC_DEF_PROXY,Number of set patterns to run" newline hexmask.long.byte 0x4 4.--7. 1. "SMS_LBIST_PATCOUNT_RESET_PC_DEF_PROXY,Number of reset patterns to run" newline hexmask.long.byte 0x4 0.--3. 1. "SMS_LBIST_PATCOUNT_SCAN_PC_DEF_PROXY,Number of chain test patterns to run" line.long 0x8 "CFG0_SMS_LBIST_SEED0_PROXY," hexmask.long 0x8 0.--31. 1. "SMS_LBIST_SEED0_PRPG_DEF_PROXY,Initial seed for PRPG (bits 31:0)" line.long 0xC "CFG0_SMS_LBIST_SEED1_PROXY," hexmask.long.tbyte 0xC 0.--20. 1. "SMS_LBIST_SEED1_PRPG_DEF_PROXY,Initial seed for PRPG (bits 52:32)" line.long 0x10 "CFG0_SMS_LBIST_SPARE0_PROXY," hexmask.long 0x10 0.--31. 1. "SMS_LBIST_SPARE0_SPARE0_PROXY,LBIST spare bits" line.long 0x14 "CFG0_SMS_LBIST_SPARE1_PROXY," hexmask.long 0x14 0.--31. 1. "SMS_LBIST_SPARE1_SPARE1_PROXY,LBIST spare bits" line.long 0x18 "CFG0_SMS_LBIST_STAT_PROXY," rbitfld.long 0x18 31. "SMS_LBIST_STAT_BIST_DONE_PROXY,LBIST is done" "0,1" newline rbitfld.long 0x18 15. "SMS_LBIST_STAT_BIST_RUNNING_PROXY,LBIST is running" "0,1" newline bitfld.long 0x18 8.--9. "SMS_LBIST_STAT_OUT_MUX_CTL_PROXY,Selects source of LBIST output 00 - LBIST IP PID value 01 - LBIST CTRL ID value 1x - MISR value" "0: LBIST IP PID value 01,?,?,?" newline hexmask.long.byte 0x18 0.--7. 1. "SMS_LBIST_STAT_MISR_MUX_CTL_PROXY,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR." rgroup.long 0xE01C++0x3 line.long 0x0 "CFG0_SMS_LBIST_MISR_PROXY," hexmask.long 0x0 0.--31. 1. "SMS_LBIST_MISR_MISR_RESULT_PROXY,32-bits of MISR value selected by misr_mux_ctl" rgroup.long 0xE280++0x3 line.long 0x0 "CFG0_SMS_LBIST_SIG_PROXY," hexmask.long 0x0 0.--31. 1. "SMS_LBIST_SIG_MISR_SIG_PROXY,MISR signature" rgroup.long 0xE2C0++0x7 line.long 0x0 "CFG0_WKUP_POST_STAT_PROXY," bitfld.long 0x0 17. "WKUP_POST_STAT_FPOST_PLL_LOCK_TIMEOUT_PROXY,Indicates PLL lock timeout for Fast POST mode operation. 0 - PLLs locked Fast POST mode was entered 1 - PLLs lock timeout occurred. Slow speed POST was performed" "0: PLLs locked,1: PLLs lock timeout occurred" newline bitfld.long 0x0 16. "WKUP_POST_STAT_FPOST_PLL_LOCKLOSS_PROXY,Indicates if PLL lock was lost during POST 0 - No PLL lock loss. Fast POST was executed 1 - PLL lock was lost. POST was terminated" "0: No PLL lock loss,1: PLL lock was lost" newline bitfld.long 0x0 15. "WKUP_POST_STAT_POST_MCU_PBIST_FAIL_PROXY,MCU PBIST failed" "0,1" newline bitfld.long 0x0 9. "WKUP_POST_STAT_POST_MCU_PBIST_TIMEOUT_PROXY,MCU PBIST timed out" "0,1" newline bitfld.long 0x0 8. "WKUP_POST_STAT_POST_MCU_PBIST_DONE_PROXY,MCU PBIST done" "0,1" newline bitfld.long 0x0 5. "WKUP_POST_STAT_POST_MCU_LBIST_TIMEOUT_PROXY,MCU LBIST timed out" "0,1" newline bitfld.long 0x0 4. "WKUP_POST_STAT_POST_SMS_LBIST_TIMEOUT_PROXY,SMS LBIST timed out" "0,1" newline bitfld.long 0x0 1. "WKUP_POST_STAT_POST_MCU_LBIST_DONE_PROXY,MCU LBIST done" "0,1" newline bitfld.long 0x0 0. "WKUP_POST_STAT_POST_SMS_LBIST_DONE_PROXY,SMS LBIST done" "0,1" line.long 0x4 "CFG0_WKUP_POST_CFG0_PROXY," bitfld.long 0x4 31. "WKUP_POST_CFG0_FAST_POST_EN_PROXY,Enable Fast POST mode" "0,1" newline bitfld.long 0x4 28.--30. "WKUP_POST_CFG0_POST_DIV2_PROXY,Fast POST PLL secondary post-divider value" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 24.--26. "WKUP_POST_CFG0_POST_DIV1_PROXY,Fast POST PLL primary post-divider value" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--21. 1. "WKUP_POST_CFG0_REF_DIV_PROXY,Fast POST PLL reference clock pre-divider value" newline hexmask.long.word 0x4 0.--11. 1. "WKUP_POST_CFG0_FB_DIV_INT_PROXY,Fast POST PLL feedback divider (integer portion) value" rgroup.long 0xE2CC++0x3 line.long 0x0 "CFG0_WKUP_POST_CFG1_PROXY," bitfld.long 0x0 31. "WKUP_POST_CFG1_FAST_POST_EN_PROXY,Enable Fast POST mode" "0,1" newline bitfld.long 0x0 28.--30. "WKUP_POST_CFG1_POST_DIV2_PROXY,Fast POST PLL secondary post-divider value" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "WKUP_POST_CFG1_POST_DIV1_PROXY,Fast POST PLL primary post-divider value" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--21. 1. "WKUP_POST_CFG1_REF_DIV_PROXY,Fast POST PLL reference clock pre-divider value" newline hexmask.long.word 0x0 0.--11. 1. "WKUP_POST_CFG1_FB_DIV_INT_PROXY,Fast POST PLL feedback divider (integer portion) value" rgroup.long 0xE300++0x3 line.long 0x0 "CFG0_WKUP_FUSE_CRC_CTRL_PROXY," bitfld.long 0x0 2. "WKUP_FUSE_CRC_CTRL_CRC_EN_2_PROXY,Enable eFuse CRC error output for chain 2" "0,1" newline bitfld.long 0x0 1. "WKUP_FUSE_CRC_CTRL_CRC_EN_1_PROXY,Enable eFuse CRC error output for chain 1" "0,1" rgroup.long 0xE304++0x7 line.long 0x0 "CFG0_WKUP_CHAIN1_CRC_FUSE_PROXY," hexmask.long 0x0 0.--31. 1. "WKUP_CHAIN1_CRC_FUSE_CRC_PROXY,Stored chain CRC" line.long 0x4 "CFG0_WKUP_CHAIN2_CRC_FUSE_PROXY," hexmask.long 0x4 0.--31. 1. "WKUP_CHAIN2_CRC_FUSE_CRC_PROXY,Stored chain CRC" rgroup.long 0xE320++0xB line.long 0x0 "CFG0_WKUP_FUSE_CRC_STAT_PROXY," bitfld.long 0x0 31. "WKUP_FUSE_CRC_STAT_AUTOLD_ERR_PROXY,Indicates eFuse autoload or programmation error on any chain" "0,1" newline bitfld.long 0x0 2. "WKUP_FUSE_CRC_STAT_CRC_ERR_2_PROXY,Indicates eFuse CRC error on chain 2" "0,1" newline bitfld.long 0x0 1. "WKUP_FUSE_CRC_STAT_CRC_ERR_1_PROXY,Indicates eFuse CRC error on chain 1" "0,1" line.long 0x4 "CFG0_WKUP_CHAIN1_CRC_CALC_PROXY," hexmask.long 0x4 0.--31. 1. "WKUP_CHAIN1_CRC_CALC_CRC_PROXY,Calculated chain CRC" line.long 0x8 "CFG0_WKUP_CHAIN2_CRC_CALC_PROXY," hexmask.long 0x8 0.--31. 1. "WKUP_CHAIN2_CRC_CALC_CRC_PROXY,Calculated chain CRC" rgroup.long 0xF008++0x7 line.long 0x0 "CFG0_LOCK3_KICK0_PROXY," hexmask.long 0x0 0.--31. 1. "LOCK3_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK3_KICK1_PROXY," hexmask.long 0x4 0.--31. 1. "LOCK3_KICK1_PROXY,- KICK1 component" rgroup.long 0xF100++0x1B line.long 0x0 "CFG0_CLAIMREG_P3_R0," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P3_R0,Claim bits for Partition 3" line.long 0x4 "CFG0_CLAIMREG_P3_R1," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P3_R1,Claim bits for Partition 3" line.long 0x8 "CFG0_CLAIMREG_P3_R2," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P3_R2,Claim bits for Partition 3" line.long 0xC "CFG0_CLAIMREG_P3_R3," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P3_R3,Claim bits for Partition 3" line.long 0x10 "CFG0_CLAIMREG_P3_R4," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P3_R4,Claim bits for Partition 3" line.long 0x14 "CFG0_CLAIMREG_P3_R5," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P3_R5,Claim bits for Partition 3" line.long 0x18 "CFG0_CLAIMREG_P3_R6," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P3_R6,Claim bits for Partition 3" rgroup.long 0x10000++0xFF line.long 0x0 "CFG0_DV_REG0," hexmask.long 0x0 0.--31. 1. "DV_REG0_BIT,Defined by DV usage" line.long 0x4 "CFG0_DV_REG1," hexmask.long 0x4 0.--31. 1. "DV_REG1_BIT,Defined by DV usage" line.long 0x8 "CFG0_DV_REG2," hexmask.long 0x8 0.--31. 1. "DV_REG2_BIT,Defined by DV usage" line.long 0xC "CFG0_DV_REG3," hexmask.long 0xC 0.--31. 1. "DV_REG3_BIT,Defined by DV usage" line.long 0x10 "CFG0_DV_REG4," hexmask.long 0x10 0.--31. 1. "DV_REG4_BIT,Defined by DV usage" line.long 0x14 "CFG0_DV_REG5," hexmask.long 0x14 0.--31. 1. "DV_REG5_BIT,Defined by DV usage" line.long 0x18 "CFG0_DV_REG6," hexmask.long 0x18 0.--31. 1. "DV_REG6_BIT,Defined by DV usage" line.long 0x1C "CFG0_DV_REG7," hexmask.long 0x1C 0.--31. 1. "DV_REG7_BIT,Defined by DV usage" line.long 0x20 "CFG0_DV_REG8," hexmask.long 0x20 0.--31. 1. "DV_REG8_BIT,Defined by DV usage" line.long 0x24 "CFG0_DV_REG9," hexmask.long 0x24 0.--31. 1. "DV_REG9_BIT,Defined by DV usage" line.long 0x28 "CFG0_DV_REG10," hexmask.long 0x28 0.--31. 1. "DV_REG10_BIT,Defined by DV usage" line.long 0x2C "CFG0_DV_REG11," hexmask.long 0x2C 0.--31. 1. "DV_REG11_BIT,Defined by DV usage" line.long 0x30 "CFG0_DV_REG12," hexmask.long 0x30 0.--31. 1. "DV_REG12_BIT,Defined by DV usage" line.long 0x34 "CFG0_DV_REG13," hexmask.long 0x34 0.--31. 1. "DV_REG13_BIT,Defined by DV usage" line.long 0x38 "CFG0_DV_REG14," hexmask.long 0x38 0.--31. 1. "DV_REG14_BIT,Defined by DV usage" line.long 0x3C "CFG0_DV_REG15," hexmask.long 0x3C 0.--31. 1. "DV_REG15_BIT,Defined by DV usage" line.long 0x40 "CFG0_DV_REG16," hexmask.long 0x40 0.--31. 1. "DV_REG16_BIT,Defined by DV usage" line.long 0x44 "CFG0_DV_REG17," hexmask.long 0x44 0.--31. 1. "DV_REG17_BIT,Defined by DV usage" line.long 0x48 "CFG0_DV_REG18," hexmask.long 0x48 0.--31. 1. "DV_REG18_BIT,Defined by DV usage" line.long 0x4C "CFG0_DV_REG19," hexmask.long 0x4C 0.--31. 1. "DV_REG19_BIT,Defined by DV usage" line.long 0x50 "CFG0_DV_REG20," hexmask.long 0x50 0.--31. 1. "DV_REG20_BIT,Defined by DV usage" line.long 0x54 "CFG0_DV_REG21," hexmask.long 0x54 0.--31. 1. "DV_REG21_BIT,Defined by DV usage" line.long 0x58 "CFG0_DV_REG22," hexmask.long 0x58 0.--31. 1. "DV_REG22_BIT,Defined by DV usage" line.long 0x5C "CFG0_DV_REG23," hexmask.long 0x5C 0.--31. 1. "DV_REG23_BIT,Defined by DV usage" line.long 0x60 "CFG0_DV_REG24," hexmask.long 0x60 0.--31. 1. "DV_REG24_BIT,Defined by DV usage" line.long 0x64 "CFG0_DV_REG25," hexmask.long 0x64 0.--31. 1. "DV_REG25_BIT,Defined by DV usage" line.long 0x68 "CFG0_DV_REG26," hexmask.long 0x68 0.--31. 1. "DV_REG26_BIT,Defined by DV usage" line.long 0x6C "CFG0_DV_REG27," hexmask.long 0x6C 0.--31. 1. "DV_REG27_BIT,Defined by DV usage" line.long 0x70 "CFG0_DV_REG28," hexmask.long 0x70 0.--31. 1. "DV_REG28_BIT,Defined by DV usage" line.long 0x74 "CFG0_DV_REG29," hexmask.long 0x74 0.--31. 1. "DV_REG29_BIT,Defined by DV usage" line.long 0x78 "CFG0_DV_REG30," hexmask.long 0x78 0.--31. 1. "DV_REG30_BIT,Defined by DV usage" line.long 0x7C "CFG0_DV_REG31," hexmask.long 0x7C 0.--31. 1. "DV_REG31_BIT,Defined by DV usage" line.long 0x80 "CFG0_DV_REG32," hexmask.long 0x80 0.--31. 1. "DV_REG32_BIT,Defined by DV usage" line.long 0x84 "CFG0_DV_REG33," hexmask.long 0x84 0.--31. 1. "DV_REG33_BIT,Defined by DV usage" line.long 0x88 "CFG0_DV_REG34," hexmask.long 0x88 0.--31. 1. "DV_REG34_BIT,Defined by DV usage" line.long 0x8C "CFG0_DV_REG35," hexmask.long 0x8C 0.--31. 1. "DV_REG35_BIT,Defined by DV usage" line.long 0x90 "CFG0_DV_REG36," hexmask.long 0x90 0.--31. 1. "DV_REG36_BIT,Defined by DV usage" line.long 0x94 "CFG0_DV_REG37," hexmask.long 0x94 0.--31. 1. "DV_REG37_BIT,Defined by DV usage" line.long 0x98 "CFG0_DV_REG38," hexmask.long 0x98 0.--31. 1. "DV_REG38_BIT,Defined by DV usage" line.long 0x9C "CFG0_DV_REG39," hexmask.long 0x9C 0.--31. 1. "DV_REG39_BIT,Defined by DV usage" line.long 0xA0 "CFG0_DV_REG40," hexmask.long 0xA0 0.--31. 1. "DV_REG40_BIT,Defined by DV usage" line.long 0xA4 "CFG0_DV_REG41," hexmask.long 0xA4 0.--31. 1. "DV_REG41_BIT,Defined by DV usage" line.long 0xA8 "CFG0_DV_REG42," hexmask.long 0xA8 0.--31. 1. "DV_REG42_BIT,Defined by DV usage" line.long 0xAC "CFG0_DV_REG43," hexmask.long 0xAC 0.--31. 1. "DV_REG43_BIT,Defined by DV usage" line.long 0xB0 "CFG0_DV_REG44," hexmask.long 0xB0 0.--31. 1. "DV_REG44_BIT,Defined by DV usage" line.long 0xB4 "CFG0_DV_REG45," hexmask.long 0xB4 0.--31. 1. "DV_REG45_BIT,Defined by DV usage" line.long 0xB8 "CFG0_DV_REG46," hexmask.long 0xB8 0.--31. 1. "DV_REG46_BIT,Defined by DV usage" line.long 0xBC "CFG0_DV_REG47," hexmask.long 0xBC 0.--31. 1. "DV_REG47_BIT,Defined by DV usage" line.long 0xC0 "CFG0_DV_REG48," hexmask.long 0xC0 0.--31. 1. "DV_REG48_BIT,Defined by DV usage" line.long 0xC4 "CFG0_DV_REG49," hexmask.long 0xC4 0.--31. 1. "DV_REG49_BIT,Defined by DV usage" line.long 0xC8 "CFG0_DV_REG50," hexmask.long 0xC8 0.--31. 1. "DV_REG50_BIT,Defined by DV usage" line.long 0xCC "CFG0_DV_REG51," hexmask.long 0xCC 0.--31. 1. "DV_REG51_BIT,Defined by DV usage" line.long 0xD0 "CFG0_DV_REG52," hexmask.long 0xD0 0.--31. 1. "DV_REG52_BIT,Defined by DV usage" line.long 0xD4 "CFG0_DV_REG53," hexmask.long 0xD4 0.--31. 1. "DV_REG53_BIT,Defined by DV usage" line.long 0xD8 "CFG0_DV_REG54," hexmask.long 0xD8 0.--31. 1. "DV_REG54_BIT,Defined by DV usage" line.long 0xDC "CFG0_DV_REG55," hexmask.long 0xDC 0.--31. 1. "DV_REG55_BIT,Defined by DV usage" line.long 0xE0 "CFG0_DV_REG56," hexmask.long 0xE0 0.--31. 1. "DV_REG56_BIT,Defined by DV usage" line.long 0xE4 "CFG0_DV_REG57," hexmask.long 0xE4 0.--31. 1. "DV_REG57_BIT,Defined by DV usage" line.long 0xE8 "CFG0_DV_REG58," hexmask.long 0xE8 0.--31. 1. "DV_REG58_BIT,Defined by DV usage" line.long 0xEC "CFG0_DV_REG59," hexmask.long 0xEC 0.--31. 1. "DV_REG59_BIT,Defined by DV usage" line.long 0xF0 "CFG0_DV_REG60," hexmask.long 0xF0 0.--31. 1. "DV_REG60_BIT,Defined by DV usage" line.long 0xF4 "CFG0_DV_REG61," hexmask.long 0xF4 0.--31. 1. "DV_REG61_BIT,Defined by DV usage" line.long 0xF8 "CFG0_DV_REG62," hexmask.long 0xF8 0.--31. 1. "DV_REG62_BIT,Defined by DV usage" line.long 0xFC "CFG0_DV_REG63," hexmask.long 0xFC 0.--31. 1. "DV_REG63_BIT,Defined by DV usage" rgroup.long 0x10200++0x7F line.long 0x0 "CFG0_DV_REG0_SET," hexmask.long 0x0 0.--31. 1. "DV_REG0_SET_BIT,Defined by DV usage" line.long 0x4 "CFG0_DV_REG1_SET," hexmask.long 0x4 0.--31. 1. "DV_REG1_SET_BIT,Defined by DV usage" line.long 0x8 "CFG0_DV_REG2_SET," hexmask.long 0x8 0.--31. 1. "DV_REG2_SET_BIT,Defined by DV usage" line.long 0xC "CFG0_DV_REG3_SET," hexmask.long 0xC 0.--31. 1. "DV_REG3_SET_BIT,Defined by DV usage" line.long 0x10 "CFG0_DV_REG4_SET," hexmask.long 0x10 0.--31. 1. "DV_REG4_SET_BIT,Defined by DV usage" line.long 0x14 "CFG0_DV_REG5_SET," hexmask.long 0x14 0.--31. 1. "DV_REG5_SET_BIT,Defined by DV usage" line.long 0x18 "CFG0_DV_REG6_SET," hexmask.long 0x18 0.--31. 1. "DV_REG6_SET_BIT,Defined by DV usage" line.long 0x1C "CFG0_DV_REG7_SET," hexmask.long 0x1C 0.--31. 1. "DV_REG7_SET_BIT,Defined by DV usage" line.long 0x20 "CFG0_DV_REG8_SET," hexmask.long 0x20 0.--31. 1. "DV_REG8_SET_BIT,Defined by DV usage" line.long 0x24 "CFG0_DV_REG9_SET," hexmask.long 0x24 0.--31. 1. "DV_REG9_SET_BIT,Defined by DV usage" line.long 0x28 "CFG0_DV_REG10_SET," hexmask.long 0x28 0.--31. 1. "DV_REG10_SET_BIT,Defined by DV usage" line.long 0x2C "CFG0_DV_REG11_SET," hexmask.long 0x2C 0.--31. 1. "DV_REG11_SET_BIT,Defined by DV usage" line.long 0x30 "CFG0_DV_REG12_SET," hexmask.long 0x30 0.--31. 1. "DV_REG12_SET_BIT,Defined by DV usage" line.long 0x34 "CFG0_DV_REG13_SET," hexmask.long 0x34 0.--31. 1. "DV_REG13_SET_BIT,Defined by DV usage" line.long 0x38 "CFG0_DV_REG14_SET," hexmask.long 0x38 0.--31. 1. "DV_REG14_SET_BIT,Defined by DV usage" line.long 0x3C "CFG0_DV_REG15_SET," hexmask.long 0x3C 0.--31. 1. "DV_REG15_SET_BIT,Defined by DV usage" line.long 0x40 "CFG0_DV_REG16_SET," hexmask.long 0x40 0.--31. 1. "DV_REG16_SET_BIT,Defined by DV usage" line.long 0x44 "CFG0_DV_REG17_SET," hexmask.long 0x44 0.--31. 1. "DV_REG17_SET_BIT,Defined by DV usage" line.long 0x48 "CFG0_DV_REG18_SET," hexmask.long 0x48 0.--31. 1. "DV_REG18_SET_BIT,Defined by DV usage" line.long 0x4C "CFG0_DV_REG19_SET," hexmask.long 0x4C 0.--31. 1. "DV_REG19_SET_BIT,Defined by DV usage" line.long 0x50 "CFG0_DV_REG20_SET," hexmask.long 0x50 0.--31. 1. "DV_REG20_SET_BIT,Defined by DV usage" line.long 0x54 "CFG0_DV_REG21_SET," hexmask.long 0x54 0.--31. 1. "DV_REG21_SET_BIT,Defined by DV usage" line.long 0x58 "CFG0_DV_REG22_SET," hexmask.long 0x58 0.--31. 1. "DV_REG22_SET_BIT,Defined by DV usage" line.long 0x5C "CFG0_DV_REG23_SET," hexmask.long 0x5C 0.--31. 1. "DV_REG23_SET_BIT,Defined by DV usage" line.long 0x60 "CFG0_DV_REG24_SET," hexmask.long 0x60 0.--31. 1. "DV_REG24_SET_BIT,Defined by DV usage" line.long 0x64 "CFG0_DV_REG25_SET," hexmask.long 0x64 0.--31. 1. "DV_REG25_SET_BIT,Defined by DV usage" line.long 0x68 "CFG0_DV_REG26_SET," hexmask.long 0x68 0.--31. 1. "DV_REG26_SET_BIT,Defined by DV usage" line.long 0x6C "CFG0_DV_REG27_SET," hexmask.long 0x6C 0.--31. 1. "DV_REG27_SET_BIT,Defined by DV usage" line.long 0x70 "CFG0_DV_REG28_SET," hexmask.long 0x70 0.--31. 1. "DV_REG28_SET_BIT,Defined by DV usage" line.long 0x74 "CFG0_DV_REG29_SET," hexmask.long 0x74 0.--31. 1. "DV_REG29_SET_BIT,Defined by DV usage" line.long 0x78 "CFG0_DV_REG30_SET," hexmask.long 0x78 0.--31. 1. "DV_REG30_SET_BIT,Defined by DV usage" line.long 0x7C "CFG0_DV_REG31_SET," hexmask.long 0x7C 0.--31. 1. "DV_REG31_SET_BIT,Defined by DV usage" rgroup.long 0x10300++0x7F line.long 0x0 "CFG0_DV_REG0_CLR," hexmask.long 0x0 0.--31. 1. "DV_REG0_CLR_BIT,Defined by DV usage" line.long 0x4 "CFG0_DV_REG1_CLR," hexmask.long 0x4 0.--31. 1. "DV_REG1_CLR_BIT,Defined by DV usage" line.long 0x8 "CFG0_DV_REG2_CLR," hexmask.long 0x8 0.--31. 1. "DV_REG2_CLR_BIT,Defined by DV usage" line.long 0xC "CFG0_DV_REG3_CLR," hexmask.long 0xC 0.--31. 1. "DV_REG3_CLR_BIT,Defined by DV usage" line.long 0x10 "CFG0_DV_REG4_CLR," hexmask.long 0x10 0.--31. 1. "DV_REG4_CLR_BIT,Defined by DV usage" line.long 0x14 "CFG0_DV_REG5_CLR," hexmask.long 0x14 0.--31. 1. "DV_REG5_CLR_BIT,Defined by DV usage" line.long 0x18 "CFG0_DV_REG6_CLR," hexmask.long 0x18 0.--31. 1. "DV_REG6_CLR_BIT,Defined by DV usage" line.long 0x1C "CFG0_DV_REG7_CLR," hexmask.long 0x1C 0.--31. 1. "DV_REG7_CLR_BIT,Defined by DV usage" line.long 0x20 "CFG0_DV_REG8_CLR," hexmask.long 0x20 0.--31. 1. "DV_REG8_CLR_BIT,Defined by DV usage" line.long 0x24 "CFG0_DV_REG9_CLR," hexmask.long 0x24 0.--31. 1. "DV_REG9_CLR_BIT,Defined by DV usage" line.long 0x28 "CFG0_DV_REG10_CLR," hexmask.long 0x28 0.--31. 1. "DV_REG10_CLR_BIT,Defined by DV usage" line.long 0x2C "CFG0_DV_REG11_CLR," hexmask.long 0x2C 0.--31. 1. "DV_REG11_CLR_BIT,Defined by DV usage" line.long 0x30 "CFG0_DV_REG12_CLR," hexmask.long 0x30 0.--31. 1. "DV_REG12_CLR_BIT,Defined by DV usage" line.long 0x34 "CFG0_DV_REG13_CLR," hexmask.long 0x34 0.--31. 1. "DV_REG13_CLR_BIT,Defined by DV usage" line.long 0x38 "CFG0_DV_REG14_CLR," hexmask.long 0x38 0.--31. 1. "DV_REG14_CLR_BIT,Defined by DV usage" line.long 0x3C "CFG0_DV_REG15_CLR," hexmask.long 0x3C 0.--31. 1. "DV_REG15_CLR_BIT,Defined by DV usage" line.long 0x40 "CFG0_DV_REG16_CLR," hexmask.long 0x40 0.--31. 1. "DV_REG16_CLR_BIT,Defined by DV usage" line.long 0x44 "CFG0_DV_REG17_CLR," hexmask.long 0x44 0.--31. 1. "DV_REG17_CLR_BIT,Defined by DV usage" line.long 0x48 "CFG0_DV_REG18_CLR," hexmask.long 0x48 0.--31. 1. "DV_REG18_CLR_BIT,Defined by DV usage" line.long 0x4C "CFG0_DV_REG19_CLR," hexmask.long 0x4C 0.--31. 1. "DV_REG19_CLR_BIT,Defined by DV usage" line.long 0x50 "CFG0_DV_REG20_CLR," hexmask.long 0x50 0.--31. 1. "DV_REG20_CLR_BIT,Defined by DV usage" line.long 0x54 "CFG0_DV_REG21_CLR," hexmask.long 0x54 0.--31. 1. "DV_REG21_CLR_BIT,Defined by DV usage" line.long 0x58 "CFG0_DV_REG22_CLR," hexmask.long 0x58 0.--31. 1. "DV_REG22_CLR_BIT,Defined by DV usage" line.long 0x5C "CFG0_DV_REG23_CLR," hexmask.long 0x5C 0.--31. 1. "DV_REG23_CLR_BIT,Defined by DV usage" line.long 0x60 "CFG0_DV_REG24_CLR," hexmask.long 0x60 0.--31. 1. "DV_REG24_CLR_BIT,Defined by DV usage" line.long 0x64 "CFG0_DV_REG25_CLR," hexmask.long 0x64 0.--31. 1. "DV_REG25_CLR_BIT,Defined by DV usage" line.long 0x68 "CFG0_DV_REG26_CLR," hexmask.long 0x68 0.--31. 1. "DV_REG26_CLR_BIT,Defined by DV usage" line.long 0x6C "CFG0_DV_REG27_CLR," hexmask.long 0x6C 0.--31. 1. "DV_REG27_CLR_BIT,Defined by DV usage" line.long 0x70 "CFG0_DV_REG28_CLR," hexmask.long 0x70 0.--31. 1. "DV_REG28_CLR_BIT,Defined by DV usage" line.long 0x74 "CFG0_DV_REG29_CLR," hexmask.long 0x74 0.--31. 1. "DV_REG29_CLR_BIT,Defined by DV usage" line.long 0x78 "CFG0_DV_REG30_CLR," hexmask.long 0x78 0.--31. 1. "DV_REG30_CLR_BIT,Defined by DV usage" line.long 0x7C "CFG0_DV_REG31_CLR," hexmask.long 0x7C 0.--31. 1. "DV_REG31_CLR_BIT,Defined by DV usage" rgroup.long 0x10400++0x3 line.long 0x0 "CFG0_LED_CTRL," hexmask.long 0x0 1.--31. 1. "LED_CTRL_CONTROL,Test control" newline rbitfld.long 0x0 0. "LED_CTRL_LED_MODE,LED mode from decoded enable key" "0,1" rgroup.long 0x10408++0x3 line.long 0x0 "CFG0_LED_ENABLE," hexmask.long 0x0 0.--31. 1. "LED_ENABLE_ENABLE_KEY,LED mode entry key 32'h204C4544 - Set PADCONFIG registers to LED mode values others - PADCONFIG registers retain programmed values" rgroup.long 0x10420++0x13 line.long 0x0 "CFG0_LED_MCU_PLL_STAT_EN," bitfld.long 0x0 2. "LED_MCU_PLL_STAT_EN_MCU_PLL2_EN,Enable MCU_PLL2 lockloss in status generation" "0,1" newline bitfld.long 0x0 1. "LED_MCU_PLL_STAT_EN_MCU_PLL1_EN,Enable MCU_PLL1 lockloss in status generation" "0,1" newline bitfld.long 0x0 0. "LED_MCU_PLL_STAT_EN_MCU_PLL0_EN,Enable MCU_PLL0 lockloss in status generation" "0,1" line.long 0x4 "CFG0_LED_MAIN_PLL_STAT_EN," bitfld.long 0x4 28. "LED_MAIN_PLL_STAT_EN_MAIN_PLL28_EN,Enable MAIN_PLL28 lockloss in status generation" "0,1" newline bitfld.long 0x4 27. "LED_MAIN_PLL_STAT_EN_MAIN_PLL27_EN,Enable MAIN_PLL27 lockloss in status generation" "0,1" newline bitfld.long 0x4 26. "LED_MAIN_PLL_STAT_EN_MAIN_PLL26_EN,Enable MAIN_PLL26 lockloss in status generation" "0,1" newline bitfld.long 0x4 25. "LED_MAIN_PLL_STAT_EN_MAIN_PLL25_EN,Enable MAIN_PLL25 lockloss in status generation" "0,1" newline bitfld.long 0x4 19. "LED_MAIN_PLL_STAT_EN_MAIN_PLL19_EN,Enable MAIN_PLL19 lockloss in status generation" "0,1" newline bitfld.long 0x4 17. "LED_MAIN_PLL_STAT_EN_MAIN_PLL17_EN,Enable MAIN_PLL17 lockloss in status generation" "0,1" newline bitfld.long 0x4 16. "LED_MAIN_PLL_STAT_EN_MAIN_PLL16_EN,Enable MAIN_PLL16 lockloss in status generation" "0,1" newline bitfld.long 0x4 14. "LED_MAIN_PLL_STAT_EN_MAIN_PLL14_EN,Enable MAIN_PLL14 lockloss in status generation" "0,1" newline bitfld.long 0x4 12. "LED_MAIN_PLL_STAT_EN_MAIN_PLL12_EN,Enable MAIN_PLL12 lockloss in status generation" "0,1" newline bitfld.long 0x4 9. "LED_MAIN_PLL_STAT_EN_MAIN_PLL9_EN,Enable MAIN_PLL9 lockloss in status generation" "0,1" newline bitfld.long 0x4 8. "LED_MAIN_PLL_STAT_EN_MAIN_PLL8_EN,Enable MAIN_PLL8 lockloss in status generation" "0,1" newline bitfld.long 0x4 7. "LED_MAIN_PLL_STAT_EN_MAIN_PLL7_EN,Enable MAIN_PLL7 lockloss in status generation" "0,1" newline bitfld.long 0x4 6. "LED_MAIN_PLL_STAT_EN_MAIN_PLL6_EN,Enable MAIN_PLL6 lockloss in status generation" "0,1" newline bitfld.long 0x4 5. "LED_MAIN_PLL_STAT_EN_MAIN_PLL5_EN,Enable MAIN_PLL5 lockloss in status generation" "0,1" newline bitfld.long 0x4 4. "LED_MAIN_PLL_STAT_EN_MAIN_PLL4_EN,Enable MAIN_PLL4 lockloss in status generation" "0,1" newline bitfld.long 0x4 3. "LED_MAIN_PLL_STAT_EN_MAIN_PLL3_EN,Enable MAIN_PLL3 lockloss in status generation" "0,1" newline bitfld.long 0x4 2. "LED_MAIN_PLL_STAT_EN_MAIN_PLL2_EN,Enable MAIN_PLL2 lockloss in status generation" "0,1" newline bitfld.long 0x4 1. "LED_MAIN_PLL_STAT_EN_MAIN_PLL1_EN,Enable MAIN_PLL1 lockloss in status generation" "0,1" newline bitfld.long 0x4 0. "LED_MAIN_PLL_STAT_EN_MAIN_PLL0_EN,Enable MAIN_PLL0 lockloss in status generation" "0,1" line.long 0x8 "CFG0_LED_PGD_STAT_EN," bitfld.long 0x8 13. "LED_PGD_STAT_EN_VDDR_CPU1_EN,Enable vddr_cpu1 PGD in status generation" "0,1" newline bitfld.long 0x8 12. "LED_PGD_STAT_EN_VDD_CPU1_EN,Enable vdd_cpu1 PGD in status generation" "0,1" newline bitfld.long 0x8 11. "LED_PGD_STAT_EN_VDDR_CORE_EN,Enable vddr_core PGD in status generation" "0,1" newline bitfld.long 0x8 10. "LED_PGD_STAT_EN_VDDR_CPU_EN,Enable vddr_cpu PGD in status generation" "0,1" newline bitfld.long 0x8 9. "LED_PGD_STAT_EN_VDD_CORE_EN,Enable vdd_core PGD in status generation" "0,1" newline bitfld.long 0x8 8. "LED_PGD_STAT_EN_VDD_CPU_EN,Enable vdd_cpu PGD in status generation" "0,1" newline bitfld.long 0x8 1. "LED_PGD_STAT_EN_VDDR_MCU_EN,Enable vddr_mcu PGD in status generation" "0,1" newline bitfld.long 0x8 0. "LED_PGD_STAT_EN_VDD_MCU_EN,Enable vdd_mcu PGD in status generation" "0,1" line.long 0xC "CFG0_LED_EFC_STAT_EN," bitfld.long 0xC 8. "LED_EFC_STAT_EN_MAIN_EFC_EN,Enable MAIN eFuse Ctrl PGD in status generation" "0,1" newline bitfld.long 0xC 0. "LED_EFC_STAT_EN_MCU_EFC_EN,Enable MCU eFuse Ctrl PGD in status generation" "0,1" line.long 0x10 "CFG0_LED_STATUS_CTRL," bitfld.long 0x10 8. "LED_STATUS_CTRL_STICKY_EN,Sticky status enable. Selects which version of status to output on the pin. 0 - Use real-time status signal 1 - Use sticky status signal" "0: Use real-time status signal 1,?" newline bitfld.long 0x10 0. "LED_STATUS_CTRL_STICKY_STATUS,Sticky status bit. This bit captures the falling edge of the status signal" "0,1" rgroup.long 0x10480++0x1F line.long 0x0 "CFG0_SIM_CFG0," hexmask.long 0x0 0.--31. 1. "SIM_CFG0_CFG_INFO,Model configuration info. Bit usage is determined by AVV team." line.long 0x4 "CFG0_SIM_CFG1," hexmask.long 0x4 0.--31. 1. "SIM_CFG1_CFG_INFO,Model configuration info. Bit usage is determined by AVV team." line.long 0x8 "CFG0_SIM_CFG2," hexmask.long 0x8 0.--31. 1. "SIM_CFG2_CFG_INFO,Model configuration info. Bit usage is determined by AVV team." line.long 0xC "CFG0_SIM_CFG3," hexmask.long 0xC 0.--31. 1. "SIM_CFG3_CFG_INFO,Model configuration info. Bit usage is determined by AVV team." line.long 0x10 "CFG0_SIM_CFG4," hexmask.long 0x10 0.--31. 1. "SIM_CFG4_CFG_INFO,Model configuration info. Bit usage is determined by AVV team." line.long 0x14 "CFG0_SIM_CFG5," hexmask.long 0x14 0.--31. 1. "SIM_CFG5_CFG_INFO,Model configuration info. Bit usage is determined by AVV team." line.long 0x18 "CFG0_SIM_CFG6," hexmask.long 0x18 0.--31. 1. "SIM_CFG6_CFG_INFO,Model configuration info. Bit usage is determined by AVV team." line.long 0x1C "CFG0_SIM_CFG7," hexmask.long 0x1C 0.--31. 1. "SIM_CFG7_CFG_INFO,Model configuration info. Bit usage is determined by AVV team." rgroup.long 0x10500++0x27 line.long 0x0 "CFG0_WKUP_MRGN_MODE0," hexmask.long.word 0x0 0.--11. 1. "WKUP_MRGN_MODE0_HS2PARF_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x4 "CFG0_WKUP_MRGN_MODE1," hexmask.long.word 0x4 0.--11. 1. "WKUP_MRGN_MODE1_HDDP_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x8 "CFG0_WKUP_MRGN_MODE2," hexmask.long.word 0x8 0.--11. 1. "WKUP_MRGN_MODE2_EHDSP_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0xC "CFG0_WKUP_MRGN_MODE3," hexmask.long.word 0xC 0.--11. 1. "WKUP_MRGN_MODE3_HD2PRF_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x10 "CFG0_WKUP_MRGN_MODE4," hexmask.long.word 0x10 0.--11. 1. "WKUP_MRGN_MODE4_UHD2PRF_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x14 "CFG0_WKUP_MRGN_MODE5," hexmask.long.word 0x14 0.--11. 1. "WKUP_MRGN_MODE5_ROM_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x18 "CFG0_WKUP_MRGN_MODE6," hexmask.long.word 0x18 0.--11. 1. "WKUP_MRGN_MODE6_HDSP_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x1C "CFG0_WKUP_MRGN_MODE7," hexmask.long.word 0x1C 0.--11. 1. "WKUP_MRGN_MODE7_HSSP_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x20 "CFG0_WKUP_MRGN_MODE8," hexmask.long.word 0x20 0.--11. 1. "WKUP_MRGN_MODE8_HD1PRF_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x24 "CFG0_WKUP_MRGN_MODE9," hexmask.long.word 0x24 0.--11. 1. "WKUP_MRGN_MODE9_HS1PRF_MEM_MRGN_ASST,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" rgroup.long 0x10700++0x3 line.long 0x0 "CFG0_ATEST_RCOSC," bitfld.long 0x0 7. "ATEST_RCOSC_ATEST_EN,Test enable 1'b0 - Disable (atestout is floating) 1'b1 - Enable (see atest_test)" "0: Disable,1: Enable" newline bitfld.long 0x0 0.--1. "ATEST_RCOSC_ATEST_SEL,Test select When atest_en = 1 2'b0x - Hi-Z (Test 3) 2'b10 - Bias current (Test 1) 2'b11 - VREF (Test 2)" "?,?,2: Bias current,3: VREF" rgroup.long 0x10720++0x7 line.long 0x0 "CFG0_ATEST_HFOSC0," bitfld.long 0x0 0. "ATEST_HFOSC0_TEST_EN_C,Test enable 1'b0 - Output test current disabled 1'b1 - Test current enabled" "0: Output test current disabled 1'b1,?" line.long 0x4 "CFG0_ATEST_HFOSC1," bitfld.long 0x4 0. "ATEST_HFOSC1_TEST_EN_C,Test enable 1'b0 - Output test current disabled 1'b1 - Test current enabled" "0: Output test current disabled 1'b1,?" rgroup.long 0x10740++0x17 line.long 0x0 "CFG0_ATEST_POR," bitfld.long 0x0 8.--10. "ATEST_POR_SEL_ATESTIN,Test select 3'b000 - Test Modes 0-4 See sel_atest value 3'b001 - Test Mode 5 when sel_atest = 6'b001111 Others - N/A (Hi-Z at ATEST_OUT)" "0: Test Modes 0-4,1: Test Mode 5 when sel_atest = 6'b001111 Others,?,?,?,?,?,?" newline hexmask.long.byte 0x0 0.--5. 1. "ATEST_POR_SEL_ATEST,Test select 6'b000000 to 001010 - Bandgap TestT (Test Mode 1) 6'b001001 to 001111 - Hi-Z (when sel_atestin = 3'b000) 6'b001001 to 001111 - HVPOR Test (when sel_atestin = 3'b001) 6'b01xx00 to 01xx11 - POKHV Test (Test Mode 2).." line.long 0x4 "CFG0_ATEST_POK_VDDA_MCU_UV_CTRL," bitfld.long 0x4 0.--2. "ATEST_POK_VDDA_MCU_UV_CTRL_POK_ATMUXSEL,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0x8 "CFG0_ATEST_POK_VDDA_MCU_OV_CTRL," bitfld.long 0x8 0.--2. "ATEST_POK_VDDA_MCU_OV_CTRL_POK_ATMUXSEL,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0xC "CFG0_ATEST_POK_VDD_MCU_UV_CTRL," bitfld.long 0xC 0.--2. "ATEST_POK_VDD_MCU_UV_CTRL_POK_ATMUXSEL,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0x10 "CFG0_ATEST_POK_VDDA_PMIC_IN," bitfld.long 0x10 0.--2. "ATEST_POK_VDDA_PMIC_IN_POK_ATMUXSEL,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0x14 "CFG0_ATEST_POK_VDD_MCU_OV_CTRL," bitfld.long 0x14 0.--2. "ATEST_POK_VDD_MCU_OV_CTRL_POK_ATMUXSEL,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" rgroup.long 0x10760++0xB line.long 0x0 "CFG0_ATEST_POK_VDDSHV_WKUP_GEN_CTRL," bitfld.long 0x0 0.--2. "ATEST_POK_VDDSHV_WKUP_GEN_CTRL_POK_ATMUXSEL,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0x4 "CFG0_ATEST_POK_VDDR_MCU_CTRL," bitfld.long 0x4 0.--2. "ATEST_POK_VDDR_MCU_CTRL_POK_ATMUXSEL,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0x8 "CFG0_ATEST_POK_VMON_CAP_MCU_GEN_CTRL," bitfld.long 0x8 0.--2. "ATEST_POK_VMON_CAP_MCU_GEN_CTRL_POK_ATMUXSEL,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" rgroup.long 0x10780++0x1B line.long 0x0 "CFG0_ATEST_POK_VDD_CORE_CTRL," bitfld.long 0x0 0.--2. "ATEST_POK_VDD_CORE_CTRL_POK_ATMUXSEL,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0x4 "CFG0_ATEST_POK_VDD_CPU_CTRL," bitfld.long 0x4 0.--2. "ATEST_POK_VDD_CPU_CTRL_POK_ATMUXSEL,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0x8 "CFG0_ATEST_POK_VMON_EXT_CTRL," bitfld.long 0x8 0.--2. "ATEST_POK_VMON_EXT_CTRL_POK_ATMUXSEL,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0xC "CFG0_ATEST_POK_VDDR_CORE_CTRL," bitfld.long 0xC 0.--2. "ATEST_POK_VDDR_CORE_CTRL_POK_ATMUXSEL,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0x10 "CFG0_ATEST_POK_VMON_EXT_MAIN1P8_CTRL," bitfld.long 0x10 0.--2. "ATEST_POK_VMON_EXT_MAIN1P8_CTRL_POK_ATMUXSEL,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0x14 "CFG0_ATEST_POK_VMON_EXT_MAIN3P3_CTRL," bitfld.long 0x14 0.--2. "ATEST_POK_VMON_EXT_MAIN3P3_CTRL_POK_ATMUXSEL,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0x18 "CFG0_ATEST_POK_VDD_CPU1_CTRL," bitfld.long 0x18 0.--2. "ATEST_POK_VDD_CPU1_CTRL_POK_ATMUXSEL,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" rgroup.long 0x11008++0x7 line.long 0x0 "CFG0_LOCK4_KICK0," hexmask.long 0x0 0.--31. 1. "LOCK4_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK4_KICK1," hexmask.long 0x4 0.--31. 1. "LOCK4_KICK1,- KICK1 component" rgroup.long 0x11100++0x3F line.long 0x0 "CFG0_CLAIMREG_P4_R0_READONLY," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P4_R0_READONLY,Claim bits for Partition 4" line.long 0x4 "CFG0_CLAIMREG_P4_R1_READONLY," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P4_R1_READONLY,Claim bits for Partition 4" line.long 0x8 "CFG0_CLAIMREG_P4_R2_READONLY," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P4_R2_READONLY,Claim bits for Partition 4" line.long 0xC "CFG0_CLAIMREG_P4_R3_READONLY," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P4_R3_READONLY,Claim bits for Partition 4" line.long 0x10 "CFG0_CLAIMREG_P4_R4_READONLY," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P4_R4_READONLY,Claim bits for Partition 4" line.long 0x14 "CFG0_CLAIMREG_P4_R5_READONLY," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P4_R5_READONLY,Claim bits for Partition 4" line.long 0x18 "CFG0_CLAIMREG_P4_R6_READONLY," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P4_R6_READONLY,Claim bits for Partition 4" line.long 0x1C "CFG0_CLAIMREG_P4_R7_READONLY," hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P4_R7_READONLY,Claim bits for Partition 4" line.long 0x20 "CFG0_CLAIMREG_P4_R8_READONLY," hexmask.long 0x20 0.--31. 1. "CLAIMREG_P4_R8_READONLY,Claim bits for Partition 4" line.long 0x24 "CFG0_CLAIMREG_P4_R9_READONLY," hexmask.long 0x24 0.--31. 1. "CLAIMREG_P4_R9_READONLY,Claim bits for Partition 4" line.long 0x28 "CFG0_CLAIMREG_P4_R10_READONLY," hexmask.long 0x28 0.--31. 1. "CLAIMREG_P4_R10_READONLY,Claim bits for Partition 4" line.long 0x2C "CFG0_CLAIMREG_P4_R11_READONLY," hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P4_R11_READONLY,Claim bits for Partition 4" line.long 0x30 "CFG0_CLAIMREG_P4_R12_READONLY," hexmask.long 0x30 0.--31. 1. "CLAIMREG_P4_R12_READONLY,Claim bits for Partition 4" line.long 0x34 "CFG0_CLAIMREG_P4_R13_READONLY," hexmask.long 0x34 0.--31. 1. "CLAIMREG_P4_R13_READONLY,Claim bits for Partition 4" line.long 0x38 "CFG0_CLAIMREG_P4_R14_READONLY," hexmask.long 0x38 0.--31. 1. "CLAIMREG_P4_R14_READONLY,Claim bits for Partition 4" line.long 0x3C "CFG0_CLAIMREG_P4_R15_READONLY," hexmask.long 0x3C 0.--31. 1. "CLAIMREG_P4_R15_READONLY,Claim bits for Partition 4" rgroup.long 0x12000++0xFF line.long 0x0 "CFG0_DV_REG0_PROXY," hexmask.long 0x0 0.--31. 1. "DV_REG0_BIT_PROXY,Defined by DV usage" line.long 0x4 "CFG0_DV_REG1_PROXY," hexmask.long 0x4 0.--31. 1. "DV_REG1_BIT_PROXY,Defined by DV usage" line.long 0x8 "CFG0_DV_REG2_PROXY," hexmask.long 0x8 0.--31. 1. "DV_REG2_BIT_PROXY,Defined by DV usage" line.long 0xC "CFG0_DV_REG3_PROXY," hexmask.long 0xC 0.--31. 1. "DV_REG3_BIT_PROXY,Defined by DV usage" line.long 0x10 "CFG0_DV_REG4_PROXY," hexmask.long 0x10 0.--31. 1. "DV_REG4_BIT_PROXY,Defined by DV usage" line.long 0x14 "CFG0_DV_REG5_PROXY," hexmask.long 0x14 0.--31. 1. "DV_REG5_BIT_PROXY,Defined by DV usage" line.long 0x18 "CFG0_DV_REG6_PROXY," hexmask.long 0x18 0.--31. 1. "DV_REG6_BIT_PROXY,Defined by DV usage" line.long 0x1C "CFG0_DV_REG7_PROXY," hexmask.long 0x1C 0.--31. 1. "DV_REG7_BIT_PROXY,Defined by DV usage" line.long 0x20 "CFG0_DV_REG8_PROXY," hexmask.long 0x20 0.--31. 1. "DV_REG8_BIT_PROXY,Defined by DV usage" line.long 0x24 "CFG0_DV_REG9_PROXY," hexmask.long 0x24 0.--31. 1. "DV_REG9_BIT_PROXY,Defined by DV usage" line.long 0x28 "CFG0_DV_REG10_PROXY," hexmask.long 0x28 0.--31. 1. "DV_REG10_BIT_PROXY,Defined by DV usage" line.long 0x2C "CFG0_DV_REG11_PROXY," hexmask.long 0x2C 0.--31. 1. "DV_REG11_BIT_PROXY,Defined by DV usage" line.long 0x30 "CFG0_DV_REG12_PROXY," hexmask.long 0x30 0.--31. 1. "DV_REG12_BIT_PROXY,Defined by DV usage" line.long 0x34 "CFG0_DV_REG13_PROXY," hexmask.long 0x34 0.--31. 1. "DV_REG13_BIT_PROXY,Defined by DV usage" line.long 0x38 "CFG0_DV_REG14_PROXY," hexmask.long 0x38 0.--31. 1. "DV_REG14_BIT_PROXY,Defined by DV usage" line.long 0x3C "CFG0_DV_REG15_PROXY," hexmask.long 0x3C 0.--31. 1. "DV_REG15_BIT_PROXY,Defined by DV usage" line.long 0x40 "CFG0_DV_REG16_PROXY," hexmask.long 0x40 0.--31. 1. "DV_REG16_BIT_PROXY,Defined by DV usage" line.long 0x44 "CFG0_DV_REG17_PROXY," hexmask.long 0x44 0.--31. 1. "DV_REG17_BIT_PROXY,Defined by DV usage" line.long 0x48 "CFG0_DV_REG18_PROXY," hexmask.long 0x48 0.--31. 1. "DV_REG18_BIT_PROXY,Defined by DV usage" line.long 0x4C "CFG0_DV_REG19_PROXY," hexmask.long 0x4C 0.--31. 1. "DV_REG19_BIT_PROXY,Defined by DV usage" line.long 0x50 "CFG0_DV_REG20_PROXY," hexmask.long 0x50 0.--31. 1. "DV_REG20_BIT_PROXY,Defined by DV usage" line.long 0x54 "CFG0_DV_REG21_PROXY," hexmask.long 0x54 0.--31. 1. "DV_REG21_BIT_PROXY,Defined by DV usage" line.long 0x58 "CFG0_DV_REG22_PROXY," hexmask.long 0x58 0.--31. 1. "DV_REG22_BIT_PROXY,Defined by DV usage" line.long 0x5C "CFG0_DV_REG23_PROXY," hexmask.long 0x5C 0.--31. 1. "DV_REG23_BIT_PROXY,Defined by DV usage" line.long 0x60 "CFG0_DV_REG24_PROXY," hexmask.long 0x60 0.--31. 1. "DV_REG24_BIT_PROXY,Defined by DV usage" line.long 0x64 "CFG0_DV_REG25_PROXY," hexmask.long 0x64 0.--31. 1. "DV_REG25_BIT_PROXY,Defined by DV usage" line.long 0x68 "CFG0_DV_REG26_PROXY," hexmask.long 0x68 0.--31. 1. "DV_REG26_BIT_PROXY,Defined by DV usage" line.long 0x6C "CFG0_DV_REG27_PROXY," hexmask.long 0x6C 0.--31. 1. "DV_REG27_BIT_PROXY,Defined by DV usage" line.long 0x70 "CFG0_DV_REG28_PROXY," hexmask.long 0x70 0.--31. 1. "DV_REG28_BIT_PROXY,Defined by DV usage" line.long 0x74 "CFG0_DV_REG29_PROXY," hexmask.long 0x74 0.--31. 1. "DV_REG29_BIT_PROXY,Defined by DV usage" line.long 0x78 "CFG0_DV_REG30_PROXY," hexmask.long 0x78 0.--31. 1. "DV_REG30_BIT_PROXY,Defined by DV usage" line.long 0x7C "CFG0_DV_REG31_PROXY," hexmask.long 0x7C 0.--31. 1. "DV_REG31_BIT_PROXY,Defined by DV usage" line.long 0x80 "CFG0_DV_REG32_PROXY," hexmask.long 0x80 0.--31. 1. "DV_REG32_BIT_PROXY,Defined by DV usage" line.long 0x84 "CFG0_DV_REG33_PROXY," hexmask.long 0x84 0.--31. 1. "DV_REG33_BIT_PROXY,Defined by DV usage" line.long 0x88 "CFG0_DV_REG34_PROXY," hexmask.long 0x88 0.--31. 1. "DV_REG34_BIT_PROXY,Defined by DV usage" line.long 0x8C "CFG0_DV_REG35_PROXY," hexmask.long 0x8C 0.--31. 1. "DV_REG35_BIT_PROXY,Defined by DV usage" line.long 0x90 "CFG0_DV_REG36_PROXY," hexmask.long 0x90 0.--31. 1. "DV_REG36_BIT_PROXY,Defined by DV usage" line.long 0x94 "CFG0_DV_REG37_PROXY," hexmask.long 0x94 0.--31. 1. "DV_REG37_BIT_PROXY,Defined by DV usage" line.long 0x98 "CFG0_DV_REG38_PROXY," hexmask.long 0x98 0.--31. 1. "DV_REG38_BIT_PROXY,Defined by DV usage" line.long 0x9C "CFG0_DV_REG39_PROXY," hexmask.long 0x9C 0.--31. 1. "DV_REG39_BIT_PROXY,Defined by DV usage" line.long 0xA0 "CFG0_DV_REG40_PROXY," hexmask.long 0xA0 0.--31. 1. "DV_REG40_BIT_PROXY,Defined by DV usage" line.long 0xA4 "CFG0_DV_REG41_PROXY," hexmask.long 0xA4 0.--31. 1. "DV_REG41_BIT_PROXY,Defined by DV usage" line.long 0xA8 "CFG0_DV_REG42_PROXY," hexmask.long 0xA8 0.--31. 1. "DV_REG42_BIT_PROXY,Defined by DV usage" line.long 0xAC "CFG0_DV_REG43_PROXY," hexmask.long 0xAC 0.--31. 1. "DV_REG43_BIT_PROXY,Defined by DV usage" line.long 0xB0 "CFG0_DV_REG44_PROXY," hexmask.long 0xB0 0.--31. 1. "DV_REG44_BIT_PROXY,Defined by DV usage" line.long 0xB4 "CFG0_DV_REG45_PROXY," hexmask.long 0xB4 0.--31. 1. "DV_REG45_BIT_PROXY,Defined by DV usage" line.long 0xB8 "CFG0_DV_REG46_PROXY," hexmask.long 0xB8 0.--31. 1. "DV_REG46_BIT_PROXY,Defined by DV usage" line.long 0xBC "CFG0_DV_REG47_PROXY," hexmask.long 0xBC 0.--31. 1. "DV_REG47_BIT_PROXY,Defined by DV usage" line.long 0xC0 "CFG0_DV_REG48_PROXY," hexmask.long 0xC0 0.--31. 1. "DV_REG48_BIT_PROXY,Defined by DV usage" line.long 0xC4 "CFG0_DV_REG49_PROXY," hexmask.long 0xC4 0.--31. 1. "DV_REG49_BIT_PROXY,Defined by DV usage" line.long 0xC8 "CFG0_DV_REG50_PROXY," hexmask.long 0xC8 0.--31. 1. "DV_REG50_BIT_PROXY,Defined by DV usage" line.long 0xCC "CFG0_DV_REG51_PROXY," hexmask.long 0xCC 0.--31. 1. "DV_REG51_BIT_PROXY,Defined by DV usage" line.long 0xD0 "CFG0_DV_REG52_PROXY," hexmask.long 0xD0 0.--31. 1. "DV_REG52_BIT_PROXY,Defined by DV usage" line.long 0xD4 "CFG0_DV_REG53_PROXY," hexmask.long 0xD4 0.--31. 1. "DV_REG53_BIT_PROXY,Defined by DV usage" line.long 0xD8 "CFG0_DV_REG54_PROXY," hexmask.long 0xD8 0.--31. 1. "DV_REG54_BIT_PROXY,Defined by DV usage" line.long 0xDC "CFG0_DV_REG55_PROXY," hexmask.long 0xDC 0.--31. 1. "DV_REG55_BIT_PROXY,Defined by DV usage" line.long 0xE0 "CFG0_DV_REG56_PROXY," hexmask.long 0xE0 0.--31. 1. "DV_REG56_BIT_PROXY,Defined by DV usage" line.long 0xE4 "CFG0_DV_REG57_PROXY," hexmask.long 0xE4 0.--31. 1. "DV_REG57_BIT_PROXY,Defined by DV usage" line.long 0xE8 "CFG0_DV_REG58_PROXY," hexmask.long 0xE8 0.--31. 1. "DV_REG58_BIT_PROXY,Defined by DV usage" line.long 0xEC "CFG0_DV_REG59_PROXY," hexmask.long 0xEC 0.--31. 1. "DV_REG59_BIT_PROXY,Defined by DV usage" line.long 0xF0 "CFG0_DV_REG60_PROXY," hexmask.long 0xF0 0.--31. 1. "DV_REG60_BIT_PROXY,Defined by DV usage" line.long 0xF4 "CFG0_DV_REG61_PROXY," hexmask.long 0xF4 0.--31. 1. "DV_REG61_BIT_PROXY,Defined by DV usage" line.long 0xF8 "CFG0_DV_REG62_PROXY," hexmask.long 0xF8 0.--31. 1. "DV_REG62_BIT_PROXY,Defined by DV usage" line.long 0xFC "CFG0_DV_REG63_PROXY," hexmask.long 0xFC 0.--31. 1. "DV_REG63_BIT_PROXY,Defined by DV usage" rgroup.long 0x12200++0x7F line.long 0x0 "CFG0_DV_REG0_SET_PROXY," hexmask.long 0x0 0.--31. 1. "DV_REG0_SET_BIT_PROXY,Defined by DV usage" line.long 0x4 "CFG0_DV_REG1_SET_PROXY," hexmask.long 0x4 0.--31. 1. "DV_REG1_SET_BIT_PROXY,Defined by DV usage" line.long 0x8 "CFG0_DV_REG2_SET_PROXY," hexmask.long 0x8 0.--31. 1. "DV_REG2_SET_BIT_PROXY,Defined by DV usage" line.long 0xC "CFG0_DV_REG3_SET_PROXY," hexmask.long 0xC 0.--31. 1. "DV_REG3_SET_BIT_PROXY,Defined by DV usage" line.long 0x10 "CFG0_DV_REG4_SET_PROXY," hexmask.long 0x10 0.--31. 1. "DV_REG4_SET_BIT_PROXY,Defined by DV usage" line.long 0x14 "CFG0_DV_REG5_SET_PROXY," hexmask.long 0x14 0.--31. 1. "DV_REG5_SET_BIT_PROXY,Defined by DV usage" line.long 0x18 "CFG0_DV_REG6_SET_PROXY," hexmask.long 0x18 0.--31. 1. "DV_REG6_SET_BIT_PROXY,Defined by DV usage" line.long 0x1C "CFG0_DV_REG7_SET_PROXY," hexmask.long 0x1C 0.--31. 1. "DV_REG7_SET_BIT_PROXY,Defined by DV usage" line.long 0x20 "CFG0_DV_REG8_SET_PROXY," hexmask.long 0x20 0.--31. 1. "DV_REG8_SET_BIT_PROXY,Defined by DV usage" line.long 0x24 "CFG0_DV_REG9_SET_PROXY," hexmask.long 0x24 0.--31. 1. "DV_REG9_SET_BIT_PROXY,Defined by DV usage" line.long 0x28 "CFG0_DV_REG10_SET_PROXY," hexmask.long 0x28 0.--31. 1. "DV_REG10_SET_BIT_PROXY,Defined by DV usage" line.long 0x2C "CFG0_DV_REG11_SET_PROXY," hexmask.long 0x2C 0.--31. 1. "DV_REG11_SET_BIT_PROXY,Defined by DV usage" line.long 0x30 "CFG0_DV_REG12_SET_PROXY," hexmask.long 0x30 0.--31. 1. "DV_REG12_SET_BIT_PROXY,Defined by DV usage" line.long 0x34 "CFG0_DV_REG13_SET_PROXY," hexmask.long 0x34 0.--31. 1. "DV_REG13_SET_BIT_PROXY,Defined by DV usage" line.long 0x38 "CFG0_DV_REG14_SET_PROXY," hexmask.long 0x38 0.--31. 1. "DV_REG14_SET_BIT_PROXY,Defined by DV usage" line.long 0x3C "CFG0_DV_REG15_SET_PROXY," hexmask.long 0x3C 0.--31. 1. "DV_REG15_SET_BIT_PROXY,Defined by DV usage" line.long 0x40 "CFG0_DV_REG16_SET_PROXY," hexmask.long 0x40 0.--31. 1. "DV_REG16_SET_BIT_PROXY,Defined by DV usage" line.long 0x44 "CFG0_DV_REG17_SET_PROXY," hexmask.long 0x44 0.--31. 1. "DV_REG17_SET_BIT_PROXY,Defined by DV usage" line.long 0x48 "CFG0_DV_REG18_SET_PROXY," hexmask.long 0x48 0.--31. 1. "DV_REG18_SET_BIT_PROXY,Defined by DV usage" line.long 0x4C "CFG0_DV_REG19_SET_PROXY," hexmask.long 0x4C 0.--31. 1. "DV_REG19_SET_BIT_PROXY,Defined by DV usage" line.long 0x50 "CFG0_DV_REG20_SET_PROXY," hexmask.long 0x50 0.--31. 1. "DV_REG20_SET_BIT_PROXY,Defined by DV usage" line.long 0x54 "CFG0_DV_REG21_SET_PROXY," hexmask.long 0x54 0.--31. 1. "DV_REG21_SET_BIT_PROXY,Defined by DV usage" line.long 0x58 "CFG0_DV_REG22_SET_PROXY," hexmask.long 0x58 0.--31. 1. "DV_REG22_SET_BIT_PROXY,Defined by DV usage" line.long 0x5C "CFG0_DV_REG23_SET_PROXY," hexmask.long 0x5C 0.--31. 1. "DV_REG23_SET_BIT_PROXY,Defined by DV usage" line.long 0x60 "CFG0_DV_REG24_SET_PROXY," hexmask.long 0x60 0.--31. 1. "DV_REG24_SET_BIT_PROXY,Defined by DV usage" line.long 0x64 "CFG0_DV_REG25_SET_PROXY," hexmask.long 0x64 0.--31. 1. "DV_REG25_SET_BIT_PROXY,Defined by DV usage" line.long 0x68 "CFG0_DV_REG26_SET_PROXY," hexmask.long 0x68 0.--31. 1. "DV_REG26_SET_BIT_PROXY,Defined by DV usage" line.long 0x6C "CFG0_DV_REG27_SET_PROXY," hexmask.long 0x6C 0.--31. 1. "DV_REG27_SET_BIT_PROXY,Defined by DV usage" line.long 0x70 "CFG0_DV_REG28_SET_PROXY," hexmask.long 0x70 0.--31. 1. "DV_REG28_SET_BIT_PROXY,Defined by DV usage" line.long 0x74 "CFG0_DV_REG29_SET_PROXY," hexmask.long 0x74 0.--31. 1. "DV_REG29_SET_BIT_PROXY,Defined by DV usage" line.long 0x78 "CFG0_DV_REG30_SET_PROXY," hexmask.long 0x78 0.--31. 1. "DV_REG30_SET_BIT_PROXY,Defined by DV usage" line.long 0x7C "CFG0_DV_REG31_SET_PROXY," hexmask.long 0x7C 0.--31. 1. "DV_REG31_SET_BIT_PROXY,Defined by DV usage" rgroup.long 0x12300++0x7F line.long 0x0 "CFG0_DV_REG0_CLR_PROXY," hexmask.long 0x0 0.--31. 1. "DV_REG0_CLR_BIT_PROXY,Defined by DV usage" line.long 0x4 "CFG0_DV_REG1_CLR_PROXY," hexmask.long 0x4 0.--31. 1. "DV_REG1_CLR_BIT_PROXY,Defined by DV usage" line.long 0x8 "CFG0_DV_REG2_CLR_PROXY," hexmask.long 0x8 0.--31. 1. "DV_REG2_CLR_BIT_PROXY,Defined by DV usage" line.long 0xC "CFG0_DV_REG3_CLR_PROXY," hexmask.long 0xC 0.--31. 1. "DV_REG3_CLR_BIT_PROXY,Defined by DV usage" line.long 0x10 "CFG0_DV_REG4_CLR_PROXY," hexmask.long 0x10 0.--31. 1. "DV_REG4_CLR_BIT_PROXY,Defined by DV usage" line.long 0x14 "CFG0_DV_REG5_CLR_PROXY," hexmask.long 0x14 0.--31. 1. "DV_REG5_CLR_BIT_PROXY,Defined by DV usage" line.long 0x18 "CFG0_DV_REG6_CLR_PROXY," hexmask.long 0x18 0.--31. 1. "DV_REG6_CLR_BIT_PROXY,Defined by DV usage" line.long 0x1C "CFG0_DV_REG7_CLR_PROXY," hexmask.long 0x1C 0.--31. 1. "DV_REG7_CLR_BIT_PROXY,Defined by DV usage" line.long 0x20 "CFG0_DV_REG8_CLR_PROXY," hexmask.long 0x20 0.--31. 1. "DV_REG8_CLR_BIT_PROXY,Defined by DV usage" line.long 0x24 "CFG0_DV_REG9_CLR_PROXY," hexmask.long 0x24 0.--31. 1. "DV_REG9_CLR_BIT_PROXY,Defined by DV usage" line.long 0x28 "CFG0_DV_REG10_CLR_PROXY," hexmask.long 0x28 0.--31. 1. "DV_REG10_CLR_BIT_PROXY,Defined by DV usage" line.long 0x2C "CFG0_DV_REG11_CLR_PROXY," hexmask.long 0x2C 0.--31. 1. "DV_REG11_CLR_BIT_PROXY,Defined by DV usage" line.long 0x30 "CFG0_DV_REG12_CLR_PROXY," hexmask.long 0x30 0.--31. 1. "DV_REG12_CLR_BIT_PROXY,Defined by DV usage" line.long 0x34 "CFG0_DV_REG13_CLR_PROXY," hexmask.long 0x34 0.--31. 1. "DV_REG13_CLR_BIT_PROXY,Defined by DV usage" line.long 0x38 "CFG0_DV_REG14_CLR_PROXY," hexmask.long 0x38 0.--31. 1. "DV_REG14_CLR_BIT_PROXY,Defined by DV usage" line.long 0x3C "CFG0_DV_REG15_CLR_PROXY," hexmask.long 0x3C 0.--31. 1. "DV_REG15_CLR_BIT_PROXY,Defined by DV usage" line.long 0x40 "CFG0_DV_REG16_CLR_PROXY," hexmask.long 0x40 0.--31. 1. "DV_REG16_CLR_BIT_PROXY,Defined by DV usage" line.long 0x44 "CFG0_DV_REG17_CLR_PROXY," hexmask.long 0x44 0.--31. 1. "DV_REG17_CLR_BIT_PROXY,Defined by DV usage" line.long 0x48 "CFG0_DV_REG18_CLR_PROXY," hexmask.long 0x48 0.--31. 1. "DV_REG18_CLR_BIT_PROXY,Defined by DV usage" line.long 0x4C "CFG0_DV_REG19_CLR_PROXY," hexmask.long 0x4C 0.--31. 1. "DV_REG19_CLR_BIT_PROXY,Defined by DV usage" line.long 0x50 "CFG0_DV_REG20_CLR_PROXY," hexmask.long 0x50 0.--31. 1. "DV_REG20_CLR_BIT_PROXY,Defined by DV usage" line.long 0x54 "CFG0_DV_REG21_CLR_PROXY," hexmask.long 0x54 0.--31. 1. "DV_REG21_CLR_BIT_PROXY,Defined by DV usage" line.long 0x58 "CFG0_DV_REG22_CLR_PROXY," hexmask.long 0x58 0.--31. 1. "DV_REG22_CLR_BIT_PROXY,Defined by DV usage" line.long 0x5C "CFG0_DV_REG23_CLR_PROXY," hexmask.long 0x5C 0.--31. 1. "DV_REG23_CLR_BIT_PROXY,Defined by DV usage" line.long 0x60 "CFG0_DV_REG24_CLR_PROXY," hexmask.long 0x60 0.--31. 1. "DV_REG24_CLR_BIT_PROXY,Defined by DV usage" line.long 0x64 "CFG0_DV_REG25_CLR_PROXY," hexmask.long 0x64 0.--31. 1. "DV_REG25_CLR_BIT_PROXY,Defined by DV usage" line.long 0x68 "CFG0_DV_REG26_CLR_PROXY," hexmask.long 0x68 0.--31. 1. "DV_REG26_CLR_BIT_PROXY,Defined by DV usage" line.long 0x6C "CFG0_DV_REG27_CLR_PROXY," hexmask.long 0x6C 0.--31. 1. "DV_REG27_CLR_BIT_PROXY,Defined by DV usage" line.long 0x70 "CFG0_DV_REG28_CLR_PROXY," hexmask.long 0x70 0.--31. 1. "DV_REG28_CLR_BIT_PROXY,Defined by DV usage" line.long 0x74 "CFG0_DV_REG29_CLR_PROXY," hexmask.long 0x74 0.--31. 1. "DV_REG29_CLR_BIT_PROXY,Defined by DV usage" line.long 0x78 "CFG0_DV_REG30_CLR_PROXY," hexmask.long 0x78 0.--31. 1. "DV_REG30_CLR_BIT_PROXY,Defined by DV usage" line.long 0x7C "CFG0_DV_REG31_CLR_PROXY," hexmask.long 0x7C 0.--31. 1. "DV_REG31_CLR_BIT_PROXY,Defined by DV usage" rgroup.long 0x12400++0x3 line.long 0x0 "CFG0_LED_CTRL_PROXY," hexmask.long 0x0 1.--31. 1. "LED_CTRL_CONTROL_PROXY,Test control" newline rbitfld.long 0x0 0. "LED_CTRL_LED_MODE_PROXY,LED mode from decoded enable key" "0,1" rgroup.long 0x12408++0x3 line.long 0x0 "CFG0_LED_ENABLE_PROXY," hexmask.long 0x0 0.--31. 1. "LED_ENABLE_ENABLE_KEY_PROXY,LED mode entry key 32'h204C4544 - Set PADCONFIG registers to LED mode values others - PADCONFIG registers retain programmed values" rgroup.long 0x12420++0x13 line.long 0x0 "CFG0_LED_MCU_PLL_STAT_EN_PROXY," bitfld.long 0x0 2. "LED_MCU_PLL_STAT_EN_MCU_PLL2_EN_PROXY,Enable MCU_PLL2 lockloss in status generation" "0,1" newline bitfld.long 0x0 1. "LED_MCU_PLL_STAT_EN_MCU_PLL1_EN_PROXY,Enable MCU_PLL1 lockloss in status generation" "0,1" newline bitfld.long 0x0 0. "LED_MCU_PLL_STAT_EN_MCU_PLL0_EN_PROXY,Enable MCU_PLL0 lockloss in status generation" "0,1" line.long 0x4 "CFG0_LED_MAIN_PLL_STAT_EN_PROXY," bitfld.long 0x4 28. "LED_MAIN_PLL_STAT_EN_MAIN_PLL28_EN_PROXY,Enable MAIN_PLL28 lockloss in status generation" "0,1" newline bitfld.long 0x4 27. "LED_MAIN_PLL_STAT_EN_MAIN_PLL27_EN_PROXY,Enable MAIN_PLL27 lockloss in status generation" "0,1" newline bitfld.long 0x4 26. "LED_MAIN_PLL_STAT_EN_MAIN_PLL26_EN_PROXY,Enable MAIN_PLL26 lockloss in status generation" "0,1" newline bitfld.long 0x4 25. "LED_MAIN_PLL_STAT_EN_MAIN_PLL25_EN_PROXY,Enable MAIN_PLL25 lockloss in status generation" "0,1" newline bitfld.long 0x4 19. "LED_MAIN_PLL_STAT_EN_MAIN_PLL19_EN_PROXY,Enable MAIN_PLL19 lockloss in status generation" "0,1" newline bitfld.long 0x4 17. "LED_MAIN_PLL_STAT_EN_MAIN_PLL17_EN_PROXY,Enable MAIN_PLL17 lockloss in status generation" "0,1" newline bitfld.long 0x4 16. "LED_MAIN_PLL_STAT_EN_MAIN_PLL16_EN_PROXY,Enable MAIN_PLL16 lockloss in status generation" "0,1" newline bitfld.long 0x4 14. "LED_MAIN_PLL_STAT_EN_MAIN_PLL14_EN_PROXY,Enable MAIN_PLL14 lockloss in status generation" "0,1" newline bitfld.long 0x4 12. "LED_MAIN_PLL_STAT_EN_MAIN_PLL12_EN_PROXY,Enable MAIN_PLL12 lockloss in status generation" "0,1" newline bitfld.long 0x4 9. "LED_MAIN_PLL_STAT_EN_MAIN_PLL9_EN_PROXY,Enable MAIN_PLL9 lockloss in status generation" "0,1" newline bitfld.long 0x4 8. "LED_MAIN_PLL_STAT_EN_MAIN_PLL8_EN_PROXY,Enable MAIN_PLL8 lockloss in status generation" "0,1" newline bitfld.long 0x4 7. "LED_MAIN_PLL_STAT_EN_MAIN_PLL7_EN_PROXY,Enable MAIN_PLL7 lockloss in status generation" "0,1" newline bitfld.long 0x4 6. "LED_MAIN_PLL_STAT_EN_MAIN_PLL6_EN_PROXY,Enable MAIN_PLL6 lockloss in status generation" "0,1" newline bitfld.long 0x4 5. "LED_MAIN_PLL_STAT_EN_MAIN_PLL5_EN_PROXY,Enable MAIN_PLL5 lockloss in status generation" "0,1" newline bitfld.long 0x4 4. "LED_MAIN_PLL_STAT_EN_MAIN_PLL4_EN_PROXY,Enable MAIN_PLL4 lockloss in status generation" "0,1" newline bitfld.long 0x4 3. "LED_MAIN_PLL_STAT_EN_MAIN_PLL3_EN_PROXY,Enable MAIN_PLL3 lockloss in status generation" "0,1" newline bitfld.long 0x4 2. "LED_MAIN_PLL_STAT_EN_MAIN_PLL2_EN_PROXY,Enable MAIN_PLL2 lockloss in status generation" "0,1" newline bitfld.long 0x4 1. "LED_MAIN_PLL_STAT_EN_MAIN_PLL1_EN_PROXY,Enable MAIN_PLL1 lockloss in status generation" "0,1" newline bitfld.long 0x4 0. "LED_MAIN_PLL_STAT_EN_MAIN_PLL0_EN_PROXY,Enable MAIN_PLL0 lockloss in status generation" "0,1" line.long 0x8 "CFG0_LED_PGD_STAT_EN_PROXY," bitfld.long 0x8 13. "LED_PGD_STAT_EN_VDDR_CPU1_EN_PROXY,Enable vddr_cpu1 PGD in status generation" "0,1" newline bitfld.long 0x8 12. "LED_PGD_STAT_EN_VDD_CPU1_EN_PROXY,Enable vdd_cpu1 PGD in status generation" "0,1" newline bitfld.long 0x8 11. "LED_PGD_STAT_EN_VDDR_CORE_EN_PROXY,Enable vddr_core PGD in status generation" "0,1" newline bitfld.long 0x8 10. "LED_PGD_STAT_EN_VDDR_CPU_EN_PROXY,Enable vddr_cpu PGD in status generation" "0,1" newline bitfld.long 0x8 9. "LED_PGD_STAT_EN_VDD_CORE_EN_PROXY,Enable vdd_core PGD in status generation" "0,1" newline bitfld.long 0x8 8. "LED_PGD_STAT_EN_VDD_CPU_EN_PROXY,Enable vdd_cpu PGD in status generation" "0,1" newline bitfld.long 0x8 1. "LED_PGD_STAT_EN_VDDR_MCU_EN_PROXY,Enable vddr_mcu PGD in status generation" "0,1" newline bitfld.long 0x8 0. "LED_PGD_STAT_EN_VDD_MCU_EN_PROXY,Enable vdd_mcu PGD in status generation" "0,1" line.long 0xC "CFG0_LED_EFC_STAT_EN_PROXY," bitfld.long 0xC 8. "LED_EFC_STAT_EN_MAIN_EFC_EN_PROXY,Enable MAIN eFuse Ctrl PGD in status generation" "0,1" newline bitfld.long 0xC 0. "LED_EFC_STAT_EN_MCU_EFC_EN_PROXY,Enable MCU eFuse Ctrl PGD in status generation" "0,1" line.long 0x10 "CFG0_LED_STATUS_CTRL_PROXY," bitfld.long 0x10 8. "LED_STATUS_CTRL_STICKY_EN_PROXY,Sticky status enable. Selects which version of status to output on the pin. 0 - Use real-time status signal 1 - Use sticky status signal" "0: Use real-time status signal 1,?" newline bitfld.long 0x10 0. "LED_STATUS_CTRL_STICKY_STATUS_PROXY,Sticky status bit. This bit captures the falling edge of the status signal" "0,1" rgroup.long 0x12480++0x1F line.long 0x0 "CFG0_SIM_CFG0_PROXY," hexmask.long 0x0 0.--31. 1. "SIM_CFG0_CFG_INFO_PROXY,Model configuration info. Bit usage is determined by AVV team." line.long 0x4 "CFG0_SIM_CFG1_PROXY," hexmask.long 0x4 0.--31. 1. "SIM_CFG1_CFG_INFO_PROXY,Model configuration info. Bit usage is determined by AVV team." line.long 0x8 "CFG0_SIM_CFG2_PROXY," hexmask.long 0x8 0.--31. 1. "SIM_CFG2_CFG_INFO_PROXY,Model configuration info. Bit usage is determined by AVV team." line.long 0xC "CFG0_SIM_CFG3_PROXY," hexmask.long 0xC 0.--31. 1. "SIM_CFG3_CFG_INFO_PROXY,Model configuration info. Bit usage is determined by AVV team." line.long 0x10 "CFG0_SIM_CFG4_PROXY," hexmask.long 0x10 0.--31. 1. "SIM_CFG4_CFG_INFO_PROXY,Model configuration info. Bit usage is determined by AVV team." line.long 0x14 "CFG0_SIM_CFG5_PROXY," hexmask.long 0x14 0.--31. 1. "SIM_CFG5_CFG_INFO_PROXY,Model configuration info. Bit usage is determined by AVV team." line.long 0x18 "CFG0_SIM_CFG6_PROXY," hexmask.long 0x18 0.--31. 1. "SIM_CFG6_CFG_INFO_PROXY,Model configuration info. Bit usage is determined by AVV team." line.long 0x1C "CFG0_SIM_CFG7_PROXY," hexmask.long 0x1C 0.--31. 1. "SIM_CFG7_CFG_INFO_PROXY,Model configuration info. Bit usage is determined by AVV team." rgroup.long 0x12500++0x27 line.long 0x0 "CFG0_WKUP_MRGN_MODE0_PROXY," hexmask.long.word 0x0 0.--11. 1. "WKUP_MRGN_MODE0_HS2PARF_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x4 "CFG0_WKUP_MRGN_MODE1_PROXY," hexmask.long.word 0x4 0.--11. 1. "WKUP_MRGN_MODE1_HDDP_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x8 "CFG0_WKUP_MRGN_MODE2_PROXY," hexmask.long.word 0x8 0.--11. 1. "WKUP_MRGN_MODE2_EHDSP_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0xC "CFG0_WKUP_MRGN_MODE3_PROXY," hexmask.long.word 0xC 0.--11. 1. "WKUP_MRGN_MODE3_HD2PRF_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x10 "CFG0_WKUP_MRGN_MODE4_PROXY," hexmask.long.word 0x10 0.--11. 1. "WKUP_MRGN_MODE4_UHD2PRF_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x14 "CFG0_WKUP_MRGN_MODE5_PROXY," hexmask.long.word 0x14 0.--11. 1. "WKUP_MRGN_MODE5_ROM_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x18 "CFG0_WKUP_MRGN_MODE6_PROXY," hexmask.long.word 0x18 0.--11. 1. "WKUP_MRGN_MODE6_HDSP_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x1C "CFG0_WKUP_MRGN_MODE7_PROXY," hexmask.long.word 0x1C 0.--11. 1. "WKUP_MRGN_MODE7_HSSP_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x20 "CFG0_WKUP_MRGN_MODE8_PROXY," hexmask.long.word 0x20 0.--11. 1. "WKUP_MRGN_MODE8_HD1PRF_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" line.long 0x24 "CFG0_WKUP_MRGN_MODE9_PROXY," hexmask.long.word 0x24 0.--11. 1. "WKUP_MRGN_MODE9_HS1PRF_MEM_MRGN_ASST_PROXY,DFT memory margin control Bits 0-3 - dft_mem_margin Bits 4-5 - dft_mem_ra Bits 6-8 - dft_mem_wa Bits 9-11 - dft_wpulse" rgroup.long 0x12700++0x3 line.long 0x0 "CFG0_ATEST_RCOSC_PROXY," bitfld.long 0x0 7. "ATEST_RCOSC_ATEST_EN_PROXY,Test enable 1'b0 - Disable (atestout is floating) 1'b1 - Enable (see atest_test)" "0: Disable,1: Enable" newline bitfld.long 0x0 0.--1. "ATEST_RCOSC_ATEST_SEL_PROXY,Test select When atest_en = 1 2'b0x - Hi-Z (Test 3) 2'b10 - Bias current (Test 1) 2'b11 - VREF (Test 2)" "?,?,2: Bias current,3: VREF" rgroup.long 0x12720++0x7 line.long 0x0 "CFG0_ATEST_HFOSC0_PROXY," bitfld.long 0x0 0. "ATEST_HFOSC0_TEST_EN_C_PROXY,Test enable 1'b0 - Output test current disabled 1'b1 - Test current enabled" "0: Output test current disabled 1'b1,?" line.long 0x4 "CFG0_ATEST_HFOSC1_PROXY," bitfld.long 0x4 0. "ATEST_HFOSC1_TEST_EN_C_PROXY,Test enable 1'b0 - Output test current disabled 1'b1 - Test current enabled" "0: Output test current disabled 1'b1,?" rgroup.long 0x12740++0x17 line.long 0x0 "CFG0_ATEST_POR_PROXY," bitfld.long 0x0 8.--10. "ATEST_POR_SEL_ATESTIN_PROXY,Test select 3'b000 - Test Modes 0-4 See sel_atest value 3'b001 - Test Mode 5 when sel_atest = 6'b001111 Others - N/A (Hi-Z at ATEST_OUT)" "0: Test Modes 0-4,1: Test Mode 5 when sel_atest = 6'b001111 Others,?,?,?,?,?,?" newline hexmask.long.byte 0x0 0.--5. 1. "ATEST_POR_SEL_ATEST_PROXY,Test select 6'b000000 to 001010 - Bandgap TestT (Test Mode 1) 6'b001001 to 001111 - Hi-Z (when sel_atestin = 3'b000) 6'b001001 to 001111 - HVPOR Test (when sel_atestin = 3'b001) 6'b01xx00 to 01xx11 - POKHV Test (Test Mode.." line.long 0x4 "CFG0_ATEST_POK_VDDA_MCU_UV_CTRL_PROXY," bitfld.long 0x4 0.--2. "ATEST_POK_VDDA_MCU_UV_CTRL_POK_ATMUXSEL_PROXY,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0x8 "CFG0_ATEST_POK_VDDA_MCU_OV_CTRL_PROXY," bitfld.long 0x8 0.--2. "ATEST_POK_VDDA_MCU_OV_CTRL_POK_ATMUXSEL_PROXY,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0xC "CFG0_ATEST_POK_VDD_MCU_UV_CTRL_PROXY," bitfld.long 0xC 0.--2. "ATEST_POK_VDD_MCU_UV_CTRL_POK_ATMUXSEL_PROXY,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0x10 "CFG0_ATEST_POK_VDDA_PMIC_IN_PROXY," bitfld.long 0x10 0.--2. "ATEST_POK_VDDA_PMIC_IN_POK_ATMUXSEL_PROXY,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0x14 "CFG0_ATEST_POK_VDD_MCU_OV_CTRL_PROXY," bitfld.long 0x14 0.--2. "ATEST_POK_VDD_MCU_OV_CTRL_POK_ATMUXSEL_PROXY,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" rgroup.long 0x12760++0xB line.long 0x0 "CFG0_ATEST_POK_VDDSHV_WKUP_GEN_CTRL_PROXY," bitfld.long 0x0 0.--2. "ATEST_POK_VDDSHV_WKUP_GEN_CTRL_POK_ATMUXSEL_PROXY,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0x4 "CFG0_ATEST_POK_VDDR_MCU_CTRL_PROXY," bitfld.long 0x4 0.--2. "ATEST_POK_VDDR_MCU_CTRL_POK_ATMUXSEL_PROXY,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0x8 "CFG0_ATEST_POK_VMON_CAP_MCU_GEN_CTRL_PROXY," bitfld.long 0x8 0.--2. "ATEST_POK_VMON_CAP_MCU_GEN_CTRL_POK_ATMUXSEL_PROXY,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" rgroup.long 0x12780++0x1B line.long 0x0 "CFG0_ATEST_POK_VDD_CORE_CTRL_PROXY," bitfld.long 0x0 0.--2. "ATEST_POK_VDD_CORE_CTRL_POK_ATMUXSEL_PROXY,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0x4 "CFG0_ATEST_POK_VDD_CPU_CTRL_PROXY," bitfld.long 0x4 0.--2. "ATEST_POK_VDD_CPU_CTRL_POK_ATMUXSEL_PROXY,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0x8 "CFG0_ATEST_POK_VMON_EXT_CTRL_PROXY," bitfld.long 0x8 0.--2. "ATEST_POK_VMON_EXT_CTRL_POK_ATMUXSEL_PROXY,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0xC "CFG0_ATEST_POK_VDDR_CORE_CTRL_PROXY," bitfld.long 0xC 0.--2. "ATEST_POK_VDDR_CORE_CTRL_POK_ATMUXSEL_PROXY,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0x10 "CFG0_ATEST_POK_VMON_EXT_MAIN1P8_CTRL_PROXY," bitfld.long 0x10 0.--2. "ATEST_POK_VMON_EXT_MAIN1P8_CTRL_POK_ATMUXSEL_PROXY,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0x14 "CFG0_ATEST_POK_VMON_EXT_MAIN3P3_CTRL_PROXY," bitfld.long 0x14 0.--2. "ATEST_POK_VMON_EXT_MAIN3P3_CTRL_POK_ATMUXSEL_PROXY,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" line.long 0x18 "CFG0_ATEST_POK_VDD_CPU1_CTRL_PROXY," bitfld.long 0x18 0.--2. "ATEST_POK_VDD_CPU1_CTRL_POK_ATMUXSEL_PROXY,Analog test mux select 2'b000 - HI-Z 2'b001 - IREF 2'b101 - VREF 2'b111 - RESDIV_VREF" "0: HI-Z 2'b001,?,?,?,?,5: VREF 2'b111,?,?" rgroup.long 0x13008++0x7 line.long 0x0 "CFG0_LOCK4_KICK0_PROXY," hexmask.long 0x0 0.--31. 1. "LOCK4_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK4_KICK1_PROXY," hexmask.long 0x4 0.--31. 1. "LOCK4_KICK1_PROXY,- KICK1 component" rgroup.long 0x13100++0x3F line.long 0x0 "CFG0_CLAIMREG_P4_R0," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P4_R0,Claim bits for Partition 4" line.long 0x4 "CFG0_CLAIMREG_P4_R1," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P4_R1,Claim bits for Partition 4" line.long 0x8 "CFG0_CLAIMREG_P4_R2," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P4_R2,Claim bits for Partition 4" line.long 0xC "CFG0_CLAIMREG_P4_R3," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P4_R3,Claim bits for Partition 4" line.long 0x10 "CFG0_CLAIMREG_P4_R4," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P4_R4,Claim bits for Partition 4" line.long 0x14 "CFG0_CLAIMREG_P4_R5," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P4_R5,Claim bits for Partition 4" line.long 0x18 "CFG0_CLAIMREG_P4_R6," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P4_R6,Claim bits for Partition 4" line.long 0x1C "CFG0_CLAIMREG_P4_R7," hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P4_R7,Claim bits for Partition 4" line.long 0x20 "CFG0_CLAIMREG_P4_R8," hexmask.long 0x20 0.--31. 1. "CLAIMREG_P4_R8,Claim bits for Partition 4" line.long 0x24 "CFG0_CLAIMREG_P4_R9," hexmask.long 0x24 0.--31. 1. "CLAIMREG_P4_R9,Claim bits for Partition 4" line.long 0x28 "CFG0_CLAIMREG_P4_R10," hexmask.long 0x28 0.--31. 1. "CLAIMREG_P4_R10,Claim bits for Partition 4" line.long 0x2C "CFG0_CLAIMREG_P4_R11," hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P4_R11,Claim bits for Partition 4" line.long 0x30 "CFG0_CLAIMREG_P4_R12," hexmask.long 0x30 0.--31. 1. "CLAIMREG_P4_R12,Claim bits for Partition 4" line.long 0x34 "CFG0_CLAIMREG_P4_R13," hexmask.long 0x34 0.--31. 1. "CLAIMREG_P4_R13,Claim bits for Partition 4" line.long 0x38 "CFG0_CLAIMREG_P4_R14," hexmask.long 0x38 0.--31. 1. "CLAIMREG_P4_R14,Claim bits for Partition 4" line.long 0x3C "CFG0_CLAIMREG_P4_R15," hexmask.long 0x3C 0.--31. 1. "CLAIMREG_P4_R15,Claim bits for Partition 4" rgroup.long 0x14040++0x3 line.long 0x0 "CFG0_FW_CTRL_OUT0," bitfld.long 0x0 3. "FW_CTRL_OUT0_EMMC_RET1,Reflects the value of the corresponding bit in fw_ctrl_out SMS output bus. This bit is used by SOC to drive an AO signal that will eventually be expanded into a complementary pair (RET + RET_B) at the boundary of EMMC-PHY.." "0,1" newline bitfld.long 0x0 2. "FW_CTRL_OUT0_EMMC_RET0,Reflects the value of the corresponding bit in fw_ctrl_out SMS output bus. This bit is used by SOC to drive an AO signal that will eventually be expanded into a complementary pair (RET + RET_B) at the boundary of EMMC-PHY.." "0,1" newline bitfld.long 0x0 0.--1. "FW_CTRL_OUT0_IO_PM_CTRL,This value is used by DMSC/SMS firmware to apply the DS (deep/deeper-sleep) values at once by qualifying the generation of the integration signal to the dsen_qualified to the IOs. These 2 bits are used in conjunction with.." "0: The active/normal mode pad-config defined values..,1: The DS value,?,?" rgroup.long 0x14044++0x7 line.long 0x0 "CFG0_FW_CTRL_OUT0_SET," bitfld.long 0x0 3. "FW_CTRL_OUT0_SET_EMMC_RET1,Sets the value of the corresponding bit in fw_ctrl_out SMS output bus. This bit is used by SOC to drive an AO signal that will eventually be expanded into a complementary pair (RET + RET_B) at the boundary of EMMC-PHY.." "0,1" newline bitfld.long 0x0 2. "FW_CTRL_OUT0_SET_EMMC_RET0,Sets the value of the corresponding bit in fw_ctrl_out SMS output bus. This bit is used by SOC to drive an AO signal that will eventually be expanded into a complementary pair (RET + RET_B) at the boundary of EMMC-PHY.." "0,1" newline bitfld.long 0x0 1. "FW_CTRL_OUT0_SET_IO_PM_CTRL_1,This MMR bit is a W1ts bit field for MMR-bit-field FW_CTRL_OUT0.io_pm_ctrl1" "0,1" newline bitfld.long 0x0 0. "FW_CTRL_OUT0_SET_IO_PM_CTRL_0,This MMR bit is a W1ts bit field for MMR-bit-field FW_CTRL_OUT0.io_pm_ctrl0" "0,1" line.long 0x4 "CFG0_FW_CTRL_OUT0_CLR," bitfld.long 0x4 3. "FW_CTRL_OUT0_CLR_EMMC_RET1,Clears the value of the corresponding bit in fw_ctrl_out SMS output bus. This bit is used by SOC to drive an AO signal that will eventually be expanded into a complementary pair (RET + RET_B) at the boundary of EMMC-PHY.." "0,1" newline bitfld.long 0x4 2. "FW_CTRL_OUT0_CLR_EMMC_RET0,Clears the value of the corresponding bit in fw_ctrl_out SMS output bus. This bit is used by SOC to drive an AO signal that will eventually be expanded into a complementary pair (RET + RET_B) at the boundary of EMMC-PHY.." "0,1" newline bitfld.long 0x4 1. "FW_CTRL_OUT0_CLR_IO_PM_CTRL_1,This MMR bit is a W1ts bit field for MMR-bit-field FW_CTRL_OUT0.io_pm_ctrl1" "0,1" newline bitfld.long 0x4 0. "FW_CTRL_OUT0_CLR_IO_PM_CTRL_0,This MMR bit is a W1ts bit field for MMR-bit-field FW_CTRL_OUT0.io_pm_ctrl0" "0,1" rgroup.long 0x14080++0xB line.long 0x0 "CFG0_PMCTRL_SYS," bitfld.long 0x0 4. "PMCTRL_SYS_PMIC_EN,PMIC enable. In order to write to this field you need to write 1 in the same access to field pmic_en_we. NOTE: This MMR bit does not reflect any contribution from any debug related signal. 0 - Drives PMIC_EN output port to 0 .." "0: Drives PMIC_EN output port to 0,1: Drives PMIC_EN output port to 1" line.long 0x4 "CFG0_PMCTRL_IO_0," rbitfld.long 0x4 25. "PMCTRL_IO_0_IO_ISO_STATUS_0,IO ISO Status 0 - IO isolation not active 1 - IO isolation active. Reflects value of SMS input port io_isoack coming back from IO pad ring" "0: IO isolation not active 1,?" newline bitfld.long 0x4 24. "PMCTRL_IO_0_IO_ISO_CTRL_0,IO ISO control. 0 - Turn off the IO isolation 1 - Turn on the IO isolation" "0: Turn off the IO isolation 1,?" newline bitfld.long 0x4 16. "PMCTRL_IO_0_GLOBAL_WUEN_0,Global IO wakeup enable. This is a gating condition to all individual IO WUEN coming from control module. Gating is done in the Spinner logic. 0 - All individual IO WUEN are gated in the Spinner logic (override to 0). 1 -.." "0: All individual IO WUEN are gated in the Spinner..,1: All individual IO WUEN from control module are.." newline rbitfld.long 0x4 9. "PMCTRL_IO_0_WUCLK_STATUS_0,Reflects value of SMS input port io_wuclkack coming back from IO pad ring" "0,1" newline bitfld.long 0x4 8. "PMCTRL_IO_0_WUCLK_CTRL_0,Direct control on WUCLKIN signal to IO pad ring. 0 - WUCLKIN signal is driven to 0. IO wakeup daisy chain is functional as well as IO whose wakeup feature is enabled. 1 - WUCLKIN signal is driven to 1. IO wakeup daisy chain is.." "0: WUCLKIN signal is driven to 0,1: WUCLKIN signal is driven to 1" newline bitfld.long 0x4 6. "PMCTRL_IO_0_ISOBYBASS_OVR_0,This MMR bit drives directly SMS output port io_isobypass0." "0,1" newline rbitfld.long 0x4 5. "PMCTRL_IO_0_IO_ON_STATUS_0,Gives the functional status of the IO ring. 0 - Part or all of the IOs are not in the ON state that is are in isolation state. 1 - All IOs are in the ON state. io_on_status = assign 1 if (io_iso == 0 & io_isoack==0 &.." "0: Part or all of the IOs are not in the ON state..,1: All IOs are in the ON state" newline bitfld.long 0x4 4. "PMCTRL_IO_0_ISOOVR_EXTEND_0,Control for IO isolation extension This drives the SOC chain ISO-OVERRIDE global control. This bit drives directly the SMS output port io_isoovr0. At the SOC level it is used to enable when 1 or gate-off when 0 the.." "0: IO isolation is not extended,1: IO isolation is extended" newline rbitfld.long 0x4 1. "PMCTRL_IO_0_ISOCLK_STATUS_0,Reflects value of io_isoclkack coming back from IO pad ring." "0,1" newline bitfld.long 0x4 0. "PMCTRL_IO_0_ISOCLK_OVRD_0,Override control on ISOCLKIN signal to IO pad ring. When not overridden this signal is controlled by hardware only. 0 - ISOCLKIN signal is not overriden. 1 - ISOCLKIN signal is overridden to active value (1)." "0: ISOCLKIN signal is not overriden,1: ISOCLKIN signal is overridden to active value" line.long 0x8 "CFG0_PMCTRL_IO_1," rbitfld.long 0x8 25. "PMCTRL_IO_1_IO_ISO_STATUS_1,IO ISO Status 0 - IO isolation not active 1 - IO isolation active. Reflects value of SMS input port io_isoack coming back from IO pad ring" "0: IO isolation not active 1,?" newline bitfld.long 0x8 24. "PMCTRL_IO_1_IO_ISO_CTRL_1,IO ISO control. 0 - Turn off the IO isolation 1 - Turn on the IO isolation" "0: Turn off the IO isolation 1,?" newline bitfld.long 0x8 16. "PMCTRL_IO_1_GLOBAL_WUEN_1,Global IO wakeup enable. This is a gating condition to all individual IO WUEN coming from control module. Gating is done in the Spinner logic. 0 - All individual IO WUEN are gated in the Spinner logic (override to 0). 1 -.." "0: All individual IO WUEN are gated in the Spinner..,1: All individual IO WUEN from control module are.." newline rbitfld.long 0x8 9. "PMCTRL_IO_1_WUCLK_STATUS_1,Reflects value of SMS input port io_wuclkack coming back from IO pad ring" "0,1" newline bitfld.long 0x8 8. "PMCTRL_IO_1_WUCLK_CTRL_1,Direct control on WUCLKIN signal to IO pad ring. 0 - WUCLKIN signal is driven to 0. IO wakeup daisy chain is functional as well as IO whose wakeup feature is enabled. 1 - WUCLKIN signal is driven to 1. IO wakeup daisy chain is.." "0: WUCLKIN signal is driven to 0,1: WUCLKIN signal is driven to 1" newline bitfld.long 0x8 6. "PMCTRL_IO_1_ISOBYBASS_OVR_1,This MMR bit drives directly SMS output port io_isobypassundefined." "0,1" newline rbitfld.long 0x8 5. "PMCTRL_IO_1_IO_ON_STATUS_1,Gives the functional status of the IO ring. 0 - Part or all of the IOs are not in the ON state that is are in isolation state. 1 - All IOs are in the ON state. io_on_status = assign 1 if (io_iso == 0 & io_isoack==0 &.." "0: Part or all of the IOs are not in the ON state..,1: All IOs are in the ON state" newline bitfld.long 0x8 4. "PMCTRL_IO_1_ISOOVR_EXTEND_1,Control for IO isolation extension This drives the SOC chain ISO-OVERRIDE global control. This bit drives directly the SMS output port io_isoovrundefined. At the SOC level it is used to enable when 1 or gate-off when 0 the.." "0: IO isolation is not extended,1: IO isolation is extended" newline rbitfld.long 0x8 1. "PMCTRL_IO_1_ISOCLK_STATUS_1,Reflects value of io_isoclkack coming back from IO pad ring." "0,1" newline bitfld.long 0x8 0. "PMCTRL_IO_1_ISOCLK_OVRD_1,Override control on ISOCLKIN signal to IO pad ring. When not overridden this signal is controlled by hardware only. 0 - ISOCLKIN signal is not overriden. 1 - ISOCLKIN signal is overridden to active value (1)." "0: ISOCLKIN signal is not overriden,1: ISOCLKIN signal is overridden to active value" rgroup.long 0x14300++0x3 line.long 0x0 "CFG0_PM_PERMISSION," bitfld.long 0x0 0. "PM_PERMISSION_DEBUG_ACTIVE,Debug mode activated Tells PM-FW that it should not power-OFF supplies externally. The debugger being active should also cause the SMS hardware to override the external rail state during deeperSleep by forcing high the.." "0: Debug not activated 1,?" rgroup.long 0x14400++0x3 line.long 0x0 "CFG0_SMS_WFI_STATUS," bitfld.long 0x0 1. "SMS_WFI_STATUS_HSM_M4_WFI,Indicates WFI status of the HSM M4 processor in SMS 0 - Normal operation 1 - M4 is in WFI state" "0: Normal operation 1,?" newline bitfld.long 0x0 0. "SMS_WFI_STATUS_TIFS_M4_WFI,Indicates WFI status of the TIFS M4 processor in SMS 0 - Normal operation 1 - M4 is in WFI state" "0: Normal operation 1,?" rgroup.long 0x15008++0x7 line.long 0x0 "CFG0_LOCK5_KICK0," hexmask.long 0x0 0.--31. 1. "LOCK5_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK5_KICK1," hexmask.long 0x4 0.--31. 1. "LOCK5_KICK1,- KICK1 component" rgroup.long 0x15100++0x23 line.long 0x0 "CFG0_CLAIMREG_P5_R0_READONLY," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P5_R0_READONLY,Claim bits for Partition 5" line.long 0x4 "CFG0_CLAIMREG_P5_R1_READONLY," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P5_R1_READONLY,Claim bits for Partition 5" line.long 0x8 "CFG0_CLAIMREG_P5_R2_READONLY," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P5_R2_READONLY,Claim bits for Partition 5" line.long 0xC "CFG0_CLAIMREG_P5_R3_READONLY," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P5_R3_READONLY,Claim bits for Partition 5" line.long 0x10 "CFG0_CLAIMREG_P5_R4_READONLY," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P5_R4_READONLY,Claim bits for Partition 5" line.long 0x14 "CFG0_CLAIMREG_P5_R5_READONLY," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P5_R5_READONLY,Claim bits for Partition 5" line.long 0x18 "CFG0_CLAIMREG_P5_R6_READONLY," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P5_R6_READONLY,Claim bits for Partition 5" line.long 0x1C "CFG0_CLAIMREG_P5_R7_READONLY," hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P5_R7_READONLY,Claim bits for Partition 5" line.long 0x20 "CFG0_CLAIMREG_P5_R8_READONLY," hexmask.long 0x20 0.--31. 1. "CLAIMREG_P5_R8_READONLY,Claim bits for Partition 5" rgroup.long 0x16040++0x3 line.long 0x0 "CFG0_FW_CTRL_OUT0_PROXY," bitfld.long 0x0 3. "FW_CTRL_OUT0_EMMC_RET1_PROXY,Reflects the value of the corresponding bit in fw_ctrl_out SMS output bus. This bit is used by SOC to drive an AO signal that will eventually be expanded into a complementary pair (RET + RET_B) at the boundary of EMMC-PHY.." "0,1" newline bitfld.long 0x0 2. "FW_CTRL_OUT0_EMMC_RET0_PROXY,Reflects the value of the corresponding bit in fw_ctrl_out SMS output bus. This bit is used by SOC to drive an AO signal that will eventually be expanded into a complementary pair (RET + RET_B) at the boundary of EMMC-PHY.." "0,1" newline bitfld.long 0x0 0.--1. "FW_CTRL_OUT0_IO_PM_CTRL_PROXY,This value is used by DMSC/SMS firmware to apply the DS (deep/deeper-sleep) values at once by qualifying the generation of the integration signal to the dsen_qualified to the IOs. These 2 bits are used in conjunction.." "0: The active/normal mode pad-config defined values..,1: The DS value,?,?" rgroup.long 0x16044++0x7 line.long 0x0 "CFG0_FW_CTRL_OUT0_SET_PROXY," bitfld.long 0x0 3. "FW_CTRL_OUT0_SET_EMMC_RET1_PROXY,Sets the value of the corresponding bit in fw_ctrl_out SMS output bus. This bit is used by SOC to drive an AO signal that will eventually be expanded into a complementary pair (RET + RET_B) at the boundary of EMMC-PHY.." "0,1" newline bitfld.long 0x0 2. "FW_CTRL_OUT0_SET_EMMC_RET0_PROXY,Sets the value of the corresponding bit in fw_ctrl_out SMS output bus. This bit is used by SOC to drive an AO signal that will eventually be expanded into a complementary pair (RET + RET_B) at the boundary of EMMC-PHY.." "0,1" newline bitfld.long 0x0 1. "FW_CTRL_OUT0_SET_IO_PM_CTRL_1_PROXY,This MMR bit is a W1ts bit field for MMR-bit-field FW_CTRL_OUT0.io_pm_ctrl1" "0,1" newline bitfld.long 0x0 0. "FW_CTRL_OUT0_SET_IO_PM_CTRL_0_PROXY,This MMR bit is a W1ts bit field for MMR-bit-field FW_CTRL_OUT0.io_pm_ctrl0" "0,1" line.long 0x4 "CFG0_FW_CTRL_OUT0_CLR_PROXY," bitfld.long 0x4 3. "FW_CTRL_OUT0_CLR_EMMC_RET1_PROXY,Clears the value of the corresponding bit in fw_ctrl_out SMS output bus. This bit is used by SOC to drive an AO signal that will eventually be expanded into a complementary pair (RET + RET_B) at the boundary of.." "0,1" newline bitfld.long 0x4 2. "FW_CTRL_OUT0_CLR_EMMC_RET0_PROXY,Clears the value of the corresponding bit in fw_ctrl_out SMS output bus. This bit is used by SOC to drive an AO signal that will eventually be expanded into a complementary pair (RET + RET_B) at the boundary of.." "0,1" newline bitfld.long 0x4 1. "FW_CTRL_OUT0_CLR_IO_PM_CTRL_1_PROXY,This MMR bit is a W1ts bit field for MMR-bit-field FW_CTRL_OUT0.io_pm_ctrl1" "0,1" newline bitfld.long 0x4 0. "FW_CTRL_OUT0_CLR_IO_PM_CTRL_0_PROXY,This MMR bit is a W1ts bit field for MMR-bit-field FW_CTRL_OUT0.io_pm_ctrl0" "0,1" rgroup.long 0x16080++0xB line.long 0x0 "CFG0_PMCTRL_SYS_PROXY," bitfld.long 0x0 4. "PMCTRL_SYS_PMIC_EN_PROXY,PMIC enable. In order to write to this field you need to write 1 in the same access to field pmic_en_we. NOTE: This MMR bit does not reflect any contribution from any debug related signal. 0 - Drives PMIC_EN output port to.." "0: Drives PMIC_EN output port to 0,1: Drives PMIC_EN output port to 1" line.long 0x4 "CFG0_PMCTRL_IO_0_PROXY," rbitfld.long 0x4 25. "PMCTRL_IO_0_IO_ISO_STATUS_0_PROXY,IO ISO Status 0 - IO isolation not active 1 - IO isolation active. Reflects value of SMS input port io_isoack coming back from IO pad ring" "0: IO isolation not active 1,?" newline bitfld.long 0x4 24. "PMCTRL_IO_0_IO_ISO_CTRL_0_PROXY,IO ISO control. 0 - Turn off the IO isolation 1 - Turn on the IO isolation" "0: Turn off the IO isolation 1,?" newline bitfld.long 0x4 16. "PMCTRL_IO_0_GLOBAL_WUEN_0_PROXY,Global IO wakeup enable. This is a gating condition to all individual IO WUEN coming from control module. Gating is done in the Spinner logic. 0 - All individual IO WUEN are gated in the Spinner logic (override to 0)." "0: All individual IO WUEN are gated in the Spinner..,1: All individual IO WUEN from control module are.." newline rbitfld.long 0x4 9. "PMCTRL_IO_0_WUCLK_STATUS_0_PROXY,Reflects value of SMS input port io_wuclkack coming back from IO pad ring" "0,1" newline bitfld.long 0x4 8. "PMCTRL_IO_0_WUCLK_CTRL_0_PROXY,Direct control on WUCLKIN signal to IO pad ring. 0 - WUCLKIN signal is driven to 0. IO wakeup daisy chain is functional as well as IO whose wakeup feature is enabled. 1 - WUCLKIN signal is driven to 1. IO wakeup daisy.." "0: WUCLKIN signal is driven to 0,1: WUCLKIN signal is driven to 1" newline bitfld.long 0x4 6. "PMCTRL_IO_0_ISOBYBASS_OVR_0_PROXY,This MMR bit drives directly SMS output port io_isobypass0." "0,1" newline rbitfld.long 0x4 5. "PMCTRL_IO_0_IO_ON_STATUS_0_PROXY,Gives the functional status of the IO ring. 0 - Part or all of the IOs are not in the ON state that is are in isolation state. 1 - All IOs are in the ON state. io_on_status = assign 1 if (io_iso == 0 & io_isoack==0 &.." "0: Part or all of the IOs are not in the ON state..,1: All IOs are in the ON state" newline bitfld.long 0x4 4. "PMCTRL_IO_0_ISOOVR_EXTEND_0_PROXY,Control for IO isolation extension This drives the SOC chain ISO-OVERRIDE global control. This bit drives directly the SMS output port io_isoovr0. At the SOC level it is used to enable when 1 or gate-off when 0 the.." "0: IO isolation is not extended,1: IO isolation is extended" newline rbitfld.long 0x4 1. "PMCTRL_IO_0_ISOCLK_STATUS_0_PROXY,Reflects value of io_isoclkack coming back from IO pad ring." "0,1" newline bitfld.long 0x4 0. "PMCTRL_IO_0_ISOCLK_OVRD_0_PROXY,Override control on ISOCLKIN signal to IO pad ring. When not overridden this signal is controlled by hardware only. 0 - ISOCLKIN signal is not overriden. 1 - ISOCLKIN signal is overridden to active value (1)." "0: ISOCLKIN signal is not overriden,1: ISOCLKIN signal is overridden to active value" line.long 0x8 "CFG0_PMCTRL_IO_1_PROXY," rbitfld.long 0x8 25. "PMCTRL_IO_1_IO_ISO_STATUS_1_PROXY,IO ISO Status 0 - IO isolation not active 1 - IO isolation active. Reflects value of SMS input port io_isoack coming back from IO pad ring" "0: IO isolation not active 1,?" newline bitfld.long 0x8 24. "PMCTRL_IO_1_IO_ISO_CTRL_1_PROXY,IO ISO control. 0 - Turn off the IO isolation 1 - Turn on the IO isolation" "0: Turn off the IO isolation 1,?" newline bitfld.long 0x8 16. "PMCTRL_IO_1_GLOBAL_WUEN_1_PROXY,Global IO wakeup enable. This is a gating condition to all individual IO WUEN coming from control module. Gating is done in the Spinner logic. 0 - All individual IO WUEN are gated in the Spinner logic (override to 0)." "0: All individual IO WUEN are gated in the Spinner..,1: All individual IO WUEN from control module are.." newline rbitfld.long 0x8 9. "PMCTRL_IO_1_WUCLK_STATUS_1_PROXY,Reflects value of SMS input port io_wuclkack coming back from IO pad ring" "0,1" newline bitfld.long 0x8 8. "PMCTRL_IO_1_WUCLK_CTRL_1_PROXY,Direct control on WUCLKIN signal to IO pad ring. 0 - WUCLKIN signal is driven to 0. IO wakeup daisy chain is functional as well as IO whose wakeup feature is enabled. 1 - WUCLKIN signal is driven to 1. IO wakeup daisy.." "0: WUCLKIN signal is driven to 0,1: WUCLKIN signal is driven to 1" newline bitfld.long 0x8 6. "PMCTRL_IO_1_ISOBYBASS_OVR_1_PROXY,This MMR bit drives directly SMS output port io_isobypassundefined." "0,1" newline rbitfld.long 0x8 5. "PMCTRL_IO_1_IO_ON_STATUS_1_PROXY,Gives the functional status of the IO ring. 0 - Part or all of the IOs are not in the ON state that is are in isolation state. 1 - All IOs are in the ON state. io_on_status = assign 1 if (io_iso == 0 & io_isoack==0 &.." "0: Part or all of the IOs are not in the ON state..,1: All IOs are in the ON state" newline bitfld.long 0x8 4. "PMCTRL_IO_1_ISOOVR_EXTEND_1_PROXY,Control for IO isolation extension This drives the SOC chain ISO-OVERRIDE global control. This bit drives directly the SMS output port io_isoovrundefined. At the SOC level it is used to enable when 1 or gate-off when.." "0: IO isolation is not extended,1: IO isolation is extended" newline rbitfld.long 0x8 1. "PMCTRL_IO_1_ISOCLK_STATUS_1_PROXY,Reflects value of io_isoclkack coming back from IO pad ring." "0,1" newline bitfld.long 0x8 0. "PMCTRL_IO_1_ISOCLK_OVRD_1_PROXY,Override control on ISOCLKIN signal to IO pad ring. When not overridden this signal is controlled by hardware only. 0 - ISOCLKIN signal is not overriden. 1 - ISOCLKIN signal is overridden to active value (1)." "0: ISOCLKIN signal is not overriden,1: ISOCLKIN signal is overridden to active value" rgroup.long 0x16300++0x3 line.long 0x0 "CFG0_PM_PERMISSION_PROXY," bitfld.long 0x0 0. "PM_PERMISSION_DEBUG_ACTIVE_PROXY,Debug mode activated Tells PM-FW that it should not power-OFF supplies externally. The debugger being active should also cause the SMS hardware to override the external rail state during deeperSleep by forcing high the.." "0: Debug not activated 1,?" rgroup.long 0x16400++0x3 line.long 0x0 "CFG0_SMS_WFI_STATUS_PROXY," bitfld.long 0x0 1. "SMS_WFI_STATUS_HSM_M4_WFI_PROXY,Indicates WFI status of the HSM M4 processor in SMS 0 - Normal operation 1 - M4 is in WFI state" "0: Normal operation 1,?" newline bitfld.long 0x0 0. "SMS_WFI_STATUS_TIFS_M4_WFI_PROXY,Indicates WFI status of the TIFS M4 processor in SMS 0 - Normal operation 1 - M4 is in WFI state" "0: Normal operation 1,?" rgroup.long 0x17008++0x7 line.long 0x0 "CFG0_LOCK5_KICK0_PROXY," hexmask.long 0x0 0.--31. 1. "LOCK5_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK5_KICK1_PROXY," hexmask.long 0x4 0.--31. 1. "LOCK5_KICK1_PROXY,- KICK1 component" rgroup.long 0x17100++0x23 line.long 0x0 "CFG0_CLAIMREG_P5_R0," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P5_R0,Claim bits for Partition 5" line.long 0x4 "CFG0_CLAIMREG_P5_R1," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P5_R1,Claim bits for Partition 5" line.long 0x8 "CFG0_CLAIMREG_P5_R2," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P5_R2,Claim bits for Partition 5" line.long 0xC "CFG0_CLAIMREG_P5_R3," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P5_R3,Claim bits for Partition 5" line.long 0x10 "CFG0_CLAIMREG_P5_R4," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P5_R4,Claim bits for Partition 5" line.long 0x14 "CFG0_CLAIMREG_P5_R5," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P5_R5,Claim bits for Partition 5" line.long 0x18 "CFG0_CLAIMREG_P5_R6," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P5_R6,Claim bits for Partition 5" line.long 0x1C "CFG0_CLAIMREG_P5_R7," hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P5_R7,Claim bits for Partition 5" line.long 0x20 "CFG0_CLAIMREG_P5_R8," hexmask.long 0x20 0.--31. 1. "CLAIMREG_P5_R8,Claim bits for Partition 5" rgroup.long 0x18000++0x3 line.long 0x0 "CFG0_POR_CTRL," bitfld.long 0x0 29. "POR_CTRL_OVRD_SET5,Reserved override set" "0,1" newline bitfld.long 0x0 28. "POR_CTRL_OVRD_SET4,POKLVB override set" "0,1" newline bitfld.long 0x0 27. "POR_CTRL_OVRD_SET3,POKLVA override set" "0,1" newline bitfld.long 0x0 26. "POR_CTRL_OVRD_SET2,POKHV override set" "0,1" newline bitfld.long 0x0 25. "POR_CTRL_OVRD_SET1,BGOK override set" "0,1" newline bitfld.long 0x0 24. "POR_CTRL_OVRD_SET0,PORHV override set" "0,1" newline bitfld.long 0x0 21. "POR_CTRL_OVRD5,Reserved override enable" "0,1" newline bitfld.long 0x0 20. "POR_CTRL_OVRD4,POKLVB override enable" "0,1" newline bitfld.long 0x0 19. "POR_CTRL_OVRD3,POKLVA override enable" "0,1" newline bitfld.long 0x0 18. "POR_CTRL_OVRD2,POKHV override enable" "0,1" newline bitfld.long 0x0 17. "POR_CTRL_OVRD1,BGOK override enable" "0,1" newline bitfld.long 0x0 16. "POR_CTRL_OVRD0,PORHV override enable" "0,1" newline bitfld.long 0x0 7. "POR_CTRL_TRIM_SEL,POR Trim Select 0 - Trim selections for Bandgap and POKs come from HHV defaults 1 - Trim selections for Bandgap and POKs come from POR_BANDGAP_CTRL and POR_POKxxx_CTRL registers" "0: Trim selections for Bandgap and POKs come from..,?" newline bitfld.long 0x0 4. "POR_CTRL_MASK_HHV,Mask HHV/SOC_PORz outputs when applying new trim values" "0,1" rgroup.long 0x18004++0x3 line.long 0x0 "CFG0_POR_STAT," bitfld.long 0x0 8. "POR_STAT_BGOK,Bandgap OK status" "0,1" newline bitfld.long 0x0 4. "POR_STAT_SOC_POR,POR module status 0 - Module is in functional mode 1 - Module is in reset mode" "0: Module is in functional mode 1,?" rgroup.long 0x18010++0x1F line.long 0x0 "CFG0_POK_VDDA_PMIC_IN_CTRL," bitfld.long 0x0 31. "POK_VDDA_PMIC_IN_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0x0 0. "POK_VDDA_PMIC_IN_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" line.long 0x4 "CFG0_POK_VDDSHV_WKUP_GEN_UV_CTRL," bitfld.long 0x4 31. "POK_VDDSHV_WKUP_GEN_UV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0x4 7. "POK_VDDSHV_WKUP_GEN_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x4 0.--6. 1. "POK_VDDSHV_WKUP_GEN_UV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and J7 efuse spec for details" line.long 0x8 "CFG0_POK_VDDR_MCU_UV_CTRL," bitfld.long 0x8 31. "POK_VDDR_MCU_UV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0x8 7. "POK_VDDR_MCU_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x8 0.--6. 1. "POK_VDDR_MCU_UV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and J7 efuse spec for details" line.long 0xC "CFG0_POK_VMON_CAP_MCU_GEN_UV_CTRL," bitfld.long 0xC 31. "POK_VMON_CAP_MCU_GEN_UV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0xC 7. "POK_VMON_CAP_MCU_GEN_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0xC 0.--6. 1. "POK_VMON_CAP_MCU_GEN_UV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x10 "CFG0_POK_VDD_MCU_OV_CTRL," bitfld.long 0x10 31. "POK_VDD_MCU_OV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0x10 7. "POK_VDD_MCU_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x10 0.--6. 1. "POK_VDD_MCU_OV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and J7 efuse spec for details" line.long 0x14 "CFG0_POK_VDDSHV_WKUP_GEN_OV_CTRL," bitfld.long 0x14 31. "POK_VDDSHV_WKUP_GEN_OV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0x14 7. "POK_VDDSHV_WKUP_GEN_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x14 0.--6. 1. "POK_VDDSHV_WKUP_GEN_OV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and J7 efuse spec for details" line.long 0x18 "CFG0_POK_VDDR_MCU_OV_CTRL," bitfld.long 0x18 31. "POK_VDDR_MCU_OV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0x18 7. "POK_VDDR_MCU_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x18 0.--6. 1. "POK_VDDR_MCU_OV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and J7 efuse spec for details" line.long 0x1C "CFG0_POK_VMON_CAP_MCU_GEN_OV_CTRL," bitfld.long 0x1C 31. "POK_VMON_CAP_MCU_GEN_OV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0x1C 7. "POK_VMON_CAP_MCU_GEN_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x1C 0.--6. 1. "POK_VMON_CAP_MCU_GEN_OV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" rgroup.long 0x18070++0x3 line.long 0x0 "CFG0_MAIN_VDOM_CTRL," bitfld.long 0x0 0. "MAIN_VDOM_CTRL_MAIN_VD_OFF,MAIN deep sleep isolation enable. This bit should be set prior to powering off the MAIN voltage domain to ensure proper signal isolation." "0,1" rgroup.long 0x18080++0xF line.long 0x0 "CFG0_POR_POKHV_UV_CTRL," bitfld.long 0x0 31. "POR_POKHV_UV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0x0 7. "POR_POKHV_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x0 0.--6. 1. "POR_POKHV_UV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and J7 efuse spec for details" line.long 0x4 "CFG0_POR_POKLVB_UV_CTRL," bitfld.long 0x4 31. "POR_POKLVB_UV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0x4 7. "POR_POKLVB_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x4 0.--6. 1. "POR_POKLVB_UV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and J7 efuse spec for details" line.long 0x8 "CFG0_POR_POKLVA_OV_CTRL," bitfld.long 0x8 31. "POR_POKLVA_OV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0x8 7. "POR_POKLVA_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x8 0.--6. 1. "POR_POKLVA_OV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and J7 efuse spec for details" line.long 0xC "CFG0_POR_BANDGAP_CTRL," hexmask.long.byte 0xC 16.--19. 1. "POR_BANDGAP_CTRL_BGAPI,Bandgap output current trim bits" newline hexmask.long.byte 0xC 8.--15. 1. "POR_BANDGAP_CTRL_BGAPV,Bandgap output voltage magnitude trim bits" newline hexmask.long.byte 0xC 0.--7. 1. "POR_BANDGAP_CTRL_BGAPC,Bandgap slope trim bits. Bit7 is used to calculate the offset" rgroup.long 0x180A0++0x3 line.long 0x0 "CFG0_TEMP_DIODE_TRIM," hexmask.long.word 0x0 0.--13. 1. "TEMP_DIODE_TRIM_TRIM,Sets the diode non-ideality factor (n) starting from 100th place decimal and going down" rgroup.long 0x180B0++0x3 line.long 0x0 "CFG0_IO_VOLTAGE_STAT," bitfld.long 0x0 16. "IO_VOLTAGE_STAT_MAIN_HYPERNET,Indicates the voltage for the HYPERNET I/O group 0 - I/O group is set for 1.8V 1 - I/O group is set for 3.3V" "0: I/O group is set for 1,1: I/O group is set for 3" newline bitfld.long 0x0 10. "IO_VOLTAGE_STAT_MAIN_MMC1,Indicates the voltage for the MMC1 I/O group 0 - I/O group is set for 1.8V 1 - I/O group is set for 3.3V" "0: I/O group is set for 1,1: I/O group is set for 3" newline bitfld.long 0x0 9. "IO_VOLTAGE_STAT_MAIN_MMC0,Indicates the voltage for the MMC0 I/O group 0 - I/O group is set for 1.8V 1 - I/O group is set for 3.3V" "0: I/O group is set for 1,1: I/O group is set for 3" newline bitfld.long 0x0 8. "IO_VOLTAGE_STAT_MAIN_GEN,Indicates the voltage for the General I/O group 0 - I/O group is set for 1.8V 1 - I/O group is set for 3.3V" "0: I/O group is set for 1,1: I/O group is set for 3" newline bitfld.long 0x0 2. "IO_VOLTAGE_STAT_MCU_RGMII,Indicates the voltage for the MCU CPSW2G RGMII I/O group 0 - I/O group is set for 1.8V 1 - I/O group is set for 3.3V" "0: I/O group is set for 1,1: I/O group is set for 3" newline bitfld.long 0x0 1. "IO_VOLTAGE_STAT_MCU_FLASH,Indicates the voltage for the MCU Flash I/O group 0 - I/O group is set for 1.8V 1 - I/O group is set for 3.3V" "0: I/O group is set for 1,1: I/O group is set for 3" newline bitfld.long 0x0 0. "IO_VOLTAGE_STAT_MCU_GEN,Indicates the voltage for the MCU General I/O group 0 - I/O group is set for 1.8V 1 - I/O group is set for 3.3V" "0: I/O group is set for 1,1: I/O group is set for 3" rgroup.long 0x18104++0x3 line.long 0x0 "CFG0_MAIN_POR_TO_CTRL," bitfld.long 0x0 0.--2. "MAIN_POR_TO_CTRL_TIMEOUT_PER,MAIN PORz hardware timeout period. During normal operation the assertion of a MAIN Domain PORz generates a reset request interrupt to the DMSC. The DMSC then performs steps to properly isolate the MAIN Domain before the.." "0: Immediate 3'b001,?,?,?,?,?,?,?" rgroup.long 0x18110++0x37 line.long 0x0 "CFG0_POK_VDD_CORE_UV_CTRL," bitfld.long 0x0 31. "POK_VDD_CORE_UV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0x0 7. "POK_VDD_CORE_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x0 0.--6. 1. "POK_VDD_CORE_UV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x4 "CFG0_POK_VDD_CPU_UV_CTRL," bitfld.long 0x4 31. "POK_VDD_CPU_UV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0x4 7. "POK_VDD_CPU_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x4 0.--6. 1. "POK_VDD_CPU_UV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x8 "CFG0_POK_VMON_EXT_UV_CTRL," bitfld.long 0x8 31. "POK_VMON_EXT_UV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0x8 7. "POK_VMON_EXT_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x8 0.--6. 1. "POK_VMON_EXT_UV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0xC "CFG0_POK_VDDR_CORE_UV_CTRL," bitfld.long 0xC 31. "POK_VDDR_CORE_UV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0xC 7. "POK_VDDR_CORE_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0xC 0.--6. 1. "POK_VDDR_CORE_UV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x10 "CFG0_POK_VDD_CORE_OV_CTRL," bitfld.long 0x10 31. "POK_VDD_CORE_OV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0x10 7. "POK_VDD_CORE_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x10 0.--6. 1. "POK_VDD_CORE_OV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x14 "CFG0_POK_VDD_CPU_OV_CTRL," bitfld.long 0x14 31. "POK_VDD_CPU_OV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0x14 7. "POK_VDD_CPU_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x14 0.--6. 1. "POK_VDD_CPU_OV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x18 "CFG0_POK_VMON_EXT_OV_CTRL," bitfld.long 0x18 31. "POK_VMON_EXT_OV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0x18 7. "POK_VMON_EXT_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x18 0.--6. 1. "POK_VMON_EXT_OV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x1C "CFG0_POK_VDDR_CORE_OV_CTRL," bitfld.long 0x1C 31. "POK_VDDR_CORE_OV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0x1C 7. "POK_VDDR_CORE_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x1C 0.--6. 1. "POK_VDDR_CORE_OV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x20 "CFG0_POK_VMON_EXT_MAIN1P8_UV_CTRL," bitfld.long 0x20 31. "POK_VMON_EXT_MAIN1P8_UV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0x20 7. "POK_VMON_EXT_MAIN1P8_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x20 0.--6. 1. "POK_VMON_EXT_MAIN1P8_UV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x24 "CFG0_POK_VMON_EXT_MAIN1P8_OV_CTRL," bitfld.long 0x24 31. "POK_VMON_EXT_MAIN1P8_OV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0x24 7. "POK_VMON_EXT_MAIN1P8_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x24 0.--6. 1. "POK_VMON_EXT_MAIN1P8_OV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x28 "CFG0_POK_VMON_EXT_MAIN3P3_UV_CTRL," bitfld.long 0x28 31. "POK_VMON_EXT_MAIN3P3_UV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0x28 7. "POK_VMON_EXT_MAIN3P3_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x28 0.--6. 1. "POK_VMON_EXT_MAIN3P3_UV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x2C "CFG0_POK_VMON_EXT_MAIN3P3_OV_CTRL," bitfld.long 0x2C 31. "POK_VMON_EXT_MAIN3P3_OV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0x2C 7. "POK_VMON_EXT_MAIN3P3_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x2C 0.--6. 1. "POK_VMON_EXT_MAIN3P3_OV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x30 "CFG0_POK_VDD_CPU1_UV_CTRL," bitfld.long 0x30 31. "POK_VDD_CPU1_UV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0x30 7. "POK_VDD_CPU1_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x30 0.--6. 1. "POK_VDD_CPU1_UV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x34 "CFG0_POK_VDD_CPU1_OV_CTRL," bitfld.long 0x34 31. "POK_VDD_CPU1_OV_CTRL_HYST_EN,Enable POK hysteresis" "0,1" newline bitfld.long 0x34 7. "POK_VDD_CPU1_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x34 0.--6. 1. "POK_VDD_CPU1_OV_CTRL_POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" rgroup.long 0x18150++0x13 line.long 0x0 "CFG0_POK_RSV0," hexmask.long 0x0 0.--31. 1. "RESERVED,Reserved POK bits" line.long 0x4 "CFG0_POK_RSV1," hexmask.long 0x4 0.--31. 1. "RESERVED,Reserved POK bits" line.long 0x8 "CFG0_POK_RSV2," hexmask.long 0x8 0.--31. 1. "RESERVED,Reserved POK bits" line.long 0xC "CFG0_POK_RSV3," hexmask.long 0xC 0.--31. 1. "RESERVED,Reserved POK bits" line.long 0x10 "CFG0_DEEPSLEEP_CTRL," bitfld.long 0x10 8. "DEEPSLEEP_CTRL_FORCE_DS_MAIN,Force all MAIN IOs into deepsleep mode when set" "0,1" newline bitfld.long 0x10 0. "DEEPSLEEP_CTRL_FORCE_DS_WKUP,Force all WKUP IOs into deepsleep mode when set" "0,1" rgroup.long 0x18170++0x7 line.long 0x0 "CFG0_POR_RST_CTRL," bitfld.long 0x0 24. "POR_RST_CTRL_MAIN_PORZ_DAISYCHAIN_EN,MAIN PORz daisy-chain event enable. Determines if MAIN PORz reset events affect daisy-chain wakeup 0 - DeepSleep MAIN PORz event is not part of daisy-chain 1 - DeepSleep MAIN PORz event is combined w/ other daisy.." "0: DeepSleep MAIN PORz event is not part of..,?" newline hexmask.long.byte 0x0 16.--19. 1. "POR_RST_CTRL_SW_MAIN_POR,Main Domain software power-on reset. When set to 4'b0110 a power-on is issued to the MAIN voltage domain. (Bits will reset to 4'b1111 on reset of the Main Domain)" newline bitfld.long 0x0 12. "POR_RST_CTRL_MAIN_PORZ_DS_STRETCH,DeepSleep mode MAIN PORz stretch. 0 - No stretching 1 - Stretch the Main PORz event captured during DeepSleep mode" "0: No stretching 1,?" newline bitfld.long 0x0 0. "POR_RST_CTRL_POR_RST_ISO_DONE_Z,Reset isolation completion (active low). This bit should be cleared only after reset isolation of the MAIN domain is complete. 0 - POR reset propagates to MAIN domain 1 - POR reset blocked from MAIN domain" "0: POR reset propagates to MAIN domain 1,?" line.long 0x4 "CFG0_MAIN_WARM_RST_CTRL," hexmask.long.byte 0x4 16.--19. 1. "MAIN_WARM_RST_CTRL_SW_WARMRST,Main Domain software warm reset. When set to 4'b0110 a warm reset is issued to the MAIN voltage domain. (Bits will reset to 4'b1111 on reset of the Main Domain)" newline bitfld.long 0x4 0. "MAIN_WARM_RST_CTRL_SOC_WARMRST_ISO_DONE_Z,Reset isolation completion (active low). This bit should be cleared only after reset isolation of the MAIN domain is complete. 0 - Warm reset propagates to MAIN domain 1 - Warm reset blocked from MAIN domain" "0: Warm reset propagates to MAIN domain 1,?" rgroup.long 0x18178++0x3 line.long 0x0 "CFG0_RST_STAT," bitfld.long 0x0 16. "RST_STAT_MCU_RST_DONE,Indicates MCU domain reset status. 0 - MCU domain is in reset 1 - MCU domain reset is complete" "0: MCU domain is in reset 1,?" newline bitfld.long 0x0 0. "RST_STAT_MAIN_RST_DONE,Indicates MAIN domain Warm reset status. 0 - MAIN domain is in Warm reset 1 - MAIN domain Warm reset is complete" "0: MAIN domain is in Warm reset 1,?" rgroup.long 0x1817C++0xB line.long 0x0 "CFG0_MCU_WARM_RST_CTRL," hexmask.long.byte 0x0 16.--19. 1. "MCU_WARM_RST_CTRL_SW_WARMRST,Chip software warm reset. When set to 4'b0110 a warm reset is issued to the device (all voltage domains). (Bits will reset to 4'b1111 on reset completion.)" line.long 0x4 "CFG0_VDD_CPU_GLDTC_CTRL," bitfld.long 0x4 31. "VDD_CPU_GLDTC_CTRL_PWDB,Power down - active low. 0 - Disable all functions 1 - Enable glitch detectors" "0: Disable all functions 1,?" newline bitfld.long 0x4 30. "VDD_CPU_GLDTC_CTRL_RSTB,Reset - active low. To ensure proper operation rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold or.." "0: Reset glitch detector flags 1,?" newline bitfld.long 0x4 16.--18. "VDD_CPU_GLDTC_CTRL_LP_FILTER_SEL,Selects the glitch detect low-pass filter bandwidth Field values (others are reserved): 3'b000 - 150 kHz 3'b001 - 125 kHz 3'b010 - 100 kHz 3'b011 - 80 kHz 3'b100 - 60 kHz 3'b101 - 45 kHz 3'b110 - 30 kHz 3'b111 - 15 kHz" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--13. 1. "VDD_CPU_GLDTC_CTRL_THRESH_HI_SEL,Selects the high voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 93.5% of VDD 6'b000001 - 94.0% of VDD 6'b000010 - 94.5% of VDD 6'b000011 - 95.0% of VDD.." newline hexmask.long.byte 0x4 0.--5. 1. "VDD_CPU_GLDTC_CTRL_THRESH_LO_SEL,Selects the low voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 106.5% of VDD 6'b000001 - 106.0% of VDD 6'b000010 - 105.5% of VDD 6'b000011 - 105.0% of VDD.." line.long 0x8 "CFG0_VDD_CPU1_GLDTC_CTRL," bitfld.long 0x8 31. "VDD_CPU1_GLDTC_CTRL_PWDB,Power down - active low. 0 - Disable all functions 1 - Enable glitch detectors" "0: Disable all functions 1,?" newline bitfld.long 0x8 30. "VDD_CPU1_GLDTC_CTRL_RSTB,Reset - active low. To ensure proper operation rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold or.." "0: Reset glitch detector flags 1,?" newline bitfld.long 0x8 16.--18. "VDD_CPU1_GLDTC_CTRL_LP_FILTER_SEL,Selects the glitch detect low-pass filter bandwidth Field values (others are reserved): 3'b000 - 150 kHz 3'b001 - 125 kHz 3'b010 - 100 kHz 3'b011 - 80 kHz 3'b100 - 60 kHz 3'b101 - 45 kHz 3'b110 - 30 kHz 3'b111 - 15 kHz" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--13. 1. "VDD_CPU1_GLDTC_CTRL_THRESH_HI_SEL,Selects the high voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 93.5% of VDD 6'b000001 - 94.0% of VDD 6'b000010 - 94.5% of VDD 6'b000011 - 95.0% of VDD.." newline hexmask.long.byte 0x8 0.--5. 1. "VDD_CPU1_GLDTC_CTRL_THRESH_LO_SEL,Selects the low voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 106.5% of VDD 6'b000001 - 106.0% of VDD 6'b000010 - 105.5% of VDD 6'b000011 - 105.0% of.." rgroup.long 0x18190++0xF line.long 0x0 "CFG0_VDD_CORE_GLDTC_CTRL," bitfld.long 0x0 31. "VDD_CORE_GLDTC_CTRL_PWDB,Power down - active low. 0 - Disable all functions 1 - Enable glitch detectors" "0: Disable all functions 1,?" newline bitfld.long 0x0 30. "VDD_CORE_GLDTC_CTRL_RSTB,Reset - active low. To ensure proper operation rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold or.." "0: Reset glitch detector flags 1,?" newline bitfld.long 0x0 16.--18. "VDD_CORE_GLDTC_CTRL_LP_FILTER_SEL,Selects the glitch detect low-pass filter bandwidth Field values (others are reserved): 3'b000 - 150 kHz 3'b001 - 125 kHz 3'b010 - 100 kHz 3'b011 - 80 kHz 3'b100 - 60 kHz 3'b101 - 45 kHz 3'b110 - 30 kHz 3'b111 - 15 kHz" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--13. 1. "VDD_CORE_GLDTC_CTRL_THRESH_HI_SEL,Selects the high voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 93.5% of VDD 6'b000001 - 94.0% of VDD 6'b000010 - 94.5% of VDD 6'b000011 - 95.0% of VDD.." newline hexmask.long.byte 0x0 0.--5. 1. "VDD_CORE_GLDTC_CTRL_THRESH_LO_SEL,Selects the low voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 106.5% of VDD 6'b000001 - 106.0% of VDD 6'b000010 - 105.5% of VDD 6'b000011 - 105.0% of.." line.long 0x4 "CFG0_VDDR_CPU_GLDTC_CTRL," bitfld.long 0x4 31. "VDDR_CPU_GLDTC_CTRL_PWDB,Power down - active low. 0 - Disable all functions 1 - Enable glitch detectors" "0: Disable all functions 1,?" newline bitfld.long 0x4 30. "VDDR_CPU_GLDTC_CTRL_RSTB,Reset - active low. To ensure proper operation rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold or.." "0: Reset glitch detector flags 1,?" newline bitfld.long 0x4 16.--18. "VDDR_CPU_GLDTC_CTRL_LP_FILTER_SEL,Selects the glitch detect low-pass filter bandwidth Field values (others are reserved): 3'b000 - 150 kHz 3'b001 - 125 kHz 3'b010 - 100 kHz 3'b011 - 80 kHz 3'b100 - 60 kHz 3'b101 - 45 kHz 3'b110 - 30 kHz 3'b111 - 15 kHz" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--13. 1. "VDDR_CPU_GLDTC_CTRL_THRESH_HI_SEL,Selects the high voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 93.5% of VDD 6'b000001 - 94.0% of VDD 6'b000010 - 94.5% of VDD 6'b000011 - 95.0% of VDD.." newline hexmask.long.byte 0x4 0.--5. 1. "VDDR_CPU_GLDTC_CTRL_THRESH_LO_SEL,Selects the low voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 106.5% of VDD 6'b000001 - 106.0% of VDD 6'b000010 - 105.5% of VDD 6'b000011 - 105.0% of.." line.long 0x8 "CFG0_VDDR_CORE_GLDTC_CTRL," bitfld.long 0x8 31. "VDDR_CORE_GLDTC_CTRL_PWDB,Power down - active low. 0 - Disable all functions 1 - Enable glitch detectors" "0: Disable all functions 1,?" newline bitfld.long 0x8 30. "VDDR_CORE_GLDTC_CTRL_RSTB,Reset - active low. To ensure proper operation rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold or.." "0: Reset glitch detector flags 1,?" newline bitfld.long 0x8 16.--18. "VDDR_CORE_GLDTC_CTRL_LP_FILTER_SEL,Selects the glitch detect low-pass filter bandwidth Field values (others are reserved): 3'b000 - 150 kHz 3'b001 - 125 kHz 3'b010 - 100 kHz 3'b011 - 80 kHz 3'b100 - 60 kHz 3'b101 - 45 kHz 3'b110 - 30 kHz 3'b111 - 15 kHz" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--13. 1. "VDDR_CORE_GLDTC_CTRL_THRESH_HI_SEL,Selects the high voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 93.5% of VDD 6'b000001 - 94.0% of VDD 6'b000010 - 94.5% of VDD 6'b000011 - 95.0% of VDD.." newline hexmask.long.byte 0x8 0.--5. 1. "VDDR_CORE_GLDTC_CTRL_THRESH_LO_SEL,Selects the low voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 106.5% of VDD 6'b000001 - 106.0% of VDD 6'b000010 - 105.5% of VDD 6'b000011 - 105.0% of.." line.long 0xC "CFG0_VDDR_CPU1_GLDTC_CTRL," bitfld.long 0xC 31. "VDDR_CPU1_GLDTC_CTRL_PWDB,Power down - active low. 0 - Disable all functions 1 - Enable glitch detectors" "0: Disable all functions 1,?" newline bitfld.long 0xC 30. "VDDR_CPU1_GLDTC_CTRL_RSTB,Reset - active low. To ensure proper operation rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold or.." "0: Reset glitch detector flags 1,?" newline bitfld.long 0xC 16.--18. "VDDR_CPU1_GLDTC_CTRL_LP_FILTER_SEL,Selects the glitch detect low-pass filter bandwidth Field values (others are reserved): 3'b000 - 150 kHz 3'b001 - 125 kHz 3'b010 - 100 kHz 3'b011 - 80 kHz 3'b100 - 60 kHz 3'b101 - 45 kHz 3'b110 - 30 kHz 3'b111 - 15 kHz" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--13. 1. "VDDR_CPU1_GLDTC_CTRL_THRESH_HI_SEL,Selects the high voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 93.5% of VDD 6'b000001 - 94.0% of VDD 6'b000010 - 94.5% of VDD 6'b000011 - 95.0% of VDD.." newline hexmask.long.byte 0xC 0.--5. 1. "VDDR_CPU1_GLDTC_CTRL_THRESH_LO_SEL,Selects the low voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 106.5% of VDD 6'b000001 - 106.0% of VDD 6'b000010 - 105.5% of VDD 6'b000011 - 105.0% of.." rgroup.long 0x181A0++0x7 line.long 0x0 "CFG0_VDD_CPU_GLDTC_STAT," bitfld.long 0x0 8. "VDD_CPU_GLDTC_STAT_THRESH_HI_FLAG,High voltage flag. This flag is cleared by clearing the VDD_CPU_GLDTC_CTRL_rstb bit. 0 - No high voltage detected 1 - Voltage above the high voltage threshold was detected." "0: No high voltage detected 1,?" newline bitfld.long 0x0 0. "VDD_CPU_GLDTC_STAT_THRESH_LOW_FLAG,Low voltage flag. This flag is cleared by clearing the VDD_CPU_GLDTC_CTRL_rstb bit. 0 - No low voltage detected 1 - Voltage below the low voltage threshold was detected." "0: No low voltage detected 1,?" line.long 0x4 "CFG0_VDD_CPU1_GLDTC_STAT," bitfld.long 0x4 8. "VDD_CPU1_GLDTC_STAT_THRESH_HI_FLAG,High voltage flag. This flag is cleared by clearing the VDD_CPU1_GLDTC_CTRL_rstb bit. 0 - No high voltage detected 1 - Voltage above the high voltage threshold was detected." "0: No high voltage detected 1,?" newline bitfld.long 0x4 0. "VDD_CPU1_GLDTC_STAT_THRESH_LOW_FLAG,Low voltage flag. This flag is cleared by clearing the VDD_CPU1_GLDTC_CTRL_rstb bit. 0 - No low voltage detected 1 - Voltage below the low voltage threshold was detected." "0: No low voltage detected 1,?" rgroup.long 0x181B0++0xF line.long 0x0 "CFG0_VDD_CORE_GLDTC_STAT," bitfld.long 0x0 8. "VDD_CORE_GLDTC_STAT_THRESH_HI_FLAG,High voltage flag. This flag is cleared by clearing the VDD_CORE_GLDTC_CTRL_rstb bit. 0 - No high voltage detected 1 - Voltage above the high voltage threshold was detected." "0: No high voltage detected 1,?" newline bitfld.long 0x0 0. "VDD_CORE_GLDTC_STAT_THRESH_LOW_FLAG,Low voltage flag. This flag is cleared by clearing the VDD_CORE_GLDTC_CTRL_rstb bit. 0 - No low voltage detected 1 - Voltage below the low voltage threshold was detected." "0: No low voltage detected 1,?" line.long 0x4 "CFG0_VDDR_CPU_GLDTC_STAT," bitfld.long 0x4 8. "VDDR_CPU_GLDTC_STAT_THRESH_HI_FLAG,High voltage flag. This flag is cleared by clearing the VDDR_CPU_GLDTC_CTRL_rstb bit. 0 - No high voltage detected 1 - Voltage above the high voltage threshold was detected." "0: No high voltage detected 1,?" newline bitfld.long 0x4 0. "VDDR_CPU_GLDTC_STAT_THRESH_LOW_FLAG,Low voltage flag. This flag is cleared by clearing the VDDR_CPU_GLDTC_CTRL_rstb bit. 0 - No low voltage detected 1 - Voltage below the low voltage threshold was detected." "0: No low voltage detected 1,?" line.long 0x8 "CFG0_VDDR_CORE_GLDTC_STAT," bitfld.long 0x8 8. "VDDR_CORE_GLDTC_STAT_THRESH_HI_FLAG,High voltage flag. This flag is cleared by clearing the VDDR_CORE_GLDTC_CTRL_rstb bit. 0 - No high voltage detected 1 - Voltage above the high voltage threshold was detected." "0: No high voltage detected 1,?" newline bitfld.long 0x8 0. "VDDR_CORE_GLDTC_STAT_THRESH_LOW_FLAG,Low voltage flag. This flag is cleared by clearing the VDDR_CORE_GLDTC_CTRL_rstb bit. 0 - No low voltage detected 1 - Voltage below the low voltage threshold was detected." "0: No low voltage detected 1,?" line.long 0xC "CFG0_VDDR_CPU1_GLDTC_STAT," bitfld.long 0xC 8. "VDDR_CPU1_GLDTC_STAT_THRESH_HI_FLAG,High voltage flag. This flag is cleared by clearing the VDDR_CPU1_GLDTC_CTRL_rstb bit. 0 - No high voltage detected 1 - Voltage above the high voltage threshold was detected." "0: No high voltage detected 1,?" newline bitfld.long 0xC 0. "VDDR_CPU1_GLDTC_STAT_THRESH_LOW_FLAG,Low voltage flag. This flag is cleared by clearing the VDDR_CPU1_GLDTC_CTRL_rstb bit. 0 - No low voltage detected 1 - Voltage below the low voltage threshold was detected." "0: No low voltage detected 1,?" rgroup.long 0x181C0++0x7 line.long 0x0 "CFG0_VDD_MCU_GLDTC_CTRL," bitfld.long 0x0 31. "VDD_MCU_GLDTC_CTRL_PWDB,Power down - active low. 0 - Disable all functions 1 - Enable glitch detectors" "0: Disable all functions 1,?" newline bitfld.long 0x0 30. "VDD_MCU_GLDTC_CTRL_RSTB,Reset - active low. To ensure proper operation rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold or.." "0: Reset glitch detector flags 1,?" newline bitfld.long 0x0 16.--18. "VDD_MCU_GLDTC_CTRL_LP_FILTER_SEL,Selects the glitch detect low-pass filter bandwidth Field values (others are reserved): 3'b000 - 150 kHz 3'b001 - 125 kHz 3'b010 - 100 kHz 3'b011 - 80 kHz 3'b100 - 60 kHz 3'b101 - 45 kHz 3'b110 - 30 kHz 3'b111 - 15 kHz" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--13. 1. "VDD_MCU_GLDTC_CTRL_THRESH_HI_SEL,Selects the high voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 93.5% of VDD 6'b000001 - 94.0% of VDD 6'b000010 - 94.5% of VDD 6'b000011 - 95.0% of VDD.." newline hexmask.long.byte 0x0 0.--5. 1. "VDD_MCU_GLDTC_CTRL_THRESH_LO_SEL,Selects the low voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 106.5% of VDD 6'b000001 - 106.0% of VDD 6'b000010 - 105.5% of VDD 6'b000011 - 105.0% of VDD.." line.long 0x4 "CFG0_VDDR_MCU_GLDTC_CTRL," bitfld.long 0x4 31. "VDDR_MCU_GLDTC_CTRL_PWDB,Power down - active low. 0 - Disable all functions 1 - Enable glitch detectors" "0: Disable all functions 1,?" newline bitfld.long 0x4 30. "VDDR_MCU_GLDTC_CTRL_RSTB,Reset - active low. To ensure proper operation rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold or.." "0: Reset glitch detector flags 1,?" newline bitfld.long 0x4 16.--18. "VDDR_MCU_GLDTC_CTRL_LP_FILTER_SEL,Selects the glitch detect low-pass filter bandwidth Field values (others are reserved): 3'b000 - 150 kHz 3'b001 - 125 kHz 3'b010 - 100 kHz 3'b011 - 80 kHz 3'b100 - 60 kHz 3'b101 - 45 kHz 3'b110 - 30 kHz 3'b111 - 15 kHz" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--13. 1. "VDDR_MCU_GLDTC_CTRL_THRESH_HI_SEL,Selects the high voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 93.5% of VDD 6'b000001 - 94.0% of VDD 6'b000010 - 94.5% of VDD 6'b000011 - 95.0% of VDD.." newline hexmask.long.byte 0x4 0.--5. 1. "VDDR_MCU_GLDTC_CTRL_THRESH_LO_SEL,Selects the low voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 106.5% of VDD 6'b000001 - 106.0% of VDD 6'b000010 - 105.5% of VDD 6'b000011 - 105.0% of.." rgroup.long 0x181D0++0x7 line.long 0x0 "CFG0_VDD_MCU_GLDTC_STAT," bitfld.long 0x0 8. "VDD_MCU_GLDTC_STAT_THRESH_HI_FLAG,High voltage flag. This flag is cleared by clearing the VDD_MCU_GLDTC_CTRL_rstb bit. 0 - No high voltage detected 1 - Voltage above the high voltage threshold was detected." "0: No high voltage detected 1,?" newline bitfld.long 0x0 0. "VDD_MCU_GLDTC_STAT_THRESH_LOW_FLAG,Low voltage flag. This flag is cleared by clearing the VDD_MCU_GLDTC_CTRL_rstb bit. 0 - No low voltage detected 1 - Voltage below the low voltage threshold was detected." "0: No low voltage detected 1,?" line.long 0x4 "CFG0_VDDR_MCU_GLDTC_STAT," bitfld.long 0x4 8. "VDDR_MCU_GLDTC_STAT_THRESH_HI_FLAG,High voltage flag. This flag is cleared by clearing the VDDR_MCU_GLDTC_CTRL_rstb bit. 0 - No high voltage detected 1 - Voltage above the high voltage threshold was detected." "0: No high voltage detected 1,?" newline bitfld.long 0x4 0. "VDDR_MCU_GLDTC_STAT_THRESH_LOW_FLAG,Low voltage flag. This flag is cleared by clearing the VDDR_MCU_GLDTC_CTRL_rstb bit. 0 - No low voltage detected 1 - Voltage below the low voltage threshold was detected." "0: No low voltage detected 1,?" rgroup.long 0x18200++0x17 line.long 0x0 "CFG0_PRG_PP_MCU_CTRL," bitfld.long 0x0 19. "PRG_PP_MCU_CTRL_POK_PP_EN,POK ping-pong enable. When set enables automatic switching between undervoltage and overvoltage detection on VDDSHV_WKUP_GENERAL VDDR_MCU and VMON_CAP_MCU_GENERAL POKs. This bit has no effect if the POK's ov_sel bit = 1." "0: No pingpong operation,1: Pingpong operation enabled" newline bitfld.long 0x0 16.--17. "PRG_PP_MCU_CTRL_DEGLITCH_SEL,Deglitch period for PRG_PP_MCU POKs Field values (others are reserved): 2'b00 - 5 us 2'b01 - 10 us 2'b10 - 15 us 2'b11 - 20 us" "0,1,2,3" newline bitfld.long 0x0 15. "PRG_PP_MCU_CTRL_POK_EN_SEL,Select POK enable source 0 - POK enables come from hardware tie-offs 1 - POK enables come from PRG_PP_MCU_CTRL register" "0: POK enables come from hardware tie-offs 1,?" newline bitfld.long 0x0 10. "PRG_PP_MCU_CTRL_POK_VMON_CAP_MCU_GEN_OV_SEL,Force VMON_CAP_MCU_GENERAL POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled. 0 - Undervoltage detection or UV/OV ping-pong operation 1-.." "0: Undervoltage detection or UV/OV ping-pong..,?" newline bitfld.long 0x0 9. "PRG_PP_MCU_CTRL_POK_VDDR_MCU_OV_SEL,Force VDDR_MCU POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled. 0 - Undervoltage detection or UV/OV ping-pong operation 1- Overvoltage detection.." "0: Undervoltage detection or UV/OV ping-pong..,?" newline bitfld.long 0x0 8. "PRG_PP_MCU_CTRL_POK_VDDSHV_WKUP_GEN_OV_SEL,Force VDDSHV_WKUP_GENERAL POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled. 0 - Undervoltage detection or UV/OV ping-pong operation 1-.." "0: Undervoltage detection or UV/OV ping-pong..,?" newline bitfld.long 0x0 2. "PRG_PP_MCU_CTRL_POK_VMON_CAP_MCU_GEN_EN,Enable VMON_CAP_MCU_GENERAL POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x0 1. "PRG_PP_MCU_CTRL_POK_VDDR_MCU_EN,Enable VDDR_MCU POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x0 0. "PRG_PP_MCU_CTRL_POK_VDDSHV_WKUP_GEN_EN,Enable VDDSHV_WKUP_GENERAL POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" line.long 0x4 "CFG0_PRG_PP_MCU_STAT," bitfld.long 0x4 31. "PRG_PP_MCU_STAT_POK_CLR,When set resets pgood sticky bits for VDDSHV_WKUP_GENERAL VDDR_MCU and VMON_CAP_MCU_GENERAL voltage POK detection." "0,1" newline rbitfld.long 0x4 10. "PRG_PP_MCU_STAT_POK_VMON_CAP_MCU_GEN_OV,VMON_CAP_MCU_GENERAL overvoltage POK 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0x4 9. "PRG_PP_MCU_STAT_POK_VDDR_MCU_OV,VDDR_MCU overvoltage POK 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0x4 8. "PRG_PP_MCU_STAT_POK_VDDSHV_WKUP_GEN_OV,VDDSHV_WKUP_GENERAL overvoltage POK 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0x4 2. "PRG_PP_MCU_STAT_POK_VMON_CAP_MCU_GEN_UV,VMON_CAP_MCU_GENERAL undervoltage POK 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" newline rbitfld.long 0x4 1. "PRG_PP_MCU_STAT_POK_VDDR_MCU_UV,VDDR_MCU undervoltage POK 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" newline rbitfld.long 0x4 0. "PRG_PP_MCU_STAT_POK_VDDSHV_WKUP_GEN_UV,VDDSHV_WKUP_GENERAL undervoltage POK 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" line.long 0x8 "CFG0_PRG_PP_POR_CTRL," bitfld.long 0x8 16.--17. "PRG_PP_POR_CTRL_DEGLITCH_SEL,Deglitch period for PRG_PP_POR POKs Field values (others are reserved): 2'b00 - 5 us 2'b01 - 10 us 2'b10 - 15 us 2'b11 - 20 us" "0,1,2,3" newline bitfld.long 0x8 15. "PRG_PP_POR_CTRL_POK_EN_SEL,Select POK enable source 0 - POK enables come from hardware tie-offs 1 - POK enables come from PRG_PP_POR_CTRL register" "0: POK enables come from hardware tie-offs 1,?" newline bitfld.long 0x8 4. "PRG_PP_POR_CTRL_POK_VDDA_PMIC_IN_UV_EN,Enable VDDA_PMIC_IN undervoltage POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x8 3. "PRG_PP_POR_CTRL_POK_VDD_MCU_OV_EN,Enable VDD_MCU overvoltage POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x8 2. "PRG_PP_POR_CTRL_POK_VDD_MCU_UV_EN,Enable VDD_MCU undervoltage POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x8 1. "PRG_PP_POR_CTRL_POK_VDDA_MCU_OV_EN,Enable 1.8V VDDA_MCU overvoltage POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x8 0. "PRG_PP_POR_CTRL_POK_VDDA_MCU_UV_EN,Enable 1.8V VDDA_MCU undervoltage POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" line.long 0xC "CFG0_PRG_PP_POR_STAT," bitfld.long 0xC 31. "PRG_PP_POR_STAT_POK_CLR,When set resets pgood sticky bits for VDDA_MCU VDD_MCU and VDDA_PMIC_IN voltage POK detection." "0,1" newline rbitfld.long 0xC 9. "PRG_PP_POR_STAT_POK_VDD_MCU_OV,VDD_MCU overvoltage POK detection 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0xC 8. "PRG_PP_POR_STAT_POK_VDDA_MCU_OV,1.8V VDDA_MCU overvoltage POK detection 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0xC 2. "PRG_PP_POR_STAT_POK_VDDA_PMIC_IN_UV,VDDA_PMIC_IN undervoltage POK detection 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" newline rbitfld.long 0xC 1. "PRG_PP_POR_STAT_POK_VDD_MCU_UV,VDD_MCU undervoltage POK detection 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" newline rbitfld.long 0xC 0. "PRG_PP_POR_STAT_POK_VDDA_MCU_UV,1.8V VDDA_MCU undervoltage POK detection 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" line.long 0x10 "CFG0_PRG_PP_MAIN_CTRL," bitfld.long 0x10 19. "PRG_PP_MAIN_CTRL_POK_PP_EN,POK ping-pong enable. When set enables automatic switching between undervoltage and overvoltage detection on VDD_CORE VDD_CPU VDDR_CORE VMON_EXT VMON_EXT_MAIN1P8 and VMON_EXT_MAIN3P3. This bit has no effect if the POK's.." "0: No pingpong operation,1: Pingpong operation enabled" newline bitfld.long 0x10 16.--17. "PRG_PP_MAIN_CTRL_DEGLITCH_SEL,Deglitch period for PRG_PP_MAIN POKs Field values (others are reserved): 2'b00 - 5 us 2'b01 - 10 us 2'b10 - 15 us 2'b11 - 20 us" "0,1,2,3" newline bitfld.long 0x10 15. "PRG_PP_MAIN_CTRL_POK_EN_SEL,Select POK enable source 0 - POK enables come from hardware tie-offs 1 - POK enables come from PRG_PP_MAIN_CTRL register" "0: POK enables come from hardware tie-offs 1,?" newline bitfld.long 0x10 14. "PRG_PP_MAIN_CTRL_POK_VDD_CPU1_OV_SEL,Force VDD_CPU1 POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled. 0 - Undervoltage detection or UV/OV ping-pong operation 1- Overvoltage detection.." "0: Undervoltage detection or UV/OV ping-pong..,?" newline bitfld.long 0x10 13. "PRG_PP_MAIN_CTRL_POK_VMON_EXT_MAIN3P3_OV_SEL,Force VMON_EXT_MAIN 3.3V POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled. 0 - Undervoltage detection or UV/OV ping-pong operation 1-.." "0: Undervoltage detection or UV/OV ping-pong..,?" newline bitfld.long 0x10 12. "PRG_PP_MAIN_CTRL_POK_VMON_EXT_MAIN1P8_OV_SEL,Force VMON_EXT_MAIN 1.8V POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled. 0 - Undervoltage detection or UV/OV ping-pong operation 1-.." "0: Undervoltage detection or UV/OV ping-pong..,?" newline bitfld.long 0x10 11. "PRG_PP_MAIN_CTRL_POK_VMON_EXT_OV_SEL,Force VMON_EXT POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled. 0 - Undervoltage detection or UV/OV ping-pong operation 1- Overvoltage detection.." "0: Undervoltage detection or UV/OV ping-pong..,?" newline bitfld.long 0x10 10. "PRG_PP_MAIN_CTRL_POK_VDDR_CORE_OV_SEL,Force VDDR_CORE POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled. 0 - Undervoltage detection or UV/OV ping-pong operation 1- Overvoltage.." "0: Undervoltage detection or UV/OV ping-pong..,?" newline bitfld.long 0x10 9. "PRG_PP_MAIN_CTRL_POK_VDD_CPU_OV_SEL,Force VDD_CPU POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled. 0 - Undervoltage detection or UV/OV ping-pong operation 1- Overvoltage detection.." "0: Undervoltage detection or UV/OV ping-pong..,?" newline bitfld.long 0x10 8. "PRG_PP_MAIN_CTRL_POK_VDD_CORE_OV_SEL,Force VDD_CORE POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled. 0 - Undervoltage detection or UV/OV ping-pong operation 1- Overvoltage detection.." "0: Undervoltage detection or UV/OV ping-pong..,?" newline bitfld.long 0x10 6. "PRG_PP_MAIN_CTRL_POK_VDD_CPU1_EN,Enable VDD_CPU1 POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x10 5. "PRG_PP_MAIN_CTRL_POK_VMON_EXT_MAIN3P3_EN,Enable VMON_EXT_MAIN 3.3V POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x10 4. "PRG_PP_MAIN_CTRL_POK_VMON_EXT_MAIN1P8_EN,Enable VMON_EXT_MAIN 1.8V POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x10 3. "PRG_PP_MAIN_CTRL_POK_VMON_EXT_EN,Enable VMON_EXT POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x10 2. "PRG_PP_MAIN_CTRL_POK_VDDR_CORE_EN,Enable VDDR_CORE POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x10 1. "PRG_PP_MAIN_CTRL_POK_VDD_CPU_EN,Enable VDD_CPU POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x10 0. "PRG_PP_MAIN_CTRL_POK_VDD_CORE_EN,Enable VDD_CORE POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" line.long 0x14 "CFG0_PRG_PP_MAIN_STAT," bitfld.long 0x14 31. "PRG_PP_MAIN_STAT_POK_CLR,When set resets pgood sticky bits for VDD_CORE VDD_CPU VDDR_CORE VMON_EXT VMON_EXT_MAIN1P8 and VMON_EXT_MAIN3P3 voltage POK detection." "0,1" newline rbitfld.long 0x14 14. "PRG_PP_MAIN_STAT_POK_VDD_CPU1_OV,VDD_CPU1 overvoltage POK 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 13. "PRG_PP_MAIN_STAT_POK_VMON_EXT_MAIN3P3_OV,VMON_EXT_MAIN 3.3V overvoltage POK 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 12. "PRG_PP_MAIN_STAT_POK_VMON_EXT_MAIN1P8_OV,VMON_EXT_MAIN 1.8V overvoltage POK 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 11. "PRG_PP_MAIN_STAT_POK_VMON_EXT_OV,VMON_EXT overvoltage POK 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 10. "PRG_PP_MAIN_STAT_POK_VDDR_CORE_OV,VDDR_CORE overvoltage POK 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 9. "PRG_PP_MAIN_STAT_POK_VDD_CPU_OV,VDD_CPU overvoltage POK 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 8. "PRG_PP_MAIN_STAT_POK_VDD_CORE_OV,VDD_CORE overvoltage POK 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 6. "PRG_PP_MAIN_STAT_POK_VDD_CPU1_UV,VDD_CPU1 undervoltage POK 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 5. "PRG_PP_MAIN_STAT_POK_VMON_EXT_MAIN3P3_UV,VMON_EXT_MAIN 3.3V undervoltage POK 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 4. "PRG_PP_MAIN_STAT_POK_VMON_EXT_MAIN1P8_UV,VMON_EXT_MAIN 1.8V undervoltage POK 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 3. "PRG_PP_MAIN_STAT_POK_VMON_EXT_UV,VMON_EXT undervoltage POK 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 2. "PRG_PP_MAIN_STAT_POK_VDDR_CORE_UV,VDDR_CORE undervoltage POK 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 1. "PRG_PP_MAIN_STAT_POK_VDD_CPU_UV,VDD_CPU undervoltage POK 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 0. "PRG_PP_MAIN_STAT_POK_VDD_CORE_UV,VDD_CORE undervoltage POK 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" rgroup.long 0x18280++0x17 line.long 0x0 "CFG0_WKUP_CLKGATE_CTRL," hexmask.long 0x0 6.--31. 1. "WKUP_CLKGATE_CTRL_WKUP_NOGATE_RSVD,WKUP reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power savings 1 - Clocks.." newline bitfld.long 0x0 5. "WKUP_CLKGATE_CTRL_WKUP_SA2SS_NOGATE,WKUP SA2SS clock gate disable 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x0 4. "WKUP_CLKGATE_CTRL_WKUP_SMS_NOGATE,WKUP SMS clock gate disable 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x0 2. "WKUP_CLKGATE_CTRL_WKUP_ECC_AGG_NOGATE,WKUP ECC Aggregator clock gate disable 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x0 1. "WKUP_CLKGATE_CTRL_WKUP_FW_CBA_NOGATE,WKUP domain Firewall bus (wkup_fw_cbass) clock gate disable 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x0 0. "WKUP_CLKGATE_CTRL_WKUP_CBA_NOGATE,WKUP domain Data bus (wkup_cbass) clock gate disable 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" line.long 0x4 "CFG0_MCU_CLKGATE_CTRL," hexmask.long.word 0x4 21.--31. 1. "MCU_CLKGATE_CTRL_MCU_PER_NOGATE_RSVD,MCU reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power savings 1 - Clocks.." newline bitfld.long 0x4 20. "MCU_CLKGATE_CTRL_MCU_PDMA_G2,MCU domain MCAN1/USART0 PDMA clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x4 19. "MCU_CLKGATE_CTRL_MCU_PDMA_G0,MCU domain MCAN0/SPI0 PDMA clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x4 18. "MCU_CLKGATE_CTRL_MCU_PULSAR_NOGATE,MCU domain Pulsar clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x4 17. "MCU_CLKGATE_CTRL_MCU_NAV_UDMASS_NOGATE,MCU NavSS UDMA interface clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x4 16. "MCU_CLKGATE_CTRL_MCU_NAV_MODSS_NOGATE,MCU NavSS MODSS interface clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline hexmask.long.word 0x4 4.--15. 1. "MCU_CLKGATE_CTRL_MCU_CBA_NOGATE_RSVD,MCU reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power savings 1 - Clocks.." newline bitfld.long 0x4 3. "MCU_CLKGATE_CTRL_MCU_DBG_CBA_NOGATE,MCU domain Debug bus (mcu_dbg_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x4 2. "MCU_CLKGATE_CTRL_MCU_ECC_AGG_NOGATE,MCU ECC Aggregator clock gate disable 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x4 1. "MCU_CLKGATE_CTRL_MCU_FW_CBA_NOGATE,MCU domain Firewall bus (mcu_fw_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x4 0. "MCU_CLKGATE_CTRL_MCU_CBA_NOGATE,MCU domain Data bus (mcu_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" line.long 0x8 "CFG0_MAIN_CLKGATE_CTRL0," bitfld.long 0x8 29.--31. "MAIN_CLKGATE_CTRL0_MAIN_CBA2_NOGATE_RSVD,MAIN CBA reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power savings 1.." "0: Clocks are gated on idle for power savings 1,?,?,?,?,?,?,?" newline bitfld.long 0x8 28. "MAIN_CLKGATE_CTRL0_MAIN_DEBUG_BOLTON_CBA,MAIN domain debug bolton bus (debug_bolton_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 27. "MAIN_CLKGATE_CTRL0_MAIN_AC_CFG_NOGATE,MAIN domain AC Configuration bus (ac_cfg_fw_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 26. "MAIN_CLKGATE_CTRL0_MAIN_AC_ECC_AGG_NOGATE,MAIN domain AC ECC aggregator bus (ac_pipe_ecc_aggr) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 25. "MAIN_CLKGATE_CTRL0_MAIN_AC_CBA_NOGATE,MAIN domain AC Firewall bus (ac_pipe_cbass_main_fw_cbass_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 24. "MAIN_CLKGATE_CTRL0_MAIN_CBA1_NOGATE_RSVD,MAIN CBA reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power savings 1.." "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 23. "MAIN_CLKGATE_CTRL0_MAIN_HC_CFG_CBA_NOGATE,MAIN domain HC Configuration bus (hc_cfg_cbass_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 22. "MAIN_CLKGATE_CTRL0_MAIN_HC_ECC_AGG_NOGATE,MAIN domain HC ECC aggregator (nogate) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 21. "MAIN_CLKGATE_CTRL0_MAIN_HC_FW_CBA_NOGATE,MAIN domain HC Firewall bus (main_hc2_fw_cbass_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 20. "MAIN_CLKGATE_CTRL0_MAIN_HC_CBA_NOGATE,MAIN domain HC Data bus (hc2_cbass_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 19. "MAIN_CLKGATE_CTRL0_MAIN_DBG_DATA_CBA_NOGATE,MAIN domain Debug Data bus (debug_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 18. "MAIN_CLKGATE_CTRL0_MAIN_DBG_CBA_NOGATE,MAIN domain Debug bus (debug_cbass_wrap_main_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 17. "MAIN_CLKGATE_CTRL0_MAIN_IP_CSI_CBA_NOGATE,MAIN domain CSI bus (csi_cbass_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 16. "MAIN_CLKGATE_CTRL0_MAIN_IP_NS_CBA_NOGATE_RSVD,MAIN nonsafety CBA reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for.." "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 15. "MAIN_CLKGATE_CTRL0_MAIN_IP_NONSAFE_CBA_NOGATE,MAIN domain Interface Peripheral nonsafety IP bus (ipphy_cbass_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 14. "MAIN_CLKGATE_CTRL0_MAIN_IP_ECC_AGG_NOGATE,MAIN domain Interface Peripheral ECC aggregator (main_spi0_g0_main_0_ecc_aggr_main_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 13. "MAIN_CLKGATE_CTRL0_MAIN_IP_FW_CBA_NOGATE,MAIN domain Interface Peripheral Firewall bus (ipphy_cbass_main_fw_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 12. "MAIN_CLKGATE_CTRL0_MAIN_IP_CBA_NOGATE,MAIN domain Interface Peripheral bus (ipphy_safe_cbass_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 11. "MAIN_CLKGATE_CTRL0_MAIN_RC_CFG_CBA_NOGATE,MAIN domain RC Configuration bus (rc_cfg_cbass_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 10. "MAIN_CLKGATE_CTRL0_MAIN_RC_ECC_AGG_NOGATE,MAIN domain RC ECC aggregator (main_rc_ecc_aggr_main_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 9. "MAIN_CLKGATE_CTRL0_MAIN_RC_FW_CBA_NOGATE,MAIN domain RC Firewall bus (rc_cbass_main_fw_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 8. "MAIN_CLKGATE_CTRL0_MAIN_RC_CBA_NOGATE,MAIN domain RC Data bus (rc_cbass_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 7. "MAIN_CLKGATE_CTRL0_MAIN_PULSAR1_MEM_NOGATE,MAIN domain Pulsar 1 memory bus (pulsar1_mem_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 6. "MAIN_CLKGATE_CTRL0_MAIN_PULSAR1_SWITCH_CBA_NOGATE,MAIN domain Pulsar 1 peripheral switch bus (pulsar1_periph_switch_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 5. "MAIN_CLKGATE_CTRL0_MAIN_PULSAR0_MEM_NOGATE,MAIN domain Pulsar 0 memory bus (pulsar0_mem_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 4. "MAIN_CLKGATE_CTRL0_MAIN_PULSAR0_SLV_NOGATE,MAIN domain Pulsar slave bus (pulsar0_slv_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 3. "MAIN_CLKGATE_CTRL0_MAIN_INFRA_NONSAFE_CBA_NOGATE,MAIN domain Infrastructure non-safety IP bus (main_infra_non_safe_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 2. "MAIN_CLKGATE_CTRL0_MAIN_INFRA_ECC_AGG_NOGATE,MAIN domain Infrastructure ECC aggregator (main_infra_ecc_aggr) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 1. "MAIN_CLKGATE_CTRL0_MAIN_INFRA_FW_CBA_NOGATE,MAIN domain Infrastructure Firewall bus (main_infra_fw_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 0. "MAIN_CLKGATE_CTRL0_MAIN_INFRA_CBA_NOGATE,MAIN domain Infrastructure bus (main_infra_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" line.long 0xC "CFG0_MAIN_CLKGATE_CTRL1," hexmask.long.byte 0xC 24.--31. 1. "MAIN_CLKGATE_CTRL1_MAIN_CG1_NOGATE_RSVD,MAIN PDMA clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power savings 1 - Clocks.." newline bitfld.long 0xC 23. "MAIN_CLKGATE_CTRL1_MAIN_PDMA_DEBUG_G1_NOGATE,MAIN domain PDMA Debug_G1 clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 22. "MAIN_CLKGATE_CTRL1_MAIN_PDMA_DEBUG_G0_NOGATE,MAIN domain PDMA Debug_G0 clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 21. "MAIN_CLKGATE_CTRL1_MAIN_PDMA_MCASP_NOGATE,MAIN domain PDMA MCASP clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 20. "MAIN_CLKGATE_CTRL1_MAIN_PDMA_MCAN_NOGATE,MAIN domain PDMA MCAN clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 19. "MAIN_CLKGATE_CTRL1_MAIN_PDMA_USART_PSILSS_NOGATE,MAIN domain PDMA USART PSILSS clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 18. "MAIN_CLKGATE_CTRL1_MAIN_PDMA_SPI_G1_NOGATE,MAIN domain PDMA SPI_G1 clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 17. "MAIN_CLKGATE_CTRL1_MAIN_PDMA_SPI_G0_NOGATE,MAIN domain PDMA SPI_G0 clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 16. "MAIN_CLKGATE_CTRL1_MAIN_PDMA_SPI_PSILSS_NOGATE,MAIN domain PDMA SPI PSILSS clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 14.--15. "MAIN_CLKGATE_CTRL1_MAIN_IP2_NOGATE_RSVD,MAIN IP reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power savings 1 -.." "0: Clocks are gated on idle for power savings 1,?,?,?" newline bitfld.long 0xC 13. "MAIN_CLKGATE_CTRL1_MAIN_VPAC1_NOGATE,MAIN domain VPAC 1 clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 12. "MAIN_CLKGATE_CTRL1_MAIN_VPAC0_NOGATE,MAIN domain VPAC 0 clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 11. "MAIN_CLKGATE_CTRL1_MAIN_IP1_NOGATE_RSVD,MAIN IP reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power savings 1 -.." "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 10. "MAIN_CLKGATE_CTRL1_MAIN_PULSAR2_NOGATE,MAIN domain Pulsar 2 clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 9. "MAIN_CLKGATE_CTRL1_MAIN_PULSAR1_NOGATE,MAIN domain Pulsar 1 clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 8. "MAIN_CLKGATE_CTRL1_MAIN_PULSAR0_NOGATE,MAIN domain Pulsar 0 clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 5.--7. "MAIN_CLKGATE_CTRL1_MAIN_IP0_NOGATE_RSVD,MAIN IP reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power savings 1 -.." "0: Clocks are gated on idle for power savings 1,?,?,?,?,?,?,?" newline bitfld.long 0xC 4. "MAIN_CLKGATE_CTRL1_MAIN_NAV_MV_FW_NOGATE,MAIN NavSS Mod/Virt Firewall interface clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 3. "MAIN_CLKGATE_CTRL1_MAIN_NAV_VIRTSS_NOGATE,MAIN NavSS VIRTSS interface clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 2. "MAIN_CLKGATE_CTRL1_MAIN_NAV_NBSS_NOGATE,MAIN NavSS NB interface clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 1. "MAIN_CLKGATE_CTRL1_MAIN_NAV_UDMASS_NOGATE,Main NavSS UDMA interface clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 0. "MAIN_CLKGATE_CTRL1_MAIN_NAV_MODSS_NOGATE,MAIN NavSS MODSS interface clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" line.long 0x10 "CFG0_MAIN_CLKGATE_CTRL2," hexmask.long.byte 0x10 26.--31. 1. "MAIN_CLKGATE_CTRL2_MAIN_CG2_2_NOGATE_RSVD,MAIN domain spare clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power savings.." newline bitfld.long 0x10 25. "MAIN_CLKGATE_CTRL2_MAIN_CSITX1_NOGATE,MAIN domain CSI_TX1 clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x10 24. "MAIN_CLKGATE_CTRL2_MAIN_CSITX0_NOGATE,MAIN domain CSI_TX0 clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline hexmask.long.byte 0x10 19.--23. 1. "MAIN_CLKGATE_CTRL2_MAIN_CG2_1_NOGATE_RSVD,MAIN domain spare clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power savings.." newline bitfld.long 0x10 18. "MAIN_CLKGATE_CTRL2_MAIN_SA2_CPSW_PSILSS_NOGATE,MAIN domain SA2_UL/SPCW PSILSS clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x10 17. "MAIN_CLKGATE_CTRL2_MAIN_DMPAC_VPAC_PSILSS_NOGATE,MAIN domain DMPAC/VPAC PSILSS clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x10 16. "MAIN_CLKGATE_CTRL2_MAIN_CSI_PSILSS_NOGATE,MAIN domain CSI PSILSS clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline hexmask.long.word 0x10 3.--15. 1. "MAIN_CLKGATE_CTRL2_MAIN_CG2_0_NOGATE_RSVD,MAIN domain spare clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power savings.." newline bitfld.long 0x10 2. "MAIN_CLKGATE_CTRL2_MAIN_AC_ECC_AGG_STOG_NOGATE,MAIN domain ac ECC aggregator Slave Timeout Gasket (main_ac_ecc_aggr_stog) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x10 1. "MAIN_CLKGATE_CTRL2_MAIN_GPU_SLV_STOG_M2P_NOGATE,MAIN domain GPU Slave Timeout Gasket output (main_gpu_slv_stog_m2p_pwr_dis) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x10 0. "MAIN_CLKGATE_CTRL2_MAIN_GPU_SLV_STOG_P2M_NOGATE,MAIN domain GPU Slave Timeout Gasket input (main_gpu_slv_stog_p2m_pwr_dis) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" line.long 0x14 "CFG0_MAIN_CLKGATE_CTRL3," hexmask.long 0x14 0.--31. 1. "MAIN_CLKGATE_CTRL3_MAIN_CG3_NOGATE_RSVD,MAIN domain spare clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power savings 1.." rgroup.long 0x18300++0x3 line.long 0x0 "CFG0_HYPERNET_WAKE_CTRL," hexmask.long 0x0 1.--31. 1. "HYPERNET_WAKE_CTRL_MW,HYPERNET IO magic word. This 31-bit value that enables placing of the HYPERNET I/Os into isolation for daisy-chain wakeup operation. 0x5555 - Magic word value to enable isolation when qualified with mw_load bit Others - Any.." newline bitfld.long 0x0 0. "HYPERNET_WAKE_CTRL_MW_LOAD_EN,Magic word load enable Setting this bit to 1 loads and locks the mw field for HYPERNET IO isolation. If the mw field matches the magic word value then the value is latched into the HYPERNET IO voltage domain and HYPERNET IO.." "0: Unlock and do not load mw value for comparison 1,?" rgroup.long 0x18308++0x7 line.long 0x0 "CFG0_HYPERNET_WAKE_STAT0," hexmask.long 0x0 1.--31. 1. "HYPERNET_WAKE_STAT0_MW_STAT,HYPERNET magic word status Indicates the latched value of the mw field." newline bitfld.long 0x0 0. "HYPERNET_WAKE_STAT0_MW_LOAD_STAT,Magic word load status. Indicates the latched value of the mw_load_en bit" "0,1" line.long 0x4 "CFG0_HYPERNET_WAKE_STAT1," bitfld.long 0x4 0. "HYPERNET_WAKE_STAT1_HYPERNET_IO_MODE,Indicates if HYPERNET IO wakeup mode is enabled. 0 - Not enabled (load_en not set or mw doesn't match magic word) 1 - HYPERNET IO mode enabled" "0: Not enabled,1: HYPERNET IO mode enabled" rgroup.long 0x18310++0x3 line.long 0x0 "CFG0_MCU_GEN_WAKE_CTRL," hexmask.long 0x0 1.--31. 1. "MCU_GEN_WAKE_CTRL_MW,MCU_GENERAL IO magic word. This 31-bit value that enables placing of the MCU_GENERAL I/Os into isolation for daisy-chain wakeup operation. 0x5555 - Magic word value to enable isolation when qualified with mw_load bit Others -.." newline bitfld.long 0x0 0. "MCU_GEN_WAKE_CTRL_MW_LOAD_EN,Magic word load enable Setting this bit to 1 loads and locks the mw field for MCU_GENERAL IO isolation. If the mw field matches the magic word value then the value is latched into the MCU_GENERAL IO voltage domain and.." "0: Unlock and do not load mw value for comparison 1,?" rgroup.long 0x18318++0x7 line.long 0x0 "CFG0_MCU_GEN_WAKE_STAT0," hexmask.long 0x0 1.--31. 1. "MCU_GEN_WAKE_STAT0_MW_STAT,MCU_GENERAL magic word status Indicates the latched value of the mw field." newline bitfld.long 0x0 0. "MCU_GEN_WAKE_STAT0_MW_LOAD_STAT,Magic word load status. Indicates the latched value of the mw_load_en bit" "0,1" line.long 0x4 "CFG0_MCU_GEN_WAKE_STAT1," bitfld.long 0x4 0. "MCU_GEN_WAKE_STAT1_MCU_GEN_IO_MODE,Indicates if MCU_GENERAL IO wakeup mode is enabled. 0 - Not enabled (load_en not set or mw doesn't match magic word) 1 - MCU_GENERAL IO mode enabled" "0: Not enabled,1: MCU_GENERAL IO mode enabled" rgroup.long 0x18380++0x7 line.long 0x0 "CFG0_POK_ISO_EVENT_SEL," hexmask.long 0x0 2.--31. 1. "POK_ISO_EVENT_SEL_POK_RSVD,Reserved for future use (do not optimize out)" newline bitfld.long 0x0 1. "POK_ISO_EVENT_SEL_POK_VDD_CORE_OV,VDD_CORE overvoltage detection triggers enabled isolation actions" "0,1" newline bitfld.long 0x0 0. "POK_ISO_EVENT_SEL_POK_VDD_CORE_UV,VDD_CORE undervoltage detection triggers enabled isolation actions" "0,1" line.long 0x4 "CFG0_POK_ISO_ACTION_EN," hexmask.long.word 0x4 21.--31. 1. "POK_ISO_ACTION_EN_RSVD_TOG_FLUSH,Reserved timeout gasket flush enable bits. Do not optimize out 0 - Enabled POK events have no effect on this gasket 1 - Enabled POK events will assert the flush for this gasket" newline bitfld.long 0x4 20. "POK_ISO_ACTION_EN_WKUP2MAIN_INFRA_STOG_FLUSH,WKUP to Main INFRA slave timeout gasket flush enable: 0 - Enabled POK events have no effect on this gasket 1 - Enabled POK events will assert the flush for this gasket" "0: Enabled POK events have no effect on this gasket..,?" newline bitfld.long 0x4 19. "POK_ISO_ACTION_EN_MCU2MAIN_INFRA_STOG_FLUSH,MCU to Main INFRA slave timeout gasket flush enable: 0 - Enabled POK events have no effect on this gasket 1 - Enabled POK events will assert the flush for this gasket" "0: Enabled POK events have no effect on this gasket..,?" newline bitfld.long 0x4 18. "POK_ISO_ACTION_EN_MCU2MAIN_RC_STOG_FLUSH,MCU to Main RC slave timeout gasket flush enable: 0 - Enabled POK events have no effect on this gasket 1 - Enabled POK events will assert the flush for this gasket" "0: Enabled POK events have no effect on this gasket..,?" newline bitfld.long 0x4 17. "POK_ISO_ACTION_EN_MCU2MAIN_FW_STOG_FLUSH,MCU to Main FW slave timeout gasket flush enable: 0 - Enabled POK events have no effect on this gasket 1 - Enabled POK events will assert the flush for this gasket" "0: Enabled POK events have no effect on this gasket..,?" newline bitfld.long 0x4 16. "POK_ISO_ACTION_EN_MAIN2MCU_MTOG_FLUSH,MAIN to MCU master timeout gasket flush enable: 0 - Enabled POK events have no effect on this gasket 1 - Enabled POK events will assert the flush for this gasket" "0: Enabled POK events have no effect on this gasket..,?" newline hexmask.long.byte 0x4 9.--15. 1. "POK_ISO_ACTION_EN_RSVD_ACT_B,Reserved isolation action enable bits. Do not optimize out" newline bitfld.long 0x4 8. "POK_ISO_ACTION_EN_ISOLATE,If enabled the isolate signal will be asserted after all enabled flush signals have been asserted for 4 of their respective time-out gasket clocks when any selected POK event occurs. 0 - Isolation is not asserted on selected.." "0: Isolation is not asserted on selected POK event 1,?" newline hexmask.long.byte 0x4 4.--7. 1. "POK_ISO_ACTION_EN_RSVD_ACT_A,Reserved isolation action enable bits. Do not optimize out" newline hexmask.long.byte 0x4 0.--3. 1. "POK_ISO_ACTION_EN_MAIN_POR,When set to 4'b0110 MAIN_PORz reset is asserted when any selected POK event occurs. (Reserved for future use do not optimize out)" rgroup.long 0x18388++0x3 line.long 0x0 "CFG0_POK_ISO_ACTION_STAT," hexmask.long 0x0 3.--31. 1. "POK_ISO_ACTION_STAT_RSVD_STAT,Reserved POK action status - do not optimize out" newline bitfld.long 0x0 2. "POK_ISO_ACTION_STAT_FLUSH,POK activated timeout gasket flush status This signal will remain asserted until a 1 is written to the POK_ISO_ACTION_CLR_flush bit. 0 - No gasket flush is being asserted by enabled POK event 1 - Enabled gasket flush signals.." "0: No gasket flush is being asserted by enabled POK..,?" newline bitfld.long 0x0 1. "POK_ISO_ACTION_STAT_ISOLATE,POK activated Isolate status This signal will remain asserted until a 1 is written to the POK_ISO_ACTION_CLR_isolate bit. 0 - No isolate is being asserted by enabled POK event 1 - Isolate signal is being asserted due to an.." "0: No isolate is being asserted by enabled POK..,?" newline bitfld.long 0x0 0. "POK_ISO_ACTION_STAT_MAIN_POR,Reserved POK activated MAIN_PORz status - do not optimize out 0 - No MAIN_PORz is being asserted by enabled POK event 1 - MAIN_PORz is being asserted due to an enabled POK event" "0: No MAIN_PORz is being asserted by enabled POK..,?" rgroup.long 0x1838C++0x7 line.long 0x0 "CFG0_POK_ISO_ACTION_CLR," hexmask.long 0x0 3.--31. 1. "POK_ISO_ACTION_CLR_RSVD_CLR,Reserved POK activated signal clear - do not optimize out Always read as 0. Writing 1 deasserts POK activated signal. 0 - Writing 0 has no effect. Bit always reads as 0 1 - Deassert signal. Bit will clear to 0 after write." newline bitfld.long 0x0 2. "POK_ISO_ACTION_CLR_FLUSH,POK activated timeout gasket flush clear Always read as 0. Writing 1 deasserts POK activated timeot gasket flush signals. 0 - Writing 0 has no effect. Bit always reads as 0 1 - Deassert gasket flush signals. Bit will clear.." "0: Writing 0 has no effect,1: Deassert gasket flush signals" newline bitfld.long 0x0 1. "POK_ISO_ACTION_CLR_ISOLATE,POK activated isolate clear Always read as 0. Writing 1 deasserts POK activated isolate signal. 0 - Writing 0 has no effect. Bit always reads as 0 1 - Deassert isolate signal. Bit will clear to 0 after write." "0: Writing 0 has no effect,1: Deassert isolate signal" newline bitfld.long 0x0 0. "POK_ISO_ACTION_CLR_MAIN_POR,Reserved POK activated MAIN_PORz clear - do not optimize out Always read as 0. Writing 1 deasserts POK activated MAIN_PORz signal. 0 - Writing 0 has no effect. Bit always reads as 0 1 - Deassert MAIN_PORz. Bit will clear.." "0: Writing 0 has no effect,1: Deassert MAIN_PORz" line.long 0x4 "CFG0_POK_ISO_GP_CTRL," hexmask.long 0x4 0.--31. 1. "POK_ISO_GP_CTRL_RSVD_CTRL,Reserved POK isolation control bits" rgroup.long 0x18394++0x3 line.long 0x0 "CFG0_POK_ISO_GP_STAT," hexmask.long 0x0 0.--31. 1. "POK_ISO_GP_STAT_RSVD_STAT,Reserved POK isolation status bits" rgroup.long 0x19008++0x7 line.long 0x0 "CFG0_LOCK6_KICK0," hexmask.long 0x0 0.--31. 1. "LOCK6_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK6_KICK1," hexmask.long 0x4 0.--31. 1. "LOCK6_KICK1,- KICK1 component" rgroup.long 0x19100++0x1F line.long 0x0 "CFG0_CLAIMREG_P6_R0_READONLY," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P6_R0_READONLY,Claim bits for Partition 6" line.long 0x4 "CFG0_CLAIMREG_P6_R1_READONLY," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P6_R1_READONLY,Claim bits for Partition 6" line.long 0x8 "CFG0_CLAIMREG_P6_R2_READONLY," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P6_R2_READONLY,Claim bits for Partition 6" line.long 0xC "CFG0_CLAIMREG_P6_R3_READONLY," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P6_R3_READONLY,Claim bits for Partition 6" line.long 0x10 "CFG0_CLAIMREG_P6_R4_READONLY," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P6_R4_READONLY,Claim bits for Partition 6" line.long 0x14 "CFG0_CLAIMREG_P6_R5_READONLY," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P6_R5_READONLY,Claim bits for Partition 6" line.long 0x18 "CFG0_CLAIMREG_P6_R6_READONLY," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P6_R6_READONLY,Claim bits for Partition 6" line.long 0x1C "CFG0_CLAIMREG_P6_R7_READONLY," hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P6_R7_READONLY,Claim bits for Partition 6" rgroup.long 0x1A000++0x3 line.long 0x0 "CFG0_POR_CTRL_PROXY," bitfld.long 0x0 29. "POR_CTRL_OVRD_SET5_PROXY,Reserved override set" "0,1" newline bitfld.long 0x0 28. "POR_CTRL_OVRD_SET4_PROXY,POKLVB override set" "0,1" newline bitfld.long 0x0 27. "POR_CTRL_OVRD_SET3_PROXY,POKLVA override set" "0,1" newline bitfld.long 0x0 26. "POR_CTRL_OVRD_SET2_PROXY,POKHV override set" "0,1" newline bitfld.long 0x0 25. "POR_CTRL_OVRD_SET1_PROXY,BGOK override set" "0,1" newline bitfld.long 0x0 24. "POR_CTRL_OVRD_SET0_PROXY,PORHV override set" "0,1" newline bitfld.long 0x0 21. "POR_CTRL_OVRD5_PROXY,Reserved override enable" "0,1" newline bitfld.long 0x0 20. "POR_CTRL_OVRD4_PROXY,POKLVB override enable" "0,1" newline bitfld.long 0x0 19. "POR_CTRL_OVRD3_PROXY,POKLVA override enable" "0,1" newline bitfld.long 0x0 18. "POR_CTRL_OVRD2_PROXY,POKHV override enable" "0,1" newline bitfld.long 0x0 17. "POR_CTRL_OVRD1_PROXY,BGOK override enable" "0,1" newline bitfld.long 0x0 16. "POR_CTRL_OVRD0_PROXY,PORHV override enable" "0,1" newline bitfld.long 0x0 7. "POR_CTRL_TRIM_SEL_PROXY,POR Trim Select 0 - Trim selections for Bandgap and POKs come from HHV defaults 1 - Trim selections for Bandgap and POKs come from POR_BANDGAP_CTRL and POR_POKxxx_CTRL registers" "0: Trim selections for Bandgap and POKs come from..,?" newline bitfld.long 0x0 4. "POR_CTRL_MASK_HHV_PROXY,Mask HHV/SOC_PORz outputs when applying new trim values" "0,1" rgroup.long 0x1A004++0x3 line.long 0x0 "CFG0_POR_STAT_PROXY," bitfld.long 0x0 8. "POR_STAT_BGOK_PROXY,Bandgap OK status" "0,1" newline bitfld.long 0x0 4. "POR_STAT_SOC_POR_PROXY,POR module status 0 - Module is in functional mode 1 - Module is in reset mode" "0: Module is in functional mode 1,?" rgroup.long 0x1A010++0x1F line.long 0x0 "CFG0_POK_VDDA_PMIC_IN_CTRL_PROXY," bitfld.long 0x0 31. "POK_VDDA_PMIC_IN_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0x0 0. "POK_VDDA_PMIC_IN_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" line.long 0x4 "CFG0_POK_VDDSHV_WKUP_GEN_UV_CTRL_PROXY," bitfld.long 0x4 31. "POK_VDDSHV_WKUP_GEN_UV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0x4 7. "POK_VDDSHV_WKUP_GEN_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x4 0.--6. 1. "POK_VDDSHV_WKUP_GEN_UV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and J7 efuse spec for details" line.long 0x8 "CFG0_POK_VDDR_MCU_UV_CTRL_PROXY," bitfld.long 0x8 31. "POK_VDDR_MCU_UV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0x8 7. "POK_VDDR_MCU_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x8 0.--6. 1. "POK_VDDR_MCU_UV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and J7 efuse spec for details" line.long 0xC "CFG0_POK_VMON_CAP_MCU_GEN_UV_CTRL_PROXY," bitfld.long 0xC 31. "POK_VMON_CAP_MCU_GEN_UV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0xC 7. "POK_VMON_CAP_MCU_GEN_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0xC 0.--6. 1. "POK_VMON_CAP_MCU_GEN_UV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x10 "CFG0_POK_VDD_MCU_OV_CTRL_PROXY," bitfld.long 0x10 31. "POK_VDD_MCU_OV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0x10 7. "POK_VDD_MCU_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x10 0.--6. 1. "POK_VDD_MCU_OV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and J7 efuse spec for details" line.long 0x14 "CFG0_POK_VDDSHV_WKUP_GEN_OV_CTRL_PROXY," bitfld.long 0x14 31. "POK_VDDSHV_WKUP_GEN_OV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0x14 7. "POK_VDDSHV_WKUP_GEN_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x14 0.--6. 1. "POK_VDDSHV_WKUP_GEN_OV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and J7 efuse spec for details" line.long 0x18 "CFG0_POK_VDDR_MCU_OV_CTRL_PROXY," bitfld.long 0x18 31. "POK_VDDR_MCU_OV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0x18 7. "POK_VDDR_MCU_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x18 0.--6. 1. "POK_VDDR_MCU_OV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and J7 efuse spec for details" line.long 0x1C "CFG0_POK_VMON_CAP_MCU_GEN_OV_CTRL_PROXY," bitfld.long 0x1C 31. "POK_VMON_CAP_MCU_GEN_OV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0x1C 7. "POK_VMON_CAP_MCU_GEN_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x1C 0.--6. 1. "POK_VMON_CAP_MCU_GEN_OV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" rgroup.long 0x1A070++0x3 line.long 0x0 "CFG0_MAIN_VDOM_CTRL_PROXY," bitfld.long 0x0 0. "MAIN_VDOM_CTRL_MAIN_VD_OFF_PROXY,MAIN deep sleep isolation enable. This bit should be set prior to powering off the MAIN voltage domain to ensure proper signal isolation." "0,1" rgroup.long 0x1A080++0xF line.long 0x0 "CFG0_POR_POKHV_UV_CTRL_PROXY," bitfld.long 0x0 31. "POR_POKHV_UV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0x0 7. "POR_POKHV_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x0 0.--6. 1. "POR_POKHV_UV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and J7 efuse spec for details" line.long 0x4 "CFG0_POR_POKLVB_UV_CTRL_PROXY," bitfld.long 0x4 31. "POR_POKLVB_UV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0x4 7. "POR_POKLVB_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x4 0.--6. 1. "POR_POKLVB_UV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and J7 efuse spec for details" line.long 0x8 "CFG0_POR_POKLVA_OV_CTRL_PROXY," bitfld.long 0x8 31. "POR_POKLVA_OV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0x8 7. "POR_POKLVA_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x8 0.--6. 1. "POR_POKLVA_OV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and J7 efuse spec for details" line.long 0xC "CFG0_POR_BANDGAP_CTRL_PROXY," hexmask.long.byte 0xC 16.--19. 1. "POR_BANDGAP_CTRL_BGAPI_PROXY,Bandgap output current trim bits" newline hexmask.long.byte 0xC 8.--15. 1. "POR_BANDGAP_CTRL_BGAPV_PROXY,Bandgap output voltage magnitude trim bits" newline hexmask.long.byte 0xC 0.--7. 1. "POR_BANDGAP_CTRL_BGAPC_PROXY,Bandgap slope trim bits. Bit7 is used to calculate the offset" rgroup.long 0x1A0A0++0x3 line.long 0x0 "CFG0_TEMP_DIODE_TRIM_PROXY," hexmask.long.word 0x0 0.--13. 1. "TEMP_DIODE_TRIM_TRIM_PROXY,Sets the diode non-ideality factor (n) starting from 100th place decimal and going down" rgroup.long 0x1A0B0++0x3 line.long 0x0 "CFG0_IO_VOLTAGE_STAT_PROXY," bitfld.long 0x0 16. "IO_VOLTAGE_STAT_MAIN_HYPERNET_PROXY,Indicates the voltage for the HYPERNET I/O group 0 - I/O group is set for 1.8V 1 - I/O group is set for 3.3V" "0: I/O group is set for 1,1: I/O group is set for 3" newline bitfld.long 0x0 10. "IO_VOLTAGE_STAT_MAIN_MMC1_PROXY,Indicates the voltage for the MMC1 I/O group 0 - I/O group is set for 1.8V 1 - I/O group is set for 3.3V" "0: I/O group is set for 1,1: I/O group is set for 3" newline bitfld.long 0x0 9. "IO_VOLTAGE_STAT_MAIN_MMC0_PROXY,Indicates the voltage for the MMC0 I/O group 0 - I/O group is set for 1.8V 1 - I/O group is set for 3.3V" "0: I/O group is set for 1,1: I/O group is set for 3" newline bitfld.long 0x0 8. "IO_VOLTAGE_STAT_MAIN_GEN_PROXY,Indicates the voltage for the General I/O group 0 - I/O group is set for 1.8V 1 - I/O group is set for 3.3V" "0: I/O group is set for 1,1: I/O group is set for 3" newline bitfld.long 0x0 2. "IO_VOLTAGE_STAT_MCU_RGMII_PROXY,Indicates the voltage for the MCU CPSW2G RGMII I/O group 0 - I/O group is set for 1.8V 1 - I/O group is set for 3.3V" "0: I/O group is set for 1,1: I/O group is set for 3" newline bitfld.long 0x0 1. "IO_VOLTAGE_STAT_MCU_FLASH_PROXY,Indicates the voltage for the MCU Flash I/O group 0 - I/O group is set for 1.8V 1 - I/O group is set for 3.3V" "0: I/O group is set for 1,1: I/O group is set for 3" newline bitfld.long 0x0 0. "IO_VOLTAGE_STAT_MCU_GEN_PROXY,Indicates the voltage for the MCU General I/O group 0 - I/O group is set for 1.8V 1 - I/O group is set for 3.3V" "0: I/O group is set for 1,1: I/O group is set for 3" rgroup.long 0x1A104++0x3 line.long 0x0 "CFG0_MAIN_POR_TO_CTRL_PROXY," bitfld.long 0x0 0.--2. "MAIN_POR_TO_CTRL_TIMEOUT_PER_PROXY,MAIN PORz hardware timeout period. During normal operation the assertion of a MAIN Domain PORz generates a reset request interrupt to the DMSC. The DMSC then performs steps to properly isolate the MAIN Domain before.." "0: Immediate 3'b001,?,?,?,?,?,?,?" rgroup.long 0x1A110++0x37 line.long 0x0 "CFG0_POK_VDD_CORE_UV_CTRL_PROXY," bitfld.long 0x0 31. "POK_VDD_CORE_UV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0x0 7. "POK_VDD_CORE_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x0 0.--6. 1. "POK_VDD_CORE_UV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x4 "CFG0_POK_VDD_CPU_UV_CTRL_PROXY," bitfld.long 0x4 31. "POK_VDD_CPU_UV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0x4 7. "POK_VDD_CPU_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x4 0.--6. 1. "POK_VDD_CPU_UV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x8 "CFG0_POK_VMON_EXT_UV_CTRL_PROXY," bitfld.long 0x8 31. "POK_VMON_EXT_UV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0x8 7. "POK_VMON_EXT_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x8 0.--6. 1. "POK_VMON_EXT_UV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0xC "CFG0_POK_VDDR_CORE_UV_CTRL_PROXY," bitfld.long 0xC 31. "POK_VDDR_CORE_UV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0xC 7. "POK_VDDR_CORE_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0xC 0.--6. 1. "POK_VDDR_CORE_UV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x10 "CFG0_POK_VDD_CORE_OV_CTRL_PROXY," bitfld.long 0x10 31. "POK_VDD_CORE_OV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0x10 7. "POK_VDD_CORE_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x10 0.--6. 1. "POK_VDD_CORE_OV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x14 "CFG0_POK_VDD_CPU_OV_CTRL_PROXY," bitfld.long 0x14 31. "POK_VDD_CPU_OV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0x14 7. "POK_VDD_CPU_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x14 0.--6. 1. "POK_VDD_CPU_OV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x18 "CFG0_POK_VMON_EXT_OV_CTRL_PROXY," bitfld.long 0x18 31. "POK_VMON_EXT_OV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0x18 7. "POK_VMON_EXT_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x18 0.--6. 1. "POK_VMON_EXT_OV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x1C "CFG0_POK_VDDR_CORE_OV_CTRL_PROXY," bitfld.long 0x1C 31. "POK_VDDR_CORE_OV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0x1C 7. "POK_VDDR_CORE_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x1C 0.--6. 1. "POK_VDDR_CORE_OV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x20 "CFG0_POK_VMON_EXT_MAIN1P8_UV_CTRL_PROXY," bitfld.long 0x20 31. "POK_VMON_EXT_MAIN1P8_UV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0x20 7. "POK_VMON_EXT_MAIN1P8_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x20 0.--6. 1. "POK_VMON_EXT_MAIN1P8_UV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x24 "CFG0_POK_VMON_EXT_MAIN1P8_OV_CTRL_PROXY," bitfld.long 0x24 31. "POK_VMON_EXT_MAIN1P8_OV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0x24 7. "POK_VMON_EXT_MAIN1P8_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x24 0.--6. 1. "POK_VMON_EXT_MAIN1P8_OV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x28 "CFG0_POK_VMON_EXT_MAIN3P3_UV_CTRL_PROXY," bitfld.long 0x28 31. "POK_VMON_EXT_MAIN3P3_UV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0x28 7. "POK_VMON_EXT_MAIN3P3_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x28 0.--6. 1. "POK_VMON_EXT_MAIN3P3_UV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x2C "CFG0_POK_VMON_EXT_MAIN3P3_OV_CTRL_PROXY," bitfld.long 0x2C 31. "POK_VMON_EXT_MAIN3P3_OV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0x2C 7. "POK_VMON_EXT_MAIN3P3_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x2C 0.--6. 1. "POK_VMON_EXT_MAIN3P3_OV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x30 "CFG0_POK_VDD_CPU1_UV_CTRL_PROXY," bitfld.long 0x30 31. "POK_VDD_CPU1_UV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0x30 7. "POK_VDD_CPU1_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x30 0.--6. 1. "POK_VDD_CPU1_UV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" line.long 0x34 "CFG0_POK_VDD_CPU1_OV_CTRL_PROXY," bitfld.long 0x34 31. "POK_VDD_CPU1_OV_CTRL_HYST_EN_PROXY,Enable POK hysteresis" "0,1" newline bitfld.long 0x34 7. "POK_VDD_CPU1_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0: Under voltage detection 1,?" newline hexmask.long.byte 0x34 0.--6. 1. "POK_VDD_CPU1_OV_CTRL_POK_TRIM_PROXY,POK trim bits. These bits are used to trim the comparator threshold voltage. See POK spec and efuse spec for details" rgroup.long 0x1A150++0x13 line.long 0x0 "CFG0_POK_RSV0_PROXY," hexmask.long 0x0 0.--31. 1. "RESERVED,Reserved POK bits" line.long 0x4 "CFG0_POK_RSV1_PROXY," hexmask.long 0x4 0.--31. 1. "RESERVED,Reserved POK bits" line.long 0x8 "CFG0_POK_RSV2_PROXY," hexmask.long 0x8 0.--31. 1. "RESERVED,Reserved POK bits" line.long 0xC "CFG0_POK_RSV3_PROXY," hexmask.long 0xC 0.--31. 1. "RESERVED,Reserved POK bits" line.long 0x10 "CFG0_DEEPSLEEP_CTRL_PROXY," bitfld.long 0x10 8. "DEEPSLEEP_CTRL_FORCE_DS_MAIN_PROXY,Force all MAIN IOs into deepsleep mode when set" "0,1" newline bitfld.long 0x10 0. "DEEPSLEEP_CTRL_FORCE_DS_WKUP_PROXY,Force all WKUP IOs into deepsleep mode when set" "0,1" rgroup.long 0x1A170++0x7 line.long 0x0 "CFG0_POR_RST_CTRL_PROXY," bitfld.long 0x0 24. "POR_RST_CTRL_MAIN_PORZ_DAISYCHAIN_EN_PROXY,MAIN PORz daisy-chain event enable. Determines if MAIN PORz reset events affect daisy-chain wakeup 0 - DeepSleep MAIN PORz event is not part of daisy-chain 1 - DeepSleep MAIN PORz event is combined w/ other.." "0: DeepSleep MAIN PORz event is not part of..,?" newline hexmask.long.byte 0x0 16.--19. 1. "POR_RST_CTRL_SW_MAIN_POR_PROXY,Main Domain software power-on reset. When set to 4'b0110 a power-on is issued to the MAIN voltage domain. (Bits will reset to 4'b1111 on reset of the Main Domain)" newline bitfld.long 0x0 12. "POR_RST_CTRL_MAIN_PORZ_DS_STRETCH_PROXY,DeepSleep mode MAIN PORz stretch. 0 - No stretching 1 - Stretch the Main PORz event captured during DeepSleep mode" "0: No stretching 1,?" newline bitfld.long 0x0 0. "POR_RST_CTRL_POR_RST_ISO_DONE_Z_PROXY,Reset isolation completion (active low). This bit should be cleared only after reset isolation of the MAIN domain is complete. 0 - POR reset propagates to MAIN domain 1 - POR reset blocked from MAIN domain" "0: POR reset propagates to MAIN domain 1,?" line.long 0x4 "CFG0_MAIN_WARM_RST_CTRL_PROXY," hexmask.long.byte 0x4 16.--19. 1. "MAIN_WARM_RST_CTRL_SW_WARMRST_PROXY,Main Domain software warm reset. When set to 4'b0110 a warm reset is issued to the MAIN voltage domain. (Bits will reset to 4'b1111 on reset of the Main Domain)" newline bitfld.long 0x4 0. "MAIN_WARM_RST_CTRL_SOC_WARMRST_ISO_DONE_Z_PROXY,Reset isolation completion (active low). This bit should be cleared only after reset isolation of the MAIN domain is complete. 0 - Warm reset propagates to MAIN domain 1 - Warm reset blocked from MAIN.." "0: Warm reset propagates to MAIN domain 1,?" rgroup.long 0x1A178++0x3 line.long 0x0 "CFG0_RST_STAT_PROXY," bitfld.long 0x0 16. "RST_STAT_MCU_RST_DONE_PROXY,Indicates MCU domain reset status. 0 - MCU domain is in reset 1 - MCU domain reset is complete" "0: MCU domain is in reset 1,?" newline bitfld.long 0x0 0. "RST_STAT_MAIN_RST_DONE_PROXY,Indicates MAIN domain Warm reset status. 0 - MAIN domain is in Warm reset 1 - MAIN domain Warm reset is complete" "0: MAIN domain is in Warm reset 1,?" rgroup.long 0x1A17C++0xB line.long 0x0 "CFG0_MCU_WARM_RST_CTRL_PROXY," hexmask.long.byte 0x0 16.--19. 1. "MCU_WARM_RST_CTRL_SW_WARMRST_PROXY,Chip software warm reset. When set to 4'b0110 a warm reset is issued to the device (all voltage domains). (Bits will reset to 4'b1111 on reset completion.)" line.long 0x4 "CFG0_VDD_CPU_GLDTC_CTRL_PROXY," bitfld.long 0x4 31. "VDD_CPU_GLDTC_CTRL_PWDB_PROXY,Power down - active low. 0 - Disable all functions 1 - Enable glitch detectors" "0: Disable all functions 1,?" newline bitfld.long 0x4 30. "VDD_CPU_GLDTC_CTRL_RSTB_PROXY,Reset - active low. To ensure proper operation rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold or.." "0: Reset glitch detector flags 1,?" newline bitfld.long 0x4 16.--18. "VDD_CPU_GLDTC_CTRL_LP_FILTER_SEL_PROXY,Selects the glitch detect low-pass filter bandwidth Field values (others are reserved): 3'b000 - 150 kHz 3'b001 - 125 kHz 3'b010 - 100 kHz 3'b011 - 80 kHz 3'b100 - 60 kHz 3'b101 - 45 kHz 3'b110 - 30 kHz 3'b111 - 15.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--13. 1. "VDD_CPU_GLDTC_CTRL_THRESH_HI_SEL_PROXY,Selects the high voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 93.5% of VDD 6'b000001 - 94.0% of VDD 6'b000010 - 94.5% of VDD 6'b000011 - 95.0% of.." newline hexmask.long.byte 0x4 0.--5. 1. "VDD_CPU_GLDTC_CTRL_THRESH_LO_SEL_PROXY,Selects the low voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 106.5% of VDD 6'b000001 - 106.0% of VDD 6'b000010 - 105.5% of VDD 6'b000011 - 105.0%.." line.long 0x8 "CFG0_VDD_CPU1_GLDTC_CTRL_PROXY," bitfld.long 0x8 31. "VDD_CPU1_GLDTC_CTRL_PWDB_PROXY,Power down - active low. 0 - Disable all functions 1 - Enable glitch detectors" "0: Disable all functions 1,?" newline bitfld.long 0x8 30. "VDD_CPU1_GLDTC_CTRL_RSTB_PROXY,Reset - active low. To ensure proper operation rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold.." "0: Reset glitch detector flags 1,?" newline bitfld.long 0x8 16.--18. "VDD_CPU1_GLDTC_CTRL_LP_FILTER_SEL_PROXY,Selects the glitch detect low-pass filter bandwidth Field values (others are reserved): 3'b000 - 150 kHz 3'b001 - 125 kHz 3'b010 - 100 kHz 3'b011 - 80 kHz 3'b100 - 60 kHz 3'b101 - 45 kHz 3'b110 - 30 kHz 3'b111 - 15.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--13. 1. "VDD_CPU1_GLDTC_CTRL_THRESH_HI_SEL_PROXY,Selects the high voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 93.5% of VDD 6'b000001 - 94.0% of VDD 6'b000010 - 94.5% of VDD 6'b000011 - 95.0% of.." newline hexmask.long.byte 0x8 0.--5. 1. "VDD_CPU1_GLDTC_CTRL_THRESH_LO_SEL_PROXY,Selects the low voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 106.5% of VDD 6'b000001 - 106.0% of VDD 6'b000010 - 105.5% of VDD 6'b000011 - 105.0%.." rgroup.long 0x1A190++0xF line.long 0x0 "CFG0_VDD_CORE_GLDTC_CTRL_PROXY," bitfld.long 0x0 31. "VDD_CORE_GLDTC_CTRL_PWDB_PROXY,Power down - active low. 0 - Disable all functions 1 - Enable glitch detectors" "0: Disable all functions 1,?" newline bitfld.long 0x0 30. "VDD_CORE_GLDTC_CTRL_RSTB_PROXY,Reset - active low. To ensure proper operation rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold.." "0: Reset glitch detector flags 1,?" newline bitfld.long 0x0 16.--18. "VDD_CORE_GLDTC_CTRL_LP_FILTER_SEL_PROXY,Selects the glitch detect low-pass filter bandwidth Field values (others are reserved): 3'b000 - 150 kHz 3'b001 - 125 kHz 3'b010 - 100 kHz 3'b011 - 80 kHz 3'b100 - 60 kHz 3'b101 - 45 kHz 3'b110 - 30 kHz 3'b111 - 15.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--13. 1. "VDD_CORE_GLDTC_CTRL_THRESH_HI_SEL_PROXY,Selects the high voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 93.5% of VDD 6'b000001 - 94.0% of VDD 6'b000010 - 94.5% of VDD 6'b000011 - 95.0% of.." newline hexmask.long.byte 0x0 0.--5. 1. "VDD_CORE_GLDTC_CTRL_THRESH_LO_SEL_PROXY,Selects the low voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 106.5% of VDD 6'b000001 - 106.0% of VDD 6'b000010 - 105.5% of VDD 6'b000011 - 105.0%.." line.long 0x4 "CFG0_VDDR_CPU_GLDTC_CTRL_PROXY," bitfld.long 0x4 31. "VDDR_CPU_GLDTC_CTRL_PWDB_PROXY,Power down - active low. 0 - Disable all functions 1 - Enable glitch detectors" "0: Disable all functions 1,?" newline bitfld.long 0x4 30. "VDDR_CPU_GLDTC_CTRL_RSTB_PROXY,Reset - active low. To ensure proper operation rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold.." "0: Reset glitch detector flags 1,?" newline bitfld.long 0x4 16.--18. "VDDR_CPU_GLDTC_CTRL_LP_FILTER_SEL_PROXY,Selects the glitch detect low-pass filter bandwidth Field values (others are reserved): 3'b000 - 150 kHz 3'b001 - 125 kHz 3'b010 - 100 kHz 3'b011 - 80 kHz 3'b100 - 60 kHz 3'b101 - 45 kHz 3'b110 - 30 kHz 3'b111 - 15.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--13. 1. "VDDR_CPU_GLDTC_CTRL_THRESH_HI_SEL_PROXY,Selects the high voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 93.5% of VDD 6'b000001 - 94.0% of VDD 6'b000010 - 94.5% of VDD 6'b000011 - 95.0% of.." newline hexmask.long.byte 0x4 0.--5. 1. "VDDR_CPU_GLDTC_CTRL_THRESH_LO_SEL_PROXY,Selects the low voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 106.5% of VDD 6'b000001 - 106.0% of VDD 6'b000010 - 105.5% of VDD 6'b000011 - 105.0%.." line.long 0x8 "CFG0_VDDR_CORE_GLDTC_CTRL_PROXY," bitfld.long 0x8 31. "VDDR_CORE_GLDTC_CTRL_PWDB_PROXY,Power down - active low. 0 - Disable all functions 1 - Enable glitch detectors" "0: Disable all functions 1,?" newline bitfld.long 0x8 30. "VDDR_CORE_GLDTC_CTRL_RSTB_PROXY,Reset - active low. To ensure proper operation rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold.." "0: Reset glitch detector flags 1,?" newline bitfld.long 0x8 16.--18. "VDDR_CORE_GLDTC_CTRL_LP_FILTER_SEL_PROXY,Selects the glitch detect low-pass filter bandwidth Field values (others are reserved): 3'b000 - 150 kHz 3'b001 - 125 kHz 3'b010 - 100 kHz 3'b011 - 80 kHz 3'b100 - 60 kHz 3'b101 - 45 kHz 3'b110 - 30 kHz 3'b111 -.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--13. 1. "VDDR_CORE_GLDTC_CTRL_THRESH_HI_SEL_PROXY,Selects the high voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 93.5% of VDD 6'b000001 - 94.0% of VDD 6'b000010 - 94.5% of VDD 6'b000011 - 95.0%.." newline hexmask.long.byte 0x8 0.--5. 1. "VDDR_CORE_GLDTC_CTRL_THRESH_LO_SEL_PROXY,Selects the low voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 106.5% of VDD 6'b000001 - 106.0% of VDD 6'b000010 - 105.5% of VDD 6'b000011 -.." line.long 0xC "CFG0_VDDR_CPU1_GLDTC_CTRL_PROXY," bitfld.long 0xC 31. "VDDR_CPU1_GLDTC_CTRL_PWDB_PROXY,Power down - active low. 0 - Disable all functions 1 - Enable glitch detectors" "0: Disable all functions 1,?" newline bitfld.long 0xC 30. "VDDR_CPU1_GLDTC_CTRL_RSTB_PROXY,Reset - active low. To ensure proper operation rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold.." "0: Reset glitch detector flags 1,?" newline bitfld.long 0xC 16.--18. "VDDR_CPU1_GLDTC_CTRL_LP_FILTER_SEL_PROXY,Selects the glitch detect low-pass filter bandwidth Field values (others are reserved): 3'b000 - 150 kHz 3'b001 - 125 kHz 3'b010 - 100 kHz 3'b011 - 80 kHz 3'b100 - 60 kHz 3'b101 - 45 kHz 3'b110 - 30 kHz 3'b111 -.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--13. 1. "VDDR_CPU1_GLDTC_CTRL_THRESH_HI_SEL_PROXY,Selects the high voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 93.5% of VDD 6'b000001 - 94.0% of VDD 6'b000010 - 94.5% of VDD 6'b000011 - 95.0%.." newline hexmask.long.byte 0xC 0.--5. 1. "VDDR_CPU1_GLDTC_CTRL_THRESH_LO_SEL_PROXY,Selects the low voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 106.5% of VDD 6'b000001 - 106.0% of VDD 6'b000010 - 105.5% of VDD 6'b000011 -.." rgroup.long 0x1A1A0++0x7 line.long 0x0 "CFG0_VDD_CPU_GLDTC_STAT_PROXY," bitfld.long 0x0 8. "VDD_CPU_GLDTC_STAT_THRESH_HI_FLAG_PROXY,High voltage flag. This flag is cleared by clearing the VDD_CPU_GLDTC_CTRL_rstb bit. 0 - No high voltage detected 1 - Voltage above the high voltage threshold was detected." "0: No high voltage detected 1,?" newline bitfld.long 0x0 0. "VDD_CPU_GLDTC_STAT_THRESH_LOW_FLAG_PROXY,Low voltage flag. This flag is cleared by clearing the VDD_CPU_GLDTC_CTRL_rstb bit. 0 - No low voltage detected 1 - Voltage below the low voltage threshold was detected." "0: No low voltage detected 1,?" line.long 0x4 "CFG0_VDD_CPU1_GLDTC_STAT_PROXY," bitfld.long 0x4 8. "VDD_CPU1_GLDTC_STAT_THRESH_HI_FLAG_PROXY,High voltage flag. This flag is cleared by clearing the VDD_CPU1_GLDTC_CTRL_rstb bit. 0 - No high voltage detected 1 - Voltage above the high voltage threshold was detected." "0: No high voltage detected 1,?" newline bitfld.long 0x4 0. "VDD_CPU1_GLDTC_STAT_THRESH_LOW_FLAG_PROXY,Low voltage flag. This flag is cleared by clearing the VDD_CPU1_GLDTC_CTRL_rstb bit. 0 - No low voltage detected 1 - Voltage below the low voltage threshold was detected." "0: No low voltage detected 1,?" rgroup.long 0x1A1B0++0xF line.long 0x0 "CFG0_VDD_CORE_GLDTC_STAT_PROXY," bitfld.long 0x0 8. "VDD_CORE_GLDTC_STAT_THRESH_HI_FLAG_PROXY,High voltage flag. This flag is cleared by clearing the VDD_CORE_GLDTC_CTRL_rstb bit. 0 - No high voltage detected 1 - Voltage above the high voltage threshold was detected." "0: No high voltage detected 1,?" newline bitfld.long 0x0 0. "VDD_CORE_GLDTC_STAT_THRESH_LOW_FLAG_PROXY,Low voltage flag. This flag is cleared by clearing the VDD_CORE_GLDTC_CTRL_rstb bit. 0 - No low voltage detected 1 - Voltage below the low voltage threshold was detected." "0: No low voltage detected 1,?" line.long 0x4 "CFG0_VDDR_CPU_GLDTC_STAT_PROXY," bitfld.long 0x4 8. "VDDR_CPU_GLDTC_STAT_THRESH_HI_FLAG_PROXY,High voltage flag. This flag is cleared by clearing the VDDR_CPU_GLDTC_CTRL_rstb bit. 0 - No high voltage detected 1 - Voltage above the high voltage threshold was detected." "0: No high voltage detected 1,?" newline bitfld.long 0x4 0. "VDDR_CPU_GLDTC_STAT_THRESH_LOW_FLAG_PROXY,Low voltage flag. This flag is cleared by clearing the VDDR_CPU_GLDTC_CTRL_rstb bit. 0 - No low voltage detected 1 - Voltage below the low voltage threshold was detected." "0: No low voltage detected 1,?" line.long 0x8 "CFG0_VDDR_CORE_GLDTC_STAT_PROXY," bitfld.long 0x8 8. "VDDR_CORE_GLDTC_STAT_THRESH_HI_FLAG_PROXY,High voltage flag. This flag is cleared by clearing the VDDR_CORE_GLDTC_CTRL_rstb bit. 0 - No high voltage detected 1 - Voltage above the high voltage threshold was detected." "0: No high voltage detected 1,?" newline bitfld.long 0x8 0. "VDDR_CORE_GLDTC_STAT_THRESH_LOW_FLAG_PROXY,Low voltage flag. This flag is cleared by clearing the VDDR_CORE_GLDTC_CTRL_rstb bit. 0 - No low voltage detected 1 - Voltage below the low voltage threshold was detected." "0: No low voltage detected 1,?" line.long 0xC "CFG0_VDDR_CPU1_GLDTC_STAT_PROXY," bitfld.long 0xC 8. "VDDR_CPU1_GLDTC_STAT_THRESH_HI_FLAG_PROXY,High voltage flag. This flag is cleared by clearing the VDDR_CPU1_GLDTC_CTRL_rstb bit. 0 - No high voltage detected 1 - Voltage above the high voltage threshold was detected." "0: No high voltage detected 1,?" newline bitfld.long 0xC 0. "VDDR_CPU1_GLDTC_STAT_THRESH_LOW_FLAG_PROXY,Low voltage flag. This flag is cleared by clearing the VDDR_CPU1_GLDTC_CTRL_rstb bit. 0 - No low voltage detected 1 - Voltage below the low voltage threshold was detected." "0: No low voltage detected 1,?" rgroup.long 0x1A1C0++0x7 line.long 0x0 "CFG0_VDD_MCU_GLDTC_CTRL_PROXY," bitfld.long 0x0 31. "VDD_MCU_GLDTC_CTRL_PWDB_PROXY,Power down - active low. 0 - Disable all functions 1 - Enable glitch detectors" "0: Disable all functions 1,?" newline bitfld.long 0x0 30. "VDD_MCU_GLDTC_CTRL_RSTB_PROXY,Reset - active low. To ensure proper operation rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold or.." "0: Reset glitch detector flags 1,?" newline bitfld.long 0x0 16.--18. "VDD_MCU_GLDTC_CTRL_LP_FILTER_SEL_PROXY,Selects the glitch detect low-pass filter bandwidth Field values (others are reserved): 3'b000 - 150 kHz 3'b001 - 125 kHz 3'b010 - 100 kHz 3'b011 - 80 kHz 3'b100 - 60 kHz 3'b101 - 45 kHz 3'b110 - 30 kHz 3'b111 - 15.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--13. 1. "VDD_MCU_GLDTC_CTRL_THRESH_HI_SEL_PROXY,Selects the high voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 93.5% of VDD 6'b000001 - 94.0% of VDD 6'b000010 - 94.5% of VDD 6'b000011 - 95.0% of.." newline hexmask.long.byte 0x0 0.--5. 1. "VDD_MCU_GLDTC_CTRL_THRESH_LO_SEL_PROXY,Selects the low voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 106.5% of VDD 6'b000001 - 106.0% of VDD 6'b000010 - 105.5% of VDD 6'b000011 - 105.0%.." line.long 0x4 "CFG0_VDDR_MCU_GLDTC_CTRL_PROXY," bitfld.long 0x4 31. "VDDR_MCU_GLDTC_CTRL_PWDB_PROXY,Power down - active low. 0 - Disable all functions 1 - Enable glitch detectors" "0: Disable all functions 1,?" newline bitfld.long 0x4 30. "VDDR_MCU_GLDTC_CTRL_RSTB_PROXY,Reset - active low. To ensure proper operation rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold.." "0: Reset glitch detector flags 1,?" newline bitfld.long 0x4 16.--18. "VDDR_MCU_GLDTC_CTRL_LP_FILTER_SEL_PROXY,Selects the glitch detect low-pass filter bandwidth Field values (others are reserved): 3'b000 - 150 kHz 3'b001 - 125 kHz 3'b010 - 100 kHz 3'b011 - 80 kHz 3'b100 - 60 kHz 3'b101 - 45 kHz 3'b110 - 30 kHz 3'b111 - 15.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--13. 1. "VDDR_MCU_GLDTC_CTRL_THRESH_HI_SEL_PROXY,Selects the high voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 93.5% of VDD 6'b000001 - 94.0% of VDD 6'b000010 - 94.5% of VDD 6'b000011 - 95.0% of.." newline hexmask.long.byte 0x4 0.--5. 1. "VDDR_MCU_GLDTC_CTRL_THRESH_LO_SEL_PROXY,Selects the low voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 106.5% of VDD 6'b000001 - 106.0% of VDD 6'b000010 - 105.5% of VDD 6'b000011 - 105.0%.." rgroup.long 0x1A1D0++0x7 line.long 0x0 "CFG0_VDD_MCU_GLDTC_STAT_PROXY," bitfld.long 0x0 8. "VDD_MCU_GLDTC_STAT_THRESH_HI_FLAG_PROXY,High voltage flag. This flag is cleared by clearing the VDD_MCU_GLDTC_CTRL_rstb bit. 0 - No high voltage detected 1 - Voltage above the high voltage threshold was detected." "0: No high voltage detected 1,?" newline bitfld.long 0x0 0. "VDD_MCU_GLDTC_STAT_THRESH_LOW_FLAG_PROXY,Low voltage flag. This flag is cleared by clearing the VDD_MCU_GLDTC_CTRL_rstb bit. 0 - No low voltage detected 1 - Voltage below the low voltage threshold was detected." "0: No low voltage detected 1,?" line.long 0x4 "CFG0_VDDR_MCU_GLDTC_STAT_PROXY," bitfld.long 0x4 8. "VDDR_MCU_GLDTC_STAT_THRESH_HI_FLAG_PROXY,High voltage flag. This flag is cleared by clearing the VDDR_MCU_GLDTC_CTRL_rstb bit. 0 - No high voltage detected 1 - Voltage above the high voltage threshold was detected." "0: No high voltage detected 1,?" newline bitfld.long 0x4 0. "VDDR_MCU_GLDTC_STAT_THRESH_LOW_FLAG_PROXY,Low voltage flag. This flag is cleared by clearing the VDDR_MCU_GLDTC_CTRL_rstb bit. 0 - No low voltage detected 1 - Voltage below the low voltage threshold was detected." "0: No low voltage detected 1,?" rgroup.long 0x1A200++0x17 line.long 0x0 "CFG0_PRG_PP_MCU_CTRL_PROXY," bitfld.long 0x0 19. "PRG_PP_MCU_CTRL_POK_PP_EN_PROXY,POK ping-pong enable. When set enables automatic switching between undervoltage and overvoltage detection on VDDSHV_WKUP_GENERAL VDDR_MCU and VMON_CAP_MCU_GENERAL POKs. This bit has no effect if the POK's ov_sel bit =.." "0: No pingpong operation,1: Pingpong operation enabled" newline bitfld.long 0x0 16.--17. "PRG_PP_MCU_CTRL_DEGLITCH_SEL_PROXY,Deglitch period for PRG_PP_MCU POKs Field values (others are reserved): 2'b00 - 5 us 2'b01 - 10 us 2'b10 - 15 us 2'b11 - 20 us" "0,1,2,3" newline bitfld.long 0x0 15. "PRG_PP_MCU_CTRL_POK_EN_SEL_PROXY,Select POK enable source 0 - POK enables come from hardware tie-offs 1 - POK enables come from PRG_PP_MCU_CTRL register" "0: POK enables come from hardware tie-offs 1,?" newline bitfld.long 0x0 10. "PRG_PP_MCU_CTRL_POK_VMON_CAP_MCU_GEN_OV_SEL_PROXY,Force VMON_CAP_MCU_GENERAL POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled. 0 - Undervoltage detection or UV/OV ping-pong operation.." "0: Undervoltage detection or UV/OV ping-pong..,?" newline bitfld.long 0x0 9. "PRG_PP_MCU_CTRL_POK_VDDR_MCU_OV_SEL_PROXY,Force VDDR_MCU POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled. 0 - Undervoltage detection or UV/OV ping-pong operation 1- Overvoltage.." "0: Undervoltage detection or UV/OV ping-pong..,?" newline bitfld.long 0x0 8. "PRG_PP_MCU_CTRL_POK_VDDSHV_WKUP_GEN_OV_SEL_PROXY,Force VDDSHV_WKUP_GENERAL POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled. 0 - Undervoltage detection or UV/OV ping-pong operation.." "0: Undervoltage detection or UV/OV ping-pong..,?" newline bitfld.long 0x0 2. "PRG_PP_MCU_CTRL_POK_VMON_CAP_MCU_GEN_EN_PROXY,Enable VMON_CAP_MCU_GENERAL POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x0 1. "PRG_PP_MCU_CTRL_POK_VDDR_MCU_EN_PROXY,Enable VDDR_MCU POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x0 0. "PRG_PP_MCU_CTRL_POK_VDDSHV_WKUP_GEN_EN_PROXY,Enable VDDSHV_WKUP_GENERAL POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" line.long 0x4 "CFG0_PRG_PP_MCU_STAT_PROXY," bitfld.long 0x4 31. "PRG_PP_MCU_STAT_POK_CLR_PROXY,When set resets pgood sticky bits for VDDSHV_WKUP_GENERAL VDDR_MCU and VMON_CAP_MCU_GENERAL voltage POK detection." "0,1" newline rbitfld.long 0x4 10. "PRG_PP_MCU_STAT_POK_VMON_CAP_MCU_GEN_OV_PROXY,VMON_CAP_MCU_GENERAL overvoltage POK 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0x4 9. "PRG_PP_MCU_STAT_POK_VDDR_MCU_OV_PROXY,VDDR_MCU overvoltage POK 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0x4 8. "PRG_PP_MCU_STAT_POK_VDDSHV_WKUP_GEN_OV_PROXY,VDDSHV_WKUP_GENERAL overvoltage POK 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0x4 2. "PRG_PP_MCU_STAT_POK_VMON_CAP_MCU_GEN_UV_PROXY,VMON_CAP_MCU_GENERAL undervoltage POK 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" newline rbitfld.long 0x4 1. "PRG_PP_MCU_STAT_POK_VDDR_MCU_UV_PROXY,VDDR_MCU undervoltage POK 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" newline rbitfld.long 0x4 0. "PRG_PP_MCU_STAT_POK_VDDSHV_WKUP_GEN_UV_PROXY,VDDSHV_WKUP_GENERAL undervoltage POK 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" line.long 0x8 "CFG0_PRG_PP_POR_CTRL_PROXY," bitfld.long 0x8 16.--17. "PRG_PP_POR_CTRL_DEGLITCH_SEL_PROXY,Deglitch period for PRG_PP_POR POKs Field values (others are reserved): 2'b00 - 5 us 2'b01 - 10 us 2'b10 - 15 us 2'b11 - 20 us" "0,1,2,3" newline bitfld.long 0x8 15. "PRG_PP_POR_CTRL_POK_EN_SEL_PROXY,Select POK enable source 0 - POK enables come from hardware tie-offs 1 - POK enables come from PRG_PP_POR_CTRL register" "0: POK enables come from hardware tie-offs 1,?" newline bitfld.long 0x8 4. "PRG_PP_POR_CTRL_POK_VDDA_PMIC_IN_UV_EN_PROXY,Enable VDDA_PMIC_IN undervoltage POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x8 3. "PRG_PP_POR_CTRL_POK_VDD_MCU_OV_EN_PROXY,Enable VDD_MCU overvoltage POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x8 2. "PRG_PP_POR_CTRL_POK_VDD_MCU_UV_EN_PROXY,Enable VDD_MCU undervoltage POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x8 1. "PRG_PP_POR_CTRL_POK_VDDA_MCU_OV_EN_PROXY,Enable 1.8V VDDA_MCU overvoltage POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x8 0. "PRG_PP_POR_CTRL_POK_VDDA_MCU_UV_EN_PROXY,Enable 1.8V VDDA_MCU undervoltage POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" line.long 0xC "CFG0_PRG_PP_POR_STAT_PROXY," bitfld.long 0xC 31. "PRG_PP_POR_STAT_POK_CLR_PROXY,When set resets pgood sticky bits for VDDA_MCU VDD_MCU and VDDA_PMIC_IN voltage POK detection." "0,1" newline rbitfld.long 0xC 9. "PRG_PP_POR_STAT_POK_VDD_MCU_OV_PROXY,VDD_MCU overvoltage POK detection 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0xC 8. "PRG_PP_POR_STAT_POK_VDDA_MCU_OV_PROXY,1.8V VDDA_MCU overvoltage POK detection 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0xC 2. "PRG_PP_POR_STAT_POK_VDDA_PMIC_IN_UV_PROXY,VDDA_PMIC_IN undervoltage POK detection 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" newline rbitfld.long 0xC 1. "PRG_PP_POR_STAT_POK_VDD_MCU_UV_PROXY,VDD_MCU undervoltage POK detection 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" newline rbitfld.long 0xC 0. "PRG_PP_POR_STAT_POK_VDDA_MCU_UV_PROXY,1.8V VDDA_MCU undervoltage POK detection 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" line.long 0x10 "CFG0_PRG_PP_MAIN_CTRL_PROXY," bitfld.long 0x10 19. "PRG_PP_MAIN_CTRL_POK_PP_EN_PROXY,POK ping-pong enable. When set enables automatic switching between undervoltage and overvoltage detection on VDD_CORE VDD_CPU VDDR_CORE VMON_EXT VMON_EXT_MAIN1P8 and VMON_EXT_MAIN3P3. This bit has no effect if the.." "0: No pingpong operation,1: Pingpong operation enabled" newline bitfld.long 0x10 16.--17. "PRG_PP_MAIN_CTRL_DEGLITCH_SEL_PROXY,Deglitch period for PRG_PP_MAIN POKs Field values (others are reserved): 2'b00 - 5 us 2'b01 - 10 us 2'b10 - 15 us 2'b11 - 20 us" "0,1,2,3" newline bitfld.long 0x10 15. "PRG_PP_MAIN_CTRL_POK_EN_SEL_PROXY,Select POK enable source 0 - POK enables come from hardware tie-offs 1 - POK enables come from PRG_PP_MAIN_CTRL register" "0: POK enables come from hardware tie-offs 1,?" newline bitfld.long 0x10 14. "PRG_PP_MAIN_CTRL_POK_VDD_CPU1_OV_SEL_PROXY,Force VDD_CPU1 POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled. 0 - Undervoltage detection or UV/OV ping-pong operation 1- Overvoltage.." "0: Undervoltage detection or UV/OV ping-pong..,?" newline bitfld.long 0x10 13. "PRG_PP_MAIN_CTRL_POK_VMON_EXT_MAIN3P3_OV_SEL_PROXY,Force VMON_EXT_MAIN 3.3V POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled. 0 - Undervoltage detection or UV/OV ping-pong operation.." "0: Undervoltage detection or UV/OV ping-pong..,?" newline bitfld.long 0x10 12. "PRG_PP_MAIN_CTRL_POK_VMON_EXT_MAIN1P8_OV_SEL_PROXY,Force VMON_EXT_MAIN 1.8V POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled. 0 - Undervoltage detection or UV/OV ping-pong operation.." "0: Undervoltage detection or UV/OV ping-pong..,?" newline bitfld.long 0x10 11. "PRG_PP_MAIN_CTRL_POK_VMON_EXT_OV_SEL_PROXY,Force VMON_EXT POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled. 0 - Undervoltage detection or UV/OV ping-pong operation 1- Overvoltage.." "0: Undervoltage detection or UV/OV ping-pong..,?" newline bitfld.long 0x10 10. "PRG_PP_MAIN_CTRL_POK_VDDR_CORE_OV_SEL_PROXY,Force VDDR_CORE POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled. 0 - Undervoltage detection or UV/OV ping-pong operation 1- Overvoltage.." "0: Undervoltage detection or UV/OV ping-pong..,?" newline bitfld.long 0x10 9. "PRG_PP_MAIN_CTRL_POK_VDD_CPU_OV_SEL_PROXY,Force VDD_CPU POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled. 0 - Undervoltage detection or UV/OV ping-pong operation 1- Overvoltage.." "0: Undervoltage detection or UV/OV ping-pong..,?" newline bitfld.long 0x10 8. "PRG_PP_MAIN_CTRL_POK_VDD_CORE_OV_SEL_PROXY,Force VDD_CORE POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled. 0 - Undervoltage detection or UV/OV ping-pong operation 1- Overvoltage.." "0: Undervoltage detection or UV/OV ping-pong..,?" newline bitfld.long 0x10 6. "PRG_PP_MAIN_CTRL_POK_VDD_CPU1_EN_PROXY,Enable VDD_CPU1 POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x10 5. "PRG_PP_MAIN_CTRL_POK_VMON_EXT_MAIN3P3_EN_PROXY,Enable VMON_EXT_MAIN 3.3V POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x10 4. "PRG_PP_MAIN_CTRL_POK_VMON_EXT_MAIN1P8_EN_PROXY,Enable VMON_EXT_MAIN 1.8V POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x10 3. "PRG_PP_MAIN_CTRL_POK_VMON_EXT_EN_PROXY,Enable VMON_EXT POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x10 2. "PRG_PP_MAIN_CTRL_POK_VDDR_CORE_EN_PROXY,Enable VDDR_CORE POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x10 1. "PRG_PP_MAIN_CTRL_POK_VDD_CPU_EN_PROXY,Enable VDD_CPU POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" newline bitfld.long 0x10 0. "PRG_PP_MAIN_CTRL_POK_VDD_CORE_EN_PROXY,Enable VDD_CORE POK detection 0 - POK detection disabled 1 - POK detection enabled" "0: POK detection disabled 1,?" line.long 0x14 "CFG0_PRG_PP_MAIN_STAT_PROXY," bitfld.long 0x14 31. "PRG_PP_MAIN_STAT_POK_CLR_PROXY,When set resets pgood sticky bits for VDD_CORE VDD_CPU VDDR_CORE VMON_EXT VMON_EXT_MAIN1P8 and VMON_EXT_MAIN3P3 voltage POK detection." "0,1" newline rbitfld.long 0x14 14. "PRG_PP_MAIN_STAT_POK_VDD_CPU1_OV_PROXY,VDD_CPU1 overvoltage POK 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 13. "PRG_PP_MAIN_STAT_POK_VMON_EXT_MAIN3P3_OV_PROXY,VMON_EXT_MAIN 3.3V overvoltage POK 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 12. "PRG_PP_MAIN_STAT_POK_VMON_EXT_MAIN1P8_OV_PROXY,VMON_EXT_MAIN 1.8V overvoltage POK 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 11. "PRG_PP_MAIN_STAT_POK_VMON_EXT_OV_PROXY,VMON_EXT overvoltage POK 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 10. "PRG_PP_MAIN_STAT_POK_VDDR_CORE_OV_PROXY,VDDR_CORE overvoltage POK 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 9. "PRG_PP_MAIN_STAT_POK_VDD_CPU_OV_PROXY,VDD_CPU overvoltage POK 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 8. "PRG_PP_MAIN_STAT_POK_VDD_CORE_OV_PROXY,VDD_CORE overvoltage POK 0 - Voltage good 1 - Voltage above threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 6. "PRG_PP_MAIN_STAT_POK_VDD_CPU1_UV_PROXY,VDD_CPU1 undervoltage POK 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 5. "PRG_PP_MAIN_STAT_POK_VMON_EXT_MAIN3P3_UV_PROXY,VMON_EXT_MAIN 3.3V undervoltage POK 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 4. "PRG_PP_MAIN_STAT_POK_VMON_EXT_MAIN1P8_UV_PROXY,VMON_EXT_MAIN 1.8V undervoltage POK 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 3. "PRG_PP_MAIN_STAT_POK_VMON_EXT_UV_PROXY,VMON_EXT undervoltage POK 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 2. "PRG_PP_MAIN_STAT_POK_VDDR_CORE_UV_PROXY,VDDR_CORE undervoltage POK 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 1. "PRG_PP_MAIN_STAT_POK_VDD_CPU_UV_PROXY,VDD_CPU undervoltage POK 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" newline rbitfld.long 0x14 0. "PRG_PP_MAIN_STAT_POK_VDD_CORE_UV_PROXY,VDD_CORE undervoltage POK 0 - Voltage good 1 - Voltage below threshold" "0: Voltage good 1,?" rgroup.long 0x1A280++0x17 line.long 0x0 "CFG0_WKUP_CLKGATE_CTRL_PROXY," hexmask.long 0x0 6.--31. 1. "WKUP_CLKGATE_CTRL_WKUP_NOGATE_RSVD_PROXY,WKUP reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power savings 1 -.." newline bitfld.long 0x0 5. "WKUP_CLKGATE_CTRL_WKUP_SA2SS_NOGATE_PROXY,WKUP SA2SS clock gate disable 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x0 4. "WKUP_CLKGATE_CTRL_WKUP_SMS_NOGATE_PROXY,WKUP SMS clock gate disable 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x0 2. "WKUP_CLKGATE_CTRL_WKUP_ECC_AGG_NOGATE_PROXY,WKUP ECC Aggregator clock gate disable 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x0 1. "WKUP_CLKGATE_CTRL_WKUP_FW_CBA_NOGATE_PROXY,WKUP domain Firewall bus (wkup_fw_cbass) clock gate disable 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x0 0. "WKUP_CLKGATE_CTRL_WKUP_CBA_NOGATE_PROXY,WKUP domain Data bus (wkup_cbass) clock gate disable 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" line.long 0x4 "CFG0_MCU_CLKGATE_CTRL_PROXY," hexmask.long.word 0x4 21.--31. 1. "MCU_CLKGATE_CTRL_MCU_PER_NOGATE_RSVD_PROXY,MCU reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power savings 1 -.." newline bitfld.long 0x4 20. "MCU_CLKGATE_CTRL_MCU_PDMA_G2_PROXY,MCU domain MCAN1/USART0 PDMA clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x4 19. "MCU_CLKGATE_CTRL_MCU_PDMA_G0_PROXY,MCU domain MCAN0/SPI0 PDMA clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x4 18. "MCU_CLKGATE_CTRL_MCU_PULSAR_NOGATE_PROXY,MCU domain Pulsar clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x4 17. "MCU_CLKGATE_CTRL_MCU_NAV_UDMASS_NOGATE_PROXY,MCU NavSS UDMA interface clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x4 16. "MCU_CLKGATE_CTRL_MCU_NAV_MODSS_NOGATE_PROXY,MCU NavSS MODSS interface clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline hexmask.long.word 0x4 4.--15. 1. "MCU_CLKGATE_CTRL_MCU_CBA_NOGATE_RSVD_PROXY,MCU reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power savings 1 -.." newline bitfld.long 0x4 3. "MCU_CLKGATE_CTRL_MCU_DBG_CBA_NOGATE_PROXY,MCU domain Debug bus (mcu_dbg_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x4 2. "MCU_CLKGATE_CTRL_MCU_ECC_AGG_NOGATE_PROXY,MCU ECC Aggregator clock gate disable 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x4 1. "MCU_CLKGATE_CTRL_MCU_FW_CBA_NOGATE_PROXY,MCU domain Firewall bus (mcu_fw_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x4 0. "MCU_CLKGATE_CTRL_MCU_CBA_NOGATE_PROXY,MCU domain Data bus (mcu_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" line.long 0x8 "CFG0_MAIN_CLKGATE_CTRL0_PROXY," bitfld.long 0x8 29.--31. "MAIN_CLKGATE_CTRL0_MAIN_CBA2_NOGATE_RSVD_PROXY,MAIN CBA reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power.." "0: Clocks are gated on idle for power savings 1,?,?,?,?,?,?,?" newline bitfld.long 0x8 28. "MAIN_CLKGATE_CTRL0_MAIN_DEBUG_BOLTON_CBA_PROXY,MAIN domain debug bolton bus (debug_bolton_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 27. "MAIN_CLKGATE_CTRL0_MAIN_AC_CFG_NOGATE_PROXY,MAIN domain AC Configuration bus (ac_cfg_fw_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 26. "MAIN_CLKGATE_CTRL0_MAIN_AC_ECC_AGG_NOGATE_PROXY,MAIN domain AC ECC aggregator bus (ac_pipe_ecc_aggr) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 25. "MAIN_CLKGATE_CTRL0_MAIN_AC_CBA_NOGATE_PROXY,MAIN domain AC Firewall bus (ac_pipe_cbass_main_fw_cbass_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 24. "MAIN_CLKGATE_CTRL0_MAIN_CBA1_NOGATE_RSVD_PROXY,MAIN CBA reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power.." "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 23. "MAIN_CLKGATE_CTRL0_MAIN_HC_CFG_CBA_NOGATE_PROXY,MAIN domain HC Configuration bus (hc_cfg_cbass_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 22. "MAIN_CLKGATE_CTRL0_MAIN_HC_ECC_AGG_NOGATE_PROXY,MAIN domain HC ECC aggregator (nogate) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 21. "MAIN_CLKGATE_CTRL0_MAIN_HC_FW_CBA_NOGATE_PROXY,MAIN domain HC Firewall bus (main_hc2_fw_cbass_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 20. "MAIN_CLKGATE_CTRL0_MAIN_HC_CBA_NOGATE_PROXY,MAIN domain HC Data bus (hc2_cbass_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 19. "MAIN_CLKGATE_CTRL0_MAIN_DBG_DATA_CBA_NOGATE_PROXY,MAIN domain Debug Data bus (debug_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 18. "MAIN_CLKGATE_CTRL0_MAIN_DBG_CBA_NOGATE_PROXY,MAIN domain Debug bus (debug_cbass_wrap_main_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 17. "MAIN_CLKGATE_CTRL0_MAIN_IP_CSI_CBA_NOGATE_PROXY,MAIN domain CSI bus (csi_cbass_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 16. "MAIN_CLKGATE_CTRL0_MAIN_IP_NS_CBA_NOGATE_RSVD_PROXY,MAIN nonsafety CBA reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle.." "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 15. "MAIN_CLKGATE_CTRL0_MAIN_IP_NONSAFE_CBA_NOGATE_PROXY,MAIN domain Interface Peripheral nonsafety IP bus (ipphy_cbass_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 14. "MAIN_CLKGATE_CTRL0_MAIN_IP_ECC_AGG_NOGATE_PROXY,MAIN domain Interface Peripheral ECC aggregator (main_spi0_g0_main_0_ecc_aggr_main_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving.." "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 13. "MAIN_CLKGATE_CTRL0_MAIN_IP_FW_CBA_NOGATE_PROXY,MAIN domain Interface Peripheral Firewall bus (ipphy_cbass_main_fw_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 12. "MAIN_CLKGATE_CTRL0_MAIN_IP_CBA_NOGATE_PROXY,MAIN domain Interface Peripheral bus (ipphy_safe_cbass_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 11. "MAIN_CLKGATE_CTRL0_MAIN_RC_CFG_CBA_NOGATE_PROXY,MAIN domain RC Configuration bus (rc_cfg_cbass_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 10. "MAIN_CLKGATE_CTRL0_MAIN_RC_ECC_AGG_NOGATE_PROXY,MAIN domain RC ECC aggregator (main_rc_ecc_aggr_main_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 9. "MAIN_CLKGATE_CTRL0_MAIN_RC_FW_CBA_NOGATE_PROXY,MAIN domain RC Firewall bus (rc_cbass_main_fw_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 8. "MAIN_CLKGATE_CTRL0_MAIN_RC_CBA_NOGATE_PROXY,MAIN domain RC Data bus (rc_cbass_0) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 7. "MAIN_CLKGATE_CTRL0_MAIN_PULSAR1_MEM_NOGATE_PROXY,MAIN domain Pulsar 1 memory bus (pulsar1_mem_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 6. "MAIN_CLKGATE_CTRL0_MAIN_PULSAR1_SWITCH_CBA_NOGATE_PROXY,MAIN domain Pulsar 1 peripheral switch bus (pulsar1_periph_switch_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving.." "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 5. "MAIN_CLKGATE_CTRL0_MAIN_PULSAR0_MEM_NOGATE_PROXY,MAIN domain Pulsar 0 memory bus (pulsar0_mem_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 4. "MAIN_CLKGATE_CTRL0_MAIN_PULSAR0_SLV_NOGATE_PROXY,MAIN domain Pulsar slave bus (pulsar0_slv_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 3. "MAIN_CLKGATE_CTRL0_MAIN_INFRA_NONSAFE_CBA_NOGATE_PROXY,MAIN domain Infrastructure non-safety IP bus (main_infra_non_safe_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 2. "MAIN_CLKGATE_CTRL0_MAIN_INFRA_ECC_AGG_NOGATE_PROXY,MAIN domain Infrastructure ECC aggregator (main_infra_ecc_aggr) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 1. "MAIN_CLKGATE_CTRL0_MAIN_INFRA_FW_CBA_NOGATE_PROXY,MAIN domain Infrastructure Firewall bus (main_infra_fw_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x8 0. "MAIN_CLKGATE_CTRL0_MAIN_INFRA_CBA_NOGATE_PROXY,MAIN domain Infrastructure bus (main_infra_cbass) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" line.long 0xC "CFG0_MAIN_CLKGATE_CTRL1_PROXY," hexmask.long.byte 0xC 24.--31. 1. "MAIN_CLKGATE_CTRL1_MAIN_CG1_NOGATE_RSVD_PROXY,MAIN PDMA clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power savings 1 -.." newline bitfld.long 0xC 23. "MAIN_CLKGATE_CTRL1_MAIN_PDMA_DEBUG_G1_NOGATE_PROXY,MAIN domain PDMA Debug_G1 clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 22. "MAIN_CLKGATE_CTRL1_MAIN_PDMA_DEBUG_G0_NOGATE_PROXY,MAIN domain PDMA Debug_G0 clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 21. "MAIN_CLKGATE_CTRL1_MAIN_PDMA_MCASP_NOGATE_PROXY,MAIN domain PDMA MCASP clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 20. "MAIN_CLKGATE_CTRL1_MAIN_PDMA_MCAN_NOGATE_PROXY,MAIN domain PDMA MCAN clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 19. "MAIN_CLKGATE_CTRL1_MAIN_PDMA_USART_PSILSS_NOGATE_PROXY,MAIN domain PDMA USART PSILSS clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 18. "MAIN_CLKGATE_CTRL1_MAIN_PDMA_SPI_G1_NOGATE_PROXY,MAIN domain PDMA SPI_G1 clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 17. "MAIN_CLKGATE_CTRL1_MAIN_PDMA_SPI_G0_NOGATE_PROXY,MAIN domain PDMA SPI_G0 clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 16. "MAIN_CLKGATE_CTRL1_MAIN_PDMA_SPI_PSILSS_NOGATE_PROXY,MAIN domain PDMA SPI PSILSS clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 14.--15. "MAIN_CLKGATE_CTRL1_MAIN_IP2_NOGATE_RSVD_PROXY,MAIN IP reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power savings.." "0: Clocks are gated on idle for power savings 1,?,?,?" newline bitfld.long 0xC 13. "MAIN_CLKGATE_CTRL1_MAIN_VPAC1_NOGATE_PROXY,MAIN domain VPAC 1 clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 12. "MAIN_CLKGATE_CTRL1_MAIN_VPAC0_NOGATE_PROXY,MAIN domain VPAC 0 clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 11. "MAIN_CLKGATE_CTRL1_MAIN_IP1_NOGATE_RSVD_PROXY,MAIN IP reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power savings.." "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 10. "MAIN_CLKGATE_CTRL1_MAIN_PULSAR2_NOGATE_PROXY,MAIN domain Pulsar 2 clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 9. "MAIN_CLKGATE_CTRL1_MAIN_PULSAR1_NOGATE_PROXY,MAIN domain Pulsar 1 clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 8. "MAIN_CLKGATE_CTRL1_MAIN_PULSAR0_NOGATE_PROXY,MAIN domain Pulsar 0 clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 5.--7. "MAIN_CLKGATE_CTRL1_MAIN_IP0_NOGATE_RSVD_PROXY,MAIN IP reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power savings.." "0: Clocks are gated on idle for power savings 1,?,?,?,?,?,?,?" newline bitfld.long 0xC 4. "MAIN_CLKGATE_CTRL1_MAIN_NAV_MV_FW_NOGATE_PROXY,MAIN NavSS Mod/Virt Firewall interface clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 3. "MAIN_CLKGATE_CTRL1_MAIN_NAV_VIRTSS_NOGATE_PROXY,MAIN NavSS VIRTSS interface clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 2. "MAIN_CLKGATE_CTRL1_MAIN_NAV_NBSS_NOGATE_PROXY,MAIN NavSS NB interface clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 1. "MAIN_CLKGATE_CTRL1_MAIN_NAV_UDMASS_NOGATE_PROXY,Main NavSS UDMA interface clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0xC 0. "MAIN_CLKGATE_CTRL1_MAIN_NAV_MODSS_NOGATE_PROXY,MAIN NavSS MODSS interface clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" line.long 0x10 "CFG0_MAIN_CLKGATE_CTRL2_PROXY," hexmask.long.byte 0x10 26.--31. 1. "MAIN_CLKGATE_CTRL2_MAIN_CG2_2_NOGATE_RSVD_PROXY,MAIN domain spare clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power.." newline bitfld.long 0x10 25. "MAIN_CLKGATE_CTRL2_MAIN_CSITX1_NOGATE_PROXY,MAIN domain CSI_TX1 clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x10 24. "MAIN_CLKGATE_CTRL2_MAIN_CSITX0_NOGATE_PROXY,MAIN domain CSI_TX0 clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline hexmask.long.byte 0x10 19.--23. 1. "MAIN_CLKGATE_CTRL2_MAIN_CG2_1_NOGATE_RSVD_PROXY,MAIN domain spare clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power.." newline bitfld.long 0x10 18. "MAIN_CLKGATE_CTRL2_MAIN_SA2_CPSW_PSILSS_NOGATE_PROXY,MAIN domain SA2_UL/SPCW PSILSS clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x10 17. "MAIN_CLKGATE_CTRL2_MAIN_DMPAC_VPAC_PSILSS_NOGATE_PROXY,MAIN domain DMPAC/VPAC PSILSS clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x10 16. "MAIN_CLKGATE_CTRL2_MAIN_CSI_PSILSS_NOGATE_PROXY,MAIN domain CSI PSILSS clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving disabled" "0: Clocks are gated on idle for power savings 1,?" newline hexmask.long.word 0x10 3.--15. 1. "MAIN_CLKGATE_CTRL2_MAIN_CG2_0_NOGATE_RSVD_PROXY,MAIN domain spare clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power.." newline bitfld.long 0x10 2. "MAIN_CLKGATE_CTRL2_MAIN_AC_ECC_AGG_STOG_NOGATE_PROXY,MAIN domain ac ECC aggregator Slave Timeout Gasket (main_ac_ecc_aggr_stog) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving.." "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x10 1. "MAIN_CLKGATE_CTRL2_MAIN_GPU_SLV_STOG_M2P_NOGATE_PROXY,MAIN domain GPU Slave Timeout Gasket output (main_gpu_slv_stog_m2p_pwr_dis) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving.." "0: Clocks are gated on idle for power savings 1,?" newline bitfld.long 0x10 0. "MAIN_CLKGATE_CTRL2_MAIN_GPU_SLV_STOG_P2M_NOGATE_PROXY,MAIN domain GPU Slave Timeout Gasket input (main_gpu_slv_stog_p2m_pwr_dis) clock gate disable. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving.." "0: Clocks are gated on idle for power savings 1,?" line.long 0x14 "CFG0_MAIN_CLKGATE_CTRL3_PROXY," hexmask.long 0x14 0.--31. 1. "MAIN_CLKGATE_CTRL3_MAIN_CG3_NOGATE_RSVD_PROXY,MAIN domain spare clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices. 0 - Clocks are gated on idle for power.." rgroup.long 0x1A300++0x3 line.long 0x0 "CFG0_HYPERNET_WAKE_CTRL_PROXY," hexmask.long 0x0 1.--31. 1. "HYPERNET_WAKE_CTRL_MW_PROXY,HYPERNET IO magic word. This 31-bit value that enables placing of the HYPERNET I/Os into isolation for daisy-chain wakeup operation. 0x5555 - Magic word value to enable isolation when qualified with mw_load bit Others -.." newline bitfld.long 0x0 0. "HYPERNET_WAKE_CTRL_MW_LOAD_EN_PROXY,Magic word load enable Setting this bit to 1 loads and locks the mw field for HYPERNET IO isolation. If the mw field matches the magic word value then the value is latched into the HYPERNET IO voltage domain and.." "0: Unlock and do not load mw value for comparison 1,?" rgroup.long 0x1A308++0x7 line.long 0x0 "CFG0_HYPERNET_WAKE_STAT0_PROXY," hexmask.long 0x0 1.--31. 1. "HYPERNET_WAKE_STAT0_MW_STAT_PROXY,HYPERNET magic word status Indicates the latched value of the mw field." newline bitfld.long 0x0 0. "HYPERNET_WAKE_STAT0_MW_LOAD_STAT_PROXY,Magic word load status. Indicates the latched value of the mw_load_en bit" "0,1" line.long 0x4 "CFG0_HYPERNET_WAKE_STAT1_PROXY," bitfld.long 0x4 0. "HYPERNET_WAKE_STAT1_HYPERNET_IO_MODE_PROXY,Indicates if HYPERNET IO wakeup mode is enabled. 0 - Not enabled (load_en not set or mw doesn't match magic word) 1 - HYPERNET IO mode enabled" "0: Not enabled,1: HYPERNET IO mode enabled" rgroup.long 0x1A310++0x3 line.long 0x0 "CFG0_MCU_GEN_WAKE_CTRL_PROXY," hexmask.long 0x0 1.--31. 1. "MCU_GEN_WAKE_CTRL_MW_PROXY,MCU_GENERAL IO magic word. This 31-bit value that enables placing of the MCU_GENERAL I/Os into isolation for daisy-chain wakeup operation. 0x5555 - Magic word value to enable isolation when qualified with mw_load bit.." newline bitfld.long 0x0 0. "MCU_GEN_WAKE_CTRL_MW_LOAD_EN_PROXY,Magic word load enable Setting this bit to 1 loads and locks the mw field for MCU_GENERAL IO isolation. If the mw field matches the magic word value then the value is latched into the MCU_GENERAL IO voltage domain and.." "0: Unlock and do not load mw value for comparison 1,?" rgroup.long 0x1A318++0x7 line.long 0x0 "CFG0_MCU_GEN_WAKE_STAT0_PROXY," hexmask.long 0x0 1.--31. 1. "MCU_GEN_WAKE_STAT0_MW_STAT_PROXY,MCU_GENERAL magic word status Indicates the latched value of the mw field." newline bitfld.long 0x0 0. "MCU_GEN_WAKE_STAT0_MW_LOAD_STAT_PROXY,Magic word load status. Indicates the latched value of the mw_load_en bit" "0,1" line.long 0x4 "CFG0_MCU_GEN_WAKE_STAT1_PROXY," bitfld.long 0x4 0. "MCU_GEN_WAKE_STAT1_MCU_GEN_IO_MODE_PROXY,Indicates if MCU_GENERAL IO wakeup mode is enabled. 0 - Not enabled (load_en not set or mw doesn't match magic word) 1 - MCU_GENERAL IO mode enabled" "0: Not enabled,1: MCU_GENERAL IO mode enabled" rgroup.long 0x1A380++0x7 line.long 0x0 "CFG0_POK_ISO_EVENT_SEL_PROXY," hexmask.long 0x0 2.--31. 1. "POK_ISO_EVENT_SEL_POK_RSVD_PROXY,Reserved for future use (do not optimize out)" newline bitfld.long 0x0 1. "POK_ISO_EVENT_SEL_POK_VDD_CORE_OV_PROXY,VDD_CORE overvoltage detection triggers enabled isolation actions" "0,1" newline bitfld.long 0x0 0. "POK_ISO_EVENT_SEL_POK_VDD_CORE_UV_PROXY,VDD_CORE undervoltage detection triggers enabled isolation actions" "0,1" line.long 0x4 "CFG0_POK_ISO_ACTION_EN_PROXY," hexmask.long.word 0x4 21.--31. 1. "POK_ISO_ACTION_EN_RSVD_TOG_FLUSH_PROXY,Reserved timeout gasket flush enable bits. Do not optimize out 0 - Enabled POK events have no effect on this gasket 1 - Enabled POK events will assert the flush for this gasket" newline bitfld.long 0x4 20. "POK_ISO_ACTION_EN_WKUP2MAIN_INFRA_STOG_FLUSH_PROXY,WKUP to Main INFRA slave timeout gasket flush enable: 0 - Enabled POK events have no effect on this gasket 1 - Enabled POK events will assert the flush for this gasket" "0: Enabled POK events have no effect on this gasket..,?" newline bitfld.long 0x4 19. "POK_ISO_ACTION_EN_MCU2MAIN_INFRA_STOG_FLUSH_PROXY,MCU to Main INFRA slave timeout gasket flush enable: 0 - Enabled POK events have no effect on this gasket 1 - Enabled POK events will assert the flush for this gasket" "0: Enabled POK events have no effect on this gasket..,?" newline bitfld.long 0x4 18. "POK_ISO_ACTION_EN_MCU2MAIN_RC_STOG_FLUSH_PROXY,MCU to Main RC slave timeout gasket flush enable: 0 - Enabled POK events have no effect on this gasket 1 - Enabled POK events will assert the flush for this gasket" "0: Enabled POK events have no effect on this gasket..,?" newline bitfld.long 0x4 17. "POK_ISO_ACTION_EN_MCU2MAIN_FW_STOG_FLUSH_PROXY,MCU to Main FW slave timeout gasket flush enable: 0 - Enabled POK events have no effect on this gasket 1 - Enabled POK events will assert the flush for this gasket" "0: Enabled POK events have no effect on this gasket..,?" newline bitfld.long 0x4 16. "POK_ISO_ACTION_EN_MAIN2MCU_MTOG_FLUSH_PROXY,MAIN to MCU master timeout gasket flush enable: 0 - Enabled POK events have no effect on this gasket 1 - Enabled POK events will assert the flush for this gasket" "0: Enabled POK events have no effect on this gasket..,?" newline hexmask.long.byte 0x4 9.--15. 1. "POK_ISO_ACTION_EN_RSVD_ACT_B_PROXY,Reserved isolation action enable bits. Do not optimize out" newline bitfld.long 0x4 8. "POK_ISO_ACTION_EN_ISOLATE_PROXY,If enabled the isolate signal will be asserted after all enabled flush signals have been asserted for 4 of their respective time-out gasket clocks when any selected POK event occurs. 0 - Isolation is not asserted on.." "0: Isolation is not asserted on selected POK event 1,?" newline hexmask.long.byte 0x4 4.--7. 1. "POK_ISO_ACTION_EN_RSVD_ACT_A_PROXY,Reserved isolation action enable bits. Do not optimize out" newline hexmask.long.byte 0x4 0.--3. 1. "POK_ISO_ACTION_EN_MAIN_POR_PROXY,When set to 4'b0110 MAIN_PORz reset is asserted when any selected POK event occurs. (Reserved for future use do not optimize out)" rgroup.long 0x1A388++0x3 line.long 0x0 "CFG0_POK_ISO_ACTION_STAT_PROXY," hexmask.long 0x0 3.--31. 1. "POK_ISO_ACTION_STAT_RSVD_STAT_PROXY,Reserved POK action status - do not optimize out" newline bitfld.long 0x0 2. "POK_ISO_ACTION_STAT_FLUSH_PROXY,POK activated timeout gasket flush status This signal will remain asserted until a 1 is written to the POK_ISO_ACTION_CLR_flush bit. 0 - No gasket flush is being asserted by enabled POK event 1 - Enabled gasket flush.." "0: No gasket flush is being asserted by enabled POK..,?" newline bitfld.long 0x0 1. "POK_ISO_ACTION_STAT_ISOLATE_PROXY,POK activated Isolate status This signal will remain asserted until a 1 is written to the POK_ISO_ACTION_CLR_isolate bit. 0 - No isolate is being asserted by enabled POK event 1 - Isolate signal is being asserted due.." "0: No isolate is being asserted by enabled POK..,?" newline bitfld.long 0x0 0. "POK_ISO_ACTION_STAT_MAIN_POR_PROXY,Reserved POK activated MAIN_PORz status - do not optimize out 0 - No MAIN_PORz is being asserted by enabled POK event 1 - MAIN_PORz is being asserted due to an enabled POK event" "0: No MAIN_PORz is being asserted by enabled POK..,?" rgroup.long 0x1A38C++0x7 line.long 0x0 "CFG0_POK_ISO_ACTION_CLR_PROXY," hexmask.long 0x0 3.--31. 1. "POK_ISO_ACTION_CLR_RSVD_CLR_PROXY,Reserved POK activated signal clear - do not optimize out Always read as 0. Writing 1 deasserts POK activated signal. 0 - Writing 0 has no effect. Bit always reads as 0 1 - Deassert signal. Bit will clear to 0.." newline bitfld.long 0x0 2. "POK_ISO_ACTION_CLR_FLUSH_PROXY,POK activated timeout gasket flush clear Always read as 0. Writing 1 deasserts POK activated timeot gasket flush signals. 0 - Writing 0 has no effect. Bit always reads as 0 1 - Deassert gasket flush signals. Bit will.." "0: Writing 0 has no effect,1: Deassert gasket flush signals" newline bitfld.long 0x0 1. "POK_ISO_ACTION_CLR_ISOLATE_PROXY,POK activated isolate clear Always read as 0. Writing 1 deasserts POK activated isolate signal. 0 - Writing 0 has no effect. Bit always reads as 0 1 - Deassert isolate signal. Bit will clear to 0 after write." "0: Writing 0 has no effect,1: Deassert isolate signal" newline bitfld.long 0x0 0. "POK_ISO_ACTION_CLR_MAIN_POR_PROXY,Reserved POK activated MAIN_PORz clear - do not optimize out Always read as 0. Writing 1 deasserts POK activated MAIN_PORz signal. 0 - Writing 0 has no effect. Bit always reads as 0 1 - Deassert MAIN_PORz. Bit will.." "0: Writing 0 has no effect,1: Deassert MAIN_PORz" line.long 0x4 "CFG0_POK_ISO_GP_CTRL_PROXY," hexmask.long 0x4 0.--31. 1. "POK_ISO_GP_CTRL_RSVD_CTRL_PROXY,Reserved POK isolation control bits" rgroup.long 0x1A394++0x3 line.long 0x0 "CFG0_POK_ISO_GP_STAT_PROXY," hexmask.long 0x0 0.--31. 1. "POK_ISO_GP_STAT_RSVD_STAT_PROXY,Reserved POK isolation status bits" rgroup.long 0x1B008++0x7 line.long 0x0 "CFG0_LOCK6_KICK0_PROXY," hexmask.long 0x0 0.--31. 1. "LOCK6_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK6_KICK1_PROXY," hexmask.long 0x4 0.--31. 1. "LOCK6_KICK1_PROXY,- KICK1 component" rgroup.long 0x1B100++0x1F line.long 0x0 "CFG0_CLAIMREG_P6_R0," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P6_R0,Claim bits for Partition 6" line.long 0x4 "CFG0_CLAIMREG_P6_R1," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P6_R1,Claim bits for Partition 6" line.long 0x8 "CFG0_CLAIMREG_P6_R2," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P6_R2,Claim bits for Partition 6" line.long 0xC "CFG0_CLAIMREG_P6_R3," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P6_R3,Claim bits for Partition 6" line.long 0x10 "CFG0_CLAIMREG_P6_R4," hexmask.long 0x10 0.--31. 1. "CLAIMREG_P6_R4,Claim bits for Partition 6" line.long 0x14 "CFG0_CLAIMREG_P6_R5," hexmask.long 0x14 0.--31. 1. "CLAIMREG_P6_R5,Claim bits for Partition 6" line.long 0x18 "CFG0_CLAIMREG_P6_R6," hexmask.long 0x18 0.--31. 1. "CLAIMREG_P6_R6,Claim bits for Partition 6" line.long 0x1C "CFG0_CLAIMREG_P6_R7," hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P6_R7,Claim bits for Partition 6" rgroup.long 0x1C000++0x33 line.long 0x0 "CFG0_PADCONFIG0," bitfld.long 0x0 31. "PADCONFIG0_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x0 30. "PADCONFIG0_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x0 29. "PADCONFIG0_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x0 28. "PADCONFIG0_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x0 27. "PADCONFIG0_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x0 26. "PADCONFIG0_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x0 25. "PADCONFIG0_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x0 24. "PADCONFIG0_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x0 23. "PADCONFIG0_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x0 22. "PADCONFIG0_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x0 21. "PADCONFIG0_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x0 19.--20. "PADCONFIG0_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x0 18. "PADCONFIG0_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x0 17. "PADCONFIG0_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x0 16. "PADCONFIG0_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x0 15. "PADCONFIG0_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x0 14. "PADCONFIG0_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x0 11.--13. "PADCONFIG0_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "PADCONFIG0_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x0 7. "PADCONFIG0_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x0 4.--5. "PADCONFIG0_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "PADCONFIG0_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b - Mux.." line.long 0x4 "CFG0_PADCONFIG1," bitfld.long 0x4 31. "PADCONFIG1_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x4 30. "PADCONFIG1_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x4 29. "PADCONFIG1_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x4 28. "PADCONFIG1_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x4 27. "PADCONFIG1_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x4 26. "PADCONFIG1_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x4 25. "PADCONFIG1_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x4 24. "PADCONFIG1_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x4 23. "PADCONFIG1_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x4 22. "PADCONFIG1_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x4 21. "PADCONFIG1_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x4 19.--20. "PADCONFIG1_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4 18. "PADCONFIG1_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x4 17. "PADCONFIG1_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x4 16. "PADCONFIG1_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x4 15. "PADCONFIG1_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x4 14. "PADCONFIG1_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x4 11.--13. "PADCONFIG1_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8. "PADCONFIG1_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x4 7. "PADCONFIG1_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x4 4.--5. "PADCONFIG1_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "PADCONFIG1_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b - Mux.." line.long 0x8 "CFG0_PADCONFIG2," bitfld.long 0x8 31. "PADCONFIG2_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x8 30. "PADCONFIG2_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x8 29. "PADCONFIG2_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x8 28. "PADCONFIG2_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x8 27. "PADCONFIG2_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x8 26. "PADCONFIG2_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x8 25. "PADCONFIG2_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x8 24. "PADCONFIG2_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x8 23. "PADCONFIG2_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x8 22. "PADCONFIG2_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x8 21. "PADCONFIG2_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x8 19.--20. "PADCONFIG2_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8 18. "PADCONFIG2_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x8 17. "PADCONFIG2_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x8 16. "PADCONFIG2_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x8 15. "PADCONFIG2_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x8 14. "PADCONFIG2_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x8 11.--13. "PADCONFIG2_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "PADCONFIG2_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x8 7. "PADCONFIG2_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x8 4.--5. "PADCONFIG2_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x8 0.--3. 1. "PADCONFIG2_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b - Mux.." line.long 0xC "CFG0_PADCONFIG3," bitfld.long 0xC 31. "PADCONFIG3_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xC 30. "PADCONFIG3_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xC 29. "PADCONFIG3_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xC 28. "PADCONFIG3_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xC 27. "PADCONFIG3_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xC 26. "PADCONFIG3_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xC 25. "PADCONFIG3_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xC 24. "PADCONFIG3_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xC 23. "PADCONFIG3_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC 22. "PADCONFIG3_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC 21. "PADCONFIG3_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xC 19.--20. "PADCONFIG3_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC 18. "PADCONFIG3_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xC 17. "PADCONFIG3_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xC 16. "PADCONFIG3_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xC 15. "PADCONFIG3_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xC 14. "PADCONFIG3_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xC 11.--13. "PADCONFIG3_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "PADCONFIG3_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xC 7. "PADCONFIG3_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xC 4.--5. "PADCONFIG3_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xC 0.--3. 1. "PADCONFIG3_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b - Mux.." line.long 0x10 "CFG0_PADCONFIG4," bitfld.long 0x10 31. "PADCONFIG4_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x10 30. "PADCONFIG4_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x10 29. "PADCONFIG4_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x10 28. "PADCONFIG4_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x10 27. "PADCONFIG4_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x10 26. "PADCONFIG4_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x10 25. "PADCONFIG4_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x10 24. "PADCONFIG4_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x10 23. "PADCONFIG4_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x10 22. "PADCONFIG4_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x10 21. "PADCONFIG4_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x10 19.--20. "PADCONFIG4_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x10 18. "PADCONFIG4_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x10 17. "PADCONFIG4_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x10 16. "PADCONFIG4_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x10 15. "PADCONFIG4_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x10 14. "PADCONFIG4_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x10 11.--13. "PADCONFIG4_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "PADCONFIG4_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x10 7. "PADCONFIG4_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x10 4.--5. "PADCONFIG4_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x10 0.--3. 1. "PADCONFIG4_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b - Mux.." line.long 0x14 "CFG0_PADCONFIG5," bitfld.long 0x14 31. "PADCONFIG5_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x14 30. "PADCONFIG5_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x14 29. "PADCONFIG5_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x14 28. "PADCONFIG5_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x14 27. "PADCONFIG5_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x14 26. "PADCONFIG5_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x14 25. "PADCONFIG5_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x14 24. "PADCONFIG5_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x14 23. "PADCONFIG5_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x14 22. "PADCONFIG5_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x14 21. "PADCONFIG5_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x14 19.--20. "PADCONFIG5_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x14 18. "PADCONFIG5_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x14 17. "PADCONFIG5_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x14 16. "PADCONFIG5_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x14 15. "PADCONFIG5_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x14 14. "PADCONFIG5_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x14 11.--13. "PADCONFIG5_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "PADCONFIG5_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x14 7. "PADCONFIG5_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x14 4.--5. "PADCONFIG5_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x14 0.--3. 1. "PADCONFIG5_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b - Mux.." line.long 0x18 "CFG0_PADCONFIG6," bitfld.long 0x18 31. "PADCONFIG6_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x18 30. "PADCONFIG6_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x18 29. "PADCONFIG6_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x18 28. "PADCONFIG6_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x18 27. "PADCONFIG6_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x18 26. "PADCONFIG6_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x18 25. "PADCONFIG6_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x18 24. "PADCONFIG6_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x18 23. "PADCONFIG6_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x18 22. "PADCONFIG6_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x18 21. "PADCONFIG6_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x18 19.--20. "PADCONFIG6_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x18 18. "PADCONFIG6_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x18 17. "PADCONFIG6_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x18 16. "PADCONFIG6_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x18 15. "PADCONFIG6_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x18 14. "PADCONFIG6_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x18 11.--13. "PADCONFIG6_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8. "PADCONFIG6_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x18 7. "PADCONFIG6_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x18 4.--5. "PADCONFIG6_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x18 0.--3. 1. "PADCONFIG6_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b - Mux.." line.long 0x1C "CFG0_PADCONFIG7," bitfld.long 0x1C 31. "PADCONFIG7_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x1C 30. "PADCONFIG7_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x1C 29. "PADCONFIG7_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x1C 28. "PADCONFIG7_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x1C 27. "PADCONFIG7_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x1C 26. "PADCONFIG7_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x1C 25. "PADCONFIG7_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x1C 24. "PADCONFIG7_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x1C 23. "PADCONFIG7_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x1C 22. "PADCONFIG7_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x1C 21. "PADCONFIG7_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x1C 19.--20. "PADCONFIG7_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1C 18. "PADCONFIG7_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x1C 17. "PADCONFIG7_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x1C 16. "PADCONFIG7_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x1C 15. "PADCONFIG7_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x1C 14. "PADCONFIG7_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x1C 11.--13. "PADCONFIG7_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "PADCONFIG7_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x1C 7. "PADCONFIG7_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x1C 4.--5. "PADCONFIG7_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x1C 0.--3. 1. "PADCONFIG7_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b - Mux.." line.long 0x20 "CFG0_PADCONFIG8," bitfld.long 0x20 31. "PADCONFIG8_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x20 30. "PADCONFIG8_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x20 29. "PADCONFIG8_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x20 28. "PADCONFIG8_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x20 27. "PADCONFIG8_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x20 26. "PADCONFIG8_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x20 25. "PADCONFIG8_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x20 24. "PADCONFIG8_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x20 23. "PADCONFIG8_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x20 22. "PADCONFIG8_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x20 21. "PADCONFIG8_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x20 19.--20. "PADCONFIG8_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x20 18. "PADCONFIG8_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x20 17. "PADCONFIG8_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x20 16. "PADCONFIG8_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x20 15. "PADCONFIG8_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x20 14. "PADCONFIG8_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x20 11.--13. "PADCONFIG8_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 8. "PADCONFIG8_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x20 7. "PADCONFIG8_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x20 4.--5. "PADCONFIG8_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x20 0.--3. 1. "PADCONFIG8_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b - Mux.." line.long 0x24 "CFG0_PADCONFIG9," bitfld.long 0x24 31. "PADCONFIG9_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x24 30. "PADCONFIG9_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x24 29. "PADCONFIG9_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x24 28. "PADCONFIG9_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x24 27. "PADCONFIG9_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x24 26. "PADCONFIG9_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x24 25. "PADCONFIG9_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x24 24. "PADCONFIG9_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x24 23. "PADCONFIG9_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x24 22. "PADCONFIG9_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x24 21. "PADCONFIG9_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x24 19.--20. "PADCONFIG9_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x24 18. "PADCONFIG9_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x24 17. "PADCONFIG9_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x24 16. "PADCONFIG9_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x24 15. "PADCONFIG9_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x24 14. "PADCONFIG9_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x24 11.--13. "PADCONFIG9_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 8. "PADCONFIG9_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x24 7. "PADCONFIG9_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x24 4.--5. "PADCONFIG9_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x24 0.--3. 1. "PADCONFIG9_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b - Mux.." line.long 0x28 "CFG0_PADCONFIG10," bitfld.long 0x28 31. "PADCONFIG10_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x28 30. "PADCONFIG10_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x28 29. "PADCONFIG10_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x28 28. "PADCONFIG10_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x28 27. "PADCONFIG10_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x28 26. "PADCONFIG10_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x28 25. "PADCONFIG10_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x28 24. "PADCONFIG10_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x28 23. "PADCONFIG10_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x28 22. "PADCONFIG10_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x28 21. "PADCONFIG10_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x28 19.--20. "PADCONFIG10_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x28 18. "PADCONFIG10_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x28 17. "PADCONFIG10_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x28 16. "PADCONFIG10_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x28 15. "PADCONFIG10_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x28 14. "PADCONFIG10_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x28 11.--13. "PADCONFIG10_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8. "PADCONFIG10_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x28 7. "PADCONFIG10_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x28 4.--5. "PADCONFIG10_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x28 0.--3. 1. "PADCONFIG10_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x2C "CFG0_PADCONFIG11," bitfld.long 0x2C 31. "PADCONFIG11_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x2C 30. "PADCONFIG11_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x2C 29. "PADCONFIG11_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x2C 28. "PADCONFIG11_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x2C 27. "PADCONFIG11_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x2C 26. "PADCONFIG11_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x2C 25. "PADCONFIG11_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x2C 24. "PADCONFIG11_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x2C 23. "PADCONFIG11_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x2C 22. "PADCONFIG11_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x2C 21. "PADCONFIG11_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x2C 19.--20. "PADCONFIG11_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x2C 18. "PADCONFIG11_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x2C 17. "PADCONFIG11_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x2C 16. "PADCONFIG11_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x2C 15. "PADCONFIG11_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x2C 14. "PADCONFIG11_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x2C 11.--13. "PADCONFIG11_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 8. "PADCONFIG11_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x2C 7. "PADCONFIG11_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x2C 4.--5. "PADCONFIG11_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x2C 0.--3. 1. "PADCONFIG11_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x30 "CFG0_PADCONFIG12," bitfld.long 0x30 31. "PADCONFIG12_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x30 30. "PADCONFIG12_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x30 29. "PADCONFIG12_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x30 28. "PADCONFIG12_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x30 27. "PADCONFIG12_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x30 26. "PADCONFIG12_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x30 25. "PADCONFIG12_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x30 24. "PADCONFIG12_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x30 23. "PADCONFIG12_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x30 22. "PADCONFIG12_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x30 21. "PADCONFIG12_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x30 19.--20. "PADCONFIG12_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x30 18. "PADCONFIG12_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x30 17. "PADCONFIG12_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x30 16. "PADCONFIG12_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x30 15. "PADCONFIG12_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x30 14. "PADCONFIG12_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x30 11.--13. "PADCONFIG12_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 8. "PADCONFIG12_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x30 7. "PADCONFIG12_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x30 4.--5. "PADCONFIG12_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x30 0.--3. 1. "PADCONFIG12_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." rgroup.long 0x1C038++0x2B line.long 0x0 "CFG0_PADCONFIG14," bitfld.long 0x0 31. "PADCONFIG14_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x0 30. "PADCONFIG14_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x0 29. "PADCONFIG14_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x0 28. "PADCONFIG14_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x0 27. "PADCONFIG14_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x0 26. "PADCONFIG14_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x0 25. "PADCONFIG14_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x0 24. "PADCONFIG14_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x0 23. "PADCONFIG14_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x0 22. "PADCONFIG14_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x0 21. "PADCONFIG14_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x0 19.--20. "PADCONFIG14_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x0 18. "PADCONFIG14_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x0 17. "PADCONFIG14_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x0 16. "PADCONFIG14_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x0 15. "PADCONFIG14_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x0 14. "PADCONFIG14_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x0 11.--13. "PADCONFIG14_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "PADCONFIG14_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x0 7. "PADCONFIG14_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x0 4.--5. "PADCONFIG14_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "PADCONFIG14_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x4 "CFG0_PADCONFIG15," bitfld.long 0x4 31. "PADCONFIG15_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x4 30. "PADCONFIG15_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x4 29. "PADCONFIG15_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x4 28. "PADCONFIG15_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x4 27. "PADCONFIG15_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x4 26. "PADCONFIG15_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x4 25. "PADCONFIG15_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x4 24. "PADCONFIG15_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x4 23. "PADCONFIG15_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x4 22. "PADCONFIG15_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x4 21. "PADCONFIG15_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x4 19.--20. "PADCONFIG15_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4 18. "PADCONFIG15_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x4 17. "PADCONFIG15_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x4 16. "PADCONFIG15_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x4 15. "PADCONFIG15_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x4 14. "PADCONFIG15_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x4 11.--13. "PADCONFIG15_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8. "PADCONFIG15_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x4 7. "PADCONFIG15_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x4 4.--5. "PADCONFIG15_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "PADCONFIG15_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x8 "CFG0_PADCONFIG16," bitfld.long 0x8 31. "PADCONFIG16_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x8 30. "PADCONFIG16_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x8 29. "PADCONFIG16_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x8 28. "PADCONFIG16_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x8 27. "PADCONFIG16_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x8 26. "PADCONFIG16_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x8 25. "PADCONFIG16_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x8 24. "PADCONFIG16_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x8 23. "PADCONFIG16_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x8 22. "PADCONFIG16_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x8 21. "PADCONFIG16_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x8 19.--20. "PADCONFIG16_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8 18. "PADCONFIG16_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x8 17. "PADCONFIG16_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x8 16. "PADCONFIG16_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x8 15. "PADCONFIG16_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x8 14. "PADCONFIG16_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x8 11.--13. "PADCONFIG16_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "PADCONFIG16_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x8 7. "PADCONFIG16_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x8 4.--5. "PADCONFIG16_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x8 0.--3. 1. "PADCONFIG16_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0xC "CFG0_PADCONFIG17," bitfld.long 0xC 31. "PADCONFIG17_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xC 30. "PADCONFIG17_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xC 29. "PADCONFIG17_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xC 28. "PADCONFIG17_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xC 27. "PADCONFIG17_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xC 26. "PADCONFIG17_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xC 25. "PADCONFIG17_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xC 24. "PADCONFIG17_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xC 23. "PADCONFIG17_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC 22. "PADCONFIG17_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC 21. "PADCONFIG17_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xC 19.--20. "PADCONFIG17_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC 18. "PADCONFIG17_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xC 17. "PADCONFIG17_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xC 16. "PADCONFIG17_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xC 15. "PADCONFIG17_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xC 14. "PADCONFIG17_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xC 11.--13. "PADCONFIG17_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "PADCONFIG17_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xC 7. "PADCONFIG17_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xC 4.--5. "PADCONFIG17_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xC 0.--3. 1. "PADCONFIG17_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x10 "CFG0_PADCONFIG18," bitfld.long 0x10 31. "PADCONFIG18_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x10 30. "PADCONFIG18_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x10 29. "PADCONFIG18_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x10 28. "PADCONFIG18_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x10 27. "PADCONFIG18_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x10 26. "PADCONFIG18_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x10 25. "PADCONFIG18_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x10 24. "PADCONFIG18_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x10 23. "PADCONFIG18_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x10 22. "PADCONFIG18_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x10 21. "PADCONFIG18_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x10 19.--20. "PADCONFIG18_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x10 18. "PADCONFIG18_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x10 17. "PADCONFIG18_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x10 16. "PADCONFIG18_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x10 15. "PADCONFIG18_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x10 14. "PADCONFIG18_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x10 11.--13. "PADCONFIG18_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "PADCONFIG18_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x10 7. "PADCONFIG18_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x10 4.--5. "PADCONFIG18_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x10 0.--3. 1. "PADCONFIG18_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x14 "CFG0_PADCONFIG19," bitfld.long 0x14 31. "PADCONFIG19_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x14 30. "PADCONFIG19_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x14 29. "PADCONFIG19_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x14 28. "PADCONFIG19_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x14 27. "PADCONFIG19_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x14 26. "PADCONFIG19_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x14 25. "PADCONFIG19_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x14 24. "PADCONFIG19_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x14 23. "PADCONFIG19_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x14 22. "PADCONFIG19_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x14 21. "PADCONFIG19_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x14 19.--20. "PADCONFIG19_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x14 18. "PADCONFIG19_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x14 17. "PADCONFIG19_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x14 16. "PADCONFIG19_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x14 15. "PADCONFIG19_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x14 14. "PADCONFIG19_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x14 11.--13. "PADCONFIG19_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "PADCONFIG19_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x14 7. "PADCONFIG19_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x14 4.--5. "PADCONFIG19_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x14 0.--3. 1. "PADCONFIG19_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x18 "CFG0_PADCONFIG20," bitfld.long 0x18 31. "PADCONFIG20_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x18 30. "PADCONFIG20_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x18 29. "PADCONFIG20_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x18 28. "PADCONFIG20_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x18 27. "PADCONFIG20_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x18 26. "PADCONFIG20_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x18 25. "PADCONFIG20_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x18 24. "PADCONFIG20_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x18 23. "PADCONFIG20_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x18 22. "PADCONFIG20_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x18 21. "PADCONFIG20_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x18 19.--20. "PADCONFIG20_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x18 18. "PADCONFIG20_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x18 17. "PADCONFIG20_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x18 16. "PADCONFIG20_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x18 15. "PADCONFIG20_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x18 14. "PADCONFIG20_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x18 11.--13. "PADCONFIG20_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8. "PADCONFIG20_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x18 7. "PADCONFIG20_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x18 4.--5. "PADCONFIG20_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x18 0.--3. 1. "PADCONFIG20_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x1C "CFG0_PADCONFIG21," bitfld.long 0x1C 31. "PADCONFIG21_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x1C 30. "PADCONFIG21_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x1C 29. "PADCONFIG21_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x1C 28. "PADCONFIG21_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x1C 27. "PADCONFIG21_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x1C 26. "PADCONFIG21_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x1C 25. "PADCONFIG21_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x1C 24. "PADCONFIG21_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x1C 23. "PADCONFIG21_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x1C 22. "PADCONFIG21_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x1C 21. "PADCONFIG21_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x1C 19.--20. "PADCONFIG21_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1C 18. "PADCONFIG21_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x1C 17. "PADCONFIG21_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x1C 16. "PADCONFIG21_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x1C 15. "PADCONFIG21_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x1C 14. "PADCONFIG21_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x1C 11.--13. "PADCONFIG21_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "PADCONFIG21_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x1C 7. "PADCONFIG21_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x1C 4.--5. "PADCONFIG21_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x1C 0.--3. 1. "PADCONFIG21_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x20 "CFG0_PADCONFIG22," bitfld.long 0x20 31. "PADCONFIG22_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x20 30. "PADCONFIG22_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x20 29. "PADCONFIG22_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x20 28. "PADCONFIG22_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x20 27. "PADCONFIG22_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x20 26. "PADCONFIG22_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x20 25. "PADCONFIG22_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x20 24. "PADCONFIG22_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x20 23. "PADCONFIG22_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x20 22. "PADCONFIG22_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x20 21. "PADCONFIG22_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x20 19.--20. "PADCONFIG22_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x20 18. "PADCONFIG22_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x20 17. "PADCONFIG22_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x20 16. "PADCONFIG22_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x20 15. "PADCONFIG22_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x20 14. "PADCONFIG22_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x20 11.--13. "PADCONFIG22_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 8. "PADCONFIG22_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x20 7. "PADCONFIG22_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x20 4.--5. "PADCONFIG22_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x20 0.--3. 1. "PADCONFIG22_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x24 "CFG0_PADCONFIG23," bitfld.long 0x24 31. "PADCONFIG23_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x24 30. "PADCONFIG23_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x24 29. "PADCONFIG23_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x24 28. "PADCONFIG23_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x24 27. "PADCONFIG23_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x24 26. "PADCONFIG23_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x24 25. "PADCONFIG23_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x24 24. "PADCONFIG23_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x24 23. "PADCONFIG23_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x24 22. "PADCONFIG23_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x24 21. "PADCONFIG23_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x24 19.--20. "PADCONFIG23_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x24 18. "PADCONFIG23_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x24 17. "PADCONFIG23_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x24 16. "PADCONFIG23_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x24 15. "PADCONFIG23_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x24 14. "PADCONFIG23_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x24 11.--13. "PADCONFIG23_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 8. "PADCONFIG23_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x24 7. "PADCONFIG23_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x24 4.--5. "PADCONFIG23_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x24 0.--3. 1. "PADCONFIG23_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x28 "CFG0_PADCONFIG24," bitfld.long 0x28 31. "PADCONFIG24_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x28 30. "PADCONFIG24_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x28 29. "PADCONFIG24_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x28 28. "PADCONFIG24_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x28 27. "PADCONFIG24_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x28 26. "PADCONFIG24_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x28 25. "PADCONFIG24_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x28 24. "PADCONFIG24_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x28 23. "PADCONFIG24_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x28 22. "PADCONFIG24_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x28 21. "PADCONFIG24_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x28 19.--20. "PADCONFIG24_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x28 18. "PADCONFIG24_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x28 17. "PADCONFIG24_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x28 16. "PADCONFIG24_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x28 15. "PADCONFIG24_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x28 14. "PADCONFIG24_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x28 11.--13. "PADCONFIG24_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8. "PADCONFIG24_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x28 7. "PADCONFIG24_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x28 4.--5. "PADCONFIG24_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x28 0.--3. 1. "PADCONFIG24_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." rgroup.long 0x1C068++0x11F line.long 0x0 "CFG0_PADCONFIG26," bitfld.long 0x0 31. "PADCONFIG26_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x0 30. "PADCONFIG26_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x0 29. "PADCONFIG26_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x0 28. "PADCONFIG26_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x0 27. "PADCONFIG26_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x0 26. "PADCONFIG26_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x0 25. "PADCONFIG26_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x0 24. "PADCONFIG26_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x0 23. "PADCONFIG26_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x0 22. "PADCONFIG26_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x0 21. "PADCONFIG26_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x0 19.--20. "PADCONFIG26_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x0 18. "PADCONFIG26_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x0 17. "PADCONFIG26_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x0 16. "PADCONFIG26_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x0 15. "PADCONFIG26_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x0 14. "PADCONFIG26_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x0 11.--13. "PADCONFIG26_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "PADCONFIG26_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x0 7. "PADCONFIG26_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x0 4.--5. "PADCONFIG26_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "PADCONFIG26_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x4 "CFG0_PADCONFIG27," bitfld.long 0x4 31. "PADCONFIG27_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x4 30. "PADCONFIG27_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x4 29. "PADCONFIG27_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x4 28. "PADCONFIG27_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x4 27. "PADCONFIG27_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x4 26. "PADCONFIG27_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x4 25. "PADCONFIG27_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x4 24. "PADCONFIG27_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x4 23. "PADCONFIG27_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x4 22. "PADCONFIG27_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x4 21. "PADCONFIG27_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x4 19.--20. "PADCONFIG27_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4 18. "PADCONFIG27_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x4 17. "PADCONFIG27_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x4 16. "PADCONFIG27_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x4 15. "PADCONFIG27_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x4 14. "PADCONFIG27_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x4 11.--13. "PADCONFIG27_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8. "PADCONFIG27_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x4 7. "PADCONFIG27_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x4 4.--5. "PADCONFIG27_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "PADCONFIG27_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x8 "CFG0_PADCONFIG28," bitfld.long 0x8 31. "PADCONFIG28_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x8 30. "PADCONFIG28_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x8 29. "PADCONFIG28_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x8 28. "PADCONFIG28_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x8 27. "PADCONFIG28_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x8 26. "PADCONFIG28_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x8 25. "PADCONFIG28_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x8 24. "PADCONFIG28_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x8 23. "PADCONFIG28_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x8 22. "PADCONFIG28_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x8 21. "PADCONFIG28_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x8 19.--20. "PADCONFIG28_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8 18. "PADCONFIG28_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x8 17. "PADCONFIG28_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x8 16. "PADCONFIG28_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x8 15. "PADCONFIG28_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x8 14. "PADCONFIG28_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x8 11.--13. "PADCONFIG28_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "PADCONFIG28_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x8 7. "PADCONFIG28_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x8 4.--5. "PADCONFIG28_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x8 0.--3. 1. "PADCONFIG28_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0xC "CFG0_PADCONFIG29," bitfld.long 0xC 31. "PADCONFIG29_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xC 30. "PADCONFIG29_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xC 29. "PADCONFIG29_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xC 28. "PADCONFIG29_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xC 27. "PADCONFIG29_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xC 26. "PADCONFIG29_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xC 25. "PADCONFIG29_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xC 24. "PADCONFIG29_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xC 23. "PADCONFIG29_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC 22. "PADCONFIG29_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC 21. "PADCONFIG29_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xC 19.--20. "PADCONFIG29_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC 18. "PADCONFIG29_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xC 17. "PADCONFIG29_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xC 16. "PADCONFIG29_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xC 15. "PADCONFIG29_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xC 14. "PADCONFIG29_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xC 11.--13. "PADCONFIG29_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "PADCONFIG29_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xC 7. "PADCONFIG29_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xC 4.--5. "PADCONFIG29_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xC 0.--3. 1. "PADCONFIG29_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x10 "CFG0_PADCONFIG30," bitfld.long 0x10 31. "PADCONFIG30_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x10 30. "PADCONFIG30_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x10 29. "PADCONFIG30_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x10 28. "PADCONFIG30_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x10 27. "PADCONFIG30_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x10 26. "PADCONFIG30_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x10 25. "PADCONFIG30_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x10 24. "PADCONFIG30_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x10 23. "PADCONFIG30_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x10 22. "PADCONFIG30_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x10 21. "PADCONFIG30_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x10 19.--20. "PADCONFIG30_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x10 18. "PADCONFIG30_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x10 17. "PADCONFIG30_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x10 16. "PADCONFIG30_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x10 15. "PADCONFIG30_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x10 14. "PADCONFIG30_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x10 11.--13. "PADCONFIG30_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "PADCONFIG30_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x10 7. "PADCONFIG30_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x10 4.--5. "PADCONFIG30_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x10 0.--3. 1. "PADCONFIG30_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x14 "CFG0_PADCONFIG31," bitfld.long 0x14 31. "PADCONFIG31_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x14 30. "PADCONFIG31_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x14 29. "PADCONFIG31_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x14 28. "PADCONFIG31_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x14 27. "PADCONFIG31_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x14 26. "PADCONFIG31_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x14 25. "PADCONFIG31_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x14 24. "PADCONFIG31_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x14 23. "PADCONFIG31_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x14 22. "PADCONFIG31_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x14 21. "PADCONFIG31_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x14 19.--20. "PADCONFIG31_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x14 18. "PADCONFIG31_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x14 17. "PADCONFIG31_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x14 16. "PADCONFIG31_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x14 15. "PADCONFIG31_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x14 14. "PADCONFIG31_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x14 11.--13. "PADCONFIG31_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "PADCONFIG31_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x14 7. "PADCONFIG31_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x14 4.--5. "PADCONFIG31_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x14 0.--3. 1. "PADCONFIG31_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x18 "CFG0_PADCONFIG32," bitfld.long 0x18 31. "PADCONFIG32_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x18 30. "PADCONFIG32_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x18 29. "PADCONFIG32_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x18 28. "PADCONFIG32_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x18 27. "PADCONFIG32_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x18 26. "PADCONFIG32_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x18 25. "PADCONFIG32_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x18 24. "PADCONFIG32_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x18 23. "PADCONFIG32_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x18 22. "PADCONFIG32_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x18 21. "PADCONFIG32_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x18 19.--20. "PADCONFIG32_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x18 18. "PADCONFIG32_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x18 17. "PADCONFIG32_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x18 16. "PADCONFIG32_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x18 15. "PADCONFIG32_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x18 14. "PADCONFIG32_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x18 11.--13. "PADCONFIG32_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8. "PADCONFIG32_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x18 7. "PADCONFIG32_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x18 4.--5. "PADCONFIG32_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x18 0.--3. 1. "PADCONFIG32_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x1C "CFG0_PADCONFIG33," bitfld.long 0x1C 31. "PADCONFIG33_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x1C 30. "PADCONFIG33_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x1C 29. "PADCONFIG33_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x1C 28. "PADCONFIG33_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x1C 27. "PADCONFIG33_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x1C 26. "PADCONFIG33_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x1C 25. "PADCONFIG33_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x1C 24. "PADCONFIG33_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x1C 23. "PADCONFIG33_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x1C 22. "PADCONFIG33_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x1C 21. "PADCONFIG33_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x1C 19.--20. "PADCONFIG33_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1C 18. "PADCONFIG33_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x1C 17. "PADCONFIG33_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x1C 16. "PADCONFIG33_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x1C 15. "PADCONFIG33_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x1C 14. "PADCONFIG33_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x1C 11.--13. "PADCONFIG33_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "PADCONFIG33_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x1C 7. "PADCONFIG33_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x1C 4.--5. "PADCONFIG33_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x1C 0.--3. 1. "PADCONFIG33_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x20 "CFG0_PADCONFIG34," bitfld.long 0x20 31. "PADCONFIG34_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x20 30. "PADCONFIG34_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x20 29. "PADCONFIG34_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x20 28. "PADCONFIG34_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x20 27. "PADCONFIG34_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x20 26. "PADCONFIG34_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x20 25. "PADCONFIG34_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x20 24. "PADCONFIG34_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x20 23. "PADCONFIG34_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x20 22. "PADCONFIG34_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x20 21. "PADCONFIG34_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x20 19.--20. "PADCONFIG34_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x20 18. "PADCONFIG34_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x20 17. "PADCONFIG34_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x20 16. "PADCONFIG34_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x20 15. "PADCONFIG34_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x20 14. "PADCONFIG34_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x20 11.--13. "PADCONFIG34_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 8. "PADCONFIG34_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x20 7. "PADCONFIG34_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x20 4.--5. "PADCONFIG34_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x20 0.--3. 1. "PADCONFIG34_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x24 "CFG0_PADCONFIG35," bitfld.long 0x24 31. "PADCONFIG35_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x24 30. "PADCONFIG35_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x24 29. "PADCONFIG35_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x24 28. "PADCONFIG35_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x24 27. "PADCONFIG35_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x24 26. "PADCONFIG35_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x24 25. "PADCONFIG35_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x24 24. "PADCONFIG35_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x24 23. "PADCONFIG35_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x24 22. "PADCONFIG35_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x24 21. "PADCONFIG35_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x24 19.--20. "PADCONFIG35_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x24 18. "PADCONFIG35_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x24 17. "PADCONFIG35_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x24 16. "PADCONFIG35_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x24 15. "PADCONFIG35_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x24 14. "PADCONFIG35_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x24 11.--13. "PADCONFIG35_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 8. "PADCONFIG35_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x24 7. "PADCONFIG35_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x24 4.--5. "PADCONFIG35_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x24 0.--3. 1. "PADCONFIG35_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x28 "CFG0_PADCONFIG36," bitfld.long 0x28 31. "PADCONFIG36_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x28 30. "PADCONFIG36_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x28 29. "PADCONFIG36_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x28 28. "PADCONFIG36_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x28 27. "PADCONFIG36_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x28 26. "PADCONFIG36_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x28 25. "PADCONFIG36_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x28 24. "PADCONFIG36_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x28 23. "PADCONFIG36_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x28 22. "PADCONFIG36_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x28 21. "PADCONFIG36_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x28 19.--20. "PADCONFIG36_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x28 18. "PADCONFIG36_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x28 17. "PADCONFIG36_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x28 16. "PADCONFIG36_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x28 15. "PADCONFIG36_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x28 14. "PADCONFIG36_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x28 11.--13. "PADCONFIG36_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8. "PADCONFIG36_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x28 7. "PADCONFIG36_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x28 4.--5. "PADCONFIG36_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x28 0.--3. 1. "PADCONFIG36_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x2C "CFG0_PADCONFIG37," bitfld.long 0x2C 31. "PADCONFIG37_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x2C 30. "PADCONFIG37_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x2C 29. "PADCONFIG37_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x2C 28. "PADCONFIG37_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x2C 27. "PADCONFIG37_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x2C 26. "PADCONFIG37_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x2C 25. "PADCONFIG37_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x2C 24. "PADCONFIG37_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x2C 23. "PADCONFIG37_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x2C 22. "PADCONFIG37_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x2C 21. "PADCONFIG37_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x2C 19.--20. "PADCONFIG37_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x2C 18. "PADCONFIG37_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x2C 17. "PADCONFIG37_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x2C 16. "PADCONFIG37_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x2C 15. "PADCONFIG37_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x2C 14. "PADCONFIG37_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x2C 11.--13. "PADCONFIG37_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 8. "PADCONFIG37_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x2C 7. "PADCONFIG37_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x2C 4.--5. "PADCONFIG37_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x2C 0.--3. 1. "PADCONFIG37_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x30 "CFG0_PADCONFIG38," bitfld.long 0x30 31. "PADCONFIG38_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x30 30. "PADCONFIG38_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x30 29. "PADCONFIG38_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x30 28. "PADCONFIG38_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x30 27. "PADCONFIG38_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x30 26. "PADCONFIG38_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x30 25. "PADCONFIG38_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x30 24. "PADCONFIG38_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x30 23. "PADCONFIG38_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x30 22. "PADCONFIG38_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x30 21. "PADCONFIG38_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x30 19.--20. "PADCONFIG38_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x30 18. "PADCONFIG38_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x30 17. "PADCONFIG38_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x30 16. "PADCONFIG38_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x30 15. "PADCONFIG38_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x30 14. "PADCONFIG38_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x30 11.--13. "PADCONFIG38_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 8. "PADCONFIG38_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x30 7. "PADCONFIG38_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x30 4.--5. "PADCONFIG38_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x30 0.--3. 1. "PADCONFIG38_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x34 "CFG0_PADCONFIG39," bitfld.long 0x34 31. "PADCONFIG39_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x34 30. "PADCONFIG39_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x34 29. "PADCONFIG39_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x34 28. "PADCONFIG39_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x34 27. "PADCONFIG39_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x34 26. "PADCONFIG39_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x34 25. "PADCONFIG39_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x34 24. "PADCONFIG39_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x34 23. "PADCONFIG39_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x34 22. "PADCONFIG39_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x34 21. "PADCONFIG39_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x34 19.--20. "PADCONFIG39_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x34 18. "PADCONFIG39_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x34 17. "PADCONFIG39_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x34 16. "PADCONFIG39_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x34 15. "PADCONFIG39_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x34 14. "PADCONFIG39_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x34 11.--13. "PADCONFIG39_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 8. "PADCONFIG39_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x34 7. "PADCONFIG39_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x34 4.--5. "PADCONFIG39_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x34 0.--3. 1. "PADCONFIG39_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x38 "CFG0_PADCONFIG40," bitfld.long 0x38 31. "PADCONFIG40_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x38 30. "PADCONFIG40_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x38 29. "PADCONFIG40_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x38 28. "PADCONFIG40_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x38 27. "PADCONFIG40_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x38 26. "PADCONFIG40_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x38 25. "PADCONFIG40_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x38 24. "PADCONFIG40_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x38 23. "PADCONFIG40_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x38 22. "PADCONFIG40_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x38 21. "PADCONFIG40_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x38 19.--20. "PADCONFIG40_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x38 18. "PADCONFIG40_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x38 17. "PADCONFIG40_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x38 16. "PADCONFIG40_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x38 15. "PADCONFIG40_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x38 14. "PADCONFIG40_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x38 11.--13. "PADCONFIG40_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 8. "PADCONFIG40_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x38 7. "PADCONFIG40_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x38 4.--5. "PADCONFIG40_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x38 0.--3. 1. "PADCONFIG40_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x3C "CFG0_PADCONFIG41," bitfld.long 0x3C 31. "PADCONFIG41_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x3C 30. "PADCONFIG41_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x3C 29. "PADCONFIG41_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x3C 28. "PADCONFIG41_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x3C 27. "PADCONFIG41_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x3C 26. "PADCONFIG41_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x3C 25. "PADCONFIG41_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x3C 24. "PADCONFIG41_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x3C 23. "PADCONFIG41_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x3C 22. "PADCONFIG41_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x3C 21. "PADCONFIG41_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x3C 19.--20. "PADCONFIG41_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x3C 18. "PADCONFIG41_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x3C 17. "PADCONFIG41_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x3C 16. "PADCONFIG41_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x3C 15. "PADCONFIG41_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x3C 14. "PADCONFIG41_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x3C 11.--13. "PADCONFIG41_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x3C 8. "PADCONFIG41_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x3C 7. "PADCONFIG41_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x3C 4.--5. "PADCONFIG41_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x3C 0.--3. 1. "PADCONFIG41_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x40 "CFG0_PADCONFIG42," bitfld.long 0x40 31. "PADCONFIG42_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x40 30. "PADCONFIG42_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x40 29. "PADCONFIG42_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x40 28. "PADCONFIG42_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x40 27. "PADCONFIG42_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x40 26. "PADCONFIG42_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x40 25. "PADCONFIG42_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x40 24. "PADCONFIG42_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x40 23. "PADCONFIG42_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x40 22. "PADCONFIG42_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x40 21. "PADCONFIG42_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x40 19.--20. "PADCONFIG42_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x40 18. "PADCONFIG42_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x40 17. "PADCONFIG42_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x40 16. "PADCONFIG42_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x40 15. "PADCONFIG42_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x40 14. "PADCONFIG42_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x40 11.--13. "PADCONFIG42_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 8. "PADCONFIG42_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x40 7. "PADCONFIG42_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x40 4.--5. "PADCONFIG42_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x40 0.--3. 1. "PADCONFIG42_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x44 "CFG0_PADCONFIG43," bitfld.long 0x44 31. "PADCONFIG43_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x44 30. "PADCONFIG43_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x44 29. "PADCONFIG43_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x44 28. "PADCONFIG43_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x44 27. "PADCONFIG43_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x44 26. "PADCONFIG43_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x44 25. "PADCONFIG43_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x44 24. "PADCONFIG43_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x44 23. "PADCONFIG43_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x44 22. "PADCONFIG43_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x44 21. "PADCONFIG43_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x44 19.--20. "PADCONFIG43_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x44 18. "PADCONFIG43_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x44 17. "PADCONFIG43_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x44 16. "PADCONFIG43_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x44 15. "PADCONFIG43_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x44 14. "PADCONFIG43_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x44 11.--13. "PADCONFIG43_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x44 8. "PADCONFIG43_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x44 7. "PADCONFIG43_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x44 4.--5. "PADCONFIG43_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x44 0.--3. 1. "PADCONFIG43_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x48 "CFG0_PADCONFIG44," bitfld.long 0x48 31. "PADCONFIG44_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x48 30. "PADCONFIG44_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x48 29. "PADCONFIG44_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x48 28. "PADCONFIG44_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x48 27. "PADCONFIG44_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x48 26. "PADCONFIG44_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x48 25. "PADCONFIG44_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x48 24. "PADCONFIG44_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x48 23. "PADCONFIG44_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x48 22. "PADCONFIG44_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x48 21. "PADCONFIG44_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x48 19.--20. "PADCONFIG44_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x48 18. "PADCONFIG44_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x48 17. "PADCONFIG44_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x48 16. "PADCONFIG44_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x48 15. "PADCONFIG44_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x48 14. "PADCONFIG44_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x48 11.--13. "PADCONFIG44_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 8. "PADCONFIG44_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x48 7. "PADCONFIG44_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x48 4.--5. "PADCONFIG44_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x48 0.--3. 1. "PADCONFIG44_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x4C "CFG0_PADCONFIG45," bitfld.long 0x4C 31. "PADCONFIG45_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x4C 30. "PADCONFIG45_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x4C 29. "PADCONFIG45_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x4C 28. "PADCONFIG45_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x4C 27. "PADCONFIG45_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x4C 26. "PADCONFIG45_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x4C 25. "PADCONFIG45_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x4C 24. "PADCONFIG45_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x4C 23. "PADCONFIG45_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x4C 22. "PADCONFIG45_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x4C 21. "PADCONFIG45_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x4C 19.--20. "PADCONFIG45_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4C 18. "PADCONFIG45_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x4C 17. "PADCONFIG45_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x4C 16. "PADCONFIG45_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x4C 15. "PADCONFIG45_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x4C 14. "PADCONFIG45_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x4C 11.--13. "PADCONFIG45_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4C 8. "PADCONFIG45_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x4C 7. "PADCONFIG45_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x4C 4.--5. "PADCONFIG45_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x4C 0.--3. 1. "PADCONFIG45_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x50 "CFG0_PADCONFIG46," bitfld.long 0x50 31. "PADCONFIG46_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x50 30. "PADCONFIG46_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x50 29. "PADCONFIG46_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x50 28. "PADCONFIG46_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x50 27. "PADCONFIG46_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x50 26. "PADCONFIG46_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x50 25. "PADCONFIG46_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x50 24. "PADCONFIG46_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x50 23. "PADCONFIG46_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x50 22. "PADCONFIG46_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x50 21. "PADCONFIG46_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x50 19.--20. "PADCONFIG46_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x50 18. "PADCONFIG46_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x50 17. "PADCONFIG46_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x50 16. "PADCONFIG46_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x50 15. "PADCONFIG46_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x50 14. "PADCONFIG46_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x50 11.--13. "PADCONFIG46_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 8. "PADCONFIG46_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x50 7. "PADCONFIG46_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x50 4.--5. "PADCONFIG46_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x50 0.--3. 1. "PADCONFIG46_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x54 "CFG0_PADCONFIG47," bitfld.long 0x54 31. "PADCONFIG47_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x54 30. "PADCONFIG47_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x54 29. "PADCONFIG47_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x54 28. "PADCONFIG47_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x54 27. "PADCONFIG47_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x54 26. "PADCONFIG47_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x54 25. "PADCONFIG47_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x54 24. "PADCONFIG47_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x54 23. "PADCONFIG47_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x54 22. "PADCONFIG47_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x54 21. "PADCONFIG47_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x54 19.--20. "PADCONFIG47_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x54 18. "PADCONFIG47_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x54 17. "PADCONFIG47_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x54 16. "PADCONFIG47_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x54 15. "PADCONFIG47_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x54 14. "PADCONFIG47_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x54 11.--13. "PADCONFIG47_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x54 8. "PADCONFIG47_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x54 7. "PADCONFIG47_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x54 4.--5. "PADCONFIG47_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x54 0.--3. 1. "PADCONFIG47_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x58 "CFG0_PADCONFIG48," bitfld.long 0x58 31. "PADCONFIG48_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x58 30. "PADCONFIG48_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x58 29. "PADCONFIG48_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x58 28. "PADCONFIG48_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x58 27. "PADCONFIG48_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x58 26. "PADCONFIG48_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x58 25. "PADCONFIG48_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x58 24. "PADCONFIG48_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x58 23. "PADCONFIG48_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x58 22. "PADCONFIG48_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x58 21. "PADCONFIG48_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x58 19.--20. "PADCONFIG48_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x58 18. "PADCONFIG48_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x58 17. "PADCONFIG48_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x58 16. "PADCONFIG48_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x58 15. "PADCONFIG48_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x58 14. "PADCONFIG48_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x58 11.--13. "PADCONFIG48_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 8. "PADCONFIG48_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x58 7. "PADCONFIG48_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x58 4.--5. "PADCONFIG48_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x58 0.--3. 1. "PADCONFIG48_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x5C "CFG0_PADCONFIG49," bitfld.long 0x5C 31. "PADCONFIG49_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x5C 30. "PADCONFIG49_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x5C 29. "PADCONFIG49_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x5C 28. "PADCONFIG49_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x5C 27. "PADCONFIG49_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x5C 26. "PADCONFIG49_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x5C 25. "PADCONFIG49_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x5C 24. "PADCONFIG49_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x5C 23. "PADCONFIG49_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x5C 22. "PADCONFIG49_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x5C 21. "PADCONFIG49_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x5C 19.--20. "PADCONFIG49_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x5C 18. "PADCONFIG49_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x5C 17. "PADCONFIG49_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x5C 16. "PADCONFIG49_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x5C 15. "PADCONFIG49_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x5C 14. "PADCONFIG49_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x5C 11.--13. "PADCONFIG49_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x5C 8. "PADCONFIG49_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x5C 7. "PADCONFIG49_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x5C 4.--5. "PADCONFIG49_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x5C 0.--3. 1. "PADCONFIG49_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x60 "CFG0_PADCONFIG50," bitfld.long 0x60 31. "PADCONFIG50_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x60 30. "PADCONFIG50_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x60 29. "PADCONFIG50_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x60 28. "PADCONFIG50_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x60 27. "PADCONFIG50_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x60 26. "PADCONFIG50_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x60 25. "PADCONFIG50_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x60 24. "PADCONFIG50_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x60 23. "PADCONFIG50_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x60 22. "PADCONFIG50_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x60 21. "PADCONFIG50_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x60 19.--20. "PADCONFIG50_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x60 18. "PADCONFIG50_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x60 17. "PADCONFIG50_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x60 16. "PADCONFIG50_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x60 15. "PADCONFIG50_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x60 14. "PADCONFIG50_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x60 11.--13. "PADCONFIG50_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 8. "PADCONFIG50_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x60 7. "PADCONFIG50_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x60 4.--5. "PADCONFIG50_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x60 0.--3. 1. "PADCONFIG50_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x64 "CFG0_PADCONFIG51," bitfld.long 0x64 31. "PADCONFIG51_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x64 30. "PADCONFIG51_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x64 29. "PADCONFIG51_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x64 28. "PADCONFIG51_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x64 27. "PADCONFIG51_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x64 26. "PADCONFIG51_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x64 25. "PADCONFIG51_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x64 24. "PADCONFIG51_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x64 23. "PADCONFIG51_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x64 22. "PADCONFIG51_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x64 21. "PADCONFIG51_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x64 19.--20. "PADCONFIG51_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x64 18. "PADCONFIG51_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x64 17. "PADCONFIG51_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x64 16. "PADCONFIG51_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x64 15. "PADCONFIG51_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x64 14. "PADCONFIG51_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x64 11.--13. "PADCONFIG51_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x64 8. "PADCONFIG51_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x64 7. "PADCONFIG51_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x64 4.--5. "PADCONFIG51_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x64 0.--3. 1. "PADCONFIG51_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x68 "CFG0_PADCONFIG52," bitfld.long 0x68 31. "PADCONFIG52_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x68 30. "PADCONFIG52_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x68 29. "PADCONFIG52_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x68 28. "PADCONFIG52_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x68 27. "PADCONFIG52_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x68 26. "PADCONFIG52_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x68 25. "PADCONFIG52_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x68 24. "PADCONFIG52_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x68 23. "PADCONFIG52_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x68 22. "PADCONFIG52_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x68 21. "PADCONFIG52_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x68 19.--20. "PADCONFIG52_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x68 18. "PADCONFIG52_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x68 17. "PADCONFIG52_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x68 16. "PADCONFIG52_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x68 15. "PADCONFIG52_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x68 14. "PADCONFIG52_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x68 11.--13. "PADCONFIG52_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 8. "PADCONFIG52_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x68 7. "PADCONFIG52_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x68 4.--5. "PADCONFIG52_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x68 0.--3. 1. "PADCONFIG52_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x6C "CFG0_PADCONFIG53," bitfld.long 0x6C 31. "PADCONFIG53_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x6C 30. "PADCONFIG53_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x6C 29. "PADCONFIG53_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x6C 28. "PADCONFIG53_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x6C 27. "PADCONFIG53_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x6C 26. "PADCONFIG53_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x6C 25. "PADCONFIG53_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x6C 24. "PADCONFIG53_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x6C 23. "PADCONFIG53_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x6C 22. "PADCONFIG53_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x6C 21. "PADCONFIG53_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x6C 19.--20. "PADCONFIG53_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x6C 18. "PADCONFIG53_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x6C 17. "PADCONFIG53_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x6C 16. "PADCONFIG53_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x6C 15. "PADCONFIG53_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x6C 14. "PADCONFIG53_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x6C 11.--13. "PADCONFIG53_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x6C 8. "PADCONFIG53_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x6C 7. "PADCONFIG53_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x6C 4.--5. "PADCONFIG53_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x6C 0.--3. 1. "PADCONFIG53_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x70 "CFG0_PADCONFIG54," bitfld.long 0x70 31. "PADCONFIG54_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x70 30. "PADCONFIG54_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x70 29. "PADCONFIG54_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x70 28. "PADCONFIG54_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x70 27. "PADCONFIG54_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x70 26. "PADCONFIG54_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x70 25. "PADCONFIG54_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x70 24. "PADCONFIG54_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x70 23. "PADCONFIG54_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x70 22. "PADCONFIG54_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x70 21. "PADCONFIG54_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x70 19.--20. "PADCONFIG54_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x70 18. "PADCONFIG54_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x70 17. "PADCONFIG54_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x70 16. "PADCONFIG54_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x70 15. "PADCONFIG54_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x70 14. "PADCONFIG54_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x70 11.--13. "PADCONFIG54_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 8. "PADCONFIG54_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x70 7. "PADCONFIG54_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x70 4.--5. "PADCONFIG54_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x70 0.--3. 1. "PADCONFIG54_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x74 "CFG0_PADCONFIG55," bitfld.long 0x74 31. "PADCONFIG55_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x74 30. "PADCONFIG55_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x74 29. "PADCONFIG55_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x74 28. "PADCONFIG55_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x74 27. "PADCONFIG55_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x74 26. "PADCONFIG55_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x74 25. "PADCONFIG55_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x74 24. "PADCONFIG55_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x74 23. "PADCONFIG55_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x74 22. "PADCONFIG55_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x74 21. "PADCONFIG55_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x74 19.--20. "PADCONFIG55_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x74 18. "PADCONFIG55_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x74 17. "PADCONFIG55_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x74 16. "PADCONFIG55_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x74 15. "PADCONFIG55_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x74 14. "PADCONFIG55_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x74 11.--13. "PADCONFIG55_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x74 8. "PADCONFIG55_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x74 7. "PADCONFIG55_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x74 4.--5. "PADCONFIG55_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x74 0.--3. 1. "PADCONFIG55_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x78 "CFG0_PADCONFIG56," bitfld.long 0x78 31. "PADCONFIG56_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x78 30. "PADCONFIG56_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x78 29. "PADCONFIG56_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x78 28. "PADCONFIG56_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x78 27. "PADCONFIG56_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x78 26. "PADCONFIG56_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x78 25. "PADCONFIG56_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x78 24. "PADCONFIG56_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x78 23. "PADCONFIG56_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x78 22. "PADCONFIG56_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x78 21. "PADCONFIG56_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x78 19.--20. "PADCONFIG56_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x78 18. "PADCONFIG56_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x78 17. "PADCONFIG56_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x78 16. "PADCONFIG56_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x78 15. "PADCONFIG56_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x78 14. "PADCONFIG56_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x78 11.--13. "PADCONFIG56_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 8. "PADCONFIG56_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x78 7. "PADCONFIG56_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x78 4.--5. "PADCONFIG56_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x78 0.--3. 1. "PADCONFIG56_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x7C "CFG0_PADCONFIG57," bitfld.long 0x7C 31. "PADCONFIG57_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x7C 30. "PADCONFIG57_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x7C 29. "PADCONFIG57_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x7C 28. "PADCONFIG57_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x7C 27. "PADCONFIG57_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x7C 26. "PADCONFIG57_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x7C 25. "PADCONFIG57_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x7C 24. "PADCONFIG57_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x7C 23. "PADCONFIG57_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x7C 22. "PADCONFIG57_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x7C 21. "PADCONFIG57_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x7C 19.--20. "PADCONFIG57_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x7C 18. "PADCONFIG57_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x7C 17. "PADCONFIG57_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x7C 16. "PADCONFIG57_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x7C 15. "PADCONFIG57_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x7C 14. "PADCONFIG57_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x7C 11.--13. "PADCONFIG57_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x7C 8. "PADCONFIG57_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x7C 7. "PADCONFIG57_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x7C 4.--5. "PADCONFIG57_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x7C 0.--3. 1. "PADCONFIG57_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x80 "CFG0_PADCONFIG58," bitfld.long 0x80 31. "PADCONFIG58_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x80 30. "PADCONFIG58_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x80 29. "PADCONFIG58_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x80 28. "PADCONFIG58_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x80 27. "PADCONFIG58_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x80 26. "PADCONFIG58_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x80 25. "PADCONFIG58_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x80 24. "PADCONFIG58_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x80 23. "PADCONFIG58_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x80 22. "PADCONFIG58_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x80 21. "PADCONFIG58_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x80 19.--20. "PADCONFIG58_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x80 18. "PADCONFIG58_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x80 17. "PADCONFIG58_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x80 16. "PADCONFIG58_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x80 15. "PADCONFIG58_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x80 14. "PADCONFIG58_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x80 11.--13. "PADCONFIG58_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 8. "PADCONFIG58_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x80 7. "PADCONFIG58_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x80 4.--5. "PADCONFIG58_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x80 0.--3. 1. "PADCONFIG58_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x84 "CFG0_PADCONFIG59," bitfld.long 0x84 31. "PADCONFIG59_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x84 30. "PADCONFIG59_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x84 29. "PADCONFIG59_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x84 28. "PADCONFIG59_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x84 27. "PADCONFIG59_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x84 26. "PADCONFIG59_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x84 25. "PADCONFIG59_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x84 24. "PADCONFIG59_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x84 23. "PADCONFIG59_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x84 22. "PADCONFIG59_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x84 21. "PADCONFIG59_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x84 19.--20. "PADCONFIG59_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x84 18. "PADCONFIG59_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x84 17. "PADCONFIG59_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x84 16. "PADCONFIG59_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x84 15. "PADCONFIG59_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x84 14. "PADCONFIG59_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x84 11.--13. "PADCONFIG59_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x84 8. "PADCONFIG59_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x84 7. "PADCONFIG59_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x84 4.--5. "PADCONFIG59_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x84 0.--3. 1. "PADCONFIG59_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x88 "CFG0_PADCONFIG60," bitfld.long 0x88 31. "PADCONFIG60_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x88 30. "PADCONFIG60_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x88 29. "PADCONFIG60_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x88 28. "PADCONFIG60_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x88 27. "PADCONFIG60_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x88 26. "PADCONFIG60_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x88 25. "PADCONFIG60_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x88 24. "PADCONFIG60_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x88 23. "PADCONFIG60_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x88 22. "PADCONFIG60_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x88 21. "PADCONFIG60_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x88 19.--20. "PADCONFIG60_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x88 18. "PADCONFIG60_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x88 17. "PADCONFIG60_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x88 16. "PADCONFIG60_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x88 15. "PADCONFIG60_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x88 14. "PADCONFIG60_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x88 11.--13. "PADCONFIG60_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 8. "PADCONFIG60_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x88 7. "PADCONFIG60_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x88 4.--5. "PADCONFIG60_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x88 0.--3. 1. "PADCONFIG60_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x8C "CFG0_PADCONFIG61," bitfld.long 0x8C 31. "PADCONFIG61_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x8C 30. "PADCONFIG61_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x8C 29. "PADCONFIG61_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x8C 28. "PADCONFIG61_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x8C 27. "PADCONFIG61_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x8C 26. "PADCONFIG61_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x8C 25. "PADCONFIG61_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x8C 24. "PADCONFIG61_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x8C 23. "PADCONFIG61_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x8C 22. "PADCONFIG61_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x8C 21. "PADCONFIG61_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x8C 19.--20. "PADCONFIG61_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8C 18. "PADCONFIG61_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x8C 17. "PADCONFIG61_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x8C 16. "PADCONFIG61_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x8C 15. "PADCONFIG61_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x8C 14. "PADCONFIG61_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x8C 11.--13. "PADCONFIG61_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8C 8. "PADCONFIG61_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x8C 7. "PADCONFIG61_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x8C 4.--5. "PADCONFIG61_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x8C 0.--3. 1. "PADCONFIG61_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x90 "CFG0_PADCONFIG62," bitfld.long 0x90 31. "PADCONFIG62_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x90 30. "PADCONFIG62_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x90 29. "PADCONFIG62_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x90 28. "PADCONFIG62_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x90 27. "PADCONFIG62_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x90 26. "PADCONFIG62_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x90 25. "PADCONFIG62_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x90 24. "PADCONFIG62_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x90 23. "PADCONFIG62_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x90 22. "PADCONFIG62_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x90 21. "PADCONFIG62_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x90 19.--20. "PADCONFIG62_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x90 18. "PADCONFIG62_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x90 17. "PADCONFIG62_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x90 16. "PADCONFIG62_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x90 15. "PADCONFIG62_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x90 14. "PADCONFIG62_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x90 11.--13. "PADCONFIG62_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 8. "PADCONFIG62_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x90 7. "PADCONFIG62_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x90 4.--5. "PADCONFIG62_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x90 0.--3. 1. "PADCONFIG62_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x94 "CFG0_PADCONFIG63," bitfld.long 0x94 31. "PADCONFIG63_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x94 30. "PADCONFIG63_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x94 29. "PADCONFIG63_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x94 28. "PADCONFIG63_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x94 27. "PADCONFIG63_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x94 26. "PADCONFIG63_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x94 25. "PADCONFIG63_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x94 24. "PADCONFIG63_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x94 23. "PADCONFIG63_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x94 22. "PADCONFIG63_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x94 21. "PADCONFIG63_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x94 19.--20. "PADCONFIG63_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x94 18. "PADCONFIG63_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x94 17. "PADCONFIG63_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x94 16. "PADCONFIG63_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x94 15. "PADCONFIG63_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x94 14. "PADCONFIG63_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x94 11.--13. "PADCONFIG63_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x94 8. "PADCONFIG63_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x94 7. "PADCONFIG63_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x94 4.--5. "PADCONFIG63_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x94 0.--3. 1. "PADCONFIG63_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x98 "CFG0_PADCONFIG64," bitfld.long 0x98 31. "PADCONFIG64_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x98 30. "PADCONFIG64_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x98 29. "PADCONFIG64_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x98 26. "PADCONFIG64_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x98 25. "PADCONFIG64_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x98 24. "PADCONFIG64_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x98 23. "PADCONFIG64_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x98 22. "PADCONFIG64_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x98 21. "PADCONFIG64_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x98 18. "PADCONFIG64_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x98 15. "PADCONFIG64_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x98 14. "PADCONFIG64_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x98 11.--13. "PADCONFIG64_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 8. "PADCONFIG64_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x98 7. "PADCONFIG64_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x98 4.--5. "PADCONFIG64_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x98 0.--3. 1. "PADCONFIG64_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x9C "CFG0_PADCONFIG65," bitfld.long 0x9C 31. "PADCONFIG65_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x9C 30. "PADCONFIG65_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x9C 29. "PADCONFIG65_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x9C 26. "PADCONFIG65_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x9C 25. "PADCONFIG65_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x9C 24. "PADCONFIG65_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x9C 23. "PADCONFIG65_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x9C 22. "PADCONFIG65_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x9C 21. "PADCONFIG65_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x9C 18. "PADCONFIG65_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x9C 15. "PADCONFIG65_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x9C 14. "PADCONFIG65_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x9C 11.--13. "PADCONFIG65_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x9C 8. "PADCONFIG65_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x9C 7. "PADCONFIG65_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x9C 4.--5. "PADCONFIG65_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x9C 0.--3. 1. "PADCONFIG65_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0xA0 "CFG0_PADCONFIG66," bitfld.long 0xA0 31. "PADCONFIG66_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xA0 30. "PADCONFIG66_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xA0 29. "PADCONFIG66_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xA0 26. "PADCONFIG66_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xA0 25. "PADCONFIG66_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xA0 24. "PADCONFIG66_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xA0 23. "PADCONFIG66_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xA0 22. "PADCONFIG66_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xA0 21. "PADCONFIG66_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xA0 18. "PADCONFIG66_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xA0 15. "PADCONFIG66_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xA0 14. "PADCONFIG66_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xA0 11.--13. "PADCONFIG66_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 8. "PADCONFIG66_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xA0 7. "PADCONFIG66_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xA0 4.--5. "PADCONFIG66_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xA0 0.--3. 1. "PADCONFIG66_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0xA4 "CFG0_PADCONFIG67," bitfld.long 0xA4 31. "PADCONFIG67_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xA4 30. "PADCONFIG67_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xA4 29. "PADCONFIG67_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xA4 26. "PADCONFIG67_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xA4 25. "PADCONFIG67_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xA4 24. "PADCONFIG67_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xA4 23. "PADCONFIG67_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xA4 22. "PADCONFIG67_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xA4 21. "PADCONFIG67_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xA4 18. "PADCONFIG67_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xA4 15. "PADCONFIG67_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xA4 14. "PADCONFIG67_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xA4 11.--13. "PADCONFIG67_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA4 8. "PADCONFIG67_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xA4 7. "PADCONFIG67_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xA4 4.--5. "PADCONFIG67_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xA4 0.--3. 1. "PADCONFIG67_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0xA8 "CFG0_PADCONFIG68," bitfld.long 0xA8 31. "PADCONFIG68_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xA8 30. "PADCONFIG68_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xA8 29. "PADCONFIG68_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xA8 28. "PADCONFIG68_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xA8 27. "PADCONFIG68_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xA8 26. "PADCONFIG68_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xA8 25. "PADCONFIG68_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xA8 24. "PADCONFIG68_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xA8 23. "PADCONFIG68_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xA8 22. "PADCONFIG68_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xA8 21. "PADCONFIG68_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xA8 19.--20. "PADCONFIG68_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xA8 18. "PADCONFIG68_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xA8 17. "PADCONFIG68_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xA8 16. "PADCONFIG68_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xA8 15. "PADCONFIG68_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xA8 14. "PADCONFIG68_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xA8 11.--13. "PADCONFIG68_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 8. "PADCONFIG68_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xA8 7. "PADCONFIG68_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xA8 4.--5. "PADCONFIG68_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xA8 0.--3. 1. "PADCONFIG68_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0xAC "CFG0_PADCONFIG69," bitfld.long 0xAC 31. "PADCONFIG69_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xAC 30. "PADCONFIG69_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xAC 29. "PADCONFIG69_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xAC 28. "PADCONFIG69_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xAC 27. "PADCONFIG69_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xAC 26. "PADCONFIG69_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xAC 25. "PADCONFIG69_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xAC 24. "PADCONFIG69_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xAC 23. "PADCONFIG69_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xAC 22. "PADCONFIG69_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xAC 21. "PADCONFIG69_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xAC 19.--20. "PADCONFIG69_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xAC 18. "PADCONFIG69_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xAC 17. "PADCONFIG69_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xAC 16. "PADCONFIG69_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xAC 15. "PADCONFIG69_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xAC 14. "PADCONFIG69_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xAC 11.--13. "PADCONFIG69_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xAC 8. "PADCONFIG69_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xAC 7. "PADCONFIG69_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xAC 4.--5. "PADCONFIG69_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xAC 0.--3. 1. "PADCONFIG69_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0xB0 "CFG0_PADCONFIG70," bitfld.long 0xB0 31. "PADCONFIG70_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xB0 30. "PADCONFIG70_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xB0 29. "PADCONFIG70_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xB0 28. "PADCONFIG70_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xB0 27. "PADCONFIG70_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xB0 26. "PADCONFIG70_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xB0 25. "PADCONFIG70_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xB0 24. "PADCONFIG70_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xB0 23. "PADCONFIG70_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xB0 22. "PADCONFIG70_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xB0 21. "PADCONFIG70_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xB0 19.--20. "PADCONFIG70_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB0 18. "PADCONFIG70_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xB0 17. "PADCONFIG70_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xB0 16. "PADCONFIG70_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xB0 15. "PADCONFIG70_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xB0 14. "PADCONFIG70_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xB0 11.--13. "PADCONFIG70_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 8. "PADCONFIG70_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xB0 7. "PADCONFIG70_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xB0 4.--5. "PADCONFIG70_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xB0 0.--3. 1. "PADCONFIG70_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0xB4 "CFG0_PADCONFIG71," bitfld.long 0xB4 31. "PADCONFIG71_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xB4 30. "PADCONFIG71_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xB4 29. "PADCONFIG71_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xB4 28. "PADCONFIG71_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xB4 27. "PADCONFIG71_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xB4 26. "PADCONFIG71_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xB4 25. "PADCONFIG71_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xB4 24. "PADCONFIG71_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xB4 23. "PADCONFIG71_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xB4 22. "PADCONFIG71_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xB4 21. "PADCONFIG71_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xB4 19.--20. "PADCONFIG71_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB4 18. "PADCONFIG71_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xB4 17. "PADCONFIG71_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xB4 16. "PADCONFIG71_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xB4 15. "PADCONFIG71_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xB4 14. "PADCONFIG71_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xB4 11.--13. "PADCONFIG71_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB4 8. "PADCONFIG71_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xB4 7. "PADCONFIG71_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xB4 4.--5. "PADCONFIG71_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xB4 0.--3. 1. "PADCONFIG71_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0xB8 "CFG0_PADCONFIG72," bitfld.long 0xB8 31. "PADCONFIG72_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xB8 30. "PADCONFIG72_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xB8 29. "PADCONFIG72_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xB8 28. "PADCONFIG72_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xB8 27. "PADCONFIG72_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xB8 26. "PADCONFIG72_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xB8 25. "PADCONFIG72_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xB8 24. "PADCONFIG72_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xB8 23. "PADCONFIG72_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xB8 22. "PADCONFIG72_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xB8 21. "PADCONFIG72_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xB8 19.--20. "PADCONFIG72_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB8 18. "PADCONFIG72_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xB8 17. "PADCONFIG72_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xB8 16. "PADCONFIG72_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xB8 15. "PADCONFIG72_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xB8 14. "PADCONFIG72_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xB8 11.--13. "PADCONFIG72_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 8. "PADCONFIG72_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xB8 7. "PADCONFIG72_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xB8 4.--5. "PADCONFIG72_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xB8 0.--3. 1. "PADCONFIG72_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0xBC "CFG0_PADCONFIG73," bitfld.long 0xBC 31. "PADCONFIG73_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xBC 30. "PADCONFIG73_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xBC 29. "PADCONFIG73_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xBC 28. "PADCONFIG73_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xBC 27. "PADCONFIG73_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xBC 26. "PADCONFIG73_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xBC 25. "PADCONFIG73_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xBC 24. "PADCONFIG73_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xBC 23. "PADCONFIG73_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xBC 22. "PADCONFIG73_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xBC 21. "PADCONFIG73_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xBC 19.--20. "PADCONFIG73_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xBC 18. "PADCONFIG73_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xBC 17. "PADCONFIG73_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xBC 16. "PADCONFIG73_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xBC 15. "PADCONFIG73_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xBC 14. "PADCONFIG73_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xBC 11.--13. "PADCONFIG73_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xBC 8. "PADCONFIG73_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xBC 7. "PADCONFIG73_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xBC 4.--5. "PADCONFIG73_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xBC 0.--3. 1. "PADCONFIG73_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0xC0 "CFG0_PADCONFIG74," bitfld.long 0xC0 31. "PADCONFIG74_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xC0 30. "PADCONFIG74_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xC0 29. "PADCONFIG74_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xC0 28. "PADCONFIG74_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xC0 27. "PADCONFIG74_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xC0 26. "PADCONFIG74_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xC0 25. "PADCONFIG74_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xC0 24. "PADCONFIG74_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xC0 23. "PADCONFIG74_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC0 22. "PADCONFIG74_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC0 21. "PADCONFIG74_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xC0 19.--20. "PADCONFIG74_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC0 18. "PADCONFIG74_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xC0 17. "PADCONFIG74_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xC0 16. "PADCONFIG74_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xC0 15. "PADCONFIG74_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xC0 14. "PADCONFIG74_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xC0 11.--13. "PADCONFIG74_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 8. "PADCONFIG74_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xC0 7. "PADCONFIG74_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xC0 4.--5. "PADCONFIG74_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xC0 0.--3. 1. "PADCONFIG74_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0xC4 "CFG0_PADCONFIG75," bitfld.long 0xC4 31. "PADCONFIG75_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xC4 30. "PADCONFIG75_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xC4 29. "PADCONFIG75_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xC4 28. "PADCONFIG75_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xC4 27. "PADCONFIG75_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xC4 26. "PADCONFIG75_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xC4 25. "PADCONFIG75_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xC4 24. "PADCONFIG75_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xC4 23. "PADCONFIG75_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC4 22. "PADCONFIG75_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC4 21. "PADCONFIG75_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xC4 19.--20. "PADCONFIG75_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC4 18. "PADCONFIG75_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xC4 17. "PADCONFIG75_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xC4 16. "PADCONFIG75_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xC4 15. "PADCONFIG75_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xC4 14. "PADCONFIG75_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xC4 11.--13. "PADCONFIG75_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC4 8. "PADCONFIG75_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xC4 7. "PADCONFIG75_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xC4 4.--5. "PADCONFIG75_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xC4 0.--3. 1. "PADCONFIG75_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0xC8 "CFG0_PADCONFIG76," bitfld.long 0xC8 31. "PADCONFIG76_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xC8 30. "PADCONFIG76_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xC8 29. "PADCONFIG76_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xC8 28. "PADCONFIG76_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xC8 27. "PADCONFIG76_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xC8 26. "PADCONFIG76_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xC8 25. "PADCONFIG76_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xC8 24. "PADCONFIG76_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xC8 23. "PADCONFIG76_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC8 22. "PADCONFIG76_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC8 21. "PADCONFIG76_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xC8 19.--20. "PADCONFIG76_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC8 18. "PADCONFIG76_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xC8 17. "PADCONFIG76_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xC8 16. "PADCONFIG76_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xC8 15. "PADCONFIG76_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xC8 14. "PADCONFIG76_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xC8 11.--13. "PADCONFIG76_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 8. "PADCONFIG76_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xC8 7. "PADCONFIG76_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0xC8 4.--5. "PADCONFIG76_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xC8 0.--3. 1. "PADCONFIG76_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0xCC "CFG0_PADCONFIG77," bitfld.long 0xCC 31. "PADCONFIG77_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xCC 11.--13. "PADCONFIG77_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xCC 4.--5. "PADCONFIG77_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xD0 "CFG0_PADCONFIG78," bitfld.long 0xD0 31. "PADCONFIG78_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xD0 11.--13. "PADCONFIG78_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 4.--5. "PADCONFIG78_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xD4 "CFG0_PADCONFIG79," bitfld.long 0xD4 31. "PADCONFIG79_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xD4 11.--13. "PADCONFIG79_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD4 4.--5. "PADCONFIG79_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xD8 "CFG0_PADCONFIG80," bitfld.long 0xD8 31. "PADCONFIG80_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xD8 11.--13. "PADCONFIG80_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 4.--5. "PADCONFIG80_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xDC "CFG0_PADCONFIG81," bitfld.long 0xDC 31. "PADCONFIG81_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xDC 11.--13. "PADCONFIG81_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xDC 4.--5. "PADCONFIG81_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xE0 "CFG0_PADCONFIG82," bitfld.long 0xE0 31. "PADCONFIG82_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xE0 11.--13. "PADCONFIG82_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 4.--5. "PADCONFIG82_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xE4 "CFG0_PADCONFIG83," bitfld.long 0xE4 31. "PADCONFIG83_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xE4 11.--13. "PADCONFIG83_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE4 4.--5. "PADCONFIG83_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xE8 "CFG0_PADCONFIG84," bitfld.long 0xE8 31. "PADCONFIG84_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xE8 11.--13. "PADCONFIG84_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 4.--5. "PADCONFIG84_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xEC "CFG0_PADCONFIG85," bitfld.long 0xEC 31. "PADCONFIG85_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xEC 11.--13. "PADCONFIG85_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xEC 4.--5. "PADCONFIG85_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xF0 "CFG0_PADCONFIG86," bitfld.long 0xF0 31. "PADCONFIG86_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xF0 11.--13. "PADCONFIG86_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 4.--5. "PADCONFIG86_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xF4 "CFG0_PADCONFIG87," bitfld.long 0xF4 31. "PADCONFIG87_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xF4 11.--13. "PADCONFIG87_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF4 4.--5. "PADCONFIG87_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xF8 "CFG0_PADCONFIG88," bitfld.long 0xF8 31. "PADCONFIG88_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xF8 11.--13. "PADCONFIG88_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 4.--5. "PADCONFIG88_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xFC "CFG0_PADCONFIG89," bitfld.long 0xFC 31. "PADCONFIG89_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xFC 11.--13. "PADCONFIG89_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xFC 4.--5. "PADCONFIG89_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0x100 "CFG0_PADCONFIG90," bitfld.long 0x100 31. "PADCONFIG90_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0x100 11.--13. "PADCONFIG90_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x100 4.--5. "PADCONFIG90_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0x104 "CFG0_PADCONFIG91," bitfld.long 0x104 31. "PADCONFIG91_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0x104 11.--13. "PADCONFIG91_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x104 4.--5. "PADCONFIG91_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0x108 "CFG0_PADCONFIG92," bitfld.long 0x108 31. "PADCONFIG92_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0x108 11.--13. "PADCONFIG92_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x108 4.--5. "PADCONFIG92_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0x10C "CFG0_PADCONFIG93," bitfld.long 0x10C 31. "PADCONFIG93_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x10C 30. "PADCONFIG93_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x10C 29. "PADCONFIG93_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x10C 28. "PADCONFIG93_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x10C 27. "PADCONFIG93_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x10C 26. "PADCONFIG93_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x10C 25. "PADCONFIG93_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x10C 24. "PADCONFIG93_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x10C 23. "PADCONFIG93_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x10C 22. "PADCONFIG93_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x10C 21. "PADCONFIG93_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x10C 19.--20. "PADCONFIG93_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x10C 18. "PADCONFIG93_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x10C 17. "PADCONFIG93_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x10C 16. "PADCONFIG93_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x10C 15. "PADCONFIG93_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x10C 14. "PADCONFIG93_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x10C 11.--13. "PADCONFIG93_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10C 8. "PADCONFIG93_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x10C 7. "PADCONFIG93_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x10C 4.--5. "PADCONFIG93_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x10C 0.--3. 1. "PADCONFIG93_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x110 "CFG0_PADCONFIG94," bitfld.long 0x110 31. "PADCONFIG94_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x110 30. "PADCONFIG94_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x110 29. "PADCONFIG94_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x110 28. "PADCONFIG94_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x110 27. "PADCONFIG94_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x110 26. "PADCONFIG94_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x110 25. "PADCONFIG94_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x110 24. "PADCONFIG94_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x110 23. "PADCONFIG94_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x110 22. "PADCONFIG94_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x110 21. "PADCONFIG94_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x110 19.--20. "PADCONFIG94_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x110 18. "PADCONFIG94_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x110 17. "PADCONFIG94_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x110 16. "PADCONFIG94_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x110 15. "PADCONFIG94_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x110 14. "PADCONFIG94_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x110 11.--13. "PADCONFIG94_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x110 8. "PADCONFIG94_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x110 7. "PADCONFIG94_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x110 4.--5. "PADCONFIG94_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x110 0.--3. 1. "PADCONFIG94_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x114 "CFG0_PADCONFIG95," bitfld.long 0x114 31. "PADCONFIG95_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x114 30. "PADCONFIG95_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x114 29. "PADCONFIG95_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x114 28. "PADCONFIG95_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x114 27. "PADCONFIG95_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x114 26. "PADCONFIG95_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x114 25. "PADCONFIG95_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x114 24. "PADCONFIG95_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x114 23. "PADCONFIG95_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x114 22. "PADCONFIG95_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x114 21. "PADCONFIG95_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x114 19.--20. "PADCONFIG95_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x114 18. "PADCONFIG95_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x114 17. "PADCONFIG95_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x114 16. "PADCONFIG95_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x114 15. "PADCONFIG95_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x114 14. "PADCONFIG95_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x114 11.--13. "PADCONFIG95_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x114 8. "PADCONFIG95_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x114 7. "PADCONFIG95_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x114 4.--5. "PADCONFIG95_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x114 0.--3. 1. "PADCONFIG95_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x118 "CFG0_PADCONFIG96," bitfld.long 0x118 31. "PADCONFIG96_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x118 30. "PADCONFIG96_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x118 29. "PADCONFIG96_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x118 28. "PADCONFIG96_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x118 27. "PADCONFIG96_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x118 26. "PADCONFIG96_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x118 25. "PADCONFIG96_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x118 24. "PADCONFIG96_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x118 23. "PADCONFIG96_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x118 22. "PADCONFIG96_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x118 21. "PADCONFIG96_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x118 19.--20. "PADCONFIG96_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x118 18. "PADCONFIG96_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x118 17. "PADCONFIG96_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x118 16. "PADCONFIG96_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x118 15. "PADCONFIG96_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x118 14. "PADCONFIG96_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x118 11.--13. "PADCONFIG96_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x118 8. "PADCONFIG96_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x118 7. "PADCONFIG96_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x118 4.--5. "PADCONFIG96_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x118 0.--3. 1. "PADCONFIG96_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." line.long 0x11C "CFG0_PADCONFIG97," bitfld.long 0x11C 31. "PADCONFIG97_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x11C 30. "PADCONFIG97_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x11C 29. "PADCONFIG97_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x11C 28. "PADCONFIG97_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x11C 27. "PADCONFIG97_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x11C 26. "PADCONFIG97_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x11C 25. "PADCONFIG97_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x11C 24. "PADCONFIG97_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x11C 23. "PADCONFIG97_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x11C 22. "PADCONFIG97_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x11C 21. "PADCONFIG97_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x11C 19.--20. "PADCONFIG97_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x11C 18. "PADCONFIG97_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x11C 17. "PADCONFIG97_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x11C 16. "PADCONFIG97_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x11C 15. "PADCONFIG97_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x11C 14. "PADCONFIG97_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x11C 11.--13. "PADCONFIG97_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x11C 8. "PADCONFIG97_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x11C 7. "PADCONFIG97_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x11C 4.--5. "PADCONFIG97_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x11C 0.--3. 1. "PADCONFIG97_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." rgroup.long 0x1C190++0x3 line.long 0x0 "CFG0_PADCONFIG100," bitfld.long 0x0 31. "PADCONFIG100_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x0 30. "PADCONFIG100_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x0 29. "PADCONFIG100_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x0 28. "PADCONFIG100_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x0 27. "PADCONFIG100_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x0 26. "PADCONFIG100_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x0 25. "PADCONFIG100_DSOUT_DIS,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x0 24. "PADCONFIG100_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x0 23. "PADCONFIG100_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x0 22. "PADCONFIG100_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x0 21. "PADCONFIG100_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x0 19.--20. "PADCONFIG100_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x0 18. "PADCONFIG100_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x0 17. "PADCONFIG100_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x0 16. "PADCONFIG100_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x0 15. "PADCONFIG100_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x0 14. "PADCONFIG100_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x0 11.--13. "PADCONFIG100_DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "PADCONFIG100_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x0 7. "PADCONFIG100_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0: Disabled,1: Enabled" newline bitfld.long 0x0 4.--5. "PADCONFIG100_VGPIO_SEL,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "PADCONFIG100_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b -.." rgroup.long 0x1D008++0x7 line.long 0x0 "CFG0_LOCK7_KICK0," hexmask.long 0x0 0.--31. 1. "LOCK7_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK7_KICK1," hexmask.long 0x4 0.--31. 1. "LOCK7_KICK1,- KICK1 component" rgroup.long 0x1D100++0xF line.long 0x0 "CFG0_CLAIMREG_P7_R0_READONLY," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P7_R0_READONLY,Claim bits for Partition 7" line.long 0x4 "CFG0_CLAIMREG_P7_R1_READONLY," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P7_R1_READONLY,Claim bits for Partition 7" line.long 0x8 "CFG0_CLAIMREG_P7_R2_READONLY," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P7_R2_READONLY,Claim bits for Partition 7" line.long 0xC "CFG0_CLAIMREG_P7_R3_READONLY," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P7_R3_READONLY,Claim bits for Partition 7" rgroup.long 0x1E000++0x33 line.long 0x0 "CFG0_PADCONFIG0_PROXY," bitfld.long 0x0 31. "PADCONFIG0_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x0 30. "PADCONFIG0_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x0 29. "PADCONFIG0_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x0 28. "PADCONFIG0_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x0 27. "PADCONFIG0_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x0 26. "PADCONFIG0_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x0 25. "PADCONFIG0_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x0 24. "PADCONFIG0_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x0 23. "PADCONFIG0_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x0 22. "PADCONFIG0_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x0 21. "PADCONFIG0_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x0 19.--20. "PADCONFIG0_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x0 18. "PADCONFIG0_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x0 17. "PADCONFIG0_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x0 16. "PADCONFIG0_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x0 15. "PADCONFIG0_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x0 14. "PADCONFIG0_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x0 11.--13. "PADCONFIG0_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "PADCONFIG0_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x0 7. "PADCONFIG0_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x0 4.--5. "PADCONFIG0_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "PADCONFIG0_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b.." line.long 0x4 "CFG0_PADCONFIG1_PROXY," bitfld.long 0x4 31. "PADCONFIG1_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x4 30. "PADCONFIG1_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x4 29. "PADCONFIG1_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x4 28. "PADCONFIG1_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x4 27. "PADCONFIG1_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x4 26. "PADCONFIG1_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x4 25. "PADCONFIG1_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x4 24. "PADCONFIG1_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x4 23. "PADCONFIG1_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x4 22. "PADCONFIG1_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x4 21. "PADCONFIG1_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x4 19.--20. "PADCONFIG1_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4 18. "PADCONFIG1_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x4 17. "PADCONFIG1_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x4 16. "PADCONFIG1_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x4 15. "PADCONFIG1_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x4 14. "PADCONFIG1_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x4 11.--13. "PADCONFIG1_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8. "PADCONFIG1_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x4 7. "PADCONFIG1_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x4 4.--5. "PADCONFIG1_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "PADCONFIG1_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b.." line.long 0x8 "CFG0_PADCONFIG2_PROXY," bitfld.long 0x8 31. "PADCONFIG2_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x8 30. "PADCONFIG2_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x8 29. "PADCONFIG2_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x8 28. "PADCONFIG2_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x8 27. "PADCONFIG2_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x8 26. "PADCONFIG2_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x8 25. "PADCONFIG2_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x8 24. "PADCONFIG2_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x8 23. "PADCONFIG2_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x8 22. "PADCONFIG2_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x8 21. "PADCONFIG2_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x8 19.--20. "PADCONFIG2_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8 18. "PADCONFIG2_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x8 17. "PADCONFIG2_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x8 16. "PADCONFIG2_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x8 15. "PADCONFIG2_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x8 14. "PADCONFIG2_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x8 11.--13. "PADCONFIG2_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "PADCONFIG2_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x8 7. "PADCONFIG2_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x8 4.--5. "PADCONFIG2_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x8 0.--3. 1. "PADCONFIG2_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b.." line.long 0xC "CFG0_PADCONFIG3_PROXY," bitfld.long 0xC 31. "PADCONFIG3_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xC 30. "PADCONFIG3_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xC 29. "PADCONFIG3_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xC 28. "PADCONFIG3_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xC 27. "PADCONFIG3_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xC 26. "PADCONFIG3_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xC 25. "PADCONFIG3_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xC 24. "PADCONFIG3_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xC 23. "PADCONFIG3_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC 22. "PADCONFIG3_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC 21. "PADCONFIG3_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xC 19.--20. "PADCONFIG3_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC 18. "PADCONFIG3_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xC 17. "PADCONFIG3_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xC 16. "PADCONFIG3_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xC 15. "PADCONFIG3_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xC 14. "PADCONFIG3_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xC 11.--13. "PADCONFIG3_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "PADCONFIG3_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xC 7. "PADCONFIG3_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0xC 4.--5. "PADCONFIG3_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xC 0.--3. 1. "PADCONFIG3_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b.." line.long 0x10 "CFG0_PADCONFIG4_PROXY," bitfld.long 0x10 31. "PADCONFIG4_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x10 30. "PADCONFIG4_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x10 29. "PADCONFIG4_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x10 28. "PADCONFIG4_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x10 27. "PADCONFIG4_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x10 26. "PADCONFIG4_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x10 25. "PADCONFIG4_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x10 24. "PADCONFIG4_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x10 23. "PADCONFIG4_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x10 22. "PADCONFIG4_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x10 21. "PADCONFIG4_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x10 19.--20. "PADCONFIG4_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x10 18. "PADCONFIG4_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x10 17. "PADCONFIG4_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x10 16. "PADCONFIG4_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x10 15. "PADCONFIG4_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x10 14. "PADCONFIG4_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x10 11.--13. "PADCONFIG4_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "PADCONFIG4_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x10 7. "PADCONFIG4_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x10 4.--5. "PADCONFIG4_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x10 0.--3. 1. "PADCONFIG4_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b.." line.long 0x14 "CFG0_PADCONFIG5_PROXY," bitfld.long 0x14 31. "PADCONFIG5_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x14 30. "PADCONFIG5_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x14 29. "PADCONFIG5_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x14 28. "PADCONFIG5_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x14 27. "PADCONFIG5_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x14 26. "PADCONFIG5_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x14 25. "PADCONFIG5_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x14 24. "PADCONFIG5_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x14 23. "PADCONFIG5_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x14 22. "PADCONFIG5_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x14 21. "PADCONFIG5_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x14 19.--20. "PADCONFIG5_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x14 18. "PADCONFIG5_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x14 17. "PADCONFIG5_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x14 16. "PADCONFIG5_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x14 15. "PADCONFIG5_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x14 14. "PADCONFIG5_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x14 11.--13. "PADCONFIG5_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "PADCONFIG5_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x14 7. "PADCONFIG5_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x14 4.--5. "PADCONFIG5_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x14 0.--3. 1. "PADCONFIG5_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b.." line.long 0x18 "CFG0_PADCONFIG6_PROXY," bitfld.long 0x18 31. "PADCONFIG6_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x18 30. "PADCONFIG6_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x18 29. "PADCONFIG6_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x18 28. "PADCONFIG6_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x18 27. "PADCONFIG6_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x18 26. "PADCONFIG6_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x18 25. "PADCONFIG6_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x18 24. "PADCONFIG6_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x18 23. "PADCONFIG6_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x18 22. "PADCONFIG6_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x18 21. "PADCONFIG6_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x18 19.--20. "PADCONFIG6_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x18 18. "PADCONFIG6_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x18 17. "PADCONFIG6_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x18 16. "PADCONFIG6_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x18 15. "PADCONFIG6_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x18 14. "PADCONFIG6_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x18 11.--13. "PADCONFIG6_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8. "PADCONFIG6_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x18 7. "PADCONFIG6_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x18 4.--5. "PADCONFIG6_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x18 0.--3. 1. "PADCONFIG6_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b.." line.long 0x1C "CFG0_PADCONFIG7_PROXY," bitfld.long 0x1C 31. "PADCONFIG7_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x1C 30. "PADCONFIG7_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x1C 29. "PADCONFIG7_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x1C 28. "PADCONFIG7_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x1C 27. "PADCONFIG7_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x1C 26. "PADCONFIG7_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x1C 25. "PADCONFIG7_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x1C 24. "PADCONFIG7_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x1C 23. "PADCONFIG7_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x1C 22. "PADCONFIG7_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x1C 21. "PADCONFIG7_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x1C 19.--20. "PADCONFIG7_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1C 18. "PADCONFIG7_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x1C 17. "PADCONFIG7_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x1C 16. "PADCONFIG7_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x1C 15. "PADCONFIG7_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x1C 14. "PADCONFIG7_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x1C 11.--13. "PADCONFIG7_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "PADCONFIG7_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x1C 7. "PADCONFIG7_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x1C 4.--5. "PADCONFIG7_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x1C 0.--3. 1. "PADCONFIG7_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b.." line.long 0x20 "CFG0_PADCONFIG8_PROXY," bitfld.long 0x20 31. "PADCONFIG8_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x20 30. "PADCONFIG8_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x20 29. "PADCONFIG8_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x20 28. "PADCONFIG8_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x20 27. "PADCONFIG8_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x20 26. "PADCONFIG8_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x20 25. "PADCONFIG8_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x20 24. "PADCONFIG8_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x20 23. "PADCONFIG8_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x20 22. "PADCONFIG8_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x20 21. "PADCONFIG8_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x20 19.--20. "PADCONFIG8_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x20 18. "PADCONFIG8_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x20 17. "PADCONFIG8_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x20 16. "PADCONFIG8_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x20 15. "PADCONFIG8_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x20 14. "PADCONFIG8_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x20 11.--13. "PADCONFIG8_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 8. "PADCONFIG8_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x20 7. "PADCONFIG8_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x20 4.--5. "PADCONFIG8_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x20 0.--3. 1. "PADCONFIG8_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b.." line.long 0x24 "CFG0_PADCONFIG9_PROXY," bitfld.long 0x24 31. "PADCONFIG9_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x24 30. "PADCONFIG9_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x24 29. "PADCONFIG9_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x24 28. "PADCONFIG9_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x24 27. "PADCONFIG9_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x24 26. "PADCONFIG9_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x24 25. "PADCONFIG9_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x24 24. "PADCONFIG9_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x24 23. "PADCONFIG9_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x24 22. "PADCONFIG9_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x24 21. "PADCONFIG9_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x24 19.--20. "PADCONFIG9_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x24 18. "PADCONFIG9_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x24 17. "PADCONFIG9_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x24 16. "PADCONFIG9_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x24 15. "PADCONFIG9_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x24 14. "PADCONFIG9_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x24 11.--13. "PADCONFIG9_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 8. "PADCONFIG9_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x24 7. "PADCONFIG9_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x24 4.--5. "PADCONFIG9_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x24 0.--3. 1. "PADCONFIG9_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7 1111b.." line.long 0x28 "CFG0_PADCONFIG10_PROXY," bitfld.long 0x28 31. "PADCONFIG10_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x28 30. "PADCONFIG10_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x28 29. "PADCONFIG10_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x28 28. "PADCONFIG10_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x28 27. "PADCONFIG10_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x28 26. "PADCONFIG10_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x28 25. "PADCONFIG10_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x28 24. "PADCONFIG10_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x28 23. "PADCONFIG10_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x28 22. "PADCONFIG10_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x28 21. "PADCONFIG10_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x28 19.--20. "PADCONFIG10_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x28 18. "PADCONFIG10_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x28 17. "PADCONFIG10_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x28 16. "PADCONFIG10_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x28 15. "PADCONFIG10_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x28 14. "PADCONFIG10_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x28 11.--13. "PADCONFIG10_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8. "PADCONFIG10_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x28 7. "PADCONFIG10_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x28 4.--5. "PADCONFIG10_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x28 0.--3. 1. "PADCONFIG10_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x2C "CFG0_PADCONFIG11_PROXY," bitfld.long 0x2C 31. "PADCONFIG11_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x2C 30. "PADCONFIG11_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x2C 29. "PADCONFIG11_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x2C 28. "PADCONFIG11_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x2C 27. "PADCONFIG11_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x2C 26. "PADCONFIG11_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x2C 25. "PADCONFIG11_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x2C 24. "PADCONFIG11_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x2C 23. "PADCONFIG11_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x2C 22. "PADCONFIG11_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x2C 21. "PADCONFIG11_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x2C 19.--20. "PADCONFIG11_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x2C 18. "PADCONFIG11_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x2C 17. "PADCONFIG11_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x2C 16. "PADCONFIG11_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x2C 15. "PADCONFIG11_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x2C 14. "PADCONFIG11_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x2C 11.--13. "PADCONFIG11_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 8. "PADCONFIG11_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x2C 7. "PADCONFIG11_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x2C 4.--5. "PADCONFIG11_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x2C 0.--3. 1. "PADCONFIG11_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x30 "CFG0_PADCONFIG12_PROXY," bitfld.long 0x30 31. "PADCONFIG12_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x30 30. "PADCONFIG12_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x30 29. "PADCONFIG12_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x30 28. "PADCONFIG12_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x30 27. "PADCONFIG12_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x30 26. "PADCONFIG12_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x30 25. "PADCONFIG12_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x30 24. "PADCONFIG12_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x30 23. "PADCONFIG12_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x30 22. "PADCONFIG12_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x30 21. "PADCONFIG12_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x30 19.--20. "PADCONFIG12_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x30 18. "PADCONFIG12_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x30 17. "PADCONFIG12_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x30 16. "PADCONFIG12_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x30 15. "PADCONFIG12_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x30 14. "PADCONFIG12_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x30 11.--13. "PADCONFIG12_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 8. "PADCONFIG12_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x30 7. "PADCONFIG12_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x30 4.--5. "PADCONFIG12_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x30 0.--3. 1. "PADCONFIG12_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." rgroup.long 0x1E038++0x2B line.long 0x0 "CFG0_PADCONFIG14_PROXY," bitfld.long 0x0 31. "PADCONFIG14_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x0 30. "PADCONFIG14_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x0 29. "PADCONFIG14_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x0 28. "PADCONFIG14_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x0 27. "PADCONFIG14_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x0 26. "PADCONFIG14_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x0 25. "PADCONFIG14_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x0 24. "PADCONFIG14_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x0 23. "PADCONFIG14_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x0 22. "PADCONFIG14_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x0 21. "PADCONFIG14_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x0 19.--20. "PADCONFIG14_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x0 18. "PADCONFIG14_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x0 17. "PADCONFIG14_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x0 16. "PADCONFIG14_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x0 15. "PADCONFIG14_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x0 14. "PADCONFIG14_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x0 11.--13. "PADCONFIG14_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "PADCONFIG14_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x0 7. "PADCONFIG14_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x0 4.--5. "PADCONFIG14_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "PADCONFIG14_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x4 "CFG0_PADCONFIG15_PROXY," bitfld.long 0x4 31. "PADCONFIG15_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x4 30. "PADCONFIG15_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x4 29. "PADCONFIG15_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x4 28. "PADCONFIG15_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x4 27. "PADCONFIG15_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x4 26. "PADCONFIG15_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x4 25. "PADCONFIG15_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x4 24. "PADCONFIG15_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x4 23. "PADCONFIG15_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x4 22. "PADCONFIG15_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x4 21. "PADCONFIG15_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x4 19.--20. "PADCONFIG15_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4 18. "PADCONFIG15_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x4 17. "PADCONFIG15_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x4 16. "PADCONFIG15_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x4 15. "PADCONFIG15_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x4 14. "PADCONFIG15_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x4 11.--13. "PADCONFIG15_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8. "PADCONFIG15_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x4 7. "PADCONFIG15_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x4 4.--5. "PADCONFIG15_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "PADCONFIG15_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x8 "CFG0_PADCONFIG16_PROXY," bitfld.long 0x8 31. "PADCONFIG16_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x8 30. "PADCONFIG16_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x8 29. "PADCONFIG16_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x8 28. "PADCONFIG16_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x8 27. "PADCONFIG16_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x8 26. "PADCONFIG16_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x8 25. "PADCONFIG16_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x8 24. "PADCONFIG16_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x8 23. "PADCONFIG16_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x8 22. "PADCONFIG16_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x8 21. "PADCONFIG16_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x8 19.--20. "PADCONFIG16_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8 18. "PADCONFIG16_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x8 17. "PADCONFIG16_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x8 16. "PADCONFIG16_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x8 15. "PADCONFIG16_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x8 14. "PADCONFIG16_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x8 11.--13. "PADCONFIG16_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "PADCONFIG16_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x8 7. "PADCONFIG16_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x8 4.--5. "PADCONFIG16_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x8 0.--3. 1. "PADCONFIG16_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0xC "CFG0_PADCONFIG17_PROXY," bitfld.long 0xC 31. "PADCONFIG17_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xC 30. "PADCONFIG17_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xC 29. "PADCONFIG17_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xC 28. "PADCONFIG17_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xC 27. "PADCONFIG17_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xC 26. "PADCONFIG17_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xC 25. "PADCONFIG17_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xC 24. "PADCONFIG17_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xC 23. "PADCONFIG17_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC 22. "PADCONFIG17_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC 21. "PADCONFIG17_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xC 19.--20. "PADCONFIG17_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC 18. "PADCONFIG17_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xC 17. "PADCONFIG17_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xC 16. "PADCONFIG17_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xC 15. "PADCONFIG17_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xC 14. "PADCONFIG17_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xC 11.--13. "PADCONFIG17_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "PADCONFIG17_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xC 7. "PADCONFIG17_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0xC 4.--5. "PADCONFIG17_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xC 0.--3. 1. "PADCONFIG17_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x10 "CFG0_PADCONFIG18_PROXY," bitfld.long 0x10 31. "PADCONFIG18_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x10 30. "PADCONFIG18_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x10 29. "PADCONFIG18_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x10 28. "PADCONFIG18_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x10 27. "PADCONFIG18_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x10 26. "PADCONFIG18_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x10 25. "PADCONFIG18_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x10 24. "PADCONFIG18_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x10 23. "PADCONFIG18_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x10 22. "PADCONFIG18_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x10 21. "PADCONFIG18_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x10 19.--20. "PADCONFIG18_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x10 18. "PADCONFIG18_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x10 17. "PADCONFIG18_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x10 16. "PADCONFIG18_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x10 15. "PADCONFIG18_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x10 14. "PADCONFIG18_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x10 11.--13. "PADCONFIG18_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "PADCONFIG18_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x10 7. "PADCONFIG18_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x10 4.--5. "PADCONFIG18_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x10 0.--3. 1. "PADCONFIG18_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x14 "CFG0_PADCONFIG19_PROXY," bitfld.long 0x14 31. "PADCONFIG19_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x14 30. "PADCONFIG19_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x14 29. "PADCONFIG19_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x14 28. "PADCONFIG19_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x14 27. "PADCONFIG19_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x14 26. "PADCONFIG19_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x14 25. "PADCONFIG19_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x14 24. "PADCONFIG19_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x14 23. "PADCONFIG19_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x14 22. "PADCONFIG19_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x14 21. "PADCONFIG19_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x14 19.--20. "PADCONFIG19_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x14 18. "PADCONFIG19_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x14 17. "PADCONFIG19_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x14 16. "PADCONFIG19_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x14 15. "PADCONFIG19_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x14 14. "PADCONFIG19_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x14 11.--13. "PADCONFIG19_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "PADCONFIG19_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x14 7. "PADCONFIG19_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x14 4.--5. "PADCONFIG19_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x14 0.--3. 1. "PADCONFIG19_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x18 "CFG0_PADCONFIG20_PROXY," bitfld.long 0x18 31. "PADCONFIG20_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x18 30. "PADCONFIG20_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x18 29. "PADCONFIG20_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x18 28. "PADCONFIG20_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x18 27. "PADCONFIG20_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x18 26. "PADCONFIG20_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x18 25. "PADCONFIG20_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x18 24. "PADCONFIG20_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x18 23. "PADCONFIG20_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x18 22. "PADCONFIG20_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x18 21. "PADCONFIG20_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x18 19.--20. "PADCONFIG20_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x18 18. "PADCONFIG20_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x18 17. "PADCONFIG20_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x18 16. "PADCONFIG20_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x18 15. "PADCONFIG20_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x18 14. "PADCONFIG20_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x18 11.--13. "PADCONFIG20_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8. "PADCONFIG20_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x18 7. "PADCONFIG20_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x18 4.--5. "PADCONFIG20_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x18 0.--3. 1. "PADCONFIG20_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x1C "CFG0_PADCONFIG21_PROXY," bitfld.long 0x1C 31. "PADCONFIG21_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x1C 30. "PADCONFIG21_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x1C 29. "PADCONFIG21_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x1C 28. "PADCONFIG21_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x1C 27. "PADCONFIG21_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x1C 26. "PADCONFIG21_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x1C 25. "PADCONFIG21_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x1C 24. "PADCONFIG21_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x1C 23. "PADCONFIG21_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x1C 22. "PADCONFIG21_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x1C 21. "PADCONFIG21_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x1C 19.--20. "PADCONFIG21_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1C 18. "PADCONFIG21_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x1C 17. "PADCONFIG21_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x1C 16. "PADCONFIG21_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x1C 15. "PADCONFIG21_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x1C 14. "PADCONFIG21_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x1C 11.--13. "PADCONFIG21_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "PADCONFIG21_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x1C 7. "PADCONFIG21_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x1C 4.--5. "PADCONFIG21_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x1C 0.--3. 1. "PADCONFIG21_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x20 "CFG0_PADCONFIG22_PROXY," bitfld.long 0x20 31. "PADCONFIG22_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x20 30. "PADCONFIG22_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x20 29. "PADCONFIG22_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x20 28. "PADCONFIG22_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x20 27. "PADCONFIG22_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x20 26. "PADCONFIG22_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x20 25. "PADCONFIG22_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x20 24. "PADCONFIG22_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x20 23. "PADCONFIG22_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x20 22. "PADCONFIG22_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x20 21. "PADCONFIG22_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x20 19.--20. "PADCONFIG22_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x20 18. "PADCONFIG22_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x20 17. "PADCONFIG22_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x20 16. "PADCONFIG22_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x20 15. "PADCONFIG22_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x20 14. "PADCONFIG22_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x20 11.--13. "PADCONFIG22_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 8. "PADCONFIG22_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x20 7. "PADCONFIG22_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x20 4.--5. "PADCONFIG22_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x20 0.--3. 1. "PADCONFIG22_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x24 "CFG0_PADCONFIG23_PROXY," bitfld.long 0x24 31. "PADCONFIG23_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x24 30. "PADCONFIG23_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x24 29. "PADCONFIG23_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x24 28. "PADCONFIG23_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x24 27. "PADCONFIG23_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x24 26. "PADCONFIG23_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x24 25. "PADCONFIG23_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x24 24. "PADCONFIG23_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x24 23. "PADCONFIG23_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x24 22. "PADCONFIG23_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x24 21. "PADCONFIG23_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x24 19.--20. "PADCONFIG23_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x24 18. "PADCONFIG23_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x24 17. "PADCONFIG23_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x24 16. "PADCONFIG23_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x24 15. "PADCONFIG23_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x24 14. "PADCONFIG23_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x24 11.--13. "PADCONFIG23_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 8. "PADCONFIG23_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x24 7. "PADCONFIG23_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x24 4.--5. "PADCONFIG23_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x24 0.--3. 1. "PADCONFIG23_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x28 "CFG0_PADCONFIG24_PROXY," bitfld.long 0x28 31. "PADCONFIG24_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x28 30. "PADCONFIG24_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x28 29. "PADCONFIG24_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x28 28. "PADCONFIG24_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x28 27. "PADCONFIG24_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x28 26. "PADCONFIG24_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x28 25. "PADCONFIG24_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x28 24. "PADCONFIG24_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x28 23. "PADCONFIG24_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x28 22. "PADCONFIG24_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x28 21. "PADCONFIG24_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x28 19.--20. "PADCONFIG24_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x28 18. "PADCONFIG24_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x28 17. "PADCONFIG24_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x28 16. "PADCONFIG24_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x28 15. "PADCONFIG24_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x28 14. "PADCONFIG24_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x28 11.--13. "PADCONFIG24_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8. "PADCONFIG24_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x28 7. "PADCONFIG24_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x28 4.--5. "PADCONFIG24_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x28 0.--3. 1. "PADCONFIG24_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." rgroup.long 0x1E068++0x11F line.long 0x0 "CFG0_PADCONFIG26_PROXY," bitfld.long 0x0 31. "PADCONFIG26_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x0 30. "PADCONFIG26_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x0 29. "PADCONFIG26_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x0 28. "PADCONFIG26_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x0 27. "PADCONFIG26_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x0 26. "PADCONFIG26_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x0 25. "PADCONFIG26_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x0 24. "PADCONFIG26_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x0 23. "PADCONFIG26_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x0 22. "PADCONFIG26_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x0 21. "PADCONFIG26_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x0 19.--20. "PADCONFIG26_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x0 18. "PADCONFIG26_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x0 17. "PADCONFIG26_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x0 16. "PADCONFIG26_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x0 15. "PADCONFIG26_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x0 14. "PADCONFIG26_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x0 11.--13. "PADCONFIG26_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "PADCONFIG26_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x0 7. "PADCONFIG26_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x0 4.--5. "PADCONFIG26_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "PADCONFIG26_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x4 "CFG0_PADCONFIG27_PROXY," bitfld.long 0x4 31. "PADCONFIG27_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x4 30. "PADCONFIG27_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x4 29. "PADCONFIG27_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x4 28. "PADCONFIG27_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x4 27. "PADCONFIG27_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x4 26. "PADCONFIG27_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x4 25. "PADCONFIG27_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x4 24. "PADCONFIG27_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x4 23. "PADCONFIG27_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x4 22. "PADCONFIG27_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x4 21. "PADCONFIG27_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x4 19.--20. "PADCONFIG27_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4 18. "PADCONFIG27_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x4 17. "PADCONFIG27_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x4 16. "PADCONFIG27_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x4 15. "PADCONFIG27_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x4 14. "PADCONFIG27_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x4 11.--13. "PADCONFIG27_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8. "PADCONFIG27_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x4 7. "PADCONFIG27_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x4 4.--5. "PADCONFIG27_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x4 0.--3. 1. "PADCONFIG27_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x8 "CFG0_PADCONFIG28_PROXY," bitfld.long 0x8 31. "PADCONFIG28_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x8 30. "PADCONFIG28_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x8 29. "PADCONFIG28_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x8 28. "PADCONFIG28_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x8 27. "PADCONFIG28_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x8 26. "PADCONFIG28_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x8 25. "PADCONFIG28_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x8 24. "PADCONFIG28_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x8 23. "PADCONFIG28_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x8 22. "PADCONFIG28_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x8 21. "PADCONFIG28_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x8 19.--20. "PADCONFIG28_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8 18. "PADCONFIG28_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x8 17. "PADCONFIG28_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x8 16. "PADCONFIG28_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x8 15. "PADCONFIG28_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x8 14. "PADCONFIG28_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x8 11.--13. "PADCONFIG28_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "PADCONFIG28_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x8 7. "PADCONFIG28_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x8 4.--5. "PADCONFIG28_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x8 0.--3. 1. "PADCONFIG28_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0xC "CFG0_PADCONFIG29_PROXY," bitfld.long 0xC 31. "PADCONFIG29_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xC 30. "PADCONFIG29_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xC 29. "PADCONFIG29_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xC 28. "PADCONFIG29_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xC 27. "PADCONFIG29_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xC 26. "PADCONFIG29_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xC 25. "PADCONFIG29_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xC 24. "PADCONFIG29_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xC 23. "PADCONFIG29_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC 22. "PADCONFIG29_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC 21. "PADCONFIG29_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xC 19.--20. "PADCONFIG29_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC 18. "PADCONFIG29_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xC 17. "PADCONFIG29_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xC 16. "PADCONFIG29_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xC 15. "PADCONFIG29_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xC 14. "PADCONFIG29_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xC 11.--13. "PADCONFIG29_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "PADCONFIG29_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xC 7. "PADCONFIG29_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0xC 4.--5. "PADCONFIG29_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xC 0.--3. 1. "PADCONFIG29_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x10 "CFG0_PADCONFIG30_PROXY," bitfld.long 0x10 31. "PADCONFIG30_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x10 30. "PADCONFIG30_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x10 29. "PADCONFIG30_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x10 28. "PADCONFIG30_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x10 27. "PADCONFIG30_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x10 26. "PADCONFIG30_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x10 25. "PADCONFIG30_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x10 24. "PADCONFIG30_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x10 23. "PADCONFIG30_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x10 22. "PADCONFIG30_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x10 21. "PADCONFIG30_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x10 19.--20. "PADCONFIG30_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x10 18. "PADCONFIG30_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x10 17. "PADCONFIG30_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x10 16. "PADCONFIG30_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x10 15. "PADCONFIG30_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x10 14. "PADCONFIG30_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x10 11.--13. "PADCONFIG30_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "PADCONFIG30_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x10 7. "PADCONFIG30_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x10 4.--5. "PADCONFIG30_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x10 0.--3. 1. "PADCONFIG30_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x14 "CFG0_PADCONFIG31_PROXY," bitfld.long 0x14 31. "PADCONFIG31_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x14 30. "PADCONFIG31_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x14 29. "PADCONFIG31_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x14 28. "PADCONFIG31_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x14 27. "PADCONFIG31_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x14 26. "PADCONFIG31_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x14 25. "PADCONFIG31_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x14 24. "PADCONFIG31_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x14 23. "PADCONFIG31_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x14 22. "PADCONFIG31_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x14 21. "PADCONFIG31_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x14 19.--20. "PADCONFIG31_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x14 18. "PADCONFIG31_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x14 17. "PADCONFIG31_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x14 16. "PADCONFIG31_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x14 15. "PADCONFIG31_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x14 14. "PADCONFIG31_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x14 11.--13. "PADCONFIG31_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "PADCONFIG31_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x14 7. "PADCONFIG31_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x14 4.--5. "PADCONFIG31_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x14 0.--3. 1. "PADCONFIG31_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x18 "CFG0_PADCONFIG32_PROXY," bitfld.long 0x18 31. "PADCONFIG32_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x18 30. "PADCONFIG32_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x18 29. "PADCONFIG32_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x18 28. "PADCONFIG32_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x18 27. "PADCONFIG32_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x18 26. "PADCONFIG32_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x18 25. "PADCONFIG32_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x18 24. "PADCONFIG32_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x18 23. "PADCONFIG32_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x18 22. "PADCONFIG32_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x18 21. "PADCONFIG32_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x18 19.--20. "PADCONFIG32_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x18 18. "PADCONFIG32_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x18 17. "PADCONFIG32_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x18 16. "PADCONFIG32_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x18 15. "PADCONFIG32_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x18 14. "PADCONFIG32_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x18 11.--13. "PADCONFIG32_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8. "PADCONFIG32_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x18 7. "PADCONFIG32_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x18 4.--5. "PADCONFIG32_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x18 0.--3. 1. "PADCONFIG32_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x1C "CFG0_PADCONFIG33_PROXY," bitfld.long 0x1C 31. "PADCONFIG33_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x1C 30. "PADCONFIG33_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x1C 29. "PADCONFIG33_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x1C 28. "PADCONFIG33_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x1C 27. "PADCONFIG33_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x1C 26. "PADCONFIG33_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x1C 25. "PADCONFIG33_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x1C 24. "PADCONFIG33_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x1C 23. "PADCONFIG33_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x1C 22. "PADCONFIG33_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x1C 21. "PADCONFIG33_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x1C 19.--20. "PADCONFIG33_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1C 18. "PADCONFIG33_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x1C 17. "PADCONFIG33_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x1C 16. "PADCONFIG33_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x1C 15. "PADCONFIG33_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x1C 14. "PADCONFIG33_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x1C 11.--13. "PADCONFIG33_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "PADCONFIG33_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x1C 7. "PADCONFIG33_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x1C 4.--5. "PADCONFIG33_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x1C 0.--3. 1. "PADCONFIG33_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x20 "CFG0_PADCONFIG34_PROXY," bitfld.long 0x20 31. "PADCONFIG34_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x20 30. "PADCONFIG34_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x20 29. "PADCONFIG34_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x20 28. "PADCONFIG34_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x20 27. "PADCONFIG34_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x20 26. "PADCONFIG34_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x20 25. "PADCONFIG34_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x20 24. "PADCONFIG34_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x20 23. "PADCONFIG34_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x20 22. "PADCONFIG34_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x20 21. "PADCONFIG34_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x20 19.--20. "PADCONFIG34_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x20 18. "PADCONFIG34_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x20 17. "PADCONFIG34_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x20 16. "PADCONFIG34_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x20 15. "PADCONFIG34_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x20 14. "PADCONFIG34_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x20 11.--13. "PADCONFIG34_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 8. "PADCONFIG34_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x20 7. "PADCONFIG34_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x20 4.--5. "PADCONFIG34_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x20 0.--3. 1. "PADCONFIG34_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x24 "CFG0_PADCONFIG35_PROXY," bitfld.long 0x24 31. "PADCONFIG35_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x24 30. "PADCONFIG35_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x24 29. "PADCONFIG35_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x24 28. "PADCONFIG35_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x24 27. "PADCONFIG35_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x24 26. "PADCONFIG35_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x24 25. "PADCONFIG35_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x24 24. "PADCONFIG35_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x24 23. "PADCONFIG35_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x24 22. "PADCONFIG35_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x24 21. "PADCONFIG35_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x24 19.--20. "PADCONFIG35_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x24 18. "PADCONFIG35_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x24 17. "PADCONFIG35_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x24 16. "PADCONFIG35_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x24 15. "PADCONFIG35_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x24 14. "PADCONFIG35_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x24 11.--13. "PADCONFIG35_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 8. "PADCONFIG35_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x24 7. "PADCONFIG35_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x24 4.--5. "PADCONFIG35_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x24 0.--3. 1. "PADCONFIG35_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x28 "CFG0_PADCONFIG36_PROXY," bitfld.long 0x28 31. "PADCONFIG36_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x28 30. "PADCONFIG36_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x28 29. "PADCONFIG36_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x28 28. "PADCONFIG36_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x28 27. "PADCONFIG36_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x28 26. "PADCONFIG36_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x28 25. "PADCONFIG36_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x28 24. "PADCONFIG36_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x28 23. "PADCONFIG36_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x28 22. "PADCONFIG36_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x28 21. "PADCONFIG36_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x28 19.--20. "PADCONFIG36_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x28 18. "PADCONFIG36_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x28 17. "PADCONFIG36_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x28 16. "PADCONFIG36_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x28 15. "PADCONFIG36_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x28 14. "PADCONFIG36_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x28 11.--13. "PADCONFIG36_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8. "PADCONFIG36_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x28 7. "PADCONFIG36_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x28 4.--5. "PADCONFIG36_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x28 0.--3. 1. "PADCONFIG36_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x2C "CFG0_PADCONFIG37_PROXY," bitfld.long 0x2C 31. "PADCONFIG37_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x2C 30. "PADCONFIG37_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x2C 29. "PADCONFIG37_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x2C 28. "PADCONFIG37_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x2C 27. "PADCONFIG37_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x2C 26. "PADCONFIG37_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x2C 25. "PADCONFIG37_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x2C 24. "PADCONFIG37_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x2C 23. "PADCONFIG37_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x2C 22. "PADCONFIG37_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x2C 21. "PADCONFIG37_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x2C 19.--20. "PADCONFIG37_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x2C 18. "PADCONFIG37_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x2C 17. "PADCONFIG37_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x2C 16. "PADCONFIG37_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x2C 15. "PADCONFIG37_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x2C 14. "PADCONFIG37_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x2C 11.--13. "PADCONFIG37_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 8. "PADCONFIG37_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x2C 7. "PADCONFIG37_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x2C 4.--5. "PADCONFIG37_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x2C 0.--3. 1. "PADCONFIG37_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x30 "CFG0_PADCONFIG38_PROXY," bitfld.long 0x30 31. "PADCONFIG38_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x30 30. "PADCONFIG38_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x30 29. "PADCONFIG38_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x30 28. "PADCONFIG38_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x30 27. "PADCONFIG38_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x30 26. "PADCONFIG38_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x30 25. "PADCONFIG38_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x30 24. "PADCONFIG38_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x30 23. "PADCONFIG38_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x30 22. "PADCONFIG38_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x30 21. "PADCONFIG38_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x30 19.--20. "PADCONFIG38_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x30 18. "PADCONFIG38_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x30 17. "PADCONFIG38_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x30 16. "PADCONFIG38_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x30 15. "PADCONFIG38_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x30 14. "PADCONFIG38_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x30 11.--13. "PADCONFIG38_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 8. "PADCONFIG38_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x30 7. "PADCONFIG38_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x30 4.--5. "PADCONFIG38_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x30 0.--3. 1. "PADCONFIG38_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x34 "CFG0_PADCONFIG39_PROXY," bitfld.long 0x34 31. "PADCONFIG39_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x34 30. "PADCONFIG39_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x34 29. "PADCONFIG39_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x34 28. "PADCONFIG39_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x34 27. "PADCONFIG39_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x34 26. "PADCONFIG39_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x34 25. "PADCONFIG39_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x34 24. "PADCONFIG39_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x34 23. "PADCONFIG39_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x34 22. "PADCONFIG39_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x34 21. "PADCONFIG39_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x34 19.--20. "PADCONFIG39_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x34 18. "PADCONFIG39_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x34 17. "PADCONFIG39_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x34 16. "PADCONFIG39_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x34 15. "PADCONFIG39_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x34 14. "PADCONFIG39_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x34 11.--13. "PADCONFIG39_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 8. "PADCONFIG39_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x34 7. "PADCONFIG39_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x34 4.--5. "PADCONFIG39_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x34 0.--3. 1. "PADCONFIG39_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x38 "CFG0_PADCONFIG40_PROXY," bitfld.long 0x38 31. "PADCONFIG40_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x38 30. "PADCONFIG40_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x38 29. "PADCONFIG40_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x38 28. "PADCONFIG40_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x38 27. "PADCONFIG40_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x38 26. "PADCONFIG40_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x38 25. "PADCONFIG40_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x38 24. "PADCONFIG40_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x38 23. "PADCONFIG40_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x38 22. "PADCONFIG40_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x38 21. "PADCONFIG40_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x38 19.--20. "PADCONFIG40_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x38 18. "PADCONFIG40_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x38 17. "PADCONFIG40_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x38 16. "PADCONFIG40_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x38 15. "PADCONFIG40_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x38 14. "PADCONFIG40_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x38 11.--13. "PADCONFIG40_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 8. "PADCONFIG40_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x38 7. "PADCONFIG40_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x38 4.--5. "PADCONFIG40_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x38 0.--3. 1. "PADCONFIG40_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x3C "CFG0_PADCONFIG41_PROXY," bitfld.long 0x3C 31. "PADCONFIG41_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x3C 30. "PADCONFIG41_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x3C 29. "PADCONFIG41_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x3C 28. "PADCONFIG41_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x3C 27. "PADCONFIG41_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x3C 26. "PADCONFIG41_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x3C 25. "PADCONFIG41_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x3C 24. "PADCONFIG41_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x3C 23. "PADCONFIG41_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x3C 22. "PADCONFIG41_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x3C 21. "PADCONFIG41_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x3C 19.--20. "PADCONFIG41_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x3C 18. "PADCONFIG41_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x3C 17. "PADCONFIG41_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x3C 16. "PADCONFIG41_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x3C 15. "PADCONFIG41_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x3C 14. "PADCONFIG41_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x3C 11.--13. "PADCONFIG41_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x3C 8. "PADCONFIG41_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x3C 7. "PADCONFIG41_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x3C 4.--5. "PADCONFIG41_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x3C 0.--3. 1. "PADCONFIG41_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x40 "CFG0_PADCONFIG42_PROXY," bitfld.long 0x40 31. "PADCONFIG42_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x40 30. "PADCONFIG42_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x40 29. "PADCONFIG42_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x40 28. "PADCONFIG42_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x40 27. "PADCONFIG42_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x40 26. "PADCONFIG42_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x40 25. "PADCONFIG42_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x40 24. "PADCONFIG42_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x40 23. "PADCONFIG42_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x40 22. "PADCONFIG42_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x40 21. "PADCONFIG42_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x40 19.--20. "PADCONFIG42_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x40 18. "PADCONFIG42_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x40 17. "PADCONFIG42_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x40 16. "PADCONFIG42_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x40 15. "PADCONFIG42_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x40 14. "PADCONFIG42_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x40 11.--13. "PADCONFIG42_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 8. "PADCONFIG42_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x40 7. "PADCONFIG42_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x40 4.--5. "PADCONFIG42_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x40 0.--3. 1. "PADCONFIG42_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x44 "CFG0_PADCONFIG43_PROXY," bitfld.long 0x44 31. "PADCONFIG43_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x44 30. "PADCONFIG43_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x44 29. "PADCONFIG43_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x44 28. "PADCONFIG43_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x44 27. "PADCONFIG43_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x44 26. "PADCONFIG43_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x44 25. "PADCONFIG43_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x44 24. "PADCONFIG43_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x44 23. "PADCONFIG43_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x44 22. "PADCONFIG43_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x44 21. "PADCONFIG43_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x44 19.--20. "PADCONFIG43_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x44 18. "PADCONFIG43_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x44 17. "PADCONFIG43_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x44 16. "PADCONFIG43_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x44 15. "PADCONFIG43_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x44 14. "PADCONFIG43_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x44 11.--13. "PADCONFIG43_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x44 8. "PADCONFIG43_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x44 7. "PADCONFIG43_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x44 4.--5. "PADCONFIG43_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x44 0.--3. 1. "PADCONFIG43_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x48 "CFG0_PADCONFIG44_PROXY," bitfld.long 0x48 31. "PADCONFIG44_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x48 30. "PADCONFIG44_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x48 29. "PADCONFIG44_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x48 28. "PADCONFIG44_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x48 27. "PADCONFIG44_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x48 26. "PADCONFIG44_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x48 25. "PADCONFIG44_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x48 24. "PADCONFIG44_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x48 23. "PADCONFIG44_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x48 22. "PADCONFIG44_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x48 21. "PADCONFIG44_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x48 19.--20. "PADCONFIG44_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x48 18. "PADCONFIG44_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x48 17. "PADCONFIG44_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x48 16. "PADCONFIG44_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x48 15. "PADCONFIG44_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x48 14. "PADCONFIG44_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x48 11.--13. "PADCONFIG44_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 8. "PADCONFIG44_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x48 7. "PADCONFIG44_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x48 4.--5. "PADCONFIG44_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x48 0.--3. 1. "PADCONFIG44_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x4C "CFG0_PADCONFIG45_PROXY," bitfld.long 0x4C 31. "PADCONFIG45_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x4C 30. "PADCONFIG45_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x4C 29. "PADCONFIG45_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x4C 28. "PADCONFIG45_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x4C 27. "PADCONFIG45_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x4C 26. "PADCONFIG45_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x4C 25. "PADCONFIG45_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x4C 24. "PADCONFIG45_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x4C 23. "PADCONFIG45_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x4C 22. "PADCONFIG45_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x4C 21. "PADCONFIG45_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x4C 19.--20. "PADCONFIG45_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4C 18. "PADCONFIG45_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x4C 17. "PADCONFIG45_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x4C 16. "PADCONFIG45_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x4C 15. "PADCONFIG45_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x4C 14. "PADCONFIG45_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x4C 11.--13. "PADCONFIG45_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4C 8. "PADCONFIG45_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x4C 7. "PADCONFIG45_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x4C 4.--5. "PADCONFIG45_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x4C 0.--3. 1. "PADCONFIG45_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x50 "CFG0_PADCONFIG46_PROXY," bitfld.long 0x50 31. "PADCONFIG46_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x50 30. "PADCONFIG46_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x50 29. "PADCONFIG46_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x50 28. "PADCONFIG46_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x50 27. "PADCONFIG46_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x50 26. "PADCONFIG46_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x50 25. "PADCONFIG46_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x50 24. "PADCONFIG46_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x50 23. "PADCONFIG46_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x50 22. "PADCONFIG46_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x50 21. "PADCONFIG46_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x50 19.--20. "PADCONFIG46_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x50 18. "PADCONFIG46_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x50 17. "PADCONFIG46_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x50 16. "PADCONFIG46_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x50 15. "PADCONFIG46_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x50 14. "PADCONFIG46_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x50 11.--13. "PADCONFIG46_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 8. "PADCONFIG46_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x50 7. "PADCONFIG46_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x50 4.--5. "PADCONFIG46_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x50 0.--3. 1. "PADCONFIG46_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x54 "CFG0_PADCONFIG47_PROXY," bitfld.long 0x54 31. "PADCONFIG47_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x54 30. "PADCONFIG47_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x54 29. "PADCONFIG47_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x54 28. "PADCONFIG47_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x54 27. "PADCONFIG47_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x54 26. "PADCONFIG47_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x54 25. "PADCONFIG47_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x54 24. "PADCONFIG47_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x54 23. "PADCONFIG47_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x54 22. "PADCONFIG47_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x54 21. "PADCONFIG47_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x54 19.--20. "PADCONFIG47_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x54 18. "PADCONFIG47_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x54 17. "PADCONFIG47_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x54 16. "PADCONFIG47_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x54 15. "PADCONFIG47_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x54 14. "PADCONFIG47_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x54 11.--13. "PADCONFIG47_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x54 8. "PADCONFIG47_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x54 7. "PADCONFIG47_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x54 4.--5. "PADCONFIG47_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x54 0.--3. 1. "PADCONFIG47_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x58 "CFG0_PADCONFIG48_PROXY," bitfld.long 0x58 31. "PADCONFIG48_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x58 30. "PADCONFIG48_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x58 29. "PADCONFIG48_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x58 28. "PADCONFIG48_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x58 27. "PADCONFIG48_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x58 26. "PADCONFIG48_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x58 25. "PADCONFIG48_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x58 24. "PADCONFIG48_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x58 23. "PADCONFIG48_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x58 22. "PADCONFIG48_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x58 21. "PADCONFIG48_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x58 19.--20. "PADCONFIG48_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x58 18. "PADCONFIG48_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x58 17. "PADCONFIG48_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x58 16. "PADCONFIG48_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x58 15. "PADCONFIG48_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x58 14. "PADCONFIG48_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x58 11.--13. "PADCONFIG48_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 8. "PADCONFIG48_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x58 7. "PADCONFIG48_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x58 4.--5. "PADCONFIG48_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x58 0.--3. 1. "PADCONFIG48_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x5C "CFG0_PADCONFIG49_PROXY," bitfld.long 0x5C 31. "PADCONFIG49_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x5C 30. "PADCONFIG49_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x5C 29. "PADCONFIG49_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x5C 28. "PADCONFIG49_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x5C 27. "PADCONFIG49_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x5C 26. "PADCONFIG49_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x5C 25. "PADCONFIG49_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x5C 24. "PADCONFIG49_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x5C 23. "PADCONFIG49_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x5C 22. "PADCONFIG49_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x5C 21. "PADCONFIG49_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x5C 19.--20. "PADCONFIG49_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x5C 18. "PADCONFIG49_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x5C 17. "PADCONFIG49_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x5C 16. "PADCONFIG49_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x5C 15. "PADCONFIG49_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x5C 14. "PADCONFIG49_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x5C 11.--13. "PADCONFIG49_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x5C 8. "PADCONFIG49_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x5C 7. "PADCONFIG49_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x5C 4.--5. "PADCONFIG49_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x5C 0.--3. 1. "PADCONFIG49_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x60 "CFG0_PADCONFIG50_PROXY," bitfld.long 0x60 31. "PADCONFIG50_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x60 30. "PADCONFIG50_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x60 29. "PADCONFIG50_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x60 28. "PADCONFIG50_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x60 27. "PADCONFIG50_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x60 26. "PADCONFIG50_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x60 25. "PADCONFIG50_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x60 24. "PADCONFIG50_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x60 23. "PADCONFIG50_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x60 22. "PADCONFIG50_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x60 21. "PADCONFIG50_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x60 19.--20. "PADCONFIG50_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x60 18. "PADCONFIG50_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x60 17. "PADCONFIG50_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x60 16. "PADCONFIG50_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x60 15. "PADCONFIG50_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x60 14. "PADCONFIG50_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x60 11.--13. "PADCONFIG50_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 8. "PADCONFIG50_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x60 7. "PADCONFIG50_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x60 4.--5. "PADCONFIG50_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x60 0.--3. 1. "PADCONFIG50_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x64 "CFG0_PADCONFIG51_PROXY," bitfld.long 0x64 31. "PADCONFIG51_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x64 30. "PADCONFIG51_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x64 29. "PADCONFIG51_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x64 28. "PADCONFIG51_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x64 27. "PADCONFIG51_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x64 26. "PADCONFIG51_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x64 25. "PADCONFIG51_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x64 24. "PADCONFIG51_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x64 23. "PADCONFIG51_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x64 22. "PADCONFIG51_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x64 21. "PADCONFIG51_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x64 19.--20. "PADCONFIG51_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x64 18. "PADCONFIG51_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x64 17. "PADCONFIG51_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x64 16. "PADCONFIG51_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x64 15. "PADCONFIG51_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x64 14. "PADCONFIG51_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x64 11.--13. "PADCONFIG51_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x64 8. "PADCONFIG51_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x64 7. "PADCONFIG51_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x64 4.--5. "PADCONFIG51_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x64 0.--3. 1. "PADCONFIG51_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x68 "CFG0_PADCONFIG52_PROXY," bitfld.long 0x68 31. "PADCONFIG52_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x68 30. "PADCONFIG52_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x68 29. "PADCONFIG52_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x68 28. "PADCONFIG52_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x68 27. "PADCONFIG52_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x68 26. "PADCONFIG52_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x68 25. "PADCONFIG52_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x68 24. "PADCONFIG52_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x68 23. "PADCONFIG52_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x68 22. "PADCONFIG52_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x68 21. "PADCONFIG52_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x68 19.--20. "PADCONFIG52_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x68 18. "PADCONFIG52_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x68 17. "PADCONFIG52_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x68 16. "PADCONFIG52_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x68 15. "PADCONFIG52_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x68 14. "PADCONFIG52_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x68 11.--13. "PADCONFIG52_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 8. "PADCONFIG52_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x68 7. "PADCONFIG52_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x68 4.--5. "PADCONFIG52_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x68 0.--3. 1. "PADCONFIG52_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x6C "CFG0_PADCONFIG53_PROXY," bitfld.long 0x6C 31. "PADCONFIG53_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x6C 30. "PADCONFIG53_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x6C 29. "PADCONFIG53_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x6C 28. "PADCONFIG53_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x6C 27. "PADCONFIG53_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x6C 26. "PADCONFIG53_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x6C 25. "PADCONFIG53_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x6C 24. "PADCONFIG53_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x6C 23. "PADCONFIG53_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x6C 22. "PADCONFIG53_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x6C 21. "PADCONFIG53_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x6C 19.--20. "PADCONFIG53_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x6C 18. "PADCONFIG53_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x6C 17. "PADCONFIG53_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x6C 16. "PADCONFIG53_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x6C 15. "PADCONFIG53_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x6C 14. "PADCONFIG53_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x6C 11.--13. "PADCONFIG53_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x6C 8. "PADCONFIG53_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x6C 7. "PADCONFIG53_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x6C 4.--5. "PADCONFIG53_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x6C 0.--3. 1. "PADCONFIG53_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x70 "CFG0_PADCONFIG54_PROXY," bitfld.long 0x70 31. "PADCONFIG54_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x70 30. "PADCONFIG54_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x70 29. "PADCONFIG54_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x70 28. "PADCONFIG54_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x70 27. "PADCONFIG54_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x70 26. "PADCONFIG54_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x70 25. "PADCONFIG54_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x70 24. "PADCONFIG54_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x70 23. "PADCONFIG54_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x70 22. "PADCONFIG54_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x70 21. "PADCONFIG54_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x70 19.--20. "PADCONFIG54_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x70 18. "PADCONFIG54_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x70 17. "PADCONFIG54_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x70 16. "PADCONFIG54_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x70 15. "PADCONFIG54_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x70 14. "PADCONFIG54_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x70 11.--13. "PADCONFIG54_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 8. "PADCONFIG54_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x70 7. "PADCONFIG54_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x70 4.--5. "PADCONFIG54_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x70 0.--3. 1. "PADCONFIG54_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x74 "CFG0_PADCONFIG55_PROXY," bitfld.long 0x74 31. "PADCONFIG55_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x74 30. "PADCONFIG55_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x74 29. "PADCONFIG55_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x74 28. "PADCONFIG55_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x74 27. "PADCONFIG55_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x74 26. "PADCONFIG55_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x74 25. "PADCONFIG55_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x74 24. "PADCONFIG55_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x74 23. "PADCONFIG55_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x74 22. "PADCONFIG55_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x74 21. "PADCONFIG55_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x74 19.--20. "PADCONFIG55_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x74 18. "PADCONFIG55_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x74 17. "PADCONFIG55_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x74 16. "PADCONFIG55_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x74 15. "PADCONFIG55_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x74 14. "PADCONFIG55_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x74 11.--13. "PADCONFIG55_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x74 8. "PADCONFIG55_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x74 7. "PADCONFIG55_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x74 4.--5. "PADCONFIG55_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x74 0.--3. 1. "PADCONFIG55_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x78 "CFG0_PADCONFIG56_PROXY," bitfld.long 0x78 31. "PADCONFIG56_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x78 30. "PADCONFIG56_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x78 29. "PADCONFIG56_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x78 28. "PADCONFIG56_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x78 27. "PADCONFIG56_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x78 26. "PADCONFIG56_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x78 25. "PADCONFIG56_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x78 24. "PADCONFIG56_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x78 23. "PADCONFIG56_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x78 22. "PADCONFIG56_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x78 21. "PADCONFIG56_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x78 19.--20. "PADCONFIG56_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x78 18. "PADCONFIG56_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x78 17. "PADCONFIG56_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x78 16. "PADCONFIG56_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x78 15. "PADCONFIG56_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x78 14. "PADCONFIG56_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x78 11.--13. "PADCONFIG56_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 8. "PADCONFIG56_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x78 7. "PADCONFIG56_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x78 4.--5. "PADCONFIG56_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x78 0.--3. 1. "PADCONFIG56_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x7C "CFG0_PADCONFIG57_PROXY," bitfld.long 0x7C 31. "PADCONFIG57_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x7C 30. "PADCONFIG57_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x7C 29. "PADCONFIG57_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x7C 28. "PADCONFIG57_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x7C 27. "PADCONFIG57_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x7C 26. "PADCONFIG57_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x7C 25. "PADCONFIG57_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x7C 24. "PADCONFIG57_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x7C 23. "PADCONFIG57_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x7C 22. "PADCONFIG57_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x7C 21. "PADCONFIG57_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x7C 19.--20. "PADCONFIG57_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x7C 18. "PADCONFIG57_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x7C 17. "PADCONFIG57_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x7C 16. "PADCONFIG57_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x7C 15. "PADCONFIG57_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x7C 14. "PADCONFIG57_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x7C 11.--13. "PADCONFIG57_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x7C 8. "PADCONFIG57_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x7C 7. "PADCONFIG57_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x7C 4.--5. "PADCONFIG57_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x7C 0.--3. 1. "PADCONFIG57_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x80 "CFG0_PADCONFIG58_PROXY," bitfld.long 0x80 31. "PADCONFIG58_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x80 30. "PADCONFIG58_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x80 29. "PADCONFIG58_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x80 28. "PADCONFIG58_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x80 27. "PADCONFIG58_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x80 26. "PADCONFIG58_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x80 25. "PADCONFIG58_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x80 24. "PADCONFIG58_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x80 23. "PADCONFIG58_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x80 22. "PADCONFIG58_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x80 21. "PADCONFIG58_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x80 19.--20. "PADCONFIG58_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x80 18. "PADCONFIG58_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x80 17. "PADCONFIG58_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x80 16. "PADCONFIG58_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x80 15. "PADCONFIG58_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x80 14. "PADCONFIG58_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x80 11.--13. "PADCONFIG58_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 8. "PADCONFIG58_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x80 7. "PADCONFIG58_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x80 4.--5. "PADCONFIG58_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x80 0.--3. 1. "PADCONFIG58_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x84 "CFG0_PADCONFIG59_PROXY," bitfld.long 0x84 31. "PADCONFIG59_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x84 30. "PADCONFIG59_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x84 29. "PADCONFIG59_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x84 28. "PADCONFIG59_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x84 27. "PADCONFIG59_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x84 26. "PADCONFIG59_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x84 25. "PADCONFIG59_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x84 24. "PADCONFIG59_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x84 23. "PADCONFIG59_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x84 22. "PADCONFIG59_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x84 21. "PADCONFIG59_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x84 19.--20. "PADCONFIG59_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x84 18. "PADCONFIG59_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x84 17. "PADCONFIG59_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x84 16. "PADCONFIG59_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x84 15. "PADCONFIG59_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x84 14. "PADCONFIG59_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x84 11.--13. "PADCONFIG59_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x84 8. "PADCONFIG59_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x84 7. "PADCONFIG59_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x84 4.--5. "PADCONFIG59_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x84 0.--3. 1. "PADCONFIG59_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x88 "CFG0_PADCONFIG60_PROXY," bitfld.long 0x88 31. "PADCONFIG60_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x88 30. "PADCONFIG60_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x88 29. "PADCONFIG60_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x88 28. "PADCONFIG60_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x88 27. "PADCONFIG60_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x88 26. "PADCONFIG60_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x88 25. "PADCONFIG60_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x88 24. "PADCONFIG60_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x88 23. "PADCONFIG60_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x88 22. "PADCONFIG60_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x88 21. "PADCONFIG60_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x88 19.--20. "PADCONFIG60_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x88 18. "PADCONFIG60_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x88 17. "PADCONFIG60_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x88 16. "PADCONFIG60_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x88 15. "PADCONFIG60_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x88 14. "PADCONFIG60_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x88 11.--13. "PADCONFIG60_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 8. "PADCONFIG60_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x88 7. "PADCONFIG60_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x88 4.--5. "PADCONFIG60_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x88 0.--3. 1. "PADCONFIG60_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x8C "CFG0_PADCONFIG61_PROXY," bitfld.long 0x8C 31. "PADCONFIG61_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x8C 30. "PADCONFIG61_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x8C 29. "PADCONFIG61_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x8C 28. "PADCONFIG61_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x8C 27. "PADCONFIG61_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x8C 26. "PADCONFIG61_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x8C 25. "PADCONFIG61_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x8C 24. "PADCONFIG61_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x8C 23. "PADCONFIG61_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x8C 22. "PADCONFIG61_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x8C 21. "PADCONFIG61_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x8C 19.--20. "PADCONFIG61_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8C 18. "PADCONFIG61_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x8C 17. "PADCONFIG61_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x8C 16. "PADCONFIG61_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x8C 15. "PADCONFIG61_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x8C 14. "PADCONFIG61_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x8C 11.--13. "PADCONFIG61_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8C 8. "PADCONFIG61_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x8C 7. "PADCONFIG61_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x8C 4.--5. "PADCONFIG61_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x8C 0.--3. 1. "PADCONFIG61_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x90 "CFG0_PADCONFIG62_PROXY," bitfld.long 0x90 31. "PADCONFIG62_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x90 30. "PADCONFIG62_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x90 29. "PADCONFIG62_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x90 28. "PADCONFIG62_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x90 27. "PADCONFIG62_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x90 26. "PADCONFIG62_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x90 25. "PADCONFIG62_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x90 24. "PADCONFIG62_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x90 23. "PADCONFIG62_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x90 22. "PADCONFIG62_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x90 21. "PADCONFIG62_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x90 19.--20. "PADCONFIG62_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x90 18. "PADCONFIG62_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x90 17. "PADCONFIG62_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x90 16. "PADCONFIG62_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x90 15. "PADCONFIG62_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x90 14. "PADCONFIG62_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x90 11.--13. "PADCONFIG62_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 8. "PADCONFIG62_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x90 7. "PADCONFIG62_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x90 4.--5. "PADCONFIG62_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x90 0.--3. 1. "PADCONFIG62_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x94 "CFG0_PADCONFIG63_PROXY," bitfld.long 0x94 31. "PADCONFIG63_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x94 30. "PADCONFIG63_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x94 29. "PADCONFIG63_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x94 28. "PADCONFIG63_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x94 27. "PADCONFIG63_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x94 26. "PADCONFIG63_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x94 25. "PADCONFIG63_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x94 24. "PADCONFIG63_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x94 23. "PADCONFIG63_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x94 22. "PADCONFIG63_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x94 21. "PADCONFIG63_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x94 19.--20. "PADCONFIG63_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x94 18. "PADCONFIG63_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x94 17. "PADCONFIG63_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x94 16. "PADCONFIG63_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x94 15. "PADCONFIG63_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x94 14. "PADCONFIG63_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x94 11.--13. "PADCONFIG63_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x94 8. "PADCONFIG63_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x94 7. "PADCONFIG63_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x94 4.--5. "PADCONFIG63_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x94 0.--3. 1. "PADCONFIG63_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x98 "CFG0_PADCONFIG64_PROXY," bitfld.long 0x98 31. "PADCONFIG64_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x98 30. "PADCONFIG64_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x98 29. "PADCONFIG64_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x98 26. "PADCONFIG64_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x98 25. "PADCONFIG64_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x98 24. "PADCONFIG64_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x98 23. "PADCONFIG64_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x98 22. "PADCONFIG64_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x98 21. "PADCONFIG64_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x98 18. "PADCONFIG64_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x98 15. "PADCONFIG64_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x98 14. "PADCONFIG64_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x98 11.--13. "PADCONFIG64_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 8. "PADCONFIG64_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x98 7. "PADCONFIG64_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x98 4.--5. "PADCONFIG64_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x98 0.--3. 1. "PADCONFIG64_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x9C "CFG0_PADCONFIG65_PROXY," bitfld.long 0x9C 31. "PADCONFIG65_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x9C 30. "PADCONFIG65_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x9C 29. "PADCONFIG65_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x9C 26. "PADCONFIG65_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x9C 25. "PADCONFIG65_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x9C 24. "PADCONFIG65_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x9C 23. "PADCONFIG65_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x9C 22. "PADCONFIG65_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x9C 21. "PADCONFIG65_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x9C 18. "PADCONFIG65_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x9C 15. "PADCONFIG65_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x9C 14. "PADCONFIG65_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x9C 11.--13. "PADCONFIG65_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x9C 8. "PADCONFIG65_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x9C 7. "PADCONFIG65_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x9C 4.--5. "PADCONFIG65_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x9C 0.--3. 1. "PADCONFIG65_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0xA0 "CFG0_PADCONFIG66_PROXY," bitfld.long 0xA0 31. "PADCONFIG66_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xA0 30. "PADCONFIG66_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xA0 29. "PADCONFIG66_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xA0 26. "PADCONFIG66_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xA0 25. "PADCONFIG66_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xA0 24. "PADCONFIG66_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xA0 23. "PADCONFIG66_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xA0 22. "PADCONFIG66_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xA0 21. "PADCONFIG66_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xA0 18. "PADCONFIG66_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xA0 15. "PADCONFIG66_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xA0 14. "PADCONFIG66_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xA0 11.--13. "PADCONFIG66_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 8. "PADCONFIG66_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xA0 7. "PADCONFIG66_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0xA0 4.--5. "PADCONFIG66_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xA0 0.--3. 1. "PADCONFIG66_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0xA4 "CFG0_PADCONFIG67_PROXY," bitfld.long 0xA4 31. "PADCONFIG67_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xA4 30. "PADCONFIG67_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xA4 29. "PADCONFIG67_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xA4 26. "PADCONFIG67_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xA4 25. "PADCONFIG67_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xA4 24. "PADCONFIG67_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xA4 23. "PADCONFIG67_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xA4 22. "PADCONFIG67_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xA4 21. "PADCONFIG67_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xA4 18. "PADCONFIG67_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xA4 15. "PADCONFIG67_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xA4 14. "PADCONFIG67_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xA4 11.--13. "PADCONFIG67_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA4 8. "PADCONFIG67_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xA4 7. "PADCONFIG67_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0xA4 4.--5. "PADCONFIG67_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xA4 0.--3. 1. "PADCONFIG67_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0xA8 "CFG0_PADCONFIG68_PROXY," bitfld.long 0xA8 31. "PADCONFIG68_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xA8 30. "PADCONFIG68_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xA8 29. "PADCONFIG68_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xA8 28. "PADCONFIG68_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xA8 27. "PADCONFIG68_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xA8 26. "PADCONFIG68_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xA8 25. "PADCONFIG68_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xA8 24. "PADCONFIG68_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xA8 23. "PADCONFIG68_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xA8 22. "PADCONFIG68_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xA8 21. "PADCONFIG68_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xA8 19.--20. "PADCONFIG68_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xA8 18. "PADCONFIG68_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xA8 17. "PADCONFIG68_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xA8 16. "PADCONFIG68_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xA8 15. "PADCONFIG68_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xA8 14. "PADCONFIG68_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xA8 11.--13. "PADCONFIG68_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 8. "PADCONFIG68_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xA8 7. "PADCONFIG68_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0xA8 4.--5. "PADCONFIG68_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xA8 0.--3. 1. "PADCONFIG68_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0xAC "CFG0_PADCONFIG69_PROXY," bitfld.long 0xAC 31. "PADCONFIG69_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xAC 30. "PADCONFIG69_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xAC 29. "PADCONFIG69_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xAC 28. "PADCONFIG69_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xAC 27. "PADCONFIG69_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xAC 26. "PADCONFIG69_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xAC 25. "PADCONFIG69_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xAC 24. "PADCONFIG69_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xAC 23. "PADCONFIG69_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xAC 22. "PADCONFIG69_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xAC 21. "PADCONFIG69_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xAC 19.--20. "PADCONFIG69_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xAC 18. "PADCONFIG69_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xAC 17. "PADCONFIG69_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xAC 16. "PADCONFIG69_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xAC 15. "PADCONFIG69_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xAC 14. "PADCONFIG69_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xAC 11.--13. "PADCONFIG69_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xAC 8. "PADCONFIG69_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xAC 7. "PADCONFIG69_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0xAC 4.--5. "PADCONFIG69_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xAC 0.--3. 1. "PADCONFIG69_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0xB0 "CFG0_PADCONFIG70_PROXY," bitfld.long 0xB0 31. "PADCONFIG70_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xB0 30. "PADCONFIG70_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xB0 29. "PADCONFIG70_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xB0 28. "PADCONFIG70_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xB0 27. "PADCONFIG70_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xB0 26. "PADCONFIG70_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xB0 25. "PADCONFIG70_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xB0 24. "PADCONFIG70_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xB0 23. "PADCONFIG70_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xB0 22. "PADCONFIG70_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xB0 21. "PADCONFIG70_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xB0 19.--20. "PADCONFIG70_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB0 18. "PADCONFIG70_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xB0 17. "PADCONFIG70_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xB0 16. "PADCONFIG70_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xB0 15. "PADCONFIG70_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xB0 14. "PADCONFIG70_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xB0 11.--13. "PADCONFIG70_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 8. "PADCONFIG70_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xB0 7. "PADCONFIG70_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0xB0 4.--5. "PADCONFIG70_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xB0 0.--3. 1. "PADCONFIG70_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0xB4 "CFG0_PADCONFIG71_PROXY," bitfld.long 0xB4 31. "PADCONFIG71_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xB4 30. "PADCONFIG71_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xB4 29. "PADCONFIG71_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xB4 28. "PADCONFIG71_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xB4 27. "PADCONFIG71_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xB4 26. "PADCONFIG71_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xB4 25. "PADCONFIG71_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xB4 24. "PADCONFIG71_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xB4 23. "PADCONFIG71_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xB4 22. "PADCONFIG71_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xB4 21. "PADCONFIG71_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xB4 19.--20. "PADCONFIG71_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB4 18. "PADCONFIG71_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xB4 17. "PADCONFIG71_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xB4 16. "PADCONFIG71_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xB4 15. "PADCONFIG71_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xB4 14. "PADCONFIG71_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xB4 11.--13. "PADCONFIG71_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB4 8. "PADCONFIG71_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xB4 7. "PADCONFIG71_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0xB4 4.--5. "PADCONFIG71_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xB4 0.--3. 1. "PADCONFIG71_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0xB8 "CFG0_PADCONFIG72_PROXY," bitfld.long 0xB8 31. "PADCONFIG72_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xB8 30. "PADCONFIG72_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xB8 29. "PADCONFIG72_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xB8 28. "PADCONFIG72_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xB8 27. "PADCONFIG72_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xB8 26. "PADCONFIG72_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xB8 25. "PADCONFIG72_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xB8 24. "PADCONFIG72_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xB8 23. "PADCONFIG72_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xB8 22. "PADCONFIG72_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xB8 21. "PADCONFIG72_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xB8 19.--20. "PADCONFIG72_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB8 18. "PADCONFIG72_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xB8 17. "PADCONFIG72_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xB8 16. "PADCONFIG72_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xB8 15. "PADCONFIG72_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xB8 14. "PADCONFIG72_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xB8 11.--13. "PADCONFIG72_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 8. "PADCONFIG72_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xB8 7. "PADCONFIG72_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0xB8 4.--5. "PADCONFIG72_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xB8 0.--3. 1. "PADCONFIG72_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0xBC "CFG0_PADCONFIG73_PROXY," bitfld.long 0xBC 31. "PADCONFIG73_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xBC 30. "PADCONFIG73_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xBC 29. "PADCONFIG73_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xBC 28. "PADCONFIG73_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xBC 27. "PADCONFIG73_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xBC 26. "PADCONFIG73_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xBC 25. "PADCONFIG73_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xBC 24. "PADCONFIG73_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xBC 23. "PADCONFIG73_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xBC 22. "PADCONFIG73_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xBC 21. "PADCONFIG73_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xBC 19.--20. "PADCONFIG73_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xBC 18. "PADCONFIG73_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xBC 17. "PADCONFIG73_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xBC 16. "PADCONFIG73_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xBC 15. "PADCONFIG73_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xBC 14. "PADCONFIG73_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xBC 11.--13. "PADCONFIG73_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xBC 8. "PADCONFIG73_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xBC 7. "PADCONFIG73_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0xBC 4.--5. "PADCONFIG73_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xBC 0.--3. 1. "PADCONFIG73_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0xC0 "CFG0_PADCONFIG74_PROXY," bitfld.long 0xC0 31. "PADCONFIG74_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xC0 30. "PADCONFIG74_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xC0 29. "PADCONFIG74_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xC0 28. "PADCONFIG74_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xC0 27. "PADCONFIG74_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xC0 26. "PADCONFIG74_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xC0 25. "PADCONFIG74_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xC0 24. "PADCONFIG74_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xC0 23. "PADCONFIG74_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC0 22. "PADCONFIG74_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC0 21. "PADCONFIG74_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xC0 19.--20. "PADCONFIG74_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC0 18. "PADCONFIG74_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xC0 17. "PADCONFIG74_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xC0 16. "PADCONFIG74_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xC0 15. "PADCONFIG74_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xC0 14. "PADCONFIG74_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xC0 11.--13. "PADCONFIG74_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 8. "PADCONFIG74_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xC0 7. "PADCONFIG74_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0xC0 4.--5. "PADCONFIG74_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xC0 0.--3. 1. "PADCONFIG74_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0xC4 "CFG0_PADCONFIG75_PROXY," bitfld.long 0xC4 31. "PADCONFIG75_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xC4 30. "PADCONFIG75_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xC4 29. "PADCONFIG75_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xC4 28. "PADCONFIG75_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xC4 27. "PADCONFIG75_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xC4 26. "PADCONFIG75_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xC4 25. "PADCONFIG75_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xC4 24. "PADCONFIG75_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xC4 23. "PADCONFIG75_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC4 22. "PADCONFIG75_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC4 21. "PADCONFIG75_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xC4 19.--20. "PADCONFIG75_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC4 18. "PADCONFIG75_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xC4 17. "PADCONFIG75_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xC4 16. "PADCONFIG75_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xC4 15. "PADCONFIG75_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xC4 14. "PADCONFIG75_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xC4 11.--13. "PADCONFIG75_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC4 8. "PADCONFIG75_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xC4 7. "PADCONFIG75_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0xC4 4.--5. "PADCONFIG75_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xC4 0.--3. 1. "PADCONFIG75_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0xC8 "CFG0_PADCONFIG76_PROXY," bitfld.long 0xC8 31. "PADCONFIG76_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0xC8 30. "PADCONFIG76_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0xC8 29. "PADCONFIG76_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0xC8 28. "PADCONFIG76_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0xC8 27. "PADCONFIG76_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0xC8 26. "PADCONFIG76_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0xC8 25. "PADCONFIG76_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0xC8 24. "PADCONFIG76_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0xC8 23. "PADCONFIG76_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC8 22. "PADCONFIG76_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0xC8 21. "PADCONFIG76_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0xC8 19.--20. "PADCONFIG76_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC8 18. "PADCONFIG76_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0xC8 17. "PADCONFIG76_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0xC8 16. "PADCONFIG76_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0xC8 15. "PADCONFIG76_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0xC8 14. "PADCONFIG76_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0xC8 11.--13. "PADCONFIG76_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 8. "PADCONFIG76_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0xC8 7. "PADCONFIG76_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0xC8 4.--5. "PADCONFIG76_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0xC8 0.--3. 1. "PADCONFIG76_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0xCC "CFG0_PADCONFIG77_PROXY," bitfld.long 0xCC 31. "PADCONFIG77_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xCC 11.--13. "PADCONFIG77_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xCC 4.--5. "PADCONFIG77_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xD0 "CFG0_PADCONFIG78_PROXY," bitfld.long 0xD0 31. "PADCONFIG78_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xD0 11.--13. "PADCONFIG78_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 4.--5. "PADCONFIG78_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xD4 "CFG0_PADCONFIG79_PROXY," bitfld.long 0xD4 31. "PADCONFIG79_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xD4 11.--13. "PADCONFIG79_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD4 4.--5. "PADCONFIG79_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xD8 "CFG0_PADCONFIG80_PROXY," bitfld.long 0xD8 31. "PADCONFIG80_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xD8 11.--13. "PADCONFIG80_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 4.--5. "PADCONFIG80_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xDC "CFG0_PADCONFIG81_PROXY," bitfld.long 0xDC 31. "PADCONFIG81_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xDC 11.--13. "PADCONFIG81_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xDC 4.--5. "PADCONFIG81_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xE0 "CFG0_PADCONFIG82_PROXY," bitfld.long 0xE0 31. "PADCONFIG82_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xE0 11.--13. "PADCONFIG82_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 4.--5. "PADCONFIG82_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xE4 "CFG0_PADCONFIG83_PROXY," bitfld.long 0xE4 31. "PADCONFIG83_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xE4 11.--13. "PADCONFIG83_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE4 4.--5. "PADCONFIG83_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xE8 "CFG0_PADCONFIG84_PROXY," bitfld.long 0xE8 31. "PADCONFIG84_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xE8 11.--13. "PADCONFIG84_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 4.--5. "PADCONFIG84_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xEC "CFG0_PADCONFIG85_PROXY," bitfld.long 0xEC 31. "PADCONFIG85_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xEC 11.--13. "PADCONFIG85_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xEC 4.--5. "PADCONFIG85_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xF0 "CFG0_PADCONFIG86_PROXY," bitfld.long 0xF0 31. "PADCONFIG86_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xF0 11.--13. "PADCONFIG86_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 4.--5. "PADCONFIG86_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xF4 "CFG0_PADCONFIG87_PROXY," bitfld.long 0xF4 31. "PADCONFIG87_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xF4 11.--13. "PADCONFIG87_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF4 4.--5. "PADCONFIG87_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xF8 "CFG0_PADCONFIG88_PROXY," bitfld.long 0xF8 31. "PADCONFIG88_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xF8 11.--13. "PADCONFIG88_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 4.--5. "PADCONFIG88_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0xFC "CFG0_PADCONFIG89_PROXY," bitfld.long 0xFC 31. "PADCONFIG89_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0xFC 11.--13. "PADCONFIG89_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xFC 4.--5. "PADCONFIG89_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0x100 "CFG0_PADCONFIG90_PROXY," bitfld.long 0x100 31. "PADCONFIG90_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0x100 11.--13. "PADCONFIG90_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x100 4.--5. "PADCONFIG90_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0x104 "CFG0_PADCONFIG91_PROXY," bitfld.long 0x104 31. "PADCONFIG91_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0x104 11.--13. "PADCONFIG91_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x104 4.--5. "PADCONFIG91_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0x108 "CFG0_PADCONFIG92_PROXY," bitfld.long 0x108 31. "PADCONFIG92_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline bitfld.long 0x108 11.--13. "PADCONFIG92_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x108 4.--5. "PADCONFIG92_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected.." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" line.long 0x10C "CFG0_PADCONFIG93_PROXY," bitfld.long 0x10C 31. "PADCONFIG93_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x10C 30. "PADCONFIG93_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x10C 29. "PADCONFIG93_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x10C 28. "PADCONFIG93_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x10C 27. "PADCONFIG93_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x10C 26. "PADCONFIG93_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x10C 25. "PADCONFIG93_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x10C 24. "PADCONFIG93_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x10C 23. "PADCONFIG93_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x10C 22. "PADCONFIG93_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x10C 21. "PADCONFIG93_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x10C 19.--20. "PADCONFIG93_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x10C 18. "PADCONFIG93_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x10C 17. "PADCONFIG93_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x10C 16. "PADCONFIG93_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x10C 15. "PADCONFIG93_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x10C 14. "PADCONFIG93_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x10C 11.--13. "PADCONFIG93_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10C 8. "PADCONFIG93_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x10C 7. "PADCONFIG93_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x10C 4.--5. "PADCONFIG93_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x10C 0.--3. 1. "PADCONFIG93_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x110 "CFG0_PADCONFIG94_PROXY," bitfld.long 0x110 31. "PADCONFIG94_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x110 30. "PADCONFIG94_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x110 29. "PADCONFIG94_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x110 28. "PADCONFIG94_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x110 27. "PADCONFIG94_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x110 26. "PADCONFIG94_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x110 25. "PADCONFIG94_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x110 24. "PADCONFIG94_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x110 23. "PADCONFIG94_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x110 22. "PADCONFIG94_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x110 21. "PADCONFIG94_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x110 19.--20. "PADCONFIG94_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x110 18. "PADCONFIG94_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x110 17. "PADCONFIG94_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x110 16. "PADCONFIG94_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x110 15. "PADCONFIG94_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x110 14. "PADCONFIG94_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x110 11.--13. "PADCONFIG94_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x110 8. "PADCONFIG94_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x110 7. "PADCONFIG94_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x110 4.--5. "PADCONFIG94_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x110 0.--3. 1. "PADCONFIG94_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x114 "CFG0_PADCONFIG95_PROXY," bitfld.long 0x114 31. "PADCONFIG95_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x114 30. "PADCONFIG95_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x114 29. "PADCONFIG95_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x114 28. "PADCONFIG95_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x114 27. "PADCONFIG95_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x114 26. "PADCONFIG95_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x114 25. "PADCONFIG95_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x114 24. "PADCONFIG95_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x114 23. "PADCONFIG95_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x114 22. "PADCONFIG95_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x114 21. "PADCONFIG95_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x114 19.--20. "PADCONFIG95_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x114 18. "PADCONFIG95_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x114 17. "PADCONFIG95_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x114 16. "PADCONFIG95_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x114 15. "PADCONFIG95_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x114 14. "PADCONFIG95_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x114 11.--13. "PADCONFIG95_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x114 8. "PADCONFIG95_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x114 7. "PADCONFIG95_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x114 4.--5. "PADCONFIG95_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x114 0.--3. 1. "PADCONFIG95_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x118 "CFG0_PADCONFIG96_PROXY," bitfld.long 0x118 31. "PADCONFIG96_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x118 30. "PADCONFIG96_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x118 29. "PADCONFIG96_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x118 28. "PADCONFIG96_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x118 27. "PADCONFIG96_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x118 26. "PADCONFIG96_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x118 25. "PADCONFIG96_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x118 24. "PADCONFIG96_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x118 23. "PADCONFIG96_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x118 22. "PADCONFIG96_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x118 21. "PADCONFIG96_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x118 19.--20. "PADCONFIG96_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x118 18. "PADCONFIG96_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x118 17. "PADCONFIG96_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x118 16. "PADCONFIG96_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x118 15. "PADCONFIG96_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x118 14. "PADCONFIG96_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x118 11.--13. "PADCONFIG96_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x118 8. "PADCONFIG96_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x118 7. "PADCONFIG96_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x118 4.--5. "PADCONFIG96_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x118 0.--3. 1. "PADCONFIG96_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." line.long 0x11C "CFG0_PADCONFIG97_PROXY," bitfld.long 0x11C 31. "PADCONFIG97_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x11C 30. "PADCONFIG97_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x11C 29. "PADCONFIG97_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x11C 28. "PADCONFIG97_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x11C 27. "PADCONFIG97_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x11C 26. "PADCONFIG97_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x11C 25. "PADCONFIG97_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x11C 24. "PADCONFIG97_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x11C 23. "PADCONFIG97_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x11C 22. "PADCONFIG97_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x11C 21. "PADCONFIG97_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x11C 19.--20. "PADCONFIG97_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x11C 18. "PADCONFIG97_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x11C 17. "PADCONFIG97_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x11C 16. "PADCONFIG97_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x11C 15. "PADCONFIG97_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x11C 14. "PADCONFIG97_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x11C 11.--13. "PADCONFIG97_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x11C 8. "PADCONFIG97_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x11C 7. "PADCONFIG97_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x11C 4.--5. "PADCONFIG97_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x11C 0.--3. 1. "PADCONFIG97_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." rgroup.long 0x1E190++0x3 line.long 0x0 "CFG0_PADCONFIG100_PROXY," bitfld.long 0x0 31. "PADCONFIG100_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0: Padconfig register is unlocked 1,?" newline rbitfld.long 0x0 30. "PADCONFIG100_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0: No wake event on pin 1,?" newline bitfld.long 0x0 29. "PADCONFIG100_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0: Wakeup operation disabled 1,?" newline bitfld.long 0x0 28. "PADCONFIG100_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0: Offmode pulldown selected 1,?" newline bitfld.long 0x0 27. "PADCONFIG100_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0: Pullup / pulldown is enabled 1,?" newline bitfld.long 0x0 26. "PADCONFIG100_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0: Output value is 0 1,?" newline bitfld.long 0x0 25. "PADCONFIG100_DSOUT_DIS_PROXY,Deep Sleep output enable 0 - Output enabled 1 - Output disabled" "0: Output enabled 1,?" newline bitfld.long 0x0 24. "PADCONFIG100_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep is active 1 - IO state is forced to OFF mode value when Deep Sleep is active" "0: IO keeps its previous state when Deep Sleep is..,?" newline bitfld.long 0x0 23. "PADCONFIG100_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0: IO isolation is preserved 1,?" newline bitfld.long 0x0 22. "PADCONFIG100_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0: IO isolation is preserved 1,?" newline bitfld.long 0x0 21. "PADCONFIG100_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0: Driver is enabled 1,?" newline bitfld.long 0x0 19.--20. "PADCONFIG100_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x0 18. "PADCONFIG100_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0: Receiver disabled 1,?" newline bitfld.long 0x0 17. "PADCONFIG100_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0: Pulldown selected 1,?" newline bitfld.long 0x0 16. "PADCONFIG100_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0: Pullup / Pulldown enabled 1,?" newline bitfld.long 0x0 15. "PADCONFIG100_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding SMS gating 0 - Deep Sleep pad controls are gated by the SMS 1 - Activate Deep Sleep pad controls (override SMS gating logic)" "0: Deep Sleep pad controls are gated by the SMS 1,?" newline bitfld.long 0x0 14. "PADCONFIG100_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0: Schmitt trigger input disabled 1,?" newline bitfld.long 0x0 11.--13. "PADCONFIG100_DEBOUNCE_SEL_PROXY,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "PADCONFIG100_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0: Low,1: High" newline bitfld.long 0x0 7. "PADCONFIG100_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0: Disabled,1: Enabled" newline bitfld.long 0x0 4.--5. "PADCONFIG100_VGPIO_SEL_PROXY,Virtual WKUP_GPIO instance select. These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7).." "0: Implement GPIO in GPIO_WKUP_0 instance 2'b01,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "PADCONFIG100_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 0000b - Mux Mode 0 0001b - Mux Mode 1 0010b - Mux Mode 2 0011b - Mux Mode 3 0100b - Mux Mode 4 0101b - Mux Mode 5 0110b - Mux Mode 6 0111b - Mux Mode 7.." rgroup.long 0x1F008++0x7 line.long 0x0 "CFG0_LOCK7_KICK0_PROXY," hexmask.long 0x0 0.--31. 1. "LOCK7_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK7_KICK1_PROXY," hexmask.long 0x4 0.--31. 1. "LOCK7_KICK1_PROXY,- KICK1 component" rgroup.long 0x1F100++0xF line.long 0x0 "CFG0_CLAIMREG_P7_R0," hexmask.long 0x0 0.--31. 1. "CLAIMREG_P7_R0,Claim bits for Partition 7" line.long 0x4 "CFG0_CLAIMREG_P7_R1," hexmask.long 0x4 0.--31. 1. "CLAIMREG_P7_R1,Claim bits for Partition 7" line.long 0x8 "CFG0_CLAIMREG_P7_R2," hexmask.long 0x8 0.--31. 1. "CLAIMREG_P7_R2,Claim bits for Partition 7" line.long 0xC "CFG0_CLAIMREG_P7_R3," hexmask.long 0xC 0.--31. 1. "CLAIMREG_P7_R3,Claim bits for Partition 7" tree.end tree "WKUP_ECC_AGGR0_REGS (WKUP_ECC_AGGR0_REGS)" base ad:0x42410000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" rgroup.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" rgroup.long 0x3C++0xB line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 30. "IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_PEND,Interrupt Pending Status for Iwku_cor_data_vbusp_32b_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x4 29. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_9_PEND,Interrupt Pending Status for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_9_pend" "0,1" newline bitfld.long 0x4 28. "IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_PEND,Interrupt Pending Status for Iwku_cor_data_vbusp_32b_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x4 27. "IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_PEND,Interrupt Pending Status for Iwku_cor_data_vbusp_32b_infra_safeg_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_PEND,Interrupt Pending Status for Iwku_cor_data_vbusp_32b_infra_safeg_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 25. "IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_PEND,Interrupt Pending Status for Iwku_cor_data_vbusp_32b_infra_safeg_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 24. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 23. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_PEND,Interrupt Pending Status for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_wkup_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_wkup_mcu_sysclk0_6_busecc_1_pend" "0,1" newline bitfld.long 0x4 20. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IJ7AM_WAKEUP_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7AM_WAKEUP_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_CBASS_DEFAULT_ERR_J7AM_WKUP_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_cbass_default_err_j7am_wkup_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 15. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_CBASS_DEFAULT_MMRS_J7AM_WKUP_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_cbass_default_mmrs_j7am_wkup_cbass_cbass_default_mmrs_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 14. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ERR_SCR_J7AM_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_err_scr_j7am_wkup_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 13. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 10. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_PEND,Interrupt Pending Status for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_wkup_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_wkup_mcu_sysclk0_3_busecc_pend" "0,1" newline bitfld.long 0x4 9. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 8. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7AM_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_cbass_int_dmsc_scr_j7am_wkup_cbass_cbass_int_dmsc_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 7. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IJ7AM_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 6. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_PEND,Interrupt Pending Status for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_wkup_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_wkup_mcu_sysclk0_6_busecc_0_pend" "0,1" newline bitfld.long 0x4 5. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IJ7AM_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 4. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 3. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ISMS_WKUP_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_WKUP_0_TIFS_VBUSP_S_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 2. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ISMS_WKUP_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_WKUP_0_HSM_VBUSP_S_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 1. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 0. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" line.long 0x8 "REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 13. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x8 12. "EFUSE_PARITY_CHAIN1_BUSECC_PEND,Interrupt Pending Status for efuse_parity_chain1_busecc_pend" "0,1" newline bitfld.long 0x8 11. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_ERR_SCR_J7AM_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7_wkup_fw_cbass_wkup_0_j7am_wkup_fw_cbass_err_scr_j7am_wkup_fw_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 10. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7_wkup_fw_cbass_wkup_0_j7am_wkup_fw_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 9. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_CBASS_DEFAULT_ERR_J7AM_WKUP_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7AM_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_8_PEND,Interrupt Pending Status for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_8_pend" "0,1" newline bitfld.long 0x8 6. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_PEND,Interrupt Pending Status for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_7_pend" "0,1" newline bitfld.long 0x8 5. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_PEND,Interrupt Pending Status for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_6_pend" "0,1" newline bitfld.long 0x8 4. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_PEND,Interrupt Pending Status for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_5_pend" "0,1" newline bitfld.long 0x8 3. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 2. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 1. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 0. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_1_pend" "0,1" rgroup.long 0x80++0x7 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x0 30. "IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Iwku_cor_data_vbusp_32b_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 29. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_9_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_9_pend" "0,1" newline bitfld.long 0x0 28. "IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Iwku_cor_data_vbusp_32b_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 27. "IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Iwku_cor_data_vbusp_32b_infra_safeg_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Iwku_cor_data_vbusp_32b_infra_safeg_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Iwku_cor_data_vbusp_32b_infra_safeg_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 24. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 23. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IJ7AM_WAKEUP_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7AM_WAKEUP_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_CBASS_DEFAULT_ERR_J7AM_WKUP_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_CBASS_DEFAULT_MMRS_J7AM_WKUP_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ERR_SCR_J7AM_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_err_scr_j7am_wkup_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 13. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 10. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 9. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 8. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7AM_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 7. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IJ7AM_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 6. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 5. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IJ7AM_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 4. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ISMS_WKUP_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_WKUP_0_TIFS_VBUSP_S_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 2. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ISMS_WKUP_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_WKUP_0_HSM_VBUSP_S_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 1. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 0. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" line.long 0x4 "REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 13. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x4 12. "EFUSE_PARITY_CHAIN1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for efuse_parity_chain1_busecc_pend" "0,1" newline bitfld.long 0x4 11. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_ERR_SCR_J7AM_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7_wkup_fw_cbass_wkup_0_j7am_wkup_fw_cbass_err_scr_j7am_wkup_fw_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7_wkup_fw_cbass_wkup_0_j7am_wkup_fw_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 9. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_CBASS_DEFAULT_ERR_J7AM_WKUP_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7AM_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_8_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_8_pend" "0,1" newline bitfld.long 0x4 6. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_7_pend" "0,1" newline bitfld.long 0x4 5. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_6_pend" "0,1" newline bitfld.long 0x4 4. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_5_pend" "0,1" newline bitfld.long 0x4 3. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 2. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 1. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 0. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_1_pend" "0,1" rgroup.long 0xC0++0x7 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x0 30. "IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Iwku_cor_data_vbusp_32b_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 29. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_9_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_9_pend" "0,1" newline bitfld.long 0x0 28. "IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Iwku_cor_data_vbusp_32b_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 27. "IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Iwku_cor_data_vbusp_32b_infra_safeg_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Iwku_cor_data_vbusp_32b_infra_safeg_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Iwku_cor_data_vbusp_32b_infra_safeg_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 24. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 23. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IJ7AM_WAKEUP_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7AM_WAKEUP_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_CBASS_DEFAULT_ERR_J7AM_WKUP_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_CBASS_DEFAULT_MMRS_J7AM_WKUP_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ERR_SCR_J7AM_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_err_scr_j7am_wkup_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 13. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 10. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 9. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 8. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7AM_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 7. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IJ7AM_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 6. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 5. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IJ7AM_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 4. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ISMS_WKUP_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_WKUP_0_TIFS_VBUSP_S_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 2. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ISMS_WKUP_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_WKUP_0_HSM_VBUSP_S_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 1. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 0. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" line.long 0x4 "REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 13. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x4 12. "EFUSE_PARITY_CHAIN1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for efuse_parity_chain1_busecc_pend" "0,1" newline bitfld.long 0x4 11. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_ERR_SCR_J7AM_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7_wkup_fw_cbass_wkup_0_j7am_wkup_fw_cbass_err_scr_j7am_wkup_fw_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7_wkup_fw_cbass_wkup_0_j7am_wkup_fw_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 9. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_CBASS_DEFAULT_ERR_J7AM_WKUP_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7AM_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_8_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_8_pend" "0,1" newline bitfld.long 0x4 6. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_7_pend" "0,1" newline bitfld.long 0x4 5. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_6_pend" "0,1" newline bitfld.long 0x4 4. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_5_pend" "0,1" newline bitfld.long 0x4 3. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 2. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 1. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 0. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_1_pend" "0,1" rgroup.long 0x13C++0xB line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 30. "IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_PEND,Interrupt Pending Status for Iwku_cor_data_vbusp_32b_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x4 29. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_9_PEND,Interrupt Pending Status for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_9_pend" "0,1" newline bitfld.long 0x4 28. "IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_PEND,Interrupt Pending Status for Iwku_cor_data_vbusp_32b_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x4 27. "IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_PEND,Interrupt Pending Status for Iwku_cor_data_vbusp_32b_infra_safeg_wr_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_PEND,Interrupt Pending Status for Iwku_cor_data_vbusp_32b_infra_safeg_rd_ramecc_pend" "0,1" newline bitfld.long 0x4 25. "IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_PEND,Interrupt Pending Status for Iwku_cor_data_vbusp_32b_infra_safeg_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 24. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 23. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 22. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 21. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_PEND,Interrupt Pending Status for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_wkup_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_wkup_mcu_sysclk0_6_busecc_1_pend" "0,1" newline bitfld.long 0x4 20. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 19. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 18. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 17. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IJ7AM_WAKEUP_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7AM_WAKEUP_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 16. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_CBASS_DEFAULT_ERR_J7AM_WKUP_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_cbass_default_err_j7am_wkup_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 15. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_CBASS_DEFAULT_MMRS_J7AM_WKUP_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_cbass_default_mmrs_j7am_wkup_cbass_cbass_default_mmrs_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 14. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ERR_SCR_J7AM_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_err_scr_j7am_wkup_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 13. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 12. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 11. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 10. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_PEND,Interrupt Pending Status for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_wkup_mcu_sysclk0_3_clk_edc_ctrl_cbass_int_wkup_mcu_sysclk0_3_busecc_pend" "0,1" newline bitfld.long 0x4 9. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 8. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7AM_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_cbass_int_dmsc_scr_j7am_wkup_cbass_cbass_int_dmsc_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 7. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IJ7AM_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 6. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_PEND,Interrupt Pending Status for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_wkup_mcu_sysclk0_6_clk_edc_ctrl_cbass_int_wkup_mcu_sysclk0_6_busecc_0_pend" "0,1" newline bitfld.long 0x4 5. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IJ7AM_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 4. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 3. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ISMS_WKUP_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_WKUP_0_TIFS_VBUSP_S_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 2. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ISMS_WKUP_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_WKUP_0_HSM_VBUSP_S_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 1. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 0. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" line.long 0x8 "REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 13. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" newline bitfld.long 0x8 12. "EFUSE_PARITY_CHAIN1_BUSECC_PEND,Interrupt Pending Status for efuse_parity_chain1_busecc_pend" "0,1" newline bitfld.long 0x8 11. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_ERR_SCR_J7AM_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for j7_wkup_fw_cbass_wkup_0_j7am_wkup_fw_cbass_err_scr_j7am_wkup_fw_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 10. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for j7_wkup_fw_cbass_wkup_0_j7am_wkup_fw_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 9. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_CBASS_DEFAULT_ERR_J7AM_WKUP_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 8. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7AM_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x8 7. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_8_PEND,Interrupt Pending Status for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_8_pend" "0,1" newline bitfld.long 0x8 6. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_PEND,Interrupt Pending Status for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_7_pend" "0,1" newline bitfld.long 0x8 5. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_PEND,Interrupt Pending Status for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_6_pend" "0,1" newline bitfld.long 0x8 4. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_PEND,Interrupt Pending Status for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_5_pend" "0,1" newline bitfld.long 0x8 3. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x8 2. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x8 1. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 0. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_1_pend" "0,1" rgroup.long 0x180++0x7 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x0 30. "IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for Iwku_cor_data_vbusp_32b_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 29. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_9_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_9_pend" "0,1" newline bitfld.long 0x0 28. "IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for Iwku_cor_data_vbusp_32b_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 27. "IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Iwku_cor_data_vbusp_32b_infra_safeg_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Iwku_cor_data_vbusp_32b_infra_safeg_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for Iwku_cor_data_vbusp_32b_infra_safeg_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 24. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 23. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 22. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 21. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 20. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 19. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 18. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 17. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IJ7AM_WAKEUP_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7AM_WAKEUP_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 16. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_CBASS_DEFAULT_ERR_J7AM_WKUP_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 15. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_CBASS_DEFAULT_MMRS_J7AM_WKUP_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 14. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ERR_SCR_J7AM_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_err_scr_j7am_wkup_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 13. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 12. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 11. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 10. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 9. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 8. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7AM_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 7. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IJ7AM_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 6. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 5. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IJ7AM_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 4. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ISMS_WKUP_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_WKUP_0_TIFS_VBUSP_S_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 2. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ISMS_WKUP_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_WKUP_0_HSM_VBUSP_S_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 1. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 0. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" line.long 0x4 "REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 13. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" newline bitfld.long 0x4 12. "EFUSE_PARITY_CHAIN1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for efuse_parity_chain1_busecc_pend" "0,1" newline bitfld.long 0x4 11. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_ERR_SCR_J7AM_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7_wkup_fw_cbass_wkup_0_j7am_wkup_fw_cbass_err_scr_j7am_wkup_fw_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for j7_wkup_fw_cbass_wkup_0_j7am_wkup_fw_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 9. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_CBASS_DEFAULT_ERR_J7AM_WKUP_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 8. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7AM_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x4 7. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_8_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_8_pend" "0,1" newline bitfld.long 0x4 6. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_7_pend" "0,1" newline bitfld.long 0x4 5. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_6_pend" "0,1" newline bitfld.long 0x4 4. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_5_pend" "0,1" newline bitfld.long 0x4 3. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 2. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 1. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 0. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_1_pend" "0,1" rgroup.long 0x1C0++0x7 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x0 30. "IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for Iwku_cor_data_vbusp_32b_src_p2m_src_busecc_pend" "0,1" newline bitfld.long 0x0 29. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_9_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_9_pend" "0,1" newline bitfld.long 0x0 28. "IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for Iwku_cor_data_vbusp_32b_m2m_src_vbuss_pend" "0,1" newline bitfld.long 0x0 27. "IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Iwku_cor_data_vbusp_32b_infra_safeg_wr_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Iwku_cor_data_vbusp_32b_infra_safeg_rd_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for Iwku_cor_data_vbusp_32b_infra_safeg_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 24. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 23. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 22. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 21. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 20. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 19. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_P2M_BRIDGE_EXPORT_J7AM_WKUP_TO_MCU_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 18. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 17. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IJ7AM_WAKEUP_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7AM_WAKEUP_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 16. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_CBASS_DEFAULT_ERR_J7AM_WKUP_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 15. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_CBASS_DEFAULT_MMRS_J7AM_WKUP_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 14. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ERR_SCR_J7AM_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_err_scr_j7am_wkup_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 13. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 12. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_M2P_BRIDGE_EXPORT_J7AM_MCU_TO_WKUP_VBUSM_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 11. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_P2P_BRIDGE_EXPORT_J7AM_WKUP_TO_MAIN_INFRA_VBUSP_L0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 10. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 9. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 8. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7AM_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 7. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IJ7AM_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 6. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 5. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IJ7AM_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7AM_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 4. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_cbass_wkup_0_j7am_wkup_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 3. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ISMS_WKUP_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_WKUP_0_TIFS_VBUSP_S_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 2. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_ISMS_WKUP_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_WKUP_0_HSM_VBUSP_S_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 1. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7AM_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 0. "J7AM_WKUP_CBASS_WKUP_0_J7AM_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" line.long 0x4 "REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 13. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" newline bitfld.long 0x4 12. "EFUSE_PARITY_CHAIN1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for efuse_parity_chain1_busecc_pend" "0,1" newline bitfld.long 0x4 11. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_ERR_SCR_J7AM_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7_wkup_fw_cbass_wkup_0_j7am_wkup_fw_cbass_err_scr_j7am_wkup_fw_cbass_err_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 10. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for j7_wkup_fw_cbass_wkup_0_j7am_wkup_fw_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 9. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_CBASS_DEFAULT_ERR_J7AM_WKUP_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 8. "J7_WKUP_FW_CBASS_WKUP_0_J7AM_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7AM_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x4 7. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_8_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_8_pend" "0,1" newline bitfld.long 0x4 6. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_7_pend" "0,1" newline bitfld.long 0x4 5. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_6_pend" "0,1" newline bitfld.long 0x4 4. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_5_pend" "0,1" newline bitfld.long 0x4 3. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_4_pend" "0,1" newline bitfld.long 0x4 2. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_3_pend" "0,1" newline bitfld.long 0x4 1. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 0. "J7AM_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for j7am_wkup_ctrl_mmr_edc_ctrl_busecc_1_pend" "0,1" rgroup.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "WKUP_ESM0_CFG (WKUP_ESM0_CFG)" base ad:0x42080000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "CFG_INFO,The Info Register gives the configuration Inforrmation of this ESM." bitfld.long 0x4 31. "LAST_RESET,Indicates the Source of the last Reset" "0,1" hexmask.long.byte 0x4 8.--15. 1. "PULSE_GROUPS,Number of Pulse Error Groups" hexmask.long.byte 0x4 0.--7. 1. "GROUPS,Total number of Error Groups" rgroup.long 0x8++0x3 line.long 0x0 "CFG_EN,The Global Enable Register has the master interrupt mask" hexmask.long.byte 0x0 0.--3. 1. "KEY,Global Enable" rgroup.long 0xC++0x3 line.long 0x0 "CFG_SFT_RST,The Global Soft Reset Register controls the global clear for raw status and enables" hexmask.long.byte 0x0 0.--3. 1. "KEY,Global Soft Reset" rgroup.long 0x10++0xF line.long 0x0 "CFG_ERR_RAW,Raw Status/Set Register for Configuration Errors" hexmask.long.byte 0x0 0.--3. 1. "STS,This is the raw status for config errors" line.long 0x4 "CFG_ERR_STS,Config Error Enable and Clear Register" hexmask.long.byte 0x4 0.--3. 1. "MSK,This is the masked status/clear for config errors" line.long 0x8 "CFG_ERR_EN_SET,Config Error Enable Set Register" hexmask.long.byte 0x8 0.--3. 1. "MSK,This is the mask enable set for config errors" line.long 0xC "CFG_ERR_EN_CLR,Config Error Interrupt Enabled Clear register" hexmask.long.byte 0xC 0.--3. 1. "MSK,This is the mask enable clear for config errors" rgroup.long 0x20++0xF line.long 0x0 "CFG_LOW_PRI,Shows which is the highest priority outstanding low priority interrupt" hexmask.long.word 0x0 16.--31. 1. "PLS,This is the highest priority outstanding low priority pulse interrupt" hexmask.long.word 0x0 0.--15. 1. "LVL,This is the highest priority outstanding low priority level interrupt" line.long 0x4 "CFG_HI_PRI,Shows which is the highest priority outstanding high priority interrupt" hexmask.long.word 0x4 16.--31. 1. "PLS,This is the highest priority outstanding high priority pulse interrupt" hexmask.long.word 0x4 0.--15. 1. "LVL,This is the highest priority outstanding high priority level interrupt" line.long 0x8 "CFG_LOW,Shows which groups have oustanding low priority interrupts" hexmask.long 0x8 0.--31. 1. "STS,This is the raw status for config errors" line.long 0xC "CFG_HI,Shows which groups have oustanding high priority interrupts" hexmask.long 0xC 0.--31. 1. "STS,This is the raw status for config errors" rgroup.long 0x30++0x3 line.long 0x0 "CFG_EOI,End of Interrupt Register" hexmask.long.word 0x0 0.--10. 1. "KEY,This is the interrupt being serviced" rgroup.long 0x40++0x3 line.long 0x0 "CFG_PIN_CTRL,This register controls the error_pin_n output" hexmask.long.byte 0x0 4.--7. 1. "PWM_EN,PWM enable" hexmask.long.byte 0x0 0.--3. 1. "KEY,Pin Control Key" rgroup.long 0x44++0x7 line.long 0x0 "CFG_PIN_STS,This register reflects the status of the error_pin_n output" bitfld.long 0x0 0. "VAL,Value of the error_pin_n" "0,1" line.long 0x4 "CFG_PIN_CNTR,This register shows the current value of the error pin counter" hexmask.long.tbyte 0x4 0.--23. 1. "COUNT,Current Counter Value" rgroup.long 0x4C++0x3 line.long 0x0 "CFG_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error Counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value" rgroup.long 0x50++0x3 line.long 0x0 "CFG_PWMH_PIN_CNTR,This register shows the current value of the error pin PWM high counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Current Counter Value" rgroup.long 0x54++0x3 line.long 0x0 "CFG_PWMH_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error PWM High Counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value" rgroup.long 0x58++0x3 line.long 0x0 "CFG_PWML_PIN_CNTR,This register shows the current value of the error pin PWM low counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Current Counter Value" rgroup.long 0x5C++0x3 line.long 0x0 "CFG_PWML_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error PWM Low Counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value" tree.end tree "WKUP_GPIO0 (WKUP_GPIO0)" base ad:0x42110000 rgroup.long 0x0++0x7 line.long 0x0 "MEM_pid,GPIO Periperal ID Register" bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code" bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code" line.long 0x4 "MEM_PCR,Peripheral Control Register" bitfld.long 0x4 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode." "0,1" bitfld.long 0x4 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_BINTEN,Bit Interrupt Enable Register" hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable. 0 = disable 1 = enable." rgroup.long 0x10++0xF line.long 0x0 "MEM_DIR01,Direction Register" hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits 0 = output 1 = input." hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits 0 = output 1 = input." line.long 0x4 "MEM_OUT_DATA01,Output Drive State Register" hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x8 "MEM_SET_DATA01,Set Output Drive State Register" hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits. Reading it returns the output drive state." hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits. Reading it returns the output drive state." line.long 0xC "MEM_CLR_DATA01,Clear Output Drive State Register" hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x20++0x3 line.long 0x0 "MEM_IN_DATA01,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits." rgroup.long 0x24++0x23 line.long 0x0 "MEM_SET_RIS_TRIG01,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits." line.long 0x4 "MEM_CLR_RIS_TRIG01,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits." line.long 0x8 "MEM_SET_FAL_TRIG01,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits." line.long 0xC "MEM_CLR_FAL_TRIG01,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits." line.long 0x10 "MEM_INTSTAT01,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR23,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA23,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA23,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA23,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x48++0x3 line.long 0x0 "MEM_IN_DATA23,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits." rgroup.long 0x4C++0x23 line.long 0x0 "MEM_SET_RIS_TRIG23,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits." line.long 0x4 "MEM_CLR_RIS_TRIG23,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits." line.long 0x8 "MEM_SET_FAL_TRIG23,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits." line.long 0xC "MEM_CLR_FAL_TRIG23,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits." line.long 0x10 "MEM_INTSTAT23,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR45,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA45,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA45,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA45,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x70++0x3 line.long 0x0 "MEM_IN_DATA45,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits." rgroup.long 0x74++0x23 line.long 0x0 "MEM_SET_RIS_TRIG45,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits." line.long 0x4 "MEM_CLR_RIS_TRIG45,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits." line.long 0x8 "MEM_SET_FAL_TRIG45,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits." line.long 0xC "MEM_CLR_FAL_TRIG45,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits." line.long 0x10 "MEM_INTSTAT45,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR67,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA67,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA67,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA67,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x98++0x3 line.long 0x0 "MEM_IN_DATA67,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits." rgroup.long 0x9C++0x23 line.long 0x0 "MEM_SET_RIS_TRIG67,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits." line.long 0x4 "MEM_CLR_RIS_TRIG67,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits." line.long 0x8 "MEM_SET_FAL_TRIG67,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits." line.long 0xC "MEM_CLR_FAL_TRIG67,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits." line.long 0x10 "MEM_INTSTAT67,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR8,Direction Register" hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA8,Output Drive State Register" hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA8,Set Output Drive State Register" hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA8,Clear Output Drive State Register" hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0xC0++0x3 line.long 0x0 "MEM_IN_DATA8,Bank Status Register" hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits." rgroup.long 0xC4++0x13 line.long 0x0 "MEM_SET_RIS_TRIG8,Set Rising Edge Detection Register" hexmask.long.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits." line.long 0x4 "MEM_CLR_RIS_TRIG8,Clear Rising Edge Detection Register" hexmask.long.word 0x4 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits." line.long 0x8 "MEM_SET_FAL_TRIG8,Set Falling Edge Detection Register" hexmask.long.word 0x8 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits." line.long 0xC "MEM_CLR_FAL_TRIG8,Clear Falling Edge Detection Register" hexmask.long.word 0xC 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits." line.long 0x10 "MEM_INTSTAT8,Bank Interrupt Status Register" hexmask.long.word 0x10 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." tree.end tree "WKUP_GPIO1 (WKUP_GPIO1)" base ad:0x42100000 rgroup.long 0x0++0x7 line.long 0x0 "MEM_pid,GPIO Periperal ID Register" bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code" bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code" line.long 0x4 "MEM_PCR,Peripheral Control Register" bitfld.long 0x4 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode." "0,1" bitfld.long 0x4 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_BINTEN,Bit Interrupt Enable Register" hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable. 0 = disable 1 = enable." rgroup.long 0x10++0xF line.long 0x0 "MEM_DIR01,Direction Register" hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits 0 = output 1 = input." hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits 0 = output 1 = input." line.long 0x4 "MEM_OUT_DATA01,Output Drive State Register" hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x8 "MEM_SET_DATA01,Set Output Drive State Register" hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits. Reading it returns the output drive state." hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits. Reading it returns the output drive state." line.long 0xC "MEM_CLR_DATA01,Clear Output Drive State Register" hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x20++0x3 line.long 0x0 "MEM_IN_DATA01,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits." rgroup.long 0x24++0x23 line.long 0x0 "MEM_SET_RIS_TRIG01,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits." line.long 0x4 "MEM_CLR_RIS_TRIG01,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits." line.long 0x8 "MEM_SET_FAL_TRIG01,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits." line.long 0xC "MEM_CLR_FAL_TRIG01,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits." line.long 0x10 "MEM_INTSTAT01,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR23,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA23,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA23,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA23,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x48++0x3 line.long 0x0 "MEM_IN_DATA23,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits." rgroup.long 0x4C++0x23 line.long 0x0 "MEM_SET_RIS_TRIG23,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits." line.long 0x4 "MEM_CLR_RIS_TRIG23,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits." line.long 0x8 "MEM_SET_FAL_TRIG23,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits." line.long 0xC "MEM_CLR_FAL_TRIG23,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits." line.long 0x10 "MEM_INTSTAT23,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR45,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA45,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA45,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA45,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x70++0x3 line.long 0x0 "MEM_IN_DATA45,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits." rgroup.long 0x74++0x23 line.long 0x0 "MEM_SET_RIS_TRIG45,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits." line.long 0x4 "MEM_CLR_RIS_TRIG45,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits." line.long 0x8 "MEM_SET_FAL_TRIG45,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits." line.long 0xC "MEM_CLR_FAL_TRIG45,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits." line.long 0x10 "MEM_INTSTAT45,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR67,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA67,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA67,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA67,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x98++0x3 line.long 0x0 "MEM_IN_DATA67,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits." rgroup.long 0x9C++0x23 line.long 0x0 "MEM_SET_RIS_TRIG67,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits." line.long 0x4 "MEM_CLR_RIS_TRIG67,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits." line.long 0x8 "MEM_SET_FAL_TRIG67,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits." line.long 0xC "MEM_CLR_FAL_TRIG67,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits." line.long 0x10 "MEM_INTSTAT67,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR8,Direction Register" hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA8,Output Drive State Register" hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA8,Set Output Drive State Register" hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA8,Clear Output Drive State Register" hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0xC0++0x3 line.long 0x0 "MEM_IN_DATA8,Bank Status Register" hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits." rgroup.long 0xC4++0x13 line.long 0x0 "MEM_SET_RIS_TRIG8,Set Rising Edge Detection Register" hexmask.long.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits." line.long 0x4 "MEM_CLR_RIS_TRIG8,Clear Rising Edge Detection Register" hexmask.long.word 0x4 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits." line.long 0x8 "MEM_SET_FAL_TRIG8,Set Falling Edge Detection Register" hexmask.long.word 0x8 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits." line.long 0xC "MEM_CLR_FAL_TRIG8,Clear Falling Edge Detection Register" hexmask.long.word 0xC 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits." line.long 0x10 "MEM_INTSTAT8,Bank Interrupt Status Register" hexmask.long.word 0x10 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." tree.end tree "WKUP_I2C0_CFG (WKUP_I2C0_CFG)" base ad:0x42120000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "CFG_I2C_REVNB_HI,Revision Number register (High)" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" rgroup.long 0x10++0x3 line.long 0x0 "CFG_I2C_SYSC,System Configuration register" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" bitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" newline bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "CFG_I2C_EOI,End Of Interrupt number specification" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" rgroup.long 0x24++0x2B line.long 0x0 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x0 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x0 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x0 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x0 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x0 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x0 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x0 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x0 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x4 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ enabled status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ enabled status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x8 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x8 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x8 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x8 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x8 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x8 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x8 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x8 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x8 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x8 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x8 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x8 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x8 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0xC "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0xC 11. "ROVR,Receive overrun enable clear" "0,1" newline bitfld.long 0xC 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x10 "CFG_I2C_WE,I2C wakeup enable vector (legacy)." bitfld.long 0x10 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x10 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x10 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x10 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x10 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x10 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x10 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x10 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x10 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x10 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x10 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x14 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.long 0x14 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x18 "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.long 0x18 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x1C "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.long 0x1C 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x20 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.long 0x20 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x24 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.long 0x24 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x24 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x24 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x24 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x24 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x24 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x24 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x24 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x24 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x24 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x24 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x24 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x28 "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" rgroup.long 0x84++0x7 line.long 0x0 "CFG_I2C_IE,I2C interrupt enable vector (legacy)." bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x4 "CFG_I2C_STAT,I2C interrupt status vector (legacy)." bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "CFG_I2C_SYSS,System Status register" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" rgroup.long 0x94++0xB line.long 0x0 "CFG_I2C_BUF,Buffer Configuration register" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "CFG_I2C_CNT,Data counter register" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "CFG_I2C_DATA,Data access register" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" rgroup.long 0xA4++0x1B line.long 0x0 "CFG_I2C_CON,I2C configuration register." bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" newline bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "CFG_I2C_OA,Own address register" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "CFG_I2C_SA,Slave address register" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "CFG_I2C_PSC,I2C Clock Prescaler Register" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 0xFF: Divide by 256" line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register." hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register." hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register." bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" newline bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "CFG_I2C_BUFSTAT,I2C Buffer Status Register." bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" rgroup.long 0xC4++0xB line.long 0x0 "CFG_I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "CFG_I2C_OA2,I2C Own Address 2" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "CFG_I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "CFG_I2C_ACTOA,I2C Active Own Address Register." bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" rgroup.long 0xD4++0x3 line.long 0x0 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree "WKUP_UART0 (WKUP_UART0)" base ad:0x42300000 rgroup.long 0x0++0x3 line.long 0x0 "MEM_DLL,Divisor Latches Low Register" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" rgroup.long 0x0++0x7 line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" line.long 0x4 "MEM_DLH,Divisor Latches High Register" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.." bitfld.long 0x0 6.--7. "NOT_USED2," "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "NOT_USED1," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT," "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x4++0x7 line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "CTS_IT," "0,1" newline bitfld.long 0x0 6. "RTS_IT," "0,1" newline bitfld.long 0x0 5. "XOFF_IT," "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE," "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT," "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" line.long 0x4 "MEM_EFR,Enhanced Feature Register" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" rgroup.long 0x8++0x3 line.long 0x0 "MEM_FCR,Notes:" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered. If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of.." "0,1,2,3" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR," "0,1" newline bitfld.long 0x0 0. "FIFO_EN," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT," "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT," "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT," "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT," "0,1" newline bitfld.long 0x0 3. "RX_OE_IT," "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT," "0,1" newline bitfld.long 0x0 1. "THR_IT," "0,1" newline bitfld.long 0x0 0. "RHR_IT," "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE," newline bitfld.long 0x0 0. "IT_PENDING," "0,1" rgroup.long 0xC++0x7 line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "DIV_EN," "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1," "0,1" newline bitfld.long 0x0 3. "PARITY_EN," "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3" line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline rbitfld.long 0x4 7. "RESERVED," "0,1" newline bitfld.long 0x4 6. "TCR_TLR," "0,1" newline bitfld.long 0x4 5. "XON_EN," "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN," "0,1" newline bitfld.long 0x4 3. "CD_STS_CH," "0,1" newline bitfld.long 0x4 2. "RI_STS_CH," "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1" newline bitfld.long 0x4 0. "DTR," "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_CIR," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "RESERVED," "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_IRDA," bitfld.long 0x0 7. "THR_EMPTY," "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL," "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE," "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG," "0,1" newline bitfld.long 0x0 3. "ABORT," "0,1" newline bitfld.long 0x0 2. "CRC," "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_UART," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "RX_FIFO_STS," "0,1" newline bitfld.long 0x0 6. "TX_SR_E," "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E," "0,1" newline bitfld.long 0x0 4. "RX_BI," "0,1" newline bitfld.long 0x0 3. "RX_FE," "0,1" newline bitfld.long 0x0 2. "RX_PE," "0,1" newline bitfld.long 0x0 1. "RX_OE," "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E," "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS," "0,1" newline bitfld.long 0x0 0. "CTS_STS," "0,1" rgroup.long 0x18++0x3 line.long 0x0 "MEM_TCR,Transmission Control Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" rgroup.long 0x18++0x7 line.long 0x0 "MEM_XOFF1,XOFF1 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" rgroup.long 0x1C++0x3 line.long 0x0 "MEM_TLR,Trigger Level Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" rgroup.long 0x1C++0xB line.long 0x0 "MEM_XOFF2,XOFF2 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP," "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7" line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is :" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_SFLSR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR," "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR," "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT," "0,1" newline bitfld.long 0x0 1. "CRC_ERROR," "0,1" newline bitfld.long 0x0 0. "RESERVED0," "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_TXFLL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" rgroup.long 0x2C++0x7 line.long 0x0 "MEM_TXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "MEM_RXFLL,IrDA modes only." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "MEM_SFREGL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" rgroup.long 0x34++0x3 line.long 0x0 "MEM_RXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "MEM_SFREGH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED," newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" rgroup.long 0x38++0x3 line.long 0x0 "MEM_BLR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED," rgroup.long 0x38++0x3 line.long 0x0 "MEM_UASR,UART Autobauding Status Register" bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." rgroup.long 0x3C++0xF line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX," "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline bitfld.long 0x4 7. "RX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1," "0,1" newline bitfld.long 0x4 5. "DSR_IT," "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT," "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL," "0,1" line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x8 3.--7. 1. "RESERVED," newline bitfld.long 0x8 2. "DMA_COUNTER_RST," "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL," "0,1" line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED," newline hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." rgroup.long 0x54++0x3 line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "MEM_SYSS," hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED," newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" rgroup.long 0x5C++0x7 line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED," newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN," "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT," "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY," "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY," "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY," "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY," "0,1" line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.." rgroup.long 0x64++0x7 line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL," line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24," newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL," rgroup.long 0x6C++0xB line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED," newline bitfld.long 0x0 2. "RHR_IT_DIS," "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1," newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED," newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1" line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED," line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED," rgroup.long 0x80++0x23 line.long 0x0 "MEM_MDR3,Mode definition register 3." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2," newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1" line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "MEM_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1," newline rbitfld.long 0x8 7. "RESERVED," "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7" line.long 0xC "MEM_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1," newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "MEM_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1," newline rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "MEM_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1," newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "MEM_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" rgroup.long 0xA4++0xF line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED," newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" line.long 0x4 "MEM_MAR,Multidrop Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "MEM_MMR,Multidrop Mask Register" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "WKUP_vdc_infra_vbusp_32b_src_safeg0_CFG (WKUP_vdc_infra_vbusp_32b_src_safeg0_CFG)" base ad:0x42900000 rgroup.long 0x0++0xB line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard" rgroup.long 0xC++0xF line.long 0x0 "CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush All other values - Normal." line.long 0x8 "CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon." line.long 0xC "CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer" rgroup.long 0x20++0x17 line.long 0x0 "CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3" line.long 0x14 "CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1" bitfld.long 0x0 1. "TYP,Type Indicator" "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1" line.long 0x4 "CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator" hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator" line.long 0x8 "CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt" hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt" line.long 0xC "CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address" line.long 0x10 "CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address" tree.end tree.end AUTOINDENT.OFF